A6812: DABiC-IV 20-Bit Serial-Input Latched Source Drivers with Active Pull-Downs

A6812
DABiC-IV 20-Bit Serial-Input Latched Source Driver
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: November 1, 2010
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A6812
DABiC-IV 20-Bit Serial-Input
Latched Source Driver
Features and Benefits
Description
▪ Controlled output slew rate
▪ High-speed data storage
▪ 60 V minimum output break down
▪ High data-input rate
▪ PNP active pull-downs
▪ Low output-saturation voltages
▪ Low-power CMOS logic and latches
▪ Improved replacements for TL5812x, UCN5812x, and
UCQ5812x
The A6812 device combines a 20-bit CMOS shift register,
accompanying data latches and control circuitry with bipolar
sourcing outputs ,and PNP active pull-downs. Designed
primarily to drive vacuum-fluorescent displays, the 60 V and
-40 mA output ratings also allow these devices to be used in
many other peripheral power driver applications. The A6812
features an increased data-input rate (compared with the older
UCN/UCQ5812-F) and a controlled output slew rate.
The CMOS shift register and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, they operate to at least 10 MHz.
A CMOS serial data output permits cascaded connections in
applications requiring additional drive lines. Similar devices
are available as the A6810 (10-bit) and A6818 (32-bit).
Package:
The A6812 output source drivers are NPN Darlingtons,
capable of sourcing up to 40 mA. The controlled output slew
rate reduces electromagnetic noise, which is an important
consideration in systems that include telecommunications
and/or microprocessors and to meet government emissions
28-pin SOICW
(Package LW)
28-pin PLCC
(EP package)
Continued on the next page…
Not to scale
Functional Block Diagram
26182.126G
DABiC-IV 20-Bit Serial-Input
Latched Source Driver
A6812
Description (continued)
regulations. For inter-digit blanking, all output drivers can be
disabled and all sink drivers turned on with a BLANKING input
high. The PNP active pull-downs sink at least 2.5 mA.
Three temperature ranges are available for optimum performance in
commercial (suffix S-), industrial (suffix E-), or automotive (suffix
K-) applications. Package styles are provided for surface-mount
SOIC (suffix -LW), or minimum-area surface-mount PLCC (suffix
-EP). Copper lead frames, low logic-power dissipation, and low
output-saturation voltages allow these drivers to source 25 mA
from all outputs continuously to more than 43°C (suffix -LW) or
61°C (suffix -EP).
Each package is available in a lead (Pb) free version, with 100%
matte tin leadframe plating.
Selection Guide
Part Number
A6812EEPTR
Pb-free
–
Package
800 pieces/13-in. reel
PLCC
Yes
1000 pieces/13-in. reel
SOIC-W
Yes
1000 pieces/13-in. reel
SOIC-W
800 pieces/13-in. reel
PLCC
1000 pieces/13-in. reel
SOIC-W
A6812EEPTR-T
Yes
A6812ELWTR-T
A6812KLWTR-T
A6812SEPTR
Packing
–
A6812SEPTR-T
Yes
A6812SLWTR-T
Yes
Ambient Temperature, TA
(°C)
–40 to 85
–40 to 125
–20 to 85
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
DABiC-IV 20-Bit Serial-Input
Latched Source Driver
A6812
Absolute Maximum Ratings*
Characteristic
Symbol
Notes
Rating
Units
Logic Supply Voltage
VDD
7
V
Driver Supply Voltage
VBB
60
V
Input Voltage Range
VIN
–0.3 to VDD + 0.3
V
Continuous Output Current Range
IOUT
–40 to 15
mA
Range E
–40 to 85
ºC
Range K
–40 to 125
ºC
Range S
–20 to 85
ºC
TJ(max)
150
ºC
Tstg
–65 to 125
ºC
Operating Ambient Temperature
TA
Maximum Junction Temperature
Storage Temperature
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
*Caution: These CMOS devices have input static protection (Class 2) but are still susceptible to damage if exposed to extremely high
static electrical charges.
2.5
2.0
SU
FF
IX
1.5
'E
P'
,R
SU
FF
QJ
IX
A=
'LW
68
oC
', R
/W
QJ
A =
80o
C/
W
1.0
0.5
0
25
50
75
100
125
AMBIENT TEMPERATURE IN oC
150
Dwg. GP-024-2
Thermal Characteristics
Characteristic
Package Thermal Resistance
Symbol
RθJA
Test Conditions*
Value Units
Package EP, 1-layer PCB with solder limited to mounting pads
68
ºC/W
Package LW, 1-layer PCB with solder limited to mounting pads
80
ºC/W
*Additional thermal information available on the Allegro website
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
DABiC-IV 20-Bit Serial-Input
Latched Source Driver
A6812
22
21
9
20
11
19
OUT 20
3
26
OUT 1
OUT 19
4
25
OUT 2
OUT 18
5
24
OUT 3
OUT 17
6
OUT 16
7
OUT 15
8
23
OUT 4
22
OUT 5
21
OUT 6
OUT 14
9
20
OUT 7
OUT 13
10
19
OUT 8
OUT 12
11
18
OUT 9
ST
14
15
16
17
18
CLOCK
STROBE
OUT10
OUT9
14
GROUND
GROUND
13
13
12
BLANKING
OUT 11
BLANKING
12
OUT 8
SERIAL
DATA IN
OUT11
CLK
10
27
VDD
LATCHES
OUT 1
26
23
LATCHES
REGISTER
8
REGISTER
LATCHES
7
2
SERIAL
DATA OUT
VBB
REGISTER
SERIAL
DATA IN
27
24
6
OUT12
OUT 2
LOGIC
SUPPLY
1
LATCHES
LOGIC
SUPPLY
V DD 28
25
5
28
LOAD
SUPPLY
REGISTER
LOAD
SUPPLY
VBB
OUT18
LW Package
1
SERIAL
DATA OUT
2
OUT20
3
4
OUT19
EP Package
BLNK
17
OUT 10
ST
28
16
STROBE
CLK
27
15
CLOCK
Dwg. PP-029-7
Dwg. PP-059-1
TYPICAL INPUT CIRCUIT
TYPICAL OUTPUT DRIVER
V DD
V
IN
BB
OUTN
Dwg. EP-021-19
Dwg. EP-010-5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
DABiC-IV 20-Bit Serial-Input
Latched Source Driver
A6812
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
IN
Serial
Data Strobe
Output Input
Latch Contents
I1
I2
I3
...
IN-1
Output Contents
IN Blanklng
I1 I2 I3 ... IN-1
H
H
R1 R2 ...
RN-2 RN-1
RN-1
L
L
R1 R2 ...
RN-2 RN-1
RN-1
X
R1 R2 R3 ...
RN-1 RN
RN
X
X
X
L
R1 R2 R3 ...
RN-1 RN
PN
H
P1 P2 P3 ...
PN-1 PN
L
P1 P2 P3 ... PN-1 PN
X
X
H
L
X
X
...
P1 P2 P3 ...
L = Low Logic Level
X
PN-1 PN
H = High Logic Level
X = Irrelevant
X
P = Present State
X
...
X
L
L
... L
L
R = Previous State
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
DABiC-IV 20-Bit Serial-Input
Latched Source Driver
A6812
ELECTRICAL CHARACTERISTICS at TA = +25°C (A6812S-) or over operating temperature range (A6812E- or
A6812K-), VBB = 60 V; unless otherwise noted
Characteristic
Output Leakage Current
Output Voltage
Symbol
ICEX
Test Conditions
VOUT = 0 V
Limits @ VDD = 3.3 V
Limits @ VDD = 5 V
Mln.
Typ.
Max.
Min.
Typ.
Max.
Units
—
<-0.1
-15
—
<-0.1
-15
μA
57.5
58.3
—
57.5
58.3
—
V
VOUT(1)
IOUT = -25 mA
VOUT(0)
IOUT = 1 mA
—
1.0
1.5
—
1.0
1.5
V
Output Pull-Down Current
IOUT(0)
VOUT = 5 V to VBB
2.5
5.0
—
2.5
5.0
—
mA
Input Voltage
VIN(1)
2.2
—
—
3.3
—
—
V
VIN(0)
—
—
1.1
—
—
1.7
V
Input Current
Input Clamp Voltage
Serial Data Output Voltage
Maximum Clock Frequency
Logic Supply Current
IIN(1)
VIN = VDD
—
<0.01
1.0
—
<0.01
1.0
μA
IIN(0)
VIN = 0 V
—
<-0.01
-1.0
—
<-0.01
-1.0
μA
IIN = -200 μA
—
-0.8
-1.5
—
-0.8
-1.5
V
VOUT(1)
IOUT = -200 μA
2.8
3.05
—
4.5
4.75
—
V
VOUT(0)
IOUT = 200 μA
—
0.15
0.3
—
0.15
0.3
V
10*
—
—
10*
—
—
MHz
VIK
fc
IDD(1)
All Outputs High
—
0.25
0.75
—
0.3
1.0
mA
IDD(0)
All Outputs Low
—
0.25
0.75
—
0.3
1.0
mA
IBB(1)
All Outputs High, No Load
—
3.0
6.0
—
3.0
6.0
mA
IBB(0)
All Outputs Low
—
0.2
20
—
0.2
20
μA
tdis(BQ)
CL = 30 pF, 50% to 50%
—
0.7
2.0
—
0.7
2.0
μs
ten(BQ)
CL = 30 pF, 50% to 50%
—
1.8
3.0
—
1.8
3.0
μs
tp(STH-QL)
RL = 2.3 kΩ, CL 30 pF
—
0.7
2.0
—
0.7
2.0
μs
tp(STH-QH)
RL = 2.3 kΩ, CL 30 pF
—
1.8
3.0
—
1.8
3.0
μs
Output Fall Time
tf
RL = 2.3 kΩ, CL 30 pF
2.4
—
12
2.4
—
12
μs
Output Rise Time
tr
RL = 2.3 kΩ, CL 30 pF
2.4
—
12
2.4
—
12
μs
Output Slew Rate
dV/dt
RL = 2.3 kΩ, CL 30 pF
4.0
—
20
4.0
—
20
V/μs
IOUT = ±200 μA
—
50
—
—
50
—
ns
Load Supply Current
Blanking-to-Output Delay
Strobe-to-Output Delay
Clock-to-Serial Data Out Delay tp(CH-SQX)
Negative current is defined as coming out of (sourcing) the specified device terminal.
Typical data is is for design information only and is at TA = +25°C.
* Operation at a clock frequency greater than the specified minimum is possible but not warranteed.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
DABiC-IV 20-Bit Serial-Input
Latched Source Driver
A6812
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
50%
CLOCK
A
SERIAL
DATA IN
B
DATA
50%
t p(CH-SQX)
SERIAL
DATA OUT
DATA
50%
D
50%
STROBE
BLANKING
E
LOW = ALL OUTPUTS ENABLED
t p(STH-QH)
t p(STH-QL)
90%
DATA
OUT N
10%
Dwg. WP-029
HIGH = ALL OUTPUTS BLANKED (DISABLED)
BLANKING
50%
t dis(BQ)
tr
t en(BQ)
OUT N
10%
DATA
tf
90%
50%
Dwg. WP-030A
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ........................................ 25 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ............................................. 25 ns
C. Clock Pulse Width, tw(CH) .............................................. 50 ns
D. Time Between Clock Activation and Strobe, tsu(C) ...... 100 ns
E. Strobe Pulse Width, tw(STH) ........................................... 50 ns
NOTE – Timing is representative of a 10 MHz clock. Higher
speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum
clock frequency.
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long
as the STROBE is held high. Applications where the latches are
bypassed (STROBE tied high) will require that the BLANKING
input be high during serial data entry.
When the BLANKING input is high, the output source drivers are disabled (OFF); the pnp active pull-down sink drivers are
ON. The information stored in the latches is not affected by the
BLANKING input. With the BLANKING input low, the outputs
are controlled by the state of their respective latches.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
DABiC-IV 20-Bit Serial-Input
Latched Source Driver
A6812
EP Package, 28-Pin PLCC
12.45±0.13
11.51±0.08
2
1
0.51
28
A
12.45±0.13
5.21±0.36
11.51±0.08
5.21±0.36
0.51 MIN
0.74±0.08
+0.20
4.37 –0.18
28X
0.10 C
SEATING
PLANE
C
0.43±0.10
1.27
5.21±0.36
5.21±0.36
For Reference Only
(reference JEDEC MS-018 AB)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
DABiC-IV 20-Bit Serial-Input
Latched Source Driver
A6812
LW Package, 28-Pin SOICW
17.90±0.20
4° ±4
28
+0.07
0.27 –0.06
28
2.20
9.60
10.30±0.33
7.50±0.10
A
+0.44
0.84 –0.43
1
2
1
2
0.65
0.25
28X
SEATING
PLANE
0.1 C
0.41 ±0.10
1.27
C
1.27
B PCB Layout Reference View
SEATING PLANE
GAUGE PLANE
2.65 MAX
0.20 ±0.10
For Reference Only
(Reference JEDEC MS-013 AE)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Reference pad layout (reference IPC SOIC127P1030X265-28M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Copyright ©2000-2009, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
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