A6821: DABiC-5 8-Bit Serial Input Latched Sink Drivers

A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: May 2, 2011
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Features and Benefits
Description
▪ 3.3 to 5 V logic supply range
▪ Power on reset (POR)
▪ To 10 MHz data input rate
▪ CMOS, TTL compatible
▪ –40°C operation available
▪ Schmitt trigger inputs for improved noise immunity
▪ Low-power CMOS logic and latches
▪ High-voltage current-sink outputs
▪ Internal pull-up/pull down resistors
A merged combination of bipolar and MOS technology
gives these devices an interface flexibility beyond the reach
of standard logic buffers and power driver arrays. Typical
applications include driving multiplexed LED displays or
incandescent lamps.
The A6821 has an eight-bit CMOS shift register and CMOS
control circuitry, eight CMOS data latches, and eight bipolar
current-sinking Darlington output drivers.
The CMOS inputs are compatible with standard CMOS logic
levels. TTL circuits may require the use of appropriate pull-up
resistors. By using the serial data output, the drivers can be
cascaded for interface applications requiring additional drive
lines.
Applications:
▪ Multiplexed LED displays
▪ Incandescent lamps
Packages:
Package A 16-pin DIP
Package LW 16-pin SOICW
The A6821SA is furnished in a standard 16-pin plastic DIP.
The A6821EA is a 16-pin plastic DIP, capable of operation
from -40°C to 85°C. The A6821SLW is a 16-lead wide-body
SOIC, for surface-mount applications. These devices are lead
(Pb) free, with 100% matte tin plated leadframes.
Not to scale
Functional Block Diagram
C LOC K
S E R IAL
DAT A IN
LOG IC
G R OUND
LOG IC
S UP P LY
V DD
S E R IAL
DAT A OUT
S E R IAL-P AR ALLE L S HIF T R E G IS T E R
S T R OB E
LAT C HE S
OUT P UT E NAB LE
(AC T IV E LOW)
MOS
B IP OLAR
P OWE R
G R OUND
S UB
OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8
26185.112F
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Selection Guide
Part Number
A6821SA-T
A6821SLWTR-T
Package
Ambient (ºC)
16-pin DIP
16-pin wide body SOIC
–20 to 85
–20 to 85
Packing
25 pieces per tube
1000 pieces per reel
Absolute Maximum Ratings
Characteristic
Logic Supply Voltage
Input Voltage Range
Symbol
Notes
VDD
VIN
Caution: CMOS devices have input-static
protection, but are susceptible to damage when
exposed to extremely high static-electrical
charges.
Rating
Unit
7
V
–0.3 to VDD + 0.3
V
Output Voltage
VOUT
50
V
Continuous Output Current
IOUT
500
mA
A package
2.1
W
LW package
1.5
W
Range E
–40 to 85
ºC
Range S
–20 to 85
ºC
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Power Dissipation
PD
Operating Ambient Temperature
TA
Maximum Junction Temperature
Storage Temperature
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, logic supply operating voltage Vdd = 3.0 V to 5.5 V
Vdd = 3.3 V
Characteristic
Min.
Typ.
Typ.
Max.
Units
VOUT = 50 V
–
–
10
–
–
10
μA
IOUT = 100 mA
–
–
1.1
–
–
1.1
V
IOUT = 200 mA
–
–
1.3
–
–
1.3
V
IOUT = 350 mA
–
–
1.6
–
–
1.6
V
VIN(1)
2.2
–
–
3.3
–
–
V
VIN(0)
–
–
1.1
–
–
1.7
V
RIN
50
–
–
50
–
–
kΩ
V
Symbol
Output Leakage Current
ICEX
Collector–Emitter Saturation
Voltage
VCE(SAT)
Input Voltage
Input Resistance
Serial Data Output Voltage
Test Conditions
IOUT = –200 μA
2.8
3.05
–
4.5
4.75
–
VOUT(0)
IOUT = 200 μA
–
0.15
0.3
–
0.15
0.3
V
10
–
–
10
–
–
MHz
fc
IDD(1)
One output on, OE = L, ST = H
–
–
2.0
–
–
2.0
mA
IDD(0)
All outputs off, OE = H, ST = H,
P1 through P8 = L
–
–
100
–
–
100
μA
tdis(BQ)
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
ten(BQ)
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
tp(STH-QL)
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
tp(STH-QH)
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
tf
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
tr
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
IOUT = ±200 μA
–
50
–
–
50
–
ns
Logic Supply Current
Output Enable-to-Output Delay
Output Fall Time
Output Rise Time
Clock-to-Serial Data Out Delay
Max. Min.
VOUT(1)
Maximum Clock Frequency2
Strobe-to-Output Delay
Vdd = 5 V
tp(CH-SQX)
1Positive
(negative) current is defined as conventional current going into (coming out of) the specified device pin.
2Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
Truth Table
Serial
Data Clock
Input Input
Shift Register Contents
I8
Serial
Data
Output
R1 R2 ...
R7
R7
R1 R2 ...
R7
R7
R1 R2 R3 ...
R8
R8
X
X
X
P8
P8
I1
I2
H
H
L
L
X
X
I3
X
...
...
P1 P2 P3 ...
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
Latch Contents
Strobe
Input
I1
I2
Output Contents
I1 I2 I3 ... I8
...
I8
L
R1 R2 R3 ...
R8
H
P1 P2 P3 ...
P8
L
P 1 P2 P3 ... P8
X
X
H
H
X
I3
Output
Enable
Input
X
...
H H ... H
R = Previous State
OE = Output Enable
ST = Strobe
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Timing Requirements and Specifications
(Logic Levels are VDD and Ground)
C
50%
CLOCK
A
SERIAL
DATA IN
B
DATA
50%
t p(CH-SQX)
SERIAL
DATA OUT
DATA
50%
D
E
50%
STROBE
OUTPUT ENABLE
LOW = ALL OUTP UTS E NABLE D
tp(STH-QH)
tp(STH-QL)
90%
DATA
OUT N
10%
HIGH = ALL OUTP UTS BLANKE D (DIS ABLE D)
OUTPUT ENABLE
50%
t en(BQ)
tr
tf
t dis(BQ)
OUT N
90%
10%
Key
Description
A
Data Active Time Before Clock Pulse (Data Set-Up Time)
B
DATA
50%
Symbol
tsu(D)
Time (ns)
Data Active Time After Clock Pulse (Data Hold Time)
th(D)
25
C
Clock Pulse Width
tw(CH)
50
D
Time Between Clock Activation and Strobe
tsu(C)
100
E
Strobe Pulse Width
tw(STH)
50
NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be
attainable; operation at high temperatures will reduce the specified maximum clock frequency.
Powering-on with the inputs in the low state ensures that the registers and
latches power-on in the low state (POR).
Serial Data present at the input is transferred to the shift register on the logical
0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK
pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the
CLOCK input waveform.
25
Information present at any register is transferred to the respective latch
when the STROBE is high (serial-to-parallel conversion). The latches will
continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that
the OUTPUT ENABLE input be high during serial data entry.
When the OUTPUT ENABLE input is high, all of the output buffers are
disabled (OFF). The information stored in the latches or shift register is not
affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE
input low, the outputs are controlled by the state of their respective latches.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Maximum Allowable Duty Cycle, IOUT = 200 mA, VDD = 5 V
Number of
Outputs ON
A mbient T emperature
40 °C
50 °C
60 °C
25 °C
70 °C
A6821SA/A6821EA
8
7
6
5
4
3
2
1
90%
100%
100%
100%
100%
100%
100%
100%
79%
90%
100%
100%
100%
100%
100%
100%
72%
82%
96%
100%
100%
100%
100%
100%
65%
74%
86%
100%
100%
100%
100%
100%
57%
65%
76%
91%
100%
100%
100%
100%
67%
77%
90%
100%
100%
100%
100%
100%
59%
68%
79%
95%
100%
100%
100%
100%
54%
62%
72%
86%
100%
100%
100%
100%
49%
56%
65%
78%
98%
100%
100%
100%
43%
49%
57%
68%
86%
100%
100%
100%
A6821SLW
8
7
6
5
4
3
2
1
Terminal List Table
Name
Description
Pin
CLK
Clock
1
VDD
Serial Data In
2
Logic Ground*
3
Logic Supply
4
Serial Data Out
5
ST
Strobe
6
OE
Output Enable (active low)
7
SUB
Power Ground*
8
OUT8
Serial Data Output
9
OUT7
Serial Data Output
10
OUT6
Serial Data Output
11
OUT5
Serial Data Output
12
OUT4
Serial Data Output
13
OUT3
Serial Data Output
14
OUT2
Serial Data Output
15
OUT1
Serial Data Output
16
* There is an indeterminate resistance between logic ground and power ground.
For proper operation, these terminals must be externally connected together.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Package A
16-pin DIP
Package LW
16-pin Wide Body SOIC
16
OUT 1
2
15
OUT 2
LOG IC
G R OUND
3
14
OUT 3
OUT 4
LOG IC
S UP P LY
4
13
OUT 4
12
OUT 5
S E R IAL
DAT A OUT
5
12
OUT 5
ST
11
OUT 6
S T R OB E
6
ST
11
OUT 6
OE
10
OUT 7
OUT P UT
E NAB LE
7
OE
10
OUT 7
9
OUT 8
P OWE R
G R OUND
8
9
OUT 8
C LOC K
1
2
15
OUT 2
S E R IAL
DAT A IN
LOGIC
GROUND
3
14
OUT 3
LOGIC
SUPPLY
4
13
SERIAL
DATA OUT
5
STROBE
6
OUTPUT
ENABLE
7
POWER
GROUND
8
LATCHES
VDD
SHIFT REGISTER
SERIAL
DATA IN
CLK
SUB
Typical Input Circuits
C LK
V DD
LAT C HE S
OUT 1
1
S HIF T R E G IS TE R
16
CLOCK
S UB
Typical Output Driver
VDD
OUT
STROBE
OUTPUT
ENABLE
7.2 kΩ
3 kΩ
SUB
VDD
CLOCK
SERIAL
DATA IN
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Package A
16-pin DIP
19.05±0.25
16
+0.10
0.25 –0.05
+0.38
10.92 –0.25
+0.76
6.35 –0.25
7.62
A
1
2
For Reference Only
(reference JEDEC MS-001 BB)
Dimensions in inches, metric dimensions (mm) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
5.33 MAX
+0.51
3.30 –0.38
1.27 MIN
2.54
+0.25
1.52 –0.38
0.46 ±0.12
Package LW
16-pin Wide Body SOIC
10.30±0.20
4° ±4
16
1.27
0.65
16
+0.07
0.27 –0.06
10.30±0.33
7.50±0.10
9.50
A
+0.44
0.84 –0.43
2.25
1
2
1
0.25
16X
SEATING
PLANE
0.10 C
0.41 ±0.10
1.27
C
2
B
PCB Layout Reference View
SEATING PLANE
GAUGE PLANE
2.65 MAX
0.20 ±0.10
For Reference Only
Dimensions in millimeters
(reference JEDEC MS-013 AA)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B
Reference pad layout (reference IPC SOIC127P1030X265-16M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A6821
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Copyright ©2004-2010, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
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