A6833: DABiC-5 32-Bit Serial Input Latched Sink Drivers

A6833
DABiC-5 32-Bit Serial Input Latched Sink Drivers
Last Time Buy
This part is in production but has been determined to be
LAST TIME BUY. This classification indicates that the product is
obsolete and notice has been given. Sale of this device is currently
restricted to existing customer applications. The device should not be
purchased for new design applications because of obsolescence in the
near future. Samples are no longer available.
Date of status change: November 1, 2010
Deadline for receipt of LAST TIME BUY orders: April 30, 2011
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A6833
DABiC-5 32-Bit Serial Input Latched Sink Drivers
Features and Benefits
Description
▪ 3.3 to 5 V logic supply range
▪ To 10 MHz data input rate
▪ 30 V minimum output breakdown
▪ Darlington current-sink outputs
▪ Low-power CMOS logic and latches
▪ Schmitt trigger inputs for improved noise immunity
Designed to reduce logic supply current, chip size, and
system cost, the A6833 integrated circuit offers high-speed
operation for thermal printers. These devices can also be
used to drive multiplexed LED displays or incandescent
lamps within their 125 mA peak output current rating. The
combination of bipolar and MOS technologies gives the
A6833 smart power IC an interface flexibility beyond the
reach of standard buffers and power driver circuits.
Applications:
This 32-bit drivers have bipolar open-collector NPN Darlington outputs, a CMOS data latch for each of the drivers,
a 32-bit CMOS shift register, and CMOS control circuitry.
The high-speed CMOS shift registers and latches allow
operation with most microprocessor-based systems. Use of
these drivers with TTL may require input pull-up resistors to
ensure an input logic high. CMOS serial data outputs permit
cascading for applications requiring additional drive lines.
▪ Thermal printheads
▪ Multiplexed LED displays
▪ Incandescent lamps
40
41
42
43
1
44
2
3
4
7
39
8
38
9
37
The A6833 is supplied in a 44-lead plastic chip carrier (quad
pack), intended for surface mounting on solder lands with
0.050 in. (1.27 mm) centers. These devices are lead (Pb)
free, with 100% matte tin plated leadframes.
28
27
29
26
30
17
25
31
16
24
32
15
23
33
14
22
34
13
21
35
12
20
36
19
10
11
18
Not to scale
5
6
Package: 44-pin PLCC (suffix EP)
Functional Block Diagram
V DD
C LOC K
S E R IAL
DATA IN
S E R IAL DATA
OUT
32-B IT S HIF T R E G IS T E R
S T R OB E
LAT C HE S
OUT P UT
E NAB LE
LOG IC
G R OUND
MOS
B IP OLAR
S UB
OUT1
26185.116C
OUT 2 OUT3
OUT 30 OUT31 OUT32
P OWE R
G R OUND
A6833
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
Selection Guide
Part Number
A6833SEPTR-T
Packing
Package
450 pieces per reel
44-pin PLCC
Absolute Maximum Ratings
Characteristic
Symbol
Logic Supply Voltage
VDD
Input Voltage Range
VIN
Output Voltage
Continuous Output Current
Output Current Sink
Notes
Caution: CMOS devices have input-static
protection, but are susceptible to damage when
exposed to extremely high static-electrical
charges.
VOUT
IOUT
Each output
IOUT(sink)
Package Power Dissipation
PD
Derate linearly to 0 W at 150ºC
Operating Ambient Temperature
TA
Range S
Maximum Junction Temperature
Storage Temperature
Rating
Unit
7
V
–0.3 to VDD + 0.3
V
30
V
125
mA
10
mA
2.5
W
–20 to 85
ºC
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A6833
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, logic supply operating voltage Vdd = 3.0 V to 5.5 V
Vdd = 3.3 V
Characteristic
Min.
Typ.
Typ.
Max.
Units
VOUT = 30 V
–
–
10
–
–
10
μA
IOUT = 50 mA
–
–
0.7
–
–
0.7
V
IOUT = 100 mA
–
–
1.0
–
–
1.0
V
2.2
–
–
3.3
–
–
V
Symbol
Output Leakage Current
ICEX
Collector–Emitter Saturation
Voltage
VCE(SAT)
Test Conditions
VIN(1)
Input Voltage
VIN(0)
Input Current
Serial Data Output Voltage
Vdd = 5 V
IIN(1)
VIN = VDD
IIN(0)
VIN = 0 V
Max. Min.
–
–
1.1
–
–
1.7
V
–
< 0.01
1.0
–
< 0.01
1.0
μA
–
< –0.01
–1.0
–
< –0.01
–1.0
μA
VOUT(1)
IOUT = –200 μA
2.8
3.05
–
4.5
4.75
–
V
VOUT(0)
IOUT = 200 μA
–
0.15
0.3
–
0.15
0.3
V
10
–
–
10
–
–
MHz
Maximum Clock Frequency2
fc
IDD(1)
One output on, IOUT = 100 mA
–
–
2.0
–
–
2.0
mA
IDD(0)
All outputs off
–
–
100
–
–
100
μA
tdis(BQ)
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
ten(BQ)
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
tp(STH-QL)
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
tp(STH-QH)
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
Output Fall Time
tf
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
500
–
–
500
ns
Output Rise Time
tr
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
500
–
–
500
ns
IOUT = ±200 μA
–
50
–
–
50
–
ns
Logic Supply Current
Output Enable-to-Output Delay
Strobe-to-Output Delay
Clock-to-Serial Data Out Delay
1Positive
tp(CH-SQX)
(negative) current is defined as conventional current going into (coming out of) the specified device pin.
at a clock frequency greater than the specified minimum value is possible but not warranteed.
2Operation
Truth Table
Serial
Shift Register Contents
Data Clock
Input Input I1 I2 I3 ... IN-1 IN
Serial
Data Strobe
Output Input
H
H
R1 R2 ...
RN-2 RN-1
RN-1
L
L
R1 R2 ...
RN-2 RN-1
RN-1
X
R1 R2 R3 ...
RN-1 RN
RN
X
X
X
X
...
P1 P2 P3 ...
L = Low Logic Level
H = High Logic Level
X = Irrelevant
X
PN-1 PN
Latch Contents
I1
I2
I3
...
IN-1
IN
Output
Enable
Input
Output Contents
I1 I2 I3 ... IN-1 I N
X
L
R1 R2 R3 ...
RN-1 RN
PN
H
P1 P2 P3 ...
PN-1 PN
H
P1 P2 P3 ... PN-1 PN
X
X
L
H H H ... H
X
X
...
X
H
P = Present State
R = Previous State
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A6833
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
Timing Requirements and Specifications
(Logic Levels are VDD and Ground)
C
50%
C LOC K
A
S E R IAL
DAT A IN
B
DAT A
50%
t p(C H-S QX)
S E R IAL
DAT A OUT
DAT A
50%
D
E
50%
S T R OB E
OUT P UT E NAB LE
HIG H = ALL OUT P UT S E NAB LE D
t p(S TH-QH)
t p(S T H-QL)
90%
DAT A
OUT N
10%
LOW = ALL OUT P UT S B LANK E D (DIS AB LE D)
OUT P UT E NAB LE
50%
t en(B Q)
tr
tf
t dis (B Q)
OUT N
90%
10%
Key
Description
A
Data Active Time Before Clock Pulse (Data Set-Up Time)
B
DAT A
50%
Symbol
tsu(D)
Time (ns)
Data Active Time After Clock Pulse (Data Hold Time)
th(D)
25
C
Clock Pulse Width
tw(CH)
50
D
Time Between Clock Activation and Strobe
tsu(C)
100
E
Strobe Pulse Width
tw(STH)
50
NOTE: Timing is representative of a 10 MHz clock. Higher speeds
may be attainable; operation at high temperatures will reduce the
specified maximum clock frequency.
Serial Data present at the input is transferred to the shift register on
the logical 0 to logical 1 transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to the respective
latch when the STROBE is high (serial-to-parallel conversion). The
25
latches will continue to accept new data as long as the STROBE is
held high. Applications where the latches are bypassed (STROBE
tied high) will require that the OUTPUT ENABLE input be low
during serial data entry.
When the OUTPUT ENABLE input is low, the output sink drivers
are disabled (OFF). The information stored in the latches is not
affected by the OUTPUT ENABLE input. With the OUTPUT
ENABLE input high, the outputs are controlled by the state of their
respective latches.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A6833
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
OUT32
NC
40
OUTPUT ENABLE
41
SERIAL DATA OUT
43
OE 42
LOGIC
SUPPLY
CLOCK
CLK 44
SERIAL DATA IN
VDD 1
POWER GROUND
2
STROBE
3
NC
5
ST 4
OUT1
6
Pin-out Diagram
OUT 2
7
39
OUT31
OUT 3
8
38
OUT30
37
OUT29
36
OUT28
OUT 6
11
OUT 7
12
LATCHES
REGISTER
REGISTER
9
10
LATCHES
OUT 4
OUT 5
35
OUT27
34
OUT26
OUT 8
13
33
OUT25
OUT 9
14
32
OUT24
OUT10
15
31
OUT23
OUT11
16
30
OUT22
OUT 12
17
29
OUT21
Typical Input Circuit
NC 28
OUT20 27
OUT19 26
OUT18 25
OUT17 24
LOGIC GROUND 23
OUT16 22
OUT15 21
OUT14 20
OUT13 19
NC 18
SUB
Typical Output Driver
VDD
OUT
IN
SUB
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A6833
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
Package EP, 44-pin PLCC
17.53 ±0.13
16.59 ±0.08
0.51
2 1 44
7.75 ±0.36
A
17.53 ±0.13 16.59 ±0.08
7.75 ±0.36
0.74 ±0.08
4.57 MAX
44X
SEATING
PLANE
0.10 C
0.43 ±0.10
C
1.27
7.75 ±0.36
For Reference Only
(reference JEDEC MS-018 AC)
Dimensions in millimeters
7.75 ±0.36
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
Copyright ©2003-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
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