A6841: DABiC-5 8-Bit Serial Input Latched Sink Drivers

A6841
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Last Time Buy
This part is in production but has been determined to be
LAST TIME BUY. This classification indicates that the product is
obsolete and notice has been given. Sale of this device is currently
restricted to existing customer applications. The device should not be
purchased for new design applications because of obsolescence in the
near future. Samples are no longer available.
Date of status change: November 1, 2010
Deadline for receipt of LAST TIME BUY orders: April 30, 2011
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A6841
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Features and Benefits
Description
▪ 3.3 to 5 V logic supply range
▪ Power-on reset (POR)
▪ To 10 MHz data input rate
▪ CMOS, TTL compatible inputs
▪ –40°C operation available
▪ Low-power CMOS logic and latches
▪ Schmitt trigger inputs for improved noise immunity
▪ High-voltage current-sink outputs
▪ Internal pull-up/pull-down resistors
▪ Output transient-protection diodes
▪ Single or split supply operation
The merging of low-power CMOS logic and bipolar output
power drivers using the proprietary DABiC-5 fabrication
process permit the A6841 integrated circuits to be used in a
wide variety of peripheral power driver applications. Each
device has an eight-bit CMOS shift register and CMOS
control circuitry, eight CMOS data latches, and eight bipolar
current-sinking Darlington output drivers. The 500 mA,
NPN Darlington outputs, with integral transient-suppression
diodes, are suitable for use with relays, solenoids, and other
inductive loads.
All package variations of the A6841 offer premium performance
with a minimum output-breakdown voltage rating of 50 V (35 V
sustaining). All drivers can be operated with a split supply
where the negative supply is up to –20 V.
Packages:
Not to scale
18-pin DIP (Package A)
20-pin SOICW (package LW)
(drop-in replacement for discontinued 18-pin SOIC variants)
The CMOS inputs are compatible with standard CMOS logic
levels. TTL circuits may require the use of appropriate pull-up
resistors. By using the serial data output, drivers can be cascaded
for interface applications requiring additional drive lines.
The A6841 is provided in an 18-pin plastic DIP (suffix A), and
a 20-pin wide-body SOIC (suffix LW) with improved thermal
characteristics compared to the 18-pin SOIC version it replaces
(100% pin-compatible electrically).These devices are lead (Pb)
free, with 100% matte tin plated leadframes.
Applications include:
▪ Relays
▪ Solenoids
▪ Inductive loads
Functional Block Diagram
CLOCK
SERIAL
DATA IN
GROUND
LOGIC
SUPPLY
V DD
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
STROBE
LATCHES
OUTPUT ENABLE
(ACTIVE LOW)
MOS
BIPOLAR
VEE or POWER GROUND
VEE or POWER GROUND
SUB
OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8
26185.114I
K
A6841
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Selection Guide
Part Number
A6841SA-T
A6841SLWTR-20-T
Package
18-pin DIP
20-pin wide body SOIC
Packing
21 pieces per tube
1000 pieces per reel
Ambient
–20ºC to 85ºC
Absolute Maximum Ratings*
Characteristic
Symbol
Notes
Rating
Units
Logic Supply Voltage
VDD
7
V
Emitter Supply Voltage
VEE
–20
V
VIN
–0.3 to VDD +0.3
V
VCE
50
V
Input Voltage Range
Output Voltage
Continuous Output Current
VCE(SUS)
IOUT
For inductive load applications
35
V
Each output
500
mA
Range E
–40 to 85
ºC
Range S
–20 to 85
ºC
Operating Ambient Temperature
TA
Maximum Junction Temperature
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Storage Temperature
Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electrical charges.
Allowable Package Power Dissipation, PD
2.5
2.0
POWER DISSIPATION (W)
18-PIN DIP, R QJA = 65oC/W
1.5
20-PIN SOIC, R QJA = 90 oC/W
1.0
0.5
0
25
50
75
100
125
AMBIENT TEMPERATURE (º C)
150
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A6841
DABiC-5 8-Bit Serial Input Latched Sink Drivers
ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, VEE = 0 V, logic supply operating
voltage VDD = 3.0 to 5.5 V
Vdd = 3.3 V
Characteristic
Typ.
VOUT = 50 V
–
–
10
IOUT = 350 mA, L = 3 mH
35
–
IOUT = 100 mA
–
IOUT = 200 mA
–
Symbol
Output Leakage Current
ICEX
Output Sustaining Voltage
VCE(SUS)
Collector–Emitter Saturation
Voltage
VCE(SAT)
Test Conditions
IOUT = 350 mA
VIN(1)
Input Voltage
Input Resistance
Serial Data Output Voltage
Maximum Clock Frequency2
Max. Min.
Typ.
Max.
Units
–
–
10
μA
–
35
–
–
V
–
1.1
–
–
1.1
V
–
1.3
–
–
1.3
V
–
–
1.6
–
–
1.6
V
2.2
–
–
3.3
–
–
V
VIN(0)
–
–
1.1
–
–
1.7
V
RIN
50
–
–
50
–
–
kΩ
V
VOUT(1)
IOUT = –200 μA
2.8
3.05
–
4.5
4.75
–
VOUT(0)
IOUT = 200 μA
–
0.15
0.3
–
0.15
0.3
V
10
–
–
10
–
–
MHz
fc
Logic Supply Current
Vdd = 5 V
Min.
IDD(1)
One output on, OE = L, ST = H
–
–
2.0
–
–
2.0
mA
IDD(0)
All outputs off, OE = H, ST = H,
P1 through P8 = L
–
–
100
–
–
100
μA
μA
Clamp Diode Leakage Current
Ir
Vr = 50 V
–
–
50
–
–
50
Clamp Diode Forward Voltage
Vf
If = 350 mA
–
–
2
–
–
2
V
tdis(BQ)
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
ten(BQ)
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
Output Enable-to-Output Delay
tp(STH-QL)
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
tp(STH-QH)
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
Output Fall Time
tf
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
Output Rise Time
tr
VCC = 50 V, R1 = 500 Ω, C1 ≤ 30 pF
–
–
1.0
–
–
1.0
μs
IOUT = ±200 μA
–
50
–
–
50
–
ns
Strobe-to-Output Delay
Clock-to-Serial Data Out Delay
tp(CH-SQX)
1Positive
(negative) current is defined as conventional current going into (coming out of) the specified device pin.
2Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
Truth Table
Serial
Data Clock
Input Input
Shift Register Contents
I8
Serial
Data
Output
R1 R2 ...
R7
R7
R1 R2 ...
R7
R7
R1 R2 R3 ...
R8
R8
X
X
X
P8
P8
I1
I2
H
H
L
L
X
X
I3
X
...
...
P1 P2 P3 ...
L = Low Logic Level
H = High Logic Level
X = Irrelevant
Latch Contents
Strobe
Input
I1
I2
Output Contents
I1 I2 I3 ... I8
...
I8
L
R1 R2 R3 ...
R8
H
P1 P2 P3 ...
P8
L
P 1 P2 P3 ... P8
X
X
H
H
X
I3
Output
Enable
Input
X
...
H H ... H
P = Present State
R = Previous State
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A6841
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Timing Requirements and Specifications
(Logic Levels are VDD and Ground)
C
50%
CLOCK
A
SERIAL
DATA IN
B
DATA
50%
t p(CH-SQX)
SERIAL
DATA OUT
DATA
50%
D
50%
STROBE
OUTPUT ENABLE
E
LOW = ALL OUTP UTS E NABLE D
tp(STH-QH)
tp(STH-QL)
90%
DATA
OUT N
10%
HIGH = ALL OUTP UTS BLANKE D (DIS ABLE D)
OUTPUT ENABLE
50%
t en(BQ)
tr
tf
t dis(BQ)
OUT N
10%
Key
Description
A
Data Active Time Before Clock Pulse (Data Set-Up Time)
B
DATA
90%
50%
Symbol
tsu(D)
Time (ns)
Data Active Time After Clock Pulse (Data Hold Time)
th(D)
25
C
Clock Pulse Width
tw(CH)
50
D
Time Between Clock Activation and Strobe
tsu(C)
100
E
Strobe Pulse Width
tw(STH)
50
NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be
attainable; operation at high temperatures will reduce the specified maximum clock frequency.
Powering-on with the inputs in the low state ensures that the registers and
latches power-on in the low state (POR).
Serial Data present at the input is transferred to the shift register on the logical
0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK
pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The serial data must appear at the input prior to the rising edge of the
CLOCK input waveform.
25
Information present at any register is transferred to the respective latch
when the STROBE is high (serial-to-parallel conversion). The latches will
continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that
the OUTPUT ENABLE input be high during serial data entry.
When the OUTPUT ENABLE input is high, all of the output buffers are
disabled (OFF). The information stored in the latches or shift register is not
affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE
input low, the outputs are controlled by the state of their respective latches.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A6841
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Pin-out Diagrams
Package A
Package LW
VEE 1
18 OUT1
VEE 1
20 OUT1
CLOCK 2
17 OUT2
CLOCK 2
19 OUT2
SERIAL DATA IN 3
16 OUT3
SERIAL DATA IN 3
18 OUT3
GROUND 4
15 OUT4
GROUND 4
17 OUT4
LOGIC SUPPLY 5
14 OUT5
LOGIC SUPPLY 5
16 OUT5
SERIAL DATA OUT 6
13 OUT6
SERIAL DATA OUT 6
15 OUT6
STROBE 7
12 OUT7
STROBE 7
14 OUT7
OUTPUT ENABLE 8
11 OUT8
OUTPUT ENABLE 8
13 OUT8
10 K
VEE 9
VEE 9
NC 10
12 K
11 NC
(NC pins, 10 and 11, not present
on discontinued 18-pin LW package)
Terminal List Table
Name
VEE
CLOCK
Description
Power Ground to substrate
Clock
Number
Package A
Package LW
1, 9
1, 9
2
2
SERIAL DATA IN
Serial Data In
3
3
GROUND
Logic Ground
4
4
VDD
Logic Supply
5
5
Serial Data Out, for cascading devices
6
6
Strobe
7
7
Output Enable (active low)
8
8
Common to +VL , for inductive loads
10
12
Not internally connected
–
10, 11
SERIAL DATA OUT
STROBE
OUTPUT ENABLE
K
NC
OUT8
Sink Output 8
11
13
OUT7
Sink Output 7
12
14
OUT6
Sink Output 6
13
15
OUT5
Sink Output 5
14
16
OUT4
Sink Output 4
15
17
OUT3
Sink Output 3
16
18
OUT2
Sink Output 2
17
19
OUT1
Sink Output 1
18
20
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A6841
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Typical Application
Relay/solenoid driver using split supply
18-pin DIP (A Package)
CLOCK
2
18
CLK
6
STROBE
7
OUTPUT
ENABLE
8
9
V DD
LATCHES
5
SHIFT REGISTER
4
17
CLOCK
2
16
SERIAL
DATA IN
3
15
OE
20
SUB
CLK
14
5
19
18
4
V DD
17
16
SERIAL
DATA OUT
6
12
STROBE
7
ST
14
11
OUTPUT
ENABLE
8
OE
13
13
ST
+30 V
1
SUB
3
SERIAL
DATA OUT
+5 V –15 V
LATCHES
1
SERIAL
DATA IN
20-pin SOICW (LW Package)
+30 V
SHIFT REGISTER
+5 V –15 V
10
9
SUB
15
12
SUB
11
10
Pins 10 and 11 can float; other pins
match discontinued 18-pin SOIC: 1 to 9
same, pins 12 to 20 match pins 10 to 18
Typical Input Circuits
Typical Output Driver
VDD
K
OUT
STROBE
OUTPUT
ENABLE
VEE
SUB
VDD
CLOCK
SERIAL
DATA IN
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A6841
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Package A, 18-Pin DIP
22.86 ±0.51
18
+0.10
0.25 –0.05
+0.76
6.35 –0.25
+0.38
10.92 –0.25
7.62
A
1
2
5.33 MAX
+0.51
3.30 –0.38
2.54
+0.25
1.52 –0.38
0.46 ±0.12
SEATING
PLANE
C
All dimensions nominal, not for tooling use
(reference JEDEC MS-001 AC)
Dimensions in inches
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
Package LW, 20-Pin SOICW
12.80±0.20
4° ±4
20
20
+0.07
0.27 –0.06
7.50±0.10
10.30±0.33
A
1
2.25
9.50
+0.44
0.84 –0.43
2
1
2
0.65
0.25
20X
SEATING
PLANE
0.10 C
0.41 ±0.10
1.27
C
SEATING PLANE
GAUGE PLANE
1.27
B PCB Layout Reference View
2.65 MAX
0.20 ±0.10
For Reference Only
Dimensions in millimeters
(Reference JEDEC MS-013 AC)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Reference pad layout (reference IPC SOIC127P1030X265-20M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A6841
DABiC-5 8-Bit Serial Input Latched Sink Drivers
Copyright ©2004-2010 Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
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