A8904: 3-Phase Brushless DC Motor Controller/Driver with Back-EMF Sensing

A8904
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
Discontinued Product
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: November 1, 2010
Recommended Substitutions:
For existing customer transition, and for new customers or new applications, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A8904
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
Features and Benefits
Description
▪ Pin-for-pin replacement for A8902CLBA
▪ Start-up commutation circuitry
▪ Sensorless commutation circuitry
▪ Option of external sector data tachometer signal
▪ Option of external speed control
▪ Oscillator operation up to 20 MHz
▪ Programmable overcurrent limit
▪ Transconductance gain options: 500 mA/V or 250 mA/V
▪ Programmable watchdog timer
▪ Directional control
▪ Serial port interface
▪ TTL-compatible inputs
▪ System diagnostics data-out ported in real time
▪ Dynamic braking through serial port or external terminal
The A8904 is a 3-phase brushless DC motor controller/driver
designed for applications where accurate control of high-speed
motors is required. The three half-bridge outputs are low
on-resistance, N-channel DMOS devices capable of driving up
to 1.2 A. The A8904 provides complete, reliable, self-contained
back EMF sensing, motor start-up, and running algorithms. A
programmable digital frequency-locked loop speed control
circuit together with the linear current control circuitry provides
precise motor speed regulation.
A serial port allows the user to program various features and
modes of operation, such as the speed control parameters,
start-up current limit, sleep mode, direction, and diagnostic
modes.
The A8904 is fabricated in the Allegro® BCD (Bipolar CMOS
DMOS) process, an advanced mixed-signal technology that
combines bipolar, analog, and digital CMOS, with DMOS
power devices.
Packages:
Not to scale
28-pin TSSOP
with exposed thermal pad
(Package LP)
The device is provided in a 24-pin wide-body SOIC package,
with 4 internally-fused leads for enhanced thermal dissipation
(package LB), and a thin (<1.2 mm overall height), 28-pin
TSSOP package with an exposed thermal pad Package LP).
Both packages are lead (Pb) free, with 100% matte tin leadframe
plating.
24-pin SOICW
with internally fused pins
(LB package)
Functional Block Diagram
LOGIC
SUPPLY
C D1
C D2
C ST
BRAKE
C RES
VDD
OUT B
OUT C
CENTERTAP
VBB
FCOM COMMUTATION
DELAY
START-UP
OSC.
BLANK
BOOST
CHARGE
PUMP
LOAD
SUPPLY
OUT A
SEQUENCE
LOGIC
OUT A
COMMUTATION
LOGIC
BRAKE
OUT B
OUTC
WATCHDOG
TIMER
C WD
SECTOR
DATA
OSC
FREQUENCYLOCKED LOOP
CURRENT
CONTROL
CHARGE
PUMP
RS
GROUND
DATA IN
SERIAL PORT
CHIP CLOCK RESET
SELECT
26301.5H
MUX
DATA OUT
TSD
GROUND
FILTER
A8904
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
Selection Guide
Part Number
A8904SLBTR-T
A8904SLPTR-T
Package
Packing
24-pin SOIC
28-pin TSSOP
450 per reel
4000 per reel
Absolute Maximum Ratings
Rating
Units
Load Supply Voltage
Characteristic
VBB
15
V
Logic Supply Voltage
VDD
7
V
Logic Input Voltage Range
VIN
Continuous
–0.3 to VDD + 0.3
V
tw < 30 ns
–1.0 to VDD + 1.0
V
±1.4
A
±3.0
A
800
A
–20 to 85
ºC
150
ºC
–55 to 150
ºC
Output Current
Peak Output Current (Brake)
IOUT(BRK) Period
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
Symbol
IOUT
Notes
Output current rating may be restricted to a value determined by system concerns and factors.
These include: system duty cycle and timing,
ambient temperature, and use of any heatsinking and/or forced cooling. For reliable operation,
the specified maximum junction temperature
should not be exceeded.
IOUT(BRK)
tfIOUT(BRK)
TA
TJ(max)
Tstg
Fall of IOUT(BRK) from ±3.0 A to ±1.4 A
Peak output current is a transient condition that
occurs during braking when the motor acts as a
generator. The 3 A level is based on the maximum peak of a sine wave that is damped. The
maximum period between the initial brake being
applied and the current through the drivers falling to 1.4 A should not exceed 800 ms. See the
Braking section for more information.
Range S
Fault conditions that produce excessive junction temperature will activate device thermal
shutdown circuitry. These conditions can be
tolerated, but should be avoided.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
A8904
Pin-out Diagrams
LB Package
LOAD
SUPPLY
1
C D2
2
C WD
3
CST
4
OUTA
COMMUTATION
DELAY
LP Package
24
C D1
23
DATA IN
22
CLOCK
21
CHIP SELECT
5
20
RESET
GROUND
6
19
GROUND
GROUND
7
18
GROUND
OUT B
8
MUX
17
DATA OUT
OUT C
99
FLL
16
OSCILLATOR
15
LOGIC
SUPPLY
14
INDEX
13
FILTER
CENTERTAP
BB
SERIAL PORT
V
V
DD
10
BRAKE
11
C RES
12
BOOST
CHARGE
PUMP
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright © 2003 Allegro MicroSystems, Inc.
3
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
A8904
LB (SOIC) Package
LP (TSSOP) Package
Thermal Characteristics
Characteristic
Symbol
Test Conditions*
Value Units
Package LB, 4-layer PCB based on JEDEC standard
Package Thermal Resistance
RθJA
35
ºC/W
50
ºC/W
Package LP, 4-layer PCB based on JEDEC standard
28
ºC/W
Package LP, 2-layer PCB with 3.8 in2 of copper area each side
36
ºC/W
Package LB, 2-layer PCB with 1
in.2
of copper area each side
*Additional thermal information available on the Allegro website
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
A8904
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5.0 V
Characteristic
Logic Supply Voltage
Logic Supply Current
Undervoltage Threshold
Symbol
VDD
IDD
UVLO
Load Supply Voltage
Load Supply Current
VBB
IBB
Thermal Shutdown
Thermal Shutdown Hysteresis
Output Drivers
Output Leakage Current
TJ
TJ
Total Output ON Resistance
(source + sink + RS)
Output Sustaining Voltage
Clamp Diode Forward Voltage
Control Logic
Logic Input Voltage
Logic Input Current
BRAKE Threshold
BRAKE Hysteresis Current
BRAKE Current
DATA Output Voltage
CST Current
CST Threshold
Filter Current
Filter Threshold
CD Current
(CD1 or CD2)
CD Current Matching
CD Threshold
CD Input Leakage
IDSX
Test Conditions
Operating
Operating
Sleep mode
Decreasing VDD
Increasing VDD
Operating
Operating
Sleep mode
Min.
4.5
—
—
—
—
4.0
—
—
—
—
Limits
Typ.
Max.
5.0
5.5
7.5
10
250
500
3.6
—
3.9
—
—
14
4.0
8.0
20
30
165
—
20
—
Units
V
mA
μA
V
V
V
mA
μA
°C
°C
VBB = 14 V, VOUT = 14 V, sleep mode
VBB = 14 V, VOUT = 0 V
IOUT = 600 mA
—
—
—
200
-2.0
1.0
300
-15
1.4
μA
μA

VDS(sus)
VF
VBB = 14 V, IOUT = IOUT(MAX), L = 3 mH
IF = 1.0 A
14
—
—
1.25
—
1.5
V
V
VIN(0)
VIN(1)
IIN(0)
IIN(1)
VBRK
IBRKL
IBRK
VOUT(0)
VOUT(1)
ICST
SECTOR DATA, RESET, CLK,
CHIP SELECT, OSC
VIN = 0 V
VIN = 5.0 V
—
2.0
—
—
1.5
—
—
—
3.5
-9.0
—
2.25
0.85
-9.0
9.0
—
1.57
-18
32
1.8
2.25
—
—
—
—
—
1.75
4.0
20
—
—
-10
500
2.5
1.0
-10
10
—
1.85
-20
40
2.0
2.5
—
0.8
—
-0.5
±1.0
2.0
—
—
1.5
—
-11
—
2.75
1.15
-11
11
±5.0
2.13
-22
48
2.2
2.75
1.0
V
V
μA
μA
V
μA
μA
V
V
μA
μA
V
V
μA
μA
nA
V
μA
μA
—
V
μA
rDS(on)
VCSTH
VCSTL
IFILTER
VFILTERTH
ICD
—
VCDTH
ICDIL
VBRK = 750 mV
Brake set, D2 = 1, IBRK = 750 mV
IOUT = 500 μA
IOUT = -500 μA
Charging
Discharging, VCST = 2.5 V
High
Low
Charging
Discharging
Leakage, VFILTER = 2.5 V
Charging
Discharging
ICD(DISCHRG)/ICD(CHRG)
Continued next page …
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A8904
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
ELECTRICAL CHARACTERISTICS (continued) at TA = +25°C, VDD = 5.0 V
Characteristic
CWD Current
CWD Threshold Voltage
Max. FLL Oscillator Frequency
Oscillator High Duration
Oscillator Low Duration
Maximum Output Current
Symbol
ICWD
VTL
VTH
fOSC
ton
toff
IOUT(MAX)
Transconductance Gain
gm
Centertap Resistors
Back-EMF Threshold with respect
RCT
—
to VCTAP at FCOM transition
Test Conditions
Charging, D26 = 0, D27 = 0
Charging, D26 = 0, D27 =1
Charging, D26 = 1 D27 = 0
Charging, D26 = 1, D27 =1
D3 = 0, D4 = 0, D28 = 0
D3 = 0, D4 = 1, D28 = 0
D3 = 1, D4 = 0, D28 = 0
D3 = 1, D4 = 1, D28 = 0
D3 = 0, D4 = 0, D28 = 1
D3 = 0, D4 = 1, D28 = 1
D3 = 1, D4 = 0, D28 = 1
D3 = 1, D4 = 1, D28 = 1
D28 = 1
D28 = 0
Min.
-9.0
-18
-27
-36
0.22
2.25
20*
20
20
1.0
0.9
500
—
500
415
—
—
210
420
5.0
5.0
Limits
Typ.
Max.
-10
-11
-20
-22
-30
-33
-40
-44
0.25
0.28
2.5
2.75
—
—
—
—
—
—
1.2
1.4
1.0
1.1
600
700
250
—
600
700
500
585
300
—
125
—
250
290
500
580
10
13
20
37
-5.0
-20
-37
Units
μA
μA
μA
μA
V
V
MHz
ns
ns
A
A
mA
mA
mA
mA
mA
mA
mA/V
mA/V
k
mV
mV
Negative current is defined as coming out of (sourcing) the specified device terminal.
* Operation at an oscillator frequency greater than the specified minimum value is possible but not waranteed.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A8904
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
Serial Port Timing Conditions
A. Minimum CHIP SELECT setup time before CLOCK rising edge ........... 100 ns
B. Minimum CHIP SELECT hold time after CLOCK rising edge ................ 150 ns
C. Minimum DATA setup time before CLOCK rising edge .......................... 150 ns
D. Minimum DATA hold time after CLOCK rising edge ............................... 150 ns
E. Minimum CLOCK low time before CHIP SELECT ................................... 50 ns
F. Maximum CLOCK frequency ................................................................ 3.3 MHz
G. Minimum CHIP SELECT high time ........................................................ 500 ns
Note: the A8904 can be directly used in an existing A8902–A application, as the five most
significant bits are reset to zero, which is the default condition for A8902–A operation. The
only consideration when using the A8904 in an A8902-A application, is to ensure the minimum CHIP SELECT high time is at least 500 ns.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A8904
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
Terminal Functions
Terminal Name
LOAD SUPPLY
CD2
Function
VBB; the 5 V or 12 V motor supply.
One of two capacitors used to generate the ideal commutation points from
the back-EMF zero crossing points.
CWD
Timing capacitor used by the watchdog circuit to blank out the back-EMF
comparators during commutation transients, and to detect incorrect motor
position.
CST
Start-up oscillator timing capacitor.
NC
No( internal) connection.
OUTA
Power amplifier A output to motor.
NC
No (internal) connection.
GROUND
Power and logic ground and thermal heat sink.
POWER GROUND
Power ground.
NC
No (internal) connection.
OUTB
Power amplifier B output to motor.
OUTC
Power amplifier C output to motor.
CENTERTAP
Motor centertap connection for back-EMF detection circuitry.
BRAKE
Active low turns ON all three sink drivers shorting the motor windings to
ground. External capacitor and resistor at BRAKE provide brake delay.
The brake function can also be controlled via the serial port.
CRES
External reservoir capacitor used to hold charge to drive the source drivers’
gates. Also provides power for brake circuit.
ANALOG GROUND
Analog ground.
FILTER
Analog voltage input/output to control motor current. Also, compensation node
for internal speed control loop.
SECTOR DATA
External tachometer input. Can use sector or index pulses from disk to
provide precise motor speed feedback to internal frequency-locked loop.
LOGIC SUPPLY
VDD; the 5 V logic supply.
OSCILLATOR
Clock input for the speed reference counter.
DATA OUT
Thermal shutdown indicator, FCOM, TACH, or SYNC signals available in
real time, controlled by 2-bit multiplexer via serial port.
NC
No (internal) connection.
GROUND
Power and logic ground and thermal heat sink.
DIGITAL GROUND
Logic ground.
RESET
When pulled low forces the chip into sleep mode; clears all serial port bits.
NC
No (internal) connection.
CHIP SELECT
Strobe input (active low) for data word.
CLOCK
Clock input for serial port.
DATA IN
Sequential data input for the serial port.
CD1
One of two capacitors used to generate the ideal commutation points from
the back-EMF zero crossing points.
* For the LP package, ground terminals 1, 8, and 22 must be connected together externally.
LB
(SOIC)
1
2
LP
(TSSOP)
15
16
3
17
4
–
5
–
6-7
–
–
8
9
10
11
18
19
20
21
–
22*
23
24
25
26
27
12
28
–
1*
13
14
2
3
15
16
17
4
5
6
–
18-19
–
20
–
21
22
23
24
7
–
8*
9
10
11
12
13
14
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A8904
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
Functional Description
Overview of operation. Each electrical revolution
contains six states that control the three half-bridge outputs.
Optimized switching from state to state is achieved through the
adaptive commutation circuitry. During any state, one output is
high, one is low and the other is high impedance. The back-EMF
at the high-impedance output is sensed and compared to the
voltage of the centertap and when the two signals are equivalent,
the FCOM signal toggles. A controlled delay is then introduced
before the sequencer commutates into the next state.
Linear current-mode control is employed to provide precision control of the motor speed while maintaining extremely
low electrical noise emissions. The speed control is realized
through a frequency-locked loop that processes the sensed
back-EMF signals from the stator phases to eventually produce a
TACH signal. The TACH signal is then compared to the desired
programmed speed, to produce an error. The error signal is then
used to linearly control the current through the low-side DMOS
power devices to obtain the correct speed.
Alternative control schemes can be introduced, giving the
user maximum flexibility and optimization for each application.
An external tachometer signal applied to the SECTOR DATA
input, along with the internal speed reference can be used for
high-precision speed control. As another alternative, the user can
introduce external speed control by driving the FILTER terminal
directly.
Start-up routines are inherent in the solution to guarantee
reliable start-up. During start-up, a YANK feature allows rapid
transition to the nominal operating condition on the FILTER
terminal. This feature is also available when the external speed
control is used.
Dynamic braking can be introduced by either the external
BRAKE terminal or through the brake bit in the serial port.
A serial port allows the user to program various features and
modes of operation, such as motor speed, internal or external
speed control, internal or external speed reference, current limit,
sleep mode, direction, charge current (for blanking pulse), motor
poles, transconductance gain, and various diagnostic outputs.
Full device protection is incorporated, including programmable overcurrent limit, thermal shutdown, and undervoltage
shutdown on the logic supply.
Power outputs. The power outputs of the A8904 are
n-channel DMOS transistors with a total source plus sink rDS(on)
of typically 1 . An internal charge pump provides a voltage rail
above the load supply for driving the high-side DMOS gates.
Intrinsic ground clamp and flyback diodes provide protection
when switching inductive loads. These diodes will also rectify
the motor back-EMF during power-down conditions. If neces-
sary, a transient voltage supply can be provided, by connecting
an external Schottky power diode or pass FET in series, between
the power source and the load supply (VBB). This FET or diode
effectively isolates the low impedance path through the power
source. A filter capacitor is also required to ‘hold up’ the rectified
signal, and is connected between the load supply and ground.
Back-EMF sensing motor start-up and running
algorithm. The A8904 provides a complete self-contained
back-EMF sensing, start-up and running commutation scheme.
A state machine with six states, (shown in the tables below for
both forward and reverse direction) controls the three half-bridge
outputs. In each state, one output is high (sourcing current), one
low (sinking current), and one is OFF (high impedance or ‘Z’).
Motor back-EMF is sensed at the output that is OFF.
Sequencer State
OUTB
OUTC
(forward direction)
OUTA
1
High
Z
Low
2
High
Low
Z
3
Z
Low
High
4
Low
Z
High
5
Low
High
Z
6
Z
High
Low
Sequencer State
(reverse direction)
1
6
5
4
3
2
OUTA
High
Z
Low
Low
Z
High
OUTB
Z
High
High
Z
Low
Low
OUTC
Low
Low
Z
High
High
Z
At start-up, the outputs are always enabled in state 1. The
back-EMF is examined at the OFF output by comparing the output voltage to the motor centertap voltage at CENTERTAP. The
motor will then either step forward, step backward or remain
stationary (if in a null-torque position).
If the motor does not move during the initial start-up state,
the outputs are commutated automatically by the start-up oscillator. When suitable back-EMF signals are detected, the start-up
oscillator is overridden and the corresponding timing clock is
generated, providing synchronous back-EMF commutation. The
start-up oscillator period is determined by
tCST = (VCSTH - VCSTL) x CST / IST(charge)
where CST is the start-up capacitor.
If the motor moves, the back-EMF detection and direction
circuit waits for the correct polarity of back-EMF zero crossing
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
A8904
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
Functional Description (cont’d)
(output crossing through centertap). If the correct polarity of
back-EMF is not detected, a watchdog circuit commutates the
output until the correct back-EMF is detected. Correct backEMF sensing is indicated by the FCOM signal, which toggles
every time the back-EMF completes a zero crossing (see waveforms below). FCOM is available at the DATA OUT terminal.
True back-EMF zero crossings are used by the adaptive
commutation delay circuit to advance the state sequencer (commutate) at the proper time to synchronously run the motor. See
next section.
Adaptive commutation delay. The adaptive commutation delay circuit uses the back-EMF zero-crossing indicator
signal (FCOM) to determine an optimal commutation time for
efficient synchronous switching of the output drivers. When the
FCOM signal changes state, one of the delay capacitors (CD1
or CD2) is discharged at approximately twice the rate of the
charging current. When the capacitor reaches the 2.5 V threshold, a commutation occurs. During this discharge period, the
other delay capacitor is being charged in anticipation of the next
FCOM state change. In addition, there is an interruption to the
charging, which is set by the blanking duration (see waveform
below, VCWD, and next section). This additional charging delay
causes the commutation to occur at slightly less than 50% of
the FCOM on or off duration, to compensate for delays caused
by winding inductance. The typical delta voltage change during
normal operation in the commutation capacitors (CD1 & CD2),
will range between
1.5 V and 2.0 V. The commutation capacitor values can be determined from:
CDX = ICD x t / VCD
where VCD = 1.5 V, ICD = 20 μA, and t = (60/rpm)/(#motor poles
x 3), duration of each state.
To avoid the capacitors charging to the supply rail, the value
selected should provide adequate margin, taking into account the
effects of capacitor tolerance, charging current, etc.
Blanking and watchdog timing functions. The blanking and watchdog timing functions are derived from one timing
capacitor CWD .
During normal commutation, at the beginning of each new
sequencer state, a blanking signal is created until the watchdog
capacitor CWD is charged to the threshold VTL (see waveforms
below). This blanking signal prohibits the back-EMF comparators from tripping due to the discharging of inductive energy and
voltage settling transients during sequence state transitions. The
duration of this blanking signal depends on the size of the CWD
capacitor and the programmed charge current, ICWD (via D2627). This blanking pulse also interrupts the commutation delay
capacitors CD1 and CD2 from charging (see previous section).
The ability to select the minimum charge current for CWD
is particularly useful during start-up, where the duration of the
diode recirculation current is highest. In applications where
high motor speeds are experienced, the charge current can be
increased so that the blanking period does not encroach significantly into the period of each sequencer state and does not cause
unbalance in the commutation points.
It is recommended to select the value of CWD in the actual
application circuit with the A8904 put into step mode. CST
should be reselected (only for this test), to be between 4.7 μF
and 10 μF, so that the motor comes to rest between steps and the
maximum diode conduction time can be measured. The value of
CWD can be determined as:
CWD = ICWD x td / VTL
where td = measured diode conduction, ICWD = charge current at
start-up, and VTL = 250 mV.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
A8904
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
Functional Description (cont’d)
Watchdog-triggered commutation
After the watchdog capacitor CWD charges to the VTL threshold,
and if the correct polarity of back-EMF signal is detected, the
back-EMF detection circuit discharges CWD to zero volts (see
waveform above) and the circuit is ready to detect the next backEMF zero crossing.
If the correct polarity of back-EMF is not detected between
the blanking period, tBLANK, and the watchdog period, tWD,
then the back-EMF detection circuit does not allow the watchdog capacitor CWD to be discharged and the watchdog circuit
commutates the outputs to the next sequencer state (see waveform above). This mode of operation continues until a suitable
back-EMF signal is detected. This function is useful in preventing excessive reverse rotation, and helps in resynchronising (or
starting) with a moving spindle.
The duration of the watchdog-triggered commutation is
determined by:
tWD = VTH x CWD / ICWD
where ICWD = normal charge current.
Speed control. The actual speed of the motor is measured
by either internally sensing the back-EMFs or by an external
scheme via the SECTOR DATA terminal. A TACH signal is
produced from these signals, which is then compared against the
desired speed, which is programmed into a 14-bit counter (see
diagram and waveforms below - assumes internal scheme used).
The resulting error signal, ERROR, is then used to charge or
discharge the FILTER terminal capacitor depending on whether
the motor is running too slow or too fast. The FILTER terminal
voltage is used to linearly drive the low-side MOSFETs to match
the desired speed.
Each back-EMF signal detected causes the state of the
FCOM signal to change. The number of FCOM transitions per
mechanical revolution is equal to the number of poles times 3.
For example, with a 4-pole motor (as shown on next page), the
number of FCOM transitions will equal 12 per mechanical revolution. The number of poles are programmed via serial port bits
D20 and D21. There are six electrical states per electrical revolution, therefore, for this example, there are 12 commutations or
two electrical revolutions per mechanical revolution.
The TACH signal changes state once per mechanical revolution and as well as providing information on the actual motor
speed is also used to trigger the REF counter which contains
the information on the desired motor speed. Alternatively an
external TACH signal can be used, an explanation of which is
presented in the Sector Mode Section.
The duration of REF is set by programming the counter to
count the desired number of OSCILLATOR cycles, according to
the following:
total count = 60 x fOSC / desired motor speed (rpm)
where the total count (number of oscillator cycles) is equal to the
sum of the count numbers selected through bits D5 to D18 in the
serial port and fOSC corresponds to the OSCILLATOR frequency.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
A8904
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
Functional Description (cont’d)
Speed error signals
A speed error signal is created by integrating the differences
between the TACH and REF signal. If the TACH signal goes low
before the REF signal then an ERROR FAST is produced and if
the TACH signal goes low after the REF signal then an ERROR
SLOW is produced. The error signal generated enables the appropriate current source (see diagram next page) to either charge
or discharge the filter components on the FILTER terminal.
The FILTER voltage is then used to provide linear current control in the windings via the transconductance stage (see
diagram next page). The output current is sensed through an
internal sense resistor, RS. The voltage across the sense resistor
is compared to the lowest of either one-tenth of the voltage at
the FILTER terminal, minus the filter threshold voltage, or to the
maximum current limit reference.
Alternatively, external control of the FILTER terminal can
be introduced by disabling the frequency-lock loop circuitry
(D24 = 1).
The transconductance function is defined as:
IOUT = (VFILTER – VFILTERTH) / (10 x RS x G)
where RS is nominally 200 m,
VFILTERTH is approximately 1.85 V,
G = 1, when D28 = 0 and gain = 500 mA/V or
G = 2, when D28 = 1 and gain = 250 mA/V.
The closed loop control response of the overall system is
shaped via the filter components that are introduced at the FILTER terminal.
Clamping the current to a level defined by the serial port
(D3 & D4) provides output current limit protection. This feature
is particularly useful where high transient currents are experienced, e.g., during start-up. Once normal running conditions are
reached, the current limit can be appropriately reduced. Note that
the current limit is scaled according to the gm value selected.
Sector mode. An external tachometer signal, such as sector or index pulses, can be used to create the TACH signal, rather
than the internally generated once-around scheme. The external
signal is applied to the SECTOR DATA terminal and the serial
port bit (D19 = 1) must be programmed to enable this feature.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
A8904
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
Functional Description (cont’d)
Speed and current control
In applications where both internal and external TACH signals are used, it is important to only switch between modes when
the SYNC signal on DATA OUT is low. This ensures the speed
control information that is being processed during the transition,
is not corrupted. SYNC is accessed through the DATA OUT
multiplexer, which is controlled by D22 & D23.
DATA OUT. The DATA OUT terminal is the output of a
2-bit input multiplexer controlled by D22 & D23 of the serial
port. Data available are TACH signal (internally or externally
generated), SYNC signal, FCOM signal, and thermal shutdown
(LOW = A8904 operating within thermal limits, HIGH = thermal
shutdown has occurred).
Speed loop initialization (YANK). To ensure rapid
transition from start-up to the normal operating condition, the
FILTER terminal is pulled up to the filter threshold voltage,
VFILTERTH, by the internal YANK command and the initial output
current will be set to the maximum selected current limit. This
condition is maintained until the motor reaches the correct speed
and the first ERROR FAST signal is produced which removes
the YANK and allows linear current control.
The YANK feature is also activated when an external
speed control scheme is used (D24 = 1). To ensure the YANK is
released at start-up by the internal speed control, it is important
to ensure the speed reference is set at a lower speed than what
the motor is designed to run at. Note that when the serial port is
programmed to run initially, the default condition for the speed
is set for the slowest condition so this will guarantee the YANK
to be released. It is important when using external speed control
that, as a minimum, the number of poles, speed control mode,
and speed reference are programmed in the serial port.
Forward/reverse. Directional control is managed through
D25 in the serial port.
Serial port. Control features and diagnostic data selection
are communicated to the A8904 through the 29-bit serial port.
See serial port timing diagrams on page 6. When CHIP SELECT
is low, data is written to the serial port on the positive edge of
the clock with the MSB (D28) fed in first. At the end of the write
cycle, the CHIP SELECT goes high, the serial port is disabled
and no more data can be transferred. In addition, the data written
to the serial port is latched and becomes active.
If a word of less than 29 bits is sent, the unused most significant bits that are not programmed, are reset to zero. There
are no compatibility issues when using the A8904 in an existing
A8902-A application as the five MSBs are reset to zero, which is
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
A8904
Functional Description (cont’d)
the default condition for A8902-A operation. The only consideration when using the A8904 in an A8902-A application is to
ensure the minimum CHIP SELECT high time is at least 500 ns.
D0 - Sleep/Run Mode; LOW = Sleep, HIGH = Run. This bit
allows the device to be powered down when not in use.
D1 - Step Mode; LOW = Normal Operation, HIGH = Step
Only. When in the step-only mode the back-EMF commutation
circuitry is disabled and the start-up oscillator commutates the
power outputs. This mode is intended for device and system
testing.
D2 - Brake; LOW = Run, HIGH = Brake.
D3, D4, and D28 - The output current limit is set by D3 &
D4; D28 sets the transconductance gain.
Current limit Transconductance
D3 D4 D28
(typical)
gain
0
0
0
1.2 A
500 mA/V
0
1
0
1.0 A
500 mA/V
1
0
0
600 mA
500 mA/V
1
1
0
250 mA
500 mA/V
0
0
1
600 mA
250 mA/V
0
1
1
500 mA
250 mA/V
1
0
1
300 mA
250 mA/V
1
1
1
125 mA
250 mA/V
D5 to D18 - 14-bit word, active low. Programs the count
number to produce the corresponding REF signal, which indicates the desired motor speed.
Bit number
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
Count number
16
32
64
128
256
512
1,024
2,048
4,096
8,192
16,384
32,768
65,536
131,072
D19 - Speed control mode; LOW = internal, once-around
speed signal, HIGH = external sector data.
D20 and D21 - Programs the number of motor poles for the
once-around FCOM counter.
D20
D21
Motor poles
0
0
8
0
1
4
1
0
16
1
1
12
D22 and D23 - Controls the multiplexer for DATA OUT.
See DATA OUT Section for status definitions.
D22 D23
DATA OUT
0
0
TACH (once around or sector) signal
0
1
Thermal shutdown
1
0
SYNC signal
1
1
FCOM signal
D24 - Speed Reference. LOW = Internal, using back-EMF
technique, HIGH = External (internal control disabled).
D25 - Direction. LOW = Forward, HIGH = Reverse.
D26 and D27 - Programs the charging current for the watchdog capacitor. This function is used for adjusting the blanking
duration and also the watchdog commutation period.
D26 D27
Watchdog charge current (typical)
0
0
-10 μA
0
1
-20 μA
1
0
-30 μA
1
1
-40 μA
D28 - Programs the transconductance gain. LOW = 500 mA/V,
HIGH = 250 mA/V.
Reset. When the RESET terminal is pulled low, all the
serial port bits are reset to LOW and the part operates in sleep
mode.
Undervoltage lockout, VDD. When an undervoltage
condition occurs, all the serial port bits are reset to LOW and the
part operates in sleep mode.
Charge pump. The charge pump is required to provide
a voltage rail above the load supply for driving the high-side
DMOS gates. In addition the charge pump supply capacitor,
CRES, also powers the brake control circuit during power-down
conditions. CRES should be 220 nF.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
A8904
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
Functional Description (cont’d)
Braking. A dynamic braking feature of the A8904 shorts
the three motor windings to ground. This is accomplished by
turning the three source drivers OFF and the three sink drivers
ON. Activation of the brake can be implemented through the
BRAKE input or through the D2 bit in the serial port.
During braking, the motor is effectively acting as three
sine-wave voltage generators, 120° out of phase, where the
voltage developed by each of the windings is proportional to the
motor speed and constant. The current through any sink driver is
simply the generated voltage divided by the center tap to OUT
resistance plus the sink driver resistance. As the motor tends to
slow during the braking process, both the generated voltage and
the corresponding current decreases.
When selecting a motor to use where braking will be applied, it is important to characterize the application to ensure
that when braking is applied, the peak current in the sink drivers
does not exceed 3A and the period from the peak current to the
maximum current limit of the drivers does not exceed 800 ms.
Another consideration is the thermals of the solution, where
repeated spin-up followed by brake cycles could cause excessive
junction temperatures.
The supply voltage for the brake circuit is derived from the
charge pump supply capacitor, CRES. With CRES chosen to be
220 nF, the brake circuit will function for at least 100 ms after a
power failure.
In certain applications such as disk drives, it is desirable to
include a brake delay to allow sensitive circuitry such as the disk
head to retract before activating the spindle motor brake. The
brake delay can be simply implemented by using an external RC
and diode to control the brake terminal.
The brake delay can be set using the equation:
tBRK = –RBCB x ln (VBRK / [VFAULT – VD]).
Once the brake is activated, the three sink drivers will remain active until the supply rails fall below the operating range.
It is recommended that the part is reset before restarting.
Centertap. It is recommended that the centertap connection of the motor be connected to the CENTERTAP terminal. If
the centertap of the motor is not connected to the CENTERTAP
terminal, the A8904 internally emulates the centertap voltage of
the motor through a series of 10 k resistors connected between
each output and CENTERTAP. This technique does not provide
ideal commutation points.
External component selection. All capacitors should
be rated to at least 25 V and the dielectric should be X7R, apart
from the start-up capacitor CST, which can be Z5U dielectric
or equivalent and the input capacitor Cfilter, which should be an
electrolytic type of value greater than 100 μF, 35 V, Iripple > 100
mA. If the solution experiences ambient temperatures of greater
than 70°C then Cfilter should be rated for 105°C.
All resistors are at least 1/8 W and have a tolerance of ±5%.
In noise-sensitive systems where electromagnetic interference is an issue, or to stabilize the current waveforms with certain motors, it may be necessary to add RC snubbers across the
motor windings as shown in the application circuit on the next
page. The A8904 solution should be relatively noise immune
from the effects of switching voltage spikes etc. if the correct
watchdog capacitor has been selected for optimum blanking and
good layout practices are implemented.
At the range of operating frequencies that the current pulses
are drawn out of the load supply, it is the capacitance reactance
as opposed to the ESR that dominates the overall impedance of
the input filter, Cfilter. Therefore, it is possible to reduce conducted electromagnetic emissions further, by simply increasing the
value of Cfilter. In extremely sensitive systems, it may be necessary to introduce a differential mode inductor in series with the
load supply line.
Layout considerations. The TSSOP part (A8904SLP)
has three separate ground connections, analog, digital, and power that must be connected together externally. A ground plane
should be used to provide heat sinking for the power switches
and the reduction of potential noise pick-up through inductive
loops and radiated emissions. The ground plane should cover the
area beneath the A8904 and extend beyond the outline to form a
plane around all the external components. The exposed thermal
pad of the TSSOP part should be connected to the ground plane.
Filter components, especially Cfilter, timing, and delay
capacitors should be positioned as close as possible to the device
terminals. It is also imperative that the traces to the serial port
and oscillator are as short and as wide as possible to reduce stray
inductance and prevent potential data corruption. In addition,
these traces should be positioned well away from any noisy
signals.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
15
A8904
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
Typical application
(LB package)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
A8904
LB package, 24-pin SOICW
15.40±0.20
4° ±4
24
24
+0.07
0.27 –0.06
10.30±0.33
7.50±0.10
A
1
2.20
9.60
+0.44
0.84 –0.43
2
1
2
0.65
1.27
0.25
24X
SEATING
PLANE
0.10 C
0.41 ±0.10
1.27
C
B PCB Layout Reference View
SEATING PLANE
GAUGE PLANE
2.65 MAX
0.20 ±0.10
For reference only
Pins 6 and 7, and 18 and 19 internally fused
Dimensions in millimeters
(Reference JEDEC MS-013 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Reference pad layout (reference IPC SOIC127P1030X265-24M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
LP package, 28-pin TSSOP
with exposed thermal pad
0.45
9.70 ±0.10
28
+0.05
0.15 –0.06
0.65
28
4° ±4
1.65
B
3.00
4.40 ±0.10
6.40 ±0.20
3.00
6.10
0.60 ±0.15
A
1
(1.00)
2
5.00
0.25
28X
SEATING
PLANE
0.10 C
+0.05
0.25 –0.06
0.65
C
SEATING PLANE
GAUGE PLANE
1 2
5.00
C
PCB Layout Reference View
1.20 MAX
0.10 MAX
For reference only
(reference JEDEC MO-153 AET)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
17
A8904
3-Phase Brushless DC Motor Controller/Driver
with Back EMF Sensing
Copyright ©2003-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
18
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