A8905: Three-Phase Brushless DC Motor Controller/Driver with Back EMF Sensing

Data Sheet
26301.3
8905
3-PHASE BRUSHLESS DC MOTOR
CONTROLLER/DRIVER WITH BACK-EMF SENSING
LOAD
SUPPLY
1
C D2
2
C WD
3
C
ST
4
OUTA
5
20
RESET
GROUND
6
19
GROUND
GROUND
7
18
GROUND
OUT B
8
MUX
17
DATA OUT
OUT C
99
FLL
16
OSCILLATOR
CENTERTAP
10
15
LOGIC
SUPPLY
BRAKE
11
14
INDEX
C RES
12
13
FILTER
BB
COMMUTATION
DELAY
SERIAL PORT
V
24
C D1
23
DATA IN
22
CLOCK
21
CHIP SELECT
The A8905CLB isw a three-phase brushless dc motor controller/
driver for use with CD-ROM or DVD drives. The three half-bridge
outputs are low on-resistance n-channel DMOS devices capable of
driving up to 1.25 A. The A8905CLB provides complete, reliable,
self-contained back-EMF sensing motor startup and running algorithms.
A programmable digital frequency-locked loop speed control circuit
together with the linear current control circuitry provides precise motor
speed regulation.
T
C
U
Y
D
L
O
N
R
O
P E
D
C
E
N
U
E
N ER
I
T
F
N
E
O
R
C
S OR
I
D F
—
VDD
BOOST
CHARGE
PUMP
Dwg. PP-040-1
ABSOLUTE MAXIMUM RATINGS
at TA = +25°C
Load Supply Voltage, VBB . . . . . . 14 V
Output Current, IOUT . . . . . . . . ±1.25 A
Logic Supply Voltage, VDD . . . . 6.0 V
Logic Input Voltage Range,
VIN . . . . . . . -0.3 V to VDD + 0.3 V
Package Power Dissipation,
PD . . . . . . . . . . . . . . . . See Graph
Operating Temperature Range,
TA . . . . . . . . . . . . . . 0°C to +70°C
Junction Temperature, TJ . . . +150°C†
Storage Temperature Range,
TS . . . . . . . . . . . . -55°C to +150°C
† Fault conditions that produce excessive
junction temperature will activate device thermal
shutdown circuitry. These conditions can be
tolerated, but should be avoided.
Output current rating may be restricted to a value
determined by system concerns and factors.
These include: system duty cycle and timing,
ambient temperature, and use of any heatsinking
and/or forced cooling. For reliable operation, the
specified maximum junction temperature should
not be exceeded.
A serial port allows the user to program various features and modes
of operation, such as the speed control parameters, startup current limit,
sleep mode, diagnostic modes, and others.
APPLICATIONS
■ CD-ROMs
■ DVDs
FEATURES
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
DMOS Outputs
Low rDS(on)
Startup Commutation Circuitry
Back-EMF Commutation Circuitry
Serial Port Interface
Frequency-Locked Loop Speed Control
Tachometer Signal Input
Programmable Start-Up Current
Diagnostics Mode
Sleep Mode
Linear Current Control
Internal Current Sensing
Dynamic Braking Through Serial Port
Power-Down Dynamic Braking
System Diagnostics Data Out
Data Out Ported in Real Time
Internal Thermal Shutdown Circuitry
Always order by complete part number, e.g., A8905CLB .
8905
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
FUNCTIONAL BLOCK DIAGRAM
LOGIC
SUPPLY
C D1
C D2
C ST
BRAKE
C RES
15
24
2
4
11
12
VDD
BRAKE
BOOST
CHARGE
PUMP
1
LOAD
SUPPLY
5
OUT A
8
OUT B
9
OUTC
V
BB
OUT B
OUT C
CENTERTAP
10
C WD
3
FCOM COMMUTATION
DELAY
SEQUENCE
LOGIC
COMMUTATION
LOGIC
OUT A
START-UP
OSC.
BLANK
WATCHDOG
TIMER
INDEX 14
23
SERIAL PORT
22
ALLOWABLE PACKAGE POWER DISSIPATION in WATTS
MUX
20
CLOCK
CHIP
SELECT
21
CURRENT
CONTROL
CHARGE
PUMP
17
DATA
OUT
DATA IN
FREQUENCYLOCKED LOOP
RESET
OSC 16
RS
1.5
R θJA = 55°C/W
0.5
0
75
100
TEMPERATURE in °C
125
GROUND
Dwg. FP-034-1
RθJT = 6°C/W
50
18-19
FILTER
2.0
25
GROUND
13
2.5
1.0
6-7
TSD
150
Dwg. GP-019B
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1998 Allegro MicroSystems, Inc.
8905
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5.0 V
Limits
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Logic Supply Voltage
VDD
Operating
4.5
5.0
5.5
V
Logic Supply Current
IDD
Operating
—
7.5
10
mA
Sleep Mode
—
—
1.5
mA
Operating
4.5
—
14
V
TJ
—
165
—
°C
∆TJ
—
20
—
°C
VBB = 14 V, VOUT = 14 V
—
1.0
300
µA
VBB = 14 V, VOUT = 0 V
—
-1.0
-300
µA
IOUT = 600 MA
—
1.1
1.4
Ω
VBB = 14 V, IOUT = IOUT(MAX), L = 3 mH
14
—
—
V
IF = 1.0 A
—
1.25
1.5
V
Load Supply Voltage
Thermal Shutdown
Thermal Shutdown Hys.
VBB
Output Drivers
Output Leakage Current
Total Output ON Resistance
Output Sustaining Voltage
Clamp Diode Forward Voltage
IDSX
rDS(on)
VDS(sus)
VF
Control Logic
Logic Input Voltage
Logic Input Current
DATA Output Voltage
CST Current
CST Threshold
Filter Current
CD Current
CD Current Matching
VIN(0)
INDEX, RESET, CLK,
-0.3
—
1.5
V
VIN(1)
CHIP SELECT, OSC, BRAKE
3.5
—
5.3
V
IIN(0)
VIN = 0 V
—
—
-0.5
µA
IIN(1)
VIN = 5.0 V
—
—
1.0
µA
VOUT(0)
IOUT = 500 µA
—
—
1.5
V
VOUT(1)
IOUT = -500 µA
3.5
—
—
V
Charging
14
20
28
µA
Discharging
-14
-20
-28
µA
VCSTH
2.1
2.5
2.9
V
VCSTL
—
500
—
mV
Charging
7.0
10
15
µA
Discharging
-7.0
-10
-15
µA
Leakage, VFILTER = 2.5 V
—
5.0
—
nA
Charging
14
22
28
µA
Discharging
-26
-35
-66
µA
ICD(DISCHRG)/ICD(CHRG)
1.7
2.2
2.3
—
—
2.5
—
V
14
22
28
µA
ICST
IFILTER
ICD
—
CD Threshold
VCD
CWD Current
ICWD
Charging
Continued next page …
8905
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
ELECTRICAL CHARACTERISTICS continued
Limits
Characteristic
Symbol
Min.
Typ.
Max.
Units
VTL
0.80
0.85
0.95
V
VTH
2.4
2.75
3.0
V
VDD = 5.1 V, TA = 25°C
20
—
—
MHz
VDD = 4.5 V, TA = 70°C
—
10
—
MHz
IOUT = 1 A
—
±20
—
%
VBRK
1.4
1.7
2.0
V
Transconductance Gain
gm
0.26
0.35
0.50
A/V
Centertap Resistors
RCT
5.0
10
13
kΩ
VBEMF - VCTAP at
15
25
40
mV
FCOM Transition
-15
-25
-40
mV
CWD Threshold Voltage
Max. FLL Oscillator Frequency
IOUT(MAX) Accuracy
BRAKE Threshold
Back-EMF Hysteresis
fOSC
—
—
Test Conditions
SERIAL PORT TIMING CONDITIONS
CHIP SELECT
E
A
B
CLOCK
C
D
C
D
DATA
Dwg. WP-019
A. Minimum CHIP SELECT setup time before CLOCK rising edge ...... 100 ns
B. Minimum CHIP SELECT hold time after CLOCK rising edge ........... 150 ns
C. Minimum DATA setup time before CLOCK rising edge .................... 150 ns
D. Minimum DATA hold time after CLOCK rising edge ........................ 150 ns
E. Minimum CLOCK low time before CHIP SELECT .............................. 50 ns
F. Maximum CLOCK frequency ........................................................... 3.3 MHz
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8905
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
TERMINAL FUNCTIONS
Term.
Terminal Name
Function
1
LOAD SUPPLY
VBB; the 5 V or 12 V motor supply.
2
CD2
One of two capacitors used to generate the ideal commutation points from the back-EMF
zero-crossing points.
3
CWD
Timing capacitor used by the watchdog circuit to disable the back-EMF comparators
during commutation transients, and to detect incorrect motor position.
4
CST
Startup oscillator timing capacitor.
5
OUTA
Power amplifier output A to motor.
6-7
GROUND
8
OUTB
Power amplifier output B to motor.
9
OUTC
Power amplifier output C to motor.
10
CENTERTAP
11
BRAKE
12
CRES
13
FILTER
Analog voltage input to control motor current. Also, compensation node for internal speed
control loop.
14
INDEX
External tachometer input.
15
LOGIC SUPPLY
VDD; the 5 V logic supply.
16
OSCILLATOR
17
DATA OUT
18-19
GROUND
20
RESET
21
CHIP SELECT
22
CLOCK
Clock input for serial port.
23
DATA IN
Sequential data input for the serial port.
24
CD1
Power and logic ground and thermal heat sink.
Motor centertap connection for back-EMF detection circuitry.
Active low turns ON all three sink drivers shorting the motor windings to ground. External
capacitor and resistor at BRAKE provide brake delay. The brake function can also be
controlled via the serial port.
External reservoir capacitor used to hold charge to drive the source drivers’ gates. Also
provides power for brake circuit.
Clock input for the speed reference counter. Typical max. frequency is 10 MHz.
Thermal shutdown indicator, FCOM, TACH, or SYNC signals available in real time,
controlled by 2-bit multiplexer in serial port.
Power and logic ground and thermal heat sink.
When pulled low forces the chip into sleep mode; clears all serial port bits.
Strobe input (active low) for data word.
One of two capacitors used to generate the ideal commutation points from the back-EMF
zero-crossing points.
8905
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
FUNCTIONAL DESCRIPTION
Power Outputs. The power outputs of the
A8905CLB are n-channel DMOS transistors with
a total source plus sink rDS(on) of typically 1.1 Ω.
Internal charge pump boost circuitry provides
voltage above supply for driving the high-side
DMOS gates. Intrinsic ground clamp and flyback
diodes provide protection when switching inductive loads and may be used to rectify motor backEMF in power-down conditions. An external
Schottky power diode or pass FET is required in
series with the load supply to allow motor backEMF rectification in power-down conditions.
Back-EMF zero crossings are indicated by FCOM, an internal signal that
toggles at every zero crossing. FCOM is available at the DATA OUT terminal
via the programmable data out multiplexer.
V
OUTA
V
OUTB
SOURCE ON
Back-EMF Sensing Motor Startup and
Running Algorithm. The A8905CLB provides a
complete self-contained back-EMF sensing startup
and running commutation scheme. The three halfbridge outputs are controlled by a state machine.
There are six possible combinations. In each state,
one output is high (sourcing current), one low
(sinking current), and one is OFF (high impedance
or ‘Z’). Motor back EMF is sensed at the OFF
output. The truth table for the output drivers
sequencing is:
Sequencer
State
OUTA
OUTB
OUTC
1
2
3
4
5
6
High
Z
Low
Low
Z
High
Low
Low
Z
High
High
Z
Z
High
High
Z
Low
Low
V
BACK-EMF VOLTAGE
OUTC
V
SINK ON
CTAP
FCOM TOGGLES AT
BACK-EMF ZERO CROSSING
FCOM
Dwg. WP-016-1
Startup Oscillator. If the motor does not move at the initial startup state,
then it is in a null-torque position. In this case, the outputs are commutated
automatically by the startup oscillator after a period set by the external
capacitor at CST.
VCSTH
VCST
VCSTL
t CST
VCWD
At startup, the outputs are enabled in one of
the sequencer states shown. The back EMF is
examined at the OFF output by comparing the
output voltage to the motor centertap voltage at
CENTERTAP. The motor will then either step
forward, step backward, or remain stationary (if in
a null-torque position). If the motor moves, the
back-EMF detection circuit waits for the correct
polarity back-EMF zero crossing (output crossing
through centertap). True back-EMF zero crossings are used by the adaptive commutation delay
circuit to advance the state sequencer (commutate)
at the proper time to synchronously run the motor.
Dwg. WP-020
where
tCST =
4(VCSTH - VCSTL) x CST
IST(charge) + IST(discharge)
In the next state, the motor will move, back EMF will be detected, and the
motor will accelerate synchronously. Once normal synchronous back-EMF
commutation occurs, the startup oscillator is defeated by pulses of pulldown
current at CST at each commutation, which prevents CST from reaching its
upper threshold and thus completing a cycle and commutating.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8905
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
Adaptive Commutation Delay. The
adaptive commutation delay circuit uses the
back-EMF zero-crossing indicator signal
(FCOM) to determine an optimal commutation
time for efficient synchronous operation. This
circuit commutates the outputs, delayed from the
last zero crossing, using two external timing
capacitors, CD1 and CD2, to measure the time
between crossings.
t FCOM
FCOM
capacitors, the voltage excursion should be 1.5 V to 2.5 V at rated speed.
Solving for C in the equation I = Cdv/dt, where dv = 2.5 V, I = 22 µA, and
20/RPM
dt = tFCOM =
#motor poles
Use of a capacitor slightly greater than this value will ensure that the commutation delay capacitors never charge to the high rail.
Blanking and Watchdog Timing Functions. The blanking and watchdog
timing functions are derived from one timing capacitor, CWD.
VTL x CWD
where
tBLANK =
ICWD
VTH x CWD
ICWD
The CWD capacitor begins charging at each commutation, initiating the
BLANK signal. BLANK is an internal signal that inhibits the back-EMF
comparators during the commutation transients, preventing errors due to
inductive recovery and voltage settling transients.
tWD =
and
VCWD
tCD1
VCD1
V TL
V CWD
t CD2
t BLANK
VCD2
BLANK
Dwg. WP-016-2
Dwg. WP-022
where
tCD = tFCOM x
NORMAL COMMUTATION
ICD(charge),
[ICD(discharge)]
CD1 charges up with a fixed current from its
2.5 V reference while FCOM is high. When
FCOM goes low at the next zero crossing, CD1 is
discharged at approximately twice the charging
current. When CD1 reaches the CD threshold, a
commutation occurs. CD2 operates similarly
except on the opposite phase of FCOM . Thus
the commutations occur approximately halfway
between zero crossings. The actual delay is
slightly less than halfway to compensate for
electrical delays in the motor, which improves
efficiency.
Because the commutation-delay capacitors
are adaptive in nature, the absolute value and
tolerance is not critical. In choosing these
VTH
V TL
V CWD
t BLANK
BLANK
t WD
Dwg. WP-021
WATCHDOG-TRIGGERED COMMUTATION
8905
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
The watchdog timing function allows time to detect correct motor position
by checking the back-EMF polarity after each commutation. If the correct
polarity is not observed between tBLANK and tWD, then the watchdog timer
commutates the outputs to the next state to synchronize the motor. This
function is useful in preventing excessive reverse rotation, and helps in
resynchronizing (or starting) with a moving spindle.
Current Control. The A8905CLB provides linear current control via the
FILTER terminal, an analog voltage input. Maximum current limit is also
provided, and is controlled in four steps via the serial port. Output current is
sensed via an internal sense resistor (RS). The voltage across the sense resistor
is compared to one-tenth the voltage at the FILTER terminal less two diode
drops, or to the maximum current limit reference, whichever is lower. This
transconductance function is IOUT = (VFILTER -2VD) / 10RS, where RS is
nominally 0.3 Ω and VD is approximately 0.7 V.
YANK
POWER UP
S
ERROR FAST
FROM FLL
R
SEQUENTIAL
LOGIC
Q
C RES
SPEED-CONTROL
INITIALIZATION
V DD
OUT
MUX
–
FILTER
+
C F1
–
x1
Id
VI max
–
1.85 V
C F2
RF1
÷10
+
Ic
FROM
SERIAL PORT
REGISTER
D3 AND D4
CHARGE
PUMP
ERROR FAST
Dwg. EP-046
Speed Control. The A8905CLB includes a frequency-locked loop speed
control system. This system monitors motor speed via internal or external
digital tachometer signals, generates a precision speed reference, determines
the digital speed error, and corrects the motor current via an internal charge
pump and external filtering components on the FILTER terminal.
SECTOR
FCOM
COUNT
(3 x MOTOR POLES)
D20 &
D21
MUX
÷2
TACH
ONCE-AROUND
PULSE
D19
REF
TACH
SERIAL PORT
REGISTER
ERROR
SLOW
D5–D18
REF
OSC
4-BIT
FIXED
COUNTER
14-BIT
PROGRAMMABLE
COUNTER
TACH
REF
=
60 x fOSC
desired motor speed (rpm)
where the total count (number of oscillator cycles)
is equal to the sum of the selected (programmed
low) count numbers corresponding to bits D5
through D18.
The speed error is detected as the difference
in falling edges of TACH and REF. The speed
error signals control the error-correcting charge
pump on the FILTER terminal, which drive the
external loop compensation components to correct
the motor current.
RS
LINEAR
CURRENT CONTROL
+
desired
total count
VBB
BOOST
CHARGE
PUMP
V DD
ERROR SLOW
FROM FLL
A once-per-revolution TACH signal can be
generated by counting cycles of FCOM (the
number of motor poles must be selected via the
serial port). TACH is then a jitter-free signal that
toggles once per motor revolution. The rising
edge of TACH triggers REF, a precision speed
reference derived by a programmable counter.
The duration of REF is set by programming the
counter to count the desired number of OSC
cycles
ERROR
FAST
Dwg. EP-045
Index. An external tachometer signal may be
used to create the TACH signal, rather than the
internally derived once around. To use this mode,
the signal is input to the INDEX terminal, and the
index mode must be enabled via the serial port.
When Switching from the once-around mode to
index mode, it is important to monitor the SYNC
signal on DATA OUT, and switch modes only
when SYNC is low. This ensures making the
transition without disturbing the speed control
loop. The speed reference counter should be
reprogrammed at the same time.
Speed Loop Initialization (YANK). To
improve the acquire time of the speed control
loop, there is an automatic feature controlled by an
internal YANK signal. The motor is started at the
maximized programmed current by bypassing the
FILTER terminal. The FILTER terminal is
clamped to two diodes above ground, initializing it
near the closed loop operating point. YANK is
enabled at startup and stays high until the desired
speed is reached. Once the first error-fast occurs,
indicating the motor crossed through the desired
speed, YANK goes low. This releases the clamp
on the FILTER terminal and current control is
returned to FILTER. This feature optimizes speed
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8905
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
acquire and minimizes settling. The Current Control Block Diagram illustrates
the YANK signal and its effects.
Braking. A dynamic braking feature of the A8905CLB shorts the three
motor windings to ground. This is accomplished by turning the three source
drivers OFF and the three sink drivers ON. Activation of the brake can be
implemented through the BRAKE input or through the D2 bit in the serial port.
The supply voltage for the brake circuitry is the CRES voltage, allowing the brake
function to remain active after power failure. Power-down braking with delay can
be implemented by using an external RC and other components to control the
brake terminal, as shown. Brake delay can be set using the equation below to
ensure that voice-coil head retract occurs before the spindle motor brake is
activated. Once the brake is activated, due to the inherent capacitive input, the
three sink drivers will remain active until the device is reset.
tBRK = RBCB
BRAKE
FAULT
BRAKE
ACTIVATED
V FAULT – V D
CB
R
VBRK
B
t BRK
Dwg. OP-004
V
Data written into the serial port is latched
and becomes active upon the low-to-high
transition of the CHIP SELECT terminal at the
end of the write cycle. D0 will be the last bit
written to the serial port.
BB
Reset. The RESET terminal (when pulled
low) clears all serial port bits, including the D0
latch, which puts the A8905CLB in the sleep
mode.
BYPASS
1
C D2
CWD
C ST
VBB
COMMUTATION
DELAY
CB
22
CLOCK
21
CHIP SELECT
5
20
RESET
6
19
7
18
3
4
0.22 µF
TYPICAL
APPLICATION
BYPASS
8
MUX
17
DATA OUT
99
FLL
16
OSC (REF)
11
12
CRES
CD1
DATA IN
VDD
10
RB
24
23
2
SERIAL PORT
VRET
FAULT
Serial Port. The serial port functions to
write various operational and diagnostic modes
to the A8905CLB. The serial port DATA IN is
enabled/disabled by the CHIP SELECT
terminal. When CHIP SELECT is high the
serial port is disabled and the chip is not
affected by changes in data at the DATA IN or
CLOCK terminals.
To write data to the serial port, the
CLOCK terminal should be low prior to the
CHIP SELECT terminal going low. Once
CHIP SELECT goes low, information on the
DATA IN terminal is read into the shift register
on the positive-going transition of the CLOCK.
There are 24 bits in the serial input port.
VBRK
VFAULT - VD
1 – ln
Centertap. The A8905CLB internally
simulates the centertap voltage of the motor.
To obtain reliable start-up performance from
motor to motor, the motor centertap should be
connected to this terminal.
BOOST
CHARGE
PUMP
15
+5 V
14
INDEX
R F1
CF1
13
CF2
Dwg. EP-036-1
8905
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
SERIAL PORT BIT DEFINITIONS
D0- Sleep/Run Mode; LOW = Sleep, HIGH = Run
This bit allows the device to be powered down when not in
use.
D19-Speed-control mode switch;
LOW = internal once-around speed signal,
HIGH = external index data.
D1- Step Mode; LOW = Normal Operation, HIGH = Step Only
When in the step-only mode the back-EMF commutation
circuitry is disabled and the power outputs are commutated
by the start-up oscillator. This mode is intended for device
and system testing.
D20 and D21-These bits program the number of motor poles
for the once-around FCOM counter:
D2- Brake; LOW = Run, HIGH = Brake.
D3 and D4-These two bits set the output current limit:
D3
D4
Current Limit
0
0
1
1
0
1
0
1
Saturated
1A
800 mA
600 mA
D5 thru D18-This 14-bit word (active low) programs the
to set desired motor speed.
Bit Number
Count Number
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
16
32
64
128
256
512
1 024
2 048
4 096
8 192
16 384
32 768
65 536
131 072
D20
D21
Motor Poles
0
0
1
1
0
1
0
1
8
–
16
12
D22 and D23-Control the multiplexer for DATA OUT:
REF time
D22
D23
Data Out
0
0
1
1
0
1
0
1
TACH (once around or index)
Thermal Shutdown
SYNC
FCOM
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8905
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
Dimensions in Inches
(for reference only)
24
13
0.0125
0.0091
0.491
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
3
0.050
0.6141
0.5985
0° TO 8
BSC
NOTE 1
NOTE 3
0.0926
0.1043
0.0040 MIN.
Dwg. MA-008-25 in
Dimensions in Millimeters
(controlling dimensions)
24
13
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
3
15.60
15.20
1.27
BSC
0° TO 8
NOTE 1
NOTE 3
2.65
2.35
0.10 MIN.
NOTES: 1. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece.
2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.
Dwg. MA-008-25A mm
8905
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
Allegro MicroSystems, Inc. reserves the right to make, from time
to time, such departures from the detail specifications as may be
required to permit improvements in the design of its products.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no
responsibility for its use; nor for any infringements of patents or
other rights of third parties which may result from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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