A8906: Bidirectional Three-Phase Brushless DC Motor Controller/Driver with Back EMF Sensing

Data Sheet
26301.4
8906
BIDIRECTIONAL 3-PHASE BRUSHLESS DC MOTOR
CONTROLLER/DRIVER WITH BACK-EMF SENSING
T
C
.
U
Y
L
D
N
O
O
R
P E
C
D
E
N
E
U
N ER
I
T
F
N
E
O
R
C
S OR
I
D F
—
LOAD
SUPPLY
1
C D2
2
C WD
3
CST
4
OUTA
COMMUTATION
DELAY
24
C D1
23
DATA IN
22
CLOCK
21
CHIP SELECT
5
20
RESET
GROUND
6
19
GROUND
GROUND
7
18
GROUND
OUT B
8
MUX
17
DATA OUT
OUT C
99
FLL
16
OSCILLATOR
CENTERTAP
10
15
LOGIC
SUPPLY
BRAKE
11
14
SECTOR
DATA
C RES
12
13
FILTER
SERIAL PORT
V BB
VDD
BOOST
CHARGE
PUMP
The A8906CLB is a bidirectional three-phase brushless dc motor
controller/driver. The three half-bridge outputs are low on-resistance nchannel DMOS devices capable of driving up to 1 A. The A8906CLB
provides complete, reliable, self-contained back-EMF sensing motor
startup and running algorithms. A programmable digital frequencylocked loop speed control circuit together with the linear current control
circuitry provides precise motor speed regulation.
A serial port allows the user to program various features and
modes of operation, such as the speed control parameters, rotational
direction, startup current limit, sleep mode, diagnostic modes, and
others.
The A8906CLB is fabricated in Allegro’s BCD (Bipolar CMOS
DMOS) process, an advanced mixed-signal technology that combines
bipolar, analog and digital CMOS, and DMOS power devices. The
A8906CLB is provided in a 24-lead wide-body SOIC batwing package.
It provides for the smallest possible construction in surface-mount
applications.
PRELIMINARY INFORMATION
Dwg. PP-040B
ABSOLUTE MAXIMUM RATINGS
at TA = +25°C
Load Supply Voltage, VBB . . . . . . . . . . 14 V
Output Current, IOUT . . . . . . . . . . . . ±1.25 A
Logic Supply Voltage, VDD . . . . . . . . . 6.0 V
Logic Input Voltage Range,
VIN . . . . . . . . . . . -0.3 V to VDD + 0.3 V
Package Power Dissipation, PD See Graph
Operating Temperature Range,
TA . . . . . . . . . . . . . . . . . . 0°C to +70°C
Junction Temperature, TJ . . . . . . . +150°C†
Storage Temperature Range,
TS . . . . . . . . . . . . . . . -55°C to +150°C
† Fault conditions that produce excessive junction
temperature will activate device thermal shutdown
circuitry. These conditions can be tolerated, but
should be avoided.
Output current rating may be restricted to a value
determined by system concerns and factors.
These include: system duty cycle and timing,
ambient temperature, and use of any heatsinking
and/or forced cooling. For reliable operation, the
specified maximum junction temperature should
not be exceeded.
FEATURES
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
(Subject to change without notice)
March 1, 1999
DMOS Outputs
Low rDS(on)
Startup Commutation Circuitry
Back-EMF Commutation Circuitry
Direction Control
Serial Port Interface
Frequency-Locked Loop Speed Control
Sector Data Tachometer Signal Input
Programmable Start-Up Current
Diagnostics Mode
Sleep Mode
Linear Current Control
Internal Current Sensing
Dynamic Braking Through Serial Port
Power-Down Dynamic Braking
System Diagnostics Data Out
Data Out Ported in Real Time
Internal Thermal Shutdown Circuitry
Always order by complete part number, e.g., A8906CLB .
8906
BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
FUNCTIONAL BLOCK DIAGRAM
LOGIC
SUPPLY
C D1
C D2
C ST
BRAKE
15
24
2
4
11
C RES
12
VDD
BRAKE
BOOST
CHARGE
PUMP
1
LOAD
SUPPLY
5
OUT A
8
OUT B
9
OUTC
VBB
OUT B
OUT C
CENTERTAP
10
C WD
3
FCOM COMMUTATION
DELAY
SEQUENCE
LOGIC
COMMUTATION
LOGIC
OUT A
START-UP
OSC.
BLANK
WATCHDOG
TIMER
SECTOR
14
DATA
23
SERIAL PORT
CLOCK
CHIP
SELECT
ALLOWABLE PACKAGE POWER DISSIPATION in WATTS
MUX
20
22
21
CURRENT
CONTROL
CHARGE
PUMP
17
DATA
OUT
DATA IN
FREQUENCYLOCKED LOOP
RESET
OSC 16
RS
1.5
R θJA = 55°C/W
0.5
0
75
100
TEMPERATURE in °C
125
GROUND
Dwg. FP-034
RθJT = 6°C/W
50
18-19
FILTER
2.0
25
GROUND
13
2.5
1.0
6-7
TSD
150
Dwg. GP-019B
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1999 Allegro MicroSystems, Inc.
8906
BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5.0 V
Limits
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Logic Supply Voltage
VDD
Operating
4.5
5.0
5.5
V
Logic Supply Current
IDD
Operating
—
7.5
10
mA
Sleep Mode
—
250
500
µA
Operating
4.0
—
14
V
TJ
—
165
—
°C
∆TJ
—
20
—
°C
VBB = 14 V, VOUT = 14 V
—
1.0
300
µA
VBB = 14 V, VOUT = 0 V
—
-1.0
-300
µA
IOUT = 600 mA
—
1.0
1.4
Ω
VBB = 14 V, IOUT = IOUT(MAX), L = 3 mH
14
—
—
V
IF = 1.0 A
—
1.25
1.5
V
Load Supply Voltage
Thermal Shutdown
Thermal Shutdown Hysteresis
VBB
Output Drivers
Output Leakage Current
Total Output ON Resistance
(Source + Sink + RS)
Output Sustaining Voltage
Clamp Diode Forward Voltage
IDSX
rDS(on)
VDS(sus)
VF
Control Logic
Logic Input Voltage
Logic Input Current
DATA Output Voltage
CST Current
VIN(0)
SECTOR DATA, RESET, CLK,
-0.3
—
1.5
V
VIN(1)
CHIP SELECT, OSC
3.5
—
5.3
V
IIN(0)
VIN = 0 V
—
—
-0.5
µA
IIN(1)
VIN = 5.0 V
—
—
1.0
µA
VOUT(0)
IOUT = 500 µA
—
—
1.5
V
VOUT(1)
IOUT = -500 µA
3.5
—
—
V
Charging
-9.0
-10
-11
µA
—
500
—
µA
VCSTH
2.25
2.5
2.75
V
VCSTL
0.85
1.0
1.15
V
Charging
-9.0
-10
-11
µA
Discharging
9.0
10
11
µA
Leakage, VFILTER = 2.5 V
—
—
5.0
nA
1.57
1.85
2.13
V
Charging
-18
-20
-22
µA
Discharging
32
40
48
µA
ICD(DISCHRG)/ICD(CHRG)
1.8
2.0
2.2
—
2.25
2.5
2.75
V
ICST
Discharging
CST Threshold
Filter Current
Filter Threshold
CD Current
IFILTER
VFILTERTH
ICD
(CD1 or CD2)
CD Current Matching
CD Threshold
—
VCDTH
Continued next page …
8906
BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
ELECTRICAL CHARACTERISTICS continued
Limits
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Units
-9.0
-10
-11
µA
CWD Current
ICWD
CWD Threshold Voltage
VTL
0.22
0.25
0.28
V
VTH
2.25
2.5
2.75
V
VDD = 5.0 V, TA = 25°C
12
—
—
MHz
D3 = 0, D4 = 0
1.0
1.2
1.4
A
D3 = 0, D4 = 1
0.9
1.0
1.1
A
D3 = 1, D4 = 0
0.5
0.6
0.7
A
D3 = 1, D4 = 1
—
250
—
mA
1.5
1.75
2.0
V
—
20
—
µA
Max. FLL Oscillator Frequency
IOUT(MAX)
Charging
fOSC
—
BRAKE Threshold
VBRK
BRAKE Hysteresis Current
IBRKL
VBRK = 750 mV
Transconductance Gain
gm
0.42
0.50
0.58
A/V
Centertap Resistors
RCT
5.0
10
13
kΩ
VBEMF - VCTAP at
5.0
20
37
mV
FCOM Transition
-5.0
-20
-37
mV
Back-EMF Hysteresis
—
SERIAL PORT TIMING CONDITIONS
CHIP SELECT
E
A
B
CLOCK
C
D
C
D
DATA
Dwg. WP-019
A. Minimum CHIP SELECT setup time before CLOCK rising edge .......... 100 ns
B. Minimum CHIP SELECT hold time after CLOCK rising edge ............... 150 ns
C. Minimum DATA setup time before CLOCK rising edge ........................ 150 ns
D. Minimum DATA hold time after CLOCK rising edge ............................. 150 ns
E. Minimum CLOCK low time before CHIP SELECT .................................. 50 ns
F. Maximum CLOCK frequency .............................................................. 3.3 MHz
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8906
BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
TERMINAL FUNCTIONS
Term.
Terminal Name
Function
1
LOAD SUPPLY
VBB; the 5 V or 12 V motor supply.
2
CD2
One of two capacitors used to generate the ideal commutation points from the
back-EMF zero crossing points.
3
CWD
Timing capacitor used by the watchdog circuit to disable the back-EMF comparators during commutation transients, and to detect incorrect motor position.
4
CST
Startup oscillator timing capacitor.
5
OUTA
Power amplifier A output to motor.
6-7
GROUND
8
OUTB
Power amplifier B output to motor.
9
OUTC
Power amplifier C output to motor.
10
CENTERTAP
11
BRAKE
12
CRES
External reservoir capacitor used to hold charge to drive the source drivers’
gates. Also provides power for brake circuit.
13
FILTER
Analog voltage input to control motor current. Also, compensation node for
internal speed control loop.
14
SECTOR DATA
External tachometer input. Can use sector or index pulses from disk to provide
precise motor speed feedback to internal frequency-locked loop.
15
LOGIC SUPPLY
VDD; the 5 V logic supply.
16
OSCILLATOR
17
DATA OUT
18-19
GROUND
20
RESET
21
CHIP SELECT
22
CLOCK
Clock input for serial port.
23
DATA IN
Sequential data input for the serial port.
24
CD1
Power and logic ground and thermal heat sink.
Motor centertap connection for back-EMF detection circuitry.
Active low turns ON all three sink drivers shorting the motor windings to ground.
External capacitor and resistor at BRAKE provide brake delay.
Clock input for the speed reference counter. Typical max. frequency is 10 MHz.
Thermal shutdown indicator, FCOM, TACH, or SYNC signals available in real
time, controlled by 2-bit multiplexer in serial port.
Power and logic ground and thermal heat sink.
When pulled low forces the chip into sleep mode; clears all serial port bits.
Strobe input (active low) for data word.
One of two capacitors used to generate the ideal commutation points from the
back-EMF zero crossing points.
8906
BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
FUNCTIONAL DESCRIPTION
Power Outputs. The power outputs of
the A8906CLB are n-channel DMOS transistors with a total source plus sink rDS(on) of
typically 1 Ω. Internal charge pump boost
circuitry provides voltage above supply for
driving the high-side DMOS gates. Intrinsic
ground clamp and flyback diodes provide
protection when switching inductive loads and
may be used to rectify motor back-EMF in
power-down conditions. An external Schottky
power diode or pass FET is required in series
with the load supply to allow motor back-EMF
rectification in power down conditions.
Back-EMF Sensing Motor Startup and
Running Algorithm. The A8906CLB provides a complete self-contained back-EMF
sensing startup and running commutation
scheme. The three half-bridge outputs are
controlled by a state machine. There are six
possible combinations. In each state, one
output is high (sourcing current), one low
(sinking current), and one is OFF (high
impedance or ‘Z’). Motor back EMF is sensed
at the OFF output. The truth table for the
output drivers sequencing is:
D2 Low
D2 High
Direction
Control
OUTA
OUTB
OUTC
High
Z
Low
Low
Z
High
Low
Low
Z
High
High
Z
Z
High
High
Z
Low
Low
At startup, the outputs are enabled in one
of the sequencer states shown. The back
EMF is examined at the OFF output by
comparing the output voltage to the motor
centertap voltage at CENTERTAP. The
motor will then either step forward, step
backward, or remain stationary (if in a nulltorque position). If the motor moves, the
back-EMF detection circuit waits for the
correct polarity back-EMF zero crossing
(output crossing through centertap). True back-EMF zero crossings are
used by the adaptive commutation delay circuit to advance the state
sequencer (commutate) at the proper time to synchronously run the
motor. Back-EMF zero crossings are indicated by FCOM, an internal
signal that toggles at every zero crossing. FCOM is available at the
DATA OUT terminal via the programmable data out multiplexer.
V
OUTA
V
OUTB
SOURCE ON
V
BACK-EMF VOLTAGE
OUTC
V
SINK ON
CTAP
FCOM TOGGLES AT
BACK-EMF ZERO CROSSING
FCOM
Dwg. WP-016-1
Direction Control. Serial port bit D2 controls the direction of
rotation (see sequencer state table). The motor should be at a complete stop before beginning a startup sequence that reverses the
direction of rotation.
Startup Oscillator. If the motor does not move at the initial startup
state, then it is in a null-torque position. In this case, the outputs are
commutated automatically by the startup oscillator after a period set by
the external capacitor at CST where
tCST =
4(VCSTH - VCSTL) x CST
IST(charge) + IST(discharge)
In the next state, the motor will move, back EMF will be detected,
and the motor will accelerate synchronously. Once normal synchronous back-EMF commutation occurs, the startup oscillator is defeated
by pulses of pulldown current at CST at each commutation, which
prevents CST from reaching its upper threshold and thus completing a
cycle and commutating.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8906
BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
Adaptive Commutation Delay. The
adaptive commutation delay circuit uses the
back-EMF zero-crossing indicator signal
(FCOM) to determine an optimal commutation time for efficient synchronous operation.
This circuit commutates the outputs, delayed
from the last zero crossing, using two
external timing capacitors, CD1 and CD2,
Blanking and Watchdog Timing Functions. The blanking and
watchdog timing functions are derived from one timing capacitor, CWD.
VTL x CWD
where
tBLANK =
ICWD
and
tWD =
VTH x CWD
ICWD
The CWD capacitor begins charging at each commutation, initiating
the BLANK signal. BLANK is an internal signal that inhibits the backEMF comparators during the commutation transients, preventing errors
due to inductive recovery and voltage settling transients.
t FCOM
FCOM
The watchdog timing function allows time to detect correct motor
position by checking the back-EMF polarity after each commutation. If
the correct polarity is not observed between tBLANK and tWD, then the
watchdog timer commutates the outputs to the next state to synchronize the motor. This function is useful in preventing excessive reverse
rotation, and helps in resynchronizing (or starting) with a moving
spindle.
VCWD
tCD1
VCD1
t CD2
V TL
V CWD
VCD2
t BLANK
BLANK
Dwg. WP-016-2
Dwg. WP-022
to measure the time between crossings.
ICD(charge)
where
tCD = tFCOM x
ICD(discharge)
CD1 charges up with a fixed current from
its 2.5 V reference while FCOM is high.
When FCOM goes low at the next zero
crossing, CD1 is discharged at approximately
twice the charging current. When CD1
reaches the CD threshold, a commutation
occurs. CD2 operates similarly except on the
opposite phase of FCOM . Thus the commutations occur approximately halfway
between zero crossings. The actual delay is
slightly less than halfway to compensate for
electrical delays in the motor, which improves efficiency.
NORMAL COMMUTATION
VTH
V TL
V CWD
t BLANK
BLANK
t WD
Dwg. WP-021
WATCHDOG-TRIGGERED
COMMUTATION
8906
BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
Current Control. The A8906CLB provides linear current control
via the FILTER terminal, an analog voltage input. Maximum current
limit is also provided, and is controlled in four steps via the serial port.
Output current is sensed via an internal sense resistor (RS). The
voltage across the sense resistor is compared to one-tenth the voltage
at the FILTER terminal less the filter threshold voltage, or to the maximum current limit reference, whichever is lower. This transconductance function is IOUT = (VFILTER -VFILTERTH) / 10RS, where RS is
nominally 0.2 Ω and VFILTERTH is approximately 1.85 V.
YANK
POWER UP
S
ERROR FAST
FROM FLL
R
SEQUENTIAL
LOGIC
Q
C RES
SPEED-CONTROL
INITIALIZATION
V DD
V DD
Ic
–
FILTER
+
–
x1
Id
VI max
–
C
÷10
MUX
C F1
1.85 V
F2
LINEAR
CURRENT CONTROL
+
RS
FROM
SERIAL PORT
REGISTER
D3 AND D4
CHARGE
PUMP
ERROR FAST
FROM FLL
MAX CURRENT LIMIT
Dwg. EP-046
Speed Control. The A8906CLB includes a frequency-locked loop
speed control system. This system monitors motor speed via internal
or external digital tachometer signals, generates a precision speed
reference, determines the digital speed error, and corrects the motor
current via an internal charge pump and external filtering components
on the FILTER terminal.
A once per revolution TACH signal can be generated by counting
cycles of FCOM (the number of motor poles must be selected via the
serial port). TACH is then a jitter-free signal that toggles once per
motor revolution. The rising edge of TACH triggers REF, a precision
speed reference derived by a programmable counter. The duration of
REF is set by programming the counter to count the desired number of
OSC cycles
SECTOR
FCOM
COUNT
(3 x MOTOR POLES)
D20 &
D21
MUX
÷2
TACH
ONCE-AROUND
PULSE
D19
REF
TACH
SERIAL PORT
REGISTER
ERROR
SLOW
D5–D18
REF
OSC
4-BIT
FIXED
COUNTER
14-BIT
PROGRAMMABLE
COUNTER
The speed error is detected as the
difference in falling edges of TACH and
REF. The speed error signals control the
error-correcting charge pump on the FILTER
terminal, which drive the external loop compensation components to correct the motor
current.
OUT
+
ERROR SLOW
FROM FLL
RF1
VBB
BOOST
CHARGE
PUMP
60 x fOSC
desired
=
total count
desired motor speed (rpm)
where the total count (number of oscillator
cycles) is equal to the sum of the selected
(programmed low) count numbers corresponding to bits D5 through D18.
TACH
REF
Sector Mode. An external tachometer
signal, such as sector or index pulses, may
be used to create the TACH signal, rather
than the internally derived once around. To
use this mode, the signal is input to the
SECTOR terminal, and the sector mode must
be enabled via the serial port. When Switching from the once-around mode to sector
mode, it is important to monitor the SYNC
signal on DATA OUT, and switch modes only
when SYNC is low. This ensures making the
transition without disturbing the speed control
loop. The speed reference counter should be
reprogrammed at the same time.
Speed Loop Initialization (YANK). To
improve the acquire time of the speed control
loop, there is an automatic feature controlled
by an internal YANK signal. The motor is
started at the maximized programmed current
by bypassing the FILTER terminal. The
FILTER terminal is clamped to an internal
reference (the filter threshold voltage),
initializing it near the closed loop operating
point. YANK is enabled at startup and stays
high until the desired speed is reached. Once
the first error-fast occurs, indicating the motor
crossed through the desired speed, YANK
goes low. This releases the clamp on the
FILTER terminal and current control is
returned to FILTER. This feature optimizes
speed acquire and minimizes settling. The
Current Control Block Diagram illustrates the
YANK signal and its effects.
ERROR
FAST
Dwg. EP-045
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8906
BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
Serial Port. The serial port functions to write various operational
and diagnostic modes to the A8906CLB. The serial port DATA IN is
enabled/disabled by the CHIP SELECT terminal. When CHIP SELECT is high the serial port is disabled and the chip is not affected by
changes in data at the DATA IN or CLOCK terminals.
Bit Number
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
To write data to the serial port, the CLOCK terminal should be low
prior to the CHIP SELECT terminal going low. Once CHIP SELECT
goes low, information on the DATA IN terminal is read into the shift
register on the positive-going transition of the CLOCK. There are 24
bits in the serial input port.
Data written into the serial port is latched and becomes active
upon the low-to-high transition of the CHIP SELECT terminal at the
end of the write cycle. D0 will be the last bit written to the serial port.
SERIAL PORT BIT DEFINITIONS
D0 - Sleep/Run Mode; LOW = Sleep, HIGH = Run
This bit allows the device to be powered down when not in use.
D1 - Step Mode; LOW = Normal Operation, HIGH = Step Only
When in the step-only mode the back-EMF commutation circuitry
is disabled and the power outputs are commutated by the startup oscillator. This mode is intended for device and system
testing.
D20 and D21 - These bits program the number
of motor poles for the once-around FCOM
counter:
D3 and D4 - These two bits set the output current limit:
D4
Current Limit
0
0
1
1
0
1
0
1
1.2 A
1A
600 mA
250 mA
D5 thru D18 - This 14-bit word (active low) programs the REF time to set
desired motor speed.
16
32
64
128
256
512
1 024
2 048
4 096
8 192
16 384
32 768
65 536
131 072
D19 - Speed-control mode switch;
LOW = internal once-around speed signal,
HIGH = external sector data.
D2 - Direction; LOW = Forward, HIGH = Reverse.
D3
Count Number
D20
D21
Motor Poles
0
0
1
1
0
1
0
1
8
4
16
12
D22 and D23 - Controls the multiplexer for
DATA OUT:
D22
D23
DATA OUT
0
0
1
1
0
1
0
1
TACH (once around or sector)
Thermal Shutdown
SYNC
FCOM
Reset. The RESET terminal when pulled
low clears all serial port bits, including the D0
latch, which puts the A8906CLB in the sleep
mode.
8906
BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
BRAKE
FAULT
V FAULT
inherent capacitive input, the three sink
drivers will remain active until the device is
reset.
BRAKE
ACTIVATED
– VD
CB
R
VBRK
B
t BRK
tBRK = RBCB
VBRK
1 – ln V
FAULT - VD
Dwg. OP-004
Centertap. The A8906CLB internally
simulates the centertap voltage of the motor.
To obtain reliable start-up performance from
motor to motor, the motor centertap should be
connected to this terminal.
Braking. A dynamic braking feature of the A8906CLB shorts the
three motor windings to ground. This is accomplished by turning the
three source drivers OFF and the three sink drivers ON. Activation of
the brake can be implemented through the BRAKE input. The supply
voltage for the brake circuitry is the CRES voltage, allowing the brake
function to remain active after power failure. Power-down braking with
delay can be implemented by using an external RC and other components to control the brake terminal, as shown. Brake delay can be set
using the equation below. Once the brake is activated, due to the
External Component Selection. Applications information regarding the selection of
external component values is available from
the factory for external component selection,
frequency-locked loop speed control, and
commutation delay capacitor selection.
TYPICAL APPLICATION
V
BB
BYPASS
1
C D2
CWD
C ST
VBB
COMMUTATION
DELAY
CB
RB
22
CLOCK
21
CHIP SELECT
5
20
RESET
6
19
7
18
3
4
BYPASS
8
MUX
17
DATA OUT
99
FLL
16
OSC (REF)
11
12
CRES
0.22 µF
CD1
DATA IN
VDD
10
FAULT
24
23
2
SERIAL PORT
VRET
BOOST
CHARGE
PUMP
15
+5 V
R F1
14
CF1
SECTOR
DATA
13
CF2
Dwg. EP-036C
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8906
BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
Dimensions in Inches
(for reference only)
24
13
0.0125
0.0091
0.491
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
3
0.050
0.6141
0.5985
0° TO 8
BSC
NOTE 1
NOTE 3
0.0926
0.1043
0.0040 MIN.
Dwg. MA-008-25 in
Dimensions in Millimeters
(controlling dimensions)
24
13
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
3
15.60
15.20
1.27
BSC
0° TO 8
NOTE 1
NOTE 3
2.65
2.35
0.10 MIN.
Dwg. MA-008-25A mm
NOTES: 1. Webbed lead frame. Leads 6, 7, 18, and 19 are internally one piece.
2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.
8906
BIDIRECTIONAL
3-PHASE BRUSHLESS DC
MOTOR CONTROLLER/DRIVER
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be required
to permit improvements in the design of its products.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third
parties which may result from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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