A8481: Dual Output Boost Regulator Using Single Inductor

A8481
Dual Output Boost Regulator Using Single Inductor
Discontinued Product
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: November 2, 2009
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A8481
Dual Output Boost Regulator Using Single Inductor
Features and Benefits
Description
▪
▪
▪
▪
The A8481 is a step-up dc-to-dc converter in a thermallyenhanced MLP package. A constant 1.2 MHz switching
frequency, with current-mode control scheme, provides stable
low-noise operation at high load conditions.
▪
▪
▪
▪
Two independently controlled channels for dual display
Output voltage up to 23 V
2.7 to 9 V input
Output disconnect allows less than 1 μA supply current
during shutdown
Single-pin dimming control for WLED
1.2 MHz switching frequency
1.5 A switch current limit
OVP, Pulse-by-Pulse OCP, OTP, and Soft Start
The A8481 is a dual output OLED + WLED driver. This device
is suitable for driving OLED bias supply as well as WLEDs
for backlight. For OLED it is capable of delivering 80 mA at
18 V, and can drive five WLEDs at 20 mA.
Independent output control and output disconnect make this
IC ideally suited for battery operated, dual display portable
applications. The IC disconnects input from the output path
during shutdown, allowing shutdown currents less than 1 μA.
Package: 10 pin MLP/DFN (suffix EJ) with
exposed thermal pad
The A8481 is available in a 10-pin 3 mm × 3 mm MLP package
that has a nominal height of only 0.75 mm.
Applications include:
▪ Dual-panel cellular phone with OLED and
WLED backlight
▪ Personal Digital Assistant (PDA)
▪ Camcorder, personal stereo, MP3 player, camera
Approximate Scale 1:1
Typical Applications
Additional applications on page 11
VOUT
L1
1
CIN
2
3
VSUPPLY
4
VIN
A8481
OUT2
ON2
SW
CAP
OUT1
ISET
ON1
10
1
COUT
CIN
9
8
2
3
VSUPPLY
4
7
R1
6
5
D1
GND
SW
FB1
CAP
VIN
A8481
OUT1
OUT2
ISET
ON2
ON1
10
COUT
9
8
7
R1
6
RSET
R2
Figure 1a. Typical application circuit for A8481
driving OLED and three WLEDs
8481-DS, Rev. 2
OLED
OLED
5
D1
GND
FB1
VOUT
L1
RP
PWM
Q1
RSET
R2
Figure 1b. OUT2 current dimming with PWM on
ISET pin, with parallel resistor
A8481
Dual Output Boost Regulator Using Single Inductor
Functional Block Diagram
SW
VIN
S1
C4
0.6 V
R
Q
Driver
S
C5
FB1
0.3 V
OUT2
Soft
Start
Select MIN
and
Error Amplifier
∑
C1
Ramp
C3
Oscillator
Clock
FB1
CAP
VCAP
UVLO
Temp
Fault
Protection
S2
C2
VREF1
ON1
On/Off
Logic
ON2
OUT1
0.6 V
OUT2
Current Regulator
ISET
IREF
S3
Decoder
ISET
GND
Absolute Maximum Ratings
Package Thermal Characteristics
Input or Output Voltage
SW, CAP, OUT1, OUT2 pins ..................................–0.3 to 26 V
VIN pin, VIN ............................................................–0.3 to 9.5 V
All other pins, Vx ....................... –0.3 to VIN + 0.3 V (7 V max.)
Operating Ambient Temperature, TA ................................ –40°C to 85°C
Maximum Junction Temperature, TJ(max) ...................................... 150°C
Storage Temperature, TS .............................................. –55°C to 150°C
RθJA = 45 °C/W, on a 4-layer board. Additional information is
available on the Allegro Web site.
Ordering Information
Use the following complete part numbers when ordering:
Part Number
Packinga
A8481EEJTR-Tb
7-in. reel, 1500 pieces/reel
aContact Allegro
bLead
Description
EJ package, MLP/DFN(SON) leadless surface mount
with exposed thermal pad
for additional packing options.
(Pb) free, with leadframe plating 100% matte tin.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A8481
Dual Output Boost Regulator Using Single Inductor
Pin-out Diagram
GND
1
10
SW
FB1
2
9
CAP
VIN
3
8
OUT1
OUT2
4
7
ISET
ON2
5
6
ON1
PAD
(Top View)
Number
Name
1
GND
Power ground and signal ground reference; connect directly to the ground plane.
Description
2
FB1
This is the feedback pin for controlling voltage on the OUT1 pin. The nominal reference
voltage on this pin is 600 mV. In order to minimize noise, connect the feedback resistor
network close to this pin.
3
VIN
This is the power input supply connection to the circuit. A bypass capacitor tying this pin
to GND must be connected close to this pin.
4
OUT2
This is the current sink pin for the WLED supply. The load current through this pin can be
controlled through the ISET pin or the ON2 pin.
5
ON2
This is the enable pin for OUT2. This pin is also used for the serial input interface to
control the OUT2 current.
6
ON1
This is the enable pin for OUT1.
7
ISET
This pin is used to set load current through the OUT2 pin.
8
OUT1
This is the voltage-controlled pin for the OLED drive. An internal switch disconnects the
OLED during shutdown.
9
CAP
This is the connection to the output capacitor for the boost regulator output.
10
SW
This is the connection between the internal boost switch and the external inductor.
Because rapid changes of current occur at this pin, the board traces connected to this pin
should be minimized and the inductor and diode should be connected as close to this pin
as possible.
–
Pad
Exposed thermal pad. Connect to GND plane for enhanced thermal performance.
Operation State Control Truth Table
Pin
State Description
ON1
ON2
0
0
IC shutdown. Total input current from VIN is < 1 μA.
0
1
OUT2 on, OUT1 off. Boost stage is controlled to regulate OUT2 current with switch S2
off.
1
0
OUT1 on, OUT2 off. Boost stage is controlled to regulate OUT1 voltage and to turn
switch S3 off.
1
1
OUT2 and OUT1 on. Boost stage is controlled such that voltage on the CAP pin is
sufficient to bias OUT1 and OUT2.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A8481
Dual Output Boost Regulator Using Single Inductor
ELECTRICAL CHARACTERISTICS at TA = 25°C, VIN = ON1 = ON2 = 3.0 V, RSET = 30 kΩ (unless noted otherwise)
Characteristics
Input Voltage Range
Symbol
Undervoltage Lockout Threshold
Feedback Reference Voltage
VUVLO
Feedback Input Current
Switch Current Limit
Switch Frequency
Cycle*
Switch S1 On Resistance
VIN rising
VFB
2.7 V ≤ VIN ≤ 9 V
Feedback Voltage Line Regulation
Switch Maximum Duty
Test Conditions
VIN
Min.
Typ.
Max.
Units
2.7
–
9
V
2.25
2.45
2.60
V
584
610
636
mV
–
0.1
–
%/V
IFB
–
45
100
nA
ISWLim
–
1.5
–
A
fSW
1
1.2
1.4
MHz
DC
RDS1(on)
85
90
–
%
ISW = 0.5 A
–
225
–
mΩ
Switch Leakage Current
ILSW
VSW = 5 V
–
–
1
μA
Quiescent Input Current
IIN(Q)
ON1 = ON2 = 0 V
–
–
1
μA
–
0.4
V
ON1, ON2 Logic Input Levels
Input Threshold Low
VIL
–
Input Threshold High
VIH
1.5
–
–
V
IL
–
65
–
μA
VOVPR
–
24.5
25.5
V
890
1000
1110
A/A
Input Leakage
Overvoltage Protection
Output Overvoltage Rising Limit
ISET to IOUT2 Current Gain
ASET
ISET = 10 μA
ISET Pin Voltage
VSET
–
0.6
–
V
ISET Current Range
ISET
1
–
20
μA
ON2 Serial Pulse Timing
ON2 Pulse Low Time
tLO
0.5
–
20
μs
ON2 Pulse High Time
tHI
0.5
–
–
μs
Initial ON2 Pulse High Time
tHII
First ON2 pulse after shutdown
1
–
–
ms
Falling edge on ON2
–
1
2
ms
–
160
–
(°)
–
10
–
(°)
–
2
–
ms
Shut Down Delay
tSHDN
Thermal Shutdown Threshold
TSHDN
Thermal Shutdown Hysteresis
TSHDNhys
Soft-Start Period
tSS
VOUT = 10 V
*Guaranteed by design.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
Dual Output Boost Regulator Using Single Inductor
Performance Characteristics
Tests performed using application circuit shown in figure 1(a)
L1 = 4.7 μH, CIN = COUT = 1 μF, TA = 25°C, VIN = 3 V (unless otherwise noted)
Efficiency with OUT1 off, OUT2 on, 5 WLEDs
Over range of dimming levels, LED voltage drop at 20 mA = 16.3 V
85
80
20 mA (Full Brightness)
75
12 mA
η (%)
70
Dimming Level
(mA)
4 mA
65
60
55
50
45
2
4
6
8
10
VIN (V)
Efficiency with OUT2 on, OUT1 off, 3 WLEDs
Over range of dimming levels, LED voltage drop at 20 mA = 9 V
85
80
20 mA (Full Brightness)
12 mA
75
η (%)
70
Dimming Level
(mA)
4 mA
65
60
55
50
45
2
4
6
8
10
VIN (V)
Efficiency with OUT1 on, OUT2 off
VOUT1= 16 V
85
80 mA
60 mA
80
40 mA
20 mA
75
10 mA
η (%)
A8481
70
Dimming Level
80 mA = Full Brightness
65
3 mA
60
55
2
4
6
8
10
VIN (V)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A8481
Dual Output Boost Regulator Using Single Inductor
Performance Characteristics
Tests performed using application circuit shown in figure 1(a)
L1 = 4.7 μH, CIN = COUT = 1 μF, TA = 25°C, VIN = 3 V (unless otherwise noted)
OLED Line Regulation
OLED Load Regulation
VOUT1= 16 V
VOUT1= 16 V
16.25
16.25
16.20
16.20
Dimming Level
80 mA = Full Brightness
16.15
16.15
80 mA
16.10
VOUT (V)
VOUT (V)
16.10
60 mA
16.05
40 mA
16.00
10 mA
1 mA
20 mA
8.5 V
16.05
7V
16.00
3 mA
15.95
15.95
15.90
15.90
15.85
15.85
5V
4V
Supply Level, VIN
3.6 V
3V
2.7 V
2
4
6
8
0
10
20
40
60
80
IOUT (mA)
VIN (V)
WLED Startup, 5 LEDs, 20 mA
OLED Startup, 18 V, 80 mA
VON2
C1
VON1
C1
ILED
C2
IIN
C3
VOUT1
C2
IIN
C3
t
Symbol
C1
C2
C3
t
Parameter
VON2
ILED
IIN
time
t
Units/Division
5V
10.0 mA
50 mA
5 ms
Symbol
C1
C2
C3
t
Parameter
VON1
VOUT1
IIN
time
Units/Division
5V
5V
500 mA
5 ms
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A8481
Dual Output Boost Regulator Using Single Inductor
Performance Characteristics
Tests performed using application circuit shown in figure 1(a)
L1 = 4.7 μH, CIN = COUT = 1 μF, TA = 25°C, VIN = 3 V (unless otherwise noted)
OLED (18 V, 80 mA) and WLED (5 LEDs, 20 mA)
Simultaneous startup and shutdown
Symbol
C1
C2
C3
C4
t
Parameter
VOUT1
VCAP
VOUT2
IIN
time
VOUT1
Units/Division
3V
3V
3V
200 mA
5 ms
VCAP
IIN
IIN
C4
VCAP
VOUT2
C2
VOUT1 , VOUT2
C1, C3
t
Serial Dimming Using ON2
20
VON2
18
16
14
IOUT2 (mA)
C1
12
10
8
IOUT2
6
4
C2
2
0
t
Symbol
C1
C2
t
Parameter
VON2
IOUT2
time
0
Units/Division
1V
10 mA
5 ms
1
2
3
4
5
6
7
Step Sequence on Pin ON2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A8481
Dual Output Boost Regulator Using Single Inductor
Functional Description
The A8481 is a dual output converter with two-stage architecture.
The first stage is a boost stage, which boosts input battery voltage
to a sufficient level to drive an OLED or a set of series-connected
WLEDs. This stage uses 1.2 MHz constant frequency, current mode
control. Typical application circuits are shown in figures 1 and 4.
The constant voltage drive for OLED is provided through the
OUT1 pin. The internal switch S2, connected between the CAP
and OUT1 pins, acts as either a switch or as a linear regulator
when OUT1 is on. Switch S2 disconnects the OLED when OUT1
is disabled.
For driving OLEDs, output voltage is sensed by the FB1 pin
through a voltage divider network. Output voltage (V) is set as:
R1 + R2
VOUT1 = 0.6 ×
(1)
R
2
The OUT2 pin provides a constant-current sink for a set of
series-connected WLEDs. It is capable of sinking 20 mA current.
Switch S3 is the current regulator. Current through S3 can be
adjusted by controlling resistor connected to the ISET pin. It can
also be programmed through the ON2 pin.
The IC provides protections against output overvoltage on the
CAP pin, overload, and over temperature. Also, it has an input
undervoltage lockout to avoid malfunction and battery drain.
At light loads, instantaneous inductor current drops to zero. This
is known as discontinuous mode operation and will result in some
low frequency ripple. In discontinuous mode, the voltage at the
SW pin will ring, due to the resonant LC circuit formed by the
inductor and the switch and diode capacitance. This ringing is
low frequency and is not harmful. It can be damped with a resistor across the inductor, but this will reduce efficiency and is not
recommended.
Start-up Sequence
When either or both outputs, OUT1 and OUT2, are enabled and
VIN is greater than VIN (min), the boost stage is ramped-up with
soft start. If only OUT1 is enabled, it controls the boost stage soft
start. OUT2 controls soft start if only OUT2 is enabled.
When only one output is enabled, the corresponding output
switch, S2 or S3, completely turns on. If ON1 and ON2 are both
enabled at start-up, the boost stage is controlled by the channel
that requires greater voltage than the other channel. Both outputs
turn on simultaneously. When both enable signals are low, the
A8481 enters shutdown mode.
During normal operation, if both outputs are enabled and one
output is out of regulation, that output will control the boost loop.
The corresponding output switch will completely turn on and the
other output switch will linearly regulate. For example:
• Case A. If the current through the OUT2 pin falls below 95%
of the set value (ISET multiplied by internal gain), the boost
stage will be controlled by OUT2, such that current through
OUT2 is same as the set value. OUT1 will be regulated through
S2 working as an LDO linear regulator.
• Case B. If the voltage across the FB pin falls below 95% of the
set value, the boost stage will be controlled by OUT1. The current through OUT2 will be controlled through S3 working as
current sink.
WLED Dimming Control
In the A8481, WLED brightness can be controlled by the follwing variety of methods:
• External resistance on the ISET pin
Dimming level can be set by controlling the resistance between
the ISET pin and ground. The resistance between the ISET pin
and ground can be dynamically controlled by switching a parallel
resistor, RP , as shown in figure 1b.
• Serial programming through the ON2 pin
The OUT2 pin current can be adjusted by clocking the ON2
pin to 8 different levels, ranging from 8% to 100% of the level
determined by RSET. An internal digital circuit decodes the clock
signal and sets the current of the OUT2 pin. Figure 2 illustrates
the timing definition of the clock at the ON2 pin. The 8 levels of
serial dimming are shown in the following table.
Pulse
Count
IOUT2
Pulse
Count
IOUT2
0
100%
4
47%
1
87%
5
34%
2
74%
6
21%
3
61%
7
8%
8
100%
The default setting is 100% , which is the OUT2 level when
no clock pulse has been applied. The OUT2 current level is
decreased in steps as each pulse is applied. After the minimum
level is reached, the counter rolls over to 100% again.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A8481
Dual Output Boost Regulator Using Single Inductor
Dimming with serial programming is disabled during startup, for
the initialization period, tHII . When ON2 is pulled low for time
longer than tSHDN, the counter resets.
When changing from one specific dimming level to another,
the user may not want to have to store the latest dimming level.
A simpler method is to program a memory reset and apply the
required number of pulses, from 100% to the target dimming
level. The total “LED off” time during shutdown, reenable, and
dimming level programming can be kept sufficiently short, such
that no delay is discernable to the human eye.
PWM can be applied only after the tHII period. The duty cycle
and frequency range will be limited due to tSHDN. Typically,
PWM control through the range of 0 to 80% can be achieved at
100 Hz PWM frequency.
PWM control via ISET pin
25
20
fPWM (Hz)
ILED (mA)
• PWM Control through the ON2 pin
The average current for the LEDs can be determined by controlling the duty cycle of the LED current using external PWM on
ON2 pin. When the ON2 pin is high, current at the 100% level
flows through the LEDs. When ON2 is low, the LED current is
less than 1 μA.
LED Supply Current versus Duty Cycle
10
5
• PWM Control through the ISET pin
The average current for the LEDs can be controlled with external
PWM on the ISET pin, as shown in figure 4a.
PWM dimming accuracy is shown in figure 3. The PWM
source used had a high level of 3 V and low level of 0 V. Also,
RSET =30 kΩ and RP =100 Ω.
Initial tHII
0
1
2
3
4
5
200
400
1000
15
0
0
20
40
60
80
100
DC (%)
Figure 3. Accuracy of External PWM on ISET
6
7
0
1
2
VON2
tSS
IOUT2
tHI
tLO
100%
87%
74%
61%
tSHDN
100%
47%
SHDN
34%
21%
8%
87%
74%
Memory
Reset
Figure 2. ON2 Clock Timing Definition
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
A8481
Dual Output Boost Regulator Using Single Inductor
Applications Information
Component Selection
rent rating above the circuit maximum.
The component values shown in the application circuits (figures 1
and 4) will be sufficient for most applications. To reduce the
output ripple, the output inductor may be increased in value, but
in most cases this will result in excessive board area and cost.
The diode RMS current rating should be:
⎯⎯
IDIODE(RMS) = IOUT = IIN √ 1–D
Inductor Selection
The inductor is the most important component in the power
supply design because it affects the steady-state performance,
transient response, and loop stability. The inductance value, dc
resistance, and the saturation current should be considered when
choosing the inductor. The dc current of the inductor can be
calculated by:
VOUT IOUT
VIN η
and the inductance value can be calculated by:
IL_DC =
(2)
⎛
⎞
V
1
⎜⎜1 – imin ⎟⎟
(3)
V
f
OUT
⎝
⎠
where ∆i = (20% to 40%) × IL_DC is the peak-to-peak ripple current.
Lmin =
Vimin
∆i η
Smaller inductance values force the converter into discontinuous
mode, which will reduce the maximum output current. Larger
inductance values reduce the gain and phase margin, which will
result in instability of the loop.
The inductor should have low winding resistance, typically < 0.2
Ω and low 1.2 MHz core loss for better efficiency.
The inductor should have a saturation current higher than 1.5 A,
in order to provide 20 V at the OUTx pins, and 100 mA at
2.7 VIN. For high temperature operation, a suitable derating factor
should be considered. Several inductor manufacturers, including:
Coilcraft, Murata, Panasonic, Sumida, Taiyo Yuden, and TDK,
have and are developing suitable small-size inductors.
Diode Selection
The diode should have a low forward voltage to reduce conduction losses and a low capacitance to reduce switching losses.
Schottky diodes can provide both of these features, if carefully
selected. The forward voltage drop is a natural advantage for
Schottky diodes and decreases as the current rating increases.
However, as the current rating increases, the diode capacitance
also increases, so the optimum selection is usually the lowest cur-
.
(4)
Diode PIV should be higher than the output voltage on the CAP
pin.
Capacitor Selection
The input capacitor selection is based on the input voltage ripple.
It can be calculated as:
CIN(min) =
8
f
∆i
VIN(ripple)
(5)
where VIN(ripple) is the input ripple.
The output capacitor selection is based on the output ripple
requirement. It can be calculated by:
COUT =
VOUT –VIN
VOUT
1
f
IOUT
Vripple(pp)
(6)
where Vripple is the peak-to-peak output ripple.
In addition, the ESR-related output ripple can be calculated by:
Vripple(ESR) = IOUT
ESR
.
(7)
If a ceramic capacitor is selected, the ESR-related ripple can be
neglected, due to the low ESR. If a tantalum electrolytic capacitor
is selected, this portion of ripple voltage has to be considered.
During load transient response, a larger output capacitance
always helps to supply or absorb additional current, which results
in lower overshoot and undershoot voltage.
Because the capacitor values are low, ceramic capacitors are the
best choice for this application. To reduce performance variation
over temperature, low drift types such as X7R and X5R should
be used. Recommended specifications are shown in the table
below. Suitable capacitors are available from TDK, Taiyo Yuden,
Murata, Kemet, and AVX.
The output capacitor is placed on the CAP pin only. An additional
capacitor can be added on the OUT1 pin, but it is not needed for
proper operation and it cannot replace the capacitor on the CAP pin.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
A8481
Dual Output Boost Regulator Using Single Inductor
VOUT
1
CIN
GND
2
FB1
3
VSUPPLY
SW
A8481
VIN
4
CAP
OUT1
OUT2
5
VOUT
L1
D1
ISET
ON2
1
COUT
CIN
9
8
2
3
VSUPPLY
7
4
R1
6
5
D1
GND
SW
FB1
CAP
A8481
VIN
OUT1
OUT2
ISET
ON2
ON1
10
COUT
9
8
7
R1
6
OLED
ON1
10
OLED
L1
RP
RSET
RSET
R2
R2
PWM
Figure 4a. OUT2 current dimming with PWM on
ISET pin
Figure 4b. Three WLED and OLED driver
VOUT
1
2
CIN
1 μF
16 V
Li+
Battery
2.7 to 5.5 V
3
4
5
L2 10 μH
GND
FB1
VIN
SW
A8481
CAP
OUT1
OUT2
ISET
ON2
ON1
D0
D1
10
Efficiency versus Input Voltage
D2
77
9
76
75
8
74
COUT
1 μF
50 V
7
D9
6
η (%)
L1 10 μH
73
72
71
70
D10
69
68
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN (V)
R1
30 kΩ
Figure 4c. Ten WLED driver
VOUT
L1
1
CIN
VSUPPLY
2
3
4
5
D0
GND
SW
FB1
CAP
VIN
A8481
OUT2
ON2
OUT1
ISET
ON1
D2
10
VOUT
L1
D1
1
Backlight
D3
9
CIN
COUT
D4
8
VSUPPLY
D6
6
Flash
D7
RSET
3
4
D5
7
2
R2
Figure 4d. Four WLED backlight and three 100 mA
WLED flash driver
5
D0
GND
SW
FB1
CAP
VIN
A8481
OUT1
OUT2
ISET
ON2
ON1
D1
10
Main
9
Dx
COUT
8
Dy
7
6
Sub
Dz
RSET
R2
Figure 4e. WLED Main and WLED sub driver
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
A8481
Dual Output Boost Regulator Using Single Inductor
Package EJ, 10-Pin MLP/DFN
0.30
3.00
0.85
0.50
10
10
3.00
1.65
3.10
A
1
2
1
11X
D
2.38
0.75
0.08 C
C
0.25
PCB Layout Reference View
0.50
1
All dimensions nominal, not for tooling use
(reference JEDEC MO-229WEED)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
2
0.40
1.65
B
10
2.38
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
SON50P300X300X80-11WEED3M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
Copyright ©2006, 2007, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
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