4.5 MB

The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07–12629–1E
8-bit Microcontrollers
CMOS
F2MC-8FX MB95330H Series
MB95F332H/F332K/F333H/F333K/F334H/F334K
■ DESCRIPTION
MB95330H is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction
set, the microcontrollers of this series contain a variety of peripheral resources.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
• Clock
• Selectable main clock source
Main OSC clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz)
External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz)
Main CR clock (1/8/10/12.5 MHz ±2%, maximum machine clock frequency: 12.5 MHz)
• Selectable subclock source
Sub-OSC clock (32.768 kHz)
External clock (32.768 kHz)
Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 200 kHz)
• Timer
• 8/16-bit composite timer × 2 channels
• 8/16-bit PPG × 3 channels
• 16-bit PPG × 1 channel (can work independently or together with the multi-pulse generator)
• 16-bit reload timer × 1 channel (can work independently or together with the multi-pulse generator)
• Time-base timer × 1 channel
• Watch prescaler × 1 channel
• UART/SIO × 1 channel
• Full duplex double buffer
• Capable of clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data
transfer
(Continued)
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.4
MB95330H Series
(Continued)
• I2C × 1 channel
• Built-in wake-up function
• Multi-pulse generator (MPG) (for DC motor control) × 1 channel
• 16-bit reload timer × 1 channel
• 16-bit PPG timer × 1 channel
• Waveform sequencer (including a 16-bit timer equipped with a buffer and a compare clear function)
• LIN-UART
• Full duplex double buffer
• Capable of clock-synchronous serial data transfer and clock-asynchronous serial data transfer
• External interrupt × 10 channels
• Interrupt by edge detection (rising edge, falling edge, and both edges can be selected)
• Can be used to wake up the device from different low power consumption (standby) modes
• 8/10-bit A/D converter × 8 channels
• 8-bit and 10-bit resolution can be chosen.
• Low power consumption (standby) modes
• Stop mode
• Sleep mode
• Watch mode
• Time-base timer mode
• I/O port
• MB95F332H/F333H/F334H (maximum no. of I/O ports: 28)
General-purpose I/O ports (N-ch open drain)
:3
General-purpose I/O ports (CMOS I/O)
: 25
• MB95F332K/F333K/F334K (maximum no. of I/O ports: 29)
General-purpose I/O ports (N-ch open drain)
:4
General-purpose I/O ports (CMOS I/O)
: 25
• On-chip debug
• 1-wire serial control
• Serial writing supported (asynchronous mode)
• Hardware/software watchdog timer
• Built-in hardware watchdog timer
• Low-voltage detection reset circuit
• Built-in low-voltage detector
• Clock supervisor counter
• Built-in clock supervisor counter function
• Programmable port input voltage level
• CMOS input level / hysteresis input level
• Dual operation Flash memory
• The erase/write operation and the read operation can be executed in different banks (upper bank/lower
bank) simultaneously.
• Flash memory security function
• Protects the content of the Flash memory
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MB95330H Series
■ PRODUCT LINE-UP
Part number
MB95F332H
MB95F333H
MB95F334H
MB95F332K
MB95F333K
MB95F334K
Parameter
Type
Flash memory product
Clock
supervisor
It supervises the main clock oscillation.
counter
Program ROM
8 Kbyte
12 Kbyte
20 Kbyte
8 Kbyte
12 Kbyte
20 Kbyte
capacity
RAM capacity
240 bytes
496 bytes
1008 bytes
240 bytes
496 bytes
1008 bytes
Low-voltage
No
Yes
detection reset
Reset input
Dedicated
Selected by software
Number of basic instructions
: 136
Instruction bit length
: 8 bits
Instruction length
: 1 to 3 bytes
CPU functions
Data bit length
: 1, 8 and 16 bits
Minimum instruction execution time : 61.5 ns (with machine clock = 16.25 MHz)
Interrupt processing time
: 0.6 µs (with machine clock = 16.25 MHz)
I/O ports (Max): 28
I/O ports (Max): 29
GeneralCMOS I/O: 25
CMOS I/O: 25
purpose I/O
N-ch open drain: 4
N-ch open drain: 3
Time-base
Interrupt cycle: 0.256 ms to 8.3 s (when external clock = 4 MHz)
timer
Hardware/
Reset generation cycle
Main oscillation clock at 10 MHz: 105 ms (Min)
software
watchdog timer The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace three bytes of data.
A wide range of communication speeds can be selected by a dedicated reload timer.
Clock-synchronous serial data transfer and clock-asynchronous serial data transfer is
LIN-UART
enabled.
The LIN function can be used as a LIN master or a LIN slave.
8 channels
8/10-bit A/D
converter
8-bit resolution and 10-bit resolution can be chosen.
2 channels
8/16-bit
The timer can be configured as an "8-bit timer x 2 channels" or a "16-bit timer x 1 channel".
composite
It has built-in timer function, PWC function, PWM function and input capture function.
timer
Count clock: it can be selected from internal clocks (seven types) and external clocks.
It can output square wave.
10 channels
External
Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
It can be used to wake up the device from different standby modes.
1-wire serial control
On-chip debug
It supports serial writing. (asynchronous mode)
(Continued)
DS07–12629–1E
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MB95330H Series
(Continued)
Part number
MB95F332H
MB95F333H
MB95F334H
MB95F332K
MB95F333K
MB95F334K
Parameter
UART/SIO
I2C
8/16-bit PPG
16-bit PPG
16-bit reload
timer
Multi-pulse
generator (for
DC motor
control)
Watch
prescaler
1 channel
Data transfer with UART/SIO is enabled.
It has a full duplex double buffer, variable data length (5/6/7/8 bits), a built-in baud rate
generator and an error detection function.
It uses the NRZ type transfer format.
LSB-first data transfer and MSB-first data transfer are available to use.
Clock-asynchronous (UART) serial data transfer and clock-synchronous (SIO) serial data
transfer is enabled.
1 channel
Master/slave transmission and receiving
It has a bus error function, an arbitration function, a transmission direction detection function
and a wake-up function.
It also has functions of generating and detecting repeated START conditions.
3 channels
Each channel of PPG can be used as two 8-bit PPG channels or a single 16-bit PPG channel.
The counter operating clock can be selected from eight clock sources.
PWM mode and one-shot mode are available to use.
The counter operating clock can be selected from eight clock sources.
It supports external trigger start.
It can work independently or together with the multi-pulse generator.
Two clock modes and two counter operating modes are available to use.
It can output square waveform.
Count clock: it can be selected from internal clocks (seven types) and external clocks.
Two counter operating modes: reload mode and one-shot mode
It can work independently or together with the multi-pulse generator.
16-bit PPG timer: 1 channel
16-bit reload timer operations: toggle output, one-shot output
Event counter: 1 channel
Waveform sequencer (including a 16-bit timer equipped with a buffer and a compare clear
function)
Eight different time intervals can be selected.
It supports automatic programming, Embedded Algorithm, and write/erase/erase-suspend/
erase-resume commands.
It has a flag indicating the completion of the operation of Embedded Algorithm.
Flash memory
Number of write/erase cycles: 100000
Data retention time: 20 years
Flash security feature for protecting the content of the Flash memory
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
FPT-32P-M30
Package
DIP-32P-M06
LCC-32P-M19
4
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MB95330H Series
■ PACKAGES AND CORRESPONDING PRODUCTS
Part number
MB95F332H
MB95F332K
MB95F333H
MB95F333K
MB95F334H
MB95F334K
FPT-32P-M30
O
O
O
O
O
O
DIP-32P-M06
O
O
O
O
O
O
LCC-32P-M19
O
O
O
O
O
O
Package
O: Available
DS07–12629–1E
5
MB95330H Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION
• Current consumption
When using the on-chip debug function, take account of the current consumption of flash erase/write.
For details of current consumption, see “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, see “■ PACKAGES AND CORRESPONDING PRODUCTS” and
“■ PACKAGE DIMENSIONS”.
• Operating voltage
The operating voltage varies, depending on whether the on-chip debug function is used or not.
For details of the operating voltage, see “■ ELECTRICAL CHARACTERISTICS”.
• On-chip debug function
The on-chip debug function requires that VCC, VSS and one serial wire be connected to an evaluation tool.
6
DS07–12629–1E
MB95330H Series
32
31
30
29
28
27
26
25
Vss
X1/PF1
X0/PF0
PF2/RST
P17/TO1/SNI0
P16/UI0/PPG21
P15/UO0/PPG20
P14/UCK0/PPG01
■ PIN ASSIGNMENT
1
2
3
4
5
6
7
8
PF2/RST
(TOP VIEW)
LQFP32
9
10
11
12
13
14
15
16
P00/INT00/AN00
P01/INT01/AN01
P02/INT02/AN02/SCK
P03/INT03/AN03/SOT
FPT-32P-M30
OPT1/PPG01/TO11/P63
OPT0/PPG00/TO10/P62
INT09/SCL/TI1/P61
INT08/SDA/DTTI/P60
SNI2/X1A/PG2
SNI1/X0A/PG1
Vcc
C
OPT5/PPG21/TRG1/P67
OPT4/PPG20/PPG1/P66
OPT3/PPG11/P65
OPT2/PPG10/EC1/P64
OPT1/PPG01/TO11/P63
OPT0/PPG00/TO10/P62
INT09/SCL/TI1/P61
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
INT08/SDA/DTTI/P60
16
X0/PF0
X1/PF1
Vss
SNI2/X1A/PG2
SNI1/X0A/PG1
Vcc
C
OPT5/PPG21/TRG1/P67
OPT4/PPG20/PPG1/P66
OPT3/PPG11/P65
OPT2/PPG10/EC1/P64
(TOP VIEW)
SH-DIP32
DIP-32P-M06
24
23
22
21
P13/PPG00
P12/DBG/EC0
P11/PPG11
P10/PPG10
20
19
18
17
P07/INT07/AN07
P06/INT06/AN06/TO01
P05/INT05/AN05/HCLK2/TO00
P04/INT04/AN04/SIN/HCLK1/EC0
32
P17/TO1/SNI0
31
30
29
28
27
26
25
24
23
22
21
P16/UI0/PPG21
P15/UO0/PPG20
P14/UCK0/PPG01
P13/PPG00
P12/DBG/EC0
P11/PPG11
P10/PPG10
P07/INT07/AN07
P06/INT06/AN06/TO01
P05/INT05/AN05/HCLK2/TO00
P04/INT04/AN04/SIN/HCLK1/EC0
20
19
18
17
P03/INT03/AN03/SOT
P02/INT02/AN02/SCK
P01/INT01/AN01
P00/INT00/AN00
(Continued)
DS07–12629–1E
7
MB95330H Series
32
31
30
29
28
27
26
25
Vss
X1/PF1
X0/PF0
PF2/RST
P17/TO1/SNI0
P16/UI0/PPG21
P15/UO0/PPG20
P14/UCK0/PPG01
(Continued)
8
(TOP VIEW)
QFN32
13
14
15
16
P00/INT00/AN00
P01/INT01/AN01
P02/INT02/AN02/SCK
P03/INT03/AN03/SOT
LCC-32P-M19
9
10
11
12
1
2
3
4
5
6
7
8
OPT1/PPG01/TO11/P63
OPT0/PPG00/TO10/P62
INT09/SCL/TI1/P61
INT08/SDA/DTTI/P60
SNI2/X1A/PG2
SNI1/X0A/PG1
Vcc
C
OPT5/PPG21/TRG1/P67
OPT4/PPG20/PPG1/P66
OPT3/PPG11/P65
OPT2/PPG10/EC1/P64
24
23
22
21
P13/PPG00
P12/DBG/EC0
P11/PPG11
P10/PPG10
20
19
18
17
P07/INT07/AN07
P06/INT06/AN06/TO01
P05/INT05/AN05/HCLK2/TO00
P04/INT04/AN04/SIN/HCLK1/EC0
DS07–12629–1E
MB95330H Series
■ PIN DESCRIPTION
Pin no.
LQFP32*1
SH-DIP32*3
& QFN32*2
Pin
name
I/O
circuit
type*4
PG2
1
2
5
6
X1A
Function
General-purpose I/O port
C
Subclock I/O oscillation pin
SNI2
Trigger input pin for the position detection function of the MPG
waveform sequencer
PG1
General-purpose I/O port
X0A
C
Subclock input oscillation pin
Trigger input pin for the position detection function of the MPG
waveform sequencer
SNI1
3
7
VCC
—
Power supply pin
4
8
C
—
Capacitor connection pin
General-purpose I/O port
High-current pin
P67
5
9
PPG21
D
TRG1
16-bit PPG ch. 1 trigger input pin
OPT5
MPG waveform sequencer output pin
General-purpose I/O port
High-current pin
P66
6
10
PPG20
D
11
16-bit PPG ch. 1 output pin
OPT4
MPG waveform sequencer output pin
General-purpose I/O port
High-current pin
PPG11
D
OPT3
12
EC1
General-purpose I/O port
High-current pin
D
PPG10
MPG waveform sequencer output pin
General-purpose I/O port
High-current pin
P63
13
TO11
PPG01
OPT1
8/16-bit composite timer ch. 1 clock input pin
8/16-bit PPG ch. 1 output pin
OPT2
9
8/16-bit PPG ch. 1 output pin
MPG waveform sequencer output pin
P64
8
8/16-bit PPG ch. 2 output pin
PPG1
P65
7
8/16-bit PPG ch. 2 output pin
D
8/16-bit composite timer ch. 1 output pin
8/16-bit PPG ch. 0 output pin
MPG waveform sequencer output pin
(Continued)
DS07–12629–1E
9
MB95330H Series
Pin no.
LQFP32*1
SH-DIP32*3
& QFN32*2
Pin
name
I/O
circuit
type*4
General-purpose I/O port
High-current pin
P62
10
14
TO10
D
PPG00
MPG waveform sequencer output pin
P61
12
13
15
16
17
INT09
SCL
General-purpose I/O port
I
P60
General-purpose I/O port
INT08
SDA
I
16
17
20
21
I2C data I/O pin
MPG waveform sequencer input pin
P00
General-purpose I/O port
INT00
E
INT01
INT02
AN02
External interrupt input pin
A/D converter analog input pin
General-purpose I/O port
E
External interrupt input pin
A/D converter analog input pin
P02
19
External interrupt input pin
DTTI
AN01
15
I2C clock I/O pin
16-bit reload timer ch. 1 input pin
P01
18
External interrupt input pin
TI1
AN00
14
8/16-bit composite timer ch. 1 output pin
8/16-bit PPG ch. 0 output pin
OPT0
11
Function
General-purpose I/O port
E
External interrupt input pin
A/D converter analog input pin
SCK
LIN-UART clock I/O pin
P03
General-purpose I/O port
INT03
AN03
E
External interrupt input pin
A/D converter analog input pin
SOT
LIN-UART data output pin
P04
General-purpose I/O port
INT04
External interrupt input pin
AN04
SIN
HCLK1
EC0
F
A/D converter analog input pin
LIN-UART data input pin
External clock input pin
8/16-bit composite timer ch. 0 clock input pin
(Continued)
10
DS07–12629–1E
MB95330H Series
Pin no.
LQFP32*1
SH-DIP32*3
& QFN32*2
18
22
Pin
name
I/O
circuit
type*4
P05
General-purpose I/O port
INT05
External interrupt input pin
AN05
E
HCLK2
8/16-bit composite timer ch. 0 output pin
P06
23
INT06
AN06
General-purpose I/O port
E
TO01
24
INT07
25
22
26
P10
PPG10
P11
PPG11
E
27
DBG
G
G
28
P13
PPG00
H
29
UCK0
G
G
UO0
G
UI0
J
TO1
G
RST
UART/SIO ch. 0 data input pin
16-bit reload timer ch. 1 output pin
Trigger input pin for the position detection function of the MPG
waveform sequencer
PF2
1
UART/SIO ch. 0 data output pin
General-purpose I/O port
SNI0
29
UART/SIO ch. 0 clock I/O pin
8/16-bit PPG ch. 2 output pin
P17
32
8/16-bit PPG ch. 0 output pin
General-purpose I/O port
PPG21
28
General-purpose I/O port
8/16-bit PPG ch. 2 output pin
P16
31
DBG input pin
General-purpose I/O port
PPG20
27
8/16-bit PPG ch. 1 output pin
8/16-bit PPG ch. 0 output pin
P15
30
General-purpose I/O port
General-purpose I/O port
PPG01
26
8/16-bit PPG ch. 1 output pin
8/16-bit composite timer ch. 0 clock input pin
P14
25
General-purpose I/O port
General-purpose I/O port
EC0
24
External interrupt input pin
A/D converter analog input pin
P12
23
A/D converter analog input pin
General-purpose I/O port
AN07
21
External interrupt input pin
8/16-bit composite timer ch. 0 output pin
P07
20
A/D converter analog input pin
External clock input pin
TO00
19
Function
General-purpose I/O port
A
Reset pin
Dedicated reset pin in MB95F332H/F333H/F334H
(Continued)
DS07–12629–1E
11
MB95330H Series
(Continued)
Pin no.
LQFP32*1
SH-DIP32*3
& QFN32*2
30
2
31
3
32
4
Pin
name
PF0
X0
PF1
X1
VSS
I/O
circuit
type*4
B
B
—
Function
General-purpose I/O port
Main clock input oscillation pin
General-purpose I/O port
Main clock I/O oscillation pin
Power supply pin (GND)
*1: Package code: FPT-32P-M30
*2: Package code: LCC-32P-M19
*3: Package code: DIP-32P-M06
*4: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
12
DS07–12629–1E
MB95330H Series
■ I/O CIRCUIT TYPE
Type
Circuit
A
Remarks
Reset input / Hysteresis input
Reset output / Digital output
N-ch
B
P-ch
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
Clock input
• N-ch open drain output
• Hysteresis input
• Reset output
• Oscillation circuit
• High-speed side
Feedback resistance:
approx. 1 MΩ
• CMOS output
• Hysteresis input
X1
X0
Standby control / Port select
P-ch
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
C
Port select
R
Pull-up control
P-ch
Digital output
P-ch
N-ch
Digital output
Standby control
Hysteresis input
• Oscillation circuit
• Low-speed side
Feedback resistance:
approx.10 MΩ
• CMOS output
• Hysteresis input
• Pull-up control available
Clock input
X1A
X0A
Standby control / Port select
Port select
R
Pull-up control
Digital output
Digital output
P-ch
N-ch
Digital output
Standby control
Hysteresis input
(Continued)
DS07–12629–1E
13
MB95330H Series
Type
Circuit
D
Remarks
P-ch
Digital output
• CMOS output
• Hysteresis input
Digital output
N-ch
Standby control
Hysteresis input
E
Pull-up control
R
P-ch
• CMOS output
• Hysteresis input
• Pull-up control available
Digital output
P-ch
Digital output
N-ch
Analog input
A/D control
Standby control
Hysteresis input
F
Pull-up control
R
P-ch
Digital output
P-ch
•
•
•
•
CMOS output
Hysteresis input
CMOS input
Pull-up control available
Digital output
N-ch
Analog input
A/D control
Standby control
Hysteresis input
CMOS input
G
Pull-up control
R
P-ch
• Hysteresis input
• CMOS output
• Pull-up control available
Digital output
P-ch
Digital output
N-ch
Standby control
Hysteresis input
H
Standby control
Hysteresis input
• N-ch open drain output
• Hysteresis input
Digital output
N-ch
(Continued)
14
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MB95330H Series
(Continued)
Type
Circuit
Remarks
I
Digital output
N-ch
Standby control
• N-ch open drain output
• Hysteresis input
• CMOS input
Hysteresis input
CMOS input
J
Pull-up control
R
P-ch
Digital output
P-ch
•
•
•
•
CMOS output
Hysteresis input
CMOS input
Pull-up control available
Digital output
N-ch
Standby control
Hysteresis input
CMOS input
DS07–12629–1E
15
MB95330H Series
■ NOTES ON DEVICE HANDLING
• Preventing latch-ups
When using the device, ensure that the voltage applied does not exceed the maximum voltage rating.
In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that
is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating
range of power supply voltage mentioned in "1. Absolute Maximum Ratings" of “■ ELECTRICAL CHARACTERISTICS” is applied to the VCC pin or the VSS pin, a latch-up may occur.
When a latch-up occurs, power supply current increases significantly, which may cause a component to be
thermally destroyed.
• Stabilizing supply voltage
Supply voltage must be stabilized.
A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within
the guaranteed operating range of the VCC power supply voltage.
As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value)
at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient
fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply.
• Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from subclock mode or stop mode.
■ PIN CONNECTION
• Treatment of unused pins
If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions
or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 kΩ. Set an
unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it
the same as an unused input pin. If there is an unused output pin, leave it unconnected.
• Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase
in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS
pin to the power supply and ground outside the device. In addition, connect the current supply source to the
VCC pin and the VSS pin with low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between
the VCC pin and the VSS pin at a location close to this device.
• DBG pin
Connect the DBG pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the debug mode due to noise, minimize the distance
between the DBG pin and the VCC or VSS pin when designing the layout of the printed circuit board.
The DBG pin should not stay at “L” level after power-on until the reset output is released.
• RST pin
Connect the RST pin directly to an external pull-up resistor.
To prevent the device from unintentionally entering the reset mode due to noise, minimize the distance
between the RST pin and the VCC or VSS pin when designing the layout of the printed circuit board.
The RST/PF2 pin functions as the reset input/output pin after power-on. In addition, the reset output of the
RST/PF2 pin can be enabled by the RSTOE bit of the SYSC register, and the reset input function and the
general purpose I/O function can be selected by the RSTEN bit of the SYSC register.
16
DS07–12629–1E
MB95330H Series
• C pin
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for
the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see
the diagram below. To prevent the device from unintentionally entering a mode to which the device is not set
to transit due to noise, minimize the distance between the C pin and CS and the distance between CS and
the VSS pin when designing the layout of a printed circuit board.
• DBG/RST/C pins connection diagram
DBG
C
RST
Cs
DS07–12629–1E
17
MB95330H Series
■ BLOCK DIAGRAM
F2MC-8FX CPU
PF2*1/RST*2
Reset with LVD
Flash with security function
(20/12/8 Kbyte)
PF1/X1*2
PF0/X0*2
(PG2/X1A*2)
Oscillator
circuit
RAM (1008/496/240 bytes)
CR
oscillator
(PG1/X0A*2)
(P04/HCLK1)
(P05/HCLK2)
(P12/DBG*1)
(P05/TO00)
8/16-bit composite timer ch. 0
Clock control
(P06/TO01)
P12/EC0, (P04/EC0)
On-chip debug
8/10-bit A/D converter
(P00/AN00 to P07/AN07)
Wild register
(P62/TO10)
P02/INT02 to P07/INT07
External interrupt
8/16-bit composite timer ch. 1
P00/INT00, P01/INT01,
P60/INT08, P61/INT09
External interrupt
MPG
C
Interrupt controller
(P63/TO11)
(P02/SCK)
(P03/SOT)
LIN-UART
Internal bus
(P64/EC1)
(P04/SIN)
16-bit reload timer
(P61/TI1)
(P17/TO1)
P62/OPT0 to P67/OPT5*3
Waveform sequencer
P17/SNI0, PG1/SNI1, PG2/SNI2
(P60/DTTI)
(P61/TI1)
(P14/UCK0)
(P15/UO0)
UART/SIO
(P16/UI0)
(P60/SDA*1)
I2C
(P61/SCL*1)
(P62/PPG00*3), P13/PPG00
(P63/PPG01*3), P14/PPG01
(P66/PPG20*3), P15/PPG20
(P67/PPG21*3), P16/PPG21
16-bit PPG
8/16-bit PPG ch. 1
(P67/TRG1)
(P66/PPG1)
P10/PPG10, (P64/PPG10*3)
P11/PPG11, (P65/PPG11*3)
8/16-bit PPG ch. 0
8/16-bit PPG ch. 2
Port
Vcc
*1: PF2, P12, P60 and P61 are N-ch open drain pins.
Vss
*2: Software option
Port
*3: P62 to P67 are high-current pins.
Note: Pins in parentheses indicate that functions of those pins are shared among different resources.
18
DS07–12629–1E
MB95330H Series
■ CPU CORE
• Memory Space
The memory space of the MB95330H Series is 64 Kbyte in size, and consists of an I/O area, a data area,
and a program area. The memory space includes areas intended for specific purposes such as
general-purpose registers and a vector table. The memory maps of the MB95330H Series are shown below.
• Memory Maps
MB95F332H/F332K
0000H
MB95F333H/F333K
0000H
0000H
I/O
0080H
0090H
0100H
0180H
Access prohibited
RAM 240 bytes
Register
I/O
0080H
0090H
0100H
Access prohibited
RAM 496 bytes
Access prohibited
0F80H
C000H
Flash 4 Kbyte
Access prohibited
F000H
FFFFH
DS07–12629–1E
Flash 4 Kbyte
0480H
Access prohibited
0F80H
1000H
Extended I/O
1000H
Access prohibited
Access prohibited
B000H
Register
Extended I/O
Extended I/O
B000H
C000H
Access prohibited
RAM 1008 bytes
0200H
Access prohibited
1000H
I/O
0080H
0090H
0100H
Register
0200H
0280H
0F80H
MB95F334H/F334K
Flash 4 Kbyte
Access prohibited
B000H
Access prohibited
Flash 20 Kbyte
E000H
Flash 8 Kbyte
FFFFH
FFFFH
19
MB95330H Series
■ I/O MAP
Address
Register
abbreviation
Register name
R/W Initial value
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
—
—
—
0005H
WATR
R/W
11111111B
0006H
—
—
—
0007H
SYCC
System clock control register
R/W
0000X011B
00000XXXB
(Disabled)
Oscillation stabilization wait time setting register
(Disabled)
0008H
STBC
Standby control register
R/W
0009H
RSRR
Reset source register
R/W XXXXXXXXB
000AH
TBTC
Time-base timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00XX0000B
000DH
SYCC2
System clock control register 2
R/W
XX100011B
000EH
to
0015H
—
—
—
0016H
PDR6
Port 6 data register
R/W
00000000B
0017H
DDR6
Port 6 direction register
R/W
00000000B
0018H
to
0027H
—
—
—
0028H
PDRF
Port F data register
R/W
00000000B
0029H
DDRF
Port F direction register
R/W
00000000B
002AH
PDRG
Port G data register
R/W
00000000B
002BH
DDRG
Port G direction register
R/W
00000000B
002CH
PUL0
Port 0 pull-up register
R/W
00000000B
002DH
PUL1
Port 1 pull-up register
R/W
00000000B
002EH
to
0034H
—
—
—
0035H
PULG
Port G pull-up register
R/W
00000000B
0036H
T01CR1
8/16-bit composite timer 01 status control register 1 ch. 0
R/W
00000000B
0037H
T00CR1
8/16-bit composite timer 00 status control register 1 ch. 0
R/W
00000000B
0038H
T11CR1
8/16-bit composite timer 11 status control register 1 ch. 1
R/W
00000000B
0039H
T10CR1
8/16-bit composite timer 10 status control register 1 ch. 1
R/W
00000000B
003AH
PC01
8/16-bit PPG timer 01 control register ch. 0
R/W
00000000B
003BH
PC00
8/16-bit PPG timer 00 control register ch. 0
R/W
00000000B
003CH
PC11
8/16-bit PPG timer 11 control register ch. 1
R/W
00000000B
003DH
PC10
8/16-bit PPG timer 10 control register ch. 1
R/W
00000000B
003EH
PC21
8/16-bit PPG timer 21 control register ch. 2
R/W
00000000B
003FH
PC20
8/16-bit PPG timer 20 control register ch. 2
R/W
00000000B
(Disabled)
(Disabled)
(Disabled)
(Continued)
20
DS07–12629–1E
MB95330H Series
Address
Register
abbreviation
0040H
TMCSRH1
16-bit reload timer control status register upper ch. 1
R/W
00000000B
0041H
TMCSRL1
16-bit reload timer control status register lower ch. 1
R/W
00000000B
0042H,
0043H
—
—
—
0044H
PCNTH1
16-bit PPG status control register upper ch. 1
R/W
00000000B
0045H
PCNTL1
16-bit PPG status control register lower ch. 1
R/W
00000000B
0046H,
0047H
—
—
—
0048H
EIC00
External interrupt circuit control register ch. 0/ch. 1
R/W
00000000B
0049H
EIC10
External interrupt circuit control register ch. 2/ch. 3
R/W
00000000B
004AH
EIC20
External interrupt circuit control register ch. 4/ch. 5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch. 6/ch. 7
R/W
00000000B
004CH
EIC01
External interrupt circuit control register ch. 8/ch. 9
R/W
00000000B
004DH
to
004FH
—
—
—
0050H
SCR
LIN-UART serial control register
R/W
00000000B
0051H
SMR
LIN-UART serial mode register
R/W
00000000B
0052H
SSR
LIN-UART serial status register
R/W
00001000B
0053H
RDR/TDR
LIN-UART receive/transmit data register
R/W
00000000B
0054H
ESCR
LIN-UART extended status control register
R/W
00000100B
0055H
ECCR
LIN-UART extended communication control register
R/W
000000XXB
0056H
SMC10
UART/SIO serial mode control register 1 ch. 0
R/W
00000000B
0057H
SMC20
UART/SIO serial mode control register 2 ch. 0
R/W
00100000B
0058H
SSR0
UART/SIO serial status and data register ch. 0
R/W
00000001B
0059H
TDR0
UART/SIO serial output data register ch. 0
R/W
00000000B
005AH
RDR0
UART/SIO serial input data register ch. 0
R
00000000B
005BH
to
005FH
—
—
—
0060H
IBCR00
R/W
00000000B
I C bus control register 1
R/W
00000000B
Register name
(Disabled)
(Disabled)
(Disabled)
(Disabled)
I2C bus control register 0
2
R/W Initial value
0061H
IBCR10
0062H
IBSR0
I2C bus status register
R/W
00000000B
0063H
IDDR0
I2C data register
0064H
IAAR0
R/W
00000000B
2
R/W
00000000B
2
I C clock control register
R/W
00000000B
I C address register
0065H
ICCR0
0066H
OPCUR
16-bit MPG output control register (upper)
R/W
00000000B
0067H
OPCLR
16-bit MPG output control register (lower)
R/W
00000000B
0068H
IPCUR
16-bit MPG input control register (upper)
R/W
00000000B
0069H
IPCLR
16-bit MPG input control register (lower)
R/W
00000000B
(Continued)
DS07–12629–1E
21
MB95330H Series
Address
Register
abbreviation
006AH
NCCR
16-bit MPG noise cancellation control register
R/W
00000000B
006BH
TCSR
16-bit MPG timer control status register
R/W
00000000B
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register (upper)
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register (lower)
R/W
00000000B
0070H
—
—
—
0071H
FSR2
Flash memory status register 2
R/W
00000000B
0072H
FSR
Flash memory status register
R/W
000X0000B
0073H
SWRE0
Flash memory sector write control register 0
R/W
00000000B
0074H
FSR3
R
0000XXXXB
0075H
—
—
—
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
—
—
—
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
—
—
—
0F80H
WRARH0
Wild register address setting register (upper) ch. 0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (lower) ch. 0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch. 0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (upper) ch. 1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (lower) ch. 1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch. 1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (upper) ch. 2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (lower) ch. 2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch. 2
R/W
00000000B
0F89H
to
0F91H
—
—
—
Register name
(Disabled)
Flash memory status register 3
(Disabled)
Mirror of register bank pointer (RP) and
mirror of direct bank pointer (DP)
(Disabled)
(Disabled)
R/W Initial value
(Continued)
22
DS07–12629–1E
MB95330H Series
Address
Register
abbreviation
0F92H
T01CR0
8/16-bit composite timer 01 status control register 0 ch. 0
R/W
00000000B
0F93H
T00CR0
8/16-bit composite timer 00 status control register 0 ch. 0
R/W
00000000B
0F94H
T01DR
8/16-bit composite timer 01 data register ch. 0
R/W
00000000B
0F95H
T00DR
8/16-bit composite timer 00 data register ch. 0
R/W
00000000B
0F96H
TMCR0
8/16-bit composite timer 00/01 timer mode control register
ch. 0
R/W
00000000B
0F97H
T11CR0
8/16-bit composite timer 11 status control register 0 ch. 1
R/W
00000000B
0F98H
T10CR0
8/16-bit composite timer 10 status control register 0 ch. 1
R/W
00000000B
0F99H
T11DR
8/16-bit composite timer 11 data register ch. 1
R/W
00000000B
0F9AH
T10DR
8/16-bit composite timer 10 data register ch. 1
R/W
00000000B
0F9BH
TMCR1
8/16-bit composite timer 10/11 timer mode control register
ch. 1
R/W
00000000B
0F9CH
PPS01
8/16-bit PPG01 cycle setting buffer register ch. 0
R/W
11111111B
0F9DH
PPS00
8/16-bit PPG00 cycle setting buffer register ch. 0
R/W
11111111B
0F9EH
PDS01
8/16-bit PPG01 duty setting buffer register ch. 0
R/W
11111111B
0F9FH
PDS00
8/16-bit PPG00 duty setting buffer register ch. 0
R/W
11111111B
0FA0H
PPS11
8/16-bit PPG11 cycle setting buffer register ch. 1
R/W
11111111B
0FA1H
PPS10
8/16-bit PPG10 cycle setting buffer register ch. 1
R/W
11111111B
0FA2H
PDS11
8/16-bit PPG11 duty setting buffer register ch. 1
R/W
11111111B
0FA3H
PDS10
8/16-bit PPG10 duty setting buffer register ch. 1
R/W
11111111B
0FA4H
PPGS
8/16-bit PPG startup register
R/W
00000000B
0FA5H
REVC
8/16-bit PPG output reverse register
R/W
00000000B
0FA6H
PPS21
8/16-bit PPG21 cycle setting buffer register ch. 2
R/W
11111111B
0FA7H
PPS20
8/16-bit PPG20 cycle setting buffer register ch. 2
R/W
11111111B
TMRH1
16-bit timer register (upper) ch. 1
TMRLRH1
16-bit reload register (upper) ch. 1
R/W
00000000B
R/W
00000000B
0FA8H
0FA9H
Register name
TMRL1
16-bit timer register (lower) ch. 1
TMRLRL1
16-bit reload register (lower) ch. 1
R/W Initial value
0FAAH
PDS21
8/16-bit PPG21 duty setting buffer register ch. 2
R/W
11111111B
0FABH
PDS20
8/16-bit PPG20 duty setting buffer register ch. 2
R/W
11111111B
0FACH
to
0FAFH
—
—
—
0FB0H
PDCRH1
16-bit PPG down counter register (upper) ch. 1
R
00000000B
0FB1H
PDCRL1
16-bit PPG down counter register (lower) ch. 1
R
00000000B
0FB2H
PCSRH1
16-bit PPG cycle setting buffer register (upper) ch. 1
R/W
11111111B
0FB3H
PCSRL1
16-bit PPG cycle setting buffer register (lower) ch. 1
R/W
11111111B
0FB4H
PDUTH1
16-bit PPG duty setting buffer register (upper) ch. 1
R/W
11111111B
0FB5H
PDUTL1
16-bit PPG duty setting buffer register (lower) ch. 1
R/W
11111111B
(Disabled)
(Continued)
DS07–12629–1E
23
MB95330H Series
Address
Register
abbreviation
Register name
0FB6H
to
0FBBH
—
(Disabled)
0FBCH
BGR1
0FBDH
R/W Initial value
—
—
LIN-UART baud rate generator register 1
R/W
00000000B
BGR0
LIN-UART baud rate generator register 0
R/W
00000000B
0FBEH
PSSR0
UART/SIO dedicated baud rate generator prescaler select
register ch. 0
R/W
00000000B
0FBFH
BRSR0
UART/SIO dedicated baud rate generator baud rate setting
register ch. 0
R/W
00000000B
0FC0H
to
0FC2H
—
—
—
0FC3H
AIDRL
A/D input disable register (lower)
R/W
00000000B
0FC4H
OPDBRH0
16-bit MPG output data buffer register (upper) ch. 0
R/W
00000000B
0FC5H
OPDBRL0
16-bit MPG output data buffer register (lower) ch. 0
R/W
00000000B
0FC6H
OPDBRH1
16-bit MPG output data buffer register (upper) ch. 1
R/W
00000000B
0FC7H
OPDBRL1
16-bit MPG output data buffer register (lower) ch. 1
R/W
00000000B
0FC8H
OPDBRH2
16-bit MPG output data buffer register (upper) ch. 2
R/W
00000000B
0FC9H
OPDBRL2
16-bit MPG output data buffer register (lower) ch. 2
R/W
00000000B
0FCAH
OPDBRH3
16-bit MPG output data buffer register (upper) ch. 3
R/W
00000000B
0FCBH
OPDBRL3
16-bit MPG output data buffer register (lower) ch. 3
R/W
00000000B
0FCCH
OPDBRH4
16-bit MPG output data buffer register (upper) ch. 4
R/W
00000000B
0FCDH
OPDBRL4
16-bit MPG output data buffer register (lower) ch. 4
R/W
00000000B
0FCEH
OPDBRH5
16-bit MPG output data buffer register (upper) ch. 5
R/W
00000000B
0FCFH
OPDBRL5
16-bit MPG output data buffer register (lower) ch. 5
R/W
00000000B
0FD0H
OPDBRH6
16-bit MPG output data buffer register (upper) ch. 6
R/W
00000000B
0FD1H
OPDBRL6
16-bit MPG output data buffer register (lower) ch. 6
R/W
00000000B
0FD2H
OPDBRH7
16-bit MPG output data buffer register (upper) ch. 7
R/W
00000000B
0FD3H
OPDBRL7
16-bit MPG output data buffer register (lower) ch. 7
R/W
00000000B
0FD4H
OPDBRH8
16-bit MPG output data buffer register (upper) ch. 8
R/W
00000000B
0FD5H
OPDBRL8
16-bit MPG output data buffer register (lower) ch. 8
R/W
00000000B
0FD6H
OPDBRH9
16-bit MPG output data buffer register (upper) ch. 9
R/W
00000000B
0FD7H
OPDBRL9
16-bit MPG output data buffer register (lower) ch. 9
R/W
00000000B
0FD8H
OPDBRHA
16-bit MPG output data buffer register (upper) ch. A
R/W
00000000B
0FD9H
OPDBRLA
16-bit MPG output data buffer register (lower) ch. A
R/W
00000000B
0FDAH
OPDBRHB
16-bit MPG output data buffer register (upper) ch. B
R/W
00000000B
0FDBH
OPDBRLB
16-bit MPG output data buffer register (lower) ch. B
R/W
00000000B
0FDCH
OPDUR
16-bit MPG output data register (upper)
R
0000XXXXB
0FDDH
OPDLR
16-bit MPG output data register (lower)
R
XXXXXXXXB
0FDEH
CPCUR
16-bit MPG compare clear register (upper)
R/W XXXXXXXXB
0FDFH
CPCLR
16-bit MPG compare clear register (lower)
R/W XXXXXXXXB
(Disabled)
(Continued)
24
DS07–12629–1E
MB95330H Series
(Continued)
Address
Register
abbreviation
Register name
0FE0H,
0FE1H
—
(Disabled)
0FE2H
TMBUR
0FE3H
R/W Initial value
—
—
16-bit MPG timer buffer register (upper)
R
XXXXXXXXB
TMBLR
16-bit MPG timer buffer register (lower)
R
XXXXXXXXB
0FE4H
CRTH
Main CR clock trimming register (upper)
R/W 0XXXXXXXB
0FE5H
CRTL
Main CR clock trimming register (lower)
R/W 00XXXXXXB
0FE6H,
0FE7H
—
0FE8H
SYSC
0FE9H
CMCR
0FEAH
CMDR
Clock monitoring data register
R
00000000B
0FEBH
WDTH
Watchdog timer selection ID register (upper)
R
XXXXXXXXB
0FECH
WDTL
Watchdog timer selection ID register (lower)
R
XXXXXXXXB
0FEDH
—
—
—
0FEEH
ILSR
Input level select register
R/W
00000000B
0FEFH
WICR
Interrupt pin control register
R/W
01000000B
0FF0H
to
0FFFH
—
—
—
(Disabled)
—
—
System configuration register
R/W
11000011B
Clock monitoring control register
R/W
00000000B
(Disabled)
(Disabled)
• R/W access symbols
R/W : Readable / Writable
R
: Read only
W
: Write only
• Initial value symbols
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is indeterminate.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
DS07–12629–1E
25
MB95330H Series
■ INTERRUPT SOURCE TABLE
Vector table address
Priority order of
interrupt
Bit name of
sources of the
interrupt level
same level
setting register
(occurring
simultaneously)
Interrupt
request
number
Upper
Lower
External interrupt ch. 0, ch. 4
IRQ00
FFFAH
FFFBH
L00 [1:0]
External interrupt ch. 1, ch. 5
IRQ01
FFF8H
FFF9H
L01 [1:0]
External interrupt ch. 2, ch. 6
IRQ02
FFF6H
FFF7H
L02 [1:0]
External interrupt ch. 3, ch. 7
IRQ03
FFF4H
FFF5H
L03 [1:0]
UART/SIO ch. 0, MPG (DTTI)
IRQ04
FFF2H
FFF3H
L04 [1:0]
8/16-bit composite timer ch. 0
(lower)
IRQ05
FFF0H
FFF1H
L05 [1:0]
8/16-bit composite timer ch. 0
(upper)
IRQ06
FFEEH
FFEFH
L06 [1:0]
LIN-UART (reception)
IRQ07
FFECH
FFEDH
L07 [1:0]
LIN-UART (transmission)
IRQ08
FFEAH
FFEBH
L08 [1:0]
8/16-bit PPG ch. 1 (lower)
IRQ09
FFE8H
FFE9H
L09 [1:0]
8/16-bit PPG ch. 1 (upper)
IRQ10
FFE6H
FFE7H
L10 [1:0]
8/16-bit PPG ch. 2 (upper)
IRQ11
FFE4H
FFE5H
L11 [1:0]
8/16-bit PPG ch. 0 (upper)
IRQ12
FFE2H
FFE3H
L12 [1:0]
8/16-bit PPG ch. 0 (lower)
IRQ13
FFE0H
FFE1H
L13 [1:0]
8/16-bit composite timer ch. 1
(upper)
IRQ14
FFDEH
FFDFH
L14 [1:0]
8/16-bit PPG ch. 2 (lower)
IRQ15
FFDCH
FFDDH
L15 [1:0]
16-bit reload timer ch. 1, MPG
(write timing/compare clear),
I2C
IRQ16
FFDAH
FFDBH
L16 [1:0]
16-bit PPG timer ch. 1, MPG
(position detection/compare
match)
IRQ17
FFD8H
FFD9H
L17 [1:0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1:0]
Time-base timer
IRQ19
FFD4H
FFD5H
L19 [1:0]
Watch prescaler
IRQ20
FFD2H
FFD3H
L20 [1:0]
External interrupt ch. 8, ch. 9
IRQ21
FFD0H
FFD1H
L21 [1:0]
8/16-bit composite timer ch. 1
(lower)
IRQ22
FFCEH
FFCFH
L22 [1:0]
Flash memory
IRQ23
FFCCH
FFCDH
L23 [1:0]
Interrupt source
26
High
Low
DS07–12629–1E
MB95330H Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1
Input voltage*1
Output voltage*
1
Maximum clamp current
Total maximum clamp
current
“L” level maximum
output current
Rating
VCC
VSS − 0.3
VSS + 6
V
VI
VSS − 0.3
VSS + 6
V
*2
VO
VSS − 0.3
VSS + 6
V
*2
ICLAMP
−2
+2
mA
Applicable to specific pins*3
Σ|ICLAMP|
—
20
mA
Applicable to specific pins*3
IOL1
IOL2
—
—
15
15
“H” level maximum
output current
mA
4
“L” level average current
“L” level total average
output current
mA
IOLAV2
—
12
ΣIOL
—
100
mA
ΣIOLAV
—
50
mA
IOH1
—
−15
IOH2
—
−15
IOHAV1
—
mA
−4
“H” level average
current
mA
IOHAV2
—
−8
ΣIOH
—
−100
mA
ΣIOHAV
—
−50
mA
Power consumption
Pd
—
320
mW
Operating temperature
TA
−40
+85
°C
Tstg
−55
+150
°C
“H” level total maximum
output current
“H” level total average
output current
Storage temperature
Remarks
Max
IOLAV1
“L” level total maximum
output current
Unit
Min
Other than P62 to P67
P62 to P67
Other than P62 to P67
Average output current =
operating current × operating ratio
(1 pin)
P62 to P67
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(Total number of pins)
Other than P62 to P67
P62 to P67
Other than P62 to P67
Average output current =
operating current × operating ratio
(1 pin)
P62 to P67
Average output current =
operating current × operating ratio
(1 pin)
Total average output current =
operating current × operating ratio
(Total number of pins)
(Continued)
DS07–12629–1E
27
MB95330H Series
(Continued)
*1: The parameter is based on VSS = 0.0 V.
*2: VI and VO must not exceed VCC + 0.3 V. VI must not exceed the rated voltage. However, if the maximum
current to/from an input is limited by means of an external component, the ICLAMP rating is used instead of
the VI rating.
*3: Applicable to the following pins: P00 to P07, P10, P11, P13 to P17, P62 to P67, PF0, PF1, PG1 and PG2
• Use under recommended operating conditions.
• Use with DC voltage (current).
• The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor
between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.
• The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller
pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the
current is transient current or stationary current.
• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High
Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin,
affecting other devices.
• If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since
power is supplied from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage
of power supply may not be sufficient to enable a power-on reset.
• Do not leave the HV (High Voltage) input pin unconnected.
• Example of a recommended circuit
• Input/Output equivalent circuit
Protective diode
VCC
HV(High Voltage) input (0 V to 16 V)
P-ch
Limiting
resistor
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
28
DS07–12629–1E
MB95330H Series
2. Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Symbol
Power supply
voltage
VCC
Smoothing
capacitor
CS
Operating
temperature
TA
Value
Min
Max
2.4*1*2
5.5*1
2.3
5.5
2.9
5.5
2.3
5.5
0.022
1
−40
+85
+5
+35
Unit
Remarks
In normal operation
V
Other than on-chip debug
Hold condition in stop mode mode
In normal operation
Hold condition in stop mode
On-chip debug mode
µF *3
°C
Other than on-chip debug mode
On-chip debug mode
*1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range.
*2: This value becomes 2.88 V when the low-voltage detection reset is used.
*3: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The bypass capacitor for
the VCC pin must have a capacitance larger than CS. For the connection to a smoothing capacitor CS, see
the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise,
minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing
the layout of a printed circuit board.
• DBG / RST / C pins connection diagram
*
DBG
C
RST
Cs
*: Since the DBG pin becomes a communication pin in on-chip debug mode,
set a pull-up resistor value suiting the input/output specifications of P12/DBG/EC0.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS07–12629–1E
29
MB95330H Series
3. DC Characteristics
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter Symbol
"H" level
input
voltage
“L” level
input
voltage
Open-drain
output
application
voltage
“H” level
output
voltage
“L” level
output
voltage
Input leak
current
(Hi-Z output
leak
current)
Pull-up
resistance
Input
capacitance
Pin name
Condition
VIHI
P04, P16, P60,
P61
Value
Unit
Remarks
VCC + 0.3
V
When CMOS input
level (hysteresis
input) is selected
—
VCC + 0.3
V
Hysteresis input
0.7 VCC
—
VCC + 0.3
V
Hysteresis input
*1
VSS − 0.3
—
0.3 VCC
V
When CMOS input
level (hysteresis
input) is selected
VILS
P00 to P07,
P10 to P17,
P60 to P67,
PF0, PF1,
PG1, PG2
*1
VSS − 0.3
—
0.2 VCC
V
Hysteresis input
VILM
PF2
—
VSS − 0.3
—
0.3 VCC
V
Hysteresis input
VD
P12, P60, P61,
PF2
—
VSS − 0.3
—
VSS + 5.5
V
VOH1
Output pins
other than P12,
IOH = −4 mA
P60 to P67,
PF2
VCC − 0.5
—
—
V
VOH2
P62 to P67
IOH = −8 mA
VCC − 0.5
—
—
V
VOL1
Output pins
other than P62 IOL = 4 mA
to P67
—
—
0.4
V
VOL2
P62 to P67
IOL = 12 mA
—
—
0.4
V
ILI
All input pins
0.0 V < VI < VCC
−5
—
+5
When pull-up
µA resistance is
disabled
RPULL
P00 to P07,
P10, P11,
P13 to P17,
PG1, PG2
VI = 0 V
25
50
100
When pull-up
kΩ resistance is
enabled
—
5
15
pF
Min
Typ
Max
*1
0.7 VCC
—
VIHS
P00 to P07,
P10 to P17,
P60 to P67,
PF0, PF1,
PG1, PG2
*1
0.8 VCC
VIHM
PF2
—
VIL
P04, P16, P60,
P61
CIN
Other than VCC
f = 1 MHz
and VSS
(Continued)
30
DS07–12629–1E
MB95330H Series
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Pin name
Condition
Value
Min
Typ
Max
Unit
Remarks
Flash memory
product (except
mA
writing and
erasing)
—
13
17
—
20.5
26.5
Flash memory
mA product (at writing
and erasing)
—
15
21
mA At A/D conversion
—
5.5
9
mA
ICCL
VCC = 5.5 V
VCC
(External clock FCL = 32 kHz
FMPL = 16 kHz
operation)
Subclock mode
(divided by 2)
TA = +25°C
—
65
153
µA
ICCLS
VCC = 5.5 V
FCL = 32 kHz
FMPL = 16 kHz
Subsleep mode
(divided by 2)
TA = +25°C
—
10
84
µA
ICCT
VCC = 5.5 V
FCL = 32 kHz
Watch mode
Main stop mode
TA = +25°C
—
5
30
µA
ICCMCR
VCC = 5.5 V
FCRH = 12.5 MHz
FMP = 12.5 MHz
Main CR clock
mode
—
10
13.2
mA
VCC = 5.5 V
Sub-CR clock
mode
(divided by 2)
TA = +25°C
—
110
410
µA
VCC = 5.5 V
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
ICC
VCC = 5.5 V
FCH = 32 MHz
FMP = 16 MHz
Main sleep mode
(divided by 2)
ICCS
Power
supply
current*2
VCC
ICCSCR
(Continued)
DS07–12629–1E
31
MB95330H Series
(Continued)
Parameter
Symbol
VCC = 5.5 V
FCH = 32 MHz
Time-base timer
VCC
mode
(External clock TA = +25°C
operation)
VCC = 5.5 V
Substop mode
TA = +25°C
—
1.1
3
mA
—
3.5
22.5
µA
ILVD
Current
consumption for
low-voltage
detection circuit
only
—
37
54
µA
ICRH
Current
consumption for
the main CR
oscillator
—
0.5
0.6
mA
Current
consumption for
the sub-CR
oscillator oscillating
at 100 kHz
—
20
72
µA
ICCTS
ICCH
Power
supply
current*2
Pin name
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Value
Condition
Unit
Remarks
Min Typ Max
ICRL
VCC
*1: The input levels of P04, P16, P60 and P61 can be switched between “CMOS input level” and “hysteresis
input level”. The input level selection register (ILSR) is used to switch between the two input levels.
*2: • The power supply current is determined by the external clock. When the low-voltage detection option is
selected, the power-supply current will be the sum of adding the current consumption of the low-voltage
detection circuit (ILVD) to one of the value from ICC to ICCH. In addition, when both the low-voltage detection
option and the CR oscillator are selected, the power supply current will be the sum of adding up the current
consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL)
and a specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit
are always enabled, and current consumption therefore increases accordingly.
• See "4. AC Characteristics: (1) Clock Timing" for FCH and FCL.
• See "4. AC Characteristics: (2) Source Clock/Machine Clock" for FMP and FMPL.
32
DS07–12629–1E
MB95330H Series
4. AC Characteristics
(1) Clock Timing
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol Pin name Condition
FCH
Clock
frequency
Input clock
pulse width
Input clock rise
time and fall
time
CR oscillation
start time
tHCYL
Max
Unit
Remarks
When the main
oscillation circuit is used
—
1
—
16.25
MHz
X0
X0, X1
HCLK1,
HCLK2
X1: open
*
1
1
—
—
12
32.5
—
1
—
32.5
MHz
MHz When the main external
clock is used
MHz
12.25
9.8
7.84
0.98
12.1875
9.75
7.8
0.975
12.5
10
8
1
12.5
10
8
1
12.75
10.2
8.16
1.02
12.8125
10.25
8.2
1.025
—
32.768
—
—
32.768
—
—
—
—
—
X0A, X1A
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
50
100
200
X0, X1
—
61.5
—
1000
X0
X0, X1
HCLK1,
HCLK2
X1: open
*
83.4
30.8
—
—
1000
1000
—
30.8
—
1000
—
—
30.5
—
µs
X1: open
*
33.4
12.4
—
—
—
—
ns
ns
—
12.4
—
—
ns
—
—
15.2
—
µs
X1: open
*
—
—
—
—
5
5
ns
ns
—
—
—
5
ns
X0A, X1A
tWH1
tWL1
X0
X0, X1
HCLK1,
HCLK2
tWH2
tWL2
X0A
tCR
tCF
X0
X0, X1
HCLK1,
HCLK2
When the main CR clock
is used
TA = −40°C to −10°C
When the sub-oscillation
circuit is used
When the sub-external
kHz
clock is used
When the sub-CR clock
kHz
is used
When the main
ns
oscillation circuit is used
ns
ns When the external clock
is used
ns
—
tLCYL
When the main CR clock
is used
TA = −10°C to +85°C
kHz
—
FCRL
Clock cycle
time
Value
Typ
X0, X1
FCRH
FCL
Min
tCRHWK
—
—
—
—
80
µs
tCRLWK
—
—
—
—
10
µs
When the subclock is
used
When the external clock
is used, the duty ratio
should range between
40% and 60%.
When the external clock
is used
When the main CR clock
is used
When the sub-CR clock
is used
*: The external clock signal is input to X0 and the inverted external clock signal to X1.
DS07–12629–1E
33
MB95330H Series
tHCYL
tWH1
tWL1
tCR
tCF
X0, X1, HCLK1, HCLK2
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0
When the external clock is used When the external clock
(X1 is open)
is used
X0
X1
X1
X0
When the external clock
is used
X1
HCLK1/HCLK2
Open
FCH
FCH
FCH
FCH
tLCYL
tWH2
tCR
X0A
tWL2
tCF
0.8 VCC 0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of subclock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0A
X1A
FCL
When the external clock
is used
X0A
X1A
Open
FCL
34
DS07–12629–1E
MB95330H Series
(2) Source Clock/Machine Clock
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Source clock
cycle time*1
tSCLK
Pin
name
—
FSP
Source clock
frequency
—
FSPL
Machine clock
cycle time*2
(minimum
instruction
execution
time)
tMCLK
—
FMPL
Unit
Remarks
Min
Typ
Max
61.5
—
2000
ns
When the main external clock is used
Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
80
—
1000
ns
When the main CR clock is used
Min: FCRH = 12.5 MHz
Max: FCRH = 1 MHz
—
61
—
µs
When the sub-oscillation clock is used
FCL = 32.768 kHz, divided by 2
—
20
—
µs
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
0.5
—
16.25
MHz When the main oscillation clock is used
1
—
12.5
MHz When the main CR clock is used
—
16.384
—
kHz When the sub-oscillation clock is used
—
50
—
kHz
61.5
—
32000
ns
When the main oscillation clock is used
Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
80
—
16000
ns
When the main CR clock is used
Min: FSP = 12.5 MHz
Max: FSP = 1 MHz, divided by 16
61
—
976.5
µs
When the sub-oscillation clock is used
Min: FSPL = 16.384 kHz, no division
Max: FSPL = 16.384 kHz, divided by 16
20
—
320
µs
When the sub-CR clock is used
Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
0.031
—
16.25
MHz When the main oscillation clock is used
0.0625
—
12.5
MHz When the main CR clock is used
1.024
—
16.384
3.125
—
50
—
FMP
Machine clock
frequency
Value
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
kHz When the sub-oscillation clock is used
kHz
When the sub-CR clock is used
FCRL = 100 kHz
*1: This is the clock before it is divided according to the division ratio set by the machine clock divide ratio select
bits (SYCC:DIV1 and DIV0). This source clock is divided to become a machine clock according to the divide
ratio set by the machine clock divide ratio select bits (SYCC:DIV1 and DIV0). In addition, a source clock can
be selected from the following.
• Main clock divided by 2
• Main CR clock
• Subclock divided by 2
• Sub-CR clock divided by 2
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
DS07–12629–1E
35
MB95330H Series
• Schematic diagram of the clock generation block
Divided
by 2
FCH
(Main oscillation)
FCRH
(Main CR clock)
FCL
(Sub-oscillation)
FCRL
(Sub-CR clock)
SCLK
(Source clock)
Divided
by 2
Divided
by 2
Clock mode select bits
(SYCC2: RCS1, RCS0)
Division
circuit
× 1
× 1/4
× 1/8
×1/16
MCLK
(Machine clock)
Machine clock divide ratio select bits
(SYCC:DIV1, DIV0)
• Operating voltage - Operating frequency (When TA = −40°C to +85°C)
MB95330H (without the on-chip debug function)
5.5
Operating voltage (V)
5.0
A/D converter operation range
4.0
3.5
3.0
2.4
16 kHz
3 MHz
10 MHz
16.25 MHz
Source clock frequency (FSP/FSPL)
• Operating voltage - Operating frequency (When TA = −40°C to +85°C)
MB95330H (with the on-chip debug function)
5.5
Operating voltage (V)
5.0
A/D converter operation range
4.0
3.5
2.9
3.0
16 kHz
3 MHz
10 MHz
16.25 MHz
Source clock frequency (FSP)
36
DS07–12629–1E
MB95330H Series
(3) External Reset
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
RST “L” level
pulse width
tRSTL
Value
Unit
Remarks
Min
Max
2 tMCLK*1
—
ns
In normal operation
Oscillation time of the
oscillator*2 + 100
—
µs
In stop mode, subclock mode,
subsleep mode, watch mode, and
power-on
100
—
µs
In time-base timer mode
*1: See “(2) Source Clock/Machine Clock” for tMCLK.
*2: The oscillation time of an oscillator is the time for it to reach 90% of its amplitude. The crystal oscillator has
an oscillation time of between several ms and tens of ms. The ceramic oscillator has an oscillation time of
between hundreds of µs and several ms. The external clock has an oscillation time of 0 ms. The CR oscillator
clock has an oscillation time of between several µs and several ms.
• In normal operation
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode, subclock mode, subsleep mode, watch mode and power-on
tRSTL
RST
X0
0.2 VCC
0.2 VCC
90% of
amplitude
Internal
operating
clock
Oscillation
time of
oscillator
Internal reset
DS07–12629–1E
100 μs
Oscillation stabilization wait time
Execute instruction
37
MB95330H Series
(4) Power-on Reset
(VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Condition
Power supply rising time
tR
Power supply cutoff time
tOFF
tR
Value
Unit
Min
Max
—
—
50
ms
—
1
—
ms
Remarks
Wait time until power-on
tOFF
2.5 V
VCC
0.2 V
0.2 V
0.2 V
Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the
power supply voltage during the operation, set the slope of rising to a value below within 30 mV/ms as
shown below.
VCC
2.3 V
Set the slope of rising to
a value below 30 mV/ms.
Hold condition in stop mode
VSS
38
DS07–12629–1E
MB95330H Series
(5) Peripheral Input Timing
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Peripheral input “H” pulse width
tILIH
Peripheral input “L” pulse width
tIHIL
Value
Pin name
INT00 to INT09, EC0, EC1,TI1,
TRG1
Unit
Min
Max
2 tMCLK*
—
ns
2 tMCLK*
—
ns
*: See “(2) Source Clock/Machine Clock” for tMCLK.
tILIH
INT00 to INT07,
EC0, EC1, TI1,
TRG1
DS07–12629–1E
0.8 VCC
tIHIL
0.8 VCC
0.2 VCC
0.2 VCC
39
MB95330H Series
(6) LIN-UART Timing
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register: SCES bit = 0, ECCR register: SCDE bit = 0)
(VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↓ → SOT delay time
tSLOVI
SCK, SOT
Valid SIN → SCK ↑
tIVSHI
SCK, SIN
SCK ↑ → valid SIN hold time
tSHIXI
SCK, SIN
Value
Condition
Unit
Min
Max
5 tMCLK*3
—
ns
+95
ns
—
ns
—
ns
Internal clock
−95
operation output pin:
3
CL = 80 pF + 1 TTL tMCLK* + 190
0
Serial clock “L” pulse width
tSLSH
SCK
3t
* − tR
—
ns
Serial clock “H” pulse width
tSHSL
SCK
tMCLK*3 + 95
—
ns
SCK ↓ → SOT delay time
tSLOVE
SCK, SOT
—
2 tMCLK*3 + 95
ns
Valid SIN → SCK ↑
tIVSHE
SCK, SIN
190
—
ns
* + 95
—
ns
SCK ↑ → valid SIN hold time
tSHIXE
SCK, SIN
MCLK 3
External clock
operation output pin:
CL = 80 pF + 1 TTL
t
MCLK 3
SCK fall time
tF
SCK
—
10
ns
SCK rise time
tR
SCK
—
10
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “(2) Source Clock/Machine Clock” for tMCLK.
40
DS07–12629–1E
MB95330H Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
tSHIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
0.8 VCC
SCK
0.2 VCC
tF
0.2 VCC
tR
tSLOVE
2.4 V
SOT
0.8 V
tIVSHE
tSHIXE
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
DS07–12629–1E
41
MB95330H Series
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register: SCES bit = 1, ECCR register: SCDE bit = 0)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↑ → SOT delay time
tSHOVI
SCK, SOT
Valid SIN → SCK ↓
tIVSLI
SCK, SIN
SCK ↓ → valid SIN hold time
tSLIXI
SCK, SIN
Value
Condition
Unit
Min
Max
5 tMCLK*3
—
ns
+95
ns
—
ns
—
ns
Internal clock
−95
operation output pin:
3
CL = 80 pF + 1 TTL tMCLK* + 190
0
Serial clock “H” pulse width
tSHSL
SCK
3t
* − tR
—
ns
Serial clock “L” pulse width
tSLSH
SCK
tMCLK*3 + 95
—
ns
SCK ↑ → SOT delay time
tSHOVE
SCK, SOT
—
2 tMCLK*3 + 95
ns
Valid SIN → SCK ↓
tIVSLE
SCK, SIN
190
—
ns
* + 95
—
ns
SCK ↓ → valid SIN hold time
tSLIXE
SCK, SIN
MCLK 3
External clock
operation output pin:
CL = 80 pF + 1 TTL
t
MCLK 3
SCK fall time
tF
SCK
—
10
ns
SCK rise time
tR
SCK
—
10
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “(2) Source Clock/Machine Clock” for tMCLK.
42
DS07–12629–1E
MB95330H Series
• Internal shift clock mode
tSCYC
2.4 V
2.4 V
SCK
0.8 V
tSHOVI
2.4 V
SOT
0.8 V
tIVSLI
tSLIXI
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
• External shift clock mode
tSHSL
0.8 VCC
tSLSH
0.8 VCC
SCK
0.2 VCC
tR
tF
0.2 VCC
0.2 VCC
tSHOVE
2.4 V
SOT
0.8 V
tIVSLE
tSLIXE
0.8 VCC 0.8 VCC
SIN
0.2 VCC 0.2 VCC
DS07–12629–1E
43
MB95330H Series
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register: SCES bit = 0, ECCR register: SCDE bit = 1)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↑ → SOT delay time
tSHOVI
SCK, SOT
Valid SIN → SCK ↓
tIVSLI
SCK, SIN
SCK ↓ → valid SIN hold time
tSLIXI
SCK, SIN
SOT → SCK ↓ delay time
tSOVLI
SCK, SOT
Value
Condition
Unit
Min
Max
5 tMCLK*3
—
ns
+95
ns
—
ns
—
ns
4 tMCLK*3
ns
−95
Internal clock
operation output pin: tMCLK*3 + 190
CL = 80 pF + 1 TTL
0
—
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock.
*3: See “(2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
0.8 V
SOT
2.4 V
2.4 V
0.8 V
0.8 V
tIVSLI
SIN
44
0.8 V
tSHOVI
tSOVLI
tSLIXI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
DS07–12629–1E
MB95330H Series
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register: SCES bit = 1, ECCR register: SCDE bit = 1)
(VCC = 5.0 V±10%, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol Pin name
Serial clock cycle time
tSCYC
SCK
SCK ↓ → SOT delay time
tSLOVI
SCK, SOT
Valid SIN → SCK ↑
tIVSHI
SCK, SIN
SCK ↑ → valid SIN hold time
tSHIXI
SCK, SIN
SOT → SCK ↑ delay time
tSOVHI
Value
Condition
Unit
Min
Max
5 tMCLK*3
—
ns
+95
ns
—
ns
—
ns
−95
Internal clock
operation output pin: tMCLK*3 + 190
CL = 80 pF + 1 TTL
0
SCK, SOT
MCLK 3
—
4t
*
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock.
*3: See “(2) Source Clock/Machine Clock” for tMCLK.
tSCYC
2.4 V
SCK
2.4 V
0.8 V
tSOVHI
SOT
2.4 V
0.8 V
0.8 V
tIVSHI
SIN
DS07–12629–1E
tSLOVI
2.4 V
tSHIXI
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
45
MB95330H Series
(7) Low-voltage Detection
(VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Value
Symbol
Min
Typ
Max
Unit
Remarks
Release voltage
VDL+
2.52
2.7
2.88
V
At power supply rise
Detection voltage
VDL-
2.42
2.6
2.78
V
At power supply fall
Hysteresis width
VHYS
70
100
—
mV
Power supply start voltage
Voff
—
—
2.3
V
Power supply end voltage
Von
4.9
—
—
V
Power supply voltage
change time
(at power supply rise)
tr
3000
—
—
µs
Slope of power supply that the reset
release signal generates within the
rating (VDL+)
Power supply voltage
change time
(at power supply fall)
tf
300
—
—
µs
Slope of power supply that the reset
detection signal generates within the
rating (VDL-)
Reset release delay time
td1
—
—
300
µs
Reset detection delay time
td2
—
—
20
µs
VCC
Von
Voff
time
tf
tr
VDL+
VHYS
VDL-
Internal reset signal
time
td2
46
td1
DS07–12629–1E
MB95330H Series
(8) I2C Timing
(VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Value
Parameter
Standardmode
Fast-mode Unit
Min
Max
Min
Max
0
100
0
400
kHz
SCL, SDA
4.0
—
0.6
—
µs
Symbol Pin name Condition
SCL clock frequency
fSCL
(Repeated) START condition hold time
SDA ↓ → SCL ↓
tHD;STA
SCL
SCL clock “L” width
tLOW
SCL
4.7
—
1.3
—
µs
SCL clock “H” width
tHIGH
SCL
4.0
—
0.6
—
µs
4.7
—
0.6
—
µs
0
3.45*2
0
0.9*3
µs
(Repeated) START condition hold time
SCL ↑ → SDA ↓
tSU;STA
Data hold time
SCL ↓ → SDA ↓↑
tHD;DAT
SCL, SDA
Data setup time
SDA ↓↑ → SCL ↑
tSU;DAT
SCL, SDA
0.25
—
0.1
—
µs
STOP condition setup time
SCL ↑ → SDA ↑
tSU;STO
SCL, SDA
4
—
0.6
—
µs
tBUF
SCL, SDA
4.7
—
1.3
—
µs
Bus free time between STOP condition
and START condition
SCL, SDA
R = 1.7 kΩ,
C = 50 pF*1
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.
*2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding
the SCL signal at “L” (tLOW) does not extend.
*3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition
of tSU;DAT ≥ 250 ns is fulfilled.
tWAKEUP
SDA
tLOW
tHD;DAT
tHIGH
tHD;STA
tBUF
SCL
tHD;STA
tSU;DAT
fSCL
tSU;STA
tSU;STO
(Continued)
DS07–12629–1E
47
MB95330H Series
(VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Sym- Pin
Condition
bol name
Value*2
Min
Max
Unit
Remarks
SCL clock “L”
width
tLOW SCL
(2 + nm/2)tMCLK − 20
—
ns
Master mode
SCL clock “H”
width
tHIGH SCL
(nm/2)tMCLK − 20
(nm/2)tMCLK + 20
ns
Master mode
START
SCL,
condition hold tHD;STA
SDA
time
(−1 + nm/2)tMCLK − 20
(−1 + nm)tMCLK + 20
ns
Master mode
Maximum value
is applied when
m, n = 1, 8.
Otherwise, the
minimum value
is applied.
STOP
condition
setup time
tSU;STO
SCL,
SDA
(1 + nm/2)tMCLK − 20
(1 + nm/2)tMCLK + 20
ns
Master mode
START
condition
setup time
tSU;STA
SCL,
SDA
(1 + nm/2)tMCLK − 20
(1 + nm/2)tMCLK + 20
ns
Master mode
tBUF
SCL,
SDA
(2 nm + 4)tMCLK − 20
—
ns
tHD;DAT
SCL,
SDA
3 tMCLK − 20
—
ns
Master mode
ns
Master mode
When assuming
that “L” of SCL is
not extended,
the minimum
value is applied
to first bit of
continuous data.
Otherwise, the
maximum value
is applied.
ns
Minimum value
is applied to
interrupt at 9th
SCL↓. Maximum
value is applied
to the interrupt at
the 8th SCL↓.
Bus free time
between
STOP
condition and
START
condition
Data hold
time
Data setup
time
tSU;DAT
SCL,
SDA
Setup time
between
clearing inter- tSU;INT SCL
rupt and SCL
rising
R = 1.7 kΩ,
C = 50 pF*1
(−2 + nm/2)tMCLK − 20
(nm/2)tMCLK − 20
(−1 + nm/2)tMCLK + 20
(1 + nm/2)tMCLK + 20
(Continued)
48
DS07–12629–1E
MB95330H Series
(Continued)
Parameter
(VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Value*2
Sym- Pin
Unit
Remarks
Condition
bol name
Min
Max
SCL clock “L” width
tLOW
SCL
4 tMCLK − 20
—
ns
At reception
SCL clock “H” width
tHIGH
SCL
4 tMCLK − 20
—
ns
At reception
START condition
detection
tHD;STA
SCL,
SDA
2 tMCLK − 20
—
ns
Not detected when
1 tMCLK is used at
reception
STOP condition
detection
tSU;STO
SCL,
SDA
2 tMCLK − 20
—
ns
Not detected when
1 tMCLK is used at
reception
RESTART condition
SCL,
tSU;STA
detection condition
SDA
2 tMCLK − 20
—
ns
Not detected when
1 tMCLK is used at
reception
2 tMCLK − 20
—
ns
At reception
Bus free time
tBUF
SCL,
SDA
Data hold time
tHD;DAT
SCL,
SDA
2 tMCLK − 20
—
ns
At slave
transmission mode
Data setup time
tSU;DAT
SCL,
SDA
tLOW − 3 tMCLK − 20
—
ns
At slave
transmission mode
Data hold time
tHD;DAT
SCL,
SDA
0
—
ns
At reception
Data setup time
tSU;DAT
SCL,
SDA
tMCLK − 20
—
ns
At reception
Oscillation
stabilization wait
time
+2 tMCLK − 20
—
ns
SDA↓ → SCL↑
SCL,
tWAKEUP
(at wakeup function)
SDA
R = 1.7 kΩ,
C = 50 pF*1
*1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines.
See “(2) Source Clock/Machine Clock” for tMCLK.
m represents the CS4 bit and CS3 bit (bit4 and bit3) in the I2C clock control register (ICCR0).
n represents the CS2 bit to CS0 bit (bit2 to bit0) in the I2C clock control register (ICCR0).
The actual timing of I2C is determined by the values of m and n set by the machine clock (tMCLK) and the
CS4 to CS0 bits in the ICCR0 register.
• Standard-mode:
m and n can be set to values in the following range: 0.9 MHz < tMCLK (machine clock) < 10 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 0.9 MHz < tMCLK ≤ 1 MHz
(m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4)
: 0.9 MHz < tMCLK ≤ 2 MHz
(m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8)
: 0.9 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 98)
: 0.9 MHz < tMCLK ≤ 10 MHz
• Fast-mode:
m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 10 MHz.
The usable frequencies of the machine clock are determined by the settings of m and n as shown below.
(m, n) = (1, 8)
: 3.3 MHz < tMCLK ≤ 4 MHz
(m, n) = (1, 22), (5, 4)
: 3.3 MHz < tMCLK ≤ 8 MHz
(m, n) = (6, 4)
: 3.3 MHz < tMCLK ≤ 10 MHz
*2: •
•
•
•
DS07–12629–1E
49
MB95330H Series
(9) UART/SIO, Serial I/O Timing
Parameter
(VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Value
Pin name
Condition
Unit
Min
Max
Symbol
Serial clock cycle time
tSCYC
UCK0
UCK ↓ → UO time
tSLOV
UCK0, UO0
Valid UI → UCK ↑
tIVSH
UCK0, UI0
UCK ↑ → valid UI hold time
tSHIX
Serial clock “H” pulse width
Serial clock “L” pulse width
4 tMCLK*
—
ns
−190
+190
ns
2 tMCLK*
—
ns
UCK, UI0
2 tMCLK*
—
ns
tSHSL
UCK0
4 tMCLK*
—
ns
tSLSH
UCK0
4 tMCLK*
—
ns
—
190
ns
Internal clock
operation
External clock
operation
UCK ↓ → UO time
tSLOV
UCK0, UO0
Valid UI → UCK ↑
tIVSH
UCK0, UI0
2 tMCLK*
—
ns
UCK ↑ → valid UI hold time
tSHIX
UCK0, UI0
2 tMCLK*
—
ns
*: See “(2) Source Clock/Machine Clock” for tMCLK.
• Internal shift clock mode
tSCYC
2.4 V
UCK0
0.8 V
0.8 V
tSLOV
2.4 V
UC0
0.8 V
tIVSH
tSHIX
0.8 VCC 0.8 VCC
UI0
0.2 VCC 0.2 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
UCK0
0.2 VCC
0.2 VCC
tSLOV
2.4 V
UC0
0.8 V
tIVSH
tSHIX
0.8 VCC 0.8 VCC
UI0
0.2 VCC 0.2 VCC
50
DS07–12629–1E
MB95330H Series
(10) MPG Input Timing
Parameter
Symbol
Input pulse width
SNI1 to SNI2,
DTTI
tTIWH
tTIWL
(VCC = 5.0 V±10%, AVSS = VSS = 0.0 V, TA = −40°C to +85°C)
Value
Pin name
Condition
Unit Remarks
Min
Max
SNI0 to SNI2,
DTTI
0.8 VCC
4 tMCLK
—
ns
0.8 VCC
0.2 VCC
tTIWH
DS07–12629–1E
—
0.2 VCC
tTIWL
51
MB95330H Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(VCC = 4.0 V to 5.5 V, VSS = 0.0 V, TA = −40°C to +85°C)
Parameter
Symbol
Resolution
Total error
Linearity error
—
Differential linear
error
Value
Unit
Min
Typ
Max
—
—
10
bit
−3
—
+3
LSB
−2.5
—
+2.5
LSB
−1.9
—
+1.9
LSB
Remarks
Zero transition
voltage
VOT
VSS − 1.5 LSB VSS + 0.5 LSB VSS + 2.5 LSB
V
Full-scale transition
voltage
VFST
VCC − 4.5 LSB
VCC − 2 LSB
VCC + 0.5 LSB
V
0.9
—
16500
µs
4.5 V ≤ VCC ≤ 5.5 V
1.8
—
16500
µs
4.0 V ≤ VCC < 4.5 V
0.6
—
∞
µs
4.5 V ≤ VCC ≤ 5.5 V,
with external
impedance < 5.4 kΩ
1.2
—
∞
µs
4.0 V ≤ VCC < 4.5 V,
with external
impedance < 2.4 kΩ
Compare time
Sampling time
—
—
Analog input current
IAIN
−0.3
—
+0.3
µA
Analog input voltage
VAIN
VSS
—
VCC
V
52
DS07–12629–1E
MB95330H Series
(2) Notes on Using the A/D Converter
• External impedance of analog input and its sampling time
• The A/D converter has a sample and hold circuit. If the external impedance is too high to keep sufficient
sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is
insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision
standard, considering the relationship between the external impedance and minimum sampling time, either
adjust the register value and operating frequency or decrease the external impedance so that the sampling
time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect
a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
Analog input
Comparator
R
C
During sampling: ON
VCC
R
C
4.5 V ≤ VCC ≤ 5.5 V
1.95 kΩ (Max)
17 pF (Max)
4.0 V ≤ VCC < 4.5 V
8.98 kΩ (Max)
17 pF (Max)
Note: The values are reference values.
• Relationship between external impedance and minimum sampling time
[External impedance = 0 kΩ to 20 kΩ]
[External impedance = 0 kΩ to 100 kΩ]
20
External impedance [kΩ]
External impedance [kΩ]
100
90
80
70
60
(VCC ≥ 4.5 V)
50
(VCC ≥ 4.0 V)
40
30
20
10
18
16
14
12
(VCC ≥ 4.5 V)
10
(VCC ≥ 4.0 V)
8
6
4
2
0
0
0
2
4
6
8
10
12
Minimum sampling time [μs]
14
0
1
2
3
4
Minimum sampling time [μs]
• A/D conversion error
As |VCC−VSS| decreases, the A/D conversion error increases proportionately.
DS07–12629–1E
53
MB95330H Series
(3) Definitions of A/D Converter Terms
• Resolution
It indicates the level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
It indicates how much an actual conversion value deviates from the straight line connecting
the zero transition point (“00 0000 0000” ← → “00 0000 0001”) of a device to
the full-scale transition point (“11 1111 1111” ← → “11 1111 1110”) of the same device.
• Differential linear error (unit: LSB)
It indicates how much the input voltage required to change the output code by 1 LSB deviates from an
ideal value.
• Total error (unit: LSB)
It indicates the difference between an actual value and a theoretical value. The error can be caused by a
zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FFH
2 LSB
3FDH
Digital output
Digital output
3FDH
004H
003H
Actual conversion
characteristic
3FEH
3FEH
VOT
{1 LSB × (N-1) + 0.5 LSB}
004H
VNT
003H
1 LSB
002H
002H
001H
Actual conversion
characteristic
Ideal characteristic
001H
0.5 LSB
VSS
Analog input
1 LSB =
VCC - VSS
(V)
1024
N
VCC
VSS
Analog input
VCC
VNT - {1 LSB × (N - 1) + 0.5 LSB}
Total error of
=
[LSB]
digital output N
1 LSB
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
(Continued)
54
DS07–12629–1E
MB95330H Series
(Continued)
Zero transition error
Full-scale transition error
004H
Ideal characteristic
Actual conversion
characteristic
3FFH
Actual conversion
characteristic
002H
Digital output
Digital output
003H
Actual conversion
characteristic
Ideal
characteristic
3FEH
VFST
(measurement
value)
3FDH
Actual conversion
characteristic
001H
3FCH
VOT (measurement value)
VSS
Analog input
VCC
VSS
3FEH
Ideal characteristic
Actual conversion
characteristic
(N+1)H
Actual conversion
characteristic
{1 LSB × N + VOT}
VFST
(measurement
value)
VNT
004H
002H
Digital output
Digital output
3FDH
V(N+1)T
NH
VNT
(N-1)H
Actual conversion
characteristic
003H
VCC
Differential linearity error
Linearity error
3FFH
Analog input
Ideal
characteristic
Actual conversion
characteristic
(N-2)H
001H
VOT (measurement value)
VSS
Analog input
VCC
VNT - {1 LSB × N + VOT}
Linearity error
=
of digital output N
1 LSB
N
VSS
Analog input
VCC
V(N+1)T - VNT
Differential linear error
=
- 1
of digital output N
1 LSB
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N - 1)H to NH
VOT (ideal value) = VSS + 0.5 LSB [V]
VFST (ideal value) = VCC - 2 LSB [V]
DS07–12629–1E
55
MB95330H Series
6. Flash Memory Write/Erase Characteristics
Parameter
Value
Unit
Remarks
Min
Typ
Max
Sector erase time
(2 Kbyte sector)
—
0.2*1
0.5*2
s
The time of writing 00H prior to
erasure is excluded.
Sector erase time
(16 Kbyte sector)
—
0.5*1
7.5*2
s
The time of writing 00H prior to
erasure is excluded.
Byte writing time
—
21
6100*2
µs
System-level overhead is excluded.
Erase/write cycle
100000
—
—
cycle
Power supply voltage at erase/
write
3.0
—
5.5
V
Flash memory data retention
time
20*3
—
—
year Average TA = +85°C
*1: TA = +25°C, VCC = 5.0 V, 100000 cycles
*2: TA = +85°C, VCC = 3.0 V, 100000 cycles
*3: This value is converted from the result of a technology reliability assessment. (The value is converted from
the result of a high temperature accelerated test using the Arrhenius equation with the average temperature
being +85°C).
56
DS07–12629–1E
MB95330H Series
■ SAMPLE CHARACTERISTICS
• Power supply current temperature characteristics
ICC − VCC
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
ICC − TA
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
20
20
15
15
10
FMP = 10 MHz
FMP = 16 MHz
ICC[mA]
ICC[mA]
FMP = 16 MHz
10
FMP = 10 MHz
FMP = 8 MHz
5
5
FMP = 4 MHz
FMP = 2 MHz
0
−50
0
2
3
4
5
6
7
0
ICCS − VCC
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
20
20
15
15
10
5
FMP = 16 MHz
5
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
0
−50
0
3
4
5
6
7
FMP = 10 MHz
0
+50
+100
+150
TA[°C]
VCC[V]
ICCL − VCC
TA = +25°C, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
ICCL − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
100
100
75
75
ICCL[μA]
ICCL[μA]
+150
10
FMP = 16 MHz
2
+100
ICCS − TA
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
ICCS[mA]
ICCS[mA]
+50
TA[°C]
VCC[V]
50
50
25
25
0
0
2
3
4
5
VCC[V]
6
7
−50
0
+50
+100
+150
TA[°C]
(Continued)
DS07–12629–1E
57
MB95330H Series
ICCLS − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
100
100
75
75
ICCLS[μA]
ICCLS[μA]
ICCLS − VCC
TA = +25°C, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
50
50
25
25
0
0
2
3
4
5
6
−50
7
0
+100
+150
ICCT − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
100
100
75
75
ICCT[μA]
ICCT[μA]
ICCT − VCC
TA = +25°C, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
50
50
25
25
0
0
2
3
4
5
6
−50
7
0
+50
+100
+150
TA[°C]
VCC[V]
ICTS − VCC
TA = +25°C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock
operating
ICTS − TA
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock
operating
2
2
1.5
1.5
1
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
0.5
ICTS[mA]
ICTS[mA]
+50
TA[°C]
VCC[V]
1
FMP = 16 MHz
FMP = 10 MHz
0.5
FMP = 4 MHz
FMP = 2 MHz
0
0
2
3
4
5
VCC[V]
6
7
−50
0
+50
+100
+150
TA[°C]
(Continued)
58
DS07–12629–1E
MB95330H Series
(Continued)
ICCH − TA
VCC = 5.5 V, FMPL = (stop)
Substop mode with the external clock stopping
20
20
15
15
ICCH[μA]
ICCH[μA]
ICCH − VCC
TA = +25°C, FMPL = (stop)
Substop mode with the external clock stopping
10
10
5
5
0
0
2
3
4
5
6
−50
7
0
ICCMCR − VCC
TA = +25°C, FMP = 1, 8, 10, 12.5 MHz (no division)
Main clock mode with the main CR clock operating
20
20
15
15
FMP = 12.5 MHz
10
FMP = 10 MHz
FMP = 8 MHz
+150
FMP = 12.5 MHz
10
FMP = 10 MHz
FMP = 8 MHz
5
5
FMP = 1 MHz
FMP = 1 MHz
0
0
2
3
4
5
6
−50
7
0
+50
+100
+150
TA[°C]
VCC[V]
ICCSCR − VCC
TA = +25°C, FMPL = 50 kHz (divided by 2)
Subclock mode with the sub-CR clock operating
ICCSCR − TA
VCC = 5.5 V FMPL = 50 kHz (divided by 2)
Subclock mode with the sub-CR clock operating
140
140
120
120
FMPL = 50 kHz
FMPL = 50 kHz
100
100
ICCSCR[μA]
ICCSCR[μA]
+100
ICCMCR − TA
VCC = 5.5 V FMP = 1, 8, 10, 12.5 MHz (no division)
Main clock mode with the main CR clock operating
ICCMCR[mA]
ICCMCR[mA]
+50
TA[°C]
VCC[V]
80
60
80
60
40
40
20
20
0
0
2
3
4
5
VCC[V]
DS07–12629–1E
6
7
−50
0
+50
+100
+150
TA[°C]
59
MB95330H Series
• Input voltage characteristics
VIHI − VCC and VILI − VCC
TA = +25°C
VIHS − VCC and VILS − VCC
TA = +25°C
4
4
3
3
VIHS
VIHS/VILS[V]
VIHI/VILI[V]
VIHI
VILI
2
1
VILS
2
1
0
0
2
3
4
5
6
2
3
VCC[V]
4
5
6
VCC[V]
VIHM − VCC and VILM − VCC
TA = +25°C
4
VIHM/VILM[V]
3
VIHM
VILM
2
1
0
2
3
4
5
6
VCC[V]
60
DS07–12629–1E
MB95330H Series
• Output voltage characteristics
(VCC − VOH1) − IOH
TA = +25°C
VCC = 2.4 V
2
(VCC − VOH2) − IOH
TA = +25°C
VCC = 2.7 V
VCC = 2.4 V
1
1.8
1.6
0.8
1.2
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
1
0.8
VCC - VOH2[V]
VCC -VOH1[V]
VCC = 2.7 V
VCC = 3.5 V
1.4
0.6
VCC = 3.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
0.4
0.6
0.4
0.2
0.2
0
0
−2
0
−4
−6
−8
−10
0
−2
−4
IOH[mA]
VOL1 − IOL
TA = +25°C
VCC = 2.4 V
2
−6
−8
−10
IOH[mA]
VOL2 − IOL
TA = +25°C
1
VCC = 2.7 V
1.8
0.8
1.6
1.4
0.6
VOL2[V]
VOL1[V]
1.2
1
VCC = 2.4 V
0.4
0.8
VCC = 3.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
0.6
0.4
VCC = 2.7 V
VCC = 3.5 V
VCC = 5.0 V
VCC = 4.5 V
VCC = 5.5 V
0.2
0.2
0
0
0
2
4
6
IOL[mA]
DS07–12629–1E
8
10
0
2
4
6
8
10
IOL[mA]
61
MB95330H Series
• Pull-up characteristics
RPULL − VCC
TA = +25°C
250
RPULL[kΩ]
200
150
100
50
0
2
3
4
5
6
VCC[V]
62
DS07–12629–1E
MB95330H Series
■ MASK OPTIONS
No.
Part Number
MB95F332H
MB95F333H
MB95F334H
Selectable/Fixed
MB95F332K
MB95F333K
MB95F334K
Fixed
1
Low-voltage detection reset Without low-voltage detection reset
2
Reset
DS07–12629–1E
With dedicated reset input
With low-voltage detection reset
Without dedicated reset input
63
MB95330H Series
■ ORDERING INFORMATION
Part Number
Package
MB95F332HPMC-G-SNE2
MB95F332KPMC-G-SNE2
MB95F333HPMC-G-SNE2
MB95F333KPMC-G-SNE2
MB95F334HPMC-G-SNE2
MB95F334KPMC-G-SNE2
32-pin plastic LQFP
(FPT-32P-M30)
MB95F332HP-G-SH-SNE2
MB95F332KP-G-SH-SNE2
MB95F333HP-G-SH-SNE2
MB95F333KP-G-SH-SNE2
MB95F334HP-G-SH-SNE2
MB95F334KP-G-SH-SNE2
32-pin plastic SH-DIP
(DIP-32P-M06)
MB95F332HWQN-G-SNE1
MB95F332KWQN-G-SNE1
MB95F333HWQN-G-SNE1
MB95F333KWQN-G-SNE1
MB95F334HWQN-G-SNE1
MB95F334KWQN-G-SNE1
32-pin plastic QFN
(LCC-32P-M19)
64
DS07–12629–1E
MB95330H Series
■ PACKAGE DIMENSION
32-pin plastic LQFP
Lead pitch
0.80 mm
Package width ×
package length
7.00 mm × 7.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.60 mm MAX
(FPT-32P-M30)
32-pin plastic LQFP
(FPT-32P-M30)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00±0.20(.354±.008)SQ
+0.05
* 7.00±0.10(.276±.004)SQ
0.13 –0.00
+.002
24
.005 –.000
17
16
25
0.10(.004)
Details of "A" part
1.60 MAX
(Mounting height)
(.063) MAX
INDEX
0.25(.010)
9
32
0~7˚
1
0.80(.031)
.014
C
"A"
8
+0.08
0.35 –0.03
+.003
–.001
0.20(.008)
0.60±0.15
(.024±.006)
0.10±0.05
(.004±.002)
M
2009 FUJITSU MICROELECTRONICS LIMITED F32051S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS07–12629–1E
65
MB95330H Series
32-pin plastic SH-DIP
Lead pitch
1.778 mm
Low space
10.16 mm
Sealing method
Plastic mold
(DIP-32P-M06)
32-pin plastic SH-DIP
(DIP-32P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
+0.20
*28.00 –0.30
1.102
+.008
–.012
INDEX
*8.89±0.25
(.350±.010)
1.02
+0.30
–0.20
+.012
.040 –.008
+0.70
4.70 –0.20
0.51(.020)
MIN.
+.028
.185 –.008
3.30
+0.20
–0.30
+.008
.130 –.012
+0.03
0.27 –0.07
+.001
.011 –.003
1.27(.050)
MAX.
C
1.778(.070)
10.16(.400)
+0.08
0.48 –0.12
+.003
0.25(.010)
M
.019 –.005
2003-2008 FUJITSU MICROELECTRONICS LIMITED D32018S-c-1-2
0~15°
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
66
DS07–12629–1E
MB95330H Series
(Continued)
32-pin plastic QFN
Lead pitch
0.50 mm
Package width ×
package length
5.00 mm × 5.00 mm
Sealing method
Plastic mold
Mounting height
0.80 mm MAX
Weight
0.06 g
(LCC-32P-M19)
32-pin plastic QFN
(LCC-32P-M19)
3.50±0.10
(.138±.004)
5.00±0.10
(.197±.004)
5.00±0.10
(.197±.004)
3.50±0.10
(.138±.004)
INDEX AREA
0.25
(.010
(3-R0.20)
((3-R.008))
0.50(.020)
+0.05
–0.07
+.002
–.003
)
0.40±0.05
(.016±.002)
1PIN CORNER
(C0.30(C.012))
(TYP)
0.75±0.05
(.030±.002)
0.02
(.001
C
+0.03
–0.02
+.001
–.001
(0.20(.008))
)
2009 FUJITSU MICROELECTRONICS LIMITED C32071S-c-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS07–12629–1E
67
MB95330H Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
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