4.3 MB

The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS702-00010-5v0-E
8-bit Microcontrollers
New 8FX MB95560H/570H/580H Series
MB95F562H/F562K/F563H/F563K/F564H/F564K
MB95F572H/F572K/F573H/F573K/F574H/F574K
MB95F582H/F582K/F583H/F583K/F584H/F584K
■ DESCRIPTION
The MB95560H/570H/580H Series is a series of general-purpose, single-chip microcontrollers. In addition
to a compact instruction set, the microcontrollers of this series contain a variety of peripheral resources.
■ FEATURES
• F2MC-8FX CPU core
Instruction set optimized for controllers
• Multiplication and division instructions
• 16-bit arithmetic operations
• Bit test branch instructions
• Bit manipulation instructions, etc.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
• Clock (The main oscillation clock and the suboscillation clock are only available on MB95F562H/F562K/
F563H/F563K/F564H/F564K/F582H/F582K/F583H/F583K/F584H/F584K.)
• Selectable main clock source
- Main oscillation clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz)
- External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz)
- Main CR clock (4 MHz ± 2%)
- The main CR clock frequency becomes 8 MHz when the PLL multiplication rate is 2.
- The main CR clock frequency becomes 10 MHz when the PLL multiplication rate is 2.5.
- The main CR clock frequency becomes 12 MHz when the PLL multiplication rate is 3.
- The main CR clock frequency becomes 16 MHz when the PLL multiplication rate is 4.
• Selectable subclock source
- Suboscillation clock (32.768 kHz)
- External clock (32.768 kHz)
- Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz)
• Timer
• 8/16-bit composite timer × 2 channels (only one channel on MB95F572H/F572K/F573H/F573K/F574H/
F574K/F582H/F582K/F583H/F583K/F584H/F584K)
• Time-base timer × 1 channel
• Watch prescaler × 1 channel
(Continued)
FUJITSU SEMICONDUCTOR provides information facilitating product development via the following website.
The website contains information useful for customers.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2011-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2013.5
MB95560H/570H/580H Series
(Continued)
• LIN-UART (only available on MB95F562H/F562K/F563H/F563K/F564H/F564K/F582H/F582K/F583H/
F583K/F584H/F584K)
• Full duplex double buffer
• Capable of clock synchronous serial data transfer and clock asynchronous serial data transfer
• External interrupt
• Interrupt by edge detection (rising edge, falling edge, and both edges can be selected)
• Can be used to wake up the device from different low power consumption (standby) modes
• 8/10-bit A/D converter
8-bit or 10-bit resolution can be selected.
• Low power consumption (standby) modes
There are four standby modes as follows:
• Stop mode
• Sleep mode
• Watch mode
• Time-base timer mode
In standby mode, the device can be made to enter either normal standby mode or deep standby mode.
• I/O port
• MB95F562H/F563H/F564H (maximum no. of I/O ports: 16)
- General-purpose I/O ports (CMOS I/O)
: 15
- General-purpose I/O ports (N-ch open drain)
:1
• MB95F562K/F563K/F564K (maximum no. of I/O ports: 17)
- General-purpose I/O ports (CMOS I/O)
: 15
- General-purpose I/O ports (N-ch open drain)
:2
• MB95F572H/F573H/F574H (maximum no. of I/O ports: 4)
- General-purpose I/O ports (CMOS I/O)
:3
- General-purpose I/O ports (N-ch open drain)
:1
• MB95F572K/F573K/F574K (maximum no. of I/O ports: 5)
- General-purpose I/O ports (CMOS I/O)
:3
- General-purpose I/O ports (N-ch open drain)
:2
• MB95F582H/F583H/F584H (maximum no. of I/O ports: 12)
- General-purpose I/O ports (CMOS I/O)
: 11
- General-purpose I/O ports (N-ch open drain)
:1
• MB95F582K/F583K/F584K (maximum no. of I/O ports: 13)
- General-purpose I/O ports (CMOS I/O)
: 11
- General-purpose I/O ports (N-ch open drain)
:2
• On-chip debug
• 1-wire serial control
• Serial writing supported (asynchronous mode)
• Hardware/software watchdog timer
• Built-in hardware watchdog timer
• Built-in software watchdog timer
• Power-on reset
A power-on reset is generated when the power is switched on.
• Low-voltage detection reset circuit (only available on MB95F562K/F563K/F564K/F572K/F573K/F574K/
F582K/F583K/F584K)
Built-in low-voltage detector
• Clock supervisor counter
Built-in clock supervisor counter function
• Dual operation Flash memory
The program/erase operation and the read operation can be executed in different banks (upper bank/lower
bank) simultaneously.
• Flash memory security function
Protects the content of the Flash memory.
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DS702-00010-5v0-E
MB95560H/570H/580H Series
■ PRODUCT LINE-UP
• MB95560H Series
Part number
MB95F562H
MB95F563H
MB95F564H
MB95F562K
MB95F563K
MB95F564K
Parameter
Type
Flash memory product
Clock
supervisor
It supervises the main clock oscillation.
counter
Flash memory
8 Kbyte
12 Kbyte
20 Kbyte
8 Kbyte
12 Kbyte
20 Kbyte
capacity
RAM capacity
240 bytes
496 bytes
496 bytes
240 bytes
496 bytes
496 bytes
Power-on reset
Yes
Low-voltage
No
Yes
detection reset
Reset input
Dedicated
Selected through software
• Number of basic instructions
: 136
• Instruction bit length
: 8 bits
• Instruction length
: 1 to 3 bytes
CPU functions
• Data bit length
: 1, 8 and 16 bits
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max) : 17
• I/O ports (Max) : 16
General• CMOS I/O
: 15
• CMOS I/O
: 15
purpose I/O
• N-ch open drain: 1
• N-ch open drain: 2
Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz)
• Reset generation cycle
Hardware/
software
Main oscillation clock at 10 MHz: 105 ms (Min)
watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace 3 bytes of data.
• A wide range of communication speed can be selected by a dedicated reload timer.
• It has a full duplex double buffer.
LIN-UART
• Both clock synchronous serial data transfer and clock asynchronous serial data transfer are
enabled.
• The LIN function can be used as a LIN master or a LIN slave.
6 channels
8/10-bit A/D
converter
8-bit or 10-bit resolution can be selected.
2 channels
• The timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel".
8/16-bit
• It has the following functions: interval timer function, PWC function, PWM function and input
composite timer capture function.
• Count clock: it can be selected from internal clocks (7 types) and external clocks.
• It can output square wave.
6 channels
External
• Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
• It can be used to wake up the device from the standby mode.
• 1-wire serial control
On-chip debug
• It supports serial writing (asynchronous mode).
(Continued)
DS702-00010-5v0-E
3
MB95560H/570H/580H Series
(Continued)
Part number
MB95F562H
MB95F563H
MB95F564H
MB95F562K
MB95F563K
MB95F564K
Parameter
Watch prescaler Eight different time intervals can be selected.
• It supports automatic programming (Embedded Algorithm), and program/erase/erasesuspend/erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
Flash memory • Flash security feature for protecting the content of the Flash memory
Number of program/erase cycles
Data retention time
1000
10000
100000
20 years
10 years
5 years
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
LCC-32P-M19
Package
FPT-20P-M09
FPT-20P-M10
4
DS702-00010-5v0-E
MB95560H/570H/580H Series
• MB95570H Series
Part number
MB95F572H
MB95F573H
MB95F574H
MB95F572K
MB95F573K
MB95F574K
Parameter
Type
Flash memory product
Clock
supervisor
It supervises the main clock oscillation.
counter
Flash memory
8 Kbyte
12 Kbyte
20 Kbyte
8 Kbyte
12 Kbyte
20 Kbyte
capacity
RAM capacity
240 bytes
496 bytes
496 bytes
240 bytes
496 bytes
496 bytes
Power-on reset
Yes
Low-voltage
No
Yes
detection reset
Reset input
Dedicated
Selected through software
• Number of basic instructions
: 136
• Instruction bit length
: 8 bits
• Instruction length
: 1 to 3 bytes
CPU functions
• Data bit length
: 1, 8 and 16 bits
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max) : 5
• I/O ports (Max) : 4
General• CMOS I/O
:3
• CMOS I/O
:3
purpose I/O
• N-ch open drain: 1
• N-ch open drain: 2
Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz)
• Reset generation cycle
Hardware/
software
Main oscillation clock at 10 MHz: 105 ms (Min)
watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace 3 bytes of data.
LIN-UART
No LIN-UART
2 channels
8/10-bit A/D
converter
8-bit or 10-bit resolution can be selected.
1 channel
• The timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel".
8/16-bit
• It has the following functions: interval timer function, PWC function, PWM function and input
composite timer capture function.
• Count clock: it can be selected from internal clocks (7 types) and external clocks.
• It can output square wave.
2 channels
External
• Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
• It can be used to wake up the device from the standby mode.
• 1-wire serial control
On-chip debug
• It supports serial writing (asynchronous mode).
Watch prescaler Eight different time intervals can be selected.
• It supports automatic programming (Embedded Algorithm), and program/erase/erasesuspend/erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
Flash memory • Flash security feature for protecting the content of the Flash memory
Number of program/erase cycles
Data retention time
1000
10000
100000
20 years
10 years
5 years
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
DIP-8P-M03
Package
FPT-8P-M08
DS702-00010-5v0-E
5
MB95560H/570H/580H Series
• MB95580H Series
Part number
MB95F582H
MB95F583H
MB95F584H
MB95F582K
MB95F583K
MB95F584K
Parameter
Type
Flash memory product
Clock
supervisor
It supervises the main clock oscillation.
counter
Flash memory
8 Kbyte
12 Kbyte
20 Kbyte
8 Kbyte
12 Kbyte
20 Kbyte
capacity
RAM capacity
240 bytes
496 bytes
496 bytes
240 bytes
496 bytes
496 bytes
Power-on reset
Yes
Low-voltage
No
Yes
detection reset
Reset input
Dedicated
Selected through software
• Number of basic instructions
: 136
• Instruction bit length
: 8 bits
• Instruction length
: 1 to 3 bytes
CPU functions
• Data bit length
: 1, 8 and 16 bits
• Minimum instruction execution time : 61.5 ns (machine clock frequency = 16.25 MHz)
• Interrupt processing time
: 0.6 µs (machine clock frequency = 16.25 MHz)
• I/O ports (Max) : 13
• I/O ports (Max) : 12
General• CMOS I/O
: 11
• CMOS I/O
: 11
purpose I/O
• N-ch open drain: 1
• N-ch open drain: 2
Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz)
• Reset generation cycle
Hardware/
software
Main oscillation clock at 10 MHz: 105 ms (Min)
watchdog timer • The sub-CR clock can be used as the source clock of the hardware watchdog timer.
Wild register
It can be used to replace 3 bytes of data.
• A wide range of communication speed can be selected by a dedicated reload timer.
• It has a full duplex double buffer.
LIN-UART
• Both clock synchronous serial data transfer and clock asynchronous serial data transfer are
enabled.
• The LIN function can be used as a LIN master or a LIN slave.
5 channels
8/10-bit A/D
converter
8-bit or 10-bit resolution can be selected.
1 channel
• The timer can be configured as an "8-bit timer × 2 channels" or a "16-bit timer × 1 channel".
8/16-bit
• It has the following functions: interval timer function, PWC function, PWM function and input
composite timer capture function.
• Count clock: it can be selected from internal clocks (7 types) and external clocks.
• It can output square wave.
6 channels
External
• Interrupt by edge detection (The rising edge, falling edge, or both edges can be selected.)
interrupt
• It can be used to wake up the device from the standby mode.
• 1-wire serial control
On-chip debug
• It supports serial writing (asynchronous mode).
(Continued)
6
DS702-00010-5v0-E
MB95560H/570H/580H Series
(Continued)
Part number
MB95F582H
MB95F583H
MB95F584H
MB95F582K
MB95F583K
MB95F584K
Parameter
Watch prescaler Eight different time intervals can be selected.
• It supports automatic programming (Embedded Algorithm), and program/erase/erasesuspend/erase-resume commands.
• It has a flag indicating the completion of the operation of Embedded Algorithm.
Flash memory • Flash security feature for protecting the content of the Flash memory
Number of program/erase cycles
Data retention time
1000
10000
100000
20 years
10 years
5 years
Standby mode Sleep mode, stop mode, watch mode, time-base timer mode
LCC-32P-M19
Package
FPT-16P-M08
FPT-16P-M23
DS702-00010-5v0-E
7
MB95560H/570H/580H Series
■ PACKAGES AND CORRESPONDING PRODUCTS
• MB95560H Series
Part number
MB95F562H
MB95F562K
MB95F563H
MB95F563K
MB95F564H
MB95F564K
Ο
Ο
Ο
X
X
X
X
Ο
Ο
Ο
X
X
X
X
Ο
Ο
Ο
X
X
X
X
Ο
Ο
Ο
X
X
X
X
Ο
Ο
Ο
X
X
X
X
Ο
Ο
Ο
X
X
X
X
MB95F572H
MB95F572K
MB95F573H
MB95F573K
MB95F574H
MB95F574K
X
X
X
X
X
Ο
Ο
X
X
X
X
X
Ο
Ο
X
X
X
X
X
Ο
Ο
X
X
X
X
X
Ο
Ο
X
X
X
X
X
Ο
Ο
X
X
X
X
X
Ο
Ο
MB95F582H
MB95F582K
MB95F583H
MB95F583K
MB95F584H
MB95F584K
Ο
X
X
Ο
Ο
X
X
Ο
X
X
Ο
Ο
X
X
Ο
X
X
Ο
Ο
X
X
Ο
X
X
Ο
Ο
X
X
Ο
X
X
Ο
Ο
X
X
Ο
X
X
Ο
Ο
X
X
Package
LCC-32P-M19
FPT-20P-M09
FPT-20P-M10
FPT-16P-M08
FPT-16P-M23
DIP-8P-M03
FPT-8P-M08
• MB95570H Series
Part number
Package
LCC-32P-M19
FPT-20P-M09
FPT-20P-M10
FPT-16P-M08
FPT-16P-M23
DIP-8P-M03
FPT-8P-M08
• MB95580H Series
Part number
Package
LCC-32P-M19
FPT-20P-M09
FPT-20P-M10
FPT-16P-M08
FPT-16P-M23
DIP-8P-M03
FPT-8P-M08
Ο: Available
X: Unavailable
8
DS702-00010-5v0-E
MB95560H/570H/580H Series
■ DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION
• Current consumption
When using the on-chip debug function, take account of the current consumption of Flash memory program/
erase.
For details of current consumption, see “■ ELECTRICAL CHARACTERISTICS”.
• Package
For details of information on each package, see “■ PACKAGES AND CORRESPONDING PRODUCTS” and
“■ PACKAGE DIMENSION”.
• Operating voltage
The operating voltage varies, depending on whether the on-chip debug function is used or not.
For details of the operating voltage, see “■ ELECTRICAL CHARACTERISTICS”.
• On-chip debug function
The on-chip debug function requires that VCC, VSS and one serial wire be connected to an evaluation tool.
For details of the connection method, refer to “CHAPTER 21 EXAMPLE OF SERIAL PROGRAMMING
CONNECTION” in “New 8FX MB95560H/570H/580H Series Hardware Manual”.
DS702-00010-5v0-E
9
MB95560H/570H/580H Series
32
31
30
29
28
27
26
25
NC
NC
NC
NC
NC
NC
NC
NC
■ PIN ASSIGNMENT
X0/PF0
X1/PF1
Vss
X1A/PG2
X0A/PG1
Vcc
C
RST/PF2
TO10/P62
TO11/P63
1
2
3
4
5
6
7
8
9
10
16
P64/EC1
The number of usable pins is 20.
14
15
8
LCC-32P-M19
(MB95560H Series)
NC
P00/AN00
RST/PF2
(TOP VIEW)
9
10
11
12
13
C
1
2
3
4
5
6
7
TO11/P63
TO10/P62
NC
NC
NC
X1/PF1
X0/PF0
VSS
X1A/PG2
X0A/PG1
Vcc
(TOP VIEW)
FPT-20P-M09
FPT-20P-M10
(MB95560H Series)
24
23
P07/INT07
P12/EC0/DBG
22
21
20
19
P06/INT06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
P03/INT03/AN03/SOT
18
P02/INT02/AN02/SCK
17
P01/AN01
20
19
18
17
16
15
14
13
12
11
P12/EC0/DBG
P07/INT07
P06/INT06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
P03/INT03/AN03/SOT
P02/INT02/AN02/SCK
P01/AN01
P00/AN00
P64/EC1
(Continued)
10
DS702-00010-5v0-E
MB95560H/570H/580H Series
X0/PF0
X1/PF1
Vss
X1A/PG2
X0A/PG1
Vcc
RST/PF2
C
1
2
3
4
5
6
7
8
Vss
Vcc
C
RST/PF2
1
2
3
4
DS702-00010-5v0-E
NC
NC
NC
NC
NC
NC
NC
NC
25
14
15
16
NC
The number of usable pins is 16.
NC
7
8
24
23
P07/INT07
P12/EC0/DBG
22
19
P06/INT06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
P03/INT03/AN03/SOT
18
17
P02/INT02/AN02/SCK
P01/AN01
21
LCC-32P-M19
(MB95580H Series) 20
NC
C
RST/PF2
(TOP VIEW)
9
10
11
12
13
1
2
3
4
5
6
NC
NC
NC
NC
NC
X1/PF1
X0/PF0
VSS
X1A/PG2
X0A/PG1
Vcc
32
31
30
29
28
27
26
(Continued)
(TOP VIEW)
FPT-16P-M08
FPT-16P-M23
(MB95580H Series)
(TOP VIEW)
DIP-8P-M03
FPT-8P-M08
(MB95570H Series)
16
15
14
13
12
11
10
9
8
7
6
5
P12/EC0/DBG
P07/INT07
P06/INT06/TO01
P05/INT05/AN05/TO00
P04/INT04/AN04/SIN/EC0
P03/INT03/AN03/SOT
P01/AN01
P02/INT02/AN02/SCK
P12/EC0/DBG
P06/INT06/TO01
P05/AN05/TO00
P04/INT04/AN04/EC0
11
MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95560H Series, 32 pins)
Pin no.
1
2
3
4
5
Pin name
PF1
X1
PF0
X0
VSS
PG2
X1A
PG1
X0A
I/O
circuit
type*
B
B
—
C
C
Function
General-purpose I/O port
Main clock I/O oscillation pin
General-purpose I/O port
Main clock input oscillation pin
Power supply pin (GND)
General-purpose I/O port
Subclock I/O oscillation pin
General-purpose I/O port
Subclock input oscillation pin
6
VCC
—
Power supply pin
7
C
—
Decoupling capacitor connection pin
PF2
8
9
RST
P63
General-purpose I/O port
A
E
TO11
10
P62
Reset pin
Dedicated reset pin on MB95F562H/F563H/F564H
General-purpose I/O port
High-current pin
8/16-bit composite timer ch. 1 output pin
E
TO10
General-purpose I/O port
High-current pin
8/16-bit composite timer ch. 1 output pin
11
12
13
NC
—
It is an internally connected pin. Always leave it unconnected.
D
General-purpose I/O port
High-current pin
14
15
P00
AN00
16
P64
A/D converter analog input pin
E
EC1
17
P01
8/16-bit composite timer ch. 1 clock input pin
D
AN01
INT02
General-purpose I/O port
High-current pin
A/D converter analog input pin
General-purpose I/O port
High-current pin
P02
18
General-purpose I/O port
High-current pin
D
External interrupt input pin
AN02
A/D converter analog input pin
SCK
LIN-UART clock I/O pin
(Continued)
12
DS702-00010-5v0-E
MB95560H/570H/580H Series
(Continued)
Pin no.
Pin name
I/O
circuit
type*
General-purpose I/O port
High-current pin
P03
19
20
21
INT03
D
A/D converter analog input pin
SOT
LIN-UART data output pin
P04
General-purpose I/O port
INT04
External interrupt input pin
AN04
D
LIN-UART data input pin
EC0
8/16-bit composite timer ch. 0 clock input pin
P05
General-purpose I/O port
High-current pin
INT05
D
External interrupt input pin
AN05
A/D converter analog input pin
TO00
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
High-current pin
INT06
E
EC0
External interrupt input pin
8/16-bit composite timer ch. 0 output pin
P12
24
A/D converter analog input pin
SIN
TO01
23
External interrupt input pin
AN03
P06
22
Function
General-purpose I/O port
F
8/16-bit composite timer ch. 0 clock input pin
DBG
DBG input pin
P07
General-purpose I/O port
High-current pin
E
INT07
External interrupt input pin
25
26
27
28
29
NC
—
It is an internally connected pin. Always leave it unconnected.
30
31
32
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
DS702-00010-5v0-E
13
MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95560H Series, 20 pins)
Pin no.
1
2
3
4
5
Pin name
PF0
X0
PF1
X1
VSS
PG2
X1A
PG1
X0A
I/O
circuit
type*
B
B
—
C
C
Function
General-purpose I/O port
Main clock input oscillation pin
General-purpose I/O port
Main clock I/O oscillation pin
Power supply pin (GND)
General-purpose I/O port
Subclock I/O oscillation pin
General-purpose I/O port
Subclock input oscillation pin
6
VCC
—
Power supply pin
7
C
—
Decoupling capacitor connection pin
PF2
8
9
RST
P62
General-purpose I/O port
A
E
TO10
10
P63
P64
E
P00
E
P01
D
D
15
General-purpose I/O port
High-current pin
A/D converter analog input pin
General-purpose I/O port
High-current pin
P02
INT02
General-purpose I/O port
High-current pin
A/D converter analog input pin
AN01
14
General-purpose I/O port
High-current pin
8/16-bit composite timer ch. 1 clock input pin
AN00
13
General-purpose I/O port
High-current pin
8/16-bit composite timer ch. 1 output pin
EC1
12
General-purpose I/O port
High-current pin
8/16-bit composite timer ch. 1 output pin
TO11
11
Reset pin
Dedicated reset pin on MB95F562H/F563H/F564H
D
External interrupt input pin
AN02
A/D converter analog input pin
SCK
LIN-UART clock I/O pin
P03
General-purpose I/O port
High-current pin
INT03
D
External interrupt input pin
AN03
A/D converter analog input pin
SOT
LIN-UART data output pin
(Continued)
14
DS702-00010-5v0-E
MB95560H/570H/580H Series
(Continued)
Pin no.
16
17
Pin name
I/O
circuit
type*
P04
General-purpose I/O port
INT04
External interrupt input pin
AN04
D
LIN-UART data input pin
EC0
8/16-bit composite timer ch. 0 clock input pin
P05
General-purpose I/O port
High-current pin
INT05
D
20
External interrupt input pin
AN05
A/D converter analog input pin
TO00
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
High-current pin
INT06
E
TO01
19
A/D converter analog input pin
SIN
P06
18
Function
P07
External interrupt input pin
8/16-bit composite timer ch. 0 output pin
E
General-purpose I/O port
High-current pin
INT07
External interrupt input pin
P12
General-purpose I/O port
EC0
DBG
F
8/16-bit composite timer ch. 0 clock input pin
DBG input pin
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
DS702-00010-5v0-E
15
MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95570H Series, 8 pins)
Pin no.
Pin name
I/O
circuit
type*
1
VSS
—
Power supply pin (GND)
2
VCC
—
Power supply pin
3
C
—
Decoupling capacitor connection pin
PF2
4
RST
General-purpose I/O port
A
P04
5
6
INT04
AN04
D
External interrupt input pin
A/D converter analog input pin
EC0
8/16-bit composite timer ch. 0 clock input pin
P05
General-purpose I/O port
High-current pin
AN05
D
INT06
General-purpose I/O port
High-current pin
E
TO01
DBG
External interrupt input pin
8/16-bit composite timer ch. 0 output pin
P12
EC0
A/D converter analog input pin
8/16-bit composite timer ch. 0 output pin
P06
8
Reset pin
Dedicated reset pin on MB95F572H/F573H/F574H
General-purpose I/O port
TO00
7
Function
General-purpose I/O port
F
8/16-bit composite timer ch. 0 clock input pin
DBG input pin
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
16
DS702-00010-5v0-E
MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95580H Series, 32 pins)
Pin no.
1
2
3
4
5
Pin name
PF1
X1
PF0
X0
VSS
PG2
X1A
PG1
X0A
I/O
circuit
type*
B
B
—
C
C
Function
General-purpose I/O port
Main clock I/O oscillation pin
General-purpose I/O port
Main clock input oscillation pin
Power supply pin (GND)
General-purpose I/O port
Subclock I/O oscillation pin
General-purpose I/O port
Subclock input oscillation pin
6
VCC
—
Power supply pin
7
C
—
Decoupling capacitor connection pin
PF2
8
RST
General-purpose I/O port
A
Reset pin
Dedicated reset pin on MB95F582H/F583H/F584H
—
It is an internally connected pin. Always leave it unconnected.
D
General-purpose I/O port
High-current pin
9
10
11
12
13
NC
14
15
16
17
P01
AN01
A/D converter analog input pin
General-purpose I/O port
High-current pin
P02
18
19
INT02
D
External interrupt input pin
AN02
A/D converter analog input pin
SCK
LIN-UART clock I/O pin
P03
General-purpose I/O port
High-current pin
INT03
D
External interrupt input pin
AN03
A/D converter analog input pin
SOT
LIN-UART data output pin
(Continued)
DS702-00010-5v0-E
17
MB95560H/570H/580H Series
(Continued)
Pin no.
20
21
Pin name
I/O
circuit
type*
P04
General-purpose I/O port
INT04
External interrupt input pin
AN04
D
LIN-UART data input pin
EC0
8/16-bit composite timer ch. 0 clock input pin
P05
General-purpose I/O port
High-current pin
INT05
D
A/D converter analog input pin
TO00
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
High-current pin
INT06
E
EC0
External interrupt input pin
8/16-bit composite timer ch. 0 output pin
P12
24
External interrupt input pin
AN05
TO01
23
A/D converter analog input pin
SIN
P06
22
Function
General-purpose I/O port
F
8/16-bit composite timer ch. 0 clock input pin
DBG
DBG input pin
P07
General-purpose I/O port
High-current pin
E
INT07
External interrupt input pin
25
26
27
28
29
NC
—
It is an internally connected pin. Always leave it unconnected.
30
31
32
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
18
DS702-00010-5v0-E
MB95560H/570H/580H Series
■ PIN FUNCTIONS (MB95580H Series, 16 pins)
Pin no.
1
2
3
4
5
6
Pin name
PF0
X0
PF1
X1
VSS
PG2
X1A
PG1
X0A
VCC
I/O
circuit
type*
B
B
—
C
C
—
PF2
7
8
RST
C
10
INT02
General-purpose I/O port
Main clock I/O oscillation pin
Power supply pin (GND)
General-purpose I/O port
Subclock I/O oscillation pin
General-purpose I/O port
Subclock input oscillation pin
Power supply pin
Reset pin
Dedicated reset pin on MB95F582H/F583H/F584H
—
Decoupling capacitor connection pin
General-purpose I/O port
High-current pin
D
External interrupt input pin
AN02
A/D converter analog input pin
SCK
LIN-UART clock I/O pin
P01
D
INT03
General-purpose I/O port
High-current pin
A/D converter analog input pin
General-purpose I/O port
High-current pin
P03
12
Main clock input oscillation pin
General-purpose I/O port
AN01
11
General-purpose I/O port
A
P02
9
Function
D
External interrupt input pin
AN03
A/D converter analog input pin
SOT
LIN-UART data output pin
P04
General-purpose I/O port
INT04
External interrupt input pin
AN04
D
A/D converter analog input pin
SIN
LIN-UART data input pin
EC0
8/16-bit composite timer ch. 0 clock input pin
(Continued)
DS702-00010-5v0-E
19
MB95560H/570H/580H Series
(Continued)
Pin no.
Pin name
I/O
circuit
type*
General-purpose I/O port
High-current pin
P05
13
INT05
D
A/D converter analog input pin
TO00
8/16-bit composite timer ch. 0 output pin
General-purpose I/O port
High-current pin
INT06
E
TO01
15
16
External interrupt input pin
AN05
P06
14
Function
P07
External interrupt input pin
8/16-bit composite timer ch. 0 output pin
E
General-purpose I/O port
High-current pin
INT07
External interrupt input pin
P12
General-purpose I/O port
EC0
DBG
F
8/16-bit composite timer ch. 0 clock input pin
DBG input pin
*: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”.
20
DS702-00010-5v0-E
MB95560H/570H/580H Series
■ I/O CIRCUIT TYPE
Type
Circuit
A
Remarks
Reset input / Hysteresis input
Reset output / Digital output
• N-ch open drain output
• Hysteresis input
• Reset output
N-ch
B
P-ch
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
Clock input
• Oscillation circuit
• High-speed side
Feedback resistance:
approx. 1 MΩ
• CMOS output
• Hysteresis input
X1
X0
Standby control / Port select
P-ch
Port select
Digital output
N-ch
Digital output
Standby control
Hysteresis input
C
Port select
R
Pull-up control
P-ch
P-ch
• Oscillation circuit
• Low-speed side
Feedback resistance:
approx.10 MΩ
Digital output
N-ch
Digital output
Standby control
Hysteresis input
• CMOS output
• Hysteresis input
• Pull-up control available
Clock input
X1A
X0A
Standby control / Port select
Port select
R
Pull-up control
Digital output
P-ch
Digital output
N-ch
Digital output
Standby control
Hysteresis input
(Continued)
DS702-00010-5v0-E
21
MB95560H/570H/580H Series
(Continued)
Type
Circuit
Remarks
D
Pull-up control
R
P-ch
Digital output
P-ch
•
•
•
•
CMOS output
Hysteresis input
Pull-up control available
Analog input
Digital output
N-ch
Analog input
A/D control
Standby control
Hysteresis input
E
Pull-up control
R
P-ch
• CMOS output
• Hysteresis input
• Pull-up control available
Digital output
P-ch
Digital output
N-ch
Standby control
Hysteresis input
F
Standby control
Hysteresis input
• N-ch open drain output
• Hysteresis input
Digital output
N-ch
22
DS702-00010-5v0-E
MB95560H/570H/580H Series
■ HANDLING PRECAUTIONS
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected
by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page
describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability
from your FUJITSU SEMICONDUCTOR semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
• Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
• Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand.
• Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent
such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause
large current flows. Such conditions if present for extended periods of time can damage the device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such
pins should be connected through an appropriate resistance to a power supply pin or ground pin.
Code: DS00-00004-2E
DS702-00010-5v0-E
23
MB95560H/570H/580H Series
• Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be
formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply
pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
• Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
• Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage
or loss from such failures by incorporating safety design measures into your facility and equipment such as
redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.
• Precautions Related to Usage of Devices
FUJITSU SEMICONDUCTOR semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or abnormal
operation may directly affect human lives or cause physical injury or property damage, or where extremely
high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales
representatives before such use. The company will not be responsible for damages arising from such use
without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under FUJITSU SEMICONDUCTOR’s recommended conditions.
For detailed information about mount conditions, contact your sales representative.
• Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board
and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering
process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage
temperature. Mounting processes should conform to FUJITSU SEMICONDUCTOR recommended mounting
conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
24
DS702-00010-5v0-E
MB95560H/570H/580H Series
• Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads
are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results
in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. FUJITSU SEMICONDUCTOR recommends the solder
reflow method, and has established a ranking of mounting conditions for each product. Users are advised
to mount packages in accordance with FUJITSU SEMICONDUCTOR ranking of recommended conditions.
• Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
• Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To
prevent, do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5 °C and 30 °C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, FUJITSU SEMICONDUCTOR packages semiconductor devices in highly moistureresistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum
laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
• Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the FUJITSU
SEMICONDUCTOR recommended conditions for baking.
Condition: 125 °C/24 h
• Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%.
Use of an apparatus for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize
shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
DS702-00010-5v0-E
25
MB95560H/570H/580H Series
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely
affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to
protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of FUJITSU SEMICONDUCTOR products in other special environmental
conditions should consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://edevice.fujitsu.com/fj/handling-e.pdf
26
DS702-00010-5v0-E
MB95560H/570H/580H Series
■ NOTES ON DEVICE HANDLING
• Preventing latch-ups
When using the device, ensure that the voltage applied does not exceed the maximum voltage rating.
In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that
is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating
range of power supply voltage mentioned in "1. Absolute Maximum Ratings" of "■ ELECTRICAL
CHARACTERISTICS" is applied to the VCC pin or the VSS pin, a latch-up may occur.
When a latch-up occurs, power supply current increases significantly, which may cause a component to be
thermally destroyed.
• Stabilizing supply voltage
Supply voltage must be stabilized.
A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within
the guaranteed operating range of the VCC power supply voltage.
As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value)
at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient
fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply.
• Notes on using the external clock
When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up
from subclock mode or stop mode.
■ PIN CONNECTION
• Treatment of unused pins
If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions
or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 kΩ. Set an
unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it
the same as an unused input pin. If there is an unused output pin, leave it unconnected.
• Power supply pins
To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase
in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS
pin to the power supply and ground outside the device. In addition, connect the current supply source to the
VCC pin and the VSS pin with low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 µF as a decoupling capacitor between
the VCC pin and the VSS pin at a location close to this device.
• DBG pin
Connect the DBG pin to an external pull-up resistor of 2 kΩ or above.
After power-on, ensure that the DBG pin does not stay at “L” level until the reset output is released.
The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends
on the tool used and the interconnection length, refer to the tool document when selecting a pull-up resistor.
• RST pin
Connect the RST pin to an external pull-up resistor of 2 kΩ or above.
To prevent the device from unintentionally entering the reset mode due to noise, minimize the interconnection length between a pull-up resistor and the RST pin and that between a pull-up resistor and the VCC pin
when designing the layout of the printed circuit board.
The PF2/RST pin functions as the reset input/output pin after power-on. In addition, the reset output of the
PF2/RST pin can be enabled by the RSTOE bit in the SYSC register, and the reset input function and the
general purpose I/O function can be selected by the RSTEN bit in the SYSC register.
DS702-00010-5v0-E
27
MB95560H/570H/580H Series
• C pin
Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The decoupling capacitor
for the VCC pin must have a capacitance equal to or larger than the capacitance of CS. For the connection to
a decoupling capacitor CS, see the diagram below. To prevent the device from unintentionally entering a
mode to which the device is not set to transit due to noise, minimize the distance between the C pin and CS
and the distance between CS and the VSS pin when designing the layout of a printed circuit board.
• DBG/RST/C pins connection diagram
DBG
C
RST
Cs
28
DS702-00010-5v0-E
MB95560H/570H/580H Series
■ BLOCK DIAGRAM (MB95560H Series)
F2MC-8FX CPU
PF2*1/RST*2
Dual operation Flash with
security function
(8/12/20 Kbyte)
Reset with LVD
PF1/X1*2
PF0/X0*2
PG2/X1A*2
Oscillator
circuit
CR
oscillator
RAM (240/496 bytes)
PG1/X0A*2
Interrupt controller
Clock control
On-chip debug
Wild register
P02*3/INT02 to P07*3/INT07
Internal bus
(P12*1/DBG)
(P05*3/TO00)
8/16-bit composite timer ch. 0
(P06*3/TO01)
P12*1/EC0, (P04/EC0)
8/10-bit A/D converter
(P00*3/AN00 to P05*3/AN05)
External interrupt
(P62*3/TO10)
(P02*3/SCK)
(P03*3/SOT)
8/16-bit composite timer ch. 1
LIN-UART
(P63*3/TO11)
P64*3/EC1
(P04/SIN)
C
Port
Port
Vcc
Vss
*1: PF2 and P12 are N-ch open drain pins.
*2: Software option
*3: P00 to P03, P05 to P07 and P62 to P64 are high-current pins.
Note: Pins in parentheses indicate that functions of those pins are shared among different resources.
DS702-00010-5v0-E
29
MB95560H/570H/580H Series
■ BLOCK DIAGRAM (MB95570H Series)
F2MC-8FX CPU
PF2*1/RST*2
Dual operation Flash with
security function
(8/12/20 Kbyte)
Reset with LVD
RAM (240/496 bytes)
CR oscillator
Clock control
(P12*1/DBG)
On-chip debug
Internal bus
Interrupt controller
(P05*3/TO00)
8/16-bit composite timer ch. 0
(P06*3/TO01)
P12*1/EC0, (P04/EC0)
Wild register
8/10-bit A/D converter
P04/INT04, P06*3/INT06
P05*3/AN05, (P04/AN04)
External interrupt
C
Port
Port
Vcc
Vss
*1: PF2 and P12 are N-ch open drain pins.
*2: Software option
*3: P05 and P06 are high-current pins.
Note: Pins in parentheses indicate that functions of those pins are shared among different resources.
30
DS702-00010-5v0-E
MB95560H/570H/580H Series
■ BLOCK DIAGRAM (MB95580H Series)
F2MC-8FX CPU
PF2*1/RST*2
Dual operation Flash with
security function
(8/12/20 Kbyte)
Reset with LVD
PF1/X1*2
PF0/X0*2
PG2/X1A*2
Oscillator
circuit
CR
oscillator
RAM (240/496 bytes)
PG1/X0A*2
Interrupt controller
Clock control
On-chip debug
Wild register
P02*3/INT02 to P07*3/INT07
Internal bus
(P12*1/DBG)
(P05*3/TO00)
8/16-bit composite timer ch. 0
(P06*3/TO01)
P12*1/EC0, (P04/EC0)
8/10-bit A/D converter
(P01*3/AN01 to P05*3/AN05)
External interrupt
(P02*3/SCK)
(P03*3/SOT)
LIN-UART
(P04/SIN)
C
Port
Port
Vcc
Vss
*1: PF2 and P12 are N-ch open drain pins.
*2: Software option
*3: P01 to P03 and P05 to P07 are high-current pins.
Note: Pins in parentheses indicate that functions of those pins are shared among different resources.
DS702-00010-5v0-E
31
MB95560H/570H/580H Series
■ CPU CORE
• Memory space
The memory space of the MB95560H/570H/580H Series is 64 Kbyte in size, and consists of an I/O area, a
data area, and a program area. The memory space includes areas intended for specific purposes such as
general-purpose registers and a vector table. The memory maps of the MB95560H/570H/580H Series are
shown below.
• Memory maps
MB95F562H/F562K/F572H/
F572K/F582H/F582K
0000H
MB95F563H/F563K/F573H/
F573K/F583H/F583K
0000H
I/O area
0080H
0090H
0100H
0180H
Access prohibited
RAM 240 bytes
Register
Access prohibited
0F80H
Flash 4 Kbyte
Access prohibited
F000H
FFFFH
32
Access prohibited
Flash 4 Kbyte
I/O area
0F80H
C000H
Access prohibited
Extension I/O area
1000H
Access prohibited
B000H
Access prohibited
RAM 496 bytes
Register
0200H
0280H
Extension I/O area
1000H
Access prohibited
C000H
Access prohibited
RAM 496 bytes
0080H
0090H
0100H
Register
0200H
0280H
Extension I/O area
B000H
0000H
I/O area
0080H
0090H
0100H
0F80H
1000H
MB95F564H/F564K/F574H/
F574K/F584H/F584K
Flash 4 Kbyte
Access prohibited
B000H
Access prohibited
Flash 20 Kbyte
E000H
Flash 8 Kbyte
FFFFH
FFFFH
DS702-00010-5v0-E
MB95560H/570H/580H Series
■ I/O MAP (MB95560H Series)
Address
Register
abbreviation
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
—
—
—
0005H
WATR
Oscillation stabilization wait time setting register
R/W
11111111B
0006H
PLLC
PLL control register
R/W
000X0000B
0007H
SYCC
System clock control register
R/W
XXX11011B
0008H
STBC
Standby control register
R/W
00000000B
0009H
RSRR
Reset source register
R/W 000XXXXXB
000AH
TBTC
Time-base timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00XX0000B
000DH
SYCC2
System clock control register 2
R/W XXXX0011B
000EH
STBC2
Standby control register 2
R/W
00000000B
000FH
to
0015H
—
—
—
0016H
PDR6
Port 6 data register
R/W
00000000B
0017H
DDR6
Port 6 direction register
R/W
00000000B
0018H
to
0027H
—
—
—
0028H
PDRF
Port F data register
R/W
00000000B
0029H
DDRF
Port F direction register
R/W
00000000B
002AH
PDRG
Port G data register
R/W
00000000B
002BH
DDRG
Port G direction register
R/W
00000000B
002CH
PUL0
Port 0 pull-up register
R/W
00000000B
002DH
to
0032H
—
—
—
0033H
PUL6
R/W
00000000B
0034H
—
—
—
0035H
PULG
Port G pull-up register
R/W
00000000B
0036H
T01CR1
8/16-bit composite timer 01 status control register 1
R/W
00000000B
0037H
T00CR1
8/16-bit composite timer 00 status control register 1
R/W
00000000B
0038H
T11CR1
8/16-bit composite timer 11 status control register 1
R/W
00000000B
0039H
T10CR1
8/16-bit composite timer 10 status control register 1
R/W
00000000B
003AH
to
0048H
—
—
—
Register name
(Disabled)
(Disabled)
(Disabled)
(Disabled)
Port 6 pull-up register
(Disabled)
(Disabled)
R/W Initial value
(Continued)
DS702-00010-5v0-E
33
MB95560H/570H/580H Series
Address
Register
abbreviation
0049H
EIC10
External interrupt circuit control register ch. 2/ch. 3
R/W
00000000B
004AH
EIC20
External interrupt circuit control register ch. 4/ch. 5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch. 6/ch. 7
R/W
00000000B
004CH,
004DH
—
—
—
004EH
LVDR
R/W
00000000B
004FH
—
—
—
0050H
SCR
LIN-UART serial control register
R/W
00000000B
0051H
SMR
LIN-UART serial mode register
R/W
00000000B
0052H
SSR
LIN-UART serial status register
R/W
00001000B
RDR
LIN-UART receive data register
R/W
00000000B
TDR
LIN-UART transmit data register
R/W
00000000B
0053H
Register name
(Disabled)
LVDR reset voltage selection ID register
(Disabled)
R/W Initial value
0054H
ESCR
LIN-UART extended status control register
R/W
00000100B
0055H
ECCR
LIN-UART extended communication control register
R/W
000000XXB
0056H
to
006BH
—
—
—
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register (upper)
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register (lower)
R/W
00000000B
0070H
—
—
—
0071H
FSR2
Flash memory status register 2
R/W
00000000B
0072H
FSR
Flash memory status register
R/W
000X0000B
0073H
SWRE0
Flash memory sector write control register 0
R/W
00000000B
0074H
FSR3
Flash memory status register 3
R
000XXXXXB
0075H
FSR4
Flash memory status register 4
R/W
00000000B
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
—
—
—
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
ILR3
Interrupt level setting register 3
R/W
11111111B
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
—
—
—
0F80H
WRARH0
Wild register address setting register (upper) ch. 0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (lower) ch. 0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch. 0
R/W
00000000B
(Disabled)
(Disabled)
Mirror of register bank pointer (RP) and direct bank pointer
(DP)
(Disabled)
(Continued)
34
DS702-00010-5v0-E
MB95560H/570H/580H Series
Address
Register
abbreviation
0F83H
WRARH1
Wild register address setting register (upper) ch. 1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (lower) ch. 1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch. 1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (upper) ch. 2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (lower) ch. 2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch. 2
R/W
00000000B
0F89H
to
0F91H
—
—
—
0F92H
T01CR0
8/16-bit composite timer 01 status control register 0
R/W
00000000B
0F93H
T00CR0
8/16-bit composite timer 00 status control register 0
R/W
00000000B
0F94H
T01DR
8/16-bit composite timer 01 data register
R/W
00000000B
0F95H
T00DR
8/16-bit composite timer 00 data register
R/W
00000000B
0F96H
TMCR0
8/16-bit composite timer 00/01 timer mode control register
R/W
00000000B
0F97H
T11CR0
8/16-bit composite timer 11 status control register 0
R/W
00000000B
0F98H
T10CR0
8/16-bit composite timer 10 status control register 0
R/W
00000000B
0F99H
T11DR
8/16-bit composite timer 11 data register
R/W
00000000B
0F9AH
T10DR
8/16-bit composite timer 10 data register
R/W
00000000B
0F9BH
TMCR1
8/16-bit composite timer 10/11 timer mode control register
R/W
00000000B
0F9CH
to
0FBBH
—
—
—
0FBCH
BGR1
LIN-UART baud rate generator register 1
R/W
00000000B
0FBDH
BGR0
LIN-UART baud rate generator register 0
R/W
00000000B
0FBEH
to
0FC2H
—
—
—
0FC3H
AIDRL
R/W
00000000B
0FC4H
to
0FE3H
—
—
—
0FE4H
CRTH
Main CR clock trimming register (upper)
R/W 000XXXXXB
0FE5H
CRTL
Main CR clock trimming register (lower)
R/W 000XXXXXB
0FE6H
—
0FE7H
CRTDA
0FE8H
Register name
(Disabled)
(Disabled)
(Disabled)
A/D input disable register (lower)
(Disabled)
(Disabled)
R/W Initial value
—
—
Main CR clock temperature dependent adjustment register
R/W 000XXXXXB
SYSC
System configuration register
R/W
11000011B
0FE9H
CMCR
Clock monitoring control register
R/W
00000000B
0FEAH
CMDR
Clock monitoring data register
R
00000000B
(Continued)
DS702-00010-5v0-E
35
MB95560H/570H/580H Series
(Continued)
Address
Register
abbreviation
0FEBH
WDTH
Watchdog timer selection ID register (upper)
R
XXXXXXXXB
0FECH
WDTL
Watchdog timer selection ID register (lower)
R
XXXXXXXXB
0FEDH
to
0FFFH
—
—
—
Register name
(Disabled)
R/W Initial value
• R/W access symbols
R/W : Readable / Writable
R
: Read only
• Initial value symbols
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is undefined.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
36
DS702-00010-5v0-E
MB95560H/570H/580H Series
■ I/O MAP (MB95570H Series)
Address
Register
abbreviation
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
—
—
—
0005H
WATR
Oscillation stabilization wait time setting register
R/W
11111111B
0006H
PLLC
PLL control register
R/W
000X0000B
0007H
SYCC
System clock control register
R/W
XXX11011B
0008H
STBC
Standby control register
R/W
00000000B
0009H
RSRR
Reset source register
R/W 000XXXXXB
000AH
TBTC
Time-base timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00XX0000B
000DH
SYCC2
System clock control register 2
R/W XXXX0011B
000EH
STBC2
Standby control register 2
R/W
00000000B
000FH
to
0027H
—
—
—
0028H
PDRF
Port F data register
R/W
00000000B
0029H
DDRF
Port F direction register
R/W
00000000B
002AH,
002BH
—
—
—
002CH
PUL0
R/W
00000000B
002DH
to
0035H
—
—
—
0036H
T01CR1
8/16-bit composite timer 01 status control register 1
R/W
00000000B
0037H
T00CR1
8/16-bit composite timer 00 status control register 1
R/W
00000000B
0038H
to
0049H
—
—
—
004AH
EIC20
External interrupt circuit control register ch. 4/ch. 5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch. 6/ch. 7
R/W
00000000B
004CH,
004DH
—
—
—
004EH
LVDR
R/W
00000000B
004FH
to
006BH
—
—
—
Register name
(Disabled)
(Disabled)
(Disabled)
Port 0 pull-up register
(Disabled)
(Disabled)
(Disabled)
LVDR reset voltage selection ID register
(Disabled)
R/W Initial value
(Continued)
DS702-00010-5v0-E
37
MB95560H/570H/580H Series
Address
Register
abbreviation
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register (upper)
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register (lower)
R/W
00000000B
0070H
—
—
—
0071H
FSR2
Flash memory status register 2
R/W
00000000B
0072H
FSR
Flash memory status register
R/W
000X0000B
0073H
SWRE0
Flash memory sector write control register 0
R/W
00000000B
0074H
FSR3
Flash memory status register 3
R
000XXXXXB
0075H
FSR4
Flash memory status register 4
R/W
00000000B
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
—
—
—
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH,
007CH
—
—
—
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
—
—
—
0F80H
WRARH0
Wild register address setting register (upper) ch. 0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (lower) ch. 0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch. 0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (upper) ch. 1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (lower) ch. 1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch. 1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (upper) ch. 2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (lower) ch. 2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch. 2
R/W
00000000B
0F89H
to
0F91H
—
—
—
0F92H
T01CR0
8/16-bit composite timer 01 status control register 0
R/W
00000000B
0F93H
T00CR0
8/16-bit composite timer 00 status control register 0
R/W
00000000B
0F94H
T01DR
8/16-bit composite timer 01 data register
R/W
00000000B
0F95H
T00DR
8/16-bit composite timer 00 data register
R/W
00000000B
0F96H
TMCR0
8/16-bit composite timer 00/01 timer mode control register
R/W
00000000B
0F97H
to
0FC2H
—
—
—
Register name
(Disabled)
Mirror of register bank pointer (RP) and direct bank pointer
(DP)
(Disabled)
(Disabled)
(Disabled)
(Disabled)
R/W Initial value
(Continued)
38
DS702-00010-5v0-E
MB95560H/570H/580H Series
(Continued)
Address
Register
abbreviation
0FC3H
AIDRL
0FC4H
to
0FE3H
—
0FE4H
CRTH
Main CR clock trimming register (upper)
R/W 000XXXXXB
0FE5H
CRTL
Main CR clock trimming register (lower)
R/W 000XXXXXB
0FE6H
—
0FE7H
CRTDA
0FE8H
Register name
A/D input disable register (lower)
(Disabled)
(Disabled)
R/W Initial value
R/W
00000000B
—
—
—
—
Main CR clock temperature dependent adjustment register
R/W 000XXXXXB
SYSC
System configuration register
R/W
11000011B
0FE9H
CMCR
Clock monitoring control register
R/W
00000000B
0FEAH
CMDR
Clock monitoring data register
R
00000000B
0FEBH
WDTH
Watchdog timer selection ID register (upper)
R
XXXXXXXXB
0FECH
WDTL
Watchdog timer selection ID register (lower)
R
XXXXXXXXB
0FEDH
to
0FFFH
—
—
—
(Disabled)
• R/W access symbols
R/W : Readable / Writable
R
: Read only
• Initial value symbols
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is undefined.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
DS702-00010-5v0-E
39
MB95560H/570H/580H Series
■ I/O MAP (MB95580H Series)
Address
Register
abbreviation
0000H
PDR0
Port 0 data register
R/W
00000000B
0001H
DDR0
Port 0 direction register
R/W
00000000B
0002H
PDR1
Port 1 data register
R/W
00000000B
0003H
DDR1
Port 1 direction register
R/W
00000000B
0004H
—
—
—
0005H
WATR
Oscillation stabilization wait time setting register
R/W
11111111B
0006H
PLLC
PLL control register
R/W
000X0000B
0007H
SYCC
System clock control register
R/W
XXX11011B
0008H
STBC
Standby control register
R/W
00000000B
0009H
RSRR
Reset source register
R/W 000XXXXXB
000AH
TBTC
Time-base timer control register
R/W
00000000B
000BH
WPCR
Watch prescaler control register
R/W
00000000B
000CH
WDTC
Watchdog timer control register
R/W
00XX0000B
000DH
SYCC2
System clock control register 2
R/W XXXX0011B
000EH
STBC2
Standby control register 2
R/W
00000000B
000FH
to
0027H
—
—
—
0028H
PDRF
Port F data register
R/W
00000000B
0029H
DDRF
Port F direction register
R/W
00000000B
002AH
PDRG
Port G data register
R/W
00000000B
002BH
DDRG
Port G direction register
R/W
00000000B
002CH
PUL0
Port 0 pull-up register
R/W
00000000B
002DH
to
0034H
—
—
—
0035H
PULG
Port G pull-up register
R/W
00000000B
0036H
T01CR1
8/16-bit composite timer 01 status control register 1
R/W
00000000B
0037H
T00CR1
8/16-bit composite timer 00 status control register 1
R/W
00000000B
0038H
to
0048H
—
—
—
0049H
EIC10
External interrupt circuit control register ch. 2/ch. 3
R/W
00000000B
004AH
EIC20
External interrupt circuit control register ch. 4/ch. 5
R/W
00000000B
004BH
EIC30
External interrupt circuit control register ch. 6/ch. 7
R/W
00000000B
004CH,
004DH
—
—
—
004EH
LVDR
R/W
00000000B
004FH
—
—
—
Register name
(Disabled)
(Disabled)
(Disabled)
(Disabled)
(Disabled)
LVDR reset voltage selection ID register
(Disabled)
R/W Initial value
(Continued)
40
DS702-00010-5v0-E
MB95560H/570H/580H Series
Address
Register
abbreviation
0050H
SCR
LIN-UART serial control register
R/W
00000000B
0051H
SMR
LIN-UART serial mode register
R/W
00000000B
0052H
SSR
LIN-UART serial status register
R/W
00001000B
RDR
LIN-UART receive data register
R/W
00000000B
TDR
LIN-UART transmit data register
R/W
00000000B
0053H
Register name
R/W Initial value
0054H
ESCR
LIN-UART extended status control register
R/W
00000100B
0055H
ECCR
LIN-UART extended communication control register
R/W
000000XXB
0056H
to
006BH
—
—
—
006CH
ADC1
8/10-bit A/D converter control register 1
R/W
00000000B
006DH
ADC2
8/10-bit A/D converter control register 2
R/W
00000000B
006EH
ADDH
8/10-bit A/D converter data register (upper)
R/W
00000000B
006FH
ADDL
8/10-bit A/D converter data register (lower)
R/W
00000000B
0070H
—
—
—
0071H
FSR2
Flash memory status register 2
R/W
00000000B
0072H
FSR
Flash memory status register
R/W
000X0000B
0073H
SWRE0
Flash memory sector write control register 0
R/W
00000000B
0074H
FSR3
Flash memory status register 3
R
000XXXXXB
0075H
FSR4
Flash memory status register 4
R/W
00000000B
0076H
WREN
Wild register address compare enable register
R/W
00000000B
0077H
WROR
Wild register data test setting register
R/W
00000000B
0078H
—
—
—
0079H
ILR0
Interrupt level setting register 0
R/W
11111111B
007AH
ILR1
Interrupt level setting register 1
R/W
11111111B
007BH
ILR2
Interrupt level setting register 2
R/W
11111111B
007CH
—
—
—
007DH
ILR4
Interrupt level setting register 4
R/W
11111111B
007EH
ILR5
Interrupt level setting register 5
R/W
11111111B
007FH
—
—
—
0F80H
WRARH0
Wild register address setting register (upper) ch. 0
R/W
00000000B
0F81H
WRARL0
Wild register address setting register (lower) ch. 0
R/W
00000000B
0F82H
WRDR0
Wild register data setting register ch. 0
R/W
00000000B
0F83H
WRARH1
Wild register address setting register (upper) ch. 1
R/W
00000000B
0F84H
WRARL1
Wild register address setting register (lower) ch. 1
R/W
00000000B
0F85H
WRDR1
Wild register data setting register ch. 1
R/W
00000000B
0F86H
WRARH2
Wild register address setting register (upper) ch. 2
R/W
00000000B
0F87H
WRARL2
Wild register address setting register (lower) ch. 2
R/W
00000000B
0F88H
WRDR2
Wild register data setting register ch. 2
R/W
00000000B
(Disabled)
(Disabled)
Mirror of register bank pointer (RP) and direct bank pointer
(DP)
(Disabled)
(Disabled)
(Continued)
DS702-00010-5v0-E
41
MB95560H/570H/580H Series
(Continued)
Address
Register
abbreviation
Register name
0F89H
to
0F91H
—
(Disabled)
0F92H
T01CR0
0F93H
R/W Initial value
—
—
8/16-bit composite timer 01 status control register 0
R/W
00000000B
T00CR0
8/16-bit composite timer 00 status control register 0
R/W
00000000B
0F94H
T01DR
8/16-bit composite timer 01 data register
R/W
00000000B
0F95H
T00DR
8/16-bit composite timer 00 data register
R/W
00000000B
0F96H
TMCR0
8/16-bit composite timer 00/01 timer mode control register
R/W
00000000B
0F97H
to
0FBBH
—
—
—
0FBCH
BGR1
LIN-UART baud rate generator register 1
R/W
00000000B
0FBDH
BGR0
LIN-UART baud rate generator register 0
R/W
00000000B
0FBEH
to
0FC2H
—
—
—
0FC3H
AIDRL
R/W
00000000B
0FC4H
to
0FE3H
—
—
—
0FE4H
CRTH
Main CR clock trimming register (upper)
R/W 000XXXXXB
0FE5H
CRTL
Main CR clock trimming register (lower)
R/W 000XXXXXB
0FE6H
—
0FE7H
CRTDA
0FE8H
(Disabled)
(Disabled)
A/D input disable register (lower)
(Disabled)
(Disabled)
—
—
Main CR clock temperature dependent adjustment register
R/W 000XXXXXB
SYSC
System configuration register
R/W
11000011B
0FE9H
CMCR
Clock monitoring control register
R/W
00000000B
0FEAH
CMDR
Clock monitoring data register
R
00000000B
0FEBH
WDTH
Watchdog timer selection ID register (upper)
R
XXXXXXXXB
0FECH
WDTL
Watchdog timer selection ID register (lower)
R
XXXXXXXXB
0FEDH
to
0FFFH
—
—
—
(Disabled)
• R/W access symbols
R/W : Readable / Writable
R
: Read only
• Initial value symbols
0
: The initial value of this bit is “0”.
1
: The initial value of this bit is “1”.
X
: The initial value of this bit is undefined.
Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value
is returned.
42
DS702-00010-5v0-E
MB95560H/570H/580H Series
■ INTERRUPT SOURCE TABLE (MB95560H Series)
Vector table address
Priority order of
Bit name of interrupt sources
interrupt level of the same level
(occurring
setting register
simultaneously)
Interrupt
request
number
Upper
Lower
External interrupt ch. 4
IRQ00
FFFAH
FFFBH
L00 [1:0]
External interrupt ch. 5
IRQ01
FFF8H
FFF9H
L01 [1:0]
IRQ02
FFF6H
FFF7H
L02 [1:0]
IRQ03
FFF4H
FFF5H
L03 [1:0]
IRQ04
FFF2H
FFF3H
L04 [1:0]
8/16-bit composite timer ch. 0
(lower)
IRQ05
FFF0H
FFF1H
L05 [1:0]
8/16-bit composite timer ch. 0
(upper)
IRQ06
FFEEH
FFEFH
L06 [1:0]
LIN-UART (reception)
IRQ07
FFECH
FFEDH
L07 [1:0]
LIN-UART (transmission)
IRQ08
FFEAH
FFEBH
L08 [1:0]
—
IRQ09
FFE8H
FFE9H
L09 [1:0]
—
IRQ10
FFE6H
FFE7H
L10 [1:0]
—
IRQ11
FFE4H
FFE5H
L11 [1:0]
—
IRQ12
FFE2H
FFE3H
L12 [1:0]
—
IRQ13
FFE0H
FFE1H
L13 [1:0]
IRQ14
FFDEH
FFDFH
L14 [1:0]
—
IRQ15
FFDCH
FFDDH
L15 [1:0]
—
IRQ16
FFDAH
FFDBH
L16 [1:0]
—
IRQ17
FFD8H
FFD9H
L17 [1:0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1:0]
Time-base timer
IRQ19
FFD4H
FFD5H
L19 [1:0]
Watch prescaler
IRQ20
FFD2H
FFD3H
L20 [1:0]
IRQ21
FFD0H
FFD1H
L21 [1:0]
8/16-bit composite timer ch. 1
(lower)
IRQ22
FFCEH
FFCFH
L22 [1:0]
Flash memory
IRQ23
FFCCH
FFCDH
L23 [1:0]
Interrupt source
External interrupt ch. 2
External interrupt ch. 6
External interrupt ch. 3
External interrupt ch. 7
—
8/16-bit composite timer ch. 1
(upper)
—
DS702-00010-5v0-E
High
Low
43
MB95560H/570H/580H Series
■ INTERRUPT SOURCE TABLE (MB95570H Series)
Vector table address
Priority order of
Bit name of interrupt sources
interrupt level of the same level
(occurring
setting register
simultaneously)
Interrupt
request
number
Upper
Lower
IRQ00
FFFAH
FFFBH
L00 [1:0]
IRQ01
FFF8H
FFF9H
L01 [1:0]
IRQ02
FFF6H
FFF7H
L02 [1:0]
IRQ03
FFF4H
FFF5H
L03 [1:0]
IRQ04
FFF2H
FFF3H
L04 [1:0]
8/16-bit composite timer ch. 0
(lower)
IRQ05
FFF0H
FFF1H
L05 [1:0]
8/16-bit composite timer ch. 0
(upper)
IRQ06
FFEEH
FFEFH
L06 [1:0]
—
IRQ07
FFECH
FFEDH
L07 [1:0]
—
IRQ08
FFEAH
FFEBH
L08 [1:0]
—
IRQ09
FFE8H
FFE9H
L09 [1:0]
—
IRQ10
FFE6H
FFE7H
L10 [1:0]
—
IRQ11
FFE4H
FFE5H
L11 [1:0]
—
IRQ12
FFE2H
FFE3H
L12 [1:0]
—
IRQ13
FFE0H
FFE1H
L13 [1:0]
—
IRQ14
FFDEH
FFDFH
L14 [1:0]
—
IRQ15
FFDCH
FFDDH
L15 [1:0]
—
IRQ16
FFDAH
FFDBH
L16 [1:0]
—
IRQ17
FFD8H
FFD9H
L17 [1:0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1:0]
Time-base timer
IRQ19
FFD4H
FFD5H
L19 [1:0]
Watch prescaler
IRQ20
FFD2H
FFD3H
L20 [1:0]
—
IRQ21
FFD0H
FFD1H
L21 [1:0]
—
IRQ22
FFCEH
FFCFH
L22 [1:0]
IRQ23
FFCCH
FFCDH
L23 [1:0]
Interrupt source
External interrupt ch. 4
—
—
External interrupt ch. 6
—
—
—
Flash memory
44
High
Low
DS702-00010-5v0-E
MB95560H/570H/580H Series
■ INTERRUPT SOURCE TABLE (MB95580H Series)
Vector table address
Priority order of
Bit name of interrupt sources
interrupt level of the same level
(occurring
setting register
simultaneously)
Interrupt
request
number
Upper
Lower
External interrupt ch. 4
IRQ00
FFFAH
FFFBH
L00 [1:0]
External interrupt ch. 5
IRQ01
FFF8H
FFF9H
L01 [1:0]
IRQ02
FFF6H
FFF7H
L02 [1:0]
IRQ03
FFF4H
FFF5H
L03 [1:0]
IRQ04
FFF2H
FFF3H
L04 [1:0]
8/16-bit composite timer ch. 0
(lower)
IRQ05
FFF0H
FFF1H
L05 [1:0]
8/16-bit composite timer ch. 0
(upper)
IRQ06
FFEEH
FFEFH
L06 [1:0]
LIN-UART (reception)
IRQ07
FFECH
FFEDH
L07 [1:0]
LIN-UART (transmission)
IRQ08
FFEAH
FFEBH
L08 [1:0]
—
IRQ09
FFE8H
FFE9H
L09 [1:0]
—
IRQ10
FFE6H
FFE7H
L10 [1:0]
—
IRQ11
FFE4H
FFE5H
L11 [1:0]
—
IRQ12
FFE2H
FFE3H
L12 [1:0]
—
IRQ13
FFE0H
FFE1H
L13 [1:0]
—
IRQ14
FFDEH
FFDFH
L14 [1:0]
—
IRQ15
FFDCH
FFDDH
L15 [1:0]
—
IRQ16
FFDAH
FFDBH
L16 [1:0]
—
IRQ17
FFD8H
FFD9H
L17 [1:0]
8/10-bit A/D converter
IRQ18
FFD6H
FFD7H
L18 [1:0]
Time-base timer
IRQ19
FFD4H
FFD5H
L19 [1:0]
Watch prescaler
IRQ20
FFD2H
FFD3H
L20 [1:0]
—
IRQ21
FFD0H
FFD1H
L21 [1:0]
—
IRQ22
FFCEH
FFCFH
L22 [1:0]
IRQ23
FFCCH
FFCDH
L23 [1:0]
Interrupt source
External interrupt ch. 2
External interrupt ch. 6
External interrupt ch. 3
External interrupt ch. 7
—
Flash memory
DS702-00010-5v0-E
High
Low
45
MB95560H/570H/580H Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Power supply voltage*1
Input voltage*
1
Output voltage*
1
Maximum clamp current
Total maximum clamp
current
“L” level maximum
output current
Rating
VCC
VSS − 0.3
VSS + 6
V
VI
VSS − 0.3
VSS + 6
V
*2
VO
VSS − 0.3
VSS + 6
V
*2
ICLAMP
−2
+2
mA
Applicable to specific pins*3
Σ|ICLAMP|
—
20
mA
Applicable to specific pins*3
IOL
—
15
mA
“L” level average current
4
—
IOLAV2
“L” level total average
output current
“H” level maximum
output current
mA
ΣIOL
—
100
mA
ΣIOLAV
—
50
mA
IOH
—
−15
mA
“H” level average
current
−4
—
mA
ΣIOH
—
−100
mA
ΣIOHAV
—
−50
mA
Power consumption
Pd
—
320
mW
Operating temperature
TA
−40
+85
°C
Storage temperature
Tstg
−55
+150
°C
“H” level total average
output current
Total average output current=
operating current × operating ratio
(Total number of pins)
Other than P00 to P03, P05 to P07, P62 to
P64*4
Average output current=
operating current × operating ratio (1 pin)
P00 to P03, P05 to P07, P62 to P64*4
Average output current=
operating current × operating ratio (1 pin)
−8
IOHAV2
Other than P00 to P03, P05 to P07, P62 to
P64*4
Average output current=
operating current × operating ratio (1 pin)
P00 to P03, P05 to P07, P62 to P64*4
Average output current=
operating current × operating ratio (1 pin)
12
IOHAV1
“H” level total maximum
output current
Remarks
Max
IOLAV1
“L” level total maximum
output current
Unit
Min
Total average output current=
operating current × operating ratio
(Total number of pins)
(Continued)
46
DS702-00010-5v0-E
MB95560H/570H/580H Series
(Continued)
*1: These parameters are based on the condition that VSS is 0.0 V.
*2: VI and VO must not exceed VCC + 0.3 V. VI must not exceed the rated voltage. However, if the maximum
current to/from an input is limited by means of an external component, the ICLAMP rating is used instead of
the VI rating.
*3: Applicable to the following pins: P00 to P07, P62 to P64, PF0, PF1, PG1, PG2 (P00, and P62 to P64 are
only available on MB95F562H/F562K/F563H/F563K/F564H/F564K. P01, P02, P03, P07, PF0. PF1, PG1,
and PG2 are only available on MB95F562H/F562K/F563H/F563K/F564H/F564K/F582H/F582K/F583H/
F583K/F584H/F584K.)
• Use under recommended operating conditions.
• Use with DC voltage (current).
• The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor
between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal.
• The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller
pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the
current is transient current or stationary current.
• When the microcontroller drive current is low, such as in low power consumption modes, the HV (High
Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin,
affecting other devices.
• If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since
power is supplied from the pins, incomplete operations may be executed.
• If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage
of power supply may not be sufficient to enable a power-on reset.
• Do not leave the HV (High Voltage) input pin unconnected.
• Example of a recommended circuit:
• Input/Output equivalent circuit
Protective diode
VCC
P-ch
Limiting
resistor
HV(High Voltage) input (0 V to 16 V)
N-ch
R
*4: P62 and P63 are only available on MB95F562H/F562K/F563H/F563K/F564H/F564K.
WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without
limitation, voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
DS702-00010-5v0-E
47
MB95560H/570H/580H Series
2. Recommended Operating Conditions
(VSS = 0.0 V)
Parameter
Symbol
Power supply
voltage
VCC
Decoupling
capacitor
CS
Operating
temperature
TA
Value
Min
Max
2.4*1, *2
5.5*1
2.3
5.5
2.9
5.5
2.3
5.5
0.022
1
−40
+85
+5
+35
Unit
Remarks
In normal operation
V
Other than on-chip debug
Hold condition in stop mode mode
In normal operation
Hold condition in stop mode
On-chip debug mode
µF *3
°C
Other than on-chip debug mode
On-chip debug mode
*1: The value varies depending on the operating frequency, the machine clock and the analog guaranteed range.
*2: The minimum power supply voltage becomes 2.88 V when a product with the low-voltage detection reset is
used.
*3: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The decoupling capacitor
for the VCC pin must have a capacitance equal to or larger than the capacitance of CS. For the connection to
a decoupling capacitor CS, see the diagram below. To prevent the device from unintentionally entering an
unknown mode due to noise, minimize the distance between the C pin and CS and the distance between CS
and the VSS pin when designing the layout of a printed circuit board.
• DBG / RST / C pins connection diagram
*
DBG
C
RST
Cs
*: Connect the DBG pin to an external pull-up resistor of 2 kΩ or above. After power-on, ensure that the
DBG pin does not stay at “L” level until the reset output is released. The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends on the tool used and the interconnection length, refer to the tool document when selecting a pull-up resistor.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of
device and could result in device failure.
No warranty is made with respect to any use, operating conditions or combinations not represented
on this data sheet. If you are considering application under any conditions other than listed herein,
please contact sales representatives beforehand.
48
DS702-00010-5v0-E
MB95560H/570H/580H Series
3. DC Characteristics
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter Symbol
Pin name
“H” level
output
voltage
“L” level
output
voltage
Input leak
current (Hi-Z
output leak
current)
Internal
pull-up
resistor
Input
capacitance
Remarks
Max
—
0.7 VCC
—
VCC + 0.3
V
Hysteresis input
VIHS
P00* to P03* ,
P05 to P07*4,
P12,
P62 to P64*3,
PF0*4, PF1*4,
PG1*4, PG2*4
—
0.8 VCC
—
VCC + 0.3
V
Hysteresis input
VIHM
PF2
—
0.8 VCC
—
VCC + 0.3
V
Hysteresis input
VIL
P04
—
VSS − 0.3
—
0.3 VCC
V
Hysteresis input
VILS
P00* to P03* ,
P05 to P07*4,
P12,
P62 to P64*3,
PF0*4, PF1*4,
PG1*4, PG2*4
—
VSS − 0.3
—
0.2 VCC
V
Hysteresis input
VILM
PF2
—
VSS − 0.3
—
0.2 VCC
V
Hysteresis input
VD
P12, PF2
—
VSS − 0.3
—
VSS + 5.5
V
P04
3
Open-drain
output
application
voltage
Unit
Typ
3
“L” level
input voltage
Value
Min
VIH
"H" level
input voltage
Condition
4
4
VOH1
P04, PF0*4,
PF1*4, PG1*4,
PG2
IOH = −4 mA
VCC − 0.5
—
—
V
VOH2
P00*3 to P03*4,
P05 to P07*4, IOH = −8 mA
P62 to P64*3
VCC − 0.5
—
—
V
VOL1
P04, P12,
PF0 to PF2*4,
PG1*4, PG2*4
—
—
0.4
V
VOL2
P00*3 to P03*4,
P05 to P07*4, IOL = 12 mA
P62 to P64*3
—
—
0.4
V
All input pins
−5
—
+5
When the internal
µA pull-up resistor is
disabled
P00*3 to P07*4,
P62 to P64*3, VI = 0 V
PG1*4, PG2*4
25
50
100
When the internal
kΩ pull-up resistor is
enabled
Other than VCC
f = 1 MHz
and VSS
—
5
15
pF
ILI
RPULL
CIN
IOL = 4 mA
0.0 V < VI < VCC
(Continued)
DS702-00010-5v0-E
49
MB95560H/570H/580H Series
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Condition
Value
Min
—
FCH = 32 MHz
FMP = 16 MHz
Main clock mode
(divided by 2)
ICC
3.5
Unit
Remarks
4.4
Except during
Flash memory
mA
programming and
erasing
—
7.4
9.8
During Flash
memory
mA
programming and
erasing
—
5.1
6.4
mA At A/D conversion
—
1.2
1.5
mA
—
65
71
µA
ICCLS*6
FCL = 32 kHz
FMPL = 16 kHz
Subsleep mode
(divided by 2)
TA = +25 °C
—
5.4
7
µA
In deep standby
mode
ICCT*6
FCL = 32 kHz
Watch mode
TA = +25 °C
—
4.8
6.9
µA
In deep standby
mode
ICCMCR
FCRH = 4 MHz
FMP = 4 MHz
Main CR clock mode
—
1.1
1.4
mA
ICCSCR
Sub-CR clock mode
(divided by 2)
TA = +25 °C
—
58
64
µA
ICCTS
FCH = 32 MHz
Time-base timer
mode
TA = +25 °C
—
290
340
µA
In deep standby
mode
—
4.1
6.5
µA
In deep standby
mode
FCH = 32 MHz
FMP = 16 MHz
Main sleep mode
(divided by 2)
ICCS
ICCL
Power supply
current*5
Typ*1 Max*2
VCC
(External clock
FCL = 32 kHz
operation)
FMPL = 16 kHz
Subclock mode
(divided by 2)
TA = +25 °C
VCC
ICCH
VCC
Main stop mode
(External clock (single external
operation)
clock product)/
Substop mode (dual
external clock
product)
TA = +25 °C
(Continued)
50
DS702-00010-5v0-E
MB95560H/570H/580H Series
(Continued)
Parameter
Power supply
current*5
Symbol
Pin name
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Condition
Unit
Remarks
Min Typ*1 Max*2
ILVD
Current
consumption for the
low-voltage
detection circuit
—
3.6
6.6
µA
ICRH
Current
consumption for the
main CR oscillator
—
220
280
µA
ICRL
Current
consumption for the
sub-CR oscillator
oscillating at
100 kHz
—
5.1
9.3
µA
Current
consumption
difference between
normal standby
mode and deep
standby mode
TA = +25 °C
—
20
30
µA
VCC
INSTBY
*1: VCC = 5.0 V, TA = + 25 °C
*2: VCC = 5.5 V, TA = + 85 °C (unless otherwise specified)
*3: P00, P62, P63 and P64 are only available on MB95F562H/F562K/F563H/F563K/F564H/F564K.
*4: P01, P02, P03, P07, PF0, PF1, PG1 and PG2 are only available on MB95F562H/F562K/F563H/F563K/
F564H/F564K/F582H/F582K/F583H/F583K/F584H/F584K.
*5: • The power supply current is determined by the external clock. When the low-voltage detection option is
selected, the power-supply current will be the sum of adding the current consumption of the low-voltage
detection circuit (ILVD) to one of the value from ICC to ICCH. In addition, when both the low-voltage detection
option and the CR oscillator are selected, the power supply current will be the sum of adding up the current
consumption of the low-voltage detection circuit, the current consumption of the CR oscillators (ICRH, ICRL)
and a specified value. In on-chip debug mode, the CR oscillator (ICRH) and the low-voltage detection circuit
are always enabled, and current consumption therefore increases accordingly.
• See “4. AC Characteristics: (1) Clock Timing” for FCH and FCL.
• See “4. AC Characteristics: (2) Source Clock / Machine Clock” for FMP and FMPL.
*6: In sub-CR clock mode, the power supply current value is the sum of adding ICRL to ICCLS or ICCT. In addition,
when the sub-CR clock mode is selected with FMPL being 50 kHz, the current consumption increases accordingly.
DS702-00010-5v0-E
51
MB95560H/570H/580H Series
4. AC Characteristics
(1) Clock Timing
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol Pin name Condition
X0, X1
FCH
X0
X0, X1
—
X1: open
*
Min
Value
Typ
1
—
16.25 MHz
1
1
—
—
12
32.5
3.92
FCRH
—
—
3.8
7.84
7.6
9.8
Clock
frequency
9.5
FMCRPLL
—
—
11.76
11.4
15.68
15.2
—
FCL
X0A, X1A
—
—
FCRL
—
—
50
Max
Unit
Remarks
When the main oscillation
circuit is used
MHz When the main external clock
MHz is used
Operating conditions
4
4.08 MHz • The main CR clock is used.
• 0 °C ≤ TA ≤ +70 °C
Operating conditions
• The main CR clock is used.
4
4.2 MHz
• −40 °C ≤ TA < 0 °C,
+70 °C < TA ≤ +85 °C
Operating conditions
8
8.16 MHz • PLL multiplication rate: 2
• 0 °C ≤ TA ≤ +70 °C
Operating conditions
• PLL multiplication rate: 2
8
8.4 MHz
• −40 °C ≤ TA < 0 °C,
+70 °C < TA ≤ +85 °C
Operating conditions
10
10.2 MHz • PLL multiplication rate: 2.5
• 0 °C ≤ TA ≤ +70 °C
Operating conditions
• PLL multiplication rate: 2.5
10
10.5 MHz
• −40 °C ≤ TA < 0 °C,
+70 °C < TA ≤ +85 °C
Operating conditions
12
12.24 MHz • PLL multiplication rate: 3
• 0 °C ≤ TA ≤ +70 °C
Operating conditions
• PLL multiplication rate: 3
12
12.6 MHz
• −40 °C ≤ TA < 0 °C,
+70 °C < TA ≤ +85 °C
Operating conditions
16
16.32 MHz • PLL multiplication rate: 4
• 0 °C ≤ TA ≤ +70 °C
Operating conditions
• PLL multiplication rate: 4
16
16.8 MHz
• −40 °C ≤ TA < 0 °C,
+70 °C < TA ≤ +85 °C
When the suboscillation circuit
32.768 —
kHz
is used
When the sub-external clock is
32.768 —
kHz
used
When the sub-CR clock is
100
150 kHz
used
(Continued)
52
DS702-00010-5v0-E
MB95560H/570H/580H Series
(Continued)
Parameter
(VCC = 2.4 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Symbol Pin name Condition
X0, X1
Clock cycle
time
tHCYL
tLCYL
Input clock
pulse width
Input clock
rising time and
falling time
CR oscillation
start time
tWH1,
tWL1
—
X0
X1: open
X0, X1
*
X0A, X1A
—
X0
X1: open
X0, X1
*
tWH2,
tWL2
X0A
tCR,
tCF
X0, X0A X1: open
X0, X1,
*
X0A, X1A
—
Min
Value
Typ
Max
61.5
—
1000
ns
83.4
30.8
—
33.4
12.4
—
—
30.5
—
—
1000
1000
—
—
—
ns
ns
µs
ns
ns
—
15.2
—
When an external clock is
used, the duty ratio should
µs range between 40% and 60%.
—
—
5
ns
—
—
5
When an external clock is
ns used
µs
tCRHWK
—
—
—
—
50
tCRLWK
—
—
—
—
30
Unit
Remarks
When the main oscillation
circuit is used
When an external clock is
used
When the subclock is used
When the main CR clock is
used
When the sub-CR clock is
µs
used
*: The external clock signal is input to X0 and the inverted external clock signal to X1.
DS702-00010-5v0-E
53
MB95560H/570H/580H Series
• Input waveform generated when an external clock (main clock) is used
tHCYL
tWH1
tWL1
tCR
tCF
0.8 VCC 0.8 VCC
X0, X1
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of main clock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0
When an external clock is used When an external clock
(X1 is open)
is used
X0
X1
X1
X0
X1
Open
FCH
FCH
FCH
• Input waveform generated when an external clock (subclock) is used
tLCYL
tWH2
tCR
tWL2
tCF
0.8 VCC 0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
• Figure of subclock input port external connection
When a crystal oscillator or
a ceramic oscillator is used
X0A
X1A
FCL
When an external clock
is used
X0A
X1A
Open
FCL
54
DS702-00010-5v0-E
MB95560H/570H/580H Series
(2) Source Clock / Machine Clock
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Source clock
cycle time*1
Symbol
tSCLK
Pin
name
—
FSP
Source clock
frequency
—
FSPL
Machine clock
cycle time*2
(minimum
instruction
execution
time)
tMCLK
—
FMPL
Unit
Remarks
Min
Typ
Max
61.5
—
2000
ns
When the main external clock is used
Min: FCH = 32.5 MHz, divided by 2
Max: FCH = 1 MHz, divided by 2
62.5
—
1000
ns
When the main CR clock is used
Min: FCRH = 4 MHz, multiplied by 4
Max: FCRH = 4 MHz, divided by 4
—
61
—
µs
When the suboscillation clock is used
FCL = 32.768 kHz, divided by 2
—
20
—
µs
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
0.5
—
16.25
—
4
—
MHz When the main CR clock is used
—
16.384
—
kHz When the suboscillation clock is used
—
50
—
kHz
61.5
—
32000
ns
When the main oscillation clock is used
Min: FSP = 16.25 MHz, no division
Max: FSP = 0.5 MHz, divided by 16
250
—
1000
ns
When the main CR clock is used
Min: FSP = 4 MHz, no division
Max: FSP = 4 MHz, divided by 4
61
—
976.5
µs
When the suboscillation clock is used
Min: FSPL = 16.384 kHz, no division
Max: FSPL = 16.384 kHz, divided by 16
20
—
320
µs
When the sub-CR clock is used
Min: FSPL = 50 kHz, no division
Max: FSPL = 50 kHz, divided by 16
0.031
—
16.25
0.25
—
16
1.024
—
16.384
3.125
—
50
MHz When the main oscillation clock is used
—
FMP
Machine clock
frequency
Value
When the sub-CR clock is used
FCRL = 100 kHz, divided by 2
MHz When the main oscillation clock is used
MHz When the main CR clock is used
kHz When the suboscillation clock is used
kHz
When the sub-CR clock is used
FCRL = 100 kHz
*1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio
select bits (SYCC:DIV[1:0]). This source clock is divided to become a machine clock according to the division
ratio set by the machine clock division ratio select bits (SYCC:DIV[1:0]). In addition, a source clock can be
selected from the following.
• Main clock divided by 2
• Main CR clock
• PLL multiplication of main CR clock (Select a multiplication rate from 2, 2.5, 3 and 4.)
• Subclock divided by 2
• Sub-CR clock divided by 2
*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.
• Source clock (no division)
• Source clock divided by 4
• Source clock divided by 8
• Source clock divided by 16
DS702-00010-5v0-E
55
MB95560H/570H/580H Series
• Schematic diagram of the clock generation block
FCH
(Main oscillation clock)
Divided by 2
FMCRPLL
(Main CR PLL clock)
SCLK
(Source clock)
FCRH
(Main CR clock)
FCL
(Suboscillation clock)
Division circuit
×
1
× 1/4
× 1/8
× 1/16
MCLK
(Machine clock)
Divided by 2
Machine clock divide ratio select bits
(SYCC:DIV[1:0])
FCRL
(Sub-CR clock)
Divided by 2
Clock mode select bits
(SYCC:SCS[2:0])
• Operating voltage - Operating frequency (TA = −40°C to +85°C)
Without the on-chip debug function
5.5
Operating voltage (V)
5.0
A/D converter operation range
4.0
3.5
3.0
2.7
2.4
16 kHz
3 MHz
10 MHz
16.25 MHz
Source clock frequency (FSP/FSPL)
• Operating voltage - Operating frequency (TA = −40 °C to +85 °C)
With the on-chip debug function
5.5
Operating voltage (V)
5.0
A/D converter operation range
4.0
3.5
2.9
3.0
16 kHz
3 MHz
12.5 MHz
16.25 MHz
Source clock frequency (FSP)
56
DS702-00010-5v0-E
MB95560H/570H/580H Series
(3) External Reset
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
RST “L” level
pulse width
Symbol
tRSTL
Value
Unit
Remarks
Min
Max
2 tMCLK*1
—
ns
In normal operation
Oscillation time of the
oscillator*2 + 200
—
µs
In stop mode, subclock mode,
subsleep mode, watch mode, and
power-on
200
—
µs
In time-base timer mode
*1: See “(2) Source Clock / Machine Clock” for tMCLK.
*2: The oscillation time of an oscillator is the time for it to reach 90% of its amplitude. The crystal oscillator has
an oscillation time of between several ms and tens of ms. The ceramic oscillator has an oscillation time of
between hundreds of µs and several ms. The external clock has an oscillation time of 0 ms. The CR oscillator
has an oscillation time of between several µs and several ms.
• In normal operation
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode, subclock mode, subsleep mode, watch mode and power-on
tRSTL
RST
X0
0.2 VCC
0.2 VCC
90% of
amplitude
Internal
operating
clock
Oscillation
time of
oscillator
Internal reset
DS702-00010-5v0-E
200 μs
Oscillation stabilization wait time
Execute instruction
57
MB95560H/570H/580H Series
(4) Power-on Reset
(VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Condition
Power supply rising time
tR
Power supply cutoff time
tOFF
tR
Value
Unit
Min
Max
—
—
50
ms
—
1
—
ms
Remarks
Wait time until power-on
tOFF
2.5 V
VCC
0.2 V
0.2 V
0.2 V
Note: A sudden change of power supply voltage may activate the power-on reset function. When changing the
power supply voltage during the operation, set the slope of rising to a value below within 30 mV/ms as
shown below.
VCC
2.3 V
Set the slope of rising to
a value below 30 mV/ms.
Hold condition in stop mode
VSS
58
DS702-00010-5v0-E
MB95560H/570H/580H Series
(5) Peripheral Input Timing
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Peripheral input “H” pulse width
Peripheral input “L” pulse width
Symbol
tILIH
tIHIL
Value
Pin name
INT02 to INT07*1,*2, EC0*1, EC1*3
Unit
Min
Max
2 tMCLK*4
—
ns
MCLK 4
—
ns
2t
*
*1: INT04, INT06 and EC0 are available on all products.
*2: INT02, INT03, INT05 and INT07 are only available on MB95F562H/F562K/F563H/F563K/F564H/F564K/
F582H/F582K/F583H/F583K/F584H/F584K.
*3: EC1 is only available on MB95F562H/F562K/F563H/F563K/F564H/F564K.
*4: See “(2) Source Clock / Machine Clock” for tMCLK.
tILIH
0.8 VCC
INT02 to INT07,
EC0, EC1
DS702-00010-5v0-E
tIHIL
0.8 VCC
0.2 VCC
0.2 VCC
59
MB95560H/570H/580H Series
(6) LIN-UART Timing (only available on MB95F562H/F562K/F563H/F563K/F564H/F564K/F582H/F582K/
F583H/F583K/F584H/F584K)
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register: SCES bit = 0, ECCR register: SCDE bit = 0)
(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Serial clock cycle time
SCK ↓→ SOT delay time
Symbol Pin name
tSCYC
SCK
tSLOVI
SCK, SOT Internal clock
operation output pin:
SCK, SIN CL = 80 pF + 1 TTL
SCK, SIN
Valid SIN → SCK ↑
tIVSHI
SCK ↑→ valid SIN hold time
tSHIXI
Serial clock “L” pulse width
Serial clock “H” pulse width
tSLSH
tSHSL
SCK ↓→ SOT delay time
tSLOVE
Valid SIN → SCK ↑
tIVSHE
SCK ↑→ valid SIN hold time
tSHIXE
Value
Condition
SCK
SCK
SCK, SOT External clock
SCK, SIN operation output pin:
SCK, SIN CL = 80 pF + 1 TTL
t
Max
5 tMCLK*3
—
ns
−50
+50
ns
MCLK 3
* + 80
—
ns
0
—
ns
* − tR
—
ns
* + 10
—
ns
MCLK 3
3t
MCLK 3
t
* + 60
MCLK 3
ns
30
—
ns
* + 30
—
ns
—
t
Unit
Min
MCLK 3
2t
SCK fall time
tF
SCK
—
10
ns
SCK rise time
tR
SCK
—
10
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “(2) Source Clock / Machine Clock” for tMCLK.
60
DS702-00010-5v0-E
MB95560H/570H/580H Series
• Internal shift clock mode
tSCYC
0.8 VCC
SCK
0.2 VCC
0.2 VCC
tSLOVI
0.8 VCC
SOT
0.2 VCC
tIVSHI
tSHIXI
0.7 VCC 0.7 VCC
SIN
0.3 VCC 0.3 VCC
• External shift clock mode
tSLSH
tSHSL
0.8 VCC
0.8 VCC
0.8 VCC
SCK
0.2 VCC
tF
0.2 VCC
tR
tSLOVE
0.8 VCC
SOT
0.2 VCC
tIVSHE
tSHIXE
0.7 VCC 0.7 VCC
SIN
0.3 VCC 0.3 VCC
DS702-00010-5v0-E
61
MB95560H/570H/580H Series
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register: SCES bit = 1, ECCR register: SCDE bit = 0)
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Serial clock cycle time
SCK ↑→ SOT delay time
Symbol Pin name
tSCYC
SCK
tSHOVI
SCK, SOT Internal clock
operation output pin:
SCK, SIN CL = 80 pF + 1 TTL
SCK, SIN
Valid SIN → SCK ↓
tIVSLI
SCK ↓→ valid SIN hold time
tSLIXI
Serial clock “H” pulse width
Serial clock “L” pulse width
tSHSL
tSLSH
SCK ↑→ SOT delay time
tSHOVE
Valid SIN → SCK ↓
tIVSLE
SCK ↓→ valid SIN hold time
tSLIXE
Value
Condition
SCK
SCK
SCK, SOT External clock
SCK, SIN operation output pin:
SCK, SIN CL = 80 pF + 1 TTL
t
Max
5 tMCLK*3
—
ns
−50
+50
ns
MCLK 3
* + 80
—
ns
0
—
ns
* − tR
—
ns
* + 10
—
ns
MCLK 3
3t
MCLK 3
t
* + 60
MCLK 3
ns
30
—
ns
* + 30
—
ns
—
t
Unit
Min
MCLK 3
2t
SCK fall time
tF
SCK
—
10
ns
SCK rise time
tR
SCK
—
10
ns
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “(2) Source Clock / Machine Clock” for tMCLK.
62
DS702-00010-5v0-E
MB95560H/570H/580H Series
• Internal shift clock mode
tSCYC
0.8 VCC
0.8 VCC
SCK
0.2 VCC
tSHOVI
0.8 VCC
SOT
0.2 VCC
tIVSLI
tSLIXI
0.7 VCC 0.7 VCC
SIN
0.3 VCC 0.3 VCC
• External shift clock mode
tSHSL
0.8 VCC
tSLSH
0.8 VCC
SCK
0.2 VCC
tR
tF
0.2 VCC
0.2 VCC
tSHOVE
0.8 VCC
SOT
0.2 VCC
tIVSLE
tSLIXE
0.7 VCC 0.7 VCC
SIN
0.3 VCC 0.3 VCC
DS702-00010-5v0-E
63
MB95560H/570H/580H Series
Sampling is executed at the rising edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register: SCES bit = 0, ECCR register: SCDE bit = 1)
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol Pin name
Value
Condition
Serial clock cycle time
tSCYC
SCK
SCK ↑→ SOT delay time
tSHOVI
SCK, SOT Internal clock
SCK, SIN operation output pin:
SCK, SIN CL = 80 pF + 1 TTL
Valid SIN → SCK ↓
tIVSLI
SCK ↓→ valid SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
SCK, SOT
t
Unit
Min
Max
5 tMCLK*3
—
ns
−50
+50
ns
MCLK 3
* + 80
—
ns
0
—
ns
* − 70
—
ns
3t
MCLK 3
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock.
*3: See “(2) Source Clock / Machine Clock” for tMCLK.
tSCYC
0.8 VCC
SCK
0.2 VCC
SOT
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tIVSLI
SIN
64
0.2 VCC
tSHOVI
tSOVLI
tSLIXI
0.7 VCC
0.7 VCC
0.3 VCC
0.3 VCC
DS702-00010-5v0-E
MB95560H/570H/580H Series
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is enabled*2.
(ESCR register: SCES bit = 1, ECCR register: SCDE bit = 1)
(VCC = 5.0 V ± 10%, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol Pin name
Value
Condition
Serial clock cycle time
tSCYC
SCK
SCK ↓→ SOT delay time
tSLOVI
SCK, SOT Internal clock
SCK, SIN operating output pin:
SCK, SIN CL = 80 pF + 1 TTL
Valid SIN → SCK ↑
tIVSHI
SCK ↑→ valid SIN hold time
tSHIXI
SOT → SCK ↑ delay time
tSOVHI
t
SCK, SOT
Unit
Min
Max
5 tMCLK*3
—
ns
−50
+50
ns
MCLK 3
* + 80
—
ns
0
—
ns
* − 70
—
ns
3t
MCLK 3
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function that delays the output signal of the serial clock for half clock.
*3: See “(2) Source Clock / Machine Clock” for tMCLK.
tSCYC
0.8 VCC
SCK
0.8 VCC
0.2 VCC
tSOVHI
SOT
0.8 VCC
0.2 VCC
0.2 VCC
tIVSHI
SIN
DS702-00010-5v0-E
tSLOVI
0.8 VCC
tSHIXI
0.7 VCC
0.7 VCC
0.3 VCC
0.3 VCC
65
MB95560H/570H/580H Series
(7) Low-voltage Detection
(VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Release voltage*
Detection voltage*
Symbol
VDL+
VDL−
Value
Min
Typ
Max
2.52
2.7
2.88
2.61
2.8
2.99
2.89
3.1
3.31
3.08
3.3
3.52
2.43
2.6
2.77
2.52
2.7
2.88
2.80
3
3.20
2.99
3.2
3.41
Unit
Remarks
V
At power supply rise
V
At power supply fall
Hysteresis width
VHYS
—
100
—
mV
Power supply start voltage
Voff
—
—
2.3
V
Power supply end voltage
Von
4.9
—
—
V
Power supply voltage
change time
(at power supply rise)
tr
650
—
—
µs
Slope of power supply that the reset
release signal generates within the
rating (VDL+)
Power supply voltage
change time
(at power supply fall)
tf
650
—
—
µs
Slope of power supply that the reset
detection signal generates within the
rating (VDL-)
Reset release delay time
td1
—
—
30
µs
Reset detection delay time
td2
—
—
30
µs
LVD threshold voltage
transition stabilization time
tstb
10
—
—
µs
*: The release voltage and the detection voltage can be selected by using the LVD reset voltage selection ID
register (LVDR) in the low-voltage detection reset circuit. For details of the LVDR register, refer to
“CHAPTER 18 LOW-VOLTAGE DETECTION RESET CIRCUIT” in “New 8FX MB95560H/570H/580H Series
Hardware Manual”.
66
DS702-00010-5v0-E
MB95560H/570H/580H Series
VCC
Von
Voff
time
tf
tr
VDL+
VHYS
VDL-
Internal reset signal
time
td2
DS702-00010-5v0-E
td1
67
MB95560H/570H/580H Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(VCC = 2.7 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Resolution
Total error
Linearity error
—
Differential linearity
error
Value
Unit
Min
Typ
Max
—
—
10
bit
−3
—
+3
LSB
−2.5
—
+2.5
LSB
−1.9
—
+1.9
LSB
Remarks
Zero transition
voltage
V0T
VSS − 1.5 LSB VSS + 0.5 LSB VSS + 2.5 LSB
V
Full-scale transition
voltage
VFST
VCC − 4.5 LSB
VCC − 2 LSB
VCC + 0.5 LSB
V
1
—
10
µs
4.5 V ≤ VCC ≤ 5.5 V
3
—
10
µs
2.7 V ≤ VCC < 4.5 V
2.7 V ≤ VCC ≤ 5.5 V,
with external
impedance < 3.3 kΩ
Compare time
—
Sampling time
—
0.6
—
∞
µs
Analog input current
IAIN
−0.3
—
+0.3
µA
Analog input voltage
VAIN
VSS
—
VCC
V
68
DS702-00010-5v0-E
MB95560H/570H/580H Series
(2) Notes on Using A/D Converter
• External impedance of analog input and its sampling time
The A/D converter of the MB95560H/570H/580H Series has a sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting A/D conversion precision. Therefore, to
satisfy the A/D conversion precision standard, considering the relationship between the external impedance
and minimum sampling time, either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 µF to the analog input pin.
• Analog input equivalent circuit
Analog input
Comparator
R
C
During sampling: ON
VCC
R
C
4.5 V ≤ VCC ≤ 5.5 V
1.45 kΩ (Max)
14.89 pF (Max)
2.7 V ≤ VCC < 4.5 V
2.7 kΩ (Max)
14.89 pF (Max)
Note: The values are reference values.
• Relationship between external impedance and minimum sampling time
[External impedance = 0 kΩ to 100 kΩ]
[External impedance = 0 kΩ to 20 kΩ]
100000
20000
External impedance [kΩ]
External impedance [kΩ]
80000
60000
40000
15000
10000
5000
20000
0
0
0
2
4
6
8
10
12
0
0.5
Minimum sampling time [μs]
1
1.5
2
2.5
Minimum sampling time [μs]
Minimum sampling time with VCC > 2.7 V
Minimum sampling time with VCC > 2.4 V
• A/D conversion error
As |VCC − VSS| decreases, the A/D conversion error increases proportionately.
DS702-00010-5v0-E
69
MB95560H/570H/580H Series
(3) Definitions of A/D Converter Terms
• Resolution
It indicates the level of analog variation that can be distinguished by the A/D converter.
When the number of bits is 10, analog voltage can be divided into 210 = 1024.
• Linearity error (unit: LSB)
It indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (“0000000000” ← → “0000000001”) of a device to the full-scale transition point (“1111111111” ←
→ “1111111110”) of the same device.
• Differential linear error (unit: LSB)
It indicates how much the input voltage required to change the output code by 1 LSB deviates from an ideal
value.
• Total error (unit: LSB)
It indicates the difference between an actual value and a theoretical value. The error can be caused by a
zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise.
Ideal I/O characteristics
Total error
VFST
3FFH
3FFH
2 LSB
3FDH
Digital output
Digital output
3FDH
004H
003H
Actual conversion
characteristic
3FEH
3FEH
V0T
{1 LSB × (N-1) + 0.5 LSB}
004H
VNT
003H
1 LSB
002H
002H
001H
Actual conversion
characteristic
Ideal characteristic
001H
0.5 LSB
VSS
Analog input
1 LSB =
VCC − VSS
(V)
1024
N
VCC
VSS
Analog input
VCC
VNT − {1 LSB × (N − 1) + 0.5 LSB}
Total error of
=
[LSB]
digital output N
1 LSB
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N − 1)H to NH
(Continued)
70
DS702-00010-5v0-E
MB95560H/570H/580H Series
(Continued)
Zero transition error
Full-scale transition error
004H
Ideal characteristic
Actual conversion
characteristic
3FFH
Actual conversion
characteristic
002H
Digital output
Digital output
003H
Actual conversion
characteristic
Ideal
characteristic
3FEH
VFST
(measurement
value)
3FDH
Actual conversion
characteristic
001H
3FCH
V0T (measurement value)
VSS
Analog input
VCC
VSS
3FEH
Ideal characteristic
Actual conversion
characteristic
(N+1)H
Actual conversion
characteristic
{1 LSB × N + V0T}
VFST
(measurement
value)
VNT
004H
Digital output
Digital output
3FDH
VNT
Ideal
characteristic
002H
V(N+1)T
NH
(N−1)H
Actual conversion
characteristic
003H
VCC
Differential linearity error
Linearity error
3FFH
Analog input
Actual conversion
characteristic
(N−2)H
001H
V0T (measurement value)
VSS
Analog input
VCC
Linearity error of digital output N =
VSS
VCC
VNT − {1 LSB × N + V0T}
1 LSB
Differential linearity error of digital output N =
N
Analog input
V(N+1)T − VNT
− 1
1 LSB
: A/D converter digital output value
VNT : Voltage at which the digital output transits from (N − 1)H to NH
V0T (ideal value) = VSS + 0.5 LSB [V]
VFST (ideal value) = VCC − 2 LSB [V]
DS702-00010-5v0-E
71
MB95560H/570H/580H Series
6. Flash Memory Program/Erase Characteristics
Value
Parameter
Unit
Remarks
Min
Typ
Max
Sector erase time
(2 Kbyte sector)
—
0.3*1
1.6*2
s
The time of writing 00H prior to
erasure is excluded.
Sector erase time
(16 Kbyte sector)
—
0.6*1
3.1*2
s
The time of writing 00H prior to
erasure is excluded.
Byte writing time
—
17
272
µs
System-level overhead is excluded.
100000
—
—
cycle
Power supply voltage at
program/erase
2.4
—
5.5
V
Flash memory data retention
time
5*3
—
—
Program/erase cycle
year Average TA = +85 °C
*1: VCC = 5.5 V, TA = +25 °C, 0 cycle
*2: VCC = 2.4 V, TA = +85 °C, 100000 cycles
*3: This value was converted from the result of a technology reliability assessment. (The value was converted
from the result of a high temperature accelerated test using the Arrhenius equation with an average temperature of +85 °C).
72
DS702-00010-5v0-E
MB95560H/570H/580H Series
■ SAMPLE CHARACTERISTICS
• Power supply current temperature characteristics
ICC − VCC
TA = +25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
ICC − TA
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Main clock mode with the external clock operating
20
20
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
15
ICC[mA]
ICC[mA]
15
FMP = 16 MHz
FMP = 10 MHz
10
5
10
5
0
0
2
3
4
5
6
−50
7
0
VCC[V]
+50
+100
+150
TA[°C]
ICCS − VCC
TA = +25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
ICCS − TA
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Main sleep mode with the external clock operating
10
10
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
8
FMP = 16 MHz
FMP = 10 MHz
8
ICCS[mA]
ICCS[mA]
6
6
4
4
2
2
0
−50
0
2
3
4
5
6
0
7
VCC[V]
ICCL − VCC
TA = +25 °C, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
+50
+100
+150
TA[°C]
ICCL − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Subclock mode with the external clock operating
100
100
80
75
ICCL[μA]
ICCL[μA]
60
50
40
25
20
0
−50
0
2
3
4
5
6
7
0
+50
+100
+150
TA[°C]
VCC[V]
(Continued)
DS702-00010-5v0-E
73
MB95560H/570H/580H Series
ICCLS − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
80
80
70
70
60
60
50
50
ICCLS[μA]
ICCLS[μA]
ICCLS − VCC
TA = +25 °C, FMPL = 16 kHz (divided by 2)
Subsleep mode with the external clock operating
40
40
30
30
20
20
10
10
0
2
3
4
5
6
0
7
−50
VCC[V]
0
+50
+100
+150
TA[°C]
ICCT − VCC
TA = +25 °C, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
ICCT − TA
VCC = 5.5 V, FMPL = 16 kHz (divided by 2)
Watch mode with the external clock operating
20
20
16
16
ICCT[μA]
ICCT[μA]
12
12
8
8
4
4
0
−50
0
2
3
4
5
6
0
7
VCC[V]
ICCTS − VCC
TA = +25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock
operating
+50
+100
+150
TA[°C]
ICCTS − TA
VCC = 5.5 V, FMP = 10, 16 MHz (divided by 2)
Time-base timer mode with the external clock
operating
1.4
1.4
FMP = 16 MHz
FMP = 10 MHz
FMP = 8 MHz
FMP = 4 MHz
FMP = 2 MHz
1.2
FMP = 16 MHz
FMP = 10 MHz
1.2
1.0
ICCTS[mA]
1.0
ICCTS[mA]
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
−50
0
+50
+100
+150
TA[°C]
0.0
2
3
4
5
6
7
VCC[V]
(Continued)
74
DS702-00010-5v0-E
MB95560H/570H/580H Series
(Continued)
ICCH − TA
VCC = 5.5 V, FMPL = (stop)
Substop mode with the external clock stopping
20
20
15
15
ICCH[μA]
ICCH[μA]
ICCH − VCC
TA = +25 °C, FMPL = (stop)
Substop mode with the external clock stopping
10
5
10
5
0
0
1
2
3
4
5
6
7
−50
VCC[V]
0
+50
+100
+150
TA[°C]
ICCMCR − TA
VCC = 5.5 V, FMP = 4 MHz (no division)
Main clock mode with the main CR clock operating
20
20
15
15
ICCMCR[mA]
ICCMCR[mA]
ICCMCR − VCC
TA = +25 °C, FMP = 4 MHz (no division)
Main clock mode with the main CR clock operating
10
5
10
5
0
0
2
3
4
5
6
−50
7
0
VCC[V]
ICCSCR − VCC
TA = +25 °C, FMPL = 50 kHz (divided by 2)
Subclock mode with the sub-CR clock operating
+100
+150
ICCSCR − TA
VCC = 5.5 V, FMPL = 50 kHz (divided by 2)
Subclock mode with the sub-CR clock operating
200
200
150
150
ICCSCR[μA]
ICCSCR[μA]
+50
TA[°C]
100
50
100
50
0
0
2
3
4
5
VCC[V]
DS702-00010-5v0-E
6
7
−50
0
+50
+100
+150
TA[°C]
75
MB95560H/570H/580H Series
• Input voltage characteristics
VIHI − VCC and VILI − VCC
TA = +25 °C
VIHS − VCC and VILS − VCC
TA = +25 °C
5
5
VIHS
VILS
VIHI
VILI
4
3
3
VIHI/VILI[V]
VIHS/VILS[V]
4
2
2
1
1
0
0
2
3
4
5
6
2
7
3
4
5
6
7
VCC[V]
VCC[V]
VIHM − VCC and VILM − VCC
TA = +25 °C
5
VIHM
VILM
VIHM/VILM[V]
4
3
2
1
0
2
3
4
5
6
7
VCC[V]
76
DS702-00010-5v0-E
MB95560H/570H/580H Series
• Output voltage characteristics
(VCC − VOH2) − IOH
TA = +25 °C
1.0
1.0
0.8
0.8
VCC − VOH2[V]
VCC − VOH1[V]
(VCC − VOH1) − IOH
TA = +25 °C
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
0
−2
−4
−6
−8
−10
0
−2
−4
IOH[mA]
−6
−8
−10
8
10
IOH[mA]
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
VOL1 − IOL
TA = +25 °C
VOL2 − IOL
TA = +25 °C
1.0
0.6
0.8
0.4
VOL1[V]
VOL2[V]
0.6
0.4
0.2
0.2
0.0
0.0
0
0
2
4
6
8
10
2
4
6
IOL[mA]
IOL[mA]
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
DS702-00010-5v0-E
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.5 V
VCC = 4.5 V
VCC = 5.0 V
VCC = 5.5 V
77
MB95560H/570H/580H Series
• Pull-up characteristics
RPULL − VCC
TA = +25 °C
250
200
RPULL[kΩ]
150
100
50
0
2
3
4
5
6
VCC[V]
78
DS702-00010-5v0-E
MB95560H/570H/580H Series
■ MASK OPTIONS
Part Number
No.
MB95F562H
MB95F563H
MB95F564H
MB95F572H
MB95F573H
MB95F574H
MB95F582H
MB95F583H
MB95F584H
Selectable/Fixed
MB95F562K
MB95F563K
MB95F564K
MB95F572K
MB95F573K
MB95F574K
MB95F582K
MB95F583K
MB95F584K
Fixed
1
Low-voltage detection reset Without low-voltage detection reset With low-voltage detection reset
2
Reset
DS702-00010-5v0-E
With dedicated reset input
Without dedicated reset input
79
MB95560H/570H/580H Series
■ ORDERING INFORMATION
Part number
MB95F562HWQN-G-SNE1
MB95F562HWQN-G-SNERE1
MB95F562KWQN-G-SNE1
MB95F562KWQN-G-SNERE1
MB95F563HWQN-G-SNE1
MB95F563HWQN-G-SNERE1
MB95F563KWQN-G-SNE1
MB95F563KWQN-G-SNERE1
MB95F564HWQN-G-SNE1
MB95F564HWQN-G-SNERE1
MB95F564KWQN-G-SNE1
MB95F564KWQN-G-SNERE1
MB95F562HPF-G-SNE2
MB95F562KPF-G-SNE2
MB95F563HPF-G-SNE2
MB95F563KPF-G-SNE2
MB95F564HPF-G-SNE2
MB95F564KPF-G-SNE2
MB95F562HPFT-G-SNE2
MB95F562KPFT-G-SNE2
MB95F563HPFT-G-SNE2
MB95F563KPFT-G-SNE2
MB95F564HPFT-G-SNE2
MB95F564KPFT-G-SNE2
MB95F582HWQN-G-SNE1
MB95F582HWQN-G-SNERE1
MB95F582KWQN-G-SNE1
MB95F582KWQN-G-SNERE1
MB95F583HWQN-G-SNE1
MB95F583HWQN-G-SNERE1
MB95F583KWQN-G-SNE1
MB95F583KWQN-G-SNERE1
MB95F584HWQN-G-SNE1
MB95F584HWQN-G-SNERE1
MB95F584KWQN-G-SNE1
MB95F584KWQN-G-SNERE1
MB95F582HPFT-G-SNE2
MB95F582KPFT-G-SNE2
MB95F583HPFT-G-SNE2
MB95F583KPFT-G-SNE2
MB95F584HPFT-G-SNE2
MB95F584KPFT-G-SNE2
MB95F582HPF-G-SNE2
MB95F582KPF-G-SNE2
MB95F583HPF-G-SNE2
MB95F583KPF-G-SNE2
MB95F584HPF-G-SNE2
MB95F584KPF-G-SNE2
Package
32-pin plastic QFN
(LCC-32P-M19)
20-pin plastic SOP
(FPT-20P-M09)
20-pin plastic TSSOP
(FPT-20P-M10)
32-pin plastic QFN
(LCC-32P-M19)
16-pin plastic TSSOP
(FPT-16P-M08)
16-pin plastic SOP
(FPT-16P-M23)
(Continued)
80
DS702-00010-5v0-E
MB95560H/570H/580H Series
(Continued)
Part number
MB95F572HPH-G-SNE2
MB95F572KPH-G-SNE2
MB95F573HPH-G-SNE2
MB95F573KPH-G-SNE2
MB95F574HPH-G-SNE2
MB95F574KPH-G-SNE2
MB95F572HPF-G-SNE2
MB95F572KPF-G-SNE2
MB95F573HPF-G-SNE2
MB95F573KPF-G-SNE2
MB95F574HPF-G-SNE2
MB95F574KPF-G-SNE2
DS702-00010-5v0-E
Package
8-pin plastic DIP
(DIP-8P-M03)
8-pin plastic SOP
(FPT-8P-M08)
81
MB95560H/570H/580H Series
■ PACKAGE DIMENSION
32-pin plastic QFN
Lead pitch
0.50 mm
Package width ×
package length
5.00 mm × 5.00 mm
Sealing method
Plastic mold
Mounting height
0.80 mm MAX
Weight
0.06 g
(LCC-32P-M19)
32-pin plastic QFN
(LCC-32P-M19)
3.50±0.10
(.138±.004)
5.00±0.10
(.197±.004)
5.00±0.10
(.197±.004)
3.50±0.10
(.138±.004)
INDEX AREA
0.25
(.010
(3-R0.20)
((3-R.008))
0.50(.020)
+0.05
–0.07
+.002
–.003
)
0.40±0.05
(.016±.002)
1PIN CORNER
(C0.30(C.012))
(TYP)
0.75±0.05
(.030±.002)
0.02
(.001
C
+0.03
–0.02
+.001
–.001
(0.20(.008))
)
2009-2010 FUJITSU SEMICONDUCTOR LIMITED C32071S-c-1-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
82
DS702-00010-5v0-E
MB95560H/570H/580H Series
20-pin plastic SOP
Lead pitch
1.27 mm
Package width ×
package length
7.50 mm × 12.70 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
2.65 mm Max
(FPT-20P-M09)
20-pin plastic SOP
(FPT-20P-M09)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
0.25
#12.70±0.10(.500±.004)
+0.07
–0.02
+.003
.010 –.001
20
11
BTM E-MARK
+0.40
#7.50±0.10 10.2 –0.20
(.295±.004) .402 +.016
–.008
INDEX
Details of "A" part
+0.13
2.52 –0.17
(Mounting height)
+.005
.099 –.007
1
"A"
10
1.27(.050)
0.40
.016
+0.09
–0.05
+.004
–.002
0.25(.010)
M
0~8°
+0.47
0.80 –0.30
+.019
.031 –.012
0.20±0.10
(.008±.004)
(Stand off)
0.10(.004)
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED F20030S-c-1-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS702-00010-5v0-E
83
MB95560H/570H/580H Series
20-pin plastic TSSOP
Lead pitch
0.65 mm
Package width ×
package length
4.40 mm × 6.50 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.20 mm MAX
Weight
0.08 g
(FPT-20P-M10)
20-pin plastic TSSOP
(FPT-20P-M10)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
+0.05
0.14 –0.04
#6.50±0.10(.256±.004)
+.002
.006 –.002
11
20
BTM E-MARK
#4.40±0.10 6.40±0.20
(.173±.004) (.252±.008)
INDEX
Details of "A" part
LEAD No.
1
1.20(.047)
(Mounting height)
MAX
10
0.65(.026)
"A"
0.24±0.04
(.009±.002)
0~8°
0.60±0.15
(.024±.006)
0.10(.004)
C
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F20031S-c-1-2
0.10±0.05
(.004±.002)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
84
DS702-00010-5v0-E
MB95560H/570H/580H Series
16-pin plastic TSSOP
Lead pitch
0.65 mm
Package width ×
package length
4.40 mm × 4.96 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.20 mm Max
Weight
0.06 g
(FPT-16P-M08)
16-pin plastic TSSOP
(FPT-16P-M08)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) * : These dimensions do not include resin protrusion.
*4.96±0.10(.195±.004)
16
0.145±0.045
(.0057±.0018)
9
*4.40±0.10 6.40±0.20
(.173±.004) (.252±.008)
INDEX
Details of "A" part
+0.10
1.10 –0.15
(Mounting height)
+0.04
.043 –0.06
LEAD No.
1
8
0.65(.026)
"A"
0.24±0.08
(.009±.003)
0.13(.005)
M
0~8°
0.60±0.15
(.024±.006)
0.10±0.05
(.004±.002)
(Stand off)
0.10(.004)
C
2007-2010 FUJITSU SEMICONDUCTOR LIMITED F16021S-c-1-5
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS702-00010-5v0-E
85
MB95560H/570H/580H Series
16-pin plastic SOP
Lead pitch
1.27 mm
Package width ×
package length
3.90 mm × 9.96 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.75 mm MAX
Weight
0.12 g
(FPT-16P-M23)
16-pin plastic SOP
(FPT-16P-M23)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) #: These dimensions do not include resin protrusion.
+0.20
#9.96±0.10(.392±.004)
0.60 –0.15
+0.08
.024 –0.06
9
16
8 ±2
8 ±2
BTM E-MARK
INDEX
(1.04 (.041))
#3.90±0.10 6.00±0.20
(.154±.004) (.236±.008)
0.40±0.10
(.016±.004)
1
0.40±0.10
(.016±.004)
8
+0.11
1.27(.050)
0.40 –0.04
(.016 +.004
–.002 )
0.25(.010)
M
0.65±0.10 (.026±.004)
1.45±0.20 (.057±.008)
7 ±2
+0.15
+0.06
1.60 –0.25 .063 –0.10
7 ±2
C
0.10(.004)
+0.10
+0.04
0.15 –0.05 .006 –0.02
2010 FUJITSU SEMICONDUCTOR LIMITED HMbF16-23Sc-1-1
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
86
DS702-00010-5v0-E
MB95560H/570H/580H Series
8-pin plastic DIP
Lead pitch
2.54 mm
Sealing method
Plastic mold
(DIP-8P-M03)
8-pin plastic DIP
(DIP-8P-M03)
9.40
.370
8
+0.40
–0.30
+.016
–.012
5
INDEX
6.35±0.25
(.250±.010)
1
4
7.62(.300)
TYP.
4.36(.172)MAX
0.50(.020)
MIN
0.25±0.05
(.010±.002)
3.00(.118)MIN
+0.35
0.46±0.08
(.018±.003)
0.89 –0.30
+.014
.035 –.012
+0.30
0.99 –0
+.012
.039 –0
C
+0.30
1.52 –0
15° MAX
+.012
.060 –0
2.54(.100)
TYP.
2006-2010 FUJITSU SEMICONDUCTOR LIMITED D08008S-c-1-4
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
DS702-00010-5v0-E
87
MB95560H/570H/580H Series
(Continued)
8-pin plastic SOP
Lead pitch
1.27 mm
Package width ×
package length
5.30 mm × 5.24 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
2.10 mm Max
(FPT-8P-M08)
8-pin plastic SOP
(FPT-8P-M08)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) # : These dimensions do not include resin protrusion.
#5.24±0.10
(.206±.004)
8
5
"A"
BTM E-MARK
#5.30±0.10
(.209±.004)
INDEX
7.80
.307
+0.45
–0.10
+.018
–.004
Details of "A" part
2.10(.083)
MAX
(Mounting height)
1
1.27(.050)
4
0.43±0.05
(.017±.002)
0.20±0.05
(.008±.002)
0~8°
+0.15
0.10 –0.05
+.006
–.002
.004
(Stand off)
C
2008-2010 FUJITSU SEMICONDUCTOR LIMITED F08016S-c-1-2
+0.10
0.75 –0.20
+.004
.030 –.008
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
88
DS702-00010-5v0-E
MB95560H/570H/580H Series
■ MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
—
—
Details
Changed the series name.
MB95560H Series → MB95560H/570H/580H Series
Added information on the MB95570H Series.
Added information on the MB95580H Series.
■ PIN CONNECTION
• DBG pin
Revised details of “• DBG pin”.
• RST pin
Revised details of “• RST pin”.
28
• C pin
Corrected the following statement.
The decoupling capacitor for the VCC pin must have a
capacitance larger than CS.
→
The decoupling capacitor for the VCC pin must have a
capacitance equal to or larger than the capacitance of CS.
39
■ I/O MAP (MB95570H Series)
Corrected the R/W attribute of the CMDR register.
R/W → R
27
Corrected the R/W attribute of the WDTH register.
R/W → R
Corrected the R/W attribute of the WDTL register.
R/W → R
42
■ I/O MAP (MB95580H Series)
Corrected the R/W attribute of the CMDR register.
R/W → R
Corrected the R/W attribute of the WDTH register.
R/W → R
Corrected the R/W attribute of the WDTL register.
R/W → R
46
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Corrected the rating of the parameter ““L” level total
maximum output current”.
48 → 100
Corrected the rating of the parameter ““H” level total
maximum output current”.
48 → −100
48
2. Recommended Operating Conditions Revised note *2.
The value is 2.88 V when the low-voltage detection reset
is used.
→
The minimum power supply voltage becomes 2.18 V
when a product with the low-voltage detection reset is
used.
Corrected the following statement in note *3.
The decoupling capacitor for the VCC pin must have a
capacitance larger than CS.
→
The decoupling capacitor for the VCC pin must have a
capacitance equal to or larger than the capacitance of CS.
Revised the remark in “• DBG/RST/C pins connection
diagram”.
(Continued)
DS702-00010-5v0-E
89
MB95560H/570H/580H Series
(Continued)
Page
49
Section
3. DC Characteristics
Details
Revised the remark of the parameter “Input leak current
(Hi-Z output leak current)”.
When pull-up resistance is disabled
→
When the internal pull-up resistor is disabled
Renamed the parameter “Pull-up resistance” to “Internal
pull-up resistor”.
Revised the remark of the parameter “Internal pull-up
resistor”.
When pull-up resistance is enabled
→
When the internal pull-up resistor is enabled
53
90
4. AC Characteristics
(1) Clock Timing
Corrected the pin names of the parameter “Input clock
rising time and falling time”.
X0 → X0, X0A
X0, X1 → X0, X1, X0A, X1A
DS702-00010-5v0-E
MB95560H/570H/580H Series
• Major changes from third edition to fourth edition
Page
Section
23 to 26 ■ HANDLING PRECAUTIONS
Details
New section
35
■ I/O MAP (MB95560H Series)
Corrected the R/W attribute of the CMDR register.
R/W → R
52
■ ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(1) Clock Timing
Corrected the operating conditions of FCRH of the
parameter “Clock frequency”.
0 °C ≤ TA < +70 °C
→
0 °C ≤ TA ≤ +70 °C
+70 °C ≤ TA < +85 °C
→
+70 °C ≤ TA ≤ +85 °C
Corrected the operating conditions of FMCRPLL of the
parameter “Clock frequency”.
0 °C ≤ TA < +70 °C
→
0 °C ≤ TA ≤ +70 °C
+70 °C ≤ TA < +85 °C
→
+70 °C < TA ≤ +85 °C
68
5. A/D Converter
(1) A/D Converter Electrical
Characteristics
Corrected the symbol of the parameter “Zero transition
voltage”.
VOT → V0T
69
5. A/D Converter
(2) Notes on Using A/D Converter
• Analog input equivalent circuit
Corrected the range of VCC.
2.7 V ≤ VCC < 5.5 V
→
2.7 V ≤ VCC < 4.5 V
Corrected the values of R.
3.3 kΩ → 1.45 kΩ
5.7 kΩ → 2.7 kΩ
70, 71
5. A/D Converter
(3) Definitions of A/D Converter Terms
DS702-00010-5v0-E
Corrected the symbol of the zero transition voltage.
VOT → V0T
91
MB95560H/570H/580H Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
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For further information please contact:
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the right to make changes to the information contained in this document without notice. Please contact your FUJITSU
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