The following document contains information on Cypress products. FUJITSU SEMICONDUCTOR DATA SHEET DS702–00019–1v0-E 8-bit Microcontrollers New 8FX MB95710M/770M Series MB95F714J/F714M/F716J/F716M/F718J/F718M MB95F774J/F774M/F776J/F776M/F778J/F778M ■ DESCRIPTION The MB95710M/770M Series is a series of general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers of this series contain a variety of peripheral resources. ■ FEATURES • F2MC-8FX CPU core Instruction set optimized for controllers • Multiplication and division instructions • 16-bit arithmetic operations • Bit test branch instructions • Bit manipulation instructions, etc. Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller. • Clock • Selectable main clock source - Main oscillation clock (up to 16.25 MHz, maximum machine clock frequency: 8.125 MHz) - External clock (up to 32.5 MHz, maximum machine clock frequency: 16.25 MHz) - Main CR clock (4 MHz ±2%) - Main CR PLL clock - The main CR PLL clock frequency becomes 8 MHz ±2% when the PLL multiplication rate is 2. - The main CR PLL clock frequency becomes 10 MHz ±2% when the PLL multiplication rate is 2.5. - The main CR PLL clock frequency becomes 12 MHz ±2% when the PLL multiplication rate is 3. - The main CR PLL clock frequency becomes 16 MHz ±2% when the PLL multiplication rate is 4. - Main PLL clock (up to 16.25 MHz, maximum machine clock frequency: 16.25 MHz) • Selectable subclock source - Suboscillation clock (32.768 kHz) - External clock (32.768 kHz) - Sub-CR clock (Typ: 100 kHz, Min: 50 kHz, Max: 150 kHz) (Continued) FUJITSU SEMICONDUCTOR provides information facilitating product development via the following website. The website contains information useful for customers. http://edevice.fujitsu.com/micom/en-support/ Copyright©2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2013.7 MB95710M/770M Series • Timer • 8/16-bit composite timer × 2 channels • 8/16-bit PPG × 2 channels • 16-bit reload timer × 1 channel • Event counter × 1 channel • Time-base timer × 1 channel • Watch counter × 1 channel • Watch prescaler × 1 channel • UART/SIO × 3 channels • Full duplex double buffer • Capable of clock asynchronous (UART) serial data transfer and clock synchronous (SIO) serial data transfer • I2C bus interface × 1 channel Built-in wake-up function • External interrupt × 8 channels • Interrupt by edge detection (rising edge, falling edge, and both edges can be selected) • Can be used to wake up the device from different low power consumption (standby) modes • 8/12-bit A/D converter × 8 channels 8-bit or 12-bit resolution can be selected. • LCD controller (LCDC) • On MB95F714J/F714M/F716J/F716M/F718J/F718M, LCD output can be selected from 40 SEG × 4 COM and 36 SEG × 8 COM. • On MB95F774J/F774M/F776J/F776M/F778J/F778M, LCD output can be selected from 32 SEG × 4 COM and 28 SEG × 8 COM. • Internal divider resistor whose resistance value can be selected from 10 kΩ or 100 kΩ through software • Interrupt in sync with the LCD module frame frequency • Blinking function • Inverted display function • Low power consumption (standby) modes There are four standby modes as follows: • Stop mode • Sleep mode • Watch mode • Time-base timer mode • I/O port • MB95F714J/F716J/F718J (number of I/O ports: 75) - General-purpose I/O ports (CMOS I/O) : 71 - General-purpose I/O ports (N-ch open drain) :4 • MB95F714M/F716M/F718M (number of I/O ports: 74) - General-purpose I/O ports (CMOS I/O) : 71 - General-purpose I/O ports (N-ch open drain) :3 • MB95F774J/F776J/F778J (number of I/O ports: 59) - General-purpose I/O ports (CMOS I/O) : 55 - General-purpose I/O ports (N-ch open drain) :4 • MB95F774M/F776M/F778M (number of I/O ports: 58) - General-purpose I/O ports (CMOS I/O) : 55 - General-purpose I/O ports (N-ch open drain) :3 • On-chip debug • 1-wire serial control • Serial writing supported (asynchronous mode) • Hardware/software watchdog timer • Built-in hardware watchdog timer • Built-in software watchdog timer • Power-on reset A power-on reset is generated when the power is switched on. (Continued) 2 DS702–00019–1v0-E MB95710M/770M Series (Continued) • Low-voltage detection (LVD) circuit (only available on MB95F714J/F716J/F718J/F774J/F776J/F778J) Built-in low-voltage detection function • Comparator × 1 channel • Clock supervisor counter Built-in clock supervisor counter • Dual operation Flash memory The program/erase operation and the read operation can be executed in different banks (upper bank/lower bank) simultaneously. • Flash memory security function Protects the content of the Flash memory. DS702–00019–1v0-E 3 MB95710M/770M Series ■ PRODUCT LINE-UP • MB95710M Series Part number MB95F714J MB95F716J MB95F718J MB95F714M MB95F716M MB95F718M Parameter Type Clock supervisor counter Flash memory product It supervises the main clock oscillation and the subclock oscillation. Flash memory capacity 20 Kbyte 36 Kbyte 60 Kbyte 20 Kbyte 36 Kbyte 60 Kbyte RAM capacity 512 bytes 1 Kbyte 2 Kbyte 512 bytes 1 Kbyte 2 Kbyte Power-on reset Yes Low-voltage detection reset Reset input • • • CPU functions • • • Generalpurpose I/O Yes No Selected through software With dedicated reset input Number of basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Interrupt processing time • I/O port • CMOS I/O • N-ch open drain : 136 : 8 bits : 1 to 3 bytes : 1, 8 and 16 bits : 61.5 ns (machine clock frequency = 16.25 MHz) : 0.6 µs (machine clock frequency = 16.25 MHz) : 75 : 71 :4 • I/O port • CMOS I/O • N-ch open drain : 74 : 71 :3 Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz) Hardware/ • Reset generation cycle software Main oscillation clock at 10 MHz: 105 ms (min) watchdog timer • The sub-CR clock can be used as the source clock of the software watchdog timer. Wild register It can be used to replace 3 bytes of data. 8/12-bit A/D converter 8 channels 8-bit or 12-bit resolution can be selected. 2 channels • The timer can be configured as an “8-bit timer × 2 channels” or a “16-bit timer × 1 channel”. 8/16-bit • It has the following functions: interval timer function, PWC function, PWM function and input composite timer capture function. • Count clock: it can be selected from internal clocks (seven types) and external clocks. • It can output square wave. External interrupt On-chip debug 8 channels • Interrupt by edge detection (The rising edge, falling edge, and both edges can be selected.) • It can be used to wake up the device from different standby modes. • 1-wire serial control • It supports serial writing (asynchronous mode). (Continued) 4 DS702–00019–1v0-E MB95710M/770M Series Part number MB95F714J MB95F716J MB95F718J MB95F714M MB95F716M MB95F718M Parameter 3 channels UART/SIO • Data transfer with UART/SIO is enabled. • It has a full duplex double buffer, variable data length (5/6/7/8 bits), an internal baud rate generator and an error detection function. • It uses the NRZ type transfer format. • LSB-first data transfer and MSB-first data transfer are available to use. • Both clock asynchronous (UART) serial data transfer and clock synchronous (SIO) serial data transfer are enabled. 1 channel I2C bus interface • Master/slave transmission and reception • It has the following functions: bus error function, arbitration function, transmission direction detection function, wake-up function, and functions of generating and detecting repeated START conditions. 2 channels 8/16-bit PPG • Each channel can be used as an “8-bit timer × 2 channels” or a “16-bit timer × 1 channel”. • The counter operating clock can be selected from eight clock sources. 1 channel 16-bit reload timer Event counter • • • • Two clock modes and two counter operating modes are available to use. It can output square wave. Count clock: it can be selected from internal clocks (seven types) and external clocks. Two counter operating modes: reload mode and one-shot mode • The event counter function is implemented by configuring the 16-bit reload timer and 8/16bit composite timer ch. 1. • When the event counter function is used, the 16-bit reload timer and 8/16-bit composite timer ch. 1 become unavailable. • COM output: 4 or 8 (max) (selectable) • SEG output: 36 or 40 (max) (selectable) - If the number of COM outputs is 4, the maximum number of SEG outputs is 40, and the maximum number of pixels that can be displayed 160 (4 × 40). - If the number of COM outputs is 8, the maximum number of SEG outputs is 36, and the maximum number of pixels that can be displayed 288 (8 × 36). LCD controller • LCD drive power supply (bias) pins: 5 (max) (LCDC) • Duty LCD mode • LCD standby mode • Blinking function • Internal divider resistor whose resistance value can be selected from 10 kΩ or 100 kΩ through software • Interrupt in sync with the LCD module frame frequency • Inverted display function • Count clock: four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s) Watch counter • The counter value can be selected from 0 to 63. (The watch counter can count for one minute when the clock source is one second and the counter value is set to 60.) Watch prescaler Eight different time intervals can be selected. Comparator 1 channel (Continued) DS702–00019–1v0-E 5 MB95710M/770M Series (Continued) Part number MB95F714J MB95F716J MB95F718J MB95F714M MB95F716M MB95F718M Parameter Flash memory • It supports automatic programming (Embedded Algorithm), and program/erase/erasesuspend/erase-resume commands. • It has a flag indicating the completion of the operation of Embedded Algorithm. • Flash security feature for protecting the content of the Flash memory Number of program/erase cycles Data retention time 1000 20 years 10000 10 years 100000 5 years There are four standby modes as follows: • Stop mode Standby mode • Sleep mode • Watch mode • Time-base timer mode Package 6 FPT-80P-M37 DS702–00019–1v0-E MB95710M/770M Series • MB95770M Series Part number MB95F774J MB95F776J MB95F778J MB95F774M MB95F776M MB95F778M Parameter Type Clock supervisor counter Flash memory product It supervises the main clock oscillation and the subclock oscillation. Flash memory capacity 20 Kbyte 36 Kbyte 60 Kbyte 20 Kbyte 36 Kbyte 60 Kbyte RAM capacity 512 bytes 1 Kbyte 2 Kbyte 512 bytes 1 Kbyte 2 Kbyte Power-on reset Yes Low-voltage detection reset Reset input • • • CPU functions • • • Generalpurpose I/O Yes No Selected through software Dedicated Number of basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Interrupt processing time • I/O port • CMOS I/O • N-ch open drain : 136 : 8 bits : 1 to 3 bytes : 1, 8 and 16 bits : 61.5 ns (machine clock frequency = 16.25 MHz) : 0.6 µs (machine clock frequency = 16.25 MHz) : 59 : 55 :4 • I/O port • CMOS I/O • N-ch open drain : 58 : 55 :3 Time-base timer Interval time: 0.256 ms to 8.3 s (external clock frequency = 4 MHz) • Reset generation cycle Hardware/ Main oscillation clock at 10 MHz: 105 ms (min) software watchdog timer • The sub-CR clock can be used as the source clock of the software watchdog timer. Wild register It can be used to replace 3 bytes of data. 8/12-bit A/D converter 8 channels 8-bit or 12-bit resolution can be selected. 2 channels • The timer can be configured as an “8-bit timer × 2 channels” or a “16-bit timer × 1 channel”. 8/16-bit • It has the following functions: interval timer function, PWC function, PWM function and input composite timer capture function. • Count clock: it can be selected from internal clocks (seven types) and external clocks. • It can output square wave. External interrupt On-chip debug 8 channels • Interrupt by edge detection (The rising edge, falling edge, and both edges can be selected.) • It can be used to wake up the device from different standby modes. • 1-wire serial control • It supports serial writing (asynchronous mode). (Continued) DS702–00019–1v0-E 7 MB95710M/770M Series Part number MB95F774J MB95F776J MB95F778J MB95F774M MB95F776M MB95F778M Parameter 3 channels UART/SIO • Data transfer with UART/SIO is enabled. • It has a full duplex double buffer, variable data length (5/6/7/8 bits), an internal baud rate generator and an error detection function. • It uses the NRZ type transfer format. • LSB-first data transfer and MSB-first data transfer are available to use. • Both clock asynchronous (UART) serial data transfer and clock synchronous (SIO) serial data transfer are enabled. 1 channel I2C bus interface • Master/slave transmission and reception • It has the following functions: bus error function, arbitration function, transmission direction detection function, wake-up function, and functions of generating and detecting repeated START conditions. 2 channels 8/16-bit PPG • Each channel can be used as an “8-bit timer × 2 channels” or a “16-bit timer × 1 channel”. • The counter operating clock can be selected from eight clock sources. 1 channel 16-bit reload timer Event counter • • • • Two clock modes and two counter operating modes are available to use. It can output square wave. Count clock: it can be selected from internal clocks (seven types) and external clocks. Two counter operating modes: reload mode and one-shot mode • The event counter function is implemented by configuring the 16-bit reload timer and 8/16bit composite timer ch. 1. • When the event counter function is used, the 16-bit reload timer and 8/16-bit composite timer ch. 1 become unavailable. • COM output: 4 or 8 (max) (selectable) • SEG output: 28 or 32 (max) (selectable) - If the number of COM outputs is 4, the maximum number of SEG outputs is 32, and the maximum number of pixels that can be displayed 128 (4 × 32). - If the number of COM outputs is 8, the maximum number of SEG outputs is 28, and the maximum number of pixels that can be displayed 224 (8 × 28). LCD controller • LCD drive power supply (bias) pins: 4 (max) (LCDC) • Duty LCD mode • LCD standby mode • Blinking function • Internal divider resistor whose resistance value can be selected from 10 kΩ or 100 kΩ through software • Interrupt in sync with the LCD module frame frequency • Inverted display function • Count clock: four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s) Watch counter • The counter value can be selected from 0 to 63. (The watch counter can count for one minute when the clock source is one second and the counter value is set to 60.) Watch prescaler Eight different time intervals can be selected. Comparator 1 channel (Continued) 8 DS702–00019–1v0-E MB95710M/770M Series (Continued) Part number MB95F774J MB95F776J MB95F778J MB95F774M MB95F776M MB95F778M Parameter Flash memory • It supports automatic programming (Embedded Algorithm), and program/erase/erasesuspend/erase-resume commands. • It has a flag indicating the completion of the operation of Embedded Algorithm. • Flash security feature for protecting the content of the Flash memory Number of program/erase cycles Data retention time 1000 20 years 10000 10 years 100000 5 years There are four standby modes as follows: • Stop mode Standby mode • Sleep mode • Watch mode • Time-base timer mode Package DS702–00019–1v0-E FPT-64P-M38 FPT-64P-M39 9 MB95710M/770M Series ■ PACKAGES AND CORRESPONDING PRODUCTS Part number MB95F714J MB95F716J MB95F718J MB95F714M MB95F716M MB95F718M Ο Ο Ο Ο Ο Ο MB95F774J MB95F776J MB95F778J MB95F774M MB95F776M MB95F778M FPT-64P-M38 Ο Ο Ο Ο Ο Ο FPT-64P-M39 Ο Ο Ο Ο Ο Ο Package FPT-80P-M37 Part number Package Ο: Available 10 DS702–00019–1v0-E MB95710M/770M Series ■ DIFFERENCES AMONG PRODUCTS AND NOTES ON PRODUCT SELECTION • Current consumption When using the on-chip debug function, take account of the current consumption of Flash memory program/erase. For details of current consumption, see “■ ELECTRICAL CHARACTERISTICS”. • Package For details of information on each package, see “■ PACKAGES AND CORRESPONDING PRODUCTS” and “■ PACKAGE DIMENSION”. • Operating voltage The operating voltage varies, depending on whether the on-chip debug function is used or not. For details of operating voltage, see “■ ELECTRICAL CHARACTERISTICS”. • On-chip debug function The on-chip debug function requires that VCC, VSS and one serial wire be connected to an evaluation tool. For details of the connection method, refer to “CHAPTER 26 EXAMPLE OF SERIAL PROGRAMMING CONNECTION” in “New 8FX MB95710M/770M Series Hardware Manual”. DS702–00019–1v0-E 11 MB95710M/770M Series P61/SEG11 P62/SEG12 P63/SEG13 P64/SEG14 P65/SEG15 P66/SEG16 P67/SEG17 P43/SEG18 P42/SEG19 P41/SEG20 P40/SEG21 PE0/SEG22 PE1/SEG23 PE2/SEG24 PE3/SEG25 PE4/SEG26 PE5/SEG27/TO11 PE6/SEG28/TO10 AVss MB95710M Series PE7/SEG29/EC1 ■ PIN ASSIGNMENT 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AVcc 1 60 P60/SEG10 P07/INT07/AN07/SEG30 2 59 PC7/SEG09 P06/INT06/AN06/SEG31 3 58 PC6/SEG08 P05/INT05/AN05/SEG32/UCK1 4 57 PC5/SEG07 P04/INT04/AN04/SEG33/UI1 5 56 PC4/SEG06 P03/INT03/AN03/SEG34/UO1 6 55 PC3/SEG05 P02/INT02/AN02/SEG35/UCK2 7 54 PC2/SEG04 P01/INT01/AN01/SEG36/UI2 8 53 PC1/SEG03 P00/INT00/AN00/UO2 9 52 PC0/SEG02 P16/PPG10 10 51 PB1/SEG01 P15/PPG11 11 50 PB0/SEG00 P14/UCK0 12 49 P17/CMP0_O P13/ADTG 13 48 PF2/RST P12/DBG 14 47 Vcc P11/UO0 15 46 PG1/X0A (TOP VIEW) LQFP80 (FPT-80P-M37) P10/UI0 16 45 PG2/X1A P53/TO0 17 44 C P52/TI0/TO00 18 43 PF0/X0 P51/EC0 19 42 PF1/X1 P50/TO01 20 41 Vss PA7/COM7 PA6/COM6 PA5/COM5 PA4/COM4 PA3/COM3 PA2/COM2 PA1/COM1 PA0/COM0 PB4/SEG39 PB3/SEG38 PB2/SEG37 P94/V0 P93/V1 P92/V2 P91/V3 P90/V4 P20/PPG00/CMP0_N P21/PPG01/CMP0_P P22/SCL P23/SDA 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 (Continued) 12 DS702–00019–1v0-E MB95710M/770M Series P61/SEG07 P62/SEG08 P63/SEG09 P64/SEG10 P65/SEG11 P66/SEG12 P67/SEG13 PE0/SEG14 PE1/SEG15 PE2/SEG16 PE3/SEG17 PE4/SEG18 PE5/SEG19/TO11 PE6/SEG20/TO10 AVss MB95770M Series PE7/SEG21/EC1 (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVcc 1 48 P60/SEG06 P07/INT07/AN07/SEG22 2 47 PC3/SEG05 P06/INT06/AN06/SEG23 3 46 PC2/SEG04 P05/INT05/AN05/SEG24/UCK1 4 45 PC1/SEG03 P04/INT04/AN04/SEG25/UI1 5 44 PC0/SEG02 P03/INT03/AN03/SEG26/UO1 6 43 PB1/SEG01 42 PB0/SEG00 41 P17/CMP0_O 40 PF2/RST P02/INT02/AN02/SEG27/UCK2 7 P01/INT01/AN01/SEG28/TO00/UI2 8 P00/INT00/AN00/SEG29/UO2 9 (TOP VIEW) LQFP64 (FPT-64P-M38) (FPT-64P-M39) P16/SEG30/PPG10 10 39 Vcc P15/SEG31/PPG11 11 38 PG1/X0A P14/UCK0/EC0/TI0 12 37 PG2/X1A P13/ADTG/TO01 13 36 C P12/DBG 14 35 PF0/X0 P11/UO0 15 34 PF1/X1 P10/UI0/TO0 16 33 Vss DS702–00019–1v0-E PA7/COM7 PA6/COM6 PA5/COM5 PA4/COM4 PA3/COM3 PA2/COM2 PA1/COM1 PA0/COM0 P93/V1 P92/V2 P91/V3 P90/V4 P20/PPG00/CMP0_N P21/PPG01/CMP0_P P22/SCL P23/SDA 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 13 MB95710M/770M Series ■ PIN FUNCTIONS (MB95710M Series) Pin no. Pin name 1 AVCC I/O circuit type*1 — P07 2 3 4 5 INT07 AN07 S 8 8/12-bit A/D converter analog input pin LCDC SEG30 output pin P06 General-purpose I/O port INT06 AN06 S External interrupt input pin 8/12-bit A/D converter analog input pin SEG31 LCDC SEG31 output pin P05 General-purpose I/O port INT05 External interrupt input pin AN05 S 8/12-bit A/D converter analog input pin SEG32 LCDC SEG32 output pin UCK1 UART/SIO ch. 1 clock I/O pin P04 General-purpose I/O port INT04 External interrupt input pin AN04 V 8/12-bit A/D converter analog input pin UI1 UART/SIO ch. 1 data input pin P03 General-purpose I/O port INT03 External interrupt input pin AN03 S 8/12-bit A/D converter analog input pin UART/SIO ch. 1 data output pin P02 General-purpose I/O port INT02 External interrupt input pin S 8/12-bit A/D converter analog input pin SEG35 LCDC SEG35 output pin UCK2 UART/SIO ch. 2 clock I/O pin P01 General-purpose I/O port INT01 External interrupt input pin AN01 V 8/12-bit A/D converter analog input pin UART/SIO ch. 2 data input pin P00 General-purpose I/O port AN00 UO2 — — — Hysteresis/ CMOS/ analog LCD — — Hysteresis/ CMOS/ analog LCD — — Hysteresis/ CMOS/ analog LCD — — CMOS/ LCD — — Hysteresis/ CMOS/ analog LCD — — Hysteresis/ CMOS/ analog LCD — — CMOS/ LCD — — Hysteresis/ CMOS/ analog LCD — — CMOS/ analog CMOS/ analog LCDC SEG36 output pin UI2 INT00 — Output OD*2 PU*3 LCDC SEG34 output pin UO1 AN02 Input LCDC SEG33 output pin SEG36 9 External interrupt input pin SEG30 SEG34 7 Power supply pin for 8/12-bit A/D converter and comparator I/O type General-purpose I/O port SEG33 6 Function W External interrupt input pin 8/12-bit A/D converter analog input pin UART/SIO ch. 2 data output pin (Continued) 14 DS702–00019–1v0-E MB95710M/770M Series Pin no. Pin name 10 11 12 13 14 15 16 17 P16 PPG10 P15 PPG11 P14 UCK0 P13 ADTG P12 DBG P11 UO0 P10 UI0 P53 TO0 I/O circuit type*1 Y Y H H D H G H P52 18 TI0 H 20 21 22 P50 TO01 P23 SDA P22 SCL PPG01 H I I T T P90 V4 — Hysteresis CMOS — — Hysteresis CMOS — Ο Hysteresis CMOS — Ο Hysteresis CMOS Ο — Hysteresis CMOS — Ο CMOS — Ο Hysteresis CMOS — Ο Hysteresis CMOS — Ο 8/16-bit composite timer ch. 0 clock input Hysteresis CMOS pin — Ο — Ο General-purpose I/O port 8/16-bit PPG ch. 1 output pin General-purpose I/O port UART/SIO ch. 0 clock I/O pin General-purpose I/O port 8/12-bit A/D converter trigger input pin General-purpose I/O port DBG input pin General-purpose I/O port UART/SIO ch. 0 data output pin General-purpose I/O port UART/SIO ch. 0 data input pin General-purpose I/O port 16-bit reload timer ch. 0 output pin CMOS 16-bit reload timer ch. 0 input pin General-purpose I/O port 8/16-bit composite timer ch. 0 output pin General-purpose I/O port I2C bus interface ch. 0 data I/O pin General-purpose I/O port I2C bus interface ch. 0 clock I/O pin Hysteresis CMOS CMOS CMOS Ο — CMOS CMOS Ο — 8/16-bit PPG ch. 0 output pin Hysteresis/ CMOS analog — Ο — Ο — — General-purpose I/O port CMP0_N 25 — Comparator ch. 0 non-inverting analog input (positive input) pin P20 PPG00 Hysteresis CMOS 8/16-bit PPG ch. 1 output pin General-purpose I/O port CMP0_P 24 Output OD*2 PU*3 General-purpose I/O port H P21 23 Input 8/16-bit composite timer ch. 0 output pin P51 EC0 General-purpose I/O port I/O type General-purpose I/O port TO00 19 Function Hysteresis/ CMOS analog Comparator ch. 0 inverting analog input (negative input) pin 8/16-bit PPG ch. 0 output pin General-purpose I/O port R LCD drive power supply pin Hysteresis/ LCD power supply CMOS/ LCD power supply (Continued) DS702–00019–1v0-E 15 MB95710M/770M Series Pin no. Pin name I/O circuit type*1 P91 26 V3 General-purpose I/O port R P92 27 V2 V1 R 30 31 32 33 34 35 36 37 38 39 40 V0 PB2 SEG37 PB3 SEG38 PB4 SEG39 PA0 COM0 PA1 COM1 PA2 COM2 PA3 COM3 PA4 COM4 PA5 COM5 PA6 COM6 PA7 COM7 LCD drive power supply pin General-purpose I/O port R P94 29 LCD drive power supply pin General-purpose I/O port P93 28 Function LCD drive power supply pin General-purpose I/O port R M M M M M M M M M M M LCD drive power supply pin General-purpose I/O port LCDC SEG37 output pin General-purpose I/O port LCDC SEG38 output pin General-purpose I/O port LCDC SEG39 output pin General-purpose I/O port LCDC COM0 output pin General-purpose I/O port LCDC COM1 output pin General-purpose I/O port LCDC COM2 output pin General-purpose I/O port LCDC COM3 output pin General-purpose I/O port LCDC COM4 output pin General-purpose I/O port LCDC COM5 output pin General-purpose I/O port LCDC COM6 output pin General-purpose I/O port LCDC COM7 output pin I/O type Input Output OD*2 PU*3 Hysteresis/ LCD power supply CMOS/ LCD power supply — — Hysteresis/ LCD power supply CMOS/ LCD power supply — — Hysteresis/ LCD power supply CMOS/ LCD power supply — — Hysteresis/ LCD power supply CMOS/ LCD power supply — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — (Continued) 16 DS702–00019–1v0-E MB95710M/770M Series Pin no. Pin name 41 42 43 44 45 46 47 VSS PF1 X1 PF0 X0 C PG2 X1A PG1 X0A VCC I/O circuit type*1 — B B — C C — PF2 48 49 50 51 52 53 54 55 56 57 58 59 60 RST P17 CMP0_O PB0 SEG00 PB1 SEG01 PC0 SEG02 PC1 SEG03 PC2 SEG04 PC3 SEG05 PC4 SEG06 PC5 SEG07 PC6 SEG08 PC7 SEG09 P60 SEG10 Function Power supply pin (GND) General-purpose I/O port Main clock I/O oscillation pin General-purpose I/O port Main clock input oscillation pin Decoupling capacitor connection pin General-purpose I/O port Subclock I/O oscillation pin General-purpose I/O port Subclock input oscillation pin Power supply pin I/O type Input — Output OD*2 PU*3 — — Hysteresis CMOS — — Hysteresis CMOS — — — — Hysteresis CMOS — Ο Hysteresis CMOS — Ο — — Hysteresis CMOS Ο — Hysteresis CMOS — Ο Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — — — — — — General-purpose I/O port A H M M M M M M M M M M M Reset pin Dedicated reset pin on MB95F714M/F716M/F718M General-purpose I/O port Comparator ch. 0 digital output pin General-purpose I/O port LCDC SEG00 output pin General-purpose I/O port LCDC SEG01 output pin General-purpose I/O port LCDC SEG02 output pin General-purpose I/O port LCDC SEG03 output pin General-purpose I/O port LCDC SEG04 output pin General-purpose I/O port LCDC SEG05 output pin General-purpose I/O port LCDC SEG06 output pin General-purpose I/O port LCDC SEG07 output pin General-purpose I/O port LCDC SEG08 output pin General-purpose I/O port LCDC SEG09 output pin General-purpose I/O port LCDC SEG10 output pin (Continued) DS702–00019–1v0-E 17 MB95710M/770M Series Pin no. Pin name 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 P61 SEG11 P62 SEG12 P63 SEG13 P64 SEG14 P65 SEG15 P66 SEG16 P67 SEG17 P43 SEG18 P42 SEG19 P41 SEG20 P40 SEG21 PE0 SEG22 PE1 SEG23 PE2 SEG24 PE3 SEG25 PE4 SEG26 I/O circuit type*1 M M M M M M M M M M M M M M M M PE5 77 SEG27 TO11 Function General-purpose I/O port LCDC SEG11 output pin General-purpose I/O port LCDC SEG12 output pin General-purpose I/O port LCDC SEG13 output pin General-purpose I/O port LCDC SEG14 output pin General-purpose I/O port LCDC SEG15 output pin General-purpose I/O port LCDC SEG16 output pin General-purpose I/O port LCDC SEG17 output pin General-purpose I/O port LCDC SEG18 output pin General-purpose I/O port LCDC SEG19 output pin General-purpose I/O port LCDC SEG20 output pin General-purpose I/O port LCDC SEG21 output pin General-purpose I/O port LCDC SEG22 output pin General-purpose I/O port LCDC SEG23 output pin General-purpose I/O port LCDC SEG24 output pin General-purpose I/O port LCDC SEG25 output pin General-purpose I/O port LCDC SEG26 output pin I/O type Input Output OD*2 PU*3 Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — General-purpose I/O port M LCDC SEG27 output pin 8/16-bit composite timer ch. 1 output pin (Continued) 18 DS702–00019–1v0-E MB95710M/770M Series (Continued) Pin no. Pin name I/O circuit type*1 PE6 78 79 SEG28 M LCDC SEG28 output pin 8/16-bit composite timer ch. 1 output pin PE7 General-purpose I/O port M Input Output OD*2 PU*3 LCDC SEG27 output pin Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — — — — — 8/16-bit composite timer ch. 1 clock input pin EC1 AVSS I/O type General-purpose I/O port TO10 SEG29 80 Function — Power supply pin (GND) for 8/12-bit A/D converter and comparator Ο: Available *1: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”. *2: N-ch open drain *3: Pull-up DS702–00019–1v0-E 19 MB95710M/770M Series ■ PIN FUNCTIONS (MB95770M Series) Pin no. Pin name 1 AVCC I/O circuit type*1 — P07 2 3 4 5 INT07 AN07 S 8 External interrupt input pin 8/12-bit A/D converter analog input pin SEG22 LCDC SEG22 output pin P06 General-purpose I/O port INT06 AN06 S External interrupt input pin 8/12-bit A/D converter analog input pin SEG23 LCDC SEG23 output pin P05 General-purpose I/O port INT05 External interrupt input pin AN05 S 8/12-bit A/D converter analog input pin SEG24 LCDC SEG24 output pin UCK1 UART/SIO ch. 1 clock I/O pin P04 General-purpose I/O port INT04 External interrupt input pin AN04 V 8/12-bit A/D converter analog input pin UI1 UART/SIO ch. 1 data input pin P03 General-purpose I/O port INT03 External interrupt input pin AN03 S 8/12-bit A/D converter analog input pin UART/SIO ch. 1 data output pin P02 General-purpose I/O port INT02 External interrupt input pin S 8/12-bit A/D converter analog input pin SEG27 LCDC SEG27 output pin UCK2 UART/SIO ch. 2 clock I/O pin P01 General-purpose I/O port INT01 External interrupt input pin AN01 SEG28 TO00 UI2 — Output OD*2 PU*3 — — — Hysteresis/ CMOS/ analog LCD — — Hysteresis/ CMOS/ analog LCD — — Hysteresis/ CMOS/ analog LCD — — CMOS/ LCD — — Hysteresis/ CMOS/ analog LCD — — Hysteresis/ CMOS/ analog LCD — — — — CMOS/ analog LCDC SEG26 output pin UO1 AN02 Input LCDC SEG25 output pin SEG26 7 Power supply pin for 8/12-bit A/D converter and comparator I/O type General-purpose I/O port SEG25 6 Function V 8/12-bit A/D converter analog input pin LCDC SEG28 output pin CMOS/ analog CMOS/ LCD 8/16-bit composite timer ch. 0 output pin UART/SIO ch. 2 data input pin (Continued) 20 DS702–00019–1v0-E MB95710M/770M Series Pin no. Pin name 9 I/O circuit type*1 P00 General-purpose I/O port INT00 External interrupt input pin AN00 S SEG29 10 UO2 UART/SIO ch. 2 data output pin P16 General-purpose I/O port SEG30 M SEG31 M 15 General-purpose I/O port DBG P11 UO0 UI0 18 P23 SDA P22 SCL H PPG01 D H G I I T 8/12-bit A/D converter trigger input pin General-purpose I/O port DBG input pin General-purpose I/O port UART/SIO ch. 0 data output pin UART/SIO ch. 0 data input pin General-purpose I/O port I2C bus interface ch. 0 data I/O pin General-purpose I/O port I2C bus interface ch. 0 clock I/O pin 8/16-bit PPG ch. 0 output pin Comparator ch. 0 non-inverting analog input (positive input) pin CMOS/ LCD — — — Ο Hysteresis CMOS — Ο Hysteresis CMOS Ο — Hysteresis CMOS — Ο CMOS CMOS — Ο CMOS CMOS Ο — CMOS CMOS Ο — Hysteresis/ CMOS analog — Ο — Ο — — General-purpose I/O port T P90 V4 Hysteresis General-purpose I/O port CMP0_N 21 — 16-bit reload timer ch. 0 output pin P20 PPG00 — General-purpose I/O port CMP0_P 20 CMOS/ LCD 8/16-bit composite timer ch. 0 output pin P21 19 Hysteresis 8/16-bit composite timer ch. 0 clock input Hysteresis CMOS pin P13 TO0 17 LCDC SEG31 output pin 16-bit reload timer ch. 0 input pin P10 16 LCDC SEG30 output pin TI0 P12 — UART/SIO ch. 0 clock I/O pin H TO01 14 — General-purpose I/O port UCK0 ADTG Hysteresis/ CMOS/ analog LCD 8/16-bit PPG ch. 1 output pin P14 13 Output OD*2 PU*3 General-purpose I/O port PPG11 EC0 Input 8/16-bit PPG ch. 1 output pin P15 12 8/12-bit A/D converter analog input pin I/O type LCDC SEG29 output pin PPG10 11 Function Hysteresis/ CMOS analog Comparator ch. 0 inverting analog input (negative input) pin 8/16-bit PPG ch. 0 output pin General-purpose I/O port R LCD drive power supply pin Hysteresis/ LCD power supply CMOS/ LCD power supply (Continued) DS702–00019–1v0-E 21 MB95710M/770M Series Pin no. Pin name I/O circuit type*1 P91 22 V3 General-purpose I/O port R P92 23 V2 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 V1 PA0 COM0 PA1 COM1 PA2 COM2 PA3 COM3 PA4 COM4 PA5 COM5 PA6 COM6 PA7 COM7 VSS PF1 X1 PF0 X0 C PG2 X1A PG1 X0A VCC R RST LCD drive power supply pin General-purpose I/O port R M M M M M M M M — B B — C C — PF2 40 LCD drive power supply pin General-purpose I/O port P93 24 Function LCD drive power supply pin General-purpose I/O port LCDC COM0 output pin General-purpose I/O port LCDC COM1 output pin General-purpose I/O port LCDC COM2 output pin General-purpose I/O port LCDC COM3 output pin General-purpose I/O port LCDC COM4 output pin General-purpose I/O port LCDC COM5 output pin General-purpose I/O port LCDC COM6 output pin General-purpose I/O port LCDC COM7 output pin Power supply pin (GND) General-purpose I/O port Main clock I/O oscillation pin General-purpose I/O port Main clock input oscillation pin Decoupling capacitor connection pin General-purpose I/O port Subclock I/O oscillation pin General-purpose I/O port Subclock input oscillation pin Power supply pin I/O type Input Output OD*2 PU*3 Hysteresis/ LCD power supply CMOS/ LCD power supply — — Hysteresis/ LCD power supply CMOS/ LCD power supply — — Hysteresis/ LCD power supply CMOS/ LCD power supply — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — — — — — Hysteresis CMOS — — Hysteresis CMOS — — — — Hysteresis CMOS — Ο Hysteresis CMOS — Ο — — Ο — — — — — General-purpose I/O port A Reset pin Dedicated reset pin on MB95F774M/F776M/F778M Hysteresis CMOS (Continued) 22 DS702–00019–1v0-E MB95710M/770M Series Pin no. Pin name 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 P17 CMP0_O PB0 SEG00 PB1 SEG01 PC0 SEG02 PC1 SEG03 PC2 SEG04 PC3 SEG05 P60 SEG06 P61 SEG07 P62 SEG08 P63 SEG09 P64 SEG10 P65 SEG11 P66 SEG12 P67 SEG13 PE0 SEG14 PE1 SEG15 PE2 SEG16 PE3 SEG17 PE4 SEG18 I/O circuit type*1 H M M M M M M M M M M M M M M M M M M M Function General-purpose I/O port Comparator ch. 0 digital output pin General-purpose I/O port LCDC SEG00 output pin General-purpose I/O port LCDC SEG01 output pin General-purpose I/O port LCDC SEG02 output pin General-purpose I/O port LCDC SEG03 output pin General-purpose I/O port LCDC SEG04 output pin General-purpose I/O port LCDC SEG05 output pin General-purpose I/O port LCDC SEG06 output pin General-purpose I/O port LCDC SEG07 output pin General-purpose I/O port LCDC SEG08 output pin General-purpose I/O port LCDC SEG09 output pin General-purpose I/O port LCDC SEG10 output pin General-purpose I/O port LCDC SEG11 output pin General-purpose I/O port LCDC SEG12 output pin General-purpose I/O port LCDC SEG13 output pin General-purpose I/O port LCDC SEG14 output pin General-purpose I/O port LCDC SEG15 output pin General-purpose I/O port LCDC SEG16 output pin General-purpose I/O port LCDC SEG17 output pin General-purpose I/O port LCDC SEG18 output pin I/O type Input Output OD*2 PU*3 Hysteresis CMOS — Ο Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — (Continued) DS702–00019–1v0-E 23 MB95710M/770M Series (Continued) Pin no. Pin name I/O circuit type*1 PE5 61 62 63 SEG19 M LCDC SEG19 output pin 8/16-bit composite timer ch. 1 output pin PE6 General-purpose I/O port M LCDC SEG20 output pin TO10 8/16-bit composite timer ch. 1 output pin PE7 General-purpose I/O port SEG21 M Input Output OD*2 PU*3 LCDC SEG21 output pin Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — Hysteresis CMOS/ LCD — — — — — — 8/16-bit composite timer ch. 1 clock input pin EC1 AVSS I/O type General-purpose I/O port TO11 SEG20 64 Function — Power supply pin (GND) for 8/12-bit A/D converter and comparator Ο: Available *1: For the I/O circuit types, see “■ I/O CIRCUIT TYPE”. *2: N-ch open drain *3: Pull-up 24 DS702–00019–1v0-E MB95710M/770M Series ■ I/O CIRCUIT TYPE Type Circuit A Remarks Reset input / Hysteresis input Reset output / Digital output • N-ch open drain output • Hysteresis input • Reset output N-ch B P-ch Port select Digital output N-ch Digital output Standby control Hysteresis input • Oscillation circuit • High-speed side Feedback resistance: approx. 1 MΩ • CMOS output • Hysteresis input Clock input X1 X0 Standby control / Port select P-ch Port select Digital output N-ch Digital output Standby control Hysteresis input C Port select R Pull-up control P-ch P-ch • Oscillation circuit • Low-speed side Feedback resistance: approx. 10 MΩ Digital output N-ch Digital output Standby control Hysteresis input • CMOS output • Hysteresis input • Pull-up control Clock input X1A X0A Standby control / Port select Port select R Pull-up control Digital output P-ch Digital output N-ch Digital output Standby control Hysteresis input (Continued) DS702–00019–1v0-E 25 MB95710M/770M Series Type Circuit D Remarks Standby control • N-ch open drain output • Hysteresis input Hysteresis input Digital output N-ch G Pull-up control R P-ch • CMOS output • CMOS input • Pull-up control Digital output P-ch Digital output N-ch Standby control CMOS input H Pull-up control R P-ch • CMOS output • Hysteresis input • Pull-up control Digital output P-ch Digital output N-ch Standby control Hysteresis input I Standby control • N-ch open drain output • CMOS input CMOS input Digital output N-ch M P-ch Digital output • CMOS output • LCD output • Hysteresis input Digital output N-ch LCD output LCD control Standby control Hysteresis input R P-ch Digital output • CMOS output • LCD power supply • Hysteresis input Digital output N-ch LCD internal divider resistor I/O LCD control Standby control Hysteresis input (Continued) 26 DS702–00019–1v0-E MB95710M/770M Series Type Circuit S Remarks P-ch Digital output Digital output N-ch • • • • CMOS output LCD output Hysteresis input Analog input • • • • CMOS output Hysteresis input Analog input Pull-up control • • • • CMOS output CMOS input LCD output Analog input Analog input LCD output LCD control A/D control Standby control Hysteresis input T Pull-up control R P-ch Digital output Digital output N-ch Analog input Analog input control Standby control Hysteresis input V P-ch Digital output Digital output N-ch Analog input LCD output LCD control A/D control Standby control CMOS input W P-ch Digital output • CMOS output • Hysteresis input • Analog input Digital output N-ch Analog input Analog input control Standby control Hysteresis input (Continued) DS702–00019–1v0-E 27 MB95710M/770M Series (Continued) Type Y Circuit Remarks P-ch Digital output • CMOS output • Hysteresis input Digital output N-ch Standby control Hysteresis input 28 DS702–00019–1v0-E MB95710M/770M Series ■ HANDLING PRECAUTIONS Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your FUJITSU SEMICONDUCTOR semiconductor devices. 1. Precautions for Product Design This section describes precautions when designing electronic equipment using semiconductor devices. • Absolute Maximum Ratings Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings. • Recommended Operating Conditions Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their sales representative beforehand. • Processing and Protection of Pins These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. (1) Preventing Over-Voltage and Over-Current Conditions Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the design stage. (2) Protection of Output Pins Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. Such conditions if present for extended periods of time can damage the device. Therefore, avoid this type of connection. (3) Handling of Unused Input Pins Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be connected through an appropriate resistance to a power supply pin or ground pin. Code: DS00-00004-2E DS702–00019–1v0-E 29 MB95710M/770M Series • Latch-up Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred mA to flow continuously at the power supply pin. This condition is called latch-up. CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the following: (1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should include attention to abnormal noise, surge levels, etc. (2) Be sure that abnormal current flows do not occur during the power-on sequence. • Observance of Safety Regulations and Standards Most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards in the design of products. • Fail-Safe Design Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. • Precautions Related to Usage of Devices FUJITSU SEMICONDUCTOR semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. 2. Precautions for Package Mounting Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance during soldering, you should only mount under FUJITSU SEMICONDUCTOR’s recommended conditions. For detailed information about mount conditions, contact your sales representative. • Lead Insertion Type Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. Direct mounting onto boards normally involves processes for inserting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. Mounting processes should conform to FUJITSU SEMICONDUCTOR recommended mounting conditions. If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment of socket contacts and IC leads be verified before mounting. 30 DS702–00019–1v0-E MB95710M/770M Series • Surface Mount Type Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. You must use appropriate mounting techniques. FUJITSU SEMICONDUCTOR recommends the solder reflow method, and has established a ranking of mounting conditions for each product. Users are advised to mount packages in accordance with FUJITSU SEMICONDUCTOR ranking of recommended conditions. • Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength may be reduced under some conditions of use. • Storage of Semiconductor Devices Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent, do the following: (1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. Store products in locations where temperature changes are slight. (2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at temperatures between 5 °C and 30 °C. When you open Dry Package that recommends humidity 40% to 70% relative humidity. (3) When necessary, FUJITSU SEMICONDUCTOR packages semiconductor devices in highly moistureresistant aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum laminate bags for storage. (4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust. • Baking Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the FUJITSU SEMICONDUCTOR recommended conditions for baking. Condition: 125 °C/24 h • Static Electricity Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus for ion generation may be needed to remove electricity. (2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 MΩ). Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4) Ground all fixtures and instruments, or protect with anti-static measures. (5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies. DS702–00019–1v0-E 31 MB95710M/770M Series 3. Precautions for Use Environment Reliability of semiconductor devices depends on ambient temperature and other conditions as described above. For reliable performance, do the following: (1) Humidity Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are anticipated, consider anti-humidity processing. (2) Discharge of Static Electricity When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use anti-static measures or processing to prevent discharges. (3) Corrosive Gases, Dust, or Oil Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. If you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) Radiation, Including Cosmic Radiation Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide shielding as appropriate. (5) Smoke, Flame CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices begin to smoke or burn, there is danger of the release of toxic gases. Customers considering the use of FUJITSU SEMICONDUCTOR products in other special environmental conditions should consult with sales representatives. Please check the latest handling precautions at the following URL. http://edevice.fujitsu.com/fj/handling-e.pdf 32 DS702–00019–1v0-E MB95710M/770M Series ■ NOTES ON DEVICE HANDLING • Preventing latch-ups When using the device, ensure that the voltage applied does not exceed the maximum voltage rating. In a CMOS IC, if a voltage higher than VCC or a voltage lower than VSS is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withstand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in “1. Absolute Maximum Ratings” of “■ ELECTRICAL CHARACTERISTICS” is applied to the VCC pin or the VSS pin, a latch-up may occur. When a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. • Stabilizing supply voltage Supply voltage must be stabilized. A malfunction may occur when power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed operating range of the VCC power supply voltage. As a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in VCC ripple (p-p value) at the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the standard VCC value, and the transient fluctuation rate does not exceed 0.1 V/ms at a momentary fluctuation such as switching the power supply. • Notes on using the external clock When an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from subclock mode or stop mode. ■ PIN CONNECTION • Treatment of unused pins If an unused input pin is left unconnected, a component may be permanently damaged due to malfunctions or latch-ups. Always pull up or pull down an unused input pin through a resistor of at least 2 kΩ. Set an unused input/output pin to the output state and leave it unconnected, or set it to the input state and treat it the same as an unused input pin. If there is an unused output pin, leave it unconnected. • Power supply pins To reduce unnecessary electro-magnetic emission, prevent malfunctions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the VCC pin and the VSS pin to the power supply and ground outside the device. In addition, connect the current supply source to the VCC pin and the VSS pin with low impedance. It is also advisable to connect a ceramic capacitor of approximately 1.0 µF as a bypass capacitor between the VCC pin and the VSS pin at a location close to this device. • DBG pin Connect the DBG pin to an external pull-up resistor of 2 kΩ or above. After power-on, ensure that the DBG pin does not stay at “L” level until the reset output is released. The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends on the tool used and the interconnection length, refer to the tool document when selecting a pull-up resistor. • RST pin Connect the RST pin to an external pull-up resistor of 2 kΩ or above. To prevent the device from unintentionally entering the reset mode due to noise, minimize the interconnection length between a pull-up resistor and the RST pin and that between a pull-up resistor and the VCC pin when designing the layout of the printed circuit board. The PF2/RST pin functions as the reset input/output pin after power-on. In addition, the reset output of the PF2/RST pin can be enabled by the RSTOE bit in the SYSC register, and the reset input function and the general-purpose I/O function can be selected by the RSTEN bit in the SYSC register. • Analog power supply Always set the same potential to the AVCC pin and the VCC pin. When VCC is larger than AVCC, the current may flow through the AN00 to AN07 pins. DS702–00019–1v0-E 33 MB95710M/770M Series • Treatment of power supply pins on the 8/12-bit A/D converter Ensure that AVCC is equal to VCC and AVSS equal to VSS even when the 8/12-bit A/D converter is not in use. Noise riding on the AVCC pin may cause accuracy degradation. Therefore, connect a ceramic capacitor of 0.1 µF (approx.) as a bypass capacitor between the AVCC pin and the AVSS pin in the vicinity of this device. • C pin Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The decoupling capacitor for the VCC pin must have a capacitance equal to or larger than the capacitance of CS. For the connection to a decoupling capacitor CS, see the diagram below. To prevent the device from unintentionally entering a mode to which the device is not set to transit due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. • DBG/RST/C pins connection diagram DBG C RST Cs • Note on serial communication In serial communication, reception of wrong data may occur due to noise or other causes. Therefore, design a printed circuit board to prevent noise from occurring. Taking account of the reception of wrong data, take measures such as adding a checksum to the end of data in order to detect errors. If an error is detected, retransmit the data. 34 DS702–00019–1v0-E MB95710M/770M Series ■ BLOCK DIAGRAM (MB95710M SERIES) F2MC-8FX CPU PF2*1/RST*2 Reset with LVD Flash with security function (60/36/20 Kbyte) PF0/X0*2 PF1/X1*2 PG1/X0A*2 Oscillator circuit RAM (2048/1024/512 bytes) CR oscillator PG2/X1A*2 Interrupt controller P52/TO00 Clock control C P50/TO01 8/16-bit composite timer ch. 0 Watch counter P12*1/DBG P51/EC0 On-chip debug P00/AN00 to P07/AN07 8/12-bit A/D converter P13/ADTG Wild register 4 COM mode: External interrupt P10/UI0 P11/UO0 UART/SIO ch. 0 P14/UCK0 Internal bus P00/INT00 to P07/INT07 LCDC (4 COM or 8 COM) P04/UI1 P03/UO1 UART/SIO ch. 1 P05/UCK1 8 COM mode: P90/V4 to P94/V0 P90/V4 to P94/V0 PA0/COM0 to PA3/COM3 PA0/COM0 to PA7/COM7 PB0/SEG00, PB1/SEG01 PB0/SEG00, PB1/SEG01 PC0/SEG02 to PC7/SEG09 PC0/SEG02 to PC7/SEG09 P60/SEG10 to P67/SEG17 P60/SEG10 to P67/SEG17 P43/SEG18 to P40/SEG21 P43/SEG18 to P40/SEG21 PE0/SEG22 to PE7/SEG29 PE0/SEG22 to PE7/SEG29 P07/SEG30 to P01/SEG36 P07/SEG30 to P02/SEG35 PB2/SEG37 to PB4/SEG39 *3 P01/UI2 P00/UO2 UART/SIO ch. 2 P02/UCK2 P20/PPG00 P21/PPG01 8/16-bit PPG ch. 0 16-bit reload timer ch. 0 P52/TI0 P53/TO0 PE6/TO10 8/16-bit composite timer ch. 1 PE5/TO11 PE7/EC1 P16/PPG10 P15/PPG11 8/16-bit PPG ch. 1 P21/CMP0_P P22*1/SCL P23*1/SDA I2C bus interface ch. 0 Port Comparator ch. 0 P20/CMP0_N P17/CMP0_O Port Vcc Vss *1: P12, P22, P23 and PF2 are N-ch open drain pins. *2: Software option *3: When the event counter operation mode is enabled, 8/16-bit composite timer ch. 1 and 16-bit reload timer ch. 0 can be used as an event counter. DS702–00019–1v0-E 35 MB95710M/770M Series ■ BLOCK DIAGRAM (MB95770M SERIES) F2MC-8FX CPU PF2*1/RST*2 Reset with LVD Flash with security function (60/36/20 Kbyte) PF0/X0*2 PF1/X1*2 PG1/X0A*2 Oscillator circuit RAM (2048/1024/512 bytes) CR oscillator PG2/X1A*2 Interrupt controller P01/TO00 Clock control C P13/TO01 8/16-bit composite timer ch. 0 Watch counter P12*1/DBG P14/EC0 On-chip debug P00/AN00 to P07/AN07 8/12-bit A/D converter P13/ADTG Wild register P10/UI0 P11/UO0 4 COM mode: External interrupt UART/SIO ch. 0 P14/UCK0 Internal bus P00/INT00 to P07/INT07 LCDC (4 COM or 8 COM) P04/UI1 P03/UO1 UART/SIO ch. 1 8 COM mode: P90/V4 to P93/V1 P90/V4 to P93/V1 PA0/COM0 to PA3/COM3 PA0/COM0 to PA7/COM7 PB0/SEG00, PB1/SEG01 PB0/SEG00, PB1/SEG01 PC0/SEG02 to PC3/SEG05 PC0/SEG02 to PC3/SEG05 P60/SEG06 to P67/SEG13 P60/SEG06 to P67/SEG13 PE0/SEG14 to PE7/SEG21 PE0/SEG14 to PE7/SEG21 P07/SEG22 to P00/SEG29 P07/SEG22 to P02/SEG27 P16/SEG30, P15/SEG31 P05/UCK1 *3 P01/UI2 P00/UO2 UART/SIO ch. 2 P02/UCK2 P20/PPG00 P21/PPG01 8/16-bit PPG ch. 0 16-bit reload timer ch. 0 P14/TI0 P10/TO0 PE6/TO10 8/16-bit composite timer ch. 1 PE5/TO11 PE7/EC1 P16/PPG10 P15/PPG11 8/16-bit PPG ch. 1 P21/CMP0_P P22*1/SCL P23*1/SDA I2C bus interface ch. 0 Port Comparator ch. 0 P20/CMP0_N P17/CMP0_O Port Vcc Vss *1: P12, P22, P23 and PF2 are N-ch open drain pins. *2: Software option *3: When the event counter operation mode is enabled, 8/16-bit composite timer ch. 1 and 16-bit reload timer ch. 0 can be used as an event counter. 36 DS702–00019–1v0-E MB95710M/770M Series ■ CPU CORE • Memory space The memory space of the MB95710M/770M Series is 64 Kbyte in size, and consists of an I/O area, an extended I/O area, a data area, and a program area. The memory space includes areas intended for specific purposes such as general-purpose registers and a vector table. The memory maps of the MB95710M/770M Series are shown below. • Memory maps MB95F714J/F714M MB95F774J/F774M 0x0000 0x0080 0x0090 0x0100 0x0200 0x0290 I/O area Access prohibited RAM 512 bytes Registers MB95F716J/F716M MB95F776J/F776M 0x0000 0x0080 0x0090 0x0100 0x0200 I/O area Access prohibited RAM 1 Kbyte Registers MB95F718J/F718M MB95F778J/F778M 0x0000 0x0080 0x0090 0x0100 0x0200 I/O area Access prohibited RAM 2 Kbyte Registers 0x0490 0x0890 Access prohibited Access prohibited Access prohibited 0x0F80 0x0F80 Extended I/O area 0x0F80 Extended I/O area 0x1000 0x1000 Flash memory 4 Kbyte Extended I/O area 0x1000 Flash memory 4 Kbyte 0x2000 0x2000 Access prohibited Access prohibited 0x8000 Flash memory 60 Kbyte Flash memory 32 Kbyte 0xC000 Flash memory 16 Kbyte 0xFFFF DS702–00019–1v0-E 0xFFFF 0xFFFF 37 MB95710M/770M Series ■ MEMORY SPACE The memory space of the MB95710M/770M Series is 64 Kbyte in size, and consists of an I/O area, an extended I/O area, a data area, and a program area. The memory space includes areas for specific applications such as general-purpose registers and a vector table. • I/O area (addresses: 0x0000 to 0x007F) • This area contains the control registers and data registers for built-in peripheral functions. • As the I/O area forms part of the memory space, it can be accessed in the same way as the memory. It can also be accessed at high-speed by using direct addressing instructions. • Extended I/O area (addresses: 0x0F80 to 0x0FFF) • This area contains the control registers and data registers for built-in peripheral functions. • As the extended I/O area forms part of the memory space, it can be accessed in the same way as the memory. • Data area • Static RAM is incorporated in the data area as the internal data area. • The internal RAM size varies according to product. • The RAM area from 0x0090 to 0x00FF can be accessed at high-speed by using direct addressing instructions. • In MB95F716J/F716M/F718J/F718M/F776J/F776M/F778J/F778M, the area from 0x0090 to 0x047F is an extended direct addressing area. It can be accessed at high-speed by direct addressing instructions with a direct bank pointer set. • In MB95F714J/F714M/F774J/F774M, the area from 0x0090 to 0x028F is an extended direct addressing area. It can be accessed at high-speed by direct addressing instructions with a direct bank pointer set. • The area from 0x0100 to 0x01FF can be used as a general-purpose register area. • Program area • The Flash memory is incorporated in the program area as the internal program area. • The Flash memory size varies according to product. • The area from 0xFFC0 to 0xFFFF is used as the vector table. • The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register. 38 DS702–00019–1v0-E MB95710M/770M Series • Memory space map 0x0000 0x0080 0x0090 0x0100 I/O area Direct addressing area Access prohibited Registers (General-purpose register area) Extended direct addressing area 0x0200 0x047F Data area 0x088F 0x0890 Access prohibited 0x0F80 0x0FFF 0x1000 Extended I/O area Program area 0xFFC0 0xFFFF DS702–00019–1v0-E Vector table area 39 MB95710M/770M Series ■ AREAS FOR SPECIFIC APPLICATIONS The general-purpose register area and vector table area are used for the specific applications. • General-purpose register area (Addresses: 0x0100 to 0x01FF) • This area contains the auxiliary registers used for 8-bit arithmetic operations, transfer, etc. • As this area forms part of the RAM area, it can also be used as conventional RAM. • When the area is used as general-purpose registers, general-purpose register addressing enables highspeed access with short instructions. • Non-volatile register data area (Addresses: 0xFFBB to 0xFFBF) The area from 0xFFBB to 0xFFBF is used to store data of the non-volatile register. For details, refer to “CHAPTER 28 NON-VOLATILE REGISTER (NVR) INTERFACE” in “New 8FX MB95710M/770M Series Hardware Manual” • Vector table area (Addresses: 0xFFC0 to 0xFFFF) • This area is used as the vector table for vector call instructions (CALLV), interrupts, and resets. • The top of the Flash memory area is allocated to the vector table area. The start address of a service routine is set to an address in the vector table in the form of data. “■ INTERRUPT SOURCE TABLE” lists the vector table addresses corresponding to vector call instructions, interrupts, and resets. For details, refer to “CHAPTER 4 RESET”, “CHAPTER 5 INTERRUPTS”, and “A.2 Special Instruction ■ Special Instruction ● CALLV #vct” in “APPENDIX” in “New 8FX MB95710M/770M Series Hardware Manual”. • Direct bank pointer and access area Direct bank pointer (DP[2:0]) Operand-specified dir Access area 0bXXX (It does not affect mapping.) 0x0000 to 0x007F 0x0000 to 0x007F 0b000 (Initial value) 0x0090 to 0x00FF 0x0090 to 0x00FF 0b001 0x0100 to 0x017F 0b010 0x0180 to 0x01FF 0b011 0x0200 to 0x027F 0b100 0x0080 to 0x00FF 0x0280 to 0x02FF* 0b101 0x0300 to 0x037F 0b110 0x0380 to 0x03FF 0b111 0x0400 to 0x047F *: Due to the memory size limit, the available access area is up to “0x028F” in MB95F714J/F714M/F774J/ F774M. 40 DS702–00019–1v0-E MB95710M/770M Series ■ I/O MAP (MB95710M SERIES) Address Register abbreviation 0x0000 PDR0 0x0001 Register name R/W Initial value Port 0 data register R/W 0b00000000 DDR0 Port 0 direction register R/W 0b00000000 0x0002 PDR1 Port 1 data register R/W 0b00000000 0x0003 DDR1 Port 1 direction register R/W 0b00000000 0x0004 — — — 0x0005 WATR Oscillation stabilization wait time setting register R/W 0b11111111 0x0006 PLLC PLL control register R/W 0b000X0000 0x0007 SYCC System clock control register R/W 0bXXX11011 0x0008 STBC Standby control register R/W 0b00000000 0x0009 RSRR Reset source register R/W 0b000XXXXX 0x000A TBTC Time-base timer control register R/W 0b00000000 0x000B WPCR Watch prescaler control register R/W 0b00000000 0x000C WDTC Watchdog timer control register R/W 0b00XX0000 0x000D SYCC2 System clock control register 2 R/W 0bXXXX0011 0x000E PDR2 Port 2 data register R/W 0b00000000 0x000F DDR2 Port 2 direction register R/W 0b00000000 0x0010, 0x0011 — — — 0x0012 PDR4 Port 4 data register R/W 0b00000000 0x0013 DDR4 Port 4 direction register R/W 0b00000000 0x0014 PDR5 Port 5 data register R/W 0b00000000 0x0015 DDR5 Port 5 direction register R/W 0b00000000 0x0016 PDR6 Port 6 data register R/W 0b00000000 0x0017 DDR6 Port 6 direction register R/W 0b00000000 0x0018 to 0x001B — — — 0x001C PDR9 Port 9 data register R/W 0b00000000 0x001D DDR9 Port 9 direction register R/W 0b00000000 0x001E PDRA Port A data register R/W 0b00000000 0x001F DDRA Port A direction register R/W 0b00000000 0x0020 PDRB Port B data register R/W 0b00000000 0x0021 DDRB Port B direction register R/W 0b00000000 0x0022 PDRC Port C data register R/W 0b00000000 0x0023 DDRC Port C direction register R/W 0b00000000 0x0024, 0x0025 — — — 0x0026 PDRE Port E data register R/W 0b00000000 0x0027 DDRE Port E direction register R/W 0b00000000 0x0028 PDRF Port F data register R/W 0b00000000 0x0029 DDRF Port F direction register R/W 0b00000000 (Disabled) (Disabled) (Disabled) (Disabled) (Continued) DS702–00019–1v0-E 41 MB95710M/770M Series Address Register abbreviation 0x002A PDRG 0x002B DDRG 0x002C — 0x002D PUL1 0x002E PUL2 0x002F, 0x0030 — 0x0031 PUL5 0x0032 to 0x0034 — 0x0035 PULG 0x0036 Register name R/W Initial value Port G data register R/W 0b00000000 Port G direction register R/W 0b00000000 — — Port 1 pull-up register R/W 0b00000000 Port 2 pull-up register R/W 0b00000000 — — R/W 0b00000000 — — Port G pull-up register R/W 0b00000000 T01CR1 8/16-bit composite timer 01 status control register 1 R/W 0b00000000 0x0037 T00CR1 8/16-bit composite timer 00 status control register 1 R/W 0b00000000 0x0038 T11CR1 8/16-bit composite timer 11 status control register 1 R/W 0b00000000 0x0039 T10CR1 8/16-bit composite timer 10 status control register 1 R/W 0b00000000 0x003A PC01 8/16-bit PPG timer 01 control register R/W 0b00000000 0x003B PC00 8/16-bit PPG timer 00 control register R/W 0b00000000 0x003C PC11 8/16-bit PPG timer 11 control register R/W 0b00000000 0x003D PC10 8/16-bit PPG timer 10 control register R/W 0b00000000 0x003E TMCSRH0 16-bit reload timer control status register (upper) ch. 0 R/W 0b00000000 0x003F TMCSRL0 16-bit reload timer control status register (lower) ch. 0 R/W 0b00000000 0x0040 to 0x0047 — — — 0x0048 EIC00 External interrupt circuit control register ch. 0/ch. 1 R/W 0b00000000 0x0049 EIC10 External interrupt circuit control register ch. 2/ch. 3 R/W 0b00000000 0x004A EIC20 External interrupt circuit control register ch. 4/ch. 5 R/W 0b00000000 0x004B EIC30 External interrupt circuit control register ch. 6/ch. 7 R/W 0b00000000 0x004C, 0x004D — — — 0x004E LVDC LVD control register R/W 0b00000100 0x004F LCDCC2 LCDC control register 2 R/W 0b00010100 0x0050 CMR0 Comparator control register ch. 0 R/W 0b00000001 0x0051 to 0x0055 — — — 0x0056 SMC10 UART/SIO serial mode control register 1 ch. 0 R/W 0b00000000 0x0057 SMC20 UART/SIO serial mode control register 2 ch. 0 R/W 0b00100000 0x0058 SSR0 UART/SIO serial status and data register ch. 0 R/W 0b00000001 0x0059 TDR0 UART/SIO serial output data register ch. 0 R/W 0b00000000 0x005A RDR0 UART/SIO serial input data register ch. 0 R 0b00000000 (Disabled) (Disabled) Port 5 pull-up register (Disabled) (Disabled) (Disabled) (Disabled) (Continued) 42 DS702–00019–1v0-E MB95710M/770M Series Address Register abbreviation 0x005B SMC11 0x005C R/W Initial value UART/SIO serial mode control register 1 ch. 1 R/W 0b00000000 SMC21 UART/SIO serial mode control register 2 ch. 1 R/W 0b00100000 0x005D SSR1 UART/SIO serial status and data register ch. 1 R/W 0b00000001 0x005E TDR1 UART/SIO serial output data register ch. 1 R/W 0b00000000 0x005F RDR1 UART/SIO serial input data register ch. 1 0x0060 0x0061 0x0062 0x0063 0x0064 IBCR00 IBCR10 IBSR0 IDDR0 IAAR0 Register name R 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 2 I C bus control register 0 ch. 0 I C bus control register 1 ch. 0 I C bus status register ch. 0 I C data register ch. 0 I C address register ch. 0 0x0065 ICCR0 I C clock control register ch. 0 R/W 0b00000000 0x0066 SMC12 UART/SIO serial mode control register 1 ch. 2 R/W 0b00000000 0x0067 SMC22 UART/SIO serial mode control register 2 ch. 2 R/W 0b00100000 0x0068 SSR2 UART/SIO serial status and data register ch. 2 R/W 0b00000001 0x0069 TDR2 UART/SIO serial output data register ch. 2 R/W 0b00000000 0x006A RDR2 UART/SIO serial input data register ch. 2 R 0b00000000 0x006B ADC3 8/12-bit A/D converter control register 3 R/W 0b01111100 0x006C ADC1 8/12-bit A/D converter control register 1 R/W 0b00000000 0x006D ADC2 8/12-bit A/D converter control register 2 R/W 0b00000000 0x006E ADDH 8/12-bit A/D converter data register (upper) R/W 0b00000000 0x006F ADDL 8/12-bit A/D converter data register (lower) R/W 0b00000000 0x0070 WCSR Watch counter control register R/W 0b00000000 0x0071 FSR2 Flash memory status register 2 R/W 0b00000000 0x0072 FSR Flash memory status register R/W 0b000X0000 0x0073 SWRE0 Flash memory sector write control register 0 R/W 0b00000000 0x0074 FSR3 Flash memory status register 3 R 0b000XXXXX 0x0075 FSR4 Flash memory status register 4 R/W 0b00000000 0x0076 WREN Wild register address compare enable register R/W 0b00000000 0x0077 WROR Wild register data test setting register R/W 0b00000000 0x0078 — — — 0x0079 ILR0 Interrupt level setting register 0 R/W 0b11111111 0x007A ILR1 Interrupt level setting register 1 R/W 0b11111111 0x007B ILR2 Interrupt level setting register 2 R/W 0b11111111 0x007C ILR3 Interrupt level setting register 3 R/W 0b11111111 0x007D ILR4 Interrupt level setting register 4 R/W 0b11111111 0x007E ILR5 Interrupt level setting register 5 R/W 0b11111111 0x007F — — — Mirror of register bank pointer (RP) and direct bank pointer (DP) (Disabled) (Continued) DS702–00019–1v0-E 43 MB95710M/770M Series Address Register abbreviation 0x0F80 WRARH0 0x0F81 R/W Initial value Wild register address setting register (upper) ch. 0 R/W 0b00000000 WRARL0 Wild register address setting register (lower) ch. 0 R/W 0b00000000 0x0F82 WRDR0 Wild register data setting register ch. 0 R/W 0b00000000 0x0F83 WRARH1 Wild register address setting register (upper) ch. 1 R/W 0b00000000 0x0F84 WRARL1 Wild register address setting register (lower) ch. 1 R/W 0b00000000 0x0F85 WRDR1 Wild register data setting register ch. 1 R/W 0b00000000 0x0F86 WRARH2 Wild register address setting register (upper) ch. 2 R/W 0b00000000 0x0F87 WRARL2 Wild register address setting register (lower) ch. 2 R/W 0b00000000 0x0F88 WRDR2 Wild register data setting register ch. 2 R/W 0b00000000 0x0F89 to 0x0F91 — — — 0x0F92 T01CR0 8/16-bit composite timer 01 status control register 0 R/W 0b00000000 0x0F93 T00CR0 8/16-bit composite timer 00 status control register 0 R/W 0b00000000 0x0F94 T01DR 8/16-bit composite timer 01 data register R/W 0b00000000 0x0F95 T00DR 8/16-bit composite timer 00 data register R/W 0b00000000 0x0F96 TMCR0 8/16-bit composite timer 00/01 timer mode control register R/W 0b00000000 0x0F97 T11CR0 8/16-bit composite timer 11 status control register 0 R/W 0b00000000 0x0F98 T10CR0 8/16-bit composite timer 10 status control register 0 R/W 0b00000000 0x0F99 T11DR 8/16-bit composite timer 11 data register R/W 0b00000000 0x0F9A T10DR 8/16-bit composite timer 10 data register R/W 0b00000000 0x0F9B TMCR1 8/16-bit composite timer 10/11 timer mode control register R/W 0b00000000 0x0F9C PPS01 8/16-bit PPG01 cycle setting buffer register R/W 0b11111111 0x0F9D PPS00 8/16-bit PPG00 cycle setting buffer register R/W 0b11111111 0x0F9E PDS01 8/16-bit PPG01 duty setting buffer register R/W 0b11111111 0x0F9F PDS00 8/16-bit PPG00 duty setting buffer register R/W 0b11111111 0x0FA0 PPS11 8/16-bit PPG11 cycle setting buffer register R/W 0b11111111 0x0FA1 PPS10 8/16-bit PPG10 cycle setting buffer register R/W 0b11111111 0x0FA2 PDS11 8/16-bit PPG11 duty setting buffer register R/W 0b11111111 0x0FA3 PDS10 8/16-bit PPG10 duty setting buffer register R/W 0b11111111 0x0FA4 PPGS 8/16-bit PPG start register R/W 0b00000000 0x0FA5 REVC 8/16-bit PPG output inversion register R/W 0b00000000 R/W 0b00000000 R/W 0b00000000 0x0FA6 0x0FA7 Register name (Disabled) TMRH0 16-bit reload timer timer register (upper) ch. 0 TMRLRH0 16-bit reload timer reload register (upper) ch. 0 TMRL0 16-bit reload timer timer register (lower) ch. 0 TMRLRL0 16-bit reload timer reload register (lower) ch. 0 0x0FA8 PSSR0 UART/SIO dedicated baud rate generator prescaler select register ch. 0 R/W 0b00000000 0x0FA9 BRSR0 UART/SIO dedicated baud rate generator baud rate setting register ch. 0 R/W 0b00000000 (Continued) 44 DS702–00019–1v0-E MB95710M/770M Series Address Register abbreviation 0x0FAA PSSR1 0x0FAB Register name R/W Initial value UART/SIO dedicated baud rate generator prescaler select register ch. 1 R/W 0b00000000 BRSR1 UART/SIO dedicated baud rate generator baud rate setting register ch. 1 R/W 0b00000000 0x0FAC PSSR2 UART/SIO dedicated baud rate generator prescaler select register ch. 2 R/W 0b00000000 0x0FAD BRSR2 UART/SIO dedicated baud rate generator baud rate setting register ch. 2 R/W 0b00000000 0x0FAE — — — 0x0FAF AIDRL A/D input disable register (lower) R/W 0b00000000 0x0FB0 LCDCC1 LCDC control register 1 R/W 0b00000000 0x0FB1 — — — 0x0FB2 LCDCE1 LCDC enable register 1 R/W 0b00111110 0x0FB3 LCDCE2 LCDC enable register 2 R/W 0b00000000 0x0FB4 LCDCE3 LCDC enable register 3 R/W 0b00000000 0x0FB5 LCDCE4 LCDC enable register 4 R/W 0b00000000 0x0FB6 LCDCE5 LCDC enable register 5 R/W 0b00000000 0x0FB7 LCDCE6 LCDC enable register 6 R/W 0b00000000 0x0FB8 LCDCE7 LCDC enable register 7 R/W 0b00000000 0x0FB9 LCDCB1 LCDC blinking setting register 1 R/W 0b00000000 0x0FBA LCDCB2 LCDC blinking setting register 2 R/W 0b00000000 0x0FBB, 0x0FBC — — — 0x0FBD to 0x0FE0 LCDRAM R/W 0b00000000 0x0FE1 — — — 0x0FE2 EVCR Event counter control register R/W 0b00000000 0x0FE3 WCDR Watch counter data register R/W 0b00111111 0x0FE4 CRTH Main CR clock trimming register (upper) R/W 0b000XXXXX 0x0FE5 CRTL Main CR clock trimming register (lower) R/W 0b000XXXXX 0x0FE6 SYSC2 System configuration register 2 R/W 0b00000000 0x0FE7 CRTDA Main CR clock temperature dependent adjustment register R/W 0b000XXXXX 0x0FE8 SYSC System configuration register R/W 0b00111111 0x0FE9 CMCR Clock monitoring control register R/W 0b00000000 0x0FEA CMDR Clock monitoring data register R 0b00000000 0x0FEB WDTH Watchdog timer selection ID register (upper) R 0bXXXXXXXX 0x0FEC WDTL Watchdog timer selection ID register (lower) R 0bXXXXXXXX 0x0FED, 0x0FEE — — — (Disabled) (Disabled) (Disabled) LCDC display RAM (36 bytes) (Disabled) (Disabled) (Continued) DS702–00019–1v0-E 45 MB95710M/770M Series (Continued) Address Register abbreviation 0x0FEF WICR 0x0FF0 to 0x0FFF — Register name Interrupt pin selection circuit control register (Disabled) R/W Initial value R/W 0b01000000 — — • R/W access symbols R/W : Readable/Writable R : Read only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned. 46 DS702–00019–1v0-E MB95710M/770M Series ■ I/O MAP (MB95770M SERIES) Address Register abbreviation 0x0000 PDR0 0x0001 Register name R/W Initial value Port 0 data register R/W 0b00000000 DDR0 Port 0 direction register R/W 0b00000000 0x0002 PDR1 Port 1 data register R/W 0b00000000 0x0003 DDR1 Port 1 direction register R/W 0b00000000 0x0004 — — — 0x0005 WATR Oscillation stabilization wait time setting register R/W 0b11111111 0x0006 PLLC PLL control register R/W 0b000X0000 0x0007 SYCC System clock control register R/W 0bXXX11011 0x0008 STBC Standby control register R/W 0b00000000 0x0009 RSRR Reset source register R/W 0b000XXXXX 0x000A TBTC Time-base timer control register R/W 0b00000000 0x000B WPCR Watch prescaler control register R/W 0b00000000 0x000C WDTC Watchdog timer control register R/W 0b00XX0000 0x000D SYCC2 System clock control register 2 R/W 0bXXXX0011 0x000E PDR2 Port 2 data register R/W 0b00000000 0x000F DDR2 Port 2 direction register R/W 0b00000000 0x0010 to 0x0015 — — — 0x0016 PDR6 Port 6 data register R/W 0b00000000 0x0017 DDR6 Port 6 direction register R/W 0b00000000 0x0018 to 0x001B — — — 0x001C PDR9 Port 9 data register R/W 0b00000000 0x001D DDR9 Port 9 direction register R/W 0b00000000 0x001E PDRA Port A data register R/W 0b00000000 0x001F DDRA Port A direction register R/W 0b00000000 0x0020 PDRB Port B data register R/W 0b00000000 0x0021 DDRB Port B direction register R/W 0b00000000 0x0022 PDRC Port C data register R/W 0b00000000 0x0023 DDRC Port C direction register R/W 0b00000000 0x0024, 0x0025 — — — 0x0026 PDRE Port E data register R/W 0b00000000 0x0027 DDRE Port E direction register R/W 0b00000000 0x0028 PDRF Port F data register R/W 0b00000000 0x0029 DDRF Port F direction register R/W 0b00000000 (Disabled) (Disabled) (Disabled) (Disabled) (Continued) DS702–00019–1v0-E 47 MB95710M/770M Series Address Register abbreviation 0x002A PDRG 0x002B DDRG 0x002C — 0x002D PUL1 0x002E PUL2 0x002F to 0x0034 — 0x0035 PULG 0x0036 Register name R/W Initial value Port G data register R/W 0b00000000 Port G direction register R/W 0b00000000 — — Port 1 pull-up register R/W 0b00000000 Port 2 pull-up register R/W 0b00000000 — — Port G pull-up register R/W 0b00000000 T01CR1 8/16-bit composite timer 01 status control register 1 R/W 0b00000000 0x0037 T00CR1 8/16-bit composite timer 00 status control register 1 R/W 0b00000000 0x0038 T11CR1 8/16-bit composite timer 11 status control register 1 R/W 0b00000000 0x0039 T10CR1 8/16-bit composite timer 10 status control register 1 R/W 0b00000000 0x003A PC01 8/16-bit PPG timer 01 control register R/W 0b00000000 0x003B PC00 8/16-bit PPG timer 00 control register R/W 0b00000000 0x003C PC11 8/16-bit PPG timer 11 control register R/W 0b00000000 0x003D PC10 8/16-bit PPG timer 10 control register R/W 0b00000000 0x003E TMCSRH0 16-bit reload timer control status register (upper) ch. 0 R/W 0b00000000 0x003F TMCSRL0 16-bit reload timer control status register (lower) ch. 0 R/W 0b00000000 0x0040 to 0x0047 — — — 0x0048 EIC00 External interrupt circuit control register ch. 0/ch. 1 R/W 0b00000000 0x0049 EIC10 External interrupt circuit control register ch. 2/ch. 3 R/W 0b00000000 0x004A EIC20 External interrupt circuit control register ch. 4/ch. 5 R/W 0b00000000 0x004B EIC30 External interrupt circuit control register ch. 6/ch. 7 R/W 0b00000000 0x004C, 0x004D — — — 0x004E LVDC LVD control register R/W 0b00000100 0x004F LCDCC2 LCDC control register 2 R/W 0b00010100 0x0050 CMR0 Comparator control register ch. 0 R/W 0b00000001 0x0051 to 0x0055 — — — 0x0056 SMC10 UART/SIO serial mode control register 1 ch. 0 R/W 0b00000000 0x0057 SMC20 UART/SIO serial mode control register 2 ch. 0 R/W 0b00100000 (Disabled) (Disabled) (Disabled) (Disabled) (Disabled) 0x0058 SSR0 UART/SIO serial status and data register ch. 0 R/W 0b00000001 0x0059 TDR0 UART/SIO serial output data register ch. 0 R/W 0b00000000 0x005A RDR0 UART/SIO serial input data register ch. 0 R 0b00000000 (Continued) 48 DS702–00019–1v0-E MB95710M/770M Series Address Register abbreviation 0x005B SMC11 0x005C R/W Initial value UART/SIO serial mode control register 1 ch. 1 R/W 0b00000000 SMC21 UART/SIO serial mode control register 2 ch. 1 R/W 0b00100000 0x005D SSR1 UART/SIO serial status and data register ch. 1 R/W 0b00000001 0x005E TDR1 UART/SIO serial output data register ch. 1 R/W 0b00000000 0x005F RDR1 UART/SIO serial input data register ch. 1 0x0060 0x0061 0x0062 0x0063 0x0064 IBCR00 IBCR10 IBSR0 IDDR0 IAAR0 Register name R 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 2 R/W 0b00000000 2 I C bus control register 0 ch. 0 I C bus control register 1 ch. 0 I C bus status register ch. 0 I C data register ch. 0 I C address register ch. 0 0x0065 ICCR0 I C clock control register ch. 0 R/W 0b00000000 0x0066 SMC12 UART/SIO serial mode control register 1 ch. 2 R/W 0b00000000 0x0067 SMC22 UART/SIO serial mode control register 2 ch. 2 R/W 0b00100000 0x0068 SSR2 UART/SIO serial status and data register ch. 2 R/W 0b00000001 0x0069 TDR2 UART/SIO serial output data register ch. 2 R/W 0b00000000 0x006A RDR2 UART/SIO serial input data register ch. 2 R 0b00000000 0x006B ADC3 8/12-bit A/D converter control register 3 R/W 0b01111100 0x006C ADC1 8/12-bit A/D converter control register 1 R/W 0b00000000 0x006D ADC2 8/12-bit A/D converter control register 2 R/W 0b00000000 0x006E ADDH 8/12-bit A/D converter data register (upper) R/W 0b00000000 0x006F ADDL 8/12-bit A/D converter data register (lower) R/W 0b00000000 0x0070 WCSR Watch counter control register R/W 0b00000000 0x0071 FSR2 Flash memory status register 2 R/W 0b00000000 0x0072 FSR Flash memory status register R/W 0b000X0000 0x0073 SWRE0 Flash memory sector write control register 0 R/W 0b00000000 0x0074 FSR3 Flash memory status register 3 R 0b000XXXXX 0x0075 FSR4 Flash memory status register 4 R/W 0b00000000 0x0076 WREN Wild register address compare enable register R/W 0b00000000 0x0077 WROR Wild register data test setting register R/W 0b00000000 0x0078 — — — 0x0079 ILR0 Interrupt level setting register 0 R/W 0b11111111 0x007A ILR1 Interrupt level setting register 1 R/W 0b11111111 0x007B ILR2 Interrupt level setting register 2 R/W 0b11111111 0x007C ILR3 Interrupt level setting register 3 R/W 0b11111111 0x007D ILR4 Interrupt level setting register 4 R/W 0b11111111 0x007E ILR5 Interrupt level setting register 5 R/W 0b11111111 0x007F — — — Mirror of register bank pointer (RP) and direct bank pointer (DP) (Disabled) (Continued) DS702–00019–1v0-E 49 MB95710M/770M Series Address Register abbreviation 0x0F80 WRARH0 0x0F81 R/W Initial value Wild register address setting register (upper) ch. 0 R/W 0b00000000 WRARL0 Wild register address setting register (lower) ch. 0 R/W 0b00000000 0x0F82 WRDR0 Wild register data setting register ch. 0 R/W 0b00000000 0x0F83 WRARH1 Wild register address setting register (upper) ch. 1 R/W 0b00000000 0x0F84 WRARL1 Wild register address setting register (lower) ch. 1 R/W 0b00000000 0x0F85 WRDR1 Wild register data setting register ch. 1 R/W 0b00000000 0x0F86 WRARH2 Wild register address setting register (upper) ch. 2 R/W 0b00000000 0x0F87 WRARL2 Wild register address setting register (lower) ch. 2 R/W 0b00000000 0x0F88 WRDR2 Wild register data setting register ch. 2 R/W 0b00000000 0x0F89 to 0x0F91 — — — 0x0F92 T01CR0 8/16-bit composite timer 01 status control register 0 R/W 0b00000000 0x0F93 T00CR0 8/16-bit composite timer 00 status control register 0 R/W 0b00000000 0x0F94 T01DR 8/16-bit composite timer 01 data register R/W 0b00000000 0x0F95 T00DR 8/16-bit composite timer 00 data register R/W 0b00000000 0x0F96 TMCR0 8/16-bit composite timer 00/01 timer mode control register R/W 0b00000000 0x0F97 T11CR0 8/16-bit composite timer 11 status control register 0 R/W 0b00000000 0x0F98 T10CR0 8/16-bit composite timer 10 status control register 0 R/W 0b00000000 0x0F99 T11DR 8/16-bit composite timer 11 data register R/W 0b00000000 0x0F9A T10DR 8/16-bit composite timer 10 data register R/W 0b00000000 0x0F9B TMCR1 8/16-bit composite timer 10/11 timer mode control register R/W 0b00000000 0x0F9C PPS01 8/16-bit PPG01 cycle setting buffer register R/W 0b11111111 0x0F9D PPS00 8/16-bit PPG00 cycle setting buffer register R/W 0b11111111 0x0F9E PDS01 8/16-bit PPG01 duty setting buffer register R/W 0b11111111 0x0F9F PDS00 8/16-bit PPG00 duty setting buffer register R/W 0b11111111 0x0FA0 PPS11 8/16-bit PPG11 cycle setting buffer register R/W 0b11111111 0x0FA1 PPS10 8/16-bit PPG10 cycle setting buffer register R/W 0b11111111 0x0FA2 PDS11 8/16-bit PPG11 duty setting buffer register R/W 0b11111111 0x0FA3 PDS10 8/16-bit PPG10 duty setting buffer register R/W 0b11111111 0x0FA4 PPGS 8/16-bit PPG start register R/W 0b00000000 0x0FA5 REVC 8/16-bit PPG output inversion register R/W 0b00000000 R/W 0b00000000 R/W 0b00000000 0x0FA6 0x0FA7 Register name (Disabled) TMRH0 16-bit reload timer timer register (upper) ch. 0 TMRLRH0 16-bit reload timer reload register (upper) ch. 0 TMRL0 16-bit reload timer timer register (lower) ch. 0 TMRLRL0 16-bit reload timer reload register (lower) ch. 0 (Continued) 50 DS702–00019–1v0-E MB95710M/770M Series Address Register abbreviation 0x0FA8 PSSR0 0x0FA9 Register name R/W Initial value UART/SIO dedicated baud rate generator prescaler select register ch. 0 R/W 0b00000000 BRSR0 UART/SIO dedicated baud rate generator baud rate setting register ch. 0 R/W 0b00000000 0x0FAA PSSR1 UART/SIO dedicated baud rate generator prescaler select register ch. 1 R/W 0b00000000 0x0FAB BRSR1 UART/SIO dedicated baud rate generator baud rate setting register ch. 1 R/W 0b00000000 0x0FAC PSSR2 UART/SIO dedicated baud rate generator prescaler select register ch. 2 R/W 0b00000000 0x0FAD BRSR2 UART/SIO dedicated baud rate generator baud rate setting register ch. 2 R/W 0b00000000 0x0FAE — — — 0x0FAF AIDRL A/D input disable register (lower) R/W 0b00000000 0x0FB0 LCDCC1 LCDC control register 1 R/W 0b00000000 0x0FB1 — — — 0x0FB2 LCDCE1 LCDC enable register 1 R/W 0b00111110 0x0FB3 LCDCE2 LCDC enable register 2 R/W 0b00000000 0x0FB4 LCDCE3 LCDC enable register 3 R/W 0b00000000 0x0FB5 LCDCE4 LCDC enable register 4 R/W 0b00000000 0x0FB6 LCDCE5 LCDC enable register 5 R/W 0b00000000 0x0FB7 LCDCE6 LCDC enable register 6 R/W 0b00000000 0x0FB8 — — — 0x0FB9 LCDCB1 LCDC blinking setting register 1 R/W 0b00000000 0x0FBA LCDCB2 LCDC blinking setting register 2 R/W 0b00000000 0x0FBB, 0x0FBC — — — 0x0FBD to 0x0FD8 LCDRAM R/W 0b00000000 0x0FD9 to 0x0FE1 — — — 0x0FE2 EVCR Event counter control register R/W 0b00000000 0x0FE3 WCDR Watch counter data register R/W 0b00111111 0x0FE4 CRTH Main CR clock trimming register (upper) R/W 0b000XXXXX 0x0FE5 CRTL Main CR clock trimming register (lower) R/W 0b000XXXXX 0x0FE6 SYSC2 System configuration register 2 R/W 0b00000000 0x0FE7 CRTDA Main CR clock temperature dependent adjustment register R/W 0b000XXXXX 0x0FE8 SYSC System configuration register R/W 0b00111111 0x0FE9 CMCR Clock monitoring control register R/W 0b00000000 0x0FEA CMDR Clock monitoring data register R 0b00000000 (Disabled) (Disabled) (Disabled) (Disabled) LCDC display RAM (28 bytes) (Disabled) (Continued) DS702–00019–1v0-E 51 MB95710M/770M Series (Continued) Address Register abbreviation 0x0FEB WDTH 0x0FEC WDTL 0x0FED, 0x0FEE — 0x0FEF WICR 0x0FF0 to 0x0FFF — Register name R/W Initial value Watchdog timer selection ID register (upper) R 0bXXXXXXXX Watchdog timer selection ID register (lower) R 0bXXXXXXXX — — R/W 0b01000000 — — (Disabled) Interrupt pin selection circuit control register (Disabled) • R/W access symbols R/W : Readable/Writable R : Read only • Initial value symbols 0 : The initial value of this bit is “0”. 1 : The initial value of this bit is “1”. X : The initial value of this bit is undefined. Note: Do not write to an address that is “(Disabled)”. If a “(Disabled)” address is read, an indeterminate value is returned. 52 DS702–00019–1v0-E MB95710M/770M Series ■ I/O PORTS (MB95710M SERIES) • List of port registers Register name Read/Write Initial value Port 0 data register PDR0 R, RM/W 0b00000000 Port 0 direction register DDR0 R/W 0b00000000 Port 1 data register PDR1 R, RM/W 0b00000000 Port 1 direction register DDR1 R/W 0b00000000 Port 2 data register PDR2 R, RM/W 0b00000000 Port 2 direction register DDR2 R/W 0b00000000 Port 4 data register PDR4 R, RM/W 0b00000000 Port 4 direction register DDR4 R/W 0b00000000 Port 5 data register PDR5 R, RM/W 0b00000000 Port 5 direction register DDR5 R/W 0b00000000 Port 6 data register PDR6 R, RM/W 0b00000000 Port 6 direction register DDR6 R/W 0b00000000 Port 9 data register PDR9 R, RM/W 0b00000000 Port 9 direction register DDR9 R/W 0b00000000 Port A data register PDRA R, RM/W 0b00000000 Port A direction register DDRA R/W 0b00000000 Port B data register PDRB R, RM/W 0b00000000 Port B direction register DDRB R/W 0b00000000 Port C data register PDRC R, RM/W 0b00000000 Port C direction register DDRC R/W 0b00000000 Port E data register PDRE R, RM/W 0b00000000 Port E direction register DDRE R/W 0b00000000 Port F data register PDRF R, RM/W 0b00000000 Port F direction register DDRF R/W 0b00000000 Port G data register PDRG R, RM/W 0b00000000 Port G direction register DDRG R/W 0b00000000 Port 1 pull-up register PUL0 R/W 0b00000000 Port 2 pull-up register PUL1 R/W 0b00000000 Port 5 pull-up register PUL5 R/W 0b00000000 Port G pull-up register PULG R/W 0b00000000 A/D input disable register (lower) AIDRL R/W 0b00000000 R/W : Readable/writable (The read value is the same as the write value.) R, RM/W : Readable/writable (The read value is different from the write value. The write value is read by the read-modify-write (RMW) type of instruction.) DS702–00019–1v0-E 53 MB95710M/770M Series 1. Port 0 Port 0 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port 0 configuration Port 0 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 0 data register (PDR0) • Port 0 direction register (DDR0) • A/D input disable register (lower) (AIDRL) (2) Block diagrams of port 0 • P00/INT00/AN00/UO2 pin This pin has the following peripheral functions: • External interrupt input pin (INT00) • 8/12-bit A/D converter analog input pin (AN00) • UART/SIO ch. 2 data output pin (UO2) • P02/INT02/AN02/SEG35/UCK2 pin This pin has the following peripheral functions: • External interrupt input pin (INT02) • 8/12-bit A/D converter analog input pin (AN02) • LCDC SEG35 output pin (SEG35) • UART/SIO ch. 2 clock I/O pin (UCK2) • P03/INT03/AN03/SEG34/UO1 pin This pin has the following peripheral functions: • External interrupt input pin (INT03) • 8/12-bit A/D converter analog input pin (AN03) • LCDC SEG34 output pin (SEG34) • UART/SIO ch. 1 data output pin (UO1) • P05/INT05/AN05/SEG32/UCK1 pin This pin has the following peripheral functions: • External interrupt input pin (INT05) • 8/12-bit A/D converter analog input pin (AN05) • LCDC SEG32 output pin (SEG32) • UART/SIO ch. 1 clock I/O pin (UCK1) • P06/INT06/AN06/SEG31 pin This pin has the following peripheral functions: • External interrupt input pin (INT06) • 8/12-bit A/D converter analog input pin (AN06) • LCDC SEG31 output pin (SEG31) • P07/INT07/AN07/SEG30 pin This pin has the following peripheral functions: • External interrupt input pin (INT07) • 8/12-bit A/D converter analog input pin (AN07) • LCDC SEG30 output pin (SEG30) 54 DS702–00019–1v0-E MB95710M/770M Series • Block diagram of P00/INT00/AN00/UO2, P02/INT02/AN02/SEG35/UCK2, P03/INT03/AN03/SEG34/UO1, P05/INT05/AN05/SEG32/UCK1, P06/INT06/AN06/SEG31 and P07/INT07/AN07/SEG30 LCD output Peripheral function input Peripheral function input enable (INT00, INT02, INT03, INT05, INT06 and INT07) A/D analog input Peripheral function output enable Peripheral function output LCD output enable 0 1 PDR0 read 1 PDR0 0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) AIDRL read AIDRL AIDRL write DS702–00019–1v0-E 55 MB95710M/770M Series • P01/INT01/AN01/SEG36/UI2 pin This pin has the following peripheral functions: • External interrupt input pin (INT01) • 8/12-bit A/D converter analog input pin (AN01) • LCDC SEG36 output pin (SEG36) • UART/SIO ch. 2 data input pin (UI2) • P04/INT04/AN04/SEG33/UI1 pin This pin has the following peripheral functions: • External interrupt input pin (INT04) • 8/12-bit A/D converter analog input pin (AN04) • LCDC SEG33 output pin (SEG33) • UART/SIO ch. 1 data input pin (UI1) • Block diagram of P01/INT01/AN01/SEG36/UI2 and P04/INT04/AN04/SEG33/UI1 LCD output Peripheral function input A/D analog input Peripheral function input enable (INT01 and INT04) LCD output enable Peripheral function output enable Peripheral function output 0 1 PDR0 read CMOS 1 PDR0 0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) AIDRL read AIDRL AIDRL write 56 DS702–00019–1v0-E MB95710M/770M Series (3) Port 0 registers • Port 0 register functions Register abbreviation PDR0 DDR0 AIDRL Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR0 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR0 value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Analog input enabled 1 Port input enabled • Correspondence between registers and pins for port 0 Correspondence between related register bits and pins Pin name P07 P06 P05 P04 P03 P02 P01 P00 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 PDR0 DDR0 AIDRL DS702–00019–1v0-E 57 MB95710M/770M Series (4) Port 0 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR0 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR0 register to external pins. • If data is written to the PDR0 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR0 register returns the PDR0 register value. • To use a pin shared with the LCDC as an output port, set a corresponding function select bit in the LCDC enable register 6 (LCDCE6:SEG[31:30]) or in the LCDC enable register 7 (LCDCE7:SEG[36:32]) to “0” to select the general-purpose I/O port function, and then set the port input control bit in the LCDC enable register 1 (LCDCE1:PICTL) to “1”. • Operation as an input port • A pin becomes an input port if the bit in the DDR0 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When using an analog input shared pin as an input port, set the corresponding bit in the A/D input disable register (lower) (AIDRL) to “1”. • If data is written to the PDR0 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR0 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. • To use a pin shared with the LCDC as an input port, set a corresponding function select bit in the LCDC enable register 6 (LCDCE6:SEG[31:30]) or in the LCDC enable register 7 (LCDCE7:SEG[36:32]) to “0” to select the general-purpose I/O port function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR0 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR0 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR0 register corresponding to the input pin of a peripheral function to “0”. • When using the analog input shared pin as another peripheral function input pin, configure it as an input port, which is the same as the operation as an input port. • Reading the PDR0 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. • Operation as an LCDC segment output pin • Set the bit in the DDR0 register corresponding to an LCDC segment output pin to “0”. • To use a pin shared with a general-purpose I/O port as an LCDC segment output pin, set a corresponding function select bit in the LCDC enable register 6 (LCDCE6:SEG[31:30]) or in the LCDC enable register 7 (LCDCE7:SEG[36:32]) to “1” to select the LCDC segment output function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation at reset If the CPU is reset, all bits in the DDR0 register are initialized to “0” and port input is enabled. As for a pin shared with analog input, its port input is disabled because the AIDRL register is initialized to “0”. 58 DS702–00019–1v0-E MB95710M/770M Series • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR0 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input is enabled for the external interrupt (INT00 to INT07), the input is enabled and not blocked. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as an analog input pin • Set the bit in the DDR0 register bit corresponding to the analog input pin to “0” and the bit corresponding to that pin in the AIDRL register to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • Operation as an external interrupt input pin • Set the bit in the DDR0 register corresponding to the external interrupt input pin to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt, disable the external interrupt function corresponding to that pin. DS702–00019–1v0-E 59 MB95710M/770M Series 2. Port 1 Port 1 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port 1 configuration Port 1 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 1 data register (PDR1) • Port 1 direction register (DDR1) • Port 1 pull-up register (PUL1) (2) Block diagrams of port 1 • P10/UI0 pin This pin has the following peripheral function: • UART/SIO ch. 0 data input pin (UI0) • Block diagram of P10/UI0 Peripheral function input Peripheral function input enable CMOS 0 Pull-up 1 PDR1 read PDR1 Pin PDR1 write Internal bus Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) PUL1 read PUL1 PUL1 write 60 DS702–00019–1v0-E MB95710M/770M Series • P12/DBG pin This pin has the following peripheral function: • DBG input pin (DBG) • Block diagram of P12/DBG Hysteresis 0 1 PDR1 read Internal bus PDR1 Pin OD PDR1 write Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E 61 MB95710M/770M Series • P11/UO0 pin This pin has the following peripheral function: • UART/SIO ch. 0 data output pin (UO0) • P13/ADTG pin This pin has the following peripheral function: • 8/12-bit A/D converter trigger input pin (ADTG) • P14/UCK0 pin This pin has the following peripheral function: • UART/SIO ch. 0 clock I/O pin (UCK0) • P17/CMP0_O pin This pin has the following peripheral function: • Comparator ch. 0 digital output pin (CMP0_O) • Block diagram of P11/UO0, P13/ADTG, P14/UCK0 and P17/CMP0_O Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output Pull-up 0 1 PDR1 read 1 PDR1 0 Pin PDR1 write Internal bus Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) PUL1 read PUL1 PUL1 write 62 DS702–00019–1v0-E MB95710M/770M Series • P15/PPG11 pin This pin has the following peripheral function: • 8/16-bit PPG ch. 1 output pin (PPG11) • P16/PPG10 pin This pin has the following peripheral function: • 8/16-bit PPG ch. 1 output pin (PPG10) • Block diagram of P15/PPG11 and P16/PPG10 Peripheral function output enable Peripheral function output 0 1 PDR1 read 1 Internal bus PDR1 0 Pin PDR1 write Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E 63 MB95710M/770M Series (3) Port 1 registers • Port 1 register functions Register abbreviation PDR1 DDR1 PUL1 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR1 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR1 value is “1”. As output port, outputs “H” level.* 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled *: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. • Correspondence between registers and pins for port 1 Correspondence between related register bits and pins Pin name P17 PDR1 DDR1 PUL1 64 bit7 P16 P15 bit6 bit5 - - P14 P13 bit4 bit3 P12 bit2 P11 P10 bit1 bit0 - DS702–00019–1v0-E MB95710M/770M Series (4) Port 1 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR1 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR1 register to external pins. • If data is written to the PDR1 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR1 register returns the PDR1 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR1 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDR1 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR1 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR1 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR1 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR1 register corresponding to the input pin of a peripheral function to “0”. • Reading the PDR1 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR1 register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR1 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input of P10/UI0 and P14/UCK0 is enabled by the external interrupt control register ch. 0 (EIC00) of the external interrupt circuit and the interrupt pin selection circuit control register (WICR) of the interrupt pin selection circuit, the input is enabled and is not blocked. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation of the pull-up register Setting the bit in the PUL1 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL1 register. DS702–00019–1v0-E 65 MB95710M/770M Series 3. Port 2 Port 2 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port 2 configuration Port 2 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 2 data register (PDR2) • Port 2 direction register (DDR2) • Port 2 pull-up register (PUL2) (2) Block diagrams of port 2 • P20/PPG00/CMP0_N pin This pin has the following peripheral functions: • 8/16-bit PPG ch. 0 output pin (PPG00) • Comparator ch. 0 inverting analog input (negative input) pin (CMP0_N) • P21/PPG01/CMP0_P pin This pin has the following peripheral functions: • 8/16-bit PPG ch. 0 output pin (PPG01) • Comparator ch. 0 non-inverting analog input (positive input) pin (CMP0_P) • Block diagram of P20/PPG00/CMP0_N and P21/PPG01/CMP0_P Analog input Peripheral function output enable Peripheral function output Analog input enable Pull-up 0 1 PDR2 read 1 PDR2 0 Pin PDR2 write Internal bus Executing bit manipulation instruction DDR2 read DDR2 DDR2 write Stop mode, watch mode (SPL = 1) PUL2 read PUL2 PUL2 write 66 DS702–00019–1v0-E MB95710M/770M Series • P22/SCL pin This pin has the following peripheral function: • I2C bus interface ch. 0 clock I/O pin (SCL) • P23/SDA pin This pin has the following peripheral function: • I2C bus interface ch. 0 data I/O pin (SDA) • Block diagram of P22/SCL and P23/SDA Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output CMOS 0 1 PDR2 read PDR2 Internal bus Pin 1 0 OD PDR2 write Executing bit manipulation instruction DDR2 read DDR2 DDR2 write Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E 67 MB95710M/770M Series (3) Port 2 registers • Port 2 register functions Register abbreviation PDR2 DDR2 PUL2 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR2 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR2 value is “1”. As output port, outputs “H” level.* 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled *: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. • Correspondence between registers and pins for port 2 Correspondence between related register bits and pins Pin name - - - - - - - - PDR2 DDR2 PUL2 68 P23 P22 bit3 bit2 - - P21 P20 bit1 bit0 DS702–00019–1v0-E MB95710M/770M Series (4) Port 2 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR2 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR2 register to external pins. • If data is written to the PDR2 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR2 register returns the PDR2 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR2 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDR2 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR2 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR2 register, the PDR2 register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR2 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR2 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR2 register, the PDR2 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR2 register corresponding to the input pin of a peripheral function to “0”. • Reading the PDR2 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR2 register, the PDR2 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR2 register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR2 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation of the pull-up register Setting the bit in the PUL2 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL2 register. • Operation as a comparator input pin • Regardless of the value of the PDR2 register and that of the DDR2 register, if the comparator analog input enable bit in the comparator control register ch. 0 (CMR0:VCID) is set to “0”, the comparator input function is enabled. • To disable the comparator input function, set the VCID bit to “1”. • For details of the comparator, refer to “CHAPTER 29 COMPARATOR” in “New 8FX MB95710M/770M Series Hardware Manual”. DS702–00019–1v0-E 69 MB95710M/770M Series 4. Port 4 Port 4 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port 4 configuration Port 4 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 4 data register (PDR4) • Port 4 direction register (DDR4) (2) Block diagrams of port 4 • P40/SEG21 pin This pin has the following peripheral function: • LCDC SEG21 output pin (SEG21) • P41/SEG20 pin This pin has the following peripheral function: • LCDC SEG20 output pin (SEG20) • P42/SEG19 pin This pin has the following peripheral function: • LCDC SEG19 output pin (SEG19) • P43/SEG18 pin This pin has the following peripheral function: • LCDC SEG18 output pin (SEG18) • Block diagram of P40/SEG21, P41/SEG20, P42/SEG19 and P43/SEG18 LCD output LCD output enable 0 1 PDR4 read Internal bus PDR4 Pin PDR4 write Executing bit manipulation instruction DDR4 read DDR4 DDR4 write 70 Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E MB95710M/770M Series (3) Port 4 registers • Port 4 register functions Register abbreviation PDR4 DDR4 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR4 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR4 value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled • Correspondence between registers and pins for port 4 Correspondence between related register bits and pins Pin name PDR4 DDR4 - - - - P43 P42 P41 P40 - - - - bit3 bit2 bit1 bit0 DS702–00019–1v0-E 71 MB95710M/770M Series (4) Port 4 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR4 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR4 register to external pins. • If data is written to the PDR4 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR4 register returns the PDR4 register value. • To use a pin shared with the LCDC as an output port, set a corresponding function select bit in the LCDC enable register 5 (LCDCE5:SEG[21:18]) to “0” to select the general-purpose I/O port function, and then set the port input control bit in the LCDC enable register 1 (LCDCE1:PICTL) to “1”. • Operation as an input port • A pin becomes an input port if the bit in the DDR4 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDR4 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR4 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR4 register, the PDR4 register value is returned. • To use a pin shared with the LCDC as an input port, set a corresponding function select bit in the LCDC enable register 5 (LCDCE5:SEG[21:18]) to “0” to select the general-purpose I/O port function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation as an LCDC segment output pin • Set the bit in the DDR4 register corresponding to an LCDC segment output pin to “0”. • To use a pin shared with a general-purpose I/O port as an LCDC segment output pin, set a corresponding function select bit in the LCDC enable register 5 (LCDCE5:SEG[21:18]) to “1” to select the LCDC segment output function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation at reset If the CPU is reset, all bits in the DDR4 register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR4 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. 72 DS702–00019–1v0-E MB95710M/770M Series 5. Port 5 Port 5 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port 5 configuration Port 5 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 5 data register (PDR5) • Port 5 direction register (DDR5) • Port 5 pull-up register (PUL5) (2) Block diagrams of port 5 • P50/TO01 pin This pin has the following peripheral function: • 8/16-bit composite timer ch. 0 output pin (TO01) • P51/EC0 pin This pin has the following peripheral function: • 8/16-bit composite timer ch. 0 clock input pin (EC0) • P52/TI0/TO00 pin This pin has the following peripheral functions: • 16-bit reload timer ch. 0 input pin (TI0) • 8/16-bit composite timer ch. 0 output pin (TO00) • P53/TO0 pin This pin has the following peripheral function: • 16-bit reload timer ch. 0 output pin (TO0) • Block diagram of P50/TO01, P51/EC0, P52/TI0/TO00 and P53/TO0 Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output Pull-up 0 1 PDR5 read 1 PDR5 0 Pin PDR5 write Internal bus Executing bit manipulation instruction DDR5 read DDR5 DDR5 write Stop mode, watch mode (SPL = 1) PUL5 read PUL5 PUL5 write DS702–00019–1v0-E 73 MB95710M/770M Series (3) Port 5 registers • Port 5 register functions Register abbreviation PDR5 DDR5 PUL5 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR5 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR5 value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled • Correspondence between registers and pins for port 5 Correspondence between related register bits and pins Pin name - - - - P53 P52 P51 P50 - - - - bit3 bit2 bit1 bit0 PDR5 DDR5 PUL5 74 DS702–00019–1v0-E MB95710M/770M Series (4) Port 5 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR5 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR5 register to external pins. • If data is written to the PDR5 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR5 register returns the PDR5 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR5 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDR5 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR5 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR5 register, the PDR5 register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR5 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR5 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR5 register, the PDR5 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR5 register corresponding to the input pin of a peripheral function to “0”. • Reading the PDR5 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR5 register, the PDR5 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR5 register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR5 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation of the pull-up register Setting the bit in the PUL5 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL5 register. DS702–00019–1v0-E 75 MB95710M/770M Series 6. Port 6 Port 6 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) 76 Port 6 configuration Port 6 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 6 data register (PDR6) • Port 6 direction register (DDR6) DS702–00019–1v0-E MB95710M/770M Series (2) Block diagrams of port 6 • P60/SEG10 pin This pin has the following peripheral function: • LCDC SEG10 output pin (SEG10) • P61/SEG11 pin This pin has the following peripheral function: • LCDC SEG11 output pin (SEG11) • P62/SEG12 pin This pin has the following peripheral function: • LCDC SEG12 output pin (SEG12) • P63/SEG13 pin This pin has the following peripheral function: • LCDC SEG13 output pin (SEG13) • P64/SEG14 pin This pin has the following peripheral function: • LCDC SEG14 output pin (SEG14) • P65/SEG15 pin This pin has the following peripheral function: • LCDC SEG15 output pin (SEG15) • P66/SEG16 pin This pin has the following peripheral function: • LCDC SEG16 output pin (SEG16) • P67/SEG17 pin This pin has the following peripheral function: • LCDC SEG17 output pin (SEG17) • Block diagram of P60/SEG10, P61/SEG11, P62/SEG12, P63/SEG13, P64/SEG14, P65/SEG15, P66/SEG16 and P67/SEG17 LCD output LCD output enable 0 1 PDR6 read Internal bus PDR6 Pin PDR6 write Executing bit manipulation instruction DDR6 read DDR6 DDR6 write Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E 77 MB95710M/770M Series (3) Port 6 registers • Port 6 register functions Register abbreviation PDR6 DDR6 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR6 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR6 value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled • Correspondence between registers and pins for port 6 Correspondence between related register bits and pins Pin name PDR6 DDR6 78 P67 P66 P65 P64 P63 P62 P61 P60 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DS702–00019–1v0-E MB95710M/770M Series (4) Port 6 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR6 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR6 register to external pins. • If data is written to the PDR6 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR6 register returns the PDR6 register value. • To use a pin shared with the LCDC as an output port, set a corresponding function select bit in the LCDC enable register 4 (LCDCE4:SEG[15:10]) or in the LCDC enable register 5 (LCDCE5:SEG[17:16]) to “0” to select the general-purpose I/O port function, and then set the port input control bit in the LCDC enable register 1 (LCDCE1:PICTL) to “1”. • Operation as an input port • A pin becomes an input port if the bit in the DDR6 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDR6 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR6 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is returned. • To use a pin shared with the LCDC as an input port, set a corresponding function select bit in the LCDC enable register 4 (LCDCE4:SEG[15:10]) or in the LCDC enable register 5 (LCDCE5:SEG[17:16]) to “0” to select the general-purpose I/O port function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation as an LCDC segment output pin • Set the bit in the DDR6 register corresponding to an LCDC segment output pin to “0”. • To use a pin shared with a general-purpose I/O port as an LCDC segment output pin, set a corresponding function select bit in the LCDC enable register 4 (LCDCE4:SEG[15:10]) or in the LCDC enable register 5 (LCDCE5:SEG[17:16]) to “1” to select the LCDC segment output function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation at reset If the CPU is reset, all bits in the DDR6 register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR6 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. DS702–00019–1v0-E 79 MB95710M/770M Series 7. Port 9 Port 9 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port 9 configuration Port 9 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 9 data register (PDR9) • Port 9 direction register (DDR9) (2) Block diagrams of port 9 • P90/V4 pin This pin has the following peripheral function: • LCD drive power supply pin (V4) • P91/V3 pin This pin has the following peripheral function: • LCD drive power supply pin (V3) • P92/V2 pin This pin has the following peripheral function: • LCD drive power supply pin (V2) • P93/V1 pin This pin has the following peripheral function: • LCD drive power supply pin (V1) • P94/V0 pin This pin has the following peripheral function: • LCD drive power supply pin (V0) • Block diagram of P90/V4, P91/V3, P92/V2, P93/V1 and P94/V0 LCD power supply LCD power supply enable 0 1 PDR9 read Internal bus PDR9 Pin PDR9 write Executing bit manipulation instruction DDR9 read DDR9 DDR9 write 80 Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E MB95710M/770M Series (3) Port 9 registers • Port 9 register functions Register abbreviation PDR9 DDR9 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR9 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR9 value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled • Correspondence between registers and pins for port 9 Correspondence between related register bits and pins Pin name PDR9 DDR9 - - - P94 P93 P92 P91 P90 - - - bit4 bit3 bit2 bit1 bit0 DS702–00019–1v0-E 81 MB95710M/770M Series (4) Port 9 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR9 register corresponding to that pin is set to “1”. • When a pin is used as an output port, it outputs the value of the PDR9 register to external pins. • If data is written to the PDR9 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR9 register returns the PDR9 register value. • To use a pin shared with the LCDC as an output port, set the bit corresponding to that pin in the VE[4:0] bits in the LCDC enable register 1 (LCDCE1) to “0” to select the general-purpose I/O port function. • Operation as an input port • A pin becomes an input port if the bit in the DDR9 register corresponding to that pin is set to “0”. • If data is written to the PDR9 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR9 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR9 register, the PDR9 register value is returned. • To use a pin shared with the LCDC as an input port, set the bit corresponding to that pin in the VE[4:0] bits in the LCDCE1 register to “0” to select the general-purpose I/O port function. • Operation at reset If the CPU is reset, all bits in the DDR9 register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR9 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as an LCD drive power supply pin • Set the bit in the DDR9 register corresponding to an LCD drive power supply pin to “0”. • To use a pin shared with a general-purpose I/O port as an LCD drive power supply pin, set the bit corresponding to that pin in the VE[4:0] bits in the LCDCE1 register to “1” to select the LCD drive power supply function. 82 DS702–00019–1v0-E MB95710M/770M Series 8. Port A Port A is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port A configuration Port A is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port A data register (PDRA) • Port A direction register (DDRA) DS702–00019–1v0-E 83 MB95710M/770M Series (2) Block diagrams of port A • PA0/COM0 pin This pin has the following peripheral function: • LCDC COM0 output pin (COM0) • PA1/COM1 pin This pin has the following peripheral function: • LCDC COM1 output pin (COM1) • PA2/COM2 pin This pin has the following peripheral function: • LCDC COM2 output pin (COM2) • PA3/COM3 pin This pin has the following peripheral function: • LCDC COM3 output pin (COM3) • PA4/COM4 pin This pin has the following peripheral function: • LCDC COM4 output pin (COM4) • PA5/COM5 pin This pin has the following peripheral function: • LCDC COM5 output pin (COM5) • PA6/COM6 pin This pin has the following peripheral function: • LCDC COM6 output pin (COM6) • PA7/COM7 pin This pin has the following peripheral function: • LCDC COM7 output pin (COM7) • Block diagram of PA0/COM0, PA1/COM1, PA2/COM2, PA3/COM3, PA4/COM4, PA5/COM5, PA6/COM6 and PA7/COM7 LCD output LCD output enable 0 1 PDRA read Internal bus PDRA Pin PDRA write Executing bit manipulation instruction DDRA read DDRA DDRA write 84 Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E MB95710M/770M Series (3) Port A registers • Port A register functions Register abbreviation PDRA DDRA Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRA value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRA value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled • Correspondence between registers and pins for port A Correspondence between related register bits and pins Pin name PDRA DDRA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DS702–00019–1v0-E 85 MB95710M/770M Series (4) Port A operations • Operation as an output port • A pin becomes an output port if the bit in the DDRA register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRA register to external pins. • If data is written to the PDRA register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRA register returns the PDRA register value. • To use a pin shared with the LCDC as an output port, set a corresponding function select bit in the LCDC enable register 2 (LCDCE2:COM[7:0]) to “0” to select the general-purpose I/O port function, and then set the port input control bit in the LCDC enable register 1 (LCDCE1:PICTL) to “1”. • Operation as an input port • A pin becomes an input port if the bit in the DDRA register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDRA register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRA register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRA register, the PDRA register value is returned. • To use a pin shared with the LCDC as an input port, set a corresponding function select bit in the LCDC enable register 2 (LCDCE2:COM[7:0]) to “0” to select the general-purpose I/O port function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation as an LCDC common output pin • Set the bit in the DDRA register corresponding to an LCDC common output pin to “0”. • To use a pin shared with a general-purpose I/O port as an LCDC common output pin, set a corresponding function select bit in the LCDC enable register 2 (LCDCE2:COM[7:0]) to “1” to select the LCDC common output function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation at reset If the CPU is reset, all bits in the DDRA register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRA register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. 86 DS702–00019–1v0-E MB95710M/770M Series 9. Port B Port B is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port B configuration Port B is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port B data register (PDRB) • Port B direction register (DDRB) (2) Block diagrams of port B • PB0/SEG00 pin This pin has the following peripheral function: • LCDC SEG00 output pin (SEG00) • PB1/SEG01 pin This pin has the following peripheral function: • LCDC SEG01 output pin (SEG01) • PB2/SEG37 pin This pin has the following peripheral function: • LCDC SEG37 output pin (SEG37) • PB3/SEG38 pin This pin has the following peripheral function: • LCDC SEG38 output pin (SEG38) • PB4/SEG39 pin This pin has the following peripheral function: • LCDC SEG39 output pin (SEG39) • Block diagram of PB0/SEG00, PB1/SEG01, PB2/SEG37, PB3/SEG38 and PB4/SEG39 LCD output LCD output enable 0 1 PDRB read Internal bus PDRB Pin PDRB write Executing bit manipulation instruction DDRB read DDRB DDRB write Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E 87 MB95710M/770M Series (3) Port B registers • Port B register functions Register abbreviation PDRB DDRB Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRB value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRB value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled • Correspondence between registers and pins for port B Correspondence between related register bits and pins Pin name PDRB DDRB 88 - - - PB4 PB3 PB2 PB1 PB0 - - - bit4 bit3 bit2 bit1 bit0 DS702–00019–1v0-E MB95710M/770M Series (4) Port B operations • Operation as an output port • A pin becomes an output port if the bit in the DDRB register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRB register to external pins. • If data is written to the PDRB register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRB register returns the PDRB register value. • To use a pin shared with the LCDC as an output port, set a corresponding function select bit in the LCDC enable register 3 (LCDCE3:SEG[01:00]) or in the LCDC enable register 7 (LCDCE7:SEG[39:37]) to “0” to select the general-purpose I/O port function, and then set the port input control bit (PICTL) in the LCDC enable register 1 (LCDCE1) to “1”. • Operation as an input port • A pin becomes an input port if the bit in the DDRB register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDRB register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRB register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRB register, the PDRB register value is returned. • To use a pin shared with the LCDC as an input port, set a corresponding function select bit in the LCDC enable register 3 (LCDCE3:SEG[01:00]) or in the LCDC enable register 7 (LCDCE7:SEG[39:37]) to “0” to select the general-purpose I/O port function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation as an LCDC segment output pin • Set the bit in the DDRB register corresponding to an LCDC segment output pin to “0”. • To use a pin shared with a general-purpose I/O port as an LCDC segment output pin, set a corresponding function select bit in the LCDC enable register 3 (LCDCE3:SEG[01:00]) or in the LCDC enable register 7 (LCDCE7:SEG[39:37]) to “1” to select the LCDC segment output function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation at reset If the CPU is reset, all bits in the DDRB register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRB register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. DS702–00019–1v0-E 89 MB95710M/770M Series 10. Port C Port C is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) 90 Port C configuration Port C is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port C data register (PDRC) • Port C direction register (DDRC) DS702–00019–1v0-E MB95710M/770M Series (2) Block diagrams of port C • PC0/SEG02 pin This pin has the following peripheral function: • LCDC SEG02 output pin (SEG02) • PC1/SEG03 pin This pin has the following peripheral function: • LCDC SEG03 output pin (SEG03) • PC2/SEG04 pin This pin has the following peripheral function: • LCDC SEG04 output pin (SEG04) • PC3/SEG05 pin This pin has the following peripheral function: • LCDC SEG05 output pin (SEG05) • PC4/SEG06 pin This pin has the following peripheral function: • LCDC SEG06 output pin (SEG06) • PC5/SEG07 pin This pin has the following peripheral function: • LCDC SEG07 output pin (SEG07) • PC6/SEG08 pin This pin has the following peripheral function: • LCDC SEG08 output pin (SEG08) • PC7/SEG09 pin This pin has the following peripheral function: • LCDC SEG09 output pin (SEG09) • Block diagram of PC0/SEG02, PC1/SEG03, PC2/SEG04, PC3/SEG05, PC4/SEG06, PC5/SEG07, PC6/SEG08 and PC7/SEG09 LCD output LCD output enable 0 1 PDRC read Internal bus PDRC Pin PDRC write Executing bit manipulation instruction DDRC read DDRC DDRC write Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E 91 MB95710M/770M Series (3) Port C registers • Port C register functions Register abbreviation PDRC DDRC Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRC value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRC value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled • Correspondence between registers and pins for port C Correspondence between related register bits and pins Pin name PDRC DDRC 92 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DS702–00019–1v0-E MB95710M/770M Series (4) Port C operations • Operation as an output port • A pin becomes an output port if the bit in the DDRC register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRC register to external pins. • If data is written to the PDRC register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRC register returns the PDRC register value. • To use a pin shared with the LCDC as an output port, set a corresponding function select bit in the LCDC enable register 3 (LCDCE3:SEG[07:02]) or in the LCDC enable register 4 (LCDCE4:SEG[09:08]) to “0” to select the general-purpose I/O port function, and then set the port input control bit in the LCDC enable register 1 (LCDCE1:PICTL) to “1”. • Operation as an input port • A pin becomes an input port if the bit in the DDRC register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDRC register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRC register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRC register, the PDRC register value is returned. • To use a pin shared with the LCDC as an input port, set a corresponding function select bit in the LCDC enable register 3 (LCDCE3:SEG[07:02]) or in the LCDC enable register 4 (LCDCE4:SEG[09:08]) to “0” to select the general-purpose I/O port function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation as an LCDC segment output pin • Set the bit in the DDRC register corresponding to an LCDC segment output pin to “0”. • To use a pin shared with a general-purpose I/O port as an LCDC segment output pin, set a corresponding function select bit in the LCDC enable register 3 (LCDCE3:SEG[07:02]) or in the LCDC enable register 4 (LCDCE4:SEG[09:08]) to “1” to select the LCDC segment output function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation at reset If the CPU is reset, all bits in the DDRC register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRC register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. DS702–00019–1v0-E 93 MB95710M/770M Series 11. Port E Port E is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port E configuration Port E is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port E data register (PDRE) • Port E direction register (DDRE) (2) Block diagrams of port E • PE0/SEG22 pin This pin has the following peripheral function: • LCDC SEG22 output pin (SEG22) • PE1/SEG23 pin This pin has the following peripheral function: • LCDC SEG23 output pin (SEG23) • PE2/SEG24 pin This pin has the following peripheral function: • LCDC SEG24 output pin (SEG24) • PE3/SEG25 pin This pin has the following peripheral function: • LCDC SEG25 output pin (SEG25) • PE4/SEG26 pin This pin has the following peripheral function: • LCDC SEG26 output pin (SEG26) • Block diagram of PE0/SEG22, PE1/SEG23, PE2/SEG24, PE3/SEG25 and PE4/SEG26 LCD output LCD output enable 0 1 PDRE read Internal bus PDRE Pin PDRE write Executing bit manipulation instruction DDRE read DDRE DDRE write 94 Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E MB95710M/770M Series • PE5/SEG27/TO11 pin This pin has the following peripheral functions: • LCDC SEG27 output pin (SEG27) • 8/16-bit composite timer ch. 1 output pin (TO11) • PE6/SEG28/TO10 pin This pin has the following peripheral functions: • LCDC SEG28 output pin (SEG28) • 8/16-bit composite timer ch. 1 output pin (TO10) • PE7/SEG29/EC1 pin This pin has the following peripheral functions: • LCDC SEG29 output pin (SEG29) • 8/16-bit composite timer ch. 1 clock input pin (EC1) • Block diagram of PE5/SEG27/TO11, PE6/SEG28/TO10 and PE7/SEG29/EC1 Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output LCD output LCD output enable 0 1 PDRE read 1 Internal bus PDRE 0 Pin PDRE write Executing bit manipulation instruction DDRE read DDRE DDRE write Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E 95 MB95710M/770M Series (3) Port E registers • Port E register functions Register abbreviation PDRE DDRE Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRE value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRE value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled • Correspondence between registers and pins for port E Correspondence between related register bits and pins Pin name PDRE DDRE 96 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DS702–00019–1v0-E MB95710M/770M Series (4) Port E operations • Operation as an output port • A pin becomes an output port if the bit in the DDRE register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRE register to external pins. • If data is written to the PDRE register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRE register returns the PDRE register value. • To use a pin shared with the LCDC as an output port, set a corresponding function select bit in the LCDC enable register 5 (LCDCE5:SEG[23:22]) or in the LCDC enable register 6 (LCDCE6:SEG[29:24]) to “0” to select the general-purpose I/O port function, and then set the port input control bit in the LCDC enable register 1 (LCDCE1:PICTL) to “1”. • Operation as an input port • A pin becomes an input port if the bit in the DDRE register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDRE register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRE register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRE register, the PDRE register value is returned. • To use a pin shared with the LCDC as an input port, set a corresponding function select bit in the LCDC enable register 5 (LCDCE5:SEG[23:22]) or in the LCDC enable register 6 (LCDCE6:SEG[29:24]) to “0” to select the general-purpose I/O port function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDRE register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDRE register. However, if the read-modify-write (RMW) type of instruction is used to read the PDRE register, the PDRE register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDRE register corresponding to the input pin of a peripheral function to “0”. • Reading the PDRE register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDRE register, the PDRE register value is returned. • Operation as an LCDC segment output pin • Set the bit in the DDRE register corresponding to an LCDC segment output pin to “0”. • To use a pin shared with a general-purpose I/O port as an LCDC segment output pin, set a corresponding function select bit in the LCDC enable register 5 (LCDCE5:SEG[23:22]) or in the LCDC enable register 6 (LCDCE6:SEG[29:24]) to “1” to select the LCDC segment output function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation at reset If the CPU is reset, all bits in the DDRE register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRE register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. DS702–00019–1v0-E 97 MB95710M/770M Series 12. Port F Port F is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port F configuration Port F is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port F data register (PDRF) • Port F direction register (DDRF) (2) Block diagrams of port F • PF0/X0 pin This pin has the following peripheral function: • Main clock input oscillation pin (X0) • PF1/X1 pin This pin has the following peripheral function: • Main clock I/O oscillation pin (X1) • Block diagram of PF0/X0 and PF1/X1 Hysteresis 0 1 PDRF read Internal bus PDRF Pin PDRF write Executing bit manipulation instruction DDRF read DDRF DDRF write 98 Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E MB95710M/770M Series • PF2/RST pin This pin has the following peripheral function: • Reset pin (RST) • Block diagram of PF2/RST Reset input Reset input enable Reset output enable Reset output Hysteresis 0 1 PDRF read PDRF Internal bus Pin 1 0 OD PDRF write Executing bit manipulation instruction DDRF read DDRF DDRF write Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E 99 MB95710M/770M Series (3) Port F registers • Port F register functions Register abbreviation PDRF DDRF Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRF value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRF value is “1”. As output port, outputs “H” level.* 0 Port input enabled 1 Port output enabled *: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. • Correspondence between registers and pins for port F Correspondence between related register bits and pins Pin name PDRF DDRF - - - - - PF2* PF1 PF0 - - - - - bit2 bit1 bit0 *: PF2/RST is the dedicated reset pin on MB95F714M/F716M/F718M. 100 DS702–00019–1v0-E MB95710M/770M Series (4) Port F operations • Operation as an output port • A pin becomes an output port if the bit in the DDRF register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRF register to external pins. • If data is written to the PDRF register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRF register returns the PDRF register value. • Operation as an input port • A pin becomes an input port if the bit in the DDRF register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDRF register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRF register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRF register, the PDRF register value is returned. • Operation at reset If the CPU is reset, all bits in the DDRF register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRF register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. DS702–00019–1v0-E 101 MB95710M/770M Series 13. Port G Port G is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port G configuration Port G is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port G data register (PDRG) • Port G direction register (DDRG) • Port G pull-up register (PULG) (2) Block diagram of port G • PG1/X0A pin This pin has the following peripheral function: • Subclock input oscillation pin (X0A) • PG2/X1A pin This pin has the following peripheral function: • Subclock I/O oscillation pin (X1A) • Block diagram of PG1/X0A and PG2/X1A Hysteresis 0 Pull-up 1 PDRG read PDRG Pin PDRG write Internal bus Executing bit manipulation instruction DDRG read DDRG DDRG write Stop mode, watch mode (SPL = 1) PULG read PULG PULG write 102 DS702–00019–1v0-E MB95710M/770M Series (3) Port G registers • Port G register functions Register abbreviation PDRG DDRG PULG Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRG value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRG value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled • Correspondence between registers and pins for port G Correspondence between related register bits and pins Pin name - - - - - PG2 PG1 - - - - - - bit2 bit1 - PDRG DDRG PULG DS702–00019–1v0-E 103 MB95710M/770M Series (4) Port G operations • Operation as an output port • A pin becomes an output port if the bit in the DDRG register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRG register to external pins. • If data is written to the PDRG register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRG register returns the PDRG register value. • Operation as an input port • A pin becomes an input port if the bit in the DDRG register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDRG register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRG register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRG register, the PDRG register value is returned. • Operation at reset If the CPU is reset, all bits in the DDRG register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRG register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation of the pull-up register Setting the bit in the PULG register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PULG register. 104 DS702–00019–1v0-E MB95710M/770M Series ■ I/O PORTS (MB95770M SERIES) • List of port registers Register name Read/Write Initial value Port 0 data register PDR0 R, RM/W 0b00000000 Port 0 direction register DDR0 R/W 0b00000000 Port 1 data register PDR1 R, RM/W 0b00000000 Port 1 direction register DDR1 R/W 0b00000000 Port 2 data register PDR2 R, RM/W 0b00000000 Port 2 direction register DDR2 R/W 0b00000000 Port 6 data register PDR6 R, RM/W 0b00000000 Port 6 direction register DDR6 R/W 0b00000000 Port 9 data register PDR9 R, RM/W 0b00000000 Port 9 direction register DDR9 R/W 0b00000000 Port A data register PDRA R, RM/W 0b00000000 Port A direction register DDRA R/W 0b00000000 Port B data register PDRB R, RM/W 0b00000000 Port B direction register DDRB R/W 0b00000000 Port C data register PDRC R, RM/W 0b00000000 Port C direction register DDRC R/W 0b00000000 Port E data register PDRE R, RM/W 0b00000000 Port E direction register DDRE R/W 0b00000000 Port F data register PDRF R, RM/W 0b00000000 Port F direction register DDRF R/W 0b00000000 Port G data register PDRG R, RM/W 0b00000000 Port G direction register DDRG R/W 0b00000000 Port 1 pull-up register PUL1 R/W 0b00000000 Port 2 pull-up register PUL2 R/W 0b00000000 Port G pull-up register PULG R/W 0b00000000 A/D input disable register (lower) AIDRL R/W 0b00000000 R/W : Readable/writable (The read value is the same as the write value.) R, RM/W : Readable/writable (The read value is different from the write value. The write value is read by the read-modify-write (RMW) type of instruction.) DS702–00019–1v0-E 105 MB95710M/770M Series 1. Port 0 Port 0 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port 0 configuration Port 0 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 0 data register (PDR0) • Port 0 direction register (DDR0) • A/D input disable register (lower) (AIDRL) (2) Block diagrams of port 0 • P00/INT00/AN00/SEG29/UO2 pin This pin has the following peripheral functions: • External interrupt input pin (INT00) • 8/12-bit A/D converter analog input pin (AN00) • LCDC SEG29 output pin (SEG29) • UART/SIO ch. 2 data output pin (UO2) • P02/INT02/AN02/SEG27/UCK2 pin This pin has the following peripheral functions: • External interrupt input pin (INT02) • 8/12-bit A/D converter analog input pin (AN02) • LCDC SEG27 output pin (SEG27) • UART/SIO ch. 2 clock I/O pin (UCK2) • P03/INT03/AN03/SEG26/UO1 pin This pin has the following peripheral functions: • External interrupt input pin (INT03) • 8/12-bit A/D converter analog input pin (AN03) • LCDC SEG26 output pin (SEG26) • UART/SIO ch. 1 data output pin (UO1) • P05/INT05/AN05/SEG24/UCK1 pin This pin has the following peripheral functions: • External interrupt input pin (INT05) • 8/12-bit A/D converter analog input pin (AN05) • LCDC SEG24 output pin (SEG24) • UART/SIO ch. 1 clock I/O pin (UCK1) • P06/INT06/AN06/SEG23 pin This pin has the following peripheral functions: • External interrupt input pin (INT06) • 8/12-bit A/D converter analog input pin (AN06) • LCDC SEG23 output pin (SEG23) • P07/INT07/AN07/SEG22 pin This pin has the following peripheral functions: • External interrupt input pin (INT07) • 8/12-bit A/D converter analog input pin (AN07) • LCDC SEG22 output pin (SEG22) 106 DS702–00019–1v0-E MB95710M/770M Series • Block diagram of P00/INT00/AN00/SEG29/UO2, P02/INT02/AN02/SEG27/UCK2, P03/INT03/AN03/SEG26/ UO1, P05/INT05/AN05/SEG24/UCK1, P06/INT06/AN06/SEG23 and P07/INT07/AN07/SEG22 LCD output Peripheral function input Peripheral function input enable (INT00, INT02, INT03, INT05, INT06 and INT07) A/D analog input Peripheral function output enable Peripheral function output LCD output enable 0 1 PDR0 read 1 PDR0 0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) AIDRL read AIDRL AIDRL write DS702–00019–1v0-E 107 MB95710M/770M Series • P01/INT01/AN01/SEG28/TO00/UI2 pin This pin has the following peripheral functions: • External interrupt input pin (INT01) • 8/12-bit A/D converter analog input pin (AN01) • LCDC SEG28 output pin (SEG28) • 8/16-bit composite timer ch. 0 output pin (TO00) • UART/SIO ch. 2 data input pin (UI2) • P04/INT04/AN04/SEG25/UI1 pin This pin has the following peripheral functions: • External interrupt input pin (INT04) • 8/12-bit A/D converter analog input pin (AN04) • LCDC SEG25 output pin (SEG25) • UART/SIO ch. 1 data input pin (UI1) • Block diagram of P01/INT01/AN01/SEG28/TO00/UI2 and P04/INT04/AN04/SEG25/UI1 LCD output Peripheral function input A/D analog input Peripheral function input enable (INT01 and INT04) LCD output enable Peripheral function output enable Peripheral function output 0 1 PDR0 read CMOS 1 PDR0 0 Pin PDR0 write Internal bus Executing bit manipulation instruction DDR0 read DDR0 DDR0 write Stop mode, watch mode (SPL = 1) AIDRL read AIDRL AIDRL write 108 DS702–00019–1v0-E MB95710M/770M Series (3) Port 0 registers • Port 0 register functions Register abbreviation PDR0 DDR0 AIDRL Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR0 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR0 value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Analog input enabled 1 Port input enabled • Correspondence between registers and pins for port 0 Correspondence between related register bits and pins Pin name P07 P06 P05 P04 P03 P02 P01 P00 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 PDR0 DDR0 AIDRL DS702–00019–1v0-E 109 MB95710M/770M Series (4) Port 0 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR0 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR0 register to external pins. • If data is written to the PDR0 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR0 register returns the PDR0 register value. • To use a pin shared with the LCDC as an output port, set a corresponding function select bit in the LCDC enable register 5 (LCDCE5:SEG[23:22]) or in the LCDC enable register 6 (LCDCE6:SEG[29:24]) to “0” to select the general-purpose I/O port function, and then set the port input control bit in the LCDC enable register 1 (LCDCE1:PICTL) to “1”. • Operation as an input port • A pin becomes an input port if the bit in the DDR0 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When using an analog input shared pin as an input port, set the corresponding bit in the A/D input disable register (lower) (AIDRL) to “1”. • If data is written to the PDR0 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR0 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. • To use a pin shared with the LCDC as an input port, set a corresponding function select bit in the LCDC enable register 5 (LCDCE5:SEG[23:22]) or in the LCDC enable register 6 (LCDCE6:SEG[29:24]) to “0” to select the general-purpose I/O port function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR0 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR0 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR0 register corresponding to the input pin of a peripheral function to “0”. • When using the analog input shared pin as another peripheral function input pin, configure it as an input port, which is the same as the operation as an input port. • Reading the PDR0 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR0 register, the PDR0 register value is returned. • Operation as an LCDC segment output pin • Set the bit in the DDR0 register corresponding to an LCDC segment output pin to “0”. • To use a pin shared with a general-purpose I/O port as an LCDC segment output pin, set a corresponding function select bit in the LCDC enable register 5 (LCDCE5:SEG[23:22]) or in the LCDC enable register 6 (LCDCE6:SEG[29:24]) to “1” to select the LCDC segment output function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation at reset If the CPU is reset, all bits in the DDR0 register are initialized to “0” and port input is enabled. As for a pin shared with analog input, its port input is disabled because the AIDRL register is initialized to “0”. 110 DS702–00019–1v0-E MB95710M/770M Series • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR0 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input is enabled for the external interrupt (INT00 to INT07), the input is enabled and not blocked. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as an analog input pin • Set the bit in the DDR0 register bit corresponding to the analog input pin to “0” and the bit corresponding to that pin in the AIDRL register to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • Operation as an external interrupt input pin • Set the bit in the DDR0 register corresponding to the external interrupt input pin to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • The pin value is always input to the external interrupt circuit. When using a pin for a function other than the interrupt, disable the external interrupt function corresponding to that pin. DS702–00019–1v0-E 111 MB95710M/770M Series 2. Port 1 Port 1 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port 1 configuration Port 1 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 1 data register (PDR1) • Port 1 direction register (DDR1) • Port 1 pull-up register (PUL1) (2) Block diagrams of port 1 • P10/UI0/TO0 pin This pin has the following peripheral functions: • UART/SIO ch. 0 data input pin (UI0) • 16-bit reload timer ch. 0 output pin (TO0) • Block diagram of P10/UI0/TO0 Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output CMOS Pull-up 0 1 PDR1 read 1 PDR1 0 Pin PDR1 write Internal bus Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) PUL1 read PUL1 PUL1 write 112 DS702–00019–1v0-E MB95710M/770M Series • P12/DBG pin This pin has the following peripheral function: • DBG input pin (DBG) • Block diagram of P12/DBG Hysteresis 0 1 PDR1 read Internal bus PDR1 Pin OD PDR1 write Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E 113 MB95710M/770M Series • P11/UO0 pin This pin has the following peripheral function: • UART/SIO ch. 0 data output pin (UO0) • P13/ADTG/TO01 pin This pin has the following peripheral functions: • 8/12-bit A/D converter trigger input pin (ADTG) • 8/16-bit composite timer ch. 0 output pin (TO01) • P14/UCK0/EC0/TI0 pin This pin has the following peripheral functions: • UART/SIO ch. 0 clock I/O pin (UCK0) • 8/16-bit composite timer ch. 0 clock input pin (EC0) • 16-bit reload timer ch. 0 input pin (TI0) • P17/CMP0_O pin This pin has the following peripheral function: • Comparator ch. 0 digital output pin (CMP0_O) • Block diagram of P11/UO0, P13/ADTG/TO01, P14/UCK0/EC0/TI0 and P17/CMP0_O Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output Pull-up 0 1 PDR1 read 1 PDR1 0 Pin PDR1 write Internal bus Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) PUL1 read PUL1 PUL1 write 114 DS702–00019–1v0-E MB95710M/770M Series • P15/SEG31/PPG11 pin This pin has the following peripheral functions: • LCDC SEG31 output pin (SEG31) • 8/16-bit PPG ch. 1 output pin (PPG11) • P16/SEG30/PPG10 pin This pin has the following peripheral functions: • LCDC SEG30 output pin (SEG30) • 8/16-bit PPG ch. 1 output pin (PPG10) • Block diagram of P15/SEG31/PPG11 and P16/SEG30/PPG10 LCD output Peripheral function output enable Peripheral function output LCD output enable 0 1 PDR1 read 1 Internal bus PDR1 0 Pin PDR1 write Executing bit manipulation instruction DDR1 read DDR1 DDR1 write Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E 115 MB95710M/770M Series (3) Port 1 registers • Port 1 register functions Register abbreviation PDR1 DDR1 PUL1 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR1 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR1 value is “1”. As output port, outputs “H” level.* 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled *: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. • Correspondence between registers and pins for port 1 Correspondence between related register bits and pins Pin name P17 PDR1 DDR1 PUL1 116 bit7 P16 P15 bit6 bit5 - - P14 P13 bit4 bit3 P12 bit2 P11 P10 bit1 bit0 - DS702–00019–1v0-E MB95710M/770M Series (4) Port 1 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR1 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR1 register to external pins. • If data is written to the PDR1 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR1 register returns the PDR1 register value. • To use a pin shared with the LCDC as an output port, set a corresponding function select bit in the LCDC enable register 6 (LCDCE6:SEG[31:30]) to “0” to select the general-purpose I/O port function, and then set the port input control bit in the LCDC enable register 1 (LCDCE1:PICTL) to “1”. • Operation as an input port • A pin becomes an input port if the bit in the DDR1 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDR1 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR1 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. • To use a pin shared with the LCDC as an input port, set a corresponding function select bit in the LCDC enable register 6 (LCDCE6:SEG[31:30]) to “0” to select the general-purpose I/O port function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR1 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR1 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR1 register corresponding to the input pin of a peripheral function to “0”. • Reading the PDR1 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR1 register, the PDR1 register value is returned. • Operation as an LCDC segment output pin • Set the bit in the DDR1 register corresponding to an LCDC segment output pin to “0”. • To use a pin shared with a general-purpose I/O port as an LCDC segment output pin, set a corresponding function select bit in the LCDC enable register 6 (LCDCE6:SEG[31:30]) to “1” to select the LCDC segment output function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation at reset If the CPU is reset, all bits in the DDR1 register are initialized to “0” and port input is enabled. DS702–00019–1v0-E 117 MB95710M/770M Series • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR1 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. However, if the interrupt input of P10/UI0/TO0 and P14/UCK0/EC0/TI0 is enabled by the external interrupt control register ch. 0 (EIC00) of the external interrupt circuit and the interrupt pin selection circuit control register (WICR) of the interrupt pin selection circuit, the input is enabled and is not blocked. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation of the pull-up register Setting the bit in the PUL1 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL1 register. 118 DS702–00019–1v0-E MB95710M/770M Series 3. Port 2 Port 2 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port 2 configuration Port 2 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 2 data register (PDR2) • Port 2 direction register (DDR2) • Port 2 pull-up register (PUL2) (2) Block diagrams of port 2 • P20/PPG00/CMP0_N pin This pin has the following peripheral functions: • 8/16-bit PPG ch. 0 output pin (PPG00) • Comparator ch. 0 inverting analog input (negative input) pin (CMP0_N) • P21/PPG01/CMP0_P pin This pin has the following peripheral functions: • 8/16-bit PPG ch. 0 output pin (PPG01) • Comparator ch. 0 non-inverting analog input (positive input) pin (CMP0_P) • Block diagram of P20/PPG00/CMP0_N and P21/PPG01/CMP0_P Analog input Peripheral function output enable Peripheral function output Analog input enable Pull-up 0 1 PDR2 read 1 PDR2 0 Pin PDR2 write Internal bus Executing bit manipulation instruction DDR2 read DDR2 DDR2 write Stop mode, watch mode (SPL = 1) PUL2 read PUL2 PUL2 write DS702–00019–1v0-E 119 MB95710M/770M Series • P22/SCL pin This pin has the following peripheral function: • I2C bus interface ch. 0 clock I/O pin (SCL) • P23/SDA pin This pin has the following peripheral function: • I2C bus interface ch. 0 data I/O pin (SDA) • Block diagram of P22/SCL and P23/SDA Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output CMOS 0 1 PDR2 read PDR2 Internal bus Pin 1 0 OD PDR2 write Executing bit manipulation instruction DDR2 read DDR2 DDR2 write 120 Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E MB95710M/770M Series (3) Port 2 registers • Port 2 register functions Register abbreviation PDR2 DDR2 PUL2 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR2 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR2 value is “1”. As output port, outputs “H” level.* 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled *: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. • Correspondence between registers and pins for port 2 Correspondence between related register bits and pins Pin name - - - - - - - - PDR2 DDR2 PUL2 DS702–00019–1v0-E P23 P22 bit3 bit2 - - P21 P20 bit1 bit0 121 MB95710M/770M Series (4) Port 2 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR2 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR2 register to external pins. • If data is written to the PDR2 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR2 register returns the PDR2 register value. • Operation as an input port • A pin becomes an input port if the bit in the DDR2 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDR2 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR2 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR2 register, the PDR2 register value is returned. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDR2 register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDR2 register. However, if the read-modify-write (RMW) type of instruction is used to read the PDR2 register, the PDR2 register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDR2 register corresponding to the input pin of a peripheral function to “0”. • Reading the PDR2 register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDR2 register, the PDR2 register value is returned. • Operation at reset If the CPU is reset, all bits in the DDR2 register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR2 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation of the pull-up register Setting the bit in the PUL2 register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PUL2 register. • Operation as a comparator input pin • Regardless of the value of the PDR2 register and that of the DDR2 register, if the comparator analog input enable bit in the comparator control register ch. 0 (CMR0:VCID) is set to “0”, the comparator input function is enabled. • To disable the comparator input function, set the VCID bit to “1”. • For details of the comparator, refer to “CHAPTER 29 COMPARATOR” in “New 8FX MB95710M/770M Series Hardware Manual”. 122 DS702–00019–1v0-E MB95710M/770M Series 4. Port 6 Port 6 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port 6 configuration Port 6 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 6 data register (PDR6) • Port 6 direction register (DDR6) DS702–00019–1v0-E 123 MB95710M/770M Series (2) Block diagrams of port 6 • P60/SEG06 pin This pin has the following peripheral function: • LCDC SEG06 output pin (SEG06) • P61/SEG07 pin This pin has the following peripheral function: • LCDC SEG07 output pin (SEG07) • P62/SEG08 pin This pin has the following peripheral function: • LCDC SEG08 output pin (SEG08) • P63/SEG09 pin This pin has the following peripheral function: • LCDC SEG09 output pin (SEG09) • P64/SEG10 pin This pin has the following peripheral function: • LCDC SEG10 output pin (SEG10) • P65/SEG11 pin This pin has the following peripheral function: • LCDC SEG11 output pin (SEG11) • P66/SEG12 pin This pin has the following peripheral function: • LCDC SEG12 output pin (SEG12) • P67/SEG13 pin This pin has the following peripheral function: • LCDC SEG13 output pin (SEG13) • Block diagram of P60/SEG06, P61/SEG07, P62/SEG08, P63/SEG09, P64/SEG10, P65/SEG11, P66/SEG12 and P67/SEG13 LCD output LCD output enable 0 1 PDR6 read Internal bus PDR6 Pin PDR6 write Executing bit manipulation instruction DDR6 read DDR6 DDR6 write 124 Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E MB95710M/770M Series (3) Port 6 registers • Port 6 register functions Register abbreviation PDR6 DDR6 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR6 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR6 value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled • Correspondence between registers and pins for port 6 Correspondence between related register bits and pins Pin name PDR6 DDR6 P67 P66 P65 P64 P63 P62 P61 P60 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DS702–00019–1v0-E 125 MB95710M/770M Series (4) Port 6 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR6 register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDR6 register to external pins. • If data is written to the PDR6 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR6 register returns the PDR6 register value. • To use a pin shared with the LCDC as an output port, set a corresponding function select bit in the LCDC enable register 3 (LCDCE3:SEG[07:06]) or in the LCDC enable register 4 (LCDCE4:SEG[13:08]) to “0” to select the general-purpose I/O port function, and then set the port input control bit in the LCDC enable register 1 (LCDCE1:PICTL) to “1”. • Operation as an input port • A pin becomes an input port if the bit in the DDR6 register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDR6 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR6 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR6 register, the PDR6 register value is returned. • To use a pin shared with the LCDC as an input port, set a corresponding function select bit in the LCDC enable register 3 (LCDCE3:SEG[07:06]) or in the LCDC enable register 4 (LCDCE4:SEG[13:08]) to “0” to select the general-purpose I/O port function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation as an LCDC segment output pin • Set the bit in the DDR6 register corresponding to an LCDC segment output pin to “0”. • To use a pin shared with a general-purpose I/O port as an LCDC segment output pin, set a corresponding function select bit in the LCDC enable register 3 (LCDCE3:SEG[07:06]) or in the LCDC enable register 4 (LCDCE4:SEG[13:08]) to “1” to select the LCDC segment output function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation at reset If the CPU is reset, all bits in the DDR6 register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR6 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. 126 DS702–00019–1v0-E MB95710M/770M Series 5. Port 9 Port 9 is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port 9 configuration Port 9 is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port 9 data register (PDR9) • Port 9 direction register (DDR9) (2) Block diagrams of port 9 • P90/V4 pin This pin has the following peripheral function: • LCD drive power supply pin (V4) • P91/V3 pin This pin has the following peripheral function: • LCD drive power supply pin (V3) • P92/V2 pin This pin has the following peripheral function: • LCD drive power supply pin (V2) • P93/V1 pin This pin has the following peripheral function: • LCD drive power supply pin (V1) • Block diagram of P90/V4, P91/V3, P92/V2 and P93/V1 LCD power supply LCD power supply enable 0 1 PDR9 read Internal bus PDR9 Pin PDR9 write Executing bit manipulation instruction DDR9 read DDR9 DDR9 write Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E 127 MB95710M/770M Series (3) Port 9 registers • Port 9 register functions Register abbreviation PDR9 DDR9 Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDR9 value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDR9 value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled • Correspondence between registers and pins for port 9 Correspondence between related register bits and pins Pin name PDR9 DDR9 128 - - - - P93 P92 P91 P90 - - - - bit3 bit2 bit1 bit0 DS702–00019–1v0-E MB95710M/770M Series (4) Port 9 operations • Operation as an output port • A pin becomes an output port if the bit in the DDR9 register corresponding to that pin is set to “1”. • When a pin is used as an output port, it outputs the value of the PDR9 register to external pins. • If data is written to the PDR9 register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDR9 register returns the PDR9 register value. • To use a pin shared with the LCDC as an output port, set the bit corresponding to that pin in the VE[4:1] bits in the LCDC enable register 1 (LCDCE1) to “0” to select the general-purpose I/O port function. • Operation as an input port • A pin becomes an input port if the bit in the DDR9 register corresponding to that pin is set to “0”. • If data is written to the PDR9 register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDR9 register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDR9 register, the PDR9 register value is returned. • To use a pin shared with the LCDC as an input port, set the bit corresponding to that pin in the VE[4:1] bits in the LCDCE1 register to “0” to select the general-purpose I/O port function. • Operation at reset If the CPU is reset, all bits in the DDR9 register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDR9 register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation as an LCD drive power supply pin • Set the bit in the DDR9 register corresponding to an LCD drive power supply pin to “0”. • To use a pin shared with a general-purpose I/O port as an LCD drive power supply pin, set the bit corresponding to that pin in the VE[4:1] bits in the LCDCE1 register to “1” to select the LCD drive power supply function. DS702–00019–1v0-E 129 MB95710M/770M Series 6. Port A Port A is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port A configuration Port A is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port A data register (PDRA) • Port A direction register (DDRA) 130 DS702–00019–1v0-E MB95710M/770M Series (2) Block diagrams of port A • PA0/COM0 pin This pin has the following peripheral function: • LCDC COM0 output pin (COM0) • PA1/COM1 pin This pin has the following peripheral function: • LCDC COM1 output pin (COM1) • PA2/COM2 pin This pin has the following peripheral function: • LCDC COM2 output pin (COM2) • PA3/COM3 pin This pin has the following peripheral function: • LCDC COM3 output pin (COM3) • PA4/COM4 pin This pin has the following peripheral function: • LCDC COM4 output pin (COM4) • PA5/COM5 pin This pin has the following peripheral function: • LCDC COM5 output pin (COM5) • PA6/COM6 pin This pin has the following peripheral function: • LCDC COM6 output pin (COM6) • PA7/COM7 pin This pin has the following peripheral function: • LCDC COM7 output pin (COM7) • Block diagram of PA0/COM0, PA1/COM1, PA2/COM2, PA3/COM3, PA4/COM4, PA5/COM5, PA6/COM6 and PA7/COM7 LCD output LCD output enable 0 1 PDRA read Internal bus PDRA Pin PDRA write Executing bit manipulation instruction DDRA read DDRA DDRA write Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E 131 MB95710M/770M Series (3) Port A registers • Port A register functions Register abbreviation PDRA DDRA Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRA value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRA value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled • Correspondence between registers and pins for port A Correspondence between related register bits and pins Pin name PDRA DDRA 132 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DS702–00019–1v0-E MB95710M/770M Series (4) Port A operations • Operation as an output port • A pin becomes an output port if the bit in the DDRA register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRA register to external pins. • If data is written to the PDRA register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRA register returns the PDRA register value. • To use a pin shared with the LCDC as an output port, set a corresponding function select bit in the LCDC enable register 2 (LCDCE2:COM[7:0]) to “0” to select the general-purpose I/O port function, and then set the port input control bit in the LCDC enable register 1 (LCDCE1:PICTL) to “1”. • Operation as an input port • A pin becomes an input port if the bit in the DDRA register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDRA register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRA register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRA register, the PDRA register value is returned. • To use a pin shared with the LCDC as an input port, set a corresponding function select bit in the LCDC enable register 2 (LCDCE2:COM[7:0]) to “0” to select the general-purpose I/O port function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation as an LCDC common output pin • Set the bit in the DDRA register corresponding to an LCDC common output pin to “0”. • To use a pin shared with a general-purpose I/O port as an LCDC common output pin, set a corresponding function select bit in the LCDC enable register 2 (LCDCE2:COM[7:0]) to “1” to select the LCDC common output function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation at reset If the CPU is reset, all bits in the DDRA register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRA register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. DS702–00019–1v0-E 133 MB95710M/770M Series 7. Port B Port B is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port B configuration Port B is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port B data register (PDRB) • Port B direction register (DDRB) (2) Block diagrams of port B • PB0/SEG00 pin This pin has the following peripheral function: • LCDC SEG00 output pin (SEG00) • PB1/SEG01 pin This pin has the following peripheral function: • LCDC SEG01 output pin (SEG01) • Block diagram of PB0/SEG00 and PB1/SEG01 LCD output LCD output enable 0 1 PDRB read Internal bus PDRB Pin PDRB write Executing bit manipulation instruction DDRB read DDRB DDRB write 134 Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E MB95710M/770M Series (3) Port B registers • Port B register functions Register abbreviation PDRB DDRB Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRB value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRB value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled • Correspondence between registers and pins for port B Correspondence between related register bits and pins Pin name PDRB DDRB - - - - - - PB1 PB0 - - - - - - bit1 bit0 DS702–00019–1v0-E 135 MB95710M/770M Series (4) Port B operations • Operation as an output port • A pin becomes an output port if the bit in the DDRB register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRB register to external pins. • If data is written to the PDRB register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRB register returns the PDRB register value. • To use a pin shared with the LCDC as an output port, set a corresponding function select bit in the LCDC enable register 3 (LCDCE3:SEG[01:00]) to “0” to select the general-purpose I/O port function, and then set the port input control bit in the LCDC enable register 1 (LCDCE1:PICTL) to “1”. • Operation as an input port • A pin becomes an input port if the bit in the DDRB register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDRB register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRB register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRB register, the PDRB register value is returned. • To use a pin shared with the LCDC as an input port, set a corresponding function select bit in the LCDC enable register 3 (LCDCE3:SEG[01:00]) to “0” to select the general-purpose I/O port function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation as an LCDC segment output pin • Set the bit in the DDRB register corresponding to an LCDC segment output pin to “0”. • To use a pin shared with a general-purpose I/O port as an LCDC segment output pin, set a corresponding function select bit in the LCDC enable register 3 (LCDCE3:SEG[01:00]) to “1” to select the LCDC segment output function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation at reset If the CPU is reset, all bits in the DDRB register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRB register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. 136 DS702–00019–1v0-E MB95710M/770M Series 8. Port C Port C is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port C configuration Port C is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port C data register (PDRC) • Port C direction register (DDRC) (2) Block diagrams of port C • PC0/SEG02 pin This pin has the following peripheral function: • LCDC SEG02 output pin (SEG02) • PC1/SEG03 pin This pin has the following peripheral function: • LCDC SEG03 output pin (SEG03) • PC2/SEG04 pin This pin has the following peripheral function: • LCDC SEG04 output pin (SEG04) • PC3/SEG05 pin This pin has the following peripheral function: • LCDC SEG05 output pin (SEG05) • Block diagram of PC0/SEG02, PC1/SEG03, PC2/SEG04 and PC3/SEG05 LCD output LCD output enable 0 1 PDRC read Internal bus PDRC Pin PDRC write Executing bit manipulation instruction DDRC read DDRC DDRC write Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E 137 MB95710M/770M Series (3) Port C registers • Port C register functions Register abbreviation PDRC DDRC Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRC value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRC value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled • Correspondence between registers and pins for port C Correspondence between related register bits and pins Pin name PDRC DDRC 138 - - - - PC3 PC2 PC1 PC0 - - - - bit3 bit2 bit1 bit0 DS702–00019–1v0-E MB95710M/770M Series (4) Port C operations • Operation as an output port • A pin becomes an output port if the bit in the DDRC register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRC register to external pins. • If data is written to the PDRC register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRC register returns the PDRC register value. • To use a pin shared with the LCDC as an output port, set a corresponding function select bit in the LCDC enable register 3 (LCDCE3:SEG[05:02]) to “0” to select the general-purpose I/O port function, and then set the port input control bit in the LCDC enable register 1 (LCDCE1:PICTL) to “1”. • Operation as an input port • A pin becomes an input port if the bit in the DDRC register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDRC register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRC register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRC register, the PDRC register value is returned. • To use a pin shared with the LCDC as an input port, set a corresponding function select bit in the LCDC enable register 3 (LCDCE3:SEG[05:02]) to “0” to select the general-purpose I/O port function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation as an LCDC segment output pin • Set the bit in the DDRC register corresponding to an LCDC segment output pin to “0”. • To use a pin shared with a general-purpose I/O port as an LCDC segment output pin, set a corresponding function select bit in the LCDC enable register 3 (LCDCE3:SEG[05:02]) to “1” to select the LCDC segment output function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation at reset If the CPU is reset, all bits in the DDRC register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRC register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. DS702–00019–1v0-E 139 MB95710M/770M Series 9. Port E Port E is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port E configuration Port E is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port E data register (PDRE) • Port E direction register (DDRE) (2) Block diagrams of port E • PE0/SEG14 pin This pin has the following peripheral function: • LCDC SEG14 output pin (SEG14) • PE1/SEG15 pin This pin has the following peripheral function: • LCDC SEG15 output pin (SEG15) • PE2/SEG16 pin This pin has the following peripheral function: • LCDC SEG16 output pin (SEG16) • PE3/SEG17 pin This pin has the following peripheral function: • LCDC SEG17 output pin (SEG17) • PE4/SEG18 pin This pin has the following peripheral function: • LCDC SEG18 output pin (SEG18) • Block diagram of PE0/SEG14, PE1/SEG15, PE2/SEG16, PE3/SEG17 and PE4/SEG18 LCD output LCD output enable 0 1 PDRE read Internal bus PDRE Pin PDRE write Executing bit manipulation instruction DDRE read DDRE DDRE write 140 Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E MB95710M/770M Series • PE5/SEG19/TO11 pin This pin has the following peripheral functions: • LCDC SEG19 output pin (SEG19) • 8/16-bit composite timer ch. 1 output pin (TO11) • PE6/SEG20/TO10 pin This pin has the following peripheral functions: • LCDC SEG20 output pin (SEG20) • 8/16-bit composite timer ch. 1 output pin (TO10) • PE7/SEG21/EC1 pin This pin has the following peripheral functions: • LCDC SEG21 output pin (SEG21) • 8/16-bit composite timer ch. 1 clock input pin (EC1) • Block diagram of PE5/SEG19/TO11, PE6/SEG20/TO10 and PE7/SEG21/EC1 Peripheral function input Peripheral function input enable Peripheral function output enable Peripheral function output LCD output LCD output enable 0 1 PDRE read 1 Internal bus PDRE 0 Pin PDRE write Executing bit manipulation instruction DDRE read DDRE DDRE write Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E 141 MB95710M/770M Series (3) Port E registers • Port E register functions Register abbreviation PDRE DDRE Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRE value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRE value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled • Correspondence between registers and pins for port E Correspondence between related register bits and pins Pin name PDRE DDRE 142 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DS702–00019–1v0-E MB95710M/770M Series (4) Port E operations • Operation as an output port • A pin becomes an output port if the bit in the DDRE register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRE register to external pins. • If data is written to the PDRE register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRE register returns the PDRE register value. • To use a pin shared with the LCDC as an output port, set a corresponding function select bit in the LCDC enable register 4 (LCDCE4:SEG[15:14]) or in the LCDC enable register 5 (LCDCE5:SEG[21:16]) to “0” to select the general-purpose I/O port function, and then set the port input control bit in the LCDC enable register 1 (LCDCE1:PICTL) to “1”. • Operation as an input port • A pin becomes an input port if the bit in the DDRE register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDRE register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRE register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRE register, the PDRE register value is returned. • To use a pin shared with the LCDC as an input port, set a corresponding function select bit in the LCDC enable register 4 (LCDCE4:SEG[15:14]) or in the LCDC enable register 5 (LCDCE5:SEG[21:16]) to “0” to select the general-purpose I/O port function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation as a peripheral function output pin • A pin becomes a peripheral function output pin if the peripheral output function is enabled by setting the output enable bit of a peripheral function corresponding to that pin. • The pin value can be read from the PDRE register even if the peripheral function output is enabled. Therefore, the output value of a peripheral function can be read by the read operation on the PDRE register. However, if the read-modify-write (RMW) type of instruction is used to read the PDRE register, the PDRE register value is returned. • Operation as a peripheral function input pin • To set a pin as an input port, set the bit in the DDRE register corresponding to the input pin of a peripheral function to “0”. • Reading the PDRE register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. However, if the read-modify-write (RMW) type of instruction is used to read the PDRE register, the PDRE register value is returned. • Operation as an LCDC segment output pin • Set the bit in the DDRE register corresponding to an LCDC segment output pin to “0”. • To use a pin shared with a general-purpose I/O port as an LCDC segment output pin, set a corresponding function select bit in the LCDC enable register 4 (LCDCE4:SEG[15:14]) or in the LCDC enable register 5 (LCDCE5:SEG[21:16]) to “1” to select the LCDC segment output function, and then set the PICTL bit in the LCDCE1 register to “1”. • Operation at reset If the CPU is reset, all bits in the DDRE register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRE register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. DS702–00019–1v0-E 143 MB95710M/770M Series 10. Port F Port F is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port F configuration Port F is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port F data register (PDRF) • Port F direction register (DDRF) (2) Block diagrams of port F • PF0/X0 pin This pin has the following peripheral function: • Main clock input oscillation pin (X0) • PF1/X1 pin This pin has the following peripheral function: • Main clock I/O oscillation pin (X1) • Block diagram of PF0/X0 and PF1/X1 Hysteresis 0 1 PDRF read Internal bus PDRF Pin PDRF write Executing bit manipulation instruction DDRF read DDRF DDRF write 144 Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E MB95710M/770M Series • PF2/RST pin This pin has the following peripheral function: • Reset pin (RST) • Block diagram of PF2/RST Reset input Reset input enable Reset output enable Reset output Hysteresis 0 1 PDRF read PDRF Internal bus Pin 1 0 OD PDRF write Executing bit manipulation instruction DDRF read DDRF DDRF write Stop mode, watch mode (SPL = 1) DS702–00019–1v0-E 145 MB95710M/770M Series (3) Port F registers • Port F register functions Register abbreviation PDRF DDRF Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRF value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRF value is “1”. As output port, outputs “H” level.* 0 Port input enabled 1 Port output enabled *: If the pin is an N-ch open drain pin, the pin state becomes Hi-Z. • Correspondence between registers and pins for port F Correspondence between related register bits and pins Pin name PDRF DDRF - - - - - PF2* PF1 PF0 - - - - - bit2 bit1 bit0 *: PF2/RST is the dedicated reset pin on MB95F774M/F776M/F778M. 146 DS702–00019–1v0-E MB95710M/770M Series (4) Port F operations • Operation as an output port • A pin becomes an output port if the bit in the DDRF register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRF register to external pins. • If data is written to the PDRF register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRF register returns the PDRF register value. • Operation as an input port • A pin becomes an input port if the bit in the DDRF register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDRF register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRF register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRF register, the PDRF register value is returned. • Operation at reset If the CPU is reset, all bits in the DDRF register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRF register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. DS702–00019–1v0-E 147 MB95710M/770M Series 11. Port G Port G is a general-purpose I/O port. This section focuses on its functions as a general-purpose I/O port. For details of peripheral functions, refer to their respective chapters in “New 8FX MB95710M/770M Series Hardware Manual”. (1) Port G configuration Port G is made up of the following elements. • General-purpose I/O pins/peripheral function I/O pins • Port G data register (PDRG) • Port G direction register (DDRG) • Port G pull-up register (PULG) (2) Block diagram of port G • PG1/X0A pin This pin has the following peripheral function: • Subclock input oscillation pin (X0A) • PG2/X1A pin This pin has the following peripheral function: • Subclock I/O oscillation pin (X1A) • Block diagram of PG1/X0A and PG2/X1A Hysteresis 0 Pull-up 1 PDRG read PDRG Pin PDRG write Internal bus Executing bit manipulation instruction DDRG read DDRG DDRG write Stop mode, watch mode (SPL = 1) PULG read PULG PULG write 148 DS702–00019–1v0-E MB95710M/770M Series (3) Port G registers • Port G register functions Register abbreviation PDRG DDRG PULG Data Read Read by read-modify-write (RMW) instruction Write 0 Pin state is “L” level. PDRG value is “0”. As output port, outputs “L” level. 1 Pin state is “H” level. PDRG value is “1”. As output port, outputs “H” level. 0 Port input enabled 1 Port output enabled 0 Pull-up disabled 1 Pull-up enabled • Correspondence between registers and pins for port G Correspondence between related register bits and pins Pin name - - - - - PG2 PG1 - - - - - - bit2 bit1 - PDRG DDRG PULG DS702–00019–1v0-E 149 MB95710M/770M Series (4) Port G operations • Operation as an output port • A pin becomes an output port if the bit in the DDRG register corresponding to that pin is set to “1”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • When a pin is used as an output port, it outputs the value of the PDRG register to external pins. • If data is written to the PDRG register, the value is stored in the output latch and is output to the pin set as an output port as it is. • Reading the PDRG register returns the PDRG register value. • Operation as an input port • A pin becomes an input port if the bit in the DDRG register corresponding to that pin is set to “0”. • For a pin shared with other peripheral functions, disable the output of such peripheral functions. • If data is written to the PDRG register, the value is stored in the output latch but is not output to the pin set as an input port. • Reading the PDRG register returns the pin value. However, if the read-modify-write (RMW) type of instruction is used to read the PDRG register, the PDRG register value is returned. • Operation at reset If the CPU is reset, all bits in the DDRG register are initialized to “0” and port input is enabled. • Operation in stop mode and watch mode • If the pin state setting bit in the standby control register (STBC:SPL) is set to “1” and the device transits to stop mode or watch mode, the pin is compulsorily made to enter the high impedance state regardless of the DDRG register value. The input of that pin is locked to “L” level and blocked in order to prevent leaks due to input open. • If the pin state setting bit is “0”, the state of the port I/O or that of the peripheral function I/O remains unchanged and the output level is maintained. • Operation of the pull-up register Setting the bit in the PULG register to “1” makes the pull-up resistor be internally connected to the pin. When the pin output is “L” level, the pull-up resistor is disconnected regardless of the value of the PULG register. 150 DS702–00019–1v0-E MB95710M/770M Series ■ INTERRUPT SOURCE TABLE Interrupt source External interrupt ch. 0 Interrupt request number Vector table address Upper Lower Interrupt level setting register Register Bit IRQ00 0xFFFA 0xFFFB ILR0 L00 [1:0] IRQ01 0xFFF8 0xFFF9 ILR0 L01 [1:0] IRQ02 0xFFF6 0xFFF7 ILR0 L02 [1:0] IRQ03 0xFFF4 0xFFF5 ILR0 L03 [1:0] IRQ04 0xFFF2 0xFFF3 ILR1 L04 [1:0] 8/16-bit composite timer ch. 0 (lower) IRQ05 0xFFF0 0xFFF1 ILR1 L05 [1:0] 8/16-bit composite timer ch. 0 (upper) IRQ06 0xFFEE 0xFFEF ILR1 L06 [1:0] UART/SIO ch. 2 IRQ07 0xFFEC 0xFFED ILR1 L07 [1:0] LCDC IRQ08 0xFFEA 0xFFEB ILR2 L08 [1:0] IRQ09 0xFFE8 0xFFE9 ILR2 L09 [1:0] 8/16-bit PPG ch. 1 (upper) IRQ10 0xFFE6 0xFFE7 ILR2 L10 [1:0] 16-bit reload timer ch. 0 IRQ11 0xFFE4 0xFFE5 ILR2 L11 [1:0] 8/16-bit PPG ch. 0 (upper) IRQ12 0xFFE2 0xFFE3 ILR3 L12 [1:0] 8/16-bit PPG ch. 0 (lower) IRQ13 0xFFE0 0xFFE1 ILR3 L13 [1:0] 8/16-bit composite timer ch. 1 (upper) IRQ14 0xFFDE 0xFFDF ILR3 L14 [1:0] Comparator ch. 0 IRQ15 0xFFDC 0xFFDD ILR3 L15 [1:0] IRQ16 0xFFDA 0xFFDB ILR4 L16 [1:0] IRQ17 0xFFD8 0xFFD9 ILR4 L17 [1:0] 8/12-bit A/D converter IRQ18 0xFFD6 0xFFD7 ILR4 L18 [1:0] Time-base timer IRQ19 0xFFD4 0xFFD5 ILR4 L19 [1:0] IRQ20 0xFFD2 0xFFD3 ILR5 L20 [1:0] IRQ21 0xFFD0 0xFFD1 ILR5 L21 [1:0] 8/16-bit composite timer ch. 1 (lower) IRQ22 0xFFCE 0xFFCF ILR5 L22 [1:0] Flash memory IRQ23 0xFFCC 0xFFCD ILR5 L23 [1:0] External interrupt ch. 4 External interrupt ch. 1 External interrupt ch. 5 External interrupt ch. 2 External interrupt ch. 6 External interrupt ch. 3 External interrupt ch. 7 UART/SIO ch. 0 Low-voltage detection circuit 8/16-bit PPG ch. 1 (lower) UART/SIO ch. 1 2 I C bus interface ch. 0 — Watch prescaler Watch counter — DS702–00019–1v0-E Priority order of interrupt sources of the same level (occurring simultaneously) High Low 151 MB95710M/770M Series ■ PIN STATES IN EACH MODE Pin name Normal operation Sleep mode Oscillation input Oscillation input PF0/X0 I/O port*2 I/O port*2 Oscillation input Oscillation input PF1/X1 PF2/RST I/O port*2 I/O port*2 Reset input Reset input I/O port*2 I/O port*2 Oscillation input Oscillation input PG1/X0A I/O port*2 I/O port*2 Oscillation input Oscillation input PG2/X1A I/O port*2 I/O port*2 Stop mode Watch mode SPL=0 SPL=1 SPL=0 SPL=1 Hi-Z Hi-Z Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*2, *3 blocked*2, *3 Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*2, *3 2, 3 blocked* * Reset input Reset input - Previous state - Hi-Z kept - Input - Input blocked*2, *3 2, 3 blocked* * Hi-Z Hi-Z - Previous state - Hi-Z*7 kept - Input - Input blocked*2, *3 blocked*2, *3 Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*2, *3 blocked*2, *3 Hi-Z Hi-Z - Previous state - Hi-Z kept - Input - Input blocked*2, *3 2, 3 blocked* * Reset input Reset input - Previous state - Hi-Z kept - Input - Input blocked*2, *3 2, 3 blocked* * Hi-Z Hi-Z - Previous state - Hi-Z*7 kept - Input - Input blocked*2, *3 blocked*2, *3 Hi-Z Hi-Z On reset Oscillation input*1 - Hi-Z - Input enabled*4 (However, it does not function.) Oscillation input*1 - Hi-Z - Input enabled*4 (However, it does not function.) Reset input*5 - Hi-Z - Input enabled*4 (However, it does not function.) Oscillation input*6 - Hi-Z - Input enabled*4 (However, it does not function.) Oscillation input*6 - Previous state - Hi-Z*7 kept - Input - Input blocked*2, *3 2, 3 blocked* * - Previous state - Hi-Z*7 kept - Input - Input blocked*2, *3 2, 3 blocked* * - Hi-Z - Input enabled*4 (However, it does not function.) - Previous state - Hi-Z kept - Input - Input blocked*3, *10 blocked*3, *10 - Previous state - Hi-Z kept - Input - Input blocked*3, *10 blocked*3, *10 - Hi-Z - Input blocked*3 P00/INT00/ AN00/ SEG29*8/ UO2 P01/INT01/ AN01/ SEG28*8/ SEG36*8/ TO00*9/UI2 I/O port/ peripheral P02/INT02/ function I/O/ AN02/ analog input SEG27*8/ SEG35*8/ UCK2 I/O port/ peripheral function I/O/ analog input P03/INT03/ AN03/ SEG26*8/ SEG34*8/ UO1 (Continued) 152 DS702–00019–1v0-E MB95710M/770M Series Pin name Normal operation Sleep mode Stop mode SPL=0 Watch mode SPL=1 SPL=0 SPL=1 On reset P04/INT04/ AN04/ SEG25*8/ SEG33*8/ UI1 P05/INT05/ AN05/ SEG24*8/ I/O port/ SEG32*8/ peripheral UCK1 function I/O/ P06/INT06/ analog input - Previous state - Hi-Z kept - Input - Input blocked*3, *10 blocked*3, *10 I/O port/ peripheral function I/O/ analog input - Previous state - Hi-Z kept - Input - Input blocked*3, *10 blocked*3, *10 I/O port/ peripheral function I/O I/O port/ peripheral function I/O - Hi-Z - Previous state - Previous state - Input enabled*4 - Hi-Z*7 - Hi-Z*7 (However, it kept kept 3 3 - Input blocked* - Input blocked* does not - Input blocked*3 - Input blocked*3 function.) I/O port/ peripheral function I/O I/O port/ peripheral function I/O - Previous state kept - Input blocked*3 P13/ADTG/ TO01*9 I/O port/ peripheral P14/UCK0/ function I/O I/O port/ peripheral function I/O - Hi-Z - Previous state - Previous state - Input enabled*4 7 7 - Hi-Z* - Hi-Z* kept kept (However, it - Input blocked*3 - Input blocked*3 - Input blocked*3 - Input blocked*3 does not function.) I/O port/ peripheral function I/O I/O port/ peripheral function I/O - Previous state - Previous state - Hi-Z - Hi-Z - Hi-Z kept kept 3 Input blocked* - Input blocked*3 - Input blocked*3 3 3 - Input blocked* - Input blocked* I/O port/ peripheral function I/O I/O port/ peripheral function I/O - Hi-Z Previous state - Input enabled*4 - Previous state - Hi-Z*7 - Hi-Z*7 11 (However, it kept* kept*11 - Input blocked*3 - Input blocked*3 does not - Input blocked*3 - Input blocked*3 function.) I/O port/ peripheral function I/O/ analog input I/O port/ peripheral function I/O/ analog input - Previous state - Previous state - Hi-Z*7 - Hi-Z*7 - Hi-Z kept kept 3, - Input blocked* - Input blocked*3, 3, 3, - Input enabled*4 Input blocked* - Input blocked* *12 *12 *12 *12 I/O port/ peripheral function I/O I/O port/ peripheral function I/O - Previous state - Hi-Z kept - Input - Input blocked*3, *13 blocked*3, *13 - Hi-Z - Input blocked*3 AN06/ SEG23*8/ SEG31*8 P07/INT07/ AN07/ SEG22*8/ SEG30*8 P10/UI0/ TO0*9 P11/UO0 P12/DBG EC0*9/TI0*9 P15/ SEG31*8/ PPG11 P16/ SEG30*8/ PPG10 P17/ CMP0_O P20/ PPG00/ CMP0_N P21/ PPG01/ CMP0_P P22/SCL P23/SDA “H” - Previous state kept - Input blocked*3 “H” - Previous state - Hi-Z kept - Input - Input blocked*3, *13 blocked*3, *13 “H” - Hi-Z - Input enabled*4 (Continued) DS702–00019–1v0-E 153 MB95710M/770M Series Pin name Normal operation Sleep mode Stop mode SPL=0 SPL=1 Watch mode SPL=0 SPL=1 On reset P40/ SEG21*14 P41/ SEG20*14 I/O port/ peripheral function I/O I/O port/ peripheral function I/O - Previous state - Previous state - Hi-Z - Hi-Z - Hi-Z kept kept 3 Input blocked* - Input blocked*3 - Input blocked*3 3 3 - Input blocked* - Input blocked* P51/EC0*14 I/O port/ peripheral P52/TI0/ function I/O 14 TO00* I/O port/ peripheral function I/O - Hi-Z - Input enabled*4 - Previous state - Previous state 7 7 - Hi-Z* - Hi-Z* (However, it kept kept 3 3 - Input blocked* - Input blocked* does not - Input blocked*3 - Input blocked*3 function.) I/O port/ peripheral function I/O I/O port/ peripheral function I/O - Previous state - Previous state - Hi-Z - Hi-Z - Hi-Z kept kept 3 3 - Input blocked*3 Input blocked* Input blocked* - Input blocked*3 - Input blocked*3 I/O port/ peripheral function I/O I/O port/ peripheral function I/O - Previous state - Previous state - Hi-Z - Hi-Z - Hi-Z kept kept 3 - Input blocked* - Input blocked*3 - Input blocked*3 3 3 - Input blocked* - Input blocked* P42/ SEG19*14 P43/ SEG18*14 P50/ TO01*14 P53/TO0*14 P60/ SEG06*8/ SEG10*8 P61/ SEG07*8/ SEG11*8 P62/ SEG08*8/ SEG12*8 P63/ SEG09*8/ SEG13*8 P64/ SEG10*8/ SEG14*8 P65/ SEG11*8/ SEG15*8 P66/ SEG12*8/ SEG16*8 P67/ SEG13*8/ SEG17*8 P90/V4 P91/V3 P92/V2 P93/V1 P94/V0*14 (Continued) 154 DS702–00019–1v0-E MB95710M/770M Series Pin name Normal operation Sleep mode Stop mode SPL=0 SPL=1 Watch mode SPL=0 SPL=1 On reset PA0/COM0 PA1/COM1 PA2/COM2 PA3/COM3 I/O port/ peripheral PA4/COM4 function I/O PA5/COM5 I/O port/ peripheral function I/O - Previous state - Previous state - Hi-Z - Hi-Z - Hi-Z kept kept 3 Input blocked* - Input blocked*3 - Input blocked*3 3 3 - Input blocked* - Input blocked* I/O port/ peripheral function I/O I/O port/ peripheral function I/O - Previous state - Previous state - Hi-Z - Hi-Z - Hi-Z kept kept 3 3 Input blocked* Input blocked* - Input blocked*3 - Input blocked*3 - Input blocked*3 I/O port/ peripheral function I/O I/O port/ peripheral function I/O - Previous state - Previous state - Hi-Z - Hi-Z - Hi-Z kept kept 3 Input blocked* - Input blocked*3 - Input blocked*3 3 3 - Input blocked* - Input blocked* PA6/COM6 PA7/COM7 PB0/SEG00 PB1/SEG01 PB2/ SEG37*14 PB3/ SEG38*14 PB4/ SEG39*14 PC0/ SEG02 PC1/ SEG03 PC2/ SEG04 PC3/ SEG05 PC4/ SEG06*14 PC5/ SEG07*14 PC6/ SEG08*14 PC7/ SEG09*14 (Continued) DS702–00019–1v0-E 155 MB95710M/770M Series Pin name Normal operation Sleep mode Stop mode SPL=0 SPL=1 Watch mode SPL=0 SPL=1 On reset PE0/ SEG14*8/ SEG22*8 PE1/ SEG15*8/ SEG23*8 PE2/ SEG16*8/ SEG24*8 PE3/ SEG17*8/ SEG25*8 PE4/ SEG18*8/ SEG26*8 I/O port/ peripheral function I/O I/O port/ peripheral function I/O - Previous state - Previous state - Hi-Z - Hi-Z - Hi-Z kept kept - Input blocked*3 - Input blocked*3 - Input blocked*3 - Input blocked*3 - Input blocked*3 PE5/ SEG19*8/ SEG27*8/ TO11 PE6/ SEG20*8/ SEG28*8/ TO10 PE7/ SEG21*8/ SEG29*8/ EC1 SPL: Pin state setting bit in the standby control register (STBC:SPL) Hi-Z: High impedance *1: PF0/X0 and PF1/X1 transit to this state on a reset when configured as a main clock oscillation pins. *2: The pin stays at the state shown when configured as a general-purpose I/O port. *3: “Input blocked” means direct input gate operation from the pin is disabled. *4: “Input enabled” means that the input function is enabled. While the input function is enabled, execute a pull-up operation or a pull-down operation to prevent leaks due to external input. If a pin is used as an output port, its pin state is the same as that of other ports. *5: PF2/RST stays at the state shown when configured as a reset pin. *6: PG1/X0A and PG2/X1A transit to this state on a reset when configured as subclock oscillation pins. *7: The pull-up control setting is still effective. (Continued) 156 DS702–00019–1v0-E MB95710M/770M Series (Continued) *8: The MB95710M Series and the MB95770M Series have different SEG output assignment as shown below. SEG output Pin on MB95710M Series Pin on MB95770M Series SEG06 PC4 P60 SEG07 PC5 P61 SEG08 PC6 P62 SEG09 PC7 P63 SEG10 P60 P64 SEG11 P61 P65 SEG12 P62 P66 SEG13 P63 P67 SEG14 P64 PE0 SEG15 P65 PE1 SEG16 P66 PE2 SEG17 P67 PE3 SEG18 P43 PE4 SEG19 P42 PE5 SEG20 P41 PE6 SEG21 P40 PE7 SEG22 PE0 P07 SEG23 PE1 P06 SEG24 PE2 P05 SEG25 PE3 P04 SEG26 PE4 P03 SEG27 PE5 P02 SEG28 PE6 P01 SEG29 PE7 P00 SEG30 P07 P16 SEG31 P06 P15 SEG32 P05 — SEG33 P04 — SEG34 P03 — SEG35 P02 — SEG36 P01 — *9: On the MB95770M Series, TO00 is assigned to P01, TO0 to P10, TO01 to P13, and EC0 and TI0 to P14. *10: Though input is blocked, an external interrupt can be input when the external interrupt request is enabled. *11: The output function of the comparator is still in operation in stop mode and watch mode. *12: Though input is blocked, an analog signal can also be input to generate a comparator interrupt when the comparator interrupt is enabled. *13: The I2C bus interface can wake up the MCU in stop mode or watch mode when its MCU standby mode wakeup function is enabled. For details of the MCU standby mode wakeup function, refer to “CHAPTER 23 I2C BUS INTERFACE” in “New 8FX MB95710M/770M Series Hardware Manual”. *14: P40/SEG21, P41/SEG20, P42/SEG19, P43/SEG18, P50/TO01, P51/EC0, P52/TI0/TO00, P53/TO0, P94/V0, PB2/SEG37, PB3/SEG38, PB4/SEG39, PC4/SEG06, PC5/SEG07, PC6/SEG08 and PC7/SEG09 are only available on the MB95710M Series. DS702–00019–1v0-E 157 MB95710M/770M Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Power supply voltage*1 Input voltage* 1 Output voltage* 1 Symbol Rating Min Max Unit Remarks VCC VSS − 0.3 VSS + 6 V VI VSS − 0.3 VSS + 6 V *2 VO VSS − 0.3 VSS + 6 V *2 ICLAMP −2 +2 mA Applicable to specific pins*3 Σ|ICLAMP| — 20 mA Applicable to specific pins*3 IOL — 15 mA “L” level average current IOLAV — 4 mA “L” level total maximum output current ΣIOL — 100 mA ΣIOLAV — 50 Total average output current = mA operating current × operating ratio (Total number of pins) IOH — −15 mA “H” level average current IOHAV — −4 mA “H” level total maximum output current ΣIOH — −100 mA ΣIOHAV — −50 Total average output current = mA operating current × operating ratio (Total number of pins) Power consumption Pd — 320 mW Operating temperature TA −40 +85 °C Storage temperature Tstg −55 +150 °C Maximum clamp current Total maximum clamp current “L” level maximum output current “L” level total average output current “H” level maximum output current “H” level total average output current Average output current = operating current × operating ratio (1 pin) Average output current = operating current × operating ratio (1 pin) (Continued) 158 DS702–00019–1v0-E MB95710M/770M Series (Continued) *1: These parameters are based on the condition that VSS is 0.0 V. *2: V1 and V0 must not exceed VCC + 0.3 V. V1 must not exceed the rated voltage. However, if the maximum current to/from an input is limited by means of an external component, the ICLAMP rating is used instead of the VI rating. *3: Specific pins: P00 to P07, P10, P11, P13 to P16, P20 to P22, P40 to P43, P50 to P53, P60 to P67, P90 to P94, PA0 to PA7, PB0 to PB4, PC0 to PC7, PE0 to PE7, PF0, PF1, PG1, PG2 (P40 to P43, P50 to P53, P94, PB2 to PB4 and PC4 to PC7 are only available on the MB95710M Series.) • Use under recommended operating conditions. • Use with DC voltage (current). • The HV (High Voltage) signal is an input signal exceeding the VCC voltage. Always connect a limiting resistor between the HV (High Voltage) signal and the microcontroller before applying the HV (High Voltage) signal. • The value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin when the HV (High Voltage) signal is input is below the standard value, irrespective of whether the current is transient current or stationary current. • When the microcontroller drive current is low, such as in low power consumption modes, the HV (High Voltage) input potential may pass through the protective diode to increase the potential of the VCC pin, affecting other devices. • If the HV (High Voltage) signal is input when the microcontroller power supply is off (not fixed at 0 V), since power is supplied from the pins, incomplete operations may be executed. • If the HV (High Voltage) input is input after power-on, since power is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. • Do not leave the HV (High Voltage) input pin unconnected. • Example of a recommended circuit: • Input/Output equivalent circuit Protective diode VCC P-ch Limiting resistor HV(High Voltage) input (0 V to 16 V) N-ch R WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings. DS702–00019–1v0-E 159 MB95710M/770M Series 2. Recommended Operating Conditions (VSS = 0.0 V) Parameter Symbol Value Min Max Unit Remarks Power supply voltage VCC 1.8*1 5.5 V In normal operation Decoupling capacitor CS 0.2 10 µF A capacitor of about 1.0 µF is recommended. *2 Operating temperature TA −40 +85 +5 +35 °C Other than on-chip debug mode On-chip debug mode *1: The minimum power supply voltage becomes 2.18 V when a product with the low-voltage detection reset is used or when the on-chip debug mode is used. *2: Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. For the connection to a decoupling capacitor CS, see the diagram below. To prevent the device from unintentionally entering an unknown mode due to noise, minimize the distance between the C pin and CS and the distance between CS and the VSS pin when designing the layout of a printed circuit board. • DBG / RST / C pins connection diagram * DBG C RST Cs *: Connect the DBG pin to an external pull-up resistor of 2 kΩ or above. After power-on, ensure that the DBG pin does not stay at “L” level until the reset output is released. The DBG pin becomes a communication pin in debug mode. Since the actual pull-up resistance depends on the tool used and the interconnection length, refer to the tool document when selecting a pull-up resistor. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated under these conditions. Any use of semiconductor devices will be under their recommended operating condition. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. 160 DS702–00019–1v0-E MB95710M/770M Series 3. DC Characteristics (VCC = 3.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol “H” level input voltage “L” level input voltage Pin name Condition VIHI P01, P04, P10, P22, P23 Value Unit Remarks Min Typ Max *1 0.7 VCC — VCC + 0.3 V VIHS P00 to P07, P10 to P17, P20 to P23, P40 to P43*2, P50 to P53*2, P60 to P67, P90 to P93, P94*2, PA0 to PA7, PB0, PB1, PB2 to PB4*2, PC0 to PC3, PC4 to PC7*2, PE0 to PE7, PF0, PF1, PG1, PG2 *1 0.8 VCC — VCC + 0.3 V Hysteresis input VIHM PF2 — 0.7 VCC — VCC + 0.3 V Hysteresis input VILI P01, P04, P10, P22, P23 *1 VSS − 0.3 — 0.3 VCC V VILS P00 to P07, P10 to P17, P20 to P23, P40 to P43*2, P50 to P53*2, P60 to P67, P90 to P93, P94*2, PA0 to PA7, PB0, PB1, PB2 to PB4*2, PC0 to PC3, PC4 to PC7*2, PE0 to PE7, PF0, PF1, PG1, PG2 *1 VSS − 0.3 — 0.2 VCC V Hysteresis input VILM PF2 — VSS − 0.3 — 0.3 VCC V Hysteresis input — VSS − 0.3 — VSS + 5.5 V VCC − 0.5 — — V Open-drain output application voltage VD P12, P22, P23, PF2 “H” level output voltage VOH Output pins other than P12, IOH = −4 mA*3 P22, P23, PF2 (Continued) DS702–00019–1v0-E 161 MB95710M/770M Series (VCC = 3.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter “L” level output voltage Input leak current (Hi-Z output leak current) Internal pull-up resistor Input capacitance Symbol Pin name Condition Value Unit Remarks Min Typ Max All output pins IOL = 4 mA*4 — — 0.4 V ILI All input pins 0.0 V < VI < VCC −5 — +5 µA RPULL P10, P11, P13, P14, P17, P20, P21, P50 to P53*2, PG1, PG2 VI = 0 V 75 100 150 When the internal kΩ pull-up resistor is enabled — 5 15 pF VOL CIN Other than VCC f = 1 MHz and VSS When the internal pull-up resistor is disabled (Continued) 162 DS702–00019–1v0-E MB95710M/770M Series (VCC = 3.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2) ICC Value Min — Typ*1 Max*5 4.7 Unit Remarks 7.3 Except during Flash memory mA programming and erasing — 9.8 15.8 During Flash memory mA programming and erasing — 2.1 3.4 mA ICCL VCC (External clock FCL = 32 kHz FMPL = 16 kHz operation) Subclock mode (divided by 2) TA = +25 °C — 35 60 µA ICCLS FCL = 32 kHz FMPL = 16 kHz Subsleep mode (divided by 2) TA = +25 °C — 2 7 µA ICCT FCL = 32 kHz Watch mode Main stop mode TA = +25 °C — 1.2 6.2 µA ICCMPLL FMPLL = 16 MHz FMP = 16 MHz Main PLL clock mode (multiplied by 4) — 5.3 8.5 mA FMCRPLL = 16 MHz FMP = 16 MHz Main CR PLL clock mode (multiplied by 4) — 4.9 8.3 mA ICCMCR FCRH = 4 MHz FMP = 4 MHz Main CR clock mode — 1.7 3.4 mA ICCSCR Sub-CR clock mode TA = +25 °C — 54 100 µA ICCS Power supply current*6 Condition ICCMCRPLL VCC FCH = 32 MHz FMP = 16 MHz Main sleep mode (divided by 2) (Continued) DS702–00019–1v0-E 163 MB95710M/770M Series (VCC = 3.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol ICCTS Pin name Condition FCH = 32 MHz Time-base timer VCC mode (External clock TA = +25 °C operation) Substop mode TA = +25 °C Value Min Typ*1 Max*5 Unit — 450 500 µA — 0.7 5 µA IA FCH = 16 MHz Current consumption of the A/D converter — 1.8 3.2 mA IAH FCH = 16 MHz Current consumption with the A/D converter halted — 0.1 1.7 µA IV FCH = 16 MHz Current consumption of the comparator — 160 700 µA IPLVD Current consumption of the low-voltage detection reset circuit in operation — 6 26 µA IILVD Current consumption of the low-voltage detection interrupt circuit operating in normal mode — 6 14 µA IILVDL Current consumption of the low-voltage detection interrupt circuit operating in low power consumption mode — 3 10 µA ICRH Current consumption of the main CR oscillator — 270 320 µA ICRL Current consumption of the sub-CR oscillator oscillating at 100 kHz — 5 20 µA ISOSC Current consumption of the suboscillator — 0.8 7 µA ICCH AVCC Power supply current*6 VCC Remarks (Continued) 164 DS702–00019–1v0-E MB95710M/770M Series (Continued) (VCC = 3.0 V±10%, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name LCD internal division resistance RLCD — COM0 to COM7 output impedance RVCOM SEG00 to SEG39*7 output impedance RVSEG SEG00 to SEG39*7 ILCDL V0*8 to V4, COM0 to COM7, SEG00 to SEG39*7 LCD leakage current Condition Between V4 and VSS COM0 to COM7 Value Min Typ*1 Max*5 Unit — 400 — kΩ — 40 — kΩ — — 5 kΩ — — 7 kΩ −1 — +1 µA Remarks V1 to V4 = 4.1 V — *1: VCC = 3.0 V, TA = +25 °C *2: P40 to P43, P50 to P53, P94, PB2 to PB4 are only available on the MB95710M Series. *3: When VCC is smaller than 4.5 V, the condition becomes IOH = −2 mA. *4: When VCC is smaller than 4.5 V, the condition becomes IOL = 2 mA. *5: VCC = 3.3 V, TA = +85 °C (unless otherwise specified) *6: • The power supply current is determined by the external clock. When the low-voltage detection reset circuit is selected, the power supply current is the sum of adding the current consumption of the low-voltage detection reset circuit (IPLVD) to one of the values from ICC to ICCH. In addition, when both the low-voltage detection reset circuit and a CR oscillator are selected, the power supply current is the sum of adding up the current consumption of the low-voltage detection reset circuit (IPLVD), the current consumption of the CR oscillator (ICRH or ICRL) and one of the values from ICC to ICCH. In on-chip debug mode, the main CR oscillator (ICRH) and the low-voltage detection reset circuit are always in operation, and current consumption therefore increases accordingly. • See “4. AC Characteristics (1) Clock Timing” for FCH, FCL, FCRH, FMCRPLL and FMPLL. • See “4. AC Characteristics (2) Source Clock/Machine Clock” for FMP and FMPL. • The power supply current in subclock mode is determined by the external clock. In subclock mode, current consumption in using the crystal oscillator is higher than that in using the external clock. When the crystal oscillator is used, the power supply current is the sum of adding ISOSC (current consumption of the suboscillator) to the power supply current in using the external clock. For details of controlling the subclock, refer to “CHAPTER 3 CLOCK CONTROLLER” and “CHAPTER 30 SYSTEM CONFIGURATION REGISTER” in “New 8FX MB95710M/770M Series Hardware Manual”. *7: SEG32 to SEG39 are only available on the MB95710M Series. *8: V0 is only available on the MB95710M Series. DS702–00019–1v0-E 165 MB95710M/770M Series 4. AC Characteristics (1) Clock Timing (VCC = 1.8 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Condition Typ Max Unit Remarks — 1 — 16.25 MHz When the main oscillation circuit is used X0 — 1 — 32.5 MHz When the main external clock is used 4 — 8.13 Operating conditions MHz • The main clock is used. • PLL multiplication rate: 2 4 — 6.5 Operating conditions MHz • The main clock is used. • PLL multiplication rate: 2.5 4 — 5.41 Operating conditions MHz • The main clock is used. • PLL multiplication rate: 3 4 — 4.06 Operating conditions MHz • The main clock is used. • PLL multiplication rate: 4 3.92 4 4.08 Operating conditions MHz • The main CR clock is used. • 0 °C ≤ TA ≤ +70 °C X0, X1 — — — Clock frequency FMCRPLL Min X0, X1 FCH FCRH Value — 3.8 4 4.2 Operating conditions • The main CR clock is used. MHz • − 40 °C ≤ TA < 0 °C, + 70 °C < TA ≤ + 85 °C 7.84 8 8.16 Operating conditions MHz • PLL multiplication rate: 2 • 0 °C ≤ TA ≤ +70 °C 7.6 8 8.4 Operating conditions • PLL multiplication rate: 2 MHz • − 40 °C ≤ TA < 0 °C, + 70 °C < TA ≤ + 85 °C 9.8 10 10.2 Operating conditions MHz • PLL multiplication rate: 2.5 • 0 °C ≤ TA ≤ +70 °C Operating conditions • PLL multiplication rate: 2.5 MHz • − 40 °C ≤ TA < 0 °C, + 70 °C < TA ≤ + 85 °C — 9.5 10 10.5 11.76 12 Operating conditions 12.24 MHz • PLL multiplication rate: 3 • 0 °C ≤ TA ≤ +70 °C 12 Operating conditions • PLL multiplication rate: 3 MHz • − 40 °C ≤ TA < 0 °C, + 70 °C < TA ≤ + 85 °C 11.4 12.6 (Continued) 166 DS702–00019–1v0-E MB95710M/770M Series (Continued) Parameter (VCC = 1.8 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name Condition — FMCRPLL Clock frequency — FMPLL FCL X0A, X1A tHCYL tLCYL Max 15.68 16 Operating conditions 16.32 MHz • PLL multiplication rate: 4 • 0 °C ≤ TA ≤ +70 °C 15.2 16 16.8 Operating conditions • PLL multiplication rate: 4 MHz • − 40 °C ≤ TA < 0 °C, + 70 °C < TA ≤ + 85 °C 8 — 16 MHz When the main PLL clock is used — 32.768 — kHz When the sub-oscillation circuit is used — 32.768 — kHz When the sub-external clock is used —— — 50 100 150 kHz When the sub-CR clock is used X0, X1 — 61.5 — 1000 ns When the main oscillation circuit is used X0 — 30.8 — 1000 ns When an external clock is used X0, X1 — — 250 — ns When the main PLL clock is used X0A, X1A — — 30.5 — µs When the subclock is used X0 — 12.4 — — ns When an external clock is used, the duty ratio should range between 40% and 60%. X0, X1 — — 125 — ns When the main PLL clock is used — — 15.2 — µs When an external clock is used, the duty ratio should range between 40% and 60%. — — — 5 ns When an external clock is used tWH1, tWL1 Input clock pulse width tWH2, tWL2 X0A Input clock rising time and tCR, tCF X0, X0A falling time CR oscillation start time Remarks Typ — — Unit Min — FCRL Clock cycle time Value tCRHWK — — — — 50 µs When the main CR clock is used tCRLWK — — — — 30 µs When the sub-CR clock is used — — — — 100 µs When the main CR PLL clock is used PLL oscillation tMCRPLLWK start time DS702–00019–1v0-E 167 MB95710M/770M Series • Input waveform generated when an external clock (main clock) is used tHCYL tWH1 tWL1 tCR tCF 0.8 VCC 0.8 VCC X0, X1 0.2 VCC 0.2 VCC 0.2 VCC • Figure of main clock input port external connection When a crystal oscillator or a ceramic oscillator is used X0 When an external clock is used X0 X1 FCH FCH • Input waveform generated when an external clock (subclock) is used tLCYL tWH2 tCR tWL2 tCF 0.8 VCC 0.8 VCC X0A 0.2 VCC 0.2 VCC 0.2 VCC • Figure of subclock input port external connection When a crystal oscillator or a ceramic oscillator is used X0A X1A When an external clock is used X0A FCL FCL • Input waveform generated when an internal clock (main CR clock) is used tCRHWK 1/FCRH Main CR clock Oscillation starts 168 Oscillation stabilizes DS702–00019–1v0-E MB95710M/770M Series • Input waveform generated when an internal clock (sub-CR clock) is used tCRLWK 1/FCRL Sub-CR clock Oscillation starts Oscillation stabilizes • Input waveform generated when an internal clock (main CR PLL clock) is used 1/FMCRPLL tMCRPLLWK Main CR PLL clock Oscillation starts DS702–00019–1v0-E Oscillation stabilizes 169 MB95710M/770M Series (2) Source Clock/Machine Clock (VCC = 1.8 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Source clock cycle time*1 Symbol tSCLK Pin name — FSPL Machine clock cycle time*2 (minimum instruction execution time) tMCLK Unit Remarks Min Typ Max 61.5 — 2000 ns When the main external clock is used Min: FCH = 32.5 MHz, divided by 2 Max: FCH = 1 MHz, divided by 2 — 250 — ns When the main CR clock is used 62.5 — 250 ns When the main PLL clock is used Min: FCH = 4 MHz, multiplied by 4 Max: FCH = 4 MHz, no division 62.5 — 250 ns When the main CR PLL clock is used Min: FCRH = 4 MHz, multiplied by 4 Max: FCRH = 4 MHz, no division — 61 — µs When the sub-oscillation clock is used FCL = 32.768 kHz, divided by 2 — 20 — µs When the sub-CR clock is used FCL = 100 kHz, divided by 2 0.5 — 16.25 — 4 — MHz When the main CR clock is used 8 — 16 MHz When the main PLL clock is used 8 — 16 MHz When the main CR PLL clock is used — 16.384 — kHz When the sub-oscillation clock is used — 50 — kHz 61.5 — 32000 ns When the main oscillation clock is used Min: FSP = 16.25 MHz, no division Max: FSP = 0.5 MHz, divided by 16 250 — 4000 ns When the main CR clock is used Min: FSP = 4 MHz, no division Max: FSP = 4 MHz, divided by 16 62.5 — 2000 ns When the main PLL clock is used Min: FSP = 4 MHz, multiplied by 4 Max: FSP = 4 MHz, divided by 16 62.5 — 2000 ns When the main CR PLL clock is used Min: FSP = 4 MHz, multiplied by 4 Max: FSP = 4 MHz, divided by 16 61 — 976.5 µs When the sub-oscillation clock is used Min: FSPL = 16.384 kHz, no division Max: FSPL = 16.384 kHz, divided by 16 20 — 320 µs When the sub-CR clock is used Min: FSPL = 50 kHz, no division Max: FSPL = 50 kHz, divided by 16 — FSP Source clock frequency Value MHz When the main oscillation clock is used — When the sub-CR clock is used FCRL = 100 kHz, divided by 2 (Continued) 170 DS702–00019–1v0-E MB95710M/770M Series (Continued) Parameter (VCC = 1.8 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name FMP Machine clock frequency — FMPL Value Unit Remarks Min Typ Max 0.031 — 16.25 0.25 — 4 MHz When the main CR clock is used 0.5 — 16 MHz When the main PLL clock is used 0.5 — 16 MHz When the main CR PLL clock is used 1.024 — 16.384 kHz When the sub-oscillation clock is used 3.125 — 50 MHz When the main oscillation clock is used kHz When the sub-CR clock is used FCRL = 100 kHz *1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio select bits (SYCC:DIV[1:0]). This source clock is divided to become a machine clock according to the division ratio set by the machine clock division ratio select bits (SYCC:DIV[1:0]). In addition, a source clock can be selected from the following. • Main clock divided by 2 • PLL multiplication of main clock (Select a multiplication rate from 2, 2.5, 3 and 4.) • Main CR clock • PLL multiplication of main CR clock (Select a multiplication rate from 2, 2.5, 3 and 4.) • Subclock divided by 2 • Sub-CR clock divided by 2 *2: This is the operating clock of the microcontroller. A machine clock can be selected from the following. • Source clock (no division) • Source clock divided by 4 • Source clock divided by 8 • Source clock divided by 16 DS702–00019–1v0-E 171 MB95710M/770M Series • Schematic diagram of the clock generation block FCH (Main oscillation clock) Divided by 2 FMPLL (Main PLL clock) FCRH (Main CR clock) SCLK (Source clock) FMCRPLL (Main CR PLL clock) FCL (Suboscillation clock) Divided by 2 FCRL (Sub-CR clock) Divided by 2 Division circuit × 1 × 1/4 × 1/8 × 1/16 MCLK (Machine clock) Machine clock divide ratio select bits (SYCC:DIV[1:0]) Clock mode select bits (SYCC:SCS[2:0]) • Operating voltage - Operating frequency (TA = −40 °C to +85 °C) 5.5 5.0 Operating voltage (V) 4.5 4.0 A/D converter operation range 3.5 3.0 2.5 2.0 1.8 1.5 ≈ 0.0 16 kHz 3 MHz 10 MHz 16.25 MHz Source clock frequency (FSP/FSPL) 172 DS702–00019–1v0-E MB95710M/770M Series (3) External Reset (VCC = 3.0 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol RST “L” level pulse width tRSTL Value Min Max 2 tMCLK* — Unit Remarks ns *: See “(2) Source Clock/Machine Clock” for tMCLK. tRSTL RST 0.2 VCC DS702–00019–1v0-E 0.2 VCC 173 MB95710M/770M Series (4) Power-on Reset (VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Value Pin name Min Typ Max Unit Remarks Power supply rising time dV/dt 0.1 — — V/ms Power supply cutoff time Toff 1 — — ms Reset release voltage Vdeth 1.44 1.60 1.76 V At voltage rise Reset detection voltage Vdetl 1.39 1.55 1.71 V At voltage fall Reset release delay time Tond — — 10 ms dV/dt ≥ 0.1 mV/µs Reset detection delay time Toffd — — 0.4 ms dV/dt ≥ −0.04 mV/µs VCC Toff Vdeth Vdetl VCC dV 0.2 V dt Power-on reset 174 Tond 0.2 V Toffd DS702–00019–1v0-E MB95710M/770M Series (5) Peripheral Input Timing (VCC = 3.0 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Peripheral input “H” pulse width tILIH Peripheral input “L” pulse width tIHIL Value Pin name INT00 to INT07, EC0, EC1, ADTG Unit Min Max 2 tMCLK* ⎯ ns 2 tMCLK* ⎯ ns *: See “(2) Source Clock/Machine Clock” for tMCLK. tILIH INT00 to INT07, EC0, EC1, ADTG DS702–00019–1v0-E 0.8 VCC tIHIL 0.8 VCC 0.2 VCC 0.2 VCC 175 MB95710M/770M Series (6) Low-voltage Detection • Normal mode (VCC = 1.8 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Value Min Typ Max Unit Remarks Reset release voltage VPDL+ 1.88 2.03 2.18 V At power supply rise Reset detection voltage VPDL− 1.8 1.93 2.06 V At power supply fall Interrupt release voltage 0 VIDL0+ 2.13 2.3 2.47 V At power supply rise Interrupt detection voltage 0 VIDL0− 2.05 2.2 2.35 V At power supply fall Interrupt release voltage 1 VIDL1+ 2.41 2.6 2.79 V At power supply rise Interrupt detection voltage 1 VIDL1− 2.33 2.5 2.67 V At power supply fall Interrupt release voltage 2 VIDL2+ 2.69 2.9 3.11 V At power supply rise Interrupt detection voltage 2 VIDL2− 2.61 2.8 2.99 V At power supply fall Interrupt release voltage 3 VIDL3+ 3.06 3.3 3.54 V At power supply rise Interrupt detection voltage 3 VIDL3− 2.98 3.2 3.42 V At power supply fall Interrupt release voltage 4 VIDL4+ 3.43 3.7 3.97 V At power supply rise Interrupt detection voltage 4 VIDL4− 3.35 3.6 3.85 V At power supply fall Interrupt release voltage 5 VIDL5+ 3.81 4.1 4.39 V At power supply rise Interrupt detection voltage 5 VIDL5− 3.73 4 4.27 V At power supply fall Power supply start voltage Voff — — 1.6 V Power supply end voltage Von 4.39 — — V tr 697.5 — — µs Slope of power supply that the reset release signal generates within the rating (VPDL+/VIDL+) Slope of power supply that the reset detection signal generates within the rating (VPDL-/VIDL-) Power supply voltage change time (at power supply rise) Power supply voltage change time (at power supply fall) tf 697.5 — — µs Reset release delay time tdp1 — — 30 µs Reset detection delay time tdp2 — — 30 µs Interrupt release delay time tdi1 — — 30 µs Interrupt detection delay time tdi2 — — 30 µs Interrupt threshold voltage transition stabilization time tstb — — 30 µs 176 DS702–00019–1v0-E MB95710M/770M Series • Low power consumption mode (VCC = 1.8 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Value Min Typ Max Unit Remarks Interrupt release voltage 0 VIDLL0+ 2.06 2.3 2.54 V At power supply rise Interrupt detection voltage 0 VIDLL0− 1.98 2.2 2.42 V At power supply fall Interrupt release voltage 1 VIDLL1+ 2.33 2.6 2.87 V At power supply rise Interrupt detection voltage 1 VIDLL1− 2.25 2.5 2.75 V At power supply fall Interrupt release voltage 2 VIDLL2+ 2.6 2.9 3.2 V At power supply rise Interrupt detection voltage 2 VIDLL2− 2.52 2.8 3.08 V At power supply fall Interrupt release voltage 3 VIDLL3+ 2.96 3.3 3.64 V At power supply rise Interrupt detection voltage 3 VIDLL3− 2.88 3.2 3.52 V At power supply fall Interrupt release voltage 4 VIDLL4+ 3.32 3.7 4.08 V At power supply rise Interrupt detection voltage 4 VIDLL4− 3.24 3.6 3.96 V At power supply fall Interrupt release voltage 5 VIDLL5+ 3.68 4.1 4.52 V At power supply rise Interrupt detection voltage 5 VIDLL5− 3.6 4 4.4 V At power supply fall Power supply start voltage VoffL — — 1.6 V Power supply end voltage VonL 4.52 — — V Power supply voltage change time (at power supply rise) Power supply voltage change time (at power supply fall) trL 7300 — — µs Slope of power supply that the interrupt release signal generates within the rating (VIDLL+) Slope of power supply that the interrupt detection signal generates within the rating (VIDLL-) tfL 7300 — — µs Interrupt release delay time tdiL1 — — 400 µs Interrupt detection delay time tdiL2 — — 400 µs Interrupt threshold voltage transition stabilization time tstbL — — 400 µs Interrupt low-voltage detection mode switch time tmdsw — — 400 µs Normal mode ⇔ Low power consumption mode Note: When being used for interrupt, the low-voltage detection circuit can be switched between normal mode and low power consumption mode. Compared with normal mode, in low power consumption mode, while the detection voltage and release voltage are less accurate, and the detection delay time and the release delay time become longer, there is less power consumption. For the difference in power consumption between normal mode and low power consumption mode, see “3. DC Characteristics”. For the method of switching between normal mode and low power consumption mode, refer to “CHAPTER 16 LOWVOLTAGE DETECTION CIRCUIT” in “New 8FX MB95710M/770M Series Hardware Manual”. DS702–00019–1v0-E 177 MB95710M/770M Series VCC Von/VonL Voff/VoffL Time tf/tfL tr/trL VPDL+/VIDL+ VPDL-/VIDL- Internal reset signal or interrupt signal Time tdp2/tdi2/tdiL2 178 tdp1/tdi1/tdiL1 DS702–00019–1v0-E MB95710M/770M Series (7) I2C Bus Interface Timing (VCC = 3.0 V to 5.5 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Value Parameter Standardmode Fast-mode Min Max Min Max 0 100 0 400 kHz SCL, SDA 4.0 — 0.6 — µs Symbol Pin name Condition SCL clock frequency fSCL (Repeated) START condition hold time SDA ↓ → SCL ↓ tHD;STA SCL Unit SCL clock “L” width tLOW SCL 4.7 — 1.3 — µs SCL clock “H” width tHIGH SCL 4.0 — 0.6 — µs 4.7 — 0.6 — µs (Repeated) START condition setup time SCL ↑ → SDA ↓ tSU;STA SCL, SDA Data hold time SCL ↓ → SDA ↓↑ tHD;DAT SCL, SDA 0 3.45*2 0 0.9*3 µs Data setup time SDA ↓↑ → SCL ↑ tSU;DAT SCL, SDA 0.25 — 0.1 — µs STOP condition setup time SCL ↑ → SDA ↑ tSU;STO SCL, SDA 4 — 0.6 — µs tBUF SCL, SDA 4.7 — 1.3 — µs Bus free time between STOP condition and START condition R = 1.7 kΩ, C = 50 pF*1 *1: R represents the pull-up resistor of the SCL and SDA lines, and C the load capacitor of the SCL and SDA lines. *2: The maximum tHD;DAT in the Standard-mode is applicable only when the time during which the device is holding the SCL signal at “L” (tLOW) does not extend. *3: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, provided that the condition of tSU;DAT ≥ 250 ns is fulfilled. tWAKEUP SDA tLOW tHD;DAT tHIGH tHD;STA tBUF SCL tHD;STA tSU;DAT fSCL tSU;STA tSU;STO (Continued) DS702–00019–1v0-E 179 MB95710M/770M Series (VCC = 3.0 V to 5.5 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin Condition name Value*2 Min Max Unit Remarks SCL clock “L” width tLOW SCL (2 + nm/2)tMCLK − 20 — ns Master mode SCL clock “H” width tHIGH SCL (nm/2)tMCLK − 20 (nm/2)tMCLK + 20 ns Master mode Master mode Maximum value is applied when ns m, n = 1, 8. Otherwise, the minimum value is applied. START condition hold time tHD;STA SCL, SDA (-1 + nm/2)tMCLK − 20 (-1 + nm)tMCLK + 20 STOP condition setup time tSU;STO SCL, SDA (1 + nm/2)tMCLK − 20 (1 + nm/2)tMCLK + 20 ns Master mode START condition setup time tSU;STA SCL, SDA (1 + nm/2)tMCLK − 20 (1 + nm/2)tMCLK + 20 ns Master mode tBUF SCL, SDA (2 nm + 4)tMCLK − 20 — ns tHD;DAT SCL, SDA 3 tMCLK − 20 — ns Master mode Bus free time between STOP condition and START condition Data hold time Data setup time Setup time between clearing interrupt and SCL rising R = 1.7 kΩ, C = 50 pF*1 SCL, SDA Master mode It is assumed that “L” of SCL is not extended. The minimum value is (-2 + nm/2)tMCLK − 20 (-1 + nm/2)tMCLK + 20 ns applied to the first bit of continuous data. Otherwise, the maximum value is applied. tSU;INT SCL The minimum value is applied to the interrupt at the ninth SCL↓. (1 + nm/2)tMCLK + 20 ns The maximum value is applied to the interrupt at the eighth SCL↓. tSU;DAT (nm/2)tMCLK − 20 SCL clock “L” width tLOW SCL 4 tMCLK − 20 — ns At reception SCL clock “H” width tHIGH SCL 4 tMCLK − 20 — ns At reception (Continued) 180 DS702–00019–1v0-E MB95710M/770M Series (Continued) Parameter START condition detection STOP condition detection RESTART condition detection condition (VCC = 3.0 V to 5.5 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin Condition name tHD;STA SCL, SDA tSU;STO SCL, SDA Value*2 Min Max Unit Remarks — No START condition is detected when 1 ns tMCLK is used at reception. — No STOP condition is detected when 1 ns tMCLK is used at reception. 2 tMCLK − 20 — No RESTART condition is ns detected when 1 tMCLK is used at reception. 2 tMCLK − 20 — ns At reception 2 tMCLK − 20 2 tMCLK − 20 tSU;STA SCL, SDA Bus free time tBUF SCL, SDA Data hold time tHD;DAT SCL, SDA 2 tMCLK − 20 — ns At slave transmission mode Data setup time tSU;DAT SCL, SDA tLOW − 3 tMCLK − 20 — ns At slave transmission mode Data hold time tHD;DAT SCL, SDA 0 — ns At reception Data setup time tSU;DAT SCL, SDA tMCLK − 20 — ns At reception SDA↓ → SCL↑ (with wakeup function in use) tWAKEUP SCL, SDA Oscillation stabilization wait time +2 tMCLK − 20 — ns R = 1.7 kΩ, C = 50 pF*1 *1: R represents the pull-up resistance of the SCL and SDA lines, and C the load capacitance of the SCL and SDA lines. *2: • See “(2) Source Clock/Machine Clock” for tMCLK. • m represents the CS[4:3] bits in the I2C clock control register ch. 0 (ICCR0). • n represents the CS[2:0] bits in the I2C clock control register ch. 0 (ICCR0). • The actual timing of the I2C bus interface is determined by the values of m and n set by the machine clock (tMCLK) and the CS[4:0] bits in the ICCR0 register. • Standard-mode: m and n can be set to values in the following range: 0.9 MHz < tMCLK (machine clock) < 16.25 MHz. The usable frequencies of the machine clock are determined by the settings of m and n as shown below. (m, n) = (1, 8) : 0.9 MHz < tMCLK ≤ 1 MHz (m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4) : 0.9 MHz < tMCLK ≤ 2 MHz (m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8) : 0.9 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 98), (5, 22), (6, 22), (7, 22) : 0.9 MHz < tMCLK ≤ 10 MHz (m, n) = (8, 22) : 0.9 MHz < tMCLK ≤ 16.25 MHz • Fast-mode: m and n can be set to values in the following range: 3.3 MHz < tMCLK (machine clock) < 16.25 MHz. The usable frequencies of the machine clock are determined by the settings of m and n as shown below. (m, n) = (1, 8) : 3.3 MHz < tMCLK ≤ 4 MHz (m, n) = (1, 22), (5, 4) : 3.3 MHz < tMCLK ≤ 8 MHz (m, n) = (1, 38), (6, 4), (7, 4), (8, 4) : 3.3 MHz < tMCLK ≤ 10 MHz (m, n) = (5, 8) : 3.3 MHz < tMCLK ≤ 16.25 MHz DS702–00019–1v0-E 181 MB95710M/770M Series (8) UART/SIO, Serial I/O Timing (VCC = 3.0 V to 5.5 V, AVSS = VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Condition Serial clock cycle time tSCYC UCK ↓ → UO time tSLOV Valid UI → UCK ↑ tIVSH UCK ↑ → valid UI hold time tSHIX Serial clock “H” pulse width Serial clock “L” pulse width tSHSL tSLSH UCK ↓ → UO time tSLOV Valid UI → UCK ↑ tIVSH UCK ↑ → valid UI hold time tSHIX UCK0, UCK1, UCK2 UCK0, UCK1, UCK2, UO0, UO1, UO2 UCK0, UCK1, UCK2, UI0, UI1, UI2 UCK0, UCK1, UCK2, UI0, UI1, UI2 UCK0, UCK1, UCK2 UCK0, UCK1, UCK2 UCK0, UCK1, UCK2, UO0, UO1, UO2 UCK0, UCK1, UCK2, UI0, UI1, UI2 UCK0, UCK1, UCK2, UI0, UI1, UI2 Value Min Max — 4 tMCLK* −190 Internal clock operation output pin: 2 tMCLK* CL = 80 pF + 1 TTL Unit ns +190 ns — ns 2 tMCLK* — ns 4 tMCLK* 4 tMCLK* — — ns ns 190 ns — ns — ns External clock — operation output pin: CL = 80 pF + 1 TTL 2 tMCLK* 2 tMCLK* *: See “(2) Source Clock/Machine Clock” for tMCLK. • Internal shift clock mode tSCYC UCK0, UCK1, UCK2 0.8 VCC 0.2 VCC 0.2 VCC tSLOV UO0, UO1, UO2 0.8 VCC 0.2 VCC tIVSH UI0, UI1, UI2 tSHIX 0.7 VCC 0.7 VCC 0.3 VCC 0.3 VCC • External shift clock mode tSLSH UCK0, UCK1, UCK2 tSHSL 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV UO0, UO1, UO2 0.8 VCC 0.2 VCC tIVSH UI0, UI1, UI2 182 tSHIX 0.7 VCC 0.7 VCC 0.3 VCC 0.3 VCC DS702–00019–1v0-E MB95710M/770M Series (9) Comparator Timing (AVCC = 1.8 V to 5.5 V, AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Pin name Value Min Typ Max Unit Remarks Voltage range CMP0_P, CMP0_N 0 — AVCC V Offset voltage CMP0_P, CMP0_N −20 — +20 mV Delay time CMP0_O — 600 1200 ns Overdrive 5 mV — 120 420 ns Overdrive 50 mV — — 1200 ns Power down recovery PD: 1 → 0 0 — 150 ns Power down PD: 0 → 1 — — 1200 ns Output stabilization time at power up 1.15 1.21 1.27 V Power down delay Power up stabilization time Bandgap reference voltage DS702–00019–1v0-E CMP0_O CMP0_O — 183 MB95710M/770M Series 5. A/D Converter (1) A/D Converter Electrical Characteristics (AVCC = 1.8 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Resolution Total error Linearity error — Differential linearity error Value Unit Remarks Min Typ Max — — 12 −6 — +6 LSB VCC ≥ 2.7 V −10 — +10 LSB VCC < 2.7 V −3 — +3 LSB VCC ≥ 2.7 V −5 — +5 LSB VCC < 2.7 V −1.9 — +1.9 LSB VCC ≥ 2.7 V −2.9 — +2.9 LSB VCC < 2.7 V bit Zero transition voltage V0T VSS − 6 LSB — VSS + 8.2 LSB V Full-scale transition voltage VFST AVCC − 6.2 LSB — AVCC + 9.2 LSB V Sampling time TS * — 10 µs Compare time Tcck 0.861 — 14 µs VCC ≥ 2.7 V 2.8 — 14 µs VCC < 2.7 V Time for transiting to operation enabled state Tstt 1 — — µs Analog input current IAIN −0.3 — +0.3 µA Analog input voltage VAIN VSS — AVCC V *: See “(2) Notes on Using A/D Converter” for details of the minimum sampling time. 184 DS702–00019–1v0-E MB95710M/770M Series (2) Notes on Using A/D Converter • External impedance of analog input and its sampling time The A/D converter of the MB95710M/770M Series has a sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, considering the relationship between the external impedance and minimum sampling time, either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. In addition, if sufficient sampling time cannot be secured, connect a capacitor of about 0.1 µF to the analog input pin. • Analog input equivalent circuit Comparator Analog signal source Rext Analog input pins (AN00 to AN07) Rin Cin VCC 4.5 V ≤ VCC ≤ 5.5 V Rin 0.9 kΩ (max) 2.7 V ≤ VCC < 4.5 V 1.6 kΩ (max) 13 pF (max) 13 pF (max) Cin 1.8 V ≤ VCC < 2.7 V 4.0 kΩ (max) 13 pF (max) Note: The values are reference values. • Relationship between external impedance and minimum sampling time The necessary sampling time varies according to external impedance. Ensure that the following conditions are fulfilled when setting the sampling time. Ts ≥ ( Rin + Rext ) × Cin × 9 Ts : Sampling time Rin : Input resistance of A/D converter Cin : Input capacitance of A/D converter Rext : Output impedance of external circuit • A/D conversion error As |VCC − VSS| decreases, the A/D conversion error increases proportionately. DS702–00019–1v0-E 185 MB95710M/770M Series (3) Definitions of A/D Converter Terms • Resolution It indicates the level of analog variation that can be distinguished by the A/D converter. When the number of bits is 12, analog voltage can be divided into 212 = 4096. • Linearity error (unit: LSB) It indicates how much an actual conversion value deviates from the straight line connecting the zero transition point (“000000000000” ← → “000000000001”) of a device to the full-scale transition point (“111111111111” ← → “111111111110”) of the same device. • Differential linear error (unit: LSB) It indicates how much the input voltage required to change the output code by 1 LSB deviates from an ideal value. • Total error (unit: LSB) It indicates the difference between an actual value and a theoretical value. The error can be caused by a zero transition error, a full-scale transition errors, a linearity error, a quantum error, or noise. Ideal I/O characteristics Total error VFST 0xFFF 0xFFF 2 LSB 0xFFD Digital output Digital output 0x004 0x003 Actual conversion characteristic 0xFFE 0xFFE 0xFFD V0T {1 LSB × (N − 1) + 0.5 LSB} 0x004 VNT 0x003 1 LSB 0x002 0x002 0x001 Actual conversion characteristic Ideal characteristic 0x001 0.5 LSB VSS Analog input 1 LSB = VCC VCC − VSS V 4096 N VSS Analog input Total error of digital output N = VCC VNT − {1 LSB × (N − 1) + 0.5 LSB} LSB 1 LSB : A/D converter digital output value VNT : Voltage at which the digital output transits from 0x(N − 1) to 0xN (Continued) 186 DS702–00019–1v0-E MB95710M/770M Series (Continued) Zero transition error Full-scale transition error 0x004 Ideal characteristic Actual conversion characteristic 0xFFF Actual conversion characteristic 0x002 Ideal characteristic Digital output Digital output 0x003 Actual conversion characteristic 0xFFE VFST (measurement value) 0xFFD Actual conversion characteristic 0x001 0xFFC V0T (measurement value) VSS Analog input VCC VSS 0xFFE Ideal characteristic Actual conversion characteristic 0x(N+1) Actual conversion characteristic {1 LSB × N + V0T} VFST Digital output Digital output 0xFFD (measurement value) VNT 0x004 Actual conversion characteristic 0x003 V(N+1)T 0xN VNT 0x(N-1) Ideal characteristic 0x002 VCC Differential linearity error Linearity error 0xFFF Analog input Actual conversion characteristic 0x(N-2) 0x001 V0T (measurement value) VSS Analog input VCC Linearity error of digital output N = VSS VCC VNT − {1 LSB × N + V0T} 1 LSB Differential linearity error of digital output N = N Analog input V(N+1)T − VNT − 1 1 LSB : A/D converter digital output value VNT : Voltage at which the digital output transits from 0x(N − 1) to 0xN V0T (ideal value) = VSS + 0.5 LSB [V] VFST (ideal value) = VCC − 2 LSB [V] DS702–00019–1v0-E 187 MB95710M/770M Series 6. Flash Memory Program/Erase Characteristics Parameter Value Unit Remarks 1.6*2 s The time of writing “0x00” prior to erasure is excluded. 0.6*1 3.1*2 s The time of writing “0x00” prior to erasure is excluded. 17 272 µs System-level overhead is excluded. Program/erase cycle 100000 — — cycle Power supply voltage at program/erase 1.8 — 5.5 V 20*3 — — Average TA = +85 °C Number of program/erase cycles: 1000 or below 10*3 — — Average TA = +85 °C year Number of program/erase cycles: 1001 to 10000 inclusive 5*3 — — Min Typ Max Sector erase time (2 Kbyte sector) — 0.3*1 Sector erase time (24 Kbyte sector and 32 Kbyte sector) — Byte writing time — Flash memory data retention time Average TA = +85 °C Number of program/erase cycles: 10001 or above *1: VCC = 5.5 V, TA = +25 °C, 0 cycle *2: VCC = 1.8 V, TA = +85 °C, 100000 cycles *3: These values were converted from the result of a technology reliability assessment. (These values were converted from the result of a high temperature accelerated test using the Arrhenius equation with the average temperature being +85 °C.) 188 DS702–00019–1v0-E MB95710M/770M Series ■ SAMPLE CHARACTERISTICS • Power supply current temperature characteristics ICC − VCC TA = +25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Main clock mode with the external clock operating ICC − TA VCC = 3.3 V, FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Main clock mode with the external clock operating 10 10 FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz 8 FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz 8 6 ICC[mA] ICC[mA] 6 4 4 2 2 0 0 1 2 3 4 5 6 −50 7 0 VCC[V] ICCS − VCC TA = +25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Main sleep mode with the external clock operating +150 4 FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz 3 ICCS[mA] 3 ICCS[mA] +100 ICCS − TA VCC = 3.3 V, FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Main sleep mode with the external clock operating 4 2 1 2 1 0 0 1 2 3 4 5 6 −50 7 0 VCC[V] +50 +100 +150 TA[°C] ICCL − VCC TA = +25 °C, FMPL = 16 kHz (divided by 2) Subclock mode with the external clock operating ICCL − TA VCC = 3.3 V, FMPL = 16 kHz (divided by 2) Subclock mode with the external clock operating 140 140 120 120 100 100 80 80 ICCL[μA] ICCL[μA] +50 TA[°C] 60 60 40 40 20 20 0 0 1 2 3 4 VCC[V] 5 6 7 −50 0 +50 +100 +150 TA[°C] (Continued) DS702–00019–1v0-E 189 MB95710M/770M Series ICCLS − TA VCC = 3.3 V, FMPL = 16 kHz (divided by 2) Subsleep mode with the external clock operating 10 10 9 9 8 8 7 7 6 6 ICCLS[μA] ICCLS[μA] ICCLS − VCC TA = +25 °C, FMPL = 16 kHz (divided by 2) Subsleep mode with the external clock operating 5 5 4 4 3 3 2 2 1 1 0 0 1 2 3 4 5 6 −50 7 0 VCC[V] ICCT − VCC TA = +25 °C, FMPL = 16 kHz (divided by 2) Watch mode with the external clock operating +100 +150 ICCT − TA VCC = 3.3 V, FMPL = 16 kHz (divided by 2) Watch mode with the external clock operating 5 4 4 3 3 ICCT[μA] ICCT[μA] 5 2 2 1 1 0 0 1 2 3 4 5 6 −50 7 0 VCC[V] +50 +100 +150 TA[°C] ICCTS − VCC TA = +25 °C, FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Time-base timer mode with the external clock operating ICCTS − TA VCC = 3.3 V, FMP = 2, 4, 8, 10, 16 MHz (divided by 2) Time-base timer mode with the external clock operating 600 600 FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz 500 FMP = 16 MHz FMP = 10 MHz FMP = 8 MHz FMP = 4 MHz FMP = 2 MHz 500 400 ICCTS[μA] 400 ICCTS[μA] +50 TA[°C] 300 300 200 200 100 100 0 0 1 2 3 4 VCC[V] 5 6 7 −50 0 +50 +100 +150 TA[°C] (Continued) 190 DS702–00019–1v0-E MB95710M/770M Series ICCH − VCC TA = +25 °C, FMPL = (stop) Substop mode with the external clock stopping ICCH − TA VCC = 3.3 V, FMPL = (stop) Substop mode with the external clock stopping 5 4 4 3 3 ICCH[μA] ICCH[μA] 5 2 2 1 1 0 0 1 2 3 4 5 6 −50 7 0 VCC[V] ICCMCR − VCC TA = +25 °C, FMP = 4 MHz (no division) Main CR clock mode +100 +150 ICCMCR − TA VCC = 3.3 V, FMP = 4 MHz (no division) Main CR clock mode 5 5 4 4 3 3 ICCMCR[mA] ICCMCR[mA] +50 TA[°C] 2 1 2 1 0 0 1 2 3 4 5 6 −50 7 0 VCC[V] +50 +100 +150 TA[°C] 10 10 8 8 ICCMCRPLL[mA] ICCMCRPLL[mA] ICCMCRPLL − TA ICCMCRPLL − VCC TA = +25 °C, FMP = 16 MHz (PLL multiplication rate: 4) VCC = 3.3 V, FMP = 16 MHz (PLL multiplication rate: 4) Main CR PLL clock mode Main CR PLL clock mode 6 4 6 4 2 2 0 0 1 2 3 4 VCC[V] 5 6 7 −50 0 +50 +100 +150 TA[°C] (Continued) DS702–00019–1v0-E 191 MB95710M/770M Series (Continued) 10 10 8 8 6 6 ICCMPLL[mA] ICCMPLL[mA] ICCMPLL − TA ICCMPLL − VCC TA = +25 °C, FMP = 16 MHz (PLL multiplication rate: 4) VCC = 3.3 V, FMP = 16 MHz (PLL multiplication rate: 4) Main PLL clock mode Main PLL clock mode 4 4 2 2 0 0 1 2 3 4 5 6 −50 7 0 VCC[V] +100 +150 ICCSCR − TA VCC = 3.3 V, FMPL = 50 kHz (divided by 2) Sub-CR clock mode 200 200 150 150 ICCSCR[μA] ICCSCR[μA] ICCSCR − VCC TA = +25 °C, FMPL = 50 kHz (divided by 2) Sub-CR clock mode 100 100 50 50 0 0 1 2 3 4 5 6 −50 7 0 VCC[V] +50 +100 +150 TA[°C] IA − AVCC TA = +25 °C, FMP = 16 MHz (divided by 2) Main clock mode with the external clock operating IA − TA VCC = 3.3 V, FMP = 16 MHz (divided by 2) Main clock mode with the external clock operating 10 8 8 6 6 IA[mA] IA[mA] 10 4 4 2 2 0 0 1 2 3 4 AVCC[V] 192 +50 TA[°C] 5 6 7 −50 0 +50 +100 +150 TA[°C] DS702–00019–1v0-E MB95710M/770M Series • Input voltage characteristics VIHI − VCC and VILI − VCC TA = +25 °C VIHS − VCC and VILS − VCC TA = +25 °C 5 5 VIHS VILS 4 4 3 3 VIHS/VILS[V] VIHI/VILI[V] VIHI VILI 2 1 2 1 0 0 1 2 3 4 5 6 1 2 3 VCC[V] 4 5 6 VCC[V] VIHM − VCC and VILM − VCC TA = +25 °C 5 VIHM VILM VIHM/VILM[V] 4 3 2 1 0 1 2 3 4 5 6 VCC[V] DS702–00019–1v0-E 193 MB95710M/770M Series • Output voltage characteristics 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0.0 0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 −11 −12 −13 −14 −15 IOH[mA] VCC = 1.8 V VCC = 2.0 V VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V 194 VOL − IOL TA = +25 °C VOL[V] VCC − VOH[V] (VCC − VOH) − IOH TA = +25 °C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IOL[mA] VCC = 1.8 V VCC = 2.0 V VCC = 2.4 V VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V VCC = 4.0 V VCC = 4.5 V VCC = 5.0 V VCC = 5.5 V DS702–00019–1v0-E MB95710M/770M Series • Pull-up characteristics RPULL − VCC TA = +25 °C 300 250 RPULL[kΩ] 200 150 100 50 0 1 2 3 4 5 6 VCC[V] DS702–00019–1v0-E 195 MB95710M/770M Series ■ MASK OPTIONS Part number No. MB95F714J MB95F716J MB95F718J MB95F774J MB95F776J MB95F778J Selectable/Fixed MB95F714M MB95F716M MB95F718M MB95F774M MB95F776M MB95F778M Fixed 1 Low-voltage detection reset With low-voltage detection reset Without low-voltage detection reset 2 Reset With dedicated reset input 196 Without dedicated reset input DS702–00019–1v0-E MB95710M/770M Series ■ ORDERING INFORMATION Part number Package MB95F714JPMC-G-SNE2 MB95F714MPMC-G-SNE2 MB95F716JPMC-G-SNE2 MB95F716MPMC-G-SNE2 MB95F718JPMC-G-SNE2 MB95F718MPMC-G-SNE2 80-pin plastic LQFP (FPT-80P-M37) MB95F774JPMC1-G-SNE2 MB95F774MPMC1-G-SNE2 MB95F776JPMC1-G-SNE2 MB95F776MPMC1-G-SNE2 MB95F778JPMC1-G-SNE2 MB95F778MPMC1-G-SNE2 64-pin plastic LQFP (FPT-64P-M38) MB95F774JPMC2-G-SNE2 MB95F774MPMC2-G-SNE2 MB95F776JPMC2-G-SNE2 MB95F776MPMC2-G-SNE2 MB95F778JPMC2-G-SNE2 MB95F778MPMC2-G-SNE2 64-pin plastic LQFP (FPT-64P-M39) DS702–00019–1v0-E 197 MB95710M/770M Series ■ PACKAGE DIMENSION 80-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 12.00 mm × 12.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.47 g (FPT-80P-M37) 80-pin plastic LQFP (FPT-80P-M37) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 14.00±0.20(.551±.008)SQ 0.145±0.055 (.006±.002) *12.00±0.10(.472±.004)SQ 60 41 Details of "A" part 61 40 +0.20 1.50 –0.10 (Mounting height) +.008 .059 –.004 0.25(.010) 0~8° 0.08(.003) INDEX 80 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.10±0.05 (.004±.002) (Stand off) 21 "A" 1 20 0.50(.020) C 0.22±0.05 (.009±.002) 0.08(.003) M 2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) 198 DS702–00019–1v0-E MB95710M/770M Series 64-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 10.00 mm × 10.00 mm Lead shape Gullwing Lead bend direction Normal bend Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.32 g (FPT-64P-M38) 64-pin plastic LQFP (FPT-64P-M38) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 12.00±0.20(.472±.008)SQ 0.145±0.055 (.006±.002) *10.00±0.10(.394±.004)SQ 48 33 49 Details of "A" part 32 +0.20 0.08(.003) 1.50 –0.10 (Mounting height) +.008 .059 –.004 0.25(.010) 0~8° INDEX 64 17 1 0.22±0.05 (.009±.002) 0.10±0.10 (.004±.004) (Stand off) "A" 16 0.50(.020) C 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.08(.003) M 2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ (Continued) DS702–00019–1v0-E 199 MB95710M/770M Series (Continued) 64-pin plastic LQFP Lead pitch 0.65 mm Package width × package length 12.00 mm × 12.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.47 g (FPT-64P-M39) 64-pin plastic LQFP (FPT-64P-M39) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 14.00±0.20(.551±.008)SQ *12.00±0.10(.472±.004)SQ 48 0.145±0.055 (.006±.002) 33 Details of "A" part 49 32 +0.20 1.50 –0.10 +.008 .059 –.004 0.10(.004) INDEX 0.50±0.20 (.020±.008) 64 17 1 C 0.32±0.05 (.013±.002) 0.10±0.10 (.004±.004) 0.25(.010)BSC 0.60±0.15 (.024±.006) 16 0.65(.026) 0~8˚ "A" 0.13(.005) M 2010-2013 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-4-3 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 200 DS702–00019–1v0-E MB95710M/770M Series MEMO DS702–00019–1v0-E 201 MB95710M/770M Series MEMO 202 DS702–00019–1v0-E MB95710M/770M Series MEMO DS702–00019–1v0-E 203 MB95710M/770M Series FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. 30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District, Shanghai 201204, China Tel : +86-21-6146-3688 Fax : +86-21-6146-3660 http://cn.fujitsu.com/fss/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 902 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://www.fujitsu.com/kr/fsk/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 2/F, Green 18 Building, Hong Kong Science Park, Shatin, N.T., Hong Kong Tel : +852-2736-3232 Fax : +852-2314-4207 http://cn.fujitsu.com/fsp/ All Rights Reserved. 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Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and safeguards against injury, damage or loss from such failures or malfunctions, by incorporating safety design measures into your facility, equipments and products such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. The products and technical information described in this document are subject to the Foreign Exchange and Foreign Trade Control Law of Japan, and may be subject to export or import laws or regulations in U.S. or other countries. You are responsible for ensuring compliance with such laws and regulations relating to export or re-export of the products and technical information described herein. All company names, brand names and trademarks herein are property of their respective owners. Edited: Sales Promotion Department