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The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13740-1Ea
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90378 Series
MB90F378/V378
■ DESCRIPTION
The MB90378 series is a line of general-purpose, 16-bit microcontrollers designed for those applications which
require high-speed real-time processing. The instruction set is designed to be optimized for controller applications
which inheriting the AT architecture of F2MC-16LX family and allow a wide range of control tasks to be processed
efficiently at high speed.
A built-in LPC interface, serial IRQ and PS/2 interface simplifies communication with host CPU and PS/2 devices
in computer system. Moreover, SMbus compliant I2C*2 and A/D converter implements the smart battery control.
With these features, the MB90378 series matches itself as keyboard controller with smart battery control.
While inheriting the AT architecture of the F2MC*1 family, the instruction set for the F2MC-16LX CPU core of the
MB90378 series incorporates additional instructions for high-level languages, supports extended addressing
modes, and contains enhanced multiplication and division instructions as well as a substantial collection of
improved bit manipulation instructions. In addition, the MB90378 series has an on-chip 32-bit accumulator which
enables processing of long-word data.
*1 : F2MC stands for FUJITSU Flexible Microcontroller.
*2 : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
■ PACKAGE
144-pin plastic LQFP
(FPT-144P-M12)
Copyright©2005-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2005.4
MB90378 Series
■ FEATURES
• Clock
• Embedded PLL clock multiplication circuit
• Operating clock (PLL clock) can selected from divided-by-2 of oscillation or one to four times the oscillation
(at oscillation of 4 MHz to 20 MHz)
• Minimum instruction execution time of 50 ns (at oscillation of 5 MHz, four times the PLL clock, operation at
VCC of 3.3 V)
• CPU addressing space of 16 Mbytes
Internal 24-bit addressing
• Instruction set optimized for controller applications
• Rich data types (bit, byte, word, long word)
• Rich addressing mode (23 types)
• High code efficiency
• Enhanced precision calculation realized by the 32-bit accumulator
• Instruction set designed for high level language (C) and multi-task operations
• Adoption of system stack pointer
• Enhanced pointer indirect instructions
• Barrel shift instructions
• Program patch function (2 address pointer)
• Improved execution speed
4-byte instruction queue
• Powerful interrupt function
• Priority level programmable : 8 levels
• 32 factors of stronger interrupt function
• Automatic data transmission function independent of CPU operation
• Extended intelligent I/O service function (EI2OS)
• Maximum 16 channels
• Low-power consumption (standby) mode
• Sleep mode (mode in which CPU operating clock is stopped)
• Timebase timer mode (mode in which operations other than timebase timer and watch timer are stopped)
• Stop mode (mode in which all oscillations are stopped)
• CPU intermittent operation mode
• Watch mode
• Dual operation flash
Upper and lower banks of flash memory can be used to execute erase/program and read operation
concurrently (MB90F378)
• Package
LQFP-144 (FPT-144P-M12 : 0.4 mm pitch)
• Process
CMOS technology
2
MB90378 Series
■ PRODUCT LINEUP
Part number
MB90F378
MB90V378
Flash type ROM
⎯
ROM size
128 Kbytes (112 Kbytes + 16 Kbytes)
Dual operation
⎯
RAM size
6 Kbytes
15.6 Kbytes
Parameter
Classification
CPU function
Number of instruction
: 351
Minimum execution time : 50 ns/5 MHz (PLL x 4)
Addressing mode
: 23
Data bit length
: 1, 8, 16 bits
Maximum memory space : 16 Mbytes
I/O port
I/O port (Nch)
I/O port (CMOS)
I/O port (CMOS with pull-up control)
Total
16-bit reload timer
Reload timer : 6 channels
Reload mode, single-shot mode or event count mode selectable
8/16-bit PPG timer
PPG timer : 2 channels (8-bit mode, 4 channels)
16-bit PPG timer
PPG timer : 3 channels
PWM mode or single-shot mode selectable
Bit decoder
Bit decoder : 1 channel
Parity generator
Parity generator : 1 channel
Selectable odd/even parity
PS/2 interface
PS/2 interface : 3 channels
4 selectable sampling clocks
LPC interface
LPC bus interface
Universal peripheral Interface
GA20 output control
Data buffer array
Serial IRQ controller
Serial IRQ request : 6 channels
LPC clock monitor/control
UART
With full-duplex double buffer (variable data length)
Clock asynchronized or clock synchronized transmission (with start and stop
bits) can be selectively used
I2C
I2C (SMbus compliant) : 1 channel
Support I2C bus of PHILIPS and the SMbus proposed by Intel I2C bus
Selectable packet error check
Timeout detection function
Multi-address I2C
Multi-address I2C (SMbus compliant) : 1 channel
Support I2C bus of PHILIPS and the SMbus proposed by Intel I2C bus
Selectable packet error check
Timeout detection function
6 addresses support
ALERT function
: 25
: 68
: 32
: 125
: 1 channel
: 4 channels
: for UPI ch 0 only
: 80 bytes
(Continued)
3
MB90378 Series
(Continued)
Part number
Parameter
MB90F378
MB90V378
Bridge circuit
Three bus connection routes can be switched by I2C/multi-address I2C
DTP/external interrupt
8 independent channels
Selectable causes : Rise/fall edge, fall edge, “L” level or “H” level
Extended external interrupt
8 multiplex channels × 2 set
Selectable causes : Rise/fall edge, fall edge, rise edge or “L” level
Key-on wake-up interrupt
8 independent channels
Causes : “L” level
8/10-bit A/D converter
8/10-bit resolution : 12 channels
Conversion time : Less than 4.2 µs (20 MHz internal clock)
8-bit D/A converter
8-bit resolution : 2 channels
LCD controller/driver
Up to 9 SEG × 4 COM
Selectable LCD output or CMOS I/O port
Low-power consumption
Stop mode/Sleep mode/CPU intermittent operation mode/Watch mode
Process
CMOS
LQFP-144
(FPT-144P-M12 : 0.4 mm pitch)
Package
Operating voltage
PGA299
2.7 V to 3.6 V at 20 MHz*
* : Varies with conditions such as the operating frequency (see “■ ELECTRICAL CHARACTERISTICS”).
Assurance for the MB90V378 is given only for operation with a tool at power supply voltage of 2.7 V to 3.6 V,
an operating temperature of 0 °C to +25 °C, and an operating frequency of 1 MHz to 20 MHz.
■ PACKAGE AND CORRESPONDING PRODUCTS
Package
MB90F378
FPT-144P-M12
PGA299
X
MB90V378
X
X
: Available
: Not available
Note : For more information about each package, see “■ PACKAGE DIMENSIONS”.
■ DIFFERENCES AMONG PRODUCTS
Memory size
In evaluation with an evaluation product, note the difference between the evaluation product and the product
actually used. The following items must be taken into consideration.
• The MB90V378 does not have an internal ROM, however, operations equivalent to chips with an internal ROM
can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the
development tool.
• In the MB90V378, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH are
mapped to bank FF only. (This setting can be changed by the development tool configuration.)
• In the MB90F378, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH are
mapped to bank FF only.
4
MB90378 Series
■ PIN ASSIGNMENT
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
P37/ADTG
P36
P35
P34
P33/PG11
P32/PG10
P31/PG01
P30/PG00
P27
P26
P25
P24
P23
P22
P21
X1
X0
VSS
VCC
P20
P17
P16
P15
P14
P13
P12
P11
P10
P07/KSI7
P06/KSI6
P05/KSI5
P04/KSI4
P03/KSI3
P02/KSI2
P01/KSI1
P00/KSI0
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP-144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P77/PPG1
P76/UI3
P75/UO3
P74/UCK3
P73/UI2
P72/UO2
P71/UCK2
P70/UI1
P67/UO1
P66/UCK1
P65/INT5
P64/INT4
P63/INT3
P62/INT2
P61/INT1
P60/INT0
PD7/PPG3
VSS
VCC
PF7/V3*
PF6/V2*
PF5/V1*
PF4/COM3*
PF3/TO6/COM2*
PF2/TIN6/COM1*
PF1/TO5/COM0*
PF0/TIN5/SEG8*
PE7/TO4/SEG7
PE6/TIN4/SEG6
PE5/TO3/SEG5
PE4/TIN3/SEG4
PE3/TO2/SEG3
PE2/TIN2/SEG2
PE1/TO1/SEG1
PE0/TIN1/SEG0
P82/ALERT
PB3/EEI11
PB4/EEI12
PB5/EEI13
PB6/EEI14
PB7/EEI15
AVCC
AVR
AVSS
PC0/AN0
PC1/AN1
PC2/AN2
PC3/AN3
PC4/AN4
PC5/AN5
PC6/AN6
PC7/AN7
PD0/AN8
VCC
VSS
MD2
MD1
MD0
PD1/AN9
PD2/AN10
PD3/AN11
PD4/DA1
PD5/DA2
PD6/PPG2
P90/SCL2
P91/SDA2
P92/SCL3
P93/SDA3
P94/SCL4
P95/SDA4
P80/SCL1
P81/SDA1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
P40/PSCK0
P41/PSDA0
P42/PSCK1
P43/PSDA1
P44/PSCK2
P45/PSDA2
P46/CLKRUN
P47/SERIRQ
P50/GA20
P51/LFRAME
P52/LRESET
P53/LCK
P54/LAD0
P55/LAD1
P56/LAD2
P57/LAD3
RST
VCC
VSS
X0A
X1A
PA0/EEI0
PA1/EEI1
PA2/EEI2
PA3/EEI3
PA4/EEI4
PA5/EEI5
PA6/EEI6
PA7/EEI7
P83/INT6
P84/INT7
P85
P86
PB0/EEI8
PB1/EEI9
PB2/EEI10
(FPT-144P-M12)
* : Heavy current pins
5
MB90378 Series
■ PIN DESCRIPTION
Pin no.
Pin status
during
reset
Pin name
I/O
circuit
128,129
X0,X1
A
Oscillating Main oscillation I/O pins.
20,21
X0A,X1A
A
Oscillating Sub-clock oscillation I/O pins.
17
RST
B
Reset input External reset input pin.
58, 57, 56
MD0 to
MD2
C
Mode input
LQFP-144
P00 to P07
109 to 116
Function
Input pin for operation mode specification. Connect this pin
directly to Vcc or Vss.
General-purpose I/O ports.
D
Can be used as key-on wake-up interrupt input ch 0 to 7. Input
is enabled when 1 is set in EICR : EN0 to 7 in standby mode.
117 to 124 P10 to P17
E
General-purpose I/O ports.
125,
P20 to P27
130 to 136
E
General-purpose I/O ports.
KSI0 to
KSI7
P30, P31
137, 138
PG00,
PG01
General-purpose I/O ports.
8/16-bit PPG timer output pins.
8-bit x 2 channels mode use : Event output from PG00/PG01
16-bit x 1channel mode use : Event output from PG00
E
P32, P33
139, 140
PG10,
PG11
141 to 143 P34 to P36
144
P37
ADTG
General-purpose I/O ports.
E
E
P40
1
PSCK0
PSDA0
PSCK1
F
PSDA1
General-purpose I/O port.
External trigger input pin (ADTG) for the A/D converter.
Serial clock I/O pin for PS/2 interface ch 0. This function is
selected when PS/2 interface ch 0 is enabled.
Serial data I/O pin for PS/2 interface ch 0. This function is
selected when PS/2 interface ch 0 is enabled.
General-purpose Nch open-drain I/O port.
F
P43
4
General-purpose I/O ports.
General-purpose Nch open-drain I/O port.
P42
3
Port input
General-purpose Nch open-drain I/O port.
F
P41
2
8/16-bit PPG timer output pins.
8-bit x 2 channels mode use : Event output from PG10/PG11.
16-bit x 1channel mode use : Event output from PG10.
E
Serial clock I/O pin for PS/2 interface ch 1. This function is
selected when PS/2 interface ch 1 is enabled.
General-purpose Nch open-drain I/O port.
F
Serial data I/O pin for PS/2 interface ch 1. This function is
selected when PS/2 interface ch 1 is enabled.
(Continued)
6
MB90378 Series
Pin no.
LQFP-144
Pin name
I/O
circuit
Pin status
during
reset
P44
5
PSCK2
General-purpose Nch open-drain I/O port.
F
Serial clock I/O pin for PS/2 interface ch 2. This function is
selected when PS/2 interface ch 2 is enabled.
P45
6
PSDA2
General-purpose Nch open-drain I/O port.
F
Serial data I/O pin for PS/2 interface ch 2. This function is
selected when PS/2 interface ch 2 is enabled.
P46
7
CLKRUN
General-purpose Nch open-drain I/O port.
LPC clock status / restart request I/O pin for serial IRQ
controller. This function is selected when serial IRQ and LPC
clock restart request is enabled.
G
P47
8
SERIRQ
General-purpose I/O port.
H
Serial IRQ data I/O pin for serial IRQ controller. This function is
selected when serial IRQ is enabled.
P50
9
GA20
General-purpose Nch open-drain I/O port.
J
GA20 output for LPC interface. This function is selected when
GA20 function is enabled.
P51
10
LFRAME
General-purpose I/O port.
H
P52
11
LRESET
LCK
LAD0 to
LAD3
H
INT0 to
INT5
UCK1
Clock input for LPC interface. This function is selected when
LPC interface is enabled.
Address/Data I/O for LPC interface. This function is selected
when LPC interface is enabled.
General-purpose I/O ports.
I
P66
99
Reset input for LPC interface. This function is selected when
LPC interface is enabled.
General-purpose I/O ports.
H
P60 to P65
93 to 98
LFRAME input for LPC interface. This function is selected when
LPC interface is enabled.
General-purpose I/O port.
P54 to P57
13 to 16
Port input
General-purpose I/O port.
H
P53
12
Function
Can be used as DTP/external interrupt request input ch 0 to 5.
Input is enabled when 1 is set in ENIR: EN0 to 5 in standby
mode.
General-purpose I/O port.
I
Serial clock I/O pin for UART ch 1. This function is enabled
when UART ch 1 enables clock output.
(Continued)
7
MB90378 Series
Pin no.
LQFP-144
Pin name
I/O
circuit
Pin status
during
reset
P67
100
UO1
General-purpose I/O port.
I
Serial data output pin for UART ch 1. This function is
enabled when UART ch 1 enables data output.
P70
101
UI1
General-purpose I/O port.
Serial data input pin for UART ch 1. While UART ch 1 is
operating for input, the input of this pin is used as required and
must not be used for any other input.
I
P71
102
UCK2
General-purpose I/O port.
I
Serial clock I/O pin for UART ch 2. This function is enabled
when UART ch 2 enables clock output.
P72
103
UO2
General-purpose I/O port.
I
Serial data output pin for UART ch 2. This function is
enabled when UART ch 2 enables data output.
P73
104
UI2
General-purpose I/O port.
UCK3
Port input
I
P75
106
UO3
UI3
71
72
PPG1
P80
SCL1
P81
SDA1
Serial clock I/O pin for UART ch 3. This function is enabled
when UART ch 3 enables clock output.
Serial data output pin for UART ch 3. This function is
enabled when UART ch 3 enables data output.
General-purpose I/O port.
I
P77
108
General-purpose I/O port.
General-purpose I/O port.
I
P76
107
Serial data input pin for UART ch 2. While UART ch 2 is
operating for input, the input of this pin is used as required and
must not be used for any other input.
I
P74
105
Function
Serial data input pin for UART ch 3. While UART ch 3 is
operating for input, the input of this pin is used as required and
must not be used for any other input.
General-purpose I/O port.
I
T
T
Output pin for PPG ch 1. This function is enabled when
PPG ch 1 output is enabled.
General-purpose Nch open-drain I/O port.
Serial clock I/O pin for multi-address I2C.
General-purpose Nch open-drain I/O port.
Serial data I/O pin for multi-address I2C.
(Continued)
8
MB90378 Series
Pin no.
LQFP-144
73
Pin name
P82
ALERT
I/O
circuit
Pin status
during
reset
General-purpose Nch open-drain I/O port.
J
ALERT output pin for multi-address I2C.
P83, P84
30, 31
INT6, INT7
Function
General-purpose I/O ports.
I
Can be used as DTP/external interrupt request input ch6, 7.
Input is enabled when 1 is set in ENIR: EN6, 7 in standby mode.
32
P85
I
General-purpose I/O port.
33
P86
I
General-purpose I/O port.
65
66
67
68
69
70
P90
SCL2
P91
SDA2
P92
SCL3
P93
SDA3
P94
SCL4
P95
SDA4
General-purpose Nch open-drain I/O port.
T
Serial clock I/O pin for bridge circuit.
General-purpose Nch open-drain I/O port.
T
Serial data I/O pin for bridge circuit.
General-purpose Nch open-drain I/O port.
T
Serial clock I/O pin for bridge circuit.
Port input
T
Serial data I/O pin for bridge circuit.
General-purpose Nch open-drain I/O port.
T
Serial clock I/O pin for bridge circuit.
General-purpose Nch open-drain I/O port.
T
Serial data I/O pin for bridge circuit.
PA0 to PA7
22 to 29
EEI0 to
EEI7
General-purpose I/O ports.
External IRQ input pin for Extend External Interrupt request ch0
to 7.
When IRQ detect, prepare to the CPU Interrupt. (Multiplex)
I
PB0 to PB7
34 to 41
EEI8 to
EEI15
General-purpose I/O ports.
External IRQ input pin for Extend External Interrupt request ch8
to 15.
When IRQ detect, prepare to the CPU Interrupt. (Multiplex)
I
PC0 to PC7
45 to 52
53,
59 to 61
AN0 to AN7
General-purpose I/O ports.
M
A/D input
PD0 to PD3
AN8 to
AN11
General-purpose Nch open-drain I/O port.
M
A/D converter analog input pin 0 to 7. This function is enabled
when the analog input specification is enabled (ADER1).
General-purpose I/O ports.
A/D converter analog input pin 8 to 11. This function is enabled
when the analog input specification is enabled (ADER2).
(Continued)
9
MB90378 Series
Pin no.
LQFP-144
Pin name
I/O
circuit
Pin status
during
reset
PD4, PD5
62, 63
DA1, DA2
General-purpose I/O ports.
N
D/A converter analog output 1, 2. This function is selected when
D/A converted is enabled.
PD6, PD7
64, 92
PPG2,
PPG3
General-purpose I/O ports.
H
Output pin for PPG ch 2, 3. This function is selected when PPG
ch 2, 3 output is enabled.
PE0
74
75
76
SEG0
General-purpose I/O port.
TIN1
External clock input pin for reload timer 1.
PE1
General-purpose I/O port.
SEG1
79
80
Segment output pin for LCD controller/driver. This function is
selected when LCD segment output is enabled.
O
TO1
Event output pin for reload timer 1.
PE2
General-purpose I/O port.
SEG2
SEG3
Segment output pin for LCD controller/driver. This function is
selected when LCD segment output is enabled.
O
Port input
PE3
78
Segment output pin for LCD controller/driver. This function is
selected when LCD segment output is enabled.
O
TIN2
77
Function
External clock input pin for reload timer 2.
General-purpose I/O port.
O
Segment output pin for LCD controller/driver. This function is
selected when LCD segment output is enabled.
TO2
Event output pin for reload timer 2.
PE4
General-purpose I/O port.
SEG4
O
Segment output pin for LCD controller/driver. This function is
selected when LCD segment output is enabled.
TIN3
External clock input pin for reload timer 3.
PE5
General-purpose I/O port.
SEG5
O
Segment output pin for LCD controller/driver. This function is
selected when LCD segment output is enabled.
TO3
Event output pin for reload timer 3.
PE6
General-purpose I/O port.
SEG6
TIN4
O
Segment output pin for LCD controller/driver. This function is
selected when LCD segment output is enabled.
External clock input pin for reload timer 4.
(Continued)
10
MB90378 Series
(Continued)
Pin no.
LQFP-144
Pin name
I/O
circuit
Pin status
during
reset
PE7
81
82
83
SEG7
General-purpose I/O port.
Segment output pin for LCD controller/driver. This function is
selected when LCD segment output is enabled.
O
TO4
Event output pin for reload timer 4.
PF0
General-purpose Nch Open-drain I/O port.
SEG8
Segment output pin for LCD controller/driver. This function is
selected when LCD segment output is enabled.
P
TIN5
External clock input pin for reload timer 5.
PF1
General-purpose Nch Open-drain I/O port.
COM0
COM output pin for LCD controller/driver. This function is selected when LCD COM output is enabled.
P
Port input
TO5
PF2
84
85
86
87 to 89
Function
COM1
Event output pin for reload timer 5.
General-purpose Nch Open-drain I/O port.
COM output pin for LCD controller/driver. This function is selected when LCD COM output is enabled.
P
TIN6
External clock input pin for reload timer 6.
PF3
General-purpose Nch Open-drain I/O port.
COM2
COM output pin for LCD controller/driver. This function is selected when LCD COM output is enabled.
P
TO6
Event output pin for reload timer 6.
PF4
General-purpose Nch Open-drain I/O port.
COM3
PF5 to
PF7
P
COM output pin for LCD controller/driver. This function is selected when LCD COM output is enabled.
General-purpose Nch Open-drain I/O ports.
Q
Power input
V1 to V3
42
AVCC
R
43
AVR
S
44
AVSS
R
19,55,91,
127
VSS
–
18,54,90,
126
VCC
–
Power input pin for LCD controller/driver. This function is selected when external voltage divider is enabled.
Vcc power input pin for analog circuits.
Power input
Vref+ input pin for the A/D converter. This voltage must not
exceed Vcc. Vref- is fixed to AVSS.
Vss power input pin for analog circuits.
Source
Power input
Power (0 V) input pin.
Power (3.3 V) input pin.
11
MB90378 Series
■ I/O CIRCUIT TYPE
Circuit
Type
Remarks
X1/X1A
Nch
A
Xout
Pch
Main/Sub clock (main/sub clock crystal oscillator)
• At an oscillation feedback resistor of
approximately 1 MΩ
Pch
X0/X0A
Nch
Standby mode control
B
• CMOS hysteresis input
• Pull-up resistor approximately 50 kΩ
R
CMOS hysteresis input
• CMOS hysteresis input
C
CMOS hysteresis input
R
Pch
Pull-up control
Pch
Pout
D
• CMOS output
• CMOS hysteresis input
• Selectable pull-up resistor
approximately 50 kΩ
• IOL = 4 mA
Nout
Nch
CMOS hysteresis input
Standby mode control
R
Pch
Pull-up control
Pch
E
Nch
Pout
• CMOS output
• CMOS input
• Selectable pull-up resistor
approximately 50 kΩ
• IOL = 4 mA
Nout
CMOS input
Standby mode control
Nch
F
Nch
Nout
•
•
•
•
Nch open-drain output
CMOS hysteresis input
IOL = 4 mA
5 V tolerant
CMOS hysteresis input
Standby mode control
(Continued)
12
MB90378 Series
Circuit
Type
Remarks
• Nch open-drain output
• CMOS input
• IOL = 4 mA
Pch
G
Nch
Nout
CMOS input
Standby mode control
Pch
H
Nch
Pout
• CMOS output
• CMOS input
• IOL = 4 mA
Nout
CMOS input
Standby mode control
Pch
I
Nch
Pout
• CMOS output
• CMOS hysteresis input
• IOL = 4 mA
Nout
CMOS hysteresis input
Standby mode control
Nch
J
Nch
Nout
•
•
•
•
Nch open-drain output
CMOS input
IOL = 4 mA
5 V tolerant
•
•
•
•
CMOS output
CMOS input
A/D analog input
IOL = 4 mA
CMOS input
Standby mode control
Pch
M
Nch
Pout
Nout
CMOS input
Standby mode control
Analog input
(Continued)
13
MB90378 Series
Circuit
Type
Pch
N
Nch
Remarks
Pout
Nout
•
•
•
•
CMOS output
CMOS input
D/A analog output
IOL = 4 mA
•
•
•
•
CMOS output
CMOS hysteresis input
Segment output
IOL = 4 mA
•
•
•
•
Nch open-drain output
CMOS hysteresis input
Segment output
IOL = 12 mA
•
•
•
•
Nch open-drain output
CMOS hysteresis input
LCD driving power supply
IOL = 12 mA
CMOS input
Standby mode control
Analog input
Pch
O
Nch
Pout
Nout
CMOS hysteresis input
R
Standby mode control
Segment output
Nch
P
Nch
Nout
CMOS hysteresis input
R
Standby mode control
Segment output
Nch
Q
Nch
Nout
CMOS hysteresis input
Standby mode control
LCD driving power supply
(Continued)
14
MB90378 Series
(Continued)
Circuit
Type
Remarks
• Power supply input protection circuit
Pch
R
IN
Nch
Pch
S
Analog input enable
IN
Nch
Analog input enable
Nch
T
• A/D converter reference voltage (AVR) input
pin with protection circuit
Nch
Nout
•
•
•
•
Nch open-drain output
CMOS input
IOL = 4 mA
5 V tolerant
CMOS input
Standby mode control
15
MB90378 Series
■ HANDLING DEVICES
1. Be sure that the maximum rated voltage is not exceeded (latch-up prevention).
A latch-up may occur on a CMOS IC if a voltage higher than VCC or lower than VSS is applied to an input or output
pin other than medium-to-high voltage pins. A latch-up may also occur if a voltage higher than the rating is
applied between VCC pin and VSS pin. A latch-up causes a rapid increase in the power supply current, which
can result in thermal damage to an element. Take utmost care that the maximum rated voltage is not exceeded.
When turning the power on or off to analog circuits, be sure that the analog supply voltages (AVCC, AVR) and
analog input voltage do not exceed the digital supply voltage (VCC).
2. Stabilize the supply voltages
Even within the operation guarantee range of the VCC supply voltage, a malfunction can be caused if the supply
voltage undergoes a rapid change. For voltage stabilization guidelines, the VCC ripple fluctuations (P-P value)
at commercial frequencies (50 Hz to 60 Hz) should be suppressed to "10%" or less of the reference VCC value.
During a momentary change such as when switching a supply voltage, voltage fluctuations should also be
suppressed so that the "transient fluctuation rate" is 0.1 V/ms or less.
3. Power-on
To prevent a malfunction in the built-in voltage drop circuit, secure "50 µs (between 0.2 V and 1.8 V)" or more
for the voltage rise time during power-on.
4. Treatment of unused input pins
An unused input pin may cause a malfunction if it is left open. Every unused input pin should be pulled up or down.
5. Treatment of A/D converter, and D/A converter power pin
When the A/D converter, D/A converter and comparator is not used, connect the pins as follows: AVCC = VCC,
AVSS = AVR = VSS.
6.
Notes on external clock
When an external clock is used, the oscillation stabilization wait time is required at power-on reset or at cancellation of sub-clock mode or stop mode. As shown in diagram below, when an external clock is used, connect
only the X0 pin and leave the X1 pin open.
X0
MB90378 series
Open
16
X1
MB90378 Series
7. Power supply pins
When a device has two or more VCC or VSS pins, the pins that should have equal potential are connected within
the device in order to prevent a latch-up or other malfunction. To reduce extraneous emission, to prevent a
malfunction of the strobe signal due to an increase in the group level, and to maintain the local output current
rating, connect all these power supply pins to an external power supply and ground them.
The current source should be connected to the VCC and VSS pins of the device with minimum impedance. It is
recommended that a bypass capacitor of about 0.1 µF be connected near the terminals between VCC and VSS.
8. Analog power-on sequence of A/D converter and D/A converter
The power to the A/D converter and D/A converter (AVCC, AVR) and analog inputs (AN0 to AN11) must be turned
on after the power to the digital circuits (VCC) is turned on. When turning off the power, turn off the power to the
digital circuits (VCC) after turning off the power to the A/D converter, D/A converter and analog inputs. When the
power is turned on or off, AVR should not exceed AVCC. Also, when a pin that is used for A/D analog input is also
used as an input port, the input voltage should not exceed AVCC. (The power to the analog circuits and the power
to the digital circuits can be simultaneously turned on or off.)
17
MB90378 Series
■ BLOCK DIAGRAM
X0, X0A
X1, X1A
Clock control
circuit
CPU
family core
2MC-16LX
F
Delayed interrupt generator
Reset circuit
(Watchdog timer)
RST
Other pins
VSS x 4, VCC x4, MD0 to MD2,
AVCC, AVSS, AVR
Nch open-drain I/O port 8, 9
P80/SCL1
P81/SDA1
P82/ALERT
P90/SCL2
P91/SDA2
P92/SCL3
P93/SDA3
P94/SCL4
P95/SDA4
Interrupt controller
P20 to P27
P30/PG00 to
P33/PG11
P34 to P36
P37/ADTG
Timebase timer
CMOS I/O port 0, 1, 2, 3*
I2C bus
8
8
8
8
P40/PSCK0
P41/PSDA0
P42/PSCK1
P43/PSDA1
P44/PSCK2
P45/PSDA2
P46/CLKRUN
P47/SERIRQ
8
Key-on wake-up
interrupt
6
8/16-bit PPG timer
(ch1, ch2)
6
2
7
Bus
interface
P50/GA20
P51/LFRAME
P52/LRESET
P53/LCK
P54/LAD0
P55/LAD1
P56/LAD2
P57/LAD3
GA20 control
UPI
(ch0, ch1, ch2, ch3)
Nch open-drain I/O P50
CMOS I/O P51 to P57
6
6
3
3
6
Extend external
interrupt 1 (8 channels)
3ch PS/2 interface
Serial IRQ (6 channels)
DTP/external interrupt
ch0, 1, 2, 3, 4, 5
UART
(ch1, ch2, ch3)
6
CMOS I/O port A, B, 8
Nch open-drain I/O port 4
(P47 is CMOS I/O port)
LPC Interface
P60/INT0 to
P65/INT5
P66/UCK1
P67/UO1
P70/UI1
P71/UCK2
P72/UO2
P73/UI2
P74/UCK3
P75/UO3
P76/UI3
P77/PPG1
Bridge circuit
F2MC-16LX bus
P00/KSI0 to
P07/KSI7
P10 to P17
I2C bus
(Multi-address)
8
8
PA0/EEI0 to
PA7/EEI7
8
Extend external
interrupt 2 (8 channels)
8
PB0/EEI8 to
PB7/EEI15
DTP/external interrupt
(ch6, ch7)
2
P83/INT6
P84/INT7
P85
P86
8/10-bit A/D converter
(12 channels)
12
8-bit D/A converter
(2 channels)
2
16-bit PPG
(ch2, ch3)
2
PC0/AN0 to
PC7/AN7
PD0/AN8 to
PD3/AN11
PD4/DA1
PD5/DA2
PD6/PPG2
PD7/PPG3
CMOS I/O port C, D
16-bit PPG (ch1)
CMOS I/O port 6, 7
RAM 6KB
FLASH 128 KB
Mirroring
Flash security
CMOS I/O port E
Nch open-drain I/O port F
16-bit reload timer
(ch1, ch2, ch3, ch4, ch5, ch6)
LCD controller/driver
(9SEG x 4COM)
6
6
16
PE0/TIN1/SEG0
PE1/TO1/SEG1
PE2/TIN2/SEG2
PE3/TO2/SEG3
PE4/TIN3/SEG4
PE5/TO3/SEG5
PE6/TIN4/SEG6
PE7/TO4/SEG7
PF0/SEG8/TIN5*
PF1/COM0/TO5*
PF2/COM1/TIN6*
PF3/COM2/TO6*
PF4/COM3*
PF5/V1* to
PF7/V3*
* : P00 to P07, P10 to P17, P20 to P27, P30 to P37 : With resistors that can be used as input pull-up resistors.
PF0 to PF7 : High current pins
18
MB90378 Series
■ MEMORY MAP
Single-chip mode
(with ROM mirroring function)
FFFFFFH
ROM area
Address #1
FC0000H
010000H
ROM area
(FF bank image)
Address #2
004000H
003F80H
Address #3
Peripheral area
RAM
area
Register
000100H
: Internal access memory
0000F8H
000000H
Peripheral area
: Access not allowed
Model
Address #1
Address #2
Address #3
MB90F378
FE0000H
004000H
001900H
MB90V378
FE0000H*
004000H*
003F80H
* : The MB90V378 does not contain ROM. Assume that the development tool uses these area for its ROM decode
areas.
Notes : • If single-chip mode (without ROM mirroring function) is selected, see Chapter 32, "ROM Mirroring
Function Selection Module" of the MB90378 series H/W manual.
• ROM data in the FF bank can be seen as an image in the higher 00 bank to validate the small model C
compiler. Because addresses of the 16 low-order bits in the FF bank are the same, the table in ROM
can be referenced without the "far" specification. For example, when 00C000H is accessed, the contents
of ROM at FFC000H are actually accessed. The ROM area in the FF bank exceeds 48 Kbytes, and all
areas cannot be seen as images in the 00 bank. Because ROM data from FF4000H to FFFFFFH is seen
as an image at 004000H to 00FFFFH, the ROM data table should be stored in the area from FF4000H to
FFFFFFH.
19
MB90378 Series
■ F2MC-16LX CPU PROGRAMMING MODEL
• Dedicated registers
AH
AL
Accumulator (A)
USP
User Stack Pointer (USP)
SSP
System Stack Pointer (SSP)
PS
Processor Status (PS)
PC
Program Counter (PC)
DPR
Direct Page Register (DPR)
PCB
Program Bank Register(PCB)
DTB
Data Bank Register (DTB)
USB
User Stack Bank Register (USB)
SSB
System Stack Bank Register (SSB)
ADB
Additional Data Bank Register (ADB)
8-bit
16-bit
32-bit
• General-purpose registers
CPU
Dedicated register
RAM
RAM
General-purpose
register
Accumulator
User stack pointer
Processor status
Program counter
Direct page register
Program bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register
20
Internal bus
System stack pointer
MB90378 Series
• Processor status (PS)
15
13 12
PS
RP
CCR
000
00000
-01XXXXX
7
6
5
4
3
2
1
0
-
I
S
T
N
Z
V
C
-
0
1
X
X
X
X
X
Default value
0
0
0
0
: CCR
: RP
B4 B3 B2 B1 B0
Default value
0
ILM
Default value
Default value
8 7
0
ILM2
ILM1
ILM0
0
0
0
: ILM
- : Not used
X : Undefined
21
MB90378 Series
■ I/O MAP
Register
Byte
Word
Resource name
access access
Initial value
Address
Abbreviation
000000H
PDR0
Port 0 data register
R/W
R/W
Port 0
XXXXXXXXB
000001H
PDR1
Port 1 data register
R/W
R/W
Port 1
XXXXXXXXB
000002H
PDR2
Port 2 data register
R/W
R/W
Port 2
XXXXXXXXB
000003H
PDR3
Port 3 data register
R/W
R/W
Port 3
XXXXXXXXB
000004H
PDR4
Port 4 data register
R/W
R/W
Port 4
X1111111B
000005H
PDR5
Port 5 data register
R/W
R/W
Port 5
XXXXXXX1B
000006H
PDR6
Port 6 data register
R/W
R/W
Port 6
XXXXXXXXB
000007H
PDR7
Port 7 data register
R/W
R/W
Port 7
XXXXXXXXB
000008H
PDR8
Port 8 data register
R/W
R/W
Port 8
-XXXX111B
000009H
PDR9
Port 9 data register
R/W
R/W
Port 9
--111111B
00000AH
PDRA
Port A data register
R/W
R/W
Port A
XXXXXXXXB
00000BH
PDRB
Port B data register
R/W
R/W
Port B
XXXXXXXXB
00000CH
PDRC
Port C data register
R/W
R/W
Port C
XXXXXXXXB
00000DH
PDRD
Port D data register
R/W
R/W
Port D
XXXXXXXXB
00000EH
PDRE
Port E data register
R/W
R/W
Port E
XXXXXXXXB
00000FH
PDRF
Port F data register
R/W
R/W
Port F
11111111B
000010H
DDR0
Port 0 direction register
R/W
R/W
Port 0
00000000B
000011H
DDR1
Port 1 direction register
R/W
R/W
Port 1
00000000B
000012H
DDR2
Port 2 direction register
R/W
R/W
Port 2
00000000B
000013H
DDR3
Port 3 direction register
R/W
R/W
Port 3
00000000B
000014H
DDR4
Port 4 direction register
R/W
R/W
Port 4
0-------B
000015H
DDR5
Port 5 direction register
R/W
R/W
Port 5
0000000-B
000016H
DDR6
Port 6 direction register
R/W
R/W
Port 6
00000000B
000017H
DDR7
Port 7 direction register
R/W
R/W
Port 7
00000000B
000018H
PGDR
Parity generator data register
R/W
R/W
000019H
PGCSR
Parity generator control status
register
R/W
R/W
Parity
generator
00001AH
DDRA
Port A direction register
R/W
R/W
Port A
00000000B
00001BH
DDRB
Port B direction register
R/W
R/W
Port B
00000000B
00001CH
DDRC
Port C direction register
R/W
R/W
Port C
00000000B
00001DH
DDRD
Port D direction register
R/W
R/W
Port D
00000000B
00001EH
DDRE
Port E direction register
R/W
R/W
Port E
00000000B
00001FH
DDR8
Port 8 direction register
R/W
R/W
Port 8
-0000---B
XXXXXXXXB
X------0B
(Continued)
22
MB90378 Series
Abbreviation
000020H
SMR1
Serial mode register 1
R/W
R/W
00000-00B
000021H
SCR1
Serial control register 1
R/W
R/W
00000100B
000022H
SIDR1/
SODR1
Input data register 1/
Output data register 1
R/W
R/W
000023H
SSR1
Serial status register 1
R/W
R/W
00001000B
000024H
M2CR1
Mode 2 control register 1
R/W
R/W
----1000B
000025H
CDCR1
Clock division control register 1
R/W
R/W
000026H
ENIR
Interrupt/DTP enable register
R/W
R/W
000027H
EIRR
Interrupt/DTP cause register
R/W
R/W
ELVR
Request level setting register
R/W
R/W
R/W
R/W
00002AH
ADER1
Analog input enable register 1
R/W
R/W
Port C, A/D
11111111B
00002BH
ADER2
Analog input enable register 2
R/W
R/W
Port D, A/D
----1111B
00002CH
BRSR
Bridge circuit selection register
R/W
R/W
Bridge circuit
--000000B
00002DH
ADC0
A/D control register
R/W
R/W
00002EH
ADCR0
R
R
000028H
000029H
00002FH
ADCR1
000030H
ADCS0
000031H
ADCS1
000032H
SICRL
000033H
Register
Byte
Word
Resource name
access access
Address
A/D data register
UART1
Communication
prescaler 1
Initial value
XXXXXXXXB
00--0000B
00000000B
DTP/external
interrupt
XXXXXXXXB
00000000B
00000000B
00000000B
XXXXXXXXB
8/10-bit
A/D converter
R/W
R/W
R/W
R/W
00--------B
R/W
R/W
00000000B
Serial interrupt request register
R/W
R/W
00000000B
SICRH
Serial interrupt control register
R/W
R/W
00000000B
000034H
SIFR1
Serial interrupt frame number
register 1
R/W
R/W
--000000B
000035H
SIFR2
Serial interrupt frame number
register 2
R/W
R/W
000036H
SIFR3
Serial interrupt frame number
register 3
R/W
R/W
--000000B
000037H
SIFR4
Serial interrupt frame number
register 4
R/W
R/W
--000000B
000038H
PDCRL1
⎯
R
11111111B
000039H
PDCRH1
⎯
R
11111111B
00003AH
PCSRL1
⎯
W
XXXXXXXXB
00003BH
PCSRH1
⎯
W
00003CH
PDUTL1
⎯
W
00003DH
PDUTH1
⎯
W
XXXXXXXXB
00003EH
PCNTL1
R/W
R/W
--000000B
00003FH
PCNTH1
R/W
R/W
00000000B
A/D control status register
PPG1 down counter register
PPG1 period setting register
PPG1 duty setting register
PPG1 control status register
Serial IRQ
16-bit PPG timer
(ch1)
00000-XXB
--000000B
XXXXXXXXB
XXXXXXXXB
(Continued)
23
MB90378 Series
Address
Abbreviation
000040H
PDCRL2
000041H
PDCRH2
000042H
PCSRL2
000043H
PCSRH2
000044H
PDUTL2
000045H
PDUTH2
000046H
PCNTL2
000047H
PCNTH2
000048H
PDCRL3
000049H
PDCRH3
00004AH
PCSRL3
00004BH
PCSRH3
00004CH
PDUTL3
00004DH
PDUTH3
00004EH
PCNTL3
00004FH
PCNTH3
000050H
PSCR0
000051H
Register
Byte
Word
Resource name
access access
Initial value
⎯
R
11111111B
⎯
R
11111111B
⎯
W
XXXXXXXXB
⎯
W
⎯
W
⎯
W
XXXXXXXXB
R/W
R/W
--000000B
R/W
R/W
00000000B
⎯
R
11111111B
⎯
R
11111111B
⎯
W
XXXXXXXXB
⎯
W
⎯
W
⎯
W
XXXXXXXXB
R/W
R/W
--000000B
R/W
R/W
00000000B
PS/2 interface control register 0
R/W
R/W
0--00000B
PSSR0
PS/2 interface status register 0
R/W
R/W
00000000B
000052H
PSCR1
PS/2 interface control register 1
R/W
R/W
0--00000B
000053H
PSSR1
PS/2 interface status register 1
R/W
R/W
00000000B
000054H
PSCR2
PS/2 interface control register 2
R/W
R/W
000055H
PSSR2
PS/2 interface status register 2
R/W
R/W
000056H
PSDR0
PS/2 interface data register 0
R/W
R/W
00000000B
000057H
PSDR1
PS/2 interface data register 1
R/W
R/W
00000000B
000058H
PSDR2
PS/2 interface data register 2
R/W
R/W
00000000B
000059H
PSMR
PS/2 interface mode register
R/W
R/W
----0000B
00005AH
DAT0
D/A converter data register 0
R/W
R/W
XXXXXXXXB
00005BH
DAT1
D/A converter data register 1
R/W
R/W
00005CH
DACR0
D/A control register 0
R/W
R/W
00005DH
DACR1
D/A control register 1
R/W
R/W
PPG2 down counter register
PPG2 period setting register
PPG2 duty setting register
PPG2 control status register
PPG3 down counter register
PPG3 period setting register
PPG3 duty setting register
PPG3 control status register
16-bit PPG timer
(ch2)
16-bit PPG timer
(ch3)
3-channel PS/2
interface
8-bit
D/A converter
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
0--00000B
00000000B
XXXXXXXXB
-------0B
-------0B
(Continued)
24
MB90378 Series
Initial value
Abbreviation
00005EH
UPAL1
UPI1 address register (lower)
R/W
R/W
XXXXXXXXB
00005FH
UPAH1
UPI1 address register (upper)
R/W
R/W
XXXXXXXXB
000060H
UPAL2
UPI2 address register (lower)
R/W
R/W
XXXXXXXXB
000061H
UPAH2
UPI2 address register (upper)
R/W
R/W
XXXXXXXXB
000062H
UPAL3
UPI3 address register (lower)
R/W
R/W
XXXXXXXXB
000063H
UPAH3
UPI3 address register (upper)
R/W
R/W
XXXXXXXXB
000064H
UPCL
UPI control register (lower)
R/W
R/W
00000000B
000065H
UPCH
UPI control register (upper)
R/W
R/W
-000-000B
000066H
UPDI0/
UPDO0
UPI0 data input register/
data output register
R/W
R/W
XXXXXXXXB
000067H
UPS0
UPI0 status register
R/W
R/W
000068H
UPDI1/
UPDO1
UPI1 data input register/
data output register
R/W
R/W
XXXXXXXXB
000069H
UPS1
UPI1 status register
R/W
R/W
00000000B
00006AH
UPDI2/
UPDO2
UPI2 data input register/
data output register
R/W
R/W
XXXXXXXXB
00006BH
UPS2
UPI2 status register
R/W
R/W
00000000B
00006CH
UPDI3/
UPDO3
UPI3 data input register/
data output register
R/W
R/W
XXXXXXXXB
00006DH
UPS3
UPI3 status register
R/W
R/W
00000000B
00006EH
LCR
LPC control register
R/W
R/W
-----000B
00006FH
ROMM
W
W
000070H
TMCSRL1
Timer control status register
CH1 (lower)
R/W
R/W
000071H
TMCSRH1
Timer control status register
CH1 (upper)
R/W
R/W
000072H
⎯
R/W
000073H
TMR1/
TMRD1
⎯
R/W
XXXXXXXXB
000074H
TMCSRL2
Timer control status register
CH2 (lower)
R/W
R/W
00000000B
000075H
TMCSRH2
Timer control status register
CH2 (upper)
R/W
R/W
000076H
TMR2/
TMRD2
⎯
R/W
⎯
R/W
000077H
Register
Byte
Word
Resource name
access access
Address
ROM mirroring function
selection register
16-bit timer/reload register CH1
16-bit timer/reload register CH2
LPC interface
ROM mirroring
function
00000000B
-------1B
00000000B
16-bit
reload timer
(ch1)
16-bit
reload timer
(ch2)
----0000B
XXXXXXXXB
----0000B
XXXXXXXXB
XXXXXXXXB
(Continued)
25
MB90378 Series
Byte
Word
Resource name
access access
Address
Abbreviation
000078H
TMCSRL3
Timer control status register
CH3 (lower)
R/W
R/W
000079H
TMCSRH3
Timer control status register
CH3 (upper)
R/W
R/W
00007AH
⎯
R/W
00007BH
TMR3/
TMRD3
⎯
R/W
XXXXXXXXB
00007CH
TMCSRL4
Timer control status register
CH4 (lower)
R/W
R/W
00000000B
00007DH
TMCSRH4
Timer control status register
CH4 (upper)
R/W
R/W
00007EH
TMR4/
TMRD4
⎯
R/W
00007FH
000080H
000081H
000082H
000083H
IBCRL
IBCRH
IBSRL
IBSRH
Register
16-bit timer/reload register CH3
16-bit timer/reload register CH4
XXXXXXXXB
R/W
R/W
----0000B
R/W
R/W
00000000B
2
R
R
00000000B
2
R/W
R/W
--000000B
2
XXXXXXXXB
I C bus control register (upper)
I C bus status register (lower)
I C bus status register (upper)
000085H
IADR
I2C address register
R/W
R/W
000086H
ICCR
I2C clock control register
R/W
R/W
000087H
ITCR
I2C timeout control register
ISTO
----0000B
2
I C bus control register (lower)
R/W
00008AH
XXXXXXXXB
XXXXXXXXB
R/W
ITOD
16-bit
reload timer
(ch4)
----0000B
R/W
I C data register
000089H
16-bit
reload timer
(ch3)
⎯
IDAR
ITOC
00000000B
2
000084H
000088H
Initial value
I2C
-XXXXXXXB
0-000000B
R/W
R/W
-0-00000B
2
R/W
R/W
00000000B
2
R/W
R/W
00000000B
2
R/W
R/W
00000000B
2
00000000B
I C timeout clock register
I C timeout data register
I C slave timeout register
00008BH
IMTO
I C master timeout register
R/W
R/W
00008CH
RDR0
Port 0 pull-up resistor setting
register
R/W
R/W
Port 0
00000000B
00008DH
RDR1
Port 1 pull-up resistor setting
register
R/W
R/W
Port 1
00000000B
00008EH
RDR2
Port 2 pull-up resistor setting
register
R/W
R/W
Port 2
00000000B
00008FH
RDR3
Port 3 pull-up resistor setting
register
R/W
R/W
Port 3
00000000B
000090H
to
00009DH
Prohibited area
00009EH
PACSR
00009FH
DIRR
Program address detect control
status register
R/W
R/W
Address match
detection
00000000B
Delayed interrupt cause/
clear register
R/W
R/W
Delayed
interrupt
-------0B
(Continued)
26
MB90378 Series
Byte
Word
Resource name
access access
Address
Abbreviation
Register
0000A0H
LPMCR
Low-power consumption mode
register
R/W
R/W
0000A1H
CKSCR
Clock selection register
R/W
R/W
0000A2H,
0000A3H
0000A4H
Low-power
consumption
control register
Initial value
00011000B
11111100B
Prohibited area
CKMC
Clock modulation control
register
0000A5H
to
0000A7H
R/W
R/W
Clock
modulation
-------0B
Prohibited area
0000A8H
WDTC
Watchdog control register
R/W
R/W
Watchdog timer
X-XXX111B
0000A9H
TBTC
Timebase timer control register
R/W
R/W
Timebase timer
1--00100B
0000AAH
WTC
Watch timer control register
R/W
R/W
Watch timer
10001000B
Key-on wake-up
interrupt
00000000B
0000ABH
Prohibited area
0000ACH
EICR
Wake-up interrupt control
register
R/W
R/W
0000ADH
EIFR
Wake-up interrupt flag register
R/W
R/W
0000AEH
FMCS
Flash memory control status
register
R/W
R/W
0000AFH
Flash memory
interface circuit
-------0B
000X0000B
Prohibited area
0000B0H
ICR00
Interrupt control register 00
R/W
R/W
00000111B
0000B1H
ICR01
Interrupt control register 01
R/W
R/W
00000111B
0000B2H
ICR02
Interrupt control register 02
R/W
R/W
00000111B
0000B3H
ICR03
Interrupt control register 03
R/W
R/W
00000111B
0000B4H
ICR04
Interrupt control register 04
R/W
R/W
00000111B
0000B5H
ICR05
Interrupt control register 05
R/W
R/W
00000111B
0000B6H
ICR06
Interrupt control register 06
R/W
R/W
00000111B
0000B7H
ICR07
Interrupt control register 07
R/W
R/W
0000B8H
ICR08
Interrupt control register 08
R/W
R/W
0000B9H
ICR09
Interrupt control register 09
R/W
R/W
00000111B
0000BAH
ICR10
Interrupt control register 10
R/W
R/W
00000111B
0000BBH
ICR11
Interrupt control register 11
R/W
R/W
00000111B
0000BCH
ICR12
Interrupt control register 12
R/W
R/W
00000111B
0000BDH
ICR13
Interrupt control register 13
R/W
R/W
00000111B
0000BEH
ICR14
Interrupt control register 14
R/W
R/W
00000111B
0000BFH
ICR15
Interrupt control register 15
R/W
R/W
00000111B
Interrupt
controller
00000111B
00000111B
(Continued)
27
MB90378 Series
Address
Abbreviation
Register
0000C0H
MBCRL
MI2C bus control register (lower)
2
Byte
Word
Resource name
access access
Initial value
R/W
R/W
----0000B
0000C1H
MBCRH
MI C bus control register (upper)
R/W
R/W
00000000B
0000C2H
MBSRL
MI2C bus status register (lower)
R
R
00000000B
0000C3H
MBSRH
MI2C bus status register (upper)
0000C4H
MDAR
R/W
R/W
--000000B
2
R/W
R/W
XXXXXXXXB
2
MI C alert register
R/W
R/W
----0000B
MI C data register
0000C5H
MALR
0000C6H
MADR1
MI2C address register 1
R/W
R/W
-XXXXXXXB
0000C7H
MADR2
MI2C address register 2
-XXXXXXXB
0000C8H
MADR3
R/W
R/W
2
R/W
R/W
2
MI C address register 3
Multi-address
I2 C
-XXXXXXXB
0000C9H
MADR4
MI C address register 4
R/W
R/W
0000CAH
MADR5
MI2C address register 5
R/W
R/W
-XXXXXXXB
0000CBH
MADR6
MI2C address register 6
0000CCH
MCCR
-XXXXXXXB
R/W
R/W
-XXXXXXXB
2
R/W
R/W
0-000000B
2
MI C clock control register
0000CDH
MTCR
MI C timeout control register
R/W
R/W
-0-00000B
0000CEH
MTOC
MI2C timeout clock register
R/W
R/W
00000000B
0000CFH
MTOD
MI2C timeout data register
0000D0H
MSTO
R/W
R/W
00000000B
2
R/W
R/W
00000000B
2
MI C slave timeout register
0000D1H
MMTO
MI C master timeout register
R/W
R/W
00000000B
0000D2H
SMR2
Serial mode register 2
R/W
R/W
00000-00B
0000D3H
SCR2
Serial control register 2
R/W
R/W
00000100B
0000D4H
SIDR2/
SODR2
Input data register 2/
output data register 2
R/W
R/W
0000D5H
SSR2
Status register 2
R/W
R/W
00001000B
0000D6H
M2CR2
Mode 2 control register 2
R/W
R/W
----1000B
0000D7H
CDCR2
Clock division control register 2
R/W
R/W
0000D8H
EENR1
Interrupt enable register
R/W
R/W
0000D9H
EERR1
Interrupt cause register
R/W
R/W
EELR1
Request level setting register
R/W
R/W
R/W
R/W
00000000B
0000DCH
EENR2
Interrupt enable register
R/W
R/W
00000000B
0000DDH
EERR2
Interrupt cause register
R/W
R/W
EELR2
Request level setting register
R/W
R/W
R/W
R/W
R/W
R/W
0000DAH
0000DBH
0000DEH
0000DFH
0000E0H
PDL3
Port 3 data latch register
UART2
Communication
prescaler 2
XXXXXXXXB
00--0000B
00000000B
Extend External
Interrupt 1
Extend External
Interrupt 2
XXXXXXXXB
00000000B
XXXXXXXXB
00000000B
00000000B
Port 3 data latch
00000000B
(Continued)
28
MB90378 Series
Address
Abbreviation
0000E1H
BDR
Bit data register
0000E2H
BRRL
0000E3H
Byte
Word
Resource name
access access
Register
Initial value
R/W
R/W
Bit result register (lower)
R
R
BRRH
Bit result register (upper)
R
R
XXXXXXXXB
0000E4H
SMR3
Serial mode register 3
R/W
R/W
00000-00B
0000E5H
SCR3
Serial control register 3
R/W
R/W
00000100B
0000E6H
SIDR3 /
SODR3
Input data register 3/
output data register 3
R/W
R/W
0000E7H
SSR3
Status register 3
R/W
R/W
00001000B
0000E8H
M2CR3
Mode 2 control register 3
R/W
R/W
----1000B
0000E9H
CDCR3
Clock division control register 3
R/W
R/W
0000EAH
TMCSRL5
Timer control status register
CH5 (lower)
R/W
R/W
0000EBH
TMCSRH5
Timer control status register
CH5 (upper)
R/W
R/W
0000ECH
⎯
R/W
0000EDH
TMR5/
TMRD5
⎯
R/W
XXXXXXXXB
0000EEH
LCRL
LCD control register 0
R/W
R/W
00010000B
0000EFH
LCRH
LCD control register 1
R/W
R/W
0000F0H
to
0000F4H
VRAM
LCD display RAM
R/W
-
16-bit timer/reload register CH5
0000F5H
to
0000F7H
Prohibited area
0000F8H
to
0000FFH
External area
000100H
to
0018FFH
Prohibited area (RAM area)
001FF0H
001FF1H
001FF2H
PADR0
Program address detection
register 0
R/W
R/W
Program address detection
register 1
R/W
R/W
Program address detection
register 2
R/W
R/W
----XXXXB
Bit decoder
UART3
Communication
prescaler 3
XXXXXXXXB
XXXXXXXXB
00--0000B
00000000B
16-bit
reload timer
(ch5)
LCD
controller/driver
----0000B
XXXXXXXXB
00000000B
XXXXXXXXB
XXXXXXXXB
Address match
detection
XXXXXXXXB
XXXXXXXXB
(Continued)
29
MB90378 Series
Address
Abbreviation
001FF3H
001FF4H
PADR1
001FF5H
001FF6H
to
003F7FH
Byte
Word
Resource name
access access
Register
Initial value
Program address detection
register 3
R/W
R/W
Program address detection
register 4
R/W
R/W
Program address detection
register 5
R/W
R/W
XXXXXXXXB
XXXXXXXXB
Address match
detection
XXXXXXXXB
Prohibited area
003F80H
UDRL10
UP data register 10 (lower)
R/W
R/W
XXXXXXXXB
003F81H
UDRH10
UP data register 10 (upper)
R/W
R/W
XXXXXXXXB
003F82H
UDRL11
UP data register 11 (lower)
R/W
R/W
XXXXXXXXB
003F83H
UDRH11
UP data register 11 (upper)
R/W
R/W
XXXXXXXXB
003F84H
UDRL12
UP data register 12 (lower)
R/W
R/W
XXXXXXXXB
003F85H
UDRH12
UP data register 12 (upper)
R/W
R/W
XXXXXXXXB
003F86H
UDRL13
UP data register 13 (lower)
R/W
R/W
XXXXXXXXB
003F87H
UDRH13
UP data register 13 (upper)
R/W
R/W
XXXXXXXXB
003F88H
UDRL14
UP data register 14 (lower)
R/W
R/W
XXXXXXXXB
003F89H
UDRH14
UP data register 14 (upper)
R/W
R/W
XXXXXXXXB
003F8AH
UDRL15
UP data register 15 (lower)
R/W
R/W
XXXXXXXXB
003F8BH
UDRH15
UP data register 15 (upper)
R/W
R/W
XXXXXXXXB
003F8CH
UDRL16
UP data register 16 (lower)
R/W
R/W
XXXXXXXXB
003F8DH
UDRH16
UP data register 16 (upper)
R/W
R/W
003F8EH
UDRL17
UP data register 17 (lower)
R/W
R/W
003F8FH
UDRH17
UP data register 17 (upper)
R/W
R/W
XXXXXXXXB
003F90H
UDRL18
UP data register 18 (lower)
R/W
R/W
XXXXXXXXB
003F91H
UDRH18
UP data register 18 (upper)
R/W
R/W
XXXXXXXXB
003F92H
UDRL19
UP data register 19 (lower)
R/W
R/W
XXXXXXXXB
003F93H
UDRH19
UP data register 19 (upper)
R/W
R/W
XXXXXXXXB
003F94H
UDRL1A
UP data register 1A (lower)
R/W
R/W
XXXXXXXXB
003F95H
UDRH1A
UP data register 1A (upper)
R/W
R/W
XXXXXXXXB
003F96H
UDRL1B
UP data register 1B (lower)
R/W
R/W
XXXXXXXXB
003F97H
UDRH1B
UP data register 1B (upper)
R/W
R/W
XXXXXXXXB
003F98H
UDRL1C
UP data register 1C (lower)
R/W
R/W
XXXXXXXXB
003F99H
UDRH1C
UP data register 1C (upper)
R/W
R/W
XXXXXXXXB
003F9AH
UDRL1D
UP data register 1D (lower)
R/W
R/W
XXXXXXXXB
003F9BH
UDRH1D
UP data register 1D (upper)
R/W
R/W
XXXXXXXXB
LPC data buffer
array-Extend
XXXXXXXXB
XXXXXXXXB
(Continued)
30
MB90378 Series
Byte
Word
Resource name
access access
Address
Abbreviation
Register
003F9CH
UDRL1E
UP data register 1E (lower)
R/W
R/W
003F9DH
UDRH1E
UP data register 1E (upper)
R/W
R/W
003F9EH
UDRL1F
UP data register 1F (lower)
R/W
R/W
003F9FH
UDRH1F
UP data register 1F (upper)
R/W
R/W
003FA0H
DBACLR
Data buffer array clear register
R/W
R/W
003FA1H
Initial value
XXXXXXXXB
LPC data buffer
array-Extend
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
LPC data buffer
array
-----000B
Prohibited area
003FA2H
FWR0
FLASH programming control
register 0
R/W
R/W
003FA3H
FWR1
FLASH programming control
register 1
R/W
R/W
003FA4H
SSR0
Sector switching register
R/W
R/W
003FA5H
to
003FAEH
00000000B
Dual operating
FLASH
00000000B
00XXXXX0B
Prohibited area
003FAFH
PCKCR
PLL clock control register
003FB0H
PRLL2
003FB1H
003FB2H
W
W
PLL
XXXX0000B
PPG reload register (lower)
R/W
R/W
XXXXXXXXB
PRLH2
PPG reload register (upper)
R/W
R/W
XXXXXXXXB
PRLL3
PPG reload register (lower)
R/W
R/W
XXXXXXXXB
8/16-bit
PPG timer 2
003FB3H
PRLH3
PPG reload register (upper)
R/W
R/W
003FB4H
PPGC2
PPG control register ch2
R/W
R/W
00000001B
003FB5H
PPGC3
PPG control register ch3
R/W
R/W
00000001B
003FB6H
PCS23
PPG clock control register
R/W
R/W
000000XXB
003FB7H
to
003FBFH
XXXXXXXXB
Prohibited area
003FC0H
UDRL0
UP data register 0 (lower)
R/W
R/W
XXXXXXXXB
003FC1H
UDRH0
UP data register 0 (upper)
R/W
R/W
XXXXXXXXB
003FC2H
UDRL1
UP data register 1 (lower)
R/W
R/W
XXXXXXXXB
003FC3H
UDRH1
UP data register 1 (upper)
R/W
R/W
XXXXXXXXB
003FC4H
UDRL2
UP data register 2 (lower)
R/W
R/W
003FC5H
UDRH2
UP data register 2 (upper)
R/W
R/W
003FC6H
UDRL3
UP data register 3 (lower)
R/W
R/W
XXXXXXXXB
003FC7H
UDRH3
UP data register 3 (upper)
R/W
R/W
XXXXXXXXB
003FC8H
UDRL4
UP data register 4 (lower)
R/W
R/W
XXXXXXXXB
003FC9H
UDRH4
UP data register 4 (upper)
R/W
R/W
XXXXXXXXB
LPC data buffer
array
XXXXXXXXB
XXXXXXXXB
(Continued)
31
MB90378 Series
Register
Byte
Word
Resource name
access access
Address
Abbreviation
003FCAH
UDRL5
UP data register 5 (lower)
R/W
R/W
XXXXXXXXB
003FCBH
UDRH5
UP data register 5 (upper)
R/W
R/W
XXXXXXXXB
003FCCH
UDRL6
UP data register 6 (lower)
R/W
R/W
XXXXXXXXB
003FCDH
UDRH6
UP data register 6 (upper)
R/W
R/W
XXXXXXXXB
003FCEH
UDRL7
UP data register 7 (lower)
R/W
R/W
XXXXXXXXB
003FCFH
UDRH7
UP data register 7 (upper)
R/W
R/W
XXXXXXXXB
003FD0H
UDRL8
UP data register 8 (lower)
R/W
R/W
XXXXXXXXB
003FD1H
UDRH8
UP data register 8 (upper)
R/W
R/W
XXXXXXXXB
003FD2H
UDRL9
UP data register 9 (lower)
R/W
R/W
XXXXXXXXB
003FD3H
UDRH9
UP data register 9 (upper)
R/W
R/W
XXXXXXXXB
003FD4H
UDRLA
UP data register A (lower)
R/W
R/W
XXXXXXXXB
003FD5H
UDRHA
UP data register A (upper)
R/W
R/W
XXXXXXXXB
003FD6H
UDRLB
UP data register B (lower)
R/W
R/W
XXXXXXXXB
003FD7H
UDRHB
UP data register B (upper)
R/W
R/W
XXXXXXXXB
003FD8H
UDRLC
UP data register C (lower)
R/W
R/W
XXXXXXXXB
003FD9H
UDRHC
UP data register C (upper)
R/W
R/W
XXXXXXXXB
003FDAH
UDRLD
UP data register D (lower)
R/W
R/W
XXXXXXXXB
003FDBH
UDRHD
UP data register D (upper)
R/W
R/W
003FDCH
UDRLE
UP data register E (lower)
R/W
R/W
003FDDH
UDRHE
UP data register E (upper)
R/W
R/W
XXXXXXXXB
003FDEH
UDRLF
UP data register F (lower)
R/W
R/W
XXXXXXXXB
003FDFH
UDRHF
UP data register F (upper)
R/W
R/W
XXXXXXXXB
003FE0H
DNDL0
DOWN data register 0 (lower)
R
R
XXXXXXXXB
003FE1H
DNDH0
DOWN data register 0 (upper)
R
R
XXXXXXXXB
003FE2H
DNDL1
DOWN data register 1 (lower)
R
R
XXXXXXXXB
003FE3H
DNDH1
DOWN data register 1 (upper)
R
R
XXXXXXXXB
003FE4H
DNDL2
DOWN data register 2 (lower)
R
R
XXXXXXXXB
003FE5H
DNDH2
DOWN data register 2 (upper)
R
R
XXXXXXXXB
003FE6H
DNDL3
DOWN data register 3 (lower)
R
R
XXXXXXXXB
003FE7H
DNDH3
DOWN data register 3 (upper)
R
R
XXXXXXXXB
003FE8H
DNDL4
DOWN data register 4 (lower)
R
R
XXXXXXXXB
003FE9H
DNDH4
DOWN data register 4 (upper)
R
R
XXXXXXXXB
003FEAH
DNDL5
DOWN data register 5 (lower)
R
R
XXXXXXXXB
003FEBH
DNDH5
DOWN data register 5 (upper)
R
R
XXXXXXXXB
003FECH
DNDL6
DOWN data register 6 (lower)
R
R
XXXXXXXXB
003FEDH
DNDH6
DOWN data register 6 (upper)
R
R
XXXXXXXXB
LPC data buffer
array
Initial value
XXXXXXXXB
XXXXXXXXB
(Continued)
32
MB90378 Series
(Continued)
Byte
Word
Resource name
access access
Address
Abbreviation
Register
003FEEH
DNDL7
DOWN data register 7 (lower)
R
R
XXXXXXXXB
003FEFH
DNDH7
DOWN data register 7 (upper)
R
R
XXXXXXXXB
003FF0H
DBAAL
Data buffer array address
register (lower)
R/W
R/W
003FF1H
DBAAH
Data buffer array address
register (upper)
R/W
R/W
XXXXXXXXB
00000000B
003FF2H,
003FF3H
LPC data buffer
array
Initial value
XXXXXXXXB
Prohibited area
003FF4H
TMCSRL6
Timer control status register
CH6 (lower)
R/W
R/W
003FF5H
TMCSRH6
Timer control status register
CH6 (upper)
R/W
R/W
003FF6H
16-bit timer/reload register CH6
⎯
R/W
003FF7H
TMR6/
TMRD6
⎯
R/W
XXXXXXXXB
003FF8H
PRLL0
PPG reload register (lower)
R/W
R/W
XXXXXXXXB
003FF9H
PRLH0
PPG reload register (upper)
R/W
R/W
XXXXXXXXB
003FFAH
PRLL1
PPG reload register (lower)
R/W
R/W
003FFBH
PRLH1
PPG reload register (upper)
R/W
R/W
003FFCH
PPGC0
PPG control register ch0
R/W
R/W
00000001B
003FFDH
PPGC1
PPG control register ch1
R/W
R/W
00000001B
003FFEH
PCS01
PPG clock control register
R/W
R/W
000000XXB
003FFFH
16-bit
reload timer
(ch6)
8/16-bit
PPG timer 1
----0000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Prohibited area
• Meaning of abbreviations used for reading and writing
R/W : Readable and writable
R
: Read-only
W : Write-only
• Explanation of initial values
0 : The bit is initialized to 0.
1 : The bit is initialized to 1.
X : The initial value of the bit is undefined.
- : The bit is not used. Its initial value is undefined.
• Instruction using IO addressing e.g. MOV A, io, is not supported for registers area 003F80H to 003FFFH.
33
MB90378 Series
■ INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt cause
EI2OS
support
Interrupt vector
Number
Interrupt control
register
Address
ICR
Address
Reset
×
#08
08H
FFFFDCH
⎯
⎯
INT9 instruction
×
#09
09H
FFFFD8H
⎯
⎯
Exception processing
×
#10
0AH
FFFFD4H
⎯
⎯
A/D converter conversion termination
#11
0BH
FFFFD0H
Timebase timer
#12
0CH
FFFFCCH
ICR00
0000B0H*1
UPI0 IBF/LPC reset
#13
0DH
FFFFC8H
UPI1 IBF
#14
0EH
FFFFC4H
ICR01
0000B1H*1
UPI2 IBF
#15
0FH
FFFFC0H
UPI3 IBF
#16
10H
FFFFBCH
ICR02
0000B2H*1
DTP/ext. interrupt channels 0/1 detection
#17
11H
FFFFB8H
DTP/ext. interrupt channels 2/3 detection
#18
12H
FFFFB4H
ICR03
0000B3H*1
DTP/ext. interrupt channels 4/5 detection
#19
13H
FFFFB0H
Key-on wake-up interrupt detection
#20
14H
FFFFACH
ICR04
0000B4H*1
UPI0/1/2/3 OBE
#21
15H
FFFFA8H
16-bit PPG timer 1 / 8/16-bit PPG timer 0/1
#22
16H
FFFFA4H
ICR05
0000B5H*2
PS/2 interface 0/1
#23
17H
FFFFA0H
PS/2 interface 2
#24
18H
FFFF9CH
ICR06
0000B6H*1
Watch timer
#25
19H
FFFF98H
I C transfer complete / bus error
#26
1AH
FFFF94H
ICR07
0000B7H*1
16-bit PPG timer 2/3
#27
1BH
FFFF90H
DTP/ext. interrupt channels 6/7 detection
#28
1CH
FFFF8CH
ICR08
0000B8H*1
Multi-address I2C transfer complete / bus
error
#29
1DH
FFFF88H
ICR09
0000B9H*1
Extend External Interrupt 00 to 07/08 to 15
#30
1EH
FFFF84H
I C timeout / standby wake-up
#31
1FH
FFFF80H
16-bit reload timer 1/2/5 underflow
#32
20H
FFFF7CH
ICR10
0000BAH*1
Multi-address I2C timeout / standby wake-up
#33
21H
FFFF78H
16-bit reload timer 3/4/6 underflow
#34
22H
FFFF74H
ICR11
0000BBH*1
UART1 receive
#35
23H
FFFF70H
UART1 send
#36
24H
FFFF6CH
ICR12
0000BCH*1
UART2 receive
#37
25H
FFFF68H
UART2 send
#38
26H
FFFF64H
ICR13
0000BDH*1
UART3 receive
#39
27H
FFFF60H
UART3 send
#40
28H
FFFF5CH
ICR14
0000BEH*1
Flash memory status
#41
29H
FFFF58H
Delayed interrupt generator module
#42
2AH
FFFF54H
ICR15
0000BFH*1
2
2
Priority*2
High
Low
(Continued)
34
MB90378 Series
(Continued)
×
:
:
:
:
Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal.
Cannot be used.
Can be used and support the EI2OS stop request.
Can be used.
*1 : • For peripheral functions that share the ICR register, the interrupt level will be the same.
• If the extended intelligent I/O service is to be used with a peripheral function that shares the ICR register
with another peripheral function, the service can be started by either of the function. And if EI2OS clear is
supported, both interrupt request flags for the two interrupt causes are cleared by EI2OS interrupt clear
signal. It is recommended to mask either of the interrupt request during the use of EI2OS.
• EI2OS service cannot be started multiple times simultaneously. Interrupt other than the operating interrupt
is masked during EI2OS operation. It is recommended to mask either of the interrupt requests during the
use of EI2OS.
*2 : This priority is applied when interrupts of the same level occur simultaneously.
35
MB90378 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Rating
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS + 4.0
V
AVCC
VSS − 0.3
VSS + 4.0
V
VCC ≥ AVCC *2
AVR
VSS − 0.3
VSS + 4.0
V
AVCC ≥ AVR, AVR ≥ AVSS
V1 to V3
VSS − 0.3
VSS + 4.0
V
V1 to V3 must not exceed VCC
VI1
VSS − 0.3
VSS + 4.0
V
All pins except P40 to P45,
P80 to P82, P90 to P95 *3
VI2
VSS − 0.3
VSS + 6.0
V
P40 to P45, P80 to P82, P90 to P95
VO
VSS − 0.3
VSS + 4.0
V
*3
ICLAMP
− 2.0
+ 2.0
mA
*5
Σ|ICLAMP|
⎯
20
mA
*5
IOL1
⎯
10
mA
All pins except PF0 to PF7 *4
IOL2
⎯
20
mA
PF0 to PF7 *4
IOLAV1
⎯
4
mA
All pins except PF0 to PF7
Average output current = operating
current × operating efficiency
IOLAV2
⎯
12
mA
PF0 to PF7
Average output current = operating
current × operating efficiency
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
Average output current = operating
current × operating efficiency
IOH
⎯
− 10
mA
*4
“H” level average output
current
IOHAV
⎯
−3
mA
Average output current = operating
current × operating efficiency
“H” level total maximum
output current
ΣIOH
⎯
− 100
mA
ΣIOHAV
⎯
− 50
mA
Power consumption
PD
⎯
200
mW
Operating temperature
TA
− 40
+ 85
°C
Tstg
− 55
+ 150
°C
Power supply voltage*1
A/D converter reference
input voltage*1
LCD power supply
voltage*1
1
Input voltage*
Output voltage*
1
Maximum clamp current
Total maximum clamp
current
“L” level maximum output
current
“L” level average output
current
“L” level total maximum
output current
“L” level total average
output current
“H” level maximum output
current
“H” level total average
output current
Storage temperature
Average output current = operating
current × operating efficiency
(Continued)
36
MB90378 Series
(Continued)
*1 : This parameter is based on VSS = AVSS = 0.0 V.
*2 : Set AVCC and VCC at the same voltage. Take care so that AVR does not exceed VCC + 0.3 V when the power is
turned on.
*3 : VI and VO shall never exceed VCC + 0.3 V.
*4 : The maximum output current is a peak value for a corresponding pin.
*5 : • Use within recommended operating conditions.
• Use at DC voltage (current).
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the Vcc pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting supply voltage may not be sufficient to poerate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, etc.) cannot accept
+B signal input.
• Sample recommended circuits :
• Input/output equivalent circuits
Protective diode
VCC
Pch
Limiting
resistance
+B input (0 V to 16 V)
Nch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
37
MB90378 Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V)
Parameter
Power supply voltage *2
A/D converter reference
input voltage *3
LCD power supply voltage
Operating temperature
Symbol
VCC
Value
Min
2.7 *1
Max
Unit
Remarks
3.6
V
Normal operation assurance range
VCC
1.8
3.6
V
Retains the RAM state in stop mode
AVR
0
AVCC
V
Normal operation assurance range
V1 to V3
VSS
VCC
V
V1 to V3 pins
(The optimum value is dependent on the
LCD element in use.)
TA
− 40
+ 85
°C
*1 : The operating voltage varies with the operation frequency.
*2 : Set AVCC and VCC at the same voltage.
*3 : Take care so that AVR does not exceed VCC + 0.3 V when power is turned on.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
38
MB90378 Series
3. DC Characteristics
(VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Open-drain
output pin
application
voltage
“H” level
output
voltage
“L” level
output
voltage
Value
Unit
Remarks
Min
Typ
Max
VIH
P10 to P17, P20 to P27,
P30 to P37, P46, P47,
P51 to P57, PC0 to PC7,
PD0 to PD7
0.7 VCC
⎯
VCC + 0.3
V
CMOS
input pins
VIHS
P00 to P07, P60 to P67,
P70 to P77, P83 to P86,
PA0 to PA7, PB0 to PB7,
PE0 to PE7, PF0 to PF7,
RST
0.8 VCC
⎯
VCC + 0.3
V
CMOS
hysteresis
input pins
“H” level
input voltage
“L” level
input voltage
Condition
⎯
VIHS5
P40 to P45
0.8 VCC
⎯
VSS + 5.5
V
5 V tolerant
CMOS
hysteresis
input pins
VIH5
P50,
P82
0.7 VCC
⎯
VSS + 5.5
V
5 V tolerant
CMOS
input pins
VIHSM
P80, P81,
P90 to P95
2.1
⎯
VSS + 5.5
V
SMbus
input pins
VIHM
MD0 to MD2
VCC − 0.3
⎯
VCC + 0.3
V
Mode pins
VIL
P10 to P17, P20 to P27,
P30 to P37, P46, P47,
P50 to P57, P82,
PC0 to PC7, PD0 to PD7
VSS − 0.3
⎯
0.3 VCC
V
CMOS
input pins
VILS
P00 to P07, P40 to P45,
P60 to P67, P70 to P77,
P83 to P86, PA0 to PA7,
PB0 to PB7, PE0 to PE7,
PF0 to PF7, RST
VSS − 0.3
⎯
0.2 VCC
V
CMOS
hysteresis
input pins
VILSM
P80, P81,
P90 to P95
VSS − 0.3
⎯
0.8
V
SMbus
input pins
VILM
MD0 to MD2
VSS − 0.3
⎯
VSS + 0.3
V
Mode pins
VD5
P40 to P45, P50,
P80 to P82, P90 to P95
VSS − 0.3
⎯
VSS + 5.5
V
VSS − 0.3
⎯
VCC + 0.3
V
VOH1
All port pins except
P40 to P46, P50,
P80 to P82, P90 to P95,
PF0 to PF7
VCC = 3.0 V
VCC − 0.5
IOH1 = − 4.0 mA
⎯
⎯
V
VOL1
All port pins except
PF0 to PF7
IOL1 = 4.0 mA
⎯
⎯
0.4
V
VOL2
PF0 to PF7
IOL2 = 12.0 mA
⎯
⎯
0.4
V
VD
⎯
⎯
P46, PF0 to PF7
(Continued)
39
MB90378 Series
Parameter
Symbol
Input leakage
current
(Hi-Z output
leakage current)
IIL
Open-drain
output leakage
current
Pin name
Value
Unit
Min
Typ
Max
−5
⎯
5
µA
⎯
⎯
⎯
5
µA
ICC
VCC = 3.3 V,
Internal operation
at 20 MHz
⎯
56
68
mA
ICCS
VCC = 3.3 V,
Internal operation
at 20 MHz,
In sleep mode
⎯
23
30
mA
ICCL
VCC = 3.3 V,
External 32 kHz,
Internal operation
at 8 kHz,
In sub-clock
mode,
TA = + 25 °C
⎯
23
80
µA
ICCLS
VCC = 3.3 V,
External 32 kHz,
Internal operation
at 8 kHz,
In sub-clock sleep
mode,
TA = + 25 °C
⎯
10
50
µA
ICCWAT
VCC = 3.3 V,
External 32 kHz,
Internal operation
at 8 kHz,
In watch mode,
TA = + 25 °C
⎯
1.5
30
µA
ICCT
VCC = 3.3 V,
Internal operation
at 20 MHz,
In timebase timer
mode
⎯
2.0
3
mA
VCC = 3.3 V,
In stop mode,
TA = + 25 °C
⎯
1
20
µA
⎯
10
80
pF
ILEAK
Power supply
current*
All input pins
P40 to P46, P50,
P80 to P82, P90 to P95,
PF0 to PF7
VCC
Power supply
current*
VCC
ICCH
Input
capacitance
Condition
CIN
All input pins except
VCC, AVCC, VSS, AVSS
VCC = 3.3 V,
VSS < VI < VCC
⎯
Remarks
(Continued)
40
MB90378 Series
(Continued)
Parameter
LCD divided
resistance
Symbol
Pin name
⎯
RLCD
Condition
Value
Unit
Min
Typ
Max
Between VCC and V3
at VCC = 3.3 V
100
200
400
Between V3 and V2
Between V2 and V1
Between V1 and VSS
at VCC = 3.3 V
50
100
200
⎯
⎯
5
kΩ
⎯
⎯
5
kΩ
kΩ
COM0 to COM3
output
impedance
RVCOM
SEG0 to SEG8
output
impedance
RVSEG
SEG0 to SEG8
LCD leakage
current
LLCDL
V1 to V3,
COM0 to COM3,
SEG0 to SEG8
⎯
⎯
⎯
±1
µA
Pull-up
resistance
RUP
P00 to P07,P10 to P17,
P20 to P27,P30 to P37,
RST
⎯
25
50
100
kΩ
Pull-down
resistance
RDOWN
MD2
⎯
25
50
100
kΩ
COM0 to COM3
Remarks
V1 to V3 = 3.3 V
MB90V378
only
* : The current value is preliminary value and may be subject to change for enhanced characteristics without
previous notice. The power supply current is measured with an external clock.
41
MB90378 Series
4. AC Characteristics
(1) Clock Timings
(VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Clock frequency
fCH
X0, X1
Value
Unit
Remarks
Min
Typ
Max
3
⎯
16
× 1/2 (When PLL stops)
MHz When using an
oscillation circuit
4
⎯
16
MHz
PLL × 1 When using an
oscillation circuit
4
⎯
10
MHz
PLL × 2 When using an
oscillation circuit
4
⎯
6.67
MHz
PLL × 3 When using an
oscillation circuit
4
⎯
5
MHz
PLL × 4 When using an
oscillation circuit
3
⎯
32
× 1/2 (When PLL stops)
MHz When using an external
clock
4
⎯
20
MHz
PLL × 1 When using an
external clock
4
⎯
10
MHz
PLL × 2 When using an
external clock
4
⎯
6.67
MHz
PLL × 3 When using an
external clock
4
⎯
5
MHz
PLL × 4 When using an
external clock
⎯
fCL
X0A, X1A
⎯
⎯
32.768
⎯
kHz
tHCYL
X0, X1
⎯
31.25
⎯
333
ns
tLCYL
X0A, X1A
⎯
⎯
30.5
⎯
µs
∆f
⎯
⎯
⎯
⎯
5
%
PWH
PWL
X0
⎯
5
⎯
⎯
ns
Recommend duty
ratio of 30% to 70%
PWHL
PWLL
X0A
⎯
⎯
15.2
⎯
µs
Recommend duty
ratio of 30% to 70%
Input clock rise/fall
time
tCR
tCF
X0
⎯
⎯
⎯
5
ns
External clock
operation
Internal operating
clock frequency
fCP
⎯
⎯
1.5
⎯
20
MHz Main clock operation
fLCP
⎯
⎯
⎯
8.192
⎯
kHz Sub-clock operation
tCP
⎯
⎯
50
⎯
666
ns
Main clock operation
tLCP
⎯
⎯
⎯
122.1
⎯
µs
Sub-clock operation
Clock cycle time
Frequency
fluctuation rate
locked*
Input clock pulse
width
Internal operating
clock cycle time
42
Symbol Pin name Condition
MB90378 Series
• X0, X1 clock timing
tHCYL
0.8 VCC
0.8 VCC
X0
0.8 VCC
0.2 VCC
PWH
0.2 VCC
PWL
tCF
tCR
• X0A, X1A clock timing
tLCYL
0.8 VCC
0.8 VCC
X0A
0.8 VCC
0.2 VCC
PWHL
0.2 VCC
PWLL
tCF
tCR
43
MB90378 Series
• PLL operation guarantee range
Power supply voltage VCC (V)
Relationship between machine clock frequency and power supply voltage
3.6
3.0
2.7
1.5 3 4
16
20
Machine clock fCP (MHz)
Operation guarantee range of PLL
Normal operation guarantee range
Guaranteed oscillation frequency range
Relationship between external clock frequency and machine clock frequency
Guaranteed oscillation frequency range
×4
Machine clock fCP (MHz)
20
×3
×2
×1
× 1 (PLL off)
2
16
12
8
4
1.5
3
4 5
6.67 8
10
12
16
20
24
32
External clock FC (MHz)*
* : When using a crystal oscillator or a ceramic oscillator, the maximum oscillation clock frequency is 16 MHz.
44
MB90378 Series
The AC ratings are measured for the following measurement reference voltages :
• Input signal waveform
Hysteresis input pin
0.8 VCC
0.2 VCC
• Output signal waveform
Output pin
2.4 V
0.8 V
CMOS input pin
0.7 VCC
0.3 VCC
SMbus input pin
2.1 V
0.8 V
45
MB90378 Series
(2) Reset Input Timing
(VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Reset input time
Symbol
tRSTL
Pin name
RST
Value
Condition
⎯
Unit
Remarks
Min
Max
16 tCP
⎯
ns
Normal
operation
Oscillation time of
oscillator* + 16 tCP
⎯
ms
In stop mode
and sub-clock
mode
* : Oscillation time of oscillator is the time to reach to 90% of the oscillation amplitude from stand still. In the crystal
oscillator, the oscillation time is between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time
is between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms.
Note : tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP.
• In stop mode
tRSTL
RST
0.2 VCC
X0
0.2 VCC
90% of
oscillation
amplitude
Internal operation
clock
16 tCP
Oscillation time
of oscillator
Oscillation stabilization time
Instruction execution
Internal reset
46
MB90378 Series
(3) Power-on Reset
(VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol Pin name Condition
Power supply rise time
Power supply cut-off time
tR
VCC*
tOFF
VCC*
⎯
Value
Unit
Min
Max
⎯
50
ms
1
⎯
ms
Remarks
Due to repeated
operations
* : VCC must be kept lower than 0.2 V before power-on.
Notes : • The above values are used for causing a power-on reset.
Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn
on the power supply using the above values.
• Make sure that power supply rises within the selected oscillation stabilization time. If the power supply
voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR
tOFF
2.2 V
0.2 V
0.2 V
0.2 V
VCC
Sudden changes in the power supply voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended
to raise the voltage smoothly to suppress fluctuations as shown below. In this case,
change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or fewer
per second, however, you can use the PLL clock.
VCC
It is recommended to keep the
rising speed of the supply voltage
at 50 mV/ms or slower.
1.8 V
RAM data hold
VSS
47
MB90378 Series
(4) UART1 to UART3
(VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
UCK ↓ → UO delay time
tSLOV
Valid UI → UCK ↑
tIVSH
UCK ↑ → valid UI hold time
tSHIX
Serial clock “H” pulse width
Condition
Value
Max
UCK1 to UCK3
4 tCP
⎯
ns
UCK1 to UCK3,
CL = 80 pF + 1 TTL
UO1 to UO3
for an output pin of
UCK1 to UCK3, internal shift clock
UI1 to UI3
mode
UCK1 to UCK3,
UI1 to UI3
−80
80
ns
100
⎯
ns
tCP
⎯
ns
tSHSL
UCK1 to UCK3
4 tCP
⎯
ns
Serial clock “L” pulse width
tSLSH
UCK1 to UCK3
4 tCP
⎯
ns
UCK ↓ → UO delay time
tSLOV
⎯
150
ns
Valid UI → UCK ↑
tIVSH
60
⎯
ns
UCK ↑ → valid UI hold time
tSHIX
60
⎯
ns
UCK1 to UCK3, CL = 80 pF + 1 TTL
UO1 to UO3
for an output pin of
UCK1 to UCK3, external shift clock
mode
UI1 to UI3
UCK1 to UCK3,
UI1 to UI3
Notes : • These are AC ratings in the CLK synchronous mode.
• CL is the load capacitance value connected to pins while testing.
• tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP.
48
Unit Remarks
Min
MB90378 Series
• Internal shift clock mode
tSCYC
UCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
UO
0.8 V
tIVSH
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
UI
• Internal shift clock mode
tSLSH
tSHSL
UCK
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSLOV
2.4 V
UO
0.8 V
tIVSH
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
UI
49
MB90378 Series
(5) Resources Input Timing
(VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Parameter
Symbol
Pin name
Condition
Unit Remarks
Min
Max
tTIWH
tTIWL
Timer input pulse width
⎯
TIN1 to TIN6
⎯
4 tCP
ns
Note : tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP.
0.8 VCC
0.8 VCC
TIN1 to TIN6
0.2 VCC
0.2 VCC
tTIWH
tTIWL
(6) Trigger Input Timing
(VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Input pulse width
tTRGH
tTRGL
ADTG,
INT0 to INT7,
EEI0 to EEI15,
KSI0 to KSI7
Condition
⎯
Value
Unit
Remarks
Min
Max
5 tCP
⎯
ns
Normal operation
1
⎯
µs
Stop mode
Note : tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP.
INT0 to INT7
EEI0 to EEI15
KSI0 to KSI7
0.8 VCC
0.8 VCC
0.2 VCC
tTRGH
0.7 VCC
0.2 VCC
tTRGL
0.7 VCC
ADTG
0.3 VCC
tTRGH
50
0.3 VCC
tTRGL
MB90378 Series
(7) I2C / Multi-address I2C Timing
(VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Value
Symbol Pin name
Min
Max
Unit
Remarks
Start condition output
tSTA
SCL,
SDA
tCP (m x n/2 − 1) − 20 tCP (m x n/2 − 1) + 20
ns
Master
mode
Stop condition output
tSTO
SCL,
SDA
tCP (m x n/2 + 3) - 20
tCP (m x n/2 + 3) + 20
ns
Master
mode
Start condition detect
tSTA
SCL,
SDA
tCP + 40
⎯
ns
Stop condition detect
tSTO
SCL,
SDA
tCP + 40
⎯
ns
Restart condition output
tSTASU
SCL,
SDA
Restart condition detect
tSTASU
SCL,
SDA
tCP + 40
⎯
ns
SCL output “L” width
tLOW
SCL
tCP x m x n/2 − 20
tCP x m x n/2 + 20
ns
Master
mode
SCL output “H” width
tHIGH
SCL
ns
Master
mode
SDA output delay
tDO
SDA
SDA output setup time
after interrupt
tDOSU
SDA
SCL input “L” pulse
tLOW
SCL input “H” pulse
tCP (m x n/2 + 3) − 20 tCP (m x n/2 + 3) + 20
tCP (m x n/2 + 2) − 20 tCP (m x n/2 + 2) + 20
ns
Master
mode
tCP x 3 − 20
tCP x 3 + 20
ns
tCP x m x n/2 − 20
⎯
ns
*1
tCP x 4 − 20
⎯
ns
*2
SCL
tCP x 3 + 40
⎯
ns
tHIGH
SCL
tCP + 40
⎯
ns
SDA output setup time
tSU
SDA
40
⎯
ns
SDA hold time
tHO
SDA
0
⎯
ns
Notes : • tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP.
• m is the setting bit of shift clock oscillation defined in the “ICCR register (CS4, CS3)” and “MCCR register
(CS4, CS3)”. Please refer to the MB90378 series H/W manual for details.
• n is the setting bit of shift clock oscillation defined in the “ICCR register (CS2 to CS0)” and “MCCR register
(CS2 to CS0)”. Please refer to the MB90378 series H/W manual for details.
• tDOSU is shown in the interrupt time is longer than the “L” width of SCL.
• SDA and SCL output value is specified on condition that the rise/fall time is “0 ns”.
*1 : At the stop condition or transferring of next byte.
*2 : After setting register bit IBCRH : SCC at restart.
51
MB90378 Series
• Data transmit (master/slave)
tDO
tDO
tSU
tHO
tDOSU
tDO
tDOSU
ACK
SDA
tSTASU
tSTA
tLOW
tHO
1
SCL
9
• Data receive (master/slave)
tSU
tHO
tDO
ACK
SDA
tHIGH
SCL
52
6
7
tLOW
tSTO
8
9
MB90378 Series
(8) PS/2 Interface Timing
(VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Condition
PSCK clock
cycle time
tPCYC
PSCK0 to PSCK2,
PSDA0 to PSDA2
⎯
PSCK↓ → PSDA
tPLOV
Valid PSDA →
PSCK↓
Value
Unit Remarks
Min
Typ
Max
4 tCP
⎯
⎯
ns
PSCK0 to PSCK2,
Transmission Mode
PSDA0 to PSDA2
2 tCP
⎯
⎯
ns
tPIVSH
PSCK0 to PSCK2,
PSDA0 to PSDA2
1 tCP
⎯
⎯
ns
PSCK↓ → valid
PSDA hold time
tPHIX
PSCK0 to PSCK2,
PSDA0 to PSDA2
1 tCP
⎯
⎯
ns
PSCK clock
“H” pulse width
tPHSL
PSCK0 to PSCK2,
PSDA0 to PSDA2
2 tCP
⎯
⎯
ns
PSCK clock
“L” pulse width
tPLSH
2 tCP
⎯
⎯
ns
Reception Mode
⎯
PSCK0 to PSCK2,
PSDA0 to PSDA2
Note : tCP is the internal operating clock cycle time. Refer to “(1) Clock Timings” rating for tCP.
tPCYC
PSCK0
PSCK1
PSCK2
0.8 VCC
0.8 VCC
0.2 VCC
• Transmission Mode
tPLOV
2.4 V
PSDA0
PSDA1
PSDA2
• Reception Mode
PSDA0
PSDA1
PSDA2
0.8 V
tPIVSH
tPHIX
0.8 VCC
0.2 VCC
53
MB90378 Series
(9) LPC Timing
(VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Condition
LCLK cycle time
tCYCLE
⎯
LCLK high time
tHIGH
LCLK low time
tLOW
Value
Typ
Max
⎯
30
⎯
⎯
ns
⎯
⎯
12
⎯
⎯
ns
⎯
⎯
12
⎯
⎯
ns
• LCLK AC timing
tCYCLE
tHIGH
0.7 VCC
0.3 VCC
LCLK
tLOW
54
Unit Remarks
Min
MB90378 Series
Parameter
Value
Symbol Pin name Condition
Min
Typ
Max
Unit
Output valid delay
tVAL
⎯
⎯
2
⎯
12
ns
Float to active delay
tON
⎯
⎯
2
⎯
⎯
ns
Active to float delay
tOFF
⎯
⎯
⎯
⎯
28
ns
Input setup time
tS
⎯
⎯
7
⎯
⎯
ns
Input hold time
tH
⎯
⎯
0
⎯
⎯
ns
Remarks
• LAD, LFRAME, GA20 AC timing
0.4 VCC
LCLK
tVAL
OUTPUT
Delay
tON
Tri-state
OUTPUT
tOFF
0.4 VCC
LCLK
tS
tH
INPUT
55
MB90378 Series
5. A/D Converter Electrical Characteristics
(2.7 V ≤ AVR − AVSS, VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Value
Symbol
Pin
name
Min
Typ
Max
Resolution
⎯
⎯
⎯
⎯
10
bit
Total error
⎯
⎯
⎯
⎯
± 3.0
LSB
Non-linear error
⎯
⎯
⎯
⎯
± 2.5
LSB
Differential linearity
error
⎯
⎯
⎯
⎯
± 1.9
LSB
Parameter
Zero transition
voltage
VOT
Full-scale transition
voltage
VFST
Conversion time
⎯
AN0 to
AN11
AVSS −
1.5 LSB
AVSS +
0.5 LSB
AN0 to
AN11
AVR −
3.5 LSB
AVR −
1.5 LSB
⎯
3.1
⎯
AVSS +
5.5 LSB
AVSS +
2.5 LSB
AVR +
0.5 LSB
⎯
Unit
For MB90V378
mV
For MB90F378
mV
µs
Actual value is specified as
a sum of values specified in
ADCR0 : CT1, CT0 and
ADCR0 : ST1, ST0. Be sure
that the setting value is
greater than the min value
Actual value is specified in
ADCR0 : ST1, ST0 bits. Be
sure that the setting value is
greater than the min value
Sampling period
⎯
⎯
2
⎯
⎯
µs
Analog port input
current
IAIN
AN0 to
AN11
⎯
0.1
10
µA
Analog input
voltage
VAIN
AN0 to
AN11
AVSS
⎯
AVR
V
Reference voltage
⎯
AVR
AVSS + 2.7
⎯
AVCC
V
Power supply
current
IA
⎯
1.4
6.4
mA
⎯
⎯
5
µA
⎯
94
300
µA
⎯
⎯
5
µA
⎯
⎯
4
LSB
Reference voltage
supply current
Offset between
channels
IAH
IR
IRH
—
AVCC
AVR
AN0 to
AN11
Remarks
*
*
*: The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVR = 3.0 V).
56
MB90378 Series
6. A/D Converter Glossary
Resolution : Analog changes that are identifiable with the A/D converter.
Linearity error : The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔
“00 0000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from
actual conversion characteristics.
Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the
theoretical value.
Total error : The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error/full-scale transition error and linearity error.
Total error
3FFH
3FEH
Actual conversion
value
0.5 LSB
Digital output
3FDH
{1 LSB × (N − 1) + 0.5 LSB}
004H
VNT
(Measured value)
003H
002H
001H
Actual conversion
value
Theoretical
characteristics
0.5 LSB
AVRL
AVRH
Analog input
Total error for digital output N =
1 LSB (Theoretical value) =
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVR − AVss [V]
1024
[LSB]
VOT (Theoretical value) = AVss + 0.5 LSB [V]
VFST (Theoretical value) = AVR − 1.5 LSB [V]
VNT : Voltage at a transition of digital output from (N − 1) to N
(Continued)
57
MB90378 Series
(Continued)
Differential linearity error
Linearity error
Theoretical
characteristics
3FFH
Digital output
3FDH
Actual conversion
value
{1 LSB × (N − 1)
+ VOT }
N+1
VNT
(Measured value)
004H
003H
Actual conversion
value
VFST
(Measured value)
Actual conversion
value
Digital output
3FEH
N
V (N + 1) T
(Measured value)
N−1
VNT
(Measured value)
002H
Theoretical characteristics
Actual conversion
value
N−2
001H
VOT (Measured value)
AVRL
AVRH
AVRL
Analog input
AVRH
Analog input
Linearity error of
=
digital output N
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
Differential linearity error
V (N + 1) T − VNT
=
1 LSB
of digital output N
1 LSB =
VFST − VOT
1022
[LSB]
− 1 [LSB]
[V]
VOT : Voltage at transition of digital output from “000H” to “001H”
VFST : Voltage at transition of digital output from “3FEH” to “3FFH”
58
MB90378 Series
7. Notes on Using A/D Converter
• About the external impedance of the analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely affecting
A/D conversion precision.
• Analog input circuit model
R
Analog input
Comparator
↑
During sampling : ON
C
Note : The values are reference values.
R
1.9 kΩ (Max)
MB90F378/V378
C
25 pF (Max)
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.
• The relationship between the external impedance and minimum sampling time
[External impedance = 0 kΩ to 20 kΩ]
100
20
90
18
80
70
60
50
40
30
MB90F378/V378
20
10
0
0
5
10
15
20
25
Minimum sampling time (µs)
30
35
External impedance (kΩ)
External impedance (kΩ)
[External impedance = 0 kΩ to 100 kΩ]
16
14
12
10
8
6
MB90F378/V378
4
2
0
0
1
2
3
4
5
6
7
8
Minimum sampling time (µs)
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• About errors
As |AVR − AVSS| becomes smaller, values of relative errors grow larger.
59
MB90378 Series
8. D/A Electrical Characteristics
(VCC = AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol Pin name
Value
Condition
Min
Typ
Max
Unit
Resolution
⎯
⎯
⎯
8
⎯
bit
Differential linearity error
⎯
⎯
⎯
⎯
± 0.9
LSB
Non-linearity error
⎯
⎯
⎯
⎯
± 1.5
LSB
Conversion time
⎯
⎯
⎯
0.6
⎯
µs
Analog output impedance
⎯
⎯
2.0
2.9
3.8
kΩ
IDVR
AVCC
⎯
⎯
460
µA
IDVRS
AVCC
⎯
0.1
⎯
µA
Power supply current
⎯
Remarks
*
D/A stops
* : With load capacitance is 20 pF.
9. Serial IRQ Electrical Characteristics
(VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C)
Parameter
Symbol Pin name Condition
Value
Min
Typ
Max
Unit
“H” level input voltage
VIH
⎯
⎯
0.7 VCC
⎯
VCC
V
“L” level input voltage
VIL
⎯
⎯
VSS
⎯
0.3 VCC
V
“H” level output voltage
VOH
⎯
⎯
VCC − 0.5
⎯
⎯
V
“L” level output voltage
VOL
⎯
⎯
⎯
⎯
0.4
V
Remarks
10. Flash Memory Program/Erase Characteristics
Parameter
Condition
Unit
Remarks
Min
Typ
Max
Sector erase time
(4 Kbytes sector)
⎯
0.2
0.5
s
Excludes 00H programming prior
to erasure
Sector erase time
(16 Kbytes sector)
⎯
0.5
7.5
s
Excludes 00H programming prior
to erasure
⎯
4.6
⎯
s
Excludes 00H programming prior
to erasure
⎯
32
3,600
µs
Except for the over head time of
the system
10,000
⎯
⎯
cycle
Chip erase time
TA = +25 °C
VCC = 3.0 V
Byte (8-bit width)
programing time
Program/Erase cycle
60
Value
⎯
MB90378 Series
■ EXAMPLE CHARACTERISTICS (MB90F378)
• Power Supply Current
TA = +25 [°C]
ICC [mA]
TA = +25 [°C]
ICCS [mA]
Fcin = 16 MHz
50.0
18.0
Fcin = 16 MHz
16.0
40.0
Fcin = 12 MHz
14.0
Fcin = 12 MHz
Fcin = 10 MHz
12.0
Fcin = 8 MHz
10.0
30.0
Fcin = 10 MHz
Fcin = 8 MHz
8.0
20.0
Fcin = 4 MHz
6.0
Fcin = 4 MHz
4.0
10.0
Fcin = 2 MHz
Fcin = 2 MHz
2.0
VCC [V]
0.0
2.0
ICCH [µA]
2.5
3.0
3.5
4.0
VCC [V]
0.0
2.0
2.5
3.0
3.5
4.0
TA = +25 [°C]
2.5
2.0
1.5
1.0
0.5
VCC [V]
0.0
2.5
3.0
3.5
4.0
(Continued)
61
MB90378 Series
(Continued)
VCC − VOH1 [V]
TA = +25 [°C]
VCC − VOH2 [V]
TA = +25 [°C]
0.7
2.0
0.6
1.5
0.5
VCC = 2.5 [V]
VCC = 2.5 [V]
1.0
VCC = 3.0 [V]
VCC = 3.5 [V]
VCC = 4.0 [V]
0.5
0.4
VCC = 3.0 [V]
VCC = 3.5 [V]
VCC = 4.0 [V]
0.3
0.2
0.1
IOH1 [mA]
0.0
0
−2
−4
−6
−8
−10
0
TA = +25 [°C]
VOL1 [V]
IOH2 [mA]
0.0
−2
−6
−8
−10
TA = +25 [°C]
VOL2 [V]
0.8
−4
0.3
VCC = 2.5 [V]
0.6
VCC = 3.0 [V]
VCC = 4.0 [V]
VCC = 3.5 [V]
VCC = 2.5 [V]
VCC = 3.0 [V]
VCC = 3.5 [V]
VCC = 4.0 [V]
0.2
0.4
0.1
0.2
IOL1 [mA]
0.0
0
62
2
4
6
8
10
IOL2 [mA]
0.0
0
2
4
6
8
10
MB90378 Series
■ ORDERING INFORMATION
Part number
MB90F378PFF-GE1
Package
Remarks
144-pin Plastic LQFP
(FPT-144P-M12)
63
MB90378 Series
■ PACKAGE DIMENSION
144-pin plastic LQFP
(FPT-144P-M12)
Note 1) * : These dimensions include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00±0.20(.709±.008)SQ
+0.40
+.016
*16.00 –0.10 .630 –.004 SQ
73
108
72
109
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
0~8˚
37
144
LEAD No.
1
64
0.60±0.15
(.024±.006)
36
0.40(.016)
C
"A"
2003 FUJITSU LIMITED F144024S-c-3-3
0.18±0.035
.007±.001
+0.05
0.07(.003)
M
0.145 –0.03
.006
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
+.002
–.001
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB90378 Series
MEMO
65
MB90378 Series
MEMO
66
MB90378 Series
MEMO
67
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
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For further information please contact:
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Korea
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Korea
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Tsimshatsui, Kowloon
Hong Kong
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited
Strategic Business Development Dept.
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