2.0 MB

The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13754-3E
16-bit Microcontrollers
CMOS
F2MC-16LX MB90930 Series
MB90931/931S/F931/F931S/V930-101/V930-102
■ DESCRIPTION
The MB90930 series is a family of general-purpose FUJITSU SEMICONDUCTOR 16-bit microcontrollers designed for applications such as vehicle instrument panel control.
The instruction set retains the AT architecture from the F2MC-8L and F2MC-16L families, with further refinements
including high-level language instructions, extended addressing modes, improved multiplication and division
operations (signed), and bit processing. In addition, long word processing is made possible by the inclusion of
a built-in 32-bit accumulator.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ FEATURES
• Clock
Built-in PLL clock frequency multiplication circuit.
Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and
multiplication of 1 to 8 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 32 MHz).
Operation by sub clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed.
• 16-bit input capture (8 channels)
Detects rising, falling, or both edges.
16-bit capture register × 8
The value of a 16-bit free-run timer counter is latched upon detection of an edge input to pin and an interrupt
request is generated.
• 16-bit reload timer (4 channels)
16-bit reload timer operation (select toggle output or one-shot output)
Selectable event count function
(Continued)
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2009-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.9
MB90930 Series
(Continued)
• Real time watch timer (main clock)
Operates directly from oscillator clock.
Interrupt can be generated by second/minute/hour/date counter overflow.
• PPG timer (6 channels)
Output pins (6 channels), external trigger input pin (1 channel)
Operation clock frequencies : fCP, fCP/22, fCP/24, fCP/26
• Delay interrupt
Generates interrupt for task switching.
Interrupts to CPU can be generated/cleared by software setting.
• External interrupts (8 channels)
8-channel independent operation
Interrupt source setting available : “L” to “H” edge/ “H” to “L” edge/ “L” level/ “H” level.
• 8/10-bit A/D converter (24 channels)
Conversion time : 3 μs (at fCP = 32 MHz)
External trigger activation available (P50/INT0/ADTG)
Internal timer activation available (16-bit reload timer 1)
• UART(LIN/SCI) (4 channels)
Equipped with full duplex double buffer
Clock-asynchronous or clock-synchronous serial transfer is available.
• CAN interface (1 channel).
Conforms to CAN specifications version 2.0 Part A and B.
Automatic resend in case of error.
Automatic transfer in response to remote frame.
16 prioritized message buffers for data and ID
Multiple message support
Flexible configuration for receive filter : Full bit compare/full bit mask/two partial bit masks
Supports up to 1 Mbps
CAN wakeup function (RX connected to INT0 internally)
• LCD controller/driver (32 segment × 4 common)
Segment driver and command driver with direct LCD panel (display) drive capability
• Reset on detection of low voltage/program loop
Automatic reset when low voltage is detected.
Program looping detection function
• Stepping motor controller (4 channels)
High current output for each channel × 4
Synchronized 8/10-bit PWM for each channel × 2
• Sound generator (2 channels)
8-bit PWM signal mixed with tone frequency from 8-bit reload counter.
PWM frequencies : 125 kHz, 62.5 kHz, 31.2 kHz, 15.6 kHz (at fCP = 32 MHz)
Tone frequencies : PWM frequency /2/ , divided by (reload frequency +1)
• Input/output ports
General-purpose input/output port (CMOS output) 93 ports
• Function for port input level selection
Automotive/CMOS-Schmitt
• Flash memory security function
Protects the contents of Flash memory (Flash memory product only)
2
DS07-13754-3E
MB90930 Series
■ PRODUCT LINEUP
Part number
MB90F931
MB90F931S
MB90931
MB90V930102
MB90931S
Parameter
Type
Flash memory
Mask ROM
Sub clock pins
(X0A, X1A)
ROM
PLL clock multiplier circuit ( × 1, × 2, × 3, × 4, × 6, × 8, 1/2 when PLL stopped)
Minimum instruction execution time 31.25ns (with 4 MHz oscillation clock × 8)
Yes
No
Yes
Flash memory 128 Kbytes
RAM
I/O port
No
91 ports
93 ports
30 Kbytes
91 ports
93 ports
93 ports
UART(LIN/SCI) 4 channels
1 channel
16-bit input capture
8 channels
16-bit reload timer
4 channels
16-bit free-run
timer
1 channel
Real time watch
timer
1 channel
16-bit PPG timer
6 channels
External interrupt
8 channels
8/10-bit
A/D converter
24 channels
Low-voltage/CPU
operating detection
reset
Yes
No
Stepping motor
controller
4 channels
Sound generator
2 channels
DS07-13754-3E
91 ports
32 segment × 4 common
CAN interface
Package
No
External
8 Kbytes
LIN-UART
Operating voltage
Yes
Mask ROM 128 Kbytes
LCD controller
Flash memory
security
Evaluation
F2MC-16LX CPU
CPU
System clock
MB90V930101
⎯
Yes
3.7 V to 5.5 V
4.5 V to 5.5 V
LQFP-120
PGA-299
3
MB90930 Series
■ PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LQFP-120
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
RST
MD0
MD1
MD2
DVSS
DVCC
P87/PWM2M3/AN23
P86/PWM2P3/AN22
P85/PWM1M3/AN21
P84/PWM1P3/AN20
P83/PWM2M2/AN19
P82/PWM2P2/AN18
P81/PWM1M2/AN17
P80/PWM1P2/AN16
DVSS
DVCC
P77/PWM2M1/AN15
P76/PWM2P1/AN14
P75/PWM1M1/AN13
P74/PWM1P1/AN12
P73/PWM2M0/AN11
P72/PWM2P0/AN10
P71/PWM1M0/AN09
P70/PWM1P0/AN08
DVSS
DVCC
PE2/SGO1/IN3R
P55/INT2
RSTO
P54/SGA1/IN2R
P94/V0
P95/V1
P96/V2
V3
AVCC
AVRH
P50/INT0/ADTG
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
VSS
PC0/SIN0/INT4
PC1/SOT0/INT5/IN3
PC2/SCK0/INT6/IN2
PC3/SIN1/INT7
PC4/SOT1
PC5/SCK1/TRG
PC6/PPG0/TOT1/IN7
PC7/PPG1/TIN1/IN6
PE0/TOT3/IN7R
PE1/TIN3/IN6R
P51/INT1/RX1
P52/TX1
P53/INT3
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
P30/SEG06
P31/SEG07
P32/SEG08
P33/SEG09
P34/SEG10
P35/SEG11
P36/SEG12
P37/SEG13
P40/SEG14
P41/SEG15
P42/SEG16
P43/SEG17
P92/X0A*1
P93/X1A*2
VCC
VSS
C
P44/SEG18
P45/SEG19
P46/SEG20
P47/SEG21
P90/SEG22
P91/SEG23
PD0/SIN2
PD1/SOT2
PD2/SCK2
PD3/SIN3
PD4/SOT3
PD5/SCK3
PD6/TOT2
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
P27/SEG05
P26/SEG04
P25/SEG03
P24/SEG02
P23/SEG01
P22/SEG00
COM3
COM2
COM1
COM0
P15/IN0
P14/TIN2/IN1
X0
X1
VSS
VCC
P13/PPG5
P12/TIN0/PPG4
P11/TOT0/PPG3/IN4
P10/PPG2/IN5
P07/SEG31
P06/SEG30
P05/SEG29
P04/SEG28
P03/SEG27
P02/SEG26
P01/SEG25
P00/SEG24
P57/SGA0/IN4R
P56/SGO0/FRCK/IN5R
(TOP VIEW)
*1 : The X0A pin is optional. The pin does not exist on the single system product.
*2 : The X1A pin is optional. The pin does not exist on the single system product.
(FPT-120P-M21)
4
DS07-13754-3E
MB90930 Series
■ PIN DESCRIPTIONS
Pin no.
Pin name
108
X0
107
X1
13
14
90
93
94
95
96
97
98
99
100
I/O circuit
type*1
A
102
103
High-speed oscillation input pin
High-speed oscillation output pin
X0A
B
Low-speed oscillation input pin
P92
I
General-purpose I/O port
X1A
B
Low-speed oscillation output pin
P93
I
General-purpose I/O port
RST
C
Reset input pin
P00
SEG24
P01
SEG25
P02
SEG26
P03
SEG27
P04
SEG28
P05
SEG29
P06
SEG30
P07
SEG31
F
F
F
F
F
F
F
F
P10
101
Function
PPG2
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
I
16-bit PPG ch.2 output pin
IN5
Input capture ch.5 trigger input pin
P11
General-purpose I/O port
TOT0
PPG3
I
16-bit reload timer ch.0 TOT output pin
16-bit PPG ch.3 output pin
IN4
Input capture ch.4 trigger input pin
P12
General-purpose I/O port
TIN0
PPG4
I
16-bit reload timer ch.0 TIN input pin
16-bit PPG ch.4 output pin
(Continued)
DS07-13754-3E
5
MB90930 Series
Pin no.
104
Pin name
P13
PPG5
I/O circuit
type*1
I
P14
109
TIN2
P15
IN0
General-purpose I/O port
16-bit PPG ch.5 output pin
General-purpose I/O port
I
IN1
110
Function
16-bit reload timer ch.2 TIN input pin
Input capture ch.1 trigger input pin
I
General-purpose I/O port
Input capture ch.0 trigger input pin
111
COM0
P
LCD controller/driver common output pin
112
COM1
P
LCD controller/driver common output pin
113
COM2
P
LCD controller/driver common output pin
114
COM3
P
LCD controller/driver common output pin
115
116
117
118
119
120
1
2
3
4
5
6
P22
SEG00
P23
SEG01
P24
SEG02
P25
SEG03
P26
SEG04
P27
SEG05
P30
SEG06
P31
SEG07
P32
SEG08
P33
SEG09
P34
SEG10
P35
SEG11
F
F
F
F
F
F
F
F
F
F
F
F
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
(Continued)
6
DS07-13754-3E
MB90930 Series
Pin no.
7
8
9
10
11
12
18
19
20
21
Pin name
P36
SEG12
P37
SEG13
P40
SEG14
P41
SEG15
P42
SEG16
P43
SEG17
P44
SEG18
P45
SEG19
P46
SEG20
P47
SEG21
I/O circuit
type*1
F
F
F
F
F
F
F
F
F
F
P50
37
INT0
I
60
P52
TX1
P53
INT3
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
INT0 external interrupt input pin
General-purpose I/O port
I
RX1
59
LCD controller/driver segment output pin
A/D converter external trigger input pin
P51
INT1
General-purpose I/O port
General-purpose I/O port
ADTG
58
Function
INT1 external interrupt input pin
CAN interface 1 RX input pin
I
I
General-purpose I/O port
CAN interface 1 TX output pin
General-purpose I/O port
INT3 external interrupt input pin
(Continued)
DS07-13754-3E
7
MB90930 Series
Pin no.
Pin name
I/O circuit
type*1
P54
61
SGA1
General-purpose I/O port
I
IN2R
63
P55
INT2
92
SGO0
FRCK
I
40
41
42
43
44
45
General-purpose I/O port
INT2 external interrupt input pin
General-purpose I/O port
I
Sound generator ch.0 SGO output pin
Free-run timer clock input pin
IN5R
Input capture ch.5 trigger input pin
P57
General-purpose I/O port
SGA0
I
IN4R
39
Sound generator ch.1 SGA output pin
Input capture ch.2 trigger input pin
P56
91
Function
P60
AN0
P61
AN1
P62
AN2
P63
AN3
P64
AN4
P65
AN5
P66
AN6
Sound generator ch.0 SGA output pin
Input capture ch.4 trigger input pin
H
H
H
H
H
H
H
General-purpose I/O port
A/D converter input pin
General-purpose I/O port
A/D converter input pin
General-purpose I/O port
A/D converter input pin
General-purpose I/O port
A/D converter input pin
General-purpose I/O port
A/D converter input pin
General-purpose I/O port
A/D converter input pin
General-purpose I/O port
A/D converter input pin
(Continued)
8
DS07-13754-3E
MB90930 Series
Pin no.
46
Pin name
P67
AN7
I/O circuit
type*1
H
P70
67
PWM1P0
L
L
General-purpose output-only port
L
AN10
PWM2M0
General-purpose output-only port
L
AN11
PWM1P1
General-purpose output-only port
L
AN12
PWM1M1
General-purpose output-only port
L
AN13
PWM2P1
General-purpose output-only port
L
AN14
PWM2M1
General-purpose output-only port
L
AN15
PWM1P2
General-purpose output-only port
L
AN16
PWM1M2
AN17
Stepping motor controller ch.2 output pin
A/D converter input pin
P81
78
Stepping motor controller ch.1 output pin
A/D converter input pin
P80
77
Stepping motor controller ch.1 output pin
A/D converter input pin
P77
74
Stepping motor controller ch.1 output pin
A/D converter input pin
P76
73
Stepping motor controller ch.1 output pin
A/D converter input pin
P75
72
Stepping motor controller ch.0 output pin
A/D converter input pin
P74
71
Stepping motor controller ch.0 output pin
A/D converter input pin
P73
70
Stepping motor controller ch.0 output pin
A/D converter input pin
P72
PWM2P0
Stepping motor controller ch.0 output pin
General-purpose output-only port
AN09
69
A/D converter input pin
A/D converter input pin
P71
PWM1M0
General-purpose I/O port
General-purpose output-only port
AN08
68
Function
General-purpose output-only port
L
Stepping motor controller ch.2 output pin
A/D converter input pin
(Continued)
DS07-13754-3E
9
MB90930 Series
Pin no.
Pin name
I/O circuit
type*1
P82
79
PWM2P2
General-purpose output-only port
L
AN18
PWM2M2
General-purpose output-only port
L
AN19
PWM1P3
General-purpose output-only port
L
AN20
PWM1M3
General-purpose output-only port
L
AN21
PWM2P3
General-purpose output-only port
L
AN22
PWM2M3
General-purpose output-only port
L
AN23
22
23
31
32
33
34
P90
SEG22
P91
SEG23
P94
V0
P95
V1
P96
V2
V3
SIN0
INT4
Stepping motor controller ch.3 output pin
A/D converter input pin
F
F
G
G
G
⎯
PC0
48
Stepping motor controller ch.3 output pin
A/D converter input pin
P87
84
Stepping motor controller ch.3 output pin
A/D converter input pin
P86
83
Stepping motor controller ch.3 output pin
A/D converter input pin
P85
82
Stepping motor controller ch.2 output pin
A/D converter input pin
P84
81
Stepping motor controller ch.2 output pin
A/D converter input pin
P83
80
Function
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver segment output pin
General-purpose I/O port
LCD controller/driver reference power supply pin
General-purpose I/O port
LCD controller/driver reference power supply pin
General-purpose I/O port
LCD controller/driver reference power supply pin
LCD controller/driver reference power supply pin
General-purpose I/O port
J
UART ch.0 serial data input pin
INT4 external interrupt input pin
(Continued)
10
DS07-13754-3E
MB90930 Series
Pin no.
Pin name
I/O circuit
type*1
PC1
49
50
51
SOT0
INT5
General-purpose I/O port
I
54
55
PC2
General-purpose I/O port
SCK0
INT6
I
25
26
27
UART ch.0 serial clock I/O pin
INT6 external interrupt input pin
IN2
Input capture ch.2 trigger input pin
PC3
General-purpose I/O port
SIN1
J
PC4
SOT1
SCK1
UART ch.1 serial data input pin
INT7 external interrupt input pin
I
General-purpose I/O port
UART ch.1 serial data output pin
General-purpose I/O port
I
UART ch.1 serial clock I/O pin
TRG
16-bit PPG ch.0 to ch.5 external trigger input pin
PC6
General-purpose I/O port
PPG0
TOT1
I
16-bit PPG ch.0 output pin
16-bit reload timer ch.1 TOT output pin
IN7
Input capture ch.7 trigger input pin
PC7
General-purpose I/O port
PPG1
TIN1
I
IN6
24
INT5 external interrupt input pin
Input capture ch.3 trigger input pin
PC5
53
UART ch.0 serial data output pin
IN3
INT7
52
Function
PD0
SIN2
PD1
SOT2
PD2
SCK2
PD3
SIN3
16-bit PPG ch.1 output pin
16-bit reload timer ch.1 TIN input pin
Input capture ch.6 trigger input pin
J
I
F
J
General-purpose I/O port
UART ch.2 serial data input pin
General-purpose I/O port
UART ch.2 serial data output pin
General-purpose I/O port
UART ch.2 serial clock I/O pin
General-purpose I/O port
UART ch.3 serial data input pin
(Continued)
DS07-13754-3E
11
MB90930 Series
(Continued)
Pin no.
28
29
30
Pin name
PD4
SOT3
PD5
SCK3
PD6
TOT2
I/O circuit
type*1
I
F
I
PE0
56
57
64
TOT3
Function
General-purpose I/O port
UART ch.3 serial data output pin
General-purpose I/O port
UART ch.3 serial clock I/O pin
General-purpose I/O port
16-bit reload timer ch.2 TOT output pin
General-purpose I/O port
I
16-bit reload timer ch.3 TOT output pin
IN7R
Input capture ch.7 trigger input pin
PE1
General-purpose I/O port
TIN3
I
16-bit reload timer ch.3 TIN input pin
IN6R
Input capture ch.6 trigger input pin
PE2
General-purpose I/O port
SGO1
I
IN3R
Sound generator ch.1 SGO output pin
Input capture ch.3 trigger input pin
62
RSTO
N
Internal reset signal output pin
65, 75, 85
DVCC
⎯
Power supply input pins dedicated for high current output buffer
66, 76, 86
DVSS
⎯
Power supply GND pins dedicated for high current output buffer
35
AVCC
⎯
A/D converter dedicated power supply input pin
38
AVSS
⎯
A/D converter dedicated power supply GND pin
36
AVRH
⎯
A/D converter Vref+ input pin. Vref- is fixed to AVSS.
89
MD0
D
Mode setting input pin. Connect to VCC pin.
88
MD1
D
Mode setting input pin. Connect to VCC pin.
87
MD2
D/E*2
Mode setting input pin. Connect to VSS pin.
17
C
⎯
External capacitor pin.
Connect a 0.1 μF capacitor between this pin and the VSS pin.
15, 105
VCC
⎯
Power supply input pins
16, 47, 106
VSS
⎯
GND power supply pins
*1 : For I/O circuit type, refer to “ ■ I/O CIRCUIT TYPE”.
*2 : The I/O circuit type is D for Flash memory products/Mask ROM products and E for evaluation products.
12
DS07-13754-3E
MB90930 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
X1
XOUT
High-speed oscillation pin
(Flash memory product, Mask ROM
product)
Oscillation feedback resistance :
approx. 1 MΩ
X0
Standby control signal
X1
Xout
High-speed oscillation pin
(Evaluation product)
Oscillation feedback resistance :
approx. 1 MΩ
X0
Standby control signal
B
X1A
Xout
low-speed oscillation pin
Oscillation feedback resistance :
approx. 10 MΩ
X0A
Standby control signal
C
CMOS hysteresis input
Input-only pin (with pull-up resistance)
• Attached pull-up resistor :
approx. 50 kΩ
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
CMOS hysteresis input
Input-only pin
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
Pull-up resistor
D
Note: The MD2 pin of the Flash
memory products uses this
circuit type.
(Continued)
DS07-13754-3E
13
MB90930 Series
Type
Circuit
E
CMOS hysteresis input
Pull-down resistor
Remarks
Input-only pin (with pull-down
resistance)
• Attached pull-down resistance :
approx. 50 kΩ
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
Note: The MD2 pin of the Mask ROM
products and the evaluation
products uses this circuit type.
F
P-ch
Pout
N-ch
Nout
LCD input
LCD output common generalpurpose port
• CMOS output
(IOH/IOL = ± 4 mA)
• Hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
CMOS hysteresis input
Standby control signal or
LCD input enable signal
Automotive input
Standby control signal or
LCD input enable signal
G
P-ch
Pout
N-ch
Nout
LCDC reference power supply
input
LCDC reference power supply common general-purpose port
• CMOS output (IOH/IOL = ± 4 mA)
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
CMOS hysteresis input
Standby control signal or
LCD output switching signal
Automotive input
Standby control signal or
LCD output switching signal
(Continued)
14
DS07-13754-3E
MB90930 Series
Type
Circuit
H
P-ch
Pout
N-ch
Nout
Analog input
Remarks
A/D converter input common
general-purpose port
• CMOS output
(IOH/IOL = ± 4 mA)
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
CMOS hysteresis input
Standby control signal or
analog input enable signal
Automotive input
Standby control signal or
analog input enable signal
I
P-ch
Pout
N-ch
Nout
General-purpose port
• CMOS output (IOH/IOL = ± 4 mA)
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
CMOS hysteresis input
Standby control signal
Automotive input
Standby control signal
J
P-ch
Pout
N-ch
Nout
CMOS hysteresis input
Standby control signal
General-purpose port (serial input)
• CMOS output (IOH/IOL = ± 4 mA)
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• CMOS input (SIN)
(VIH/VIL = 0.7 VCC/0.3 VCC)
• Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
Automotive input
Standby control signal
CMOS input (SIN)
Standby control signal
(Continued)
DS07-13754-3E
15
MB90930 Series
Type
Circuit
Remarks
K
P-ch
Pout
N-ch
Nout
Analog output
CMOS hysteresis input
Standby control signal or
analog input enable signal
A/D converter input common general-purpose port (serial input)
• CMOS output (IOH/IOL = ± 4 mA)
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• CMOS input (SIN)
(VIH/VIL = 0.7 VCC/0.3 VCC)
• Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
Automotive input
Standby control signal or
analog input enable signal
CMOS input (SIN)
Standby control signal or
analog input enable signal
L
P-ch
N-ch
Pout
High current
Nout
A/D converter input common and
high current output port (SMC pin)
CMOS output (IOH/IOL = ± 30 mA)
Analog input
(Continued)
16
DS07-13754-3E
MB90930 Series
(Continued)
Type
Circuit
Remarks
M
P-ch
Pout
N-ch
Nout
LCDC output
CMOS hysteresis input
Standby control signal or
LCDC output switching signal
LCDC output common generalpurpose port (serial input) )
• CMOS output (IOH/IOL = ± 4 mA)
• CMOS hysteresis input
(VIH/VIL = 0.8 VCC/0.2 VCC)
• CMOS input (SIN)
(VIH/VIL = 0.7 VCC/0.3 VCC)
• Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
Automotive input
Standby control signal or
LCDC output switching signal
CMOS input (SIN)
Standby control signal or
LCDC output switching signal
N
N-ch open-drain pin
IOL = 4 mA
Flash / Mask product
Evaluation product
P-ch
Nout
N-ch
N-ch
Nout
O
Automotive input
P
Input-only pin
Automotive input
(VIH/VIL = 0.8 VCC/0.5 VCC)
LCDC output pin (COM pin)
P-ch
LCDC output
N-ch
DS07-13754-3E
17
MB90930 Series
■ HANDLING DEVICES
• Strictly observe maximum rated voltages (preventing latch-up)
In CMOS IC devices, a condition known as latch-up may occur if voltages higher than VCC or lower than VSS are
applied to input or output pins other than medium or high withstand voltage pins, or if the voltage applied between
VCC and VSS pins exceeds the rated voltage level. If a latch-up occurs, the power supply current may increase
dramatically and may destroy semiconductor elements. When using semiconductor devices, always take sufficient care to avoid exceeding maximum ratings.
When the analog system power supply is switched on or off, be careful not to apply the analog power supply
(AVCC, AVRH), the analog input voltages and the power supply voltage for the high current output buffer pins
(DVCC) in excess of the digital power supply voltage (VCC).
Once the digital power supply voltage (VCC) has been disconnected, the analog power supply (AVCC, AVRH) and
the power supply voltage for the high current output buffer pins (DVCC) may be turned on in any sequence.
• Supply voltage stabilization
Rapid fluctuations in the power supply voltage can cause malfunctions even if the Vcc power supply voltage
remains within the warranted operating range. It is recommended that the power supply be stabilized such that
ripple fluctuations (P-P value) at commercial frequencies (50 Hz/60 Hz) be limited to within 10% of the standard
VCC value, and that transient fluctuations due to power supply switching, etc. be limited to a rate of 0.1 V/ms or less.
• Precautions when turning the power on
In order to prevent the built-in step-down circuits from malfunctioning, the time taken for the voltage to rise
(0.2 V to 2.7 V) during power-on should be less than 50 μs.
• Handling unused pins
If unused input pins are left open, they may cause malfunctions or latch-up which may lead to permanent damage
to the semiconductor. Unused input pins should therefore be pulled up or pulled down through a resistor of at
least 2 kΩ.
Unused input/output pins may be set to the output state and left open, or set to the input state and connected
to a pull-up or pull-down resistance of 2 kΩ or more.
• Handling A/D converter power supply pins
Even if the A/D converter is not used, the power supply pins should be connected such as AVCC = VCC, and
AVSS = AVRH = VSS.
• Notes on using an external clock
Even when an external clock is used, an oscillation stabilization wait time is required following power-on reset
or release from sub clock mode or stop mode. Furthermore, only the X0A pin should be driven when an external
clock is used, with the X1A pin open as shown in the following diagram. Do not use high-speed oscillation pins
(X0 and X1) for external clock input.
X0A
OPEN
X1A
MB90930 Series
Sample external clock connection
18
DS07-13754-3E
MB90930 Series
• Notes on operating in PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off while the PLL clock mode is selected, a selfoscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, FUJITSU
SEMICONDUCTOR will not guarantee results of operations if such failure occurs.
• Crystal oscillator circuit
Noise around the X0/X1 may cause this device to operate abnormally. Make sure to provide bypass capacitors
via shortest distance from X0, X1 pins, crystal oscillator (or ceramic oscillator) and ground lines, and make sure,
to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits while you design a
printed circuit board.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
Please ask each crystal maker to evaluate the oscillational characteristics of the crystal and this device.
• Power supply pins
Devices including multiple VCC or VSS pins are designed such that pins that need to be at the same potential
are interconnected internally to prevent malfunctions such as latch-up. To reduce unnecessary radiation, prevent
malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output
current, be sure to externally connect the VCC and VSS pins to the power supply and ground respectively.
Always connect all of the VCC pins to the same potential and all of the VSS pins to ground as shown in the
following diagram. The device will not operate correctly if multiple VCC or VSS pins are connected to different
voltages, even if those voltages are within the guaranteed operating ranges.
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
Power supply input pins (Vcc/Vss)
In addition, care must be given to connecting the VCC and VSS pins of this device to the current supply source
with as low impedance as possible. It is recommended that a 1.0 μF bypass capacitor be connected between
the VCC and VSS pins as close to the pins as possible.
DS07-13754-3E
19
MB90930 Series
• Sequence for connecting the A/D converter power supply and analog inputs
The A/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN23) must be applied after the digital
power supply (VCC) is switched on. When turning the power off, the A/D converter power supply and analog
inputs must be disconnected before the digital power supply is switched off (VCC). Ensure that AVRH does not
exceed AVcc during either power-on or power-off. Even when pins which double as analog input pins are used
as input ports, be sure that the input voltage does not exceed AVCC (turning on/off the analog and digital power
supplies simultaneously is acceptable).
• Handling the power supply for high-current output buffer pins (DVCC, DVSS)
• Flash memory products/Mask ROM products (MB90F931/MB90F931S/MB90931/MB90931S)
In the Flash memory products/Mask ROM products, the power supply for the high-current output buffer pins
(DVCC, DVSS) is isolated from the digital power supply (VCC). Therefore, DVcc can be set to a higher voltage
than Vcc. If the power supply for the high-current output buffer pins (DVCC, DVSS) is supplied before the digital
power supply (VCC), however, care needs to be taken because it is possible that the port 7 or port 8 stepping
motor outputs may momentarily output an “H” or “L” level during the DVcc rise. In order to prevent this, connect
the digital power supply (VCC) prior to connecting the power supply for the high-current output buffer pins.
Even when the high-current output buffer pins are used as general-purpose ports, power should be supplied
to the power supply pins for the high-current output buffer pins (DVCC, DVSS).
• Evaluation product (MB90V930-102/MB90V930-101)
In the evaluation products, the power supply for the high-current output buffer pins (DVCC, DVSS) is not isolated
from the digital power supply (VCC). Therefore, DVcc must be set to a lower voltage than Vcc. The power supply
for the high-current output buffer pins (DVCC, DVSS) must always be applied after the digital power supply
(VCC) has been connected, and disconnected before the digital power supply (Vcc) is disconnected (the power
supply for the high-current output buffer pins may also be connected and disconnected simultaneously with
the digital power supply).
Even when the high-current output buffer pins are used as general-purpose ports, power should be supplied
to the power supply pins for the high-current output buffer pins (DVCC, DVSS).
• Pull-up/pull-down resistors
MB90930 series does not support internal pull-up/pull-down resistors. Use external components as necessary.
• Precautions when not using a sub clock signal
If the X0A and X1A pins are not connected to an oscillator, apply a pull-down resistance to the X0A pin and
leave the X1A pin open.
• Flash memory security function
A security bit is located within the Flash memory region. The security function is activated by writing the protection
code 01H to the security bit.
Do not write the value 01H to this address if you are not using the security function.
Please refer to following table for the address of the security bit.
MB90F931
MB90F931S
20
Flash memory size
Address for security bit
Built-in 1 Mbit Flash Memory
FE0001H
DS07-13754-3E
MB90930 Series
• Serial communication
In serial communication, reception of wrong data may occur due to noise or other causes. Therefore, design a printed circuit board to prevent noise from occurring. Taking account of the reception of wrong data, detect errors by
measures such as adding a checksum to the end of data. If an error is detected, retransmit the data.
• Characteristic difference between flash device and mask ROM device
In the flash device and the mask ROM device, the electrical characteristic including current consumption, ESD,
latch-up, the noise characteristic, and oscillation characteristic, etc. is different according to the difference between
the chip layout and the memory structure.
Reconfirm the electrical characteristic when the product is replaced by another product of the same series.
DS07-13754-3E
21
MB90930 Series
■ BLOCK DIAGRAM
Clock control circuit
CPU
F2MC-16LX core
Watchdog timer
Time-base timer
Watch timer
(for sub clock)
Interrupt controller
Low-voltage reset
Sound generator 0
Sound generator 1
CPU operation
detection reset
CAN controller 1
External interrupt
(8 channels)
16-bit PPG timer 0
16-bit PPG timer 1
16-bit PPG timer 2
16-bit PPG timer 3
16-bit PPG timer 4
16-bit PPG timer 5
16-bit reload timer 0
16-bit reload timer 1
16-bit reload timer 2
16-bit reload timer 3
Stepping motor controller 1
Stepping motor controller 2
F2MC-16LX BUS
LIN-UART 0
Prescaler 0
LIN-UART 1
Prescaler 1
LIN-UART 2
Prescaler 2
LIN-UART 3
Prescaler 3
Stepping motor controller 0
Stepping motor controller 3
A/D converter
(24 channels)
LCD controller/driver
(32 SEG/4 COM)
RAM
(8 Kbytes)*
Flash / ROM
(128 Kbytes)*
Real-time watch timer
16-bit ICU 0 (2 channels)
16-bit ICU 1 (2 channels)
16-bit ICU 2 (2 channels)
16-bit ICU 3 (2 channels)
16-bit free-run timer
* : Flash memory products/Mask ROM products.
22
DS07-13754-3E
MB90930 Series
■ MEMORY MAP
MB90V930-102/
MB90V930-101
000000H
MB90F931/MB90F931S
MB90931/MB90931S
000000H
Peripheral area
0000F0H
Peripheral area
0000F0H
000100H
000100H
Register
RAM area
(13.5 Kbytes)
003700H
Register
002100H
RAM area
(8 Kbytes)
003700H
Peripheral area
004000H
Peripheral area
004000H
RAM area
(16 Kbytes)
008000H
008000H
ROM area
(FF bank image)
ROM area
(FF bank image)
010000H
010000H
F80000H
ROM decoding area
FFFFFFH
FE0000H
FFFFFFH
Flash / ROM area
(128 Kbytes)
: Internal access prohibited
Note: To select models without the ROM mirror function, refer to the “ROM Mirror Function Selection Module” in
Hardware Manual. The image of the ROM data in the FF bank appears at the top of the 00 bank, in order
to enable efficient use of small C compiler models. The lower 16-bits of the FF bank addresses are allocated
to the same addresses as the lower 16-bits of the 00 bank, making it possible to reference tables in ROM
without declaring the “far” modifier with the pointers. For example, when an access is made to the address
00C000H, the actual address to be accessed is FFC000H in ROM. Because the size of the FF bank ROM
area exceeds 32 Kbytes, it is not possible to view the entire region in the 00 bank image. Therefore because
the ROM data from FF8000H to FFFFFFH appears in the image from 008000H to 00FFFFH, it is recommended
that ROM data tables be stored in the area from FF8000H to FFFFFFH.
DS07-13754-3E
23
MB90930 Series
■ I/O MAP
Address
Register name
Symbol
Read/write
Resource name
Initial value
000000H Port 0 data register
PDR0
R/W
Port 0
XXXXXXXXB
000001H Port 1 data register
PDR1
R/W
Port 1
XXXXXXXXB
000002H Port 2 data register
PDR2
R/W
Port 2
XXXXXXXXB
000003H Port 3 data register
PDR3
R/W
Port 3
XXXXXXXXB
000004H Port 4 data register
PDR4
R/W
Port 4
XXXXXXXXB
000005H Port 5 data register
PDR5
R/W
Port 5
XXXXXXXXB
000006H Port 6 data register
PDR6
R/W
Port 6
XXXXXXXXB
000007H Port 7 data register
PDR7
R/W
Port 7
XXXXXXXXB
000008H Port 8 data register
PDR8
R/W
Port 8
XXXXXXXXB
000009H Port 9 data register
PDR9
R/W
Port 9
XXXXXXXXB
00000AH,
00000BH
(Disabled)
00000CH Port C data register
PDRC
R/W
Port C
XXXXXXXXB
00000DH Port D data register
PDRD
R/W
Port D
XXXXXXXXB
00000EH Port E data register
PDRE
R/W
Port E
XXXXXXXXB
00000FH
(Disabled)
000010H Port 0 direction register
DDR0
R/W
Port 0
00000000B
000011H Port 1 direction register
DDR1
R/W
Port 1
XX000000B
000012H Port 2 direction register
DDR2
R/W
Port 2
000000XXB
000013H Port 3 direction register
DDR3
R/W
Port 3
00000000B
000014H Port 4 direction register
DDR4
R/W
Port 4
00000000B
000015H Port 5 direction register
DDR5
R/W
Port 5
00000000B
000016H Port 6 direction register
DDR6
R/W
Port 6
00000000B
000017H Port 7 direction register
DDR7
R/W
Port 7
00000000B
000018H Port 8 direction register
DDR8
R/W
Port 8
00000000B
000019H Port 9 direction register
DDR9
R/W
Port 9
X0000000B
00001AH Analog input enable
ADER6
R/W
Port 6, A/D
11111111B
00001BH Analog input enable
ADER7
R/W
Port7, A/D
11111111B
00001CH Port C direction register
DDRC
R/W
Port C
00000000B
00001DH Port D direction register
DDRD
R/W
Port D
X0000000B
00001EH Port E direction register
DDRE
R/W
Port E
XXXXX000B
00001FH Analog input enable
ADER8
R/W
Port8, A/D
11111111B
000020H Lower A/D control status register
ADCS0
R/W
000021H Higher A/D control status register
ADCS1
R/W
000022H Lower A/D data register
ADCR0
R
000023H Higher A/D data register
ADCR1
R
000XXXX0B
A/D converter
0000000XB
00000000B
XXXXXX00B
(Continued)
24
DS07-13754-3E
MB90930 Series
Address
000024H
000025H
000026H
000027H
Register name
Compare clear register
Timer data register
Symbol
Read/write
CPCLR
Initial value
R/W
XXXXXXXXB
R/W
XXXXXXXXB
R/W
TCDT
Resource name
R/W
16-bit
free-run timer
00000000B
00000000B
000028H Lower timer control status register
TCCSL
R/W
00000000B
000029H Higher timer control status register
TCCSH
R/W
01X00000B
00002AH Lower PPG0 control status register
PCNTL0
R/W
00002BH Higher PPG0 control status register
PCNTH0
R/W
00002CH Lower PPG1 control status register
PCNTL1
R/W
00002DH Higher PPG1 control status register
PCNTH1
R/W
00002EH Lower PPG2 control status register
PCNTL2
R/W
00002FH Higher PPG2 control status register
PCNTH2
R/W
000030H External interrupt enable
ENIR
R/W
000031H External interrupt request
EIRR
R/W
000032H Lower external interrupt level
ELVRL
R/W
000033H Higher external interrupt level
ELVRH
R/W
00000000B
000034H Serial mode register 0
SMR0
R/W, W
00000000B
000035H Serial control register 0
SCR0
R/W, W
00000000B
000036H Reception/transmission data register 0
RDR0/
TDR0
R/W
00000000B
000037H Serial status register 0
SSR0
R/W, R
ECCR0
R/W, R
000039H Extended status control register 0
ESCR0
R/W
00000100B
00003AH Baud rate generator register 00
BGR00
R/W
00000000B
00003BH Baud rate generator register 01
BGR01
R/W, R
00000000B
000038H
Extended communication control
register 0
00003CH
to
000047H
000048H Input capture input select register
16-bit PPG0
16-bit PPG1
16-bit PPG2
00000000B
00000001B
00000000B
00000001B
00000000B
00000001B
00000000B
External interrupt
UART
(LIN/SCI) 0
00000000B
00000000B
00001000B
000000XXB
(Disabled)
ICISR
000049H
(Disabled)
00004AH
to
00004FH
(Disabled)
R/W
Input capture
0/1/2/3/4/5/6/7
00000000B
(Continued)
DS07-13754-3E
25
MB90930 Series
Address
Symbol
Read/write
000050H Lower timer control status register 0
TMCSR0L
R/W
000051H Higher timer control status register 0
TMCSR0H
R/W
TMR0/
TMRLR0
R/W
000054H Lower timer control status register 1
TMCSR1L
R/W
000055H Higher timer control status register 1
TMCSR1H
R/W
TMR1/
TMRLR1
R/W
000058H LCD output control register 1
LOCR1
R/W
000059H LCD output control register 2
LOCR2
R/W
00005AH Lower sound control register 0
SGCRL0
R/W
00000000B
00005BH Higher sound control register 0
SGCRH0
R/W
0XXXX100B
00005CH Frequency data register 0
SGFR0
R/W
00005DH Amplitude data register 0
SGAR0
R/W
00005EH Decrement grade register 0
SGDR0
R/W
XXXXXXXXB
00005FH Tone count register 0
SGTR0
R/W
XXXXXXXXB
IPCP0
R
000052H
000053H
000056H
000057H
000060H
000061H
000062H
000063H
000064H
000065H
000066H
Register name
Timer register 0/reload register 0
Timer register 1/reload register 1
Input capture register 0
Resource name
00000000B
16-bit reload timer XXX10000B
0
XXXXXXXXB
XXXXXXXXB
00000000B
16-bit reload timer XXX10000B
1
XXXXXXXXB
XXXXXXXXB
LCDC
Sound generator 0
IPCP1
R
Input capture register 2
IPCP2
R
00000000B
XXXXXXXXB
00000000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Input capture 2/3
XXXXXXXXB
XXXXXXXXB
IPCP3
R
000068H Input capture control status 0/1
ICS01
R/W
000069H Input capture edge register 0/1
ICE01
R/W
00006AH Input capture control status 2/3
ICS23
R/W
00006BH Input capture edge register 2/3
ICE23
R/W
00006CH Lower LCD control register
LCRL
R/W
00006DH Higher LCD control register
LCRH
R/W
LVRC
R/W
Low voltage/CPU
operation
detection reset
00111000B
ROMM
W
ROM mirror
XXXXXXX1B
000067H
00006EH
Input capture register 3
11111111B
XXXXXXXXB
Input capture 0/1
Input capture register 1
Initial value
Low voltage/CPU operation
detection reset control register
00006FH ROM mirror
XXXXXXXXB
Input capture 0/1
Input capture 2/3
LCD controller/
driver
00000000B
XXX0X0XXB
00000000B
XXXXXXXXB
00010000B
00000000B
(Continued)
26
DS07-13754-3E
MB90930 Series
Address
Register name
000070H
to
00007FH
Symbol
Read/write
Resource name
Initial value
Area reserved for CAN Controller 1(Refer to “■ CAN CONTROLLERS”).
000080H PWM control register 0
000081H
PWC0
R/W
Stepping motor
controller 0
000000X0B
R/W
Stepping motor
controller 1
000000X0B
R/W
Stepping motor
controller 2
000000X0B
R/W
Stepping motor
controller 3
000000X0B
R/W
LCDC
XXXXX111B
(Disabled)
000082H PWM control register 1
000083H
PWC1
(Disabled)
000084H PWM control register 2
000085H
PWC2
(Disabled)
000086H PWM control register 3
000087H
PWC3
(Disabled)
000088H LCD output control register 3
000089H
LOCR3
(Disabled)
00008AH A/D setting register 0
ADSR0
R/W
00008BH A/D setting register 1
ADSR1
R/W
PIL0
R/W
00008CH Port input level select 0
00008DH Port input level select 1
PIL1
R/W
00008EH Port input level select 2
PIL2
R/W
00008FH
to
00009DH
A/D converter
00000000B
00000000B
00000000B
Port input level
select
XXXX0000B
XXXX0000B
(Disabled)
PACSR
R/W
Address match
detection
XXXX0X0XB
DIRR
R/W
Delay interrupt
XXXXXXX0B
0000A0H Power saving mode control register
LPMCR
R/W
00011000B
0000A1H Clock select register
CKSCR
R/W, R
Power saving
control circuit
11111100B
00009EH
Program address detection control
register
00009FH
Delayed Interrupt source generation /
Release Register
0000A2H
to
0000A7H
(Disabled)
0000A8H Watchdog timer control register
WDTC
R, W
Watchdog timer
XXXXX111B
0000A9H Time-base timer control register
TBTC
R/W, W
Time-base timer
1XX00100B
0000AAH Watch timer control register
WTC
R/W, W, R
Watch timer
(sub clock)
10001000B
0000ABH
to
0000ADH
(Disabled)
(Continued)
DS07-13754-3E
27
MB90930 Series
Address
Register name
0000AEH Flash memory control status register
0000AFH
Symbol
Read/write
Resource name
Initial value
FMCS
R/W
Flash interface
000X0000B
(Disabled)
0000B0H Interrupt control register 00
ICR00
R/W
00000111B
0000B1H Interrupt control register 01
ICR01
R/W
00000111B
0000B2H Interrupt control register 02
ICR02
R/W
00000111B
0000B3H Interrupt control register 03
ICR03
R/W
00000111B
0000B4H Interrupt control register 04
ICR04
R/W
00000111B
0000B5H Interrupt control register 05
ICR05
R/W
00000111B
0000B6H Interrupt control register 06
ICR06
R/W
00000111B
0000B7H Interrupt control register 07
ICR07
R/W
0000B8H Interrupt control register 08
ICR08
R/W
0000B9H Interrupt control register 09
ICR09
R/W
00000111B
0000BAH Interrupt control register 10
ICR10
R/W
00000111B
0000BBH Interrupt control register 11
ICR11
R/W
00000111B
0000BCH Interrupt control register 12
ICR12
R/W
00000111B
0000BDH Interrupt control register 13
ICR13
R/W
00000111B
0000BEH Interrupt control register 14
ICR14
R/W
00000111B
0000BFH Interrupt control register 15
ICR15
R/W
00000111B
0000C0H
to
0000C3H
Interrupt controller
00000111B
00000111B
(Disabled)
0000C4H Serial mode register 1
SMR1
R/W, W
00000000B
0000C5H Serial control register 1
SCR1
R/W, W
00000000B
Reception/transmission
data register 1
RDR1/
TDR1
R/W
00000000B
SSR1
R/W, R
ECCR1
R/W, R
0000C9H Extended status control register 1
ESCR1
R/W
00000100B
0000CAH Baud rate generator register 10
BGR10
R/W
00000000B
0000CBH Baud rate generator register 11
BGR11
R/W, R
00000000B
0000CCH Lower watch timer control register
WTCRL
R/W
0000C6H
0000C7H Serial status register 1
0000C8H
Extended communication
control register 1
0000CDH Middle watch timer control register
WTCRM
R/W
0000CEH Higher watch timer control register
WTCRH
R/W
UART
(LIN/SCI) 1
00001000B
000000XXB
000XXXX0B
Real-time
watch timer
00000000B
XXXXXX00B
(Continued)
28
DS07-13754-3E
MB90930 Series
Address
Symbol
Read/write
Resource name
Initial value
0000CFH PLL/Sub clock control register
PSCCR
W
PLL/Sub clock
XXXX0000B
0000D0H Input capture control status 4/5
ICS45
R/W
0000D1H Input capture edge register 4/5
ICE45
R/W, R
0000D2H Input capture control status 6/7
ICS67
R/W
0000D3H Input capture edge register 6/7
ICE67
R/W, R
0000D4H Lower timer control status register 2
TMCSR2L
R/W
0000D5H Higher timer control status register 2
TMCSR2H
R/W
0000D6H Lower timer control status register 3
TMCSR3L
R/W
0000D7H Higher timer control status register 3
TMCSR3H
R/W
0000D8H Lower sound control register 1
SGCRL1
R/W
0000D9H Higher sound control register 1
SGCRH1
R/W
0000DAH Lower PPG3 control status register
PCNTL3
R/W
0000DBH Higher PPG3 control status register
PCNTH3
R/W
0000DCH Lower PPG4 control status register
PCNTL4
R/W
0000DDH Higher PPG4 control status register
PCNTH4
R/W
0000DEH Lower PPG5 control status register
PCNTL5
R/W
0000DFH Higher PPG5 control status register
PCNTH5
R/W
0000E0H Serial mode register 2
SMR2
R/W, W
00000000B
0000E1H Serial control register 2
SCR2
R/W, W
00000000B
0000E2H Reception/transmission data register 2
RDR2/
TDR2
R/W
00000000B
0000E3H Serial status register 2
SSR2
R/W, R
ECCR2
R/W, R
0000E5H Extended status control register 2
ESCR2
R/W
00000100B
0000E6H Baud rate generator register 20
BGR20
R/W
00000000B
0000E7H Baud rate generator register 21
BGR21
R/W, R
00000000B
0000E8H Serial mode register 3
SMR3
R/W, W
00000000B
0000E9H Serial control register 3
SCR3
R/W, W
00000000B
0000EAH Reception/transmission data register 3
RDR3/
TDR3
R/W
00000000B
0000EBH Serial status register 3
SSR3
R/W, R
ECCR3
R/W, R
0000EDH Extended status control register 3
ESCR3
R/W
00000100B
0000EEH Baud rate generator register 30
BGR30
R/W
00000000B
0000EFH Baud rate generator register 31
BGR31
R/W, R
00000000B
0000E4H
0000ECH
Register name
Extended communication control
register 2
Extended communication control
register 3
Input capture 4/5
Input capture 6/7
16-bit
reload timer 2
16-bit
reload timer 3
Sound generator 1
16-bit PPG3
16-bit PPG4
16-bit PPG5
UART
(LIN/SCI) 2
UART
(LIN/SCI) 3
00000000B
XXXXXXXXB
00000000B
XXX0X0XXB
00000000B
XXX10000B
00000000B
XXX10000B
00000000B
0XXXX100B
00000000B
00000001B
00000000B
00000001B
00000000B
00000001B
00001000B
000000XXB
00001000B
000000XXB
(Continued)
DS07-13754-3E
29
MB90930 Series
Address
Register name
Symbol
Read/write
001FF0H Program address detection register 0
PADR0
R/W
XXXXXXXXB
001FF1H Program address detection register 1
PADR0
R/W
XXXXXXXXB
001FF2H Program address detection register 2
PADR0
R/W
001FF3H Program address detection register 3
PADR1
R/W
001FF4H Program address detection register 4
PADR1
R/W
XXXXXXXXB
001FF5H Program address detection register 5
PADR1
R/W
XXXXXXXXB
003700H
to
0037FFH
(Disabled)
003800H
to
0038FFH
(Disabled)
003900H
to
00391FH
(Disabled)
003920H
PPG0 down counter register
PDCR0
R
PPG0 cycle setting register
PCSR0
W
PPG0 duty setting register
PDUT0
W
003926H PPG0 output division setting register
PPGDIV0
R/W, R
003921H
003922H
003923H
003924H
003925H
003927H
003928H
PDCR1
R
PPG1 cycle setting register
PCSR1
W
PPG1 duty setting register
PDUT1
W
00392EH PPG1 output division setting register
PPGDIV1
R/W, R
00392AH
00392BH
00392CH
00392DH
00392FH
Address match
detection
Initial value
XXXXXXXXB
XXXXXXXXB
11111111B
11111111B
11111111B
16-bit PPG0
11111111B
00000000B
00000000B
11111100B
(Disabled)
PPG1 down counter register
003929H
Resource name
11111111B
11111111B
11111111B
16-bit PPG1
11111111B
00000000B
00000000B
11111100B
(Disabled)
(Continued)
30
DS07-13754-3E
MB90930 Series
Address
Symbol
Read/write
PPG2 down counter register
PDCR2
R
PPG2 cycle setting register
PCSR2
W
PPG2 duty setting register
PDUT2
W
003936H PPG2 output division setting register
PPGDIV2
R/W, R
003930H
003931H
003932H
003933H
003934H
003935H
Register name
003937H
to
00393FH
003940H
003941H
003942H
003943H
003944H
003945H
003946H
003947H
003951H
003952H
003953H
Initial value
11111111B
11111111B
11111111B
16-bit PPG2
11111111B
00000000B
00000000B
11111100B
(Disabled)
Input capture register 4
IPCP4
XXXXXXXXB
R
Input capture 4/5
Input capture register 5
IPCP5
R
Input capture register 6
IPCP6
R
Input capture register 7
IPCP7
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Input capture 6/7
003948H
to
00394FH
003950H
Resource name
R
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Disabled)
Timer register 2/Reload register 2
TMR2/
TMRLR2
R/W
16-bit reload timer XXXXXXXXB
2
XXXXXXXXB
Timer register 3/Reload register 3
TMR3/
TMRLR3
R/W
16-bit reload timer XXXXXXXXB
3
XXXXXXXXB
003954H
to
003957H
(Disabled)
XXXXXXXXB
003958H
003959H Sub second data register
WTBR
R/W
XXXXXXXXB
00395AH
XXXXXXXXB
Real time
watch timer
00395BH Second data register
WTSR
R/W
00395CH Minute data register
WTMR
R/W
XX000000B
00395DH Hour data register
WTHR
R/W
XXX00000B
00395EH Day data register
WTDR
R/W
00X00001B
00395FH
XX000000B
(Disabled)
(Continued)
DS07-13754-3E
31
MB90930 Series
Address
Register name
Symbol
Read/write
Resource name
Initial value
003960H
XXXXXXXXB
003961H
XXXXXXXXB
003962H
XXXXXXXXB
003963H
XXXXXXXXB
003964H
XXXXXXXXB
003965H
XXXXXXXXB
003966H
XXXXXXXXB
003967H
003968H
LCD display RAM
VRAM
R/W
LCD
controller/
driver
XXXXXXXXB
XXXXXXXXB
003969H
XXXXXXXXB
00396AH
XXXXXXXXB
00396BH
XXXXXXXXB
00396CH
XXXXXXXXB
00396DH
XXXXXXXXB
00396EH
XXXXXXXXB
00396FH
XXXXXXXXB
003970H
to
003973H
(Disabled)
003974H Frequency data register 1
SGFR1
R/W
003975H Amplitude data register 1
SGAR1
R/W
003976H Decrement grade register 1
SGDR1
R/W
003977H Tone count register 1
SGTR1
R/W
003978H
to
00397FH
003980H
XXXXXXXXB
Sound generator 1
00000000B
XXXXXXXXB
XXXXXXXXB
(Disabled)
XXXXXXXXB
PWM1 compare register 0
PWC10
R/W
PWM2 compare register 0
PWC20
R/W
003984H PWM1 select register 0
PWS10
R/W
00000000B
003985H PWM2 select register 0
PWS20
R/W
X0000000B
003981H
003982H
003983H
003986H,
003987H
XXXXXXXXB
Stepping motor
controller 0
XXXXXXXXB
XXXXXXXXB
(Disabled)
(Continued)
32
DS07-13754-3E
MB90930 Series
Address
Symbol
Read/write
PWM1 compare register 1
PWC11
R/W
PWM2 compare register 1
PWC21
R/W
00398CH PWM1 select register 1
PWS11
R/W
00000000B
00398DH PWM2 select register 1
PWS21
R/W
X0000000B
003988H
003989H
00398AH
00398BH
Register name
00398EH,
00398FH
003990H
Resource name
Initial value
XXXXXXXXB
XXXXXXXXB
Stepping motor
controller 1
XXXXXXXXB
XXXXXXXXB
(Disabled)
XXXXXXXXB
PWM1 compare register 2
PWC12
R/W
PWM2 compare register 2
PWC22
R/W
003994H PWM1 select register 2
PWS12
R/W
00000000B
003995H PWM2 select register 2
PWS22
R/W
X0000000B
003991H
003992H
003993H
003996H,
003997H
003998H
XXXXXXXXB
Stepping motor
controller 2
XXXXXXXXB
XXXXXXXXB
(Disabled)
XXXXXXXXB
PWM1 compare register 3
PWC13
R/W
PWM2 compare register 3
PWC23
R/W
00399CH PWM1 select register 3
PWS13
R/W
00000000B
00399DH PWM2 select register 3
PWS23
R/W
X0000000B
003999H
00399AH
00399BH
00399EH
to
0039A5H
XXXXXXXXB
Stepping motor
controller 3
XXXXXXXXB
XXXXXXXXB
(Disabled)
0039A6H Flash write control register 0
FWR0
0039A7H Flash write control register 1
FWR1
0039A8H
to
0039BFH
(Disabled)
0039C0H
to
0039DFH
(Disabled)
0039E0H
to
0039FFH
(Disabled)
R/W
Flash I/F
00000000B
00000000B
(Continued)
DS07-13754-3E
33
MB90930 Series
(Continued)
Address
Register name
Symbol
Read/write
Resource name
Initial value
003A00H
to
003AFFH
(Disabled)
003B00H
to
003BFFH
Area reserved for CAN Controller 1(Refer to “■ CAN CONTROLLERS”).
003C00H
to
003CFFH
(Disabled)
003D00H
to
003DFFH
Area reserved for CAN Controller 1(Refer to “■ CAN CONTROLLERS”).
003E00H
to
003EFFH
(Disabled)
003F00H
to
003FFFH
(Disabled)
34
DS07-13754-3E
MB90930 Series
■ CAN CONTROLLERS
The CAN controller has the following features :
• Conforms to CAN Specification Version 2.0 Part A and B
• Supports transmission/reception in standard frame and extended frame formats
• Supports transmission of data frames by receiving remote frames
• 16 transmission/reception message buffers
• 29-bit ID and 8-byte data
• Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as ID acceptance mask
• 2 acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 kbps to 2 Mbps (when input clock is at 16 MHz)
List of Control Registers(1)
Address
Register
Abbreviation
Access
Initial Value
Control status register
CSR
R/W, R
00---000B
0----0-1B
Last event indicator register
LEIR
R/W
--------B
000-0000B
RX/TX error counter
RTEC
R
00000000B
00000000B
BTR
R/W
-1111111B
11111111B
CAN1
003D00H
003D01H
003D02H
003D03H
003D04H
003D05H
003D06H
003D07H
DS07-13754-3E
Bit timing register
35
MB90930 Series
List of Control Registers(2)
Address
Register
Abbreviation
Access
Initial Value
Message buffer valid register
BVALR
R/W
00000000B
00000000B
Transmit request register
TREQR
R/W
00000000B
00000000B
Transmit cancel register
TCANR
W
00000000B
00000000B
Transmit complete register
TCR
R/W
00000000B
00000000B
Receive complete register
RCR
R/W
00000000B
00000000B
Remote request receive register
RRTRR
R/W
00000000B
00000000B
Receive overrun register
ROVRR
R/W
00000000B
00000000B
Receive interrupt enable register
RIER
R/W
00000000B
00000000B
IDE register
IDER
R/W
Transmit RTR register
TRTRR
R/W
Remote frame receive wait register
RFWTR
R/W
XXXXXXXXB
XXXXXXXXB
TIER
R/W
00000000B
00000000B
CAN1
000070H
000071H
000072H
000073H
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
00007BH
00007CH
00007DH
00007EH
00007FH
003D08H
003D09H
003D0AH
003D0BH
003D0CH
003D0DH
003D0EH
003D0FH
Transmit interrupt enable register
003D10H
003D11H
003D12H
Acceptance mask select register
AMSR
XXXXXXXXB
XXXXXXXXB
Acceptance mask register 0
AMR0
R/W
XXXXX---B
XXXXXXXXB
003D18H
003D1AH
003D1BH
36
00000000B
XXXXXXXXB
XXXXXXXXB
003D17H
003D19H
00000000B
R/W
003D14H
003D16H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
003D13H
003D15H
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Acceptance mask register 1
AMR1
R/W
XXXXX---B
XXXXXXXXB
DS07-13754-3E
MB90930 Series
List of Message Buffers (ID Registers)
Address
Register
CAN1
003B00H
to
003B1FH
General-purpose RAM
Abbreviation
Access
Initial Value
⎯
R/W
XXXXXXXXB
to
XXXXXXXXB
003B20H
003B21H
003B22H
XXXXXXXXB
XXXXXXXXB
ID register 0
IDR0
R/W
XXXXX---B
XXXXXXXXB
003B23H
003B24H
003B25H
003B26H
XXXXXXXXB
XXXXXXXXB
ID register 1
IDR1
R/W
XXXXX---B
XXXXXXXXB
003B27H
003B28H
003B29H
003B2AH
XXXXXXXXB
XXXXXXXXB
ID register 2
IDR2
R/W
XXXXX---B
XXXXXXXXB
003B2BH
003B2CH
003B2DH
003B2EH
XXXXXXXXB
XXXXXXXXB
ID register 3
IDR3
R/W
XXXXX---B
XXXXXXXXB
003B2FH
003B30H
003B31H
003B32H
XXXXXXXXB
XXXXXXXXB
ID register 4
IDR4
R/W
XXXXX---B
XXXXXXXXB
003B33H
003B34H
003B35H
003B36H
XXXXXXXXB
XXXXXXXXB
ID register 5
IDR5
R/W
XXXXX---B
XXXXXXXXB
003B37H
003B38H
003B39H
003B3AH
XXXXXXXXB
XXXXXXXXB
ID register 6
IDR6
R/W
XXXXX---B
XXXXXXXXB
003B3BH
003B3CH
003B3DH
003B3EH
003B3FH
XXXXXXXXB
XXXXXXXXB
ID register 7
IDR7
R/W
XXXXX---B
XXXXXXXXB
(Continued)
DS07-13754-3E
37
MB90930 Series
(Continued)
Address
Register
CAN1
Abbreviation
Access
003B40H
003B41H
003B42H
XXXXXXXXB
XXXXXXXXB
ID register 8
IDR8
R/W
XXXXX---B
XXXXXXXXB
003B43H
003B44H
003B45H
003B46H
XXXXXXXXB
XXXXXXXXB
ID register 9
IDR9
R/W
XXXXX---B
XXXXXXXXB
003B47H
003B48H
003B49H
003B4AH
XXXXXXXXB
XXXXXXXXB
ID register 10
IDR10
R/W
XXXXX---B
XXXXXXXXB
003B4BH
003B4CH
003B4DH
003B4EH
XXXXXXXXB
XXXXXXXXB
ID register 11
IDR11
R/W
XXXXX---B
XXXXXXXXB
003B4FH
003B50H
003B51H
003B52H
XXXXXXXXB
XXXXXXXXB
ID register 12
IDR12
R/W
XXXXX---B
XXXXXXXXB
003B53H
003B54H
003B55H
003B56H
XXXXXXXXB
XXXXXXXXB
ID register 13
IDR13
R/W
XXXXX---B
XXXXXXXXB
003B57H
003B58H
003B59H
003B5AH
XXXXXXXXB
XXXXXXXXB
ID register 14
IDR14
R/W
XXXXX---B
XXXXXXXXB
003B5BH
003B5CH
003B5DH
003B5EH
003B5FH
38
Initial Value
XXXXXXXXB
XXXXXXXXB
ID register 15
IDR15
R/W
XXXXX---B
XXXXXXXXB
DS07-13754-3E
MB90930 Series
List of Message Buffers (DLC Registers)
Address
Register
Abbreviation
Access
Initial Value
DLC register 0
DLCR0
R/W
----XXXXB
DLC register 1
DLCR1
R/W
----XXXXB
DLC register 2
DLCR2
R/W
----XXXXB
DLC register 3
DLCR3
R/W
----XXXXB
DLC register 4
DLCR4
R/W
----XXXXB
DLC register 5
DLCR5
R/W
----XXXXB
DLC register 6
DLCR6
R/W
----XXXXB
DLC register 7
DLCR7
R/W
----XXXXB
DLC register 8
DLCR8
R/W
----XXXXB
DLC register 9
DLCR9
R/W
----XXXXB
DLC register 10
DLCR10
R/W
----XXXXB
DLC register 11
DLCR11
R/W
----XXXXB
DLC register 12
DLCR12
R/W
----XXXXB
DLC register 13
DLCR13
R/W
----XXXXB
DLC register 14
DLCR14
R/W
----XXXXB
DLC register 15
DLCR15
R/W
----XXXXB
CAN1
003B60H
003B61H
003B62H
003B63H
003B64H
003B65H
003B66H
003B67H
003B68H
003B69H
003B6AH
003B6BH
003B6CH
003B6DH
003B6EH
003B6FH
003B70H
003B71H
003B72H
003B73H
003B74H
003B75H
003B76H
003B77H
003B78H
003B79H
003B7AH
003B7BH
003B7CH
003B7DH
003B7EH
003B7FH
DS07-13754-3E
39
MB90930 Series
List of Message Buffers (Data register)
Address
CAN1
Register
Abbreviation
Access
Initial Value
003B80H
to
003B87H
Data register 0 (8 bytes)
DTR0
R/W
XXXXXXXXB
to
XXXXXXXXB
003B88H
to
003B8FH
Data register 1 (8 bytes)
DTR1
R/W
XXXXXXXXB
to
XXXXXXXXB
003B90H
to
003B97H
Data register 2 (8 bytes)
DTR2
R/W
XXXXXXXXB
to
XXXXXXXXB
003B98H
to
003B9FH
Data register 3 (8 bytes)
DTR3
R/W
XXXXXXXXB
to
XXXXXXXXB
003BA0H
to
003BA7H
Data register 4 (8 bytes)
DTR4
R/W
XXXXXXXXB
to
XXXXXXXXB
003BA8H
to
003BAFH
Data register 5 (8 bytes)
DTR5
R/W
XXXXXXXXB
to
XXXXXXXXB
003BB0H
to
003BB7H
Data register 6 (8 bytes)
DTR6
R/W
XXXXXXXXB
to
XXXXXXXXB
003BB8H
to
003BBFH
Data register 7 (8 bytes)
DTR7
R/W
XXXXXXXXB
to
XXXXXXXXB
003BC0H
to
003BC7H
Data register 8 (8 bytes)
DTR8
R/W
XXXXXXXXB
to
XXXXXXXXB
003BC8H
to
003BCFH
Data register 9 (8 bytes)
DTR9
R/W
XXXXXXXXB
to
XXXXXXXXB
003BD0H
to
003BD7H
Data register 10 (8 bytes)
DTR10
R/W
XXXXXXXXB
to
XXXXXXXXB
003BD8H
to
003BDFH
Data register 11 (8 bytes)
DTR11
R/W
XXXXXXXXB
to
XXXXXXXXB
003BE0H
to
003BE7H
Data register 12 (8 bytes)
DTR12
R/W
XXXXXXXXB
to
XXXXXXXXB
003BE8H
to
003BEFH
Data register 13 (8 bytes)
DTR13
R/W
XXXXXXXXB
to
XXXXXXXXB
(Continued)
40
DS07-13754-3E
MB90930 Series
(Continued)
Address
CAN1
Register
Abbreviation
Access
Initial Value
003BF0H
to
003BF7H
Data register 14 (8 bytes)
DTR14
R/W
XXXXXXXXB
to
XXXXXXXXB
003BF8H
to
003BFFH
Data register 15 (8 bytes)
DTR15
R/W
XXXXXXXXB
to
XXXXXXXXB
DS07-13754-3E
41
MB90930 Series
■ INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interrupt source
EI2OS
corresponding
Interrupt vector
Number
Interrupt control
register
Address
ICR
Address
Reset
×
#08
08H
FFFFDCH
⎯
⎯
INT9 instruction
×
#09
09H
FFFFD8H
⎯
⎯
Exception processing
×
#10
0AH
FFFFD4H
⎯
⎯
⎯
×
#11
0BH
FFFFD0H
⎯
×
#12
0CH
FFFFCCH
ICR00
0000B0H
CAN1 received
×
#13
0DH
FFFFC8H
CAN1 transmitted/node status/
×
#14
0EH
FFFFC4H
ICR01
0000B1H*1
Input capture 0
#15
0FH
FFFFC0H
DTP/ external interrupt
- ch.0/ch.1 detected
#16
10H
FFFFBCH
ICR02
0000B2H*1
Reload timer 0
#17
11H
FFFFB8H
Reload timer 2
#18
12H
FFFFB4H
ICR03
0000B3H*1
Input capture 1
#19
13H
FFFFB0H
DTP/ external interrupt
- ch.2/ch.3 detected
#20
14H
FFFFACH
ICR04
0000B4H*1
Input capture 2
#21
15H
FFFFA8H
Reload timer 3
#22
16H
FFFFA4H
ICR05
0000B5H*1
Input capture 3/4/5/6/7
#23
17H
FFFFA0H
DTP/ external interrupt
- ch.4/ ch.5 detected UART3 RX
#24
18H
FFFF9CH
ICR06
0000B6H*1
PPG timer 0
#25
19H
FFFF98H
DTP/ external interrupt
- ch.6/ ch.7 detected UART3 TX
#26
1AH
FFFF94H
ICR07
0000B7H*1
PPG timer 1
#27
1BH
FFFF90H
Reload timer 1
#28
1CH
FFFF8CH
ICR08
0000B8H*1
PPG timer 2/3/4/5
#29
1DH
FFFF88H
ICR09
0000B9H*1
ICR10
0000BAH *1
ICR11
0000BBH*1
ICR12
0000BCH*1
Real time watch timer /
Watch timer (Sub clock)
×
#30
1EH
FFFF84H
Free-run timer overflow/clear
×
#31
1FH
FFFF80H
#32
20H
FFFF7CH
A/D converter conversion complete
Sound generator 0/1
×
#33
21H
FFFF78H
Time-base timer
×
#34
22H
FFFF74H
UART2 RX
#35
23H
FFFF70H
UART2 TX
#36
24H
FFFF6CH
Priority
*2
High
Low
(Continued)
42
DS07-13754-3E
MB90930 Series
(Continued)
Interrupt source
EI2OS
corresponding
Interrupt vector
Number
Address
UART 1 RX
#37
25H
FFFF68H
UART 1 TX
#38
26H
FFFF64H
UART 0 RX
#39
27H
FFFF60H
UART 0 TX
#40
28H
FFFF5CH
Flash memory status
×
#41
29H
FFFF58H
Delay interrupt generator module
×
#42
2AH
FFFF54H
Interrupt control
register
ICR
Address
ICR13
0000BDH*1
ICR14
0000BEH*1
ICR15
0000BFH*1
Priority
*2
High
Low
: Usable, and has extended intelligent I/O services (EI2OS) stop function
: Usable
: Usable when interrupt sources sharing ICR are not in use
× : Unusable
*1 : • Peripheral functions that share the ICR register have the same interrupt level.
• If the extended intelligent I/O service (EI2OS) is used with peripheral functions that share the ICR register,
only one of the peripheral functions that share the register can be used.
• When the extended intelligent I/O service (EI2OS) is specified for one of the peripheral functions that shares
the ICR register, interrupts cannot be used from the other peripheral functions that share the register.
*2 : Priority applies when interrupts of the same level are generated.
DS07-13754-3E
43
MB90930 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Power supply voltage*1
Symbol
VCC
VSS − 0.3
VSS + 6.0
V
AVCC
VSS − 0.3
VSS + 6.0
V
AVCC = VCC*2
AVRH
VSS − 0.3
VSS + 6.0
V
AVCC ≥ AVRH*2
DVCC
VSS − 0.3
VSS + 6.0
V
DVCC = VCC*2
VI
VSS − 0.3
VCC + 0.3
V
*3
VO
VSS − 0.3
VCC + 0.3
V
ICLAMP
−4
+4
mA
*7
⎯
40
mA
*7
IOL1
⎯
15
mA
Except P70 to P77 and P80 to P87
IOL2
⎯
40
mA
P70 to P77 and P80 to P87
IOLAV1
⎯
4
mA
Except P70 to P77 and P80 to P87
IOLAV2
⎯
30
mA
P70 to P77 and P80 to P87
ΣIOL1
⎯
100
mA
Except P70 to P77 and P80 to P87
ΣIOL2
⎯
330
mA
P70 to P77 and P80 to P87
ΣIOLAV1
⎯
50
mA
Except P70 to P77 and P80 to P87
ΣIOLAV2
⎯
250
mA
P70 to P77 and P80 to P87
I
OH1 4
⎯
−15
mA
Except P70 to P77 and P80 to P87
I
OH2 4
⎯
−40
mA
P70 to P77 and P80 to P87
I
OHAV1 5
⎯
−4
mA
Except P70 to P77 and P80 to P87
I
OHAV2 5
*
⎯
−30
mA
P70 to P77 and P80 to P87
ΣIOH1
⎯
−100
mA
Except P70 to P77 and P80 to P87
ΣIOH2
⎯
−330
mA
P70 to P77 and P80 to P87
⎯
−50
mA
Except P70 to P77 and P80 to P87
⎯
−250
mA
P70 to P77 and P80 to P87
Maximum clamp current
Total maximum clamp current Σ| ICLAMP |
“L” level maximum
output current*4
“L” level average output
current*5
“L” level maximum
total output current
“H” level maximum
output current
“H” level average
output current
“H” level maximum
total output current
“H” level average total
output current
*
*
*
ΣI
*
ΣI
*
OHAV1 6
OHAV2 6
Power consumption
PD
⎯
490
mW
Operating temperature
TA
− 40
+ 105
°C
TSTG
− 55
+ 150
°C
Storage temperature
Remarks
Max
1
“L” level average total
output current
Unit
Min
Input voltage*1
Output voltage*
Rating
*1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V.
*2 : AVCC, AVRH must not exceed VCC, and AVRH must not exceed AVCC.
When using an evaluation product, DVCC must not exceed VCC (however, DVCC can be set to a higher voltage
than VCC when using a Flash memory product/Mask ROM product).
*3 : If the input current or the maximum input current is limited using external components, ICLAMP is the applicable
rating instead of VI.
*4 : Maximum output current is defined as the peak value of current through any one of the corresponding pins.
(Continued)
44
DS07-13754-3E
MB90930 Series
(Continued)
*5 : Average output current is defined as the average value of the current flowing through any one of the
corresponding pins within a period of 100 ms. The “average value” can be calculated by multiplying the
“operating current” by the “operating factor”.
*6 : Average total output current is defined as the average value of the current flowing through all of the
corresponding pins within a period of 100 ms. The “average value” can be calculated by multiplying the
“operating current” by the “ operating factor”.
*7 : • Applicable to pins: P00 to P07, P10 to P15, P22 to P27, P30 to P37, P40 to P47, P50 to P57, P70 to P77,
P80 to P87
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied, the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the
microcontroller may partially malfunction on power supplied through the +B signal pin.
• Note that if the +B input is applied during power-on, the power supply voltage may reach a level such that
the power-on reset does not function due to the power supplied from the +B signal.
• Care must be taken not to leave +B input pins open.
• Note that analog system input/output pins (LCD common pins, comparator input pins, etc.) cannot accept
+B signal inputs.
• Sample recommended circuit :
• Input/output equivalent circuit
Protective diode
VCC
+B input (0 V to 16 V)
P-ch
Limiting
resistance
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS07-13754-3E
45
MB90930 Series
2. Recommended Operating Conditions
(VSS = DVSS = AVSS = 0.0 V)
Parameter
Power supply
voltage
Symbol
VCC,
AVCC,
DVCC
Value
Unit
Remarks
5.5
V
The low voltage detection reset operates when the power
supply voltage reaches 4.0 V ± 0.3 V.
5.5
V
Maintain stop operation status
The low voltage detection reset operates when the power
supply voltage reaches 4.0 V ± 0.3 V.
Use a ceramic capacitor or other capacitor of equivalent
frequency characteristics. Use a capacitor with a capacitance greater than this capacitor as the bypass capacitor
for the VCC pin.
Min
Max
3.7
3.7
Smoothing
capacitor*
CS
0.1
1.0
μF
Operating
temperature
TA
− 40
+ 105
°C
* : Refer to the following diagram for details on the connection of the smoothing capacitor CS.
• C pin connection diagram
C
CS
VSS
DVSS
AVSS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
46
DS07-13754-3E
MB90930 Series
3. DC Characteristics
Parameter
Symbol
VIHA
“H” level
input voltage
VIHS
VIHC
VILA
“L” level
input voltage
VILS
VILR
ICC
ICCS
ICTS
Power supply
current*
ICTSPLL
ICCL
ICCLS
ICCT
ICCH
DS07-13754-3E
(VCC = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Value
Pin
Conditions
Unit
Remarks
name
Min
Typ
Max
Pin inputs if
⎯
⎯
0.8 VCC ⎯
⎯
V Automotive input
levels are selected
Pin inputs if CMOS
⎯
⎯
0.8 VCC ⎯
⎯
V hysteresis input
levels are selected
RST input pin
⎯
⎯
0.7 VCC ⎯
⎯
V
(CMOS hysteresis)
Pin inputs if
⎯
⎯
⎯
⎯ 0.5 VCC V Automotive input
levels are selected
Pin inputs if CMOS
⎯
⎯
⎯
⎯ 0.2 VCC V hysteresis input
levels are selected
RST input pin
⎯
⎯
⎯
⎯ 0.3 VCC V
(CMOS hysteresis)
Maximum operating
frequency FCP = 32 MHz,
⎯
30
40
mA
normal operation
Maximum operating
⎯
40
55
mA
frequency FCP = 32 MHz,
writing Flash memory
Operating frequency
FCP = 32 MHz,
⎯
12
20
mA
sleep mode
Operating frequency
FCP = 2 MHz,
⎯
0.6
1.0
mA
time-base timer mode
Operating frequency
FCP = 32 MHz,
⎯
2.5
4
mA
PLL timer mode,
VCC
External frequency = 4 MHz
Operating frequency
FCP = 8 kHz,
⎯
170
340
μA
TA = + 25 °C,
Sub clock operation
Operating frequency
FCP = 8 kHz,
⎯
⎯
270
μA
TA = + 25 °C,
Sub sleep operation
Operating frequency
FCP = 8 kHz,
⎯
⎯
250
μA
TA = + 25 °C,
Watch mode
TA = + 25 °C,
⎯
⎯
170
μA
Stop mode
(Continued)
47
MB90930 Series
(VCC = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Parameter
Input leakage
current
Symbol
IIL
Pin name
All input pins
Conditions
Value
Unit
Min
Typ
Max
VCC = DVCC = AVCC =
5.5 V,
VSS < VI < VCC
⎯
⎯
10
μA
⎯
⎯
⎯
15
pF
Remarks
Input
capacitance 1
CIN1
All pins except
VCC, VSS,
DVCC, DVSS,
AVCC, AVSS,
C,
P70 to P77,
P80 to P87
Input capacitance 2
CIN2
P70 to P77,
P80 to P87
⎯
⎯
⎯
45
pF
Pull-up resistance
RUP
RST
⎯
⎯
⎯
100
kΩ
Excluding
Flash
kΩ
memory
product
Pull-down
resistance
RDOWN
MD2
⎯
⎯
⎯
100
VCC − 0.5
⎯
⎯
V
VCC − 0.5
⎯
⎯
V
⎯
⎯
0.4
V
General-purpose
output “H” voltage
VOH1
All pins except
VCC = 4.5 V,
P70 to P77,
IOH = −4.0 mA
P80 to P87
Stepping motor
output “H” voltage
VOH2
P70 to P77,
P80 to P87
General-purpose
output “L” voltage
VOL1
All pins except
VCC = 4.5 V,
P70 to P77,
IOL = 4.0 mA
P80 to P87
Stepping motor
output “L” voltage
VOL2
P70 to P77,
P80 to P87
VCC = 4.5 V,
IOL = 30.0 mA
⎯
⎯
0.55
V
ΔVOH
PWM1Pn,
PWM1Mn,
PWM2Pn,
PWM2Mn,
n = 0 to 3
VCC = 4.5 V,
IOH = −30.0 mA,
maximum deviation
VOH2
⎯
⎯
90
mV
ΔVOL
PWM1Pn,
PWM1Mn,
PWM2Pn,
PWM2Mn,
n = 0 to 3
VCC = 4.5 V,
IOL = 30.0 mA,
maximum deviation
VOL2
⎯
⎯
90
mV
6.25
12.5
25
kΩ Evaluation
RLCD
Between V0
and V1,
Between V1
and V2,
Between V2
and V3
8.75
12.5
17.0
Stepping motor
output phase
variation “H”
Stepping motor
output phase
variation “L”
LCD internal
divider resistance
VCC = 4.5 V,
IOH = −30.0 mA
⎯
kΩ
Flash/Mask
ROM
(Continued)
48
DS07-13754-3E
MB90930 Series
(Continued)
Parameter
LCDC leakage
current
LCD output
impedance
(VCC = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Symbol
Pin name
Conditions
ILCDC
V0 to V3,
COMm
(m = 0 to 3) ,
SEGn,
(n = 00 to 31)
Rvcom
Rvseg
Value
Unit
Min
Typ
Max
⎯
⎯
⎯
5.0
μA
COMn
(n = 0 to 3)
⎯
⎯
⎯
4.5
kΩ
SEGn
(n = 00 to 31)
⎯
⎯
⎯
17
kΩ
Remarks
* : Power supply current values are assumed by an external clock supplied from the X1 pin. Users must be aware
that power supply current levels differ depending on whether an external clock or oscillator is used.
DS07-13754-3E
49
MB90930 Series
4. AC Characteristics
(1) Clock timing
(VCC = 5.0 V ±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Symbol
FC
Clock frequency
Clock cycle time
Internal operating
clock frequency
Internal operating
clock cycle time
Pin name
Conditions
X0, X1
⎯
Value
Unit
Remarks
Min
Typ
Max
3
⎯
16
1/2 (PLL stopped)
MHz When using the
oscillator circuit
4
⎯
32
MHz PLL multiplied by 1
3
⎯
16
MHz PLL multiplied by 2
3
⎯
10.7
MHz PLL multiplied by 3
3
⎯
8
MHz PLL multiplied by 4
3
⎯
5.33
MHz PLL multiplied by 6
4
MHz PLL multiplied by 8
3
⎯
32.768
⎯
kHz
62.5
⎯
333
ns
FLC
X0A, X1A
tCYL
X0, X1
tLCYL
X0A, X1A
FCP
⎯
1.5
⎯
32
MHz
FLCP
⎯
⎯
8.192
⎯
kHz Using sub clock
tCP
⎯
31.25
—
666
ns
Using main clock
(PLL clock)
tLCP
⎯
⎯
122.1
⎯
μs
Using sub clock
μs
30.5
Using main clock
(PLL clock)
• X0, X1 clock timing
tCYL
0.8 VCC
X0
X1
0.2 VCC
PWH
PWL
tcf
tcr
• X0A, X1A clock timing
tCYL
0.8 VCC
X0A
X1A
0.2 VCC
PWH
PWL
tcf
50
tcr
DS07-13754-3E
MB90930 Series
• Guaranteed PLL Operation Range
Power supply voltage VCC (V)
Internal operating clock frequency vs. Power supply voltage
5.5
Range of warranted PLL operation
3.7
Normal operating range
1.5
4
32
Internal clock fCP (MHz)
Notes: • For PLL 1 × only, use with tcp = 4 MHz or greater.
• Refer to “5. A/D Converter (1) Electrical Characteristics” for details on the A/D converter operating
frequency.
(Continued)
DS07-13754-3E
51
MB90930 Series
(Continued)
Base oscillator frequency vs. Internal operating clock frequency
Internal clock fCP (MHz)
32
x 8*3
25
24
20
18
16
x 3*1
No multiplier
x 6*3
x 2*1,*2
x 1*1
x4
*1,*2
12
9
8
6
4
1.5
3 4 5 6 8 10 12.5 16
20
25
32
Base oscillator clock FCP (MHz)
*1 : When the PLL multiplier is × 1, × 2, × 3 or × 4 and the internal clock is 20 MHz < fCP ≤ 32 MHz, set
DIV2 bit = “1”*4, CS2 bit = “1” in the PSCCR register.
[Example]When using a base oscillator frequency of 24 MHz at PLL × 1 :
CKSCR register : CS1 bit = “0”, CS0 bit = “0”
PSCCR register : DIV2 bit = “1”*4 ,CS2 bit = “1”
[Example]When using a base oscillator frequency of 6 MHz at PLL × 3 :
CKSCR register : CS1 bit = “1”, CS0 bit = “0”
PSCCR register : DIV2 bit = “1”*4 , CS2 bit = “1”
*2 : When the PLL multiplier is × 2 or × 4 and the internal clock is 20 MHz < fCP ≤ 32 MHz, the following
settings are also supported.
PLL × 2 : CKSCR register : CS1 bit = “0”, CS0 bit = “0”
PSCCR register : DIV2 bit = “0”*4 ,CS2 bit = “0”
PLL × 4 : CKSCR register : CS1 bit = “0”, CS0 bit = “1”
PSCCR register : DIV2 bit = “0”*4 ,CS2 bit = “0”
*3 : When the PLL multiplier is set to × 6 or × 8, set “DIV2 bit = “0”*4 CS2 bit = “1”
and “PLL2 bit = 1” in the PSCCR register.
[Example]When using a base oscillator frequency of 4 MHz at PLL × 6 :
CKSCR register : CS1 bit = “1”, CS0 bit = “0”
PSCCR register : DIV2 bit = “0”*4 ,CS2 bit = “1”
[Example]When using a base oscillator frequency of 3 MHz at PLL × 8 :
CKSCR register : CS1 bit = “1”, CS0 bit = “1”
PSCCR register : DIV2 bit = “0”*4 ,CS2 bit = “1”
Note: The DIV2 bit is assigned to bit 9 of the PSCCR register and the CS2 bit is assigned to bit 8 of the PSCCR
register. Both bits have a default value of “0”.
52
DS07-13754-3E
MB90930 Series
(2) Reset input
(VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Parameter
Value
Symbol Pin name
Reset input time
tRSTL
Unit
Remarks
Min
Max
10
⎯
μs
During normal
operation
Oscillator oscillation time* + 100 μs
⎯
ms
In stop mode
100
⎯
μs
In time-base timer
mode
1
⎯
μs
⎯
RST
Width of Reset
input removal
*: The oscillation time of the oscillator is the time taken to reach 90% of the amplitude. The oscillation time of a
crystal oscillator is between several ms and tens of ms. The oscillation time of a ceramic oscillator is between
hundreds of μs and several ms. The oscillation time of an external clock is 0 ms.
Note: tCP is the internal operating clock cycle time. (Unit : ns)
• During normal operation
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode and power-on
tRSTL
RST
0.2 Vcc
X0
Internal
operating
clock
0.2 Vcc
90 % of
amplitude
Oscillator
oscillation time
100 μs
Oscillation stabilization wait time
Execution of the instructions
Internal
reset
DS07-13754-3E
53
MB90930 Series
(3) Power-on reset
(VCC = 2.7 V to 3.6 V, VSS = 0.0 V, TA = − 40 °C to +105 °C)
Symbol
Parameter
Power supply rise time
Pin
Conditions
name
tR
Power supply cutoff time
tOFF
⎯
VCC
Value
Unit
Min
Max
0.05
30
ms
1
⎯
ms
Remarks
Waiting time until
power-on
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
Note: Extreme variations in power supply voltage may trigger a power-on reset. When the power
supply voltage is changed during operation, it is recommended that increases in voltage are
smoothed out as shown in the following diagram. The PLL clock of the device should not be
in use when varying the voltage. However, the PLL clock may continue to be used if the rate
of the voltage drop is 1 V/s or less.
5.0 V
0V
54
VCC
VSS
RAM data hold
It is recommended that rises
in voltage have a slope of
50 mV/ms or less
DS07-13754-3E
MB90930 Series
(4) UART0/1/2/3 (LIN/SCI)
• Bit setting: ESCR0/1/2/3:SCES=0, ECCR0/1/2/3:SCDE=0
(VCC = 5.0 V±10 %, VSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
Valid SIN → SCK ↑
tIVSHI
SCK ↑ → valid SIN hold time
tSHIXI
Serial clock “L” pulse width
tSLSH
Serial clock “H” pulse width
tSHSL
SCK ↓ → SOT delay time
tSLOVE
Valid SIN → SCK ↑
tIVSHE
SCK ↑ → valid SIN hold time
tSHIXE
SCK ↓ time
tF
SCK ↑ time
tR
Conditions
Value
Unit
Min
Max
SCK0 to SCK3
5 tCP
⎯
ns
SCK0 to SCK3, Internal shift clock
SOT0 to SOT3 mode output pin
SCK0 to SCK3, CL = 80 pF + 1TTL
− 50
+ 50
ns
tCP + 80
⎯
ns
0
⎯
ns
3 tCP − tR
⎯
ns
tCP + 10
⎯
ns
⎯
2 tCP + 60
ns
30
⎯
ns
tCP + 30
⎯
ns
⎯
10
ns
⎯
10
ns
SIN0 to SIN3
SCK0 to SCK3
SCK0 to SCK3,
SOT0 to SOT3 External shift clock
mode output pin
SCK0 to SCK3, CL = 80 pF + 1TTL
SIN0 to SIN3
SCK0 to SCK3
Notes: • Depending on the machine clock frequency to be used, the maximum baud rate may be limited by some
parameters. These parameters are shown in “MB90930 series hardware manual”.
• CL is the load capacitance connected to the pin during testing.
• tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
DS07-13754-3E
55
MB90930 Series
• Internal shift clock mode
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSLOVI
2.4 V
SOT
0.8 V
tIVSHI
SIN
tSHIXI
VIH
VIH
VIL
VIL
• External shift clock mode
tSLSH
SCK
tSHSL
VIH
VIL
tF
VIH
VIL
tR
tSLOVE
2.4 V
SOT
0.8 V
tIVSHE
SIN
56
tSHIXE
VIH
VIH
VIL
VIL
DS07-13754-3E
MB90930 Series
• Bit setting: ESCR0/1/2/3:SCES=1, ECCR0/1/2/3:SCDE=0
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = − 40 °C to +105 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
Valid SIN → SCK ↓
tIVSLI
SCK ↓ → valid SIN hold time
tSLIXI
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
SCK ↑ → SOT delay time
tSHOVE
Valid SIN → SCK ↓
tIVSLE
SCK ↓ → valid SIN hold time
tSLIXE
SCK ↓ time
tF
SCK ↑ time
tR
Conditions
Value
Unit
Min
Max
SCK0 to SCK3
5 tCP
⎯
ns
SCK0 to SCK3, Internal shift clock
SOT0 to SOT3 mode output pin
CL = 80 pF + 1TTL
SCK0 to SCK3,
SIN0 to SIN3
− 50
+ 50
ns
tCP + 80
⎯
ns
0
⎯
ns
3 tCP − tR
⎯
ns
tCP + 10
⎯
ns
⎯
2 tCP + 60
ns
30
⎯
ns
tCP + 30
⎯
ns
⎯
10
ns
⎯
10
ns
SCK0 to SCK3
SCK0 to SCK3,
SOT0 to SOT3 External shift clock
mode output pin
SCK0 to SCK3, CL = 80 pF + 1TTL
SIN0 to SIN3
SCK0 to SCK3
Notes: • Depending on the machine clock frequency to be used, the maximum baud rate may be limited by some
parameters. These parameters are shown in “MB90930 series hardware manual”.
• CL is the load capacitance connected to the pin during testing.
• tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
DS07-13754-3E
57
MB90930 Series
• Internal shift clock mode
SCK
tSCYC
2.4 V
2.4 V
0.8 V
tSHOVI
2.4 V
SOT
0.8 V
tIVSLI
SIN
tSLIXI
VIH
VIH
VIL
VIL
• External shift clock mode
tSHSL
SCK
VIH
tSLSH
VIH
VIL
VIL
tR
tF
tSHOVE
2.4 V
SOT
0.8 V
tIVSLE
SIN
58
tSLIXE
VIH
VIH
VIL
VIL
DS07-13754-3E
MB90930 Series
• Bit setting: ESCR0/1/2/3:SCES=0, ECCR0/1/2/3:SCDE=1
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK0 to SCK3
SCK ↑ → SOT delay time
tSHOVI
SCK0 to SCK3,
SOT0 to SOT3
Valid SIN → SCK ↓
tIVSLI
SCK ↓ → valid SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
SCK0 to SCK3,
SIN0 to SIN3
Conditions
Internal shift clock
mode output pin
CL = 80 pF + 1TTL
SCK0 to SCK3,
SOT0 to SOT3
Value
Unit
Min
Max
5 tCP
⎯
ns
− 50
+ 50
ns
tCP + 80
⎯
ns
0
⎯
ns
3 tCP − 70
⎯
ns
Notes: • Depending on the machine clock frequency to be used, the maximum baud rate may be limited by some
parameters. These parameters are shown in “MB90930 series hardware manual”.
• CL is the load capacitance connected to the pin during testing.
• tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
tSCYC
2.4 V
SCK
0.8 V
0.8 V
tSHOVI
tSOVLI
SOT
2.4 V
2.4 V
0.8 V
0.8 V
tIVSLI
SIN
DS07-13754-3E
tSLIXI
VIH
VIH
VIL
VIL
59
MB90930 Series
• Bit setting: ESCR0/1/2/3:SCES=1, ECCR0/1/2/3:SCDE=1
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK0 to SCK3
SCK ↓ → SOT delay time
tSLOVI
SCK0 to SCK3,
SOT0 to SOT3
Valid SIN → SCK ↓
tIVSHI
SCK ↑ → valid SIN hold time
tSHIXI
SOT → SCK ↑ delay time
tSOVHI
SCK0 to SCK3,
SIN0 to SIN3
Conditions
Internal shift clock
mode output pin
CL = 80 pF + 1TTL
SCK0 to SCK3,
SOT0 to SOT3
Value
Unit
Min
Max
5 tCP
⎯
ns
− 50
+ 50
ns
tCP + 80
⎯
ns
0
⎯
ns
3 tCP − 70
⎯
ns
Notes: • Depending on the machine clock frequency to be used, the maximum baud rate may be limited by some
parameters. These parameters are shown in “MB90930 series hardware manual”.
• CL is the load capacitance connected to the pin during testing.
• tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
tSCYC
SCK
2.4 V
2.4 V
0.8 V
tSLOVI
tSOVHI
SOT
2.4 V
2.4 V
0.8 V
0.8 V
tIVSHI
SIN
60
tSHIXI
VIH
VIH
VIL
VIL
DS07-13754-3E
MB90930 Series
(5) Timer input timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTIWH
tTIWL
TIN0, TIN1,
IN0 to IN3
⎯
Value
Min
Max
4 tCP
⎯
Unit
ns
Note: tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
• Timer input timing
tTIWH
TIN0, TIN1
IN0 to IN3
DS07-13754-3E
VIH
tTIWL
VIH
VIL
VIL
61
MB90930 Series
(6) Trigger input timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTRGH,
tTRGL
INT0 to INT7
ADTG
Value
Unit
Min
Max
⎯
200
⎯
ns
⎯
tCP + 200
⎯
ns
Remarks
During normal
operation
Note: tCP is the internal operating clock cycle time. Refer to “ (1) Clock timing”.
• Trigger input timing
tTRGH
INT0 to INT7
ADTG
62
VIH
tTRGL
VIH
VIL
VIL
DS07-13754-3E
MB90930 Series
(7) Low voltage detection
(VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Symbol
Parameter
Detection voltage
Hysteresis width
Pin name
Conditions
⎯
VCC
VDL
VHYS
⎯
VCC
Value
Min
Typ
3.7
4.0
⎯
169
− 0.1
Power supply voltage
change rate
dV/dt
⎯
−0.004
Detection delay time
⎯
td
⎯
⎯
4.3
⎯
+ 0.1
Unit
Remarks
V
Flash memory
product/Mask ROM
product, during
voltage drop
mV
Flash memory
product/Mask ROM
product, during
voltage rise
Flash memory
product/Mask ROM
V/μs
product, dV/dt at low
voltage reset
⎯
Flash memory
product/Mask ROM
product, dV/dt at
+ 0.004 V/μs standard value of
low voltage
detection/release
voltage
⎯
Flash memory
product/Mask ROM
product, when
dV/dt ≤ 0.004 V/μs
⎯
VCC
Max
3.2
μs
Internal reset
VCC
dV
dt
td
DS07-13754-3E
VHYS
td
63
MB90930 Series
5. A/D Converter
(1) Electrical Characteristics
(VCC = AVCC = AVRH = 4.0 V to 5.5 V, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter
Symbol
Pin name
Resolution
⎯
Total error
Value
Unit
Remarks
Min
Typ
Max
⎯
⎯
⎯
10
bit
⎯
⎯
− 3.0
⎯
+ 3.0
LSB
Non-linear error
⎯
⎯
− 2.5
⎯
+ 2.5
LSB
Differential linear error
⎯
⎯
− 1.9
⎯
+ 1.9
LSB
Zero transition voltage
VOT
AN0 to
AN23
AVSS −
1.5 LSB
AVSS +
0.5 LSB
AVSS +
2.5 LSB
V
Full scale transition
voltage
VFST
AN0 to
AN23
AVRH −
3.5 LSB
AVRH −
1.5 LSB
AVRH +
0.5 LSB
V
Sampling time
tSMP
⎯
⎯
16500
μs
Compare time
tCMP
⎯
⎯
⎯
μs
A/D conversion time
tCNV
⎯
1.44
⎯
⎯
μs
Analog port
input current
IAIN
AN0 to
AN23
− 1.0
⎯
+ 1.0
μA
Analog input voltage
VAIN
AN0 to
AN23
0
⎯
AVRH
V
Reference voltage
AV+
AVRH
AVss +
2.7
⎯
AVCC
V
⎯
2.3
6.0
mA
⎯
⎯
5
μA
*2
⎯
⎯
900
μA
VAVRH = 5.0 V
⎯
⎯
5
μA
*2
⎯
⎯
4
LSB
Power supply current
IA
IAH
IR
Reference voltage
supply current
IRH
Inter-channel variation
—
AVCC
AVRH
AN0 to
AN23
0.4
1.0
0.66
2.2
1 LSB =
(AVRH − AVSS) /
1024
4.5 V ≤ AVcc ≤ 5.5 V
4.0 V ≤ AVcc ≤ 4.5 V
4.5 V ≤ AVcc ≤ 5.5 V
4.0 V ≤ AVcc ≤ 4.5 V
*1
*1 : The time per channel (4.5 V ≤ AVCC ≤ 5.5 V, and internal operating frequency = 32 MHz) .
*2 : Defined as supply current (when VCC = AVCC = AVRH = 5.0 V) with A/D converter not operating, and CPU in
stop mode.
64
DS07-13754-3E
MB90930 Series
• Notes on the external impedance and sampling time of analog inputs
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
If the sampling time is still not sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
• Analog input equivalent circuit
R
Analog input
Comparator
C
During sampling : ON
MB90F931/MB90F931S/MB90931/MB90931S
R
C
4.5 V ≤ AVcc ≤ 5.5 V : 2.6 kΩ (Max) 8.5 pF (Max)
4.0 V ≤ AVcc ≤ 4.5 V : 12.1 kΩ (Max) 8.5 pF (Max)
MB90V930-102/MB90V930-101
R
4.5 V ≤ AVcc ≤ 5.5 V : 2.0 kΩ (Max)
4.0 V ≤ AVcc ≤ 4.5 V : 8.2 kΩ (Max)
C
14.4 pF (Max)
14.4 pF (Max)
Note : The values are reference values.
DS07-13754-3E
65
MB90930 Series
• The relationship between the external impedance and minimum sampling time
• At 4.5 V ≤ AVcc ≤ 5.5 V
(External impedance = 0 kΩ to 20 kΩ)
MB90V930-102/MB90V930-101
100
90
80
70
60
50
40
30
20
10
0
MB90F931/MB90F931S/
MB90931/MB90931S
0
5
10
15
20
25
30
External impedance [kΩ]
External impedance [kΩ]
(External impedance = 0 kΩ to 100 kΩ)
35
MB90V930-102/MB90V930-101
20
18
16
14
12
10
8
6
4
2
0
MB90F931/MB90F931S/
MB90931/MB90931S
0
1
2
3
4
5
6
7
8
Minimum sampling time [μs]
Minimum sampling time [μs]
• At 4.0 V ≤ AVcc ≤ 4.5 V
(External impedance = 0 kΩ to 20 kΩ)
MB90V930-102/MB90V930-101
100
90
80
70
60
50
40
30
20
10
0
MB90F931/MB90F931S/
MB90F035/MB90035
MB90931/MB90931S
0
5
10
15
20
25
30
External impedance [kΩ]
External impedance [kΩ]
(External impedance = 0 kΩ to 100 kΩ)
35
Minimum sampling time [μs]
MB90V930-102/MB90V930-101
20
18
16
14
12
10
8
6
4
2
0
MB90F931/MB90F931S/
MB90931/MB90931S
0
1
2
3
4
5
6
7
8
Minimum sampling time [μs]
•About errors
As |AVRH - AVSS| becomes smaller, the relative errors grow larger.
66
DS07-13754-3E
MB90930 Series
(2) Definition of terms
Resolution
: Analog changes that are identifiable by the A/D converter.
Non-Linear error : The deviation of the straight line connecting the transition point
(“00 0000 0000” ←→ “00 0000 0001”) with the full-scale transition point
(“11 1111 1110” ←→ “11 1111 1111”) from actual conversion characteristics.
Differential linear : The deviation from the ideal value of the input voltage needed to change the output code by
error
1 LSB.
: The total error is the difference between the actual value and the theoretical value,
Total error
and includes transition error/full-scale transition error and linear error.
Total error
Digital output
3FFH
3FEH
3FDH
Actual conversion
value
1.5 LSB
{1 LSB x (N - 1) + 0.5 LSB}
004H
003H
Actual conversion value
002H
001H
0.5 LSB
VNT
(Measured value)
Ideal
characteristics
AVSS
AVRH
Analog input
Total error for digital output N =
1 LSB (Ideal) =
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
[LSB]
AVRH − AVSS [V]
1024
N : A/D converter digital output value
VOT (Ideal) = AVss + 0.5 LSB [V]
VFST (Ideal) = AVRH − 1.5 LSB [V]
VNT : Voltage when the digital output changes from (N - 1) to N
(Continued)
DS07-13754-3E
67
MB90930 Series
(Continued)
Non-Linear error
Ideal
characteristics
Actual conversion
value
{1 LSB x (N -1)
+ VOT}
VFST
(Measured
value)
VNT
(Measured value)
004H
003H
Actual conversion value
002H
Ideal
characteristics
001H
Actual conversion
value
(N + 1)
Digital output
Digital output
3FFH
3FEH
3FDH
Differential linear error
N
V(N + 1)T
(Measured
value)
(N - 1)
VNT
(Measured value)
Actual conversion value
(N - 2)
VOT (Measured value)
AVRH
AVss
Analog input
Analog input
Non-linear error of
digital output N
=
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
Differential linear error
V (N + 1) T − VNT
=
1 LSB
of digital output N
1 LSB =
AVRH
AVss
VFST − VOT
1022
[LSB]
− 1 [LSB]
[V]
N : A/D converter digital output value
VOT : Voltage when digital output changes from 000H to 001H
VFST : Voltage when digital output changes from 3FEH to 3FFH
68
DS07-13754-3E
MB90930 Series
6. Flash Memory Program/Erase Characteristics
Parameter
Sector erase time
Word (16-bit width)
programming time
Chip programming
time
Erase/program cycle
Flash memory data
retention time
Conditions
Value
Unit
Remarks
Min
Typ
Max
⎯
0.9
3.6
s
Excludes pre-programming
before erase
⎯
23
370
μs
Excludes system-level overhead
TA = + 25 °C,
VCC = 5.0 V
⎯
3.4
55
s
⎯
10000
⎯
⎯
cycle
Average
TA = + 85 °C
20
⎯
⎯
year
TA = + 25 °C,
VCC = 5.0 V
*
* : This value is calculated from the results of evaluating the reliability of the technology (using Arrhenius equation
to translate high temperature measurements into normalized value at + 85 °C) .
DS07-13754-3E
69
MB90930 Series
■ ORDERING INFORMATION
Part number
Package
MB90F931PMC
MB90F931SPMC
MB90931PMC
MB90931SPMC
120-pin plastic LQFP
(FPT-120P-M21)
MB90V930-102
MB90V930-101
299-pin ceramic PGA
(PGA-299C-A01)
70
Remarks
Evaluation
DS07-13754-3E
MB90930 Series
■ PACKAGE DIMENSION
120-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
16.0 × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.88 g
Code
(Reference)
P-LFQFP120-16×16-0.50
(FPT-120P-M21)
120-pin plastic LQFP
(FPT-120P-M21)
Note 1) * : These dimensions do not include resin protrusion.
Resin protrusion is +0.25(.010) MAX(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00±0.20(.709±.008)SQ
+0.40
* 16.00 –0.10 .630 +.016
–.004 SQ
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
0~8°
120
LEAD No.
1
30
0.50(.020)
C
"A"
31
0.22±0.05
(.009±.002)
0.08(.003)
M
0.145
.006
2002-2010 FUJITSU SEMICONDUCTOR LIMITED F120033S-c-4-7
+0.05
–0.03
+.002
–.001
0.60±0.15
(.024±.006)
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-13754-3E
71
MB90930 Series
■ MAIN CHANGES IN THIS EDITION
Page
13
21
49
Section
Change Results
■ I/O CIRCUIT TYPE
Corrected the circuit type A and B.
■ HANDLING DEVICES
Added the following items.
• Serial communication
• Characteristic difference between flash device and mask
ROM device
■ ELECTRICAL CHARACTERISTICS Added the item for “LCD output impedance”.
3. DC Characteristic
The vertical lines marked in the left side of the page show the changes.
72
DS07-13754-3E
MB90930 Series
MEMO
DS07-13754-3E
73
MB90930 Series
MEMO
74
DS07-13754-3E
MB90930 Series
MEMO
DS07-13754-3E
75
MB90930 Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
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Tel: +1-408-737-5600 Fax: +1-408-737-5999
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#05-08 New Tech Park 556741 Singapore
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http://www.fujitsu.com/sg/services/micro/semiconductor/
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http://emea.fujitsu.com/semiconductor/
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Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fss/
Korea
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Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not
warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device
based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or
any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other
right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property
rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
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