3.0 MB

The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07–13807–2E
16-bit Proprietary Microcontroller
CMOS
F2MC-16FX MB96370 Series
MB96375RS/RW, MB96F378HS/HW, MB96F379RS/RW
■ DESCRIPTION
MB96370 series is based on Fujitsu’s advanced 16FX architecture (16-bit with instruction pipeline for RISClike performance). The CPU uses the same instruction set as the established 16LX series - thus allowing
for easy migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous
generation include significantly improved performance - even at the same operation frequency, reduced
power consumption and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply
the CPU with up to 40MHz operation frequency from an external 4MHz resonator. The result is a minimum
instruction cycle time of 25ns going together with excellent EMI behavior. An on-chip clock modulation circuit
significantly reduces emission peaks in the frequency spectrum. The emitted power is minimized by the onchip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable
operation frequencies for peripheral resources independent of the CPU speed.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
FUJITSU SEMICONDUCTOR provides information facilitating product development via the following website.
The website contains information useful for customers.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2010-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2013.05
MB96370 Series
■ FEATURES
Feature
Technology
Description
• 0.18µm CMOS
• F2MC-16FX CPU
• Up to 40 MHz internal, 25 ns instruction cycle time
CPU
• Optimized instruction set for controller applications (bit, byte, word and long-word
data types; 23 different addressing modes; barrel shift; variety of pointers)
• 8-byte instruction execution queue
• Signed multiply (16-bit × 16-bit) and divide (32-bit/16-bit) instructions available
• On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop)
• 3 MHz - 16 MHz external crystal oscillator clock (maximum frequency when using
ceramic resonator depends on Q-factor).
• Up to 40 MHz external clock
• 32 kHz - 100 kHz subsystem quartz clock
System clock
• 100kHz/2MHz internal RC clock for quick and safe startup, oscillator stop detection,
watchdog
• Clock source selectable from main- and subclock oscillator (part number suffix “W”)
and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals.
• Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes,
Stop mode)
• Clock modulator
On-chip voltage
regulator
Low voltage reset
Code Security
Memory Patch Function
DMA
• Internal voltage regulator supports reduced internal MCU voltage, offering low EMI
and low power consumption figures
• Reset is generated when supply voltage is below minimum.
• Protects ROM content from unintended read-out
• Replaces ROM content
• Can also be used to implement embedded debug support
• Automatic transfer function independent of CPU, can be assigned freely to resources
• Fast Interrupt processing
Interrupts
• 8 programmable priority levels
• Non-Maskable Interrupt (NMI)
Timers
• Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit
Sub clock timer)
• Watchdog Timer
2
DS07-13807-2E
MB96370 Series
Feature
Description
• Supports CAN protocol version 2.0 part A and B
• ISO16845 certified
• Bit rates up to 1 Mbit/s
• 32 message objects
CAN
• Each message object has its own identifier mask
• Programmable FIFO mode (concatenation of message objects)
• Maskable interrupt
• Disabled Automatic Retransmission mode for Time Triggered CAN applications
• Programmable loop-back mode for self-test operation
• Full duplex USARTs (SCI/LIN)
USART
• Wide range of baud rate settings using a dedicated reload timer
• Special synchronous options for adapting to different synchronous serial protocols
• LIN functionality working either as master or slave LIN device
I2C
• Up to 400 kbps
• Master and Slave functionality, 7-bit and 10-bit addressing
• SAR-type
A/D converter
• 10-bit resolution
• Signals interrupt on conversion end, single conversion mode, continuous conversion
mode, stop conversion mode, activation by software, external trigger or reload timer
• 16-bit wide
Reload Timers
• Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency
• Event count function
Free Running Timers
• Signals an interrupt on overflow, supports timer clear upon match with Output
Compare (0, 4), Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27,1/28 of
peripheral clock frequency
• 16-bit wide
Input Capture Units
• Signals an interrupt upon external event
• Rising edge, falling edge or rising & falling edge sensitive
• 16-bit wide
Output Compare Units • Signals an interrupt when a match with 16-bit I/O Timer occurs
• A pair of compare registers can be used to generate an output signal.
• 16-bit down counter, cycle and duty setting registers
• Interrupt at trigger, counter borrow and/or duty match
Programmable Pulse
Generator
• PWM operation and one-shot operation
• Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and
Reload timer underflow as clock input
• Can be triggered by software or reload timer
DS07-13807-2E
3
MB96370 Series
Feature
Description
• Stepper Motor Controller with integrated high current output drivers
• Four high current outputs for each channel
Stepper Motor
Controller
• Two synchronized 8/10-bit PWMs per channel
• Internal prescaling for PWM clock: 1, 1/4, 1/5, 1/6, 1/8, 1/10, 1/12, 1/16 of peripheral
clock
• Separate power supply for high current output drivers
• LCD controller with up to 4 COM ×72 SEG
• Internal or external voltage generation
• Duty cycle: Selectable from options: 1/2, 1/3 and 1/4
• Fixed 1/3 bias
• Programmable frame period
• Clock source selectable from three options (peripheral clock, subclock or RC
oscillator clock)
LCD Controller
• On-chip drivers for internal divider resistors or external divider resistors
• On-chip data memory for display
• LCD display can be operated in Timer Mode
• Blank display: selectable
• All SEG, COM and V pins can be switched between general and specialized
purposes
• External divided resistors can be also used to shut off the current when LCD is
deactivated
Sound Generator
• 8-bit PWM signal is mixed with tone frequency from 16-bit reload counter
• PWM clock by internal prescaler: 1, 1/2, 1/4, 1/8 of peripheral clock
• Can be clocked either from sub oscillator (devices with part number suffix “W”), main
oscillator or from the RC oscillator
Real Time Clock
• Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock
calibration)
• Read/write accessible second/minute/hour registers
• Can signal interrupts every half second/second/minute/hour/day
• Internal clock divider and prescaler provide exact 1s clock
• Edge sensitive or level sensitive
External Interrupts
• Interrupt mask and pending bit per channel
• Each available CAN channel RX has an external interrupt for wake-up
• Selected USART channels SIN have an external interrupt for wake-up
• Disabled after reset
Non Maskable Interrupt
• Once enabled, can not be disabled other than by reset.
• Level high or level low sensitive
• Pin shared with external interrupt 0.
4
DS07-13807-2E
MB96370 Series
Feature
Description
• 8-bit or 16-bit bidirectional data
• Up to 24-bit addresses
• 6 chip select signals
External bus interface
• Multiplexed address/data lines
• Non-multiplexed address/data lines
• Wait state request
• External bus master possible
• Timing programmable
• Monitors an external voltage and generates an interrupt in case of a voltage lower or
higher than the defined thresholds
Alarm comparator*1
• Threshold voltages defined externally or generated internally
• Status is readable, interrupts can be masked separately
• Virtually all external pins can be used as general purpose I/O
• All push-pull outputs (except when used as I2C SDA/SCL line)
• Bit-wise programmable as input/output or peripheral signal
I/O Ports
• Bit-wise programmable input enable
• Bit-wise programmable input levels: Automotive / CMOS-Schmitt trigger / TTL
• Bit-wise programmable pull-up resistor
• Bit-wise programmable output driving strength for EMI optimization
Packages
• 144-pin plastic LQFP M08/12
• Supports automatic programming, Embedded Algorithm
• Write/Erase/Erase-Suspend/Resume commands
• A flag indicating completion of the algorithm
• Number of erase cycles: 10,000 times
Flash Memory
• Data retention time: 20 years
• Erase can be performed on each sector individually
• Sector protection
• Flash Security feature to protect the content of the Flash Memory
• Low voltage detection during Flash erase
*1: No alarm comparator available on MB96375R.
DS07-13807-2E
5
MB96370 Series
■ PRODUCT LINEUP
Features
MB96V300C
MB96(F)37x
Product type
Evaluation
sample
Flash product: MB96F37x
Mask ROM product: MB9637x
Product options
RS
Low voltage reset can be disabled / Single clock devices
RW
Low voltage reset can be disabled / Dual clock devices
NA
HS
indep. 32KB Flash / Low voltage reset can be disabled /
Dual clock devices
HW
6
indep. 32KB Flash / Low voltage reset can be disabled /
Single clock devices
Flash/ROM
RAM
160KB
12KB
576KB
[Flash A: 544KB,
Flash B: 32KB]
28KB
832KB
[Flash A: 544KB,
Flash B: 288KB]
32KB
ROM/Flash
memory
emulation by
external RAM,
92KB internal
RAM
MB96375RS/RW
MB96F378HS/HW
MB96F379RS/RW
Package
BGA416
FPT-144P-M08, FPT-144P-M12
DMA
16 channels
7 channels
USART
10 channels
6 channels
I2C
2 channels
2 channels
A/D Converter
40 channels
22 channels
A/D Converter Reference Voltage
switch
Yes
No
16-bit Reload Timer
6 channels
+ 1 channel (for
PPG)
4 channels + 1 channel (for PPG)
16-bit Free-Running Timer
4 channels
2 channels
16-bit Output Compare
12 channels
6 channels
16-bit Input Capture
12 channels
8 channels
16-bit Programmable Pulse
Generator
20 channels
12 channels
CAN Interface
5 channels
2 channels
Stepper Motor Controller
6 channels
6 channels
External Interrupts
16 channels
8 channels
DS07-13807-2E
MB96370 Series
Features
MB96V300C
MB96(F)37x
Non-Maskable Interrupt
1 channel
Sound generator
2 channels
LCD Controller
4 COM x 72 SEG
Real Time Clock
1
I/O Ports
Alarm comparator
136
2 channels
118 for part number with suffix "W", 120 for part number with
suffix "S"
Other than MB96375R: 2 channels
MB96375R: no alarm comparator
External bus interface
Yes
Chip select
6 signals
Clock output function
2 channels
Low voltage reset
Yes
On-chip RC-oscillator
Yes
DS07-13807-2E
7
MB96370 Series
■ BLOCK DIAGRAM
Block diagram of MB96(F)37x
AD00 ... AD15
A00 ... A23
ALE
RDX
WR(L)X, WRHX
HRQ
HAKX
NMI
RDY
ECLK
LBX, UBX
CS0 ... CS5, CS3_R
External Bus
Interface
16FX
CPU
Interrupt
Controller
CKOT0, CKOT1, CKOT0_R, CKOT1_R
CKOTX0, CKOTX1, CKOTX1_R
X0, X1
X0A, X1A *1
RSTX
MD0...MD2
Flash
Memory A
Flash
Memory B
Memory Patch
Unit
Clock &
Mode Controller
16FX Core Bus (CLKB)
AVCC
AVSS
AVRH
AVRL
AN0 ... AN21
ADTG
TIN0 ... TIN3
TIN1_R, TIN2_R
TOT0 ... TOT3
TOT1_R, TOT2_R
FRCK0
FRCK0_R
IN0 ... IN3
IN0_R ... IN3_R
OUT0 ... OUT3
OUT0_R...OUT3_R
FRCK1
IN4 ... IN7
IN4_R ... IN7_R
OUT4, OUT5
INT0 ... INT7
INT1_R ... INT7_R
V0 ... V3
COM0 ... COM3
SEG0 ... SEG71
Peripheral
Bus Bridge
Peripheral
Bus Bridge
Peripheral Bus 2 (CLKP2)
SDA0, SDA1
SCL0, SCL1
Watchdog
I2C
2 ch.
10-bit ADC
22 ch.
16-bit Reload
Timer
4 ch.
I/O Timer 0
ICU 01/2/3
OCU 0/1/2/3
I/O Timer 1
ICU 4/5/6/7
OCU 4/5
Peripheral Bus 1 (CLKP1)
DMA
Controller
External
Interrupt
LCD
controller/
driver
USART
6 ch.
Alarm
Comparator
2 ch.*2
16-bit PPG
12 ch.
RLT6
Stepper
Motor
Controller
6 ch.
Real Time
Clock
RAM
Boot ROM
Voltage
Regulator
VCC
VSS
C
CAN
Interface
2 ch.
Sound
Generator
2 ch.
TX0 ,TX1
RX0 , RX1
SGO0, SGO1, SGO0_R, SGO1_R
SGA0, SGA1, SGA0_R, SGA1_R
SIN0...SIN5
SOT0...SOT5
SCK0...SCK5
ALARM0
ALARM1
TTG0 ... TTG11
PPG0 ... PPG11
PPG0_R ... PPG5_R
PWM1M0 ... PWM1M5
PWM1P0 ... PWM1P5
PWM2M0 ... PWM2M5
PWM2P0 ... PWM2P5
DVCC
DVSS
WOT
*1: X0A, X1A only available on devices with suffix “W”
*2: No alarm comparator available on MB96375R
8
DS07-13807-2E
MB96370 Series
■ PIN ASSIGNMENTS
Vss
P00_3/INT6_R/A00/CS3_R/SEG15
P00_4/INT7_R/ALE/SEG16
P00_5/TTG2/TTG6/IN6/RDX/SEG17
P00_6/TTG3/TTG7/IN7/WRLX/WRX/SEG18
P00_7/SGO0/ECLK/SEG19
P01_0/SGA0/AD00/SEG20
P01_1/OUT0/CKOT1/AD01/SEG21
P01_2/OUT1/CKOTX1/AD02/SEG22
P01_3/PPG5/AD03/SEG23
P01_4/AD04/SIN4/SEG24
P01_5/AD05/SOT4/SEG25
P01_6/AD06/SCK4/SEG26
P01_7/CKOTX1_R/AD07/SEG27
P02_0/CKOT1_R/AD08/SEG28
P02_1/IN6_R/AD09/SEG29
P02_2/CKOT0_R/IN7_R/AD10/SEG30
P02_3/SGO0_R/AD11/SEG31
P02_4/SGA0_R/AD12/SEG32
P02_5/OUT0_R/AD13/SEG33
P02_6/OUT1_R/AD14/SEG34
P02_7/PPG5_R/AD15/SEG35
P16_0/PPG8/IN4
Vss
X1
X0
MD2
MD1
MD0
Vss
Vcc
P16_7/OUT5/TTG11
P16_6/OUT4/TTG10
P16_5/IN3/TTG9
P16_4/IN2/TTG8
P00_2/INT5_R/RDY/SEG14
P00_1/INT4_R/WRHX/SEG13
P00_0/INT3_R/HAKX/SEG12
P12_7/INT1_R/HRQ/SEG11
P12_6/TOT2_R/A15/SEG10
P12_5/TIN2_R/A14/SEG9
P12_4/OUT3_R/A13/SEG8
P12_3/OUT2_R/A12/SEG7
P12_2/TOT1_R/A11/SEG6
P12_1/TIN1_R/A10/SEG5
P12_0/IN1_R/A09/SEG4
P11_7/IN0_R/A08/SEG3
P11_6/FRCK0_R/A07/SEG2
P11_5/PPG4_R/A06/SEG1
P11_4/PPG3_R/A05/SEG0
P11_3/PPG2_R/A04/COM3
P11_2/PPG1_R/A03/COM2
P11_1/PPG0_R/A02/COM1
P11_0/A01/COM0/CS5
P16_3/PPG11
P16_2/PPG10
RSTX
X1A/P04_1 *1
X0A/P04_0 *1
Pin assignment of MB96(F)37x
108
106
104
102
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
107
105
103
101
109
72
110
71
111
70
112
69
113
68
114
67
115
66
116
65
117
64
118
63
119
62
120
61
LQFP - 144
121
122
123
60
59
58
124
57
Package code (mold)
FPT-144P-M08/FPT-144P-M12
125
126
127
56
55
54
128
53
129
52
130
51
131
50
P16_1/PPG9/IN5
132
49
P03_0/V0/A16/SEG36
P03_1/V1/A17/SEG37
P03_2/V2/A18/SEG38
P03_3/V3/A19/SEG39
P03_4/INT4/RX0
P03_5/TX0
P03_6/NMI/INT0
P04_6/SDA1
P04_7/SCL1
P07_6/SEG71
P07_7
Vcc
133
48
134
47
135
46
136
45
137
44
138
139
43
42
140
41
141
40
142
39
143
38
37
144
3
4
5
6
7
8
*1: Devices with suffix W: X0A/X1A
Devices with suffix S: P04_0, P04_1
P08_4/PWM1P1
P08_3/PWM2M0
P08_2/PWM2P0
P08_1/PWM1M0
P08_0/PWM1P0
P05_7/AN15/TOT2/SGA1_R/SEG64
P05_6/AN14/TIN2/SGO1_R/SEG63
P05_5/AN13/TX1/SEG62
P05_4/AN12/RX1/INT2_R/SEG61
Vss
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
P07_2/SEG67/SCK3/AN18
P07_3/SEG68/AN19
Vcc
2
Vss
C
P03_7/INT1/SIN1/CS0/A20/SEG40
P13_0/INT2/SOT1/CS1/A21/SEG41
P13_1/INT3/SCK1/CS2/A22/SEG42
P13_2/PPG0/TIN0/FRCK1/CS3/A23/SEG43
P13_3/PPG1/TOT0/WOT/UBX/SEG44
P13_4/SIN0/INT6/SEG45
P13_5/SOT0/ADTG/INT7/SEG46
P13_6/SCK0/CKOTX0/LBX/SEG47
P13_7/PPG2/CKOT0/CS4/SEG48
P04_4/PPG3/SDA0
P04_5/PPG4/SCL0
P07_4/AN20/SEG69
P07_5/AN21/SEG70
P06_0/AN0/SCK5/IN2_R/SEG49
P06_1/AN1/SOT5/IN3_R/SEG50
P06_2/AN2/INT5/SIN5/SEG51
P06_3/AN3/FRCK0/SEG52
P06_4/AN4/IN0/TTG0/TTG4/SEG53
P06_5/AN5/IN1/TTG1/TTG5/SEG54
P06_6/AN6/TIN1/IN4_R/SEG55
P06_7/AN7/TOT1//IN5_R/SEG56
AVcc
AVRH
AVRL
AVss
P05_0/AN8/ALARM0/SEG57*2
P05_1/AN9/ALARM1/SEG58*2
P05_2/AN10/OUT2/SGO1/SEG59
P05_3/AN11/OUT3/SGA1/SEG60
P07_0/SEG65/SIN3/AN16
P07_1/SEG66/SOT3/AN17
1
Vcc
P10_3/PWM2M4/PPG7
P10_2/PWM2P4/SCK2/PPG6
P10_1/PWM1M4/SOT2/TOT3
P10_0/PWM1P4/SIN2/TIN3
P09_7/PWM2M3
DVss
DVcc
P10_7/PWM2M5
P10_6/PWM2P5
P09_6/PWM2P3
P09_5/PWM1M3
P09_4/PWM1P3
P09_3/PWM2M2
P09_2/PWM2P2
DVss
DVcc
P09_1/PWM1M2
P09_0/PWM1P2
P08_7/PWM2M1
P08_6/PWM2P1
P08_5/PWM1M1
P10_5/PWM1M5
P10_4/PWM1P5
DVss
DVcc
(FPT-144P-M08/FPT-144P-M12)
*2: No alarm comparator available on MB96375R
DS07-13807-2E
9
MB96370 Series
■ PIN FUNCTION DESCRIPTION
Pin Function description (1 of 3)
Pin name
Feature
Description
ADn
External bus
External bus interface (non multiplexed mode) data input/
output. External bus interface (multiplexed mode) address
output and data input/output
ADTG
ADC
A/D converter trigger input
ALARMn
Alarm comparator*1
Alarm Comparator n input
ALE
External bus
External bus Address Latch Enable output
An
External bus
External bus non-multiplexed address output
ANn
ADC
A/D converter channel n input
AVCC
Supply
Analog circuits power supply
AVRH
ADC
A/D converter high reference voltage input
AVRL
ADC
A/D converter low reference voltage input
AVSS
Supply
Analog circuits power supply
C
Voltage regulator
Internally regulated power supply stabilization capacitor pin
CKOTn
Clock output function
Clock Output function n output
CKOTn_R
Clock output function
Relocated Clock Output function n output
CKOTXn
Clock output function
Clock Output function n inverted output
CKOTXn_R
Clock output function
Relocated Clock Output function n inverted output
COMn
LCD
LCD COM pins
ECLK
External bus
External bus clock output
CSn
External bus
External bus chip select n output
CSn_R
External bus
Relocated External bus chip select n output
DVCC
Supply
SMC pins power supply
FRCKn
Free Running Timer
Free Running Timer n input
FRCKn_R
Free Running Timer
Relocated Free Running Timer n input
HAKX
External bus
External bus Hold Acknowledge
HRQ
External bus
External bus Hold Request
INn
ICU
Input Capture Unit n input
INn_R
ICU
Relocated Input Capture Unit n input
INTn
External Interrupt
External Interrupt n input
INTn_R
External Interrupt
Relocated External Interrupt n input
10
DS07-13807-2E
MB96370 Series
Pin Function description (2 of 3)
Pin name
Feature
Description
LBX
External bus
External Bus Interface Lower Byte select strobe output
MDn
Core
Input pins for specifying the operating mode.
NMI
External Interrupt
Non-Maskable Interrupt input
OUTn
OCU
Output Compare Unit n waveform output
OUTn_R
OCU
Relocated Output Compare Unit n waveform output
Pxx_n
GPIO
General purpose IO
PPGn
PPG
Programmable Pulse Generator n output
PPGn_R
PPG
Relocated Programmable Pulse Generator n output
PWMn
SMC
SMC PWM high current
RDX
External bus
External bus interface read strobe output
RDY
External bus
External bus interface external wait state request input
RSTX
Core
Reset input
RXn
CAN
CAN interface n RX input
SCKn
USART
USART n serial clock input/output
SCLn
I2C
I2C interface n clock I/O input/output
SDAn
I2C
I2C interface n serial data I/O input/output
SEGn
LCD
LCD segment n
SGAn
Sound Generator
SG amplitude output
SGOn
Sound Generator
SG sound/tone output
SGAn_R
Sound Generator
Relocated SG amplitude output
SGOn_R
Sound Generator
Relocated SG sound/tone output
SINn
USART
USART n serial data input
SOTn
USART
USART n serial data output
TINn
Reload Timer
Reload Timer n event input
TINn_R
Reload Timer
Relocated Reload Timer n event input
TOTn
Reload Timer
Reload Timer n output
TOTn_R
Reload Timer
Relocated Reload Timer n output
TTGn
PPG
Programmable Pulse Generator n trigger input
TXn
CAN
CAN interface n TX output
UBX
External bus
External Bus Interface Upper Byte select strobe output
DS07-13807-2E
11
MB96370 Series
Pin Function description (3 of 3)
Pin name
Feature
Description
Vn
LCD
LCD voltage references
VCC
Supply
Power supply
VSS
Supply
Power supply
WOT
RTC
Real Timer clock output
WRHX
External bus
External bus High byte write strobe output
WRLX/WRX
External bus
External bus Low byte / Word write strobe output
X0
Clock
Oscillator input
X0A
Clock
Subclock Oscillator input (only for devices with suffix "W")
X1
Clock
Oscillator output
X1A
Clock
Subclock Oscillator output (only for devices with suffix "W")
*1: No alarm comparator available on MB96375R.
12
DS07-13807-2E
MB96370 Series
■ PIN CIRCUIT TYPE
Pin circuit types (1 of 2)
FPT-144P-M08 or M12
Pin no.
Circuit
type *1
1
Supply
2
F
3 to 11
J
12, 13
N
14 to 23
K
24
Supply
25
G
26, 27
Supply
28 to 35
K
36,37
Supply
38 to 41
K
42 to 46
M
47, 48
Supply
49 to 55
M
56, 57
Supply
58 to 64
M
65, 66
Supply
67 to 71
M
72, 73
Supply
74 to 76
C
77, 78
A
79
Supply
80, 81
B *2
80, 81
H *3
82
E
83, 84
H
85 to 103
J
104 to 107
H
108, 109
Supply
DS07-13807-2E
13
MB96370 Series
Pin circuit types (2 of 2)
FPT-144P-M08 or M12
Pin no.
Circuit
type *1
110 to 130
J
131, 132
H
133 to 136
L
137 to 139
H
140, 141
N
142
J
143
H
144
Supply
*1: Please refer to “■ I/O CIRCUIT TYPE” for details on the I/O circuit types
*2: Devices with suffix ”W”
*3: Devices without suffix ”W”
14
DS07-13807-2E
MB96370 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
X1
R
A
0
Xout
MRFBE
1
High-speed oscillation circuit:
• Programmable between oscillation mode (external crystal or resonator connected to X0/X1
pins) and Fast external Clock Input (FCI) mode
(external clock connected to X0 pin)
• Programmable feedback resistor = approx.
2 * 0.5 MΩ. Feedback resistor is grounded in
the center when the oscillator is disabled or in
FCI mode
FCI
R
X0
FCI or osc disable
Xout
X1A
R
B
Low-speed oscillation circuit:
• Programmable feedback resistor = approx.
20 MΩ ( X1A:19.5 MΩ, X0A:0.5 MΩ). Feedback resistor is grounded in the center when
the oscillator is disabled
SRFBE
R
X0A
osc disable
C
R
Hysteresis
inputs
• Mask ROM and EVA device:
CMOS Hysteresis input pin
• Flash device:
CMOS input pin
• CMOS Hysteresis input pin
• Pull-up resistor value: approx. 50 kΩ
E
Pull-up
Resistor
R
DS07-13807-2E
Hysteresis
inputs
15
MB96370 Series
Type
Circuit
Remarks
• Power supply input protection circuit
2EJ
F
0EJ
ANE
2EJ
2EJ
G
0EJ
0EJ
AVR
ANE
pull-up control
P-ch
• A/D converter ref+ (AVRH) power supply input
pin with protection circuit
• Flash devices do not have a protection circuit
against VCC for pins AVRH
P-ch
Pout
N-ch
Nout
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
R
H
16
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Automotive input
Standby control
for input shutdown
TTL input
DS07-13807-2E
MB96370 Series
Type
Circuit
Remarks
pull-up control
P-ch
P-ch
Pout
N-ch
Nout
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
• SEG or COM output
R
J
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Automotive input
Standby control
for input shutdown
TTL input
SEG, COM output
pull-up control
P-ch
P-ch
Pout
N-ch
Nout
R
K
Standby control
for input shutdown
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function.
• Programmable pull-up resistor: 50kΩ approx.
• Analog input
• SEG output
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Automotive input
Standby control
for input shutdown
TTL input
Analog input
SEG output
DS07-13807-2E
17
MB96370 Series
Type
Circuit
Remarks
pull-up control
P-ch
P-ch
Pout
N-ch
Nout
R
L
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Automotive input
Standby control
for input shutdown
TTL input
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
• Analog input
• Vx input
• SEG output
Analog input
SEG output
Vx input
pull-up control
P-ch
P-ch
Pout
N-ch
Nout
• CMOS level output (programmable IOL = 5mA,
IOH = -5mA and IOL = 2mA, IOH = -2mA, IOL =
30mA, IOH = -30mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
R
M
18
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Automotive input
Standby control
for input shutdown
TTL input
DS07-13807-2E
MB96370 Series
Type
Circuit
Remarks
pull-up control
P-ch
P-ch
Pout
N-ch
Nout *1
R
N
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Hysteresis input
Standby control
for input shutdown
Automotive input
Standby control
for input shutdown
TTL input
DS07-13807-2E
• CMOS level output (IOL = 3mA, IOH = -3mA)
• 2 different CMOS hysteresis inputs with input
shutdown function
• Automotive input with input shutdown function
• TTL input with input shutdown function
• Programmable pull-up resistor: 50kΩ approx.
*1: N-channel transistor has slew rate control according to I2C spec, irrespective of usage.
Output fall time delay is defined in AC spec
of I2C as tof.
19
MB96370 Series
■ MEMORY MAP
MB96V300C
MB96(F)37x
Emulation ROM
USER ROM /
External Bus*4
External Bus
External Bus
Boot-ROM
Boot-ROM
FF:FFFFH
DE:0000H
10:0000H
0F:E000H
Reserved
0E:0000H
Reserved
External RAM
02:0000H
Internal RAM
bank 1
RAMEND1*2
RAMSTART1*2
01:0000H
ROM/RAM MIRROR
Reserved
Internal RAM
bank 1
Reserved
RAM availability depending on the device
ROM/RAM MIRROR
00:8000H
Internal RAM
bank 0
RAMSTART0
Internal RAM
bank 0
Reserved
External Bus end
address*2
External Bus
RAMSTART0*3
00:0C00H
*2
External Bus
Peripherals
Peripherals
GPR*1
GPR*1
DMA
DMA
External Bus
External Bus
Peripheral
Peripheral
00:0380H
00:0180H
00:0100H
00:00F0H
00:0000H
*1: Unused GPR banks can be used as RAM area
*2: For External Bus end address and RAMSTART/END addresses, please refer to the table on the next page.
*3: For EVA device, RAMSTART0 depends on the configuration of the emulated device.
*4: For details about USER ROM area, please refer to ■ USER ROM MEMORY MAP FOR FLASH DEVICES and
■ USER ROM MEMORY MAP FOR MASK ROM DEVICES on the following pages.
The External Bus area and DMA area are only available if the device contains the corresponding resource.
The available RAM and ROM area depends on the device.
20
DS07-13807-2E
MB96370 Series
■ RAMSTART/END AND EXTERNAL BUS END ADDRESSES
Devices
Bank 0
Bank 1 External Bus
RAM size RAM size end address
RAMSTART0
RAMSTART1 RAMEND1
MB96375
12KByte
-
00:51FFH
00:5240H
-
-
MB96F378
28KByte
-
00:11FFH
00:1240H
-
-
MB96F379
28KByte
4KByte
00:11FFH
00:1240H
01:8000H
01:8FFFH
DS07-13807-2E
21
MB96370 Series
■ USER ROM MEMORY MAP FOR FLASH DEVICES
CPU mode
address
FF:FFFFH
FF:0000H
FE:FFFFH
FE:0000H
FD:FFFFH
FD:0000H
FC:FFFFH
FC:0000H
FB:FFFFH
FB:0000H
FA:FFFFH
FA:0000H
F9:FFFFH
F9:0000H
F8:FFFFH
F8:0000H
F7:FFFFH
F7:0000H
F6:FFFFH
F6:0000H
F5:FFFFH
F5:0000H
F4:FFFFH
F4:0000H
F3:FFFFH
F3:0000H
F2:FFFFH
F2:0000H
F1:FFFFH
F1:0000H
F0:FFFFH
F0:0000H
E0:FFFFH
Flash memory
mode address
3F:FFFFH
3F:0000H
3E:FFFFH
3E:0000H
3D:FFFFH
3D:0000H
3C:FFFFH
3C:0000H
3B:FFFFH
3B:0000H
3A:FFFFH
3A:0000H
39:FFFFH
39:0000H
38:FFFFH
38:0000H
37:FFFFH
37:0000H
36:FFFFH
36:0000H
35:FFFFH
35:0000H
34:FFFFH
34:0000H
33:FFFFH
33:0000H
32:FFFFH
32:0000H
31:FFFFH
31:0000H
30:FFFFH
30:0000H
E0:0000H
DF:FFFFH
DF:8000H
DF:7FFFH
DF:6000H
DF:5FFFH
DF:4000H
DF:3FFFH
DF:2000H
DF:1FFFH
DF:0000H
DE:FFFFH
DE:8000H
DE:7FFFH
DE:6000H
DE:5FFFH
DE:4000H
DE:3FFFH
DE:2000H
DE:1FFFH
DE:0000H
1F:7FFFH
1F:6000H
1F:5FFFH
1F:4000H
1F:3FFFH
1F:2000H
1F:1FFFH
1F:0000H
1E:7FFFH
1E:6000H
1E:5FFFH
1E:4000H
1E:3FFFH
1E:2000H
1E:1FFFH
1E:0000H
MB96F378H
MB96F379R
Flash size
576KByte
Flash size
832KByte
S39 - 64K
S38 - 64K
S37 - 64K
S36 - 64K
S35 - 64K
S34 - 64K
S33 - 64K
S32 - 64K
S39 - 64K
S38 - 64K
S37 - 64K
S36 - 64K
S35 - 64K
S34 - 64K
S33 - 64K
S32 - 64K
S31 - 64K
S30 - 64K
S29 - 64K
S28 - 64K
Flash A
Flash B
External bus
External bus
Reserved
Reserved
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K *1
SA3 - 8K
SA2 - 8K
SA1 - 8K
SA0 - 8K *1
Reserved
Reserved
SB3 - 8K
SB2 - 8K
SB1 - 8K
SB0 - 8K *2
SB3 - 8K
SB2 - 8K
SB1 - 8K
SB0 - 8K *2
Flash A
Flash B
*1: Sector SA0 contains the ROM Configuration Block RCBA at CPU address DF:0000H - DF:007FH
*2: Sector SB0 contains the ROM Configuration Block RCBB at CPU address DE:0000H - DE:002FH
22
DS07-13807-2E
MB96370 Series
■ USER ROM MEMORY MAP FOR MASK ROM DEVICES
MB96375R
CPU address
ROM size
160KByte
FF:FFFFH
FF:0000H
FE:FFFFH
128K ROM
FE:0000H
FD:FFFFH
External bus
E0:0000H
DF:FFFFH
Reserved
DF:8000H
DF:7FFFH
32K ROM
DF:0080H
DF:007FH
DF:0000H
DE:FFFFH
ROM configuration
block RCB
Reserved
DE:0000H
DS07-13807-2E
23
MB96370 Series
■ SERIAL PROGRAMMING COMMUNICATION INTERFACE
USART pins for Flash serial programming (MD[2:0] = 010)
MB96F37x
Pin number
USART Number
Normal function
LQFP-144
8
9
SIN0
USART0
SOT0
10
SCK0
3
SIN1
4
USART1
SOT1
5
SCK1
68
SIN2
69
USART2
SOT2
70
SCK2
32
SIN3
33
34
USART3
SOT3
SCK3
Note: If a Flash programmer and its software need to use a handshaking pin, Fujitsu suggests to the tool vendor
to support at least port P00_1 on pin 102.
If handshaking is used by the tool but P00_1 is not available in customer’s application, Fujitsu suggests to the
customer to check the tool manual or to contact the tool vendor for alternative handshaking pins.
24
DS07-13807-2E
MB96370 Series
■ I/O MAP
I/O map MB96(F)37x (1 of 34)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000000H
I/O Port P00 - Port Data Register
PDR00
R/W
000001H
I/O Port P01 - Port Data Register
PDR01
R/W
000002H
I/O Port P02 - Port Data Register
PDR02
R/W
000003H
I/O Port P03 - Port Data Register
PDR03
R/W
000004H
I/O Port P04 - Port Data Register
PDR04
R/W
000005H
I/O Port P05 - Port Data Register
PDR05
R/W
000006H
I/O Port P06 - Port Data Register
PDR06
R/W
000007H
I/O Port P07 - Port Data Register
PDR07
R/W
000008H
I/O Port P08 - Port Data Register
PDR08
R/W
000009H
I/O Port P09 - Port Data Register
PDR09
R/W
00000AH
I/O Port P10 - Port Data Register
PDR10
R/W
00000BH
I/O Port P11 - Port Data Register
PDR11
R/W
00000CH
I/O Port P12 - Port Data Register
PDR12
R/W
00000DH
I/O Port P13 - Port Data Register
PDR13
R/W
00000EH00000FH
Reserved
000010H
I/O Port P16 - Port Data Register
000011H000017H
Reserved
000018H
ADC0 - Control Status register Low
ADCSL
000019H
ADC0 - Control Status register High
ADCSH
00001AH
ADC0 - Data Register Low
ADCRL
00001BH
ADC0 - Data Register High
ADCRH
00001CH
ADC0 - Setting Register
00001DH
ADC0 - Setting Register
00001EH
ADC0 - Extended Configuration Register
00001FH
Reserved
000020H
FRT0 - Data register of free-running timer
000021H
FRT0 - Data register of free-running timer
DS07-13807-2E
PDR16
R/W
ADCS
R/W
R/W
ADCR
R
R
ADSR
R/W
R/W
ADECR
R/W
TCDT0
R/W
R/W
25
MB96370 Series
I/O map MB96(F)37x (2 of 34)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000022H
FRT0 - Control status register of free-running timer Low
TCCSL0
TCCS0
R/W
000023H
FRT0 - Control status register of free-running timer High
TCCSH0
000024H
FRT1 - Data register of free-running timer
000025H
FRT1 - Data register of free-running timer
000026H
FRT1 - Control status register of free-running timer Low
TCCSL1
000027H
FRT1 - Control status register of free-running timer High
TCCSH1
R/W
000028H
OCU0 - Output Compare Control Status
OCS0
R/W
000029H
OCU1 - Output Compare Control Status
OCS1
R/W
00002AH
OCU0 - Compare Register
00002BH
OCU0 - Compare Register
00002CH
OCU1 - Compare Register
00002DH
OCU1 - Compare Register
00002EH
OCU2 - Output Compare Control Status
OCS2
R/W
00002FH
OCU3 - Output Compare Control Status
OCS3
R/W
000030H
OCU2 - Compare Register
000031H
OCU2 - Compare Register
000032H
OCU3 - Compare Register
000033H
OCU3 - Compare Register
000034H
OCU4 - Output Compare Control Status
OCS4
R/W
000035H
OCU5 - Output Compare Control Status
OCS5
R/W
000036H
OCU4 - Compare Register
000037H
OCU4 - Compare Register
000038H
OCU5 - Compare Register
000039H
OCU5 - Compare Register
00003AH00003FH
Reserved
000040H
ICU0/ICU1 - Control Status Register
ICS01
R/W
000041H
ICU0/ICU1 - Edge register
ICE01
R/W
26
R/W
TCDT1
R/W
R/W
TCCS1
OCCP0
R/W
R/W
R/W
OCCP1
R/W
R/W
OCCP2
R/W
R/W
OCCP3
R/W
R/W
OCCP4
R/W
R/W
OCCP5
R/W
R/W
-
DS07-13807-2E
MB96370 Series
I/O map MB96(F)37x (3 of 34)
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
ICU0 - Capture Register Low
IPCPL0
IPCP0
R
000043H
ICU0 - Capture Register High
IPCPH0
000044H
ICU1 - Capture Register Low
IPCPL1
000045H
ICU1 - Capture Register High
IPCPH1
R
000046H
ICU2/ICU3 - Control Status Register
ICS23
R/W
000047H
ICU2/ICU3 - Edge register
ICE23
R/W
000048H
ICU2 - Capture Register Low
IPCPL2
000049H
ICU2 - Capture Register High
IPCPH2
00004AH
ICU3 - Capture Register Low
IPCPL3
00004BH
ICU3 - Capture Register High
IPCPH3
R
00004CH
ICU4/ICU5 - Control Status Register
ICS45
R/W
00004DH
ICU4/ICU5 - Edge register
ICE45
R/W
00004EH
ICU4 - Capture Register Low
IPCPL4
00004FH
ICU4 - Capture Register High
IPCPH4
000050H
ICU5 - Capture Register Low
IPCPL5
000051H
ICU5 - Capture Register High
IPCPH5
R
000052H
ICU6/ICU7 - Control Status Register
ICS67
R/W
000053H
ICU6/ICU7 - Edge register
ICE67
R/W
000054H
ICU6 - Capture Register Low
IPCPL6
000055H
ICU6 - Capture Register High
IPCPH6
000056H
ICU7 - Capture Register Low
IPCPL7
000057H
ICU7 - Capture Register High
IPCPH7
R
000058H
EXTINT0 - External Interrupt Enable Register
ENIR0
R/W
000059H
EXTINT0 - External Interrupt Interrupt request
Register
EIRR0
R/W
00005AH
EXTINT0 - External Interrupt Level Select Low
ELVRL0
00005BH
EXTINT0 - External Interrupt Level Select High
ELVRH0
00005CH00005FH
Reserved
000060H
RLT0 - Timer Control Status Register Low
TMCSRL0
000061H
RLT0 - Timer Control Status Register High
TMCSRH0
Address
Register
000042H
DS07-13807-2E
R
IPCP1
IPCP2
R
R
R
IPCP3
IPCP4
R
R
R
IPCP5
IPCP6
R
R
R
IPCP7
ELVR0
R
R/W
R/W
-
TMCSR0
R/W
R/W
27
MB96370 Series
I/O map MB96(F)37x (4 of 34)
Address
28
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000062H
RLT0 - Reload Register - for writing
TMRLR0
W
000062H
RLT0 - Reload Register - for reading
TMR0
R
000063H
RLT0 - Reload Register - for writing
W
000063H
RLT0 - Reload Register - for reading
R
000064H
RLT1 - Timer Control Status Register Low
TMCSRL1
000065H
RLT1 - Timer Control Status Register High
TMCSRH1
000066H
RLT1 - Reload Register - for writing
TMRLR1
W
000066H
RLT1 - Reload Register - for reading
TMR1
R
000067H
RLT1 - Reload Register - for writing
W
000067H
RLT1 - Reload Register - for reading
R
000068H
RLT2 - Timer Control Status Register Low
TMCSRL2
000069H
RLT2 - Timer Control Status Register High
TMCSRH2
00006AH
RLT2 - Reload Register - for writing
TMRLR2
W
00006AH
RLT2 - Reload Register - for reading
TMR2
R
00006BH
RLT2 - Reload Register - for writing
W
00006BH
RLT2 - Reload Register - for reading
R
00006CH
RLT3 - Timer Control Status Register Low
TMCSRL3
00006DH
RLT3 - Timer Control Status Register High
TMCSRH3
00006EH
RLT3 - Reload Register - for writing
TMRLR3
W
00006EH
RLT3 - Reload Register - for reading
TMR3
R
00006FH
RLT3 - Reload Register - for writing
W
00006FH
RLT3 - Reload Register - for reading
R
000070H
RLT6 - Timer Control Status Register Low (dedic.
RLT for PPG)
TMCSRL6
000071H
RLT6 - Timer Control Status Register High
(dedic. RLT for PPG)
TMCSRH6
000072H
RLT6 - Reload Register (dedic. RLT for PPG) - for
writing
TMRLR6
W
000072H
RLT6 - Reload Register (dedic. RLT for PPG) - for
reading
TMR6
R
000073H
RLT6 - Reload Register (dedic. RLT for PPG) - for
writing
TMCSR1
R/W
R/W
TMCSR2
R/W
R/W
TMCSR3
R/W
R/W
TMCSR6
R/W
R/W
W
DS07-13807-2E
MB96370 Series
I/O map MB96(F)37x (5 of 34)
Abbreviation
8-bit access
Address
Register
000073H
RLT6 - Reload Register (dedic. RLT for PPG) - for
reading
000074H
PPG3-PPG0 - General Control register 1 Low
GCN1L0
000075H
PPG3-PPG0 - General Control register 1 High
GCN1H0
000076H
PPG3-PPG0 - General Control register 2 Low
GCN2L0
000077H
PPG3-PPG0 - General Control register 2 High
GCN2H0
000078H
PPG0 - Timer register
000079H
PPG0 - Timer register
00007AH
PPG0 - Period setting register
00007BH
PPG0 - Period setting register
00007CH
PPG0 - Duty cycle register
00007DH
PPG0 - Duty cycle register
00007EH
PPG0 - Control status register Low
PCNL0
00007FH
PPG0 - Control status register High
PCNH0
000080H
PPG1 - Timer register
000081H
PPG1 - Timer register
000082H
PPG1 - Period setting register
000083H
PPG1 - Period setting register
000084H
PPG1 - Duty cycle register
000085H
PPG1 - Duty cycle register
000086H
PPG1 - Control status register Low
PCNL1
000087H
PPG1 - Control status register High
PCNH1
000088H
PPG2 - Timer register
000089H
PPG2 - Timer register
00008AH
PPG2 - Period setting register
00008BH
PPG2 - Period setting register
00008CH
PPG2 - Duty cycle register
00008DH
PPG2 - Duty cycle register
00008EH
PPG2 - Control status register Low
PCNL2
00008FH
PPG2 - Control status register High
PCNH2
DS07-13807-2E
Abbreviation
16-bit access
Access
R
GCN10
R/W
R/W
GCN20
R/W
R/W
PTMR0
R
R
PCSR0
W
W
PDUT0
W
W
PCN0
R/W
R/W
PTMR1
R
R
PCSR1
W
W
PDUT1
W
W
PCN1
R/W
R/W
PTMR2
R
R
PCSR2
W
W
PDUT2
W
W
PCN2
R/W
R/W
29
MB96370 Series
I/O map MB96(F)37x (6 of 34)
Address
30
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
PTMR3
R
000090H
PPG3 - Timer register
000091H
PPG3 - Timer register
000092H
PPG3 - Period setting register
000093H
PPG3 - Period setting register
000094H
PPG3 - Duty cycle register
000095H
PPG3 - Duty cycle register
000096H
PPG3 - Control status register Low
PCNL3
000097H
PPG3 - Control status register High
PCNH3
000098H
PPG7-PPG4 - General Control register 1 Low
GCN1L1
000099H
PPG7-PPG4 - General Control register 1 High
GCN1H1
00009AH
PPG7-PPG4 - General Control register 2 Low
GCN2L1
00009BH
PPG7-PPG4 - General Control register 2 High
GCN2H1
00009CH
PPG4 - Timer register
00009DH
PPG4 - Timer register
00009EH
PPG4 - Period setting register
00009FH
PPG4 - Period setting register
0000A0H
PPG4 - Duty cycle register
0000A1H
PPG4 - Duty cycle register
0000A2H
PPG4 - Control status register Low
PCNL4
0000A3H
PPG4 - Control status register High
PCNH4
0000A4H
PPG5 - Timer register
0000A5H
PPG5 - Timer register
0000A6H
PPG5 - Period setting register
0000A7H
PPG5 - Period setting register
0000A8H
PPG5 - Duty cycle register
0000A9H
PPG5 - Duty cycle register
0000AAH
PPG5 - Control status register Low
PCNL5
0000ABH
PPG5 - Control status register High
PCNH5
R/W
0000ACH
I2C0 - Bus Status Register
IBSR0
R
0000ADH
I2C0 - Bus Control Register
IBCR0
R/W
R
PCSR3
W
W
PDUT3
W
W
PCN3
R/W
R/W
GCN11
R/W
R/W
GCN21
R/W
R/W
PTMR4
R
R
PCSR4
W
W
PDUT4
W
W
PCN4
R/W
R/W
PTMR5
R
R
PCSR5
W
W
PDUT5
W
W
PCN5
R/W
DS07-13807-2E
MB96370 Series
I/O map MB96(F)37x (7 of 34)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
ITBA0
R/W
0000AEH
I2C0 - Ten bit Slave address Register Low
ITBAL0
0000AFH
I2C0 - Ten bit Slave address Register High
ITBAH0
0000B0H
I2C0 - Ten bit Address mask Register Low
ITMKL0
0000B1H
I2C0 - Ten bit Address mask Register High
ITMKH0
R/W
0000B2H
I2C0 - Seven bit Slave address Register
ISBA0
R/W
0000B3H
I2C0 - Seven bit Address mask Register
ISMK0
R/W
0000B4H
I2C0 - Data Register
IDAR0
R/W
0000B5H
I2C0 - Clock Control Register
ICCR0
R/W
0000B6H
I2C1 - Bus Status Register
IBSR1
R
0000B7H
I2C1 - Bus Control Register
IBCR1
R/W
0000B8H
I2C1 - Ten bit Slave address Register Low
ITBAL1
0000B9H
I2C1 - Ten bit Slave address Register High
ITBAH1
0000BAH
I2C1 - Ten bit Address mask Register Low
ITMKL1
0000BBH
I2C1 - Ten bit Address mask Register High
ITMKH1
R/W
0000BCH
I2C1 - Seven bit Slave address Register
ISBA1
R/W
0000BDH
I2C1 - Seven bit Address mask Register
ISMK1
R/W
0000BEH
I2C1 - Data Register
IDAR1
R/W
0000BFH
I2C1 - Clock Control Register
ICCR1
R/W
0000C0H
USART0 - Serial Mode Register
SMR0
R/W
0000C1H
USART0 - Serial Control Register
SCR0
R/W
0000C2H
USART0 - TX Register
TDR0
W
0000C2H
USART0 - RX Register
RDR0
R
0000C3H
USART0 - Serial Status
SSR0
R/W
0000C4H
USART0 - Control/Com. Register
ECCR0
R/W
0000C5H
USART0 - Ext. Status Register
ESCR0
R/W
0000C6H
USART0 - Baud Rate Generator Register Low
BGRL0
0000C7H
USART0 - Baud Rate Generator Register High
BGRH0
R/W
0000C8H
USART0 - Extended Serial Interrupt Register
ESIR0
R/W
0000C9H
Reserved
0000CAH
USART1 - Serial Mode Register
DS07-13807-2E
R/W
ITMK0
ITBA1
R/W
R/W
R/W
ITMK1
BGR0
R/W
R/W
SMR1
R/W
31
MB96370 Series
I/O map MB96(F)37x (8 of 34)
Address
32
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0000CBH
USART1 - Serial Control Register
SCR1
R/W
0000CCH
USART1 - TX Register
TDR1
W
0000CCH
USART1 - RX Register
RDR1
R
0000CDH
USART1 - Serial Status
SSR1
R/W
0000CEH
USART1 - Control/Com. Register
ECCR1
R/W
0000CFH
USART1 - Ext. Status Register
ESCR1
R/W
0000D0H
USART1 - Baud Rate Generator Register Low
BGRL1
0000D1H
USART1 - Baud Rate Generator Register High
BGRH1
R/W
0000D2H
USART1 - Extended Serial Interrupt Register
ESIR1
R/W
0000D3H
Reserved
0000D4H
USART2 - Serial Mode Register
SMR2
R/W
0000D5H
USART2 - Serial Control Register
SCR2
R/W
0000D6H
USART2 - TX Register
TDR2
W
0000D6H
USART2 - RX Register
RDR2
R
0000D7H
USART2 - Serial Status
SSR2
R/W
0000D8H
USART2 - Control/Com. Register
ECCR2
R/W
0000D9H
USART2 - Ext. Status Register
ESCR2
R/W
0000DAH
USART2 - Baud Rate Generator Register Low
BGRL2
0000DBH
USART2 - Baud Rate Generator Register High
BGRH2
R/W
0000DCH
USART2 - Extended Serial Interrupt Register
ESIR2
R/W
0000DDH
Reserved
0000DEH
USART3 - Serial Mode Register
SMR3
R/W
0000DFH
USART3 - Serial Control Register
SCR3
R/W
0000E0H
USART3 - TX Register
TDR3
W
0000E0H
USART3 - RX Register
RDR3
R
0000E1H
USART3 - Serial Status
SSR3
R/W
0000E2H
USART3 - Control/Com. Register
ECCR3
R/W
0000E3H
USART3 - Ext. Status Register
ESCR3
R/W
0000E4H
USART3 - Baud Rate Generator Register Low
BGRL3
0000E5H
USART3 - Baud Rate Generator Register High
BGRH3
BGR1
R/W
-
BGR2
R/W
-
BGR3
R/W
R/W
DS07-13807-2E
MB96370 Series
I/O map MB96(F)37x (9 of 34)
Address
Register
0000E6H
USART3 - Extended Serial Interrupt Register
0000E7H0000EFH
Reserved
0000F0H0000FFH
External Bus area
000100H
Abbreviation
8-bit access
Abbreviation
16-bit access
ESIR3
Access
R/W
-
EXTBUS0
R/W
DMA0 - Buffer address pointer low byte
BAPL0
R/W
000101H
DMA0 - Buffer address pointer middle byte
BAPM0
R/W
000102H
DMA0 - Buffer address pointer high byte
BAPH0
R/W
000103H
DMA0 - DMA control register
DMACS0
R/W
000104H
DMA0 - I/O register address pointer low byte
IOAL0
000105H
DMA0 - I/O register address pointer high byte
IOAH0
000106H
DMA0 - Data counter low byte
DCTL0
000107H
DMA0 - Data counter high byte
DCTH0
R/W
000108H
DMA1 - Buffer address pointer low byte
BAPL1
R/W
000109H
DMA1 - Buffer address pointer middle byte
BAPM1
R/W
00010AH
DMA1 - Buffer address pointer high byte
BAPH1
R/W
00010BH
DMA1 - DMA control register
DMACS1
R/W
00010CH
DMA1 - I/O register address pointer low byte
IOAL1
00010DH
DMA1 - I/O register address pointer high byte
IOAH1
00010EH
DMA1 - Data counter low byte
DCTL1
00010FH
DMA1 - Data counter high byte
DCTH1
R/W
000110H
DMA2 - Buffer address pointer low byte
BAPL2
R/W
000111H
DMA2 - Buffer address pointer middle byte
BAPM2
R/W
000112H
DMA2 - Buffer address pointer high byte
BAPH2
R/W
000113H
DMA2 - DMA control register
DMACS2
R/W
000114H
DMA2 - I/O register address pointer low byte
IOAL2
000115H
DMA2 - I/O register address pointer high byte
IOAH2
000116H
DMA2 - Data counter low byte
DCTL2
000117H
DMA2 - Data counter high byte
DCTH2
R/W
000118H
DMA3 - Buffer address pointer low byte
BAPL3
R/W
000119H
DMA3 - Buffer address pointer middle byte
BAPM3
R/W
DS07-13807-2E
IOA0
R/W
R/W
DCT0
IOA1
R/W
R/W
R/W
DCT1
IOA2
R/W
R/W
R/W
DCT2
R/W
33
MB96370 Series
I/O map MB96(F)37x (10 of 34)
Address
34
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
00011AH
DMA3 - Buffer address pointer high byte
BAPH3
R/W
00011BH
DMA3 - DMA control register
DMACS3
R/W
00011CH
DMA3 - I/O register address pointer low byte
IOAL3
00011DH
DMA3 - I/O register address pointer high byte
IOAH3
00011EH
DMA3 - Data counter low byte
DCTL3
00011FH
DMA3 - Data counter high byte
DCTH3
R/W
000120H
DMA4 - Buffer address pointer low byte
BAPL4
R/W
000121H
DMA4 - Buffer address pointer middle byte
BAPM4
R/W
000122H
DMA4 - Buffer address pointer high byte
BAPH4
R/W
000123H
DMA4 - DMA control register
DMACS4
R/W
000124H
DMA4 - I/O register address pointer low byte
IOAL4
000125H
DMA4 - I/O register address pointer high byte
IOAH4
000126H
DMA4 - Data counter low byte
DCTL4
000127H
DMA4 - Data counter high byte
DCTH4
R/W
000128H
DMA5 - Buffer address pointer low byte
BAPL5
R/W
000129H
DMA5 - Buffer address pointer middle byte
BAPM5
R/W
00012AH
DMA5 - Buffer address pointer high byte
BAPH5
R/W
00012BH
DMA5 - DMA control register
DMACS5
R/W
00012CH
DMA5 - I/O register address pointer low byte
IOAL5
00012DH
DMA5 - I/O register address pointer high byte
IOAH5
00012EH
DMA5 - Data counter low byte
DCTL5
00012FH
DMA5 - Data counter high byte
DCTH5
R/W
000130H
DMA6 - Buffer address pointer low byte
BAPL6
R/W
000131H
DMA6 - Buffer address pointer middle byte
BAPM6
R/W
000132H
DMA6 - Buffer address pointer high byte
BAPH6
R/W
000133H
DMA6 - DMA control register
DMACS6
R/W
000134H
DMA6 - I/O register address pointer low byte
IOAL6
000135H
DMA6 - I/O register address pointer high byte
IOAH6
000136H
DMA6 - Data counter low byte
DCTL6
000137H
DMA6 - Data counter high byte
DCTH6
IOA3
R/W
R/W
DCT3
IOA4
R/W
R/W
R/W
DCT4
IOA5
R/W
R/W
R/W
DCT5
IOA6
R/W
R/W
R/W
DCT6
R/W
R/W
DS07-13807-2E
MB96370 Series
I/O map MB96(F)37x (11 of 34)
Address
Register
000138H00017FH
Reserved
000180H00037FH
CPU - General-Purpose registers (RAM access)
000380H
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
-
GPR_RAM
R/W
DMA0 - Interrupt select
DISEL0
R/W
000381H
DMA1 - Interrupt select
DISEL1
R/W
000382H
DMA2 - Interrupt select
DISEL2
R/W
000383H
DMA3 - Interrupt select
DISEL3
R/W
000384H
DMA4 - Interrupt select
DISEL4
R/W
000385H
DMA5 - Interrupt select
DISEL5
R/W
000386H
DMA6 - Interrupt select
DISEL6
R/W
000387H00038FH
Reserved
000390H
DMA - Status register low byte
DSRL
000391H
DMA - Status register high byte
DSRH
000392H
DMA - Stop status register low byte
DSSRL
000393H
DMA - Stop status register high byte
DSSRH
000394H
DMA - Enable register low byte
DERL
000395H
DMA - Enable register high byte
DERH
000396H00039FH
Reserved
0003A0H
Interrupt level register
ILR
0003A1H
Interrupt index register
IDX
0003A2H
Interrupt vector table base register Low
TBRL
0003A3H
Interrupt vector table base register High
TBRH
R/W
0003A4H
Delayed Interrupt register
DIRR
R/W
0003A5H
Non Maskable Interrupt register
NMI
R/W
0003A6H0003ABH
Reserved
0003ACH
EDSU communication interrupt selection Low
EDSU2L
0003ADH
EDSU communication interrupt selection High
EDSU2H
R/W
0003AEH
ROM mirror control register
ROMM
R/W
DS07-13807-2E
DSR
R/W
R/W
DSSR
R/W
R/W
DER
R/W
R/W
-
ICR
R/W
R/W
TBR
R/W
EDSU2
R/W
35
MB96370 Series
I/O map MB96(F)37x (12 of 34)
Address
36
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
EDSU
Access
0003AFH
EDSU configuration register
R/W
0003B0H
Memory patch control/status register ch 0/1
0003B1H
Memory patch control/status register ch 0/1
0003B2H
Memory patch control/status register ch 2/3
0003B3H
Memory patch control/status register ch 2/3
0003B4H
Memory patch control/status register ch 4/5
0003B5H
Memory patch control/status register ch 4/5
0003B6H
Memory patch control/status register ch 6/7
0003B7H
Memory patch control/status register ch 6/7
0003B8H
Memory Patch function - Patch address 0 low
PFAL0
R/W
0003B9H
Memory Patch function - Patch address 0 middle
PFAM0
R/W
0003BAH
Memory Patch function - Patch address 0 high
PFAH0
R/W
0003BBH
Memory Patch function - Patch address 1 low
PFAL1
R/W
0003BCH
Memory Patch function - Patch address 1 middle
PFAM1
R/W
0003BDH
Memory Patch function - Patch address 1 high
PFAH1
R/W
0003BEH
Memory Patch function - Patch address 2 low
PFAL2
R/W
0003BFH
Memory Patch function - Patch address 2 middle
PFAM2
R/W
0003C0H
Memory Patch function - Patch address 2 high
PFAH2
R/W
0003C1H
Memory Patch function - Patch address 3 low
PFAL3
R/W
0003C2H
Memory Patch function - Patch address 3 middle
PFAM3
R/W
0003C3H
Memory Patch function - Patch address 3 high
PFAH3
R/W
0003C4H
Memory Patch function - Patch address 4 low
PFAL4
R/W
0003C5H
Memory Patch function - Patch address 4 middle
PFAM4
R/W
0003C6H
Memory Patch function - Patch address 4 high
PFAH4
R/W
0003C7H
Memory Patch function - Patch address 5 low
PFAL5
R/W
0003C8H
Memory Patch function - Patch address 5 middle
PFAM5
R/W
0003C9H
Memory Patch function - Patch address 5 high
PFAH5
R/W
0003CAH
Memory Patch function - Patch address 6 low
PFAL6
R/W
0003CBH
Memory Patch function - Patch address 6 middle
PFAM6
R/W
0003CCH
Memory Patch function - Patch address 6 high
PFAH6
R/W
PFCS0
R/W
R/W
PFCS1
R/W
R/W
PFCS2
R/W
R/W
PFCS3
R/W
R/W
DS07-13807-2E
MB96370 Series
I/O map MB96(F)37x (13 of 34)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0003CDH
Memory Patch function - Patch address 7 low
PFAL7
R/W
0003CEH
Memory Patch function - Patch address 7 middle
PFAM7
R/W
0003CFH
Memory Patch function - Patch address 7 high
PFAH7
R/W
0003D0H
Memory Patch function - Patch data 0 Low
PFDL0
0003D1H
Memory Patch function - Patch data 0 High
PFDH0
0003D2H
Memory Patch function - Patch data 1 Low
PFDL1
0003D3H
Memory Patch function - Patch data 1 High
PFDH1
0003D4H
Memory Patch function - Patch data 2 Low
PFDL2
0003D5H
Memory Patch function - Patch data 2 High
PFDH2
0003D6H
Memory Patch function - Patch data 3 Low
PFDL3
0003D7H
Memory Patch function - Patch data 3 High
PFDH3
0003D8H
Memory Patch function - Patch data 4 Low
PFDL4
0003D9H
Memory Patch function - Patch data 4 High
PFDH4
0003DAH
Memory Patch function - Patch data 5 Low
PFDL5
0003DBH
Memory Patch function - Patch data 5 High
PFDH5
0003DCH
Memory Patch function - Patch data 6 Low
PFDL6
0003DDH
Memory Patch function - Patch data 6 High
PFDH6
0003DEH
Memory Patch function - Patch data 7 Low
PFDL7
0003DFH
Memory Patch function - Patch data 7 High
PFDH7
0003E0H0003F0H
Reserved
0003F1H
Memory Control Status Register A
MCSRA
0003F2H
Memory Timing Configuration Register A Low
MTCRAL
0003F3H
Memory Timing Configuration Register A High
MTCRAH
0003F4H
Reserved
0003F5H
Memory Control Status Register B
MCSRB
0003F6H
Memory Timing Configuration Register B Low
MTCRBL
0003F7H
Memory Timing Configuration Register B High
MTCRBH
R/W
0003F8H
Flash Memory Write Control register 0
FMWC0
R/W
0003F9H
Flash Memory Write Control register 1
FMWC1
R/W
DS07-13807-2E
PFD0
R/W
R/W
PFD1
R/W
R/W
PFD2
R/W
R/W
PFD3
R/W
R/W
PFD4
R/W
R/W
PFD5
R/W
R/W
PFD6
R/W
R/W
PFD7
R/W
R/W
R/W
MTCRA
R/W
R/W
R/W
MTCRB
R/W
37
MB96370 Series
I/O map MB96(F)37x (14 of 34)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0003FAH
Flash Memory Write Control register 2
FMWC2
R/W
0003FBH
Flash Memory Write Control register 3
FMWC3
R/W
0003FCH
Flash Memory Write Control register 4
FMWC4
R/W
0003FDH
Flash Memory Write Control register 5
FMWC5
R/W
0003FEH0003FFH
Reserved
000400H
Standby Mode control register
SMCR
R/W
000401H
Clock select register
CKSR
R/W
000402H
Clock Stabilization select register
CKSSR
R/W
000403H
Clock monitor register
CKMR
R
000404H
Clock Frequency control register Low
CKFCRL
000405H
Clock Frequency control register High
CKFCRH
000406H
PLL Control register Low
PLLCRL
000407H
PLL Control register High
PLLCRH
R/W
000408H
RC clock timer control register
RCTCR
R/W
000409H
Main clock timer control register
MCTCR
R/W
00040AH
Sub clock timer control register
SCTCR
R/W
00040BH
Reset cause and clock status register with clear
function
RCCSRC
R
00040CH
Reset configuration register
RCR
R/W
00040DH
Reset cause and clock status register
RCCSR
R
00040EH
Watchdog timer configuration register
WDTC
R/W
00040FH
Watchdog timer clear pattern register
WDTCP
W
000410H000414H
Reserved
000415H
Clock output activation register
000416H
38
-
CKFCR
R/W
R/W
PLLCR
R/W
COAR
R/W
Clock output configuration register 0
COCR0
R/W
000417H
Clock output configuration register 1
COCR1
R/W
000418H
Clock Modulator control register
CMCR
R/W
000419H
Reserved
00041AH
Clock Modulator Parameter register Low
CMPRL
CMPR
R/W
DS07-13807-2E
MB96370 Series
I/O map MB96(F)37x (15 of 34)
Address
Register
Abbreviation
8-bit access
Access
00041BH
Clock Modulator Parameter register High
00041CH00042BH
Reserved
00042CH
Voltage Regulator Control register
VRCR
R/W
00042DH
Clock Input and LVD Control Register
CILCR
R/W
00042EH00042FH
Reserved
000430H
I/O Port P00 - Data Direction Register
DDR00
R/W
000431H
I/O Port P01 - Data Direction Register
DDR01
R/W
000432H
I/O Port P02 - Data Direction Register
DDR02
R/W
000433H
I/O Port P03 - Data Direction Register
DDR03
R/W
000434H
I/O Port P04 - Data Direction Register
DDR04
R/W
000435H
I/O Port P05 - Data Direction Register
DDR05
R/W
000436H
I/O Port P06 - Data Direction Register
DDR06
R/W
000437H
I/O Port P07 - Data Direction Register
DDR07
R/W
000438H
I/O Port P08 - Data Direction Register
DDR08
R/W
000439H
I/O Port P09 - Data Direction Register
DDR09
R/W
00043AH
I/O Port P10 - Data Direction Register
DDR10
R/W
00043BH
I/O Port P11 - Data Direction Register
DDR11
R/W
00043CH
I/O Port P12 - Data Direction Register
DDR12
R/W
00043DH
I/O Port P13 - Data Direction Register
DDR13
R/W
00043EH00043FH
Reserved
000440H
I/O Port P16 - Data Direction Register
000441H000443H
Reserved
000444H
I/O Port P00 - Port Input Enable Register
PIER00
R/W
000445H
I/O Port P01 - Port Input Enable Register
PIER01
R/W
000446H
I/O Port P02 - Port Input Enable Register
PIER02
R/W
000447H
I/O Port P03 - Port Input Enable Register
PIER03
R/W
000448H
I/O Port P04 - Port Input Enable Register
PIER04
R/W
DS07-13807-2E
CMPRH
Abbreviation
16-bit access
R/W
-
-
DDR16
R/W
-
39
MB96370 Series
I/O map MB96(F)37x (16 of 34)
Address
40
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000449H
I/O Port P05 - Port Input Enable Register
PIER05
R/W
00044AH
I/O Port P06 - Port Input Enable Register
PIER06
R/W
00044BH
I/O Port P07 - Port Input Enable Register
PIER07
R/W
00044CH
I/O Port P08 - Port Input Enable Register
PIER08
R/W
00044DH
I/O Port P09 - Port Input Enable Register
PIER09
R/W
00044EH
I/O Port P10 - Port Input Enable Register
PIER10
R/W
00044FH
I/O Port P11 - Port Input Enable Register
PIER11
R/W
000450H
I/O Port P12 - Port Input Enable Register
PIER12
R/W
000451H
I/O Port P13 - Port Input Enable Register
PIER13
R/W
000452H000453H
Reserved
000454H
I/O Port P16 - Port Input Enable Register
000455H000457H
Reserved
000458H
I/O Port P00 - Port Input Level Register
PILR00
R/W
000459H
I/O Port P01 - Port Input Level Register
PILR01
R/W
00045AH
I/O Port P02 - Port Input Level Register
PILR02
R/W
00045BH
I/O Port P03 - Port Input Level Register
PILR03
R/W
00045CH
I/O Port P04 - Port Input Level Register
PILR04
R/W
00045DH
I/O Port P05 - Port Input Level Register
PILR05
R/W
00045EH
I/O Port P06 - Port Input Level Register
PILR06
R/W
00045FH
I/O Port P07 - Port Input Level Register
PILR07
R/W
000460H
I/O Port P08 - Port Input Level Register
PILR08
R/W
000461H
I/O Port P09 - Port Input Level Register
PILR09
R/W
000462H
I/O Port P10 - Port Input Level Register
PILR10
R/W
000463H
I/O Port P11 - Port Input Level Register
PILR11
R/W
000464H
I/O Port P12 - Port Input Level Register
PILR12
R/W
000465H
I/O Port P13 - Port Input Level Register
PILR13
R/W
000466H000467H
Reserved
000468H
I/O Port P16 - Port Input Level Register
PIER16
R/W
-
PILR16
R/W
DS07-13807-2E
MB96370 Series
I/O map MB96(F)37x (17 of 34)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000469H00046BH
Reserved
00046CH
I/O Port P00 - Extended Port Input Level Register
EPILR00
R/W
00046DH
I/O Port P01 - Extended Port Input Level Register
EPILR01
R/W
00046EH
I/O Port P02 - Extended Port Input Level Register
EPILR02
R/W
00046FH
I/O Port P03 - Extended Port Input Level Register
EPILR03
R/W
000470H
I/O Port P04 - Extended Port Input Level Register
EPILR04
R/W
000471H
I/O Port P05 - Extended Port Input Level Register
EPILR05
R/W
000472H
I/O Port P06 - Extended Port Input Level Register
EPILR06
R/W
000473H
I/O Port P07 - Extended Port Input Level Register
EPILR07
R/W
000474H
I/O Port P08 - Extended Port Input Level Register
EPILR08
R/W
000475H
I/O Port P09 - Extended Port Input Level Register
EPILR09
R/W
000476H
I/O Port P10 - Extended Port Input Level Register
EPILR10
R/W
000477H
I/O Port P11 - Extended Port Input Level Register
EPILR11
R/W
000478H
I/O Port P12 - Extended Port Input Level Register
EPILR12
R/W
000479H
I/O Port P13 - Extended Port Input Level Register
EPILR13
R/W
00047AH00047BH
Reserved
00047CH
I/O Port P16 - Extended Port Input Level Register
00047DH00047FH
Reserved
000480H
I/O Port P00 - Port Output Drive Register
PODR00
R/W
000481H
I/O Port P01 - Port Output Drive Register
PODR01
R/W
000482H
I/O Port P02 - Port Output Drive Register
PODR02
R/W
000483H
I/O Port P03 - Port Output Drive Register
PODR03
R/W
000484H
I/O Port P04 - Port Output Drive Register
PODR04
R/W
000485H
I/O Port P05 - Port Output Drive Register
PODR05
R/W
000486H
I/O Port P06 - Port Output Drive Register
PODR06
R/W
000487H
I/O Port P07 - Port Output Drive Register
PODR07
R/W
000488H
I/O Port P08 - Port Output Drive Register
PODR08
R/W
000489H
I/O Port P09 - Port Output Drive Register
PODR09
R/W
DS07-13807-2E
-
EPILR16
R/W
-
41
MB96370 Series
I/O map MB96(F)37x (18 of 34)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
00048AH
I/O Port P10 - Port Output Drive Register
PODR10
R/W
00048BH
I/O Port P11 - Port Output Drive Register
PODR11
R/W
00048CH
I/O Port P12 - Port Output Drive Register
PODR12
R/W
00048DH
I/O Port P13 - Port Output Drive Register
PODR13
R/W
00048EH00048FH
Reserved
000490H
I/O Port P16 - Port Output Drive Register
000491H00049BH
Reserved
00049CH
I/O Port P08 - Port High Drive Register
PHDR08
R/W
00049DH
I/O Port P09 - Port High Drive Register
PHDR09
R/W
00049EH
I/O Port P10 - Port High Drive Register
PHDR10
R/W
00049FH0004A7H
Reserved
0004A8H
I/O Port P00 - Pull-Up resistor Control Register
PUCR00
R/W
0004A9H
I/O Port P01 - Pull-Up resistor Control Register
PUCR01
R/W
0004AAH
I/O Port P02 - Pull-Up resistor Control Register
PUCR02
R/W
0004ABH
I/O Port P03 - Pull-Up resistor Control Register
PUCR03
R/W
0004ACH
I/O Port P04 - Pull-Up resistor Control Register
PUCR04
R/W
0004ADH
I/O Port P05 - Pull-Up resistor Control Register
PUCR05
R/W
0004AEH
I/O Port P06 - Pull-Up resistor Control Register
PUCR06
R/W
0004AFH
I/O Port P07 - Pull-Up resistor Control Register
PUCR07
R/W
0004B0H
I/O Port P08 - Pull-Up resistor Control Register
PUCR08
R/W
0004B1H
I/O Port P09 - Pull-Up resistor Control Register
PUCR09
R/W
0004B2H
I/O Port P10 - Pull-Up resistor Control Register
PUCR10
R/W
0004B3H
I/O Port P11 - Pull-Up resistor Control Register
PUCR11
R/W
0004B4H
I/O Port P12 - Pull-Up resistor Control Register
PUCR12
R/W
0004B5H
I/O Port P13 - Pull-Up resistor Control Register
PUCR13
R/W
0004B6H0004B7H
Reserved
0004B8H
I/O Port P16 - Pull-Up resistor Control Register
42
PODR16
R/W
-
-
PUCR16
R/W
DS07-13807-2E
MB96370 Series
I/O map MB96(F)37x (19 of 34)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0004B9H0004BBH
Reserved
0004BCH
I/O Port P00 - External Pin State Register
EPSR00
R
0004BDH
I/O Port P01 - External Pin State Register
EPSR01
R
0004BEH
I/O Port P02 - External Pin State Register
EPSR02
R
0004BFH
I/O Port P03 - External Pin State Register
EPSR03
R
0004C0H
I/O Port P04 - External Pin State Register
EPSR04
R
0004C1H
I/O Port P05 - External Pin State Register
EPSR05
R
0004C2H
I/O Port P06 - External Pin State Register
EPSR06
R
0004C3H
I/O Port P07 - External Pin State Register
EPSR07
R
0004C4H
I/O Port P08 - External Pin State Register
EPSR08
R
0004C5H
I/O Port P09 - External Pin State Register
EPSR09
R
0004C6H
I/O Port P10 - External Pin State Register
EPSR10
R
0004C7H
I/O Port P11 - External Pin State Register
EPSR11
R
0004C8H
I/O Port P12 - External Pin State Register
EPSR12
R
0004C9H
I/O Port P13 - External Pin State Register
EPSR13
R
0004CAH0004CBH
Reserved
0004CCH
I/O Port P16 - External Pin State Register
0004CDH0004CFH
Reserved
0004D0H
ADC analog input enable register 0
ADER0
R/W
0004D1H
ADC analog input enable register 1
ADER1
R/W
0004D2H
ADC analog input enable register 2
ADER2
R/W
0004D3H
ADC analog input enable register 3
ADER3
R/W
0004D4H
ADC analog input enable register 4
ADER4
R/W
0004D5H
Reserved
0004D6H
Peripheral Resource Relocation Register 0
PRRR0
R/W
0004D7H
Peripheral Resource Relocation Register 1
PRRR1
R/W
0004D8H
Peripheral Resource Relocation Register 2
PRRR2
R/W
0004D9H
Peripheral Resource Relocation Register 3
PRRR3
R/W
DS07-13807-2E
-
EPSR16
R
-
-
43
MB96370 Series
I/O map MB96(F)37x (20 of 34)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0004DAH
Peripheral Resource Relocation Register 4
PRRR4
R/W
0004DBH
Peripheral Resource Relocation Register 5
PRRR5
R/W
0004DCH
Peripheral Resource Relocation Register 6
PRRR6
R/W
0004DDH
Peripheral Resource Relocation Register 7
PRRR7
R/W
0004DEH
Peripheral Resource Relocation Register 8
PRRR8
R/W
0004DFH
Peripheral Resource Relocation Register 9
PRRR9
R/W
0004E0H
RTC - Sub Second Register L
WTBRL0
0004E1H
RTC - Sub Second Register M
WTBRH0
R/W
0004E2H
RTC - Sub-Second Register H
WTBR1
R/W
0004E3H
RTC - Second Register
WTSR
R/W
0004E4H
RTC - Minutes
WTMR
R/W
0004E5H
RTC - Hour
WTHR
R/W
0004E6H
RTC - Timer Control Extended Register
WTCER
R/W
0004E7H
RTC - Clock select register
WTCKSR
R/W
0004E8H
RTC - Timer Control Register Low
WTCRL
0004E9H
RTC - Timer Control Register High
WTCRH
R/W
0004EAH
CAL - Calibration unit Control register
CUCR
R/W
0004EBH
Reserved
0004ECH
CAL - Duration Timer Data Register Low
CUTDL
0004EDH
CAL - Duration Timer Data Register High
CUTDH
0004EEH
CAL - Calibration Timer Register 2 Low
CUTR2L
0004EFH
CAL - Calibration Timer Register 2 High
CUTR2H
0004F0H
CAL - Calibration Timer Register 1 Low
CUTR1L
0004F1H
CAL - Calibration Timer Register 1 High
CUTR1H
0004F2H0004F9H
Reserved
0004FAH
RLT - Timer input select (for Cascading)
0004FBH00051FH
Reserved
000520H
USART4 - Serial Mode Register
SMR4
R/W
000521H
USART4 - Serial Control Register
SCR4
R/W
44
WTBR0
WTCR
R/W
R/W
CUTD
R/W
R/W
CUTR2
R
R
CUTR1
R
R
-
TMISR
R/W
-
DS07-13807-2E
MB96370 Series
I/O map MB96(F)37x (21 of 34)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000522H
USART4 - TX Register
TDR4
W
000522H
USART4 - RX Register
RDR4
R
000523H
USART4 - Serial Status
SSR4
R/W
000524H
USART4 - Control/Com. Register (internal)
ECCR4
R/W
000525H
USART4 - Ext. Status Register
ESCR4
R/W
000526H
USART4 - Baud Rate Generator Register Low
BGRL4
000527H
USART4 - Baud Rate Generator Register High
BGRH4
R/W
000528H
USART4 - Extended Serial Interrupt Register
ESIR4
R/W
000529H
Reserved
00052AH
USART5 - Serial Mode Register
SMR5
R/W
00052BH
USART5 - Serial Control Register
SCR5
R/W
00052CH
USART5 - RX Register
TDR5
W
00052CH
USART5 - TX Register
RDR5
R
00052DH
USART5 - Serial Status
SSR5
R/W
00052EH
USART5 - Control/Com. Register
ECCR5
R/W
00052FH
USART5 - Ext. Status Register
ESCR5
R/W
000530H
USART5 - Baud Rate Generator Register Low
BGRL5
000531H
USART5 - Baud Rate Generator Register High
BGRH5
R/W
000532H
USART5 - Extended Serial Interrupt Register
ESIR5
R/W
000533H00055FH
Reserved
000560H
ALARM0 - Control Status Register*1
000561H
ALARM0 - Extended Control Status Register*1
000562H
ALARM1 - Control Status Register*1
000563H
ALARM1 - Extended Control Status Register*1
000564H
PPG6 - Timer register
000565H
PPG6 - Timer register
000566H
PPG6 - Period setting register
000567H
PPG6 - Period setting register
000568H
PPG6 - Duty cycle register
DS07-13807-2E
BGR4
R/W
-
BGR5
R/W
ACSR0
R/W
AECSR0
R/W
ACSR1
R/W
AECSR1
R/W
PTMR6
R
R
PCSR6
W
W
PDUT6
W
45
MB96370 Series
I/O map MB96(F)37x (22 of 34)
Address
46
Register
Abbreviation
8-bit access
000569H
PPG6 - Duty cycle register
00056AH
PPG6 - Control status register Low
PCNL6
00056BH
PPG6 - Control status register High
PCNH6
00056CH
PPG7 - Timer register
00056DH
PPG7 - Timer register
00056EH
PPG7 - Period setting register
00056FH
PPG7 - Period setting register
000570H
PPG7 - Duty cycle register
000571H
PPG7 - Duty cycle register
000572H
PPG7 - Control status register Low
PCNL7
000573H
PPG7 - Control status register High
PCNH7
000574H
PPG11-PPG8 - General Control register 1 Low
GCN1L2
000575H
PPG11-PPG8 - General Control register 1 High
GCN1H2
000576H
PPG11-PPG8 - General Control register 2 Low
GCN2L2
000577H
PPG11-PPG8 - General Control register 2 High
GCN2H2
000578H
PPG8 - Timer register
000579H
PPG8 - Timer register
00057AH
PPG8 - Period setting register
00057BH
PPG8 - Period setting register
00057CH
PPG8 - Duty cycle register
00057DH
PPG8 - Duty cycle register
00057EH
PPG8 - Control status register Low
PCNL8
00057FH
PPG8 - Control status register High
PCNH8
000580H
PPG9 - Timer register
000581H
PPG9 - Timer register
000582H
PPG9 - Period setting register
000583H
PPG9 - Period setting register
000584H
PPG9 - Duty cycle register
000585H
PPG9 - Duty cycle register
000586H
PPG9 - Control status register Low
Abbreviation
16-bit access
Access
W
PCN6
R/W
R/W
PTMR7
R
R
PCSR7
W
W
PDUT7
W
W
PCN7
R/W
R/W
GCN12
R/W
R/W
GCN22
R/W
R/W
PTMR8
R
R
PCSR8
W
W
PDUT8
W
W
PCN8
R/W
R/W
PTMR9
R
R
PCSR9
W
W
PDUT9
W
W
PCNL9
PCN9
R/W
DS07-13807-2E
MB96370 Series
I/O map MB96(F)37x (23 of 34)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
000587H
PPG9 - Control status register High
000588H
PPG10 - Timer register
000589H
PPG10 - Timer register
00058AH
PPG10 - Period setting register
00058BH
PPG10 - Period setting register
00058CH
PPG10 - Duty cycle register
00058DH
PPG10 - Duty cycle register
00058EH
PPG10 - Control status register Low
PCNL10
00058FH
PPG10 - Control status register High
PCNH10
000590H
PPG11 - Timer register
000591H
PPG11 - Timer register
000592H
PPG11 - Period setting register
000593H
PPG11 - Period setting register
000594H
PPG11 - Duty cycle register
000595H
PPG11 - Duty cycle register
000596H
PPG11 - Control status register Low
PCNL11
000597H
PPG11 - Control status register High
PCNH11
000598H0005DFH
Reserved
0005E0H
SMC0 - PWM control register
0005E1H
SMC0 - Extended control register (Output enable)
0005E2H
SMC0 - PWM compare register PWM 1
0005E3H
SMC0 - PWM compare register PWM 1
0005E4H
SMC0 - PWM compare register PWM 2
0005E5H
SMC0 - PWM compare register PWM 2
0005E6H
SMC0 - PWM Select register
PWS10
R/W
0005E7H
SMC0 - PWM Select register
PWS20
R/W
0005E8H0005E9H
Reserved
0005EAH
SMC1 - PWM control register
DS07-13807-2E
PCNH9
Access
R/W
PTMR10
R
R
PCSR10
W
W
PDUT10
W
W
PCN10
R/W
R/W
PTMR11
R
R
PCSR11
W
W
PDUT11
W
W
PCN11
R/W
R/W
-
PWC0
R/W
PWEC0
R/W
PWC10
R/W
R/W
PWC20
R/W
R/W
PWC1
R/W
47
MB96370 Series
I/O map MB96(F)37x (24 of 34)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0005EBH
SMC1 - Extended control register (Output enable)
0005ECH
SMC1 - PWM compare register PWM 1
0005EDH
SMC1 - PWM compare register PWM 1
0005EEH
SMC1 - PWM compare register PWM 2
0005EFH
SMC1 - PWM compare register PWM 2
0005F0H
SMC1 - PWM Select register
PWS11
R/W
0005F1H
SMC1 - PWM Select register
PWS21
R/W
0005F2H0005F3H
Reserved
0005F4H
SMC2 - PWM control register
0005F5H
SMC2 - Extended control register (Output enable)
0005F6H
SMC2 - PWM compare register PWM 1
0005F7H
SMC2 - PWM compare register PWM 1
0005F8H
SMC2 - PWM compare register PWM 2
0005F9H
SMC2 - PWM compare register PWM 2
0005FAH
SMC2 - PWM Select register
PWS12
R/W
0005FBH
SMC2 - PWM Select register
PWS22
R/W
0005FCH0005FDH
Reserved
0005FEH
SMC3 - PWM control register
0005FFH
SMC3 - Extended control register (Output enable)
000600H
SMC3 - PWM compare register PWM 1
000601H
SMC3 - PWM compare register PWM 1
000602H
SMC3 - PWM compare register PWM 2
000603H
SMC3 - PWM compare register PWM 2
000604H
SMC3 - PWM Select register
PWS13
R/W
000605H
SMC3 - PWM Select register
PWS23
R/W
000606H000607H
Reserved
48
PWEC1
R/W
PWC11
R/W
R/W
PWC21
R/W
R/W
PWC2
R/W
PWEC2
R/W
PWC12
R/W
R/W
PWC22
R/W
R/W
PWC3
R/W
PWEC3
R/W
PWC13
R/W
R/W
PWC23
R/W
R/W
-
DS07-13807-2E
MB96370 Series
I/O map MB96(F)37x (25 of 34)
Abbreviation
8-bit access
Abbreviation
16-bit access
Address
Register
000608H
SMC4 - PWM control register
000609H
SMC4 - Extended control register (Output enable)
00060AH
SMC4 - PWM compare register PWM 1
00060BH
SMC4 - PWM compare register PWM 1
00060CH
SMC4 - PWM compare register PWM 2
00060DH
SMC4 - PWM compare register PWM 2
00060EH
SMC4 - PWM Select register
PWS14
R/W
00060FH
SMC4 - PWM Select register
PWS24
R/W
000610H000611H
Reserved
000612H
SMC5 - PWM control register
000613H
SMC5 - Extended control register (Output enable)
000614H
SMC5 - PWM compare register PWM 1
000615H
SMC5 - PWM compare register PWM 1
000616H
SMC5 - PWM compare register PWM 2
000617H
SMC5 - PWM compare register PWM 2
000618H
SMC5 - PWM Select register
PWS15
R/W
000619H
SMC5 - PWM Select register
PWS25
R/W
00061AH00061BH
Reserved
00061CH
LCD - Output Enable Register 0 (Seg 7-0)
LCDER0
R/W
00061DH
LCD - Output Enable Register 1 (Seg 15-8)
LCDER1
R/W
00061EH
LCD - Output Enable Register 2 (Seg 23-16)
LCDER2
R/W
00061FH
LCD - Output Enable Register 3 (Seg 31-24)
LCDER3
R/W
000620H
LCD - Output Enable Register 4 (Seg 39-32)
LCDER4
R/W
000621H
LCD - Output Enable Register 5 (Seg 47-40)
LCDER5
R/W
000622H
LCD - Output Enable Register 6 (Seg 55-48)
LCDER6
R/W
000623H
LCD - Output Enable Register 7 (Seg 63-56)
LCDER7
R/W
000624H
LCD - Output Enable Register 8 (Seg 71-64)
LCDER8
R/W
DS07-13807-2E
Access
PWC4
R/W
PWEC4
R/W
PWC14
R/W
R/W
PWC24
R/W
R/W
PWC5
R/W
PWEC5
R/W
PWC15
R/W
R/W
PWC25
R/W
R/W
-
49
MB96370 Series
I/O map MB96(F)37x (26 of 34)
Address
50
Register
000625H
Reserved
000626H
LCD - Output Enable Register V (Vx)
000627H
LCD - Extended Control Register
000628H
LCD - Common pin switching register
000629H
LCD - Control Register
00062AH
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
-
LCDVER
R/W
LECR
R/W
LCDCMR
R/W
LCR
R/W
LCD - Data register for Segment 1-0
VRAM0
R/W
00062BH
LCD - Data register for Segment 3-2
VRAM1
R/W
00062CH
LCD - Data register for Segment 5-4
VRAM2
R/W
00062DH
LCD - Data register for Segment 7-6
VRAM3
R/W
00062EH
LCD - Data register for Segment 9-8
VRAM4
R/W
00062FH
LCD - Data register for Segment 11-10
VRAM5
R/W
000630H
LCD - Data register for Segment 13-12
VRAM6
R/W
000631H
LCD - Data register for Segment 15-14
VRAM7
R/W
000632H
LCD - Data register for Segment 17-16
VRAM8
R/W
000633H
LCD - Data register for Segment 19-18
VRAM9
R/W
000634H
LCD - Data register for Segment 21-20
VRAM10
R/W
000635H
LCD - Data register for Segment 23-22
VRAM11
R/W
000636H
LCD - Data register for Segment 25-24
VRAM12
R/W
000637H
LCD - Data register for Segment 27-26
VRAM13
R/W
000638H
LCD - Data register for Segment 29-28
VRAM14
R/W
000639H
LCD - Data register for Segment 31-30
VRAM15
R/W
00063AH
LCD - Data register for Segment 33-32
VRAM16
R/W
00063BH
LCD - Data register for Segment 35-34
VRAM17
R/W
00063CH
LCD - Data register for Segment 37-36
VRAM18
R/W
00063DH
LCD - Data register for Segment 39-38
VRAM19
R/W
00063EH
LCD - Data register for Segment 41-40
VRAM20
R/W
00063FH
LCD - Data register for Segment 43-42
VRAM21
R/W
000640H
LCD - Data register for Segment 45-44
VRAM22
R/W
000641H
LCD - Data register for Segment 47-46
VRAM23
R/W
000642H
LCD - Data register for Segment 49-48
VRAM24
R/W
DS07-13807-2E
MB96370 Series
I/O map MB96(F)37x (27 of 34)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
000643H
LCD - Data register for Segment 51-50
VRAM25
R/W
000644H
LCD - Data register for Segment 53-52
VRAM26
R/W
000645H
LCD - Data register for Segment 55-54
VRAM27
R/W
000646H
LCD - Data register for Segment 57-56
VRAM28
R/W
000647H
LCD - Data register for Segment 59-58
VRAM29
R/W
000648H
LCD - Data register for Segment 61-60
VRAM30
R/W
000649H
LCD - Data register for Segment 63-62
VRAM31
R/W
00064AH
LCD - Data register for Segment 65-64
VRAM32
R/W
00064BH
LCD - Data register for Segment 67-66
VRAM33
R/W
00064CH
LCD - Data register for Segment 69-68
VRAM34
R/W
00064DH
LCD - Data register for Segment 71-70
VRAM35
R/W
00064EH00065FH
Reserved
000660H
Peripheral Resource Relocation Register 10
PRRR10
R/W
000661H
Peripheral Resource Relocation Register 11
PRRR11
R/W
000662H
Peripheral Resource Relocation Register 12
PRRR12
R/W
000663H
Peripheral Resource Relocation Register 13
PRRR13
W
000664H0006DFH
Reserved
0006E0H
External Bus - Area configuration register 0 Low
EACL0
0006E1H
External Bus - Area configuration register 0 High
EACH0
0006E2H
External Bus - Area configuration register 1 Low
EACL1
0006E3H
External Bus - Area configuration register 1 High
EACH1
0006E4H
External Bus - Area configuration register 2 Low
EACL2
0006E5H
External Bus - Area configuration register 2 High
EACH2
0006E6H
External Bus - Area configuration register 3 Low
EACL3
0006E7H
External Bus - Area configuration register 3 High
EACH3
0006E8H
External Bus - Area configuration register 4 Low
EACL4
0006E9H
External Bus - Area configuration register 4 High
EACH4
0006EAH
External Bus - Area configuration register 5 Low
EACL5
0006EBH
External Bus - Area configuration register 5 High
EACH5
DS07-13807-2E
-
EAC0
R/W
R/W
EAC1
R/W
R/W
EAC2
R/W
R/W
EAC3
R/W
R/W
EAC4
R/W
R/W
EAC5
R/W
R/W
51
MB96370 Series
I/O map MB96(F)37x (28 of 34)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
0006ECH
External Bus - Area select register 2
EAS2
R/W
0006EDH
External Bus - Area select register 3
EAS3
R/W
0006EEH
External Bus - Area select register 4
EAS4
R/W
0006EFH
External Bus - Area select register 5
EAS5
R/W
0006F0H
External Bus - Mode register
EBM
R/W
0006F1H
External Bus - Clock and Function register
EBCF
R/W
0006F2H
External Bus - Address output enable register 0
EBAE0
R/W
0006F3H
External Bus - Address output enable register 1
EBAE1
R/W
0006F4H
External Bus - Address output enable register 2
EBAE2
R/W
0006F5H
External Bus - Control signal register
EBCS
R/W
0006F6H0006FFH
Reserved
000700H
CAN0 - Control register Low
CTRLRL0
000701H
CAN0 - Control register High (reserved)
CTRLRH0
000702H
CAN0 - Status register Low
STATRL0
000703H
CAN0 - Status register High (reserved)
STATRH0
000704H
CAN0 - Error Counter Low (Transmit)
ERRCNTL0
000705H
CAN0 - Error Counter High (Receive)
ERRCNTH0
000706H
CAN0 - Bit Timing Register Low
BTRL0
000707H
CAN0 - Bit Timing Register High
BTRH0
000708H
CAN0 - Interrupt Register Low
INTRL0
000709H
CAN0 - Interrupt Register High
INTRH0
00070AH
CAN0 - Test Register Low
TESTRL0
00070BH
CAN0 - Test Register High (reserved)
TESTRH0
00070CH
CAN0 - BRP Extension register Low
BRPERL0
00070DH
CAN0 - BRP Extension register High (reserved)
BRPERH0
00070EH00070FH
Reserved
000710H
CAN0 - IF1 Command request register Low
IF1CREQL0
000711H
CAN0 - IF1 Command request register High
IF1CREQH0
000712H
CAN0 - IF1 Command Mask register Low
IF1CMSKL0
52
CTRLR0
R/W
R
STATR0
R/W
R
ERRCNT0
R
R
BTR0
R/W
R/W
INTR0
R
R
TESTR0
R/W
R
BRPER0
R/W
R
-
IF1CREQ0
R/W
R/W
IF1CMSK0
R/W
DS07-13807-2E
MB96370 Series
I/O map MB96(F)37x (29 of 34)
Address
Register
Abbreviation
8-bit access
000713H
CAN0 - IF1 Command Mask register High (reserved)
IF1CMSKH0
000714H
CAN0 - IF1 Mask 1 Register Low
IF1MSK1L0
000715H
CAN0 - IF1 Mask 1 Register High
IF1MSK1H0
000716H
CAN0 - IF1 Mask 2 Register Low
IF1MSK2L0
000717H
CAN0 - IF1 Mask 2 Register High
IF1MSK2H0
000718H
CAN0 - IF1 Arbitration 1 Register Low
IF1ARB1L0
000719H
CAN0 - IF1 Arbitration 1 Register High
IF1ARB1H0
00071AH
CAN0 - IF1 Arbitration 2 Register Low
IF1ARB2L0
00071BH
CAN0 - IF1 Arbitration 2 Register High
IF1ARB2H0
00071CH
CAN0 - IF1 Message Control Register Low
IF1MCTRL0
00071DH
CAN0 - IF1 Message Control Register High
IF1MCTRH0
00071EH
CAN0 - IF1 Data A1 Low
IF1DTA1L0
00071FH
CAN0 - IF1 Data A1 High
IF1DTA1H0
000720H
CAN0 - IF1 Data A2 Low
IF1DTA2L0
000721H
CAN0 - IF1 Data A2 High
IF1DTA2H0
000722H
CAN0 - IF1 Data B1 Low
IF1DTB1L0
000723H
CAN0 - IF1 Data B1 High
IF1DTB1H0
000724H
CAN0 - IF1 Data B2 Low
IF1DTB2L0
000725H
CAN0 - IF1 Data B2 High
IF1DTB2H0
000726H00073FH
Reserved
000740H
CAN0 - IF2 Command request register Low
IF2CREQL0
000741H
CAN0 - IF2 Command request register High
IF2CREQH0
000742H
CAN0 - IF2 Command Mask register Low
IF2CMSKL0
000743H
CAN0 - IF2 Command Mask register High (reserved)
IF2CMSKH0
000744H
CAN0 - IF2 Mask 1 Register Low
IF2MSK1L0
000745H
CAN0 - IF2 Mask 1 Register High
IF2MSK1H0
000746H
CAN0 - IF2 Mask 2 Register Low
IF2MSK2L0
000747H
CAN0 - IF2 Mask 2 Register High
IF2MSK2H0
DS07-13807-2E
Abbreviation
16-bit access
Access
R
IF1MSK10
R/W
R/W
IF1MSK20
R/W
R/W
IF1ARB10
R/W
R/W
IF1ARB20
R/W
R/W
IF1MCTR0
R/W
R/W
IF1DTA10
R/W
R/W
IF1DTA20
R/W
R/W
IF1DTB10
R/W
R/W
IF1DTB20
R/W
R/W
-
IF2CREQ0
R/W
R/W
IF2CMSK0
R/W
R
IF2MSK10
R/W
R/W
IF2MSK20
R/W
R/W
53
MB96370 Series
I/O map MB96(F)37x (30 of 34)
Address
54
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
IF2ARB10
R/W
000748H
CAN0 - IF2 Arbitration 1 Register Low
IF2ARB1L0
000749H
CAN0 - IF2 Arbitration 1 Register High
IF2ARB1H0
00074AH
CAN0 - IF2 Arbitration 2 Register Low
IF2ARB2L0
00074BH
CAN0 - IF2 Arbitration 2 Register High
IF2ARB2H0
00074CH
CAN0 - IF2 Message Control Register Low
IF2MCTRL0
00074DH
CAN0 - IF2 Message Control Register High
IF2MCTRH0
00074EH
CAN0 - IF2 Data A1 Low
IF2DTA1L0
00074FH
CAN0 - IF2 Data A1 High
IF2DTA1H0
000750H
CAN0 - IF2 Data A2 Low
IF2DTA2L0
000751H
CAN0 - IF2 Data A2 High
IF2DTA2H0
000752H
CAN0 - IF2 Data B1 Low
IF2DTB1L0
000753H
CAN0 - IF2 Data B1 High
IF2DTB1H0
000754H
CAN0 - IF2 Data B2 Low
IF2DTB2L0
000755H
CAN0 - IF2 Data B2 High
IF2DTB2H0
000756H00077FH
Reserved
000780H
CAN0 - Transmission Request 1 Register Low
TREQR1L0
000781H
CAN0 - Transmission Request 1 Register High
TREQR1H0
000782H
CAN0 - Transmission Request 2 Register Low
TREQR2L0
000783H
CAN0 - Transmission Request 2 Register High
TREQR2H0
000784H00078FH
Reserved
000790H
CAN0 - New Data 1 Register Low
NEWDT1L0
000791H
CAN0 - New Data 1 Register High
NEWDT1H0
000792H
CAN0 - New Data 2 Register Low
NEWDT2L0
000793H
CAN0 - New Data 2 Register High
NEWDT2H0
000794H00079FH
Reserved
0007A0H
CAN0 - Interrupt Pending 1 Register Low
INTPND1L0
0007A1H
CAN0 - Interrupt Pending 1 Register High
INTPND1H0
0007A2H
CAN0 - Interrupt Pending 2 Register Low
INTPND2L0
R/W
IF2ARB20
R/W
R/W
IF2MCTR0
R/W
R/W
IF2DTA10
R/W
R/W
IF2DTA20
R/W
R/W
IF2DTB10
R/W
R/W
IF2DTB20
R/W
R/W
-
TREQR10
R
R
TREQR20
R
R
-
NEWDT10
R
R
NEWDT20
R
R
-
INTPND10
R
R
INTPND20
R
DS07-13807-2E
MB96370 Series
I/O map MB96(F)37x (31 of 34)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
INTPND2H0
Access
0007A3H
CAN0 - Interrupt Pending 2 Register High
0007A4H0007AFH
Reserved
0007B0H
CAN0 - Message Valid 1 Register Low
MSGVAL1L0
0007B1H
CAN0 - Message Valid 1 Register High
MSGVAL1H0
0007B2H
CAN0 - Message Valid 2 Register Low
MSGVAL2L0
0007B3H
CAN0 - Message Valid 2 Register High
MSGVAL2H0
0007B4H0007CDH
Reserved
0007CEH
CAN0 - Output enable register
0007CFH
Reserved
0007D0H
SG0 - Sound Generator Control Register Low
SGCRL0
0007D1H
SG0 - Sound Generator Control Register High
SGCRH0
R/W
0007D2H
SG0 - Sound Generator Frequency Register
SGFR0
R/W
0007D3H
SG0 - Sound Generator Amplitude Register
SGAR0
R/W
0007D4H
SG0 - Sound Generator Decrement Register
SGDR0
R/W
0007D5H
SG0 - Sound Generator Tone Register
SGTR0
R/W
0007D6H
SG1 - Sound Generator Control Register Low
SGCRL1
0007D7H
SG1 - Sound Generator Control Register High
SGCRH1
R/W
0007D8H
SG1 - Sound Generator Frequency Register
SGFR1
R/W
0007D9H
SG1 - Sound Generator Amplitude Register
SGAR1
R/W
0007DAH
SG1 - Sound Generator Decrement Register
SGDR1
R/W
0007DBH
SG1 - Sound Generator Tone Register
SGTR1
R/W
0007DCH0007FFH
Reserved
MSGVAL10
R
R
MSGVAL20
R
R
-
COER0
R/W
SGCR0
SGCR1
R/W
R/W
-
000800H
CAN1 - Control register Low
CTRLRL1
000801H
CAN1 - Control register High (reserved)
CTRLRH1
000802H
CAN1 - Status register Low
STATRL1
000803H
CAN1 - Status register High (reserved)
STATRH1
000804H
CAN1 - Error Counter Low (Transmit)
ERRCNTL1
000805H
CAN1 - Error Counter High (Receive)
ERRCNTH1
DS07-13807-2E
R
CTRLR1
R/W
R
STATR1
R/W
R
ERRCNT1
R
R
55
MB96370 Series
I/O map MB96(F)37x (32 of 34)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
BTR1
R/W
000806H
CAN1 - Bit Timing Register Low
BTRL1
000807H
CAN1 - Bit Timing Register High
BTRH1
000808H
CAN1 - Interrupt Register Low
INTRL1
000809H
CAN1 - Interrupt Register High
INTRH1
00080AH
CAN1 - Test Register Low
TESTRL1
00080BH
CAN1 - Test Register High (reserved)
TESTRH1
00080CH
CAN1 - BRP Extension register Low
BRPERL1
00080DH
CAN1 - BRP Extension register High (reserved)
BRPERH1
00080EH00080FH
Reserved
000810H
CAN1 - IF1 Command request register Low
IF1CREQL1
000811H
CAN1 - IF1 Command request register High
IF1CREQH1
000812H
CAN1 - IF1 Command Mask register Low
IF1CMSKL1
000813H
CAN1 - IF1 Command Mask register High (reserved)
IF1CMSKH1
000814H
CAN1 - IF1 Mask 1 Register Low
IF1MSK1L1
000815H
CAN1 - IF1 Mask 1 Register High
IF1MSK1H1
000816H
CAN1 - IF1 Mask 2 Register Low
IF1MSK2L1
000817H
CAN1 - IF1 Mask 2 Register High
IF1MSK2H1
000818H
CAN1 - IF1 Arbitration 1 Register Low
IF1ARB1L1
000819H
CAN1 - IF1 Arbitration 1 Register High
IF1ARB1H1
00081AH
CAN1 - IF1 Arbitration 2 Register Low
IF1ARB2L1
00081BH
CAN1 - IF1 Arbitration 2 Register High
IF1ARB2H1
00081CH
CAN1 - IF1 Message Control Register Low
IF1MCTRL1
00081DH
CAN1 - IF1 Message Control Register High
IF1MCTRH1
00081EH
CAN1 - IF1 Data A1 Low
IF1DTA1L1
00081FH
CAN1 - IF1 Data A1 High
IF1DTA1H1
000820H
CAN1 - IF1 Data A2 Low
IF1DTA2L1
000821H
CAN1 - IF1 Data A2 High
IF1DTA2H1
000822H
CAN1 - IF1 Data B1 Low
IF1DTB1L1
000823H
CAN1 - IF1 Data B1 High
IF1DTB1H1
56
R/W
INTR1
R
R
TESTR1
R/W
R
BRPER1
R/W
R
-
IF1CREQ1
R/W
R/W
IF1CMSK1
R/W
R
IF1MSK11
R/W
R/W
IF1MSK21
R/W
R/W
IF1ARB11
R/W
R/W
IF1ARB21
R/W
R/W
IF1MCTR1
R/W
R/W
IF1DTA11
R/W
R/W
IF1DTA21
R/W
R/W
IF1DTB11
R/W
R/W
DS07-13807-2E
MB96370 Series
I/O map MB96(F)37x (33 of 34)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
IF1DTB21
R/W
000824H
CAN1 - IF1 Data B2 Low
IF1DTB2L1
000825H
CAN1 - IF1 Data B2 High
IF1DTB2H1
000826H00083FH
Reserved
000840H
CAN1 - IF2 Command request register Low
IF2CREQL1
000841H
CAN1 - IF2 Command request register High
IF2CREQH1
000842H
CAN1 - IF2 Command Mask register Low
IF2CMSKL1
000843H
CAN1 - IF2 Command Mask register High (reserved)
IF2CMSKH1
000844H
CAN1 - IF2 Mask 1 Register Low
IF2MSK1L1
000845H
CAN1 - IF2 Mask 1 Register High
IF2MSK1H1
000846H
CAN1 - IF2 Mask 2 Register Low
IF2MSK2L1
000847H
CAN1 - IF2 Mask 2 Register High
IF2MSK2H1
000848H
CAN1 - IF2 Arbitration 1 Register Low
IF2ARB1L1
000849H
CAN1 - IF2 Arbitration 1 Register High
IF2ARB1H1
00084AH
CAN1 - IF2 Arbitration 2 Register Low
IF2ARB2L1
00084BH
CAN1 - IF2 Arbitration 2 Register High
IF2ARB2H1
00084CH
CAN1 - IF2 Message Control Register Low
IF2MCTRL1
00084DH
CAN1 - IF2 Message Control Register High
IF2MCTRH1
00084EH
CAN1 - IF2 Data A1 Low
IF2DTA1L1
00084FH
CAN1 - IF2 Data A1 High
IF2DTA1H1
000850H
CAN1 - IF2 Data A2 Low
IF2DTA2L1
000851H
CAN1 - IF2 Data A2 High
IF2DTA2H1
000852H
CAN1 - IF2 Data B1 Low
IF2DTB1L1
000853H
CAN1 - IF2 Data B1 High
IF2DTB1H1
000854H
CAN1 - IF2 Data B2 Low
IF2DTB2L1
000855H
CAN1 - IF2 Data B2 High
IF2DTB2H1
000856H00087FH
Reserved
000880H
CAN1 - Transmission Request 1 Register Low
TREQR1L1
000881H
CAN1 - Transmission Request 1 Register High
TREQR1H1
DS07-13807-2E
R/W
IF2CREQ1
R/W
R/W
IF2CMSK1
R/W
R
IF2MSK11
R/W
R/W
IF2MSK21
R/W
R/W
IF2ARB11
R/W
R/W
IF2ARB21
R/W
R/W
IF2MCTR1
R/W
R/W
IF2DTA11
R/W
R/W
IF2DTA21
R/W
R/W
IF2DTB11
R/W
R/W
IF2DTB21
R/W
R/W
-
TREQR11
R
R
57
MB96370 Series
I/O map MB96(F)37x (34 of 34)
Address
Register
Abbreviation
8-bit access
Abbreviation
16-bit access
Access
TREQR21
R
000882H
CAN1 - Transmission Request 2 Register Low
TREQR2L1
000883H
CAN1 - Transmission Request 2 Register High
TREQR2H1
000884H00088FH
Reserved
000890H
CAN1 - New Data 1 Register Low
NEWDT1L1
000891H
CAN1 - New Data 1 Register High
NEWDT1H1
000892H
CAN1 - New Data 2 Register Low
NEWDT2L1
000893H
CAN1 - New Data 2 Register High
NEWDT2H1
000894H00089FH
Reserved
0008A0H
CAN1 - Interrupt Pending 1 Register Low
INTPND1L1
0008A1H
CAN1 - Interrupt Pending 1 Register High
INTPND1H1
0008A2H
CAN1 - Interrupt Pending 2 Register Low
INTPND2L1
0008A3H
CAN1 - Interrupt Pending 2 Register High
INTPND2H1
0008A4H0008AFH
Reserved
0008B0H
CAN1 - Message Valid 1 Register Low
MSGVAL1L1
0008B1H
CAN1 - Message Valid 1 Register High
MSGVAL1H1
0008B2H
CAN1 - Message Valid 2 Register Low
MSGVAL2L1
0008B3H
CAN1 - Message Valid 2 Register High
MSGVAL2H1
0008B4H0008CDH
Reserved
0008CEH
CAN1 - Output enable register
0008CFH000BFFH
Reserved
R
NEWDT11
R
R
NEWDT21
R
R
-
INTPND11
R
R
INTPND21
R
R
-
MSGVAL11
R
R
MSGVAL21
R
R
-
COER1
R/W
-
*1: No alarm comparator available on MB96375R.
Note: Any write access to reserved addresses in the I/O map should not be performed. A read access to a reserved
address results in reading “X”.
Registers of resources which are described in this table, but which are not supported by the device, should
also be handled as “Reserved”.
58
DS07-13807-2E
MB96370 Series
■ INTERRUPT VECTOR TABLE
Interrupt vector table MB96(F)37x (1 of 3)
Offset in
Index in
Vector
Cleared by
vector taVector name
ICR to pronumber
DMA
ble
gram
Description
0
3FCH
CALLV0
No
-
1
3F8H
CALLV1
No
-
2
3F4H
CALLV2
No
-
3
3F0H
CALLV3
No
-
4
3ECH
CALLV4
No
-
5
3E8H
CALLV5
No
-
6
3E4H
CALLV6
No
-
7
3E0H
CALLV7
No
-
8
3DCH
RESET
No
-
9
3D8H
INT9
No
-
10
3D4H
EXCEPTION
No
-
11
3D0H
NMI
No
-
12
3CCH
DLY
No
12
Delayed Interrupt
13
3C8H
RC_TIMER
No
13
RC Timer
14
3C4H
MC_TIMER
No
14
Main Clock Timer
15
3C0H
SC_TIMER
No
15
Sub Clock Timer
16
3BCH
RESERVED
No
16
Reserved
17
3B8H
EXTINT0
Yes
17
External Interrupt 0
18
3B4H
EXTINT1
Yes
18
External Interrupt 1
19
3B0H
EXTINT2
Yes
19
External Interrupt 2
20
3ACH
EXTINT3
Yes
20
External Interrupt 3
21
3A8H
EXTINT4
Yes
21
External Interrupt 4
22
3A4H
EXTINT5
Yes
22
External Interrupt 5
23
3A0H
EXTINT6
Yes
23
External Interrupt 6
24
39CH
EXTINT7
Yes
24
External Interrupt 7
25
398H
CAN0
No
25
CAN Controller 0
26
394H
CAN1
No
26
CAN Controller 1
27
390H
PPG0
Yes
27
Programmable Pulse Generator 0
28
38CH
PPG1
Yes
28
Programmable Pulse Generator 1
29
388H
PPG2
Yes
29
Programmable Pulse Generator 2
30
384H
PPG3
Yes
30
Programmable Pulse Generator 3
31
380H
PPG4
Yes
31
Programmable Pulse Generator 4
32
37CH
PPG5
Yes
32
Programmable Pulse Generator 5
DS07-13807-2E
Non-Maskable Interrupt
59
MB96370 Series
Interrupt vector table MB96(F)37x (2 of 3)
Offset in
Index in
Vector
Cleared by
vector taVector name
ICR to pronumber
DMA
ble
gram
60
Description
33
378H
PPG6
Yes
33
Programmable Pulse Generator 6
34
374H
PPG7
Yes
34
Programmable Pulse Generator 7
35
370H
RLT0
Yes
35
Reload Timer 0
36
36CH
RLT1
Yes
36
Reload Timer 1
37
368H
RLT2
Yes
37
Reload Timer 2
38
364H
RLT3
Yes
38
Reload Timer 3
39
360H
PPGRLT
Yes
39
Reload Timer 6 - dedicated for PPG
40
35CH
ICU0
Yes
40
Input Capture Unit 0
41
358H
ICU1
Yes
41
Input Capture Unit 1
42
354H
ICU2
Yes
42
Input Capture Unit 2
43
350H
ICU3
Yes
43
Input Capture Unit 3
44
34CH
ICU4
Yes
44
Input Capture Unit 4
45
348H
ICU5
Yes
45
Input Capture Unit 5
46
344H
ICU6
Yes
46
Input Capture Unit 6
47
340H
ICU7
Yes
47
Input Capture Unit 7
48
33CH
OCU0
Yes
48
Output Compare Unit 0
49
338H
OCU1
Yes
49
Output Compare Unit 1
50
334H
OCU2
Yes
50
Output Compare Unit 2
51
330H
OCU3
Yes
51
Output Compare Unit 3
52
32CH
FRT0
Yes
52
Free Running Timer 0
53
328H
FRT1
Yes
53
Free Running Timer 1
54
324H
RTC0
No
54
Real Timer Clock
55
320H
CAL0
No
55
Clock Calibration Unit
56
31CH
SG0
No
56
Sound Generator 0
57
318H
SG1
No
57
Sound Generator 1
58
314H
IIC0
Yes
58
I2C interface 0
59
310H
ADC0
Yes
59
A/D Converter
60
30CH
ALARM0
No
60
Alarm Comparator 0*1
61
308H
ALARM1
No
61
Alarm Comparator 1*1
62
304H
LINR0
Yes
62
LIN USART 0 RX
63
300H
LINT0
Yes
63
LIN USART 0 TX
64
2FCH
LINR1
Yes
64
LIN USART 1 RX
65
2F8H
LINT1
Yes
65
LIN USART 1 TX
66
2F4H
LINR2
Yes
66
LIN USART 2 RX
67
2F0H
LINT2
Yes
67
LIN USART 2 TX
DS07-13807-2E
MB96370 Series
Interrupt vector table MB96(F)37x (3 of 3)
Offset in
Index in
Vector
Cleared by
vector taVector name
ICR to pronumber
DMA
ble
gram
Description
68
2ECH
LINR4
Yes
68
LIN USART 4 RX
69
2E8H
LINT4
Yes
69
LIN USART 4 TX
70
2E4H
LINR5
Yes
70
LIN USART 5 RX
71
2E0H
LINT5
Yes
71
LIN USART 5 TX
72
2DCH
FLASH_A
No
72
Flash memory A (only Flash devices)
73
2D8H
FLASH_B
No
73
Flash memory B (only Flash devices with
Flash B)
74
2D4H
PPG8
Yes
74
Programmable Pulse Generator 8
75
2D0H
PPG9
Yes
75
Programmable Pulse Generator 9
76
2CCH
PPG10
Yes
76
Programmable Pulse Generator 10
77
2C8H
PPG11
Yes
77
Programmable Pulse Generator 11
78
2C4H
OCU4
Yes
78
Output Compare Unit 4
79
2C0H
OCU5
Yes
79
Output Compare Unit 5
80
2BCH
IIC1
Yes
80
I2C Interface 1
81
2B8H
LINR3
Yes
81
LIN USART 3 RX
82
2B4H
LINT3
Yes
82
LIN USART 3 TX
*1: No alarm comparator available on MB96375R.
DS07-13807-2E
61
MB96370 Series
■ HANDLING DEVICES
Special care is required for the following when handling the device:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Latch-up prevention
Unused pins handling
External clock usage
Unused sub clock signal
Notes on PLL clock mode operation
Power supply pins (VCC/VSS)
Crystal oscillator and ceramic resonator circuit
Turn on sequence of power supply to A/D converter and analog inputs
Pin handling when not using the A/D converter
Notes on energization
Stabilization of power supply voltage
SMC power supply pins
Serial communication
Clock modulator
1. Latch-up prevention
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC pins and VSS pins.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current dramatically, causing thermal damages to the device.
For the same reason, extra care is required to not let the analog power-supply voltage (AVCC, AVRH) exceed
the digital power-supply voltage.
2. Unused pins handling
Unused input pins can be left open when the input is disabled (corresponding bit of Port Input Enable register
PIER = 0).
Leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent
damage of the device. They must therefore be pulled up or pulled down through resistors. To prevent latch-up,
those resistors should be more than 2 kΩ.
Unused bidirectional pins can be set either to the output state and be then left open, or to the input state with
either input disabled or external pull-up/pull-down resistor as described above.
3. External clock usage
The permitted frequency range of an external clock depends on the oscillator type and configuration. Please
refer to AC Characteristics for detailed modes and frequency limits. Single and opposite phase external clocks
must be connected as follows:
1. Single phase external clock
• When using a single phase external clock, X0 (X0A) pin must be driven and X1 (X1A) pin left open.
X0
X1
62
DS07-13807-2E
MB96370 Series
2. Opposite phase external clock
• When using an opposite phase external clock, X1 (X1A) pins must be supplied with a clock signal which has
the opposite phase to the X0 (X0A) pins.
X0
X1
4. Unused sub clock signal
If the pins X0A and X1A are not connected to an oscillator, a pull-down resistor must be connected on the X0A
pin and the X1A pin must be left open.
5. Notes on PLL clock mode operation
If the PLL clock mode is selected and no external oscillator is operating or no external clock is supplied, the
microcontroller attempts to work with the free oscillating PLL. Performance of this operation, however, cannot
be guaranteed.
6. Power supply pins (VCC/VSS)
It is required that all VCC-level as well as all VSS-level power supply pins are at the same potential. If there is more
than one VCC or VSS level, the device may operate incorrectly or be damaged even within the guaranteed operating
range.
VCC and VSS pins must be connected to the device from the power supply with lowest possible impedance.
As a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 µF between
VCC and VSS pins as close as possible to VCC and VSS pins.
Please add the bypass capacitor of the power supply in order to not exceed 0.1V/µs.
7. Crystal oscillator and ceramic resonator circuit
Noise at X0, X1 pins or X0A, X1A pins might cause abnormal operation. It is required to provide bypass capacitors
with shortest possible distance to X0, X1 pins and X0A, X1A pins, crystal oscillator (or ceramic resonator) and
ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins and X0A, X1A pins
with a ground area for stabilizing the operation.
It is highly recommended to evaluate the quartz/MCU or resonator/MCU system at the quartz or resonator
manufacturer, especially when using low-Q resonators at higher frequencies.
8. Turn on sequence of power supply to A/D converter and analog inputs
It is required to turn the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (ANn) on after
turning the digital power supply (VCC) on.
It is also required to turn the digital power off after turning the A/D converter supply and analog inputs off. In this
case, the voltage must not exceed AVRH or AVCC (turning the analog and digital power supplies simultaneously
on or off is acceptable).
9. Pin handling when not using the A/D converter
It is required to connect the unused pins of the A/D converter as AVCC = VCC, AVSS = AVRH = AVRL = VSS.
DS07-13807-2E
63
MB96370 Series
10. Notes on Power-on
To prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on
should be slower than 50µs from 0.2 V to 2.7 V.
11. Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation safety range of the Vcc power supply voltage,
a malfunction may occur. The Vcc power supply voltage must therefore be stabilized. As stabilization guidelines,
the power supply voltage must be stabilized in such a way that Vcc ripple fluctuations (peak to peak value) in
the commercial frequencies (50 to 60 Hz) fall within 10% of the standard Vcc power supply voltage and the
transient fluctuation rate becomes 0.1V/µs or less in instantaneous fluctuation for power supply switching.
12. SMC power supply pins
All DVSS pins must be set to the same level as the VSS pins.
The DVCC power supply level can be set independently of the VCC power supply level. However note that the
SMC I/O pin state is undefined if DVCC is powered on and VCC is below 3V. To avoid this, we recommend to
always power VCC before DVCC.
13. Serial communication
There is a possibility to receive wrong data due to noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider receiving of wrong data when designing the system. For example apply a checksum and retransmit
the data if an error occurs.
14. Clock modulator
Please contact Fujitsu Semiconductor Limited before using this function.
64
DS07-13807-2E
MB96370 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Power supply voltage
AD Converter voltage references
SMC Power supply
LCD power supply voltage
Symbol
Rating
Min
Max
Unit
Remarks
VCC
VSS - 0.3 VSS + 6.0
V
AVCC
VSS - 0.3 VSS + 6.0
V
VCC = AVCC *1
AVRH,
AVRL
VSS - 0.3 VSS + 6.0
V
AVCC ≥ AVRH, AVCC ≥ AVRL,
AVRH > AVRL, AVRL ≥ AVSS
DVCC
VSS - 0.3 VSS + 6.0
V
Please refer to *7
V0 to V3 VSS - 0.3 VSS + 6.0
V
V0 to V3 must not exceed VCC
Input voltage
VI
VSS - 0.3 VSS + 6.0
V
VI ≤ (D)VCC + 0.3V
Output voltage
VO
VSS - 0.3 VSS + 6.0
V
VO ≤ (D)VCC + 0.3V *2
Maximum Clamp Current
Total Maximum Clamp Current
“L” level maximum output current
“L” level average output current
“L” level maximum overall output current
“L” level average overall output current
”H” level maximum output current
DS07-13807-2E
*2
ICLAMP
-4.0
+4.0
mA
Applicable to general-purpose
I/O pins *3
Σ|ICLAMP|
-
40
mA
Applicable to general-purpose
I/O pins *3
IOL1
-
15
mA
Outputs with driving strength
set to 2mA/3mA/5mA
IOLSMC
-
40
mA
High current outputs with driving strength set to 30mA
IOLAV2
-
2
mA
Outputs with driving strength
set to 2mA
IOLAV3
-
3
mA Outputs of I/O circuit type “N”
IOLAV5
-
5
mA
Outputs with driving strength
set to 5mA
IOLAVSMC
-
30
mA
High current outputs with driving strength set to 30mA
ΣIOL1
-
100
mA Normal outputs
ΣIOLSMC
-
330
mA High current outputs
ΣIOLAV1
-
50
mA Normal outputs
ΣIOLAVSMC
-
250
mA High current outputs
IOH1
-
-15
mA
Outputs with driving strength
set to 2mA/3mA/5mA
IOHSMC
-
-40
mA
High current outputs with driving strength set to 30mA
65
MB96370 Series
Parameter
”H” level average output current
”H” level maximum overall output current
”H” level average overall output current
Permitted Power dissipation (Mask ROM
devices) *4
Permitted Power dissipation (Flash devices) *4
Operating ambient temperature
Storage temperature
Symbol
Rating
Unit
Remarks
Min
Max
IOHAV2
-
-2
mA
IOHAV3
-
-3
mA Outputs of I/O circuit type “N”
IOHAV5
-
-5
mA
Outputs with driving strength
set to 5mA
IOHAVSMC
-
-30
mA
High current outputs with driving strength set to 30mA
ΣIOH1
-
-100
mA Normal outputs
ΣIOHSMC
-
-330
mA High current outputs
ΣIOHAV1
-
-50
mA Normal outputs
ΣIOHASMC
-
-250
mA High current outputs
-
*5
350
mW TA=125oC
-
630*5
mW TA=105oC
-
350*5
mW TA=105oC
-
700*5
mW TA=85oC
-
960*5
mW TA=70oC
-
430*5
mW
TA=125oC, no Flash program/
erase *6
-
780*5
mW
TA=105oC, no Flash program/
erase *6
0
+70
-40
+105
-40
+125
-55
+150
PD
PD
TA
TSTG
Outputs with driving strength
set to 2mA
MB96V300C
o
C
*6
o
C
*1: AVCC and VCC must be set to the same voltage. It is required that AVCC does not exceed VCC and that the voltage
at the analog inputs does not exceed AVCC neither when the power is switched on.
*2: VI and VO should not exceed (D)VCC + 0.3 V. VI should also not exceed the specified ratings. However if the
maximum current to/from a input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. Input/output voltages of high current ports depend on DVCC. Input/output voltages of standard
ports depend on VCC.
*3: • Applicable to all general-purpose I/O pins (Pnn_m) except I/O pins with SEG or COM functionality.
• Use within recommended operating conditions.
• Use at DC voltage (current)
• The +B signal should always be applied a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V), the power
66
DS07-13807-2E
MB96370 Series
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting
supply voltage may not be sufficient to operate the Power reset (except devices with persistent low voltage
reset in internal vector mode).
• No +B signal must be applied to any LCD I/O pin (including unused SEG/COM pins).
• Sample recommended circuits:
Protective Diode
VCC
Limiting
resistance
P-ch
+B input (0V to 16V)
N-ch
R
*4: The maximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the
thermal conductance of the package on the PCB.
The actual power dissipation depends on the customer application and can be calculated as follows:
PD = PIO + PINT
PIO = ∑ (VOL * IOL + VOH * IOH) (IO load power dissipation, sum is performed on all IO ports)
PINT = VCC * (ICC + IA) (internal power dissipation)
ICC is the total core current consumption into VCC as described in “DC characteristics” and depends on the
selected operation mode and clock frequency and the usage of functions like Flash programming or the clock
modulator.
IA is the analog current consumption into AVCC.
*5: Worst case value for a package mounted on single layer PCB at specified TA without air flow.
*6: Please contact Fujitsu for reliability limitations when using under these conditions.
*7: If DVCC is powered before VCC, then SMC I/O pins state is undefined. To avoid this, we recommend to always
power VCC before DVCC. It is not necessary to set VCC and DVCC to the same value.
WARNING: Semiconductor devices may be permanently damaged by application of stress (including, without
limitation, voltage, current or temperature) in excess of absolute maximum ratings. Do not exceed any
of these ratings.
DS07-13807-2E
67
MB96370 Series
2. Recommended Operating Conditions
Parameter
Power supply voltage
Smoothing capacitor at C
pin
Symbol
Value
Unit
Min
Typ
Max
VCC, DVCC
3.0
-
5.5
V
CS
3.5
4.7
15
µF
Remarks
Use a X7R ceramic capacitor or
a capacitor that has similar frequency characteristics
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition. Operation
under any conditions other than these conditions may adversely affect reliability of device and could
result in device failure. No warranty is made with respect to any use, operating conditions or
combinations not represented on this data sheet. If you are considering application under any
conditions other than listed herein, please contact sales representatives beforehand.
68
DS07-13807-2E
MB96370 Series
3. DC characteristics
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter
Symbol
Pin
Input H voltage
Value
Unit
Remarks
Min
Typ
Max
0.8
VCC
-
(D)VCC
+ 0.3
V
0.7
VCC
-
(D)VCC
+ 0.3
V
(D)VCC ≥ 4.5V
0.74
VCC
-
(D)VCC
+ 0.3
V
(D)VCC < 4.5V
0.8
VCC
-
(D)VCC
+ 0.3
V
TTL input selected
2.0
-
(D)VCC
+ 0.3
V
CMOS Hysteresis
0.8/0.2 input selected
VIH
CMOS Hysteresis
Port inputs 0.7/0.3 input selected
Pnn_m
AUTOMOTIVE
Hysteresis input
selected
VIHX0F
X0
External clock in
“Fast Clock Input
mode”
0.8
VCC
-
VCC +
0.3
V
VIHX0S
X0,X1,
X0A,X1A
External clock in
“oscillation mode”
2.5
-
VCC +
0.3
V
VIHR
RSTX
-
0.8
VCC
-
VCC +
0.3
V
VIHM
MD2-MD0
-
VCC 0.3
-
VCC +
0.3
V
CMOS Hysteresis
0.8/0.2 input selected
VSS 0.3
-
0.2
(D)VCC
V
CMOS Hysteresis
0.7/0.3 input sePort inputs lected
VSS 0.3
-
0.3
(D)VCC
V
VSS 0.3
-
0.5
(D)VCC
V
(D)VCC ≥ 4.5V
VSS 0.3
-
0.46
(D)VCC
V
(D)VCC < 4.5V
TTL input selected
VSS 0.3
-
0.8
V
Input L voltage
VIL
DS07-13807-2E
Condition
Pnn_m
AUTOMOTIVE
Hysteresis input
selected
VILX0F
X0
External clock in
“Fast Clock Input
mode”
VSS 0.3
-
0.2 VCC
V
VILX0S
X0,X1,
X0A,X1A
External clock in
“oscillation mode”
VSS 0.3
-
0.4
V
VILR
RSTX
-
VSS 0.3
-
0.2 VCC
V
VILM
MD2-MD0
-
VSS 0.3
-
VSS +
0.3
V
CMOS Hysteresis input
CMOS Hysteresis input
69
MB96370 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter
Symbol
Pin
Output H voltage
VOH2
Normal
and High
Current
outputs
Condition
Value
Min
Typ
Max
Unit
4.5V ≤ (D)VCC ≤
5.5V
IOH = -2mA
3.0V ≤ (D)VCC <
4.5V
(D)VCC
- 0.5
-
-
Remarks
V
Driving strength set
to 2mA
(PODR:OD=1,
PHDR:HD=0)
IOH = -1.6mA
VOH5
Normal
and High
Current
outputs
4.5V ≤ (D)VCC ≤
5.5V
(D)VCC
- 0.5
-
-
V
Driving strength set
to 5mA
(PODR:OD=0,
PHDR:HD=0)
DVCC 0.5
3.0V ≤ DVCC < 4.5V
-
-
V
Driving strength set
to 30mA
(PHDR:HD=1)
-
-
V
I/O circuit type “N”
V
Driving strength set
to 2mA
(PODR:OD=1,
PHDR:HD=0)
IOH = -5mA
3.0V ≤ (D)VCC <
4.5V
IOH = -3mA
4.5V ≤ DVCC ≤ 5.5V
VOH30
High current outputs
IOH = -30mA
IOH = -20mA
4.5V ≤ VCC ≤ 5.5V
VOH3
3mA outputs
IOH = -3mA
3.0V ≤ VCC < 4.5V
VCC 0.5
IOH = -2mA
Output L voltage
VOL2
Normal
and High
Current
outputs
4.5V ≤ (D)VCC ≤
5.5V
IOL = +2mA
3.0V ≤ (D)VCC <
4.5V
-
-
0.4
IOL = +1.6mA
VOL5
Normal
and High
Current
outputs
4.5V ≤ (D)VCC ≤
5.5V
IOL = +5mA
3.0V ≤ (D)VCC <
4.5V
-
-
0.4
V
Driving strength set
to 5mA
(PODR:OD=0,
PHDR:HD=0)
-
-
0.5
V
Driving strength set
to 30mA
(PHDR:HD=1)
-
-
0.4
V
I/O circuit type “N”
-1
-
+1
IOL = +3mA
4.5V ≤ DVCC ≤ 5.5V
VOL30
High current outputs
IOL = +30mA
3.0V ≤ DVCC < 4.5V
IOL = +20mA
VOL3
3mA outputs
IIL
Pnn_m
3.0V ≤ VCC ≤ 5.5V
IOL = +3mA
VSS < VI < VCC
Input leak current
70
AVSS, AVRL < VI <
AVCC, AVRH
µA Single port pin
DS07-13807-2E
MB96370 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter
Symbol
Pin
Condition
Total LCD leak
current
Σ|IILCD|
all SEG/
COM pins
Internal LCD divide resistance
RLCD
Between
V3 and VSS
Pull-up resistance
RUP
Pnn_m,
RSTX
Value
Unit
Remarks
Min
Typ
Max
VCC = 5.0V
-
0.5
10
Maximum leakage
µA current of all LCD
pins
VCC = 5.0V
25
40
65
kΩ
VCC = 3.3V ± 10%
40
100
160
kΩ
VCC = 5.0V ± 10%
25
50
100
kΩ
Note: Input/output voltages of high current ports depend on DVCC, of other ports on VCC.
DS07-13807-2E
71
MB96370 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter
Symbol
Typ
Max
+25˚C
10
13
+125˚C
10.5
15
1 Flash/ROM wait state
+25˚C
17.5
23
(CLKRC and CLKSC
stopped)
+125˚C
19
26
+25˚C
18
23
+125˚C
18.5
25
2 Flash/ROM wait states
+25˚C
28
34
(CLKRC and CLKSC
stopped)
+125˚C
30
37.5
+25˚C
17
22
+125˚C
17.5
24
0 Flash/ROM wait states
+25˚C
32
44
(CLKRC and CLKSC
stopped)
+125˚C
34
47.5
PLL Run mode with
+25˚C
CLKS1/2 = 80MHz,
CLKB = CLKP1 = 40MHz, +125˚C
CLKP2 = 20MHz
25
30
25.5
32
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1 = 16MHz,
CLKP2 = 8MHz
PLL Run mode with
CLKS1/2 = CLKB =
CLKP1 = 32MHz,
CLKP2 = 16MHz
ICCPLL
Power supply current in Run
modes*
PLL Run mode with
CLKS1/2 = 48MHz,
CLKB = CLKP1/2 =
24MHz
mA MB96375
mA MB96F378/F379
mA MB96375
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+125˚C
46
61.5
+25˚C
2.5
3.5
+125˚C
3
5
+25˚C
4.8
5.8
+125˚C
5.5
8.2
+25˚C
1.3
2.3
+125˚C
1.8
3.8
+25˚C
3
4.1
+125˚C
3.7
6.5
1 Flash/ROM wait state
(CLKMC, CLKPLL and
CLKSC stopped)
72
mA MB96F378/F379
58
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 2MHz
ICCRCH
mA MB96375
44
(CLKPLL, CLKSC and
CLKRC stopped)
Remarks
mA MB96F378/F379
+25˚C
1 Flash/ROM wait state
Unit
mA MB96375
1 Flash/ROM wait state
Main Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 4MHz
ICCMAIN
Value
Condition (at TA)
mA MB96F378/F379
mA MB96375
mA MB96F378/F379
mA MB96375
mA MB96F378/F379
DS07-13807-2E
MB96370 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter
Symbol
Typ
Max
+25˚C
0.12
0.23
+125˚C
0.5
1.66
1 Flash/ROM wait state
+25˚C
0.4
0.6
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
+125˚C
0.95
2.8
+25˚C
0.09
0.18
+125˚C
0.48
1.6
+25˚C
0.15
0.25
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
+125˚C
regulator in low power
mode, no Flash programming/erasing allowed)
0.7
2.45
+25˚C
0.04
0.12
+125˚C
0.43
1.55
+25˚C
(CLKMC, CLKPLL and
CLKRC stopped, no Flash
programming/erasing al- +125˚C
lowed)
0.1
0.2
0.65
2.4
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 100kHz,
SMCR:LPMS = 0
ICCRCL
Power supply current in Run
modes*
RC Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 100kHz,
SMCR:LPMS = 1
1 Flash/ROM wait state
Sub Run mode with
CLKS1/2 = CLKB =
CLKP1/2 = 32kHz
ICCSUB
DS07-13807-2E
Value
Condition (at TA)
1 Flash/ROM wait state
Unit
Remarks
mA MB96375
mA MB96F378/F379
mA MB96375
mA MB96F378/F379
mA MB96375
mA MB96F378/F379
73
MB96370 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter
Symbol
Value
Condition (at TA)
PLL Sleep mode with
CLKS1/2 = CLKP1 =
16MHz,
CLKP2 = 8MHz
(CLKRC and CLKSC
stopped)
PLL Sleep mode with
CLKS1/2 = CLKP1 =
32MHz,
CLKP2 = 16MHz
(CLKRC and CLKSC
stopped)
Typ
Max
+25˚C
5
7
+125˚C
5.5
9
+25˚C
5
7
+125˚C
5.7
9.5
+25˚C
9
11.5
+125˚C
9.5
13.5
+25˚C
9
11.5
+125˚C
10
14
+25˚C
9
11
+125˚C
9.5
13
+25˚C
9
11
+125˚C
10
13.5
+25˚C
13
15.5
+125˚C
13.5
17.5
+25˚C
13
15.5
+125˚C
14
18
+25˚C
1.3
1.7
+125˚C
1.8
3.2
+25˚C
1.5
2
+125˚C
2.1
4.2
+25˚C
0.7
1.1
+125˚C
1.2
2.6
+25˚C
0.9
1.5
+125˚C
1.5
3.7
Unit
Remarks
mA MB96375
mA MB96F378/F379
mA MB96375
mA MB96F378/F379
ICCSPLL
PLL Sleep mode with
CLKS1/2 = 48MHz,
CLKP1/2 = 24MHz
(CLKRC and CLKSC
stopped)
Power supply current in Sleep
modes*
PLL Sleep mode with
CLKS1/2 = 80MHz,
CLKP1 = 40MHz,
CLKP2 = 20MHz
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
ICCSMAIN
Main Sleep mode with
CLKS1/2 = CLKP1/2 =
4MHz
(CLKPLL, CLKSC and
CLKRC stopped)
ICCSRCH
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
2MHz
(CLKMC, CLKPLL and
CLKSC stopped)
74
mA MB96375
mA MB96F378/F379
mA MB96375
mA MB96F378/F379
mA MB96375
mA MB96F378/F379
mA MB96375
mA MB96F378/F379
DS07-13807-2E
MB96370 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter
Symbol
Typ
Max
+25˚C
0.08
0.19
+125˚C
0.47
1.6
+25˚C
0.3
0.5
+125˚C
0.8
2.7
+25˚C
0.05
0.14
+125˚C
0.44
1.56
+25˚C
0.05
0.15
+125˚C
0.56
2.3
+25˚C
0.035
0.11
+125˚C
0.42
1.55
+25˚C
0.04
0.12
+125˚C
0.54
2.3
+25˚C
PLL Timer mode with
CLKMC = 4MHz, CLKPLL
+125˚C
= 48MHz
1.2
1.7
1.7
3.3
(CLKRC and CLKSC
stopped. Core voltage at
1.9V)
+25˚C
1.5
2
+125˚C
2.1
4.4
+25˚C
0.11
0.2
+125˚C
0.5
1.65
+25˚C
0.35
0.5
+125˚C
0.85
2.7
+25˚C
0.08
0.15
+125˚C
0.47
1.6
+25˚C
0.08
0.15
+125˚C
0.6
2.3
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
100kHz,
SMCR:LPMSS = 0
ICCSRCL
Power supply current in Sleep
modes*
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
RC Sleep mode with
CLKS1/2 = CLKP1/2 =
100kHz,
SMCR:LPMSS = 1
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode)
ICCSSUB
Sub Sleep mode with
CLKS1/2 = CLKP1/2 =
32kHz
(CLKMC, CLKPLL and
CLKRC stopped)
ICCTPLL
Main Timer mode with
CLKMC = 4MHz,
SMCR:LPMSS = 0
Power supply current in Timer
modes*
Value
Condition (at TA)
(CLKPLL, CLKRC and
CLKSC stopped. Voltage
regulator in high power
mode)
Unit
Remarks
mA MB96375
mA MB96F378/F379
mA MB96375
mA MB96F378/F379
mA MB96375
mA MB96F378/F379
mA MB96375
mA MB96F378/F379
mA MB96375
mA MB96F378/F379
ICCTMAIN
Main Timer mode with
CLKMC = 4MHz,
SMCR:LPMSS = 1
(CLKPLL, CLKRC and
CLKSC stopped. Voltage
regulator in low power
mode)
DS07-13807-2E
mA MB96375
mA MB96F378/F379
75
MB96370 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter
Symbol
Value
Condition (at TA)
Typ
Max
+25˚C
0.1
0.2
+125˚C
0.49
1.65
+25˚C
0.35
0.5
+125˚C
0.85
2.7
+25˚C
0.07
0.15
+125˚C
0.46
1.6
+25˚C
0.07
0.15
+125˚C
0.6
2.3
+25˚C
0.06
0.15
+125˚C
0.44
1.6
+25˚C
0.3
0.45
+125˚C
0.8
2.6
+25˚C
0.03
0.1
+125˚C
0.41
1.55
+25˚C
0.03
0.1
+125˚C
0.53
2.25
+25˚C
0.03
0.1
Sub Timer mode with
CLKSC = 32kHz
+125˚C
0.41
1.55
(CLKMC, CLKPLL and
CLKRC stopped)
+25˚C
0.035
0.1
+125˚C
0.53
2.25
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 0
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
Unit
Remarks
mA MB96375
mA MB96F378/F379
ICCTRCH
RC Timer mode with
CLKRC = 2MHz,
SMCR:LPMSS = 1
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode)
RC Timer mode with
CLKRC = 100kHz,
SMCR:LPMSS = 0
Power supply current in Timer
modes*
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in high power
mode)
mA MB96375
mA MB96F378/F379
mA MB96375
mA MB96F378/F379
ICCTRCL
RC Timer mode with
CLKRC = 100kHz,
SMCR:LPMSS = 1
(CLKMC, CLKPLL and
CLKSC stopped. Voltage
regulator in low power
mode)
ICCTSUB
76
mA MB96375
mA MB96F378/F379
mA MB96375
mA MB96F378/F379
DS07-13807-2E
MB96370 Series
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter
Symbol
Value
Condition (at TA)
Unit
Remarks
Typ
Max
+25˚C
0.02
0.08
VRCR:LPMB[2:0] = 110B
+125˚C
0.4
1.5
(Core voltage at 1.8V)
+25˚C
0.02
0.08
+125˚C
0.52
2.2
+25˚C
0.015
0.06
VRCR:LPMB[2:0] = 000B
+125˚C
0.3
1.2
(Core voltage at 1.2V)
+25˚C
0.015
0.06
+125˚C
0.4
1.65
+25˚C
5
10
µA
MB96375
+125˚C
7
20
µA
Must be added to all
current above
+25˚C
90
140
mA MB96375
mA MB96F378/F379
Power supply current in Stop Mode
ICCH
mA MB96375
mA MB96F378/F379
Power supply current for active Low
Voltage detector
ICCLVD
Low voltage detector enabled (RCR:LVDE = 1)
MB96F378/F379
µA
+125˚C
100
150
Must be added to all
current above
Power supply current for active
Clock modulator
ICCCLOMO
Clock modulator enabled
(CMCR:PDX = 1)
-
3
4.5
mA
Must be added to all
current above
Flash Write/Erase
current
ICCFLASH
Current for one Flash
module
-
15
40
mA
Must be added to all
current above
Input capacitance
CIN
-
-
15
30
pF
High current outputs
pF
Other than C, AVCC,
AVSS, AVRH, AVRL,
VCC, VSS, DVCC, DVSS,
High current outputs
Input capacitance
CIN
-
-
5
15
*: The power supply current is measured with a 4MHz external clock connected to the Main oscillator and a 32kHz
external clock connected to the Sub oscillator. Please refer to chapter “Standby mode and voltage regulator control
circuit” of the Hardware Manual for further details about voltage regulator control.
DS07-13807-2E
77
MB96370 Series
4. AC Characteristics
Source Clock timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter
Clock frequency
Clock frequency
Symbol
fC
fFCI
Pin
X0, X1
fCL
X0A
Clock frequency
fCR
Unit
Remarks
Min
Typ
Max
3
-
16
MHz When using a crystal oscillator, PLL off
0
-
16
MHz
When using an opposite phase external
clock, PLL off
3.5
-
16
MHz
When using a crystal oscillator or opposite phase external clock, PLL on
0
-
56
MHz
When using a single phase external
clock in “Fast Clock Input mode” , PLL off
3.5
-
56
MHz
When using a single phase external
clock in “Fast Clock Input mode” , PLL on
32
32.768
100
kHz When using an oscillation circuit
0
-
100
kHz
When using an opposite phase external
clock
0
-
50
kHz
When using a single phase external
clock
50
100
200
kHz
When using slow frequency of RC oscillator
1
2
4
MHz
When using fast frequency of RC oscillator
X0
X0A, X1A
Clock frequency
Value
-
RC clock stabilization time
tRCSTAB
-
64 or 256 RC clock cycles
Applied after any reset and when activating the RC oscillator.
MB96375: 256 cycles
MB96F378/F379: 64 cycles
PLL Clock frequency
fCLKVCO
-
64
-
200
MHz
Permitted VCO output frequency of PLL
(CLKVCO)
PLL Phase Jitter
TPSKEW
-
-
-
±5
ns
For CLKMC (PLL input clock) ≥ 4MHz,
jitter coming from external oscillator,
crystal or resonator is not covered
Input clock pulse
width
PWH, PWL
X0,X1
8
-
-
ns
Duty ratio is about 30% to 70%
5
-
-
µs
Input clock pulse
width
78
PWHL, PWLL X0A,X1A
DS07-13807-2E
MB96370 Series
tCYL
VIH
X0
VIL
PWH
PWL
tCYLL
VIH
X0A
VIL
PWHL
PWLL
When using an oscillation circuit
tCYL
Amplitude:
It varies depending on the external resistance, power rating
and the different kind of device.
Reference values: 1 V to 2.5 V
X0, X1
When using an oscillation circuit
tCYLL
X0A, X1A
DS07-13807-2E
Amplitude:
It varies depending on the external resistance, power rating
and the different kind of device.
Reference values: 1 V to 2.5 V
79
MB96370 Series
Internal Clock timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Core Voltage Settings
Parameter
Internal System clock frequency (CLKS1 and
CLKS2)
Internal CPU clock frequency (CLKB), internal
peripheral clock frequency
(CLKP1)
Internal peripheral clock
frequency (CLKP2)
80
Symbol
fCLKS1, fCLKS2
fCLKB, fCLKP1
fCLKP2
1.8V
1.9V
Unit
Remarks
Min
Max
Min
Max
0
92
0
96
MHz
Others than below
0
72
0
80
MHz
MB96375/
MB96F378/
MB96F379
0
52
0
56
MHz
Others than below
0
36
0
40
MHz
MB96375/
MB96F378/
MB96F379
0
28
0
32
MHz
DS07-13807-2E
MB96370 Series
External Reset timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter
Reset input time
Symbol
Pin
tRSTL
RSTX
Value
Min
Typ
Max
500
-
-
Unit
Remarks
ns
tRSTL
RSTX
0.2 VCC
DS07-13807-2E
0.2 VCC
81
MB96370 Series
Power On Reset timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter
Power on rise time
Power off time
Symbol
Pin
tR
tOFF
Value
Unit
Min
Typ
Max
Vcc
0.05
-
30
ms
Vcc
1
-
-
ms
Remarks
tR
2.7V
VCC
0.2 V
0.2 V
0.2 V
tOFF
If the power supply is changed too rapidly, a power-on reset may occur.
We recommend a smooth startup by restraining voltages when changing the
power supply voltage during operation, as shown in the figure below.
VCC
3V
82
Rising edge of 50 mV/ms
maximum is allowed
DS07-13807-2E
MB96370 Series
External Input timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol
Pin
Value
Condition
INTn(_R)
NMI(_R)
Input pulse
width
tINH,
tINL
Min
Max
200
-
Unit
Used Pin input function
External Interrupt
ns
NMI
Pnn_m
General-Purpose IO
TINn(_R)
Reload Timer
-
TTGn(_R)
PPG Trigger input
2*tCLKP1 + 200
(tCLKP1=1/
fCLKP1)
ADTG(_R)
-
ns
AD Converter Trigger
FRCKn(_R)
Free Running Timer
external clock
INn(_R)
Input Capture
Note : Relocated Resource Inputs have same characteristics.
External Pin input
VIH
VIH
tINH
DS07-13807-2E
VIL
VIL
tINL
83
MB96370 Series
Slew Rate High Current Outputs
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter Symbol
Output
rise/fall
time
tR30,
tF30
Pin
Condition
I/O circuit type M
Output
driving
strength
set to
“30mA”
Value
Min
Max
15
-
Unit
Remarks
ns
Note : Relocated Resource Inputs have same characteristics.
• Slew rate output timing
VH
VH
VL
VL
tR30
84
VH = VOL30 + 0.9 × (VOH30 - VOL30)
VL = VOL30 + 0.1 × (VOH30 - VOL30)
tF30
DS07-13807-2E
MB96370 Series
External Bus timing
Note: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output
timing described in the different tables must then be increased by 10ns.
Basic Timing
Parameter
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Symbol
Pin
Condition
Min
Max
25
-
tCYC/2-5
tCYC/2+5
tCLCH
tCYC/2-5
tCYC/2+5
tCHCBH
-20
+20
-20
+20
-20
+20
tCLCBL
-20
+20
tCHLH
-10
+10
-10
+10
-10
+10
-10
+10
-15
+15
-15
+15
-15
+15
-15
+15
-15
+15
-15
+15
-10
+10
-10
+10
-10
+10
-10
+10
tCYC
ECLK
ECLK →
UBX/ LBX / CSn time
ECLK → ALE time
tCHCL
tCHCBL
tCLCBH
tCHLL
tCLLH
ECLK
CSn, UBX,
LBX, ECLK
ALE, ECLK
-
-
-
tCLLL
ECLK → address valid time
(non-multiplexed)
tCHAV
tCLAV
tCHAV
ECLK → address valid time
(multiplexed)
tCLAV
tCLADV
tCHADV
A[23:0], ECLK
EBM:NMS=1
A[23:16],
ECLK
EBM:NMS=0
AD[15:0],
ECLK
EBM:NMS=0
tCHRWH
ECLK → RDX /WRX time
tCHRWL
tCLRWH
tCLRWL
DS07-13807-2E
Value
RDX, WRX,
WRLX,WRHX,
ECLK
-
Unit
Remarks
ns
ns
ns
ns
ns
ns
ns
85
MB96370 Series
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
Pin
Condition
Min
Max
30
-
tCYC/2-8
tCYC/2+8
tCLCH
tCYC/2-8
tCYC/2+8
tCHCBH
-25
+25
-25
+25
-25
+25
tCLCBL
-25
+25
tCHLH
-15
+15
-15
+15
-15
+15
-15
+15
-20
+20
-20
+20
-20
+20
-20
+20
-20
+20
-20
+20
-15
+15
-15
+15
-15
+15
-15
+15
tCYC
ECLK
ECLK →
UBX/ LBX / CSn time
ECLK → ALE time
tCHCL
tCHCBL
tCLCBH
tCHLL
tCLLH
ECLK
CSn, UBX,
LBX, ECLK
ALE, ECLK
-
-
-
tCLLL
ECLK → address valid time
(non-multiplexed)
tCHAV
tCLAV
tCHAV
ECLK → address valid time
(multiplexed)
tCLAV
tCLADV
tCHADV
A[23:0], ECLK EBM:NMS=1
A[23:16],
ECLK
EBM:NMS=0
AD[15:0],
ECLK
EBM:NMS=0
tCHRWH
ECLK → RDX /WRX time
tCHRWL
tCLRWH
tCLRWL
86
Value
RDX, WRX,
WRLX, WRHX,
ECLK
-
Unit
Remarks
ns
ns
ns
ns
ns
ns
ns
DS07-13807-2E
MB96370 Series
tCYC
tCHCL
ECLK
tCLCH
0.8*Vcc
0.2*Vcc
tCLAV
tCHAV
A[23:0]
tCHCBL
tCLCBH
tCLCBL
tCHCBH
tCHRWL
tCLRWH
tCLRWL
tCHRWH
CSn
LBX
UBX
RDX
WRX (WRLX, WRHX)
tCLLH
tCHLL
tCHLH
tCLLL
ALE
tCHADV
tCLADV
AD[15:0]
Address
Refer to the Hardware Manual for detailed Timing Charts
DS07-13807-2E
87
MB96370 Series
Bus Timing (Read)
Parameter
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Symbol
Pin
Conditions
Min
Max
tCYC/2 − 5
-
tCYC − 5
-
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 − 5
-
EACL:STS=0 and
EACL:ACE=0
tCYC − 15
-
EACL:STS=0 and
EACL:ACE=0
ALE pulse width
(multiplexed)
tLHLL ALE
tAVLL ALE, A[23:16]
Valid address
⇒ ALE ↓ time
(multiplexed)
tADVLL ALE,AD[15:0]
ALE ↓
⇒ Address valid time
(multiplexed)
tLLAX ALE, AD[15:0]
Valid address
⇒ RDX ↓ time
(non-multiplexed)
tAVRL RDX, A[23:0]
tAVRL
RDX, A[23:16]
Valid address
⇒ RDX ↓ time
(multiplexed)
tADVRL RDX, AD[15:0]
Valid address
⇒ Valid data input
(non-multiplexed)
88
tAVDV
A[23:0],
AD[15:0]
Value
EACL:STS=1
EACL:STS=1 and
3tCYC/2 − 15
EACL:ACE=0
-
EACL:STS=0 and
EACL:ACE=1
-
2tCYC − 15
Unit
Remarks
ns
ns
EACL:STS=1 and
5tCYC/2 − 15
EACL:ACE=1
-
EACL:STS=0 and
EACL:ACE=0
tCYC/2 − 15
-
EACL:STS=1 and
EACL:ACE=0
tCYC − 15
-
EBM:NMS =
0
ns
EACL:STS=0 and
3tCYC/2 − 15
EACL:ACE=1
-
EACL:STS=1 and
EACL:ACE=1
2tCYC − 15
-
EACL:STS=0
tCYC/2 − 15
-
EACL:STS=1
-15
-
EBM:NMS= 1
tCYC/2 − 15
-
EACL:ACE=0
EBM:NMS=0
3tCYC/2 − 15
-
EACL:ACE=1
EBM:NMS=0
5tCYC/2 − 15
-
EACL:ACE=0
EBM:NMS=0
tCYC − 15
-
EACL:ACE=1
EBM:NMS=0
2tCYC − 15
-
EBM:NMS= 1
-
2tCYC − 55
ns
ns
ns
ns
ns
w/o cycle
extension
DS07-13807-2E
MB96370 Series
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
tAVDV
Valid address
⇒ Valid data input
(multiplexed)
Pin
A[23:16],
AD[15:0]
tADVDV AD[15:0]
Conditions
Value
Unit
Remarks
ns
w/o cycle
extension
ns
w/o cycle
extension
ns
w/o cycle
extension
3tCYC/2 − 50 ns
w/o cycle
extension
Min
Max
EACL:ACE=0
EBM:NMS=0
-
3tCYC − 55
EACL:ACE=1
EBM:NMS=0
-
4tCYC − 55
EACL:ACE=0
EBM:NMS=0
-
5tCYC/2 − 55
EACL:ACE=1
EBM:NMS=0
-
7tCYC/2 − 55
-
RDX pulse width
tRLRH RDX
-
3tCYC/2 − 5
RDX ↓ ⇒ Valid data input
tRLDV RDX, AD[15:0]
-
-
RDX ↑ ⇒ Data hold time
tRHDX RDX, AD[15:0]
-
0
-
ns
Address valid ⇒ Data hold
time
tAXDX
A[23:0],
AD[15:0]
-
0
-
ns
RDX ↑ ⇒ ALE ↑ time
tRHLH RDX, ALE
tAVCH A[23:0], ECLK
Valid address
⇒ ECLK ↑ time
tADVCH AD[15:0], ECLK
RDX ↓ ⇒ ECLK ↑ time
tRLCH RDX, ECLK
ALE ↓ ⇒ RDX ↓ time
tLLRL ALE, RDX
ECLK↑ ⇒ Valid data input
tCHDV AD[15:0], ECLK
DS07-13807-2E
EACL:STS=1 and
3tCYC/2 − 10
EACL:ACE=1
-
other ECL:STS,
tCYC/2 − 10
EACL:ACE setting
-
ns
tCYC − 15
-
tCYC/2 − 15
-
tCYC/2 − 10
-
EACL:STS=0
tCYC/2 − 10
-
EACL:STS=1
− 10
-
-
tCYC − 50
-
-
ns
ns
ns
ns
89
MB96370 Series
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
Pin
Conditions
Min
Max
tCYC/2 − 8
-
tCYC − 8
-
EACL:STS=0 and
EACL:ACE=1
3tCYC/2 − 8
-
EACL:STS=0 and
EACL:ACE=0
tCYC − 20
-
EACL:STS=0 and
EACL:ACE=0
ALE pulse width
(multiplexed)
tLHLL ALE
tAVLL ALE, A[23:16]
Valid address
⇒ ALE ↓ time
(multiplexed)
tADVLL ALE, AD[15:0]
ALE ↓
⇒ Address valid time
(multiplexed)
tLLAX ALE, AD[15:0]
Valid address
⇒ RDX ↓ time
(non-multiplexed)
tAVRL RDX, A[23:0]
tAVRL
RDX, A[23:16]
Valid address
⇒ RDX ↓ time
(multiplexed)
tADVRL RDX, AD[15:0]
Valid address
⇒ Valid data input
(non-multiplexed)
90
tAVDV
A[23:0],
AD[15:0]
Value
EACL:STS=1
EACL:STS=1 and
3tCYC/2 − 20
EACL:ACE=0
-
EACL:STS=0 and
EACL:ACE=1
-
2tCYC − 20
Unit
Remarks
ns
ns
EACL:STS=1 and
5tCYC/2 − 20
EACL:ACE=1
-
EACL:STS=0 and
EACL:ACE=0
tCYC/2 − 20
-
EACL:STS=1 and
EACL:ACE=0
tCYC − 20
-
EBM:NMS
=0
ns
EACL:STS=0 and
3tCYC/2 − 20
EACL:ACE=1
-
EACL:STS=1 and
EACL:ACE=1
2tCYC − 20
-
EACL:STS=0
tCYC/2 − 20
-
EACL:STS=1
-20
-
EBM:NMS= 1
tCYC/2 − 20
-
EACL:ACE=0
EBM:NMS=0
3tCYC/2 − 20
-
EACL:ACE=1
EBM:NMS=0
5tCYC/2 − 20
-
EACL:ACE=0
EBM:NMS=0
tCYC − 20
-
EACL:ACE=1
EBM:NMS=0
2tCYC − 20
-
EBM:NMS= 1
-
2tCYC − 60
ns
ns
ns
ns
ns
w/o cycle
extension
DS07-13807-2E
MB96370 Series
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
tAVDV
Valid address
⇒ Valid data input
(multiplexed)
Pin
A[23:16],
AD[15:0]
tADVDV AD[15:0]
Conditions
Value
Unit
Remarks
ns
w/o cycle
extension
ns
w/o cycle
extension
ns
w/o cycle
extension
3tCYC/2 − 55 ns
w/o cycle
extension
Min
Max
EACL:ACE=0
EBM:NMS=0
-
3tCYC − 60
EACL:ACE=1
EBM:NMS=0
-
4tCYC − 60
EACL:ACE=0
EBM:NMS=0
-
5tCYC/2 − 60
EACL:ACE=1
EBM:NMS=0
-
7tCYC/2 − 60
-
RDX pulse width
tRLRH RDX
-
3tCYC/2 − 8
RDX ↓ ⇒ Valid data input
tRLDV RDX, AD[15:0]
-
-
RDX ↑ ⇒ Data hold time
tRHDX RDX, AD[15:0]
-
0
-
ns
Address valid ⇒ Data hold
time
tAXDX A[23:0]
-
0
-
ns
RDX ↑ ⇒ ALE ↑ time
tRHLH RDX, ALE
tAVCH A[23:0], ECLK
Valid address
⇒ ECLK ↑ time
tADVCH AD[15:0], ECLK
RDX ↓ ⇒ ECLK ↑ time
tRLCH RDX, ECLK
ALE ↓ ⇒ RDX ↓ time
tLLRL ALE, RDX
ECLK↑ ⇒ Valid data input
tCHDV AD[15:0], ECLK
DS07-13807-2E
EACL:STS=1 and
3tCYC/2 − 15
EACL:ACE=1
-
other ECL:STS,
tCYC/2 − 15
EACL:ACE setting
-
ns
tCYC − 20
-
tCYC/2 − 20
-
tCYC/2 − 15
-
EACL:STS=0
tCYC/2 − 15
-
EACL:STS=1
− 15
-
-
tCYC − 55
-
-
ns
ns
ns
ns
91
MB96370 Series
tAVCH
tRLCH
tADVCH
tCHDV
0.8*Vcc
ECLK
tAVLL
tLLAX
tADVLL
ALE
tRHLH
0.2*VCC
tLHLL
tAVRL
tADVRL
tRLRH
RDX
tLLRL
A[23:0]
tRLDV
tAXDX
tAVDV
tRHDX
tADVDV
AD[15:0]
VIH
VIH
Address
Read data
VIL
VIL
Refer to the Hardware Manual for detailed Timing Charts
.
Bus Timing (Write)
Parameter
Valid address
⇒ WRX ↓ time
(non-multiplexed)
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Symbol
tAVWL
tAVWL
Valid address
⇒ WRX ↓ time
(multiplexed)
tADVWL
WRX pulse width
92
tWLWH
Pin
WRX, WRLX,
WRHX,
A[23:0]
WRX, WRLX,
WRHX,
A[23:16]
WRX, WRLX,
WRHX,
AD[15:0]
WRX, WRLX,
WRHX
Condition
EACL:STS=0
EBM:NMS=1
Value
Min
Max
tCYC/2 − 15
-
Remarks
ns
EACL:STS=1
EBM:NMS=1
tCYC − 15
-
EACL:ACE=0
EBM:NMS=0
3tCYC/2 −
15
-
EACL:ACE=1
EBM:NMS=0
5tCYC/2 −
15
-
EACL:ACE=0
EBM:NMS=0
tCYC − 15
-
EACL:ACE=1
EBM:NMS=0
2tCYC − 15
-
tCYC − 5
-
-
Unit
ns
ns
ns
w/o cycle
extension
DS07-13807-2E
MB96370 Series
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
Pin
Condition
Value
Min
Max
Unit
Valid data output
⇒ WRX ↑ time
tDVWH
WRX, WRLX,
WRHX,
AD[15:0]
-
tCYC − 20
-
ns
WRX ↑
⇒ Data hold time
tWHDX
WRX, WRLX,
WRHX,
AD[15:0]
-
tCYC/2 − 15
-
ns
WRX ↑
⇒ Address valid time
(non-multiplexed)
− 15
-
ns
tWHAX
WRX, WRLX, EBM:NMS=1
WRHX, A[23:0] EACL:STS=0
EBM:NMS=1
tCYC/2 − 15
-
ns
WRX ↑
⇒ Address valid time
(multiplexed)
tWHAX
WRX, WRLX,
WRHX,
A[23:16]
EBM:NMS=0
tCYC/2 − 15
-
ns
2tCYC − 10
-
WRX, WRLX,
WRHX, ALE
EBM:ACE=1 and
EACL:STS=1
other EBM:ACE
and
EACL:STS setting
tCYC − 10
-
WRX, WRLX,
WRHX, ECLK
-
tCYC/2 − 10
-
EACL:STS=0
EBM:NMS=1
-
tCYC/2 − 15
EACL:STS=1
EBM:NMS=1
-
tCYC − 15
EACL:ACE=0
EBM:NMS=0
-
3tCYC/2 −
15
-
5tCYC/2 −
15
EACL:STS=1
WRX ↑ ⇒ ALE ↑ time
(multiplexed)
tWHLH
WRX ↓ ⇒ ECLK ↑
time
tWLCH
CSn ⇒ WRX time
(non-multiplexed)
CSn ⇒ WRX time
(multiplexed)
WRX, WRLX,
WRHX, CSn
tCSLWL
WRX, WRLX,
WRHX, CSn
tCSLWL
WRX ⇒ CSn time
(non-multiplexed)
tWHCSH
WRX ⇒ CSn time
(multiplexed)
tWHCSH
EACL:ACE=1
EBM:NMS=0
ns
Remarks
w/o cycle
extension
EBM:NMS=0
ns
ns
ns
WRX, WRLX,
WRHX, CSn
EACL:STS=1
EBM:NMS=1
EACL:STS=0
EBM:NMS=1
− 15
-
ns
tCYC/2 − 15
-
ns
WRX, WRLX,
WRHX, CSn
EBM:NMS=0
tCYC/2 − 15
-
ns
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Valid address
⇒ WRX ↓ time
(non-multiplexed)
DS07-13807-2E
Symbol
tAVWL
Pin
WRX, WRLX,
WRHX,
A[23:0]
Condition
Value
Min
Max
EACL:STS=0
EBM:NMS=1
tCYC/2 − 20
-
EACL:STS=1
EBM:NMS=1
tCYC − 20
-
Unit
Remarks
ns
93
MB96370 Series
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
tAVWL
Valid address
⇒ WRX ↓ time
(multiplexed)
tADVWL
Pin
WRX, WRLX,
WRHX,
A[23:16]
WRX, WRLX,
WRHX,
AD[15:0]
Condition
Value
Min
Max
EACL:ACE=0
EBM:NMS=0
3tCYC/2 −
20
-
EACL:ACE=1
EBM:NMS=0
5tCYC/2 −
20
-
EACL:ACE=0
EBM:NMS=0
tCYC − 20
-
EACL:ACE=1
EBM:NMS=0
2tCYC − 20
-
Unit
Remarks
ns
ns
WRX pulse width
tWLWH
WRX, WRLX,
WRHX
-
tCYC − 8
-
ns
w/o cycle
extension
Valid data output
⇒ WRX ↑ time
tDVWH
WRX, WRLX,
WRHX,
AD[15:0]
-
tCYC − 25
-
ns
w/o cycle
extension
WRX ↑
⇒ Data hold time
tWHDX
WRX, WRLX,
WRHX,
AD[15:0]
-
tCYC/2 − 20
-
ns
WRX ↑
⇒ Address valid time
(non-multiplexed)
− 20
-
ns
tWHAX
WRX, WRLX, EBM:NMS=1
WRHX, A[23:0] EACL:STS=0
EBM:NMS=1
tCYC/2 − 20
-
ns
WRX ↑
⇒ Address valid time
(multiplexed)
tWHAX
WRX, WRLX,
WRHX,
A[23:16]
EBM:NMS=0
tCYC/2 − 20
-
ns
2tCYC − 15
-
WRX, WRLX,
WRHX, ALE
EBM:ACE=1 and
EACL:STS=1
other EBM:ACE
and
EACL:STS setting
tCYC − 15
-
-
tCYC/2 − 15
-
EACL:STS=0
EBM:NMS=1
-
tCYC/2 − 20
EACL:STS=1
EBM:NMS=1
-
tCYC − 20
EACL:ACE=0
EBM:NMS=0
-
3tCYC/2 −
20
EACL:ACE=1
EBM:NMS=0
-
5tCYC/2 −
20
EACL:STS=1
WRX ↑ ⇒ ALE ↑ time
(multiplexed)
tWHLH
WRX ↓ ⇒ ECLK ↑
time
tWLCH
WRX, WRLX,
WRHX, ECLK
tCSLWL
WRX, WRLX,
WRHX, CSn
CSn ⇒ WRX time
(non-multiplexed)
CSn ⇒ WRX time
(multiplexed)
tCSLWL
WRX ⇒ CSn time
(non-multiplexed)
tWHCSH
WRX ⇒ CSn time
(multiplexed)
tWHCSH
94
WRX, WRLX,
WRHX, CSn
ns
EBM:NMS=0
ns
ns
ns
WRX, WRLX,
WRHX, CSn
EACL:STS=1
EBM:NMS=1
EACL:STS=0
EBM:NMS=1
− 20
-
ns
tCYC/2 − 20
-
ns
WRX, WRLX,
WRHX, CSn
EBM:NMS=0
tCYC/2 − 20
-
ns
DS07-13807-2E
MB96370 Series
tWLCH
0.8*VCC
ECLK
tWHLH
ALE
.
tAVWL
tWLWH
tADVWL
WRX (WRLX, WRHX)
0.2*VCC
tCSLWL
tWHCSH
CSn
tWHAX
A[23:0]
tDVWH
AD[15:0]
tWHDX
Write data
Address
Refer to the Hardware Manual for detailed Timing Charts
Ready Input Timing
Parameter
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Symbol
Pin
RDY setup time
tRYHS
RDY
RDY hold time
tRYHH
RDY
Test
Condition
-
Rated Value
Units
Min
Max
35
-
ns
0
-
ns
Remarks
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
Pin
RDY setup time
tRYHS
RDY
RDY hold time
tRYHH
RDY
Test
Condition
-
Rated Value
Units
Min
Max
45
-
ns
0
-
ns
Remarks
Note : If the RDY setup time is insufficient, use the auto-ready function.
DS07-13807-2E
95
MB96370 Series
0.8*VCC
ECLK
tRYHS
tRYHH
VIH
VIH
RDY
When WAIT is not used.
RDY
When WAIT is used.
VIL
Refer to the Hardware Manual for detailed Timing Charts
Hold Timing
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
Pin
Pin floating ⇒ HAKX ↓ time
tXHAL
HAKX
HAKX ↑ time ⇒ Pin valid time
tHAHV
HAKX
Value
Condition
-
Min
Max
Units
tCYC − 20 tCYC + 20
ns
tCYC − 20 tCYC + 20
ns
Remarks
(TA = −40 °C to +125 °C, VCC = 3.0 to 4.5V, VSS = 0.0 V, IOdrive = 5mA, CL = 50pF)
Parameter
Symbol
Pin
Pin floating ⇒ HAKX ↓ time
tXHAL
HAKX
HAKX ↑ time ⇒ Pin valid time
tHAHV
HAKX
Value
Condition
-
Min
Max
Units
tCYC − 25 tCYC + 25
ns
tCYC − 25 tCYC + 25
ns
Remarks
0.8*VCC
HAKX
0.2*VCC
tHAHV
tXHAL
Each pin
0.8*VCC
High-Z
0.2*VCC
Refer to the Hardware Manual for detailed Timing Charts
96
DS07-13807-2E
MB96370 Series
USART timing
Note: The values given below are for an I/O driving strength IOdrive = 5mA. If IOdrive is 2mA, all the maximum output
timing described in the different tables must then be increased by 10ns.
(TA = -40˚C to 125˚C, VCC = 3.0V to 5.5V, VSS = AVSS = 0V, IOdrive = 5mA, CL = 50pF)
Parameter
Condition
VCC = AVCC= 4.5V VCC = AVCC= 3.0V
to 5.5V
to 4.5V
Unit
Min
Max
Min
Max
Symbol
Pin
Serial clock cycle time
tSCYCI
SCKn
4 tCLKP1
-
4 tCLKP1
-
ns
SCK ↓ → SOT delay
time
tSLOVI
SCKn,
SOTn
-20
+20
-30
+30
ns
SOT → SCK ↑ delay
time
tOVSHI
SCKn,
SOTn
N*tCLKP1
- 20 *1
-
N*tCLKP1 30 *1
-
ns
Valid SIN → SCK ↑
tIVSHI
SCKn,
SINn
tCLKP1 +
45
-
tCLKP1 +
55
-
ns
SCK ↑ → Valid SIN
hold time
tSHIXI
SCKn,
SINn
0
-
0
-
ns
Serial clock “L” pulse
width
tSLSHE
SCKn
tCLKP1 +
10
-
tCLKP1 +
10
-
ns
Serial clock “H” pulse
width
tSHSLE
SCKn
tCLKP1 +
10
-
tCLKP1 +
10
-
ns
SCK ↓ → SOT delay
time
tSLOVE
SCKn,
SOTn
-
2 tCLKP1
+ 45
-
2 tCLKP1
+ 55
ns
Valid SIN → SCK ↑
tIVSHE
SCKn,
SINn
tCLKP1/2
+ 10
-
tCLKP1/2 +
10
-
ns
SCK ↑ → Valid SIN
hold time
tSHIXE
SCKn,
SINn
tCLKP1 +
10
-
tCLKP1 +
10
-
ns
SCK fall time
tFE
SCKn
-
20
-
20
ns
SCK rise time
tRE
SCKn
-
20
-
20
ns
Internal Shift
Clock Mode
External Shift
Clock Mode
Notes: • AC characteristic in CLK synchronized mode.
• CL is the load capacity value of pins when testing.
• Depending on the used machine clock frequency, the maximum possible baud rate can be limited by some
parameters. These parameters are shown in “MB96300 Super series HARDWARE MANUAL”.
• tCLKP1 is the cycle time of the peripheral clock 1 (CLKP1), Unit : ns
*1: Parameter N depends on tSCYCI and can be calculated as follows:
• if tSCYCI = 2*k*tCLKP1, then N = k, where k is an integer > 2
• if tSCYCI = (2*k+1)*tCLKP1, then N = k+1, where k is an integer > 1
Examples:
tSCYCI
N
DS07-13807-2E
4*tCLKP1
2
5*tCLKP1, 6*tCLKP1
3
7*tCLKP1, 8*tCLKP1
4
...
...
97
MB96370 Series
tSCYCI
SCK for
ESCR:SCES = 0
0.8*VCC
0.2*VCC
0.2*VCC
SCK for
ESCR:SCES = 1
0.8*VCC
0.8*VCC
0.2*VCC
tSLOVI
tOVSHI
0.8*VCC
SOT
0.2*VCC
tSHIXI
tIVSHI
SIN
VIH
VIH
VIL
VIL
Internal Shift Clock Mode
tSLSHE
SCK for
ESCR:SCES = 0
tSHSLE
VIH
VIH
VIL
VIL
VIH
VIL
tFE
VIH
VIL
VIL
SCK for
ESCR:SCES = 1
VIH
tSLOVE
tRE
SOT
0.8*VCC
0.2*VCC
tIVSHE
SIN
tSHIXE
VIH
VIH
VIL
VIL
External Shift Clock Mode
98
DS07-13807-2E
MB96370 Series
I2C Timing
(TA = -40˚C to 125˚C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Standard-mode
Symbol
Fast-mode*1
Unit
Min
Max
Min
Max
fSCL
0
100
0
400
kHz
tHDSTA
4.0
-
0.6
-
µs
“L” width of the SCL clock
tLOW
4.7
-
1.3
-
µs
“H” width of the SCL clock
tHIGH
4.0
-
0.6
-
µs
Set-up time for a repeated START condition
SCL↑→SDA↓
tSUSTA
4.7
-
0.6
-
µs
Data hold time
SCL↓→SDA↓↑
tHDDAT
0
3.45
0
0.9
µs
Data set-up time
SDA↓↑→SCL↑
tSUDAT
250
-
100
-
ns
Set-up time for STOP condition
SCL↑→SDA↑
tSUSTO
4.0
-
0.6
-
µs
Bus free time between a STOP and START
condition
tBUS
4.7
-
1.3
-
µs
Output fall time from 0.7*Vcc to 0.3*Vcc with
a bus capacitance from 10 pF to 400 pF
tof
20 + 0.1*Cb *2
300
20 + 0.1*Cb *2
300
ns
Capacitive load for each bus line
Cb
-
400
-
400
pF
Pulse width of spikes which will be suppressed by input noise filter
tSP
n/a
n/a
0
1*tCLKP1*3
ns
SCL clock frequency
Hold time (repeated) START condition
SDA↓→SCL↓
*1 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz.
*2 : Cb = capacitance of one bus line in pF.
*3 : tCLKP1 is the cycle time of the peripheral clock CLKP1.
tof
SDA
tSUDAT
tLOW
tSUSTA
tSP
tof
tBUS
SCL
tHDSTA
tHDDAT
tHIGH
tHDSTA
tSUSTO
• VOH = 0.7 * VCC
• VOL = 0.3 * VCC
• CMOS Hysteresis 0.7/0.3 input selected
DS07-13807-2E
99
MB96370 Series
5. Analog Digital Converter
(TA = -40 ˚C to +125 ˚C, 3.0 V ≤ AVRH - AVRL, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Pin
Resolution
-
Total error
Value
Unit
Min
Typ
Max
-
-
-
10
bit
-
-
-
-
±3
LSB
Nonlinearity error
-
-
-
-
± 2.5
LSB
Differential nonlinearity
error
-
-
-
-
± 1.9
LSB
Zero transition voltage
VOT
ANn
AVRL - AVRL+ AVRL +
1.5 LSB 0.5 LSB 2.5 LSB
V
Full scale transition
voltage
VFST
ANn
AVRH - AVRH - AVRH +
3.5 LSB 1.5 LSB 0.5 LSB
V
Compare time
-
-
Sampling time
-
-
Remarks
1.0
-
16,500
µs
4.5V ≤ ΑVCC ≤ 5.5V
2.0
-
-
µs
3.0V ≤ ΑVCC < 4.5V
0.5
-
-
µs
4.5V ≤ ΑVCC ≤ 5.5V
1.2
-
-
µs
3.0V ≤ ΑVCC < 4.5V
-1
-
+1
-1.2
-
+1.2
TA ≤ 105 ˚C,
µA AVSS, AVRL < VI <
AVCC, AVRH
Analog input leakage
current (during conversion)
IAIN
Analog input voltage
range
VAIN
ANn
AVRL
-
AVRH
V
AVRH
AVRH
0.75
AVcc
-
AVcc
V
AVRL
AVRL
AVSS
-
0.25
AVCC
V
IA
AVcc
-
2.5
5
mA A/D Converter active
IAH
AVcc
-
-
5
µA
IR
AVRH/
AVRL
-
0.7
1
mA A/D Converter active
IRH
AVRH/
AVRL
-
-
5
µA
-
ANn
-
-
4
LSB
Reference voltage
range
Power supply current
Reference voltage current
Offset between input
channels
ANn
105 ˚C < TA ≤ 125 ˚C,
µA AVSS, AVRL < VI <
AVCC, AVRH
A/D Converter not operated
A/D Converter not operated
Note: The accuracy gets worse as |AVRH - AVRL| becomes smaller.
100
DS07-13807-2E
MB96370 Series
Definition of A/D Converter Terms
Resolution: Analog variation that is recognized by an A/D converter.
Total error: Difference between the actual value and the ideal value. The total error includes zero transition error,
full-scale transition error and nonlinearity error.
Nonlinearity error: Deviation between a line across zero-transition line (“00 0000 0000” <--> “00 0000 0001”)
and full-scale transition line (“11 1111 1110” <--> “11 1111 1111”) and actual conversion characteristics.
Differential nonlinearity error: Deviation of input voltage, which is required for changing output code by 1 LSB,
from an ideal value.
Zero transition voltage: Input voltage which results in the minimum conversion value.
Full scale transition voltage: Input voltage which results in the maximum conversion value.
Total error
3FF
3FE
Actual conversion
characteristics
1.5 LSB
Digital output
3FD
{1 LSB × (N − 1) + 0.5 LSB}
004
VNT
(Actually-measured value)
003
Actual conversion
characteristics
Ideal characteristics
002
001
0.5 LSB
AVRL
AVRH
Analog input
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
AVRH − AVRL
1 LSB = (Ideal value)
[V]
1024
Total error of digital output “N” =
[LSB]
N: A/D converter digital output value
VOT (Ideal value) = AVRL + 0.5 LSB [V]
VFST (Ideal value) = AVRH − 1.5 LSB [V]
VNT : A voltage at which digital output transitions from (N − 1) to N.
DS07-13807-2E
101
MB96370 Series
Nonlinearity error
Differential nonlinearity error
Ideal
characteristics
3FF
Digital output
3FD
Actual conversion
characteristics
{1 LSB × (N − 1)
+ VOT }
N+1
VFST (actual
measurement
value)
VNT (actual
measurement value)
004
003
Actual conversion
characteristics
Digital output
3FE
Actual conversion
characteristics
N
V (N + 1) T
(actual measurement
value)
VNT
(actual measurement value)
N−1
002
Ideal characteristics
Actual conversion
characteristics
N−2
001
VOT (actual measurement value)
AVRL
AVRH
AVRL
Analog input
AVRH
Analog input
Nonlinearity error of digital output N =
Differential nonlinearity error of digital output N =
1 LSB =
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
V (N+1) T − VNT
1 LSB
VFST − VOT
1022
[LSB]
−1 LSB [LSB]
[V]
N
: A/D converter digital output value
VOT : Voltage at which digital output transits from “000H” to “001H.”
VFST : Voltage at which digital output transits from “3FEH” to “3FFH.”
102
DS07-13807-2E
MB96370 Series
Accuracy and setting of the A/D Converter sampling time
If the external impedance is too high or the sampling time too short, the analog voltage charged to the internal
sample and hold capacitor is insufficient, adversely affecting the A/D conversion precision.
To satisfy the A/D conversion precision, a sufficient sampling time must be selected. The required sampling time
depends on the external driving impedance Rext, the board capacitance of the A/D converter input pin Cext and
the AVcc voltage level. The following replacement model can be used for the calculation:
MCU
Analog
input
Rext
RADC
Comparator
Source
Cext
CIN
CADC
Sampling switch
Rext: external driving impedance
Cext: capacitance of PCB at A/D converter input
CIN: capacitance of MCU input pin: 15pF (max)
RADC: resistance within MCU: 2.6kΩ (max) for 4.5V ≤ AVcc ≤ 5.5V
12kΩ (max) for 3.0V ≤ AVcc < 4.5V
CADC: sampling capacitance within MCU: 10pF (max)
The sampling time should be set to minimum “7τ“. The following approximation formula for the replacement
model above can be used:
Tsamp [min] = 7 × (Rext × (Cext + CIN) + (Rext + RADC) × CADC)
• Do not select a sampling time below the absolute minimum permitted value
(0.5µs for 4.5V ≤ AVcc ≤ 5.5V; 1.2 µs for 3.0V ≤ AVcc < 4.5V).
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin. In this
case the internal sampling capacitance CADC will be charged out of this external capacitance.
• A big external driving impedance also adversely affects the A/D conversion precision due to the pin input
leakage current IIL (static current before the sampling switch) or the analog input leakage current IAIN (total
leakage current of pin input and comparator during sampling). The effect of the pin input leakage current IIL
cannot be compensated by an external capacitor.
• The accuracy gets worse as |AVRH - AVRL| becomes smaller.
DS07-13807-2E
103
MB96370 Series
6. Alarm Comparator*1
(TA = -40 ˚C to +125 ˚C, VCC = AVCC = 3.0V - 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Pin
IA5ALMF
Power supply current
IA5ALMS
AVCC
IA5ALMH
Value
Unit
Remarks
45
µA
Alarm comparator
enabled in fast
mode (one channel)
7
13
µA
Alarm comparator
enabled in slow
mode (one channel)
-
-
5
µA
Alarm comparator
disabled
-1
-
+1
µA TA = 25 ˚C
-3
-
+3
µA TA = 125 ˚C
Min
Typ
Max
-
25
-
ALARM pin input current
IALIN
ALARM pin input voltage range
VALIN
0
-
AVCC
V
External low threshold
high->low transition
VEVTL(H->L)
0.36 * AVCC
-0.25
0.36 *
AVCC -0.1
-
V
External low threshold
low->high transition
VEVTL(L->H)
-
External high threshold
high->low transition
VEVTH(H->L)
0.78 * AVCC
-0.25
External high threshold
low->high transition
VEVTH(L->H)
Internal low threshold
high->low transition
VIVTL(H->L)
Internal low threshold
low->high transition
VIVTL(L->H)
Internal high threshold
high->low transition
VIVTH(H->L)
2.2
2.4
-
V
Internal high threshold
low->high transition
VIVTH(L->H)
-
2.6
2.85
V
VHYS
50
-
300
mV
tCOMPF
-
0.1
1
µs
CMD = 1 (fast)
tCOMPS
-
1
10
µs
CMD = 0 (slow)
Power-up stabilization
time after enabling
alarm comparator
tPD
-
1
10
ms
Slow/Fast mode transition time
tCMD
-
100
500
µs
Threshold levels
specified above are
not guaranteed
within this time
Switching hysteresis
Comparison time
0.36 *
0.36 * AVCC
AVCC +0.1
+0.25
V
0.78 *
AVCC -0.1
V
-
0.78 *
0.78 * AVCC
AVCC +0.1
+0.25
ALARM0,
ALARM1
INTREF = 0
V
0.9
1.1
-
V
-
1.3
1.55
V
INTREF = 1
*1: No alarm comparator available on MB96375R.
104
DS07-13807-2E
MB96370 Series
Comparator
Output
H
L
VxVTx(H->L)
VHYS
VALIN
VxVTx(L->H)
DS07-13807-2E
105
MB96370 Series
7. Low Voltage Detector characteristics
(TA = -40 ˚C to +125 ˚C, Vcc = AVcc = 3.0V - 5.5V, Vss = AVss = 0V)
Value *1
Value *2
Unit
Remarks
110
µs
After power-up or change of detection
level
2.4
2.8
V
CILCR:LVL[3:0]=”0000”
3.1
2.8
3.2
V
CILCR:LVL[3:0]=”0001”
3.1
3.3
3
3.4
V
CILCR:LVL[3:0]=”0010”
VDL3
3.5
3.75
3.35
3.8
V
CILCR:LVL[3:0]=”0011”
Level 4
VDL4
3.6
3.85
3.5
3.95
V
CILCR:LVL[3:0]=”0100”
Level 5
VDL5
3.7
3.95
3.6
4.1
V
CILCR:LVL[3:0]=”0101”
Level 6
VDL6
3.8
4.05
3.7
4.2
V
CILCR:LVL[3:0]=”0110”
Level 7
VDL7
3.9
4.15
3.8
4.3
V
CILCR:LVL[3:0]=”0111”
Level 8
VDL8
4.0
4.25
3.9
4.4
V
CILCR:LVL[3:0]=”1000”
Level 9
VDL9
4.1
4.35
3.95
4.5
V
CILCR:LVL[3:0]=”1001”
Level 10
VDL10
not used
not used
-
Level 11
VDL11
not used
not used
-
Level 12
VDL12
not used
Level 13
VDL13
not used
not used
-
Level 14
VDL14
not used
not used
-
Level 15
VDL15
not used
not used
-
Parameter
Symbol
Stabilization time
Min
Max
Min
Max
TLVDSTAB
-
75
-
Level 0
VDL0
2.7
2.9
Level 1
VDL1
2.9
Level 2
VDL2
Level 3
2.6
3
V
CILCR:LVL[3:0]=”1100”
*1: valid for all devices except devices listed under “*2”
*2: valid for: MB96375
CILCR:LVL[3:0] are the low voltage detector level select bits of the CILCR register.
V
For correct detection, the slope of the voltage level must satisfy dV ≤ 0.004 ----- .
dt
µs
Faster variations are regarded as noise and may not be detected.
The functional operation of the MCU is guaranteed down to the minimum low voltage detection level of
“Level 0” (VDL0_MIN). The electrical characteristics however are only valid in the specified range (usually down to
3.0V).
Please use the inclination of the power-supply voltage with 0.1V/µs or less.
106
DS07-13807-2E
MB96370 Series
Low Voltage Detector Operation
In the following figure, the occurrence of a low voltage condition is illustrated. For a detailed description of the
reset and startup behavior, please refer to the corresponding hardware manual chapter.
Voltage [V]
VCC
VDLx, Max
VDLx, Min
dV
dt
Time [s]
Normal Operation
DS07-13807-2E
Low Voltage Reset Assertion
Power Reset Extension Time
107
MB96370 Series
8. FLASH memory program/erase characteristics
(TA = -40˚C to 105˚C, VCC = AVCC = 3.0V to 5.5V, DVCC = 3.0V to 5.5V, VSS = AVSS = DVSS = 0V)
Parameter
Sector erase time
Chip erase time
Value
Unit
Remarks
7.5
s
1.0
4.1
s
Includes write time prior to
internal erase
-
28.4
122.8
s
-
21.6
92.8
s
Includes write time prior to
internal erase
-
23
370
µs
Without overhead time for submitting write command
10,000
-
-
cycle
20
-
-
year
Min
Typ
Max
Large Sector
-
1.7
Small Sector
-
MB96F379
MB96F378
Word (16-bit width) programming time
Program/Erase cycle
Flash data retention time
*1
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius
equation to convert high temperature measurements into normalized value at 85oC).
108
DS07-13807-2E
MB96370 Series
■ EXAMPLE CHARACTERISTICS
1. Temperature dependency of power supply currents
The following diagrams show the current consumption of samples with typical wafer process parameters in different operation modes.
Common condition for all operation modes:
• VCC = AVCC = 5.0V
• Main clock = 4MHz external clock
• Sub clock = 32kHz external clock
Operation mode details:
Mode name
Details
PLL Run 40
PLL Run mode current ICCPLL with the following settings:
• fCLKS1 = fCLKS2 = 80MHz
• fCLKB = fCLKP1 = 40MHz
• fCLKP2 = 20MHz
• Regulator in High Power Mode
• Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)
• 1 Flash/ROM wait states (MTCRA=6B09H)
• RC oscillator and Sub oscillator stopped
PLL Run 24
PLL Run mode current ICCPLL with the following settings:
• fCLKS1 = fCLKS2 = 48MHz
• fCLKB = fCLKP1 = fCLKP2 = 24MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• 0 Flash/ROM wait states (MTCRA=2208H)
• RC oscillator and Sub oscillator stopped
Main Run
Main Run mode current ICCMAIN with the following settings:
• fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 4MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• 1 Flash/ROM wait states (MTCRA=0239H)
• PLL, RC oscillator and Sub oscillator stopped
RC Run 2M
RC Run mode current ICCRCH with the following settings:
• RC oscillator set to 2MHz (CKFCR:RCFS = 1)
• fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 2MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• 1 Flash/ROM wait states (MTCRA=0239H)
• PLL, Main oscillator and Sub oscillator stopped
RC Run 100k
RC Run mode current ICCRCL with the following settings:
• RC oscillator set to 100kHz (CKFCR:RCFS = 0)
• fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 100kHz
• Regulator in Low Power Mode A (SMCR:LPMS = 1)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• 1 Flash/ROM wait states (MTCRA=0239H)
• PLL, Main oscillator and Sub oscillator stopped
DS07-13807-2E
109
MB96370 Series
Mode name
Details
Sub Run
Sub Run mode current ICCSUB with the following settings:
• fCLKS1 = fCLKS2 = fCLKB = fCLKP1 = fCLKP2 = 32kHz
• Regulator in Low Power Mode A (by hardware)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• 1 Flash/ROM wait states (MTCRA=0239H)
• PLL, RC oscillator and Main oscillator stopped
PLL Sleep 40
PLL Sleep mode current ICCSPLL with the following settings:
• fCLKS1 = fCLKS2 = 80MHz
• fCLKP1 = 40MHz
• fCLKP2 = 20MHz
• Regulator in High Power Mode
• Core voltage at 1.9V (VRCR:HPM[1:0] = 11B)
• RC oscillator and Sub oscillator stopped
PLL Sleep 24
PLL Sleep mode current ICCSPLL with the following settings:
• fCLKS1 = fCLKS2 = 48MHz
• fCLKP1 = fCLKP2 = 24MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• RC oscillator and Sub oscillator stopped
Main Sleep
Main Sleep mode current ICCSMAIN with the following settings:
• fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 4MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• PLL, RC oscillator and Sub oscillator stopped
RC Sleep 2M
RC Sleep mode current ICCSRCH with the following settings:
• RC oscillator set to 2MHz (CKFCR:RCFS = 1)
• fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 2MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• PLL, Main oscillator and Sub oscillator stopped
RC Sleep 100k
RC Sleep mode current ICCSRCL with the following settings:
• RC oscillator set to 100kHz (CKFCR:RCFS = 0)
• fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 100kHz
• Regulator in Low Power Mode A (SMCR:LPMSS = 1)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• PLL, Main oscillator and Sub oscillator stopped
Sub Sleep
Sub Sleep mode current ICCSSUB with the following settings:
• fCLKS1 = fCLKS2 = fCLKP1 = fCLKP2 = 32kHz
• Regulator in Low Power Mode A (by hardware)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• PLL, RC oscillator and Main oscillator stopped
PLL Timer 40
PLL Timer mode current ICCTPLL with the following settings:
• fCLKS1 = fCLKS2 = 40MHz
• Regulator in High Power Mode
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B)
• RC oscillator and Sub oscillator stopped
110
DS07-13807-2E
MB96370 Series
Mode name
Details
Main Timer
Main Timer mode current ICCTMAIN with the following settings:
• fCLKS1 = fCLKS2 = 4MHz
• Regulator in Low Power Mode A (SMCR:LPMSS = 1)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• PLL, RC oscillator and Sub oscillator stopped
RC Timer 2M
RC Timer mode current ICCTRCH with the following settings:
• RC oscillator set to 2MHz (CKFCR:RCFS = 1)
• fCLKS1 = fCLKS2 = 2MHz
• Regulator in Low Power Mode A (SMCR:LPMSS = 1)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• PLL, Main oscillator and Sub oscillator stopped
RC Timer 100k
RC Timer mode current ICCTRCL with the following settings:
• RC oscillator set to 100kHz (CKFCR:RCFS = 0)
• fCLKS1 = fCLKS2 = 100kHz
• Regulator in Low Power Mode A (SMCR:LPMSS = 1)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• PLL, Main oscillator and Sub oscillator stopped
Sub Timer
Sub Timer mode current ICCTSUB with the following settings:
• fCLKS1 = fCLKS2 = 32kHz
• Regulator in Low Power Mode A (by hardware)
• Core voltage at 1.8V (VRCR:LPMA[2:0] = 110B)
• PLL, RC oscillator and Main oscillator stopped
Stop 1.8V
Stop mode current ICCH with the following settings:
• Regulator in Low Power Mode B (by hardware)
• Core voltage at 1.8V (VRCR:LPMB[2:0] = 110B)
Stop 1.2V
Stop mode current ICCH with the following settings:
• Regulator in Low Power Mode B (by hardware)
• Core voltage at 1.2V (VRCR:LPMB[2:0] = 000B)
Note: The internal clock frequencies shown for the different operating modes define the upper bound of the operating
frequencies.
DS07-13807-2E
111
MB96370 Series
MB96375 PLL Run and Sleep mode currents
40.000
30.000
PLL Run 40
Icc[mA]
20 000
20.000
PLL Run 24
PLL Sleep 40
10.000
PLL Sleep 24
0.000
-60
-40
-20
0
20
40
60
80
100
120
100
120
Ta [˚C]
MB96375 operation modes with medium currents
5.000
4.000
Icc[m
mA]
3.000
Main Run
2.000
Main Sleep
RC Run 2M
1.000
PLL Timer 40
RC Sleep 2M
0.000
-60
-40
-20
0
20
40
60
80
Ta [˚C]
112
DS07-13807-2E
MB96370 Series
MB96375 Low power mode currents
1.0000
0.1000
Main Timer
Icc[m
mA]
RC Timer 2M
RC Run 100k
RC
CS
Sleep 100k
Sub Run
Sub Sleep
Sub Timer
RC Timer 100k
0.0100
Stop 1.8V
Stop 1.2V
0.0010
-60
60
-40
40
-20
20
0
20
40
60
80
100
120
100
120
Ta [˚C]
MB96F378/F379 PLL Run and Sleep mode currents
PLL Run 40
40
PLL Run 24
Icc[mA]
30
20
PLL Sleep 40
10
PLL Sleep 24
0
-60
-40
-20
0
20
40
60
80
Ta [˚C]
DS07-13807-2E
113
MB96370 Series
MB96F378/F379 operation modes with medium currents
5
Main Run
4
Icc[m
mA]
3
RC Run 2M
2
PLL Timer 40
Main Sleep
1
RC Sleep 2M
0
60
-60
-40
40
-20
20
0
20
40
60
80
100
120
80
100
120
Ta [˚C]
MB96F378/F379 Low power mode currents
1
0.1
RC Run 100k
Main Timer
Sub Run
Icc[mA]
RC Timer 2M
Sub Sleep
RC Sleep 100k
Sub Timer
0.01
RC Timer 100k
Stop 1.8V
Stop 1.2V
0.001
-60
-40
-20
0
20
40
60
Ta [˚C]
114
DS07-13807-2E
MB96370 Series
2. Frequency dependency of power supply currents in PLL Run mode
The following diagrams show the current consumption of samples with typical wafer process parameters in PLL
Run mode at different frequencies and Flash timing settings.
Measurement conditions:
• VCC = AVCC = 5.0V
• Ta = 25˚C
• fCLKS1 = fCLKB or fCLKS1 = 2*fCLKB as described in diagram
• fCLKS2 = fCLKS1
• fCLKP1 = fCLKB
• fCLKP2 = fCLKB/2
• Core voltage at 1.8V (VRCR:HPM[1:0] = 10B) or 1.9V (VRCR:HPM[1:0] = 11B) as described in diagram
• Main clock = 4MHz external clock
• Flash memory timing settings:
• MTCRA=2128H/2208H (0 Flash/ROM wait states, fCLKS1 = 2*fCLKB)
• MTCRA=0239H/2129H (1 Flash/ROM wait state, fCLKS1 = fCLKB)
• MTCRA=4C09H/6B09H (1 Flash/ROM wait state, fCLKS1 = 2*fCLKB)
• MTCRA=233AH (2 Flash/ROM wait states, fCLKS1 = fCLKB)
• Average Flash access rate (number of read accesses to the Flash per CLKB clock cycle, no buffer hit):
• 0 Flash/ROM wait states: 0.5
• 1 Flash/ROM wait states: 0.33
• 2 Flash/ROM wait states: 0.25
MB96375 PLL Run mode currents
40
: Specified in "DC characteristics"
35
30
1 wait state
(CLKS1=2*CLKB, 1.9V)*3
ICCPLL (mA)
25
1 wait state
(CLKS1=2*CLKB, 1.8V)
20
0 wait states
(CLKS1=2*CLKB, 1.8V)*1
2 wait states
(CLKS1=CLKB, 1.9V)*3
15
2 wait states
(CLKS1=CLKB, 1.8V)
10
1 wait state
(CLKS1=CLKB, 1.8V)*2
5
0
0
4
8
12
16
20
24
28
32
36
40
CLKB/CLKP1 (MHz)
DS07-13807-2E
115
MB96370 Series
MB96F378/F379 PLL Run mode currents
45
1 Flash wait state
(CLKS1=2*CLKB, 1.9V)*3
40
1 Flash wait state
(CLKS1=2*CLKB, 1.8V)
35
30
ICCP
PLL (mA)
2 Flash wait states
(CLKS1=CLKB, 1.9V)*3
25
0 Flash wait states
(CLKS1=2 CLKB, 1
(CLKS1=2*CLKB
1.8V)
8V)*1
1
2 Flash wait states
(CLKS1=CLKB, 1.8V)
20
15
1 Flash wait state
(CLKS1=CLKB, 1.8V)*2
10
: Specified in "DC characteristics"
5
0
0
4
8
12
16
20
24
28
32
36
40
CLKB/CLKP1 (MH
(MHz))
*1:
The setting of 0 Flash/ROM wait state, CLKS1=2*CLKB and 1.8V can be set until CLKB=25MHz
The setting of 0 Flash/ROM wait state, CLKS1=2*CLKB and 1.9V can be set until CLKB=28MHz
*2:
The setting of 1 Flash/ROM wait state, CLKS1=CLKB and 1.8V can be set until CLKB=30MHz
The setting of 1 Flash/ROM wait state, CLKS1=CLKB and 1.9V can be set until CLKB=32MHz
*3:
Please refer to AC Characteristics of Internal Clock timing for frequency limits
116
DS07-13807-2E
MB96370 Series
■ ORDERING INFORMATION
Part number
Subclock
Package*
MB96375RSAPMC-GSE2
No
MB96375RWAPMC-GSE2
Yes
144 Pin Plastic LQFP
FPT-144P-M08
MB96375RSAPMC1-GSE2
Flash/ROM
ROM (160KB)
No
MB96375RWAPMC1-GSE2
Yes
MB96F378HSBPMC-GSE2
No
MB96F378HWBPMC-GSE2
Yes
MB96F378HSBPMC1-GSE2
Flash A (544KB),
Flash B (32KB)
No
MB96F378HWBPMC1-GSE2
Yes
MB96F379RSBPMC-GSE2
No
MB96F379RWBPMC-GSE2
Yes
MB96F379RSBPMC1-GSE2
Flash A (544KB),
Flash B (288kB)
MB96F379RWBPMC1-GSE2
MB96V300CRB-ES
(for evaluation)
No
Yes
Emulated by ext. RAM
Yes
144 Pin Plastic LQFP
FPT-144P-M12
144 Pin Plastic LQFP
FPT-144P-M08
144 Pin Plastic LQFP
FPT-144P-M12
144 Pin Plastic LQFP
FPT-144P-M08
144 Pin Plastic LQFP
FPT-144P-M12
416 pin Plastic BGA
(BGA-416P-M02)
*
: For details about package, please refer to “■PACKAGE DIMENSION”.
Note: This datasheet is also valid for the following outdated devices.
MB96F378TSA, MB96F378HSA, MB96F378TWA, MB96F378HWA
MB96F379YSA, MB96F379RSA, MB96F379YWA, MB96F379RWA
DS07-13807-2E
117
MB96370 Series
■ PACKAGE DIMENSION
144-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
20.0 × 20.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
1.20 g
Code
(Reference)
P-LFQFP144-20×20-0.50
(FPT-144P-M08)
144-pin plastic LQFP
(FPT-144P-M08)
Note 1) *:Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
22.00±0.20(.866±.008)SQ
* 20.00±0.10(.787±.004)SQ
108
0.145±0.055
(.006±.002)
73
109
72
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
0°~8°
INDEX
144
37
"A"
LEAD No.
1
36
0.50(.020)
C
0.22±0.05
(.009±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
(Mounting height)
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
M
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F144019S-c-4-8
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
118
DS07-13807-2E
MB96370 Series
144-pin plastic LQFP
Lead pitch
0.40 mm
Package width ×
package length
16.0 × 16.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.88 g
Code
(Reference)
P-LFQFP144-16×16-0.40
(FPT-144P-M12)
144-pin plastic LQFP
(FPT-144P-M12)
Note 1) * : These dimensions include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
18.00±0.20(.709±.008)SQ
+0.40
+.016
*16.00 –0.10 .630 –.004 SQ
73
108
72
109
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
.059
+.008
–.004
(Mounting height)
INDEX
0~8°
37
144
LEAD No.
1
0.60±0.15
(.024±.006)
36
0.40(.016)
C
"A"
0.18±0.035
.007±.001
+0.05
0.07(.003)
M
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F144024S-c-3-5
0.145 –0.03
0.10±0.05
(.004±.002)
(Stand off)
0.25(.010)
+.002
.006 –.001
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-13807-2E
119
MB96370 Series
■ MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
Front Page
-
Change Result
Added Mask device informations.
6, 7
■ PRODUCT LINEUP
Added Mask device informations.
15
■ I/O CIRCUIT TYPE
Error correction in Remarks of Type B.
19
■ I/O CIRCUIT TYPE
Added Remarks in Type N.
21
■ RAMSTART/END AND
EXTERNAL BUS END ADDRESSES
Added Mask device informations.
23
■ USER ROM MEMORY MAP FOR
MASK ROM DEVICES
Added new subject for Mask device.
63
■ HANDLING DEVICES
Item “6. Power supply pins (Vcc/Vss)”: Added note for bypass capacitor.
64
■ HANDLING DEVICES
Added new item “14. Clock modulator”.
■ ELECTRICAL
CHARACTERISTICS
Added output current spec for 2mA and 3mA outputs.
Added Permitted Power dissipation spec for Mask device.
68
2. Recommended Operating
Conditions
Smoothing capacitor: changed proper value for Typ.
70
3. DC characteristics
Added Port drive condition in Remarks.
72 to 77
3. DC characteristics
• Added Mask device specification (target values).
• Added Mode Conditions.
• Changed proper value for flash devices.
78
4. AC Characteristics
Added RC clock stabilization time.
Added remark in “PLL Phase Jitter”
79
When using an oscillation circuit
Added Figure of Amplitude.
80
Internal Clock timing
Added Mask device informations.
99
I2C Timing
Added new parameter “Output fall time” ,”Capacitive load
for each bus line” and “Pulse width of spikes”.
100
5. Analog Digital Converter
Deleted double expression for IAIN and corrected value.
103
Accuracy and setting of the A/D
Converter sampling time
Prepared a more accurate estimation for sampling time by
Rext, Cext, CIN, RADC and CADC
106
7. Low Voltage Detector
characteristics
• Added specification for Mask device (Value *2).
• Added note description for inclination of the power-supply
voltage.
108
8. FLASH memory program/erase
characteristics
Erase time specification now includes “write time prior to internal erase”. Separate specification for large and small
Sectors.
65, 66
120
DS07-13807-2E
MB96370 Series
Page
109 to 116
117
Section
Change Result
■ EXAMPLE CHARACTERISTICS
Added new section.
■ ORDERING INFORMATION
• Added the part numbers of mask devices.
• Deleted the following part numbers:
MB96F378TSA, MB96F378HSA,
MB96F378TWA, MB96F378HWA,
MB96F379YSA, MB96F379RSA,
MB96F379YWA, MB96F379RWA
DS07-13807-2E
121
MB96370 Series
■ REVISION HISTORY
Revision
Date
Prelim 1
2007-11-27
Creation
Prelim 2
2007-12-19
Add TTG3/TTG7 in pin assignment
Some IO circuit drawings have been modified.
Modification of the memory map and IO map
Block diagram includes now the relocated pins
Main Flash becomes Flash memory A, Satellite Flash becomes Flash memory B
Prelim 3
2008-04-14
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
122
Modification
Added note for devices under development
Maximum CPU frequency corrected to 40MHz
Product lineup: Product options added, reload timer for PPG added
Block diagram: Flash B added, CKOT*_R added, IN*_R added
Pin assignment: CKOT0_R added
Pin function description corrected (all existing pin types included)
Pin circuit types: Description improved
Memory map: common 16FX memory map included
External bus and RAM start/end addressed specified more precise
Flash sector addresses: Start/end addresses corrected
Serial programming interface: Note about handshaking pins improved
I/O map newly generated (naming style update)
Permitted power dissipation specified
Ordering information updated
Disclaimer added
ICC spec corrected (wrong conditions were specified). However specification
is still preliminary, especially regarding the leakage current.
DS07-13807-2E
MB96370 Series
Revision
Date
Modification
Prelim 4
2009-01-09
• Format adjusted to official Fujitsu Microelectronics datasheet standard (mainly style changes and official notes and disclaimer added)
• specified AD converter channel offset to 4LSB
• package code of MB96V300 corrected in ordering information
• Internal LCD divider resistance value corrected: Typ 35kOhm -> 40kOhm,
Max 50kOhm -> 65kOhm
• Added voltage condition to pull-up resistance and LCD divide resistance spec
• Lineup: Term “Data Flash” replaced by “independent 32KB Flash”
• Ordering information: column “Satellite Flash” replaced by new column “Flash/
ROM”, column “Remarks” removed
• Official package dimension drawing with additional notes added
• Empty pages removed
• DC values adjusted after evaluation (higher Run and Sleep mode currents,
smaller standby current at high temp)
• Alarm comparator: Power supply current max values increased, comparison
time reduced, mode transition time and power-up stabilization time newly
added
• Handling devices: Notes added about Serial communication and about using
ceramic resonators.
• Feature list and AC Characteristics: 16MHz maximum frequency is valid for
crystal oscillators. For resonators, maximum frequency depends on Q-factor
• AC characteristics: PLL phase skew spec added, CLKVCO min=64MHz
• VOL3 spec improved: spec valid for 3mA load for full Vcc range
• C-Pin cap spec updated: 4.7uF-10uF capacitor with tolerance permitted
DS07-13807-2E
123
MB96370 Series
Revision
Date
Modification
Prelim 5
2010-06-14
• AD converter IAIN spec improved: 1uA valid up to 105deg, 1.2uA above 105deg
• Note added that PLL phase jitter spec does not include jitter coming from
Main clock
• Alarm comparator: Maximum power-up stabilization time increased to 10ms
• Note added in DC characteristics how to select driving strength of ports
• I2C AC spec updated: tof, Cb and tSP spec added, wrong footnotes and
Condition removed
• I/O Circuit type: Note added for type “N” (slew rate control according to I2C
spec)
• Updated Power Supply current spec in Run/Sleep/Timer/Stop modes (new
spec items in PLL Run/Sleep mode, small adjustment of most other values)
• Prepared Example characteristics
• Package dimension: Added the following sentence under the figure: “Please
confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/”
• AD converter: Impact of input pin capacitance and external capacitance added to formula for calculation of the sampling time
• Added specification of RC clock stabilization time
• Ordering information updated: MB96F378/F379**A -> MB96F378/F379**B
• Feature description I2C: ‘8-bit addressing’ corrected to ‘7-bit addressing’
• Feature description PPG: ‘Reload timer overflow as clock input’ corrected to
‘Reload timer underflow as clock input’
• Company name updated on the cover page: Fujitsu Microelectronics Limited
-> Fujitsu Semiconductor Limited
124
DS07-13807-2E
MB96370 Series
MEMO
DS07-13807-2E
125
MB96370 Series
MEMO
126
DS07-13807-2E
MB96370 Series
MEMO
DS07-13807-2E
127
MB96370 Series
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://sg.fujitsu.com/semiconductor/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District,
Shanghai 201204, China
Tel : +86-21-6146-3688 Fax : +86-21-6146-3660
http://cn.fujitsu.com/fss/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://www.fujitsu.com/kr/fsk/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
2/F, Green 18 Building, Hong Kong Science Park,
Shatin, N.T., Hong Kong
Tel : +852-2736-3232 Fax : +852-2314-4207
http://cn.fujitsu.com/fsp/
All Rights Reserved.
FUJITSU SEMICONDUCTOR LIMITED, its subsidiaries and affiliates (collectively, "FUJITSU SEMICONDUCTOR") reserves
the right to make changes to the information contained in this document without notice. Please contact your FUJITSU
SEMICONDUCTOR sales representatives before order of FUJITSU SEMICONDUCTOR device.
Information contained in this document, such as descriptions of function and application circuit examples is presented solely for
reference to examples of operations and uses of FUJITSU SEMICONDUCTOR device. FUJITSU SEMICONDUCTOR disclaims
any and all warranties of any kind, whether express or implied, related to such information, including, without limitation, quality,
accuracy, performance, proper operation of the device or non-infringement. If you develop equipment or product incorporating the
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manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high levels of safety is secured,
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Any semiconductor devices fail or malfunction with some probability. You are responsible for providing adequate designs and
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