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FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
CM44-10105-6E
F2MC-16LX
16-BIT MICROCONTROLLER
MB90590 Series
HARDWARE MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90590 Series
HARDWARE MANUAL
The information for microcontroller supports is shown in the following homepage.
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page
"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU MICROELECTRONICS LIMITED
PREFACE
■ Objectives and Intended Reader
Thank you very much for your continued patronage of Fujitsu semiconductor products.
The MB90590 series has been developed as a general-purpose version of the F2MC-16LX
family, which is an original 16-bit single-chip microcontroller compatible with the Application
Specific IC (ASIC).
This manual explains the functions and operation of the MB90590 series for designers who
actually use the MB90590 series to design products. Read this manual first.
■ Trademark
F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
Other system and product names in this manual are trademarks of respective companies or
organizations.
■ Structure of This Manual
CHAPTER 1 "OVERVIEW"
The MB90590 series is a family member of the F2MC-16LX microcontrollers.
CHAPTER 2 "CPU"
This chapter explains the CPU.
CHAPTER 3 "INTERRUPTS"
This chapter explains the interrupt functions and operations.
CHAPTER 4 "DELAYED INTERRUPTS"
This chapter explains the functions and operations of the delayed interrupt.
CHAPTER 5 "CLOCK AND RESET"
This chapter explains the functions and operations of clocks and resets.
CHAPTER 6 "LOW-POWER CONTROL CIRCUIT"
This chapter explains the functions and operations of the low-power control circuits.
CHAPTER 7 "MEMORY ACCESS MODES"
This chapter explains the functions and operations of the memory access modes.
CHAPTER 8 "I/O PORTS"
This chapter explains the functions and operations of the I/O ports.
CHAPTER 9 "TIMEBASE TIMER"
This chapter explains the functions and operations of the timebase timer.
CHAPTER 10 "WATCH-DOG TIMER"
This chapter explains the functions and operations of the watch-dog timer.
CHAPTER 11 "16-BIT I/O TIMER"
This chapter explains the functions and operations of the 16-bit I/O timer.
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CHAPTER 12 "16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)"
This chapter explains the functions and operations of the 16-bit reload timer (with the event
count function).
CHAPTER 13 "WATCH TIMER"
This chapter explains the functions and operations of the Watch Timer.
CHAPTER 14 "8/16-BIT PPG"
This chapter explains the 8/16-bit PPG and explains its functions.
CHAPTER 15 "DTP/EXTERNAL INTERRUPTS"
This chapter explains the functions and operations of the DTP/external interrupts.
CHAPTER 16 "A/D CONVERTER"
This chapter explains the functions and operations of the A/D converter.
CHAPTER 17 "UART0"
This chapter explains the UART0 functions and operations.
CHAPTER 18 "SERIAL I/O"
This chapter explains the functions and operations of the serial I/O.
CHAPTER 19 "CAN CONTROLLER"
This chapter explains the functions and operations of the CAN controller.
CHAPTER 20 "STEPPING MOTOR CONTROLLER"
This chapter explains the functions and operations of the stepping motor controller.
CHAPTER 21 "SOUND GENERATOR"
This chapter explains the functions and operations of the sound generator.
CHAPTER 22 "ADDRESS MATCH DETECTION FUNCTION"
This chapter explains the address match detection function and operation.
CHAPTER 23 "ROM MIRRORING MODULE"
This chapter explains the ROM mirroring module.
CHAPTER 24 "2M/3M-BIT FLASH MEMORY"
This chapter explains the functions and operation of the 2M/3M-bit flash memory.
CHAPTER 25 "EXAMPLES OF MB90F594A/MB90F594G/MB90F591A/MB90F591G
SERIAL PROGRAMMING CONNECTION"
This chapter provides examples of F2MC-16LX MB90F594A/MB90F594G/MB90F591A/
MB90F591G serial programming connection.
APPENDIX
The appendixes provide I/O maps, instructions, and other information.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©2006-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Product Overview ............................................................................................................................... 2
Features .............................................................................................................................................. 3
Block Diagram .................................................................................................................................... 5
Package Dimensions .......................................................................................................................... 6
Pin Assignment ................................................................................................................................... 7
Pin Functions ...................................................................................................................................... 8
Input-Output Circuits ......................................................................................................................... 12
Handling Device ................................................................................................................................ 14
CHAPTER 2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.8
2.9
2.10
2.11
CPU ............................................................................................................ 19
Outline of CPU ..................................................................................................................................
Memory Space ..................................................................................................................................
Memory Space Map ..........................................................................................................................
Linear Addressing .............................................................................................................................
Bank Addressing ...............................................................................................................................
Multi-byte Data in Memory Space .....................................................................................................
Registers ...........................................................................................................................................
Accumulator (A) ...........................................................................................................................
User Stack Pointer (USP) and System Stack Pointer (SSP) .......................................................
Processor Status (PS) .................................................................................................................
Program Counter (PC) .................................................................................................................
Register Bank ...................................................................................................................................
Prefix Codes .....................................................................................................................................
Interrupt Disable Instructions ............................................................................................................
Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions ................................................
CHAPTER 3
3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.6
3.7
3.7.1
3.7.2
3.8
3.9
OVERVIEW ................................................................................................... 1
20
21
22
23
24
26
27
30
31
32
35
36
38
40
41
INTERRUPTS ............................................................................................. 43
Outline of Interrupts ..........................................................................................................................
Interrupt Vector .................................................................................................................................
Interrupt Control Registers (ICR) ......................................................................................................
Interrupt Flow ....................................................................................................................................
Hardware Interrupts ..........................................................................................................................
Hardware Interrupt Operation ......................................................................................................
Occurrence and Release of Hardware Interrupt ..........................................................................
Multiple interrupts ........................................................................................................................
Software Interrupts ...........................................................................................................................
Extended Intelligent I/O Service (EI2OS) ..........................................................................................
Extended Intelligent I/O Service Descriptor (ISD) .......................................................................
EI2OS Status Register (ISCS) .....................................................................................................
Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS) ..............
Exceptions ........................................................................................................................................
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47
48
51
53
54
55
57
58
60
62
64
66
68
CHAPTER 4
4.1
4.2
4.3
Outline of Delayed Interrupt Module ................................................................................................. 70
Delayed Interrupt Register ................................................................................................................ 71
Delayed Interrupt Operation ............................................................................................................. 72
CHAPTER 5
5.1
5.2
5.3
LOW-POWER CONTROL CIRCUIT .......................................................... 81
Outline of Low-Power Control Circuit ................................................................................................
Registers ...........................................................................................................................................
Low-Power Mode Control Register (LPMCR) ..............................................................................
Clock Selection Register (CKSCR) .............................................................................................
Low-Power Mode Operation .............................................................................................................
Sleep Mode .................................................................................................................................
Watch Mode ................................................................................................................................
Stop Mode ...................................................................................................................................
Hardware Standby Mode .............................................................................................................
Intermittent CPU Operation ..............................................................................................................
Switching Machine Clocks ................................................................................................................
Status Transition of Clock Selection .................................................................................................
CHAPTER 7
7.1
7.2
7.3
CLOCK AND RESET ................................................................................. 73
Clock Generator ................................................................................................................................ 74
Reset Cause Occurrence ................................................................................................................. 75
Reset Causes ................................................................................................................................... 78
CHAPTER 6
6.1
6.2
6.2.1
6.2.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.4
6.5
6.6
DELAYED INTERRUPT ............................................................................. 69
MEMORY ACCESS MODES .................................................................... 101
Outline of Memory Access Modes .................................................................................................. 102
Mode Pins ....................................................................................................................................... 103
Mode Data ...................................................................................................................................... 104
CHAPTER 8
I/O PORTS ................................................................................................ 107
8.1
I/O Ports ..........................................................................................................................................
8.2
I/O Port Registers ...........................................................................................................................
8.2.1
Port Data Register (PDR0 to PDR9) .........................................................................................
8.2.2
Port Direction Register (DDR0 to DDR9) ..................................................................................
8.2.3
Analog Input Enable Register (ADER) ......................................................................................
CHAPTER 9
9.1
9.2
9.3
82
84
85
87
89
91
92
94
96
97
98
99
108
109
110
111
112
TIMEBASE TIMER ................................................................................... 113
Outline of Timebase Timer ............................................................................................................. 114
Timebase Timer Control Register (TBTC) ...................................................................................... 115
Operations of Timebase Timer ....................................................................................................... 117
CHAPTER 10 WATCH-DOG TIMER ............................................................................... 119
10.1
10.2
Outline of Watch-Dog Timer ........................................................................................................... 120
Watch-Dog Timer Operation ........................................................................................................... 123
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CHAPTER 11 16-BIT I/O TIMER ..................................................................................... 125
11.1 Outline of 16-Bit I/O Timer ..............................................................................................................
11.2 16-Bit I/O Timer Registers ..............................................................................................................
11.3 16-Bit Free-running Timer ...............................................................................................................
11.3.1 Timer Counter Data Register (TCDT) ........................................................................................
11.3.2 Timer Counter Control Status Register (TCCS) ........................................................................
11.3.3 16-bit Free-running Timer Operation .........................................................................................
11.4 Output Compare .............................................................................................................................
11.4.1 Output Compare Register ..........................................................................................................
11.4.2 Control Status Register of Output Compare (OCS0/1) ..............................................................
11.4.3 16-bit Output Compare Operation .............................................................................................
11.5 Input Capture ..................................................................................................................................
11.5.1 Input Capture Register Details ..................................................................................................
11.5.2 16-bit Input Capture Operation ..................................................................................................
126
128
129
130
131
134
136
137
138
141
144
146
148
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) ................ 151
12.1 Outline of 16-Bit Reload Timer (with Event Count Function) ..........................................................
12.2 16-Bit Reload Timer ........................................................................................................................
12.2.1 Timer Control Status Register (TMCSR) ...................................................................................
12.2.2 Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR) ...................
12.3 Internal Clock and External Clock Operations of 16-Bit Reload Timer ...........................................
12.4 Underflow Operation of 16-Bit Reload Timer ..................................................................................
12.5 Output Pin Functions of 16-Bit Reload Timer .................................................................................
12.6 Counter Operation State .................................................................................................................
152
154
155
158
159
161
162
163
CHAPTER 13 WATCH TIMER ........................................................................................ 165
13.1 Outline of Watch Timer ...................................................................................................................
13.2 Watch Timer Registers ...................................................................................................................
13.2.1 Timer Control Register (WTCR) ................................................................................................
13.2.2 Sub-second Registers (WTBR) .................................................................................................
13.2.3 Second/Minute/Hour Registers (WTSR/WTMR/WTHR) ............................................................
166
167
169
171
172
CHAPTER 14 8/16-BIT PPG ........................................................................................... 173
14.1 Outline of 8/16-bit PPG ...................................................................................................................
14.2 Block Diagram of 8/16-bit PPG .......................................................................................................
14.3 8/16-bit PPG Registers ...................................................................................................................
14.3.1 PPG0 Operation Mode Control Register (PPGC0) ....................................................................
14.3.2 PPG1 Operation Mode Control Register (PPGC1) ....................................................................
14.3.3 PPG0/PPG1 Clock Selection Register (PPG01) .......................................................................
14.3.4 Reload Register (PRLL/PRLH) ..................................................................................................
14.4 Operations of 8/16-bit PPG .............................................................................................................
14.5 Selecting a Count Clock for 8/16-bit PPG .......................................................................................
14.6 Controlling Pin Output of 8/16-bit PPG Pulses ...............................................................................
14.7 8/16-bit PPG Interrupts ...................................................................................................................
14.8 Initial Values of 8/16-bit PPG Hardware .........................................................................................
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174
175
177
178
180
182
184
185
187
188
189
190
CHAPTER 15 DTP/EXTERNAL INTERRUPTS .............................................................. 193
15.1
15.2
15.3
15.4
15.5
Outline of DTP/External Interrupts ..................................................................................................
DTP/External Interrupt Registers ....................................................................................................
Operations of DTP/External Interrupts ............................................................................................
Switching between External Interrupt and DTP Requests ..............................................................
Notes on Using DTP/External Interrupts .........................................................................................
194
196
198
200
201
CHAPTER 16 A/D Converter .......................................................................................... 203
16.1 Features of A/D Converter ..............................................................................................................
16.2 Block Diagram of A/D Converter .....................................................................................................
16.3 A/D Converter Registers .................................................................................................................
16.3.1 A/D Control Status Register 0 (ADCS0) ....................................................................................
16.3.2 A/D Control Status Register 1 (ADCS1) ....................................................................................
16.3.3 A/D Data Registers 0/1 (ADCR1 and ADCR0) ..........................................................................
16.4 Operations of A/D Converter ..........................................................................................................
16.5 Conversion Using EI2OS ................................................................................................................
16.5.1 Starting EI2OS in Single Mode ..................................................................................................
16.5.2 Starting EI2OS in Continuous Mode ..........................................................................................
16.5.3 Starting EI2OS in Stop Mode .....................................................................................................
16.6 Conversion Data Protection ............................................................................................................
204
206
207
208
211
214
216
218
219
221
223
225
CHAPTER 17 UART0 ...................................................................................................... 227
17.1 Feature of UART0 ...........................................................................................................................
17.2 UART0 Block Diagram ....................................................................................................................
17.3 UART0 Registers ............................................................................................................................
17.3.1 Serial Mode Control Register 0 (UMC0) ....................................................................................
17.3.2 Serial Status Register 0 (USR0) ................................................................................................
17.3.3 Serial Input Data Register 0 (UIDR0) and Serial Output Data Register 0 (UODR0) .................
17.3.4 Rate and Data Register 0 (URD0) .............................................................................................
17.4 UART0 Operation ...........................................................................................................................
17.5 Baud Rate .......................................................................................................................................
17.6 Internal and External Clock .............................................................................................................
17.7 Transfer Data Format .....................................................................................................................
17.8 Parity Bit .........................................................................................................................................
17.9 Interrupt Generation and Flag Set Timings .....................................................................................
17.9.1 Flag Set Timings for a Receive Operation (in Mode 0, Mode 1, or Mode 3) .............................
17.9.2 Flag Set Timings for a Receive Operation (in Mode 2) .............................................................
17.9.3 Flag Set Timings for a Transmit Operation ................................................................................
17.9.4 Status Flag During Transmit and Receive Operation ................................................................
17.10 UART0 Application Example ..........................................................................................................
228
229
230
231
233
235
236
238
239
242
243
244
245
246
247
248
249
250
CHAPTER 18 SERIAL I/O ............................................................................................... 253
18.1 Outline of Serial I/O ........................................................................................................................
18.2 Serial I/O Registers .........................................................................................................................
18.2.1 Serial Mode Control Status Register (SMCS) ...........................................................................
18.2.2 Serial Shift Data Register (SDR) ...............................................................................................
18.3 Serial I/O Prescaler (CDCR) ...........................................................................................................
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254
255
256
260
261
18.4 Serial I/O Operation ........................................................................................................................
18.4.1 Shift Clock .................................................................................................................................
18.4.2 Serial I/O Operation ...................................................................................................................
18.4.3 Shift Operation Start/Stop Timing ..............................................................................................
18.4.4 Interrupt Function of the Extended Serial I/O Interface .............................................................
18.5 Negative Clock Operation ...............................................................................................................
262
263
264
266
269
270
CHAPTER 19 CAN CONTROLLER ................................................................................ 271
19.1 Features of CAN Controller ............................................................................................................
19.2 Block Diagram of CAN Controller ...................................................................................................
19.3 List of Overall Control Registers .....................................................................................................
19.4 List of Message Buffers (ID Registers) ...........................................................................................
19.5 List of Message Buffers (DLC Registers and Data Registers) ........................................................
19.6 Classifying the CAN Controller Registers .......................................................................................
19.6.1 CAN Control Status Register (CSR) ..........................................................................................
19.6.2 Bus Operation Stop Bit (HALT = 1) ...........................................................................................
19.6.3 Last Event Indicator Register (LEIR) .........................................................................................
19.6.4 Receive and Transmit Error Counters (RTEC) ..........................................................................
19.6.5 Bit Timing Register (BTR) ..........................................................................................................
19.6.6 Message Buffer Valid Register (BVALR) ...................................................................................
19.6.7 IDE register (IDER) ....................................................................................................................
19.6.8 Transmission Request Register (TREQR) ................................................................................
19.6.9 Transmission RTR Register (TRTRR) .......................................................................................
19.6.10 Remote Frame Receiving Wait Register (RFWTR) ...................................................................
19.6.11 Transmission Cancel Register (TCANR) ...................................................................................
19.6.12 Transmission Complete Register (TCR) ....................................................................................
19.6.13 Transmission Interrupt Enable Register (TIER) .........................................................................
19.6.14 Reception Complete Register (RCR) ........................................................................................
19.6.15 Remote Request Receiving Register (RRTRR) ........................................................................
19.6.16 Receive Overrun Register (ROVRR) .........................................................................................
19.6.17 Reception Interrupt Enable Register (RIER) .............................................................................
19.6.18 Acceptance Mask Select Register (AMSR) ...............................................................................
19.6.19 Acceptance Mask Registers 0/1 (AMR0/AMR1) ........................................................................
19.6.20 Message Buffers ........................................................................................................................
19.6.21 ID Register x (x = 0 to 15) (IDRx) ..............................................................................................
19.6.22 DLC Register x (x = 0 to 15) (DLCRx) .......................................................................................
19.6.23 Data Register x (x = 0 to 15) (DTRx) .........................................................................................
19.7 Transmission of CAN Controller .....................................................................................................
19.8 Reception of CAN Controller ..........................................................................................................
19.9 Reception Flowchart of CAN Controller ..........................................................................................
19.10 How to Use the CAN Controller ......................................................................................................
19.11 Procedure for Transmission by Message Buffer (x) .......................................................................
19.12 Procedure for Reception by Message Buffer (x) .............................................................................
19.13 Setting Configuration of Multi-level Message Buffer .......................................................................
19.14 Precautions when Using CAN Controller ........................................................................................
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273
274
276
279
283
284
287
289
291
292
295
296
297
298
299
300
301
302
303
304
305
306
307
309
311
312
314
315
317
319
322
323
325
327
329
332
CHAPTER 20 STEPPING MOTOR CONTROLLER ....................................................... 335
20.1 Outline of Stepping Motor Controller ..............................................................................................
20.2 Stepping Motor Controller Registers ...............................................................................................
20.2.1 PWM Control 0 register (PWC0) ...............................................................................................
20.2.2 PWM1&2 Compare Registers (PWC10/PWC20) ......................................................................
20.2.3 PWM1&2 Select Registers (PWS10/PWS20) ...........................................................................
20.3 Notes on Using the Stepping Motor Controller ...............................................................................
336
337
338
339
340
342
CHAPTER 21 SOUND GENERATOR ............................................................................. 343
21.1 Outline of Sound Generator ............................................................................................................
21.2 Sound Generator Registers ............................................................................................................
21.2.1 Sound Control Register (SGCR) ...............................................................................................
21.2.2 Frequency Data register (SGFR) ...............................................................................................
21.2.3 Amplitude Data Register (SGAR) ..............................................................................................
21.2.4 Decrement Grade Register (SGDR) ..........................................................................................
21.2.5 Tone Count Register (SGTR) ....................................................................................................
344
345
346
348
349
350
351
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ......................................... 353
22.1
22.2
22.3
22.4
Outline of the Address Match Detection Function ..........................................................................
Registers of the Address Match Detection Function .......................................................................
Operation of the Address Match Detection Function ......................................................................
Example of the Address Match Detection Function ........................................................................
354
355
357
358
CHAPTER 23 ROM MIRRORING MODULE ................................................................... 361
23.1
23.2
Outline of ROM Mirroring Module ................................................................................................... 362
ROM Mirroring Register (ROMM) ................................................................................................... 363
CHAPTER 24 2M/3M-BIT FLASH MEMORY .................................................................. 365
24.1 Overview of 2M/3M-bit Flash Memory ............................................................................................
24.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory ..........
24.3 Write/Erase Modes .........................................................................................................................
24.4 Flash Memory Control Status Register (FMCS) .............................................................................
24.5 Starting the Flash Memory Automatic Algorithm ............................................................................
24.6 Confirming the Automatic Algorithm Execution State .....................................................................
24.6.1 Data Polling Flag (DQ7) ............................................................................................................
24.6.2 Toggle Bit Flag (DQ6) ................................................................................................................
24.6.3 Timing Limit Exceeded Flag (DQ5) ...........................................................................................
24.6.4 Sector Erase Timer Flag (DQ3) .................................................................................................
24.6.5 Toggle Bit-2 Flag (DQ2) ............................................................................................................
24.7 Detailed Explanation of Writing to and Erasing Flash Memory .......................................................
24.7.1 Setting the Read/Reset State ....................................................................................................
24.7.2 Writing Data ...............................................................................................................................
24.7.3 Erasing All Data (Erasing Chips) ...............................................................................................
24.7.4 Erasing Optional Data (Erasing Sectors) ...................................................................................
24.7.5 Suspending Sector Erase ..........................................................................................................
24.7.6 Restarting Sector Erase ............................................................................................................
24.8 Notes on using 2M-bit Flash Memory .............................................................................................
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366
368
370
372
374
376
378
380
381
382
383
385
386
387
389
390
392
393
394
24.9 Reset Vector Address in Flash Memory ......................................................................................... 395
24.10 Example of Programming 2M-bit Flash Memory ............................................................................ 396
CHAPTER 25 EXAMPLES OF MB90F594A/MB90F594G/MB90F591A/MB90F591G
SERIAL PROGRAMMING CONNECTION .............................................. 401
25.1
25.2
25.3
25.4
25.5
Basic Configuration of MB90F594A/MB90F594G/MB90F591A/MB90F591G
Serial Programming Connection .....................................................................................................
Example of Serial Programming Connection (User Power Supply Used) ......................................
Example of Serial Programming Connection (Power Supplied from the Programmer) ..................
Example of Minimum Connection to the Flash Microcomputer Programmer
(User Power Supply Used) .............................................................................................................
Example of Minimum Connection to the Flash Microcomputer Programmer
(Power Supplied from the Programmer) .........................................................................................
402
406
408
410
412
APPENDIX ......................................................................................................................... 415
APPENDIX A I/O Maps ...........................................................................................................................
APPENDIX B Instructions ...........................................................................................................................
B.1 Instruction Types ............................................................................................................................
B.2 Addressing .....................................................................................................................................
B.3 Direct Addressing ...........................................................................................................................
B.4 Indirect Addressing ........................................................................................................................
B.5 Execution Cycle Count ...................................................................................................................
B.6 Effective address field ....................................................................................................................
B.7 How to Read the Instruction List ....................................................................................................
B.8 F2MC-16LX Instruction List ............................................................................................................
B.9 Instruction Map ...............................................................................................................................
APPENDIX C Timing Diagrams in Flash Memory Mode .........................................................................
APPENDIX D List of MB90590 Series Interrupt Vectors .........................................................................
416
428
429
430
432
438
446
449
450
453
467
489
494
INDEX................................................................................................................................... 499
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Main changes in this edition
Page
428 to 488
Changes (For details, refer to main body.)
Changed the entire part of "APPENDIX B Instructions"
The vertical lines marked in the left side of the page show the changes.
Reference: Main changes (Rev.4 → Rev.5)
Page
Changes (For details, refer to main body.)
−
Register name is changed.
(PWM control 0 register (PWMC0) → PWM control 0 register (PWC0))
3
Watch Timer in Table 1.2-1 MB90590 Features (1/2) is changed.
(The description of Facility to correct oscillation deviation is deleted.)
14
■ Handling the Device is changed.
(❍ Stabilization of supply voltage is added.)
16
❍ Crystal Oscillator Circuit is changed.
(Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. is
added.)
24
❍ User stack bank register (USB)/system stack bank register (SSB) is changed.
(USP → USB)
(SSP → SSB)
38
❍ I/O access instructions is changed.
58
■ Software Interrupts is changed.
(• Sets I in the PS register. → • Sets "0" to PS: I flag.)
59
Figure 3.6-1 Occurrence and Release of Software Interrupt is changed.
(➂ is added.)
76
MCS of Table 5.2-2 Registers not Initialized by Reset Input is changed.
(N → Y)
82
■ Outline of Lower-power Control Circuit is changed.
(The PLL clock multiplication factor can be selected from 1, 2, 3, and 4 by setting the CS1 and CS0 bits. is
deleted.)
Note: is changed.
(If the mode is switched to another clock mode or low-power-consumption mode before completion of
switching, the mode may not be switched. is added.)
90
Table 6.3-2 List of Instructions Used for Transition to Low-power Mode is changed.
98
Note: is changed.
(If the mode is switched to another clock mode or low-power-consumption mode before completion of
switching, the mode may not be switched. is added.)
100
Note: is changed.
(If the mode is switched to another clock mode or low-power-consumption mode before completion of
switching, the mode may not be switched. is added.)
xiii
Reference: Main changes (Rev.4 → Rev.5)
Page
Changes (For details, refer to main body.)
175
Overview of 14.2 Block Diagram of 8/16-bit PPG is changed.
(8/16-bit → 8-bit)
Figure 14.2-1 8-bit PPG ch.0 Block Diagram is changed.
(Figure is changed)
(PPG output signal of ch.0 is not connected with an external terminal. is added.)
176
Figure 14.2-2 8-bit PPG ch.1 Block Diagram is changed.
(Figure is changed.)
Figure 14.2-3 Relation among PPG module, Unit number, and External pin is added.
178
[bit 5] PE00 is changed to reserved bit.
190
❍ Pulse outputs is changed.
❍ Interrupt requests is changed.
201
❍ External interrupt/DTP operation procedure is changed.
(1. Set the general-purpose I/O port that is shared with the pin for the external interrupt input as the input
port. is added.)
202
Figure 15.5-1 Clearing the Interrupt Request Flag Bit (EIRR:ER) upon Level Set and
Figure 15.5-2 Interrupt Cause and Interrupt Request to the Interrupt Controller while Interrupts are Enabled
are changed.
209
Notes: of [bit 5 to bit 3] ANS2, ANS1, and ANS0 (Analog start channel set) in ■ A/D Control Status Register 0 (ADCS0) is changed.
(However, until A/D conversion starts, the previous conversion channel will be read even if these bits have
already been set to the new value. is added.)
210
Notes: is changed.
(• A/D conversion mode select bit (MD1, MD0) and A/D conversion end channel select bit (ANE2, ANE1,
ANE0) should not be set by the read-modify-write instruction after setting the A/D conversion start channel
select bit (ANS2, ANS1, ANS0) to the start channel. The last conversion channel is read from ANS2, ANS1,
and ANS0 bit until starting A/D conversion.
Therefore, if the MD1, MD0 bits and the ANE2, ANE1, and ANE0 bits is set by the read-modify- write
instruction after setting the ANS2, ANS1, and ANS0 bits to the start channel, the value of the ANE2, ANE1,
and ANE0 bits may be re-written to a different value. is added.)
213
[bit 9] STRT (Start): is changed.
(The byte/word command reads "1".
The read-modify-write instructions read "0". is added.)
243
■ Transfer Data Format is changed.
(The transfer data format of SIN0 and SOUT0 is the same as shown in Figure 17.7-1 "Transfer Data Format".
→ The transfer data format of SIN0 and SOT0 is the same as shown in Figure 17.7-1 "Transfer Data Format".)
286
[bit 0] HALT: Bus operation stop bit is changed.
287
Notes in ■ Conditions for Canceling Bus Operation Stop (HALT = 0) is changed.
(• When write "0" to HALT during the node status is Bus Off, ensure that "1" is written to this bit after confirming HALT is "1". is added.)
342
20.3 Notes on Using the Stepping Motor Controller is added.
371
Table 24.3-1 Flash Memory Control Signals is changed.
(RY/BY → RY/BY)
xiv
Reference: Main changes (Rev.4 → Rev.5)
Page
Changes (For details, refer to main body.)
381
❍ Write/chip sector erase operation is changed.
(In rare cases normal termination may be seen as with the case where "1" can be written. is added.)
391
Figure 24.7-2 Example of the Flash Memory Sector Erase Procedure is changed.
392
■ Suspending Erasing of Flash Memory Sectors is changed.
(Before issuing a sector erase suspend command, wait for 20µs after issuing the sector erase command or
sector erase resume command. is added.)
394
❍ Input of a hardware reset (RST) is changed.
(50ns → 500ns)
(A hardware reset during erasing may make the sector being erased unusable. → The erasing sector might
become using prohibited by hardware-reset or turning off the power under erasing.)
❍ Applying VID is changed.
(Applying VID required for the sector protect operation should always be started and terminated when the
supply voltage is on. → During power-ON, please start and end the VID supply for the sector protect operation.)
402
Table 25.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming is changed.
(− → Input a "L" level to P00 and "H" level to P01.)
406, 408
Figure 25.2-1 Example of Serial Programming Connection for MB90F594A/MB90F594G/ MB90F591A/
MB90F591G (User Power Supply Used) and Figure 25.3-1 Example of Serial Programming Connection for
MB90F594A/MB90F594G/MB90F591A/MB90F591G (Power Supplied from the Programmer) are changed.
(The figure of resistance is added to the right side of (5).)
416 to 421
Table A-1 I/O Map is changed.
422 to 426
Table A-2 I/O Map (19XX Address) is changed.
465
Table B.8-17 6 Accumulator Operation Instructions (Byte, Word) is changed.
(SWAPW / XCHW A, T → SWAPW )
xv
xvi
CHAPTER 1
OVERVIEW
The MB90590 series is a family member of the F2MC-16LX microcontrollers.
1.1 Product Overview
1.2 Features
1.3 Block Diagram
1.5 Pin Assignment
1.4 Package Dimensions
1.6 Pin Functions
1.7 Input-Output Circuits
1.8 Handling Device
1
CHAPTER 1 OVERVIEW
1.1
Product Overview
Table 1.1-1 provides a quick outlook of the MB90590 series.
■ Product Overview
Table 1.1-1 Product Overview
Features
MB90V590G
MB90F594A/F594G/F591A/
F591G
MB90594G/591/591G
Product type
Evaluation sample
Flash memory version
Mask ROM version
CPU
F2MC-16LX CPU
System clock
On-chip PLL clock multiplier (x1, x2, x3, x4, 1/2 when PLL stops)
Minimum instruction execution time: 62.5 ns (4 MHz osc. PLL x4)
ROM/Flash
memory
External
RAM
8 Kbytes
6 Kbytes/8 Kbytes
Package
PGA-256
QFP100
None
-
Emulator- specific
power supply *
Boot-block
Flash memory 256K/384K
bytes with Hard-wired reset
vector
Mask ROM 256K/384K bytes
*: It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.
Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details.
Note:
With the product with G-suffix at the end of part numbers, functionality the CAN controller is
enhanced. Please refer to the description of the Bit Timing Register in the CAN chapter.
2
CHAPTER 1 OVERVIEW
1.2
Features
Table 1.2-1 lists the features of the MB90590 series.
■ Features
Table 1.2-1 MB90590 Features (1/2)
Function
Feature
UART
(3 channels)
Full duplex double buffer
Supports asynchronous/synchronous (with start/stop bit) transfer
Baud rate: 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous)
500K/1M/2M bps (synchronous) at System clock = 16 MHz
Serial I/O
Transfer can be started from MSB or LSB
Supports positive-edge and negative-edge clock synchronization
Baud rate: 31.25K/62.5K/125K/500K/1M/2M bps at System clock = 16 MHz
A/D
Converter
10 or 8-bit resolution
8 input channels
Conversion time: 26.3 µs (per one channel)
16-bit Reload Timer
(2 channels)
Watch Timer
16-bit
I/O Timer
16-bit
Output Compare
(6 channels)
16-bit
Input Capture
(6 channels)
8/16-bit
Programmable Pulse
Generator
(6 channels)
Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = System clock frequency)
Supports External Event Count function
Directly operates with the oscillation clock
Facility to correct oscillation deviation
Read/Write accessible Second/Minute/Hour registers
Signals interrupts
Signals an interrupt when overflow
Supports Timer Clear when a match with Output Compare (Channel 0)
Operation clock frequency: fsys/22, fsys/24,fsys/26, fsys/28 (fsys = System clock
frequency)
Signals an interrupt when a match with 16-bit I/O Timer
Six 16-bit compare registers
A pair of compare registers can be used to generate an output signal
Rising edge, falling edge or rising & falling edge sensitive
Six 16-bit Capture registers
Signals an interrupt upon external event
Supports 8-bit and 16-bit operation modes
8-bit reload counter: 2 × 6 units
8-bit reload register for "L" pulse width: 2 × 6 units
8-bit reload register for "H" pulse width: 2 × 6 units
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler plus 8-bit reload counter
6 output pins
Operation clock frequency: fsys, fsys/21, fsys/22, fsys/23, fsys/24 or
128 µ[email protected] = 4 MHz
(fsys = System clock frequency, fosc = Oscillation clock frequency)
3
CHAPTER 1 OVERVIEW
Table 1.2-1 MB90590 Features (2/2)
Function
Feature
CAN Interface
(2 channels)
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible acceptance filter
Full bit compare / Full bit mask / Two partial bit masks
Supports up to 1M bps
Stepping Motor
Controller
(4 channels)
Four high current outputs for each channel
Synchronized two 8-bit PWM’s for each channel
Succeeds to MB89940 design resource
External
Interrupt
(8 channels)
Sound Generator
I/O Ports
Flash Memory
Either edge detection or level detection can be specified.
The MB90V590G supports only four of the eight input channels.
8-bit PWM signal is mixed with tone frequency from 8-bit reload counter
PWM frequency: 62.5k, 31.2k, 15.6k, 7.8kHz at System clock = 16 MHz
Tone frequency: PWM frequency / 2 / (reload value + 1)
Virtually all external pins can be used as general purpose I/O
All push-pull outputs and schmitt trigger inputs
Bit-wise programmable as input/output or peripheral signal
Supports automatic programming, Embedded AlgorithmTM *
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Hard-wired reset vector available in order to point to a fixed boot sector in Flash
Memory
Boot block configuration
Erase can be performed on each block
*: Embedded Algorithm is a trademark of Advanced Micro Devices Inc.
4
CHAPTER 1 OVERVIEW
1.3
Block Diagram
Figure 1.3-1 shows a block diagram of the MB90590 series.
■ Block Diagram
Figure 1.3-1 Block Diagram
X0,X1
RST
Clock
Controller
F2MC-16LX
CPU
HST
RAM 6K/8K
I/O Timer
ROM/Flash
Input
Capture
6channels
IN[5:0]
Output
Compare
6channels
OUT[5:0]
8/16-bit
PPG
6channels
PPG[5:0]
256K/384K
Prescaler x3
SOT[2:0]
SCK[2:0]
UART
3channels
SIN[2:0]
SOT3
SCK3
Serial I/O
SIN3
F2MC-16LX Bus
Prescaler
CAN
2channels
RX[1:0]
TX[1:0]
PWM1M[3:0]
PWM1P[3:0]
AVCC
SMC
4channels
AVSS
PWM2M[3:0]
PWM2P[3:0]
AN[7:0]
10-bit ADC
DVCC
AVRH
8channels
DVSS
AVRL
ADTG
TIN
TOT/WOT
16-bit Reload
Timer
2channels
External
Interrupt
8channels
Sound
Generator
INT[7:0]
SGO
SGA
Watch
Timer
5
CHAPTER 1 OVERVIEW
1.4
Package Dimensions
Figure 1.4-1 shows the package dimensions of the MB90590 series.
Note that the dimensions shown below are reference dimensions. For formal
dimensions of each package, contact us.
■ Package Dimensions
Figure 1.4-1 Package Dimensions
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP100-14×20-0.65
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
51
80
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
"A"
C
6
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8˚
31
2002 FUJITSU LIMITED F100008S-c-5-5
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
P16/SGO
P17/SGA
P15/TX1
C
P00/IN0
P01/IN1
P02/IN2
P03/IN3
P04/IN4
P05/IN5
P06/OUT0
P07/OUT1
P10/OUT2
P11/OUT3
P12/OUT4
P13/OUT5
P14/RX1
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
QFP-100
Package code (mold)
FPT-100P-M06
P50/PPG0
P51/PPG1
P52/PPG2
Vss
X0
X1
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
P95/INT3
P94/INT2
P93/INT1
RST
P92/INT0
P91/RX0
P90/TX0
DVss
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
DVcc
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVss
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
DVcc
P73/PWM2M0
P72/PWM2P0
P71/PWM1M0
P70/PWM1P0
DVss
HST
MD2
1.5
P20
P21
P22
P23
P24/INT4
P25/INT5
P26/INT6
P27/INT7
P30
P31
Vss
P32
P33
P34/SOT0
P35/SCK0
P36/SIN0
P37/SIN1
P40/SCK1
P41/SOT1
P42/SOT2
P43/SCK2
P44/SIN2
Vcc
P45/SIN3
P46/SCK3
P47/SOT3
CHAPTER 1 OVERVIEW
Pin Assignment
Figure 1.5-1 shows the pin assignments for the MB90590 series.
■ Pin Assignment
Figure 1.5-1 Pin Assignment
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
MD1
MD0
P57/TOT/WOT
P56/TIN
P67/AN7
P66/AN6
P65/AN5
P64/AN4
Vss
P63/AN3
P62/AN2
P61/AN1
P60/AN0
AVss
AVRL
AVRH
AVcc
P55/PPG5/ADTG
P54/PPG4
P53/PPG3
7
CHAPTER 1 OVERVIEW
1.6
Pin Functions
Table 1.6-1 describes the pin functions of the MB90590 series.
■ Pin Functions
Table 1.6-1 Pin Functions (1/4)
No.
Pin name
82
X0
Circuit type
Function
Oscillation input
A
83
X1
Oscillation output
77
RST
B
Reset input
52
HST
C
Hardware standby input
P00 to P05
85 to 90
General purpose I/O
D
IN0 to IN5
Inputs for the Input Captures
P06 to P07
P10 to P13
General purpose I/O
91 to 96
D
OUT0 to
OUT5
P14
97
General purpose I/O
D
RX1
RX input for CAN Interface 1
P15
General purpose I/O
TX1
TX output for CAN Interface 1.
To enable the signal output, the corresponding bit of the Port
Direction register should be set to "1".
P16
General purpose I/O
98
D
SGO
SGO output for the Sound Generator.
To enable the signal output, the corresponding bit of the Port
Direction register should be set to "1".
P17
General purpose I/O
99
D
100
D
SGA output for the Sound Generator.
To enable the signal output, the corresponding bit of the Port
Direction register should be set to "1".
D
General purpose I/O
SGA
1 to 4
P20 to P23
P24 to P27
5 to 8
General purpose I/O
D
INT4 to INT7
8
Outputs for the Output Compares.
To enable the signal outputs, the corresponding bits of the
Port Direction registers should be set to "1".
External interrupt input for INT4 to INT7
These pin functions are not supported by MB90V590G.
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Functions (2/4)
No.
Pin name
Circuit type
9, 10
P30, P31
D
General purpose I/O
12, 13
P32, P33
D
General purpose I/O
P34
14
General purpose I/O
D
SOT0
P35
15
D
P36
SCK input/output for UART 0
To enable the signal output, the corresponding bit of the Port
Direction register should be set to "1".
General purpose I/O
D
SIN0
SIN input for UART 0
P37
17
General purpose I/O
D
SIN1
SIN input for UART 1
P40
18
General purpose I/O
D
SCK1
SCK input/output for UART 1
P41
19
General purpose I/O
D
SOT1
SOT output for UART 1
P42
20
General purpose I/O
D
SOT2
SOT output for UART 2
P43
21
General purpose I/O
D
SCK2
SCK input/output for UART 2
P44
22
General purpose I/O
D
SIN2
SIN input for UART 2
P45
24
General purpose I/O
D
SIN3
SIN input for the Serial I/O
P46
25
General purpose I/O
D
SCK3
SCK input/output for the Serial I/O
P47
26
General purpose I/O
D
SOT3
SOT output for the Serial I/O
P50 to P55
28 to 33
SOT output for UART 0
To enable the signal output, the corresponding bit of the Port
Direction register should be set to "1".
General purpose I/O
SCK0
16
Function
PPG0 to
PPG5,
ADTG
General purpose I/O
D
Outputs for the Programmable Pulse Generators.
Pin number 33 is also shared with ADTG input for the
external trigger of the A/D Converter.
9
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Functions (3/4)
No.
Pin name
Circuit type
P60 to P63
38 to 41
General purpose I/O
E
AN0 to AN3
Inputs for the A/D Converter
P64 to P67
43 to 46
General purpose I/O
E
AN4 to AN7
Inputs for the A/D Converter
P56
47
General purpose I/O
D
TIN
TIN input for the 16-bit Reload Timer
P57
General purpose I/O
TOT/WOT
TOT output for the 16-bit Reload Timer and WOT output for
the Watch Timer. Only one of three output enable flags in
these peripheral blocks can be set at a time. Otherwise the
output signal has no meaning.
P70 to P73
General purpose I/O
48
54 to 57
D
PWM1P0
PWM1M0
PWM2P0
PWM2M0
F
P74 to P77
59 to 62
PWM1P1
PWM1M1
PWM2P1
PWM2M1
PWM1P2
PWM1M2
PWM2P2
PWM2M2
F
PWM1P3
PWM1M3
PWM2P3
PWM2M3
F
F
Output for Stepping Motor Controller channel 3.
General purpose I/O
D
TX0
TX output for CAN Interface 0
P91
75
General purpose I/O
D
RX0
RX input for CAN Interface 0
P92
76
General purpose I/O
D
INT0
10
Output for Stepping Motor Controller channel 2.
General purpose I/O
P90
74
Output for Stepping Motor Controller channel 1.
General purpose I/O
P84 to P87
69 to 72
Output for Stepping Motor Controller channel 0.
General purpose I/O
P80 to P83
64 to 67
Function
External interrupt input for INT0
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Functions (4/4)
No.
Pin name
Circuit type
P93
78
Function
General purpose I/O
D
INT1
External interrupt input for INT1
P94
79
General purpose I/O
D
INT2
External interrupt input for INT2
P95
80
General purpose I/O
D
INT3
External interrupt input for INT3
58,
68
DVCC
-
53,
63,
73
DVSS
-
Dedicated ground pins for the high current output buffers
(Pin No. 54 to 72)
34
AVCC
-
Dedicated power supply pin for the A/D Converter
37
AVSS
-
Dedicated ground pin for the A/D Converter
35
AVRH
-
Upper reference voltage input for the A/D Converter
36
AVRL
-
Lower reference voltage input for the A/D Converter
49,
50
MD0,
MD1
C
Test mode inputs. These pins should be connected to VCC.
51
MD2
G
Test mode input. This pin should be connected to VSS.
27
C
-
External capacitor pin. A capacitor of 0.1µF should be
connected to this pin and VSS.
23,
84
VCC
-
11,
42,
81
VSS
-
Dedicated power supply pins for the high current output
buffers (Pin No. 54 to 72)
Power supply pins
Ground pins
11
CHAPTER 1 OVERVIEW
1.7
Input-Output Circuits
Table 1.7-1 lists the input-output circuits.
■ Input-Output Circuits
Table 1.7-1 Input-output Circuits (1/2)
Circuit Type
Circuit
Remarks
A
•
Oscillation feedback resistor:
1 MΩ approx.
•
•
Hysteresis input with pull-up Resistor
Pull-up resistor: 50 kΩ approx.
•
Hysteresis input
•
•
CMOS output
Hysteresis input
X1
Oscillation feedback resistor
Clock pulse
input
X0
Hard, soft standby control
B
R (pull-up)
HYS input
R
C
HYS input
R
D
P-ch
N-ch
R
12
HYS input
CHAPTER 1 OVERVIEW
Table 1.7-1 Input-output Circuits (2/2)
Circuit Type
Circuit
Remarks
E
•
•
•
CMOS output
Hysteresis input
Analog input
•
•
CMOS high current output
Hysteresis input
•
•
•
Hysteresis input with pull-down resistor
Pull-down resistor: 50 kΩ approx.
Flash memory version does not have pulldown resistor.
P-ch
N-ch
P-ch
Analog input
N-ch
R
HYS input
F
High current
R
HYS input
G
R
HYS input
R (pull-down)
13
CHAPTER 1 OVERVIEW
1.8
Handling Device
Special care is required for the following when handling the device:
• Preventing latch-up
• Stabilization of supply voltage
• Treatment of unused pins
• Using external clock
• Power supply pins (VCC/VSS)
•
•
•
•
•
•
•
•
•
•
•
Pull-up/Pull-down resistors
Crystal Oscillator Circuit
Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Connection of Unused Pins of A/D Converter
N.C. Pin
Precautions at power on
Initialization
Indeterminate outputs from ports 0 and 1
Using the "DIV A, Ri" and "DIVW A, RWi" instructions
Using REALOS
Notes on during operation of PLL clock mode
■ Handling the Device
❍ Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions:
•
A voltage higher than VCC or lower than VSS is applied to an input or output pin.
•
A voltage higher than the rated voltage is applied between VCC and VSS.
•
The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the
device.
❍ Stabilization of supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the
specified VCC supply voltage operating range. Therefore, the VCC supply voltage should be
stabilized.
For reference, the supply voltage should be controlled so that VCC ripple variations (peak-topeak values) at commercial frequencies (50 to 60Hz) fall below 10% of the standard VCC supply
voltage and the coefficient of fluctuation dose not exceed 0.1 V/ms at instantaneous power
switching.
14
CHAPTER 1 OVERVIEW
❍ Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent
damage of the device. Therefore they must be pulled up or pulled down through resistors. In this
case those resistors should be more than 2 kΩ.
Unused I/O pins should be set to the output state and can be left open, or the input state with
the above described connection.
❍ Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
Figure 1.8-1 is a diagram of how to use external clock.
Figure 1.8-1 Using External Clock
MB90590 Series
X0
Open
X1
❍ Power supply pins (VCC/VSS)
Ensure that all VCC-level power supply pins are at the same potential. In addition, ensure the
same for all VSS-level power supply pins. (See the Figure 1.8-2.) If there are more than one VCC
or VSS system, the device may operate incorrectly even within the guaranteed operating range.
Figure 1.8-2 Power Supply Pins (VCC/VSS)
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90590
Series
Vcc
Vss
Vss
Vcc
❍ Pull-up/Pull-down resistors
The MB90590 series does not support internal pull-up/pull-down resistors option. Use external
components where needed.
15
CHAPTER 1 OVERVIEW
❍ Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to
provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic
resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit
not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins
with a ground area for stabilizing the operation.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this
device.
❍ Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter, D/A converter power supply (AVCC, AVRH, AVRL,
DVCC, DVSS) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this
case, make sure that the voltage not exceed AVRH or AVCC (turning on/off the analog and
digital power supplies simultaneously is acceptable).
❍ Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.
❍ N.C. Pin
The N.C. (internally connected) pin must be opened for use.
❍ Precautions at power on
To prevent a malfunction of the internal step-down circuit, the voltage rise time at power-on
should be 50 µs or more (between 0.2 V and 2.7 V).
❍ Initialization
In the device, there are internal registers which is initialized only by a power-on reset. To
initialize these registers turning on the power again.
16
CHAPTER 1 OVERVIEW
❍ Indeterminate outputs from ports 0 and 1 (Except MB90F594G, MB90F591G, and
MB90591G)
During oscillation stabilization wait time of step-down circuit (during a power-on reset) after the
power is turned on, the outputs from ports 0 and 1 become following state.
•
If RST pin is "H", the outputs become indeterminate.
•
If RST pin is "L", the outputs become high-impedance *.
*: Other than P06, P07, P10 to P13, P16, and P17. (The output of these pins become
indeterminate only.)
Pay attention to the port output timing shown as follows:
Figure 1.8-3 Indeterminate Output from Ports 0 and 1 (RST pin is "H")
Oscillation stabilization wait time
Power-on reset
Vcc (Power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal
*1: Power-on reset time: Period of "clock frequency
Period of indeterminated
217 " (Clock frequency of 16 MHz: approx. 8.19 ms)
*2: Oscillation stabilization wait time: Period of "clock frequency
218 " (Clock frequency of 16 MHz: approx. 16.38ms)
Figure 1.8-4 High-Impedance Output from Ports 0 and 1 (RST Pin is "L")
Oscillation stabilization wait time
Power-on reset
Vcc (Power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal
High-impedance
*1: Power-on reset time: Period of "clock frequency
2
17
" (Clock frequency of 16 MHz: approx. 8.19 ms)
*2: Oscillation stabilization wait time: Period of "clock frequency
218 " (Clock frequency of 16 MHz: approx. 16.38ms)
17
CHAPTER 1 OVERVIEW
❍ Using the "DIV A, Ri" and "DIVW A, RWi" instructions
Before using the multiplication and division instructions using signs ("DIV A, Ri" and "DIVW A,
RWi"), set "00H" in the corresponding bank registers (DTB, ADB, USB, and SSB). If the
corresponding bank registers (DTB, ADB, USB, and SSB) are set to other than "00H", the
remainder in the execution results of the instruction is not stored in the register of the instruction
operand. For more information, see Section "2.11 Precautions for Use of "DIV A, Ri" and
"DIVW A, RWi" Instructions".
❍ Using REALOS
The use of EI2OS is not possible with the REALOS real time operating system.
❍ Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the selfoscillating circuit in PLL even when there is no external oscillator or external clock input is
stopped. Performance of this operation, however, cannot be guaranteed.
18
CHAPTER 2
CPU
This chapter explains the CPU.
2.1 Outline of CPU
2.2 Memory Space
2.3 Memory Space Map
2.4 Linear Addressing
2.5 Bank Addressing
2.6 Multi-byte Data in Memory Space
2.7 Registers
2.8 Register Bank
2.9 Prefix Codes
2.10 Interrupt Disable Instructions
2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions
19
CHAPTER 2 CPU
2.1
Outline of CPU
The F2MC-16LX CPU core is a 16-bit CPU designed for applications that require highspeed real-time processing, such as home-use or vehicle-mounted electronic
appliances. The F2MC-16LX instruction set is designed for controller applications, and
is capable of high-speed and highly efficient control processing.
■ Outline of CPU
In addition to 16-bit data, the F2MC-16LX CPU core can process 32-bit data by using an internal
32-bit accumulator. (32-bit data can be processed with some instructions.) Up to 16 Mbytes of
memory space (expandable) can be used, which can be accessed by either the linear pointer or
bank method. The instruction system, based on the F2MC-8L A-T architecture, has been
reinforced by adding instructions compatible with high-level languages, expanding addressing
modes, reinforcing multiplication and division instructions, and enhancing bit processing. The
features of the F2MC-16LX CPU are explained below.
❍ Minimum instruction execution time
62.5 ns (at 4-MHz oscillation, 4 times clock multiplication)
❍ Maximum memory space
16 Mbytes, accessed in linear or bank mode
❍ Instruction set optimized for controller applications
•
Rich data types:
Bit, byte, word, long word
•
Extended addressing modes: 23 types
•
High-precision operation (32-bit length) based on 32-bit accumulator
❍ Powerful interrupt functions
Eight priority levels (programmable)
❍ CPU-independent automatic transfer
Up to 16 channels of the extended intelligent I/O service
❍ Instruction set compatible with high-level language (C language)/multitasking
System stack pointer/instruction set symmetry/barrel-shift instructions
❍ Improved execution speed
4-byte queue
20
CHAPTER 2 CPU
2.2
Memory Space
An F2MC-16LX CPU has a 16 Mbyte memory space. All data program input and output
managed by the F2MC-16LX CPU are located in this 16 Mbyte memory space. The CPU
accesses the resources by indicating their addresses using a 24-bit address bus.
■ Outline of CPU Memory Space
Figure 2.2-1 shows a sample relationship between F2MC-16LX system and memory map.
Figure 2.2-1 Sample Relationship between F2MC-16LX System and Memory Map
FFFFFFH
Program
FF8000H
Data
810000H
Interrupt
800000H
F2MC-16LX
CPU
Program area
Data area
0000C0H
Peripheral
circuits
[Device]
Generalpurpose ports
0000B0H
Interrupt controller
Peripheral circuits
000020H
General-purpose ports
000000H
■ Address Generation Types
The F2MC-16LX has the following two addressing:
❍ Linear addressing
An entire 24-bit address is specified by an instruction.
❍ Bank addressing
The eight high-order bits of an address are specified by an appropriate bank register, and the
remaining 16 low-order bits are specified by an instruction.
21
CHAPTER 2 CPU
2.3
Memory Space Map
The memory space of the MB90590 series is shown in Figure 2.3-1.
■ Memory Space Map
The high-order portion of bank "00" gives the image of the FF bank ROM to make the small
model of the C compiler effective. Since the low-order 16 bits are the same, the table in ROM
can be referenced without using the far specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in FF bank exceeds 48 Kbytes, and its entire image cannot be shown in bank
"00".
The image between FF4000H and FFFFFFH is visible in bank "00", while the image between
FF0000H and FF3FFFH is visible only in FF bank.
Figure 2.3-1 Memory Space Map
MB90V590G
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
MB90F594A/MB90F594G/MB90594G
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
00FFFFH
004000H
ROM (FA bank)
ROM (Image of
FF bank)
00FFFFH
004000H
ROM (Image of
FF bank)
00FFFFH
004000H
002100H
0020FFH
001900H
0018FFH
Peripheral
001900H
0018FFH
RAM 6 Kbytes
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
ROM (Image of
FF bank)
0000BFH
000000H
RAM 2 Kbytes
Peripheral
RAM 6 Kbytes
000100H
000100H
Peripheral
ROM (FD bank)
001FFFH
001FFFH
Peripheral
ROM (FE bank)
0028FFH
RAM 2 Kbytes
000100H
22
FD0000H
FCFFFFH
F90000H
RAM 6 Kbytes
0000BFH
000000H
FE0000H
FDFFFFH
ROM (FF bank)
FA0000H
F9FFFFH
ROM (F9 bank)
001FFFH
001900H
0018FFH
FF0000H
FEFFFFH
FB0000H
FAFFFFH
0028FFH
002100H
0020FFH
FFFFFFH
FC0000H
FBFFFFH
ROM (FB bank)
FA0000H
F9FFFFH
F90000H
MB90F591A/MB90591
MB90F591G/MB90591G
Peripheral
0000BFH
000000H
Peripheral
CHAPTER 2 CPU
2.4
Linear Addressing
There are two types of linear addressing as follows:
• 24-bit operand specification:
Directly specifies a 24-bit address using
operands.
• 32-bit register indirect specification: Indirectly quote the 24 low-order bits of a 32-bit
general-purpose register value as the address.
■ 24-bit Operand Specification
Figure 2.4-1 shows an example of 24-bit operand specification. Figure 2.4-2 shows an example
of 32-bit register indirect specification.
Figure 2.4-1 Example of Linear Addressing (24-bit Register Operand Specification)
JMPP 123456 H
Old program counter
+ program bank
17
17452D H
452D
JMPP 123456 H
123456 H
New program counter
+ program bank
12
Next instruction
3456
Figure 2.4-2 Example of Linear Addressing (32-bit Register Indirect Specification)
MOV A, @RL1+7
Old AL
090700 H
XXXX
3A
+7
RL1
240906F9
(The high-order eight bits are ignored.)
New AL
003A
23
CHAPTER 2 CPU
2.5
Bank Addressing
In the bank addressing, the 16 Mbyte space is divided into 256 with 64 Kbyte banks.
The following five bank registers are used to specify the banks corresponding to each
space:
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional bank register (ADB)
■ Bank Addressing Types
❍ Program bank register (PCB)
The 64 Kbyte bank specified by the PCB is called a program (PC) space. The PC space
contains instruction codes, vector tables, and immediate value data, for example.
❍ Data bank register (DTB)
The 64 Kbyte bank specified by the DTB is called a data (DT) space. The DT space contains
readable/writable data, and control/data registers for internal and external resources.
❍ User stack bank register (USB)/system stack bank register (SSB)
The 64 Kbyte bank specified by the USB or SSB is called a stack (SP) space. The SP space is
accessed when a stack access occurs during a push/pop instruction or interrupt register saving.
The S flag in the condition code register determines which the stack space to be accessed.
24
CHAPTER 2 CPU
❍ Additional bank register (ADB)
The 64 Kbyte bank specified by the ADB is called an additional (AD) space. The AD space, for
example, contains the data that cannot fit into the DT space.
Table 2.5-1 lists the default spaces used in each addressing mode, which are pre-determined to
improve instruction coding efficiency. To use a non-default space for an addressing mode,
specify a prefix code corresponding to a bank before the instruction. This enables access to the
bank space corresponding to the specified prefix code.
After reset, the DTB, USB, SSB, and ADB are initialized to 00H. The PCB is initialized to a value
specified by the reset vector. After reset, the DT, SP, and AD spaces are allocated in bank 00H
(000000H to 00FFFFH), and the PC space is allocated in the bank specified by the reset vector.
Table 2.5-1 Default Space
Default space
Program space
Addressing mode
PC indirect, program access, branch
Data space
Addressing mode using @RW0, @RW1, @RW4, @RW5,
@A, addr16, and dir
Stack space
Addressing mode using PUSHW, POPW, @RW3, @RW7
Additional space
Addressing mode using @RW2, @RW6
Figure 2.5-1 is an example of a memory space divided into register banks.
Figure 2.5-1 Physical Addresses of Each Space
FFFFFF H
Program space
FF0000 H
FF H
:
PCB (Program bank register)
B3 H
: ADB (Additional bank register)
92 H
: USB (User stack bank register)
68 H
: DTB (Data bank register)
4B H
: SSB (System stack bank register)
B3FFFF H
Additional space
Physical address
B30000 H
92FFFF H
User stack space
920000 H
68FFFF H
680000 H
Data space
4BFFFF H
System stack space
4B0000 H
000000 H
25
CHAPTER 2 CPU
2.6
Multi-byte Data in Memory Space
Data is written to memory from the low-order addresses. Therefore, for a 32-bit data
item, the low-order 16 bits are transferred before the high-order 16 bits.
If a reset signal is input immediately after the low-order bits are written, the high-order
bits might not be written.
■ Multi-byte Data Allocation in Memory Space
Figure 2.6-1 is a diagram of multi-byte data configuration in memory. The low-order eight bits of
a data item are stored at address n, then address n+1, address n+2, address n+3, etc.
Figure 2.6-1 Sample Allocation of Multi-byte Data in Memory
MSB
H
LSB
01010101
11001100
11111111
00010100
01010101
11001100
11111111
Address n
00010100
L
■ Accessing Multi-byte Data
Fundamentally, accesses are made within a bank. For an instruction accessing a multi-byte
data item, address FFFFH is followed by address 0000H of the same bank. Figure 2.6-2 is an
example of an instruction accessing multi-byte data.
Figure 2.6-2 Execution of MOVW A, 080FFFFH
H
80FFFF H
AL before execution
??
AL after execution
23 H
??
01H
·
·
·
23 H
800000 H
L
26
01H
CHAPTER 2 CPU
2.7
Registers
The F2MC-16LX registers are largely classified into two types: special registers in the
CPU and general-purpose registers in memory. The special registers are dedicated
internal hardware of the CPU, and they have specific use defined by the CPU
architecture. The general-purpose registers share the CPU address space with RAM.
The general-purpose registers are the same as the special registers in that they can be
accessed without using an address. The applications of the general-purpose registers
can be specified by the user however, as is ordinary memory space.
■ Special Registers
The F2MC-16LX CPU core has the following 11 special registers:
•
Accumulator (A=AH:AL):
Two 16-bit accumulators (Can be used as a total 32-bit
accumulator.)
•
User stack pointer (USP):
16-bit pointer indicating the user stack area
•
System stack pointer (SSP):
16-bit pointer indicating the system stack area
•
Processor status (PS):
16-bit register indicating the system status
•
Program counter (PC):
16-bit register holding the address of the program
•
Program bank register (PCB):
8-bit register indicating the PC space
•
Data bank register (DTB):
8-bit register indicating the DT space
•
User stack bank register (USB):
8-bit register indicating the user stack space
•
System stack bank register (SSB): 8-bit register indicating the system stack space
•
Additional bank register (ADB):
8-bit register indicating the AD space
•
Direct page register (DPR):
8-bit register indicating a direct page
Figure 2.7-1 is a diagram of the special registers.
27
CHAPTER 2 CPU
Figure 2.7-1 Special Registers
AH
AL
Accumulator
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
DPR
Direct page register
PCB
Program bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8 bit
16 bit
32 bit
28
CHAPTER 2 CPU
■ General-Purpose Registers
The F2MC-16LX general-purpose registers are located from addresses 000180H to 00037FH
(maximum configuration) of main storage. The register bank pointer (RP) indicates which of the
above addresses are currently being used as a register bank. Each bank has the following three
types of registers. These registers are mutually dependent as described in Figure 2.7-2.
•
R0 to R7:
8-bit general-purpose register
•
RW0 to RW7: 16-bit general-purpose register
•
RL0 to RL3: 32-bit general-purpose register
Figure 2.7-2 General-purpose Registers
MSB
LSB
16 bit
000180H + RP × 10H
RW0
Low-order
RL0
First address of
general-purpose register
RW1
RW2
RL1
RW3
R1
R0
RW4
R3
R2
RW5
R5
R4
RW6
R7
R6
RW7
RL2
RL3
High-order
The relationship between the high-order and low-order bytes of a byte or word register is
expressed as follows:
RW (i+4) = R (i × 2+1) × 256+R (i × 2) [i=0 to 3]
The relationship between the high-order and low-order bytes of RLi and RW can be expressed
as follows:
RL (i) = RW (i × 2+1) × 65536+RW (i × 2) [i=0 to 3]
29
CHAPTER 2 CPU
2.7.1
Accumulator (A)
The accumulator (A) register consists of two 16-bit arithmetic operation registers (AH
and AL), and is used as a temporary storage for operation results and transfer data.
■ Accumulator (A)
The A register consists of two 16-bit arithmetic operation registers (AH and AL). The A register
is used as a temporary storage for operation results and transfer data. During 32-bit data
processing, AH and AL are used together. Only AL is used for word processing in 16-bit data
processing mode or for byte processing in 8-bit data processing mode (see Figure 2.7-3 and
Figure 2.7-4). The data stored in the A register can be operated upon with the data in memory
or registers (Ri, Rwi, or Rli). In the same manner as with the F2MC-8L, when a word or shorter
data item is transferred to AL, the previous data item in AL is automatically sent to AH (data
preservation function). The data preservation function and operation between AL and AH help
improve processing efficiency.
When a byte or shorter data item is transferred to AL, the data is sign-extended or zeroextended and stored as a 16-bit data item in AL. The data in AL can be handled either as word
or byte long.
When a byte-processing arithmetic operation instruction is executed on AL, the high-order eight
bits of AL before operation are ignored. The high-order eight bits of the operation result all
become zeroes.
The A register is not initialized by a reset. The A register holds an undefined value immediately
after a reset.
Figure 2.7-3 32-bit Data Transfer
MOVL A,@RW1+6
A before
execution
XXXX H
MSB
XXXX H
A6 H
DTB
An after
execution
8F74 H
A61540 H
8F H
74 H
A6153E H
2B H
52 H
15 H
38 H
+6
2B52 H
AH
LSB
RW1
AL
Figure 2.7-4 AL-AH Transfer
MSB
MOVW A,@RW1+6
A before
execution
XXXX H
1234 H
A6 H
DTB
An after
execution
30
1234 H
2B52 H
AH
AL
LSB
A61540 H
8F H
74 H
A6153E H
2B H
52 H
15 H
38 H
+6
RW1
CHAPTER 2 CPU
2.7.2
User Stack Pointer (USP) and System Stack Pointer (SSP)
USP and SSP are 16-bit registers that indicate the memory addresses for saving and
restoring data when a push/pop instruction or subroutine is executed.
■ User Stack Pointer (USP) and System Stack Pointer (SSP)
The USP and SSP registers are used by stack instructions. The USP register is enabled when
the S flag in the processor status register is "0", and the SSP register is enabled when the S flag
is "1" (see Figure 2.7-5). Since the S flag is set when an interrupt is accepted, register values
are always saved in the memory area indicated by SSP during interrupt processing. SSP is
used for stack processing in an interrupt routine, while USP is used for stack processing outside
an interrupt routine. If the stack space is not divided, use only the SSP.
During stack processing, the high-order 8 bits of an address are indicated by SSB (for SSP) or
USB (for USP). USP and SSP are not initialized by a reset. Instead, they hold undefined values.
Figure 2.7-5 Stack Operation Instruction and Stack Pointer (PUSHW A when the S flag is "0")
MSB
Before execution
AL
S flag
After execution
AL
A624 H
USB
C6 H
USP
F328 H
0
SSB
56 H
SSP
1234 H
A624 H
USB
C6 H
USP
F326 H
0
SSB
56 H
SSP
1234 H
C6F326 H
LSB
XX
XX
User stack is used because
the S flag is "0".
C6F326 H
A6 H
24 H
Figure 2.7-6 Stack Operation Instruction and Stack Pointer (PUSHW A when the S flag is "1")
MSB
Before execution
AL
S flag
After execution
AL
A624 H
USB
C6 H
USP
F328 H
1
SSB
56 H
SSP
1234 H
A624 H
USB
C6 H
USP
F328 H
1
SSB
56 H
SSP
1232 H
LSB
561232 H
XX
XX
561232 H
A6 H
24 H
System stack is used because
the S flag is "1".
Note:
Specify an even-numbered address in the stack pointer whenever possible.
31
CHAPTER 2 CPU
2.7.3
Processor Status (PS)
The PS register consists of the bits controlling the CPU Operation and the bits
indicating the CPU status.
■ Processor Status (PS)
As shown in Figure 2.7-7, "Processor Status (PS) Structure", the PS register consists of a
register bank pointer (RP) and an interrupt level mask register (ILM). The RP indicates the start
address of a register bank. The low-order byte of the PS register is a condition code register
(CCR), containing the flags to be set or reset depending on the results of instruction execution
or interrupt occurrences.
Figure 2.7-7 Processor Status (PS) Structure
bit 15
13 12
PS
8 7
ILM
0
RP
CCR
■ Condition Code Register (CCR)
Figure 2.7-8 is a diagram of condition code register configuration.
Figure 2.7-8 Condition Code Register (CCR) Configuration
bit
Initial value →
7
-
6
I
0
5
S
1
3
T
X
4
N
X
2
Z
X
1
V
X
0
C
X
: CCR
X: Undefined
❍ I: Interrupt enable flag:
Interrupts other than software interrupts are enabled when the I flag is "1" and are masked when
the I flag is "0". The I flag is cleared by a reset.
❍ S: Stack flag:
When the S flag is "0", USP is enabled as the stack manipulation pointer.
When the S flag is "1", SSP is enabled as the stack manipulation pointer.
The S flag is set by an interrupt reception or reset.
❍ T: Sticky bit flag:
"1" is set in the T flag when there is at least one "1" in the data shifted out from the carry after
execution of a logical right/arithmetic right shift instruction. Otherwise, "0" is set in the T flag. In
addition, "0" is set in the T flag when the shift amount is zero.
❍ N: Negative flag:
The N flag is set when the MSB of the operation result is "1", and is otherwise cleared.
❍ Z: Zero flag:
The Z flag is set when the operation result is all zeroes, and is otherwise cleared.
32
CHAPTER 2 CPU
❍ V: Overflow flag:
The V flag is set when an overflow of a signed value occurs as a result of operation execution
and is otherwise cleared.
❍ C: Carry flag:
The C flag is set when a carry-up or carry-down from the MSB occurs as a result of operation
execution, and is otherwise cleared.
■ Register Bank Pointer (RP)
The RP register indicates the relationship between the general-purpose registers of the F2MC16LX and the internal RAM addresses. Specifically, the RP register indicates the first memory
address of the currently used register bank in the following conversion expression: [00180H +
(RP)×10H] (see Figure 2.7-9). The RP register consists of five bits, and can take a value
between 00H and 1FH. Register banks can be allocated at addresses from 000180H to 00037H
in memory.
Even within that range, however, the register banks cannot be used as general-purpose
registers if the banks are not in internal RAM. The RP register is initialized to all zeroes by a
reset. An instruction may transfer an eight-bit immediate value to the RP register; however, only
the low-order five bits of that data are used.
Figure 2.7-9 Register Bank Pointer (RP)
Initial value →
B4
0
B3
0
B2
0
B1
0
B0
0
: RP
33
CHAPTER 2 CPU
■ Interrupt Level Mask Register (ILM)
The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt
request is accepted only when the level of the interrupt is higher than that indicated by these
three bits. Level 0 is the highest priority interrupt, and level 7 is the lowest priority interrupt (see
Table 2.7-1). Therefore, for an interrupt to be accepted, its level value must be smaller than the
current ILM value. When an interrupt is accepted, the level value of that interrupt is set in ILM.
Thus, an interrupt of the same or lower level cannot be accepted subsequently. ILM is initialized
to all zeroes by a reset. An instruction may transfer an eight-bit immediate value to the ILM
register, but only the low-order three bits of that data are used.
Figure 2.7-10 Interrupt Level Register (ILM)
Initial value →
ILM2
0
ILM1
0
ILM0
0
: ILM
Table 2.7-1 Levels Indicated by the Interrupt Level Mask (ILM) Register
34
ILM2
ILM1
ILM0
Level value
Acceptable interrupt level
0
0
0
0
Interrupt disabled
0
0
1
1
0 only
0
1
0
2
Level value smaller than 1
0
1
1
3
Level value smaller than 2
1
0
0
4
Level value smaller than 3
1
0
1
5
Level value smaller than 4
1
1
0
6
Level value smaller than 5
1
1
1
7
Level value smaller than 6
CHAPTER 2 CPU
2.7.4
Program Counter (PC)
The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory
address of an instruction code to be executed by the CPU. The high-order eight bits of
the address are indicated by the PCB. The PC register is updated by a conditional
branch instruction, subroutine call instruction, interrupt, or reset.
The PC register can also be used as a base pointer for operand access.
■ Program Counter (PC)
Figure 2.7-11 shows the program counter.
Figure 2.7-11 Program Counter
PCB
FEH
PC
ABCDH
Next instruction to be executed
FEABCDH
35
CHAPTER 2 CPU
2.8
Register Bank
A register bank consists of eight words. The register bank can be used as the
following general-purpose registers for arithmetic operations: byte registers R0 to R7,
word registers RW0 to RW7, and long word registers RL0 to RL3. In addition, R0 to R7
can be used as instruction pointers.
■ Register Bank
Table 2.8-1 lists the functions of the registers. Table 2.8-2 indicates the relationship between the
registers.
In the same manner as for an ordinary RAM area, the register bank values are not initialized by
a reset. The status before a reset is maintained. When the power is turned on, however, the
register bank will have an undefined value.
Table 2.8-1 Each Register Functions
R0 to R7
RW0 to RW7
RL0 to RL3
Used as operands of instructions.
Note: R0 is also used as a counter for barrel shift or normalization
instructions.
Used as pointers.
Used as operands of instructions.
Note: RW0 is used as a counter for string instructions.
Used as long pointers.
Used as operands of instructions.
Table 2.8-2 Relationship between Each Registers
RW0
RL0
RW1
RW2
RL1
RW3
R0
RW4
R1
RL2
R2
RW5
R3
R4
RW6
R5
RL3
R6
RW7
R7
36
CHAPTER 2 CPU
❍ Direct page register (DPR) <Initial value: 01H>
DPR specifies addr8 to addr15 of the instruction operands in direct addressing mode as shown
in Figure 2.8-1. DPR is eight bits long, and is initialized to 01H by a reset.
Figure 2.8-1 Generating a Physical Address in Direct Addressing Mode
DTB register
DPR register
Direct address during instruction
αααααααα
ββββββββ
γγγγγγγγ
LSB
MSB
24-bit physical
address
ααααααααββββββββγγγγγγγγ
❍ Program counter bank register (PCB) <Initial value: Value in reset vector>
❍ Data bank register(DTB) <Initial value: 00H>
❍ User stack bank register(USB) <Initial value: 00H>
❍ System stack bank register(SSB) <Initial value: 00H>
❍ Additional data bank register(ADB) <Initial value: 00H>
Each bank register indicates the memory bank where the PC, DT, SP (user), SP (system), or
AD space is allocated. All bank registers are one byte long. PCB is initialized to the value of
reset vector. Bank registers other than PCB can be read or written to. PCB can be read but
cannot be written to.
PCB is rewritten when the JMPP, CALLP, RETP, RETIQ, or RETF instruction branching to the
entire 16 Mbyte space is executed or when an interrupt occurs. For operation of each register,
see Section "2.2 Memory Space".
37
CHAPTER 2 CPU
2.9
Prefix Codes
Placing a prefix code before an instruction partially changes the operation of the
instruction. Three types of prefix codes can be used: bank select prefix, common
register bank prefix, and flag change disable prefix.
■ Bank Select Prefix
The memory space used for accessing data is determined for each addressing mode.
When a bank select prefix is placed before an instruction, the memory space used for accessing
data by that instruction can be selected regardless of the addressing mode.
Table 2.9-1 lists the bank select prefixes and the corresponding memory spaces.
Table 2.9-1 Bank Select Prefix
Bank select prefix
Selected space
PCB
PC space
DTB
Data space
ADB
AD space
SPB
Either the SSP or USP space is used according to the stack flag
value.
However, use the following instructions with care:
❍ String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW)
The bank register specified by an operand is used regardless of existence of the prefix.
❍ Stack manipulation instructions (PUSHW, POPW)
SSB or USB is used according to the S flag regardless of existence of the prefix.
❍ I/O access instructions
MOV A, io / MOV io, A /MOVX A, io / MOVW A, io /MOVW io, A / MOV io, #imm8
MOVW io, #imm16 / MOVB A, io:bp / MOVB io:bp, A /SETB io:bp / CLRB io:bp
BBC io:bp, rel / BBS io:bp, rel/WBTC, WBTS
The IO space of the bank is used regardless of the prefix.
❍ Flag change instructions (AND CCR,#imm8/OR CCR,#imm8)
The instruction is executed normally, but the prefix affects the next instruction.
❍ POPW PS
SSB or USB is used according to the S flag regardless of existence of the prefix. The prefix
affects the next instruction.
❍ MOV ILM,#imm8
The instruction is executed normally, but the prefix affects the next instruction.
38
CHAPTER 2 CPU
❍ RETI
SSB is used regardless of existence of the prefix.
■ Common Register Bank Prefix (CMR)
To simplify data exchange between multiple tasks, the same register bank must be accessed
relatively easily regardless of the RP value. When CMR is placed before an instruction that
accesses a register bank, that instruction accesses the common bank (the register bank
selected when RP=0) at addresses from 000180H to 00018FH regardless of the current RP
value. However, use the following instructions with care:
❍ String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW)
If an interrupt request occurs during execution of a string instruction with a prefix code, the
prefix code becomes invalid when the string instruction is resumed after the interrupt is
processed. Thus, the string instruction is executed falsely after the interrupt is processed. Do
not prefix any of the above string instructions with CMR.
❍ Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS)
The instruction is executed normally, but the prefix affects the next instruction.
❍ MOV ILM,#imm8
The instruction is executed normally, but the prefix affects the next instruction.
■ Flag Change Disable Prefix (NCC)
To disable flag changes, use the flag change disable prefix code (NCC). Placing NCC before an
instruction disables flag changes associated with that instruction. Use the following instructions
with care:
❍ String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW)
If an interrupt request occurs during execution of a string instruction with a prefix code, the
prefix code becomes invalid when the string instruction is resumed after the interrupt is
processed. Thus, the string instruction is executed incorrectly after the interrupt is processed.
Do not prefix any of the above string instructions with NCC.
❍ Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS)
The instruction is executed normally, but the prefix affects the next instruction.
❍ Interrupt instructions (INT #vct8, INT9, INT addr16, INTP addr24, RETI)
CCR changes according to the instruction specifications regardless of existence of the prefix.
❍ JCTX @A
CCR changes according to the instruction specifications regardless of existence of the prefix.
❍ MOV ILM,#imm8
The instruction is executed normally, but the prefix affects the next instruction.
39
CHAPTER 2 CPU
2.10 Interrupt Disable Instructions
Interrupt requests are not sampled for the following ten instructions:
- MOV ILM,#imm8
- PCB
- SPB
- OR CCR,#imm8
- NCC
- AND CCR,#imm8
- ADB
- CMR
- POPW PS
- DTB
■ Interrupt Disable Instructions
If a valid interrupt request occurs during execution of any of the above instructions, the interrupt
can be processed only when an instruction other than the above is executed. For details, see
Figure 2.10-1.
Figure 2.10-1 Interrupt Disable Instruction
Interrupt disable instruction
• • • • • • • •
(a)
•••
(a) Ordinary
instruction
Interrupt request generated
Interrupt acceptance
■ Restrictions on Interrupt Disable Instructions and Prefix Instructions
When a prefix code is placed before an interrupt disable instruction, the prefix code affects the
first instruction after the code other than the interrupt disable instruction. For details, see Figure
2.10-2.
Figure 2.10-2 Interrupt Disable Instructions and Prefix Codes
Interrupt disable instruction
MOV A, FFH
NCC
••••
MOV ILM,#imm8
CCR:XXX10XX
ADD A,01H
CCR:XXX10XX
CCR does not change with NCC.
■ Consecutive Prefix Codes
When competitive prefix codes are placed consecutively, the latter becomes valid.
In the figure below, competitive prefix codes are PCB, ADB, DTB, and SPB. For details, see
Figure 2.10-3.
Figure 2.10-3 Consecutive Prefix Codes
Prefix code
•••••
ADB
DTB
PCB
ADD A,01H
••••
PCB is valid as the prefix code.
40
CHAPTER 2 CPU
2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi"
Instructions
Set "00H" in the bank register before using the "DIV A, Ri" and "DIVW A, RWi"
Instructions.
■ Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions
Table 2.11-1 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions (i = 0 to 7)
Instruction
Bank register
affected by the
execution of the
instructions listed
on the left
Address that stores the remainder
DIV A, R0
(DTB: Upper 8 bits) + (0180H + RP x 10H + 8H : Lower 16 bits)
DIV A, R1
(DTB: Upper 8 bits) + (0180H + RP x 10H + 9H : Lower 16 bits)
DIV A, R4
(DTB: Upper 8 bits) + (0180H + RP x 10H + CH : Lower 16 bits)
DIV A, R5
DTB
(DTB: Upper 8 bits) + (0180H + RP x 10H + DH : Lower 16 bits)
DIVW A, RW0
(DTB: Upper 8 bits) + (0180H + RP x 10H + 0H : Lower 16 bits)
DIVW A, RW1
(DTB: Upper 8 bits) + (0180H + RP x 10H + 2H : Lower 16 bits)
DIVW A, RW4
(DTB: Upper 8 bits) + (0180H + RP x 10H + 8H : Lower 16 bits)
DIVW A, RW5
(DTB: Upper 8 bits) + (0180H + RP x 10H + AH : Lower 16 bits)
DIV A, R2
(ADB: Upper 8 bits) + (0180H + RP x 10H + AH : Lower 16 bits)
DIV A, R6
ADB
(ADB: Upper 8 bits) + (0180H + RP x 10H + EH : Lower 16 bits)
DIVW A, RW2
(ADB: Upper 8 bits) + (0180H + RP x 10H + 4H : Lower 16 bits)
DIVW A, RW6
(ADB: Upper 8 bits) + (0180H + RP x 10H + EH : Lower 16 bits)
DIV A, R3
(USB *2: Upper 8 bits) + (0180H + RP x 10H + BH : Lower 16 bits)
DIV A, R7
DIVW A, RW3
DIVW A, RW7
USB
SSB *1
(USB *2: Upper 8 bits) + (0180H + RP x 10H + FH : Lower 16 bits)
(USB *2: Upper 8 bits) + (0180H + RP x 10H + 6H : Lower 16 bits)
(USB *2: Upper 8 bits) + (0180H + RP x 10H + EH : Lower 16 bits)
*1: Depends on the S bit of the CCR register.
*2: In the event that the S bit of the CCR register is "0"
If the value of the bank registers (DTB, ADB, USB, and SSB) is "00H", the remainder after
division is stored in the register of the instruction operands. Otherwise, the upper eight bits is
specified by the bank register corresponding to the register of the instruction operand, and the
lower 16 bits is the same as the address of the register of the instruction operand. The
remainder is stored in the bank register specified by the upper eight bits.
41
CHAPTER 2 CPU
❍ Example:
If "DIV A,R0" is executed with DTB = 053H and RP = 03H, the address of R0 is 0180H + RP
(03H) x 10H + 08H (R0 corresponding address) = 0001B8H. Since the data bank register
(DTB) is specified by "DIV A,R0" as the bank register, the remainder is stored in address
"05301B8H", which was obtained by adding the bank address "053H".
Reference:
For information about the bank register and Ri and RWi registers, see Section "2.7 Registers".
■ Use of the "DIV A, Ri" and "DIVW A, RWi" Instructions without Precautions
To enable users to develop programs without having to take precautions for using the "DIV
A,Ri" and "DIVW A,RWi" instructions, special compilers and assemblers are available. The
special compiler does not generate the instructions in Table 2.11-1. The special assemblers
have a function that replaces the instructions in Table 2.11-1 with equivalent instruction strings.
For the MB90590 series, use the following types of compilers and assemblers:
❍ Compiler
cc907 V02L06 or later, or fcc907s V30L02 or later
❍ Assembler
asm907a V03L04 or later, or fasm907s V30L04 (Rev. 300004) or later
42
CHAPTER 3
INTERRUPTS
This chapter explains the interrupt functions and operations.
3.1 Outline of Interrupts
3.2 Interrupt Vector
3.3 Interrupt Control Registers (ICR)
3.4 Interrupt Flow
3.5 Hardware Interrupts
3.6 Software Interrupts
3.7 Extended Intelligent I/O Service (EI2OS)
3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O
Service (EI2OS)
3.9 Exceptions
43
CHAPTER 3 INTERRUPTS
3.1
Outline of Interrupts
The F2MC-16LX has interrupt functions that terminate the currently executing
processing and transfer control to another specified program when a specified event
occurs.
■ Outline of Interrupts
There are four types of interrupt functions:
• Hardware interrupt:
Interrupt processing due to an internal resource event
• Software interrupt:
Interrupt processing due to a software event occurrence
instruction
• Extended intelligent I/O service (EI2OS): Transfer processing due to an internal resource event
• Exception:
Interruption due to an occurrence of exclusive operation
This section explains these 4 types of interrupt.
■ Hardware Interrupts
A hardware interrupt is activated by an interrupt request from an internal resource. A hardware
interrupt request occurs when both the interrupt request flag and the interrupt enable flag in an
internal resource are set. Therefore, an internal resource must have an interrupt request flag
and interrupt enable flag to issue a hardware interrupt request.
❍ Specifying an interrupt level
An interrupt level can be specified for the hardware interrupt. To specify an interrupt level, use
the level setting bits (IL0, IL1, and IL2) of the interrupt controller.
❍ Masking a hardware interrupt request
A hardware interrupt request can be masked by using the I flag of the processor status register
(PS) in the CPU and the ILM bits (IL0, IL1, and IL2). When an unmasked interrupt request
occurs, the CPU saves 12 bytes of data that consists of registers PS, PC, PCB, DTB, ADB,
DPR, and A in the memory area indicated by the SSB and SSP registers.
Figure 3.1-1 Overview of Hardware Interrupts
PS
Register file
IR
➅
F2M C - 1 6 LX . CPU
➆
44
➁
Interrupt level IL
Enable FF
AND
➄
Comparator
➃
➂
Peripheral
Cause FF
➀
ILM
Check
Level comparator
F2MC-16LX bus
Microcode
I
Interrupt
controller
PS: Processor status
I:
Interrupt enable flag
ILM: Interrupt level mask register
IR: Instruction register
CHAPTER 3 INTERRUPTS
■ Software Interrupts
Software interrupts has a transfer function of control from executing the CPU current operation
to interrupt processing program defined by user.
Interrupts requested by executing the INT instruction are software interrupts. An interrupt
request by the INT instruction does not have an interrupt request or enable flag. An interrupt
request is issued always by executing the INT instruction.
No interrupt level is assigned to the INT instruction. Therefore, ILM is not updated when the INT
instruction is used. Instead, the I flag is cleared and the continuing interrupt requests are
suspended.
Figure 3.1-2 Overview of Software Interrupts
➀
PS
Register file
F2MC-16LX bus
➁
Microcode
F 2 M C - 1 6 LX · C P U
I
S
B unit
IR
Queue
PS:
I:
ILM:
IR:
B unit:
Processor status
Interrupt enable flag
Interrupt level mask register
Instruction register
Bus interface unit
Fetch
Save
Instruction bus
RAM
■ Extended Intelligent I/O Service (EI2OS)
The extended intelligent I/O service automatically transfers data between an internal resource
and memory. This processing is traditionally performed by an interrupt processing program, but
the EI2OS enables data to be transferred in a manner similar to a DMA (direct memory access)
operation.
To activate the extended intelligent I/O service function from an internal resource, the interrupt
control register (ICR) of the interrupt controller must have an extended intelligent I/O service
enable flag (ISE).
The extended intelligent I/O service is started when an interrupt request occurs with "1"
specified in the ISE flag. To generate a normal interrupt using a hardware interrupt request, set
the ISE flag to "0".
45
CHAPTER 3 INTERRUPTS
Figure 3.1-3 Overview of the Extended Intelligent I/O Service (EI2OS)
Memory space
by IOA
I/O register
I/O register
Peripheral
Interrupt request
CPU
➂
➂
ISD
by ICS
➁
➀
Interrupt control register
Interrupt controller
by BAP
➃
Buffer
➀ I/O requests transfer.
➁ The interrupt controller selects the
descriptor.
➂ The transfer source and destination
are read from the descriptor.
by DCT
➃ Data is transferred between I/O and
memory.
■ Exceptions
Exception processing is basically the same as interrupt processing. When an exception is
detected between instructions, exception processing is performed. In general, exception
processing occurs as a result of an unexpected operation. Therefore, use exception processing
only for debugging programs or for activating recovery software in an emergency.
46
CHAPTER 3 INTERRUPTS
3.2
Interrupt Vector
An interrupt vector uses the same area for both hardware and software interrupts. For
example, interrupt request number INT42 is used for a delayed hardware interrupt and
for software interrupt INT #42. Therefore, the delayed interrupt and INT #42 call the
same interrupt processing routine. Interrupt vectors are allocated between addresses
FFFC00H and FFFFFFH as shown in Table 3.2-1.
■ Interrupt Vector
Table 3.2-1 Interrupt Vectors
Interrupt request
Vector address L
Vector address H
Vector address
bank
Mode register
INT 0 *1
FFFFFCH
FFFFFDH
FFFFFEH
Unused
INT 1 *1
FFFFF8H
FFFFF9H
FFFFFAH
Unused
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
INT 7 *1
FFFFE0H
FFFFE1H
FFFFE2H
Unused
INT 8 *2
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDFH
INT 9
FFFFD8H
FFFFD9H
FFFFDAH
Unused
INT 10 *3
FFFFD4H
FFFFD5H
FFFFD6H
Unused
INT 11
FFFFD0H
FFFFD1H
FFFFD2H
Unused
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
INT 254
FFFC04H
FFFC05H
FFFC06H
Unused
INT 255
FFFC00H
FFFC01H
FFFC02H
Unused
*1: When PCB is FFH, the vector area for the CALLV instruction is the same as that for INT #vct8 (#0 to #7).
*2: The vector is a reset vector.
*3: The vector is an exception processing vector.
■ Listing of Interrupt Vectors
See Table D-1 in "APPENDIX D List of MB90590 Series Interrupt Vectors".
47
CHAPTER 3 INTERRUPTS
3.3
Interrupt Control Registers (ICR)
The interrupt control registers are in the interrupt controller. Each interrupt control
register has a corresponding I/O that has an interrupt function. The interrupt control
registers have the following three functions:
• Setting an interrupt level for corresponding peripherals
• Selecting whether to use an ordinary interrupt or extended intelligent I/O service for
the corresponding peripherals
• Selecting the extended intelligent I/O service channel
Do not access an interrupt control register by using a read-modify-write instruction, as
doing so causes a malfunction.
■ Interrupt Control Register (ICR)
Figure 3.3-1 is a diagram of the bit configuration of an interrupt control register.
Figure 3.3-1 Interrupt Control Register (ICR)
bit
15/7
14/6
ICS3
ICS2
W
W
13/5
ICS1
or
S1
*
12/4
ICS0
or
S0
*
11/3
10/2
9/1
8/0
ISE
IL2
IL1
IL0
R/W
R/W
R/W
R/W
Interrupt control register
00000111B when reset
*: "1" is always read. ICS1 and ICS0 are valid for write only. S1 and S0 are valid for read only.
Note:
ICS3 to ICS0 are valid only when EI2OS is activated. Set "1" in ISE to activate EI2OS, and set "0"
in ISE not to activate it. When EI2OS is not to be activated, any value can be set in ICS3 to ICS0.
48
CHAPTER 3 INTERRUPTS
[bit 10 to bit 8] [bit 2 to bit 0]: IL0, IL1, and IL2 (Interrupt Level setting bits)
These bits are readable and writable, and specify the interrupt level of the corresponding
internal resources. Upon a reset, these bits are initialized to level 7 (no interrupt). Table 3.3-1
describes the relationship between the interrupt level setting bits and interrupt levels.
Table 3.3-1 Interrupt Level Setting Bits and Interrupt Levels
ILM2
ILM1
ILM0
Level
0
0
0
0 (Highest)
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6 (Lowest)
1
1
1
7 (No interrupt)
[bit 11, bit 3]: ISE (Extended Intelligent I/O Service enable bits)
The ISE bit is readable and writable. In response to an interrupt request, EI2OS is activated
when "1" is set in the ISE bit and an interrupt sequence is activated when "0" is set in the ISE
bit. Upon completion of EI2OS, the ISE bit is cleared to a zero. If the corresponding
peripheral does not have the EI2OS function, the ISE bit must be set to "0" on the software
side. These bits are readable and writable.
Upon a reset, the ISE bit is initialized to "0".
49
CHAPTER 3 INTERRUPTS
[bit 15 to bit 12] [bit 7 to bit 4]: ICS 3 to ICS 0 (Extended Intelligent I/O Service channel
select bits)
ICS3 to ICS0 are write-only bits. These bits specify the EI2OS channel. The values set in
these bits determined the intelligent I/O service descriptor addresses in memory, which is
explained later. The ICS bits are initialized "0000" by a reset.
Table 3.3-2 describes the correspondence between the ICS bits, channel numbers, and
descriptor addresses.
Table 3.3-2 ICS bits, Channel Numbers, and Descriptor Addresses
ICS3
ICS2
ICS1
ICS0
Selected channel
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
[bit 13, bit 12] [bit 5, bit 4]: S0 and S1 (Extended Intelligent I/O Service status)
S0 and S1 are read-only bits. The values set in these bits indicate the end condition of
EI2OS. By checking the value of these bits when EI2OS ends, the terminal condition can be
determined. These bits are initialized to "00" upon a reset.
Table 3.3-3 shows the relationship between the S bits and the end conditions.
Table 3.3-3 S Bits and End Conditions
50
S1
S0
End condition
0
0
EI2OS running or not activated
0
1
Termination by count
1
0
Reserved
1
1
Termination by request from resource
CHAPTER 3 INTERRUPTS
3.4
Interrupt Flow
Figure 3.4-1 shows the interrupt flow.
■ Interrupt Flow
Figure 3.4-1 Interrupt Flow
I:
ILM:
IF:
IE:
Flag in CCR
Level register in CPU
Internal resource interrupt request
Internal resource interrupt enable flag
ISE: EI2OS enable flag
IL: Internal resource interrupt request level
S: Flag in CCR
I & IF & IE = 1
AND
ILM > IL
YES
NO
NO
YES
ISE = 1
Fetching and decoding
the next instruction
Saving PS, PC, PCB, DTB,
ADB, DPR, and A into the
stack of SSP, and setting ILM=IL
Executing the extended
intelligent I/O service
YES
INT instruction
NO
Executing an ordinary
instruction
NO
Completion of
string instruction
repetition
YES
Saving PS, PC, PCB, DTB, ADB,
DPR, and A into the stack of SSP,
and setting I=O and ILM=IL
S 1
Fetching the interrupt vector
Updating PC
51
CHAPTER 3 INTERRUPTS
Figure 3.4-2 Register Saving during Interrupt Processing
Word (16 bits)
MSB
LSB
H
SSP (SSP value before interrupt generation)
AH
AL
DPR
ADB
DPB
PCB
PC
PS
L
52
SSP (SSP value after interrupt generation)
CHAPTER 3 INTERRUPTS
3.5
Hardware Interrupts
In response to an interrupt request signal from an internal resource, the CPU pauses
current program execution and transfers control to the interrupt processing program
defined by the user. This function is called the hardware interrupt function.
■ Hardware Interrupts
A hardware interrupt occurs when the relevant conditions are satisfied as a result of two
operations: comparison between the interrupt request level and the value in the interrupt level
mask register (ILM) of PS in the CPU, and hardware reference to the I flag value of PS.
The CPU performs the following processing when a hardware interrupt occurs:
•
Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to
the system stack.
•
Sets ILM in the PS register. The currently requested interrupt level is automatically set.
•
Fetches the corresponding interrupt vector value and branches to the processing indicated
by that value.
■ Structure of Hardware Interrupt
Hardware interrupts are handled by the following three sections:
❍ Internal resources
Interrupt enable and request bits: Used to control interrupt requests from resources.
❍ Interrupt controller
ICR: Assigns interrupt levels and determines the priority levels of simultaneously requested
interrupts.
❍ CPU
I and ILM:
Used to compare the requested and current interrupt levels and to identify the
interrupt enable status.
Microcode: Interrupt processing step
The status of these sections are indicated by the resource control registers for internal
resources, the ICR for the interrupt controller, and the CCR value for the CPU. To
use a hardware interrupt, set the three sections beforehand by using software.
The interrupt vector table referenced during interrupt processing is assigned to addresses
FFFC00H to FFFFFFH in memory. These addresses are shared with software interrupts.
Table D-2 in "APPENDIX D List of MB90590 Series Interrupt Vectors" lists the assignments for
the MB90590 series.
53
CHAPTER 3 INTERRUPTS
3.5.1
Hardware Interrupt Operation
An internal resource that has the hardware interrupt request function has an interrupt
request flag and interrupt enable flag. The interrupt request flag indicates whether an
interrupt request exists, and the interrupt enable flag indicates whether the relevant
internal resource requests an interrupt to the CPU. The interrupt request flag is set
when an event occurs that is unique to the internal resource. When the interrupt
enable flag indicates "enable", the resource issues an interrupt request to the interrupt
controller.
■ Hardware Interrupt Operation
When two or more interrupt requests are received at the same time, the interrupt controller
compares the interrupt levels (IL) in ICR, selects the request at the highest level (the smallest IL
value), then reports that request to the CPU. If multiple requests are at the same level, the
interrupt controller selects the request with the lowest interrupt number. The relationship
between the interrupt requests and ICRs is determined by the hardware.
The CPU compares the received interrupt level and the ILM in the PS register. If the interrupt
level is smaller than the ILM value and the I bit of the PS register is set to "1", the CPU activates
the interrupt processing microcode after the currently executing instruction is completed. The
CPU references the ISE bit of the ICR of the interrupt controller at the beginning of the interrupt
processing microcode, checks that the ISE bit is "0" (interrupt), and activates the interrupt
processing body.
The interrupt processing body saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the
memory area indicated by SSB and SSP, fetches three bytes of interrupt vector and loads them
onto PC and PCB, updates the ILM of PS to a level value of the received interrupt, sets the S
flag to "1", then performs branch processing. As a result, the interrupt processing program
defined by the user is executed next.
54
CHAPTER 3 INTERRUPTS
3.5.2
Occurrence and Release of Hardware Interrupt
Figure 3.5-1 shows the processing flow from occurrence of a hardware interrupt to
release of the interrupt request in an interrupt processing program.
■ Occurrence and Release of Hardware Interrupt
Figure 3.5-1 Occurrence and Release of Hardware Interrupt
IR
➅
Check
➄
F2M C - 1 6 LX . C P U
➆
➁
Level comparator
Enable FF
AND
Comparator
➃
PS:
I:
ILM:
IR:
Processor status
Interrupt enable flag
Interrupt level mask register
Instruction register
➂
Peripheral
Cause FF
➀
ILM
Interrupt level IL
F2MC-16LX bus
Microcode
I
PS
Register file
Interrupt
controller
1. An interrupt cause occurs in the inside of peripheral.
2. The interrupt enable bit in the peripheral is referenced. If interrupts are enabled, the
peripheral issues an interrupt request to the interrupt controller.
3. Upon reception of the interrupt request, the interrupt controller determines the priority levels
of simultaneously requested interrupts. Then, the interrupt controller transfers the interrupt
level of the corresponding interrupt to the CPU.
4. The CPU compares the interrupt level requested by the interrupt controller with the ILM bit of
the processor status register.
5. If the comparison shows that the requested level is higher than the current interrupt
processing level, the I flag value of the same processor status register is checked.
6. If the check in step 5. shows that the I flag indicates interrupt enable status, the requested
level is written to the ILM bit. Interrupt processing is performed as soon as the currently
executing instruction is completed, then control is transferred to the interrupt processing
routine.
7. When the interrupt cause of step 1. is cleared by software in the user interrupt processing
routine, the interrupt request is completed.
55
CHAPTER 3 INTERRUPTS
The time required for the CPU to execute the interrupt processing in steps 6. and 7. is shown
below.
Interrupt start: 24 + 6
× (Table 3.3-2 machine cycles)
Interrupt return: 15 + 6 x (Table 3.3-2 machine cycles) RETI instruction
Table 3.5-1 Compensation Values for Interrupt Processing Cycle Count
Address indicated by the stack pointer
Cycle count compensation value
Internal area, even-numbered address
0
Internal area, odd-numbered address
+2
56
CHAPTER 3 INTERRUPTS
3.5.3
Multiple interrupts
As a special case, no hardware interrupt request can be accepted while data is being
written to the I/O area. This is intended to prevent the CPU from operating falsely
because of an interrupt request issued while an interrupt control register for a
resource is being updated.
If an interrupt occurs during interrupt processing, a higher-level interrupt is processed
first.
■ Multiple Interrupts
The F2MC-16LX CPU supports multiple interrupts. If an interrupt of a higher level occurs while
another interrupt is being processed, control is transferred to the high-level interrupt after the
currently executing instruction is completed. After processing of the high-level interrupt is
completed, the original interrupt processing is resumed. An interrupt of the same or lower level
may be generated while another interrupt is being processed. If this happens, the new interrupt
request is suspended until the current interrupt processing is completed, unless the ILM value or
I flag is changed by an instruction. The extended intelligent I/O service cannot be activated from
multiple sources; while an extended intelligent I/O service is being processed, all other interrupt
requests or extended intelligent I/O service requests are suspended.
Figure 3.5-2 shows the order of the registers saved in the stack.
Figure 3.5-2 Registers Saved in Stack
Word (16 bits)
MSB
LSB
H
SSP (SSP value before interrupt generation)
AH
AL
DPR
ADB
DPB
PCB
PC
PS
SSP (SSP value after interrupt generation)
L
57
CHAPTER 3 INTERRUPTS
3.6
Software Interrupts
In response to execution of a special instruction, control is transferred from the
program currently executed by the CPU to the interrupt processing program defined
by the user. This is called the software interrupt function. A software interrupt occurs
always when the software interrupt instruction is executed.
■ Software Interrupts
The CPU performs the following processing when a software interrupt occurs:
•
Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to
the system stack.
•
Sets "0" to PS: I flag. Interrupts are automatically disabled.
•
Fetches the corresponding interrupt vector value, then branches to the processing indicated
by that value.
A software interrupt request issued by the INT instruction has no interrupt request or enable
flag. A software interrupt request is always issued by executing the INT instruction.
The INT instruction does not have an interrupt level. Therefore, the INT instruction does not
update ILM. The INT instruction sets I flag to "0" to suspend subsequent interrupt requests.
■ Structure of Software Interrupts
Software interrupts are handled within the CPU:
CPU.....Microcode: Interrupt processing step
■ List of MB90590 Series Interrupt Vectors
Table D-1 lists the interrupt vectors of the MB90590 series.
As shown in Table D-1, software interrupts share the same interrupt vector area with hardware
interrupts.
For example, interrupt request number INT 12 is used for external interrupt of a hardware
interrupt as well as for INT #12 of a software interrupt. Therefore, external interrupt and INT #12
call the same interrupt processing routine.
■ Software Interrupt Operation
When the CPU fetches and executes the software interrupt instruction, the software interrupt
processing microcode is activated. The software interrupt processing microcode saves 12 bytes
(PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP. The
microcode then fetches three bytes of interrupt vector and loads them onto PC and PCB, sets I
flag to "0" and S flag to "1", and sets the S flag. Then, the microcode performs branch
processing. As a result, the interrupt processing program defined by the user application
program is executed next.
Figure 3.6-1 illustrates the flow from the occurrence of a software interrupt until there is no
interrupt request in the interrupt processing program.
58
CHAPTER 3 INTERRUPTS
Figure 3.6-1 Occurrence and Release of Software Interrupt
➀
PS
Register file
F2MC-16LX bus
➁
Microcode
F 2 M C - 1 6 LX . C P U
I
S
B unit
IR
Queue
Fetch
PS:
I:
ILM:
IR:
B unit:
Processor status
Interrupt enable flag
Interrupt level mask register
Instruction register
Bus interface unit
➂
Save
Instruction bus
RAM
1. The software interrupt instruction is executed.
2. Special CPU registers in the register file are saved according to the microcode
corresponding to the software interrupt instruction.
3. The interrupt processing is completed with the RETI instruction in the user interrupt
processing routine.
■ Others
When the program bank register (PCB) is FFH, the CALLV instruction vector area overlaps the
table of the INT #vct8 instruction. When designing software, ensure that the CALLV instruction
does not use the same address as that of the #vct8 instruction.
Table D-2 shows the relationship of interrupt cause, interrupt vector, and interrupt control
register in the MB90590 series.
59
CHAPTER 3 INTERRUPTS
3.7
Extended Intelligent I/O Service (EI2OS)
Extended Intelligent I/O Service (EI2OS) is a kind of hardware interrupt operation. The
EI2OS function automatically transfers data between input and output and memory. An
interrupt processing program was conventionally used for such processing, but EI2OS
enables data transfer to be performed like DMA (direct memory access).
■ Extended Intelligent I/O Service (EI2OS)
EI2OS has the following advantages over the conventional method:
•
The program size can be small because it is not necessary to write a transfer program.
•
No internal register is used for transfer, eliminating the need for register saving and
increasing the transfer speed.
•
Transfer can be terminated from I/O, preventing unnecessary data from being transferred.
•
The buffer address may either be incremented or left unupdated.
•
The I/O register address may either be incremented or left unupdated.
At the end of EI2OS, processing automatically branches to an interrupt processing routine after
the end condition is set. Thus, the user can identify the end condition.
To implement EI2OS, the hardware is distributed in two blocks. Each block has the following
registers and descriptors.
❍ Interrupt control register
Exists in the interrupt controller and indicates the ISD address.
❍ Extended intelligent I/O service descriptor (ISD)
Exists in RAM and holds the transfer mode, I/O address, number of transfers, and buffer
address.
Note:
The use of EI2OS is not possible with the REALOS real time operating system.
Figure 3.7-1 outlines the extended intelligent I/O service.
60
CHAPTER 3 INTERRUPTS
Figure 3.7-1 Outline of Extended Intelligent I/O Service
Memory space
by IOA
I/O register
••• ••• ••• ••• •••
I/O register
Peripheral
CPU
Interrupt request ➀
➂
ISD
➂
by ICS
➁
Interrupt control register
Interrupt controller
by BAP
➃
Buffer
➀ I/O requests transfer.
➁ The interrupt controller selects the
descriptor.
➂ The transfer source and destination
by
are read from the descriptor.
DCT
➃ Data is transferred between I/O and
memory.
Notes:
The area that can be specified by IOA is between 000000H and 00FFFFH.
The area that can be specified by BAP is between 000000H and FFFFFFH.
The maximum transfer count that can be specified by DCT is 65536.
■ Structure
EI2OS is handled by the following four sections:
• Internal resources
Interrupt enable and request bits: Used to control interrupt requests from resources.
• Interrupt controller
ICR:
Assigns interrupt levels, determines the priority levels of simultaneously
requested interrupts, and selects the EI2OS operation.
• CPU
I and ILM: Used to compare the requested and current interrupt levels and to identify the
interrupt enable status
Microcode: EI2OS processing step
• RAM
Descriptor: Describes the EI2OS transfer information.
61
CHAPTER 3 INTERRUPTS
3.7.1
Extended Intelligent I/O Service Descriptor (ISD)
The extended intelligent I/O service descriptor exists between 000100H and 00017FH in
internal RAM, and consists of the following items:
• Control data for data transfer
• Status data
• Buffer address pointer
■ Extended Intelligent I/O Service Descriptor (ISD)
Figure 3.7-2 shows the configuration of the extended intelligent I/O service descriptor.
Figure 3.7-2 Extended Intelligent I/O Service Descriptor Configuration
H
High-order 8 bits of data counter (DCTH)
Low-order 8 bits of data counter (DCTL)
High-order 8 bits of I/O address pointer (IOAH)
Low-order 8 bits of I/O address pointer (IOAL)
EI 2OS status (ISCS)
High-order 8 bits of buffer address pointer (BAPH)
000100 H + 8 × ICS
Medium-order 8 bits of buffer address pointer (BAPM)
ISD start address
Low-order 8 bits of buffer address pointer (BAPL)
L
■ Data Counter (DCT)
This is a 16-bit register that works as a counter corresponding to the number of data items
transferred. This counter is decremented by one before data transfer. EI2OS is terminated when
this counter reaches "0". Figure 3.7-3 is a diagram of the data counter configuration.
Figure 3.7-3 Data Counter Configuration
62
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
B15
B14
B13
B12
B11
B10
B09
B08
B07
B06
B05
B04
B03
B02
B01
B00
DCT
(Undefined when reset)
CHAPTER 3 INTERRUPTS
■ I/O Register Address Pointer (IOA)
This is a 16-bit register that indicates the low-order address (A15 to A0) of the buffer and I/O
register used for data transfer. The high-order address (A23 to A16) are all zeroes, and any I/O
between addresses 000000H and 00FFFFH can be specified. Figure 3.7-4 is a diagram of the
IOA configuration.
Figure 3.7-4 I/O Register Address Pointer Configuration
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
A15
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
IOA
(Undefined when reset)
■ Buffer Address Pointer (BAP)
This 24-bit register holds the address used for the next EI2OS transfer. BAP exists for each
EI2OS channel. Therefore, each EI2OS channel can be used for transfer with anywhere in the
16-Mbyte space. If the BF bit of ISCS is set to "0" (update enabled), only the low-order 16 bits of
BAP changes and BAPH does not change.
63
CHAPTER 3 INTERRUPTS
EI2OS Status Register (ISCS)
3.7.2
This eight-bit register indicates the update direction (increment/decrement), transfer
data format (byte/word), and transfer direction of the buffer address pointer and the I/O
register address pointer. This register also indicates whether the buffer address
pointer or I/O register address pointer is updated or fixed.
■ EI2OS Status Register (ISCS)
Figure 3.7-5 is a diagram of the ISCS configuration.
Note:
Always write "0" to bit 7 to bit 5 of ISCS.
Figure 3.7-5 ISCS Configuration
bit
7
6
5
Reserved Reserved Reserved
4
3
2
1
0
IF
BW
BF
DIR
SE
ISCS
(Undefined when reset)
Each bit is described below.
[bit 4] IF : Specify whether the I/O register address pointer is updated or fixed.
0 : The I/O register address pointer is updated after data transfer.
1 : The I/O register address pointer is not updated after data transfer.
Note:
Only increment is allowed.
[bit 3] BW : Specify the transfer data length.
0 : Byte
1 : Word
[bit 2] BF : Specify whether the buffer address pointer is updated or fixed.
0 : The buffer address pointer is updated after data transfer.
1 : The buffer address pointer is not updated after data transfer.
Note:
Only the low-order 16 bits of the buffer address are updated. Only increment is allowed.
64
CHAPTER 3 INTERRUPTS
[bit 1] DIR : Specify the data transfer direction.
0 : I/O address pointer --> Buffer address pointer
1 : Buffer address pointer --> I/O address pointer
[bit 0] SE : Control the termination of the extended intelligent I/O service based on resource
requests.
0 : The extended intelligent I/O service is not terminated by a resource request.
1 : The extended intelligent I/O service is terminated by a resource request.
65
CHAPTER 3 INTERRUPTS
3.8
Operation Flow of and Procedure for Using the Extended
Intelligent I/O Service (EI2OS)
Figure 3.8-1 is a diagram of the EI2OS operation flow. Figure 3.8-2 is a diagram of the
EI2OS use procedure.
■ EI2OS Operation Flow
Figure 3.8-1 EI2OS Operation Flow
BAP:
Buffer address pointer
I/OA:
I/O address pointer
ISD:
EI2OS descriptor
ISCS:
EI2OS status
DCT:
Data counter
ISE:
EI2OS enable bit
S1 and S0: EI2OS end status
Interrupt request issued
from internal resource
ISE = 1
NO
Interrupt sequence
YES
Reading ISD/ISCS
End request from resource
YES
SE = 1
NO
DIR = 1
YES
NO
Data indicated by IOA
⇓ (Data transfer)
Memory indicated by BAP
IF = 0
YES
NO
BF = 0
Data indicated by BAP
⇓ (Data transfer)
Memory indicated by IOA
Update value
depends on BW.
Updating IOA
Update value
depends on BW.
Updating BAP
YES
NO
Decrementing DCT
DCT = 00
YES
NO
Setting S1 and S0 to "01"
Setting S1 and S0 to "11"
Setting S1 and S0 to "00"
66
Clearing resource
interrupt request
Clearing ISE to "0"
CPU operation return
Interrupt sequence
CHAPTER 3 INTERRUPTS
Figure 3.8-2 EI2OS Use Flow
Processing by EI2OS
Processing by CPU
EI2OS initialization
JOB execution
Normal
termination
(Interrupt request)
AND (ISE = 1)
Data transfer
Count out or interrupt
occurrence by request
for termination from
resource.
Re-setting of extended intelligent
I/O service
(Switching channels)
Processing data in buffer
The extended EI2OS execution time for each flow is described below.
❍ When data transfer continues (when the stop condition is not satisfied)
(Table 3.8-1 + Table 3.8-2) machine cycles
❍ When a stop request is issued from a resource
(36 + 6 × Table D-2) machine cycles
❍ When the counting is completed
(Table 3.8-1 + Table 3.8-2 + (21 + 6 × Table D-2)) machine cycles
Table 3.8-1 Execution Time when the Extended EI2OS Continues
ISCS SE bit
Set to "0"
I/O address pointer
Set to "1"
Fixed
Updated
Fixed
Updated
Fixed
32
34
33
35
Updated
34
36
35
37
Buffer address pointer
Table 3.8-2 Data Transfer Compensation Values for Extended EI2OS Execution Time
Internal access
I/O address pointer
Buffer address pointer
Internal
access
B/E
O
B/E
0
+2
O
+2
+4
B: Byte data transfer
E: Even address word transfer
O: Odd address word transfer
67
CHAPTER 3 INTERRUPTS
3.9
Exceptions
The F2MC-16LX performs exception processing when the following event occurs:
■ Execution of an Undefined Instruction
Exception processing is fundamentally the same as interrupt processing. When an exception is
detected between instructions, exception processing is performed separately from ordinary
processing. In general, exception processing is performed as a result of an unexpected
operation. Fujitsu recommends using exception processing only for debugging or for activating
emergency recovery software.
■ Exception due to Execution of an Undefined Instruction
The F2MC-16LX handles all codes that are not defined in the instruction map as undefined
instructions. When an undefined instruction is executed, processing equivalent to the INT 10
software interrupt instruction is performed. Specifically, the AL, AH, DPR, DTB, ADB, PCB, PC,
and PS values are saved into the system stack, and processing branches to the routine
indicated by the interrupt number 10 vector. In addition, the I flag is set to "0" and the S flag is
set to "1". The PC value saved in the stack is the address at which the undefined instruction is
stored. Processing can be restored by the RETI instruction, but is of no use, however, because
the same exception occurs again.
68
CHAPTER 4
DELAYED INTERRUPT
This chapter explains the functions and operations of the delayed interrupt.
4.1 Outline of Delayed Interrupt Module
4.2 Delayed Interrupt Register
4.3 Delayed Interrupt Operation
69
CHAPTER 4 DELAYED INTERRUPT
4.1
Outline of Delayed Interrupt Module
The delayed interrupt source module is used to generate interrupts for switching
tasks. Using this module, interrupt requests to the F2MC-16LX CPU can be issued and
canceled by software.
■ Block Diagram of Delayed Interrupt
Figure 4.1-1 is a block diagram of the delayed interrupt source module.
Figure 4.1-1 Block Diagram of Delayed Interrupt Source Mode
F2MC-16LX bus
Delayed interrupt cause issuance/cancellation decoder
Cause latch
■ Notes on Operation
This lock is set by writing "1" to the corresponding bit of DIRR, and is cleared by writing "0" to
the same bit. Therefore, interrupt processing is reactivated immediately after control returns
from interrupt processing, unless the software is designed so that the cause of the interrupt is
cleared within the interrupt processing routine.
70
CHAPTER 4 DELAYED INTERRUPT
4.2
Delayed Interrupt Register
DIRR controls issuance and cancellation of delayed interrupt requests. Writing "1" to
this register issues a delayed interrupt request, and writing "0" cancels the delayed
interrupt request. Upon a reset, the request is canceled.
■ Delayed Interrupt Cause Issuance/Cancellation Register (DIRR: Delayed Interrupt Request Register)
In DIRR, either "0" or "1" can be written to the reserved bit area. However, it is recommended
that a set bit or clear bit instruction be used to access this register for future expansions.
Figure 4.2-1 Delayed Interrupt Cause Issuance/Cancellation Register (DIRR)
bit
Address: 00009FH
Read/write→
Initial value→
15
(-)
(-)
14
(-)
(-)
13
(-)
(-)
12
(-)
(-)
11
(-)
(-)
10
(-)
(-)
9
(-)
(-)
8
R0
(R/W)
(0)
DIRR
At a reset, the request is canceled.
71
CHAPTER 4 DELAYED INTERRUPT
4.3
Delayed Interrupt Operation
When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in
the delayed interrupt source module is set and an interrupt request is issued to the
interrupt controller.
■ Delayed Interrupt Occurrence
When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the
delayed interrupt source module is set and an interrupt request is issued to the interrupt
controller. If this interrupt has the highest priority or if there is no other interrupt request, the
interrupt controller issues an interrupt request to the F2MC-16LX CPU. The F2MC-16LX CPU
compares the ILM bit of its internal CCR register and the interrupt request, and starts the
hardware interrupt processing microprogram as soon as the current instruction is completed if
the interrupt level of the request is higher than that of the ILM bit. The interrupt processing
routine for this interrupt is thus executed.
Figure 4.3-1 Delayed Interrupt Issuance
Delayed interrupt source module
Interrupt controller
F2MC-16LX CPU
WRITE
Other requests
ICR yy
IL
CMP
CMP
DIRR
ICR xx
ILM
INTA
72
CHAPTER 5
CLOCK AND RESET
This chapter explains the functions and operations of clocks and resets.
5.1 Clock Generator
5.2 Reset Cause Occurrence
5.3 Reset Causes
73
CHAPTER 5 CLOCK AND RESET
5.1
Clock Generator
The clock generator controls internal clock operation, including such functions as
sleep, timer, stop, and PLL multiplication. This internal clock is called the machine
clock, and one cycle of the machine clock is called a machine cycle. A clock based on
the source oscillation is called the main clock, and a clock based on the internal VCO
oscillation is called the PLL clock.
■ Notes on Clock Generator
When the operating voltage is 5V, the OSC source oscillation can be between 3 MHz and 5
MHz. When an external clock source is used, its frequency can be between 3 MHz and 16 MHz.
The highest operating frequency for the CPU and peripheral resource circuits is 16 MHz,
however. Normal operation is not guaranteed if a multiplication factor resulting in a higher
frequency than 16 MHz is specified. For example, if the external clock frequency is 16 MHz,
only "1" can be specified as the multiplication factor.
The lowest operating frequency of the VCO oscillation is 4 MHz, and an oscillation below 4 MHz
must not be specified.
Figure 5.1-1 is a block diagram of the clock generator circuit.
Figure 5.1-1 Block Diagram of Clock Generator Circuit
S Q
Reset
Interrupt
HST
Transition to
stop mode
S Q
Machine clock
Transition to
timer or
sleep mode R
R
Selecting the machine clock
S Q
1
R
2
3
4
PLL multiplication
Selecting the oscillation
stabilization wait time
Timebase timer
1/2
X0
1/2048
1/4
1/4
1/8
XL
Selecting the watch-dog
interval
Monitoring
timer
Watch-dog reset
74
CHAPTER 5 CLOCK AND RESET
5.2
Reset Cause Occurrence
When a reset cause occurs, F2MC-16LX terminates the currently executing processing
and waits for reset release. A reset is caused by the following factors:
■ Reset Cause Occurrence
A reset is caused by the following factors:
•
Power-on reset
•
Hardware standby release
•
Watch-dog timer overflow
•
External reset request via RST pin
•
Reset request by software
■ Operation after Reset Release
When a reset cause is removed, the F2MC-16LX immediately outputs the address in which the
reset vector is stored, then fetches the reset vector and mode data. The reset vector and mode
data are assigned to the four bytes between FFFFDCH and FFFFDFH. After reset is released,
the reset vector and mode data are transferred to the registers by the hardware as described in
Figure 5.2-1.
The bus mode after the reset vector and mode data are read is specified by the mode data.
Figure 5.2-1 Source and Destination of Reset Vector and Mode Data
F2MC-16LX CPU
Mode
Memory space
Register
FFFFDFH
Mode data
FFFFDEH
Reset vector bits 23 to 16
FFFFDD H
Reset vector bits 15 to 8
FFFFDCH
Reset vector bits 7 to 0
Micro ROM
Reset sequence
PCB
PC
Note:
For MB90F594A, MB90F594G, MB90F591A and MB90F591G, the reset vector and mode data
have predetermined values by the hard-wired logic.
For more information, refer to Section "24.9 Reset Vector Address in Flash Memory".
75
CHAPTER 5 CLOCK AND RESET
■ Registers not Initialized by Reset Input
This microcontroller contains registers initialized only by a power-on reset.
Table 5.2-1 lists registers not initialized by each reset cause.
Table 5.2-1 Registers not Initialized by Reset Input
CKSCR
LPMCR
Type of reset
WS1
WS0
MCS
CS1
CS0
CG1
CG0
Software reset
(Only RST is used.)
N
N
N
N
N
N
N
Watch-dog reset
N
N
Y
N
N
Y
Y
Power-on reset
Y
Y
Y
Y
Y
Y
Y
Hardware standby
N
N
Y
N
N
Y
Y
WS1 and WS0: Set the oscillation stabilization time for the main clock.
MCS:
Specifies the machine clock (0 = PLL clock or 1 = main clock).
CS1 and CS0: Set the multiplication factor for the PLL clock.
CG1,CG0:
Set the intermittent CPU operation.
Y: Initialized
N: Not initialized (previous status maintained)
In particular, handle the MCS bit carefully because it sets the machine clock. For example, if
power-on does not satisfy the power-on reset specification, no power-on reset occurs. For this
reason, the internal operating frequency may become outside the valid operation range,
because MCS is not initialized, and the microcontroller may not operate normally.
If the CPU crashes for some reason and MCS, CS1, or CS0 is rewritten, the internal operating
frequency may also become outside the valid operation range. The microcontroller may not be
able to recover normally from this status by RST input only (however, if the internal watchdog
state occurs, MCS is initialized and the microcontroller operates normally).
When either of the above cases occurs, use of HST plus RST (connecting HST and RST with a
jumper) is recommended.
Table 5.2-2 lists registers that are not initialized by reset input using HST plus RST. Note that
the operation status after the reset is released differs depending on the reset input type, HST
plus RST reset input, or only RST input, as listed in Table 5.2-2.
Table 5.2-2 Registers not Initialized by Reset Input
CKSCR
LPMCR
Type of reset
HST + RST
WS1
WS0
MCS
CS1
CS0
CG1
CG0
N
N
Y
N
N
Y
Y
Y: Initialized
N: Not initialized (previous status maintained)
76
CHAPTER 5 CLOCK AND RESET
Figure 5.2-2 Operation Transition by Reset Input
[Operation Transition by Reset Input]
Reset input
(RST, HST+RST)
A. Oscillation status
Status
Only RST used (HST ="H")
HST + RST used
Oscillating
Oscillating
Stopped
Waiting for main
clock oscillation
stabilization
Main clock operation enabled
B. Execution timing ("L": Stop, "H": Start)
Only RST used (HST ="H")
HST plus RST used
Main clock mode
Oscillation stabilization
time set before reset input
Power-on reset
Vcc (power supply)
Status
Power-on reset
Oscillating
Stopped
Waiting for main
clock oscillation
stabilization
Main clock operation enabled
Oscillation stabilization time
of 218main clock cycles
Main mode
77
CHAPTER 5 CLOCK AND RESET
5.3
Reset Causes
Table 5.3-1 lists the five reset causes. The machine clock and watch-dog function are
initialized differently for each reset cause.
The reset cause register indicates the reset cause.
■ Reset Causes
Table 5.3-1 Reset Causes
Reset
Cause
Machine clock
Watch-dog timer
Oscillation
stabilization wait
Power-on
When the power is
turned on
Main clock
Stop
Yes
Hardware standby
"L" level input to HST
pin
Main clock
Stop
Yes
Watch-dog timer
Watch-dog timer
overflow
Main clock
Stop
Yes
External pin
"L" level input to RST
pin
Previous status
maintained
Previous status
maintained
No
Software
"0" written to RST bit
of LPMCR
Previous status
maintained
Previous status
maintained
No
Notes: • In stop or hardware standby mode, a reset input allows for oscillation stabilization time regardless
of the reset cause.
• The oscillation stabilization time for a power-on reset is fixed to 218 cycles of source oscillation.
For other types of reset, the oscillation stabilization wait time is determined by CS1 and CS0 of the
clock selection register.
As shown in Figure 5.3-1 each reset cause has a corresponding flip-flop. The contents of the
flip-flop can be obtained by reading the watch-dog timer control register. If identifying the reset
cause is required after the reset is released, ensure that the value read from the watch-dog
timer control register is processed by software and processing branches to an appropriate
program. Figure 5.3-2 is a diagram of the watch-dog timer control register.
78
CHAPTER 5 CLOCK AND RESET
Figure 5.3-1 Reset Cause Bit Block Diagram
HST pin
RST pin
HST=L
RST=L
Without periodic clear
Power on
RST bit set
Power-on
detection circuit
S
R
Hardware standby
release detection
circuit
S
R
Watch-dog timer
reset generating
detection circuit
External reset
request detection
circuit
S
R
S
R
S
WTC register
R
F/F
F/F
F/F
F/F
F/F
Q
Q
Q
Q
Q
LPMCR.RST bit
write detection circuit
Delay
circuit
WTC register read
F2MC-16LX internal bus
Figure 5.3-2 WDTC (Watch-Dog Timer Control) Register
bit
7
6
5
4
Address: 0000A8H
PONR STBR WRST ERST
Read/write→
(R)
(R)
(R)
(R)
Initial value→
(X)
(X)
(X)
(X)
3
SRST
(R)
(X)
2
WTE
(W)
(1)
1
WT1
(W)
(1)
0
WT0
(W)
(1)
WDTC
When there are multiple reset causes, the corresponding reset cause bits in the watch-dog timer
control register are set. Therefore, if an external reset request and a watch-dog reset occur at
the same time, both the ERST and WRST bits are set to "1".
A power-on reset is an exception; while the PONR bit is "1", the values of other bits do not
indicate the correct reset causes. Therefore, design software so that the other reset cause bit
values are ignored while the PONR bit is set to "1".
Table 5.3-2 Reset Cause Bits
Reset cause
PONR
STBR
WRST
ERST
SRST
Power-on
1
-
-
-
-
Hardware standby
*
1
*
*
*
Watch-dog timer
*
*
1
*
*
External pin
*
*
*
1
*
RST bit
*
*
*
*
1
*: The previous value is maintained.
79
CHAPTER 5 CLOCK AND RESET
80
CHAPTER 6
LOW-POWER CONTROL CIRCUIT
This chapter explains the functions and operations of the low-power control circuits.
6.1 Outline of Low-Power Control Circuit
6.2 Registers
6.3 Low-Power Mode Operation
6.4 Intermittent CPU Operation
6.5 Switching Machine Clocks
6.6 Status Transition of Clock Selection
81
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
6.1
Outline of Low-Power Control Circuit
The MB90590 series supports various operation modes to help reduce the power
dissipation.
The operation modes include PLL clock mode, PLL sleep mode, watch mode, main
clock mode, main sleep mode, stop mode, and hardware standby mode. Modes other
than PLL clock mode are classified as low-power modes.
■ Outline of Lower-power Control Circuit
In main clock mode or main sleep mode, the main clock (OSC oscillation clock) is used. The
operation clock is generated by dividing the main clock by two, and the PLL clock (VCO
oscillation clock) is stopped.
In PLL sleep mode or main sleep mode, only the CPU operation clock is stopped. All other
clocks are in operation.
In watch mode, only the timebase timer is in operation.In stop mode or hardware standby mode,
oscillation is stopped. The data can be maintained at the lowest power consumption possible.
The intermittent CPU operation function is used to intermittently enable the clock supplied to the
CPU when a register, internal memory, or internal resource is accessed. CPU execution is
slowed while high-speed clock is supplied to the internal resources, enabling processing at lowpower-consumption.
The oscillation stabilization wait time for the main clock upon release of stop or hardware
standby mode can be set by the WS1 and WS0 bits.
Note:
In attempting to switch the clock mode, do not attempt to switch to another clock mode or lowpower-consumption mode until the first switching is completed. The MCM bit of the clock selection
register (CKSCR) indicates that switching is completed. If the mode is switched to another clock
mode or low-power-consumption mode before completion of switching, the mode may not be
switched.
82
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
■ Block Diagram
Figure 6.1-1 Low-power Control Circuit and Clock Generator
CKSCR
MCM
MCS
Main clock
(OSC oscillation)
PLL multiplication
circuit
1
2
3
4
1/2
CPU clock
generation
CKSCR
CS1
CPU clock
CPU clock selector
0/9/17/33 intermittent
cycle selection
CS0
LPMCR
CG1
CG0
Intermittent CPU
operation function
Cycle count selection
circuit
Peripheral clock
generation
LPMCR
F2MC-16LX bus
SLP
STP
Standby control circuit
Peripheral
clock
HST
RST Release activation
HST pin
Interrupt
request or RST
CKSCR
WS1
WS0
Oscillation
stabilization
wait time
selector
210
213
215
217*
Clock input
Timebase timer
Timebase
clock
212 214 216 219
LPMCR
SPL
LPMCR
RST
Pin high-impedance control
circuit
Internal reset
generation circuit
Pin HI-Z
RST pin
Internal RST
To watch-dog
timer
18
*: 2
at power-on
WDGRST
83
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
6.2
Registers
A low-power control circuit has the following two registers:
• Low-power mode control register
• Clock selection register
■ Low-Power Mode Control Register
Figure 6.2-1 Low-Power Mode Control Register
Low-power mode control register
bit
Address: 0000A0H
Read/write→
Initial value→
7
6
5
4
3
2
1
0
STP
(W)
(0)
SLP
(W)
(0)
SPL
(R/W)
(0)
RST
(W)
(1)
Reserved
CG1
(R/W)
(0)
CG0
(R/W)
(0)
Reserved
(-)
(1)
LPMCR
(-)
(0)
Clock selection register
bit
Address: 0000A1H
Read/write→
Initial value→
84
15
14
13
12
11
10
9
8
Reserved
MCM
(R)
(1)
WS1
(R/W)
(1)
WS0
(R/W)
(1)
Reserved
MCS
(R/W)
(1)
CS1
(R/W)
(0)
CS0
(R/W)
(0)
(-)
(1)
(-)
(1)
CKSCR
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
6.2.1
Low-Power Mode Control Register (LPMCR)
In association with the clock selection register, the low-power mode control register
sets various operation modes to reduce power consumption.
■ Low-Power Mode Control Register (LPMCR)
Figure 6.2-2 Low-Power Mode Control Register (LPMCR)
bit
Address: 0000A0H
Read/write→
Initial value→
7
6
5
4
3
2
1
0
STP
(W)
(0)
SLP
(W)
(0)
SPL
(R/W)
(0)
RST
(W)
(1)
Reserved
CG1
(R/W)
(0)
CG0
(R/W)
(0)
Reserved
(-)
(1)
LPMCR
(-)
(0)
[bit 7] STP
Writing "1" to this bit starts the watch mode (CKSCR.MCS=0) or stop mode
(CKSCR.MCS=1). Writing "0" performs no operation. This bit is cleared to "0" upon a reset,
watch mode release, or stop mode release. This is a write-only bit. "0" is always read from
this bit.
[bit 6] SLP
Writing "1" to this bit starts sleep mode. Writing "0" performs no operation. This bit is cleared
to "0" upon a reset, clock release, or stop release.
Writing "1" to the STP and SLP bits simultaneously starts clock or stop mode. This is a writeonly bit. "0" is always read from this bit.
[bit 5] SPL
When "0" is written to this bit, the external pin level in watch mode or stop mode is
maintained. When "1" is written to this bit, the external pin in clock or stop mode is set to high
impedance. This bit is cleared to "0" upon a reset. This bit is readable and writable.
It is important to note that when SPL is set to "0" and the microcontroller is in the stop mode
or the watch mode (STP=1), all inputs must be provided with stable digital values. Otherwise
it results in current consumption at the input buffers. (A/D analog inputs are exception.)
Generally it is recommended to set the SPL bit to "1" when the microcontroller is in the stop
mode or the watch mode in order to disable all input buffers.
[bit 4] RST
Writing "0" to this bit generates internal reset signals for three machine cycles. Writing "1"
performs no operation. "1" is always read from this bit.
[bit 3] Reserved
This bit must be set to "1".
85
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
[bit 2, bit 1] CG1 and CG0
These bits are used to set the clock pause cycle count during intermittent CPU operation.
These bits are initialized to "00" upon a reset by power-on, hardware standby, or watch-dog.
These bits are not initialized by any other type of reset. These bits are readable and writable.
The intermittent CPU operation function pauses the clock to the CPU when a register,
internal memory, or internal resource is accessed, thus delaying the activation of the internal
bus cycle. CPU execution is slowed while high-speed clock is supplied to an internal
resource, enabling processing at low-power-consumption.
Table 6.2-1 CG Bit Setting
CG1
CG0
CPU clock pause cycle count
0
0
0 cycle (CPU clock = Resource clock)
0
1
9 cycles (CPU clock: Resource clock = 1:3 to 4 approx.)
1
0
17 cycles (CPU clock: Resource clock = 1:5 to 6 approx.)
1
1
33 cycles (CPU clock: Resource clock = 1:9 to 10 approx.)
[bit 0] Reserved
This bit must be set to "0".
Note:
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop
mode or watch mode, disable the output of peripheral functions, and set the STP bit of the lowpower mode control register (LPMCR) to "1".
This applies to the following pins:
P06/OUT0, P07/OUT1, P10/OUT2, P11/OUT3, P12/OUT4, P13/OUT5, P15/TX1, P16/SG0, P17/
SGA, P34/SOT0, and P35/SCK0
86
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
6.2.2
Clock Selection Register (CKSCR)
The clock selection register sets and controls the CPU machine clock, and sets the
oscillation stabilization wait time when power is turned on or oscillation is restored.
■ Clock Selection Register (CKSCR)
Figure 6.2-3 Clock Selection Register (CKSCR)
bit
Address: 0000A1H
Read/write→
Initial value→
15
14
13
12
11
10
9
8
Reserved
MCM
(R)
(1)
WS1
(R/W)
(1)
WS0
(R/W)
(1)
Reserved
MCS
(R/W)
(1)
CS1
(R/W)
(0)
CS0
(R/W)
(0)
(-)
(1)
(-)
(1)
CKSCR
[bit 14] MCM
This bit indicates whether the main clock or PLL clock is selected as the machine clock. "0"
indicates that the PLL clock is selected, and "1" indicates that the main clock is selected.
When MCS=0 and MCM=1, the system is waiting for the PLL clock oscillation to stabilize.
The PLL clock oscillation stabilization wait time is fixed to 213 main clock cycles.
Writing this bit has no effect on operation.
[bit 13, bit 12] WS1 and WS0
These bits are used to set the main clock oscillation stabilization wait time upon release of
stop or hardware standby mode.
These bits are initialized to "11" upon a power-on reset. These bits are not initialized by any
other type of reset. These bits are readable and writable.
Table 6.2-2 WS Bit Setting
WS1
WS0
Oscillation stabilization wait time (at 4 MHz source oscillation)
0
0
Approx. 256µs (210 counts of source oscillation)
0
1
Approx. 2.05 ms (213 counts of source oscillation)
1
0
Approx. 8.19 ms (215 counts of source oscillation)
1
1
Approx. 32.77 ms (217 counts of source oscillation)
Note:
Approx. 65.54ms (218 counts of source oscillation) at power-on.
[bit 11] Reserved
This bit must be set to "1".
87
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
[bit 10] MCS
This bit is used to select the main clock or PLL clock as the machine clock. Writing "0"
selects the PLL clock and writing "1" selects the main clock. When this bit is updated from
"1" to "0", the PLL clock oscillation stabilization wait period is created by automatically
clearing the timebase timer. The oscillation stabilization wait time for the PLL clock is fixed to
213 main clock cycles. (The oscillation wait time is about 2 ms at 4 MHz source oscillation.)
When the main clock is selected, the operation clock is generated by dividing the main clock
by two. (The operation clock is 2 MHz at 4 MHz source oscillation.)
This bit is initialized to "1" by the power-on reset, hardware standby, or watch-dog reset. But
it is not initialized by the external reset from the RST pin or by the software reset (the RST bit
in the LPMCR register).
Note:
When updating the MCS bit from "1" to "0", ensure that the timebase timer interrupt is masked by
the TBIE bit or the ILM bit of the CPU.
[bit 9, bit 8] CS1 and CS0
These bits are used to select the multiplication factor of the PLL clock.
These bits are initialized to "00" upon a power-on reset. These bits are not initialized by any
other type of reset.
Write is disabled when "0" is written to the MCS bit. To update the CS bit, set "1" in the MCS
bit (to start main clock mode).
These bits are readable and writable.
Table 6.2-3 CS Bit Setting
CS1
CS0
Machine clock (at 4 MHz source oscillation)
0
0
4 MHz (Operation frequency = OSC oscillation frequency)
0
1
8 MHz (Operation frequency = OSC oscillation frequency × 2)
1
0
12 MHz (Operation frequency = OSC oscillation frequency × 3)
1
1
16 MHz (Operation frequency = OSC oscillation frequency × 4)
Note:
When the operating voltage is 5 V, the OSC source oscillation can be between 3 MHz and 5 MHz.
When an external clock source is used, its frequency can be between 3MHz and 16MHz. Since the
highest operating frequency for the CPU and peripheral resource circuits is 16 MHz, however,
normal operation is not guaranteed if a multiplication factor resulting in a higher frequency than 16
MHz is specified. For example, if the external clock frequency is 16 MHz, only 1 can be specified as
the multiplication factor.
The lowest operating frequency of the VCO oscillation is 4 MHz, and an oscillation below 4 MHz
must not be specified.
88
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
6.3
Low-Power Mode Operation
Table 6.3-1 lists the chip status in each operation mode.
■ Low-Power Mode Operation
Table 6.3-1 Low-Power Mode Status
Transition
condition
Oscillation &
T.B.T
PLL
CPU
Watch Timer
Other
Peripheral
Pin
Main sleep
MCS=1
SLP=1
Operating
Stopped
Stopped
Operating
Operating
Operating
External Reset
Interrupt
PLL sleep
MCS=0
SLP=1
Operating
Operating
Stopped
Operating
Operating
Operating
External Reset
Interrupt
Watch
(SPL=0)
MCS=0
STP=1
Operating
Stopped
Stopped
Operating
Stopped
Held *
External Reset
External Interrupt
Watch
(SPL=1)
MCS=0
STP=1
Operating
Stopped
Stopped
Operating
Stopped
HI-Z
External Reset
External Interrupt
Stop
(SPL=0)
MCS=1
STP=1
Stopped
Stopped
Stopped
Stopped
Stopped
Held *
External Reset
External Interrupt
Stop
(SPL=1)
MCS=1
STP=1
Stopped
Stopped
Stopped
Stopped
Stopped
HI-Z
External Reset
External Interrupt
Hardware
standby
HST=L
Stopped
Stopped
Stopped
Stopped
Stopped
HI-Z
HST=H
Release method
*: When the SPL is set to "0" in the stop mode or the watch mode, all inputs must be provided with stable digital values. Otherwise it results in current
consumption at the input buffers. (A/D analog inputs are exception.)
Note:
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop
mode or watch mode, disable the output of peripheral functions, and set the STP bit of the lowpower mode control register (LPMCR) to 1.
This applies to the following pins:
P06/OUT0, P07/OUT1, P10/OUT2, P11/OUT3, P12/OUT4, P13/OUT5, P15/TX1, P16/SG0, P17/
SGA, P34/SOT0, and P35/SCK0
89
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
■ Note: Low-Power Mode Control Register Access
Writing data to the low-power mode control register starts low-power mode (stop or sleep
mode). In this case, use an instruction shown in Table 6.3-2. If any other instruction is used to
start low-power mode, malfunction may result. Any instruction can be used to control functions
other than transition of the low-power mode control register to low-power mode.
To write data to the low-power mode control register in word length, ensure that the data is
written to an even-number address. If low-power mode is started by writing data to an oddnumber address, malfunction may result.
Table 6.3-2 List of Instructions Used for Transition to Low-power Mode
MOV io,#imm8
MOV io,A
MOV RLi+dip8,A
MOVW io,#imm16
MOVW io,A
MOVW RLi+dip8,A
SETB io:bp
CLRB io:bp
MOV dir,#imm8
MOV dir,A
MOV eam,#imm8
MOV addr16,A
MOV eam,Ri
MOV eam,A
MOVW dir,#imm16
MOVW dir,A
MOVW eam,#imm16 MOVW eam,RWi
MOVW addr16,A
MOVW eam,A
SETB dir:bp
CLRB dir:bp
SETB addr16:bp
CLRB addr16:bp
■ Notes on the Transition to Low-Power Mode
To set a pin to high impedance when the pin is shared by a peripheral function and a port in
stop mode or watch mode, use the following procedure:
1. Disable the output of peripheral functions.
2. Set the SPL bit of the low-power mode control register (LPMCR) to "1", and set the STP bit
to "1".
90
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
6.3.1
Sleep Mode
In sleep mode, only the clock supplied to the CPU is stopped. As a result, the CPU
terminates while peripheral circuits keep operating.
■ Transition to Sleep Mode
The standby control circuit is set in sleep mode by writing "1" to the SLP bit and "0" to the STP
bit of the low-power mode control register. In sleep mode, only the clock supplied to the CPU is
stopped. The CPU stops, and the peripheral circuits continue operation.
If an interrupt request has been issued when "1" is written to the SLP bit, the standby control
circuit does not enter sleep mode. Therefore, the CPU executes the next instruction if the
interrupt cannot be accepted, or immediately branches to the interrupt processing routine if the
interrupt can be accepted.
In sleep mode, the values of special registers such as the accumulator and the internal RAM are
maintained.
■ Releasing Sleep Mode
The standby control circuit releases sleep mode in the event of a reset input or an interrupt. If
sleep mode is released by a reset, the reset status takes effect after sleep mode is released.
If a peripheral circuit or similar issues an interrupt request of a higher interrupt level than 7 in
sleep mode, the standby control circuit releases sleep mode. After sleep mode is released,
processing is handled as normal interrupt processing. The CPU executes interrupt processing if
the interrupt can be accepted according to the I flag, ILM, and the interrupt control register
(ICR). If the interrupt cannot be accepted, processing continues from the instruction following
the instruction that was being executed before the transition to sleep mode.
Note:
Usually, interrupt processing is started after the instruction following the instruction that was
executed during the transition to sleep mode.
91
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
6.3.2
Watch Mode
Watch mode stops operations other than the source oscillation, timebase timer, and
watch timer, resulting in almost all functions of the chip being stopped.
■ Transition to Watch Mode
The standby control circuit is set to watch mode when the MCS bit of the clock selection register
is "0" and "1" is written to the STP bit of the low-power mode control register. In watch mode, all
operations are stopped except for the source oscillation and timebase timer. Most functions of
the chip stop.
Using the STP bit of the low-power mode control register, the I/O pin may be maintained at the
immediately preceding status or at high impedance in watch mode.
If an interrupt request has been issued when "1" is written to the STP bit, the standby control
circuit does not enter watch mode.
In watch mode, the values of special registers such as the accumulator and the internal RAM
are maintained.
Note:
To set a pin to high impedance when the pin is shared by a peripheral function and a port in watch
mode, disable the output of peripheral functions, and set the STP bit of the low-power mode control
register (LPMCR) to "1".
This applies to the following pins:
P06/OUT0, P07/OUT1, P10/OUT2, P11/OUT3, P12/OUT4, P13/OUT5, P15/TX1, P16/SG0, P17/
SGA, P34/SOT0, and P35/SCK0
■ Releasing Watch Mode
The standby control circuit releases watch mode in the event of a reset input or an interrupt. If
watch mode is released by a reset, the reset status takes effect after watch mode is released.
To return from watch mode, the standby control circuit initially releases watch mode, then enters
the PLL clock oscillation stabilization wait state. The MCS bit is not cleared by an external reset,
so the reset sequence is performed using the main clock if the reset period is shorter than the
PLL clock oscillation stabilization wait period. The PLL clock oscillation stabilization wait time is
213 to 3 × 213 main clock cycles depending on the timebase timer status, because the timebase
timer is not cleared.
If a peripheral circuit or similar issues an interrupt request of a higher interrupt level than 7 in
watch mode, the standby control circuit releases watch mode. After the watch mode is released,
processing is handled as normal interrupt processing. The CPU executes interrupt processing if
the interrupt can be accepted according to the I flag, ILM, and the interrupt control register
(ICR). If the interrupt cannot be accepted, processing continues from the instruction following
the instruction that was being executed during transition to watch mode.
92
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
Notes:
• Usually, interrupt processing is started after the instruction following the instruction that was
being executed during the transition to watch mode.
• The standby control circuit enters PLL clock oscillation stabilization wait status when watch
mode is released. If the PLL clock is not used, write "1" to the MCS bit by an instruction
immediately following the reset or interrupt.
93
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
6.3.3
Stop Mode
Stop mode stops the source oscillation, resulting in all functions of the chip being
stopped. Data can be maintained at the lowest power consumption possible.
■ Transition to Stop Mode
The standby control circuit is set to stop mode when the MCS bit of the clock selection register
is "1" and "1" is written to the STP bit of the low-power mode control register. In stop mode, the
source oscillation is stopped and all functions of the chip are stopped. Therefore, data can be
maintained at the lowest power consumption possible.
Using the SPL bit of the LPMCR, the I/O pins can be maintained at the immediately preceding
status or at high impedance in stop mode. When the SPL bit is set to 0, all inputs must be
provided with stable digital values. Otherwise it results in current consumption at the input
buffers. (A/D analog inputs are exception.)
If an interrupt request has been issued when "1" is written to the STP bit, the standby control
circuit does not enter the stop mode.
In stop mode, the values of special registers such as the accumulator and the internal RAM are
maintained.
Note:
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop
mode, disable the output of peripheral functions, and set the STP bit of the low-power mode control
register (LPMCR) to "1".
This applies to the following pins:
P06/OUT0, P07/OUT1, P10/OUT2, P11/OUT3, P12/OUT4, P13/OUT5, P15/TX1, P16/SG0, P17/
SGA, P34/SOT0, and P35/SCK0
■ Releasing Stop Mode
The standby control circuit releases stop mode in the event of a reset input or an interrupt. If
stop mode is released by a reset, the reset status takes effect after stop mode is released.
If a peripheral circuit or similar issues an interrupt request of a higher interrupt level than 7 in
stop mode, the standby control circuit releases stop mode. After stop mode is released, the
processing is handled as normal interrupt processing after the main clock oscillation stabilization
wait time specified by the WS1 and WS0 bits of CKSCR. The CPU executes interrupt
processing if the interrupt can be accepted according to the I flag, ILM, and the interrupt control
register (ICR). If the interrupt cannot be accepted, processing continues from the instruction
following the instruction that was being executed during transition to stop mode.
94
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
■ Setting the Oscillation Stabilization Wait Time
Use the WS1 and WS0 bits to specify the oscillation stabilization wait time when stop mode or
hardware standby mode is released. Specify the oscillation stabilization wait time according to
the types and characteristics of the oscillator circuit and oscillator device connected to the X0
and X1 pins.
These bits are not initialized upon a reset, except for a power-on reset. Upon a power-on reset,
these bits are initialized to "11". Therefore, at power-on, the oscillation stabilization wait time is
about 217 counts of source oscillation.
Note:
Usually, interrupt processing is started after the instruction following the instruction that was being
executed during the transition to stop mode.
95
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
6.3.4
Hardware Standby Mode
In the hardware standby mode, oscillation is stopped and all I/O pins are set to high
impedance while the HST pin is at "L" level, regardless of other statuses (including
reset).
■ Transition to Hardware Standby Mode
The standby control circuit can be set in hardware standby mode from any status by setting the
HST pin at "L" level. In hardware standby mode, oscillation is stopped and all I/O pins are set to
high impedance while the HST pin is at "L" level, regardless of other status including reset.
In hardware standby mode, the internal RAM contents are maintained but the special registers
such as the accumulator are initialized.
■ Releasing Hardware Standby Mode
Hardware standby mode can be released only by the HST pin. When the HST pin is set at "H"
level, the standby control circuit releases hardware standby mode, enables the internal reset
signal, and enters oscillation stabilization wait status. After the oscillation stabilization wait time,
the standby control circuit releases the internal reset, and consequently the CPU starts
execution from the reset sequence.
■ Setting the Oscillation Stabilization Wait time
Use the WS1 and WS0 bits to specify the oscillation stabilization wait time when stop mode or
hardware standby mode is released. Specify the oscillation stabilization wait time according to
the types and characteristics of the oscillator circuit and oscillator device connected to the X0
and X1 pins.
These bits are not initialized upon a reset, except for a power-on reset. Upon a power-on reset,
these bits are initialized to "11". Therefore, at power-on, the oscillation stabilization wait time is
about 217 counts of source oscillation.
96
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
6.4
Intermittent CPU Operation
The intermittent CPU operation function pauses the clock supplied to the CPU when a
register, or internal memory (ROM, RAM, I/O, or resource) is accessed, delaying the
activation of the internal bus cycle. The CPU execution speed is decreased while a
high-speed clock is supplied to internal resources, thus enabling processing at lowpower-consumption.
■ Intermittent CPU Operation
Figure 6.4-1 is a diagram of intermittent CPU operation. For intermittent CPU operation, the
CG1 and CG0 bits are used to select the cycle count for clock pausing.
The external bus operation itself is performed using the same clock as that used for the
resources.
An instruction execution time using the intermittent CPU operation function can be obtained by
adding a compensation value to the ordinary execution time. The compensation value is
obtained by multiplying the number of accesses to a register, internal memory, or internal
resource by the cycle count for pausing.
Figure 6.4-1 Intermittent CPU Operation
Peripheral clock
CPU clock
Intermittent operation pause cycle
Internal bus activation cycle
Internal bus activation
97
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
6.5
Switching Machine Clocks
Writing to the MCS bit in the CKSCR register switches the machine clock from the
main clock to the PLL clock.
■ Switching between Main Clock and PLL Clock
Write data to the MCS bit of the CKSCR register to switch between the main clock and PLL
clock.
When the MCS bit is changed from "1" to "0", the PLL clock takes over the main clock after the
PLL clock oscillation stabilization wait time (213 machine clock cycles).
When the MCS bit is changed from "0" to "1", the main clock takes over the PLL clock when the
edges of the PLL and main clocks match (after about 1 to 8 PLL clock cycles).
Writing to the MCS bit does not change the machine clock immediately. To manipulate a
resource that depends on the machine clock, always reference the MCM bit beforehand to
check that the machine clock has been switched.
Note:
In attempting to switch the clock mode, do not attempt to switch to another clock mode or lowpower-consumption mode until the first switching is completed. The MCM bit of the clock selection
register (CKSCR) indicates that switching is completed. If the mode is switched to another clock
mode or low-power-consumption mode before completion of switching, the mode may not be
switched.
■ Initializing the Machine Clock
The MCS bit cannot be initialized by a reset that uses the RST external reset pin or the RST bit.
The MCS bit is initialized to "1" by any other reset.
98
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
6.6
Status Transition of Clock Selection
The oscillation stabilization wait time for the PLL clock is fixed at 213 main clock
cycles. (The oscillation wait time is about 2 ms at a source oscillation of 4 MHz.)
■ Status Transition of Clock Selection
Figure 6.6-1 is a diagram of status transition of clock selection.
Figure 6.6-1 Status Transition of Clock Selection
Power on
➀
Main
MCS = 1
MCM = 1
CS1/0=XXB
Main⇒PLLx
MCS = 0
MCM = 1
CS1/0=XXB
➆
➁
➂
➃
PLL⇒Main
MCS = 1
MCM = 0
CS1/0=00B
➅
PLL1
multiplication
MCS = 0
MCM = 0
CS1/0=00B
➆
PLL2⇒Main
➆
MCS = 1
➅
MCM = 0
CS1/0=01B
PLL2
multiplication
MCS = 0
MCM = 0
CS1/0=01B
➄
PLL3⇒Main
➆
MCS = 1
MCM = 0
➅
CS1/0=10B
PLL4⇒Main
MCS = 1
MCM = 0
➅
CS1/0=11B
➀
➁
➂
➃
➄
➅
➆
PLL3
multiplication
MCS = 0
MCM = 0
CS1/0=10B
PLL4
multiplication
MCS = 0
MCM = 0
CS1/0=11B
MCS bit clear
End of PLL clock oscillation stabilization wait & CS1/0=00B
End of PLL clock oscillation stabilization wait & CS1/0=01B
End of PLL clock oscillation stabilization wait & CS1/0=10B
End of PLL clock oscillation stabilization wait & CS1/0=11B
MCS bit set (including hardware standby and watch-dog reset)
Synchronization timing between PLL clock and main clock
99
CHAPTER 6 LOW-POWER CONTROL CIRCUIT
Note:
In attempting to switch the clock mode, do not attempt to switch to another clock mode or lowpower-consumption mode until the first switching is completed. The MCM bit of the clock selection
register (CKSCR) indicates that switching is completed. If the mode is switched to another clock
mode or low-power-consumption mode before completion of switching, the mode may not be
switched.
100
CHAPTER 7
MEMORY ACCESS MODES
This chapter explains the functions and operations of the memory access modes.
7.1 Outline of Memory Access Modes
7.2 Mode Pins
7.3 Mode Data
101
CHAPTER 7 MEMORY ACCESS MODES
7.1
Outline of Memory Access Modes
In the F2MC-16LX, the following two memory access modes are provided for each of
the access methods and access areas:
• Operation mode
• Bus mode
■ Memory Access Modes
Figure 7.1-1 Memory Access Modes
Operation mode
RUN
Flash programming
Bus mode
Single chip
For the MB90590 series, the external bus function is not supported. Therefor the following part
of this document is not fully supported. In user applications, please use the MB90590 series in
the single chip mode.
To set the MB90590 series into the single chip mode, the mode inputs (MD2 to MD0) should be
"011" and the most significant two bits of the mode data (M1 and M0) should be "00".
❍ Operation mode
Operation mode means the mode for controlling the device operation status. The operation
mode is specified by the MDx mode. By selecting an operation mode, normal operation, internal
test program activation, or special test function activation can be performed.
❍ Bus mode
Bus mode means the mode for controlling the internal ROM operation and external access
function. The bus mode is specified by the MDx mode setting pin and the Mx bit in mode data.
The MDx mode setting pin specifies the bus mode for reading the reset vector and mode data,
and the Mx bit in mode data specifies the bus mode for normal operation.
102
CHAPTER 7 MEMORY ACCESS MODES
7.2
Mode Pins
Table 7.2-1 describes the operations specified by combinations of the MD2 to MD0
external pins.
■ Mode pins
Table 7.2-1 Mode Pins and Modes
Mode pin setting
MD2
MD1
MD0
0
0
0
0
0
1
0
1
0
Mode name
Reset
vector
access area
External
data bus
width
Remarks
Internal
(Mode data)
Reset sequence and
later segments are
controlled based on
mode data.
-
Specification not allowed
0
1
1
Internal vector mode
1
0
0
1
0
1
1
1
0
Flash memory serial
programming *
-
-
1
1
1
Flash memory mode
-
-
Specification not allowed
Mode for use of a
parallel programmer
*: Data cannot be written only by setting the flash serial programming mode by mode pins.
The others must be set. For details, see "CHAPTER 25 EXAMPLES OF MB90F594A/MB90F594G/
MB90F591A/MB90F591G SERIAL PROGRAMMING CONNECTION".
103
CHAPTER 7 MEMORY ACCESS MODES
7.3
Mode Data
Mode data is stored at FFFFDFH of main memory and used for controlling the CPU
operation. This data is fetched during a reset sequence and stored in the mode
register inside the device. The mode register value can be changed only by a reset
sequence.
The setting of this register is valid after the reset sequence.
Always set the reserved bits to "0".
■ Mode Data
Figure 7.3-1 is a diagram of the setting of the bits.
Figure 7.3-1 Mode Data Structure
Mode data
7
6
5
4
3
2
1
0
M1
M0
0
0
0
0
0
0
Function extension bits (reserved area)
Bus mode setting bits
■ Bus Mode Setting Bits
These bits are used to specify the operation mode after the reset sequence is completed. Table
7.3-1 shows the relationship between the bits and the functions.
Table 7.3-1 Bus Mode Setting Bits and Functions
M1
M0
0
0
0
1
1
0
1
1
Function
Single chip mode
(Inhibited)
Figure 7.3-2 is a diagram of the correspondence between the access areas and physical
addresses for each bus mode.
104
CHAPTER 7 MEMORY ACCESS MODES
Figure 7.3-2 Access Areas and Physical Addresses in each Bus Mode
FFFFFF H
ROM
Devicedependent #1
FF0000 H
010000 H
ROM
004000 H
Devicedependent
002100 H
RAM
I/O
001100 H
RAM
000100 H
0000C0 H
000000 H
: No access
: Internal access
I/O
Single chip
Note:
"Device-dependent" means an address that is determined depending on the device.
■ Recommended Setting
Table 7.3-2 lists a sample recommended setting of mode pins and mode data.
Table 7.3-2 Sample Recommended Setting of Mode Pins and Mode Data
Sample setting
Single chip
MD2
MD1
MD0
M1
M0
0
1
1
0
0
Note:
For the MB90590 series devices with Flash memory, the mode data have predetermined values by
the hard-wired logic.
For more information, refer to Section "24.9 Reset Vector Address in Flash Memory".
105
CHAPTER 7 MEMORY ACCESS MODES
106
CHAPTER 8
I/O PORTS
This chapter explains the functions and operations of the I/O ports.
8.1 I/O Ports
8.2 I/O Port Registers
107
CHAPTER 8 I/O PORTS
8.1
I/O Ports
Each pin of the ports can be specified as input or output using the direction register if
the corresponding peripheral does not use the pin. When a pin is specified as input,
the logic level at the pin is read. When a pin is specified as output, the data register
value is read. The above also applies to a read operation for the read-modify-write
instructions.
■ I/O Ports
Only for Port 0, Port 1, Port 2 and Port 3, the corresponding bits of the Port Direction registers
should be set to "1" in order to enable peripheral signal outputs.
When a pin is used as an output of other peripheral function, the peripheral output value is read
regardless of the direction register value.
It is generally recommended that the read-modify-write instructions should not be used for
setting the data register prior to setting the port as an output. This is because the read-modifywrite instruction in this case results reading the logic level at the port rather than the register
value.
Figure 8.1-1 is a block diagram of the I/O ports.
Figure 8.1-1 I/O Port Block Diagram
Internal data bus
Data register read
Data register
Data register write
Direction register
Direction register write
Direction register read
108
Pin
CHAPTER 8 I/O PORTS
8.2
I/O Port Registers
There are three types of I/O port registers:
• Port data register
• Port direction register
• Analog input enable register
■ I/O Port Registers
Figure 8.2-1 shows the I/O port registers.
Figure 8.2-1 I/O Port Registers
bit
Address: 000000H
Address: 000001H
Address: 000002H
Address: 000003H
Address: 000004H
Address: 000005H
Address: 000006H
Address: 000007H
Address: 000008H
Address: 000009H
7
6
5
4
3
2
1
0
P07
P17
P27
P37
P47
P57
P67
P77
P87
-
P06
P16
P26
P36
P46
P56
P66
P76
P86
-
P05
P15
P25
P35
P45
P55
P65
P75
P85
P95
P04
P14
P24
P34
P44
P54
P64
P74
P84
P94
P03
P13
P23
P33
P43
P53
P63
P73
P83
P93
P02
P12
P22
P32
P42
P52
P62
P72
P82
P92
P01
P11
P21
P31
P41
P51
P61
P71
P81
P91
P00
P10
P20
P30
P40
P50
P60
P70
P80
P90
bit
Address: 000010H
Address: 000011H
Address: 000012H
Address: 000013H
Address: 000014H
Address: 000015H
Address: 000016H
Address: 000017H
Address: 000018H
Address: 000019H
7
6
5
4
3
2
1
0
D07
D17
D27
D37
D47
D57
D67
D77
D87
-
D06
D16
D26
D36
D46
D56
D66
D76
D86
-
D05
D15
D25
D35
D45
D55
D65
D75
D85
D95
D04
D14
D24
D34
D44
D54
D64
D74
D84
D94
D03
D13
D23
D33
D43
D53
D63
D73
D83
D93
D02
D12
D22
D32
D42
D52
D62
D72
D82
D92
D01
D11
D21
D31
D41
D51
D61
D71
D81
D91
D00
D10
D20
D30
D40
D50
D60
D70
D80
D90
Port data register (PDR0)
Port data register (PDR1)
Port data register (DDR2)
Port data register (PDR3)
Port data register (PDR4)
Port data register (PDR5)
Port data register (PDR6)
Port data register (PDR7)
Port data register (PDR8)
Port data register (PDR9)
Port direction register (DDR0)
Port direction register (DDR1)
Port direction register (DDR2)
Port direction register (DDR3)
Port direction register (DDR4)
Port direction register (DDR5)
Port direction register (DDR6)
Port direction register (DDR7)
Port direction register (DDR8)
Port direction register (DDR9)
bit
7
6
5
4
3
2
1
0
Address: 00001BH ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Analog input enable register (ADER)
109
CHAPTER 8 I/O PORTS
8.2.1
Port Data Register (PDR0 to PDR9)
Note that R/W for I/O ports differ from R/W for memory in the following points:
Input mode
Read: The level at the corresponding pin is read.
Write: Data is written to an output latch.
Output mode
Read: The data register latch value is read.
Write: Data is written to an output latch and output to the corresponding pin.
■ Port data Register (PDR0 to PDR9)
Figure 8.2-2 shows the port data registers.
Figure 8.2-2 Port Data Registers (PDR0 to PDR9)
PDR0bit
Address: 000000H
7
P07
6
P06
5
P05
4
P04
3
P03
2
P02
1
P01
0
P00
Initial value Access
XXXXXXXXB R/W
PDR1bit
Address: 000001H
7
P17
6
P16
5
P15
4
P14
3
P13
2
P12
1
P11
0
P10
XXXXXXXXB
R/W
PDR2bit
Address: 000002H
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
XXXXXXXXB
R/W
PDR3bit
Address: 000003H
7
P37
6
P36
5
P35
4
P34
3
P33
2
P32
1
P31
0
P30
XXXXXXXXB
R/W
PDR4bit
Address: 000004H
7
P47
6
P46
5
P45
4
P44
3
P43
2
P42
1
P41
0
P40
XXXXXXXXB
R/W
PDR5bit
Address: 000005H
7
6
5
4
3
2
1
0
P57
P56
P55
P54
P53
P52
P51
P50
XXXXXXXXB
R/W
PDR6bit
Address: 000006H
7
P67
6
P66
5
P65
4
P64
3
P63
2
P62
1
P61
0
P60
XXXXXXXXB
R/W
PDR7bit
Address: 000007H
7
P77
6
P76
5
P75
4
P74
3
P73
2
P72
1
P71
0
P70
XXXXXXXXB
R/W
PDR8bit
Address: 000008H
7
6
5
4
3
2
1
0
P87
P86
P85
P84
P83
P82
P81
P80
XXXXXXXXB
R/W
7
6
5
4
3
2
1
0
-
-
P95
P94
P93
P92
P91
P90
--XXXXXXB
R/W
PDR9bit
Address: 000009H
110
CHAPTER 8 I/O PORTS
8.2.2
Port Direction Register (DDR0 to DDR9)
When a pin is used as a port, the corresponding pin is controlled as described below:
0: Input mode
1: Output mode
■ Port Direction Register (DDR0 to DDR9)
Figure 8.2-3 shows the port direction registers.
Figure 8.2-3 Port Direction Registers (DDR0 to DDR9)
DDR0
bit
Address: 000010H
7
D07
6
D06
5
D05
4
D04
3
D03
2
D02
1
D01
0
D00
Initial value
00000000B
Access
R/W
DDR1
bit
Address: 000011H
7
D17
6
D16
5
D15
4
D14
3
D13
2
D12
1
D11
0
D10
00000000B
R/W
DDR2
bit
Address: 000012H
7
D27
6
D26
5
D25
4
D24
3
D23
2
D22
1
D21
0
D20
00000000B
R/W
DDR3
bit
Address: 000013H
7
D37
6
D36
5
D35
4
D34
3
D33
2
D32
1
D31
0
D30
00000000B
R/W
DDR4
bit
Address: 000014H
7
D47
6
D46
5
D45
4
D44
3
D43
2
D42
1
D41
0
D40
00000000B
R/W
DDR5
bit
Address: 000015H
7
D57
6
D56
5
D55
4
D54
3
D53
2
D52
1
D51
0
D50
00000000B
R/W
DDR6
bit
Address: 000016H
7
D67
6
D66
5
D65
4
D64
3
D63
2
D62
1
D61
0
D60
00000000B
R/W
DDR7
bit
Address: 000017H
7
D77
6
D76
5
D75
4
D74
3
D73
2
D72
1
D71
0
D70
00000000B
R/W
DDR8
bit
Address: 000018H
7
D87
6
D86
5
D85
4
D84
3
D83
2
D82
1
D81
0
D80
00000000B
R/W
DDR9
bit
Address: 000019H
7
-
6
-
5
D95
4
D94
3
D93
2
D92
1
D91
0
D90
--000000B
R/W
Note:
The Port Direction Registers for Ports 0 and 1 will stay undefined during Power-On reset and will
be initialized to 00H after the completion of Power-On reset. Therefore, the Port 0 and 1 outputs
become undefined during Power-On reset.
111
CHAPTER 8 I/O PORTS
8.2.3
Analog Input Enable Register (ADER)
This register controls the port 6 pins as described below:
0: Port input/output mode
1: Analog input mode
If an external pin is used as an analog input for the A/D converter, the corresponding
bit should be set to "1".
■ Analog Input Enable Register (ADER)
Figure 8.2-4 shows the analog input enable register.
Figure 8.2-4 Analog Input Enable Register (ADER)
bit
7
Address: 00001BH ADE7
6
5
4
3
2
1
0
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
Read/write→ (R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Initial value→
112
(1)
ADER
CHAPTER 9
TIMEBASE TIMER
This chapter explains the functions and operations of the timebase timer.
9.1 Outline of Timebase Timer
9.2 Timebase Timer Control Register (TBTC)
9.3 Operations of Timebase Timer
113
CHAPTER 9 TIMEBASE TIMER
9.1
Outline of Timebase Timer
The timebase timer consists of an 18-bit timebase counter and a control register. The
18-bit timebase counter divides the system clock. The timebase timer issues interrupts
at specified intervals based on carry signals of the timebase counter.
■ Outline of Timebase Timer
When the power is turned on, the timebase counter can be cleared to all zeroes by setting the
stop mode or by software (writing "0" to the TBR bit). The timebase counter is incremented
while the source oscillation is input.
The timebase counter can be used as a timer for supplying clock to the watch-dog timer or for
waiting for the oscillation to stabilize.
■ Block Diagram of Timebase Timer
Figure 9.1-1 shows a block diagram of the timebase timer.
Figure 9.1-1 Block Diagram of Timebase Timer
WTE
Output enable
WT1
WT0
Reset
control
2-bit
counter
Selector
Reset
Timebase counter
f/2
Power-on
reset
STOP
mode
1
1
1
1
1
1
1
1
2
11
12
13
14
15
16
17
2
Selector
1/210 to 1/217
WS1
114
2
2
2
TBOF
TBC1
WS0
2
Clear
control
TBR
TBC0
2
Selector
2
1
218
IRQ
TBOF
Clear
EI 2OS
Timebase division output
Oscillation stabilization wait completion signal
CHAPTER 9 TIMEBASE TIMER
9.2
Timebase Timer Control Register (TBTC)
The timebase timer control register controls interrupts of the timebase timer and can
clear the timebase counter.
■ Timebase Timer Control Register (TBTC)
Figure 9.2-1 Timebase Timer Control Register (TBTC)
bit
Address: 0000A9H
Read/write→
Initial value→
15
14
13
12
11
10
9
8
Reserved
(-)
(-)
(-)
(-)
TBIE
(R/W)
(0)
TBOF
(R/W)
(0)
TBR
(W)
(1)
TBC1
(R/W)
(0)
TBC0
(R/W)
(0)
(W)
(1)
TBTC
[bit 15] Reserved
This is a reserved bit. When writing data to this register, ensure that "1" is written to this bit.
[bit 12] TBIE
This bit is used to enable interval interrupts based on the timebase timer. Writing "1" to this
bit enables interrupts, and writing "0" disables interrupts. This bit is initialized to "0" upon a
reset. This bit is readable and writable.
[bit 11] TBOF
This is an interrupt request flag for the timebase timer. While the TBIE bit is "1", an interrupt
request is issued when "1" is written to TBOF. This bit is set to "1" for each interval specified
with the TBC1 and TBC0 bits.
This bit is cleared by writing "0", transition to stop or hardware standby mode, or a reset.
Writing "1" has no effect.
"1" is always read by a read-modify-write instruction.
[bit 10] TBR
This bit clears all bits of the timebase timer counter to "0".
Writing "0" clears the timebase counter.
Writing "1" has no effect.
"1" is always read from this bit.
115
CHAPTER 9 TIMEBASE TIMER
[bit 9, bit 8] TBC1 and TBC0
These bits are used to set the timebase timer interval.
Table 9.2-1 lists of selecting the timebase timer interval.
Table 9.2-1 Selecting the Timebase Timer Interval
116
TBC1
TBC0
Interval at 4 MHz source oscillation
0
0
1.024 ms
0
1
4.096 ms
1
0
16.384 ms
1
1
131.072 ms
CHAPTER 9 TIMEBASE TIMER
9.3
Operations of Timebase Timer
The timebase timer functions as a watch-dog timer clock source, timer for waiting for
the oscillation to stabilize, and interval timer for generating interrupts at specified
intervals.
■ Timebase Counter
The timebase counter consists of an 18-bit counter for a clock generated by dividing the source
oscillation input by two. This clock is used to generate the machine clock. While the source
oscillation is input, the timebase counter keeps counting. The timebase counter is cleared by a
power-on reset, transition to stop or hardware standby mode, or writing "0" to the TBR bit of the
TBTC register.
■ Interval Interrupt Function
Interrupts are generated at specified intervals according to the carry signals of the timebase
counter. The TBOF flag is set at the intervals specified with the TBC1 and TBC0 bits of the
TBTC register. The flag is written to reference to the time at which the timebase timer is cleared
last.
Upon transition to stop or hardware standby mode, the timebase timer is used as a timer for
waiting for the oscillation to stabilize upon recovery. Therefore, the TBOF flag is immediately
cleared upon mode transition.
117
CHAPTER 9 TIMEBASE TIMER
118
CHAPTER 10
WATCH-DOG TIMER
This chapter explains the functions and operations of the watch-dog timer.
10.1 Outline of Watch-Dog Timer
10.2 Watch-Dog Timer Operation
119
CHAPTER 10 WATCH-DOG TIMER
10.1 Outline of Watch-Dog Timer
The watch-dog timer consists of a 2-bit watch-dog counter, control register, and
watch-dog reset controller. The 2-bit watch-dog counter uses the carry signals of an
18-bit timebase counter as a clock source.
■ Watch-dog Timer Block Diagram
Figure 10.1-1 is a diagram of the configuration of the watch-dog timer.
Figure 10.1-1 Watch-dog Timer Block Diagram
WTE
Output enable
WT1
WT0
2-bit
counter
Selector
Reset
control
Reset
Timebase counter
f/2
Power-on
reset
STOP
mode
1
1
1
1
1
1
1
1
2
11
12
13
14
15
16
17
2
2
2
Clear
control
2
2
2
TBOF
Selector
2
1
218
IRQ
TBOF
TBR
TBC1
TBC0
WS1
WS0
120
1/210 to 1/217
Selector
Clear
EI 2OS
Timebase division output
Oscillation stabilization wait completion signal
CHAPTER 10 WATCH-DOG TIMER
■ Watch-dog Timer Control Register (WDTC)
Figure 10.1-2 Watch-dog Timer Control Register (WDTC)
bit
7
6
5
4
Address: 0000A8H PONR STBR WRST ERST
Read/write→
(R)
(R)
(R)
(R)
Initial value→
(X)
(X)
(X)
(X)
3
2
1
0
SRST
(R)
(X)
WTE
(W)
(1)
WT1
(W)
(1)
WT0
(W)
(1)
WDTC
[bit 7 to bit 3] PONR, STBR, WRST, ERST, and SRST
These flags indicate the reset causes. The flags are set upon a reset as described in Table
10.1-1.
All bits are cleared to "0" after the WDTC register is read. These bits are read-only bits. For
details, see Section "5.2 Reset Cause Occurrence".
Table 10.1-1 Reset Cause Registers
Reset cause
PONR
STBR
WRST
ERST
SRST
Power-on
1
-
-
-
-
Hardware standby
*
1
*
*
*
Watch-dog timer
*
*
1
*
*
External pin
*
*
*
1
*
RST bit
*
*
*
*
1
*: The previous value is maintained.
[bit 2] WTE
While the watch-dog timer is stopped, writing "0" to this bit activates the watch-dog timer.
Subsequently, writing "0" clears the watch-dog timer counter. Writing "1" has no effect.
The watch-dog timer is stopped by power-on, hardware standby, or reset by watch-dog
timer. "1" is always read from this bit.
121
CHAPTER 10 WATCH-DOG TIMER
[bit 1, bit 0] WT1 and WT0
These bits are used to select the watch-dog timer interval. Only the data items written during
watch-dog timer activation are valid. Data items that are written outside watch-dog timer
activation are ignored. Table 10.1-2 lists the interval settings.
These bits are write-only bits.
Table 10.1-2 Watch-dog Timer Interval Selection Bit
WT1
WT0
Interval (at a source oscillation of 4
MHz)
Minimum
Maximum
Main clock cycle
count
0
0
approx. 3.58 ms
approx. 4.61 ms
214 plus or minus 211
cycles
0
1
approx. 14.33 ms
approx. 18.43 ms
216 plus or minus 213
cycles
1
0
approx. 57.23 ms
approx. 73.73 ms
218 plus or minus 215
cycles
1
1
approx. 458.7 ms
approx. 589.82 ms
221 plus or minus 218
cycles
Note:
The interval becomes the maximum when the timebase counter is not reset during watchdog timer operation.
122
CHAPTER 10 WATCH-DOG TIMER
10.2 Watch-Dog Timer Operation
The watch-dog timer function enables detection of program malfunction.
If the watch-dog timer is not accessed within the specified time due to, for example, a
program malfunction, the watch-dog timer resets the system.
■ Activation
The watch-dog timer is activated by writing "0" to the WTE bit of the WDTC register while the
watch-dog timer is stopped. At the same time, the WT1 and WT0 bits are used to set the watchdog timer reset interval. Only the interval setting specified during activation is valid.
■ Watch-dog Counter
Once the watch-dog timer is activated, the watch-dog timer counter must be periodically cleared
within the program. Writing "0" to the WTE bit of the WDTC register clears the watch-dog
counter. The watch-dog counter consists of a two-bit counter which uses the carry signals of the
timebase counter as a clock source. Therefore, the watch-dog reset time may become shorter
than the setting if the timebase counter is cleared.
The watch-dog counter is cleared not only by writing to the WTE bit but also by a reset and
transition to the sleep or stop mode. (The watch-dog counter is not cleared by transition to
watch mode.)
Figure 10.2-1 is a diagram of the watch-dog timer operation.
Figure 10.2-1 Watch-dog Timer Operation
Timebase
Watch-dog
00
01
10
00
01
10
11
00
WTE write
Watch-dog activation
Watch-dog clear
Watch-dog reset
■ Watch-dog Stop
Once activated, the watch-dog timer is initialized and stopped only by power-on, hardware
standby, or reset by watch-dog. Reset by an external pin or software merely clears the watchdog counter without stopping the watch-dog function.
123
CHAPTER 10 WATCH-DOG TIMER
124
CHAPTER 11
16-BIT I/O TIMER
This chapter explains the functions and operations of the 16-bit I/O timer.
11.1 Outline of 16-Bit I/O Timer
11.2 16-Bit I/O Timer Registers
11.3 16-Bit Free-running Timer
11.4 Output Compare
11.5 Input Capture
125
CHAPTER 11 16-BIT I/O TIMER
11.1 Outline of 16-Bit I/O Timer
The MB90590 series contains one 16-bit free-running timer module, three output
compare modules, and three input capture modules and supports six input channels
and six output channels. The following sections only describes the 16-bit free-running
timer, Output Compare 0/1 and Input Capture 0/1.
The remaining modules have the identical functions and the register addresses should
be found in "APPENDIX A I/O Maps".
■ 16-bit Free-running Timer
The 16-bit free-running timer consists of a 16-bit up counter, control register, and prescaler. The
values output from this timer counter are used as the base timer for input capture and output
compare.
❍ Four counter clocks are available.
Internal clock: φ /4, φ/16, φ/64, φ/256
❍ An interrupt can be generated upon a counter overflow or a match with compare register
0.
❍ The counter value can be initialized to "0000H" upon a reset, software clear, or match with
compare register 0.
■ Output Compare (2 Channels per One Module)
The output compare module consists of two 16-bit compare registers, compare output latch, and
control register.
When the 16-bit free-running timer value matches the compare register value, the output level is
reversed and an interrupt can be issued.
❍ The two compare registers can be used independently.
Output pins and interrupt flags corresponding to each compare register.
❍ Output pins can be controlled based on pairs of the two compare registers.
Output pins can be inverted by using the two compare registers.
❍ Initial values for output pins can be set.
❍ Interrupts can be generated upon a compare match.
126
CHAPTER 11 16-BIT I/O TIMER
■ Input Capture (2 Channels per one Module)
The input capture module consists of two 16-bit capture registers and control registers
corresponding to two independent external input pins. The 16-bit free-running timer value can
be stored in the capture register and an interrupt is issued simultaneously upon detection of an
edge of a signal input from an external input pin.
❍ The detection edge of an external input signal can be specified.
Rising, falling, or both edges can be selected.
❍ Two input channels can operate independently.
❍ An interrupt can be issued upon a valid edge of an external input signal.
The intelligent I/O service can be activated upon an input capture interrupt.
■ Block Diagram of 16-bit I/O Timer
Figure 11.1-1 shows a block diagram of the 16-bit I/O timer.
Figure 11.1-1 Block Diagram of 16-bit I/O Timer
Control logic
To each block
Interrupt
16-bit free-running timer
16-bit timer
Bus
Clear
Output compare 0
Compare register 0
T
Q
OUT0
T
Q
OUT1
Edge selection
IN0
Edge selection
IN1
Output compare 1
Compare register 1
Input capture 0
Capture register 0
Input capture 1
Capture register 1
127
CHAPTER 11 16-BIT I/O TIMER
11.2 16-Bit I/O Timer Registers
The 16-bit I/O timer has the following three registers:
• 16-bit free-running timer register
• 16-bit output compare register
• 16-bit input capture register
■ 16-bit Free-running Timer
Figure 11.2-1 16-bit Free-running Timer
15
0
001944H
TCDT
Timer data register
TCCS
00006EH
Control status register
■ 16-bit Output Compare
Figure 11.2-2 16-bit Output Compare
15
0
001930H
001932H
OCCP0/OCCP1
000058H
OCS1
Compare register
OCS0
Control status register
■ 16-bit Input Capture
Figure 11.2-3 16-bit Input Capture
15
001920H
001922H
000054H
128
0
IPCP0/IPCP1
ICS0/ICS1
Capture register
Control status register
CHAPTER 11 16-BIT I/O TIMER
11.3 16-Bit Free-running Timer
The 16-bit free-running timer consists of a 16-bit up counter and a control status
register. The count values of this timer are used as the base timer for the output
compares and input captures.
• Four counter clock frequencies are available.
• An interrupt can be generated upon a counter value overflow.
• The counter value can be initialized upon a match with compare register 0,
depending on setting the mode.
■ 16-bit Free-running Timer Block Diagram
Figure 11.3-1 16-bit Free-running Timer Block Diagram
Interrupt request
IVF
IVFE STOP MODE CLR CLK1 CLK0
φ
Divider
Comparator 0
Bus
16-bit free-running timer
Clock
Count value output
T15
to
T00
129
CHAPTER 11 16-BIT I/O TIMER
11.3.1 Timer Counter Data Register (TCDT)
The timer counter data register (TCDT) can read the count value of the 16-bit freerunning timer. The count value is cleared to "0000" upon a reset. The timer value can
be set by writing a value to this register. However, ensure that the value is written
while the operation is stopped (STOP=1).
The data register must be accessed by the word access instructions.
■ Timer Counter Data Register (TCDT)
Figure 11.3-2 Timer Counter Data Register (TCDT)
bit
15
Address: 001945H
T15
Read/write→ (R/W)
Initial value→
(0)
14
13
12
11
10
9
8
T14
(R/W)
(0)
T13
(R/W)
(0)
T12
(R/W)
(0)
T11
(R/W)
(0)
T10
(R/W)
(0)
T9
(R/W)
(0)
T8
(R/W)
(0)
bit
7
Address: 001944H
T07
Read/write→ (R/W)
Initial value→
(0)
6
5
4
3
2
1
0
T06
(R/W)
(0)
T05
(R/W)
(0)
T04
(R/W)
(0)
T03
(R/W)
(0)
T02
(R/W)
(0)
T01
(R/W)
(0)
T00
(R/W)
(0)
TCDT
TCDT
The 16-bit free-running timer is initialized upon the following factors:
130
•
Reset
•
Clear bit (CLR) of control status register
•
A match between compare register 0 and the timer counter value. (This mode setting is
required.)
CHAPTER 11 16-BIT I/O TIMER
11.3.2 Timer Counter Control Status Register (TCCS)
The timer counter control status register (TCCS) sets the operation mode of the 16-bit
free-running timer, starts and stops the 16-bit free-running timer, and controls
interrupts.
■ Timer Counter Control Status Register (TCCS)
Figure 11.3-3 Timer Counter Control Status Register (TCCS)
bit
7
6
Address: 00006EH
Reserved
IVF
Read/write→ (R/W) (R/W)
Initial value→
(0)
(0)
5
IVFE
(R/W)
(0)
4
3
2
STOP MODE CLR
(R/W) (R/W) (R/W)
(0)
(0)
(0)
1
0
CLK1
(R/W)
(0)
CLK0
(R/W)
(0)
TCCS
[bit 7] Reserved bit
Always write "0" to this bit.
[bit 6] IVF
This bit is an interrupt request flag of the 16-bit free-running timer.
If the 16-bit free-running timer overflows, or if the counter is cleared by a match with
compare register 0 by mode setting, "1" is set to this bit.
An interrupt is issued if the interrupt request enable bit (bit 5: IVFE) is set.
This bit is cleared by writing "0". Writing "1" has no effect.
"1" is always read by a read-modify-write instruction.
0
No interrupt request (initial value)
1
Interrupt request
[bit 5] IVFE
IVFE is an interrupt enable bit of the 16-bit free-running timer. While this bit is "1", an
interrupt is issued if "1" is set to the interrupt flag (bit 6: IVF).
0
Interrupt disabled (initial value)
1
Interrupt enabled
131
CHAPTER 11 16-BIT I/O TIMER
[bit 4] STOP
The STOP bit is used to stop the 16-bit free-running timer.
Writing "1" to this bit stops counting of 16-bit free-running timer. Writing "0" starts counting.
0
Counter enabled (operation) (initial value)
1
Counter disabled (stop)
Note:
The output compare operation stops when the 16-bit free-running timer stops.
[bit 3] MODE
The MODE bit is used to set the condition to initialize of the 16-bit free-running timer.
When "0" is set, the counter value can be initialized by RESET or a clear bit (bit 2: CLR).
When "1" is set, the counter value can be initialized by a match with the value of compare
register 0 of output compare in addition to RESET and a clear bit (bit 2: CLR).
0
Initialization by reset or clear bit (initial value)
1
Initialization by reset, clear bit, or compare register 0
Note:
The clear bit and the match with compare register initializes the timer when the timer value
changes.
[bit 2] CLR
The CLR bit initializes the operating 16-bit free-running timer value to "0000".
When "1" is written, the counter value is initialized to "0000". Writing "0" has no effect. "0" is
always read from this bit. The counter value is initialized when the count value changes.
0
No effect (initial value)
1
The counter value is initialized to "0000".
Note:
To initialize the counter value while the 16-bit free-running timer is stopped, write "0000" to the data
register.
132
CHAPTER 11 16-BIT I/O TIMER
[bit 1, bit 0] CLK1 and CLK0
These bits are used to select the count clock for the 16-bit free-running timer. The clock is
updated immediately after a value is written to these bits. Therefore, ensure that the output
compare and input capture operations are stopped before a value is written to these bits.
CLK1
CLK0
Count clock
division ratio
φ=16 MHz
φ=8 MHz
φ=4 MHz
φ=1 MHz
0
0
φ/4
0.25 µs
0.5 µs
1 µs
4 µs
0
1
φ/16
1 µs
2 µs
4 µs
16 µs
1
0
φ/64
4 µs
8 µs
16 µs
64 µs
1
1
φ/256
16 µs
32 µs
64 µs
256 µs
φ = Machine clock
133
CHAPTER 11 16-BIT I/O TIMER
11.3.3 16-bit Free-running Timer Operation
The 16-bit free-running timer starts counting from counter value "0000" after the reset
is released. The counter value is used as the base time for the 16-bit output compare
and 16-bit input capture operations.
■ 16-bit Free-running Timer Operation
The counter value is cleared in the following conditions:
•
When an overflow occurs.
•
When a compare match with the value of output compare register 0 occurs. (The mode
setting is required.)
•
When "1" is written to the CLR bit of the TCCS register during operation.
•
When "0000" is written to the TCDC register during stopped.
•
At reset.
An interrupt can be generated when an overflow occurs or when the counter values correspond
to ones of the output compare register 0. (Compare match interrupts can be used only in setting
the mode.)
Figure 11.3-4 Clearing the Counter by an Overflow
Counter value
FFFF H
Overflow
BFFF H
7FFF H
3FFF H
0000 H
Reset
Interrupt
134
Time
CHAPTER 11 16-BIT I/O TIMER
■ Clearing the Counter upon a Match with Output Compare Resister 0
Figure 11.3-5 Clearing the Counter upon a Match with Output Compare Register 0
Counter value
FFFF H
Match
BFFF H
Match
7FFF H
3FFF H
Time
0000 H
Reset
Compare
register value
Interrupt
BFFFH
■ 16-bit Free-running Timer Timing
The counter can be cleared upon a reset, software clear, or a match with the compare register
0. By a reset or software clear, the counter is immediately cleared. By a match with compare
register 0, the counter is cleared in synchronization with the count timing.
Figure 11.3-6 16-bit Free-Running Timer Clear Timing (Match with the Compare Register 0)
φ
N
Compare
register value
Compare match
Counter value
N
0000
135
CHAPTER 11 16-BIT I/O TIMER
11.4 Output Compare
The output compare module consists of two 16-bit compare registers, two compare
output pins, and control registers. If the value written to the compare register of this
module matches the 16-bit free-running timer value, the output level of the pin can be
inverted and an interrupt can be issued.
■ Output Compare
•
Two compare registers exist that can be used independently. Depending on the setting, the
two compare registers can be used to control pin outputs.
•
The initial value for the pin output can be specified.
•
An interrupt can be issued by the compare match.
■ Output Compare Block Diagram
Figure 11.4-1 shows a block diagram of output compare.
Figure 11.4-1 Output Compare Block Diagram
16-bit timer counter value (T15 to T00)
T
Compare control
Q
OTE0
OUT0
OTE1
OUT1
Compare register 0
CMOD
16-bit timer counter value (T15 to T00)
Bus
T
Compare control
Q
Compare register 1
ICP1
Controller
Control blocks
136
ICP0 ICE1 ICE0
Compare 1
interrupt
Compare 0
interrupt
CHAPTER 11 16-BIT I/O TIMER
11.4.1 Output Compare Register
These 16-bit compare registers are compared with the 16-bit free-running timer. Since
the initial register values are undefined, set appropriate value before enabling the
operation. These registers must be accessed by the word access instructions. When
the value of the register matches that of the 16-bit free-running timer, a compare signal
is generated and the output compare interrupt flag is set. If output is enabled, the
output level corresponding to the compare register is inverted.
■ Output Compare Register
Figure 11.4-2 Output Compare Register
bit
15
C15
Address: 001931H
001933H
Read/write→ (R/W)
Initial value→
(X)
bit
7
C07
Address: 001930H
001932H
Read/write→ (R/W)
Initial value→
(X)
14
C14
13
C13
12
C12
11
C11
10
C10
9
C09
8
C08
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
6
C06
5
C05
4
C04
3
C03
2
C02
1
C01
0
C00
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
OCCP0/
OCCP1
OCCP0/
OCCP1
137
CHAPTER 11 16-BIT I/O TIMER
11.4.2 Control Status Register of Output Compare (OCS0/1)
The control status register (OCS0/1) sets the operation mode of output compare, starts
and stops output compare, controls interrupts, and sets the external output pins.
■ Control Status Register of Output Compare (OCS0/1)
Figure 11.4-3 Control Status Register of Output Compare (OCS0/1)
bit
Address: 000059H
Read/write→
Initial value→
15
(-)
(-)
bit
7
Address: 000058H
ICP1
Read/write→ (R/W)
Initial value→
(0)
14
(-)
(-)
13
(-)
(-)
12
11
CMOD OTE1
(R/W) (R/W)
(0)
(0)
10
OTE0
(R/W)
(0)
9
OTD1
(R/W)
(0)
8
OTD0
(R/W)
(0)
6
5
4
3
2
1
0
ICP0
(R/W)
(0)
ICE1
(R/W)
(0)
ICE0
(R/W)
(0)
(-)
(-)
(-)
(-)
CST1
(R/W)
(0)
CST0
(R/W)
(0)
OCS1
OCS0
[bit 15 to bit 13] Unused bits
[bit 12] CMOD
CMOD is used to switch the pin output level reverse operation mode upon a compare match
while pin output is enabled (OTE1=1 or OTE0=1).
•
•
138
When CMOD=0 (initial value), the output level of the pin corresponding to the compare
register is inverted.
•
OUT0: The level is inverted upon a match with compare register 0.
•
OUT1: The level is inverted upon a match with compare register 1.
When CMOD=1, the output level is inverted for the compare register 0 in the same manner
as for CMOD=0. The output level of the pin corresponding to compare register 1 (OUT1),
however, is inverted upon both match with compare register 0 and 1. If compare registers 0
and 1 have the same value, the same operation as with a single compare register is
performed.
•
OUT0: The level is inverted upon a match with compare register 0.
•
OUT1: The level is inverted upon both match with compare register 0 and 1.
CHAPTER 11 16-BIT I/O TIMER
[bit 11, bit 10] OTE1 and OTE0
These bits are used to enable the output compare output pins. The initial value for these bits
is "0".
0
General-purpose port (initial value)
1
Output compare pin output
Note:
OTE1: Corresponds to output compare 1 (OUT1).
OTE0: Corresponds to output compare 0 (OUT0).
When they are specified as outputs, the corresponding bits of the Port Direction registers
should also be set to "1".
[bit 9, bit 8] OTD1 and OTD0
These bits are used to change the pin output level when the output compare pin output is
enabled. The initial value of the compare pin output is "0". Ensure that the compare
operation is stopped before a value is written. When read, these bits indicate the output
compare pin output value.
0
Sets "0" for the compare pin output. (initial value)
1
Sets "1" for the compare pin output.
Note:
OTD1: Corresponds to output compare 1.
OTD0: Corresponds to output compare 0.
[bit 7, bit 6] ICP1 and ICP0
These bits are used as output compare interrupt flags. "1" is set to these bits when the
compare register value matches the 16-bit free-running timer value. While the interrupt
request bits (ICE1 and ICE0) are enabled, an output compare interrupt occurs when the
ICP1 and ICP0 bits are set. These bits are cleared by writing "0". Writing "1" has no effect.
"1" is always read by a read-modify-write instruction.
0
No compare match (initial value)
1
Compare match
Note:
ICP1: Corresponds to output compare 1.
ICP0: Corresponds to output compare 0.
139
CHAPTER 11 16-BIT I/O TIMER
[bit 5, bit 4] ICE1 and ICE0
These bits are used as output compare interrupt enable flags. While the "1" is written to
these bits, an output compare interrupt occurs when an interrupt flag (ICP1 or ICP0) is set.
0
Output compare interrupt disabled (initial value)
1
Output compare interrupt enabled
Note:
ICE1: Corresponds to output compare 1.
ICE0: Corresponds to output compare 0.
[bit 3, bit 2] Unused bits
[bit 1, bit 0] CST1 and CST0
These bits are used to enable a match with 16-bit free-running timer.
0
Compare operation disabled (initial value)
1
Compare operation enabled
Ensure that a value is written to the compare register before the compare operation is
enabled.
Note:
CST1: Corresponds to output compare 1.
CST0: Corresponds to output compare 0.
Since output compare is synchronized with the 16-bit free-running timer clock, stopping the
16-bit free-running timer stops compare operation.
140
CHAPTER 11 16-BIT I/O TIMER
11.4.3 16-bit Output Compare Operation
The 16-bit output compare compares the specified compare register value with a 16-bit
free-running timer value.
When a match occurs, it can set the interrupt request flag and invert the output level.
■ Sample of a Output Waveform when Compare Registers 0 and 1 are Used
(The Initial Output Value is "0".)
Figure 11.4-4 Sample of Output Waveform when Compare Registers 0 and 1 are Used
Counter value
FFFFH
BFFF H
7FFFH
3FFFH
Time
0000H
Reset
Compare register
0 value
Compare register
1 value
OUT0
BFFFH
7FFFH
OUT1
Compare 0
interrupt
Compare 1
interrupt
141
CHAPTER 11 16-BIT I/O TIMER
■ Sample of a Output Waveform with Two Compare Registers (The Initial Output Value is "0".)
The output level can be changed using two compare registers (when CMOD=1).
Figure 11.4-5 Sample of a Output Waveform with Two Compare Registers (The Initial Output Value is "0")
Counter value
FFFFH
BFFF H
7FFFH
3FFFH
0000H
Time
Reset
BFFFH
Compare register
0 value
Compare register
1 value
OUT0
7FFFH
Corresponds to
compare 0 and 1
OUT1
Compare 0
interrupt
Compare 1
interrupt
■ Output Compare Timing
In output compare operation, a compare match signal is generated when the 16-bit free-running
timer value matches the specified compare register value. The output value can be inverted and
an interrupt can be issued. The output reverse timing upon a compare match is synchronized
with the counter count timing.
❍ Compare operation upon update of compare register
When the compare register is updated, comparison with the counter value is not performed.
Figure 11.4-6 Compare Operation upon Update of Compare Register
N
Counter value
N+1
N+2
N+3
No match signal is generated.
142
Compare register
0 value
Compare register
0 write
M
Compare register
1 value
Compare register
1 write
M
N+1
N+3
Compare 0 stop
Compare 1 stop
CHAPTER 11 16-BIT I/O TIMER
Figure 11.4-7 Interrupt Timing of Output Compare
φ
N
Counter value
N+1
N
Compare register
value
Compare match
Interrupt
Figure 11.4-8 Output Pin Change Timing of Output Compare
Counter value
Compare register
value
N
N+1
N
N+1
N
Compare match
signal
Pin output
143
CHAPTER 11 16-BIT I/O TIMER
11.5 Input Capture
Input capture detects a rising or falling edge or both edges of an external input signal
and stores a 16-bit free-running timer value at that time in a register. In addition, input
capture can generate an interrupt upon detection of an edge. Input capture consists of
an input capture data register and a control status register.
■ Input Capture
Each input capture has a corresponding external input pin.
❍ The valid edge of an external input can be selected from the following 3 types:
Rising edge
Falling edge
Both edges
❍ An interrupt can be generated upon detection of a valid edge of an external input.
144
CHAPTER 11 16-BIT I/O TIMER
■ Input Capture Block Diagram
Figure 11.5-1 shows a block diagram of input capture.
Figure 11.5-1 Input Capture Block Diagram
IN0
Edge detection
Capture data register 0
EG11 EG10 EG01 EG00
16-bit timer counter value (T15 to T00)
Bus
Edge detection
Capture data register 1
ICP1
ICP0
ICE1
IN1
ICE0
Interrupt
Interrupt
145
CHAPTER 11 16-BIT I/O TIMER
11.5.1 Input Capture Register Details
Input capture has the two registers listed. These registers store a value from the 16-bit
free running timer when a valid edge of the corresponding external pin input waveform
is detected. (The registers must be accessed in word mode. No values can be written
to the registers.)
• Input capture data register (IPCP0/1)
• Input capture control status register (ICS0/1)
■ Input Capture Data Register (IPCP0/1)
Figure 11.5-2 Input Capture Data Register (IPCP0/1)
bit
Address: 001921H
001923H
Read/write→
Initial value→
bit
Address: 001920H
001922H
Read/write→
Initial value→
15
CP15
14
CP14
13
CP13
12
CP12
11
CP11
10
CP10
9
CP09
8
CP08
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
7
CP07
6
CP06
5
CP05
4
CP04
3
CP03
2
CP02
1
CP01
0
CP00
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
IPCP0/
IPCP1
IPCP0/
IPCP1
■ Input Capture Control Status Register (ICS0/1)
Figure 11.5-3 Input Capture Control Status Register (ICS0/1)
bit
7
Address: 000054H
ICP1
Read/write→ (R/W)
Initial value→
(0)
6
ICP0
(R/W)
(0)
5
ICE1
(R/W)
(0)
4
ICE0
(R/W)
(0)
3
EG11
(R/W)
(0)
2
EG10
(R/W)
(0)
1
EG01
(R/W)
(0)
0
EG00
(R/W)
(0)
ICS0/ICS1
[bit 7, bit 6] ICP1 and ICP0
These bits are used as input capture interrupt flags. "1" is set to this bit upon detection of a
valid edge of an external input pin. While the interrupt enable bits (ICE0 and ICE1) are set,
an interrupt can be generated upon detection of a valid edge.
These bits are cleared by writing "0". Writing "1" has no effect. "1" is always read by a readmodify-write instruction.
146
0
No valid edge detection (initial value)
1
Valid edge detection
CHAPTER 11 16-BIT I/O TIMER
Note:
ICP0: Corresponds to input capture 0.
ICP1: Corresponds to input capture 1.
[bit 5, bit 4] ICE1 and ICE0
These bits are used to enable input capture interrupts. While these bits are "1", an input
capture interrupt is generated when the interrupt flag (ICP0 or ICP1) is set.
0
Interrupt disabled (initial value)
1
Interrupt enabled
Note:
ICE0: Corresponds to input capture 0.
ICE1: Corresponds to input capture 1.
[bit 3 to bit 0] EG11, EG10, EG01, and EG00
These bits are used to specify the valid edge polarity of the external inputs. These bits are
also used to enable input capture operation.
EG11
EG01
EG10
EG00
0
0
No edge detection (stop) (initial value)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edge detection
Edge detection polarity
Note:
EG01 and EG00: Correspond to input capture 0.
EG11 and EG10: Correspond to input capture 1.
147
CHAPTER 11 16-BIT I/O TIMER
11.5.2 16-bit Input Capture Operation
In 16-bit input capture operation, an interrupt can be generated upon detection of at
the specified edge, fetching the 16-bit free-running timer value and writing it to the
capture register.
■ Sample of Input Capture Fetch Timing
•
Capture 0: Rising edge
•
Capture 1: Falling edge
•
Capture example: Both edges (for example)
Figure 11.5-4 Sample of Input Capture Fetch Timing
Counter value
FFFF H
BFFF H
7FFF H
3FFF H
0000 H
Time
Reset
IN0
IN1
IN example
Capture 0
Capture 1
Capture
example
Capture 0
interrupt
Capture 1
interrupt
Capture
interrupt
148
Undefined
3FFFH
Undefined
Undefined
7FFFH
BFFFH
3FFFH
CHAPTER 11 16-BIT I/O TIMER
■ Input Capture Input Timing
❍ Capture timing for input signals
Figure 11.5-5 Capture timing for input signals
φ
Counter value
Input capture
input
N
N+1
Valid edge
Capture signal
Capture register
N+1
Interrupt
149
CHAPTER 11 16-BIT I/O TIMER
150
CHAPTER 12
16-BIT RELOAD TIMER (WITH EVENT
COUNT FUNCTION)
This chapter explains the functions and operations of the 16-bit reload timer (with the
event count function).
12.1 Outline of 16-Bit Reload Timer (with Event Count Function)
12.2 16-Bit Reload Timer
12.3 Internal Clock and External Clock Operations of 16-Bit Reload Timer
12.4 Underflow Operation of 16-Bit Reload Timer
12.5 Output Pin Functions of 16-Bit Reload Timer
12.6 Counter Operation State
151
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
12.1 Outline of 16-Bit Reload Timer (with Event Count Function)
The 16-bit reload timer consists of a 16-bit down-counter, a 16-bit reload register, one
input pin (TIN) and one output pin (TOT), and a control register. The input clock can be
selected from one external clock and three types of internal clock.
■ Outline of 16-bit Reload Timer (with Event Count Function)
The output pin (TOT) outputs a toggle output waveform in reload mode and outputs a square
waveform indicating counting in one-shot mode. The input pin (TIN) is used for event input in
event count mode, and can be used for trigger input or gate input in internal clock mode.
The MB90590 series has two 16-bit reload timers. However the TIN input and TOT output
external pins are shared between the two timers.
■ Intelligent I/O Service (EI2OS) Function and Interrupts
The timer includes a circuit that supports EI2OS. The timer can activate EI2OS when an
underflow occurs. EI2OS can be used with both timers on this product. However, as both timers
(ch.0 and ch.1) are connected to the same interrupt control register (ICRx) in the interrupt
controller, ch.0 and ch.1 cannot be assigned to different EI2OS services. Also, as the two timers
have different interrupt vectors, they can be assigned to two different interrupt services.
However, as ch.0 and ch.1 share an interrupt control register as described above, the same
interrupt level applies to both channels.
152
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
■ Block Diagram of 16-bit Reload Timer
Figure 12.1-1 shows a block diagram of the 16-bit reload timer.
Figure 12.1-1 Block Diagram of 16-bit Reload Timer
16
16-bit reload register
8
Reload
RELD
UF
16-bit down-counter
OUTE
F2 M C - 16LX bus
16
OUTL
2
OUT
CTL.
GATE
INTE
UF
IRQ
CSL1
Clock selector
CNTE
CSL0
TRG
Clear
EI2OSCLR
Re-trigger
2
EXCK
Port (TIN)
IN CTL
Output enable
3
21
23
25
Prescaler
clear
Port (TOT)
MOD2
MOD1
Peripheral clock
UART baud rate (ch.0)
A/DC (ch.1)
MOD0
3
153
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
12.2 16-Bit Reload Timer
The 16-bit reload timer has the following two types of registers:
• Timer control status register
• 16-bit timer register/16-bit reload register
■ 16-bit Reload Timer Register
Figure 12.2-1 16-bit Reload Timer Register
Timer control status register (upper)
Address:ch.0 000051H
ch.1 000053 H
Read/write
Initial value
bit
Read/write
Initial value
16-bit timer register (upper)/
16-bit reload register (upper)
Address: ch.0 001941H
ch.1 001943 H
Read/write
Initial value
16-bit timer register (lower)/
16-bit reload register (lower)
Address:ch.0 001940 H
ch.1 001942 H
Read/write
Initial value
154
14
13
12
11
10
9
8
—
—
—
—
CSL1
CSL0
MOD2
MOD1
—
—
—
—
—
—
—
—
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
3
bit
7
6
5
4
MOD0
OUTE
OUTL
RELD
INTE
UF
CNTE
TRG
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
10
9
8
Timer control status register (lower)
Address: ch.0 000050 H
ch.1 000052 H
15
bit
15
(R/W)
(X)
14
13
12
2
11
1
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
6
5
4
3
2
1
bit
0
TMCSR
0
TMR/
TMRLR
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
12.2.1 Timer Control Status Register (TMCSR)
Controls the operation mode and interrupts for the 16-bit timer. Only modify bits other
than UF, CNTE, and TRG when CNTE = 0.
■ Register Layout of Timer Control Status Register (TMCSR)
Figure 12.2-2 Timer Control Register (TMCSR)
Timer control status register (upper)
Address:ch.0 000051H
ch1 000053
00003DHH
ch.1
Read/write
Initial value
Timer control status register (lower)
Address:ch.0 000050 H
ch1 000052
00003CHH
ch.1
Read/write
Initial value
bit
15
14
13
12
11
10
9
8
—
—
—
—
CSL1
CSL0
MOD2
MOD1
—
—
—
—
—
—
—
—
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
3
bit
7
6
5
4
2
1
MOD0
OUTE
OUTL
RELD
INTE
UF
CNTE
TRG
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
0
TMCSR
■ Register Contents of Timer Control Status Register (TMCSR)
[bit 11, bit 10] CSL1, CSL0 (Clock select 1, 0)
The count clock select bits. Table 12.2-1 lists the selected clock sources.
Table 12.2-1 Clock Sources for CSL Bit Settings
CSL1
CSL0
Clock Source (Machine cycle φ = 16 MHz)
0
0
φ/21 (0.125 µs)
0
1
φ/23 (0.5 µs)
1
0
φ/25 (2.0 µs)
1
1
External event count mode
155
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
[bit 9 to bit 7] MOD2, MOD1, MOD0
These bits set the operation mode and I/O pin functions.
The MOD2 bit selects the I/O functions. When MOD2 = 0, the input pin functions as a trigger
input. In this case, the reload register contents is loaded to the counter when an active edge
is input to the input pin and count operation proceeds. When MOD2 = 1, the timer operates
in gate counter mode and the input pin functions as a gate input. In this mode, the counter
only counts while an active level is input to the input pin.
The MOD1 and MOD0 bits set the pin functions for each mode. Table 12.2-2 and Table
12.2-3 list the MOD2, MOD1, MOD0 bit settings.
Table 12.2-2 MOD2, MOD1, MOD0 Bit Settings (1)
MOD2
MOD1
MOD0
Input Pin Function
Active Edge or Level
0
0
0
Trigger disabled
-
0
0
1
Trigger input
Rising edge
0
1
0
Falling edge
0
1
1
Both edges
1
×
0
1
×
1
Gate input
"L" level
"H" level
Internal clock mode (CSL0, 1 = 00, 01, or 10)
Table 12.2-3 MOD2, 1, 0 Bit Settings (2)
MOD2
×
MOD1
MOD0
Input Pin Function
Active Edge or Level
0
0
-
-
0
1
Trigger input
Rising edge
1
0
Falling edge
1
1
Both edges
•
Event counter mode (CSL0, CSL1 = 11)
•
Bits marked as × in the table can be set to any value.
[bit 6] OUTE
Output enable bit. The TOT pin functions as a general-purpose port when this bit is "0" and
as the timer output pin when this bit is "1". In reload mode, the output waveform toggles. In
one-shot mode, TOT outputs a square waveform that indicates that counting is in progress.
156
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
[bit 5] OUTL
This bit sets the output level for the TOT pin.
Table 12.2-4 OUTE, RELD, and OUTL Settings
OUTE
RELD
OUTL
Output Waveform
0
×
×
General-purpose port
1
0
0
Output an "H" level square waveform during counting.
1
0
1
Output an "L" level square waveform during counting.
1
1
0
Toggle output. Starts with "L" level output.
1
1
1
Toggle output. Starts with "H" level output.
[bit 4] RELD (RELoaD)
This bit enables reload operations. When RELD is "1", the timer operates in reload mode. In
this mode, the timer loads the reload register contents into the counter and continues
counting whenever an underflow occurs (when the counter value changes from 0000H to
FFFFH). When RELD is "0", the timer operates in one-shot mode. In this mode, the count
operation stops when an underflow occurs due to the counter value changing from 0000H to
FFFFH.
[bit 3] INTE (INTerrupt Enable)
Timer interrupt request enable bit. When INTE is "1", an interrupt request is generated when
the UF bit changes to "1". When INTE is "0", no interrupt request is generated, even when
the UF bit changes to "1".
[bit 2] UF (UnderFlow)
Timer interrupt request flag. UF is set to "1" when an underflow occurs (when the counter
value changes from 0000H to FFFFH). Cleared by writing "0" or by the intelligent I/O service.
Writing "1" to this bit has no meaning. Read as "1" by read-modify-write instructions.
[bit 1] CNTE (CouNT Enable)
Timer count enable bit. Writing "1" to CNTE sets the timer to wait for a trigger activation.
Writing "0" stops count operation.
[bit 0] TRG (TRiGger)
Software trigger bit. Writing "1" to TRG applies a software trigger, causing the timer to load
the reload register contents to the counter and start counting. Writing "0" has no meaning.
Reading always returns "0". Applying a trigger using this register is only valid when CNTE =
1. CNTE = 0 has no effect.
157
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
12.2.2 Register Layout of 16-bit Timer Register (TMR)/16-bit
Reload Register (TMRLR)
TMRLR contents (for writing)
The 16-bit reload register holds the initial count value. The initial value is undefined.
Always write to this register using the word transfer instructions.
TMR contents (for reading)
Reading this register reads the count value of the 16-bit timer. The initial value is
undefined. Always read this register using the word transfer instructions.
■ Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR)
Figure 12.2-3 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR)
16-bit timer register (upper)/
16-bit reload register (upper)
bit
15
14
13
12
11
10
9
8
Address:ch.0 001941H
ch1 001943
00003FHH
ch.1
Read/write
Initial value
16-bit timer register (lower)/
16-bit reload register (lower)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
6
5
4
3
2
1
bit
Address:ch.0 001940H
ch1 001942
00003EHH
ch.1
Read/write
Initial value
158
0
TMR/
TMRLR
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
12.3 Internal Clock and External Clock Operations of 16-Bit
Reload Timer
The machine clock divided by 21, 23, or 25 can be selected as the clock sources for
operating the timer from an internal divide clock. The external input pin can be
selected as either a trigger input or gate input by a register setting.
If an external clock is selected, the TIN pin functions as an external event input pin to
count the number of valid edges set in the register.
■ Internal Clock Operation of 16-bit Reload Timer
Writing "1" to both the CNTE and TRG bits in the control register enables and starts counting at
one time. Using the TRG bit as a trigger input is always available when the 16-bit reload timer is
enabled (CNTE = 1), regardless of the operation mode.
Figure 12.3-1 shows counter activation and counter operation. A time period T (T: machine
cycle) is required from the counter start trigger being input until the reload register data is
loaded into counter.
Figure 12.3-1 Activation and Operation of 16-bit Reload Timer Counter
Count clock
Counter
Reload data
-1
-1
-1
Data load
CNTE (bit)
TRG (bit)
T
159
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
■ Input Pin Functions of 16-bit Reload Timer (in Internal Clock Mode)
The TIN pin can be used as either a trigger input or a gate input when an internal clock is
selected as the clock source. When used as a trigger input, input of an active edge causes the
timer to load the reload register contents to the counter and then start count operation after
clearing the internal prescaler. Input a pulse width of at least 2T (T is the machine cycle) to TIN
pin.
Figure 12.3-2 shows the operation of trigger input.
Figure 12.3-2 Trigger Input Operation of 16-bit Reload Timer
Count clock
Rising edge detected
TIN
Prescaler clear
Counter
Reload data
0000H
-1
-1
-1
Load
2T to
2.5T
When used as a gate input, the counter only counts while the active level specified by the
MOD0 bit of the control register is input to the TIN pin. In this case, the count clock continues to
operate unless stopped. The software trigger can be used in gate mode, regardless of the gate
level. Input a pulse width of at least 2T (T is the machine cycle) to the TIN pin. Figure 12.3-3
shows the operation of gate input.
Figure 12.3-3 Gate Input Operation of 16-bit Reload Timer
Count clock
When MOD0 = 1 (Count when "H" is input)
TIN
Counter
-1
-1
-1
■ External Event Counter
The TIN pin functions as an external event input pin when an external clock is selected. The
counter counts on the active edge specified in the register. Input a pulse width of at least 4T (T
is the machine cycle) to the TIN pin.
160
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
12.4 Underflow Operation of 16-Bit Reload Timer
An underflow is defined for this timer as the time when the counter value changes
from 0000H to FFFFH. Therefore, an underflow occurs after (reload register setting + 1)
counts.
■ Underflow Operation of 16-bit Reload Timer
If the RELD bit in the control register is "1" when the underflow occurs, the contents of the
reload register is loaded into the counter and counting continues. When RELD is "0", counting
stops with the counter at FFFFH.
The UF bit in the control register is set when the underflow occurs. If the INTE bit is "1" at this
time, an interrupt request is generated.
Figure 12.4-1 shows the operation when an underflow occurs.
Figure 12.4-1 Underflow Operation of 16-bit Reload Timer
Count clock
Counter
0000H
Reload data
-1
-1
-1
Data load
Underflow set
[RELD=1]
Count clock
Counter
0000H
FFFFH
Underflow set
[RELD=0]
161
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
12.5 Output Pin Functions of 16-Bit Reload Timer
In reload mode, the TOT pin performs toggle output (inverts at each underflow). In oneshot mode, the TOT pin functions as a pulse output while the count is in progress.
■ Output Pin Functions of 16-bit Reload Timer
The OUTL bit of the register sets the output polarity 16-bit reload timer. When OUTL = 0, the
initial value for toggle output is "0" and the one-shot pulse output is "1" while the count is in
progress. The output waveforms are inverted when OUTL = 1.
Figure 12.5-1 and Figure 12.5-2 show the output pin functions.
Figure 12.5-1 Output Pin Function of 16-bit Reload Timer (1)
Count start
Underflow
Level is inverted
when OUTL = 1.
TOT
General-purpose port
CNTE
Activating
Trigger
[RELD=1, OUTL=0]
Figure 12.5-2 Output Pin Function of 16-bit Reload Timer (2)
Underflow
TOT
Level is inverted
when OUTL = 1.
General-purpose port
CNTE
Activating
Trigger
Waiting for
an activating trigger
[RELD=0, OUTL=0]
162
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
12.6 Counter Operation State
The counter state is determined by the CNTE bit in the control register and the internal
WAIT signal. Available states are: CNTE = 0 and WAIT = 1 (STOP state), CNTE = 1 and
WAIT = 1 (WAIT state for trigger), and CNTE = 1 and WAIT = 0 (RUN state).
■ Counter Operation State
Figure 12.6-1 shows the transitions between each state.
Figure 12.6-1 Counter State Transitions
Reset
State transitions by hardware
STOP
CNTE=0, WAIT=1
State transitions by register access
TIN pin: Input disabled
TOT pin: General-purpose port
Counter: Retains the value while
counting stopped.
Value undefined after reset.
CNTE=0
CNTE=0
CNTE=1
TRG=1
CNTE=1
TRG=0
WAIT
RUN
CNTE=1, WAIT=1
CNTE=1, WAIT=0
TIN pin: Only trigger input enabled
TIN pin: Functions as TIN pin
TOT pin: Initial value output
TOT pin: Functions as TOT pin
Counter: Retains the value while
counting stopped. Value
undefined after reset
until load.
Counter: Running
RELD·UF
TRG=1
TRG=1
RELD·UF
LOAD
CNTE=1, WAIT= 0
Load complete
Load contents of the reload
register to the counter.
163
CHAPTER 12 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
164
CHAPTER 13
WATCH TIMER
This chapter explains the functions and operations of the Watch Timer.
13.1 Outline of Watch Timer
13.2 Watch Timer Registers
165
CHAPTER 13 WATCH TIMER
13.1 Outline of Watch Timer
The Watch Timer consists of the Timer Control register, Sub-second register, Second/
Minute/Hour registers, 1/2 clock divider, 21-bit prescaler and Second/Minute/Hour
counters. The oscillation frequency of the MCU is assumed to be at 4MHz for the
aimed operation of the Watch Timer. The Watch Timer operates as the real-world timer
and provides the real-world time information.
■ Block Diagram of Watch Timer
Figure 13.1-1 shows a block diagram of the Watch Timer.
Figure 13.1-1 Block Diagram of Watch Timer
Oscillation
clock
OE
2-bit Prescaler
1/2 Clock
Divider
OE
WOT
CO
EN
Sub-second
register
UPDT
Second Counter
CI
EN
CO
LOAD
ST
6bits
INTE0
INT0
INTE1
Minute Counter
Hour Counter
CO
CO
6bits
5bits
Second/Minute/Hour register
INT1
INTE2
INT2
INT3
INT3
IRQ
166
CHAPTER 13 WATCH TIMER
13.2 Watch Timer Registers
The Watch Timer has the following five types of registers:
• Timer control register
• Sub-second register
• Second register
• Minute register
• Hour register
■ Watch Timer Registers
Figure 13.2-1 Watch Timer Registers
Timer control register
bit
7
6
5
Address: 000060H
Reserved Reserved Reserved
Read/write→ (R/W) (R/W) (R/W)
Initial value→
(0)
(0)
(0)
4
3
2
1
0
-
-
UPDT
(R/W)
(0)
OE
(R/W)
(0)
ST
(R/W)
(0)
11
10
9
8
WTCR
Timer control register
bit
15
Address: 000061H
INTE3
Read/write→ (R/W)
Initial value→
(0)
14
INT3
(R/W)
(0)
13
12
INTE2 INT2
(R/W) (R/W)
(0)
(0)
INTE1 INT1
(R/W) (R/W)
(0)
(0)
INTE0 INT0
(R/W) (R/W)
(0)
(0)
WTCR
Sub-second register
bit
7
Address: 00194AH
D7
Read/write→ (R/W)
Initial value→
(X)
6
5
4
3
2
1
0
D6
(R/W)
(X)
D5
(R/W)
(X)
D4
(R/W)
(X)
D3
(R/W)
(X)
D2
(R/W)
(X)
D1
(R/W)
(X)
D0
(R/W)
(X)
WTBR
Sub-second register
bit
15
Address: 00194BH
D15
Read/write→ (R/W)
Initial value→
(X)
14
13
12
11
10
9
8
D14
(R/W)
(X)
D13
(R/W)
(X)
D12
(R/W)
(X)
D11
(R/W)
(X)
D10
(R/W)
(X)
D9
(R/W)
(X)
D8
(R/W)
(X)
7
6
5
4
3
2
1
0
-
-
-
D20
(R/W)
(X)
D19
(R/W)
(X)
D18
(R/W)
(X)
D17
(R/W)
(X)
D16
(R/W)
(X)
WTBR
Sub-second register
bit
Address: 00194CH
Read/write→
Initial value→
WTBR
167
CHAPTER 13 WATCH TIMER
Figure 13.2-1 Watch Timer Registers (continued)
Second register
bit
Address: 00194DH
Read/write→
Initial value→
15
14
13
12
11
10
9
8
-
-
S5
(R/W)
(0)
S4
(R/W)
(0)
S3
(R/W)
(0)
S2
(R/W)
(0)
S1
(R/W)
(0)
S0
(R/W)
(0)
7
6
5
4
3
2
1
0
-
-
M5
(R/W)
(0)
M4
(R/W)
(0)
M3
(R/W)
(0)
M2
(R/W)
(0)
M1
(R/W)
(0)
M0
(R/W)
(0)
15
14
13
12
11
10
9
8
-
-
-
H4
(R/W)
(0)
H3
(R/W)
(0)
H2
(R/W)
(0)
H1
(R/W)
(0)
H0
(R/W)
(0)
WTSR
Minute register
bit
Address: 00194EH
Read/write→
Initial value→
WTMR
Hour register
bit
Address: 00194FH
Read/write→
Initial value→
168
WTHR
CHAPTER 13 WATCH TIMER
13.2.1 Timer Control Register (WTCR)
The timer control register (WTCR) starts and stops the Watch Timer, controls
interrupts, and sets the external output pins.
■ Timer Control Register (WTCR)
Figure 13.2-2 Timer Control Register (WTCR)
Timer control register
bit
7
6
5
Address: 000060H
Reserved Reserved Reserved
Read/write→ (R/W) (R/W) (R/W)
Initial value→
(0)
(0)
(0)
4
3
2
1
0
-
-
UPDT
(R/W)
(0)
OE
(R/W)
(0)
ST
(R/W)
(0)
12
11
10
9
WTCR
Timer control register
bit
15
Address: 000061H
INTE3
Read/write→ (R/W)
Initial value→
(0)
14
13
INT3 INTE2
(R/W) (R/W)
(0)
(0)
INT2 INTE1
(R/W) (R/W)
(0)
(0)
INT1 INTE0
(R/W) (R/W)
(0)
(0)
8
INT0
(R/W)
(0)
WTCR
[bit 15 to bit 8] INT3 to INT0, INTE3 to INT0: Interrupt flags and Interrupt enable flags
INT0 to INT3 are the interrupt flags. They are set when the second counter, minute counter
and hour counter overflow respectively. If an INT bit is set while the corresponding INTE bit
is "1", the Watch Timer signals an interrupt. These flags are intended to signal an interrupt
every second/minute/hour/day.
Writing "0" to the INT bits clears the flags and writing "1" does not have any effect. Any readmodify-write instruction performed on the INT bit results reading "1".
[bit 7 to bit 5] Reserved bits
These are reserved bits. Always write "0" to these bits.
[bit 2] UPDT: Update bit
The UPDT bit is prepared for modifying the Second/Minute/Hour counter values.
To modify the counter values, write the modified data in the Second/Minute/Hour registers.
Then set the UPDT bit to "1". The register values are loaded to the counter at the next CO
signal from the 21-bit prescaler. The UPDT bit is reset by the hardware when the counter
values are rewritten. However, if the set operation by software and the reset operation by
hardware occur at the same time, the UPDT bit will not be reset.
Writing "0" to the UPDT bit does not have any effect. The result of reading by a read-modifywrite instruction is always "0".
Note:
When the second counter indicates "59 seconds", the counter value is not changed and this bit is
cleared, even if UPDT bit is set.
It is recommended to change the counter value by ST bit.
169
CHAPTER 13 WATCH TIMER
[bit 1] OE: Output enable bit
When the OE bit is set to "1", the WOT external pin serves as the output for the Watch
Timer. Otherwise it can be used as a general purpose I/O or for another peripheral block.
[bit 0] ST: Start bit
When the ST bit is set to "1", the Watch Timer loads Second/Minute/Hour values from the
registers and starts its operation. When it is reset to "0", all the counters and the prescalers
are reset to "0" and halts.
170
CHAPTER 13 WATCH TIMER
13.2.2 Sub-second Registers (WTBR)
The sub-second register (WTBR) stores a reload value for the 21-bit prescaler that
divides the oscillation clock. The reload value is usually set so that the 21-bit prescaler
will output exactly within a one-second cycle. This register is not initialized by reset,
but 21-bit prescaler is initialized by reset.
■ Sub-second Registers (WTBR)
Figure 13.2-3 Sub-second Registers (WTBR)
bit
7
Address: 00194AH
D7
Read/write→ (R/W)
Initial value→
(X)
6
5
4
3
2
1
0
D6
(R/W)
(X)
D5
(R/W)
(X)
D4
(R/W)
(X)
D3
(R/W)
(X)
D2
(R/W)
(X)
D1
(R/W)
(X)
D0
(R/W)
(X)
WTBR
Sub-second register
bit
15
Address: 00194BH
D15
Read/write→ (R/W)
Initial value→
(X)
14
13
12
11
10
9
8
D14
(R/W)
(X)
D13
(R/W)
(X)
D12
(R/W)
(X)
D11
(R/W)
(X)
D10
(R/W)
(X)
D9
(R/W)
(X)
D8
(R/W)
(X)
WTBR
Sub-second register
bit
7
6
5
4
3
2
1
0
Address: 00194CH
Read/write→
Initial value→
-
-
-
D20
(R/W)
(X)
D19
(R/W)
(X)
D18
(R/W)
(X)
D17
(R/W)
(X)
D16
(R/W)
(X)
WTBR
[bit 20 to bit 0] D20 to D0
The Sub-second register stores the reload value for the 21-bit prescaler. This value is
reloaded after the reload counter reaches "0". Note that when modifying all three bytes,
make sure the reload operation will not be performed in between the write instructions.
Otherwise the 21-bit prescaler loads the incorrect value of the combination of new data and
old data bytes. It is generally recommended that the Sub-Second register are updated while
the ST bit is "0". If the sub-second registers are set to "0", the 21-bit prescaler does not
operate at all.
The input clock frequency always equals the oscillation clock frequency and it is intended to
be 4MHz. The reload value of the 21-bit prescaler is typically set to hexadecimal 1E847F
which equals to "27 × 56-1". Therefore the combination of these two prescalers is intended to
provide a clock signal of exact one second.
171
CHAPTER 13 WATCH TIMER
13.2.3 Second/Minute/Hour Registers (WTSR/WTMR/WTHR)
The Second/Minute/Hour registers (WTSR/WTMR/WTHR) stores the time information. It
is a binary representation of the second, minute and hour.
Reading any of these register always results in the corresponding counter value.
These registers are write associable however, the written data is loaded in the
counters after the UPDT bit is set to "1". These registers and counter are initialized by
reset.
■ Second/Minute/Hour Registers (WTSR/WTMR/WTHR)
Figure 13.2-4 Second/Minute/Hour Registers (WTSR/WTMR/WTHR)
Second register
bit
Address: 00194DH
Read/write→
Initial value→
15
14
13
12
11
10
9
8
-
-
S5
(R/W)
(0)
S4
(R/W)
(0)
S3
(R/W)
(0)
S2
(R/W)
(0)
S1
(R/W)
(0)
S0
(R/W)
(0)
7
6
5
4
3
2
1
0
-
-
M5
(R/W)
(0)
M4
(R/W)
(0)
M3
(R/W)
(0)
M2
(R/W)
(0)
M1
(R/W)
(0)
M0
(R/W)
(0)
15
14
13
12
11
10
9
8
-
-
-
H4
(R/W)
(0)
H3
(R/W)
(0)
H2
(R/W)
(0)
H1
(R/W)
(0)
H0
(R/W)
(0)
WTSR
Minute register
bit
Address: 00194EH
Read/write→
Initial value→
WTMR
Hour register
bit
Address: 00194FH
Read/write→
Initial value→
WTHR
Since there are three byte-registers, make sure the obtained values from the registers are
consistent.
i.e. Obtained value of "1 hour, 59 minutes, 59 seconds" could be "0 hour 59 minutes, 59
seconds" or "1 hour, 0 minute, 0 second" or "2 hour, 0 minute, 0 second".
Also when the operation clock of the MCU is the half of the oscillation clock (When the PLL is
stopped), the read values from these registers may be erroneous. This is due to the
synchronization of the read operation and the count operation. Therefore it is recommended is
use a second interrupt to trigger the read instructions.
172
CHAPTER 14
8/16-BIT PPG
This chapter explains the 8/16-bit PPG and explains its functions.
14.1 Outline of 8/16-bit PPG
14.2 Block Diagram of 8/16-bit PPG
14.3 8/16-bit PPG Registers
14.4 Operations of 8/16-bit PPG
14.5 Selecting a Count Clock for 8/16-bit PPG
14.6 Controlling Pin Output of 8/16-bit PPG Pulses
14.7 8/16-bit PPG Interrupts
14.8 Initial Values of 8/16-bit PPG Hardware
173
CHAPTER 14 8/16-BIT PPG
14.1 Outline of 8/16-bit PPG
The 8/16-bit Programmable Pulse Generator (PPG) consists of two eight-bit down
counters, four eight-bit reload registers, one 16-bit control register, two external pulse
output signals, and two interrupt outputs. The following functions are implemented:
■ Function of 8/16-bit PPG
❍ 8-bit PPG output, 2-channel independent operation mode:
Two independent channels of PPG output operation are implemented.
❍ 16-bit PPG output operation mode:
One channel of 16-bit PPG output operation is implemented.
❍ 8-bit prescaler + 8-bit PPG output operation mode:
8-bit PPG output operation is implemented at specified intervals, using ch.0 output as ch.1 clock
input.
❍ PPG output operation:
Pulse waves are output at specified intervals and duty ratio. With an external circuit, this module
can be used as a D/A converter.
Ch.0 and ch.1 of PPG are matched and it is called the 1 unit.
There are 6 units PPG in the MB90590 series. The following sections only describe the
functions of the ch.0 and ch.1 of PPG. The remaining PPGs have the identical function and the
register addresses should be found in the I/O map.
Ch.0 of PPG is called PPG (ch.0) and ch.1 of PPG is called PPG (ch.1).
174
CHAPTER 14 8/16-BIT PPG
14.2 Block Diagram of 8/16-bit PPG
Figure 14.2-1 shows a block diagram of the 8-bit PPG (ch.0). Figure 14.2-2 shows a
block diagram of the 8-bit PPG (ch.1).
■ Block Diagram of 8-bit PPG
Figure 14.2-1 8-bit PPG ch.0 Block Diagram
Peripheral clock 16-division
Peripheral clock 8-division
Peripheral clock 4-division
Peripheral clock 2-division
Peripheral clock
PPG0
Output latch
Invert
Clear
PEN0
In MB90590 Series, this IRQ signal is
merged with the PPG (ch.1) IRQ signal
by OR logic.
Count clock
selection
Timebase counter output
512-division of main clock
L/H selection
S
RQ
PCNT
(down counter)
IRQ
Reload
ch.1-borrow
L/H selector
P RLL0
PRLBH0
PIE0
PRLH0
PUF0
"L" side data bus
"H" side data bus
PPGC0
(Operation mode control)
PPG output signal of ch.0 is not connected with an external terminal.
175
CHAPTER 14 8/16-BIT PPG
Figure 14.2-2 8-bit PPG ch.1 Block Diagram
PPG0 pin output enable
PPG0 pin
Peripheral clock 16-division
Peripheral clock 8-division
Peripheral clock 4-division
Peripheral clock 2-division
Peripheral clock
In MB90590 Series this pin is connected to
the "PPG0" external pin.
PPG1
Output latch
Invert
Count clock
selection
ch.0 borrow
Timebase counter output
512-division of main clock
L/H selection
Clear
PEN1
In MB90590 Series, this IRQ signal is
merged with the PPG (ch.1) IRQ signal
by OR logic.
S
RQ
PCNT
(down counter)
IRQ
Reload
L/H selector
PRLL1
PRLBH1
PIE1
PRLH1
PUF1
"L" side data bus
"H" side data bus
PPGC1
(Operation mode control)
Figure 14.2-3 Relation among PPG module, Unit number, and External pin
PPG unit0
PPG (ch.0), PPG (ch.1)
PPG0
PPG unit1
PPG (ch.2), PPG (ch.3)
PPG1
PPG unit2
PPG (ch.4), PPG (ch.5)
PPG2
PPG unit3
PPG (ch.6), PPG (ch.7)
PPG3
PPG unit4
PPG (ch.8), PPG (ch.9)
PPG4
PPG unit5
PPG (ch.A), PPG (ch.B)
PPG5
External pin
176
CHAPTER 14 8/16-BIT PPG
14.3 8/16-bit PPG Registers
The 8/16-bit PPG has the following five types of registers:
• PPG0 operation mode control register
• PPG1 operation mode control register
• PPG0/1 clock selection register
• Reload register H
• Reload register L
■ 8/16-bit PPG Registers
Figure 14.3-1 8/16-bit PPG Registers
PPG0 operation mode control register
Address: bit
ch.0 000038H
7
6
5
4
3
2
1
0
PEN0
-
PE00
PIE0
PUF0
-
-
Reserved
(-)
(-)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(-)
(-)
(-)
(-)
(W)
(1)
Read/write→ (R/W)
Initial value→
(0)
PPGC0
PPG1 operation mode control register
Address: bit
15
14
13
12
11
10
9
8
PEN1
-
PE10
PIE1
PUF1
MD1
MD0
Reserved
(-)
(-)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(W)
(1)
7
6
5
4
3
2
1
0
PCS2
PCS1
PCS0
PCM2 PCM1 PCM0
-
-
Read/write→ (R/W)
Initial value→
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(-)
(-)
(-)
(-)
ch.1 000039H
Read/write→ (R/W)
Initial value→
(0)
PPGC1
PPG0/1 clock selection register
Address: bit
ch.0/1 003AH
Reload register H
Address:
ch.0 001901H
ch.1 001903H
Read/write→
Initial value→
Reload register L
Address:
ch.0 001900H
ch.1 001902H
Read/write→
Initial value→
bit
15
14
13
(R/W)
(0)
12
(R/W)
(0)
11
10
9
PPG01
8
PRLH
(R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X)
(X)
(X)
(X)
bit
7
6
5
4
(R/W) (R/W)
(X)
(X)
3
2
(R/W)
(X)
1
0
PRLL
(R/W) (R/W)
(X) (X)
(R/W) (R/W) (R/W)
(X)
(X)
(X)
(R/W) (R/W)
(X)
(X)
(R/W)
(X)
177
CHAPTER 14 8/16-BIT PPG
14.3.1 PPG0 Operation Mode Control Register (PPGC0)
PPGC0 is a five-bit control register that selects the operation mode of the block,
controls pin outputs, selects count clock, and controls triggers. This register controls
PPG (ch.0).
■ PPG0 Operation Mode Control Register (PPGC0)
Figure 14.3-2 PPG0 Operation Mode Control Register (PPGC0)
Address: bit
ch.0 000038H
7
6
5
4
3
2
1
0
PEN0
-
PE00
PIE0
PUF0
-
-
Reserved
(-)
(-)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(-)
(-)
(-)
(-)
(W)
(1)
Read/write→ (R/W)
Initial value→
(0)
PPGC0
[bit 7] PEN0 (PPG enable): Operation enable bit
This bit enables the counter operation of the PPG (ch.0) below.
PEN0
Operation
0
Stop ("L" level output maintained)
1
PPG (ch.0) operation enabled
Setting this bit to "1" enables the counter operation of PPG (ch.0).
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit 5] PE00
This bit is reserved bit. This bit is always set to "0".
[bit 4] PIE0 (PPG interrupt enable): PPG interrupt enable bit
This bit controls PPG (ch.0) interrupt as described below.
0
Interrupt disabled
1
Interrupt enabled
While this bit is "1", an interrupt request is issued as soon as PUF0 is set to "1". No interrupt
request is issued while this bit is set to "0".
This bit is initialized to "0" upon a reset. This bit is readable and writable.
178
CHAPTER 14 8/16-BIT PPG
[bit 3] PUF0 (PPG underflow flag): PPG counter underflow bit
This bit controls the PPG (ch.0) counter underflow as described below.
0
PPG (ch.0) counter underflow is not detected.
1
PPG (ch.0) counter underflow is detected.
In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" when
an underflow occurs as a result of the ch.0 counter value becoming from 00H to FFH. In 16bit PPG mode, this bit is set to "1" when an underflow occurs as a result of the ch.1 and ch.0
counter value becoming from 0000H to FFFFH. To set this bit to "0", write "0". Writing "1" to
this bit has not effect. Upon a read operation during a read-modify-write instruction, "1" is
read.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit 0]
This is a reserved bit. This bit is always set to "1".
This bit is always read "1".
179
CHAPTER 14 8/16-BIT PPG
14.3.2 PPG1 Operation Mode Control Register (PPGC1)
PPGC0 is a seven-bit control register that selects the operation mode of the block,
controls pin outputs, selects count clock, and controls triggers. The control of
PPG(ch.1) and the operation mode of PPG unit 0 are selected.
■ PPG1 Operation Mode Control Register (PPGC1)
Figure 14.3-3 PPG1 Operation Mode Control Register (PPGC1)
Address: bit
ch.1 000039H
15
14
13
12
11
10
9
8
PEN1
-
PE10
PIE1
PUF1
MD1
MD0
Reserved
(-)
(-)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(W)
(1)
Read/write→ (R/W)
Initial value→
(0)
PPGC1
[bit 15] PEN1 (PPG enable): Operation enable bit
This bit enables the counter operation of the PPG (ch.1).
PEN1
Operation
0
Stop ("L" level output maintained)
1
PPG (ch.1) operation enabled
Writing "1" to this bit, PWM starts counting.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit 13] PE10 (PPG output enable 10): PPG0 pin output enable bit
This bit controls the PPG0 pulse output external pin as described below.
0
General-purpose port pin (pulse output disabled)
1
PPG0 = pulse output pin (pulse output enabled)
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit 12] PIE1 (PPG interrupt enable): PPG interrupt enable bit
This bit controls PPG (ch.1) interrupt as described below.
0
Interrupt disabled
1
Interrupt enabled
While this bit is "1", an interrupt request is issued as soon as PUF1 is set to "1". No interrupt
request is issued while this bit is set to "0".
This bit is initialized to "0" upon a reset. This bit is readable and writable.
180
CHAPTER 14 8/16-BIT PPG
[bit 11] PUF1 (PPG underflow flag): PPG counter underflow bit
This bit indicates the PPG (ch.1) counter underflow as described below.
0
PPG (ch.1) counter underflow is not detected.
1
PPG (ch.1) counter underflow is detected.
In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" when
an underflow occurs as a result of the ch.1 counter value becoming from 00H to FFH. In 16bit PPG mode, this bit is set to "1" when an underflow occurs as a result of the ch.1 and ch.0
counter value becoming from 0000H to FFFFH. To set this bit to "0", write "0". Writing "1" to
this bit has not effect. Upon a read operation during a read-modify-write instruction, "1" is
read.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit 10, bit 9] MD1, MD0 (PPG count mode): Operation mode selection bit
These bits selects the PPG unit operation mode as described below.
MD1
MD0
Operation mode
0
0
8-bit PPG 2ch independent mode
0
1
8-bit prescaler + 8-bit PPG 1ch mode
1
0
Reserved
1
1
16-bit PPG 1ch mode
These bits are initialized to "00" upon a reset. These bits are readable and writable.
Notes:
• Do not set "10" in these bits.
• To write "01" to these bits, ensure that "01" is not written to the PEN0 bit of PPGC0 or PEN1 bit
of PPGC1. Write "11" or "00" in both the PEN0 and PEN1 bits simultaneously.
• To write "11" to these bits, update PPGC0 and PPGC1 by word transfer and write "11" or "00" to
both the PEN0 and PEN1 bits simultaneously.
[bit 8]
This is a reserved bit. When setting PPGC1, always write "1" to this bit.
181
CHAPTER 14 8/16-BIT PPG
14.3.3 PPG0/PPG1 Clock Selection Register (PPG01)
The PPG0/PPG1 clock selection register (PPG01) is an 8-bit control register that
controls the pin output of the 8/16-bit PPG.
■ PPG0/PPG1 Clock Selection Register (PPG01)
Figure 14.3-4 PPG0/PPG1 Clock Selection Register (PPG01)
Address: bit
7
6
5
PCS2
PCS1
PCS0
PCM2 PCM1 PCM0
Read/write→ (R/W)
Initial value→
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
ch.0, ch.1 003AH
4
3
(R/W)
(0)
2
(R/W)
(0)
1
0
-
-
(-)
(-)
(-)
(-)
PPG01
[bit 7 to bit 5] PCS2 to PCS0 (PPG count select): Count clock selection bit
These bits select the operation clock for the down counter of ch.1 as described below.
PCS2
PCS1
PCS0
Operation mode
0
0
0
Peripheral clock (62.5 ns machine clock, 16 MHz)
0
0
1
Peripheral clock/2 (125 ns machine clock, 16 MHz)
0
1
0
Peripheral clock/4 (250 ns machine clock, 16 MHz)
0
1
1
Peripheral clock/8 (500 ns machine clock, 16 MHz)
1
0
0
Peripheral clock/16 (1 µs machine clock, 16 MHz)
1
1
1
Clock input from the timebase timer (128 µs, 4 MHz source
oscillation)
These bits are initialized to "000" upon a reset. These bits are readable and writable.
Note:
In 8-bit prescaler + 8-bit PPG mode or in 16-bit PPG mode, ch.1 PPG operates in response to a
counter clock from ch.0. Therefore, the setting of PCS2 to PCS0 bits has no effect.
182
CHAPTER 14 8/16-BIT PPG
[bit 4 to bit 2] PCM2 to PCM0 (PPG count mode): Count clock selection bit
These bits select the operation clock for the down counter of Channel 0 as described below.
PCM2
PCM1
PCM0
Operation mode
0
0
0
Peripheral clock (62.5 ns machine clock, 16 MHz)
0
0
1
Peripheral clock/2 (125 ns machine clock, 16 MHz)
0
1
0
Peripheral clock/4 (250 ns machine clock, 16 MHz)
0
1
1
Peripheral clock/8 (500 ns machine clock, 16 MHz)
1
0
0
Peripheral clock/16 (1 µs machine clock, 16 MHz)
1
1
1
Clock input from the timebase timer (128 µs, 4 MHz
source oscillation)
These bits are initialized to "000" upon a reset. These bits are is readable and writable.
183
CHAPTER 14 8/16-BIT PPG
14.3.4 Reload Register (PRLL/PRLH)
The reload registers (PRLL and PRLH) are 8-bit registers that store reload values for
the PCNT down counters. The PRLL and PRLH registers are readable and writable.
■ Reload Register (PRLL/PRLH)
Figure 14.3-5 Reload Register (PRLL/PRLH)
Reload register H
Address:
bit
15
14
13
12
11
10
9
8
ch.0 001901H
ch.1 001903H
PRLH
Read/write→
Initial value→
Reload register L
Address:
(R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X)
(X)
(X)
(X)
bit
ch.0 001900H
ch.1 001902H
Read/write→
Initial value→
7
6
5
4
(R/W) (R/W)
(X)
(X)
3
2
(R/W)
(X)
1
0
PRLL
(R/W) (R/W)
(X) (X)
(R/W) (R/W) (R/W)
(X)
(X)
(X)
(R/W) (R/W)
(X)
(X)
Register name
(R/W)
(X)
Function
0
Holds the "L" side reload value.
Set length of "L" pulse width.
1
Holds the "H" side reload value.
Set length of "H" pulse width.
Note:
In 8-bit prescaler + 8-bit PPG mode, different values in PRLL and PRLH of ch.0 may cause the
PPG waveform of ch.1 to vary in each cycle. It is recommended to write the same value to PRLL
and PRLH of ch.0.
184
CHAPTER 14 8/16-BIT PPG
14.4 Operations of 8/16-bit PPG
One 8/16-bit PPG consists of two channels of 8-bit PPG units. By connecting
operation, these two channels can be used in three modes: independent two-channel
mode, 8-bit prescaler + 8-bit PPG mode, and single-channel 16-bit PPG mode.
■ Operations of 8/16-bit PPG
Each of the 8-bit PPG units has two eight-bit reload registers. One reload register is for the "L"
pulse width (PRLL) and the other is for the "H" pulse width (PRLH). The values stored in these
registers are reloaded into the 8-bit down counter (PCNT), from the PRLL and PRLH by turns.
The value of PPG0 output pin is inverted upon a reload caused by counter borrow. This
operation outputs in the pulses of the specified "L" pulse width and "H" pulse width
corresponding to the value of reload register.
Table 14.4-1 lists the relationship between the reload operation and pulse outputs.
Table 14.4-1 Reload Operation and Pulse Output
Reload operation
Pin output change
PRLH --> PCNT
PPG0 output pin [0 --> 1]
Rise
PRLL --> PCNT
PPG0 output pin [1 --> 0]
Fall
When "1" is set in bit 4 (PIE0) of PPGC0 or in bit 12 (PIE1) of PPGC1, an interrupt request is
output upon a borrow from 00 to FF (from 0000 to FFFF in 16-bit PPG mode) of each counter.
■ Operation Modes of 8/16-bit PPG
In 8/16-bit PPG there are in three operation modes: independent two-channel mode, 8-bit
prescaler + 8-bit PPG mode, and 16-bit PPG1 mode.
❍ Independent two-channel mode
The two channels of 8-bit PPG units operate independently.
❍ 8-bit prescaler + 8-bit PPG mode
ch.0 is used as an 8-bit prescaler while the count in ch.1 is based on borrow outputs from ch.0.
Thus, 8-bit PPG waveforms can be output with optional length of cycle time.
❍ 16-bit PPG1 channel mode
This is an operation mode that ch.0 and ch.1 are connected and used as a single 16-bit PPG.
185
CHAPTER 14 8/16-BIT PPG
■ 8/16-bit PPG Output Operation
In 8/16-bit PPG, the ch.0 PPG is activated to start counting when "1" is written to bit 7 (PEN0) of
the PPGC0 register. Similarly, the ch.1 PPG is activated to start counting when "1" is written to
bit 15 (PEN1) of the PPGC1 register.
For the MB90590 series, the output signal from the ch.0 PPG is not connected to any external
pin.
In 8-bit prescaler + 8-bit PPG mode, do not set ch.1 to be in operation while ch.0 operation is
stopped.
In 8/16-bit PPG, ensure that setting bit 7 (PEN0) of PPGC0 (PMW operation mode control
register) and bit 15 (PEN1) of PPGC1 register to "1" activates operation and starts counting.
After starting operation, writing "0" to bit 7 (PEN0) of PPGC0 or bit 15 (PEN1) of PPGC1 stops
the count operation. After stop, the pulse output holds "L" level.
Figure 14.4-1 PPG Output Operation, Output Waveform
PEN
Starts operation based on PEN (from "L" side).
PPG0
Output pin
T
(L+1)
T
L : PRLL value
H : PRLH value
T : Input from peripheral clock ( , /4, /16)
or timer base counter (depending on the
clock selection by PPGC)
(H+1)
(Start)
■ Relationship between 8/16-bit PPG Reload Value and Pulse Width
The width of the output pulse is determined by adding 1 to the reload register value and
multiplying it by the count clock cycle. Note that when the reload register value is 00H during 8bit PPG operation and 0000H during 16-bit PPG operation, the pulse width is equivalent to one
count clock cycle. In addition, note that when the reload register value is FFH during 8-PPG
operation, the pulse width is equivalent to 256 count clock cycles. When the reload register
value is FFFFH during 16-bit PPG operation, the pulse width is equivalent to 65536 count clock
cycles.
Pl=T
Ph=T
186
(L+1)
(H+1)
L:
H:
T:
Ph:
Pl:
PRLL value
PRLH value
Input clock cycle
High pulse width
Low pulse width
CHAPTER 14 8/16-BIT PPG
14.5 Selecting a Count Clock for 8/16-bit PPG
The count clock used for the operation is supplied from the peripheral clock or the
timebase timer. The count clock can be selected from six choices.
■ Selecting a Count Clock for 8/16-bit PPG
Select ch.0 clock at bit 4 to bit 2 (PCM2 to PCM0) of the PPG0 and PPG1 clock selection register,
and ch.1 clock at bit 7 to bit 5 (PCS2 to PCS0) of the PPG0/PPG1 register.
The clock is selected from a peripheral clock 1/16 to 1 times higher than a machine clock or an
input clock from the timebase timer.
In 8-bit prescaler + 8-bit PPG mode or 16-bit PPG mode, however, the setting in the PCS2 to
PCS0 has no effect.
When the timebase timer input is used, the first count cycle after a trigger or a stop may be
shifted. The cycle may also be shifted if the timebase counter is cleared during operation of this
module.
In 8-bit prescaler + 8-bit PPG mode, if ch.1 is activated while ch.0 is in operation and ch.1 is
stopped, the first count cycle may be shifted.
187
CHAPTER 14 8/16-BIT PPG
14.6 Controlling Pin Output of 8/16-bit PPG Pulses
The pulses generated by this module can be output from external pins PPG0.
■ Controlling Pin Output of 8/16-bit PPG Pulses
When bit 13 (PE10) of PPG1 operation mode control register (PPGC1) is "0"(default), the pulses
are not output from the corresponding external pins; the pins work as general-purpose ports.
Setting this bit to "1", the pulses are output from external pins.
In 8-bit prescaler + 8-bit PPG mode, the 8-bit prescaler toggle waveform of PPG (ch.0) is output,
while the 8-bit PPG waveform of PPG (ch.1) is output. Figure 14.6-1 is a diagram of output
waveforms in this mode.
For the MB90590 series, the output signal from the ch.0 PPG is not connected to any external
pin.
Figure 14.6-1 8-bit Prescaler + 8-bit PPG Output Operation Waveform
Ph0
Pl0
PPG(ch.0)
outoput
(internal signal)
PPG(ch.1)
outoput
(PPG0 pin
waveform)
Ph1
Pl0 = T
Pl1
(L0+1)
Ph0 = T
(L0+1)
Pl1 = T
(L0+1)
(L1+1)
Ph1 = T
(L0+1)
(H1+1)
L0:
L1:
H1:
T:
Ph0:
Pl0:
Ph1: PPG10 high pulse width
Pl1: PPG10 low pulse width
Note:
Set the same value in ch.0 PRLL and ch.0 PRLH.
188
ch.0 PRLL value and ch0 PRLH value
ch.1 PRLL value
ch.1 PRLH value
Input clock cycle
PPG00 high pulse width
PPG00 low pulse width
CHAPTER 14 8/16-BIT PPG
14.7 8/16-bit PPG Interrupts
The 8/16-bit PPG outputs interrupt request when the reload value counts out and a
borrow occurs.
■ 8/16-bit PPG Interrupts
In 8-bit PPG 2channel mode or 8-bit prescaler + 8-bit PPG mode, an interrupt is requested by a
borrow in each counter. In 16-bit PPG mode, PUG0 and PUF1 are simultaneously set by a
borrow in the 16-bit counter. Therefore, enable only one for PIE0 or PIE1 to unify the interrupt
causes. In addition, simultaneously clear the interrupt causes for PUF0 and PUF1.
189
CHAPTER 14 8/16-BIT PPG
14.8 Initial Values of 8/16-bit PPG Hardware
The hardware components of this block are initialized to the following values when
reset:
■ Initial Values of 8/16-bit PPG Hardware
❍ Registers
•
PPGC0 --> 0-000--1B
•
PPGC1 --> 0-000001B
•
PPG10 -->
------00B
❍ Pulse outputs
PPG0 pin becomes an output prohibition.
When the output is permitted, it becomes "L" output.
❍ Interrupt requests
It becomes an interrupt prohibition.
The reload value is maintained.
Note:
Write timing for 8/16-bit PPG reload registers (PRLL, PRLH);
In a mode other than 16-bit PPG mode, it is recommended to use a word transfer instruction to
write data in reload registers PRLL and PRLH. If two byte transfer instructions are used to write a
data item to these registers, a pulse of unexpected cycle time may be output depending on the
timing.
Figure 14.8-1 Write Timing Chart for 8/16-bit PPG Reload Registers (PRLL and PRLH)
PPG0
B
A
B
A
C
B
C
➀
C
D
D
➀ in the time chart above, and PRLH is
updated from B to D after ➀. Since the PRL values at ➀ are PRLL=C and PRLH=B, a pulse of
Assume that PRLL is updated from A to C before
"L" side count value C and "H" side count value B is output only once.
Similarly, to write data in PRL of ch.0 and ch.1 in 16-bit PPG mode, use a long word transfer
instruction, or use word transfer instructions in the order of ch.0 and then ch.1. In this mode, the
data is only temporarily written to ch.0 PRL. Then, the data is actually written into ch.0 PRL when
the ch.1 PRL is written to.
In a mode other than 16-bit PPG mode, ch.0 and ch.1 PRL are written independently.
190
CHAPTER 14 8/16-BIT PPG
Figure 14.8-2 PRL Write Operation Block Diagram
ch.0 PRL write data
ch.1 PRL write data
Transferred in synchronization
with ch.1 write in 16-bit
Temporary latch
PPG mode
ch.0 write in a mode other
than 16-bit PPG mode
ch.1 write
ch.0 PRL
ch.1 PRL
191
CHAPTER 14 8/16-BIT PPG
192
CHAPTER 15
DTP/EXTERNAL INTERRUPTS
This chapter explains the functions and operations of the DTP/external interrupts.
15.1 Outline of DTP/External Interrupts
15.2 DTP/External Interrupt Registers
15.3 Operations of DTP/External Interrupts
15.4 Switching between External Interrupt and DTP Requests
15.5 Notes on Using DTP/External Interrupts
193
CHAPTER 15 DTP/EXTERNAL INTERRUPTS
15.1 Outline of DTP/External Interrupts
The data transfer peripheral (DTP) is a peripheral located between an external
peripheral and the F2MC-16LX CPU. The DTP receives a DMA request or interrupt
request from the external peripheral, transfers the request to the F2MC-16LX CPU to
activate the intelligent I/O service or interrupt processing.
■ Outline of DTP/External Interrupts
For the intelligent I/O service, "H" and "L" request levels are available. For an external interrupt
request, four request levels are available: "H", "L", rising edge, and falling edge.
For the MB90590 series, the external bus interface is not supported. Therefore the DTP/
External Interrupt cannot serve as the data transfer peripheral. It can be only used as the
external Interrupt.
For MB90V590G, there are only four external pins assigned to this block. Therefore the external
interrupt ch.4 to ch.7 are not supported. These external interrupts should be disabled.
■ Block Diagram of DTP/External Interrupts
Figure 15.1-1 Block Diagram of DTP/External Interrupts
8
8
8
16
194
DTP/Interrupt enable register
Gate
Cause F/F
Edge detection circuit
DTP/Interrupt cause register
Request level setting register
8
Request input
CHAPTER 15 DTP/EXTERNAL INTERRUPTS
■ DTP/External Interrupts Registers
Figure 15.1-2 DTP/External Interrupts Registers
bit
Address: 000030H
bit
Address: 000031H
bit
Address: 000032H
bit
Address: 000033H
7
6
5
4
3
2
1
0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
15
14
13
12
11
10
9
8
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
7
6
5
4
3
2
1
0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
15
14
13
12
11
10
9
8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
Interrupt/DTP enable register
(ENIR)
Interrupt/DTP cause register
(EIRR)
Request level setting register
(ELVR)
Request level setting register
(ELVR)
195
CHAPTER 15 DTP/EXTERNAL INTERRUPTS
15.2 DTP/External Interrupt Registers
The DTP/external interrupts has the following three types of registers:
• DTP/Interrupt enable register (ENIR: Interrupt request enable register)
• DTP/Interrupt source register (EIRR: External interrupt request register)
• Request level setting register (ELVR: External level register)
■ DTP/Interrupt Enable Register (ENIR: Interrupt request enable register)
ENIR enables the function to issue a request to the interrupt controller using a device pin as an
external DTP/interrupt request input. A pin corresponding to a "1" bit of this register is used as
an external DTP/interrupt request input. A pin corresponding to a "0" bit holds the external DTP/
interrupt request input cause, but does not issue a request to the interrupt controller.
Figure 15.2-1 DTP/Interrupt Enable Register (ENIR)
bit
Address: 000030H
Read/write→
Initial value→
7
6
5
4
3
2
1
0
EN7
R/W
0
EN6
R/W
0
EN5
R/W
0
EN4
R/W
0
EN3
R/W
0
EN2
R/W
0
EN1
R/W
0
EN0
R/W
0
ENIR
■ DTP/Interrupt Source Register (EIRR: External interrupt request register)
The EIRR indicates the presence of DTP/external interrupt requests at the pins corresponding
to the "1" bits of this register. Writing "0" to a bit of this register clears the corresponding request
flag. Writing "1" has no effect. Reading this register with a read-modify-write instruction always
results in the reading value "1".
Figure 15.2-2 Interrupt/DTP Source Register (EIRR)
bit
Address: 000031H
Read/write→
Initial value→
15
14
13
12
11
10
9
8
ER7
R/W
X
ER6
R/W
X
ER5
R/W
X
ER4
R/W
X
ER3
R/W
X
ER2
R/W
X
ER1
R/W
X
ER0
R/W
X
EIRR
The objects differ
for R and W.
Note:
If more than one external interrupt request output is enabled (EN7 to EN0 of ENIR are set to "1"),
clear to "0" only the bit for which the CPU accepted an interrupt (any of bits ER7 to ER0 that are set
to "1"). Do not clear the other bits without a valid reason.
196
CHAPTER 15 DTP/EXTERNAL INTERRUPTS
■ Request Level Setting Register (ELVR: External level register)
Figure 15.2-3 Request Level Setting Register (ELVR)
bit
Address: 000032H
Read/write→
Initial value→
bit
Address: 000033H
Read/write→
Initial value→
7
6
5
4
3
2
1
0
LB3
R/W
0
LA3
R/W
0
LB2
R/W
0
LA2
R/W
0
LB1
R/W
0
LA1
R/W
0
LB0
R/W
0
LA0
R/W
0
7
6
5
4
3
2
1
0
LB7
R/W
0
LA7
R/W
0
LB6
R/W
0
LA6
R/W
0
LB5
R/W
0
LA5
R/W
0
LB4
R/W
0
LA4
R/W
0
ELVR
ELVR
ELVR defines the request event at the external pin. Each pin is assigned two bits as described
in Table 15.2-1. If a request is detected by the input level, the interrupt flag is set as long as the
input is maintained at the specified level even after the flag is reset by software.
Table 15.2-1 Interrupt Request Detection Factor for LBx and LAx Pins
LBx
LAx
Interrupt request detection factor
0
0
"L" level pin input
0
1
"H" level pin input
1
0
Rising edge pin input
1
1
Falling edge pin input
197
CHAPTER 15 DTP/EXTERNAL INTERRUPTS
15.3 Operations of DTP/External Interrupts
When the interrupt flag is set, this block signals an interrupt to the interrupt controller.
The interrupt controller judges the priority levels of the simultaneous interrupts, and
issues an interrupt request to the F2MC-16LX CPU if the interrupt from this resource
has the highest priority. The F2MC-16LX CPU compares the ILM bits of its internal CCR
register and the interrupt request. If the interrupt level of the request is higher than
that indicated by the ILM bits, the F2MC-16LX CPU activates the hardware interrupt
processing microprogram as soon as the currently executing instruction is terminated.
■ External Interrupt Operation
In the hardware interrupt processing microprogram, the CPU reads the ISE bit information from
the interrupt controller, identifies that the request is for interrupt processing based on that
information, and branches to the interrupt processing microprogram. The interrupt processing
microprogram reads the interrupt vector area and issues an interrupt acknowledgment signal for
the interrupt controller. Then, the microprogram transfers the jump destination address of the
macro instruction generated from the vector to the program counter, and executes the user
interrupt processing program.
Figure 15.3-1 External Interrupt Operation
External interrupt/DTP
Interrupt controller
F2MC-16LX CPU
ICRyy
IL
Other request
ELVR
EIRR
ENIR
Cause
198
CMP
ICRxx
CMP
ILM
INTA
CHAPTER 15 DTP/EXTERNAL INTERRUPTS
■ DTP operation
To activate the intelligent I/O service, the user program initially sets the address of a register,
assigned between 000000H and 0000FFH, in the I/O address pointer of the intelligent I/O
service descriptor. Then, the user program sets the start address of the memory buffer in the
buffer address pointer.
The DTP operation sequence is almost the same as for external interrupts. The operation is
identical until the CPU activates the hardware interrupt processing microprogram. Then, for the
DTP, control is transferred to the intelligent I/O service processing microprogram, since the ISE
bit read by the CPU within the hardware interrupt processing microprogram indicates the DTP.
Once the intelligent I/O service is activated, a read or write signal is sent to the addresses
external peripheral, and data is transferred between the peripheral and the chip. The external
peripheral must cancel the interrupt request to this chip within three machine cycles after the
transfer is made. When the transfer is completed, the descriptor is updated, and the interrupt
controller generates a signal that clears the transfer cause. Upon receiving the signal to clear
the transfer cause, this resource clears the flip-flop holding the cause and prepares for the next
request from the pin. For details of the intelligent I/O service processing, refer to the F2MC-16LX
Programming Manual.
Figure 15.3-2 Timing to Cancel the External Interrupt at the End of DTP Operation
Edge request or "H" level request
Internal operation
Interrupt cause
* When data is transferred from the I/O register to memory
in the intelligent I/O service
Selecting and
reading
descriptor
Write address
Read address
Address bus pin
Data bus pin
Read data
Read signal
Write data
➀
Write signal
➁
Cancel within three machine cycles.
Data, address
bus
Internal bus
Register
External peripheral
Figure 15.3-3 Sample Interface to the External Peripheral
➀
INT
IRQ
DTP
Cancel within three machine
cycles after transfer.
➁
CORE
MEMORY
MB90590
199
CHAPTER 15 DTP/EXTERNAL INTERRUPTS
15.4 Switching between External Interrupt and DTP Requests
To switch between external interrupt and DTP requests, use the ISE bit in the ICR
register corresponding to this resource, which is in the interrupt controller. Each pin is
individually assigned ICR. Thus, a pin is used for a DTP request if "1" is written to the
ISE bit of the corresponding ICR, and is used for an external interrupt request if "0" is
written to the bit.
■ Switching between External Interrupt and DTP Requests
Figure 15.4-1 Switching between External Interrupt and DTP Requests
Interrupt controller
0
ICR xx
ICR yy
1
F 2 MC-16LX CPU
Pin
External
interrupt/DTP
DTP
External interrupt
200
CHAPTER 15 DTP/EXTERNAL INTERRUPTS
15.5 Notes on Using DTP/External Interrupts
Note carefully the following items when using DTP/external interrupts:
• Conditions on the externally connected peripheral when DTP is used
• Recovery from standby
• External interrupt/DTP operation procedure
• External interrupt request level
■ Notes on Using DTP/External Interrupts
❍ Conditions on the externally connected peripheral when DTP is used
DTP supports only external peripherals that automatically clear a request once a transfer is
completed. The system must be designed so that a transfer request is canceled within three
machine cycles (provisional) after transfer operation starts. Otherwise, this resource assumes
that a transfer request is issued.
❍ Recovery from standby
To use an external interrupt to recover from the standby state in stop mode and watch mode,
use an "H" or "L" level request as an input request. If an edge request is used, recovery from
the standby state in stop mode and watch mode cannot be performed.
❍ External interrupt/DTP operation procedure
To set registers in the external interrupt/DTP, follow the steps below:
1. Set the general-purpose I/O port that is shared with the pin for the external interrupt input as
the input port.
2. Disable the bits corresponding to the enable register.
3. Set the bits corresponding to the request level setting register.
4. Clear the bits corresponding to the cause register.
5. Enable the bits corresponding to the enable register.
(Steps 4. and 5. can be simultaneously performed by word specification.)
To set a register in this resource, ensure that the enable register is disabled. Before enabling
the enable register, ensure that the cause register is cleared. Clearing the cause register
prevents a false interrupt cause from being determined while registers are set or interrupts are
enabled.
201
CHAPTER 15 DTP/EXTERNAL INTERRUPTS
❍ External interrupt request level
To detect an edge for an edge request level, the pulse width must be at least three machine
cycles.
As shown in Figure 15.5-1, when the request input level is related to the level setting, a request
that is input from an external device to the interrupt controller is kept active while the interrupt
request is enable (ENIR:EN=1), even if the request is later canceled because a cause hold
circuit has been installed. To cancel the request to the interrupt controller, the interrupt request
flag bit (EIRR:ER) must be cleared as shown in Figure 15.5-2.
Figure 15.5-1 Clearing the Interrupt Request Flag Bit (EIRR:ER) upon Level Set
Level detection
Interrupt cause
the interrupt request flag bit
(EIRR:ER)
Enable gate
To interrupt
controller
The cause is kept held unless cleared.
Figure 15.5-2 Interrupt Cause and Interrupt Request to the Interrupt Controller while Interrupts are
Enabled
Interrupt cause
(At detecting "H" level)
Interrupt request to
the interrupt controller
202
Cancel the interrupt request
Set inactive when the interrupt request flag bit (EIRR:ER) is cleared.
CHAPTER 16
A/D Converter
This chapter explains the functions and operations of the A/D converter.
16.1 Features of A/D Converter
16.2 Block Diagram of A/D Converter
16.3 A/D Converter Registers
16.4 Operations of A/D Converter
16.5 Conversion Using EI2OS
16.6 Conversion Data Protection
203
CHAPTER 16 A/D Converter
16.1 Features of A/D Converter
The A/D converter converts analog input voltages into digital values. The A/D
converter has the following features:
■ Features of A/D converter
❍ Conversion time:
26.3 µs min. per channel (at 16 MHz machine clock)
❍ RC sequential compare conversion with sample and hold circuit
❍ Resolution of 8 bit or 10 bit
❍ Analog input selected from eight channels by programming
Single conversion mode: One channel is selected for conversion.
Scan conversion mode: Consecutive in multiple channels are converted. Up to eight channels
can be programmed.
Continuous conversion mode: The specified channel are converted repeatedly.
Stop conversion mode: The specified channel are converted, then the system pauses and
stands by for the next activation. (The conversion start points can be
synchronized.)
❍ Interrupt request
At the end of A/D conversion, a relevant interrupt request can be issued to the CPU. This
interrupt can be used to activate the EI2OS, which automatically transfers A/D conversion result
to memory. This feature is suitable for continuous processing.
❍ Selectable activation cause
The activation can be done by software, external trigger (falling edge), or timer (rising edge).
204
CHAPTER 16 A/D Converter
■ Analog Input Enable Register
Always write "1" to the ADER bit corresponding to a pin used as analog input.
Port 6 pins are controlled as described below.
Figure 16.1-1 Analog Input Enable Register
bit
7
Address: 00001BH
ADE7
Read/write→ R/W
Initial value→
1
6
ADE6
R/W
1
5
ADE5
R/W
1
4
ADE4
R/W
1
3
ADE3
R/W
1
2
ADE2
R/W
1
1
ADE1
R/W
1
0
ADE0
R/W
1
0: Port input/output mode
1: Analog input mode
"1" is set upon a reset.
■ Input Impedance
The sampling circuit of the A/D Converter can be represented with the equivalent circuit shown
below.
Driving impedance to an analog input should be lower than 15.5kΩ when the sampling time is
set to 4µs (ST1=0 and ST0=0 at 16MHz machine clock). Otherwise the conversion accuracy will
be worsened. If this is the case, set the sampling time longer (ST1=1 and ST0=1) or add
external capacitor in order to compensate the driving impedance.
Figure 16.1-2 The Sampling Circuit of the A/D Converter can be Represented with the Equivalent Circuit
Analog input
ADC
30 pF Max.
205
CHAPTER 16 A/D Converter
16.2 Block Diagram of A/D Converter
Figure 16.2-1 shows a block diagram of the A/D converter.
■ Block Diagram of A/D Converter
Figure 16.2-1 Block Diagram of A/D Converter
AVcc
AVRH/L
AVss
D/A converter
Sequential compare register
Data bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Input circuit
MPX
Comparator
Decoder
Sample and hold circuit
A/D Data register
ADCR0, ADCR1
A/D control register 0
A/D control register 1
Activation by external trigger
ADCS0, ADCS1
ADTG
Activation by timer
Operation clock
16-bit Reload Timer 1
Prescaler
206
CHAPTER 16 A/D Converter
16.3 A/D Converter Registers
The A/D converter has the following two types of registers:
• A/D Control status register
• A/D Data register
■ A/D Converter Registers
Figure 16.3-1 A/D Converter Register Configuration
15
bit
Address: 000034H
8
7
0
ADCS1
ADCS0
ADCR1
ADCR0
8 bits
8 bits
7
6
5
4
3
2
1
MD1
MD0
ANS2
ANS1
ANS0
ANE2
ANE1
14
13
12
11
10
9
INT
INTE
PAUS
STS1
STS0
STRT
Reserved
bit
15
Address: 000035H BUSY
0
ANE0 A/D Control status
registers
(ADCS0 and ADCS1)
8
bit
Address: 000036H
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
bit
Address: 000037H
15
14
13
12
11
10
9
8
S10
ST1
ST0
CT1
CT0
-
D9
D8
A/D Data registers
(ADCR0 and ADCR1)
207
CHAPTER 16 A/D Converter
16.3.1 A/D Control Status Register 0 (ADCS0)
The control status register 0 (ADCS0) controls the A/D converter and indicates the
status. Do not rewrite ADCS0 during A/D conversion.
■ A/D Control Status Register 0 (ADCS0)
Figure 16.3-2 A/D Control Status Register 0 (ADCS0)
bit
Address: 000034H
Read/write→
Initial value→
7
6
5
4
3
2
1
0
MD1
MD0
ANS2
ANS1
ANS0
ANE2
ANE1
ANE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
ADCS0
[bit 7, bit 6] MD1 and MD0 (A/D converter mode set):
Table 16.3-1 Operation Mode Setting
MD1
MD0
Operation mode
0
0
Single mode. Reactivation during operation is allowed.
0
1
Single mode. Reactivation during operation is not allowed.
1
0
Continuous mode. Reactivation during operation is not allowed.
1
1
Stop mode. Reactivation during operation is not allowed.
❍ Single mode:
A/D conversion is continuously performed from the channel specified with ANS2 to ANS0 to the
channel specified with ANE2 to ANE0. The conversion stops once it has been done for all these
channels.
❍ Continuous mode:
A/D conversion is repeatedly performed from the channel specified with ANS2 to ANS0 to the
channel specified with ANE2 to ANE0.
❍ Stop mode:
A/D conversion is performed from the channel specified with ANS2 to ANS0 to the channel
specified with ANE2 to ANE0, pausing for each channel. The A/D conversion is resumed upon
an activation.
Upon a reset, these bits are initialized to "00".
208
CHAPTER 16 A/D Converter
Notes:
• When activated in the continuous or stop mode, A/D conversion continues until it is stopped by
the BUSY bit.
• The conversion is stopped by writing "0" to the BUSY bit.
• Reactivation disabled in single mode, continuous mode, and stop mode applies to all kinds of
activation by software, an external trigger, and a timer.
[bit 5 to bit 3] ANS2, ANS1, and ANS0 (Analog start channel set):
Use these bits to specify the start channel for A/D conversion.
When the A/D converter is activated, A/D conversion starts from the channel selected with
these bits.
Table 16.3-2 Analog Start Channel Set
ANS2
ANS1
ANS0
Start channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
Notes:
• During A/D conversion, the current conversion channel is read from these bits. If the system is
stopped in the stop mode, the last conversion channel is read.
However, until A/D conversion starts, the previous conversion channel will be read even if these
bits have already been set to the new value.
• Upon a reset, these bits are initialized to "000B".
209
CHAPTER 16 A/D Converter
[bit 2 to bit 0] ANE2, ANE1, and ANE0 (Analog end channel set):
Use these bits to set the A/D conversion end channel.
Table 16.3-3 Analog End Channel Set
ANE2
ANE1
ANE0
End channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
Notes:
• A/D conversion mode select bit (MD1, MD0) and A/D conversion end channel select bit (ANE2,
ANE1, ANE0) should not be set by the read-modify-write instruction after setting the A/D
conversion start channel select bit (ANS2, ANS1, ANS0) to the start channel. The last
conversion channel is read from ANS2, ANS1, and ANS0 bit until starting A/D conversion.
Therefore, if the MD1, MD0 bits and the ANE2, ANE1, and ANE0 bits is set by the read-modifywrite instruction after setting the ANS2, ANS1, and ANS0 bits to the start channel, the value of
the ANE2, ANE1, and ANE0 bits may be re-written to a different value.
• When the same channel is written to ANE2 to ANE0 and ANS2 to ANS0, conversion is
performed for one channel only (single conversion).
• In the continuous or stop mode, operation returns to the start channel specified in ANS2 to
ANS0 after the conversion is completed for the channel specified in ANE2 to ANE0.
• If the ANS value is greater than the ANE value, conversion starts from the ANS channel. Then,
once conversion is complete up to AN7, operation returns to AN0 and conversion is performed
up to the ANE channel.
Example: ANS=6, ANE=3, single mode
Conversion is performed in the following sequence: AN6 → AN7 → AN0 → AN1 → AN2 → AN3
• Upon a reset, these bits are initialized to "000B".
210
CHAPTER 16 A/D Converter
16.3.2 A/D Control Status Register 1 (ADCS1)
The A/D control status register 1 (ADCS1) controls the A/D converter and indicates the
status.
■ A/D Control Status Register 1 (ADCS1)
Figure 16.3-3 A/D Control Status Register 1 (ADCS1)
bit
15
Address: 000035H
BUSY
Read/write→ R/W
Initial value→
0
14
13
12
11
10
9
8
INT
INTE
PAUS
STS1
STS0
STRT
Reserved
R/W
R/W
R/W
R/W
R/W
W
R/W
0
0
0
0
0
0
0
ADCS1
[bit 15] BUSY (busy flag and stop):
• In reading
This bit indicates the A/D converter operation.
This bit is set when A/D conversion starts and is cleared when the conversion ends.
• In writing
Writing "0" to this bit during A/D conversion forces the conversion to terminate.
The above feature is used for forced stop in continuous or stop mode.
"1" cannot be written to the BUSY bit. With a read-modify-write (RMW) instruction, "1" is read
from this bit. In single mode, this bit is cleared at the end of A/D conversion.
In continuous or stop mode, this bit is not cleared until conversion is stopped by writing "0".
This bit is initialized to "0" upon a reset.
Do not perform a forced stop and activation by software simultaneously (BUSY = 0, STRT =
1).
[bit 14] INT (Interrupt):
This bit is set when conversion data is written to ADCR.
An interrupt request is issued if this bit is set while bit 5 (INTE) is "1". In addition, the EI2OS
is activated if it is enabled. Writing "1" has no effect.
This bit is cleared by writing "0" or by the EI2OS interrupt clear signal.
Note:
To clear this bit by writing "0", ensure that A/D conversion is not in progress.
This bit initialized to "0" upon a reset.
211
CHAPTER 16 A/D Converter
[bit 13] INTE (Interrupt enable):
This bit is used to enable or disable interrupts at the end of conversion.
• 0: Interrupts are disabled.
• 1: Interrupts are enabled.
Set this bit when using the EI2OS. The EI2OS is activated when an interrupt request is
issued.
Upon a reset, this bit is initialized to "0".
[bit 12] PAUS (A/D conversion pause):
This bit is set when the A/D conversion is paused.
Only one register is available for storing the A/D conversion result. Therefore, unless the
conversion results are transferred by the EI2OS, the result data would be continuously
updated and destroyed in continuous conversion.
To prevent the above condition, the system is designed so that a data register value must be
transferred by the EI2OS before the next conversion data is saved. A/D conversion pauses
during that period. A/D conversion is resumed at the end of transfer by the EI2OS.
This register is valid only when the EI2OS is used.
Notes:
• For the conversion data protection function, see Section "16.6 Conversion Data Protection".
• Upon a reset, this bit is initialized to "0".
[bit 11, bit 10] STS1 and STS0 (Start source select):
Upon a reset, these bits are initialized to "00".
These bits are used to select the A/D conversion activation source.
Table 16.3-4 Function of STS1,STS0
STS1
STS0
Function
0
0
Activation by software
0
1
Activation by external pin trigger and software
1
0
Activation by 16-bit reload timer and software
1
1
Activation by external pin trigger, 16-bit reload timer, and
software
In a mode allowing two or more activation factors, A/D conversion is activated by the source
that occurs first.
The activation source setting changes as soon as it is updated. Thus, take care when
updating it during A/D conversion.
212
CHAPTER 16 A/D Converter
Notes:
• The external pin trigger is detected by the falling edge. If this bit is updated to external trigger
activation while the external trigger input level is "L", A/D may be activated at once.
• When 16-bit reload timer is selected, the 16-bit Reload Timer 1 is selected.
[bit 9] STRT (Start):
A/D conversion is activated when "1" is written to this bit.
To reactivate A/D conversion, write "1" to this bit again.
Upon a reset, this bit is initialized to "0".
In the stop mode, a reactivation during the operation is not supported. Check the BUSY bit
before writing "1".
Do not perform a forced stop and activation by software simultaneously. (BUSY=0, STRT=1)
The byte/word command reads "1".
The read-modify-write instructions read "0".
[bit 8] Reserved
This is a reserved bit. Always write "0" to this bit.
213
CHAPTER 16 A/D Converter
16.3.3 A/D Data Registers 0/1 (ADCR1 and ADCR0)
These registers are used to store the digital values produced as a result of the
conversion. ADCR1 stores the most significant two bits of the conversion result, while
ADCR0 stores the lower eight bits. These register values are updated each time
conversion is completed. Usually, the final conversion value is stored in these bits.
■ A/D Data Registers 0/1 (ADCR1 and ADCR0)
"0" is always read from the bit 10 to bit 15 of ADCR1.
The conversion data protection function is available. See Section "16.6
Protection".
Conversion Data
Ensure that no data is written to these registers during A/D conversion.
Figure 16.3-4 A/D Data Registers 0/1 (ADCR1 and ADCR0)
bit
7
6
5
4
3
2
1
0
Address: 000036H
Read/write→
D7
D6
D5
D4
D3
D2
D1
D0
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
Initial value→
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
bit
15
14
13
12
11
10
9
8
Address: 000037H
Read/write→
S10
ST1
ST0
CT1
CT0
-
D9
D8
(W)
(W)
(W)
(W)
(W)
(-)
(W)
(W)
Initial value→
(0)
(0)
(0)
(0)
(1)
(0)
(X)
(X)
ADCR0
ADCR1
[bit 15] S10
This bit specifies the resolution of the conversion. When it is set to "0", the 10-bit A/D
conversion is performed. Otherwise the 8-bit A/D conversion is performed and the result is
stored in the D7 to D0.
Reading this bit always results in the reading value "0".
[bit 14, bit 13] ST1 and ST0 (Sampling time):
Table 16.3-5 Function of ST1,ST0
ST1
ST0
Function
0
0
64 machine cycles (4 µs at 16 MHz)
0
1
Reserved
1
0
Reserved
1
1
4096 machine cycles (256 µs at 16 MHz)
These bits determines the duration of the voltage sampling time at the input.
Reading these bits always results in the reading value "00".
214
CHAPTER 16 A/D Converter
[bit 12, bit 11] CT1 and CT0 (Compare time):
Table 16.3-6 Function of CT1,CT0
CT1
CT0
Function
0
0
176 machine cycles (22 µs at 8 MHz)
0
1
352 machine cycles (22 µs at 16 MHz)
1
0
Reserved
1
1
Reserved
These bits determines the duration of the compare operation time.
Do not set to "00" unless the machine clock is 8MHz. In exceeding 8MHz, the conversion
accuracy is not guaranteed.
Reading these bits group always results in the reading value "00".
215
CHAPTER 16 A/D Converter
16.4 Operations of A/D Converter
The A/D converter operates employs the sequential compare technique, and can be
selected from 10-bit or 8-bit resolution.
Since the A/D converter has one register (16 bits) for storing the conversion result, the
A/D data registers 0/1 (ADCR0 and ADCR1) are updated each time conversion is
completed. Thus, the A/D converter alone must not be used for the continuous
conversion. Use the External intelligent I/O service (EI2OS) function to transfer
converted data to memory while conversion is in progress.
■ Single Mode
In this mode, the converter sequentially converts the analog inputs specified with the ANS and
ANE bits. The converter stops operation after the conversion is completed for the end channel
specified with the ANE bits. If the start and end channels are the same (ANS=ANE), conversion
is performed only for the channel specified with ANS.
Example:
ANS = 0 0 0 , ANE = 0 1 1
Start --> AN0 --> AN1 --> AN2 --> AN3 --> End
ANS = 0 1 0 , ANE = 0 1 0
Start --> AN2 --> End
■ Continuous Mode
In this mode, the converter sequentially converts the analog inputs specified with the ANS and
ANE bits. After the conversion is completed for the end channel specified with the ANE bits,
conversion is repeated from the analog inputs of the ANS. If the start and end channels are the
same (ANS=ANE), conversion for the channel specified with ANS is repeated.
Example:
ANS = 0 0 0 , ANE = 0 1 1
Start --> AN0 --> AN1 --> AN2 --> AN3 --> AN0 --> Repeat
ANS = 0 1 0 , ANE = 0 1 0
Start --> AN2 --> AN2 --> AN2 --> Repeat
In continuous mode, conversion is repeated until "0" is written to the BUSY bit. (Writing "0" to
the BUSY bit forces the operation to end.) If the operation is terminated forcibly, conversion
stops before conversion is completed. (Upon a forced stop, the conversion register stores the
last data that has been converted completely.)
216
CHAPTER 16 A/D Converter
■ Stop Mode
In this mode, the converter sequentially converts the analog inputs specified with the ANS and
ANE bits, pausing each time conversion for one channel is completed. To release pausing,
activate the converter again.
After the conversion is completed for the end channel specified with the ANE bits, conversion is
repeated from the analog inputs of the ANS. If the start and end channels are the same
(ANS=ANE), conversion is performed only for one channel.
Example:
ANS = 0 0 0 , ANE = 0 1 1
Start --> AN0 --> Stop --> Restart --> AN1 --> Stop --> Restarte --> AN2 --> Stop -->
--> Restart --> AN3 --> Stop --> Restart --> AN0 --> Repeat
ANS = 0 1 0 , ANE = 0 1 0
Start --> AN2 --> Stop --> Restart --> AN2 --> Stop --> Restarte --> AN2 --> Repeat
Only the activation sources specified with STS1 and STS0 are used.
Using this mode, start of conversion can be synchronized with the activation source.
217
CHAPTER 16 A/D Converter
16.5 Conversion Using EI2OS
Figure 16.5-1 shows the processing flow from the start of A/D conversion to the
transfer of converted data (in continuous mode).
■ Conversion Using EI2OS
Figure 16.5-1 A/D Conversion Processing Flow from the Start to Converted Data Transfer
(in Continuous Mode)
Starting A/D conversion
Sample and hold
Activating EI2OS
Conversion
Transferring data
Interrupt processing
End of conversion
Issuing interrupt
The portion indicated by the star (
218
Clearing interrupt
) is determined according to the EI2 OS setting.
CHAPTER 16 A/D Converter
16.5.1 Starting EI2OS in Single Mode
Follow the steps below to start the EI2OS in single mode.
• To terminate conversion after analog inputs AN1 to AN3 are converted
• To transfer conversion data sequentially to addresses 200H to 205H
• To start conversion by software
• To use the highest interrupt level
■ Starting EI2OS in Single Mode
Table 16.5-1 Example of Starting EI2OS in Single Mode
Settings
Sample program
MOV ICR10 #08H
Function
Specifies the highest interrupt level, EI2OS
activation upon an interrupt, and the descriptor
address setting.
MOV BAPL, #00H
MOV BAPM, #02H
Specifies the transfer destination address of
converted data.
MOV BAPH, #00H
2
EI OS setting
A/D converter
setting
Interrupt
sequence
ICR10:
BAPL:
BAPM:
BAPH:
ISCS:
I/OA:
DCT:
MOV ISCS, #18H
Specifies word data transfer. The transfer
destination address is incremented after
transfer. Data is transferred from I/O to memory.
Transfer is not terminated in response to a
request from a resource.
MOV I/OA, #36H
Transfer source address
MOV DCT, #03H
EI2OS transfer is performed three times. This
count is the same as the conversion count.
MOV ADCS0 #0BH
Specifies single mode, start channel AN1, and
end channel AN3.
MOV ADCS1 #A2H
Specifies activation by software and start of A/D
conversion.
RET
Specifies return from an interrupt.
Interrupt control register
Buffer address pointer, low-order
Buffer address pointer, medium-order
Buffer address pointer, high-order
EI2OS status register
I/O address counter
Data counter
219
CHAPTER 16 A/D Converter
Figure 16.5-2 Flow of Example of Starting EI2OS in Single Mode
Start activation
AN1
Interrupt
EI2 OS transfer
AN2
Interrupt
EI 2OS transfer
AN3
Interrupt
EI 2OS transfer
End
Interrupt sequence
Parallel processing
220
CHAPTER 16 A/D Converter
16.5.2 Starting EI2OS in Continuous Mode
Follow the steps below to start the EI2OS in continuous mode.
• To convert analog inputs AN3 to AN5 and obtain two conversion data items for each
channel
• To transfer conversion data sequentially to addresses 600H to 60BH
• To start conversion by external edge input
• To use the highest interrupt level
■ Starting EI2OS in Continuous Mode
Table 16.5-2 Example of Starting EI2OS in Continuous Mode
Settings
Sample program
MOV ICR10 #08H
Function
Specifies the highest interrupt level, EI2OS
activation upon an interrupt, and the
descriptor address setting.
MOV BAPL, #00H
MOV BAPM, #06H
Specifies the transfer destination address of
converted data.
MOV BAPH, #00H
2
EI OS setting
MOV ISCS, #18H
Specifies word data transfer. The transfer
destination address is incremented after
transfer. Data is transferred from I/O to
memory. Transfer is not terminated in
response to a request from a resource.
MOV I/OA, #36H
Transfer source address
MOV DCT, #06H
EI2OS transfer is performed six times. Data
is transferred for three channels x 2.
MOV ADCS0 #9DH
Specifies continuous mode, start channel
AN3, and end channel AN5.
MOV ADCS1 #A4H
Specifies activation by external edge and
start of A/D conversion.
A/D converter setting
Interrupt sequence
MOV ADCS1 #00H
Specifies return from an interrupt.
RET
ICR10:
BAPL:
BAPM:
BAPH:
ISCS:
I/OA:
DCT:
Interrupt control register
Buffer address pointer, low-order
Buffer address pointer, medium-order
Buffer address pointer, high-order
EI2OS status register
I/O address counter
Data counter
221
CHAPTER 16 A/D Converter
Figure 16.5-3 Flow of Example of Starting EI2OS in Continuous Mode
Start activation
AN3
Interrupt
EI2OS transfer
AN4
Interrupt
EI2OS transfer
AN5
Interrupt
EI2OS transfer
After a total of six transfers
Interrupt sequence
End
222
CHAPTER 16 A/D Converter
16.5.3 Starting EI2OS in Stop Mode
Follow the steps below to start the EI2OS in stop mode.
• To convert analog input AN3 12 times at fixed intervals
• To transfer conversion data sequentially to addresses 600H to 617H
• To start conversion by external edge input
• To use the highest interrupt level
■ Starting EI2OS in Stop Mode
Table 16.5-3 Flow of Example of Starting EI2OS in Stop Mode
Settings
Sample program
MOV ICR10 #08H
Function
Specifies the highest interrupt level, EI2OS
activation upon an interrupt, and the
descriptor address setting.
MOV BAPL, #00H
MOV BAPM, #06H
Specifies the transfer destination address of
converted data.
MOV BAPH, #00H
2
EI OS setting
MOV ISCS, #18H
Specifies word data transfer. The transfer
destination address is incremented after
transfer.
Data is transferred from I/O to memory.
Transfer is not terminated in response to a
request from a resource.
MOV I/OA, #36H
Transfer source address
MOV DCT, #0CH
EI2OS transfer is performed 12 times.
MOV ADCS0 #DBH
Specifies stop mode, start channel AN3, and
end channel AN3 (one-channel conversion).
MOV ADCS1 #A4H
Specifies activation by external edge and
start of A/D conversion.
A/D converter setting
Interrupt sequence
MOV ADCS1 #00H
Specifies return from an interrupt.
RET
ICR10:
BAPL:
BAPM:
BAPH:
ISCS:
I/OA:
DCT:
Interrupt control register
Buffer address pointer, low-order
Buffer address pointer, medium-order
Buffer address pointer, high-order
EI2OS status register
I/O address counter
Data counter
223
CHAPTER 16 A/D Converter
Figure 16.5-4 Flow of Example of Starting EI2OS in Stop Mode
Start activation
AN3 → Interrupt → EI2OS transfer
After 12 transfers
Stop
Activation by external edge
Interrupt sequence
End
224
CHAPTER 16 A/D Converter
16.6 Conversion Data Protection
The A/D converter has a conversion data protection function that enables continuous
conversion and preservation of multiple data items using EI2OS.
Since there is only one A/D data register, its value is updated each time conversion is
completed. Thus, continuous data conversion results in the loss of the previous data
due to storage of the new data. To prevent this situation, the A/D converter pauses
after conversion if the previous data item has not been transferred to memory by
EI2OS. The converted data is not saved until the previous data is transferred to
memory.
■ Conversion Data Protection
The pause is released after data is transferred to memory by EI2OS.
If the previous data has been transferred to memory, the A/D converter continues operation
without pausing.
Note:
This function is related to the INT and INTE bits of ADCS1.
The Conversion data protection function operates only when interrupts are enabled (INTE=1).
If interrupts are disabled (INTE=0), this function is disabled. Continuous A/D conversion results in
loss of previous data, since the converted data items are saved to the register one after another.
If EI2OS is not used while interrupts are enabled (INTE=1), the INT bit is not cleared. Thus, the
conversion data protection function works and the A/D converter pauses. In this case, clearing the
INT bit in the interrupt sequence releases the pause.
If the A/D converter is pausing during EI2OS operation, disabling interrupts may restart the A/D
converter. In this case, the value in the A/D data register may be changed without being
transferred.
Restarting the A/D converter while it is pausing destroys the standby data.
225
CHAPTER 16 A/D Converter
■ Flow of Conversion Data Protection Function (When EI2OS is Used)
Figure 16.6-1 Flow of Conversion Data Protection Function (When EI2OS is Used)
Setting EI 2OS
Starting continuous A/D conversion
Ending of first conversion
Saving the result in the A/D data register
Starting EI2 OS
Ending of second conversion
End EI 2 OS?
NO
Pausing A/D conversion
YES
YES
Saving the result in the A/D data register
End EI2OS?
Ending of third conversion
Starting EI 2OS
NO
Continued
Starting EI 2 OS
Ending the last conversion
Interrupt routine
End
Stopping A/D conversion
■ Notes on using the Conversion Data Protection Function
To start the A/D converter upon an external trigger or internal timer, A/D activation factor bits
STS1 and STS0 of the ADCS1 register are used. Ensure that the input values of the external
trigger or internal timer should be set in side of inactive. If the values are in side of active, A/D
conversion may start immediately.
When setting STS1 and STS0, ensure that "1" (input) is specified for ADTG and "0" (output) is
specified for the internal timer (timer 2).
226
CHAPTER 17
UART0
This chapter explains the UART0 functions and operations.
17.1 Feature of UART0
17.2 UART0 Block Diagram
17.3 UART0 Registers
17.4 UART0 Operation
17.5 Baud Rate
17.6 Internal and External Clock
17.7 Transfer Data Format
17.8 Parity Bit
17.9 Interrupt Generation and Flag Set Timings
17.10 UART0 Application Example
227
CHAPTER 17 UART0
17.1 Feature of UART0
The UART is a serial I/O port for asynchronous or CLK synchronous communication.
The MB90590 series contains three UARTs. The following sections only describe the
functionality of the UART 0. The remaining UARTs have the identical function and the
register addresses should be found in "APPENDIX A I/O Maps".
■ Feature of UART0
UART0 has the following features.
228
•
Full duplex double buffer
•
Supports CLK synchronous and CLK asynchronous start-stop data transfer.
•
Multiprocessor mode support (mode 2)
•
Internally dedicated baud rate generator (12 types)
•
Supports flexible baud rate setting using an external clock input or internal timer.
•
Variable data length (7 to 9 bits, [no parity]; 6 to 8 bits [with parity]).
•
Error detect function (framing, overrun, and parity)
•
Interrupt function (receive and transmit interrupts)
•
NRZ type transfer format
CHAPTER 17 UART0
17.2 UART0 Block Diagram
Figure 17.2-1 shows a block diagram of the UART.
■ UART0 Block Diagram
Figure 17.2-1 UART0 Block Diagram
CONTROL BUS
Receive interrupt
(to CPU)
Dedicated baud rate clock
SCK0
Transmit clock
16-bit reload timer 0
Clock select
circuit
Transmit interrupt
(to CPU)
Receive clock
SCK0
SIN0
Receive control circuit
Transmit control circuit
Start bit detect
circuit
Transmit start circuit
Receive bit counter
Transmit bit counter
Receive parity
counter
Transmit parity
counter
SOT0
Receive status
evaluation circuit
Transmit shifter
Receive shifter
Receive
complete
Transmit start
UIDR
UODR
Receive error
generation signal
for EI2OS (to CPU)
Data bus
UMC
register
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
USR
register
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
URD
register
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
CONTROL BUS
229
CHAPTER 17 UART0
17.3 UART0 Registers
The UART0 has the following four registers:
• Serial mode control register 0
• Serial status register 0
• Serial input data register/Serial output data register 0
• Rate and data register 0
■ UART0 Registers
Figure 17.3-1 UART0 Registers
Serial mode control register 0
bit
Address: 000020H
7
6
5
4
3
2
1
0
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(W)
(1)
(R/W)
(0)
(R/W)
(0)
14
13
12
11
10
9
8
PE
TDRE
RIE
TIE
RBF
TBF
(R)
(0)
(R)
(1)
(R/W)
(0)
(R/W)
(0)
(R)
(0)
(R)
(0)
Read/write→ (R/W)
Initial value→
(0)
UMC0
Serial status register 0
bit
Address: ch.0 000021H
Read/write→
Initial value→
15
RDRF ORFE
(R)
(0)
(R)
(0)
USR0
Serial input data register 0/Serial output data register 0
bit
Address: 000022H
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
14
13
12
11
10
9
8
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(X)
Read/write→ (R/W)
Initial value→
(X)
UIDR0(read)
UODR0(write)
Rate and data register 0
bit
Address: ch.0 000023H
Read/write→ (R/W)
Initial value→
(0)
230
URD0
CHAPTER 17 UART0
17.3.1 Serial Mode Control Register 0 (UMC0)
UMC0 specifies the operation mode of UART0. Set the operation mode while operation
is halted. However, the RFC bit can be accessed during operation.
■ Configuration of Serial Mode Control Register 0 (UMC0)
Figure 17.3-2 Configuration of Serial Mode Control Register 0 (UMC0)
bit
Address: 000020H
7
6
5
4
3
2
1
0
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(W)
(1)
(R/W)
(0)
(R/W)
(0)
Read/write→ (R/W)
Initial value→
(0)
UMC0
■ Serial Mode Control Register 0 (UMC0) Contents
[bit 7] PEN (Parity enable)
Specifies whether to add (for transmit) or detect (for receive) a parity bit in serial data I/O.
Set to "0" in mode 2.
0: Do not use parity
1: Use parity
[bit 6] SBL (Stop bit length)
Specifies the number of stop bits for transmit data. For receive data, the first stop bit only is
recognized and any second stop bit is ignored.
0: 1 bit length
1: 2 bits length
[bit 5, bit 4] MC1, MC0 (Mode control)
These bits control the length of the transferred data. Table 17.3-1 lists the four transfer
modes (data lengths) selectable by these bits.
Table 17.3-1 UART Operation Modes
Mode
MC1
MC0
Data Length*1
0
0
0
7 (6)
1
0
1
8 (7)
2*2
1
0
8+1
3
1
1
9 (8)
*1: The figures enclosed in parentheses indicate the data length with parity.
*2: Mode 2 is used when a number of slave CPUs are connected to a single host CPU. As
the receive parity check function cannot be used, set PEN in the UMC register to "0" (see
Section "17.4 UART0 Operation" for details). The transmit data length is 9 bits and no
parity bit can be added.
231
CHAPTER 17 UART0
[bit 3] SMDE (Synchro mode enable)
This bit selects the transfer method.
0:Start-stop CLK synchronous transfer (clocked synchronous transfer using start and stop
bits.)
1:Start-stop CLK asynchronous transfer
[bit 2] RFC (Receiver flag clear)
Writing "0" to this bit clears the RDRF, ORFE, and PE flags in the USR register. Writing "1"
has no effect. Reading always returns "1".
Note:
When receive interrupts are enabled during UART0 operation, only write "0" to RFC when either
RDRF, ORFE, or PE is "1".
[bit 1] SCKE (SCLK enable)
Writing "1" to this bit in CLK synchronous mode switches the port pin to the UART0 serial
clock output pin and outputs the synchronizing clock. Set to "0" in CLK asynchronous mode
or external clock mode.
0: The pin functions as a general purpose I/O port and does not output the serial clock. The
pin functions as the external clock input pin when the port is set to input mode (DDR=0)
and RC3 to RC0 are set to "1111".
1: The pin functions as the UART0 serial clock output pin.
Note:
The corresponding bit of the Port Direction register should be set to "1" when the port pin is used
as the clock output. This is for UART0 only.
[bit 0] SOE (Serial output enable)
Writing "1" to this bit switches the port pin to the UART0 serial data output pin and enables
serial output.
0: The pin functions as a port pin and does not output serial data.
1: The pin functions as the UART0 serial data output pin (SOT).
Note:
The corresponding bit of the Port Direction register should be set to "1" when the port pin is used
as the serial output. This is for UART0 only.
232
CHAPTER 17 UART0
17.3.2 Serial Status Register 0 (USR0)
USR0 indicates the current state of the UART0 port.
■ Serial Status Register 0 (USR0) Configuration
Figure 17.3-3 Serial Status Register 0 (USR0) Configuration
bit
Address: ch.0 000021H
Read/write→
Initial value→
15
14
RDRF ORFE
(R)
(0)
(R)
(0)
13
12
11
10
9
8
PE
TDRE
RIE
TIE
RBF
TBF
(R)
(0)
(R)
(1)
(R/W)
(0)
(R/W)
(0)
(R)
(0)
(R)
(0)
USR0
■ Serial Status Register 0 (USR0) Contents
[bit 15] RDRF (Receiver data register full)
This flag indicates the state of the UIDR0 (input data register). The flag is set when the
receive data is loaded into UIDR0. Reading UIDR0 or writing "0" to RFC in the UMC0
register clears the flag. If RIE is active, a receive interrupt request is generated when RDRF
is set.
0: No data in UIDR0
1: Data present in UIDR0
[bit 14] ORFE (Over-run/framing error)
The flag is set when an overrun or framing error occurs in receiving. Writing "0" to RFC in the
UMC0 register clears the flag. When this flag is set, the data in UIDR0 is invalid and the load
from the receive shifter to UIDR0 is not performed. If RIE is active, a receive interrupt
request is generated when ORFE is set.
0: No error
1: Error
Table 17.3-2 lists the UIDR0 states after receive completion by RDRF or ORFE.
Table 17.3-2 UIDR State after Receive Completion
RDRF
ORFE
UIDR0 Data State
0
0
Empty
0
1
Framing error
1
0
Valid data
1
1
Overrun error
The data in UIDR is invalid if an overrun or framing error has occurred. Next data can be
received after clearing the flag(s).
233
CHAPTER 17 UART0
[bit 13] PE (Parity error)
The flag is set when a receive parity error occurs. Writing "0" to RFC in the UMC register
clears the flag. When this flag is set, the data in UIDR0 is invalid and the load from the
receive shifter to UIDR0 is not performed. If RIE is active, a receive interrupt request is
generated when PE is set.
0: No parity error
1: Parity error
[bit 12] TDRE (Transmitter data register empty)
This flag indicates the state of the UODR0 (output data register). Writing transmit data to the
UODR0 register clears the flag. The flag is set when the data is loaded to the transmit shifter
and the transmission is started. If TIE is active, a transmit interrupt request is generated
when TDRE is set.
0: Data present in UODR0
1: No data in UODR0
[bit 11] RIE (Receiver interrupt enable)
Enables receive interrupt requests.
0: Disable interrupts.
1: Enable interrupts.
[bit 10] TIE (Transmitter interrupt enable)
Enables transmit interrupt requests. A transmit interrupt is generated immediately if transmit
interrupts are enabled when TDRE is "1".
0: Disable interrupts.
1: Enable interrupts.
[bit 9] RBF (Receiver busy flag)
This flag indicates that UART0 is receiving input data. The flag is set when the start bit is
detected and cleared when the stop bit is detected.
0: Receiver idle
1: Receiver busy
[bit 8] TBF (Transmitter busy flag)
This flag indicates that UART0 is transmitting input data. The flag is set when transmit data
is written to the UODR0 register and cleared when transmission completes.
0: Transmitter idle
1: Transmitter busy
234
CHAPTER 17 UART0
17.3.3 Serial Input Data Register 0 (UIDR0) and Serial Output
Data Register 0 (UODR0)
UIDR0 (serial input data register 0) is the serial data input (for reception) register.
UODR0 (serial output data register 0) is the serial data output (for transmission)
register.
■ Serial Input Data Register 0 (UIDR0) and Serial Output Data Register 0 (UODR0)
Figure 17.3-4 Serial Input Data Register 0 (UIDR0) and Serial Output Data Register 0 (UODR0)
bit
Address: 000022H
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
Read/write→ (R/W)
Initial value→
(X)
UIDR0(read)
UODR0(write)
The most significant two bits (D7 and D6) are ignored if the data length is 6 bits and the most
significant bit (D7) is ignored if the data length is 7 bits. Write to UODR only when TDRE = 1 in
the USR register. Read UIDR only when RDRF = 1 in the USR register.
235
CHAPTER 17 UART0
17.3.4 Rate and Data Register 0 (URD0)
URD0 selects the data transfer speed (baud rate) for UART0. The register also holds
the most significant bit (bit 8) of the data when the transmit data length is 9 bits. Set
the baud rate and parity when UART0 is halted.
■ Configuration of Rate and Data Register 0 (URD0)
Figure 17.3-5 Layout of Rate and Data Register 0 (URD0)
bit
Address: ch.0 000023H
15
14
13
12
11
10
9
8
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(X)
Read/write→ (R/W)
Initial value→
(0)
URD0
■ Rate and Data Register 0 (URD0) Contents
[bit 15, bit 10] BCH, BCH0 (Baud rate clock change)
Specifies the machine cycles for the baud rate clock (see Section "17.5 Baud Rate" for
details).
Table 17.3-3 Setting Example of Machine Cycle
BCH
BCH0
Divider ratio
Setting Example for Each Machine Cycle
0
0
-
Setting disabled
0
1
Divide by 4
For a 16-MHz machine cycle: 16/4 = 4 MHz
1
0
Divide by 3
For a 12-MHz machine cycle: 12/3 = 4 MHz
1
1
Divide by 5
For a 10-MHz machine cycle: 10/5 = 2 MHz
Note:
Do not set BCH and BCH0 to "00".
236
CHAPTER 17 UART0
[bit 14 to bit 11] RC3, RC2, RC1, RC0 (Rate control)
Selects the clock input for the UART0 port (see Section "17.5 Baud Rate" for details).
Table 17.3-4 Clock Input Selection
RC3 to RC0
0000 to 1011
Clock Input
Dedicated baud rate generator
1101
16-bit Reload Timer 0
1111
External clock
Note:
Do not set the rate control bits to "1100" or "1110".
[bit 9] P (Parity)
Sets even or odd parity when parity is active (PEN = 1).
0: Even parity
1: Odd parity
[bit 8] D8
Holds the bit 8 of the transfer data in mode 2 or 3 (9-bit data length) and no parity. Treated
as bit 8 of the UIDR0 register for reading. Treated as bit 8 of the UODR0 register for writing.
The bit has no meaning in the other modes. Write to D8 only when TDRE = 1 in the USR0
register.
237
CHAPTER 17 UART0
17.4 UART0 Operation
Table 17.4-1 lists the operating modes for UART0. Set the value to the UMC register to
switch the modes.
■ UART0 Operation Modes
Table 17.4-1 UART0 Operating Modes
Mode
Parity
Data Length
On
6
Off
7
On
7
Off
8
Off
8+1
On
8
Off
9
Clock Mode
Length of Stop bits*
0
1
2
CLK asynchronous or
CLK synchronous
1 bit or 2 bits
3
*: The length of stop bits can only be set for transmission. The length of receive stop bits is always set to one.
Do not set modes other than those listed above. UART0 does not operate if an invalid mode is set.
Note:
UART0 uses start-stop clock synchronous transfer. Therefore, a start and stop bit are added to the
data even in clock synchronous transfer.
238
CHAPTER 17 UART0
17.5 Baud Rate
When the dedicated baud rate generator is used, the following two types of baud rates
are available:
• CLK synchronous baud rate
• CLK asynchronous baud rate
■ CLK Synchronous Baud Rate
The five URD register, BCH, BCH0, RC3, RC2, and RC1 select the baud rate for CLK
synchronous transfer.
First select the machine clock divider ratio using BCH and BCH0.
BCH BCH0
0
1
1
0
1
1
-->
-->
-->
Divide by 4 [For example, at 16 MHz: 16/4 = 4 MHz]
Divide by 3 [For example, at 12 MHz: 12/3 = 4 MHz]
Divide by 5 [For example, at 10 MHz: 10/5 = 2 MHz]
Then, set the division ratio for the clock selected above in RC3, RC2, and RC1. The following
three settings are available for CLK synchronous transfer. Other settings are prohibited.
RC3
0
0
1
RC2
1
1
0
RC1
0
1
0
-->
-->
-->
Divide by 2 [For example, at 4 MHz: 4/2 = 2.0 M (bps)]
Divide by 4 [For example, at 4 MHz: 4/4 = 1.0 M (bps)]
Divide by 8 [For example, at 4 MHz: 4/8 = 0.5 M (bps)]
(At 2 MHz, the speed becomes half the above examples.)
■ CLK Asynchronous Baud Rate
The six URD register, BCH, BCH0, RC3, RC2, RC1, and RC0 select the baud rate for CLK
asynchronous transfer.
First select the machine clock divider ratio using BCH and BCH0.
BCH BCH0
0
1
1
0
1
1
-->
-->
-->
Divide by 4 [For example, at 16 MHz: 16/4 = 4 MHz]
Divide by 3 [For example, at 12 MHz: 12/3 = 4 MHz]
Divide by 5 [For example, at 10 MHz: 10/5 = 2 MHz]
Then, set the asynchronous transfer clock division ratio for the clock selected above in RC3,
RC2, RC1, and RC0. The following settings are available for CLK synchronous transfer.
239
CHAPTER 17 UART0
0
0
0
--> 8 × Divide by 1
0
1
0
--> 8 × Divide by 2
0
1
1
--> 8 × Divide by 4
1
0
0
--> 8 × Divide by 8
0
0
1
--> Not divided
1
0
1
--> Divide by 8
⎧
⎪
⎪
⎨
⎪
⎩
⎧
⎪
⎨
⎪
⎪
⎩
RC0
⎧
⎪ 0 => Divide by 12
× ⎨
⎪ 1 => Divide by 13
⎪
⎩
×
⎧
⎪
⎪
⎨
⎪
⎩
RC3 RC2 RC1
0
=> Prohibited setting
1
=> Divide by 8
The above 12 baud rates can be selected. The following formula shows how to calculate the
CLK synchronous baud rate.
φ is a machine cycle and m is in decimal notation for RC3 to RC1.
/4
Baud rate =
m-1
[bps] (machine cycle = 16 MHz)
2
Baud rate =
/3
2m-1
/5
Baud rate =
2
m-1
[bps] (machine cycle = 12 MHz)
[bps] (machine cycle = 10 MHz)
Note:
The above formula for m=0 or m=1 cannot be calculated.
Data transfer is possible if the CLK asynchronous baud rate is in the range -1% to +1%. The baud
rate is the CLK asynchronous baud rate divided by 8 x 13, 8 x 12, or 8.
Table 17.5-1 shows examples for 16 MHz, 12 MHz, and 10 MHz machine cycles. However, do not
use the settings marked as "_" in the table.
240
CHAPTER 17 UART0
Table 17.5-1 Baud Rate
CLK asynchronous (µs/Baud)
RC3
RC2
RC1
RC0
16 MHz
12 MHz
10 MHz
BCH/
0=01
BCH/
0=10
BCH/
0=11
CLK
asynchronous
divider
ratio
CLK synchronous (µs/Baud)
16 MHz
12 MHz
10 MHz
BCH/
0=01
BCH/
0=10
BCH/
0=11
0
0
0
0
-
-
48/ 20833
8 × 12
-
-
-
0
0
0
1
26/ 38460
26/ 38460
52/ 19230
8 × 13
-
-
-
0
0
1
0
-
-
-
8
-
-
-
0
0
1
1
2/500000
2/500000
4/250000
8
-
-
-
0
1
0
0
48/ 20833
48/ 20833
96/10417
8 × 12
-
-
-
0
1
0
1
52/ 19230
52/ 19230
104/ 9615
8 × 13
0.5 / 2M
0.5 / 2M
1 / 1M
0
1
1
0
96/10417
96/10417
192/ 5208
8 × 12
-
-
-
0
1
1
1
104/ 9615
104/ 9615
208/ 4808
8 × 13
1 / 1M
1 / 1M
2 / 500K
1
0
0
0
192/ 5208
192/ 5208
-
8 × 12
-
-
-
1
0
0
1
208/ 4808
208/ 4808
416/ 2404
8 × 13
2 / 500K
2 / 500K
4 / 250K
1
0
1
0
-
-
-
8
1
0
1
1
16/ 62500
16/ 62500
32/ 31250
8
-
-
-
241
CHAPTER 17 UART0
17.6 Internal and External Clock
Setting RC3 to RC0 to "1101" selects the clock signal from the 16-bit Reload Timer.
Setting RC3 to RC0 to "1111" selects the external clock. The external clock frequency
has a maximum value of 2 MHz.
■ Internal and External Clock
The CLK asynchronous baud rate is the CLK synchronous baud rate divided by 8. Also, data
transfer is possible if the CLK asynchronous baud rate is in the range -1% to +1% of the
selected baud rate. Table 17.6-1 lists the baud rates when the internal timer is selected as the
clock. The values in this table are calculated for a machine cycle of 7.3728 MHz. However, do
not use the settings marked as "_" in the table.
Baud rate=
φ/X
8 × 2 (n+1)
[bps]
⎛ φ: Machine cycle
⎜
⎜ X: Divider ratio for the count clock source for
⎜
the internal timer
⎜
⎝ n: Reload value (decimal)
⎞
⎟
⎟
⎟
⎟
⎠
Table 17.6-1 Baud Rate and Reload Value
Baud Rate
Reload Value
X = 21
(divide machine cycle by 2)
X = 23
(divide machine cycle by 8)
76800
2
-
38400
5
-
19200
11
2
9600
23
5
4800
47
11
2400
95
23
1200
191
47
600
383
95
300
767
191
The values in the table are the reload values (decimal) for reload count operation of the 16-bit
Reload Timer.
242
CHAPTER 17 UART0
17.7 Transfer Data Format
UART0 only handles NRZ (non-return-to-zero) type data. Figure 17.7-1 shows the
relationship between the transmit/receive clock and the data for CLK synchronous
mode.
■ Transfer Data Format
Figure 17.7-1 Transfer Data Format
SCK0
SIN0, SOT0
0
1
0
StartLSBMSBStop
1
1
0
10
0
1
D8Stop
1
⎫
⎬
⎭
Depends
on the mode.
The transferred data is 01001101B (mode 1) or 101001101B (mode 3).
As shown in Figure 17.7-1, the transfer data always starts with the start bit ("L" level data), the
specified number of data bits are transmitted with the LSB first, then transmission ends with the
stop bit ("H" level data). Always input a clock if external clock operation is selected. When an
internal clock (the dedicated baud rate generator or 16-bit Reload Timer) is selected, the clock
is output continuously. When using CLK synchronous transfer, do not start data transfer until the
selected baud rate clock has stabilized (for two baud rate clock cycles).
When using CLK asynchronous transfer, set the SCKE bit in the UMC0 register to "0" to disable
clock output. The transfer data format of SIN0 and SOT0 is the same as shown in Figure 17.7-1.
243
CHAPTER 17 UART0
17.8 Parity Bit
The P (Prity) bit in the URD0 register specifies whether to use even or odd parity when
parity is enabled. The PEN bit in the UMC0 register enables parity.
■ Parity Bit
Inputting the data shown in Figure 17.8-1 to SIN when even parity is set causes a receive parity
error. Figure 17.8-1 also shows the data transmitted when sending 001101B with even parity
and odd parity.
Figure 17.8-1 Serial Data with Parity Enabled
SIN0
(Receive parity error occurs P = 0)
0
1
0
StartLSBMSBStop
1
1
0
00
1
(Parity)
SOT0
(Even parity transmission P = 0)
0
1
0
StartLSBMSBStop
1
1
0
10
1
(Parity)
SOT0
(Odd parity transmission P = 1)
0
1
0
StartLSBMSBStop
1
1
0
00
1
(Parity)
244
CHAPTER 17 UART0
17.9 Interrupt Generation and Flag Set Timings
UART0 has two interrupt causes and six flags. The two interrupt causes are the receive
and transmit interrupts. The six flags are RDRF, ORFE, PE, TDRE, RBF, and TBF. For
reception, the RDRF, ORFE, and PE flags request an interrupt. For transmission, the
TDRE flag requests an interrupt.
■ Set Timings of the Six Flags
❍ RDRF flag
The RDRF flag is set when receive data is loaded into the UIDR register. The flag is cleared by
writing "0" to RFC in the UMC register or by reading the UIDR0 register.
❍ ORFE flag
The ORFE flag is an overrun or framing error flag. The flag is set when a receive error occurs
and is cleared by writing "0" to RFC in the UMC0 register.
❍ PE flag
The PE flag is a receive parity error flag. The flag is set when a receive parity error occurs and
is cleared by writing "0" to RFC in the UMC0 register. Note that the parity detect function is not
available in mode 2.
❍ TDRE flag
The TDRE flag is set when the UODR0 register becomes empty and is available for writing. The
flag is cleared by writing to the UODR0 register. The above four flags (RDRF, ORFE, PE, and
TDRE) activates transmit or receive interrupts.
❍ RBF and TBF flags
The RBF and TBF flags indicate that reception or transmission is in progress. The RBF flag
becomes active during reception, and the TBF flag becomes active during transmission.
245
CHAPTER 17 UART0
17.9.1 Flag Set Timings for a Receive Operation
(in Mode 0, Mode 1, or Mode 3)
The RDRF, ORFE, and PE flags are set and an interrupt request to the CPU generated
when the final stop bit is detected indicating the end of reception transfer. The data in
UIDR0 is invalid when either the ORFE or PE bit is active.
■ Flag Set Timings for a Receive Operation (in Mode 0, Mode 1, or Mode 3)
Figure 17.9-1, Figure 17.9-2, and Figure 17.9-3 show the set timings of the RDRF, ORFE, and
PE flags respectively.
Figure 17.9-1 RDRF Set Timing (Mode 0, Mode 1, or Mode 3)
Stop
Data
(Stop)
RDRF
Receive interrupt
Figure 17.9-2 ORFE Set Timing (Mode 0, Mode 1, or Mode 3)
Data
Stop
Data
RDRF = 1
RDRF = 0
ORFE
ORFE
Receive interrupt
Stop
Receive interrupt
(Overrun error)
(Framing error)
Figure 17.9-3 PE Set Timing (Mode 0, Mode 1, or Mode 3)
Data
PE
Receive interrupt
246
Stop
(Stop)
CHAPTER 17 UART0
17.9.2 Flag Set Timings for a Receive Operation (in Mode 2)
The RDRF flag is set when the final stop bit is detected and reception transfer ends
with the last data bit (D8) having the value "1".
The ORFE flag is set when the final stop bit is detected, irrespective of the value of the
last data bit (D8). The data in UIDR0 is invalid when the ORFE bit is active.
The interrupt request to the CPU is generated when either of the flags are set (see
Section "17.10 UART0 Application Example" for details on using mode 2).
■ Flag Set Timings for a Receive Operation (in Mode 2)
Figure 17.9-4 RDRF Set Timing (Mode 2)
Data
D6
D7
D8
Stop
(Stop)
RDRF
Receive interrupt
Figure 17.9-5 ORFE Set Timing (Mode 2)
Data
D7
D8
Stop
Data
RDRF = 1
RDRF = 0
ORFE
ORFE
Receive interrupt
D7
D8
Stop
Receive interrupt
(Overrun error)
(Framing error)
247
CHAPTER 17 UART0
17.9.3 Flag Set Timings for a Transmit Operation
TDRE is set and an interrupt request to the CPU is generated when the data written in
UODR0 register is transferred to the internal shift register and the next data can be
written to UODR0.
■ Flag Set Timings for a Transmit Operation
Figure 17.9-6 TDRE Set Timing (Mode 0)
UODR write
TDRE
Interrupt request to the CPU
Transmit interrupt
SOT0 output
ST D0 D1
ST: Start bit
248
D2 D3 D4
D5 D6 D7
D0 to D7: Data bits
SP
SP ST D0 D1
SP: Stop bit
D2 D3
CHAPTER 17 UART0
17.9.4 Status Flag During Transmit and Receive Operation
RBF is set when the start bit is detected, and cleared when a stop bit is detected. The
receive data in UIDR0 at the RBF clear timing is not yet valid. The data in UIDR0
becomes valid at the RDRF set timing.
■ Status Flag during Transmit and Receive Operation
Figure 17.9-7 shows the relationship between the RBF and receive interrupt flag timing.
Figure 17.9-7 RBF Set Timing (Mode 0)
SIN0 input
ST D0 D1
D2 D3 D4
D5 D6 D7
SP
RBF
RDRF, PE, ORFE
ST: Start bit
D0 to D7: Data bits
SP: Stop bit
Writing the transmission data to UODR0 sets TBF. TBF is cleared when transmission
completes.
Figure 17.9-8 TBF Set Timing (Mode 0)
UODR write
ST D0 D1
SOT0 output
D2 D3 D4
D5 D6 D7
SP
SP
TBF
ST: Start bit
D0 to D7: Data bits
SP: Stop bit
Note:
Receive operation starts after releasing a reset unless the SIN input pin is fixed at "1". Therefore,
before setting the mode, write "0" to RFC in the UMC0 register to clear any receive flags that have
been set.
Set the communication mode when the RBF and TBF flags in the USR0 register are "0". The data
transmitted and received during mode setting cannot be guaranteed.
■ EI2OS (Extended intelligent I/O service)
See the Section "3.7 Extended Intelligent I/O Service (EI2OS)" for details on EI2OS.
249
CHAPTER 17 UART0
17.10 UART0 Application Example
Mode 2 is used when a number of slave CPUs are connected to a host CPU (see Figure
17.10-1).
■ Application Example
Figure 17.10-1 RBF Set Timing (Mode 0)
SIN0 input
ST D0 D1
D2 D3 D4
D5 D6 D7
SP
RBF
RDRF, PE, ORFE
ST: Start bit
D0 to D7: Data bits
SP: Stop bit
As shown in Figure 17.10-2, communication starts with the host CPU transmitting address data.
The ninth bit (D8) of the address data is set to "1". The address selects the slave CPU with
which communication will be established. The selected slave CPU communicates with the host
CPU using a protocol determined by the user. In normal data, D8 is set to "0". Unselected slave
CPUs wait in standby until the next communication session starts. Figure 17.10-3 shows a
flowchart of operation in this mode.
Because the parity check function is not available in this mode, set the PEN bit in the UMC0
register to "0".
Figure 17.10-2 Example System Configuration Using Mode 2
SOT0
SIN0
Host CPU
250
SOT0 SIN0
SOT0 SIN0
Slave CPU #0
Slave CPU #1
CHAPTER 17 UART0
Figure 17.10-3 Communication Flowchart for Mode 2 Operation
(Host CPU)(Slave CPU)
Start
Start
Set the transfer mode to 3
Set the transfer mode to 2
Set the slave CPU selection
in D0 to D7. Set D8 to "1".
Transfer a byte.
Receive a byte
NO
Selected?
Set D8 to "0" and perform
communications
End
YES
Set the transfer mode to 3
and enable SOT0 output
Perform communications
with the master CPU
Use the status flag to
confirm transfer completion,
then set the transfer mode to
2 and disable SOT0 output
251
CHAPTER 17 UART0
252
CHAPTER 18
SERIAL I/O
This chapter explains the functions and operations of the serial I/O.
18.1 Outline of Serial I/O
18.2 Serial I/O Registers
18.3 Serial I/O Prescaler (CDCR)
18.4 Serial I/O Operation
18.5 Negative Clock Operation
253
CHAPTER 18 SERIAL I/O
18.1 Outline of Serial I/O
The serial I/O operates in two modes:
• Internal shift clock mode: Data is transferred in synchronization with the internal
clock.
• External shift clock mode:Data is transferred in synchronization with the clock
supplied via the external pin (SCK3). By manipulating the
general-purpose port sharing the external pin (SCK3), data
can also be transferred by a CPU instruction in this mode.
■ Serial I/O Block Diagram
This block diagram is a serial I/O interface that allows data transfer using clock synchronization.
The interface consists of a single eight-bit channel. Data can be transferred from the LSB or
MSB.
Figure 18.1-1 Extended Serial I/O Interface Block Diagram
Internal data bus
(MSB first) D7 to D0
D7 to D0 (LSB first)
Transfer direction selection
SIN3
Read
SDR (Serial data register)
Write
SOT3
SCK3
Control circuit
Shift clock counter
Internal clock
2
SMD2
1
0
SMD1 SMD0
SIE
SIR
BUSY
STOP
STRT MODE
Interrupt
request
Internal data bus
254
BDS
SOE
SCOE
CHAPTER 18 SERIAL I/O
18.2 Serial I/O Registers
The serial I/O has the following two registers:
• Serial mode control status register
• Serial data register
■ Serial I/O Registers
Figure 18.2-1 Serial I/O Registers
bit
15
14
13
Address: 00002DH SMD2 SMD1 SMD0
12
11
10
9
8
SIE
SIR
BUSY
STOP
STRT
bit
7
6
5
4
3
2
1
0
Address: 00002CH
-
-
-
-
MODE
BDS
SOE
SCOE
bit
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Address: 00002EH
Serial mode control status
register (SMCS)
Serial data register (SDR)
255
CHAPTER 18 SERIAL I/O
18.2.1 Serial Mode Control Status Register (SMCS)
The serial mode control status register (SMCS) controls the serial I/O transfer mode.
■ Serial Mode Control Status Register (SMCS)
Figure 18.2-2 Serial Mode Control Status Register (SMCS)
SMCS
bit
Address: 00002DH
SMCS
bit
Address: 00002CH
15
14
13
SMD2 SMD1 SMD0
12
11
10
9
8
Initial value
SIE
SIR
BUSY
STOP
STRT
00000010B
R/W
R/W
R/W
R/W
R/W
↑
*1
R
R/W
R/W
↑
*2
7
6
5
4
3
2
1
0
Initial value
-
-
-
-
MODE
BDS
SOE
SCOE
----0000B
R/W
R/W
R/W
R/W
*1: Only "0" can be written.
*2: Only "1" can be written. "0" is always read.
■ Bit functions of Serial Mode Control Status Register (SMCS)
[bit 3] Serial mode selection bit (MODE)
The serial mode selection bit is used to select the conditions to start the transfer operation
from the stop state. This bit must not be updated during operation.
Table 18.2-1 Setting the Serial Mode Selection Bit
MODE
Operation
0
Transfer starts when STRT=1. [Default]
1
Transfer starts when the serial data register is read or written to.
This bit is initialized to "0" upon a reset, and can be read or written to. To activate the
intelligent I/O service, ensure that "1" is written to this bit.
[bit 2] Bit direction select bit (BDS)
When serial data is input or output, this bit determines from which bit data is to be
transferred first, the least significant bit (LSB first) or the most significant bit (MSB first), as
shown in Table 18.2-2.
Table 18.2-2 Setting the Transfer Direction Selection Bit
256
0
LSB first [default]
1
MSB first
CHAPTER 18 SERIAL I/O
Note:
Set the transfer direction selection bit before writing data to SDR.
[bit 1] Serial output enable bit (SOE: Serial out enable)
This bit controls the output from the serial I/O output external pins (SOT3) as shown in Table
18.2-3.
Table 18.2-3 Setting the Serial Output Enable Bit
0
General-purpose port pin [default]
1
Serial data output
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit 0] Shift clock output enable bit (SCOE: SCK3 output enable)
This bit controls the output from the shift clock I/O output external pin (SCK3) as shown in
Table 18.2-4.
Table 18.2-4 Setting the Shift Clock Output Enable Bit
0
General-purpose port pin, transfer for each instruction [default]
1
Shift clock output pin
Ensure that "0" is written to this bit when data is transferred for each instruction in external
shift clock mode.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
257
CHAPTER 18 SERIAL I/O
[bit 15 to bit 13] Shift clock selection bits (SMD2, SMD1, SMD0: Serial shift clock mode)
These bits are used to select the serial shift clock mode, as shown in Table 18.2-5.
Table 18.2-5 Setting the Serial Shift Clock Mode
SMD2
SMD1
SMD0
φ=16MHz
div=4
φ=8MHz
div=4
φ=4MHz
div=4
0
0
0
2 MHz
1 MHz
500 kHz
0
0
1
1 MHz
500 kHz
250 kHz
0
1
0
250 kHz
125 kHz
62.5 kHz
0
1
1
125 kHz
62.5 kHz
31.25 kHz
1
0
0
62.5 kHz
31.25 kHz
15.625 kHz
1
0
1
External shift clock mode
1
1
0
Reserved
1
1
1
Reserved
div
M1
DIV3
DIV2
DIV1
DIV0
Recommended
machine cycle
3
1
1
1
0
1
6 MHz
4
1
1
1
0
0
8 MHz
5
1
1
0
1
1
10 MHz
6
1
1
0
1
0
12 MHz
7
1
1
0
0
1
14 MHz
8
1
1
0
0
0
16 MHz
For details, see "18.3 Serial I/O Prescaler (CDCR)".
These bits are initialized to "000" upon a reset. These bits must not be updated during data
transfer.
Five types of internal shift clock and an external shift clock are available. Do not set "110" or
"111" in SMD2, SMD1, and SMD0 as these values are reserved.
Shift operation can be performed for each instruction by specifying SCOE =0 during clock
selection and by using the ports that share the SCK3 pin.
[bit 12] Serial I/O interrupt enable bit (SIE: Serial I/O interrupt enable)
This bit controls the serial I/O interrupt request as shown in Table 18.2-6.
Table 18.2-6 Setting the Interrupt Request Enable Bit
0
Serial I/O interrupt disabled [default]
1
Serial I/O interrupt enabled
This bit is initialized to "0" upon a reset. This bit is readable and writable.
258
CHAPTER 18 SERIAL I/O
[bit 11] Serial I/O interrupt request bit (SIR: Serial I/O interrupt request)
When serial data transfer is completed, "1" is set to this bit. If this bit is set while interrupts
are enabled (SIE=1), an interrupt request is issued to the CPU. The clear condition varies
with the MODE bit.
When "0" is written to the MODE bit, the SIR bit is cleared by writing "0". When "1" is written
to the MODE bit, the SIR bit is cleared by reading or writing to SDR. When the system is
reset or "1" is written to the STOP bit, the SIR bit is cleared regardless of the MODE bit
value.
Writing "1" to the SIR bit has no effect. "1" is always read by a read operation of a readmodify-write instruction.
[bit 10] Transfer status bit (BUSY)
The transfer status bit indicates whether serial transfer is being executed.
Table 18.2-7 Setting the Transfer Status Bit
BUSY
Operation
0
Stopped, or standby for serial shift data register R/W [default]
1
Serial transfer
This bit is initialized to "0" upon a reset. This is a read-only bit.
[bit 9] Stop bit (STOP)
The stop bit forcibly terminates serial transfer. When "1" is written to this bit, the transfer is
stopped.
Table 18.2-8 Setting the Stop Bit
STOP
Operation
0
Normal operation
1
Transfer stop by STOP=1 [default]
This bit is initialized to "1" upon a reset. This bit is readable and writable.
[bit 8] Start bit (STRT: Start)
The start bit activates serial transfer. Writing "1" to this bit starts the data transfer in the
stopped status.
Writing "1" is ignored while the system is performing serial transfer or standing by for a serial
shift data register read or write. Writing "0" has no effect. "0" is always read for read
operation.
259
CHAPTER 18 SERIAL I/O
18.2.2 Serial Shift Data Register (SDR)
This serial data register stores the serial I/O transfer data. During transfer, the SDR
must not be read or written to.
■ Serial Shift Data Register (SDR)
Figure 18.2-3 Serial Shift Data Register (SDR)
bit
Address: 00002EH
Read/write→
Initial value→
260
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
SDR
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
(undefined)
CHAPTER 18 SERIAL I/O
18.3 Serial I/O Prescaler (CDCR)
The Serial I/O Prescaler provides the shift clock for the Serial I/O.
The operation clock for the Serial I/O is obtained by dividing the machine clock. The
Serial I/O is designed so that a constant baud rate can be obtained for a variety of
machine clocks by the user of the communication prescaler. The CDCR register
controls the machine clock division.
■ Serial I/O Prescaler (CDCR)
Figure 18.3-1 Serial I/O Prescaler (CDCR)
bit
Address: 00006DH
Read/write→
Initial value→
15
14
13
12
11
10
9
8
MD
-
-
-
DIV3
DIV2
DIV1
DIV0
R/W
0
-
-
-
R/W
1
R/W
1
R/W
1
R/W
1
CDCR
[bit 15] MD (Machine clock divide mode select):
This bit is used to control the operation of the communication prescaler.
0: The Serial I/O Prescaler is disabled.
1: The Serial I/O Prescaler is enabled.
[bit 11 to bit 8] DIV3 to DIV0 (Divide 3 to Divide 0):
These bits are used to determine the machine clock division ratio.
Table 18.3-1 Machine Clock Division Ratio
DIV3 to DIV0
Division ratio
1101B
3
1100B
4
1011B
5
1010B
6
1001B
7
1000B
8
Note:
When the division ratio is changed, allow two cycles for the clock to stabilize before starting
communication.
261
CHAPTER 18 SERIAL I/O
18.4 Serial I/O Operation
The extended serial I/O interface consists of the serial mode control status register
(SMCS) and serial shift data register (SDR), and is used for input and output of 8-bit
serial data.
■ Serial I/O Operation
The bits in the shift register are output in bit series via the serial output pin (SOT3 pin) at the
falling edge of the serial shift clock (external clock or internal clock). The bits are input in bit
series to the shift register (SDR) via the serial input pin (SIN3 pin) at the rising edge of the serial
shift clock. The shift direction (transfer from MSB or LSB) can be specified by the direction
specification bit (BDS) of the serial mode control status register (SMCS).
At the end of serial data transfer, this block is stopped or stands by for a read or write of the
data register according to the MODE bit of the serial mode control status register (SMCS). To
start transfer from the stop or standby state, follow the procedure below.
• To resume operation from the stop state, write "0" to the STOP bit and "1" to the STRT bit.
(The STOP and STRT bits can be set simultaneously.)
• To resume operation from the serial shift data register R/W standby state, read or write to the
data register.
262
CHAPTER 18 SERIAL I/O
18.4.1 Shift Clock
There are two modes of shift clock: internal or external shift clock. These two modes
are selected by setting the SMCS. To switch the modes, ensure that serial I/O transfer
is stopped. To check whether the serial I/O transfer is stopped, read the BUSY bit.
■ Internal Shift Clock Mode
In internal shift clock mode, data transfer is based on the internal clock. As a synchronization
timing output, a shift clock of 50% duty ratio can be output from the SCK3 pin. Data is
transferred at one bit per clock. The transfer speed (baud rate) is expressed as follows:
"A" is the division ratio indicated by the SMD bits of SMCS. The value can be 21, 22, 24, 25, or
2 6.
Transfer speed (s)=
A div
Internal clock machine cycle (Hz)
Table 18.4-1 Formulas for Calculation Baud Rate in Internal Shift Clock Mode
SMD2
SMD1
SMD0
φ / div = 4 MHz
φ / div = 2 MHz
φ / div = 1 MHz
0
0
0
2 MHz
1 MHz
500 kHz
(φ/div)/21
0
0
1
1 MHz
500 kHz
250 kHz
(φ/div)/22
0
1
0
250 kHz
125 kHz
62.5 kHz
(φ/div)/24
0
1
1
125 kHz
62.5 kHz
31.25 kHz
(φ/div)/25
1
0
0
62.5 kHz
31.2 kHz
15.625 kHz
(φ/div)/26
Formula
See Table 18.3-1 for the div value.
■ External Shift Clock Mode
In external shift clock mode, the data transfer is based on the external clock supplied via the
SCK3 pin. Data is transferred at one bit per clock.
The transfer speed can be between DC and 1/(8 machine cycles). For example, the transfer
speed can be up to 2 MHz when 1 machine cycle is equal to 62.5 ns.
A data bit can also be transferred by instruction, which is enabled as described below.
Select external shift clock mode, and write "0" to the SCOE bit of SMCS. Then, write "1" to the
direction register for the port sharing the SCK3 pin, and set the port in output mode. Then, when
"1" and "0" are written to the data register (PDR) of the port, the port value output via the SCK3
pin is fetched as the external clock, and transfer starts. Ensure that the shift clock starts from
"H".
Note:
The SMCS or SDR must not be written to during serial I/O operation.
263
CHAPTER 18 SERIAL I/O
18.4.2 Serial I/O Operation
There are four serial I/O operation statuses:
• STOP
• Halt
• SDR R/W standby
• Transfer
■ Serial I/O Operation
❍ STOP
The STOP state is initiated upon RESET or when "1" is written to the STOP bit of SMCS. The
shift counter is initialized, and "0" is written to SIR.
To resume operation from the STOP state, write "0" to STOP and "1" to STRT. (These two bits
can be written to simultaneously.) Since the STOP bit overrides the STRT bit, transfer cannot be
started by writing "1" to STRT while "1" is written to STOP.
❍ Halt
When transfer is completed while the MODE bit is "0", "0" is set to BUSY and "1" is set to SIR of
the SMCS, the counter is initialized, and the system halts. To resume operation from the halt
state, write "1" to STRT.
❍ Serial shift data register R/W standby
When transfer is completed while the MODE bit is "1", "0" is set to BUSY and "1" is set to SIR of
the SMCS, and the system becomes the serial shift data register R/W standby state. If the
interrupt enable register is valid set, an interrupt signal is output from this block.
To resume operation from R/W standby state, read or write to the serial shift data register. This
sets the BUSY bit to "1" and restarts data transfer.
❍ Transfer
"1" is set to the BUSY bit and serial transfer is being performed. According to the MODE bit, it is
transitted to the halt state or R/W standby state.
Figure 18.4-1 is diagrams of the operation transitions.
264
CHAPTER 18 SERIAL I/O
Figure 18.4-1 Extended Serial I/O Interface Operation Transitions
STOP
STRT=0, BUSY=0
MODE=0
MODE=0
&
STOP=0
&
END
STOP=0
&
STRT=1
Reset
STOP=0 & STRT=0
End of transfer
STRT=0, BUSY=0
STOP=1
STOP=1
STOP=1
STOP=0
&
STRT=1
Transfer
Serial shift data register R/W standby
MODE=1 & END & STOP=0
STRT=1, BUSY=1
STRT=1, BUSY=0
MODE=1
SDR R/W & MODE=1
Serial data
Figure 18.4-2 Serial Shift Data Register Read/write
Data bus
Data bus
Read
Write
Interrupt output
SOT3
SIN3
Extended serial I/O
interface
Read
Write
➁
CPU
➀
Interrupt input
Data bus Interrupt controller
1. If "1" is written to MODE, transfer ends according to the shift clock counter. The read/write
standby state starts when "1" is written to SIR. If "1" is written to the SIE bit, an interrupt
signal is generated. No interrupt signal is generated when SIE is inactive or transfer has
been terminated by writing "1" to STOP.
2. Reading or writing to the serial shift data register clears the interrupt request and starts serial
transfer.
265
CHAPTER 18 SERIAL I/O
18.4.3 Shift Operation Start/Stop Timing
To start the shift operation, set the STOP bit to "0" and the STRT bit to "1" in SMCS.
The system may stop the shift operation at the end of transfer or when "1" is set in the
STOP bit.
• Stop by STOP=1 ->
The system stops with SIR=0 regardless of the MODE
bit.
• Stop by end of transfer -> The system stops with SIR=1 regardless of the MODE
bit.
Regardless of the MODE bit, the BUSY bit becomes "1" during serial transfer and
becomes "0" during stop or R/W standby state. To check the transfer status, read this
bit.
■ Shift Operation Start/Stop Timing
❍ Internal shift clock mode (LSB first)
Figure 18.4-3 Shift Operation Start/Stop Timing (Internal Clock)
"1" output
SCK3
(Transfer start)
STRT
(Transfer end)
If MODE=0
BUSY
SOT3
DO0
DO7 (Data maintained)
❍ External shift clock mode (LSB first)
Figure 18.4-4 Shift Operation Start/Stop Timing (External Clock)
SCK3
(Transfer start)
STRT
(Transfer end)
If MODE=0
BUSY
SOT3
266
DO0
DO7 (Data maintained)
CHAPTER 18 SERIAL I/O
❍ External shift clock mode with instruction shift (LSB first)
Figure 18.4-5 Shift Operation Start/Stop Timing (External Shift Clock Mode with Instruction Shift)
SCK="0" in PDR
SCK3
STRT
SCK="0" in PDR
SCK="1" in PDR (Transfer end)
If MODE=0
BUSY
DO7 (Data maintained)
DO6
SOT3
* For an instruction shift, "H" is output when "1" is written to the bit corresponding to SCK of PDR,
and "L" is output when "0" is written. (When SCOE=0 in external shift clock mode)
❍ Stop by STOP=1 (LSB first, internal clock)
Figure 18.4-6 Stop Timing when "1" is Written to the STOP Bit
"1" output
SCK3
(Transfer start)
(Transfer stop)
If MODE=0
STRT
BUSY
STOP
SOT3
DO3
DO4
DO5 (Data maintained)
Note:
DO7 to DO0 indicate output data.
During serial data transfer, data is output from the serial output pin (SOT3) at the falling edge of
the shift clock, and input from the serial input pin (SIN3) at the rising edge.
267
CHAPTER 18 SERIAL I/O
Figure 18.4-7 Serial Data I/O Shift Timing
❍ LSB first (When the BDS bit is "0")
SCK3
SIN Input
SIN3
D10
D11
D12
D13
SOT Output
D14
D15
D16
D17
SOT3
DO0
DO1
DO2
DO4
DO5
DO6
DO7
DO3
❍ MSB first (When the BDS bit is "1")
SCK3
SIN3
SIN Input
D17
D16
D15
D14
D13
D12
D11
D10
DO4
DO3
DO2
DO1
DO0
SOT Output
SOT3
268
DO7
DO6
DO5
CHAPTER 18 SERIAL I/O
18.4.4 Interrupt Function of the Extended Serial I/O Interface
The extended serial I/O interface can issue an interrupt request to the CPU. At the end
of data transfer, the SIR bit is set as an interrupt flag. When "1" is written to the
interrupt enable bit (SIE bit) of SMCS, an interrupt request is issued to the CPU.
■ Interrupt Function of the Extended Serial I/O Interface
Figure 18.4-8 Interrupt Signal Output Timing of the Extended Serial I/O Interface
SCK3
(Transfer end)
BUSY
Note: When MODE=1
SIE=1
SIR
SDR RD/WR
SOT3
DO6
DO7 (Data is maintained.)
269
CHAPTER 18 SERIAL I/O
18.5 Negative Clock Operation
MB90590 series supports the negative clock operation of the Serial I/O. In this
operation, the shift clock signal is simply reversed by a inverter. Therefore, the
definition of the shift clock signal in "18.4.1 Shift Clock" is inverted from the logic "L"
level to logic "H" level, from the negative edge to the positive edge and vise-versa.
This is the same for both the serial clock input and output.
■ Negative Clock Operation
Figure 18.5-1 Negative Clock Operation
Serial edge selector register
bit
Address: 00002FH
Read/write→
Initial value→
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
NEG
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(R/W)
(0)
Table 18.5-1 Setting the NEG Bit
NEG
270
Operation
0
Normal operation [default]
1
The shift clock signal is inverted
SES
CHAPTER 19
CAN CONTROLLER
This chapter explains the functions and operations of the CAN controller.
19.1 Features of CAN Controller
19.2 Block Diagram of CAN Controller
19.3 List of Overall Control Registers
19.4 List of Message Buffers (ID Registers)
19.5 List of Message Buffers (DLC Registers and Data Registers)
19.6 Classifying the CAN Controller Registers
19.7 Transmission of CAN Controller
19.8 Reception of CAN Controller
19.9 Reception Flowchart of CAN Controller
19.10 How to Use the CAN Controller
19.11 Procedure for Transmission by Message Buffer (x)
19.12 Procedure for Reception by Message Buffer (x)
19.13 Setting Configuration of Multi-level Message Buffer
19.14 Precautions when Using CAN Controller
271
CHAPTER 19 CAN CONTROLLER
19.1 Features of CAN Controller
The CAN controller is a module built into a 16-bit microcontroller (F2MC-16LX). The
CAN (Controller Area Network) is the standard protocol for serial communication
between automobile controllers and is widely used in industrial applications.
■ Features of CAN Controller
The CAN controller has the following features:
❍ Conforms to CAN Specification Version 2.0 Part A and B
Supports transmission/reception in standard frame and extended frame formats
❍ Supports transmitting of data frames by receiving remote frames
❍ 16 transmitting/receiving message buffers
29-bit ID and 8-byte data
Multi-level message buffer configuration
❍ Supports full-bit comparison, full-bit mask and partial bit mask filtering
Two acceptance mask registers in either standard frame format or extended frame formats
❍ Bit rate programmable from 10 Kbps to 1 Mbps (A minimum 8 MHz machine clock is
required if 1 Mbps is used)
272
CHAPTER 19 CAN CONTROLLER
19.2 Block Diagram of CAN Controller
Figure 19.2-1 shows a block diagram of the CAN controller.
■ Block Diagram of CAN Controller
Figure 19.2-1 Block Diagram of CAN Controller
F2MC-16LX
TQ (Operating clock)
bus
Prescaler
1 to 64 frequency division
Clock
Bit timing generation
SYNC, TSEG1, TSEG2
PSC
TS1
BTR
TS2
RSJ
TOE
TS
RS
CSR
HALT
NIE
NT
Node status change
interrupt generation
IDLE, INT, SUSPND,
transmit, receive,
ERR, OVRLD
Bus state
machine
Node status
change interrupt
NS1, 0
Error
control
RTEC
Transmitting/receiving
sequencer
BVALR
TREQR
TBFx, clear
Transmitting
buffer x decision
TBFx
Data
counter
Error frame
generation
Acceptance
filter control
Overload
frame
generation
TDLC RDLC
TBFx
IDSEL
BITER, STFER,
CRCER, FRMER,
ACKER
TCANR
Output
driver
ARBLOST
TX
TRTRR
TCR
Stuffing
Transmission
shift register
RFWTR
TBFx, set, clear
Transmission
complete
interrupt
Transmission complete
interrupt generation
TDLC
TIER
CRC
generation
ACK
generation
CRCER
RBFx, set
RDLC
RCR
Reception
complete
interrupt
Reception complete
interrupt generation
RIER
RBFx, TBFx, set, clear
CRC generation/error
check
Receive shift
register
STFER
Destuffing/stuffing
error check
RRTRR
RBFx, set
IDSEL
ROVRR
ARBLOST
AMSR
AMR0
0
1
Acceptance
filter
Receiving buffer x
decision
BITER
Bit error
check
ACKER
Acknowledgment
error check
AMR1
RBFx
IDR0 to 15
DLCR0 to 15
DTR0 to 15
RAM
RAM address
generation
Arbitration
check
FRMER
Form error
check
PH1
Input
latch
RX
RBFx, TBFx, RDLC, TDLC, IDSEL
LEIR
LDER
273
CHAPTER 19 CAN CONTROLLER
19.3 List of Overall Control Registers
Table 19.3-1 lists overall control registers.
■ List of Overall Control Registers
Table 19.3-1 List of Overall Control Registers (1/2)
Address
Register
CAN0
CAN1
000070H
000080H
000071H
000081H
000072H
000082H
000073H
000083H
000074H
000084H
000075H
000085H
000076H
000086H
000077H
000087H
000078H
000088H
000079H
000089H
00007AH
00008AH
00007BH
00008BH
00007CH
00008CH
00007DH
00008DH
00007EH
00008EH
00007FH
00008FH
001C00H
001D00H
001C01H
001D01H
001C02H
001D02H
001C03H
001D03H
001C04H
001D04H
001C05H
001D05H
001C06H
001D06H
001C07H
001D07H
274
Abbreviation
Access
Initial Value
Message buffer valid
register
BVALR
R/W
00000000 00000000
Transmit request
register
TREQR
R/W
00000000 00000000
Transmit cancel register
TCANR
W
00000000 00000000
Transmit complete
register
TCR
R/W
00000000 00000000
Receive complete
register
RCR
R/W
00000000 00000000
Remote request
receiving register
RRTRR
R/W
00000000 00000000
Receive overrun
register
ROVRR
R/W
00000000 00000000
Receive interrupt enable
register
RIER
R/W
00000000 00000000
CAN Control status
register
CSR
R/W, R
00---000 0----001
Last event indicator
register
LEIR
R/W
-------- 000-0000
Receive/transmit error
counter
RTEC
R
00000000 00000000
BTR
R/W
-1111111 11111111
Bit timing register
CHAPTER 19 CAN CONTROLLER
Table 19.3-1 List of Overall Control Registers (2/2)
Address
Register
CAN0
CAN1
001C08H
001D08H
001C09H
001D09H
001C0AH
001D0AH
001C0BH
001D0BH
001C0CH
001D0CH
001C0DH
001D0DH
001C0EH
001D0EH
001C0FH
001D0FH
001C10H
001D10H
001C11H
001D11H
001C12H
001D12H
001C13H
001D13H
001C14H
001D14H
001C15H
001D15H
001C16H
001D16H
001C17H
001D17H
001C18H
001D18H
001C19H
001D19H
001C1AH
001D1AH
001C1BH
001D1BH
Abbreviation
Access
Initial Value
IDER
R/W
XXXXXXXX XXXXXXXX
Transmit RTR register
TRTRR
R/W
00000000 00000000
Remote frame receive
waiting register
RFWTR
R/W
XXXXXXXX XXXXXXXX
TIER
R/W
00000000 00000000
IDE register
Transmit interrupt
enable register
XXXXXXXX XXXXXXXX
Acceptance mask select
register
AMSR
R/W
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
Acceptance mask
register 0
AMR0
R/W
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
Acceptance mask
register 1
AMR1
R/W
XXXXX--- XXXXXXXX
275
CHAPTER 19 CAN CONTROLLER
19.4 List of Message Buffers (ID Registers)
Table 19.4-1 lists message buffers (ID registers).
■ List of Message Buffers (ID Registers)
Table 19.4-1 List of Message Buffers (ID Registers) (1/3)
Address
Register
276
CAN0
CAN1
001A00H
to
001A1FH
001B00H
to
001B1FH
001A20H
001B20H
001A21H
001B21H
001A22H
001B22H
001A23H
001B23H
001A24H
001B24H
001A25H
001B25H
001A26H
001B26H
001A27H
001B27H
001A28H
001B28H
001A29H
001B29H
001A2AH
001B2AH
001A2BH
001B2BH
001A2CH
001B2CH
001A2DH
001B2DH
001A2EH
001B2EH
001A2FH
001B2FH
001A30H
001B30H
001A31H
001B31H
001A32H
001B32H
001A33H
001B33H
Generalpurpose
RAM
Abbreviation
Access
Initial Value
--
R/W
XXXXXXXX
to
XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 0
IDR0
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 1
IDR1
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 2
IDR2
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 3
IDR3
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 4
IDR4
R/W
XXXXX--XXXXXXXX
CHAPTER 19 CAN CONTROLLER
Table 19.4-1 List of Message Buffers (ID Registers) (2/3)
Address
Register
CAN0
CAN1
001A34H
001B34H
001A35H
001B35H
001A36H
001B36H
001A37H
001B37H
001A38H
001B38H
001A39H
001B39H
001A3AH
001B3AH
001A3BH
001B3BH
001A3CH
001B3CH
001A3DH
001B3DH
001A3EH
001B3EH
001A3FH
001B3FH
001A40H
001B40H
001A41H
001B41H
001A42H
001B42H
001A43H
001B43H
001A44H
001B44H
001A45H
001B45H
001A46H
001B46H
001A47H
001B47H
001A48H
001B48H
001A49H
001B49H
001A4AH
001B4AH
001A4BH
001B4BH
001A4CH
001B4CH
001A4DH
001B4DH
001A4EH
001B4EH
001A4FH
001B4FH
Abbreviation
Access
Initial Value
XXXXXXXX
XXXXXXXX
ID register 5
IDR5
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 6
IDR6
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 7
IDR7
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 8
IDR8
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 9
IDR9
R/W
XXXXX--XXXXXXXX
ID register
10
ID register
11
XXXXXXXX
XXXXXXXX
IDR10
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
IDR11
R/W
XXXXX--XXXXXXXX
277
CHAPTER 19 CAN CONTROLLER
Table 19.4-1 List of Message Buffers (ID Registers) (3/3)
Address
Register
278
CAN0
CAN1
001A50H
001B50H
001A51H
001B51H
001A52H
001B52H
001A53H
001B53H
001A54H
001B54H
001A55H
001B55H
001A56H
001B56H
001A57H
001B57H
001A58H
001B58H
001A59H
001B59H
001A5AH
001B5AH
001A5BH
001B5BH
001A5CH
001B5CH
001A5DH
001B5DH
001A5EH
001B5EH
001A5FH
001B5FH
ID register
12
ID register
13
ID register
14
ID register
15
Abbreviation
Access
Initial Value
XXXXXXXX
XXXXXXXX
IDR12
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
IDR13
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
IDR14
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
IDR15
R/W
XXXXX--XXXXXXXX
CHAPTER 19 CAN CONTROLLER
19.5 List of Message Buffers (DLC Registers and Data Registers)
Table 19.5-1 lists message buffers (DLC registers), and Table 19.5-2 lists message
buffers (data registers).
■ List of Message Buffers (DLC Registers and Data Registers)
Table 19.5-1 List of Message Buffers (DLC Registers) (1/2)
Address
Register
CAN0
CAN1
001A60H
001B60H
001A61H
001B61H
001A62H
001B62H
001A63H
001B63H
001A64H
001B64H
001A65H
001B65H
001A66H
001B66H
001A67H
001B67H
001A68H
001B68H
001A69H
001B69H
001A6AH
001B6AH
001A6BH
001B6BH
001A6CH
001B6CH
001A6DH
001B6DH
001A6EH
001B6EH
001A6FH
001B6FH
001A70H
001B70H
001A71H
001B71H
001A72H
001B72H
001A73H
001B73H
001A74H
001B74H
001A75H
001B75H
Abbreviation
Access
Initial Value
DLC register 0
DLCR0
R/W
----XXXX
DLC register 1
DLCR1
R/W
----XXXX
DLC register 2
DLCR2
R/W
----XXXX
DLC register 3
DLCR3
R/W
----XXXX
DLC register 4
DLCR4
R/W
----XXXX
DLC register 5
DLCR5
R/W
----XXXX
DLC register 6
DLCR6
R/W
----XXXX
DLC register 7
DLCR7
R/W
----XXXX
DLC register 8
DLCR8
R/W
----XXXX
DLC register 9
DLCR9
R/W
----XXXX
DLC register 10
DLCR10
R/W
----XXXX
279
CHAPTER 19 CAN CONTROLLER
Table 19.5-1 List of Message Buffers (DLC Registers) (2/2)
Address
Register
CAN0
CAN1
001A76H
001B76H
001A77H
001B77H
001A78H
001B78H
001A79H
001B79H
001A7AH
001B7AH
001A7BH
001B7BH
001A7CH
001B7CH
001A7DH
001B7DH
001A7EH
001B7EH
001A7FH
001B7FH
280
Abbreviation
Access
Initial Value
DLC register 11
DLCR11
R/W
----XXXX
DLC register 12
DLCR12
R/W
----XXXX
DLC register 13
DLCR13
R/W
----XXXX
DLC register 14
DLCR14
R/W
----XXXX
DLC register 15
DLCR15
R/W
----XXXX
CHAPTER 19 CAN CONTROLLER
■ List of Message Buffers (Data Registers)
Table 19.5-2 List of Message Buffers (Data Registers) (1/2)
Address
Register
Abbreviation
Access
Initial Value
001B80H
to
001B87H
Data register 0 (8 bytes)
DTR0
R/W
XXXXXXXX
to
XXXXXXXX
001A88H
to
001A8FH
001B88H
to
001B8FH
Data register 1 (8 bytes)
DTR1
R/W
XXXXXXXX
to
XXXXXXXX
001A90H
to
001A97H
001B90H
to
001B97H
Data register 2 (8 bytes)
DTR2
R/W
XXXXXXXX
to
XXXXXXXX
001A98H
to
001A9FH
001B98H
to
001B9FH
Data register 3 (8 bytes)
DTR3
R/W
XXXXXXXX
to
XXXXXXXX
001AA0H
to
001AA7H
001BA0H
to
001BA7H
Data register 4 (8 bytes)
DTR4
R/W
XXXXXXXX
to
XXXXXXXX
001AA8H
to
001AAFH
001BA8H
to
001BAFH
Data register 5 (8 bytes)
DTR5
R/W
XXXXXXXX
to
XXXXXXXX
001AB0H
to
001AB7H
001BB0H
to
001BB7H
Data register 6 (8 bytes)
DTR6
R/W
XXXXXXXX
to
XXXXXXXX
001AB8H
to
001ABFH
001BB8H
to
001BBFH
Data register 7 (8 bytes)
DTR7
R/W
XXXXXXXX
to
XXXXXXXX
001AC0H
to
001AC7H
001BC0H
to
001BC7H
Data register 8 (8 bytes)
DTR8
R/W
XXXXXXXX
to
XXXXXXXX
001AC8H
to
001ACFH
001BC8H
to
001BCFH
Data register 9 (8 bytes)
DTR9
R/W
XXXXXXXX
to
XXXXXXXX
001AD0H
to
001AD7H
001BD0H
to
001BD7H
Data register 10
(8 bytes)
DTR10
R/W
XXXXXXXX
to
XXXXXXXX
001AD8H
to
001ADFH
001BD8H
to
001BDFH
Data register 11
(8 bytes)
DTR11
R/W
XXXXXXXX
to
XXXXXXXX
001AE0H
to
001AE7H
001BE0H
to
001BE7H
Data register 12
(8 bytes)
DTR12
R/W
XXXXXXXX
to
XXXXXXXX
CAN0
CAN1
001A80H
to
001A87H
281
CHAPTER 19 CAN CONTROLLER
Table 19.5-2 List of Message Buffers (Data Registers) (2/2)
Address
Register
Abbreviation
Access
Initial Value
Data register 13
(8 bytes)
DTR13
R/W
XXXXXXXX
to
XXXXXXXX
001BF0H
to
001BF7H
Data register 14
(8 bytes)
DTR14
R/W
XXXXXXXX
to
XXXXXXXX
001BF8H
to
001BFFH
Data register 15
(8 bytes)
DTR15
R/W
XXXXXXXX
to
XXXXXXXX
CAN0
CAN1
001AE8H
to
001AEFH
001BE8H
to
001BEFH
001AF0H
to
001AF7H
001AF8H
to
001AFFH
282
CHAPTER 19 CAN CONTROLLER
19.6 Classifying the CAN Controller Registers
There are three types of CAN controller registers:
• Overall control registers
• Message buffer control registers
• Message buffers
■ Overall Control Registers
The overall control registers are the following four registers:
•
CAN control status register (CSR)
•
Last event indicator register (LEIR)
•
Receive and transmit error counter (RTEC)
•
Bit timing register (BTR)
■ Message Buffer Control Registers
The message buffer control registers are the following 14 registers:
•
Message buffer valid register (BVALR)
•
IDE register (IDER)
•
Transmission request register (TREQR)
•
Transmission RTR register (TRTRR)
•
Remote frame receiving wait register (RFWTR)
•
Transmission cancel register (TCANR)
•
Transmission complete register (TCR)
•
Transmission interrupt enable register (TIER)
•
Reception complete register (RCR)
•
Remote request receiving register (RRTRR)
•
Receive overrun register (ROVRR)
•
Reception interrupt enable register (RIER)
•
Acceptance mask select register (AMSR)
•
Acceptance mask registers 0 and 1 (AMR0 and AMR1)
■ Message Buffers
The message buffers are the following three registers:
•
ID register x (x = 0 to 15) (IDRx)
•
DLC register x (x = 0 to 15) (DLCRx)
•
Data register x (x = 0 to 15) (DTRx)
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CHAPTER 19 CAN CONTROLLER
19.6.1 CAN Control Status Register (CSR)
The lower 8bits with the CAN control status register (CSR) is prohibited from
executing any bit manipulation instructions (Read-modify-write instructions).
Only in the case of HALT bits unchanged, use any bit manipulation instructions
without problems (initialization of the macro instructions, etc.).
■ CAN Control Status Register (CSR)
Figure 19.6-1 CAN Control Status Register (CSR)
bit
Address: 001C01H (CAN0)
001D01H (CAN1)
Read/write→
Initial value→
15
14
13
12
11
10
9
8
TS
RS
-
-
-
NT
NS1
NS0
(R)
(0)
(R)
(0)
(-)
(-)
(-)
(-)
(-)
(-)
(R/W)
(0)
(R)
(0)
(R)
(0)
6
5
4
3
2
1
0
-
-
-
-
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
bit
7
Address: 001C00H (CAN0)
TOE
001D00H (CAN1)
Read/write→ (R/W)
Initial value→
(0)
ReHALT
served
(R/W)
(W)
(R/W)
(0)
(0)
(1)
NIE
[bit 15] TS: Transmit status bit
This bit indicates whether a message is being transmitted.
0: Message not being transmitted
1: Message being transmitted
This bit is "0" even while error and overload frames are transmitted.
[bit 14] RS: Receive status bit
This bit indicates whether a message is being received.
0: Message not being received
1: Message being received
While a message is on the bus, this bit becomes "1". Therefore, this bit is also "1" while a
message is being transmitted. This bit does not necessarily indicates whether a receiving
message passes through the acceptance filter.
As a result, when this bit is "0", it implies that the bus operation is stopped (HALT = 0); the
bus is in the intermission/bus idle or an error/overload frame is on the bus.
[bit 10] NT: Node status transition flag
If the node status is changed to increment, or from Bus Off to Error Active, this bit is set to
"1".
In other words, the NT bit is set to "1" if the node status is changed from Error Active (00) to
Warning (01), from Warning (01) to Error Passive (10), from Error Passive (10) to Bus Off
(11), and from Bus Off (11) to Error Active (00). Numbers in parentheses indicate the values
of NS1 and NS0 bits.
284
CHAPTER 19 CAN CONTROLLER
When the node status transition interrupt enable bit (NIE) is "1", an interrupt is generated.
Writing "0" sets the NT bit to "0". Writing "1" to the NT bit is ignored. "1" is read when readmodify-write instruction is performed.
[bit 9, bit 8] NS1 and NS0: Node status bits 1 and 0
These bits indicate the current node status.
Table 19.6-1 Correspondence between NS1 and NS0 and Node Status
NS1
NS0
Node Status
0
0
Error active
0
1
Warning (error active)
1
0
Error passive
1
1
Bus off
Note:
Warning (error active) is included in the error active in CAN Specification 2.0B for the node status,
however, indicates that the transmit error counter or receive error counter has exceeded 96. The
node status change diagram is shown in Figure 19.6-2.
Figure 19.6-2 Node Status Transition Diagram
Hardware reset
REC: Receive error counter
TEC: Transmit error counter
Error active
After "0" has been written to the HALT bit
of the register (CSR), continuous 11-bit
"H" levels (recessive bits) are input 128
times to the receive input pin (RX).
REC 96
or
TEC 96
REC < 96
and
TEC < 96
REC
TEC
128
or
Warning
(Error active)
128
REC < 128
and
TEC < 128
Error
passive
Bus off
TEC
256
[bit 7] TOE: Transmit output enable bit
Writing "1" to this bit switches from a general-purpose port pin to a transmit pin of the CAN
controller.
0: General-purpose port pin
1: Transmit pin of CAN controller
285
CHAPTER 19 CAN CONTROLLER
[bit 2] NIE: Node status transition interrupt enable bit
This bit enables or disables a node status transition interrupt (when NT = 1).
0: Node status transition interrupt disabled
1: Node status transition interrupt enabled
[bit 1] Reserved
The is a reserved bit. Do not write "1" to this bit.
[bit 0] HALT: Bus operation stop bit
This bit sets or cancels bus operation stop, or displays its state.
Reading this bit
0 : Bus operation in progress
1 : Bus operation in stop state
Writing to this bit
0 : Cancels bus operation stop
1 : Sets bus operation stop
Note:
When write "0" to this bit during the node status is Bus Off, ensure that "0" is written to after
confirming HALT bit is "1".
Example program:
switch (IO_CANCT0. CSR. bit. NS)
{
case 0 : /* error active */
break;
case 1 : /*warning */
break;
case 2 : /* error passive */
break;
default : /* bus off */
for (i = 0; (i <=500) || (IO_CANCT0. CSR. bit. HALT == 0); i++);
IO_CANCT0.CSR. word = 0x0084; /* HALT = 0 */
break;
}
* : The variable "1" is used for fail-safe.
286
CHAPTER 19 CAN CONTROLLER
19.6.2 Bus Operation Stop Bit (HALT = 1)
The bus operation stop bit sets or cancels stopping of bus operation, or indicates its
status.
■ Conditions for Setting Bus Operation Stop (HALT=1)
There are three conditions for setting bus operation stop (HALT = 1):
•
After hardware reset
•
When node status changed to bus off
•
By writing "1" to HALT
Notes:
• The bus operation should be stopped by writing "1" to HALT before the F2MC-16LX is transitted
in low-power-consumption mode (stop mode, clock mode, and hardware stand-by mode).
If transmission is in progress when "1" is written to HALT, the bus operation is stopped (HALT =
1) after transmission is terminated. If reception is in progress when "1" is written to HALT, the
bus operation is stopped immediately (HALT = 1). If received messages are being stored in the
message buffer (x), stop the bus operation (HALT = 1) after storing the messages.
• To check whether the bus operation has stopped, always read the HALT bit.
■ Conditions for Canceling Bus Operation Stop (HALT = 0)
By writing "0" to HALT
Notes:
• Canceling the bus operation stop after hardware reset or by writing "1" to HALT as above
conditions is performed after "0" is written to HALT and continuous 11-bit High levels (recessive
bits) have been input to the receive input pin (RX) (HALT = 0).
• Canceling the bus operation stop when the node status is changed to bus off as above
conditions is performed after "0" is written to HALT and continuous 11-bit High levels (recessive
bits) have been input 128 times to the receive input pin (RX) (HALT = 0). Then, the values of
both transmit and receive error counters reach 0 and the node status is changed to error active.
• When write "0" to HALT during the node status is Bus Off, ensure that "1" is written to this bit
after confirming HALT is "1".
■ State during Bus Operation Stop (HALT = 1)
•
The bus does not perform any operation, such as transmission and reception.
•
The transmit output pin (TX) outputs a High level (recessive bit).
•
The values of other registers and error counters are not changed.
287
CHAPTER 19 CAN CONTROLLER
Note:
The bit timing register (BTR) should be set during bus operation stop (HALT = 1).
288
CHAPTER 19 CAN CONTROLLER
19.6.3 Last Event Indicator Register (LEIR)
This register indicates the last event.
The NTE, TCE, and RCE bits are exclusive. When the corresponding bit of the last
event is set to "1", other bits are set to 0s.
■ Last Event Indicator Register (LEIR)
Figure 19.6-3 Last Event Indicator Register (LEIR)
bit
7
Address: 001C02H (CAN0)
NTE
001D02H (CAN1)
Read/write→ (R/W)
Initial value→
(0)
6
5
4
TCE
RCE
-
(R/W)
(0)
(R/W)
(0)
(-)
(-)
3
2
1
0
MBP3 MBP2 MBP1
MBP0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
[bit 7] NTE: Node status transition event bit
• When this bit is "1", node status transition is the last event.
• This bit is set to "1" at the same time the NT bit of the control status register (CSR) is set.
• This bit is also set to "1" irrespective of the setting of the node status transition interrupt
enable bit (NIE) of CSR.
• Writing "0" to this bit sets the NTE bit to "0". Writing "1" to this bit is ignored.
• "1" is read when read-modify-write instruction is executed.
[bit 6] TCE: Transmit completion event bit
When this bit is "1", it indicates that transmit completion is the last event.
This bit is set to "1" at the same time as any one of the bits of the transmit completion
register (TCR). This bit is also set to "1", irrespective of the settings of the bits of the transmit
interrupt enable register (TIER).
Writing "0" sets this bit to "0". Writing "1" to this bit is ignored.
"1" is read when read-modify-write instruction is read.
When this bit is set to "1", the MBP3 to MBP0 bits are used to indicate the message buffer
number completing the transmit operation.
[bit 5] RCE: Receive completion event bit
When this bit is "1", it indicates that receive completion is the last event.
This bit is set to "1" at the same time as any one of the bits of the receive complete register
(RCR). This bit is also set to "1" irrespective of the settings of the bits of the receive interrupt
enable register (RIER).
Writing "0" sets this bit to "0". Writing "1" to this bit is ignored.
"1 is read when read-modify-write instruction is read.
When this bit is set to "1", the MBP3 to MBP0 bits are used to indicate the message buffer
number completing the receive operation.
289
CHAPTER 19 CAN CONTROLLER
[bit 3 to bit 0] MBP3 to MBP0: Message buffer pointer bits
When the TCE or RCE bit is set to "1", these bits indicate the corresponding numbers of the
message buffers (0 to 15). If the NTE bit is set to "1", these bits have no meaning.
Writing "0" sets these bits to 0s. Writing "1" to these bits is ignored.
1s are read when read-modify-write instruction is read.
If LEIR is accessed within an CAN interrupt handler, the event causing the interrupt is not
neccessarily the same as indicated by LEIR. In the time from interrupt request to the LEIR
access by the interrupt handler there may occur other CAN events.
290
CHAPTER 19 CAN CONTROLLER
19.6.4 Receive and Transmit Error Counters (RTEC)
The receive and transmit error counters indicate the counts for transmission errors
and reception errors defined in the CAN specifications. These registers can only be
read.
■ Receive and Transmit Error Counters (RTEC)
Figure 19.6-4 Receive and Transmit Error Counters (RTEC)
bit
15
Address: 001C05H (CAN0)
TEC7
001D05H (CAN1)
Read/write→ (R)
Initial value→
(0)
bit
7
Address: 001C04H (CAN0)
REC7
001D04H (CAN1)
Read/write→ (R)
Initial value→
(0)
14
13
12
11
10
9
8
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
6
5
4
3
2
1
0
REC6
REC5
REC4
REC3
REC2
REC1
REC0
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
[bit 15 to bit 8] TEC7 to TEC0: Transmit error counter
These are transmit error counters.
TEC7 to TEC0 values indicate 0 to 7 when the counter value is more than 256, and the
subsequent increment is not counted for counter value. In this case, Bus Off is indicated for
the node status (NS1 and NS0 of control status register CSR = 11).
[bit 7 to bit 0] REC7 to REC0: Receive error counter
These are receive error counters.
REC7 to REC0 values indicate 0 to 7 when the counter value is more than 256, and the
subsequent increment is not counted for counter value. In this case, Error Passive is
indicated for the node status (NS1 and NS0 of control status register CSR = 10).
291
CHAPTER 19 CAN CONTROLLER
19.6.5 Bit Timing Register (BTR)
Bit timing register (BTR) stores the prescaler and bit timing setting.
■ Bit Timing Register (BTR)
Figure 19.6-5 Bit Timing Register (BTR)
bit
Address: 001C07H (CAN0)
001D07H (CAN1)
Read/write→
Initial value→
15
14
13
12
11
10
9
8
-
TS2.2
TS2.1
TS2.0
TS1.3
TS1.2
TS1.1
TS1.0
(-)
(-)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
6
5
4
3
2
1
0
RSJ0
PSC5
PSC4
PSC3
PSC2
PSC1
PSC0
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
bit
7
Address: 001C06H (CAN0)
RSJ1
001D06H (CAN1)
Read/write→ (R/W)
Initial value→
(1)
Note:
This register should be set during bus operation stop (HALT = 1).
[bit 14 to bit 12] TS2.2 to TS2.0: Time segment 2 setting bit 2 to bit 0
These bits define the number of the time quanta (TQ’s) for the time segment 2 (TSEG2) by
dividing [(TS2.2 to TS2.0) +1]. The time segment 2 is equal to the phase buffer segment 2
(PHASE_SEG2) in the CAN specification.
[bit 11 to bit 8] TS1.3 to TS1.0: Time segment 1 setting bit 3 to bit 0
These bits define the number of the time quanta (TQ’s) for the time segment 1 (TSEG1) by
dividing [(TS1.3 to TS1.0) +1]. The time segment 1 is equal to the propagation segment
(PROP_SEG) + phase buffer segment 1 (PHASE_SEG1) in the CAN specification.
[bit 7, bit 6] RSJ1 and RSJ0: Resynchronization jump width setting bit 1 and bit 0
These bits define the number of the time quanta (TQ’s) for the resynchronization jump width
by dividing [(RSJ1, RSJ0) +1].
292
CHAPTER 19 CAN CONTROLLER
[bit 5 to bit 0] PSC5 to PSC0: Prescaler setting bit 5 to bit 0
These bits define the time quanta (TQ) of the CAN controller by dividing the frequency
[(PCS5 to PCS0) +1] for input clock.
The bit time segments defined in the CAN specification, and the CAN controller are shown in
Figure 19.6-6 and Figure 19.6-7 respectively.
Figure 19.6-6 Bit Time Segment in CAN Specification
Nominal bit time
SYNC_SEG
PROP_SEG
PHASE_SEG1 PHASE_SEG2
Sample point
Figure 19.6-7 Bit Time Segment in CAN Controller
Nominal bit time
SYNC_SEG
TSEG1
TSEG2
Sample point
The relationship between PSC = PSC5 to PSC0, TSI = TS1.3 to TS1.0, TS2 = TS2.2 to TS1.0,
and RSJ = RSJ1 and RSJ0 when the input clock (CLK), time quanta (TQ), bit time (BT),
synchronous segment (SYNC_SEG), time segment 1 and 2 (TSEG1 and TSEG2), and
resynchronization jump width [(RSJ1 and RSJ0) +1] frequency division is shown below.
TQ
BT
= (PSC + 1) x CLK
= SYNC_SEG + TSEG1 + TSEG2
= (1 + (TS1 + 1) + (TS2 +1)) x TQ
= (3 + TS1 +TS2) x TQ
RSJW = (RSJ + 1) x TQ
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CHAPTER 19 CAN CONTROLLER
For correct operation, the following conditions should be met.
Device with "G" suffix:
For 1
PSC
TSEG1
TSEG1
TSEG2
TSEG2
For PSC = 0:
TSEG1
TSEG2
TSEG2
63:
2TQ
RSJW
2TQ
RSJW
5TQ
2TQ
RSJW
Device without "G" suffix:
For 1
PSC
63:
TSEG1
RSJW
TSEG2
RSJW + 2TQ
For PSC = 0:
TSEG1
5TQ
TSEG2
RSJW + 2TQ
In order to meet the bit timing requirements defined in the CAN specification, additions have to
be met, e.g. the propagation delay has to be considered.
294
CHAPTER 19 CAN CONTROLLER
19.6.6 Message Buffer Valid Register (BVALR)
Message buffer valid register (BVALR) stores the validity of the message buffers or
displays their state.
■ Message Buffer Valid Register (BVALR)
Figure 19.6-8 Message Buffer Valid Register (BVALR)
bit
15
14
13
12
11
10
9
8
Address: 000071H (CAN0)
BVAL15 BVAL14 BVAL13 BVAL12 BVAL11 BVAL10 BVAL9 BVAL8
000081H (CAN1)
Read/write→ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value→
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
bit
7
Address: 000070H (CAN0) BVAL
7
000080H (CAN1)
Read/write→ (R/W)
Initial value→
(0)
6
5
4
3
2
1
0
BVAL
6
(R/W)
(0)
BVAL
5
(R/W)
(0)
BVAL
4
(R/W)
(0)
BVAL
3
(R/W)
(0)
BVAL
2
(R/W)
(0)
BVAL
1
(R/W)
(0)
BVAL
0
(R/W)
(0)
0: Message buffer (x) invalid
1: Message buffer (x) valid
If the message buffer (x) is set to invalid, it will not transmit or receive messages.
If the buffer is set to invalid during transmission operating, it becomes invalid (BVALx = 0) after
the transmission is completed or terminated by an error.
If the buffer is set to invalid during reception operating, it immediately becomes invalid (BVALx =
0). If received messages are stored in a message buffer (x), the message buffer (x) is invalid
after storing the messages.
Notes:
• x indicates a message buffer number (x = 0 to 15).
• When invaliding a message buffer (x) by writing "0" to a bit (BVALx), execution of a bit
manipulation instruction is prohibited until the bit is set to "0".
• To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while CAN Controller is
participating in CAN communication (the read value of the CSR: HALT bit is "0" and CAN
Controller is ready to receive or transmit messages), follow the cautions in Section "19.14
Precautions when Using CAN Controller".
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CHAPTER 19 CAN CONTROLLER
19.6.7 IDE register (IDER)
This register stores the frame format used by the message buffers (x) during
transmission/reception.
■ IDE Register (IDER)
Figure 19.6-9 IDE Register (IDER)
bit
15
Address: 001C09H (CAN0)
IDE15
001D09H (CAN1)
Read/write→ (R/W)
Initial value→
(X)
bit
7
Address: 001C08H (CAN0)
IDE7
001D08H (CAN1)
Read/write→ (R/W)
Initial value→
(X)
14
13
12
11
10
9
8
IDE14
IDE13
IDE12
IDE11
IDE10
IDE9
IDE8
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
6
5
4
3
2
1
0
IDE6
IDE5
IDE4
IDE3
IDE2
IDE1
IDE0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
0: Standard frame format (ID11 bit) is used for message buffer (x)
1: Extended frame format (ID29 bit) is used for message buffer (x)
Notes:
• This register should be set when the message buffer (x) is invalid (BVALx of the message buffer
valid register (BVALR) = 0). Setting when the buffer is valid (BVALx = 1) may cause
unnecessary received messages to be stored.
• To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while CAN Controller is
participating in CAN communication (the read value of the CSR: HALT bit is 0 and CAN
Controller is ready to receive or transmit messages), follow the cautions in Section "19.14
Precautions when Using CAN Controller".
296
CHAPTER 19 CAN CONTROLLER
19.6.8 Transmission Request Register (TREQR)
Transmission request register (TREQR) stores transmission requests to the message
buffers (x) or displays their state.
■ Transmission Request Register (TREQR)
Figure 19.6-10 Transmission Request Register (TREQR)
bit
15
14
13
12
11
10
9
8
Address: 000073H (CAN0)
TREQ15 TREQ14 TREQ13 TREQ12 TREQ11 TREQ10 TREQ9 TREQ8
000083H (CAN1)
Read/write→ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value→
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
bit
7
6
5
4
3
2
1
0
Address: 000072H (CAN0)
TREQ7 TREQ6 TREQ5 TREQ4 TREQ3 TREQ2 TREQ1 TREQ0
000082H (CAN1)
Read/write→ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value→
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
When "1" is written to TREQx, transmission to the message buffer (x) starts. If RFWTx of the
remote frame receiving wait register (RFWTR)*1 is "0", transmission starts immediately.
However, if RFWTx = 1, transmission starts after waiting until a remote frame is received
(RRTRx of the remote request receiving register (RRTRR)*1 becomes "1"). Transmission
starts*2 immediately even when RFWTx = 1, if RRTRx is already "1" when "1" is written to
TREQx.
*1: For TRTRR and RFWTR, see "19.6.9 Transmission RTR Register (TRTRR)" and "19.6.10
Remote Frame Receiving Wait Register (RFWTR)".
*2: For cancellation of transmission, see "19.6.11 Transmission Cancel Register (TCANR)" and
"19.6.12 Transmission Complete Register (TCR)".
Writing "0" to TREQx is ignored.
"0" is read when read-modify-write instruction is performed.
If clearing (to 0) at completion of the transmit operation and setting by writing "1" are concurrent,
clearing is preferred.
If "1" is written to more than one bit, transmission is performed, starting with the lowernumbered message buffer (x).
TREQx is "1" while transmission is waiting, and becomes "0" when transmission is completed or
canceled.
297
CHAPTER 19 CAN CONTROLLER
19.6.9 Transmission RTR Register (TRTRR)
This register stores the RTR (Remote Transmission Request) bits for the message
buffers (x).
■ Transmission RTR Register (TRTRR)
Figure 19.6-11 Transmission RTR Register (TRTRR)
bit
15
14
13
12
11
10
9
8
Address: 001C0BH (CAN0)
TRTR15 TRTR14 TRTR13 TRTR12 TRTR11 TRTR10 TRTR9 TRTR8
001D0BH (CAN1)
Read/write→ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value→
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
bit
7
6
5
4
3
2
1
0
Address: 001C0AH (CAN0)
TRTR7 TRTR6 TRTR5 TRTR4 TRTR3 TRTR2 TRTR1 TRTR0
001D0AH (CAN1)
Read/write→ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value→
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
0: Data frame is transmitted
1: Remote frame is transmitted
298
CHAPTER 19 CAN CONTROLLER
19.6.10 Remote Frame Receiving Wait Register (RFWTR)
Remote frame receiving wait register (RFWTR) stores the conditions for starting
transmission when a request for data frame transmission is set (TREQx of the
transmission request register (TREQR) is "1" and TRTRx of the transmitting RTR
register (TRTRR) is "0").
0: Transmission starts immediately
1: Transmission starts after waiting until remote frame received (RRTRx of remote
request receiving register (RRTRR) becomes "1")
■ Remote Frame Receiving Wait Register (RFWTR)
Figure 19.6-12 Remote Frame Receiving Wait Register (RFWTR)
bit
15
14
13
12
11
10
9
8
Address: 001C0DH (CAN0)
RFWT15 RFWT14 RFWT13 RFWT12 RFWT11 RFWT10 RFWT9 RFWT8
001D0DH (CAN1)
Read/write→ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value→
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
bit
7
6
5
4
3
2
1
0
Address: 001C0CH (CAN0)
RFWT7 RFWT6 RFWT5 RFWT4 RFWT3 RFWT2 RFWT1 RFWT0
001D0CH (CAN1)
Read/write→ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value→
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Notes:
• Transmission starts immediately if RRTRx is already "1" when a request for transmission is set.
• For remote frame transmission, do not set RFWTx to "1".
299
CHAPTER 19 CAN CONTROLLER
19.6.11 Transmission Cancel Register (TCANR)
When "1" is written to TCANx, this register cancels a waiting request for transmission
to the message buffer (x).
At completion of cancellation, TREQx of the transmission request register (TREQR)
becomes "0". Writing "0" to TCANx is ignored.
This is a write-only register and its read value is always "0".
■ Transmission Cancel Register (TCANR)
Figure 19.6-13 Transmission Cancel Register (TCANR)
bit
15
14
13
12
11
10
9
8
Address: 000075H (CAN0)
TCAN15 TCAN14 TCAN13 TCAN12 TCAN11 TCAN10 TCAN9 TCAN8
000085H (CAN1)
Read/write→ (W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
Initial value→
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
bit
7
6
5
4
3
2
1
0
Address: 000074H (CAN0)
TCAN7 TCAN6 TCAN5 TCAN4 TCAN3 TCAN2 TCAN1 TCAN0
000084H (CAN1)
Read/write→ (W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
Initial value→
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
300
CHAPTER 19 CAN CONTROLLER
19.6.12 Transmission Complete Register (TCR)
At completion of transmission by the message buffer (x), the corresponding TCx
becomes "1".
If TIEx of the transmission complete interrupt enable register (TIER) is "1", an interrupt
occurs.
■ Transmission Complete Register (TCR)
Figure 19.6-14 Transmission Complete Register (TCR)
bit
15
Address: 000077H (CAN0)
TC15
000087H (CAN1)
Read/write→ (R/W)
Initial value→
(0)
bit
7
Address: 000076H (CAN0)
TC7
000086H (CAN1)
Read/write→ (R/W)
Initial value→
(0)
14
13
12
11
10
9
8
TC14
TC13
TC12
TC11
TC10
TC9
TC8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
6
5
4
3
2
1
0
TC6
TC5
TC4
TC3
TC2
TC1
TC0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
❍ Conditions for TCx = 0
•
Write "0" to TCx.
•
Write "1" to TREQx of the transmission request register (TREQR).
After the completion of transmission, write "0" to TCx is to set it to "0". Writing "1" to TCx is
ignored.
"1" is read when read-modify-write instruction is performed.
Note:
If setting to "1" by completion of the transmit operation and clearing to "0" by writing occur at the
same time, the setting to "1" is preferred.
301
CHAPTER 19 CAN CONTROLLER
19.6.13 Transmission Interrupt Enable Register (TIER)
This register enables or disables the transmission interrupt by the message buffer (x).
The transmission interrupt is generated at transmission completion (when TCx of the
transmission complete register (TCR) is "1").
■ Transmission Interrupt Enable Register (TIER)
Figure 19.6-15 Transmission Interrupt Enable Register (TIER)
bit
15
Address: 001C0FH (CAN0)
TIE15
001D0FH (CAN1)
Read/write→ (R/W)
Initial value→
(0)
bit
7
Address: 001C0EH (CAN0)
TIE7
001D0EH (CAN1)
Read/write→ (R/W)
Initial value→
(0)
14
13
12
11
10
9
8
TIE14
TIE13
TIE12
TIE11
TIE10
TIE9
TIE8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
6
5
4
3
2
1
0
TIE6
TIE5
TIE4
TIE3
TIE2
TIE1
TIE0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
0: Transmission interrupt disabled
1: Transmission interrupt enabled
302
CHAPTER 19 CAN CONTROLLER
19.6.14 Reception Complete Register (RCR)
At completion of storing received message in the message buffer (x), RCx becomes
"1".
If RIEx of the reception complete interrupt enable register (RIER) is "1", an interrupt
occurs.
■ Reception Complete Register (RCR)
Figure 19.6-16 Reception Complete Register (RCR)
bit
15
Address: 000079H (CAN0)
RC15
000089H (CAN1)
Read/write→ (R/W)
Initial value→
(0)
bit
7
Address: 000078H (CAN0)
RC7
000088H (CAN1)
Read/write→ (R/W)
Initial value→
(0)
14
13
12
11
10
9
8
RC14
RC13
RC12
RC11
RC10
RC9
RC8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
6
5
4
3
2
1
0
RC6
RC5
RC4
RC3
RC2
RC1
RC0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
❍ Conditions for RCx = 0
Write "0" to RCx.
After completion of handling received message, write "0" to RCx and set it to "0". Writing "1" to
RCx is ignored.
"1" is read when read-modify-write instruction is performed.
Note:
If setting to "1" by completion of the receive operation and clearing to "0" by writing occur at the
same time, the setting to "0" is preferred.
303
CHAPTER 19 CAN CONTROLLER
19.6.15 Remote Request Receiving Register (RRTRR)
After a remote frame is stored in the message buffer (x), RRTRx becomes "1" (at the
same time as RCx setting to "1").
■ Remote Request Receiving Register (RRTRR)
Figure 19.6-17 Remote Request Receiving Register (RRTRR)
bit
15
14
13
12
11
10
9
8
Address: 00007BH (CAN0)
RRTR15 RRTR14 RRTR13 RRTR12 RRTR11 RRTR10 RRTR9 RRTR8
00008BH (CAN1)
Read/write→ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value→
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
bit
7
6
5
4
3
2
1
0
Address: 00007AH (CAN0)
RRTR7 RRTR6 RRTR5 RRTR4 RRTR3 RRTR2 RRTR1 RRTR0
00008AH (CAN1)
Read/write→ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value→
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
❍ Conditions for RRTRx = 0
•
Write "0" to RRTRx.
•
After a received data frame is stored in the message buffer (x) (at the same time as RCx
setting to "1").
•
Transmission by the message buffer (x) is completed (TCx of the transmission complete
register (TCR) is "1").
Writing "1" to RRTRx is ignored.
"1" is read when read-modify-write instruction is performed.
Note:
If setting to "1" by completion of the receive operation and clearing to 0 by writing occur at the
same time, the setting to "1" is preferred.
304
CHAPTER 19 CAN CONTROLLER
19.6.16 Receive Overrun Register (ROVRR)
If RCx of the reception complete register (RCR) is "1" when completing storing of a
received message in the message buffer (x), ROVRx becomes "1", indicating that
reception has overrun.
■ Receive Overrun Register (ROVRR)
Figure 19.6-18 Receive Overrun Register (ROVRR)
bit
15
14
13
12
11
10
9
8
Address: 00007DH (CAN0) ROVR1 ROVR1 ROVR1 ROVR1 ROVR1 ROVR1
ROVR9 ROVR8
5
4
3
2
1
0
00008DH (CAN1)
Read/write→ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value→
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
bit
7
6
5
4
3
2
1
0
Address: 00007CH (CAN0)
ROVR7 ROVR6 ROVR5 ROVR4 ROVR3 ROVR2 ROVR1 ROVR0
00008CH (CAN1)
Read/write→ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value→
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Writing "0" to ROVRx results in ROVRx = 0. Writing "1" to ROVRx is ignored. After checking that
reception has overrun, write "0" to ROVRx is to set it to "0".
"1" is read when read-modify-write instruction is performed.
Note:
If setting to "1" by completion of the receive operation and clearing to "0" by writing occur at the
same time, the setting to "1" is preferred.
305
CHAPTER 19 CAN CONTROLLER
19.6.17 Reception Interrupt Enable Register (RIER)
Reception interrupt enable register (RIER) enables or disables the reception interrupt
by the message buffer (x).
The reception interrupt is generated at reception completion (when RCx of the
reception completion register (RCR) is "1").
■ Reception Interrupt Enable Register (RIER)
Figure 19.6-19 Reception Interrupt Enable Register (RIER)
bit
15
14
13
12
11
10
Address: 00007FH (CAN0)
RIE15 RIE14 RIE13 RIE12 RIE11 RIE10
00008FH (CAN1)
Read/write→ (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value→
(0)
(0)
(0)
(0)
(0)
(0)
bit
7
Address: 00007EH (CAN0)
RIE7
00008EH (CAN1)
Read/write→ (R/W)
Initial value→
(0)
0: Reception interrupt disabled
1: Reception interrupt enabled
306
9
8
RIE9
RIE8
(R/W)
(0)
(R/W)
(0)
6
5
4
3
2
1
0
RIE6
RIE5
RIE4
RIE3
RIE2
RIE1
RIE0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
CHAPTER 19 CAN CONTROLLER
19.6.18 Acceptance Mask Select Register (AMSR)
This register selects masks (acceptance mask) for comparison between the received
message ID’s and the message buffer ID’s.
■ Acceptance Mask Select Register (AMSR)
Figure 19.6-20 Acceptance Mask Select Register (AMSR)
BYTE0
bit
7
Address: 001C10H (CAN0) AMS
001D10H (CAN1) 3.1
Read/write→ (R/W)
Initial value→
(X)
BYTE1
bit
15
Address: 001C11H (CAN0) AMS
001D11H (CAN1) 7.1
Read/write→ (R/W)
Initial value→
(X)
BYTE2
bit
7
Address: 001C12H (CAN0) AMS
001D12H (CAN1) 11.1
Read/write→ (R/W)
Initial value→
(X)
BYTE3
bit
15
Address: 001C13H (CAN0) AMS
001D13H (CAN1) 15.1
Read/write→ (R/W)
Initial value→
(X)
6
5
4
3
2
1
0
AMS
3.0
(R/W)
(X)
AMS
2.1
(R/W)
(X)
AMS
2.0
(R/W)
(X)
AMS
1.1
(R/W)
(X)
AMS
1.0
(R/W)
(X)
AMS
0.1
(R/W)
(X)
AMS
0.0
(R/W)
(X)
14
13
12
11
10
9
8
AMS
7.0
(R/W)
(X)
AMS
6.1
(R/W)
(X)
AMS
6.0
(R/W)
(X)
AMS
5.1
(R/W)
(X)
AMS
5.0
(R/W)
(X)
AMS
4.1
(R/W)
(X)
AMS
4.0
(R/W)
(X)
6
5
4
3
2
1
0
AMS
11.0
(R/W)
(X)
AMS
10.1
(R/W)
(X)
AMS
10.0
(R/W)
(X)
AMS
9.1
(R/W)
(X)
AMS
9.0
(R/W)
(X)
AMS
8.1
(R/W)
(X)
AMS
8.0
(R/W)
(X)
14
13
12
11
10
9
8
AMS
15.0
(R/W)
(X)
AMS
14.1
(R/W)
(X)
AMS
14.0
(R/W)
(X)
AMS
13.1
(R/W)
(X)
AMS
13.0
(R/W)
(X)
AMS
12.1
(R/W)
(X)
AMS
12.0
(R/W)
(X)
307
CHAPTER 19 CAN CONTROLLER
Table 19.6-2 Selection of Acceptance Mask
AMSx.1
AMSx.0
Acceptance Mask
0
0
Full-bit comparison
0
1
Full-bit mask
1
0
Acceptance mask register 0 (AMR0)
1
1
Acceptance mask register 1 (AMR1)
Notes:
• AMSx.1 and AMSx.0 should be set when the message buffer (x) is invalid (BVALx of the
message buffer valid register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may
cause unnecessary received messages to be stored
• To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while CAN Controller is
participating in CAN communication (the read value of the CSR: HALT bit is "0" and CAN
Controller is ready to receive or transmit messages), follow the cautions in Section "19.14
Precautions when Using CAN Controller".
308
CHAPTER 19 CAN CONTROLLER
19.6.19 Acceptance Mask Registers 0/1 (AMR0/AMR1)
There are two acceptance mask registers, AMR0 and AMR1, both of which are
available either in the standard frame format or extended frame format.
AM28 to AM18 (11 bits) are used for acceptance masks in the standard frame format
and AM28 to AM0 (29 bits) are used for acceptance masks in the extended format.
■ Acceptance Mask Registers 0/1 (AMR0/AMR1)
Figure 19.6-21 Acceptance Mask Registers 0/1 (AMR0/AMR1)
AMR0 BYTE0
bit
7
Address: 001C14H (CAN0)
AM28
001D14H (CAN1)
Read/write→ (R/W)
Initial value→
(X)
AMR0 BYTE1
bit
15
Address: 001C15H (CAN0)
AM20
001D15H (CAN1)
Read/write→ (R/W)
Initial value→
(X)
AMR0 BYTE2
bit
7
Address: 001C16H (CAN0)
AM12
001D16H (CAN1)
Read/write→ (R/W)
Initial value→
(X)
AMR0 BYTE3
bit
15
Address: 001C17H (CAN0)
AM4
001D17H (CAN1)
Read/write→ (R/W)
Initial value→
(X)
6
5
4
3
2
1
0
AM27
AM26
AM25
AM24
AM23
AM22
AM21
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
14
13
12
11
10
9
8
AM19
AM18
AM17
AM16
AM15
AM14
AM13
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
6
5
4
3
2
1
0
AM11
AM10
AM9
AM8
AM7
AM6
AM5
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
14
13
12
11
10
9
8
AM3
AM2
AM1
AM0
-
-
-
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(-)
(-)
(-)
(-)
(-)
(-)
309
CHAPTER 19 CAN CONTROLLER
Figure 19.6-21 Acceptance Mask Registers 0/1 (AMR0/AMR1) (continued)
AMR1 BYTE0
bit
7
Address: 001C18H (CAN0)
AM28
001D18H (CAN1)
Read/write→ (R/W)
Initial value→
(X)
AMR1 BYTE1
bit
15
Address: 001C19H (CAN0)
AM20
001D19H (CAN1)
Read/write→ (R/W)
Initial value→
(X)
AMR1 BYTE2
bit
7
Address: 001C1AH (CAN0)
AM12
001D1AH (CAN1)
Read/write→ (R/W)
Initial value→
(X)
AMR1 BYTE3
bit
15
Address: 001C1BH (CAN0)
AM5
001D1BH (CAN1)
Read/write→ (R/W)
Initial value→
(X)
6
5
4
3
2
1
0
AM27
AM26
AM25
AM24
AM23
AM22
AM21
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
14
13
12
11
10
9
8
AM19
AM18
AM17
AM16
AM15
AM14
AM13
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
6
5
4
3
2
1
0
AM11
AM10
AM9
AM8
AM7
AM6
AM5
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
14
13
12
11
10
9
8
AM4
AM3
AM2
AM0
-
-
-
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(-)
(-)
(-)
(-)
(-)
(-)
❍ 0: Compare
Compare the bit of the acceptance code (ID register IDRx for comparing with the received
message ID) corresponding to this bit with the bit of the received message ID. If there is no
match, no message is received.
❍ 1: Mask
Mask the bit of the acceptance code ID register (IDRx) corresponding to this bit. No comparison
is made with the bit of the received message ID.
Notes:
• AMR0 and AMR1 should be set when all the message buffers (x) selecting AMR0 and AMR1
are invalid (BVALx of the message buffer valid register (BVALR) is "0"). Setting when the buffers
are valid (BVALx = 1) may cause unnecessary received messages to be stored.
• To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while CAN Controller is
participating in CAN communication (the read value of the CSR: HALT bit is 0 and CAN
Controller is ready to receive or transmit messages), follow the cautions in Section "19.14
Precautions when Using CAN Controller".
310
CHAPTER 19 CAN CONTROLLER
19.6.20 Message Buffers
There are 16 message buffers. Message buffer x (x = 0 to 15) consists of an ID register
(IDRx), DLC register (DLCRx), and data register (DTRx).
■ Message Buffers
❍ The message buffer (x) is used both for transmission and reception.
❍ The lower-numbered message buffers are assigned higher priority.
•
At transmission, when a request for transmission is made to more than one message buffer,
transmission is performed, starting with the lowest-numbered message buffer (See "19.7
Transmission of CAN Controller").
•
At reception, when the received message ID passes through the acceptance filter
(mechanism for comparing the acceptance-masked ID of received message and message
buffer) of more than one message buffer, the received message is stored in the lowestnumbered message buffer (See "19.8 Reception of CAN Controller").
❍ When the same acceptance filter is set in more than one message buffer, the message buffers
can be used as a multi-level message buffer. This provides allowance for receiving time.
(See "19.12 Procedure for Reception by Message Buffer (x)").
Notes:
• A write operation to message buffers and general-purpose RAM areas should be performed in
words to even addresses only. A write operation in bytes causes undefined data to be written to
the upper byte at writing to the lower byte.
• When the BVALx bit of the message buffer valid register (BVALR) is "0" (Invalid), the message
buffers x (IDRx, DLCRx, and DTRx) can be used as general-purpose RAM.
During the receive/transmit operation of the CAN controller, the CAN Controller write/read to/
from the message buffers. If the CPU tries to write/read to/from the message buffers in this
period, the CPU has to wait a maximum time of 64 machine cycles.
This is also true for the general-purpose RAM area (address 001A00H to 001A1FH and address
001B00H to 001B1FH).
311
CHAPTER 19 CAN CONTROLLER
19.6.21 ID Register x (x = 0 to 15) (IDRx)
ID Register x (x = 0 to 15) (IDRx) is the ID register for message buffer (x).
■ ID Register x (x = 0 to 15) (IDRx)
Figure 19.6-22 ID Register x (x = 0 to 15) (IDRx)
BYTE0
bit
7
Address: 001A20H+4x (CAN0)
ID28
001B20H+4x (CAN1)
Read/write→ (R/W)
Initial value→
(X)
BYTE1
bit
15
Address: 001A21H+4x (CAN0)
ID20
001B21H+4x (CAN1)
Read/write→ (R/W)
Initial value→
(X)
BYTE2
bit
7
Address: 001A22H+4x (CAN0)
ID12
001B22H+4x (CAN1)
Read/write→ (R/W)
Initial value→
(X)
BYTE3
bit
15
Address: 001A23H+4x (CAN0)
ID4
001B23H+4x (CAN1)
Read/write→ (R/W)
Initial value→
(X)
6
5
4
3
2
1
0
ID27
ID26
ID25
ID24
ID23
ID22
ID21
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
14
13
12
11
10
9
8
ID19
ID18
ID17
ID16
ID15
ID14
ID13
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
6
5
4
3
2
1
0
ID11
ID10
ID9
ID8
ID7
ID6
ID5
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
14
13
12
11
10
9
8
ID3
ID2
ID1
ID0
-
-
-
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(-)
(-)
(-)
(-)
(-)
(-)
When using the message buffer (x) in the standard frame format (IDEx of the IDE register
(IDER) = 0), use 11 bits of ID28 to ID18. When using the buffer in the extended frame format
(IDEx = 1), use 29 bits of ID28 to ID0.
ID28 to ID0 have the following functions:
•
Set acceptance code (ID for comparing with the received message ID).
•
Set transmitted message ID.
Note:
In the standard frame format, setting "1"s to all bits of ID28 to ID22 is prohibited.
•
312
Store the received message ID.
CHAPTER 19 CAN CONTROLLER
Note:
All received message ID bits are stored (even if bits are masked). In the standard frame format,
ID17 to ID0 stores the undefined value, part of the last received messages.
Notes:
• A write operation to this register should be performed in words. A write operation in bytes
causes undefined data to be written to the upper byte at writing to the lower byte. Writing to the
upper byte is ignored.
• This register should be set when the message buffer (x) is invalid (BVALx of the message buffer
valid register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause
unnecessary received messages to be stored.
• To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while CAN Controller is
participating in CAN communication (the read value of the CSR: HALT bit is 0 and CAN
Controller is ready to receive or transmit messages), follow the cautions in Section "19.14
Precautions when Using CAN Controller".
313
CHAPTER 19 CAN CONTROLLER
19.6.22 DLC Register x (x = 0 to 15) (DLCRx)
DLC Register x (x = 0 to 15) (DLCRx) is the DLC register for message buffer x.
■ DLC Register x (x = 0 to 15) (DLCRx)
Figure 19.6-23 DLC Register x (x = 0 to 15) (DLCRx)
bit
Address: 001A60H+2x (CAN0)
001B60H+2x (CAN1)
Read/write→
Initial value→
7
6
5
4
3
2
1
0
-
-
-
-
DLC3
DLC2
DLC1
DLC0
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
❍ Transmission
•
Set the data length (byte count) of a transmitted message when a data frame is transmitted
(TRTRx of the transmitting RTR register (TRTRR) is "0").
•
Set the data length (byte count) of a requested message when a remote frame is transmitted
(TRTRx = 1).
Note:
Setting other than 0000 to 1000 (0 to 8 bytes) is prohibited.
❍ Reception
•
Store the data length (byte count) of a received message when a data frame is received
(RRTRx of the remote frame request receiving register (RRTRR) is "0").
•
Store the data length (byte count) of a requested message when a remote frame is received
(RRTRx = 1).
Note:
A write operation to this register should be performed in words. A write operation in bytes causes
undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte
is ignored.
314
CHAPTER 19 CAN CONTROLLER
19.6.23 Data Register x (x = 0 to 15) (DTRx)
Data register x (x = 0 to 15) (DTRx) is the data register for message buffer (x).
This register is used only in transmitting and receiving a data frame but not in
transmitting and receiving a remote frame.
■ Data Register x (x = 0 to 15) (DTRx)
Figure 19.6-24 Data Register x (x = 0 to 15) (DTRx)
BYTE0
bit
7
Address: 001A80H+8x (CAN0)
D7
001B80H+8x (CAN1)
Read/write→ (R/W)
Initial value→
(X)
BYTE1
bit
15
Address: 001A81H+8x (CAN0)
D7
001B81H+8x (CAN1)
Read/write→ (R/W)
Initial value→
(X)
BYTE2
bit
7
Address: 001A82H+8x (CAN0)
D7
001B82H+8x (CAN1)
Read/write→ (R/W)
Initial value→
(X)
BYTE3
bit
15
Address: 001A83H+8x (CAN0)
D7
001B83H+8x (CAN1)
Read/write→ (R/W)
Initial value→
(X)
6
5
4
3
2
1
0
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
14
13
12
11
10
9
8
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
6
5
4
3
2
1
0
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
14
13
12
11
10
9
8
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
315
CHAPTER 19 CAN CONTROLLER
Figure 19.6-24 Data Register x (x = 0 to 15) (DTRx) (continued)
BYTE4
bit
7
Address: 001A84H+8x (CAN0)
D7
001B84H+8x (CAN1)
Read/write→ (R/W)
Initial value→
(X)
BYTE5
bit
15
Address: 001A85H+8x (CAN0)
D7
001B85H+8x (CAN1)
Read/write→ (R/W)
Initial value→
(X)
BYTE6
bit
7
Address: 001A86H+8x (CAN0)
D7
001B86H+8x (CAN1)
Read/write→ (R/W)
Initial value→
(X)
BYTE7
bit
15
Address: 001A87H+8x (CAN0)
D7
001B87H+8x (CAN1)
Read/write→ (R/W)
Initial value→
(X)
6
5
4
3
2
1
0
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
14
13
12
11
10
9
8
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
6
5
4
3
2
1
0
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
14
13
12
11
10
9
8
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
❍ Sets transmitted message data (any of 0 to 8 bytes).
Data is transmitted in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB.
❍ Stores received message data.
Data is stored in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB.
Even if the received message data is less than 8 bytes, the remaining bytes of the data register
(DTRx), to which data are stored, are undefined.
Note:
A write operation to this register should be performed in words. A write operation in bytes causes
undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte
is ignored.
316
CHAPTER 19 CAN CONTROLLER
19.7 Transmission of CAN Controller
When "1" is written to TREQx of the transmission request register (TREQR),
transmission by the message buffer (x) starts. At this time, TREQx becomes "1" and
TCx of the transmission complete register (TCR) becomes "0".
■ Starting Transmission of the CAN Controller
If RFWTx of the remote frame receiving wait register (RFWTR) is "0", transmission starts
immediately. If RFWTx is "1", transmission starts after waiting until a remote frame is received
(RRTRx of the remote request receiving register (RRTRR) becomes "1").
If a request for transmission is made to more than one message buffer (more than one TREQx
is "1"), transmission is performed, starting with the lowest-numbered message buffer.
Message transmission to the CAN bus (by the transmit output pin TX) starts when the bus is idle.
If TRTRx of the transmission RTR register (TRTRR) is "0", a data frame is transmitted. If TRTRx
is "1", a remote frame is transmitted.
If the message buffer competes with other CAN controllers on the CAN bus for transmission and
arbitration fails, or if an error occurs during transmission, the message buffer waits until the bus
is idle and repeats retransmission until it is successful.
■ Canceling a Transmission Request from the CAN Controller
❍ Canceling by transmission cancel register (TCANR)
A transmission request for message buffer (x) having not executed transmission during
transmission waiting can be canceled by writing "1" to TCANx of the transmission cancel
register (TCANR). At completion of cancellation, TREQx becomes "0".
❍ Canceling by storing received message
The message buffer (x) having not executed transmission despite transmission request also
performs reception.
If the message buffer (x) has not executed transmission despite a request for transmission of a
data frame (TRTRx = 0 or TREQx = 1), the transmission request is canceled after storing
received data frames passing through the acceptance filter (TREQx = 0).
Note:
A transmission request is not canceled by storing remote frames (TREQx = 1 remains unchanged).
If the message buffer (x) has not executed transmission despite a request for transmission of a
remote frame (TRTRx = 1 or TREQx = 1), the transmission request is canceled after storing
received remote frames passing through the acceptance filter (TREQx = 0).
Note:
The transmission request is canceled by storing either data frames or remote frames.
317
CHAPTER 19 CAN CONTROLLER
■ Completing Transmission of the CAN Controller
When transmission is successful, RRTRx becomes "0", TREQx becomes "0", and TCx of the
transmission complete register (TCR) becomes "1".
If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt
enable register (TIER) is "1"), an interrupt occurs.
■ Transmission Flowchart of the CAN Controller
Figure 19.7-1 shows a transmission flowchart of the CAN controller.
Figure 19.7-1 Transmission Flowchart of the CAN Controller
Transmission request
(TREQx := 1)
TCx := 0
0
TREQx?
1
0
RFWTx?
1
0
RRTRx?
1
If there are any other message buffers
meeting the above conditions, select
the lowest-numbered message buffer.
NO
Is the bus idle?
YES
0
1
TRTRx?
A data frame is transmitted.
A remote frame is transmitted.
NO
Is transmission
successful?
YES
TCANx?
1
RRTRx: = 0
TREQx: = 0
TCx:
=1
TREQx := 0
1
TIEx ?
0
A transmission complete
interrupt occurs.
End of transmission
318
0
CHAPTER 19 CAN CONTROLLER
19.8 Reception of CAN Controller
Reception starts when the start of data frame or remote frame (SOF) is detected on the
CAN bus.
■ Acceptance Filtering
The received message in the standard frame format is compared with the message buffer (x)
set in the standard frame format (IDEx of the IDE register (IDER) is "0"). The received message
in the extended frame format is compared with the message buffer (x) set (IDEx is "1") in the
extended frame format.
If all the bits set to Compare by the acceptance mask agree after comparison between the
received message ID and acceptance code (ID register (IDRx) for comparing with the received
message ID), the received message passes to the acceptance filter of the message buffer (x).
■ Storing Received Message
When the receive operation is successful, received messages are stored in a message buffer x
including IDs passed through the acceptance filter.
When receiving data frames, received messages are stored in the ID register (IDRx), DLC
register (DLCRx), and data register (DTRx).
Even if received message data is less than 8 bytes, some data is stored in the remaining bytes
of the DTRx and its value is undefined.
When receiving remote frames, received messages are stored only in the IDRx and DLCRx,
and the DTRx remains unchanged.
If there is more than one message buffer including IDs passed through the acceptance filter, the
message buffer x in which received messages are to be stored is determined according to the
following rules.
•
The order of priority of the message buffer x (x = 0 to 15) rises as its number lower; in other
words, message buffer 0 is given the highest and the message buffer 15 is given the lowest
priority.
•
Basically, message buffers with the RCx bit of 0 in the receive completion register (RCR) are
preferred in storing received messages.
•
If the bits of the acceptance mask select register (AMSR) are set to All Bits Compare (for
message buffers with the AMSx.1 and AMSx.0 bits set to "00"), received messages are
stored irrespective of the value of the RCx bit of the RCR.
•
If there are message buffers with the RCx bit of the RCR set to "0", or with the bits of the
AMSR set to All Bits Compare, received messages are stored in the lowest-number (highestpriority) message buffer x.
•
If there are no message buffers above-mentioned, received messages are stored in a lowernumber message buffer x.
319
CHAPTER 19 CAN CONTROLLER
Figure 19.8-1 shows a flowchart for determining the message buffer (x) where received
messages are to be stored. It is recommended that message buffers be arranged in the
following order: message buffers in which each AMSR bit is set to All Bits Compare, message
buffers using AMR0 or AMR1, and message buffers in which each AMSR bit is set to All Bits
Mask.
Figure 19.8-1 Flowchart Determining Message Buffer (x) where Received Messages Stored
Start
Are message buffers with RCx set to "0"
or with AMSx.1 and AMSx.0 set to "00"
found?
NO
YES
Select the lowest-numbered
message buffer.
Select the lowest-numbered
message buffer.
End
■ Receive Overrun
When a message is stored in the message buffer with the corresponding RCx being already set
to "1", it will result in receive overrun. In this case, the corresponding ROVRx bit in the receive
overrun register ROVRR is set to "1".
■ Processing for Reception of Data Frame and Remote Frame
❍ Processing for reception of data frame
RRTRx of the remote request receiving register (RRTRR) becomes "0".
TREQx of the transmission request register (TREQR) becomes "0" (immediately before storing
the received message). A transmission request for message buffer (x) having not executed
transmission will be canceled.
Note:
A request for transmission of either a data frame or remote frame is canceled.
❍ Processing for reception of remote frame
RRTRx becomes "1".
If TRTRx of the transmitting RTR register (TRTRR) is "1", TREQx becomes "0". As a result, the
request for transmitting remote frame to message buffer having not executed transmission will
be canceled.
320
CHAPTER 19 CAN CONTROLLER
Notes:
• A request for data frame transmission is not canceled.
• For cancellation of a transmission request, see "19.7 Transmission of CAN Controller".
■ Completing Reception
RCx of the reception complete register (RCR) becomes "1" after storing the received message.
If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is "1"),
an interrupt occurs.
Note:
This CAN controller will not receive any messages transmitted by itself.
321
CHAPTER 19 CAN CONTROLLER
19.9 Reception Flowchart of CAN Controller
Figure 19.9-1 shows a reception flowchart of the CAN controller.
■ Reception Flowchart of the CAN Controller
Figure 19.9-1 Reception Flowchart of the CAN Controller
Detection of start of data frame
or remote frame (SOF)
NO
Is any message buffer (x) passing to
the acceptance filter found?
YES
NO
Is reception
successful?
YES
Determine message buffer (x) where received messages to be stored.
Store the received message
in the message buffer (x).
1
RCx?
0
Data frame
ROVRx := 1
Remote frame
Received message?
RRTRx := 0
RRTRx := 1
1
TRTRx?
0
TREQx := 0
RCx := 1
RIEx ?
0
End of reception
322
1
A reception interrupt
occurs.
CHAPTER 19 CAN CONTROLLER
19.10 How to Use the CAN Controller
The following settings are required to use the CAN controller:
• Bit timing
• Frame format
• ID
• Acceptance filter
• Low-power-consumption mode
■ Setting Bit Timing
The bit timing register (BTR) should be set during bus operation stop (when the bus operation
stop bit (HALT) of the control status register (CSR) is "1").
After the setting completion, write "0" to HALT to cancel bus operation stop.
■ Setting Frame Format
Set the frame format used by the message buffer (x). When using the standard frame format,
set IDEx of the IDE register (IDER) to "0". When using the extended frame format, set IDEx to
"1".
This setting should be made when the message buffer (x) is invalid (BVALx of the message
buffer valid register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause
unnecessary received messages to be stored.
■ Setting ID
Set the message buffer (x) ID to ID28 to ID0 of ID register (IDRx). The message buffer (x) ID
need not be set to ID11 to ID0 in the standard frame format. The message buffer (x) ID is used
as a transmission message at transmission and is used as an acceptance code at reception.
This setting should be made when the message buffer (x) is invalid (BVALx of the message
buffer valid register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause
unnecessary received messages to be stored.
■ Setting Acceptance Filter
The acceptance filter of the message buffer (x) is set by an acceptance code and acceptance
mask set. It should be set when the acceptance message buffer (x) is invalid (BVALx of the
message buffer enable register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1)
may cause unnecessary received messages to be stored.
Set the acceptance mask used in each message buffer (x) by the acceptance mask select
register (AMSR). The acceptance mask registers (AMR0 and AMR1) should also be set if used
(For the setting details, see "19.6.18 Acceptance Mask Select Register (AMSR)" and "19.6.19
Acceptance Mask Registers 0/1 (AMR0/AMR1)").
The acceptance mask should be set so that a transmission request may not be canceled when
unnecessary received messages are stored. For example, it should be set to a full-bit
comparison if only one specific ID message is used for the transmission.
323
CHAPTER 19 CAN CONTROLLER
■ Setting low-power-consumption Mode
To set the F2MC-16LX in a low-power-consumption mode (Stop, Watch, Hardware Standby,
etc.), write "1" to the bus operation stop bit (HALT) of the control status register (CSR), and then
check that the bus operation has stopped (HALT = 1).
324
CHAPTER 19 CAN CONTROLLER
19.11 Procedure for Transmission by Message Buffer (x)
After setting the bit timing, frame format, ID, and acceptance filter, set BVALx to "1" to
activate the message buffer (x).
■ Procedure for Transmission by Message Buffer (x)
❍ Setting transmit data length code
Set the transmit data length code (byte count) to DLC3 to DLC0 of the DLC register (DLCRx).
For data frame transmission (when TRTRx of the transmission RTR register (TRTRR) is "0"),
set the data length of the transmitted message.
For remote frame transmission (when TRTRx = 1), set the data length (byte count) of the
requested message.
Note:
Setting other than 0000 to 1000 (0 to 8 bytes) is prohibited.
❍ Setting transmit data (only for transmission of data frame)
For data frame transmission (when TRTRx of the transmission register (TRTRR) is "0"), set data
as the count of byte transmitted in the data register (DTRx).
Note:
Transmit data should be rewritten while the TREQx bit of the transmission request register
(TREQR) set to "0". There is no need for setting the BVALx bit of the message buffer valid register
(BVALR) to "0". Setting the BVALx bit to "0" may cause incoming remote frame to be lost.
❍ Setting transmission RTR register
For data frame transmission, set TRTRx of the transmission RTR register (TRTRR) to "0".
For remote frame transmission, set TRTRx to "1".
❍ Setting conditions for starting transmission (only for transmission of data frame)
Set RFWTx of the remote frame receiving wait register (RFWTR) to "0" to start transmission
immediately after a request for data frame transmission is set (TREQx of the transmission
request register (TREQR) is "1" and TRTRx of the transmission RTR register (TRTRR) is "0").
Set RFWTx to "1" to start transmission after waiting until a remote frame is received (RRTRx of
the remote request receiving register (RRTRR) becomes "1") after a request for data frame
transmission is set (TREQx = 1 and TRTRx = 0).
325
CHAPTER 19 CAN CONTROLLER
Note:
Remote frame transmission cannot be performed, if RFWTx is set to "1".
❍ Setting transmission complete interrupt
When generating a transmission complete interrupt, set TIEx of the transmission complete
interrupt enable register (TIER) to "1".
When not generating a transmission complete interrupt, set TIEx to "0".
❍ Setting transmission request
For a transmission request, set TREQx of the transmission request register (TREQR) to "1".
❍ Canceling transmission request
When canceling a request for transmission to the message buffer (x), write "1" to TCANx of the
transmission cancel register (TCANR).
Check TREQx. For TREQx = 0, transmission cancellation is terminated or transmission is
completed. Check TCx of the transmission complete register (TCR). For TCx = 0, transmission
cancellation is terminated. For TCx = 1, transmission is completed.
❍ Processing for completion of transmission
If transmission is successful, TCx of the transmission complete register (TCR) becomes "1".
If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt
enable register (TIER) is "1"), an interrupt occurs.
After checking the transmission completion, write "0" to TCx and set it to 0. This cancels the
transmission complete interrupt.
In the following cases, the waiting transmission request is canceled by receiving and storing a
message.
•
Request for data frame transmission by reception of data frame
•
Request for remote frame transmission by reception of data frame
•
Request for remote frame transmission by reception of remote frame
Request for data frame transmission is not canceled by receiving and storing a remote frame. ID
and DLC, however, are changed by the ID and DLC of the received remote frame. Note that the
ID and DLC of data frame to be transmitted become the value of received remote frame.
326
CHAPTER 19 CAN CONTROLLER
19.12 Procedure for Reception by Message Buffer (x)
After setting the bit timing, frame format, ID, and acceptance filter, make the settings
described below.
■ Procedure for Reception by Message Buffer (x)
❍ Setting reception interrupt
To enable reception interrupt, set RIEx of the reception interrupt enable register (RIER) to "1".
To disable reception interrupt, set RIEx to "0".
❍ Starting reception
When starting reception after setting, set BVALx of the message buffer valid register (BVALR) to
"1" to make the message buffer (x) valid.
❍ Processing for reception completion
If reception is successful after passing to the acceptance filter, the received message is stored
in the message buffer (x) and RCx of the reception complete register (RCR) becomes "1". For
data frame reception, RRTRx of the remote request receiving register (RRTRR) becomes "0".
For remote frame reception, RRTRx becomes "1".
If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is "1"),
an interrupt occurs.
After checking the reception completion (RCx = 1), process the received message.
After completion of processing the received message, check ROVRx of the reception overrun
register (ROVRR).
If ROVRx = 0, the processed received message is valid. Write 0 to RCx to set it to "0" (the
reception complete interrupt is also canceled) to terminate reception.
If ROVRx = 1, a reception overrun occurred and the next message may have overwritten the
processed message. In this case, received messages should be processed again after setting
the ROVRx bit to "0" by writing "0" to it.
Figure 19.12-1 shows an example of receive interrupt handling.
327
CHAPTER 19 CAN CONTROLLER
Figure 19.12-1 Example of Receive Interrupt Handling
Interrupt with RCx = 1
Read received messages.
A: = ROVRx
ROVRx := 0
A = 0?
YES
RCx := 0
End
328
NO
CHAPTER 19 CAN CONTROLLER
19.13 Setting Configuration of Multi-level Message Buffer
If the receptions are performed frequently, or if several different ID’s of messages are
received, in other words, if there is insufficient time for handling messages, more than
one message buffer can be combined into a multi-level message buffer to provide
allowance for processing time of the received message by CPU.
■ Setting Configuration of Multi-level Message Buffer
To provide a multi-level message buffer, the same acceptance filter must be set in the combined
message buffers.
If the bits of the acceptance mask select register (AMSR) are set to All Bits Compare ((AMSx.1,
AMSx.0) = (0, 0)), multi-level message configuration of message buffers is not allowed. This is
because All Bits Compare causes received messages to be stored irrespective of the value of
the RCx bit of the receive completion register (RCR), so received messages are always stored
in lower-numbered (lower-priority) message buffers even if All Bits Compare and identical
acceptance code (ID register (IDRx)) are specified for more than one message buffer.
Therefore, All Bits Compare and identical acceptance code should not be specified for more
than one message buffer.
Figure 19.13-1 shows operational examples of multi-level message buffers.
329
CHAPTER 19 CAN CONTROLLER
Figure 19.13-1 Examples of Operation of Multi-level Message Buffer
Initialization
AMS15, AMS14, AMS13
AMSR 10 10 10
Select AMR0.
...
AM28 to AM18
AMS0
ID28 to ID18
0000 1111 111
RC15, RC14, RC13
IDE
...
Message buffer 13
0101 0000 000
0
...
RCR 0
0
0
...
Message buffer 14
0101 0000 000
0
...
ROVRR 0
0
0
...
0
...
Message buffer 15
0101 0000 000
ROVR15, ROVR14, ROVR13
Mask
Message receiving
"The received message is stored in message buffer 13.
IDE
ID28 to ID18
Message receiving
0101 1111 000
0
...
Message buffer 13
0101 1111 000
0
...
RCR 0
0
1
...
ROVRR 0
0
0
...
Message buffer 14
0101 0000 000
0
...
Message buffer 15
0101 0000 000
0
...
Message receiving
"The received message is stored in message buffer 14.
Message receiving
0101 1111 001
0
...
Message buffer 13
0101 1111 000
0
...
RCR 0
1
1
...
ROVRR 0
0
0
...
Message buffer 14
0101 1111 001
0
...
Message buffer 15
0101 0000 000
0
...
Message receiving
"The received message is stored in message buffer 15.
Message receiving
0101 1111 010
0
...
Message buffer 13
0101 1111 000
0
...
RCR 1
1
1
...
ROVRR 0
0
0
...
Message buffer 14
0101 1111 001
0
...
Message buffer 15
0101 1111 010
0
...
Message receiving "An overrun occurs (ROVR13 = 1) and the received message is stored in message buffer 13.
330
Message receiving
0101 1111 011
0
...
Message buffer 13
0101 1111 011
0
...
RCR 1
1
1
...
Message buffer 14
0101 1111 001
0
...
ROVRR 0
0
1
...
Message buffer 15
0101 1111 010
0
...
CHAPTER 19 CAN CONTROLLER
Note:
Four messages are received with the same acceptance filter set in message buffers 13, 14 and 15.
331
CHAPTER 19 CAN CONTROLLER
19.14 Precautions when Using CAN Controller
The use of BVAL bits may affect malfunction of CAN Controller when messages
buffers are set disabled (BVAL bit of message buffer valid register is "0") while CAN
Controller is participating in CAN communication (read value of HALT bit is "0" and
CAN Controller is ready to receive or transmit messages). It is avoided by the
following operation.
■ Caution for Using CAN Controller
❍ Condition
When following two conditions occur at the same time, CAN Controller will not perform to
receive or transmit messages normally.
•
CAN Controller is participating in the CAN communication. (i.e. The read value of HALT bit is
0 and CAN Controller is ready to receive or transmit messages)
•
Message buffers are read or written when the message buffers are disabled by BVAL bits.
❍ Operation for re-configuring receiving message buffers
According to CAN application, the configuration of message buffer may be changed based on
the information gotten after CAN communication.
While CAN Controller is participating in CAN communication (the read value of HALT bit is 0
and CAN Controller is ready to receive or transmit messages), it is necessary to following one
from the two operations described below to re-configure message buffers by ID, AMS and
AMR0/1 register-settings.
•
Use of HALT bit
Write "1" to HALT bit and read it back for checking the result is "1". Then change the settings
for ID Register (IDR), Acceptance Mask Select Register (AMSR), Acceptance Mask Register
0/1 (AMR0/AMR1).
•
No Use of Message Buffer 0
Don't use the message buffer 0 for either transmitting or receiving. In other words, disable
message buffer (BVAL0=0), prohibit receive interrupt (RIE0=0) and do not request
transmission (TREQ0=0).
❍ Operation for processing received message
Don't use the receiving prohibition by BVAL bit to avoid over-written of next message when the
receiving message reads from message buffer. Do not make the receiving disable by BVAL bit
of massage buffer valid register (BVALR:BAVL=0). Use the ROVR bit for checking if over-write
has been performed. For details, refer to sections "19.6.16 Receive Overrun Register
(ROVRR)" and "19.12 Procedure for Reception by Message Buffer (x)".
❍ Operation for suppressing transmission request
Don't use BVAL bit for suppressing transmission request (BVAL=0), use TCAN bit instead of it
(TCAN=1).
332
CHAPTER 19 CAN CONTROLLER
❍ Operation for composing transmission message
For composing a transmission message, it is necessary to disable the message buffer by BVAL
bit to change contents of ID and IDE registers. In this case, BVAL bit should reset (BVAL=0)
after checking if TREQ bit is 0 or after completion of the previous message transmission (TC=1).
333
CHAPTER 19 CAN CONTROLLER
334
CHAPTER 20
STEPPING MOTOR CONTROLLER
This chapter explains the functions and operations of the stepping motor controller.
20.1 Outline of Stepping Motor Controller
20.2 Stepping Motor Controller Registers
20.3 Notes on Using the Stepping Motor Controller
335
CHAPTER 20 STEPPING MOTOR CONTROLLER
20.1 Outline of Stepping Motor Controller
The Stepping Motor Controller consists of two PWM Pulse Generators, four motor
drivers and Selector Logic. The four motor drivers have high output drive capabilities
and they can be directly connected to the four ends of two motor coils. The
combination of the PWM Pulse Generators and Selector Logic is designed to control
the rotation of the motor. A Synchronization mechanism assures the synchronous
operations of the two PWMs. The following sections describe the Stepping Motor
Controller 0 only. The other controllers have the same functions. The register
addresses are found in the I/O map.
■ Block Diagram of Stepping Motor Controller
Figure 20.1-1 shows a block diagram of the stepping motor controller.
Figure 20.1-1 Block Diagram of Stepping Motor Controller
Machine Clock
OE1
CK
Prescaler
EN
P1
PWM1P0
Selector
PWM1 pulse generator
PWM
PWM1M0
P0
PWM1 Compare register
PWM1 Select register
OE2
CK
CE
EN
Output enable
PWM2P0
Selector
PWM2 pulse generator
PWM2M0
PWM
Load
PWM2 Compare register
336
Output enable
BS
PWM2 Select register
CHAPTER 20 STEPPING MOTOR CONTROLLER
20.2 Stepping Motor Controller Registers
The stepping motor controller has the following five types of registers:
• PWM control 0 register (PWC0)
• PWM1 compare 0 register (PWC10)
• PWM2 compare 0 register (PWC20)
• PWM1 select register (PWS10)
• PWM2 select register (PWS20)
■ Stepping Motor Controller Registers
Figure 20.2-1 Stepping Motor Controller Registers
PWM Control 0 register
bit
7
Address: 000062H
OE2
Read/write→ (R/W)
Initial value→
(0)
6
5
4
3
2
1
0
OE1
(R/W)
(0)
P1
(R/W)
(0)
P0
(R/W)
(0)
CE
(R/W)
(0)
(-)
(-)
(-)
(-)
Reserved
PWC0
(R/W)
(0)
PWM1 Compare 0 register
bit
7
Address: 001950H
D7
Read/write→ (R/W)
Initial value→
(X)
6
5
4
3
2
1
0
D6
(R/W)
(X)
D5
(R/W)
(X)
D4
(R/W)
(X)
D3
(R/W)
(X)
D2
(R/W)
(X)
D1
(R/W)
(X)
D0
(R/W)
(X)
14
13
12
11
10
9
8
D6
(R/W)
(X)
D5
(R/W)
(X)
D4
(R/W)
(X)
D3
(R/W)
(X)
D2
(R/W)
(X)
D1
(R/W)
(X)
D0
(R/W)
(X)
PWC10
PWM2 Compare 0 register
bit
15
Address: 001951H
D7
Read/write→ (R/W)
Initial value→
(X)
PWC20
PWM1 Select register
bit
Address: 001952H
Read/write→
Initial value→
7
6
5
4
3
2
1
0
(-)
(-)
(-)
(-)
P2
(R/W)
(0)
P1
(R/W)
(0)
P0
(R/W)
(0)
M2
(R/W)
(0)
M1
(R/W)
(0)
M0
(R/W)
(0)
PWS10
PWM2 Select register
bit
Address: 001953H
Read/write→
Initial value→
15
14
13
12
11
10
9
8
(-)
(-)
BS
(R/W)
(0)
P2
(R/W)
(0)
P1
(R/W)
(0)
P0
(R/W)
(0)
M2
(R/W)
(0)
M1
(R/W)
(0)
M0
(R/W)
(0)
PWS20
337
CHAPTER 20 STEPPING MOTOR CONTROLLER
20.2.1 PWM Control 0 register (PWC0)
The PWM control 0 register (PWC0) starts and stops the stepping motor controller,
controls interrupts, and sets the external output pins.
■ PWM Control 0 Register (PWC0)
Figure 20.2-2 PWM Control 0 Register (PWC0)
PWM Control 0 register
bit
7
Address: 000062H
OE2
Read/write→ (R/W)
Initial value→
(0)
6
5
4
3
2
1
0
OE1
(R/W)
(0)
P1
(R/W)
(0)
P0
(R/W)
(0)
CE
(R/W)
(0)
(-)
(-)
(-)
(-)
Reserved
PWC0
(R/W)
(0)
[bit 7] OE2: Output enable bit
When this bit is set to "1", the external pins are assigned as PWM2P0 and PWM2M0
outputs. Otherwise they can be used as general purpose I/O.
[bit 6] OE1: Output enable bit
When this bit is set to "1", the external pins are assigned as PWM1P0 and PWM1M0
outputs. Otherwise they can be used as general purpose I/O.
[bit 5, bit 4] P1 to P0: Operation clock select bits
These bits specify the clock input signal for the PWM pulse generators.
P1
P0
Clock input
0
0
Machine clock
0
1
1/2 Machine clock
1
0
1/4 Machine clock
1
1
1/8 Machine clock
[bit 3] CE: Count enable bit
This bit enables the operation of the PWM pulse generators. When it is set to "1", the PWM
pulse generators start their operation. Note that the PWM2 pulse generator starts the
operation one machine clock cycle after the PWM1 pulse generators is started. This is to
help reduce the switching noise from the output drivers.
[bit 0] Reserved bit
This is a reserved bit. Always write "0" to this bit.
338
CHAPTER 20 STEPPING MOTOR CONTROLLER
20.2.2 PWM1&2 Compare Registers (PWC10/PWC20)
The contents of the two 8-bit compare registers (PWC10/PWC20) determine the widths
of PWM pulses.
The stored value of "00H" represents the PWM duty of 0% and "FFH" represents the
duty of 99.6%.
■ PWM1&2 Compare Registers (PWC10/PWC20)
PWM1&2 compare registers (PWC10/PWC20) are accessible at any time, however the modified
values are reflected to the pulse width at the end of the current PWM cycle after the BS bit of
the PWM2 Select register is set to "1".
Figure 20.2-3 PWM1&2 Compare Registers (PWC10/PWC20)
PWM1 Compare 0 register
bit
7
Address: 001950H
D7
Read/write→ (R/W)
Initial value→
(X)
6
5
4
3
2
1
0
D6
(R/W)
(X)
D5
(R/W)
(X)
D4
(R/W)
(X)
D3
(R/W)
(X)
D2
(R/W)
(X)
D1
(R/W)
(X)
D0
(R/W)
(X)
PWC10
PWM2 Compare 0 register
bit
15
Address: 001951H
D7
Read/write→ (R/W)
Initial value→
(X)
14
13
12
11
10
9
8
D6
(R/W)
(X)
D5
(R/W)
(X)
D4
(R/W)
(X)
D3
(R/W)
(X)
D2
(R/W)
(X)
D1
(R/W)
(X)
D0
(R/W)
(X)
PWC20
One PWM Cycle
256 input clock cycles
Register value
00H
80H
128 input clock cycles
FFH
255 input clock cycles
339
CHAPTER 20 STEPPING MOTOR CONTROLLER
20.2.3 PWM1&2 Select Registers (PWS10/PWS20)
The PWM1&2 Select Registers (PWS10/PWS20) select "0", "1", the PWM pulse, or high
impedance for the external pin output of the stepping motor controller.
■ PWM1&2 Select Registers (PWS10/PWS20)
Figure 20.2-4 PWM1&2 Select Registers (PWS10/PWS20)
PWM1 Select register
bit
Address: 001952H
Read/write→
Initial value→
7
6
5
4
3
2
1
0
(-)
(-)
(-)
(-)
P2
(R/W)
(0)
P1
(R/W)
(0)
P0
(R/W)
(0)
M2
(R/W)
(0)
M1
(R/W)
(0)
M0
(R/W)
(0)
PWS10
PWM2 Select register
bit
Address: 001953H
Read/write→
Initial value→
15
14
13
12
11
10
9
8
(-)
(-)
BS
(R/W)
(0)
P2
(R/W)
(0)
P1
(R/W)
(0)
P0
(R/W)
(0)
M2
(R/W)
(0)
M1
(R/W)
(0)
M0
(R/W)
(0)
PWS20
[bit 14] BS: Update bit
This bit is prepared to synchronize the settings for the PWM outputs. Any modifications in
the two compare registers and two select registers are not reflected to the output signals
until this bit is set.
When this bit is set to "1", the PWM pulse generators and selectors load the register
contents at the end of the current PWM cycle. The BS bit is reset to "0" automatically at the
beginning of the next PWM cycle. If the BS bit is set to "1" by software at the same time as
this automatic reset, the BS bit is set to "1" (or remains unchanged) and the automatic reset
is cancelled.
[bit 13 to bit 11] P2 to P0: Output Select bits
These bits selects the output signal at PWM2P0.
[bit 10 to bit 8] M2 to M0: Output Select bits
These bits selects the output signal at PWM2M0.
[bit 5 to bit 3] P2 to P0: Output Select bits
These bits selects the output signal at PWM1P0.
340
CHAPTER 20 STEPPING MOTOR CONTROLLER
[bit 2 to bit 0] M2 to M0: Output Select bits
These bits selects the output signal at PWM1M0.
The following table shows the relationship between the output levels and select bits.
P2
P1
P0
PWMnP0
M2
M1
M0
PWMnM0
0
0
0
"L"
0
0
0
"L"
0
0
1
"H"
0
0
1
"H"
0
1
X
PWM pulses
0
1
X
PWM pulses
1
X
X
High impedance
1
X
X
High impedance
341
CHAPTER 20 STEPPING MOTOR CONTROLLER
20.3 Notes on Using the Stepping Motor Controller
This section provides notes on using the stepping motor controller.
■ Notes on Changing the PWM Setting Values
PWM Compare Register 1 (PWC10), PWM Compare Register 2 (PWC20), PWM Selection
Register 1 (PWS10), and PWM Selection Register 2 (PWS20) can always be accessed. To
change the setting of the PWM’s "H" width or PWM output, write the setting values to these
registers, then set the BS bit of PWM Selection Register 2 to "1" (or do this simultaneously).
If the BS bit is set to "1", the new setting value will become effective at the end of the current
PWM cycle, and the BS bit is automatically cleared.
If setting the BS bit to "1" and resetting the BS bit at the end of the PWM cycle both occur at the
same time, writing "1" has priority and resetting the BS bit will be cancelled.
342
CHAPTER 21
SOUND GENERATOR
This chapter explains the functions and operations of the sound generator.
21.1 Outline of Sound Generator
21.2 Sound Generator Registers
343
CHAPTER 21 SOUND GENERATOR
21.1 Outline of Sound Generator
The Sound Generator consists of the Sound Control register, Frequency Data register,
Amplitude Data register, Decrement Grade register, Tone Count register, PWM pulse
generator, Frequency counter, Decrement counter and Tone Pulse counter.
■ Block Diagram of Sound Generator
Figure 21.1-1 shows a block diagram of the sound generator.
Figure 21.1-1 Block Diagram of Sound Generator
Clock input
Prescaler
S1
S0
8bit PWM pulse
Generator CO
EN
PWM
CI
Frequency
Counter
Toggle
Flip-flop
reload
Amplitude Data
register
reload
Q
1/d
Frequency data
register
DEC
DEC
Decrement
Counter
D
EN
CO
EN
CI
CO
EN
SGA
OE1
Decrement Grade
register
Tone Pulse
Counter
Tone Count
register
OE1
Mix
SGO
TONE OE2
OE2
CI
CO
EN
INTE
INT
ST
IRQ
344
CHAPTER 21 SOUND GENERATOR
21.2 Sound Generator Registers
The sound generator has the following types of registers:
• Sound control register
• Frequency data register
• Amplitude data register
• Decrement grade register
• Tone count register
■ Sound Generator Registers
Figure 21.2-1 Sound Generator Registers
Sound Control register
bit
7
6
5
4
3
2
1
0
Address: 00005EH
S1
Read/write→ (R/W)
Initial value→
(0)
S0
(R/W)
(0)
TONE
(R/W)
(0)
OE2
(R/W)
(0)
OE1
(R/W)
(0)
INTE
(R/W)
(0)
INT
(R/W)
(0)
ST
(R/W)
(0)
bit
15
Address: 00005FH
Reserved
Read/write→ (R/W)
Initial value→
(0)
14
13
12
11
10
9
8
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
BUSY
(R)
(0)
DEC
(R/W)
(0)
SGCR
SGCR
Frequency Data register
bit
7
Address: 001946H
D7
Read/write→ (R/W)
Initial value→
(X)
6
5
4
3
2
1
0
D6
(R/W)
(X)
D5
(R/W)
(X)
D4
(R/W)
(X)
D3
(R/W)
(X)
D2
(R/W)
(X)
D1
(R/W)
(X)
D0
(R/W)
(X)
14
13
12
11
10
9
8
D6
(R/W)
(0)
D5
(R/W)
(0)
D4
(R/W)
(0)
D3
(R/W)
(0)
D2
(R/W)
(0)
D1
(R/W)
(0)
D0
(R/W)
(0)
6
5
4
3
2
1
0
D6
(R/W)
(X)
D5
(R/W)
(X)
D4
(R/W)
(X)
D3
(R/W)
(X)
D2
(R/W)
(X)
D1
(R/W)
(X)
D0
(R/W)
(X)
SGFR
Amplitude Data register
bit
15
Address: 001947H
D7
Read/write→ (R/W)
Initial value→
(0)
SGAR
Decrement Grade register
bit
7
Address: 001948H
D7
Read/write→ (R/W)
Initial value→
(X)
SGDR
Tone Count register
bit
15
Address: 001949H
D7
Read/write→ (R/W)
Initial value→
(X)
14
13
12
11
10
9
8
D6
(R/W)
(X)
D5
(R/W)
(X)
D4
(R/W)
(X)
D3
(R/W)
(X)
D2
(R/W)
(X)
D1
(R/W)
(X)
D0
(R/W)
(X)
SGTR
345
CHAPTER 21 SOUND GENERATOR
21.2.1 Sound Control Register (SGCR)
The sound control register (SGCR) controls the operation status of the sound
generator by controlling interrupts and setting the external output pins.
■ Sound Control Register (SGCR)
Figure 21.2-2 Sound Control Register (SGCR)
bit
7
6
5
4
3
2
1
0
Address: 00005EH
S1
Read/write→ (R/W)
Initial value→
(0)
S0
(R/W)
(0)
TONE
(R/W)
(0)
OE2
(R/W)
(0)
OE1
(R/W)
(0)
INTE
(R/W)
(0)
INT
(R/W)
(0)
ST
(R/W)
(0)
bit
15
Address: 00005FH
Reserved
Read/write→ (R/W)
Initial value→
(0)
14
13
12
11
10
9
8
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
BUSY
(R)
(0)
DEC
(R/W)
(0)
SGCR
SGCR
[bit 15] Reserved bit
This is a reserved bit. Always write "0" to this bit.
[bit 9] BUSY: Busy bit
This bit indicates whether the Sound Generator is in operation. This bit is set to "1" upon the
ST bit is set to "1". It is reset to "0" when the ST bit is reset to "0" and the operation is
completed at the end of one tone cycle. Any write instructions performed on this bit has no
effect.
[bit 8] DEC: Auto-decrement enable bit
The DEC bit is prepared for an automatic de-gradation of the sound in conjunction with the
Decrement Grade register.
If this bit is set to "1", the stored value in the Amplitude Data register is decremented by
1(one), every time when the Decrement counter counts the number of tone pulses from the
toggle flip-flop specified by the Decrement Grade register.
[bit 7, bit 6] S1 and S0: Operation clock select bits
These bits specify the clock input signal for the Sound Generator.
Table 21.2-1 Clock input
346
S1
S0
Clock input
0
0
Machine clock
0
1
1/2 Machine clock
1
0
1/4 Machine clock
1
1
1/8 Machine clock
CHAPTER 21 SOUND GENERATOR
[bit 5] TONE: Tone output bit
When this bit is set to "1", the SGO signal becomes a simple square-waveform (tone pulses)
from the toggle flip-flop. Otherwise it is the mixed (AND logic) signal of the tone and PWM
pulses.
[bit 4] OE2: Sound output enable bit
When this bit is set to "1", the external pin is assigned as the SGO output. Otherwise the pin
can be used as a general purpose I/O. To enable the SGO output, the corresponding bit of
the Port Direction register should also be set to "1".
[bit 3] OE1: Amplitude output enable bit
When this bit is set to "1", the external pin is assigned as the SGA output. Otherwise the pin
can be used as a general purpose I/O. To enable the SGA output, the corresponding bit of
the Port Direction register should also be set to "1".
The SGA signal is the PWM pulses from the PWM pulse generator representing the
amplitude of the sound.
[bit 2] INTE: Interrupt enable bit
This bit enables the interrupt signal of the Sound Generator. When this bit is "1" and the INT
bit is set to "1", the Sound Generator signals an interrupt.
[bit 1] INT: Interrupt bit
This bit is set to "1" when the Tone Pulse counter counts the number of the tone pulses
specified by the Tone Count register and Decrement Grade register.
This bit is reset to "0" by writing "0". Writing "1" has no effect and Read-Modify-Write
instructions always result in reading "1".
[bit 0] ST: Start bit
This bit is for starting the operation of the Sound Generator. While this bit is "1", the Sound
Generator perform its operation.
When this bit is reset to "0", the Sound Generator stops its operation at the end of the current
tone cycle. The BUSY bit indicates whether the Sound Generator is fully stopped.
When this bit is changed from "0" to "1", the value of Frequency Data register, Amplitude
Data register, Decrement Grade register, and Tone Count register is loaded into each
counter.
347
CHAPTER 21 SOUND GENERATOR
21.2.2 Frequency Data register (SGFR)
The Frequency Data register (SGFR) stores the reload value for the Frequency Counter.
The stored value represents the frequency of the sound (or the tone signal from the
toggle flip-flop). The register value is reloaded into the counter at Frequency Counter
underflow and PWM pulse generator underflow.
The following figure shows the relationship between the tone signal and the register
value.
■ Frequency Data Register (SGFR)
Figure 21.2-3 Frequency Data Register (SGFR)
bit
7
Address: 001946H
D7
Read/write→ (R/W)
Initial value→
(X)
6
5
4
3
2
1
0
D6
(R/W)
(X)
D5
(R/W)
(X)
D4
(R/W)
(X)
D3
(R/W)
(X)
D2
(R/W)
(X)
D1
(R/W)
(X)
D0
(R/W)
(X)
SGFR
Figure 21.2-4 shows the relationship between a tone signal and a register value.
Figure 21.2-4 Relationship between Tone Signal and Register Value
One Tone Cycle
Tone signal
(register value+1) x
One PWM cycle
(register value+1) x
One PWM cycle
It should be noted that modifications of the register value while operation may alter the duty
cycle of 50% depending on the timing of the modification.
348
CHAPTER 21 SOUND GENERATOR
21.2.3 Amplitude Data Register (SGAR)
The Amplitude Data register (SGAR) stores the reload value for the PWM pulse
generator. The register value represents the amplitude of the sound. The register value
is reloaded into the PWM pulse generator at falling edge of tone signal.
■ Amplitude Data Register (SGAR)
Figure 21.2-5 Amplitude Data Register (SGAR)
bit
15
Address: 001947H
D7
Read/write→ (R/W)
Initial value→
(0)
14
13
12
11
10
9
8
D6
(R/W)
(0)
D5
(R/W)
(0)
D4
(R/W)
(0)
D3
(R/W)
(0)
D2
(R/W)
(0)
D1
(R/W)
(0)
D0
(R/W)
(0)
SGAR
When the DEC bit is "1" and the Decrement counter reaches its reload value, this register value
is decremented by 1(one). And when the register value reaches "00", further decrements are
not performed. However the sound generator continues its operation until the ST bit is cleared.
Figure 21.2-6 shows the relationship between the register value and the PWM pulse.
Figure 21.2-6 Relationship between Register Value and PWM Pulse
One PWM Cycle
256 input clock cycles
Register value
00H
One input clock cycle
80H
129 input clock cycles
FEH
255 input clock cycles
FFH
256 input clock cycles
When the register value is set to "FF", the PWM signal is always "1".
349
CHAPTER 21 SOUND GENERATOR
21.2.4 Decrement Grade Register (SGDR)
The Decrement Grade register (SGDR) stores the reload value for the Decrement
counter. They are prepared to automatically decrement the stored value in the
Amplitude Data register. The register value is reloaded into the counter at Decrement
counter underflow and falling edge of tone signal.
■ Decrement Grade Register (SGDR)
Figure 21.2-7 Decrement Grade Register (SGDR)
bit
7
Address: 001948H
D7
Read/write→ (R/W)
Initial value→
(X)
6
5
4
3
2
1
0
D6
(R/W)
(X)
D5
(R/W)
(X)
D4
(R/W)
(X)
D3
(R/W)
(X)
D2
(R/W)
(X)
D1
(R/W)
(X)
D0
(R/W)
(X)
SGDR
When the DEC bit is "1" and the Decrement counter counts the number of tone pulses up to the
reload value, the stored value in the Amplitude Data register is decremented by 1(one) at the
end of the tone cycle.
This operation realizes automatic de-gradation of the sound with fewer number of CPU
interventions.
It should be noted that the number of the tone pulses specified by this register equals to
"register value +1". When the Decrement Grade register is set to "00", the decrement operation
is performed every tone cycle.
350
CHAPTER 21 SOUND GENERATOR
21.2.5 Tone Count Register (SGTR)
The Tone Count register (SGTR) stores the reload value for the Tone Pulse counter.
The Tone Pulse counter accumulate the number of tone pulses (or number of
decrement operations) and when it reaches the reload value it sets the INT bit. They
are intended to reduce the frequency of interrupts. The register value is reloaded into
the counter at Tone Pulse counter underflow, Decrement counter underflow, and
falling edge of tone signal.
■ Tone Count Register (SGTR)
Figure 21.2-8 Tone Count Register (SGTR)
bit
15
Address: 001949H
D7
Read/write→ (R/W)
Initial value→
(X)
14
13
12
11
10
9
8
D6
(R/W)
(X)
D5
(R/W)
(X)
D4
(R/W)
(X)
D3
(R/W)
(X)
D2
(R/W)
(X)
D1
(R/W)
(X)
D0
(R/W)
(X)
SGTR
The count input of the Tone Pulse counter is connected to the carry-out signal from the
Decrement counter. And when the Tone count register is set to "00", the Tone Pulse counter
sets the INT bit every carry-out from the Decrement counter. Thus the number of accumulated
tone pulses is;
((Decrement Grade register) +1) x ((Tone Count register) +1)
i.e. When the both registers are set to "00", the INT bit is set every tone cycle.
351
CHAPTER 21 SOUND GENERATOR
352
CHAPTER 22
ADDRESS MATCH DETECTION FUNCTION
This chapter explains the address match detection function and operation.
22.1 Outline of the Address Match Detection Function
22.2 Registers of the Address Match Detection Function
22.3 Operation of the Address Match Detection Function
22.4 Example of the Address Match Detection Function
353
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
22.1 Outline of the Address Match Detection Function
When an address matches the value set in the address detection register, the
instruction code to be read by the CPU is replaced with the INT9 instruction code
(01H). Consequently, the CPU executes the INT9 instruction when executing a
specified instruction. The address match detection function can be achieved using the
INT9 interrupt routine for processing.
There are two address detection registers, each with a compare enable bit. When an
address matches the value set in the address detection register and the interrupt
enable bit is "1", the instruction code to be read by the CPU is replaced with the INT9
instruction code forcibly.
■ Block Diagram of the Address Match Detection Function
Address latch
Address detection
register
Enable bit
F2MC-16LX bus
354
Comparison
Figure 22.1-1 Block Diagram of the Address Match Detection Function
INT9
instruction
F2MC-16LX
CPU core
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
22.2 Registers of the Address Match Detection Function
The two types of registers for the address match detection function are as follows:
• Program address detection registers (PADR0 and PADR1)
• Program address detection control status register (PACSR)
■ Program Address Detection Registers (PADR0 and PADR1)
The program address detection registers 0 and 1 (PADR0 and PADR1) compare the address
with the value written in each register. If they match when the interrupt enable bit corresponding
to ADCSR is "1", the CPU is requested to issue the INT9 instruction.
When the corresponding interrupt bit is "0", nothing occurs, even if they match.
Figure 22.2-1 Program Address Detection Registers (PADR0 and PADR1)
Program address detection registers
PADR0 1FF2H/1FF1H/1FF0H
PADR1 1FF5H/1FF4H/1FF3H
byte
byte
byte
Access
Initial value
R/W
R/W
Not defined
Not defined
Table 22.2-1 lists the correspondence between the program address detection registers
(PADR0 and PADR1) and PACSR.
Table 22.2-1 Correspondence between PADR0 and PADR1 Registers and PACSR
Address detection register
Interrupt enable bit
PADR0
AD0E
PADR1
AD1E
■ Program Address Detection Control Status Register (PACSR)
The program address detection control status register (PACSR) controls the operation of the
address detection function.
Figure 22.2-2 Program Address Detection Control Status Register (PACSR)
bit
7
6
5
4
3
Address: 009EH
Reserved Reserved Reserved Reserved AD1E
Read/write→ (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value→
(0)
(0)
(0)
(0)
(0)
2
1
0
Reserved
AD0E
(R/W)
(0)
Reserved
(R/W)
(0)
PACSR
(R/W)
(0)
[bit 7 to bit 4] Reserved bits
Bit 7 to bit 4 are reserved. Set these bits to "0" before setting PACSR.
[bit 3] AD1E (Address detect register 1 enable)
The AD1E bit is the operation enable bit of ASIE ADR1.
When this bit is 1, the address is compared with the PADR1 register. If they match, the INT9
instruction is issued.
355
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
[bit 2] Reserved bit
Bit 2 is reserved. Set this bit to "0" before setting PACSR.
[bit 1] AD0E (Address Detect register 0 Enable)
The AD0E bit is the operation enable bit of PADR0.
When this bit is "1", the address is compared with the PADR0 register. If they match, the
INT9 instruction is issued.
[bit 0] Reserved bit
Bit 0 is reserved. Set this bit to "0" before setting PACSR.
356
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
22.3 Operation of the Address Match Detection Function
If the program counter specifies the same address as the address match detection
register, the INT9 instruction is executed. The address match detection function can
be achieved by processing the INT9 instruction routine.
■ Operation of the Address Match Detection Function
There are two address detection registers with a compare enable bit. When the value set in the
address detection register and the value of the program counter match and the compare enable
bit is set to "1", the CPU executes the INT9 instruction.
Note:
If the value of the address detection register and the value of the program counter match, the
contents of internal data bus is changed to 01H. Consequently, the INT9 instruction is executed.
Before changing the contents of the address detection register, always set the compare enable bit
to "0". While the compare enable bit is set to "1", changing the contents of the address detection
register may result in a malfunction.
357
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
22.4 Example of the Address Match Detection Function
Figure 22.4-1 shows a system configuration example of the address match detection
function. Table 22.4-1 lists the E2PROM memory map.
■ System Configuration Example of the Address Match Detection Function
Figure 22.4-1 System Configuration Example of the Address Match Detection Function
E2PROM
MCU
F2MC-16LX
Pull-up resistor
SIN
Connector (UART)
Table 22.4-1 E2PROM Memory Map
Address
Description
0000H
Number of bytes of patch program No.0 (If "0", no
program error exists.)
0001H
Program address No.0 bit 7 to bit 0
0002H
Program address No.0 bit 15 to bit 8
0003H
Program address No.0 bit 24 to bit 16
0004H
Number of bytes of patch program No.1 (If "0", no
program error exists.)
0005H
Program address No.1 bit 7 to bit 0
0006H
Program address No.1 bit 15 to bit 8
0007H
Program address No.1 bit 24 to bit 16
0010H or higher
Main body of patch program No. 0/1
❍ Initial status
E2PROM is set to all 0s.
❍ When a program error occurs:
The main body of the patch program and program address are transferred to the MCU through
the connector (UART). The MCU writes the information to E2PROM.
358
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
❍ Reset sequence
The MCU reads the value of E2PROM after reset. If the number of bytes of the patch program is
not "0", the main body of the patch program is read from E2PROM and written to RAM. The
MCU then uses either PADR0 or PADR1 to set the patch address and sets the compare enable
bit. If the relocatable patch program is required, the first address of the patched program can be
written to the RAM area. In this case, the INT9 routine accesses this user-defined RAM area
and jumps to the patched program.
❍ INT9 interrupt
The interrupt routine can know the address where the interrupt occurs by checking the value of
the stack program counter. The information that has been placed on the stack during the
interrupt is discarded.
■ Example of Program Patch Processing
Figure 22.4-2 Example of program patch processing
FFFFFFH
Abnormal program
PC = address in error
ROM
External E2PROM
Register set for
program patch
Number of program bytes
Address where the interrupt occurs
Corrected program
Data transfer using UART
Corrected program
RAM
000000H
359
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
Figure 22.4-3 Flow of Program Patch Processing
Reset
Read 0000H of E2PROM
INT9
YES
0000H(E2PROM)=0
To patch program
JMP 000400H
NO
Read address
0001H to 0003H (E2PROM)
MOV
PADR0 (MCU)
Execute patch program
000400H to 000480H
Read patch program
0010H to 0090H (E2PROM)
MOV
000400H to 000480H (MCU)
Terminate patch program
JMP FF0050H
Enable compare
MOV PACSR, #02H
Execute normal program
NO
PC=PADR0
YES
INT9
FFFFFFH
FF0050H
ROM
E2PROM
Abnormal program
FF0000H
FFFFH
FE0000H
0090H
Patch program
0010H
001100H
Stack area
0003H
0002H
0001H
0000H
360
Program address
low-order:
Program address
middle-order:
Program address
high-order:
Number of bytes of
the patch program:
RAM area
00
00
000480H
Patch program
RAM
000400H
RAM and register area
FF
000100H
I/O area
80
000000H
CHAPTER 23
ROM MIRRORING MODULE
This chapter explains the ROM mirroring module.
23.1 Outline of ROM Mirroring Module
23.2 ROM Mirroring Register (ROMM)
361
CHAPTER 23 ROM MIRRORING MODULE
23.1 Outline of ROM Mirroring Module
The ROM Mirroring module switches whether to mirror the image of the FF bank of the
ROM to the 00 bank.
■ Block Diagram of ROM Mirroring Module
Figure 23.1-1 Block Diagram of ROM Mirroring Module
F2MC-16LX bus
ROM Mirroring Register
Address Area
FF bank
00 bank
ROM
362
CHAPTER 23 ROM MIRRORING MODULE
23.2 ROM Mirroring Register (ROMM)
Do not access the ROM mirroring register (ROMM) when addresses 004000H to
00FFFFH are being accessed.
■ ROM Mirroring Register (ROMM)
Figure 23.2-1 ROM Mirroring Register (ROMM)
bit
Address: 0006FH
Read/write→
Initial value→
15
14
13
12
11
10
9
8
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
MI
(W)
(1)
ROMM
[bit 8]: MI
The image of the ROM data in the FF bank can also be found in the 00 bank when "1" is
written to this bit. However, this memory mapping will not be done when this bit is written to
"0". This bit is write only.
Note:
Only addresses FF4000 to FFFFFF is mirrored to 004000 to 00FFFF when ROM mirroring function
is activated. Therefore, addresses FF0000 to FF3FFF will not be mirrored to 00 bank.
363
CHAPTER 23 ROM MIRRORING MODULE
364
CHAPTER 24
2M/3M-BIT FLASH MEMORY
This chapter explains the functions and operation of the 2M/3M-bit flash memory. The
following three methods are available for writing data to and erasing data from the
flash memory:
• Parallel programmer
• Serial dedicated programmer
• Executing programs to write/erase data
This chapter explains "Executing programs to write/erase data".
24.1 Overview of 2M/3M-bit Flash Memory
24.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the
Flash Memory
24.3 Write/Erase Modes
24.4 Flash Memory Control Status Register (FMCS)
24.5 Starting the Flash Memory Automatic Algorithm
24.6 Confirming the Automatic Algorithm Execution State
24.7 Detailed Explanation of Writing to and Erasing Flash Memory
24.8 Notes on using 2M-bit Flash Memory
24.9 Reset Vector Address in Flash Memory
24.10 Example of Programming 2M-bit Flash Memory
365
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.1 Overview of 2M/3M-bit Flash Memory
The 2M/3M-bit flash memory is mapped to the FC to FF bank in the CPU memory map.
The functions of the flash memory interface circuit enable read-access and programaccess from the CPU in the same way as mask ROM. Instructions from the CPU can be
used via the flash memory interface circuit to write data to and erase data from the
flash memory. Internal CPU control therefore enables rewriting of the flash memory
while it is mounted. As a result, improvements in programs and data can be performed
efficiently.
■ 2M/3M-bit Flash Memory Features
•
Use of automatic program algorithm (Embedded Algorithm: Equivalent to MBM29LV200)
•
Erase pause/restart functions provided
•
Detection of completion of writing/erasing using data polling or toggle bit functions
•
Detection of completion of writing/erasing using CPU interrupts
•
Sector erase function (any combination of sectors)
•
Minimum of 10000 write/erase operations
•
Flash memory read cycle time (minimum): 2 machine cycles
Embedded Algorithm is a trademark of Advanced Micro Devices, Inc.
Note:
The manufacturer code and device code do not have the reading function. These codes cannot be
accessed by the command.
■ Writing to/Erasing Flash Memory
The flash memory cannot be written to and read at the same time. That is, when data is written
to or erased data from the flash memory, the program in the flash memory must first be copied
to RAM. The entire process is then executed in RAM so that data is simply written to the flash
memory. This eliminates the need for the program to access the flash memory from the flash
memory itself.
366
CHAPTER 24 2M/3M-BIT FLASH MEMORY
■ Flash Memory Register
❍ Flash Memory Control Status Register (FMCS)
Figure 24.1-1 Flash Memory Control Status Register (FMCS)
bit
Address: 0000AEH
7
5
4
3
2
1
0
WE
RDY
Reserved
LPM1
Reserved
LPM0
(R/W)
(R/W)
(R)
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(X)
(0)
(0)
(0)
(0)
INTE RDYINT
Read/write→ (R/W)
Initial value→
6
(0)
FMCS
367
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.2 Block Diagram of the Entire Flash Memory and Sector
Configuration of the Flash Memory
Figure 24.2-1 shows a block diagram of the entire flash memory with the flash memory
interface circuit included. Figure 24.2-2 shows the sector configuration of the flash
memory.
■ Block Diagram of the Entire Flash Memory
Figure 24.2-1 Block Diagram of the Entire Flash Memory
Flash memory
interface circuit
2Mbit/3Mbit
Flash memory
BYTE
Port 2
Port 3
Port 4
F2MC-16LX
bus
INT
BYTE
CE
CE
OE
OE
WE
WE
AQ0 to AQ18
AQ0 to AQ17
AQ-1
DQ0 to DQ15
DQ0 to DQ15
RY/BY
RY/BY
RESET
Write enable interrupt signal
(to CPU)
External reset signal
RY/BY write
enable signal
■ Sector Configuration of the 2M/3M-bit Flash Memory
Figure 24.2-2 shows the sector configuration of the 2M/3M-bit flash memory. The addresses in
the figure indicate the high-order and low-order addresses of each sector.
368
CHAPTER 24 2M/3M-BIT FLASH MEMORY
Figure 24.2-2 Sector Configuration of the 2M/3M-bit Flash Memory
MB90F594A/MB90F594G (2M-bit flash memory)
Programmer address*
SA6 (16 Kbytes)
SA5 (8 Kbytes)
SA4 (8 Kbytes)
SA3 (32 Kbytes)
SA2 (64 Kbytes)
MB90F591A/MB90F591G (3M-bit flash memory)
Programmer address*
CPU address
7FFFFH
FFFFFFH
7BFFFH
FFBFFFH
79FFFH
FF9FFFH
77FFFH
FF7FFFH
6FFFFH
FEFFFFH
5FFFFH
FDFFFFH
SA1 (64 Kbytes)
SA11 (16 Kbytes)
SA10 (8 Kbytes)
SA8 (8 Kbytes)
SA8 (32 Kbytes)
SA7 (64 Kbytes)
CPU address
7FFFFH
FFFFFFH
7BFFFH
FFBFFFH
79FFFH
FF9FFFH
77FFFH
FF7FFFH
6FFFFH
FEFFFFH
5FFFFH
FDFFFFH
4FFFFH
FCFFFFH
3FFFFH
FBFFFFH
3BFFFH
FBBFFFH
39FFFH
FB9FFFH
37FFFH
FB7FFFH
2FFFFH
FAFFFFH
1FFFFH
F9FFFFH
0FFFFH
F8FFFFH
00000H
F80000H
SA6 (64 Kbytes)
4FFFFH
FCFFFFH
SA0 (64 Kbytes)
Unused
40000H
FC0000H
SA5 (16 Kbytes)
SA4 (8 Kbytes)
SA3 (8 Kbytes)
SA2 (32 Kbytes)
SA1(64 Kbytes)
SA0 (64 Kbytes)
Unused
*: The programmer address is equivalent to the CPU address when data is written to the flash memory
using a parallel programmer. When a general programmer is used for writing/erasing, this address
is used for writing/erasing.
369
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.3 Write/Erase Modes
The flash memory can be accessed in two different ways: Flash memory mode and
alternative mode. Flash memory mode enables data to be directly written to or erased
from the external pins. Alternative mode enables data to be written to or erased from
the CPU via the internal bus. Use the mode external pins to select the mode.
■ Flash Memory Mode
The CPU stops when the mode pins are set to 111 while the reset signal is asserted. The flash
memory interface circuit is connected directly to ports 0, 2, 3, and 4, enabling direct control from
the external pins. This mode makes the MCU seem like a standard flash memory to the external
pins, and write/erase can be performed using a flash memory programmer.
In flash memory mode, all operations supported by the flash memory automatic algorithm can
be used.
■ Alternative Mode
The flash memory is located in the FC (F9) to FF banks in the CPU memory space, and like
ordinary mask ROM, can be read-accessed and program-accessed from the CPU via the flash
memory interface circuit.
Since writing/erasing the flash memory is performed by instructions from the CPU via the flash
memory interface circuit, this mode allows rewriting even when the MCU is soldered on the
target board.
Sector protect operations cannot be performed in these modes.
■ Flash Memory Control Signals
Table 24.3-1 lists the flash memory control signals in flash memory mode.
There is almost a one-to-one correspondence between the flash memory control signals and the
external pins of the MBM29LV200. The VID (12 V) pins required by the sector protect operations
are MD0, MD1, and MD2 instead of A9, RESET, and OE for the MBM29LV200.
In flash memory mode, the external data bus signal width is limited to 8 bits, enabling only onebyte access. The DQ15 to DQ8 pins are not supported. The BYTE pin should always be set to
"0".
370
CHAPTER 24 2M/3M-BIT FLASH MEMORY
Table 24.3-1 Flash Memory Control Signals
MB90F594A/MB90F594G/MB90F591A/MB90F591G
MBM29LV200
Pin number
Normal function
Flash memory mode
1 to 8
P20 to P27
AQ0 to AQ7
A-1, A0 to A6
9
P30
AQ16
A15
10
P31
CE
CE
12
P32
OE
OE
13
P33
WE
WE
14 (15)
P34 (P35)
AQ17 (AQ18)
A16
16
P36
BYTE
BYTE
17
P37
RY/BY
RY/BY
18 to 22
P40 to P44
AQ8 to AQ12
A7 to A11
24 to 26
P45 to P47
AQ13 to AQ15
A12 to A14
49
MD0
MDO
A9 (VID)
50
MD1
MD1
RESET (VID)
51
MD2
MD2
OE (VID)
85 to 92
P00 to P07
DQ0 to DQ7
DQ0 to DQ7
77
RST
RESET
RESET
Not supported
DQ8 to DQ15
371
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.4 Flash Memory Control Status Register (FMCS)
The flash memory control status register (FMCS), together with the flash memory
interface circuit, is used to write data to and erase data from the flash memory.
■ Flash Memory Control Status Register (FMCS)
Figure 24.4-1 Flash Memory Control Status Register (FMCS)
bit
7
6
5
Address: 0000AEH
INTE RDYINT WE
Read/write→ (R/W) (R/W) (R/W)
Initial value→
(0)
(0)
(0)
4
3
2
1
0
RDY
(R)
(X)
Reserved
LPM1
(R/W)
(0)
Reserved
LPM0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
FMCS
❍ Explanation of bits
[bit 7] INTE (interrupt enable)
This bit generates an interrupt to the CPU when flash memory write/erase terminates.
An interrupt to the CPU is generated when the INTE and RDYINT bits are "1". No interrupt is
generated when the INTE bit is "0".
•
0: Disables interrupts when write/erase terminates.
•
1: Enables interrupts when write/erase terminates.
[bit 6] RDYINT (ready interrupt)
This bit indicates the operating state of the flash memory.
This bit is set to "1" when flash memory write/erase terminates. Data cannot be written to or
erased from the flash memory while this bit is "0" after a flash memory write/erase. Flash
memory write/erase is enabled when write/erase terminates and this bit is set to "1".
Writing "0" clears this bit to "0". Writing "1" is ignored. This bit is set to 1 at the termination
timing of the flash memory automatic algorithm (see Section "24.5 Starting the Flash
Memory Automatic Algorithm"). When the read-modify-write (RMW) instruction is used, "1" is
always read.
•
0: Write/erase is being executed.
•
1: Write/erase has terminated (interrupt request generated).
[bit 5] WE (write enable)
This bit enables writing to the flash memory area.
When this bit is "1", writing after the command sequence (see Section "24.5 Starting the
Flash Memory Automatic Algorithm") is issued to the FC (F9) to FF bank writes to the flash
memory area. When this bit is "0", the write/erase signal is not generated. This bit is used
when the flash memory Write/Erase command is activated.
If write/erase is not performed, it is recommended that this bit be set to "0" to prevent data
from being mistakenly written to the flash memory.
372
•
0: Disables flash memory write/erase.
•
1: Enables flash memory write/erase.
CHAPTER 24 2M/3M-BIT FLASH MEMORY
[bit 4] RDY (ready)
This bit enables flash memory write/erase.
Flash memory write/erase is disabled while this bit is "0". However, Suspend commands,
such as the Read/Reset command and Sector Erase command, can be accepted even if this
bit is "0".
•
0: Write/erase is being executed.
•
1: Write/erase has terminated (next data write/erase enabled).
[bit 3, bit 1] Reserved bits
These bits are reserved for testing. During regular use, they should always be set to "0".
[bit 2, bit 0] LPM1 and LPM0 (low power mode)
These bits control the current consumed by the flash memory when the flash memory is
accessed. Since the access time to the flash memory from the CPU is largely dependent on
this setting, select a setting value based on the operating frequency of the CPU.
•
01: Low power consumption mode (Operates at an internal operating frequency up to 4
MHz.)
•
10: Low power consumption mode (Operates at an internal operating frequency up to 8
MHz.)
•
11: Low power consumption mode (Operates at an internal operating frequency up to 10
MHz.)
•
00: Regular power consumption mode (Operates at an internal operating frequency up to 16
MHz.)
For the MB90F591A and the MB90F591G, these bits must be set to "00". For settings other
than "00", there will be no access to the Flash Memory.
Note:
The RDYINT and RDY bits cannot be changed at the same time. Make a program so that decisions
are made using one or the other of these bits.
Automatic algorithm
Termination timing
RDYINT bit
RDY bit
1 machine cycle
373
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.5 Starting the Flash Memory Automatic Algorithm
Four types of commands are available for starting the flash memory automatic
algorithm: Read/Reset, Write, Sector Erase and Chip Erase. Control of suspend and
restart is enabled for sector erase.
■ Command Sequence Table
Table 24.5-1 lists the commands used for flash memory write/erase. All of the data written to the
command register is in bytes, but use word access to write. The data of the high-order bytes at
this time is ignored.
Table 24.5-1 Command Sequence Table
Command
sequence
Bus
write
access
1st bus write
cycle
2nd bus write
cycle
3rd bus write
cycle
4th bus write
cycle
5th bus write
cycle
6th bus write
cycle
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Read/Reset *
1
FxXXXX
XXF0
-
-
-
-
-
-
-
-
-
-
Read/Reset *
4
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XXF0
RA
RD
-
-
-
-
Write
program
4
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XXA0
PA
(even)
PD
(word)
-
-
-
-
Chip Erase
6
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX80
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX10
Sector Erase
6
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX80
FxAAAA
XXAA
Fx5554
XX55
SA
(even)
XX30
Sector Erase Suspend
Sector Erase Restart
Auto-select
3
FxAAAA
Entering address FxXXXX data (xxB0H) suspends erasing during sector erase.
Entering address FxXXXX data (xx30H) restarts erasing after erasing is suspended during sector erase.
XXAA
Fx5554
XX55
FxAAAA
XX90
-
-
-
-
-
-
*: Both of the two types of Read/Reset commands can reset the flash memory to read mode.
Notes:
374
•
The addresses Fx in the table mean FF, FE, FD, and FC for 2M-bit Flash Memory and FF,
FE, FD, FB, FA and F9 for 3M-bit Flash Memory. Use these addresses as the access target
bank values for operations.
•
The addresses in the table are the values in the CPU memory map. All addresses and data
are represented using hexadecimal notation. However, the letter X is an optional value.
•
RA: Read address
•
PA: Write address. Only even addresses can be specified.
•
SA: Sector address. See Section "24.2 Block Diagram of the Entire Flash Memory and
Sector Configuration of the Flash Memory".
•
RD: Read data
•
PD: Write data. Only word data can be specified.
CHAPTER 24 2M/3M-BIT FLASH MEMORY
The Auto-select command shown in Table 24.5-1 is used to know the state of sector protection.
When using the Auto-select command, set the address as follows.
Table 24.5-2 Address Setting at Auto-select
Sector protection
AQ13 to AQ17 (AQ18)
AQ7
AQ2
AQ1
AQ0
DQ7 to DQ0
Sector Address
L
H
L
L
CODE*
*: When the sector address is protected, the output is "01H".
When the sector address is not protected, the output is "00H".
375
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.6 Confirming the Automatic Algorithm Execution State
Because the write/erase flow of the flash memory is controlled using the automatic
algorithm, the flash memory has hardware for posting its internal operating state and
completion of operation. This automatic algorithm enables confirmation of the
operating state of the built-in flash memory using the following hardware sequence
flags.
■ Hardware Sequence Flags
The hardware sequence flags are configured from the five-bit output of DQ7, DQ6, DQ5, DQ3
and DQ2. The functions of these bits are those of the data polling flag (DQ7), toggle bit flag
(DQ6), timing limit exceeded flag (DQ5), sector erase timer flag (DQ3) and toggle bit-2 flag
(DQ2). The hardware sequence flags can therefore be used to confirm that writing or chip sector
erase has been completed or that erase code write is valid.
The hardware sequence flags can be accessed by read-accessing the addresses of the target
sectors in the flash memory after setting of the command sequence (see Table 24.5-1 in
Section "24.5 Starting the Flash Memory Automatic Algorithm". Table 24.6-1 lists the bit
assignments of the hardware sequence flags.
Table 24.6-1 Bit Assignments of Hardware Sequence Flags
bit
7
6
5
4
3
2
1
0
Hardware sequence flag
DQ7
DQ6
DQ5
-
DQ3
DQ2
-
-
To determine whether automatic writing or chip sector erase is being executed, the hardware
sequence flags can be checked or the status can be determined from the RDY bit of the flash
memory control register (FMCS) that indicates whether writing has been completed. After
writing/erasing has terminated, the state returns to the read/reset state. When making a
program, use one of the flags to confirm that automatic writing/erasing has terminated. Then,
perform the next processing operation, such as data read. In addition, the hardware sequence
flags can be used to confirm whether the second or subsequent sector erase code write is valid.
The following sections describe each hardware sequence flag separately. Table 24.6-2 lists the
functions of the hardware sequence flags.
376
CHAPTER 24 2M/3M-BIT FLASH MEMORY
Table 24.6-2 Hardware Sequence Flag Functions
State
Write --> Write completed (write
address specified)
Chip/sector erase --> Erase
completed
State
change for
normal
operation
Abnormal
operation
DQ7
DQ7 -->
DATA:7
DQ6
Toggle -->
DATA:6
DQ5
DQ3
DQ2
0 -->
DATA:5
0 -->
DATA:3
1 -->
DATA:2
0 --> 1
Toggle -->
Stop
0 --> 1
1
Toggle -->
Stop
Sector erase wait --> Erase started
0
Toggle
0
0 --> 1
Toggle
Erase --> Sector erase suspended
(sector being erased)
0 --> 1
Toggle -->
1
0
1 --> 0
Toggle
Sector erase suspend --> Erase
restarted (sector being erased)
1 --> 0
1 -->
Toggle
0
0 --> 1
Toggle
Sector erase suspended (sector not
being erased)
DATA:7
DATA:6
DATA:5
DATA:3
DATA:2
DQ7
Toggle
1
0
1
0
Toggle
1
1
*
Write
Chip/sector erase
*: If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2 to
toggle. DQ2 does not toggle when the successive reads are executed to other sectors.
377
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.6.1 Data Polling Flag (DQ7)
The data polling flag (DQ7) uses the data polling function to post that the automatic
algorithm is being executed or has terminated
■ Data Polling Flag (DQ7)
Table 24.6-3 and Table 24.6-4 list the state transitions of the data polling flag.
Table 24.6-3 Data Polling Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
Chip/sector
erase -->
Completed
DQ7
DQ7 -->
0 --> 1
Sector
erase wait
--> Started
Sector erase
--> Erase
suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
0
0 --> 1
1 --> 0
DATA:7
Table 24.6-4 Data Polling Flag State Transitions (State Change for Abnormal Operation)
Operating
state
Write
operation
Chip/sector
erase
operation
DQ7
DQ7
0
❍ Write operation
Read-access during execution of the automatic write algorithm causes the flash memory to
output the inverted data of bit 7 last written, regardless of the value at the address specified by
the address signal. Read-access at the end of the automatic write algorithm causes the flash
memory to output bit 7 of the read value of the address specified by the address signal.
❍ Chip/sector erase operation
For a sector erase, read-access during execution of the chip erase/sector erase algorithm
causes the flash memory to output "0" from the sector currently being erased. For a chip erase,
read-access causes the flash memory to output "0" regardless of the value at the address
specified by the address signal. Read-access at the end of the automatic write algorithm causes
the flash memory to output "1" in the same way.
❍ Sector erase suspend operation
Read-access during a sector erase suspend causes the flash memory to output "1" if the
address specified by the address signal belongs to the sector being erased. The flash memory
outputs bit 7 (DATA: 7) of the read value at the address specified by the address signal if the
address specified by the address signal does not belong to the sector being erased.
Referencing this flag together with the toggle bit flag (DQ6) enables a decision to be made on
whether the flash memory is in the erase suspended state and which sector is being erased.
378
CHAPTER 24 2M/3M-BIT FLASH MEMORY
Note:
When the automatic algorithm is being activated, read-access to the specified address is ignored.
Since termination of the data polling flag (DQ7) can be accepted for a data read and other bits
output, data read after the automatic algorithm has terminated should be performed after readaccess has confirmed that data polling has terminated.
379
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.6.2 Toggle Bit Flag (DQ6)
Like the data polling flag, the toggle bit flag (DQ6) uses the toggle bit function to post
that the automatic algorithm is being executed or has terminated.
■ Toggle Bit Flag (DQ6)
Table 24.6-5 and Table 24.6-6 list the state transitions of the toggle bit flag.
Table 24.6-5 Toggle Bit Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
Chip/sector
erase -->
Completed
DQ6
Toggle -->
DATA:6
Toggle -->
Stop
Sector
erase wait
--> Started
Sector erase
--> Erase
suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
Toggle
Toggle --> 1
1 --> Toggle
DATA:6
Table 24.6-6 Toggle Bit Flag State Transitions (State Change for Abnormal Operation)
Operating
state
Write
operation
Chip/sector
erase
operation
DQ6
Toggle
Toggle
❍ Write/chip sector erase operation
Continuous read-access during execution of the automatic write algorithm and chip/sector erase
algorithm causes the flash memory to toggle the 1 or 0 state for every read cycle, regardless of
the value at the address specified by the address signal. Continuous read-access at the end of
the automatic write algorithm and chip/sector erase algorithm causes the flash memory to stop
toggling bit 6 and output bit 6 (DATA: 6) of the read value of the address specified by the
address signal.
❍ Sector erase suspend operation
Read-access during a sector erase suspend causes the flash memory to output "1" if the
address specified by the address signal belongs to the sector being erased. The flash memory
outputs bit 6 (DATA: 6) of the read value at the address specified by the address signal if the
address specified by the address signal does not belong to the sector being erased.
Note:
For a write, if the sector where data is to be written is rewrite-protected, the toggle bit terminates
the toggle operation after approximately 2µs without any data being rewritten. For an erase, if all of
the selected sectors are write-protected, the toggle bit performs toggling for approximately 100µs
and then returns to the read/reset state without any data being rewritten.
380
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.6.3 Timing Limit Exceeded Flag (DQ5)
The timing limit exceeded flag (DQ5) is used to post that execution of the automatic
algorithm has exceeded the time (internal pulse count) prescribed in the flash memory.
■ Timing Limit Exceeded Flag (DQ5)
Table 24.6-7 and Table 24.6-8 list the state transitions of the timing limit exceeded flag.
Table 24.6-7 Timing Limit Exceeded Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
Chip/sector
erase -->
Completed
DQ5
0 -->
DATA:5
0 --> 1
Sector
erase wait
--> Started
Sector erase
--> Erase
suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
0
0
0
DATA:5
Table 24.6-8 Timing Limit Exceeded Bit Flag State Transitions
(State Change for Abnormal Operation)
Operating
state
Write
operation
Chip/sector
erase
operation
DQ5
1
1
❍ Write/chip sector erase operation
Read-access after write or chip/sector erase automatic algorithm activation causes the flash
memory to output "0" if the time is within the prescribed time (time required for write/erase) or to
output "1" if the prescribed time has been exceeded. Because this is done regardless of
whether the automatic algorithm is being executed or has terminated, it is possible to determine
whether write/erase was successful or unsuccessful. That is, when this flag outputs "1", writing
can be determined to have been unsuccessful if the automatic algorithm is still being executed
by the data polling function or toggle bit function.
For example, writing "1" to a flash memory address where 0 has been written will cause the fail
state to occur. In this case, the flash memory will lock and execution of the automatic algorithm
will not terminate. In rare cases normal termination may be seen as with the case where "1" can
be written. As a result, valid data will not be output from the data polling flag (DQ7). In addition,
the toggle bit flag (DQ6) will exceed the time limit without stopping the toggle operation and the
timing limit exceeded flag (DQ5) will output "1". Note that this state indicates that the flash
memory is not faulty, but has been used correctly. When this state occurs, execute the Reset
command.
381
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.6.4 Sector Erase Timer Flag (DQ3)
The sector erase timer flag (DQ3) is used to post whether the automatic algorithm is
being executed during the sector erase wait period after the Sector Erase command
has been started.
■ Sector Erase Timer Flag (DQ3)
Table 24.6-9 and Table 24.6-10 list the state transitions of the sector erase timer flag.
Table 24.6-9 Sector Erase Timer Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
Chip/sector
erase -->
Completed
DQ3
0 -->
DATA:3
1
Sector
erase wait
--> Started
Sector erase
--> Erase
suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
0 --> 1
1 --> 0
0 --> 1
DATA:3
Table 24.6-10 Sector Erase Timer Flag State Transitions
(State Change for Abnormal Operation)
Operating
state
Write
operation
Chip/sector
erase
operation
DQ3
0
1
❍ Sector erase operation
Read-access after the Sector Erase command has been started causes the flash memory to
output "0" if the automatic algorithm is being executed during the sector erase wait period,
regardless of the value at the address specified by the address signal of the sector that issued
the command. The flash memory outputs "1" if the sector erase wait period has been exceeded.
If the data polling function or toggle bit function indicates that the erase algorithm is being
executed, internally controlled erase has already started if this flag is "1". Continuous write of
the sector erase codes or commands other than the Sector Erase Suspend command will be
ignored until erase is terminated.
If this flag is "0", the flash memory will accept write of additional sector erase codes. To confirm
this, it is recommended that the state of this flag be checked before continuing to write sector
erase codes. If this flag is "1" after the second state check, it is possible that additional sector
erase codes may not be accepted.
❍ Sector erase operation
Read-access during execution of sector erase suspend causes the flash memory to output "1" if
the address specified by the address signal belongs to the sector being erased. The flash
memory outputs bit 3 (DATA: 3) of the read value of the address specified by the address signal
if the address specified by the address signal does not belong to the sector being erased.
382
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.6.5 Toggle Bit-2 Flag (DQ2)
The toggle bit-2 flag (DQ2) is a flag that uses the toggle bit function to indicate that the
sector is in the erase-suspended state.
■ Toggle Bit-2 Flag (DQ2)
Table 24.6-11 and Table 24.6-12 list the state transitions of the toggle bit flag.
Table 24.6-11 Toggle Bit-2 Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
Chip/sector
erase -->
Completed
DQ2
1 -->
DATA:2
Toggle -->
Stop
Sector
erase wait
--> Started
Sector erase
--> Erase
suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
Toggle
Toggle
Toggle
DATA:2
Table 24.6-12 Toggle Bit-2 Flag State Transitions (State Change for Abnormal Operation)
Operating
state
Write
operation
Chip/sector
erase
operation
DQ2
1
*
*: If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2
to toggle. DQ2 does not toggle when the successive reads are executed from other sectors.
❍ During a sector erase operation
If successive reads are executed during the execution of the chip sector erase algorithm, a flash
memory toggles to output "1" and "0" to addresses alternately at every read access regardless
of the location indicated by the addresses. If successive reads are executed after the chip
sector erase algorithm is completed, the flash memory stops the toggle operation of the bit 2
and outputs the read value of the bit 2 (DATA: 2) to the location indicated by the address.
383
CHAPTER 24 2M/3M-BIT FLASH MEMORY
❍ While a sector erase operation is suspended
If successive reads are executed while a sector erase operation is suspended, and if the
address indicates the sector to be erased, the flash memory toggles to alternately output "1"
and "0". If the address indicates the sector is not to be erased, the flash memory outputs the
read value of the bit 2 (DATA: 2) to the location indicated by the address.
In the erase-suspend-program mode, successive reads from the non-erase suspended sector
causes the flash memory to output "1".
Both DQ2 and DQ6 are used for detecting an erase-suspended sector (DQ2 toggles, but DQ6
does not).
DQ2 is also used for detecting an erasing sector. While erasing a sector, if a read access is
executed from the erasing sector, DQ2 toggles.
Reference:
If all sectors selected for erasing are write-protected, the toggle bit-2 toggles for about 100µs, and
then returns to the read/reset mode without writing the data.
384
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.7 Detailed Explanation of Writing to and Erasing Flash
Memory
This section describes each operation procedure of flash memory Read/Reset, Write,
Chip Erase, Sector Erase, Sector Erase Suspend, and Sector Erase Restart when a
command that starts the automatic algorithm is issued.
■ Detailed Explanation of Flash Memory Write/Erase
The flash memory executes the automatic algorithm by issuing a command sequence (see
Table 24.5-1 in Section "24.5 Starting the Flash Memory Automatic Algorithm") for a write cycle
to the bus to perform Read/Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, or
Sector Erase Restart operations. Each bus write cycle must be performed continuously. In
addition, whether the automatic algorithm has terminated can be determined using the data
polling or other function. At normal termination, the flash memory is returned to the read/reset
state.
Each operation of the flash memory is described in the following order:
•
Setting the read/reset state
•
Writing data
•
Erasing data (erasing all chips)
•
Erasing all data (erasing sectors)
•
Suspending sector erase
•
Restarting sector erase
385
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.7.1 Setting the Read/Reset State
This section describes the procedure for issuing the Read/Reset command to set the
flash memory to the read/reset state.
■ Setting the Flash Memory to the Read/Reset State
The flash memory can be set to the read/reset state by sending the Read/Reset command in
the command sequence table (see Table 24.5-1 in Section "24.5 Starting the Flash Memory
Automatic Algorithm") continuously to the target sector in the flash memory.
The Read/Reset command has two types of command sequences that execute the first and
third bus operations. However, there are no essential differences between these command
sequences.
The read/reset state is the initial state of the flash memory. When the power is turned on and
when a command terminates normally, the flash memory is set to the read/reset state. In the
read/reset state, other commands wait for input.
In the read/reset state, data is read by regular read-access. As with the mask ROM, program
access from the CPU is enabled. The Read/Reset command is not required to read data by a
regular read. The Read/Reset command is mainly used to initialize the automatic algorithm in
such cases as when a command does not terminate normally.
386
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.7.2 Writing Data
This section describes the procedure for issuing the Write command to write data to
the flash memory.
■ Writing Data to the Flash Memory
The data write automatic algorithm of the flash memory can be started by sending the Write
command in the command sequence table (see Table 24.5-1 in Section "24.5 Starting the
Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory.
When data write to the target address is completed in the fourth cycle, the automatic algorithm
and automatic write are started.
❍ Specifying addresses
Only even addresses can be specified as the write addresses specified in a write data cycle.
Odd addresses cannot be written correctly. That is, writing to even addresses must be done in
units of word data.
Writing can be done in any order of addresses or even if the sector boundary is exceeded.
However, the Write command writes only data of one word for each execution.
❍ Notes on writing data
Writing cannot return data "0" to data "1". When data "1" is written to data "0", the data polling
algorithm (DQ7) or toggle operation (DQ6) does not terminate and the flash memory elements
are determined to be faulty. If the time prescribed for writing is thus exceeded, the timing limit
exceeded flag (DQ5) is determined to be an error. Otherwise, the data is viewed as if dummy
data "1" had been written. However, when data is read in the read/reset state, the data remains
"0". Data "0" can be set to data "1" only by erase operations.
All commands are ignored during execution of the automatic write algorithm. If a hardware reset
is started during writing, the data of the written addresses will be guaranteed.
■ Writing to the Flash Memory
Figure 24.7-1 is an example of the procedure for writing to the flash memory. The hardware
sequence flags (see Section "24.6 Confirming the Automatic Algorithm Execution State") can
be used to determine the state of the automatic algorithm in the flash memory. Here, the data
polling flag (DQ7) is used to confirm that writing has terminated.
The data read to check the flag is read from the address written to last.
The data polling flag (DQ7) changes at the same time that the timing limit exceeded flag (DQ5)
changes. For example, even if the timing limit exceeded flag (DQ5) is "1", the data polling flag
bit (DQ7) must be rechecked.
Also for the toggle bit flag (DQ6), the toggle operation stops at the same time that the timing
limit exceeded flag bit (DQ5) changes to "1". The toggle bit flag (DQ6) must therefore be
rechecked.
387
CHAPTER 24 2M/3M-BIT FLASH MEMORY
Figure 24.7-1 Example of the Flash Memory Write Procedure
Start writing
FMCS: WE (bit 5)
Enable flash memory write
Write command sequence
(1) FxAAAA <-- XXAA
(2) Fx5554 <-- XX55
(3) FxAAAA <-- XXA0
(4) Write address <-- Write data
Read internal address
Data polling (DQ7)
Next address
Data
Data
0
Timing limit (DQ5)
1
Read internal address
Data
Data polling (DQ7)
Data
Write error
Final address
NO
YES
FMCS: WE (bit 5)
Disable flash memory write
Complete writing
388
Confirm with the hardware
sequence flags.
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.7.3 Erasing All Data (Erasing Chips)
This section describes the procedure for issuing the Chip Erase command to erase all
data in the flash memory.
■ Erasing all Data in the Flash Memory (Erasing Chips)
All data can be erased from the flash memory by sending the Chip Erase command in the
command sequence table (see Table 24.5-1 in Section "24.5 Starting the Flash Memory
Automatic Algorithm") continuously to the target sector in the flash memory.
The Chip Erase command is executed in six bus operations. When writing of the sixth cycle is
completed, the chip erase operation is started. For chip erase, the user need not write to the
flash memory before erasing. During execution of the automatic erase algorithm, the flash
memory writes "0" for verification before all of the cells are erased automatically.
389
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.7.4 Erasing Optional Data (Erasing Sectors)
This section describes the procedure for issuing the Sector Erase command to erase
optional data (erase sector) in the flash memory. Individual sectors can be erased.
Multiple sectors can also be specified at one time.
■ Erasing Optional Data (Erasing Sectors) in the Flash Memory
Optional sectors in the flash memory can be erased by sending the Sector Erase command in
the command sequence table (see Table 24.5-1 in Section "24.5 Starting the Flash Memory
Automatic Algorithm") continuously to the target sector in the flash memory.
❍ Specifying sectors
The Sector Erase command is executed in six bus operations. Sector erase wait of 50µs is
started by writing the sector erase code (30H) to an accessible even-numbered address in the
target sector in the sixth cycle. To erase multiple sectors, write the erase code (30H) to the
addresses in the target sectors after the above processing operation.
❍ Notes on specifying multiple sectors
Erase is started when the sector erase wait period of 50µs terminates after the final sector erase
code has been written. That is, to erase multiple sectors at one time, an erase code (sixth cycle
of the command sequence) must be written within 50µs of writing of the address of a sector and
the address of the next sector must be written within 50µs of writing of the previous erase code.
Otherwise, the address and erase code may not be accepted. The sector erase timer (hardware
sequence flag DQ3) can be used to check whether writing of the subsequent sector erase code
is valid. At this time, specify so that the address used for reading the sector erase timer
indicates the sector to be erased.
■ Erasing Sectors in the Flash Memory
The hardware sequence flags (see Section "24.6 Confirming the Automatic Algorithm Execution
State") can be used to determine the state of the automatic algorithm in the flash memory.
Figure 24.7-2 is an example of the procedure for erasing sectors in the flash memory. Here, the
toggle bit flag (DQ6) is used to confirm that erasing has terminated.
The data that is read to check the flag is read from the sector to be erased.
The toggle bit flag (DQ6) stops the toggle operation at the same time that the timing limit
exceeded flag (DQ5) is changed to "1". For example, even if the timing limit exceeded flag
(DQ5) is "1", the toggle bit flag (DQ6) must be rechecked.
The data polling flag (DQ7) also changes at the same time that the timing limit exceeded flag bit
(DQ5) changes. As a result, the data polling flag (DQ7) must be rechecked.
390
CHAPTER 24 2M/3M-BIT FLASH MEMORY
Figure 24.7-2 Example of the Flash Memory Sector Erase Procedure
Start erasing
FMCS: WE (bit 5)
Enable flash memory erase
Erase command sequence
(1) FxAAAA <-- XXAA
(2) Fx5554 <-- XX55
(3) FxAAAA <-- XX80
(4) FxAAAA <-- XXAA
(5) Fx5554 <-- XX55
(6) Enter code to erase sector
(30H)
YES
Another erase sector
NO
Read internal address 1
Next sector
Read internal address 2
NO
YES
Toggle bit (DQ6)
data 1(DQ6) = data 2(DQ6)
Sector Erase
Completed
Yes
No
0
Timing limit (DQ5)
1
Read internal address 1
Read internal address 2
NO
Toggle bit (DQ6)
data 1(DQ6) = data 2(DQ6)
YES
Erase error
Final sector
NO
YES
FMCS: WE (bit 5)
Disable flash memory erase
Confirm with the hardware
sequence flags.
Complete erasing
391
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.7.5 Suspending Sector Erase
This section describes the procedure for issuing the Sector Erase Suspend command
to suspend erasing of flash memory sectors. Data can be read from sectors that are
not being erased.
■ Suspending Erasing of Flash Memory Sectors
Erasing of flash memory sectors can be suspended by sending the Sector Erase Suspend
command in the command sequence table (see Table 24.5-1 in Section "24.5 Starting the
Flash Memory Automatic Algorithm") to the target sector in the flash memory.
The Sector Erase Suspend command suspends the sector erase operation being executed and
enables data to be read from sectors that are not being erased. In this state, only reading is
enabled; data cannot be written. This command is valid only during sector erase operations that
include the erase wait time. The command will be ignored during chip erase or write operations.
This command is implemented by writing the erase suspend code (B0H). At this time, specify an
optional address in the flash memory for the address. An Erase Suspend command issued
again during erasing of sectors will be ignored.
Entering the Sector Erase Suspend command during the sector erase wait period will
immediately terminate sector erase wait, suspend the erase operation, and set the erase stop
state. Entering the Erase Suspend command during the erase operation after the sector erase
wait period has terminated will set the erase suspend state after a maximum period of 20µs has
elapsed. Before issuing a sector erase suspend command, wait for 20µs after issuing the sector
erase command or sector erase resume command.
392
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.7.6 Restarting Sector Erase
This section describes the procedure for issuing the Sector Erase Restart command to
restart suspended erasing of flash memory sectors.
■ Restarting Erasing of Flash Memory Sectors
Suspended erasing of flash memory sectors can be restarted by sending the Sector Erase
Restart command in the command sequence table (see Table 24.5-1 in Section "24.5 Starting
the Flash Memory Automatic Algorithm") continuously to the target sector in the flash memory.
The Sector Erase Restart command is used to restart erasing of sectors from the sector erase
suspend state set using the Sector Erase Suspend command. The Sector Erase Restart
command is implemented by writing the erase restart code (30H). At this time, specify an
optional address in the flash memory area for the address.
If a Sector Erase Restart command is issued during sector erase, the command will be ignored.
393
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.8 Notes on using 2M-bit Flash Memory
This section contains notes on using 2M-bit flash memory.
■ Notes on using flash memory
❍ Input of a hardware reset (RST)
To input a hardware reset when the automatic algorithm has not been started and reading is in
progress, a minimum "L" level width of 500 ns must be maintained. In this case, a maximum of
500 ns is required until data can be read from the flash memory after a hardware reset has been
activated.
Similarly, to input a hardware reset when the automatic algorithm has been activated and writing
or erasing is in progress, a minimum "L" level width of 500 ns must be maintained. In this case,
20 µs are required until data can be read after the operation for initializing the flash memory has
terminated.
A hardware reset during writing the data being written to be undefined. The erasing sector might
become using prohibited by hardware-reset or turning off the power under erasing.
❍ Canceling of a software reset, watchdog timer reset, and hardware standby
When the flash memory is being written to or erased with CPU access and if reset conditions
occur while the automatic algorithm is active, the CPU may run out of control. This occurs
because these reset conditions cause the automatic algorithm to continue without initializing the
flash memory unit, possibly preventing the flash memory unit from entering the read state when
the CPU starts the sequence after the reset has been deasserted. These reset conditions must
be disabled during writing to or erasing of the flash memory.
❍ Program access to flash memory
When the automatic algorithm is operating, read access to the flash memory is disabled. With
the memory access mode of the CPU set to internal ROM mode, writing or erasing must be
started after the program area is switched to another area such as RAM. In this case, when
sectors (SA6/SA11) containing interrupt vectors are erased, writing or erasing interrupt
processing cannot be executed. For the same reason, all interrupt sources other than the flash
memory are disabled while the automatic algorithm is operating.
❍ Extended intelligent I/O service (EI2OS)
Because write and erase interrupts issued to the CPU from the flash memory interface circuit
cannot be accepted by the EI2OS, they should not be used.
❍ Applying VID
During power-ON, please start and end the VID supply for the sector protect operation.
394
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.9 Reset Vector Address in Flash Memory
The MB90F594A, MB90F594G, MB90F591A, and MB90F591G supports a hard-wired
reset vector.
When the addresses FFFFDCH to FFFFDFH are accessed for reading data in internal
vector mode, the values that have been determined by the hard-wired logic in advance
are read. However, in flash memory mode, as mentioned in the previous section, all
addresses can be accessed.
Consequently, it is meaningless to write data to these addresses. Especially when
programming flash memory from the CPU (that is, not in flash memory mode), do not
read these addresses for software polling. Otherwise, the flash memory returns a fixed
reset vector value instead of the hardware sequence flag value.
■ Reset Vector Address in Flash Memory
The following table shows the reset vector and mode data values determined in advance.
Reset vector
FFA000H
Mode data
00H
Note:
Because of the hard-wired reset vector, it is not necessary to specify the reset vector in the
software. However it is recommended to specify the same vector and the same mode data in the
program, this will prevent the Mask ROM device to behave differently from the Flash device when
the same program is used.
395
CHAPTER 24 2M/3M-BIT FLASH MEMORY
24.10 Example of Programming 2M-bit Flash Memory
This section presents a programming example of 2M-bit flash memory.
■ Programming Example of 2M-bit Flash Memory
NAME
FLASHWE
TITLE FLASHWE
;------------------------------------------------------------------------------;2M-bit-FLASH test program
;
;1: Transmits the program (address: FFBC00H, sector: SA6) from FLASH to RAM
;
(address: 001500H).
;2: Executes the program on RAM.
;3: Writes the PDR1 value to FLASH (address: FI0000H, sector: SA1).
;4: Reads the written value (address: FD0000H, sector: SA1) and outputs it to PDR2.
;5: Erases the written sector (SA1).
;6: Checks and outputs erase data.
;Conditions
; - Number of bytes transmitted to RAM: 100H (256B)
; - Write/erase termination judgment
;
Judgment according to DQ5 (timing limit excess flag)
;
Judgment according to DQ6 (toggle bit flag)
;
Judgment according to RDY (FMCS)
; - Error handling
;
Hi output to P00 to P07
;
Reset command issuance
;------------------------------------------------------------------;
RESOUS IOSEG
ABS=00
;"RESOUS" I/O segment definition
ORG
0000H
PDR0
RB
1
PDR1
RB
1
PDR2
RB
1
PDR3
RB
1
ORG
0010H
DDR0
RB
1
DDR1
RB
1
DDR2
RB
1
DDR3
RB
1
ORG
00A1H
CKSCR
RB
1
ORG
00AEH
FMCS
RB
1
ORG
006FH
ROMM
RB
1
RESOUS ENDS
;
SSTA
SSEG
RW
0127H
STA_T
RW
1
SSTA
ENDS
;
DATA
DSEG
ABS=0FFH
;FLASH command address
ORG
5554H
COMADR2 RW
1
ORG
0AAAAH
COMADR1 RW
1
DATA
ENDS
396
CHAPTER 24 2M/3M-BIT FLASH MEMORY
;/////////////////////////////////////////////////////////////
;Main program (FFA000H)
;/////////////////////////////////////////////////////////////
CODE
CSEG
START:
;
/////////////////////////////////////////////////////
;
Initialization
;
/////////////////////////////////////////////////////
MOV
CKSCR,#0BAH
;3-multiple setting
MOV
RP,#0
MOV
A,#!STA_T
MOV
SSB,A
MOVW
A,#STA_T
MOVW
SP,A
MOV
ROMM,#00H
;Mirror OFF
MOV
PDR0,#00H
;For error check
MOV
DDR0,#0FFH
MOV
PDR1,#00H
;Port for data input
MOV
DDR1,#00H
MOV
PDR2,#00H
;Port for data output
MOV
DDR2,#0FFH
;
//////////////////////////////////////////////////////////////
;
Transfer of "FLASH write erase program (FFBC00H)" to RAM (1500H address)
;
//////////////////////////////////////////////////////////////
MOVW
A,#1500H
;Transfer destination RAM area
MOVW
A,#0BC00H
;Transfer source address (program position)
MOVW
RW0,#100H
;Number of bytes to be transferred
MOVS
ADB,PCB
;Transfer of 100H from FFBC00H to 001500H
CALLP
001500H
;Jump to the address containing the transferred
;
program
;
/////////////////////////////////////////////////////
;
Data output
;
/////////////////////////////////////////////////////
OUT
MOV
A,#0FDH
MOV
ADB,A
MOVW
RW2,#0000H
MOVW
A,@RW2+00
MOV
PDR2,A
END
JMP
*
CODE
ENDS
;////////////////////////////////////////////////////////////
;FLASH write erase program (SA6)
;////////////////////////////////////////////////////////////
RAMPRG CSEG
ABS=0FFH
ORG
0BC00H
;
////////////////////////////////////////////
Initialization
;
////////////////////////////////////////////
MOVW
RW0,#0500H
;RW0:RAM space for input data acquisition
From 00:0500
MOVW
RW2,#0000H
;RW2:Flash memory write address
From FD:0000
MOV
A,#00H
;DTB modification
MOV
DTB,A
;Bank specification for @RW0
MOV
A,#0FDH
;ADB modification 1
MOV
ADB,A
;Bank specification for write mode specification
;
address
MOV
PDR3,#00H
;Switch initialization
MOV
DDR3,#00H
;
WAIT1
BBC
PDR3:0,WAIT1
;PDR3: 0(write start at "H" level)
;
;////////////////////////////////////////////////
;Write (SA1)
;////////////////////////////////////////////////
MOV
A,PDR1
MOVW
@RW0+00,A
;PDR1 data allocation to RAM
MOV
FMCS,#20H
;Write mode setting
MOVW
ADB:COMADR1,#00AAH
;Flash write command 1
397
CHAPTER 24 2M/3M-BIT FLASH MEMORY
MOVW
MOVW
ADB:COMADR2,#0055H
ADB:COMADR1,#00A0H
;Flash write command 2
;Flash write command 3
;
;
;
;
;
;
;
;
;
NTOW
;
;
;
MOVW
A,@RW0+00
;Input data (RW0) write to flash memory (RW2)
MOVW
@RW2+00,A
WRITE
;Wait time check
///////////////////////////////////////////////////////////////////
ERROR when the time limit excess check flag is set and toggle operation is
in progress
///////////////////////////////////////////////////////////////////
MOVW
A,@RW2+00
AND
A,#20H
;DQ5 time limit check
BZ
NTOW
;Time limit over
MOVW
A,@RW2+00
;AH
MOVW
A,@RW2+00
;AL
XORW
A
;XOR of AH and AL (1 when the values differ)
AND
A,#40H
;Is the DQ6 toggle bit different?
BNZ
ERROR
;To ERROR when the DQ6 toggle bit is different
///////////////////////////////////////
Write termination check (FMCS-RDY)
///////////////////////////////////////
///////////////////////////////////////
MOVW
A,FMCS
AND
A,#10H
;Extraction of FMCS RDY bit (bit 4)
BZ
WRITE
;End of write?
MOV
FMCS,#00H
;Write mode release
/////////////////////////////////////////////////////
Write data output
/////////////////////////////////////////////////////
MOVW
RW2,#0000H
;Write data output
MOVW
A,@RW2+00
MOV
PDR2,A
;
WAIT2
BBC
PDR3:1,WAIT2
;PDR3: 1(sector erase start at "H" level)
;
;/////////////////////////////////////////////
;Sector erase (SA1)
;/////////////////////////////////////////////
MOV
@RW2+00,#0000H
;Address initialization
MOV
FMCS,#20H
;Erase mode setting
MOVW
ADB:COMADR1,#00AAH
;Flash erase command 1
MOVW
ADB:COMADR2,#0055H
;Flash erase command 2
MOVW
ADB:COMADR1,#0080H
;Flash erase command 3
MOVW
ADB:COMADR1,#00AAH
;Flash erase command 4
MOVW
ADB:COMADR2,#0055H
;Flash erase command 5
MOV
@RW2+00,#0030H
;Issuance of erase command 6 to the sector
to be erased
ELS
;Wait time check
;
///////////////////////////////////////////////////////////////////
;
ERROR when the time limit excess check flag is set and toggle operation is
;
in progress
;
///////////////////////////////////////////////////////////////////
MOVW
A,@RW2+00
AND
A,#20H
;DQ5 time limit check
BZ
NTOE
;Time limit over
MOVW
A,@RW2+00
;AH "H" and "L" are alternately output from
MOVW
A,@RW2+00
;AL DQ6 per read during write operation.
XORW
A
;XOR of AH and AL (If the DQ6 value differs,
;
write operation is in progress (1)).
AND
A,#40H
;Is the DQ6 toggle bit "H"?
BNZ
ERROR
;ERROR when the DQ6 toggle bit is "H"
;
///////////////////////////////////////
;
Erase termination check (FMCS-RDY)
;
///////////////////////////////////////
NTOE
MOVW
A,FMCS
;
AND
A,#10H
;Extraction of FMCS RDY bit (bit 4)
BZ
ELS
;End of sector erase?
MOV
FMCS,#00H
;FLASH erase mode release
RETP
;Return to the main program
398
CHAPTER 24 2M/3M-BIT FLASH MEMORY
;//////////////////////////////////////////////
;Error
;//////////////////////////////////////////////
ERROR
MOV
ADB:COMADR1,#0F0H
;Reset command (read is enabled)
MOV
FMCS,#00H
;FLASH mode release
MOV
PDR0,#0FFH
;Error handling check
RETP
;Return to the main program
RAMPRG ENDS
;/////////////////////////////////////////////
VECT
CSEG
ABS=0FFH
ORG
0FFDCH
DSL
START
DB
00H
VECT
ENDS
;
399
CHAPTER 24 2M/3M-BIT FLASH MEMORY
400
CHAPTER 25
EXAMPLES OF MB90F594A/MB90F594G/
MB90F591A/MB90F591G SERIAL
PROGRAMMING CONNECTION
This chapter provides examples of the serial programming connection using AF220/
AF210/AF120/AF110 flash microcomputer programmer manufactured by Yokogawa
Digital Computer Corporation.
25.1 Basic Configuration of MB90F594A/MB90F594G/MB90F591A/
MB90F591G Serial Programming Connection
25.2 Example of Serial Programming Connection (User Power Supply Used)
25.3 Example of Serial Programming Connection (Power Supplied from the
Programmer)
25.4 Example of Minimum Connection to the Flash Microcomputer Programmer
(User Power Supply Used)
25.5 Example of Minimum Connection to the Flash Microcomputer Programmer
(Power Supplied from the Programmer)
401
CHAPTER 25 EXAMPLES OF MB90F594A/MB90F594G/MB90F591A/MB90F591G SERIAL PROGRAMMING CONNECTION
25.1 Basic Configuration of MB90F594A/MB90F594G/
MB90F591A/MB90F591G Serial Programming Connection
The MB90F594A/MB90F594G/MB90F591A/MB90F591G supports flash ROM serial
onboard programming (Fujitsu standard). This section describes the specifications.
■ Basic Configuration of MB90F594A/MB90F594G/MB90F591A/MB90F591G Serial Programming
Connection
The AF220/AF210/AF120/AF110 flash microcomputer programmer from Yokogawa Digital Computer
Corporation is used for Fujitsu standard serial onboard programming.
Figure 25.1-1 Basic Configuration of MB90F594A/MB90F594G/MB90F591A/MB90F591G
Serial Programming
Host interface cable (AZ201)
AF220/AF210/
AF120/AF110
flash
microcomputer
programmer
+
memory card
General-purpose
common cable (AZ210)
CLK synchronous serial
MB90F594A/
MB90F594G/
MB90F591A/
MB90F591G
user system
Stand-alone operation enabled
Note:
Ask the company representative from Yokogawa Digital Computer Corporation for details about the
functions and operations of the AF220/AF210/AF120/AF110 flash microcomputer programmer,
general-purpose common cable for connection (AZ210), and connectors.
Table 25.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming (1/2)
Pin
MD2, MD1
MD0
Function
Additional information
Mode pins
Controls programming mode from the flash microcomputer
programmer.
X0, X1
Oscillation pins
In programming mode, the CPU internal operation clock
signal is one multiple of the PLL clock signal frequency.
Therefore, the oscillation clock frequency becomes the
internal operation clock signal.
P00, P01
programming activation pins
Input a "L" level to P00 and "H" level to P01.
RST
Reset pin
SIN3
Serial data input pin
SOT3
Serial data output pin
SCK3
Serial clock signal input pin
402
-
Serial input-output is used.
CHAPTER 25 EXAMPLES OF MB90F594A/MB90F594G/MB90F591A/MB90F591G SERIAL PROGRAMMING CONNECTION
Table 25.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming (2/2)
Pin
Function
Additional information
C pin
This external capacitor pin is used to stabilize the power
supply. Connect a ceramic capacitor of approximately
0.1µF to the outside.
VCC
Power voltage supply pin
If the programming voltage (5 V ± 10%) is supplied from the
user system, the flash microcomputer programmer need
not be connected. Connect so that the power supply of the
user side is not short-circuited.
VSS
GND pin
Common to the ground of the flash microcomputer
programmer.
HST
Hardware standby pin
Input "H" level during serial programming mode.
C
Even if the P00, SIN3, SOT3, and SCK3 pins are used for the user system, the control circuit
shown in the figure below is required. The /TICS signal of the flash microcomputer programmer
can be used to disconnect the user circuit during serial programming.
Sections "25.2 Example of Serial Programming Connection (User Power Supply Used)" to
"25.5 Example of Minimum Connection to the Flash Microcomputer Programmer (Power
Supplied from the Programmer)" present examples the following four types of serial
programming connection. See each Section as required.
•
Serial programming connection (user power supply used)
•
Serial programming connection (power supplied from the programmer)
•
Minimum connection to the flash microcomputer programmer (user power supply used)
•
Minimum connection to the flash microcomputer programmer (power supplied from the
programmer)
Figure 25.1-2 Control Circuit
AF220/AF210/
AF120/AF110
write control pin
MB90F594A/MB90F594G/
MB90F591A/MB90F591G
write control pin
10 k
AF220/AF210/
AF120/AF110
/TICS pin
User
403
CHAPTER 25 EXAMPLES OF MB90F594A/MB90F594G/MB90F591A/MB90F591G SERIAL PROGRAMMING CONNECTION
Table 25.1-2 System Configuration of Flash Microcomputer Programmers (Manufactured
by Yokogawa Digital Computer Corporation)
Model
Function
AF220/AC4P
Ethernet interface built-in model and 100 to 220 V AC power
adapter
AF210/AC4P
Standard model and 100 to 220 V AC power adapter
AF120/AC4P
Single-key Ethernet interface built-in model and 100 to 220 V
AC power adapter
AF110/AC4P
Single-key model and 100 to 220 V AC power adapter
Main unit
AZ221
PC/AT RS232C cable for programmer
AZ210
Standard target probe (a) with a 1 m
FF201
Fujitsu F2MC-16LX flash microcomputer control module
AZ290
Remote controller
/P2
2 Mbytes PC card (optional) for flash memory sizes up to
128 Kbytes
/P4
4 Mbytes PC card (optional) for flash memory sizes up to
512 Kbytes
Inquiries: Yokogawa Digital Computer Corporation
Telephone number: (81)-42-333-6224
Note:
Although the AF200 flash microcomputer programmer is no longer manufactured, the programmer
still can be used in combination with the FF201 control module.
Examples of serial programming connection are given in Sections "25.2
Programming Connection (User Power Supply Used)" and the later sections.
404
Example of Serial
CHAPTER 25 EXAMPLES OF MB90F594A/MB90F594G/MB90F591A/MB90F591G SERIAL PROGRAMMING CONNECTION
■ Oscillating Clock Frequency and Serial Clock Input Frequency
The equation listed below can be used to calculate the serial clock frequencies that can be used
for the MB90F594A, MB90F594G, MB90F591A, and MB90F591G. Set an appropriate serial
clock input frequency in the flash microcomputer programmer according to the oscillating clock
frequency in use.
Serial clock frequency that can be used = 0.125 x oscillating clock frequency
Table 25.1-3 Examples of Serial Clock Frequencies that can be Used
Oscillating clock
frequency
Maximum serial clock
frequency that can be
used for
microcomputers
Maximum serial clock
frequency that can be
used for the AF220,
AF210, AF120, and
AF110
Maximum serial clock
frequency that can be
used for the AF200
4 MHz
500 kHz
500 kHz
500 kHz
8 MHz
1 MHz
850 kHz
500 kHz
16 MHz
2 MHz
1.25 MHz
500 kHz
405
CHAPTER 25 EXAMPLES OF MB90F594A/MB90F594G/MB90F591A/MB90F591G SERIAL PROGRAMMING CONNECTION
25.2 Example of Serial Programming Connection (User Power
Supply Used)
Figure 25.2-1 is an example of a serial programming connection when the user power
supply is used.
The value 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the
AF220/AF210/AF120/AF110 programmer.
Serial reprogramming mode: MD2, MD1, MD0 = 110.
■ Example of Serial Programming Connection (User Power Supply Used)
Figure 25.2-1 Example of Serial Programming Connection for MB90F594A/MB90F594G/MB90F591A/
MB90F591G (User Power Supply Used)
AF220/AF210/AF120/AF110
flash microcomputer
programmer
TAUX3
User system
MB90F594A /MB90F594G/
MB90F591A/MB90F591G
Connector
DX10-28S or DX20-28S
MD2
(19)
10 kΩ
10 kΩ
MD1
10 kΩ
TMODE
MD0
X0
(12)
X1
TAUX
P00
(23)
10 kΩ
/TICS
(10)
User
10 kΩ
User
HST
10 kΩ
/TRES
10 kΩ
RST
(5)
10 kΩ
User
0.1µF
TTXD
TRXD
TCK
(13)
(27)
(6)
TVcc
(2)
GND
(7, 8,
14,15,
21, 22
1, 28)
P01
C
SIN3
SOT3
SCK3
Vcc
User power
supply
Vss
Pin 14
Pins 3, 4, 9, 11, 16, 17, 18, 20,
24, 25, and 26 are open.
DX10-28S: Right-angle type
•
406
Pin 1
DX10-28S
Pin 28
Pin 15
Connector (Hirose Electronics Ltd.)
pin arrangement
Even if the SIN3, SOT3, and SCK3 pins are used for the user system, the control circuit
shown in the figure below is required in the same way that it is for P00. The /TICS signal of
CHAPTER 25 EXAMPLES OF MB90F594A/MB90F594G/MB90F591A/MB90F591G SERIAL PROGRAMMING CONNECTION
the flash microcomputer programmer can be used to disconnect the user circuit during serial
programming.
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
AF220/AF210/
AF120/AF110
write control pin
MB90F594A/MB90F594G/
MB90F591A/MB90F591G
write control pin
10 k
AF220/AF210/
AF120/AF110
/TICS pin
User
407
CHAPTER 25 EXAMPLES OF MB90F594A/MB90F594G/MB90F591A/MB90F591G SERIAL PROGRAMMING CONNECTION
25.3 Example of Serial Programming Connection (Power
Supplied from the Programmer)
Figure 25.3-1 is an example of a serial programming connection when power is
supplied from the programmer.
The value 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the
AF220/AF210/AF120/AF110 programmer.
Serial reprogramming mode: MD2, MD1, MD0 = 110.
■ Example of Serial Programming Connection (Power Supplied from the Programmer)
Figure 25.3-1 Example of Serial Programming Connection for MB90F594A/MB90F594G/MB90F591A/
MB90F591G (Power Supplied from the Programmer)
AF220/AF210/AF120/AF110 User system
flash microcomputer
Connector
programmer
DX10-28S
TAUX3
MB90F594A /MB90F594G/
MB90F591A/MB90F591G
MD2
(19)
10 kΩ
10 kΩ
MD1
10 kΩ
TMODE
MD0
X0
(12)
X1
TAUX
P00
(23)
10 kΩ
/TICS
(10)
User
10 kΩ
User
HST
10 kΩ
/TRES
10 kΩ
RST
(5)
10 kΩ
User
0.1µF
TTXD
TRXD
TCK
TVcc
Vcc
TVPP1
GND
(13)
(27)
(6)
(2)
(3)
(16)
(7, 8,
14,15,
21, 22
1, 28)
Pins 4, 9, 11, 17, 18, 20,
24, 25, and 26 are open.
P01
C
SIN3
SOT3
SCK3
Vcc
User power
supply
Vss
Pin 14
Pin 1
Pin 28
Pin 15
DX10-28S
DX10-28S: Right-angle type
Connector (Hirose Electronics Ltd.)
pin arrangement
•
408
Even if the SIN3, SOT3, and SCK3 pins are used for the user system, the control circuit
shown in the figure below is required in the same way that it is for P00. The /TICS signal of
the flash microcomputer programmer can be used to disconnect the user circuit during serial
CHAPTER 25 EXAMPLES OF MB90F594A/MB90F594G/MB90F591A/MB90F591G SERIAL PROGRAMMING CONNECTION
programming.
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
•
When the programming power is supplied from the AF220/AF210/AF120/AF110, be careful
not to short-circuit the user power supply.
AF220/AF210/
AF120/AF110
write control pin
MB90F594A/MB90F594G/
MB90F591A/MB90F591G
write control pin
10 k
AF220/AF210/
AF120/AF110
/TICS pin
User
409
CHAPTER 25 EXAMPLES OF MB90F594A/MB90F594G/MB90F591A/MB90F591G SERIAL PROGRAMMING CONNECTION
25.4 Example of Minimum Connection to the Flash
Microcomputer Programmer (User Power Supply Used)
Figure 25.4-1 is an example of the minimum connection to the flash microcomputer
programmer when the user power supply is used.
Serial reprogramming mode: MD2, MD1, MD0 = 110.
■ Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used)
For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcomputer
programmer need not be connected if the pins are set as described below.
Figure 25.4-1 Example of Minimum Connection to the Flash Microcomputer Programmer
(User Power Supply Used)
AF220/AF210/AF120/AF110 User system
flash microcomputer
programmer
1 for serial
reprogramming
10 kΩ
MB90F594A/MB90F594G/
MB90F591A/MB90F591G
MD2
1 for serial
reprogramming
10 kΩ
10 kΩ
MD1
10 kΩ
10 kΩ
MD0
0 for serial
reprogramming
10 kΩ
X0
X1
10 kΩ
0 for serial
reprogramming
P00
10 kΩ
User circuit
P01
1 for serial reprogramming
10 kΩ
(5)
(13)
(27)
(6)
(2)
GND
(7, 8,
14,15,
21, 22,
1, 28)
10 kΩ
RST
SIN3
SOT3
SCK3
Vcc
User power supply
Pins 3, 4, 9, 10, 11, 12, 16, 17, 18, 19,
20, 23, 24, 25, and 26 are open.
DX10-28S: Right-angle type
HST
C
0.1µF
Connector
DX10-28S
/TRES
TTXD
TRXD
TCK
TVcc
User
circuit
Vss
Pin 14
Pin 1
Pin 28
Pin 15
DX10-28S
Connector (Hirose Electronics Ltd.)
pin arrangement
•
410
Even if the SIN3, SOT3, and SCK3 pins are used for the user system, the control circuit
CHAPTER 25 EXAMPLES OF MB90F594A/MB90F594G/MB90F591A/MB90F591G SERIAL PROGRAMMING CONNECTION
shown in the figure below is required. The /TICS signal of the flash microcomputer
programmer can be used to disconnect the user circuit during serial programming.
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
AF220/AF210/
AF120/AF110
write control pin
MB90F594A/MB90F594G/
MB90F591A/MB90F591G
write control pin
10 k
AF220/AF210/
AF120/AF110
/TICS pin
User
411
CHAPTER 25 EXAMPLES OF MB90F594A/MB90F594G/MB90F591A/MB90F591G SERIAL PROGRAMMING CONNECTION
25.5 Example of Minimum Connection to the Flash
Microcomputer Programmer
(Power Supplied from the Programmer)
Figure 25.5-1 is an example of the minimum connection to the flash microcomputer
programmer when power is supplied from the Programmer.
Serial reprogramming mode: MD2, MD1, MD0 = 110.
■ Example of Minimum Connection to the Flash Microcomputer Programmer
(Power Supplied from the Programmer)
For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcomputer
programmer need not be connected if the pins are set as described below.
Figure 25.5-1 Example of Minimum Connection to the Flash Microcomputer Programmer
(Power Supplied from the Programmer)
AF220/AF210/AF120/AF110 User system
flash microcomputer
programmer
1 for serial
reprogramming
10 kΩ
MB90F594A/MB90F594G/
MB90F591A/MB90F591G
MD2
1 for serial
reprogramming
10 kΩ
10 kΩ
10 kΩ
10 kΩ
MD1
MD0
0 for serial
reprogramming
10 kΩ
X0
X1
P00
10 kΩ
0 for serial
reprogramming
10 kΩ
User circuit
P01
1 for serial reprogramming
10 kΩ
Connector
DX10-28S
/TRES
TTXD
TRXD
TCK
(5)
(13)
(27)
(6)
(2)
(3)
(16)
User
circuit
0.1µF
10 kΩ
RST
SIN3
SOT3
SCK3
Vcc
TVcc
GND
(7,8,
14,15,
21, 22,
1, 28)
Pins 4, 9, 10, 11, 12, 17, 18, 19,
20, 23, 24, 25, and 26 are open.
DX10-28S: Right-angle type
HST
C
Vss
Pin 14
Pin 1
Pin 28
Pin 15
DX10-28S
Connector (Hirose Electronics Ltd.)
pin arrangement
•
412
Even if the SIN3, SOT3, and SCK3 pins are used for the user system, the control circuit
shown in the figure below is required. The /TICS signal of the flash microcomputer
CHAPTER 25 EXAMPLES OF MB90F594A/MB90F594G/MB90F591A/MB90F591G SERIAL PROGRAMMING CONNECTION
programmer can be used to disconnect the user circuit during serial programming.
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
•
When the programming power is supplied from the AF220/AF210/AF120/AF110, be careful
not to short-circuit the user power supply.
AF220/AF210/
AF120/AF110
write control pin
MB90F594A/MB90F594G/
MB90F591A/MB90F591G
write control pin
10 k
AF220/AF210/
AF120/AF110
/TICS pin
User
413
CHAPTER 25 EXAMPLES OF MB90F594A/MB90F594G/MB90F591A/MB90F591G SERIAL PROGRAMMING CONNECTION
414
APPENDIX
The appendixes provide I/O maps and instructions of F2MC-16LX.
APPENDIX A I/O Maps
APPENDIX B Instructions
APPENDIX C Timing Diagrams in Flash Memory Mode
APPENDIX D List of MB90590 Series Interrupt Vectors
415
APPENDIX A I/O Maps
APPENDIX A I/O Maps
Table A-1 lists addresses to be assigned to the registers in the peripheral blocks.
■ I/O Maps
Table A-1 I/O Map (1/6)
Address
Register
Abbreviation
Access
Resource
Initial value
000000 H
Port Data Register (for port 0)
PDR0
R/W
Port 0
XXXXXXXXB
000001 H
Port Data Register (for port 1)
PDR1
R/W
Port 1
XXXXXXXXB
000002 H
Port Data Register (for port 2)
PDR2
R/W
Port 2
XXXXXXXXB
000003 H
Port Data Register (for port 3)
PDR3
R/W
Port 3
XXXXXXXXB
000004 H
Port Data Register (for port 4)
PDR4
R/W
Port 4
XXXXXXXXB
000005 H
Port Data Register (for port 5)
PDR5
R/W
Port 5
XXXXXXXXB
000006 H
Port Data Register (for port 6)
PDR6
R/W
Port 6
XXXXXXXXB
000007 H
Port Data Register (for port 7)
PDR7
R/W
Port 7
XXXXXXXXB
000008 H
Port Data Register (for port 8)
PDR8
R/W
Port 8
XXXXXXXXB
000009 H
Port Data Register (for port 9)
PDR9
R/W
Port 9
--XXXXXXB
00000A to
00000FH
Use prohibited
000010 H
Port Direction Register (for port 0)
DDR0
R/W
Port 0
00000000B
000011 H
Port Direction Register (for port 1)
DDR1
R/W
Port 1
00000000B
000012 H
Port Direction Register (for port 2)
DDR2
R/W
Port 2
00000000B
000013 H
Port Direction Register (for port 3)
DDR3
R/W
Port 3
00000000B
000014 H
Port Direction Register (for port 4)
DDR4
R/W
Port 4
00000000B
000015 H
Port Direction Register (for port 5)
DDR5
R/W
Port 5
00000000B
000016 H
Port Direction Register (for port 6)
DDR6
R/W
Port 6
00000000B
000017 H
Port Direction Register (for port 7)
DDR7
R/W
Port 7
00000000B
000018 H
Port Direction Register (for port 8)
DDR8
R/W
Port 8
00000000B
000019 H
Port Direction Register (for port 9)
DDR9
R/W
Port 9
--000000B
R/W
Port 6, A/D
11111111B
00001A H
00001B H
416
Use prohibited
Analog Input Enable Register
(for port 6)
ADER
APPENDIX A I/O Maps
Table A-1 I/O Map (2/6)
Address
Register
00001C to
00001F H
Abbreviation
Access
Resource
Initial value
Use prohibited
000020 H
Serial Mode Control Register 0
UMC0
W,R/W
00000100B
000021 H
Serial Status Register 0
USR0
R,R/W
00010000B
000022 H
Serial Input/Serial Output Data
Register 0
UIDR0/
UODR0
R/W
XXXXXXXXB
000023 H
Rate/Data Register 0
URD0
R/W
0000000XB
000024 H
Serial Mode Control Register 1
UMC1
W,R/W
00000100B
000025 H
Serial Status Register 1
USR1
R,R/W
00010000B
000026 H
Serial Input/Serial Output Data
Register 1
UIDR1/
UODR1
R/W
XXXXXXXXB
000027 H
Rate/Data Register 1
URD1
R/W
0000000XB
000028 H
Serial Mode Control Register 2
UMC2
W,R/W
00000100B
000029 H
Serial Status Register 2
USR2
R,R/W
00010000B
00002A H
Serial Input/Serial Output Data
Register 2
UIDR2/
UODR2
R/W
XXXXXXXXB
00002B H
Rate/Data Register 2
URD2
R/W
0000000XB
00002C H
Serial Mode Control Status
Register
R/W
SMCS
----0000B
00002D H
UART0
UART1
UART2
R,R/W
Serial I/O
00000010B
00002E H
Serial Data Register
SDR
R/W
XXXXXXXXB
00002F H
Serial Edge Selector Register
SES
R/W
-------0B
000030 H
DTP/Interrupt Enable Register
ENIR
R/W
00000000B
000031 H
DTP/Interrupt Request Register
EIRR
R/W
External Interrupt Level Register
ELVR
R/W
000032 H
DTP/External
interrupt
000033 H
XXXXXXXXB
00000000B
00000000B
000034 H
A/D Control Status Register 0
ADCS0
R/W
00000000B
000035 H
A/D Control Status Register 1
ADCS1
W,R/W
000036 H
A/D Data Register 0
ADCR0
R
XXXXXXXXB
000037 H
A/D Data Register 1
ADCR1
R,W
000010XXB
000038 H
PPG0 Operation Mode Control
Register
PPGC0
W,R/W
000039 H
PPG1 Operation Mode Control
Register
PPGC1
W,R/W
00003A H
PPG0/1 Clock Selection Register
PPG01
R/W
A/D converter
00000000B
0-000--1B
PPG
(ch.0,ch.1)
unit 0
0-000001B
000000--B
417
APPENDIX A I/O Maps
Table A-1 I/O Map (3/6)
Address
Register
00003B H
Abbreviation
Access
PPGC2
00003D H
PPG3 Operation Mode Control
Register
PPGC3
W,R/W
00003E H
PPG2/3 Clock Selection Register
PPG23
R/W
00003F H
W,R/W
PPGC4
000041 H
PPG5 Operation Mode Control
Register
PPGC5
W,R/W
000042 H
PPG4/5 Clock Selection Register
PPG45
R/W
000043 H
000045 H
PPG7 Operation Mode Control
Register
PPGC7
W,R/W
000046 H
PPG6/7 Clock Selection Register
PPG67
R/W
000047 H
0-000--1B
PPG
(ch.6,ch.7)
unit 3
0-000001B
000000--B
Use prohibited
PPGC8
000049 H
PPG9 Operation Mode Control
Register
PPGC9
W,R/W
00004A H
PPG8/9 Clock Selection Register
PPG89
R/W
00004B H
W,R/W
0-000--1B
PPG
(ch.8,ch.9)
unit 4
0-000001B
000000--B
Use prohibited
PPGA Operation Mode Control
Register
PPGCA
00004D H
PPGB Operation Mode Control
Register
PPGCB
W,R/W
00004E H
PPGA/B Clock Selection Register
PPGAB
R/W
00004F H
0-000--1B
W,R/W
PPG
(ch.A,ch.B)
unit 5
0-000001B
000000--B
Use prohibited
000050 H
Timer Control Status Register 0
(lower)
TMCSR0
000051 H
Timer Control Status Register 0
(upper)
TMCSR0
R/W
000052 H
Timer Control Status Register 1
(lower)
TMCSR1
R/W
418
0-000001B
000000--B
W,R/W
PPG8 Operation Mode Control
Register
00004C H
0-000--1B
PPG
(ch.4,ch.5)
unit 2
Use prohibited
PPGC6
000048 H
0-000001B
000000--B
W,R/W
PPG6 Operation Mode Control
Register
000044 H
0-000--1B
PPG
(ch.2,ch.3)
unit 1
Use prohibited
PPG4 Operation Mode Control
Register
000040 H
Initial value
Use prohibited
PPG2 Operation Mode Control
Register
00003C H
Resource
R/W
16-bit reload
timer 0
00000000B
----0000B
16-bit reload
timer 1
00000000B
APPENDIX A I/O Maps
Table A-1 I/O Map (4/6)
Address
Register
Abbreviation
Access
Resource
Initial value
TMCSR1
R/W
16-bit reload
timer 1
----0000B
000053 H
Timer Control Status Register 1
(upper)
000054 H
Input Capture Control Status
Register 0/1
ICS01
R/W
Input capture
0/1
00000000B
000055 H
Input Capture Control Status
Register 2/3
ICS23
R/W
Input capture
2/3
00000000B
000056 H
Input Capture Control Status
Register 4/5
ICS45
R/W
Input capture
4/5
00000000B
000057 H
Use prohibited
000058 H
Output Compare Control Status
Register 0
OCS0
000059 H
Output Compare Control Status
Register 1
OCS1
R/W
00005A H
Output Compare Control Status
Register 2
OCS2
R/W
00005B H
Output Compare Control Status
Register 3
OCS3
R/W
00005C H
Output Compare Control Status
Register 4
OCS4
R/W
00005D H
Output Compare Control Status
Register 5
OCS5
R/W
00005E H
Sound Control Register (lower)
SGCR
R/W
00005F H
Sound Control Register (upper)
SGCR
R,R/W
000060 H
Timer Control Register (lower)
WTCR
R/W
000061 H
Timer Control Register (upper)
WTCR
R/W
000062 H
PWM Control Register 0
PWC0
R/W
Stepping
motor
controller 0
00000--0B
R/W
Stepping
motor
controller 1
00000--0B
R/W
Stepping
motor
controller 2
00000--0B
000067 H
0000--00B
---00000B
Output
compare 2/3
0000--00B
---00000B
Output
compare 4/5
0000--00B
---00000B
Sound
generator
00000000B
0-----00B
000--000B
00000000B
Use prohibited
PWM Control Register 1
000065 H
000066 H
Output
compare 0/1
Watch timer
000063 H
000064 H
R/W
PWC1
Use prohibited
PWM Control Register 2
PWC2
Use prohibited
419
APPENDIX A I/O Maps
Table A-1 I/O Map (5/6)
Address
000068 H
Register
PWM Control Register 3
Abbreviation
Access
Resource
Initial value
PWC3
R/W
Stepping
motor
controller 3
00000--0B
000069 H
Use prohibited
00006A to
00006C H
Use prohibited
00006D H
Serial I/O Prescaler Register
CDCR
R/W
Serial I/O
0---1111B
00006E H
Timer Counter Control Status
Register
TCCS
R/W
I/O timer
00000000B
00006F H
ROM Mirror Function Select
Register
ROMM
W
ROM mirror
function select
module
-------1B
000070 to
00008F H
Reserved for CAN interface 0/1. See the "CAN Controller Hardware Manual".
000090 to
00009D H
Use prohibited
PACSR
R/W
Address
Match
Detection
Function
DIRR
R/W
Delayed
interrupt
Low-Power Mode Control Register
LPMCR
W,R/W
Clock Selection Register
CKSCR
R,R/W
00009E H
Program Address Detection
Control Status Register
00009F H
Delayed Interrupt/Release
Register
0000A0 H
0000A1 H
0000A2 to
0000A7H
Low-power
control circuit
00000000B
-------0B
00011000B
11111100B
Use prohibited
0000A8 H
Watch-dog Timer Control Register
WDTC
R,W
Watch-dog
timer
XXXXX111B
0000A9 H
Timebase Timer Control Register
TBTC
W,R/W
Timebase
timer
1--00100B
Flash memory
000X0000B
0000AA to
0000AD H
0000AE H
0000AF H
420
Use prohibited
Flash Memory Control Status
Register (only for MB90F594A/
MB90F594G/MB90591A/
MB90F591G. Use prohibited for
other controllers.)
FMCS
R,R/W
Use prohibited
APPENDIX A I/O Maps
Table A-1 I/O Map (6/6)
Address
Register
Abbreviation
Access
Resource
Initial value
0000B0 H
Interrupt Control Register 00
ICR00
W,R/W
00000111B
0000B1 H
Interrupt Control Register 01
ICR01
W,R/W
00000111B
0000B2 H
Interrupt Control Register 02
ICR02
W,R/W
00000111B
0000B3 H
Interrupt Control Register 03
ICR03
W,R/W
00000111B
0000B4 H
Interrupt Control Register 04
ICR04
W,R/W
00000111B
0000B5 H
Interrupt Control Register 05
ICR05
W,R/W
00000111B
0000B6 H
Interrupt Control Register 06
ICR06
W,R/W
00000111B
0000B7 H
Interrupt Control Register 07
ICR07
W,R/W
0000B8 H
Interrupt Control Register 08
ICR08
W,R/W
0000B9 H
Interrupt Control Register 09
ICR09
W,R/W
00000111B
0000BA H
Interrupt Control Register 10
ICR10
W,R/W
00000111B
0000BB H
Interrupt Control Register 11
ICR11
W,R/W
00000111B
0000BC H
Interrupt Control Register 12
ICR12
W,R/W
00000111B
0000BD H
Interrupt Control Register 13
ICR13
W,R/W
00000111B
0000BE H
Interrupt Control Register 14
ICR14
W,R/W
00000111B
0000BF H
Interrupt Control Register 15
ICR15
W,R/W
00000111B
0000C0 to
0000FF H
Interrupt
controller
00000111B
00000111B
Use prohibited
421
APPENDIX A I/O Maps
Table A-2 I/O Map (19XX Address) (1/5)
Address
Register
Abbreviation
Access
Resource
Initial value
1900 H
Reload Register L
PRLL0
R/W
1901 H
Reload Register H
PRLH0
R/W
1902 H
Reload Register L
PRLL1
R/W
1903 H
Reload Register H
PRLH1
R/W
XXXXXXXXB
1904 H
Reload Register L
PRLL2
R/W
XXXXXXXXB
1905 H
Reload Register H
PRLH2
R/W
1906 H
Reload Register L
PRLL3
R/W
1907 H
Reload Register H
PRLH3
R/W
XXXXXXXXB
1908 H
Reload Register L
PRLL4
R/W
XXXXXXXXB
1909 H
Reload Register H
PRLH4
R/W
190A H
Reload Register L
PRLL5
R/W
190B H
Reload Register H
PRLH5
R/W
XXXXXXXXB
190C H
Reload Register L
PRLL6
R/W
XXXXXXXXB
190D H
Reload Register H
PRLH6
R/W
190E H
Reload Register L
PRLL7
R/W
190F H
Reload Register H
PRLH7
R/W
XXXXXXXXB
1910 H
Reload Register L
PRLL8
R/W
XXXXXXXXB
1911 H
Reload Register H
PRLH8
R/W
1912 H
Reload Register L
PRLL9
R/W
1913 H
Reload Register H
PRLH9
R/W
XXXXXXXXB
1914 H
Reload Register L
PRLLA
R/W
XXXXXXXXB
1915 H
Reload Register H
PRLHA
R/W
1916 H
Reload Register L
PRLLB
R/W
1917 H
Reload Register H
PRLHB
R/W
1918 to
191F H
422
Use prohibited
XXXXXXXXB
PPG
(ch.0,ch.1)
unit 0
PPG
(ch.2,ch.3)
unit 1
PPG
(ch.4,ch.5)
unit 2
PPG
(ch.6,ch.7)
unit 3
PPG
(ch.8,ch.9)
unit 4
PPG
(ch.A,ch.B)
unit 5
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
APPENDIX A I/O Maps
Table A-2 I/O Map (19XX Address) (2/5)
Address
Register
Abbreviation
Access
Resource
Initial value
1920 H
Input Capture Data
Register 0 (lower)
IPCP0
R
XXXXXXXXB
1921 H
Input Capture Data
Register 0 (upper)
IPCP0
R
XXXXXXXXB
1922 H
Input Capture Data
Register 1 (lower)
IPCP1
R
XXXXXXXXB
1923 H
Input Capture Data
Register 1 (upper)
IPCP1
R
XXXXXXXXB
1924 H
Input Capture Data
Register 2 (lower)
IPCP2
R
XXXXXXXXB
1925 H
Input Capture Data
Register 2 (upper)
IPCP2
R
XXXXXXXXB
1926 H
Input Capture Data
Register 3 (lower)
IPCP3
R
XXXXXXXXB
1927 H
Input Capture Data
Register 3 (upper)
IPCP3
R
XXXXXXXXB
1928 H
Input Capture Data
Register 4 (lower)
IPCP4
R
XXXXXXXXB
1929 H
Input Capture Data
Register 4 (upper)
IPCP4
R
192A H
Input Capture Data
Register 5 (lower)
IPCP5
R
XXXXXXXXB
192B H
Input Capture Data
Register 5 (upper)
IPCP5
R
XXXXXXXXB
Input capture 0/1
Input capture 2/3
192D to
192F H
Input capture 4/5
XXXXXXXXB
Use prohibited
1930 H
Output Compare Register 0
(lower)
OCCP0
R/W
XXXXXXXXB
1931 H
Output Compare Register 0
(upper)
OCCP0
R/W
XXXXXXXXB
1932 H
Output Compare Register 1
(lower)
OCCP1
R/W
XXXXXXXXB
1933 H
Output Compare Register 1
(upper)
OCCP1
R/W
XXXXXXXXB
Output compare 0/1
423
APPENDIX A I/O Maps
Table A-2 I/O Map (19XX Address) (3/5)
Address
Register
Abbreviation
Access
Resource
Initial value
1934 H
Output Compare Register 2
(lower)
OCCP2
R/W
XXXXXXXXB
1935 H
Output Compare Register 2
(upper)
OCCP2
R/W
XXXXXXXXB
1936 H
Output Compare Register 3
(lower)
OCCP3
R/W
XXXXXXXXB
1937 H
Output Compare Register 3
(upper)
OCCP3
R/W
XXXXXXXXB
1938 H
Output Compare Register 4
(lower)
OCCP4
R/W
XXXXXXXXB
1939 H
Output Compare Register 4
(upper)
OCCP4
R/W
XXXXXXXXB
193A H
Output Compare Register 5
(lower)
OCCP5
R/W
XXXXXXXXB
193B H
Output Compare Register 5
(upper)
OCCP5
R/W
XXXXXXXXB
Output compare 2/3
Output compare 4/5
193D to
193F H
Use prohibited
1940 H
Timer Register 0/reload
Register 0 (lower)
TMR0/
TMRLR0
1941 H
Timer Register 0/Reload
Register 0 (upper)
TMR0/
TMRLR0
R/W
XXXXXXXXB
1942 H
Timer Register 1/Reload
Register 1 (lower)
TMR1/
TMRLR1
R/W
XXXXXXXXB
1943 H
Timer Register 1/Reload
Register 1 (upper)
TMR1/
TMRLR1
R/W
XXXXXXXXB
1944 H
Timer Counter Data
Register (lower)
TCDT
R/W
00000000B
1945 H
Timer Counter Data
Register (upper)
TCDT
R/W
00000000B
1946 H
Frequency Data Register
SGFR
R/W
XXXXXXXXB
1947 H
Amplitude Data Register
SGAR
R/W
1948 H
Decrement Grade Register
SGDR
R/W
XXXXXXXXB
1949 H
Tone Count Register
SGTR
R/W
XXXXXXXXB
R/W
XXXXXXXXB
16-bit reload timer 0
16-bit reload timer 1
I/O timer
424
Sound generator
00000000B
APPENDIX A I/O Maps
Table A-2 I/O Map (19XX Address) (4/5)
Address
Register
Abbreviation
Access
Resource
Initial value
194A H
Sub-second Register
(lower)
WTBR
R/W
XXXXXXXXB
194B H
Sub-second Register
(middle)
WTBR
R/W
XXXXXXXXB
194C H
Sub-second Register
(upper)
WTBR
R/W
194D H
Second Register
WTSR
R/W
--000000B
194E H
Minute Register
WTMR
R/W
--000000B
194F H
Hour Register
WTHR
R/W
---00000B
1950 H
PWM1 Compare Register 0
(lower)
PWC10
R/W
XXXXXXXXB
1951 H
PWM2 Compare Register 0
(upper)
PWC20
R/W
1952 H
PWM1 Select Register 0
(lower)
PWS10
R/W
--000000B
1953 H
PWM2 Select Register 0
(upper)
PWS20
R/W
-0000000B
1954 H
PWM1 Compare Register 1
(lower)
PWC11
R/W
XXXXXXXXB
1955 H
PWM2 Compare Register 1
(upper)
PWC21
R/W
1956 H
PWM1 Select Register 1
(lower)
PWS11
R/W
--000000B
1957 H
PWM2 Select Register 1
(upper)
PWS21
R/W
-0000000B
1958 H
PWM1 Compare Register 2
(lower)
PWC12
R/W
XXXXXXXXB
1959 H
PWM2 Compare Register 2
(upper)
PWC22
R/W
195A H
PWM1 Select Register 2
(lower)
PWS12
R/W
--000000B
195B H
PWM2 Select Register 2
(upper)
PWS22
R/W
-0000000B
Watch timer
Stepping motor
controller 0
Stepping motor
controller 1
Stepping motor
controller 2
---XXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
425
APPENDIX A I/O Maps
Table A-2 I/O Map (19XX Address) (5/5)
Address
Register
Abbreviation
Access
195C H
PWM1 Compare Register 3
(lower)
PWC13
R/W
195D H
PWM2 Compare Register 3
(upper)
PWC23
R/W
195E H
PWM1 Select Register 3
(lower)
PWS13
R/W
--000000B
195F H
PWM2 Select Register 3
(upper)
PWS23
R/W
-0000000B
1960 to
19FF H
Resource
XXXXXXXXB
Stepping motor
controller 3
XXXXXXXXB
Used prohibited
1A00 to
1AFF H
Reserved for CAN interface 0. See the "CAN Controller Hardware Manual".
1B00 to
1BFF H
Reserved for CAN interface 1. See the "CAN Controller Hardware Manual".
1C00 to
1CFF H
Reserved for CAN interface 0. See the "CAN Controller Hardware Manual".
1D00 to
1DFF H
Reserved for CAN interface 1. See the "CAN Controller Hardware Manual".
1E00 to
1EFF H
Use prohibited
1EF0 H
Program Address Detection
Register 0 (low-order)
1EF1 H
Program Address Detection
Register 0 (middle-order)
1EF2 H
Program Address Detection
Register 0 (high-order)
1EF3 H
Program Address Detection
Register 1 (low-order)
1EF4 H
Program Address Detection
Register 1 (middle-order)
1EF5 H
Program Address Detection
Register 1 (high-order)
1EF6 to
1FFF H
426
Initial value
XXXXXXXXB
PADR0
R/W
XXXXXXXXB
Address match
detection function
XXXXXXXXB
XXXXXXXXB
PADR1
R/W
XXXXXXXXB
XXXXXXXXB
Use prohibited
•
Initial value "-" indicates an unused bit, and "X" indicates an undefined value.
•
The addresses between 0000H and 00FFH, which are not listed, have been reserved for the
main functions of the MCU. The result of read access to these reserved addresses is "X".
Write access to these addresses is prohibited.
APPENDIX A I/O Maps
❍ Explanation of write and read
R/W: Both read and write enabled
R: Only read enabled
W: Only write enabled
❍ Explanation of initial values
0: The initial value of this bit is "0".
1: The initial value of this bit is "1".
X: The initial value of this bit is undefined.
-: This bit is not used, and the initial value is undefined.
427
APPENDIX B Instructions
APPENDIX B Instructions
APPENDIX B describes the instructions used by the F2MC-16LX.
B.1 Instruction Types
B.2 Addressing
B.3 Direct Addressing
B.4 Indirect Addressing
B.5 Execution Cycle Count
B.6 Effective address field
B.7 How to Read the Instruction List
B.8 F2MC-16LX Instruction List
B.9 Instruction Map
Code: CM44-00202-1E
428
APPENDIX B Instructions
B.1
Instruction Types
The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an
effective address field of each instruction or using the instruction code itself.
■
Instruction Types
The F2MC-16LX supports the following 351 types of instructions:
•
41 transfer instructions (byte)
•
38 transfer instructions (word or long word)
•
42 addition/subtraction instructions (byte, word, or long word)
•
12 increment/decrement instructions (byte, word, or long word)
•
11 comparison instructions (byte, word, or long word)
•
11 unsigned multiplication/division instructions (word or long word)
•
11 signed multiplication/division instructions (word or long word)
•
39 logic instructions (byte or word)
•
6 logic instructions (long word)
•
6 sign inversion instructions (byte or word)
•
1 normalization instruction (long word)
•
18 shift instructions (byte, word, or long word)
•
50 branch instructions
•
6 accumulator operation instructions (byte or word)
•
28 other control instructions (byte, word, or long word)
•
21 bit operation instructions
•
10 string instructions
429
APPENDIX B Instructions
B.2
Addressing
With the F2MC-16LX, the address format is determined by the instruction effective
address field or the instruction code itself (implied). When the address format is
determined by the instruction code itself, specify an address in accordance with the
instruction code used. Some instructions permit the user to select several types of
addressing.
■
Addressing
The F2MC-16LX supports the following 23 types of addressing:
430
•
Immediate (#imm)
•
Register direct
•
Direct branch address (addr16)
•
Physical direct branch address (addr24)
•
I/O direct (io)
•
Abbreviated direct address (dir)
•
Direct address (addr16)
•
I/O direct bit address (io:bp)
•
Abbreviated direct bit address (dir:bp)
•
Direct bit address (addr16:bp)
•
Vector address (#vct)
•
Register indirect (@RWj j = 0 to 3)
•
Register indirect with post increment (@RWj+ j = 0 to 3)
•
Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
•
Long register indirect with displacement (@RLi + disp8 i = 0 to 3)
•
Program counter indirect with displacement (@PC + disp16)
•
Register indirect with base index (@RW0 + RW7, @RW1 + RW7)
•
Program counter relative branch address (rel)
•
Register list (rlst)
•
Accumulator indirect (@A)
•
Accumulator indirect branch address (@A)
•
Indirectly-specified branch address (@ear)
•
Indirectly-specified branch address (@eam)
APPENDIX B Instructions
■
Effective Address Field
Table B.2-1 lists the address formats specified by the effective address field.
Table B.2-1 Effective Address Field
Code
Representation
00
R0
RW0
RL0
01
R1
RW1
(RL0)
02
R2
RW2
RL1
03
R3
RW3
(RL1)
04
R4
RW4
RL2
05
R5
RW5
(RL2)
06
R6
RW6
RL3
07
R7
RW7
(RL3)
08
@RW0
09
@RW1
Address format
Default bank
Register direct: Individual parts correspond to the
byte, word, and long word types in order from the
left.
None
DTB
DTB
Register indirect
0A
@RW2
ADB
0B
@RW3
SPB
0C
@RW0+
DTB
0D
@RW1+
DTB
Register indirect with post increment
0E
@RW2+
ADB
0F
@RW3+
SPB
10
@RW0+disp8
DTB
11
@RW1+disp8
DTB
Register indirect with 8-bit displacement
12
@RW2+disp8
ADB
13
@RW3+disp8
SPB
14
@RW4+disp8
DTB
15
@RW5+disp8
DTB
Register indirect with 8-bit displacement
16
@RW6+disp8
ADB
17
@RW7+disp8
SPB
18
@RW0+disp16
DTB
19
@RW1+disp16
DTB
Register indirect with 16-bit displacement
1A
@RW2+disp16
ADB
1B
@RW3+disp16
SPB
1C
@RW0+RW7
Register indirect with index
DTB
1D
@RW1+RW7
Register indirect with index
DTB
1E
@PC+disp16
PC indirect with 16-bit displacement
PCB
1F
addr16
Direct address
DTB
431
APPENDIX B Instructions
B.3
Direct Addressing
An operand value, register, or address is specified explicitly in direct addressing mode.
■
Direct Addressing
● Immediate addressing (#imm)
Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32).
Figure B.3-1 Example of Immediate Addressing (#imm)
MOVW A, #01212H (This instruction stores the operand value in A.)
Before execution
A 2233
4455
After execution
A 4455
1 2 1 2 (Some instructions transfer AL to AH.)
● Register direct addressing
Specify a register explicitly as an operand. Table B.3-1 lists the registers that can be specified. Figure B.3-2
shows an example of register direct addressing.
Table B.3-1 Direct Addressing Registers
General-purpose register
Special-purpose register
Byte
R0, R1, R2, R3, R4, R5, R6, R7
Word
RW0, RW1, RW2, RW3, RW4, RW5, RW6,
RW7
Long word
RL0, RL1, RL2, RL3
Accumulator
A, AL
Pointer
SP *
Bank
PCB, DTB, USB, SSB, ADB
Page
DPR
Control
PS, CCR, RP, ILM
*: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on
the value of the S flag bit in the condition code register (CCR). For branch instructions, the program
counter (PC) is not specified in an instruction operand but is specified implicitly.
432
APPENDIX B Instructions
Figure B.3-2 Example of Register Direct Addressing
MOV R0, A (This instruction transfers the eight low-order bits of A to the generalpurpose register R0.)
Before execution
A 0716
2534
Memory space
R0
After execution
A 0716
2564
??
Memory space
R0
34
● Direct branch addressing (addr16)
Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which
indicates the branch destination in the logical address space. Direct branch addressing is used for an
unconditional branch, subroutine call, or software interrupt instruction. Bit23 to bit16 of the address are
specified by the program counter bank register (PCB).
Figure B.3-3 Example of Direct Branch Addressing (addr16)
JMP 3B20H (This instruction causes an unconditional branch by direct branch
addressing in a bank.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
62
4F3C21H
20
4F3C22H
3B
JMP 3B20H
433
APPENDIX B Instructions
● Physical direct branch addressing (addr24)
Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical
direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction.
Figure B.3-4 Example of Direct Branch Addressing (addr24)
JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit
addressing.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 3 3
Memory space
333B20H
Next instruction
4F3C20H
63
4F3C21H
20
4F3C22H
3B
4F3C23H
33
JMPP 333B20H
● I/O direct addressing (io)
Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the
physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB)
and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an
instruction using I/O direct addressing.
Figure B.3-5 Example of I/O Direct Addressing (io)
MOVW A, i : 0C0H (This instruction reads data by I/O direct addressing and stores it
in A.)
Before execution
After execution
434
A 0716
2534
A 2534 FFEE
Memory space
0000C0H
EE
0000C1H
FF
APPENDIX B Instructions
● Abbreviated direct addressing (dir)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB).
Figure B.3-6 Example of Abbreviated Direct Addressing (dir)
MOV S : 20H, A (This instruction writes the contents of the eight low-order bits of A in
abbreviated direct addressing mode.)
Before execution
A 4455
DPR 6 6
After execution
A 4455
DPR 6 6
1212
DTB 7 7
Memory space
776620H
1212
DTB 7 7
??
Memory space
776620H
12
● Direct addressing (addr16)
Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are
specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for
this mode of addressing.
Figure B.3-7 Example of Direct Addressing (addr16)
MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.)
Before execution
After execution
A 2020
A AABB
AABB
0123
DTB 5 5
Memory space
553B21H
01
553B20H
23
DTB 5 5
435
APPENDIX B Instructions
● I/O direct bit addressing (io:bp)
Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp",
where the larger number indicates the most significant bit (MSB) and the lower number indicates the least
significant bit (LSB).
Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp)
SETB i : 0C1H : 0 (This instruction sets bits by I/O direct bit addressing.)
Memory space
Before execution
0000C1H
00
Memory space
After execution
0000C1H
01
● Abbreviated direct bit addressing (dir:bp)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure B.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp)
SETB S : 10H : 0 (This instruction sets bits by abbreviated direct bit addressing.)
Memory space
Before execution
DTB 5 5
DPR 6 6
556610H
00
Memory space
After execution
DTB 5 5
DPR 6 6
556610H
01
● Direct bit addressing (addr16:bp)
Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure B.3-10 Example of Direct Bit Addressing (addr16:bp)
SETB 2222H : 0 (This instruction sets bits by direct bit addressing.)
Memory space
Before execution
DTB 5 5
552222H
00
Memory space
After execution
436
DTB 5 5
552222H
01
APPENDIX B Instructions
● Vector Addressing (#vct)
Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector
numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction.
Figure B.3-11 Example of Vector Addressing (#vct)
CALLV #15 (This instruction causes a branch to the address indicated by the interrupt
vector specified in an operand.)
Before execution
PC 0 0 0 0
Memory space
PCB F F
After execution
FFC000H
EF
CALLV #15
PC D 0 0 0
PCB F F
FFFFE0H
00
FFFFE1H
D0
Table B.3-2 CALLV Vector List
Instruction
Vector address L
Vector address H
CALLV #0
XXFFFEH
XXFFFFH
CALLV #1
XXFFFCH
XXFFFDH
CALLV #2
XXFFFAH
XXFFFBH
CALLV #3
XXFFF8H
XXFFF9H
CALLV #4
XXFFF6H
XXFFF7H
CALLV #5
XXFFF4H
XXFFF5H
CALLV #6
XXFFF2H
XXFFF3H
CALLV #7
XXFFF0H
XXFFF1H
CALLV #8
XXFFEEH
XXFFEFH
CALLV #9
XXFFECH
XXFFEDH
CALLV #10
XXFFEAH
XXFFEBH
CALLV #11
XXFFE8H
XXFFE9H
CALLV #12
XXFFE6H
XXFFE7H
CALLV #13
XXFFE4H
XXFFE5H
CALLV #14
XXFFE2H
XXFFE3H
CALLV #15
XXFFE0H
XXFFE1H
Note: A PCB register value is set in XX.
Note:
When the program counter bank register (PCB) is FFH, the vector area overlaps the vector area of
INT #vct8 (#0 to #7). Use vector addressing carefully (see Table B.3-2).
437
APPENDIX B Instructions
B.4
Indirect Addressing
In indirect addressing mode, an address is specified indirectly by the address data of an
operand.
■
Indirect Addressing
● Register indirect addressing (@RWj j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to
23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register
(SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when
RW2 is used.
Figure B.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3)
MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores
it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 0 F
DTB 7 8
● Register indirect addressing with post increment (@RWj+ j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. After operand
operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word).
Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system
stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank
register (ADB) when RW2 is used.
If the post increment results in the address of the register that specifies the increment, the incremented
value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to
writing by an instruction and, therefore, the register that would be incremented becomes write data.
438
APPENDIX B Instructions
Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3)
MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post
increment and stores it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 1 1
DTB 7 8
● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
Memory is accessed using the address obtained by adding an offset to the contents of general-purpose
register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric
values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or
RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is
used, or additional data bank register (ADB) when RW2 or RW6 is used.
Figure B.4-3 Example of Register Indirect Addressing with Offset
(@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+10H)
RW1 D 3 0 F
After execution
DTB 7 8
Memory space
78D31FH
EE
78D320H
FF
A 2534 FFEE
RW1 D 3 0 F
DTB 7 8
439
APPENDIX B Instructions
● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the
contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value.
Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3)
MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+25H)
RL2 F 3 8 2
After execution
4B02
Memory space
824B27H
EE
824B28H
FF
A 2534 FFEE
RL2 F 3 8 2
4B02
● Program counter indirect addressing with offset (@PC + disp16)
Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one
word long. Address bits 16 to 23 are specified by the program counter bank register (PCB). Note that the
operand address of each of the following instructions is not deemed to be (next instruction address +
disp16):
•
DBNZ eam, rel
•
DWBNZ eam, rel
•
CBNE eam, #imm8, rel
•
CWBNE eam, #imm16, rel
•
MOV eam, #imm8
•
MOVW eam, #imm16
Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16)
MOVW A, @PC+20H (This instruction reads data by program counter indirect
addressing with an offset and stores it in A.)
Before execution
A 0716
2534
Memory space
PCB C 5 PC 4 5 5 6
After execution
A 2534
FFEE
PCB C 5 PC 4 5 5 A
440
+4
C54556H
73
C54557H
9E
C54558H
20
C54559H
00
C5455AH
.
.
.
+20H
C5457AH
EE
C5457BH
FF
MOVW
A, @PC+20H
APPENDIX B Instructions
● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7)
Memory is accessed using the address determined by adding RW0 or RW1 to the contents of generalpurpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB).
Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7)
MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with
a base index and stores it in A.)
Before execution
A 0716
RW1 D 3 0 F
WR7 0 1 0 1
After execution
A 2534
RW1 D 3 0 F
2534
+
DTB 7 8
Memory space
78D410H
EE
78D411H
FF
FFEE
DTB 7 8
WR7 0 1 0 1
441
APPENDIX B Instructions
● Program counter relative branch addressing (rel)
The address of the branch destination is a value determined by adding an 8-bit offset to the program
counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is
not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte
bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to
23 are indicated by the program counter bank register (PCB).
Figure B.4-7 Example of Program Counter Relative Branch Addressing (rel)
BRA 10H (This instruction causes an unconditional relative branch.)
Before execution
After execution
PC 3 C 2 0
PC 3 C 3 2
PCB 4 F
PCB 4 F
Memory space
4F3C32H
Next instruction
4F3C21H
10
4F3C20H
60
BRA 10H
● Register list (rlst)
Specify a register to be pushed onto or popped from a stack.
Figure B.4-8 Configuration of the Register List
MSB
LSB
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
A register is selected when the corresponding bit is 1 and deselected when the bit is 0.
442
APPENDIX B Instructions
Figure B.4-9 Example of Register List (rlist)
POPW, RW0, RW4 (This instruction transfers memory data indicated by the SP to
multiple word registers indicated by the register list.)
SP
34FA
SP
34FE
RW0
×× ××
RW0
02 01
RW1
×× ××
RW1
×× ××
RW2
×× ××
RW2
×× ××
RW3
×× ××
RW3
×× ××
RW4
×× ××
RW4
04 03
RW5
×× ××
RW5
×× ××
RW6
×× ××
RW6
×× ××
RW7
×× ××
RW7
×× ××
Memory space
SP
Memory space
01
34FAH
01
34FAH
02
34FBH
02
34FBH
03
34FCH
03
34FCH
04
34FDH
04
34FDH
34FEH
SP
Before execution
34FEH
After execution
● Accumulator indirect addressing (@A)
Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the
accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB).
Figure B.4-10 Example of Accumulator Indirect Addressing (@A)
MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.)
Before execution
A
0716
2534
DTB B B
After execution
A
0716
Memory space
BB2534H
EE
BB2535H
FF
FFEE
DTB B B
443
APPENDIX B Instructions
● Accumulator indirect branch addressing (@A)
The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the
accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are
specified by the program counter bank register (PCB). For the Jump Context (JCTX) instruction, however,
address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for
unconditional branch instructions.
Figure B.4-11 Example of Accumulator Indirect Branch Addressing (@A)
JMP @A (This instruction causes an unconditional branch by accumulator indirect
branch addressing.)
Before execution
PC 3 C 2 0
A 6677
After execution
PC 3 B 2 0
A 6677
PCB 4 F
3B20
Memory space
4F3B20H
Next instruction
4F3C20H
61
JMP @A
PCB 4 F
3B20
● Indirect specification branch addressing (@ear)
The address of the branch destination is the word data at the address indicated by ear.
Figure B.4-12 Example of Indirect Specification Branch Addressing (@ear)
JMP @@RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
After execution
PC 3 C 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
PC 3 B 2 0
RW0 7 F 4 8
444
PCB 4 F
DTB 2 1
Memory space
217F48H
20
217F49H
3B
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
08
JMP @@RW0
APPENDIX B Instructions
● Indirect specification branch addressing (@eam)
The address of the branch destination is the word data at the address indicated by eam.
Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam)
JMP @RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
PC 3 C 2 0
PCB 4 F
RW0 3 B 2 0
After execution
PC 3 B 2 0
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
00
JMP @RW0
RW0 3 B 2 0
445
APPENDIX B Instructions
B.5
Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is
obtained by adding the number of cycles required for each instruction, "correction
value" determined by the condition, and the number of cycles for instruction fetch.
■
Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is obtained by adding the
number of cycles required for each instruction, "correction value" determined by the condition, and the
number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal
ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments.
Therefore, intervening in data access increases the execution cycle count.
Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the
program fetches every byte of an instruction being executed. Therefore, intervening in data access increases
the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register,
internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the
cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register.
Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add
the "access count x cycle count for the halt" as a correction value to the normal execution count.
446
APPENDIX B Instructions
■
Calculating the Execution Cycle Count
Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data.
Table B.5-1 Execution Cycle Counts in Each Addressing Mode
(a) *
Code
Operand
00
|
07
Ri
Rwi
RLi
08
|
0B
Execution cycle count in
each addressing mode
Register access count in
each addressing mode
See the instruction list.
See the instruction list.
@RWj
2
1
0C
|
0F
@RWj+
4
2
10
|
17
@RWi+disp8
2
1
18
|
1B
@RWi+disp16
2
1
1C
1D
1E
1F
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
4
4
2
1
2
2
0
0
*: (a) is used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List".
447
APPENDIX B Instructions
Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles
(b) byte *
Operand
(c) word *
(d) long *
Cycle
count
Access
count
Cycle
count
Access
count
Cycle
count
Access
count
Internal register
+0
1
+0
1
+0
2
Internal memory
Even address
+0
1
+0
1
+0
2
Internal memory
Odd address
+0
1
+2
2
+4
4
External data bus
16-bit even address
+1
1
+1
1
+2
2
External data bus
16-bit odd address
+1
1
+4
2
+8
4
External data bus
8-bits
+1
1
+4
2
+8
4
*: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction
List".
Note:
When an external data bus is used, the cycle counts during which an instruction is made to wait by
ready input or automatic ready must also be added.
Table B.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
-
+2
External data bus 16-bits
-
+3
External data bus 8-bits
+3
-
Notes:
• When an external data bus is used, the cycle counts during which an instruction is made to wait
by ready input or automatic ready must also be added.
• Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the
correction values to calculate the worst case.
448
APPENDIX B Instructions
B.6
Effective address field
Table B.6-1 shows the effective address field.
■
Effective Address Field
Table B.6-1 Effective Address Field
Code
Representation
Address format
Byte count of
extended
address part *
00
R0
RW0
RL0
01
R1
RW1
(RL0)
02
R2
RW2
RL1
Register direct: Individual parts correspond to
03
R3
RW3
(RL1)
the byte, word, and long word types in order
04
R4
RW4
RL2
from the left.
05
R5
RW5
(RL2)
06
R6
RW6
RL3
07
R7
RW7
(RL3)
08
@RW0
09
@RW1
Register indirect
0
0A
@RW2
0B
@RW3
0C
@RW0+
0D
@RW1+
Register indirect with post increment
0
0E
@RW2+
0F
@RW3+
10
@RW0+disp8
11
@RW1+disp8
12
@RW2+disp8
13
@RW3+disp8
Register indirect with 8-bit displacement
1
14
@RW4+disp8
15
@RW5+disp8
16
@RW6+disp8
17
@RW7+disp8
18
@RW0+disp16
19
@RW1+disp16
Register indirect with 16-bit displacement
2
1A
@RW2+disp16
1B
@RW3+disp16
1C
@RW0+RW7
Register indirect with index
0
1D
@RW1+RW7
Register indirect with index
0
1E
@PC+disp16
PC indirect with 16-bit displacement
2
1F
addr16
Direct address
2
*1: Each byte count of the extended address part applies to + in the # (byte count) column in "B.8 F2MC-16LX
Instruction List".
449
APPENDIX B Instructions
B.7
How to Read the Instruction List
Table B.7-1 describes the items used in "B.8 F2MC-16LX Instruction List", and Table
B.7-2 describes the symbols used in the same list.
■
Description of Instruction Presentation Items and Symbols
Table B.7-1 Description of Items in the Instruction List (1/2)
Item
Mnemonic
Uppercase, symbol: Represented as is in the assembler.
Lowercase: Rewritten in the assembler.
Number of following lowercase: Indicates bit length in the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
See Table B.2-1 for the alphabetical letters in items.
RG
B
Operation
Indicates the number of times a register access is performed during instruction
execution.
The number is used to calculate the correction value for CPU intermittent
operation.
Indicates the correction value used to calculate the actual number of cycles during
instruction execution.
The actual number of cycles during instruction execution can be determined by
adding the value in the ~ column to this value.
Indicates the instruction operation.
LH
Indicates the special operation for bit15 to bit08 of the accumulator.
Z: Transfers 0.
X: Transfers after sign extension.
-: No transfer
AH
Indicates the special operation for the 16 high-order bits of the accumulator.
*: Transfers from AL to AH.
-: No transfer
Z: Transfers 00 to AH.
X: Transfers 00H or FFH to AH after AL sign extension.
I
S
T
N
Z
V
C
450
Description
Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N
(negative), Z (zero), V (overflow), C (carry).
*: Changes upon instruction execution.
-: No change
S: Set upon instruction execution.
R: Reset upon instruction execution.
APPENDIX B Instructions
Table B.7-1 Description of Items in the Instruction List (1/2)
Item
Description
RMW
Indicates whether the instruction is a Read Modify Write instruction (reading data
from memory by the I instruction and writing the result to memory).
*: Read Modify Write instruction
-: Not Read Modify Write instruction
Note:
Cannot be used for an address that has different meanings between read and
write operations.
Table B.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
A
Explanation
The bit length used varies depending on the 32-bit accumulator instruction.
Byte: Low-order 8 bits of byte AL
Word: 16 bits of word AL
Long word: 32 bits of AL and AH
AH
16 high-order bits of A
AL
16 low-order bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
program counter bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
Ri
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
Direct addressing
addr24
Physical direct addressing
ad24 0-15
Bit0 to bit15 of addr24
451
APPENDIX B Instructions
Table B.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
ad24 16-23
io
Bit16 to bit23 of addr24
I/O area (000000H to 0000FFH)
#imm4
4-bit immediate data
#imm8
8-bit immediate data
#imm16
16-bit immediate data
#imm32
32-bit immediate data
ext (imm8)
16-bit data obtained by sign extension of 8-bit immediate data
disp8
8-bit displacement
disp16
16-bit displacement
bp
452
Explanation
Bit offset
vct4
Vector number (0 to 15)
vct8
Vector number (0 to 255)
( )b
Bit address
rel
PC relative branch
ear
Effective addressing (code 00 to 07)
eam
Effective addressing (code 08 to 1F)
rlst
Register list
APPENDIX B Instructions
B.8
F2MC-16LX Instruction List
Table B.8-1 to Table B.8-18 list the instructions used by the F2MC-16LX.
■
F2MC-16LX Instruction List
Table B.8-1 41 Transfer Instructions (Byte)
Mnemonic
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
XCH
XCH
XCH
XCH
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RLi+disp8
A,#imm4
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
Ri,A
ear,A
eam,A
io,A
@RLi+disp8,A
Ri,ear
Ri,eam
ear,Ri
eam,Ri
Ri,#imm8
io,#imm8
dir,#imm8
ear,#imm8
eam,#imm8
@AL,AH
A,ear
A,eam
Ri,ear
Ri,eam
#
~
RG
B
2
3
1
2
2+
2
2
2
3
1
2
3
2
2
2+
2
2
2
2
3
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
2
2+
2
2+
3
4
2
2
3 + (a)
3
2
3
10
1
3
4
2
2
3 + (a)
3
2
3
5
10
3
4
2
2
3 + (a)
3
10
3
4 + (a)
4
5 + (a)
2
5
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
0
0
1
1
0
0
0
0
2
0
0
0
1
1
0
0
0
0
1
2
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
2
0
4
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
0
2 × (b)
0
2 × (b)
Operation
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi)+disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
Z
Z
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table.
453
APPENDIX B Instructions
Table B.8-2 38 Transfer Instructions (Word, Long Word)
Mnemonic
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW
XCHW
XCHW
MOVL
MOVL
MOVL
MOVL
MOVL
A,dir
A,addr16
A,SP
A,RWi
A,ear
A,eam
A,io
A,@A
A,#imm16
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
SP,A
RWi,A
ear,A
eam,A
io,A
@RWi+disp8,A
@RLi+disp8,A
RWi,ear
RWi,eam
ear,RWi
eam,RWi
RWi,#imm16
io,#imm16
ear,#imm16
eam,#imm16
@AL,AH
A,ear
A,eam
RWi, ear
RWi, eam
A,ear
A,eam
A,#imm32
ear,A
eam,A
#
~
RG
B
2
3
1
1
2
2+
2
2
3
2
3
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
2
2
2+
2
2+
2
2+
5
2
2+
3
4
1
2
2
3 + (a)
3
3
2
5
10
3
4
1
2
2
3 + (a)
3
5
10
3
4 + (a)
4
5 + (a)
2
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
4
5 + (a)
3
4
5 + (a)
0
0
0
1
1
0
0
0
0
1
2
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
0
2
0
4
2
2
0
0
2
0
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
0
(c)
0
(c)
0
(c)
0
(c)
(c)
0
2 × (c)
0
2 × (c)
0
(d)
0
0
(d)
Operation
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi)+disp8)
word (A) ← ((RLi)+disp8)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
word ((RWi)+disp8) ← (A)
word ((RLi)+disp8) ← (A)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
word (ear) ← imm16
word (eam) ← imm16
word ((A)) ← (AH)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
long (ear) ← (A)
long(eam) ← (A)
LH
AH
I
S
T
N
Z
V
C
RMW
-
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a), (c), and (d) in the table.
454
APPENDIX B Instructions
Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
ADDW
ADDW
ADDW
ADDW
ADDW
ADDW
ADDCW
ADDCW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBCW
SUBCW
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A,ear
A,eam
A,#imm32
A,ear
A,eam
A,#imm32
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
2+
5
2
2+
5
2
3
4+(a)
2
3
5+(a)
3
4+(a)
2
3
4+(a)
2
3
5+(a)
3
4+(a)
6
7+(a)
4
6
7+(a)
4
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
2
0
0
2
0
0
0
0
(c)
0
0
2 × (c)
0
(c)
0
0
(c)
0
0
2 × (c)
0
(c)
0
(d)
0
0
(d)
0
Operation
byte (A) ← (A) + imm8
byte (A) ← (A) + (dir)
byte (A) ← (A) + (ear)
byte (A) ← (A) + (eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear)+ (C)
byte (A) ← (A) + (eam)+ (C)
byte (A) ← (AH) + (AL) + (C)
(decimal)
byte (A) ← (A) - imm8
byte (A) ← (A) - (dir)
byte (A) ← (A) - (ear)
byte (A) ← (A) - (eam)
byte (ear) ← (ear) - (A)
byte (eam) ← (eam) - (A)
byte (A) ← (AH) - (AL) - (C)
byte (A) ← (A) - (ear) - (C)
byte (A) ← (A) - (eam) - (C)
byte (A) ← (AH) - (AL) - (C)
(decimal)
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) - (AL)
word (A) ← (A) - (ear)
word (A) ← (A) - (eam)
word (A) ← (A) - imm16
word (ear) ← (ear) - (A)
word (eam) ← (eam) - (A)
word (A) ← (A) - (ear) - (C)
word (A) ← (A) - (eam) - (C)
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
long (A) ← (A) - (ear)
long (A) ← (A) - (eam)
long (A) ← (A) - imm32
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
455
APPENDIX B Instructions
Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word)
#
~
RG
B
INC
Mnemonic
ear
2
3
2
0
INC
eam
2+
5+(a)
0
2 × (b)
LH
AH
I
S
T
N
Z
V
C
byte (ear) ← (ear) + 1
Operation
-
-
-
-
-
*
*
*
-
RMW
-
byte (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DEC
ear
2
3
2
0
byte (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
DEC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
INCW
ear
2
3
2
0
word (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
INCW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DECW
ear
2
3
2
0
DECW
eam
2+
5+(a)
0
2 × (c)
INCL
ear
2
7
4
0
INCL
eam
2+
9+(a)
0
2 × (d)
DECL
ear
2
7
4
0
DECL
eam
2+
9+(a)
0
2 × (d)
word (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
word (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
Table B.8-5 11 Compare Instructions (Byte, Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
CMP
Mnemonic
A
1
1
0
0
byte (AH) - (AL)
Operation
-
-
-
-
-
*
*
*
*
-
CMP
A,ear
2
2
1
0
byte (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMP
A,eam
2+
3+(a)
0
(b)
byte (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMP
A,#imm8
2
2
0
0
byte (A) - imm8
-
-
-
-
-
*
*
*
*
-
CMPW
A
1
1
0
0
word (AH) - (AL)
-
-
-
-
-
*
*
*
*
-
CMPW
A,ear
2
2
1
0
word (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPW
A,eam
2+
3+(a)
0
(c)
word (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPW
A,#imm16
3
2
0
0
word (A) - imm16
-
-
-
-
-
*
*
*
*
-
CMPL
A,ear
2
6
2
0
long (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPL
A,eam
2+
7+(a)
0
(d)
long (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPL
A,#imm32
5
3
0
0
long (A) - imm32
-
-
-
-
-
*
*
*
*
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
456
APPENDIX B Instructions
Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
DIVU
Mnemonic
A
1
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
Operation
-
-
-
-
-
-
-
*
*
-
DIVU
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
-
-
-
-
-
-
-
*
*
-
DIVU
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MULU
A
1
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
MULU
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A
1
*11
0
0
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
MULUW
A,ear
2
*12
1
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,eam
2+
*13
0
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
*1: 3: Division by 0 7: Overflow 15: Normal
*2: 4: Division by 0 8: Overflow 16: Normal
*3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal
*4: 4: Division by 0 7: Overflow 22: Normal
*5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal
*6: (b): Division by 0 or overflow 2 × (b): Normal
*7: (c): Division by 0 or overflow 2 × (c): Normal
*8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0.
*9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0.
*10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0.
*11: 3: Word (AH) is 0. 11: Word (AH) is not 0.
*12: 4: Word (ear) is 0. 12: Word (ear) is not 0.
*13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0.
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
457
APPENDIX B Instructions
Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
DIV
Mnemonic
A
2
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
Operation
Z
-
-
-
-
-
-
*
*
-
DIV
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
Z
-
-
-
-
-
-
*
*
-
DIV
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
Z
-
-
-
-
-
-
*
*
-
DIVW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MUL
A
2
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,eam
2+
*10
0
(b)
MULW
A
2
*11
0
0
MULW
A,ear
2
*12
1
MULW
A,eam
2+
*13
0
*1:
*2:
*3:
*4:
3: Division by 0, 8 or 18: Overflow, 18: Normal
4: Division by 0, 11 or 22: Overflow, 23: Normal
5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal
When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal
When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal
*5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal
When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal
*6: (b): Division by 0 or overflow, 2 × (b): Normal
*7: (c): Division by 0 or overflow, 2 × (c): Normal
*8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative
*9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative
*10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative
*11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative
*12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative
*13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative
Notes:
• The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a
pre-operation count or a post-operation count depending on the detection timing.
• When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed.
• See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
458
APPENDIX B Instructions
Table B.8-8 39 Logic 1 Instructions (Byte, Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
AND
A,#imm8
2
2
0
0
byte (A) ← (A) and imm8
-
-
-
-
-
*
*
R
-
-
AND
A,ear
2
3
1
0
byte (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
AND
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
byte (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
byte (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
AND
ear,A
2
3
2
0
AND
eam,A
2+
5+(a)
0
2 × (b)
OR
A,#imm8
2
2
0
0
byte (A) ← (A) or imm8
-
-
-
-
-
*
*
R
-
-
OR
A,ear
2
3
1
0
byte (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
OR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
OR
ear,A
2
3
2
0
byte (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
OR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XOR
A,#imm8
2
2
0
0
byte (A) ← (A) xor imm8
-
-
-
-
-
*
*
R
-
-
XOR
A,ear
2
3
1
0
byte (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XOR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XOR
ear,A
2
3
2
0
byte (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XOR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOT
A
1
2
0
0
byte (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOT
ear
2
3
2
0
byte (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOT
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
ANDW
A
1
2
0
0
word (A) ← (AH) and (A)
-
-
-
-
-
*
*
R
-
-
ANDW
A,#imm16
3
2
0
0
word (A) ← (A) and imm16
-
-
-
-
-
*
*
R
-
-
ANDW
A,ear
2
3
1
0
word (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
word (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
word (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
0
word (A) ← (AH) or (A)
-
-
-
-
-
*
*
R
-
-
0
word (A) ← (A) or imm16
-
-
-
-
-
*
*
R
-
-
1
0
word (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
4+(a)
0
(c)
word (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
2
3
2
0
word (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XORW
A
1
2
0
0
word (A) ← (AH) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
A,#imm16
3
2
0
0
word (A) ← (A) xor imm16
-
-
-
-
-
*
*
R
-
-
XORW
A,ear
2
3
1
0
word (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
ear,A
2
3
2
0
ANDW
eam,A
2+
5+(a)
0
2 × (c)
ORW
A
1
2
0
ORW
A,#imm16
3
2
0
ORW
A,ear
2
3
ORW
A,eam
2+
ORW
ear,A
ORW
XORW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XORW
ear,A
2
3
2
0
word (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOTW
A
1
2
0
0
word (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOTW
ear
2
3
2
0
word (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOTW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
459
APPENDIX B Instructions
Table B.8-9 6 Logic 2 Instructions (Long Word)
Mnemonic
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
ANDL
A,ear
2
6
2
0
long (A) ← (A) and (ear)
Operation
-
-
-
-
-
*
*
R
-
RMW
-
ANDL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
ORL
A,ear
2
6
2
0
long (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
ORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
XORL
A,ear
2
6
2
0
long (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (d) in the table.
Table B.8-10 6 Sign Inversion Instructions (Byte, Word)
Mnemonic
NEG
A
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
1
2
0
0
byte (A) ← 0 - (A)
X
-
-
-
-
*
*
*
*
-
byte (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
byte (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
word (A) ← 0 - (A)
-
-
-
-
-
*
*
*
*
-
NEG
ear
2
3
2
0
NEG
eam
2+
5+(a)
0
2 × (b)
NEGW
A
1
2
0
0
NEGW
ear
2
3
2
0
NEGW
eam
2+
5+(a)
0
2 × (c)
Operation
word (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
word (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
Table B.8-11 1 Normalization Instruction (Long Word)
Mnemonic
NRML
A,R0
#
~
RG
B
2
*1
1
0
Operation
long (A) ← Shift left to the position where '1' is set
for the first time.
byte (R0) ← Shift count at that time
*1: 4 when all accumulators have a value of 0; otherwise, 6+(R0)
460
LH
AH
I
S
T
N
Z
V
C
RMW
-
-
-
-
-
-
*
-
-
-
APPENDIX B Instructions
Table B.8-12 18 Shift Instructions (Byte, Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RORC
Mnemonic
A
2
2
0
0
byte (A) ← Right rotation with carry
Operation
-
-
-
-
-
*
*
-
*
RMW
-
ROLC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
ear
2
3
2
0
byte (ear) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
*
ROLC
ear
2
3
2
0
byte (ear) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
*
ASR
A,R0
2
*1
1
0
byte (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSR
A,R0
2
*1
1
0
byte (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSL
A,R0
2
*1
1
0
byte (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRW
A
1
2
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSRW
A/SHRW A
1
2
0
0
word (A) ← Logical right shift (A, 1 bit)
-
-
-
-
*
R
*
-
*
-
LSLW
A/SHLW A
1
2
0
0
word (A) ← Logical left shift (A, 1 bit)
-
-
-
-
-
*
*
-
*
-
ASRW
A,R0
2
*1
1
0
word (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRW
A,R0
2
*1
1
0
word (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLW
A,R0
2
*1
1
0
word (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRL
A,R0
2
*2
1
0
long (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRL
A,R0
2
*2
1
0
long (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLL
A,R0
2
*2
1
0
long (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
*1: 6 when R0 is 0; otherwise, 5 + (R0)
*2: 6 when R0 is 0; otherwise, 6 + (R0)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table.
461
APPENDIX B Instructions
Table B.8-13 31 Branch 1 Instructions
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
BZ/BEQ
Mnemonic
rel
2
*1
0
0
Branch on (Z) = 1
Operation
-
-
-
-
-
-
-
-
-
RMW
-
BNZ/
BNE
rel
2
*1
0
0
Branch on (Z) = 0
-
-
-
-
-
-
-
-
-
-
BC/BLO
rel
2
*1
0
0
Branch on (C) = 1
-
-
-
-
-
-
-
-
-
-
BNC/
BHS
rel
2
*1
0
0
Branch on (C) = 0
-
-
-
-
-
-
-
-
-
-
BN
rel
2
*1
0
0
Branch on (N) = 1
-
-
-
-
-
-
-
-
-
-
BP
rel
2
*1
0
0
Branch on (N) = 0
-
-
-
-
-
-
-
-
-
-
BV
rel
2
*1
0
0
Branch on (V) = 1
-
-
-
-
-
-
-
-
-
-
BNV
rel
2
*1
0
0
Branch on (V) = 0
-
-
-
-
-
-
-
-
-
-
BT
rel
2
*1
0
0
Branch on (T) = 1
-
-
-
-
-
-
-
-
-
-
BNT
rel
2
*1
0
0
Branch on (T) = 0
-
-
-
-
-
-
-
-
-
-
BLT
rel
2
*1
0
0
Branch on (V) xor (N) = 1
-
-
-
-
-
-
-
-
-
-
BGE
rel
2
*1
0
0
Branch on (V) xor (N) = 0
-
-
-
-
-
-
-
-
-
-
BLE
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BGT
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BLS
rel
2
*1
0
0
Branch on (C) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BHI
rel
2
*1
0
0
Branch on (C) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BRA
rel
2
*1
0
0
Unconditional branch
-
-
-
-
-
-
-
-
-
-
JMP
@A
1
2
0
0
word (PC) ← (A)
-
-
-
-
-
-
-
-
-
-
JMP
addr16
3
3
0
0
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
JMP
@ear
2
3
1
0
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
JMP
@eam
2+
4+(a)
0
(c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
JMPP
@ear *3
2
5
2
0
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
JMPP
@eam *3
2+
6+(a)
0
(d)
JMPP
addr24
4
4
0
0
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
CALL
@ear *4
2
6
1
(c)
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
CALL
@eam *4
2+
7+(a)
0
2 × (c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
CALL
addr16 *5
3
6
0
(c)
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
CALLV
#vct4 *5
1
7
0
2 × (c)
Vector call instruction
-
-
-
-
-
-
-
-
-
-
CALLP
@ear *6
2
10
2
2 × (c)
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
CALLP
@eam *6
2+
11+(a)
0
*2
CALLP
addr24 *7
4
10
0
2 × (c)
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
*1: 4 when a branch is made; otherwise, 3
*2: 3 × (c) + (b)
*3: Read (word) of branch destination address
*4: W: Save to stack (word) R: Read (word) of branch destination address
*5: Save to stack (word)
*6: W: Save to stack (long word), R: Read (long word) of branch destination address
*7: Save to stack (long word)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
462
APPENDIX B Instructions
Table B.8-14 19 Branch 2 Instructions
Mnemonic
#
~
RG
B
LH
AH
I
S T N Z V C
CBNE
A,#imm8,rel
3
*1
0
0
Branch on byte (A) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
A,#imm16,rel
4
*1
0
0
Branch on word (A) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CBNE
ear,#imm8,rel
4
*2
1
0
Branch on byte (ear) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CBNE
eam,#imm8,rel *9
4+
*3
0
(b)
Branch on byte (eam) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
ear,#imm16,rel
5
*4
1
0
Branch on word (ear) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CWBNE
eam,#imm16,rel*9
5+
*3
0
(c)
Branch on word (eam) not equal to imm16
-
-
-
-
-
*
*
*
*
-
DBNZ
ear,rel
3
*5
2
0
byte (ear) ← (ear) - 1, Branch on (ear) not equal to 0
-
-
-
-
-
*
*
*
-
*
DBNZ
eam,rel
3+
*6
2
DWBNZ
ear,rel
3
*5
2
DWBNZ
eam,rel
3+
*6
2
INT
#vct8
2
20
INT
addr16
3
16
INTP
addr24
4
INT9
RETI
LINK
#imm8
UNLINK
Operation
2 × (b) byte (eam) ← (eam) - 1, Branch on (eam) not equal to 0
RMW
-
-
-
-
-
*
*
*
-
-
-
-
-
-
*
*
*
-
-
2 × (c) word (eam) ← (eam) - 1, Branch on (eam) not equal to 0
-
-
-
-
-
*
*
*
-
*
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
17
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
1
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
1
*8
0
*7
Return from interrupt
-
-
*
*
*
*
*
*
*
-
2
6
0
(c)
Saves the old frame pointer in the stack upon entering the
function, then sets the new frame pointer and reserves the
local pointer area.
-
-
-
-
-
-
-
-
-
-
1
5
0
(c)
Recovers the old frame pointer from the stack upon exiting
the function.
-
-
-
-
-
-
-
-
-
-
0
word (ear) ← (ear) - 1, Branch on (ear) not equal to 0
RET
*10
1
4
0
(c)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
RETP
*11
1
6
0
(d)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
*1: 5 when a branch is made; otherwise, 4
*2: 13 when a branch is made; otherwise, 12
*3: 7+(a) when a branch is made; otherwise, 6+(a)
*4: 8 when a branch is made; otherwise, 7
*5: 7 when a branch is made; otherwise, 6
*6: 8+(a) when a branch is made; otherwise, 7+(a)
*7: 3 × (b) + 2 × (c) when jumping to the next interruption request; 6 × (c) when returning from the current interruption
*8: 15 when jumping to the next interruption request; 17 when returning from the current interruption
*9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction.
*10: Return from stack (word)
*11: Return from stack (long word)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
463
APPENDIX B Instructions
Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
PUSHW
Mnemonic
A
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (A)
Operation
-
-
-
-
-
-
-
-
-
RMW
-
PUSHW
AH
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (AH)
-
-
-
-
-
-
-
-
-
-
PUSHW
PS
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (PS)
-
-
-
-
-
-
-
-
-
-
PUSHW
rlst
2
*3
*5
*4
(SP) ← (SP) - 2n, ((SP)) ← (rlst)
-
-
-
-
-
-
-
-
-
-
POPW
A
1
3
0
(c)
word (A) ← ((SP)), (SP) ← (SP) + 2
-
*
-
-
-
-
-
-
-
-
POPW
AH
1
3
0
(c)
word (AH) ← ((SP)), (SP) ← (SP) + 2
-
-
-
-
-
-
-
-
-
-
POPW
PS
1
4
0
(c)
word (PS) ← ((SP)), (SP) ← (SP) + 2
-
-
*
*
*
*
*
*
*
-
POPW
rlst
2
*2
*5
*4
(rlst) ← ((SP)), (SP) ← (SP) + 2n
-
-
-
-
-
-
-
-
-
-
JCTX
@A
1
14
0
6 × (c)
Context switch instruction
-
-
*
*
*
*
*
*
*
-
AND
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) and imm8
-
-
*
*
*
*
*
*
*
-
OR
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) or imm8
-
-
*
*
*
*
*
*
*
-
MOV
RP,#imm8
2
2
0
0
byte (RP) ← imm8
-
-
-
-
-
-
-
-
-
-
MOV
ILM,#imm8
2
2
0
0
byte (ILM) ← imm8
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,ear
2
3
1
0
word (RWi) ← ear
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,eam
2+
2+(a)
1
0
word (RWi) ← eam
-
-
-
-
-
-
-
-
-
-
MOVEA
A,ear
2
1
0
0
word (A) ← ear
-
*
-
-
-
-
-
-
-
-
MOVEA
A,eam
2+
1+(a)
0
0
word (A) ← eam
-
*
-
-
-
-
-
-
-
-
ADDSP
#imm8
2
3
0
0
word (SP) ← (SP) + ext(imm8)
-
-
-
-
-
-
-
-
-
-
ADDSP
#imm16
3
3
0
0
word (SP) ← (SP) + imm16
-
-
-
-
-
-
-
-
-
-
MOV
A,brg1
2
*1
0
0
byte (A) ← (brg1)
Z
*
-
-
-
*
*
-
-
-
MOV
brg2,A
-
2
1
0
0
byte (brg2) ← (A)
-
-
-
-
-
*
*
-
-
NOP
1
1
0
0
No operation
-
-
-
-
-
-
-
-
-
-
ADB
1
1
0
0
Prefix code for AD space access
-
-
-
-
-
-
-
-
-
-
DTB
1
1
0
0
Prefix code for DT space access
-
-
-
-
-
-
-
-
-
-
PCB
1
1
0
0
Prefix code for PC space access
-
-
-
-
-
-
-
-
-
-
SPB
1
1
0
0
Prefix code for SP space access
-
-
-
-
-
-
-
-
-
-
NCC
1
1
0
0
Prefix code for flag no-change
-
-
-
-
-
-
-
-
-
-
CMR
1
1
0
0
Prefix code for common register bank
-
-
-
-
-
-
-
-
-
-
*1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2
*2: 7 + 3 × (POP count) + 2 × (POP last register number), 7 when RLST = 0 (no transfer register)
*3: 29 + 3 × (PUSH count) - 3 × (PUSH last register number), 8 when RLST = 0 (no transfer register)
*4: (POP count) × (c) or (PUSH count) × (c)
*5: (POP count) or (PUSH count)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (c) in the table.
464
APPENDIX B Instructions
Table B.8-16 21 Bit Operand Instructions
Mnemonic
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
MOVB
A,dir:bp
3
5
0
(b)
byte (A) ← (dir:bp)b
Operation
Z
*
-
-
-
*
*
-
-
RMW
-
MOVB
A,addr16:bp
4
5
0
(b)
byte (A) ← (addr16:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,io:bp
3
4
0
(b)
byte (A) ← (io:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
dir:bp,A
3
7
0
2 × (b)
bit (dir:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
addr16:bp,A
4
7
0
2 × (b)
bit (addr16:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
io:bp,A
3
6
0
2 × (b)
bit (io:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
SETB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
*
CLRB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 0
-
-
-
-
-
-
-
-
-
CLRB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
CLRB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
BBC
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
io:bp,rel
4
*2
0
(b)
Branch on (io:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBS
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
io:bp,rel
4
*2
0
(b)
SBBS
addr16:bp,rel
5
*3
0
2 × (b)
Branch on (io:bp) b = 1
-
-
-
-
-
-
*
-
-
-
Branch on (addr16:bp) b = 1,
bit (addr16:bp) b ← 1
-
-
-
-
-
-
*
-
-
*
WBTS
io:bp
3
*4
0
WBTC
io:bp
3
*4
0
*5
Waits until (io:bp) b = 1
-
-
-
-
-
-
-
-
-
-
*5
Waits until (io:bp) b = 0
-
-
-
-
-
-
-
-
-
-
RMW
*1: 8 when a branch is made; otherwise, 7
*2: 7 when a branch is made; otherwise, 6
*3: 10 when the condition is met; otherwise, 9
*4: Undefined count
*5: Until the condition is met
Note:
See Table B.5-1 and Table B.5-2 for information on (b) in the table.
Table B.8-17 6 Accumulator Operation Instructions (Byte, Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
SWAP
Mnemonic
1
3
0
0
byte (A)0-7 ↔ (A)8-15
Operation
-
-
-
-
-
-
-
-
-
-
SWAPW
1
2
0
0
word (AH) ↔ (AL)
-
*
-
-
-
-
-
-
-
-
EXT
1
1
0
0
Byte sign extension
X
-
-
-
-
*
*
-
-
-
EXTW
1
2
0
0
Word sign extension
-
X
-
-
-
*
*
-
-
-
ZEXT
1
1
0
0
Byte zero extension
Z
-
-
-
-
R
*
-
-
-
ZEXTW
1
1
0
0
Word zero extension
-
Z
-
-
-
R
*
-
-
-
465
APPENDIX B Instructions
Table B.8-18 10 String Instructions
#
~
RG
B
MOVS / MOVSI
Mnemonic
2
*2
*5
*3
byte transfer @AH+ ← @AL+, counter = RW0
Operation
LH
AH
-
-
I
S
T
N
Z
V
C
RMW
-
-
-
-
-
-
-
-
MOVSD
2
*2
*5
*3
byte transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCEQ / SCEQI
2
*1
*8
*4
byte search @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCEQD
2
*1
*8
*4
byte search @AH- ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
FILS / FILSI
2
6m+6
*8
*3
byte fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
MOVSW / MOVSWI
2
*2
*5
*6
word transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
-
MOVSWD
2
*2
*5
*6
word transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCWEQ / SCWEQI
2
*1
*8
*7
word search @AH+ - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCWEQD
2
*1
*8
*7
word search @AH- - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
FILSW / FILSWI
2
6m+6
*8
*6
word fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
*1: 5 when RW0 is 0, 4 + 7 × (RW0) when the counter expires, or 7n + 5 when a match occurs
*2: 5 when RW0 is 0; otherwise, 4 + 8 × (RW0)
*3: (b) × (RW0) + (b) × (RW0) When the source and destination access different areas, calculate the (b) item individually.
*4: (b) × n
*5: 2 × (b) × (RW0)
*6: (c) × (RW0) + (c) × (RW0) When the source and destination access different areas, calculate the (c) item individually.
*7: (c) × n
*8: (b) × (RW0)
Note:
m: RW0 value (counter value), n: Loop count
See Table B.5-1 and Table B.5-2 for information on (b) and (c) in the table.
466
APPENDIX B Instructions
B.9
Instruction Map
Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction
map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F2MC-16LX
instruction map.
■
Structure of Instruction Map
Figure B.9-1 Structure of Instruction Map
Basic page map
Bit operation
instructions
Character string
operation
instructions
2-byte
instructions
: Byte 1
ea instructions × 9 : Byte 2
An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An
instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it
references byte 1, and can check the following one byte by referencing the map for byte 2. Figure B.9-2
shows the correspondence between an actual instruction code and instruction map.
467
APPENDIX B Instructions
Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map
Some instructions do
not contain byte 2.
Instruction
code
Length varies
depending on the
instruction.
Byte 1
Byte 2
Operand
Operand
...
[Basic page map]
XY
+Z
[Extended page map]*
UV
+W
*: The extended page map is a generic name of maps for bit operation instructions, character
string operation instructions, 2-byte instructions, and ea instructions. Actually, there are
multiple extended page maps for each type of instructions.
An example of an instruction code is shown in Table B.9-1.
Table B.9-1 Example of an Instruction Code
Byte 1
(from basic page map)
Byte 2
(from extended page map)
NOP
00 +0=00
-
AND A, #8
30 +4=34
-
MOV A, ADB
60 +F=6F
00 +0=00
@RW2+d8, #8, rel
70 +0=70
F0 +2=F2
Instruction
468
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
A
ZEXT
SWAP
ADDSP
DTB
ADB
SPB
#8
A, #8
dir, A
A, dir
io, A
A, io
JMP
BRA
60
MULU
DIVU
ea
@A instruction 2
A
MOVW
MOVX
RET
SP, A A, addr16
A0
B0
C0
ea
instruction 8
D0
E0
rel
rel
LSRW
ASRW
LSLW
SWAPW
ZEXTW
XORW
ORW
ANDW
ORW
PUSHW
POPW
A, #16
AH
AH
MOVW
ea, RWi
Bit operation MOV
A instruction
ea, Ri
MOVW
RWi, ea
PUSHW
POPW
2-byte
XCHW
A
rlst
rlst instruction
RWi, ea
Character
XORW
PUSHW
POPW
XCH
operation
A
A, #16
PS
PS string
Ri, ea
instruction
A
ANDW
PUSHW
POPW
A
A, #16
A
CMPW
MOVL
MOVW
RETI
A, #16
A, #32 addr16, A
ADDSP
MULUW
NOTW
A
#16
A
A
A
EXTW
A
BHI
BLS
BGT
BLE
rel
rel
rel
rel
rel
BGE
CMPL
CMPW
A, #32
NEGW
A
rel
rel
rel
rel
rel
rel
BLT
BT
BNV
BV
BP
BN
BNC/BHS
rel
BC/BLO
BNZ/BNE
rel
BZ/BEQ
MOV
MOV
CBNE A, CWBNE A, MOVW
MOVW
INTP
MOV
RP, #8
ILM, #8
#8, rel
#16, rel
A, #16 A,addr16
addr24
Ri, ea
#4
F0
rel
ADDW
MOVW
MOVW
INT
ea
MOVW
MOVW
MOVW
MOV A,
MOVW
A, #16
A, dir
A, io
#vct8 instruction 9
A, RWi
RWi, A RWi, #16 @RWi+d8 @RWi+d8, A
NOT
ea
instruction 7
MOVX
MOVX
CALLP
ea
A, dir
A, io
addr24 instruction 6
MOVW
MOVW
RETP
A, #8
A, SP
io, #16
A, #8
90
BNT
SUBL
SUBW
A, #32
A
A
A
XOR
OR
OR
CCR, #8
80
ea
MOV
MOV
MOV
MOV
MOVX A, MOV
CALL
rel instruction 1
A, Ri
Ri, A
Ri, #8
A, Ri @RWi+d8
A, #4
70
MOV
JMP
ea
A, addr16
addr16 instruction 3
MOV
MOV
50
MOVX
MOV
JMPP
ea
A, #8
A, #8 addr16, A
addr24 instruction 4
MOV
MOV
MOV
40
SUBW
MOVW
MOVW
INT
MOVEA
A
A, #16
dir, A
io, A
addr16
RWi, ea
UNLINK
A
CMP
A
A, #8
A, #8
SUBC
SUB
ADD
30
AND
AND
MOV
MOV
CALL
ea
CCR, #8
A, #8
dir, #8
io, #8
addr16 instruction 5
CMP
A
A, dir
A, dir
ADDC
SUB
ADD
20
LINK
ADDL
ADDW
#imm8
A, #32
EXT
@A
PCB
A
JCTX
SUBDC
ADDDC
NEG
NCC
INT9
A
CMR
10
NOP
00
APPENDIX B Instructions
Table B.9-2 Basic Page Map
469
470
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
10
MOVB
io:bp, A
20
30
CLRB
io:bp
40
50
SETB
io:bp
60
70
BBC
io;bp, rel
80
90
BBS
io:bp, rel
A0
B0
MOVB
MOVB A, MOVB
MOVB
CLRB
CLRB
SETB
SETB
BBC
BBC
BBS
BBS
A, dir:bp addr16:bp
dir:bp, A addr16:bp,A
dir:bp addr16:bp
dir:bp addr16:bp dir:bp, rel addr16:bp,rel dir:bp, rel addr16:bp,rel
MOVB
A, io:bp
00
WBTS
io:bp
C0
D0
WBTC
io:bp
E0
SBBS
addr16:bp
F0
APPENDIX B Instructions
Table B.9-3 Bit Operation Instruction Map (First Byte = 6CH)
MOVSI
MOVSD
PCB, PCB
PCB, DTB
PCB, ADB
PCB, SPB
DTB, PCB
DTB, DTB
DTB, ADB
DTB, SPB
ADB, PCB
ADB, DTB
ADB, ADB
ADB, SPB
SPB, PCB
SPB, DTB
SPB, ADB
SPB, SPB
+1
+2
+3
+4
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
10
+0
00
MOVSWI
20
MOVSWD
30
40
50
60
70
90
A0
B0
C0
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SCEQI
SCEQD
SCWEQI SCWEQD FILSI
PCB
PCB
PCB
PCB
PCB
80
D0
FILSI
SPB
ADB
DTB
PCB
E0
F0
APPENDIX B Instructions
Table B.9-4 Character String Operation Instruction Map (First Byte = 6EH)
471
472
LSLW
LSLL
LSL
MOVW
MOVW
A, R0
A, R0
A, R0 @RL2+d8, A A, @RL2+d8
MOVW
MOVW
NRML
A, @A @AL, AH
A, R0
ASRW
ASRL
ASR
MOVW
MOVW
A, R0
A, R0
A, R0 @RL3+d8, A A, @RL3+d8
LSRW
LSRL
LSR
A, R0
A, R0
A, R0
+D
+E
+F
MOVW
MOVW
@RL1+d8, A A, @RL1+d8
MOVW
MOVW
@RL0+d8, A A, @RL0+d8
+C
+B
+A
+9
+8
A
MOV
MOV
MOVX
MOV
MOV
A, PCB
A, @A A, @RL3+d8 @RL3+d8, A A, @RL3+d8
+6
ROLC
MOV
MOV
A, @A @AL, AH
+5
A
MOV
MOV
MOVX
MOV
MOV
A, DPR
DPR, A A, @RL2+d8 @RL2+d8, A A, @RL2+d8
+4
ROLC
MOV
MOV
A, USB
USB, A
+3
+7
MOV
MOV
MOVX
MOV
MOV
A, SSB
SSB, A A, @RL1+d8 @RL1+d8, A A, @RL1+d8
+2
40
MOV
MOV
A, ADB
ADB, A
30
+1
20
MOV
MOV
MOVX
MOV
MOV
A, DTB
DTB, A A, @RL0+d8 @RL0+d8, A A, @RL0+d8
10
+0
00
50
DIVU
MULW
MUL
60
A
A
A
70
80
90
A0
B0
C0
D0
E0
F0
APPENDIX B Instructions
Table B.9-5 2-byte Instruction Map (First Byte = 6FH)
50
90
B0
D0
@RW1, @RW1+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
@RW2, @RW2+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
@RW3, @RW3+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
SUBL
SUBL A,
A, RL2 @RW5+d8
SUBL
SUBL A,
A, RL3 @RW6+d8
SUBL
SUBL A,
A, RL3 @RW7+d8
ADDL
ADDL A,
A, RL2 @RW5+d8
ADDL
ADDL A,
A, RL3 @RW6+d8
ADDL
ADDL A,
A, RL3 @RW7+d8
ADDL
ADDL A, SUBL
SUBL A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ADDL
ADDL A, SUBL
SUBL A, Use
@RW0+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW0+RW7
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
#16, rel A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
,#8, rel
ADDL
ADDL A, SUBL
SUBL A, Use
@RW1+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW1+RW7
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
#16, rel A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
,#8, rel
ADDL
ADDL A,
A,@RW2+ @PC+d16
ADDL
ADDL A, SUBL
SUBL A, Use
A,@RW3+
addr16 A,@RW3+
addr16 prohibited
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
SUBL
SUBL A,
A,@RW2+ @PC+d16
@RW0, @RW0+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
SUBL
SUBL A,
A, RL2 @RW4+d8
Use
prohibited
ANDL
ANDL A,
A,@RW2+ @PC+d16
ANDL
ANDL A,
A, RL3 @RW7+d8
ANDL
ANDL A,
A, RL3 @RW6+d8
ANDL
ANDL A,
A, RL2 @RW5+d8
ANDL
ANDL A,
A, RL2 @RW4+d8
ORL
ORL A,
A,@RW2+ @PC+d16
ORL
ORL A,
A, RL3 @RW7+d8
ORL
ORL A,
A, RL3 @RW6+d8
ORL
ORL A,
A, RL2 @RW5+d8
ORL
ORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A,@RW2+ @PC+d16
XORL
XORL A,
A, RL3 @RW7+d8
XORL
XORL A,
A, RL3 @RW6+d8
XORL
XORL A,
A, RL2 @RW5+d8
XORL
XORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A, RL1 @RW3+d8
addr16,
,#8, rel
Use
@PC+d16,
prohibited
,#8, rel
@RW3, @RW3+d16
#8, rel
,#8, rel
@RW2, @RW2+d16
#8, rel
,#8, rel
@RW1, @RW1+d16
#8, rel
,#8, rel
@RW0, @RW0+d16
#8, rel
,#8, rel
R7, @RW7+d8,
#8, rel
#8, rel
R6, @RW6+d8,
#8, rel
#8, rel
R5, @RW5+d8,
#8, rel
#8, rel
R4, @RW4+d8,
#8, rel
#8, rel
R3, @RW3+d8,
#8, rel
#8, rel
addr16, CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
#16, rel A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 prohibited
@PC+d16, CMPL
CMPL A,
#16, rel A,@RW2+ @PC+d16
RW7, @RW7+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW7+d8
RW6, @RW6+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW6+d8
RW5, @RW5+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW5+d8
RW4, @RW4+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW4+d8
ORL
ORL A,
A, RL1 @RW3+d8
R2, @RW2+d8,
#8, rel
#8, rel
R1, @RW1+d8,
#8, rel
#8, rel
ADDL
ADDL A,
A, RL2 @RW4+d8
ANDL
ANDL A,
A, RL1 @RW3+d8
XORL
XORL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW1+d8
+4
RW3, @RW3+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW3+d8
ORL
ORL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW1+d8
SUBL
SUBL A,
A, RL1 @RW3+d8
ANDL
ANDL A,
A, RL1 @RW2+d8
ANDL
ANDL A,
A, RL0 @RW1+d8
ADDL
ADDL A,
A, RL1 @RW3+d8
RW2, @RW2+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW2+d8
RW1, @RW1+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW1+d8
+3
CBNE ↓
F0
R0, @RW0+d8,
#8, rel
#8, rel
CBNE ↓
E0
SUBL
SUBL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW0+d8
C0
ADDL
ADDL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW0+d8
A0
+2
ANDL
ANDL A,
A, RL0 @RW0+d8
80
SUBL
SUBL A,
A, RL0 @RW1+d8
70
ADDL
ADDL A,
A, RL0 @RW1+d8
60
RW0, @RW0+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW0+d8
CWBNE ↓ CWBNE ↓
40
+1
30
+0
20
SUBL
SUBL A,
A, RL0 @RW0+d8
10
ADDL
ADDL A,
A, RL0 @RW0+d8
00
APPENDIX B Instructions
Table B.9-6 ea Instruction 1 (First Byte = 70H)
473
474
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW7+d8
@RL3 @@RW7+d8
RL3 @RW7+d8
RL3 @RW7+d8
A, RL3 @RW7+d8
RL3, A @RW7+d8,A
R7, #8 @RW7+d8,#8
A, RW7 @RW7+d8
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #8 @RW0+d16,#8
A,@RW0 @RW0+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1,A @RW1+d16,A @RW1, #8 @RW1+d16,#8
A,@RW1 @RW1+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2,A @RW2+d16,A @RW2, #8 @RW2+d16,#8
A,@RW2 @RW2+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3,A @RW3+d16,A @RW3, #8 @RW3+d16,#8
A,@RW3 @RW3+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+,A @RW0+RW7,A @RW0+, #8 @RW0+RW7,#8 A,@RW0+ @RW0+RW7
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+,A @RW1+RW7,A @RW1+, #8 @RW1+RW7,#8 A,@RW1+ @RW1+RW7
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+,A @PC+d16, A @RW2+, #8 @PC+d16, #8 A,@RW2+ @PC+d16
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+,A
addr16, A @RW3+, #8
addr16, #8 A,@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW6+d8
@RL3 @@RW6+d8
RL3 @RW6+d8
RL3 @RW6+d8
A, RL3 @RW6+d8
RL3, A @RW6+d8,A
R6, #8 @RW6+d8,#8
A, RW6 @RW6+d8
D0
+6
C0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW5+d8
@RL2 @@RW5+d8
RL2 @RW5+d8
RL2 @RW5+d8
A, RL2 @RW5+d8
RL2, A @RW5+d8,A
R5, #8 @RW5+d8,#8
A, RW5 @RW5+d8
B0
+5
A0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW4+d8
@RL2 @@RW4+d8
RL2 @RW4+d8
RL2 @RW4+d8
A, RL2 @RW4+d8
RL2, A @RW4+d8,A
R4, #8 @RW4+d8,#8
A, RW4 @RW4+d8
90
+4
80
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW3+d8
@RL1 @@RW3+d8
RL1 @RW3+d8
RL1 @RW3+d8
A, RL1 @RW3+d8
RL1, A @RW3+d8,A
R3, #8 @RW3+d8,#8
A, RW3 @RW3+d8
70
+3
60
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW2+d8
@RL1 @@RW2+d8
RL1 @RW2+d8
RL1 @RW2+d8
A, RL1 @RW2+d8
RL1, A @RW2+d8,A
R2, #8 @RW2+d8,#8
A, RW2 @RW2+d8
50
+2
40
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW1+d8
@RL0 @@RW1+d8
RL0 @RW1+d8
RL0 @RW1+d8
A, RL0 @RW1+d8
RL0, A @RW1+d8,A
R1, #8 @RW1+d8,#8
A, RW1 @RW1+d8
30
+1
20
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW0+d8
@RL0 @@RW0+d8
RL0 @RW0+d8
RL0 @RW0+d8
A, RL0 @RW0+d8
RL0, A @RW0+d8,A
R0, #8 @RW0+d8,#8
A, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-7 ea Instruction 2 (First Byte = 71H)
D0
E0
F0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A A,@RW3+
addr16 A,@RW3+
addr16
+D
+E
+F
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R7 @RW7+d8
A, R7 @RW7+d8
R7, A @RW7+d8,A
A, R7 @RW7+d8
A, R7 @RW7+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R6 @RW6+d8
A, R6 @RW6+d8
R6, A @RW6+d8,A
A, R6 @RW6+d8
A, R6 @RW6+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R5 @RW5+d8
A, R5 @RW5+d8
R5, A @RW5+d8,A
A, R5 @RW5+d8
A, R5 @RW5+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R4 @RW4+d8
A, R4 @RW4+d8
R4, A @RW4+d8,A
A, R4 @RW4+d8
A, R4 @RW4+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R3 @RW3+d8
A, R3 @RW3+d8
R3, A @RW3+d8,A
A, R3 @RW3+d8
A, R3 @RW3+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R2 @RW2+d8
A, R2 @RW2+d8
R2, A @RW2+d8,A
A, R2 @RW2+d8
A, R2 @RW2+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R1 @RW1+d8
A, R1 @RW1+d8
R1, A @RW1+d8,A
A, R1 @RW1+d8
A, R1 @RW1+d8
+C
INC
DEC
R7 @RW7+d8
C0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ROLC
RORC
RORC
INC
R7 @RW7+d8
R7 @RW7+d8
ROLC
INC
DEC
R6 @RW6+d8
B0
+B
ROLC
RORC
RORC
INC
R6 @RW6+d8
R6 @RW6+d8
ROLC
INC
DEC
R5 @RW5+d8
A0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ROLC
RORC
RORC
INC
R5 @RW5+d8
R5 @RW5+d8
ROLC
INC
DEC
R4 @RW4+d8
90
+A
ROLC
RORC
RORC
INC
R4 @RW4+d8
R4 @RW4+d8
ROLC
INC
DEC
R3 @RW3+d8
INC
DEC
R2 @RW2+d8
INC
DEC
R1 @RW1+d8
80
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R0 @RW0+d8
A, R0 @RW0+d8
R0, A @RW0+d8,A
A, R0 @RW0+d8
A, R0 @RW0+d8
70
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ROLC
RORC
RORC
INC
R3 @RW3+d8
R3 @RW3+d8
ROLC
60
INC
DEC
R0 @RW0+d8
50
+9
ROLC
RORC
RORC
INC
R2 @RW2+d8
R2 @RW2+d8
ROLC
40
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0, A @RW0+d16,A
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ROLC
RORC
RORC
INC
R1 @RW1+d8
R1 @RW1+d8
ROLC
30
ROLC
RORC
RORC
INC
R0 @RW0+d8
R0 @RW0+d8
20
ROLC
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX B Instructions
Table B.9-8 ea Instruction 3 (First Byte = 72H)
475
476
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16 @RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, #16 @RW3+d16,#16 A,@RW3 @RW3+d16
+B
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A @RW3+, #16
addr16, #16 A,@RW3+
addr16
INCW @
+F
INCW
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16 @RW2+ @@PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A @RW2+, #16 @PC+d16, #16 A,@RW2+ @PC+d16
CALL @
+E
CALL
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, #16 @RW1+RW7,#16 A,@RW1+ @RW1+RW7
XCHW
XCHW A,
A, RW7 @RW7+d8
XCHW
XCHW A,
A, RW6 @RW6+d8
XCHW
XCHW A,
A, RW5 @RW5+d8
+D @@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7
INCW @
MOVW
MOVW
RW7, #16 @RW7+d8,#16
MOVW
MOVW
RW6, #16 @RW6+d8,#16
MOVW
MOVW
RW5, #16 @RW5+d8,#16
XCHW
XCHW A,
A, RW4 @RW4+d8
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, #16 @RW0+RW7,#16 A,@RW0+ @RW0+RW7
INCW
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW7 @RW7+d8
RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, A @RW7+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW6 @RW6+d8
RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, A @RW6+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW5 @RW5+d8
RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, A @RW5+d8,A
MOVW
MOVW
RW4, #16 @RW4+d8,#16
+C @@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7
JMP @
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16 @RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, #16 @RW2+d16,#16 A,@RW2 @RW2+d16
+A
JMP
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16 @RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, #16 @RW1+d16,#16 A,@RW1 @RW1+d16
+9
CALL @
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16 @RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #16 @RW0+d16,#16 A,@RW0 @RW0+d16
+8
CALL
CALL
CALL
RW7 @@RW7+d8
JMP
JMP
@RW7 @@RW7+d8
+7
JMP @
CALL
CALL
RW6 @@RW6+d8
JMP
JMP
@RW6 @@RW6+d8
+6
JMP
CALL
CALL
RW5 @@RW5+d8
JMP
JMP
@RW5 @@RW5+d8
+5
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW4 @RW4+d8
RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, A @RW4+d8,A
XCHW
XCHW A,
A, RW3 @RW3+d8
XCHW
XCHW A,
A, RW2 @RW2+d8
XCHW
XCHW A,
A, RW1 @RW1+d8
CALL
CALL
RW4 @@RW4+d8
MOVW
MOVW
RW3, #16 @RW3+d8,#16
MOVW
MOVW
RW2, #16 @RW2+d8,#16
MOVW
MOVW
RW1, #16 @RW1+d8,#16
JMP
JMP
@RW4 @@RW4+d8
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW3 @RW3+d8
RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, A @RW3+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW2 @RW2+d8
RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, A @RW2+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW1 @RW1+d8
RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, A @RW1+d8,A
+4
F0
XCHW
XCHW A,
A, RW0 @RW0+d8
E0
CALL
CALL
RW3 @@RW3+d8
D0
MOVW
MOVW
RW0, #16 @RW0+d8,#16
C0
JMP
JMP
@RW3 @@RW3+d8
B0
+3
A0
CALL
CALL
RW2 @@RW2+d8
90
JMP
JMP
@RW2 @@RW2+d8
80
+2
70
CALL
CALL
RW1 @@RW1+d8
60
JMP
JMP
@RW1 @@RW1+d8
50
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW0 @RW0+d8
RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, A @RW0+d8,A
40
+1
30
CALL
CALL
RW0 @@RW0+d8
20
JMP
JMP
@RW0 @@RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-9 ea Instruction 4 (First Byte = 73H)
ADD
A, SUB
SUB
SUB
ADDC
A, ADDC
A,
ADDC
ADDC A,
A, CMP
CMP
CMP
CMP
A,
A,
A, AND
AND
AND
AND
AND
AND
A,
A,
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r PC+d16, r
+F A,@RW3+
ADD
ADD
SUB
SUB
ADDC
ADDC
CMP
CMP
AND
AND
OR
OR
XOR
XOR
DBNZ
DBNZ
A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+
A, addr16 A,@RW3+ A, addr16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ADD
SUB
CMP
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW1+ @RW1+RW7 @RW1+, r W1+RW7, r
A,
CMP
OR
OR
A,
A,@RW1+ @RW1+RW7
ADD
ADD
ADDC A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ADDC
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW0+ @RW0+RW7 @RW0+, r W0+RW7, r
A,
OR
OR
A,
A,@RW0+ @RW0+RW7
SUB
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
SUB
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW3 @RW3+d16 @RW3, r W3+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
A,
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW2 @RW2+d16 @RW2, r W2+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW1 @RW1+d16 @RW1, r W1+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW0 @RW0+d16 @RW0, r W0+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
R7, r RW7+d8, r
ADD
F0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
R6, r RW6+d8, r
E0
ADD
D0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
R5, r RW5+d8, r
C0
ADD
B0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
R4, r RW4+d8, r
A0
ADD
90
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
R3, r RW3+d8, r
80
ADD
70
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
R2, r RW2+d8, r
60
ADD
50
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
R1, r RW1+d8, r
40
ADD
30
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
R0, r RW0+d8, r
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX B Instructions
Table B.9-10 ea Instruction 5 (First Byte = 74H)
477
478
NOT
NOT
R2 @RW2+d8
SUB
SUB
SUB
SUB
ADD
SUB
SUB
@RW1+RW7,A @RW1+, A @RW1+RW7,A
ADD @R
@RW0+RW7,A @RW0+, A @RW0+RW7,A
ADD @R
+F
ADD
ADD
@RW3+, A addr16, A
SUB
SUB
@RW3+, A addr16, A
+E @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
ADD
+D @RW1+, A
ADD
+C @RW0+, A
ADD
NOT
NOT
@RW1+ @RW1+RW7
NOT
NOT
@RW0+ @RW0+RW7
SUBC
SUBC A, NEG
NEG A,
AND
AND
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
OR
OR
@RW3+, A addr16, A
XOR
XOR
@RW3+, A addr16, A
NOT
NOT
@RW3+
addr16
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
NOT
NOT
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+ @PC+d16
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A
NOT
NOT
@RW3 @RW3+d16
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
+B
XOR
NOT
NOT
R7, A @RW7+d8, A
R7 @RW7+d8
XOR
NOT
NOT
R6, A @RW6+d8, A
R6 @RW6+d8
XOR
NOT
NOT
R5, A @RW5+d8, A
R5 @RW5+d8
XOR
NOT
NOT
R4, A @RW4+d8, A
R4 @RW4+d8
XOR
NOT
NOT
R3, A @RW3+d8, A
R3 @RW3+d8
XOR
R2, A @RW2+d8,A
XOR
NOT
NOT
R1, A @RW1+d8, A
R1 @RW1+d8
NOT
NOT
@RW2 @RW2+d16
XOR
F0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
NEG A,
AND
AND
OR
OR
R7 @RW7+d8
R7, A @RW7+d8, A
R7, A @RW7+d8, A
XOR
XOR
XOR
XOR
XOR
XOR
E0
XOR
NOT
NOT
R0, A @RW0+d8, A
R0 @RW0+d8
D0
+A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R7, A @RW7+d8, A
R7, A @RW7+d8, A
A, R7 @RW7+d8
ADD
NEG A,
AND
AND
OR
OR
R6 @RW6+d8
R6, A @RW6+d8, A
R6, A @RW6+d8, A
NEG A,
AND
AND
OR
OR
R5 @RW5+d8
R5, A @RW5+d8, A
R5, A @RW5+d8, A
NEG A,
AND
AND
OR
OR
R4 @RW4+d8
R4, A @RW4+d8, A
R4, A @RW4+d8, A
NEG A,
AND
AND
OR
OR
R3 @RW3+d8
R3, A @RW3+d8, A
R3, A @RW3+d8, A
NEG A,
AND
AND
OR
OR
R2 @RW2+d8
R2, A @RW2+d8,A
R2, A @RW2+d8,A
NEG A,
AND
AND
OR
OR
R1 @RW1+d8
R1, A @RW1+d8, A
R1, A @RW1+d8, A
XOR
C0
NOT
NOT
@RW1 @RW1+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R6, A @RW6+d8, A
R6, A @RW6+d8, A
A, R6 @RW6+d8
ADD
B0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R5, A @RW5+d8, A
R5, A @RW5+d8, A
A, R5 @RW5+d8
ADD
A0
+9
ADD
SUB
SUB
SUBC
SUBC A, NEG
R4, A @RW4+d8, A
R4, A @RW4+d8, A
A, R4 @RW4+d8
ADD
90
NOT
NOT
@RW0 @RW0+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R3, A @RW3+d8, A
R3, A @RW3+d8, A
A, R3 @RW3+d8
ADD
80
NEG A,
AND
AND
OR
OR
R0 @RW0+d8
R0, A @RW0+d8, A
R0, A @RW0+d8, A
70
ADD
ADD
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R2, A @RW2+d8,A
R2, A @RW2+d8,A
A, R2 @RW2+d8
60
ADD
50
ADD
SUB
SUB
SUBC
SUBC A, NEG
R1, A @RW1+d8, A
R1, A @RW1+d8, A
A, R1 @RW1+d8
40
ADD
30
ADD
SUB
SUB
SUBC
SUBC A, NEG
R0, A @RW0+d8, A
R0, A @RW0+d8, A
A, R0 @RW0+d8
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX B Instructions
Table B.9-11 ea Instruction 6 (First Byte = 75H)
ADDW A, SUBW
ADDW
ADDCW
CMPW
ADDCW A, CMPW
ADDCW A,
ANDW
CMPW A, ANDW
CMPW A,
ORW
ORW
ANDW A, ORW
ANDW A,
ANDW A,
ORW
ORW
ORW
A,
A,
A, XORW
XORW A, DWBNZ
DWBNZ
+F A,@RW3+
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
addr 16 A,@RW3+ addr 16
A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr16 A,@RW3+
addr 16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r @PC+d16,r
SUBW A, ADDCW
SUBW A,
ANDW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW1+ @RW1+RW7 @RW1+, r @RW1+RW7,r
SUBW
ADDW A,
ADDW
CMPW A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
CMPW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW0+ @RW0+RW7 @RW0+, r @RW0+RW7,r
ADDCW A,
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ADDCW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW3 @RW3+d16 @RW3, r @RW3+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
SUBW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW2 @RW2+d16 @RW2, r @RW2+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
SUBW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW1 @RW1+d16 @RW1, r @RW1+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADDW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW0 @RW0+d16 @RW0, r @RW0+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
ADDW
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, r @RW7+d8,r
F0
+7
E0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, r @RW6+d8,r
D0
+6
C0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, r @RW5+d8,r
B0
+5
A0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, r @RW4+d8,r
90
+4
80
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, r @RW3+d8,r
70
+3
60
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, r @RW2+d8,r
50
+2
40
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, r @RW1+d8,r
30
+1
20
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, r @RW0+d8,r
10
+0
00
APPENDIX B Instructions
Table B.9-12 ea Instruction 7 (First Byte = 76H)
479
480
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
@RW3 @RW3+d16
SUBW
SUBW
@RW3+, A addr16, A
ADDW
ADDW
@RW3+, A addr16, A
+F
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
ORW
ORW
@RW3+, A addr16, A
XORW
XORW
@RW3+, A addr16, A
NOTW
NOTW
@RW3+
addr16
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
@RW2+ @PC+d16
SUBW
SUBW
@RW2+, A @PC+d16,A
ADDW
ADDW
@RW2+, A @PC+d16,A
+E
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+ @RW1+RW7
SUBCW
+D
SUBW
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+ @RW0+RW7
SUBW
SUBCW
+C
ADDW
ADDW
SUBW
SUBCW A,
+B @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
SUBW
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
@RW2 @RW2+d16
ADDW
ADDW
SUBW
+A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
SUBW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
@RW1 @RW1+d16
ADDW
ADDW
SUBCW A,
+9 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
@RW0 @RW0+d16
SUBW
NOTW
NOTW
RW7 @RW7+d8
NOTW
NOTW
RW6 @RW6+d8
NOTW
NOTW
RW5 @RW5+d8
+8 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
SUBW
XORW
XORW
RW7, A @RW7+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
A, RW7 @RW7+d8
RW7 @RW7+d8
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
+7
ADDW
XORW
XORW
RW6, A @RW6+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
A, RW6 @RW6+d8
RW6 @RW6+d8
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
+6
ADDW
XORW
XORW
RW5, A @RW5+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
A, RW5 @RW5+d8
RW5 @RW5+d8
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
+5
NOTW
NOTW
RW4 @RW4+d8
XORW
XORW
RW4, A @RW4+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
A, RW4 @RW4+d8
RW4 @RW4+d8
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
+4
F0
NOTW
NOTW
RW0 @RW0+d8
E0
NOTW
NOTW
RW3 @RW3+d8
D0
XORW
XORW
RW3, A @RW3+d8, A
C0
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
A, RW3 @RW3+d8
RW3 @RW3+d8
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
B0
+3
A0
NOTW
NOTW
RW2 @RW2+d8
90
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
A, RW2 @RW2+d8
RW2 @RW2+d8
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
80
+2
70
NOTW
NOTW
RW1 @RW1+d8
60
XORW
XORW
RW1, A @RW1+d8, A
50
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
A, RW1 @RW1+d8
RW1 @RW1+d8
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
40
+1
30
XORW
XORW
RW0, A @RW0+d8, A
20
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
A, RW0 @RW0+d8
RW0 @RW0+d8
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
10
+0
00
APPENDIX B Instructions
Table B.9-13 ea Instruction 8 (First Byte = 77H)
DIV
DIV
A, DIVW
DIVW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
DIV
DIV
A, DIVW
DIVW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW MULUW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MULU
MULU A, MULUW MULUW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MULU
MULU A, MULUW MULUW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
+9
+A
+B
+C
+D
+E
+F A, @RW3+
MULU
DIV
DIV
A, DIVW
DIVW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
addr16 A,@RW3+ addr16
A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
A, DIVW
DIVW A,
addr16 A,@RW3+
addr16
DIV
DIV
A, DIVW
DIVW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
F0
+7
E0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
D0
+6
C0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
B0
+5
A0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
90
+4
80
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
70
+3
60
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
50
+2
40
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
30
+1
20
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-14 ea Instruction 9 (First Byte = 78H)
481
482
MOVEA
MOVEA RW1
RW1,RW4 ,@RW4+d8
MOVEA
MOVEA RW1
RW1,RW5 ,@RW5+d8
MOVEA
MOVEA RW1
RW1,RW6 ,@RW6+d8
MOVEA
MOVEA RW1
RW1,RW7 ,@RW7+d8
MOVEA
MOVEA RW1
RW1,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,@RW1 ,@RW1+d16
MOVEA
MOVEA RW1
RW1,@RW2 ,@RW2+d16
MOVEA
MOVEA RW1
RW1,@RW3 ,@RW3+d16
MOVEA
MOVEA RW0
RW0,RW4 ,@RW4+d8
MOVEA
MOVEA RW0
RW0,RW5 ,@RW5+d8
MOVEA
MOVEA RW0
RW0,RW6 ,@RW6+d8
MOVEA
MOVEA RW0
RW0,RW7 ,@RW7+d8
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
+4
+5
+6
+7
50
70
90
B0
C0
D0
F0
MOVEA
MOVEA RW3
RW3,@RW2+ ,@PC+d16
MOVEA
MOVEA RW4
RW4,@RW2+ ,@PC+d16
MOVEA
MOVEA RW7
RW7,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
RW6,@RW3+ RW6, addr16 [email protected]+ RW7, addr16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2+ ,@PC+d16
RW6,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
RW0,@RW3+ RW0, addr16 RW1,@RW3+ RW1, addr16 RW2,@RW3+ RW2, addr16 RW3,@RW3+ RW3, addr16 RW4,@RW3+ RW4, addr16 RW5,@RW3+ RW5, addr16
MOVEA
MOVEA RW2
RW2,@RW2+ ,@PC+d16
+F
MOVEA
MOVEA RW1
RW1,@RW2+ ,@PC+d16
MOVEA
MOVEA RW0
RW0,@RW2+ ,@PC+d16
MOVEA RW1
+E
MOVEA
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW5,@RW1+ ,@RW1+RW7 RW6,@RW1+ ,@RW1+RW7 RW7,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW7
RW7,@RW3 ,@RW3+d16
MOVEA
MOVEA RW7
RW7,@RW2 ,@RW2+d16
MOVEA
MOVEA RW7
RW7,@RW1 ,@RW1+d16
MOVEA
MOVEA RW7
RW7,@RW0 ,@RW0+d16
MOVEA
MOVEA RW7
RW7,RW7 ,@RW7+d8
MOVEA
MOVEA RW7
RW7,RW6 ,@RW6+d8
MOVEA
MOVEA RW7
RW7,RW5 ,@RW5+d8
MOVEA
MOVEA RW7
RW7,RW4 ,@RW4+d8
MOVEA
MOVEA RW7
RW7,RW3 ,@RW3+d8
MOVEA
MOVEA RW7
RW7,RW2 ,@RW2+d8
MOVEA
MOVEA RW7
RW7,RW1 ,@RW1+d8
MOVEA
MOVEA RW7
RW7,RW0 ,@RW0+d8
E0
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4
RW2,@RW1+ ,@RW1+RW7 RW3,@RW1+ ,@RW1+RW7 RW4,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW3 ,@RW3+d16 RW6,@RW3 ,@RW3+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2 ,@RW2+d16 RW6,@RW2 ,@RW2+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW1 ,@RW1+d16 RW6,@RW1 ,@RW1+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW0 ,@RW0+d16 RW6,@RW0 ,@RW0+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW7 ,@RW7+d8
RW6,RW7 ,@RW7+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW6 ,@RW6+d8
RW6,RW6 ,@RW6+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW5 ,@RW5+d8
RW6,RW5 ,@RW5+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW4 ,@RW4+d8
RW6,RW4 ,@RW4+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW3 ,@RW3+d8
RW6,RW3 ,@RW3+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW2 ,@RW2+d8
RW6,RW2 ,@RW2+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW1 ,@RW1+d8
RW6,RW1 ,@RW1+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW0 ,@RW0+d8
RW6,RW0 ,@RW0+d8
A0
+D RW0,@RW1+ ,@RW1+RW7 RW1,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW4
RW4,@RW3 ,@RW3+d16
MOVEA
MOVEA RW4
RW4,@RW2 ,@RW2+d16
MOVEA
MOVEA RW4
RW4,@RW1 ,@RW1+d16
MOVEA
MOVEA RW4
RW4,@RW0 ,@RW0+d16
MOVEA
MOVEA RW4
RW4,RW7 ,@RW7+d8
MOVEA
MOVEA RW4
RW4,RW6 ,@RW6+d8
MOVEA
MOVEA RW4
RW4,RW5 ,@RW5+d8
MOVEA
MOVEA RW4
RW4,RW4 ,@RW4+d8
MOVEA
MOVEA RW4
RW4,RW3 ,@RW3+d8
MOVEA
MOVEA RW4
RW4,RW2 ,@RW2+d8
MOVEA
MOVEA RW4
RW4,RW1 ,@RW1+d8
MOVEA
MOVEA RW4
RW4,RW0 ,@RW0+d8
80
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW5,@RW0+ ,@RW0+RW7 RW6,@RW0+ ,@RW0+RW7 RW7,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW3
RW3,@RW3 ,@RW3+d16
MOVEA
MOVEA RW3
RW3,@RW2 ,@RW2+d16
MOVEA
MOVEA RW3
RW3,@RW1 ,@RW1+d16
MOVEA
MOVEA RW3
RW3,@RW0 ,@RW0+d16
MOVEA
MOVEA RW3
RW3,RW7 ,@RW7+d8
MOVEA
MOVEA RW3
RW3,RW6 ,@RW6+d8
MOVEA
MOVEA RW3
RW3,RW5 ,@RW5+d8
MOVEA
MOVEA RW3
RW3,RW4 ,@RW4+d8
MOVEA
MOVEA RW3
RW3,RW3 ,@RW3+d8
MOVEA
MOVEA RW3
RW3,RW2 ,@RW2+d8
MOVEA
MOVEA RW3
RW3,RW1 ,@RW1+d8
MOVEA
MOVEA RW3
RW3,RW0 ,@RW0+d8
60
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4
RW2,@RW0+ ,@RW0+RW7 RW3,@RW0+ ,@RW0+RW7 RW4,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW2
RW2,@RW3 ,@RW3+d16
MOVEA
MOVEA RW2
RW2,@RW2 ,@RW2+d16
MOVEA
MOVEA RW2
RW2,@RW1 ,@RW1+d16
MOVEA
MOVEA RW2
RW2,@RW0 ,@RW0+d16
MOVEA
MOVEA RW2
RW2,RW7 ,@RW7+d8
MOVEA
MOVEA RW2
RW2,RW6 ,@RW6+d8
MOVEA
MOVEA RW2
RW2,RW5 ,@RW5+d8
MOVEA
MOVEA RW2
RW2,RW4 ,@RW4+d8
MOVEA
MOVEA RW2
RW2,RW3 ,@RW3+d8
MOVEA
MOVEA RW2
RW2,RW2 ,@RW2+d8
MOVEA
MOVEA RW2
RW2,RW1 ,@RW1+d8
MOVEA
MOVEA RW2
RW2,RW0 ,@RW0+d8
40
+C RW0,@RW0+ ,@RW0+RW7 RW1,@RW0+ ,@RW0+RW7
+B RW0,@RW3 ,@RW3+d16
+A RW0,@RW2 ,@RW2+d16
+9 RW0,@RW1 ,@RW1+d16
MOVEA RW1
MOVEA
MOVEA RW1
RW1,RW3 ,@RW3+d8
MOVEA
MOVEA RW0
RW0,RW3 ,@RW3+d8
+3
MOVEA
MOVEA
MOVEA RW1
RW1,RW2 ,@RW2+d8
MOVEA
MOVEA RW0
RW0,RW2 ,@RW2+d8
+2
+8 RW0,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,RW1 ,@RW1+d8
MOVEA
MOVEA RW0
RW0,RW1 ,@RW1+d8
+1
30
MOVEA
MOVEA RW1
RW1,RW0 ,@RW0+d8
20
MOVEA
MOVEA RW0
RW0,RW0 ,@RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-15 MOVEA RWi, ea Instruction (First Byte = 79H)
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW2 @RW2+d16 R1,@RW2 @RW2+d16 R2,@RW2 @RW2+d16 R3,@RW2 @RW2+d16 R4,@RW2 @RW2+d16 R5,@RW2 @RW2+d16 R6,@RW2 @RW2+d16 R7,@RW2 @RW2+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW3+
addr16 @RW3+
addr16
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16
@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-16 MOV Ri, ea Instruction (First Byte = 7AH)
483
484
MOVW
MOVW RW5,
RW5,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW1 @RW1+d16 RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16 RW3,@RW1 @RW1+d16 RW4,@RW1 @RW1+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW2 @RW2+d16 RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16 RW3,@RW2 @RW2+d16 RW4,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW3 @RW3+d16 RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16 RW3,@RW3 @RW3+d16 RW4,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4, MOVW
MOVW RW5, MOVW
MOVW RW6, MOVW
MOVW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, @RW2+ @PC+d16
RW2, @RW2+ @PC+d16
RW3, @RW2+ @PC+d16
RW4, @RW2+ @PC+d16
MOVW
MOVW
RW1, @RW3+ RW1, addr16
MOVW
RW0, @RW1+
MOVW
MOVW
RW0, @RW2+ @PC+d16
MOVW
MOVW
RW0, @RW3+ RW0, addr16
+9
+A
+B
+C
+D
+E
+F
MOVW
MOVW
RW2, @RW3+ RW2, addr16
MOVW
MOVW
RW3, @RW3+ RW3, addr16
MOVW
MOVW
RW5, @RW3+ RW5, addr16
MOVW
MOVW
RW5, @RW2+ @PC+d16
MOVW
MOVW
RW6, @RW3+ RW6, addr16
MOVW
MOVW RW6,
RW6, @RW2+ @PC+d16
MOVW
MOVW
RW7, @RW3+ RW7, addr16
MOVW
MOVW RW7,
RW7, @RW2+ @PC+d16
MOVW RW7,
@RW1+RW7
MOVW
MOVW RW7,
RW7,@RW3 @RW3+d16
MOVW
MOVW RW7,
RW7,@RW2 @RW2+d16
MOVW
MOVW RW7,
RW7,@RW1 @RW1+d16
MOVW
MOVW RW7,
RW7,@RW0 @RW0+d16
MOVW
MOVW RW7,
RW7, RW7 @RW7+d8
MOVW
MOVW RW7,
RW7, RW6 @RW6+d8
MOVW
MOVW RW7,
RW7, RW5 @RW5+d8
MOVW
MOVW RW7,
RW7, RW4 @RW4+d8
MOVW RW6, MOVW
@RW1+RW7 RW7, @RW1+
MOVW
MOVW RW6,
RW6,@RW3 @RW3+d16
MOVW
MOVW RW6,
RW6,@RW2 @RW2+d16
MOVW
MOVW RW6,
RW6,@RW1 @RW1+d16
MOVW
MOVW RW6,
RW6,@RW0 @RW0+d16
MOVW
MOVW RW6,
RW6, RW7 @RW7+d8
MOVW
MOVW RW6,
RW6, RW6 @RW6+d8
MOVW
MOVW RW6,
RW6, RW5 @RW5+d8
MOVW
MOVW RW6,
RW6, RW4 @RW4+d8
MOVW
MOVW
@RW1+RW7 RW6, @RW1+
MOVW
MOVW RW5,
RW5, RW6 @RW6+d8
MOVW
MOVW RW5,
RW5, RW5 @RW5+d8
MOVW RW4, MOVW
@RW1+RW7 RW5, @RW1+
MOVW
MOVW
RW4, @RW3+ RW4, addr16
MOVW RW3, MOVW
@RW1+RW7 RW4, @RW1+
MOVW
MOVW RW5,
RW5,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW0 @RW0+d16 RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16 RW3,@RW0 @RW0+d16 RW4,@RW0 @RW0+d16
+8
MOVW RW2, MOVW
@RW1+RW7 RW3, @RW1+
MOVW
MOVW RW5,
RW5,@RW1 @RW1+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
MOVW
MOVW
RW0, RW7 @RW7+d8
+7
MOVW RW1, MOVW
@RW1+RW7 RW2, @RW1+
MOVW
MOVW RW5,
RW5,@RW0 @RW0+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
MOVW
MOVW
RW0, RW6 @RW6+d8
+6
MOVW
MOVW
@RW1+RW7 RW1, @RW1+
MOVW
MOVW RW5,
RW5, RW7 @RW7+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
MOVW
MOVW
RW0, RW5 @RW5+d8
+5
MOVW
MOVW RW5,
RW5, RW4 @RW4+d8
MOVW
MOVW RW7,
RW7, RW3 @RW3+d8
MOVW
MOVW RW7,
RW7, RW2 @RW2+d8
MOVW
MOVW RW7,
RW7, RW1 @RW1+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
MOVW
MOVW RW6,
RW6, RW3 @RW3+d8
MOVW
MOVW RW6,
RW6, RW2 @RW2+d8
MOVW
MOVW RW6,
RW6, RW1 @RW1+d8
MOVW
MOVW
RW0, RW4 @RW4+d8
MOVW
MOVW RW5,
RW5, RW3 @RW3+d8
MOVW
MOVW RW5,
RW5, RW2 @RW2+d8
MOVW
MOVW RW5,
RW5, RW1 @RW1+d8
+4
F0
MOVW
MOVW RW7,
RW7, RW0 @RW0+d8
E0
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
D0
MOVW
MOVW RW6,
RW6, RW0 @RW0+d8
C0
MOVW
MOVW
RW0, RW3 @RW3+d8
B0
MOVW
MOVW RW5,
RW5, RW0 @RW0+d8
A0
+3
90
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
80
MOVW
MOVW
RW0, RW2 @RW2+d8
70
+2
60
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
50
MOVW
MOVW
RW0, RW1 @RW1+d8
40
+1
30
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
20
MOVW
MOVW
RW0, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-17 MOVW RWi, ea Instruction (First Byte = 7BH)
+F
+E
+D
+C
+B
+A
+9
+8
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R1 addr16, R1
MOV
MOV
@RW3+, R0 addr16, R0
MOV
MOV
MOV
@RW2+, R1 @PC+d16, R1
@RW2+, R0 @PC+d16, R0
MOV
MOV
MOV
MOV
MOV
@RW0+, R1 @RW0+RW7, R1
MOV
@RW3, R1 @RW3+d16, R1
MOV
@RW2, R1 @RW2+d16, R1
MOV
@RW1, R1 @RW1+d16, R1
MOV
@RW1+, R1 @RW1+RW7, R1
MOV
MOV
@RW0, R1 @RW0+d16, R1
MOV
@RW1+, R0 @RW1+RW7, R0
MOV
@RW0+, R0 @RW0+RW7, R0
MOV
@RW3, R0 @RW3+d16, R0
MOV
@RW2, R0 @RW2+d16, R0
MOV
@RW1, R0 @RW1+d16, R0
MOV
@RW0, R0 @RW0+d16, R0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R2 addr16, R2
MOV
@RW2+, R2 @PC+d16, R2
MOV
@RW1+, R2 @RW1+RW7, R2
MOV
@RW0+, R2 @RW0+RW7, R2
MOV
@RW3, R2 @RW3+d16, R2
MOV
@RW2, R2 @RW2+d16, R2
MOV
@RW1, R2 @RW1+d16, R2
MOV
@RW0, R2 @RW0+d16, R2
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R3 addr16, R3
MOV
@RW2+, R3 @PC+d16, R3
MOV
@RW1+, R3 @RW1+RW7, R3
MOV
@RW0+, R3 @RW0+RW7, R3
MOV
@RW3, R3 @RW3+d16, R3
MOV
@RW2, R3 @RW2+d16, R3
MOV
@RW1, R3 @RW1+d16, R3
MOV
@RW0, R3 @RW0+d16, R3
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R4 addr16, R4
MOV
@RW2+, R4 @PC+d16, R4
MOV
@RW1+, R4 @RW1+RW7, R4
MOV
@RW0+, R4 @RW0+RW7, R4
MOV
@RW3, R4 @RW3+d16, R4
MOV
@RW2, R4 @RW2+d16, R4
MOV
@RW1, R4 @RW1+d16, R4
MOV
@RW0, R4 @RW0+d16, R4
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R5 addr16, R5
MOV
@RW2+, R5 @PC+d16, R5
MOV
@RW1+, R5 @RW1+RW7, R5
MOV
@RW0+, R5 @RW0+RW7, R5
MOV
@RW3, R5 @RW3+d16, R5
MOV
@RW2, R5 @RW2+d16, R5
MOV
@RW1, R5 @RW1+d16, R5
MOV
@RW0, R5 @RW0+d16, R5
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R6 addr16, R6
MOV
@RW2+, R6 @PC+d16, R6
MOV
@RW1+, R6 @RW1+RW7, R6
MOV
@RW0+, R6 @RW0+RW7, R6
MOV
@RW3, R6 @RW3+d16, R6
MOV
@RW2, R6 @RW2+d16, R6
MOV
@RW1, R6 @RW1+d16, R6
MOV
@RW0, R6 @RW0+d16,
R6
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R7 addr16, R7
MOV
@RW2+, R7 @PC+d16, R7
MOV
@RW1+, R7 @RW1+RW7, R7
MOV
@RW0+, R7 @RW0+RW7, R7
MOV
@RW3, R7 @RW3+d16, R7
MOV
@RW2, R7 @RW2+d16, R7
MOV
@RW1, R7 @RW1+d16, R7
MOV
@RW0, R7 @RW0+d16, R7
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R7, R0 @RW7+d8, R0
R7, R1 @RW7+d8, R1
R7, R2 @RW7+d8, R2
R7, R3 @RW7+d8, R3
R7, R4 @RW7+d8, R4
R7, R5 @RW7+d8, R5
R7, R6 @RW7+d8, R6
R7, R7 @RW7+d8, R7
F0
+7
E0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R6, R0 @RW6+d8, R0
R6, R1 @RW6+d8, R1
R6, R2 @RW6+d8, R2
R6, R3 @RW6+d8, R3
R6, R4 @RW6+d8, R4
R6, R5 @RW6+d8, R5
R6, R6 @RW6+d8, R6
R6, R7 @RW6+d8, R7
D0
+6
C0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R5, R0 @RW5+d8, R0
R5, R1 @RW5+d8, R1
R5, R2 @RW5+d8, R2
R5, R3 @RW5+d8, R3
R5, R4 @RW5+d8, R4
R5, R5 @RW5+d8, R5
R5, R6 @RW5+d8, R6
R5, R7 @RW5+d8, R7
B0
+5
A0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R4, R0 @RW4+d8, R0
R4, R1 @RW4+d8, R1
R4, R2 @RW4+d8, R2
R4, R3 @RW4+d8, R3
R4, R4 @RW4+d8, R4
R4, R5 @RW4+d8, R5
R4, R6 @RW4+d8, R6
R4, R7 @RW4+d8, R7
90
+4
80
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R3, R0 @RW3+d8, R0
R3, R1 @RW3+d8, R1
R3, R2 @RW3+d8, R2
R3, R3 @RW3+d8, R3
R3, R4 @RW3+d8, R4
R3, R5 @RW3+d8, R5
R3, R6 @RW3+d8, R6
R3, R7 @RW3+d8, R7
70
+3
60
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R2, R0 @RW2+d8, R0
R2, R1 @RW2+d8, R1
R2, R2 @RW2+d8, R2
R2, R3 @RW2+d8, R3
R2, R4 @RW2+d8, R4
R2, R5 @RW2+d8, R5
R2, R6 @RW2+d8, R6
R2, R7 @RW2+d8, R7
50
+2
40
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R1, R0 @RW1+d8, R0
R1, R1 @RW1+d8, R1
R1, R2 @RW1+d8, R2
R1, R3 @RW1+d8, R3
R1, R4 @RW1+d8, R4
R1, R5 @RW1+d8, R5
R1, R6 @RW1+d8, R6
R1, R7 @RW1+d8, R7
30
+1
20
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R0, R0 @RW0+d8, R0
R0, R1 @RW0+d8, R1
R0, R2 @RW0+d8, R2
R0, R3 @RW0+d8, R3
R0, R4 @RW0+d8, R4
R0, R5 @RW0+d8, R5
R0, R6 @RW0+d8, R6
R0, R7 @RW0+d8, R7
10
+0
00
APPENDIX B Instructions
Table B.9-18 MOV ea, Ri Instruction (First Byte = 7CH)
485
486
MOVW
[email protected]
@RW2, RW1 +d16, RW1
MOVW
[email protected]
@RW3, RW1 +d16, RW1
MOVW
[email protected]
@RW0+, RW1 +RW7,RW1
MOVW
[email protected]
@RW1+,RW1 +RW7,RW1
MOVW
[email protected]
@RW2+,RW1 +d16, RW1
MOVW
MOVW
@RW3+,RW1 addr16, RW1
MOVW
[email protected]
@RW2, RW0 +d16, RW0
MOVW
[email protected]
@RW3, RW0 +d16, RW0
MOVW
[email protected]
@RW0+,RW0 +RW7,RW0
MOVW
[email protected]
@RW1+,RW0 +RW7,RW0
MOVW
[email protected]
@RW2+,RW0 +d16, RW0
MOVW
MOVW
@RW3+,RW0 addr16, RW0
+B
+C
+D
+E
+F
MOVW
MOVW
@RW3+,RW2 addr16, RW2
MOVW
[email protected]
@RW2+,RW2 +d16, RW2
MOVW
[email protected]
@RW1+,RW2 +RW7,RW2
MOVW
[email protected]
@RW0+,RW2 +RW7,RW2
MOVW
[email protected]
@RW3, RW2 +d16, RW2
MOVW
[email protected]
@RW2, RW2 +d16, RW2
MOVW
MOVW
@RW3+,RW3 addr16, RW3
MOVW
[email protected]
@RW2+,RW3 +d16, RW3
MOVW
[email protected]
@RW1+,RW3 -+RW7,RW3
MOVW
[email protected]
@RW0+,RW3 +RW7,RW3
MOVW
[email protected]
@RW3, RW3 +d16, RW3
MOVW
[email protected]
@RW2, RW3 +d16, RW3
MOVW
[email protected]
@RW1, RW3 +d16, RW3
MOVW
MOVW
@RW3+,RW4 addr16, RW4
MOVW
[email protected]
@RW2+,RW4 +d16, RW4
MOVW
[email protected]
@RW1+,RW4 +RW7,RW4
MOVW
[email protected]
@RW0+,RW4 +RW7,RW4
MOVW
[email protected]
@RW3, RW4 +d16, RW4
MOVW
[email protected]
@RW2, RW4 +d16, RW4
MOVW
[email protected]
@RW1, RW4 +d16, RW4
MOVW
MOVW
@RW3+,RW5 addr16, RW5
MOVW
[email protected]
@RW2+,RW5 +d16, RW5
MOVW
[email protected]
@RW1+,RW5 +RW7,RW5
MOVW
[email protected]
@RW0+,RW5 +RW7,RW5
MOVW
[email protected]
@RW3, RW5 +d16, RW5
MOVW
[email protected]
@RW2, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW5 +d16, RW5
MOVW
MOVW
@RW3+,RW6 addr16, RW6
MOVW
MOVW @PC
@RW2+,RW6 +d16, RW6
MOVW
[email protected]
@RW1+,RW6 +RW7,RW6
MOVW
[email protected]
@RW0+,RW6 +RW7,RW6
MOVW
[email protected]
@RW3, RW6 +d16, RW6
MOVW
[email protected]
@RW2, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW6 +d16, RW6
MOVW
MOVW
@RW3+,RW7 addr16, RW7
MOVW
[email protected]
@RW2+,RW7 +d16, RW7
MOVW
[email protected]
@RW1+,RW7 +RW7,RW7
MOVW
[email protected]
@RW0+,RW7 +RW7,RW7
MOVW
[email protected]
@RW3, RW7 +d16, RW7
MOVW
[email protected]
@RW2, RW7 +d16, RW7
MOVW
[email protected]
@RW1, RW7 +d16, RW7
MOVW
[email protected]
@RW0, RW7 +d16, RW7
+A
MOVW
[email protected]
@RW1, RW2 +d16, RW2
MOVW
[email protected]
@RW0, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW1 +d16, RW1
MOVW
[email protected]
@RW0, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW0 +d16, RW0
MOVW
[email protected]
@RW0, RW4 +d16, RW4
+9
MOVW
[email protected]
@RW0, RW3 +d16, RW3
MOVW
[email protected]
@RW0, RW1 +d16, RW1
MOVW
[email protected]
@RW0, RW0 +d16, RW0
+8
MOVW
[email protected]
@RW0, RW2 +d16, RW2
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW7, RW0 @RW7+d8, RW0
RW7, RW1 @RW7+d8, RW1 RW7, RW2 @RW7+d8, RW2 RW7, RW3 @RW7+d8, RW3 RW7, RW4 @RW7+d8, RW4 RW7, RW5 @RW7+d8, RW5 RW7, RW6 @RW7+d8, RW6 RW7, RW7 @RW7+d8, RW7
F0
+7
E0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW6, RW0 @RW6+d8, RW0
RW6, RW1 @RW6+d8, RW1 RW6, RW2 @RW6+d8, RW2 RW6, RW3 @RW6+d8, RW3 RW6, RW4 @RW6+d8, RW4 RW6, RW5 @RW6+d8, RW5 RW6, RW6 @RW6+d8, RW6 RW6, RW7 @RW6+d8, RW7
D0
+6
C0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW5, RW0 @RW5+d8, RW0
RW5, RW1 @RW5+d8, RW1 RW5, RW2 @RW5+d8, RW2 RW5, RW3 @RW5+d8, RW3 RW5, RW4 @RW5+d8, RW4 RW5, RW5 @RW5+d8, RW5 RW5, RW6 @RW5+d8, RW6 RW5, RW7 @RW5+d8, RW7
B0
+5
A0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW4, RW0 @RW4+d8, RW0
RW4, RW1 @RW4+d8, RW1 RW4, RW2 @RW4+d8, RW2 RW4, RW3 @RW4+d8, RW3 RW4, RW4 @RW4+d8, RW4 RW4, RW5 @RW4+d8, RW5 RW4, RW6 @RW4+d8, RW6 RW4, RW7 @RW4+d8, RW7
90
+4
80
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW3, RW0 @RW3+d8, RW0
RW3, RW1 @RW3+d8, RW1 RW3, RW2 @RW3+d8, RW2 RW3, RW3 @RW3+d8, RW3 RW3, RW4 @RW3+d8, RW4 RW3, RW5 @RW3+d8, RW5 RW3, RW6 @RW3+d8, RW6 RW3, RW7 @RW3+d8, RW7
70
+3
60
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW2, RW0 @RW2+d8, RW0
RW2, RW1 @RW2+d8, RW1 RW2, RW2 @RW2+d8, RW2 RW2, RW3 @RW2+d8, RW3 RW2, RW4 @RW2+d8, RW4 RW2, RW5 @RW2+d8, RW5 RW2, RW6 @RW2+d8, RW6 RW2, RW7 @RW2+d8, RW7
50
+2
40
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW1, RW0 @RW1+d8, RW0
RW1, RW1 @RW1+d8, RW1 RW1, RW2 @RW1+d8, RW2 RW1, RW3 @RW1+d8, RW3 RW1, RW4 @RW1+d8, RW4 RW1, RW5 @RW1+d8, RW5 RW1, RW6 @RW1+d8, RW6 RW1, RW7 @RW1+d8, RW7
30
+1
20
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW0, RW0 @RW0+d8, RW0
RW0, RW1 @RW0+d8, RW1 RW0, RW2 @RW0+d8, RW2 RW0, RW3 @RW0+d8, RW3 RW0, RW4 @RW0+d8, RW4 RW0, RW5 @RW0+d8, RW5 RW0, RW6 @RW0+d8, RW6 RW0, RW7 @RW0+d8, RW7
10
+0
00
APPENDIX B Instructions
Table B.9-19 MOVW ea, Rwi Instruction (First Byte = 7DH)
XCH
XCH
XCH
XCH
R1,
XCH
XCH R1,
R1,@RW2 W2+d16, A
XCH
XCH
R2,
XCH
XCH R2,
R2,@RW2 W2+d16, A
XCH
XCH
R3,
XCH
XCH R3,
R3,@RW2 W2+d16, A
XCH
XCH
R4,
XCH
XCH R4,
R4,@RW2 W2+d16, A
XCH
XCH
R5,
XCH
XCH R5,
R5,@RW2 W2+d16, A
XCH
XCH
R6,
XCH
XCH R6,
R6,@RW2 W2+d16, A
XCH
XCH
R7,
XCH
XCH R7,
R7,@RW2 W2+d16, A
XCH
XCH
XCH
XCH
XCH
R1, XCH
XCH
R2, XCH
XCH
R3, XCH
XCH
R4, XCH
XCH
R5, XCH
XCH
R6, XCH
XCH
R7,
+F R0,@RW3+ R0, addr16
XCH
XCH
R1,@RW3+ R1, addr16
XCH
XCH
R2,@RW3+ R2, addr16
XCH
XCH
R3,@RW3+ R3, addr16
XCH
XCH
R4,@RW3+ R4, addr16
XCH
XCH
R5,@RW3+ R5, addr16
XCH
XCH
R6,@RW3+ R6, addr16
XCH
XCH
R7,@RW3+ R7, addr16
+E R0,@RW2+ @PC+d16 R1,@RW2+ @PC+d16 R2,@RW2+ @PC+d16 R3,@RW2+ @PC+d16 R4,@RW2+ @PC+d16 R5,@RW2+ @PC+d16 R6,@RW2+ @PC+d16 R7,@RW2+ @PC+d16
R0, XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW1+RW7 R1,@RW1+ @RW1+RW7 R2,@RW1+ @RW1+RW7 R3,@RW1+ @RW1+RW7 R4,@RW1+ @RW1+RW7 R5,@RW1+ @RW1+RW7 R6,@RW1+ @RW1+RW7 R7,@RW1+ @RW1+RW7
+D R0,@RW1+
XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW0+RW7 R1,@RW0+ @RW0+RW7 R2,@RW0+ @RW0+RW7 R3,@RW0+ @RW0+RW7 R4,@RW0+ @RW0+RW7 R5,@RW0+ @RW0+RW7 R6,@RW0+ @RW0+RW7 R7,@RW0+ @RW0+RW7
XCH
+C R0,@RW0+
+B R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
R0,
+A R0,@RW2 W2+d16, A
R0,
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
+9
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
+8
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
F0
+7
E0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH)
487
488
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2+ @PC+d16
RW1,@RW2+ @PC+d16
RW2,@RW2+ @PC+d16
RW3,@RW2+ @PC+d16
RW4,@RW2+ @PC+d16
RW5,@RW2+ @PC+d16
RW6,@RW2+ @PC+d16
RW7,@RW2+ @PC+d16
XCHW
XCHW
RW0,@RW3+ RW0, addr16
+E
+F
XCHW
XCHW
RW7,@RW3+ RW7, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW1+ @RW1+RW7 RW1,@RW1+ @RW1+RW7 RW2,@RW1+ @RW1+RW7 RW3,@RW1+ @RW1+RW7 RW4,@RW1+ @RW1+RW7 RW5,@RW1+ @RW1+RW7 RW6,@RW1+ @RW1+RW7 RW7,@RW1+ @RW1+RW7
+D
XCHW
XCHW
RW6,@RW3+ RW6, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
+C
XCHW
XCHW
RW5,@RW3+ RW5, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW3 @RW3+d16
RW1,@RW3 @RW3+d16
RW2,@RW3 @RW3+d16
RW3,@RW3 @RW3+d16
RW4,@RW3 @RW3+d16
RW5,@RW3 @RW3+d16
RW6,@RW3 @RW3+d16
RW7,@RW3 @RW3+d16
+B
XCHW
XCHW
RW4,@RW3+ RW4, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2 @RW2+d16
RW1,@RW2 @RW2+d16
RW2,@RW2 @RW2+d16
RW3,@RW2 @RW2+d16
RW4,@RW2 @RW2+d16
RW5,@RW2 @RW2+d16
RW6,@RW2 @RW2+d16
RW7,@RW2 @RW2+d16
+A
XCHW
XCHW
RW3,@RW3+ RW3, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW1 @RW1+d16
RW1,@RW1 @RW1+d16
RW2,@RW1 @RW1+d16
RW3,@RW1 @RW1+d16
RW4,@RW1 @RW1+d16
RW5,@RW1 @RW1+d16
RW6,@RW1 @RW1+d16
RW7,@RW1 @RW1+d16
+9
XCHW
XCHW
RW2,@RW3+ RW2, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW0 @RW0+d16
RW1,@RW0 @RW0+d16
RW2,@RW0 @RW0+d16
RW3,@RW0 @RW0+d16
RW4,@RW0 @RW0+d16
RW5,@RW0 @RW0+d16
RW6,@RW0 @RW0+d16
RW7,@RW0 @RW0+d16
+8
XCHW
XCHW
RW1,@RW3+ RW1, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW7 @RW7+d8
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
RW5, RW7 @RW7+d8
RW6, RW7 @RW7+d8
RW7, RW7 @RW7+d8
F0
+7
E0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW6 @RW6+d8
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
RW5, RW6 @RW6+d8
RW6, RW6 @RW6+d8
RW7, RW6 @RW6+d8
D0
+6
C0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW5 @RW5+d8
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
RW5, RW5 @RW5+d8
RW6, RW5 @RW5+d8
RW7, RW5 @RW5+d8
B0
+5
A0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW4 @RW4+d8
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
RW5, RW4 @RW4+d8
RW6, RW4 @RW4+d8
RW7, RW4 @RW4+d8
90
+4
80
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW3 @RW3+d8
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
RW5, RW3 @RW3+d8
RW6, RW3 @RW3+d8
RW7, RW3 @RW3+d8
70
+3
60
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW2 @RW2+d8
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
RW5, RW2 @RW2+d8
RW6, RW2 @RW2+d8
RW7, RW2 @RW2+d8
50
+2
40
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW1 @RW1+d8
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
RW5, RW1 @RW1+d8
RW6, RW1 @RW1+d8
RW7, RW1 @RW1+d8
30
+1
20
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW0 @RW0+d8
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
RW5, RW0 @RW0+d8
RW6, RW0 @RW0+d8
RW7, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-21 XCHW RWi, ea Instruction (First Byte = 7FH)
APPENDIX C Timing Diagrams in Flash Memory Mode
APPENDIX C Timing Diagrams in Flash Memory Mode
Each timing diagram for the external pins of the MB90F594 in the Flash Memory mode is
shown below.
■ Data read by Read Access
Figure C-1 Timing Diagram for Read Access
tRC
Address stable
AQ16 to AQ0
tACC
CE
tDF
tOE
OE
tOEH
WE
tOH
tCE
High
impedance
High impedance
DQ7 to DQ0
Output defined
■ Write, Data polling, Read (WE control)
Figure C-2 Write Data polling Read (WE control)
Third bus cycle
AQ18
to
AQ0
Data polling
7AAAAH
PA
tWC
tAS
PA
tRC
tAH
CE
tGHWL
OE
tWP
tWHWH1
WE
tCS
DQ7
to
DQ0
tOE
tWPH
tDF
tDH
A0H
PD
DQ7
DOU
T
tDS
tOH
5.0 V
PA: Write address
PD: Write data
DQ7: Reverse output of write data
DOUT: Output of write data
tCE
Note: The last two bus cycle sequences out of the four are described.
489
APPENDIX C Timing Diagrams in Flash Memory Mode
■ Write, Data Polling, Read (CE control)
Figure C-3 Timing Diagram for Write Access (CE Control)
Third bus cycle
Data polling
7AAAAH
AQ18 to AQ0
PA
tWC
tAS
PA
tAH
tWH
WE
tGHWL
OE
tCP
tWHWH1
CE
tCPH
tWS
tDH
A0H
PD
DQ7
DOU
T
DQ7 to DQ0
tDS
5.0 V
PA: Write address
PD: Write data
DQ7: Reverse output of write data
DOUT: Output of write data
Note: The last two bus cycle sequences out of the four are described.
■ Chip Erase/sector Erase Command Sequence
Figure C-4 Timing Diagram for Write Access (Chip Erasing/Sector Erasing)
tAS
AQ18
to
AQ0
7AAAAH
tAH
75555H
7AAAAH
7AAAAH
75555H
SA*
CE
tGHWL
OE
tWP
WE
tWPH
tCS
DQ7
to
DQ0
tDH
AAH
55H
80H
AAH
55H
10H/30H
tDS
VCC
tVCS
*: SA is the sector address at sector erasing. 7AAAAH (or 6AAAAH) is the address at chip
erasing.
490
APPENDIX C Timing Diagrams in Flash Memory Mode
■ Data Polling
Figure C-5 Timing Diagram for Data Polling
tCH
CE
tOE
tDF
OE
tOEH
WE
tCE
tOH
*
DQ7
High
impedance
DQ7 = Valid data
DQ7
tWHWH1 or
tWHWH2
DQ6 to DQ0
DQ6 to DQ0 = Invalid
DQ6 to DQ0
= Valid data
tOE
*: DQ7 is valid data (The device terminates automatic operation).
■ Toggle Bit
Figure C-6 Timing Diagram for Toggle Bit
CE
tOE
H
WE
tOES
OE
*
Data (DQ7 to DQ0)
DQ6 = Toggle
DQ6 = Toggle
DQ7 = Stop toggling
DQ7 to
DQ0 = Valid
tOE
*: DQ7 stops toggling (The device terminates automatic operation).
■ RY/BY Timing During Writing/erasing
Figure C-7 Timing Diagram for Output of RY/BY Signal during Writing/Erasing
CE
Rising edge of last write pulse
WE
Writing or erasing
RY/BY
tBUSY
491
APPENDIX C Timing Diagrams in Flash Memory Mode
■ RST and RY/BY timing
Figure C-8 Timing Diagram for Output of RY/BY Signal at Hardware Reset
CE
RY/BY
tRP
RST
tReady
■ Enable Sector Protect/Verify Sector Protect
Figure C-9 Enable Sector Protect/Verify Sector Protect
AQ18 to AQ9
SAx
AQ8, AQ2, and AQ1
SAy
(AQ8, AQ2, AQ1) = (0, 1, 0)
MD0 12 V
5V
MD2 12 V
5V
tVLHT
tVLHT
OE
WE
tWPP
tOESP
CE
tCSP
DQ7 to DQ0
01H
SAx: First sector address
SAy: Next sector address
492
tOE
APPENDIX C Timing Diagrams in Flash Memory Mode
■ Temporary Sector Protect Cancellation
Figure C-10 Temporary Sector Protect Cancellation
Write/erase command
sequence
493
APPENDIX D List of MB90590 Series Interrupt Vectors
APPENDIX D List of MB90590 Series Interrupt Vectors
The interrupt vector table to be referenced for interrupt processing is allocated to
FFFC00H to FFFFFFH in the memory area and also used for software interrupts.
■ List of MB90590 Series Interrupt Vectors
Table D-1 lists the interrupt vectors for the MB90590 series.
Table D-1 MB90590 Series Interrupt Vectors (1/2)
Software
interrupt
instruction
Vector
address L
Vector
address M
Vector
address H
Mode
register
Interrupt
No.
INT 0
FFFFECH
FFFFEDH
FFFFEEH
Unused
#0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
INT 7
FFFFE0H
FFFFE1H
FFFFE2H
Unused
#7
None
INT 8
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDF
#8
(RESET vector)
INT 9
FFFFD8H
FFFFD9H
FFFFDAH
Unused
#9
ROM correction
INT 10
FFFFD4H
FFFFD5H
FFFFD6H
Unused
#10
<Exception>
INT 11
FFFFD0H
FFFFD1H
FFFFD2H
Unused
#11
Timebase timer
INT 12
FFFFCCH
FFFFCDH
FFFFCEH
Unused
#12
External interrupt
(INT0 to INT7)
INT 13
FFFFC8H
FFFFC9H
FFFFCAH
Unused
#13
CAN 0 RX
INT 14
FFFFC4H
FFFFC5H
FFFFC6H
Unused
#14
CAN 0 TX/NS
INT 15
FFFFC0H
FFFFC1H
FFFFC2H
Unused
#15
CAN 1 RX
INT 16
FFFFBCH
FFFFBDH
FFFFBEH
Unused
#16
CAN 1 TX/NS
INT 17
FFFFB8H
FFFFB9H
FFFFBAH
Unused
#17
PPG (ch.0,ch.1) unit 0
INT 18
FFFFB4H
FFFFB5H
FFFFB6H
Unused
#18
PPG (ch.2,ch.3) unit 1
INT 19
FFFFB0H
FFFFB1H
FFFFB2H
Unused
#19
PPG (ch.4,ch.5) unit 2
INT 20
FFFFACH
FFFFADH
FFFFAEH
Unused
#20
PPG (ch.6,ch.7) unit 3
INT 21
FFFFA8H
FFFFA9H
FFFFAAH
Unused
#21
PPG (ch.8,ch.9) unit 4
INT 22
FFFFA4H
FFFFA5H
FFFFA6H
Unused
#22
PPG (ch.A,ch.B) unit 5
INT 23
FFFFA0H
FFFFA1H
FFFFA2H
Unused
#23
16-bit reload timer 0
INT 24
FFFF9CH
FFFF9DH
FFFF9EH
Unused
#24
16-bit reload timer 1
INT 25
FFFF98H
FFFF99H
FFFF9AH
Unused
#25
Input capture 0/1
494
Hardware interrupt
None
.
.
.
APPENDIX D List of MB90590 Series Interrupt Vectors
Table D-1 MB90590 Series Interrupt Vectors (2/2)
Software
interrupt
instruction
Vector
address L
Vector
address M
Vector
address H
Mode
register
Interrupt
No.
INT 26
FFFF94H
FFFF95H
FFFF96H
Unused
#26
Output compare 0/1
INT 27
FFFF90H
FFFF91H
FFFF92H
Unused
#27
Input capture 2/3
INT 28
FFFF8CH
FFFF8DH
FFFF8EH
Unused
#28
Output compare 2/3
INT 29
FFFF88H
FFFF89H
FFFF8AH
Unused
#29
Input capture 4/5
INT 30
FFFF84H
FFFF85H
FFFF86H
Unused
#30
Output compare 4/5
INT 31
FFFF80H
FFFF81H
FFFF82H
Unused
#31
A/D converter
INT 32
FFFF7CH
FFFF7DH
FFFF7EH
Unused
#32
I/O timer/Watch timer
INT 33
FFFF78H
FFFF79H
FFFF7AH
Unused
#33
Serial I/O
INT 34
FFFF74H
FFFF75H
FFFF76H
Unused
#34
Sound generator
INT 35
FFFF70H
FFFF71H
FFFF72H
Unused
#35
UART 0 RX
INT 36
FFFF6CH
FFFF6DH
FFFF6EH
Unused
#36
UART 0 TX
INT 37
FFFF68H
FFFF69H
FFFF6AH
Unused
#37
UART 1 RX
INT 38
FFFF64H
FFFF65H
FFFF66H
Unused
#38
UART 1 TX
INT 39
FFFF60H
FFFF61H
FFFF62H
Unused
#39
UART 2 RX
INT 40
FFFF5CH
FFFF5DH
FFFF5EH
Unused
#40
UART 2 TX
INT 41
FFFF58H
FFFF59H
FFFF5AH
Unused
#41
Flash Memory
INT 42
FFFF54H
FFFF55H
FFFF56H
Unused
#42
Delayed interrupt
INT 43
FFFF50H
FFFF51H
FFFF52H
Unused
#43
None
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
INT 254
FFFC04H
FFFC05H
FFFC06H
Unused
#254
None
INT 255
FFFC00H
FFFC01H
FFFC02H
Unused
#255
None
Hardware interrupt
.
.
.
495
APPENDIX D List of MB90590 Series Interrupt Vectors
■ Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers
Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (1/2)
Interrupt cause
496
EI2OS
clear
Interrupt vector
Interrupt control
register
Number
Address
Number
Address
Reset
N
#08
FFFFDCH
—
—
INT9 instruction
N
#09
FFFFD8H
—
—
Exception
N
#10
FFFFD4H
—
—
Timebase timer
N
#11
FFFFD0H
External interrupt (INT0
to INT7)
Y1
#12
FFFFCCH
ICR00
0000B0H
CAN 0 RX
N
#13
FFFFC8H
ICR01
CAN 0 TX/NS
N
#14
FFFFC4H
0000B1H
CAN 1 RX
N
#15
FFFFC0H
ICR02
CAN 1 TX/NS
N
#16
FFFFBCH
0000B2H
PPG (ch.0,ch.1) unit 0
N
#17
FFFFB8H
ICR03
PPG (ch.2,ch.3) unit 1
N
#18
FFFFB4H
0000B3H
PPG (ch.4,ch.5) unit 2
N
#19
FFFFB0H
ICR04
PPG (ch.6,ch.7) unit 3
N
#20
FFFFACH
0000B4H
PPG (ch.8,ch.9) unit 4
N
#21
FFFFA8H
ICR05
PPG (ch.A,ch.B) unit 5
N
#22
FFFFA4H
0000B5H
16-bit reload timer 0
Y1
#23
FFFFA0H
ICR06
16-bit reload timer 1
Y1
#24
FFFF9CH
0000B6H
Input capture 0/1
Y1
#25
FFFF98H
ICR07
Output compare 0/1
Y1
#26
FFFF94H
0000B7H
Input capture 2/3
Y1
#27
FFFF90H
ICR08
Output compare 2/3
Y1
#28
FFFF8CH
0000B8H
Input capture 4/5
Y1
#29
FFFF88H
ICR09
Output compare 4/5
Y1
#30
FFFF84H
0000B9H
A/D converter
Y1
#31
FFFF80H
ICR10
I/O timer/Watch timer
N
#32
FFFF7CH
0000BAH
Serial I/O
Y1
#33
FFFF78H
ICR11
Sound generator
N
34
FFFF74H
0000BBH
APPENDIX D List of MB90590 Series Interrupt Vectors
Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (2/2)
Interrupt cause
EI2OS
clear
Interrupt vector
Number
Address
UART 0 RX
Y2
35
FFFF70H
UART 0 TX
Y1
36
FFFF6CH
UART 1 RX
Y2
37
FFFF68H
UART 1 TX
Y1
38
FFFF64H
UART 2 RX
Y2
39
FFFF60H
UART 2 TX
Y1
40
FFFF5CH
Flash memory
N
41
FFFF58H
Delayed interrupt
N
42
FFFF54H
Interrupt control
register
Number
Address
ICR12
0000BCH
ICR13
0000BDH
ICR14
0000BEH
ICR15
0000BFH
Y1: An EI2OS interrupt clear signal or EI2OS register read access clears the interrupt
request flag.
Y2: An EI2OS interrupt clear signal or EI2OS register read access clears the interrupt
request flag. A stop request is issued.
N: An EI2OS interrupt clear signal does not clear the interrupt request flag.
Notes: • For a peripheral module having two interrupt causes for one interrupt number, an EI2OS
interrupt clear signal clears both interrupt request flags.
• When EI2OS ends, an EI2OS clear signal is sent to every interrupt flag assigned to each
interrupt number.
• EI2OS is activated when one of two interrupts assigned to an interrupt control register
(ICR) is caused while EI2OS is enabled. This means that an EI2OS descriptor that
should essentially be specific to each interrupt cause is shared by two interrupts.
Therefore, while one interrupt is enabled, the other interrupt must be disabled.
497
APPENDIX D List of MB90590 Series Interrupt Vectors
498
INDEX
INDEX
The index follows on the next page.
This is listed in alphabetic order.
499
INDEX
Index
Numerics
A
16-bit
16-bit Free-running Timer......................... 126, 128
16-bit Free-running Timer Block Diagram .......... 129
16-bit Free-running Timer Operation.................. 134
16-bit Free-running Timer Timing ..................... 135
16-bit Input Capture ......................................... 128
16-bit Output Compare ..................................... 128
16-bit Reload Timer Register............................. 154
Block Diagram of 16-bit I/O Timer .................... 127
Block Diagram of 16-bit Reload Timer............... 153
Input Pin Functions of
16-bit Reload Timer
(in Internal Clock Mode)...................... 160
Internal Clock Operation of 16-bit
Reload Timer ...................................... 159
Outline of 16-bit Reload Timer
(with Event Count Function) ................ 152
Output Pin Functions of 16-bit
Reload Timer ...................................... 162
Register Layout of 16-bit Timer Register (TMR)/
16-bit Reload Register (TMRLR).......... 158
Underflow Operation of 16-bit
Reload Timer ...................................... 161
24-bit
24-bit Operand Specification ............................... 23
8/16-bit
8/16-bit PPG Interrupts ..................................... 189
8/16-bit PPG Output Operation.......................... 186
8/16-bit PPG Registers...................................... 177
Controlling Pin Output of
8/16-bit PPG Pulses ............................. 188
Function of 8/16-bit PPG .................................. 174
Initial Values of 8/16-bit PPG Hardware............. 190
Operation Modes of 8/16-bit PPG ...................... 185
Operations of 8/16-bit PPG ............................... 185
Relationship between 8/16-bit PPG Reload Value and
Pulse Width ........................................ 186
Selecting a Count Clock for 8/16-bit PPG ........... 187
8-bit
Block Diagram of 8-bit PPG.............................. 175
A
500
Accumulator (A)................................................ 30
A/D
A/D Control Status Register 0 (ADCS0) ............ 208
A/D Control Status Register 1 (ADCS1) ............ 211
A/D Data Registers 0/1
(ADCR1 and ADCR0)......................... 214
A/D Converter
A/D Converter Registers................................... 207
Block Diagram of A/D Converter ...................... 206
Features of A/D Converter ................................ 204
Acceptance
Acceptance Filtering ........................................ 319
Acceptance Mask Registers 0/1
(AMR0/AMR1) .................................. 309
Acceptance Mask Select Register (AMSR)......... 307
Setting Acceptance Filter .................................. 323
Access Mode
Memory Access Mode...................................... 102
Accumulator
Accumulator (A)................................................ 30
Activation
Activation ....................................................... 123
ADCR
A/D Data Registers 0/1
(ADCR1 and ADCR0)......................... 214
ADCS
A/D Control Status Register 0 (ADCS0) ............ 208
A/D Control Status Register 1 (ADCS1) ............ 211
Address Detection
Program Address Detection Control Status Register
(PACSR)............................................ 355
Program Address Detection Registers
(PADR0 and PADR1) ......................... 355
Address Generation
Address Generation Types .................................. 21
Address Match
Block Diagram of the Address Match Detection
Function............................................. 354
Operation of the Address Match Detection
Function............................................. 357
System Configuration Example of the Address Match
Detection Function.............................. 358
Addressing
Addressing ...................................................... 430
Direct Addressing ............................................ 432
Indirect Addressing .......................................... 438
INDEX
ADER
Analog Input Enable Register (ADER)............... 112
Alternative
Alternative Mode ............................................. 370
Amplitude
Amplitude Data Register (SGAR)...................... 349
AMR
Acceptance Mask Registers 0/1
(AMR0/AMR1) .................................. 309
AMSR
Acceptance Mask Select Register (AMSR)......... 307
Analog
Analog Input Enable Register............................ 205
Analog Input Enable Register (ADER)............... 112
Application
Application Example........................................ 250
Asynchronous
CLK Asynchronous Baud Rate.......................... 239
B
Bank
Bank Select Prefix.............................................. 38
Register Bank .................................................... 36
Bank Addressing
Bank Addressing Types ...................................... 24
BAP
Buffer Address Pointer (BAP) ............................. 63
Baud Rate
CLK Asynchronous Baud Rate.......................... 239
CLK Synchronous Baud Rate............................ 239
Bit Timing
Bit Timing Register (BTR) ............................... 292
Setting Bit Timing............................................ 323
Block Diagram
16-bit Free-running Timer Block Diagram.......... 129
Block Diagram .............................................. 5, 83
Block Diagram of 16-bit I/O Timer.................... 127
Block Diagram of 16-bit Reload Timer .............. 153
Block Diagram of 8-bit PPG ............................. 175
Block Diagram of A/D Converter ...................... 206
Block Diagram of CAN Controller .................... 273
Block Diagram of Delayed Interrupt .................... 70
Block Diagram of DTP/External Interrupts......... 194
Block Diagram of ROM Mirroring Module ........ 362
Block Diagram of Sound Generator ................... 344
Block Diagram of Stepping Motor
Controller........................................... 336
Block Diagram of the Address Match Detection
Function............................................. 354
Block Diagram of the Entire Flash Memory........ 368
Block Diagram of Timebase Timer .................... 114
Block Diagram of Watch Timer......................... 166
Input Capture Block Diagram............................ 145
Output Compare Block Diagram ....................... 136
Serial I/O Block Diagram ..................................254
UART0 Block Diagram.....................................229
Watch-dog Timer Block Diagram ......................120
BTR
Bit Timing Register (BTR) ................................292
Buffer
Buffer Address Pointer (BAP) .............................63
Bus Mode
Bus Mode Setting Bits ......................................104
Bus Operation
Conditions for Canceling Bus Operation Stop
(HALT=0) ..........................................287
Conditions for Setting Bus Operation Stop
(HALT=1) ..........................................287
State during Bus Operation Stop (HALT=1)........287
BVALR
Message Buffer Valid Register (BVALR) ...........295
BY
RST and RY/BY timing ....................................492
RY/BY Timing During Writing/erasing ..............491
C
Calculating
Calculating the Execution Cycle Count...............447
CAN
CAN Control Status Register (CSR) ...................284
CAN Controller
Block Diagram of CAN Controller .....................273
Canceling a Transmission Request from the
CAN Controller ...................................317
Caution for Using CAN Controller .....................332
Completing Transmission of the
CAN Controller ...................................318
Features of CAN Controller ...............................272
Reception Flowchart of the CAN Controller........322
Starting Transmission of the
CAN Controller ...................................317
Transmission Flowchart of the
CAN Controller ...................................318
Cancellation
Delayed Interrupt Cause Issuance/Cancellation
Register (DIRR: Delayed Interrupt Request
Register) ..............................................71
CCR
Condition Code Register (CCR) ...........................32
CDCR
Serial I/O Prescaler (CDCR) ..............................261
CE
Write,Data Polling,Read (CE control).................490
Chip Erase
Chip Erase/sector Erase Command
Sequence ............................................490
Circuits
Input-Output Circuits ..........................................12
501
INDEX
CKSCR
Clock Selection Register (CKSCR) ...................... 87
CLK
CLK Asynchronous Baud Rate .......................... 239
CLK Synchronous Baud Rate ............................ 239
Clock
Clock Selection Register (CKSCR) ...................... 87
Initializing the Machine Clock............................. 98
Internal and External Clock ............................... 242
Notes on Clock Generator ................................... 74
Status Transition of Clock Selection..................... 99
Switching between Main Clock and
PLL Clock ............................................ 98
CMR
Common Register Bank Prefix (CMR) ................. 39
Command Sequence
Chip Erase/sector Erase Command
Sequence ............................................ 490
Command Sequence Table ................................ 374
Common
Common Register Bank Prefix (CMR) ................. 39
Compare
Sample of a Output Waveform when Compare
Registers 0 and 1 are Used
(The Initial Output Value is "0".) .......... 141
Compare Register
Sample of a Output Waveform with Two Compare
Registers
(The Initial Output Value is "0".) .......... 142
Condition Code Register
Condition Code Register (CCR)........................... 32
Continuous Mode
Continuous Mode ............................................. 216
Starting EI2OS in Continuous Mode................... 221
Controller
Block Diagram of Stepping Motor
Controller ........................................... 336
Stepping Motor Controller Registers .................. 337
Conversion
Conversion Data Protection............................... 225
Conversion Using EI2OS .................................. 218
Flow of Conversion Data Protection Function
(When EI2OS is Used) ......................... 226
Notes on using the Conversion Data Protection
Function ............................................. 226
Count Clock
Selecting a Count Clock for 8/16-bit PPG ........... 187
Counter
Clearing the Counter upon a Match with Output
Compare Resister 0 ............................. 135
Counter Operation State.................................... 163
Data Counter (DCT) ........................................... 62
External Event Counter..................................... 160
502
CPU
Intermittent CPU Operation ................................ 97
Outline of CPU.................................................. 20
Outline of CPU Memory Space ........................... 21
CSR
CAN Control Status Register (CSR) .................. 284
D
Data Frame
Processing for Reception of Data Frame and
Remote Frame .................................... 320
Data Polling
Data Polling .................................................... 491
Write,Data Polling,Read (CE control) ................ 490
Write,Data Polling,Read (WE control) ............... 489
Data Protection
Conversion Data Protection .............................. 225
Flow of Conversion Data Protection Function
(When EI2OS is Used)......................... 226
Notes on using the Conversion Data Protection
Function............................................. 226
Data Register
Data Register x (x=0 to 15) (DTRx)................... 315
DCT
Data Counter (DCT)........................................... 62
DDR
Port Direction Register (DDR0 to DDR9) .......... 111
Decrement
Decrement Grade Register (SGDR) ................... 350
Description
Description of Instruction Presentation Items and
Symbols ............................................. 450
Direct Addressing
Direct Addressing ............................................ 432
DIRR
Delayed Interrupt Cause Issuance/Cancellation
Register (DIRR: Delayed Interrupt Request
Register) ............................................. 71
DIV A
Precautions for Use of "DIV A,Ri" and "DIVW
A,RWi" Instructions.............................. 41
Use of the "DIV A,Ri" and "DIVW A,RWi"
Instructions without Precautions ............. 42
DIVW A
Precautions for Use of "DIV A,Ri" and "DIVW
A,RWi" Instructions.............................. 41
Use of the "DIV A,Ri" and "DIVW A,RWi"
Instructions without Precautions ............. 42
DLC
DLC Register x (x=0 to 15) (DLCRx) ................ 314
List of Message Buffers
(DLC Registers and Data Registers)...... 279
DLCRx
DLC Register x (x=0 to 15) (DLCRx) ................ 314
INDEX
DQ
Data Polling Flag (DQ7)................................... 378
Sector Erase Timer Flag (DQ3) ......................... 382
Timing Limit Exceeded Flag (DQ5)................... 381
Toggle Bit Flag (DQ6) ..................................... 380
Toggle Bit-2 Flag (DQ2) .................................. 383
DTP
Block Diagram of DTP/External Interrupts......... 194
DTP operation ................................................. 199
DTP/External Interrupts Registers ..................... 195
DTP/Interrupt Enable Register (ENIR: Interrupt
request enable register) ........................ 196
DTP/Interrupt Source Register (EIRR: External
interrupt request register) ..................... 196
Notes on Using DTP/External Interrupts ............ 201
Outline of DTP/External Interrupts .................... 194
Switching between External Interrupt and DTP
Requests............................................. 200
DTRx
Data Register x (x=0 to 15) (DTRx)................... 315
E
Effective Address Field
Effective Address Field ............................ 431, 449
EI2OS
Conversion Using EI2OS .................................. 218
EI2OS (Extended intelligent I/O service) ............ 249
EI2OS Operation Flow........................................ 66
EI2OS Status Register (ISCS).............................. 64
Extended Intelligent I/O Service (EI2OS) ....... 45, 60
Flow of Conversion Data Protection Function
(When EI2OS is Used)......................... 226
Intelligent I/O Service (EI2OS) Function and
Interrupts............................................ 152
Starting EI2OS in Continuous Mode .................. 221
Starting EI2OS in Single Mode.......................... 219
Starting EI2OS in Stop Mode ............................ 223
EIRR
DTP/Interrupt Source Register (EIRR: External
interrupt request register) ..................... 196
ELVR
Request Level Setting Register (ELVR: External level
register).............................................. 197
Enable Sector Protect
Enable Sector Protect/Verify Sector Protect........ 492
ENIR
DTP/Interrupt Enable Register (ENIR: Interrupt
request enable register) ........................ 196
Erasing
Erasing all Data in the Flash Memory
(Erasing Chips) ................................... 389
Erasing Optional Data (Erasing Sectors) in the Flash
Memory ............................................. 390
Erasing Sectors in the Flash Memory ................. 390
Restarting Erasing of Flash Memory
Sectors................................................393
Suspending Erasing of Flash Memory
Sectors................................................392
Writing to/Erasing Flash Memory ......................366
Error Counters
Receive and Transmit Error Counters
(RTEC)...............................................291
Example
Application Example ........................................250
Exceptions
Exceptions .........................................................46
Execution Cycle Count
Calculating the Execution Cycle Count...............447
Execution Cycle Count......................................446
External
Block Diagram of DTP/External Interrupts .........194
DTP/External Interrupts Registers ......................195
External Event Counter .....................................160
External Interrupt Operation ..............................198
External Shift Clock Mode ................................263
Notes on Using DTP/External Interrupts .............201
Outline of DTP/External Interrupts.....................194
Switching between External Interrupt and DTP
Requests .............................................200
External Clock
Internal and External Clock ...............................242
F
F2MC-16LX Instruction List
F2MC-16LX Instruction List .............................453
Features
Features ...............................................................3
Fetch
Sample of Input Capture Fetch Timing ...............148
Filter
Setting Acceptance Filter...................................323
Filtering
Acceptance Filtering .........................................319
Flag
Data Polling Flag (DQ7) ...................................378
Flag Set Timings for a Receive Operation
(in Mode 0,Mode 1,or Mode 3) .............246
Flag Set Timings for a Receive Operation
(in Mode 2) .........................................247
Flag Set Timings for a Transmit Operation..........248
Hardware Sequence Flags..................................376
Sector Erase Timer Flag (DQ3)..........................382
Set Timings of the Six Flags ..............................245
Status Flag during Transmit and
Receive Operation ...............................249
Timing Limit Exceeded Flag (DQ5) ...................381
Toggle Bit Flag (DQ6) ......................................380
Toggle Bit-2 Flag (DQ2) ...................................383
503
INDEX
Flag Change
Flag Change Disable Prefix (NCC) ...................... 39
Flash
Example of Minimum Connection to the Flash
Microcomputer Programmer
(Power Supplied from the Programmer)
.......................................................... 412
Example of Minimum Connection to the Flash
Microcomputer Programmer
(User Power Supply Used) ................... 410
Flash Memory
2M/3M-bit Flash Memory Features.................... 366
Block Diagram of the Entire Flash Memory........ 368
Detailed Explanation of Flash Memory
Write/Erase......................................... 385
Erasing all Data in the Flash Memory
(Erasing Chips) ................................... 389
Erasing Optional Data (Erasing Sectors) in the Flash
Memory ............................................. 390
Erasing Sectors in the Flash Memory ................. 390
Flash Memory Control Signals .......................... 370
Flash Memory Control Status Register
(FMCS) .............................................. 372
Flash Memory Mode ........................................ 370
Flash Memory Register..................................... 367
Notes on using Flash Memory ........................... 394
Programming Example of 2M-bit
Flash Memory..................................... 396
Reset Vector Address in Flash Memory.............. 395
Restarting Erasing of Flash Memory
Sectors ............................................... 393
Sector Configuration of the 2M/3M-bit
Flash Memory..................................... 368
Setting the Flash Memory to the Read/Reset
State................................................... 386
Suspending Erasing of Flash Memory
Sectors ............................................... 392
Writing Data to the Flash Memory ..................... 387
Writing to the Flash Memory............................. 387
Writing to/Erasing Flash Memory ...................... 366
Flowchart
Reception Flowchart of the CAN Controller ....... 322
Transmission Flowchart of the
CAN Controller................................... 318
FMCS
Flash Memory Control Status Register
(FMCS) .............................................. 372
Frame Format
Setting Frame Format ....................................... 323
Free-running
16-bit Free-running Timer Operation.................. 134
Free-running Timer
16-bit Free-running Timer......................... 126, 128
16-bit Free-running Timer Block Diagram .......... 129
16-bit Free-running Timer Timing ..................... 135
504
Frequency
Frequency Data Register (SGFR) ...................... 348
Oscillating Clock Frequency and Serial Clock Input
Frequency .......................................... 405
Function
Intelligent I/O Service (EI2OS) Function and
Interrupts ........................................... 152
G
General-Purpose
General-Purpose Registers .................................. 29
Generator
Notes on Clock Generator................................... 74
H
HALT
Conditions for Canceling Bus Operation Stop
(HALT=0).......................................... 287
Conditions for Setting Bus Operation Stop
(HALT=1).......................................... 287
State during Bus Operation Stop (HALT=1) ....... 287
Handling
Handling the Device........................................... 14
Hour
Second/Minute/Hour Registers
(WTSR/WTMR/WTHR) ..................... 172
I
I/O
Block Diagram of 16-bit I/O Timer.................... 127
EI2OS (Extended intelligent I/O service) ............ 249
Extended Intelligent I/O Service (EI2OS) ....... 45, 60
Extended Intelligent I/O Service Descriptor
(ISD) ................................................... 62
I/O Port Registers ............................................ 109
I/O Register Address Pointer (IOA) ..................... 63
Intelligent I/O Service (EI2OS) Function and
Interrupts ........................................... 152
I/O Maps
I/O Maps......................................................... 416
I/O Ports
I/O Ports ......................................................... 108
ICR
Interrupt Control Register (ICR).......................... 48
ICS
Input Capture Control Status Register
(ICS0/1) ............................................. 146
ID
ID Register x (x=0 to 15) (IDRx)....................... 312
List of Message Buffers (ID Registers) .............. 276
Setting ID........................................................ 323
IDE
IDE Register (IDER) ........................................ 296
INDEX
IDER
IDE Register (IDER) ........................................ 296
IDRx
ID Register x (x=0 to 15) (IDRx)....................... 312
ILM
Interrupt Level Mask Register (ILM) ................... 34
Impedance
Input Impedance .............................................. 205
Indirect Addressing
Indirect Addressing .......................................... 438
Initial Values
Initial Values of 8/16-bit PPG Hardware ............ 190
Input
Input-Output Circuits ......................................... 12
Input Capture
16-bit Input Capture ......................................... 128
Input Capture................................................... 144
Input Capture (2 Channels per one Module)........ 127
Input Capture Block Diagram............................ 145
Input Capture Control Status Register
(ICS0/1) ............................................. 146
Input Capture Data Register (IPCP0/1)............... 146
Input Capture Input Timing............................... 149
Sample of Input Capture Fetch Timing............... 148
Instruction
Description of Instruction Presentation Items and
Symbols ............................................. 450
Exception due to Execution of an Undefined
Instruction ............................................ 68
Execution of an Undefined Instruction ................. 68
F2MC-16LX Instruction List............................. 453
Instruction Types ............................................. 429
Interrupt Disable Instructions .............................. 40
Restrictions on Interrupt Disable Instructions and
Prefix Instructions ................................. 40
Structure of Instruction Map ............................. 467
Instruction Presentation Items and Symbols
Description of Instruction Presentation Items and
Symbols ............................................. 450
Interface
Interrupt Function of the Extended Serial I/O
Interface............................................. 269
Internal
Internal and External Clock............................... 242
Internal Shift Clock Mode................................. 263
Internal Clock Mode
Input Pin Functions of
16-bit Reload Timer
(in Internal Clock Mode) ..................... 160
Interrupt
8/16-bit PPG Interrupts..................................... 189
Block Diagram of Delayed Interrupt .................... 70
Block Diagram of DTP/External Interrupts......... 194
Delayed Interrupt Cause Issuance/Cancellation
Register (DIRR: Delayed Interrupt Request
Register) ..............................................71
Delayed Interrupt Occurrence ..............................72
DTP/External Interrupts Registers ......................195
DTP/Interrupt Enable Register (ENIR: Interrupt
request enable register).........................196
DTP/Interrupt Source Register (EIRR: External
interrupt request register)......................196
External Interrupt Operation ..............................198
Hardware Interrupt Operation ..............................54
Hardware Interrupts ......................................44, 53
Intelligent I/O Service (EI2OS) Function and
Interrupts ............................................152
Interrupt Causes,Interrupt Vectors,and Interrupt
Control Registers .................................496
Interrupt Control Register (ICR) ..........................48
Interrupt Disable Instructions...............................40
Interrupt Flow ....................................................51
Interrupt Function of the Extended Serial I/O
Interface .............................................269
Interrupt Level Mask Register (ILM)....................34
Interrupt Vector ..................................................47
Interval Interrupt Function.................................117
List of MB90590 Series Interrupt Vectors
....................................................58, 494
Listing of Interrupt Vectors .................................47
Multiple Interrupts..............................................57
Notes on Using DTP/External Interrupts .............201
Occurrence and Release of Hardware
Interrupt................................................55
Outline of DTP/External Interrupts.....................194
Outline of Interrupts............................................44
Reception Interrupt Enable Register (RIER)........306
Restrictions on Interrupt Disable Instructions and
Prefix Instructions..................................40
Software Interrupt...............................................58
Software Interrupt Operation ...............................58
Software Interrupts .............................................45
Structure of Hardware Interrupt ...........................53
Structure of Software Interrupts ...........................58
Switching between External Interrupt and DTP
Requests .............................................200
Transmission Interrupt Enable Register
(TIER)................................................302
IOA
I/O Register Address Pointer (IOA)......................63
IPCP
Input Capture Data Register (IPCP0/1) ...............146
ISCS
EI2OS Status Register (ISCS) ..............................64
ISD
Extended Intelligent I/O Service Descriptor
(ISD) ....................................................62
505
INDEX
Issuance
Delayed Interrupt Cause Issuance/Cancellation
Register (DIRR: Delayed Interrupt Request
Register).............................................. 71
L
Last Event
Last Event Indicator Register (LEIR) ................. 289
LEIR
Last Event Indicator Register (LEIR) ................. 289
Limit
Timing Limit Exceeded Flag (DQ5) ................... 381
Lower-Power
Outline of Lower-power Control Circuit ............... 82
Low-Power
Low-Power Mode Control Register...................... 84
Low-Power Mode Control Register
(LPMCR) ............................................. 85
Low-Power Mode Operation ............................... 89
Note: Low-Power Mode Control Register
Access.................................................. 90
Notes on the Transition to Low-Power Mode ........ 90
LPMCR
Low-Power Mode Control Register
(LPMCR) ............................................. 85
M
Machine Clock
Initializing the Machine Clock............................. 98
Main Clock
Switching between Main Clock and
PLL Clock ............................................ 98
Map
Memory Space Map ........................................... 22
Mask
Acceptance Mask Registers 0/1
(AMR0/AMR1) .................................. 309
Acceptance Mask Select Register (AMSR) ......... 307
Match
Block Diagram of the Address Match Detection
Function ............................................. 354
Operation of the Address Match Detection
Function ............................................. 357
System Configuration Example of the Address Match
Detection Function .............................. 358
MB90590
List of MB90590 Series Interrupt Vectors
.................................................... 58, 494
Memory
Memory Access Modes..................................... 102
Memory Space
Memory Space Map ........................................... 22
Multi-byte Data Allocation in Memory Space ....... 26
506
Outline of CPU Memory Space ........................... 21
Message Buffer
List of Message Buffers (Data Registers) ........... 281
List of Message Buffers
(DLC Registers and Data Registers)...... 279
List of Message Buffers (ID Registers) .............. 276
Message Buffer Control Registers ..................... 283
Message Buffer Valid Register (BVALR) .......... 295
Message Buffers ...................................... 283, 311
Procedure for Reception by Message Buffer
(x) ..................................................... 327
Procedure for Transmission by Message Buffer
(x) ..................................................... 325
Setting Configuration of Multi-level Message
Buffer ................................................ 329
Minute
Second/Minute/Hour Registers
(WTSR/WTMR/WTHR) ..................... 172
Mirroring
Block Diagram of ROM Mirroring Module ........ 362
ROM Mirroring Register (ROMM).................... 363
Mode Data
Mode Data ...................................................... 104
Mode Pin
Mode pins ....................................................... 103
Multi-byte
Accessing Multi-byte Data.................................. 26
Multi-byte Data Allocation in Memory Space....... 26
Multi-level
Setting Configuration of Multi-level Message
Buffer ................................................ 329
N
NCC
Flag Change Disable Prefix (NCC) ...................... 39
Negative Clock
Negative Clock Operation................................. 270
O
OCS
Control Status Register of Output Compare
(OCS0/1) ........................................... 138
Operand
24-bit Operand Specification............................... 23
Operation
Notes on Operation ............................................ 70
Oscillating Clock
Oscillating Clock Frequency and Serial Clock Input
Frequency .......................................... 405
Oscillation
Setting the Oscillation Stabilization
Wait Time ...................................... 95, 96
INDEX
Others
Others ............................................................... 59
Outline
Outline of CPU .................................................. 20
Outline of CPU Memory Space ........................... 21
Output
Input-Output Circuits ......................................... 12
Output Compare
16-bit Output Compare ..................................... 128
Clearing the Counter upon a Match with Output
Compare Resister 0 ............................. 135
Control Status Register of Output Compare
(OCS0/1)............................................ 138
Output Compare .............................................. 136
Output Compare
(2 Channels per One Module)............... 126
Output Compare Block Diagram ....................... 136
Output Compare Register.................................. 137
Output Compare Timing ................................... 142
Overall
List of Overall Control Registers ....................... 274
Overall Control
Overall Control Registers.................................. 283
Overrun
Receive Overrun .............................................. 320
Receive Overrun Register (ROVRR) ................. 305
P
Package
Package Dimensions ............................................ 6
PACSR
Program Address Detection Control Status Register
(PACSR)............................................ 355
PADR
Program Address Detection Registers
(PADR0 and PADR1) ......................... 355
Parity Bit
Parity Bit......................................................... 244
Patch
Example of Program Patch Processing ............... 359
PC
Program Counter (PC) ........................................ 35
PDR
Port data Register (PDR0 to PDR9) ................... 110
Pin Assignment
Pin Assignment.................................................... 7
Pin Functions
Pin Functions....................................................... 8
PLL
Switching between Main Clock and
PLL Clock............................................ 98
Polling
Data Polling Flag (DQ7)................................... 378
Port
Port data Register (PDR0 to PDR9) ....................110
Port Direction Register (DDR0 to DDR9) ...........111
Power Supply
Example of Serial Programming Connection (Power
Supplied from the Programmer) ............408
Example of Serial Programming Connection
(User Power Supply Used)....................406
PPG
8/16-bit PPG Interrupts .....................................189
8/16-bit PPG Output Operation ..........................186
8/16-bit PPG Registers ......................................177
Block Diagram of 8-bit PPG ..............................175
Controlling Pin Output of
8/16-bit PPG Pulses .............................188
Function of 8/16-bit PPG...................................174
Initial Values of 8/16-bit PPG Hardware .............190
Operation Modes of 8/16-bit PPG ......................185
Operations of 8/16-bit PPG................................185
PPG0 Operation Mode Control Register
(PPGC0) .............................................178
PPG0/PPG1 Clock Selection Register
(PPG01)..............................................182
PPG1 Operation Mode Control Register
(PPGC1) .............................................180
Relationship between 8/16-bit PPG Reload Value and
Pulse Width.........................................186
Selecting a Count Clock for 8/16-bit PPG ...........187
PPGC
PPG0 Operation Mode Control Register
(PPGC0) .............................................178
PPG1 Operation Mode Control Register
(PPGC1) .............................................180
Precautions
Precautions for Use of "DIV A,Ri" and "DIVW
A,RWi" Instructions...............................41
Use of the "DIV A,Ri" and "DIVW A,RWi"
Instructions without Precautions..............42
Prefix
Bank Select Prefix ..............................................38
Common Register Bank Prefix (CMR) .................39
Consecutive Prefix Codes....................................40
Flag Change Disable Prefix (NCC).......................39
Restrictions on Interrupt Disable Instructions and
Prefix Instructions..................................40
Prescaler
Serial I/O Prescaler (CDCR) ..............................261
PRLH
Reload Register (PRLL/PRLH)..........................184
PRLL
Reload Register (PRLL/PRLH)..........................184
Processor Status
Processor Status (PS) ..........................................32
Product
Product Overview .................................................2
507
INDEX
Program
Example of Program Patch Processing ............... 359
Program Address Detection Control Status Register
(PACSR) ............................................ 355
Program Address Detection Registers
(PADR0 and PADR1).......................... 355
Program Counter
Program Counter (PC) ........................................ 35
Programmer
Example of Minimum Connection to the Flash
Microcomputer Programmer
(Power Supplied from the Programmer)
.......................................................... 412
Example of Minimum Connection to the Flash
Microcomputer Programmer
(User Power Supply Used) ................... 410
Programming
Basic Configuration of MB90F594A/MB90F594G/
MB90F591A/MB90F591G
Serial Programming Connection ........... 402
Programming Example of 2M-bit
Flash Memory..................................... 396
PS
Processor Status (PS).......................................... 32
Pulse
Controlling Pin Output of
8/16-bit PPG Pulses ............................. 188
Pulse Width
Relationship between 8/16-bit PPG Reload Value and
Pulse Width ........................................ 186
PWC
PWM Control 0 Register (PWC0)...................... 338
PWM1&2 Compare Registers
(PWC10/PWC20)................................ 339
PWM
Notes on Changing the PWM Setting Values
.......................................................... 342
PWM Control 0 Register (PWC0)...................... 338
PWM1&2 Compare Registers
(PWC10/PWC20)................................ 339
PWM1&2 Select Registers (PWS10/PWS20)
.......................................................... 340
PWS
PWM1&2 Select Registers (PWS10/PWS20)
.......................................................... 340
R
Rate
Configuration of Rate and Data Register 0
(URD0) .............................................. 236
Rate and Data Register 0 (URD0) Contents ........ 236
RCR
Reception Complete Register (RCR) .................. 303
508
Read Access
Data read by Read Access................................. 489
Receive
Flag Set Timings for a Receive Operation
(in Mode 0,Mode 1,or Mode 3) ............ 246
Flag Set Timings for a Receive Operation
(in Mode 2) ........................................ 247
Status Flag during Transmit and
Receive Operation............................... 249
Received Message
Storing Received Message ................................ 319
Reception
Completing Reception ...................................... 321
Procedure for Reception by Message Buffer
(x) ..................................................... 327
Processing for Reception of Data Frame and
Remote Frame .................................... 320
Reception Flowchart of the CAN Controller ....... 322
Reception Interrupt Enable Register (RIER) ....... 306
Reception Complete
Reception Complete Register (RCR).................. 303
Register
16-bit Reload Timer Register ............................ 154
8/16-bit PPG Registers ..................................... 177
A/D Control Status Register 0 (ADCS0) ............ 208
A/D Control Status Register 1 (ADCS1) ............ 211
A/D Converter Registers................................... 207
A/D Data Registers 0/1
(ADCR1 and ADCR0)......................... 214
Acceptance Mask Registers 0/1
(AMR0/AMR1) .................................. 309
Acceptance Mask Select Register (AMSR)......... 307
Amplitude Data Register (SGAR)...................... 349
Analog Input Enable Register............................ 205
Analog Input Enable Register (ADER) .............. 112
Bit functions of Serial Mode Control Status Register
(SMCS) ............................................. 256
Bit Timing Register (BTR) ............................... 292
CAN Control Status Register (CSR) .................. 284
Clock Selection Register (CKSCR)...................... 87
Common Register Bank Prefix (CMR)................. 39
Configuration of Rate and Data Register 0
(URD0).............................................. 236
Configuration of Serial Mode Control Register 0
(UMC0) ............................................. 231
Control Status Register of Output Compare
(OCS0/1) ........................................... 138
Data Register x (x=0 to 15) (DTRx)................... 315
Decrement Grade Register (SGDR) ................... 350
Delayed Interrupt Cause Issuance/Cancellation
Register (DIRR: Delayed Interrupt Request
Register) ............................................. 71
DLC Register x (x=0 to 15) (DLCRx) ................ 314
DTP/External Interrupts Registers ..................... 195
DTP/Interrupt Enable Register (ENIR: Interrupt
request enable register) ........................ 196
INDEX
DTP/Interrupt Source Register (EIRR: External
interrupt request register) ..................... 196
EI2OS Status Register (ISCS).............................. 64
Flash Memory Control Status Register
(FMCS).............................................. 372
Flash Memory Register..................................... 367
Frequency Data Register (SGFR) ...................... 348
General-Purpose Registers .................................. 29
I/O Port Registers............................................. 109
I/O Register Address Pointer (IOA) ..................... 63
ID Register x (x=0 to 15) (IDRx)....................... 312
IDE Register (IDER) ........................................ 296
Input Capture Control Status Register
(ICS0/1) ............................................. 146
Input Capture Data Register (IPCP0/1)............... 146
Interrupt Causes,Interrupt Vectors,and Interrupt
Control Registers ................................ 496
Interrupt Control Register (ICR) .......................... 48
Interrupt Level Mask Register (ILM) ................... 34
Last Event Indicator Register (LEIR) ................. 289
List of Message Buffers (Data Registers) ........... 281
List of Message Buffers
(DLC Registers and Data Registers)...... 279
List of Message Buffers (ID Registers) .............. 276
List of Overall Control Registers ....................... 274
Low-Power Mode Control Register ..................... 84
Low-Power Mode Control Register
(LPMCR) ............................................. 85
Message Buffer Control Registers ..................... 283
Message Buffer Valid Register (BVALR) .......... 295
Note: Low-Power Mode Control Register
Access ................................................. 90
Output Compare Register.................................. 137
Overall Control Registers.................................. 283
Port data Register (PDR0 to PDR9) ................... 110
Port Direction Register (DDR0 to DDR9) .......... 111
PPG0 Operation Mode Control Register
(PPGC0) ............................................ 178
PPG0/PPG1 Clock Selection Register
(PPG01) ............................................. 182
PPG1 Operation Mode Control Register
(PPGC1) ............................................ 180
Program Address Detection Control Status Register
(PACSR)............................................ 355
Program Address Detection Registers
(PADR0 and PADR1) ......................... 355
PWM Control 0 Register (PWC0)...................... 338
PWM1&2 Compare Registers
(PWC10/PWC20) ............................... 339
PWM1&2 Select Registers (PWS10/PWS20) ..... 340
Rate and Data Register 0 (URD0) Contents ........ 236
Receive Overrun Register (ROVRR) ................. 305
Reception Complete Register (RCR).................. 303
Reception Interrupt Enable Register (RIER) ....... 306
Register Bank .................................................... 36
Register Contents of Timer Control Status Register
(TMCSR) ........................................... 155
Register Layout of 16-bit Timer Register (TMR)/
16-bit Reload Register (TMRLR) ..........158
Register Layout of Timer Control Status Register
(TMCSR)............................................155
Registers not Initialized by Reset Input .................76
Reload Register (PRLL/PRLH)..........................184
Remote Frame Receiving Wait Register
(RFWTR) ...........................................299
Remote Request Receiving Register
(RRTRR) ............................................304
Request Level Setting Register (ELVR: External level
register) ..............................................197
ROM Mirroring Register (ROMM) ....................363
Sample of a Output Waveform when Compare
Registers 0 and 1 are Used
(The Initial Output Value is "0".) ..........141
Second/Minute/Hour Registers
(WTSR/WTMR/WTHR) ......................172
Serial I/O Registers...........................................255
Serial Input Data Register 0 (UIDR0) and Serial
Output Data Register 0 (UODR0)..........235
Serial Mode Control Register 0 (UMC0)
Contents .............................................231
Serial Mode Control Status Register
(SMCS) ..............................................256
Serial Shift Data Register (SDR) ........................260
Serial Status Register 0 (USR0)
Configuration ......................................233
Serial Status Register 0 (USR0) Contents............233
Sound Control Register (SGCR) ........................346
Sound Generator Registers ................................345
Special Registers ................................................27
Stepping Motor Controller Registers ..................337
Sub-second Registers (WTBR) ..........................171
Timebase Timer Control Register (TBTC) ..........115
Timer Control Register (WTCR) ........................169
Timer Counter Control Status Register
(TCCS)...............................................131
Timer Counter Data Register (TCDT).................130
Tone Count Register (SGTR).............................351
Transmission Cancel Register (TCANR) ............300
Transmission Complete Register (TCR)..............301
Transmission Interrupt Enable Register
(TIER)................................................302
Transmission Request Register (TREQR) ...........297
Transmission RTR Register (TRTRR) ................298
UART0 Registers .............................................230
Watch Timer Registers......................................167
Watch-dog Timer Control Register
(WDTC) .............................................121
Register Bank Pointer
Register Bank Pointer (RP)..................................33
Reload
Relationship between 8/16-bit PPG Reload Value and
Pulse Width.........................................186
Reload Register (PRLL/PRLH)..........................184
509
INDEX
Reload Timer
16-bit Reload Timer Register............................. 154
Block Diagram of 16-bit Reload Timer............... 153
Input Pin Functions of
16-bit Reload Timer
(in Internal Clock Mode)...................... 160
Internal Clock Operation of 16-bit
Reload Timer ...................................... 159
Outline of 16-bit Reload Timer
(with Event Count Function) ................ 152
Output Pin Functions of 16-bit
Reload Timer ...................................... 162
Underflow Operation of 16-bit
Reload Timer ...................................... 161
Remote Frame
Processing for Reception of Data Frame and
Remote Frame..................................... 320
Remote Frame Receiving Wait Register
(RFWTR) ........................................... 299
Remote Request
Remote Request Receiving Register
(RRTRR)............................................ 304
Request
Request Level Setting Register (ELVR: External level
register) .............................................. 197
Transmission Request Register (TREQR) ........... 297
Reset
Operation after Reset Release .............................. 75
Registers not Initialized by Reset Input................. 76
Reset Cause Occurrence...................................... 75
Reset Causes...................................................... 78
Reset Vector Address in Flash Memory.............. 395
Resister
Clearing the Counter upon a Match with Output
Compare Resister 0 ............................. 135
Restrictions
Restrictions on Interrupt Disable Instructions and
Prefix Instructions ................................. 40
RFWTR
Remote Frame Receiving Wait Register
(RFWTR) ........................................... 299
Ri
Precautions for Use of "DIV A,Ri" and "DIVW
A,RWi" Instructions .............................. 41
Use of the "DIV A,Ri" and "DIVW A,RWi"
Instructions without Precautions ............. 42
RIER
Reception Interrupt Enable Register (RIER) ....... 306
ROM
Block Diagram of ROM Mirroring Module......... 362
ROM Mirroring Register (ROMM) .................... 363
ROMM
ROM Mirroring Register (ROMM) .................... 363
ROVRR
Receive Overrun Register (ROVRR).................. 305
510
RP
Register Bank Pointer (RP) ................................. 33
RRTRR
Remote Request Receiving Register
(RRTRR) ........................................... 304
RST
RST and RY/BY timing.................................... 492
RTEC
Receive and Transmit Error Counters
(RTEC) .............................................. 291
RTR
Transmission RTR Register (TRTRR) ............... 298
RWi
Precautions for Use of "DIV A,Ri" and "DIVW
A,RWi" Instructions.............................. 41
Use of the "DIV A,Ri" and "DIVW A,RWi"
Instructions without Precautions ............. 42
RY
RST and RY/BY timing.................................... 492
RY/BY Timing During Writing/erasing ............. 491
S
SDR
Serial Shift Data Register (SDR) ....................... 260
Second
Second/Minute/Hour Registers
(WTSR/WTMR/WTHR) ..................... 172
Sector
Sector Configuration of the 2M/3M-bit
Flash Memory .................................... 368
Sector Erase
Chip Erase/sector Erase Command
Sequence............................................ 490
Sector Erase Timer Flag (DQ3) ......................... 382
Sector Protect
Temporary Sector Protect Cancellation .............. 493
Sectors
Restarting Erasing of Flash Memory
Sectors ............................................... 393
Suspending Erasing of Flash Memory
Sectors ............................................... 392
Sequence
Command Sequence Table................................ 374
Hardware Sequence Flags ................................. 376
Serial Clock
Oscillating Clock Frequency and Serial Clock Input
Frequency .......................................... 405
Serial I/O
Interrupt Function of the Extended Serial I/O
Interface............................................. 269
Serial I/O Block Diagram ................................. 254
Serial I/O Operation ................................. 262, 264
Serial I/O Prescaler (CDCR) ............................. 261
Serial I/O Registers .......................................... 255
INDEX
Serial Input
Serial Input Data Register 0 (UIDR0) and Serial
Output Data Register 0 (UODR0) ......... 235
Serial Mode
Bit functions of Serial Mode Control Status Register
(SMCS).............................................. 256
Configuration of Serial Mode Control Register 0
(UMC0) ............................................. 231
Serial Mode Control Register 0 (UMC0)
Contents............................................. 231
Serial Mode Control Status Register
(SMCS).............................................. 256
Serial Output
Serial Input Data Register 0 (UIDR0) and Serial
Output Data Register 0 (UODR0) ......... 235
Serial Programming
Example of Serial Programming Connection (Power
Supplied from the Programmer)............ 408
Example of Serial Programming Connection
(User Power Supply Used) ................... 406
Serial Shift
Serial Shift Data Register (SDR) ....................... 260
Serial Status
Serial Status Register 0 (USR0)
Configuration ..................................... 233
Serial Status Register 0 (USR0) Contents ........... 233
Setting
Recommended Setting...................................... 105
Setting low-power-consumption
Setting low-power-consumption Mode............... 324
SGAR
Amplitude Data Register (SGAR)...................... 349
SGCR
Sound Control Register (SGCR) ........................ 346
SGDR
Decrement Grade Register (SGDR) ................... 350
SGFR
Frequency Data Register (SGFR) ...................... 348
SGTR
Tone Count Register (SGTR) ............................ 351
Shift Clock
External Shift Clock Mode................................ 263
Internal Shift Clock Mode................................. 263
Shift Operation
Shift Operation Start/Stop Timing ..................... 266
Single Mode
Single Mode .................................................... 216
Starting EI2OS in Single Mode.......................... 219
Sleep Mode
Releasing Sleep Mode ........................................ 91
Transition to Sleep Mode.................................... 91
SMCS
Bit functions of Serial Mode Control Status Register
(SMCS).............................................. 256
Serial Mode Control Status Register
(SMCS) ..............................................256
Sound Control
Sound Control Register (SGCR) ........................346
Sound Generator
Block Diagram of Sound Generator....................344
Sound Generator Registers ................................345
SSP
User Stack Pointer (USP) and System Stack Pointer
(SSP)....................................................31
Stabilization
Setting the Oscillation Stabilization
Wait Time.......................................95, 96
Standby Mode
Releasing Hardware Standby Mode ......................96
Transition to Hardware Standby Mode..................96
Stepping Motor
Block Diagram of Stepping Motor
Controller ...........................................336
Stepping Motor Controller Registers ..................337
Stop Mode
Releasing Stop Mode ..........................................94
Starting EI2OS in Stop Mode .............................223
Stop Mode .......................................................217
Transition to Stop Mode ......................................94
Structure
Structure ............................................................61
Structure of Instruction Map ..............................467
Sub-second
Sub-second Registers (WTBR) ..........................171
Switching
Switching between External Interrupt and DTP
Requests .............................................200
Switching between Main Clock and
PLL Clock ............................................98
Synchronous
CLK Synchronous Baud Rate ............................239
System Stack Pointer
User Stack Pointer (USP) and System Stack Pointer
(SSP)....................................................31
T
TBTC
Timebase Timer Control Register (TBTC) ..........115
TCANR
Transmission Cancel Register (TCANR) ............300
TCCS
Timer Counter Control Status Register
(TCCS)...............................................131
TCDT
Timer Counter Data Register (TCDT).................130
TCR
Transmission Complete Register (TCR)..............301
511
INDEX
TIER
Transmission Interrupt Enable Register
(TIER) ............................................... 302
Timebase
Block Diagram of Timebase Timer .................... 114
Timebase Counter
Timebase Counter ............................................ 117
Timebase Timer
Outline of Timebase Timer................................ 114
Timebase Timer Control Register (TBTC) .......... 115
Timer
16-bit Free-running Timer................................. 126
16-bit Free-running Timer Operation.................. 134
Block Diagram of 16-bit I/O Timer .................... 127
Register Contents of Timer Control Status Register
(TMCSR) ........................................... 155
Register Layout of Timer Control Status Register
(TMCSR) ........................................... 155
Sector Erase Timer Flag (DQ3) ......................... 382
Timer Control Register (WTCR)........................ 169
Timer Counter Control Status Register
(TCCS) .............................................. 131
Timer Counter Data Register (TCDT) ................ 130
Timer Register
Register Layout of 16-bit Timer Register (TMR)/
16-bit Reload Register (TMRLR).......... 158
Timing
Flag Set Timings for a Receive Operation
(in Mode 0,Mode 1,or Mode 3)............. 246
Flag Set Timings for a Receive Operation
(in Mode 2)......................................... 247
Flag Set Timings for a Transmit Operation ......... 248
Output Compare Timing ................................... 142
RST and RY/BY Timing................................... 492
RY/BY Timing During Writing/erasing.............. 491
Set Timings of the Six Flags.............................. 245
Shift Operation Start/Stop Timing...................... 266
Timing Limit Exceeded Flag (DQ5) ................... 381
TMCSR
Register Contents of Timer Control Status Register
(TMCSR) ........................................... 155
Register Layout of Timer Control Status Register
(TMCSR) ........................................... 155
TMR
Register Layout of 16-bit Timer Register (TMR)/
16-bit Reload Register (TMRLR).......... 158
TMRLR
Register Layout of 16-bit Timer Register (TMR)/
16-bit Reload Register (TMRLR).......... 158
Toggle Bit
Toggle Bit ....................................................... 491
Toggle Bit Flag (DQ6)...................................... 380
Toggle Bit-2 Flag (DQ2)................................... 383
Tone Count
Tone Count Register (SGTR) ............................ 351
512
Transfer
Transfer Data Format ....................................... 243
Transition
Notes on the Transition to Low-Power Mode........ 90
Status Transition of Clock Selection .................... 99
Transition to Sleep Mode.................................... 91
Transmission
Completing Transmission of the
CAN Controller .................................. 318
Procedure for Transmission by Message Buffer
(x) ..................................................... 325
Starting Transmission of the
CAN Controller .................................. 317
Transmission Flowchart of the
CAN Controller .................................. 318
Transmission Interrupt Enable Register
(TIER) ............................................... 302
Transmission Request Register (TREQR)........... 297
Transmission RTR Register (TRTRR) ............... 298
Transmission Cancel
Transmission Cancel Register (TCANR)............ 300
Transmission Complete
Transmission Complete Register (TCR) ............. 301
Transmission Request
Canceling a Transmission Request from the
CAN Controller .................................. 317
Transmit
Flag Set Timings for a Transmit Operation ......... 248
Status Flag during Transmit and
Receive Operation............................... 249
TREQR
Transmission Request Register (TREQR)........... 297
TRTRR
Transmission RTR Register (TRTRR) ............... 298
U
UART
Feature of UART0 ........................................... 228
UART0 Block Diagram .................................... 229
UART0 Operation Modes ................................. 238
UART0 Registers............................................. 230
UIDR
Serial Input Data Register 0 (UIDR0) and Serial
Output Data Register 0 (UODR0) ......... 235
UMC
Configuration of Serial Mode Control Register 0
(UMC0) ............................................. 231
Serial Mode Control Register 0 (UMC0)
Contents............................................. 231
UODR
Serial Input Data Register 0 (UIDR0) and Serial
Output Data Register 0 (UODR0) ......... 235
INDEX
URD
Configuration of Rate and Data Register 0
(URD0).............................................. 236
Rate and Data Register 0 (URD0) Contents ........ 236
User Stack Pointer
User Stack Pointer (USP) and System Stack Pointer
(SSP) ................................................... 31
USP
User Stack Pointer (USP) and System Stack Pointer
(SSP) ................................................... 31
USR
Serial Status Register 0 (USR0)
Configuration ..................................... 233
Serial Status Register 0 (USR0) Contents ........... 233
V
Vector
Interrupt Vector ................................................. 47
List of MB90590 Series Interrupt Vectors ............ 58
Listing of Interrupt Vectors ................................. 47
Reset Vector Address in Flash Memory ............. 395
Verify Sector Protect
Enable Sector Protect/Verify Sector Protect........ 492
W
Wait Time
Setting the Oscillation Stabilization
Wait Time ...................................... 95, 96
Watch Mode
Releasing Watch Mode....................................... 92
Transition to Watch Mode .................................. 92
Watch Timer
Block Diagram of Watch Timer......................... 166
Watch Timer Registers ..................................... 167
Watch-dog Counter
Watch-dog Counter .......................................... 123
Watch-dog Stop
Watch-dog Stop................................................123
Watch-dog Timer
Watch-dog Timer Block Diagram ......................120
Watch-dog Timer Control Register
(WDTC) .............................................121
Waveform
Sample of a Output Waveform when Compare
Registers 0
and 1 are Used
(The Initial Output Value is "0".) ..........141
Sample of a Output Waveform with Two Compare
Registers
(The Initial Output Value is "0".) ..........142
WDTC
Watch-dog Timer Control Register
(WDTC) .............................................121
WE
Write,Data polling,Read (WE control) ................489
Writing
Writing to/Erasing Flash Memory ......................366
WTBR
Sub-second Registers (WTBR) ..........................171
WTCR
Timer Control Register (WTCR) ........................169
WTS
Second/Minute/Hour Registers
(WTSR/WTMR/WTHR) ......................172
X
x
Procedure for Reception by Message Buffer
(x) ......................................................327
Procedure for Transmission by Message Buffer
(x) ......................................................325
513
INDEX
514
CM44-10105-6E
FUJITSU MICROELECTRONICS • CONTROLLER MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90590 Series
HARDWARE MANUAL
July 2008 the sixth edition
Published
FUJITSU MICROELECTRONICS LIMITED
Edited
Business & Media Promotion Dept.
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