The following document contains information on Cypress products. CM44-10107-5ET3 Errata This errata sheet is for MB90560/565 Series Hardware Manual Rev.5 (CM44-10107-5E) F2MC-16LX 16-BIT MICROCONTROLLER MB90560/565 Series HARDWARE MANUAL 2009.4. 2 Date - Page 5 Item Table 1.2-1 Description The caption was corrected as follows: Table 1.2-1 Product Lineup of the MB90560 Series - 2009/ 4/2 6 7 Table 1.2-1 Section 1.2 The shading in the table below indicates changes made to Table 1.2-1. Model MB90V560 Package PGA-256 MB90F562/B MB90562/A MB90561/A QFP-64 (FPT-64P-M09: 0.65 mm pin pitch) QFP-64 (FPT-64P-M06: 1.00 mm pin pitch) SH-DIP-64 (DIP-64P-M01: 1.778 mm pin pitch) Table 1.2-2 was corrected as indicated by the shading below. • Error Model Operating voltage MB90F568 MB90568 MB90567 3V+10% to 3V-10% (on maximum machine clock of 8 MHz) • Correct Model Operating voltage MB90F568 MB90568 MB90567 3.3V+0.3V to 3.3V-0.3V (on maximum machine clock of 8 MHz) [mcu_doc0338] - 11 Figure 1.4-3 The following description was added at the under-left of Figure 1.4-3: *1: Neither MB90568, MB90567 nor MB90F568 are supported. - 20 Table 1.7-1 The shading in the table below indicates changes made to Table 1.7-1. Classification A Remarks Oscillation circuit Oscillation feedback resistor: 1 MΩapprox. 1/15 Date - Page 21 Item Table 1.7-1 Description The shading in the table below indicates changes made to Table 1.7-1. Classification Remarks CMOS I/O pin : : IOL = 12mA E - 25 Section 1.8 The following description was added at the end of the page: Notes on during operation of PLL clock mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. N.C. Pin The N.C. (internally connected) pin must be opened for use. - 33 Figure 2.3-1 The description in Figure 2.3-1 was corrected as indicated by the shading below: Model MB90V560 Address #1 FE0000H * 2/15 Date - Page 87 Item Table 4.3-1 Description The shading in the table below indicates changes made to Table 4.3-1. Bit name bit13 bit12 bit10 - 88 Section 4.4 Function WS1, WS0: Oscillation stabilization wait interval selection bita MCS: Machine clock selection bit These bits select the oscillation stabilization wait interval for the oscillation clock after the stop mode has been cleared due to an external interrupt. When PLL stop mode is returned to PLL clock mode, the oscillation stabilization wait interval requires 214/HCLK or more. When changing to PLL clock mode, these bits are set to "10B" or "11B". :: : : When the main clock mode is switched to PLL clock mode, the oscillation stabilization wait interval is fixed to 214/HCLK. The oscillation stabilization wait interval is about 4.1 ms if the oscillation clock frequency is 4 MHz.) When the main clock has been selected, the oscillation clock divided by 2 is used as the machine clock. :: The shaded portion below was added to the Note for " Clock Mode Transition". In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power consumption mode until the first switching is completed. The MCM bit of the clock selection register (CKSCR) indicates that switching is completed. - 88 Section 4.4 The following description of " Switching from PLL clock mode to main clock mode " in " Clock Mode Transition " were added as indicated by shading below. Note: Before setting the peripheral functions (resources) after the machine clock switching, makesure that the machine clock has been switched by referring to the MCM bit of the CKSCR. If the mode is switched to another clock mode or low-power-consumption mode before completion of switching, the mode may not be switched. - 90 Section 4.5 The last line of " below. Oscillation Stabilization Wait Interval" was corrected as indicated by the shading during an oscillation stabilization wait interval. After the oscillation stabilization wait interval has elapsed, the CPU changes to PLL clock mode. - 95 Section 5.1 The Note for " Standby Mode" was corrected as indicated by the shading below. Note: Because stop mode and hardware standby mode turn the oscillation clock off, these modes save the most power while data is being retained. In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power consumption mode until the first switching is completed. The MCM bit of the clock selection register (CKSCR) indicates that switching is completed. If the mode is switched to another clock mode or low-power-consumption mode before completion of switching, the mode may not be switched. 3/15 Date - Page 99 Item Section 5.3 Description The following note was added at the end of the page: Note: To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode or time-base timer mode, disable the output of peripheral functions, and set the STP bit of the low-power consumption mode control register (LPMCR) to 1 or set the TMD bit to 0. This applies to the following pins: P21/TO0, P23/TO1, P30/RTO0, P31/RTO1, P32/RTO2, P33/RTO3, P34/RTO4, P35/RTO5, P37/SOT0 - - 100 102 Section 5.3 Table 5.5-1 Table5.3-2 was corrected as indicated by shading below. • Error MOV MOV MOV MOVW MOVW MOVW io,#imm8 io,A ＠RLi+disp8,A io,#imm16 io,A ＠RLi+disp8,A MOV MOV MOVP MOVW MOVW MOVPW dir,#imm8 dir,A addr24,A dir,#imm16 dir,A addr24,A MOV MOV • Correct MOV MOV MOV MOVW MOVW MOVW SETB CLRB io,#imm8 io,A @RLi+disp8,A io,#imm16 io,A @RLi+disp8,A io:bp io:bp MOV MOV dir,#imm8 dir,A MOV MOV MOVW MOVW dir,#imm16 MOVW eam,#imm16 MOVW eam,RWi dir,A MOVW addr16,A MOVW eam,A SETB CLRB dir:bp dir:bp 102 Section 5.5 eam, Ri eam,A MOVW eam,#imm16 MOVW eam,RWi MOVW addr16 MOVW eam,A SETB CLRB eam,#imm8 MOV addr16,A MOV eam,Ri eam,A addr16:bp addr16:bp The shading in the table below indicates changes made to Table 5.5-1. Standby mode - eam,#imm8 MOV addr16,A MOV Condition for switch Oscillation Machine clock The following note was added to " Operating Status during Standby Mode": Note: To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode or time-base timer mode, disable the output of peripheral functions, and set the STP bit of the low-power consumption mode control register (LPMCR) to 1 or set the TMD bit to 0. This applies to the following pins: P21/TO0, P23/TO1, P30/RTO0, P31/RTO1, P32/RTO2, P33/RTO3, P34/RTO4, P35/RTO5, P37/SOT0 - 103 Section 5.5.1 The following description was deleted: Hold function In sleep mode, the hold function is enabled. A hold request sets the hold status. 4/15 Date - Page Item 105 Section 5.5.2 Description The following note was added to " Switching to Timebase Timer Mode": Note: To set a pin to high impedance when the pin is shared by a peripheral function and a port in time-base timer mode, disable the output of peripheral functions, and set the TMD bit of the low-power consumption mode control register (LPMCR) to 0. This applies to the following pins: P21/TO0, P23/TO1, P30/RTO0, P31/RTO1, P32/RTO2, P33/RTO3, P34/RTO4, P35/RTO5, P37/SOT0 - 107 Section 5.5.3 The following note was added to " Switching to Stop Mode": Note: To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode, disable the output of peripheral functions, and set the STP bit of the low-power consumption mode control register (LPMCR) to 1. This applies to the following pins: P21/TO0, P23/TO1, P30/RTO0, P31/RTO1, P32/RTO2, P33/RTO3, P34/RTO4, P35/RTO5, P37/SOT0 - 107 Section 5.5.3 The following sentence was added at the second line of " Release of Stop Mode": At return from stop mode, since the oscillation clock (HCLK) has stopped, the stop mode is released after the oscillation stabilization wait interval of the main clock. - 108 Section 5.5.3 The following note was added at the end of the page: Note: In PLL stop mode, the main clock and PLL multiplication circuit stop. At return from PLL stop mode, it is necessary to allot the main clock oscillation stabilization wait interval and PLL clock oscillation stabilization wait interval. The oscillation stabilization wait intervals for the main clock and PLL clock are counted simultaneously according to the value specified in the oscillation stabilization wait interval selection bits (CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait interval selection bits (CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the longer of main clock and PLL clock oscillation stabilization wait interval. The PLL clock oscillation stabilization wait interval, however, requires 214/HCLK or more. Set the oscillation stabilization wait interval selection bits (CKSCR: WS1, WS0) in the clock selection register to "10B" or "11B". 5/15 Date - Page 109 Item Figure 5.6-1 Description The shading in the figure below indicates changes made to Figure 5.6-1. External reset, Watchdog timer reset, Software reset Power-on Reset Oscillation stabilization waiting terminated MCS="1" Main mode PLL mode MCS="0" SLP="1" SLP="1" Interrupt PLL sleep mode Main sleep TMD="0" TMD="0" Interrupt STP="1" Main stop mode Interrupt 110 Section 5.7 PLL stop mode Oscillation stabilization waiting terminated Main clock oscillation stabilization waiting - Interrupt Timebase timer mode Timebase timer mode STP="1" Interrupt Interrupt Oscillation stabilization waiting terminated Main clock oscillation stabilization waiting The following note was added to " Status of Pins in Single-Chip Mode": Note: To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode or time-base timer mode, disable the output of peripheral functions, and set the STP bit of the low-power consumption mode control register (LPMCR) to 1 or set the TMD bit to 0. This applies to the following pins: P21/TO0, P23/TO1, P30/RTO0, P31/RTO1, P32/RTO2, P33/RTO3, P34/RTO4, P35/RTO5, P37/SOT0 - 111010 Table 5.7-1 The shading in the table below indicates changes made to Table 5.7-1. Pin name Sleep mode Standby mode Stop mode / Timebase timer mode SPL=0 SPL=1 6/15 Hold Date - Page 111 Item Section 5.8 Description The following description was added below the " Switching to Standby Mode and Interrupts": Notes on the transition to standby mode To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode or time-base timer mode, use the following procedure: 1. Disable the output of peripheral functions. 2. Set the SPL bit of the low-power consumption mode control register (LPMCR) to 1, and set the STP bit to 1 or set the TMD bit to 0. - 112 Section 5.8 The description of " PLL clock oscillation stabilization wait interval" was corrected as follows: In main clock mode, the PLL multiplication circuit stops. When changing to PLL clock mode, it is necessary to reserve the PLL clock oscillation stabilization wait interval. While waiting for PLL clock oscillation stabilization, the CPU operates on the main clock. The PLL clock oscillation stabilization wait interval is fixed at 214/HCLK (HCLK: clock oscillation frequency). In PLL stop mode, the main clock and PLL multiplication circuit stop. At return from PLL stop mode, it is necessary to allot the main clock oscillation stabilization wait interval and PLL clock oscillation stabilization wait interval. The oscillation stabilization wait intervals for the main clock and PLL clock are counted simultaneously according to the value specified in the oscillation stabilization wait interval selection bits (CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait interval selection bits (CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the longer of main clock and PLL clock oscillation stabilization wait interval. The PLL clock oscillation stabilization wait interval, however, requires 214/HCLK or more. Set the oscillation stabilization wait interval selection bits (CKSCR: WS1, WS0) in the clock selection register to "10B" or "11B". - 112 Section 5.8 The following description was added at the end of the page: Switching the clock mode In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power consumption mode until the first switching is completed. The MCM bit of the clock selection register (CKSCR) indicates that switching is completed. If the mode is switched to another clock mode or low-power-consumption mode before completion of switching, the mode may not be switched. - 184 Section 8.5.2 The following note was added to " Port operation in stop or time-base timer mode": Note: To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode or time-base timer mode, disable the output of peripheral functions, and set the STP bit of the low-power consumption mode control register (LPMCR) to 1 or set the TMD bit to 0. This applies to the following pins: P21/TO0, P23/TO1 - 189 Section 8.6.2 The following note was added to " Port operation in stop or time-base timer mode": Note: To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode or time-base timer mode, disable the output of peripheral functions, and set the STP bit of the low-power consumption mode control register (LPMCR) to 1 or set the TMD bit to 0. This applies to the following pins: P30/RTO0, P31/RTO1, P32/RTO2, P33/RTO3, P34/RTO4, P35/RTO5, P37/SOT0 7/15 Date - Page 215 Item Table 9.3-1 Description The shading in the table below indicates changes made to Table 9.3-1. Bit name bit11 - 217 Section 9.5 Function : : When this bit is set to "1", there is no effect on operation. Reading by read - modify - write type instructions always returns "1". Note: : : This bit is cleared to "0" when writing "0", a transition to stop mode occurs, a transition from main clock mode to PLL clock mode, the timebase timer is cleared due to the timebase timer initialization bit (TBR), or a reset occurs. The first line of " Oscillation Stabilization Wait Interval Timer Function" was corrected as follows: The timebase timer is also used as the oscillation stabilization wait interval timer for the main clock and the PLL clocks. - 218 Table 9.5-1 The shading in the table below indicates changes made to Table 9.5-1. Operation TBTC: Writing of 0 to TBR Power - on reset Watchdog reset Releasing of stop mode Transition from main clock mode to PLL clock mode (MCS = 1 to 0) Releasing of timebase timer mode Releasing of sleep mode - Counter clear X TBOF clear Oscillation Stabilization Wait Interval PLL clock oscillation stabilization wait Interval X X Not provided X X Not provided Main clock oscillation stabilization wait Interval Main clock oscillation stabilization wait Interval 276 Section 12.3.2 The following note was added at the end of the page: Note: To rewriting the compare register, within the compare interrupt routine or compare operation is disabled. Be sure not to occur simultaneously a compare match and writing the compare register. - 302 Section 12.4.2 The following sentence was deleted from the " Output Compare Timing": No compare operation with the counter value is performed when setting the compare register. - 302 Section 12.4.2 The Figure 12.4-7 was deleted. - 303 Section 12.4.2 The following note was added at the end of the page: Note: To rewriting the compare register, within the compare interrupt routine or compare operation is disabled. Be sure not to occur simultaneously a compare match and writing the compare register. 8/15 Date - Page 324 Item Table 13.1-1 Description The shading in the table below indicates changes made to Table 13.1-1. Baud rate - 327 Figure 13.2-1 Up to 2MHz (when the machine clock is operated at 16MHz) A dedicated baud rate generator is provided. Baud rate by an external clock (clock input through the SCK0/SCK1 pins) Internal clock (internal clocks supplied from 16-bit reload timer 0 and 1 can be used.) The baud rate can be selected from a total of eight types In the description upper-left the figure, the following terms was changed as indicated by the shading below: 16-bit reload timer --> 16-bit reload timer 0, 1 - 327 Section 13.2 The last line of " Clock Selector" was corrected as follows: supplied from the 16-bit reload timer). --> supplied from the 16-bit reload timer 0 and 1). - 335 Figure 13.4-3 The description in Figure 13.4-3 was corrected as indicated by the shading below: "110B" - 336 Table 13.4-2 The shading in the table below indicates changes made to Table 13.4-2. bit 5 bit 4 bit 3 - 349 Section 13.6 Baud rate by internal timer (16-bit reload timer 0, 1) CS2 to CS0: Clock selection bits This bit selects a baud rate clock source. When the dedicated baud rate : : Clock input can be selected from external clocks (SCK0/SCK1 pin input), the internal clock (16-bit reload timer 0 and 1), and the dedicated baud rate generator. The third line of the summary was corrected as follows: Internal clock (16-bit reload timer 0) --> Internal clock (16-bit reload timer 0 and 1). - 349 Section 13.6 The following description was corrected: Baud Rates Determined Using the Internal Clock The internal clock supplied from 16-bit reload timer 0 and 1 is used as is (synchronous) or by dividing it by 16 (asynchronous) for the baud rate. Any baud rate can be set by the reload timer 0 and 1 value. - 350 Figure 13.6-1 In the description left the figure, the following terms was changed as indicated by the shading below: 16-bit reload timer 0 --> 16-bit reload timer 0, 1 9/15 Date - Page Item 353 Section 13.6.2 The section title was corrected as follows: Description 13.6.2 Baud Rates Determined Using the Internal Timer (16-bit Reload Timer 0 and 1) - 353 Section 13.6.2 The summary was corrected as follows: This section describes the settings used when the internal clock supplied from 16-bit reload timer 0 and 1 is selected as the UART transfer clock. It also shows the baud rate calculation formulas. - 353 Section 13.6.2 The following description was corrected: Baud Rates Determined Using the Internal Timer (16-bit Reload Timer 0 and 1) If the clock setting bits (CS2 to CS0) of the mode register (SMR0/SMR1) are set to "110B", the baud rate is set by the internal clock. The baud rate can be set by specifying the prescaler division ratio and reload value of the 16-bit reload timer 0 and 1. - 353 Figure 13.6-2 The caption was corrected as follows: Figure 13.6-2 Baud Rate Selection Circuit for the Internal Timer (16-Bit Reload Timer 0, 1) - 353 Figure 13.6-2 In the description left the figure, the following terms was changed as indicated by the shading below: 16-bit reload timer output --> 16-bit reload timer 0, 1 output - 353 Section 13.6.2 The sentences of " Baud Rate Calculation Formulas" were corrected as indicated by the shading below. N: Division ratio for the prescaler of 16-bit reload timer 0, 1 (21, 23, or 25) n: Reload value for 16-bit reload timer 0, 1 (0 to 65535) - 354 Table 13.6-4 The footer of the Table 13.6-4 was corrected as follows: N: Division ratio for the prescaler of 16-bit reload timer 0, 1 10/15 Date - Page 359 Item 13.7.1 Description The following description was added below the " Receiving Operation": Detecting the start bit Implement the following settings to detect the start bit: Set the communication line level to H (attach the mark level) before the communication period. Specify reception permission (RXE = H) while the communication line level is H (mark level). Do not specify reception permission (RXE = H) for periods other than the communication period (without mark level). Otherwise, data is not received correctly. After the stop bit is detected (the RDRF flag is set to 1), specify reception inhibition (RXE = L) while the communication line level is H (mark level). Communication period Non-communication period Mark level Start bit SIN ST Non-communication period Stop bit Data D0 D1 D0 D1 D2 D3 D4 D5 D6 D7 SP (Sending 01010101b) RXE Receive clock Sampling clock Receive clock (8 pulse) Recognition by the microcontroller ST Generating sampling clocks by dividing the receive clock by 16 D2 D3 D4 D5 D6 D7 SP (Receiving 01010101b) Note that specifying reception permission at the timing shown below obstructs the correct recognition of the input data (SIN) by the microcontroller. Example of operation if reception permission (RXE = H) is specified while the communication line level is L. Communication period Non-communication period Mark level SIN (Sending 01010101b) RXE Start bit Non-communication period Stop bit Data ST D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SP SP Receive clock Sampling clock Recognition by the microcontroller ST recognition (Receiving 10101010b) PE,ORE,FRE Occurrence of a reception error - 381 Section 14.4.1 The Note was corrected as follows: Note: A read-modify-write instruction always reads "1" from the DTP/interrupt cause register (EIRR). If more than one external interrupt request output is enabled (EN7 to EN0 of ENIR are set to 1), clear to 0 only the bit for which the CPU accepted an interrupt (any of bits ER7 to ER0 that are set to 1). Do not clear the other bits without a valid reason. 11/15 Date - Page Item Description 416 Section 16.4.1 Table 16.4-1 was added as indicated by shading below. Bit name bit 9 - 418 Function STRT: A/D conversion activation bit l This bit allows software to start A/D conversion. When this bit is set to "0", operation is not affected. Writing 1 to this bit activates A/D conversion. In stop conversion mode, conversion cannot be reactivated with this bit. The value read from this bit is "1". The read-modify-write series commands read "0". Note: Never perform the forced stop and activation (BUSY="0", STRT="1") of the A/D conversion simultaneously. Section 16.4.2 Table 16.4-2 was corrected as indicated by shading below. • Error Bit name bit5 bit4 bit3 Function ANS2, ANS1, ANS0: A/D conversion start channel setting bit These bits are used to set the A/D conversion start channel and check the channel number being converted. When the A/D conversion is activated, it is started from the channel specified by the A/D conversion start channel setting bits (ANS2 to ANS0). During A/D conversion, the channel number being converted is read out. During a pause in stop conversion mode, the channel number converted just before is read out. ・Correct Bit name bit5 bit4 bit3 - 456 Function ANS2, ANS1, ANS0: A/D conversion start channel setting bit These bits are used to set the A/D conversion start channel and check the channel number being converted. When the A/D conversion is activated, it is started from the channel specified by the A/D conversion start channel setting bits (ANS2 to ANS0). During A/D conversion, the channel number being converted is read out. And before A/D conversion starts, the previous conversion channel will be read even if these bits have already been set to the new value. These bits are initialized to "000B" at reset. Section 19.1 The eighth line of "■ Characteristics of the 512K-Bit Flash Memory" was corrected as follows: Minimum of 10,000 write/erase operations - 460 Table 19.3-1 The shading in the table below indicates changes made to Table 19.3-1. bit 3 bit 1 Reserved: Reserved bit Always set this bit to "0". 12/15 Date 2009/ 4/2 Page Item Description 476 Section 19.6.4 Figure 19.6-2 was corrected as indicated by the shading below. Start erasing FMCS: WE (bit 5) Enable flash memory erase Erase command sequence (1) FxAAAAH <-- XXAAH (2) Fx5554H <-- XX55H (3) FxAAAAH <-- XX80H (4) FxAAAAH <-- XXAAH (5) Fx5554H <-- XX55H (6) Enter code to erase sector (30H) YES Another erase sector? NO Read internal address 1 YES NO Next sector Read internal address 2 Sector Erase Completed Toggle bit (DQ6) data 1(DQ6) = data 2(DQ6)? YES NO 0 Timing limit (DQ5)? 1 Read internal address 1 Read internal address 2 NO Toggle bit (DQ6) data 1(DQ6) = data 2(DQ6)? YES Erase error Final sector? NO YES FMCS: WE (bit 5) Disable flash memory erase Confirm with the hardware sequence flags. Complete erasing 13/15 Date 2009/ 4/2 Page Item Description 505 Section 20.6.4 Figure 20.6-2 was corrected as indicated by the shading below. Start erasing FMCS: WE (bit 5) Enable flash memory erase Erase command sequence (1) FxAAAA <-- XXAA (2) Fx5554 <-- XX55 (3) FxAAAA <-- XX80 (4) FxAAAA <-- XXAA (5) Fx5554 <-- XX55 (6) Enter code to erase sector (30H) Y Another erase sector? N Read internal address 1 Next sector Read internal address 2 Y N Toggle bit (DQ6) data 1(DQ6) = data 2(DQ6)? Sector Erase Completed Y N 0 Timing limit (DQ5)? 1 Read internal address 1 Read internal address 2 N Toggle bit (DQ6) data 1(DQ6) = data 2(DQ6)? Y Erase error Final sector? N Y FMCS: WE (bit 5) Disable flash memory erase Confirm with the hardware sequence flags. Complete erasing 14/15 Date 2009/ 4/2 Page 513 Item Section 21.1 Description Table 21.1-3 was deleted as indicated by the shading below. Model Function AZ264 Power regulator (MB90F568: Required when power is supplied from the flash microcomputer programmer to the 3V products) 2009/ 4/2 517 518 Section 21.3 The description of section 21.3.2 was deleted. - 519 Figure 21.4-1 The description in Figure 21.4-1 was corrected as indicated by the shading below: C 0.1 F Connector DX10-28S 10 K /TRES (5) TTXD (13) SIN1 TRXD (27) SOT1 TCK (6) SCK0 TVcc (16) GND 2009/ 4/2 521 Section 21.5 2009/ 1/16 592 APPENDIX B (1, 7, 8, 14, 15, 21, 22, 28) RST Vcc User power supply Vss The description of section 21.5.2 was deleted. ■Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH) is changed. ・Error Item "A" Line of +A "W2+d16,A" ・Correct Item "A0" Line of +A "@RW2+d16" 15/15 Corrections of Hardware Manual MB90560/5 hm90560-cm44-10107-5e-corr-x1-05 © Fujitsu Microelectronics Europe GmbH Addendum, MB90560/5 Hardware Manual (CM42-10107-5E) This is the Addendum for the Hardware Manual CM42-10107-5E of the MB90560/5 microcontroller series. It describes all known discrepancies of the MB90560/5 microcontroller series Hardware Manual. Ref. Number Date (Internal ref. number) Version Chapter/Page No. Description/Correction (Text Link) dd.mm.yy HWM90560001 11.06.01 1.00 6.4.5 Interrupt Processing time HWM90560002 11.06.01 1.00 1.8 Power On Reset HWM90560003 20.08.01 1.02 19 HWM90560004 11.06.01 1.00 1.8 HWM90560005 28.06.01 1.01 1.8 Flash Security Feature, Description updated Handling the Device, Information about reserved memory area RTO Port behaviour during Reset hm90560-cm44-10107-5e-corr-x1-05 1 / 5 HWM90560001 Chapter 6.4.5 Interrupt processing Time The correct interrupt processing time is calculated with: When returning from an interrupt : o = 15 + 6 * z machine cycles HWM90560002 Power-On Reset =================================== Output “unknown value” , when the power supply Is turned on If F2MC16LX is used. (Note) 1.Device covered MB90V560, MB90F562, MB90F568, MB90561, MB90562, MB90567, MB90568 2. Note: During testing it has been found that some port pins may enter an undefined state during power on. By asserting RSTx during the power on reset (217 cycles of main clock) port pins can be forced to high impedance. The following Ports will output a High Impedance (Hi-z) at the terminal when the power supply is turned on when PONR and RSTX = 1: P40 – P67 The following ports will output High Impedance (High-Z) on RSTX or with the End of PONR and Start of internal clocks: P00 – P17 The following Ports will output High Impedance (high-Z) with the End of PONR and Start of the internal Clock. RSTX does not force the pins to high-Z during power on. P20 – P37 Note: This workaround will work for Mode pin setting 011 (Single chip, Internal ROM external bus), 110 (Burn_In ROM), 111 (EPROM mode) hm90560-cm44-10107-5e-corr-x1-05 2 / 5 The following diagram shows the timing chart in detail. O scillation Under“power-on Vcc (power supply i “power-on ” ” i RSTX (external sign RST Internal PrograExecuti MCLK (main clock) i Internal operation Hi- Output port outpu“unknown How to “Hi-” “power-on ” ” Input external RSTX (external sign Output port 0 1 2 17 x oscillation clock Hi- Timing Under “power-on reset” 217 x oscillation clock frequency (8.192ms in case of oscillation clock frequency = 16MHz) Waiting time to be stabilized oscillation 218 x oscillation clock frequency (16.384ms in case of oscillation clock frequency = 16MHz). hm90560-cm44-10107-5e-corr-x1-05 3 / 5 HWM90560003 CHAPTER 19 512K-BIT (64 KB) FLASH MEMORY Flash Security Feature ==================== Correction: The Flash Security Feature is not inside MB90F562 Series, these Feature is only inside MB90F562B Series! Chapter 19.8 Flash Security Feature The Flash security Controller provides possibilities to protect the content of the flash memory from being read from external pins. • Flash Security Feature One predefined address of the flash memory is assigned to the Flash Security Controller (512K-bit flash memory: FF0001). If the protection code of "01H" is written is this address, access to the flash memory is restricted. Once the flash memory is protected, performing the chip erase operation only can unlock the function otherwise read/write access to the flash memory from any external pins is not generally possible. This function is suitable for applications requiring security of selfcontaining and data stored in the flash memory. If the target application requires any part of program to locate outside the microcontroller, the Flash Security Controller can not offer the intended features. For this reason, the External Vector Fetch mode should not be used when the protection code is set. Programming of the flash microcontroller by standard parallel programmer may require unique set-up. For example, with the programmer from Minato Electronics the device checking should be turned off. Writing the protection code is generally recommended to take place at the end of the flash programming. This is to avoid unnecessary protection during the programming. In order to re-program the once protected flash memory, the chip erase operation should be performed. For further information, please contact Fujitsu. HWM90560004 Chapter 1.8 Handling the Device Reserved Area ================================= Last Word of Memory (FFFFFE – FFFFFF) is reserved AREA. Do not use this last WORD hm90560-cm44-10107-5e-corr-x1-05 4 / 5 HWM90560005 Chapter 1.8 Handling the device RTO Port pin (P30-P35) behaviour during Reset When using RTO port Function or the port pins P30-P35, the following behaviour occurs if the external RST Reset pin is asserted: When asserting RST low, the RTO Ports (P30-P35) will drive active ‘High’ Level about 400 ns, starting with the falling edge of the RST signal. This might cause problems in some kind of applications. Especially in case of IGBT drivers, a workaround could be used to disable the output drivers during reset. This could be done e.g by using an additional I/O port, which is tristate during RST. With a corresponding pull-up/down resistance at this port, the level on this pin can be hold high/low during reset in order to keep the driver disabled. After the reset the drivers could be enabled by initialising the port pin correspondingly by software. hm90560-cm44-10107-5e-corr-x1-05 5 / 5