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The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
CM44-10108-6E
F2MC-16LX
16-BIT MICROCONTROLLER
MB90540/545 Series
HARDWARE MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90540/545 Series
HARDWARE MANUAL
The information for microcontroller supports is shown in the following homepage.
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page
"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU MICROELECTRONICS LIMITED
PREFACE
■ Objectives and Intended Reader
Thank you for your continued use of Fujitsu semiconductor products.
The MB90540/545 series has been developed as a general-purpose version of the F2MC-16LX
family, which is an original 16-bit single-chip microcontroller compatible with Application Specific
ICs (ASICs).
This manual describes the functions and operation of the MB90540/545 series for designers
who will use the MB90540/545 series to design products. Read this manual before starting to
design products.
■ Trademark
F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
Other system and product names in this manual are trademarks of respective companies or
organizations.
The symbols ™ and ® are sometimes omitted in this manual.
■ Structure of This Manual
This manual has 25 chapters and an appendix:
Chapter 1 "OVERVIEW"
This chapter explains the features and basic specifications of the M90540/545 series
products.
Chapter 2 "CPU"
This chapter explains the CPU.
Chapter 3 "INTERRUPTS"
This chapter explains the interrupt functions and operations.
Chapter 4 "CLOCK AND RESET"
This chapter explains the functions and operations of clocks and resets.
Chapter 5 "LOW-POWER CONTROL CIRCUIT"
This chapter explains the functions and operation of the low-power control circuit.
Chapter 6 "LOW POWER CONSUMPTION MODES"
This chapter explains the functions and operation of the low-power consumption modes.
Chapter 7 "MEMORY ACCESS MODES"
This chapter explains the functions and operations of the memory access modes.
Chapter 8 "I/O PORTS"
This chapter explains the functions and operations of the I/O ports.
Chapter 9 "TIMEBASE TIMER"
This chapter explains the functions and operations of the timebase timer.
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Chapter 10 "WATCH-DOG TIMER"
This chapter explains the functions and operations of the watch-dog timer.
Chapter 11 "WATCH TIMER"
This chapter explains the functions and operations of the watch timer.
Chapter 12 "16-BIT I/O TIMER"
This chapter explains the functions and operations of the 16-bit I/O timer.
Chapter 13 "16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)"
This chapter explains the functions and operations of the 16-bit reload timer (with the event
count function).
Chapter 14 "8/16-BIT PPG"
This chapter explains the functions and operation of the 8/16-bit PPG.
Chapter 15 "DELAYED INTERRUPTS"
This chapter explains the functions and operations of the delayed interrupt.
Chapter 16 "DTP/EXTERNAL INTERRUPTS"
This chapter explains the functions and operations of the DTP/external interrupts.
Chapter 17 "A/D CONVERTER"
This chapter explains the functions and operations of the A/D converter.
Chapter 18 "UART0"
This chapter explains the UART0 functions and operations.
Chapter 19 "UART1 (SCI)"
This chapter explains the UART1 (SCI) functions and operation.
Chapter 20 "SERIAL I/O"
This chapter explains the functions and operations of the serial I/O.
Chapter 21 "CAN CONTROLLER"
This chapter explains the functions and operations of the CAN controller.
Chapter 22 "ADDRESS MATCH DETECTION FUNCTION"
This chapter explains the address match detection function and operation.
Chapter 23 "ROM MIRRORING FUNCTION SELECTION MODULE"
This chapter explains the ROM mirroring function selection module.
Chapter 24 "1M/2M-BIT FLASH MEMORY"
This chapter explains the functions and operation of the 1M/2M-bit flash memory.
Chapter 25 “EXAMPLES OF MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/
F548GL(S) SERIAL PROGRAMMING CONNECTION”
This chapter provides examples of serial programming connection of MB90F543/F549/
F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S).
Appendix
The appendix provides I/O maps and outlines instructions.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©2006-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
CHAPTER 2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.8
2.9
2.10
2.11
CPU ............................................................................................................ 25
Outline of CPU ..................................................................................................................................
Memory Space ..................................................................................................................................
Memory Space Map ..........................................................................................................................
Linear Addressing .............................................................................................................................
Bank Addressing ...............................................................................................................................
Multi-byte Data in Memory Space .....................................................................................................
Registers ...........................................................................................................................................
Accumulator (A) ...........................................................................................................................
User Stack Pointer (USP) and System Stack Pointer (SSP) .......................................................
Processor Status (PS) .................................................................................................................
Program Counter (PC) .................................................................................................................
Register Bank ...................................................................................................................................
Prefix Codes .....................................................................................................................................
Interrupt Disable Instructions ............................................................................................................
Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions ...........................................................
CHAPTER 3
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.7
OVERVIEW ................................................................................................... 1
Product Overview ............................................................................................................................... 2
Features .............................................................................................................................................. 3
Block Diagram .................................................................................................................................... 5
Package Dimensions .......................................................................................................................... 6
Pin Assignment ................................................................................................................................... 8
Pin Functions .................................................................................................................................... 10
I/O Circuits ........................................................................................................................................ 17
Handling the Device .......................................................................................................................... 20
26
27
28
29
30
32
33
35
36
37
40
41
44
46
47
INTERRUPTS ............................................................................................. 49
Outline of Interrupts ..........................................................................................................................
Interrupt Sources ..............................................................................................................................
Interrupt Vector .................................................................................................................................
Hardware Interrupts ..........................................................................................................................
Hardware Interrupt Operation ......................................................................................................
Flow of Hardware Interrupt Operation .........................................................................................
Required Time to Start Interrupt Processing ...............................................................................
Software Interrupts ...........................................................................................................................
Extended Intelligent I/O Service (EI2OS) ..........................................................................................
Interrupt Control Register (ICR) ...................................................................................................
Extended Intelligent I/O Service Descriptor (ISD) .......................................................................
Operation of Extended Intelligent I/O Service (EI2OS) ................................................................
Execution Time of the Extended Intelligent I/O Service (EI2OS) .................................................
Exception Due to Execution of an Undefined Instruction ..................................................................
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50
51
53
55
57
59
60
62
64
66
69
73
75
76
CHAPTER 4
4.1
4.2
4.3
Clock Generator ................................................................................................................................ 78
Reset Cause Occurrence ................................................................................................................. 79
Reset Causes ................................................................................................................................... 84
CHAPTER 5
5.1
5.2
5.3
5.3.1
5.3.2
5.4
CLOCK AND RESET ................................................................................. 77
LOW-POWER CONTORL CIRCUIT .......................................................... 87
Outline of Low-Power Control Circuit ................................................................................................
Block Diagram of Low-Power Control Circuit ....................................................................................
Low-Power Control Circuit Registers ................................................................................................
Low-Power Consumption Mode Control Register (LPMCR) ........................................................
Clock Selection Register (CKSCR) .............................................................................................
Status Transition for Clock Selection ................................................................................................
CHAPTER 6
LOW-POWER CONSUMPTION MODES ................................................. 101
6.1
Low-Power Consumption Modes ....................................................................................................
6.1.1
Sleep Mode ...............................................................................................................................
6.1.2
Pseudo Timer Mode ..................................................................................................................
6.1.3
Timer Mode ...............................................................................................................................
6.1.4
Stop mode .................................................................................................................................
6.1.5
Hardware Standby Mode ...........................................................................................................
6.1.6
Intermittent CPU Operation .......................................................................................................
6.2
Status Transitions in Low-Power Consumption Mode ....................................................................
6.3
Status Transition Diagram for Low-Power Consumption Mode ......................................................
CHAPTER 7
102
106
107
108
109
111
112
113
118
MEMORY ACCESS MODES .................................................................... 127
7.1
Outline of Memory Access Modes ..................................................................................................
7.1.1
Mode Pins ..................................................................................................................................
7.1.2
Mode Data .................................................................................................................................
7.1.3
Memory Space in Each Bus Mode ............................................................................................
7.2
External Memory Access (Bus Pin Control Circuit) ........................................................................
7.2.1
External Memory Access (External Bus Pin Control Circuit) Registers .....................................
7.2.2
Automatic Ready Function Selection Register (ARSR) .............................................................
7.2.3
External Address Output Control Register (HACR) ...................................................................
7.2.4
Bus Control Signal Selection Register (ECSR) .........................................................................
7.3
External Memory Access Control Signal Operation ........................................................................
7.3.1
Ready Function .........................................................................................................................
7.3.2
Hold Function ............................................................................................................................
CHAPTER 8
88
90
91
92
94
97
128
129
130
131
133
134
135
137
138
141
143
145
I/O PORTS ................................................................................................ 147
8.1
I/O Ports ..........................................................................................................................................
8.2
I/O Port Registers ...........................................................................................................................
8.2.1
Port Data Register (PDR0 to PDRA) (for port 0 to port A) .........................................................
8.2.2
Port Direction Register (DDR0 to DDRA) (for port 0 to port A) ..................................................
8.2.3
Pull-up Control Register (PUCR0 to PUCR3) (for port 0 to port 3) ............................................
8.2.4
Analog Input Enable Register (ADER) ......................................................................................
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148
149
150
151
152
154
CHAPTER 9
9.1
9.2
9.3
TIMEBASE TIMER ................................................................................... 155
Outline of Timebase Timer ............................................................................................................. 156
Timebase Timer Control Register (TBTC) ...................................................................................... 158
Operations of Timebase Timer ....................................................................................................... 160
CHAPTER 10 WATCH-DOG TIMER ............................................................................... 161
10.1
10.2
10.3
Outline of Watch-dog Timer ............................................................................................................ 162
Watch-dog Timer Control Register (WDTC) ................................................................................... 164
Watch-dog Timer Operation ........................................................................................................... 166
CHAPTER 11 WATCH TIMER ........................................................................................ 167
11.1
11.2
11.3
Outline of Watch Timer ................................................................................................................... 168
Watch Timer Control Register (WTC) ............................................................................................. 170
Watch Timer Operation ................................................................................................................... 172
CHAPTER 12 16-BIT I/O TIMER ..................................................................................... 173
12.1 Outline of 16-Bit I/O Timer ..............................................................................................................
12.2 16-bit I/O Timer Registers ...............................................................................................................
12.3 16-bit Free Running Timer ..............................................................................................................
12.3.1 16-bit Free Running Timer Registers ........................................................................................
12.3.2 Timer Counter Control Status Register (TCCS) ........................................................................
12.3.3 16-bit Free Running Timer Operation ........................................................................................
12.4 Output Compare .............................................................................................................................
12.4.1 Output Compare Register (OCCP0, OCCP1) ...........................................................................
12.4.2 Control Status Register of Output Compare (OCS0/OCS1) ......................................................
12.4.3 16-bit Output Compare Operation .............................................................................................
12.5 Input Capture ..................................................................................................................................
12.5.1 Input Capture Register Details ..................................................................................................
12.5.2 16-bit Input Capture Operation ..................................................................................................
174
176
177
178
179
182
184
185
186
189
192
193
195
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) ................ 197
13.1 Outline of 16-Bit Reload Timer (with Event Count Function) ..........................................................
13.2 Registers of 16-Bit Reload Timer ....................................................................................................
13.2.1 Timer Control Status Register (TMCSR) ...................................................................................
13.2.2 Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR) ...................
13.3 Internal Clock and External Clock Operations of 16-bit Reload Timer ...........................................
13.4 Underflow Operation of 16-bit Reload Timer ..................................................................................
13.5 Output Pin Functions of 16-bit Reload Timer ..................................................................................
13.6 Counter Operation State .................................................................................................................
198
200
201
204
205
207
208
209
CHAPTER 14 8/16-BIT PPG ........................................................................................... 211
14.1 Outline of 8/16-bit PPG ...................................................................................................................
14.2 Block Diagram of 8/16-bit PPG .......................................................................................................
14.3 8/16-bit PPG Registers ...................................................................................................................
14.3.1 PPG0 Operation Mode Control Register (PPGC0) ....................................................................
14.3.2 PPG1 Operation Mode Control Register (PPGC1) ....................................................................
14.3.3 PPG unit 0 Clock Selection Register (PPG01) ..........................................................................
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212
213
215
216
218
221
14.3.4 Reload Register (PRLL/PRLH) ..................................................................................................
14.4 Operations of 8/16-bit PPG .............................................................................................................
14.5 Selecting a Count Clock for 8/16-bit PPG .......................................................................................
14.6 Controlling Pin Output of 8/16-bit PPG Pulses ...............................................................................
14.7 8/16-bit PPG Interrupts ...................................................................................................................
14.8 Initial Values of 8/16-bit PPG Hardware .........................................................................................
223
224
226
227
228
229
CHAPTER 15 DELAYD INTERRUPT .............................................................................. 231
15.1
15.2
15.3
Outline of Delayed Interrupt Module ............................................................................................... 232
Delayed Interrupt Register .............................................................................................................. 233
Delayed Interrupt Operation ........................................................................................................... 234
CHAPTER 16 DTP/EXTERNAL INTERRUPTS .............................................................. 235
16.1
16.2
16.3
16.4
16.5
Outline of DTP/External Interrupts ..................................................................................................
DTP/External Interrupt Registers ....................................................................................................
Operations of DTP/External Interrupts ............................................................................................
Switching between External Interrupt and DTP Requests ..............................................................
Notes on Using DTP/External Interrupts .........................................................................................
236
238
240
242
243
CHAPTER 17 A/D CONVERTER .................................................................................... 245
17.1 Features of A/D Converter ..............................................................................................................
17.2 Block Diagram of A/D Converter .....................................................................................................
17.3 A/D Converter Registers .................................................................................................................
17.3.1 A/D Control Status Register 0 (ADCS0) ....................................................................................
17.3.2 A/D Control Status Register 1 (ADCS1) ....................................................................................
17.3.3 A/D Data Register 0/1(ADCR0 and ADCR1) .............................................................................
17.4 Operations of A/D Converter ..........................................................................................................
17.5 Conversion Using EI2OS ................................................................................................................
17.5.1 Example of Starting EI2OS in Single Mode ...............................................................................
17.5.2 Example of Starting EI2OS in Continuous Mode .......................................................................
17.5.3 Example of Starting EI2OS in Stop Mode ..................................................................................
17.6 Conversion Data Protection Function .............................................................................................
246
248
249
250
253
256
258
260
261
263
265
267
CHAPTER 18 UART0 ...................................................................................................... 269
18.1 Feature of UART0 ...........................................................................................................................
18.2 UART0 Block Diagram ....................................................................................................................
18.3 UART0 Registers ............................................................................................................................
18.3.1 Serial Mode Control Register 0 (UMC0) ....................................................................................
18.3.2 Serial Status Register 0 (USR0) ................................................................................................
18.3.3 Serial Input Data Register 0 (UIDR0) and Serial Output Data Register 0 (UODR0) .................
18.3.4 Rate and Data Register 0 (URD0) .............................................................................................
18.4 UART0 Operation ...........................................................................................................................
18.5 Baud Rate .......................................................................................................................................
18.6 Internal and External Clock .............................................................................................................
18.7 Transfer Data Format .....................................................................................................................
18.8 Parity Bit .........................................................................................................................................
18.9 Interrupt Generation and Flag Set Timings .....................................................................................
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270
271
272
273
275
277
278
280
281
284
285
286
287
18.9.1 Flag Set Timings for a Receive Operation (in Mode 0, 1, or 3) .................................................
18.9.2 Flag Set Timings for a Receive Operation (in Mode 2) .............................................................
18.9.3 Flag Set Timings for a Transmit Operation ................................................................................
18.9.4 Status Flag During Transmit and Receive Operation ................................................................
18.10 UART0 Application Example ..........................................................................................................
288
289
290
291
292
CHAPTER 19 UART1 (SCI) ............................................................................................. 295
19.1 Features of UART1 .........................................................................................................................
19.2 UART1 Block Diagram ....................................................................................................................
19.3 UART1 Registers ............................................................................................................................
19.3.1 Serial Mode Register 1 (SMR1) .................................................................................................
19.3.2 Serial Control Register 1 (SCR1) ..............................................................................................
19.3.3 Serial Input Data Register 1 (SIDR1) / Serial Output Data Register 1 (SODR1) .......................
19.3.4 Serial Status Register 1 (SSR1) ................................................................................................
19.3.5 UART1 Communication Prescaler Control Register (CDCR) ....................................................
19.4 UART1 Operating Modes and Clock Selection ...............................................................................
19.4.1 Asynchronous (Start-Stop Synchronized) Mode .......................................................................
19.4.2 CLK Synchronous Mode ............................................................................................................
19.5 UART1 Flags and Interrupt Sources ...............................................................................................
19.6 UART1 Interrupts and Flag Set Timing ...........................................................................................
19.7 Negative Clock Operation ...............................................................................................................
19.8 UART1 Sample Applications and Precautionary Information .........................................................
296
297
298
299
301
303
304
306
307
311
312
314
315
318
319
CHAPTER 20 SERIAL I/O ............................................................................................... 321
20.1 Outline of Serial I/O ........................................................................................................................
20.2 Serial I/O Registers .........................................................................................................................
20.2.1 Serial Mode Control Status Register (SMCS) ...........................................................................
20.2.2 Serial Shift Data Register (SDR) ...............................................................................................
20.2.3 Serial I/O Prescaler (SCDCR) ...................................................................................................
20.3 Serial I/O Operation ........................................................................................................................
20.3.1 Shift Clock .................................................................................................................................
20.3.2 Serial I/O Operation ...................................................................................................................
20.3.3 Shift Operation Start/Stop Timing ..............................................................................................
20.3.4 Interrupt Function of the Serial I/O Interface .............................................................................
20.4 Negative Clock Operation ...............................................................................................................
322
324
325
329
330
331
332
333
335
338
339
CHAPTER 21 CAN CONTROLLER ................................................................................ 341
21.1 Features of CAN Controller ............................................................................................................
21.2 Block Diagram of CAN Controller ...................................................................................................
21.3 List of Overall Control Registers .....................................................................................................
21.4 List of Message Buffers (ID Registers) ...........................................................................................
21.5 List of Message Buffers (DLC Registers and Data Registers) ........................................................
21.6 Classifying the CAN Controller Registers .......................................................................................
21.6.1 Control Status Register (CSR) ..................................................................................................
21.6.2 Bus Operation Stop Bit (HALT = 1) ...........................................................................................
21.6.3 Last Event Indicator Register (LEIR) .........................................................................................
21.6.4 Receive and Transmit Error Counters (RTEC) ..........................................................................
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342
343
344
346
349
353
354
357
359
361
21.6.5 Bit Timing Register (BTR) ..........................................................................................................
21.6.6 Message Buffer Valid Register (BVALR) ...................................................................................
21.6.7 IDE register (IDER) ....................................................................................................................
21.6.8 Transmission Request Register (TREQR) ................................................................................
21.6.9 Transmission RTR Register (TRTRR) .......................................................................................
21.6.10 Remote Frame Receiving Wait Register (RFWTR) ...................................................................
21.6.11 Transmission Cancel Register (TCANR) ...................................................................................
21.6.12 Transmission Complete Register (TCR) ....................................................................................
21.6.13 Transmission Interrupt Enable Register (TIER) .........................................................................
21.6.14 Reception Complete Register (RCR) ........................................................................................
21.6.15 Remote Request Receiving Register (RRTRR) ........................................................................
21.6.16 Receive Overrun Register (ROVRR) .........................................................................................
21.6.17 Reception Interrupt Enable Register (RIER) .............................................................................
21.6.18 Acceptance Mask Select Register (AMSR) ...............................................................................
21.6.19 Acceptance Mask Registers 0/1 (AMR0/AMR1) ........................................................................
21.6.20 Message Buffers ........................................................................................................................
21.6.21 ID Register x (x = 0 to 15) (IDRx) ..............................................................................................
21.6.22 DLC Register x (x = 0 to 15) (DLCRx) .......................................................................................
21.6.23 Data Register x (x = 0 to 15) (DTRx) .........................................................................................
21.7 Transmission of CAN Controller .....................................................................................................
21.8 Reception of CAN Controller ..........................................................................................................
21.9 Reception Flowchart of CAN Controller ..........................................................................................
21.10 How to Use the CAN Controller ......................................................................................................
21.11 Procedure for Transmission by Message Buffer (x) .......................................................................
21.12 Procedure for Reception by Message Buffer (x) .............................................................................
21.13 Setting Configuration of Multi-level Message Buffer .......................................................................
21.14 Precautions when Using CAN Controller ........................................................................................
362
364
365
366
367
368
369
370
371
372
373
374
375
376
378
380
381
383
384
386
389
392
393
395
397
399
402
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ......................................... 403
22.1
22.2
22.3
22.4
Overview of the Address Match Detection Function .......................................................................
Registers of the Address Match Detection Function .......................................................................
Operation of the Address Match Detection Function ......................................................................
Example of the Address Match Detection Function ........................................................................
404
405
407
408
CHAPTER 23 ROM MIRRORING FUNCTION SELECTION MODULE .......................... 411
23.1
23.2
Outline of ROM Mirroring Function Selection Module .................................................................... 412
ROM Mirroring Function Selection Register (ROMM) .................................................................... 413
CHAPTER 24 1M/2M-BIT FLASH MEMORY .................................................................. 415
24.1 Outline of 1M/2M-bit Flash Memory ................................................................................................
24.2 Sector Configuration of the Flash Memory .....................................................................................
24.3 Write/Erase Modes .........................................................................................................................
24.4 Flash Memory Control Status Register (FMCS) .............................................................................
24.5 Starting the Flash Memory Automatic Algorithm ............................................................................
24.6 Confirming the Automatic Algorithm Execution State .....................................................................
24.6.1 Data Polling Flag (DQ7) ............................................................................................................
24.6.2 Toggle Bit Flag (DQ6) ................................................................................................................
x
416
417
418
420
422
424
426
428
24.6.3 Timing Limit Exceeded Flag (DQ5) ...........................................................................................
24.6.4 Sector Erase Timer Flag (DQ3) .................................................................................................
24.6.5 Toggle Bit 2 Flag (DQ2) .............................................................................................................
24.7 Detailed Explanation of Writing to and Erasing Flash Memory .......................................................
24.7.1 Setting The Read/Reset State ...................................................................................................
24.7.2 Writing Data ...............................................................................................................................
24.7.3 Erasing All Data (Erasing Chips) ...............................................................................................
24.7.4 Erasing Optional Data (Erasing Sectors) ...................................................................................
24.7.5 Suspending Sector Erase ..........................................................................................................
24.7.6 Restarting Sector Erase ............................................................................................................
24.8 Notes on using 1M/2M-bit Flash Memory .......................................................................................
24.9 Flash Security Feature ....................................................................................................................
24.10 Example of Programming 1M/2M-bit Flash Memory ......................................................................
429
430
431
433
434
435
437
438
440
441
442
443
444
CHAPTER 25 EXAMPLES OF MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/
F548GL(S) SERIAL PROGRAMMING CONNECTION ........................... 449
25.1
25.2
25.3
25.4
25.5
Basic Configuration of MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S)
Serial Programming Connection ...................................................................................................... 450
Example of Serial Programming Connection (User Power Supply Used) ...................................... 454
Example of Serial Programming Connection (Power Supplied from the Programmer) .................. 456
Example of Minimum Connection to the Flash Microcomputer Programmer
(User Power Supply Used) ............................................................................................................. 458
Example of Minimum Connection to the Flash Microcomputer Programmer
(Power Supplied from the Programmer) ......................................................................................... 460
APPENDIX ......................................................................................................................... 463
APPENDIX A I/O Maps ..............................................................................................................................
APPENDIX B Instructions ...........................................................................................................................
B.1 Instruction Types ............................................................................................................................
B.2 Addressing .....................................................................................................................................
B.3 Direct Addressing ...........................................................................................................................
B.4 Indirect Addressing ........................................................................................................................
B.5 Execution Cycle Count ...................................................................................................................
B.6 Effective address field ....................................................................................................................
B.7 How to Read the Instruction List ....................................................................................................
B.8 F2MC-16LX Instruction List ............................................................................................................
B.9 Instruction Map ...............................................................................................................................
464
473
474
475
477
483
491
494
495
498
512
INDEX................................................................................................................................... 535
xi
xii
Main changes in this edition
Page
Changes (For details, refer to main body.)
473 to 533 Changed the entire part of "APPENDIX B Instructions"
The vertical lines marked in the left side of the page show the changes.
Reference: Main changes (Rev.4 → Rev.5)
Page
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4
Changes (For details, refer to main body.)
Register names are changed.
(Program bank register (PCB) → Program counter bank register (PCB))
(Additional bank register (ADB) → Additional data bank register (ADB))
(timer control status register → timer counter control status register)
(Control Status Register → Input Capture Control Status Register)
(Interrupt/DTP enable register → DTP/external interrupt enable register)
(Interrupt/DTP cause register → DTP/external interrupt cause register)
(conversion data register → A/D data register)
(Status register → Serial status register)
(Prescaler control register → UART1 communication prescaler control register)
(Input data register/output data register → Serial input data register/serial output data register)
(Output Data Register 0 (UODR0) → Serial Output Data Register 0 (UODR0))
(Serial data register (SDR) → Serial shift data register)
(UART1 prescaler control register → UART1 communication prescaler control register)
(Serialedgeselectregister2 → Serial edge select register)
(External interrupt level register → Request level setting register)
(Delayed interrupt/release register → Delayed interrupt/cause issurance/cancellation register)
(low-power mode control register → low-power consumption mode control register)
(Port n data register → Port data register (PDRn) (for port n)) n = 0 to A
(Port n direction register → Port direction register (DDRn) (for port n)) n = 0 to A
(Port 0 pull-up control register (PUCR0) → Pull-up control register (PUCR0) (for port 0))
(Port 1 pull-up control register (PUCR1) → Pull-up control register (PUCR1) (for port 1))
(Port 2 pull-up control register (PUCR2) → Pull-up control register (PUCR2) (for port 2))
(Port 3 pull-up control register (PUCR3) → Pull-up control register (PUCR3) (for port 3))
(Port 6 analog input enable register (ADER) → Analog input enable register (ADER))
(PPG0 and PPG1 clock selection register → PPG unit 0 clock selection register)
(Control status resister → A/D Control status resister 0/1)
(Data register → A/D Data register 0/1)
(A/D control status register (lower) → A/D control status register 0)
(A/D control status register (upper) → A/D control status register 1)
(Data register (lower) → A/D Data register 0)
(Data register (upper) → A/D Data register 1)
(control status register (ADCS1) controls → A/D control status register 1 (ADCS1) controls)
(conversion data register → A/D data register)
(ThePbitintheURD0register → The P (Parity) bit in the URD0 register)
(Serial control register → Serial control register 1)
(Serial input data register → Serial input data register 1)
(Serial output data register → Serial output data register 1)
(Prescaler control register → UART1 communication prescaler control register)
Table 1.2-1 MB90540/545 Features (2/2) is changed.
(Eight 8-bit reload counters → Two × four units 8-bit reload counters)
(Eight 8-bit reload registers for L pulse width → Two × four units 8-bit reload registers for "L" pulse width)
(Eight 8-bit reload registers for H pulse width → Two × four units 8-bit reload registers for "H" pulse width)
(Virtually all external pins can be used as general purpose IO → 81 general purpose I/O ports)
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Reference: Main changes (Rev.4 → Rev.5)
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12
12
13
17 to 19
20
21
22
23
29
30
Changes (For details, refer to main body.)
Table 1.6-1 Pin Functions is changed.
Table 1.6-1 Pin Functions (3/7) is changed.
((DDR0 to DDRA) → (DDR))
Table 1.6-1 Pin Functions (3/7) is changed.
(SCKO → SCK0)
Table 1.6-1 Pin Functions (4/7) is changed.
((DDR0 to DDRA) → (DDR))
Table 1.7-1 I/O Circuits is changed.
(Hysteresis input → CMOS Hysteresis input)
❍ Preventing latch-up is changed.
(The text that It should be careful not to exceed the absolute maximum ratings (Preventing latch-up). is added)
(• The AVCC power supply is applied before the VCC voltage. is deleted.)
(For the same reason, also be careful not let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage. → For the same reason, also be careful not let the analog power-supply voltage
(AVCC, AVRH) and analog input voltage exceed the digital power-supply voltage, when power supply is
tuned on or off.)
❍ Notes for using external clock is changed.
(To use external clock, drive X0 pin only and leave X1 pin. → To use external clock, drive X0 pin only and
leave X1 pin open.)
(The text that Below is a diagram of how to use external clock. is deleted.)
❍ Power supply pins (VCC/VSS) is changed.
(Figure 1.8-2 Handing of Power Supply Pins (VCC/VSS) is added.)
❍ Crystal Oscillator Circuit is changed.
(Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. is
added.)
❍ Connection of Unused Pins of A/D Converter is changed.
(Connect unused pins of A/D converter to AVCC=VCC,AVSS=AVRH=VSS. → Connect unused pins of A/D
converter and D/A converter to AVCC = VCC, AVSS = AVRH = VSS.)
❍ Notes on Energization is changed.
(To prevent the internal regulator circuit from malfunctioning, → To prevent the built-in down-convention circuit from malfunctioning,)
❍ Indeterminate outputs from ports 0 and 1 (MB90F543/F549/V540/V540G only) is changed.
Figure 1.8-3 Timing Chart of Port 0/1 Indeterminate (RST Pin is "H") is changed.
(*1: Power-on reset time → *1: Oscillation setting time for step-down circuit)
❍ Indeterminate outputs from ports 0 and 1 (MB90F543/F549/V540/V540G only) is changed.
Figure 1.8-4 Timing Chart of Port 0/1 to be High-impedance (RST Pin is "L") is changed.
(*1: Power-on reset time → *1: Oscillation setting time for step-down circuit)
❍ Initialization is changed.
❍ Directions of "DIV A, Ri" and "DIVW A, RWi" instructions is changed.
(The text that Please refer to "2.11 Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions" for details.
is added.)
Summary of 2.4 Linear Addressing is changed.
(There are two types of linear addressing: → There are 2 types of linear addressing as follows:)
(Indirectly specifies the 24 low-order bits of a → Indirectly quote the 24 low-order bits of a)
❍ User stack bank register (USB)/system stack bank register (SSB) is changed.
(USP → USB)
(SSP → SSB)
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Reference: Main changes (Rev.4 → Rev.5)
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34
36
38
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44
45
Changes (For details, refer to main body.)
■ Special Registers is changed.
(The F2MC-----16LX CPU core has the following 13 special registers: → The F2MC------16LX CPU core has
the following 11 special registers:)
■ General-purpose Registers is changed.
(The relationship bet ween the high-order and low-order bytes of Rli and RW can be expressed as follows: →
The relationship between the high-order and low-order bytes of RLi and RW can be expressed as follows:)
■ User Stack Pointer (USP) and System Stack Pointer (SSP) is changed.
(The text that USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring
data in the event of a push/pop instruction or subroutine execution. is deleted.)
Figure 2.7-5 Stack Operation Instruction and Stack Pointer (PUSHW A when the S Flag is "0") is changed.
(Figure 2.7-5 Stack Manipulation Instruction and Stack Pointer → Figure 2.7-5 Stack Operation Instruction
and Stack Pointer (PUSHW A when the S Flag is "0"))
(Figure 2.7-6 Stack Operation Instruction and Stack Pointer (PUSHW A when the S Flag is "1") is added.)
■ Register Bank Pointer (RP) is changed.
(000180H to 00037H → 000180H to 00037FH)
Additional data bank register (ADB) <Initial value: 00H> is changed.
(PCB is initialized to 00H by a reset. → PCB is initialized to a reset vector value.)
Summary of 2.9 Prefix Codes is changed.
(flag change disable prefix. → flag change suppressive prefix.)
■ Bank Select Prefix is changed.
(that instruction can be selected → that instruction can be selected freely)
Table 2.9-1 Bank Select Prefix is changed.
(the stack flag value. → the stack flag status.)
❍ String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) is changed.
(regardless of the prefix. → regardless of existence of the prefix.)
❍ Stack manipulation instructions (PUSHW, POPW) is changed.
(regardless of the prefix. → regardless of existence of the prefix.)
❍ I/O access instructions is changed.
(MOV io, imm16/MOVB A, io:bp/MOB io:bp, A/SETB io:bp/CLRB io:bp → MOVW io, #imm16 / MOVB
A, io:bp / MOVB A io:bp, A /SETB io:bp / CLRB io:bp)
(BBC io:bp, rel/BBS io:bp, relWBTC, WBTS → BBC io:bp, rel / BBS io:bp, rel/WBTC, WBTS)
(The IO space of the bank is used regardless of the prefix. → The I/O space of the bank is used regardless of
existence of the prefix.)
❍ POPW PS is changed.
(regardless of the prefix. → regardless of existence of the prefix.)
❍ RETI is changed.
(regardless of the prefix. → regardless of existence of the prefix.)
■ Common Register Bank Prefix (CMR) is changed.
(that instruction accesses the common bank → that instruction changes the common bank)
❍ String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) is changed.
(Do not prefix any of the above → Do not add any prefix of the above)
■ Flag Change Suppressive Prefix (NCC) is changed.
(disable → suppressive)
(disables → suppressive)
❍ String instructions (MOVS/MOVSW/SCEQ/SCWEQ/FILS/FILSW) is changed.
(Do not prefix any of the above → Do not add any prefix the above)
❍ Interrupt instructions (INT #vct8/INT9/INT addr16/INTP addr24/RETI) is changed.
(regardless of the prefix. → regardless of the existence of the prefix.)
❍ JCTX @A is changed.
(regardless of the prefix. → regardless of the existence of the prefix.)
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51
52
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54
55
58
59
60
61
62
63
64
Changes (For details, refer to main body.)
■ Interrupt Disable Instructions is changed.
(If a valid interrupt request → If a valid hardware interrupt request)
Figure 2.10-1 Interrupt Disable Instruction is changed.
(Interrupt request → Interrupt request generated)
[Example] is changed.
(DTB=053H/RP=003H, → DTB=053H/RP=03H, )
(0180H RP(003H)x → 0180H+RP (03H) x )
■ Evasion of Notes is changed.
(Use the following compiler and assembler. → Use the following compiler and assembler as for MB90540/545
series.)
Table 3.2-1 Interrupt Sources, Interrupt Vectors, and Interrupt Control Registers (1/2) is changed.
(PPG 0/1 → PPG (ch0, ch1) unit 0)
(PPG 2/3 → PPG (ch2, ch3) unit 1)
(PPG 4/5 → PPG (ch4, ch5) unit 2)
Table 3.2-1 Interrupt Sources, Interrupt Vectors, and Interrupt Control Registers (2/2) is changed.
(PPG 6/7 → PPG (ch6, ch7) unit 3)
Table 3.3-1 Interrupt Vector (1/2) is changed.
(PPG 0/1 → PPG (ch0, ch1) unit 0)
(PPG 2/3 → PPG (ch2, ch3) unit 1)
Table 3.3-1 Interrupt Vector (2/2) is changed.
(PPG 4/5 → PPG (ch4, ch5) unit 2)
(PPG 6/7 → PPG (ch6, ch7) unit 3)
Summary of 3.4 Hardware Interrupts is changed.
(internal resource → peripheral function)
❍ CPU is changed.
(internal resource → peripheral function)
■ Hardware Interrupt Request During Writing to the Input-Output Area is changed.
(rewritten to the interrupt control registers for each source. → rewritten to the interrupt control registers for
each resource.)
Figure 3.4-2 Occurrence and Release of Hardware Interrupt is changed.
(ILM: Interrupt level in PS → ILM: Interrupt level mask register in PS)
Figure 3.4-3 Flow of Hardware Interrupt Operation is changed.
(S → 1 → S ← 1)
3.4.3 Required Time to Start Interrupt Processing is changed.
(time required → required time)
Table 3.4-2 Compensation Value (Z) of Interrupt Handling Time is changed.
(Corrective Value (Z) → Compensation Value (Z))
Summary of ■ Software Interrupts is changed.
(• Sets I in the PS register. → • Set PS: I flag to "0".)
Figure 3.5-1 Occurrence and Release of Software Interrupt is changed.
((3) is added.)
(ILM: Iinterrupt level in PS → ILM : Interrupt level mask register in PS)
■ Note on Software Interrupt is changed.
(program bank register (PCB) → program counter bank register (PCB))
Summary of 3.6ExtendedIntelligent I/O Service (EI2OS) is changed.
(The text that Note: The use of EI2OS is not possible with the REALOS real time operating system. is deleted.)
Note is changed.
(The text that Note: The extended intelligent I/O service (EI2OS) can be used if using the REALOS. is added.)
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Changes (For details, refer to main body.)
Figure 3.6-1 Outline of Extended Intelligent I/O Service is changed.
(➄ is added.)
Figure 3.6-7 Operation Flow of the Extended Intelligent I/O Service (EI2OS) is changed.
(Interrupt request generated by internal resource → Interrupt request generated by peripheral function)
(Clear interrupt request from internal resource → Peripheral function: Clear interrupt request )
Figure 3.6-8 Procedure for Using the Extended Intelligent I/O Service (EI2OS) is changed.
(internal resource → peripheral function)
Notes: is changed.
(In stop mode, input of the external pin reset signal allows an oscillation stabilization wait time to be set. → •
In stop mode, input of the external pin reset signal allows an oscillation stabilization wait time to be set regardless of reset cause.)
(The text that Also, the oscillation stabilization wait time of the hardware standby reset in the subclock mode is
fixed to 217 cycles of the source oscillation. is added.)
❍ Switching between main clock and PLL clock is changed.
(Writing to the MCS bit → Rewriting to the MCS bit)
❍ Switching between main clock and subclock is changed.
(Writing to the SCS bit → Rewriting to the SCS bit)
❍ Initializing the machine clock is changed.
(The MCS bit and SCS bit are → The MCS bit is)
Note of ❍ Initializing the machine clock is changed.
(When tune on the power or hardware standby mode → When the power is turned on or hardware standby
mode)
■ PLL Clock Multiplication Function is changed.
(The text that This clock is divided by two and used as a machine clock signal. is deleted.)
Figure 5.3-1 Low-Power Control Circuit Registers is changed.
(SSR → Reserved)
((R/W) → (-))
■ Clock Selection Register (CKSCR) is changed.
(The text that Writing this bit has no effect on operation. is added.)
[bit15] SCM is changed.
(When SCS=1 and SCM=0, the system is waiting for main clock oscillation to stabilize. → When SCS=1 and
SCM=0, the system is in the main clock oscillation stabilization wait time.)
(The description that One clock system: is deleted. )
(The text that The read value is always "1". is deleted.)
[bit14] MCM is changed.
(When MCS=0 and MCM=1, the system is waiting for the PLL clock oscillation to stabilize. → When MCS=0
and MCM=1, the system is in the PLL clock oscillation stabilization wait time.)
[bit11] SCS is changed.
(When this bit is updated from 0 to 1, the oscillation stabilization wait time for oscillation clock is generated
and the timebase timer is cleared automatically. When the subclock is selected, the operation clock is generated by dividing the subclock by fore (the operation clock is 8kHz at a source oscillation of 32kHz). → When
this bit is set to "1", writing "0" switches to subclock mode in synchronized with subclock. When this bit is set
to "0", writing "1" the oscillation stabilization wait time for main clock is generated and then the timebase
timer is cleared automatically. When both SCS bit and MCS bit are "0", SCS bit has priority and subclock is
selected.)
[bit10] MCS is changed.
(the operation clock is generated by dividing the main clock → the operation clock is generated by dividing the
oscillation clock)
(The text that Note: TheMCSbitisinitializedto1byapower-on, hardware standby, or watch-dog reset instead of
are set using an external pin or RST bit. is deleted.)
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Reference: Main changes (Rev.4 → Rev.5)
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Changes (For details, refer to main body.)
Table 5.3-4 CS Bit Setting is changed.
(OSC oscillation frequency → OSC oscillation clock)
Figure 5.4-3 Clock Selection Status Transition 3 (One-way Item) is changed.
(Main clock → Main)
(PLL multiplication → PLL1 multiplication )
(PLL multiplication → PLL2 multiplication )
(PLL multiplication → PLL3 multiplication )
(PLL multiplication → PLL4 multiplication )
(factor: 1 is deleted.)
(factor: 2 is deleted.)
(factor: 3 is deleted.)
(factor: 4 is deleted.)
(The texts of ➀ to ➆ are changed.)
❍ Intermittent CPU operation function is changed.
(The text that The CS1 and CS0 bits are used to set the multiplication factor of the PLL clock. The multiplication factor is obtained by multiplying the clock signal by 2, 4, 6, or 8. This clock signal is divided by two and
used as a machine clock signal. is deleted.)
Table 6.1-2 Operation Status in Low-Power Consumption Mode (Single Clock (system) Parts) is changed.
(*4 → *1)
(*5 → *2)
Summary of 6.1.1 Sleep Mode is changed.
(As a result, the CPU terminates while peripheral circuits keep operating. → As a result, the CPU terminates
while internal peripheral resource circuits keep operating.)
(The text that However, the timer mode can not be used in the one clock system parts. is deleted.)
■ Transition to Sleep Mode is changed.
(In sleep mode, the values of special registers such as the → In sleep mode, the values of dedicated registers
such as the)
■ Releasing Sleep Mode is changed.
(The standby control circuit releases sleep mode in the event of a reset input or an interrupt. → The standby
control circuit releases sleep mode in the event of a reset input or an interrupt request.)
(If a peripheral circuit or similar issues an interrupt request of → If a peripheral circuit and internal resource
issues an interrupt request of)
■ Releasing Timer Mode is changed.
(then immediately enters subclock state. → then immediately enters subclock mode.)
(After pseudo timer mode is released, → After timer mode is released,)
(when the interrupt can be accepted according to the I flag in → when the interrupt can be accepted according
to the setting of I flag in)
(processing continues with the instruction following the instruction → processing continues with following the
instruction)
■ Releasing Stop Mode is changed.
(the subclock oscillation stabilization wait time applies and processing is → the subclock oscillation stabilization wait time is applied and processing is)
(when the interrupt can be accepted according to the I flag in → when the interrupt can be accepted according
to the setting of I flag in)
(processing continues with the instruction following the → processing continues with following the)
■ Releasing Hardware Standby Mode is changed.
(The oscillation stabilization wait time for hardware standby mode is fixed to 218 cycles of the → The oscillation stabilization wait time for hardware standby mode is fixed to 218 counts of the)
Table 6.2-1 Transition Conditions of the Two Clocks System Parts (1/4) is changed.
(Main timer transition mode → Main watch transition mode)
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Reference: Main changes (Rev.4 → Rev.5)
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Changes (For details, refer to main body.)
Table 6.2-1 Transition Conditions of the Two Clocks System Parts (2/4) is changed.
(PLL timer transition P → PLL watch transition P)
(Pseudo timer transition mode → Pseudo watch transition mode)
(10SCS=1,MCS1write → 10 SCS=1, MCS=1 write)
(Main timer transition mode → Main watch transition mode)
(02 Main oscillation stabilization time wait termination → 02 Main oscillation stabilization wait time termination)
(PLL timer transition mode → PLL watch transition mode)
Table 6.2-1 Transition Conditions of the Two Clocks System Parts (4/4) is changed.
(Main timer → Main watch)
(Main timer transition → Main watch transition)
(PLL timer → PLL watch)
(PLL timer transition M → PLL watch transition M)
(PLL timer transition P → PLL watch transition P)
(Subclock timer → Subclock watch)
(Pseudo timer → Pseudo watch)
(Pseudo timer transition → Pseudo watch transition)
(PLL timer → PLL watch)
(PLL time transition M → PLL watch transition M)
Table 6.2-2 Transition Conditions of the Single Clock (System) Parts is changed.
(oscillation stabilization wait → oscillation stabilization wait time)
(57 TMD=1,STP=1write is deleted.)
(Pseudo timer transition is deleted.)
(13 PLL/main switching timing wait end → 13 PLL-->main switching timing wait end)
(34 PLL/main switching timing wait end → 34 PLL-->main clock switching timing wait end)
(61 PLL/main switching timing wait end → 61 PLL-->main clock switching timing wait end)
■ Status Transition Diagram for Low-Power Consumption Mode (Two Clocks System Parts) is changed.
(main oscillation stabilization period → main oscillation stabilization time)
Figure 6.3-1 Status Transition Diagram A for Low-Power Consumption Mode (Two Clocks System Parts) is
changed.
(Main oscillation stabilization period → Main oscillation stabilization time)
Table 7.1-1 Mode Pins and Modes is changed.
(The line of Test functions is deleted.)
❍ Operation mode is changed.
(By selecting an operation mode, normal operation, internal test program activation, or special test function
activation can be performed. → By selecting an operation mode, normal operation or internal test program
activation can be performed.)
Table 7.1-2 Mode Pins and Modes is changed.
(Reserved → Prohibited)
■ External Memory Access (Bus Pin Control Circuit) is changed.
(• WRL/WR (P32) : Write signal for lower 8 bits of data bus in 16-bit access mode, for 8-bit access mode → •
WRL/WR (P32) : Write signal for lower 8 bits of data bus write single for 8 bits of data bus in 8-bit access
mode)
■ External Memory Access Control Signal is changed.
(output of the ALE signal without asserting RD, WR, WRL, and WRH → output of the ALE signal without
asserting RD, WRL, WRH and WR.)
Summary of 7.3.1 Ready Function is changed.
(If the RYE bit of the bus control signal selection register (EPCR) is set to 1, → If the RYE bit of the bus control signal selection register (ECSR) is set to "1",)
■ Ready Function is changed.
(If the RYE bit of the EPCR is set to 1 and → If the RYE bit of the ECSR is set to "1" and)
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Changes (For details, refer to main body.)
Summary of 7.3.2 Hold Function is changed.
(the bus control signal selection register (EPCR) is set to 1, → the bus control signal selection register (ECSR)
is set to "1",)
(the external bus hold function → the external address hold function)
■ Hold Function is changed.
(• Address output: P27/A23 to P20/A16 → • Address output: P23/A17 to P20/A16)
(• Address/data I/O: P17/D15 to P00/D00 → • Address/data I/O: P17/AD15 to P00/AD00)
(state and restarting the CPU operation. → state and restarting the bus operation.)
(Figure7.3-4HoldTiming(inanExternalBus16-Bit Mode) → Figure 7.3-4 Hold Timing)
Figure 8.2-2 Port Data Registers (PDR0 to PDRA) (for Port 0 to Port A) is changed.
(Undefined → XXXXXXXXB)
(Undefined → -------XB)
(Read: The pin output value is read. → Read: The value of data register latch is read.)
Summary of 9.3 Operations of Timebase Timer is changed.
(timer for waiting for main clock and PLL clock oscillation to stabilize, → timer for main clock and PLL clock
oscillation stabilization wait time,)
■ Interval Interrupt Function of Timebase Timer is changed.
(the timebase timer is used as a timer that waits for PLL clock oscillation to stabilize. → the timebase timer is
used as a timer for PLL clock oscillation stabilization wait.)
(because the timebase timer is used as a timer that waits for oscillation of the oscillation clock to stabilize. →
because the timebase timer is used as a timer for oscillation stabilization wait of the oscillation clock.)
(because the timebase timer is used as a timer that waits until oscillation to stabilize upon recovery. → because
the timebase timer is used as a timer for oscillation stabilization time wait at recovery.)
Figure 10.1-2 Block Diagram of Watch-dog Timer is changed.
(* is deleted.)
Figure 11.1-2 Block Diagram of Watch Timer is changed.
(* is deleted.)
[bit3] WTR is changed.
(Writing 0 to this bit clears the timer counter. → Writing "0" to this bit clears the watch counter.)
Notes is changed.
(• To clear the watch timer by writing "0" to the WTR bit in the → • To clear the watch timer by writing "0" to
the WTC bit in the)
■ Interval Interrupt Function of Watch Timer is changed.
(signals of the timer counter. → signals of the watch counter.)
(The WTOF flag is set at the intervals specified by → The WTOF flag is set at each intervals specified by)
(This flag is set by using as a reference the last time that the watch timer was cleared. → The timing of flag setting is based on the time when the watch timer was last cleared.)
(oscillation to stabilize upon recovery, → oscillation stabilization time upon recovery,)
■ Setting Operation Clock for Watch-dog Timer is changed.
(The clock source of the watchdog timer can be .set by the WDCS bit in → The clock source of the watch-dog
timer can be set by the watch-dog clock selection bit (WDCS) bit in)
■ Output Compare (2 Channels Per One Module) is changed.
(the output level is reversed and an interrupt is issued. → the output level is reversed and an interrupt can be
issued.)
(Output pins can be controlled based on pairs of the two compare registers. → • Output pins can be controlled
by pairing the two compare registers.)
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Changes (For details, refer to main body.)
The addresses in Figure 12.2-1 16-bit I/O Timer Registers are changed.
(003920H → 003918H)
(003922H → 00391AH)
(Compare registers 0 and 1 → Output compare registers 0 and 1)
(Compare control status registers 0 and 1 → Output compare control status registers 0 and 1)
[bit4] STOP is changed.
(Writing "0" starts the timer. → Writing "0" starts the timer count.)
(Counter enabled (operation) (initial value) → Count enabled (operation) (initial value))
(Counter disabled (stop) → Count disabled (stop))
[bit3] MODE is changed.
(The MODE bit is used to set the reset condition of the 16-bit free-running timer. → The MODE bit is used to
set the initialization condition of the 16-bit free running timer.)
Note of [bit3] MODE is changed.
(The clear bit and a match with the compare register initialize the timer when the timer value changes. → The
clear bit and a match with the compare register initialize the timer at the change point of the timer value.)
[bit2] CLR is changed.
(The counter value is initialized when the count value changes. → The counter value is initialized at the
change point of the count value.)
■ Output Compare is changed.
(• An interrupt can be issued upon a match as a result of comparison. → • An interrupt can be issued by the
compare match.)
■ Control Status Register of Output Compare (OCS0/OCS1) is changed.
(Figure 12.4-3 Control Status Register → Figure 12.4-3 Control Status Register of Output Compare (OCS0/
OCS1))
[bit12] CMOD is changed.
(CMOD is used to switch the pin output level reverse mode upon a → CMOD is used to switch the pin output
level reverse operation mode upon a)
[bit1 and bit0] CST1 and CST0 is changed.
(These bits are used to enable the comparison with 16-bit free-run timer. → These bits are used to enable a
match with 16-bit free running timer.)
Summary of 12.4.3 16-bit Output Compare Operation is changed.
(In the 16-bit output compare operation, an interrupt request flag can be set and the output level can be
reversed when the specified compare register value matches the 16-bit free-run timer value. → The 16-bit output compare compares the specified compare register value with a 16-bit freerun timer value. When a match
occurs, it can set the interrupt request flag and reverse the output level.)
■ Output Compare Timing is changed.
(The text that When the compare register is updated, comparison with the counter value is not performed. is
deleted.)
Figure 12.5-3 Input Capture Control Status Register (ICS01) is changed.
(ICS0/1 → ICS01)
■ Sample of Input Capture Fetch Timing is changed.
(• Capture example: Both edges → • Capture example: Both edges (for example))
Figure 12.5-4 Sample of Input Capture Fetch Timing is changed.
(Capture interrupt → Capture example interrupt)
(Capture 0 = Rising edge
Capture 1 = Falling edge
The description that Capture example = Both edge (for example) is added.)
■ Intelligent I/O Service ( EI2OS) Function and Interrupts is changed.
(The text that EI2OS can be used with both timers on this product. is deleted.)
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Changes (For details, refer to main body.)
Figure 13.1-1 Block Diagram of 16-bit Reload Timer is changed.
(The description that Available clock judge circuit is added.)
(The description that Operation control circuit is added.)
(Re-trigger → Trigger)
(■ Pin Name of 16-bit Reload Timer is added.)
Figure 13.2-1 16-bit Reload Timer Register is changed.
(TMCSR → TMCSR0/1)
(TMR/TMRLR → TMR0/TMRLR0 TMR1/TMRLR1)
Figure 13.2-2 Timer Control Status Register (TMCSR) is changed.
(TMCSR → TMCSR0/1)
[bit6] OUTE is changed.
(TOT outputs a square waveform that indicates that counting is inprogress. → TOT outputs a rectangular
waveform that indicates that counting is in progress.)
Table 13.2-4 OUTE, RELD, and OUTL Settings is changed.
(Output an "H" level square waveform during counting. → Output an "H" level rectangular waveform during
counting.)
(Output an "L" level square waveform during counting. → Output an "L" level rectangular waveform during
counting.)
(Toggle output. Starts with "L" level output. → Toggle output with "L" at count start.)
(Toggle output. Starts with "H" level output. → Toggle output with "H" at count start.)
Summary of 13.3 Internal Clock and External Clock Operations of 16-bit Reload Timer is changed.
(the TIN pin functions as an external event input pin to count the number of valid edges set in the register. →
the TIN pin functions as an external event input pin to count valid edges set in the register.)
Figure 13.3-2 Trigger Input Operation of 16-bit Reload Timer is changed.
(0000H → -1)
Summary of 13.4 Underflow Operation of 16-bit Reload Timer is changed.
(An underflow is defined for this timer as the time when the counter value changes → An underflow is defined
by 16-bit reload timer when the counter value changes)
■ Output Pin Functions of 16-bit Reload Timer is changed.
(The OUTL bit of the control register sets the output polarity. → The OUTL bit of the register sets the output
polarity 16-bit reload timer.)
(The output waveforms are opposite when OUTL="1". → The output waveforms are inverted when OUTL = 1.)
Figure 13.5-1 Output Pin Function of 16-bit Reload Timer (RELD=1, OUTL=0) is changed.
(Level is opposite when OUTL="1". → Level is inverted when OUTL = 1.)
(Trigger → Activating trigger)
Figure 13.5-2 Output Pin Function of 16-bit Reload Timer (RELD=0, OUTL=0) is changed.
(Level is opposite when OUTL="1". → Level is inverted when OUTL = 1.)
(Trigger → Activating trigger)
(Waiting for a trigger → Waiting for an activating trigger)
Figure 13.6-1 Counter State Transitions is changed.
(The description that Activated from TIN is added.)
Summary of 14.1 Outline of 8/16-bit PPG is changed.
(two external pulse output signals, → two external pulse output pins, )
❍ 8-bit prescaler + 8-bit PPG output operation mode is changed.
(❍ 8+8-bit PPG output operation mode → ❍ 8-bit prescaler + 8-bit PPG output operation mode)
❍ PPG output operation is changed.
(The text that The pair of ch0 and ch1 of PPG is called 1 unit. is added.)
(four PPG’s → four units of PPG’s)
(PPG0/1 → ch0 and ch1 of PPG)
(The channel 0 PPG output signal is not connected to any external pin. → Ch0 of PPG is shown PPG (ch0) and
ch1 of PPG is shown PPG (ch1).)
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Changes (For details, refer to main body.)
Figure 14.2-1 8-bit PPG ch0 Block Diagram is changed.
(Some figures and texts are deleted.)
(Channel 1 → PPG(ch1))
(Timebase counter output 512-division of main clock → Timebase timer output 512-division of main clock)
(The text that The PPG output signal of ch0 is not connected with an external terminal. is added.)
Figure 14.2-2 8-bit PPG ch1 Block Diagram is changed.
(PPG10 output enable → PPG0 pin output enable)
(PPG10 → PPG0 pin)
(In MB90540/545Series, this IRQ signal merged with → In MB90540/545 Series, this IRQ signal is merged
with)
(Channel 0 → PPG(ch0))
(PIE → PIE1)
(PUF → PUF1)
■ PPG0 Operation Mode Control Register (PPGC0) is changed.
(PPG00 → PPG0)
(PPG → PPG(ch0))
■ PPG1 Operation Mode Control Register (PPGC1) is changed.
(PPG → PPG(ch1))
(PPG10 → PPG0)
[bit11] PUF1 (PPG underflow flag): PPG counter underflow bit is changed.
(PPG counter underflow is not detected. → PPG (ch1) counter underflow has not been detected.)
(PPG counter underflow is detected. → PPG (ch1) counter underflow has been detected.)
14.3.3 PPG unit 0 Clock Selection Register (PPG01) is changed.
(PPG0/1 → PPG01)
Table in ■ Reload Register (PRLL/PRLH) is changed.
(The text that Sets "L" pulse width. is added.)
(The text that Sets "H" pulse width. is added.)
■ Operations of 8/16-bit PPG is changed.
(pin output → PPG0 output pin)
Table 14.4-1 Reload Operation and Pulse Output is changed.
(PPG00/10 → PPG0 output pin)
❍ Independent two-channel mode is changed.
(The text that The PPG00 pin is connected to the ch0 PPG output, while the PPG10 pin is connected to the ch1
PPG output. is deleted.)
❍ 8-bit prescaler + 8-bit PPG mode is changed.
(The PPG00 pin is connected to the ch0 prescaler output, while the PPG10 pin is connected to the ch1 PPG
output. is deleted.)
❍ 16-bit PPG 1ch mode is changed.
(The PPG00 and PPG10 pins are connected to the 16-bit PPG output. is deleted.)
(For the MB90540/545S eries, the output signal from the Channel 0 PPG is not connected to any external pin.
is deleted.)
Figure 14.4-1 PPG Output Operation, Output Waveform is changed.
(PPG00/10 Output pin → PPG0 Output pin)
■ Relationship Between 8/16-bit PPG Reload Value and Pulse Width is changed.
(P1=T × (L+1) → Pl =T × (L+1))
■ Selecting a Count Clock for 8/16-bit PPG is changed.
(PPG01 register → PPG unit 0 clock selection register)
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Changes (For details, refer to main body.)
14.5 Selecting a Count Clock for 8/16-bit PPG is changed.
(The count clock used for the operation is → The count clock used for the 8/16-bit PPG operation is)
(The count clock can be → The count Input clock can be)
■ Selecting a Count Clock for 8/16-bit PPG is changed.
(input clock from the timebase timer. → input clock from the timebase counter.)
Summary of 14.6 Controlling Pin Output of 8/16-bit PPG Pulses is changed.
(external pins PPG00 and PPG10 → external pins PPG0)
■ Controlling Pin Output of 8/16-bit PPG Pulses is changed.
(When "0" is written to these bits (default) → When "0" is written to bit13 (PE10) of PPG1 operation mode
control register (PPGC1) bits (default))
(Text that To output the pulses from an external pin, write "1" to the bit corresponding to each pin. is deleted.)
(Text that When "1" is written to these bits, the pulses are output from external pins. is added.)
(the 8-bit prescaler toggle output waveform is output from → the 8-bit prescaler toggle waveform is output
from)
(PPG00 → PPG(ch0) output (internal signal))
(PPG10 → PPG(ch1) output (PPG0 pin waveform))
Figure 14.6-1 8-bit Prescaler + 8-bit PPG Output Operation Waveform is changed.
(Pl1 = T × (L0+1) × (Ll+1) → Pl1 = T × (L0+1) × (L1+1))
(Ph1 = T × (L0+1) × (Hl+1) → Ph1 = T × (L0+1) × (H1+1))
(Ph0:PPG00 high pulse width → Ph0 :PPG (ch0) "H" pulse width)
(Pl0:PPG00 low pulse width → Pl0 :PPG (ch0) "L" pulse width)
(Ph1:PPG10 high pulse width → Ph1 :PPG (ch1) "H" pulse width)
(Pl1:PPG10 low pulse width → Pl1 :PPG (ch1) "L" pulse width)
Summary of 14.7 8/16-bit PPG Interrupts is changed.
(For the 8/16-bit PPG, an interrupt becomes active when the reload value counts out and a borrow occurs. →
The 8/16-bit PPG outputs interrupt request when the reload value counts out and a borrow occurs.)
❍ <Registers> is changed.
(0X000XX1B → 0-000--1B)
(0X000001B → 0-000001B)
(PPG10 → XXXXXX00B → PPG01 → 000000--B)
❍ <Pulse outputs> is changed.
(The text is changed to The PPG0 pin is set to be output prohibited. )
❍ <Interrupt requests> is changed.
(The text is changed to It becomes an interrupt prohibition. The reload value is maintained.)
Summary of 15.1 Outline of Delayed Interrupt Module is changed.
(The delayed interrupt source module is used to → The delayed interrupt generating module is used to)
■ Delayed Interrupt Occurrence is changed.
(The text that When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the
delayed interrupt source module is set and an interrupt request is issued to the interrupt controller. is deleted.)
❍ DTP/external interrupt operation procedure is changed.
(The text that 1. Set the general-purpose I/O port that is shared with the pin for the external interrupt input as
the input port. is added.)
❍ Analog input selected from eight channels by programming is changed.
(Stop conversion mode: Voltages at the one channel is converted, → • Stop conversion mode: The specified
channel is converted, )
■ Input Impedance is changed.
(The description of Figure 17.1-2 Input Impedance is added.)
(Driving impedance to an analog input should be lower than 15.5 KΩ → Driving impedance to an analog input
should be 15.5 kΩ or lower)
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■ A/D Converter Registers is changed.
(Figure 17.3-1 A/D Converter Register Configuration → Figure 17.3-1 A/D Converter Register Assignment)
Notes: of [bit2, bit1, and bit0] ANE2, ANE1, and ANE0 (Analog end channel set): is changed.
(Then, once conversion is complete up to channel 7, operation returns to channel 0 and conversion is → Then,
once conversion is complete up to AN7, operation returns to AN0 and conversion is)
(Conversion is performed in the following sequence: CH6, CH7, CH0, CH1, CH2, CH3 → Conversion is performed in the following sequence: AN6 → AN7 → AN0 → AN1 → AN2 → AN3)
Read/Write in Figure 17.3-4 A/D Control Status Register 1 (ADCS1) is changed.
((R/W) → (W))
Summary of 17.3.3 A/D Data Register 0/1(ADCR0 and ADCR1) is changed.
(ADCR1 stores the most significant two bits of the conversion result, while ADCR0 stores the lower eight bits.
→ ADCR1 stores ADCR0 stores the lower 8 bits result, while the most significant 2 bits of the conversion.)
■ A/D Data Registers 0/1 (ADCR0 and ADCR1) is changed.
(Data Registers (ADCR1 and ADCR0) → A/D Data Registers 0/1 (ADCR0 and ADCR1) )
([bits15] S10 → [bit15] SI0)
[bit12 and bit11] CT1 and CT0 (Compare time) is changed.
(The description of (CT1=CT0=0) is deleted.)
Summary of 17.4 Operations of A/D Converter is changed.
(The A/D converter operates employs the sequential compare technique, and has a 10-bit resolution. → The A/
D converter operates in the sequential compare technique, and can select a 10-bit or 8-bit resolution.)
(conversion data registers → A/D data registers 0/1)
■ Single Mode is changed.
(The converter stops operation after the → The A/D converter stops operation after the)
Example of ■ Stop Mode is changed.
(End → Stop)
(Start -> AN2 -> End -> Restart -> AN2 -> End -> Restart -> AN2 Repeat → Start → AN2 → Stop →
Restart → AN2 → Stop → Restart → AN2 → Repeat)
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Table 17.5-1 Example of Starting EI2OS in Single Mode is changed.
(The description of Specifies is deleted.)
(The description of Transfer source address is added.)
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Table 17.5-2 Example of Starting EI2OS in Continuous Mode is changed.
(The description of Specifies is deleted.)
264
Figure 17.5-3 Example of Starting EI2OS in Continuous Mode is changed.
(After six transfers → After a total of six transfers)
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Table 17.5-3 Example of Starting EI2OS in Stop Mode is changed.
(The description of Specifies is deleted.)
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Figure 17.5-4 Example of Starting EI2OS in Stop Mode is changed.
(Activation → Start activation)
Note of ■ Conversion Data Protection Function is changed.
(data protection function → conversion data protection function)
(If interrupts are disabled (INTE=0), this function is disabled. → If interrupts are disabled (INTE=0), this function does not work.)
(Restarting the A/D converter while it is pausing destroys the standby data. → Also, the standby data is
destroyed if the A/D is restarted during a suspension (pause).)
■ Notes on Using the Conversion Data Protection Function is changed.
(ADCS2 register → ADCS1 register)
■ Feature of UART0 is changed.
(The description of Error detect function (framing, overrun, and parity) is deleted.)
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Changes (For details, refer to main body.)
Figure 18.2-1 Overall Block Diagram is changed.
(Receive error indication signal for EI2OS (to CPU) → Receive error generation signal for EI2OS (to CPU))
[bit12] TDRE (Transmitter data register empty) is changed.
(If TIE is active, a transmit interrupt request is → If TIE is active, a receive interrupt request is)
■ CLK Asynchronous Baud Rate is changed.
(The six URD0 register bits: → The six URD register bits,)
(The following settings are available. → The following settings are available for CLK synchronous transfer.)
Note in ■ CLK Asynchronous Baud Rate is changed.
(The baud rate is the CLK synchronous baud rate divided by → The baud rate is the CLK asynchronous baud
rate divided by)
■ Internal and External Clock is changed.
(X: Divider ratio for the count clock source for the internal timer → X: Divider ratio for the count clock source
for the internal clock)
Table 18.6-1 Baud Rate and Reload Value is changed.
(The description of Reload value is added.)
((divide machine cycle by → (divide machine clock by )
■ Transfer Data Format is changed.
(SOUT0 → SOT0)
Figure 18.7-1 Transfer Data Format is changed.
Figure 18.9-1 RDRF Set Timing (Mode 0, 1, or 3) is changed.
Figure 18.9-2 ORFE Set Timing (Mode 0, 1, or 3) is changed.
Figure 18.9-3 PE Set Timing (Mode 0, 1, or 3) is changed.
Figure 18.9-4 RDRF Set Timing (Mode 2) is changed.
Figure 18.9-5 ORFE Set Timing (Mode 2 )is changed.
Summary of 18.9.3 Flag Set Timings for a Transmit Operation is changed.
(UODR0 register is transferred to the internal shift register and the next data → UODR0 register is transferred
to the internal shift register at the transfer operation and the next data)
Figure 18.9-6 TDRE Set Timing (Mode 0) is changed.
Figure 18.9-7 RBF Set Timing (Mode 0) is changed.
Figure 18.9-8 TBF Set Timing (Mode 0) is changed.
Summary of 19.1 Features of UART1 is changed.
(• Transfer communication in NR transfer format → • Transfer signal is NRZ sign)
Note of [bit7, bit6] MD1, MD0 (MoDe select) is changed.
(Mode1, CLK-asynchronous multi-processor mode, is used when one host CPU is connected to multiple slave
CPUs. This UART1 resource is not able to determine the data format of incoming data, and therefore in multiprocessor mode supports only the master processor. → CLK-asynchronous (multi-processor) mode of mode 1,
is used when one host CPU is connected to multiple slave CPUs. This UART1 resource is not able to determine the data format of reception data, and therefore in multi-processor mode supports only the master processor. )
(UMC1 register → SCR1 register)
[bit5 to bit3] CS2, CS1, CS0 (Clock Select) is changed.
(The baud rate is determined at the same time as selection of the baud rate generator. → The baud rate is determined at the same time as selection of the dedicated baud rate generator.)
Note of [bit1] SCKE (SCLK Enable) is changed.
(When the pin functions as a clock input, → When the pin functions as a clock input pin,)
[bit0] SOE (Serial Output Enable) is changed.
(This bit determines whether external pins that also can be used as general purpose I/O port pins will function
as serial output pins (SOT1) or as I/O port pins. → This bit determines whether external pins (SOT1) that also
can be used as general-purpose I/O port pins will function as serial output pins or as I/O port pins.)
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Summary of 19.3.2 Serial Control Register 1 (SCR1) is changed.
(The serial control register (SCR1) register controls the transfer protocol used for serial transmission. → The
serial control register 1 (SCR1) register controls the transfer protocol used for serial communication.)
Figure 19.3-4 Serial Control Register 1 (SCR1) is changed.
(Figure 19.3-4 Serial Control Register (SCR1) → Figure 19.3-4 Serial Control Register 1 (SCR1))
[bit15] PEN (Parity ENable) is changed.
(This bit determines whether parity bits are attached to data in serial transmission. → This bit determines
whether parity bits are attached to data in serial communication.)
(1:Parity → 1: Parity is attached)
Note of [bit15] PEN (Parity ENable) is changed.
(all CLK-synchronous communication (mode 2) → CLK-synchronous communication (mode 2))
Note of [bit12] CL (Character Length) is changed.
(all CLK-synchronous communication (mode 2) → CLK-synchronous communication (mode 2))
[bit10] REC (Receiver Error Clear) is changed.
(A write value of "1" is not valid, and the read value is "1" at all times. → A write value of "1" is not valid, and
the read value is always "1".)
Summary of 19.3.3 Serial Input Data Register 1 (SIDR1) / Serial Output Data Register 1 (SODR1) is changed.
(These registers function as receive and transmit data buffer registers. → Serial Input Data Register 1 (SIDR1)
/Serial Output Data Register 1 (SODR1) are data buffer registers for receive and transmit. )
■ Serial Input Data Register 1 (SIDR1) / Serial Output Data Register 1 (SODR1) is changed.
(When using 7-bit data length, the top bit (D7) contains invalid data. → When using 7-bit data length, the top
1-bit (D7) contains invalid data.)
(Be sure the DTRE bit in the SSR1 register is set to "1" before writing to the SODR1 register. → Be sure the
TDRE bit in the SSR1 register is set to "1" before writing to the SODR1 register. )
Summary of 19.3.4 Serial Status Register 1 (SSR1) is changed.
(The serial status register (SSR1) → The serial status register 1 (SSR1))
[bit12] RDRF (Receiver Data Register Full) is changed.
(This interrupt request flag is set to indicate that data is present in the SIDR1 register. → This interrupt request
flag is set to indicate that reception data is present in the SIDR1 register.)
[bit11] TDRE (Transmit Data Register Empty) is changed.
(This interrupt request flag is set to indicate that outgoing data can be written to the SODR1 register. → This
interrupt request flag is set to indicate that transmission data can be written to the SODR1 register.)
(into the transmit shifter to indicate → into the transmit shifter and transferring to indicate)
(that the next data can be written to the SODR1 register. → that the next transmission data can be written to the
SODR1 register.)
Summary of 19.3.5 UART1 Communication Prescaler Control Register (CDCR) is changed.
(prescaler control register (CDCR) → UART1 communication prescaler control register (CDCR))
■ UART1 Communication Prescaler Control Register (CDCR) is changed.
(The description that Figure 19.3-7 UART1 Communication Prescaler Control Register (CDCR) is added.)
[bit7] MD (Machine clock divide MoDe select) is changed.
(This bit enables the prescaler operation. → This bit enables the communication prescaler operation.)
(0: Prescaler stopped → 0: Communication prescaler stopped)
(1: Prescaler operating → 1: Communication prescaler operating)
[bit3, bit2, bit1, bit0] DIV3 to DIV0 (DIVide 3 to DIVide 0) is changed.
(These bits determine the division of the machine clock frequency → These bits determine the division ratio of
the machine clock frequency)
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Summary of 19.4 UART1 Operating Modes and Clock Selection is changed.
(Changes of mode are controlled by settings in the SMR1 register → Changes of mode are controlled by setting values in the SMR1 register)
Table 19.4-1 UART1 Operating Modes is changed.
(* is added.)
(In asynchronous (start-stop synchronized) normal mode, stop bit length can be set for outgoing transmission
only. For receive, the setting is always 1-bit. → In asynchronous (start-stop synchronized) normal mode, stop
bit length can be set for transmit operation only. For receive, the setting is always 1-bit length.)
❍ Dedicated baud rate generator is changed.
(Also, prescaler settings are shown in Table 19.4-4 "Prescaler Settings". → Also, communication prescaler settings are shown in Table 19.4-4.)
Table 19.4-2 Baud Rates (Asynchronous Communication) is changed.
((φ/div)/(8 × 3 × 22) → (φ/div) / (8 × 13 × 22))
❍ Internal timer is changed.
(When bits CS2-0 are set to"110", the internal timer signal is selected, and the 16-bit (timer0) operates in
reload mode. → When CS2 to CS0 are set to "110B" and the internal timer signal is selected, the reload timer 0
(at 16-bit operating) operates in reload mode.)
❍ Internal timer is changed.
(TOT0 is already connected to → TOT0 has been already connected to)
Table 19.4-5 Baud Rates and Reload Values is changed.
(Reload value is moved.)
((machine cycle division by → (machine clock division by)
■ Asynchronous (Start-Stop Synchronized) Mode Transfer Data Format is changed.
(Figure 19.4-1 Asynchronous (Start-Stop Synchronized) Mode Data Transfer Format (Mode 0, 1) → Figure
19.4-1 Asynchronous (Start-Stop Synchronized) Mode Transfer Data Format (Mode 0, 1))
■ Asynchronous (Start-Stop Synchronized) Mode Receive Operation is changed.
(Appearance of a start bit on the receive → Detection of a start bit on the receive)
(,andthentheRDRFflag(SSTregisterbit12)isset. → , and then the RDRF flag in Serial Status Register (SSR1) is
set.)
(RXE bit (bit 9) → RXE bit)
(RDRF flag (SST register bit 12) → RDRF flag in Serial Status Register (SSR1) )
(RIE bit (bit 9) → RIE bit)
■ Asynchronous (Start-Stop Synchronized) Mode Transmit Operation is changed.
(, the TDRE flag is reset. → , the TDRE flag in SSR1 register is reset. )
(TDRE flag (bit 11) → TDRE flag)
(the UART1 is writing outgoing → the UART1 is writing transmission)
(TXE bit (bit 8) → TXE bit in SCR1)
(the TDRE flag is reset. → the TDRE flag in SSR1 register is reset.)
(TIEbit(bit8) → TIE bit)
Figure 19.4-2 CLK Synchronous Mode Transfer Data Format (Mode 2) is changed.
(SODR write → SODR1 write)
(SCLK → SCK1)
■ UART1 Flags is changed.
(and are released by writing "0" → and are cleared by writing "0")
Figure 19.6-1 PE, ORE, FRE, RDRF Flag Set Timing (Mode 0) is changed.
(The line of Receiving interrupt is added.)
Figure 19.6-4 TDRE Flag Set Timing (Mode 0, 1) and Figure 19.6-5 TDRE Flag Set Timing (Mode 2) are
changed.
(SODR write → SODR1 write)
Figure 19.7-1 Serial Edge Select Register (SES1) is changed.
(Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) → (-) (-) (-) (-) (-) (-) (-) (R/W))
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Changes (For details, refer to main body.)
Figure 20.1-1 Extended Serial I/O Interface Block Diagram is changed.
(The parts of SIN2, SOT2, SCK2 are changed.)
(SDR (Serial data register) → SDR (Serial shift data register))
(Internal clock (Prescaler) → Internal clock (Communication prescaler))
Summary of 20.2 Serial I/O Registers is changed.
(two registers → three registers)
(The description of • Serial I/O prescaler is added.)
Figure 20.2-1 Serial I/O Registers is changed.
(MI → MD)
(Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) → (R/W) (-) (-) (-) (R/W) (R/W) (R/W)
(R/W))
[bit15, bit14, and bit13] SMD2, SMD1, SMD0: Serial shift clock mode (Shift clock selection bits) is changed.
(The text of Setting of the Serial I/O prescaler (SCDCR) is deleted.)
Table 20.2-6 Setting the Interrupt Request Enable Bit is changed.
(SEE → SIE)
[bit8] STRT: Start (Start bit) is changed.
(The text of When the MODE bit is set to 1 and the STRT bit is set to 1, writing the data into serial data register
starts the transfer. is deleted.)
(Writing "1" to this bit starts the data transfer when the MODE bit is set to 0. → Writing "1" to this bit starts
the data transfer in the stop status.)
("0" is always read. → "0" is always read in reading time.)
Figure 20.2-4 Serial I/O Prescaler (SCDCR) is changed.
(MI → MD)
(Read/write (R/W) (R/W) (R/W) (R/W) (R/W) → (R/W) (-) (-) (-) (R/W) (R/W) (R/W) (R/W))
(Initial value (0) (1) (1) (1) (1) → (0) (-) (-) (-) (1) (1) (1) (1))
[bit15] MD (Machine clock divide mode select) is changed.
(This bit is used to control the operation of the communication prescaler. → This bit is used to enable the operation of the communication prescaler.)
■ Internal Shift Clock Mode is changed.
(A is a frequency-division ratio and is 21, 22, 24, 25, or 26 indicated by the SMCS SMD bits. → A is a frequency-division ratio and is 21, 22, 24, 25, or 26 indicated by the SMD bits of SMCS.)
Table 20.3-1 Formulas for Calculating Baud Rate in Internal Shift Clock Mode is changed.
(62.5Hz → 62.5 kHz)
■ External Shift Clock Mode is changed.
(In external shift clock mode, the data transfer is based on the external clock → In external shift clock mode,
the data transfer is based on the external shift clock)
(A data bit can also be transferred by software, which is enabled as described below. → A data bit can also be
transferred by instruction, which is enabled as described below.)
❍ Halt is changed.
(the counter is initialized, and the system stops. → the counter is initialized, and the system halts.)
(To resume operation from the stop state, → To resume operation from the halt state,)
Summary of 20.3.3 Shift Operation Start/Stop Timing is changed.
(The system may stop the shift operation at the end of transfer or when "1" is set in the STOP bit. → The system may stop the shift operation when "1" is set in the STOP bit or at the end of transfer.)
Figure 20.3-9 Interrupt Signal Output Timing of Serial I/O is changed.
(Figure 20.3-9 Interrupt Signal Output Timing of the Extended Serial I/O Interface → Figure 20.3-9 Interrupt
Signal Output Timing of Serial I/O)
(* is added.)
(SDR RD/WR → RD/WR of SDR)
Read/write in Figure 20.4-1 Serial Edge Select Register (SES2) is changed.
(Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) → (-) (-) (-) (-) (-) (-) (-) (R/W))
xxix
Reference: Main changes (Rev.4 → Rev.5)
Page
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354
356
357
359
362
362,363
363
367
370
372
Changes (For details, refer to main body.)
Table 21.3-1 List of Overall Control Registers (1/2) is changed.
(Initial Value of CSR 00---000 0----0-1 → 00---000 0----001)
Summary of 21.6.1 Control Status Register (CSR) is changed.
(, use any bit manipulation instructions → , it is possible to use any bit manipulation instructions)
[bit0] HALT: Bus operation stop bit is changed.
(0:Bus operation not in stop state → 0: Bus operation inprogress)
Notes: of ■ Conditions for Setting Bus Operation Stop (HALT=1) are changed.
((stop mode, timer mode, and hardware stand-by mode) → (stop mode, clock mode, and hardware stand-by
mode))
(stop the bus operation (HALT=1) after → the bus operation is stopped (HALT = 1) after)
[bit7] NTE: Node status transition event bit is changed.
(Writing 0 to this bit sets the NTE bit to 0. → Writing "0" to this bit sets the NT bit to "0".)
Summary of '21.6.5 Bit Timing Register (BTR) is changed.
(Bit timing register (BTR) stores the prescaler and bit timing setting. → Bit timing register (BTR) sets the
prescaler and bit timing.)
Initial value in Figure 21.6-5 Bit Timing Register (BTR) is changed.
((-) (1) (1) (1) (1) (1) (0) (0) → (-) (1) (1) (1) (1) (1) (1) (1))
[bit14 to bit12] TS2.2 to TS2.0: Time segment 2 setting bit 2 to bit 0 is changed.
(These bits define the number of the time quanta (TQ’s) for → These bits define the number of the time quanta
(TQ’s) by dividing [(TS2.2 to TS2.0)+1] for)
[bit11 to bit8] TS1.3 to TS1.0: Time segment 1 setting bit 3 to bit 0 is changed.
(These bits define the number of the time quanta (TQ’s) for → These bits define the number of the time quanta
(TQ’s) by dividing [(TS1.3 to TS1.0)+1] for)
[bit7 and bit6] RSJ1 and RSJ0: Resynchronization jump width setting bit 1 and bit 0 is changed.
(These bits define the number of the time quanta (TQ’s) for → These bits define the number of the time quanta
(TQ’s) by dividing [(RSJ1 to RSJ0)+1] for)
[bit5 to bit0] PSC5 to PSC0: Prescaler setting bit 5 to bit 0 is changed.
(These bits define the time quanta (TQ) of → These bits define the time quanta (TQ) by dividing the frequency
[(PSC5 to PSC0)+1] of)
(The relationship between PSC = PSC5 to PSC0, TSI = TS1.3 to TS1.0, → The relationship between PSC =
PSC5 to PSC0, TS1 = TS1.3 to TS1.0,)
(The input clock is supplied with the machine clock. → The input clock is built-in to the machine clock.)
(In order to meet the bit timing requirements defined in the CAN specification, additions have to be met, e.g.
the propagation delay has to be considered. → In order to meet the bit timing settings defined in the CAN specification, the other conditions, e.g. delay time, should be considered.)
■ Bit Timing Register (BTR) is changed.
(TSI = TS1.3 to TS1.0, → TS1 = TS1.3 to TS1.0, TS2 = TS2.2 to TS2.0,)
■ Transmission RTR Register (TRTRR) is changed.
(0: Data frame → 0: Data frame is transmitted)
(1: Remote frame → 1: Remote frame is transmitted)
Note of ❍ Conditions for TCx = 0 is changed.
(If setting to 1 by completion of the transmit operation and clearing to 0 by writing occur at the same time, the
bit is set to 1. → If setting to "1" by completion of the transmit operation and clearing by writing "0" occur at
the same time, the setting of "1" is prior. )
Note of ❍ Conditions for RCx = 0 is changed.
(If setting to 1 by completion of the receive operation and clearing to 0 by writing occur at the same time, the
bit is set to 1. → If setting to "1" by completion of the receive operation and clearing by writing "0" occur at
the same time, the setting to "1" is prior.)
xxx
Reference: Main changes (Rev.4 → Rev.5)
Page
373
374
380
382
389
390
402
405
Changes (For details, refer to main body.)
Note of ❍ Conditions for RRTRx = 0 is changed.
(If setting to 1 by completion of the recieve operation and clearing to 0 by writing occur at the same time, the
bit is set to 1. → If setting to "1" by completion of the receive operation and clearing by writing "0" occur at
the same time, the setting to "1" is prior.)
Summary of 21.6.16 Receive Overrun Register (ROVRR) is changed.
(If RCx of the reception complete register (RCR) is 1 → If RCx of the reception complete register (RCR) has
been already "1")
■ Receive Overrun Register (ROVRR) is changed.
(write 0 to ROVRx to set it to 0. → writing "0" to ROVRx clears it to "0".)
Note of ■ Receive Overrun Register (ROVRR) is changed.
(If setting to 1 by completion of the recieve operation and clearing to 0 by writing occur at the same time, the
bit is set to 1. → If setting to "1" by completion of the receive operation and clearing by writing "0" occur at
the same time, the setting to "1" is prior.)
■ Message Buffers is changed.
((See 21.12 "Procedure for Reception by Message Buffer (x)"). → (See "21.13 Setting Configuration of Multilevel Message Buffer").)
Note of ■ Message Buffers is changed.
(This is also true for general-purpose RAM → This is also same for general-purpose RAM)
Notes: of ■ ID Register x (x = 0 to 15) (IDRx) is changed.
(ID17 to ID0 stores image of old message left in → ID17 to ID0 stores indefinite value of the part of old message left in)
■ Storing Received Message is changed.
(• Basically, message buffers with the RCx bit of 0 in the receive completion register (RCR) are preferred in
storing received messages. → • Basically, message buffers with the RCx bit of "0" in the receive completion
register (RCR) are preceded in storing received messages.)
(• If the bits of the acceptance mask select register (AMSR) → • If each bit of the acceptance mask select register (AMSR))
(• Message buffers should be arranged in ascending numeric order. The lowest message buffers should be with
All Bits Compare, then AMR0 or AMR1 masks. And The text that The highest message buffers should be with
All Bits Mask.is deleted.)
■ Receive Overrun is changed.
(The ROVRx bit in the receive overrun register (ROVRR) is set to 1, indicating receive → The ROVRx bit in
the receive overrun register (ROVRR) is set to "1", and indicates receive)
• No Use of Message Buffer 0 is changed.
(• Don't use the message buffer 0. → Do not use the message buffer "0" for transmission and reception.)
Operation for composing transmission message is changed.
(For composing a transmission message, it is necessary to disable the message buffer by BVAL bit to change
contents of ID and IDE registers. In this case, BVAL bit should reset (BVAL=0) after checking if TREQ bit is
0 or after completion of the previous message transmission (TC=1). → For composing a transmission message,
it is necessary to disable the message buffer by BVAL bit to set ID and IDE registers. In this case, BVAL bit
should reset (BVAL=0) after checking if TREQ bit is "0" (TREQ=0) by reading transmission request bit or
after completion of the previous message transmission (TC=1) by transmission complete bit.)
■ Program Address Detection Registers (PADR0 and PADR1) is changed.
(ADCSR → PACSR)
(Whenthecorrespondinginterruptbitis0,nothingoccurs. → When the corresponding interrupt bit is "0", nothing
occurs even if they match.)
■ Program Address Detection Control Status Register (PACSR) is changed.
(ADR1 → PADR1)
Figure 22.2-2 Program Address Detection Control Status Register (PACSR) is changed.
((R/W) → (-))
((-) → (0))
xxxi
Reference: Main changes (Rev.4 → Rev.5)
Page
406
408
409
411
415
416
421
422
424
426
428
429
Changes (For details, refer to main body.)
[bit3] AD1E (Address detect register 1 enable) is changed.
(ASIE is deleted.)
(The AD1E bit is the operation permission bit of ASIE ADR1. → The AD1E bit is the operation permission bit
of PADR1.)
[bit1] AD0E (Address Detect register 0 Enable) is changed.
(The AD0E bit is the operation permission bit of ADR0. → The AD0E bit is the operation permission bit of
PADR0.)
Table 22.4-1 EEPROM Memory Map is changed.
(Main body of patch program No.0 → Main body of patch program No. 0 and No. 1)
❍ INT9 instruction is changed.
(INT9 interrupt → INT9 instruction)
Summary of CHAPTER 23 ROM MIRRORING FUNCTION SELECTION MODULE is deleted.
(This chapter explains the ROM mirroring function selection module. → This chapter explains the function
and the operation of the ROM mirroring function selection module.)
Summary of CHAPTER 24 1M/2M-BIT FLASH MEMORY is deleted.
(• Serial programmer → • Serial dedicated programmer)
■ 1M/2M-bit Flash Memory Features is changed.
(• Sector erase function (any combination of sectors) → • Enabled sector erase function (any combination of
sectors is available))
■ Writing to/Erasing Flash Memory is changed.
(The flash memory cannot be written to and read at the same time. → The flash memory cannot be written to
or erased and read at the same time.)
[bit4] RDY (ReaDY) is changed.
(The description that Suspend commands, such as is deleted.)
[bit2 and bit0] LPM1 and LPM0 (Low Power Mode) is changed.
(These bits control the current consumed by the flash memory when the flash memory is accessed. → These
bits control the power consumption by the flash memory when the LPM1 and LPM0 are used.)
(• 11: Low power consumption mode (Operates at an internal operating frequency up to 10MHz.) → • 11:
Low power consumption mode (Operates at an internal operating frequency up to 12.58 MHz.) )
Note of [bit2 and bit0] LPM1 and LPM0 (Low Power Mode) is changed.
(Create a program so that → Make a program so that)
(The text that (See Figure 24.4-2 RDYINT and RDY Bit Change Timing). is added.)
Summary of 24.5 Starting the Flash Memory Automatic Algorithm is changed.
(Read/Reset, Write, and Chip Erase → Read/Reset, Write, Chip Erase, and Sector Erase)
Table 24.5-1 Command Sequence Table is changed.
(FxAAA → FxAAAA)
■ Hardware Sequence Flags is changed.
(When creating a program, → When making a program,)
(The text that The following sections describe each hardware sequence flag separately. is deleted.)
❍ Write is changed.
(the flash memory to output the opposite data of bit 7 last written, → the flash memory to output the inverted
data of bit7 last written,)
❍ Write/chip sector erase is changed.
(the flash memory to toggle the 1 or 0 state for every read cycle, → the flash memory to toggle "1" or "0" state
alternately for every read cycle,)
❍ Write/chip sector erase is changed.
(The text that Occasionally, it is likely to end normally as writing "1". is added.)
xxxii
Reference: Main changes (Rev.4 → Rev.5)
Page
440
442
442
444
445
Changes (For details, refer to main body.)
■ Suspending Erasing of Flash Memory Sectors is changed.
(maximum period of 15µs → maximum period of 20µs)
(The text that Please execute the sector erase suspend command after 20µs or more after issuing the sector
erase command or the sector erase restart command. is added.)
❍ Input of a hardware reset (RST) is changed.
(Upper line is added to RST)
(By hardware reset or the power supply's cutting during erasing may make the sector being erased unusable. →
By hardware reset or the power supply's switching off during erasing may make the sector being erased unusable.)
❍ Program access to flash memory is changed.
(The text that For the same reason, all interrupt sources other than the flash memory are disabled while the
automatic algorithm is operating.. Also, while the automatic algorithm is being executed, all interrupt sources
except flash memory are disabled.is deleted.)
❍ Hold function is changed.
((HDE bit of EPCR set to 1) → (HDE bit of ECSR set to "1"))
(control status register (FMCS) is 0. → flash memory control status register (FMCS) is "0".)
❍ Applying VID is changed.
(Applying VID required for the sector protect operation should always be started and terminated when the supply voltage is on. → Applying VID required for the sector protect operation should be started and terminated
when the power supply is on.)
■ Programming Example of 1M/2M-bit Flash Memory is changed.
(;4: Reads the written value (address: FD0000H, sector: SA0/SA2) and outputs it to PDR2. → ;4: Reads the
written value (address: FE0000H, sector: SA0/SA2) and outputs it to PDR2.)
■ Programming Example of 1M/2M-bit Flash Memory is changed.
(;Main program (SAI) → ;Main program (SA1))
(MOVS ADB,PCB ;Transfer of 100H from FFBC00H to 00700H → MOVS ADB,PCB ;Transfer of 100H from
FFBC00H to 000700H)
Table 25.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming is changed.
(The text that Input a "L" level to P00 and a "H" level to P01. is added.)
Figure 25.2-1 Example of Serial Programming Connection for MB90F543/F549/F543G(S)/F548G(S)/
F549G(S)/F546G(S)/F548GL(S) Single-chip Modes (User Power Supply Used) is changed.
454
(TICS → /TICS)
(TRES → /TRES)
Figure 25.3-1 Example of Serial Programming Connection for MB90F543/F549/F543G(S)/F548G(S)/
F549G(S)/F546G(S)/F548GL(S) Single-chip Modes (Power Supplied from the Programmer) is changed.
456
(TICS → /TICS)
(TRES → /TRES)
Figure 25.4-1 Example of Minimum Connection to the MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/
458
F546G(S)/F548GL(S) Flash Microcomputer Programmer (User Power Supply Used) is changed.
(TRES → /TRES)
Figure 25.5-1 Example of Minimum Connection to the MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/
460
F546G(S)/F548GL(S) Flash Microcomputer Programmer (Power Supplied from the Programmer) is changed.
(TRES → /TRES)
Summary of APPENDIX A I/O Maps is changed.
464
(Table A-1 "I/O Map" lists addresses to be assigned to the registers in the peripheral blocks. → Table A-1 and
Table A-2 lists addresses to be assigned to the registers in each resource of this microcontroller.)
The Register of the following registers in Table A-1 I/O Map is changed.
464 to 472 (PDR0 to PDRA, DDR0 to DDRA, ADER, PUCR0 to PUCR3, URD0, CDCR, SMCS, SDR, ENIR, EIRR,
TMR0/TMRLR0, TMR1/TMRLR1, FMCS, IPCP0 to IPCP7)
451
xxxiii
Reference: Main changes (Rev.4 → Rev.5)
Page
465, 466
466
467
468, 469
477
480
481
482
491
510
Changes (For details, refer to main body.)
Accesses of the following registers in Table A-1 I/O Map are changed.
(UMC0, USR0, SCR1, SSR1, ADCR1, PPGC0 to PPGC7)
Resources in the following registers in Table A-1 I/O Map are changed.
(PPGC0, PPGC1, PPGC2, PPGC3, PPGC4, PPGC5, PPGC6, PPGC7)
Accesses of the following registers in Table A-1 I/O Map (4/7) are changed.
(ROMM)
Initial values of the following registers in Table A-1 I/O Map are changed.
(ICR00 to ICR15)
Table B.3-1 Direct Addressing Registers is changed.
(R5W → RW5)
Figure B.3-6 Example of Abbreviated Direct Addressing (dir) is changed.
(MOVW S ; 20H, A → MOV S : 20H, A)
Figure B.3-7 Example of Direct Addressing (addr16) is changed.
Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp) is changed.
(SETB I:0C1H: → SETB i : 0C1H )
Note is changed.
(IN vct8( 0to 7) → INT #vct8 (#0 to #7))
Summary of B.5 Execution Cycle Count is changed.
(and the number of cycles for instruction fetch. → and the number of cycles for fetch. )
■ Execution Cycle Count is changed.
(and the number of cycles for instruction fetch. → and the number of cycles for program fetch. )
Table B.8-17 6 Accumulator Operation Instructions (Byte, Word) is changed.
(SWAPW / XCHW A, T → SWAPW)
xxxiv
CHAPTER 1 OVERVIEW
This chapter explains the features and basic specifications of the MB90540/545 series
products.
1.1 Product Overview
1.2 Features
1.3 Block Diagram
1.4 Package Dimensions
1.5 Pin Assignment
1.6 Pin Functions
1.7 I/O Circuits
1.8 Handling the Device
1
CHAPTER 1 OVERVIEW
1.1
Product Overview
The following table provides a quick outlook of the MB90540/545 Series
■ Overview of MB90540/545 Series Products
Table 1.1-1 Overview
Features
MB90V540/
V540G
MB90F543/F549/F543G(S)/F548G(S)/
F549G(S)/F546G(S)/F548GL(S)
MB90543G(S)/547G(S)/548G(S)/
549G(S)
F2MC-16LX CPU
CPU
On-chip PLL clock multiplier (x1, x2, x3, x4, 1/2 when PLL stop)
Minimum instruction execution time: 62.5 ns (4 MHz osc. PLL x4)
System clock
ROM capacity
RAM capacity
External
Flash memory
MB90F543/F543G(S)/F548G(S)/
F548GL(S): 128 Kbytes
MB90F549/F549G(S)/F546G(S):
256 Kbytes
MASK ROM
MB90547G(S):64 Kbytes
MB90543G(S)/548G(S):
128 Kbytes
MB90549G(S): 256 Kbytes
8 Kbytes
MB90F548G(S)/F548GL(S): 4K bytes
MB90F543/F549/F543G(S)/F549G(S):
6 Kbytes
MB90F546G(S): 8Kbytes
MB90547G(S):2 Kbytes
MB90548G(S):4 Kbytes
MB90543G(S)/549G(S): 6 Kbytes
MB90F543/F549/F543G/F548G/F549G/
F546G/F548GL:
2 clocks system
MB90F543GS/F548GS/F549GS/F546GS/
F548GLS: Single clock (system)
MB90543G/547G/548G/549G:
2 clocks system
MB90543GS/547GS/548GS/
549GS: Single clock (system)
Two clocks *1
Clocks
system
Package
Emulator- specific
power supply *2
PGA-256
QFP100, LQFP100
None
-
*1: When single clock (system) is used, provide the clock from the tool side at X0A and X1A pins.
*2: It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.
Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power) about details.
Note:
With the product with G-suffix at the end of part numbers, functionality the CAN controller is
enhanced. Please refer to the description of the Bit Timing Register in "CHAPTER 21 CAN
CONTROLLER".
2
CHAPTER 1 OVERVIEW
1.2
Features
Table 1.2-1 lists the features of the MB90540/545 series.
■ Features
Table 1.2-1 MB90540/545 Features (1/2)
Function
Feature
UART0
Full duplex double buffer
Supports asynchronous/synchronous (with start/stop bit) transfer
Baud rate: 4808/5208/9615/10417/19230/38460/62500/500000bps
(asynchronous)
500K/1M/2Mbps (synchronous) at System clock = 16MHz
UART1
(SCI)
Full duplex double buffer
Asynchronous (start-stop synchronized) and CLK-synchronous
communication
Baud rate: 1202/2404/4808/9615/192301/31250/38460/62500bps
(asynchronous)
62.5K/125K/250K/500K/1Mbps (synchronous) at 6,8,10,12,16 MHz
Serial I/O
Transfer can be started from MSB or LSB
Supports internal clock synchronized transfer and external clock
synchronized transfer
Supports positive-edge and negative-edge clock synchronization
Baud rate: 31.25K/62.5K/125K/500K/1M/2M bps at System clock =
16MHz
A/D Converter
10-bit or 8-bit resolution
8 input channels
Conversion time: 26.3µs (per one channel)
16-bit Reload
Timer
(2 channels)
Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = System clock
frequency)
Supports External Event Count function
16-bit I/O Timer
Signals an interrupt when overflow
Supports Timer Clear when a match with Output Compare (Channel 0)
Operation clock freq.: fsys/22, fsys/24, fsys/26, fsys/28(fsys = System
clock freq.)
16-bit Output
Compare
(4 channels)
Signals an interrupt when a match with 16-bit I/O Timer
Four 16-bit compare registers
A pair of compare registers can be used to generate an output signal
16-bit Input
Capture
(8 channels)
Rising edge, falling edge or rising & falling edge sensitive
Four 16-bit Capture registers
Signals an interrupt upon external event
3
CHAPTER 1 OVERVIEW
Table 1.2-1 MB90540/545 Features (2/2)
Function
Feature
8/16-bit
Programmable
Pulse Generator
(4 channels)
Supports 8-bit and 16-bit operation modes
Two × four units 8-bit reload counters
Two × four units 8-bit reload registers for "L" pulse width
Two × four units 8-bit reload registers for "H" pulse width
A pair of 8-bit reload counters can be configured as one 16-bit reload
counter or as 8-bit prescaler plus 8-bit reload counter
4 output pins
Operation clock freq.: fsys, fsys/21, fsys/22, fsys/23, fsys/24 or
128µ[email protected]=4MHz
(fsys = System clock frequency, fosc = Oscillation clock frequency)
CAN Interface
MB90540 series:
2 channels
MB90545 series:
1 channel
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering: Full bit compare / Full bit
mask / 2 partial bit masks
Supports up to 1Mbps
External Interrupt
Can be programmed edge sensitive or level sensitive
External bus
interface
External access using the selectable 8-bit or 16-bit bus is enabled
(external bus mode).
I/O Ports
81 general purpose I/O ports
All push-pull outputs and schmitt trigger inputs
Bit-wise programmable as input/output or peripheral signal
32 kHz subclock
Subclock for low-power operation
Flash Memory
Supports automatic programming, Embedded AlgorithmTM *
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles: 10,000 times
Data retention time: 10 years
Boot block configuration
Erase can be performed on each block
Block protection by externally programmed voltage
*: Embeded Algorithm is a trade mark of Advanced Micro Devices, Inc.
4
CHAPTER 1 OVERVIEW
1.3
Block Diagram
Figure 1.3-1 shows a block diagram of the MB90540/545 series.
■ Block Diagram
Figure 1.3-1 Block Diagram
X0, X1
X0A, X1A
RST
HST
Clock
Controller
F2MC-16LX
CPU
RAM
4 Kbytes/
6 Kbytes/
8 Kbytes
I/O Timer
Input
Capture
ROM
128 Kbytes/
256 Kbytes
SOT0
SCK0
SIN0
UART0
IN6/OUT2, IN7/OUT3
Output
Compare
Internal data bus
Prescaler
Prescaler
SOT1
SCK1
SIN1
IN0 to IN5
UART1
(SCI)
8/16-bit
PPG
CAN
Controller
16-bit Reload
OUT0, OUT1
PPG0 to PPG3
RX0, RX1*
TX0, TX1*
TIN0, TIN1
TOT0, TOT1
Prescaler
SCK2
SOT2
SIN2
AVCC
AVSS
AN0 to AN7
AVRH
AVRL
ADTG
AD00 to AD15
A16 to A23
Serial I/O
External
bus
interface
10-bit
ALE
RD
WRL/WR
WRH
HRQ
HAK
RDY
CLK
External
Interrupt
INT0 to INT7
*: Only the MB90540 series has two channels.
5
CHAPTER 1 OVERVIEW
1.4
Package Dimensions
Figure 1.4-1 shows the package dimensions of the FPT-100P-M06. Figure 1.4-2 shows
the package dimensions of the FPT-100P-M05.
Note that the dimensions shown below are reference dimensions.
For formal dimensions of each package, contact us.
■ FPT-100P-M06 Package Dimensions
Figure 1.4-1 FPT-100P-M06 Package Dimensions
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP100-14×20-0.65
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
"A"
C
6
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8˚
31
2002 FUJITSU LIMITED F100008S-c-5-5
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
CHAPTER 1 OVERVIEW
■ FPT-100P-M05 Package Dimensions
Figure 1.4-2 FPT-100P-M05 Package Dimensions
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.0 × 14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.65g
Code
(Reference)
P-LFQFP100-14×14-0.50
(FPT-100P-M05)
100-pin plastic LQFP
(FPT-100P-M05)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
100
26
25
1
C
2003 FUJITSU LIMITED F100007S-c-4-6
0.20±0.05
(.008±.002)
0.08(.003)
M
0.10±0.10
(.004±.004)
(Stand off)
0°~8°
"A"
0.50(.020)
+.008
1.50 –0.10 .059 –.004
(Mounting height)
INDEX
0.145±0.055
(.0057±.0022)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
7
CHAPTER 1 OVERVIEW
1.5
Pin Assignment
Figure 1.5-1 shows the pin assignments of the FPT-100P-M06. Figure 1.5-2 shows the
pin assignments of the FPT-100P-M05.
■ Pin Assignment
HST
MD2
P70/IN0
P72/IN2
P71/IN1
P73/IN3
P74/IN4
P75/IN5
P76/OUT2/IN6
P77/OUT3/IN7
P80/PPG0
P81/PPG1
P82/PPG2
P83/PPG3
P84/OUT0
P85/OUT1
P86/TIN1
P87/TOT1
P91/INT1
P90/INT0
P92/INT2
P93/INT3
P94/TX0
P95/RX0
P96/TX1
P97/RX1
PA0
RST
X0A
X1A
Figure 1.5-1 Pin Assignment of FPT-100P-M06
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS
81
50
MD1
X0
82
49
MD0
X1
83
48
P57/TOT0
VCC
84
47
P56/TIN0
P00/AD00
85
46
P67/AN7
P01/AD01
86
45
P66/AN6
P02/AD02
87
44
P65/AN5
P03/AD03
88
43
P64/AN4
P04/AD04
89
P05/AD05
P06/AD06
90
P07/AD07
92
42
VSS
41
P63/AN3
40
39
P62/AN2
P61/AN1
93
38
P60/AN0
94
37
AVSS
P12/AD10
95
36
AVRL
P13/AD11
96
35
AVRH
P14/AD12
97
34
AVCC
P15/AD13
98
33
P55/ADTG
P16/AD14
99
32
P54/INT7
P17/AD15
100
31
P53/INT6
91
P52/INT5
P50/SIN2
P51/INT4
C
P47/SCK2
P46/SOT2
P45/SOT1
P44/SCK1
VCC
P42/SIN0
P43/SIN1
P40/SOT0
P41/SCK0
P37/CLK
P35/HAK
P36/RDY
P33/WRH
P34/HRQ
P32/WRL/WR
P30/ALE
VSS
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P31/RD
7 8
P27/A23
P23/A19
5 6
P26/A22
4
P25/A21
2 3
P24/A20
1
P20/A16
FPT-100P-M06
P21/A17
P22/A18
P10/AD08
P11/AD09
8
QFP-100
MB90540/545 series
(TOP VIEW)
CHAPTER 1 OVERVIEW
100 P21/A17
99 P20/A16
98 P17/AD15
97 P16/AD14
96 P15/AD13
95 P14/AD12
94 P13/AD11
93 P12/AD10
92 P11/AD09
91 P10/AD08
90 P07/AD07
89 P06/AD06
88 P05/AD05
87 P04/AD04
86 P03/AD03
85 P02/AD02
84 P01/AD01
83 P00/AD00
82 VCC
81 X1
80 X0
79 VSS
78 X0A
77 X1A
76 PA0
Figure 1.5-2 Pin Assignment of FPT-100P-M05
LQFP-100
MB90540/545 series
(TOP VIEW)
FPT-100P-M05
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RST
P97/RX1
P96/TX1
P95/RX0
P94/TX0
P93/INT3
P92/INT2
P91/INT1
P90/INT0
P87/TOT1
P86/TIN1
P85/OUT1
P84/OUT0
P83/PPG3
P82/PPG2
P81/PPG1
P80/PPG0
P77/OUT3/IN7
P76/OUT2/IN6
P75/IN5
P74/IN4
P73/IN3
P72/IN2
P71/IN1
P70/IN0
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P50/SIN2
P51/INT4
P52/INT5
P53/INT6
P54/INT7
P55/ADTG
AVCC
AVRH
AVRL
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
VSS
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P56/TIN0
P57/TOT0
MD0
MD1
MD2
HST
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
P30/ALE
P31/RD
VSS
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SOT0
P41/SCK0
P42/SIN0
P43/SIN1
P44/SCK1
VCC
P45/SOT1
P46/SOT2
P47/SCK2
C
9
CHAPTER 1 OVERVIEW
1.6
Pin Functions
Table 1.6-1 lists pin names, circuit types, and pin functions.
■ Pin Functions
Table 1.6-1 Pin Functions (1/7)
Pin No.
Pin name
I/O Circuit
type*3
A
(Oscillation)
Function
LQFP*2
QFP*1
80
81
82
83
X0
X1
78
80
X0A
77
79
X1A
A
(Oscillation)
75
77
RST
B
External reset request input pin
50
52
HST
C
Hardware standby input pin
91 to
98
85 to
92
93 to
100
I
I/O pins for 8 lower bits of the external address/data bus. This
function is enabled when the external bus is enabled.
P10 to P17
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode.
I
AD08 to
AD15
I/O pins for 8 higher bits of the external address/data bus.
This function is enabled when the external bus is enabled.
General I/O port with programmable pull-up. In external bus
mode, this function is valid when the corresponding bits in the
external address output control resister (HACR) are set to “1”.
1 to 8
I
A16 to A23
*1: FPT-100P-M06
*2: FPT-100P-M05
*3: Refer to "1.7 I/O Circuits" for I/O circuit type.
10
Low speed crystal oscillator input pins. For the one clock system parts, leave it open.
AD00 to
AD07
P20 to P27
99 to 6
Low speed crystal oscillator input pins. For the one clock system parts, perform external pull-down processing.
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode.
P00 to P07
83 to
90
High speed crystal oscillator input pins
8-bit I/O pins for A16 to A23 at the external address/data bus.
In external bus mode, this function is valid when the corresponding bits in the external address output control resister
(HACR) are set to “0”.
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Functions (2/7)
Pin No.
LQFP*2
QFP*1
Pin name
I/O Circuit
type*3
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode.
P30
7
8
10
9
I
ALE
Address latch enable output pin. This function is enabled
when the external bus is enabled.
P31
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode.
10
12
I
RD
Read strobe output pin for the data bus. This function is enabled when the external bus is enabled.
P32
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode or when the WR/WRL pin
output is disabled.
WRL
I
WR
12
13
13
Write strobe output pin for the data bus. This function is enabled when both the external bus and the WR/WRL pin output are enabled. WRL is write-strobe output pin for the lower
8 bits of the data bus in 16-bit access. WR is write-strobe output pin for the 8 bits of the data bus in 8-bit access.
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode, external bus 8-bit mode or
when WRH pin output is disabled.
P33
11
Function
I
WRH
Write strobe output pin for the 8 higher bits of the data bus.
This function is enabled when the external bus is enabled,
when the external bus 16-bit mode is selected, and when the
WRH output pin is enabled.
P34
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode or when the hold function is
disabled.
14
I
HRQ
Hold request input pin. This function is enabled when both the
external bus and the hold functions are enabled.
P35
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode or when the hold function is
disabled.
15
I
HAK
Hold acknowledge output pin. This function is enabled when
both the external bus and the hold functions are enabled.
*1: FPT-100P-M06
*2: FPT-100P-M05
*3: Refer to "1.7 I/O Circuits" for I/O circuit type.
11
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Functions (3/7)
Pin No.
LQFP*2
QFP*1
Pin name
I/O Circuit
type*3
P36
14
15
16
16
I
Ready input pin. This function is enabled when both the
external bus and the external ready functions are enabled.
P37
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode or when the clock output is
disabled.
17
H
CLK
Clock output pin. This function is enabled when both the
external bus and clock outputs are enabled.
P40
General I/O port. This function is enabled when UART0
disables the serial data output.
18
G
Serial data output pin for UART0. This function is enabled
when UART0 enables the serial data output.
General I/O port. This function is enabled when UART0
disables serial clock output.
P41
19
G
Serial clock I/O pin for UART0. This function is enabled when
UART0 enables the serial clock output.
SCK0
P42
18
19
20
20
General I/O port. This function is always enabled.
G
SIN0
Serial data input pin for UART0. Set the corresponding Port
Direction Register (DDR) to input if this function is used.
P43
General I/O port. This function is always enabled.
21
G
SIN1
Serial data input pin for UART1. Set the corresponding Port
Direction Register (DDR) to input if this function is used.
P44
General I/O port. This function is enabled when UART1
disables the clock output.
22
G
Serial clock pulse I/O pin for UART1. This function is
enabled when UART1 enables the serial clock output.
SCK1
General I/O port. This function is enabled when UART1
disables the serial data output.
P45
22
24
G
SOT1
*1: FPT-100P-M06
*2: FPT-100P-M05
*3: Refer to "1.7 I/O Circuits" for I/O circuit type.
12
General I/O port with programmable pull-up. This function is
enabled in the single-chip mode or when the external ready
function is disabled.
RDY
SOT0
17
Function
Serial data output pin for UART1. This function is enabled
when UART1 enables the serial data output.
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Functions (4/7)
Pin No.
LQFP*2
QFP*1
Pin name
I/O Circuit
type*3
General I/O port. This function is enabled when the Extended
I/O serial interface disables the serial data output.
P46
23
24
25
G
SOT2
Serial data output pin for the Extended I/O serial interface.
This function is enabled when the Extended I/O serial interface enables the serial data output.
P47
General I/O port. This function is enabled when the Extended
I/O serial interface disables the clock output.
26
G
SCK2
P50
26
28
D
P51 to P54
29 to
32
D
INT4 to INT7
33
D
41 to
44
E
AN0 to AN3
Analog input pins for the 8/10-bit A/D converter. This function
is enabled when the analog input enable register specifies A/
D.
P64 to P67
General I/O port. The function is enabled when the analog
input enable register specifies a port.
43 to
46
E
AN4 to AN7
P56
45
Trigger input pin for the A/D converter. Set the corresponding
Port Direction Register (DDR) to input if this function is used.
General I/O port. This function is enabled when the analog
input enable register specifies a port.
P60 to P63
38 to
41
External interrupt request input pins for INT4 to INT7. Set the
corresponding Port Direction Register (DDR) to input if this
function is used.
General I/O port. This function is always enabled.
ADTG
36 to
39
Serial data input pin for the Extended I/O serial interface. Set
the corresponding Port Direction Register (DDR) to input if
this function is used.
General I/O port. This function is always enabled.
P55
31
Serial clock pulse I/O pin for the Extended I/O serial interface.
This function is enabled when the Extended I/O serial interface enables the Serial clock output.
General I/O port. This function is always enabled.
SIN2
27 to
30
Function
47
Analog input pins for the 8/10-bit A/D converter. This function
is enabled when the analog input enable register specifies A/
D.
General I/O port. This function is always enabled.
D
TIN0
Event input pin for the 16-bit reload timers 0. Set the
corresponding Port Direction Register to input if this function
is used.
*1: FPT-100P-M06
*2: FPT-100P-M05
*3: Refer to "1.7 I/O Circuits" for I/O circuit type.
13
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Functions (5/7)
Pin No.
LQFP*2
QFP*1
Pin name
I/O Circuit
type*3
General I/O port. This function is enabled when the 16-bit
reload timers 0 disables the output.
P57
46
48
D
Output pin for the 16-bit reload timers 0. This function is
enabled when the 16-bit reload timers 0 enables the output.
TOT0
P70 to P75
51 to
56
57, 58
53 to
58
59, 60
General I/O ports. This function is always enabled.
IN0 to IN5
Trigger input pins for input captures ICU0 to ICU5. Set the
corresponding Port Direction Register (DDR) to input if this
function is used.
P76, P77
General I/O ports. This function is enabled when the OCU
disables the waveform output.
OUT2,
OUT3
Event output pins for output compares OCU2 and OCU3.
This function is enabled when the OCU enables the waveform output.
D
D
Trigger input pins for input captures ICU6 and ICU7. Set the
corresponding Port Direction Register to input and disable
the OCU waveform output if this function is used.
IN6, IN7
General I/O ports. This function is enabled when 8/16-bit
PPG disables the waveform output.
P80 to P83
59, 62
63, 64
61 to
64
D
PPG0 to
PPG3
Output pins for 8/16-bit PPGs. This function is enabled when
8/16-bit PPG enables the waveform output.
P84, P85
General I/O ports. This function is enabled when the OCU
disables the waveform output.
65, 66
D
OUT0,
OUT1
P86
65
66
Waveform output pins for output compares OCU0 and
OCU1. This function is enabled when the OCU enables the
waveform output.
General I/O port. This function is always enabled.
TIN1
Input pin for the 16-bit reload timers 1. Set the
corresponding Port Direction Register to input if this function
is used.
P87
General I/O port. This function is enabled when the 16-bit
reload timers 0 disables the output.
67
D
68
D
TOT1
*1: FPT-100P-M06
*2: FPT-100P-M05
*3: Refer to "1.7 I/O Circuits" for I/O circuit type.
14
Function
Output pin for the 16-bit reload timers 1.This function is
enabled when the 16-bit reload timers 1 enables the output.
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Functions (6/7)
Pin No.
LQFP*2
QFP*1
Pin name
I/O Circuit
type*3
P90 to P93
67 to
70
69 to
72
General I/O port. This function is always enabled.
D
INT0 to INT3
72
73
74
73
External interrupt request input pins for INT0 to INT3. Set the
corresponding Port Direction Register to input if this function
is used.
General I/O port. This function is enabled when CAN0 disables the output.
P94
71
Function
D
TX0
TX output pin for CAN0. This function is enabled when CAN0
enables the output.
P95
General I/O port. This function is always enabled.
74
D
RX0
RX input pin for CAN0 Interface. When the CAN function is
used, output from the other functions must be stopped.
P96
General I/O port. This function is enabled when CAN1 disables the output.
75
D
TX1
TX output pin for CAN1. This function is enabled when CAN1
enables the output (only MB90540 series) .
P97
General I/O port. This function is always enabled.
76
D
RX input pin for CAN1 Interface. When the CAN function is
used, output from the other functions must be stopped (only
MB90540 series) .
General I/O port. This function is always enabled.
RX1
76
78
PA0
D
32
34
AVCC
Power
supply
Power supply pin for the A/D Converter. This power supply
must be turned on or off while a voltage higher than or equal
to AVCC is applied to VCC.
35
37
AVSS
Power
supply
Power supply pin for the A/D Converter.
33
35
AVRH
Power
supply
External reference voltage input pin for the A/D Converter.
This power supply must be turned on or off while a voltage
higher than or equal to AVRH is applied to AVCC.
34
36
AVRL
Power
supply
External reference voltage input pin for the A/D Converter.
47
48
49
50
MD0
MD1
C
Input pins for specifying the operating mode. The pins must
be directly connected to VCC or VSS.
49
51
MD2
F
Input pin for specifying the operating mode. The pin must be
directly connected to VCC or VSS.
*1: FPT-100P-M06
*2: FPT-100P-M05
*3: Refer to "1.7 I/O Circuits" for I/O circuit type.
15
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Functions (7/7)
Pin No.
Pin name
I/O Circuit
type*3
27
C
⎯
21, 82
23, 84
VCC
Power
supply
Input pin for power supply (5.0 V) .
9, 40,
79
11, 42,
81
VSS
Power
supply
Input pin for power supply (0.0 V) .
LQFP*2
QFP*1
25
*1: FPT-100P-M06
*2: FPT-100P-M05
*3: Refer to "1.7 I/O Circuits" for I/O circuit type.
16
Function
Power supply stabilization capacitor pin. It should be connected externally to an 0.1 µF ceramic capacitor.
CHAPTER 1 OVERVIEW
1.7
I/O Circuits
Table 1.7-1 shows input/output circuits.
■ I/O Circuits
Table 1.7-1 I/O Circuits (1/3)
Circuit Type
Diagram
Remarks
A
•
Oscillation feedback resistor:
Approx. 1 MΩ (High-speed oscillation)
Approx. 10 MΩ (Low-speed
oscillation)
•
•
CMOS Hysteresis input
Pull-up resistor: Approx. 50 kΩ
•
CMOS Hysteresis input
X1, X1A
Clock input
X0, X0A
Standby control signal
B
R (pull-up)
R
HYS
R
HYS
C
17
CHAPTER 1 OVERVIEW
Table 1.7-1 I/O Circuits (2/3)
Circuit Type
Diagram
Remarks
D
•
•
CMOS output
CMOS Hysteresis input
•
•
•
CMOS output
CMOS Hysteresis input
Analog input
•
•
CMOS Hysteresis input
Pull-down resistor:
Approx. 50 kΩ(except flash device
product)
•
•
•
CMOS output
CMOS Hysteresis input
TTL input (for flash device product in
flash write mode only)
P-ch
N-ch
R
HYS
E
Vcc
P-ch
N-ch
P-ch
Analog input
N-ch
HYS
R
F
R
HYS
R (pull-down)
G
Vcc
P-ch
N-ch
HYS
R
TTL
R
18
CHAPTER 1 OVERVIEW
Table 1.7-1 I/O Circuits (3/3)
Circuit Type
H
Diagram
Remarks
CNTL
Vcc
Vcc
P-ch
•
•
•
CMOS output
CMOS Hysteresis input
Programmable pull-up resistor:
Approx. 50 kΩ
•
•
•
CMOS output
CMOS Hysteresis input
TTL input (for flash device product in
flash write mode only)
Programmable pull-up resistor:
Approx. 50 kΩ
N-ch
HYS
R
I
Vcc
CNTL
Vcc
P-ch
•
N-ch
HYS
R
TTL
R
19
CHAPTER 1 OVERVIEW
1.8
Handling the Device
The notes necessary to be careful when handling devices are shown below.
■ Notes for Handling the Devices
❍ Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation assurance range of the VCC
power supply voltage, a malfunction may occur. The VCC power supply voltage must therefore be
stabilized.
As stabilization guidelines, stabilize the power supply voltage so that VCC ripple fluctuations (peak
to peak value) in the commercial frequencies (50 to 60 Hz) fall within 10% of the standard VCC
power supply voltage and the transient fluctuation rate becomes 0.1V/ms or less in instantaneous
fluctuation for power supply switching.
❍ Preventing latch-up
It should be careful not to exceed the absolute maximum ratings (Preventing latch-up).
CMOS IC chips may suffer latch-up under the following conditions:
•
A voltage higher than Vcc or lower than Vss is applied to an input or output pin.
•
A voltage higher than the rated voltage is applied between VCC and VSS.
Latch-up may increase the power supply current drastically, causing thermal damage to the
device.
For the same reason, also be careful not let the analog power-supply voltage (AVCC, AVRH) and
analog input voltage exceed the digital power-supply voltage, when power supply is tuned on or
off.
❍ Treatment of unused pins
Unused input pins left open may cause abnormal operation, or latch-up leading to permanent
damage. Unused input pins should be pulled up or pulled down through at least 2kΩ resistance.
Unused I/O pins may be left open in output state, but if such pins are in input state they should be
handled in the same way as input pins.
❍ Notes for using external clock
To use external clock, drive X0 pin only and leave X1 pin open.
Figure 1.8-1 Example of Using External Clock
MB90540/545 series
X0
Open
20
X1
CHAPTER 1 OVERVIEW
❍ Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the
same potential are connected the inside of the device to prevent such malfunctioning as latch
up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of
ground level, and observe the standard for total output current, be sure to connect the VCC and
VSS pins to the power supply and ground externally. Please refer to Figure 1.8-2.
• Connect VCC and VSS to the device from the current supply source at a low impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1µF as a bypass
capacitor between VCC and VSS in the vicinity of VCC and VSS pins of the device.
Figure 1.8-2 Handing of Power Supply Pins (VCC/VSS)
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90540/545
Vcc
Series
Vss
Vss
Vcc
❍ Pull-up/down resistors
The MB90540/545 Series does not support internal pull-up/down resistors option (except Port0 to
Port3:pull-up resistors). Use external components where needed.
❍ Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to
provide bypass capacitors via the shortest distances from X0, X1 pins, crystal oscillator (or
ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation
circuits do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins
with a ground area for stabilizing the operation. Please ask the crystal maker to evaluate the
oscillational characteristics of the crystal and this device.
❍ Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs
(AN0 to AN7) after turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this
case, make sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and
digital power supplies simultaneously is acceptable).
21
CHAPTER 1 OVERVIEW
❍ Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter and D/A converter to AVCC = VCC, AVSS = AVRH = VSS.
❍ N.C. Pin
The N.C. (internally connected) pin must be opened for use.
❍ Notes on Energization
To prevent the built-in down-convention circuit from malfunctioning, set the voltage rise time
during energization at 50 µs or more (0.2 V to 2.7 V).
❍ Use of the subclock
Use the single clock (system) parts when the subclock is not used. In that case, pull-down the pin
X0A and leave the pin X1A open. When using the two clock system parts, a 32 kHz or less
oscillator has to be connected to the X0A and X1A pins.
❍ Indeterminate outputs from ports 0 and 1 (MB90F543/F549/V540/V540G only)
During oscillation setting time of step-down circuit (during a power-on reset) after the power is
turned on, the outputs from ports 0 and 1 become following state.
•
If RST pin is "H", the outputs become indeterminate.
•
If RST pin is "L", the outputs become high-impedance.
Pay attention to the port output timing shown as follows:
Figure 1.8-3 Timing Chart of Port 0/1 Indeterminate (RST Pin is "H")
Oscillation setting time *2
RST pin is "H"
Power-on reset *1
Vcc (Power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal
Period of indeterminated
*1: Oscillation setting time for step-down circuit: Period of "clock frequency × 217 "
(Clock frequency of 16 MHz: 8.19 ms)
*2: Oscillation setting time: Period of "clock frequency × 218 " (Clock frequency of 16 MHz: 16.38ms)
22
CHAPTER 1 OVERVIEW
Figure 1.8-4 Timing Chart of Port 0/1 to be High-impedance (RST Pin is "L")
Oscillation setting time *2
RST pin is "L"
Power-on reset *1
Vcc (Power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal
High-impedance
*1: Oscillation setting time for step-down circuit: Period of "clock frequency 217 "
(Clock frequency of 16 MHz: 8.19 ms)
*2: Oscillation setting time: Period of "clock frequency 218 " (Clock frequency of 16 MHz: 16.38ms)
❍ Initialization
In the device, there are built-in registers which are initialized only by a power-on reset. To
initialize these registers, please turn on the power again.
❍ Directions of "DIV A, Ri" and "DIVW A, RWi" instructions
In the Signed multiplication and division instructions ("DIV A, Ri" and "DIVW A, RWi"), the value
of the corresponding bank register (DTB, ADB, USB, SSB) is set in "00H".
If the values of the corresponding bank registers (DTB,ADB,USB,SSB) are set to other than
"00H", the remainder by the execution result of the instruction is not stored in the register of the
instruction operand.
Please refer to "2.11 Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions" for details.
❍ Using REALOS
The use of EI2OS is not possible with the REALOS real time operating system.
❍ Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the selfoscillating circuit even when there is no external oscillator or external clock input is stopped.
Performance of this operation, however, cannot be guaranteed.
23
CHAPTER 1 OVERVIEW
24
CHAPTER 2
CPU
This chapter explains the CPU.
2.1 Outline of CPU
2.2 Memory Space
2.3 Memory Space Map
2.4 Linear Addressing
2.5 Bank Addressing
2.6 Multi-byte Data in Memory Space
2.7 Registers
2.8 Register Bank
2.9 Prefix Codes
2.10 Interrupt Disable Instructions
2.11 Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions
25
CHAPTER 2 CPU
2.1
Outline of CPU
The F2MC-16LX CPU core is a 16-bit CPU designed for applications that require highspeed real-time processing, such as home-use or vehicle-mounted electronic
appliances. The F2MC-16LX instruction set is designed for controller applications, and
is capable of high-speed, highly efficient control processing.
■ Outline of CPU
In addition to 16-bit data, the F2MC-16LX CPU core can process 32-bit data by using an internal
32-bit accumulator (32-bit data can be processed by some instructions). Memory space of up to
16 Mbytes (expandable) can be accessed by either the linear or bank method. The instruction
set, based on the F2MC-8L A-T architecture, has been made richer by adding instructions that
are compatible with high-level languages, expanding addressing modes, improving the
multiplication and division instructions, and enhancing bit processing.
The features of the F2MC-16LX CPU are explained below.
❍ Minimum instruction execution time
62.5 ns (at 4-MHz oscillation, 4 times clock multiplication)
❍ Maximum memory space
16 Mbytes, accessed in linear or bank mode
❍ Instruction set optimized for controller applications
•
Rich data types: Bit, byte, word, long word
•
Extended addressing modes: 23 types
•
High-precision operation (32-bit length) based on 32-bit accumulator
❍ Powerful interrupt functions
Eight priority levels (programmable)
❍ CPU-independent automatic transfer
Up to 16 channels of the extended intelligent I/O service
❍ Instruction set compatible with high-level language (C)/multitasking
System stack pointer/instruction set symmetry/barrel-shift instructions
❍ Improved execution speed
4-byte queue
26
CHAPTER 2 CPU
2.2
Memory Space
An F2MC-16LX CPU has a 16M-byte memory space. All data items, programs, and inputoutputs managed by F2MC-16LX CPU are located in this 16M-byte memory space. The
CPU can access resources by indicating their addresses using a 24-bit address bus.
■ Outline of CPU Memory Space
Figure 2.2-1 shows a sample relationship between the F2MC-16LX system and memory map.
Figure 2.2-1 Sample Relationship between F2MC-16LX System and Memory Map
FFFFFF H
Program
FF8000H
Data
810000H
Interrupt
800000H
F2MC-16LX
CPU
Program area
Data area
0000C0H
[Device]
Peripheral
circuits
0000B0 H
Generalpurpose ports
000020H
Interrupt controller
Peripheral circuits
General-purpose ports
000000H
■ Address Generation Types
The F2MC-16LX has the following 2 addressing:
❍ Linear addressing
An entire 24-bit address is specified by an instruction.
❍ Bank addressing
The eight high-order bits of an address are specified by an appropriate bank register, and the
remaining 16 low-order bits are specified by an instruction.
27
CHAPTER 2 CPU
2.3
Memory Space Map
The memory space of the MB90540/545 Series is shown in Figure 2.3-1.
■ Memory Space Map
The high-order portion of bank "00" gives the image of the FF bank ROM to make the small
model of the C compiler effective. Since the low-order 16 bits are the same, the table in ROM can
be referenced without using the far specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank
"00".
The image between FF4000H and FFFFFFH is visible in bank "00", while the image between
FF0000H and FF3FFFH is visible only in bank FF.
Figure 2.3-1 Memory Space Map
MB90V540/V540G/
F546G(S)
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
ROM (FF bank)
ROM (FE bank)
FF0000H
FEFFFFH
FE0000H
ROM (FF bank)
ROM (FE bank)
FF0000H
FEFFFFH
FE0000H
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
External access
memory
External access
memory
ROM (FC bank)
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
004000H
003FFFH
ROM (Image of
FF bank)
00FFFFH
004000H
003FFFH
External access
memory
0020FFH
001FF5H ROM correction
001FF0H
003900H
002000H
000000H
External access memory
Peripheral
*: 002000H for MB90F549
28
External access
memory
0018FFH
RAM 8 Kbytes
000100H
0000BFH
ROM (Image of
FF bank)
00FFFFH
004000H
003FFFH
Peripheral
Peripheral
003900H
FFFFFFH
ROM (FF bank)
FF0000H
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
External access
memory
ROM (FC bank)
External access
memory
External access
memory
00FFFFH
MB90547G(S)
MB90F549/549G(S)/
F549G(S)
FFFFFFH
FFFFFFH
FFFFFFH
FFFFFFH
MB90F548G(S)/
F548GL(S)/548G(S)
MB90543G(S)/F543/
F543G(S)
Peripheral
003900H
002000H
000000H
External access
memory
External access memory
Peripheral
00FFFFH ROM (Image of
FF bank)
004000H
003FFFH
Peripheral
003900H
External access
memory
002100H *
RAM 6 Kbytes
RAM 4 Kbytes
000100H
0000BFH
000000H
00FFFFH ROM (Image of
FF bank)
004000H
003FFFH
Peripheral
003900H
External access
memory
002000H
0018FFH
0010FFH
RAM 6 Kbytes
000100H
0000BFH
ROM (Image of
FF bank)
External access memory
Peripheral
000100H
0000BFH
000000H
External access memory
Peripheral
0008FFH
000100H
0000BFH
000000H
RAM 2 Kbytes
External access memory
Peripheral
CHAPTER 2 CPU
2.4
Linear Addressing
There are 2 types of linear addressing as follows:
• 24-bit operand specification:
Directly specifies a 24-bit address using
operands.
• 32-bit register indirect specification:Indirectly quote the 24 low-order bits of a 32-bit
general-purpose register value as the address.
■ 24-bit Operand Specification
Figure 2.4-1 shows an example of 24-bit operand specification. Figure 2.4-2 shows an example of
32-bit register indirect specification.
Figure 2.4-1 Example of Linear Method (24-bit Register Operand Specification)
JMPP 123456H
Old program counter
+ program bank
17
17452D H
452D
JMPP 123456 H
123456 H
New program counter
+ program bank
12
Next instruction
3456
■ 32-bit Register Indirect Specification
Figure 2.4-2 Example of Linear Method (32-bit Register Indirect Specification)
MOV A, @RL1+7
Old AL
090700 H
XXXX
3A
+7
RL1
240906F9
(The high-order eight bits are ignored.)
New AL
003A
29
CHAPTER 2 CPU
2.5
Bank Addressing
In the bank method, the 16M-byte space is divided into 256 for 64K-byte banks. The
following five bank registers are used to specify the banks corresponding to each
space:
• Program counter bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional data bank register (ADB)
■ Bank Addressing Types
❍ Program counter bank register (PCB)
The 64K-byte bank specified by the PCB is called a program (PC) space. The PC space contains
instruction codes, vector tables, and immediate value data, for example.
❍ Data bank register (DTB)
The 64K-byte bank specified by the DTB is called a data (DT) space. The DT space contains
readable/writable data, and control/data registers for internal and external resources.
❍ User stack bank register (USB)/system stack bank register (SSB)
The 64K-byte bank specified by the USB or SSB is called a stack (SP) space. The SP space is
accessed when a stack access occurs during a push/pop instruction or interrupt register saving.
The S flag in the condition code register determines the stack space to be accessed.
❍ Additional data bank register (ADB)
The 64K-byte bank specified by the ADB is called an additional (AD) space. The AD space, for
example, contains data that cannot fit into the DT space.
Table 2.5-1 lists the default spaces used in each addressing mode, which are pre-determined to
improve instruction coding efficiency. To use a non-default space for an addressing mode, specify
a prefix code corresponding to a bank before the instruction. This enables access to the bank
space corresponding to the specified prefix code.
After reset, the DTB, USB, SSB, and ADB are initialized to 00H. The PCB is initialized to a value
specified by the reset vector. After reset, the DT, SP, and AD spaces are allocated in bank 00H
(000000H to 00FFFFH), and the PC space is allocated in the bank specified by the reset vector.
30
CHAPTER 2 CPU
Table 2.5-1 Default Space
Default space
Program space
Addressing mode
PC indirect, program access, branch group
Data space
Addressing mode using @RW0, @RW1, @RW4, or @RW5, @A, addr16, and dir
Stack space
Addressing mode using PUSHW, POPW, @RW3, or @RW7
Additional space
Addressing mode using @RW2 or @RW6
Figure 2.5-1 is an example of a memory space divided into register banks.
Figure 2.5-1 Physical Addresses of Each Space
FFFFFF H
Program space
FF0000 H
FF H
:
PCB (Program counter bank register)
B3 H
: ADB (Additional data bank register)
92 H
: USB (User stack bank register)
68 H
: DTB (Data bank register)
4B H
: SSB (System stack bank register)
B3FFFF H
Additional space
Physical address
B30000 H
92FFFF H
User stack space
920000 H
68FFFF H
680000 H
Data space
4BFFFF H
System stack space
4B0000 H
000000 H
31
CHAPTER 2 CPU
2.6
Multi-byte Data in Memory Space
Data is written to memory from the low-order addresses. Therefore, for a 32-bit data
item, the low-order 16 bits are transferred before the high-order 16 bits.
If a reset signal is input immediately after the low-order bits are written, the high-order
bits might not be written.
■ Multi-byte Data Allocation in Memory Space
Figure 2.6-1 is a diagram of multi-byte data configuration in memory. The low-order 8 bits of a
data item are stored at address n, then address n+1, address n+2, address n+3, etc.
Figure 2.6-1 Sample Allocation of Multi-byte Data in Memory
MSB
H
LSB
01010101
11001100
11111111
00010100
01010101
11001100
11111111
Address n
00010100
L
■ Accessing Multi-byte Data
Fundamentally, accesses are made within a bank. For an instruction accessing a multi-byte data
item, address FFFFH is followed by address 0000H of the same bank. Figure 2.6-2 is an example
of an instruction accessing multi-byte data.
Figure 2.6-2 Execution of MOVW A, 080FFFFH
H
AL before execution
80FFFF H
??
??
23 H
01H
01H
·
·
·
23 H
800000 H
L
32
AL after execution
CHAPTER 2 CPU
2.7
Registers
The F2MC-16LX registers are largely classified into two types: special registers in the
CPU and general-purpose registers in memory. The special registers are dedicated
internal hardware of the CPU, and they have specific use defined by the CPU
architecture. The general-purpose registers share the CPU address space with RAM.
The general-purpose registers are the same as the special registers in that they can be
accessed without using an address. The applications of the general-purpose registers
can be specified by the user however, as is ordinary memory space.
■ Special Registers
The F2MC-16LX CPU core has the following 11 special registers:
•
Accumulator (A=AH:AL):
Two 16-bit accumulators
(Can be used as a total 32-bit accumulator.)
•
User stack pointer (USP):
16-bit pointer indicating the user stack area
•
System stack pointer (SSP):
16-bit pointer indicating the system stack area
•
Processor status (PS):
16-bit register indicating the system status
•
Program counter (PC):
16-bit register holding the address of the program
•
Program counter bank register (PCB): 8-bit register indicating the PC space
•
Data bank register (DTB):
8-bit register indicating the DT space
•
User stack bank register (USB):
8-bit register indicating the user stack space
•
System stack bank register (SSB):
8-bit register indicating the system stack space
•
Additional data bank register (ADB):
8-bit register indicating the A/D space
•
Direct page register (DPR):
8-bit register indicating a direct page
Figure 2.7-1 shows the bit configuration of the special registers.
33
CHAPTER 2 CPU
Figure 2.7-1 Special Registers
AL
AH
Accumulator
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
DPR
Direct page register
PCB
Program counter bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8 bit
16 bit
32 bit
■ General-purpose Registers
The F2MC-16LX general-purpose registers are located from addresses 000180H to 00037FH
(maximum configuration) of main storage. The register bank pointer (RP) indicates which of the
above addresses are currently being used as a register bank. Each bank has the following three
types of registers. These registers are mutually dependent as described in Figure 2.7-2.
•
R0 to R7: 8-bit general-purpose register
•
RW0 to RW7: 16-bit general-purpose register
•
RL0 to RL3: 32-bit general-purpose register
Figure 2.7-2 General-purpose Registers
MSBLSB
16 bit
000180H + RP × 10H
RW0
Low-order
RL0
First address of
general-purpose register
RW1
RW2
RL1
RW3
R1
R0
RW4
R3
R2
RW5
R5
R4
RW6
R7
R6
RW7
RL2
RL3
High-order
The relationship between the high-order and low-order bytes of a byte or word register is
expressed as follows:
RW (i+4) = R (i×2+1) × 256+R (i×2) [i=0 to 3]
The relationship between the high-order and low-order bytes of RLi and RW can be expressed as
follows:
RL (i) = RW (i×2+1) × 65536+RW (i×2) [i=0 to 3]
34
CHAPTER 2 CPU
2.7.1
Accumulator (A)
The accumulator (A) register consists of two 16-bit arithmetic operation registers (AH
and AL), and is used as a temporary storage for operation results and transfer data.
■ Accumulator (A)
In 32-bit data processing, AH and AL are used together. Only AL is used for word processing in
16-bit data processing mode or for byte processing in 8-bit data processing mode (see Figure
2.7-3 and Figure 2.7-4). The data in the A register can be operated upon with data in memory or
with registers (Ri, RWi, or RLi). As with the F2MC-8L, when a word or shorter data item is
transferred to AL, the previous data item in AL is automatically transferred to AH (data save
function). The data save function and the operations between AL and AH help to improve
processing efficiency.
When a byte or shorter data item is transferred to AL, the data is sign-extended or zero-extended
and stored as a 16-bit data item in AL. The data in AL can be handled either as word or byte long.
When a byte-processing arithmetic operation instruction is executed on AL, the high-order eight
bits of AL before operation are ignored. The high-order eight bits of the operation result all
become zeroes.
The A register is not initialized by a reset. The A register holds an undefined value immediately
after a reset.
Figure 2.7-3 Example of 32-bit Data Transfer
MOVL A,@RW1+6
(Instruction that performs a long-word-length read using the result of
RW1 + an 8-bit offset as the address and stores the read value in the A register)
Memory space
MSB
Before execution
XXXXH
XXXXH
8F74H
A61540H
8FH
74H
A6153EH
2BH
52H
15H
38H
A6H
DTB
After execution
LSB
+6
2B52H
RW1
AL
AH
Figure 2.7-4 Example of AL-AH Transfer
(Instruction that performs a word-length read using the result of RW1 + an
8-bit offset as the address and stores the read value in the A register)
MOVW A,@RW1+6
MSB
Before execution
XXXXH
1234H
A6H
DTB
Memory space
LSB
A61540H
8FH
74H
A6153EH
2BH
52H
15H
38H
+6
After execution
1234H
2B52H
AH
AL
RW1
35
CHAPTER 2 CPU
2.7.2
User Stack Pointer (USP) and System Stack Pointer (SSP)
USP and SSP are 16-bit registers that indicate the memory addresses for saving and
restoring data when a push/pop instruction or subroutine is executed.
■ User Stack Pointer (USP) and System Stack Pointer (SSP)
The USP and SSP registers are used by stack instructions. The USP register is enabled when
the S flag in the processor status register is "0," and the SSP register is enabled when the S flag
is "1" (see Figure 2.7-5). Since the S flag is set when an interrupt is accepted, register values are
always saved in the memory area indicated by SSP during interrupt processing. SSP is used for
stack processing in an interrupt routine, while USP is used for stack processing outside an
interrupt routine. If the stack space is not divided, use only the SSP.
During stack processing, the high-order 8 bits of an address are indicated by SSB (for SSP) or
USB (for USP). USP and SSP are not initialized by a reset. Instead, they hold undefined values.
Figure 2.7-5 Stack Operation Instruction and Stack Pointer (PUSHW A when the S Flag is "0")
MSBLSB
Before execution
AL
S flag
After execution
AL
A624H
USB
C6H
USP
F328H
0
SSB
56H
SSP
1234H
A624H
USB
C6H
USP
F326H
0
SSB
56H
SSP
1234H
C6F326H
XXH
XXH
User stack is used because
the S flag is "0".
C6F326H
A6H
24H
Figure 2.7-6 Stack Operation Instruction and Stack Pointer (PUSHW A when the S Flag is "1")
Before execution
After execution
AL
AL
A624H
USB
C6H
USP
F328H
1
SSB
56H
SSP
1234H
A624H
USB
C6H
USP
F328H
1
SSB
56H
SSP
1232H
561232
XXH
XXH
561232
A6H
24H
System stack is used because
the S flag is "1".
Note:
Specify an even-numbered address in the stack pointer whenever possible.
36
CHAPTER 2 CPU
2.7.3
Processor Status (PS)
The PS register consists of the bits controlling the CPU Operation and the bits
indicating the CPU status.
■ Processor Status (PS)
As shown in Figure 2.7-7, the PS register consists of a register bank pointer (RP) and an interrupt
level mask register (ILM). The RP indicates the start address of a register bank. The low-order
byte of the PS register is a condition code register (CCR), containing the flags to be set or reset
depending on the results of instruction execution or interrupt occurrences.
Figure 2.7-7 Processor Status (PS) Structure
15
13 12
ILM
000
PS
Initial value →
8 7
0
RP
00000
CCR
-01XXXXX
X: Undefined
■ Condition Code Register (CCR)
Figure 2.7-8 is a diagram of condition code register (CCR) configuration.
Figure 2.7-8 Condition Code Register (CCR) Configuration
Initial value →
7
-
6
I
0
5
S
1
3
T
X
4
N
X
2
Z
X
1
V
X
0
C
X
: CCR
X: Undefined
❍ I: Interrupt enable flag:
Interrupts other than software interrupts are enabled when the I flag is "1" and are masked when
the I flag is "0". The I flag is cleared by a reset.
❍ S: Stack flag:
When the S flag is "0", USP is enabled as the stack manipulation pointer.
When the S flag is "1", SSP is enabled as the stack manipulation pointer.
The S flag is set by an interrupt reception or a reset.
❍ T: Sticky bit flag:
"1" is set in the T flag when there is at least one "1" in the data shifted out from the carry after
execution of a logical right/arithmetic right shift instruction. Otherwise, "0" is set in the T flag. In
addition, "0" is set in the T flag when the shift amount is "0".
❍ N: Negative flag:
The N flag is set when the MSB of the operation result is "1," and is otherwise cleared.
37
CHAPTER 2 CPU
❍ Z: Zero flag:
The Z flag is set when the operation result is all zeroes, and is otherwise cleared.
❍ V: Overflow flag:
The V flag is set when an overflow of a signed value occurs as a result of operation execution
and is otherwise cleared.
❍ C: Carry flag:
The C flag is set when a carry-up or carry-down from the MSB occurs as a result of operation
execution, and is otherwise cleared.
■ Register Bank Pointer (RP)
The RP register indicates the relationship between the general-purpose registers of the F2MC16LX and the internal RAM addresses. Specifically, the RP register indicates the first memory
address of the currently used register bank in the following conversion expression: [00180H +
(RP)×10H] (see Figure 2.7-9). The RP register consists of five bits, and can take a value between
00H and 1FH. Register banks can be allocated at addresses from 000180H to 00037FH in
memory.
Even within that range, however, the register banks cannot be used as general-purpose registers
if the banks are not in internal RAM. The RP register is initialized to all zeroes by a reset. An
instruction may transfer an eight-bit immediate value to the RP register; however, only the loworder five bits of that data are used.
Figure 2.7-9 is a diagram of register bank pointer (RP).
Figure 2.7-9 Register Bank Pointer (RP)
Initial value→
B4
0
B3
0
B2
0
B1
0
B0
0
: RP
■ Interrupt Level Mask Register (ILM)
The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt
request is accepted only when the level of the interrupt is higher than that indicated by these
three bits. Level 0 is the highest priority interrupt, and level 7 is the lowest priority interrupt (see
Table 2.7-1). Therefore, for an interrupt to be accepted, its level value must be smaller than the
current ILM value. When an interrupt is accepted, the level value of that interrupt is set in ILM.
Thus, an interrupt of the same or lower level cannot be accepted subsequently. ILM is initialized
to all zeroes by a reset. An instruction may transfer an eight-bit immediate value to the ILM
register, but only the low-order three bits of that data are used.
Figure 2.7-10 is a diagram of interrupt level mask register (ILM).
Figure 2.7-10 Interrupt Level Register (ILM)
Initial value→
38
ILM2
0
ILM1
0
ILM0
0
: ILM
CHAPTER 2 CPU
Table 2.7-1 Levels Indicated by the Interrupt Level Mask (ILM) Register
ILM2
ILM1
ILM0
Level value
Acceptable interrupt level
0
0
0
0
Interrupt disabled
0
0
1
1
"0" only
0
1
0
2
Level value smaller than "1"
0
1
1
3
Level value smaller than "2"
1
0
0
4
Level value smaller than "3"
1
0
1
5
Level value smaller than "4"
1
1
0
6
Level value smaller than "5"
1
1
1
7
Level value smaller than "6"
39
CHAPTER 2 CPU
2.7.4
Program Counter (PC)
The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory
address of an instruction code to be executed by the CPU. The high-order eight bits of
the address are indicated by the PCB. The PC register is updated by a conditional
branch instruction, subroutine call instruction, interrupt, or reset.
The PC register can also be used as a base pointer for operand access.
■ Program Counter (PC)
Figure 2.7-11 shows the program counter.
Figure 2.7-11 Program Counter
PCB
FEH
PC
ABCDH
Next instruction to be executed
FEABCDH
40
CHAPTER 2 CPU
2.8
Register Bank
A register bank consists of eight words. The register bank can be used as the following
general-purpose registers for arithmetic operations: byte registers R0 to R7, word
registers RW0 to RW7, and long word registers RL0 to RL3. In addition, the register
bank can be used as instruction pointers.
■ Register Bank
Table 2.8-1 lists the functions of the registers. Table 2.8-2 indicates the relationship between the
registers.
In the same manner as for an ordinary RAM area, the register bank values are not initialized by a
reset. The status before a reset is maintained. When the power is turned on, however, the
register bank will have an undefined value.
Table 2.8-1 Each Register Functions
R0 to R7
RW0 to RW7
RL0 to RL3
Used as operands of instructions.
Note: R0 is also used as a counter for barrel shift or normalization
instructions.
Used as pointers.
Used as operands of instructions.
Note: RW0 is used as a counter for string instructions.
Used as long pointers.
Used as operands of instructions.
41
CHAPTER 2 CPU
Table 2.8-2 Relationship between Each Registers
RW0
RL0
RW1
RW2
RL1
RW3
R0
RW4
R1
RL2
R2
RW5
R3
R4
RW6
R5
RL3
R6
RW7
R7
❍ Direct page register (DPR) <Initial value: 01H>
DPR specifies addr8 to addr15 of the instruction operands in direct addressing mode as shown in
Figure 2.8-1. DPR is eight bits long, and is initialized to 01H by a reset. DPR can be read or
written to by an instruction.
Figure 2.8-1 Generating a Physical Address in Direct Addressing Mode
DTB register
DPR register
Direct address during instruction
αααααααα
ββββββββ
γγγγγγγγ
MSB
24-bit physical
address
LSB
ααααααααββββββββγγγγγγγγ
❍ Program counter bank register (PCB) <Initial value: Value in reset vector>
❍ Data bank register (DTB) <Initial value: 00H>
❍ User stack bank register (USB) <Initial value: 00H>
❍ System stack bank register (SSB) <Initial value: 00H>
42
CHAPTER 2 CPU
❍ Additional data bank register (ADB) <Initial value: 00H>
Each bank register indicates the memory bank where the PC, DT, SP (user), SP (system), or AD
space is allocated. All bank registers are one byte long. PCB is initialized to a reset vector value.
Bank registers other than PCB can be read or written to. PCB can be read but cannot be written
to.
PCB is updated when the JMPP, CALLP, RETP, RETI, or RETF instruction branching to the
entire 16-Mbyte space is executed or when an interrupt occurs. For operation of each register,
see Section "2.2 Memory Space".
43
CHAPTER 2 CPU
2.9
Prefix Codes
Placing a prefix code before an instruction partially changes the operation of the
instruction. Three types of prefix codes can be used: bank select prefix, common
register bank prefix, and flag change suppressive prefix.
■ Bank Select Prefix
The memory space used for accessing data is determined for each addressing mode.
When a bank select prefix is placed before an instruction, the memory space used for accessing
data by that instruction can be selected freely regardless of the addressing mode.
Table 2.9-1 lists the bank select prefixes and the corresponding memory spaces.
Table 2.9-1 Bank Select Prefix
Bank select prefix
Selected space
PCB
PC space
DTB
Data space
ADB
AD space
SPB
Either the SSP or USP space is used according to the stack flag status.
Use the following instructions with care:
❍ String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW)
The bank register specified by an operand is used regardless of existence of the prefix.
❍ Stack manipulation instructions (PUSHW, POPW)
SSB or USB is used according to the S flag regardless of existence of the prefix.
❍ I/O access instructions
MOV A, io / MOV io, A /MOVX A, io / MOVW A, io /MOVW io, A / MOV io, #imm8
MOVW io, #imm16 / MOVB A, io:bp / MOVB A io:bp, A /SETB io:bp / CLRB io:bp
BBC io:bp, rel / BBS io:bp, rel/WBTC, WBTS
The I/O space of the bank is used regardless of existence of the prefix.
❍ Flag change instructions (AND CCR,#imm8/ OR CCR,#imm8)
The instruction is executed normally, but the prefix affects the next instruction.
❍ POPW PS
SSB or USB is used according to the S flag regardless of existence of the prefix. The prefix
affects the next instruction.
44
CHAPTER 2 CPU
❍ MOV ILM,#imm8
The instruction is executed normally, but existence of the prefix affects the next instruction.
❍ RETI
SSB is used regardless of existence of the prefix.
■ Common Register Bank Prefix (CMR)
To simplify data exchange between multiple tasks, the same register bank must be accessed
relatively easily regardless of the RP value. When CMR is placed before an instruction that
accesses a register bank, that instruction changes the common bank (the register bank selected
when RP=0) at addresses from 000180H to 00018FH regardless of the current RP value. When
using the common register bank prefix (CMR), use the following instructions carefully:
❍ String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW)
If an interrupt request occurs during execution of a string instruction with a prefix code, the prefix
code becomes invalid when the string instruction is resumed after the interrupt is processed.
Thus, the string instruction is executed falsely after the interrupt is processed. Do not add any
prefix of the above string instructions with CMR.
❍ Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS)
The instruction is executed normally, but the prefix affects the next instruction.
❍ MOV ILM,#imm8
The instruction is executed normally, but the prefix affects the next instruction.
■ Flag Change Suppressive Prefix (NCC)
To suppress flag changes, use the flag change suppressive prefix code (NCC). Placing NCC
before an instruction suppressive flag changes associated with that instruction. When using the
flag change suppressive prefix (NCC), use the following instructions carefully:
❍ String instructions (MOVS/MOVSW/SCEQ/SCWEQ/FILS/FILSW)
If an interrupt request occurs during execution of a string instruction with a prefix code, the prefix
code becomes invalid when the string instruction is resumed after the interrupt is processed.
Thus, the string instruction is executed incorrectly after the interrupt is processed. Do not add any
prefix the above string instructions with NCC.
❍ Flag change instructions (AND CCR,#imm8/OR CCR,#imm8/POPW PS)
The instruction is executed normally, but the prefix affects the next instruction.
❍ Interrupt instructions (INT #vct8/INT9/INT addr16/INTP addr24/RETI)
CCR changes according to the instruction specifications regardless of the existence of the prefix.
❍ JCTX @A
CCR changes according to the instruction specifications regardless of the existence of the prefix.
❍ MOV ILM,#imm8
The instruction is executed normally, but the prefix affects the next instruction.
45
CHAPTER 2 CPU
2.10 Interrupt Disable Instructions
Interrupt requests are not sampled for the following ten instructions:
• MOV ILM,#imm8
• PCB
• SPB
• OR CCR,#imm8
• AND CCR,#imm8
• ADB
• CMR
• POPW PS
•
NCC
• DTB
■ Interrupt Disable Instructions
If a valid hardware interrupt request occurs during execution of any of the above instructions, the
interrupt can be processed only when an instruction other than the above is executed. For details,
see Figure 2.10-1.
Figure 2.10-1 Interrupt Disable Instruction
Interrupt disable instruction
(a)
(a) Ordinary
instruction
Interrupt request generated
Interrupt acceptance
■ Restrictions on Interrupt Disable Instructions and Prefix Instructions
When a prefix code is placed before an interrupt disable instruction, the prefix code affects the
first instruction after the code other than the interrupt disable instruction.
Figure 2.10-2 Interrupt Disable Instructions and Prefix Codes
Interrupt disable instruction
MOV A, FFH
NCC
ADD A,01H
MOV ILM,#imm8
CCR:XXX10XXB
CCR:XXX10XXB
CCR does not change with NCC.
■ Consecutive Prefix Codes
When competitive prefix codes are placed consecutively, the latter becomes valid.
In the figure below, competitive prefix codes are PCB, ADB, DTB, and SPB.
Figure 2.10-3 Consecutive Prefix Codes
Prefix code
ADB
DTB
PCB
A D D A , 0 1H
PCB is valid as the prefix code
46
CHAPTER 2 CPU
2.11 Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions
Set the value of the corresponding bank register to "00H" when using "DIV A, Ri" and
"DIVW A, RWi" instructions.
■ Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions
Table 2.11-1 Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions
Instruction
Name of the bank
register affected when
executing the
instructions shown in
the table
Address at which the remainder is stored
DIV A, R0
(DTB: Higher 8-bit) + (0180H + RP x 10H + 8H: Lower 16-bit)
DIV A, R1
(DTB: Higher 8-bit) + (0180H + RP x 10H + 9H: Lower 16-bit)
DIV A, R4
(DTB: Higher 8-bit) + (0180H + RP x 10H + CH: Lower 16-bit)
DIV A, R5
DTB
(DTB: Higher 8-bit) + (0180H + RP x 10H + DH: Lower 16-bit)
DIVW A, RW0
(DTB: Higher 8-bit) + (0180H + RP x 10H + 0H: Lower 16-bit)
DIVW A, RW1
(DTB: Higher 8-bit) + (0180H + RP x 10H + 2H: Lower 16-bit)
DIVW A, RW4
(DTB: Higher 8-bit) + (0180H + RP x 10H + 8H: Lower 16-bit)
DIVW A, RW5
(DTB: Higher 8-bit) + (0180H + RP x 10H + AH: Lower 16-bit)
DIV A, R2
(ADB: Higher 8-bit) + (0180H + RP x 10H + AH: Lower 16-bit)
DIV A, R6
ADB
(ADB: Higher 8-bit) + (0180H + RP x 10H + EH: Lower 16-bit)
DIVW A, RW2
(ADB: Higher 8-bit) + (0180H + RP x 10H + 4H: Lower 16-bit)
DIVW A, RW6
(ADB: Higher 8-bit) + (0180H + RP x 10H +EH: Lower 16-bit)
DIV A, R3
(USB *2: Higher 8-bit) + (0180H + RP x 10H + BH: Lower 16-bit)
DIV A, R7
DIVW A, RW3
DIVW A, RW7
USB
SSB *1
(USB *2: Higher 8-bit) + (0180H + RP x 10H + FH: Lower 16-bit)
(USB *2: Higher 8-bit) + (0180H + RP x 10H + 6H: Lower 16-bit)
(USB *2: Higher 8-bit) + (0180H + RP x 10H + EH: Lower 16-bit)
*1: Depending on the S bit of the CCR register
*2: When the S bit of the CCR register is "0"
If the value of corresponding bank registers (DTB, ADB, USB, SSB) is set to "00H", the remainder
of division results are stored in the register of the instruction operand. If the value is set to a value
other than "00H", the higher 8-bit address is specified by the bank register corresponding to the
register of the instruction operand. The lower 16-bit address then becomes the same address as
that of the register of the instruction operand at which the remainder is stored.
47
CHAPTER 2 CPU
[Example]
If "DIV A, R0" instruction is executed in the case of DTB=053H/RP=03H, the address of R0 is
as follows: 0180H+RP (03H) x 10H+08H (address equivalent to R0) = 0001B8H
The bank register to be specified by "DIV A, R0" is DTB, so the address to which bankspecified 053H is added, that is 05301B8H, is the address at which the remainder of a result is
stored.
Reference:
For an explanation of the bank register, Ri register, and RWi register, see Section "2.7 Registers".
■ Evasion of Notes
In order to evade notes of the "DIV A, Ri" and "DIVW A, RWi" instructions during program
development, the compiler modifies the program so that the respective instructions are not
generated. The assembler then replaces these instructions by functions equivalent to the
instruction strings.
Use the following compiler and assembler as for MB90540/545 series.
48
•
Compiler
: Version V02L06 of cc907 or later, and version V30L02 of fcc907s or later
•
Assembler : Version V03L04 of asm907a or later, and version V30L04 (Rev.30004) of
fasm907s or later
CHAPTER 3
INTERRUPTS
This chapter explains the interrupt functions and operations.
3.1 Outline of Interrupts
3.2 Interrupt Sources
3.3 Interrupt Vector
3.4 Hardware Interrupts
3.5 Software Interrupts
3.6 Extended Intelligent I/O Service (EI2OS)
3.7 Exception Due to Execution of an Undefined Instruction
49
CHAPTER 3 INTERRUPTS
3.1
Outline of Interrupts
The F2MC-16LX has interrupt functions that, when an event occurs, terminate the
processing being currently executed and transfer control to a separately defined
program.
■ Outline of Interrupts
There are 4 types of interrupt functions:
•
Hardware interrupt : Interrupt processing due to an internal resource event
•
Software interrupt : Interrupt processing due to an instruction causing a software event
•
Extended intelligent I/O service (EI2OS)
: Transfer processing due to an internal resource event
•
Exception
: Termination due to an operation exception
This chapter explains these 4 types of interrupt.
50
CHAPTER 3 INTERRUPTS
3.2
Interrupt Sources
Table 3.2-1 lists the interrupt sources, interrupt vectors, and interrupt control registers
in the MB90540/545 series.
■ Interrupt Sources
Table 3.2-1 Interrupt Sources, Interrupt Vectors, and Interrupt Control Registers (1/2)
Interrupt source
EI2OS clear
Interrupt vector
Interrupt control register
Number
Address
Number
Address
Reset
X
#08
FFFFDCH
-
-
INT9 instruction
X
#09
FFFFD8H
-
-
Exception
X
#10
FFFFD4H
-
-
CAN 0 RX
X
#11
FFFFD0H
ICR00
CAN 0 TX/NS
X
#12
FFFFCCH
0000B0H
CAN 1 RX
X
#13
FFFFC8H
ICR01
CAN 1 TX/NS
X
#14
FFFFC4H
0000B1H
External interrupt INT0/INT1
O
#15
FFFFC0H
ICR02
Timebase timer
X
#16
FFFFBCH
0000B2H
16-bit reload timer 0
O
#17
FFFFB8H
ICR03
A/D converter
O
#18
FFFFB4H
0000B3H
Input/output timer
X
#19
FFFFB0H
ICR04
External interrupt INT2/INT3
O
#20
FFFFACH
0000B4H
Serial I/O
O
#21
FFFFA8H
ICR05
PPG (ch0, ch1) unit 0
X
#22
FFFFA4H
0000B5H
Input capture 0
O
#23
FFFFA0H
ICR06
External interrupt INT4/INT5
O
#24
FFFF9CH
0000B6H
Input capture 1
O
#25
FFFF98H
ICR07
PPG (ch2, ch3) unit 1
X
#26
FFFF94H
0000B7H
External interrupt INT6/INT7
O
#27
FFFF90H
ICR08
Monitoring timer
X
#28
FFFF8CH
0000B8H
PPG (ch4, ch5) unit 2
X
#29
FFFF88H
ICR09
Input capture 2/3
O
#30
FFFF84H
0000B9H
51
CHAPTER 3 INTERRUPTS
Table 3.2-1 Interrupt Sources, Interrupt Vectors, and Interrupt Control Registers (2/2)
Interrupt source
EI2OS clear
Interrupt vector
Number
Address
PPG (ch6, ch7) unit 3
X
#31
FFFF80H
Output compare 0
O
#32
FFFF7CH
Output compare 1
O
#33
FFFF78H
Input capture 4/5
O
#34
FFFF74H
Output compare 2/3-input
capture 6/7
O
#35
FFFF70H
16-bit reload timer 1
O
#36
FFFF6CH
UART 0 RX
*
#37
FFFF68H
UART 0 TX
O
#38
FFFF64H
UART 1 RX
*
#39
FFFF60H
UART 1 TX
O
#40
FFFF5CH
Flash memory
X
#41
FFFF58H
Delayed interrupt
X
#42
FFFF54H
Interrupt control register
Number
Address
ICR10
0000BAH
ICR11
0000BBH
ICR12
0000BCH
ICR13
0000BDH
ICR14
0000BEH
ICR15
0000BFH
*: An EI2OS interrupt clear signal clears the interrupt request flag. A stop request is issued.
O: An EI2OS interrupt clear signal clears the interrupt request flag.
X: An EI2OS interrupt clear signal does not clear the interrupt request flag.
Note:
In a peripheral module in which two interrupt sources are assigned to the same interrupt number, an
EI2OS interrupt clear signal clears both interrupt request flags.
At EI2OS termination, an EI2OS clear signal is issued to all interrupt flags assigned to the same
interrupt number. If an interrupt flag starts EI2OS and another interrupt flag is set by a hardware
event, the flag is cleared by the EI2OS clear signal issued by the first event and the latter event is
lost. Do not use EI2OS for this interrupt number.
When EI2OS is enabled, one of two interrupt signals in the same interrupt control register (ICR) is
issued to start EI2OS. Although an individual EI2OS descriptor should be provided for each interrupt
source, the two interrupt sources actually share the same EI2OS descriptor. While one interrupt
source is using EI2OS, therefore, the other interrupt source must be disabled.
52
CHAPTER 3 INTERRUPTS
3.3
Interrupt Vector
Table 3.3-1 lists MB90540/545 series interrupt vectors.
■ Interrupt Vector
Table 3.3-1 Interrupt Vector (1/2)
Software
interrupt
instruction
Vector
address L
Vector
address M
Vector
address H
Mode
register
Interrupt
No.
INT 0
FFFFFCH
FFFFFDH
FFFFFEH
Not used
#0
:
:
:
:
:
:
INT 7
FFFFE0H
FFFFE1H
FFFFE2H
Not used
#7
None
INT 8
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDFH
#8
(RESET vector)
INT 9
FFFFD8H
FFFFD9H
FFFFDAH
Not used
#9
ROM correction
INT 10
FFFFD4H
FFFFD5H
FFFFD6H
Not used
#10
<Exception>
INT 11
FFFFD0H
FFFFD1H
FFFFD2H
Not used
#11
CAN 0 RX
INT 12
FFFFCCH
FFFFCDH
FFFFCEH
Not used
#12
CAN 0 TX/NS
INT 13
FFFFC8H
FFFFC9H
FFFFCAH
Not used
#13
CAN 1 RX
INT 14
FFFFC4H
FFFFC5H
FFFFC6H
Not used
#14
CAN 1 TX/NS
INT 15
FFFFC0H
FFFFC1H
FFFFC2H
Not used
#15
External interrupt INT0/
INT1
INT 16
FFFFBCH
FFFFBDH
FFFFBEH
Not used
#16
Timebase timer
INT 17
FFFFB8H
FFFFB9H
FFFFBAH
Not used
#17
16-bit reload timer 0
INT 18
FFFFB4H
FFFFB5H
FFFFB6H
Not used
#18
A/D converter
INT 19
FFFFB0H
FFFFB1H
FFFFB2H
Not used
#19
I/O timer
INT 20
FFFFACH
FFFFADH
FFFFAEH
Not used
#20
External interrupt INT2/
INT3
INT 21
FFFFA8H
FFFFA9H
FFFFAAH
Not used
#21
Serial I/O
INT 22
FFFFA4H
FFFFA5H
FFFFA6H
Not used
#22
PPG (ch0, ch1) unit 0
INT 23
FFFFA0H
FFFFA1H
FFFFA2H
Not used
#23
Input capture 0
INT 24
FFFF9CH
FFFF9DH
FFFF9EH
Not used
#24
External interrupt INT4/
INT5
INT 25
FFFF98H
FFFF99H
FFFF9AH
Not used
#25
Input capture 1
INT 26
FFFF94H
FFFF95H
FFFF96H
Not used
#26
PPG (ch2, ch3) unit 1
Hardware interrupt
None
:
53
CHAPTER 3 INTERRUPTS
Table 3.3-1 Interrupt Vector (2/2)
Software
interrupt
instruction
Vector
address L
Vector
address M
Vector
address H
Mode
register
Interrupt
No.
INT 27
FFFF90H
FFFF91H
FFFF92H
Not used
#27
External interrupt INT6/
INT7
INT 28
FFFF8CH
FFFF8DH
FFFF8EH
Not used
#28
Monitoring timer
INT 29
FFFF88H
FFFF89H
FFFF8AH
Not used
#29
PPG (ch4, ch5) unit 2
INT 30
FFFF84H
FFFF85H
FFFF86H
Not used
#30
Input capture 2/3
INT 31
FFFF80H
FFFF81H
FFFF82H
Not used
#31
PPG (ch6, ch7) unit 3
INT 32
FFFF7CH
FFFF7DH
FFFF7EH
Not used
#32
Output compare 0
INT 33
FFFF78H
FFFF79H
FFFF7AH
Not used
#33
Output compare 1
INT 34
FFFF74H
FFFF75H
FFFF76H
Not used
#34
Input capture 4/5
INT 35
FFFF70H
FFFF71H
FFFF72H
Not used
#35
Output compare 2/3
Input capture 6/7
INT 36
FFFF6CH
FFFF6DH
FFFF6EH
Not used
#36
16-bit reload timer 1
INT 37
FFFF68H
FFFF69H
FFFF6AH
Not used
#37
UART 0 RX
INT 38
FFFF64H
FFFF65H
FFFF66H
Not used
#38
UART 0 TX
INT 39
FFFF60H
FFFF61H
FFFF62H
Not used
#39
UART 1 RX
INT 40
FFFF5CH
FFFF5DH
FFFF5EH
Not used
#40
UART 1 TX
INT 41
FFFF58H
FFFF59H
FFFF5AH
Not used
#41
Flash memory
INT 42
FFFF54H
FFFF55H
FFFF56H
Not used
#42
Delayed interrupt
INT 43
FFFF50H
FFFF51H
FFFF52H
Not used
#43
None
:
:
:
:
:
:
INT 254
FFFC04H
FFFC05H
FFFC06H
Not used
#254
None
INT 255
FFFC00H
FFFC01H
FFFC02H
Not used
#255
None
54
Hardware interrupt
:
CHAPTER 3 INTERRUPTS
3.4
Hardware Interrupts
In response to an interrupt request signal from an peripheral function, the CPU pauses
current program execution and transfers control to the interrupt processing program
defined by the user. This function is called the hardware interrupt function.
■ Hardware Interrupts
A hardware interrupt occurs when the relevant conditions are satisfied as a result of two
operations: comparison between the interrupt request level and the value in the interrupt level
mask register (ILM) of PS in the CPU, and hardware reference to the I flag value of PS.
The CPU performs the following processing when a hardware interrupt occurs:
•
Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to
the system stack.
•
Sets ILM in the PS register. The currently requested interrupt level is automatically set.
•
Fetches the corresponding interrupt vector value and branches to the processing indicated by
that value.
■ Structure of Hardware Interrupt
Hardware interrupts are handled by the following three sections:
❍ Peripheral functions
Interrupt enable and request bits: Used to control interrupt requests from resources.
❍ Interrupt controller
ICR: Assigns interrupt levels and determines the priority levels of simultaneously requested
interrupts.
❍ CPU
I and ILM: Used to compare the requested and current interrupt levels and to identify the interrupt
enable status.
Microcode: Interrupt processing step
The status of these sections are indicated by the resource control registers for peripheral
functions, the ICR for the interrupt controller, and the CCR value for the CPU. To use a hardware
interrupt, set the three sections beforehand by using software.
The interrupt vector table referenced during interrupt processing is assigned to addresses
FFFC00H to FFFFFFH in memory. These addresses are shared with software interrupts.
■ Hardware Interrupt Request During Writing to the Input-Output Area
When data is being written to the input-output area, hardware interrupt requests are not accepted.
This prevents the CPU from making operational mistakes, which could be caused if an interrupt
request were generated while data was being rewritten to the interrupt control registers for each
resource.
55
CHAPTER 3 INTERRUPTS
■ Multiple Interrupts
The F2MC-16LX CPU supports multiple interrupts. If an interrupt of a higher level occurs while
another interrupt is being processed, control is transferred to the higher-level interrupt after the
current instruction completes execution. After the higher-level interrupt terminates, the CPU
returns to processing of the previous interrupt. If an interrupt of the same or lower level occurs
while another interrupt is being processed, the new interrupt request is kept pending until
termination of the current interrupt processing unless the ILM value or I flag is changed by an
instruction. The extended intelligent I/O service cannot be used for the activation of multiple
interrupts. During processing of the extended intelligent I/O service, all other interrupt requests or
extended intelligent I/O service requests are kept pending.
■ Register Saving onto the Stack
Figure 3.4-1 shows the order of the registers saved in the stack.
Figure 3.4-1 Registers Saved on the Stack
Word (16 bits)
MSB
LSB
H
↑
←
SSP
(SSP value before interrupt)
AH
AL
DPR
ADB
DTB
PCB
PC
↓
L
56
PS
←
SSP
(SSP value after interrupt)
CHAPTER 3 INTERRUPTS
3.4.1
Hardware Interrupt Operation
An internal resource that has the hardware interrupt request function has an interrupt
request flag and interrupt enable flag. The interrupt request flag indicates whether an
interrupt request exists, and the interrupt enable flag indicates whether the relevant
internal resource requests an interrupt to the CPU. The interrupt request flag is set
when an event occurs that is unique to the internal resource. When the interrupt enable
flag indicates "enable", the resource issues an interrupt request to the interrupt
controller.
■ Hardware Interrupt Operation
When two or more interrupt requests are received at the same time, the interrupt controller
compares the interrupt levels (IL) in ICR, selects the request at the highest level (the smallest IL
value), then reports that request to the CPU. If multiple requests are at the same level, the
interrupt controller selects the request with the lowest interrupt number. The relationship between
the interrupt requests and ICRs is determined by the hardware.
The CPU compares the received interrupt level and the ILM in the PS register. If the interrupt
level is smaller than the ILM value and the I bit of the PS register is set to 1, the CPU activates
the interrupt processing microcode after the currently executing instruction is completed. The
CPU references the ISE bit of the ICR of the interrupt controller at the beginning of the interrupt
processing microcode, checks that the ISE bit is 0 (interrupt), and activates the interrupt
processing body.
The interrupt processing body saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the
memory area indicated by SSB and SSP, fetches three bytes of interrupt vector and loads them
onto PC and PCB, updates the ILM of PS to a level value of the received interrupt, sets the S
flag, then performs branch processing. As a result, the interrupt processing program defined by
the user is executed next.
Figure 3.4-2 illustrates the flow from the occurrence of a hardware interrupt until there is no
interrupt request in the interrupt processing program.
57
CHAPTER 3 INTERRUPTS
Figure 3.4-2 Occurrence and Release of Hardware Interrupt
Register file
PS
IR
(6)
(5)
F2MC-16LX CPU
Enable FF
AND
(2)
Cause FF
Level comparator
··
··
·
(1)
(4)
PS: Processor status
I:
Interrupt enable flag in CCR
ILM: Interrupt level mask register
in PS
IR: Instruction register
(3)
Peripheral
(7)
Comparator
Check
Interrupt level IL
Internal data bus
Microcode
ILM
I
Interrupt
controller
Peripheral
Operations (1) to (7) in Figure 3.4-2 are explained below.
(1) An interrupt cause occurs in a peripheral.
(2) The interrupt enable bit in the peripheral is referenced. If interrupts are enabled, the peripheral
issues an interrupt request to the interrupt controller.
(3) Upon reception of the interrupt request, the interrupt controller determines the priority levels of
simultaneously requested interrupts. Then, the interrupt controller transfers the interrupt level
of the corresponding interrupt to the CPU.
(4) The CPU compares the interrupt level requested by the interrupt controller with the ILM bit of
the processor status register.
(5) If the comparison shows that the requested level is higher than the current interrupt
processing level, the I flag value of the same processor status register is checked.
(6) If the check in step 5. shows that the I flag indicates interrupt enable status, the requested
level is written to the ILM bit. Interrupt processing is performed as soon as the currently
executing instruction is completed, then control is transferred to the interrupt processing
routine.
(7) When the interrupt cause of step 1. is cleared by software in the user interrupt processing
routine, the interrupt request is completed.
The time required for the CPU to execute the interrupt processing in steps 6. and 7. is shown
below.
Interrupt start : 24 + 6
× (Table 3.4-1 machine cycles)
Interrupt return : 15 + 6 × (Table 3.4-1 machine cycles) RETI instruction
Table 3.4-1 Compensation Values for Interrupt Processing Cycle Count
Address indicated by the stack pointer
Cycle count compensation value
External area, 8-bit data bus
+4
External area, even-numbered address
+1
External area, odd-numbered address
+4
Internal area, even-numbered address
0
Internal area, odd-numbered address
+2
58
CHAPTER 3 INTERRUPTS
3.4.2
Flow of Hardware Interrupt Operation
Figure 3.4-3 shows the flow of hardware interrupt operation.
■ Flow of Hardware Interrupt Operation
Figure 3.4-3 Flow of Hardware Interrupt Operation
I
ILM
IF
IE
ISE
IL
S
I&IF&IE=1
AND
ILM > IL
:
:
:
:
:
:
:
Interrupt enable flag in CCR
Interrupt level mask register in PS
Interrupt request for internal resource
Interrupt enable flag for internal resource
EI2OS enable flag
Interrupt request level for internal resource
Flag in CCR
YES
NO
NO
Fetch the next instruction
and decode
Save PS, PC, PCB, DTB,
ADB, DPR, and A to the
SSP stack, then set ILM = IL
INT instruction?
Execute an ordinary instruction
Repetition of
string type instruction
completed?
Extended intelligent I/O
service processing
YES
NO
NO
YES
ISE = 1
Save PS, PC, PCB, DTB, ADB,
DPR, and A to the SSP stack,
then set I = 0 and ILM = IL
S←1
(fetch interrupt vector)
YES
Update PC
59
CHAPTER 3 INTERRUPTS
3.4.3
Required Time to Start Interrupt Processing
The time for terminating the currently executing instruction plus the interrupt handling
time is required from generation of the hardware interrupt request to execution of the
interrupt-processing.
■ Required Time to Start Interrupt Processing
The interrupt request sampling wait time and the interrupt handling time (required time for
preparation for interrupt processing) are required from generation of the interrupt request and
acceptance of interrupt, to execution of the interrupt processing. Figure 3.4-4 shows the interrupt
processing time.
Figure 3.4-4 Interrupt Processing Time
Operation of CPU
Interrupt wait time
Execution of
normal instruction
Interrupt request
sampling wait time
Interrupt handling
Interrupt processing
Interrupt handling time
( machine cycle)*
Interrupt request generated
*
: Last instruction cycle when sampling interrupt request.
: One machine cycle is equal to one clock cycle of the machine clock (φ).
❍ Interrupt request sampling wait time
It indicates a time from the generation of the interrupt request to the termination of currently
executing instruction.
Whether an interrupt request is generated or not is determined by sampling the interrupt request
in the last cycle of each instruction. The CPU cannot recognize the interrupt request during
execution of each instruction, as a result wait time occurs.
Reference:
The interrupt request sampling wait time is the longest when the interrupt request is generated
immediately after starting execution of the POPW, RW0, ...RW7 instructions with the longest
execution cycle (45 machine cycles).
60
CHAPTER 3 INTERRUPTS
❍ Interrupt handling time (θ machine cycles)
The CPU requires an interrupt handling time of θ machine cycles to save the dedicated registers
to the system stack and fetch the interrupt vector table address after accepting the interrupt
request. The interrupt handling time (θ) is obtained using the following equations.
θ = 24 + 6 × Z machine cycles (Z: compensation value of interrupt handling time)
The interrupt handling time depends on the address set by the stack pointer. Table 3.4-2 shows
the compensation value (Z) of the interrupt handling time.
Table 3.4-2 Compensation Value (Z) of Interrupt Handling Time
Address Set by Stack Pointer
Compensation Value (Z)
For external area (8-bit address)
+4
For external area (even address)
+1
For external area (odd address)
+4
For internal area (even address)
0
For internal area (odd address)
+2
Reference:
One machine cycle equal to one clock cycle of the machine clock (φ).
61
CHAPTER 3 INTERRUPTS
3.5
Software Interrupts
The software interrupt function returns control from the program being executed by the
CPU to the user-defined interrupt processing program in response to execution of a
special instruction.
■ Software Interrupts
A software interrupt is always activated when the software interrupt instruction is executed.
The CPU performs the following processing when a software interrupt occurs:
•
Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to
the system stack.
•
Set PS: I flag to "0". Interrupts are automatically disabled.
•
Fetches the corresponding interrupt vector value, then branches to the processing indicated
by that value.
A software interrupt request issued by the INT instruction has no interrupt request or enable flag.
A software interrupt request is always issued by executing the INT instruction.
The INT instruction does not have an interrupt level. Therefore, the INT instruction does not
update ILM. The INT instruction clears the I flag to suspend subsequent interrupt requests.
■ Structure of Software Interrupts
Software interrupts are handled within the CPU:
❍ CPU
•
Microcode: Interrupt processing step
As shown in Table 3.3-1, software interrupts share the same interrupt vector area with hardware
interrupts. For example, interrupt request number INT15 is used for external interrupt #0
(hardware interrupt) as well as for INT #15 (software interrupt). Therefore, external interrupts #0
and INT #15 call the same interrupt processing routine.
■ Software Interrupt Operation
When the CPU fetches and executes the software interrupt instruction, the software interrupt
processing microcode is activated. The software interrupt processing microcode saves 12 bytes
(PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP. The
microcode then fetches three bytes of interrupt vector and loads them onto PC and PCB, resets
the I flag, and sets the S flag. Then, the microcode performs branch processing. As a result, the
interrupt processing program defined by the user application program is executed next.
Figure 3.5-1 illustrates the flow from the occurrence of a software interrupt until there is no
interrupt request in the interrupt processing program.
62
CHAPTER 3 INTERRUPTS
Figure 3.5-1 Occurrence and Release of Software Interrupt
(1)
PS
Internal data bus
Register file
I
S
(2)
Microcode
F2MC-16LX CPU
B unit
IR
Queue
Fetch
(3)
Save
Instruction bus
PS
I
ILM
RAM
IR
B unit
: Processor status
: Interrupt enable flag in CCR
: Interrupt level mask register
in PS
: Instruction register
: Bus interface unit
Figure 3.5-1 illustrates the flow from the occurrence of a software interrupt until there is no
interrupt request in the interrupt processing program.
(1) The software interrupt instruction is executed.
(2) Special CPU registers in the register file are saved according to the microcode corresponding
to the software interrupt instruction.
(3) The interrupt processing is completed with the RETI instruction in the user interrupt
processing routine.
■ Note on Software Interrupt
When the program counter bank register (PCB) is FFH, the CALLV instruction vector area
overlaps the table of the INT #vct8 instruction. When designing software, ensure that the CALLV
instruction does not use the same address as that of the #vct8 instruction.
63
CHAPTER 3 INTERRUPTS
3.6
Extended Intelligent I/O Service (EI2OS)
The EI2OS function automatically transfers data between input and output and memory.
An interrupt processing program was conventionally used for such processing, but
EI2OS enables data transfer to be performed like DMA (direct memory access).
■ Extended Intelligent I/O Service (EI2OS)
The extended intelligent I/O service (EI2OS) has the following advantages over the conventional
interrupt processing method:
•
The program size can be small because it is not necessary to write a transfer program.
•
No internal register is used for transfer, eliminating the need for register saving and increasing
the transfer speed.
•
Transfer can be terminated from I/O, preventing unnecessary data from being transferred.
•
Incrementing, decrementing, or no update can be selected for the buffer address.
•
Incrementing, decrementing, or no update can be selected for the I/O register address (if the
buffer address is updated).
At the end of EI2OS, processing automatically branches to an interrupt processing routine after
the end condition is set. Thus, the user can identify the end condition.
Note:
The extended intelligent I/O service (EI2OS) can be used if using the REALOS.
Figure 3.6-1 provides an overview of EI2OS.
64
CHAPTER 3 INTERRUPTS
Figure 3.6-1 Outline of Extended Intelligent I/O Service
Memory space
by IOA
I/O register
I/O register
Peripheral
CPU
Interrupt request
ISD
by ICS
Interrupt control register
Interrupt controller
by BAP
Buffer
by
DCT
I/O requests transfer.
The interrupt controller selects the
descriptor.
The transfer source and destination
are read from the descriptor.
Data is transferred between I/O and
memory.
The interrupt source is automatically cleared.
Notes:
• The area that can be specified by IOA is between 000000H and 00FFFFH.
• The area that can be specified by BAP is between 000000H and FFFFFFH.
• The maximum transfer count that can be specified by DTC is 65,536.
■ Structure of Extended Intelligent I/O Service (EI2OS)
EI2OS is handled by the following four sections:
❍ Internal resources
Interrupt enable and request bits: Used to control interrupt requests from resources.
❍ Interrupt controller
ICR: Assigns interrupt levels, determines the priority levels of simultaneously requested
interrupts, and selects the EI2OS operation.
❍ CPU
I and ILM: Used to compare the requested and current interrupt levels and to identify the
interrupt enable status
Microcode: EI2OS processing step
❍ RAM
Descriptor: Describes the EI2OS transfer information.
65
CHAPTER 3 INTERRUPTS
3.6.1
Interrupt Control Register (ICR)
The interrupt control register, located in the interrupt controller, handles the interrupts
corresponding to all I/Os that have an interrupt function. The interrupt control register
has the following three functions:
• Setting an interrupt level for each related peripheral
• Selecting whether to use an ordinary interrupt or extended intelligent I/O service for a
related peripheral
• Selecting the extended intelligent I/O service channel
Do not access an interrupt control register with a read-modify-write instruction, since
an erroneous operation will result.
■ Interrupt Control Register (ICR)
Figure 3.6-2 shows the bit configuration of the interrupt control register (ICR).
Figure 3.6-2 Interrupt Control Register (ICR)
15/7
14/6
13/5
12/4
11/3
10/2
9/1
8/0
←Bit No.
ICS3
ICS2
ICS1
ICS0
ISE
IL2
IL1
IL0
During writing
Read/Write→
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
Initial value→
(0)
(0)
(0)
(0)
(0)
(1)
(1)
(1)
15/7
14/6
13/5
12/4
11/3
10/2
9/1
8/0
←Bit No.
⎯
⎯
S1
S0
ISE
IL2
IL1
IL0
During reading
Read/Write→
(-)
(-)
(R)
(R)
(R)
(R)
(R)
(R)
Initial value→
(-)
(-)
(0)
(0)
(0)
(1)
(1)
(1)
Address: B0H to BFH
Address: B0H to BFH
Note:
ICS3 to ICS0 are valid only when EI2OS is activated. Set ISE to "1" to activate EI2OS and to "0" not
to activate it. When EI2OS is not to be activated, any value can be set in ICS3 to ICS0.
For ICS3 and ICS2, "1" is always read.
ICS1 and ICS0 can only be written to. S1 and S0 can only be read.
[bit15 to bit12 and bit7 to bit4] ICS3 to ICS0
The ICS3 to ICS0 bits specify the EI2OS channel.
They are write-only bits. The values set for these bits determine the extended intelligent I/O
service descriptor addresses in memory. The ICS bits are initialized by a reset.
Table 3.6-1 lists the correspondence between ICS bits, channel numbers, and descriptor
addresses.
66
CHAPTER 3 INTERRUPTS
Table 3.6-1 ICS Bits, Channel Numbers, and Descriptor Addresses
ICS3
ICS2
ICS1
ICS0
Selected channel
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
[bit13 and bit12 and bit5 and bit4] S0 and S1
The S0 and S1 bits indicate the EI2OS termination status.
They are read-only bits. When the values in these bits are checked at EI2OS termination, the
termination condition can be identified. These bits are initialized to "00B" by a reset.
Table 3.6-2 shows the relationship between the S bits and termination conditions.
Table 3.6-2 S Bits and Termination Conditions
S1
S0
Termination condition
0
0
EI2OS running or not activated
0
1
Stopped status due to count termination
1
0
Reserved
1
1
Stopped status due to a request from the internal resource
67
CHAPTER 3 INTERRUPTS
[bit11 and bit3] ISE
The ISE bit enables EI2OS. This bit can be read and written to.
If this bit is "1" when an interrupt request is generated, EI2OS is activated. If this bit is "0"
when an interrupt request is generated, the interrupt sequence is activated. When the EI2OS
termination condition is met (when the S1 and S0 bits are not "00B"), the ISE bit is cleared to
"0". If the corresponding peripheral function does not have the EI2OS function, the ISE bit
must be set to "0" by software. The ISE bit is initialized to "0" by a reset.
[bit10 to bit8 and bit2 to bit0] IL0, IL1, and IL2
The IL0, IL1, and IL2 bits set the interrupt level.
These bits specify the interrupt level of the corresponding internal resources. These bits can
be read and written to. These bits are initialized to level 7 (no interrupt) by a reset. Table 3.6-3
shows the relationship between the interrupt level setting bits and interrupt levels.
Table 3.6-3 Interrupt Level Setting Bits and Interrupt Levels
68
ILM2
ILM1
ILM0
Interrupt level
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6 (lowest interrupt)
1
1
1
7 (no interrupt)
0 (highest interrupt)
CHAPTER 3 INTERRUPTS
3.6.2
Extended Intelligent I/O Service Descriptor (ISD)
The extended intelligent I/O service descriptor exists between 000100H and 00017FH in
internal RAM, and consists of the following items:
• Data transfer control data
• Status data
• Buffer address pointer
■ Extended Intelligent I/O Service Descriptor (ISD)
Figure 3.6-3 shows the configuration of the extended intelligent I/O service descriptor.
Figure 3.6-3 Extended Intelligent I/O Service Descriptor Configuration
H
High-order 8 bits of data counter (DCTH)
Low-order 8 bits of data counter (DCTL)
High-order 8 bits of I/O register address pointer (IOAH)
Low-order 8 bits of I/O register address pointer (IOAL)
EI 2OS status (ISCS)
High-order 8 bits of buffer address pointer (BAPH)
000100 H + 8 × ICS
Medium-order 8 bits of buffer address pointer (BAPM)
ISD start address
Low-order 8 bits of buffer address pointer (BAPL)
L
■ Data Counter (DCT)
This is a 16-bit register that works as a counter corresponding to the number of data items
transferred. This counter is decremented by one before data transfer. EI2OS is terminated when
this counter reaches 0. Figure 3.6-4 shows the data counter (DTC) configuration.
Figure 3.6-4 Data Counter (DTC) Configuration
Data counter (upper)
Initial value→
15
B15
14
B14
13
B13
12
B12
11
B11
10
B10
9
B09
8
B08
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
6
B06
(X)
5
B05
(X)
4
B04
(X)
3
B03
(X)
2
B02
(X)
1
B01
(X)
0
B00
(X)
←Bit No.
DCTH
Data counter (lower)
Initial value→
7
B07
(X)
←Bit No.
DCTL
69
CHAPTER 3 INTERRUPTS
■ I/O Register Address Pointer (IOA)
This is a 16-bit register that indicates the buffer used for data transfer and the low-order address
(A15 to A00) of I/O register. The high-order address (A23 to A16) are all zeroes, and any I/O
between addresses 000000H and 00FFFFH can be specified. Figure 3.6-5 shows the I/O register
address pointer (IOA) configuration.
Figure 3.6-5 I/O Register Address Pointer (IOA) Configuration
I/O register address pointer (upper)
15
A15
(X)
Initial value→
14
A14
(X)
13
A13
(X)
12
A12
(X)
11
A11
(X)
10
A10
(X)
9
A09
(X)
8
A08
(X)
←Bit No.
IOAH
5
A05
(X)
4
A04
(X)
3
A03
(X)
2
A02
(X)
1
A01
(X)
0
A00
(X)
←Bit No.
IOAL
I/O register address pointer (lower)
7
A07
(X)
Initial value→
6
A06
(X)
■ EI2OS Status Register (ISCS)
The EI2OS status register (ISCS) is 8-bit register, and indicates the update direction
(increment/decrement), transfer data format (byte/word), and transfer direction of the buffer
address pointer and I/O register address pointer.
This register also indicates whether the buffer address pointer or I/O register address pointer
is updated or fixed.
Figure 3.6-6 shows the EI2OS Status Register (ISCS) configuration.
Figure 3.6-6 EI2OS Status Register (ISCS) Configuration
7
6
5
Reserved Reserved Reserved
Initial value→
(X)
(X)
(X)
4
3
2
1
0
IF
BW
BF
DIR
SE
(X)
(X)
(X)
(X)
(X)
←Bit No.
Each bit is described below.
[bit4] IF
The IF bit specifies whether the I/O register address pointer is updated or fixed.
Table 3.6-4 I/O Register Address Pointer Update/Fixed Bit (IF)
IF
70
Function
0
After data transfer, the I/O register address pointer is updated.
1
After data transfer, the I/O register address pointer is not updated.
CHAPTER 3 INTERRUPTS
[bit3] BW
The BW bit specifies the transfer data length.
Table 3.6-5 Transfer Data Length Specifying Bit (BW)
BW
Function
0
Byte
1
Word
71
CHAPTER 3 INTERRUPTS
[bit2] BF
The BF bit specifies whether the buffer address pointer is updated or fixed.
Table 3.6-6 Buffer Address Pointer Update/Fixed Selection Bit (BF)
BF
Function
0
After data transfer, the buffer address pointer is updated.
1
After data transfer, the buffer address pointer is not updated.
Note:
Only the lower 16 bits of the buffer address pointer are updated. Only incrementing is allowed.
[bit1] DIR
The DIR bit specifies the data transfer direction.
Table 3.6-7 Data Transfer Direction Specification Bit (DIR)
DIR
Setting
0
I/O -> buffer
1
Buffer -> I/O
[bit0] SE
The SE bit controls the termination of the extended intelligent I/O service based on resource
requests.
Table 3.6-8 EI2OS Termination Control Bit
SE
Setting
0
Not terminated by a resource request.
1
Terminated by a resource request.
■ Buffer Address Pointer (BAP)
This 24-bit register holds the address used for the next EI2OS transfer. BAP exists for each
EI2OS channel. Therefore, each EI2OS channel can be used for transfer with anywhere in the 16Mbyte space.
Note:
If the BF bit of ISCS is set to "0" (update enabled), only the low-order 16 bits of BAP changes and
BAPH does not change.
72
CHAPTER 3 INTERRUPTS
3.6.3
Operation of Extended Intelligent I/O Service (EI2OS)
Figure 3.6-7 shows the operation flow of the extended intelligent I/O service (EI2OS).
Figure 3.6-8 shows the procedure for using the extended intelligent I/O service (EI2OS).
■ Operation Flow of the Extended Intelligent I/O Service (EI2OS)
Figure 3.6-7 Operation Flow of the Extended Intelligent I/O Service (EI2OS)
Interrupt request
generated
by peripheral function
ISE = 1
NO
YES
Read ISD/ISCS
Termination
request from
resource?
Interrupt sequence
YES
DIR = 1
NO
NO
YES
Data indicated by IOA
(Data transfer)
Memory indicated by BAP
IF = 0
NO
BF = 0
Data indicated by BAP
(Data transfer)
Memory indicated by BAP
YES
DCT = 00
NO
Set S1 and S0 to 00
Update value
by BW
Update IOA
Update value
by BW
Update BAP
YES
NO
Decrement DCT
(-1)
YES
EI2 OS termination processing
Set S1 and S0 to 01
Peripheral function :
Clear interrupt request
Return to CPU operation
2
YES
SE = 1
NO
ISD : EI OS descriptor
ISCS : EI2OS status register
IF
: IOA update/fixed selection bit in the
EI2OS status register (ISCS)
BW : Transfer data length specification
bit in the EI2OS status register (ISCS)
BF
: BAP update/fixed selection bit in the
EI2OS status register (ISCS)
DIR : Data transfer direction specification
bit in the EI2OS status register (ISCS)
SE
: EI2OS termination control bit in the
EI2OS status register (ISCS)
Set S1 and S0 to 11
Clear ISE to 0
Interrupt sequence
DCT
IOA
BAP
ISE
S1,S0
: Data counter
: I/O register address pointer
: Buffer address pointer
: EI2OS enable bit in the interrupt control register (ICR)
: EI2OS status in the interrupt control register (ICR)
73
CHAPTER 3 INTERRUPTS
Figure 3.6-8 Procedure for Using the Extended Intelligent I/O Service (EI2OS)
Software processing
Hardware processing
Start
Initialization
Set the system stack area
Set the EI2OS descriptor
Initialize the peripheral function
Set the interrupt
control register (ICR)
Set the peripheral function
to start operation. Set the
interrupt enable bit (ICR)
Set the ILM and I in the PS
S1, S0 = "00"
Execute the user program
(Interrupt request)and (ISE = 1)
Transfer data
Decide whether to
end counting or to branch to
an interrupt by termination
request from resource
(Branch to interrupt vector)
Set the extended
intelligent I/O service
again (switch channels)
S1, S0 = "01" or
S1, S0 = "11"
Process data in the buffer
RETI
ISE:
EI2OS enable bit in the interrupt control register (ICR)
S1, S0: EI2OS status of the interrupt control register (ICR)
74
YES
NO
CHAPTER 3 INTERRUPTS
3.6.4
Execution Time of the Extended Intelligent I/O Service
(EI2OS)
The time required for executing the extended intelligent I/O service (EI2OS) changes in
the following three cases:
• When data transfer continues (when the stop condition is not satisfied)
• When a stop request is issued from a resource
• When the counting is completed
■ Execution Time of the Extended Intelligent I/O Service (EI2OS)
❍ When data transfer continues (when the stop condition is not satisfied)
(Table 3.6-9 + Table 3.6-10) machine cycles
Table 3.6-9 Execution Time when the Extended EI2OS Continues
ISCS SE bit
Set to "0"
I/O register address pointer
Set to "1"
Fixed
Updated
Fixed
Updated
Fixed
32
34
33
35
Updated
34
36
35
37
Buffer address pointer
❍ When a stop request is issued from a resource
(36 + 6 x Table 3.4-1) machine cycles
❍ When the counting is completed
(Table 3.6-9 + Table 3.6-10 + (21 + 6 x Table 3.4-1)) machine cycles
Table 3.6-10 Data Transfer Compensation Values for Extended EI2OS Execution Time
Internal access
External access
I/O register address pointer
Buffer
address
pointer
B/E
O
B/E
8/O
Internal
access
B/E
0
+2
+1
+4
O
+2
+4
+3
+6
External
access
B/E
+1
+3
+2
+5
8/O
+4
+6
+5
+8
B: Byte data transfer
8: 8-bit external bus word transfer
E: Even address word transfer
O: Odd address word transfer
75
CHAPTER 3 INTERRUPTS
3.7
Exception Due to Execution of an Undefined Instruction
In the F2MC-16LX, an exception occurs when an undefined instruction is executed and
exception processing is performed. Exception processing is fundamentally the same as
interrupt processing. When an exception is detected between instructions, exception
processing is performed separately from ordinary processing. In general, exception
processing is performed as the result of an unexpected operation. It is recommended
that exception processing is used only for debugging or for activating emergency
recovery software.
■ Exception Due to Execution of an Undefined Instruction
The F2MC-16LX handles all codes that are not defined in the instruction map as undefined
instructions. When an undefined instruction is executed, processing equivalent to the INT 10
software interrupt instruction is performed. Specifically, the AL, AH, DPR, DTB, ADB, PCB, PC,
and PS values are saved onto the system stack, and processing branches to the routine indicated
by the interrupt number 10 vector. In addition, the I flag is cleared and the S flag is set. The PC
value saved on the stack is the address at which the undefined instruction is stored. Although
processing can be restored with the RETI instruction, this is pointless because the same
exception occurs again.
76
CHAPTER 4
CLOCK AND RESET
This chapter explains the functions and operations of clocks and resets.
4.1 Clock Generator
4.2 Reset Cause Occurrence
4.3 Reset Causes
77
CHAPTER 4 CLOCK AND RESET
4.1
Clock Generator
The clock generator controls internal clock operation, including such functions as
sleep, timer, stop, and PLL multiplication. This internal clock is called the machine
clock, and one cycle of the machine clock is called a machine cycle. A clock based on
the source oscillation is called the main clock, and a clock based on the internal VCO
oscillation is called the PLL clock.
■ Notes on Clock Generator
When the operating voltage is 5 V, its frequency can be between 3 MHz and 16MHz. The highest
operating frequency for the CPU and peripheral resource circuits is 16 MHz, however. Normal
operation is not guaranteed if a multiplication factor resulting in a higher frequency than 16 MHz
is specified. For example, if the external clock frequency is 16 MHz, only 1 can be specified as
the multiplication factor.
The lowest operating frequency of the VCO oscillation is 4 MHz, and an oscillation below 4 MHz
must not be specified.
Figure 4.1-1 Clock Generator Circuit Block Diagram
S Q
Reset
Interrupt HST
Transition to
stop mode
S Q
R
Machine clock
Transition to
timer or
R
sleep mode
S Q
Selecting the machine clock
1
R
2
3
4
PLL multiplication
Selecting the oscillation
stabilization wait time
Timebase timer
1/2
X0
1/2048
1/4
1/4
1/8
XL
Selecting the watch-dog
timer interval
Watch-dog
timer
Watch-dog reset
78
CHAPTER 4 CLOCK AND RESET
4.2
Reset Cause Occurrence
When a reset cause occurs, F2MC-16LX terminates the currently executing processing
and waits for reset release.
■ Reset Cause Occurrence
A reset is caused by the following five factors:
•
Power-on reset
•
Hardware standby release
•
Watch-dog timer overflow
•
External reset request via RST pin
•
Reset request by software
Upon exit from the stop mode or after a power-on reset, the oscillation stabilization interval is
inserted before operation is restarted.
If a reset cause is generated, the F2MC-16LX immediately stops the current operation being
executed and enters reset release standby mode.
The machine clock and watch-dog function are initialized based on the reset causes.
The content of the watch-dog timer control register will change according to the reset cause.
Thus, the cause of the previous reset can be known.
Note:
In a mode other than stop mode, external reset input is internally sampled by the clock circuit. When
external clock signal supply is used, reset signal input is not received.
If an external bus is being used, the address generated by the device is undefined when a reset
cause occurs. The signals to be used for external bus access, including RD and WR, become
inactive.
79
CHAPTER 4 CLOCK AND RESET
■ Operation after Reset Release
When a reset cause is removed, the F2MC-16LX immediately outputs the address in which the
reset vector is stored, then fetches the reset vector and mode data. The reset vector and mode
data are assigned to the four bytes between FFFFDCH and FFFFDFH. After reset is released, the
reset vector and mode data are transferred to the registers by the hardware as described in
Figure 4.2-1.
Use the mode pin to specify whether to read the reset vector and mode data from internal ROM
or from external memory. When the mode pin is set to external vector mode, the F2MC-16LX
reads the reset vector and mode data from external memory. When using the F2MC-16LX in
single chip mode or internal ROM external bus mode, Fujitsu recommends specifying internal
vector mode.
The bus mode after the reset vector and mode data are read is specified by the mode data.
Figure 4.2-1 Source and Destination of Reset Vector and Mode Data
F2MC-16LX CPU core
Mode
Memory space
Register
FFFFDFH
Mode data
FFFFDEH
Reset vector (bits 23 to 16)
FFFFDD H
Reset vector (bits 15 to 8)
FFFFDCH
Reset vector (bits 7 to 0)
Micro ROM
Reset sequence
PCB
PC
Note:
The mode register in the above diagram is not defined immediately after a reset. Store mode data in
the memory space so that the value is written to this area.
80
CHAPTER 4 CLOCK AND RESET
■ Registers not Initialized by Reset Input
This microcontroller contains registers initialized only by a power-on reset.
Table 4.2-1 lists registers not initialized by each reset cause.
Table 4.2-1 Registers not Initialized by Reset Input
CKSCR
WTC
LPMCR
Type of reset
WS1
WS0
MCS
CS1
CS0
WDCS
CG1
CG0
Software reset
(Only RST is used.)
N
N
Y
N
N
N
N
N
Watch-dog reset
N
N
Y
N
N
N
Y
Y
Power-on reset
Y
Y
Y
Y
Y
Y
Y
Y
Hardware standby
(Device without G-suffix)
N
N
Y
N
N
N
Y
Y
Main
mode
N
N
Y
N
N
N
Y
Y
Sub
mode
Y
Y
Y
Y
Y
Y
Y
Y
Hardware standby
(Device with G-suffix)
WS1 and WS0: Set the oscillation stabilization wait time for the main clock.
MCS:
Specifies the machine clock (0 = PLL clock or 1 = main clock).
CS1 and CS0: Set the multiplication factor for the PLL clock.
WDCS:
Specifies the input clock source for the watch-dog timer
(0 = watch timer or 1 = timebase timer).
Y:
Initialized
N:
Not initialized
In particular, handle the MCS bit carefully because it sets the machine clock. For example, if
power-on does not satisfy the power-on reset specification, no power-on reset occurs. For this
reason, the internal operating frequency may become outside the valid operation range, because
MCS is not initialized, and the microcontroller may not operate normally.
If the CPU crashes for some reason and MCS, CS1, or CS0 is rewritten, the internal operating
frequency may also become outside the valid operation range. The microcontroller may not be
able to recover normally from this status by RST input only (however, if the internal watch-dog
state occurs, MCS is initialized and the microcontroller operates normally).
When either of the above cases occurs, use of HST plus RST (connecting HST and RST with a
jumper) is recommended.
Table 4.2-2 lists registers that are not initialized by reset input using HST plus RST. Note that the
operation status after the reset is released differs depending on the reset input type, HST plus
RST reset input, or only RST input, as listed in Table 4.2-2.
81
CHAPTER 4 CLOCK AND RESET
Table 4.2-2 Registers not Initialized by Reset Input
CKSCR
WTC
LPMCR
Type of reset
WS1
WS0
MCS
CS1
CS0
WDCS
CG1
CG0
N
N
Y
N
N
N
Y
Y
Main
mode
N
N
Y
N
N
N
Y
Y
Sub
mode *
Y
Y
Y
Y
Y
Y
Y
Y
HST + RST
(Device without G-suffix)
HST + RST (Device
with G-suffix)
Y: Initialized
N: Not initialized
*: Including the sub mode transition period.
82
CHAPTER 4 CLOCK AND RESET
Figure 4.2-2 Operation Transition by Reset Input
Reset input
(RST, HST+RST)
A. Oscillation status
Oscillating
Status
Main
Oscillating
Sub
Oscillating
Main
Waiting for main
clock oscillation
stabilization
Only RST
used
(HST ="H")
HST + RST
used
Oscillating
Stopped
Sub
Main clock operation enabled
Waiting for subclock
oscillation stabilization
Subclock operation
enabled
B. Execution timing (L: Stop, H: Start)
Only RST used (HST ="H")
HST + RST used
Main clock mode
Oscillation stabilization
time set before reset input
When sub mode is requested,
main clock operation is enabled.
During the main clock operation,
writing to SCS bits is possible.
Subclock mode
216 counts of subclock oscillation (32 kHz) (about 2 s)
Power-on reset
Vcc (power supply)
Oscillating
Power-on
reset
Status
Main
Oscillating
Sub
Stopped
Waiting for main
clock oscillation
stabilization
Main clock operation enabled
Waiting for subclock
oscillation stabilization
Subclock operation
enabled
Oscillation stabilization time
of 218main clock counts
Main mode
Sub mode
When sub mode is requested,
main clock operation is enabled.
During the main clock operation,
writing to SCS bits is possible.
216 counts of subclock oscillation (32 kHz) (about 2 s)
83
CHAPTER 4 CLOCK AND RESET
4.3
Reset Causes
Table 4.3-1 lists the five reset causes. The machine clock and watch-dog function are
initialized differently for each reset cause.
The reset cause register indicates the reset cause.
■ Reset Causes
Table 4.3-1 Reset Causes
Machine clock
Reset
At sub clock
At PLL clock
Watch-dog
timer
Cause
Oscillation
stabilization
wait
Power-on
When the power is
turned on
Main clock *
Main clock *
Stop
Yes
Hardware
standby
"L" level input to HST pin
Main clock *
Main clock *
Stop
Yes
Watch-dog
timer
Watch-dog timer
overflow
Main clock *
Main clock *
Stop
Yes
External pin
"L" level input to RST pin
PLL clock
Previous status
maintained
No
Software
"0" written to the RST bit
in the LPMCR register
PLL clock
Previous status
maintained
No
Main clock * or
PLL clock
Main clock * or
PLL clock
*: fosc/2 (fosc: the source oscillation)
Notes:
• In stop mode, input of the external pin reset signal allows an oscillation stabilization wait time to
be set regardless of reset cause.
• The oscillation stabilization wait time for a power-on reset is fixed to 218 cycles of source
oscillation. Also, the oscillation stabilization wait time of the hardware standby reset in the
subclock mode is fixed to 217 cycles of the source oscillation. For other types of reset, the
oscillation stabilization wait time is determined by WS1 and WS0 of the clock selection register.
Each reset cause has a corresponding flip-flop. The contents of the flip-flop can be obtained by
reading the watch-dog timer control register. If the reset cause must be identified after the reset is
released, be sure that the value read from the watch-dog timer control register is processed by
software and processing branches to an appropriate application program.
84
CHAPTER 4 CLOCK AND RESET
Figure 4.3-1 Reset Cause Bit Block Diagram
HST pin
RST pin
RST=L
HST=L
Without periodic clear
Power on
RST bit set
Power-on
detection circuit
S
R
F/F
Hardware standby
release detection
circuit
S
R
S
F/F
Watch-dog timer
reset generating
detection circuit
External reset
request detection
circuit
R
F/F
S
R
F/F
S
R
F/F
LPMCR. RST bit
write detection circuit
WTC register
Delay
circuit
WTC register read
Internal data bus
When there are multiple reset causes, the corresponding reset cause bits in the watch-dog timer
control register are set. Therefore, if an external reset request and a watch-dog reset occur at the
same time, both the ERST and WRST bits are set to "1".
A power-on reset is an exception; while the PONR bit is "1", the values of other bits do not
indicate the correct reset causes. Therefore, design software so that the other reset cause bit
values are ignored while the PONR bit is set to "1".
Table 4.3-2 The Value of Reset Cause Bits and Reset Cause
Reset cause
PONR
STBR
WRST
ERST
SRST
Power-on
1
-
-
-
-
Hardware standby
*
1
*
*
*
Watch-dog timer
*
*
1
*
*
External pin
*
*
*
1
*
RST bit
*
*
*
*
1
*: The previous value is maintained.
The reset cause bits are only cleared by reading the watch-dog timer control register. The reset
cause bit that corresponds to the reset cause that has already been generated remains 1 even if
another reset cause is generated.
See Chapter 9 "TIMEBASE TIMER", Chapter 10 "WATCH-DOG TIMER" and Chapter 11
"WATCH TIMER" for details of the configuration and reset cause bits of the watch-dog timer
control register.
85
CHAPTER 4 CLOCK AND RESET
86
CHAPTER 5
LOW-POWER CONTORL CIRCUIT
This chapter explains the functions and operation of the low-power control circuit.
5.1 Outline of Low-Power Control Circuit
5.2 Block Diagram of Low-Power Control Circuit
5.3 Low-Power Control Circuit Registers
5.4 Status Transition for Clock Selection
87
CHAPTER 5 LOW-POWER CONTORL CIRCUIT
5.1
Outline of Low-Power Control Circuit
The low-power control circuit is mainly used in low-power consumption mode. The
intermittent CPU operation function and oscillation stabilization wait time can be set by
setting register bits.
In the overall block diagram, the low-power control circuit is a part of the clock control
circuit (see Section "1.3 Block Diagram").
■ Operation Modes of Low-Power Control Circuit
The MB90540/545 series supports the following operation modes: PLL clock mode, PLL sleep
mode, PLL timer mode, pseudo timer mode, main clock mode, main sleep mode, main timer
mode, main stop mode, subclock mode, subclock sleep mode, subclock timer mode, subclock
stop mode, and hardware standby mode as operating mode. Operation modes other than PLL
clock mode are classified as low-power modes.
■ Intermittent CPU Operation Function
The intermittent CPU operation function pauses the clock supplied to the CPU for a certain period
to delay the activation of the internal bus cycle when an internal register, internal memory (ROM,
RAM, I/O, or resource memory), or external bus is accessed. The CPU execution speed is
decreased while a high-speed clock is supplied to internal resources, enabling processing with
less power consumed. The CG1 and CG0 bits of the low power consumption mode control
register (LPMCP) are used to select the cycle count for pausing the clock to be supplied to the
CPU.
Note that the external bus operation is performed by using the same clock signal as that used for
peripheral resources.
The instruction execution time using the intermittent CPU operation function can be obtained by
adding a compensation value to the ordinary execution time. The compensation value is obtained
by multiplying the number of accesses to a register, internal memory, or internal resource by the
cycle count for pausing.
■ Main Clock Oscillation Stabilization Wait Time
The WS1 and WS0 bits of the clock selection register (CKSCR) are used to select the main clock
oscillation stabilization wait time when stop mode is released. Select the oscillation stabilization
wait time according to the type and characteristics of the oscillation circuit and oscillation device
to be connected to X0 and X1 pins.
Reset signals other than power-on reset and hardware standby do not initialize these bits. After
power-on reset or hardware standby release is generated, these bits are initialized to 11. In that
case, the main clock oscillation stabilization wait time is about 218 counts of the source oscillation.
Note:
In the device without G-suffix, the oscillation stabilization wait time for hardware standby is
determined by WS1 and WS0 bits, and hardware standby do not initialize these bits.
88
CHAPTER 5 LOW-POWER CONTORL CIRCUIT
■ Switching between Machine Clocks
❍ Switching between main clock and PLL clock
Data is written to the MCS bit of the clock selection register (CKSCR) to switch between the main
clock and PLL clock.
When the MCS bit is changed from 1 to 0, the PLL clock takes over from the main clock after the
PLL clock oscillation stabilization wait time (213 machine clock cycles).
When the MCS bit is changed from 0 to 1, the main clock takes over from the PLL clock the next
time the edges of the PLL clock and main clock signals match (after 1 to 8 PLL clock cycles).
Rewriting to the MCS bit does not immediately change the machine clock. To manipulate a
resource that depends on the machine clock, always reference the MCM bit beforehand to check
that the machine clock has been switched.
❍ Switching between main clock and subclock
In the two clocks system parts, data is written to the SCS bit of the clock selection register
(CKSCR) to switch between the main clock and subclock.
If the SCS bit is changed from 1 to 0, the operation is switched from the main clock to subclock
synchronizing the subclock (approx. 130 µs).
If the SCS bit is changed from 0 to 1, the operation is switched from the subclock to the main
clock after the main clock oscillation stabilization wait time.
Rewriting to the SCS bit does not immediately change the machine clock. Manipulate a resource
after the machine clock operation is checked.
However, subclocks can not be used in the single clock (system) parts.
Note:
When subclock mode is returned to main clock mode using an external reset pin (RST pin), input "L"
level for at least 2 machine cycles of the subclock.
❍ Initializing the machine clock
The MCS bit is not initialized by a reset using an external pin or RST bit. These bits are initialized
to 1 by any other reset.
Note:
When the power is turned on or hardware standby mode or stop mode is released, the subclock
oscillation stabilization time (about 2 seconds) is generated. In the meantime, when switching from the
main clock mode to the subclock mode, the oscillation stabilization time is generated. In attempting to
switch the clock mode, do not attempt to switch to another clock mode or low-power consumption mode
until the first switching is completed. The MCM and SCM bits of the clock selection register (CKSCR)
indicate that switching is completed. If the mode is switched to another clock mode or low-powerconsumption mode before completion of switching, the mode may not be switched.
■ PLL Clock Multiplication Function
The PLL clock multiplication factor can be selected from 1, 2, 3, and 4 by setting the CS1 and
CS0 bits.
89
CHAPTER 5 LOW-POWER CONTORL CIRCUIT
5.2
Block Diagram of Low-Power Control Circuit
This section contains a block diagram of the low-power control circuit.
■ Block Diagram of Low-Power Control Circuit
Figure 5.2-1 Block Diagram of Low-Power Control Circuit and Clock Generator
CKSCR
SCM
SCS
Subclock
switch control
Dividing by 4
1/4
1/2
CKSCR
MCM
MCS
PLL multiplication
circuit
1
2
3 4
Dividing by 2
CPU
clock generation
CKSCR
CS1
CS0
LPMCR
CG1
Internal data bus
CG0
STP
TMD
Main clock
(OSC oscillation)
CPU clock
1/2 1/4
CPU
clock selector
0/9/17/33
intermittent cycle selection
Intermittent
CPU operation function
Cycle count
selection circuit
Peripheral
clock generation
LPMCR
SLP
Subclock
(OSC oscillation)
SCM
Peripheral clock
SLEEP
Standby control
circuit
Main clock OSC stop
MSTP
Subclock OSC stop
HST STOP
RST Release activation
HST pin
Interrupt request or RST
CKSCR
WS1
WS0
Oscillation
stabilization
wait time
selector
210
213
215
217
1/2
Clock input
*
Timebase timer
212 214 216 219
LPMCR
SPL
SSR
LPMCR
RST
Pin high-impedance control circuit
Pin HI-Z
Self-refresh control circuit
Self refresh
Internal reset
generation circuit
RST pin
Internal RST
To watch-dog timer
WDGRST
*: 218 at power-on
90
CHAPTER 5 LOW-POWER CONTORL CIRCUIT
5.3
Low-Power Control Circuit Registers
A low-power control circuit has the following two registers:
• Low-power Consumption mode control register
• Clock selection register
■ Low Power Mode Control Register
Figure 5.3-1 shows the bit configuration of the low-power control circuit registers.
Figure 5.3-1 Low-Power Control Circuit Registers
Low-Power Consumption Mode Control Register
7
6
5
4
3
2
1
0
STP
SLP
SPL
RST
TMD
CG1
CG0
Reserved
Read/write→
(W)
(W)
(R/W)
(W)
(W)
(R/W)
(R/W)
(-)
Initial value→
(0)
(0)
(0)
(1)
(1)
(0)
(0)
(0)
Address: 0000A0H
←Bit No.
LPMCR
Clock selection register
15
14
13
12
11
10
9
8
SCM
MCM
WS1
WS0
SCS
MCS
CS1
CS0
Read/write→
(R)
(R)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value→
(1)
(1)
(1)
(1)
(1)
(1)
(0)
(0)
Address: 0000A1H
←Bit No.
CKSCR
91
CHAPTER 5 LOW-POWER CONTORL CIRCUIT
5.3.1
Low-Power Consumption Mode Control Register (LPMCR)
This section explains the configuration and bit functions of the low-power consumption
mode control register (LPMCR).
■ Low-Power Consumption Mode Control Register (LPMCR)
Figure 5.3-2 shows the bit configuration of the low-power Consumption mode control register
(CPMCR).
Figure 5.3-2 Low-Power Consumption Mode Control Register (CPMCR)
Address: 0000A0H
7
6
5
4
3
2
1
0
STP
SLP
SPL
RST
TMD
CG1
CG0
Reserved
Read/write→
(W)
(W)
(R/W)
(W)
(W)
(R/W)
(R/W)
(-)
Initial value→
(0)
(0)
(0)
(1)
(1)
(0)
(0)
(0)
←Bit No.
LPMCR
[bit7] STP
Writing "1" to this bit starts pseudo timer mode (CKSCR. MCS=0 and SCS=1) or stop mode
(CKSCR. MCS=1 or SCS=0). Writing "0" performs no operation. This bit is cleared to "0" by a
reset, timer mode release, or stop mode release. This is a write-only bit. The value read from
this bit is always "0".
[bit6] SLP
Writing "1" to this bit starts sleep mode. Writing "0" performs no operation. This bit is cleared
to "0" by a reset, sleep mode release, or stop mode release.
Writing "1" to the STP and SLP bits simultaneously starts timer mode or pseudo timer mode.
This is a write-only bit. The value read from this bit is always "0".
[bit5] SPL
When "0" is written to this bit, the external pin level in timer mode, pseudo timer mode, or stop
mode is maintained. When "1" is written to this bit, the external pin in timer mode, pseudo
timer mode, or stop mode is set to high impedance. This bit is cleared to "0" by a reset.
[bit4] RST
Writing "0" to this bit generates internal reset signals for three machine cycles. Writing "1"
performs no operation. "1" is always read from this bit.
[bit3] TMD
Two clocks system:
Writing "0" to this bit starts timer mode. Writing "1" performs no operation. This bit is
cleared to "1" by a reset, timer mode release, or stop mode release. This is a write-only bit.
The value read from this bit is always "1".
Single clock (system):
Always write "1".
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CHAPTER 5 LOW-POWER CONTORL CIRCUIT
[bit2 and bit1] CG1 and CG0
These bits are used to set the clock pause cycle count during intermittent CPU operation.
These bits are initialized to "00" upon a reset by power-on, hardware standby, or watch-dog.
These bits are not initialized by any other type of reset.
Table 5.3-1 lists the CG bit setting.
Table 5.3-1 CG Bit Setting.
CG1
CG0
CPU clock pause cycle count
0
0
0 cycle (CPU clock = Resource clock)
0
1
9 cycles (CPU clock: Resource clock = 1:3 to 4 approx.)
1
0
17 cycles (CPU clock: Resource clock = 1:5 to 6 approx.)
1
1
33 cycles (CPU clock: Resource clock = 1:9 to 10 approx.)
[bit0] Reserved
This is a reserved bit. Always write "0".
■ Access to the Low-Power Consumption Mode Control Register
To use word length to write data to the low-power consumption mode control register, be sure
that even addresses are used. Writing with odd addresses to switch to low-power consumption
mode may cause a malfunction.
Writing data to the low-power consumption mode control register starts low-power consumption
mode (including stop mode and sleep mode). Use the instructions listed in Table 5.3-2 for this
purpose. Using other instructions to start low-power consumption mode may cause a malfunction.
Any instruction can be used to control functions other than switching from the low-power
consumption mode control register to low-power consumption mode.
To use word length to write data to the low-power consumption mode control register, be sure
that even addresses are used. Writing with odd addresses to start low-power consumption mode
may cause a malfunction.
Table 5.3-2 Instructions to Be Used for Transferring to Low-Power Consumption Mode
MOV
io,#imm8
MOV
dir,#imm8
MOV
eam,#imm8
MOV
eam,Ri
MOV
io,A
MOV
dir,A
MOV
addr16,A
MOV
eam,A
MOV
@RLi+disp8,A
MOVW io,#imm16
MOVW dir,#imm16
MOVW eam,#imm16
MOVW eam,RWi
MOVW io,A
MOVW dir,A
MOVW addr16,A
MOVW eam,A
SETB io:bp
SETB dir:bp
SETB addr16:bp
CLRB io:bp
CLRB dir:bp
CLRB addr16:bp
MOVW @RLi+disp8,A
93
CHAPTER 5 LOW-POWER CONTORL CIRCUIT
5.3.2
Clock Selection Register (CKSCR)
This section explains the configuration and bit functions of the clock selection register
(CKSCR).
■ Clock Selection Register (CKSCR)
Figure 5.3-2 shows the bit configuration of the clock selection register (CKSCR).
Figure 5.3-3 Clock Selection Register (CKSCR)
15
14
13
12
11
10
9
8
SCM
MCM
WS1
WS0
SCS
MCS
CS1
CS0
Read/write→
(R)
(R)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value→
(1)
(1)
(1)
(1)
(1)
(1)
(0)
(0)
Address: 0000A1H
←Bit No.
CKSCR
[bit15] SCM
Two clocks system:
This bit indicates whether the main clock or subclock is selected as the machine clock. When
this bit is set to "0", the subclock is selected. When this bit is set to "1", the main clock is
selected. When SCS=1 and SCM=0, the system is in the main clock oscillation stabilization
wait time.
Writing this bit has no effect on operation.
[bit14] MCM
This bit indicates whether the main clock or PLL clock is selected as the machine clock. "0"
indicates that the PLL clock is selected, and "1" indicates that the main clock is selected.
When MCS=0 and MCM=1, the system is in the PLL clock oscillation stabilization wait time.
The PLL clock oscillation stabilization wait time is fixed to 213 main clock cycles.
Writing this bit has no effect on operation.
[bit13 and bit12] WS1 and WS0
The WS1 and WS0 bits are used to specify the oscillation stabilization wait time when stop
mode is released. Specify the oscillation stabilization time according to the type and
characteristics of the oscillation circuits and oscillation devices connected to the X0 and X1
pins.
These bits are not initialized by a reset except a power-on reset.* At power-on reset, "11" is
initialized. Therefore, at power-on reset, the oscillation stabilization wait time is about 218
counts of source oscillation. These bits can be read and written.
*: In case of the device with G-suffix, these bits are also initialized by a reset of hardware
standby in subclock mode.
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CHAPTER 5 LOW-POWER CONTORL CIRCUIT
Table 5.3-3 lists the WS bit setting.
Table 5.3-3 WS Bit Setting
WS1
WS0
Oscillation stabilization wait time (at 4 MHz source oscillation)
0
0
Approx. 256µs (210 counts of source oscillation)
0
1
Approx. 2.05 ms (213 counts of source oscillation)
1
0
Approx. 8.19 ms (215 counts of source oscillation)
1
1
Approx. 32.77 ms (217 counts of source oscillation)
Approx. 65.54 ms (218 counts of source oscillation) at power-on reset only
[bit11] SCS
Two clocks system:
This bit is used to select the main clock or subclock as the machine clock. Writing "0" selects
the subclock. Writing "1" selects the main clock. When this bit is set to "1", writing "0" switches
to subclock mode in synchronized with subclock. When this bit is set to "0", writing "1" the
oscillation stabilization wait time for main clock is generated and then the timebase timer is
cleared automatically. When both SCS bit and MCS bit are "0", SCS bit has priority and
subclock is selected.
This bit is initialized to "1" by a power-on, hardware standby, watch-dog, external, or software
reset.
Single clock (system):
Always write "1".
[bit10] MCS
This bit is used to select the main clock or PLL clock as the machine clock. Writing "0" selects
the PLL clock and writing "1" selects the main clock. When this bit is updated from "1" to "0",
the PLL clock oscillation stabilization wait period is created by automatically clearing the
timebase timer. The oscillation stabilization wait time for the PLL clock is fixed to 213 main
clock cycles.
When the main clock is selected, the operation clock is generated by dividing the oscillation
clock by two. (The operation clock is 2 MHz at 4 MHz source oscillation.)
When the MCS bit is updated from "0" to "1", the main clock takes over from the PLL clock
when the edges of the main clock and PLL clock match (after about 1 to 8 PLL clock cycles).
Writing to the MCS bit does not immediately change the machine clock. To use a resource
that depends on the machine clock, always reference the MCM bit beforehand to check
whether the machine clock has been changed.
95
CHAPTER 5 LOW-POWER CONTORL CIRCUIT
[bit9 and bit8] CS1 and CS0
These bits determine the multiplication factor of the PLL clock. These bits are not initialized by
an external pin, RST bit, watch-dog timer or hardware standby* reset. These bits are initialized
to "00B" by only a power-on reset.
*: In case of the device with G-suffix, these bits are also initialized by a hardware standby in
subclock mode.
When the MCS bit is "0", write is disabled. Write "1" to the MCS bit (main clock mode), then
update the CS bits. These bits can be read and written to.
Table 5.3-4 lists the settings of the CS bits.
Table 5.3-4 CS Bit Setting
CS1
CS0
Machine clock (at 4 MHz source oscillation)
0
0
4 MHz (Operation frequency = OSC oscillation clock)
0
1
8 MHz (Operation frequency = OSC oscillation clock × 2)
1
0
12 MHz (Operation frequency = OSC oscillation clock × 3)
1
1
16 MHz (Operation frequency = OSC oscillation clock × 4)
Note:
When the operating voltage is 5 V, the source oscillation can be between 3 MHz and 16MHz. Since
the highest operating frequency for the CPU and peripheral resource circuits is 16 MHz, however,
normal operation is not guaranteed if a multiplication factor resulting in a higher frequency than 16
MHz is specified. For example, if the external clock frequency is 16 MHz, only 1 can be specified as
the multiplication factor.
The lowest operating frequency of the VCO oscillation is 4 MHz, and an oscillation below 4 MHz
must not be specified.
96
CHAPTER 5 LOW-POWER CONTORL CIRCUIT
5.4
Status Transition for Clock Selection
This section explains the status transitions for clock selection.
■ Status Transition for Clock Selection
Figure 5.4-1 Status Transition Diagram 1 for Clock Selection (Two Clocks System Parts No.1)
Power on
Main
SCS=1, MCS=1
SCM=1, MCM=1
CS1/0=XXB
Subclock
PLLx
SCS=1, MCS=0
SCM=0, MCM=1
CS1/0=XXB
subclock
Main
SCS=0, MCS=x
SCM=1
SCM=1
PLLx
Main
SCS=1, MCS=0
SCM=1, MCM=1
CS1/0=XXB
PLL1
main
SCS=0 or MCS=1
SCM=1, MCM=0
CS1/0=00B
PLL1 multiplication
SCS=1, MCS=0
SCM=1, MCM=0
CS1/0=00B
main
PLL2
SCS=0 or MCS=1
SCM=1, MCM=0
CS1/0=01B
PLL2 multiplication
SCS=1, MCS=0
SCM=1, MCM=0
CS1/0=01B
PLL3
main
SCS=0 or MCS=1
SCM=1, MCM=0
CS1/0=10B
PLL3 multiplication
SCS=1, MCS=0
SCM=1, MCM=0
CS1/0=10B
PLL4
main
SCS=0 or MCS=1
SCM=1, MCM=0
CS1/0=11B
PLL4 multiplication
SCS=1, MCS=0
SCM=1, MCM=0
CS1/0=11B
MCS bit clear and SCS bit set
PLL clock oscillation stabilization wait termination and CS1/0=00B
PLL clock oscillation stabilization wait termination and CS1/0=01B
PLL clock oscillation stabilization wait termination and CS1/0=10B
PLL clock oscillation stabilization wait termination and CS1/0=11B
MCS bit set or SCS bit clear
Synchronization timing between PLL clock and main clock and SCS=1
Synchronization timing between PLL clock and main clock and SCS=0
Main clock oscillation stabilization wait termination and MCS=0
97
CHAPTER 5 LOW-POWER CONTORL CIRCUIT
Figure 5.4-2 Status Transition Diagram 2 for Clock Selection (Two Clocks System Parts No.2)
Power on
Main
SCS=1, MCS=1
SCM=1
MCM=1
subclock
PLLx
SCS=0, MCS=x
SCM=1, MCM=0
CS1/0=XXB
subclock
Main
SCS=0
SCM=1
MCM=1
subclock
SCS=1
SCM=0
MCM=1
Main
Main
PLLx
SCS=1, MCS=0
SCM=1, MCM=1
CS1/0=XXB
SCS bit clear
Subclock edge detection timing
SCS bit set
Main clock oscillation stabilization wait termination and MCS=1
Synchronization timing between PLL clock and main clock and SCS=0
Main clock oscillation stabilization wait termination and MCS=0
98
subclock
SCS=0
SCM=0
MCM=1
CHAPTER 5 LOW-POWER CONTORL CIRCUIT
Figure 5.4-3 Clock Selection Status Transition 3 (One-way Item)
Power-on
Main
SCS = 1, MCS = 1
SCM = 1, MCM = 1
CS1/0 = XXB
Main
PLLx
SCS = 1, MCS = 0
SCM = 1, MCM = 1
CS1/0 = XXB
PLL1 multiplication
Main
SCS = 1, MCS = 1
SCM = 1, MCM = 0
CS1/0 = 00B
PLL1 multiplication
SCS = 1, MCS = 0
SCM = 1, MCM = 0
CS1/0 = 00B
PLL2 multiplication
Main
SCS = 1, MCS = 1
SCM = 1, MCM = 0
CS1/0 = 01B
PLL2 multiplication
SCS = 1, MCS = 0
SCM = 1, MCM = 0
CS1/0 = 01B
PLL3 multiplication
Main
SCS = 1, MCS = 1
SCM = 1, MCM = 0
CS1/0 = 10B
PLL3 multiplication
SCS = 1, MCS = 0
SCM = 1, MCM = 0
CS1/0 = 10B
PLL4 multiplication
Main
SCS = 1, MCS = 1
SCM = 1, MCM = 0
CS1/0 = 11B
PLL4 multiplication
SCS = 1, MCS = 0
SCM = 1, MCM = 0
CS1/0 = 11B
MCS bit clear and SCS bit clear.
PLL clock oscillation stabilization wait termination and CS1/0 = 00B.
PLL clock oscillation stabilization wait termination and CS1/0 = 01B.
PLL clock oscillation stabilization wait termination and CS1/0 = 10B.
PLL clock oscillation stabilization wait termination and CS1/0 = 10B.
MCS bit set.
Synchronous timing between PLL clock and main clock and SCS = 1.
Note:
In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power
consumption mode until the first switching is completed. The MCM and SCM bits of the clock
selection register (CKSCR) indicate that switching is completed. If the mode is switched to another
clock mode or low-power-consumption mode before completion of switching, the mode may not be
switched.
99
CHAPTER 5 LOW-POWER CONTORL CIRCUIT
100
CHAPTER 6
LOW-POWER CONSUMPTION MODES
This chapter explains the functions and operation of the low-power consumption
modes.
6.1 Low-Power Consumption Modes
6.2 Status Transitions in Low-Power Consumption Mode
6.3 Status Transition Diagram for Low-Power Consumption Mode
101
CHAPTER 6 LOW-POWER CONSUMPTION MODES
6.1
Low-Power Consumption Modes
The MB90540/545 supports the following operation modes:
• PLL clock mode
• PLL sleep mode
• PLL timer mode
• Pseudo timer mode
• Main clock mode
• Main sleep mode
• Main timer mode
• Main stop mode
• Subclock mode
• Sub-sleep mode
• Sub-timer mode
• Sub-stop mode
• Hardware standby mode
• Intermittent CPU operation function
Modes other than PLL clock mode are classified as low-power consumption modes.
■ Low-Power Consumption Modes
❍ Main clock mode and main sleep mode
The main clock (main OSC oscillation clock) and the subclock (subclock OSC oscillation clock)
are used for operation.
The operation clock is generated by dividing the main clock signal by two, and the subclock signal
(subclock OSC oscillation clock) is used as the timer clock signal while the PLL clock (VCO
oscillation clock) is stopped.
❍ Subclock mode and sub-sleep mode
Only the subclock is used for operation. The operation clock is generated by the subclock signal
by four, and the main clock and PLL clock are stopped.
❍ PLL sleep mode and main sleep mode
Only the CPU operation clock is stopped. Clocks other than the CPU clock are used for
operation.
❍ Pseudo timer mode
Only the watch timer and timebase timer are used for operation.
102
CHAPTER 6 LOW-POWER CONSUMPTION MODES
❍ PLL timer mode, main timer mode, and sub-timer mode
Only the watch timer is used for operation. Only the subclock signal is used for operation and the
main clock and PLL clock are stopped. PLL timer mode, main timer mode, and sub-timer mode
are different in that the operation modes at return by interrupts are PLL clock mode, main clock
mode, and subclock mode. The operation in the timer modes is the same.
❍ Main stop mode, sub-stop mode, and hardware standby mode
Oscillation is stopped and data can be held at the lowest power consumption level. Main stop
mode and sub-stop mode are different in that the operation mode at return by interrupts is main
clock mode and subclock mode. Operation in the stop modes is the same.
❍ Intermittent CPU operation function
The intermittent CPU operation function causes intermittent operation of the clock supplied to the
CPU when an internal register, internal memory, internal resource, or external bus is accessed.
The CPU execution speed is decreased while a high-speed clock is supplied to internal
resources, enabling processing with little power consumed.
Note:
In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power
consumption mode until the first switching is completed. The MCM and SCM bits of the clock
selection register (CKSCR) indicate that switching is completed. If the mode is switched to another
clock mode or low-power-consumption mode before completion of switching, the mode may not be
switched.
103
CHAPTER 6 LOW-POWER CONSUMPTION MODES
■ Operation Status of Low-Power Consumption Mode
Table 6.1-1 and Table 6.1-2 lists the chip operation status in each operation mode.
Table 6.1-1 Operation Status in Low-Power Consumption Mode (Two Clocks System Parts)
Transition
condition
Subclock
oscillation
Main
oscillation
Machine
clock
CPU
Peripheral
Pin
Subclock
SCS=0
MCS=x
Operating
Stopped
Operating
Operating
Operating
Operating
External
reset
Interrupt
Subsleep
SCS=0
MCS=x
SLP=1
Operating
Stopped
Operating
Stopped
Operating
Operating
External
reset
Interrupt
Main
sleep
SCS=1
MCS=1
SLP=1
Operating
Operating
Operating
Stopped
Operating
Operating
External
reset
Interrupt
PLL
sleep
SCS=1
MCS=0
SLP=1
Operating
Operating
Operating
Stopped
Operating
Operating
External
reset
Interrupt
Pseudo
timer
(SPL=0)
SCS=1
MCS=0
STP=1
Operating
Operating
Stopped
Stopped
Stopped
Previous
status
held
External
reset
Interrupt *1
Pseudo
timer
(SPL=1)
SCS=1
MCS=0
STP=1
Operating
Operating
Stopped
Stopped
Stopped
HI-Z
External
reset
Interrupt *1
Timer
(SPL=0)
SCS=x
MCS=x
TMD=0
Operating
Stopped
Stopped
Stopped
Stopped
Previous
status
held
External
reset
Interrupt *2
Timer
(SPL=1)
SCS=x
MCS=x
TMD=0
Operating
Stopped
Stopped
Stopped
Stopped
HI-Z
External
reset
Interrupt *2
Stop
(SPL=0)
MCS=1
or SCS=0
STP=1
Stopped
Stopped
Stopped
Stopped
Stopped
Previous
status
held
External
reset
Interrupt *3
Stop
(SPL=1)
MCS=1
or SCS=0
STP=1
Stopped
Stopped
Stopped
Stopped
Stopped
HI-Z
External
reset
Interrupt *3
Hardware
standby
HST=L
Stopped
Stopped
Stopped
Stopped
Stopped
HI-Z
HST=H
Status
*1: Watch timer, timebase timer, and external interrupt
*2: Watch timer and external interrupt
*3: External interrupt
104
Release
method
CHAPTER 6 LOW-POWER CONSUMPTION MODES
Table 6.1-2 Operation Status in Low-Power Consumption Mode (Single Clock (system) Parts)
Transition
condition
Subclock
oscillation
Main
clock
oscillation
Machine
clock
CPU
Peripheral
s
Pins
Release
method
Main
sleep
SCS=1
MCS=1
SLP=1
-
Operating
Operating
Stopped
Operating
Operating
External
reset
interrupt
POLL
sleep
SCS=1
MCS=0
SLP=1
-
Operating
Operating
Stopped
Operating
Operating
External
reset
interrupt
Pseudo
timer
(SPL=0)
SCS=1
MCS=0
STP=1
-
Operating
Stopped
Stopped
Stopped
Retained
External
reset
interrupt *1
Pseudo
timer
(SPL=1)
SCS=1
MCS=0
STP=1
-
Operating
Stopped
Stopped
Stopped
Hi-z
External
reset
interrupt *1
Stop
(SPL=0)
SCS=1
MCS=1
STP=1
-
Stopped
Stopped
Stopped
Stopped
Retained
External
reset
interrupt *2
Stop
(SPL=1)
SCS=1
MCS=1
STP=1
-
Stopped
Stopped
Stopped
Stopped
Hi-z
External
reset
interrupt *2
Hardware
standby
HST=L
-
Stopped
Stopped
Stopped
Stopped
Hi-z
HST=H
*1: Timebase timer and external interrupt
*2: External interrupt
105
CHAPTER 6 LOW-POWER CONSUMPTION MODES
6.1.1
Sleep Mode
In sleep mode, only the clock supplied to the CPU is stopped. As a result, the CPU
terminates while internal peripheral resource circuits keep operating.
■ Transition to Sleep Mode
Writing "1" to the SLP bit, "1" to the TMD bit, and "0" to the STP bit of low-power consumption
mode control register (LPMCR) starts transition to sleep mode.
If an interrupt request has been issued when "1" is written to the SLP bit, the standby control
circuit does not enter sleep mode. Therefore, the CPU executes the next instruction if the
interrupt cannot be accepted, or immediately branches to the interrupt processing routine if the
interrupt can be accepted.
In sleep mode, the values of dedicated registers such as the accumulator and the internal RAM
are maintained.
■ Releasing Sleep Mode
The standby control circuit releases sleep mode in the event of a reset input or an interrupt
request. If sleep mode is released by a reset, the reset status takes effect after sleep mode is
released.
If a peripheral circuit and internal resource issues an interrupt request of a higher interrupt level
than 7 in sleep mode, the standby control circuit releases sleep mode. After sleep mode is
released, processing is handled as normal interrupt processing. The CPU executes the
instruction that is not in the standby write pending state, then executes interrupt processing when
the interrupt can be accepted according to the I flag in the condition code register (CCR), interrupt
level mask register (ILM), and interrupt control register (ICR). If the interrupt cannot be accepted,
processing continues with the instruction following the instruction that was placed in sleep mode.
Note:
When subclock mode is returned to main clock mode using an external reset pin (RST pin), input
level "L" for at least 2 machine cycles of the subclock.
106
CHAPTER 6 LOW-POWER CONSUMPTION MODES
6.1.2
Pseudo Timer Mode
Pseudo timer mode stops operations other than source oscillation (main and subclock),
the watch timer, and the timebase timer, causing almost all functions of the MB90540/
545 to stop.
■ Transition to Pseudo Timer Mode
Writing "1" to the SCS bit and "0" to the MCS bit of the clock selection register (CKSCR) and "1"
to the TMD bit and "1" to the STP bit of low-power consumption mode control register (LPMCR)
starts transition to pseudo timer mode.
The SPL bit of the low-power consumption mode control register (LPMCR) can be used to control
whether the I/O pin is maintained at the immediately preceding status or at high impedance in
pseudo timer mode.
If an interrupt request has been issued when "1" is written to the STP bit, the standby control
circuit does not enter pseudo timer mode.
In pseudo timer mode, the values of special registers such as the accumulator and the internal
RAM register are maintained.
■ Releasing Pseudo Timer Mode
The standby control circuit releases pseudo timer mode when a reset signal is input or an
interrupt request is issued. If pseudo timer mode is released by a reset cause, the reset status
takes effect after pseudo timer mode is released.
To return from pseudo timer mode, the standby control circuit initially releases pseudo timer
mode, then enters the PLL clock oscillation stabilization wait state. When the release of pseudo
timer mode starts by an interrupt request, the reset sequence is performed using the main clock.
If a peripheral resource circuit issues an interrupt request of a higher interrupt level than 7, the
standby control circuit releases pseudo timer mode. After pseudo timer mode is released,
processing is handled as normal interrupt processing. The CPU executes the instruction that both
is not in the write pending state and follows the standby write instruction, then executes interrupt
processing when the interrupt can be accepted according to the I flag in the condition code
register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR). If the
interrupt cannot be accepted, processing continues with the instruction following the instruction
that was executed before transition to pseudo timer mode.
Notes: [only for MB90543G(S)/547G(S)/548G(S)]
• When pseudo timer mode is returned to main clock mode using an external reset pin (RST pin),
input level "L" for at least 100µs.
• When pseudo timer mode is returned by an interrupt, the interrupt processing is performed after
the maximum 80µs after the interrupt request is accepted.
107
CHAPTER 6 LOW-POWER CONSUMPTION MODES
6.1.3
Timer Mode
Timer mode stops operations other than subclock source oscillation and the watch
timer, causing almost all functions of the MB90540/545 to stop.
However, the timer mode cannot be used in the single clock (system) parts.
■ Transition to Timer Mode
Writing "0" to the TMD bit of the clock selection register (CKSCR) starts transition to timer mode.
The SPL bit of the low-power consumption mode control register (LPMCR) can be used to control
whether the I/O pin is maintained at the immediately preceding status or at high impedance in
pseudo timer mode.
If an interrupt request has been issued when "1" is written to the TMD bit, the standby control
circuit does not enter timer mode.
In timer mode, the values of special registers such as the accumulator and the internal RAM
register are maintained.
■ Releasing Timer Mode
The standby control circuit releases timer mode when a reset signal is input or an interrupt
request is issued. If timer mode is released by a reset cause, the reset status takes effect after
timer mode is released.
To return from sub-timer mode, the standby control circuit initially releases timer mode, then
immediately enters subclock mode. When the release of sub-timer mode is a reset cause, the
reset sequence is performed using the subclock signal.
To return from main timer mode or PLL timer mode, the standby control circuit initially releases
timer mode, then enters the main clock oscillation stabilization wait state. When the release of
timer mode is a reset cause, the reset sequence is performed using the subclock signal.
If a peripheral resource circuit issues an interrupt request of a higher interrupt level than 7, the
standby control circuit releases timer mode. After timer mode is released, processing is handled
as normal interrupt processing. The CPU executes the instruction that both is not in the write
pending state and follows the standby write instruction, then executes interrupt processing when
the interrupt can be accepted according to the setting of I flag in the condition code register
(CCR), interrupt level mask register (ILM), and interrupt control register (ICR). If the interrupt
cannot be accepted, processing continues with following the instruction that was executed before
transition to timer mode.
Note:
When timer mode is returned to main clock mode using an external reset pin (RST pin), input level
"L" for at least 2 machine cycles of the subclock.
108
CHAPTER 6 LOW-POWER CONSUMPTION MODES
6.1.4
Stop mode
Stop mode stops source oscillation (main and subclock), causing all device functions
of the MB90540/545 to stop. Data can be maintained at the lowest power consumption
level.
■ Transition to Stop Mode
Writing "0" to the SCS bit or "1" to the MCS bit of the clock control register and "1" to the STP bit
of the low-power consumption mode control register (LPMCR) causes the standby control circuit
to enter stop mode.
The SPL bit of the low-power consumption mode control register (LPMCR) can be used to control
whether the I/O pin is maintained at the immediately preceding status or at high impedance.
If an interrupt request has been issued when "1" is written to the STP bit, the standby control
circuit does not enter stop mode.
In stop mode, the values of special registers such as the accumulator and the internal RAM
register are maintained.
■ Releasing Stop Mode
The standby control circuit releases stop mode when a reset signal is input or an interrupt is
generated. If stop mode is released by a reset cause, the reset status takes effect after stop
mode is released.
To return from sub-timer mode, the standby control circuit initially enters subclock oscillation
stabilization wait mode, then releases stop mode. When the release of stop mode is a reset
cause, the reset sequence is performed after the subclock oscillation stabilization wait time
elapses.
To return from main stop mode, the standby control circuit initially enters main clock oscillation
stabilization wait mode, then releases stop mode. When the release of stop mode is a reset
cause, the reset sequence is performed after the main clock oscillation stabilization wait time
elapses.
If a peripheral circuit or other resource issues an interrupt request of a higher interrupt level than
7 in stop mode, the MB90540/545 is released from stop mode. After sub-stop mode is released,
the subclock oscillation stabilization wait time is applied and processing is handled as normal
interrupt processing. The CPU executes the instruction that both is not in the write pending state
and follows the standby write instruction, then executes interrupt processing when the interrupt
can be accepted according to the setting of I flag in the condition code register (CCR), interrupt
level mask register (ILM), and interrupt control register (ICR). If the interrupt cannot be accepted,
processing continues with the instruction following the instruction that was executed before
transition to stop mode.
After main stop mode is released, the oscillation stabilization wait time specified in WS1 and WS0
bits of the clock selection register (CKSCR) elapses and processing is then handled as normal
interrupt processing. The CPU executes the instruction that both is not in the write pending state
and follows the standby write instruction, then branches to interrupt processing when the interrupt
can be accepted according to the I flag in the condition code register (CCR), interrupt level mask
register (ILM), and interrupt control register (ICR). If the interrupt cannot be accepted, processing
continues with following the instruction that was executed before transition to stop mode.
109
CHAPTER 6 LOW-POWER CONSUMPTION MODES
Note:
When stop mode is returned to main clock mode using an external reset pin (RST pin), input level "L"
for at least the oscillation time of the oscillator * + 4 machine cycles.
*: The oscillation time of the oscillator is the time required to reach 90% of amplitude. It takes several
to dozens of ms for crystal oscillators, hundreds of µs to several ms for FAR/ceramic oscillators,
and 0 ms for external clocks.
110
CHAPTER 6 LOW-POWER CONSUMPTION MODES
6.1.5
Hardware Standby Mode
In the hardware standby mode, oscillation is stopped and all I/O pins are set to high
impedance while the HST pin is at "L" level, regardless of other statuses (including
reset).
■ Transition to Hardware Standby Mode
The standby control circuit can be set in hardware standby mode from any status by setting the
HST pin at "L" level. In hardware standby mode, oscillation is stopped and all I/O pins are set to
high impedance while the HST pin is at "L" level, regardless of other status including reset.
In hardware standby mode, the internal RAM contents are maintained but the special registers
such as the accumulator are initialized.
■ Releasing Hardware Standby Mode
Hardware standby mode can be released only by the HST pin. When the HST pin is set at "H"
level, the standby control circuit releases hardware standby mode, enables the internal reset
signal, and enters oscillation stabilization wait status. After the oscillation stabilization wait period,
the standby control circuit releases the internal reset, and consequently the CPU starts execution
from the reset sequence.
The oscillation stabilization wait time for hardware standby mode is fixed to 218 counts of the
source oscillation for device with G-suffix, is determined by WS1 and WS0 bits of the clock
selection register for device without G-suffix.
111
CHAPTER 6 LOW-POWER CONSUMPTION MODES
6.1.6
Intermittent CPU Operation
The intermittent CPU operation function delays the activity of the internal bus cycle to
stop the clock supplied to the CPU when a register, internal memory (ROM, RAM, I/O or
resource), or the external bus is accessed. While a high-speed clock is supplied to
internal resources, the CPU execution speed is decreased, thus enabling processing
with little power consumed. The CG1 and CG0 bits are used to specify the cycle count
for clock stop.
External bus operation is performed using the same clock as that for the resource.
■ Intermittent CPU Operation
The instruction execution time using the intermittent CPU operation function can be obtained by
adding a compensation value to the ordinary execution time. The compensation value is obtained
by multiplying the number of accesses to a register, internal memory, internal resource, or
external bus by the cycle count for pausing.
112
CHAPTER 6 LOW-POWER CONSUMPTION MODES
6.2
Status Transitions in Low-Power Consumption Mode
In low-power consumption mode, the transition to each status is based on the condition
setting in the clock selection register or low-power consumption mode control register.
■ Transition Conditions in Low-Power Consumption Mode
The meanings of symbols used in the table and figure are explained below:
•
MCS: MCS bit (clock selection register) (PLL clock mode selected when MCS=0)
•
SCS: SCS bit (clock selection register) (subclock mode selected when SCS=0)
•
STP: STP bit (low-power consumption mode control register) (stop mode selected when
STP=1)
•
SLP: SLP bit (low-power consumption mode control register) (sleep mode selected when
SLP=1)
•
TMD: TMD bit (low-power consumption mode control register) (timer mode selected when
TMD=0)
•
MCM: MCM bit (clock selection register) (PLL clock used when MCM=0)
•
SCM: SCM bit (clock selection register) (subclock used when SCM=0)
•
SCD: Subclock oscillation stop (subclock oscillation stopped when SCD=1)
•
MCD: Main clock oscillation stop (main clock oscillation stopped when MCD=1)
•
PCD: PLL clock oscillation stop (PLL clock oscillation stopped when PCD=1)
Table 6.2-1 Transition Conditions of the Two Clocks System Parts (1/4)
Status before transition
Transition condition
Status after transition
Power-on
01 Main oscillation stabilization wait time
termination
Main mode
Main oscillation stabilization
05 Main oscillation stabilization wait time
termination
Main mode
Main mode
06 SCS=0 write
MS transition mode
07 SCS=1, MCS=0 write
MP transition mode
31 TMD=1, STP=0, SLP=1 write
Main sleep mode
32 TMD=0 write
Main watch transition mode
33 TMD=1, STP=1 write
Main stop
113
CHAPTER 6 LOW-POWER CONSUMPTION MODES
Table 6.2-1 Transition Conditions of the Two Clocks System Parts (2/4)
Status before transition
PLL mode
Subclock mode
PM transition mode
SM transition mode
MP transition mode
114
Transition condition
Status after transition
21 SCS=0 write
PS transition mode
20 SCS=1, MCS1 write
PM transition mode
59 TMD=1, STP=0, SLP=1 write
PLL sleep mode
58 TMD=0 write
PLL watch transition P
57 TMD=1, STP=1 write
Pseudo watch transition mode
10 SCS=1, MCS=1 write
SM transition mode
12 SCS=1, MCS=0 write
SP transition mode
11 Reset activation
Main oscillation stabilization
42 TMD=1, STP=0, SLP=1 write
Sub-sleep mode
43 TMD=0 write
Sub-timer mode
44 TMD=1, STP=1 write
Sub-stop mode
13 PLL -> main switch wait termination
Main mode
38 TMD=1, STP=0, SLP=1 write
PM transition sleep mode
39 TMD=0 write and PLL -> main switch wait
termination
Main watch transition mode
40 TMD=1, STP =1 write and PLL -> main
switch wait termination
Main stop mode
02 Main oscillation stabilization wait time
termination
Main mode
03 Reset activation or interrupt
Main oscillation stabilization
04 SCS=0 write
Subclock mode
27 TMD=1, STP=0, SLP=1 write
SM transition sleep mode
28 TMD=0 write and main oscillation
stabilization wait time termination
Main timer mode
29 TMD=1, STP=1 write and main oscillation
stabilization wait time termination
Main stop mode
16 PLL oscillation stabilization wait time
termination
PLL mode
14 SCS=1, MCS=1 write
Main mode
15 SCS=0 write
MS transition mode
68 TMD=1, STP=0, SLP=1 write
MP transition sleep mode
70 TMD=0 write
PLL watch transition mode
69 TMD=1, STP=1 write
Pseudo timer mode
CHAPTER 6 LOW-POWER CONSUMPTION MODES
Table 6.2-1 Transition Conditions of the Two Clocks System Parts (3/4)
Status before transition
SP transition mode
MS transition mode
Transition condition
Status after transition
17 Main oscillation stabilization wait time
termination
MP transition mode
18 MCS=1 write
SM transition mode
19 Reset activation
Main oscillation stabilization
75 TMD=1, STP=0, SLP=1 write
SP transition sleep mode
76 TMD=0 write
PLL timer mode
78 TMD=1, STP=1 write and main oscillation
stabilization wait time termination
Pseudo timer mode
09 Main -> subclock switch wait termination
Subclock mode
08 Reset activation
Main mode
51 TMD=1, STP=0, SLP=1 write
MS transition sleep mode
52 TMD=0 write and main -> subclock switch
wait termination
Sub-timer mode
53 TMD=1, STP=1 write and main -> subclock Sub-stop mode
switch wait termination
PS transition mode
23 PLL -> main clock switch wait termination
MS transition mode
22 SCS=1 write
PM transition mode
56 TMD=1, STP=0, SLP=1 write
PS transition sleep mode
Main sleep
26 Interrupt or reset activation
Main mode
SM transition sleep
24 Main oscillation stabilization wait time
termination
Main sleep
25 Interrupt or reset activation
SM transition mode
34 PLL -> main clock switch wait termination
Main sleep mode
35 Interrupt or reset activation
PM transition mode
PLL sleep mode
63 Interrupt or reset activation
PLL mode
MP transition sleep
66 PLL oscillation stabilization wait time
termination
PLL sleep mode
67 Interrupt or reset activation
MP transition mode
73 Main oscillation stabilization wait time
termination
MP transition sleep
74 Interrupt or reset activation
SP transition mode
Sub-sleep
46 Interrupt or reset activation
Subclock mode
MS transition sleep
49 Main -> subclock switch wait termination
Sub-sleep mode
50 Interrupt or reset activation
MS transition mode
PM transition sleep
SP transition sleep
115
CHAPTER 6 LOW-POWER CONSUMPTION MODES
Table 6.2-1 Transition Conditions of the Two Clocks System Parts (4/4)
Status before transition
PS transition sleep
Transition condition
Status after transition
54 PLL -> main clock switch wait termination
MS transition sleep mode
55 Interrupt or reset activation
PS transition mode
Main watch
30 Interrupt or reset activation
SM transition mode
Main watch transition
36 Main -> subclock switch wait termination
Main timer
37 Interrupt or reset activation
Main mode
PLL watch
77 Interrupt or reset activation
SP transition mode
PLL watch transition M
72 Main -> subclock switch wait termination
PLL watch
71 Interrupt or reset activation
MP transition mode
65 PLL -> main clock switch wait termination
PLL watch transition M
64 Interrupt or reset activation
PLL mode
Subclock watch
47 Interrupt or reset activation
Subclock mode
Main stop
41 Interrupt or reset activation
Main oscillation stabilization
Pseudo watch
62 Interrupt or reset activation
MP transition mode
Pseudo watch transition
61 PLL -> main clock switch wait termination
Pseudo timer mode
60 Interrupt or reset activation
PLL mode
48 Interrupt
Subclock oscillation stabilization
79 Reset activation
Main oscillation stabilization
45 Subclock oscillation stabilization wait time
termination
Subclock mode
80 Reset activation
Main oscillation stabilization
PLL watch transition P
Sub-stop
Subclock oscillation
stabilization
Notes:
• When stop mode is returned to main clock mode using an external reset pin (RST pin), input level
"L" for at least the oscillation time of the oscillator * + 4 machine cycles.
*: The oscillation time of the oscillator is the time required to reach 90% of amplitude. It takes
several to dozens of ms for crystal oscillators, hundreds of µs to several ms for FAR/ceramic
oscillators, and 0 ms for external clocks.
• When subclock mode, sleep mode or timer mode is returned to main clock mode using an
external reset pin (RST pin), input level "L" for at least 2 machine cycles of the subclock.
116
CHAPTER 6 LOW-POWER CONSUMPTION MODES
Table 6.2-2 Transition Conditions of the Single Clock (System) Parts
Status before
transition
Transition condition
Status after transition
Power-on
01
Main oscillation stabilization wait time end
Main mode
Main oscillation
stabilization
05
Main oscillation stabilization wait time end
Main mode
07
SCS=1, MCS=0 write
MP transition mode
31
TMD=1, STP=0, SLP=1 write
Main sleep
33
TMD=1, STP=1 write
Main stop
20
SCS=1, MCS=1 write
PM transition mode
59
TMD=1, STP=0, SLP=1 write
PLL sleep
13
PLL-->main switching timing wait end
Main mode
38
TMD=1, STP=0, SLP=1 write
PM transition sleep
40
TMD=1, STP=1 write & PLL to main switching
timing wait end
Main stop
16
PLL oscillation stabilization wait time end
PLL mode
14
SCS=1, MCS=1 write
Main mode
68
TMD=1, STP=0, SLP=1 write
MP transition sleep
69
TMD=1, STP=1 write
Pseudo timer mode
Main sleep
26
Interrupt or reset activation
Main mode
PM transition sleep
34
PLL-->main clock switching timing wait end
Main sleep
35
Interrupt or reset activation
PM transition mode
PLL sleep
63
Interrupt or reset activation
PLL mode
MP transition sleep
66
PLL oscillation stabilization wait time end
PLL sleep
67
Interrupt or reset activation
MP transition mode
Main stop
41
Interrupt or reset activation
Main oscillation
stabilization
Pseudo timer
62
Interrupt or reset activation
MP transition mode
Pseudo timer transition
61
PLL-->main clock switching timing wait end
Pseudo timer mode
60
Interrupt or reset activation
PLL mode
Main mode
PLL mode
PM transition mode
MP transition mode
Notes:
When stop mode is returned to main clock mode using an external reset pin (RST pin), input
level "L" for at least the oscillation time of the oscillator * + 4 machine cycles.
*: The oscillation time of the oscillator is the time required to reach 90% of amplitude. It takes
several to dozens of ms for crystal oscillators, hundreds of µs to several ms for FAR/ceramic
oscillators, and 0 ms for external clocks.
117
CHAPTER 6 LOW-POWER CONSUMPTION MODES
6.3
Status Transition Diagram for Low-Power Consumption
Mode
Figure 6.3-1 to Figure 6.3-7 are status transition diagrams.
For simplification, the status transition diagrams show events that occur
simultaneously as stepwise transitions. In actuality, status transition takes place
instantaneously.
■ Status Transition Diagram for Low-Power Consumption Mode (Two Clocks System Parts)
For simplification, the status transition diagram shows events that occur simultaneously as
stepwise transitions. In actuality, however, status transitions take place instantaneously.
In the status transition diagram, if MSC=1 and SLP=1 are set simultaneously in PLL clock mode,
a transition to PM transition mode is followed by a transition to PM transition sleep. In actuality,
however, a transition from PLL clock mode to PM transition sleep takes place instantaneously. If
reset is activated in sub-sleep mode, a transition to subclock mode is followed by a transition to a
main oscillation stabilization time. In actuality, however, a transition from sub-sleep mode to a
main oscillation stabilization time takes place.
Notes:
• When stop mode is returned to main clock mode using an external reset pin (RST pin), input level
"L" for at least the oscillation time of the oscillator * + 4 machine cycles.
*: The oscillation time of the oscillator is the time required to reach 90% of amplitude. It takes
several to dozens of ms for crystal oscillators, hundreds of µs to several ms for FAR/ceramic
oscillators, and 0 ms for external clocks.
• When subclock mode, sleep mode and timer mode is returned to main clock mode using an
external reset pin (RST pin), input level "L" for at least 2 machine cycles of the subclock.
118
CHAPTER 6 LOW-POWER CONSUMPTION MODES
Figure 6.3-1 Status Transition Diagram A for Low-Power Consumption Mode (Two Clocks System Parts)
Power-on reset
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=1
SCM=1,MCM=1,
SCD=0, MCD=0,
PCD=1
SM transition mode
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=1
SCM=0,MCM=1,
SCD=0, MCD=0,
PCD=1
Main oscillation
stabilization time
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=1
SCM=1,MCM=1,
SCD=0, MCD=0,
PCD=1
03
04
02
01
05
10
11
Main mode
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=1
SCM=1,MCM=1,
SCD=0, MCD=0,
PCD=1
06
MS transition mode
SCS=0, MCS=x,
STP=0, SLP=0,
TMD=1
08
SCM=1,MCM=1,
SCD=0, MCD=0,
PCD=1
Subclock mode
SCS=0, MCS=x,
STP=0, SLP=0,
TMD=1
SCM=0,MCM=1,
SCD=0, MCD=1,
PCD=1
09
07
12
18
13
PM transition mode
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=1
SCM=1,MCM=0,
SCD=0, MCD=0,
PCD=1
19
15
14
MP transition mode
SCS=1, MCS=0,
STP=0, SLP=0,
TMD=1
SCM=1,MCM=1,
SCD=0, MCD=0,
PCD=0
17
SP transition mode
SCS=1, MCS=0,
STP=0, SLP=0,
TMD=1
SCM=0,MCM=1,
SCD=0, MCD=0,
PCD=1
16
23
20
PLL mode
SCS=1, MCS=0,
STP=0, SLP=0,
TMD=1
SCM=1,MCM=0,
SCD=0, MCD=0,
PCD=0
22
21
PS transition mode
SCS=0, MCS=x,
STP=0, SLP=0,
TMD=1
SCM=1,MCM=0,
SCD=0, MCD=0,
PCD=0
119
CHAPTER 6 LOW-POWER CONSUMPTION MODES
Figure 6.3-2 Status Transition Diagram B for Low-Power Consumption Mode (Two Clocks System Parts)
SM transition sleep
SCS=1, MCS=1,
STP=0, SLP=1,
TMD=1
SCM=0, MCM=1,
SCD=0, MCD=0,
PCD=1
Main sleep
SCS=1, MCS=1,
STP=0, SLP=1,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=1
24
26
25
27
31
SM transition mode
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=1
SCM=0, MCM=1,
SCD=0, MCD=0,
PCD=1
28
30
Main timer
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=0
SCM=0, MCM=1,
SCD=0, MCD=1,
PCD=1
Main mode
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=1
32
29
03
33
37
34
36
PM transition sleep
SCS=1, MCS=1,
STP=0, SLP=1,
TMD=1
SCM=1, MCM=0,
SCD=0, MCD=0,
PCD=0
05
Main oscillation
stabilization time
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=1
Main timer transition
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=0
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=1
35
38
39
PM transition mode
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=1
SCM=1, MCM=0,
SCD=0, MCD=0,
PCD=0
120
40
Main stop
SCS=1,
STP=1,
TMD=1
SCM=1,
SCD=1,
PCD=1
MCS=1,
SLP=0,
MCM=1,
MCD=1,
41
CHAPTER 6 LOW-POWER CONSUMPTION MODES
Figure 6.3-3 Status Transition Diagram C for Low-Power Consumption Mode (Two Clocks System Parts)
Subclock mode
SCS=0, MCS=x,
STP=0, SLP=0,
TMD=1
SCM=0, MCM=1,
SCD=0, MCD=1,
PCD=1
42
45
44
Subclock oscillation
stabilization time
SCS=0, MCS=x,
STP=0, SLP=0,
TMD=1
SCM=0, MCM=1,
SCD=0, MCD=1,
PCD=1
Main oscillation
stabilization time
SCS=1, MCS=x,
STP=0, SLP=0,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=1
80
43
46
48
Subclock sleep
SCS=0, MCS=x,
STP=0, SLP=1,
TMD=1
SCM=0, MCM=1,
SCD=0, MCD=1,
PCD=1
47
49
Subclock timer
SCS=0, MCS=x,
STP=0, SLP=0,
TMD=0
SCM=0, MCM=1,
SCD=0, MCD=1,
PCD=1
79
Subclock stop
SCS=0, MCS=x,
STP=1, SLP=0,
TMD=1
SCM=0, MCM=1,
SCD=1, MCD=1,
PCD=1
52
53
MS transition sleep
SCS=0, MCS=x,
STP=0, SLP=1,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=1
51
50
MS transition mode
SCS=0, MCS=x,
STP=0, SLP=0,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=1
23
54
PM transition sleep
SCS=1, MCS=x,
STP=0, SLP=1,
TMD=1
SCM=1, MCM=0,
SCD=0, MCD=0,
PCD=0
56
55
PM transition mode
SCS=0, MCS=x,
STP=0, SLP=0,
TMD=1
SCM=1, MCM=0,
SCD=0, MCD=0,
PCD=0
121
CHAPTER 6 LOW-POWER CONSUMPTION MODES
Figure 6.3-4 Status Transition Diagram D for Low-Power Consumption Mode (Two Clocks System Parts)
PLL mode
SCS=1, MCS=0,
STP=0, SLP=0,
TMD=1
SCM=1, MCM=0,
SCD=0, MCD=0,
PCD=0
57
58
60 Pseudo timer transition
SCS=1, MCS=0,
61
STP=1, SLP=0,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=0
62
Pseudo timer mode
SCS=1, MCS=0,
STP=1, SLP=0,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=1
59
63
PLL sleep
SCS=1, MCS=0,
STP=0, SLP=1,
TMD=1
SCM=1, MCM=0,
SCD=0, MCD=0,
PCD=1
64
PLL timer transition P
SCS=1, MCS=0,
STP=0, SLP=0,
TMD=0
SCM=1, MCM=0,
SCD=0, MCD=0
PCD=0
65
16
66
MP transition sleep
SCS=1, MCS=0,
STP=0, SLP=1,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=0
69
68
67
MP transition mode
SCS=1, MCS=0,
STP=0, SLP=0,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=0
70
71 PLL timer transition M
SCS=1, MCS=0,
STP=0, SLP=0,
TMD=0
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=1
78
73
SP transition sleep
SCS=1, MCS=0,
STP=0, SLP=1,
TMD=1
SCM=0, MCM=1,
SCD=0, MCD=0,
PCD=1
17
75
74
SP transition mode
SCS=1, MCS=0,
STP=0, SLP=0,
TMD=1
SCM=0, MCM=1,
SCD=0, MCD=0,
PCD=1
72
77
76
PLL timer
SCS=1, MCS=0,
STP=0, SLP=0,
TMD=0
SCM=0, MCM=1,
SCD=0, MCD=1,
PCD=1
Note:
In attempting to switch the clock mode, do not attempt to switch to another clock mode or lowpower consumption mode until the first switching is completed. The MCM and SCM bits of the
clock selection register (CKSCR) indicate that switching is completed. If the mode is switched
to another clock mode or low-power-consumption mode before completion of switching, the
mode may not be switched.
122
CHAPTER 6 LOW-POWER CONSUMPTION MODES
■ Status Transition Diagram for Low-Power Consumption Mode (Single Clock (System) Parts)
Figure 6.3-5 Status Transition Diagram 1 for Low-Power Consumption Mode (Single Clock (System) Parts)
Power-on reset
SCS=1,MCS=1
STP=0,SLP=0
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=1
Main oscillation
stabilization time
SCS=1,MCS=1
STP=0,SLP=0
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=1
05
01
Main mode
SCS=1,MCS=1
STP=0,SLP=0
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=1
07
13
PM transition mode
SCS=1,MCS=1
STP=0,SLP=0
TMD=1
SCM=1,MCM=0
SCD=0,MCD=0
PCD=0
14
MP transition mode
SCS=1,MCS=0
STP=0,SLP=0
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=0
16
20
PLL mode
SCS=1,MCS=0
STP=0,SLP=0
TMD=1
SCM=1,MCM=0
SCD=0,MCD=0
PCD=0
123
CHAPTER 6 LOW-POWER CONSUMPTION MODES
Figure 6.3-6 Status Transition Diagram 2 for Low-Power Consumption Mode (Single Clock (System) Parts)
Main sleep
SCS=1,MCS=1
STP=0,SLP=1
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=1
26
31
Main mode
SCS=1,MCS=1
STP=0,SLP=0
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=1
33
34
05
PM transition sleep
SCS=1,MCS=1
STP=0,SLP=1
TMD=1
SCM=1,MCM=0
SCD=0,MCD=0
PCD=0
Main oscillation
stabilization time
SCS=1,MCS=1
STP=0,SLP=0
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=1
35
38
PM transition mode
SCS=1,MCS=1
STP=0,SLP=0
TMD=1
SCM=1,MCM=0
SCD=0,MCD=0
PCD=0
124
40
Main stop
SCS=1,MCS=1
STP=1,SLP=0
TMD=1
SCM=1,MCM=1
SCD=1,MCD=1
PCD=1
41
CHAPTER 6 LOW-POWER CONSUMPTION MODES
Figure 6.3-7 Status Transition Diagram 3 for Low-Power Consumption Mode (Single Clock (System) Parts)
PLL mode
SCS=1,MCS=0
STP=0,SLP=0
TMD=1
SCM=1,MCM=0
SCD=0,MCD=0
PCD=0
57
60 Pseudo timer
transition
SCS=1,MCS=0
STP=1,SLP=0
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=1
61
62
Pseudo timer mode
SCS=1,MCS=0
STP=1,SLP=0
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=1
59
63
PLL sleep
SCS=1,MCS=0
STP=0,SLP=1
TMD=1
SCM=1,MCM=0
SCD=0,MCD=0
PCD=0
16
69
66
MS transition sleep
SCS=1,MCS=0
STP=0,SLP=1
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
67
PCD=0
68
MP transition mode
SCS=1,MCS=0
STP=0,SLP=0
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=0
Note:
In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power
consumption mode until the first switching is completed. The MCM and SCM bits of the clock
selection register (CKSCR) indicate that switching is completed. If the mode is switched to another
clock mode or low-power-consumption mode before completion of switching, the mode may not be
switched.
125
CHAPTER 6 LOW-POWER CONSUMPTION MODES
126
CHAPTER 7
MEMORY ACCESS MODES
This chapter explains the functions and operations of the memory access modes.
7.1 Outline of Memory Access Modes
7.2 External Memory Access (Bus Pin Control Circuit)
7.3 External Memory Access Control Signal Operation
127
CHAPTER 7 MEMORY ACCESS MODES
7.1
Outline of Memory Access Modes
In the F2MC-16LX, various modes are provided for access methods, access areas, and
test methods. The following classification applies to this module.
■ Memory Access Modes
Table 7.1-1 Mode Pins and Modes
Operation mode
Bus mode
Access mode
Single chip
8 bits
Internal ROM, external bus
RUN
16 bits
8 bits
External ROM, external bus
16 bits
Flash programming
-
-
❍ Operation mode
Operation mode means the mode for controlling the device operation status. The operation mode
is specified by the MDx mode setting pin and the Ex bit in mode data. By selecting an operation
mode, normal operation or internal test program activation can be performed.
❍ Bus mode
Bus mode means the mode for controlling the internal ROM operation and external access
function. The bus mode is specified by the MDx mode setting pin and the Mx bit in mode data.
The MDx mode setting pin specifies the bus mode for reading the reset vector and mode data,
and the Mx bit in mode data specifies the bus mode for normal operation.
❍ Access mode
Access mode means the mode for controlling the external data bus width. The access mode is
specified by the MDx mode setting pin and the SO bit in mode data. By selecting an access
mode, an 8- or 16-bit external data bus is specified.
128
CHAPTER 7 MEMORY ACCESS MODES
7.1.1
Mode Pins
Table 7.1-2 lists the operations that can be specified by combining the three external
pins MD2 to MD0.
■ Mode Pins
Table 7.1-2 Mode Pins and Modes
Mode pin setting
Mode name
Reset vector
access area
External data
bus width
Remarks
MD2
MD1
MD0
0
0
0
External vector mode 0
External
8 bits
0
0
1
External vector mode 1
External
16 bits
Reset vector, 16-bit
bus width access
0
1
0
Prohibited
Internal
(Mode data)
Reset sequence and
later segments are
controlled based on
mode data.
0
1
1
Internal vector mode
1
0
0
1
0
1
1
1
0
Flash memory serial
programming *
-
-
1
1
1
Flash memory
-
-
Prohibited
Mode when parallel
writer is used
*: Data cannot be written only by setting the flash serial programming mode by mode pins.
Other must be set. For detail, see the examples of flash memory serial programming connection.
129
CHAPTER 7 MEMORY ACCESS MODES
7.1.2
Mode Data
Mode data is stored at FFFFDFH of main memory and used for controlling the CPU
operation. This data is fetched during a reset sequence and stored in the mode register
inside the device. The mode register value can be changed only by a reset sequence.
The setting of this register is valid after the reset sequence.
Always set the reserved bits to "0".
■ Mode Data
Figure 7.1-1 shows the bit configuration of the mode data configuration.
Figure 7.1-1 Mode Data Configuration
Address: FFFFDFH
7
6
5
M1
M0
4
Reserved Reserved
3
S0
2
1
0
←Bit No.
Reserved Reserved Reserved
[bit7 and bit6] M1, M0 (bus mode setting bits)
The M1 and M0 bits are used to specify the operation mode after the reset sequence is
completed. Table 7.1-3 shows the relationship between the M1 and M0 bits and the functions.
Table 7.1-3 M1 and M0 (Bus Mode Setting Bit) Functions
M1
M0
Function
0
0
Single-chip mode
0
1
Internal ROM, external bus mode
1
0
External ROM, external bus mode
1
1
Setting prohibited
[bit3] S0 (mode setting bit)
The S0 bit is used to specify the bus mode or access mode after the reset sequence is
completed. Table 7.1-4 shows the relationship between the S0 bit and the functions.
Table 7.1-4 S0 (Mode Setting Bit) Functions
S0
130
Function
0
External 8-bit data bus mode
1
External 16-bit data bus mode
CHAPTER 7 MEMORY ACCESS MODES
7.1.3
Memory Space in Each Bus Mode
Figure 7.1-2 shows the correspondence between the access areas and physical
addresses for each bus mode.
■ Memory Space in Each Bus Mode
Figure 7.1-2 Relationship between Access Areas and Physical Addresses for Each Bus Mode
FFFFFFH
ROM area
ROM area
ROM area
(FF bank image)
ROM area
(FF bank image)
I/O
I/O
I/O
RAM
RAM
RAM
Address #1
010000H
004000H
003900H
Address #2
Address #3
: Internal
: External
000100H
0000C0H
I/O
I/O
Single chip
Internal ROM, external bus
000000H
Model
: No access
I/O
External ROM, external bus
Address #1
Address #2
Address #3
MB90F543/F543G(S)
FE0000H
002000H
001900H
MB90F548G(S)
FE0000H
002000H
001100H
MB90F549
FC0000H
002000H
001900H
MB90549G(S)/F549G(S)
FC0000H
002100H
001900H
MB90F546G(S)
FC0000H
002100H
002100H
(FC0000H)
002100H
002100H
MB90V540/V540G
131
CHAPTER 7 MEMORY ACCESS MODES
■ Recommended Setting
Table 7.1-5 lists an example of recommended settings for mode pins and mode data.
Table 7.1-5 Example of Recommended Settings for Mode Pins and Mode Data
Sample setting
MD1
MD1
MD0
M1
M0
S0
Single chip
0
1
1
0
0
x
Internal ROM and external bus mode, 16-bit bus
0
1
1
0
1
1
Internal ROM and external bus mode, 8-bit bus
0
1
1
0
1
0
External ROM and external bus mode, 16-bit bus,
vector 16 bus width
0
0
1
1
0
1
External ROM and external bus mode, 8-bit bus
0
0
0
1
0
0
External pins have signal functions that depend on each mode.
Table 7.1-6 External Pin Functions for Each Mode
Function
Pin name
External bus expansion
Single chip
8 bits
P07 to 00
16 bits
AD07 to 00
P17 to 10
A15 to 08
Flash
programming
D07 to 00
AD15 to 08
A15 to 08
P27 to 20
A23 to 16*
A07 to 00
P30
ALE
A16
P31
RD
CE
P32
P33
Port
WR *
WRL *
OE
Port
WRH *
PGM
P34
HRQ*
P35
HAK *
P36
RDY*
P37
CLK*
Unused
*: The upper address output pins and the WRL/WR, WRH, HRQ, HAK, RDY, and CLK pins can be used as
ports through function selection. See Section "7.2 External Memory Access (Bus Pin Control Circuit)" for
details.
132
CHAPTER 7 MEMORY ACCESS MODES
7.2
External Memory Access (Bus Pin Control Circuit)
The external bus pin control circuit controls the external bus pins for external
expansion of the CPU address and data buses.
■ External Memory Access (Bus Pin Control Circuit)
The following address, data, and control signals are used to access external memory and
peripherals of the MB90540/545 device:
•
CLK (P37): Machine cycle clock (KBP) output pin
•
RDY (P36): External ready input pin
•
WRH (P33): Write signal for upper 8 bits of data bus
•
WRL/WR (P32): Write signal for lower 8 bits of data bus write single for 8 bits of data bus in 8bit access mode
•
RD (P31): Read signal
•
ALE (P30): Address latch enable signal
The external bus pin control circuit is used to control the external bus pins to enable external
expansion of the CPU address and data buses.
■ Block Diagram of External Memory Access
Figure 7.2-1 External Bus Controller
P0
P0 data
P1
P2
P3
P3
P0
P0 direction
RB
Data control
Address control
Access control
Access control
133
CHAPTER 7 MEMORY ACCESS MODES
7.2.1
External Memory Access (External Bus Pin Control Circuit)
Registers
External memory access (external bus pin control circuit) uses the following three types
of registers:
• Automatic ready function selection register
• External address output control register
• Bus control signal selection register
■ External Memory Access Registers
Figure 7.2-2 shows the bit configuration of the external memory access (external bus pin control
circuit) registers.
Figure 7.2-2 External Memory access (External Bus Pin Control Circuit) Registers
Automatic ready function selection register
15
14
13
12
11
10
9
8
IOR1
IOR0
HMR1
HMR0
⎯
⎯
LMR1
LMR0
Read/write→
(W)
(W)
(W)
(W)
(-)
(-)
(W)
(W)
Initial value→
(0)
(0)
(1)
(1)
(-)
(-)
(0)
(0)
Address: 0000A5H
←Bit No.
ARSR
External address output control register
7
6
5
4
3
2
1
0
E23
E22
E21
E20
E19
E18
E17
E16
Read/write→
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
Initial value→
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
15
14
13
12
11
10
9
8
CKE
RYE
HDE
IOBS
HMBS
WRE
LMBS
⎯
Read/write→
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(-)
Initial value→
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(-)
Address: 0000A6H
←Bit No.
HACR
Bus control signal selection register
Address: 0000A7H
134
←Bit No.
ECSR
CHAPTER 7 MEMORY ACCESS MODES
7.2.2
Automatic Ready Function Selection Register (ARSR)
The automatic ready function selection register (ARSR) is used to set the automatic
wait time for memory access for each area during external access.
■ Automatic Ready Function Selection Register (ARSR)
Figure 7.2-3 shows the bit configuration of the automatic ready function selection register
configuration.
Figure 7.2-3 Automatic Ready Function Selection Register Configuration (ARSR)
15
14
13
12
11
10
9
8
IOR1
IOR0
HMR1
HMR0
⎯
⎯
LMR1
LMR0
Read/write→
(W)
(W)
(W)
(W)
(-)
(-)
(W)
(W)
Initial value→
(0)
(0)
(1)
(1)
(-)
(-)
(0)
(0)
Address: 0000A5H
←Bit No.
ARSR
[bit15 and bit14] IOR1, IOR0
The IOR1 and IOR0 bits are used to specify the automatic wait function for external access to
the area from 0000C0H to 0000FFH. Table 7.2-1 lists the settings that can be specified by
combining the IOR1 and IOR0 bits.
Table 7.2-1 IOR1 and IOR0 (Automatic Wait Function Specification Bit) Functions
IOR1
IOR0
Function
0
0
Automatic wait disabled [initial value]
0
1
Automatic wait of 1 cycle is inserted at external access
1
0
Automatic wait of 2 cycles is inserted at external access
1
1
Automatic wait of 3 cycles is inserted at external access
[bit13 and bit12] HMR1, HMR0
The HMR1 and HMR0 bits are used to specify the automatic wait function for external access
to the area from 800000H to FFFFFFH. Table 7.2-2 lists the settings that can be specified by
combining the HMR1 and HMR0 bits.
Table 7.2-2 HMR1 and HMR0 (Automatic Wait Function Specification Bit) Functions
HMR1
HMR0
Function
0
0
Automatic wait disabled
0
1
Automatic wait of 1 cycle is inserted at external access
1
0
Automatic wait of 2 cycles is inserted at external access
1
1
Automatic wait of 3 cycles is inserted at external access
[initial value]
135
CHAPTER 7 MEMORY ACCESS MODES
[bit9 and bit8] LMR1, LMR0
The LMR1 and LMR0 bits are used to specify the automatic wait function for external access
to the areas between 002000H and 7FFFFFH. Table 7.2-3 lists the settings that can be
specified by combining the LMR1 and LMR0 bits.
Table 7.2-3 LMR1 and LMR0 (Automatic Wait Function Specification Bit) Functions
136
LMR1
LMR0
Function
0
0
Automatic wait disabled [initial value]
0
1
Automatic wait of 1 cycle is inserted at external access
1
0
Automatic wait of 2 cycles is inserted at external access
1
1
Automatic wait of 3 cycles is inserted at external access
CHAPTER 7 MEMORY ACCESS MODES
7.2.3
External Address Output Control Register (HACR)
The external address output control register (HACR) controls the external output of
addresses (A23 to A16). The bits correspond to addresses A23 to A16, which control
address output pins, as shown in Figure 7.2-4.
■ External Address Output Control Register (HACR)
Figure 7.2-4 shows the bit configuration of the external address output control address
configuration.
Figure 7.2-4 External Address Output Control Address Configuration (HACR)
7
6
5
4
3
2
1
0
E23
E22
E21
E20
E19
E18
E17
E16
Read/write→
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
Initial value→
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Address: 0000A6H
←Bit No.
HACR
[bit7 to bit0] E23 to E16
The HACR register controls output of addresses (A23 to A16) to the external circuit. The address
output pin is controlled as follows with the eight bits that correspond to address bits A23 to A16.
The HACR register cannot be accessed when the device is in single-chip mode, since all pins
function as I/O ports regardless of the value of this register.
All bits of this register are write-only bits, and the value read from the bits is 1.
Table 7.2-4 External Address Output Control Register (E16 to E23 Bits) Functions
0
The corresponding pin is used for address output (AXX) [initial value].
1
The corresponding pin is used as an I/O port (PXX).
137
CHAPTER 7 MEMORY ACCESS MODES
7.2.4
Bus Control Signal Selection Register (ECSR)
The bus control signal selection register sets the bus operation control function in
external bus mode. This register cannot be accessed when the device is in single-chip
mode, since all pins function as I/O ports regardless of the value of this register. All bits
of the bus control signal selection register are write-only bits, and the value read from
the bits is 1.
■ Bus Control Signal Selection Register (ECSR)
Figure 7.2-5 shows the bit configuration of the bus control signal selection register configuration.
Figure 7.2-5 Bus Control Signal Selection Register Configuration (ECSR)
15
14
13
12
11
10
9
8
CKE
RYE
HDE
IOBS
HMBS
WRE
LMBS
⎯
Read/write→
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(-)
Initial value→
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(-)
Address: 0000A7H
←Bit No.
ECSR
[bit15] CKE
The CKE bit controls output of the external clock signal pin (CLK), as shown in Table 7.2-5.
Table 7.2-5 CKE (External Clock (CLK) Output Control Bit) Functions
0
I/O port (P37) operation (clock output disabled) [initial value]
1
Clock signal (CLK) output enabled
[bit14] RYE
The RYE bit controls input of the external ready (RDY) signal pin, as shown in Table 7.2-6.
Table 7.2-6 RYE (External Ready (RDY) Input Control Bit) Functions
0
I/O port (P36) operation (external RDY input disabled) [initial value]
1
External ready (RDY) input enabled
[bit13] HDE
The HDE bit specifies that input-output of hold signals is enabled. The hold request input
signal (HRQ) and hold acknowledge output signal (HAK) are controlled according to the
setting of the HDE bit, as shown in Table 7.2-7.
Table 7.2-7 HDE (Hold Signal Input-Output Enable Specification Bit) Functions
138
0
I/O port (P35, P34) operation (hold function input-output disabled) [initial value]
1
Hold request (HRQ) input/hold acknowledge (HAK) output enabled
CHAPTER 7 MEMORY ACCESS MODES
[bit12] IOBS
The IOBS bit is used to specify the bus width for external access to the area from 0000C0H to
0000FFH in external 16-bit data bus mode. Control is based on the setting of this bit, as shown
in Table 7.2-8.
Table 7.2-8 IOBS (Bus Width Specification Bit)
0
16-bit bus width access [initial value]
1
8-bit bus width access
[bit11] HMBS
The HMBS bit is used to specify the bus width for external access to the area from 800000H to
FFFFFFH in external 16-bit data bus mode. Control is based on the setting of this bit, as
shown in Table 7.2-9.
Table 7.2-9 HMBS (Bus Width Specification Bit) Functions
0
16-bit bus width access [initial value]
1
8-bit bus width access
[bit10] WRE
The WRE bit controls output of external write signals (both WRH and WRL pins in external
data bus 16-bit mode and WR pin in external data bus 8-bit mode), as shown in Table 7.2-10.
In external 8-bit data bus mode, P33 functions as the I/O port regardless of the setting value of
this bit.
Table 7.2-10 WRE (External Write Signal Output Control Bit) Functions
0
I/O port (P33, P32) operation (write signal output disabled) [initial value]
1
Write strobe signal (WRH/WRL or WR only) output enabled
139
CHAPTER 7 MEMORY ACCESS MODES
[bit9] LMBS
The LMBS bit is used to specify the bus width for external access to the area from 002000H to
7FFFFFH in external 16-bit data bus mode. Control is based on the setting of this bit, as
shown in Table 7.2-11.
Table 7.2-11 LMBS (Bus Width Specification Bit) Functions
0
16-bit bus width access [initial value]
1
8-bit bus width access
Notes:
• To use the WRE bit to enable the WR, WRH, and WRL functions in external data bus 16-bit
mode, set P33 and P32 in input mode (set bit3 and bit2 of the DDR3 register to "0").
• To use the WRE bit to enable the WR function in external data bus 8-bit mode, set P32 in input
mode (set bit2 of the DDR3 register to "0").
• If the RYE and HDE bits are used to enable the RDY and HRQ signals, the I/O port function of the
port is also enabled. Be sure to write "0" (input mode) to the DDR3 register that corresponds to
the port.
140
CHAPTER 7 MEMORY ACCESS MODES
7.3
External Memory Access Control Signal Operation
If the ready function is not used, external memory is accessed in three cycles. The 8-bit
bus width access function is used to read and write the 8-bit width peripheral chip when
the 8-bit and 16-bit width peripheral chips are connected together to the external bus.
■ External Memory Access Control Signal
The HMBS, LMBS, and IOBS bits in ECSR register are used to specify whether 16-bit bus width
access or 8-bit bus width access is to be used in external data bus 16-bit mode.
Actually, bus operation may not be performed by providing only address output and assert output
of the ALE signal without asserting RD, WRL, WRH and WR. Be sure that access to a peripheral
chip using only the ALE signal is not executed.
Figure 7.3-1 Timing Chart for External Memory Access (External Data Bus 8-bit Mode)
Read
Read
Write
P37/CLK
P33/WRH
(Port data)
P32/WRL/WR
P31/RD
P30/ALE
P27 to 20/A23 to 16
Read address
Write address
Read address
P17 to 10/A15 to 08
Read address
Write address
Read address
P07 to 00/AD07 to 00
Read
address
Write
address
Read data
Read address
Write data
141
CHAPTER 7 MEMORY ACCESS MODES
Figure 7.3-2 Timing Chart for External Memory Access (External Data Bus 16-bit Mode)
(16-bit Bus Width access and 8-bit Bus Width Access)
8-bit bus width byte read
Even address byte read
8-bit bus width byte write
Even address byte write
P37/CLK
P33/WRH
P32/WRL/WR
P31/RD
P30/ALE
P27 to 20/A23 to 16
Write address
Read address
P17 to 10/AD15 to 08
Read address
P07 to 00/AD07 to 00
Read address
Invalid
Write address
(Undefined)
Read address
Read address
Write address
Write data
Read data
Odd address byte read
Read address
Odd address byte write
P37/CLK
P33/WRH
P32/WRL/WR
P31/RD
P30/ALE
P27 to 20/A23 to 16
Read address
P17 to 10/AD15 to 08
Read address
P07 to 00/AD07 to 00
Read address
Write address
Read address
Write address
Invalid
Write address
Read address
(Undefined)
Read address
Write data
Read data
Even address word read
Even address word write
Read address
Write address
P37/CLK
P33/WRH
P32/WRL/WR
P31/RD
P30/ALE
P27 to 20/A23 to16
Read address
P17 to 10/AD15 to 08
Read address
Write address
Read address
P07 to 00/AD07 to 00
Read address
Write address
Read address
Read data
Write data
Note:
Set the external circuit so that data is always read in word mode.
The setting of P36/RDY pin or the automatic ready function selection register (ARSR) enables
access to low-speed memory and peripheral circuits.
142
CHAPTER 7 MEMORY ACCESS MODES
7.3.1
Ready Function
The setting of P36/RDY pin or the automatic ready function selection register (ARSR)
enables access to the low-speed memory and peripheral circuits.
If the RYE bit of the bus control signal selection register (ECSR) is set to "1", the wait
cycle is entered to enable extension of the access cycle while the "L" level is input to
P36/RDY signal during access to the external circuit.
■ Ready Function
Figure 7.3-3 Timing Chart for Ready Function
Even address word read
Even address word write
P37/CLK
P33/WRH
P32/WRL/WR
P31/RD
P30/ALE
P27 to 20/A23 to 16
Write address
Read address
P17 to 10/AD15 to 08
Read address
Write address
P07 to 00/AD07 to 00
Read address
Write address
P36/RDY
Read data
RDY pin fetch
Even address word write
Write data
Even address word read
P37/CLK
P33/WRH
P32/WRL/WR
P31/RD
P30/ALE
P27 to 20/A23 to 16
Write address
P17 to 10/AD15 to 08
Write address
Read address
P07 to 00/AD07 to 00
Write address
Read address
Read address
Write data
Cycle extended by auto ready
The MB90540/545 has two types of auto ready functions for external memory access. The auto
ready function can automatically insert 1 to 3 wait cycles to extend the access cycle without an
external circuit for access to the external areas at lower addresses 002000H to 7FFFFFH and at
143
CHAPTER 7 MEMORY ACCESS MODES
upper addresses 800000H to FFFFFFH. This function is activated according to the setting of the
LMR1 and LMR0 bits (external areas at lower addresses) of ARSR and the HMR1 and HMR0 bits
(external area at upper addresses) of ARSR.
The MB90540/545 also has an auto ready function for I/O that is independent of the auto ready
function for memory. When the IOR1 and IOR0 bits of the ARSR register are set to "0", 1 to 3
wait cycles can be automatically inserted to extend the access cycle without an external circuit for
access to the external area from addresses 0000C0H to 0000FFH.
If the RYE bit of the ECSR is set to "1" and the "L" level is continues to be input to P36/RDY pin
after the wait cycle using the auto ready function for external memory and for external I/O is
completed, the wait cycle continues.
144
CHAPTER 7 MEMORY ACCESS MODES
7.3.2
Hold Function
If the HDE bit in the bus control signal selection register (ECSR) is set to "1", the
external address hold function specified by the P34/HRQ and P35/HAK pins is enabled.
■ Hold Function
If the high level is applied to the P34/HRQ pin, the hold state is set up at termination of a CPU
instruction (for a string instruction, at termination of 1-element data processing). The P35/HAK pin
outputs the low level to place the following pins in a high-impedance state:
•
Address output: P27/A23 to P20/A16
•
Address/data I/O: P17/AD15 to P00/AD00
•
Bus control signal: P30/ALE, P31/RD, P32/WRL/WR, P33/WRH
Thus, an external bus can be used from a device external circuit. When the low level is input to
the P34/HRQ pin, the P35/HAK pin outputs the high-level, thereby restoring the external pin state
and restarting the bus operation. In the stop status, hold request input is not accepted.
Figure 7.3-4 shows the hold timing (in an external 16-bit bus mode).
Figure 7.3-4 Hold Timing
Read cycle
Hold cycle
Write cycle
P37/CLK
P34/HRQ
P35/HAK
P33/WRH
P32/WRL/WR
P31/RD
P30/ALE
P27 to 20/A23 to 16
(Address)
(Address)
P17 to 10/AD15 to 08
(Address)
(Address)
P07 to 00/AD07 to 00
Read data
Write data
145
CHAPTER 7 MEMORY ACCESS MODES
146
CHAPTER 8
I/O PORTS
This chapter explains the functions of the I/O ports.
8.1 I/O Ports
8.2 I/O Port Registers
147
CHAPTER 8 I/O PORTS
8.1
I/O Ports
Each pin of the ports can be specified as input or output using the port direction
register (DDR0 to DDRA) if the corresponding peripheral does not use the pin.
■ Outline of I/O Ports
When a pin is specified as input, the logic level at the pin is read. When a pin is specified as
output, the data register value is read. The above is also applied to a read operation for the readmodify-write instructions.
However, when a pin is used as an output for another peripheral, the logic level at the pin is read
regardless of the value of the data register.
It is generally recommended that the read-modify-write instructions are not used for setting the
data register before a port is set for output and the output of the peripheral resource is prohibited.
The reason is that a read-modify-write instruction in this case reads the logic level at the port
instead of the register value.
Figure 8.1-1 is a block diagram of the I/O ports.
Figure 8.1-1 I/O Port Block Diagram
Internal data bus
Data register read
Data register
Data register write
Direction register
Direction register write
Direction register read
148
Pin
CHAPTER 8 I/O PORTS
8.2
I/O Port Registers
Figure 8.2-1 shows the bit configuration of the I/O port registers.
■ I/O Port Registers
Figure 8.2-1 shows the bit configuration of the I/O port registers.
Figure 8.2-1 I/O Port Registers
Bit No.→
7
6
5
4
3
2
1
Address: 000000H
P07
P06
P05
P04
P03
P02
P01
P00 Port data register (PDR0) (for port 0)
0
Address: 000001H
P17
P16
P15
P14
P13
P12
P11
P10 Port data register (PDR1) (for port 1)
Address: 000002H
P27
P26
P25
P24
P23
P22
P21
P20 Port data register (DDR2) (for port 2)
Address: 000003H
P37
P36
P35
P34
P33
P32
P31
P30 Port data register (PDR3) (for port 3)
Address: 000004H
P47
P46
P45
P44
P43
P42
P41
P40 Port data register (PDR4) (for port 4)
Address: 000005H
P57
P56
P55
P54
P53
P52
P51
P50 Port data register (PDR5) (for port 5)
Address: 000006H
P67
P66
P65
P64
P63
P62
P61
P60 Port data register (PDR6) (for port 6)
Address: 000007H
P77
P76
P75
P74
P73
P72
P71
P70 Port data register (PDR7) (for port 7)
Address: 000008H
P87
P86
P85
P84
P83
P82
P81
P80 Port data register (PDR8) (for port 8)
Address: 000009H
P97
P96
P95
P94
P93
P92
P91
P90 Port data register (PDR9) (for port 9)
Address: 00000AH
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PA0 Port data register (PDRA) (for port A)
Bit No.→
7
6
5
4
3
2
1
0
Address: 000010H
D07
D06
D05
D04
D03
D02
D01
D00 Port direction register (DDR0) (for port 0)
Address: 000011H
D17
D16
D15
D14
D13
D12
D11
D10 Port direction register (DDR1) (for port 1)
Address: 000012H
D27
D26
D25
D24
D23
D22
D21
D20 Port direction register (DDR2) (for port 2)
Address: 000013H
D37
D36
D35
D34
D33
D32
D31
D30 Port direction register (DDR3) (for port 3)
Address: 000014H
D47
D46
D45
D44
D43
D42
D41
D40 Port direction register (DDR4) (for port 4)
Address: 000015H
D57
D56
D55
D54
D53
D52
D51
D50 Port direction register (DDR5) (for port 5)
Address: 000016H
D67
D66
D65
D64
D63
D62
D61
D60 Port direction register (DDR6) (for port 6)
Address: 000017H
D77
D76
D75
D74
D73
D72
D71
D70 Port direction register (DDR7) (for port 7)
Address: 000018H
D87
D86
D85
D84
D83
D82
D81
D80 Port direction register (DDR8) (for port 8)
Address: 000019H
D97
D96
D95
D94
D93
D92
D91
D90 Port direction register (DDR9) (for port 9)
Address: 00001AH
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DA0 Port direction register (DDRA) (for port A)
Bit No.→
7
6
5
4
3
2
1
0
Address: 00001CH PU07 PU06 PU05 PU04 PU03 PU02 PU01 PU00 Pull-up control register (PUCR0) (for port 0)
Address: 00001DH PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 Pull-up control register (PUCR1) (for port 1)
Address: 00001EH PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20 Pull-up control register (PUCR2) (for port 2)
Address: 00001FH PU37 PU36 PU35 PU34 PU33 PU32 PU31 PU30 Pull-up control register (PUCR3) (for port 3)
Bit No.→
7
6
5
4
3
2
1
0
Address: 00001BH ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Analog input enable register (ADER)
149
CHAPTER 8 I/O PORTS
8.2.1
Port Data Register (PDR0 to PDRA) (for port 0 to port A)
Figure 8.2-2 shows the detailed bit configuration of the port data register (PDR0 to PDRA)
(for port 0 to port A).
■ Port Data Register (PDR0 to PDRA) (for Port 0 to Port A)
Figure 8.2-2 shows the bit configuration of the port data register (PDR0 to PDRA) (for port 0 to
port A).
Figure 8.2-2 Port Data Registers (PDR0 to PDRA) (for Port 0 to Port A)
PDR0 (for port 0)
Bit No.→
Address: 000000H
PDR1 (for port 1)
Bit No.→
Address: 000001H
PDR2 (for port 2)
Bit No.→
Address: 000002H
PDR3 (for port 3)
Bit No.→
Address: 000003H
PDR4 (for port 4)
Bit No.→
Address: 000004H
PDR5 (for port 5)
Bit No.→
Address: 000005H
PDR6 (for port 6)
Bit No.→
Address: 000006H
PDR7 (for port 7)
Bit No.→
Address: 000007H
PDR8 (for port 8)
Bit No.→
Address: 000008H
PDR9 (for port 9)
Bit No.→
Address: 000009H
PDRA (for port A)
Bit No.→
Address: 00000AH
7
P07
6
P06
5
P05
4
P04
3
P03
2
P02
1
P01
0
P00
Initial value Access
XXXXXXXXB R/W*
7
P17
6
P16
5
P15
4
P14
3
P13
2
P12
1
P11
0
P10
XXXXXXXXB
R/W*
7
P27
6
P26
5
P25
4
P24
3
P23
2
P22
1
P21
0
P20
XXXXXXXXB
R/W*
7
P37
6
P36
5
P35
4
P34
3
P33
2
P32
1
P31
0
P30
XXXXXXXXB
R/W*
7
P47
6
P46
5
P45
4
P44
3
P43
2
P42
1
P41
0
P40
XXXXXXXXB
R/W*
7
P57
6
P56
5
P55
4
P54
3
P53
2
P52
1
P51
0
P50
XXXXXXXXB
R/W*
7
P67
6
P66
5
P65
4
P64
3
P63
2
P62
1
P61
0
P60
XXXXXXXXB
R/W*
7
P77
6
P76
5
P75
4
P74
3
P73
2
P72
1
P71
0
P70
XXXXXXXXB
R/W*
7
P87
6
P86
5
P85
4
P84
3
P83
2
P82
1
P81
0
P80
XXXXXXXXB
R/W*
7
P97
6
P96
5
P95
4
P94
3
P93
2
P92
1
P91
0
P90
XXXXXXXXB
R/W*
7
⎯
6
⎯
5
⎯
4
⎯
3
⎯
2
⎯
1
⎯
0
PA0
-------XB
R/W*
*: Note the following differences between R/W for the I/O ports and R/W for memory:
- Input mode
Read: The level at the corresponding pin is read.
Write: Data is written to an output latch.
- Output mode
Read: The value of data register latch is read.
Write: Data is written to an output latch and output to the corresponding pin.
150
CHAPTER 8 I/O PORTS
8.2.2
Port Direction Register (DDR0 to DDRA) (for port 0 to port A)
Figure 8.2-3 shows the bit configuration of the port direction register (DDR0 to DDRA)
(for port 0 to port A).
■ Port Direction Register (DDR0 to DDRA) (for Port 0 to Port A)
Figure 8.2-3 shows the bit configuration of the port direction registers (DDR0 to DDRA) (for port 0
to port A).
Figure 8.2-3 Port Direction Registers (DDR0 to DDRA)
DDR0 (for port 0)
Bit No.→
Address: 000010H
DDR1 (for port 1)
Bit No.→
Address: 000011H
DDR2 (for port 2)
Bit No.→
Address: 000012H
DDR3 (for port 3)
Bit No.→
Address: 000013H
DDR4 (for port 4)
Bit No.→
Address: 000014H
DDR5 (for port 5)
Bit No.→
Address: 000015H
DDR6 (for port 6)
Bit No.→
Address: 000016H
DDR7 (for port 7)
Bit No.→
Address: 000017H
DDR8 (for port 8)
Bit No.→
Address: 000018H
DDR9 (for port 9)
Bit No.→
Address: 000019H
DDRA (for port A)
Bit No.→
Address: 00001AH
7
P07
6
P06
5
P05
4
P04
3
P03
2
P02
1
P01
0
P00
Initial value
Undefined
Access
R/W
7
P17
6
P16
5
P15
4
P14
3
P13
2
P12
1
P11
0
P10
00000000B
R/W
7
P27
6
P26
5
P25
4
P24
3
P23
2
P22
1
P21
0
P20
00000000B
R/W
7
P37
6
P36
5
P35
4
P34
3
P33
2
P32
1
P31
0
P30
00000000B
R/W
7
P47
6
P46
5
P45
4
P44
3
P43
2
P42
1
P41
0
P40
00000000B
R/W
7
P57
6
P56
5
P55
4
P54
3
P53
2
P52
1
P51
0
P50
00000000B
R/W
7
P67
6
P66
5
P65
4
P64
3
P63
2
P62
1
P61
0
P60
00000000B
R/W
7
P77
6
P76
5
P75
4
P74
3
P73
2
P72
1
P71
0
P70
00000000B
R/W
7
P87
6
P86
5
P85
4
P84
3
P83
2
P82
1
P81
0
P80
00000000B
R/W
7
P97
6
P96
5
P95
4
P94
3
P93
2
P92
1
P91
0
P90
00000000B
R/W
7
⎯
6
⎯
5
⎯
4
⎯
3
⎯
2
⎯
1
⎯
0
PA0
-------0B
R/W
When a pin functions as a port, the corresponding pin is controlled as follows:
0: Input mode
1: Output mode
The bits are set to "0" by a reset.
151
CHAPTER 8 I/O PORTS
8.2.3
Pull-up Control Register (PUCR0 to PUCR3)
(for port 0 to port 3)
Figure 8.2-4 shows the bit configuration of the pull-up control register (PUCR0 to
PUCR3) (for port 0 to port 3), and Figure 8.2-5 is the block diagram.
■ Pull-up Control Register (PUCR0 to PUCR3) (for Port 0 to Port 3)
Figure 8.2-4 shows the bit configuration of the pull-up control register (PUCR0 to PUCR3) (for
port 0 to port 3).
Figure 8.2-4 Bit Configuration of Pull-up Control Register (PUCR0 to PUCR3) (for Port 0 to Port 3)
152
6
PU06
(R/W)
(0)
5
PU05
(R/W)
(0)
4
PU04
(R/W)
(0)
3
PU03
(R/W)
(0)
2
PU02
(R/W)
(0)
1
PU01
(R/W)
(0)
0
PU00
(R/W)
(0)
←Bit No.
Address: 00001CH
Read/write→
Initial value→
7
PU07
(R/W)
(0)
6
PU16
(R/W)
(0)
5
PU15
(R/W)
(0)
4
PU14
(R/W)
(0)
3
PU13
(R/W)
(0)
2
PU12
(R/W)
(0)
1
PU11
(R/W)
(0)
0
PU10
(R/W)
(0)
←Bit No.
Address: 00001DH
Read/write→
Initial value→
7
PU17
(R/W)
(0)
6
PU26
(R/W)
(0)
5
PU25
(R/W)
(0)
4
PU24
(R/W)
(0)
3
PU23
(R/W)
(0)
2
PU22
(R/W)
(0)
1
PU21
(R/W)
(0)
0
PU20
(R/W)
(0)
←Bit No.
Address: 00001EH
Read/write→
Initial value→
7
PU27
(R/W)
(0)
6
PU36
(R/W)
(0)
5
PU35
(R/W)
(0)
4
PU34
(R/W)
(0)
3
PU33
(R/W)
(0)
2
PU32
(R/W)
(0)
1
PU31
(R/W)
(0)
0
PU30
(R/W)
(0)
←Bit No.
Address: 00001FH
Read/write→
Initial value→
7
PU37
(R/W)
(0)
PUCR0
(for port 0)
PUCR1
(for port 1)
PUCR2
(for port 2)
PUCR3
(for port 3)
CHAPTER 8 I/O PORTS
■ Block Diagram of Pull-up Control Register (PUCR0 to PUCR3)
Figure 8.2-5 Block Diagram of Pull-up Control Register (PUCR0 to PUCR3)
Pull-up resistor (about 50kΩ)
Data register
Port input-output
Direction register
Resistor register
Internal data bus
Notes:
• In input mode, the pull-up resistor is controlled.
0: No pull-up resistor in input mode
1: Pull-up resistor in input mode
• In output mode, this register has no meaning (no pull-up resistor).
• The direction register (DDR0 to DDRA) determines the input-output mode.
• In hardware standby mode and stop mode (SPL=1), the state with no pull-up resistor is entered
(high impedance).
• If the port is used as an external bus, this function is disabled and data is not written to the
register.
153
CHAPTER 8 I/O PORTS
8.2.4
Analog Input Enable Register (ADER)
Figure 8.2-6 shows the bit configuration of the analog input enable register (ADER).
■ Analog Input Enable Register (ADER)
Figure 8.2-6 shows the bit configuration of the analog input enable register (ADER).
Figure 8.2-6 Bit Configuration of Analog Input Enable Register (ADER)
Address: 00001BH
Read/write→
Initial value→
15
ADE7
R/W
(1)
14
ADE6
R/W
(1)
13
ADE5
R/W
(1)
12
ADE4
R/W
(1)
11
ADE3
R/W
(1)
10
ADE2
R/W
(1)
9
ADE1
R/W
(1)
8
ADE0
R/W
(1)
←Bit No.
ADER
The analog input enable register (ADER) controls the pins of port 6 as follows:
•
0: Port input mode
•
1: Analog input mode
If an external pin is used as analog input of the A/D converter, set the corresponding bit to "1".
154
CHAPTER 9
TIMEBASE TIMER
This chapter explains the functions and operations of the timebase timer.
9.1 Outline of Timebase Timer
9.2 Timebase Timer Control Register (TBTC)
9.3 Operations of Timebase Timer
155
CHAPTER 9 TIMEBASE TIMER
9.1
Outline of Timebase Timer
The timebase timer consists of an 18-bit timer and a circuit that controls an interval
interrupt. The timebase timer uses the main clock signal regardless of the MSC and
SCS bits of the clock selection register (CKSCR).
■ Timebase Timer Registers
Figure 9.1-1 shows the bit configuration of the timebase timer registers.
Figure 9.1-1 Timebase Timer Registers
15
Address: 0000A9H
Read/write→
Initial value→
156
Reserved
(R/W)
(1)
14
⎯
(-)
(-)
13
⎯
(-)
(-)
12
TBIE
(R/W)
(0)
11
TBOF
(R/W)
(0)
10
TBR
(R/W)
(1)
9
TBC1
(R/W)
(0)
8
TBC0
(R/W)
(0)
←Bit No.
TBTC
CHAPTER 9 TIMEBASE TIMER
■ Block Diagram of Timebase Timer
Figure 9.1-2 Block Diagram of Timebase Timer
Main clock
TBTC
TBC1
Selector
TBC0
Clock input
212
214
16
2
Timebase timer
219
212 214 216 219
TBTRES
TBR
TBIE
AND
Q
S
R
TBOF
Time base
interrupt
WDTC
WT1
Selector
WT0
2-bit counter
OF
CLR
Watch-dog reset
generation circuit
CLR
Internal data bus
WTE
WDGRST
To internal reset
generation circuit
WTC
WDCS
AND
SCE
Q
SCM
Power-on reset
Subclock stop
S
R
210
WTC2
WTC1
WTC0
WTOF
214
215
Watch timer
WTR
WTIE
213
Selector
WTRES
AND
Q
S
R
Clock input
Subclock/4
Timer
interrupt
WDTC
PONR
From power-on generation
STBR
From hardware standby
control circuit
WRST
ERST
RST pin
SRST
From RST bit of
LPMCR register
157
CHAPTER 9 TIMEBASE TIMER
9.2
Timebase Timer Control Register (TBTC)
The timebase timer control register (TBTC) controls the operation of the timebase timer
and the interval interrupt time.
■ Timebase Timer Control Register (TBTC)
Figure 9.2-1 shows the bit configuration of the timebase timer control register (TBTC).
Figure 9.2-1 Timebase Timer Control Register (TBTC)
15
Address: 0000A9H
Read/write→
Initial value→
Reserved
(R/W)
(1)
14
⎯
(-)
(-)
13
⎯
(-)
(-)
12
TBIE
(R/W)
(0)
11
TBOF
(R/W)
(0)
10
TBR
(R/W)
(1)
9
TBC1
(R/W)
(0)
8
TBC0
(R/W)
(0)
←Bit No.
TBTC
[bit15] Reserved bit
Ensure that "1" is always written to this bit.
[bit14 and bit13] Unused bits
Bit14 and bit13 are unused.
[bit12] TBIE
This bit is used to enable interval interrupts based on the timebase timer. Writing "1" to this bit
enables interrupts, and writing "0" disables interrupts. This bit is initialized to "0" by a reset.
This bit is readable and writable.
[bit11] TBOF
This is an interrupt request flag for the timebase timer. While the TBIE bit is "1", an interrupt
request is issued when "1" is written to TBOF. This bit is set to "1" for each interval specified
with the TBC1 and TBC0 bits.
This bit is cleared by writing "0", transition to stop or hardware standby mode, or a reset.
Writing "1" has no effect.
"1" is always read by a read-modify-write instruction.
[bit10] TBR
This bit clears all bits of the timebase timer counter to "0".
Writing "0" clears the timebase timer.
Writing "1" has no effect.
"1" is always read from this bit.
158
CHAPTER 9 TIMEBASE TIMER
[bit9 and bit8] TBC1 and TBC0
These bits are used to set the timebase timer interval time. These bits are initialized to 00B by
a reset. These bits can be read and written to.
Table 9.2-1 lists the settings for the timebase timer interval time.
Table 9.2-1 Settings for Timebase Timer Interval Time
TBC1
TBC0
Interval time at 4 MHz source oscillation
0
0
1.024 ms
0
1
4.096 ms
1
0
16.384 ms
1
1
131.072 ms
159
CHAPTER 9 TIMEBASE TIMER
9.3
Operations of Timebase Timer
The timebase timer functions as a watch-dog timer clock source, timer for main clock
and PLL clock oscillation stabilization wait time, and interval timer for generating
interrupts at specified intervals.
■ Timebase Timer
The timebase timer consists of an 18-bit counter that counts the pulses of the oscillation clock
used to generate the machine clock. While the oscillation clock is input, the timebase timer keeps
counting.
The timebase timer is cleared by a power-on reset, transition to stop or hardware standby mode,
or transition from the main clock to the PLL clock by writing data to the MCS bit of the clock
selection register (CKSCR). The timebase timer is also cleared by transition from the main clock
to the subclock by writing data to the SCS bit of the clock selection register (CKSCR) or writing 0
to the TBR bit of the timebase timer control register (TBTC).
The watch-dog counter and interval interrupt function using output from the timebase timer are
affected by clearing the timebase counter.
■ Interval Interrupt Function of Timebase Timer
Interrupts are generated at specified intervals according to the carry signals of the timebase
counter. The TBOF flag is set at the intervals specified with the TBC1 and TBC0 bits of the
timebase timer control register (TBTC). This flag is set by using as a reference the last time that
the timebase timer was cleared.
On transition from main clock mode to PLL clock mode, the timebase timer is cleared because
the timebase timer is used as a timer for PLL clock oscillation stabilization wait.
On transition from oscillation clock mode to subclock mode, the timebase timer is cleared
because the timebase timer is used as a timer for oscillation stabilization wait of the oscillation
clock.
On transition to stop mode and hardware standby mode, the TBOF flag is immediately cleared
when mode transition is complete because the timebase timer is used as a timer for oscillation
stabilization time wait at recovery.
160
CHAPTER 10
WATCH-DOG TIMER
This chapter explains the functions and operations of the watch-dog timer.
10.1 Outline of Watch-dog Timer
10.2 Watch-dog Timer Control Register (WDTC)
10.3 Watch-dog Timer Operation
161
CHAPTER 10 WATCH-DOG TIMER
10.1 Outline of Watch-dog Timer
The watch-dog timer consists of a 2-bit watch-dog counter that uses the carry signal of
the 18-bit timebase timer or 15-bit watch timer as a clock source, control register, and
watch-dog reset controller.
■ Watch-dog Timer Register
Figure 10.1-1 shows the bit configuration of the watch-dog timer register.
Figure 10.1-1 Watch-dog Timer Register
Address: 0000A8H
Read/write→
Initial value→
162
7
PONR
(R)
(X)
6
STBR
(R)
(X)
5
WRST
(R)
(X)
4
ERST
(R)
(X)
3
SRST
(R)
(X)
2
WTE
(W)
(1)
1
WT1
(W)
(1)
0
WT0
(W)
(1)
←Bit No.
WDTC
CHAPTER 10 WATCH-DOG TIMER
■ Watch-dog Timer Block Diagram
Figure 10.1-2 Block Diagram of Watch-dog Timer
Main clock
TBTC
TBC1
Selector
TBC0
212
Clock input
214
16
Timebase timer
2
219
212 214 216 219
TBTRES
TBR
TBIE
AND
Q
S
R
TBOF
Internal data bus
Time base
interrupt
WDTC
WT1
Selector
WT0
2-bit counter
OF
CLR
Watch-dog reset
generation circuit
CLR
WTE
WDGRST
To internal reset
generation circuit
WTC
WDCS
AND
SCE
Q
SCM
Power-on reset
Subclock stop
S
R
210
WTC2
WTC1
WTC0
214
215
Watch timer
WTR
WTIE
213
Selector
WTRES
AND
Q
S
R
Clock input
Subclock/4
WTOF
Timer
interrupt
WDTC
PONR
From power-on generation
STBR
From hardware standby
control circuit
WRST
ERST
RST pin
SRST
From RST bit of
LPMCR register
163
CHAPTER 10 WATCH-DOG TIMER
10.2 Watch-dog Timer Control Register (WDTC)
The watch-dog timer control register (WDTC) consists of the bits that control the watchdog timer and bits that identify reset causes.
■ Watch-dog Timer Control Register (WDTC)
Figure 10.2-1 shows the bit configuration of the watch-dog timer control register (WDTC).
Figure 10.2-1 Watch-dog Timer Control Register (WDTC)
7
PONR
(R)
(X)
Address: 0000A8H
Read/write→
Initial value→
6
STBR
(R)
(X)
5
WRST
(R)
(X)
4
ERST
(R)
(X)
3
SRST
(R)
(X)
2
WTE
(W)
(1)
1
WT1
(W)
(1)
←Bit No.
0
WT0
(W)
(1)
WDTC
[bit7 to bit3] PONR, STBR, WRST, ERST, and SRST
These flags indicate the reset causes. The flags are set upon a reset as described in Table
10.2-1.
All bits are cleared to "0" after the WDTC register is read. These bits are read-only bits. At
power-on, the values of reset cause bits other than PONR bit are not defined. When the
PONR bit is "1", ensure that the values of the bits other than PONR bit are ignored.
Table 10.2-1 Reset Cause Bits and Reset Causes
Reset cause
PONR
STBR
WRST
ERST
SRST
Power-on
1
-
-
-
-
Hardware standby
*
1
*
*
*
Watch-dog timer
*
*
1
*
*
External pin
*
*
*
1
*
RST bit
*
*
*
*
1
*: The previous value is maintained.
[bit2] WTE
While the watch-dog timer is stopped, writing "0" to this bit activates the watch-dog timer.
Subsequently, writing 0 clears the watch-dog timer counter. Writing "1" has no effect.
The watch-dog timer is stopped by power-on, hardware standby, or reset by watch-dog timer.
"1" is always read from this bit.
164
CHAPTER 10 WATCH-DOG TIMER
[bit1 and bit0] WT1 and WT0
These bits are used to select the watch-dog timer interval.
Only the data items written during watch-dog timer activation are valid. Data items that are
written at any other time are ignored. In the two clocks system parts, the clock signal input to
the watch-dog timer is selected according to the values of the WDCS bit of the watch timer
control register (WTC) (timebase timer and watch timer). Table 10.2-2 lists the setting for the
interval time.
Table 10.2-2 Access to WT1 and WT0 (Read-only)
WDCS
WT1
Interval time*
WT0
Minimum
Maximum
1
0
0
About 3.58ms
About 4.61ms
1
0
1
About 14.33ms
About 18.43ms
1
1
0
About 57.23ms
About 73.73ms
1
1
1
About 458.75ms
About 589.82ms
0
0
0
About 0.457s
About 0.576s
0
0
1
About 3.584s
About 4.608s
0
1
0
About 7.167s
About 9.216s
0
1
1
About 14.336s
About 18.432s
*: For a source oscillation of 4 MHz. For a sub-oscillation clock of 32 kHz.
Note:
The interval time uses the carry signal of the timebase timer or watch timer as a count clock. If the
timebase timer or watch timer is cleared, the interval time of the watch-dog timer may become long.
Note that the timebase timer is also cleared by writing "0" to the TBR bit in the timebase timer control
register (TBTC), transition from main clock mode to PLL clock mode, transition from subclock mode
to main clock mode and transition from subclock mode to PLL clock mode.
165
CHAPTER 10 WATCH-DOG TIMER
10.3 Watch-dog Timer Operation
The watch-dog timer function enables detection of program surge. If 0 is not written to
the WTE bit of the watch-dog timer within the specified time due to a program surge, the
watch-dog timer issues a watch-dog reset request.
■ Activating the Watch-dog Timer
The watch-dog timer is activated by writing "0" to the WTE bit of the watch-dog timer control
register (WDTC) while the watch-dog timer is stopped. At the same time, the WT1 and WT0 bits
are used to set the watch-dog timer interval. Only the interval setting specified during activation is
valid.
■ Resetting the Watch-dog Timer
When the watch-dog timer is activated, the 2-bit watch-dog counter must be program-cleared
periodically. Specifically, 0 must be periodically written to the WTE bit of the watch-dog timer
control register (WDTC). The watch-dog timer consists of a 2-bit counter that uses the carry
signals of the timebase timer as a clock source. When the timebase timer is cleared, the watchdog reset interval may exceed the setting.
Figure 10.3-1 is a diagram of the watch-dog timer operation.
Figure 10.3-1 Watch-dog Timer Operation
Time base
Watch-dog
00B
01B
10B
00B
01B
10B
11B
00B
WTE write
Watch-dog activation
Watch-dog clear
Watch-dog reset occurs
■ Stopping the Watch-dog Counter
Once activated, the watch-dog timer is initialized and stopped only by power-on, hardware
standby, or reset by watch-dog. Reset by an external pin or software merely clears the watch-dog
counter without stopping the watch-dog function.
■ Clearing the Watch-dog Counter
The watch-dog counter is cleared by writing "0" to the WTE bit of the watch-dog timer control
register (WDTC), occurrence of a reset, or transition to sleep mode, stop mode, or hold
acknowledge signal.
166
CHAPTER 11
WATCH TIMER
This chapter explains the functions and operations of the watch timer.
The watch timer cannot be used in the single clock (system) parts.
11.1 Outline of Watch Timer
11.2 Watch Timer Control Register (WTC)
11.3 Watch Timer Operation
167
CHAPTER 11 WATCH TIMER
11.1 Outline of Watch Timer
The watch timer consists of a 15-bit timer and a circuit that controls an interval
interrupt. The watch timer uses subclock signals regardless of the MCS bit and SCS bit
of the clock selection register (CKSCR).
■ Watch Timer Register
Figure 11.1-1 shows the bit configuration of the watch timer control register (WTC).
Figure 11.1-1 Watch Timer Control Register (WTC)
Address: 0000AAH
Read/write→
Initial value→
168
7
WDCS
(R/W)
(1)
6
SCE
(R/W)
(X)
5
WTIE
(R/W)
(0)
4
WTOF
(R/W)
(0)
3
WTR
(R/W)
(0)
2
WTC2
(R/W)
(0)
1
WTC1
(R/W)
(0)
0
←Bit No.
WTC0
WTC
(R/W)
(0)
CHAPTER 11 WATCH TIMER
■ Block Diagram of Watch Timer
Figure 11.1-2 Block Diagram of Watch Timer
Main clock
TBTC
TBC1
Selector
TBC0
212
214
216
219
TBTRES
Clock input
Timebase timer
212
214
216
219
TBR
TBIE
AND
Q
S
R
TBOF
Time base
interrupt
WDTC
OF
Selector
WT0
Internal data bus
Watch-dog reset
generation circuit
2-bit counter
WT1
CLR
CLR
WDGRST
To internal reset
generation circuit
WTE
WTC
WDCS
AND
SCE
Q
SCM
Power-on reset
Subclock stop
S
R
210
WTC2
WTC1
WTC0
Selector
WTR
WTIE
Q
S
R
214
215
Watch timer
WTRES
AND
213
Clock input
Subclock/4
WTOF
Timer
interrupt
WDTC
PONR
From power-on generation
STBR
From hardware standby
control circuit
WRST
ERST
RST pin
SRST
From RST bit of
LPMCR register
169
CHAPTER 11 WATCH TIMER
11.2 Watch Timer Control Register (WTC)
The watch timer control register (WTC) controls the operation of the watch timer and
the interval interrupt time.
■ Watch Timer Control Register (WTC)
Figure 11.2-1 shows the bit configuration of the watch timer control register (WTC).
Figure 11.2-1 Watch Timer Control Register (WTC)
Address: 0000AAH
Read/write→
Initial value→
7
WDCS
(R/W)
(1)
6
SCE
(R/W)
(X)
5
WTIE
(R/W)
(0)
4
WTOF
(R/W)
(0)
3
WTR
(R/W)
(0)
2
WTC2
(R/W)
(0)
1
WTC1
(R/W)
(0)
0
←Bit No.
WTC0
WTC
(R/W)
(0)
[bit7] WDCS
The WDCS bit is used to specify whether the clock signal of the watch timer or timebase timer
is used as the input clock of the watch-dog timer.
< For the main clock or PLL clock mode >
WDCS 1: Timebase timer clock
2: Watch timer clock
< For the subclock mode >
WDCS : This bit must be written to "0".
This bit is initialized to "1" by a power-on reset.
Note:
If WDCS is set to "1", the watch-dog timer counter may be run because the timebase timer output
and watch timer output are asynchronous. If WDCS is set to "1", the watch-dog timer must be
cleared before and after the clock mode is changed.
If the timebase timer is used as the input clock of the watch-dog timer in the subclock mode
(WDCS=1), the watch-dog timer stops. The watch timer must be selected as the input clock of the
watch-dog timer (WDCS=0), when the watch-dog timer is used in the subclock mode.
[bit6] SCE
The SCE bit indicates that the subclock oscillation stabilization wait time has elapsed. When
this bit is "0", the oscillation stabilization wait time is currently in progress. The oscillation
stabilization wait time is fixed to 214 cycles (subclock). This bit is initialized to "0" by a poweron reset or stop.
[bit5] WTIE
The WTIE bit enables an interval interrupt by the watch timer. When this bit is "1", the interrupt
is enabled. When this bit is "0", the interrupt is disabled. This bit is initialized to "0" by a reset.
This bit can be read and written to.
170
CHAPTER 11 WATCH TIMER
[bit4] WTOF
The WTOF bit is the watch timer interrupt flag. When the WTIE bit is "1" and WTOF is set to
"1", an interrupt request is issued. This bit is set to "1" at each interval specified by the WTC1
and WTC0 bits. This bit is cleared by writing "0", transition to stop mode or hardware standby
mode, or a reset. Writing "1" has no effect.
During read operation using a read-modify-write instruction, "1" is always read from this bit.
[bit3] WTR
The WTR bit clears all bits of the watch timer counter to "0". Writing "0" to this bit clears the
watch counter. Writing "1" has no effect. The value read from this bit is always "1".
[bit2, bit1, and bit0] WTC2, WTC1, WTC0
The WTC2, WTC1, and WTC0 bits set the watch timer interval time. Table 11.2-1 lists the
settings for the interval time. These bits are initialized to 000B by a reset. These bits can be
read and written to.
When data is written to these bits, bit4 (WTOF) should be cleared.
Table 11.2-1 Settings for the Watch Timer Interval
WTC2
WTC1
WTC0
Interval (subclock: 32kHz)
0
0
0
62.5 ms
0
0
1
125 ms
0
1
0
250 ms
0
1
1
500 ms
1
0
0
1.000 s
1
0
1
2.000 s
1
1
0
4.000 s
1
1
1
-
171
CHAPTER 11 WATCH TIMER
11.3 Watch Timer Operation
The watch timer functions as a watch-dog counter clock source, a timer for waiting for
the subclock oscillation stabilization time, and an interval timer for generating
interrupts at specified intervals.
■ Watch Timer
The watch timer consists of a 15-bit counter that counts oscillation inputs generated by the
subclock. While the subclock is input, the watch timer keeps counting. The watch timer is cleared
by a power-on reset or writing "0" to the WTR bit of the watch timer control register (WTC).
Notes:
•
Clearing the watch timer counter affects the watch-dog counter and interval interrupts that use
watch timer output.
•
To clear the watch timer by writing "0" to the WTR bit in the watch timer control register
(WTC), set the WTIE bit to "0" and set the watch timer to interrupt inhibited state. Before
permitting an interrupt, clear the interrupt request issued by writing "0" to the WTOF flag.
■ Interval Interrupt Function of Watch Timer
The interval interrupt function generates interrupts at specified intervals according to the carry
signals of the watch counter. The WTOF flag is set at each intervals specified by the WTC1 and
WTC0 bits of the watch timer control register (WTC). The timing of flag setting is based on the
time when the watch timer was last cleared.
On transition to stop or hardware standby mode, the watch timer is used as a timer for subclock
oscillation stabilization time upon recovery, and the WTOF flag is immediately cleared upon mode
transition.
■ Setting Operation Clock for Watch-dog Timer
The clock source of the watch-dog timer can be set by the watch-dog clock selection bit (WDCS)
bit in the watch timer control register (WTC). When the subclock is used for the machine clock,
select the watch timer output with the WDCS bit setting to "0". If the mode transits to the subclock
mode with the WDCS bit setting to "1", the watch-dog timer stops.
172
CHAPTER 12
16-BIT I/O TIMER
This chapter explains the functions and operations of the 16-bit I/O timer.
12.1 Outline of 16-Bit I/O Timer
12.2 16-bit I/O Timer Registers
12.3 16-bit Free Running Timer
12.4 Output Compare
12.5 Input Capture
173
CHAPTER 12 16-BIT I/O TIMER
12.1 Outline of 16-Bit I/O Timer
MB90540/545 series products contain one 16-bit free running timer module, two output
compare modules, and four input capture modules, and support eight input channels
and four output channels. The following sections only describes the 16-bit free running
timer, Output Compare 0/1 and Input Capture 0/1.
The remaining modules have the identical functions and the register addresses should
be found in the I/O map.
■ 16-bit Free Running Timer
The 16-bit free running timer consists of a 16-bit up counter, control register, and prescaler. The
values output from this timer counter are used as the base timer for input capture and output
compare.
•
Four counter clocks are available.
Internal clock: φ/4, φ/16, φ/64, φ/256
•
An interrupt can be generated upon a counter overflow or a match with compare register 0.
•
The counter value can be initialized to "0000H" upon a reset, software clear, or a match with
compare register 0.
■ Output Compare (2 Channels Per One Module)
The output compare module consists of two 16-bit compare registers, compare output latch, and
control register.
When the 16-bit free running timer value matches the compare register value, the output level is
reversed and an interrupt can be issued.
•
The two compare registers can be used independently.
Output pins and interrupt flags corresponding to compare registers
•
Output pins can be controlled by pairing the two compare registers.
Output pins can be reversed by using the two compare registers.
•
Initial values for output pins can be set.
•
Interrupts can be generated upon a compare match.
■ Input Capture (2 Channels Per One Module)
The input capture module consists of two 16-bit capture registers and control registers
corresponding to two independent external input pins. The 16-bit free running timer value can be
stored in the capture register and an interrupt is issued simultaneously upon detection of an edge
of a signal input from an external input pin.
174
•
The detection edge of an external input signal can be specified.
Rising, falling, or both edges
•
Two input channels can operate independently.
•
An interrupt can be issued upon a valid edge of an external input signal.
The intelligent I/O service can be activated upon an input capture interrupt.
CHAPTER 12 16-BIT I/O TIMER
■ Block Diagram of 16-bit I/O Timer
Figure 12.1-1 shows a block diagram of the 16-bit I/O timer.
Figure 12.1-1 Block Diagram of 16-bit I/O Timer
Control logic
To each block
Interrupt
16-bit free-run timer
16-bit timer 1
Internal data bus
Clear
Output compare 0
Compare register 0
T Q
OUT0
T Q
OUT1
Output compare 1
Compare register 1
Input capture 0
Capture register 0
Edge selection
IN0
Edge selection
IN1
Input capture 1
Capture register 1
175
CHAPTER 12 16-BIT I/O TIMER
12.2 16-bit I/O Timer Registers
The 16-bit I/O timer has the following three registers:
• 16-bit free running timer register
• 16-bit output compare register
• 16-bit input capture register
■ 16-bit I/O Timer Registers
Figure 12.2-1 shows the bit configuration of the 16-bit I/O timer registers.
Figure 12.2-1 16-bit I/O Timer Registers
16-bit free running timer register
15
Address: 00006CH
0
TCDT
Timer counter data register
7
16-bit output capture register
15
Address: 003928H
00392AH
15
Address: 000058H
16-bit input capture register
15
Address: 003918H
00391AH
0
TCCS
Address: 00006EH
0
OCCP0/1
Output compare registers 0 and 1
0
OCS1
OCS0
176
Output compare control status
registers 0 and 1
0
IPCP0/1
Input capture data registers 0 and 1
7
Address: 00004CH
Timer counter control status register
0
ICS01
Input capture control status registers
0 and 1
CHAPTER 12 16-BIT I/O TIMER
12.3 16-bit Free Running Timer
The 16-bit free running timer consists of a 16-bit up counter and a control status
register. The count values are used as the base timer for the output compares and input
captures.
• Four counter clock are available.
• An interrupt can be generated upon a counter value overflow.
• The counter value can be initialized upon a match with compare register 0, depending
on the mode.
■ 16-bit Free Running Timer Block Diagram
Figure 12.3-1 16-bit Free Running Timer Block Diagram
Internal data bus
Interrupt request
IVF
IVFE
STOP MODE CLR
CLK1
Machine clock
φ
Divider
CLK0
(TCCS)
Comparator 0
16-bit free-running time
Clock
Count value output
T15
to
T00
177
CHAPTER 12 16-BIT I/O TIMER
12.3.1 16-bit Free Running Timer Registers
The data register can read the count value of the 16-bit free running timer. The counter
value is cleared to "0000B" upon a reset. The timer value can be set by writing a value to
this register. However, ensure that the value is written while the operation is stopped
(STOP=1).
The data register must be accessed by the word access instructions.
■ Timer Counter Data Register (TCDT)
Figure 12.3-2 shows the bit configuration of the timer counter data register (TCDT).
Figure 12.3-2 Timer Counter Data Register (TCDT)
15
T15
(R/W)
(0)
14
T14
(R/W)
(0)
13
T13
(R/W)
(0)
12
T12
(R/W)
(0)
11
T11
(R/W)
(0)
10
T10
(R/W)
(0)
9
T09
(R/W)
(0)
8
T08
(R/W)
(0)
←Bit No.
Address: 00006DH
Read/write→
Initial value→
6
T06
(R/W)
(0)
5
T05
(R/W)
(0)
4
T04
(R/W)
(0)
3
T03
(R/W)
(0)
2
T02
(R/W)
(0)
1
T01
(R/W)
(0)
0
T00
(R/W)
(0)
←Bit No.
Address: 00006CH
Read/write→
Initial value→
7
T07
(R/W)
(0)
TCDT
The 16-bit free running timer is initialized upon the following factors:
178
•
Reset
•
Clear bit (CLR) of timer counter control status register
•
A match between compare register 0 and the timer counter value (Setting the mode is
required).
CHAPTER 12 16-BIT I/O TIMER
12.3.2 Timer Counter Control Status Register (TCCS)
The timer counter control status register (TCCS) sets the operation mode of the 16-bit
free running timer, starts and stops the 16-bit free running timer, and controls
interrupts.
■ Timer Counter Control Status Register (TCCS)
Figure 12.3-3 shows the bit configuration of the timer counter control status register (TCCS).
Figure 12.3-3 Timer Counter Control Status Register (TCCS)
7
6
Address: 00006EH Reserved IVF
Read/write→ (R/W) (R/W)
Initial value→
(0)
(0)
5
IVFE
(R/W)
(0)
4
3
2
STOP MODE CLR
(R/W) (R/W) (R/W)
(0)
(0)
(0)
1
CLK1
(R/W)
(0)
0
←Bit No.
CLK0
TCCS
(R/W)
(0)
[bit7] Reserved bit
Always write "0" to this bit.
[bit6] IVF
This bit is an interrupt request flag of the 16-bit free running timer.
If the 16-bit free running timer overflows, or if the counter is cleared by a match with compare
register 0, "1" is set to this bit.
An interrupt is issued if the interrupt request enable bit (bit5: IVFE) is set.
This bit is cleared by writing "0". Writing "1" has no effect.
"1" is always read by a read-modify-write instruction.
0
No interrupt request (initial value)
1
Interrupt request
[bit5] IVFE
IVFE is an interrupt enable bit of the 16-bit free running timer. While this bit is "1", an interrupt
is issued if "1" is set to the interrupt flag (bit5: IVF).
0
Interrupt disabled (initial value)
1
Interrupt enabled
179
CHAPTER 12 16-BIT I/O TIMER
[bit4] STOP
The STOP bit is used to stop the 16-bit free running timer.
Writing "1" to this bit stops the timer. Writing "0" starts the timer count.
0
Count enabled (operation) (initial value)
1
Count disabled (stop)
Note:
The output compare operation stops when the 16-bit free running timer stops.
[bit3] MODE
The MODE bit is used to set the initialization condition of the 16-bit free running timer.
When "0" is set, the counter value can be initialized by reset or a clear bit (bit2: CLR).
When "1" is set, the counter value can be initialized by a match with compare register 0 in
addition to reset and a clear bit (bit2: CLR).
0
Initialization by reset or clear bit (initial value)
1
Initialization by reset, clear bit, or compare register 0
Note:
The clear bit and a match with the compare register initialize the timer at the change point of the
timer value.
[bit2] CLR
The CLR bit initializes the operating 16-bit free running timer value to "0000".
When "1" is set, the counter value is initialized to "0000". Writing "0" has no effect. "0" is always
read from this bit. The counter value is initialized at the change point of the count value.
0
No effect (initial value)
1
The counter value is initialized to "0000".
Note:
To initialize the counter value while the timer is stopped, write "0000H" to the data register.
180
CHAPTER 12 16-BIT I/O TIMER
[bit1 and bit0] CLK1 and CLK0
CLK1 and CLK0 are used to select the count clock for the 16-bit free running timer. The clock is
updated immediately after a value is written to these bits. Therefore, ensure that the output
compare and input capture operations are stopped before a value is written to these bits.
CLK1
CLK0
Count clock
φ=16 MHz
φ=8 MHz
φ=4 MHz
φ=2 MHz
0
0
φ/4
0.25 µs
0.5 µs
1 µs
2 µs
0
1
φ/16
1 µs
2 µs
4 µs
8 µs
1
0
φ/64
4 µs
8 µs
16 µs
32 µs
1
1
φ/256
16 µs
32 µs
64 µs
128 µs
Note: φ = Machine clock
181
CHAPTER 12 16-BIT I/O TIMER
12.3.3 16-bit Free Running Timer Operation
The 16-bit free running timer starts counting from counter value "0000H" after the reset
is released. The counter value is used as the reference time for the 16-bit output
compare and 16-bit input capture operations.
■ 16-bit Free Running Timer Operation
The counter value is cleared in the following conditions:
•
When an overflow occurs.
•
When a match with the output compare register 0 occurs. (Mode setting is required.)
•
When "1" is written to the CLR bit of the TCCS register during operation.
•
When "0000" is written to the TCDT register during stop.
•
Reset
An interrupt can be generated when an overflow occurs or when the counter is cleared by a
match with the compare register 0. (Compare match interrupts require mode setting.)
Figure 12.3-4 Clearing the Counter by an Overflow
Counter value
Overflow
FFFF H
BFFF H
7FFF H
3FFF H
Time
0000 H
Reset
Interrupt
Figure 12.3-5 Clearing the Counter upon a Match with Output Compare Register 0
Counter value
FFFF H
BFFF H
Match
Match
7FFF H
3FFF H
Time
0000 H
Reset
Compare
register value
Interrupt
182
BFFFH
CHAPTER 12 16-BIT I/O TIMER
■ 16-bit Free Running Timer Timing
As shown in Figure 12.3-6, the 16-bit free running timer is counted up based on the input clock
(internal or external clock). When an external clock is selected, the 16-bit free running timer is
counted at the rising edge.
Figure 12.3-6 16-bit Free Running Timer Count Timing
Machine clock φ
External clock
input
Count clock
N
Counter value
N+1
As shown in Figure 12.3-7, the counter can be cleared by a reset, software clear, or match with
compare register 0. For a reset or software clear, the counter is immediately cleared. For a match
with compare register 0, the counter is cleared synchronously with the count timing.
Figure 12.3-7 16-bit Free Running Timer Clear Timing (Match with the Compare Register 0)
Machine clock φ
N
Compare
register value
Compare match
Counter value
N
0000H
183
CHAPTER 12 16-BIT I/O TIMER
12.4 Output Compare
The output compare module consists of two 16-bit compare registers, two compare
output pins, and control register. If the value written to the compare register of this
module matches the 16-bit free running timer value, the output level of the pin can be
reversed and an interrupt can be issued.
■ Output Compare
•
Two compare registers exist that can be used independently. Depending on the setting, the
two compare registers can be used to control pin outputs.
•
The initial value for the pin output can be specified.
•
An interrupt can be issued by the compare match.
■ Output Compare Block Diagram
Figure 12.4-1 Output Compare Block Diagram
16-bit timer counter value (T15 to T00)
T
Compare control
Q
OTE0
OUT0
OTE1
OUT1
Internal data bus
Compare register 0
16-bit timer counter value (T15 to T00)
CMOD
T
Compare control
Q
Compare register 1
ICP1 ICP0 ICE1 ICE0
Controller
Control blocks
184
Compare 1
interrupt
Compare 0
interrupt
CHAPTER 12 16-BIT I/O TIMER
12.4.1 Output Compare Register (OCCP0, OCCP1)
These 16-bit compare registers are compared with the 16-bit free running timer. Since
the initial register values are undefined, set appropriate value before enabling the
operation. These registers must be accessed by the word access instructions. When
the value of the register matches that of the 16-bit free running timer, a compare signal
is generated and the output compare interrupt flag is set. If output is enabled, the
output level corresponding to the compare register is reversed.
■ Output Compare Register (OCCP0, OCCP1)
Figure 12.4-2 shows the bit configuration of the output compare register (OCCP0, OCCP1).
Figure 12.4-2 Output Compare Register (OCCP0,OCCP1)
Address: 003929H
00392BH
Read/write→
Initial value→
15
C15
(R/W)
(X)
14
C14
(R/W)
(X)
13
C13
(R/W)
(X)
12
C12
(R/W)
(X)
11
C11
(R/W)
(X)
10
C10
(R/W)
(X)
9
C09
(R/W)
(X)
8
C08
(R/W)
(X)
←Bit No.
Address: 003928H
00392AH
Read/write→
Initial value→
7
C07
(R/W)
(X)
6
C06
(R/W)
(X)
5
C05
(R/W)
(X)
4
C04
(R/W)
(X)
3
C03
(R/W)
(X)
2
C02
(R/W)
(X)
1
C01
(R/W)
(X)
0
C00
(R/W)
(X)
←Bit No.
OCCP0, OCCP1
185
CHAPTER 12 16-BIT I/O TIMER
12.4.2 Control Status Register of Output Compare (OCS0/OCS1)
The control status register (OCS0/OCS1)sets the operation mode of output compare,
starts and stops output compare, controls interrupts, and sets the external output pins.
■ Control Status Register of Output Compare (OCS0/OCS1)
Figure 12.4-3 shows the bit configuration of the control status register of output compare (OCS0/
OCS1).
Figure 12.4-3 Control Status Register of Output Compare (OCS0/OCS1)
15
⎯
(-)
(-)
14
⎯
(-)
(-)
13
⎯
(-)
(-)
12
CMOD
(R/W)
(0)
11
OTE1
(R/W)
(0)
10
OTE0
(R/W)
(0)
9
OTD1
(R/W)
(0)
8
OTD0
(R/W)
(0)
←Bit No.
Address: 000059H
Read/write→
Initial value→
7
ICP1
(R/W)
(0)
6
ICP0
(R/W)
(0)
5
ICE1
(R/W)
(0)
4
ICE0
(R/W)
(0)
3
⎯
(-)
(-)
2
⎯
(-)
(-)
1
CST1
(R/W)
(0)
0
CST0
(R/W)
(0)
←Bit No.
Address: 000058H
Read/write→
Initial value→
OCS0/OCS1
[bit15, bit14, and bit13] Unused bits
[bit12] CMOD
CMOD is used to switch the pin output level reverse operation mode upon a match while pin
output is enabled (OTE1=1 or OTE0=1).
•
•
186
When CMOD=0 (initial value), the output level of the pin corresponding to the compare
register is reversed.
•
OUT0: The level is reversed upon a match with compare register 0.
•
OUT1: The level is reversed upon a match with compare register 1.
When CMOD=1, the output level is reversed for the compare register 0 in the same manner as
for CMOD=0. The output level of the pin corresponding to compare register 1 (OUT1),
however, is reversed upon a match with compare register 0 or 1. If compare registers 0 and 1
have the same value, the same operation as with a single compare register is performed.
•
OUT0: The level is reversed upon a match with compare register 0.
•
OUT1: The level is reversed upon a match with compare register 0 or 1.
CHAPTER 12 16-BIT I/O TIMER
[bit11 and bit10] OTE1 and OTE0
These bits are used to enable the output compare output pins. The initial value for these bits is
"0".
0
General-purpose port (initial value).
1
Output compare pin output.
Note:
OTE1: Corresponds to output compare 1 (OUT1).
OTE0: Corresponds to output compare 0 (OUT0).
[bit9 and bit8] OTD1 and OTD0
These bits are used to change the pin output level when the output compare pin output is
enabled. The initial value of the compare pin output is "0". Ensure that the compare operation
is stopped before a value is written. When read, these bits indicate the output compare pin
output value.
0
Sets "0" for the compare pin output (initial value).
1
Sets "1" for the compare pin output.
Note:
OTD1: Corresponds to output compare 1.
OTD0: Corresponds to output compare 0.
[bit7 and bit6] ICP1 and ICP0
These bits are used as output compare interrupt flags. "1" is set to these bits when the
compare register value matches the 16-bit free running timer value. While the interrupt request
bits (ICE1 and ICE0) are enabled, an output compare interrupt occurs when the ICP1 and
ICP0 bits are set. These bits are cleared by writing "0".
Writing "1" has no effect. "1" is always read by a read-modify-write instruction.
0
No compare match (initial value)
1
Compare match
Note:
ICP1: Corresponds to output compare 1.
ICP0: Corresponds to output compare 0.
187
CHAPTER 12 16-BIT I/O TIMER
[bit5 and bit4] ICE1 and ICE0
These bits are used as output compare interrupt enable flags. While the "1" is written to these
bits, an output compare interrupt occurs when an interrupt flag (ICP1 or ICP0) is set.
0
Output compare interrupt disabled (initial value)
1
Output compare interrupt enabled
Note:
ICE1: Corresponds to output compare 1.
ICE0: Corresponds to output compare 0.
[bit3 and bit2] Unused bits
[bit1 and bit0] CST1 and CST0
These bits are used to enable a match with 16-bit free running timer.
0
Compare operation disabled (initial value)
1
Compare operation enabled
Ensure that a value is written to the compare register before the compare operation is
enabled.
Note:
CST1: Corresponds to output compare 1.
CST0: Corresponds to output compare 0.
Since output compare is synchronized with the 16-bit free running timer clock, stopping the 16-bit
free running timer stops compare operation.
188
CHAPTER 12 16-BIT I/O TIMER
12.4.3 16-bit Output Compare Operation
The 16-bit output compare compares the specified compare register value with a 16-bit
freerun timer value.
When a match occurs, it can set the interrupt request flag and reverse the output level.
■ Sample of Output Waveform when Compare Registers 0 and 1 are Used (The Initial Output Value is "0".)
Figure 12.4-4 Sample of Output Waveform when Compare Registers 0 and 1 are Used
(The Initial Output Value is "0".)
Counter value
FFFFH
BFFF H
7FFFH
3FFFH
Time
0000H
Reset
Compare register
0 value
Compare register
1 value
OUT0
BFFFH
7FFFH
OUT1
Compare 0
interrupt
Compare 1
interrupt
The output level can be changed using two compare registers (when CMOD=1).
189
CHAPTER 12 16-BIT I/O TIMER
■ Sample of a Output Waveform with Two Compare Registers (The Initial Output Value is "0".)
Figure 12.4-5 Sample of a Output Waveform with Two Compare Registers
(The Initial Output Value is "0".)
Counter value
FFFFH
BFFF H
7FFFH
3FFFH
0000H
Time
Reset
BFFFH
Compare register
0 value
Compare register
1 value
OUT0
7FFFH
Corresponds to compare 0
Corresponds to
compare 0 and 1
OUT1
Compare 0
interrupt
Compare 1
interrupt
■ Output Compare Timing
In output compare operation, a compare match signal is generated when the free running timer
value matches the specified compare register value. The output value can be reversed and an
interrupt can be issued. The output reverse timing upon a compare match is synchronized with
the counter count timing.
As shown in Figure 12.4-6, when the compare register is updated, comparison with the counter
value is not performed.
Figure 12.4-6 Compare Operation upon Update of Compare Register
N
Counter value
N+1
N+2
N+3
No match signal is generated.
Compare register
0 value
Compare register
0 write
M
Compare register
1 value
Compare register
1 write
M
N+1
N+3
Compare 0 stop
Compare 1 stop
Figure 12.4-7 shows the output compare interrupt timing, and Figure 12.4-8 shows the output
compare output pin change timing.
190
CHAPTER 12 16-BIT I/O TIMER
Figure 12.4-7 Interrupt Timing of Output Compare
Machine clock φ
Counter value
N
N+1
Compare register
value
N
Compare match
Interrupt
Figure 12.4-8 Output Pin Change Timing of Output Compare
Counter value
Compare register
value
N
N+1
N
N+1
N
Compare match
signal
Pin output
191
CHAPTER 12 16-BIT I/O TIMER
12.5 Input Capture
Input capture detects a rising or falling edge or both edges of an external input signal
and stores a 16-bit free running timer value at that time in a register. In addition, input
capture can generate an interrupt upon detection of an edge. Input capture consists of
an input capture data register and a control status register.
■ Input Capture
Each input capture has a corresponding external input pin.
❍ The detection edge of an external input can be selected from the following 3 types:
Rising edge
Falling edge
Both edges
❍ An interrupt can be generated upon detection of a valid edge of an external input.
■ Input Capture Block Diagram
Figure 12.5-1 Input Capture Block Diagram
Internal data bus
IN0
Edge detection
Capture data register 0
EG11 EG10 EG01 EG00
16-bit timer counter value (T15 to T00)
Edge detection
Capture data register 1
ICP1
ICP0
ICE1
IN1
ICE0
Interrupt
Interrupt
192
CHAPTER 12 16-BIT I/O TIMER
12.5.1 Input Capture Register Details
Input capture has the two registers listed. These registers store a value from the 16-bit
timer when a valid edge of the corresponding external pin input waveform is detected.
(The registers must be accessed in word mode. No values can be written to the
registers.)
■ Input Capture Data Register (IPCP0/1)
Figure 12.5-2 shows the bit configuration of the input capture data register (IPCP0/1).
Figure 12.5-2 Input Capture Data Register (IPCP0/1)
Address: 003919H
00391BH
Read/write→
Initial value→
15
CP15
(R)
(X)
14
CP14
(R)
(X)
13
CP13
(R)
(X)
12
CP12
(R)
(X)
11
CP11
(R)
(X)
10
CP10
(R)
(X)
9
CP09
(R)
(X)
8
CP08
(R)
(X)
←Bit No.
Address: 003918H
00391AH
Read/write→
Initial value→
7
CP07
(R)
(X)
6
CP06
(R)
(X)
5
CP05
(R)
(X)
4
CP04
(R)
(X)
3
CP03
(R)
(X)
2
CP02
(R)
(X)
1
CP01
(R)
(X)
0
CP00
(R)
(X)
←Bit No.
IPCP0/1
■ Input Capture Control Status Register (ICS01)
Figure 12.5-3 shows the bit configuration of the input capture control status register (ICS01).
Figure 12.5-3 Input Capture Control Status Register (ICS01)
Address: 00004CH
Read/write→
Initial value→
7
ICP1
(R/W)
(0)
6
ICP0
(R/W)
(0)
5
ICE1
(R/W)
(0)
4
ICE0
(R/W)
(0)
3
EG11
(R/W)
(0)
2
EG10
(R/W)
(0)
1
EG01
(R/W)
(0)
0
EG00
(R/W)
(0)
←Bit No.
ICS01
[bit7 and bit6] ICP1 and ICP0
These bits are used as input capture interrupt flags. "1" is set to this bit upon detection of a
valid edge of an external input pin. While the interrupt enable bits (ICE0 and ICE1) are set, an
interrupt can be generated upon detection of a valid edge.
These bits are cleared by writing "0". Writing "1" has no effect. "1" is always read by a readmodify-write instruction.
0
No valid edge detection (initial value)
1
Valid edge detection
193
CHAPTER 12 16-BIT I/O TIMER
Note:
ICP0: Corresponds to input capture 0.
ICP1: Corresponds to input capture 1.
[bit5 and bit4] ICE1 and ICE0
These bits are used to enable input capture interrupts. While these bits are "1", an input
capture interrupt is generated when the interrupt flag (ICP0 or ICP1) is set.
0
Interrupt disabled (initial value)
1
Interrupt enabled
Note:
ICE0: Corresponds to input capture 0.
ICE1: Corresponds to input capture 1.
[bit3, bit2, bit1, and bit0] EG11, EG10, EG01, and EG00
These bits are used to specify the valid edge polarity of the external inputs. These bits are
also used to enable input capture operation.
EG11
EG01
EG10
EG00
0
0
No edge detection (stop) (initial value)
0
1
Rising edge detection ↑
1
0
Falling edge detection ↓
1
1
Both edge detection ↑↓
Note:
EG01 and EG00: Correspond to input capture 0.
EG11 and EG10: Correspond to input capture 1.
194
Edge detection polarity
CHAPTER 12 16-BIT I/O TIMER
12.5.2 16-bit Input Capture Operation
In 16-bit input capture operation, an interrupt can be generated upon detection of at the
specified valid edge, fetching the 16-bit free running timer value to the capture register.
■ Sample of Input Capture Fetch Timing
•
Capture 0: Rising edge
•
Capture 1: Falling edge
•
Capture example: Both edges (for example)
Figure 12.5-4 Sample of Input Capture Fetch Timing
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
IN0
IN1
IN example
Capture 0
Undefined
Capture 1
Undefined
Capture example
Undefined
3FFFH
7FFFH
BFFFH
3FFFH
Capture 0 interrupt
Capture 1 interrupt
Capture example
interrupt
Capture 0 = Rising edge
Capture 1 = Falling edge
Capture example = Both edge (for example)
195
CHAPTER 12 16-BIT I/O TIMER
■ Input Capture Input Timing
Figure 12.5-5 Capture Timing for Input Signals
Machine clock
φ
Counter value
Input capture
input
N
N+1
Valid edge
Capture signal
Input capture
register
Interrupt
196
N+1
CHAPTER 13
16-BIT RELOAD TIMER (WITH EVENT
COUNT FUNCTION)
This chapter explains the functions and operations of the 16-bit reload timer (with the
event count function).
13.1 Outline of 16-Bit Reload Timer (with Event Count Function)
13.2 Registers of 16-Bit Reload Timer
13.3 Internal Clock and External Clock Operations of 16-bit Reload Timer
13.4 Underflow Operation of 16-bit Reload Timer
13.5 Output Pin Functions of 16-bit Reload Timer
13.6 Counter Operation State
197
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.1 Outline of 16-Bit Reload Timer (with Event Count Function)
The 16-bit reload timer consists of a 16-bit down-counter, a 16-bit reload register, one
input pin (TIN) and one output pin (TOT), and a control register. The input clock can be
selected from one external clock and three types of internal clock.
■ Outline of 16-bit Reload Timer (with Event Count Function)
The output pin (TOT) outputs a toggle output waveform in reload mode and outputs a square
waveform indicating counting in one-shot mode. The input pin (TIN) is used for event input in
event count mode, and can be used for trigger input or gate input in internal clock mode.
MB90540/545 series products have two 16-bit reload timers.
■ Intelligent I/O Service (EI2OS) Function and Interrupts
The timer includes a circuit that supports EI2OS. The timer can activate EI2OS when an
underflow occurs.
198
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
■ Block Diagram of 16-bit Reload Timer
Figure 13.1-1 shows a block diagram of the 16-bit reload timer.
Figure 13.1-1 Block Diagram of 16-bit Reload Timer
16
16-bit reload register
8
Reload
Internal data bus
RELD
16-bit down-counter
16
OUTE
UF
OUTL
Available
clock judge
circuit
2
INTE
OUT
CTL.
GATE
UF
IRQ
CSL1
Clock selector
Operation
control
circuit
CSL0
CNTE
TRG
Clear
EI 2 OSCLR
Trigger
2
IN CTL
Port (TIN)
EXCK
φ
21
φ
23
Output enable
3
φ
25
Prescaler
clear
Port (TOT)
MOD2
MOD1
Machine clock
MOD0
UART baud rate (ch0)
A/DC (ch1)
3
■ Pin Name of 16-bit Reload Timer
16-bit reload timer contains two timers, and the input pin name (TIN) and output pin name (TOT)
of each timer are shown below.
Input pin (TIN)
Output pin (TOT)
Timer 1
TIN0
TOT0
Timer 2
TIN1
TOT1
199
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.2 Registers of 16-Bit Reload Timer
The 16-bit reload timer has the following two types of registers:
• Timer control status register
• 16-bit timer register/16-bit reload register
■ 16-bit Reload Timer Register
Figure 13.2-1 shows the bit configuration of the 16-bit reload timer register.
Figure 13.2-1 16-bit Reload Timer Register
Timer control status register (upper)
Address: ch0 000051H
ch1 000055H
Read/write
Initial value
15
Read/write
Initial value
200
11
10
9
—
—
CSL1
CSL0
MOD2
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
6
5
4
3
OUTE
OUTL
RELD
INTE
UF
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
15
14
13
12
11
8
Bit No.
TMCSR0/1
MOD1
(R/W)
(0)
2
MOD0
1
0
CNTE
(R/W)
(0)
10
Bit No.
TMCSR0/1
TRG
(R/W)
(0)
9
8
Bit No.
TMR0/TMRLR0
TMR1/TMRLR1
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
7
16-bit timer register (lower)/
16-bit reload register (lower)
Address: ch0 000052H
ch1
ch1 000056
00003EHH
Read/write
Initial value
12
—
16-bit timer register (upper)/
16-bit reload register (upper)
Address: ch0 000053H
ch1 000057H
Read/write
Initial value
13
—
Timer control status register (lower)
Address: ch0 000050H
ch1 000054H
14
6
5
4
3
2
1
0
Bit No.
TMR0/TMRLR0
TMR1/TMRLR1
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.2.1 Timer Control Status Register (TMCSR)
Controls the operation mode and interrupts for the 16-bit timer. Only modify bits other
than UF, CNTE, and TRG when CNTE = 0.
■ Timer Control Status Register (TMCSR)
Figure 13.2-2 shows the bit configuration of the timer control status register (TMCSR).
Figure 13.2-2 Timer Control Status Register (TMCSR)
Timer control status register (upper)
Address: ch0 000051H
ch1 000055
00003DHH
ch1
Read/write
Initial value
15
14
Read/write
Initial value
12
11
10
9
8
—
—
—
—
CSL1
CSL0
MOD2
MOD1
(—)
(—)
(—)
(—)
(R/W)
(R/W)
(R/W)
(R/W)
(—)
(—)
(—)
(—)
(0)
(0)
(0)
(0)
Timer control status register (lower)
Address: ch0 000050H
ch1 000054
00003CHH
ch1
13
7
6
5
4
3
2
MOD0
OUTE
OUTL
RELD
INTE
UF
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
1
CNTE
(R/W)
(0)
TRG
Bit No.
TMCSR0/1
0
Bit No.
TMCSR0/1
(R/W)
(0)
[bit11, bit10] CSL1, CSL0 (Clock select 1, 0)
The count clock select bits. Table 13.2-1 lists the selected clock sources.
Table 13.2-1 Clock Sources for CSL Bit Settings
CSL1
CSL0
Clock Source (Machine cycle φ = 16 MHz)
0
0
φ/21 (0.125 µs)
0
1
φ/23 (0.5 µs)
1
0
φ/25 (2.0 µs)
1
1
External event count mode
201
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
[bit9, bit8, bit7] MOD2, MOD1, MOD0
These bits set the operation mode and I/O pin functions.
The MOD2 bit selects the I/O functions. When MOD2 = "0", the input pin functions as a trigger
input. In this case, the reload register contents is loaded to the counter when an active edge is
input to the input pin and count operation proceeds. When MOD2 = "1", the timer operates in
gate counter mode and the input pin functions as a gate input. In this mode, the counter only
counts while an active level is input to the input pin.
The MOD1 and MOD0 bits set the pin functions for each mode. Table 13.2-2 and Table 13.2-3
list the MOD2, MOD1, MOD0 bit settings.
Table 13.2-2 MOD2, 1, 0 Bit Settings (1)
MOD2
MOD1
MOD0
Input Pin Function
Active Edge or Level
0
0
0
Trigger disabled
-
0
0
1
Trigger input
Rising edge
0
1
0
↑
Falling edge
0
1
1
↑
Both edges
1
×
0
Gate input
"L" level
1
×
1
↑
"H" level
Internal clock mode (CSL0, CSL1 = 00B, 01B, or 10B)
Table 13.2-3 MOD2, 1, 0 Bit Settings (2)
MOD2
MOD1
MOD0
Input Pin Function
Active Edge or Level
0
0
-
-
0
1
Trigger input
Rising edge
1
0
↑
Falling edge
1
1
↑
Both edges
×
•
Event counter mode (CSL0,CSL1 = 11B)
•
Bits marked as × in the table can be set to any value.
[bit6] OUTE
Output enable bit. The TOT pin functions as a general-purpose port when this bit is "0" and as
the timer output pin when this bit is "1". In reload mode, the output waveform toggles. In oneshot mode, TOT outputs a rectangular waveform that indicates that counting is in progress.
202
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
[bit5] OUTL
This bit sets the output level for the TOT pin.
Table 13.2-4 OUTE, RELD, and OUTL Settings
OUTE
RELD
OUTL
Output Waveform
0
×
×
General-purpose port
1
0
0
Output an "H" level rectangular waveform during counting.
1
0
1
Output an "L" level rectangular waveform during counting.
1
1
0
Toggle output with "L" at count start.
1
1
1
Toggle output with "H" at count start.
[bit4] RELD (Reload)
This bit enables reload operations. When RELD is "1", the timer operates in reload mode. In
this mode, the timer loads the reload register contents into the counter and continues counting
whenever an underflow occurs (when the counter value changes from 0000H to FFFFH).
When RELD is "0", the timer operates in one-shot mode. In this mode, the count operation
stops when an underflow occurs due to the counter value changing from 0000H to FFFFH.
[bit3] INTE (Interrupt enable)
Timer interrupt request enable bit. When INTE is "1", an interrupt request is generated when
the UF bit changes to "1". When INTE is "0", no interrupt request is generated, even when the
UF bit changes to "1".
[bit2] UF (Underflow)
Timer interrupt request flag. UF is set to "1" when an underflow occurs (when the counter
value changes from 0000H to FFFFH). Cleared by writing "0" or by the intelligent I/O service.
Writing "1" to this bit has no meaning. Read as "1" by read-modify-write instructions.
[bit1] CNTE (Count enable)
Timer count enable bit. Writing "1" to CNTE sets the timer to wait for a trigger. Writing "0"
stops count operation.
[bit0] TRG (Trigger)
Software trigger bit. Writing "1" to TRG applies a software trigger, causing the timer to load the
reload register contents to the counter and start counting. Writing "0" has no meaning.
Reading always returns "0". Applying a trigger using this register is only valid when CNTE = 1.
Writing "1" has no effect if CNTE = 0.
203
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.2.2 Register Layout of 16-bit Timer Register (TMR)/16-bit
Reload Register (TMRLR)
TMR contents (for reading):
Reading this register reads the count value of the 16-bit timer. The initial value is
undefined. Always read this register using the word access instructions.
TMRLR contents (for writing):
The 16-bit reload register holds the initial count value. The initial value is undefined.
Always write to this register using the word access instructions.
■ 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR)
Figure 13.2-3 shows the bit configuration of the 16-bit timer register (TMR) and the 16-bit reload
register (TMRLR).
Figure 13.2-3 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR)
16-bit timer register (upper)/
16-bit reload register (upper)
15
14
13
12
11
10
9
Bit No.
8
TMR0/TMRLR0
TMR1/TMRLR1
Address: ch0 000053H
ch1 000057
00003FHH
ch1
Read/write
Initial value
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
6
5
4
3
2
1
16-bit timer register (lower)/
16-bit reload register (lower)
Address: ch0 000052H
ch1 000056
00003EHH
ch1
Read/write
Initial value
204
0
Bit No.
TMR0/TMRLR0
TMR1/TMRLR1
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.3 Internal Clock and External Clock Operations of 16-bit
Reload Timer
The machine clock divided by 21, 23, or 25 can be selected as the clock sources for
operating the timer from an internal divide clock. The external input pin can be selected
as either a trigger input or gate input by a register setting.
If an external clock is selected, the TIN pin functions as an external event input pin to
count valid edges set in the register.
■ Internal Clock Operation of 16-bit Reload Timer
Writing "1" to both the CNTE and TRG bits in the control register enables and starts counting at
one time. Using the TRG bit as a trigger input is always available when the timer is enabled
(CNTE = 1), regardless of the operation mode.
Figure 13.3-1 shows counter activation and counter operation. A time period T (T: machine cycle)
is required from the counter start trigger being input until the reload register data is loaded into
counter.
Figure 13.3-1 Activation and Operation of 16-bit Reload Timer Counter
Count clock
Counter
Reload data
-1
-1
-1
Data load
CNTE (bit)
TRG (bit)
T
205
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
■ Input Pin Functions of 16-bit Reload Timer (in Internal Clock Mode)
The TIN pin can be used as either a trigger input or a gate input when an internal clock is
selected as the clock source. When used as a trigger input, input of an active edge causes the
timer to load the reload register contents to the counter and then start count operation after
clearing the internal prescaler. Input a pulse width of at least 2T (T is the machine cycle) to TIN.
Figure 13.3-2 shows the operation of trigger input.
Figure 13.3-2 Trigger Input Operation of 16-bit Reload Timer
Count clock
Rising edge detected
TIN pin
Prescaler clear
Counter
-1
Reload data
-1
-1
-1
Load
2T to
2.5T
When used as a gate input, the counter only counts while the active level specified by the MOD0
bit of the control register is input from the TIN pin. In this case, the count clock continues to
operate unless stopped. The software trigger can be used in gate mode, regardless of the gate
level. Input a pulse width of at least 2T (T is the machine cycle) to the TIN pin. Figure 13.3-3
shows the operation of gate input.
Figure 13.3-3 Gate Input Operation of 16-bit Reload Timer
Count clock
TIN pin
Counter
When MOD0 = 1 (Count when "H" is input)
-1
-1
-1
■ External Event Counter
The TIN pin functions as an external event input pin when an external clock is selected. The
counter counts on the active edge specified in the register. Input a pulse width of at least 4T (T is
the machine cycle) to the TIN pin.
206
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.4 Underflow Operation of 16-bit Reload Timer
An underflow is defined by 16-bit reload timer when the counter value changes from
0000H to FFFFH. Therefore, an underflow occurs after (reload register setting + 1)
counts.
■ Underflow Operation of 16-bit Reload Timer
If the RELD bit in the control register is "1" when the underflow occurs, the contents of the reload
register is loaded into the counter and counting continues. When RELD is "0", counting stops with
the counter at FFFFH.
The UF bit in the control register is set when the underflow occurs. If the INTE bit is "1" at this
time, an interrupt request is generated.
Figure 13.4-1 and Figure 13.4-2 show the operation when an underflow occurs.
Figure 13.4-1 Underflow Operation of 16-bit Reload Timer [RELD=1]
Count clock
Counter
0000H
Reload data
-1
-1
-1
Data load
Underflow set
Figure 13.4-2 Underflow Operation of 16-bit Reload Timer [RELD=0]
Count clock
Counter
0000H
FFFFH
Underflow set
207
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.5 Output Pin Functions of 16-bit Reload Timer
In reload mode, the TOT pin performs toggle output (inverts at each underflow). In oneshot mode, the TOT pin functions as a pulse output that outputs a particular level while
the count is in progress.
■ Output Pin Functions of 16-bit Reload Timer
The OUTL bit of the register sets the output polarity 16-bit reload timer. When OUTL = 0, the
initial value for toggle output is "0" and the one-shot pulse output is "1" while the count is in
progress. The output waveforms are inverted when OUTL = 1.
Figure 13.5-1 and Figure 13.5-2 show the output pin functions.
Figure 13.5-1 Output Pin Function of 16-bit Reload Timer (RELD=1, OUTL=0)
Count start
Underflow
TOT
General-purpose port
Level is inverted
when OUTL = 1.
CNTE
Activating trigger
Figure 13.5-2 Output Pin Function of 16-bit Reload Timer (RELD=0, OUTL=0)
Underflow
Level is inverted
when OUTL = 1.
TOT
General-purpose port
CNTE
Activating trigger
Waiting for
an activating trigger
208
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.6 Counter Operation State
The counter state is determined by the CNTE bit in the control register and the internal
WAIT signal. Available states are: CNTE = 0 and WAIT = 1 (STOP state), CNTE = 1 and
WAIT = 1 (WAIT state for trigger), and CNTE = 1 and WAIT = 0 (RUN state).
■ Counter Operation State
Figure 13.6-1 shows the transitions between each state.
Figure 13.6-1 Counter State Transitions
Reset
State transitions by hardware
STOP
CNTE=0, WAIT=1
State transitions by register access
TIN pin: Input disabled
TOT pin: General-purpose port
Counter: Retains the value while
counting stopped.
Value undefined after reset.
CNTE= 0
CNTE= 0
CNTE= 1
TRG= 1
CNTE= 1
TRG= 0
WAIT
RUN
CNTE=1, WAIT=1
CNTE=1, WAIT=0
TIN pin: Only trigger input enabled
TIN pin: Functions as TIN pin
TOT pin: Initial value output
TOT pin: Functions as TOT pin
Counter: Retains the value while
counting stopped.
Value undefined after reset until
load.
TRG= 1
Activated
from TIN
Counter: Running
RELD·UF
TRG= 1
RELD·UF
LOAD
CNTE=1, WAIT= 0
Load complete
Load contents of the reload
register to the counter.
209
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
210
CHAPTER 14
8/16-BIT PPG
This chapter explains the functions and operation of the 8/16-bit PPG.
14.1 Outline of 8/16-bit PPG
14.2 Block Diagram of 8/16-bit PPG
14.3 8/16-bit PPG Registers
14.4 Operations of 8/16-bit PPG
14.5 Selecting a Count Clock for 8/16-bit PPG
14.6 Controlling Pin Output of 8/16-bit PPG Pulses
14.7 8/16-bit PPG Interrupts
14.8 Initial Values of 8/16-bit PPG Hardware
211
CHAPTER 14 8/16-BIT PPG
14.1 Outline of 8/16-bit PPG
The 8/16-bit Programable Pulse Generator (PPG) consists of two 8-bit down counters,
four 8-bit reload registers, one 16-bit control register, two external pulse output pins,
and two interrupt outputs. The following functions are implemented:
■ Function of 8/16-bit PPG
❍ 8-bit PPG output, 2-channel independent operation mode
Two independent channels of PPG output operation are implemented.
❍ 16-bit PPG output operation mode
One channel of 16-bit PPG output operation is implemented.
❍ 8-bit prescaler + 8-bit PPG output operation mode
8-bit PPG output operation is implemented at specifies intervals, using channel 0 output as
channel 1 clock input.
❍ PPG output operation
Pulse waves are output at specified intervals and duty ratio. With an external circuit, this module
can be used as a D/A converter.
The pair of ch0 and ch1 of PPG is called 1 unit.
The MB90540/545 Series contains four units of PPG’s. The following sections only describe the
functions of the ch0 and ch1 of PPG. The remaining PPG’s have the identical function and the
register address should be found in the I/O map.
Ch0 of PPG is shown PPG (ch0) and ch1 of PPG is shown PPG (ch1).
212
CHAPTER 14 8/16-BIT PPG
14.2 Block Diagram of 8/16-bit PPG
Figure 14.2-1 shows a block diagram of the 8/16-bit PPG (ch0). Figure 14.2-2 shows a
block diagram of the 8/16-bit PPG (ch1).
■ Block Diagram of 8/16-bit PPG
Figure 14.2-1 8-bit PPG ch0 Block Diagram
Peripheral clock 16-division
Peripheral clock 8-division
Peripheral clock 4-division
Peripheral clock 2-division
Peripheral clock
PPG0
Output latch
Invertsion
Clear
PEN0
Count clock
selection
Timebase timer output
512-division of main clock
L/H selection
S
RQ
PCNT
(down counter)
In MB90540/545 Series, this IRQ signal is
merged with the PPG (ch1) IRQ signal
by OR logic.
IRQ
Reload
ch1-borrow
L/H selector
P RLL0
PRLBH0
PIE0
PRLH0
PUF0
"L" data bus
"H" data bus
PPGC0
(Operation mode control)
The PPG output signal of ch0 is not connected with an external terminal.
213
CHAPTER 14 8/16-BIT PPG
Figure 14.2-2 8-bit PPG ch1 Block Diagram
PPG0 pin output enable
PPG0 pin
Peripheral clock 16-division
Peripheral clock 8-division
Peripheral clock 4-division
Peripheral clock 2-division
Peripheral clock
In MB90540/545 Series this pin is connected to
the "PPG0" external pin.
PPG1
Output latch
Invertsion
Count clock
selection
Clear
PEN1
In MB90540/545 Series, this IRQ signal is
merged with the PPG (ch0) IRQ signal
by OR logic.
ch0 borrow
Timebase timer output
512-division of main clock
L/H selection
S
RQ
PCNT
(down counter)
IRQ
Reload
L/H selector
P RLL1
PRLBH1
PIE1
PRLH1
PUF1
"L" data bus
"H" data bus
PPGC1
(Operation mode control)
Figure 14.2-3 Relationship between PPG Modules, Unit Number and External Pins
PPG unit 0
PPG (ch0), PPG (ch1)
PPG0
PPG unit 1
PPG (ch2), PPG (ch3)
PPG1
PPG unit 2
PPG (ch4), PPG (ch5)
PPG2
PPG unit 3
PPG (ch6), PPG (ch7)
PPG3
External pins
214
CHAPTER 14 8/16-BIT PPG
14.3 8/16-bit PPG Registers
The 8/16-bit PPG has the following five types of registers:
• PPG0 operation mode control register
• PPG1 operation mode control register
• PPG unit 0 clock selection register
• Reload register H
• Reload register L
■ 8/16-bit PPG Registers
Figure 14.3-1 shows the bit configuration of the 8/16 bit PPG registers.
Figure 14.3-1 8/16 Bit PPG Registers
PPG0 operation mode control register
7
Address: ch0 000038H
6
5
PEN0
PE00
4
3
2
PIE0
PUF0
1
0
Bit No.
Reserved
PPGC0
Read/write
Initial value
(R/W)
(0)
PPG1 operation mode control register
15
Address: ch0 000039H
PEN1
Read/write
Initial value
PPG unit 0 clock selection register
(-)
(-)
(R/W) (R/W) (R/W)
(0)
(0)
(0)
14
(-)
(-)
(-)
(-)
(W)
(1)
Bit No.
13
12
11
10
9
8
PE10
PIE1
PUF1
MD1
MD0
Reserved
PPGC1
(R/W)
(0)
(-)
(-)
7
6
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
5
4
3
2
1
(W)
(1)
0
Bit No.
Address: ch0, ch1 00003AH
PCS1 PCS0 PCM2 PCM1 PCM0
PCS2
Read/write
Initial value
PPG0/PPG1
(R/W) (R/W)
(0)
(0)
15
Reload register H
Address: ch0 003901H
ch1 003903H
Read/write
Initial value
(R/W) (R/W)
(0)
(0)
14
13
12
11
(-)
(-)
(-)
(-)
(R/W) (R/W)
(0)
(0)
10
9
8
PRLH0/
PRLH1
(R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
7
6
5
4
(R/W) (R/W)
(X)
(X)
3
2
1
(R/W)
(X)
0
Reload register L
Address: ch0 003900H
ch1 003902H
Read/write
Initial value
Bit No.
Bit No.
PRLL0/
PRLL1
(R/W)
(X)
(R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(R/W) (R/W)
(X)
(X)
(R/W)
(X)
215
CHAPTER 14 8/16-BIT PPG
14.3.1 PPG0 Operation Mode Control Register (PPGC0)
The operation mode control register (PPGC0) is a 5-bit control register that selects the
operation mode of the block, controls pin outputs, selects a count clock, and controls
triggers. This register controls PPG (ch0).
■ PPG0 Operation Mode Control Register (PPGC0)
Figure 14.3-2 shows the bit configuration of the PPG0 operation mode control register (PPGC0).
Figure 14.3-2 PPG0 Operation Mode Control Register (PPGC0)
Address: ch0,000038H
Read/write→
Initial value→
7
PEN0
(R/W)
(0)
6
⎯
(-)
(-)
5
PE00
(R/W)
(0)
4
PIE0
(R/W)
(0)
3
PUF0
(R/W)
(0)
2
⎯
(-)
(-)
1
⎯
(-)
(-)
0
Reserved
(W)
(1)
[bit7] PEN0 (PPG enable): Operation enable bit
This bit enables PPG (ch0) count operation.
PEN0
Operation
0
Stop ("L" level output maintained)
1
PPG (ch0) operation enabled
Setting this bit to "1" enables the counter operation.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit5] PE00 (PPG output enable 00): PPG0 pin output enable bit
This bit controls the PPG0 pulse output external pin as described below.
PE00
Operation
0
General-purpose port pin (pulse output disabled)
1
PPG0 = pulse output pin (pulse output enabled)
This bit is initialized to "0" upon a reset. This bit is readable and writable.
In MB90540/545 series, this bit should always be set to "0".
216
←Bit No.
PPGC0
CHAPTER 14 8/16-BIT PPG
[bit4] PIE0 (PPG interrupt enable): PPG interrupt enable bit
This bit controls PPG (ch0) interrupt as described below.
PIE0
Operation
0
Interrupt disabled
1
Interrupt enabled
While this bit is "1", an interrupt request is issued as soon as PUF0 is set to "1". No interrupt
request is issued while this bit is set to "0".
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit3] PUF0 (PPG underflow flag): PPG counter underflow bit
This bit indicates the PPG (ch0) counter underflow bit as described below.
PUF0
Operation
0
PPG (ch0) counter underflow is not detected.
1
PPG (ch0) counter underflow is detected.
In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" when an
underflow occurs as a result of the ch0 counter value becoming from 00H to FFH. In 16-bit
PPG mode, this bit is set to "1" when an underflow occurs as a result of the Channel 0 and 1
counter value becoming from 0000H to FFFFH. To set this bit to "0", write "0". Writing "1" to
this bit has not effect. Upon a read operation during a read-modify-write instruction, "1" is read.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit0]
This is a reserved bit. Always set this bit to "1".
The value read from this bit is always "1".
217
CHAPTER 14 8/16-BIT PPG
14.3.2 PPG1 Operation Mode Control Register (PPGC1)
The PPG1 operation mode control register (PPGC1) is a 7-bit control register that
selects the operation mode of the block, controls pin outputs, selects a count clock,
and controls triggers.
The control of PPG (ch1) and the operation mode of PPG unit 0 are selected.
■ PPG1 Operation Mode Control Register (PPGC1)
Figure 14.3-3 shows the bit configuration of the PPG1 operation mode control register (PPGC1).
Figure 14.3-3 PPG1 Operation Mode Control Register (PPGC1)
Address: ch1 000039H
Read/write→
Initial value→
15
14
13
12
11
10
9
8
PEN1
(R/W)
(0)
⎯
(-)
(-)
PE10
(R/W)
(0)
PIE1
(R/W)
(0)
PUF1
(R/W)
(0)
MD1
(R/W)
(0)
⎯
(R/W)
(0)
Reserved
(W)
(1)
[bit15] PEN1 (PPG enable): Operation enable bit
This bit enables the counter operation of the PPG (ch1).
PEN1
Operation
0
Stop ("L" level output maintained)
1
PPG (ch1) operation enabled
Setting this bit to "1" enables the counter operation.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit13] PE10 (PPG output enable 10): PPG0 pin output enable bit
This bit controls the PPG0 pulse output external pin as described below.
PE10
Operation
0
General-purpose port pin (pulse output disabled)
1
PPG0 = pulse output pin (pulse output enabled)
This bit is initialized to "0" upon a reset. This bit is readable and writable.
218
←Bit No.
PPGC1
CHAPTER 14 8/16-BIT PPG
[bit12] PIE1 (PPG interrupt enable): PPG interrupt enable bit
This bit controls PPG (ch1) interrupt as described below.
PIE1
Operation
0
Interrupt disabled
1
Interrupt enabled
While this bit is "1", an interrupt request is issued as soon as PUF1 is set to "1". No interrupt
request is issued while this bit is set to "0".
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit11] PUF1 (PPG underflow flag): PPG counter underflow bit
This bit indicates the PPG (ch1) counter underflow as described below.
PUF1
Operation
0
PPG (ch1) counter underflow has not been detected.
1
PPG (ch1) counter underflow has been detected.
In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" when an
underflow occurs as a result of the Channel 1 counter value becoming from 00H to FFH. In 16bit PPG mode, this bit is set to "1" when an underflow occurs as a result of the Channel 0 and
1 counter value becoming from 0000H to FFFFH. To set this bit to "0", write "0". Writing "1" to
this bit has not effect. Upon a read operation during a read-modify-write instruction, "1" is read.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit10, bit9] MD1, MD0 (PPG count mode): Operation mode selection bit
These bits selects the PPG unit operation mode as described below.
MD1
MD0
Operation mode
0
0
8-bit PPG 2-channel independent mode
0
1
8-bit prescaler + 8-bit PPG 1-channel mode
1
0
Reserved (setting prohibited)
1
1
16-bit PPG 1-channel mode
These bits are initialized to "00B" upon a reset. These bits are readable and writable.
Note:
Do not set "10B" in these bits.
To write "01B" to these bits, ensure that "01B" is not written to the PEN0 bit of PPGC0 or PEN1 bit of
PPGC1. Write "11B" or "00B" in both the PEN0 and PEN1 bits simultaneously.
To write "11B" to these bits, update PPGC0 and PPGC1 by word transfer and write "11B" or "00B" to
both the PEN0 and PEN1 bits simultaneously.
219
CHAPTER 14 8/16-BIT PPG
[bit8] Reserved bit
This is a reserved bit.
When setting PPGC1, always write "1" to this bit.
The value read from this bit is always "1".
220
CHAPTER 14 8/16-BIT PPG
14.3.3 PPG unit 0 Clock Selection Register (PPG01)
The PPG unit 0 clock selection register (PPG01) is an 8-bit control register that controls
the PPG operation clock.
■ PPG Unit 0 Clock Selection Register (PPG01)
Figure 14.3-4 shows the bit configuration of the PPG unit 0 clock selection register (PPG01).
Figure 14.3-4 PPG Unit 0, 1 Clock Selection Register (PPG01)
Address: ch0,ch1 00003AH
Read/write→
Initial value→
7
6
5
4
3
2
1
0
PCS2
(R/W)
(0)
PCS1
(R/W)
(0)
PCS0
(R/W)
(0)
PCM2
(R/W)
(0)
PCM1
(R/W)
(0)
PCM0
(R/W)
(0)
⎯
(-)
(-)
⎯
(-)
(-)
←Bit No.
PPG01
[bit7 to bit5] PCS2 to PCS0 (PPG count select): Count clock selection bit
These bits select the operation clock for the down counter of Channel 1 as described below.
PCS2
PCS1
PCS0
Operation mode
0
0
0
Peripheral clock (62.5 ns machine clock, 16 MHz)
0
0
1
Peripheral clock/2 (125 ns machine clock, 16 MHz)
0
1
0
Peripheral clock/4 (250 ns machine clock, 16 MHz)
0
1
1
Peripheral clock/8 (500 ns machine clock, 16 MHz)
1
0
0
Peripheral clock/16 (1 µs machine clock, 16 MHz)
1
1
1
Clock input from the timebase timer (128 µs, 4 MHz source
oscillation)
These bits are initialized to "000B" upon a reset. These bits are readable and writable.
Note:
In 8-bit prescaler + 8-bit PPG mode or in 16-bit PPG mode, ch1 PPG operates in response to a
counter clock from ch0. Therefore, the setting in these bits has no effect.
221
CHAPTER 14 8/16-BIT PPG
[bit4 to bit2] PCM2 to PCM0 (PPG count mode): Count clock selection bit
These bits select the operation clock for the down counter of Channel 0 as described below.
PCM2
PCM1
PCM0
Operation mode
0
0
0
Peripheral clock (62.5 ns machine clock, 16 MHz)
0
0
1
Peripheral clock/2 (125 ns machine clock, 16 MHz)
0
1
0
Peripheral clock/4 (250 ns machine clock, 16 MHz)
0
1
1
Peripheral clock/8 (500 ns machine clock, 16 MHz)
1
0
0
Peripheral clock/16 (1 µs machine clock, 16 MHz)
1
0
1
Clock input from the timebase timer
(128 µs, 4 MHz source oscillation)
These bits are initialized to "000B" upon a reset. These bits are readable and writable.
222
CHAPTER 14 8/16-BIT PPG
14.3.4 Reload Register (PRLL/PRLH)
The reload registers (PRLL and PRLH) are 8-bit registers that store reload values for the
PCNT down counters. The PRLL and PRLH registers are readable and writable.
■ Reload Register (PRLL/PRLH)
Figure 14.3-5 shows the bit configuration of the reload register (PRLL/PRLH).
Figure 14.3-5 Reload Register (PRLL/PRLH)
15141312111098
Bit No.
Reload register H
Address: ch0 003901H
ch1 003903H
Read/write
Initial value
PRLH0/1
(R/W) (R/W) (R/W) (R/W) (R/W)
(X)(X)
(X)
(X)
(X)
7
6
5
4
(R/W) (R/W)
(X)
(X)
3
2
1
(R/W)
(X)
0
Reload register L
Address: ch0 003900H
ch1 003902H
Read/write
Initial value
Register name
Bit No.
PRLL0/1
(R/W)(R/W)
(X)(X)
(R/W) (R/W) (R/W)
(X)
(X)
(X)
(R/W) (R/W)
(X)
(X)
(R/W)
(X)
Function
PRLL
Holds the "L" side reload value. Sets "L" pulse width.
PRLH
Holds the "H" side reload value. Sets "H" pulse width.
Note:
In 8-bit prescaler + 8-bit PPG mode, different values in PRLL and PRLH of Channel 0 may cause the
PPG waveform of ch1 to vary in each cycle. Write the same value to PRLL and PRLH of ch0.
223
CHAPTER 14 8/16-BIT PPG
14.4 Operations of 8/16-bit PPG
One 8/16-bit PPG consists of two channels of 8-bit PPG units. These two channels can
be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG
mode, and single-channel 16-bit PPG mode.
■ Operations of 8/16-bit PPG
Each of the 8-bit PPG units has two 8-bit reload registers. One reload register is for the "L" pulse
width (PRLL) and the other is for the "H" pulse width (PRLH). The values stored in these registers
are reloaded into the 8-bit down counter (PCNT), from the PRLL and PRLH in turn. PPG0 output
pin is inverted upon a reload caused by counter borrow. This operation results in the pulses of the
specified "L" pulse width and "H" pulse width.
Table 14.4-1 lists the relationship between the reload operation and pulse outputs.
Table 14.4-1 Reload Operation and Pulse Output
Reload operation
Pin output change
PRLH --> PCNT
PPG0 output pin
[0 --> 1]
↑
Rise
PRLL --> PCNT
PPG0 output pin
[1 --> 0]
↓
Fall
When "1" is set in bit4 (PIE0) of PPGC0 or in bit12 (PIE1) of PPGC1, an interrupt request is
output upon a borrow from 00H to FFH (from 0000H to FFFFH in 16-bit PPG mode) of each
counter.
■ Operation Modes of 8/16-bit PPG
This block can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit
PPG mode, and single-channel 16-bit PPG mode.
❍ Independent two-channel mode
The two channels of 8-bit PPG units operate independently.
❍ 8-bit prescaler + 8-bit PPG mode
ch0 is used as an 8-bit prescaler while the count in ch1 is based on borrow outputs from ch0.
Thus, 8-bit PPG waveforms can be output with arbitrary length of cycle time.
❍ 16-bit PPG 1ch mode
ch0 and ch1 are connected and used as a single 16-bit PPG.
224
CHAPTER 14 8/16-BIT PPG
■ 8/16-bit PPG Output Operation
The 8/16-bit channel 0 PPG is activated by setting bit7 (PEN0) of the PPGC0 register to "1". The
8/16-bit channel 1 PPG is activated by setting bit15 (PEN1) of the PPGC1 register to "1". After
operation is started, counting is stopped by writing "0" to bit7 (PEN0) of PPGC0 or bit15 (PEN1)
of PPGC1. After counting is stopped, the pulse output is maintained at the L level. In the
MB90540/545 series, the output signal from the channel 0 PPG is not connected to any external
pin.
In 8-bit prescaler + 8-bit PPG mode, do not set ch1 to be in operation while ch0 operation is
stopped.
In 16-bit PPG mode, ensure that bit7 (PEN0) of PPGC0 register and bit15 (PEN1) of PPGC1
register are started or stopped simultaneously. The figure below is a diagram of PPG output
operation. During PPG operation, a pulse wave is continuously output at a frequency and duty
ratio (the ratio of the "H" level period of the pulse wave to the "L" level period). PPG continues
operation until stop is specified explicitly.
Figure 14.4-1 PPG Output Operation, Output Waveform
PEN
Starts operation based on PEN (from "L" side).
PPG0
Output pin
T
(L+1)T
(Start)
(H+1)
L :PRLL value
H :PRLH value
T :Input from peripheral clock (φ, φ/4, φ/16)
or timer base counter (depending on the
clock selection by PPGCc
■ Relationship Between 8/16-bit PPG Reload Value and Pulse Width
The width of the output pulse is determined by adding 1 to the reload register value and
multiplying it by the count clock cycle. Note that when the reload register value is 00H during 8-bit
PPG operation or 0000H during 16-bit PPG operation, the pulse width is equivalent to one count
clock cycle. In addition, note that when the reload register value is FFH during 8-PPG operation,
the pulse width is equivalent to 256 count clock cycles. When the reload register value is FFFFH
during 16-bit PPG operation, the pulse width is equivalent to 65536 count clock cycles. The
following is an example of calculating the pulse width:
Pl =T
Ph=T
(L+1)
(H+1)
L : PRLL value
H : PRLH value
T : Input clock cycle
Ph: "H" pulse width
Pl : "L" pulse width
225
CHAPTER 14 8/16-BIT PPG
14.5 Selecting a Count Clock for 8/16-bit PPG
The count clock used for the 8/16-bit PPG operation is supplied from the peripheral
clock or the timebase timer. The count Input clock can be selected from six choices.
■ Selecting a Count Clock for 8/16-bit PPG
Select ch0 clock at bit4 to bit2 (PCM2 to PCM0) of the PPG unit 0 clock selection register, and
ch1 clock at bit7 to bit5 (PCS2 to PCS0) of the PPG unit 0 clock selection register.
The clock is selected from a peripheral clock 1/16 to 1 times higher than a machine clock or an
input clock from the timebase counter.
In 8-bit prescaler + 8-bit PPG mode or 16-bit PPG mode, however, the setting in the PCS2 to 0
has no effect.
When the timebase timer input is used, the first count cycle after a trigger or a stop may be
shifted. The cycle may also be shifted if the timebase counter is cleared during operation of this
module.
In 8-bit prescaler + 8-bit PPG mode, if ch1 is activated while ch0 is in operation and ch1 is
stopped, the first count cycle may be shifted.
226
CHAPTER 14 8/16-BIT PPG
14.6 Controlling Pin Output of 8/16-bit PPG Pulses
The pulses generated by this module can be output from external pins PPG0.
■ Controlling Pin Output of 8/16-bit PPG Pulses
When "0" is written to bit13 (PE10) of PPG1 operation mode control register (PPGC1) bits
(default), the pulses are not output from the corresponding external pins; the pins work as
general-purpose ports. When "1" is written to these bits, the pulses are output from external pins.
In 8-bit prescaler + 8-bit PPG mode, the 8-bit prescaler toggle waveform is output from PPG
(ch0), while the 8-bit PPG waveform is output from PPG (ch01). Figure 14.6-1 is a example of
output waveforms in this mode.
For the MB90540/545 Series, the output signal from the Channel 0 PPG is not connected to any
external pin.
Figure 14.6-1 8-bit Prescaler + 8-bit PPG Output Operation Waveform
Ph0
Pl0
PPG (ch0)
output
(internal signal)
PPG (ch1)
output
(PPG0 pin
waveform)
Ph1
Pl0 = T
Pl1
(L0+1)
Ph0 = T
(L0+1)
Pl1 = T
(L0+1)
(L1+1)
Ph1 = T
(L0+1)
(H1+1)
L0 :ch0 PRLL value and ch0 PRLH value
L1 :ch1 PRLL value
H1 :ch1 PRLH value
T : Input clock cycle
Ph0 :PPG (ch0) "H" pulse width
Pl0 :PPG (ch0) "L" pulse width
Ph1 :PPG (ch1) "H" pulse width
Pl1 :PPG (ch1) "L" pulse width
Note:
Set the same value in ch0 PRLL and ch0 PRLH.
227
CHAPTER 14 8/16-BIT PPG
14.7 8/16-bit PPG Interrupts
The 8/16-bit PPG outputs interrupt request when the reload value counts out and a
borrow occurs.
■ 8/16-bit PPG Interrupts
In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, an interrupt is requested by a
borrow in each counter. In 16-bit PPG mode, PUF0 and PUF1 are simultaneously set by a borrow
in the 16-bit counter. Therefore, enable only PIE0 or PIE1 to unify the interrupt causes. In
addition, simultaneously clear the interrupt flags for PUF0 and PUF1.
228
CHAPTER 14 8/16-BIT PPG
14.8 Initial Values of 8/16-bit PPG Hardware
The hardware components of this block are initialized to the following values when
reset:
■ Initial Values of 8/16-bit PPG Hardware
❍ <Registers>
•
PPGC0 --> 0-000--1B
•
PPGC1 --> 0-000001B
•
PPG01
--> 000000--B
❍ <Pulse outputs>
The PPG0 pin is set to be output prohibited.
When the output is permitted, it becomes "L" output.
❍ <Interrupt requests>
It becomes an interrupt prohibition. The reload value is maintained.
Note:
Write timing for 8/16-bit PPG reload registers (PRLL and PRLH)
In a mode other than 16-bit PPG mode, it is recommended to use a word transfer instruction to write
data in reload registers PRLL and PRLH. If two byte transfer instructions are used to write a data
item to these registers, a pulse of unexpected cycle time may be output depending on the timing.
Figure 14.8-1 Write Timing for 8/16-bit PPG Reload Registers (PRLL and PRLH)
PPG0
B
A
B
C
A
B
C
C
D
D
➀
Assume that PRLL is updated from A to C before point 1 in the time chart above, and PRLH is
updated from B to D after point 1. Since the PRL values at point 1 are PRLL=C and PRLH=B, a
pulse of "L" side count value C and "H" side count value B is output only once.
Similarly, to write data in PRL of ch0 and ch1 in 16-bit PPG mode, use a long word transfer
instruction, or use word transfer instructions in the order of ch0 and then ch1. In this mode, the
data is only temporarily written to ch0 PRL. Then, the data is actually written into ch0 PRL when
the ch1 PRL is written to.
As shown in Figure 14.8-2 in a mode other than 16-bit PPG mode, ch0 PRL and ch1 PRL can be
written independently.
229
CHAPTER 14 8/16-BIT PPG
Figure 14.8-2 PRL Write Operation Block Diagram
ch0 PRL write data
ch1 PRL write data
Transferred in synchronization
with ch1 write in 16-bit
Temporary latch
PPG mode
ch0 write in a mode other
than 16-bit PPG mode
ch1 write
ch0 PRL
230
ch1 PRL
CHAPTER 15
DELAYD INTERRUPT
This chapter explains the functions and operations of the delayed interrupt.
15.1 Outline of Delayed Interrupt Module
15.2 Delayed Interrupt Register
15.3 Delayed Interrupt Operation
231
CHAPTER 15 DELAYD INTERRUPT
15.1 Outline of Delayed Interrupt Module
The delayed interrupt generating module is used to generate interrupts for switching
tasks. Using this module, interrupt requests to the F2MC-16LX CPU can be issued and
canceled by software.
■ Block Diagram of Delayed Interrupt
Figure 15.1-1 is a block diagram of the delayed interrupt source module.
Internal data bus
Figure 15.1-1 Block Diagram of Delayed Interrupt
Delayed interrupt cause issuance/cancellation decoder
Cause latch
■ Notes on Operation
This lock is set by writing "1" to the corresponding bit of DIRR, and is cleared by writing "0" to the
same bit. Therefore, interrupt processing is reactivated immediately after control returns from
interrupt processing, unless the software is designed so that the cause of the interrupt is cleared
within the interrupt processing routine.
232
CHAPTER 15 DELAYD INTERRUPT
15.2 Delayed Interrupt Register
DIRR controls issuance and cancellation of delayed interrupt requests. Writing "1" to
this register issues a delayed interrupt request, and writing "0" cancels the delayed
interrupt request. Upon a reset, the request is canceled.
■ Delayed Interrupt Cause Issuance/Cancellation Register (DIRR)
In DIRR, either "0" or "1" can be written to the reserved bit area. However, it is recommended that
a set bit or clear bit instruction is used to access this register for future expansions.
Figure 15.2-1 shows the bit configuration of the delayed interrupt cause issuance/cancellation
register (DIRR).
Figure 15.2-1 Delayed Interrupt Cause Issuance/Cancellation Register (DIRR)
Address: 00009FH
Read/write→
Initial value→
15
⎯
(-)
(-)
14
⎯
(-)
(-)
13
⎯
(-)
(-)
12
⎯
(-)
(-)
11
⎯
(-)
(-)
10
⎯
(-)
(-)
9
⎯
(-)
(-)
8
R0
(R/W)
(0)
←Bit No.
DIRR
233
CHAPTER 15 DELAYD INTERRUPT
15.3 Delayed Interrupt Operation
When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the
delayed interrupt source module is set and an interrupt request is issued to the
interrupt controller.
■ Delayed Interrupt Occurrence
If this interrupt has the highest priority or if there is no other interrupt request, the interrupt
controller issues an interrupt request to the F2MC-16LX CPU. The F2MC-16LX CPU compares
the ILM bit of its internal CCR register and the interrupt request, and starts the hardware interrupt
processing microprogram as soon as the current instruction is completed if the interrupt level of
the request is higher than that of the ILM bit. The interrupt processing routine for this interrupt is
thus executed.
Figure 15.3-1 Delayed Interrupt Issuance
F 2 MC-16LX CPU
Delayed interrupt source moduleInterrupt controller
WRITE
Other requests
ICR yy
IL
CMP
CMP
DIRR
ICR xx
ILM
NTA
Writing "0" to the relevant DIRR bit in the interrupt processing routine clears the cause of this
interrupt and switches between tasks.
234
CHAPTER 16
DTP/EXTERNAL INTERRUPTS
This chapter explains the functions and operations of the DTP/external interrupts.
16.1 Outline of DTP/External Interrupts
16.2 DTP/External Interrupt Registers
16.3 Operations of DTP/External Interrupts
16.4 Switching between External Interrupt and DTP Requests
16.5 Notes on Using DTP/External Interrupts
235
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.1 Outline of DTP/External Interrupts
The data transfer peripheral (DTP) is located between an external peripheral and the
F2MC-16LX CPU. The DTP receives a DMA request or interrupt request from the external
peripheral, transfers the request to the F2MC-16LX CPU to activate the intelligent I/O
service or interrupt processing.
■ Outline of DTP/External Interrupts
For the intelligent I/O service, "H" and "L" request levels are available. For an external interrupt
request, four request levels are available: "H", "L", rising edge, and falling edge.
■ Block Diagram of DTP/External Interrupts
Figure 16.1-1 Block Diagram of DTP/External Interrupts
Internal data bus
8
8
8
16
236
DTP/external interrupt enable register
Gate
Cause F/F
Edge detection circuit
DTP/external interrupt cause register
Request level setting register
8
Request input
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
■ DTP/External Interrupts Registers
Figure 16.1-2 shows the bit configuration of the DTP/external interrupts registers.
Figure 16.1-2 DTP/External Interrupts Registers
DTP/external interrupt enable register
7
6
EN7
EN6
Address: 000030H
(R/W) (R/W)
Read/write→
Initial value→
(0)
(0)
5
EN5
(R/W)
(0)
4
EN4
(R/W)
(0)
3
EN3
(R/W)
(0)
2
EN2
(R/W)
(0)
1
EN1
(R/W)
(0)
0
EN0
(R/W)
(0)
←Bit No.
DTP/external interrupt cause register
15
14
ER7
ER6
Address: 000031H
(R/W) (R/W)
Read/write→
Initial value→
(X)
(X)
13
ER5
(R/W)
(X)
12
ER4
(R/W)
(X)
11
ER3
(R/W)
(X)
10
ER2
(R/W)
(X)
9
ER1
(R/W)
(X)
8
ER0
(R/W)
(X)
←Bit No.
Request level setting register
15
LB7
Address: 000033H
(R/W)
Read/write→
Initial value→
(0)
14
LA7
(R/W)
(0)
13
LB6
(R/W)
(0)
12
LA6
(R/W)
(0)
11
LB5
(R/W)
(0)
10
LA5
(R/W)
(0)
9
LB4
(R/W)
(0)
8
LA4
(R/W)
(0)
←Bit No.
7
LB3
(R/W)
(0)
6
LA3
(R/W)
(0)
5
LB2
(R/W)
(0)
4
LA2
(R/W)
(0)
3
LB1
(R/W)
(0)
2
LA1
(R/W)
(0)
1
LB0
(R/W)
(0)
0
LA0
(R/W)
(0)
←Bit No.
Address: 000032H
Read/write→
Initial value→
ENIR
EIRR
ELVR
237
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.2 DTP/External Interrupt Registers
The DTP/external interrupts has the following three types of registers:
• DTP/external interrupt enable register (ENIR: Interrupt request enable register)
• DTP/external interrupt cause register (EIRR: External interrupt request register)
• Request level setting register (ELVR: External level register)
■ DTP/external Interrupt Enable Register (ENIR: Interrupt Request Enable Register)
Figure 16.2-1 shows the bit configuration of the DTP/external interrupt enable register (ENIR).
Figure 16.2-1 DTP/external Interrupt Enable Register (ENIR)
Address: 000030H
Read/write→
Initial value→
7
EN7
(R/W)
(0)
6
EN6
(R/W)
(0)
5
EN5
(R/W)
(0)
4
EN4
(R/W)
(0)
3
EN3
(R/W)
(0)
2
EN2
(R/W)
(0)
1
EN1
(R/W)
(0)
0
EN0
(R/W)
(0)
←Bit No.
ENIR
ENIR enables the function to issue a request to the interrupt controller using a device pin as an
DTP/external interrupt request input. A pin corresponding to a "1" bit of this register is used as an
DTP/external interrupt request input. A pin corresponding to a "0" bit holds the DTP/external
interrupt request input cause, but does not issue a request to the interrupt controller.
■ DTP/external Interrupt Cause Register (EIRR: External Interrupt Request Register)
Figure 16.2-2 shows the bit configuration of the DTP/external interrupt cause register (EIRR).
Figure 16.2-2 DTP/external Interrupt Cause Register (EIRR)
Address: 000031H
Read/write→
Initial value→
15
ER7
(R/W)
(X)
14
ER6
(R/W)
(X)
13
ER5
(R/W)
(X)
12
ER4
(R/W)
(X)
11
ER3
(R/W)
(X)
10
ER2
(R/W)
(X)
9
ER1
(R/W)
(X)
8
ER0
(R/W)
(X)
←Bit No.
EIRR
The EIRR indicates the presence of DTP/external interrupt requests at the pins corresponding to
the "1" bits of this register. Writing "0" to a bit of this register clears the corresponding request
flag. Writing "1" has no effect. "1" is always read from this register by a read-modify-write
instruction.
Note:
If more than one external interrupt request output is enabled (EN7 to EN0 of ENIR are set to "1"),
clear to "0" only the bit for which the CPU accepted an interrupt (any of bits ER7 to ER0 that are set
to "1"). Do not clear the other bits without a valid reason.
238
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
■ Request Level Setting Register (ELVR: External Level Register)
Figure 16.2-3 shows the bit configuration of the request level setting register (ELVR).
Figure 16.2-3 Request Level Setting Register (ELVR)
14
LA7
(R/W)
(0)
13
LB6
(R/W)
(0)
12
LA6
(R/W)
(0)
11
LB5
(R/W)
(0)
10
LA5
(R/W)
(0)
9
LB4
(R/W)
(0)
8
LA4
(R/W)
(0)
←Bit No.
Address: 000033H
Read/write→
Initial value→
15
LB7
(R/W)
(0)
6
LA3
(R/W)
(0)
5
LB2
(R/W)
(0)
4
LA2
(R/W)
(0)
3
LB1
(R/W)
(0)
2
LA1
(R/W)
(0)
1
LB0
(R/W)
(0)
0
LA0
(R/W)
(0)
←Bit No.
Address: 000032H
Read/write→
Initial value→
7
LB3
(R/W)
(0)
ELVR
ELVR defines the request event at the external pin. Each pin is assigned two bits as described in
Table 16.2-1. If a request is detected by the input level, the interrupt flag is set as long as the
input is at the specified level even after the flag is reset by software.
Table 16.2-1 Interrupt Request Detection Factor for LBx and LAx Pins
LBx
LAx
0
0
1
1
0
1
0
1
Interrupt request detection factor
"L" level is input to pin.
"H" level is input to pin.
Rising edge is input to pin.
Falling edge is input to pin.
239
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.3 Operations of DTP/External Interrupts
When the interrupt flag is set, this block signals an interrupt to the interrupt controller.
The interrupt controller judges the priority levels of the simultaneous interrupts, and
issues an interrupt request to the F2MC-16LX CPU if the interrupt from this block has
the highest priority. The F2MC-16LX CPU compares the ILM bits of its internal CCR
register and the interrupt request. If the interrupt level of the request is higher than that
indicated by the ILM bits, the F2MC-16LX CPU activates the hardware interrupt
processing microprogram as soon as the currently executing instruction is terminated.
■ External Interrupt Operation
In the hardware interrupt processing microprogram, the CPU reads the ISE bit information from
the interrupt controller, identifies that the request is for interrupt processing based on that
information, and branches to the interrupt processing microprogram. The interrupt processing
microprogram reads the interrupt vector area and issues an interrupt acknowledgment signal for
the interrupt controller. Then, the microprogram transfers the jump destination address of the
macro instruction generated from the vector to the program counter, and executes the user
interrupt processing program.
Figure 16.3-1 External Interrupt
DTP/External interrupt
Interrupt controller
F2MC-16LX CPU
ICRyy
IL
Other request
ELVR
EIRR
ENIR
Cause
240
CMP
ICRxx
CMP
ILM
NTA
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
■ DTP Operation
To activate the intelligent I/O service, the user program initially sets the address of a register,
assigned between 000000H and 0000FFH, in the I/O register address pointer of the intelligent I/
O service descriptor. Then, the user program sets the start address of the memory buffer in the
buffer address pointer.
The DTP operation sequence is almost the same as for external interrupts. The operation is
identical until the CPU activates the hardware interrupt processing microprogram. Then, for the
DTP, control is transferred to the intelligent I/O service processing microprogram, since the ISE
bit read by the CPU within the hardware interrupt processing microprogram indicates the DTP.
Once the intelligent I/O service is activated, a read or write signal is sent to the addresses
external peripheral, and data is transferred between the peripheral and the chip. The external
peripheral must cancel the interrupt request to this chip within three machine cycles after the
transfer is made. When the transfer is completed, the descriptor is updated, and the interrupt
controller generates a signal that clears the transfer cause. Upon receiving the signal to clear the
transfer cause, this resource clears the flip-flop holding the cause and prepares for the next
request from the pin. For details of the intelligent I/O service processing, refer to the MB90500
Programming Manual.
Figure 16.3-2 Timing to Cancel the External Interrupt at the End of DTP Operation
Edge request or H level request
Interrupt cause
Internal operation
Selecting and
reading
descriptor
When data is transferred from the I/O register to memory
in the extended intelligent I/O service
Read address
Address bus pin
Data bus pin
Write address
Read data
Read signal
Write data
➀
Write signal
➁
Cancel within three machine cycles.
Data, address
bus
Internal data bus
Register
External peripheral
Figure 16.3-3 Sample Interface to the External Peripheral
➀
INT
IRQ
DTP
Cancel within three machine
cycles after transfer.
➁
CORE
MEMORY
MB90540/545
241
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.4 Switching between External Interrupt and DTP Requests
To switch between external interrupt and DTP requests, use the ISE bit in the ICR
register corresponding to this block, which is in the interrupt controller. Each pin is
individually assigned ICR. Thus, a pin is used for a DTP request if "1" is written to the
ISE bit of the corresponding ICR, and is used for an external interrupt request if "0" is
written to the bit.
■ Switching Between External Interrupt and DTP Requests
Figure 16.4-1 Switching Between External Interrupt and DTP Requests
Interrupt controller
0
ICR xx
ICR yy
1
F 2 MC-16 LX CPU
Pin
DTP/
External interrupt
DTP
External interrupt
242
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.5 Notes on Using DTP/External Interrupts
Note carefully the following items when using DTP/external interrupts:
• Conditions on the externally connected peripheral when DTP is used
• DTP/external interrupt operation procedure
• External interrupt request level
■ Notes on Using DTP/External Interrupts
❍ Conditions on the externally connected peripheral when DTP is used
DTP supports only external peripherals that automatically clear a request once a transfer is
completed. The system must be designed so that a transfer request is canceled within three
machine cycles (provisional) after transfer operation starts. Otherwise, this resource assumes
that a transfer request is issued.
❍ DTP/external interrupt operation procedure
To set registers in the DTP/external interrupt, follow the steps below:
1. Set the general-purpose I/O port that is shared with the pin for the external interrupt input as
the input port.
2 Disable the bits corresponding to the enable register.
3. Set the bits corresponding to the request level setting register.
4. Clear the bits corresponding to the cause register.
5. Enable the bits corresponding to the enable register.
(Steps 4. and 5. can be simultaneously performed by word specification.)
To set a register in this resource, ensure that the enable register is disabled. Before enabling the
enable register, ensure that the cause register is cleared. Clearing the cause register prevents a
false interrupt cause from being determined while registers are set or interrupts are enabled.
243
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
❍ External interrupt request level
To detect an edge for an edge request level, the pulse width must be at least three machine
cycles.
To detect an edge for an edge request level, the pulse width must be at least three machine
cycles.
As shown in Figure 16.5-1, when the request input level is related to the level setting, a request
that is input from an external device to the interrupt controller is kept active while the interrupt
request is enable (ENIR:EN=1) even if the request is later canceled.
To cancel the request to the interrupt controller, the interrupt request flag bit (EIRR:ER) must be
cleared as shown in Figure 16.5-2.
Figure 16.5-1 Clearing the Interrupt Request Flag Bit (EIRR: ER) Upon Level Set
Interrupt cause
Level detection
The interrupt request flag bit
(EIRR: ER)
Enable gate
To interrupt
controller
The cause is kept holding unless cleared.
Figure 16.5-2 Interrupt Cause and Interrupt Request to the Interrupt Controller While Interrupts are
Enabled
Interrupt cause
(At the "H" level detection)
Interrupt request to
the interrupt controller
Canceled interrupt cause
Set inactive when the interrupt request
flag bit (EIRR: ER) is cleared.
244
CHAPTER 17
A/D CONVERTER
This chapter explains the functions and operations of the A/D converter.
17.1 Features of A/D Converter
17.2 Block Diagram of A/D Converter
17.3 A/D Converter Registers
17.4 Operations of A/D Converter
17.5 Conversion Using EI2OS
17.6 Conversion Data Protection Function
245
CHAPTER 17 A/D CONVERTER
17.1 Features of A/D Converter
The A/D converter converts analog input voltages into digital values. The A/D converter
has the following features:
■ Features of A/D Converter
❍ Conversion time:
26.3 µs min. per channel (at 16 MHz machine clock)
❍ RC sequential compare conversion with sample and hold circuit
❍ 10-bit or 8-bit resolution
❍ Analog input selected from eight channels by programming
• Single conversion mode:
One channel is selected for conversion.
• Scan conversion mode:
Voltages in multiple consecutive channels are converted. Up to
eight channels can be programmed.
• Continuous conversion mode: Voltages at the specified channel are converted repeatedly.
• Stop conversion mode:
The specified channel is converted, then the system pauses
and stands by for the next activation. (The conversion start
points can be synchronized.)
❍ Interrupt request
At the end of A/D conversion, a relevant interrupt request can be issued to the CPU. This
interrupt can be used to activate the EI2OS, which automatically transfers A/D conversion result
to memory. This feature is suitable for continuous processing.
❍ Selectable activation cause
The activation can be done by software, external trigger (falling edge), or timer (rising edge).
246
CHAPTER 17 A/D CONVERTER
■ Analog Input Enable Register
Always write "1" to the ADER bit corresponding to a pin used as analog input.
Figure 17.1-1 shows the bit configuration of the analog input enable register.
Figure 17.1-1 Analog Input Enable Register
Address: 00001BH
Read/write→
Initial value→
7
ADE7
R/W
(1)
6
ADE6
R/W
(1)
5
ADE5
R/W
(1)
4
ADE4
R/W
(1)
3
ADE3
R/W
(1)
2
ADE2
R/W
(1)
1
ADE1
R/W
(1)
0
ADE0
R/W
(1)
←Bit No.
ADER
Port 6 pins are controlled as described below.
• 0: Port input/output mode
• 1: Analog input mode
• "1" is set upon a reset.
■ Input Impedance
The sampling circuit of the A/D converter can be represented with the equivalent circuit shown
below.
Figure 17.1-2 Input Impedance
3.2 kΩ Max
Analog input
ADC
30 pF Max
Driving impedance to an analog input should be 15.5 kΩ or lower when the sampling time is set
to 4µs (ST=0 and ST0=0 at 16MHz machine clock). Otherwise the conversion accuracy will be
worsened. In this case, set the sampling time longer (ST1=1 and ST0=1) or add external
capacitor in order to compensate the driving impedance.
247
CHAPTER 17 A/D CONVERTER
17.2 Block Diagram of A/D Converter
Figure 17.2-1 shows a block diagram of the A/D converter.
■ Block Diagram of A/D Converter
Figure 17.2-1 Block Diagram of A/D Converter
AVCC
AVRH/L
AVSS
A/D converter
Sequential compare register
Comparator
Decoder
Sample and hold circuit
A/D data register
ADCR0/1
A/D control status register 0
A/D control status register 1
ADCS0/
ADCS1
Activation by external trigger
ADTG pin
Activation by timer
Operation clock
16-bit Reload Timer 1
Prescaler
248
Internal data bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Input circuit
MPX
CHAPTER 17 A/D CONVERTER
17.3 A/D Converter Registers
The A/D converter has the following two types of registers:
• A/D Control status resister 0/1
• A/D Data register 0/1
■ A/D Converter Registers
The A/D converter has the following registers:
Figure 17.3-1 A/D Converter Register Assignment
15
8 7
0
ADCS1
ADCS0
ADCR1
8 bit
ADCR0
8 bit
Figure 17.3-2 shows the bit configuration of the A/D converter registers.
Figure 17.3-2 A/D Converter Registers
A/D control status register 0
7
MD1
Address: 000034H
(R/W)
Read/write→
Initial value→
(0)
6
MD0
(R/W)
(0)
5
ANS2
(R/W)
(0)
4
ANS1
(R/W)
(0)
3
ANS0
(R/W)
(0)
2
ANE2
(R/W)
(0)
1
ANE1
(R/W)
(0)
0
ANE0
(R/W)
(0)
←Bit No.
A/D control status register 1
15
BUSY
Address: 000035H
(R/W)
Read/write→
Initial value→
(0)
14
INT
(R/W)
(0)
13
INTE
(R/W)
(0)
12
PAUS
(R/W)
(0)
11
STS1
(R/W)
(0)
10
STS0
(R/W)
(0)
9
STRT
(W)
(0)
8
←Bit No.
Reserved
ADCS0
ADCS1
(R/W)
(0)
A/D Data register 0
Address: 000036H
Read/write→
7
D7
(R)
6
D6
(R)
5
D5
(R)
4
D4
(R)
3
D3
(R)
2
D2
(R)
1
D1
(R)
0
D0
(R)
←Bit No.
A/D Data register 1
Address: 000037H
Read/write→
Initial value→
Initial value→
15
SI0
(W)
(0)
(X)
14
ST1
(W)
(0)
(X)
13
ST0
(W)
(0)
(X)
12
CT1
(W)
(0)
(X)
11
CT0
(W)
(1)
(X)
10
⎯
(-)
(-)
(X)
9
D9
(R)
(X)
(X)
8
D8
(R)
(X)
(X)
←Bit No.
ADCR0
ADCR1
249
CHAPTER 17 A/D CONVERTER
17.3.1 A/D Control Status Register 0 (ADCS0)
The A/D control status register 0 (ADCS0) controls the A/D converter and indicates the
status. Do not rewrite ADCS0 during A/D conversion.
■ A/D Control Status Register 0 (ADCS0)
Figure 17.3-3 shows the bit configuration of the A/D control status register (ADCS0).
Figure 17.3-3 A/D Control Status Register 0 (ADCS0)
Address: 000034H
Read/write→
Initial value→
7
MD1
(R/W)
(0)
6
MD0
(R/W)
(0)
5
ANS2
(R/W)
(0)
4
ANS1
(R/W)
(0)
3
ANS0
(R/W)
(0)
2
ANE2
(R/W)
(0)
1
ANE1
(R/W)
(0)
0
ANE0
(R/W)
(0)
←Bit No.
ADCS0
[bit7 and bit6] MD1 and MD0 (A/D converter mode set):
Use the MD1 and MD0 bits to set the operation mode.
MD1
MD0
Operation mode
0
0
Single mode. Reactivation during operation is allowed.
0
1
Single mode. Reactivation during operation is not allowed.
1
0
Continuous mode. Reactivation during operation is not allowed.
1
1
Stop mode. Reactivation during operation is not allowed.
❍ Single mode:
A/D conversion is continuously performed from the channel specified with ANS2 to ANS0 to the
channel specified with ANE2 to ANE0. The conversion stops once it has been done for all these
channels.
❍ Continuous mode:
A/D conversion is repeatedly performed from the channel specified with ANS2 to ANS0 to the
channel specified with ANE2 to ANE0.
250
CHAPTER 17 A/D CONVERTER
❍ Stop mode:
A/D conversion is performed from the channel specified with ANS2 to ANS0 to the channel
specified with ANE2 to ANE0, pausing for each channel. The A/D conversion is resumed upon an
activation.
Upon a reset, these bits are initialized to "00B".
Note:
When activated in the continuous or stop mode, A/D conversion continues until it is stopped by the
BUSY bit.
The conversion is stopped by writing "0" to the BUSY bit.
Reactivation disabled in single mode, continuous mode, and stop mode applies to all kinds of
activation by software, an external trigger, and a timer.
[bit5, bit4, and bit3] ANS2, ANS1, and ANS0 (Analog start channel set):
Use these bits to specify the start channel for A/D conversion.
When the A/D converter is activated, A/D conversion starts from the channel selected with
these bits.
ANS2
ANS1
ANS0
Start channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
Notes:
• Read
During A/D conversion, the current conversion channel is read from these bits. If the system is
stopped in the stop mode, the last conversion channel is read.
And before A/D conversion starts, the previous conversion channel will be read even if these bits
have already been set to the new value.
• Upon a reset, these bits are initialized to "000B".
251
CHAPTER 17 A/D CONVERTER
[bit2, bit1, and bit0] ANE2, ANE1, and ANE0 (Analog end channel set):
Use these bits to set the A/D conversion end channel.
ANE2
ANE1
ANE0
End channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
Notes:
• When the same channel is written to ANE2 to ANE0 and ANS2 to ANS0, conversion is performed
for one channel only (single conversion).
• In the continuous or stop mode, operation returns to the start channel specified in ANS2 to ANS0
after the conversion is completed for the channel specified in ANE2 to ANE0.
• If the ANS value is greater than the ANE value, conversion starts from the ANS channel. Then,
once conversion is complete up to AN7, operation returns to AN0 and conversion is performed up
to the ANE channel.
Example:
ANS=6, ANE=3, single mode
Conversion is performed in the following sequence
AN6 → AN7 → AN0 → AN1 → AN2 → AN3
• Upon a reset, these bits are initialized to "000B".
252
CHAPTER 17 A/D CONVERTER
17.3.2 A/D Control Status Register 1 (ADCS1)
The A/D control status register 1 (ADCS1) controls the A/D converter and indicates the
status.
■ A/D Control Status Register 1 (ADCS1)
Figure 17.3-4 shows the bit configuration of the A/D control status register (ADCS1).
Figure 17.3-4 A/D Control Status Register 1 (ADCS1)
Address: 000035H
Read/write→
Initial value→
15
BUSY
(R/W)
(0)
14
INT
(R/W)
(0)
13
INTE
(R/W)
(0)
12
PAUS
(R/W)
(0)
11
STS1
(R/W)
(0)
10
STS0
(R/W)
(0)
9
STRT
(W)
(0)
8
Reserved
←Bit No.
ADCS1
(R/W)
(0)
[bit15] BUSY (busy flag and stop)
•
•
Read
-
This bit indicates the A/D converter operation.
-
This bit is set when A/D conversion starts and is cleared when the conversion ends.
Write
-
Writing "0" to this bit during A/D conversion forces the conversion to terminate.
-
The above feature is used for forced stop in continuous or stop mode.
"1" cannot be written to the BUSY bit. With a read-modify-write (RMW) instruction, "1" is read
from this bit. In single mode, this bit is cleared at the end of A/D conversion.
In continuous or stop mode, this bit is not cleared until conversion is stopped by writing "0".
This bit is initialized to "0" upon a reset.
Do not perform a forced stop and activation by software simultaneously (BUSY = 0, STRT =
1).
[bit14] INT (Interrupt)
This bit is set when conversion data is written to ADCR.
An interrupt request is issued if this bit is set while bit5 (INTE) is "1". In addition, the EI2OS is
activated if it is enabled. Writing "1" has no effect.
This bit is cleared by writing "0" or by the EI2OS interrupt clear signal.
Note:
To clear this bit by writing "0", ensure that A/D conversion is not in progress.
This bit is initialized to "0" upon a reset.
253
CHAPTER 17 A/D CONVERTER
[bit13] INTE (Interrupt enable)
This bit is used to enable or disable interrupts at the end of conversion.
- 0: Interrupts are disabled.
- 1: Interrupts are enabled.
Set this bit when using the EI2OS. The EI2OS is activated when an interrupt request is issued.
Upon a reset, this bit is initialized to "0".
[bit12] PAUS (A/D conversion pause)
This bit is set when the A/D conversion is paused.
Only one register is available for storing the A/D conversion result. Therefore, unless the
conversion results are transferred by the EI2OS, the result data would be continuously
updated and destroyed in continuous conversion.
To prevent the above condition, the system is designed so that a data register value must be
transferred by the EI2OS before the next conversion data is saved. A/D conversion pauses
during that period. A/D conversion is resumed at the end of transfer by the EI2OS.
This bit is valid only when the EI2OS is used.
Notes:
• For the conversion data protection function, see section "17.4 Operations of A/D Converter".
• Upon a reset, this bit is initialized to "0".
254
CHAPTER 17 A/D CONVERTER
[bit11 and bit10] STS1 and STS0 (Start source select)
Upon a reset, these bits are initialized to "00B".
These bits are used to select the A/D conversion activation source.
STS1
STS0
Function
0
0
Activation by software
0
1
Activation by external pin trigger and software
1
0
Activation by timer and software
1
1
Activation by external pin trigger, timer, and software
In a mode allowing two or more activation factors, A/D conversion is activated by the source
that occurs first.
The activation source setting changes as soon as it is updated. Thus, take care when
updating it during A/D conversion.
Notes:
• The external pin trigger is detected by the falling edge. If this bit is updated to external trigger
activation while the external trigger input level is "L", A/D may be activated at once.
• When timer is selected, the 16-bit Reload Timer 1 is selected.
[bit9] STRT (Start)
A/D conversion is activated when "1" is written to this bit.
To reactivate A/D conversion, write "1" to this bit again.
Upon a reset, this bit is initialized to "0".
In the stop mode, a reactivation during the operation is not supported. Check the BUSY bit
before writing "1".
Do not perform a forced stop and activation by software simultaneously. (BUSY=0, STRT=1)
The byte/word instructions read "1".
The read-modify-write type instructions read "0".
[bit8] Reserved bit
Always write "0" to this bit.
255
CHAPTER 17 A/D CONVERTER
17.3.3 A/D Data Register 0/1(ADCR0 and ADCR1)
These registers are used to store the digital values produced as a result of the
conversion. ADCR1 stores ADCR0 stores the lower 8 bits result, while the most
significant 2 bits of the conversion. These register values are updated each time
conversion is completed. Usually, the final conversion value is stored in these bits.
■ A/D Data Registers 0/1 (ADCR0 and ADCR1)
Figure 17.3-5 shows the bit configuration of the A/D data registers (ADCR0 and ADCR1).
Figure 17.3-5 A/D Data Register 0/1(ADCR0 and ADCR1)
A/D Data register 0
Address: 000036H
Read/write→
Initial value→
7
D7
(R)
(X)
6
D6
(R)
(X)
5
D5
(R)
(X)
4
D4
(R)
(X)
3
D3
(R)
(X)
2
D2
(R)
(X)
1
D1
(R)
(X)
0
D0
(R)
(X)
←Bit No.
15
SI0
(W)
(0)
14
ST1
(W)
(0)
13
ST0
(W)
(0)
12
CT1
(W)
(0)
11
CT0
(W)
(1)
10
⎯
(-)
(-)
9
D9
(R)
(X)
8
D8
(R)
(X)
←Bit No.
ADCR0
A/D Data register 1
Address: 000037H
Read/write→
Initial value→
ADCR1
"0" is always read from the bit10 to bit15 of ADCR1.
The conversion data protection function is available. See section "17.4 Operations of A/D
Converter" for details. Ensure that no data is written to these registers during A/D conversion.
[bit15] SI0
This bit specifies the resolution of the conversion. When it is set to "0", the 10-bit A/D
conversion is performed. Otherwise the 8-bit A/D conversion is performed and the result is
stored in the D7 to D0.
Reading this bit always returns "0".
[bit14 and bit13] ST1 and ST0 (Sampling time)
ST1
ST0
Function
0
0
64 machine cycles (4µs at 16MHz)
0
1
Reserved
1
0
Reserved
1
1
4096 machine cycles (256µs at 16MHz)
These bits determine the duration of the voltage sampling time at the input.
Reading these bits always returns "00B".
256
CHAPTER 17 A/D CONVERTER
[bit12 and bit11] CT1 and CT0 (Compare time)
CT1
CT0
Function
0
0
176 machine cycles (22µs at 8MHz)
0
1
352 machine cycles (22µs at 16MHz)
1
0
Reserved
1
1
Reserved
These bits determine the duration of the compare operation time.
Set these bits to "00B" while the machine clock is 8MHz or less. Conversion accuracy is not
guaranteed when the machine clock is more than 8MHz.
Reading these bits always returns "00B".
257
CHAPTER 17 A/D CONVERTER
17.4 Operations of A/D Converter
The A/D converter operates in the sequential compare technique, and can select a 10-bit
or 8-bit resolution.
Since the A/D converter has only one register (16 bits) for storing the conversion result,
the A/D data registers 0/1(ADCR0 and ADCR1) are updated each time conversion is
completed. Thus, the A/D converter alone must not be used for the continuous
conversion. Use the F2MC-16 intelligent I/O service (EI2OS) function to transfer
converted data to memory while conversion is in progress.
The operation modes are explained below.
■ Single Mode
In this mode, the converter sequentially converts the analog inputs specified with the ANS and
ANE bits. The A/D converter stops operation after the conversion is completed for the end
channel specified with the ANE bits. If the start and end channels are the same (ANS=ANE),
conversion is performed only for one channel.
Example:
ANS = 000B, ANE = 011B
Start → AN0 → AN1 → AN2 → AN3 → End
ANS = 010B, ANE = 010B
Start → AN2 → End
■ Continuous Mode
In this mode, the converter sequentially converts the analog inputs specified with the ANS and
ANE bits. After the conversion is completed for the end channel specified with the ANE bits,
conversion is repeated from the analog inputs of the ANS. If the start and end channels are the
same (ANS=ANE), conversion for one channel is repeated.
Example:
ANS = 000B, ANE = 011B
Start → AN0 → AN1 → AN2 → AN3 → AN0 → Repeat
ANS = 010B, ANE = 010B
Start → AN2 → AN2 → AN2 → Repeat
In continuous mode, conversion is repeated until "0" is written to the BUSY bit. (Writing "0" to the
BUSY bit forces the operation to end.) If the operation is terminated forcibly, conversion stops
before conversion is completed. (Upon a forced stop, the conversion register stores the last data
that has been converted completely.)
258
CHAPTER 17 A/D CONVERTER
■ Stop Mode
In this mode, the converter sequentially converts the analog inputs specified with the ANS and
ANE bits, pausing each time conversion for one channel is completed. To release pausing,
activate the converter again.
After the conversion is completed for the end channel specified with the ANE bits, conversion is
repeated from the analog inputs of the ANS. If the start and end channels are the same
(ANS=ANE), conversion is performed only for one channel.
Example:
ANS = 000B, ANE = 011B
Start → AN0 → Stop → Restart → AN1 → Stop → Restart → AN2 → Stop →
→ Restart → AN3 → Stop → Restart → AN0 → Repeat
ANS = 010B, ANE = 010B
Start → AN2 → Stop → Restart → AN2 → Stop → Restart → AN2 → Repeat
Only the activation sources specified with STS1 and STS0 are used.
Using this mode, start of conversion can be synchronized with the activation source.
259
CHAPTER 17 A/D CONVERTER
17.5 Conversion Using EI2OS
Figure 17.5-1 shows the processing flow from the start of A/D conversion to the transfer
of converted data (in continuous mode).
■ Conversion Using EI2OS
Figure 17.5-1 A/D Conversion Processing Flow from the Start to Converted Data Transfer
(in Continuous Mode)
Starting A/D conversion
Sample and hold
Starting EI2OS
Transferring data
Conversion
End of conversion
Issuing interrupt
*
Clearing interrupt
*: is determined according to the EI2OS setting.
260
Interrupt processing
CHAPTER 17 A/D CONVERTER
17.5.1 Example of Starting EI2OS in Single Mode
Follow the steps below to start the EI2OS in single mode.
• To terminate conversion after analog inputs AN1 to AN3 are converted
• To transfer conversion data sequentially to addresses 200H to 205H
• To start conversion by software
• To use the highest interrupt level
■ Example of Starting EI2OS in Single Mode
Table 17.5-1 Example of Starting EI2OS in Single Mode
Settings
Sample program
MOV ICR3, #08H
Function
Specifies the highest interrupt level, EI2OS
activation upon an interrupt, and the descriptor
address.
MOV BAPL, #00H
MOV BAPM, #02H
The transfer destination address of converted data.
MOV BAPH, #00H
2
EI OS setting
A/D converter
setting
Interrupt
sequence
MOV ISCS, #18H
Specifies word data transfer. The transfer
destination address is incremented after transfer.
Data is transferred from I/O to memory. Transfer is
not terminated in response to a request from a
resource.
MOV I/OA, #36H
Transfer source address
MOV DCT, #03H
EI2OS transfer is performed three times. This count
is the same as the conversion count.
MOV ADCS0 #0BH
Single mode, start channel AN1, and end channel
AN3
MOV ADCS1 #A2H
Activation by software and start of A/D conversion
RET
Return from an interrupt
ICR3: Interrupt control register
BAPL: Buffer address pointer, low-order
BAPM: Buffer address pointer, medium-order
BAPH: Buffer address pointer, high-order
ISCS: EI2OS status register
I/OA: I/O address counter
DCT: Data counter
261
CHAPTER 17 A/D CONVERTER
Figure 17.5-2 Example of Starting EI2OS in Single Mode
Start activation
AN1
Interrupt
EI2 OS transfer
AN2
Interrupt
EI 2OS transfer
AN3
Interrupt
EI 2OS transfer
EndInterrupt sequence
Parallel processing
262
CHAPTER 17 A/D CONVERTER
17.5.2 Example of Starting EI2OS in Continuous Mode
Follow the steps below to start the EI2OS in continuous mode.
• To convert analog inputs AN3 to AN5 and obtain two conversion data items for each
channel
• To transfer conversion data sequentially to addresses 600H to 60BH
• To start conversion by external edge input
• To use the highest interrupt level
■ Example of Starting EI2OS in Continuous Mode
Table 17.5-2 Example of Starting EI2OS in Continuous Mode
Settings
Sample program
MOV ICR3, #08H
Function
Specifies the highest interrupt level, EI2OS
activation upon an interrupt, and the descriptor
address.
MOV BAPL, #00H
MOV BAPM, #06H
The transfer destination address of converted
data.
MOV BAPH, #00H
2
EI OS setting
MOV ISCS, #18H
Specifies word data transfer. The transfer
destination address is incremented after
transfer. Data is transferred from I/O to
memory. Transfer is not terminated in
response to a request from a resource.
MOV I/OA, #36H
Transfer source address
MOV DCT, #06H
EI2OS transfer is performed six times. Data is
transferred for three channels x 2.
MOV ADCS0 #9DH
Continuous mode, start channel AN3, and end
channel AN5
MOV ADCS1 #A4H
Activation by external edge and start of A/D
conversion
A/D converter setting
Interrupt sequence
MOV ADCS1 #00H
Return from an interrupt
RET
ICR3: Interrupt control register
BAPL: Buffer address pointer, low-order
BAPM: Buffer address pointer, medium-order
BAPH: Buffer address pointer, high-order
ISCS: EI2OS status register
I/OA: I/O address counter
DCT: Data counter
263
CHAPTER 17 A/D CONVERTER
Figure 17.5-3 Example of Starting EI2OS in Continuous Mode
Start activation
EI 2 OS transfer
AN3
Interrupt
AN4
Interrupt
EI 2 OS transfer
AN5
Interrupt
EI 2 OS transfer
After a total of
six transfers
Interrupt sequence
End
264
CHAPTER 17 A/D CONVERTER
17.5.3 Example of Starting EI2OS in Stop Mode
Follow the steps below to start the EI2OS in stop mode.
• To convert analog input AN3 12 times at fixed intervals
• To transfer conversion data sequentially to addresses 600H to 617H
• To start conversion by external edge input
• To use the highest interrupt level
■ Example of Starting EI2OS in Stop Mode
Table 17.5-3 Example of Starting EI2OS in Stop Mode
Settings
Sample program
MOV ICR3, #08H
Function
Specifies the highest interrupt level, EI2OS
activation upon an interrupt, and the
descriptor address.
MOV BAPL, #00H
MOV BAPM, #06H
EI2OS setting
The transfer destination address of
converted data.
MOV BAPH, #00H
MOV ISCS, #18H
Specifies word data transfer. The transfer
destination address is incremented after
transfer. Data is transferred from I/O to
memory. Transfer is not terminated in
response to a request from a resource.
MOV I/OA, #36H
Transfer source address
MOV DCT, #0CH
EI2OS transfer is performed 12 times.
MOV ADCS0 #DBH
Stop mode, start channel AN3, and end
channel AN3 (one-channel conversion)
MOV ADCS1 #A4H
Activation by external edge and start of A/D
conversion
A/D converter setting
Interrupt sequence for
terminating
EI2OS
MOV ADCS1 #00H
Return from an interrupt
RET
ICR3: Interrupt control register
BAPL: Buffer address pointer, low-order
BAPM: Buffer address pointer, medium-order
BAPH: Buffer address pointer, high-order
ISCS: EI2OS status register
I/OA: I/O address counter
DCT: Data counter
265
CHAPTER 17 A/D CONVERTER
Figure 17.5-4 Example of Starting EI2OS in Stop Mode
Start activation
2
AN3 → Interrupt → EI OS transfer
After 12 transfers
Stop
Activation by external edge
Interrupt sequence
End
266
CHAPTER 17 A/D CONVERTER
17.6 Conversion Data Protection Function
The A/D converter has a conversion data protection function that enables continuous
conversion and preservation of multiple data items using EI2OS.
One A/D data register is provided, and its value is updated after conversion. When
continuous A/D conversion is performed, conversion data is stored upon completion of
each conversion and the previous data is lost. To prevent this situation, the A/D
converter pauses without storing conversion data in the register if the previous data
has not been transferred to memory by EI2OS, even though conversion has been
completed.
■ Conversion Data Protection Function
The pause is released after data is transferred to memory by EI2OS.
If the previous data has been transferred to memory, the A/D converter continues operation
without pausing.
Note:
This function is related to the INT and INTE bits of ADCS1.
The conversion data protection function operates only when interrupts are enabled (INTE=1).
If interrupts are disabled (INTE=0), this function does not work. Continuous A/D conversion results in
loss of previous data, since the converted data items are saved to the register one after another.
If EI2OS is not used while interrupts are enabled (INTE=1), the INT bit is not cleared. Thus, the data
protection function works and the A/D converter pauses. In this case, clearing the INT bit in the
interrupt sequence releases the pause.
If the A/D converter is pausing during EI2OS operation, disabling interrupts may restart the A/D
converter. In this case, the value in the A/D data register may be changed without being transferred.
Also, the standby data is destroyed if the A/D is restarted during a suspension (pause).
267
CHAPTER 17 A/D CONVERTER
■ Flow of Conversion Data Protection Function (When EI2OS is Used)
Figure 17.6-1 Flow of Conversion Data Protection Function (When EI2OS Is Used)
Setting EI 2OS
Starting continuous A/D conversion
Ending of first conversion
Saving the result in the A/D data register
Starting EI2 OS
Ending of second conversion
End EI 2 OS?
NO
Pausing A/D conversion
YES
Saving the result in the A/D data register
YES
End EI2OS?
*
NO
Starting EI 2OS
Ending of third conversion
Continued
Starting EI 2 OS
Ending the last conversion
Interrupt routine
End
Stopping A/D conversion
*: If the converter is restarted when it is pausing, standby conversion data is lost.
■ Notes on Using the Conversion Data Protection Function
To start the A/D converter upon an external trigger or internal timer, A/D activation factor bits
STS1 and STS0 of the ADCS1 register are used. Ensure that the input values of the external
trigger or internal timer are inactive. If the values are active, A/D conversion may start
immediately.
When setting STS1 and STS0, ensure that "1" (input) is specified for ADTG and "0" (output) is
specified for the internal timer (timer 2).
268
CHAPTER 18
UART0
This chapter explains the UART0 functions and operations.
18.1 Feature of UART0
18.2 UART0 Block Diagram
18.3 UART0 Registers
18.4 UART0 Operation
18.5 Baud Rate
18.6 Internal and External Clock
18.7 Transfer Data Format
18.8 Parity Bit
18.9 Interrupt Generation and Flag Set Timings
18.10 UART0 Application Example
269
CHAPTER 18 UART0
18.1 Feature of UART0
UART0 is a serial I/O port for asynchronous (start-stop) or CLK synchronous
communication with external devices.
■ Feature of UART0
UART0 has the following features.
270
•
Full duplex double buffer
•
Supports CLK synchronous and CLK asynchronous start-stop data transfer.
•
Multiprocessor mode support (mode 2)
•
Built in dedicated baud rate generator (12 types)
•
Supports flexible baud rate setting using an external clock input or internal timer.
•
Variable data length (7 to 9 bits, [no parity]; 6 to 8 bits [with parity]).
•
Error detect function (parity framing, and overrun)
•
Interrupt function (receive and transmit interrupts)
•
NRZ type transfer format
CHAPTER 18 UART0
18.2 UART0 Block Diagram
Figure 18.2-1 shows a block diagram of the UART0.
■ UART0 Block Diagram
Figure 18.2-1 Overall Block Diagram
Control signal
Receive interrupt
(to CPU)
Dedicated baud rate clock
SCK0
Transmit clock
16-bit reload timer 0
Clock select
circuit
Transmit interrupt
(to CPU)
Receive clock
SCK0
SIN0
Receive control circuit
Transmit control circuit
Start bit detect
circuit
Transmit start circuit
Receive bit counter
Transmit bit counter
Receive parity
counter
Transmit parity
counter
SOT0
Receive status
evaluation circuit
Receive shifter
Transmit shifter
Receive
complete
Transmit start
UIDR0
UODR0
Receive error
generation signal
for EI2OS (to CPU)
Internal data bus
UMC0
register
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
USR0
register
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
URD0
register
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
Control signal
271
CHAPTER 18 UART0
18.3 UART0 Registers
The UART0 has the following four registers:
• Serial mode control register
• Serial status register
• Serial input data register/serial output data register
• Rate and data register
■ UART0 Registers
Figure 18.3-1 shows the bit configuration of the UART0 register.
Figure 18.3-1 UART0 Register
Serial mode control register 0
7
PEN
Address: 000020H
(R/W)
Read/write→
Initial value→
(0)
6
SBL
(R/W)
(0)
5
MC1
(R/W)
(0)
4
3
MC0 SMDE
(R/W) (R/W)
(0)
(0)
2
RFC
(W)
(1)
1
SCKE
(R/W)
(0)
0
SOE
(R/W)
(0)
←Bit No.
12
TDRE
(R)
(1)
11
RIE
(R/W)
(0)
10
TIE
(R/W)
(0)
9
RBF
(R)
(0)
8
TBF
(R)
(0)
←Bit No.
3
2
1
0
←Bit No.
UMC0
Serial status register 0
Address: 000021H
Read/write→
Initial value→
15
14
RDRF ORFE
(R)
(R)
(0)
(0)
13
PE
(R)
(0)
Serial input data register 0/Serial output data register 0
7
6
5
4
Address: 000022H
Read/write→
Initial value→
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
14
RC3
(R/W)
(0)
13
RC2
(R/W)
(0)
12
RC1
(R/W)
(0)
11
RC0
(R/W)
(0)
10
BCH0
(R/W)
(0)
9
P
(R/W)
(0)
8
D8
(R/W)
(X)
USR0
UIDR0(read)
UODR0(write)
Rate and data register 0
Address: 000023H
Read/write→
Initial value→
272
15
BCH
(R/W)
(0)
←Bit No.
URD0
CHAPTER 18 UART0
18.3.1 Serial Mode Control Register 0 (UMC0)
UMC0 specifies the operation mode of UART0. Set the operation mode while operation
is halted. However, the RFC bit can be accessed during operation.
■ Serial Mode Control Register 0 (UMC0)
Figure 18.3-2 shows the bit configuration of the serial mode control register 0 (UMC0).
Figure 18.3-2 Serial Mode Control Register 0 (UMC0)
7
PEN
(R/W)
(0)
Address: 000020H
Read/write→
Initial value→
6
SBL
(R/W)
(0)
5
MC1
(R/W)
(0)
4
3
MC0 SMDE
(R/W) (R/W)
(0)
(0)
2
RFC
(W)
(1)
1
SCKE
(R/W)
(0)
0
SOE
(R/W)
(0)
←Bit No.
UMC0
[bit7] PEN (Parity enable)
Specifies whether to add (for transmit) or detect (for receive) a parity bit in serial data I/O. Set
to "0" in mode 2.
0: Do not use parity
1: Use parity
[bit6] SBL (Stop bit length)
Specifies the number of stop bits for transmit data. For receive data, the first stop bit only is
recognized and any second stop bit is ignored.
0: 1 bit length
1: 2 bit length
[bit5, bit4] MC1, MC0 (Mode control)
These bits control the length of the transferred data. Table 18.3-1 lists the four transfer modes
(data lengths) selectable by these bits.
Table 18.3-1 UART0 Operation Modes
Mode
MC1
MC0
Data Length*1
0
0
0
7 (6)
1
0
1
8 (7)
2*2
1
0
8+1
3
1
1
9 (8)
*1: The figures enclosed in parentheses indicate the data length with parity.
*2: Mode 2 is used when a number of slave CPUs are connected to a single host CPU.
As the receive parity check function cannot be used, set PEN in the UMC0 register to "0"
(see Section "18.4 UART0 Operation" for details). The transmit data length is 9 bits and
no parity bit can be added.
273
CHAPTER 18 UART0
[bit3] SMDE (Synchronous mode enable)
This bit selects the transfer method.
0:Start-stop CLK synchronous transfer (clocked synchronous transfer using start and stop
bits.)
1:Start-stop CLK asynchronous transfer
[bit2] RFC (Receiver flag clear)
Writing "0" to this bit clears the RDRF, ORFE, and PE flags in the USR0 register. Writing "1"
has no effect. Reading always returns "1".
Note:
When receive interrupts are enabled during UART0 operation, only write "0" to RFC when either
RDRF, ORFE, or PE is "1".
[bit1] SCKE (SCLK enable)
Writing "1" to this bit in CLK synchronous mode switches the port pin to the UART0 serial
clock output pin and outputs the synchronizing clock. Set to "0" in CLK asynchronous mode or
external clock mode.
0: The pin functions as a general purpose I/O port and does not output the serial clock. The
pin functions as the external clock input pin when the port is set to input mode (DDR=0)
and RC3 to 0 are set to "1111B".
1: The pin functions as the UART0 serial clock output pin.
[bit0] SOE (Serial Output Enable)
Writing "1" to this bit switches the port pin to the UART0 serial data output pin, enabling serial
output.
0: The pin functions as a port pin and does not output serial data.
1: The pin functions as the UART0 serial data output pin (SOT).
274
CHAPTER 18 UART0
18.3.2 Serial Status Register 0 (USR0)
USR0 indicates the current state of the UART0 port.
■ Serial Status Register 0 (USR0)
Figure 18.3-3 shows the bit configuration of the serial status register 0 (USR0).
Figure 18.3-3 Serial Status Register 0 (USR0)
Address: 000021H
Read/write→
Initial value→
15
14
RDRF ORFE
(R)
(R)
(0)
(0)
13
PE
(R)
(0)
12
TDRE
(R)
(1)
11
RIE
(R/W)
(0)
10
TIE
(R/W)
(0)
9
RBF
(R)
(0)
8
TBF
(R)
(0)
←Bit No.
USR0
[bit15] RDRF (Receiver data register full)
This flag indicates the state of the UIDR0 (serial input data register). The flag is set when the
receive data is loaded into UIDR0. Reading UIDR0 or writing "0" to RFC in the UMC0 register
clears the flag. If RIE is active, a receive interrupt request is generated when RDRF is set.
0: No data in UIDR0
1: Data present in UIDR0
[bit14] ORFE (Over-run/framing error)
The flag is set when an overrun or framing error occurs in receiving. Writing "0" to RFC in the
UMC0 register clears the flag. When this flag is set, the data in UIDR0 is invalid and the load
from the receive shifter to UIDR0 is not performed. If RIE is active, a receive interrupt request
is generated when ORFE is set.
0: No error
1: Error
Table 18.3-2 lists the UIDR0 states after receive completion by RDRF or ORFE.
Table 18.3-2 UIDR0 State after Receive Completion
RDRF
ORFE
UIDR0 Data State
0
0
Empty
0
1
Framing error
1
0
Valid data
1
1
Overrun error
The data in UIDR0 is invalid if an overrun or framing error has occurred. Next data can be
received after clearing the flag(s).
275
CHAPTER 18 UART0
[bit13] PE (Parity error)
The flag is set when a receive parity error occurs. Writing "0" to RFC in the UMC0 register
clears the flag. When this flag is set, the data in UIDR0 is invalid and the load from the receive
shifter to UIDR0 is not performed. If RIE is active, a receive interrupt request is generated
when PE is set.
0: No parity error
1: Parity error
[bit12] TDRE (Transmitter data register empty)
This flag indicates the state of the UODR0 (serial output data register). Writing transmit data to
the UODR0 register clears the flag. The flag is set when the data is loaded to the transmit
shifter and the transmission is started. If TIE is active, a receive interrupt request is generated
when TDRE is set.
0: Data present in UODR0
1: No data in UODR0
[bit11] RIE (Receiver interrupt enable)
Enables receive interrupt requests.
0: Disable interrupts.
1: Enable interrupts.
[bit10] TIE (Transmitter interrupt enable)
Enables transmit interrupt requests. A transmit interrupt is generated immediately if transmit
interrupts are enabled when TDRE is "1".
0: Disable interrupts.
1: Enable interrupts.
[bit9] RBF (Receiver busy flag)
This flag indicates that UART0 is receiving input data. The flag is set when the start bit is
detected and cleared when the stop bit is detected.
0: Receiver is idle.
1: Receiver is busy.
[bit8] TBF (Transmitter busy flag)
This flag indicates that UART0 is transmitting input data. The flag is set when transmit data is
written to the UODR0 register and cleared when transmission completes.
0: Transmitter is idle.
1: Transmitter is busy.
276
CHAPTER 18 UART0
18.3.3 Serial Input Data Register 0 (UIDR0) and Serial Output Data
Register 0 (UODR0)
UIDR0 (serial input data register 0) is the register to input (receive) the serial data.
UODR0 (serial output data register 0) is the register to output (transmit) the serial data.
■ Serial Input Data Register 0 (UIDR0) and Serial Output Data Register 0 (UODR0)
Figure 18.3-4 shows the bit configuration of the serial input data register 0 (UIDR0) and the serial
output register 0 (UODR0).
Figure 18.3-4 Serial Input Data Register 0 (UIDR0) and Serial Output Data Register 0 (UODR0)
Address: 000022H
Read/write→
Initial value→
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
←Bit No.
UIDR0(read)
UODR0(write)
The most significant two bits (D7 and D6) are ignored if the data length is 6 bits and the most
significant bit (D7) is ignored if the data length is 7 bits. Write to UODR0 only when TDRE = 1 in
the USR0 register. Read UIDR0 only when RDRF = 1 in the USR0 register.
277
CHAPTER 18 UART0
18.3.4 Rate and Data Register 0 (URD0)
URD0 selects the data transfer speed (baud rate) for UART0. The register also holds the
most significant bit (bit8) of the data when the transmit data length is 9 bits. Set the
baud rate and parity when UART0 is halted.
■ Rate and Data Register 0 (URD0)
Figure 18.3-5 shows the bit configuration of the rate and data register 0 (URD0).
Figure 18.3-5 Rate and Data Register 0 (URD0)
Address: 000023H
Read/write→
Initial value→
15
BCH
(R/W)
(0)
14
RC3
(R/W)
(0)
13
RC2
(R/W)
(0)
12
RC1
(R/W)
(0)
11
RC0
(R/W)
(0)
10
BCH0
(R/W)
(0)
9
P
(R/W)
(0)
8
D8
(R/W)
(X)
←Bit No.
URD0
[bit15, bit10] BCH, BCH0 (Baud rate clock change)
Specifies the machine cycles for the baud rate clock (see Table 18.4-1 for details).
Table 18.3-3 Setting Example of Machine Cycle
BCH
BCH0
Divider ratio
Setting Example for Each Machine Cycle
0
0
-
Prohibited setting
0
1
Divide by 4
For a 16 MHz machine cycle: 16/4 = 4 MHz
1
0
Divide by 3
For a 12 MHz machine cycle: 12/3 = 4 MHz
1
1
Divide by 5
For a 10 MHz machine cycle: 10/5 = 2 MHz
Note:
Do not set BCH and BCH0 to "00B".
278
CHAPTER 18 UART0
[bit14 to bit11] RC3, RC2, RC1, RC0 (Rate control)
Selects the clock input for the UART0 port (see Table 18.4-1 for details).
Table 18.3-4 Clock Input Selection
RC3 to RC0
"0000B" to "1011B"
Clock Input
Dedicated baud rate generator
"1101B"
16-bit Reload Timer 0
"1111B"
External clock
Note:
Do not set the rate control bits to "1100B" "1110B".
[bit9] P (Parity)
Sets even or odd parity when parity is active (PEN = 1).
0: Even parity
1: Odd parity
[bit8] D8
Holds the bit8 of the transfer data in mode 2 or 3 (9-bit data length) and no parity. Treated as
bit8 of the UIDR0 register for reading. Treated as bit8 of the UODR0 register for writing. The
bit has no meaning in the other modes. Write to D8 only when TDRE = 1 in the USR0 register.
279
CHAPTER 18 UART0
18.4 UART0 Operation
Table 18.4-1 lists the operating modes for UART0. Set the value to UMC0 register to
switch between modes.
■ UART0 Operation Modes
Table 18.4-1 UART0 Operating Modes
Mode
Parity
Data Length
On
6
Off
7
On
7
Off
8
Off
8+1
On
8
Off
9
Clock Mode
Length of Stop Bits*
0
1
2
CLK asynchronous or CLK
synchronous
1 bit or 2 bits
3
*: The number of stop bits can only be set for transmission. The number of receive stop bits is always set to
"1". Do not set modes other than those listed above. UART0 does not operate if an invalid mode is set.
Note:
UART0 uses start-stop clock synchronous transfer. Therefore, a start and stop bit are added to the
data even in clock synchronous transfer.
280
CHAPTER 18 UART0
18.5 Baud Rate
When the dedicated baud rate generator is used, the following two types of baud rates
are available:
• CLK synchronous baud rate
• CLK asynchronous baud rate
■ CLK Synchronous Baud Rate
The five URD0 register bits: BCH, BCH0, RC3, RC2 and RC1 select the baud rate for CLK
synchronous transfer.
First select the machine clock divider ratio using BCH and BCH0.
BCH BCH0
0
1
=>
Divide by 4 [For example, at 16 MHz: 16/4 = 4 MHz]
1
0
=>
Divide by 3 [For example, at 12 MHz: 12/3 = 4 MHz]
1
1
=>
Divide by 5 [For example, at 10 MHz: 10/5 = 2 MHz]
Then, set the division ratio for the clock selected above in RC3, RC2, and RC1. The following
three settings are available for CLK synchronous transfer. Other settings are prohibited.
RC3
RC2
RC1
0
1
0
=>
Divide by 2 [For example, at 4 MHz: 4/2 = 2.0 Mbps]
0
1
1
=>
Divide by 4 [For example, at 4 MHz: 4/4 = 1.0 Mbps]
1
0
0
=>
Divide by 8 [For example, at 4 MHz: 4/8 = 0.5 Mbps]
(At 2 MHz, the speed becomes half the above examples.)
■ CLK Asynchronous Baud Rate
The six URD register bits, BCH, BCH0, RC3, RC2, RC1 and RC0 select the baud rate for CLK
asynchronous transfer.
First select the machine clock divider ratio using BCH and BCH0.
BCH BCH0
0
1
=>
Divide by 4 [For example, at 16 MHz: 16/4 = 4 MHz]
1
0
=>
Divide by 3 [For example, at 12 MHz: 12/3 = 4 MHz]
1
1
=>
Divide by 5 [For example, at 10 MHz: 10/5 = 2 MHz]
Then, set the asynchronous transfer clock division ratio for the clock selected above in RC3,
RC2, RC1, and RC0. The following settings are available for CLK synchronous transfer.
281
CHAPTER 18 UART0
0
0
0
⇒ Divide by 8 × 1
0
1
0
⇒ Divide by 8 × 2
0
1
1
⇒ Divide by 8 × 4
1
0
0
⇒ Divide by 8 × 8
0
0
1
⇒ Not divide
1
0
1
⇒ Divide by 8
⎧
⎪
⎪
⎨
⎪
⎩
⎧
⎪
⎨
⎪
⎪
⎩
RC0
×
×
⎧
⎪
⎨ 0 ⇒ Divide by 12
⎪ 1 ⇒ Divide by 13
⎪
⎩
⎧
⎪
⎪
⎨
⎪
⎩
RC3 RC2 RC1
0
⇒ Prohibited setting
1
⇒ Divide by 8
The above 12 baud rates can be selected. The following formula shows how to calculate the CLK
synchronous baud rate.
Baud rate =
φ/4
2m-1
bps (machine cycle = 16 MHz)
Baud rate =
φ/3
2m-1
bps (machine cycle = 12 MHz)
Baud rate =
φ/5
2m-1
bps (machine cycle = 10 MHz)
In this formula, φ is a machine cycle and "m" is in decimal notation for RC3 to RC1.
Note:
The above formula for m=0 or m=1 cannot be calculated.
Data transfer is possible if the CLK asynchronous baud rate is in the range -1% to +1%. The baud
rate is the CLK asynchronous baud rate divided by 8 x 13, 8 x 12, or 8.
Table 18.5-1 shows examples for 16 MHz, 12 MHz, and 10 MHz machine cycles. However, do not
use the settings marked as "-" in the table.
282
CHAPTER 18 UART0
Table 18.5-1 Baud Rate
CLK asynchronous (µs/Baud)
RC
3
RC
2
RC
1
RC
0
0
0
0
0
0
0
CLK synchronous (µs/Baud)
CLK
10 MHz
asynchro16 MHz
12 MHz
10 MHz
nous
divider
BCH/
BCH/
BCH/
BCH/
ratio
BCH0=11
BCH0=01 BCH0=10 BCH0=11
16 MHz
12 MHz
BCH/
BCH0=01
BCH/
BCH0=10
0
-
-
48/ 20833
8 × 12
-
-
-
0
1
26/ 38460
26/ 38460
52/ 19230
8 × 13
-
-
-
0
1
0
-
-
-
8
-
-
-
0
0
1
1
2/500000
2/500000
4/250000
8
-
-
-
0
1
0
0
48/ 20833
48/ 20833
96/10417
8 × 12
-
-
-
0
1
0
1
52/ 19230
52/ 19230
104/ 9615
8 × 13
0.5 / 2M
0.5 / 2M
1 / 1M
0
1
1
0
96/10417
96/10417
192/ 5208
8 × 12
-
-
-
0
1
1
01
104/ 9615
104/ 9615
208/ 4808
8 × 13
1 / 1M
1 / 1M
2 / 500K
1
0
0
0
192/ 5208
192/ 5208
-
8 × 12
-
-
-
1
0
0
1
208/ 4808
208/ 4808
416/ 2404
8 × 13
2 / 500K
2 / 500K
4 / 250K
1
0
1
0
-
-
-
8
-
-
-
1
0
1
1
16/ 62500
16/ 62500
32/ 31250
8
-
-
-
283
CHAPTER 18 UART0
18.6 Internal and External Clock
Setting RC3 to RC0 to "1101B" selects the clock signal from the 16-bit Reload Timer.
Setting RC3 to RC0 to "1111B" selects the external clock.
■ Internal and External Clock
The CLK asynchronous baud rate is the CLK synchronous baud rate divided by 8. Also, data
transfer is possible if the CLK asynchronous baud rate is in the range -1% to +1% of the selected
baud rate. Table 18.6-1 lists the baud rates when the internal timer is selected as the clock. The
values in this table are calculated for a machine cycle of 7.3728 MHz. However, do not use the
settings marked as "-" in the table.
Baud rate=
φ/X
8 × 2 (n+1)
bps
⎛ φ: Machine cycle
⎜
⎜ X: Divider ratio for the count clock source for
⎜
the internal clock
⎜
⎝ n: Reload value (decimal)
⎞
⎟
⎟
⎟
⎟
⎠
Table 18.6-1 Baud Rate and Reload Value
Reload Value
Reload value
X = 21
(divide machine clock by 2)
X = 23
(divide machine clock by 8)
76800
2
-
38400
5
-
19200
11
2
9600
23
5
4800
47
11
2400
95
23
1200
191
47
600
383
95
300
767
191
Baud Rate
The values in the table are the reload values (decimal) for reload count operation of the 16-bit
Reload Timer.
284
CHAPTER 18 UART0
18.7 Transfer Data Format
UART0 only handles NRZ (non-return-to-zero) type data. Figure 18.7-1 shows the
relationship between the transmit/receive clock and the data for CLK synchronous
mode.
■ Transfer Data Format
Figure 18.7-1 Transfer Data Format
SCK0
SIN0, SOT0
0
1
Start LSB
0
1
1
0
0
1
0
1
1
⎫
MSB Stop
⎬ Depends
D8 Stop ⎭ on the mode.
The transferred data is "01001101B" (mode 1) or "101001101B" (mode 3).
As shown in Figure 18.7-1, the transfer data always starts with the start bit ("L" level data), the
specified number of data bits are transmitted with the LSB first, then transmission ends with the
stop bit ("H" level data). Always input a clock if external clock operation is selected.
When an internal clock (the dedicated baud rate generator or 16-bit Reload Timer) is selected,
the clock is output continuously. When using CLK synchronous transfer, do not start data transfer
until the selected baud rate clock has stabilized (for two baud rate clock cycles).
When using CLK asynchronous transfer, set the SCKE bit in the UMC0 register to "0" to disable
clock output. The transfer data format of SIN0 and SOT0 is the same as shown in Figure 18.7-1.
285
CHAPTER 18 UART0
18.8 Parity Bit
The P (Parity) bit in the URD0 register specifies whether to use even or odd parity when
parity is enabled. The PEN bit in the UMC0 register enables parity.
■ Parity Bit
Inputting the data shown in Figure 18.8-1 to SIN0 when even parity is set causes a receive parity
error. Figure 18.8-1 also shows the data transmitted when sending "001101B" with even parity
and odd parity.
Figure 18.8-1 Serial Data with Parity Enabled
SIN0
(Receive parity error occurs P = 0)
0
Start
1
LSB
0
1
1
0
0
MSB
0
1
Stop
(Parity)
SOT0
(Even parity transmission P = 0)
0
Start
1
LSB
0
1
1
0
0
MSB
1
1
Stop
(Parity)
SOT0
(Odd parity transmission P = 1)
0
Start
1
LSB
0
1
1
0
0
MSB
0
(Parity)
286
1
Stop
CHAPTER 18 UART0
18.9 Interrupt Generation and Flag Set Timings
UART0 has two interrupt causes and six flags. The two interrupt causes are the receive
and transmit interrupts. The six flags are RDRF, ORFE, PE, TDRE, RBF, and TBF. For
reception, the RDRF, ORFE, and PE flags request an interrupt. For transmission, the
TDRE flag requests an interrupt.
■ Set Timings of the Six Flags
❍ RDRF flag
The RDRF flag is set when receive data is loaded into the UIDR0 register. The flag is cleared by
writing "0" to RFC in the UMC0 register or by reading the UIDR0 register.
❍ ORFE flag
The ORFE flag is an overrun or framing error flag. The flag is set when a receive error occurs and
is cleared by writing "0" to RFC in the UMC0 register.
❍ PE flag
The PE flag is a reception parity error flag. The flag is set when a receive parity error occurs and
is cleared by writing "0" to RFC in the UMC0 register. Note that the parity detect function is invalid
in mode 2.
❍ TDRE flag
The TDRE flag is set when the UODR0 register becomes empty and is available for writing. The
flag is cleared by writing to the UODR0 register. The above four flags (RDRF, ORFE, PE, and
TDRE) trigger transmit or receive interrupts.
❍ RBF and TBF flags
The RBF and TBF flags indicate that reception or transmission is in progress. The RBF flag
becomes active during reception, and the TBF flag becomes active during transmission.
287
CHAPTER 18 UART0
18.9.1 Flag Set Timings for a Receive Operation (in Mode 0, 1, or 3)
The RDRF, ORFE, and PE flags are set and an interrupt request to the CPU generated
when the final stop bit is detected indicating the end of reception transfer. The data in
UIDR0 is invalid when either the ORFE or PE bit is active.
■ Flag Set Timings for a Receive Operation (in Mode 0, 1, or 3)
Figure 18.9-1, Figure 18.9-2, and Figure 18.9-3 show the set timings of the RDRF, ORFE, and
PE flags respectively.
Figure 18.9-1 RDRF Set Timing (Mode 0, 1, or 3)
Data
(Stop)
Stop
RDRF
Receive interrupt
Figure 18.9-2 ORFE Set Timing (Mode 0, 1, or 3)
Stop
Data
Stop
Data
RDRF = 1
RDRF = 0
ORFE
ORFE
Receive interrupt
Receive interrupt
(Overrun error)
(Framing error)
Figure 18.9-3 PE Set Timing (Mode 0, 1, or 3)
Data
PE
Receive interrupt
288
Stop
(Stop)
CHAPTER 18 UART0
18.9.2 Flag Set Timings for a Receive Operation (in Mode 2)
The RDRF flag is set when the final stop bit is detected and reception transfer ends with
the last data bit (D8) having the value "1".
The ORFE flag is set when the final stop bit is detected, irrespective of the value of the
last data bit (D8). The data in UIDR0 is invalid when the ORFE bit is active.
The interrupt request to the CPU is generated when either of the flags are set (see
Section "18.10 UART0 Application Example" for details on using mode 2).
■ Flag Set Timings for a Receive Operation (in Mode 2)
Figure 18.9-4 RDRF Set Timing (Mode 2)
Data
D6
D7
D8
(Stop)
Stop
RDRF
Receive interrupt
Figure 18.9-5 ORFE Set Timing (Mode 2)
Data
D7
D8
Stop
Data
RDRF = 1
RDRF = 0
ORFE
ORFE
Receive interrupt
Receive interrupt
(Overrun error)
D7
D8
Stop
(Framing error)
289
CHAPTER 18 UART0
18.9.3 Flag Set Timings for a Transmit Operation
TDRE is set and an interrupt request to the CPU is generated when the data written in
UODR0 register is transferred to the internal shift register at the transfer operation and
the next data can be written to UODR0.
■ Flag Set Timings for a Transmit Operation
Figure 18.9-6 TDRE Set Timing (Mode 0)
UODR0 write
TDRE
Interrupt request to the CPU
Transmit interrupt
SOT0 output
ST D0
ST: Start bit
290
D1 D2
D3
D4 D5
D0 to D7: Data bits
D6
D7 SP SP
SP: Stop bit
ST D0
D1 D2 D3
CHAPTER 18 UART0
18.9.4 Status Flag During Transmit and Receive Operation
RBF is set when the start bit is detected and cleared when a stop bit is detected. The
receive data in UIDR0 at the RBF clear timing is not yet valid. The data in UIDR0
becomes valid at the RDRF set timing.
■ Status Flag During Transmit and Receive Operation
Figure 18.9-7 shows the relationship between the RBF and receive interrupt flag timing.
Figure 18.9-7 RBF Set Timing (Mode 0)
SIN0 input
ST D0 D1
D2 D3 D4
D5 D6 D7
SP
RBF
RDRF, PE, ORFE
Writing the transmission data to UODR0 sets TBF. TBF is cleared when transmission completes.
Figure 18.9-8 TBF Set Timing (Mode 0)
UODR write
SOT0 output
ST D0 D1
D2 D3 D4
D5 D6 D7
SP
SP
TBF
Note:
Receive operation starts after releasing a reset unless the SIN0 input pin is fixed at "1". Therefore,
before setting the mode, write "0" to RFC in the UMC0 register to clear any receive flags that have
been set.
Set the communication mode when the RBF and TBF flags in the USR0 register are "0". The data
transmitted and received during mode setting cannot be guaranteed.
■ EI2OS (Extended Intelligent I/O Service)
See Section "3.6 Extended Intelligent I/O Service (EI2OS)" for details about the extended
intelligent I/O service (EI2OS).
291
CHAPTER 18 UART0
18.10
UART0 Application Example
Mode 2 is used when a number of slave CPUs are connected to a host CPU (see Figure
18.10-1.)
■ Application Example of UART0
As shown in Figure 18.10-1, communication starts with the host CPU transmitting address data.
The ninth bit (D8) of the address data is set to "1". The address selects the slave CPU with which
communication will be established. The selected slave CPU communicates with the host CPU
using a protocol determined by the user. In normal data, D8 is set to "0". Unselected slave CPUs
wait in standby until the next communication session starts.
Figure 18.10-2 shows a flowchart of operation in this mode.
Because the parity check function is not available in this mode, set the PEN bit in the UMC0
register to "0".
Figure 18.10-1 Example System Configuration Using Mode 2
SOT0
SIN0
Host CPU
292
SOT0 SIN0
SOT0 SIN0
Slave CPU #0
Slave CPU #1
CHAPTER 18 UART0
Figure 18.10-2 Communication Flowchart for Mode 2 Operation
(Host CPU)(Slave CPU)
Start
Start
Set the transfer mode to "3"
Set the transfer mode to "2"
Set the slave CPU selection
in D0 to D7. Set D8 to "1".
Transfer a byte.
Receive a byte
No
Selected?
Set D8 to "0" and perform
communications
End
Yes
Set the transfer mode to "3"
and enable SOT0 output
Perform communications
with the master CPU
Use the status flag to
confirm transfer completion,
then set the transfer mode to
"2" and disable SOT0 output
293
CHAPTER 18 UART0
294
CHAPTER 19
UART1 (SCI)
This chapter explains the UART1 (SCI) functions and operation.
19.1 Features of UART1
19.2 UART1 Block Diagram
19.3 UART1 Registers
19.4 UART1 Operating Modes and Clock Selection
19.5 UART1 Flags and Interrupt Sources
19.6 UART1 Interrupts and Flag Set Timing
19.7 Negative Clock Operation
19.8 UART1 Sample Applications and Precautionary Information
295
CHAPTER 19 UART1 (SCI)
19.1 Features of UART1
The UART1 is a serial I/O port used for asynchronous (start-stop synchronized)
communication or for CLK-synchronized communication.
■ Features of UART1
UART provides the following features.
•
Full-duplex double buffer
•
Asynchronous (start-stop synchronized) and CLK-synchronous communication capability
•
Multi-processor mode support
•
On-chip dedicated baud rate generator
At internal machine clock of 6, 8, 10, 12, 16MHz.
Asynchronous: 62500/38460/31250/19230/9615/4808/2404/1202 bps
CLK synchronous: 1M/500K/250K/125K/62.5 Kbps
296
•
Automatic baud rate setting from external clock input or internal timer
•
Error detection function (parity, framing, overrun)
•
Transfer signal is NRZ sign
•
Intelligent I/O service support
CHAPTER 19 UART1 (SCI)
19.2 UART1 Block Diagram
Figure 19.2-1 shows the UART1 block diagram.
■ UART1 Block Diagram
Figure 19.2-1 UART1 Block Diagram
Control signals
Receive interrupt
(to CPU)
Dedicated baud
rate generator
16-bit reload timer 0
SCK1
Transmit clock
Clock
selector
circuit
Transmit
interrupt
(to CPU)
Receive clock
External clock
SIN1
Receive control circuit
Transmit control circuit
Start bit detect circuit
Transmit start circuit
Receive bit counter
Transmit bit counter
Receive parity counter
Transmit parity counter
SOT1
Receive status decision circuit
Receive shifter
Transmit shifter
Receive
complete
Transmit
Start
SIDR1
SODR1
Receive error indication
signal for EI2OS (to CPU)
Internal data bus
SMR1
register
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
SCR1
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR1
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
Control signal
297
CHAPTER 19 UART1 (SCI)
19.3 UART1 Registers
Figure 19.3-2 lists the UART1 registers.
■ UART1 Registers
Figure 19.3-1 UART1 Register Configuration
15
8 7
0
SCR1
SMR1
(R/W)
SSR1
SIDR1(R)/SODR1(W)
(R/W)
⎯
8 bit
CDCR
8 bit
(R/W)
Figure 19.3-2 UART1 Registers
0
SOE
(R/W)
(0)
←Bit No.
(R/W)
(0)
1
SCKE
(R/W)
(0)
11
A/D
(R/W)
(0)
10
REC
(W)
(1)
9
RXE
(R/W)
(0)
8
TXE
(R/W)
(0)
←Bit No.
3
D3
(R/W)
(X)
2
D2
(R/W)
(X)
1
D1
(R/W)
(X)
0
D0
(R/W)
(X)
←Bit No.
10
⎯
(-)
(-)
9
RIE
(R/W)
(0)
8
TIE
(R/W)
(0)
←Bit No.
10
DIV2
(R/W)
(1)
9
DIV1
(R/W)
(1)
8
DIV0
(R/W)
(1)
←Bit No.
Serial mode register 1
Address: 000024H
Read/write→
Initial value→
7
MD1
(R/W)
(0)
6
MD0
(R/W)
(0)
5
CS2
(R/W)
(0)
4
CS1
(R/W)
(0)
3
CS0
(R/W)
(0)
Serial control register 1
Address: 000025H
Read/write→
Initial value→
15
PEN
(R/W)
(0)
14
P
(R/W)
(0)
13
SBL
(R/W)
(0)
12
CL
(R/W)
(0)
7
D7
(R/W)
(X)
6
D6
(R/W)
(X)
5
D5
(R/W)
(X)
4
D4
(R/W)
(X)
15
PE
(R)
(0)
14
ORE
(R)
(0)
13
FRE
(R)
(0)
2
Reserved
SMR1
SCR1
Serial input data register 1
Serial output data register 1
Address: 000026H
Read/write→
Initial value→
Serial status register 1
Address: 000027H
Read/write→
Initial value→
UART1 communication prescaler control register
15
14
13
⎯
⎯
⎯
Address: 000028H
(R/W)
(-)
(-)
Read/write→
Initial value→
(0)
(-)
(-)
298
12
11
RDRF TDRE
(R)
(R)
(0)
(1)
12
⎯
(-)
(-)
11
DIV3
(R/W)
(1)
SIDR1(read)
SODR1(write)
SSR1
CDCR
CHAPTER 19 UART1 (SCI)
19.3.1 Serial Mode Register 1 (SMR1)
The serial mode register 1 (SMR1) sets the operating mode of the UART1. Operating
mode settings should be entered when the unit is not in operation. Do not write to this
register during operation.
■ Serial Mode Register 1 (SMR1)
Figure 19.3-3 shows the bit configuration of the serial mode register 1(SMR1).
Figure 19.3-3 Serial Mode Register 1(SMR1)
Address: 000024H
Read/write→
Initial value→
7
MD1
(R/W)
(0)
6
MD0
(R/W)
(0)
5
CS2
(R/W)
(0)
4
CS1
(R/W)
(0)
3
CS0
(R/W)
(0)
2
Reserved
(R/W)
(0)
1
SCKE
(R/W)
(0)
0
SOE
(R/W)
(0)
←Bit No.
SMR1
[bit7, bit6] MD1, MD0 (MoDe select)
These bits select the UART1 operation mode, according to the settings listed in Table 19.3-1.
Table 19.3-1 Operating Mode Selections
Mode
MD1
MD0
Operating mode
0
0
0
Asynchronous (start-stop synchronized) normal mode
1
0
1
Asynchronous (start-stop synchronized) multi-processor
mode
2
1
0
CLK synchronous mode
—
1
1
Prohibited
Note:
CLK-asynchronous (multi-processor) mode of mode 1, is used when one host CPU is connected to
multiple slave CPUs. This UART1 resource is not able to determine the data format of reception
data, and therefore in multi-processor mode supports only the master processor.
Also, in this configuration the receive parity check function cannot be used, and therefore the PEN
bit in the SCR1 register should be set to "0".
[bit5 to bit3] CS2, CS1, CS0 (Clock Select)
These bits select the baud rate clock source. The baud rate is determined at the same time as
selection of the dedicated baud rate generator. Table 19.3-2 shows the clock input selection
settings.
299
CHAPTER 19 UART1 (SCI)
Table 19.3-2 Clock Input Selection Settings
CS2 to CS0
Clock input
000B to 100B
Dedicated baud rate generator
101B
Reserved
110B
Internal timer*
111B
External clock
*: When the internal timer is selected, the MB90540/545 series selects 16-bit reload timer 0
output.
[bit2] Reserved
Always write "0" to this bit.
[bit1] SCKE (SCLK Enable)
For communication in CLK synchronous mode (mode 2), this bit determines whether the
SCK1 pin is used as a clock input pin or a clock output pin.
In CLK asynchronous modes or external clock mode, this bit should be set to "0".
0: SCK1 pin functions as clock input pin
1: SCK1 pin functions as clock output pin
Note:
When the pin functions as a clock input pin, an external clock source must be selected.
[bit0] SOE (Serial Output Enable)
This bit determines whether external pins (SOT1) that also can be used as general-purpose I/
O port pins will function as serial output pins or as I/O port pins.
0: General-purpose I/O port pin function
1: Serial data output pin (SOT1) function
300
CHAPTER 19 UART1 (SCI)
19.3.2 Serial Control Register 1 (SCR1)
The serial control register 1 (SCR1) register controls the transfer protocol used for
serial communication.
■ Serial Control Register 1 (SCR1)
Figure 19.3-4 shows the bit configuration of the serial control register 1 (SCR1).
Figure 19.3-4 Serial Control Register 1 (SCR1)
Address: 000025H
Read/write→
Initial value→
15
PEN
(R/W)
(0)
14
P
(R/W)
(0)
13
SBL
(R/W)
(0)
12
CL
(R/W)
(0)
11
A/D
(R/W)
(0)
10
REC
(W)
(1)
9
RXE
(R/W)
(0)
8
TXE
(R/W)
(0)
←Bit No.
SCR1
[bit15] PEN (Parity ENable)
This bit determines whether parity bits are attached to data in serial communication.
0: No parity
1: Parity is attached
Note:
Parity bit attachment is available only in asynchronous (start-stop synchronized) communications in
normal mode (mode 0). In multi-processor mode (mode 1) and CLK-synchronous communication
(mode 2), no parity bits may be attached.
[bit14] P (Parity)
This bit selects even or odd parity for data communications in which a parity bit is used.
0: Even parity
1: Odd parity
[bit13] SBL (Stop Bit Length)
This bit sets the length of the stop bit that marks the frame end in asynchronous (start-stop
synchronized) communication.
0: 1 stop bit
1: 2 stop bits
[bit12] CL (Character Length)
This bit sets the data length of one frame.
0: 7-bit data
1: 8-bit data
301
CHAPTER 19 UART1 (SCI)
Note:
7-bit data handling is available only in asynchronous (start-stop synchronized) communications in
normal mode (mode 0). In multi-processor mode (mode 1) and CLK-synchronous communication
(mode 2), 8-bit data should be used.
[bit11] A/D (Address/Data)
This bit determines the data format of transmit frames in asynchronous (start-stop
synchronized) communication in multi-processor mode (mode 1).
0: Data frame
1: Address frame
[bit10] REC (Receiver Error Clear)
Writing "0" to this bit clears the error flags (PE, ORE, FRE) in the SSR1 register.
A write value of "1" is not valid, and the read value is always "1".
[bit9] RXE (Receiver Enable)
This bit controls UART1 receiver operations.
0: Receiver operation prohibited
1: Receiver operation enabled
Note:
If receiver operation is prohibited while reception is in progress (while data is present in the receive
shift register), the receiver will not stop operating until reception of the current frame is completed,
and the data has been stored in the receive data buffer SIDR1 register.
[bit8] TXE (Transmit Enable)
This bit controls UART1 transmit operation.
0: Transmit operation prohibited
1: Transmit operation enabled
Note:
If transmit operation is prohibited while transmission is in progress (while data is being output from
the transmit register), the transmitter will not stop operating until there is no more data remaining in
the transmit data buffer SODR1 register.
302
CHAPTER 19 UART1 (SCI)
19.3.3 Serial Input Data Register 1 (SIDR1) / Serial Output Data
Register 1 (SODR1)
Serial Input Data Register 1 (SIDR1) /Serial Output Data Register 1 (SODR1) are data
buffer registers for receive and transmit.
■ Serial Input Data Register 1 (SIDR1) / Serial Output Data Register 1 (SODR1)
Figure 19.3-5 shows the bit configuration of the serial input data register 1 (SIDR1) and the serial
output data register 1 (SODR1).
Figure 19.3-5 Serial Input Data Register 1 (SIDR1)/Serial Output Data Register 1 (SODR1)
Address: 000026H
Read/write→
Initial value→
7
D7
(R/W)
(X)
6
D6
(R/W)
(X)
5
D5
(R/W)
(X)
4
D4
(R/W)
(X)
3
D3
(R/W)
(X)
2
D2
(R/W)
(X)
1
D1
(R/W)
(X)
0
D0
(R/W)
(X)
←Bit No.
SIDR1(read)
SODR1(write)
The serial input data register 1 (SIDR1) functions as a data buffer register for receiving serial
data. The serial output data register 1 (SODR1) functions as a data buffer register for transmitting
serial data. When using 7-bit data length, the top 1-bit (D7) contains invalid data. Be sure the
TDRE bit in the SSR1 register is set to "1" before writing to the SODR1 register.
Note:
Writing to these addresses refers to writing to the SODR1 register, and reading refers to reading
from the SIDR1 register.
303
CHAPTER 19 UART1 (SCI)
19.3.4 Serial Status Register 1 (SSR1)
The serial status register 1 (SSR1) is composed of flags that indicate the operating
status of the UART1.
■ Serial Status Register 1 (SSR1)
Figure 19.3-6 shows the bit configuration of the serial status register 1 (SSR1).
Figure 19.3-6 Serial Status Register 1 (SSR1)
Address: 000027H
Read/write→
Initial value→
15
PE
(R)
(0)
14
ORE
(R)
(0)
13
FRE
(R)
(0)
12
11
RDRF TDRE
(R)
(R)
(0)
(1)
10
⎯
(-)
(-)
9
RIE
(R/W)
(0)
8
TIE
(R/W)
(0)
←Bit No.
SSR1
[bit15] PE (Parity Error)
This interrupt request flag is set when a parity error occurs during receive. Once set, this flag
is cleared by writing "0" to the REC bit (bit10) in the SCR1 register.
When this bit is set, data in the SIDR1 register is invalid.
0: No parity error
1: Parity error occurred
[bit14] ORE (Over Run Error)
This interrupt request flag is set when an overrun error occurs during receive. Once set, this
flag is cleared by writing ‘0" to the REC bit (bit10) in the SCR1 register.
When this bit is set, data in the SIDR1 register is invalid.
0: No overrun error
1: Overrun error occurred
[bit13] FRE (Framing Error)
This interrupt request flag is set when a framing error occurs during receive. Once set, this
flag is cleared by writing ‘0" to the REC bit (bit10) in the SCR1 register.
When this bit is set, data in the SIDR1 register is invalid.
0: No framing error
1: Framing error occurred
[bit12] RDRF (Receiver Data Register Full)
This interrupt request flag is set to indicate that reception data is present in the SIDR1
register.
This flag is set when receive data is loaded into the SIDR1 register, and is automatically
cleared when the data is read from the SIDR1 register.
0: No receive data
1: Receive data present
304
CHAPTER 19 UART1 (SCI)
[bit11] TDRE (Transmit Data Register Empty)
This interrupt request flag is set to indicate that transmission data can be written to the
SODR1 register.
This flag is cleared when transmission data is written to the SODR1 register. It is then reset
when the written data starts loading into the transmit shifter and transferring to indicate that
the next transmission data can be written to the SODR1 register.
0: Prohibits writing of send data
1: Enables writing of send data
[bit9] RIE (Receiver Interrupt Enable)
This bit controls receiver interrupts.
0: Interrupt prohibited
1: Interrupt enabled
Note:
Receiver interrupt sources include PE, ORE and FRE errors, as well as normal receive as indicated
by the RDRF flag.
[bit8] TIE (Transmit Interrupt Enable)
This bit controls transmit interrupts.
0: Interrupt prohibited
1: Interrupt enabled
Note:
Transmit interrupt sources include transmission requests indicated by the TDRE flag.
305
CHAPTER 19 UART1 (SCI)
19.3.5 UART1 Communication Prescaler Control Register (CDCR)
The UART1 communication prescaler control register (CDCR) controls the machine
clock frequency divider. The UART1 operating clock signal can be generated by
dividing the machine clock signal pulse. The prescaler is designed to enable constant
baud rates from a variety of machine clock speeds.
■ UART1 Communication Prescaler Control Register (CDCR)
Figure 19.3-7 shows the bit configuration of the UART1 communication prescaler control register
(CDCR).
Figure 19.3-7 UART1 Communication Prescaler Control Register (CDCR)
Address: 000028H
Read/write→
Initial value→
15
⎯
(R/W)
(0)
14
⎯
(-)
(-)
13
⎯
(-)
(-)
12
⎯
(-)
(-)
11
DIV3
(R/W)
(1)
10
DIV2
(R/W)
(1)
9
DIV1
(R/W)
(1)
8
DIV0
(R/W)
(1)
←Bit No.
CDCR
[bit7] MD (Machine clock divide MoDe select)
This bit enables the communication prescaler operation.
0: Communication prescaler stopped
1: Communication prescaler operating
[bit3, bit2, bit1, bit0] DIV3 to DIV0 (DIVide 3 to DIVide 0)
These bits determine the division ratio of the machine clock frequency as shown in Table
19.3-3.
Table 19.3-3 Machine Clock Division Ratios
DIV3
DIV2
DIV1
DIV0
Division ratio *
1
1
1
0
Divide by 2
1
1
0
1
Divide by 3
1
1
0
0
Divide by 4
1
0
1
1
Divide by 5
1
0
1
0
Divide by 6
1
0
0
1
Divide by 7
1
0
0
0
Divide by 8
*: After changing the division ratio, allow an interval of 2 cycles for the clock frequency to
stabilize before starting communication.
306
CHAPTER 19 UART1 (SCI)
19.4 UART1 Operating Modes and Clock Selection
The UART1 has two types of operating mode, asynchronous mode and CLKsynchronous mode. Changes of mode are controlled by setting values in the SMR1
register and SCR1 register.
■ UART1 Operating Modes
Table 19.4-1 shows the UART1 operating modes.
Table 19.4-1 UART1 Operating Modes
Mode
Parity bit
Data
length
Y/N
7
Y/N
8
0
Operating mode
Stop bit length*
Asynchronous (start-stop
synchronized) normal
mode
1-bit or 2-bit
1
N
8+1
Asynchronous (start-stop
synchronized) multiprocessor mode
2
N
8
CLK synchronous mode
N
*: In asynchronous (start-stop synchronized) normal mode, stop bit length can be set for transmit
operation only. For receive, the setting is always 1-bit length. The unit does not operate in
modes other than those shown, and only these settings should be used.
307
CHAPTER 19 UART1 (SCI)
■ UART1 Clock Selection
❍ Dedicated baud rate generator
When the dedicated baud rate generator is selected, the baud rate settings listed in Table 19.4-2
and Table 19.4-3 are available. Also, communication prescaler settings are shown in Table 19.44.
φ in the tables indicates the machine clock.
Table 19.4-2 Baud Rates (Asynchronous Communication)
CS2
CS1
CS0
φ/div=2MHz
φ/div=4MHz
φ/div=8MHz
Calculation formula
0
0
0
9615
19230
38460
(φ/div) / (8×13×2)
0
0
1
4808
9615
19230
(φ/div) / (8× 13×22)
0
1
0
2404
4808
9615
(φ/div) / (8×13×23)
0
1
1
1202
2404
4808
((φ/div) / (8×13×24)
1
0
0
31250
62500
-
(φ/div) / 26
Table 19.4-3 Baud Rates (CLK-synchronized Communication)
308
CS2
CS1
CS0
φ/div=2MHz
φ/div=4MHz
φ/div=8MHz
Calculation formula
0
0
0
1 MHz
-
-
(φ/div) / 2
0
0
1
500 kHz
1 MHz
-
(φ/div) / 22
0
1
0
250 kHz
500 kHz
1 MHz
(φ/div) / 23
0
1
1
125 kHz
250 kHz
500 kHz
(φ/div) / 24
1
0
0
62.5 kHz
125 kHz
250 kHz
(φ/div) / 25
CHAPTER 19 UART1 (SCI)
Table 19.4-4 Communication Prescaler Setting Value
Recommended machine
clock speed (φ)
div
DIV3
DIV2
DIV1
DIV0
4 MHz
4
1
1
0
0
6 MHz
6
1
0
1
0
8 MHz
8
1
0
0
0
6 MHz
3
1
1
0
1
8 MHz
4
1
1
0
0
10 MHz
5
1
0
1
1
12 MHz
6
1
0
1
0
14 MHz
7
1
0
0
1
16 MHz
8
1
0
0
0
8 MHz
2
1
1
1
0
12 MHz
3
1
1
0
1
16 MHz
4
1
1
0
0
16 MHz
2
1
1
1
0
φ/div
1 MHz
2 MHz
4 MHz
8 MHz
❍ Internal timer
When CS2 to CS0 are set to "110B" and the internal timer signal is selected, the reload timer 0 (at
16-bit operating) operates in reload mode. In this case, baud rates are determined as follows.
Asynchronous (start-stop synchronized): (φ / N) / (16 × 2 × (n + 1))
CLK synchronous:
(φ / N) / (2 × (n + 1))
N: timer count clock source
n: timer reload value
Table 19.4-5 shows the relation between baud rates and reload values (decimal values) at a
machine cycle speed of 7.3728MHz.
309
CHAPTER 19 UART1 (SCI)
Table 19.4-5 Baud Rates and Reload Values
Reload value
N=21
(machine clock division by 2)
N=23
(machine clock division by 8)
38400
2
—
19200
5
—
9600
11
2
4800
23
5
2400
47
11
1200
95
23
600
191
47
300
383
95
Baud rate
When selecting the internal timer (16-bit timer 0) as the baud rate clock source, note that the 16bit timer 0 output signal TOT0 has been already connected to the MB90540/545 controller
internally. Therefore, it is not necessary to make an external connection from the 16-bit timer 0
external output pins TOT0 to the UART1 external clock input pin SCK1. Also, this means that
unless used in some other fashion, the timer pins are available for use as I/O port pins.
❍ External clock
When CS2 to CS0 are set to "111B" the external clock source is selected and baud rates are
determined by the following formula, in which f represents the external clock frequency.
Asynchronous (start-stop synchronized) mode: f/16
CLK synchronous:
Note that f has a maximum value of 2 MHz.
310
f
CHAPTER 19 UART1 (SCI)
19.4.1 Asynchronous (Start-Stop Synchronized) Mode
The UART1 handles only data in NRZ (non-return to zero) format.
■ Asynchronous (Start-Stop Synchronized) Mode Transfer Data Format
Figure 19.4-1 shows transfer data format.
Figure 19.4-1 Asynchronous (Start-Stop Synchronized) Mode Transfer Data Format (Mode 0, 1)
SIN1,SOT1
0
1
0
Start LSB
1
1
0
0
1
0
1
1
MSB Stop........(Mode 0)
A/D Stop........(Mode 1)
Transferred data "01001101B"
As shown in Figure 19.4-1, transfer data must begin with a start bit ("L" level data value), followed
by LSB-first data of the designated bit-length, and ending with a stop bit ("H" level data value).
When an external clock signal is selected, the clock should be input at all times.
In normal mode (mode 0), data length may be set to 7 bits or 8 bits, however in multi-processor
mode (mode 1) the data length must be 8 bits. Also, no parity bit may be attached in multiprocessor mode. Instead, an A/D bit must be attached.
■ Asynchronous (Start-Stop Synchronized) Mode Receive Operation
Whenever the RXE bit in the SCR1 register is set to "1", UART1 is receiving.
Detection of a start bit on the receive line allows one frame of data to be received in the data
format determined by the SCR1 register. After the frame is received, error flags are set if the
corresponding errors have occurred, and then the RDRF flag in Serial Status Register (SSR1) is
set. If the RIE bit in the SSR1 register is set to "1", a receive interrupt is sent to the CPU. The
CPU checks each flag in the SSR1 register and reads the SIDR1 register to see if the data has
been received correctly. If any errors have occurred, take the required action.
The RDRF flag is cleared when the SIDR1 register is read.
■ Asynchronous (Start-Stop Synchronized) Mode Transmit Operation
Whenever the TDRE flag in the SSR1 register is set to "1", the UART1 is writing transmission
data to the SODR1 register. If the TXE bit in SCR1 is set to "1", transmit operation is in progress.
As soon as data in the SODR1 register starts to be transferred to the transmit shift register for
transmission, the TDRE flag in SSR1 register is reset. This enables the next unit of outgoing data
to be placed in the SODR1 register. At this time if the TIE bit in the SSR1 register is set to "1" a
transmission interrupt is sent to the CPU, causing outgoing data to be placed into the SODR1
register.
The TDRE flag is momentarily cleared each time data is placed into the SODR1 register.
311
CHAPTER 19 UART1 (SCI)
19.4.2 CLK Synchronous Mode
The UART1 handles only data in NRZ (non-return to zero) format.
■ CLK Synchronous Mode Transfer Data Format
Figure 19.4-2 shows the relation between the transmit and receive clock and data in CLK
synchronous mode.
Figure 19.4-2 CLK Synchronous Mode Transfer Data Format (Mode 2)
SODR1 write
Mark
SCK1
RXE,TXE
SIN1,SOT1
1
0
1
1
0
0
LSB
1
0
MSB...................(Mode 2)
Transferred data "01001101B"
When an internal clock signal source (dedicated baud rate generator or internal timer) is selected,
a receive clock signal is automatically generated each time data is transmitted.
When an external clock source is selected, it is necessary to provide an accurate 1-byte clock
signal after data is confirmed present in the transmit data buffer register SODR1 (indicated by the
TDRE flag = "0"). Note also that the signal must return to mark level before and after transmit
operation.
Data length is 8-bit only, and no parity bit may be attached. Also, there is no start/stop bit so that
no error detection is enabled except for overrun errors.
■ Control Register Settings for CLK Synchronous Mode
When using CLK synchronous mode, the following settings are made to each of the control
registers.
❍ SMR1 register
MD1, MD0:
"10"
CS2, CS1, CS0: Indicate clock input
312
SCKE:
"1" for dedicated baud rate generator or internal timer, "0" for external clock
SOE:
"1" to send, "0" to receive only
CHAPTER 19 UART1 (SCI)
❍ SCR1 register
PEN:
"0"
P, SBL, A/D: These bits have no significance
CL:
"1"
REC:
"0" (to initialize)
RXE, TXE:
At least one must be "1"
❍ SSR1 Register
RIE: "1" if interrupts are used, "0" if interrupts are not used
TIE: "0"
■ Start of Communication in CLK Synchronous Mode
Communication starts by writing to the SODR1 register. Even if data is to be only received (not
sent), it is first necessary to write dummy data to the SODR1 register.
■ End of Communication in CLK Synchronous Mode
The end of communication can be verified by the change of the RDRF flag in the SSR1 register to
"1". To determine whether the communication was performed normally, read the ORE bit in the
SSR1 register.
313
CHAPTER 19 UART1 (SCI)
19.5 UART1 Flags and Interrupt Sources
The UART1 has five flags, PE, ORE, FRE, RDRF and TDRE, and two interrupt sources,
one for transmit and one for receive.
■ UART1 Flags
The five flags are the PE, ORE, FRE, RDRF and TDRE flags. The first three are set when
transmit errors occur, the PE flag for a parity error, the ORE flag for an overrun error, and the
FRE flag for a framing error, and are cleared by writing "0" to the REC bit in the SCR1 register.
The RDRF flag is set when receive a data is loaded into the SIDR1 register, and cleared when
the data is read out of the SIDR1 register. Note however that there is no parity detect function in
mode 1, and no parity detect function or framing error detect function in mode 2. The TDRE flag
is set when the SODR1 register is empty and ready for data write access, and is cleared when
data is written to the SODR1 register.
■ UART1 Interrupt Sources
The UART1 has two interrupt sources, one for receive and one for transmit. During receive,
interrupt requests are initiated by setting the PE, ORE, FRE or RDRF flags. During transmit,
interrupt requests are initiated by setting the TDRE flag.
Interrupt flag set timing in each operating mode is described in section "19.6 UART1 Interrupts
and Flag Set Timing".
314
CHAPTER 19 UART1 (SCI)
19.6 UART1 Interrupts and Flag Set Timing
This section describes the timing of interrupts and flag setting in each UART1 operating
mode.
■ UART1 Interrupts and Flag Set Timing
❍ Mode 0 Receive
The PE, ORE, FRE and RDRF flags are set and the interrupt request signal is sent to the CPU
following the end of a receive transfer, when the final stop bit is detected. If any one of the PE,
ORE or FRE flags is active, the data in the SIDR1 register will be invalid.
Figure 19.6-1 shows the set timing of the PE, ORE, FRE, and RDRF flags (mode 0).
Figure 19.6-1 PE, ORE, FRE, RDRF Flag Set Timing (Mode 0)
Data
D6
D7
Stop
PE,ORE,FRE
RDRF
Receiving interrupt
❍ Mode 1 Receive
The ORE, FRE and RDRF flags are set and the interrupt request signal is sent to the CPU after
the end of a receive transfer, when the final stop bit is detected. Also, if the receive data length is
8 bits, the 9th bit indicating address/data will be invalid. If either the ORE or FRE flags is active,
the data in the SIDR1 register will be invalid.
Figure 19.6-2 shows the timing of the ORE, FRE, and RDRF flags (mode 1).
315
CHAPTER 19 UART1 (SCI)
Figure 19.6-2 ORE, FRE, RDRF Flag Set Timing (Mode 1)
Data
D7
Address/data
Stop
ORE,FRE
RDRF
Receiving interrupt
❍ Mode 2 Receive
The ORE and RDRF flags are set and the interrupt request signal is sent to the CPU after the end
of a receive transfer, when the final data (D7) is detected. If the ORE flag is active, the data in the
SIDR1 register will be invalid.
Figure 19.6-3 shows the set timing of the ORE and RDRF flags (mode 2).
Figure 19.6-3 ORE, RDRF Flag Set Timing (Mode 2)
Data
D5
D6
D7
ORE
RDRF
Receiving interrupt
❍ Mode 0, Mode 1, and Mode 2 Transmit
The TDRE flag is cleared when data is written to the SODR1 register. The TDRE flag is set (and
an interrupt request sent to the CPU) as soon as the data in the SODR1 register is transferred to
the internal shift register, to ready the SODR1 register for the next data write cycle. During a
transmit operation, if "0" is written to the TXE bit in the SCR1 register (including the RXE bit in
mode 2), the TDRE bit in the SSR1 register will be set to "1" and the UART1 transmit operation
will be disabled as soon as the transmit shifter stops. The data written to the SODR1 register will
be sent, however, between the writing of "0" to the TXE bit in the SCR1 register (including the
RXE bit in mode 2), and the end of the transmit operation. Figure 19.6-4 shows the set timing of
the TDRE flag (mode 0, mode 1), and Figure 19.6-5 shows the set timing of the TDRE flag (mode
2).
316
CHAPTER 19 UART1 (SCI)
Figure 19.6-4 TDRE Flag Set Timing (Mode 0, 1)
SODR1 write
TDRE
Interrupt request to CPU
SOT1 interrupt
SOT1 output
ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3
A/D
ST: Start bit D0 to D7: Data bits SP: Stop bit A/D: Address/data multiplexer
Figure 19.6-5 TDRE Flag Set Timing (Mode 2)
SODR1 write
TDRE
Interrupt request to CPU
SOT1 interrupt
SOT1 output
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
DO to D7: Data bits
317
CHAPTER 19 UART1 (SCI)
19.7 Negative Clock Operation
The MB90540/545 series supports the negative clock operation of UART1. In this
operation, an inverter can invert the shift clock signal simplistically. The definition for
the shift clock signal in an active section in UART1 is inverted from the logic "L" level to
the logic "H" level, from the negative edge to the positive edge, or vice versa. This is the
same for serial clock input and output. Thus, the edge selector register is prepared.
■ Negative Clock Operation
Figure 19.7-1 shows the bit configuration of the serial edge select register (SES1)
Figure 19.7-1 Serial Edge Select Register (SES1)
Address: 000029H
Read/write→
Initial value→
7
⎯
(-)
(-)
6
⎯
(-)
(-)
5
⎯
(-)
(-)
4
⎯
(-)
(-)
3
⎯
(-)
(-)
2
⎯
(-)
(-)
1
⎯
(-)
(-)
Table 19.7-1 Setting the NEG Bit
NEG
318
Operation
0
Normal operation [default]
1
The shift clock signal is inverted
0
NEG
(R/W)
(0)
←Bit No.
SES1
CHAPTER 19 UART1 (SCI)
19.8 UART1 Sample Applications and Precautionary Information
This section presents a sample system configuration and communication flow chart as
a sample application of the UART1 used in Mode 1.
■ UART1 Sample Application (System Configuration in Mode 1)
Mode 1 is used when one host CPU is connected to multiple slave CPU's (see Figure 19.8-1).
This UART1 resource supports only communication interface with the host-side unit.
Figure 19.8-1 Sample System Configuration in Mode 1
S0
S1
Host CPU
S0
S1
Slave CPU #0
S0
S1
Slave CPU #1
■ UART1 Communication Flow Chart
Transmission begins with the transfer of address data by the host CPU. Address data is data
handled while the A/D bit in the SCR1 register is set to "1" and is used to select the slave CPU
that is to receive the transmission, and to enable communication with the host CPU. In normal
data, the A/D bit in the SCR1 register is set to "0". Figure 19.8-2 illustrates the flow of this
process.
No parity check function is available in mode 2, so that the PEN bit in the SCR1 register should
be set to "0".
319
CHAPTER 19 UART1 (SCI)
Figure 19.8-2 Communications Flowchart Using Mode 1
(Host CPU)
START
Set transfer mode to "1"
Set D0 to D7 to data selecting slave
CPU, set A/D to "1" and transfer 1 byte
Set A/D to "0"
Enable the receiving operation
Communicate with the slave CPU
No
Communication
ended?
Yes
Communicate with
other slave CPU?
No
Yes
Disable receiving operation
END
■ Intelligent I/O Service (EI2OS)
For details about EI2OS, see section "3.6 Extended Intelligent I/O Service (EI2OS)".
■ Precautions on UART1 Using
Always make communications mode settings when the UART1 is not operating. Transmit and
receive data values are not assured during mode setting.
320
CHAPTER 20
SERIAL I/O
This chapter explains the functions and operations of the serial I/O.
20.1 Outline of Serial I/O
20.2 Serial I/O Registers
20.3 Serial I/O Operation
20.4 Negative Clock Operation
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CHAPTER 20 SERIAL I/O
20.1 Outline of Serial I/O
The serial I/O interface operates in two modes:
• Internal shift clock mode: Data is transferred in synchronization with the internal
clock.
• External shift clock mode: Data is transferred in synchronization with the clock
supplied via the external pin (SCK2). By manipulating the
general-purpose port sharing the external pin (SCK2),
data can also be transferred by a CPU instruction in this
mode.
■ Serial I/O Block Diagram
This block diagram is a serial I/O interface that allows data transfer using clock synchronization.
The interface consists of a single eight-bit channel. Data can be transferred from the LSB or
MSB.
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CHAPTER 20 SERIAL I/O
Figure 20.1-1 Extended Serial I/O Interface Block Diagram
Internal data bus
(MSB first) D7 to D0
D7 to D0 (LSB first)
Transfer direction selection
SIN2
Read
SDR (Serial shift data register)
Write
SOT2
SCK2
Control circuit
Shift clock counter
Internal clock
(Communication prescaler)
2
SMD2
1
0
SMD1 SMD0
SIE
SIR
BUSY
STOP
STRT
MODE
BDS
SOE
SCOE
Interrupt
request
Internal data bus
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CHAPTER 20 SERIAL I/O
20.2 Serial I/O Registers
The serial I/O has the following three registers:
• Serial mode control status register
• Serial shift data register
• Serial I/O prescaler
■ Serial I/O Resisters
Figure 20.2-1 shows the bit configuration of the serial I/O registers.
Figure 20.2-1 Serial I/O Registers
Serial Mode Control Status Register
15
14
13
SMD2 SMD1 SMD0
Address: 00002DH
(R/W) (R/W) (R/W)
Read/write→
Initial value→
(0)
(0)
(0)
12
SIE
(R/W)
(0)
10
9
BUSY STOP
(R)
(R/W)
(0)
(1)
8
STRT
(R/W)
(0)
←Bit No.
SMCS
3
2
MODE BDS
(R/W) (R/W)
(0)
(0)
1
SOE
(R/W)
(0)
0
SCOE
(R/W)
(0)
←Bit No.
4
D4
(R/W)
(X)
3
D3
(R/W)
(X)
2
D2
(R/W)
(X)
1
D1
(R/W)
(X)
0
D0
(R/W)
(X)
←Bit No.
12
⎯
(-)
(-)
11
DIV3
(R/W)
(1)
10
DIV2
(R/W)
(1)
9
DIV1
(R/W)
(1)
8
DIV0
(R/W)
(1)
←Bit No.
7
⎯
(-)
(-)
6
⎯
(-)
(-)
5
⎯
(-)
(-)
4
⎯
(-)
(-)
Address: 00002EH
Read/write→
Initial value→
7
D7
(R/W)
(X)
6
D6
(R/W)
(X)
5
D5
(R/W)
(X)
Serial I/O prescaler
Address: 00002BH
Read/write→
Initial value→
15
MD
(R/W)
(0)
14
⎯
(-)
(-)
13
⎯
(-)
(-)
Address: 00002CH
Read/write→
Initial value→
11
SIR
(R/W)
(0)
SMCS
Serial shift data register
324
SDR
SCDCR
CHAPTER 20 SERIAL I/O
20.2.1 Serial Mode Control Status Register (SMCS)
The serial mode control status register (SMCS) controls the serial I/O transfer mode.
■ Serial Mode Control Status Register (SMCS)
Figure 20.2-2 shows the bit configuration of the serial mode control status register (SMCS).
Figure 20.2-2 Serial Mode Control Status Register (SMCS)
Address: 00002DH
Read/write→
Initial value→
Address: 00002CH
Read/write→
Initial value→
15
14
13
SMD2 SMD1 SMD0
(R/W) (R/W) (R/W)
(0)
(0)
(0)
7
⎯
(-)
(-)
6
⎯
(-)
(-)
5
⎯
(-)
(-)
12
SIE
(R/W)
(0)
4
⎯
(-)
(-)
11
10
9
8
SIR
BUSY STOP STRT
(R/W)
(R)
(R/W) (R/W)
(0)
(0)
(1)
(0)
↑
↑
*1
*2
3
2
1
0
MODE BDS
SOE SCOE
(R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
←Bit No.
SMCS
←Bit No.
SMCS
*1: Only "0" can be written.
*2: Only "1" can be written. "0" is always read.
[bit3] Serial mode selection bit (MODE)
The serial mode selection bit is used to select the conditions to start the transfer operation
from the stop state. This bit must not be updated during operation.
Table 20.2-1 Setting the Serial Mode Selection Bit
MODE
Operation
0
Transfer starts when STRT=1. [Default]
1
Transfer starts when the serial shift data register is read or written to.
This bit is initialized to a "0" upon a reset, and can be read or written to. To activate the
intelligent I/O service, ensure that "1" is written to this bit.
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CHAPTER 20 SERIAL I/O
[bit2] BDS (Bit Direction Select bit)
When serial data is input or output, this bit determines from which bit data is to be transferred
first, the least significant bit (LSB first) or the most significant bit (MSB first), as shown in Table
20.2-2.
Table 20.2-2 Setting the Transfer Direction Selection Bit
BDS
Operation
0
LSB first [default]
1
MSB first
Note:
Specify the BDS bit ordering before any data is written to SDR.
[bit1] SOE (Serial Output Enable bit)
This bit controls the output from the serial I/O output external pins (SOT2) as shown in Table
20.2-3.
Table 20.2-3 Setting the Serial Output Enable Bit
SOE
Operation
0
General-purpose port pin [default]
1
Serial data output
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit0] SCOE: SCK2 Output Enable (Shift Clock Output Enable bit)
This bit controls the output from the shift clock I/O output external pins (SCK2) as shown in
Table 20.2-4.
Table 20.2-4 Setting the Shift Clock Output Enable Bit
SCOE
Operation
0
General-purpose port pin, transfer for each instruction [default]
1
Shift clock output pin
Ensure that "0" is written to this bit when data is transferred for each instruction in external
shift clock mode.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
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CHAPTER 20 SERIAL I/O
[bit15, bit14, and bit13] SMD2, SMD1, SMD0: Serial shift clock mode (Shift clock selection
bits)
These bits are used to select the serial shift clock mode, as shown in Table 20.2-5.
Table 20.2-5 Setting the Serial Shift Clock Mode
SMD2
SMD1
SMD0
φ/div=4 MHz
φ/div=2 MHz
φ/div=1 MHz
0
0
0
2 MHz
1 MHz
500 kHz
0
0
1
1 MHz
500 kHz
250 kHz
0
1
0
250 kHz
125 kHz
62.5 kHz
0
1
1
125 kHz
62.5 kHz
31.25 kHz
1
0
0
62.5 kHz
31.25 kHz
15.625 kHz
1
0
1
External shift clock mode
1
1
0
Reserved
1
1
1
Reserved
div
M1
DIV3
DIV2
DIV1
DIV0
Recommended
machine cycle
3
1
1
1
0
1
6 MHz
4
1
1
1
0
0
8 MHz
5
1
1
0
1
1
10 MHz
6
1
1
0
1
0
12 MHz
7
1
1
0
0
1
14 MHz
8
1
1
0
0
0
16 MHz
Note: For details of each bit, see "20.2.3 Serial I/O Prescaler (SCDCR)".
These bits are initialized to "000B" upon a reset. These bits must not be updated during data
transfer.
Five types of internal shift clock and an external shift clock are available. Do not set "110B" or
"111B" into SMD2, SMD1, and SMD0 as these values are reserved.
When external shift clock mode is selected, changing the output levels of the general-purpose
I/O devices sharing the shift clock input will also enable bit shifting.
[bit12] SIE: Serial I/O interrupt enable (Serial I/O interrupt enable bit)
This bit controls the serial I/O interrupt request as shown in Table 20.2-6.
Table 20.2-6 Setting the Interrupt Request Enable Bit
SIE
Operation
0
Serial I/O interrupt disabled [initial value]
1
Serial I/O interrupt enabled
This bit is initialized to "0" upon a reset. This bit is readable and writable.
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CHAPTER 20 SERIAL I/O
[bit11] SIR: Serial I/O interrupt request (Serial I/O interrupt request bit)
When serial data transfer is completed, "1" is set to this bit. If this bit is set while interrupts are
enabled (SIE=1), an interrupt request is issued to the CPU. The clear condition varies with the
MODE bit.
When "0" is written to the MODE bit, the SIR bit is cleared by writing "0". When "1" is written to
the MODE bit, the SIR bit is cleared by reading or writing to SDR. When the system is reset or
"1" is written to the STOP bit, the SIR bit is cleared regardless of the MODE bit value.
Writing "1" to the SIR bit has no effect. "1" is always read by a read operation of a readmodify-write instruction.
[bit10] BUSY (Transfer status bit)
The transfer status bit indicates whether serial transfer is being executed.
Table 20.2-7 Setting the Transfer Status Bit
BUSY
Operation
0
Stopped, or standing by for serial shift data register R/W [default]
1
Serial transfer
This bit is initialized to "0" upon a reset. This is a read-only bit.
[bit9] STOP (Stop bit)
The stop bit forcibly terminates serial transfer. When "1" is written to this bit, the transfer is
stopped.
Table 20.2-8 Setting the Stop Bit
STOP
Operation
0
Normal operation
1
Transfer stop by STOP=1 [initial value]
This bit is initialized to "1" upon a reset. This bit is readable and writable.
[bit8] STRT: Start (Start bit)
The start bit activates serial transfer. Writing "1" to this bit starts the data transfer in the stop
status.
Writing "1" is ignored while the system is performing serial transfer or standing by for a serial
shift data register read or write. Writing "0" has no effect. "0" is always read in reading time.
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CHAPTER 20 SERIAL I/O
20.2.2 Serial Shift Data Register (SDR)
This serial shift data register (SDR) stores the serial I/O transfer data. During transfer, it
is prohibited to be read on written to.
■ Serial Shift Data Register (SDR)
Figure 20.2-3 shows the bit configuration of the serial shift data register (SDR).
Figure 20.2-3 Serial Shift Data Register (SDR)
Address: 00002EH
Read/write→
Initial value→
7
D7
(R/W)
(X)
6
D6
(R/W)
(X)
5
D5
(R/W)
(X)
4
D4
(R/W)
(X)
3
D3
(R/W)
(X)
2
D2
(R/W)
(X)
1
D1
(R/W)
(X)
0
D0
(R/W)
(X)
←Bit No.
SDR
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CHAPTER 20 SERIAL I/O
20.2.3 Serial I/O Prescaler (SCDCR)
The Serial I/O Prescaler (SCDCR) provides the shift clock for the Serial I/O.
The operation clock for the Serial I/O is obtained by dividing the machine clock. The
serial I/O is designed so that a constant baud rate can be obtained for a variety of
machine clocks by the user of the communication prescaler. The SCDCR register
controls the machine clock division.
■ Serial I/O Prescaler (SCDCR)
Figure 20.2-4 shows the bit configuration of the serial I/O prescaler (SCDCR).
Figure 20.2-4 Serial I/O Prescaler (SCDCR)
Address: 00002BH
Read/write→
Initial value→
15
MD
(R/W)
(0)
14
⎯
(-)
(-)
13
⎯
(-)
(-)
12
⎯
(-)
(-)
11
DIV3
(R/W)
(1)
10
DIV2
(R/W)
(1)
9
DIV1
(R/W)
(1)
8
DIV0
(R/W)
(1)
←Bit No.
SCDCR
[bit15] MD (Machine clock divide mode select)
This bit is used to enable the operation of the communication prescaler.
0: The Serial I/O Prescaler is disabled.
1: The Serial I/O Prescaler is enabled.
[bit11, bit10, bit9, and bit8] DIV3 to DIV0 (DiVide 3 to 0):
These bits are used to determine the machine clock division ratio.
Table 20.2-9 Machine Clock Division Ratio
DIV3 to DIV0
Division ratio
1101B
3
1100B
4
1011B
5
1010B
6
1001B
7
1000B
8
Note:
When the division ratio is changed, allow two cycles for the clock to stabilize before starting
communication.
330
CHAPTER 20 SERIAL I/O
20.3 Serial I/O Operation
The serial I/O consists of the serial mode control status register (SMCS) and serial shift
data register (SDR), and is used for input and output of 8-bit serial data.
■ Serial I/O Operation
The bits in the shift register are serially output via the serial output pin (SOT2 pin) at the falling
edge of the serial shift clock (external clock or internal clock). The bits are serially input to the
serial shift data register (SDR) via the serial input pin (SIN2 pin) at the rising edge of the serial
shift clock. The shift direction (transfer from MSB or LSB) is specified by the direction
specification bit (BDS) of the serial mode control status register (SMCS).
At the end of serial data transfer, this block is stopped or stands by for a read or write of the data
register according to the MODE bit of the serial mode control status register (SMCS). To start
transfer from the stop or standby state, follow the procedure below.
• To resume operation from the stop state, write "0" to the STOP bit and "1" to the STRT bit.
(The STOP and STRT bits can be set simultaneously.)
• To resume operation from the serial shift data register R/W standby state, read or write to the
data register.
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CHAPTER 20 SERIAL I/O
20.3.1 Shift Clock
There are two modes of shift clock: internal or external shift clock. These two modes
are selected by setting the SMCS. To switch the modes, ensure that serial I/O transfer is
stopped. To check whether the serial I/O transfer is stopped, read the BUSY bit.
■ Internal Shift Clock Mode
In internal clock mode, the internal clock determines operation, and shift clocks with a duty ratio
of 50% can be output from the SCK2 pin. One bit of data is transferred for each clock. The
transfer speed (baud rate) is shown below:
φ / div
A
Baud rate =
A is a frequency-division ratio and is 21, 22, 24, 25, or 26 indicated by the SMD bits of SMCS.
Table 20.3-1 Formulas for Calculating Baud Rate in Internal Shift Clock Mode
SMD2
SMD1
SMD0
φ/div=4MHz
φ/div=2MHz
φ/div=1MHz
Formula
0
0
0
2 MHz
1 MHz
500 kHz
(φ/div)/21
0
0
1
1 MHz
500 kHz
250 kHz
(φ/div)/22
0
1
0
250 kHz
125 kHz
62.5 kHz
(φ/div)/24
0
1
1
125 kHz
62.5 kHz
31.25 kHz
(φ/div)/25
1
0
0
62.5 kHz
31.2 kHz
15.625 kHz
(φ/div)/26
See Table 19.4-4, for the div values.
■ External Shift Clock Mode
In external shift clock mode, the data transfer is based on the external shift clock supplied via the
SCK2 pin. Data is transferred at one bit per clock.
The transfer speed can be between DC and 1/(8 machine cycles). For example, the transfer
speed can be up to 2 MHz when 1 machine cycle is equal to 62.5 ns.
A data bit can also be transferred by instruction, which is enabled as described below.
Select external shift clock mode, and write "0" to the SCOE bit of SMCS. Then, write "1" to the
direction register for the port sharing the SCK2 pin, and place the port in output mode. Then,
when "1" and "0" are written to the port data register (PDR0 to PDRA), the port value output via
the SCK2 pin is fetched as the external clock and transfer starts. Ensure that the shift clock starts
from "H".
Note:
The SMCS or SDR must not be written to during serial I/O operation.
332
CHAPTER 20 SERIAL I/O
20.3.2 Serial I/O Operation
There are four serial I/O operation statuses:
• STOP
• Halt
• SDR R/W standby
• Transfer
■ Serial I/O Operation
❍ STOP
The STOP state is initiated upon RESET or when "1" is written to the STOP bit of SMCS. The
shift counter is initialized, and "0" is written to SIR.
To resume operation from the STOP state, write "0" to STOP and "1" to STRT. (These two bits
can be written to simultaneously.) Since the STOP bit overrides the STRT bit, transfer cannot be
started by writing "1" to STRT while "1" is written to STOP.
❍ Halt
When transfer is completed while the MODE bit is "0", "0" is set to BUSY and "1" is set to SIR of
the SMCS, the counter is initialized, and the system halts. To resume operation from the halt
state, write "1" to STRT.
❍ Serial shift data register R/W standby
When transfer is completed while the MODE bit is "1", "0" is set to BUSY and "1" is set to SIR of
the SMCS, and the system enters the serial shift data register R/W standby state. If the interrupt
enable flag is set, an interrupt signal is output from this block.
To resume operation from R/W standby state, read or write to the serial shift data register. This
sets the BUSY bit to "1" and starts data transfer.
❍ Transfer
"1" is set to the BUSY bit and serial transfer is being performed. According to the MODE bit, the
halt state or R/W standby state comes next.
Figure 20.3-1 is diagrams of the operation transitions.
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CHAPTER 20 SERIAL I/O
Figure 20.3-1 Serial I/O Operation Transitions
End of transfer
STOP
STRT=0, BUSY=0
MODE=0
MODE=0
&
STOP=0
&
END
STOP=0
&
STRT=1
Reset
STOP=0 & STRT=0
STRT=0, BUSY=0
STOP=1
STOP=1
STOP=0
&
STRT=1
STOP=1
Serial shift data register R/W standby
Transfer
MODE=1 & END & STOP=0
STRT=1, BUSY=1
STRT=1, BUSY=0
MODE=1
SDR R/W & MODE=1
Serial data
Figure 20.3-2 Serial Shift Data Register Read/write
Data bus
Data bus
Read
Write
Interrupt output
SOT2
SIN2
Extended I/O
serial interface
Read
Write
➁
CPU
➀
Interrupt input
Data bus
Interrupt controller
1. If "1" is written to MODE, transfer ends according to the shift clock counter. The read/write
standby state starts when "1" is written to SIR. If "1" is written to the SIE bit, an interrupt signal
is generated. No interrupt signal is generated when SIE is inactive or transfer has been
terminated by writing "1" to STOP.
2. Reading or writing to the serial shift data register clears the interrupt request and starts serial
transfer.
334
CHAPTER 20 SERIAL I/O
20.3.3 Shift Operation Start/Stop Timing
To start the shift operation, set the STOP bit to "0" and the STRT bit to "1" in SMCS.
The system may stop the shift operation when "1" is set in the STOP bit or at the end of
transfer.
• Stop by STOP=1 ->The system stops with SIR=0 regardless of the MODE bit.
• Stop by end of transfer -> The system stops with SIR=1 regardless of the MODE bit.
Regardless of the MODE bit, the BUSY bit becomes "1" during serial transfer and
becomes "0" during stop or R/W standby state. To check the transfer status, read this
bit.
■ Shift Operation Start/Stop Timing
❍ Internal shift clock mode (LSB first)
Figure 20.3-3 Shift Operation Start/Stop Timing (Internal Clock)
"1" output
SCK2
(Transfer start)
STRT
(Transfer end)
If MODE=0
BUSY
SOT2
D00
D07 (Data maintained)
❍ External shift clock mode (LSB first)
Figure 20.3-4 Shift Operation Start/Stop Timing (External Clock)
SCK2
(Transfer start)
STRT
(Transfer end)
If MODE=0
BUSY
SOT2
D00
D07 (Data maintained)
335
CHAPTER 20 SERIAL I/O
❍ External shift clock mode with instruction shift (LSB first)
Figure 20.3-5 Shift Operation Start/Stop Timing (External Shift Clock Mode with Instruction Shift)
SCK2
SCK2="0" in PDR
STRT
SCK2="0" in PDR
SCK2="1" in PDR (Transfer end)
If MODE=0
BUSY
D07 (Data maintained)
D06
SOT2
Note:
For an instruction shift, "H" is output when "1" is written to the bit corresponding to SCK2 of PDR,
and "L" is output when "0" is written. (When SCOE=0 in external shift clock mode)
❍ Stop by STOP=1 (LSB first, internal clock)
Figure 20.3-6 Stop Timing when "1" is Written to the STOP Bit
"1" output
SCK2
(Transfer start)
(Transfer stop)
If MODE=0
STRT
BUSY
STOP
SOT2
D03
D04
D05 (Data maintained)
Note:
D07 to D00 indicate output data.
During serial data transfer, data is output from the serial output pin (SOT2) at the falling edge of the
shift clock, and input from the serial input pin (SIN2) at the rising edge.
336
CHAPTER 20 SERIAL I/O
❍ LSB first (When the BDS bit is "0")
Figure 20.3-7 Serial Data I/O Shift Timing 1
SCK2
SIN2
SIN2 Input
D10
D11
D12
D15
D16
D17
D05
D06
D07
D13
D12
D11
D10
D03
D02
D01
D13
D14
SOT2 Output
SOT2
D00
D01
D02
D03
D04
❍ MSB first (When the BDS bit is "1")
Figure 20.3-8 Serial Data I/O Shift Timing 2
SCK2
SIN2
SIN2 Input
D17
D16
D15
D14
SOT2 Output
SOT2
D07
D06
D05
D04
D00
337
CHAPTER 20 SERIAL I/O
20.3.4 Interrupt Function of the Serial I/O Interface
This block can issue an interrupt request to the CPU. At the end of data transfer, the SIR
bit is set as an interrupt flag. When "1" is written to the interrupt enable bit (SIE bit) of
SMCS, an interrupt request is issued to the CPU.
■ Interrupt Function of the Serial I/O Interface
Figure 20.3-9 Interrupt Signal Output Timing of Serial I/O
SCK2
(Transfer end)*
BUSY
SIE=1
SIR
RD/WR of SDR
SOT2
338
D06
D07 (Data is maintained.)
* When MODE=1
CHAPTER 20 SERIAL I/O
20.4 Negative Clock Operation
The MB90540/545 Series supports the negative clock operation of the Serial I/O. In this
operation, the shift clock signal is simply negated by a inverter. Therefore the definition
of the shift clock signal in the proceeding sections of the Serial I/O is inversed from the
logic "L" level to logic "H" level, from the negative edge to the positive edge and viseversa. This is the same for both the serial clock input and output. The edge select
register is installed for this purpose.
■ Negative Clock Operation
Figure 20.4-1 shows the bit configuration of the serial edge select register (SES2).
Figure 20.4-1 Serial Edge Select Register (SES2)
Address: 00002FH
Read/write→
Initial value→
7
⎯
(-)
(-)
6
⎯
(-)
(-)
5
⎯
(-)
(-)
4
⎯
(-)
(-)
3
⎯
(-)
(-)
2
⎯
(-)
(-)
1
⎯
(-)
(-)
0
NEG
(R/W)
(0)
←Bit No.
SES2
Table 20.4-1 Setting the NEG Bit
NEG
Operation
0
Normal operation [default]
1
The shift clock signal is inverted
339
CHAPTER 20 SERIAL I/O
340
CHAPTER 21
CAN CONTROLLER
This chapter explains the functions and operations of the CAN controller.
21.1 Features of CAN Controller
21.2 Block Diagram of CAN Controller
21.3 List of Overall Control Registers
21.4 List of Message Buffers (ID Registers)
21.5 List of Message Buffers (DLC Registers and Data Registers)
21.6 Classifying the CAN Controller Registers
21.7 Transmission of CAN Controller
21.8 Reception of CAN Controller
21.9 Reception Flowchart of CAN Controller
21.10 How to Use the CAN Controller
21.11 Procedure for Transmission by Message Buffer (x)
21.12 Procedure for Reception by Message Buffer (x)
21.13 Setting Configuration of Multi-level Message Buffer
21.14 Precautions when Using CAN Controller
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CHAPTER 21 CAN CONTROLLER
21.1 Features of CAN Controller
The MB90540 series has two CAN controllers (CAN0, CAN1); the MB90545 series has
one CAN controller (CAN0). The MB90V540 evaluation chip also has two CAN
controllers.
The CAN controller is a module built into a 16-bit microcomputer (F2MC-16LX). The CAN
(Controller Area Network) is the standard protocol for serial communication between
automobile controllers and is used widely in industrial applications.
■ Features of CAN Controller
The CAN controller has the following features:
❍ Conforms to CAN Specification Version 2.0 Part A and B
Supports transmission/reception in standard frame and extended frame formats
❍ Supports transmitting of data frames by receiving remote frames
❍ 16 transmitting/receiving message buffers
29-bit ID and 8-byte data
Multi-level message buffer configuration
❍ Acceptance register0/1 for each message buffer for full-bit comparison, full-bit mask, and
ID acceptance mask
Two acceptance mask registers in either standard frame format or extended frame formats
❍ Bit rate programmable from 10 Kbps to 1 Mbps (A minimum 8 MHz machine clock is
required if 1 Mbps is used).
342
CHAPTER 21 CAN CONTROLLER
21.2 Block Diagram of CAN Controller
Figure 21.2-1 shows a block diagram of the CAN controller.
■ Block Diagram of CAN Controller
Figure 21.2-1 Block Diagram of CAN Controller
TQ (Operating clock)
Internal data bus
Prescaler
1 to 64 frequency division
Clock
Bit timing generation
SYNC, TSEG1, TSEG2
PSC
TS1
BTR
TS2
RSJ
TOE
TS
RS
CSR
HALT
NIE
NT
Node status change
interrupt generation
IDLE, INT, SUSPND,
transmit, receive,
ERR, OVRLD
Busstate
machine
Node status
change interrupt
NS1, 0
Error
control
RTEC
Transmitting/receiving
sequencer
BVALR
TREQR
TBFx, clear
Transmitting
buffer x decision
TBFx
Data
counter
Error frame
generation
Acceptance
filter control
Overload
frame
generation
TDLC RDLC
TBFx
IDSEL
BITER, STFER,
CRCER, FRMER,
ACKER
TCANR
Output
driver
ARBLOST
TX
TRTRR
TCR
Stuffing
Transmission
shift register
RFWTR
TBFx, set, clear
Transmission
complete
interrupt
Transmissioncomplete
interrupt generation
TDLC
TIER
CRC
generation
ACK
generation
CRCER
RBFx, set
RDLC
RCR
Reception
complete
interrupt
Reception complete
interrupt generation
RIER
RBFx, TBFx, set, clear
CRCgeneration/error
check
Receive shift
register
STFER
Destuffing/stuffing
error check
RRTRR
RBFx, set
IDSEL
ROVRR
ARBLOST
AMSR
AMR0
0
1
Acceptance
filter
Receivingbufferx
decision
BITER
Bit error
check
ACKER
Acknowledgment
error check
AMR1
RBFx
IDR0 to 15
DLCR0 to 15
DTR0 to 15
RAM
RAM address
generation
Arbitration
check
FRMER
Form error
check
PH1
Input
latch
RX
RBFx, TBFx, RDLC, TDLC, IDSEL
LEIR
LDER
343
CHAPTER 21 CAN CONTROLLER
21.3 List of Overall Control Registers
Table 21.3-1 lists overall control registers.
■ List of Overall Control Registers
Table 21.3-1 List of Overall Control Registers (1/2)
Address
Abbreviation
Access
Initial Value
Message buffer valid
register
BVALR
R/W
00000000 00000000
Transmit request
register
TREQR
R/W
00000000 00000000
Transmit cancel register
TCANR
W
00000000 00000000
Transmit complete
register
TCR
R/W
00000000 00000000
Receive complete
register
RCR
R/W
00000000 00000000
Remote request
receiving register
RRTRR
R/W
00000000 00000000
Receive overrun
register
ROVRR
R/W
00000000 00000000
Receive interrupt enable
register
RIER
R/W
00000000 00000000
Control status register
CSR
R/W, R
00---000 0----001
Last event indicator
register
LEIR
R/W
-------- 000-0000
Receive/transmit error
counter
RTEC
R
00000000 00000000
Register
CAN0
CAN1
000070H
000080H
000071H
000081H
000072H
000082H
000073H
000083H
000074H
000084H
000075H
000085H
000076H
000086H
000077H
000087H
000078H
000088H
000079H
000089H
00007AH
00008AH
00007BH
00008BH
00007CH
00008CH
00007DH
00008DH
00007EH
00008EH
00007FH
00008FH
003B00H
003D00H
003B01H
003D01H
003B02H
003D02H
003B03H
003D03H
003B04H
003D04H
003B05H
003D05H
344
CHAPTER 21 CAN CONTROLLER
Table 21.3-1 List of Overall Control Registers (2/2)
Address
Abbreviation
Access
Initial Value
Bit timing register
BTR
R/W
-1111111 11111111
IDE register
IDER
R/W
XXXXXXXX XXXXXXXX
Transmit RTR register
TRTRR
R/W
00000000 00000000
Remote frame receive
waiting register
RFWTR
R/W
XXXXXXXX XXXXXXXX
TIER
R/W
00000000 00000000
Register
CAN0
CAN1
003B06H
003D06H
003B07H
003D07H
003B08H
003D08H
003B09H
003D09H
003B0AH
003D0AH
003B0BH
003D0BH
003B0CH
003D0CH
003B0DH
003D0DH
003B0EH
003D0EH
003B0FH
003D0FH
003B10H
003D10H
003B11H
003D11H
003B12H
003D12H
003B13H
003D13H
003B14H
003D14H
003B15H
003D15H
003B16H
003D16H
003B17H
003D17H
003B18H
003D18H
003B19H
003D19H
003B1AH
003D1AH
003B1BH
003D1BH
Transmit interrupt
enable register
XXXXXXXX XXXXXXXX
Acceptance mask select
register
AMSR
R/W
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
Acceptance mask
register 0
AMR0
R/W
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
Acceptance mask
register 1
AMR1
R/W
XXXXX--- XXXXXXXX
345
CHAPTER 21 CAN CONTROLLER
21.4 List of Message Buffers (ID Registers)
Table 21.4-1 lists message buffers (ID registers).
■ List of Message Buffers (ID Registers)
Table 21.4-1 List of Message Buffers (ID Registers) (1/3)
Address
346
CAN0
CAN1
003A00H
to
003A1FH
003C00H
to
003C1FH
003A20H
003C20H
003A21H
003C21H
003A22H
003C22H
003A23H
003C23H
003A24H
003C24H
003A25H
003C25H
003A26H
003C26H
003A27H
003C27H
003A28H
003C28H
003A29H
003C29H
003A2AH
003C2AH
003A2BH
003C2BH
003A2CH
003C2CH
003A2DH
003C2DH
003A2EH
003C2EH
003A2FH
003C2FH
003A30H
003C30H
003A31H
003C31H
003A32H
003C32H
003A33H
003C33H
Register
Abbrevia-tion
Access
Initial Value
Generalpurpose RAM
--
R/W
XXXXXXXX
to
XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 0
IDR0
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 1
IDR1
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 2
IDR2
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 3
IDR3
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 4
IDR4
R/W
XXXXX--XXXXXXXX
CHAPTER 21 CAN CONTROLLER
Table 21.4-1 List of Message Buffers (ID Registers) (2/3)
Address
Register
CAN0
CAN1
003A34H
003C34H
003A35H
003C35H
003A36H
003C36H
003A37H
003C37H
003A38H
003C38H
003A39H
003C39H
003A3AH
003C3AH
003A3BH
003C3BH
003A3CH
003C3CH
003A3DH
003C3DH
003A3EH
003C3EH
003A3FH
003C3FH
003A40H
003C40H
003A41H
003C41H
003A42H
003C42H
003A43H
003C43H
003A44H
003C44H
003A45H
003C45H
003A46H
003C46H
003A47H
003C47H
003A48H
003C48H
003A49H
003C49H
003A4AH
003C4AH
003A4BH
003C4BH
003A4CH
003C4CH
003A4DH
003C4DH
003A4EH
003C4EH
003A4FH
003C4FH
Abbrevia-tion
Access
Initial Value
XXXXXXXX
XXXXXXXX
ID register 5
IDR5
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 6
IDR6
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 7
IDR7
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 8
IDR8
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 9
IDR9
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 10
IDR10
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 11
IDR11
R/W
XXXXX--XXXXXXXX
347
CHAPTER 21 CAN CONTROLLER
Table 21.4-1 List of Message Buffers (ID Registers) (3/3)
Address
Register
348
CAN0
CAN1
003A50H
003C50H
003A51H
003C51H
003A52H
003C52H
003A53H
003C53H
003A54H
003C54H
003A55H
003C55H
003A56H
003C56H
003A57H
003C57H
003A58H
003C58H
003A59H
003C59H
003A5AH
003C5AH
003A5BH
003C5BH
003A5CH
003C5CH
003A5DH
003C5DH
003A5EH
003C5EH
003A5FH
003C5FH
Abbrevia-tion
Access
Initial Value
XXXXXXXX
XXXXXXXX
ID register 12
IDR12
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 13
IDR13
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 14
IDR14
R/W
XXXXX--XXXXXXXX
XXXXXXXX
XXXXXXXX
ID register 15
IDR15
R/W
XXXXX--XXXXXXXX
CHAPTER 21 CAN CONTROLLER
21.5 List of Message Buffers (DLC Registers and Data Registers)
Table 21.5-1 lists message buffers (DLC registers), and Table 21.5-2 lists message
buffers (data registers).
■ List of Message Buffers (DLC Registers and Data Registers)
Table 21.5-1 List of Message Buffers (DLC Registers and Data Registers) (1/2)
Address
Abbrevia
-tion
Access
Initial Value
DLC register 0
DLCR0
R/W
-------- ----XXXX
DLC register 1
DLCR1
R/W
-------- ----XXXX
DLC register 2
DLCR2
R/W
-------- ----XXXX
DLC register 3
DLCR3
R/W
-------- ----XXXX
DLC register 4
DLCR4
R/W
-------- ----XXXX
DLC register 5
DLCR5
R/W
-------- ----XXXX
DLC register 6
DLCR6
R/W
-------- ----XXXX
DLC register 7
DLCR7
R/W
-------- ----XXXX
DLC register 8
DLCR8
R/W
-------- ----XXXX
DLC register 9
DLCR9
R/W
-------- ----XXXX
DLC register 10
DLCR10
R/W
-------- ----XXXX
Register
CAN0
CAN1
003A60H
003C60H
003A61H
003C61H
003A62H
003C62H
003A63H
003C63H
003A64H
003C64H
003A65H
003C65H
003A66H
003C66H
003A67H
003C67H
003A68H
003C68H
003A69H
003C69H
003A6AH
003C6AH
003A6BH
003C6BH
003A6CH
003C6CH
003A6DH
003C6DH
003A6EH
003C6EH
003A6FH
003C6FH
003A70H
003C70H
003A71H
003C71H
003A72H
003C72H
003A73H
003C73H
003A74H
003C74H
003A75H
003C75H
349
CHAPTER 21 CAN CONTROLLER
Table 21.5-1 List of Message Buffers (DLC Registers and Data Registers) (2/2)
Address
350
CAN0
CAN1
003A76H
003C76H
003A77H
003C77H
003A78H
003C78H
003A79H
003C79H
003A7AH
003C7AH
003A7BH
003C7BH
003A7CH
003C7CH
003A7DH
003C7DH
003A7EH
003C7EH
003A7FH
003C7FH
Register
Abbrevia
-tion
Access
Initial Value
DLC register 11
DLCR11
R/W
-------- ----XXXX
DLC register 12
DLCR12
R/W
-------- ----XXXX
DLC register 13
DLCR13
R/W
-------- ----XXXX
DLC register 14
DLCR14
R/W
-------- ----XXXX
DLC register 15
DLCR15
R/W
-------- ----XXXX
CHAPTER 21 CAN CONTROLLER
■ List of Message Buffers (Data Registers)
Table 21.5-2 List of Message Buffers (Data Registers) (1/2)
Address
Register
Abbrevia
-tion
Access
Initial Value
CAN0
CAN1
003A80H
to
003A87H
003C80H
to
003C87H
Data register 0 (8 bytes)
DTR0
R/W
XXXXXXXX
to
XXXXXXXX
003A88H
to
003A8FH
003C88H
to
003C8FH
Data register 1 (8 bytes)
DTR1
R/W
XXXXXXXX
to
XXXXXXXX
003A90H
to
003A97H
003C90H
to
003C97H
Data register 2 (8 bytes)
DTR2
R/W
XXXXXXXX
to
XXXXXXXX
003A98H
to
003A9FH
003C98H
to
003C9FH
Data register 3 (8 bytes)
DTR3
R/W
XXXXXXXX
to
XXXXXXXX
003AA0H
to
003AA7H
003CA0H
to
003CA7H
Data register 4 (8 bytes)
DTR4
R/W
XXXXXXXX
to
XXXXXXXX
003AA8H
to
003AAFH
003CA8H
to
003CAFH
Data register 5 (8 bytes)
DTR5
R/W
XXXXXXXX
to
XXXXXXXX
003AB0H
to
003AB7H
003CB0H
to
003CB7H
Data register 6 (8 bytes)
DTR6
R/W
XXXXXXXX
to
XXXXXXXX
003AB8H
to
003ABFH
003CB8H
to
003CBFH
Data register 7 (8 bytes)
DTR7
R/W
XXXXXXXX
to
XXXXXXXX
003AC0H
to
003AC7H
003CC0H
to
003CC7H
Data register 8 (8 bytes)
DTR8
R/W
XXXXXXXX
to
XXXXXXXX
003AC8H
to
003ACFH
003CC8H
to
003CCFH
Data register 9 (8 bytes)
DTR9
R/W
XXXXXXXX
to
XXXXXXXX
003AD0H
to
003AD7H
003CD0H
to
003CD7H
Data register 10
(8 bytes)
DTR10
R/W
XXXXXXXX
to
XXXXXXXX
003AD8H
to
003ADFH
003CD8H
to
003CDFH
Data register 11
(8 bytes)
DTR11
R/W
XXXXXXXX
to
XXXXXXXX
351
CHAPTER 21 CAN CONTROLLER
Table 21.5-2 List of Message Buffers (Data Registers) (2/2)
Address
Register
352
Abbrevia
-tion
Access
Initial Value
CAN0
CAN1
003AE0H
to
003AE7H
003CE0H
to
003CE7H
Data register 12
(8 bytes)
DTR12
R/W
XXXXXXXX
to
XXXXXXXX
003AE8H
to
003AEFH
003CE8H
to
003CEFH
Data register 13
(8 bytes)
DTR13
R/W
XXXXXXXX
to
XXXXXXXX
003AF0H
to
003AF7H
003CF0H
to
003CF7H
Data register 14
(8 bytes)
DTR14
R/W
XXXXXXXX
to
XXXXXXXX
003AF8H
to
003AFFH
003CF8H
to
003CFFH
Data register 15
(8 bytes)
DTR15
R/W
XXXXXXXX
to
XXXXXXXX
CHAPTER 21 CAN CONTROLLER
21.6 Classifying the CAN Controller Registers
There are three types of CAN controller registers:
• Overall control registers
• Message buffer control registers
• Message buffers
■ Overall Control Registers
The overall control registers are the following four registers:
•
Control status register (CSR)
•
Last event indicator register (LEIR)
•
Receive and transmit error counter (RTEC)
•
Bit timing register (BTR)
■ Message Buffer Control Registers
The message buffer control registers are the following 14 registers:
•
Message buffer valid register (BVALR)
•
IDE register (IDER)
•
Transmission request register (TREQR)
•
Transmission RTR register (TRTRR)
•
Remote frame receiving wait register (RFWTR)
•
Transmission cancel register (TCANR)
•
Transmission complete register (TCR)
•
Transmission interrupt enable register (TIER)
•
Reception complete register (RCR)
•
Remote request receiving register (RRTRR)
•
Receive overrun register (ROVRR)
•
Reception interrupt enable register (RIER)
•
Acceptance mask select register (AMSR)
•
Acceptance mask registers 0 and 1 (AMR0 and AMR1)
■ Message Buffers
The message buffers are the following three registers:
•
ID register x (x = 0 to 15) (IDRx)
•
DLC register x (x = 0 to 15) (DLCRx)
•
Data register x (x = 0 to 15) (DTRx)
353
CHAPTER 21 CAN CONTROLLER
21.6.1 Control Status Register (CSR)
The lower 8bits with the control status register (CSR) is prohibited from executing any
bit manipulation instructions (Read-Modify-Write instructions).
Only in the case of HALT bits unchanged, it is possible to use any bit manipulation
instructions without problems (initialization of the macro instructions etc.).
■ Control Status Register (CSR)
Figure 21.6-1 shows the bit configuration of the control status register (CSR).
Figure 21.6-1 Control Status Register (CSR)
Address: 003B01H(CAN0)
003D01H(CAN1)
Read/write→
Initial value→
15
TS
(R)
(0)
14
RS
(R)
(0)
13
⎯
(-)
(-)
12
⎯
(-)
(-)
11
⎯
(-)
(-)
10
NT
(R/W)
(0)
Address: 003B00H(CAN0)
003D00H(CAN1)
Read/write→
Initial value→
7
TOE
(R/W)
(0)
6
⎯
(-)
(-)
5
⎯
(-)
(-)
4
⎯
(-)
(-)
3
⎯
(-)
(-)
2
NIE
(R/W)
(0)
9
NS1
(R)
(0)
1
Reserved
(W)
(0)
8
NS0
(R)
(0)
←Bit No.
CSR
0
←Bit No.
HALT
CSR
(R/W)
(1)
[bit15] TS: Transmit status bit
This bit indicates whether a message is being transmitted.
0: Message not being transmitted
1: Message being transmitted
This bit is "0" even while error and overload frames are transmitted.
[bit14] RS: Receive status bit
This bit indicates whether a message is being received.
0: Message not being received
1: Message being received
While a message is on the bus, this bit becomes "1". Therefore, this bit is also "1" while a
message is being transmitted. This bit does not necessarily indicates whether a receiving
message passes through the acceptance filter.
As a result, when this bit is "0", it implies that the bus operation is stopped (HALT = 0); the bus
is in the intermission/bus idle or a error/overload frame is on the bus.
[bit10] NT: Node status transition flag
If the node status is changed to increment, or from Bus Off to Error Active, this bit is set to "1".
In other words, the NT bit is set to "1" if the node status is changed from Error Active (00B) to
Warning (01B), from Warning (01B) to Error Passive (10B), from Error Passive (10B) to Bus Off
(11B), and from Bus Off (11B) to Error Active (00B). Numbers in parentheses indicate the
values of NS1 and NS0 bits.
When the node status transition interrupt enable bit (NIE) is "1", an interrupt is generated.
Writing "0" sets the NT bit to "0". Writing "1" to the NT bit is ignored. "1" is read when a Read
354
CHAPTER 21 CAN CONTROLLER
Modify Write instruction is performed.
[bit9 and bit8] NS1 and NS0: Node status bits 1 and 0
These bits indicate the current node status.
Table 21.6-1 Correspondence between NS1, NS0 and Node Status
NS1
NS0
Node Status
0
0
Error active
0
1
Warning (error active)
1
0
Error passive
1
1
Bus off
Note:
Warning (error active) is included in the error active in CAN Specification 2.0B for the node status,
however, indicates that the transmit error counter or receive error counter has exceeded 96.
The node status change diagram is shown in Figure 21.6-2.
Figure 21.6-2 Node Status Transition Diagram
Hardware reset
REC: Receive error counter
TEC: Transmit error counter
Error active
REC >
= 96
or
TEC >
= 96
After "0" has been written to the HALT bit
of the register (CSR), continuous 11-bit "H"
levels (recessive bits) are input 128 times
to the receive input pin (RX).
REC < 96
and
TEC < 96
REC >
= 128
or
TEC >
= 128
Warning
(Error active)
REC < 128
and
TEC < 128
Error passive
Bus off
TEC >
= 256
[bit7] TOE: Transmit output enable bit
Writing "1" to this bit switches from a general-purpose port pin to a transmit pin of the CAN
controller.
0: General-purpose port pin
1: Transmit pin of CAN controller
355
CHAPTER 21 CAN CONTROLLER
[bit2] NIE: Node status transition interrupt enable bit
This bit enables or disables a node status transition interrupt (when NT = 1).
0: Node status transition interrupt disabled
1: Node status transition interrupt enabled
[bit1] Reserved: Reserved bit
Always write "0" to this bit. The read value is always "0".
[bit0] HALT: Bus operation stop bit
This bit controls the bus halt. The halt state of the bus can be checked by reading this bit.
Reading this bit
0: Bus operation inprogress
1: Bus operation in stop state
Writing to this bit
0: Cancels bus operation stop
1: Sets bus operation stop
Note:
When write "0" to this bit during the node status is Bus Off, ensure that "1" is written to this bit.
Example program:
switch (IO_CANCTO.CSR.bit.NS)
{
case 0 : /∗error active ∗/
break;
case 1 : /∗warning ∗/
break;
case 2 : /∗error passive ∗/
break;
default : /∗bus off ∗/
for (i = 0; (i <= 500)&&(IO_CANCTO.CSR.bit.HALT == 0); i++) ;
IO_CANCTO.CSR.word = 0x0084; /∗HALT = 0 ∗/
break;
}
*: The variable "i" is used for fail-safe.
356
CHAPTER 21 CAN CONTROLLER
21.6.2 Bus Operation Stop Bit (HALT = 1)
The bus operation stop bit sets or cancels stopping of bus operation, or indicates its
status.
■ Conditions for Setting Bus Operation Stop (HALT=1)
There are three conditions for setting bus operation stop (HALT = 1):
•
After hardware reset
•
When node status changed to bus off
•
By writing "1" to HALT
Notes:
• The bus operation should be stopped by writing "1" to HALT before the F2MC-16LX is changed in
low-power consumption mode (stop mode, clock mode, and hardware stand-by mode).
If transmission is in progress when "1" is written to HALT, the bus operation is stopped (HALT =
1) after transmission is terminated. If reception is in progress when "1" is written to HALT, the bus
operation is stopped immediately (HALT = 1). If received messages are being stored in the
message buffer (x), the bus operation is stopped (HALT = 1) after storing the messages.
• To check whether the bus operation has stopped, always read the HALT bit.
■ Conditions for Canceling Bus Operation Stop (HALT = 0)
By writing "0" to HALT
Notes:
• Canceling the bus operation stop after hardware reset or by writing "1" to HALT as above
conditions is performed after "0" is written to HALT and continuous 11-bit "H" levels (recessive
bits) have been input to the receive input pin (RX) (HALT = 0).
• Canceling the bus operation stop when the node status is changed to bus off as above conditions
is performed after "0" is written to HALT and continuous 11-bit "H" levels (recessive bits) have
been input 128 times to the receive input pin (RX) (HALT = 0). Then, the values of both transmit
and receive error counters reach "0" and the node status is changed to error active.
• When write "0" to HALT during the node status is Bus Off, ensure that "1" is written to this bit.
357
CHAPTER 21 CAN CONTROLLER
■ State During Bus Operation Stop (HALT = 1)
•
The bus does not perform any operation, such as transmission and reception.
•
The transmit output pin (TX) outputs "H" level (recessive bit).
•
The values of other registers and error counters are not changed.
Note:
The bit timing register (BTR) should be set during bus operation stop (HALT = 1).
358
CHAPTER 21 CAN CONTROLLER
21.6.3 Last Event Indicator Register (LEIR)
This register indicates the last event.
The NTE, TCE, and RCE bits are exclusive. When the corresponding bit of the last event
is set to "1", other bits are set to "0"s.
■ Last Event Indicator Register (LEIR)
Figure 21.6-3 shows the bit configuration of the last event indicator register (LEIR).
Figure 21.6-3 Last Event Indicator Register (LEIR)
Address: 003B02H(CAN0)
003D02H(CAN1)
Read/write→
Initial value→
7
NTE
(R/W)
(0)
6
TCE
(R/W)
(0)
5
RCE
(R/W)
(0)
4
⎯
(-)
(-)
3
MBP3
(R/W)
(0)
2
MBP2
(R/W)
(0)
1
MBP1
(R/W)
(0)
0
←Bit No.
MBP0
LEIR
(R/W)
(0)
[bit7] NTE: Node status transition event bit
• When this bit is "1", node status transition is the last event.
• This bit is set to "1" at the same time the NT bit of the control status register (CSR) is set.
• This bit is also set to "1" irrespective of the setting of the node status transition interrupt
enable bit (NIE) of CSR.
• Writing "0" to this bit sets the NT bit to "0". Writing "1" to this bit is ignored.
• "1" is read when a Read Modify Write instruction is executed.
[bit6] TCE: Transmit completion event bit
When this bit is "1", it indicates that transmit completion is the last event.
This bit is set to "1" at the same time as any one of the bits of the transmit completion register
(TCR). This bit is also set to "1", irrespective of the settings of the bits of the transmit interrupt
enable register (TIER).
Writing "0" sets this bit to "0". Writing "1" to this bit is ignored.
"1" is read when a Read Modify Write instruction is performed.
When this bit is set to "1", the MBP3 to MBP0 bits are used to indicate the message buffer
number completing the transmit operation.
[bit5] RCE: Receive completion event bit
When this bit is "1", it indicates that receive completion is the last event.
This bit is set to "1" at the same time as any one of the bits of the receive complete register
(RCR). This bit is also set to "1" irrespective of the settings of the bits of the receive interrupt
enable register (RIER).
Writing "0" sets this bit to "0". Writing "1" to this bit is ignored.
"1" is read when a Read Modify Write instruction is performed.
When this bit is set to "1", the MBP3 to MBP0 bits are used to indicate the message buffer
number completing the receive operation.
359
CHAPTER 21 CAN CONTROLLER
[bit3 to bit0] MBP3 to MBP0: Message buffer pointer bits
When the TCE or RCE bit is set to "1", these bits indicate the corresponding numbers of the
message buffers (0 to 15). If the NTE bit is set to "1", these bits have no meaning.
Writing "0" sets these bits to "0"s. Writing "1" to these bits is ignored.
"1"s are read when a Read Modify Write instruction is performed.
If LEIR is accessed within an CAN interrupt handler, the event causing the interrupt is not
necessarily the same as indicated by LEIR. In the time from interrupt request to the LEIR
access in the interrupt handler there may occur other CAN events.
360
CHAPTER 21 CAN CONTROLLER
21.6.4 Receive and Transmit Error Counters (RTEC)
The receive and transmit error counters indicate the counts for transmission errors and
reception errors defined in the CAN specifications. These registers can only be read.
■ Receive and Transmit Error Counters (RTEC)
Figure 21.6-4 shows the bit configuration of the receive and transmit error counters (RTEC).
Figure 21.6-4 Receive and Transmit Error Counters (RTEC)
Address: 003B05H(CAN0)
003D05H(CAN1)
Read/write→
Initial value→
15
TEC7
(R)
(0)
14
TEC6
(R)
(0)
13
TEC5
(R)
(0)
12
TEC4
(R)
(0)
11
TEC3
(R)
(0)
10
TEC2
(R)
(0)
9
TEC1
(R)
(0)
8
←Bit No.
TEC0
RTEC
(R)
(0)
Address: 003B04H(CAN0)
003D04H(CAN1)
Read/write→
Initial value→
7
REC7
(R)
(0)
6
REC6
(R)
(0)
5
REC5
(R)
(0)
4
REC4
(R)
(0)
3
REC3
(R)
(0)
2
REC2
(R)
(0)
1
REC1
(R)
(0)
0
←Bit No.
REC0
RTEC
(R)
(0)
[bit15 to bit8] TEC7 to TEC0: Transmit error counter
These are transmit error counters.
TEC7 to TEC0 values indicate 0 to 7 when the counter value is more than 256, and the
subsequent increment is not counted for counter value. In this case, Bus Off is indicated for
the node status (NS1 and NS0 of control status register CSR = 11B).
[bit7 to bit0] REC7 to REC0: Receive error counter
These are receive error counters.
REC7 to REC0 values indicate 0 to 7 when the counter value is more than 256, and the
subsequent increment is not counted for counter value. In this case, Error Passive is indicated
for the node status (NS1 and NS0 of control status register CSR = 10B).
361
CHAPTER 21 CAN CONTROLLER
21.6.5 Bit Timing Register (BTR)
Bit timing register (BTR) sets the prescaler and bit timing.
■ Bit Timing Register (BTR)
Figure 21.6-5 shows the bit configuration of the bit timing register (BTR).
Figure 21.6-5 Bit Timing Register (BTR)
Address: 003B07H(CAN0)
003D07H(CAN1)
Read/write→
Initial value→
15
⎯
(-)
(-)
14
TS2.2
(R/W)
(1)
13
TS2.1
(R/W)
(1)
12
TS2.0
(R/W)
(1)
11
TS1.3
(R/W)
(1)
10
TS1.2
(R/W)
(1)
9
TS1.1
(R/W)
(1)
8
←Bit No.
TS1.0
BTR
(R/W)
(1)
Address: 003B06H(CAN0)
003D06H(CAN1)
Read/write→
Initial value→
7
RSJ1
(R/W)
(1)
6
RSJ0
(R/W)
(1)
5
PSC5
(R/W)
(1)
4
PSC4
(R/W)
(1)
3
PSC3
(R/W)
(1)
2
PSC2
(R/W)
(1)
1
PSC1
(R/W)
(1)
0
←Bit No.
PSC0
BTR
(R/W)
(1)
Note:
This register should be set during bus operation stop (HALT = 1).
[bit14 to bit12] TS2.2 to TS2.0: Time segment 2 setting bit 2 to bit 0
These bits define the number of the time quanta (TQ’s) by dividing [(TS2.2 to TS2.0)+1] for the
time segment 2 (TSEG2). The time segment 2 is equal to the phase buffer segment 2
(PHASE_SEG2) in the CAN specification.
[bit11 to bit8] TS1.3 to TS1.0: Time segment 1 setting bit 3 to bit 0
These bits define the number of the time quanta (TQ’s) by dividing [(TS1.3 to TS1.0)+1] for the
time segment 1 (TSEG1). The time segment 1 is equal to the propagation segment
(PROP_SEG) + phase buffer segment 1 (PHASE_SEG1) in the CAN specification.
[bit7 and bit6] RSJ1 and RSJ0: Resynchronization jump width setting bit 1 and bit 0
These bits define the number of the time quanta (TQ’s) by dividing [(RSJ1 to RSJ0)+1] for the
resynchronization jump width.
[bit5 to bit0] PSC5 to PSC0: Prescaler setting bit 5 to bit 0
These bits define the time quanta (TQ) by dividing the frequency [(PSC5 to PSC0)+1] of the
CAN controller.
362
CHAPTER 21 CAN CONTROLLER
The bit time segments defined in the CAN specification, and the CAN controller are shown in
Figure 21.6-6 and Figure 21.6-7 respectively.
Figure 21.6-6 Bit Time Segment in CAN Specification
Nominal bit time
SYNC_SEG
PROP_SEG
PHASE_SEG1 PHASE_SEG2
Sample point
Figure 21.6-7 Bit Time Segment in CAN Controller
Nominal bit time
SYNC_SEG
TSEG1
TSEG2
Sample point
The relationship between PSC = PSC5 to PSC0, TS1 = TS1.3 to TS1.0, TS2 = TS2.2 to TS2.0,
and RSJ = RSJ1 and RSJ0 when the input clock (CLK), time quanta (TQ), bit time (BT),
synchronous segment (SYNC_SEG), time segment 1 and 2 (TSEG1 and TSEG2), and
resynchronization jump width [(RSJ1 and RSJ0) +1] frequency division is shown below.
The input clock is built-in to the machine clock.
TQ
BT
= (PSC + 1) × CLK
= SYNC_SEG + TSEG1 + TSEG2
= (1 + (TS1 + 1) + (TS2 +1)) × TQ
= (3 + TS1 +TS2) × TQ
RSJW = (RSJ + 1) × TQ
For correct operation, the following conditions should be met.
• Device with "G" suffix:
For 1 <
= PSC <
= 63:
>
TSEG1 = 2TQ
TSEG1 >
= RSJW
TSEG2 >
= 2TQ
TSEG2 >
= RSJW
For PSC = 0:
TSEG1 >
= 5TQ
TSEG2 >
= 2TQ
TSEG2 >
= RSJW
• Device without "G" suffix:
For 1 <
= PSC <
= 63:
TSEG1 >
= RSJW
TSEG2 >
= RSJW + 2TQ
For PSC = 0:
TSEG1 >
= 5TQ
TSEG2 >
= RSJW + 2TQ
In order to meet the bit timing settings defined in the CAN specification, the other conditions, e.g.
delay time, should be considered.
363
CHAPTER 21 CAN CONTROLLER
21.6.6 Message Buffer Valid Register (BVALR)
Message buffer valid register (BVALR) stores the validity of the message buffers or
displays their state.
■ Message Buffer Valid Register (BVALR)
Figure 21.6-8 shows the bit configuration of the message buffer valid register (BVALR).
Figure 21.6-8 Message Buffer Valid Register (BVALR)
Address: 000071H(CAN0)
000081H(CAN1)
Read/write→
Initial value→
Address: 000070H(CAN0)
000080H(CAN1)
Read/write→
Initial value→
15
14
13
12
11
10
9
8
←Bit No.
BVAL15 BVAL14 BVAL13 BVAL12 BVAL11 BVAL10 BVAL9 BVAL8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
6
5
4
3
2
1
0
BVALR
←Bit No.
BVAL7 BVAL6 BVAL5 BVAL4 BVAL3 BVAL2 BVAL1 BVAL0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
BVALR
0: Message buffer (x) invalid
1: Message buffer (x) valid
If the message buffer (x) is set to invalid, it will not transmit or receive messages.
If the buffer is set to invalid during transmission operating, it becomes invalid (BVALx = 0) after
the transmission is completed or terminated by an error.
If the buffer is set to invalid during reception operating, it immediately becomes invalid (BVALx =
0). If received messages are stored in a message buffer (x), the message buffer (x) is invalid after
storing the messages.
Notes:
• x indicates a message buffer number (x = 0 to 15).
• When invaliding a message buffer (x) by writing "0" to a bit (BVALx), execution of a bit
manipulation instruction is prohibited until the bit is set to "0".
• To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while CAN Controller is
participating in CAN communication (the read value of the CSR: HALT bit is "0" and CAN
Controller is ready to receive or transmit messages), follow the cautions in Section "21.14
Precautions when Using CAN Controller".
364
CHAPTER 21 CAN CONTROLLER
21.6.7 IDE register (IDER)
This register stores the frame format used by the message buffers (x) during
transmission/reception.
■ IDE Register (IDER)
Figure 21.6-9 shows the bit configuration of the IDE register (IDER).
Figure 21.6-9 IDE Register (IDER)
Address: 003B09H(CAN0)
003D09H(CAN1)
Read/write→
Initial value→
Address: 003B08H(CAN0)
003D08H(CAN1)
Read/write→
Initial value→
15
14
13
12
11
10
9
8
IDE15
(R/W)
(X)
IDE14
(R/W)
(X)
IDE13
(R/W)
(X)
IDE12
(R/W)
(X)
IDE11
(R/W)
(X)
IDE10
(R/W)
(X)
IDE9
(R/W)
(X)
IDE8
(R/W)
(X)
7
6
5
4
3
2
1
0
IDE7
(R/W)
(X)
IDE6
(R/W)
(X)
IDE5
(R/W)
(X)
IDE4
(R/W)
(X)
IDE3
(R/W)
(X)
IDE2
(R/W)
(X)
IDE1
(R/W)
(X)
IDE0
(R/W)
(X)
←Bit No.
IDER
←Bit No.
IDER
0: The standard frame format (ID11 bit) is used for the message buffer (x).
1: The extended frame format (ID29 bit) is used for the message buffer (x).
Notes:
• This register should be set when the message buffer (x) is invalid (BVALx of the message buffer
valid register (BVALR) = 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary
received messages to be stored.
• To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while CAN Controller is
participating in CAN communication (the read value of the CSR: HALT bit is "0" and CAN
Controller is ready to receive or transmit messages), follow the cautions in Section "21.14
Precautions when Using CAN Controller".
365
CHAPTER 21 CAN CONTROLLER
21.6.8 Transmission Request Register (TREQR)
Transmission request register (TREQR) stores transmission requests to the message
buffers (x) or displays their state.
■ Transmission Request Register (TREQR)
Figure 21.6-10 shows the bit configuration of the transmission request register (TREQR).
Figure 21.6-10 Transmission Request Register (TREQR)
Address: 000073H(CAN0)
000083H(CAN1)
Read/write→
Initial value→
Address: 000072H(CAN0)
000082H(CAN1)
Read/write→
Initial value→
15
14
13
12
11
10
9
8
TREQ15 TREQ14 TREQ13 TREQ12 TREQ11 TREQ10 TREQ9 TREQ8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
6
5
4
3
2
1
0
TREQ7 TREQ6 TREQ5 TREQ4 TREQ3 TREQ2 TREQ1 TREQ0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
←Bit No.
TREQR
←Bit No.
TREQR
(R/W)
(0)
When "1" is written to TREQx, transmission to the message buffer (x) starts. If RFWTx of the
remote frame receiving wait register (RFWTR)*1 is "0", transmission starts immediately. However,
if RFWTx = 1, transmission starts after waiting until a remote frame is received (RRTRx of the
remote request receiving register (RRTRR)*1 becomes "1"). Transmission starts*2 immediately
even when RFWTx = 1, if RRTRx is already "1" when "1" is written to TREQx.
*1: For RFWTR and TRTRR, see "21.6.9 Transmission RTR Register (TRTRR)" and "21.6.10
Remote Frame Receiving Wait Register (RFWTR)".
*2: For cancellation of transmission, see "21.6.11 Transmission Cancel Register (TCANR)" and
"21.6.12 Transmission Complete Register (TCR)".
Writing "0" to TREQx is ignored.
"0" is read when a Read Modify Write instruction is performed.
If clearing (to "0") at completion of the transmit operation and setting by writing "1" are concurrent,
clearing is preferred.
If "1" is written to more than one bit, transmission is performed, starting with the lower-numbered
message buffer (x).
TREQx is "1" while transmission is pending, and becomes "0" when transmission is completed or
canceled.
366
CHAPTER 21 CAN CONTROLLER
21.6.9 Transmission RTR Register (TRTRR)
This register stores the RTR (Remote Transmission Request) bits for the message
buffers (x).
■ Transmission RTR Register (TRTRR)
Figure 21.6-11 shows the bit configuration of the transmission RTR register (TRTRR).
Figure 21.6-11 Transmission RTR Register (TRTRR)
Address: 003B0BH(CAN0)
003D0BH(CAN1)
Read/write→
Initial value→
15
14
13
12
11
10
9
TRTR15 TRTR14 TRTR13 TRTR12 TRTR11 TRTR10 TRTR9
8
TRTR8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Address: 003B0AH(CAN0)
003D0AH(CAN1)
7
6
5
4
3
2
1
0
TRTR7
TRTR6
TRTR5
TRTR4
TRTR3
TRTR2
TRTR1
TRTR0
Read/write→
Initial value→
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
←Bit No.
TRTRR
←Bit No.
TRTRR
0: Data frame is transmitted
1: Remote frame is transmitted
367
CHAPTER 21 CAN CONTROLLER
21.6.10
Remote Frame Receiving Wait Register (RFWTR)
Remote frame receiving wait register (RFWTR) stores the conditions for starting
transmission when a request for data frame transmission is set (TREQx of the
transmission request register (TREQR) is "1" and TRTRx of the transmitting RTR
register (TRTRR) is "0").
0: Transmission starts immediately
1: Transmission starts after waiting until remote frame received (RRTRx of remote
request receiving register (RRTRR) becomes "1")
■ Remote Frame Receiving Wait Register (RFWTR)
Figure 21.6-12 shows the bit configuration of the remote frame receiving wait register (RFWTR).
Figure 21.6-12 Remote Frame Receiving Wait Register (RFWTR)
Address: 003B0DH(CAN0)
003D0DH(CAN1)
Read/write→
Initial value→
Address: 003B0CH(CAN0)
003D0CH(CAN1)
Read/write→
Initial value→
15
14
13
12
11
10
9
8
RFWT15 RFWT14 RFWT13 RFWT12 RFWT11 RFWT10 RFWT9 RFWT8
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
6
5
4
3
2
1
0
RFWT7 RFWT6 RFWT5 RFWT4 RFWT3 RFWT2 RFWT1 RFWT0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
←Bit No.
RFWTR
←Bit No.
RFWTR
(R/W)
(X)
Notes:
• Transmission starts immediately if RRTRx is already "1" when a request for transmission is set.
• For remote frame transmission, do not set RFWTx to "1".
368
CHAPTER 21 CAN CONTROLLER
21.6.11
Transmission Cancel Register (TCANR)
When "1" is written to TCANx, this register cancels a pending request for transmission
to the message buffer (x).
At completion of cancellation, TREQx of the transmission request register (TREQR)
becomes "0". Writing "0" to TCANx is ignored.
This is a write-only register and its read value is always "0".
■ Transmission Cancel Register (TCANR)
Figure 21.6-13 shows the bit configuration of the transmission cancel register (TCANR).
Figure 21.6-13 Transmission Cancel Register (TCANR)
Address: 000075H(CAN0)
000085H(CAN1)
Read/write→
Initial value→
Address: 000074H(CAN0)
000084H(CAN1)
Read/write→
Initial value→
15
14
13
12
11
10
9
TCAN15 TCAN14 TCAN13 TCAN12 TCAN11 TCAN10 TCAN9
8
TCAN8
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
7
6
5
4
3
2
1
0
TCAN7
TCAN6
TCAN5
TCAN4
TCAN3
TCAN2
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
TCAN1 TCAN0
(W)
(0)
←Bit No.
TCANR
←Bit No.
TCANR
(W)
(0)
369
CHAPTER 21 CAN CONTROLLER
21.6.12
Transmission Complete Register (TCR)
At completion of transmission by the message buffer (x), the corresponding TCx
becomes "1".
If TIEx of the transmission complete interrupt enable register (TIER) is "1", an interrupt
occurs.
■ Transmission Complete Register (TCR)
Figure 21.6-14 shows the bit configuration of the transmission complete register (TCR).
Figure 21.6-14 Transmission Complete Register (TCR)
Address: 000077H(CAN0)
000087H(CAN1)
Read/write→
Initial value→
Address: 000076H(CAN0)
000086H(CAN1)
Read/write→
Initial value→
15
14
13
12
11
10
9
8
TC15
(R/W)
(0)
TC14
(R/W)
(0)
TC13
(R/W)
(0)
TC12
(R/W)
(0)
TC11
(R/W)
(0)
TC10
(R/W)
(0)
TC9
(R/W)
(0)
TC8
(R/W)
(0)
7
6
5
4
3
2
1
0
TC7
(R/W)
(0)
TC6
(R/W)
(0)
TC5
(R/W)
(0)
TC4
(R/W)
(0)
TC3
(R/W)
(0)
TC2
(R/W)
(0)
TC1
(R/W)
(0)
TC0
(R/W)
(0)
←Bit No.
TCR
←Bit No.
TCR
❍ Conditions for TCx = 0
•
Write "0" to TCx.
•
Write "1" to TREQx of the transmission request register (TREQR).
After the completion of transmission, write "0" to TCx sets it to "0". Writing "1" to TCx is ignored.
"1" is read when a Read Modify Write instruction is performed.
Note:
If setting to "1" by completion of the transmit operation and clearing by writing "0" occur at the same
time, the setting of "1" is prior.
370
CHAPTER 21 CAN CONTROLLER
21.6.13
Transmission Interrupt Enable Register (TIER)
This register enables or disables the transmission interrupt by the message buffer (x).
The transmission interrupt is generated at transmission completion (when TCx of the
transmission complete register (TCR) is "1").
■ Transmission Interrupt Enable Register (TIER)
Figure 21.6-15 shows the bit configuration of the transmission interrupt register (TIER).
Figure 21.6-15 Transmission Interrupt Register (TIER)
Address: 003B0FH(CAN0)
003D0FH(CAN1)
Read/write→
Initial value→
Address: 003B0EH(CAN0)
003D0EH(CAN1)
Read/write→
Initial value→
15
14
13
12
11
10
9
8
TIE15
(R/W)
(0)
TIE14
(R/W)
(0)
TIE13
(R/W)
(0)
TIE12
(R/W)
(0)
TIE11
(R/W)
(0)
TIE10
(R/W)
(0)
TIE9
(R/W)
(0)
TIE8
(R/W)
(0)
7
6
5
4
3
2
1
0
TIE7
(R/W)
(0)
TIE6
(R/W)
(0)
TIE5
(R/W)
(0)
TIE4
(R/W)
(0)
TIE3
(R/W)
(0)
TIE2
(R/W)
(0)
TIE1
(R/W)
(0)
TIE0
(R/W)
(0)
←Bit No.
TIER
←Bit No.
TIER
0: Transmission interrupt disabled
1: Transmission interrupt enabled
371
CHAPTER 21 CAN CONTROLLER
21.6.14
Reception Complete Register (RCR)
At completion of storing received message in the message buffer (x), RCx becomes "1".
If RIEx of the reception complete interrupt enable register (RIER) is "1", an interrupt
occurs.
■ Reception Complete Register (RCR)
Figure 21.6-16 shows the bit configuration of the reception complete register (RCR).
Figure 21.6-16 Reception Complete Register (RCR)
Address: 000079H(CAN0)
000089H(CAN1)
Read/write→
Initial value→
Address: 000078H(CAN0)
000088H(CAN1)
Read/write→
Initial value→
15
14
13
12
11
10
9
8
RC15
(R/W)
(0)
RC14
(R/W)
(0)
RC13
(R/W)
(0)
RC12
(R/W)
(0)
RC11
(R/W)
(0)
RC10
(R/W)
(0)
RC9
(R/W)
(0)
RC8
(R/W)
(0)
7
6
5
4
3
2
1
0
RC7
(R/W)
(0)
RC6
(R/W)
(0)
RC5
(R/W)
(0)
RC4
(R/W)
(0)
RC3
(R/W)
(0)
RC2
(R/W)
(0)
RC1
(R/W)
(0)
RC0
(R/W)
(0)
←Bit No.
RCR
←Bit No.
RCR
❍ Conditions for RCx = 0
• Write "0" to RCx.
• After completion of handling received message, write "0" to RCx to set it to "0". Writing "1" to
RCx is ignored.
"1" is read when a Read Modify Write instruction is performed.
Note:
If setting to "1" by completion of the receive operation and clearing by writing "0" occur at the
same time, the setting to "1" is prior.
372
CHAPTER 21 CAN CONTROLLER
21.6.15
Remote Request Receiving Register (RRTRR)
After a remote frame is stored in the message buffer (x), RRTRx becomes "1" (at the
same time as RCx setting to "1").
■ Remote Request Receiving Register (RRTRR)
Figure 21.6-17 shows the bit configuration of the remote request receiving register (RRTRR).
Figure 21.6-17 Remote Request Receiving Register (RRTRR)
Address: 00007BH(CAN0)
00008BH(CAN1)
Read/write→
Initial value→
Address: 00007AH(CAN0)
00008AH(CAN1)
Read/write→
Initial value→
15
14
13
12
11
10
9
8
RRTR15 RRTR14 RRTR13 RRTR12 RRTR11 RRTR10 RRTR9 RRTR8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
6
5
4
3
2
1
0
RRTR7 RRTR6 RRTR5 RRTR4 RRTR3 RRTR2 RRTR1 RRTR0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
←Bit No.
RRTRR
←Bit No.
RRTRR
❍ Conditions for RRTRx = 0
•
Write "0" to RRTRx.
•
After a received data frame is stored in the message buffer (x) (at the same time as RCx
setting to "1").
•
Transmission by the message buffer (x) is completed (TCx of the transmission complete
register (TCR) is "1").
Writing "1" to RRTRx is ignored.
"1" is read when a Read Modify Write instruction is performed.
Note:
If setting to "1" by completion of the receive operation and clearing by writing "0" occur at the same
time, the setting to "1" is prior.
373
CHAPTER 21 CAN CONTROLLER
21.6.16
Receive Overrun Register (ROVRR)
If RCx of the reception complete register (RCR) has been already "1" when completing
storing of a received message in the message buffer (x), ROVRx becomes "1",
indicating that reception has overrun.
■ Receive Overrun Register (ROVRR)
Figure 21.6-18 shows the bit configuration of the receive overrun register (ROVRR).
Figure 21.6-18 Receive Overrun Register (ROVRR)
Address: 00007DH(CAN0)
00008DH(CAN1)
Read/write→
Initial value→
Address: 00007CH(CAN0)
00008CH(CAN1)
Read/write→
Initial value→
15
14
13
12
11
10
9
8
ROVR15 ROVR14 ROVR13 ROVR12 ROVR11 ROVR10 ROVR9 ROVR8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
6
5
4
3
2
1
0
ROVR7 ROVR6 ROVR5 ROVR4 ROVR3 ROVR2 ROVR1 ROVR0
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
←Bit No.
ROVRR
←Bit No.
ROVRR
Writing "0" to ROVRx results in ROVRx = 0. Writing "1" to ROVRx is ignored. After checking that
reception has overrun, writing "0" to ROVRx clears it to "0".
"1" is read when a Read Modify Write instruction is performed.
Note:
If setting to "1" by completion of the receive operation and clearing by writing "0" occur at the same
time, the setting to "1" is prior.
374
CHAPTER 21 CAN CONTROLLER
21.6.17
Reception Interrupt Enable Register (RIER)
Reception interrupt enable register (RIER) enables or disables the reception interrupt by
the message buffer (x).
The reception interrupt is generated at reception completion (when RCx of the reception
completion register (RCR) is "1").
■ Reception Interrupt Enable Register (RIER)
Figure 21.6-19 shows the bit configuration of the reception interrupt enable register (RIER).
Figure 21.6-19 Reception Interrupt Enable Register (RIER)
Address: 00007FH(CAN0)
00008FH(CAN1)
Read/write→
Initial value→
Address: 00007EH(CAN0)
00008EH(CAN1)
Read/write→
Initial value→
15
14
13
12
11
10
9
8
RIE15
(R/W)
(0)
RIE14
(R/W)
(0)
RIE13
(R/W)
(0)
RIE12
(R/W)
(0)
RIE11
(R/W)
(0)
RIE10
(R/W)
(0)
RIE9
(R/W)
(0)
RIE8
(R/W)
(0)
7
6
5
4
3
2
1
0
RIE7
(R/W)
(0)
RIE6
(R/W)
(0)
RIE5
(R/W)
(0)
RIE4
(R/W)
(0)
RIE3
(R/W)
(0)
RIE2
(R/W)
(0)
RIE1
(R/W)
(0)
RIE0
(R/W)
(0)
←Bit No.
RIER
←Bit No.
RIER
0: Reception interrupt disabled
1: Reception interrupt enabled
375
CHAPTER 21 CAN CONTROLLER
21.6.18
Acceptance Mask Select Register (AMSR)
This register selects masks (acceptance mask) for comparison between the received
message ID’s and the message buffer ID’s.
■ Acceptance Mask Select Register (AMSR)
Figure 21.6-20 shows the bit configuration of the acceptance mask select register (AMSR).
Figure 21.6-20 Acceptance Mask Select Register (AMSR)
Type1
Address: 003B10H(CAN0)
003D10H(CAN1)
Read/write→
Initial value→
7
AMS
3.1
(R/W)
(X)
6
AMS
3.0
(R/W)
(X)
5
AMS
2.1
(R/W)
(X)
4
AMS
2.0
(R/W)
(X)
3
AMS
1.1
(R/W)
(X)
2
AMS
1.0
(R/W)
(X)
1
AMS
0.1
(R/W)
(X)
0
←Bit No.
AMS
AMSR BYTE0
0.0
(R/W)
(X)
Type2
Address: 003B11H(CAN0)
003D11H(CAN1)
Read/write→
Initial value→
15
AMS
7.1
(R/W)
(X)
14
AMS
7.0
(R/W)
(X)
13
AMS
6.1
(R/W)
(X)
12
AMS
6.0
(R/W)
(X)
11
AMS
5.1
(R/W)
(X)
10
AMS
5.0
(R/W)
(X)
9
AMS
4.1
(R/W)
(X)
8
←Bit No.
AMS
AMSR BYTE1
4.0
(R/W)
(X)
Type3
Address: 003B12H(CAN0)
003D12H(CAN1)
Read/write→
Initial value→
7
AMS
11.1
(R/W)
(X)
6
AMS
11.0
(R/W)
(X)
5
AMS
10.1
(R/W)
(X)
4
AMS
10.0
(R/W)
(X)
3
AMS
9.1
(R/W)
(X)
2
AMS
9.0
(R/W)
(X)
1
AMS
8.1
(R/W)
(X)
←Bit No.
0
AMS
AMSR BYTE2
8.0
(R/W)
(X)
Type4
Address: 003B13H(CAN0)
003D13H(CAN1)
Read/write→
Initial value→
15
AMS
15.1
(R/W)
(X)
14
AMS
15.0
(R/W)
(X)
13
AMS
14.1
(R/W)
(X)
12
AMS
14.0
(R/W)
(X)
11
AMS
13.1
(R/W)
(X)
10
AMS
13.0
(R/W)
(X)
9
AMS
12.1
(R/W)
(X)
8
←Bit No.
AMS
AMSR BYTE3
12.0
(R/W)
(X)
Table 21.6-2 Selection of Acceptance Mask
376
AMSx.1
AMSx.0
Acceptance Mask
0
0
Full-bit comparison
0
1
Full-bit mask
1
0
Acceptance mask register 0 (AMR0)
1
1
Acceptance mask register 1 (AMR1)
CHAPTER 21 CAN CONTROLLER
Notes:
• AMSx.1 and AMSx.0 should be set when the message buffer (x) is invalid (BVALx of the message
buffer valid register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause
unnecessary received messages to be stored
• To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while CAN Controller is
participating in CAN communication (the read value of the CSR: HALT bit is "0" and CAN
Controller is ready to receive or transmit messages), follow the cautions in Section "21.14
Precautions when Using CAN Controller".
377
CHAPTER 21 CAN CONTROLLER
21.6.19
Acceptance Mask Registers 0/1 (AMR0/AMR1)
There are two acceptance mask registers, AMR0 and AMR1, both of which are available
either in the standard frame format or extended frame format.
AM28 to AM18 (11 bits) are used for acceptance masks in the standard frame format
and AM28 to AM0 (29 bits) are used for acceptance masks in the extended format.
■ Acceptance Mask Registers 0/1 (AMR0/AMR1)
Figure 21.6-21 shows the bit configuration of the acceptance mask registers 0/1 (AMR0/AMR1).
Figure 21.6-21 Acceptance Mask Registers 0/1 (AMR0/AMR1)
Address: 003B14H(CAN0)
003D14H(CAN1)
Read/write→
Initial value→
7
AM28
(R/W)
(X)
6
AM27
(R/W)
(X)
5
AM26
(R/W)
(X)
4
AM25
(R/W)
(X)
3
AM24
(R/W)
(X)
2
AM23
(R/W)
(X)
1
AM22
(R/W)
(X)
←Bit No.
0
AM21
AMR0 BYTE0
(R/W)
(X)
Address: 003B15H(CAN0)
003D15H(CAN1)
Read/write→
Initial value→
15
AM20
(R/W)
(X)
14
AM19
(R/W)
(X)
13
AM18
(R/W)
(X)
12
AM17
(R/W)
(X)
11
AM16
(R/W)
(X)
10
AM15
(R/W)
(X)
9
AM14
(R/W)
(X)
8
←Bit No.
AM13
AMR0 BYTE1
(R/W)
(X)
Address: 003B16H(CAN0)
003D16H(CAN1)
Read/write→
Initial value→
7
AM12
(R/W)
(X)
6
AM11
(R/W)
(X)
5
AM10
(R/W)
(X)
4
AM9
(R/W)
(X)
3
AM8
(R/W)
(X)
2
AM7
(R/W)
(X)
1
AM6
(R/W)
(X)
0
←Bit No.
AM5
AMR0 BYTE2
(R/W)
(X)
Address: 003B17H(CAN0)
003D17H(CAN1)
Read/write→
Initial value→
15
AM4
(R/W)
(X)
14
AM3
(R/W)
(X)
13
AM2
(R/W)
(X)
12
AM1
(R/W)
(X)
11
AM0
(R/W)
(X)
10
⎯
(-)
(-)
9
⎯
(-)
(-)
Address: 003B18H(CAN0)
003D18H(CAN1)
Read/write→
Initial value→
7
AM28
(R/W)
(X)
6
AM27
(R/W)
(X)
5
AM26
(R/W)
(X)
4
AM25
(R/W)
(X)
3
AM24
(R/W)
(X)
2
AM23
(R/W)
(X)
1
AM22
(R/W)
(X)
0
←Bit No.
AM21
AMR1 BYTE0
(R/W)
(X)
Address: 003B19H(CAN0)
003D19H(CAN1)
Read/write→
Initial value→
15
AM20
(R/W)
(X)
14
AM19
(R/W)
(X)
13
AM18
(R/W)
(X)
12
AM17
(R/W)
(X)
11
AM16
(R/W)
(X)
10
AM15
(R/W)
(X)
9
AM14
(R/W)
(X)
←Bit No.
8
AM13
AMR1 BYTE1
(R/W)
(X)
Address: 003B1AH(CAN0)
7
AM12
(R/W)
(X)
6
AM11
(R/W)
(X)
5
AM10
(R/W)
(X)
4
AM9
(R/W)
(X)
3
AM8
(R/W)
(X)
2
AM7
(R/W)
(X)
1
AM6
(R/W)
(X)
0
←Bit No.
AM5
AMR1 BYTE2
(R/W)
(X)
15
AM4
(R/W)
(X)
14
AM3
(R/W)
(X)
13
AM2
(R/W)
(X)
12
AM1
(R/W)
(X)
11
AM0
(R/W)
(X)
10
⎯
(-)
(-)
9
⎯
(-)
(-)
003D1AH(CAN1)
Read/write→
Initial value→
Address: 003B1BH(CAN0)
003D1BH(CAN1)
Read/write→
Initial value→
378
8
⎯
(-)
(-)
8
⎯
(-)
(-)
←Bit No.
AMR0 BYTE3
←Bit No.
AMR1 BYTE3
CHAPTER 21 CAN CONTROLLER
❍ 0: Compare
Compare the bit of the acceptance code (ID register IDRx for comparing with the received
message ID) corresponding to this bit with the bit of the received message ID. If there is no
match, no message is received.
❍ 1: Mask
Mask the bit of the acceptance code ID register (IDRx) corresponding to this bit. No comparison
is made with the bit of the received message ID.
Notes:
• AMR0 and AMR1 should be set when all the message buffers (x) selecting AMR0 and AMR1 are
invalid (BVALx of the message buffer valid register (BVALR) is "0"). Setting when the buffers are
valid (BVALx = 1) may cause unnecessary received messages to be stored.
• To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while CAN Controller is
participating in CAN communication (the read value of the CSR: HALT bit is "0" and CAN
Controller is ready to receive or transmit messages), follow the cautions in Section "21.14
Precautions when Using CAN Controller".
379
CHAPTER 21 CAN CONTROLLER
21.6.20
Message Buffers
There are 16 message buffers. Message buffer x (x = 0 to 15) consists of an ID register
(IDRx), DLC register (DLCRx), and data register (DTRx).
■ Message Buffers
❍ The message buffer (x) is used both for transmission and reception.
❍ The lower-numbered message buffers are assigned higher priority.
•
At transmission, when a request for transmission is made to more than one message buffer,
transmission is performed, starting with the lowest-numbered message buffer (See "21.7
Transmission of CAN Controller").
•
At reception, when the received message ID passes through the acceptance filter (mechanism
for comparing the acceptance-masked ID of received message and message buffer) of more
than one message buffer, the received message is stored in the lowest-numbered message
buffer (See "21.8 Reception of CAN Controller").
❍ When the same acceptance filter is set in more than one message buffer, the message buffers can
be used as a multi-level message buffer. This provides allowance for receiving time.
(See "21.13 Setting Configuration of Multi-level Message Buffer").
Notes:
• A write operation to message buffers and general-purpose RAM areas should be performed in
words to even addresses only. A write operation in bytes causes undefined data to be written to
the upper byte at writing to the lower byte. Writing to the upper byte is ignored.
• When the BVALx bit of the message buffer valid register (BVALR) is "0" (Invalid), the message
buffers x (IDRx, DLCRx, and DTRx) can be used as general-purpose RAM. During the receive/
transmit operation of the CAN controller, the CAN Controller write/read to/from the message
buffers. If the CPU tries to write/read to/from the message buffers in this period, the CPU has to
wait a maximum time of 64 machine cycles. This is also same for general-purpose RAM
(Addresses 003A00H to 003C1FH and 003D00H to 003D1FH).
380
CHAPTER 21 CAN CONTROLLER
21.6.21
ID Register x (x = 0 to 15) (IDRx)
ID Register x (x = 0 to 15) (IDRx) is the ID register for message buffer (x).
■ ID Register x (x = 0 to 15) (IDRx)
Figure 21.6-22 shows the bit configuration of the ID register x (x = 0 to 15) (IDRx).
Figure 21.6-22 ID Register x (x = 0 to 15) (IDRx)
Address: 003A20H+4x(CAN0)
003C20H+4x(CAN1)
Read/write→
Initial value→
7
ID28
(R/W)
(X)
6
ID27
(R/W)
(X)
5
ID26
(R/W)
(X)
4
ID25
(R/W)
(X)
3
ID24
(R/W)
(X)
2
ID23
(R/W)
(X)
1
ID22
(R/W)
(X)
←Bit No.
0
ID21
IDRx BYTE0
(R/W)
(X)
Address: 003A21H+4x(CAN0)
003C21H+4x(CAN1)
Read/write→
Initial value→
15
ID20
(R/W)
(X)
14
ID19
(R/W)
(X)
13
ID18
(R/W)
(X)
12
ID17
(R/W)
(X)
11
ID16
(R/W)
(X)
10
ID15
(R/W)
(X)
9
ID14
(R/W)
(X)
←Bit No.
8
ID13
IDRx BYTE1
(R/W)
(X)
Address: 003A22H+4x(CAN0)
003C22H+4x(CAN1)
Read/write→
Initial value→
7
ID12
(R/W)
(X)
6
ID11
(R/W)
(X)
5
ID10
(R/W)
(X)
4
ID9
(R/W)
(X)
3
ID8
(R/W)
(X)
2
ID7
(R/W)
(X)
1
ID6
(R/W)
(X)
0
←Bit No.
ID5
IDRx BYTE2
(R/W)
(X)
Address: 003A23H+4x(CAN0)
003C23H+4x(CAN1)
Read/write→
Initial value→
15
ID4
(R/W)
(X)
14
ID3
(R/W)
(X)
13
ID2
(R/W)
(X)
12
ID1
(R/W)
(X)
11
ID0
(R/W)
(X)
10
⎯
(-)
(-)
9
⎯
(-)
(-)
8
⎯
(-)
(-)
←Bit No.
IDRx BYTE3
When using the message buffer (x) in the standard frame format (IDEx of the IDE register (IDER)
= 0), use 11 bits of ID28 to ID18. When using the buffer in the extended frame format (IDEx = 1),
use 29 bits of ID28 to ID0.
ID28 to ID0 have the following functions:
•
Set acceptance code.
ID for comparing with the received message ID.
•
Set transmitted message ID.
•
Store the received message ID.
381
CHAPTER 21 CAN CONTROLLER
Notes:
• In the standard frame format, setting "1"s to all bits of ID28 to ID22 is prohibited.
• All received message ID bits are stored (even if bits are masked). In the standard frame format,
ID17 to ID0 stores indefinite value of the part of old message left in the receive shift register.
• A write operation to ID register x (x = 0 to 15) (IDRx) should be performed in words. A write
operation in bytes causes undefined data to be written to the upper byte at writing to the lower
byte. Writing to the upper byte is ignored.
• This register should be set when the message buffer (x) is invalid (BVALx of the message buffer
valid register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause
unnecessary received messages to be stored.
• To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while CAN Controller is
participating in CAN communication (the read value of the CSR: HALT bit is "0" and CAN
Controller is ready to receive or transmit messages), follow the cautions in Section "21.14
Precautions when Using CAN Controller".
382
CHAPTER 21 CAN CONTROLLER
21.6.22
DLC Register x (x = 0 to 15) (DLCRx)
DLC register x (x = 0 to 15) (DLCRx) stores DLC values for message buffer x.
■ DLC Register x (x = 0 to 15) (DLCRx)
Figure 21.6-23 shows the bit configuration of the DLC register x (x = 0 to 15) (DLCRx).
Figure 21.6-23 DLC Register x (x = 0 to 15) (DLCRx)
Address: 003A60H+2x(CAN0)
003C60H+2x(CAN1)
Read/write→
Initial value→
7
⎯
(-)
(-)
6
⎯
(-)
(-)
5
⎯
(-)
(-)
4
⎯
(-)
(-)
3
DLC3
(R/W)
(X)
2
DLC2
(R/W)
(X)
1
DLC1
(R/W)
(X)
←Bit No.
0
DLC0
DLCRx BYTE0
(R/W)
(X)
❍ Transmission
•
Set the data length (byte count) of a transmitted message when a data frame is transmitted
(TRTRx of the transmitting RTR register (TRTRR) is "0").
•
Set the data length (byte count) of a requested message when a remote frame is transmitted
(TRTRx = 1).
Note:
Setting other than 0000B to 1000B (0 to 8 bytes) is prohibited.
❍ Reception
•
Store the data length (byte count) of a received message when a data frame is received
(RRTRx of the remote frame request receiving register (RRTRR) is "0").
•
Store the data length (byte count) of a requested message when a remote frame is received
(RRTRx = 1).
Note:
A write operation to this register should be performed in words. A write operation in bytes causes
undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is
ignored.
383
CHAPTER 21 CAN CONTROLLER
21.6.23
Data Register x (x = 0 to 15) (DTRx)
Data register x (x = 0 to 15) (DTRx) is the data register for message buffer (x).
This register is used only in transmitting and receiving a data frame but not in
transmitting and receiving a remote frame.
■ Data Register x (x = 0 to 15) (DTRx)
Figure 21.6-24 shows the bit configuration of the data register x (x = 0 to 15) (DTRx).
Figure 21.6-24 Data Register x (x = 0 to 15) (DTRx)
Address: 003A80H+8x(CAN0)
003C80H+8x(CAN1)
Read/write→
Initial value→
7
D7
(R/W)
(X)
6
D6
(R/W)
(X)
5
D5
(R/W)
(X)
4
D4
(R/W)
(X)
3
D3
(R/W)
(X)
2
D2
(R/W)
(X)
1
D1
(R/W)
(X)
←Bit No.
0
D0
DTRx BYTE0
(R/W)
(X)
Address: 003A81H+8x(CAN0)
003C81H+8x(CAN1)
Read/write→
Initial value→
15
D7
(R/W)
(X)
14
D6
(R/W)
(X)
13
D5
(R/W)
(X)
12
D4
(R/W)
(X)
11
D3
(R/W)
(X)
10
D2
(R/W)
(X)
9
D1
(R/W)
(X)
8
←Bit No.
D0
DTRx BYTE1
(R/W)
(X)
Address: 003A82H+8x(CAN0)
003C82H+8x(CAN1)
Read/write→
Initial value→
7
D7
(R/W)
(X)
6
D6
(R/W)
(X)
5
D5
(R/W)
(X)
4
D4
(R/W)
(X)
3
D3
(R/W)
(X)
2
D2
(R/W)
(X)
1
D1
(R/W)
(X)
0
←Bit No.
D0
DTRx BYTE2
(R/W)
(X)
Address: 003A83H+8x(CAN0)
003C83H+8x(CAN1)
Read/write→
Initial value→
15
D7
(R/W)
(X)
14
D6
(R/W)
(X)
13
D5
(R/W)
(X)
12
D4
(R/W)
(X)
11
D3
(R/W)
(X)
10
D2
(R/W)
(X)
9
D1
(R/W)
(X)
←Bit No.
8
D0
DTRx BYTE3
(R/W)
(X)
Address: 003A84H+8x(CAN0)
003C84H+8x(CAN1)
Read/write→
Initial value→
7
D7
(R/W)
(X)
6
D6
(R/W)
(X)
5
D5
(R/W)
(X)
4
D4
(R/W)
(X)
3
D3
(R/W)
(X)
2
D2
(R/W)
(X)
1
D1
(R/W)
(X)
0
←Bit No.
D0
DTRx BYTE4
(R/W)
(X)
Address: 003A85H+8x(CAN0)
003C85H+8x(CAN1)
Read/write→
Initial value→
15
D7
(R/W)
(X)
14
D6
(R/W)
(X)
13
D5
(R/W)
(X)
12
D4
(R/W)
(X)
11
D3
(R/W)
(X)
10
D2
(R/W)
(X)
9
D1
(R/W)
(X)
←Bit No.
8
D0
DTRx BYTE5
(R/W)
(X)
Address: 003A86H+8x(CAN0)
003C86H+8x(CAN1)
7
6
5
4
3
2
1
0
D7
(R/W)
(X)
D6
(R/W)
(X)
D5
(R/W)
(X)
D4
(R/W)
(X)
D3
(R/W)
(X)
D2
(R/W)
(X)
D1
(R/W)
(X)
D0
(R/W)
(X)
15
14
13
12
11
10
9
8
D7
(R/W)
(X)
D6
(R/W)
(X)
D5
(R/W)
(X)
D4
(R/W)
(X)
D3
(R/W)
(X)
D2
(R/W)
(X)
D1
(R/W)
(X)
D0
(R/W)
(X)
Read/write→
Initial value→
Address: 003A87H+8x(CAN0)
003C87H+8x(CAN1)
Read/write→
Initial value→
384
←Bit No.
DTRx BYTE6
←Bit No.
DTRx BYTE7
CHAPTER 21 CAN CONTROLLER
❍ Sets transmitted message data (any of 0 to 8 bytes).
Data is transmitted in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB.
❍ Stores received message data.
Data is stored in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB.
Even if the received message data is less than 8 bytes, the remaining bytes of the data register
(DTRx), to which data are stored, are undefined.
Note:
A write operation to this register should be performed in words. A write operation in bytes causes
undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is
ignored.
385
CHAPTER 21 CAN CONTROLLER
21.7 Transmission of CAN Controller
When "1" is written to TREQx of the transmission request register (TREQR),
transmission by the message buffer (x) starts. At this time, TREQx becomes "1" and
TCx of the transmission complete register (TCR) becomes "0".
■ Starting Transmission of the CAN Controller
If RFWTx of the remote frame receiving wait register (RFWTR) is "0", transmission starts
immediately. If RFWTx is "1", transmission starts after waiting until a remote frame is received
(RRTRx of the remote request receiving register (RRTRR) becomes "1").
If a request for transmission is made to more than one message buffer (more than one TREQx is
"1"), transmission is performed, starting with the lowest-numbered message buffer.
Message transmission to the CAN bus (by the transmit output pin TX) starts when the bus is idle.
If TRTRx of the transmission RTR register (TRTRR) is "0", a data frame is transmitted. If TRTRx
is "1", a remote frame is transmitted.
If the message buffer competes with other CAN controllers on the CAN bus for transmission and
arbitration fails, or if an error occurs during transmission, the message buffer waits until the bus is
idle and repeats retransmission until it is successful.
■ Canceling a Transmission Request from the CAN Controller
❍ Canceling by transmission cancel register (TCANR)
A transmission request for message buffer (x) having not executed transmission during
transmission pending can be canceled by writing "1" to TCANx of the transmission cancel register
(TCANR). At completion of cancellation, TREQx becomes "0".
❍ Canceling by storing received message
The message buffer (x) having not executed transmission despite of transmission request also
performs reception.
If the message buffer (x) has not executed transmission despite of a request for transmission of a
data frame (TRTRx = 0 or TREQx = 1), the transmission request is canceled after storing
received data frames passing through the acceptance filter (TREQx = 0).
Note:
A transmission request is not canceled by storing remote frames (TREQx = 1 remains unchanged).
If the message buffer (x) has not executed transmission despite of a request for transmission of a
remote frame (TRTRx = 1 or TREQx = 1), the transmission request is canceled after storing
received remote frames passing through the acceptance filter (TREQx = 0).
386
CHAPTER 21 CAN CONTROLLER
Note:
The transmission request is canceled by storing either data frames or remote frames.
■ Completing Transmission of the CAN Controller
When transmission is successful, RRTRx becomes "0", TREQx becomes "0", and TCx of the
transmission complete register (TCR) becomes "1".
If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt
enable register (TIER) is "1"), an interrupt occurs.
■ Transmission Flowchart of the CAN Controller
Figure 21.7-1 shows a transmission flowchart of the CAN controller.
387
CHAPTER 21 CAN CONTROLLER
Figure 21.7-1 Transmission Flowchart of the CAN Controller
Transmission request
(TREQx:= 1)
TCx := 0
0
TREQx?
1
0
RFWTx?
1
0
RRTRx?
1
If there are any other message buffers
meeting the above conditions, select
the lowest-numbered message buffer.
NO
Is the bus idle?
YES
0
1
TRTRx?
A data frame is transmitted.
A remote frame is transmitted.
NO
Is transmission
successful?
YES
TCANx ?
RRTRx:= 0
TREQx:= 0
TCx := 1
TREQx:= 0
1
1
TIEx ?
0
A transmission complete
interrupt occurs.
End of transmission
388
0
CHAPTER 21 CAN CONTROLLER
21.8 Reception of CAN Controller
Reception starts when the start of data frame or remote frame (SOF) is detected on the
CAN bus.
■ Acceptance Filtering
The received message in the standard frame format is compared with the message buffer (x) set
in the standard frame format (IDEx of the IDE register (IDER) is "0"). The received message in
the extended frame format is compared with the message buffer (x) set (IDEx is "1") in the
extended frame format.
If all the bits set to compare by the acceptance mask agree after comparison between the
received message ID and acceptance code (ID register (IDRx) for comparing with the received
message ID), the received message passes to the acceptance filter of the message buffer (x).
■ Storing Received Message
When the receive operation is successful, received messages are stored in a message buffer x
including IDs passed through the acceptance filter.
When receiving data frames, received messages are stored in the ID register (IDRx), DLC
register (DLCRx), and data register (DTRx).
Even if received message data is less than 8 bytes, some data is stored in the remaining bytes of
the DTRx and its value is undefined.
When receiving remote frames, received messages are stored only in the IDRx and DLCRx, and
the DTRx remains unchanged.
If there is more than one message buffer including IDs passed through the acceptance filter, the
message buffer x in which received messages are to be stored is determined according to the
following rules.
•
The order of priority of the message buffer x (x = 0 to 15) rises as its number lower; in other
words, message buffer 0 is given the highest and the message buffer 15 is given the lowest
priority.
•
Basically, message buffers with the RCx bit of "0" in the receive completion register (RCR) are
preceded in storing received messages.
•
If each bit of the acceptance mask select register (AMSR) are set to All Bits Compare (for
message buffers with the AMSx.1 and AMSx.0 bits set to "00B"), received messages are
stored irrespective of the value of the RCx bit of the RCR.
•
If there are message buffers with the RCx bit of the RCR set to "0", and with the bits of the
AMSR set to All Bits Compare, received messages are stored in the lowest-number (highestpriority) message buffer x.
•
If there are no message buffers corresponding to the above-mentioned conditions, received
messages are stored in the lowest-number message buffer including IDs passed through the
acceptance filter and the overrun is generated (ROVRR:ROVRx=1).
389
CHAPTER 21 CAN CONTROLLER
Figure 21.8-1 shows a flowchart for determining the message buffer (x) where received
messages are to be stored. It is recommended that message buffers be arranged in the following
order: message buffers in which each AMSR bit is set to All Bits Compare, message buffers using
AMR0 or AMR1, and message buffers in which each AMSR bit is set to All Bits Mask.
Figure 21.8-1 Flowchart Determining Message Buffer (x) where Received Messages Stored
Start
Are message buffers with RCx set to "0"
or with AMSx.1 and AMSx.0 set to "00B" found?
NO
YES
Selectthelowest-numbered
message buffer.
Selectthelowest-numbered
message buffer.
End
■ Receive Overrun
The ROVRx bit in the receive overrun register (ROVRR) is set to "1", and indicates receive
overrun when storage of a received message is completed in message buffer x with the RCR
register RCx bit corresponding to message buffer x already set to "1".
■ Processing for Reception of Data Frame and Remote Frame
❍ Processing for reception of data frame
RRTRx of the remote request receiving register (RRTRR) becomes "0".
TREQx of the transmission request register (TREQR) becomes "0" (immediately before storing
the received message). A transmission request for message buffer (x) having not executed
transmission will be canceled.
Note:
A request for transmission of either a data frame or remote frame is canceled.
390
CHAPTER 21 CAN CONTROLLER
❍ Processing for reception of remote frame
RRTRx becomes "1".
If TRTRx of the transmitting RTR register (TRTRR) is "1", TREQx becomes "0". As a result, the
request for transmitting remote frame to message buffer having not executed transmission will be
canceled.
Notes:
• A request for data frame transmission is not canceled.
• For cancellation of a transmission request, see "21.7 Transmission of CAN Controller".
■ Completing Reception
RCx of the reception complete register (RCR) becomes "1" after storing the received message.
If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is "1"),
an interrupt occurs.
Note:
This CAN controller will not receive any messages transmitted by itself.
391
CHAPTER 21 CAN CONTROLLER
21.9 Reception Flowchart of CAN Controller
Figure 21.9-1 shows a reception flowchart of the CAN controller.
■ Reception Flowchart of the CAN Controller
Figure 21.9-1 Reception Flowchart of the CAN Controller
Detectionofstartofdataframe
or remote frame (SOF)
NO
Isanymessagebuffer( x )passingto
the acceptance filter found?
YES
NO
Is reception
successful?
YES
Determinemessagebuffer( x )wherereceived messages to be stored.
Store the received message
in the message buffer (x).
1
RCx?
0
Data frame
ROVRx := 1
Remote frame
Received message?
RRTRx:= 0
RRTRx := 1
1
TRTRx?
0
TREQx:= 0
RCx := 1
RIEx ?
0
End of reception
392
1
A reception interrupt
occurs.
CHAPTER 21 CAN CONTROLLER
21.10
How to Use the CAN Controller
The following settings are required to use the CAN controller:
• Bit timing
• Frame format
• ID
• Acceptance filter
• Low-power consumption mode
■ Setting Bit Timing
The bit timing register (BTR) should be set during bus operation stop (when the bus operation
stop bit (HALT) of the control status register (CSR) is "1").
After the setting completion, write "0" to HALT to cancel bus operation stop.
■ Setting Frame Format
Set the frame format used by the message buffer (x). When using the standard frame format, set
IDEx of the IDE register (IDER) to "0". When using the extended frame format, set IDEx to "1".
This setting should be made when the message buffer (x) is invalid (BVALx of the message buffer
valid register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause
unnecessary received messages to be stored.
■ Setting ID
Set the message buffer (x) ID to ID28 to ID0 of ID register (IDRx). The message buffer (x) ID
need not be set to ID17 to ID0 in the standard frame format. The message buffer (x) ID is used as
a transmission message at transmission and is used as an acceptance code at reception.
This setting should be made when the message buffer (x) is invalid (BVALx of the message buffer
valid register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause
unnecessary received messages to be stored.
■ Setting Acceptance Filter
The acceptance filter of the message buffer (x) is set by an acceptance code and acceptance
mask set. It should be set when the acceptance message buffer (x) is invalid (BVALx of the
message buffer enable register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may
cause unnecessary received messages to be stored.
Set the acceptance mask used in each message buffer (x) by the acceptance mask select
register (AMSR). The acceptance mask registers (AMR0 and AMR1) should also be set if used
(For the setting details, see "21.6.18 Acceptance Mask Select Register (AMSR)" and "21.6.19
Acceptance Mask Registers 0/1 (AMR0/AMR1)").
The acceptance mask should be set so that a transmission request may not be canceled when
unnecessary received messages are stored. For example, it should be set to a full-bit comparison
if only one specific ID is used for the transmission.
393
CHAPTER 21 CAN CONTROLLER
■ Setting Low-Power Consumption Mode
To set the F2MC-16LX in a low-power consumption mode (Stop, Timer, Hardware Standby, etc.),
write "1" to the bus operation stop bit (HALT) of the control status register (CSR), and then check
that the bus operation has stopped (HALT = 1).
394
CHAPTER 21 CAN CONTROLLER
21.11
Procedure for Transmission by Message Buffer (x)
After setting the bit timing, frame format, ID, and acceptance filter, set BVALx to "1" to
activate the message buffer (x).
■ Procedure for Transmission by Message Buffer (x)
❍ Setting transmit data length code
Set the transmit data length code (byte count) to DLC3 to DLC0 of the DLC register (DLCRx).
For data frame transmission (when TRTRx of the transmission RTR register (TRTRR) is "0"), set
the data length of the transmitted message.
For remote frame transmission (when TRTRx = 1), set the data length (byte count) of the
requested message.
Note:
Setting other than 0000B to 1000B (0 to 8 bytes) is prohibited.
❍ Setting transmit data (only for transmission of data frame)
For data frame transmission (when TRTRx of the transmission register (TRTRR) is "0"), set data
as the count of byte transmitted in the data register (DTRx).
Note:
Transmit data should be rewritten while the TREQx bit of the transmission request register (TREQR)
set to "0". There is no need for setting the BVALx bit of the message buffer valid register (BVALR) to
"0". Setting the BVALx bit to "0" may cause incoming remote frame to be lost.
❍ Setting transmission RTR register
For data frame transmission, set TRTRx of the transmission RTR register (TRTRR) to "0".
For remote frame transmission, set TRTRx to "1".
❍ Setting conditions for starting transmission (only for transmission of data frame)
Set RFWTx of the remote frame receiving wait register (RFWTR) to "0" to start transmission
immediately after a request for data frame transmission is set (TREQx of the transmission
request register (TREQR) is "1" and TRTRx of the transmission RTR register (TRTRR) is "0").
Set RFWTx to "1" to start transmission after waiting until a remote frame is received (RRTRx of
the remote request receiving register (RRTRR) becomes "1") after a request for data frame
transmission is set (TREQx = 1 and TRTRx = 0).
395
CHAPTER 21 CAN CONTROLLER
Note:
Remote frame transmission cannot be made, if RFWTx is set to "1".
❍ Setting transmission complete interrupt
When generating a transmission complete interrupt, set TIEx of the transmission complete
interrupt enable register (TIER) to "1".
When not generating a transmission complete interrupt, set TIEx to "0".
❍ Setting transmission request
For a transmission request, set TREQx of the transmission request register (TREQR) to "1".
❍ Canceling transmission request
When canceling a pending request for transmission to the message buffer (x), write "1" to TCANx
of the transmission cancel register (TCANR).
Check TREQx. When TREQx = 0, transmission cancellation is terminated or transmission is
completed. Check TCx of the transmission complete register (TCR). When TCx = 0, transmission
cancellation is terminated. When TCx = 1, transmission is completed.
❍ Processing for completion of transmission
If transmission is successful, TCx of the transmission complete register (TCR) becomes "1".
If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt
enable register (TIER) is "1"), an interrupt occurs.
After checking the transmission completion, write "0" to TCx to clear. This cancels the
transmission complete interrupt.
In the following cases, the pending transmission request is canceled by receiving and storing a
message.
•
Request for data frame transmission by reception of data frame
•
Request for remote frame transmission by reception of data frame
•
Request for remote frame transmission by reception of remote frame
Request for data frame transmission is not canceled by receiving and storing a remote frame. ID
and DLC, however, are changed by the ID and DLC of the received remote frame. Note that the
ID and DLC of data frame to be transmitted become the value of received remote frame.
396
CHAPTER 21 CAN CONTROLLER
21.12
Procedure for Reception by Message Buffer (x)
After setting the bit timing, frame format, ID, and acceptance filter, make the settings
described below.
■ Procedure for Reception by Message Buffer (x)
❍ Setting reception interrupt
To enable reception interrupt, set RIEx of the reception interrupt enable register (RIER) to "1".
To disable reception interrupt, set RIEx to "0".
❍ Starting reception
When starting reception after setting, set BVALx of the message buffer valid register (BVALR) to
"1" to make the message buffer (x) valid.
❍ Processing for reception completion
If reception is successful after passing to the acceptance filter, the received message is stored in
the message buffer (x) and RCx of the reception complete register (RCR) becomes "1". For data
frame reception, RRTRx of the remote request receiving register (RRTRR) becomes "0". For
remote frame reception, RRTRx becomes "1".
If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is "1"),
an interrupt occurs.
After checking the reception completion (RCx = 1), process the received message.
After completion of processing the received message, check ROVRx of the reception overrun
register (ROVRR).
If ROVRx = 0, the processed received message is valid. Write "0" to RCx to set it to "0" (the
reception complete interrupt is also canceled) to terminate reception.
If ROVRx = 1, a reception overrun occurred and the next message may have overwritten the
processed message. In this case, received messages should be processed again after setting the
ROVRx bit to "0" by writing "0" to it.
Figure 21.12-1 shows an example of receive interrupt processing.
397
CHAPTER 21 CAN CONTROLLER
Figure 21.12-1 Example of Receive Interrupt Processing
Interrupt with RCx = 1
Read received messages.
A := ROVRx
ROVRx:= 0
A = 0?
YES
RCx := 0
End
398
NO
CHAPTER 21 CAN CONTROLLER
21.13
Setting Configuration of Multi-level Message Buffer
If the receptions are performed frequently, or if several different ID’s of messages are
received, in other words, if there is insufficient time for handling messages, more than
one message buffer can be combined into a multi-level message buffer to provide
allowance for processing time of the received message by CPU.
■ Setting Configuration of Multi-level Message Buffer
To provide a multi-level message buffer, the same acceptance filter must be set in the combined
message buffers.
If the bits of the acceptance mask select register (AMSR) are set to All Bits Compare ((AMSx.1,
AMSx.0) = (0, 0)), multi-level message configuration of message buffers is not allowed. This is
because All Bits Compare causes received messages to be stored irrespective of the value of the
RCx bit of the receive completion register (RCR), so received messages are always stored in
lower-numbered (lower-priority) message buffers even if All Bits Compare and identical
acceptance code (ID register (IDRx)) are specified for more than one message buffer. Therefore,
All Bits Compare and identical acceptance code should not be specified for more than one
message buffer.
Figure 21.13-1 shows operational examples of multi-level message buffers.
399
CHAPTER 21 CAN CONTROLLER
Figure 21.13-1 Examples of Operation of Multi-level Message Buffer
: Initialization
AMS15, AMS14, AMS13
AMSR 10 10 10
Select AMR0.
...
AM28 to AM18
AMS0
ID28 to ID18
0000 1111 111
RC15, RC14, RC13
IDE
...
Message buffer 13
0101 0000 000
0
...
RCR 0
0
0
...
Message buffer 14
0101 0000 000
0
...
ROVRR 0
0
0
...
Message buffer 15
0101 0000 000
0
...
ROVR15, ROVR14, ROVR13
Mask
Message receiving
"The received message is stored in message buffer 13.
IDE
ID28 to ID18
Message receiving
0101 1111 000
0
...
Message buffer 13
0101 1111 000
0
...
RCR 0
0
1
...
Message buffer 14
0101 0000 000
0
...
ROVRR 0
0
0
...
Message buffer 15
0101 0000 000
0
...
Message receiving
"The received message is stored in message buffer 14.
Message receiving
0101 1111 001
0
...
Message buffer 13
0101 1111 000
0
...
RCR 0
1
1
...
ROVRR 0
0
0
...
Message buffer 14
0101 1111 001
0
...
Message buffer 15
0101 0000 000
0
...
Message receiving
"The received message is stored in message buffer 15.
Message receiving
0101 1111 010
0
...
Message buffer 13
0101 1111 000
0
...
RCR 1
1
1
...
ROVRR 0
0
0
...
Message buffer 14
0101 1111 001
0
...
Message buffer 15
0101 1111 010
0
...
Message receiving "An overrun occurs (ROVR13=1) and the received message is stored in message buffer 13.
400
Message receiving
0101 1111 011
0
...
Message buffer 13
0101 1111 011
0
...
RCR 1
1
1
...
Message buffer 14
0101 1111 001
0
...
ROVRR 0
0
1
...
Message buffer 15
0101 1111 010
0
...
CHAPTER 21 CAN CONTROLLER
Note:
Four messages are received with the same acceptance filter set in message buffers 13, 14 and 15.
401
CHAPTER 21 CAN CONTROLLER
21.14
Precautions when Using CAN Controller
Use of the CAN Controller requires the following cautions.
■ Caution for Disabling Message Buffers by BVAL Bits
The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set
disabled while CAN Controller is participating in CAN communication (the read value of the CSR:
HALT bit is 0 and CAN Controller is ready to receive or transmit messages). This section shows
the work around of this malfunction.
❍ Condition
When following two conditions occur at the same time, CAN Controller will not perform to receive
or transmit messages normally.
•
CAN Controller is participating in the CAN communication. (i.e. The read value of the CSR:
HALT bit is "0" and CAN Controller is ready to receive or transmit messages)
•
Message buffers are read or written when the message buffers are disabled by BVAL bits.
❍ Work around
Operation for re-configuring receiving message buffers
While CAN Controller is participating in CAN communication (the read value of the CSR: HALT bit
is "0" and CAN Controller is ready to receive or transmit messages), it is necessary to following
one from the two operations described below to re-configure message buffers by ID, AMS and
AMR0/1 register-settings.
•
Use of HALT bit
Write "1" to HALT bit and read it back for checking the result is "1". Then change the settings
for ID/AMS/AMR0/1 registers.
•
No Use of Message Buffer 0
Do not use the message buffer "0" for transmission and reception. In other words, disable
message buffer (BVAL0=0), prohibit receive interrupt (RIE0=0) and do not request
transmission (TREQ0=0).
Operation for processing received message
Do not use the receiving prohibition by BVAL bit to avoid over-written of next message. Use the
ROVR bit for checking if over-write has been performed. For details, refer to section "21.6.16
Receive Overrun Register (ROVRR)" and "21.12 Procedure for Reception by Message Buffer
(x)".
Operation for suppressing transmission request
Do not use BVAL bit for suppressing transmission request, use TCAN bit instead of it.
Operation for composing transmission message
For composing a transmission message, it is necessary to disable the message buffer by BVAL
bit to set ID and IDE registers. In this case, BVAL bit should reset (BVAL=0) after checking if
TREQ bit is "0" (TREQ=0) by reading transmission request bit or after completion of the previous
message transmission (TC=1) by transmission complete bit.
402
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
CHAPTER 22
ADDRESS MATCH DETECTION FUNCTION
This chapter explains the address match detection function and operation.
22.1 Overview of the Address Match Detection Function
22.2 Registers of the Address Match Detection Function
22.3 Operation of the Address Match Detection Function
22.4 Example of the Address Match Detection Function
403
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
22.1 Overview of the Address Match Detection Function
When an address matches the value set in the address detection register, the
instruction code to be read by the CPU is replaced with the INT9 instruction code (01H).
Consequently, the CPU executes the INT9 instruction when executing a specified
instruction. The address match detection function can be achieved using the INT9
interrupt routine for processing.
There are two address detection registers, each with an interrupt permission bit. When
an address matches the value set in the address detection register and the interrupt
permission bit is 1, the instruction code to be read by the CPU is replaced with the INT9
instruction code.
■ Block Diagram of the Address Match Detection Function
Address latch
Address detection
register
Permission bit
F2MC-16LX bus
404
Comparison
Figure 22.1-1 Block Diagram of the Address Match Detection Function
INT9
instruction
F2MC-16LX
CPU core
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
22.2 Registers of the Address Match Detection Function
The two types of registers for the address match detection function are as follows:
• Program address detection registers 0/1 (PADR0 and PADR1)
• Program address detection control status register (PACSR)
■ Program Address Detection Registers 0/1 (PADR0 and PADR1)
The program address detection registers 0/1 (PADR0 and PADR1) compare the address with the
value written in each register. If they match when the interrupt permission bit corresponding to
PACSR is "1", the CPU is requested to issue the INT9 instruction.
When the corresponding interrupt bit is "0", nothing occurs even if they match.
Figure 22.2-1 shows the bit configuration of the program address detection registers (PADR0 and
PADR1).
Figure 22.2-1 Program Address Detection Registers 0/1 (PADR0 and PADR1)
PADR0 001FF2H/001FF1H/001FF0H
byte
byte
byte
Access
R/W
Initial value
Not defined
PADR1 001FF5H/001FF4H/001FF3H
R/W
Not defined
Table 22.2-1 lists the correspondence between the program address detection registers 0/1
(PADR0 and PADR1) and PACSR.
Table 22.2-1 Correspondence between PADR0 and PADR1 Registers and PACSR
Address detection register
Interrupt permission bit
PADR0
AD0E
PADR1
AD1E
■ Program Address Detection Control Status Register (PACSR)
The program address detection control status register (PACSR) controls the operation of the
address detection function.
Figure 22.2-2 shows the bit configuration of the program address detection control status register
(PACSR).
Figure 22.2-2 Program Address Detection Control Status Register (PACSR)
7
Address: 00009EH
Read/write→
Initial value→
6
5
4
Reserved Reserved Reserved Reserved
(-)
(0)
(-)
(0)
(-)
(0)
(-)
(0)
3
AD1E
(R/W)
(0)
2
Reserved
(-)
(0)
1
AD0E
(R/W)
(0)
0
Reserved
←Bit No.
PACSR
(-)
(0)
[bit7 to bit4] Reserved bits
Bit7 to bit4 are reserved. Set these bits to "0" before setting PACSR.
405
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
[bit3] AD1E (Address detect register 1 enable)
The AD1E bit is the operation permission bit of PADR1.
When this bit is "1", the address is compared with the PADR1 register. If they match, the INT9
instruction is issued.
[bit2] Reserved bit
Bit2 is reserved. Set this bit to "0" before setting PACSR.
[bit1] AD0E (Address Detect register 0 Enable)
The AD0E bit is the operation permission bit of PADR0.
When this bit is "1", the address is compared with the PADR0 register. If they match, the INT9
instruction is issued.
[bit0] Reserved bit
Bit0 is reserved. Set this bit to "0" before setting PACSR.
406
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
22.3 Operation of the Address Match Detection Function
If the program counter specifies the same address as the address match detection
register, the INT9 instruction is executed. The address match detection function can be
achieved by processing the INT9 instruction routine.
■ Operation of the Address Match Detection Function
There are two address detection registers with a compare enable bit. When the value set in the
address detection register and the value of the program counter match and the compare enable
bit is set to "1", the CPU executes the INT9 instruction.
Note:
If the value of the address detection register and the value of the program counter match, the
contents of internal data bus is changed to 01H forcibly. Consequently, the INT9 instruction is
executed. Before changing the contents of the address detection register, always set the compare
enable bit to "0". While the compare enable bit is set to "1", changing the contents of the address
detection register may result in a malfunction.
407
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
22.4 Example of the Address Match Detection Function
Figure 22.4-1 shows a system configuration example of the address match detection
function. Table 22.4-1 lists the EEPROM memory map.
■ System Configuration Example of the Address Match Detection Function
Figure 22.4-1 System Configuration Example of the Address Match Detection Function
EEPROM
MCU
F2MC-16LX
SIN
Table 22.4-1 EEPROM Memory Map
Address
Description
0000H
Number of bytes of patch program No.0 (If 0, no
program error exists.)
0001H
Program address No.0 bit7 to bit0
0002H
Program address No.0 bit15 to bit8
0003H
Program address No.0 bit24 to bit16
0004H
Number of bytes of patch program No.1 (If 0, no
program error exists.)
0005H
Program address No.1 bit7 to bit0
0006H
Program address No.1 bit15 to bit8
0007H
Program address No.1 bit24 to bit16
0010H or higher
Main body of patch program No. 0 and No. 1
❍ Initial status
EEPROM is set to all "0"s.
❍ When a program error occurs:
The main body of the patch program and program address are transferred to the MCU through
the connector (UART). The MCU writes the information to EEPROM.
408
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
❍ Reset sequence
The MCU reads the value of EEPROM after reset. If the number of bytes of the patch program is
not "0", the main body of the patch program is read from EEPROM and written to RAM. The MCU
then uses either PADR0 or PADR1 to set the patch address and sets the compare enable bit. If
the relocatable patch program is required, the first address of the patched program can be written
to the RAM area. In this case, the INT9 routine accesses this user-defined RAM area and jumps
to the patched program.
❍ INT9 instruction
The interrupt routine can know the address where the interrupt occurs by checking the value of
the stack program counter. The information that has been placed on the stack during the interrupt
is discarded.
■ Example of Program Patch Processing
Figure 22.4-2 Example of Program Patch Processing
FFFFFFh
Abnormal program
PC = address in error
ROM
External EEPROM
Register set for
program patch
Number of program bytes
Address where the interrupt occurs
Corrected program
Data transfer using UART
Corrected program
RAM
000000H
409
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
Figure 22.4-3 Flow of Program Patch Processing
Reset
Reads 0000H of E2PROM
INT9
YES
0000H(E2PROM)=0
To patch program
JMP 000400H
NO
Read address
0001H to 0003H (E2PROM)
MOV
PADR0 (MCU)
Execute patch program
000400H to 000480H
Read patch program
0010H to 0090H (E2PROM)
MOV
000400H to 000480H (MCU)
Terminate patch program
JMP FF0050H
Enable compare
MOV PACSR, #02H
Execute normal program
NO
PC=PADR0
YES
INT9
FFFFFFH
FF0050H
Abnormal program
ROM
FFFFH
FF0000H
E2PROM
FE0000H
0090H
Patch program
0010H
001100H
Stack area
0003H
0002H
0001H
0000H
410
Program address
low-order: 00H
Program address
middle-order: 00H
Program address
high-order: FFH
Number of bytes of
the patch program: 80H
RAM area
000480H
Patch program
RAM
000400H
RAM and register area
000100H
I/O area
000000H
CHAPTER 23
ROM MIRRORING FUNCTION SELECTION
MODULE
This chapter explains the function and the operation of the ROM mirroring function
selection module.
23.1 Outline of ROM Mirroring Function Selection Module
23.2 ROM Mirroring Function Selection Register (ROMM)
411
CHAPTER 23 ROM MIRRORING FUNCTION SELECTION MODULE
23.1 Outline of ROM Mirroring Function Selection Module
The ROM Mirroring function selection module switches whether to mirror the image of
the FF bank of the ROM to the 00 bank.
■ Block Diagram of ROM Mirroring Function Selection Module
Figure 23.1-1 Block Diagram of ROM Mirroring Function Selection Module
Internal data bus
ROM Mirrroring Function Selection Register
Address Area
Address
FF bank
00 bank
Data
ROM
412
CHAPTER 23 ROM MIRRORING FUNCTION SELECTION MODULE
23.2 ROM Mirroring Function Selection Register (ROMM)
Do not access the ROM mirroring function selection register (ROMM) when addresses
004000H to 00FFFFH are being accessed.
■ ROM Mirroring Function Selection Register (ROMM)
Figure 23.2-1 shows the bit configuration of the ROM mirroring function selection register
(ROMM).
Figure 23.2-1 ROM Mirroring Function Selection Register (ROMM)
Address: 00006FH
Read/write→
Initial value→
15
⎯
(-)
(-)
14
⎯
(-)
(-)
13
⎯
(-)
(-)
12
⎯
(-)
(-)
11
⎯
(-)
(-)
10
⎯
(-)
(-)
9
⎯
(-)
(-)
8
MI
(W)
(1)
←Bit No.
ROMM
[bit8] MI
The image of the ROM data in the FF bank can also be found in the 00 bank when "1" is
written to this bit. However, this memory mapping will not be done when this bit is written to
"0". This bit is write only.
Note:
Only FF4000H to FFFFFFH is mirrored to 004000H to 00FFFFH when ROM mirroring function
is activated. Therefore, addresses FF0000H to FF3FFFH will not be mirrored to 00 bank.
413
CHAPTER 23 ROM MIRRORING FUNCTION SELECTION MODULE
414
CHAPTER 24
1M/2M-BIT FLASH MEMORY
This chapter explains the functions and operation of the 1M/2M-bit flash memory. The
following three methods are available for writing data to and erasing data from the
flash memory:
• Parallel programmer
• Serial dedicated programmer
• Executing programs to write/erase data
This chapter explains "Executing programs to write/erase data".
24.1 Outline of 1M/2M-bit Flash Memory
24.2 Sector Configuration of the Flash Memory
24.3 Write/Erase Modes
24.4 Flash Memory Control Status Register (FMCS)
24.5 Starting the Flash Memory Automatic Algorithm
24.6 Confirming the Automatic Algorithm Execution State
24.7 Detailed Explanation of Writing to and Erasing Flash Memory
24.8 Notes on using 1M/2M-bit Flash Memory
24.9 Flash Security Feature
24.10 Example of Programming 1M/2M-bit Flash Memory
415
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.1 Outline of 1M/2M-bit Flash Memory
The 1M/2M-bit flash memory is mapped to the FEH/FCH to FFH bank in the CPU memory
map. The functions of the flash memory interface circuit enable read-access and
program-access from the CPU in the same way as mask ROM. Instructions from the
CPU can be used via the flash memory interface circuit to write data to and erase data
from the flash memory. Internal CPU control therefore enables rewriting of the flash
memory while it is mounted. As a result, improvements in programs and data can be
performed efficiently.
■ 1M/2M-bit Flash Memory Features
•
Use of automatic program algorithm (Embedded AlgorithmTM : Equivalent to MBM29LV200)
•
Erase pause/restart functions provided
•
Detection of completion of writing/erasing using data polling or toggle bit functions
•
Detection of completion of writing/erasing using CPU interrupts
•
Enabled sector erase function (any combination of sectors is available)
•
Minimum of 10,000 write/erase operations
Embedded Algorithm is a trademark of Advanced Micro Devices, Inc.
Note:
The manufacturer code and device code do not have the reading function. These codes cannot be
accessed by the command.
■ Writing to/Erasing Flash Memory
The flash memory cannot be written to or erased and read at the same time. That is, when data is
written to or erased data from the flash memory, the program in the flash memory must first be
copied to RAM. The entire process is then executed in RAM so that data is simply written to the
flash memory. This eliminates the need for the program to access the flash memory from the
flash memory itself.
■ Flash Memory Register
Figure 24.1-1 shows the bit configuration of the flash memory control status register (FMCS).
Figure 24.1-1 Flash Memory Control Status Register (FMCS)
7
6
5
Address: 0000AEH INTE RDYINT WE
Read/write→ (R/W) (R/W) (R/W)
Initial value→
(0)
(0)
(0)
416
4
RDY
(R)
(X)
3
Reserved
(R/W)
(0)
2
LPM1
(R/W)
(0)
1
Reserved
(R/W)
(0)
0
LPM0
(R/W)
(0)
←Bit No.
FMCS
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.2 Sector Configuration of the Flash Memory
Figure 24.2-1 shows the sector configuration of the flash memory.
■ Sector Configuration of the 1M/2M-bit Flash Memory
Figure 24.2-1 shows the sector configuration of the 1M/2M-bit flash memory. The addresses in
the figure indicate the high-order and low-order addresses of each sector.
Figure 24.2-1 Sector Configuration of the 1M/2M-bit Flash Memory
Flash memory
CPU address
Programmer
address*
FFFFFFH
7FFFFH
SA4(16 Kbytes)
Flash memory
CPU address
Programmer
address*
FFFFFFH
7FFFFH
FFBFFFH
7BFFFH
FF9FFFH
79FFFH
FF7FFFH
77FFFH
FEFFFFH
6FFFFH
FDFFFFH
5FFFFH
FCFFFFH
4FFFFH
FC0000H
40000H
SA6(16 Kbytes)
FFBFFFH
7BFFFH
SA3(8 Kbytes)
SA5(8 Kbytes
FF9FFFH
79FFFH
SA2(8 Kbytes)
SA4(8 Kbytes)
FF7FFFH
77FFFH
SA1(32 Kbytes)
SA3(32 Kbytes
FEFFFFH
6FFFFH
SA0(64 Kbytes)
SA2(64 Kbytes)
FE0000H
60000H
SA1(64 Kbytes)
SA0(64 Kbytes)
*: The programmer address is equivalent to the CPU address when data is written to the flash
memory using a parallel programmer. When a general programmer is used for writing/erasing,
this address is used for writing/erasing.
417
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.3 Write/Erase Modes
The flash memory can be accessed in two different ways: Flash memory mode and
alternative mode. Flash memory mode enables data to be directly written to or erased
from the external pins. Alternative mode enables data to be written to or erased from
the CPU via the internal bus. Use the mode external pins to select the mode.
■ Flash Memory Mode
The CPU stops when the mode pins are set to "111B" while the reset signal is asserted. The flash
memory interface circuit is connected directly to ports 0, 2, 3, and 4, enabling direct control from
the external pins. This mode makes the MCU seem like a standard flash memory to the external
pins, and write/erase can be performed using a flash memory programmer.
In flash memory mode, all operations supported by the flash memory automatic algorithm can be
used.
■ Alternative Mode
The flash memory is located in the FE/FC to FF banks in the CPU memory space, and like
ordinary mask ROM, can be read-accessed and program-accessed from the CPU via the flash
memory interface circuit.
Since writing/erasing the flash memory is performed by instructions from the CPU via the flash
memory interface circuit, this mode allows rewriting even when the MCU is soldered on the target
board.
Sector protect operations cannot be performed in these modes.
■ Flash Memory Control Signals
Table 24.3-1 lists the flash memory control signals in flash memory mode.
There is almost a one-to-one correspondence between the flash memory control signals and the
external pins of the MBM29LV200. The VID (12 V) pins required by the sector protect operations
are MD0, MD1, and MD2 instead of A9, RESET, and OE for the MBM29LV200.
In flash memory mode, the external data bus signal width is limited to 8 bits, enabling only onebyte access. The DQ15 to DQ8 pins are not supported. The BYTE pin should always be set to 0.
418
CHAPTER 24 1M/2M-BIT FLASH MEMORY
Table 24.3-1 Flash Memory Control Signals
MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S)
MBM29LV200
Pin number
Normal function
Flash memory mode
1 to 8
P20 to P27
AQ0 to AQ7
A-1, A0 to A6
9
P30
AQ16
A15
10
P31
CE
CE
12
P32
OE
OE
13
P33
WE
WE
14
P34
AQ17
A16
16
P36
BYTE
BYTE
17
P37
RY/BY
RY/BY
18 to 22
P40 to P44
AQ8 to AQ12
A7 to A11
24 to 26
P45 to P47
AQ13 to AQ15
A12 to A14
49
MD0
MDO
A9 (VID)
50
MD1
MD1
RESET (VID)
51
MD2
MD2
OE (VID)
85 to 92
P00 to P07
DQ0 to DQ7
DQ0 to DQ7
77
RST
RESET
RESET
Not supported
DQ8 to DQ15
419
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.4 Flash Memory Control Status Register (FMCS)
The flash memory control status register (FMCS), together with the flash memory
interface circuit, is used to write data to and erase data from the flash memory.
■ Flash Memory Control Status Register (FMCS)
Figure 24.4-1 shows the bit configuration of the flash memory control status register (FMCS).
Figure 24.4-1 Flash Memory Control Status Register (FMCS)
7
6
5
INTE RDYINT WE
Address: 0000AEH
Read/write→ (R/W) (R/W) (R/W)
Initial value→
(0)
(0)
(0)
4
RDY
(R)
(X)
3
Reserved
(R/W)
(0)
2
LPM1
(R/W)
(0)
1
Reserved
(R/W)
(0)
0
LPM0
(R/W)
(0)
←Bit No.
FMCS
[bit7] INTE (INTerrupt Enable)
This bit generates an interrupt to the CPU when flash memory write/erase terminates.
An interrupt to the CPU is generated when the INTE and RDYINT bits are "1". No interrupt is
generated when the INTE bit is "0".
•
0: Disables interrupts when write/erase terminates.
•
1: Enables interrupts when write/erase terminates.
[bit6] RDYINT (ReaDY INTerrupt)
This bit indicates the operating state of the flash memory.
This bit is set to "1" when flash memory write/erase terminates. Data cannot be written to or
erased from the flash memory while this bit is "0" after a flash memory write/erase. Flash
memory write/erase is enabled when write/erase terminates and this bit is set to "1".
Writing "0" clears this bit to "0". Writing "1" is ignored. This bit is set to "1" at the termination
timing of the flash memory automatic algorithm (see Section "24.5 Starting the Flash Memory
Automatic Algorithm"). When the read-modify-write (RMW) instruction is used, "1" is always
read.
•
0: Write/erase is being executed.
•
1: Write/erase has terminated (interrupt request generated).
[bit5] WE (Write Enable)
This bit enables writing to the flash memory area.
When this bit is "1", writing after the command sequence (see Section "24.5 Starting the
Flash Memory Automatic Algorithm") is issued to the FE/FC to FF bank writes to the flash
memory area. When this bit is "0", the write/erase signal is not generated. This bit is used
when the flash memory write/erase command is started.
If write/erase is not performed, it is recommended that this bit be set to "0" to prevent data
from being mistakenly written to the flash memory.
420
•
0: Disables flash memory write/erase.
•
1: Enables flash memory write/erase.
CHAPTER 24 1M/2M-BIT FLASH MEMORY
[bit4] RDY (ReaDY)
This bit enables flash memory write/erase.
Flash memory write/erase is disabled while this bit is "0". However, the Read/Reset command
and Sector Erase command, can be accepted even if this bit is "0".
•
0: Write/erase is being executed (next data write/erase disabled).
•
1: Write/erase has terminated (next data write/erase enabled).
[bit3] Reserved bit
This bit is reserved for testing. During regular use, it should always be set to "0".
[bit1] Free bit
During regular use, this bit should always be set to "0".
[bit2 and bit0] LPM1 and LPM0 (Low Power Mode)
These bits control the power consumption by the flash memory when the LPM1 and LPM0 are
used. Since the access time to the flash memory from the CPU is largely dependent on this
setting, select a setting value based on the operating frequency of the CPU.
•
01: Low power consumption mode (Operates at an internal operating frequency up to 4 MHz.)
•
10: Low power consumption mode (Operates at an internal operating frequency up to 8 MHz.)
•
11: Low power consumption mode (Operates at an internal operating frequency up to 12.58
MHz.)
•
00: Regular power consumption mode (Operates at an internal operating frequency up to 16
MHz.)
Note:
The RDYINT and RDY bits cannot be changed at the same time. Make a program so that decisions
are made using one or the other of these bits (See Figure 24.4-2 RDYINT and RDY Bit Change
Timing).
Figure 24.4-2 RDYINT and RDY Bit Change Timing
Automatic algorithm
Termination timing
RDYINT bit
RDY bit
1 machine cycle
421
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.5 Starting the Flash Memory Automatic Algorithm
Four types of commands are available for starting the flash memory automatic
algorithm: Read/Reset, Write, Chip Erase, and Sector Erase. Control of suspend and
restart is enabled for sector erase.
■ Command Sequence Table
Table 24.5-1 lists the commands used for flash memory write/erase. All of the data written to the
command register is in bytes, but use word access to write. The data of the high-order bytes at
this time is ignored.
Table 24.5-1 Command Sequence Table
Bus
write
access
1st bus write cycle
2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
1
FxXXXX
XXF0
-
-
-
-
-
-
-
-
-
-
4
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XXF0
RA
RD
-
-
-
-
Write
program
4
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XXA0
PA
(even)
PD
(word)
-
-
-
-
Chip Erase
6
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX80
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX10
Sector Erase
6
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX80
FxAAAA
XXAA
Fx5554
XX55
SA
(even)
XX30
Command
sequence
Read/Reset *
Sector Erase Suspend
Sector Erase Restart
Auto-select
3
FxAAAA
Entering address FxXXXX data (xxB0H) suspends erasing during sector erase.
Entering address FxXXXX data (xx30H) restarts erasing after erasing is suspended during sector erase.
XXAAA
Fx5554
XX55
FxAAAA
XX90
-
-
-
-
-
-
*: Both of the 2 types of Read/Reset commands can reset the flash memory to read mode.
Notes:
• The addresses Fx in the table mean FF and FE for 1M-bit flash memory, FF, FE, FD and FC for
2M-bit flash memory. Use these addresses as the access target bank values for operations.
• The addresses in the table are the values in the CPU memory map. All addresses and data are
represented using hexadecimal notation. However, the letter "X" is an optional value.
• RA: Read address
• PA: Write address. Only even addresses can be specified.
• SA: Sector address. See Section "24.2 Sector Configuration of the Flash Memory".
• RD: Read data
• PD: Write data. Only word data can be specified.
422
CHAPTER 24 1M/2M-BIT FLASH MEMORY
The Auto-select command shown in Table 24.5-2 is used to know the state of sector protection.
When using the Auto-select command, set the address as follows.
Table 24.5-2 Address Setting at Auto-select
Sector protection
AQ13 to AQ16
AQ7
AQ2
AQ1
AQ0
DQ7 to DQ0
Sector Address
L
H
L
L
CODE*
*: When the sector address is protected, the output is "01H".
When the sector address is not protected, the output is "00H".
423
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.6 Confirming the Automatic Algorithm Execution State
Because the write/erase flow of the flash memory is controlled using the automatic
algorithm, the flash memory has hardware for informing its internal operating state and
completion of operation. This automatic algorithm enables confirmation of the
operating state of the built-in flash memory using the following hardware sequence
flags.
■ Hardware Sequence Flags
The hardware sequence flags are configured from the four-bit output of DQ7, DQ6, DQ5, DQ3
and DQ2. The functions of these bits are those of the data polling flag (DQ7), toggle bit flag
(DQ6), timing limit exceeded flag (DQ5), sector erase timer flag (DQ3) and toggle bit 2 flag
(DQ2). The hardware sequence flags can therefore be used to confirm that writing or chip sector
erase has been completed or that erase code write is valid.
The hardware sequence flags can be accessed by read-accessing the addresses of the target
sectors in the flash memory after setting of the command sequence (see Table 24.5-1 in Section
"24.5 Starting the Flash Memory Automatic Algorithm"). Table 24.6-1 lists the bit assignments of
the hardware sequence flags.
Table 24.6-1 Bit Assignments of Hardware Sequence Flags
Bit No.
Hardware sequence flag
7
6
5
4
3
2
1
0
DQ7
DQ6
DQ5
-
DQ3
DQ2
-
-
To determine whether automatic writing or chip sector erase is being executed, the hardware
sequence flags can be checked or the status can be determined from the RDY bit of the flash
memory control register (FMCS) that indicates whether writing has been completed. After writing/
erasing has terminated, the state returns to the read/reset state. When making a program, use
one of the flags to confirm that automatic writing/erasing has terminated. Then, perform the next
processing operation, such as data read. In addition, the hardware sequence flags can be used to
confirm whether the second or subsequent sector erase code write is valid. Table 24.6-2 lists the
functions of the hardware sequence flags.
424
CHAPTER 24 1M/2M-BIT FLASH MEMORY
Table 24.6-2 Hardware Sequence Flag Functions
State
Write --> Write completed (write
address specified)
Chip/sector erase --> Erase
completed
State
change for
normal
operation
Abnormal
operation
DQ7
DQ7 -->
DATA:7
DQ6
Toggle -->
DATA:6
DQ5
DQ3
DQ2
0 -->
DATA:5
0 -->
DATA:3
1 -->
DATA:2
0 --> 1
Toggle -->
Stop
0 --> 1
1
Toggle -->
Stop
Sector erase wait --> Erase started
0
Toggle
0
0 --> 1
Toggle
Erase --> Sector erase suspended
(sector being erased)
0 --> 1
Toggle -->
1
0
1 --> 0
Toggle
Sector erase suspend --> Erase
restarted (sector being erased)
1 --> 0
1 -->
Toggle
0
0 --> 1
Toggle
Sector erase suspended (sector not
being erased)
DATA:7
DATA:6
DATA:5
DATA:3
DATA:2
DQ7
Toggle
1
0
1
0
Toggle
1
1
*
Write
Chip/sector erase
*: If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2 to toggle.
DQ2 does not toggle when the successive reads are executed from other sectors.
425
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.6.1 Data Polling Flag (DQ7)
The data polling flag (DQ7) uses the data polling function to post that the automatic
algorithm is being executed or has terminated
■ Data Polling Flag (DQ7)
Table 24.6-3 and Table 24.6-4 list the state transitions of the data polling flag.
Table 24.6-3 Data Polling Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
Chip/sector
erase -->
Completed
DQ7
DQ7 -->
DATA:7
0 --> 1
Sector
erase wait
--> Started
Sector erase
--> Erase
suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
0
0 --> 1
1 --> 0
DATA:7
Table 24.6-4 Data Polling Flag State Transitions (State Change for Abnormal Operation)
Operating state
Write
Chip/sector erase
DQ7
DQ7
0
❍ Write
Read-access during execution of the automatic write algorithm causes the flash memory to output
the inverted data of bit7 last written, regardless of the value at the address specified by the
address signal. Read-access at the end of the automatic write algorithm causes the flash memory
to output bit7 of the read value of the address specified by the address signal.
❍ Chip/sector erase
For a sector erase, read-access during execution of the chip erase/sector erase algorithm causes
the flash memory to output "0" from the sector currently being erased. For a chip erase, readaccess causes the flash memory to output "0" regardless of the value at the address specified by
the address signal. Read-access at the end of the automatic write algorithm causes the flash
memory to output "1" in the same way.
❍ Sector erase suspend
Read-access during a sector erase suspend causes the flash memory to output "1" if the address
specified by the address signal belongs to the sector being erased. The flash memory outputs
bit7 (DATA: 7) of the read value at the address specified by the address signal if the address
specified by the address signal does not belong to the sector being erased. Referencing this flag
together with the toggle bit flag (DQ6) enables a decision to be made on whether the flash
memory is in the erase suspended state and which sector is being erased.
426
CHAPTER 24 1M/2M-BIT FLASH MEMORY
Note:
When the automatic algorithm is being started, read-access to the specified address is ignored.
Since termination of the data polling flag (DQ7) can be accepted for a data read and other bits
output, data read after the automatic algorithm has terminated should be performed after readaccess has confirmed that data polling has terminated.
427
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.6.2 Toggle Bit Flag (DQ6)
Like the data polling flag (DQ7), the toggle bit flag (DQ6) uses the toggle bit function to
post that the automatic algorithm is being executed or has terminated.
■ Toggle Bit Flag (DQ6)
Table 24.6-5 and Table 24.6-6 list the state transitions of the toggle bit flag.
Table 24.6-5 Toggle Bit Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
Chip/sector
erase -->
Completed
DQ6
Toggle -->
DATA:6
Toggle -->
Stop
Sector
erase wait
--> Started
Sector erase
--> Erase
suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
Toggle
Toggle --> 1
1 --> Toggle
DATA:6
Table 24.6-6 Toggle Bit Flag State Transitions (State Change for Abnormal Operation)
Operating state
Write
Chip/sector erase
DQ6
Toggle
Toggle
❍ Write/chip sector erase
Continuous read-access during execution of the automatic write algorithm and chip/sector erase
algorithm causes the flash memory to toggle "1" or "0" state alternately for every read cycle,
regardless of the value at the address specified by the address signal. Continuous read-access at
the end of the automatic write algorithm and chip/sector erase algorithm causes the flash memory
to stop toggling bit 6 and output bit 6 (DATA: 6) of the read value of the address specified by the
address signal.
❍ Sector erase suspend
Read-access during a sector erase suspend causes the flash memory to output "1" if the address
specified by the address signal belongs to the sector being erased. The flash memory outputs
bit6 (DATA: 6) of the read value at the address specified by the address signal if the address
specified by the address signal does not belong to the sector being erased.
Reference:
For a write, if the sector where data is to be written is rewrite-protected, the toggle bit terminates the
toggle operation after approximately 2µs without any data being rewritten. For an erase, if all of the
selected sectors are write-protected, the toggle bit performs toggling for approximately 100µs and
then returns to the read/reset state without any data being rewritten.
428
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.6.3 Timing Limit Exceeded Flag (DQ5)
The timing limit exceeded flag (DQ5) is used to post that execution of the automatic
algorithm has exceeded the time (internal pulse count) prescribed in the flash memory.
■ Timing Limit Exceeded Flag (DQ5)
Table 24.6-7 and Table 24.6-8 list the state transitions of the timing limit exceeded flag.
Table 24.6-7 Timing Limit Exceeded Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
Chip/sector
erase -->
Completed
DQ5
0 -->
DATA:5
0 --> 1
Sector
erase wait
--> Started
Sector erase
--> Erase
suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
0
0
0
DATA:5
Table 24.6-8 Timing Limit Exceeded Bit Flag State Transitions (State Change for Abnormal
Operation)
Operating state
Write
Chip/sector erase
DQ5
1
1
❍ Write/chip sector erase
Read-access after write or chip/sector erase automatic algorithm activation causes the flash
memory to output "0" if the time is within the prescribed time (time required for write/erase) or to
output "1" if the prescribed time has been exceeded. Because this is done regardless of whether
the automatic algorithm is being executed or has terminated, it is possible to determine whether
write/erase was successful or unsuccessful. That is, when this flag outputs "1", writing can be
determined to have been unsuccessful if the automatic algorithm is still being executed by the
data polling function or toggle bit function.
For example, writing "1" to a flash memory address where "0" has been written will cause the fail
state to occur. In this case, the flash memory will lock and execution of the automatic algorithm
will not terminate. Ocasionally, it is likely to end normally as writing "1". As a result, valid data will
not be output from the data polling flag (DQ7). In addition, the toggle bit flag (DQ6) will exceed
the time limit without stopping the toggle operation and the timing limit exceeded flag (DQ5) will
output "1". Note that this state indicates that the flash memory is not faulty, but has been used
correctly. When this state occurs, execute the Reset command.
429
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.6.4 Sector Erase Timer Flag (DQ3)
The sector erase timer flag (DQ3) is used to post whether the automatic algorithm is
being executed during the sector erase wait period after the Sector Erase command has
been started.
■ Sector Erase Timer Flag (DQ3)
Table 24.6-9 and Table 24.6-10 list the state transitions of the sector erase timer flag.
Table 24.6-9 Sector Erase Timer Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
Chip/sector
erase -->
Completed
DQ3
0 -->
DATA:3
1
Sector
erase wait
--> Started
Sector erase
--> Erase
suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
0 --> 1
1 --> 0
0 --> 1
DATA:3
Table 24.6-10 Sector Erase Timer Flag State Transitions (State Change for Abnormal
Operation)
Operating state
Write
Chip/sector erase
DQ3
0
1
❍ Sector erase
Read-access after the Sector Erase command has been started causes the flash memory to
output "0" if the automatic algorithm is being executed during the sector erase wait period,
regardless of the value at the address specified by the address signal of the sector that issued
the command. The flash memory outputs "1" if the sector erase wait period has been exceeded.
If the data polling function or toggle bit function indicates that the erase algorithm is being
executed, internally controlled erase has already started if this flag is "1". Continuous write of the
sector erase codes or commands other than the Sector Erase Suspend command will be ignored
until erase is terminated.
If this flag is "0", the flash memory will accept write of additional sector erase codes. To confirm
this, it is recommended that the state of this flag be checked before continuing to write sector
erase codes. If this flag is "1" after the second state check, it is possible that additional sector
erase codes may not be accepted.
❍ Sector erase
Read-access during execution of sector erase suspend causes the flash memory to output "1" if
the address specified by the address signal belongs to the sector being erased. The flash
memory outputs bit3 (DATA: 3) of the read value of the address specified by the address signal if
the address specified by the address signal does not belong to the sector being erased.
430
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.6.5 Toggle Bit 2 Flag (DQ2)
The toggle bit 2 flag (DQ2) is a flag that uses the toggle bit function to indicate that the
sector is in the erase-suspended state.
■ Toggle Bit 2 Flag (DQ2)
Table 24.6-11 and Table 24.6-12 list the state transitions of the toggle bit 2 flag.
Table 24.6-11 Toggle Bit 2 Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
Chip/sector
erase -->
Completed
DQ2
1 -->
DATA:2
Toggle -->
Stop
Sector
erase wait
--> Started
Sector erase
--> Erase
suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
Toggle
Toggle
Toggle
DATA:2
Table 24.6-12 Toggle Bit 2 Flag State Transitions (State Change for Abnormal Operation)
Operating state
Write
Chip/sector erase
DQ2
1
*
*: If the DQ5 outputs "1" (exceed the timing limit), successive reads to a writing or erasing sector cause
DQ2 to toggle. DQ2 does not toggle to other sectors.
❍ During a sector erase operation
If successive reads are executed during the execution of the chip sector erase algorithm, a flash
memory toggles to output "1" and "0" to addresses alternately at every read access regardless of
the location indicated by the addresses. If successive reads are executed after the chip sector
erase algorithm is completed, the flash memory stops the toggle operation of the bit2 and outputs
the read value of the bit2 (DATA: 2) to the location indicated by the address.
431
CHAPTER 24 1M/2M-BIT FLASH MEMORY
❍ While a sector erase operation is suspended
If successive reads are executed while a sector erase operation is suspended, and if the address
indicates the sector to be erased, the flash memory toggles to alternately output "1" and "0". If the
address indicates the sector is not to be erased, the flash memory outputs the read value of the
bit2 (DATA: 2) to the location indicated by the address.
In the erase-suspend-program mode, successive reads from the non-erase suspended sector
causes the flash memory to output "1".
Both DQ2 and DQ6 are used for detecting an erase-suspended sector (DQ2 toggles, but DQ6
does not).
DQ2 is also used for detecting an erasing sector. While erasing a sector, if a read access is
executed from the erasing sector, DQ2 toggles.
Reference:
If all sectors selected for erasing are write-protected, the toggle bit 2 toggles for approx. 100µs, and
then returns to the read/reset mode without writing the data.
432
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.7 Detailed Explanation of Writing to and Erasing Flash
Memory
This section describes each operation procedure of flash memory Read/Reset, Write,
Chip Erase, Sector Erase, Sector Erase Suspend, and Sector Erase Restart when a
command that starts the automatic algorithm is issued.
■ Detailed Explanation of Flash Memory Write/Erase
The flash memory executes the automatic algorithm by issuing a command sequence (see Table
24.5-1 in Section "24.5 Starting the Flash Memory Automatic Algorithm") for a write cycle to the
bus to perform Read/Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, or Sector
Erase Restart operations. Each bus write cycle must be performed continuously. In addition,
whether the automatic algorithm has terminated can be determined using the data polling or other
function. At normal termination, the flash memory is returned to the read/reset state.
Each operation of the flash memory is described in the following order:
•
Setting the read/reset state
•
Writing data
•
Erasing all data (erasing all chips)
•
Erasing optional data (erasing sectors)
•
Suspending sector erase
•
Restarting sector erase
433
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.7.1 Setting The Read/Reset State
This section describes the procedure for issuing the Read/Reset command to set the
flash memory to the read/reset state.
■ Setting the Flash Memory to the Read/Reset State
The flash memory can be set to the read/reset state by sending the Read/Reset command in the
command sequence table (see Table 24.5-1 in Section "24.5 Starting the Flash Memory
Automatic Algorithm") continuously to the target sector in the flash memory.
The Read/Reset command has two types of command sequences that execute the first and third
bus operations. However, there are no essential differences between these command
sequences.
The read/reset state is the initial state of the flash memory. When the power is turned on and
when a command terminates normally, the flash memory is set to the read/reset state. In the
read/reset state, other commands wait for input.
In the read/reset state, data is read by regular read-access. As with the mask ROM, program
access from the CPU is enabled. The Read/Reset command is not required to read data by a
regular read. The Read/Reset command is mainly used to initialize the automatic algorithm in
such cases as when a command does not terminate normally.
434
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.7.2 Writing Data
This section describes the procedure for issuing the Write command to write data to the
flash memory.
■ Writing Data to the Flash Memory
The data write automatic algorithm of the flash memory can be started by sending the Write
command in the command sequence table (see Table 24.5-1 in Section "24.5 Starting the Flash
Memory Automatic Algorithm") continuously to the target sector in the flash memory. When data
write to the target address is completed in the fourth cycle, the automatic algorithm and automatic
write are started.
❍ Specifying addresses
Only even addresses can be specified as the write addresses specified in a write data cycle. Odd
addresses cannot be written correctly. That is, writing to even addresses must be done in units of
word data.
Writing can be done in any order of addresses or even if the sector boundary is exceeded.
However, the Write command writes only data of one word for each execution.
❍ Notes on writing data
Writing cannot return data "0" to data "1". When data "1" is written to data "0", the data polling
algorithm (DQ7) or toggle operation (DQ6) does not terminate and the flash memory elements
are determined to be faulty. If the time prescribed for writing is thus exceeded, the timing limit
exceeded flag (DQ5) is determined to be an error. Otherwise, the data is viewed as if dummy
data "1" had been written. However, when data is read in the read/reset state, the data remains
"0". Data "0" can be set to data "1" only by erase operations.
All commands are ignored during execution of the automatic write algorithm. If a hardware reset
is started during writing, the data of the written addresses will not be assured.
■ Writing to the Flash Memory
Figure 24.7-1 is an example of the procedure for writing to the flash memory. The hardware
sequence flags (see Section "24.6 Confirming the Automatic Algorithm Execution State") can be
used to determine the state of the automatic algorithm in the flash memory. Here, the data polling
flag (DQ7) is used to confirm that writing has terminated.
The data read to check the flag is read from the address written to the last.
The data polling flag (DQ7) changes at the same time that the timing limit exceeded flag (DQ5)
changes. For example, even if the timing limit exceeded flag (DQ5) is "1", the data polling flag bit
(DQ7) must be rechecked.
Also for the toggle bit flag (DQ6), the toggle operation stops at the same time that the timing limit
exceeded flag bit (DQ5) changes to "1". The toggle bit flag (DQ6) must therefore be rechecked.
435
CHAPTER 24 1M/2M-BIT FLASH MEMORY
Figure 24.7-1 Example of the Flash Memory Write Procedure
Start writing
FMCS: WE (bit 5)
Enable flash memory write
Write command sequence
(1) FxAAAA <-- XXAA
(2) Fx5554 <-- XX55
(3) FxAAAA <-- XXA0
(4) Write address <-- Write data
Next address
Read internal address
Data polling flag
(DQ7)
Data
Data
Timing limit (DQ5)
1
Read internal address
Data
Data polling (DQ7)
Data
NO
Write error
Final address
YES
FMCS: WE (bit 5)
Disable flash memory write
Complete writing
436
Confirm with the hardware
sequence flags.
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.7.3 Erasing All Data (Erasing Chips)
This section describes the procedure for issuing the Chip Erase command to erase all
data in the flash memory.
■ Erasing All Data in the Flash Memory (Erasing Chips)
All data can be erased from the flash memory by sending the Chip Erase command in the
command sequence table (see Table 24.5-1 in Section "24.5 Starting the Flash Memory
Automatic Algorithm") continuously to the target sector in the flash memory.
The Chip Erase command is executed in six bus operations. When writing of the sixth cycle is
completed, the chip erase operation is started. For chip erase, the user need not write to the flash
memory before erasing. During execution of the automatic erase algorithm, the flash memory
writes "0" for verification before all of the cells are erased automatically.
437
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.7.4 Erasing Optional Data (Erasing Sectors)
This section describes the procedure for issuing the Sector Erase command to erase
optional data (erase sector) in the flash memory. Individual sectors can be erased.
Multiple sectors can also be specified at one time.
■ Erasing Optional Data (Erasing Sectors) in the Flash Memory
Optional sectors in the flash memory can be erased by sending the Sector Erase command in the
command sequence table (see Table 24.5-1 in Section "24.5 Starting the Flash Memory
Automatic Algorithm") continuously to the target sector in the flash memory.
❍ Specifying sectors
The Sector Erase command is executed in six bus operations. Sector erase wait of 50µs is
started by writing the sector erase code (30H) to an accessible even-numbered address in the
target sector in the sixth cycle. To erase multiple sectors, write the erase code (30H) to the
addresses in the target sectors after the above processing operation.
❍ Notes on specifying multiple sectors
Erase is started when the sector erase wait period of 50µs terminates after the final sector erase
code has been written. That is, to erase multiple sectors at one time, an erase code (sixth cycle of
the command sequence) must be written within 50µs of writing of the address of a sector and the
address of the next sector must be written within 50µs of writing of the previous erase code.
Otherwise, the address and erase code may not be accepted. The sector erase timer (hardware
sequence flag DQ3) can be used to check whether writing of the subsequent sector erase code is
valid. At this time, specify so that the address used for reading the sector erase timer indicates
the sector to be erased.
■ Erasing Sectors in the Flash Memory
The hardware sequence flags (see Section "24.6 Confirming the Automatic Algorithm Execution
State") can be used to determine the state of the automatic algorithm in the flash memory. Figure
24.7-2 is an example of the procedure for erasing sectors in the flash memory. Here, the toggle
bit flag (DQ6) is used to confirm that erasing has terminated.
The data that is read to check the flag is read from the sector to be erased.
The toggle bit flag (DQ6) stops the toggle operation at the same time that the timing limit
exceeded flag (DQ5) is changed to "1". For example, even if the timing limit exceeded flag (DQ5)
is "1", the toggle bit flag (DQ6) must be rechecked.
The data polling flag (DQ7) also changes at the same time that the timing limit exceeded flag bit
(DQ5) changes. As a result, the data polling flag (DQ7) must be rechecked.
438
CHAPTER 24 1M/2M-BIT FLASH MEMORY
Figure 24.7-2 Example of the Flash Memory Sector Erase Procedure
Start erasing
FMCS: WE (bit 5)
Enable flash memory erase
Erase command sequence
(1) FxAAAA <-- XXAA
(2) Fx5554 <-- XX55
(3) FxAAAA <-- XX80
(4) FxAAAA <-- XXAA
(5) Fx5554 <-- XX55
(6) Sector address <-Erase code (30H)
Yes
Another erase sector
No
Read internal address 1
Read internal address 2
No
Yes
Next sector
Toggle bit (DQ6)
data 1(DQ6) = data 2(DQ6)
Sector
Erase completed ?
Yes
No
0
Timing limit (DQ5)
1
Read internal address 1
Read internal address 2
No
Toggle bit (DQ6)
data 1(DQ6) = data 2(DQ6)
Yes
Erase error
Final sector
No
Yes
FMCS: WE (bit 5)
Disable flash memory erase
Confirm with the hardware
sequence flags.
Complete erasing
439
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.7.5 Suspending Sector Erase
This section describes the procedure for issuing the Sector Erase Suspend command
to suspend erasing of flash memory sectors. Data can be read from sectors that are not
being erased.
■ Suspending Erasing of Flash Memory Sectors
Erasing of flash memory sectors can be suspended by sending the Sector Erase Suspend
command in the command sequence table (see Table 24.5-1 in Section "24.5 Starting the Flash
Memory Automatic Algorithm") to the target sector in the flash memory.
The Sector Erase Suspend command suspends the sector erase operation being executed and
enables data to be read from sectors that are not being erased. In this state, only reading is
enabled; data cannot be written. This command is valid only during sector erase operations that
include the erase wait time. The command will be ignored during chip erase or write operations.
This command is implemented by writing the erase suspend code (B0H). At this time, specify an
optional address in the flash memory for the address. An Erase Suspend command issued again
during erasing of sectors will be ignored.
Entering the Sector Erase Suspend command during the sector erase wait period will
immediately terminate sector erase wait, cancel the erase operation, and set the erase stop state.
Entering the Erase Suspend command during the erase operation after the sector erase wait
period has terminated will set the erase suspend state after a maximum period of 20µs has
elapsed. Please execute the sector erase suspend command after 20µs or more after issuing the
sector erase command or the sector erase restart command.
440
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.7.6 Restarting Sector Erase
This section describes the procedure for issuing the Sector Erase Restart command to
restart suspended erasing of flash memory sectors.
■ Restarting Erasing of Flash Memory Sectors
Suspended erasing of flash memory sectors can be restarted by sending the Sector Erase
Restart command in the command sequence table (see Table 24.5-1 in Section "24.5 Starting
the Flash Memory Automatic Algorithm") to the target sector in the flash memory.
The Sector Erase Restart command is used to restart erasing of sectors from the sector erase
suspend state set using the Sector Erase Suspend command. The Sector Erase Restart
command is implemented by writing the erase restart code (30H). At this time, specify an optional
address in the flash memory area for the address.
If a Sector Erase Restart command is issued during sector erase, the command will be ignored.
441
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.8 Notes on using 1M/2M-bit Flash Memory
This section contains notes on using 1M/2M-bit flash memory.
■ Notes on Using Flash Memory
❍ Input of a hardware reset (RST)
To input a hardware reset when the automatic algorithm has not been started and reading is in
progress, a minimum "L" level width of 500 ns must be maintained. In this case, a maximum of
500 ns is required until data can be read from the flash memory after a hardware reset has been
activated.
Similarly, to input a hardware reset when the automatic algorithm has been activated and writing
or erasing is in progress, a minimum "L" level width of 500 ns must be maintained. In this case,
20 µs are required until data can be read after the operation for initializing the flash memory has
terminated.
A hardware reset during writing the data being written to be undefined. By hardware reset or the
power supply's switching off during erasing may make the sector being erased unusable.
❍ Canceling of a software reset, watch-dog timer reset, and hardware standby
When the flash memory is being written to or erased with CPU access and if reset conditions
occur while the automatic algorithm is active, the CPU may run out of control. This occurs
because these reset conditions cause the automatic algorithm to continue without initializing the
flash memory unit, possibly preventing the flash memory unit from entering the read state when
the CPU starts the sequence after the reset has been deasserted. These reset conditions must
be disabled during writing to or erasing of the flash memory.
❍ Program access to flash memory
When the automatic algorithm is operating, read access to the flash memory is disabled. With the
memory access mode of the CPU set to internal ROM mode, writing or erasing must be started
after the program area is switched to another area such as RAM. In this case, when sectors
(SA4/SA6) containing interrupt vectors are erased, writing or erasing interrupt processing cannot
be executed.
❍ Hold function
When the CPU accepts a hold request, the Write signal WE of the flash memory unit may be
skewed, causing erroneous writing or erasing due to an erroneous write. When the acceptance of
a hold request is enabled (HDE bit of ECSR set to "1"), ensure that the WE bit of the flash
memory control status register (FMCS) is "0".
❍ Extended intelligent I/O service (EI2OS)
Because write and erase interrupts issued to the CPU from the flash memory interface circuit
cannot be accepted by the EI2OS, they should not be used.
❍ Applying VID
Applying VID required for the sector protect operation should be started and terminated when the
power supply is on.
442
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.9 Flash Security Feature
The Flash security Controller provides possibilities to protect the content of the flash
memory from being read from external pins.
■ Flash Security Feature
One predefined address of the flash memory is assigned to the Flash Security Controller (1M-bit
flash memory: FE0001H, 2M-bit flash memory: FC0001H). If the protection code of "01H" is written
in this address, access to the flash memory is restricted. Once the flash memory is protected,
performing the chip erase operation only can unlock the function otherwise read/write access to
the flash memory from any external pins is not generally possible.
This function is suitable for applications requiring security of self-containing and data stored in the
flash memory. If the target application requires any part of program to locate outside the
microcontroller, the Flash Security Controller can not offer the intended features. For this reason,
the External Vector Fetch mode should not be used when the protection code is set.
Programming of the flash microcontroller by standard parallel programmer may require unique
set-up. For example, with the programmer from Minato Electronics the device checking should be
turned off. Writing the protection code is generally recommended to take place at the end of the
flash programming. This is to avoid unnecessary protection during the programming.
In order to re-program the once protected flash memory, the chip erase operation should be
performed.
For further information, please contact Fujitsu.
443
CHAPTER 24 1M/2M-BIT FLASH MEMORY
24.10
Example of Programming 1M/2M-bit Flash Memory
This section presents a programming example of 1M/2M-bit flash memory.
■ Programming Example of 1M/2M-bit Flash Memory
NAME
FLASHWE
TITLE FLASHWE
;------------------------------------------------------------------------------;1M/2M-bit-FLASH sample program
;
;1: Transmits the program (address: FFC000H, sector: SA4/SA6) from FLASH to RAM
;
(address: 000700H).
;2: Executes the program on RAM.
;3: Writes the PDR1 value to FLASH (address: FE0000H, sector: SA0/SA2).
;4: Reads the written value (address: FE0000H, sector: SA0/SA2) and outputs it to PDR2.
;5: Erases the written sector (SA0/SA2).
;6: Checks and outputs erase data.
;Conditions
; - Number of bytes transmitted to RAM: 100H (256B)
; - Write/erase termination judgment
;
Judgment according to DQ5 (timing limit excess flag)
;
Judgment according to DQ6 (toggle bit flag)
;
Judgment according to RDY (FMCS)
; - Error handling
;
Hi output to P00 to P07
;
Reset command issuance
;------------------------------------------------------------------;
RESOUS IOSEG
ABS=00
;"RESOUS" I/O segment definition
ORG
0000H
PDR0
RB
1
PDR1
RB
1
PDR2
RB
1
PDR3
RB
1
ORG
0010H
DDR0
RB
1
DDR1
RB
1
DDR2
RB
1
DDR3
RB
1
ORG
00A1H
CKSCR
RB
1
ORG
00AEH
FMCS
RB
1
ORG
006FH
ROMM
RB
1
RESOUS ENDS
;
SSTA
SSEG
RW
0127H
STA_T
RW
1
SSTA
ENDS
;
DATA
DSEG
ABS=0FFH
;FLASH command address
ORG
5554H
COMADR2 RW
1
ORG
0AAAAH
COMADR1 RW
1
DATA
ENDS
444
CHAPTER 24 1M/2M-BIT FLASH MEMORY
;/////////////////////////////////////////////////////////////
;Main program (SA1)
;/////////////////////////////////////////////////////////////
CODE
CSEG
START:
;/////////////////////////////////////////////////////
; Initialization
;/////////////////////////////////////////////////////
MOV
CKSCR,#0BAH
;3-multiple setting
MOV
RP,#0
MOV
A,#!STA_T
MOV
SSB,A
MOVW
A,#STA_T
MOVW
SP,A
MOV
ROMM,#00H
;Mirror OFF
MOV
PDR0,#00H
;For error check
MOV
DDR0,#0FFH
MOV
PDR1,#00H
;Port for data input
MOV
DDR1,#00H
MOV
PDR2,#00H
;Port for data output
MOV
DDR2,#0FFH
;
//////////////////////////////////////////////////////////////
;
Transfer of "FLASH write erase program (FFC000H)" to RAM (700H address)
;
//////////////////////////////////////////////////////////////
MOVW
A,#0700H
;Transfer destination RAM area
MOVW
A,#0C000H
;Transfer source address (program position)
MOVW
RW0,#100H
;Number of bytes to be transferred
MOVS
ADB,PCB
;Transfer of 100H from FFBC00H to 000700H
CALLP
000700H
;Jump to the address containing the transferred
;
program
;
/////////////////////////////////////////////////////
;
Data output
;
/////////////////////////////////////////////////////
OUT
MOV
A,#0FEH
MOV
ADB,A
MOVW
RW2,#0000H
MOVW
A,@RW2+00
MOV
PDR2,A
END
JMP
*
CODE
ENDS
;////////////////////////////////////////////////////////////
;FLASH write erase program (SA4/SA6)
;////////////////////////////////////////////////////////////
RAMPRG CSEG
ABS=0FFH
ORG
0C000H
;
////////////////////////////////////////////
Initialization
;
////////////////////////////////////////////
MOVW
RW0,#0500H
;RW0:RAM space for input data acquisition 00:0500 to
MOVW
RW2,#0000H
;RW2:Flash memory write address
FD:0000 to
MOV
A,#00H
;DTB modification
MOV
DTB,A
;Bank specification for @RW0
MOV
A,#0FDH
;ADB modification 1
MOV
ADB,A
;Bank specification for write mode specification
;
address
MOV
PDR3,#00H
;Switch initialization
MOV
DDR3,#00H
;
WAIT1
BBC
PDR3:0,WAIT1
;PDR3: 0(write start at high level)
;
;////////////////////////////////////////////////
;Write (SA0/SA2)
;////////////////////////////////////////////////
MOV
A,PDR1
MOVW
@RW0+00,A
;PDR1 data allocation to RAM
MOV
FMCS,#20H
;Write mode setting
MOVW
ADB:COMADR1,#00AAH
;Flash write command 1
MOVW
ADB:COMADR2,#0055H
;Flash write command 2
445
CHAPTER 24 1M/2M-BIT FLASH MEMORY
MOVW
ADB:COMADR1,#00A0H
;Flash write command 3
;
WRITE
;
;
;
;
;
;
;
;
NTOW
;
;
;
MOVW
A,@RW0+00
;Input data (RW0) write to flash memory (RW2)
MOVW
@RW2+00,A
;Wait time check
///////////////////////////////////////////////////////////////////
ERROR when the time limit excess check flag is set and toggle operation is
in progress
///////////////////////////////////////////////////////////////////
MOVW
A,@RW2+00
AND
A,#20H
;DQ5 time limit check
BZ
NTOW
;Time limit over
MOVW
A,@RW2+00
;AH
MOVW
A,@RW2+00
;AL
XORW
A
;XOR of AH and AL (1 when the values differ)
AND
A,#40H
;Is the DQ6 toggle bit different?
BNZ
ERROR
;To ERROR when the DQ6 toggle bit is different
///////////////////////////////////////
Write termination check (FMCS-RDY)
///////////////////////////////////////
///////////////////////////////////////
MOVW
A,FMCS
AND
A,#10H
;Extraction of FMCS RDY bit (bit 4)
BZ
WRITE
;End of write?
MOV
FMCS,#00H
;Write mode release
/////////////////////////////////////////////////////
Write data output
/////////////////////////////////////////////////////
MOVW
RW2,#0000H
;Write data output
MOVW
A,@RW2+00
MOV
PDR2,A
;
WAIT2
BBC
PDR3:1,WAIT2
;PDR3: 1(sector erase start at high level)
;
;/////////////////////////////////////////////
;Sector erase (SA0/SA2)
;/////////////////////////////////////////////
MOV
@RW2+00,#0000H
;Address initialization
MOV
FMCS,#20H
;Erase mode setting
MOVW
ADB:COMADR1,#00AAH
;Flash erase command 1
MOVW
ADB:COMADR2,#0055H
;Flash erase command 2
MOVW
ADB:COMADR1,#0080H
;Flash erase command 3
MOVW
ADB:COMADR1,#00AAH
;Flash erase command 4
MOVW
ADB:COMADR2,#0055H
;Flash erase command 5
MOV
@RW2+00,#0030H
;Issuance of erase command 6 to the sector
to be erased
ELS
;Wait time check
;
///////////////////////////////////////////////////////////////////
;
ERROR when the time limit excess check flag is set and toggle operation is
;
in progress
;
///////////////////////////////////////////////////////////////////
MOVW
A,@RW2+00
AND
A,#20H
;DQ5 time limit check
BZ
NTOE
;Time limit over
MOVW
A,@RW2+00
;AH High and Low are alternately output from
MOVW
A,@RW2+00
;AL DQ6 per read during write operation.
XORW
A
;XOR of AH and AL (If the DQ6 value differs,
;
"1" write operation is in progress).
AND
A,#40H
;Is the DQ6 toggle bit High?
BNZ
ERROR
;ERROR when the DQ6 toggle bit is High
;
///////////////////////////////////////
;
Erase termination check (FMCS-RDY)
;
///////////////////////////////////////
NTOE
MOVW
A,FMCS
;
AND
A,#10H
;Extraction of FMCS RDY bit (bit 4)
BZ
ELS
;End of sector erase?
MOV
FMCS,#00H
;FLASH erase mode release
RETP
;Return to the main program
446
CHAPTER 24 1M/2M-BIT FLASH MEMORY
;//////////////////////////////////////////////
;Error
;//////////////////////////////////////////////
ERROR
MOV
ADB:COMADR1,#0F0H
;Reset command (read is enabled)
MOV
FMCS,#00H
;FLASH mode release
MOV
PDR0,#0FFH
;Error handling check
RETP
;Return to the main program
RAMPRG ENDS
;/////////////////////////////////////////////
VECT
CSEG
ABS=0FFH
ORG
0FFDCH
DSL
START
DB
00H
VECT
ENDS
;
END
START
447
CHAPTER 24 1M/2M-BIT FLASH MEMORY
448
CHAPTER 25
EXAMPLES OF MB90F543/F549/F543G(S)/
F548G(S)/F549G(S)/F546G(S)/F548GL(S)
SERIAL PROGRAMMING CONNECTION
This chapter provides examples of serial programming connection with the AF220/
AF210/AF120/AF110 flash microcomputer programmer manufactured by Yokogawa
Digital Computer Corporation.
25.1 Basic Configuration of MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/
F546G(S)/F548GL(S) Serial Programming Connection
25.2 Example of Serial Programming Connection (User Power Supply Used)
25.3 Example of Serial Programming Connection (Power Supplied from the
Programmer)
25.4 Example of Minimum Connection to the Flash Microcomputer Programmer
(User Power Supply Used)
25.5 Example of Minimum Connection to the Flash Microcomputer Programmer
(Power Supplied from the Programmer)
449
CHAPTER 25 EXAMPLES OF MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S) SERIAL PROGRAMMING CONNECTION
25.1 Basic Configuration of MB90F543/F549/F543G(S)/F548G(S)/
F549G(S)/F546G(S)/F548GL(S) Serial Programming
Connection
The MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S) supports flash
ROM serial on-board programming (Fujitsu standard). This section describes the
specifications.
■ Basic Configuration of MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S) Serial
Programming Connection
The AF220/AF210/AF120/AF110 flash microcomputer programmer manufactured by Yokogawa
Digital Computer Corporation is used for Fujitsu standard serial on-board programming. Figure
25.1-1 shows the basic configuration of the MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/
F546G(S)/F548GL(S) serial programming connection.
Figure 25.1-1 Basic Configuration of MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S)
Serial Programming Connection
Host interface cable
RS232C
General-purpose
common cable (AZ210)
AF220/AF210/
AF120/AF110
flash
microcomputer
programmer
+
memory card
CLK synchronous
serial
MB90F543/F549
/F543G(S)/F548G(S)
/F549G(S)/F546G(S)
/F548GL(S)
user system
Stand-alone operation enabled
Note:
Ask Yokogawa Digital Computer Corporation for information about the functions and
operations of the AF220/AF210/AF120/AF110 flash microcomputer programmer, general-purpose
common cable (AZ210) for connection, and connectors.
450
CHAPTER 25 EXAMPLES OF MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S) SERIAL PROGRAMMING CONNECTION
Table 25.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming
Pin
MD2, MD1
MD0
Function
Additional information
Mode pins
Controls programming mode from the flash microcomputer
programmer.
X0, X1
Oscillation pins
In programming mode, the CPU internal operation clock
signal is one multiple of the PLL clock signal frequency.
Therefore, the oscillation clock frequency becomes the
internal operation clock signal.
P00, P01
Programming activation pins
Input a "L" level to P00 and a "H" level to P01.
RST
Reset pin
SIN1
Serial data input pin
SOT1
Serial data output pin
SCK1
Serial clock input pin
C
C pin
The capacitor pin is used to stabilize the power supply.
Connect a ceramic capacitor of approximately 0.1µF to the
outside.
Vcc
Power voltage supply pin
If the programming voltage (5 V ± 10%) is supplied from the
user system, the flash microcomputer programmer need not
be connected. Connect so that the power supply of the user
side is not short-circuited.
Vss
GND pin
Common to the ground of the flash microcomputer
programmer.
HST
Hardware standby pin
Input "H" level during serial programming mode.
-
The UART1 is used in CLK synchronous mode.
Even if the P00, SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit
shown in the figure below is required. (The /TICS signal of the flash microcomputer programmer
can be used to disconnect the user circuit during serial programming).
Figure 25.1-2 Control Circuit
AF220/AF210/AF120/AF110
write control pin
10kΩ
AF220/AF210/AF120/AF110
/TICS pin
MB90F543/F549/
F543G(S)/F548G(S)/
F549G(S)/F546G(S)/
F548GL(S)
write control pin
User circuit
Sections "25.2 Example of Serial Programming Connection (User Power Supply Used)" to "25.5
Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from
the Programmer)" present examples the following four types of serial programming connection.
See each Section as required.
451
CHAPTER 25 EXAMPLES OF MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S) SERIAL PROGRAMMING CONNECTION
•
Serial programming connection in MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/
F548GL(S) internal vector mode (user power supply used)
•
Serial programming connection in MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/
F548GL(S) internal vector mode (power supplied from the Programmer)
•
Example of minimum connection to the flash microcomputer programmer (user power supply
used)
•
Example of minimum connection to the flash microcomputer programmer (power supplied
from the Programmer)
Table 25.1-2 Flash Microcomputer Programmer System Configuration (Manufactured by Yokogawa Digital
Computer Corporation)
Model
Function
AF220/AC4P
Model with Ethernet interface built in / 100V to 220 V power adaptor
AF210/AC4P
Standard model / 100V to 220 V power adaptor
AF120/AC4P
Single-key Ethernet interface model / 100V to 220 V power adaptor
AF110/AC4P
Single-key model/100V to 220 V power adaptor
Mainframe
AZ221
PC/AT RS232C cable only for Programmer
AZ210
Standard target probe (a), length: 1 m
FF201
Fujitsu F2MC-16LX flash microcomputer control model
AZ290
Remote controller
/P2
2 Mbytes PC card (option) for flash memory sizes of up to 128 Kbytes
/P4
4 Mbytes PC card (option) for flash memory sizes of up to 512 Kbytes
Inquiries: Yokogawa Digital Computer Corporation
Telephone number: (81)-42-333-6224
Note:
The AF200 flash microcomputer programmer, which is not supported now, can be used by using
control module FF201. For the serial programming connection information, see the following clause,
"Oscillation Clock Frequency and Serial Clock Input Frequency".
452
CHAPTER 25 EXAMPLES OF MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S) SERIAL PROGRAMMING CONNECTION
■ Oscillation Clock Frequency and Serial Clock Input Frequency
The formula shown below can be used to calculate the maximum serial clock frequency that can
be input to the MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S).
Maximum serial clock frequency that can be input = 0.125 x oscillation clock frequency
Consequently, change the serial clock input frequency by setting the serial clock frequency of the
flash microcomputer programmer according to the current oscillation clock frequency.
Table 25.1-3 Examples of the Maximum Serial Clock Frequency That Can Be Input
Oscillation clock
frequency
Maximum serial clock
frequency that can be
input for the
microcomputer
Maximum serial clock
frequency that can be set
with AF220/AF210/
AF120/AF110
Maximum serial clock
frequency that can be set
with AF200
4 MHz
500 kHz
500 kHz
500 kHz
8 MHz
1 MHz
850 kHz
500 kHz
16 MHz
2 MHz
1.25 MHz
500 kHz
453
CHAPTER 25 EXAMPLES OF MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S) SERIAL PROGRAMMING CONNECTION
25.2 Example of Serial Programming Connection (User Power
Supply Used)
Figure 25.2-1 shows an example of serial programming connection when the
microcomputer power voltage is supplied from the user power supply. The values 1 and
0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/
AF120/AF110 programmer.
Serial reprogramming mode: MD2, MD1, MD0 = 110
■ Example of Serial Programming Connection (User Power Supply Used)
Figure 25.2-1 Example of Serial Programming Connection for MB90F543/F549/F543G(S)/F548G(S)/
F549G(S)/F546G(S)/F548GL(S) Single-chip Modes (User Power Supply Used)
AF220/AF210/AF120/AF110
flash microcomputer
programmer
TAUX3
User system
MB90F543/F549/
F543G(S)/F548G(S)/
F549G(S)/F546G(S)/
F548GL(S)
Connector
DX10-28S
(19)
MD2
10kΩ
10kΩ
MD1
10kΩ
TMODE
MD0
X0
(12)
X1
TAUX
(23)
P00
10kΩ
/TICS
(10)
User
10kΩ
User
HST
10kΩ
/TRES
RST
(5)
10kΩ
User
0.1µF
TTXD
TRXD
TCK
(13)
(27)
(6)
TVcc
(2)
GND
(7,8,
14,15,
21, 22
1, 28)
P01
C
SIN1
SOT1
SCK1
Vcc
User power
supply
Vss
Pin 14
Pins 3, 4, 9, 11, 16, 17, 18, 20,
24, 25, and 26 are open.
DX10-28S: Right-angle type
454
Pin 1
DX10-28S
Pin 28
Pin 15
Connector (Hirose Electronics Ltd.)
pin arrangement
CHAPTER 25 EXAMPLES OF MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S) SERIAL PROGRAMMING CONNECTION
•
Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit
shown in the figure below is required in the same way that it is for P00. (The /TICS signal of
the flash microcomputer programmer can be used to disconnect the user circuit during serial
programming.)
Figure 25.2-2 Control Circuit
AF220/AF210/AF120/AF110
write control pin
10kΩ
AF220/AF210/
AF120/AF110
/TICS pin
MB90F543/F549/
F543G(S)/F548G(S)/
F549G(S)/F546G(S)/
F548GL(S)/
write control pin
User circuit
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
455
CHAPTER 25 EXAMPLES OF MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S) SERIAL PROGRAMMING CONNECTION
25.3 Example of Serial Programming Connection (Power
Supplied from the Programmer)
Figure 25.3-1 shows an example of serial programming connection when the
microcomputer power voltage is supplied from the programmer. The values 1 and 0 are
input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/AF120/
AF110 programmer.
Serial reprogramming mode: MD2, MD1, MD0 = 110B
■ Example of Serial Programming Connection (Power Supplied from the Programmer)
Figure 25.3-1 Example of Serial Programming Connection for MB90F543/F549/F543G(S)/F548G(S)/
F549G(S)/F546G(S)/F548GL(S) Single-chip Modes (Power Supplied from the Programmer)
AF220/AF210/AF120/AF110
flash microcomputer
programmer
TAUX3
User system
MB90F543/F549/
F543G(S)/F548G(S)/
F549G(S)/F546G(S)/
F548GL(S)
Connector
DX10-28S
(19)
MD2
10kΩ
10kΩ
MD1
10kΩ
TMODE
MD0
X0
(12)
X1
TAUX
(23)
/TICS
(10)
P00
10kΩ
User
10kΩ
User
HST
10kΩ
10kΩ
/TRES
(5)
RST
10kΩ
User
0.1µF
TTXD
TRXD
TCK
TVcc
Vcc
TVPP1
GND
(13)
(27)
(6)
(2)
(3)
(16)
SIN1
SOT1
SCK1
Vcc
(7, 8,
14,15,
21, 22
1, 28)
Pins 4, 9, 11, 17, 18, 20,
24, 25, and 26 are open.
P01
C
Vss
Pin 14
Pin 1
Pin 28
Pin 15
DX10-28S
DX10-28S: Right-angle type
Connector (Hirose Electronics Ltd.)
pin arrangement
456
CHAPTER 25 EXAMPLES OF MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S) SERIAL PROGRAMMING CONNECTION
•
Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit
shown in the figure below is required in the same way that it is for P00. (The /TICS signal of
the flash microcomputer programmer can be used to disconnect the user circuit during serial
programming.)
Figure 25.3-2 Control Circuit
AF220/AF210/AF120/AF110
write control pin
MB90F543/F549/
F543G(S)/F548G(S)/
F549G(S)/F546G(S)/
F548GL(S)
write control pin
10kΩ
AF220/AF210/
AF120/AF110
/TICS pin
User circuit
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
•
When the programming power is supplied from the AF220/AF210/AF120/AF110, be careful
not to short-circuit the user power supply.
457
CHAPTER 25 EXAMPLES OF MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S) SERIAL PROGRAMMING CONNECTION
25.4 Example of Minimum Connection to the Flash
Microcomputer Programmer (User Power Supply Used)
Figure 25.4-1 is an example of the minimum connection to the flash microcomputer
programmer when the user power supply is used.
Serial reprogramming mode: MD2, MD1, MD0 = 110B
■ Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used)
For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcomputer
programmer need not be connected if the pins are set as indicated below.
Figure 25.4-1 Example of Minimum Connection to the MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/
F546G(S)/F548GL(S) Flash Microcomputer Programmer (User Power Supply Used)
AF220/AF210/AF120/AF110 User system
flash microcomputer
1 for serial
reprogramming
programmer
10kΩ
MB90F543/F549/
F543G(S)/F548G(S)/
F549G(S)/F546G(S)/
F548GL(S)
MD2
1 for serial
reprogramming
10kΩ
10kΩ
MD1
10kΩ
10kΩ
0 for serial
reprogramming
10kΩ
MD0
X0
X1
P00
10kΩ
0 for serial
reprogramming
10kΩ
User circuit
P01
1 for serial reprogramming
User
10kΩ
circuit
Connector
DX10-28S
0.1µF
HST
C
10kΩ
(5)
(13)
(27)
(6)
(2)
/TRES
TTXD
TRXD
TCK
TVcc
GND
(7,8,
14,15,
21,22,
1,28)
RST
SIN1
SOT1
SCK1
Vcc
User power supply
Pins 3, 4, 9, 10, 11, 12, 16, 17, 18, 19,
20, 23, 24, 25, and 26 are open.
DX10-28S: Right-angle type
Vss
Pin 14
Pin 1
Pin 28
Pin 15
DX10-28S
Connector (Hirose Electronics Ltd.)
pin arrangement
458
CHAPTER 25 EXAMPLES OF MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S) SERIAL PROGRAMMING CONNECTION
•
Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit
shown in the figure below is required. (The /TICS signal of the flash microcomputer
programmer can be used to disconnect the user circuit during serial programming.)
Figure 25.4-2 Control Circuit
AF220/AF210/AF120/AF110
write control pin
MB90F543/F549/
F543G(S)/F548G(S)/
F549G(S)/F546G(S)/
F548GL(S)
write control pin
10kΩ
AF220/AF210/
AF120/AF110
/TICS pin
User circuit
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
459
CHAPTER 25 EXAMPLES OF MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S) SERIAL PROGRAMMING CONNECTION
25.5 Example of Minimum Connection to the Flash
Microcomputer Programmer (Power Supplied from the
Programmer)
Figure 25.5-1 is an example of the minimum connection to the flash microcomputer
programmer when power is supplied from the programmer.
Serial reprogramming mode: MD2, MD1, MD0 = 110B
■ Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the
Programmer)
For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcomputer
programmer need not be connected if the pins are set as indicated below.
Figure 25.5-1 Example of Minimum Connection to the MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/
F546G(S)/F548GL(S) Flash Microcomputer Programmer (Power Supplied from the Programmer)
AF220/AF210/AF120/AF110 User system
flash microcomputer
1 for serial
programmer
reprogramming
10kΩ
MB90F543/F549/
F543G(S)/F548G(S)/
F549G(S)/F546G(S)/
F548GL(S)
MD2
1 for serial
reprogramming
10kΩ
10kΩ
MD1
10kΩ
10kΩ
MD0
0 for serial
reprogramming
10kΩ
X0
X1
P00
10kΩ
0 for serial
reprogramming
10kΩ
User circuit
P01
1 for serial reprogramming
User
10kΩ
circuit
Connector
DX10-28S
/TRES
TTXD
TRXD
TCK
TVcc
Vu
TVPP1
GND
(5)
(13)
(27)
(6)
(2)
(3)
(16)
0.1µF
HST
C
10kΩ
RST
SIN1
SOT1
SCK1
Vcc
(7,8,
14,15,
21,22,
1,28)
Pins 3, 4, 9, 10, 11, 12, 17, 18, 19,
20, 23, 24, 25, and 26 are open.
DX10-28S: Right-angle type
Vss
Pin 14
Pin 1
Pin 28
Pin 15
DX10-28S
Connector (Hirose Electronics Ltd.)
pin arrangement
460
CHAPTER 25 EXAMPLES OF MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S) SERIAL PROGRAMMING CONNECTION
•
Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit
shown in the figure below is required. (The /TICS signal of the flash microcomputer
programmer can be used to disconnect the user circuit during serial programming.)
Figure 25.5-2 Control Circuit
AF220/AF210/AF120/AF110
write control pin
10kΩ
AF220/AF210/
AF120/AF110
/TICS pin
MB90F543/F549/
F543G(S)/F548G(S)/
F549G(S)/F546G(S)/
F548GL(S)
write control pin
User circuit
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
•
When the programming power is supplied from the AF220/AF210/AF120/AF110, be careful
not to short-circuit the user power supply.
461
CHAPTER 25 EXAMPLES OF MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/F546G(S)/F548GL(S) SERIAL PROGRAMMING CONNECTION
462
APPENDIX
The appendix provides I/O maps and outlines of instructions.
APPENDIX A I/O Maps
APPENDIX B Instructions
463
APPENDIX A I/O Maps
APPENDIX A I/O Maps
Table A-1 and Table A-2 lists addresses to be assigned to the registers in each resource
of this microcontroller.
■ I/O Maps
Table A-1 I/O Map (1/6)
Address
Register
Abbrevia
Access
-tion
Resource
Initial value
000000H Port data register (for port 0)
PDR0
R/W
Port 0
XXXXXXXXB
000001H Port data register (for port 1)
PDR1
R/W
Port 1
XXXXXXXXB
000002H Port data register (for port 2)
PDR2
R/W
Port 2
XXXXXXXXB
000003H Port data register (for port 3)
PDR3
R/W
Port 3
XXXXXXXXB
000004H Port data register (for port 4)
PDR4
R/W
Port 4
XXXXXXXXB
000005H Port data register (for port 5)
PDR5
R/W
Port 5
XXXXXXXXB
000006H Port data register (for port 6)
PDR6
R/W
Port 6
XXXXXXXXB
000007H Port data register (for port 7)
PDR7
R/W
Port 7
XXXXXXXXB
000008H Port data register (for port 8)
PDR8
R/W
Port 8
XXXXXXXXB
000009H Port data register (for port 9)
PDR9
R/W
Port 9
XXXXXXXXB
00000AH Port data register (for port A)
PDRA
R/W
Port A
-------XB
00000BH
to
00000FH
Reserved
000010H Port direction register (for port 0)
DDR0
R/W
Port 0
00000000B
000011H Port direction register (for port 1)
DDR1
R/W
Port 1
00000000B
000012H Port direction register (for port 2)
DDR2
R/W
Port 2
00000000B
000013H Port direction register (for port 3)
DDR3
R/W
Port 3
00000000B
000014H Port direction register (for port 4)
DDR4
R/W
Port 4
00000000B
000015H Port direction register (for port 5)
DDR5
R/W
Port 5
00000000B
000016H Port direction register (for port 6)
DDR6
R/W
Port 6
00000000B
000017H Port direction register (for port 7)
DDR7
R/W
Port 7
00000000B
000018H Port direction register (for port 8)
DDR8
R/W
Port 8
00000000B
464
APPENDIX A I/O Maps
Table A-1 I/O Map (2/6)
Address
Register
Abbrevia
Access
-tion
Resource
Initial value
000019H Port direction register (for port 9)
DDR9
R/W
Port 9
00000000B
00001AH Port direction register (for port A)
DDRA
R/W
Port A
-------0B
00001BH Analog input enable register (for port 6)
ADER
R/W
Port 6, A/D
11111111B
00001CH Pull-up control register (for port 0)
PUCR0
R/W
Port 0
00000000B
00001DH Pull-up control register (for port 1)
PUCR1
R/W
Port 1
00000000B
00001EH Pull-up control register (for port 2)
PUCR2
R/W
Port 2
00000000B
00001FH Pull-up control register (for port 3)
PUCR3
R/W
Port 3
00000000B
000020H Serial mode control register 0
UMC0
W, R/W
00000100B
000021H Serial status register 0
USR0
R, R/W
00010000B
UIDR0/
UODR0
R/W
XXXXXXXXB
000023H Rate and data register 0
URD0
R/W
0000000XB
000024H Serial mode register 1
SMR1
R/W
00000000B
000025H Serial control register 1
SCR1
W, R/W
00000100B
SIDR1/
SODR1
R/W
XXXXXXXXB
SSR1
R, R/W
00001-00B
CDCR
R/W
0---1111B
000029H Serial edge select register 1
SES1
R/W
------0B
00002AH
Use prohibited
000022H
000026H
Serial input data register 0/serial output
data register 0
Serial input data register 1/serial output
data register 1
UART0
UART1
000027H Serial status register 1
000028H
UART1 communication prescaler
control register
00002BH Serial I/O prescaler
00002CH
Serial mode control status register
SCDCR
R/W
SMCS
R/W
0---1111B
----0000B
Serial I/O
00002DH
00000010B
00002EH Serial shift data register
SDR
R/W
XXXXXXXXB
00002FH Serial edge select register
SES2
R/W
-------0B
000030H DTP/external interrupt enable register
ENIR
R/W
00000000B
000031H DTP/external interrupt request register
EIRR
R/W
ELVR
R/W
000032H
000033H
Request level setting register
DTP/external
interrupt
XXXXXXXXB
00000000B
00000000B
465
APPENDIX A I/O Maps
Table A-1 I/O Map (3/6)
Address
Register
Abbrevia
Access
-tion
Resource
Initial value
000034H A/D control status register 0
ADCS0
R/W
000035H A/D control status register 1
ADCS1
R/W
000036H A/D data register 0
ADCR0
R
XXXXXXXXB
000037H A/D data register 1
ADCR1
R, W
00001-XXB
000038H PPG0 operation mode control register
PPGC0
W, R/W
000039H PPG1 operation mode control register
PPGC1
W, R/W
00003AH PPG unit 0 clock selection register
PPG01
R/W
00003BH
A/D converter
PPGC2
W, R/W
00003DH PPG3 operation mode control register
PPGC3
W, R/W
00003EH PPG unit 1 clock selection register
PPG23
R/W
0-000--1B
0-000001B
000000--B
PPG
(ch2, ch3)
unit 1
0-000--1B
0-000001B
000000--B
Use prohibited
000040H PPG4 operation mode control register
PPGC4
W, R/W
000041H PPG5 operation mode control register
PPGC5
W, R/W
000042H PPG unit 2 clock selection register
PPG45
R/W
000043H
PPG
(ch0, ch1)
unit 0
00000000B
Reserved
00003CH PPG2 operation mode control register
00003FH
00000000B
PPG
(ch4, ch5)
unit 2
0-000--1B
0-000001B
000000--B
Use prohibited
000044H PPG6 operation mode control register
PPGC6
W, R/W
000045H PPG7 operation mode control register
PPGC7
W, R/W
000046H PPG unit 3 clock selection register
PPG67
R/W
0-000--1B
PPG
(ch6, ch7)
unit 3
0-000001B
000000--B
000047H
to
00004BH
Use prohibited
00004CH Input capture control status register 0/1
ICS01
R/W
Input capture
0/1
00000000B
00004DH Input capture control status register 2/3
ICS23
R/W
Input capture
2/3
00000000B
00004EH Input capture control status register 4/5
ICS45
R/W
Input capture
4/5
00000000B
00004FH Input capture control status register 6/7
ICS67
R/W
Input capture
6/7
00000000B
466
APPENDIX A I/O Maps
Table A-1 I/O Map (4/6)
Address
000050H
Abbrevia
Access
-tion
Register
Timer control status register 0
TMCSR0
H
000054H
Timer control status register 1
16-bit reload
timer 0
TMR0/
TMRLR0
R/W
TMCSR1
R/W
TMR1/
TMRLR1
000058H Output compare control register 0
OCS0
000059H Output compare control register 1
OCS1
00005AH Output compare control register 2
OCS2
00005BH Output compare control register 3
OCS3
00005CH
to
00006BH
Use prohibited
R/W
R/W
TCDT
0000--00B
Output
compare 2/3
0000--00B
00006FH ROM mirror function selection register
ROMM
R/W
W
ROM mirror
function
selection
module
Reserved (for CAN0 interface)
000080H
to
00008FH
Reserved (for CAN1 interface)
000090H
to
00009DH
Use prohibited
PACSR
R/W
---00000B
00000000B
00000000B
000070H
to
00007FH
Program address detection control
00009EH
status register
---00000B
00000000B
I/O timer
TCCS
XXXXXXXXB
Output
compare 0/1
R/W
00006DH
00006EH Timer counter control status register
----0000B
XXXXXXXXB
R/W
Timer counter data register
XXXXXXXXB
00000000B
16-bit reload
timer 1
000056H 16-bit timer register 1/16-bit reload
000057 register 1
00006CH
----0000B
XXXXXXXXB
000055H
H
Initial value
00000000B
R/W
000051H
000052H 16-bit timer register 0/16-bit reload
000053 register 0
Resource
Address
match
detection
function
-------1B
00000000B
467
APPENDIX A I/O Maps
Table A-1 I/O Map (5/6)
Address
Register
Delayed interrupt/cause issurance/
00009FH
cancellation register
0000A0H
Low-power consumption mode control
register
0000A1H Clock selection register
0000A2H
to
0000A4H
0000A5H
Abbrevia
Access
-tion
DIRR
R/W
LPMCR
R/W
CKSCR
R/W
Resource
Initial value
Delayed
interrupt
generation
module
-------0B
Low-power
control circuit
00011000B
11111100B
Use prohibited
Automatic ready function selection
register
ARSR
W
External
memory
access
0011--00B
0000A6H External address output control register
HACR
0000A7H Bus control signal selection register
ECSR
0000A8H Watch-dog timer control register
WDTC
R/W
Watch-dog
timer
XXXXX111B
0000A9H Timebase timer control register
TBTC
R/W
Timebase
timer
1--00100B
0000AAH Watch timer control register
WTC
R/W
Watch timer
1X000000B
0000ABH
to
0000ADH
Use prohibited
0000AEH Flash memory control status register
FMCS
Flash
memory
000X0000B
0000AFH
Use prohibited
0000B0H Interrupt control register 00
ICR00
0000B1H Interrupt control register 01
ICR01
0000B2H Interrupt control register 02
ICR02
0000B3H Interrupt control register 03
ICR03
0000B4H Interrupt control register 04
ICR04
468
00000000B
0000000-B
R/W
When write 00000111B
R/W
When read --000111B
When write 00000111B
R/W
When read --000111B
R/W
R/W
Interrupt
controller
When write 00000111B
When read --000111B
When write 00000111B
When read --000111B
R/W
When write 00000111B
When read --000111B
APPENDIX A I/O Maps
Table A-1 I/O Map (6/6)
Address
Register
Abbrevia
Access
-tion
0000B5H Interrupt control register 05
ICR05
0000B6H Interrupt control register 06
ICR06
0000B7H Interrupt control register 07
ICR07
0000B8H Interrupt control register 08
ICR08
0000B9H Interrupt control register 09
ICR09
0000BAH Interrupt control register 10
ICR10
0000BBH Interrupt control register 11
ICR11
0000BCH Interrupt control register 12
ICR12
0000BDH Interrupt control register 13
ICR13
0000BEH Interrupt control register 14
ICR14
0000BFH Interrupt control register 15
ICR15
0000C0H
to
0000FFH
When write 00000111B
R/W
When read --000111B
When write 00000111B
R/W
When read --000111B
When write 00000111B
R/W
When read --000111B
When write 00000111B
R/W
When read --000111B
R/W
Interrupt
controller
When write 00000111B
When read --000111B
When write 00000111B
R/W
When read --000111B
When write 00000111B
R/W
When read --000111B
When write 00000111B
R/W
When read --000111B
When write 00000111B
R/W
When read --000111B
When write 00000111B
R/W
When read --000111B
External area
R/W
PADR0
001FF3H
R/W
PADR1
XXXXXXXXB
R/W
R/W
001FF5H
When write 00000111B
R/W
001FF2H
001FF4H Program address detection register 1
Initial value
When read --000111B
001FF0H
001FF1H Program address detection register 0
Resource
XXXXXXXXB
Address
match
detection
function
XXXXXXXXB
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
469
APPENDIX A I/O Maps
Table A-2 I/O Map (1/2)
Address
Register
Abbreviation
Access
Resource
Initial value
003900H
Reload register L
PRLL0
R/W
003901H
Reload register H
PRLH0
R/W
003902H
Reload register L
PRLL1
R/W
003903H
Reload register H
PRLH1
R/W
XXXXXXXXB
003904H
Reload register L
PRLL2
R/W
XXXXXXXXB
003905H
Reload register H
PRLH2
R/W
003906H
Reload register L
PRLL3
R/W
003907H
Reload register H
PRLH3
R/W
XXXXXXXXB
003908H
Reload register L
PRLL4
R/W
XXXXXXXXB
003909H
Reload register H
PRLH4
R/W
00390AH
Reload register L
PRLL5
R/W
00390BH
Reload register H
PRLH5
R/W
XXXXXXXXB
00390CH
Reload register L
PRLL6
R/W
XXXXXXXXB
00390DH
Reload register H
PRLH6
R/W
00390EH
Reload register L
PRLL7
R/W
00390FH
Reload register H
PRLH7
R/W
XXXXXXXXB
XXXXXXXXB
003910H to
003917H
XXXXXXXXB
PPG
(ch0, ch1)
unit 0
PPG
(ch2, ch3)
unit 1
PPG
(ch4, ch5)
unit 2
PPG
(ch6, ch7)
unit 3
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Reserved
003918H
Input capture data register 0
IPCP0
R
003919H
Input capture data register 0
IPCP0
R
00391AH
Input capture data register 1
IPCP1
R
00391BH
Input capture data register 1
IPCP1
R
XXXXXXXXB
00391CH
Input capture data register 2
IPCP2
R
XXXXXXXXB
00391DH
Input capture data register 2
IPCP2
R
00391EH
Input capture data register 3
IPCP3
R
00391FH
Input capture data register 3
IPCP3
R
XXXXXXXXB
003920H
Input capture data register 4
IPCP4
R
XXXXXXXXB
003921H
Input capture data register 4
IPCP4
R
003922H
Input capture data register 5
IPCP5
R
003923H
Input capture data register 5
IPCP5
R
470
Input capture
0/1
Input capture
2/3
Input capture
4/5
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
APPENDIX A I/O Maps
Table A-2 I/O Map (2/2)
Address
•
•
•
Register
Abbreviation
Access
Resource
Initial value
003924H
Input capture data register 6
IPCP6
R
003925H
Input capture data register 6
IPCP6
R
003926H
Input capture data register 7
IPCP7
R
003927H
Input capture data register 7
IPCP7
R
XXXXXXXXB
003928H
Output compare register 0
OCCP0
R/W
XXXXXXXXB
003929H
Output compare register 0
OCCP0
R/W
00392AH
Output compare register 1
OCCP1
R/W
00392BH
Output compare register 1
OCCP1
R/W
XXXXXXXXB
00392CH
Output compare register 2
OCCP2
R/W
XXXXXXXXB
00392DH
Output compare register 2
OCCP2
R/W
00392EH
Output compare register 3
OCCP3
R/W
00392FH
Output compare register 3
OCCP3
R/W
003930H to
0039FFH
Reserved
003A00H to
003AFFH
Reserved (for CAN0 interface)
003B00H to
003BFFH
Reserved (for CAN0 interface)
003C00H to
003CFFH
Reserved (for CAN1 interface)
003D00H to
003DFFH
Reserved (for CAN1 interface)
003E00H to
003FFFH
Reserved
XXXXXXXXB
Input capture
6/7
Output
compare 0/1
Output
compare 2/3
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
In the Initial value column, "0" indicates that the initial value is "0", "1" indicates that the initial value is "1", "X"
indicates that the initial value is undefined, and "-" indicates that the initial value is undefined (no value).
Address 00FFH and later are reserved. The external bus access signal is impossible.
The boundary (#H) between the RAM area and reserved area depends on the model.
Note:
For bits to which values can be written, the values initialized by a reset are those written in the Initial
value column. These values are not read values.
The LPMCR/CKSCR/WDTC bits are not always be initialized by a reset. Whether they are initialized
depends on the reset type. The values initialized by a reset are listed in the Initial value column for
these registers.
471
APPENDIX A I/O Maps
•
•
•
Free Running timer 2 is used for compare registers 0 to 3, and free running timer 1 is used for 4 to 7. Free
Running timer 1 is also used for the input capture.
Explanation of write and read
R/W: Both read and write enabled
R: Only read enabled
W: Only write enabled
Explanation of initial values
0: The initial value of this bit is "0".
1: The initial value of this bit is "1".
X: The initial value of this bit is undefined.
-: This bit is not used, and the initial value is undefined.
Note:
Any write access to reserved addresses in I/O map should not be performed.
A read access to reserved address results in reading "X".
472
APPENDIX B Instructions
APPENDIX B Instructions
APPENDIX B describes the instructions used by the F2MC-16LX.
B.1 Instruction Types
B.2 Addressing
B.3 Direct Addressing
B.4 Indirect Addressing
B.5 Execution Cycle Count
B.6 Effective address field
B.7 How to Read the Instruction List
B.8 F2MC-16LX Instruction List
B.9 Instruction Map
Code: CM44-00202-1E
473
APPENDIX B Instructions
B.1
Instruction Types
The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an
effective address field of each instruction or using the instruction code itself.
■
Instruction Types
The F2MC-16LX supports the following 351 types of instructions:
474
•
41 transfer instructions (byte)
•
38 transfer instructions (word or long word)
•
42 addition/subtraction instructions (byte, word, or long word)
•
12 increment/decrement instructions (byte, word, or long word)
•
11 comparison instructions (byte, word, or long word)
•
11 unsigned multiplication/division instructions (word or long word)
•
11 signed multiplication/division instructions (word or long word)
•
39 logic instructions (byte or word)
•
6 logic instructions (long word)
•
6 sign inversion instructions (byte or word)
•
1 normalization instruction (long word)
•
18 shift instructions (byte, word, or long word)
•
50 branch instructions
•
6 accumulator operation instructions (byte or word)
•
28 other control instructions (byte, word, or long word)
•
21 bit operation instructions
•
10 string instructions
APPENDIX B Instructions
B.2
Addressing
With the F2MC-16LX, the address format is determined by the instruction effective
address field or the instruction code itself (implied). When the address format is
determined by the instruction code itself, specify an address in accordance with the
instruction code used. Some instructions permit the user to select several types of
addressing.
■
Addressing
The F2MC-16LX supports the following 23 types of addressing:
•
Immediate (#imm)
•
Register direct
•
Direct branch address (addr16)
•
Physical direct branch address (addr24)
•
I/O direct (io)
•
Abbreviated direct address (dir)
•
Direct address (addr16)
•
I/O direct bit address (io:bp)
•
Abbreviated direct bit address (dir:bp)
•
Direct bit address (addr16:bp)
•
Vector address (#vct)
•
Register indirect (@RWj j = 0 to 3)
•
Register indirect with post increment (@RWj+ j = 0 to 3)
•
Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
•
Long register indirect with displacement (@RLi + disp8 i = 0 to 3)
•
Program counter indirect with displacement (@PC + disp16)
•
Register indirect with base index (@RW0 + RW7, @RW1 + RW7)
•
Program counter relative branch address (rel)
•
Register list (rlst)
•
Accumulator indirect (@A)
•
Accumulator indirect branch address (@A)
•
Indirectly-specified branch address (@ear)
•
Indirectly-specified branch address (@eam)
475
APPENDIX B Instructions
■
Effective Address Field
Table B.2-1 lists the address formats specified by the effective address field.
Table B.2-1 Effective Address Field
Code
Representation
00
R0
RW0
RL0
01
R1
RW1
(RL0)
02
R2
RW2
RL1
03
R3
RW3
(RL1)
04
R4
RW4
RL2
05
R5
RW5
(RL2)
06
R6
RW6
RL3
07
R7
RW7
(RL3)
08
@RW0
09
@RW1
Address format
Default bank
Register direct: Individual parts correspond to the
byte, word, and long word types in order from the
left.
None
DTB
DTB
Register indirect
0A
@RW2
ADB
0B
@RW3
SPB
0C
@RW0+
DTB
0D
@RW1+
DTB
Register indirect with post increment
0E
@RW2+
ADB
0F
@RW3+
SPB
10
@RW0+disp8
DTB
11
@RW1+disp8
DTB
Register indirect with 8-bit displacement
12
@RW2+disp8
ADB
13
@RW3+disp8
SPB
14
@RW4+disp8
DTB
15
@RW5+disp8
DTB
Register indirect with 8-bit displacement
16
@RW6+disp8
ADB
17
@RW7+disp8
SPB
18
@RW0+disp16
DTB
19
@RW1+disp16
DTB
Register indirect with 16-bit displacement
476
1A
@RW2+disp16
ADB
1B
@RW3+disp16
SPB
1C
@RW0+RW7
Register indirect with index
DTB
1D
@RW1+RW7
Register indirect with index
DTB
1E
@PC+disp16
PC indirect with 16-bit displacement
PCB
1F
addr16
Direct address
DTB
APPENDIX B Instructions
B.3
Direct Addressing
An operand value, register, or address is specified explicitly in direct addressing mode.
■
Direct Addressing
● Immediate addressing (#imm)
Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32).
Figure B.3-1 Example of Immediate Addressing (#imm)
MOVW A, #01212H (This instruction stores the operand value in A.)
Before execution
A 2233
4455
After execution
A 4455
1 2 1 2 (Some instructions transfer AL to AH.)
● Register direct addressing
Specify a register explicitly as an operand. Table B.3-1 lists the registers that can be specified. Figure B.3-2
shows an example of register direct addressing.
Table B.3-1 Direct Addressing Registers
General-purpose register
Special-purpose register
Byte
R0, R1, R2, R3, R4, R5, R6, R7
Word
RW0, RW1, RW2, RW3, RW4, RW5, RW6,
RW7
Long word
RL0, RL1, RL2, RL3
Accumulator
A, AL
Pointer
SP *
Bank
PCB, DTB, USB, SSB, ADB
Page
DPR
Control
PS, CCR, RP, ILM
*: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on
the value of the S flag bit in the condition code register (CCR). For branch instructions, the program
counter (PC) is not specified in an instruction operand but is specified implicitly.
477
APPENDIX B Instructions
Figure B.3-2 Example of Register Direct Addressing
MOV R0, A (This instruction transfers the eight low-order bits of A to the generalpurpose register R0.)
Before execution
A 0716
2534
Memory space
R0
After execution
A 0716
2564
??
Memory space
R0
34
● Direct branch addressing (addr16)
Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which
indicates the branch destination in the logical address space. Direct branch addressing is used for an
unconditional branch, subroutine call, or software interrupt instruction. Bit23 to bit16 of the address are
specified by the program counter bank register (PCB).
Figure B.3-3 Example of Direct Branch Addressing (addr16)
JMP 3B20H (This instruction causes an unconditional branch by direct branch
addressing in a bank.)
Before execution
After execution
478
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
62
4F3C21H
20
4F3C22H
3B
JMP 3B20H
APPENDIX B Instructions
● Physical direct branch addressing (addr24)
Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical
direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction.
Figure B.3-4 Example of Direct Branch Addressing (addr24)
JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit
addressing.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 3 3
Memory space
333B20H
Next instruction
4F3C20H
63
4F3C21H
20
4F3C22H
3B
4F3C23H
33
JMPP 333B20H
● I/O direct addressing (io)
Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the
physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB)
and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an
instruction using I/O direct addressing.
Figure B.3-5 Example of I/O Direct Addressing (io)
MOVW A, i : 0C0H (This instruction reads data by I/O direct addressing and stores it
in A.)
Before execution
After execution
A 0716
2534
Memory space
0000C0H
EE
0000C1H
FF
A 2534 FFEE
479
APPENDIX B Instructions
● Abbreviated direct addressing (dir)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB).
Figure B.3-6 Example of Abbreviated Direct Addressing (dir)
MOV S : 20H, A (This instruction writes the contents of the eight low-order bits of A in
abbreviated direct addressing mode.)
Before execution
A 4455
DPR 6 6
After execution
A 4455
DPR 6 6
1212
DTB 7 7
Memory space
776620H
1212
DTB 7 7
??
Memory space
776620H
12
● Direct addressing (addr16)
Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are
specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for
this mode of addressing.
Figure B.3-7 Example of Direct Addressing (addr16)
MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.)
Before execution
After execution
480
A 2020
A AABB
AABB
0123
DTB 5 5
DTB 5 5
Memory space
553B21H
01
553B20H
23
APPENDIX B Instructions
● I/O direct bit addressing (io:bp)
Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp",
where the larger number indicates the most significant bit (MSB) and the lower number indicates the least
significant bit (LSB).
Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp)
SETB i : 0C1H : 0 (This instruction sets bits by I/O direct bit addressing.)
Memory space
Before execution
0000C1H
00
Memory space
After execution
0000C1H
01
● Abbreviated direct bit addressing (dir:bp)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure B.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp)
SETB S : 10H : 0 (This instruction sets bits by abbreviated direct bit addressing.)
Memory space
Before execution
DTB 5 5
DPR 6 6
556610H
00
Memory space
After execution
DTB 5 5
DPR 6 6
556610H
01
● Direct bit addressing (addr16:bp)
Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure B.3-10 Example of Direct Bit Addressing (addr16:bp)
SETB 2222H : 0 (This instruction sets bits by direct bit addressing.)
Memory space
Before execution
DTB 5 5
552222H
00
Memory space
After execution
DTB 5 5
552222H
01
481
APPENDIX B Instructions
● Vector Addressing (#vct)
Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector
numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction.
Figure B.3-11 Example of Vector Addressing (#vct)
CALLV #15 (This instruction causes a branch to the address indicated by the interrupt
vector specified in an operand.)
Before execution
PC 0 0 0 0
Memory space
PCB F F
After execution
FFC000H
EF
CALLV #15
PC D 0 0 0
PCB F F
FFFFE0H
00
FFFFE1H
D0
Table B.3-2 CALLV Vector List
Instruction
Vector address L
Vector address H
CALLV #0
XXFFFEH
XXFFFFH
CALLV #1
XXFFFCH
XXFFFDH
CALLV #2
XXFFFAH
XXFFFBH
CALLV #3
XXFFF8H
XXFFF9H
CALLV #4
XXFFF6H
XXFFF7H
CALLV #5
XXFFF4H
XXFFF5H
CALLV #6
XXFFF2H
XXFFF3H
CALLV #7
XXFFF0H
XXFFF1H
CALLV #8
XXFFEEH
XXFFEFH
CALLV #9
XXFFECH
XXFFEDH
CALLV #10
XXFFEAH
XXFFEBH
CALLV #11
XXFFE8H
XXFFE9H
CALLV #12
XXFFE6H
XXFFE7H
CALLV #13
XXFFE4H
XXFFE5H
CALLV #14
XXFFE2H
XXFFE3H
CALLV #15
XXFFE0H
XXFFE1H
Note: A PCB register value is set in XX.
Note:
When the program counter bank register (PCB) is FFH, the vector area overlaps the vector area of
INT #vct8 (#0 to #7). Use vector addressing carefully (see Table B.3-2).
482
APPENDIX B Instructions
B.4
Indirect Addressing
In indirect addressing mode, an address is specified indirectly by the address data of an
operand.
■
Indirect Addressing
● Register indirect addressing (@RWj j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to
23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register
(SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when
RW2 is used.
Figure B.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3)
MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores
it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 0 F
DTB 7 8
● Register indirect addressing with post increment (@RWj+ j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. After operand
operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word).
Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system
stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank
register (ADB) when RW2 is used.
If the post increment results in the address of the register that specifies the increment, the incremented
value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to
writing by an instruction and, therefore, the register that would be incremented becomes write data.
483
APPENDIX B Instructions
Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3)
MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post
increment and stores it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 1 1
DTB 7 8
● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
Memory is accessed using the address obtained by adding an offset to the contents of general-purpose
register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric
values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or
RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is
used, or additional data bank register (ADB) when RW2 or RW6 is used.
Figure B.4-3 Example of Register Indirect Addressing with Offset
(@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+10H)
RW1 D 3 0 F
After execution
A 2534 FFEE
RW1 D 3 0 F
484
DTB 7 8
DTB 7 8
Memory space
78D31FH
EE
78D320H
FF
APPENDIX B Instructions
● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the
contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value.
Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3)
MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+25H)
RL2 F 3 8 2
After execution
4B02
Memory space
824B27H
EE
824B28H
FF
A 2534 FFEE
RL2 F 3 8 2
4B02
● Program counter indirect addressing with offset (@PC + disp16)
Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one
word long. Address bits 16 to 23 are specified by the program counter bank register (PCB). Note that the
operand address of each of the following instructions is not deemed to be (next instruction address +
disp16):
•
DBNZ eam, rel
•
DWBNZ eam, rel
•
CBNE eam, #imm8, rel
•
CWBNE eam, #imm16, rel
•
MOV eam, #imm8
•
MOVW eam, #imm16
Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16)
MOVW A, @PC+20H (This instruction reads data by program counter indirect
addressing with an offset and stores it in A.)
Before execution
A 0716
2534
Memory space
PCB C 5 PC 4 5 5 6
After execution
A 2534
FFEE
PCB C 5 PC 4 5 5 A
+4
C54556H
73
C54557H
9E
C54558H
20
C54559H
00
MOVW
A, @PC+20H
C5455AH
.
.
.
+20H
C5457AH
EE
C5457BH
FF
485
APPENDIX B Instructions
● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7)
Memory is accessed using the address determined by adding RW0 or RW1 to the contents of generalpurpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB).
Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7)
MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with
a base index and stores it in A.)
Before execution
A 0716
RW1 D 3 0 F
WR7 0 1 0 1
After execution
A 2534
RW1 D 3 0 F
WR7 0 1 0 1
486
2534
+
DTB 7 8
FFEE
DTB 7 8
Memory space
78D410H
EE
78D411H
FF
APPENDIX B Instructions
● Program counter relative branch addressing (rel)
The address of the branch destination is a value determined by adding an 8-bit offset to the program
counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is
not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte
bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to
23 are indicated by the program counter bank register (PCB).
Figure B.4-7 Example of Program Counter Relative Branch Addressing (rel)
BRA 10H (This instruction causes an unconditional relative branch.)
Before execution
After execution
PC 3 C 2 0
PC 3 C 3 2
PCB 4 F
PCB 4 F
Memory space
4F3C32H
Next instruction
4F3C21H
10
4F3C20H
60
BRA 10H
● Register list (rlst)
Specify a register to be pushed onto or popped from a stack.
Figure B.4-8 Configuration of the Register List
MSB
LSB
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
A register is selected when the corresponding bit is 1 and deselected when the bit is 0.
487
APPENDIX B Instructions
Figure B.4-9 Example of Register List (rlist)
POPW, RW0, RW4 (This instruction transfers memory data indicated by the SP to
multiple word registers indicated by the register list.)
SP
34FA
SP
34FE
RW0
×× ××
RW0
02 01
RW1
×× ××
RW1
×× ××
RW2
×× ××
RW2
×× ××
RW3
×× ××
RW3
×× ××
RW4
×× ××
RW4
04 03
RW5
×× ××
RW5
×× ××
RW6
×× ××
RW6
×× ××
RW7
×× ××
RW7
×× ××
Memory space
SP
Memory space
01
34FAH
01
34FAH
02
34FBH
02
34FBH
03
34FCH
03
34FCH
04
34FDH
04
34FDH
34FEH
SP
Before execution
34FEH
After execution
● Accumulator indirect addressing (@A)
Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the
accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB).
Figure B.4-10 Example of Accumulator Indirect Addressing (@A)
MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.)
Before execution
A
0716
2534
DTB B B
After execution
A
0716
DTB B B
488
FFEE
Memory space
BB2534H
EE
BB2535H
FF
APPENDIX B Instructions
● Accumulator indirect branch addressing (@A)
The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the
accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are
specified by the program counter bank register (PCB). For the Jump Context (JCTX) instruction, however,
address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for
unconditional branch instructions.
Figure B.4-11 Example of Accumulator Indirect Branch Addressing (@A)
JMP @A (This instruction causes an unconditional branch by accumulator indirect
branch addressing.)
Before execution
PC 3 C 2 0
A 6677
After execution
PC 3 B 2 0
A 6677
PCB 4 F
3B20
Memory space
4F3B20H
Next instruction
4F3C20H
61
JMP @A
PCB 4 F
3B20
● Indirect specification branch addressing (@ear)
The address of the branch destination is the word data at the address indicated by ear.
Figure B.4-12 Example of Indirect Specification Branch Addressing (@ear)
JMP @@RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
After execution
PC 3 C 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
PC 3 B 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
Memory space
217F48H
20
217F49H
3B
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
08
JMP @@RW0
489
APPENDIX B Instructions
● Indirect specification branch addressing (@eam)
The address of the branch destination is the word data at the address indicated by eam.
Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam)
JMP @RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
PC 3 C 2 0
PCB 4 F
RW0 3 B 2 0
After execution
PC 3 B 2 0
RW0 3 B 2 0
490
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
00
JMP @RW0
APPENDIX B Instructions
B.5
Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is
obtained by adding the number of cycles required for each instruction, "correction
value" determined by the condition, and the number of cycles for instruction fetch.
■
Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is obtained by adding the
number of cycles required for each instruction, "correction value" determined by the condition, and the
number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal
ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments.
Therefore, intervening in data access increases the execution cycle count.
Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the
program fetches every byte of an instruction being executed. Therefore, intervening in data access increases
the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register,
internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the
cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register.
Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add
the "access count x cycle count for the halt" as a correction value to the normal execution count.
491
APPENDIX B Instructions
■
Calculating the Execution Cycle Count
Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data.
Table B.5-1 Execution Cycle Counts in Each Addressing Mode
(a) *
Code
Operand
00
|
07
Ri
Rwi
RLi
08
|
0B
Execution cycle count in
each addressing mode
Register access count in
each addressing mode
See the instruction list.
See the instruction list.
@RWj
2
1
0C
|
0F
@RWj+
4
2
10
|
17
@RWi+disp8
2
1
18
|
1B
@RWi+disp16
2
1
1C
1D
1E
1F
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
4
4
2
1
2
2
0
0
*: (a) is used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List".
492
APPENDIX B Instructions
Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles
(b) byte *
Operand
(c) word *
(d) long *
Cycle
count
Access
count
Cycle
count
Access
count
Cycle
count
Access
count
Internal register
+0
1
+0
1
+0
2
Internal memory
Even address
+0
1
+0
1
+0
2
Internal memory
Odd address
+0
1
+2
2
+4
4
External data bus
16-bit even address
+1
1
+1
1
+2
2
External data bus
16-bit odd address
+1
1
+4
2
+8
4
External data bus
8-bits
+1
1
+4
2
+8
4
*: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction
List".
Note:
When an external data bus is used, the cycle counts during which an instruction is made to wait by
ready input or automatic ready must also be added.
Table B.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
-
+2
External data bus 16-bits
-
+3
External data bus 8-bits
+3
-
Notes:
• When an external data bus is used, the cycle counts during which an instruction is made to wait
by ready input or automatic ready must also be added.
• Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the
correction values to calculate the worst case.
493
APPENDIX B Instructions
B.6
Effective address field
Table B.6-1 shows the effective address field.
■
Effective Address Field
Table B.6-1 Effective Address Field
Code
Representation
00
01
02
03
04
05
06
07
08
09
0A
R0
R1
R2
R3
R4
R5
R6
R7
@RW0
@RW1
@RW2
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
0B
0C
0D
0E
0F
10
11
12
13
14
15
@RW3
@RW0+
@RW1+
@RW2+
@RW3+
@RW0+disp8
@RW1+disp8
@RW2+disp8
@RW3+disp8
@RW4+disp8
@RW5+disp8
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Address format
Byte count of
extended
address part *
Register direct: Individual parts correspond to
the byte, word, and long word types in order
from the left.
-
Register indirect
0
Register indirect with post increment
0
Register indirect with 8-bit displacement
1
16
@RW6+disp8
17
@RW7+disp8
18
@RW0+disp16
19
@RW1+disp16
Register indirect with 16-bit displacement
2
1A
@RW2+disp16
1B
@RW3+disp16
1C
@RW0+RW7
Register indirect with index
0
1D
@RW1+RW7
Register indirect with index
0
1E
@PC+disp16
PC indirect with 16-bit displacement
2
1F
addr16
Direct address
2
*1: Each byte count of the extended address part applies to + in the # (byte count) column in "B.8 F2MC-16LX
Instruction List".
494
APPENDIX B Instructions
B.7
How to Read the Instruction List
Table B.7-1 describes the items used in "B.8 F2MC-16LX Instruction List", and Table
B.7-2 describes the symbols used in the same list.
■
Description of Instruction Presentation Items and Symbols
Table B.7-1 Description of Items in the Instruction List (1/2)
Item
Mnemonic
Description
Uppercase, symbol: Represented as is in the assembler.
Lowercase: Rewritten in the assembler.
Number of following lowercase: Indicates bit length in the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
See Table B.2-1 for the alphabetical letters in items.
RG
B
Operation
Indicates the number of times a register access is performed during instruction
execution.
The number is used to calculate the correction value for CPU intermittent
operation.
Indicates the correction value used to calculate the actual number of cycles during
instruction execution.
The actual number of cycles during instruction execution can be determined by
adding the value in the ~ column to this value.
Indicates the instruction operation.
LH
Indicates the special operation for bit15 to bit08 of the accumulator.
Z: Transfers 0.
X: Transfers after sign extension.
-: No transfer
AH
Indicates the special operation for the 16 high-order bits of the accumulator.
*: Transfers from AL to AH.
-: No transfer
Z: Transfers 00 to AH.
X: Transfers 00H or FFH to AH after AL sign extension.
495
APPENDIX B Instructions
Table B.7-1 Description of Items in the Instruction List (1/2)
Item
Description
I
Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N
(negative), Z (zero), V (overflow), C (carry).
*: Changes upon instruction execution.
-: No change
S: Set upon instruction execution.
R: Reset upon instruction execution.
S
T
N
Z
V
C
RMW
Indicates whether the instruction is a Read Modify Write instruction (reading data
from memory by the I instruction and writing the result to memory).
*: Read Modify Write instruction
-: Not Read Modify Write instruction
Note:
Cannot be used for an address that has different meanings between read and
write operations.
Table B.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
A
496
Explanation
The bit length used varies depending on the 32-bit accumulator instruction.
Byte: Low-order 8 bits of byte AL
Word: 16 bits of word AL
Long word: 32 bits of AL and AH
AH
16 high-order bits of A
AL
16 low-order bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
program counter bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
APPENDIX B Instructions
Table B.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
Ri
Explanation
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
Direct addressing
addr24
Physical direct addressing
ad24 0-15
Bit0 to bit15 of addr24
ad24 16-23
Bit16 to bit23 of addr24
io
I/O area (000000H to 0000FFH)
#imm4
4-bit immediate data
#imm8
8-bit immediate data
#imm16
16-bit immediate data
#imm32
32-bit immediate data
ext (imm8)
16-bit data obtained by sign extension of 8-bit immediate data
disp8
8-bit displacement
disp16
16-bit displacement
bp
Bit offset
vct4
Vector number (0 to 15)
vct8
Vector number (0 to 255)
( )b
Bit address
rel
PC relative branch
ear
Effective addressing (code 00 to 07)
eam
Effective addressing (code 08 to 1F)
rlst
Register list
497
APPENDIX B Instructions
B.8
F2MC-16LX Instruction List
Table B.8-1 to Table B.8-18 list the instructions used by the F2MC-16LX.
■
F2MC-16LX Instruction List
Table B.8-1 41 Transfer Instructions (Byte)
Mnemonic
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
XCH
XCH
XCH
XCH
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RLi+disp8
A,#imm4
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
Ri,A
ear,A
eam,A
io,A
@RLi+disp8,A
Ri,ear
Ri,eam
ear,Ri
eam,Ri
Ri,#imm8
io,#imm8
dir,#imm8
ear,#imm8
eam,#imm8
@AL,AH
A,ear
A,eam
Ri,ear
Ri,eam
#
~
RG
B
2
3
1
2
2+
2
2
2
3
1
2
3
2
2
2+
2
2
2
2
3
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
2
2+
2
2+
3
4
2
2
3 + (a)
3
2
3
10
1
3
4
2
2
3 + (a)
3
2
3
5
10
3
4
2
2
3 + (a)
3
10
3
4 + (a)
4
5 + (a)
2
5
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
0
0
1
1
0
0
0
0
2
0
0
0
1
1
0
0
0
0
1
2
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
2
0
4
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
0
2 × (b)
0
2 × (b)
Operation
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi)+disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
Z
Z
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table.
498
APPENDIX B Instructions
Table B.8-2 38 Transfer Instructions (Word, Long Word)
Mnemonic
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW
XCHW
XCHW
MOVL
MOVL
MOVL
MOVL
MOVL
A,dir
A,addr16
A,SP
A,RWi
A,ear
A,eam
A,io
A,@A
A,#imm16
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
SP,A
RWi,A
ear,A
eam,A
io,A
@RWi+disp8,A
@RLi+disp8,A
RWi,ear
RWi,eam
ear,RWi
eam,RWi
RWi,#imm16
io,#imm16
ear,#imm16
eam,#imm16
@AL,AH
A,ear
A,eam
RWi, ear
RWi, eam
A,ear
A,eam
A,#imm32
ear,A
eam,A
#
~
RG
B
2
3
1
1
2
2+
2
2
3
2
3
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
2
2
2+
2
2+
2
2+
5
2
2+
3
4
1
2
2
3 + (a)
3
3
2
5
10
3
4
1
2
2
3 + (a)
3
5
10
3
4 + (a)
4
5 + (a)
2
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
4
5 + (a)
3
4
5 + (a)
0
0
0
1
1
0
0
0
0
1
2
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
0
2
0
4
2
2
0
0
2
0
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
0
(c)
0
(c)
0
(c)
0
(c)
(c)
0
2 × (c)
0
2 × (c)
0
(d)
0
0
(d)
Operation
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi)+disp8)
word (A) ← ((RLi)+disp8)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
word ((RWi)+disp8) ← (A)
word ((RLi)+disp8) ← (A)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
word (ear) ← imm16
word (eam) ← imm16
word ((A)) ← (AH)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
long (ear) ← (A)
long(eam) ← (A)
LH
AH
I
S
T
N
Z
V
C
RMW
-
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a), (c), and (d) in the table.
499
APPENDIX B Instructions
Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
ADDW
ADDW
ADDW
ADDW
ADDW
ADDW
ADDCW
ADDCW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBCW
SUBCW
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A,ear
A,eam
A,#imm32
A,ear
A,eam
A,#imm32
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
2+
5
2
2+
5
2
3
4+(a)
2
3
5+(a)
3
4+(a)
2
3
4+(a)
2
3
5+(a)
3
4+(a)
6
7+(a)
4
6
7+(a)
4
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
2
0
0
2
0
0
0
0
(c)
0
0
2 × (c)
0
(c)
0
0
(c)
0
0
2 × (c)
0
(c)
0
(d)
0
0
(d)
0
Operation
byte (A) ← (A) + imm8
byte (A) ← (A) + (dir)
byte (A) ← (A) + (ear)
byte (A) ← (A) + (eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear)+ (C)
byte (A) ← (A) + (eam)+ (C)
byte (A) ← (AH) + (AL) + (C)
(decimal)
byte (A) ← (A) - imm8
byte (A) ← (A) - (dir)
byte (A) ← (A) - (ear)
byte (A) ← (A) - (eam)
byte (ear) ← (ear) - (A)
byte (eam) ← (eam) - (A)
byte (A) ← (AH) - (AL) - (C)
byte (A) ← (A) - (ear) - (C)
byte (A) ← (A) - (eam) - (C)
byte (A) ← (AH) - (AL) - (C)
(decimal)
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) - (AL)
word (A) ← (A) - (ear)
word (A) ← (A) - (eam)
word (A) ← (A) - imm16
word (ear) ← (ear) - (A)
word (eam) ← (eam) - (A)
word (A) ← (A) - (ear) - (C)
word (A) ← (A) - (eam) - (C)
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
long (A) ← (A) - (ear)
long (A) ← (A) - (eam)
long (A) ← (A) - imm32
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
500
APPENDIX B Instructions
Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
INC
ear
2
3
2
0
INC
eam
2+
5+(a)
0
2 × (b)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
byte (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
byte (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DEC
ear
2
3
2
0
byte (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
DEC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
INCW
ear
2
3
2
0
word (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
INCW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DECW
ear
2
3
2
0
DECW
eam
2+
5+(a)
0
2 × (c)
INCL
ear
2
7
4
0
INCL
eam
2+
9+(a)
0
2 × (d)
DECL
ear
2
7
4
0
DECL
eam
2+
9+(a)
0
2 × (d)
word (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
word (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
Table B.8-5 11 Compare Instructions (Byte, Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
CMP
Mnemonic
A
1
1
0
0
byte (AH) - (AL)
Operation
-
-
-
-
-
*
*
*
*
-
CMP
A,ear
2
2
1
0
byte (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMP
A,eam
2+
3+(a)
0
(b)
byte (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMP
A,#imm8
2
2
0
0
byte (A) - imm8
-
-
-
-
-
*
*
*
*
-
CMPW
A
1
1
0
0
word (AH) - (AL)
-
-
-
-
-
*
*
*
*
-
CMPW
A,ear
2
2
1
0
word (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPW
A,eam
2+
3+(a)
0
(c)
word (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPW
A,#imm16
3
2
0
0
word (A) - imm16
-
-
-
-
-
*
*
*
*
-
CMPL
A,ear
2
6
2
0
long (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPL
A,eam
2+
7+(a)
0
(d)
long (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPL
A,#imm32
5
3
0
0
long (A) - imm32
-
-
-
-
-
*
*
*
*
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
501
APPENDIX B Instructions
Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIVU
A
1
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
-
-
-
-
-
-
-
*
*
-
DIVU
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
-
-
-
-
-
-
-
*
*
-
DIVU
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MULU
A
1
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,eam
2+
*10
0
(b)
MULUW
A
1
*11
0
0
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,ear
2
*12
1
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,eam
2+
*13
0
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
*1: 3: Division by 0 7: Overflow 15: Normal
*2: 4: Division by 0 8: Overflow 16: Normal
*3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal
*4: 4: Division by 0 7: Overflow 22: Normal
*5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal
*6: (b): Division by 0 or overflow 2 × (b): Normal
*7: (c): Division by 0 or overflow 2 × (c): Normal
*8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0.
*9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0.
*10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0.
*11: 3: Word (AH) is 0. 11: Word (AH) is not 0.
*12: 4: Word (ear) is 0. 12: Word (ear) is not 0.
*13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0.
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
502
APPENDIX B Instructions
Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIV
A
2
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
Z
-
-
-
-
-
-
*
*
-
DIV
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
Z
-
-
-
-
-
-
*
*
-
DIV
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
Z
-
-
-
-
-
-
*
*
-
DIVW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MUL
A
2
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,eam
2+
*10
0
(b)
MULW
A
2
*11
0
0
MULW
A,ear
2
*12
1
MULW
A,eam
2+
*13
0
*1:
*2:
*3:
*4:
3: Division by 0, 8 or 18: Overflow, 18: Normal
4: Division by 0, 11 or 22: Overflow, 23: Normal
5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal
When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal
When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal
*5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal
When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal
*6: (b): Division by 0 or overflow, 2 × (b): Normal
*7: (c): Division by 0 or overflow, 2 × (c): Normal
*8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative
*9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative
*10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative
*11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative
*12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative
*13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative
Notes:
• The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a
pre-operation count or a post-operation count depending on the detection timing.
• When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed.
• See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
503
APPENDIX B Instructions
Table B.8-8 39 Logic 1 Instructions (Byte, Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
AND
A,#imm8
2
2
0
0
byte (A) ← (A) and imm8
-
-
-
-
-
*
*
R
-
AND
A,ear
2
3
1
0
byte (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
AND
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
byte (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
byte (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
AND
ear,A
2
3
2
0
AND
eam,A
2+
5+(a)
0
2 × (b)
OR
A,#imm8
2
2
0
0
byte (A) ← (A) or imm8
-
-
-
-
-
*
*
R
-
-
OR
A,ear
2
3
1
0
byte (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
OR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
OR
ear,A
2
3
2
0
byte (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
OR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XOR
A,#imm8
2
2
0
0
byte (A) ← (A) xor imm8
-
-
-
-
-
*
*
R
-
-
XOR
A,ear
2
3
1
0
byte (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XOR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XOR
ear,A
2
3
2
0
byte (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XOR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOT
A
1
2
0
0
byte (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOT
ear
2
3
2
0
byte (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOT
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
ANDW
A
1
2
0
0
word (A) ← (AH) and (A)
-
-
-
-
-
*
*
R
-
-
ANDW
A,#imm16
3
2
0
0
word (A) ← (A) and imm16
-
-
-
-
-
*
*
R
-
-
ANDW
A,ear
2
3
1
0
word (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
word (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
word (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
0
word (A) ← (AH) or (A)
-
-
-
-
-
*
*
R
-
-
0
word (A) ← (A) or imm16
-
-
-
-
-
*
*
R
-
-
1
0
word (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
4+(a)
0
(c)
word (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
2
3
2
0
word (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XORW
A
1
2
0
0
word (A) ← (AH) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
A,#imm16
3
2
0
0
word (A) ← (A) xor imm16
-
-
-
-
-
*
*
R
-
-
XORW
A,ear
2
3
1
0
word (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
ear,A
2
3
2
0
ANDW
eam,A
2+
5+(a)
0
2 × (c)
ORW
A
1
2
0
ORW
A,#imm16
3
2
0
ORW
A,ear
2
3
ORW
A,eam
2+
ORW
ear,A
ORW
XORW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
XORW
ear,A
2
3
2
0
word (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOTW
A
1
2
0
0
word (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOTW
ear
2
3
2
0
word (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOTW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
504
APPENDIX B Instructions
Table B.8-9 6 Logic 2 Instructions (Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
ANDL
A,ear
2
6
2
0
long (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
ORL
A,ear
2
6
2
0
long (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
ORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
XORL
A,ear
2
6
2
0
long (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (d) in the table.
Table B.8-10 6 Sign Inversion Instructions (Byte, Word)
Mnemonic
NEG
A
#
~
RG
B
1
2
0
0
byte (A) ← 0 - (A)
byte (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
byte (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
word (A) ← 0 - (A)
-
-
-
-
-
*
*
*
*
-
NEG
ear
2
3
2
0
NEG
eam
2+
5+(a)
0
2 × (b)
NEGW
A
1
2
0
0
NEGW
ear
2
3
2
0
NEGW
eam
2+
5+(a)
0
2 × (c)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
X
-
-
-
-
*
*
*
*
-
word (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
word (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
Table B.8-11 1 Normalization Instruction (Long Word)
Mnemonic
NRML
A,R0
#
~
RG
B
2
*1
1
0
Operation
long (A) ← Shift left to the position where '1' is set
for the first time.
byte (R0) ← Shift count at that time
LH
AH
I
S
T
N
Z
V
C
RMW
-
-
-
-
-
-
*
-
-
-
*1: 4 when all accumulators have a value of 0; otherwise, 6+(R0)
505
APPENDIX B Instructions
Table B.8-12 18 Shift Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
RORC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
ear
2
3
2
0
byte (ear) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
*
ROLC
ear
2
3
2
0
byte (ear) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
*
ASR
A,R0
2
*1
1
0
byte (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSR
A,R0
2
*1
1
0
byte (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSL
A,R0
2
*1
1
0
byte (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRW
A
1
2
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSRW
A/SHRW A
1
2
0
0
word (A) ← Logical right shift (A, 1 bit)
-
-
-
-
*
R
*
-
*
-
LSLW
A/SHLW A
1
2
0
0
word (A) ← Logical left shift (A, 1 bit)
-
-
-
-
-
*
*
-
*
-
ASRW
A,R0
2
*1
1
0
word (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRW
A,R0
2
*1
1
0
word (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLW
A,R0
2
*1
1
0
word (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRL
A,R0
2
*2
1
0
long (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRL
A,R0
2
*2
1
0
long (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLL
A,R0
2
*2
1
0
long (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
*1: 6 when R0 is 0; otherwise, 5 + (R0)
*2: 6 when R0 is 0; otherwise, 6 + (R0)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table.
506
APPENDIX B Instructions
Table B.8-13 31 Branch 1 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
BZ/BEQ
rel
2
*1
0
0
Branch on (Z) = 1
-
-
-
-
-
-
-
-
-
-
BNZ/
BNE
rel
2
*1
0
0
Branch on (Z) = 0
-
-
-
-
-
-
-
-
-
-
BC/BLO
rel
2
*1
0
0
Branch on (C) = 1
-
-
-
-
-
-
-
-
-
-
BNC/
BHS
rel
2
*1
0
0
Branch on (C) = 0
-
-
-
-
-
-
-
-
-
-
BN
rel
2
*1
0
0
Branch on (N) = 1
-
-
-
-
-
-
-
-
-
-
BP
rel
2
*1
0
0
Branch on (N) = 0
-
-
-
-
-
-
-
-
-
-
BV
rel
2
*1
0
0
Branch on (V) = 1
-
-
-
-
-
-
-
-
-
-
BNV
rel
2
*1
0
0
Branch on (V) = 0
-
-
-
-
-
-
-
-
-
-
BT
rel
2
*1
0
0
Branch on (T) = 1
-
-
-
-
-
-
-
-
-
-
BNT
rel
2
*1
0
0
Branch on (T) = 0
-
-
-
-
-
-
-
-
-
-
BLT
rel
2
*1
0
0
Branch on (V) xor (N) = 1
-
-
-
-
-
-
-
-
-
-
BGE
rel
2
*1
0
0
Branch on (V) xor (N) = 0
-
-
-
-
-
-
-
-
-
-
BLE
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BGT
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BLS
rel
2
*1
0
0
Branch on (C) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BHI
rel
2
*1
0
0
Branch on (C) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BRA
rel
2
*1
0
0
Unconditional branch
-
-
-
-
-
-
-
-
-
-
JMP
@A
1
2
0
0
word (PC) ← (A)
-
-
-
-
-
-
-
-
-
-
JMP
addr16
3
3
0
0
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
JMP
@ear
2
3
1
0
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
JMP
@eam
2+
4+(a)
0
(c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
JMPP
@ear *3
2
5
2
0
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
JMPP
@eam *3
2+
6+(a)
0
(d)
JMPP
addr24
4
4
0
0
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
CALL
@ear *4
2
6
1
(c)
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
CALL
@eam *4
2+
7+(a)
0
2 × (c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
CALL
addr16 *5
3
6
0
(c)
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
CALLV
#vct4 *5
1
7
0
2 × (c)
Vector call instruction
-
-
-
-
-
-
-
-
-
-
CALLP
@ear *6
2
10
2
2 × (c)
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
CALLP
@eam *6
2+
11+(a)
0
*2
CALLP
addr24 *7
4
10
0
2 × (c)
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
*1: 4 when a branch is made; otherwise, 3
*2: 3 × (c) + (b)
*3: Read (word) of branch destination address
*4: W: Save to stack (word) R: Read (word) of branch destination address
*5: Save to stack (word)
*6: W: Save to stack (long word), R: Read (long word) of branch destination address
*7: Save to stack (long word)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
507
APPENDIX B Instructions
Table B.8-14 19 Branch 2 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S T N Z V C
RMW
CBNE
A,#imm8,rel
3
*1
0
0
Branch on byte (A) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
A,#imm16,rel
4
*1
0
0
Branch on word (A) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CBNE
ear,#imm8,rel
4
*2
1
0
Branch on byte (ear) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CBNE
eam,#imm8,rel *9
4+
*3
0
(b)
Branch on byte (eam) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
ear,#imm16,rel
5
*4
1
0
Branch on word (ear) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CWBNE
eam,#imm16,rel*9
5+
*3
0
(c)
Branch on word (eam) not equal to imm16
-
-
-
-
-
*
*
*
*
-
DBNZ
ear,rel
3
*5
2
0
byte (ear) ← (ear) - 1, Branch on (ear) not equal to 0
-
-
-
-
-
*
*
*
-
*
DBNZ
eam,rel
3+
*6
2
DWBNZ
ear,rel
3
*5
2
DWBNZ
eam,rel
3+
*6
2
2 × (b) byte (eam) ← (eam) - 1, Branch on (eam) not equal to 0
-
-
-
-
-
*
*
*
-
-
-
-
-
-
*
*
*
-
-
2 × (c) word (eam) ← (eam) - 1, Branch on (eam) not equal to 0
-
-
-
-
-
*
*
*
-
*
0
word (ear) ← (ear) - 1, Branch on (ear) not equal to 0
INT
#vct8
2
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT
addr16
3
16
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INTP
addr24
4
17
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
1
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT9
RETI
LINK
#imm8
UNLINK
1
*8
0
*7
Return from interrupt
-
-
*
*
*
*
*
*
*
-
2
6
0
(c)
Saves the old frame pointer in the stack upon entering the
function, then sets the new frame pointer and reserves the
local pointer area.
-
-
-
-
-
-
-
-
-
-
1
5
0
(c)
Recovers the old frame pointer from the stack upon exiting
the function.
-
-
-
-
-
-
-
-
-
-
RET
*10
1
4
0
(c)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
RETP
*11
1
6
0
(d)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
*1: 5 when a branch is made; otherwise, 4
*2: 13 when a branch is made; otherwise, 12
*3: 7+(a) when a branch is made; otherwise, 6+(a)
*4: 8 when a branch is made; otherwise, 7
*5: 7 when a branch is made; otherwise, 6
*6: 8+(a) when a branch is made; otherwise, 7+(a)
*7: 3 × (b) + 2 × (c) when jumping to the next interruption request; 6 × (c) when returning from the current interruption
*8: 15 when jumping to the next interruption request; 17 when returning from the current interruption
*9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction.
*10: Return from stack (word)
*11: Return from stack (long word)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
508
APPENDIX B Instructions
Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
PUSHW
A
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (A)
-
-
-
-
-
-
-
-
-
-
PUSHW
AH
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (AH)
-
-
-
-
-
-
-
-
-
-
PUSHW
PS
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (PS)
-
-
-
-
-
-
-
-
-
-
PUSHW
rlst
2
*3
*5
*4
(SP) ← (SP) - 2n, ((SP)) ← (rlst)
-
-
-
-
-
-
-
-
-
-
POPW
A
1
3
0
(c)
word (A) ← ((SP)), (SP) ← (SP) + 2
-
*
-
-
-
-
-
-
-
-
POPW
AH
1
3
0
(c)
word (AH) ← ((SP)), (SP) ← (SP) + 2
-
-
-
-
-
-
-
-
-
-
POPW
PS
1
4
0
(c)
word (PS) ← ((SP)), (SP) ← (SP) + 2
-
-
*
*
*
*
*
*
*
-
POPW
rlst
2
*2
*5
*4
(rlst) ← ((SP)), (SP) ← (SP) + 2n
-
-
-
-
-
-
-
-
-
-
JCTX
@A
1
14
0
6 × (c)
Context switch instruction
-
-
*
*
*
*
*
*
*
-
AND
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) and imm8
-
-
*
*
*
*
*
*
*
-
OR
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) or imm8
-
-
*
*
*
*
*
*
*
-
MOV
RP,#imm8
2
2
0
0
byte (RP) ← imm8
-
-
-
-
-
-
-
-
-
-
MOV
ILM,#imm8
2
2
0
0
byte (ILM) ← imm8
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,ear
2
3
1
0
word (RWi) ← ear
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,eam
2+
2+(a)
1
0
word (RWi) ← eam
-
-
-
-
-
-
-
-
-
-
MOVEA
A,ear
2
1
0
0
word (A) ← ear
-
*
-
-
-
-
-
-
-
-
MOVEA
A,eam
2+
1+(a)
0
0
word (A) ← eam
-
*
-
-
-
-
-
-
-
-
ADDSP
#imm8
2
3
0
0
word (SP) ← (SP) + ext(imm8)
-
-
-
-
-
-
-
-
-
-
ADDSP
#imm16
3
3
0
0
word (SP) ← (SP) + imm16
-
-
-
-
-
-
-
-
-
-
MOV
A,brg1
2
*1
0
0
byte (A) ← (brg1)
Z
*
-
-
-
*
*
-
-
-
MOV
brg2,A
-
2
1
0
0
byte (brg2) ← (A)
-
-
-
-
-
*
*
-
-
NOP
1
1
0
0
No operation
-
-
-
-
-
-
-
-
-
-
ADB
1
1
0
0
Prefix code for AD space access
-
-
-
-
-
-
-
-
-
-
DTB
1
1
0
0
Prefix code for DT space access
-
-
-
-
-
-
-
-
-
-
PCB
1
1
0
0
Prefix code for PC space access
-
-
-
-
-
-
-
-
-
-
SPB
1
1
0
0
Prefix code for SP space access
-
-
-
-
-
-
-
-
-
-
NCC
1
1
0
0
Prefix code for flag no-change
-
-
-
-
-
-
-
-
-
-
CMR
1
1
0
0
Prefix code for common register bank
-
-
-
-
-
-
-
-
-
-
*1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2
*2: 7 + 3 × (POP count) + 2 × (POP last register number), 7 when RLST = 0 (no transfer register)
*3: 29 + 3 × (PUSH count) - 3 × (PUSH last register number), 8 when RLST = 0 (no transfer register)
*4: (POP count) × (c) or (PUSH count) × (c)
*5: (POP count) or (PUSH count)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (c) in the table.
509
APPENDIX B Instructions
Table B.8-16 21 Bit Operand Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
MOVB
A,dir:bp
3
5
0
(b)
byte (A) ← (dir:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,addr16:bp
4
5
0
(b)
byte (A) ← (addr16:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,io:bp
3
4
0
(b)
byte (A) ← (io:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
dir:bp,A
3
7
0
2 × (b)
bit (dir:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
addr16:bp,A
4
7
0
2 × (b)
bit (addr16:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
io:bp,A
3
6
0
2 × (b)
bit (io:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
SETB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
*
CLRB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 0
-
-
-
-
-
-
-
-
-
CLRB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
CLRB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
BBC
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
io:bp,rel
4
*2
0
(b)
Branch on (io:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBS
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
io:bp,rel
4
*2
0
(b)
SBBS
addr16:bp,rel
5
*3
0
2 × (b)
Branch on (io:bp) b = 1
-
-
-
-
-
-
*
-
-
-
Branch on (addr16:bp) b = 1,
bit (addr16:bp) b ← 1
-
-
-
-
-
-
*
-
-
*
WBTS
io:bp
3
*4
0
WBTC
io:bp
3
*4
0
*5
Waits until (io:bp) b = 1
-
-
-
-
-
-
-
-
-
-
*5
Waits until (io:bp) b = 0
-
-
-
-
-
-
-
-
-
-
RMW
*1: 8 when a branch is made; otherwise, 7
*2: 7 when a branch is made; otherwise, 6
*3: 10 when the condition is met; otherwise, 9
*4: Undefined count
*5: Until the condition is met
Note:
See Table B.5-1 and Table B.5-2 for information on (b) in the table.
Table B.8-17 6 Accumulator Operation Instructions (Byte, Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
SWAP
Mnemonic
1
3
0
0
byte (A)0-7 ↔ (A)8-15
-
-
-
-
-
-
-
-
-
-
SWAPW
1
2
0
0
word (AH) ↔ (AL)
-
*
-
-
-
-
-
-
-
-
EXT
1
1
0
0
Byte sign extension
X
-
-
-
-
*
*
-
-
-
EXTW
1
2
0
0
Word sign extension
-
X
-
-
-
*
*
-
-
-
ZEXT
1
1
0
0
Byte zero extension
Z
-
-
-
-
R
*
-
-
-
ZEXTW
1
1
0
0
Word zero extension
-
Z
-
-
-
R
*
-
-
-
510
Operation
APPENDIX B Instructions
Table B.8-18 10 String Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
MOVS / MOVSI
2
*2
*5
*3
byte transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
MOVSD
2
*2
*5
*3
byte transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCEQ / SCEQI
2
*1
*8
*4
byte search @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCEQD
2
*1
*8
*4
byte search @AH- ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
FILS / FILSI
2
6m+6
*8
*3
byte fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
MOVSW / MOVSWI
2
*2
*5
*6
word transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
-
MOVSWD
2
*2
*5
*6
word transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCWEQ / SCWEQI
2
*1
*8
*7
word search @AH+ - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCWEQD
2
*1
*8
*7
word search @AH- - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
FILSW / FILSWI
2
6m+6
*8
*6
word fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
*1: 5 when RW0 is 0, 4 + 7 × (RW0) when the counter expires, or 7n + 5 when a match occurs
*2: 5 when RW0 is 0; otherwise, 4 + 8 × (RW0)
*3: (b) × (RW0) + (b) × (RW0) When the source and destination access different areas, calculate the (b) item individually.
*4: (b) × n
*5: 2 × (b) × (RW0)
*6: (c) × (RW0) + (c) × (RW0) When the source and destination access different areas, calculate the (c) item individually.
*7: (c) × n
*8: (b) × (RW0)
Note:
m: RW0 value (counter value), n: Loop count
See Table B.5-1 and Table B.5-2 for information on (b) and (c) in the table.
511
APPENDIX B Instructions
B.9
Instruction Map
Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction
map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F2MC-16LX
instruction map.
■
Structure of Instruction Map
Figure B.9-1 Structure of Instruction Map
Basic page map
Bit operation
instructions
Character string
operation
instructions
2-byte
instructions
: Byte 1
ea instructions × 9 : Byte 2
An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An
instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it
references byte 1, and can check the following one byte by referencing the map for byte 2. Figure B.9-2
shows the correspondence between an actual instruction code and instruction map.
512
APPENDIX B Instructions
Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map
Some instructions do
not contain byte 2.
Instruction
code
Length varies
depending on the
instruction.
Byte 1
Byte 2
Operand
Operand
...
[Basic page map]
XY
+Z
[Extended page map]*
UV
+W
*: The extended page map is a generic name of maps for bit operation instructions, character
string operation instructions, 2-byte instructions, and ea instructions. Actually, there are
multiple extended page maps for each type of instructions.
An example of an instruction code is shown in Table B.9-1.
Table B.9-1 Example of an Instruction Code
Byte 1
(from basic page map)
Byte 2
(from extended page map)
NOP
00 +0=00
-
AND A, #8
30 +4=34
-
MOV A, ADB
60 +F=6F
00 +0=00
@RW2+d8, #8, rel
70 +0=70
F0 +2=F2
Instruction
513
514
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
A
ZEXT
SWAP
ADDSP
DTB
ADB
SPB
#8
A, #8
dir, A
A, dir
io, A
A, io
JMP
BRA
60
MULU
DIVU
ea
@A instruction 2
A
MOVW
MOVX
RET
SP, A A, addr16
A0
B0
C0
ea
instruction 8
D0
E0
rel
rel
LSRW
ASRW
LSLW
SWAPW
ZEXTW
XORW
ORW
ANDW
ORW
PUSHW
POPW
A, #16
AH
AH
MOVW
ea, RWi
Bit operation MOV
A instruction
ea, Ri
MOVW
RWi, ea
PUSHW
POPW
2-byte
XCHW
A
rlst
rlst instruction
RWi, ea
Character
XORW
PUSHW
POPW
XCH
operation
A
A, #16
PS
PS string
Ri, ea
instruction
A
ANDW
PUSHW
POPW
A
A, #16
A
CMPW
MOVL
MOVW
RETI
A, #16
A, #32 addr16, A
ADDSP
MULUW
NOTW
A
#16
A
A
A
EXTW
A
BHI
BLS
BGT
BLE
rel
rel
rel
rel
rel
BGE
CMPL
CMPW
A, #32
NEGW
A
rel
rel
rel
rel
rel
rel
BLT
BT
BNV
BV
BP
BN
BNC/BHS
rel
BC/BLO
BNZ/BNE
rel
BZ/BEQ
MOV
MOV
CBNE A, CWBNE A, MOVW
MOVW
INTP
MOV
RP, #8
ILM, #8
#8, rel
#16, rel
A, #16 A,addr16
addr24
Ri, ea
#4
F0
rel
ADDW
MOVW
MOVW
INT
ea
MOVW
MOVW
MOVW
MOV A,
MOVW
A, #16
A, dir
A, io
#vct8 instruction 9
A, RWi
RWi, A RWi, #16 @RWi+d8 @RWi+d8, A
NOT
ea
instruction 7
MOVX
MOVX
CALLP
ea
A, dir
A, io
addr24 instruction 6
MOVW
MOVW
RETP
A, #8
A, SP
io, #16
A, #8
90
BNT
SUBL
SUBW
A, #32
A
A
A
XOR
OR
OR
CCR, #8
80
ea
MOV
MOV
MOV
MOV
MOVX A, MOV
CALL
rel instruction 1
A, Ri
Ri, A
Ri, #8
A, Ri @RWi+d8
A, #4
70
MOV
JMP
ea
A, addr16
addr16 instruction 3
MOV
MOV
50
MOVX
MOV
JMPP
ea
A, #8
A, #8 addr16, A
addr24 instruction 4
MOV
MOV
MOV
40
SUBW
MOVW
MOVW
INT
MOVEA
A
A, #16
dir, A
io, A
addr16
RWi, ea
UNLINK
A
CMP
A
A, #8
A, #8
SUBC
SUB
ADD
30
AND
AND
MOV
MOV
CALL
ea
CCR, #8
A, #8
dir, #8
io, #8
addr16 instruction 5
CMP
A
A, dir
A, dir
ADDC
SUB
ADD
20
LINK
ADDL
ADDW
#imm8
A, #32
EXT
@A
PCB
A
JCTX
SUBDC
ADDDC
NEG
NCC
INT9
A
CMR
10
NOP
00
APPENDIX B Instructions
Table B.9-2 Basic Page Map
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
10
MOVB
io:bp, A
20
30
CLRB
io:bp
40
50
SETB
io:bp
60
70
BBC
io;bp, rel
80
90
BBS
io:bp, rel
A0
B0
MOVB
MOVB A, MOVB
MOVB
CLRB
CLRB
SETB
SETB
BBC
BBC
BBS
BBS
A, dir:bp addr16:bp
dir:bp, A addr16:bp,A
dir:bp addr16:bp
dir:bp addr16:bp dir:bp, rel addr16:bp,rel dir:bp, rel addr16:bp,rel
MOVB
A, io:bp
00
WBTS
io:bp
C0
D0
WBTC
io:bp
E0
SBBS
addr16:bp
F0
APPENDIX B Instructions
Table B.9-3 Bit Operation Instruction Map (First Byte = 6CH)
515
516
MOVSI
MOVSD
PCB, PCB
PCB, DTB
PCB, ADB
PCB, SPB
DTB, PCB
DTB, DTB
DTB, ADB
DTB, SPB
ADB, PCB
ADB, DTB
ADB, ADB
ADB, SPB
SPB, PCB
SPB, DTB
SPB, ADB
SPB, SPB
+1
+2
+3
+4
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
10
+0
00
MOVSWI
20
MOVSWD
30
40
50
60
70
90
A0
B0
C0
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SCEQI
SCEQD
SCWEQI SCWEQD FILSI
PCB
PCB
PCB
PCB
PCB
80
D0
FILSI
SPB
ADB
DTB
PCB
E0
F0
APPENDIX B Instructions
Table B.9-4 Character String Operation Instruction Map (First Byte = 6EH)
LSLW
LSLL
LSL
MOVW
MOVW
A, R0
A, R0
A, R0 @RL2+d8, A A, @RL2+d8
MOVW
MOVW
NRML
A, @A @AL, AH
A, R0
ASRW
ASRL
ASR
MOVW
MOVW
A, R0
A, R0
A, R0 @RL3+d8, A A, @RL3+d8
LSRW
LSRL
LSR
A, R0
A, R0
A, R0
+D
+E
+F
MOVW
MOVW
@RL1+d8, A A, @RL1+d8
MOVW
MOVW
@RL0+d8, A A, @RL0+d8
+C
+B
+A
+9
+8
A
MOV
MOV
MOVX
MOV
MOV
A, PCB
A, @A A, @RL3+d8 @RL3+d8, A A, @RL3+d8
+6
ROLC
MOV
MOV
A, @A @AL, AH
+5
A
MOV
MOV
MOVX
MOV
MOV
A, DPR
DPR, A A, @RL2+d8 @RL2+d8, A A, @RL2+d8
+4
ROLC
MOV
MOV
A, USB
USB, A
+3
+7
MOV
MOV
MOVX
MOV
MOV
A, SSB
SSB, A A, @RL1+d8 @RL1+d8, A A, @RL1+d8
+2
40
MOV
MOV
A, ADB
ADB, A
30
+1
20
MOV
MOV
MOVX
MOV
MOV
A, DTB
DTB, A A, @RL0+d8 @RL0+d8, A A, @RL0+d8
10
+0
00
50
DIVU
MULW
MUL
60
A
A
A
70
80
90
A0
B0
C0
D0
E0
F0
APPENDIX B Instructions
Table B.9-5 2-byte Instruction Map (First Byte = 6FH)
517
518
50
90
B0
D0
@RW1, @RW1+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
@RW2, @RW2+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
@RW3, @RW3+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
SUBL
SUBL A,
A, RL2 @RW5+d8
SUBL
SUBL A,
A, RL3 @RW6+d8
SUBL
SUBL A,
A, RL3 @RW7+d8
ADDL
ADDL A,
A, RL2 @RW5+d8
ADDL
ADDL A,
A, RL3 @RW6+d8
ADDL
ADDL A,
A, RL3 @RW7+d8
ADDL
ADDL A, SUBL
SUBL A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ADDL
ADDL A, SUBL
SUBL A, Use
@RW0+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW0+RW7
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
#16, rel A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
,#8, rel
ADDL
ADDL A, SUBL
SUBL A, Use
@RW1+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW1+RW7
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
#16, rel A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
,#8, rel
ADDL
ADDL A,
A,@RW2+ @PC+d16
ADDL
ADDL A, SUBL
SUBL A, Use
A,@RW3+
addr16 A,@RW3+
addr16 prohibited
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
SUBL
SUBL A,
A,@RW2+ @PC+d16
@RW0, @RW0+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
SUBL
SUBL A,
A, RL2 @RW4+d8
Use
prohibited
ANDL
ANDL A,
A,@RW2+ @PC+d16
ANDL
ANDL A,
A, RL3 @RW7+d8
ANDL
ANDL A,
A, RL3 @RW6+d8
ANDL
ANDL A,
A, RL2 @RW5+d8
ANDL
ANDL A,
A, RL2 @RW4+d8
ORL
ORL A,
A,@RW2+ @PC+d16
ORL
ORL A,
A, RL3 @RW7+d8
ORL
ORL A,
A, RL3 @RW6+d8
ORL
ORL A,
A, RL2 @RW5+d8
ORL
ORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A,@RW2+ @PC+d16
XORL
XORL A,
A, RL3 @RW7+d8
XORL
XORL A,
A, RL3 @RW6+d8
XORL
XORL A,
A, RL2 @RW5+d8
XORL
XORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A, RL1 @RW3+d8
addr16,
,#8, rel
Use
@PC+d16,
prohibited
,#8, rel
@RW3, @RW3+d16
#8, rel
,#8, rel
@RW2, @RW2+d16
#8, rel
,#8, rel
@RW1, @RW1+d16
#8, rel
,#8, rel
@RW0, @RW0+d16
#8, rel
,#8, rel
R7, @RW7+d8,
#8, rel
#8, rel
R6, @RW6+d8,
#8, rel
#8, rel
R5, @RW5+d8,
#8, rel
#8, rel
R4, @RW4+d8,
#8, rel
#8, rel
R3, @RW3+d8,
#8, rel
#8, rel
addr16, CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
#16, rel A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 prohibited
@PC+d16, CMPL
CMPL A,
#16, rel A,@RW2+ @PC+d16
RW7, @RW7+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW7+d8
RW6, @RW6+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW6+d8
RW5, @RW5+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW5+d8
RW4, @RW4+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW4+d8
ORL
ORL A,
A, RL1 @RW3+d8
R2, @RW2+d8,
#8, rel
#8, rel
R1, @RW1+d8,
#8, rel
#8, rel
ADDL
ADDL A,
A, RL2 @RW4+d8
ANDL
ANDL A,
A, RL1 @RW3+d8
XORL
XORL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW1+d8
+4
RW3, @RW3+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW3+d8
ORL
ORL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW1+d8
SUBL
SUBL A,
A, RL1 @RW3+d8
ANDL
ANDL A,
A, RL1 @RW2+d8
ANDL
ANDL A,
A, RL0 @RW1+d8
ADDL
ADDL A,
A, RL1 @RW3+d8
RW2, @RW2+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW2+d8
RW1, @RW1+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW1+d8
+3
CBNE ↓
F0
R0, @RW0+d8,
#8, rel
#8, rel
CBNE ↓
E0
SUBL
SUBL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW0+d8
C0
ADDL
ADDL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW0+d8
A0
+2
ANDL
ANDL A,
A, RL0 @RW0+d8
80
SUBL
SUBL A,
A, RL0 @RW1+d8
70
ADDL
ADDL A,
A, RL0 @RW1+d8
60
RW0, @RW0+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW0+d8
CWBNE ↓ CWBNE ↓
40
+1
30
+0
20
SUBL
SUBL A,
A, RL0 @RW0+d8
10
ADDL
ADDL A,
A, RL0 @RW0+d8
00
APPENDIX B Instructions
Table B.9-6 ea Instruction 1 (First Byte = 70H)
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW7+d8
@RL3 @@RW7+d8
RL3 @RW7+d8
RL3 @RW7+d8
A, RL3 @RW7+d8
RL3, A @RW7+d8,A
R7, #8 @RW7+d8,#8
A, RW7 @RW7+d8
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #8 @RW0+d16,#8
A,@RW0 @RW0+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1,A @RW1+d16,A @RW1, #8 @RW1+d16,#8
A,@RW1 @RW1+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2,A @RW2+d16,A @RW2, #8 @RW2+d16,#8
A,@RW2 @RW2+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3,A @RW3+d16,A @RW3, #8 @RW3+d16,#8
A,@RW3 @RW3+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+,A @RW0+RW7,A @RW0+, #8 @RW0+RW7,#8 A,@RW0+ @RW0+RW7
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+,A @RW1+RW7,A @RW1+, #8 @RW1+RW7,#8 A,@RW1+ @RW1+RW7
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+,A @PC+d16, A @RW2+, #8 @PC+d16, #8 A,@RW2+ @PC+d16
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+,A
addr16, A @RW3+, #8
addr16, #8 A,@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW6+d8
@RL3 @@RW6+d8
RL3 @RW6+d8
RL3 @RW6+d8
A, RL3 @RW6+d8
RL3, A @RW6+d8,A
R6, #8 @RW6+d8,#8
A, RW6 @RW6+d8
D0
+6
C0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW5+d8
@RL2 @@RW5+d8
RL2 @RW5+d8
RL2 @RW5+d8
A, RL2 @RW5+d8
RL2, A @RW5+d8,A
R5, #8 @RW5+d8,#8
A, RW5 @RW5+d8
B0
+5
A0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW4+d8
@RL2 @@RW4+d8
RL2 @RW4+d8
RL2 @RW4+d8
A, RL2 @RW4+d8
RL2, A @RW4+d8,A
R4, #8 @RW4+d8,#8
A, RW4 @RW4+d8
90
+4
80
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW3+d8
@RL1 @@RW3+d8
RL1 @RW3+d8
RL1 @RW3+d8
A, RL1 @RW3+d8
RL1, A @RW3+d8,A
R3, #8 @RW3+d8,#8
A, RW3 @RW3+d8
70
+3
60
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW2+d8
@RL1 @@RW2+d8
RL1 @RW2+d8
RL1 @RW2+d8
A, RL1 @RW2+d8
RL1, A @RW2+d8,A
R2, #8 @RW2+d8,#8
A, RW2 @RW2+d8
50
+2
40
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW1+d8
@RL0 @@RW1+d8
RL0 @RW1+d8
RL0 @RW1+d8
A, RL0 @RW1+d8
RL0, A @RW1+d8,A
R1, #8 @RW1+d8,#8
A, RW1 @RW1+d8
30
+1
20
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW0+d8
@RL0 @@RW0+d8
RL0 @RW0+d8
RL0 @RW0+d8
A, RL0 @RW0+d8
RL0, A @RW0+d8,A
R0, #8 @RW0+d8,#8
A, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-7 ea Instruction 2 (First Byte = 71H)
519
520
D0
E0
F0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A A,@RW3+
addr16 A,@RW3+
addr16
+D
+E
+F
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R7 @RW7+d8
A, R7 @RW7+d8
R7, A @RW7+d8,A
A, R7 @RW7+d8
A, R7 @RW7+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R6 @RW6+d8
A, R6 @RW6+d8
R6, A @RW6+d8,A
A, R6 @RW6+d8
A, R6 @RW6+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R5 @RW5+d8
A, R5 @RW5+d8
R5, A @RW5+d8,A
A, R5 @RW5+d8
A, R5 @RW5+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R4 @RW4+d8
A, R4 @RW4+d8
R4, A @RW4+d8,A
A, R4 @RW4+d8
A, R4 @RW4+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R3 @RW3+d8
A, R3 @RW3+d8
R3, A @RW3+d8,A
A, R3 @RW3+d8
A, R3 @RW3+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R2 @RW2+d8
A, R2 @RW2+d8
R2, A @RW2+d8,A
A, R2 @RW2+d8
A, R2 @RW2+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R1 @RW1+d8
A, R1 @RW1+d8
R1, A @RW1+d8,A
A, R1 @RW1+d8
A, R1 @RW1+d8
+C
INC
DEC
R7 @RW7+d8
C0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ROLC
RORC
RORC
INC
R7 @RW7+d8
R7 @RW7+d8
ROLC
INC
DEC
R6 @RW6+d8
B0
+B
ROLC
RORC
RORC
INC
R6 @RW6+d8
R6 @RW6+d8
ROLC
INC
DEC
R5 @RW5+d8
A0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ROLC
RORC
RORC
INC
R5 @RW5+d8
R5 @RW5+d8
ROLC
INC
DEC
R4 @RW4+d8
90
+A
ROLC
RORC
RORC
INC
R4 @RW4+d8
R4 @RW4+d8
ROLC
INC
DEC
R3 @RW3+d8
INC
DEC
R2 @RW2+d8
INC
DEC
R1 @RW1+d8
80
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R0 @RW0+d8
A, R0 @RW0+d8
R0, A @RW0+d8,A
A, R0 @RW0+d8
A, R0 @RW0+d8
70
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ROLC
RORC
RORC
INC
R3 @RW3+d8
R3 @RW3+d8
ROLC
60
INC
DEC
R0 @RW0+d8
50
+9
ROLC
RORC
RORC
INC
R2 @RW2+d8
R2 @RW2+d8
ROLC
40
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0, A @RW0+d16,A
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ROLC
RORC
RORC
INC
R1 @RW1+d8
R1 @RW1+d8
ROLC
30
ROLC
RORC
RORC
INC
R0 @RW0+d8
R0 @RW0+d8
20
ROLC
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX B Instructions
Table B.9-8 ea Instruction 3 (First Byte = 72H)
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16 @RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, #16 @RW3+d16,#16 A,@RW3 @RW3+d16
+B
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A @RW3+, #16
addr16, #16 A,@RW3+
addr16
INCW @
+F
INCW
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16 @RW2+ @@PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A @RW2+, #16 @PC+d16, #16 A,@RW2+ @PC+d16
CALL @
+E
CALL
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, #16 @RW1+RW7,#16 A,@RW1+ @RW1+RW7
XCHW
XCHW A,
A, RW7 @RW7+d8
XCHW
XCHW A,
A, RW6 @RW6+d8
XCHW
XCHW A,
A, RW5 @RW5+d8
+D @@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7
INCW @
MOVW
MOVW
RW7, #16 @RW7+d8,#16
MOVW
MOVW
RW6, #16 @RW6+d8,#16
MOVW
MOVW
RW5, #16 @RW5+d8,#16
XCHW
XCHW A,
A, RW4 @RW4+d8
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, #16 @RW0+RW7,#16 A,@RW0+ @RW0+RW7
INCW
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW7 @RW7+d8
RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, A @RW7+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW6 @RW6+d8
RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, A @RW6+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW5 @RW5+d8
RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, A @RW5+d8,A
MOVW
MOVW
RW4, #16 @RW4+d8,#16
+C @@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7
JMP @
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16 @RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, #16 @RW2+d16,#16 A,@RW2 @RW2+d16
+A
JMP
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16 @RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, #16 @RW1+d16,#16 A,@RW1 @RW1+d16
+9
CALL @
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16 @RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #16 @RW0+d16,#16 A,@RW0 @RW0+d16
+8
CALL
CALL
CALL
RW7 @@RW7+d8
JMP
JMP
@RW7 @@RW7+d8
+7
JMP @
CALL
CALL
RW6 @@RW6+d8
JMP
JMP
@RW6 @@RW6+d8
+6
JMP
CALL
CALL
RW5 @@RW5+d8
JMP
JMP
@RW5 @@RW5+d8
+5
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW4 @RW4+d8
RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, A @RW4+d8,A
XCHW
XCHW A,
A, RW3 @RW3+d8
XCHW
XCHW A,
A, RW2 @RW2+d8
XCHW
XCHW A,
A, RW1 @RW1+d8
CALL
CALL
RW4 @@RW4+d8
MOVW
MOVW
RW3, #16 @RW3+d8,#16
MOVW
MOVW
RW2, #16 @RW2+d8,#16
MOVW
MOVW
RW1, #16 @RW1+d8,#16
JMP
JMP
@RW4 @@RW4+d8
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW3 @RW3+d8
RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, A @RW3+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW2 @RW2+d8
RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, A @RW2+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW1 @RW1+d8
RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, A @RW1+d8,A
+4
F0
XCHW
XCHW A,
A, RW0 @RW0+d8
E0
CALL
CALL
RW3 @@RW3+d8
D0
MOVW
MOVW
RW0, #16 @RW0+d8,#16
C0
JMP
JMP
@RW3 @@RW3+d8
B0
+3
A0
CALL
CALL
RW2 @@RW2+d8
90
JMP
JMP
@RW2 @@RW2+d8
80
+2
70
CALL
CALL
RW1 @@RW1+d8
60
JMP
JMP
@RW1 @@RW1+d8
50
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW0 @RW0+d8
RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, A @RW0+d8,A
40
+1
30
CALL
CALL
RW0 @@RW0+d8
20
JMP
JMP
@RW0 @@RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-9 ea Instruction 4 (First Byte = 73H)
521
522
ADD
A, SUB
SUB
SUB
ADDC
A, ADDC
A,
ADDC
ADDC A,
A, CMP
CMP
CMP
CMP
A,
A,
A, AND
AND
AND
AND
AND
AND
A,
A,
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r PC+d16, r
+F A,@RW3+
ADD
ADD
SUB
SUB
ADDC
ADDC
CMP
CMP
AND
AND
OR
OR
XOR
XOR
DBNZ
DBNZ
A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+
A, addr16 A,@RW3+ A, addr16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ADD
SUB
CMP
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW1+ @RW1+RW7 @RW1+, r W1+RW7, r
A,
CMP
OR
OR
A,
A,@RW1+ @RW1+RW7
ADD
ADD
ADDC A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ADDC
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW0+ @RW0+RW7 @RW0+, r W0+RW7, r
A,
OR
OR
A,
A,@RW0+ @RW0+RW7
SUB
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
SUB
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW3 @RW3+d16 @RW3, r W3+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
A,
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW2 @RW2+d16 @RW2, r W2+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW1 @RW1+d16 @RW1, r W1+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW0 @RW0+d16 @RW0, r W0+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
R7, r RW7+d8, r
ADD
F0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
R6, r RW6+d8, r
E0
ADD
D0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
R5, r RW5+d8, r
C0
ADD
B0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
R4, r RW4+d8, r
A0
ADD
90
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
R3, r RW3+d8, r
80
ADD
70
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
R2, r RW2+d8, r
60
ADD
50
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
R1, r RW1+d8, r
40
ADD
30
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
R0, r RW0+d8, r
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX B Instructions
Table B.9-10 ea Instruction 5 (First Byte = 74H)
NOT
NOT
R2 @RW2+d8
SUB
SUB
SUB
SUB
ADD
SUB
SUB
@RW1+RW7,A @RW1+, A @RW1+RW7,A
ADD @R
@RW0+RW7,A @RW0+, A @RW0+RW7,A
ADD @R
+F
ADD
ADD
@RW3+, A addr16, A
SUB
SUB
@RW3+, A addr16, A
+E @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
ADD
+D @RW1+, A
ADD
+C @RW0+, A
ADD
NOT
NOT
@RW1+ @RW1+RW7
NOT
NOT
@RW0+ @RW0+RW7
SUBC
SUBC A, NEG
NEG A,
AND
AND
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
OR
OR
@RW3+, A addr16, A
XOR
XOR
@RW3+, A addr16, A
NOT
NOT
@RW3+
addr16
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
NOT
NOT
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+ @PC+d16
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A
NOT
NOT
@RW3 @RW3+d16
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
+B
XOR
NOT
NOT
R7, A @RW7+d8, A
R7 @RW7+d8
XOR
NOT
NOT
R6, A @RW6+d8, A
R6 @RW6+d8
XOR
NOT
NOT
R5, A @RW5+d8, A
R5 @RW5+d8
XOR
NOT
NOT
R4, A @RW4+d8, A
R4 @RW4+d8
XOR
NOT
NOT
R3, A @RW3+d8, A
R3 @RW3+d8
XOR
R2, A @RW2+d8,A
XOR
NOT
NOT
R1, A @RW1+d8, A
R1 @RW1+d8
NOT
NOT
@RW2 @RW2+d16
XOR
F0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
NEG A,
AND
AND
OR
OR
R7 @RW7+d8
R7, A @RW7+d8, A
R7, A @RW7+d8, A
XOR
XOR
XOR
XOR
XOR
XOR
E0
XOR
NOT
NOT
R0, A @RW0+d8, A
R0 @RW0+d8
D0
+A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R7, A @RW7+d8, A
R7, A @RW7+d8, A
A, R7 @RW7+d8
ADD
NEG A,
AND
AND
OR
OR
R6 @RW6+d8
R6, A @RW6+d8, A
R6, A @RW6+d8, A
NEG A,
AND
AND
OR
OR
R5 @RW5+d8
R5, A @RW5+d8, A
R5, A @RW5+d8, A
NEG A,
AND
AND
OR
OR
R4 @RW4+d8
R4, A @RW4+d8, A
R4, A @RW4+d8, A
NEG A,
AND
AND
OR
OR
R3 @RW3+d8
R3, A @RW3+d8, A
R3, A @RW3+d8, A
NEG A,
AND
AND
OR
OR
R2 @RW2+d8
R2, A @RW2+d8,A
R2, A @RW2+d8,A
NEG A,
AND
AND
OR
OR
R1 @RW1+d8
R1, A @RW1+d8, A
R1, A @RW1+d8, A
XOR
C0
NOT
NOT
@RW1 @RW1+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R6, A @RW6+d8, A
R6, A @RW6+d8, A
A, R6 @RW6+d8
ADD
B0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R5, A @RW5+d8, A
R5, A @RW5+d8, A
A, R5 @RW5+d8
ADD
A0
+9
ADD
SUB
SUB
SUBC
SUBC A, NEG
R4, A @RW4+d8, A
R4, A @RW4+d8, A
A, R4 @RW4+d8
ADD
90
NOT
NOT
@RW0 @RW0+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R3, A @RW3+d8, A
R3, A @RW3+d8, A
A, R3 @RW3+d8
ADD
80
NEG A,
AND
AND
OR
OR
R0 @RW0+d8
R0, A @RW0+d8, A
R0, A @RW0+d8, A
70
ADD
ADD
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R2, A @RW2+d8,A
R2, A @RW2+d8,A
A, R2 @RW2+d8
60
ADD
50
ADD
SUB
SUB
SUBC
SUBC A, NEG
R1, A @RW1+d8, A
R1, A @RW1+d8, A
A, R1 @RW1+d8
40
ADD
30
ADD
SUB
SUB
SUBC
SUBC A, NEG
R0, A @RW0+d8, A
R0, A @RW0+d8, A
A, R0 @RW0+d8
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX B Instructions
Table B.9-11 ea Instruction 6 (First Byte = 75H)
523
524
ADDW A, SUBW
ADDW
ADDCW
CMPW
ADDCW A, CMPW
ADDCW A,
ANDW
CMPW A, ANDW
CMPW A,
ORW
ORW
ANDW A, ORW
ANDW A,
ANDW A,
ORW
ORW
ORW
A,
A,
A, XORW
XORW A, DWBNZ
DWBNZ
+F A,@RW3+
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
addr 16 A,@RW3+ addr 16
A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr16 A,@RW3+
addr 16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r @PC+d16,r
SUBW A, ADDCW
SUBW A,
ANDW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW1+ @RW1+RW7 @RW1+, r @RW1+RW7,r
SUBW
ADDW A,
ADDW
CMPW A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
CMPW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW0+ @RW0+RW7 @RW0+, r @RW0+RW7,r
ADDCW A,
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ADDCW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW3 @RW3+d16 @RW3, r @RW3+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
SUBW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW2 @RW2+d16 @RW2, r @RW2+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
SUBW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW1 @RW1+d16 @RW1, r @RW1+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADDW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW0 @RW0+d16 @RW0, r @RW0+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
ADDW
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, r @RW7+d8,r
F0
+7
E0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, r @RW6+d8,r
D0
+6
C0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, r @RW5+d8,r
B0
+5
A0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, r @RW4+d8,r
90
+4
80
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, r @RW3+d8,r
70
+3
60
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, r @RW2+d8,r
50
+2
40
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, r @RW1+d8,r
30
+1
20
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, r @RW0+d8,r
10
+0
00
APPENDIX B Instructions
Table B.9-12 ea Instruction 7 (First Byte = 76H)
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
@RW3 @RW3+d16
SUBW
SUBW
@RW3+, A addr16, A
ADDW
ADDW
@RW3+, A addr16, A
+F
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
ORW
ORW
@RW3+, A addr16, A
XORW
XORW
@RW3+, A addr16, A
NOTW
NOTW
@RW3+
addr16
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
@RW2+ @PC+d16
SUBW
SUBW
@RW2+, A @PC+d16,A
ADDW
ADDW
@RW2+, A @PC+d16,A
+E
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+ @RW1+RW7
SUBCW
+D
SUBW
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+ @RW0+RW7
SUBW
SUBCW
+C
ADDW
ADDW
SUBW
SUBCW A,
+B @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
SUBW
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
@RW2 @RW2+d16
ADDW
ADDW
SUBW
+A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
SUBW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
@RW1 @RW1+d16
ADDW
ADDW
SUBCW A,
+9 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
@RW0 @RW0+d16
SUBW
NOTW
NOTW
RW7 @RW7+d8
NOTW
NOTW
RW6 @RW6+d8
NOTW
NOTW
RW5 @RW5+d8
+8 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
SUBW
XORW
XORW
RW7, A @RW7+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
A, RW7 @RW7+d8
RW7 @RW7+d8
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
+7
ADDW
XORW
XORW
RW6, A @RW6+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
A, RW6 @RW6+d8
RW6 @RW6+d8
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
+6
ADDW
XORW
XORW
RW5, A @RW5+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
A, RW5 @RW5+d8
RW5 @RW5+d8
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
+5
NOTW
NOTW
RW4 @RW4+d8
XORW
XORW
RW4, A @RW4+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
A, RW4 @RW4+d8
RW4 @RW4+d8
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
+4
F0
NOTW
NOTW
RW0 @RW0+d8
E0
NOTW
NOTW
RW3 @RW3+d8
D0
XORW
XORW
RW3, A @RW3+d8, A
C0
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
A, RW3 @RW3+d8
RW3 @RW3+d8
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
B0
+3
A0
NOTW
NOTW
RW2 @RW2+d8
90
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
A, RW2 @RW2+d8
RW2 @RW2+d8
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
80
+2
70
NOTW
NOTW
RW1 @RW1+d8
60
XORW
XORW
RW1, A @RW1+d8, A
50
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
A, RW1 @RW1+d8
RW1 @RW1+d8
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
40
+1
30
XORW
XORW
RW0, A @RW0+d8, A
20
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
A, RW0 @RW0+d8
RW0 @RW0+d8
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
10
+0
00
APPENDIX B Instructions
Table B.9-13 ea Instruction 8 (First Byte = 77H)
525
526
DIV
DIV
A, DIVW
DIVW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
DIV
DIV
A, DIVW
DIVW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW MULUW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MULU
MULU A, MULUW MULUW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MULU
MULU A, MULUW MULUW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
+9
+A
+B
+C
+D
+E
+F A, @RW3+
MULU
DIV
DIV
A, DIVW
DIVW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
addr16 A,@RW3+ addr16
A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
A, DIVW
DIVW A,
addr16 A,@RW3+
addr16
DIV
DIV
A, DIVW
DIVW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
F0
+7
E0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
D0
+6
C0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
B0
+5
A0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
90
+4
80
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
70
+3
60
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
50
+2
40
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
30
+1
20
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-14 ea Instruction 9 (First Byte = 78H)
MOVEA
MOVEA RW1
RW1,RW4 ,@RW4+d8
MOVEA
MOVEA RW1
RW1,RW5 ,@RW5+d8
MOVEA
MOVEA RW1
RW1,RW6 ,@RW6+d8
MOVEA
MOVEA RW1
RW1,RW7 ,@RW7+d8
MOVEA
MOVEA RW1
RW1,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,@RW1 ,@RW1+d16
MOVEA
MOVEA RW1
RW1,@RW2 ,@RW2+d16
MOVEA
MOVEA RW1
RW1,@RW3 ,@RW3+d16
MOVEA
MOVEA RW0
RW0,RW4 ,@RW4+d8
MOVEA
MOVEA RW0
RW0,RW5 ,@RW5+d8
MOVEA
MOVEA RW0
RW0,RW6 ,@RW6+d8
MOVEA
MOVEA RW0
RW0,RW7 ,@RW7+d8
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
+4
+5
+6
+7
50
70
90
B0
C0
D0
F0
MOVEA
MOVEA RW3
RW3,@RW2+ ,@PC+d16
MOVEA
MOVEA RW4
RW4,@RW2+ ,@PC+d16
MOVEA
MOVEA RW7
RW7,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
RW6,@RW3+ RW6, addr16 [email protected]+ RW7, addr16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2+ ,@PC+d16
RW6,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
RW0,@RW3+ RW0, addr16 RW1,@RW3+ RW1, addr16 RW2,@RW3+ RW2, addr16 RW3,@RW3+ RW3, addr16 RW4,@RW3+ RW4, addr16 RW5,@RW3+ RW5, addr16
MOVEA
MOVEA RW2
RW2,@RW2+ ,@PC+d16
+F
MOVEA
MOVEA RW1
RW1,@RW2+ ,@PC+d16
MOVEA
MOVEA RW0
RW0,@RW2+ ,@PC+d16
MOVEA RW1
+E
MOVEA
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW5,@RW1+ ,@RW1+RW7 RW6,@RW1+ ,@RW1+RW7 RW7,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW7
RW7,@RW3 ,@RW3+d16
MOVEA
MOVEA RW7
RW7,@RW2 ,@RW2+d16
MOVEA
MOVEA RW7
RW7,@RW1 ,@RW1+d16
MOVEA
MOVEA RW7
RW7,@RW0 ,@RW0+d16
MOVEA
MOVEA RW7
RW7,RW7 ,@RW7+d8
MOVEA
MOVEA RW7
RW7,RW6 ,@RW6+d8
MOVEA
MOVEA RW7
RW7,RW5 ,@RW5+d8
MOVEA
MOVEA RW7
RW7,RW4 ,@RW4+d8
MOVEA
MOVEA RW7
RW7,RW3 ,@RW3+d8
MOVEA
MOVEA RW7
RW7,RW2 ,@RW2+d8
MOVEA
MOVEA RW7
RW7,RW1 ,@RW1+d8
MOVEA
MOVEA RW7
RW7,RW0 ,@RW0+d8
E0
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4
RW2,@RW1+ ,@RW1+RW7 RW3,@RW1+ ,@RW1+RW7 RW4,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW3 ,@RW3+d16 RW6,@RW3 ,@RW3+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2 ,@RW2+d16 RW6,@RW2 ,@RW2+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW1 ,@RW1+d16 RW6,@RW1 ,@RW1+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW0 ,@RW0+d16 RW6,@RW0 ,@RW0+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW7 ,@RW7+d8
RW6,RW7 ,@RW7+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW6 ,@RW6+d8
RW6,RW6 ,@RW6+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW5 ,@RW5+d8
RW6,RW5 ,@RW5+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW4 ,@RW4+d8
RW6,RW4 ,@RW4+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW3 ,@RW3+d8
RW6,RW3 ,@RW3+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW2 ,@RW2+d8
RW6,RW2 ,@RW2+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW1 ,@RW1+d8
RW6,RW1 ,@RW1+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW0 ,@RW0+d8
RW6,RW0 ,@RW0+d8
A0
+D RW0,@RW1+ ,@RW1+RW7 RW1,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW4
RW4,@RW3 ,@RW3+d16
MOVEA
MOVEA RW4
RW4,@RW2 ,@RW2+d16
MOVEA
MOVEA RW4
RW4,@RW1 ,@RW1+d16
MOVEA
MOVEA RW4
RW4,@RW0 ,@RW0+d16
MOVEA
MOVEA RW4
RW4,RW7 ,@RW7+d8
MOVEA
MOVEA RW4
RW4,RW6 ,@RW6+d8
MOVEA
MOVEA RW4
RW4,RW5 ,@RW5+d8
MOVEA
MOVEA RW4
RW4,RW4 ,@RW4+d8
MOVEA
MOVEA RW4
RW4,RW3 ,@RW3+d8
MOVEA
MOVEA RW4
RW4,RW2 ,@RW2+d8
MOVEA
MOVEA RW4
RW4,RW1 ,@RW1+d8
MOVEA
MOVEA RW4
RW4,RW0 ,@RW0+d8
80
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW5,@RW0+ ,@RW0+RW7 RW6,@RW0+ ,@RW0+RW7 RW7,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW3
RW3,@RW3 ,@RW3+d16
MOVEA
MOVEA RW3
RW3,@RW2 ,@RW2+d16
MOVEA
MOVEA RW3
RW3,@RW1 ,@RW1+d16
MOVEA
MOVEA RW3
RW3,@RW0 ,@RW0+d16
MOVEA
MOVEA RW3
RW3,RW7 ,@RW7+d8
MOVEA
MOVEA RW3
RW3,RW6 ,@RW6+d8
MOVEA
MOVEA RW3
RW3,RW5 ,@RW5+d8
MOVEA
MOVEA RW3
RW3,RW4 ,@RW4+d8
MOVEA
MOVEA RW3
RW3,RW3 ,@RW3+d8
MOVEA
MOVEA RW3
RW3,RW2 ,@RW2+d8
MOVEA
MOVEA RW3
RW3,RW1 ,@RW1+d8
MOVEA
MOVEA RW3
RW3,RW0 ,@RW0+d8
60
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4
RW2,@RW0+ ,@RW0+RW7 RW3,@RW0+ ,@RW0+RW7 RW4,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW2
RW2,@RW3 ,@RW3+d16
MOVEA
MOVEA RW2
RW2,@RW2 ,@RW2+d16
MOVEA
MOVEA RW2
RW2,@RW1 ,@RW1+d16
MOVEA
MOVEA RW2
RW2,@RW0 ,@RW0+d16
MOVEA
MOVEA RW2
RW2,RW7 ,@RW7+d8
MOVEA
MOVEA RW2
RW2,RW6 ,@RW6+d8
MOVEA
MOVEA RW2
RW2,RW5 ,@RW5+d8
MOVEA
MOVEA RW2
RW2,RW4 ,@RW4+d8
MOVEA
MOVEA RW2
RW2,RW3 ,@RW3+d8
MOVEA
MOVEA RW2
RW2,RW2 ,@RW2+d8
MOVEA
MOVEA RW2
RW2,RW1 ,@RW1+d8
MOVEA
MOVEA RW2
RW2,RW0 ,@RW0+d8
40
+C RW0,@RW0+ ,@RW0+RW7 RW1,@RW0+ ,@RW0+RW7
+B RW0,@RW3 ,@RW3+d16
+A RW0,@RW2 ,@RW2+d16
+9 RW0,@RW1 ,@RW1+d16
MOVEA RW1
MOVEA
MOVEA RW1
RW1,RW3 ,@RW3+d8
MOVEA
MOVEA RW0
RW0,RW3 ,@RW3+d8
+3
MOVEA
MOVEA
MOVEA RW1
RW1,RW2 ,@RW2+d8
MOVEA
MOVEA RW0
RW0,RW2 ,@RW2+d8
+2
+8 RW0,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,RW1 ,@RW1+d8
MOVEA
MOVEA RW0
RW0,RW1 ,@RW1+d8
+1
30
MOVEA
MOVEA RW1
RW1,RW0 ,@RW0+d8
20
MOVEA
MOVEA RW0
RW0,RW0 ,@RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-15 MOVEA RWi, ea Instruction (First Byte = 79H)
527
528
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW2 @RW2+d16 R1,@RW2 @RW2+d16 R2,@RW2 @RW2+d16 R3,@RW2 @RW2+d16 R4,@RW2 @RW2+d16 R5,@RW2 @RW2+d16 R6,@RW2 @RW2+d16 R7,@RW2 @RW2+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW3+
addr16 @RW3+
addr16
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16
@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-16 MOV Ri, ea Instruction (First Byte = 7AH)
MOVW
MOVW RW5,
RW5,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW1 @RW1+d16 RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16 RW3,@RW1 @RW1+d16 RW4,@RW1 @RW1+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW2 @RW2+d16 RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16 RW3,@RW2 @RW2+d16 RW4,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW3 @RW3+d16 RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16 RW3,@RW3 @RW3+d16 RW4,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4, MOVW
MOVW RW5, MOVW
MOVW RW6, MOVW
MOVW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, @RW2+ @PC+d16
RW2, @RW2+ @PC+d16
RW3, @RW2+ @PC+d16
RW4, @RW2+ @PC+d16
MOVW
MOVW
RW1, @RW3+ RW1, addr16
MOVW
RW0, @RW1+
MOVW
MOVW
RW0, @RW2+ @PC+d16
MOVW
MOVW
RW0, @RW3+ RW0, addr16
+9
+A
+B
+C
+D
+E
+F
MOVW
MOVW
RW2, @RW3+ RW2, addr16
MOVW
MOVW
RW3, @RW3+ RW3, addr16
MOVW
MOVW
RW5, @RW3+ RW5, addr16
MOVW
MOVW
RW5, @RW2+ @PC+d16
MOVW
MOVW
RW6, @RW3+ RW6, addr16
MOVW
MOVW RW6,
RW6, @RW2+ @PC+d16
MOVW
MOVW
RW7, @RW3+ RW7, addr16
MOVW
MOVW RW7,
RW7, @RW2+ @PC+d16
MOVW RW7,
@RW1+RW7
MOVW
MOVW RW7,
RW7,@RW3 @RW3+d16
MOVW
MOVW RW7,
RW7,@RW2 @RW2+d16
MOVW
MOVW RW7,
RW7,@RW1 @RW1+d16
MOVW
MOVW RW7,
RW7,@RW0 @RW0+d16
MOVW
MOVW RW7,
RW7, RW7 @RW7+d8
MOVW
MOVW RW7,
RW7, RW6 @RW6+d8
MOVW
MOVW RW7,
RW7, RW5 @RW5+d8
MOVW
MOVW RW7,
RW7, RW4 @RW4+d8
MOVW RW6, MOVW
@RW1+RW7 RW7, @RW1+
MOVW
MOVW RW6,
RW6,@RW3 @RW3+d16
MOVW
MOVW RW6,
RW6,@RW2 @RW2+d16
MOVW
MOVW RW6,
RW6,@RW1 @RW1+d16
MOVW
MOVW RW6,
RW6,@RW0 @RW0+d16
MOVW
MOVW RW6,
RW6, RW7 @RW7+d8
MOVW
MOVW RW6,
RW6, RW6 @RW6+d8
MOVW
MOVW RW6,
RW6, RW5 @RW5+d8
MOVW
MOVW RW6,
RW6, RW4 @RW4+d8
MOVW
MOVW
@RW1+RW7 RW6, @RW1+
MOVW
MOVW RW5,
RW5, RW6 @RW6+d8
MOVW
MOVW RW5,
RW5, RW5 @RW5+d8
MOVW RW4, MOVW
@RW1+RW7 RW5, @RW1+
MOVW
MOVW
RW4, @RW3+ RW4, addr16
MOVW RW3, MOVW
@RW1+RW7 RW4, @RW1+
MOVW
MOVW RW5,
RW5,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW0 @RW0+d16 RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16 RW3,@RW0 @RW0+d16 RW4,@RW0 @RW0+d16
+8
MOVW RW2, MOVW
@RW1+RW7 RW3, @RW1+
MOVW
MOVW RW5,
RW5,@RW1 @RW1+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
MOVW
MOVW
RW0, RW7 @RW7+d8
+7
MOVW RW1, MOVW
@RW1+RW7 RW2, @RW1+
MOVW
MOVW RW5,
RW5,@RW0 @RW0+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
MOVW
MOVW
RW0, RW6 @RW6+d8
+6
MOVW
MOVW
@RW1+RW7 RW1, @RW1+
MOVW
MOVW RW5,
RW5, RW7 @RW7+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
MOVW
MOVW
RW0, RW5 @RW5+d8
+5
MOVW
MOVW RW5,
RW5, RW4 @RW4+d8
MOVW
MOVW RW7,
RW7, RW3 @RW3+d8
MOVW
MOVW RW7,
RW7, RW2 @RW2+d8
MOVW
MOVW RW7,
RW7, RW1 @RW1+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
MOVW
MOVW RW6,
RW6, RW3 @RW3+d8
MOVW
MOVW RW6,
RW6, RW2 @RW2+d8
MOVW
MOVW RW6,
RW6, RW1 @RW1+d8
MOVW
MOVW
RW0, RW4 @RW4+d8
MOVW
MOVW RW5,
RW5, RW3 @RW3+d8
MOVW
MOVW RW5,
RW5, RW2 @RW2+d8
MOVW
MOVW RW5,
RW5, RW1 @RW1+d8
+4
F0
MOVW
MOVW RW7,
RW7, RW0 @RW0+d8
E0
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
D0
MOVW
MOVW RW6,
RW6, RW0 @RW0+d8
C0
MOVW
MOVW
RW0, RW3 @RW3+d8
B0
MOVW
MOVW RW5,
RW5, RW0 @RW0+d8
A0
+3
90
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
80
MOVW
MOVW
RW0, RW2 @RW2+d8
70
+2
60
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
50
MOVW
MOVW
RW0, RW1 @RW1+d8
40
+1
30
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
20
MOVW
MOVW
RW0, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-17 MOVW RWi, ea Instruction (First Byte = 7BH)
529
530
+F
+E
+D
+C
+B
+A
+9
+8
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R1 addr16, R1
MOV
MOV
@RW3+, R0 addr16, R0
MOV
MOV
MOV
@RW2+, R1 @PC+d16, R1
@RW2+, R0 @PC+d16, R0
MOV
MOV
MOV
MOV
MOV
@RW0+, R1 @RW0+RW7, R1
MOV
@RW3, R1 @RW3+d16, R1
MOV
@RW2, R1 @RW2+d16, R1
MOV
@RW1, R1 @RW1+d16, R1
MOV
@RW1+, R1 @RW1+RW7, R1
MOV
MOV
@RW0, R1 @RW0+d16, R1
MOV
@RW1+, R0 @RW1+RW7, R0
MOV
@RW0+, R0 @RW0+RW7, R0
MOV
@RW3, R0 @RW3+d16, R0
MOV
@RW2, R0 @RW2+d16, R0
MOV
@RW1, R0 @RW1+d16, R0
MOV
@RW0, R0 @RW0+d16, R0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R2 addr16, R2
MOV
@RW2+, R2 @PC+d16, R2
MOV
@RW1+, R2 @RW1+RW7, R2
MOV
@RW0+, R2 @RW0+RW7, R2
MOV
@RW3, R2 @RW3+d16, R2
MOV
@RW2, R2 @RW2+d16, R2
MOV
@RW1, R2 @RW1+d16, R2
MOV
@RW0, R2 @RW0+d16, R2
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R3 addr16, R3
MOV
@RW2+, R3 @PC+d16, R3
MOV
@RW1+, R3 @RW1+RW7, R3
MOV
@RW0+, R3 @RW0+RW7, R3
MOV
@RW3, R3 @RW3+d16, R3
MOV
@RW2, R3 @RW2+d16, R3
MOV
@RW1, R3 @RW1+d16, R3
MOV
@RW0, R3 @RW0+d16, R3
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R4 addr16, R4
MOV
@RW2+, R4 @PC+d16, R4
MOV
@RW1+, R4 @RW1+RW7, R4
MOV
@RW0+, R4 @RW0+RW7, R4
MOV
@RW3, R4 @RW3+d16, R4
MOV
@RW2, R4 @RW2+d16, R4
MOV
@RW1, R4 @RW1+d16, R4
MOV
@RW0, R4 @RW0+d16, R4
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R5 addr16, R5
MOV
@RW2+, R5 @PC+d16, R5
MOV
@RW1+, R5 @RW1+RW7, R5
MOV
@RW0+, R5 @RW0+RW7, R5
MOV
@RW3, R5 @RW3+d16, R5
MOV
@RW2, R5 @RW2+d16, R5
MOV
@RW1, R5 @RW1+d16, R5
MOV
@RW0, R5 @RW0+d16, R5
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R6 addr16, R6
MOV
@RW2+, R6 @PC+d16, R6
MOV
@RW1+, R6 @RW1+RW7, R6
MOV
@RW0+, R6 @RW0+RW7, R6
MOV
@RW3, R6 @RW3+d16, R6
MOV
@RW2, R6 @RW2+d16, R6
MOV
@RW1, R6 @RW1+d16, R6
MOV
@RW0, R6 @RW0+d16,
R6
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R7 addr16, R7
MOV
@RW2+, R7 @PC+d16, R7
MOV
@RW1+, R7 @RW1+RW7, R7
MOV
@RW0+, R7 @RW0+RW7, R7
MOV
@RW3, R7 @RW3+d16, R7
MOV
@RW2, R7 @RW2+d16, R7
MOV
@RW1, R7 @RW1+d16, R7
MOV
@RW0, R7 @RW0+d16, R7
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R7, R0 @RW7+d8, R0
R7, R1 @RW7+d8, R1
R7, R2 @RW7+d8, R2
R7, R3 @RW7+d8, R3
R7, R4 @RW7+d8, R4
R7, R5 @RW7+d8, R5
R7, R6 @RW7+d8, R6
R7, R7 @RW7+d8, R7
F0
+7
E0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R6, R0 @RW6+d8, R0
R6, R1 @RW6+d8, R1
R6, R2 @RW6+d8, R2
R6, R3 @RW6+d8, R3
R6, R4 @RW6+d8, R4
R6, R5 @RW6+d8, R5
R6, R6 @RW6+d8, R6
R6, R7 @RW6+d8, R7
D0
+6
C0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R5, R0 @RW5+d8, R0
R5, R1 @RW5+d8, R1
R5, R2 @RW5+d8, R2
R5, R3 @RW5+d8, R3
R5, R4 @RW5+d8, R4
R5, R5 @RW5+d8, R5
R5, R6 @RW5+d8, R6
R5, R7 @RW5+d8, R7
B0
+5
A0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R4, R0 @RW4+d8, R0
R4, R1 @RW4+d8, R1
R4, R2 @RW4+d8, R2
R4, R3 @RW4+d8, R3
R4, R4 @RW4+d8, R4
R4, R5 @RW4+d8, R5
R4, R6 @RW4+d8, R6
R4, R7 @RW4+d8, R7
90
+4
80
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R3, R0 @RW3+d8, R0
R3, R1 @RW3+d8, R1
R3, R2 @RW3+d8, R2
R3, R3 @RW3+d8, R3
R3, R4 @RW3+d8, R4
R3, R5 @RW3+d8, R5
R3, R6 @RW3+d8, R6
R3, R7 @RW3+d8, R7
70
+3
60
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R2, R0 @RW2+d8, R0
R2, R1 @RW2+d8, R1
R2, R2 @RW2+d8, R2
R2, R3 @RW2+d8, R3
R2, R4 @RW2+d8, R4
R2, R5 @RW2+d8, R5
R2, R6 @RW2+d8, R6
R2, R7 @RW2+d8, R7
50
+2
40
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R1, R0 @RW1+d8, R0
R1, R1 @RW1+d8, R1
R1, R2 @RW1+d8, R2
R1, R3 @RW1+d8, R3
R1, R4 @RW1+d8, R4
R1, R5 @RW1+d8, R5
R1, R6 @RW1+d8, R6
R1, R7 @RW1+d8, R7
30
+1
20
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R0, R0 @RW0+d8, R0
R0, R1 @RW0+d8, R1
R0, R2 @RW0+d8, R2
R0, R3 @RW0+d8, R3
R0, R4 @RW0+d8, R4
R0, R5 @RW0+d8, R5
R0, R6 @RW0+d8, R6
R0, R7 @RW0+d8, R7
10
+0
00
APPENDIX B Instructions
Table B.9-18 MOV ea, Ri Instruction (First Byte = 7CH)
MOVW
[email protected]
@RW2, RW1 +d16, RW1
MOVW
[email protected]
@RW3, RW1 +d16, RW1
MOVW
[email protected]
@RW0+, RW1 +RW7,RW1
MOVW
[email protected]
@RW1+,RW1 +RW7,RW1
MOVW
[email protected]
@RW2+,RW1 +d16, RW1
MOVW
MOVW
@RW3+,RW1 addr16, RW1
MOVW
[email protected]
@RW2, RW0 +d16, RW0
MOVW
[email protected]
@RW3, RW0 +d16, RW0
MOVW
[email protected]
@RW0+,RW0 +RW7,RW0
MOVW
[email protected]
@RW1+,RW0 +RW7,RW0
MOVW
[email protected]
@RW2+,RW0 +d16, RW0
MOVW
MOVW
@RW3+,RW0 addr16, RW0
+B
+C
+D
+E
+F
MOVW
MOVW
@RW3+,RW2 addr16, RW2
MOVW
[email protected]
@RW2+,RW2 +d16, RW2
MOVW
[email protected]
@RW1+,RW2 +RW7,RW2
MOVW
[email protected]
@RW0+,RW2 +RW7,RW2
MOVW
[email protected]
@RW3, RW2 +d16, RW2
MOVW
[email protected]
@RW2, RW2 +d16, RW2
MOVW
MOVW
@RW3+,RW3 addr16, RW3
MOVW
[email protected]
@RW2+,RW3 +d16, RW3
MOVW
[email protected]
@RW1+,RW3 -+RW7,RW3
MOVW
[email protected]
@RW0+,RW3 +RW7,RW3
MOVW
[email protected]
@RW3, RW3 +d16, RW3
MOVW
[email protected]
@RW2, RW3 +d16, RW3
MOVW
[email protected]
@RW1, RW3 +d16, RW3
MOVW
MOVW
@RW3+,RW4 addr16, RW4
MOVW
[email protected]
@RW2+,RW4 +d16, RW4
MOVW
[email protected]
@RW1+,RW4 +RW7,RW4
MOVW
[email protected]
@RW0+,RW4 +RW7,RW4
MOVW
[email protected]
@RW3, RW4 +d16, RW4
MOVW
[email protected]
@RW2, RW4 +d16, RW4
MOVW
[email protected]
@RW1, RW4 +d16, RW4
MOVW
MOVW
@RW3+,RW5 addr16, RW5
MOVW
[email protected]
@RW2+,RW5 +d16, RW5
MOVW
[email protected]
@RW1+,RW5 +RW7,RW5
MOVW
[email protected]
@RW0+,RW5 +RW7,RW5
MOVW
[email protected]
@RW3, RW5 +d16, RW5
MOVW
[email protected]
@RW2, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW5 +d16, RW5
MOVW
MOVW
@RW3+,RW6 addr16, RW6
MOVW
MOVW @PC
@RW2+,RW6 +d16, RW6
MOVW
[email protected]
@RW1+,RW6 +RW7,RW6
MOVW
[email protected]
@RW0+,RW6 +RW7,RW6
MOVW
[email protected]
@RW3, RW6 +d16, RW6
MOVW
[email protected]
@RW2, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW6 +d16, RW6
MOVW
MOVW
@RW3+,RW7 addr16, RW7
MOVW
[email protected]
@RW2+,RW7 +d16, RW7
MOVW
[email protected]
@RW1+,RW7 +RW7,RW7
MOVW
[email protected]
@RW0+,RW7 +RW7,RW7
MOVW
[email protected]
@RW3, RW7 +d16, RW7
MOVW
[email protected]
@RW2, RW7 +d16, RW7
MOVW
[email protected]
@RW1, RW7 +d16, RW7
MOVW
[email protected]
@RW0, RW7 +d16, RW7
+A
MOVW
[email protected]
@RW1, RW2 +d16, RW2
MOVW
[email protected]
@RW0, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW1 +d16, RW1
MOVW
[email protected]
@RW0, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW0 +d16, RW0
MOVW
[email protected]
@RW0, RW4 +d16, RW4
+9
MOVW
[email protected]
@RW0, RW3 +d16, RW3
MOVW
[email protected]
@RW0, RW1 +d16, RW1
MOVW
[email protected]
@RW0, RW0 +d16, RW0
+8
MOVW
[email protected]
@RW0, RW2 +d16, RW2
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW7, RW0 @RW7+d8, RW0
RW7, RW1 @RW7+d8, RW1 RW7, RW2 @RW7+d8, RW2 RW7, RW3 @RW7+d8, RW3 RW7, RW4 @RW7+d8, RW4 RW7, RW5 @RW7+d8, RW5 RW7, RW6 @RW7+d8, RW6 RW7, RW7 @RW7+d8, RW7
F0
+7
E0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW6, RW0 @RW6+d8, RW0
RW6, RW1 @RW6+d8, RW1 RW6, RW2 @RW6+d8, RW2 RW6, RW3 @RW6+d8, RW3 RW6, RW4 @RW6+d8, RW4 RW6, RW5 @RW6+d8, RW5 RW6, RW6 @RW6+d8, RW6 RW6, RW7 @RW6+d8, RW7
D0
+6
C0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW5, RW0 @RW5+d8, RW0
RW5, RW1 @RW5+d8, RW1 RW5, RW2 @RW5+d8, RW2 RW5, RW3 @RW5+d8, RW3 RW5, RW4 @RW5+d8, RW4 RW5, RW5 @RW5+d8, RW5 RW5, RW6 @RW5+d8, RW6 RW5, RW7 @RW5+d8, RW7
B0
+5
A0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW4, RW0 @RW4+d8, RW0
RW4, RW1 @RW4+d8, RW1 RW4, RW2 @RW4+d8, RW2 RW4, RW3 @RW4+d8, RW3 RW4, RW4 @RW4+d8, RW4 RW4, RW5 @RW4+d8, RW5 RW4, RW6 @RW4+d8, RW6 RW4, RW7 @RW4+d8, RW7
90
+4
80
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW3, RW0 @RW3+d8, RW0
RW3, RW1 @RW3+d8, RW1 RW3, RW2 @RW3+d8, RW2 RW3, RW3 @RW3+d8, RW3 RW3, RW4 @RW3+d8, RW4 RW3, RW5 @RW3+d8, RW5 RW3, RW6 @RW3+d8, RW6 RW3, RW7 @RW3+d8, RW7
70
+3
60
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW2, RW0 @RW2+d8, RW0
RW2, RW1 @RW2+d8, RW1 RW2, RW2 @RW2+d8, RW2 RW2, RW3 @RW2+d8, RW3 RW2, RW4 @RW2+d8, RW4 RW2, RW5 @RW2+d8, RW5 RW2, RW6 @RW2+d8, RW6 RW2, RW7 @RW2+d8, RW7
50
+2
40
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW1, RW0 @RW1+d8, RW0
RW1, RW1 @RW1+d8, RW1 RW1, RW2 @RW1+d8, RW2 RW1, RW3 @RW1+d8, RW3 RW1, RW4 @RW1+d8, RW4 RW1, RW5 @RW1+d8, RW5 RW1, RW6 @RW1+d8, RW6 RW1, RW7 @RW1+d8, RW7
30
+1
20
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW0, RW0 @RW0+d8, RW0
RW0, RW1 @RW0+d8, RW1 RW0, RW2 @RW0+d8, RW2 RW0, RW3 @RW0+d8, RW3 RW0, RW4 @RW0+d8, RW4 RW0, RW5 @RW0+d8, RW5 RW0, RW6 @RW0+d8, RW6 RW0, RW7 @RW0+d8, RW7
10
+0
00
APPENDIX B Instructions
Table B.9-19 MOVW ea, Rwi Instruction (First Byte = 7DH)
531
532
XCH
XCH
XCH
XCH
R1,
XCH
XCH R1,
R1,@RW2 W2+d16, A
XCH
XCH
R2,
XCH
XCH R2,
R2,@RW2 W2+d16, A
XCH
XCH
R3,
XCH
XCH R3,
R3,@RW2 W2+d16, A
XCH
XCH
R4,
XCH
XCH R4,
R4,@RW2 W2+d16, A
XCH
XCH
R5,
XCH
XCH R5,
R5,@RW2 W2+d16, A
XCH
XCH
R6,
XCH
XCH R6,
R6,@RW2 W2+d16, A
XCH
XCH
R7,
XCH
XCH R7,
R7,@RW2 W2+d16, A
XCH
XCH
XCH
XCH
XCH
R1, XCH
XCH
R2, XCH
XCH
R3, XCH
XCH
R4, XCH
XCH
R5, XCH
XCH
R6, XCH
XCH
R7,
+F R0,@RW3+ R0, addr16
XCH
XCH
R1,@RW3+ R1, addr16
XCH
XCH
R2,@RW3+ R2, addr16
XCH
XCH
R3,@RW3+ R3, addr16
XCH
XCH
R4,@RW3+ R4, addr16
XCH
XCH
R5,@RW3+ R5, addr16
XCH
XCH
R6,@RW3+ R6, addr16
XCH
XCH
R7,@RW3+ R7, addr16
+E R0,@RW2+ @PC+d16 R1,@RW2+ @PC+d16 R2,@RW2+ @PC+d16 R3,@RW2+ @PC+d16 R4,@RW2+ @PC+d16 R5,@RW2+ @PC+d16 R6,@RW2+ @PC+d16 R7,@RW2+ @PC+d16
R0, XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW1+RW7 R1,@RW1+ @RW1+RW7 R2,@RW1+ @RW1+RW7 R3,@RW1+ @RW1+RW7 R4,@RW1+ @RW1+RW7 R5,@RW1+ @RW1+RW7 R6,@RW1+ @RW1+RW7 R7,@RW1+ @RW1+RW7
+D R0,@RW1+
XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW0+RW7 R1,@RW0+ @RW0+RW7 R2,@RW0+ @RW0+RW7 R3,@RW0+ @RW0+RW7 R4,@RW0+ @RW0+RW7 R5,@RW0+ @RW0+RW7 R6,@RW0+ @RW0+RW7 R7,@RW0+ @RW0+RW7
XCH
+C R0,@RW0+
+B R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
R0,
+A R0,@RW2 W2+d16, A
R0,
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
+9
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
+8
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
F0
+7
E0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH)
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2+ @PC+d16
RW1,@RW2+ @PC+d16
RW2,@RW2+ @PC+d16
RW3,@RW2+ @PC+d16
RW4,@RW2+ @PC+d16
RW5,@RW2+ @PC+d16
RW6,@RW2+ @PC+d16
RW7,@RW2+ @PC+d16
XCHW
XCHW
RW0,@RW3+ RW0, addr16
+E
+F
XCHW
XCHW
RW7,@RW3+ RW7, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW1+ @RW1+RW7 RW1,@RW1+ @RW1+RW7 RW2,@RW1+ @RW1+RW7 RW3,@RW1+ @RW1+RW7 RW4,@RW1+ @RW1+RW7 RW5,@RW1+ @RW1+RW7 RW6,@RW1+ @RW1+RW7 RW7,@RW1+ @RW1+RW7
+D
XCHW
XCHW
RW6,@RW3+ RW6, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
+C
XCHW
XCHW
RW5,@RW3+ RW5, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW3 @RW3+d16
RW1,@RW3 @RW3+d16
RW2,@RW3 @RW3+d16
RW3,@RW3 @RW3+d16
RW4,@RW3 @RW3+d16
RW5,@RW3 @RW3+d16
RW6,@RW3 @RW3+d16
RW7,@RW3 @RW3+d16
+B
XCHW
XCHW
RW4,@RW3+ RW4, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2 @RW2+d16
RW1,@RW2 @RW2+d16
RW2,@RW2 @RW2+d16
RW3,@RW2 @RW2+d16
RW4,@RW2 @RW2+d16
RW5,@RW2 @RW2+d16
RW6,@RW2 @RW2+d16
RW7,@RW2 @RW2+d16
+A
XCHW
XCHW
RW3,@RW3+ RW3, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW1 @RW1+d16
RW1,@RW1 @RW1+d16
RW2,@RW1 @RW1+d16
RW3,@RW1 @RW1+d16
RW4,@RW1 @RW1+d16
RW5,@RW1 @RW1+d16
RW6,@RW1 @RW1+d16
RW7,@RW1 @RW1+d16
+9
XCHW
XCHW
RW2,@RW3+ RW2, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW0 @RW0+d16
RW1,@RW0 @RW0+d16
RW2,@RW0 @RW0+d16
RW3,@RW0 @RW0+d16
RW4,@RW0 @RW0+d16
RW5,@RW0 @RW0+d16
RW6,@RW0 @RW0+d16
RW7,@RW0 @RW0+d16
+8
XCHW
XCHW
RW1,@RW3+ RW1, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW7 @RW7+d8
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
RW5, RW7 @RW7+d8
RW6, RW7 @RW7+d8
RW7, RW7 @RW7+d8
F0
+7
E0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW6 @RW6+d8
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
RW5, RW6 @RW6+d8
RW6, RW6 @RW6+d8
RW7, RW6 @RW6+d8
D0
+6
C0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW5 @RW5+d8
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
RW5, RW5 @RW5+d8
RW6, RW5 @RW5+d8
RW7, RW5 @RW5+d8
B0
+5
A0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW4 @RW4+d8
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
RW5, RW4 @RW4+d8
RW6, RW4 @RW4+d8
RW7, RW4 @RW4+d8
90
+4
80
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW3 @RW3+d8
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
RW5, RW3 @RW3+d8
RW6, RW3 @RW3+d8
RW7, RW3 @RW3+d8
70
+3
60
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW2 @RW2+d8
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
RW5, RW2 @RW2+d8
RW6, RW2 @RW2+d8
RW7, RW2 @RW2+d8
50
+2
40
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW1 @RW1+d8
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
RW5, RW1 @RW1+d8
RW6, RW1 @RW1+d8
RW7, RW1 @RW1+d8
30
+1
20
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW0 @RW0+d8
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
RW5, RW0 @RW0+d8
RW6, RW0 @RW0+d8
RW7, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-21 XCHW RWi, ea Instruction (First Byte = 7FH)
533
APPENDIX B Instructions
534
INDEX
INDEX
The index follows on the next page.
This is listed in alphabetic order.
535
INDEX
Index
Numerics
16-bit Free Running Timer
16-bit Free Running Timer ................................ 174
16-bit Free Running Timer Block Diagram ......... 177
16-bit Free Running Timer Operation................. 182
16-bit Free Running Timer Timing .................... 183
16-bit I/O Timer
Block Diagram of 16-bit I/O Timer .................... 175
16-bit I/O Timer Registers
16-bit I/O Timer Registers................................. 176
16-bit Reload Register
16-bit Timer Register (TMR)/16-bit Reload Register
(TMRLR) ........................................... 204
16-bit Reload Timer
Block Diagram of 16-bit Reload Timer............... 199
Input Pin Functions of 16-bit Reload Timer
(in Internal Clock Mode)...................... 206
Internal Clock Operation
of 16-bit Reload Timer......................... 205
Outline of 16-bit Reload Timer
(with Event Count Function) ................ 198
Output Pin Functions of 16-bit Reload
Timer ................................................. 208
Pin Name of 16-bit Reload Timer ...................... 199
Underflow Operation of 16-bit Reload Timer...... 207
16-bit Reload Timer Register
16-bit Reload Timer Register............................. 200
16-bit Timer Register
16-bit Timer Register (TMR)/16-bit Reload Register
(TMRLR) ........................................... 204
1M/2M-bit Flash Memory
1M/2M-bit Flash Memory Features.................... 416
Programming Example of 1M/2M-bit
Flash Memory..................................... 444
Sector Configuration of the 1M/2M-bit
Flash Memory..................................... 417
2 Channels Per One Module
Input Capture (2 Channels Per One Module) ....... 174
Output Compare
(2 Channels Per One Module)............... 174
24-bit Operand
24-bit Operand Specification ............................... 29
32-bit Register Indirect Specification
32-bit Register Indirect Specification ................... 29
8/16-bit PPG
8/16-bit PPG Interrupts ..................................... 228
8/16-bit PPG Output Operation.......................... 225
8/16-bit PPG Registers...................................... 215
Block Diagram of 8/16-bit PPG ......................... 213
536
Controlling Pin Output of 8/16-bit
PPG Pulses......................................... 227
Function of 8/16-bit PPG .................................. 212
Initial Values of 8/16-bit PPG Hardware ............ 229
Operation Modes of 8/16-bit PPG...................... 224
Operations of 8/16-bit PPG ............................... 224
Relationship Between 8/16-bit PPG Reload Value and
Pulse Width........................................ 225
Selecting a Count Clock for 8/16-bit PPG .......... 226
INDEX
A
A
Accumulator (A)................................................ 35
A/D Control Status Register
A/D Control Status Register 1 (ADCS1) ............ 253
A/D Converter
A/D Converter Registers................................... 249
Block Diagram of A/D Converter ...................... 248
Features of A/D Converter ................................ 246
A/D Converter Registers
A/D Converter Registers................................... 249
A/D Data Registers
A/D Data Registers 0/1
(ADCR0 and ADCR1)......................... 256
Acceptance Filter
Setting Acceptance Filter .................................. 393
Acceptance Filtering ........................................ 389
Acceptance Mask Registers
Acceptance Mask Registers 0/1
(AMR0/AMR1) .................................. 378
Acceptance Mask Select Register
Acceptance Mask Select Register (AMSR)......... 376
Access
Access to the Low-Power Mode Control
Register................................................ 93
Accessing Multi-byte Data.................................. 32
Accumulator
Accumulator (A)................................................ 35
Activating
Activating the Watch-dog Timer ....................... 166
ADCR
A/D Data Registers 0/1
(ADCR0 and ADCR1)......................... 256
ADCS
A/D Control Status Register 1 (ADCS1) ............ 253
Control Status Register 0 (ADCS0).................... 250
Address Generation
Address Generation Types .................................. 27
Address Match Detection Function
Block Diagram of the Address Match Detection
Function............................................. 404
Operation of the Address Match Detection
Function............................................. 407
System Configuration Example of the Address Match
Detection Function .............................. 408
Addressing
Addressing ...................................................... 475
Direct Addressing ............................................ 477
Indirect Addressing .......................................... 483
ADER
Analog Input Enable Register (ADER)............... 154
Alternative Mode
Alternative Mode ............................................. 418
AMR
Acceptance Mask Registers 0/1
(AMR0/AMR1)...................................378
AMSR
Acceptance Mask Select Register (AMSR) .........376
Analog Input Enable Register
Analog Input Enable Register ............................247
Analog Input Enable Register (ADER) ...............154
Application Example
Application Example of UART0 ........................292
ARSR
Automatic Ready Function Selection Register
(ARSR) ..............................................135
Asynchronous
Asynchronous (Start-Stop Synchronized) Mode
Receive Operation ...............................311
Asynchronous (Start-Stop Synchronized) Mode
Transfer Data Format ...........................311
Asynchronous (Start-Stop Synchronized) Mode
Transmit Operation ..............................311
CLK Asynchronous Baud Rate ..........................281
Automatic Ready Function Selection Register
Automatic Ready Function Selection Register
(ARSR) ..............................................135
B
Bank Addressing Types
Bank Addressing Types.......................................30
Bank Select Prefix
Bank Select Prefix ..............................................44
BAP
Buffer Address Pointer (BAP) .............................72
Basic Configuration
Basic Configuration of MB90F543/F549/F543G(S)/
F548G(S)/F549G(S)/F546G(S)/F548GL(S)
Serial Programming Connection............450
Baud Rate
CLK Asynchronous Baud Rate ..........................281
CLK Synchronous Baud Rate ............................281
Bit Timing
Setting Bit Timing ............................................393
Bit Timing Register
Bit Timing Register (BTR) ................................362
Block Diagram
16-bit Free Running Timer Block Diagram .........177
Block Diagram .....................................................5
Block Diagram of 16-bit I/O Timer ....................175
Block Diagram of 16-bit Reload Timer ...............199
Block Diagram of 8/16-bit PPG .........................213
Block Diagram of A/D Converter.......................248
Block Diagram of CAN Controller .....................343
Block Diagram of Delayed Interrupt...................232
Block Diagram of DTP/External Interrupts .........236
Block Diagram of External Memory Access........133
537
INDEX
Block Diagram of Low-Power Control Circuit ...... 90
Block Diagram of Pull-up Control Register
(PUCR0 to PUCR3) ............................ 153
Block Diagram of ROM Mirroring Function Selection
Module............................................... 412
Block Diagram of the Address Match Detection
Function ............................................. 404
Block Diagram of Timebase Timer .................... 157
Block Diagram of Watch Timer......................... 169
Input Capture Block Diagram ............................ 192
Output Compare Block Diagram........................ 184
Serial I/O Block Diagram.................................. 322
UART0 Block Diagram .................................... 271
UART1 Block Diagram .................................... 297
Watch-dog Timer Block Diagram ...................... 163
BTR
Bit Timing Register (BTR)................................ 362
Buffer Address Pointer
Buffer Address Pointer (BAP) ............................. 72
Bus Control Signal Selection Register
Bus Control Signal Selection Register
(ECSR) .............................................. 138
Bus Mode
Memory Space in Each Bus Mode ..................... 131
Bus Operation Stop
Conditions for Canceling Bus Operation Stop
(HALT=0) .......................................... 357
Conditions for Setting Bus Operation Stop
(HALT=1) .......................................... 357
State During Bus Operation Stop (HALT=1)....... 358
Bus Pin Control Circuit
External Memory Access
(Bus Pin Control Circuit) ..................... 133
BVAL
Caution for Disabling Message Buffers
by BVAL Bits ..................................... 402
BVAL Bits
Caution for Disabling Message Buffers
by BVAL Bits ..................................... 402
BVALR
Message Buffer Valid Register (BVALR)........... 364
C
Calculating
Calculating the Execution Cycle Count .............. 492
CAN
Block Diagram of CAN Controller..................... 343
Canceling a Transmission Request from the CAN
Controller ........................................... 386
Completing Transmission of the CAN
Controller ........................................... 387
Features of CAN Controller............................... 342
Reception Flowchart of the CAN Controller ....... 392
Starting Transmission of the CAN Controller...... 386
538
Transmission Flowchart of the CAN
Controller........................................... 387
CAN Controller
Block Diagram of CAN Controller .................... 343
Canceling a Transmission Request from the CAN
Controller........................................... 386
Completing Transmission of the CAN
Controller........................................... 387
Features of CAN Controller .............................. 342
Reception Flowchart of the CAN Controller ....... 392
Starting Transmission of the CAN Controller ..... 386
Transmission Flowchart of the CAN
Controller........................................... 387
Canceling a Transmission Request
Canceling a Transmission Request from the CAN
Controller........................................... 386
Caution
Caution for Disabling Message Buffers
by BVAL Bits .................................... 402
CCR
Condition Code Register (CCR) .......................... 37
CDCR
UART1 Communication Prescaler Control Register
(CDCR) ............................................. 306
CKSCR
Clock Selection Register (CKSCR)...................... 94
Clearing
Clearing the Watch-dog Counter ....................... 166
CLK
CLK Asynchronous Baud Rate.......................... 281
CLK Synchronous Baud Rate............................ 281
CLK Synchronous Mode Transfer Data
Format ............................................... 312
Control Register Settings for CLK Synchronous
Mode ................................................. 312
End of Communication in CLK Synchronous
Mode ................................................. 313
Start of Communication in CLK Synchronous
Mode ................................................. 313
CLK Asynchronous Baud Rate
CLK Asynchronous Baud Rate.......................... 281
CLK Synchronous Baud Rate
CLK Synchronous Baud Rate............................ 281
CLK Synchronous Mode
CLK Synchronous Mode Transfer Data
Format ............................................... 312
Control Register Settings for CLK Synchronous
Mode ................................................. 312
End of Communication in CLK Synchronous
Mode ................................................. 313
Start of Communication in CLK Synchronous
Mode ................................................. 313
Clock Generator
Notes on Clock Generator................................... 78
INDEX
Clock Selection
Status Transition for Clock Selection ................... 97
UART1 Clock Selection ................................... 308
Clock Selection Register
Clock Selection Register (CKSCR)...................... 94
CMR
Common Register Bank Prefix (CMR)................. 45
Command Sequence Table
Command Sequence Table................................ 422
Common Register Bank Prefix
Common Register Bank Prefix (CMR)................. 45
Communication Flow Chart
UART1 Communication Flow Chart.................. 319
Compare
Control Status Register of Output Compare
(OCS0/OCS1)..................................... 186
Output Compare .............................................. 184
Output Compare
(2 Channels Per One Module) .............. 174
Output Compare Block Diagram ....................... 184
Output Compare Register (OCCP0,OCCP1) ....... 185
Output Compare Timing ................................... 190
Sample of a Output Waveform with Two Compare
Registers
(The Initial Output Value is "0".) .......... 190
Sample of Output Waveform when Compare Registers
0 and 1 are Used
(The Initial Output Value is "0".) .......... 189
Compare Registers
Sample of Output Waveform when Compare Registers
0 and 1 are Used
(The Initial Output Value is "0".) .......... 189
Completing Reception
Completing Reception ...................................... 391
Completing Transmission
Completing Transmission of the CAN
Controller........................................... 387
Condition Code Register
Condition Code Register (CCR) .......................... 37
Conditions
Conditions for Canceling Bus Operation Stop
(HALT=0).......................................... 357
Conditions for Setting Bus Operation Stop
(HALT=1).......................................... 357
Configuration
Basic Configuration of MB90F543/F549/F543G(S)/
F548G(S)/F549G(S)/F546G(S)/F548GL(S)
Serial Programming Connection ........... 450
Sector Configuration of the 1M/2M-bit
Flash Memory .................................... 417
Setting Configuration of Multi-level Message
Buffer ................................................ 399
System Configuration Example of the Address Match
Detection Function .............................. 408
UART1 Sample Application
(System Configuration in Mode 1) ........319
Consecutive Prefix Codes
Consecutive Prefix Codes....................................46
Continuous Mode
Continuous Mode .............................................258
Example of Starting EI2OS in Continuous
Mode..................................................263
Control Register
Control Register Settings for CLK Synchronous
Mode..................................................312
Control Signals
Flash Memory Control Signals...........................418
Control Status Register
Control Status Register (CSR) ...........................354
Control Status Register 0 (ADCS0) ....................250
Control Status Register of Output Compare
(OCS0/OCS1) .....................................186
Controlling Pin Output
Controlling Pin Output of 8/16-bit
PPG Pulses .........................................227
Conversion
Conversion Data Protection Function .................267
Conversion Using EI2OS...................................260
Flow of Conversion Data Protection Function
(When EI2OS is Used) .........................268
Notes on Using the Conversion Data Protection
Function .............................................268
Conversion Data Protection Function
Flow of Conversion Data Protection Function
(When EI2OS is Used) .........................268
Notes on Using the Conversion Data Protection
Function .............................................268
Count Clock
Selecting a Count Clock for 8/16-bit PPG ...........226
Counter Operation State
Counter Operation State ....................................209
CPU
Intermittent CPU Operation ...............................112
Intermittent CPU Operation Function ...................88
Outline of CPU...................................................26
Outline of CPU Memory Space............................27
CSR
Control Status Register (CSR) ...........................354
D
Data Counter
Data Counter (DCT) ...........................................69
Data Format
Transfer Data Format ........................................285
Data Frame
Processing for Reception of Data Frame and Remote
Frame .................................................390
539
INDEX
Data Polling Flag
Data Polling Flag (DQ7) ................................... 426
Data Protection
Conversion Data Protection Function ................. 267
Data Register
Data Register x (x = 0 to 15) (DTRx) ................. 384
List of Message Buffers (Data Registers)............ 351
List of Message Buffers (DLC Registers and Data
Registers) ........................................... 349
Serial Shift Data Register (SDR)........................ 329
DCT
Data Counter (DCT) ........................................... 69
DDR
Port Direction Register (DDR0 to DDRA)
(for Port 0 to Port A)............................ 151
Delayed Interrupt
Block Diagram of Delayed Interrupt .................. 232
Delayed Interrupt Cause Issuance/Cancellation
Register (DIRR) .................................. 233
Delayed Interrupt Occurrence ............................ 234
Delayed Interrupt Cause Issuance/Cancellation
Register
Delayed Interrupt Cause Issuance/Cancellation
Register (DIRR) .................................. 233
Description
Description of Instruction Presentation Items and
Symbols ............................................. 495
Detailed
Detailed Explanation of Flash Memory
Write/Erase......................................... 433
Direct Addressing
Direct Addressing............................................. 477
DIRR
Delayed Interrupt Cause Issuance/Cancellation
Register (DIRR) .................................. 233
Disabling Message Buffers
Caution for Disabling Message Buffers
by BVAL Bits ..................................... 402
DIV A,Ri
Notes on Using "DIV A,Ri" and "DIVW A,RWi"
Instructions ........................................... 47
DIVW A,RWi
Notes on Using "DIV A,Ri" and "DIVW A,RWi"
Instructions ........................................... 47
DLC Register
DLC Register x (x = 0 to 15) (DLCRx) .............. 383
List of Message Buffers (DLC Registers and Data
Registers) ........................................... 349
DLCRx
DLC Register x (x = 0 to 15) (DLCRx) .............. 383
DQ2
Toggle Bit 2 Flag (DQ2) ................................... 431
DQ3
Sector Erase Timer Flag (DQ3) ......................... 430
540
DQ5
Timing Limit Exceeded Flag (DQ5) .................. 429
DQ6
Toggle Bit Flag (DQ6) ..................................... 428
DQ7
Data Polling Flag (DQ7)................................... 426
DTP
Block Diagram of DTP/External Interrupts......... 236
DTP Operation ................................................ 241
DTP/External Interrupts Registers ..................... 237
Notes on Using DTP/External Interrupts ............ 243
Outline of DTP/External Interrupts .................... 236
Switching Between External Interrupt and DTP
Requests ............................................ 242
DTP Requests
Switching Between External Interrupt and DTP
Requests ............................................ 242
DTP/External Interrupt
Block Diagram of DTP/External Interrupts......... 236
DTP/External Interrupt Cause Register (EIRR:
External Interrupt Request Register) ..... 238
DTP/External Interrupt Enable Register (ENIR:
Interrupt Request Enable Register) ....... 238
DTP/External Interrupts Registers ..................... 237
Notes on Using DTP/External Interrupts ............ 243
Outline of DTP/External Interrupts .................... 236
DTP/External Interrupt Cause Register
DTP/External Interrupt Cause Register (EIRR:
External Interrupt Request Register) ..... 238
DTP/External Interrupt Enable Register
DTP/External Interrupt Enable Register (ENIR:
Interrupt Request Enable Register) ....... 238
DTRx
Data Register x (x = 0 to 15) (DTRx)................. 384
E
Each Bus Mode
Memory Space in Each Bus Mode ..................... 131
ECSR
Bus Control Signal Selection Register
(ECSR) .............................................. 138
Effective Address Field
Effective Address Field ............................ 476, 494
2
EI OS
Conversion Using EI2OS .................................. 260
EI2OS (Extended Intelligent I/O Service) ........... 291
EI2OS Status Register (ISCS).............................. 70
Example of Starting EI2OS in Continuous
Mode ................................................. 263
Example of Starting EI2OS in Single Mode ........ 261
Example of Starting EI2OS in Stop Mode........... 265
Execution Time of the Extended Intelligent I/O
Service (EI2OS) .................................... 75
Extended Intelligent I/O Service (EI2OS) ............. 64
INDEX
Flow of Conversion Data Protection Function
(When EI2OS is Used)......................... 268
Intelligent I/O Service (EI2OS).......................... 320
Intelligent I/O Service (EI2OS) Function and
Interrupts............................................ 198
Operation Flow of the Extended Intelligent I/O
Service (EI2OS) .................................... 73
Structure of Extended Intelligent I/O Service
(EI2OS)................................................ 65
EI2OS Status Register
EI2OS Status Register (ISCS).............................. 70
EIRR
DTP/External Interrupt Cause Register (EIRR:
External Interrupt Request Register) ..... 238
ELVR
Request Level Setting Register
(ELVR: External Level Register).......... 239
End of Communication
End of Communication in CLK Synchronous
Mode ................................................. 313
ENIR
DTP/External Interrupt Enable Register (ENIR:
Interrupt Request Enable Register)........ 238
Erasing All Data
Erasing All Data in the Flash Memory
(Erasing Chips) ................................... 437
Erasing Chips
Erasing All Data in the Flash Memory
(Erasing Chips) ................................... 437
Erasing Optional Data
Erasing Optional Data (Erasing Sectors) in the Flash
Memory ............................................. 438
Erasing Sectors
Erasing Optional Data (Erasing Sectors) in the Flash
Memory ............................................. 438
Erasing Sectors in the Flash Memory ................. 438
Error
Receive and Transmit Error Counters
(RTEC) .............................................. 361
Evasion
Evasion of Notes................................................ 48
Event Count Function
Outline of 16-bit Reload Timer
(with Event Count Function) ................ 198
Example
Application Example of UART0 ....................... 292
Example of Minimum Connection to the Flash
Microcomputer Programmer
(Power Supplied from the
Programmer) ...................................... 460
Example of Minimum Connection to the Flash
Microcomputer Programmer
(User Power Supply Used) ................... 458
Example of Program Patch Processing ............... 409
Example of Serial Programming Connection (Power
Supplied from the Programmer) ............456
Example of Serial Programming Connection
(User Power Supply Used)....................454
Example of Starting EI2OS in Continuous
Mode..................................................263
Example of Starting EI2OS in Single Mode.........261
Example of Starting EI2OS in Stop Mode ...........265
Programming Example of 1M/2M-bit
Flash Memory .....................................444
System Configuration Example of the Address Match
Detection Function...............................408
Exception Due to Execution
Exception Due to Execution of an Undefined
Instruction.............................................76
Execution Cycle Count
Calculating the Execution Cycle Count...............492
Execution Cycle Count......................................491
Execution Time
Execution Time of the Extended Intelligent I/O
Service (EI2OS).....................................75
Extended Intelligent I/O Service
EI2OS (Extended Intelligent I/O Service)............291
Execution Time of the Extended Intelligent I/O
Service (EI2OS).....................................75
Extended Intelligent I/O Service (EI2OS)..............64
Operation Flow of the Extended Intelligent I/O
Service (EI2OS).....................................73
Structure of Extended Intelligent I/O Service
(EI2OS) ................................................65
Extended Intelligent I/O Service Descriptor
Extended Intelligent I/O Service Descriptor
(ISD) ....................................................69
External Address Output Control Register
External Address Output Control Register
(HACR)..............................................137
External Clock
Internal and External Clock ...............................284
External Event Counter
External Event Counter .....................................206
External Interrupt
Block Diagram of DTP/External Interrupts .........236
DTP/External Interrupt Cause Register (EIRR:
External Interrupt Request Register)
..........................................................238
DTP/External Interrupt Enable Register (ENIR:
Interrupt Request Enable Register) ........238
DTP/External Interrupts Registers ......................237
External Interrupt Operation ..............................240
Notes on Using DTP/External Interrupts .............243
Outline of DTP/External Interrupts.....................236
Switching Between External Interrupt and DTP
Requests .............................................242
541
INDEX
External Interrupt Request Register
DTP/External Interrupt Cause Register (EIRR:
External Interrupt Request Register)...... 238
External Level Register
Request Level Setting Register
(ELVR: External Level Register) .......... 239
External Memory Access
Block Diagram of External Memory Access ....... 133
External Memory Access
(Bus Pin Control Circuit) ..................... 133
External Memory Access Control Signal ............ 141
External Memory Access Registers
External Memory Access Registers .................... 134
External Shift Clock Mode
External Shift Clock Mode ................................ 332
F
F2MC-16LX Instruction List
F2MC-16LX Instruction List............................. 498
Feature
1M/2M-bit Flash Memory Features.................... 416
Feature of UART0............................................ 270
Features............................................................... 3
Features of A/D Converter ................................ 246
Features of CAN Controller............................... 342
Features of UART1 .......................................... 296
Fetch Timing
Sample of Input Capture Fetch Timing ............... 195
Flag
Data Polling Flag (DQ7) ................................... 426
Hardware Sequence Flags ................................. 424
Sector Erase Timer Flag (DQ3) ......................... 430
Set Timings of the Six Flags.............................. 287
Status Flag During Transmit
and Receive Operation ......................... 291
Timing Limit Exceeded Flag (DQ5) ................... 429
Toggle Bit 2 Flag (DQ2) ................................... 431
Toggle Bit Flag (DQ6)...................................... 428
UART1 Flags................................................... 314
UART1 Interrupts and Flag Set Timing .............. 315
Flag Change Suppressive Prefix
Flag Change Suppressive Prefix (NCC)................ 45
Flag Set Timings
Flag Set Timings for a Receive Operation
(in Mode 0, 1, or 3).............................. 288
Flag Set Timings for a Receive Operation
(in Mode 2)......................................... 289
Flag Set Timings for a Transmit Operation ......... 290
Flash Memory
1M/2M-bit Flash Memory Features.................... 416
Detailed Explanation of Flash Memory
Write/Erase......................................... 433
Erasing All Data in the Flash Memory
(Erasing Chips) ................................... 437
542
Erasing Optional Data (Erasing Sectors) in the Flash
Memory ............................................. 438
Erasing Sectors in the Flash Memory ................. 438
Flash Memory Control Signals .......................... 418
Flash Memory Control Status Register
(FMCS) ............................................. 420
Flash Memory Mode ........................................ 418
Flash Memory Register .................................... 416
Notes on Using Flash Memory .......................... 442
Programming Example of 1M/2M-bit
Flash Memory .................................... 444
Restarting Erasing of Flash Memory Sectors ...... 441
Sector Configuration of the 1M/2M-bit
Flash Memory .................................... 417
Setting the Flash Memory to the Read/Reset
State .................................................. 434
Suspending Erasing of Flash Memory Sectors
......................................................... 440
Writing Data to the Flash Memory..................... 435
Writing to the Flash Memory ............................ 435
Writing to/Erasing Flash Memory...................... 416
Flash Memory Control Status Register
Flash Memory Control Status Register
(FMCS) ............................................. 420
Flash Memory Mode
Flash Memory Mode ........................................ 418
Flash Memory Register
Flash Memory Register .................................... 416
Flash Microcomputer Programmer
Example of Minimum Connection to the Flash
Microcomputer Programmer
(Power Supplied from the
Programmer) ...................................... 460
Example of Minimum Connection to the Flash
Microcomputer Programmer
(User Power Supply Used)................... 458
Flash Security
Flash Security Feature ...................................... 443
Flow
Flow of Conversion Data Protection Function
(When EI2OS is Used)......................... 268
Flow of Hardware Interrupt Operation ................. 59
FMCS
Flash Memory Control Status Register
(FMCS) ............................................. 420
Format
Asynchronous (Start-Stop Synchronized) Mode
Transfer Data Format .......................... 311
CLK Synchronous Mode Transfer Data
Format ............................................... 312
Setting Frame Format ....................................... 393
Transfer Data Format ....................................... 285
FPT-100P-M05
FPT-100P-M05 Package Dimensions..................... 7
INDEX
FPT-100P-M06
FPT-100P-M06 Package Dimensions..................... 6
Frame Format
Setting Frame Format ....................................... 393
Function
Function of 8/16-bit PPG .................................. 212
Input Pin Functions of 16-bit Reload Timer
(in Internal Clock Mode) ..................... 206
Output Pin Functions of 16-bit Reload
Timer................................................. 208
Pin Functions..................................................... 10
G
General-purpose Registers
General-purpose Registers .................................. 34
H
HACR
External Address Output Control Register
(HACR) ............................................. 137
HALT
Conditions for Canceling Bus Operation Stop
(HALT=0).......................................... 357
Conditions for Setting Bus Operation Stop
(HALT=1).......................................... 357
State During Bus Operation Stop (HALT=1) ...... 358
Handling the Devices
Notes for Handling the Devices ........................... 20
Hardware Interrupt
Flow of Hardware Interrupt Operation ................. 59
Hardware Interrupt Operation.............................. 57
Hardware Interrupt Request During Writing to the
Input-Output Area ................................. 55
Hardware Interrupts ........................................... 55
Structure of Hardware Interrupt ........................... 55
Hardware Sequence Flags
Hardware Sequence Flags ................................. 424
Hardware Standby Mode
Releasing Hardware Standby Mode ................... 111
Transition to Hardware Standby Mode ............... 111
Hold
Hold Function.................................................. 145
Hold Function
Hold Function.................................................. 145
I
I/O
16-bit I/O Timer Registers ................................ 176
Block Diagram of 16-bit I/O Timer.................... 175
EI2OS (Extended Intelligent I/O Service) ........... 291
Execution Time of the Extended Intelligent I/O
Service (EI2OS) .................................... 75
Extended Intelligent I/O Service (EI2OS) ............. 64
Extended Intelligent I/O Service Descriptor
(ISD) ....................................................69
I/O Circuits ........................................................17
I/O Maps .........................................................464
I/O Port Registers .............................................149
I/O Register Address Pointer (IOA)......................70
Intelligent I/O Service (EI2OS) ..........................320
Intelligent I/O Service (EI2OS) Function and
Interrupts ............................................198
Interrupt Function of the Serial I/O Interface .......338
Operation Flow of the Extended Intelligent I/O
Service (EI2OS).....................................73
Outline of I/O Ports ..........................................148
Serial I/O Block Diagram ..................................322
Serial I/O Operation..................................331, 333
Serial I/O Prescaler (SCDCR) ............................330
Serial I/O Resisters ...........................................324
Structure of Extended Intelligent I/O Service
(EI2OS) ................................................65
I/O Circuits
I/O Circuits ........................................................17
I/O Maps
I/O Maps .........................................................464
I/O Port
I/O Port Registers .............................................149
Outline of I/O Ports ..........................................148
I/O Port Registers
I/O Port Registers .............................................149
I/O Register Address Pointer
I/O Register Address Pointer (IOA)......................70
I/O Timer
16-bit I/O Timer Registers .................................176
Block Diagram of 16-bit I/O Timer ....................175
ICR
Interrupt Control Register (ICR) ..........................66
ICS
Input Capture Control Status Register
(ICS01)...............................................193
ID
ID Register x (x = 0 to 15) (IDRx)......................381
List of Message Buffers (ID Registers) ...............346
Setting ID ........................................................393
ID Register
ID Register x (x = 0 to 15) (IDRx)......................381
List of Message Buffers (ID Registers) ...............346
IDE Register
IDE Register (IDER).........................................365
IDER
IDE Register (IDER).........................................365
IDRx
ID Register x (x = 0 to 15) (IDRx)......................381
ILM
Interrupt Level Mask Register (ILM)....................38
543
INDEX
Indirect Addressing
Indirect Addressing .......................................... 483
Initial
Initial Values of 8/16-bit PPG Hardware............. 229
Initial Output Value
Sample of a Output Waveform with Two Compare
Registers
(The Initial Output Value is "0".) .......... 190
Sample of Output Waveform when Compare Registers
0 and 1 are Used
(The Initial Output Value is "0".) .......... 189
Input Capture
Input Capture ................................................... 192
Input Capture (2 Channels Per One Module) ....... 174
Input Capture Block Diagram ............................ 192
Input Capture Input Timing ............................... 196
Sample of Input Capture Fetch Timing ............... 195
Input Capture Control Status Register
Input Capture Control Status Register
(ICS01) .............................................. 193
Input Capture Data Register
Input Capture Data Register (IPCP0/1) ............... 193
Input Impedance
Input Impedance............................................... 247
Input Pin Functions
Input Pin Functions of 16-bit Reload Timer
(in Internal Clock Mode)...................... 206
Instruction
Description of Instruction Presentation Items and
Symbols ............................................. 495
Exception Due to Execution of an Undefined
Instruction ............................................ 76
F2MC-16LX Instruction List............................. 498
Instruction Types.............................................. 474
Interrupt Disable Instructions .............................. 46
Notes on Using "DIV A,Ri" and "DIVW A,RWi"
Instructions ........................................... 47
Restrictions on Interrupt Disable Instructions and
Prefix Instructions ................................. 46
Structure of Instruction Map.............................. 512
Instruction Presentation Items and Symbols
Description of Instruction Presentation Items and
Symbols ............................................. 495
Intelligent I/O Service
Intelligent I/O Service (EI2OS) .......................... 320
Intelligent I/O Service (EI2OS) Function and
Interrupts ............................................ 198
Interface
Interrupt Function of the Serial I/O Interface....... 338
Intermittent
Intermittent CPU Operation Function ................... 88
Intermittent CPU Operation
Intermittent CPU Operation............................... 112
544
Internal and External Clock
Internal and External Clock............................... 284
Internal Clock
Input Pin Functions of 16-bit Reload Timer
(in Internal Clock Mode) ..................... 206
Internal Clock Operation
of 16-bit Reload Timer ........................ 205
Internal Shift Clock Mode
Internal Shift Clock Mode................................. 332
Interrupt
8/16-bit PPG Interrupts..................................... 228
Block Diagram of Delayed Interrupt .................. 232
Block Diagram of DTP/External Interrupts......... 236
Delayed Interrupt Cause Issuance/Cancellation
Register (DIRR).................................. 233
Delayed Interrupt Occurrence ........................... 234
DTP/External Interrupt Cause Register (EIRR:
External Interrupt Request Register) ..... 238
DTP/External Interrupt Enable Register (ENIR:
Interrupt Request Enable Register) ....... 238
DTP/External Interrupts Registers ..................... 237
External Interrupt Operation ............................. 240
Flow of Hardware Interrupt Operation ................. 59
Hardware Interrupt Operation ............................. 57
Hardware Interrupt Request During Writing to the
Input-Output Area................................. 55
Hardware Interrupts ........................................... 55
Intelligent I/O Service (EI2OS) Function and
Interrupts ........................................... 198
Interrupt Control Register (ICR).......................... 66
Interrupt Disable Instructions .............................. 46
Interrupt Function of the Serial I/O Interface ...... 338
Interrupt Level Mask Register (ILM) ................... 38
Interrupt Sources................................................ 51
Interrupt Vector ................................................. 53
Interval Interrupt Function of Timebase
Timer................................................. 160
Interval Interrupt Function of Watch Timer ........ 172
Multiple Interrupts ............................................. 56
Note on Software Interrupt.................................. 63
Notes on Using DTP/External Interrupts ............ 243
Outline of DTP/External Interrupts .................... 236
Outline of Interrupts........................................... 50
Reception Interrupt Enable Register (RIER) ....... 375
Required Time to Start Interrupt Processing ......... 60
Restrictions on Interrupt Disable Instructions and
Prefix Instructions................................. 46
Software Interrupt Operation............................... 62
Software Interrupts............................................. 62
Structure of Hardware Interrupt........................... 55
Structure of Software Interrupts........................... 62
Switching Between External Interrupt and DTP
Requests ............................................ 242
Transmission Interrupt Enable Register
(TIER) ............................................... 371
UART1 Interrupt Sources ................................. 314
INDEX
UART1 Interrupts and Flag Set Timing.............. 315
Interrupt Control Register
Interrupt Control Register (ICR) .......................... 66
Interrupt Disable Instructions
Interrupt Disable Instructions .............................. 46
Restrictions on Interrupt Disable Instructions and
Prefix Instructions ................................. 46
Interrupt Function
Interrupt Function of the Serial I/O Interface ...... 338
Interrupt Level Mask Register
Interrupt Level Mask Register (ILM) ................... 38
Interrupt Request Enable Register
DTP/External Interrupt Enable Register (ENIR:
Interrupt Request Enable Register)........ 238
Interrupt Sources
Interrupt Sources................................................ 51
UART1 Interrupt Sources ................................. 314
Interrupt Vector
Interrupt Vector ................................................. 53
Interval Interrupt Function
Interval Interrupt Function of Timebase
Timer................................................. 160
Interval Interrupt Function of Watch Timer ........ 172
IOA
I/O Register Address Pointer (IOA) ..................... 70
IPCP
Input Capture Data Register (IPCP0/1)............... 193
ISCS
EI2OS Status Register (ISCS).............................. 70
ISD
Extended Intelligent I/O Service Descriptor
(ISD) ................................................... 69
L
Last Event Indicator Register
Last Event Indicator Register (LEIR) ................. 359
LEIR
Last Event Indicator Register (LEIR) ................. 359
List
List of Message Buffers (Data Registers) ........... 351
List of Message Buffers (DLC Registers and Data
Registers) ........................................... 349
List of Message Buffers (ID Registers) .............. 346
List of Overall Control Registers ....................... 344
Low Power Mode Control Register
Low Power Mode Control Register...................... 91
Low Power Mode Control Register (LPMCR) ...... 92
Low-Power Consumption Mode
Low-Power Consumption Modes....................... 102
Operation Status of Low-Power Consumption
Mode ................................................. 104
Setting Low-Power Consumption Mode ............. 394
Status Transition Diagram for Low-Power
Consumption Mode
(Single Clock (System) Parts) ...............123
Status Transition Diagram for Low-Power
Consumption Mode
(Two Clocks System Parts)...................118
Transition Conditions in Low-Power Consumption
Mode..................................................113
Low-Power Control Circuit
Block Diagram of Low-Power Control Circuit.......90
Operation Modes of Low-Power Control
Circuit ..................................................88
Low-Power Mode Control Register
Access to the Low-Power Mode Control
Register ................................................93
LPMCR
Low Power Mode Control Register (LPMCR) .......92
M
Machine Clocks
Switching between Machine Clocks .....................89
Main Clock Oscillation Stabilization Wait Time
Main Clock Oscillation Stabilization
Wait Time.............................................88
MB90540/545 Series
Overview of MB90540/545 Series Products ............2
MB90F543/F549/F543G(S)/F548G(S)/F549G(S)/
F546G(S)/F548GL(S)
Basic Configuration of MB90F543/F549/F543G(S)/
F548G(S)/F549G(S)/F546G(S)/F548GL(S)
Serial Programming Connection............450
Memory Access Modes
Memory Access Modes .....................................128
Memory Space
Memory Space in Each Bus Mode......................131
Memory Space Map............................................28
Multi-byte Data Allocation in Memory Space........32
Outline of CPU Memory Space............................27
Message
Caution for Disabling Message Buffers
by BVAL Bits .....................................402
List of Message Buffers (Data Registers) ............351
List of Message Buffers (DLC Registers and Data
Registers)............................................349
List of Message Buffers (ID Registers) ...............346
Message Buffer Control Registers ......................353
Message Buffer Valid Register (BVALR) ...........364
Message Buffers .......................................353, 380
Procedure for Reception by Message Buffer
(x) ......................................................397
Procedure for Transmission by Message Buffer
(x) ......................................................395
Setting Configuration of Multi-level Message
Buffer.................................................399
Storing Received Message.................................389
545
INDEX
Message Buffer
Caution for Disabling Message Buffers
by BVAL Bits ..................................... 402
List of Message Buffers (Data Registers)............ 351
List of Message Buffers (DLC Registers and Data
Registers) ........................................... 349
List of Message Buffers (ID Registers)............... 346
Message Buffers....................................... 353, 380
Procedure for Reception by Message Buffer
(x)...................................................... 397
Procedure for Transmission by Message Buffer
(x)...................................................... 395
Setting Configuration of Multi-level Message
Buffer ................................................ 399
Message Buffer Control Registers
Message Buffer Control Registers...................... 353
Message Buffer Valid Register
Message Buffer Valid Register (BVALR)........... 364
Minimum Connection
Example of Minimum Connection to the Flash
Microcomputer Programmer
(Power Supplied from the
Programmer)....................................... 460
Example of Minimum Connection to the Flash
Microcomputer Programmer
(User Power Supply Used) ................... 458
Mode
Access to the Low-Power Mode Control
Register ................................................ 93
Alternative Mode ............................................. 418
Asynchronous (Start-Stop Synchronized) Mode
Receive Operation ............................... 311
Asynchronous (Start-Stop Synchronized) Mode
Transfer Data Format........................... 311
Asynchronous (Start-Stop Synchronized) Mode
Transmit Operation.............................. 311
CLK Synchronous Mode Transfer Data
Format ............................................... 312
Continuous Mode ............................................. 258
Control Register Settings for CLK Synchronous
Mode ................................................. 312
End of Communication in CLK Synchronous
Mode ................................................. 313
Example of Starting EI2OS in Continuous
Mode ................................................. 263
Example of Starting EI2OS in Single Mode ........ 261
Example of Starting EI2OS in Stop Mode ........... 265
External Shift Clock Mode ................................ 332
Flag Set Timings for a Receive Operation
(in Mode 0, 1, or 3).............................. 288
Flag Set Timings for a Receive Operation
(in Mode 2)......................................... 289
Flash Memory Mode ........................................ 418
Input Pin Functions of 16-bit Reload Timer
(in Internal Clock Mode)...................... 206
Internal Shift Clock Mode ................................. 332
546
Low Power Mode Control Register...................... 91
Low Power Mode Control Register (LPMCR) ...... 92
Low-Power Consumption Modes ...................... 102
Memory Access Modes .................................... 128
Memory Space in Each Bus Mode ..................... 131
Mode Data ...................................................... 130
Mode Pins ....................................................... 129
Operation Modes of 8/16-bit PPG...................... 224
Operation Modes of Low-Power Control
Circuit ................................................. 88
Operation Status of Low-Power Consumption
Mode ................................................. 104
PPG0 Operation Mode Control Register
(PPGC0) ............................................ 216
PPG1 Operation Mode Control Register
(PPGC1) ............................................ 218
Releasing Hardware Standby Mode ................... 111
Releasing Pseudo Timer Mode .......................... 107
Releasing Sleep Mode ...................................... 106
Releasing Stop Mode ....................................... 109
Releasing Timer Mode ..................................... 108
Serial Mode Control Register 0 (UMC0) ............ 273
Serial Mode Control Status Register
(SMCS) ............................................. 325
Serial Mode Register 1 (SMR1) ........................ 299
Setting Low-power Consumption Mode ............. 394
Single Mode .................................................... 258
Start of Communication in CLK Synchronous
Mode ................................................. 313
Status Transition Diagram for Low-Power
Consumption Mode
(Single Clock (System) Parts) .............. 123
Status Transition Diagram for Low-Power
Consumption Mode
(Two Clocks System Parts) .................. 118
Stop Mode....................................................... 259
Transition Conditions in Low-Power Consumption
Mode ................................................. 113
Transition to Hardware Standby Mode ............... 111
Transition to Pseudo Timer Mode...................... 107
Transition to Sleep Mode.................................. 106
Transition to Stop Mode ................................... 109
Transition to Timer Mode ................................. 108
UART0 Operation Modes ................................. 280
UART1 Operating Modes ................................. 307
UART1 Sample Application
(System Configuration in Mode 1)........ 319
Mode Data
Mode Data ...................................................... 130
Mode Pins
Mode Pins ....................................................... 129
Module
Block Diagram of ROM Mirroring Function Selection
Module .............................................. 412
Input Capture (2 Channels Per One Module) ...... 174
INDEX
Output Compare
(2 Channels Per One Module) .............. 174
Multi-byte Data
Accessing Multi-byte Data.................................. 32
Multi-byte Data Allocation
Multi-byte Data Allocation in Memory Space ....... 32
Multi-level Message Buffer
Setting Configuration of Multi-level Message
Buffer ................................................ 399
Multiple Interrupts
Multiple Interrupts ............................................. 56
Multiplication
PLL Clock Multiplication Function ..................... 89
N
NCC
Flag Change Suppressive Prefix (NCC)................ 45
Negative Clock Operation
Negative Clock Operation......................... 318, 339
Note
Evasion of Notes................................................ 48
Note on Software Interrupt.................................. 63
Notes for Handling the Devices ........................... 20
Notes on Clock Generator................................... 78
Notes on Operation .......................................... 232
Notes on Using "DIV A,Ri" and "DIVW A,RWi"
Instructions........................................... 47
Notes on Using DTP/External Interrupts ............ 243
Notes on Using Flash Memory .......................... 442
Notes on Using the Conversion Data Protection
Function............................................. 268
O
OCCP
Output Compare Register (OCCP0,OCCP1) ....... 185
OCS
Control Status Register of Output Compare
(OCS0/OCS1)..................................... 186
Operating Modes
UART1 Operating Modes ................................. 307
Operation
16-bit Free Running Timer Operation ................ 182
8/16-bit PPG Output Operation ......................... 225
Asynchronous (Start-Stop Synchronized) Mode
Receive Operation............................... 311
Asynchronous (Start-Stop Synchronized) Mode
Transmit Operation ............................. 311
Conditions for Canceling Bus Operation Stop
(HALT=0).......................................... 357
Conditions for Setting Bus Operation Stop
(HALT=1).......................................... 357
Counter Operation State.................................... 209
DTP Operation ................................................ 241
External Interrupt Operation.............................. 240
Flag Set Timings for a Receive Operation
(in Mode 0, 1, or 3) ..............................288
Flag Set Timings for a Receive Operation
(in Mode 2) .........................................289
Flag Set Timings for a Transmit Operation..........290
Flow of Hardware Interrupt Operation ..................59
Hardware Interrupt Operation ..............................57
Intermittent CPU Operation ...............................112
Intermittent CPU Operation Function ...................88
Internal Clock Operation
of 16-bit Reload Timer .........................205
Negative Clock Operation .........................318, 339
Notes on Operation ...........................................232
Operation after Reset Release ..............................80
Operation Modes of 8/16-bit PPG ......................224
Operation Modes of Low-Power Control
Circuit ..................................................88
Operation of the Address Match Detection
Function .............................................407
Operation Status of Low-Power Consumption
Mode..................................................104
Operations of 8/16-bit PPG................................224
PPG0 Operation Mode Control Register
(PPGC0) .............................................216
PPG1 Operation Mode Control Register
(PPGC1) .............................................218
Serial I/O Operation..................................331, 333
Setting Operation Clock for Watch-dog
Timer .................................................172
Shift Operation Start/Stop Timing ......................335
Software Interrupt Operation ...............................62
State During Bus Operation Stop (HALT=1) .......358
Status Flag During Transmit
and Receive Operation .........................291
UART0 Operation Modes..................................280
Underflow Operation of 16-bit Reload Timer ......207
Operation Flow
Operation Flow of the Extended Intelligent I/O
Service (EI2OS).....................................73
Operation Modes
Operation Modes of 8/16-bit PPG ......................224
Operation Modes of Low-Power Control
Circuit ..................................................88
UART0 Operation Modes..................................280
Operation Status
Operation Status of Low-Power Consumption
Mode..................................................104
Oscillation Clock Frequency
Oscillation Clock Frequency and Serial Clock Input
Frequency ...........................................453
Outline
Outline of 16-bit Reload Timer
(with Event Count Function).................198
Outline of CPU...................................................26
Outline of CPU Memory Space............................27
Outline of DTP/External Interrupts.....................236
547
INDEX
Outline of I/O Ports .......................................... 148
Outline of Interrupts ........................................... 50
Output Compare
Control Status Register of Output Compare
(OCS0/OCS1) ..................................... 186
Output Compare............................................... 184
Output Compare
(2 Channels Per One Module)............... 174
Output Compare Block Diagram........................ 184
Output Compare Timing ................................... 190
Output Compare Register
Output Compare Register (OCCP0,OCCP1) ....... 185
Output Pin Functions
Output Pin Functions of 16-bit Reload
Timer ................................................. 208
Output Waveform
Sample of Output Waveform when Compare Registers
0 and 1 are Used
(The Initial Output Value is "0".) .......... 189
Output Waveform with Two Compare Registers
Sample of a Output Waveform with Two Compare
Registers
(The Initial Output Value is "0".) .......... 190
Overall Control Registers
List of Overall Control Registers ....................... 344
Overall Control Registers.................................. 353
Overview
Overview of MB90540/545 Series Products............ 2
P
Package
FPT-100P-M05 Package Dimensions ..................... 7
FPT-100P-M06 Package Dimensions ..................... 6
Package Dimensions
FPT-100P-M05 Package Dimensions ..................... 7
FPT-100P-M06 Package Dimensions ..................... 6
PACSR
Program Address Detection Control Status Register
(PACSR) ............................................ 405
PADR
Program Address Detection Registers
(PADR0 and PADR1).......................... 405
Parity Bit
Parity Bit ......................................................... 286
PC
Program Counter (PC) ........................................ 40
PDR
Port Data Register (PDR0 to PDRA)
(for Port 0 to Port A)............................ 150
Pin Assignment
Pin Assignment .................................................... 8
Pin Control
External Memory Access
(Bus Pin Control Circuit) ..................... 133
548
Pin Functions
Input Pin Functions of 16-bit Reload Timer
(in Internal Clock Mode) ..................... 206
Output Pin Functions of 16-bit Reload
Timer................................................. 208
Pin Functions..................................................... 10
Pin Name
Pin Name of 16-bit Reload Timer ...................... 199
PLL
PLL Clock Multiplication Function ..................... 89
PLL Clock
PLL Clock Multiplication Function ..................... 89
Port
Port Data Register (PDR0 to PDRA)
(for Port 0 to Port A) ........................... 150
Port Direction Register (DDR0 to DDRA)
(for Port 0 to Port A) ........................... 151
Pull-up Control Register (PUCR0 to PUCR3)
(for Port 0 to Port 3) ............................ 152
Port Data Register
Port Data Register (PDR0 to PDRA)
(for Port 0 to Port A) ........................... 150
Port Direction Register
Port Direction Register (DDR0 to DDRA)
(for Port 0 to Port A) ........................... 151
Power Supplied
Example of Minimum Connection to the Flash
Microcomputer Programmer
(Power Supplied from the
Programmer) ...................................... 460
Example of Serial Programming Connection (Power
Supplied from the Programmer) ........... 456
PPG
8/16-bit PPG Interrupts..................................... 228
8/16-bit PPG Output Operation ......................... 225
8/16-bit PPG Registers ..................................... 215
Block Diagram of 8/16-bit PPG......................... 213
Controlling Pin Output of 8/16-bit
PPG Pulses......................................... 227
Function of 8/16-bit PPG .................................. 212
Initial Values of 8/16-bit PPG Hardware ............ 229
Operation Modes of 8/16-bit PPG...................... 224
Operations of 8/16-bit PPG ............................... 224
PPG Unit 0 Clock Selection Register
(PPG01) ............................................. 221
PPG0 Operation Mode Control Register
(PPGC0) ............................................ 216
PPG1 Operation Mode Control Register
(PPGC1) ............................................ 218
Relationship Between 8/16-bit PPG Reload Value and
Pulse Width........................................ 225
Selecting a Count Clock for 8/16-bit PPG .......... 226
PPG Unit 0 Clock Selection Register
PPG Unit 0 Clock Selection Register
(PPG01) ............................................. 221
INDEX
PPG0 Operation Mode Control Register
PPG0 Operation Mode Control Register
(PPGC0) ............................................ 216
PPG1 Operation Mode Control Register
PPG1 Operation Mode Control Register
(PPGC1) ............................................ 218
PPGC
PPG0 Operation Mode Control Register
(PPGC0) ............................................ 216
PPG1 Operation Mode Control Register
(PPGC1) ............................................ 218
Precautions
Precautions on UART1 Using ........................... 320
Prefix Instructions
Restrictions on Interrupt Disable Instructions and
Prefix Instructions ................................. 46
PRLL/PRLH
Reload Register (PRLL/PRLH) ......................... 223
Procedure
Procedure for Reception by Message Buffer
(x) ..................................................... 397
Procedure for Transmission by Message Buffer
(x) ..................................................... 395
Processing
Example of Program Patch Processing ............... 409
Processing for Reception of Data Frame and Remote
Frame ................................................ 390
Required Time to Start Interrupt Processing ......... 60
Processor Status
Processor Status (PS).......................................... 37
Program
Program Address Detection Registers
(PADR0 and PADR1) ......................... 405
Program Counter (PC) ........................................ 40
Program Address Detection Control Status Register
Program Address Detection Control Status Register
(PACSR)............................................ 405
Program Address Detection Registers
Program Address Detection Registers
(PADR0 and PADR1) ......................... 405
Program Counter
Program Counter (PC) ........................................ 40
Program Patch Processing
Example of Program Patch Processing ............... 409
Programmer
Example of Minimum Connection to the Flash
Microcomputer Programmer
(Power Supplied from the
Programmer) ...................................... 460
Example of Minimum Connection to the Flash
Microcomputer Programmer
(User Power Supply Used) ................... 458
Example of Serial Programming Connection (Power
Supplied from the Programmer)............ 456
Programming Example
Programming Example of 1M/2M-bit
Flash Memory .....................................444
Protection Function
Conversion Data Protection Function .................267
PS
Processor Status (PS) ..........................................37
Pseudo Timer Mode
Releasing Pseudo Timer Mode...........................107
Transition to Pseudo Timer Mode ......................107
PUCR
Block Diagram of Pull-up Control Register
(PUCR0 to PUCR3).............................153
Pull-up Control Register (PUCR0 to PUCR3)
(for Port 0 to Port 3).............................152
Pull-up Control Register
Block Diagram of Pull-up Control Register
(PUCR0 to PUCR3).............................153
Pull-up Control Register (PUCR0 to PUCR3)
(for Port 0 to Port 3).............................152
Pulse Width
Relationship Between 8/16-bit PPG Reload Value and
Pulse Width.........................................225
R
Rate and Data Register
Rate and Data Register 0 (URD0) ......................278
RCR
Reception Complete Register (RCR) ..................372
Ready Function
Automatic Ready Function Selection Register
(ARSR) ..............................................135
Ready Function ................................................143
Receive and Transmit Error Counters
Receive and Transmit Error Counters
(RTEC)...............................................361
Receive Operation
Asynchronous (Start-Stop Synchronized) Mode
Receive Operation ...............................311
Flag Set Timings for a Receive Operation
(in Mode 0, 1, or 3) ..............................288
Flag Set Timings for a Receive Operation
(in Mode 2) .........................................289
Status Flag During Transmit
and Receive Operation .........................291
Receive Overrun
Receive Overrun...............................................390
Receive Overrun Register
Receive Overrun Register (ROVRR) ..................374
Received Message
Storing Received Message.................................389
Reception
Procedure for Reception by Message Buffer
(x) ......................................................397
549
INDEX
Processing for Reception of Data Frame and Remote
Frame................................................. 390
Reception Complete Register
Reception Complete Register (RCR) .................. 372
Reception Flowchart
Reception Flowchart of the CAN Controller ....... 392
Reception Interrupt Enable Register
Reception Interrupt Enable Register (RIER) ....... 375
Recommended Setting
Recommended Setting ...................................... 132
Register
16-bit I/O Timer Registers................................. 176
16-bit Reload Timer Register............................. 200
16-bit Timer Register (TMR)/16-bit Reload Register
(TMRLR) ........................................... 204
32-bit Register Indirect Specification ................... 29
8/16-bit PPG Registers...................................... 215
A/D Control Status Register 1 (ADCS1)............. 253
A/D Converter Registers ................................... 249
A/D Data Registers 0/1
(ADCR0 and ADCR1) ......................... 256
Acceptance Mask Registers 0/1
(AMR0/AMR1) .................................. 378
Acceptance Mask Select Register (AMSR) ......... 376
Access to the Low-Power Mode Control
Register ................................................ 93
Analog Input Enable Register ............................ 247
Analog Input Enable Register (ADER) ............... 154
Automatic Ready Function Selection Register
(ARSR) .............................................. 135
Bit Timing Register (BTR)................................ 362
Block Diagram of Pull-up Control Register
(PUCR0 to PUCR3) ............................ 153
Bus Control Signal Selection Register
(ECSR) .............................................. 138
Clock Selection Register (CKSCR) ...................... 94
Common Register Bank Prefix (CMR) ................. 45
Condition Code Register (CCR)........................... 37
Control Register Settings for CLK Synchronous
Mode ................................................. 312
Control Status Register (CSR) ........................... 354
Control Status Register 0 (ADCS0) .................... 250
Control Status Register of Output Compare
(OCS0/OCS1) ..................................... 186
Data Register x (x = 0 to 15) (DTRx) ................. 384
Delayed Interrupt Cause Issuance/Cancellation
Register (DIRR) .................................. 233
DLC Register x (x = 0 to 15) (DLCRx) .............. 383
DTP/External Interrupt Cause Register (EIRR:
External Interrupt Request Register)...... 238
DTP/External Interrupt Enable Register (ENIR:
Interrupt Request Enable Register)........ 238
DTP/External Interrupts Registers...................... 237
EI2OS Status Register (ISCS) .............................. 70
External Address Output Control Register
(HACR) ............................................. 137
550
External Memory Access Registers.................... 134
Flash Memory Control Status Register
(FMCS) ............................................. 420
Flash Memory Register .................................... 416
General-purpose Registers .................................. 34
I/O Port Registers ............................................ 149
I/O Register Address Pointer (IOA) ..................... 70
ID Register x (x = 0 to 15) (IDRx) ..................... 381
IDE Register (IDER) ........................................ 365
Input Capture Control Status Register
(ICS01) .............................................. 193
Input Capture Data Register (IPCP0/1) .............. 193
Interrupt Control Register (ICR).......................... 66
Interrupt Level Mask Register (ILM) ................... 38
Last Event Indicator Register (LEIR) ................. 359
List of Message Buffers (Data Registers) ........... 351
List of Message Buffers (DLC Registers and Data
Registers) ........................................... 349
List of Message Buffers (ID Registers) .............. 346
List of Overall Control Registers ....................... 344
Low Power Mode Control Register...................... 91
Low Power Mode Control Register (LPMCR) ...... 92
Message Buffer Control Registers ..................... 353
Message Buffer Valid Register (BVALR) .......... 364
Output Compare Register (OCCP0,OCCP1) ....... 185
Overall Control Registers ................................. 353
Port Data Register (PDR0 to PDRA)
(for Port 0 to Port A) ........................... 150
Port Direction Register (DDR0 to DDRA)
(for Port 0 to Port A) ........................... 151
PPG Unit 0 Clock Selection Register
(PPG01) ............................................. 221
PPG0 Operation Mode Control Register
(PPGC0) ............................................ 216
PPG1 Operation Mode Control Register
(PPGC1) ............................................ 218
Program Address Detection Control Status Register
(PACSR)............................................ 405
Program Address Detection Registers
(PADR0 and PADR1) ......................... 405
Pull-up Control Register (PUCR0 to PUCR3)
(for Port 0 to Port 3) ............................ 152
Rate and Data Register 0 (URD0)...................... 278
Receive Overrun Register (ROVRR) ................. 374
Reception Complete Register (RCR).................. 372
Reception Interrupt Enable Register (RIER) ....... 375
Register Bank .................................................... 41
Register Bank Pointer (RP) ................................. 38
Register Saving onto the Stack ............................ 56
Registers not Initialized by Reset Input ................ 81
Reload Register (PRLL/PRLH) ......................... 223
Remote Frame Receiving Wait Register
(RFWTR)........................................... 368
Remote Request Receiving Register
(RRTRR) ........................................... 373
Request Level Setting Register
(ELVR: External Level Register).......... 239
INDEX
ROM Mirroring Function Selection Register
(ROMM)............................................ 413
Sample of a Output Waveform with Two Compare
Registers
(The Initial Output Value is "0".) .......... 190
Sample of Output Waveform when Compare Registers
0 and 1 are Used
(The Initial Output Value is "0".) .......... 189
Serial Control Register 1 (SCR1)....................... 301
Serial Input Data Register 0 (UIDR0) and Serial
Output Data Register 0 (UODR0) ......... 277
Serial Input Data Register 1 (SIDR1)/Serial Output
Data Register 1 (SODR1) .................... 303
Serial Mode Control Register 0 (UMC0) ............ 273
Serial Mode Control Status Register
(SMCS).............................................. 325
Serial Mode Register 1 (SMR1)......................... 299
Serial Shift Data Register (SDR) ....................... 329
Serial Status Register 0 (USR0)......................... 275
Serial Status Register 1 (SSR1) ......................... 304
Special Registers................................................ 33
Timebase Timer Control Register (TBTC).......... 158
Timebase Timer Registers................................. 156
Timer Control Status Register (TMCSR)............ 201
Timer Counter Control Status Register
(TCCS) .............................................. 179
Timer Counter Data Register (TCDT) ................ 178
Transmission Cancel Register (TCANR) ............ 369
Transmission Complete Register (TCR) ............. 370
Transmission Interrupt Enable Register
(TIER) ............................................... 371
Transmission Request Register (TREQR)........... 366
Transmission RTR Register (TRTRR) ............... 367
UART0 Registers............................................. 272
UART1 Communication Prescaler Control Register
(CDCR) ............................................. 306
UART1 Registers............................................. 298
Watch Timer Control Register (WTC) ............... 170
Watch Timer Register....................................... 168
Watch-dog Timer Control Register (WDTC) ...... 164
Watch-dog Timer Register ................................ 162
Register Bank
Common Register Bank Prefix (CMR)................. 45
Register Bank .................................................... 41
Register Bank Pointer
Register Bank Pointer (RP) ................................. 38
Register Saving onto the Stack
Register Saving onto the Stack ............................ 56
Relationship
Relationship Between 8/16-bit PPG Reload Value and
Pulse Width ........................................ 225
Release
Operation after Reset Release.............................. 80
Releasing Pseudo Timer Mode .......................... 107
Releasing Sleep Mode ...................................... 106
Releasing Stop Mode........................................ 109
Releasing Timer Mode ......................................108
Releasing Hardware Standby Mode
Releasing Hardware Standby Mode ....................111
Reload Register
16-bit Timer Register (TMR)/16-bit Reload Register
(TMRLR) ...........................................204
Reload Register (PRLL/PRLH)..........................223
Reload Timer
16-bit Reload Timer Register .............................200
Block Diagram of 16-bit Reload Timer ...............199
Input Pin Functions of 16-bit Reload Timer
(in Internal Clock Mode) ......................206
Internal Clock Operation
of 16-bit Reload Timer .........................205
Outline of 16-bit Reload Timer
(with Event Count Function).................198
Output Pin Functions of 16-bit Reload
Timer .................................................208
Pin Name of 16-bit Reload Timer.......................199
Underflow Operation of 16-bit Reload Timer ......207
Reload Value
Relationship Between 8/16-bit PPG Reload Value and
Pulse Width.........................................225
Remote Frame
Processing for Reception of Data Frame and Remote
Frame .................................................390
Remote Frame Receiving Wait Register
Remote Frame Receiving Wait Register
(RFWTR) ...........................................368
Remote Request Receiving Register
Remote Request Receiving Register
(RRTRR) ............................................373
Request Level Setting Register
Request Level Setting Register
(ELVR: External Level Register) ..........239
Request Register
DTP/External Interrupt Cause Register (EIRR:
External Interrupt Request Register) ......238
Required Time
Required Time to Start Interrupt Processing ..........60
Reset
Operation after Reset Release ..............................80
Registers not Initialized by Reset Input .................81
Reset Cause Occurrence ......................................79
Reset Causes ......................................................84
Resetting the Watch-dog Timer..........................166
Setting the Flash Memory to the Read/Reset
State ...................................................434
Reset Causes
Reset Causes ......................................................84
Reset Input
Registers not Initialized by Reset Input .................81
Restarting Erasing
Restarting Erasing of Flash Memory Sectors .......441
551
INDEX
Restrictions
Restrictions on Interrupt Disable Instructions and
Prefix Instructions ................................. 46
RFWTR
Remote Frame Receiving Wait Register
(RFWTR) ........................................... 368
RIER
Reception Interrupt Enable Register (RIER) ....... 375
ROM Mirroring Function Selection Module
Block Diagram of ROM Mirroring Function Selection
Module............................................... 412
ROM Mirroring Function Selection Register
ROM Mirroring Function Selection Register
(ROMM) ............................................ 413
ROMM
ROM Mirroring Function Selection Register
(ROMM) ............................................ 413
ROVRR
Receive Overrun Register (ROVRR).................. 374
RP
Register Bank Pointer (RP) ................................. 38
RRTRR
Remote Request Receiving Register
(RRTRR)............................................ 373
RTEC
Receive and Transmit Error Counters
(RTEC) .............................................. 361
S
Sample
Sample of a Output Waveform with Two Compare
Registers
(The Initial Output Value is "0".) .......... 190
Sample of Input Capture Fetch Timing ............... 195
Sample of Output Waveform when Compare Registers
0 and 1 are Used
(The Initial Output Value is "0".) .......... 189
SCDCR
Serial I/O Prescaler (SCDCR)............................ 330
SCR
Serial Control Register 1 (SCR1) ....................... 301
SDR
Serial Shift Data Register (SDR)........................ 329
Sector Configuration
Sector Configuration of the 1M/2M-bit
Flash Memory..................................... 417
Sector Erase Timer Flag
Sector Erase Timer Flag (DQ3) ......................... 430
Selecting a Count Clock
Selecting a Count Clock for 8/16-bit PPG ........... 226
Selection
Automatic Ready Function Selection Register
(ARSR) .............................................. 135
552
Block Diagram of ROM Mirroring Function Selection
Module .............................................. 412
Bus Control Signal Selection Register
(ECSR) .............................................. 138
Clock Selection Register (CKSCR)...................... 94
PPG Unit 0 Clock Selection Register
(PPG01) ............................................. 221
ROM Mirroring Function Selection Register
(ROMM)............................................ 413
Status Transition for Clock Selection ................... 97
UART1 Clock Selection ................................... 308
Serial Clock Input Frequency
Oscillation Clock Frequency and Serial Clock Input
Frequency .......................................... 453
Serial Control Register
Serial Control Register 1 (SCR1)....................... 301
Serial I/O
Interrupt Function of the Serial I/O Interface ...... 338
Serial I/O Block Diagram ................................. 322
Serial I/O Operation ................................. 331, 333
Serial I/O Prescaler (SCDCR) ........................... 330
Serial I/O Resisters .......................................... 324
Serial I/O Prescaler
Serial I/O Prescaler (SCDCR) ........................... 330
Serial I/O Resisters
Serial I/O Resisters .......................................... 324
Serial Input Data Register
Serial Input Data Register 0 (UIDR0) and Serial
Output Data Register 0 (UODR0) ......... 277
Serial Input Data Register 1 (SIDR1)/Serial Output
Data Register 1 (SODR1) .................... 303
Serial Mode Control Register
Serial Mode Control Register 0 (UMC0) ............ 273
Serial Mode Control Status Register
Serial Mode Control Status Register
(SMCS) ............................................. 325
Serial Mode Register
Serial Mode Register 1 (SMR1) ........................ 299
Serial Output Data Register
Serial Input Data Register 0 (UIDR0) and Serial
Output Data Register 0 (UODR0) ......... 277
Serial Input Data Register 1 (SIDR1)/Serial Output
Data Register 1 (SODR1) .................... 303
Serial Programming Connection
Example of Serial Programming Connection (Power
Supplied from the Programmer) ........... 456
Example of Serial Programming Connection
(User Power Supply Used)................... 454
Serial Shift Data Register
Serial Shift Data Register (SDR) ....................... 329
Serial Status Register
Serial Status Register 0 (USR0)......................... 275
Serial Status Register 1 (SSR1) ......................... 304
INDEX
Set Timings
Set Timings of the Six Flags ............................. 287
Setting
Conditions for Setting Bus Operation Stop
(HALT=1).......................................... 357
Recommended Setting...................................... 132
Request Level Setting Register
(ELVR: External Level Register).......... 239
Setting the Flash Memory to the Read/Reset
State .................................................. 434
Setting Acceptance Filter
Setting Acceptance Filter .................................. 393
Setting Bit Timing
Setting Bit Timing............................................ 393
Setting Configuration
Setting Configuration of Multi-level Message
Buffer ................................................ 399
Setting Frame Format
Setting Frame Format ....................................... 393
Setting ID
Setting ID........................................................ 393
Setting Low-Power Consumption Mode
Setting Low-Power Consumption Mode ............. 394
Setting Operation Clock
Setting Operation Clock for Watch-dog
Timer................................................. 172
Shift
External Shift Clock Mode................................ 332
Internal Shift Clock Mode................................. 332
Serial Shift Data Register (SDR) ....................... 329
Shift Operation Start/Stop Timing ..................... 335
Shift Operation
Shift Operation Start/Stop Timing ..................... 335
SIDR
Serial Input Data Register 1 (SIDR1)/Serial Output
Data Register 1 (SODR1) .................... 303
Single Mode
Example of Starting EI2OS in Single Mode ........ 261
Single Mode .................................................... 258
Six Flags
Set Timings of the Six Flags ............................. 287
Sleep
Releasing Sleep Mode ...................................... 106
Transition to Sleep Mode.................................. 106
Sleep Mode
Releasing Sleep Mode ...................................... 106
Transition to Sleep Mode.................................. 106
SMCS
Serial Mode Control Status Register
(SMCS).............................................. 325
SMR
Serial Mode Register 1 (SMR1)......................... 299
SODR
Serial Input Data Register 1 (SIDR1)/Serial Output
Data Register 1 (SODR1) .....................303
Software
Note on Software Interrupt ..................................63
Software Interrupt Operation ...............................62
Software Interrupts .............................................62
Structure of Software Interrupts ...........................62
Software Interrupt
Note on Software Interrupt ..................................63
Software Interrupt Operation ...............................62
Software Interrupts .............................................62
Structure of Software Interrupts ...........................62
Special Registers
Special Registers ................................................33
SSP
User Stack Pointer (USP) and System Stack Pointer
(SSP)....................................................36
SSR
Serial Status Register 1 (SSR1) ..........................304
Start Interrupt Processing
Required Time to Start Interrupt Processing ..........60
Start of Communication
Start of Communication in CLK Synchronous
Mode..................................................313
Start/Stop
Shift Operation Start/Stop Timing ......................335
Starting Transmission
Starting Transmission of the CAN Controller ......386
Start-Stop Synchronized
Asynchronous (Start-Stop Synchronized) Mode
Receive Operation ...............................311
Asynchronous (Start-Stop Synchronized) Mode
Transfer Data Format ...........................311
Asynchronous (Start-Stop Synchronized) Mode
Transmit Operation ..............................311
State
Counter Operation State ....................................209
Setting the Flash Memory to the Read/Reset
State ...................................................434
State During Bus Operation Stop (HALT=1) .......358
Status
A/D Control Status Register 1 (ADCS1) .............253
Control Status Register (CSR) ...........................354
Control Status Register 0 (ADCS0) ....................250
Control Status Register of Output Compare
(OCS0/OCS1) .....................................186
EI2OS Status Register (ISCS) ..............................70
Flash Memory Control Status Register
(FMCS) ..............................................420
Input Capture Control Status Register
(ICS01)...............................................193
Operation Status of Low-Power Consumption
Mode..................................................104
Processor Status (PS) ..........................................37
553
INDEX
Program Address Detection Control Status Register
(PACSR) ............................................ 405
Serial Mode Control Status Register
(SMCS) .............................................. 325
Serial Status Register 0 (USR0) ......................... 275
Serial Status Register 1 (SSR1).......................... 304
Status Transition Diagram for Low-Power
Consumption Mode
(Single Clock (System) Parts)............... 123
Status Transition Diagram for Low-Power
Consumption Mode
(Two Clocks System Parts) .................. 118
Status Transition for Clock Selection ................... 97
Timer Control Status Register (TMCSR) ............ 201
Timer Counter Control Status Register
(TCCS) .............................................. 179
Status Flag
Status Flag During Transmit
and Receive Operation ......................... 291
Status Transition
Status Transition for Clock Selection ................... 97
Status Transition Diagram
Status Transition Diagram for Low-Power
Consumption Mode
(Single Clock (System) Parts)............... 123
Status Transition Diagram for Low-Power
Consumption Mode
(Two Clocks System Parts) .................. 118
Stop
Conditions for Canceling Bus Operation Stop
(HALT=0) .......................................... 357
Conditions for Setting Bus Operation Stop
(HALT=1) .......................................... 357
Example of Starting EI2OS in Stop Mode ........... 265
Releasing Stop Mode ........................................ 109
State During Bus Operation Stop (HALT=1)....... 358
Stop Mode ....................................................... 259
Stopping the Watch-dog Counter ....................... 166
Transition to Stop Mode.................................... 109
Stop Mode
Example of Starting EI2OS in Stop Mode ........... 265
Releasing Stop Mode ........................................ 109
Stop Mode ....................................................... 259
Transition to Stop Mode.................................... 109
Storing Received Message
Storing Received Message ................................ 389
Structure
Structure of Extended Intelligent I/O Service
(EI2OS) ................................................ 65
Structure of Hardware Interrupt ........................... 55
Structure of Instruction Map.............................. 512
Structure of Software Interrupts ........................... 62
Suspending Erasing
Suspending Erasing of Flash Memory Sectors
.......................................................... 440
554
Switching
Switching Between External Interrupt and DTP
Requests ............................................ 242
Switching between Machine Clocks..................... 89
Synchronous Mode
CLK Synchronous Mode Transfer Data
Format ............................................... 312
Control Register Settings for CLK Synchronous
Mode ................................................. 312
End of Communication in CLK Synchronous
Mode ................................................. 313
Start of Communication in CLK Synchronous
Mode ................................................. 313
System Configuration
UART1 Sample Application
(System Configuration in Mode 1)........ 319
System Configuration Example
System Configuration Example of the Address Match
Detection Function.............................. 408
System Stack Pointer
User Stack Pointer (USP) and System Stack Pointer
(SSP) ................................................... 36
T
TBTC
Timebase Timer Control Register (TBTC) ......... 158
TCANR
Transmission Cancel Register (TCANR)............ 369
TCCS
Timer Counter Control Status Register
(TCCS) .............................................. 179
TCDT
Timer Counter Data Register (TCDT) ................ 178
TCR
Transmission Complete Register (TCR) ............. 370
TIER
Transmission Interrupt Enable Register
(TIER) ............................................... 371
Timebase Timer
Block Diagram of Timebase Timer .................... 157
Interval Interrupt Function of Timebase
Timer................................................. 160
Timebase Timer............................................... 160
Timebase Timer Control Register
Timebase Timer Control Register (TBTC) ......... 158
Timebase Timer Registers
Timebase Timer Registers ................................ 156
Timer Control Status Register
Timer Control Status Register (TMCSR)............ 201
Timer Counter Control Status Register
Timer Counter Control Status Register
(TCCS) .............................................. 179
Timer Counter Data Register
Timer Counter Data Register (TCDT) ................ 178
INDEX
Timer Mode
Releasing Timer Mode ..................................... 108
Transition to Timer Mode ................................. 108
Timing Limit Exceeded Flag
Timing Limit Exceeded Flag (DQ5)................... 429
TMCSR
Timer Control Status Register (TMCSR)............ 201
TMR
16-bit Timer Register (TMR)/16-bit Reload Register
(TMRLR)........................................... 204
TMRLR
16-bit Timer Register (TMR)/16-bit Reload Register
(TMRLR)........................................... 204
Toggle Bit 2 Flag
Toggle Bit 2 Flag (DQ2)................................... 431
Toggle Bit Flag
Toggle Bit Flag (DQ6) ..................................... 428
Transfer
Asynchronous (Start-Stop Synchronized) Mode
Transfer Data Format .......................... 311
CLK Synchronous Mode Transfer Data
Format ............................................... 312
Transfer Data Format ....................................... 285
Transfer Data Format
Asynchronous (Start-Stop Synchronized) Mode
Transfer Data Format .......................... 311
CLK Synchronous Mode Transfer Data
Format ............................................... 312
Transfer Data Format ....................................... 285
Transition
Transition to Hardware Standby Mode ............... 111
Transition to Pseudo Timer Mode...................... 107
Transition to Sleep Mode.................................. 106
Transition to Stop Mode ................................... 109
Transition to Timer Mode ................................. 108
Transition Conditions
Transition Conditions in Low-Power Consumption
Mode ................................................. 113
Transmission
Procedure for Transmission by Message Buffer
(x) ..................................................... 395
Transmission Cancel Register
Transmission Cancel Register (TCANR) ............ 369
Transmission Complete Register
Transmission Complete Register (TCR) ............. 370
Transmission Flowchart
Transmission Flowchart of the CAN
Controller........................................... 387
Transmission Interrupt Enable Register
Transmission Interrupt Enable Register
(TIER) ............................................... 371
Transmission Request Register
Transmission Request Register (TREQR)........... 366
Transmission RTR Register
Transmission RTR Register (TRTRR) ................367
Transmit and Receive Operation
Status Flag During Transmit
and Receive Operation .........................291
Transmit Operation
Asynchronous (Start-Stop Synchronized) Mode
Transmit Operation ..............................311
Flag Set Timings for a Transmit Operation..........290
TREQR
Transmission Request Register (TREQR) ...........366
TRTRR
Transmission RTR Register (TRTRR) ................367
Two Clocks System
Status Transition Diagram for Low-Power
Consumption Mode
(Two Clocks System Parts)...................118
U
UART0
Application Example of UART0 ........................292
Feature of UART0 ............................................270
UART0 Block Diagram.....................................271
UART0 Operation Modes..................................280
UART0 Registers .............................................272
UART0 Registers
UART0 Registers .............................................272
UART1
Features of UART1...........................................296
Precautions on UART1 Using ............................320
UART1 Block Diagram.....................................297
UART1 Clock Selection....................................308
UART1 Communication Flow Chart ..................319
UART1 Communication Prescaler Control Register
(CDCR) ..............................................306
UART1 Flags...................................................314
UART1 Interrupt Sources..................................314
UART1 Interrupts and Flag Set Timing ..............315
UART1 Operating Modes..................................307
UART1 Registers .............................................298
UART1 Sample Application
(System Configuration in Mode 1) ........319
UART1 Communication Prescaler Control Register
UART1 Communication Prescaler Control Register
(CDCR) ..............................................306
UART1 Registers
UART1 Registers .............................................298
UIDR
Serial Input Data Register 0 (UIDR0) and Serial
Output Data Register 0 (UODR0)..........277
UMC
Serial Mode Control Register 0 (UMC0).............273
555
INDEX
Undefined Instruction
Exception Due to Execution of an Undefined
Instruction ............................................ 76
Underflow Operation
Underflow Operation of 16-bit Reload Timer...... 207
UODR
Serial Input Data Register 0 (UIDR0) and Serial
Output Data Register 0 (UODR0) ......... 277
URD
Rate and Data Register 0 (URD0) ...................... 278
User Power Supply
Example of Minimum Connection to the Flash
Microcomputer Programmer
(User Power Supply Used) ................... 458
Example of Serial Programming Connection
(User Power Supply Used) ................... 454
User Stack Pointer
User Stack Pointer (USP) and System Stack Pointer
(SSP) ................................................... 36
USP
User Stack Pointer (USP) and System Stack Pointer
(SSP) ................................................... 36
USR
Serial Status Register 0 (USR0) ......................... 275
W
Watch Timer
Block Diagram of Watch Timer......................... 169
Interval Interrupt Function of Watch Timer......... 172
Watch Timer.................................................... 172
Watch Timer Control Register
Watch Timer Control Register (WTC)................ 170
Watch Timer Register
Watch Timer Register....................................... 168
556
Watch-dog Counter
Clearing the Watch-dog Counter ....................... 166
Stopping the Watch-dog Counter....................... 166
Watch-dog Timer
Activating the Watch-dog Timer ....................... 166
Resetting the Watch-dog Timer ......................... 166
Setting Operation Clock for Watch-dog
Timer................................................. 172
Watch-dog Timer Block Diagram...................... 163
Watch-dog Timer Control Register
Watch-dog Timer Control Register (WDTC) ...... 164
Watch-dog Timer Register
Watch-dog Timer Register ................................ 162
WDTC
Watch-dog Timer Control Register (WDTC) ...... 164
Writing Data
Writing Data to the Flash Memory..................... 435
Writing to the Flash Memory
Writing to the Flash Memory ............................ 435
Writing to the Input-Output Area
Hardware Interrupt Request During Writing to the
Input-Output Area................................. 55
Writing to/Erasing Flash Memory
Writing to/Erasing Flash Memory...................... 416
WTC
Watch Timer Control Register (WTC) ............... 170
X
x
Data Register x (x = 0 to 15) (DTRx)................. 384
DLC Register x (x = 0 to 15) (DLCRx) .............. 383
ID Register x (x = 0 to 15) (IDRx) ..................... 381
Procedure for Reception by Message Buffer
(x) ..................................................... 397
Procedure for Transmission by Message Buffer
(x) ..................................................... 395
CM44-10108-6E
FUJITSU MICROELECTRONICS • CONTROLLER MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90540/545 Series
HARDWARE MANUAL
July 2008 the sixth edition
Published
FUJITSU MICROELECTRONICS LIMITED
Edited
Business & Media Promotion Dept.