The following document contains information on Cypress products. CM44-10108-6ET2 Errata This errata sheet is for MB90540/545 Series Hardware Manual Rev.6 (CM44-10108-6E) F2MC-16LX 16-BIT MICROCONTROLLER MB90540/545 Series HARDWARE MANUAL 2009.1.14 ：Corrected part Updated 2009/ 1/14 Page 532 Item APPENDIX B Description ■Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH) is changed. ・Error Item "A" Line of +A "W2+d16,A" ・Correct Item "A0" Line of +A "@RW2+d16" 1/1 Corrections of Hardware Manual MB90540 hm90540-cm44-10108-6e-corr-x1-00 © Fujitsu Microelectronics Europe GmbH Addendum, MB90540 Hardware Manual (CM44-10108-6E) This is the Addendum for the Hardware Manual CM44-10108-6E microcontroller series. It describes all known discrepancies of the MB90540 microcontroller series Hardware Manual. Ref. Number Date Version Chapter/Page No. Description/Correction (Text Link) dd.mm.yy HWM90540001 27.02.04 1.00 Chapter 1.8 HWM90540002 27.02.04 1.00 HWM90540003 27.02.04 1.00 HWM90540004 27.02.04 1.00 Chapter Chapter Chapter HWM90540005 27.02.04 1.00 Chapter HWM90540006 29.04.08 1.00 Chapter hm90540-cm44-10108-6e-corr-x1-00.doc Info about power-on pin-state behaviour of MB90F54x, MB9054x added 11 Release from Watch Mode 1.8 Voltage drop down 14.3 PPG, wrong Bit setting for timebase timer Mode 21 CAN, ‘Hit and Away’ description added 14.3.2 Figure 14.3-3 corrected. PPG1 Operation Mode Control Register 1/8 HWM90540001 Chapter 1.8 Handling the Device TOP MB90F54X, MB9054X: power-on pin-state behaviour Conditions: Mode pins = 011 (single chip mode), RSTX and HSTX = 1 during power-on P00 to P37 = "X" (external bus) P46, P47 = "X" (Serial IO outputs) P76 to P84 = "X" (PPG, Output compare) all other ports "Z" P means Port, not pin. "X" can be anything (high, low, Z) Asserting RSTX instantly sets all ports to "Z", even if the oscillation didn't start yet. If RSTX is NOT the end of the (32ms for 4MHz starts and ALL asserted, the ports mentioned above remain "X" until power on reset time which is 2^17 oscillation cycles crystal). At the end of this time, the internal clock ports will be set to "Z". Fixed versions: MB90F543GS: Fixed After Date Code 0137-K02 MB90F546G/GS: Fixed After Date Code 0140-K28 MB90F548GS : Fixed After Date Code 0139-K01 MB90F548G : not affected MB90549G/GS : not affected MB90548G/GS : not affected MB90547G/GS : not affected hm90540-cm44-10108-6e-corr-x1-00.doc 2/8 Oscillation stabilization time Under “power-on reset” Vcc (power supply terminal) “power-on reset” signal RSTX (external asynchronous reset) signal RST (Internal reset) signal Program Execution MCLK (main clock) signal Internal operation clock signal Hi-z Output port 0, 1, 2, 3 output “unknown value” How to output “Hi-z” under “power-on reset” Input external reset over ２１７ x oscillation clock frequency RSTX (external asynchronous reset) signal Output port 0, 1, 2, 3 Hi Output port 0, 1, 2, 3 Timing chart Under “power-on reset” 217 x oscillation clock frequency (8.192ms in case of oscillation clock frequency = 16MHz) Waiting time to be stabilized oscillation 218 x oscillation clock frequency (16.384ms in case of oscillation clock frequency = 16MHz). hm90540-cm44-10108-6e-corr-x1-00.doc 3/8 HWM90540002 TOP Chapter 11: Watchmode --------Condition: Watch Mode Subclock connected(normal operation) or Watchmode, No subclock connected Description: If MCU has entered the Watch Mode and only the RST Reset signal is asserted, it could happen, that the CPU does not restart correctly. Workaround: RST and HST reset must be asserted simultaneously. Also a power-on reset will restart the CPU correctly again. HWM90540003 TOP Chapter 1.8 Handling the Device Voltage Drop down ----------------Condition: Voltage Drop on Vcc, No Subclock connected Description: If no subclock is connected, it possibly may happen, that after a voltage drop on Vcc, the MCU does not restart correctly, even if RST and HST is asserted simultaneously. Details: If a voltage drop on Vcc occurs, there is no power-on reset executed, if the voltage Vcc does not drop below under 0.2V for a certain time (toff), which is specified in the DS. See details on Vcc in the corresponding Datasheet. Normally, if HST & RST is asserted afterwards, the MCU would restart correctly. If no subclock is connected, it possibly may happen, that the CPU does not start/work correctly even after RST & HST reset. Workaround: a) The usage of a Subclock is highly recommended. If a Subclock is connected and a RST & HST Reset is asserted (RST = HST, reset simultaneously) the CPU will restart correctly. b) Perform a correct power-on Reset (corresponding to Vcc timing specified in Datasheet) c) Usage of: MB90F543GS*, MB90F546GS*, MB90F548GS*, MB90F549GS* *Note: GS version is a single clock version and therefore not affected. When using GS version: connect X0A to GND and leave X1A open. hm90540-cm44-10108-6e-corr-x1-00.doc 4/8 HWM90540004 TOP Chapter 14 8/16-BIT PPG Chapter 14.3.3 PPG0,1 Clock Selection Register (PPG0/1) Wrong Bit Settings for timebase timer mode. Correction: PCM2 1 PCM1 1 PCM0 1 Operation mode Clock input from the timebase timer (128us, 4MHz source) HWM90540005 TOP Chapter 21 CAN ‘Hit and Away’ description: Affected Parts: MB90V540/G, MB9054x/G/GS/DS, MB90F54x/G/GS/DS Caution for disabling Message Buffers by BVAL bits 1 Caution for Reception 1.1 Behaviour If there is a complete (no error until 6th bit of EOF) incoming message that have passed the acceptance filter, then this message is stored into a message buffer x (with x=0…15). If this store operation coincides with reset operation of the corresponding BVAL bit (BVALx=0), the received message will be stored into the message buffer 0 regardless of register settings. Note that this coincidence has to happen within a specific CAN-clock cycle (see event 2 in figures). Hence, the probability is very low. If transmission request of buffer 0 is set (TREQ0=1), the above-mentioned behaviour will lead to the following transmission of a message. This message consists of the received ID, DLC and Data together with original IDE and RTR bits set of the message buffer 0. However, if there are two or more message buffers with passing acceptance filers for the incoming message and only buffer x is disabled, the message will be stored into the 2nd prioritised message buffer. If there are two or more message buffers with passing acceptance filers for the incoming message and all those buffers are disabled, the message will be stored into buffer 0. 1.2 Operation to avoid When disabling message buffers by the BVAL register, it must be avoided that the write operation to the BVAL register coincides with the store operation of the received message in the CAN Controller. hm90540-cm44-10108-6e-corr-x1-00.doc 5/8 DLC Data dlc data Id-Arbitration CRC ACK ID RTR ID SRR IDE idle SOF The following diagram illustrates the timing to be avoided for the BVAL write operation. EOF ITM ID, DLC and DTR are copied to buffer 0 no RX-flags are set LEIR (buffer pointer) set to 0 determine one or more buffers with Hit 16 cycles 64 cycles 3 4 Away 1 Hit ACK DEL idle EOF6 EOF5 EOF4 EOF3 EOF2 EOF1 EOF0 SYNC_SEG TSEG1 TSEG2 sample point RS=1? 0 2 disable all buffers x to y with hit exactly one CAN-clock cycle after sample point (BVALx..y=0) c d e f CAN-controller determines buffers, which can store the message, because their acceptance filters had been passed. Software disable all buffers with hit exactly one CAN-clock cycle after the sample point of EOF1. CAN-controller stores received ID, DLC and data in buffer 0 regardless of the buffers determined in c. CAN-Controller sets LEIR to point to buffer 0 but RX-flags (RCR, ROVR, RRTRR) are not set. f 2. Caution for Transmission 2.1 Behaviour When there is a pending transmission of buffer x and the CAN bus status is in Intermission or in Bus Idle, the CAN-controller will load the message from buffer x in order to send it. If this load operation coincides with disabling the pending message buffer x by clearing the BVAL bit, this results in transmission of a Standard message. This message consists of RTR=0, IDE=0, DLC, 11 ID bits and Data stored in the message buffer 0. Note that this coincidence has to happen with in a specific CAN-clock cycle. Hence, the probability is very low. The position of that cycle depends also on previous frame reception and occurrence of error frames. 2.2 Operation to avoid When disabling message buffers by the BVAL register, it must be avoided that the write operation to the BVAL register coincides with the preparation for the next transmission in the CAN Controller. The following diagram illustrates the timing to be avoided for the BVAL write operation. hm90540-cm44-10108-6e-corr-x1-00.doc 6/8 DLC Data dlc data CRC ACK ID RTR ID SRR IDE SOF idle ... EOF ITM idle 5 Id-Arbitration TREQx=1 TREQx=1 6 EOF-SOF BVALx=0 BVALx=0 7 Hit 8 Away LEIR set to buffer 0 TCR remains unchanged transmit standard data frame with ID, DLC and data of buffer 0 g h i j Software requests transmission of buffer x by setting TREQx. Software disables the buffer x by clearing BVALx. CAN-controller transmits a standard data frame with ID, length code and data of buffer 0. After completion of frame only LEIR is updated for buffer 0. However, TCR is not set (neither for buffer 0 nor for buffer x). 3. Correct Operation 3.1 Operation for re-configuring receive message buffers Depending on CAN applications, it may be necessary to re-configure message buffers after receiving messages through the already active CAN communication. While the CAN bus is active, it is necessary to follow one of the two operations described below to re-configure message buffers by ID, AMS and AMR0/1 register settings. "Active" means that read value of the HALT bit is 0 and the CAN Controller is ready to receive and transmit messages. 1.1.1 Use of HALT bit Write 1 to the HALT bit and read it back for checking the result is 1. Then change settings for the ID/AMS/AMR0/1 registers. 1.1.2 No use of Message Buffer 0 Do not use the message buffer 0. In other words, disable message buffer (BVAL=0), prohibit receive interrupt (RIE=0) and do not request transmission (TREQ=0). 3.2 Operation for processing received message. When reading a received message from a message buffer, consideration must be given for possible over-write operation by next incoming messages. Disabling receive operation by the BVAL bit must not be used for this purpose. Use the ROVR bit for checking, if over-writing has been performed. For details, refer to description of ROVR in the hardware manual. hm90540-cm44-10108-6e-corr-x1-00.doc 7/8 3.3 Cancellation of transmission request Do not use the BVAL bit for suppressing/cancellation of transmission request. The TCANR bit is prepared for this purpose. 3.4 Composing transmission message When composing a transmission message by writing to ID, data and other registers, the message buffer should be disabled by the BVAL bit. In this case, the BVAL bit should reset (BVAL=0) after checking if the TREQ bit is 0 or after completion of the previous message transmission (TC=1). 4. Example of avoiding Hit-And-Away 1. Do not use message buffer 0. Keep it always disabled (BVAL0 = 0). By not using buffer 0 the processing of wrongly received messages in buffer 0 is avoided. Even if data are received in this buffer, they have no influence. 2. Set an unused 11-Bit identifier in buffer 0. "Unused" means that the identifier has no meaning to any node in the network. If an invalid standard data frame is sent according to the condition described in "0 2. Caution for Transmission", that frame must not cause misoperation of other nodes. 3. Use overrun test while processing a received message. After temporarily saving received message, test for overrun (ROVRR). If overrun occurred, read the buffer again, because the read data before overrun could be inconsistent. 4. Wait for completion of transmission. A buffer must not be disabled by clearing the BVAL-flag, as long as there is a pending transmission. Easiest way to wait for transmission completion is to use transmission interrupt but polling of TREQ is also possible. TOP HWM90540006 Chapter 14.3.2 PPG1 Operation Mode Control Register (PPGC1) Figure 14.3-3: Bit 9 of PPG1 Operation Mode Control Register (PPGC1) is wrong. Incorrect: Correct: MD0 hm90540-cm44-10108-6e-corr-x1-00.doc 8/8