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FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
CM44-10114-7E
F2MC-16LX
16-BIT MICROCONTROLLER
MB90495G Series
HARDWARE MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90495G Series
HARDWARE MANUAL
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system
development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU SEMICONDUCTOR LIMITED
MB90495G Series
PREFACE
■ Manual Objectives and Readers
The MB90495G series is one of the general-purpose products in the F2MC-16LX family of 16-bit single-chip
microcontrollers that is developed by using an application-specific integrated circuit (ASIC).
This manual covers the functions and operations of the MB90495G series for engineers to develop LSIs
using this series.
■ Trademarks
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
Other system and product names in this manual are trademarks of respective companies or organizations.
The symbols TM and ® are sometimes omitted in this manual.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU
SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you
develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use
of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the
information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of
the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's
intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any
infringement of the intellectual property rights or other rights of third parties which would result from the use of information
contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and
manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e.,
nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support
system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and
artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages
arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©2004-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved.
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HOW TO READ THIS MANUAL
■ Page Structure
Each section content can be read easily because it is mentioned within one page or double spread.
A summary under the title in each section outlines the section contents.
The top-level title at the top of a double spread indicates where you are reading without returning to the table
of contents or the chapter title page.
■ How to Find Information
To find information in each section, use the following index in addition to general table of contents and
index.
● Register index
This index helps you find the page containing the explanation of the corresponding register from a register
name or related resource name. You can also check the mapped addresses on memory and reset values.
● Pin function index
This index helps you find the page containing the explanation or block diagram of the corresponding pin
from a pin number, pin name, or related resource name. You can also check the circuit types.
● Interrupt vector index
This index helps you find the page containing the explanation of a corresponding interrupt from a name of
resource generating the interrupt or an interrupt number. You can also check the names and addresses of
interrupt control registers (ICRs), and the interrupt vector addresses.
■ Representation of Register Name and Bit Name
● Representation of register name and bit name
By writing 1 to the sleep bit of the standby control register (STBC: SLP), .......
Bit name
Register name
Abbreviation of bit name
Abbreviation of register name
Disable the time-based timer for output of an interrupt request (TBTC: TBIE = 0).
Set data
Abbreviation of bit name
Abbreviation of register name
If an interrupt is enabled (CCR: I = 1), an interrupt can be accepted.
Current state
Abbreviation of bit name
Abbreviation of register name
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CM44-10114-7E
MB90495G Series
● Representation of dual-purpose pin
P41/SCK1 pin
Some pins are dual-purpose pins which functions can be switched by the setting of program. A slosh (/)
separates and represents the names corresponding to the functions of the dual-purpose pins.
■ Register Representation
The F2MC-16LX family is a CPU with a 16-bit bus width. The bit position of each control register and data
register is given in 16 bits.
In 16-bit registers, bits 15 to 8 are allocated to odd addresses and bits 7 to 0 even addresses.
Even in 8-bit registers, the position of bits allocated to odd addresses is given in bits 15 to 8.
The F2MC-16LX family enables access to 8-bit data in order to increase the efficiency of programs. So, if
odd-address registers are accessed in 8 bits, bits 7 to 0 in data correspond to bits 15 to 8 in the manual
representation.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
CHAPTER 2
2.1
HANDLING DEVICES ................................................................................ 19
Precautions when Handling Devices ................................................................................................ 20
CHAPTER 3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
OVERVIEW ................................................................................................... 1
Features of MB90495G Series ........................................................................................................... 2
Product Lineup for MB90495G Series ................................................................................................ 5
Block Diagram of MB90495G Series .................................................................................................. 8
Pin Assignment ................................................................................................................................... 9
Package Dimension .......................................................................................................................... 11
Pin Description .................................................................................................................................. 13
I/O Circuit .......................................................................................................................................... 17
CPU ............................................................................................................ 25
Memory Space ..................................................................................................................................
Mapping of and Access to Memory Space ..................................................................................
Memory Map ................................................................................................................................
Addressing ...................................................................................................................................
Linear Addressing ........................................................................................................................
Bank Addressing .........................................................................................................................
Allocation of Multi-byte Data on Memory .....................................................................................
Dedicated Registers .........................................................................................................................
Dedicated Registers and General-purpose Register ...................................................................
Accumulator (A) ...........................................................................................................................
Stack Pointer (USP, SSP) ...........................................................................................................
Processor Status (PS) .................................................................................................................
Program Counter (PC) .................................................................................................................
Direct Page Register (DPR) ........................................................................................................
Bank Register (PCB, DTB, USB, SSB, and ADB) .......................................................................
General-purpose Register ................................................................................................................
Prefix Codes .....................................................................................................................................
Bank Select Prefix (PCB, DTB, ADB, and SPB) ..........................................................................
Common Register Bank Prefix (CMR) .........................................................................................
Flag Change Inhibit Prefix (NCC) ................................................................................................
Restrictions on Prefix Code .........................................................................................................
Interrupt ............................................................................................................................................
Interrupt Factor and Interrupt Vector ...........................................................................................
Interrupt Control Registers and Resources .................................................................................
Interrupt Control Register (ICR00 to ICR15) ...............................................................................
Function of Interrupt Control Register .........................................................................................
Hardware Interrupt .......................................................................................................................
Operation of Hardware Interrupt ..................................................................................................
Procedure for Use of Hardware Interrupt ....................................................................................
Multiple Interrupts ........................................................................................................................
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3.5.9
Software Interrupt ........................................................................................................................ 84
3.5.10 Interrupt by EI2OS ....................................................................................................................... 85
3.5.11 EI2OS Descriptor (ISD) ................................................................................................................ 87
3.5.12 Each Register of EI2OS Descriptor (ISD) .................................................................................... 89
3.5.13 Operation of EI2OS ...................................................................................................................... 92
3.5.14 Procedure for Use of EI2OS ........................................................................................................ 93
3.5.15 EI2OS Processing Time ............................................................................................................... 94
3.5.16 Exception Processing Interrupt .................................................................................................... 96
3.5.17 Time Required to Start Interrupt Processing ............................................................................... 97
3.5.18 Stack Operation for Interrupt Processing .................................................................................... 99
3.5.19 Program Example of Interrupt Processing ................................................................................. 100
3.6
Reset .............................................................................................................................................. 104
3.6.1
Reset Factors and Oscillation Stabilization Wait Time .............................................................. 106
3.6.2
External Reset Pin ..................................................................................................................... 108
3.6.3
Reset Operation ........................................................................................................................ 109
3.6.4
Reset Factor Bit ......................................................................................................................... 111
3.6.5
State of Each Pin at Reset ........................................................................................................ 113
3.7
Clocks ............................................................................................................................................. 114
3.7.1
Block Diagram of Clock Generation Section ............................................................................. 116
3.7.2
Register in Clock Generation Section ........................................................................................ 118
3.7.3
Clock Select Register (CKSCR) ................................................................................................ 119
3.7.4
Clock Mode ................................................................................................................................ 122
3.7.5
Oscillation Stabilization Wait Time ............................................................................................ 126
3.7.6
Connection of Oscillator and External Clock ............................................................................. 127
3.8
Low-power Consumption Mode ...................................................................................................... 128
3.8.1
Block Diagram of Low-power Consumption Circuit ................................................................... 131
3.8.2
Registers for Setting Low-power Consumption Modes ............................................................. 133
3.8.3
Low-power Consumption Mode Control Register (LPMCR) ...................................................... 134
3.8.4
CPU Intermittent Operation Mode ............................................................................................. 137
3.8.5
Standby Mode ........................................................................................................................... 138
3.8.6
State Transition in Standby Mode ............................................................................................. 149
3.8.7
Pin State in Standby Mode, at Reset ......................................................................................... 150
3.8.8
Precautions when Using Low-power Consumption Mode ......................................................... 153
3.9
CPU Mode ...................................................................................................................................... 156
3.9.1
Mode Pins (MD2 to MD0) .......................................................................................................... 158
3.9.2
Mode Data ................................................................................................................................. 160
3.9.3
Memory Access Mode ............................................................................................................... 162
3.9.4
Selection of Memory Access Mode ........................................................................................... 164
3.10 External Access .............................................................................................................................. 165
3.10.1 External Bus Pins ...................................................................................................................... 167
3.10.2 Registers used in External Access Mode .................................................................................. 170
3.10.3 Bus Control Signal Select Register (ECSR) .............................................................................. 171
3.10.4 Auto Ready Function Select Register (ARSR) .......................................................................... 173
3.10.5 High Address Control Register (HACR) .................................................................................... 175
3.10.6 Bus Sizing Function ................................................................................................................... 177
3.10.7 Ready Function ......................................................................................................................... 178
3.10.8 Hold Function ............................................................................................................................ 182
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3.10.9
External Access Timing ............................................................................................................. 184
CHAPTER 4
4.1
4.2
4.3
4.3.1
4.3.2
4.4
4.4.1
4.4.2
4.5
4.5.1
4.5.2
4.6
4.6.1
4.6.2
4.7
4.7.1
4.7.2
4.8
4.8.1
4.8.2
4.9
4.9.1
4.9.2
Overview of I/O Port .......................................................................................................................
Registers of I/O Port and Assignment of Pins Serving as External Bus .........................................
Port 0 ..............................................................................................................................................
Registers for Port 0 (PDR0, DDR0) ...........................................................................................
Operation of Port 0 ....................................................................................................................
Port 1 ..............................................................................................................................................
Registers for Port 1 (PDR1, DDR1) ...........................................................................................
Operation of Port 1 ....................................................................................................................
Port 2 ..............................................................................................................................................
Registers for Port 2 (PDR2, DDR2) ...........................................................................................
Operation of Port 2 ....................................................................................................................
Port 3 ..............................................................................................................................................
Registers for Port 3 (PDR3, DDR3) ...........................................................................................
Operation of Port 3 ....................................................................................................................
Port 4 ..............................................................................................................................................
Registers for Port 4 (PDR4, DDR4) ...........................................................................................
Operation of Port 4 ....................................................................................................................
Port 5 ..............................................................................................................................................
Registers for Port 5 (PDR5, DDR5, ADER) ...............................................................................
Operation of Port 5 ....................................................................................................................
Port 6 ..............................................................................................................................................
Registers for Port 6 (PDR6, DDR6) ...........................................................................................
Operation of Port 6 ....................................................................................................................
CHAPTER 5
5.1
5.2
5.3
5.3.1
5.4
5.5
5.6
5.7
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WATCHDOG TIMER ................................................................................ 247
Overview of Watchdog Timer .........................................................................................................
Configuration of Watchdog Timer ...................................................................................................
Watchdog Timer Registers .............................................................................................................
Watchdog Timer Control Register (WDTC) ...............................................................................
Explanation of Operation of Watchdog Timer .................................................................................
Precautions when Using Watchdog Timer ......................................................................................
Program Examples of Watchdog Timer ..........................................................................................
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TIMEBASE TIMER ................................................................................... 231
Overview of Timebase Timer ..........................................................................................................
Block Diagram of Timebase Timer .................................................................................................
Configuration of Timebase Timer ...................................................................................................
Timebase Timer Control Register (TBTC) .................................................................................
Timebase Timer Interrupt ...............................................................................................................
Explanation of Operation of Timebase Timer .................................................................................
Precautions when Using Timebase Timer ......................................................................................
Program Example of Timebase Timer ............................................................................................
CHAPTER 6
6.1
6.2
6.3
6.3.1
6.4
6.5
6.6
I/O PORT .................................................................................................. 187
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CHAPTER 7
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
7.5
7.6
7.7
7.8
Overview of 16-bit Input/Output Timer ............................................................................................
Block Diagram of 16-bit Input/Output Timer ...................................................................................
Block Diagram of 16-bit Free-run Timer ....................................................................................
Block Diagram of Input Capture ................................................................................................
Configuration of 16-bit Input/Output Timer .....................................................................................
Timer Counter Control Status Register (TCCS) (High) ..............................................................
Timer Counter Control Status Register (TCCS) (Low) ..............................................................
Timer Counter Data Register (TCDT) ........................................................................................
Input Capture Control Status Registers (ICS01 and ICS23) .....................................................
Input Capture Data Registers 0 to 3 (IPCP0 to IPCP3) .............................................................
Interrupts of 16-bit Input/Output Timer ............................................................................................
Explanation of Operation of 16-bit Free-run Timer .........................................................................
Explanation of Operation of Input Capture .....................................................................................
Precautions when Using 16-bit Input/Output Timer ........................................................................
Program Example of 16-bit Input/Output Timer ..............................................................................
CHAPTER 8
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.4
8.5
8.5.1
8.5.2
8.6
8.7
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16-BIT RELOAD TIMER ........................................................................... 285
Overview of 16-bit Reload Timer ....................................................................................................
Block Diagram of 16-bit Reload Timer ............................................................................................
Configuration of 16-bit Reload Timer ..............................................................................................
Timer Control Status Registers (High) (TMCSR0:H, TMCSR1:H) .............................................
Timer Control Status Registers (Low) (TMCSR0:L, TMCSR1:L) ..............................................
16-bit Timer Registers (TMR0, TMR1) ......................................................................................
16-bit Reload Registers (TMRLR0, TMRLR1) ...........................................................................
Interrupts of 16-bit Reload Timer ....................................................................................................
Explanation of Operation of 16-bit Reload Timer ............................................................................
Operation in Internal Clock Mode ..............................................................................................
Operation in Event Count Mode ................................................................................................
Precautions when Using 16-bit Reload Timer ................................................................................
Program Example of 16-bit Reload Timer ......................................................................................
CHAPTER 9
9.1
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9.3
9.3.1
9.4
9.5
9.6
16-BIT INPUT/OUTPUT TIMER ............................................................... 259
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WATCH TIMER ........................................................................................ 315
Overview of Watch Timer ...............................................................................................................
Block Diagram of Watch Timer .......................................................................................................
Configuration of Watch Timer .........................................................................................................
Watch Timer Control Register (WTC) ........................................................................................
Watch Timer Interrupt .....................................................................................................................
Explanation of Operation of Watch Timer .......................................................................................
Program Example of Watch Timer ..................................................................................................
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CHAPTER 10 8-/16-BIT PPG TIMER .............................................................................. 327
10.1 Overview of 8-/16-bit PPG Timer ....................................................................................................
10.2 Block Diagram of 8-/16-bit PPG Timer ...........................................................................................
10.2.1 Block Diagram for 8-/16-bit PPG Timer 0 ..................................................................................
10.2.2 Block Diagram of 8-/16-bit PPG Timer 1 ...................................................................................
10.3 Configuration of 8-/16-bit PPG Timer .............................................................................................
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10.3.1 PPG0 Operation Mode Control Register (PPGC0) ....................................................................
10.3.2 PPG1 Operation Mode Control Register (PPGC1) ....................................................................
10.3.3 PPG0/1 Count Clock Select Register (PPG01) .........................................................................
10.3.4 PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1) ..........................................................
10.4 Interrupts of 8-/16-bit PPG Timer ....................................................................................................
10.5 Explanation of Operation of 8-/16-bit PPG Timer ...........................................................................
10.5.1 8-bit PPG Output 2-channel Independent Operation Mode .......................................................
10.5.2 16-bit PPG Output Operation Mode ..........................................................................................
10.5.3 8+8-bit PPG Output Operation Mode ........................................................................................
10.6 Precautions when Using 8-/16-bit PPG Timer ................................................................................
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CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE .................................. 357
11.1 Overview of Delayed Interrupt Generation Module .........................................................................
11.2 Block Diagram of Delayed Interrupt Generation Module ................................................................
11.3 Configuration of Delayed Interrupt Generation Module ..................................................................
11.3.1 Delayed Interrupt Request Generate/Cancel Register (DIRR) ..................................................
11.4 Explanation of Operation of Delayed Interrupt Generation Module ................................................
11.5 Precautions when Using Delayed Interrupt Generation Module .....................................................
11.6 Program Example of Delayed Interrupt Generation Module ...........................................................
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CHAPTER 12 DTP/EXTERNAL INTERRUPT ................................................................. 365
12.1 Overview of DTP/External Interrupt ................................................................................................
12.2 Block Diagram of DTP/External Interrupt ........................................................................................
12.3 Configuration of DTP/External Interrupt ..........................................................................................
12.3.1 DTP/External Interrupt Factor Register (EIRR) .........................................................................
12.3.2 DTP/External Interrupt Enable Register (ENIR) ........................................................................
12.3.3 Detection Level Setting Register (ELVR) (High) ........................................................................
12.3.4 Detection Level Setting Register (ELVR) (Low) ........................................................................
12.4 Explanation of Operation of DTP/External Interrupt .......................................................................
12.4.1 External Interrupt Function ........................................................................................................
12.4.2 DTP Function .............................................................................................................................
12.5 Precautions when Using DTP/External Interrupt ............................................................................
12.6 Program Example of DTP/External Interrupt Function ...................................................................
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CHAPTER 13 8-/10-BIT A/D CONVERTER .................................................................... 385
13.1 Overview of 8-/10-bit A/D Converter ...............................................................................................
13.2 Block Diagram of 8-/10-bit A/D Converter ......................................................................................
13.3 Configuration of 8-/10-bit A/D Converter ........................................................................................
13.3.1 A/D Control Status Register (High) (ADCS:H) ...........................................................................
13.3.2 A/D Control Status Register (Low) (ADCS:L) ............................................................................
13.3.3 A/D Data Register (High) (ADCR:H) ..........................................................................................
13.3.4 A/D Data Register (Low) (ADCR:L) ...........................................................................................
13.3.5 Analog Input Enable Register (ADER) ......................................................................................
13.4 Interrupt of 8-/10-bit A/D Converter ................................................................................................
13.5 Explanation of Operation of 8-/10-bit A/D Converter ......................................................................
13.5.1 Single-shot Conversion Mode ...................................................................................................
13.5.2 Continuous Conversion Mode ...................................................................................................
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13.5.3 Pause-conversion Mode ............................................................................................................
13.5.4 Conversion Using EI2OS Function ............................................................................................
13.5.5 A/D-converted Data Protection Function ...................................................................................
13.6 Precautions when Using 8-/10-bit A/D Converter ...........................................................................
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CHAPTER 14 UART0 ...................................................................................................... 415
14.1 Overview of UART0 ........................................................................................................................
14.2 Block Diagram of UART0 ................................................................................................................
14.3 Configuration of UART0 ..................................................................................................................
14.3.1 Serial Control Register 0 (SCR0) ..............................................................................................
14.3.2 Serial Mode Register 0 (SMR0) .................................................................................................
14.3.3 Serial Status Register 0 (SSR0) ................................................................................................
14.3.4 Serial Input Data Register 0 (SIDR0) and Serial Output Data Register 0 (SODR0) ..................
14.3.5 Communication Prescaler Control Register 0 (CDCR0) ............................................................
14.3.6 Serial Edge Select Register 0 (SES0) .......................................................................................
14.4 Interrupt of UART0 ..........................................................................................................................
14.4.1 Generation of Receive Interrupt and Timing of Flag Set ...........................................................
14.4.2 Generation of Transmit Interrupt and Timing of Flag Set ..........................................................
14.5 Baud Rate of UART0 ......................................................................................................................
14.5.1 Baud Rate by Dedicated Baud Rate Generator ........................................................................
14.5.2 Baud Rate by Internal Timer 0 (16-bit Reload Timer) ................................................................
14.5.3 Baud Rate by External Clock .....................................................................................................
14.6 Operation of UART0 .......................................................................................................................
14.6.1 Operation in Asynchronous Mode (Operation Mode 0 or 1) ......................................................
14.6.2 Operation in Clock Synchronous Mode (Operation Mode 2) .....................................................
14.6.3 Bidirectional Communication Function (Operation Modes 0 and 2) ..........................................
14.6.4 Master/Slave Type Communication Function (Multiprocessor Mode) .......................................
14.7 Precautions when Using UART0 ....................................................................................................
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CHAPTER 15 UART1 ...................................................................................................... 461
15.1 Overview of UART1 ........................................................................................................................
15.2 Block Diagram of UART1 ................................................................................................................
15.3 Configuration of UART1 ..................................................................................................................
15.3.1 Serial Control Register 1 (SCR1) ..............................................................................................
15.3.2 Serial Mode Register 1 (SMR1) .................................................................................................
15.3.3 Serial Status Register 1 (SSR1) ................................................................................................
15.3.4 Serial Input Data Register 1 (SIDR1) and Serial Output Data Register 1 (SODR1) ..................
15.3.5 Communication Prescaler Control Register 1 (CDCR1) ............................................................
15.4 Interrupt of UART1 ..........................................................................................................................
15.4.1 Generation of Receive Interrupt and Timing of Flag Set ...........................................................
15.4.2 Generation of Transmit Interrupt and Timing of Flag Set ..........................................................
15.5 Baud Rate of UART1 ......................................................................................................................
15.5.1 Baud Rate by Dedicated Baud Rate Generator ........................................................................
15.5.2 Baud Rate by Internal Timer (16-bit Reload Timer) ...................................................................
15.5.3 Baud Rate by External Clock .....................................................................................................
15.6 Explanation of Operation of UART1 ...............................................................................................
15.6.1 Operation in Asynchronous Mode (Operation Mode 0 or 1) ......................................................
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15.6.2 Operation in Clock Synchronous Mode (Operation Mode 2) .....................................................
15.6.3 Bidirectional Communication Function (Operation Modes 0 and 2) ..........................................
15.6.4 Master/Slave Type Communication Function (Multiprocessor Mode) .......................................
15.7 Precautions when Using UART1 ....................................................................................................
15.8 Program Example for UART1 .........................................................................................................
498
501
503
506
507
CHAPTER 16 CAN CONTROLLER ................................................................................ 509
16.1 Overview of CAN Controller ............................................................................................................
16.2 Block Diagram of CAN Controller ...................................................................................................
16.3 Configuration of CAN Controller .....................................................................................................
16.3.1 Control Status Register (High) (CSR:H) ....................................................................................
16.3.2 Control Status Register (Low) (CSR:L) .....................................................................................
16.3.3 Last Event Indicate Register (LEIR) ..........................................................................................
16.3.4 Receive/Transmit Error Counter (RTEC) ...................................................................................
16.3.5 Bit Timing Register (BTR) ..........................................................................................................
16.3.6 Message Buffer Valid Register (BVALR) ...................................................................................
16.3.7 IDE Register (IDER) ..................................................................................................................
16.3.8 Transmission Request Register (TREQR) ................................................................................
16.3.9 Transmission RTR Register (TRTRR) .......................................................................................
16.3.10 Remote Frame Receiving Wait Register (RFWTR) ...................................................................
16.3.11 Transmission Cancel Register (TCANR) ...................................................................................
16.3.12 Transmission Complete Register (TCR) ....................................................................................
16.3.13 Transmission Complete Interrupt Enable Register (TIER) ........................................................
16.3.14 Reception Complete Register (RCR) ........................................................................................
16.3.15 Reception RTR Register (RRTRR) ............................................................................................
16.3.16 Reception Overrun Register (ROVRR) ......................................................................................
16.3.17 Reception Complete Interrupt Enable Register (RIER) .............................................................
16.3.18 Acceptance Mask Select Register (AMSR) ...............................................................................
16.3.19 Acceptance Mask Register (AMR) ............................................................................................
16.3.20 Message Buffers ........................................................................................................................
16.3.21 ID Register (IDRx, x = 7 to 0) ....................................................................................................
16.3.22 DLC Register (DLCR) ................................................................................................................
16.3.23 Data Register (DTR) ..................................................................................................................
16.4 Interrupts of CAN Controller ...........................................................................................................
16.5 Explanation of Operation of CAN Controller ...................................................................................
16.5.1 Transmission .............................................................................................................................
16.5.2 Reception ..................................................................................................................................
16.5.3 Procedures for Transmitting and Receiving ..............................................................................
16.5.4 Setting Multiple Message Receiving ..........................................................................................
16.6 Precautions when Using CAN Controller ........................................................................................
16.7 Program Example of CAN Controller ..............................................................................................
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511
515
519
521
524
526
528
532
534
536
538
540
542
544
546
548
550
552
554
556
558
560
561
564
565
566
568
569
572
576
583
585
586
xi
MB90495G Series
CHAPTER 17 8/16 ADDRESS MATCH DETECTION FUNCTION ................................. 589
17.1 Overview of Address Match Detection Function .............................................................................
17.2 Block Diagram of Address Match Detection Function ....................................................................
17.3 Configuration of Address Match Detection Function ......................................................................
17.3.1 Address Detection Control Register (PACSR) ..........................................................................
17.3.2 Detect Address Setting Registers (PADR0 and PADR1) ..........................................................
17.4 Explanation of Operation of Address Match Detection Function ....................................................
17.4.1 Example of using Address Match Detection Function ...............................................................
17.5 Program Example of Address Match Detection Function ...............................................................
590
591
592
593
595
597
598
603
CHAPTER 18 MIRRORING FUNCTION SELECT MODULE .......................................... 605
18.1
18.2
Overview of ROM Mirroring Function Select Module ...................................................................... 606
ROM Mirroring Function Select Register (ROMM) ......................................................................... 608
CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY ........................................................ 609
19.1 Overview of 512 Kbit/1 Mbit Flash Memory ....................................................................................
19.2 Registers and Sector Configuration of Flash Memory ....................................................................
19.3 Flash Memory Control Status Register (FMCS) .............................................................................
19.4 How to Start Automatic Algorithm of Flash Memory .......................................................................
19.5 Check the Execution State of Automatic Algorithm ........................................................................
19.5.1 Data Polling Flag (DQ7) ............................................................................................................
19.5.2 Toggle Bit Flag (DQ6) ................................................................................................................
19.5.3 Timing Limit Over Flag (DQ5) ....................................................................................................
19.5.4 Sector Erase Timer Flag (DQ3) .................................................................................................
19.6 Details of Programming/Erasing Flash Memory .............................................................................
19.6.1 Read/Reset State in Flash Memory ...........................................................................................
19.6.2 Data programming to flash memory ..........................................................................................
19.6.3 Data Erase from Flash Memory (Chip Erase) ...........................................................................
19.6.4 Erasing Any Data in Flash Memory (Sector Erasing) ................................................................
19.6.5 Sector Erase Suspension ..........................................................................................................
19.6.6 Sector Erase Resumption ..........................................................................................................
19.7 Sample Program for 512 Kbit Flash Memory ..................................................................................
610
611
612
615
617
619
621
622
623
624
625
626
628
629
631
632
633
CHAPTER 20 FLASH SERIAL PROGRAMMING CONNECTION ................................. 637
20.1
20.2
20.3
20.4
20.5
xii
Basic Configuration of Serial Programming Connection for F2MC-16LX MB90F497G/F498G ......
Connection Example in Single-chip Mode (User Power Supply) ....................................................
Connection Example in Single-chip Mode (Writer Power Supply) ..................................................
Example of Minimum Connection to Flash Microcontroller Programmer (User Power Supply) .....
Example of Minimum Connection to Flash Microcontroller Programmer (Writer Power Supply) ...
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643
645
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MB90495G Series
APPENDIX ......................................................................................................................... 649
APPENDIX A Instructions ...........................................................................................................................
A.1 Instruction Types ............................................................................................................................
A.2 Addressing .....................................................................................................................................
A.3 Direct Addressing ...........................................................................................................................
A.4 Indirect Addressing ........................................................................................................................
A.5 Execution Cycle Count ...................................................................................................................
A.6 Effective address field ....................................................................................................................
A.7 How to Read the Instruction List ....................................................................................................
A.8 F2MC-16LX Instruction List ............................................................................................................
A.9 Instruction Map ...............................................................................................................................
APPENDIX B Register Index ......................................................................................................................
APPENDIX C Pin Function Index ...............................................................................................................
APPENDIX D Interrupt Vector Index ..........................................................................................................
650
651
652
654
660
668
671
673
676
690
712
722
725
INDEX................................................................................................................................... 727
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MB90495G Series
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FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
MB90495G Series
Major changes in this edition
Page
9
Changes (For details, refer to main body.)
CHAPTER 1 OVERVIEW
1.4 Pin Assignment
10
Corrected Figure 1.4-1.
(P33/WRL → P33/WRH)
Changed package of LQFP-64.
(FPT-64P-M09 → FPT-64P-M23)
Corrected Figure 1.4-2.
(P34/FRQ → P34/HRQ)
12
13 to 16
17
1.5 Package Dimension
Changed package of LQFP-64.
(FPT-64P-M09 → FPT-64P-M23)
1.6 Pin Description
Changed "PIN No." of Table finding.
(M09 → M23)
1.7 I/O Circuit
Corrected the circuit of classification A of Table 1.7-1.
18
Corrected the circuit of classification F of Table 1.7-1.
23
CHAPTER 2
HANDLING DEVICES
2.1 Precautions when Handling
Devices
Added the following items.
("● Serial communication"
"● Characteristic difference among products with different memory size
and between flash memory product and mask ROM product")
176
CHAPTER 3 CPU
3.10.5 High Address Control
Register (HACR)
Added the note.
198
CHAPTER 4 I/O PORT
4.4 Port 1
Corrected Figure 4.4-1.
200
4.4.2 Operation of Port 1
Corrected "● Operation of resource output".
201
Added "● Reading value of the port data register (PDR)".
204
4.5 Port 2
Corrected Figure 4.5-1.
207
4.5.2 Operation of Port 2
Corrected "● Operation of resource output".
208
Added "● Reading value of the port data register (PDR)".
211
4.6 Port 3
Corrected Figure 4.6-1.
213
4.6.2 Operation of Port 3
Corrected "● Operation of resource output".
214
Added "● Reading value of the port data register (PDR)".
219
4.7.2 Operation of Port 4
Added "● Reading value of the port data register (PDR)".
223
4.8.1 Registers for Port 5
(PDR5, DDR5, ADER)
Corrected Table 4.8-3.
(an input port pin → an output port pin)
225
4.8.2 Operation of Port 5
Added "● Reading value of the port data register (PDR)".
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MB90495G Series
Page
270
CHAPTER 7 16-BIT
INPUT/OUTPUT TIMER
7.3 Configuration of 16-bit
Input/Output Timer
Added the note to bit 7 of Table 7.3-3.
299
CHAPTER 8 16-BIT RELOAD
TIMER
8.4 Interrupts of 16-bit Reload
Timer
Added the explanation to "■ Interrupts of 16-bit Reload Timer".
303
CHAPTER 8 16-BIT RELOAD
TIMER
8.5 Explanation of Operation of
16-bit Reload Timer
Added the explanation to the note in "■ Operation in Internal Clock
Mode".
273
274
305
Added the note to bit 6 of Table 7.3-4.
Added the note to bit 7 of Table 7.3-4.
Corrected the note in "■ Operation in Internal Clock Mode".
309
8.5.2 Operation in Event Count
Mode
Corrected the note in "■ Operation in Event Count Mode".
312
8.7 Program Example of 16-bit
Reload Timer
Corrected "● Coding example".
(#30D4H → #30D3H)
322
CHAPTER 9 WATCH TIMER
9.3.1 Watch Timer Control
Register (WTC)
Added the note to bit 4 of Table 9.3-1.
325
9.5 Explanation of Operation of
Watch Timer
Added the note.
388
CHAPTER 13 8-/10-BIT
A/D CONVERTER
13.2 Block Diagram of
8-/10-bit A/D Converter
Corrected the pin name in Table 13.2-1.
( VCC Input pin → A/D converter power supply pin
VSS Input pin → A/D converter analog GND pin)
398
CHAPTER 13 8-/10-BIT
A/D CONVERTER
13.3.3 A/D Data Register
(High) (ADCR:H)
Added the item to the note in bit 11/ bit 12 of Table 13.3-4.
471
CHAPTER 15 UART1
15.3.2 Serial Mode Register 1
(SMR1)
Corrected Figure 15.3-3.
617
CHAPTER 19 512 KBIT/
1 MBIT FLASH MEMORY
19.5 Check the Execution State
of Automatic Algorithm
Deleted "• Toggle bit 2 flag (DQ2)".
618
624
xvi
Changes (For details, refer to main body.)
Added the item to the note in bit 13/ bit 14 of Table 13.3-4.
Deleted column: Toggle bit 2 flag (DQ2) in Table 19.5-2.
Deleted "19.5.5 Toggle Bit 2 Flag (DQ2)".
626
19.6.2 Data programming to
flash memory
Added the item to "● Notes on data programming".
628
19.6.3 Data Erase from Flash
Memory (Chip Erase)
Added "■ Note on Chip Erase".
629
19.6.4 Erasing Any Data in
Flash Memory (Sector Erasing)
Added "■ Note on Sector Erase".
630
19.6.4 Erasing Any Data in
Flash Memory (Sector Erasing)
Corrected Figure 19.6-2.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
MB90495G Series
Page
Changes (For details, refer to main body.)
654
APPENDIX A Instructions
A.3 Direct Addressing
● Register direct addressing
Changed Table A.3-1.
( S flag bit → stack flag (S) )
656
A.3 Direct Addressing
● I/O direct addressing (io)
Changed Figure A.3-5.
(MOVW A, i : 0C0H → MOVW A, I:0C0H)
Added the note to Figure A.3-5.
657
A.3 Direct Addressing
● Abbreviated direct addressing (dir)
Added the note to Figure A.3-6.
658
A.3 Direct Addressing
● I/O direct bit addressing
(io:bp)
Changed Figure A.3-8.
(SETB i : 0C1H : 0 → SETB I:0C1H:0)
A.3 Direct Addressing
● Abbreviated direct bit
addressing (dir:bp)
Added the note to Figure A.3-9.
659
A.3 Direct Addressing
● Vector Addressing (#vct)
Corrected Table A.3-2.
Corrected the explanation of XX.
(Note: A PCB register value is set in XX. →
* : XX is replaced by the value of the program counter bank register
(PCB). )
664
A.4 Indirect Addressing
● Program counter relative
branch addressing (rel)
Changed Figure A.4-7.
(BRA 10H → BRA 3C32H)
665
A.4 Indirect Addressing
● Register list (rlst)
Changed Figure A.4-9.
(POPW, RW0, RW4 → POPW RW0, RW4)
676
A.8 F2MC-16LX Instruction
List
■ F2MC-16LX Instruction List
Corrected Table A.8-1.
Corrected the number of bytes (#) for "MOVX A, Ri" instruction.
(2 → 1)
A.9 Instruction Map
■ Structure of Instruction Map
Changed column: instruction in Table A.9-1.
(@RW2+d8, #8, rel → CBNE @RW2+d8, #8, rel)
691
692
Added the note to Figure A.3-8.
Changed the operand at row: +0, column: E0 in Table A.9-2.
(#4 → #vct4)
Changed the mnemonic at row: +0, column: D0 in Table A.9-2.
(MOV → MOVN)
Changed the mnemonic at row: +0, column: B0 in Table A.9-2.
(MOV → MOVX)
Changed the mnemonic at row: +8, column: B0 in Table A.9-2.
(MOV → MOVW)
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MB90495G Series
Page
694
695
Changes (For details, refer to main body.)
APPENDIX A Instructions
A.9 Instruction Map
■ Structure of Instruction Map
Changed the mnemonic at row: +0, column: E0 in Table A.9-4.
(FILSI → FILSWI)
Changed Table A.9-5.
(· Moved "MUL A" and "MULW A" instruction from column:60 to column:70.
· Changed mnemonic and moved the Instruction from column:60, row:+A
to column:70, row:+A.
(DIVU → DIV)
)
696
Changed the operand at row: +E and +F, column: F0 in Table A.9-6.
(,#8, rel → #8, rel)
699
Changed the operand at row: +8 to +E, column: 50 in Table A.9-9.
(@@ → @)
Changed the operand at row: +0 to +7, column: 20 in Table A.9-9.
(RWi → @RWi)
700
Changed the operand at column: E0 and F0 in Table A.9-10.
(,r → ,rel)
701
Changed the operand at column: 70 in Table A.9-11.
(NEG A, → NEG)
702
Changed the operand at column: E0 and F0 in Table A.9-12.
(,r → ,rel)
710
Changed Table A.9-20 XCH Ri, ea Instruction (First Byte = 7EH).
(Column "A" → Column "A0",
Changed row "+A" ( W2+d16,A → @RW2+d16 ))
722 to 724
APPENDIX C Pin Function
Index
Changed "PIN No." of Table C-1 finding.
(M09 → M23)
The vertical lines marked in the left side of the page show the changes.
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FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 1
OVERVIEW
This chapter describes the features and basic
specifications of the MB90495G series.
1.1 Features of MB90495G Series
1.2 Product Lineup for MB90495G Series
1.3 Block Diagram of MB90495G Series
1.4 Pin Assignment
1.5 Package Dimension
1.6 Pin Description
1.7 I/O Circuit
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 1 OVERVIEW
1.1 Features of MB90495G Series
1.1
MB90495G Series
Features of MB90495G Series
The MB90495G series is a general-purpose, high-performance 16-bit microcontroller
designed for control of processors such as consumer products requiring high-speed
real-time processing. This series has a full CAN interface and flash ROM.
The instruction system is based on the architecture of the F2MC family and provides
additional high-level language instructions, extended addressing modes, enhanced
multiply/divide instructions, and enriched bit processing instructions. A 32-bit
accumulator enables long-word data (32 bits) processing.
■ Features of MB90495G Series
● Clock
• Built-in PLL clock multiplying circuit
• Machine clock (PLL clock) selectable from 1/2 frequency of oscillation clock or 1 to 4-multiplied
oscillation clock (4 MHz to 16 MHz when oscillation clock is 4 MHz)
• Subclock operation (8.192 kHz)
• Minimum instruction execution time:
62.5 ns (4-MHz oscillation clock, 4-multiplied PLL clock, and
VCC = 5.0 V)
● 16-MB CPU memory space
• Internal 24-bit addressing
• External access by selection between 18-bit and 16-bit bus widths (external bus mode)
● Instruction system optimized for controllers
• Various data types (bit, byte, word, long word)
• 23 types of addressing modes
• Enhanced signed instructions of multiplication/division and RETI
• High-accuracy operations enhanced by 32-bit accumulator
● Instruction system for high-level language (C language)/multitask
• System stack pointer
• Enhanced pointer indirect instructions
• Barrel shift instructions
● Higher execution speed
• 4-byte instruction queue
● Powerful interrupt function
• Powerful interrupt function with 8 levels and 34 factors
2
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 1 OVERVIEW
1.1 Features of MB90495G Series
MB90495G Series
● CPU-independent automatic data transfer function
• Extended intelligent I/O service (EI2OS): Maximum 16 channels
● Lower-power consumption (standby) modes
• Sleep mode (stops CPU clock)
• Timebase timer mode (operates only oscillation clock and subclock, timebase timer and watch timer)
• Watch mode (operates only subclock and watch timer)
• Stop mode (stops oscillation clock and subclock)
• CPU Intermittent operation mode
● Process
• CMOS Technology
● I/O ports
• General-purpose I/O ports (CMOS output): 49
● Timers
• Timebase timer, watch timer, watchdog timer: 1 channel
• 8/16-bit PPG timer: 8 bits × 4 channels or 16 bits × 2 channels
• 16-bit reload timer: 2 channels
• 16-bit I/O timer
- 16-bit free-run timer: 1 channel
- 16-bit input capture (ICU): 4 channels
By detecting the edge of the pin input, the count value of the 16-bit free-run timer is latched to generate an
interrupt request.
● CAN Controller: 1 channel
• Conforms to CAN Specification Ver. 2.0A and Ver. 2.0B.
• Built-in 8 message buffers
• Transfer rate: 10 Kbps to 1 Mbps (at 16-MHz machine clock frequency)
● UART0 (SCI) and UART1 (SCI): 2 channels
• Full-duplex double buffer
• Clock asynchronous or clock synchronous serial transfer
● DTP/external interrupt: 8 channels
• External input to start EI2OS and external interrupt generation module
● Delayed interrupt generation module
• Generates interrupt request for task switching
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 1 OVERVIEW
1.1 Features of MB90495G Series
MB90495G Series
● 8-/10-bit A/D converter: 8 channels
• 8-bit and 10-bit resolutions
• Start by external trigger input
• Conversion time: 6.13μs (including sampling time at 16-MHz machine clock frequency)
● Program patch function
• Detects address match for two address pointers
● Clock output function
4
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 1 OVERVIEW
1.2 Product Lineup for MB90495G Series
MB90495G Series
1.2
Product Lineup for MB90495G Series
The MB90495G series is available in four types. This section provides the product
lineup, CPU, and resources.
■ Product Lineup for MB90495G Series
Table 1.2-1 Product Lineup for MB90495G Series
Classification
MB90V495G
MB90F497G
MB90497G
MB90F498G
Evaluation product
Flash ROM
Mask ROM
Flash ROM
ROM Size
--
RAM Size
6 KB
Process
Package
Power supply for emulator
128 KB
2 KB
CMOS
PGA256
Operating supply voltage
*
64 KB
LQFP-64 (with 0.65-mm pin pitch),
QFP-64 (with 1.00-mm pin pitch)
4.5 V to 5.5 V
Not provided
--
*: Setting of DIP Switch (S2) when using emulation pod (MB2145-507). For details, refer to the MB2145-507 Hardware
Manual (Section 2.7 Emulator-specific Power Supply).
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 1 OVERVIEW
1.2 Product Lineup for MB90495G Series
MB90495G Series
■ CPU and Resources for MB90495G Series
Table 1.2-2 CPU and Resources for MB90495G Series (1 / 2)
MB90V495G
CPU Function
MB90F497G
MB90497G
MB90F498G
Basic instruction count: 351
Instruction bit length: 8 or 16 bits
Instruction length: 1 to 7 bytes
Data bit length: 1, 8, or 16 bits
Minimum instruction execution time: 62.5 ns (at 16-MHz machine clock frequency)
Interrupt processing time: 1.5 μs (at 16-MHz machine clock frequency)
Low-power consumption
(standby) modes
Sleep mode, timer mode, timebase timer mode, stop mode, CPU intermittent operation
mode
I/O Ports
General-purpose I/O ports (CMOS output): 49
Timebase timer
18-bit free-run counter
Interrupt cycle: 1.024, 4.096, 16.834, 131.072 ms
(at 4-MHz oscillation clock frequency)
Watchdog timer
Reset cycle: 3.58, 14.33, 57.23, 458.75 ms (at 4-MHz oscillation clock frequency)
16-bit I/O timers
6
16-bit freerun timer
Channel count: 1
Overflow interrupt
Input capture
Channel count: 4
Free-run timer values saved by pin input (rising edge, falling edge, both edges)
16-bit reload timer
Channel count: 2
Operation of 16-bit reload timer
Count clock cycle: 0.25μs, 0.5μs, 2.0μs (at 16-MHz machine clock frequency)
External event countable
Watch timer
15-bit free-run counter
Interrupt cycle: 31.25, 62.5, 12, 250, 500 ms, and 1.0 s, 2.0 s (at 8.192-kHz subclock
frequency)
8-/16-bit PPG timer
Channel count: 2 (operable with 8 bits x 2 channels)
PPG operable with 8 bits x 2 channels or 16 bits x 1 channel
Pulse waveform output at arbitrary cycle and duty
Count clock: 62.5 ns to 1μs (at 16-MHz machine clock frequency)
Module for generating delayed
interrupt generating module
Interrupt generation module for switching task
Used for Real-time OS
DTP/external interrupt
Input count: 8
Start on rising or falling edges and by High- or Low-level inputs
External interrupts or (EI2OS)
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 1 OVERVIEW
1.2 Product Lineup for MB90495G Series
MB90495G Series
Table 1.2-2 CPU and Resources for MB90495G Series (2 / 2)
MB90V495G
MB90F497G
MB90497G
MB90F498G
8-/10-bit A/D converter
Channel count: 8
Resolution: 10 or 8 bits
Conversion time: 6.13μs (including sampling time at 16-MHz machine clock
frequency)
Two or more continuous channels can be converted sequentially (up to 8 channels)
Single conversion mode: Selected channel converted once only
Continuous conversion mode: Selected channel converted continuously
Stop conversion mode: Selected channel converted and temporary stopped alternately
UART 0(SCI)
Channel count: 1
Clock synchronous transfer: 62.5 Kbps to 2 Mbps
Clock asynchronous transfer: 1,202 bps to 62,500 bps
Two-way serial communication function, master/slave-connected communication
UART 1(SCI)
Channel count: 2
Clock synchronous transfer: 62.5 Kbps to 2 Mbps
Clock asynchronous transfer: 9,615 bps to 500Kbps
Two-way serial communication function, master/slave-connected communication
CAN
Conforms to CAN Specification Ver. 2.0A and Ver. 2.0B
Transmit/receive message buffer: 8
Transfer bit rate: 10 Kbps to 1 Mbps (at 16-MHz machine clock)
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 1 OVERVIEW
1.3 Block Diagram of MB90495G Series
1.3
MB90495G Series
Block Diagram of MB90495G Series
Block diagram of the MB90495G series is shown in the figure below.
■ Block Diagram of MB90495G Series
Figure 1.3-1 Block Diagram of MB90495G Series
X0,X1
RST
X0A,X1A
Clock control circuit
CPU
F2MC-16LX core
Watch timer
16-bit free-run timer
Time-base timer
Input capture
(4 ch)
ROM/FLASH
Prescaler
SOT1
SCK1
SIN1
Internal data bus
RAM
16-bit PPG timer
(2 ch)
CAN
FRCK
IN0 to IN3
PPG0 to PPG3
RX
TX
UART1
DTP/external interrupt
INT0 to INT7
Prescaler
SOT0
SCK0
SIN0
UART0
16-bit reload timer
(2 ch)
AVcc
AVss
AN0 to AN7
AVR
8-/10-bit
A/D converter
(8 ch)
External bus
ADTG
8
FUJITSU SEMICONDUCTOR LIMITED
TIN0, TIN1
TOT0, TOT1
AD00 to AD15
A16 to A23
ALE
RD
WRL
WRH
HRQ
HAK
RDY
CLK
CM44-10114-7E
CHAPTER 1 OVERVIEW
1.4 Pin Assignment
MB90495G Series
1.4
Pin Assignment
Pin assignment of the MB90495G series is shown in the figure below.
■ Pin Assignment (FPT-64P-M06)
P30/SOT0/ALE
VSS
P27/INT7/A23
P26/INT6/A22
P25/INT5/A21
P24/INT4/A20
P23/TOT1/A19
P22/TIN1/A18
P21/TOT0/A17
P20/TIN0/A16
P17/PPG3/AD15
P16/PPG2/AD14
P15/PPG1/AD13
P14/PPG0/AD12
P13/IN3/AD11
P12/IN2/AD10
P11/IN1/AD09
P10/IN0/AD08
P07/AD07
Figure 1.4-1 Pin Assignment (FPT-64P-M06)
51
P31/SCK0/RD
P32/SIN0/WRL
P33/WRH
P34/HRQ
P35/HAK
VCC
C
P36/FRCK/RDY
P37/ADTG/CLK
P40/SIN1
P41/SCK1
P42/SOT1
P43/TX
42
33
32
52
QFP-64
58
26
FPT-64P-M06
64
20
1
10
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VSS
X1
X0
MD2
MD1
RST
19
MD0
P63/INT3
X1A
X0A
P60/INT0
AVSS
AVR
AVCC
P57/AN7
P56/AN6
P55/AN5
P54/AN4
P53/AN3
P52/AN2
P51/AN1
P50/AN0
P62/INT2
P61/INT1
P44/RX
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
9
CHAPTER 1 OVERVIEW
1.4 Pin Assignment
MB90495G Series
■ Pin Assignment (FPT-64-M23)
P27/INT7/A23
P26/INT6/A22
P25/INT5/A21
P24/INT4/A20
P23/TOT1/A19
P22/TIN1/A18
P21/TOT0/A17
P20/TIN0/A16
P17/PPG3/AD15
P16/PPG2/AD14
P15/PPG1/AD13
P14/PPG0/AD12
P13/IN3/AD11
P12/IN2/AD10
P11/IN1/AD09
P10/IN0/AD08
Figure 1.4-2 Pin Assignment (FPT-64P-M23)
48
VSS
P30/SOT0/ALE
P31/SCK0/RD
P32/SIN0/WRL
P33/WRH
P34/HRQ
P35/HAK
VCC
C
P36/FRCK/RDY
P37/ADTG/CLK
P40/SIN1
P41/SCK1
P42/SOT1
P43/TX
P44/RX
40
33
49
32
LQFP-64
57
24
FPT-64P-M23
64
17
1
8
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VSS
X1
X0
MD2
MD1
RST
MD0
P63/INT3
16
X1A
X0A
P60/INT0
AVSS
AVR
AVCC
P57/AN7
P56/AN6
P55/AN5
P54/AN4
P53/AN3
P52/AN2
P51/AN1
P50/AN0
P62/INT2
P61/INT1
10
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 1 OVERVIEW
1.5 Package Dimension
MB90495G Series
1.5
Package Dimension
The MB90495G series is available in two types of package.
The package dimensions below are for reference only. Contact Fujitsu for the nominal
package dimensions.
■ Package Dimension of FPT-64P-M06
64-pin plastic QFP
Lead pitch
1.00 mm
Package width ×
package length
14 × 20 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP64-14×20-1.00
(FPT-64P-M06)
64-pin plastic QFP
(FPT-64P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
24.70±0.40(.972±.016)
* 20.00±0.20(.787±.008)
51
0.17±0.06
(.007±.002)
33
32
52
18.70±0.40
(.736±.016)
Details of "A" part
*14.00±0.20
(.551±.008)
+0.35
3.00 –0.20
INDEX
+.014
.118 –.008
(Mounting height)
20
64
0~8°
1
19
1.00(.039)
0.42±0.08
(.017±.003)
0.20(.008)
+0.15
M
0.25 –0.20
1.20±0.20
(.047±.008)
+.006
.010 –.008
(Stand off)
"A"
0.10(.004)
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F64013S-c-5-7
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
11
CHAPTER 1 OVERVIEW
1.5 Package Dimension
MB90495G Series
■ Package Dimension of FPT-64P-M23
64-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
12.0 × 12.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.47 g
Code
(Reference)
P-LQFP64-12×12-0.65
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
*12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.006±.002)
33
49
32
0.10(.004)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0.25(.010)
INDEX
0~8°
64
17
1
0.65(.026)
C
0.32±0.05
(.013±.002)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
"A"
16
0.13(.005)
0.10±0.10
(.004±.004)
(Stand off)
M
2003-2010 FUJITSU SEMICONDUCTOR LIMITED F64034S-c-1-4
Dimensions in mm (inches).
Note: The values in parentheses are reference values
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
12
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 1 OVERVIEW
1.6 Pin Description
MB90495G Series
1.6
Pin Description
This section describes the I/O pins and their functions of the MB90495G series.
■ Pin Description
Table 1.6-1 Pin Description (1 / 4)
Pin No.
Pin Name
M06
M23
2
1
Circuit
Type
P61
General-purpose I/O port
D
INT1
External interrupt input pin. This pin should be set to "input port".
P62
3
4 to 11
Function
2
General-purpose I/O port
D
INT2
External interrupt input pin. This pin should be set to "input port".
P50 to P57
General-purpose I/O port
3 to 10
E
Analog input pin for A/D converter. These pins work when the analog
input is set to "enable."
AN0 to AN7
12
11
AVCC
--
VCC power input pin for A/D converter
13
12
AVR
--
Power (Vref+) input pin for A/D converter. The power supply should
not be input exceeding
14
13
AVSS
--
VSS power input pin for A/D converter
15
14
P60
General-purpose I/O port
D
INT0
External interrupt input pin. This pin should be set to "input port".
16
15
X0A
A
Low-speed oscillation pin. This pin should be pulled down when not
connected to the oscillator.
17
16
X1A
A
Low-speed oscillation pin. This pin should be left open when not
connected to the oscillator.
18
17
P63
General-purpose I/O port
D
INT3
External interrupt input pin. This pin should be set to "input port".
19
18
MD0
C
Input pin for selecting operation mode
20
19
RST
B
Input pin for external reset
21
20
MD1
C
Input pin for selecting operation mode
22
21
MD2
F
Input pin for selecting operation mode
23
22
X0
A
High-speed oscillation pin
24
23
X1
A
High-speed oscillation pin
25
24
VSS
--
Power (0 V) input pin
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 1 OVERVIEW
1.6 Pin Description
MB90495G Series
Table 1.6-1 Pin Description (2 / 4)
Pin No.
Pin Name
M06
M23
Circuit
Type
General-purpose I/O ports
These ports are enabled only in the single-chip mode.
P00 to P07
26 to 33
34 to 37
38 to 41
42
43
44
25 to 32
33 to 36
37 to 40
41
42
43
D
AD00 to
AD07
External address and data bus lower 8-bit I/O pin. These pins are
enabled only in the external bus mode.
P10 to P13
General-purpose I/O ports. These ports are enabled only in the singlechip mode.
IN0 to IN3
D
Trigger input pins for input capture channels 0 to 3. These pins should
be set to "input port".
AD08 to
AD11
I/O pins for upper 4 bits of external address bus and data bus. These pins
are enabled only in the external bus mode.
P14 to P17
General-purpose I/O ports. These ports are enabled only in the singlechip mode.
PPG0 to PPG3
D
Output pins for PPG timers 01 and 23. These pins are enabled when the
output setting is "enabled."
AD12 to
AD15
I/O pins for upper 4 bits of external address bus and data bus. These pins
are enabled only in the external bus mode.
P20
General-purpose I/O port. If the corresponding bit of the high address
control register (HACR) is 1 in external bus mode, this pin functions as a
general-purpose I/O port.
TIN0
D
Event input pin for reload timer 0. This pin should be set to "input port."
A16
Output pin for external address bus (A16). In external bus mode, they
are only enabled if the corresponding bit of the high address control
register (HACR) is 0.
P21
General-purpose I/O port. If the corresponding bit of the high address
control register (HACR) is 1 in external bus mode, this pin functions as a
general-purpose I/O port.
TOT0
D
Event output pin for reload timer 0. This pin is enabled only when the
output setting is "enabled".
A17
Output pin for external address bus (A17). In external bus mode, they
are only enabled if the corresponding bit of the high address control
register (HACR) is 0.
P22
General-purpose I/O port. If the corresponding bit of the high address
control register (HACR) is 1 in external bus mode, this pin functions as a
general-purpose I/O port.
TIN1
A18
14
Function
D
Event input pin for reload timer 1. This pin should be set to "input port."
Output pin for external address bus (A18). In external bus mode, they
are only enabled if the corresponding bit of the high address control
register (HACR) is 0.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 1 OVERVIEW
1.6 Pin Description
MB90495G Series
Table 1.6-1 Pin Description (3 / 4)
Pin No.
Pin Name
M06
M23
Circuit
Type
General-purpose I/O port. If the corresponding bit of the high address
control register (HACR) is 1 in external bus mode, this pin functions as a
general-purpose I/O port.
P23
45
46 to 49
50
51
52
44
45 to 48
49
50
51
TOT1
D
54
Output pin for external address bus (A19). In external bus mode, they
are only enabled if the corresponding bit of the high address control
register (HACR) is 0.
P24 to P27
General-purpose I/O port. If the corresponding bit of the high address
control register (HACR) is 1 in external bus mode, these pins functions
as a general-purpose I/O port.
INT4 to INT7
D
Output pins for external address buses (A20 to A23). In external bus
mode, they are only enabled if the corresponding bit of the high address
control register (HACR) is 0.
VSS
Power (0 V) input pin.
P30
General-purpose I/O port. This port is enabled only the single-chip
mode.
SOT0
D
Serial data output pin for UART0. This pin is enabled only when the
serial data output setting of the UART0 is "enabled".
ALE
Address latch enable output pin. This pin is enabled only in the external
bus mode.
P31
General-purpose I/O port. This port is enabled only in the single-chip
mode.
SCK0
D
Serial clock I/O pin for UART0. This pin functions only when the serial
clock I/O setting of the UART0 is "enabled".
RD
Read strobe output pin. This pin is enabled only in the external bus
mode.
P32
General-purpose I/O port.
52
Serial data input pin for UART0. This pin should be set to "input port".
D
WRL
Write strobe output pin for lower 8 bits of data bus. This pin is enabled
only in the external bus mode and when the WRL pin output is
"enabled".
P33
General-purpose I/O port.
53
D
P34
54
Write strobe output pin for higher 8 bits of data bus. This pin is enabled
only in the external bus mode, the 16-bit bus mode, and when the WRH
pin output is enabled.
General-purpose I/O port.
D
HRQ
CM44-10114-7E
External interrupt input pins. These pins should be set to "input port."
A20 to A23
WRH
55
Event output pin for reload timer 1. This pin is enabled only when the
output setting is "enabled".
A19
SIN0
53
Function
Hold request input pin. This pin functions only in the external bus mode
and when the hold input/output is "enabled".
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 1 OVERVIEW
1.6 Pin Description
MB90495G Series
Table 1.6-1 Pin Description (4 / 4)
Pin No.
Pin Name
M06
M23
Circuit
Type
P35
56
55
General-purpose I/O port.
D
HAK
Hold acknowledge output pin. This pin is enabled only in the external
bus mode and when the hold input/output is "enabled".
57
56
VCC
Power (5 V) input pin.
58
57
C
Capacity pin for stabilizing power supply. This pin should be connected
to a ceramic capacitor of approx. 0.1μF.
P36
General-purpose I/O port.
59
60
58
59
FRCK
D
External ready input pin. This pin is enabled only in the external bus
mode and when the external ready input is "enabled".
P37
General-purpose I/O port.
ADTG
D
60
General-purpose I/O port
D
SIN1
Serial data input pin for UART1. This pin should be set to "input port."
P41
62
61
General-purpose I/O port.
D
SCK1
P42
63
62
P43
63
P44
64
Serial data I/O pin for UART1. This pin functions only when the serial
data I/O setting of the UART1 is "enabled".
General-purpose I/O port.
D
TX
1
Serial data input pin for UART1. This pin is enabled only when the
serial clock I/O setting of the UART1 is "enabled."
General-purpose I/O port.
D
SOT1
64
External trigger input pin for A/D converter. This pin should be set to
"input port".
External clock output pin. This pin is enabled only in the external bus
mode and when the external clock output is "enabled".
P40
61
External clock input pin for 16-bit free-run timer. This pin should be set
to "input port."
RDY
CLK
CAN transmission output pin. This pin is enabled only when the output
setting is "enabled".
General-purpose I/O port.
D
RX
16
Function
CAN reception input pin. This pin should be set to "input port."
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 1 OVERVIEW
1.7 I/O Circuit
MB90495G Series
1.7
I/O Circuit
I/O circuit of the MB90495G series is shown in the figure below.
■ I/O Circuit
Table 1.7-1 I/O Circuit (1 / 2)
Classification
A
Circuit
Remark
X1
Clock input
N-ch
X1A P-ch
X0
X0A
B
• Approximately 1 MΩ high speed
oscillation feedback resistor.
• Oscillation feedback resistor for low
speed approximately 10 MΩ
Standby mode control signal
Vcc
R
R
Hysteresis input
C
• Hysteresis input
R
Hysteresis input
D
• CMOS hysteresis input
• CMOS-level output
• Standby control provided
Vcc
P ch
R
N ch
Vss
Digital output
Digital output
Hysteresis input
IOL = 4 mA
E
Standby mode control
Vcc
P ch
R
IOL = 4 mA
N ch
Vss
Digital output
•
•
•
•
CMOS hysteresis input
CMOS-level output
Also used as analog input pin
Standby control provided
Digital output
Hysteresis input
Standby mode control
Analog input
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
17
CHAPTER 1 OVERVIEW
1.7 I/O Circuit
MB90495G Series
Table 1.7-1 I/O Circuit (2 / 2)
Classification
Circuit
F
R
Hysteresis input
R
Remark
• Hysteresis input with pull-down resistor.
• Pull-down Resistor : Approximately
50 kΩ approximately (except FLASH
device)
• No pull-down resistor in FLASH product
Vss
18
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 2
HANDLING DEVICES
This chapter describes the precautions when handling
general-purpose one chip micro-controller.
2.1 Precautions when Handling Devices
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
19
CHAPTER 2 HANDLING DEVICES
2.1 Precautions when Handling Devices
2.1
MB90495G Series
Precautions when Handling Devices
This section describes the precautions against the power supply voltage of the device
and processing of pin.
■ Precautions when Handling Devices
● Voltage not exceeding maximum ratings (preventing latch-up)
• For a CMOS IC, latch-up may occur when a voltage higher than VCC or a voltage lower than VSS is
impressed to the I/O pin other than medium-/high-voltage withstand I/O pins, or when a voltage that
exceeds the rated voltage is impressed between VCC and VSS.
• Latch-up may cause a sudden increase in supply current, resulting in thermal damage to the device.
Therefore, the maximum voltage ratings must not be exceeded.
• When turning the analog power supply on and off, the analog supply voltage (AVCC and AVR) and the
analog input voltage should not exceed the digital supply voltage (VCC).
● Handling not-used pins
If unused input pins remain open, a malfunction or latch-up may cause permanent damage, so take
countermeasures such as pull-up or pull-down using a 2 kΩ or larger resistor.
● Precautions of using external clock
When an external clock is used, drive only the X0 pin and open the X1 pin. Figure 2.1-1 shows an use
example of external clock.
Figure 2.1-1 Example of Using External Clock
X0
Open
X1
MB90495G series
● Precautions of non-use of subclock
If an oscillator is not connected to the X0A and X1A pins, connect the X0A pin to Pull-down resistor and
leave the X1A pin open.
● Precautions during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit
even when there is no external oscillator or external clock input is stopped. Performance of this operation,
however, cannot be guaranteed.
20
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 2 HANDLING DEVICES
2.1 Precautions when Handling Devices
MB90495G Series
● Power pins
• When plural VCC pins and VSS pins are provided, pins designed to be at the same electric potential are
internally connected to the device to prevent malfunctions such as latch-up. However, always connect
all same electric potential pins to power supply and ground outside the device to prevent decrease of
unnecessary radiation, the malfunction of the strobe signal due to a rise of ground level, and follow the
standards of total output current.
• The power pins should be connected to VCC and VSS of the MB90495G series device at the lowest
possible impedance from the current supply source.
• It is best to connect approximately 0.1μF capacitor between VCC and VSS as a bypass capacitor near the
pins of the MB90495G series device.
● Crystal oscillator circuit
• Noise near the X0 and X1 pins may cause the MB90495G series to malfunction. Design the PC board so
that the X0 and X1 pins, the crystal (or ceramic) oscillator, and the bypass capacitor to ground are as
close as possible to each other, and so the wiring of the X0 and X1 pins and other wiring do not cross.
• For stable operation, the PC board is recommended to have the artwork with the X0 and X1 pins
enclosed by a ground line.
● Procedure of A/D converter/analog input power-on
• Always apply a power to the A/D converter power and the analog input (AN0 to AN7 pins) after or
concurrently with the digital power (VCC)-on.
• Always turn off the A/D converter power and the analog input before or concurrently with the digital
power-down.
• Note that AVR should not exceed AVCC at turn on or off. (The analog power and digital power can be
simultaneously turned on or off with no problem.)
● Handling pins when not using A/D converter
When not using the A/D converter, the pins should be connected so that AVCC = AVR = VCC and AVSS =
VSS.
● Precautions at power on
To prevent a malfunction of the internal step-down circuit, the voltage rise time at power-on should be
50 μs or more (between 0.2 V and 2.7 V).
● Initialization
The device has internal registers that are initialized only by a power-on reset. When initializing the device,
the power supply should be turned off and turn on again.
● Stabilization of supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC
supply voltage operating range. Therefore, the VCC supply voltage should be stabilized.
For reference, the supply voltage should be controlled so that VCC ripple variations (peak-to-peak values)
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
21
CHAPTER 2 HANDLING DEVICES
2.1 Precautions when Handling Devices
MB90495G Series
at commercial frequencies (50 to 60 Hz) fall below 10% of the standard VCC supply voltage and the
coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
● Undefined signal output from ports 0 and 1
If the RST pin is High during the stabilization waiting time (power-on reset) of the step-down circuit after
the power is turned on, undefined signals are output from ports 0 and 1. If the RST pin is Low, ports 0 and
1 enter the high-impedance state. Figure 2.1-2 and Figure 2.1-3 show the timing of ports 0 and 1 producing
outputs and entering the high-impedance state, respectively.
Figure 2.1-2 Timing Chart for Ports 0 and 1 to Output Undefined Signals (RST Pin High)
Stabilization waiting time*2
Stabilization waiting
time of step-down circuit*1
VCC (Power supply pins)
PONR (Power-on reset) signal
RST (External asynchronous reset) signal
RST (Internal reset) signal
Oscillation clock signal
KA (Internal operation clock A) signal
KB (Internal operation clock B) signal
Undefined signal output period
PORT (Port output) signal
*1: Stabilization waiting time of step-down circuit
*2: Stabilization waiting time
22
217/oscillation clock frequency (about 8.19 ms at 16-MHz oscillation clock frequency)
18
2 /Oscillation clock frequency (about 16.38 ms at 16-MHz oscillation clock frequency)
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 2 HANDLING DEVICES
2.1 Precautions when Handling Devices
MB90495G Series
Figure 2.1-3 Timing Chart for Ports 0 and 1 to Enter High-impedance State (RST Pin Low)
Stabilization waiting time*2
Stabilization waiting
time of step-down circuit*1
VCC (Power supply pins)
PONR (Power-on reset) signal
RST (External asynchronous reset) signal
RST (Internal reset) signal
Oscillation clock signal
KA (Internal operation clock A) signal
KB (Internal operation clock B) signal
High impedance
PORT (Port output) signal
*1: Stabilization waiting time of step-down circuit
*2: Stabilization waiting time
17
/oscillation clock frequency (about 8.19 ms at 16-MHz oscillation clock frequency)
18
2 /Oscillation clock frequency (about 16.38 ms at 16-MHz oscillation clock frequency)
2
● Serial communication
In serial communication, reception of wrong data may occur due to noise or other causes. Therefore, design
a printed circuit board to prevent noise from occurring. Taking account of the reception of wrong data,
detect errors by measures such as adding a checksum to the end of data. If an error is detected, retransmit
the data.
● Characteristic difference among products with different memory size and between flash memory
product and mask ROM product
Among products with different memory size and between flash memory product and mask ROM product,
the electrical characteristic including the current consumption, ESD, latch-up, the noise characteristic, and
the oscillation characteristic, etc. is different because of their chip layout and memory structure. Reevaluate
the electrical specification when another product of the same series is replaced.
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
23
CHAPTER 2 HANDLING DEVICES
2.1 Precautions when Handling Devices
24
FUJITSU SEMICONDUCTOR LIMITED
MB90495G Series
CM44-10114-7E
CHAPTER 3
CPU
This chapter explains the CPU function of the MB90495G
series.
3.1 Memory Space
3.2 Dedicated Registers
3.3 General-purpose Register
3.4 Prefix Codes
3.5 Interrupt
3.6 Reset
3.7 Clocks
3.8 Low-power Consumption Mode
3.9 CPU Mode
3.10 External Access
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
25
CHAPTER 3 CPU
3.1 Memory Space
3.1
MB90495G Series
Memory Space
The memory space of the F2MC-16LX is 16 MB and is allocated to I/O, programs, and
data. Part of the memory space is used for specific uses such as the expansion
intelligent I/O service (EI2OS) descriptors, the general-purpose registers, and the vector
tables.
■ Memory Space
I/O, programs and data are all allocated somewhere in the 16-MB memory space of the F2MC-16LX CPU.
The CPU can indicate their addresses in the 24-bit address bus to access each resource.
Figure 3.1-1 shows an example of the relationships between the F2MC-16LX and the memory map.
Figure 3.1-1 Example of Relationships between F2MC-16LX System and Memory Map
F2MC-16LX Device
Generalpurpose port
Resource
Interrupt
2
F MC-16LX
CPU
Internal data bus
EI2OS
Data
000000 H
000020 H
0000B0 H
0000C0 H
000100 H
000180 H
000380 H
000D00 H*1
002000 H
004000 H
010000 H
100000 H
I/O port control register area
Resource control register area
I/O area
Interrupt control register area
External area
EI2OS
descriptor area
General-purpose register
RAM area
Data area
External area*3
ROM area
(image of FF bank)
External area*3
FF0000 H*2
Program area
Program
ROM area
FFFC00 H
Vector table area
FFFFFF H
*1: The capacity of the internal RAM depends on the device.
*2: The capacity of the internal ROM depends on the device.
*3: No access to this area in the single-chip mode
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CM44-10114-7E
CHAPTER 3 CPU
3.1 Memory Space
MB90495G Series
■ ROM Area
● Vector table area (address: "FFFC00H" to "FFFFFFH")
• The vector table is provided for reset and interrupts.
• This area is allocated at the top of the ROM area. The starting address of the corresponding processing
routine is set to the address of each vector table as data.
● Program area (address: to "FFFBFFH")
• ROM is contained as the internal program area.
• The capacity of the internal ROM depends on the product.
■ RAM Area
● Data area (address: "000100H" to "000900H")
• Static RAM is contained as the internal data area.
• The capacity of the internal RAM depends on the product.
● General-purpose register area (address: "000180H" to "00037FH")
• Auxiliary registers for operations or transfer of the 8-bit, 16-bit, or 32-bit data are allocated in this area.
• This area is allocated to part of the RAM area, and can also be used as ordinary RAM.
• When this area is used as general-purpose registers, they can be accessed quickly using a short
instruction through general-purpose register addressing.
● Expanded intelligent I/O service (EI2OS) descriptor area (address: "000100H" to "00017FH")
• This area holds the transfer mode, I/O address, transfer count, and buffer address.
• This area is allocated to part of the RAM area, and can also be used as ordinary RAM.
■ I/O Area
● Interrupt control register area (address: "0000B0H" to "0000BFH")
The interrupt control registers (ICR00 to ICR15) correspond to all resources with an interrupt function, and
control the setting of interrupt level and EI2OS.
● Resource control register area (address: "000020H" to "0000AFH")
This area controls the resource function and data I/O.
● I/O port control register area (address: "000000H" to "00001FH")
This area controls the I/O ports and data I/O.
■ External Area
• External RAM and ROM enable expansion of the data area and program area to an external area.
• This area is enabled in the external bus mode. The expandable area in the internal-ROM external-bus
mode is different from that in the external-ROM external-bus mode.
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CHAPTER 3 CPU
3.1 Memory Space
3.1.1
MB90495G Series
Mapping of and Access to Memory Space
In the MB90495G series, the single-chip mode, internal-ROM external-bus mode, and
external-ROM external-bus mode can be set as memory access modes.
■ Memory Map for MB90495G Series
In the MB90495G series, the internal address bus is output up to a width of 24 bits and the external address
bus is output up to a width of 24 bits; the external access memory can access up to the 16-MB memory
space.
Figure 3.1-2 shows the memory map when the ROM mirroring function is enabled and disabled.
Figure 3.1-2 Memory Map for MB90495G Series
000000H
0000C0H
000100H
Single-chip mode
(with ROM mirroring
function)
Internal-ROM
external bus mdoe
Resource
Resource
RAM area
Register
RAM area
Resource
Extend I/O area
Extend I/O area
RAM area
Register
Register
Adress#1
002000H
003800H
003900H
External-ROM
external bus mdoe
Extend I/O area
Adress#2
ROM area
ROM area
(image of FF bank)
(image of FF bank)
ROM area
ROM area
010000H
Adress#3
FFFFFFH
Device
Adress#1*
Adress#2
Adress#3*
MB90V495G
001900H
004000H
(FC0000H)
MB90F497G
000900H
004000H
FF0000H
MB90497G
000900H
004000H
FF0000H
MB90F498G
000900H
004000H
FE0000H
: Internal access memory
: External access memory
: Access disabled
*
28
: Address #1, #3 depend on the device.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 3 CPU
3.1 Memory Space
MB90495G Series
■ Image Access to Internal ROM
In the F2MC-16LX family, with the internal ROM in operation, ROM data in the FF bank can be seen as an
image in the top 00 bank. This function is called ROM mirroring and enables effective use of a small C
compiler.
In the F2MC-16LX family, the lower 16-bit addresses of the FF bank are the same as the lower 16-bit
addresses of the 00 bank, so the table in ROM can be referenced without specifying "far" with a pointer.
For example, if "00C000H" is accessed, data in ROM at "FFC000H" is actually accessed. However, the
ROM area in the FF bank exceeds 48 KB and all areas cannot be seen as images in the 00 bank. Therefore,
ROM data from "FF4000H" to "FFFFFFH" is see as an image from "004000H" to "00FFFFH" so the ROM
data table should be stored in the area from "FF4000H" to "FFFFFH".
To disable the ROM mirroring function (ROMM:MI=0), see Section "18.1 Overview of ROM Mirroring
Function Select Module".
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CHAPTER 3 CPU
3.1 Memory Space
3.1.2
MB90495G Series
Memory Map
The MB90495G series memory map is shown for each device.
■ Memory Map
Figure 3.1-3 shows the memory map for the MB90495G series.
Figure 3.1-3 Memory Map of MB90495G Series
MB90497G
000000H
0000C0H
000100H
single chip
internal ROM
external bus
external ROM
external bus
I/O
I/O
I/O
RAM
000900H
002000H
003800H
003900H
004000H
RAM
RAM
general-purpose
register
general-purpose
register
general-purpose
register
Extend I/O area
Extend I/O area
Extend I/O area
ROM area *2
(image of
FF bank)
MB90F497G
000000H
0000C0H
000100H
single chip
internal ROM
external bus
external ROM
external bus
I/O
I/O
I/O
RAM
RAM
RAM
general-purpose
register
general-purpose
register
general-purpose
register
Extend I/O area
Extend I/O area
Extend I/O area
ROM area *2
ROM area *2
ROM area *2
(image of
FF bank)
(image of
FF bank)
(image of
FF bank)
000900H
002000H
003800H
003900H
004000H
010000H
010000H
FE0000H
FE0000H
FF0000H
FF0000H
ROM
ROM
ROM
FFFFFFH
MB90F498G
000000H
0000C0H
000100H
single chip
internal ROM
external bus
external ROM
external bus
I/O
I/O
I/O
RAM
000900H
002000H
003800H
003900H
004000H
ROM
FFFFFFH
RAM
RAM
general-purpose
register
general-purpose
register
general-purpose
register
Extend I/O area
Extend I/O area
Extend I/O area
ROM area *2
ROM area *2
(image of
FF bank)
(image of
FF bank)
010000H
MB90V495G
000000H
0000C0H
000100H
001900H
002000H
003800H
003900H
004000H
single chip
internal ROM
external bus
external ROM
external bus
I/O
I/O
I/O
RAM
RAM
RAM
general-purpose
register
general-purpose
register
general-purpose
register
Extend I/O area
Extend I/O area
Extend I/O area
ROM area
ROM area
(image of
FF bank)
(image of
FF bank)
010000H
FE0000H
ROM
ROM
FFFFFFH
FC0000H
ROM*1
ROM*1
FFFFFFH
: Internal access memory
: External access memory
: Access disabled
*1 : The ROM is not built in the MB90V945G.
Only the dedicated development tool can be operated in the same way as the internal ROM products.
*2 : The area from "FF4000H" to "FFFFFFH" of MB90497G, MB90F497G, MB90F498G and MB90V495G
can be seen as image in the 00 bank.
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CM44-10114-7E
CHAPTER 3 CPU
3.1 Memory Space
MB90495G Series
3.1.3
Addressing
Linear and bank types are available for addressing.
The F2MC-16LX family uses basically bank addressing.
• Linear type: direct-addressing all 24 bits by instruction
• Bank type: addressing higher 8 bits by bank registers suitable for the use, and lower
16 bits by instruction
■ Linear Addressing and Bank Addressing
The linear addressing is to access the 16-MB memory space by direct-addressing. The bank addressing is to
access the 16-MB memory space which divided into 256 64-KB bank, by specifying banks and addresses in
banks.
Figure 3.1-4 shows overview of memory management in linear and bank type.
Figure 3.1-4 Memory Management in Linear and Bank Types
Linear addressing
000000 H
123456H
123456H
FFFFFF H
FD0000 H
FDFFFF H
FE0000 H
FEFFFF H
FF0000 H
FFFFFF H
123456H
Specified by instruction
CM44-10114-7E
Bank addressing
000000 H
00FFFF H
010000 H
01FFFF H
020000H
02FFFF H
00 bank
64 KB
01 bank
02 bank
12 bank
FD bank
FE bank
FF bank
123456 H
Specified by instruction
Specified by bank register
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 3 CPU
3.1 Memory Space
3.1.4
MB90495G Series
Linear Addressing
The linear addressing has the following two types:
• Direct-addressing 24 bits by instruction
• Using lower 24 bits of 32-bit general-purpose register for address
■ Linear Addressing by Specifying 24-bit Operand
Figure 3.1-5 Example of 24-bit Physical Direct Addressing in Linear Type
JMPP 123456H
Old program bank
+ program counter
10
452D
10452D H
New program bank
+ program counter
12
3456
123456 H
JMPP 123456H
Next instruction
■ Addressing by Indirect-specifying 32-bit Register
Figure 3.1-6 Example of indirect-specifying 32-bit General-purpose Register in Linear Type
MOV A,@RL1+7
Upper 8 bits ignored
Old AL
RL1
XXXX
FFFF06F9H
+7
New AL
003A
FF0700H
3AH
RL1 : 32-bit (long word) general-purpose register
32
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CM44-10114-7E
CHAPTER 3 CPU
3.1 Memory Space
MB90495G Series
3.1.5
Bank Addressing
The bank addressing is a type of addressing each of 254 64-KB banks into which the 16MB memory space is divided, using the bank register, and the lower 16 bits by an
instruction.
Bank register has the following five types depending on the use.
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional bank register (ADB)
■ Bank Registers and Access Space
Table 3.1-1 shows the access space for each bank register and the major use of it.
Table 3.1-1 Access Space for Each Bank Register and Major Use of Access Space
Bank Register Name
Access Space
Major Use
Reset Value
Program bank register
(PCB)
Program (PC)
space
Stores instruction code, vector
tables, immediate data.
FFH
Data bank register
(DTB)
Data (DT)
space
Stores data that can be read/written
and can access resource control
registers and data registers.
00H
User stack bank
register (USB)
System stack bank
register (SSB)*
Additional bank
register (ADB)
Stack (SP)
space
Additional
(AD) space
These are used for the stack
accessing such as the PUSH/POP
instruction and the register saving at
an interrupt. When the stack flag
(CCR:S) is 1, SSB is used. When the
stack flag is 0, USB is used*.
Stores data that cannot be stored in
data (DT) space.
00H
00H
00H
*: SSB is always used for the stack at an interrupt.
Figure 3.1-7 shows the relationships between the memory space divided into banks and each register.
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CHAPTER 3 CPU
3.1 Memory Space
MB90495G Series
Figure 3.1-7 Example of Bank Addressing
000000H
070000H
System stack space
07H
: SSB (System stack bank register)
Data space
0BH
: DTB (Data bank register)
User stack space
0DH
: USB (User stack bank register)
Additional space
0FH
: ADB (Additional bank register)
Program space
FFH
: PCB (Program bank register)
07FFFF H
Physical address
0B0000 H
0BFFFF H
0D0000 H
0DFFFF H
0F0000 H
0FFFFF H
FF0000 H
FFFFFF H
For details, see Section "3.2 Dedicated Registers".
■ Bank Addressing and Default Space
To improve the instruction code efficiency, the default space shown in Table 3.1-2 is determined for each
instruction in each addressing type. To use any bank space other than the default space, specify the prefix
code for that bank space before the instruction, which makes the arbitrary bank space corresponding to the
prefix code accessible.
Table 3.1-2 Addressing and Default Spaces
Default Spaces
Addressing
Program space
PC indirect addressing, program-access addressing, branch
instruction addressing
Data space
Addressing with @RW0, @RW1, @RW4, @RW5, @A, addr16,
and dir
Stack space
Addressing with PUSHW, POPW, @RW3, and @RW7
Additional space
Addressing with @RW2 and @RW6
For details of the prefix codes, see Section "3.4 Prefix Codes".
34
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CM44-10114-7E
CHAPTER 3 CPU
3.1 Memory Space
MB90495G Series
3.1.6
Allocation of Multi-byte Data on Memory
Multi-byte data is written to memory in sequence starting from the low address. For 32bit length data, the lower 16 bits are written first, and then the higher 16 bits are written.
If a reset signal is output immediately after the lower 16 bits is written, the higher data
may not be written.
■ Store of Multi-byte Data in RAM
Figure 3.1-8 shows the order in which multi-byte data is stored. Lower 8 bits are allocated to n address, and
in order of n+1, n+2 n+3 and . . ..
Figure 3.1-8 Storage of Multi-byte Data in RAM
Low address
Address n
00010100B
n+1
11111111B
n+2
n+3
11001100B
01010101B
MSB
High address
LSB
01010101B 11001100B 11111111B 00010100B
MSB: Most significant bit
LSB: Least significant bit
■ Storage of Multi-byte Length Operand
Figure 3.1-9 shows the configuration of a multi-byte length operand in memory.
Figure 3.1-9 Storage of Multi-byte Operand
JMPP 123456H
Low address
Address n
n+1
n+2
n+3
JMPP 1 2 3 4 5 6H
63H
56H
34H
12H
High address
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CHAPTER 3 CPU
3.1 Memory Space
MB90495G Series
■ Storage of Multi-byte Data in Stack
Figure 3.1-10 shows the order in which multi-byte data is stored in the stack.
Figure 3.1-10 Storage of Multi-byte Data in Stack
PUSHW RW1,RW3
Low address
PUSHW RW1,
RW3
(35A4H) (6DF0H)
A4H
35H
F0H
6DH
SP
High address
RW1: 35A4H
RW3: 6DF0H
*:
State of stack after execution of PUSHW instruction
■ Access to Multi-byte Data
All accesses are basically made inside the bank. Consequently, for an instruction that accesses multi-byte
data, the address after the "FFFFH" address is the "0000H" address of the same bank.
Figure 3.1-11 shows an example of access instruction for multi-byte data on the bank boundary.
Figure 3.1-11 Access to Multi-byte Data on Bank Boundary
Low address
AL before execution
800000H
:
:
80FFFFH
??
??
23H
01H
MOVW A, 080FFFFH
AL after execution
23H
01H
High address
36
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CM44-10114-7E
CHAPTER 3 CPU
3.2 Dedicated Registers
MB90495G Series
3.2
Dedicated Registers
The CPU has the following dedicated registers.
• Accumulator
• User stack pointer
• System stack pointer
• Processor status
• Program counter
• Direct page register
• Bank registers (program bank register, data bank register, user stack bank register,
system stack bank register, additional data bank register)
■ Configuration of Dedicated Registers
Figure 3.2-1 Configuration of Dedicated Registers
AH
AL
USP
: Accumulator (A)
The accumulator is two 16-bit registers, and is used to store operation results.
It can also be used as one 32-bit register.
: User stack pointer (USP)
This is a 16-bit pointer that indicates the user stack address.
SSP
: System stack pointer (SSP)
This is a 16-bit pointer that indicates the system stack address.
PS
: Processor status (PS)
PC
: Program counter (PC)
This is a 16-bit register that indicates the system status.
This is a 16-bit register that indicates the current instruction store location.
DPR : Direct page register (DPR)
This is an 8-bit register that sets bits 8 to 15 of 24 bits of addresses when using abbreviated direct page addressing.
PCB : Program bank register (PCB)
This is an 8-bit register that indicates the program space.
DTB : Data bank register (DTB)
This is an 8-bit register that indicates the data space.
USB : User stack bank register (USB)
This is an 8-bit register that indicates the user stack space.
SSB : System stack bank register (SSB)
This is an 8-bit register that indicates the system stack space.
ADB : Additional data bank register (ADB)
This is an 8-bit register that indicates the additional space.
8 bits
16 bits
32 bits
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CHAPTER 3 CPU
3.2 Dedicated Registers
MB90495G Series
Table 3.2-1 Reset Values of Dedicated Registers
Dedicated Register
Reset Value
Accumulator (A)
Undefined
User stack pointer (USP)
Undefined
System stack pointer (SSP)
Undefined
Processor status (PS)
PS
bit15 to bit13 bit12 to
bit8 bit7
to
bit0
CCR
RP
ILM
0 0 0 0 0 0 0 0
0 1 x x x x x
− : Unused
X : Undefined
Program counter (PC)
Value of reset vector (data at "FFFFDCH" and "FFFFDH")
01H
Direct page register (DPR)
Program bank register (PCB)
Value of reset vector (data at "FFFFDEH")
Data bank register (DTB)
00H
User stack bank register (USB)
00H
System stack bank register (SSB)
00H
Additional data bank register (ADB)
00H
Note:
38
The above reset values are the reset values for the device. The reset values for the ICE (such as emulator)
are different from those of the device.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 3 CPU
3.2 Dedicated Registers
MB90495G Series
3.2.1
Dedicated Registers and General-purpose Register
The F2MC-16LX family has two types of registers:
dedicated registers in the CPU and general-purpose register in the internal RAM.
■ Dedicated Registers and General-purpose Register
The dedicated registers are limited to the use in the hardware architecture of the CPU.
The general-purpose registers are in the internal RAM in the CPU address space. As with the dedicated
registers, these registers can be used for addressing and the use of these register is not limited.
Figure 3.2-2 shows the allocation of the dedicated registers and the general-purpose registers.
Figure 3.2-2 Dedicated Registers and General-purpose Register
CPU
Internal RAM
Dedicated register
General-purpose register
Accumulator
User stack pointer
Internal bus
System stack pointer
Processor status
Program counter
Direct page register
Program bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register
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CHAPTER 3 CPU
3.2 Dedicated Registers
3.2.2
MB90495G Series
Accumulator (A)
An accumulator (A) consists of two 16-bit length operation registers (AH and AL) used
for temporary storage of the operation result or data.
Accumulator can be used as a 32-, 16-, or 8-bit register. Various operations can be
performed between the register and memory or the other register, or between the AH
register and the AL register.
■ Accumulator (A)
● Data transfer to accumulator
The accumulator can process 32-bit data (long word), 16-bit data (word), and 8-bit data (byte).
• When processing 32-bit data, the AH register and the AL register are concatenated and used.
• When processing 16- or 8-bit data, only the AL register is used.
Data retention function
When data of word length or less is transferred to the AL register, data stored in the AL register is
transferred automatically to the AH register.
Code-extended function and zero-extended function
When transferring data of byte length or less to the AL register, the data is code-extended (MOVX
instruction) or zero-extended (MOVX instruction) to be the 16-bit length and stored in the AL register.
Data in the AL register can also be treated in word and byte lengths.
Figure 3.2-3 shows data transfer to the accumulator and a concrete example.
Figure 3.2-3 Data Transfer to Accumulator
32 bits
AH
AL
32-bit data transfer
Data transfer Data transfer
AH
16-bit data transfer
AL
Data saving
Data transfer
AH
8-bit data transfer
AL
Data saving
00H or FFH* Data transfer
(* : zero-extended or code-extended)
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CM44-10114-7E
CHAPTER 3 CPU
3.2 Dedicated Registers
MB90495G Series
● Byte processing arithmetic operation of accumulator
When the arithmetic operation instruction for byte processing is executed for the AL register, the higher 8
bits of the AL register in pre-operation are ignored, and the higher 8 bits of the operation result become all
0s.
● Reset value of accumulator
The reset value is undefined.
Figure 3.2-4 Example of 8-bit Data Transfer to Accumulator (A) (Data Saving)
MOVW A,3000H
(Instruction that stores the data at address "3000H" in the AL register.)
Memory space
MSB
Before execution
AH
AL
XXXXH
2456H
DTB
After execution
2456H
B53001 H
77H
LSB
B53000 H
88H
B5H
X
MSB
LSB
DTB
7788H
:
:
:
:
Undefined
Most Significant Bit
Least Significant Bit
Data bank register
Figure 3.2-5 Example of 8-bit Data Transfer to Accumulator (A) (Data Saving, Zero-extended)
(Instruction that zero-extends the data at address "3000H"
and stores the extended data in the AL register.)
MOV A,3000H
MSB Memory space
Before
execution
AH
AL
XXXXH
2456H
DTB
After
execution
CM44-10114-7E
2456H
0088H
B53001 H
77H
LSB
88H
B53000 H
B5H
X
MSB
LSB
DTB
:
:
:
:
Undefined
Most significant bit
Least significant bit
Data bank register
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 3 CPU
3.2 Dedicated Registers
MB90495G Series
Figure 3.2-6 Example of 16-bit Data Transfer to Accumulator (A) (Data Saving)
MOVW A,@RW1+6
Before
execution
AH
XXXXH
(Instruction that performs word length read using the result obtained
by adding the 8-bit length offset to data of RW1 as an address, and then
stores the read value in the A register.)
1234H
DTB
After
execution
1234H
Memory space
MSB
AL
A6H
RW1
15H
38H
A6153FH
A61541H
2BH
8FH
52H
74H
LSB
+6
2B52H
X
MSB
LSB
DTB
:
:
:
:
A6153EH
A61540H
Undefined
Most significant bit
Least significant bit
Data bank register
Figure 3.2-7 Example of 32-bit Data Transfer to Accumulator (A) (Register Indirect)
MOVL A,@RW1+6
Before
execution
AH
XXXXH
(Instruction that performs long-word length read using the result obtained
by adding the 8-bit length offset to data of RW1 as an address, and then
stores the read value in the A register.)
DTB
After
execution
8F74H
2B52H
A6H
RW1
15H
38H
A6153FH
A61541H
2BH
8FH
52H
74H
LSB
+6
X
MSB
LSB
DTB
42
Memory space
MSB
AL
XXXXH
:
:
:
:
A6153EH
A61540H
Undefined
Most significant bit
Least significant bit
Data bank register
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 3 CPU
3.2 Dedicated Registers
MB90495G Series
3.2.3
Stack Pointer (USP, SSP)
The stack pointers include a user stack pointer (USP) and a system stack pointer (SSP).
Both these pointers indicate the address where saved data and return data are stored
when the PUSH instruction, the POP instruction, and the subroutine is executed.
• The higher 8 bits of the stack address are set by the user stack bank register (USB) or
the system stack bank register (SSB).
• When the stack flag (PS:CCR:S) is 0, the USP and USB register are enabled. When the
stack flag is 1, the SSP and SSB register are enabled.
■ Stack Selection
For the F2MC-16LX family, two types of stack pointer can be used: system stack, and user stack.
The addresses of the stack pointers are set by the stack flag of the condition code register (CCR:S) as
shown in Table 3.2-2.
Table 3.2-2 Stack Address Specification
Stack Address
S Flag
Higher 8 Bits
Lower 16 Bits
0
User stack bank register (USB)
User stack pointer (USP)
1*
System stack bank register (SSB)
System stack pointer (SSP)
*: Reset value
Since the stack flag (CCR:S) is set to 1 by a reset, the system stack pointer is used after reset.
Ordinarily, the system stack pointer is used in processing the stack at the interrupt routine, and the user
stack pointer is used in processing the stack at other than interrupt routine. When it is necessary to divide
the stack space, use only the system stack pointer.
Note:
When an interrupt is accepted, the stack flag (CCR:S) is set and the system stack pointer is always used.
Figure 3.2-8 shows an example of the stack operation using the system stack.
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CHAPTER 3 CPU
3.2 Dedicated Registers
MB90495G Series
Figure 3.2-8 Stack Operation Instructions and Stack Pointers
PUSHW A when S flag = 0
Before
Execution
After
Execution
MSB
AL A624H
USB C6H
USP F328H
0
SSB 56H
SSP 1234H
AL A624H
USB C6H
USP F326H
S flag
SSB 56H
SSP 1234H
S flag
0
C6F327 H
LSB
XXH
C6F326 H
XXH
User stack pointer used
because S flag = 0
C6F327 H
A6H
24H
C6F326 H
PUSHW A when S flag = 1
MSB
Before
Execution
After
Execution
AL A624H
USB C6H
USP F328H
S flag
1
SSB 56H
SSP 1234H
AL A624H
USB C6H
USP F328H
S flag
SSB 56H
SSP 1232H
1
LSB
561233 H
XXH
XXH
561232 H
561233 H
A6H
24H
561232 H
System stack pointer used
because S flag = 1
X
: Undefined
MSB : Most significant bit
LSB : Least significant bit
Notes:
• Use even addresses for setting value to the stack pointer. Setting an odd address divides the word
access into two accesses, decreasing the efficiency.
• The reset values of the USP and SSP registers are undefined.
■ System Stack Pointer (SSP)
When using the system stack pointer (SSP), the stack flag (CCR:S) is set to 1. The higher 8 bits of the
address used in processing the stack are set by the system stack bank register (SSB).
■ User Stack Pointer (USP)
When using the user stack pointer (USP), the stack flag (CCR:S) is set to 0. The higher 8 bits of the address
used in processing the stack are set by the user stack bank register (USB).
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CHAPTER 3 CPU
3.2 Dedicated Registers
MB90495G Series
■ Stack Area
● Securing stack area
The stack area is used to save and return the program counter (PC) at execution of the interrupt processing,
subroutine call instruction (CALL) and vector call instruction (CALLV). It is also used to save and return
temporary registers using the PUSHW and POPW instructions.
The stack area is secured with the data area in RAM.
The stack area is as shown below:
Figure 3.2-9 Stack Area
000000 H
I/O area
0000C0 H
000100 H
000180 H
Generalpurpose
register bank
Stack area
000380 H
Internal RAM area
001100 H
~
~
FF0000 H
~
~
*
ROM area
Vector table
(reset, interrupt vector
call instruction)
FFFC00H
FFFFFFH
*: Internal ROM capacity depends on devices
Notes:
.
• As a general rule, even addresses should be set in the stack pointers (SSP and USP).
• The system stack area, user stack area, and data area should not overlap.
● System stack area and user stack area
The system stack area is used for interrupt processing. When an interrupt occurs, even if the user stack area
is used, it is switched forcibly to the system stack area. Therefore, in systems mainly using the user stack
area also, the system stack area must be set correctly.
In particular, only the system stack area should be used unless it is necessary to divide the stack space.
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CHAPTER 3 CPU
3.2 Dedicated Registers
3.2.4
MB90495G Series
Processor Status (PS)
The processor status (PS) consists of the bits controlling CPU and various bits
indicating the CPU status. The PS consists of the following three registers.
• Interrupt level mask register (ILM)
• Register bank pointer (RP)
• Condition code register (CCR)
■ Configuration of Processor Status (PS)
The processor status (PS) consists of bits controlling CPU and various bits indicating the CPU status.
Figure 3.2-10 shows the configuration of the processor status (PS).
Figure 3.2-10 Processor Status (PS)
RP
ILM
bit 15 14 13 12 11 10
PS
CCR
7
6
5
4
3
2
1 bit 0
ILM2 ILM1 ILM0 B4 B3 B2 B1 B0 ⎯
I
S
T
N
Z
V
C
⎯
0
1
X
X
X
X
X
Reset value 0
0
0
0
0
0
9
0
8
0
⎯ : Unused
X : Undefined
● interrupt level mask register (ILM)
This register indicates the level of the interrupt that the CPU is currently accepting. The value of this
register is compared to the value of the interrupt level setting bits of the interrupt control register (ICR:IL0
to IL2) corresponding to the interrupt request of each resource.
● Register bank pointer (RP)
This register set the memory block (register bank) to be used for the general-purpose registers allocated in
the internal RAM.
General-purpose registers can be set for up to 32 banks. The general-purpose register banks to be used are
set by setting 0 to 31 in the register bank pointer (RP).
● Condition code register (CCR)
This register consists of various flags that are set (1) or cleared (0) by instruction execution result or
acceptance of an interrupt.
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CHAPTER 3 CPU
3.2 Dedicated Registers
MB90495G Series
3.2.4.1
Condition Code Register (PS:CCR)
The condition code register (PS:CCR) is an 8-bit register consisting of bits indicating
the result of instruction execution, and the bits enabling or disabling the interrupt
request.
■ Configuration of Condition Code Register (CCR)
Figure 3.2-11 shows the configuration of the CCR register.
Figure 3.2-11 Configuration of Condition Code Register (CCR)
RP
ILM
bit 15 14 13 12 11 10
PS
CCR
7
6
5
4
3
2
1 bit 0 CCR reset value
ILM2 ILM1 ILM0 B4 B3 B2 B1 B0 ⎯
I
S
T
N
Z
V
C
⎯
0
1
X
X
X
X
X
0
⎯ : Unused
X : Undefined
0
0
0
0
0
9
0
8
0
-01XXXXXB
Interrupt enable flag
Stack flag
Sticky-bit flag
Negative flag
Zero flag
Overflow flag
Carry flag
● Interrupt enable flag (I)
All interrupts except software interrupts are enabled when the interrupt enable flag (CCR:I) is set to 1, and
are disabled when the interrupt enable flag is set to 0. This flag is cleared to 0 by a reset.
● Stack flag (S)
This flag sets the pointer for stack processing.
When the stack flag (CCR:S) is 0, the user stack pointer (USP) is enabled. When the stack flag is 1, the
system stack pointer (SSP) is enabled. If an interrupt is accepted or a reset occurs, the flag is set to 1.
● Sticky-bit flag (T)
If either one of the data shifted out of the carry is 1 when the logic right-shift instruction or arithmetic rightshift instruction is executed, this flag is set to 1. If all the shifted-out data is 0 or the shift amount is 0, this
flag is set to 0.
● Negative flag (N)
If the most significant bit (MSB) of the operation result is 1, this flag is set to 1. If the MSB is 0, the flag is
cleared to 0.
● Zero flag (Z)
If all the bits of the operation result are 0, this flag is set to 1. If any bit is 1, the flag is cleared to 0.
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CHAPTER 3 CPU
3.2 Dedicated Registers
MB90495G Series
● Overflow flag (V)
If an overflow occurs as a signed numeric value at the execution of operation, this flag is set to 1. If no
overflow occurs, the flag is cleared to 0.
● Carry flag (C)
If a carry from the MSB or to the least significant bit (LSB) occurs at the execution of operation, this flag is
set to 1. If no carry occurs, this flag is cleared to 0.
For the state of the condition code register (CCR) at instruction execution, refer to the Programming
Manual.
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CHAPTER 3 CPU
3.2 Dedicated Registers
MB90495G Series
3.2.4.2
Register Bank Pointer (PS:RP)
The register bank pointer (RP) is a 5-bit register that indicates the starting address of
the currently used general-purpose register bank.
■ Register Bank Pointer (RP)
Figure 3.2-12 shows the configuration of the register bank pointer (RP).
Figure 3.2-12 Configuration of Register Bank Pointer (RP)
ILM
RP
bit 15 14 13 12 11 10
PS
CCR
9
8
7
6
5
4
3
2
1 bit 0
ILM2 ILM1 ILM0 B4 B3 B2 B1 B0 ⎯
I
S
T
N
Z
V
C
RP reset value
00000B
■ General-purpose Register Area and Register Bank Pointer
The register bank pointer (RP) indicates the allocation of general-purpose registers used in the internal
RAM. The relationship between the values of PR and the actual addresses should conform to the
conversion rule shown in Figure 3.2-13.
Figure 3.2-13 Physical Address Conversion Rules in General-purpose Register Area
Conversion expression [000180H + (RP) × 10H]
When RP = 10H
000180 H
Register bank 0
:
:
000280 H
Register bank 16
:
:
000370 H
Register bank 31
• The register bank pointer (RP) can take the values from "00H" to "1FH" so that the starting address of
the register bank can be set within the range of "000180H" to "00037FH".
• The assembler instruction can use the 8-bit immediate value transfer instruction that is transferred to
The register bank pointer (RP), but only the lower 5 bits of that data is actually used.
• The reset value of the register bank pointer (RP) is set to "00H" after a reset.
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CHAPTER 3 CPU
3.2 Dedicated Registers
MB90495G Series
Interrupt Level Mask Register (PS:ILM)
3.2.4.3
The interrupt level mask register (ILM) is a 3-bit register indicating the interrupt level
accepted by the CPU.
■ Interrupt Level Mask Register (ILM)
Figure 3.2-14 shows the configuration of the interrupt level mask register (ILM).
Figure 3.2-14 Configuration of Interrupt Level Mask Register (ILM)
RP
ILM
bit 15 14 13 12 11 10
PS
CCR
9
8
7
6
5
4
3
2
1 bit 0
ILM2 ILM1 ILM0 B4 B3 B2 B1 B0 ⎯
I
S
T
N
Z
V
C
ILM reset value
000B
The interrupt level mask register (ILM) indicates the level of an interrupt that the CPU is accepting for
comparison with the values of the interrupt level setting bits (ICR:IL2 to IL0) set according to interrupt
requests from each resource. The CPU performs interrupt processing only when an interrupt with a lower
value (interrupt level) than that indicated by the interrupt level mask register (ILM) is requested with an
interrupt enabled (CCR:I = 1).
• When an interrupt is accepted, its interrupt level value is set in the interrupt level mask register (ILM).
Thereafter, an interrupt with a level value lower than the set level value is not accepted.
• At a reset, the interrupt level mask register (ILM) is always set to 0s to enter the interrupt-disabled
(highest interrupt level) state.
• The assembler instruction can use the 8-bit immediate value transfer instruction that is transferred to the
interrupt level mask register (ILM), but only the lower 3 bits of that data is actually used.
Table 3.2-3 Interrupt Level Mask Register (ILM) and Interrupt Level (High/Low)
ILM2
ILM1
ILM0
Interrupt
Level
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Interrupt Level (High/Low)
High (Interrupts Disabled)
Low
For details of the interrupts, see Section "3.5 Interrupt".
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CHAPTER 3 CPU
3.2 Dedicated Registers
MB90495G Series
3.2.5
Program Counter (PC)
The program counter (PC) is a 16-bit counter indicating the lower 16 bits of the address
for the next instruction code to be executed by the CPU.
■ Program Counter (PC)
The program bank register (PCB) indicates the higher 8 bits of addresses where the next instruction code to
be executed by the CPU is stored; the program counter (PC) indicates the lower 16 bits. As shown in Figure
3.2-15, the actual addresses are combined into 24 bits.
The program counter (PC) is updated by the execution of the conditional branch instruction, the subroutine
call instruction, by an interrupt or reset, etc.
The program counter (PC) can also be used as the base pointer when reading the operand.
Figure 3.2-15 Program Counter (PC)
Upper 8 bits
PCB FEH
Lower 16 bits
PC ABCDH
FEABCDH
Note:
CM44-10114-7E
Next instruction to
be executed
Neither the program counter (PC) nor The program bank register (PCB) can be rewritten directly by a
program (such as MOV PC and #FF).
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CHAPTER 3 CPU
3.2 Dedicated Registers
3.2.6
MB90495G Series
Direct Page Register (DPR)
The direct page register (DPR) sets bit 8 to bit 15 (addr 15 to addr 8) for the 8 bits of the
low address directly specified using the operand when executing the instruction by the
abbreviated direct addressing.
■ Direct Page Register (DPR)
The direct page register (DPR) sets bit 8 to bit 15 (addr 15 to addr 8) for the 8 bits of the low address
directly specified using the operand when executing the instruction by the abbreviated direct addressing.
The direct page register (DPR) is 8 bits long and is set to "01H" at a reset. It is a read and write register.
Figure 3.2-16 Generation of Physical Address in Direct Page Register (DPR)
DTB register
AAAAAAAA
DPR register
BBBBBBBB
Direct address during instruction
CCCCCCCC
24-bit
MSB
physical address
AAAAAAAA
LSB
BBBBBBBB
CCCCCCCC
bit 16 bit 15
bit 8 bit 7
bit 0
bit 24
MSB : Most significant bit
LSB : Least significant bit
Figure 3.2-17 shows the setting of direct page register (DPR) and an example of data access.
Figure 3.2-17 Setting of Direct Page Register (DPR) and Data Access Example
Result from executing instruction
MOV S:56H, #5AH
Higher 8 bits Lower 8 bits
DTB register
12H
DPR register
34H
MSB : Most significant bit
LSB : Least significant bit
52
123455H
123457H
123459H
MSB
FUJITSU SEMICONDUCTOR LIMITED
123454H
5AH
123456H
123458H
LSB
CM44-10114-7E
CHAPTER 3 CPU
3.2 Dedicated Registers
MB90495G Series
3.2.7
Bank Register (PCB, DTB, USB, SSB, and ADB)
The bank register sets the MSB 8 bit of the 24-bit address using bank addressing and
consists of the following five registers:
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional bank register (ADB)
Each of the above registers indicate the memory bank to which the program, data, user
stack, system stack, or additional is allocated.
■ Program Bank Register (PCB)
The program bank register (PCB) sets the program (PC) space.
This register is rewritten at execution of the JMPP, CALLP, RETP, or RETI instruction that branches to the
entire 16-MB space, at executing a software interrupt instruction, or at a hardware interrupt or exception
interrupt.
■ Data Bank Register (DTB)
The data bank register (DTB) sets the data (DT) space.
■ User Stack Bank Register (USB) and System Stack Bank Register (SSB)
The user stack bank register (USB) and system stack bank register (SSB) set the stack (SP) space. The bank
register that is used is determined by the value of the stack flag (CCR:S).
■ Additional Bank Register (ADB)
The additional bank register (ADB) sets’ the additional (AD) space.
■ Setting of Each Bank and Data Access
Each bank register is 8 bits long. At a reset, the program bank register (PCB) is set to "FFH" and other bank
registers are set to "00H".
The program bank register (PCB) is a read-only register and other bank registers are read and write
registers.
For the operation of each bank register, see Section "3.1 Memory Space".
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CHAPTER 3 CPU
3.3 General-purpose Register
3.3
MB90495G Series
General-purpose Register
The general-purpose register is a memory block allocated to addresses "000180H" to
"00037FH" in the internal RAM in bank units of 16 bits x 8. It is configured as follows:
• General-purpose 8-bit register (byte registers R0 to R7)
• 16-bit register (word registers RW0 to RW7)
• 32-bit register (long-word registers RL0 to RL3)
■ Configuration of General-purpose Register
General-purpose registers are provided as 32 banks in the internal RAM from "000180H" to "00037FH".
The banks that are used are set by the register bank pointer (RP). The current banks are indicated by
reading the register bank pointer (RP).
The register bank pointer (RP) determines the starting address of each bank as the following expression.
Starting address of general-purpose register = "000180H" + RP × "10H"
Figure 3.3-1 shows the allocation and configuration of the general-purpose register banks in memory space.
Figure 3.3-1 Allocation and Configuration of General-Purpose Register Banks in Memory Space
Internal RAM
:
000180 H Register bank 0
000190 H
Register bank 1
0001A0H
Register bank 2
0001B0H
Byte
address
0002B0H Register bank 19
0002C0H
Register bank 20
0002D0H
0002E0H Register bank 21
:
:
:
:
:
:
000360H
Register bank 30
000370H
Register bank 31
000380H
:
Note:
54
RP
14H
Byte
address
02C0H
RW0
02C1H
02C2H
RW1
02C3H
02C4H
RW2
02C5H
02C6H
02C7H
02C8H
RW3
R1
R0
02CAH
R2
R3
02CCH
R4
R5
02CBH RW5
02CDH RW6
02CEH
R6
R7
02CFH RW7
LSB
16bit
02C9H RW4
RL0
RL1
RL2
RL3
MSB
Conversion expression [000180H + RP × 10H]
R0 to R7
: Byte register
RW0 to RW7 : Word register
RL0 to RL3 : Long-word register
MSB : Most significant bit
LSB : Least significant bit
The register bank pointer (RP) is initialized to "00000B" by a reset.
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CHAPTER 3 CPU
3.3 General-purpose Register
MB90495G Series
■ Register Bank
The register bank can be used as a general-purpose register (byte registers R0 to R7, word registers RW0 to
RW7, and long-word registers RL0 to RL3) to perform various operations or to serve as a pointer. The
long- word register can also be used as a linear addressing to directly access the entire memory space.
In the same way as ordinary RAM, the value in the general-purpose register is unchanged by a reset,
meaning that the state before the reset is held. However, at power-on, the value is undefined.
Table 3.3-1 shows the typical function of the general-purpose register.
Table 3.3-1 Typical Function of the General-purpose Register
Register Name
CM44-10114-7E
Function
R0 to R7
Used as operands for various instructions
Note:
R0 can also be used as the barrel shift counter or the normalized
instruction counter.
RW0 to RW7
Used as addressing
Used as operands for various instructions
Note:
RW0 can also be used as the string instruction counter.
RL0 to RL3
Used as linear addressing
Used as operands for various instructions
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CHAPTER 3 CPU
3.4 Prefix Codes
3.4
MB90495G Series
Prefix Codes
When prefix code is inserted by an instruction, the operation of the instruction can be
changed partially. The prefix code has the following three types:
• Bank select prefix (PCB, DTB, ADB, and SPB)
• Common register bank prefix (CMR)
• Flag change inhibit prefix (NCC)
■ Prefix Code
● Bank select prefix (PCB, DTB, ADB, and SPB)
When the bank select prefix (PCB, DTB, ADB, SPB) codes precede an instruction, any memory space to
be accessed by the instruction can be selected, regardless of the addressing types.
● Common register bank prefix (CMR)
When the common register bank prefix (CMR) code precedes an instruction for accessing a generalpurpose register, the general-purpose register to be accessed by the instruction can be changed to a common
bank (register bank selected when the register bank pointer (RP) is 0) at "000180H" to "00018FH",
regardless of the current value of the register bank pointer (RP).
● Flag change inhibit prefix (NCC)
When the flag change inhibit (NCC) code precedes an instruction for changing various flags of the
condition code register (CCR), a flag change with instruction execution can be inhibited.
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CHAPTER 3 CPU
3.4 Prefix Codes
MB90495G Series
3.4.1
Bank Select Prefix (PCB, DTB, ADB, and SPB)
When the bank select prefix (PCB, DTB, ADB, SPB) codes precede an instruction, any
memory space accessed by the instruction can be set, regardless of the addressing
modes.
■ Bank Select Prefix (PCB, DTB, ADB, SPB)
Memory space used at data access is predetermined for each addressing mode. However, when the bank
select prefix (PCB, DTB, ADB, SPB) codes precede an instruction statement, any memory space accessed
by the instruction statement can be set, regardless of the addressing types. Table 3.4-1 shows the bank
select prefix code and the memory space to be selected.
Table 3.4-1 Bank Select Prefix
Bank Select Prefix
Selected Space
PCB
Program space
DTB
Data space
ADB
Additional space
SPB
When the stack flag (CCR:S) is 0, user stack space is
selected. When the stack flag is 1, system stack
space is selected.
The use of the bank select prefix (PCB, DTB, ADB, SPB) codes causes some instructions to perform
exceptional operations as explained below.
Table 3.4-2 shows the instructions not affected by the bank select prefix code, and Table 3.4-3 shows the
instructions requiring precaution when using the bank select prefix.
Table 3.4-2 Instructions Unaffected by Bank Select Prefix (1 / 2)
Instruction Type
Instruction
Effect
String instruction
MOVS
SCEQ
FILS
MOVSW
SCWEQ
FILSW
The bank register specified for the operand is used
irrespective of the presence or absence of the bank
select prefix code.
Stack instruction
PUSHW
POPW
Irrespective of the presence or absence of the bank
select prefix code, the user stack bank (USB) is
used when the S flag is 0; and the system stack bank
(SSB) is used when the S flag is 1
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CHAPTER 3 CPU
3.4 Prefix Codes
MB90495G Series
Table 3.4-2 Instructions Unaffected by Bank Select Prefix (2 / 2)
Instruction Type
I/O Access
instruction
Interrupt return
instruction
Instruction
MOV A,io
MOVX A, io
MOVW A,io
MOV io,A
MOVW io,A
MOV io,#imm8
MOVW io,#imm16
MOVB A,io:bp
MOVB io:bp,A
SETB io:bp
CLRB io:bp
BBC io:bp,rel
BBS io:bp,rel
WBTC io,bp
WBTS io:bp
RETI
Effect
The I/O space ("000000H" to "0000FFH") is
accessed irrespective of the presence or absence of
the bank select prefix code.
The system stack bank (SSB) is used irrespective of
the presence or absence of the bank select prefix
code.
Table 3.4-3 Instructions Requiring Precaution When Using Bank Select Prefix
Instruction Type
58
Instruction
Explanation
Flag change
instruction
AND CCR,#imm8
OR CCR,#imm8
The bank select prefix code affects up to the next
instruction.
ILM setting
instruction
MOV ILM,#imm8
The bank select prefix code affects up to the next
instruction.
PS Return instruction
POPW PS
Do not add the bank select prefix code to the PS
return instruction.
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CM44-10114-7E
CHAPTER 3 CPU
3.4 Prefix Codes
MB90495G Series
3.4.2
Common Register Bank Prefix (CMR)
When the common register bank prefix (CMR) code precedes an instruction for
accessing a general-purpose register, the general-purpose register to be accessed by
the instruction can be changed to a common bank (register bank selected when the
register bank pointer (RP) is 0) at "000180H" to "00018FH", regardless of the current
value of the register bank pointer (RP).
■ Common Register Bank Prefix (CMR)
The F2MC-16LX family provides common banks at "000180H" to "00018FH" as register banks that can be
commonly accessed by each task, regardless of the values of the register bank pointer (RP).
The use of the common banks facilitates data exchange between two or more tasks.
When the common register bank prefix (CMR) code precedes an instruction for accessing a generalpurpose register, the general-purpose register accessed by the instruction can be changed to a common bank
(register bank to be selected when the register bank pointer (RP) is 0) at "000180H" to "00018FH",
regardless of the current value of the register bank pointer (RP).
Table 3.4-4 shows the instructions requiring care when using the common register bank prefix.
Table 3.4-4 Instructions Requiring Precaution When Using Bank Select Prefix (CMR)
Instruction Type
CM44-10114-7E
Instruction
MOVSW
SCWEQ
FILSW
Explanation
String instruction
MOVS
SCEQ
FILS
Do not add the CMR code to string instructions.
Flag change
instruction
AND CCR,#imm8
OR CCR,#imm8
The CMR code affects up to the next instruction.
PS return instruction
POPW PS
The CMR code affects up to the next instruction.
ILM setting
instruction
MOV ILM,#imm8
The CMR code affects up to the next instruction.
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CHAPTER 3 CPU
3.4 Prefix Codes
3.4.3
MB90495G Series
Flag Change Inhibit Prefix (NCC)
When the flag change inhibit prefix (NCC) code precedes an instruction for changing
various flags of the condition code register (CCR), a flag change caused by instruction
execution can be inhibited.
■ Flag Change Inhibit Prefix (NCC)
The flag change inhibit prefix (NCC) code is used to inhibit an unnecessary flag change.
When the flag change inhibit prefix (NCC) code precedes an instruction for changing various flags of the
condition code register (CCR), a flag change caused by instruction execution can be inhibited. The
inhibited flags are:
• Sticky-bit flag (CCR:T)
• Negative flag (CCR:N)
• Zero flag (CCR:Z)
• Overflow flag (CCR:V)
• Carry flag (CCR:C)
Table 3.4-5 shows the instructions requiring precaution when using the flag change inhibit prefix.
Table 3.4-5 Instructions Requiring Precaution When Using Flag Change Inhibit Prefix (NCC)
Instruction Type
Instruction
Do not the add the NCC code to the string
instruction.
String instruction
MOVS
SCEQ
FILS
Flag change
instruction
AND CCR,#imm8
OR CCR,#imm8
The CCR changes by execution of an
instruction, regardless of the presence or
absence of the NCC code.
The NCC code affects the next
instruction.
PS return instruction
POPW PS
The CCR changes by execution of an
instruction, regardless of the presence or
absence of the NCC code.
The NCC code affects the next
instruction.
ILM setting
instruction
MOV ILM,#imm8
The NCC code affects the next
instruction.
Interrupt instruction
Interrupt return
instruction
INT #vct8
INT addr16
RETI
Context
switch instruction
JCTX @ A
60
MOVSW
SCWEQ
FILSW
Explanation
INT9
INTP addr24
The CCR changes by execution of an
instruction statement, regardless of the
presence or absence of the NCC code.
The CCR changes by execution of an
instruction statement, regardless of the
presence or absence of the NCC code.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 3 CPU
3.4 Prefix Codes
MB90495G Series
3.4.4
Restrictions on Prefix Code
he use of the prefix codes is restricted as follows:
• No interrupt request is accepted during execution of a prefix code and interrupt
inhibit instruction.
• When a prefix code precedes an interrupt inhibit instruction, The effect of the prefix
code is delayed.
• When conflicting prefix codes are used in succession, the last prefix code is enabled.
■ Prefix Code and Interrupt Inhibit Instruction
The interrupt inhibit instruction and prefix code are restricted as shown below.
Table 3.4-6 Prefix Code and Interrupt Inhibit Instruction
Prefix Code
PCB
DTB
ADB
SPB
CMR
NCC
Instruction that does not
accept interrupt request
Interrupt/Hold Inhibit Instruction
(instruction that delays effect of prefix code)
MOV ILM,#imm8
OR CCR,#imm8
AND CCR,#imm8
POPW PS
● Interrupt Inhibition
Even if generated, an interrupt request is not accepted during execution of a prefix code and interrupt
inhibit instruction. When other instructions are executed after execution of a prefix code and interrupt
inhibit instruction, an interrupt is processed.
Figure 3.4-1 Interrupt Inhibition
Interrupt inhibit instruction
. . . . . . . . . . . . . . .
Interrupt request generated
CM44-10114-7E
(a)
Interrupt accepted
FUJITSU SEMICONDUCTOR LIMITED
. . .
(a) Ordinary
instruction
61
CHAPTER 3 CPU
3.4 Prefix Codes
MB90495G Series
● Delay of the effect of the prefix code
When a prefix code precedes an interrupt inhibit instruction, it affects an instruction next to the interrupt
inhibit instruction.
Figure 3.4-2 Interrupt Inhibit Instruction and Prefix Code
Interrupt inhibit instruction
MOV A,FFH
NCC
. . . .
MOV ILM,#imm8
ADD A,01H
CCR: XXX10XXB
CCR: XXX10XXB
CCR does not change by the NCC.
■ Array of Prefix Codes
For array of conflicting prefix codes (PCB, ADB, DTB, SPB) the last one is enabled.
Figure 3.4-3 Array of Prefix Codes
Prefix codes
...
ADB
DTB
PCB
ADD A,01H
...
PCB of the last code of the prefix code is valid
62
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 3 CPU
3.5 Interrupt
MB90495G Series
3.5
Interrupt
The F2MC-16LX family has four interrupt functions for suspending the current
processing to transfer control to a program which is defined separately at generation of
event.
• Hardware interrupt
• Software interrupt
• Interrupts by extended intelligent I/O service (EI2OS)
• Exception processing
■ Type and Function of Interrupt
● Hardware interrupt
This transits control to the interrupt processing program defined by user in response to the interrupt request
from resources.
● Software interrupt
This transfers control to the interrupt processing program defined by user by executing an instruction (such
as INT instruction) dedicated to the software interrupt.
● Interrupt by extended intelligent I/O service (EI2OS)
The extended intelligent I/O service (EI2OS) provides automatic data transfer between resources and
memory. Data can be transferred just by creating the startup-setting program and end program of the
EI2OS. At completion of data transfer, the interrupt processing program is executed automatically.
An interrupt generated by the EI2OS is a type of the above hardware interrupt.
● Exception processing
If an exception (execution of an undefined instruction) is detected among instructions, ordinary processing
is suspended to perform exception processing. This is equivalent to the above software interrupt instruction
INT10.
CM44-10114-7E
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CHAPTER 3 CPU
3.5 Interrupt
MB90495G Series
■ Interrupt Operation
Figure 3.5-1 shows interrupt start and return processing.
Figure 3.5-1 General Flow of Interrupt Operation
START
Executing of
string family*
instruction
Main program
YES
Interrupt request
enabled?
Interrupt start/return processing
NO
Start EI2OS?
Fetch and decode
next instruction
YES
EI2OS
NO
YES
INT instruction?
NO
EI2OS processing
Software
interrupt/
exception
processing
Save dedicated registers
to system stack
Hardware
interrupt
Disable acceptance of
hardware interrupt (I = 0)
Specified count
YES ended? Or termination
request from
resource?
Save dedicated registers
to system stack
NO
Updating of CPU interrupt
processing level (ILM)
YES
RETI instruction?
NO
Dedicated registers from
system stack return, and return
to previous processing which
is the one before calling
interrupt processing
Executing of
ordinary instruction
NO
Return to
processing
due to interrupt
Read interrupt vector,
update PC and PCB,
and branch to
interrupt processing
Repetitive execution
of string family* instruction
completed?
YES
Move pointer to next
instruction by updating PC
*:
64
Interrupt determination is performed by the step during execution of string family instruction
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 3 CPU
3.5 Interrupt
MB90495G Series
3.5.1
Interrupt Factor and Interrupt Vector
The F2MC-16LX family has vector tables corresponding to 256 types of interrupt factor.
■ Interrupt Vector
The interrupt vector tables referenced at interrupt processing are allocated to the most significant addresses
("FFFC00H" to "FFFFFFH") of the memory area. The interrupt vectors share the same area with the EI2OS,
exception processing, and hardware and software interrupts.
• Interrupts (INT0 to INT255) are used as software interrupts.
• At hardware interrupts, the interrupt vectors and interrupt control register (ICR) are fixed for each
resource.
Table 3.5-1 shows the interrupt number and allocation of interrupt vector.
Table 3.5-1 List of Interrupt Vectors
Software
Interrupt
Instruction
Vector
Address
(Low)
Vector
Address
(Middle)
Vector
Address
(High)
Mode
Data
Interrupt
Number
Hardware Interrupt
INT0
FFFFFCH
FFFFFDH
FFFFFEH
Unused
#0
None
:
:
:
:
:
:
:
INT7
FFFFE0H
FFFFE1H
FFFFE2H
Unused
#7
None
INT8
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDFH
#8
(RESET vector)
INT9
FFFFD8H
FFFFD9H
FFFFDAH
Unused
#9
None
INT10
FFFFD4H
FFFFD5H
FFFFD6H
Unused
#10
<Exception processing>
INT11
FFFFD0H
FFFFD1H
FFFFD2H
Unused
#11
Resource interrupt #0
INT12
FFFFCCH
FFFFCDH
FFFFCEH
Unused
#12
Resource interrupt #1
INT13
FFFFC8H
FFFFC9H
FFFFCAH
Unused
#13
Resource interrupt #2
INT14
FFFFC4H
FFFFC5H
FFFFC6H
Unused
#14
Resource interrupt #
:
:
:
:
:
:
:
INT254
FFFC04H
FFFC05H
FFFC06H
Unused
#254
None
INT255
FFFC00H
FFFC01H
FFFC02H
Unused
#255
None
Reference:
CM44-10114-7E
It is recommended to set the unused interrupt vectors to the addresses for exception processing.
FUJITSU SEMICONDUCTOR LIMITED
65
CHAPTER 3 CPU
3.5 Interrupt
MB90495G Series
■ Interrupt Factor, Interrupt Vector, and Interrupt Control Register
Table 3.5-2 shows the relationships between the interrupt factor except software interrupt, and interrupt
vector and interrupt control register.
Table 3.5-2 Interrupt Factor, Interrupt Vector, and Interrupt Control Register (1 / 2)
Interrupt Vector
Interrupt Factor
2
EI OSCorresponded
Number
Interrupt Control
Register
Priority*3
Address
ICR
Address
Reset
X
#08
08H
FFFFDCH
−
−
INT9 instruction
X
#09
09H
FFFFD8H
−
−
Exception processing
X
#10
0AH
FFFFD4H
−
−
CAN controller receive
completion (RX)
X
#11
0BH
FFFFD0H
ICR00
0000B0H*1
ICR01
0000B1H
ICR02
0000B2H*1
ICR03
0000B3H*1
ICR04
0000B4H*1
ICR05
0000B5H*2
ICR06
0000B6H*1
ICR07
0000B7H*1
ICR08
0000B8H*1
CAN controller transmit
completion (TX)/node status
transition (NS)
X
#12
0CH
FFFFCCH
Reserved
X
#13
0DH
FFFFC8H
Reserved
X
#14
0EH
FFFFC4H
External interrupt (INT0/INT1)
Δ
#15
0FH
FFFFC0H
Timebase timer
X
#16
10H
FFFFBCH
16-bit reload timer 0
Δ
#17
11H
FFFFB8H
8-/10-bit A/D converter
Δ
#18
12H
FFFFB4H
16-bit free-run timer overflow
Δ
#19
13H
FFFFB0H
External interrupt (INT2/INT3)
Δ
#20
14H
FFFFACH
Reserved
X
#21
15H
FFFFA8H
PPG timer ch 0/1 underflow
X
#22
16H
FFFFA4H
Input capture 0 fetched
Δ
#23
17H
FFFFA0H
External interrupt (INT4/INT5)
Δ
#24
18H
FFFF9CH
Input capture 1 fetched
Δ
#25
19H
FFFF98H
PPG timer ch 2/3 underflow
X
#26
1AH
FFFF94H
External interrupt (INT6/INT7)
Δ
#27
1BH
FFFF90H
Watch timer
Δ
#28
1CH
FFFF8CH
66
FUJITSU SEMICONDUCTOR LIMITED
Highest
CM44-10114-7E
CHAPTER 3 CPU
3.5 Interrupt
MB90495G Series
Table 3.5-2 Interrupt Factor, Interrupt Vector, and Interrupt Control Register (2 / 2)
Interrupt Vector
Interrupt Factor
EI2OSCorresponded
Number
Address
Reserved
X
#29
1DH
FFFF88H
Input capture 2 fetched
Input capture 3 fetched
X
#30
1EH
FFFF84H
Reserved
X
#31
1FH
FFFF80H
Reserved
X
#32
20H
FFFF7CH
Reserved
X
#33
21H
FFFF78H
Reserved
X
#34
22H
FFFF74H
Reserved
X
#35
23H
FFFF70H
16-bit reload timer 1
O
#36
24H
FFFF6CH
#37
25H
FFFF68H
#38
26H
FFFF64H
#39
27H
FFFF60H
UART1 receive
UART1 transmit
Δ
UART0 receive
UART0 transmit
Δ
#40
28H
FFFF5CH
Flash memory
X
#41
29H
FFFF58H
Delayed interrupt generation
module
X
#42
2AH
FFFF54H
Interrupt Control
Register
ICR
Address
ICR09
0000B9H*1
ICR10
0000BAH*1
ICR11
0000BBH*1
ICR12
0000BCH*1
ICR13
0000BDH*1
ICR14
0000BEH*1
ICR15
0000BFH*1
Priority*3
Lowest
O: Interrupt factor corresponds to EI2OS
X: Interrupt factor does not correspond to EI2OS
: Interrupt factor corresponds to EI2OS and has EI2OS stop function
Δ: Interrupt factor can be used when not using interrupt sources sharing ICR register
*1: • The interrupt level for resources sharing an ICR register become the same.
• When two resources share an ICR register, only one can use the EI2OS.
• When two resources share an ICR register and one specifies the EI2OS, the remaining resource cannot use the
interrupt.
*2: Only the 16-bit reload timer corresponds to the EI2OS. Since the PPG timer does not correspond to the EI2OS, it should
be disabled for interrupts when the 16-bit reload timer uses the EI2OS.
*3: The priority is given when plural interrupts with the same level are generated simultaneously.
CM44-10114-7E
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67
CHAPTER 3 CPU
3.5 Interrupt
3.5.2
MB90495G Series
Interrupt Control Registers and Resources
The interrupt control registers (ICR00 to ICR15) are allocated in he interrupt controller,
and correspond to all resources with interrupt functions. The registers control the
interrupt and extended intelligent I/O service (EI2OS).
■ Interrupt Control Register List
Table 3.5-3 lists the resources corresponding to the interrupt control registers.
Table 3.5-3 Interrupt Control Register List
Address
Register
Abbreviation
Corresponding Resource
0000B0H
Interrupt control register 00
ICR00
CAN controller
0000B1H
Interrupt control register 01
ICR01
Reserved
0000B2H
Interrupt control register 02
ICR02
External interrupt INT0/INT1
Timebase timer
0000B3H
Interrupt control register 03
ICR03
16-bit reload timer 0
A/D converter
0000B4H
Interrupt control register 04
ICR04
Input/output timer
External interrupt INT2/INT3
0000B5H
Interrupt control register 05
ICR05
PPG timer 0/1
0000BH
Interrupt control register 06
ICR06
ICR06
External interrupt INT4/INT5
0000B7H
Interrupt control register 07
ICR07
Input capture 1
PPG timer 2/3
0000B8H
Interrupt control register 08
ICR08
External interrupt INT6/INT7
Watch timer
0000B9H
Interrupt control register 09
ICR09
Input capture 2/3
0000BAH
Interrupt control register 10
ICR10
Reserved
0000BBH
Interrupt control register 11
ICR11
Reserved
0000BCH
Interrupt control register 12
ICR12
16-bit reload timer 1
0000BDH
Interrupt control register 13
ICR13
UART1
0000BEH
Interrupt control register 14
ICR14
UART0
0000BFH
Interrupt control register 15
ICR15
Flash memory, delayed interrupt
generation module
The interrupt control register (ICR) has the following four functions.
Some functions of the interrupt control register (ICR) are different at write and read.
68
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 3 CPU
3.5 Interrupt
MB90495G Series
• Setting of interrupt level of corresponding resource
• Selection of whether to perform normal interrupt or EI2OS for corresponding resource
• Selection of channel of EI2OS
• Display of end state of EI2OS
Note:
CM44-10114-7E
Do not access the interrupt control register (ICR) using the read modify write instruction because it
causes a malfunction.
FUJITSU SEMICONDUCTOR LIMITED
69
CHAPTER 3 CPU
3.5 Interrupt
MB90495G Series
Interrupt Control Register (ICR00 to ICR15)
3.5.3
The functions of the interrupt control registers are shown below.
■ Interrupt Control Register (ICR00 to ICR15)
Port of functions differ depending on whether data is written to or read from the interrupt control registers.
Figure 3.5-2 Interrupt Control Register (ICR00 to ICR15) at Write
At write
7
6
5
4
3
2
1
0
Reset value
00000111
W
W
W
B
W R/W R/W R/W R/W
bit 2 bit 1 bit 0
IL2 IL1 IL0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
bit 3
ISE
0
1
Interrupt level setting bits
Interrupt level 0 (highest)
Interrupt level 7 (no interrupt)
EI2OS enable bit
Starts normal interrupt processing at an interrupt
Starts EI2OS at an interrupt
bit 7 bit 6 bit 5 bit 4
ICS3 ICS2 ICS1 ICS0
R/W : Read/Write
W
: Write only
: Reset value
70
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EI2OS channel select bit
Channel
Descriptor address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FUJITSU SEMICONDUCTOR LIMITED
000100H
000108H
000110H
000118H
000120H
000128H
000130H
000138H
000140H
000148H
000150H
000158H
000160H
000168H
000170H
000178H
CM44-10114-7E
CHAPTER 3 CPU
3.5 Interrupt
MB90495G Series
Figure 3.5-3 Interrupt Control Register (ICR00 to ICR15) at Read
At read
7
6
5
4
3
2
1
0
Reset value
XX000111
⎯
⎯
R
R
B
R/W R/W R/W R/W
bit 2 bit 1 bit 0
IL2 IL1 IL0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
bit 3
ISE
0
1
Interrupt level setting bits
Interrupt level 0 (highest)
Interrupt level 7 (no interrupt)
EI2OS enable bit
Starts normal interrupt processing at an interrupt
Starts EI2OS at an interrupt
bit 5 bit 4
R/W
W
⎯
X
CM44-10114-7E
:
:
:
:
:
Read/Write
Write only
Unused
Undefined
Reset value
S1
0
0
1
1
S0
0
1
0
1
EI2OS status bits
When EI OS in operation or not started
Stop state by end of counting
Reserved
Stop state by request from resource
2
FUJITSU SEMICONDUCTOR LIMITED
71
CHAPTER 3 CPU
3.5 Interrupt
3.5.4
MB90495G Series
Function of Interrupt Control Register
The interrupt control registers (ICR00 to ICR15) consist of the following bits with four
functions.
• Interrupt level setting bits (IL2 to IL0)
• EI2OS enable bit (ISE)
• EI2OS channel select bits (ICS3 to ICS0)
• EI2OS status bits (S1 and S0)
■ Bit Configuration of Interrupt Control Register (ICR)
The bit configuration of the interrupt control registers (ICR) is show below.
Figure 3.5-4 Configuration of Interrupt Control Register (ICR)
Configuration of interrupt control register (ICR) at write
bit 7
6
5
4
3
ICS3 ICS2 ICS1 ICS0 ISE
W
W
W
2
1
bit 0
IL2
IL1
IL0
W
W
W
W
W
Reset value
00000111B
Configuration of interrupt control register (ICR) at read
bit 7
6
5
4
3
2
1
bit 0
⎯
⎯
S1
S0
ISE
IL2
IL1
IL0
⎯
⎯
R
R
R
R
R
R
Reset value
XX000111B
R : Read only
W : Write only
⎯ : Unused
References:
72
• he setting of the channel select bits (ICR:ICS3 to ICS0) is enabled only when starting the EI2OS.
When starting the EI2OS, set the EI2OS enable bit (ICR:ISE) to 1. When not starting the EI2OS, set
the bit to 0.
• The channel select bits (ICR:ICS3 to ICS0) are enabled only at write, and the EI2OS status bits
(ICR:S1, S0) are enabled only at read.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 3 CPU
3.5 Interrupt
MB90495G Series
■ Function of Interrupt Control Register
● Interrupt level setting bits (IL2 to IL0)
These bits set the interrupt levels of the corresponding resources. At reset, the bits are set to level 7 (IL2 to
IL0 = "111B": no interrupt).
Table 3.5-4 shows the relationship between the interrupt level setting bits and interrupt levels.
Table 3.5-4 Relationship between Interrupt Level Setting Bits and Interrupt Levels
IL2
IL1
IL0
Interrupt Level
0
0
0
0 (Highest)
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
6 (Lowest)
1
1
1
7 (No interrupt)
● EI2OS enable bit (ISE)
When an interrupt occurs with the ISE bit set to 1, the EI2OS is started. When an interrupt occurs with the
ISE bit set to 0, ordinary interrupt processing is started. If the EI2OS end condition is satisfied (when the
status bits S1 and S0 are not "00B"), the ISE bit is cleared. When the corresponding resources have no
EI2OS function, this bit must be set to 0 by the program. At reset, the ISE bit is set to 0.
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73
CHAPTER 3 CPU
3.5 Interrupt
MB90495G Series
● EI2OS channel select bits (ICS3 to ICS0)
These bits select EI2OS channels. The EI2OS descriptor addresses are set according to the setting values of
the ICS3 to ICS0 bits. At reset, the ICS3 to ICS0 are set to "0000B".
Table 3.5-5 shows the correspondence between the EI2OS channel select bits and descriptor addresses.
Table 3.5-5 Correspondence between EI2OS Channel Select Bits and Descriptor
Addresses
74
ICS3
ICS2
ICS1
ICS0
Channel to be Selected
Descriptor Address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 3 CPU
3.5 Interrupt
MB90495G Series
● EI2OS status bits (S1 and S0)
When the S1 and S0 bits are read at the termination of the EI2OS, the operating and end states can be
checked. At reset, the S1 and S0 bits are set to "00B".
Table 3.5-6 shows the relationship between the EI2OS status bits (ICR:S1, S0) and the EI2OS status.
Table 3.5-6 Relationships Between EI2OS Status Bits and EI2OS Status
CM44-10114-7E
S1
S0
0
0
When EI2OS in operation or not started
0
1
top state by end of counting
1
0
Reserved
1
1
Stop state by request from resource
EI2OS Status
FUJITSU SEMICONDUCTOR LIMITED
75
CHAPTER 3 CPU
3.5 Interrupt
3.5.5
MB90495G Series
Hardware Interrupt
The hardware interrupt responds to the interrupt request from a resource, suspends the
current-executing program and transfers control to the interrupt processing program
defined by user.
The hardware interrupt corresponds to the EI2OS.
■ Hardware Interrupt
● Function of hardware interrupt
When a hardware interrupt is generated, the interrupt level (IR:IL) of an interrupt request from a resource is
compared with the interrupt level mask register (PS:ILM) and the state of the interrupt enable flag (CCR:I)
is referenced to determine whether to accept the hardware interrupt.
When the hardware interrupt is accepted, registers in the CPU are automatically saved in the system stack.
The interrupt level of the accepted interrupt is stored in the interrupt level mask register (ILM), then
branches to the corresponding interrupt vector.
● Multiple interrupts
Multiple hardware interrupts can be started.
● EI2OS
When the EI2OS function ends, normal interrupt processing is performed. No multiple EI2OSs are started.
Other interrupt requests and EI2OS requests are held during EI2OS processing.
● External interrupt
The external interrupt (wake-up interrupt included) is accepted as a hardware interrupt via the resource
(interrupt request detector).
● Interrupt vector
The interrupt vector tables referenced during interrupt processing are allocated to "FFFC00H" to
"FFFFFFH" in the memory and shared with software interrupts.
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■ Mechanism of Hardware Interrupt
The mechanism related to the hardware interrupt consists of the four sections.
When starting the hardware interrupt, these four sections must be set by the program.
Table 3.5-7 Mechanism Related to Hardware Interrupt
Mechanism Related to
Hardware Interrupt
Function
Resource
Interrupt enable bit, interrupt
request bit
Controls interrupt request from
resource
Interrupt controller
Interrupt control register (ICR)
Sets interrupt level and controls
EI2OS
Interrupt enable flag (I)
Identifies interrupt enable state
Interrupt level mask register
(ILM)
Compares requested interrupt level
and current interrupt level
Microcode
Executes interrupt routine
Interrupt vector table
Stores branch destination address
at interrupt processing
CPU
"FFFC00H" to
"FFFFFFH" in memory
■ Hardware Interrupt Inhibition
No hardware interrupt requests are inhibited under following conditions.
● Hardware interrupt inhibition during write to resource control register in I/O area
No hardware interrupt requests are accepted during write to resource control register. This prevents the
CPU from malfunctioning with respect to interrupt requests generated during rewrite related to interrupt
control registers of each resource.
Figure 3.5-5 shows the hardware interrupt operation during write to the resource control register.
Figure 3.5-5 Hardware Interrupt Request During Write to the Resource Control Register
Write instruction to resource control register
MOV A,#08
MOV io,A
Interrupt request
generated here
CM44-10114-7E
MOV A,2000H
Does not transit to
interrupt processing
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Interrupt processing
Transits to interrupt
processing
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● Hardware interrupt inhibition by interrupt inhibit instruction
Table 3.5-8 shows the hardware interrupt inhibit instructions.
If a hardware interrupt is generated during execution of a hardware interrupt inhibit instruction, it is
processed after execution of the hardware interrupt inhibit instruction, then and other instruction.
Table 3.5-8 Hardware Interrupt Inhibit Instructions
Prefix code
Instruction that does not
accept interrupt request
PCB
DTB
ADB
SPB
CMR
NCC
Interrupt Inhibit Instruction
MOV ILM,#imm8
OR CCR,#imm8
AND CCR,#imm8
POPW PS
● Hardware interrupt inhibition during execution of software interrupt
When a software interrupt is started, the interrupt enable flag (CCR:I) is cleared to 0 and the interrupt is
disabled.
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CHAPTER 3 CPU
3.5 Interrupt
MB90495G Series
3.5.6
Operation of Hardware Interrupt
The operation from the generation of hardware interrupt request to the completion of
interrupt processing is explained below.
■ Start of Hardware Interrupt
● Operation of resource (generation of interrupt request)
The resources with a hardware interrupt request function have an interrupt request flag indicating the
generation of an interrupt request, as well as an interrupt enable flag selecting between enabling and
disabling an interrupt request. The interrupt request flag is set when events inherent to resources occur.
When the interrupt enable flag is set to "enabled", an interrupt request is generated to the interrupt
controller.
● Operation of interrupt controller (control of interrupt request)
The interrupt controller compares the interrupt level (ICR:IL2 to IL0) of simultaneously generated interrupt
requests, selects the request with the highest level (with the smallest IL setting value), and posts it to the
CPU. If there are two or more interrupt requests with the same level, the interrupt request with the smallest
interrupt number is preferred.
● Operation of CPU (interrupt request acceptance and interrupt processing)
The CPU compares the received interrupt level (ICR:IL2 to IL0) with the value of the interrupt level mask
register (ILM) and generates an interrupt processing microcode after end of the current instruction
execution if the interrupt level (IL) is smaller than the value of the interrupt level mask register (ILM) and
an interrupt is enabled (CCR:I = 1).
The EI2OS enable bit (ICR:ISE) is referenced at the beginning of the interrupt processing microcode. When
the EI2OS enable bit (ICR:ISE) is set to 0, ordinary interrupt processing is performed. If the bit is set to 1,
the EI2OS starts.
At interrupt processing, the values of the dedicated registers (A, DPR, ADB, DTB, PCB, PC and PS) are
saved in the system stack (system stack space indicated by SSB and SSP) first.
Next, the address of the vector table corresponding to the generated interrupt is loaded to the program
counter (PCB, PC), the interrupt level mask register (ILM) is updated, and the stack flag (CCR:S) is set to
1.
■ Return from Hardware Interrupt
When the interrupt processing program clears, the interrupt request flag in the resource that causes the
interrupt to execute the RETI instruction, the values of the dedicated registers saved in the system stack are
returned to each register and the operation returns to the processing executed before transition to interrupt
processing.
The interrupt request output to the interrupt controller by the resource is cleared by clearing the interrupt
request flag.
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■ Operation of Hardware Interrupt
Figure 3.5-6 shows the operation from the generation of hardware interrupt to the completion of interrupt
processing.
Figure 3.5-6 Operation of Hardware Interrupt
Internal bus
(7)
PS,PC . .
Microcode
F2MC-16LX
PS
IR
CPU
(6)
I
ILM
Check
Comparator
(5)
(4)
(3)
Other resources
..
.
Resource that generates the interrupt request
Enable FF
AND
Factor FF
(8)
Level
Interrupt
comparator level IL
(2)
(1)
Interrupt controller
RAM
IL
PS
I
ILM
IR
FF
:
:
:
:
:
:
Interrupt level setting bit of interrupt control register (ICR)
Processor status
Interrupt enable flag
Interrupt level mask register
Instruction register
Flip-flop
1. The resource generates an interrupt request.
2. When the interrupt enable bit in the resource is set to "enabled", the resource generates an interrupt
request to the interrupt controller.
3. The interrupt controller that received the interrupt request determines the priority of interrupts
simultaneously requested and posts the interrupt level (IL) corresponding to the appropriate interrupt
request to the CPU.
4. The CPU compares the interrupt level (IL) requested from the interrupt controller with the value of the
interrupt level mask register (ILM).
5. If the interrupt request is preferred to the interrupt mask register (ILM), the interrupt enable flag
(CCR:I) is checked.
6. When an interrupt is enabled by the interrupt enable flag (CCR:I = 1), the requested interrupt level (IL)
is set to the interrupt level mask register (ILM) after completion of the current instruction execution.
7. The values of the dedicated registers are saved, and processing transits to interrupt processing.
8. The program clears the interrupt request generated from the resource and executes the interrupt return
instruction (RETI) to terminate interrupt processing.
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MB90495G Series
3.5.7
Procedure for Use of Hardware Interrupt
The settings of the system stack area, resources, interrupt control registers (ICR) are
required for using the hardware interrupt.
■ Procedure for Use of Hardware Interrupt
Figure 3.5-7 shows an example of the procedure for use of the hardware interrupt.
Figure 3.5-7 Procedure for Use of Hardware Interrupt
Start
(1)
Set system stack area
(2)
Set interrupt of resource
(3)
Set ICR in
interrupt controller
(4)
Set resource to start
operation and interrupt
enable bit to "enabled"
(5)
Interrupt processing program
Stack processing and
(8)
branching to interrupt vector
(7)
Processing
by hardware
Set ILM and I in PS
(9)
Processing interrupt
to resource
(Execute the interruptprocessing)
Clear interrupt factor
(10) Execute interrupt return instruction (RETI)
Main program
(6)
Interrupt request genarated
Main program
1. Set the system stack area.
2. Set an interrupt of the resource with the interrupt request function.
3. Set the interrupt control register (ICR) in the interrupt controller.
4. Set the resource to start operation and the interrupt enable bit to "enabled".
5. Set the interrupt level mask register (ILM) and the interrupt enable flag (CCR:I) ready to accept an
interrupt (CCR:I = 1).
6. An interrupt generated from the resource generates a hardware interrupt request.
7. The interrupt controller saves data in the dedicated registers, and processing transits to interrupt
processing.
8. Execute the program for interrupt generation at interrupt processing.
9. Clear the interrupt request from the resource.
10.Execute the interrupt return instruction (RETI) to return to the program executed before transition to
interrupt processing.
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3.5.8
MB90495G Series
Multiple Interrupts
Multiple hardware interrupts can be generated by setting different interrupt levels in the
interrupt level setting bits of the interrupt control register (ICR:ILO to IL2) in response
to plural interrupt requests from the resource. However, multiple EI2OS cannot be
started.
■ Multiple Interrupts
● Operation of multiple interrupts
If an interrupt request with a higher priority than the interrupt level of the current interrupt processing is
generated during interrupt processing, the current interrupt processing is suspended to accept the generated
higher-level interrupt request. When the higher-level interrupt processing is terminated, the suspended
interrupt processing is resumed. The interrupt level (IL) can be set to 0 to 7. The interrupt request set to
level 7 is never accepted.
If an interrupt request with a priority equal to or lower than the interrupt level of the current-executing
interrupt is generated during interrupt processing, unless the setting of the interrupt enable flag (CCR:I) or
the interrupt level mask register (ILM) is changed, the new interrupt request is held until the current
interrupt processing is completed.
Starting of multiple interrupts generated during interrupt processing can be disabled temporarily by setting
the interrupt enable flag (CCR:I) to "disabled" (CCR:1= 0) or the interrupt level mask register (ILM) to
"disabled" (ILM = 000).
Note:
Multiple EI2OSs cannot be started. During EI2OS processing, other interrupt requests and other EI2OS
requests are all held.
● Example of multiple interrupts
As an example of multiple interrupt processing, assuming that a timer interrupt is preferred to an A/D
converter interrupt, set the interrupt level of the A/D converter to 2 and the interrupt level of the timer to 1.
Figure 3.5-8 shows the processing of the timer interrupt generated during processing of the A/D converter
interrupt.
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Figure 3.5-8 Example of Multiple Interrupts
Main program
(ILM = "111B")
Set interrupt
A/D interrupt
genarated
A/D Interrupt processing (ILM = "010B")
Interrupt level 2
Timer interrupt processing (ILM = "001B")
(IL = "010B")
(1)
Interrupt level 1
(IL = "001B")
(3) Timer interrupt
(2)
generated
(4) Timer interrupt
Suspended
processing
Resumed
Resumption of (8)
main processing
(6) A/D interrupt processing
(5) Return from timer
interrupt
(7) Return from A/D interrupt
• When processing of the A/D converter interrupt is started, the interrupt level mask register (ILM) is set
automatically to the value (2 in example) of the interrupt level (ICR:IL2 to IL0) of the A/D converter.
When an interrupt request with an interrupt level of 1 or 0 is generated under this condition, processing
the generated interrupt is preferred.
• When the interrupt return instruction (RETI) is executed after the completion of interrupt processing, the
values of the dedicated registers (A, DPR, ADB, DTB, PCB, PC, PS) saved in the system stack are
returned to each register and the interrupt level mask register (ILM) is returned to the value before
interrupt processing was suspended.
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3.5.9
MB90495G Series
Software Interrupt
The software interrupt is a function for transiting control from the current-executing
program to the interrupt processing program defined by user by execution of a software
interrupt instruction (INT instruction). The software interrupt is held during execution of
a software interrupt.
■ Start of Software Interrupt
● Start and operation of software interrupt
A software interrupt is started by executing the INT instruction. It does not have an interrupt request flag or
an interrupt enable flag. An interrupt request is generated immediately after the INT instruction is executed.
● Hardware interrupt inhibition
Interrupts by the INT instruction have no interrupt level and the interrupt level mask register (ILM) is not
updated. During execution of the INT instruction, the interrupt enable flag (CCR:I) is set to 0 and a
hardware interrupt is masked.
When enabling a hardware interrupt during software interrupt processing, set the interrupt enable flag
(CCR:I) to 1 during software interrupt processing.
● Operation of software interrupt
When the INT instruction is executed, the software interrupt processing microcode in the CPU is started.
The software interrupt processing microcode saves the values of the dedicated registers in the system stack;
branching to the address of the corresponding interrupt vector table after a hardware interrupt is masked
(CCR:I = 0).
■ Return from Software Interrupt
When the interrupt return instruction (RETI) is executed in the interrupt processing program, the values of
the dedicated registers saved in the system stack are returned to each register and the operation is returned
to the processing performed before branching to interrupt processing.
Note:
84
When the program bank register (PCB) is "FFH", the vector area for the CALLV instruction overlaps the
table for the INT #vct8 instruction. A CALLV and INT #vct8 instructions can not use the same address in
creating a software.
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CHAPTER 3 CPU
3.5 Interrupt
MB90495G Series
3.5.10
Interrupt by EI2OS
EI2OS is a function to automatically transfer data between the resources (I/O) and
memory. It generates the hardware interrupt at termination of data transfer.
■ EI2OS
The EI2OS provides automatic data transfer between the I/O area and memory. When data transfer is
terminated, the termination factor (end condition) is set, branching automatically to the interrupt processing
routine. Data can be transferred just by creating a setup program for starting the EI2OS and an end
program.
● Advantages of EI2OS
Compared to data transfer using the interrupt-processing routine, EI2OS has the following advantages.
• Since the creation of transfer program is not required, the program size can be reduced.
• The transfer count can be set to prevent transfer of unnecessary data.
• Whether to update the buffer address pointer can be specified.
• Whether to update the I/O address pointer can be specified.
● Interrupt by EI2OS termination
At completion of data transfer by the EI2OS, the end condition is set in the EI2OS status bits (ICR:S1, S0),
and then the processing automatically transits to interrupt processing.
The EI2OS termination factor can be determined by checking the EI2OS status bits (ICR:S1, S0) using the
interrupt processing program.
● Interrupt control register (ICR)
This register is within the interrupt controller, and displays the states at starting, setting channel, and
terminating the EI2OS.
● EI2OS descriptor (ISD)
The EI2OS descriptor (ISD), which is allocated between "000100H" and "00017FH" in internal RAM, is 8byte data that is used to set the transfer mode, addresses, transfer count and buffer addresses. It has 16
channels, and a channel number is allocated to each of these channels by the interrupt control register
(ICR).
Note:
CM44-10114-7E
The CPU stops while the EI2OS is in operation.
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■ Operation of EI2OS
Figure 3.5-9 shows the operation of the EI2OS.
Figure 3.5-9 Operation of EI2OS
Memory space
By IOA
I/O area
00 bank area
(5)
CPU
(2)
(3)
Interrupt request
(1)
By ICS
ISD
Interrupt control register (ICR)
(3)
Interrupt controller
By BAP
(4)
ISD
IOA
BAP
ICS
DCT
:
:
:
:
:
Buffer
Count by DCT
EI2OS descriptor
I/O address pointer
Buffer address pointer
EI2OS channel select bit of ICR
Data counter
1. An interrupt request is generated and the EI2OS is started.
2. The interrupt controller selects the EI2OS descriptor.
3. The transfer-source and transfer-destination address pointers are read from the EI2OS descriptor.
4. Data is transferred according to the transfer-source and transfer-destination address pointers.
5. An interrupt factor is cleared automatically.
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MB90495G Series
3.5.11
EI2OS Descriptor (ISD)
The EI2OS descriptor (ISD) is allocated to the addresses "000100H" to "00017FH" in the
internal RAM, and consists of 8 bytes × 16 channels.
■ Configuration of EI2OS Descriptor (ISD)
ISD consists of 8 bytes x 16 channels, and each ISD is composed as shown in Figure 3.5-10. Table 3.5-9
shows the correspondence between the channel number and ISD address.
Figure 3.5-10 Configuration of EI2OS Descriptor (ISD)
MSB
LSB
Higher 8 bits of data counter (DCTH)
H
Lower 8 bits of data counter (DCTL)
Higher 8 bits of I/O address pointer (IOAH)
Lower 8 bits of I/O address pointer (IOAL)
EI2OS status register (ISCS)
Higher 8 bits of buffer address pointer (BAPH)
Middle 8 bits of buffer address pointer (BAPM)
ISD starting address
(000100H + 8 × ICS)
Lower 8 bits of buffer address pointer (BAPL)
L
ICS: EI2OS channel select bit (ICR: ICS3 to ICS0)
Table 3.5-9 EI2OS Descriptor (ISD) Area (1 / 2)
CM44-10114-7E
Channel
(ICR:ICS3 to ICS0)
Descriptor Starting Address
0
000100H
1
000108H
2
000110H
3
000118H
4
000120H
5
000128H
6
000130H
7
000138H
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Table 3.5-9 EI2OS Descriptor (ISD) Area (2 / 2)
88
Channel
(ICR:ICS3 to ICS0)
Descriptor Starting Address
8
000140H
9
000148H
10
000150H
11
000158H
12
000160H
13
000168H
14
000170H
15
000178H
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CHAPTER 3 CPU
3.5 Interrupt
MB90495G Series
Each Register of EI2OS Descriptor (ISD)
3.5.12
The EI2OS descriptor (ISD) consists of the following registers.
• Data counter (DCT)
• I/O address pointer (IOA)
• EI2OS status register (ISCS)
• Buffer address pointer (BAP)
The reset value of each register is undefined and a reset should be performed carefully.
■ Data Counter (DCT)
The data counter (DCT) is a 16-bit register, and corresponds to the transfer data count. It decrements by
one each time data is transferred. When the data counter (DCT) reaches 0, the EI2OS is terminated and then
the processing transits to interrupt processing.
Figure 3.5-11 shows the configuration of the data counter (DCT).
Figure 3.5-11 Configuration of Data Counter (DCT)
DCTL
DCTH
bit 15 14
13
12
11
10
9
bit 8 bit 7
6
5
4
3
2
1
bit 0
DCT B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00
Reset value
XXXXXXXX XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Read/Write
X
: Undefined
■ I/O Address Pointer (IOA)
The I/O address pointer (IOA) is a 16-bit register that sets the low addresses (A15 to A0) of the 00 bank
area where data is transferred to or from the buffer. The high addresses (A23 to A16) are set all to 0 and the
area between "000000H" and "00FFFFH" can be addressed.
Figure 3.5-12 shows the configuration of I/O address pointer (IOA).
Figure 3.5-12 Configuration of I/O Address Pointer (IOA)
IOAL
IOAH
bit 15 14
IOA
13
12
11
10
9
bit 8 bit 7
6
5
4
3
2
1
bit 0
A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
Reset value
XXXXXXXX XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Read/Write
X
: Undefined
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■ EI2OS Status Register (ISCS)
The EI2OS status register (ISCS) is an 8-bit register that sets the method to update the buffer address
pointer and I/O address pointer, transfer data format (byte/word), and transfer direction.
Figure 3.5-13 shows the bit configuration of the EI2OS status register (ISCS).
Figure 3.5-13 Configuration of EI2OS Status Register (ISCS)
7
6
5
4
3
2
1
0
Reset value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
SE
0
1
EI2OS termination control bit
Not terminated by a request from resource
Terminated by a request from resource
bit 1
DIR
0
1
Data transfer direction specify bit
I/O address pointer → Buffer address pointer
Buffer address pointer → I/O address pointer
bit 2
BF
0
1
BAP updating/fixing select bit
Buffer address pointer updated after data transfer *1
Buffer address pointer not updated after data transfer
bit 3
BW
0
1
Byte
Word
bit 4
IF
0
1
IOA updating/fixing select bit
I/O address pointer updated after data transfer *2
I/O address pointer not updated after data transfer
Transfer data length specify bit
bit 7 bit 6 bit 5
Reserved Reserved Reserved
R/W
X
*1
*2
90
:
:
:
:
0
0
0
Reserved bits
Always write 0
Read/Write
Undefined
The buffer address pointer changes only in lower 16 bits, and can only be incremented.
I/O address pointer can only be incremented.
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MB90495G Series
■ Buffer Address Pointer (BAP)
The buffer address pointer (BAP) is a 24-bit register and sets the 16-MB addresses where data is transferred
to or from I/O area. When the BAP updating/fixing select bit of the EI2OS status register (ISCS:BF) is set
to "updated", the buffer address pointer (BAP) changes only in the lower 16 bits (BAPH, BAPL) and does
not change in the higher 8 bits (BAPH). Figure 3.5-14 shows the configuration of the buffer address pointer
(BAP).
Figure 3.5-14 Configuration of Buffer Address Pointer (BAP)
bit 23
BAP
bit 16 bit 15
BAPH
R/W
bit 8 bit 7
bit 0
BAPM
BAPL
R/W
R/W
Reset value
XXXXXXH
R/W : Read/Write
X
: Undefined
References:
CM44-10114-7E
• The area that can be set by the I/O address pointer (IOA) is "000000H" to "00FFFFH".
• The area that can be set by the buffer address pointer (BAP) is "000000H" to "FFFFFFH".
• The maximum transfer count that can be set by the data counter (DCT) is 65,536.
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3.5.13
MB90495G Series
Operation of EI2OS
The flowchart of operation of the EI2OS using the microcode in the CPU is shown
below:
■ Operation of EI2OS
Figure 3.5-15 Flowchart of Operation of EI2OS
Interrupt request
generated from resource
NO
ISE = 1
YES
Read ISD/ISCS
Interrupt processing
Termination
request from
resource?
YES
NO
YES
Address set to BAP
(Data transfer)
(Data transfer)
Address set to BAP
IF=0?
NO
Updating value
depends on BW
IOA updated
YES
Updating value
depends on BW
Decrement DCT
DCT = "00H"?
NO
Set S1 and S0 to "00B"
92
Address set to IOA
YES
BF = 0?
NO
YES
SE = 1?
NO
DIR = 1?
NO
Address set to IOA
: EI2OS descriptor
: EI2OS status register
: IOA updating/fixing
select bit
BW
: Transfer data length
specify bit
BF
: BAP updating/fixing
select bit
DIR
: Data transfer direction
specify bit
SE
: EI2OS termination control
bit
DCT : Data counter
IOA
: I/O register address
pointer
BAP : Buffer address pointer
ISE
: EI2OS enable bit (ICR)
S1, S0 : EI2OS status (ICR)
ISD
ISCS
IF
BAP updated
(-1)
YES
EI2OS termination processing
Set S1 and S0 to "01B"
Set S1 and S0 to "11B"
Clear resource
interupt request
Clear ISE to "0"
Return of CPU operation
Interrupt processing
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CHAPTER 3 CPU
3.5 Interrupt
MB90495G Series
3.5.14
Procedure for Use of EI2OS
The procedure for using the EI2OS is shown below:
■ Procedure for Use of EI2OS
Figure 3.5-16 Procedure for Use of EI2OS
Processing by software
Processing by hardware
Start
Initial Setting
Set system stack area
Set EI2OS descripter
Set resource interrupt
Set interrupt control register
(ICR)
Set start operation of
intenal resource and
interrupt enable bit
Set ILM and I in PS
S1, S0 = "00B"
Execute user program
(Interrupt request) and (ISE = 1)
Data transfer
Determine transition to interrupt
by specified times transfer
termination ortermination
request from resources.
Transits to interrupt processing
Reset EI2OS
(channel switching)
NO
YES
S1, S0 = "01B"or
S1, S0 = "11B"
Data processing in buffer
RETI
ISE
: EI2OS enable bit (ICR)
S1, S0 : EI2OS status (ICR)
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3.5.15
MB90495G Series
EI2OS Processing Time
The time required for EI2OS processing depends on the following factors:
• Setting of EI2OS status register (ISCS)
• Data length of transfer data
Some interrupt handling time is required at the transition to hardware interrupt
processing after completion of data transfer.
■ EI2OS Processing Time (time for one transfer)
● At continuing data transfer (DCT ≠ 0, ISCS:SE=0)
The EI2OS processing time at continuing data transfer is determined by the setting of the EI2OS status
register (ISCS) as shown in Table 3.5-10.
Table 3.5-10 EI2OS Execution Time
Setting of EI2OS Termination
Control Bit (SE)
Setting of IOA Updating/Fixing
Select Bit (IF)
Setting of BAP address
updating/fixing select bit (BF)
Termination by
Termination Request
from Resource
Ignores Termination
Request from Resource
Fixed
Updated
Fixed
Updated
Fixed
32
34
33
35
Updated
34
36
35
37
Unit: Machine cycle (one machine cycle is equal to one cycle of the machine clock (φ).)
In addition, compensation is required depending on the conditions at executing EI2OS as shown in Table
3.5-11.
Table 3.5-11 Compensation Value for Data Transfer at EI2OS Processing Time
Internal Access
External Access
II/O Register Address Pointer
B/even
Odd
B/even
8/odd
B/even
0
+2
+1
+4
Odd
+2
+4
+3
+6
B/even
+1
+3
+2
+5
8/odd
+4
+6
+5
+8
Internal access
Buffer address
pointer
External access
B: Byte data transfer
8: Word of 8-bit external bus width
Even: Word transfer at even address
Odd: Word transfer at odd address
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● At end of data counter (DCT) (DCT ≠ 0, ISCS:SE=0)
At completion of data transfer by the EI2OS, since the hardware interrupt is started, the interrupt handling
time is added. The EI2OS processing time at the end of counting is calculated by the following expression.
EI2OS processing time at end of counting = EI2OS processing time at continuing data transfar + (21 + 6 x Z)
machine cycles
Interrupt handling time
(Z: Compensation value of interrupt handling time)
The interrupt handling time depends on the address set by the stack pointer. Table 3.5-12 shows the
compensation value (Z) of the interrupt handling time.
Table 3.5-12 Compensation Value (Z) of Interrupt Handling Time
Address Set by Stack Pointer
Compensation Value (Z)
For external area (8-bit address)
+4
For external area (even address)
+1
For external area (odd address)
+4
For internal area (even address)
0
For internal area (odd address)
+2
● At termination by termination request from resource (DCT ≠ 0, ISCS=1)
If data transfer by the EI2OS is terminated during its processing by the termination request from a resource
(ICR:S1, S0 = "11B"), processing transits to interrupt processing. The EI2OS processing time at a
termination request from a resource is calculated as follows:
EI2OS processing time at termination during processing = 36 + 6 x Z
machine cycles
(Z: Compensation value of interrupt handling time)
Reference:
CM44-10114-7E
One machine cycle is equal to one clock cycle of the machine clock (φ).
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CHAPTER 3 CPU
3.5 Interrupt
3.5.16
MB90495G Series
Exception Processing Interrupt
The F2MC-16LX family performs exception processing when an undefined instruction is
executed.
Exception is basically the same as interrupt. When an exception is detected between
instructions, normal processing is suspended to perform exception processing.
Exception processing is performed when an unexpected operation is performed, and
should be used only for starting recovery software at debugging or in an emergency.
■ Exception Processing
● Operation of exception processing
The F2MC-16LX family treats all instruction codes not defined in the instruction map as undefined
instructions. If an undefined instruction is executed, the processing equal to the software interrupt
instruction INT # 10 is performed.
At exception processing, the following processing is performed before the transition to interrupt
processing:
• The values of dedicated registers (A, DPR, ADB, DTB, PCB, PC, PS) saved to the system stack
• The interrupt enable flag (CCR:I) cleared to 0 and an interrupt disabled
• The stack flag (CCR:S) set to 1
The value of the program counter (PC) saved in the stack is a value of the address where undefined
instructions are stored. For instruction codes of 2 bytes or more, the value of the program counter (PC) is a
value of the address where instruction codes that can be identified as undefined are stored. When the type
of exception factor must be determined at exception processing, use the saved program counter (PC).
● Return from exception processing
When the program counter (PC) indicates an undefined instruction, the interrupt return instruction (RETI)
from exception processing is executed to return to exception processing. Some measures such as
performing a software reset should be taken when returning from exception processing.
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3.5.17
Time Required to Start Interrupt Processing
The time for terminating the currently executing instruction plus the interrupt handling
time is required from generation of the hardware interrupt request to execution of the
interrupt-processing.
■ Time Required to Start Interrupt Processing
The interrupt request sampling wait time and the interrupt handling time (time required for preparation for
interrupt processing) are required from generation of the interrupt request and acceptance of interrupt, to
execution of the interrupt processing. Figure 3.5-17 shows the interrupt processing time.
Figure 3.5-17 Interrupt Processing Time
Operation of CPU
Interrupt wait time
Execution of normal instruction
Interrupt request
sampling wait time
Interrupt handling
Interrupt processing
Interrupt handling time
(θ machine cycle)*
Interrupt request generated
: Last instruction cycle where sampling interrupt request.
: One machine cycle is equal to one cycle of the machine clock (φ).
*
● Interrupt request sampling wait time
It indicates a time from the generation of the interrupt request to the termination of the currently executing
instruction.
Whether the interrupt request is generated or not is determined by sampling the interrupt request in the last
cycle of each instruction. The CPU cannot recognize the interrupt request during execution of each
instruction, as a result wait time occurs.
Reference:
CM44-10114-7E
The interrupt request sampling wait time is longest when the interrupt request is generated immediately
after starting execution of the POPW, RW0, …RW7 instructions with the longest execution cycle (45
machine cycles).
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3.5 Interrupt
MB90495G Series
● Interrupt handling time (θ machine cycles)
The CPU requires an interrupt handling time of θ machine cycles to save the dedicated registers to the
system stack and fetch the interrupt vector table address after accepting the interrupt request. The interrupt
handling time (θ) is obtained using the following equations.
θ = 24 + 6 x Z machine cycles (Z: compensation value of interrupt handling time)
The interrupt handling time depends on the address set by the stack pointer. Table 3.5-13 shows the
compensation value (Z) of the interrupt handling time.
Table 3.5-13 Compensation Value (Z) of Interrupt Handling Time
Address Set by Stack Pointer
Reference:
98
Compensation Value (Z)
For external area (8-bit address)
+4
For external area (even address)
+1
For external area (odd address)
+4
For internal area (even address)
0
For internal area (odd address)
+2
One machine cycle is equal to one clock cycle of the machine clock (φ).
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MB90495G Series
3.5.18
Stack Operation for Interrupt Processing
When an interrupt request is accepted, the values of dedicated registers are
automatically saved to the system stack before transition to interrupt processing. At
completion of interrupt processing, the values of the dedicated registers are
automatically returned from the system stack.
■ Stack Operation at Starting Interrupt Processing
When an interrupt is accepted, the CPU automatically saves the values of the current-dedicated registers in
the system stack in the following order.
• Accumulator (AH, AL)
• Direct page register (DPR)
• Additional data bank register (ADB)
• Data bank register (DTB)
• Program bank register (PCB)
• Program counter (PC)
• Processor status (PS)
Figure 3.5-18 shows the stack operation at starting interrupt processing.
Figure 3.5-18 Stack Operation at Starting Interrupt Processing
Immediately before interrupt
SSB
00 H
SSP
08FEH
A
0000 H
AH
08F2H
08FEH
AL
DPR 01 H
ADB 00 H
00 H
PCB FF H
DTB
PC
803FH
PS
20E0H
Immediately before interrupt
Address Memory
XX H
XX H
XX H
XX H
XX H
XX H
XX H
XX H
XX H
XX H
XX H
XX H
08FEH
08FF H
Low
SSB
Address Memory
00 H
SSP
08F2H
A
0000H
AH
08F2H
08FEH
AL
DPR 01 H
ADB 00 H
00 H
PCB FF H
DTB
PC
803FH
PS
20E0H
SP
Byte
High
E0 H
20H
3F H
80H
FF H
00H
00H
01H
FEH
08H
00H
00H
08FEH
08FF H
SP after
updating
PS
PC
PCB
DTB
ADB
DPR
AL
AH
SP
Byte
■ Stack Operation at Return from Interrupt Processing
When the interrupt return instruction (RETI) is executed after completion of interrupt processing, the
values of the dedicated registers (PS, PC, PCB, DTB, ADB, DPR, AL, AH) are returned to each register
from the system stack, and the dedicated registers are returned to the state before interrupt processing was
started.
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CHAPTER 3 CPU
3.5 Interrupt
3.5.19
MB90495G Series
Program Example of Interrupt Processing
This section gives a program example of interrupt processing.
■ Program Example of Interrupt Processing
● Processing specification
This is an example of interrupt program using external interrupt 4 (INT4).
● Coding example
DDR2
EQU 000011H
; Port 2 direction registe
ENIR
EQU 000030H
; Interrupt/DTP enable register
EIRR
EQU 000031H
; Interrupt/DTP flag
ELVR
EQU 000032H
; Request level setting register
ICR00
EQU 0000B0H
; Interrupt control register
STACK
SSEG
; Stack
RW
100
STACK_T RW
1
STACK
ENDS
;-----Main program--------------------------------------------------------------CODE
CSEG
;
START:
MOV RP,#0
; The general-purpose register uses the starting bank.
MOV ILM,#07H
; ILM in PS set to level 7
MOV A,#!STACK_T
; System stack set
MOV SSB,A
MOVW A,#STACK_T
; Stack pointer set
MOVW SP,A
; In this case, S flag = 1, so set to SSP
MOV DDR2,#00000000B
; The P24/INT4 pin set to input.
OR
CCR,#40H
; I flag of CCR in PS set to interrupt enabled
MOV I:ICR00,#00H
; Interrupt level 0 (highest)
MOV I:ELVR,#00010000B ; INT4 as an High level request
MOV I:EIRR,#00H
; INT4 interrupt factor cleared
MOV I:ENIR,#10H
; INT4 input enabled
:
LOOP:
NOP
; Dummy loop
NOP
NOP
NOP
BRA LOOP
; Unconditional jump
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;-----Interrupt program---------------------------------------------------------ED_INT1:
MOV I:EIRR,#00H
; New acceptance of INT0 disabled
NOP
NOP
NOP
NOP
NOP
NOP
RETI
; Return from interrupt
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS = OFFH
ORG OFFDOH
; Vector set to interrupt #11 (OBH)
DSL ED_INT1
ORG OFFDCH
; Reset vector set
DSL START
DB
00H
; Set to single-chip mode
VECT
ENDS
END
START
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CHAPTER 3 CPU
3.5 Interrupt
MB90495G Series
■ Program Example of EI2OS
● Processing specification
• The EI2OS is started by detecting the High level of the signal to be input to the INT0 pin.
• When the High level is input to the INT0 pin, EI2OS is started and the data of port 0 is transferred to
memory address "3000H".
• The transfer data is 100 bytes. After 100 bytes are transferred, an interrupt is generated at completion of
transfer by the EI2OS transfer.
● Coding example
DDR1
ENIR
EIRR
ELVR
ICR00
BAPL
BAPM
BAPH
ISCS
IOAL
IOAH
DCTL
DCTH
ER0
STACK
EQU 000011H
; Port 1 direction register
EQU 000030H
; Interrupt/DTP enable register
EQU 000031H
; Interrupt/DTP factor registe
EQU 000032H
; Request level setting register
EQU 0000B0H
; Interrupt control register
EQU 000100H
; Lower of buffer address pointer
EQU 000101H
; Middle of buffer address pointer
EQU 000102H
; Higher of buffer address pointer
EQU 000103H
; EI2OS status
EQU 000104H
; Lower of I/O address pointer
EQU 000105H
; Higher of I/O address pointer
EQU 000106H
; Lower of data counter
EQU 000107H
; Higher of data counter
EQU EIRR:0
; External interrupt request flag bit defined
SSEG
; Stack
RW
100
STACK_T RW 1
STACK
ENDS
;-----Main program--------------------------------------------------------------CODE
CSEG
START:
AND CCR,#0BFH
; I flag of CCR in PS cleared to interrupt disabled
MOV RP,#00
; Register bank pointer set
MOV A,#!STACK_T
; System stack set
MOV SSB,A
MOVW A,#STACK_T
; System stack set
; in this case, S flag = 1, so set to SSP
MOVW SP,A
MOV I:DDR1,#00000000B ; P10/INT0 pin set to input
MOV BAPL,#00H
; Buffer address set (003000H)
MOV BAPM,#30H
MOV BAPH,#00H
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MOV
ISCS,#00010001B
;
;
;
;
;
;
I/O Address not updated, byte transfer performed,
and buffer address updated
Data transferred from I/O to buffer,
and termination by resource
Transfer destination address set
(port 0: 000000H)
MOV
IOAL,#00H
MOV
MOV
MOV
MOV
IOAH,#00H
DCTL,#64H
; Transfer byte count set (100 bytes)
DCTH,#00H
I:ELVR,#00000001B ; EI2OS channel 0, EI2OS enabled,
; and interrupt level 0 (highest)
I:ELVR,#00000001B ; INT0 set as an High level request
I:EIRR,#00H
; INT0 interrupt factor cleared
I:ENIR,#01H
; INT0 interrupt enabled
ILM,#07H
; ILM in PS set to level 7
CCR,#40H
; I flag of CCR in PS set to interrupt enabled
MOV
MOV
MOV
MOV
OR
:
LOOP:
BRA LOOP
; Infinite loop
;-----Interrupt program---------------------------------------------------------WARI
CLRB ER0
; Interrupt/DTP request flag cleared
:
Processing by user
; EI2OS termination factor checked,
:
; data processing during buffering
; EI2OS reset
RETI
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS = OFFH
ORG OFFDOH
; Vector set to interrupt #11 (0BH).
DSL WARI
ORG OFFDCH
; Reset vector set
DSL START
DB
00H
; Set to single-chip mode
VECT
ENDS
END START
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CHAPTER 3 CPU
3.6 Reset
3.6
MB90495G Series
Reset
When a reset factor occurs, the CPU immediately suspends the current processing and
starts the reset operation.
The reset factors are as follows:
• Power-on
• Overflow of watchdog timer
• Software reset request
• Generation of external reset request (RST pin)
■ Reset Factors
Table 3.6-1 Reset Factor
Reset
Factor
Machine
Clock
Watchdog
Timer
Oscillation
Stabilization
Waiting
Power on reset
At power on
MCLK
Stops
Generated
Watchdog timer reset
Watchdog timer overflow
MCLK
Stops
None
Software reset
0 is written to the RST bit
MCLK
Stops
None
External reset
Input L level to RST pin
MCLK
Stops
None
MCLK: Main clock
● Power on reset
• The power on reset occurs at power on.
• The reset operation is executed after the oscillation stabilization wait time of 218/HCLK has elapsed.
● Watchdog timer reset
• Unless the watchdog timer is periodically cleared at the interval time to be repeatedly counted after
starting, an overflow occurs, causing a reset.
• The oscillation stabilization wait time is not generated by a watchdog timer reset.
For the details of the Watchdog timer, see "CHAPTER 6 WATCHDOG TIMER".
● Software reset
• The software reset occurs when 0 is written to the internal reset signal generate bit (LPMCR:RST) in the
low-power consumption mode control register.
• The oscillation stabilization wait time is not generated by a software reset.
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● External reset
• The external reset occurs when a Low level is input to the external reset pin (RST pin). The time for
inputting Low level from the RST pin requires at least 16 machine cycles (16/φ). It also occurs if the
extension of the bus cycle lasts for 16 machine cycles (16/φ) or more when external bus access is set.
• An external reset does not require the oscillation stabilization wait time.
Note:
CM44-10114-7E
If an external reset request is generated from the RST pin during writing by a transfer instruction (such as
MOV), the reset cancel wait state is set after completion of the transfer instruction, so writing is
terminated normally. For a string instruction (such as MOVS), the reset cancel wait state may be set
before completion of transfer by a specified counter value.
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CHAPTER 3 CPU
3.6 Reset
3.6.1
MB90495G Series
Reset Factors and Oscillation Stabilization Wait Time
The oscillation stabilization wait state after reset varies depending on the reset factors.
■ Reset Sources and Oscillation Stabilization Wait Time
Table 3.6-2 Reset Factors and Oscillation Stabilization Wait Times
Oscillation Stabilization Wait Time
(The parenthesized values are provided when the
oscillation clock operates at 4 MHz.)
Reset Factor
Power on reset
218/HCLK
Watchdog reset
None
Software reset
None
External reset
None
HCLK: Oscillation clock
Figure 3.6-1 Oscillation Stabilization Wait Interval for the MB90495G Series during a Power-on Reset
Vcc
CLK
CPU operation
2 17 /HCLK
Voltage step-down circuit
stabilization wait interval
2 18 /HCLK
Oscillation stabilization wait interval
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Table 3.6-3 Oscillation Stabilization Wait Time by Clock Select Register (CKSCR)
Clock Select Bit
Oscillation Stabilization Wait Time
(The parenthesized values are provided when the
oscillation clock operates at 4 MHz.)
WS1
WS0
0
0
210/HCLK (256 μs)
0
1
213/HCLK (approx. 2.048 ms)
1
0
215/HCLK (approx. 8.192 ms)
1
1
217/HCLK (approx. 32.77 ms) *
HCLK: Oscillation clock
*: At power on, the oscillation stabilization wait time is fixed at 218/HCLK (approximately
65.54 ms).
Note:
Ceramic or crystal oscillators require the oscillation stabilization wait time of some tens of milliseconds
to stabilize oscillation.
For the details of the clock, see "3.7 Clocks".
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CHAPTER 3 CPU
3.6 Reset
3.6.2
MB90495G Series
External Reset Pin
The external reset pin (RST pin) is a reset input pin. Input of an external Low level
generates a reset factor. The MB90495G series starts the reset operation in
synchronization between the CPU and clock.
■ Block Diagram of External Reset Pin
Figure 3.6-2 Block Diagram of External Reset Pin
RST
Pch
Pin
Nch
CPU operating clock
(PLL multiplying circuit, 2 frequency division of HCLK)
Synchronization
circuit
HCLK: Oscillation clock
Notes:
108
Internal reset signal
Input buffer
• To prevent damage to memory due to a reset during writing to memory, a Low level is input to the
RST pin in a machine cycle in which memory is not damaged.
• The CPU operation clock is required to initialize internal circuits. In particular, at operation on an
external clock, the reset signal and CPU operation clock signal must be input.
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3.6 Reset
MB90495G Series
3.6.3
Reset Operation
During reset operation, the mode for reading mode data and reset vectors is set
according to the settings of the mode pins (MD0 to MD2) and a mode fetch is executed.
When the oscillation clock is returned from stop states (power on, stop mode) by a
reset, a mode fetch is executed after the elapse of the main clock oscillation
stabilization wait time.
■ Flowchart of Reset Operation
Figure 3.6-3 shows the flowchart of reset operation.
Figure 3.6-3 Flowchart of Reset Operation
Power-on reset
Software reset
External reset (RST pin)
Watchdog timer reset
Reset operation
Oscillation stabilization wait time
Reset cleared
Mode data fetched
Reset sequence
Changes pin state
and function related
to external bus mode
Reset vector fetched
Normal operation
(RUN state)
Processing from address indicated
by reset vector executed
■ Oscillation Stabilization Wait Time in Standby Mode
When a reset occurs during operation in a stop mode or subclock mode in which the oscillation clock is
stopped, and oscillation stabilization wait time of 217/HCLK (approximately 32.77 ms when the oscillation
clock operates at 4 MHz) is generated.
Reference:
For standby mode operation, see Section "3.8 Low-power Consumption Mode".
■ Mode Pin
The MD0 to MD2 mode pins are external pins. They are used to set the mode for reading data and reset
vectors.
For the details of the mode pins (MD0 to MD2), see Section "3.9.3 Memory Access Mode".
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3.6 Reset
MB90495G Series
■ Mode Fetch
At transition to the reset operation, the CPU automatically transfers mode data and reset vectors by
hardware to the appropriate register in the CPU core. The mode data and reset vector are allocated to four
bytes of addresses "FFFFDCH" to "FFFFDFH". After a reset factor is generated (or after the elapse of the
oscillation stabilization wait time), the CPU immediately outputs the addresses of the mode data and reset
vectors to the bus to fetch the mode data and reset vectors. This operation is called "mode fetch." At
completion of mode fetch, the CPU starts processing from the address indicated by the reset vector.
Figure 3.6-4 Transfer of Mode Data and Reset Vectors
Memory space
F2MC-16LX CPU core
PC
FFFFDCH
Reset vector bits 7 to 0
FFFFDDH
Reset vector bits 15 to 8
FFFFDE H
FFFFDFH
PCB
Reset vector bits 23 to 16
CPU mode data
Reset sequence
Micro ROM
Mode
register
Note:
Whether to read the mode data and reset vectors from internal ROM or from external ROM is set by the
mode pins (MD0 to MD2). When the mode pins are in the external vector mode, the mode data and reset
vectors are fetched from external ROM. For use in the single-chip mode or the internal-ROM externalbus mode, the mode pins should be set to the internal vector mode.
● Mode data
The mode data is used to set a memory access mode or a memory access area. It is allocated to address
"FFFFDFH". During the reset operation, this data is read automatically by a mode fetch and stored in the
mode register.
● Reset vectors
The reset vectors are the start addresses of execution after completion of the reset operation. They are
allocated to addresses "FFFFDCH" to "FFFFDEH". During the reset operation, these vectors are read
automatically by a mode fetch and transferred to the program counter.
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3.6.4
Reset Factor Bit
To check reset factors, read the value of the watchdog timer control register (WDTC).
■ Reset Factor Bit
Each reset factor provides a flip-flop circuit corresponding to each factor. The state of the flip-flop circuit
can be checked by reading the value of the watchdog timer control register (WDTC). If it is necessary to
identify reset factors after completion of the reset operation, read the value of the watchdog timer control
register (WDTC) by software to branch the value to the appropriate program.
Figure 3.6-5 Block Diagram of Reset Factor Bits
RST pin
Power-on
Power-on
detector
Watchdog timer
control register
(WDTC)
No clear during
interval time
RST = L
External reset
request detector
RST bit set
LPMCR register
RST bit write
detector
Watchdog timer
reset detector
Clear
S
R
S
F/F
R
S
F/F
Q
R
S
F/F
Q
R
Delay
circuit
F/F
Q
Q
The watchdog timer
control register
(WDTC) is read
F2MC-16LX Internal bus
S :
R :
Q :
F/F :
Set
Reset
Output
Flip-flop circuit
■ Correspondence of Reset Factor Bit and Reset Factor
Figure 3.6-6 shows the configuration of the reset factor bits in the watchdog timer control register
(WDTC:PONR, WRST, ERST, SRST).
Figure 3.6-6 Configuration of Reset Factor Bit
Watchdog timer
control register (WDTC)
bit 7
bit 6
PONR
⎯
R
⎯
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
WRST ERST SRST WTE WT1 WT0
R
R
R
W
W
Reset value
XXXXX111B
W
R : Read only
W : Write only
X : Undefined
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CHAPTER 3 CPU
3.6 Reset
MB90495G Series
Table 3.6-4 Correspondence of Reset Factor Bit Value and Reset Factor
Reset Factor
PONR
WRST
ERST
SRST
Power on reset
1
X
X
X
Watchdog timer reset
*
1
*
*
Input of external reset signal to RST pin
*
*
1
*
Software reset (RST bit)
*
*
*
1
*: The previous state is held
X: Undefined
■ Notes on Reset Factor Bit
● Power on reset
When a power on reset is executed, the PONR bit is set to 1 after completion of the reset operation. Any
reset factor bit other than the PONR bit is undefined. When the PONR bit is 1 after completion of the reset
operation, ignore the value of any bit other than the PONR bit.
● At two or more reset factors
The reset factor bit is set to 1 according to each reset factor even when two or more reset factors are
generated. For example, if the watchdog timer overflows and an external reset request is generated from the
RST pin at the same time, both WRST and ERST bits are set to 1 after completion of the reset operation.
● Clearing of reset factor bit
Once set, the reset factor bit is not cleared even if any reset factor other than the set factor is generated. The
reset factor bit is cleared after the completion of reading the watchdog timer control register (WDTC).
For the watchdog timer, see "CHAPTER 6 WATCHDOG TIMER".
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3.6.5
State of Each Pin at Reset
This section explains the state of each pin at reset.
■ State of Pins at Reset
The state of the pins during reset operation is determined by the settings of the mode pins (MD2 to MD0).
● When internal vector mode set:
• If the internal vector mode is set, all I/O pins enter the high-impedance state and mode data is read to
internal ROM.
● When external vector mode set:
• If the external vector mode 1 is set, the operating state or pin state of the external bus pins
corresponding to ports 1 and 2 is determined. Port 3 partly enters the input-enable state.
• If the external vector mode 2 is set, the operating state or pin state of the external bus pin corresponding
to port 2 is determined. Port 3 partly enters the input-enable state.
• If both external vector modes 1 and 2 are set, other I/O pins enter the high-impedance state and mode
data is read to external ROM.
■ State of Pins after Mode Data Read
The state of the pins after the mode data is read is determined by the bus mode setting bit (M1 and M0) in
the mode register.
● When single-chip mode selected
• The I/O pins (resource pins) are all set to the high-impedance state, and the mode data read destination
is the internal ROM.
● External bus mode
• Ports 0 to 2 function as external bus pins and port 3 as an external bus control pin. When mode data is
read to internal ROM, the pins corresponding to ports 0 to 3 change from the high-impedance state to
the operating state.
Note:
CM44-10114-7E
Don’t let the device connected to pins that enter the high-impedance state, malfunction when the reset
factor is generated.
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3.7 Clocks
3.7
MB90495G Series
Clocks
The clock generation section controls the internal clock that is an operating clock for
the CPU or resources. The clock generated by the clock generation section is called a
"machine clock" and one cycle of the machine clock is a machine cycle. The clock to be
supplied from a high-speed oscillator is called an "oscillation clock" and the 2frequency division of the oscillation clock is called a "main clock." The 4-frequency
division of a clock to be supplied from a low-speed oscillator is called a "subclock" and
the clock to be supplied from the PLL oscillator circuit is called a "PLL clock."
■ Clock
The clock generation section has oscillators and generates an oscillation clock by connecting an oscillator
to oscillation pins. External clocks that are input to the oscillation pins can be used as oscillation clocks.
The PLL clock multiplying circuit can be used to generate four clocks for multiplying the oscillation clock.
The clock generation section controls the oscillation stabilization wait time, PLL clock multiplying circuit,
and selects internal clock by the clock selector.
● Oscillation clock (HCLK)
This clock is generated by connecting an oscillator or inputting an external clock to the high-speed
oscillation pins (X0 and X1).
● Main clock (MCLK)
This clock is 2-frequency division of oscillation clock, and is an input clock to the timebase timer and clock
selector.
● Subclock (SCLK)
This clock is a clock with 4-frequency division of the clock generated by connecting an oscillator or
inputting an external clock to the low-speed oscillation pins (X0A and X1A). It can also be used as an
operating clock for the watch timer or as a low-speed machine clock.
● PLL clock (PCLK)
This clock is multiplied by the PLL clock multiplying circuit (PLL oscillator). It can be selected from four
types of clock according to the setting of the multiplication rate select bits (CKSCR:CS1, CS0).
● Machine clock
This clock is an operating clock for the CPU and the resources. One cycle of the machine clock is a
machine cycle (1/φ). One clock can be selected from the main clock subclock, and four types of PLL clock.
Note:
114
When the operating voltage is 5 V, the oscillation clock can oscillate at 3 MHz to 16 MHz. The maximum
operating frequency of the CPU or resources is 16 MHz. If a multiplication rate that exceeds the
maximum operating frequency is set, the device does not operate normally. If the oscillation clock is 16
MHz, the multiplication rate of PLL clock can only be set to x1. The PLL oscillator oscillates in the range
of 3 MHz to 16 MHz, which varies depending on the operating voltage and multiplication rate.
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CHAPTER 3 CPU
3.7 Clocks
MB90495G Series
■ Clock Supply Map
Machine clocks generated by the clock generation section are supplied as operating clocks of the CPU and
resources. The operation of the CPU and resources is affected by switching between the main clock,
subclock, and PLL clock (clock mode) or by switching the multiplication rate of PLL clock. The clockdivided output of the timebase timer is supplied to some resources, and the operating clock can be selected
for each resource.
Figure 3.7-1 shows the clock supply map.
Figure 3.7-1 Clock Supply Map
Resources
4
4
Watchdog timer
Watch timer
8-/16- bit
PPG timer 0, 1
Timebase timer
8-/16- bit
PPG timer 2, 3
Clock generation section
X0A
Pin
1 2 3 4
16-bit reload
timer 0
PLL multiplying circuit
X0
Pin
X1
Pin
PPG2,3
Pin
TIN0
Pin
Subclock
generator
X1A
Pin
PPG0,1
Pin
4-devided
clock
SCLK
PCLK
Oscillation
2-devided
clock
Clock selector
clock
generator HCLK
MCLK
φ
UART0
TOT0
Pin
SIN0
Pin
SCK0
Pin
SOT0
Pin
Communucation prescaler 0
CPU intermittent
operation
Communucation prescaler 1
CPU
UART1
SCK1
Pin
SOT1
Pin
SIN1
Pin
TIN1
Pin
16-bit reload
timer 1
TOT1
Pin
ADTG
Pin
8-/10- bit
A/D converter
IN0,1,2,3
Pin
Input capture unit
16-bit free-run timer
HCLK
MCLK
PCLK
SCLK
φ
CM44-10114-7E
:
:
:
:
:
Oscillation clock
Main clock
PLL clock
Subclock
Machine clock
CAN controller
3
FRCK
Pin
RX
Pin
TX
Pin
Oscillation stabilization
wait control
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3.7 Clocks
MB90495G Series
Block Diagram of Clock Generation Section
3.7.1
The clock generation section consists of the following five blocks:
• Oscillation clock generator/subclock generator
• PLL multiplying circuit
• Clock selector
• Clock select register (CKSCR)
• Oscillation stabilization wait time selector
■ Block Diagram of Clock Generation Section
Figure 3.7-2 shows the block diagram of the clock generation section.
It also includes the standby controller and timebase timer circuit.
Figure 3.7-2 Block Diagram of Clock Generation Section
Standby controller
Low-power consumption mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0
Reserved
2
CPU intermittent
operation cycle
selector
CPU clock
controller
CPU
operating
clock
Watch mode
Sleep signal
Stop signal
Resource clock
controller
S
Q
S
R
S
Reset
Interrupt
Machine clock
R
S
Q
Resource
operating
clock
Q
Q
R
R
Operating
clock
selector
2
Oscillation
stabilization wait
time selector
2
PLL multiplying
circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock select register (CKSCR)
X0
Pin
X1
Pin
Oscillation
clock
Oscillation clock (HCLK)
generator
X0A
Pin
X1A
Pin
2-devided
clock
1024-devided
clock
Main
clock
2-devided
clock
4-devided
clock
2-devided
clock
2-devided
clock
2-devided
clock
2-devided
clock
Timebase timer
Subclock
4-devided
clock
2-devided
clock
To watchdog timer
1024-devided
clock
8-devided
clock
2-devided
clock
2-devided
clock
Watch timer
Subclock generator
S: Set
R: Reset
Q: Output
116
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CHAPTER 3 CPU
3.7 Clocks
MB90495G Series
● Oscillation clock generator
This generator generates an oscillation clock (HCLK) by connecting an oscillator or inputting an external
clock to the high-speed oscillation pins.
● Subclock generator
This generator generates a subclock (SCLK) by connecting an oscillator or inputting an external clock to
the low-speed oscillation pins (X0A, X1A).
● PLL multiplying circuit
This circuit multiplies the oscillation clock and supplies it as a PLL clock (PCLK) to the clock selector.
● Clock selector
This selector selects the clock that is supplied to the CPU or resources from the main clock, subclock, and
four types of PLL clock.
● Clock select register (CKSCR)
This register selects between the oscillation clock and the PLL clock, between the main clock and the
subclock, the oscillation stabilization wait time, and the multiplication rate of the PLL clock.
● Oscillation stabilization wait time selector
This selector selects the oscillation stabilization wait time of the oscillation clock. There are four timebase
timer outputs to select.
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3.7 Clocks
3.7.2
MB90495G Series
Register in Clock Generation Section
This section explains the register in the clock generation section.
■ Register in Clock Generation Section and List of Reset Values
Figure 3.7-3 Clock Select Register and List of Reset Values
bit
Clock select register (CKSCR)
118
15
14
13
12
11
10
9
8
1
1
1
1
1
1
0
0
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CM44-10114-7E
CHAPTER 3 CPU
3.7 Clocks
MB90495G Series
3.7.3
Clock Select Register (CKSCR)
The clock select register (CKSCR) switches between the main clock, subclock, and PLL
clock, selects the oscillation stabilization wait time and the multiplication rate of PLL
clock.
■ Configuration of Clock Select Register (CKSCR)
Figure 3.7-4 Clock Select Register (CKSCR)
15
14
R/W
R
13
12
11
10
9
8
Reset value
11111100 B
R/W R/W R/W R/W R/W R/W
bit 9 bit 8
CS1 CS0
Multiplication rate select bits
The parenthesized values are provided when the oscillation clock (HCLK) operates at 4 MHz
0
0
1 × HCLK (4 MHz)
0
1
2 × HCLK (8 MHz)
1
0
3 × HCLK (12 MHz)
1
1
4 × HCLK (16 MHz)
bit 10
MCS
PLL clock select bit
The PLL clock selected
0
1
The main clock selected
bit 11
SCS
Subclock select bit
0
The subclock selected
1
The main clock selected
bit 13 bit 12
WS1 WS0
Oscillation stabilization wait time select bits
The parenthesized values are provided when the oscillation clock (HCLK) operates at 4 MHz
0
0
210/HCLK (approx. 256 μs)
0
1
213/HCLK (approx. 2.05 ms)
1
0
215/HCLK (approx. 8.19 ms)
1
1
217/HCLK (approx.32.77 ms, except power on reset)
218/HCLK (approx. 65.54 ms, only power on reset)
bit 14
PLL clock flag bit
MCM
0
Operating on the PLL clock
1
Operating on the main clock or subclock
HCLK : Oscillation clock
R/W : Read/Write
R
: Read only
: Reset value
CM44-10114-7E
bit 15
Subclock flag bit
SCM
0
Operating on the subclock
1
Operating on the main clock or PLL clock
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3.7 Clocks
MB90495G Series
Table 3.7-1 Function of Each Bit of Clock Select Register (CKSCR) (1 / 2)
Bit Name
120
Function
bit 9
bit 8
CS1, CS0:
Multiplication rate select
bits
These bits are used to select the multiplication rate of the PLL clock from four types.
When reset, they all return to their reset value.
Note:
When the PLL clock is selected (CKSCR:MCS = 0), writing is inhibited. When
changing the multiplication rate, write 1 to the PLL clock select bit (CKSCR:MCS),
rewrite the multiplication rate select bits (CKSCR:CS1, CS0), and then return the
PLL clock select bit (CKSCR:MCS) to "0".
bit 10
MCS:
PLL clock select bit
This bit sets where to select the main clock or PLL clock as a machine clock.
If the machine clock is switched from the main clock to the PLL clock (CKSCR:MCS = 1
--> 0), the oscillation stabilization wait time of the PLL clock is generated and then the
mode transits to the PLL clock mode. The timebase timer is automatically cleared. When
the main clock mode is switched to PLL clock, the oscillation stabilization wait time is
fixed to 214/HCLK (approximately 4.1 ms when the oscillation clock operates at 4 MHz).
When subclock mode is switched to PLL clock, the oscillation stabilization wait time uses
the specified values in the oscillation stabilization wait time selection bits (CKSCR:WS1,
WS0).
When reset, this bit returns to its reset value.
Notes:
1. If both the MCS and SCS bits are 0, the SCS bit is preferred and the subclock mode is
set.
2. When switching the machine clock from the main clock to the PLL clock
(CKSCR:MCS = 1 --> 0), use the interrupt enable bit of the timebase timer
(TBTC:TBIE) or the interrupt level mask register (ILM:ILM2 to ILM0) to disable the
timebase timer interrupts.
bit 11
SCS:
Subclock select bit (sub)
This bit sets whether to select main clock or subclock as machine clock.
• When the machine clock is switched from the main clock to the subclock
(CKSCR:SCS = 1 --> 0), the main clock mode transits to the subclock mode in
synchrony with the subclock (approximately 130 μs).
• When the machine clock is switched from the subclock to the main clock
(CKSCR:SCS = 0 --> 1), the subclock mode transits to the main clock mode after the
main clock oscillation stabilization wait time is generated. The timebase timer is
automatically cleared.
When reset, this bit returns to its reset value.
Notes:
1. If both the MCS and SCS bits are 0, the SCS bit is preferred and the subclock mode is
set.
2. If both the subclock select bit (CKSCR:MCS) and PLL clock select bit (CKSCR:SCS)
are 0, the subclock is preferred.
3. When switching the machine clock from the main clock to the subclock (CKSCR:SCS
= 1 --> 0), use the interrupt enable bit of the timebase timer (TBTC:TBIE) or the
interrupt level mask register (ILM:ILM2 to ILM0) to disable the timebase timer.
4. At power on or when the stop mode is cancelled, the subclock oscillation stabilization
wait time (approximately 2 s) is generated. Therefore, if the mode is switched from the
main clock mode to the subclock mode, the oscillation stabilization wait time is
generated.
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CM44-10114-7E
CHAPTER 3 CPU
3.7 Clocks
MB90495G Series
Table 3.7-1 Function of Each Bit of Clock Select Register (CKSCR) (2 / 2)
Bit Name
Function
bit 13
bit 12
WS1, WS0:
Oscillation stabilization
wait time select bits
These bits select an oscillation stabilization wait interval of the oscillation clock when
stop mode was released, when transition occurred from subclock mode to main clock
mode, or when transition occurred from subclock mode to PLL clock mode.
• These bits are used to select from four timebase timer outputs.
When reset, they all return to their reset value.
Note:
Set an oscillation stabilization wait time appropriate for an oscillator. For details, see
Section "3.6.1 Reset Factors and Oscillation Stabilization Wait Time".
When the main clock mode is switched to PLL clock, the oscillation stabilization wait
time is fixed to 214/HCLK (approximately 4.1 ms when the oscillation clock operates
at 4 MHz). When subclock mode is switched to PLL clock or when PLL stop mode is
returned to PLL clock mode, the oscillation stabilization wait time uses the specified
values in the WS1 and WS0 bits. For PLL clock oscillation stabilization wait time, at
least 214 /HCLK is required. Accordingly, when subclock mode is switched to PLL
clock mode, or when PLL clock mode is switched to PLL stop mode, set WS1 and
WS0 bits to "10B" or "11B".
bit14
MCM:
PLL clock flag bit
This bit indicates whether to select main clock or PLL clock as machine clock.
• If the PLL clock flag bit (CKSCR:MCM) is 1 and the PLL clock select bit
(CKSCR:MCS) is 0, it indicates that the oscillation stabilization wait time of the PLL
clock is taken.
• Writing this bit has no effect on operation.
bit 15
SCM:
Subclock flag bit
This bit indicates whether to select main clock or the subclock as the machine clock.
• If the subclock flag bit (CKSCR:SCM) is 0 and the subclock select bit (CKSCR:SCS)
is 1, it indicates that the subclock switches to the main clock. If the subclock flag bit
(CKSCR:SCM) is 1 and the subclock select bit (CKSCR:SCS) is 0, it indicates that the
main clock switches to the subclock.
• Writing this bit has no effect on operation.
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CHAPTER 3 CPU
3.7 Clocks
3.7.4
MB90495G Series
Clock Mode
Clock modes have a main clock mode, subclock mode, and PLL clock mode.
■ Clock Mode
● Main clock mode
In the main clock mode, a clock with 2-frequency division of the clock generated by connecting an
oscillator or inputting an external clock to the high-speed oscillation pins (X0, X1) is used as the operating
clock for the CPU or resources.
● Subclock mode
In the subclock mode, a clock with 4-frequency division of the clock generated by connecting an oscillator
or inputting an external clock to the low-speed oscillation pins (X0A, X1A) is used as the operating clock
for the CPU or resources.
● PLL clock mode
In the PLL clock mode, the oscillation clock multiplied by the PLL clock multiplying circuit (PLL
oscillator circuit) is used as the operating clock for the CPU or resources. The PLL clock multiplication rate
can be set using the clock select register (CKSCR:CS1, CS0).
■ Transition of Clock Mode
In clock modes, the setting of the PLL clock select bit (CKSCR:MCS) and subclock select bit
(CKSCR:SCS) transits to the main clock mode, subclock mode or PLL clock mode.
● Transition from main clock mode to PLL clock mode
If the PLL clock select bit (CKSCR:MCS) is rewritten from 1 to 0, the main clock switches to the PLL
clock after the PLL oscillation stabilization wait time (214/HCLK) has elapsed.
● Transition from PLL clock mode to main clock mode
If the PLL clock select bit (CKSCR:MCS) is rewritten from 0 to 1, the PLL clock switches to the main
clock when the edge of the PLL clock matches the edge of the main clock (after 1 to 8 PLL clocks).
● Transition from main clock mode to subclock mode
If the subclock select bit (CKSCR:SCS) is rewritten from 1 to 0, the main clock switches to the subclock
synchronizing the sub-clock (approx 130 μs).
● Transition from subclock mode to main clock mode
When the subclock select bit (CKSCR:SCS) is rewritten from 0 to 1, the subclock switches to the main
clock after the main clock oscillation stabilization wait time has elapsed.
122
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MB90495G Series
● Transition from PLL clock mode to subclock mode
When the subclock select bit (CKSCR:SCS) is rewritten from 1 to 0, the PLL clock switches to the
subclock.
● Transition from subclock mode to PLL clock mode
When the subclock select bit (CKSCR:SCS) is rewritten from 0 to 1, the subclock switches to the PLL
clock after the main clock oscillation stabilization wait time has elapsed.
■ Selection of PLL Clock Multiplication Rate
The PLL clock multiplication rate can be set from x1 to x4 by writing values of "00B" to "11B" to the
multiplication rate select bits (CKSCR:CS1, CS0).
■ Machine Clock
The PLL clock, main clock, and subclock output from the PLL multiplying circuit are used as machine
clocks supplied to the CPU or resources.
Any of the main clock, PLL clock, and subclock can be selected by writing to the subclock select bit
(CKSCR:SCS) and the PLL clock select bit (CKSCR:MCS).
Notes:
• The machine clock is not switched immediately even when the PLL clock select bit (CKSCR:MCS)
and the subclock select bit (CKSCR:SCS) are rewritten. When running resources that depend on the
machine clock, after switching the machine clock, reference the value of the PLL clock flag bit
(CKSCR:MCM) or the subclock flag bit to check that the machine clock has been switched.
• When the PLL clock select bit (CKSCR:MCS) is 0 (PLL clock mode) and the subclock select bit
(CKSCR:SCS) is 0 (subclock mode), the SCS bit the SCS bit is preferred, transiting to the subclock
mode.
• When transiting a clock mode, do not transit a clock mode to any other clock mode or a low-power
consumption mode until the completion of transition. Reference the MCM and SCM bits in the clock
select register (CKSCR) to check that the transition of a clock mode is completed. If the mode is
switched to another clock mode or low-power-consumption mode before completion of switching, the
mode may not be switched.
Figure 3.7-5 shows the transition of a clock mode.
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CHAPTER 3 CPU
3.7 Clocks
MB90495G Series
Figure 3.7-5 Clock Mode Transition
Main → Sub
MCS = 1
MCM = 1
(9)
SCS = 0
(10)
SCM = 1
CS1,CS0 = xx
(8)
Main
MCS = 1
MCM = 1
SCS = 1
(1)
SCM = 1
CS1,CS0 = xx
Sub
MCS = 1
MCM = 1
(16) SCS = 0
(10) SCM = 0
CS1,CS0 = xx
(11) Sub → Main
MCS = 1
(8)
MCM = 1
SCS = 1
(6)
(8)
SCM = 0
(12) Sub → PLL
Main → PLLx (2)
CS1,CS0 = xx
MCS = 0
(3)
(13) MCS = 0
MCM = 1
MCM = 1
(4)
(14)
SCS = 1
SCS = 1
(5)
(15) SCM = 0
SCM = 1
CS1,CS0 = xx
CS1,CS0 = xx
124
PLL1 → Main
MCS = 1
(7) MCM = 0
SCS = 1
SCM = 1
CS1,CS0 = 00
PLL1 multiplication
MCS = 0
MCM = 0
(6) SCS = 1
(8)
SCM = 1
CS1,CS0 = 00
PLL1 → Sub
MCS = 1
(17)
MCM = 0
SCS = 0
SCM = 1
CS1,CS0 = 00
PLL2 → Main
MCS = 1
(7) MCM = 0
SCS = 1
SCM = 1
CS1,CS0 = 01
PLL2 multiplication
MCS = 0
MCM = 0
(6) SCS = 1
(8)
SCM = 1
CS1,CS0 = 01
PLL2 → Sub
MCS = 1
(17)
MCM = 0
SCS = 0
SCM = 1
CS1,CS0 = 01
PLL3 → Main
MCS = 1
(7) MCM = 0
SCS = 1
SCM = 1
CS1,CS0 = 10
PLL3 multiplication
MCS = 0
MCM = 0
(6) SCS = 1
(8)
SCM = 1
CS1,CS0 = 10
PLL3 → Sub
MCS = 1
(17)
MCM = 0
SCS = 0
SCM = 1
CS1,CS0 = 10
PLL4 → Main
MCS = 1
(7) MCM = 0
SCS = 1
SCM = 1
CS1,CS0 = 11
PLL4 multiplication
MCS = 0
MCM = 0
(6) SCS = 1
(8)
SCM = 1
CS1,CS0 = 11
PLL4 → Sub
MCS = 1
(17)
MCM = 0
SCS = 0
SCM = 1
CS1,CS0 = 11
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 3 CPU
3.7 Clocks
MB90495G Series
(1) 0 write to MCS bit
(2) PLL clock oscillation stabilization waiting termination & CS1, CS0 = 00
(3) PLL clock oscillation stabilization waiting termination & CS1, CS0 = 01
(4) PLL clock oscillation stabilization waiting termination & CS1, CS0 = 10
(5) PLL clock oscillation stabilization waiting termination & CS1, CS0 = 11
(6) 1 write to MCS bit (hardware standby and the watchdog reset included)
(7) Synchronous timing of PLL clock and main clock
(8) 0 write to SCS bit
(9) Subclock oscillation stabilization wait time termination (214/SCLK)
(10) 1 write to SCS bit
(11) Main clock oscillation stabilization waiting termination
(12) Main clock oscillation stabilization waiting termination & CS1, CS0 = 00
(13) Main clock oscillation stabilization waiting termination & CS1, CS0 = 01
(14) Main clock oscillation stabilization waiting termination & CS1, CS0 = 10
(15) Main clock oscillation stabilization waiting termination & CS1, CS0 = 11
(16) 1 write to SCS bit and 0 to MCS bit
(17) Synchronous timing of PLL clock and subclock
MCS
MCM
SCS
SCM
CS1,CS0
Notes:
CM44-10114-7E
: PLL clock select bit of clock select register (CKSCR)
: PLL clock display bit of clock select register (CKSCR)
: Subclock select bit of clock select register (CKSCR)
: Subclock display bit of clock select register (CKSCR)
: Multiplication rate select bit of clock select register (CKSCR)
• The reset value of the machine clock is in the main clock mode (MCS = 1, SCS = 1)
• When SCS and MCS are both 0, SCS is preferred, and the subclock is selected.
• When transiting from the subclock mode to the PLL clock mode, set the oscillation stabilization wait
time select bit of the CKSCR register (WS1, WS0) to 10B or 11B.
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CHAPTER 3 CPU
3.7 Clocks
3.7.5
MB90495G Series
Oscillation Stabilization Wait Time
At power on or return from the stop mode when the oscillation clock is stopped, a time
taken until the oscillation clock stabilizes (oscillation stabilization wait time) is required
after starting an oscillation. The oscillation stabilization wait time is also required for
switching the clock mode from main clock mode to PLL clock mode, from main clock
mode to subclock mode, from subclock mode to main clock mode, and from subclock
mode to PLL clock mode.
■ Operation During Oscillation Stabilization Wait Time
Ceramic and crystal oscillators require some tens of milliseconds to reach a stable oscillation frequency
after starting oscillation. Therefore when, immediately after an oscillation starts, once the CPU operation is
disabled and then an oscillation stabilizes after the elapse of oscillation stabilization wait time, the machine
clock is supplied to the CPU.
The oscillation stabilization wait time varies with the type of oscillator (ceramic, crystal, etc.).
It is necessary to select a oscillation stabilization wait time appropriate to an oscillator to be used.
The oscillation stabilization wait time can be selected using the clock select register (CKSCR).
When clock mode is switched from main clock to PLL clock, main clock to subclock, subclock to main
clock, or subclock to PLL clock, the CPU runs in the clock mode set before switching for the oscillation
stabilization wait time. After the oscillation stabilization wait time has elapsed, the CPU changes to the
specified clock mode. Figure 3.7-6 shows the oscillating operation immediately after it starts.
Figure 3.7-6 Operation after Oscillation Stabilization Wait Time
Oscillation time
of oscillator
Oscillation
stabilization wait time
Starting of normal
operation or transiting to
PLL clock/subclock
X1
The oscillation started
126
The oscillation stabilized
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 3 CPU
3.7 Clocks
MB90495G Series
3.7.6
Connection of Oscillator and External Clock
The MB90495G series has a system clock generator and generates an internal clock by
connecting an oscillator to the oscillation pins. External clocks input to the oscillation
pins can be used as oscillation clocks.
■ Connection of Oscillator and External Clock
● Example of connection of crystal oscillator or ceramic oscillator
Figure 3.7-7 Example of Connection of Crystal Oscillator or Ceramic Oscillator
X0
X1
C1
C2
MB90495G series
X0A
X1A
C3
C4
● Example of connection of external clock
Figure 3.7-8 Example of Connection of External Clock
X0
~
Open
X1
MB90495G series
X0A
~
CM44-10114-7E
Open
X1A
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CHAPTER 3 CPU
3.8 Low-power Consumption Mode
3.8
MB90495G Series
Low-power Consumption Mode
The CPU operation modes are classified as follows according to the selection of the
operation clock and the oscillation control of a clock. All the operation modes except
the PLL clock mode are low-power consumption modes.
• Clock modes (main clock, PLL clock and subclock modes)
• CPU intermittent operation modes (main clock, PLL clock, and subclock modes)
• Standby modes (sleep, stop, watch, and timebase timer modes)
■ CPU Operation Modes and Current Consumption
Figure 3.8-1 shows the relationships between the CPU operation mode and current consumption.
Figure 3.8-1 CPU Operation Mode and Current Consumption
Current consumption
High
CPU operation
mode
PLL clock mode
4-multiplied clock
3-multiplied clock
2-multiplied clock
1-multiplied clock
PLL clock intermittent operation mode
4-multiplied clock
3-multiplied clock
2-multiplied clock
1-multiplied clock
Main clock mode (21/HCLK)
Main clock intermittent operation mode
Subclock mode (SCLK)
Subclock intermittent operation mode
Standby mode
Sleep mode
Watch mode
Timebase timer mode
Stop mode
Low
Low-power consumption mode
Note: This figure shows an image of operation mode.
So the current consumption shown above may be different from the actual one .
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■ Clock Mode
● PLL clock mode
In PLL clock mode, the CPU and resources operate on a PLL multiplying clock of oscillation clock
(HCLK).
● Main clock mode
In main clock mode, the CPU and resources operate on a clock with 2-frequency division of oscillation
clock (HCLK). In this mode, the PLL multiplying circuit stops.
● Subclock mode
In subclock mode, the CPU and resources operate on a subclock (SCLK). In this mode, the main clock and
PLL multiplying circuit stop.
The subclock oscillation stabilization wait time (approximately 2 s) is generated at power on or at
cancellation of the stop mode. Therefore, if the clock mode transits from the main clock mode to the
subclock mode during that period, the oscillation stabilization wait time is generated.
For the clock mode, see Section "3.7 Clocks".
■ CPU Intermittent Operation Mode
In CPU intermittent operation mode, the CPU performs the intermittent operation with the high-speed clock
supplied to the resource to reduce the power consumption. In this mode, the intermittent clock is input to
only the CPU at accessing registers, internal memory, resources, or at the external access.
■ Standby Mode
The standby mode causes the standby control circuit to stop the supply of an operation clock to the CPU or
resources or to stop the oscillation clock (HCLK) in order to reduce power consumption.
● Sleep mode
The sleep mode stops supply of an operation clock to the CPU during operation in each clock mode. The
CPU stops and the resources operate in the clock mode before the transition to the sleep mode. The sleep
mode is divided into the main sleep mode, PLL sleep mode, and sub-sleep mode according to the clock
mode before the transition to the sleep mode.
● Watch mode
The watch mode operates only the subclock (SCLK) and watch timer. The main clock and PLL clock stop.
All resources except the watch timer stop.
● Timebase timer mode
The timebase timer mode operates only the oscillation clock (HCLK), subclock (SCLK), timebase timer,
and watch timer. Resources other than the timebase timer and watch timer stop.
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● Stop mode
The stop mode stops the oscillation clock (HCLK) and subclock (SCLK) during operation in each clock
mode. It enables data to be retained with the least power consumption.
Note:
130
When transiting a clock mode, do not transit a clock mode to any other clock mode or a low-power
consumption mode until the completion of transition. Reference the MCM and SCM bits in the clock
select register (CKSCR) to check that the transition of a clock mode is completed. If the mode is switched
to another clock mode or low-power-consumption mode before completion of switching, the mode may
not be switched.
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3.8 Low-power Consumption Mode
MB90495G Series
3.8.1
Block Diagram of Low-power Consumption Circuit
This section shows block diagram of low-power consumption circuit.
■ Block Diagram of Low-power Consumption Circuit
Figure 3.8-2 Block Diagram of Low-power Consumption Circuit
Low-power consumption mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0
Reserved
Pin high
impedance
controller
Pin Hi-Z control
Internal reset
generator
RST Pin
CPU intermittent
operation
cycle selector
Intermittent cycle selected
CPU clock
controller
Reset
(cancellation)
Intrerrupt
(cancellation)
CPU operating clock
Timer and sleep, stop signal
Standby
controller
2
Internal reset
Timer and stop signal
Resource
Resource
clock
operating clock
controller
Clock
generation
section
Subclock oscillaton stabilization waiting cancelled
Main clock oscillaton stabilization waiting cancelled
Operating
clock
selector
Machine clock
Oscillation
stabilization wait
time selector
2
2
PLL multiplying
circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock select register (CKSCR)
X0 Pin
X1 Pin
2-devided
clock
1024-devided
2-devided
clock
clock
Main
Oscillator
clock
clock (HCLK)
Timebase timer
Oscillation clock
Subclock
oscillator
(SCLK)
4-devided
clock
X0A Pin
1024-devided
clock
4-devided
clock
2-devided
clock
2-devided
clock
2-devided
clock
2-devided
clock
2-devided
clock
To watchdog timer
8-devided
clock
2-devided
clock
2-devided
clock
Watch timer
X1A Pin
Subclock oscillator
● CPU intermittent operation selector
This selector selects the halt cycle count of the CPU clock in the CPU intermittent operation mode.
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● Standby controller
This controller causes the CPU clock controller and resource clock controller to switch between the CPU
operating clock and the resource operating clock, and to transits a clock mode to, and cancel the standby
mode.
● CPU clock controller
This controller supplies an operating clock to the CPU.
● Pin high-impedance controller
This controller causes the input/output pins to become high impedance in the watch mode, timebase timer
mode, and stop mode.
● Internal reset generator
This generator generates the internal reset signal.
● Low-power consumption mode control register (LPMCR)
This register transits a clock mode to, and cancels the standby mode, and sets the CPU intermittent
operation mode.
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3.8.2
Registers for Setting Low-power Consumption Modes
This section explains the registers to be used to set lower-power consumption modes.
■ Low-power Consumption Mode Control Register and Reset Values
Figure 3.8-3 Low-power Consumption Mode Control Register and Reset Values
bit
Low-power consumption mode control register (LPMCR)
CM44-10114-7E
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0
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Low-power Consumption Mode Control Register
(LPMCR)
3.8.3
The low-power consumption mode control register (LPMCR) transits an operation mode
to, and cancels the low-power consumption modes, generates an internal reset signal,
and sets the halt cycle count in the CPU intermittent operation mode.
■ Low-power Consumption Mode Control Register (LPMCR)
Figure 3.8-4 Low-power Consumption Mode Control Register (LPMCR)
7
6
5
4
3
W
W
R/W
W
W
2
1
0
Reset value
00011000 B
R/W R/W R/W
bit 0
Reserved bit
Reserved
0
Always set to "0"
bit 2 bit 1
CG1 CG0
0
0 cycle (CPU clock = resource clock)
0
1
8 cycles (CPU clock: resource clock = 1: approx. 3 to 4)
1
0
16 cycles (CPU clock: resource clock = 1: approx. 5 to 6)
1
1
32 cycles (CPU clock: resource clock = 1: approx. 9 to 10)
bit 3
TMD
0
1
Transits to watch mode or timebase timer mode
No effect
bit 4
RST
0
1
Generates internal reset signal of 3 machine cycles
No effect
bit 5
SPL
0
1
bit 6
SLP
0
1
bit 7
STP
R/W : Read/Write
W
: Write only
: Reset value
134
CPU halt cycle count select bits
0
0
1
Timer mode bit
Internal reset signal generate bit
Pin state specify bit
Holds input/output pin state
High impedance
Only in the timebase timer, watch, and stop modes
Sleep mode bit
No effect
Transits to sleep mode
Stop mode bit
No effect
Transits to stop mode
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MB90495G Series
Table 3.8-1 Function of Each Bit of Low-power Consumption Mode Control Register
(LPMCR)
Bit Name
CM44-10114-7E
Function
bit 0
Reserved bit
Always set this bit to 0.
bit 1
bit 2
CG1, CG0:
CPU halt cycle count
select bit
These bits are used to set the halt cycle count of the CPU clock
in the CPU intermittent operation mode.
bit 3
TMD:
Timer mode bit
This bit is used to transit the operation mode to the watch
mode or the timebase timer mode.
When set to 0: The mode transits to the watch mode.
When set to 1: Not effect
• This bit is set to 1 by a reset or interrupt.
Read: 1 is always read.
bit 4
RST:
Internal reset signal
generate bit
This bit is used to generate a software reset.
When set to 0:Three machine cycles of internal reset signals
are generated.
When set to 1: No effect
Read: 1 is always read.
bit 5
SPL:
Pin state specify bit
This bit is used to set the state of input/output pins in transiting
to the stop mode, watch mode or timebase timer mode.
When set to 0:The current level of input/output pins is held.
When set to 1:The input/output pins are set to high
impedance.
• This bit is initialized to 0 by a reset.
bit 6
SLP:
Sleep mode bit
This bit is used to transit the mode to the sleep mode.
When set to 0: No effect
When set to 1: The mode transits to the sleep mode.
• This bit is initialized to 0 by a reset or external interrupt.
• When both the STP and SLP bits are set to 1
simultaneously, the STP bit is preferred and the mode
transits to the stop mode.
bit 7
STP:
Stop mode bit
This bit is used to transit the mode to the stop mode.
When set to 0: No effect
When set to 1: The mode is transits to the stop mode.
When read: 1 is always read.
• This bit is initialized to 0 by a reset or external interrupt.
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Notes:
MB90495G Series
• When transiting to a low-power consumption mode using the low-power consumption mode control
register (LPMCR), use the instructions listed in Table 3.8-2.
• The low-power consumption mode transition instruction in table 3.8-2 must always be followed by an
array of instructions highlighted by a dotted line below.
MOV
LPMCR,#H'XX ; the low-power consumption mode transition instruction in table 3.8-2
NOP
NOP
JMP
$+3
; jump to next instruction
MOV
A,#H'10
; any instruction
The devices does not guarantee its operation after returning from the standby mode if you place an
array of instructions other than the one enclosed in the dotted line.
• To access the low-power consumption mode control register (LPMCR) with C language, refer to
"■Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to Enter the
Standby Mode" in the section 3.8.8 "Notes on Using the Low-Power Consumption Mode".
• When word-length is used for writing the low-power consumption mode control register, even
addresses must be used. Using odd addresses to switch to a low-power consumption mode may result
in a malfunction.
• To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode,
watch mode or timebase timer mode, disable the output of peripheral functions, and set the STP bit of
the low-power consumption mode control register (LPMCR) to 1 or set the TMD bit to 0.
This applies to the following pins:
P14/PPGO/AD12, P15/PPG1/AD13, P16/PPG2/AD14, P17/PPG3/AD15, P21/TOT0/A17,
P23/TOT1/A19, P30/SOT0/ALE, P31/SCK0/RD
Table 3.8-2 Instructions at Transition to Low-power Consumption Mode
MOV io,#imm8
MOV dir,#imm8
MOV eam,#imm8
MOV eam,Ri
MOV io,A
MOV dir,A
MOV addr16,A
MOV eam,A
MOVW io,#imm16
MOVW dir,#imm16
MOVW eam,#imm16
MOVW eam,RWi
MOVW io,A
MOVW dir,A
MOVW addr16,A
MOVW eam,A
SETB io:bp
SETB dir:bp
SETB addr16:bp
CLRB io:bp
CLRB dir:bp
CLRB addr16:bp
MOV @RLi+disp8,A
MOVW @RLi+disp8,A
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3.8.4
CPU Intermittent Operation Mode
The CPU intermittent operation mode causes the CPU to operate intermittently with an
operating clock supplied to the CPU or resources to reduce power consumption.
■ Operation in CPU Intermittent Operation Mode
The CPU intermittent operation mode halts the clock supplied to the CPU at every instruction execution
when the CPU accesses registers, internal memory, I/O, resources, or external buses, delaying to start the
internal bus. Decreasing the CPU processing speed while supplying a high-speed clock to resources reduces
the power consumption.
• The count of machine cycles in which clock supply to the CPU halts is set by the CG1 and CG0 bits in
the low-power consumption mode control register (LPMCR).
• The instruction execution time in the CPU intermittent operation mode is determined by adding the
"normal execution time" to the "compensation value" obtained by multiplying "count of accesses to
registers, internal memory, resources, and external buses" by "halt cycle count."
Figure 3.8-5 shows the clock operation in the CPU intermittent operation mode.
Figure 3.8-5 Clock Operation in CPU Intermittent Operation Mode
Resource clock
CPU clock
A instruction
execution
cycle
Halt cycle
Starting of internal bus
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3.8.5
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Standby Mode
The standby mode causes the standby control circuit to either stop supplying an
operation clock to the CPU and resources, or to stop the oscillation clock (HCLK) to
reduce power consumption.
■ Operating State in Each Standby Mode
Table 3.8-3 shows the operating state in each standby mode.
Table 3.8-3 Operating State in Each Standby Mode
Mode Name
Sleep mode
Timebase
timer mode
Subclock
(SCLK)
Machine
Clock
CPU
Resource
Pin
Cancellation
MCS = 1
SCS = 1
SLP = 1
O
O
O
X
O
O
External reset or
interrupt
Sub-sleep
mode
MCS = X
SCS = 0
SLP = 1
X
O
O
X
O
O
External reset or
interrupt
PLL sleep
mode
MCS = 0
SCS = 1
SLP = 1
O
O
O
X
O
O
External reset or
interrupt
SPL = 0
MCS = X
SCS = 1
TMD = 0
O
O
X
X
X *1
MCS = X
SCS = 1
TMD = 0
O
O
X
X
X *1
MCS =X
SCS = 0
TMD = 0
X
O
X
X
X *2
MCS = X
SCS = 0
TMD = 0
X
O
X
X
X *2
X
X
X
X
X
X
X
X
X
X
SPL = 0
SPL = 1
Stop mode
Oscillation
Clock
(HCLK)
Main sleep
mode
SPL = 1
Watch mode
Transition
Condition
SPL = 0
SPL = 1
STP = 1
STP = 1
External reset or
interrupt *4
External reset or
Hi-Z *3
interrupt*4
External reset or
interrupt *5
External reset or
Hi-Z *3
interrupt *5
External reset or
interrupt *6
Hi-Z *3
External reset or
interrupt *6
O: Operate X: Stop
: Pre-transition state held Hi-Z: High-impedance
*1: The timebase timer and the watch timer operate.
*2: The watch timer operates
*3: DTP/external interrupt input pins operates
*4: Watch timer, timebase timer, and external interrupt
*5: Watch timer and external interrupt
*6: External interrupt
MCS: PLL clock select bit of clock select register (CKSCR)
CSC: Subclock select bit of CKSCR
SPL: Pin state specify bit of low-power consumption mode control register (LPMCR)
SLP: Sleep mode bit of LPMCR
STP: Stop mode bit of LPMCR
TMD: Watch mode bit of LPMCR
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Note:
CM44-10114-7E
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode,
watch mode or timebase timer mode, disable the output of peripheral functions, and set the STP bit of the
low-power consumption mode control register (LPMCR) to 1 or set the TMD bit to 0.
This applies to the following pins:
P14/PPGO/AD12, P15/PPG1/AD13, P16/PPG2/AD14, P17/PPG3/AD15, P21/TOT0/A17,
P23/TOT1/A19, P30/SOT0/ALE, P31/SCK0/RD
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3.8.5.1
MB90495G Series
Sleep Mode
The sleep mode stops the operating clock to the CPU during an operation in each clock
mode. The CPU stops and the resources continue to operate.
■ Transition to Sleep Mode
When the mode transits to the sleep mode by setting the low-power consumption mode control register
(LPMCR:SLP = 1, STP = 0), the mode transits to the sleep mode according to the settings of the MCS and
SCS bits in the clock select register (CKSCR).
Table 3.8-4 shows the settings of the MCS and SCS bits in the clock select register (CKSCR) and the sleep
modes.
Table 3.8-4 Settings of MCS and SCS Bits in Clock Select Register (CKSCR) and Sleep
Modes
Clock Select Register (CKSCR)
Sleep Mode to be transited
MCS
SCS
1
1
Main sleep mode
0
1
PLL sleep mode
1
0
0
0
Sub-sleep mode
Note:
If both the STP and SLP bits in the low-power consumption mode control register (LPMCR) are set to 1
simultaneously, the STP bit is preferred and the mode transits to the stop mode.
If the SLP bit is set to 1 and the TMD bit is set to 0 at the same time, the TMD bit is preferred and the
mode transits to the timebase timer mode or the watch mode.
● Data hold function
In the sleep mode, data in the dedicated registers such as accumulators and internal RAM are held.
● External bus hold function
In the sleep mode, the external bus hold function is active. If a hold request is generated to the CPU, the
external buses enter the hold state.
● Operation when interrupt request generated
If an interrupt request is generated when the SLP bit in the low-power consumption mode control register
(LPMCR) is set to 1, the mode does not transit to the sleep mode. If the CPU is not ready to accept any
interrupt request, the instruction next to the currently executing instruction is executed. If the CPU is ready
to accept any interrupt request, an interrupt operation immediately branches to the interrupt processing
routine.
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● Pin state
In the sleep mode, pins other than those used for bus input/output or bus control are held in the state before
transiting to the sleep mode.
■ Return from Sleep Mode
The sleep mode is cancelled by a reset factor or when an interrupt is generated.
● Return by reset factor
When the sleep mode is cancelled by a reset factor, the mode transits to the main clock mode after the sleep
mode is cancelled, transiting to the reset sequence.
● Return by interrupt
When a higher interrupt request than the interrupt level (IL) of 7 is generated from the resources in the
sleep mode, the sleep mode is cancelled. After the sleep mode is cancelled, as with normal interrupt
processing, the generated interrupt request is identified according to the settings of the I flag in the
condition code register (CCR), the interrupt level mask register (ILM), and the interrupt control register
(ICR).
• When the CPU is not ready to accept any interrupt request, the instruction next to the currently
executing instruction is executed.
• When the CPU is ready to accept any interrupt request, it branches immediately to the interrupt
processing routine.
Figure 3.8-6 shows the cancellation of sleep mode by an interrupt.
Figure 3.8-6 Cancellation of Sleep Mode by Interrupt
Set interrupt flag of resource
INT generated
(IL<7)
YES
NO
Sleep mode not cancelled
Sleep mode cancelled
YES
I=0
Sleep mode not cancelled
Next instruction executed
NO
YES
ILM<IL
NO
Interrupt processing
executed
Note:
CM44-10114-7E
When an interrupt processing is executed, the CPU usually proceeds to the interrupt processing after
executing the instruction next to the one specifying the sleep mode. When a transition to the sleep mode
is concurrent with acceptance of the external bus hold request, the CPU may proceed to the interrupt
processing before executing the next instruction.
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3.8.5.2
MB90495G Series
Watch mode
The watch mode operates only the subclock (SCLK) and the watch timer. The main
clock and PLL clock stop.
■ Transition to Watch mode
In the subclock mode, when 0 is written to the TMD bit in the LPMCR register according to the settings of
the low-power consumption mode control register (LPMCR), the mode transits to the watch mode.
● Data hold function
In the watch mode, data in the dedicated registers such as an accumulator and internal RAM are held.
● External bus hold function
In the watch mode, the external bus hold function stops. The CPU does not accept any hold request even if
one is input. If a hold request is input during transition to the watch mode, the HAK signal may not become
Low level with the bus in the high-impedance state.
● Operation when interrupt request generated
When interrupt request generated with the TMD bit of the low-power consumption mode control register
(LPMCR) set to 0 the mode does not transit to the watch mode. If the CPU is not ready to accept any
interrupt request, the instruction next to the currently executing instruction is executed. If the CPU is ready
to accept any interrupt request, it immediately branches to the interrupt processing routine.
● Pin state
In the watch mode, the input/output pins can be set to the high-impedance state or held in the state before
transiting to the watch mode according to the setting of the SPL bit in the low-power consumption mode
control register (LPMCR).
Note:
142
To set a pin to high impedance when the pin is shared by a peripheral function and a port in watch mode,
disable the output of peripheral functions, and set the TMD bit of the low-power consumption mode
control register (LPMCR) to 0.
This applies to the following pins:
P14/PPGO/AD12, P15/PPG1/AD13, P16/PPG2/AD14, P17/PPG3/AD15, P21/TOT0/A17,
P23/TOT1/A19, P30/SOT0/ALE, P31/SCK0/RD
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3.8 Low-power Consumption Mode
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■ Return from Watch mode
The watch mode is cancelled by a reset factor or when an interrupt is generated.
● Return by reset factor
When the watch mode is cancelled by a reset factor, the mode transits to the main clock mode after the
watch mode is cancelled, transiting to the reset sequence.
● Return by an interrupt
When an interrupt request higher than the interrupt level (IL) of 7 is generated from the watch timer and
external interrupt in the watch mode, the watch mode is cancelled. After the watch mode is cancelled, as
with normal interrupt processing, the generated interrupt request is identified according to the settings of
the I flag in the condition code register (CCR), the interrupt level mask register (ILM), and the interrupt
control register (ICR). In the sub-timer mode, no oscillation stabilization wait time is generated and the
interrupt request is identified immediately after return from the watch mode.
• When the CPU is not ready to accept any interrupt request, the instruction next to the currently
executing instruction is executed.
• When the CPU is ready to accept any interrupt request, it branches immediately to the interrupt
processing routine.
Note:
CM44-10114-7E
When an interrupt processing is executed, the CPU usually proceeds to the interrupt processing after
executing the instruction next to the one specifying the watch mode. When a transition to the watch mode
is concurrent with acceptance of the external bus hold request, the CPU may proceed to interrupt
processing before executing the next instruction.
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3.8.5.3
MB90495G Series
Timebase Timer Mode
The timebase timer mode operates only the oscillation clock (HCKL), subclock (SCLK),
timebase timer, and watch timer. Resources other than the timebase timer and watch
timer stop.
■ Transition to Timebase Timer Mode
The mode transits to the timebase timer mode when 0 is written to the TMD bit of the low-power
consumption mode control register (LPMCR) during operation in the PLL clock mode or the main clock
mode (CKSCR:SCM = 1).
● Data hold function
In the timebase timer mode, data in the dedicated registers such as an accumulator and internal RAM are
held.
● External bus hold function
In the timebase timer mode, the external bus hold function stops. The CPU does not accept any hold
request even if one is input. When a hold request is input during transition to the timebase timer mode, the
HAK signal may not become Low level with the bus in the high-impedance state.
● Operation when interrupts request generated
When an interrupt request is generated with the TMD bit of the low-power consumption mode control
register (LPMCR) set to 0, the mode does not transit to the timebase timer mode. When the CPU is not
ready to accept any interrupt request, the instruction next to the currently executing instruction is executed.
When the CPU is ready to accept any interrupt request, it branches immediately to the interrupt processing
routine.
● Pin state
In the timebase timer mode, the input/output pins can be set to the high-impedance state or held in the state
before transiting to the timebase timer mode according to the setting of the SPL bit in the low-power
consumption mode control register (LPMCR).
Note:
144
To set a pin to high impedance when the pin is shared by a peripheral function and a port in timebase
timer mode, disable the output of peripheral functions, and set the TMD bit of the low-power
consumption mode control register (LPMCR) to 0.
This applies to the following pins:
P14/PPGO/AD12, P15/PPG1/AD13, P16/PPG2/AD14, P17/PPG3/AD15, P21/TOT0/A17,
P23/TOT1/A19, P30/SOT0/ALE, P31/SCK0/RD
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3.8 Low-power Consumption Mode
MB90495G Series
■ Return from Timebase Timer Mode
The timebase timer mode is cancelled by a reset factor or when an interrupt is generated.
● Return by reset factor
When the timebase timer mode is cancelled by a reset factor, the mode transits to the main clock mode after
the timebase timer mode is cancelled, transiting to the reset sequence.
● Return by an interrupt
When an interrupt request higher than interrupt level (IL) 7 is generated from the watch timer, timebase
timer, and external interrupt in the timebase timer mode, the timebase timer mode is cancelled. After the
timebase timer mode is cancelled, as with normal interrupt processing, the generated interrupt request is
identified according to the settings of the I flag in the condition code register (CCR), the interrupt level
mask register (ILM), and the interrupt control register (ICR).
• When the CPU is not ready to accept any interrupt request, the instruction next to the currently
executing instruction is executed.
• When the CPU is ready to accept any interrupt request, it branches immediately to the interrupt
processing routine.
• The following two timebase timer modes are available:
- Main clock <-- --> timebase timer mode
- PLL clock <-- --> timebase timer mode
Note:
CM44-10114-7E
At interrupt processing, the CPU usually proceeds to the interrupt processing after executing the
instruction next to the one specifying the timebase timer mode. When a transition to the timebase timer
mode is concurrent with acceptance of the external bus hold request, the CPU may proceed to the
interrupt processing before executing the next instruction.
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3.8.5.4
MB90495G Series
Stop Mode
The stop mode stops the oscillation clock (HCLK) and subclock (SCLK) during
operation in each clock mode. Data can be held with the minimum power consumption.
■ Stop Mode
When 1 is written to the STP bit of the low-power consumption mode control register (LPMCR) during
operation in the PLL clock mode, the mode transits to the stop mode according to the settings of the MCS
bit and SCS bit in the clock select register (CKSCR).
Table 3.8-5 shows the settings of the MCS and SCS bits in the clock select register (CKSCR) and the stop
modes.
Table 3.8-5 Settings of MCS and SCS Bits in Clock Select Register (CKSCR) and Stop
Modes
Clock Select Register (CKSCR)
Stop Mode to be Transited
MCS
SCS
1
1
Main stop mode
0
1
PLL stop mode
1
0
0
0
Sub-stop mode
Note:
If both the STP and SLP bits in the low-power consumption mode control register (LPMCR) are set to 1
simultaneously, the STP bit is preferred and the mode transits to the stop mode.
● Data hold function
In the stop mode, data in the dedicated registers such as accumulators and internal RAM are held.
● External bus hold function
In the stop mode, the external bus hold function stops. The CPU does not accept any hold request even if
one is input. If a hold request is input during transiting to the stop mode, the HAK signal may not become
Low level with the bus in the high-impedance state.
● Operation when interrupt request generated
When an interrupt request is generated with the STP bit in the low-power consumption mode control
register (LPMCR) set to 1, the mode does not transit to the stop mode. When the CPU is not ready to accept
any interrupt request, the instruction next to the currently executing instruction is executed. If the CPU is
ready to accept any interrupt request, it immediately branches to the interrupt processing routine.
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● Pin state
In the stop mode, the input/output pins can be set to the high-impedance state or held in the state before
transiting to the stop mode according to the setting of the SPL bit in the low-power consumption mode
control register (LPMCR).
Note:
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode,
disable the output of peripheral functions, and set the STP bit of the low-power consumption mode
control register (LPMCR) to 1.
This applies to the following pins:
P14/PPGO/AD12, P15/PPG1/AD13, P16/PPG2/AD14, P17/PPG3/AD15, P21/TOT0/A17,
P23/TOT1/A19, P30/SOT0/ALE, P31/SCK0/RD
■ Return from Stop Mode
The stop mode is cancelled by a reset factor or when an interrupt is generated. At return from the stop
mode, the oscillation clock (HCLK) stops and the subclock (SCLK), so the stop mode is cancelled after the
elapse of the main clock oscillation stabilization wait time or the subclock oscillation stabilization wait
time.
● Return by reset factor
When the stop mode is cancelled by a reset factor, the main clock oscillation stabilization wait time is
generated. After the termination of the main clock oscillation stabilization wait time, the stop mode is
cancelled, transiting to the reset sequence.
Figure 3.8-7 shows the return from the sub-stop mode by an external reset.
Figure 3.8-7 Return from the Sub-stop Mode by an External Reset
RST pin
Stop mode
Main clock
Oscillation stabilization wait
Oscillating
Subclock
Oscillation stabilization wait
Oscillating
PLL clock
Oscillation stabilization wait
CPU operation clock
CPU operation
Subclock
Stop
Reset sequence
Main clock
Oscillating
PLL clock
Normal processing
Stop mode cancelled
Reset cancelled
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● Return by an interrupt
When an interrupt request higher than the interrupt level (IL) of 7 is generated from external interrupt in the
stop mode, the stop mode is cancelled. In the stop mode, the main clock oscillation stabilization wait time
or the subclock oscillation stabilization wait time is generated after the stop mode is cancelled. After the
stop mode is cancelled, as with normal interrupt processing, the generated interrupt request is identified
according to the settings of the I flag in the condition code register (CCR), the interrupt level mask register
(ILM), and the interrupt control register (ICR).
• When the CPU is not ready to accept any interrupt request, the instruction next to the currently
executing instruction is executed.
• When the CPU is ready to accept any interrupt request, it branches immediately to the interrupt
processing routine.
Notes:
148
• At interrupt processing, the CPU usually proceeds to the interrupt processing after executing the
instruction next to the one specifying the stop mode. When the mode transits to the stop mode and an
external bus hold request is accepted at the same time, the CPU may proceed to interrupt processing
before executing the next instruction.
When changing to PLL stop mode, these bits are set the oscillation stabilization wait time selection
bits (CKSCR:WS1, WS0) in the clock selection register to "10B" or "11B".
• In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL stop
mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock
oscillation stabilization wait time. The oscillation stabilization wait times for the main clock and PLL
clock are counted simultaneously according to the value specified in the oscillation stabilization wait
time selection bits (CKSCR:WS1, WS0) in the clock selection register. The oscillation stabilization
wait time selection bits (CKSCR:WS1, WS0) in the clock selection register must be selected
accordingly to account for the longer of main clock and PLL clock oscillation stabilization wait time.
The PLL clock oscillation stabilization wait time, however, requires 214/HCLK or more. Set the
oscillation stabilization wait time selection bits (CKSCR:WS1, WS0) in the clock selection register to
"10B" or "11B".
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3.8 Low-power Consumption Mode
MB90495G Series
3.8.6
State Transition in Standby Mode
The operating state and state transition in the clock mode and standby mode in the
MB90495G series are shown in the diagram.
■ State Transition Diagram
Figure 3.8-8 State Transition Diagram
Power-on
External reset, watchdog timer reset, and software reset
Power-on reset
Reset
SCS=0
SCS=1
Oscillation stabilization
waiting terminated
Main clock mode
MCS=0
PLL clock mode
MCS=1
SLP=1
Interrupt
Main sleep mode
TMD=0
Interrupt
Timebase timer mode
STP=1
Oscillation stabilization
waiting terminated
Main clock oscillation
stabilization waiting
CM44-10114-7E
Subclock mode
SCS=1
SLP=1
Interrupt
PLL sleep mode
TMD=0
Interrupt
Timebase timer mode
STP=1
Main stop mpde
Interrupt
SCS=0
Interrupt
Sub-sleep mode
TMD=0
Interrupt
Watch mode
STP =1
PLL stop mode
Interrupt
SLP=1
Oscillation stabilization
waiting terminated
Main clock oscillation
stabilization waiting
FUJITSU SEMICONDUCTOR LIMITED
Sub-stop mode
Interrupt
Oscillation stabilization
waiting terminated
Subclock oscillation
stabilization waiting
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3.8.7
MB90495G Series
Pin State in Standby Mode, at Reset
The state of input/output pins in the standby mode and at reset is shown in each access
mode.
■ State of Input/Output Pins (Single Chip Mode)
Table 3.8-6 State of Input/Output Pins (Single-chip Mode)
Stop/Watch/Timebase timer
Pin Name
Sleep
Hold
SPL = 0
Reset
SPL = 1
P07 to P00
P17 to P10
P27 to P20
P37 to P30
P44 to P40
Immediatelypreceding state
held *1
Input cut off/
immediatelypreceding state
held*1
Input cut off/
output Hi-Z *2
Not provided
Input disabled/
output Hi-Z
P57 to P50
P63 to P60
*1: Indicates that state of pins output immediately before entering each standby mode is output as it is or "input disabled".
"State of pins output is output as it is" means that if the resource output is in operation, the state of pins is output
according to the state of the resource and if the state of output pins is output, it is held. "Input disabled" means that no
pin value can be accepted internally because the operation of the input gates of pins is enabled but the internal circuit
stops.
*2: "Input cut off" means that operation of the input gates of pins is disabled and "output Hi-Z" means that the driving of
pin driving transistors is disabled to set pins to the high-impedance state.
Note:
150
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode,
watch mode or timebase timer mode, disable the output of peripheral functions, and set the STP bit of the
low-power consumption mode control register (LPMCR) to 1 or set the TMD bit to 0.
This applies to the following pins:
P14/PPGO/AD12, P15/PPG1/AD13, P16/PPG2/AD14, P17/PPG3/AD15, P21/TOT0/A17,
P23/TOT1/A19, P30/SOT0/ALE, P31/SCK0/RD
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MB90495G Series
■ State of Input/Output Pins (16-bit Access Mode)
Table 3.8-7 State of Input/Output pins (16-bit Access Mode)
Stop/Watch/Timebase timer
Pin Name
Sleep
Hold
SPL = 0
P07 to P00
(AD07 to AD00)
Reset
SPL = 1
Internal ROM
access immediately
after reset
cancellation
Internal ROM
access after
external ROM
access
Input disabled/
output Hi-Z
Input cut off/
output Hi-Z
Input disabled/
output Hi-Z
Input disabled/
output Hi-Z
Output Hi-Z/Input
enabled
Output Hi-Z/Input
enabled
P27 to P20
(A23 to A16)
Output state
Output state
*1,*3
*1,*3
Input disabled/
output Hi-Z *3
Output state *1
Output state(*1)
Maintains the
previous address
P37 (CLK)
Input disabled/
output enabled
Input disabled/
output state *1,*3
Input disabled/
output enabled
Input disabled/
output enabled *2
CLK output
CLK output
Output Hi-Z/Input
enabled
Output Hi-Z/Input
enabled
High output
"H" output
"H" output
Output enabled *2
"L" output
"L" output
Output Hi-Z/Input
enabled
Output Hi-Z/Input
enabled
P17 to P10
(AD15 to AD08)
*2,*3
P36 (RDY)
P35 (HAK)
Immediatelypreceding state
held *4
P34 (HRQ)
Input cut off/
immediatelypreceding state
held *4
P33 (WRH)
High output *3
High output *3
P32 (WRL)
P31 (RD)
High output
High output
P30 (ALE)
Low output
Low output
Immediatelypreceding state
held *4
Input cut off/
immediatelypreceding state
held *4
P44 to P40
P57 to P50
P63 to P60
*2,*3
Input disabled
Input cut off/
output Hi-Z *5
Low output
Input disabled/
output Hi-Z
1 Input
Input disabled/
output Hi-Z *3
Input disabled/
output Hi-Z
Immediatelypreceding state
held*4
Input disabled/
output Hi-Z
*1: "Output state" means that High-level or Low-level fixed values are output because the driving of pin driving transistors
is enabled but the internal circuit stops. If the resource is in operation and the output function is used, the output
changes except when a reset occurs (the output at reset does not change).
*2: "Output enabled" means that the operation value is output to pins because pin driving transistors are driving and the
internal circuit is enabled.
*3: When the pins are used as output pins, the immediately preceding output values are held.
*4: Indicates that state of pins output immediately before transiting to each standby mode is output as it is or "input
disabled". "State of pins output is output as it is" means that if the resource output is in operation, the state of pins is
output according to the state of the resource and if the state of output pins is output, it is held. "Input disabled" means
that no pin value can be accepted internally because the operation of the input gates of pins is enabled but the internal
circuit stops.
*5: "Input cut off" means that the operation of the input gates of pins is disabled and "output Hi-Z" means that the driving
of pin driving transistors is disabled to set pins to the high-impedance state.
Note:
CM44-10114-7E
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode,
watch mode or timebase timer mode, disable the output of peripheral functions, and set the STP bit of the
low-power consumption mode control register (LPMCR) to 1 or set the TMD bit to 0.
This applies to the following pins:
P14/PPGO/AD12, P15/PPG1/AD13, P16/PPG2/AD14, P17/PPG3/AD15, P21/TOT0/A17,
P23/TOT1/A19, P30/SOT0/ALE, P31/SCK0/RD
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■ State of Input/Output Pins (8-bit Access Mode)
Table 3.8-8 State of Input/Output Pins (8-bit Access Mode)
Stop/Watch/Timebase timer
Pin Name
Sleep
Hold
SPL = 0
P07 to P00
(AD07 to AD00)
Input disabled/output
Hi-Z
Input cut off/
output Hi-Z
P17 to P10
(AD15 to AD08)
Output state *1
Output state *1
P27 to P20
(A23 to A16)
Output state
P37 (CLK)
Input disabled/output
enabled *2, *3
*1, *3
Output state
P35 (HAK)
Input disabled/
output Hi-Z
Input disabled/
output Hi-Z *3
*1, *3
Input disabled/
output state *1, *3
Input cut off/
Immediatelyimmediatelypreceding state held *4 preceding state
held *4
P32 (WRL)
High output *3
High output *3
P31 (RD)
High output
High output
P30 (ALE)
Low output
Low output
P44 to P40
Input cut off/
Immediatelyimmediately*4 preceding state
preceding state held
held *4
P63 to P60
Internal ROM access
after external ROM
access
Input disabled/
output Hi-Z
Output Hi-Z/Input
enabled
Output Hi-Z/Input
enabled
Output state *1
Output state(*1)
Maintains the previous
address
CLK output
CLK output
Output Hi-Z/Input
enabled
Output Hi-Z/Input
enabled
High output
"H" output
"H" output
Low output
"L" output
"L" output
Output Hi-Z/Input
enabled
Output Hi-Z/Input
enabled
Input disabled/
Input disabled/
output Hi-Z *2, *3 output Hi-Z *2
Input disabled
P33 (WRH)
P57 to P50
Internal ROM access
immediately after
reset cancellation
SPL = 1
P36 (RDY)
P34 (HRQ)
Reset
Low output
Input cut off/
Hi-Z *5
1 Input
Input disabled/
output Hi-Z
Immediatelypreceding state
held *4
Input disabled/
output Hi-Z *3
Input disabled/
output Hi-Z
Immediatelypreceding state
held *4
Input disabled/
output Hi-Z
*1: "Output state" means that High-level or Low-level fixed values are output because the driving of pin driving transistors
is enabled but the internal circuit stops. If the resource is in operation and the output function is used, the output
changes except when a reset occurs (the output at reset does not change).
*2: "Output enabled" means that the operation value is output to pins because pin driving transistors are driving and the
internal circuit is enabled.
*3: When the pins are used as output pins, the immediately preceding output values are held.
*4: Indicates that state of pins output immediately before transiting to each standby mode is output as it is or "input
disabled". "State of pins output is output as it is" means that if the resource output is in operation, the state of pins is
output according to the state of the resource and if the state of output pins is output, it is held. "Input disabled" means
that no pin value can be accepted internally because the operation of the input gates of pins is enabled but the internal
circuit stops.
*5: "Input cut off" means that the operation of the input gates of pins is disabled and "output Hi-Z" means that the driving
of pin driving transistors is disabled to set pins to the high-impedance state.
Note:
152
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode,
watch mode or timebase timer mode, disable the output of peripheral functions, and set the STP bit of the
low-power consumption mode control register (LPMCR) to 1 or set the TMD bit to 0.
This applies to the following pins:
P14/PPGO/AD12, P15/PPG1/AD13, P16/PPG2/AD14, P17/PPG3/AD15, P21/TOT0/A17,
P23/TOT1/A19, P30/SOT0/ALE, P31/SCK0/RD
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3.8 Low-power Consumption Mode
MB90495G Series
3.8.8
Precautions when Using Low-power Consumption Mode
This section explains the precautions when using the low-power consumption modes.
■ Transition to Standby Mode
When an interrupt request is generated from the resource to the CPU, the mode does not transit to each
standby mode even after setting the STP and SLP bits in the low-power consumption mode control register
(LPMCR) to 1 and the TMD bit to 0 (and also even after interrupt processing).
If the CPU is in interrupt processing, the interrupt request flag during interrupt processing is cleared and the
mode can transit to each standby mode if no other interrupt requests are generated.
■ Notes on the Transition to Standby Mode
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode,
watch mode, or timebase timer mode, use the following procedure:
1. Disable the output of peripheral functions.
2. Set the SPL bit to "1", STP bit to "1", or TMD bit to "0" in the low-power consumption mode control
register (LPMCR).
■ Cancellation of Standby Mode by Interrupt
When an interrupt request higher than the interrupt level (IL) of 7 is generated from the resource and
external interrupt during operation in the sleep mode, watch mode, timebase timer mode, or stop mode, the
standby mode is cancelled. The standby mode is cancelled by an interrupt regardless of whether the CPU
accept interrupts or not.
Note:
Take measures, such as disabling interrupts, not to branch to the interrupt processing immediately after
return from the standby mode.
■ Note on Cancelling Standby Mode
The standby mode can be cancelled by an input according to the settings of an input factor of an external
interrupt. The input factor can be selected from High level, Low level, rising edge, and falling edge.
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■ Oscillation Stabilization Wait Time
● Oscillation stabilization wait time of main clock
In the subclock mode, watch mode, or stop mode, the oscillation of the main clock stops and the oscillation
stabilization wait time of the main clock is required. The oscillation stabilization wait time of the main
clock is set by the WS1 and WS0 bits in the clock select register (CKSCR).
● Oscillation stabilization wait time of subclock
In the sub-stop mode, the oscillation of the subclock stops and the oscillation stabilization wait time of the
subclock is required. The oscillation stabilization wait time of the subclock is fixed at 214/SCLK (SCLK:
subclock).
● Oscillation stabilization wait time of PLL clock
In main clock mode, the PLL multiplication circuit stops. When changing to PLL clock mode, it is
necessary to reserve the PLL clock oscillation stabilization wait time. The CPU runs in main clock mode
till the PLL clock oscillation stabilization wait time has elapsed. When the main clock is switched to PLL
clock mode, the PLL clock oscillation stabilization wait time is fixed at 214/HCLK (HCLK: oscillation
clock).
In subclock mode, the main clock and PLL multiplication circuit stop. When changing to PLL clock mode,
it is necessary to reserve the main clock oscillation stabilization wait time and PLL clock oscillation
stabilization wait time. The oscillation stabilization wait times for main clock and PLL clock are counted
simultaneously according to the value specified in the oscillation stabilization wait time selection bits
(CKSCR:WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection bits
(CKSCR:WS1, WS0) in the clock selection register must be selected accordingly to account for the longer
of the main clock and PLL clock oscillation stabilization wait times. The PLL clock oscillation stabilization
wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time selection bits
(CKSCR:WS1, WS0) in the clock selection register to "10B" or "11B".
In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL stop
mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock oscillation
stabilization wait time. The oscillation stabilization wait times for the main clock and PLL clock are
counted simultaneously according to the value specified in the oscillation stabilization wait time selection
bits (CKSCR:WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection
bits (CKSCR:WS1, WS0) in the clock selection register must be selected accordingly to account for the
longer of main clock and PLL clock oscillation stabilization wait time. The PLL clock oscillation
stabilization wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time
selection bits (CKSCR:WS1, WS0) in the clock selection register to "10B" or "11B".
■ Transition of Clock Mode
When transiting a clock mode, do not transit a clock mode to any other clock mode or a low-power
consumption mode until the completion of transition. Reference the MCM and SCM bits in the clock select
register (CKSCR) to check that the transition of a clock mode is completed. If the mode is switched to
another clock mode or low-power-consumption mode before completion of switching, the mode may not be
switched.
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MB90495G Series
■ Notes on Accessing the Low-power Consumption Mode Control Register (LPMCR) to
Enter the Standby Mode
● To access the low-power consumption mode control register (LPMCR) with assembler language
• To set the low-power consumption mode control register (LPMCR) to enter the standby mode, use the
instruction listed in Table 3.8-2.
• The low-power consumption mode transition instruction in Table 3.8-2 must always be followed by an array
of instructions highlighted by a dotted line below.
MOV
LPMCR,#H’XX ; the low-power consumption mode transition instruction in Table 3.8-2
NOP
NOP
JMP
$+3
; jump to next instruction
MOV
A,#H’10
; any instruction
The devices does not guarantee its operation after returning from the standby mode if you place an array of instructions other than the one enclosed in the dotted line.
● To access the low-power consumption mode (LPMCR) with C language
To enter the standby mode using the low-power consumption mode control register (LPMCR), use one of the following methods (1) to (3) to access the register:
(1) Specify the standby mode transition instruction as a function and insert two _wait_nop() built-in functions
after that instruction. If any interrupt other than the interrupt to return from the standby mode can occur within
the function, optimize the function during compilation to suppress the LINK and UNLINK instructions from
occurring.
Example: Watch mode or timebase timer mode transition function
void enter_watch(){
IO_LPMCR.byte = 0x10;
/* Set LPMCR TMD bit to "0" */
_wait_nop();
_wait_nop();
}
(2) Define the standby mode transition instruction using _asm statements and insert two NOP and JMP instructions after that instruction.
Example: Transition to sleep mode
_asm(" MOVI: _IO_LPMCR,#H’58); /* Set LPMCR SLP bit to "1" */
_asm(" NOP");
_asm(" NOP");
_asm(" JMP $+3");
/* Jump to next instruction */
(3) Define the standby mode transition instruction between #pragma asm and #pragma endasm and insert two
NOP and JMP instructions after that instruction.
Example: Transition to stop mode
#pragma asm
MOV I: _IO_LPMCR,#H’98
/* Set LPMCR STP bit to "1" */
NOP
NOP
JMP $+3
#pragma endasm
CM44-10114-7E
/* Jump to next instruction */
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3.9 CPU Mode
3.9
MB90495G Series
CPU Mode
The F2MC-16XL family enables the transition of operation modes and memory access
modes to set the CPU operation and access modes and areas.
■ Classification of Modes
Table 3.9-1 shows the classification of operation modes and memory access modes for the F2MC-16XL
family. Each mode is set by mode pins (MD2 to MD0) in reset and mode-fetched mode data.
Table 3.9-1 Classification of Modes
Operation Modes
RUN modes
Memory Access Modes
Bus Modes
External Access Modes
(external data bus width)
Single-chip mode
(Internal-ROM internal-bus mode)
−
Internal-ROM external-access
mode
8-bit access mode
External-ROM external-access
mode
8-bit access mode
16-bit access mode
16-bit access mode
Flash serial
programming mode
−
−
Flash memory mode
−
−
■ Operation Mode
The operation modes control the operating state of the device and are set by the mode pins (MD2 to MD0).
● RUN mode
The RUN mode is the normal CPU operation mode. It provides various low-power consumption modes,
such as the main clock mode, PLL clock mode, and subclock mode.
For details of the low-power consumption modes, see Section "3.8 Low-power Consumption Mode".
● Flash serial programming mode and flash memory mode
Some products in the MB90495G series have user-programmable flash memory.
The flash serial programming mode is that for serially programming data to flash memory.
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3.9 CPU Mode
MB90495G Series
■ Memory Access Modes
The memory access modes is mode data allocated to "FFFFDFH" and set the operation after reset.
● Bus mode
The bus mode sets the operation of the internal ROM and the external access function. It has a single-chip
mode (internal-ROM internal-bus mode), internal-ROM external-access mode, and external-ROM externalaccess mode.
● External access mode
The external access mode selects the external data bus width at external access between 8 bits and 16 bits.
For details of the external access, see Section "3.10 External Access".
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3.9 CPU Mode
3.9.1
MB90495G Series
Mode Pins (MD2 to MD0)
The mode pins are three external pins of MD2 to MD0, and enable a combination of
these pins to set, the following:
• Operation modes (RUN mode, flash serial programming mode, flash memory mode)
• Reading reset vectors and mode data
• Bus width when selecting external data bus
■ Setting of Mode Pins (MD2 to MD0)
Table 3.9-2 shows the settings of the mode pins.
Table 3.9-2 Setting of Mode Pins
Mode Pin*
Mode Name
Reset Vector
Access Area
External Data Bus Width
(Lower: 000200H to
7FFFFFH)
External Data Bus Width
(Higher: 800000H to
FFFFFFH)
MD2
MD1
MD0
0
0
0
External vector mode
0
External
8 bits
8 bits
0
0
1
External vector mode
1
External
16 bits
16 bits
0
1
0
External vector mode
2
External
16 bits
8 bits
0
1
1
Internal vector mode
Internal
(Mode data)
(Mode data)
1
0
0
1
0
1
1
1
0
Flash serial
programming mode
−
−
−
1
1
1
Flash memory mode
−
−
−
Setting disabled
*: Set MD2 to MD0: 0 = VSS or 1 = VCC.
● External vector mode
Reset vectors are read from external ROM. The pins also serving as bus ports function as external bus pins.
The external vector mode is divided into the following three modes according to an external data bus
width.:
• External vector mode 0: 8-bit external data bus width
• External vector mode 1: 16-bit external data bus width
• External vector mode 2:8-bit bus width when area between addresses "800000H" and "FFFFFFH"
accessed
Note:
When start ROM has an 8-bit wide bus and RAM has a 16-bit wide bus, set External vector mode 2.
For details of the external access, see Section "3.10 External Access".
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3.9 CPU Mode
MB90495G Series
● Internal vector mode
Reset vectors are read from internal ROM. The external data bus width is set by the external access mode
setting bit (S0) of mode data.
● Flash serial programming mode
Flash serial programming cannot be performed just by the settings of the mode pins.
For details of flash serial programming, see "CHAPTER 20
CONNECTION".
FLASH SERIAL PROGRAMMING
● Flash memory mode
This mode is set when using a parallel writer.
■ Setting Mode Pins
Set the mode pins as shown inFigure 3.9-1.
Figure 3.9-1 Flow of Mode Pin Setting
Set mode pin
Data programmed
to flash memory
NO
YES
Read reset vector
and mode data
from internal ROM?
YES
NO
Reset vector and
fetch are 8-bit bus
width access?
NO
YES
External data bus
width is 16 bits?
NO
YES
Flash
programming
mode
Internal vector
mode
External vector
mode 0
External vector
mode 1
External vector
mode 2
MD2 MD1 MD0 MD2 MD1 MD0 MD2 MD1 MD0 MD2 MD1 MD0 MD2 MD1 MD0
"1" "1" "1"
"0" "1" "1"
"0" "0" "0"
"0" "0" "1"
"0" "1" "0"
MD0 to MD2: Set 0 = Vss and 1 = Vcc. Do not set value except the value described above.
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3.9 CPU Mode
3.9.2
MB90495G Series
Mode Data
Mode data is used to set the memory access mode. It is automatically read to the CPU
by mode fetch.
■ Mode Data
The values of the mode register can be changed only in the reset sequence. The changed mode register
values are enabled after the reset sequence.
Figure 3.9-2 Mode Data
15
14
13
12
11
10
9
8
Reset value
00XX0XXX B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 8 bit 9 bit 10 bit 12 bit 13
Reserved bits
Reserved
0
bit 11
S0
0
1
Always set to "0"
External access mode setting bits
8-bit access mode
16-bit access mode
bit 15 bit 14
M0
M1
R/W : Read/Write
X
: Undefined
: Reset value
160
Bus mode setting bits
0
0
Single-chip mode
0
1
Internal ROM external bus mode
1
0
External ROM external bus mode
1
1
Setting disable
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CHAPTER 3 CPU
3.9 CPU Mode
MB90495G Series
Table 3.9-3 Function of Mode Register
Bit Name
bit 8 to bit 13
Function
Reserved: Reserved bits
Always write 0 to these bits.
bit 11
SO:
External access mode
setting bit
This bit is used to set the external access mode.
When set to 0: 8-bit access mode set (8-bit bus width at external access)
When set to 1: 16-bit access mode set (16-bit bus width at external access)
bit 14
bit 15
M1, M0:
Bus mode setting bit
These bits are used to set the bus mode.
When set to "00B": Internal ROM read to access internal bus
When set to "01B": Internal ROM read to access external bus
When set to "10B": External ROM read to access external bus
Note:
Set a mode pin so that the values of the mode pins match the values of the mode register. Do not set a
mode pin so that the mode pins are in the external vector mode, and the mode register is in the single-chip
mode (internal-bus internal-access).
■ Setting Mode Data
Set mode data according to Figure 3.9-3.
Figure 3.9-3 Flow of Mode Data Setting
Set mode data
Single-chip
mode
NO
YES
NO
Use internal
ROM?
YES
External data bus
width is 8 bits?
NO
YES
Single-chip
mode
Mode data "00H"
External data bus
width is 8 bits?
NO
YES
Internal ROM
External ROM
External ROM
Internal ROM
External bus mode External bus mode External bus mode External bus mode
External bus 8 bits
Mode data "40H"
External bus
16 bits
Mode data "48H"
External bus 8 bits
Mode data "80H"
External bus
16 bits
Mode data "88H"
Do not set mode data to value except the value described above.
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3.9 CPU Mode
3.9.3
MB90495G Series
Memory Access Mode
The memory access mode is divided into the following two modes:
• Bus mode: Sets access area (internal/external)
• External access mode: Sets external bus data width at external access
■ Bus Mode
Figure 3.9-4 shows the memory map in each mode.
Figure 3.9-4 Memory Map in Each Mode
000000 H
Single-chip mode
(with ROM mirroring
function)
Internal-ROM
external bus mdoe
External-ROM
external bus mdoe
Resource
Resource
Resource
0000C0 H
000100 H
RAM area
RAM area
RAM area
Register
Register
Register
Address#1*
001100 H
003800 H
Extend I/O area
Extend I/O area
Extend I/O area
004000 H
ROM area
(image of FF bank)
ROM area
(image of FF bank)
ROM area
ROM area
010000 H
Address#2*1
FFFFFFH
: Internal access memory
: External access memory
: Access disabled
*
: Addresses #1, #2 depend on the device.
For details of the access area, see Section "3.1 Memory Space".
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MB90495G Series
● Single-chip mode (internal-ROM internal-access)
• Only internal ROM and internal RAM are used and no external access occurs.
• Ports 0 to 3 can be used as general-purpose I/O ports.
Note:
If the single-chip mode is set, do not write to the automatic ready function select register (ARSR), high
address control register (HACR), and bus control signal select register (ECSR).
● Internal-ROM external-access mode and external-ROM external-access mode
• In the internal-ROM external-access mode, the internal ROM area is used for internal access and other
external areas are used for external access.
• In the external-ROM external-access mode, the internal ROM area is isolated into an external area, and
the external memory is accessed by external bus operation.
• Ports 0 to 2 can be used as external pins for input/output of addresses and data.
• Port 3 functions as an external bus control pin.
• Ports 2 and 3 can also be used as general-purpose I/O ports according to the setting.
• When the external access mode is set, the ready and hold functions for access to low-speed external
memory and resources can be used.
For details of the low-power consumption modes, see Section "3.10 External Access".
■ External Access Mode
Table 3.9-4 shows the settings of mode pins and the memory access modes.
Table 3.9-4 Settings of Mode Pins and Memory Access Modes
Mode Pin
Mode Data
Setting
MD2
MD1
MD0
M1
M0
S0
Memory Access Mode
0
1
1
0
0
X/1
0
1
1
0
1
1
Internal-ROM external-bus
mode
16-bit bus
0
1
1
0
1
0
Internal-ROM external-bus
mode
8-bit bus
0
0
1
1
0
1
External-ROM externalbus mode
16-bit bus
0
1
0
1
0
1
External-ROM externalbus mode
16-bit bus/8-bit bus *
0
0
0
1
0
0
External-ROM externalbus mode
8-bit bus
Single-chip Mode
External Data Bus
−
*: The 8-bit bus width is used at external access to the area between addresses "800000H" and "FFFFFH".
Note:
The external data bus width in the 16-bit access mode (S0 = 1) is determined by the settings of the bus
control signal select register (ECSR). The initial value of the external data bus width at power-on or
reset is set according to the setting of the S0 bit in the mode pins (MD2 to MD0) and mode data.
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3.9 CPU Mode
3.9.4
MB90495G Series
Selection of Memory Access Mode
his section explains selection of the memory access mode in the reset sequence.
■ Selection of Memory Access Mode
After reset is cancelled, the CPU selects the memory access mode according to the procedure shown in
Figure 3.9-5 by referencing the settings of the mode pins and mode data.
Figure 3.9-5 Selection of Memory Access Mode
Reset factor
How mode pins
(MD2, MD1, and MD0)
are set?
Check of mode pin
Mode data read
to external ROM
Internal data read
to internal ROM
*
All I/O pins in highimpedence state
Reset factor
cancellation waiting
(External reset or
oscillation stabilization wait time)
YES
Reset operating?
Reset operating?
NO
Mode fetch
YES
NO
Fetch mode data and reset
vector from internal ROM
Fetch mode data and reset
vector from internal ROM
*
(M1,M0="00B")
How are M1 and M0 bits
of mode data?
(M1,M0="10B")
(M1,M0="01B")
*
Check mode data
Set to single-chip mode
Set to internal-ROM
external-bus mode
(S0=0)
Set to external-ROM
external-bus mode
How are S0 bits
of mode data?
Set external bus width
to 8 bits
(S0=1)
Set external bus width
to 16 bits
*: Address data, RD, WRL, WRH , ALE, CLK, RDY operation state
Note: After resetting, bus width can be changed for each area by setting bus control signal select register (ECSR).
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CHAPTER 3 CPU
3.10 External Access
MB90495G Series
3.10
External Access
When the external access mode is set, the CPU accesses external memory and
resources, and inputs and outputs addresses, data and external bus control signals. By
changing the data bus width for each external area, resources with a combined 8-bit
data bus width and a 16-bit data bus width can be connected to external data buses.
■ Control Signals in External Access Mode
In the external access mode, the CPU inputs and outputs external bus control signals to access external
memory and resources. Table 3.10-1 shows the external bus control signals in the external access mode.
Table 3.10-1 External Bus Control Signals in External Access Mode
Signal
Name
CM44-10114-7E
Pin Name
Function
ALE
P30/ALE/SOT0
Outputs address latch enable signals
RD
P31/RD/SIN0
Outputs read strobe signals
WRL
P32/WRL/SIN0
16-bit bus mode: Output a lower 8-bit write strobe signal of data bus
8-bit bus mode: Outputs write strobe signals.
WRH
P33/WRH
Outputs a higher 8-bit write strobe signals of data bus
(This signal functions only in the 16-bit bus mode.)
HRQ
P34/HRQ
Inputs hold request signals
HAK
P35/HAK
Outputs hold acknowledge signals
RDY
P36/RDY/
FRCK
Inputs external ready signals
CLK
P37/CLK/
ADTG
Outputs machine clocks (φ)
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MB90495G Series
■ Functions in External Access Mode
The following functions can be used in the external access mode.
● Ready/auto-ready function
This function enables access to low-speed external memory and resources in an extended bus cycle.
● Hold function
This function causes the CPU to release the bus so that resources can use the bus.
● Bus sizing function
This function enables access by switching between an 8-bit data bus width and 16-bit data bus width for
each external area.
Notes:
166
• If the ready function is not used, access to external memory is based on three machine cycles (3/φ).
• Only the address and ALE signal are output and the RD, WRL and WRL signals are not output, so no
bus operation may actually be performed. Note that access to resources should not be made only by
the ALE signal.
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CHAPTER 3 CPU
3.10 External Access
MB90495G Series
3.10.1
External Bus Pins
In the external access mode, ports 0 to 2 function as external bus pins and port 3
functions as an external bus control pin.
■ External Bus Pin Control Circuit
Figure 3.10-1 External Bus Pin Control Circuit
P3
Pin
P2
P3
P1
P0
Internal address bus
P0 data
Pin
P0
P0 direction
Internal data bus
Data control
Address control
Access control
CM44-10114-7E
Access control
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MB90495G Series
■ Pin Related to External Bus
Table 3.10-2 shows the relationship between pins related to external buses and bus modes. Table 3.10-3
lists the functions of each pin in the external access mode.
Table 3.10-2 Pin Related to External Access and Bus Mode
Pin Name
Internal Access
(single-chip mode)
External Access
8-bit Bus Mode
16-bit Bus Mode
P00/AD00 to
P07/AD07
P00 to P07:
general-purpose I/O port 0
AD00 to AD07: input/output lower bits of address/data bus
P10/AD08/IN0 to
P17/AD15/PPG3
P10 to P17:
general-purpose I/O port 1
A08 to A15: output middle
bits of address bus
P20/TIN0/A16 to
P27/INT7/A23
P20 to P27:
general-purpose I/O port 1
A16 to A23: input/output higher bits of address bus*1
P30/ALE/SOT0
P30:
general-purpose I/O port 3
ALE: outputs address latch enable signals
P31/RD/SCK0
P31:
general-purpose I/O port 3
RD: outputs read strobe signals
P32/WRL/SIN0
P32:
general-purpose I/O port 3
Output lower 8-bit write strobe signals of data bus*2
P33WRH
P33:
general-purpose I/O port 3
P33:
general-purpose I/O port 3
P34/HRQ
P34:
general-purpose I/O port 3
HRQ: inputs higher 8-bit hold request signals of data bus*2
P35/HAK
P35:
general-purpose I/O port 3
HAK: outputs hold acknowledge signals*2
P36/RDY/FRCK
P36:
general-purpose I/O port 3
RDY: outputs ready signals*2
P37/CLK/ADTG
P37:
general-purpose I/O port 3
CLK: output clock signals
AD08 to AD15: input/
output middle bits of
address/data bus
Output higher 8-bit write
strobe signals of data bus*2
*1: These ports can be used as general-purpose I/O ports according to the settings of the high address control
register (HACR).
*2: These ports can be used as general-purpose I/O ports according to the settings of the bus control signal
select register (ECSR).
Table 3.10-3 Pin Functions in External Access Mode (1 / 2)
Pin Name
I/O
AD00 to AD07
I/O
168
Function
Input/output lower 8-bit external address/data bus
• These are external bus pins for time-shared input/output of the lower 8 bits of addresses
and data. The addresses must be latched externally by the ALE signal.
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3.10 External Access
MB90495G Series
Table 3.10-3 Pin Functions in External Access Mode (2 / 2)
Pin Name
I/O
Function
AD08 to AD15
I/O
Input/output middle 8-bit external address/data bus
• These are external bus pins for time-shared input/output of the middle 8 bits of addresses
and the higher 8 bits of data. The addresses must be latched externally by the ALE signal.
A16 to A23 *1
O
Output higher 8-bit external address bus
• These are external bus pins for output of the higher 8 bits of addresses. The higher 8 bits
of addresses are output continuously while the lower bits of addresses and data are
multiplexed, so the addresses need not be latched by the ALE signal.
ALE
O
Outputs address latch enable signal
• This is a signal to latch address signals externally. Latch addresses on the rising edge of
the address latch enable signal.
RD
O
Outputs read strobe signal
• This is a strobe signal to read data. This signal goes Low at read operation and data on the
data bus is read on the rising edge of the read strobe signal.
O
Outputs write strobe signal (lower 8 bits in 16-bit access mode)
• This is a strobe signal to write data at AD00 to AD07. In the 16-bit access mode, data is
written to the lower 8 bits. This signal goes Low at write operation and data is output to
the data bus. External memory and resources read data on the data bus on the rising edge
of the write strobe signal.
O
Outputs write strobe signal (higher 8 bits)
• This is a strobe signal to write data at AD08 to AD15. This signal goes Low at write
operation and data is output to the data bus. External memory and resources read data on
the data bus on the rising edge of the write strobe signal. This signal can be used only the
16-bit bus mode.
I
Inputs hold request signal
• This is a signal to request the CPU to release the external buses so that resources can use
them. While a High level is input to the HRQ pin, the external bus pins and some external
control signal pin enter the high impedance state.
O
Outputs hold acknowledge signal
• This is a signal to acknowledge the CPU release of the external buses in respond to input
of the hold request signals (HRQ signals) from the resources. When the HAK signal goes
Low, the resources can use the external buses.
RDY *2
I
Inputs ready signal
• This is a signal to extend a bus cycle for access to low-speed external memory. While a
Low level is input to the RDY pin, the bus cycle is extended by the operation clock
(machine cycle) of the CPU.
CLK *2
O
Outputs clock signal
• The operation clock (machine clock) of the CPU is output.
WRL *2
WRH *2
HRQ *2
HAK *2
*1: When not used for external access, the pins can be used as general-purpose I/O ports according to the settings of the
high address control register (HACR).
*2: When not used for external access, the pins can be used as general-purpose I/O ports according to the settings of the bus
control signal select register (ECSR).
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3.10 External Access
3.10.2
MB90495G Series
Registers used in External Access Mode
This section lists and details the registers used in the external access mode.
■ Registers Used in External Access Mode
Figure 3.10-2 List of Registers used in External Access Mode and Reset Values
bit
Bus control signal select register (ECSR)
bit
Auto ready function select register (ARSR)
bit
High address control register (HACR)
15
14
13
12
11
10
9
8
0
0
0
0
0/1
0
0
×
15
14
13
12
11
10
9
8
0
0
1
1
×
×
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
× : Undefined
0/1: 0 or 1
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3.10 External Access
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3.10.3
Bus Control Signal Select Register (ECSR)
The bus control signal select register (ECSR) enables or disables the clock output,
ready output and hold function, and sets the data bus width in the external access
mode.
■ Bus Control Signal Select Register (ECSR)
Figure 3.10-3 Bus Control Signal Select Register (ECSR)
15
W
14
W
13
12
11
10
9
W
W
W
W
W
8
Reset value
0000000XB
or
⎯
0000100XB
bit 9
Lower memory data bus width select bit
LMBS
("002000H" to "7FFFFFH" area)
0
1
16-bit data bus width access
8-bit data bus width access
bit 10
External write output enable bit
WRE
General-purpose I/O port
0
External write signal output enable
1
bit 11
Higher memory data bus width select bit
("800000H" to "FFFFFFH" area)
HMBS*
0
1
16-bit data bus width access
8-bit data bus width access
bit 12
External I/O data bus width select bit
("0000C0H" to "0000FFH" area)
IOBS
0
1
16-bit data bus width access
8-bit data bus width access
bit 13
Hold I/O enable bit
HDE
0
General-purpose I/O port
1
Hold I/O
bit 14
External ready input enable bit
RYE
General-purpose I/O port
0
External ready input
1
W
⎯
*
CM44-10114-7E
:
:
:
:
bit 15
External clock output enable bit
CKE
General-purpose I/O port
0
Clock output
1
Write only
Unused
Reset value
Reset value depends on setting of mode pin
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Table 3.10-4 Functions of Bus Control Signal Select Register (ECSR)
Bit Name
172
Function
bit 8
Unused bit
Read: The value is undefined.
Write: No effect
bit 9
LMBS:
Lower memory data bus
width select bit
If the 16-bit bus mode is set, this bit is used to determine the data bus width for
external access to the area at addresses "002000H" to "7FFFFFH".
When set to 0: The area at addresses "002000H" to "7FFFFFH" has a 16-bit data
bus width.
When set to 1: The area at addresses "002000H" to "7FFFFFH" has an 8-bit data
bus width.
bit 10
WRE:
External write output
enable bit
This bit is used to enable or disable output of an external write signal.
When set to 0: The WRL and WRH pins function as general-purpose I/O ports.
When set to 1: The WRL and WRH pins function as external write signal
outputs.
bit 11
HMBS:
Higher memory data bus
width select bit
If the 16-bit bus mode is set, this bit is used to determine the data bus width for
external access to the area at addresses "800000H" to "FFFFFFH".
When set to 0:The area at addresses "800000H" to "FFFFFFH" has a 16-bit data
bus width.
When set to 1:The area at addresses "800000H" to "FFFFFFH" has an 8-bit data
bus width.
Note:
At external vector mode 2, the reset value is 1. In a mode other than external
vector mode 2, the reset value is 0.
bit 12
IOBS:
External I/O bus width
select bit
When the 16-bit bus mode is set, this bit is used to determine the data bus width
for external access to the area at addresses "C000C0H" to "0000FFH".
When set to 0: The area at addresses "C000C0H" to "0000FFH" has a 16-bit
data bus width.
When set to 1: The area at addresses "0000C0H" to "0000FFH" has an 8-bit data
bus width
bit 13
HDE:
Hold input/output enable
bit
This bit is used to enable or disable output of a bit related to the hold function
When set to 0: The HRQ and HAK pins function as general-purpose I/O ports
When set to 1: The HRQ and HAK pins function as hold-acknowledge outputs.
bit 14
RYE:
External ready input
enable bit
This bit is used to select the function of the ready pin (RDY).
When set to 0: The RDY pin functions as a general-purpose I/O port.
When set to 1: The RDY pin functions as an external ready input.
bit 15
CKE:
External clock output
enable bit
This bit is used to select the function of the external clock pin (CLK).
When set to 0: The CLK pin functions as a general-purpose I/O port.
When set to 1: The CLK pin functions as an external clock output.
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CHAPTER 3 CPU
3.10 External Access
MB90495G Series
3.10.4
Auto Ready Function Select Register (ARSR)
The auto ready function select register (ARSR) sets the auto wait time for memory
access for each external area used in the external access mode.
■ Auto Ready Function Select Register (ARSR)
Figure 3.10-4 Auto Ready Function Select Register (ARSR)
15
14
13
12
11
10
9
8
Reset value
0011XX00 B
W
W
W
W
⎯
⎯
W
W
bit 9 bit 8
LMR1 LMR0
0
0
1
1
0
1
0
1
Lower memory area auto wait select bits
("002000H" to "7FFFFFH" area)
Auto wait disable
Auto wait of 1 machine cycle
Auto wait of 2 machine cycle
Auto wait of 3 machine cycle
bit 13 bit 12
HMR1 HMR0
0
0
1
1
0
1
0
1
Higher memory area auto wait select bits
("800000H" to "FFFFFFH" area)
Auto wait disable
Auto wait of 1 machine cycle
Auto wait of 2 machine cycle
Auto wait of 3 machine cycle
bit 15 bit 14
IOR1 IOR0
W
⎯
X
: Write only
0
: Unused
0
: Undefined
1
: Reset value
1
1 machine cycle is 1/φ (φ: machine clock)
CM44-10114-7E
0
1
0
1
External area auto wait select bits
("0000C0H" to "0000FFH" area)
Auto wait disable
Auto wait of 1 machine cycle
Auto wait of 2 machine cycle
Auto wait of 3 machine cycle
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Table 3.10-5 Functions of Auto Ready Function Select Register (ARSR)
Bit Name
174
Function
bit 8
bit 9
LMR1, LMR0:
Lower memory area auto
wait select bits
These bits are used to set the auto wait time for external access to the area at
addresses "002000H" to "7FFFFFH".
bit 10
bit 11
Unused bits
Read: The values are undefined
Write: No effect
bit 12
bit 13
HMR1, HMR0:
Higher memory area
auto wait select bits
These bits are used to set the auto wait time for external access to the area at
addresses "800000H" to "FFFFFFH".
bit 14
bit 15
IOR1, IOR0:
External area auto wait
select bits
These bits are used to set the auto wait time for external access to the area at
addresses "0000C0H" to "0000FFH".
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 3 CPU
3.10 External Access
MB90495G Series
3.10.5
High Address Control Register (HACR)
The high address control register (HACR) enables or disables the external output of
addresses (A16 to A23). This register cannot be accessed in the single-chip mode.
■ High Address Control Register (HACR)
Figure 3.10-5 High Address Control Register (HACR)
7
6
5
4
3
2
1
0
W
W
W
W
W
W
W
W
Reset value
00000000
W
⎯
X
CM44-10114-7E
:
:
:
:
Write only
Unused
Undefined
Reset value
B
bit 0
E16
0
1
High address bit output control bit (A16)
Address output
General-purpose I/O port
bit 1
E17
0
1
High address bit output control bit (A17)
Address output
General-purpose I/O port
bit 2
E18
0
1
High address bit output control bit (A18)
Address output
General-purpose I/O port
bit 3
E19
0
1
High address bit output control bit (A19)
Address output
General-purpose I/O port
bit 4
E20
0
1
High address bit output control bit (A20)
Address output
General-purpose I/O port
bit 5
E21
0
1
High address bit output control bit (A21)
Address output
General-purpose I/O port
bit 6
E22
0
1
High address bit output control bit (A22)
Address output
General-purpose I/O port
bit 7
E23
0
1
High address bit output control bit (A23)
Address output
General-purpose I/O port
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Table 3.10-6 Functions of High Address Control Register (HACR)
Bit Name
bit 0 to bit 7
Note:
176
Function
E23 to E16:
High address bit output
control bits
These bits are used to enable or disable external output at addresses (A16 to
A23).
When set to 0:The address bus pins (A16 to A23) function as address bus
outputs.
When set to 1:The address bus pins (A16 to A23) function as generalpurpose I/O ports.
In the case that the external. bus is used, the pins shared with addresses (A16 to A23) can only be used as
general purpose ports (P20 to P27) or as resource inputs (TIN0, TIN1, INT4 to INT7). They cannot be
used as resource output (TOT0 and TOT1).
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CM44-10114-7E
CHAPTER 3 CPU
3.10 External Access
MB90495G Series
3.10.6
Bus Sizing Function
The width of the data bus for external memory space can be set to 8 bits or 16 bits for
each external area.
■ Bus Sizing Function
• Resources with an 8-bit or 16-bit data bus width can be combined to connect external buses by changing
the data bus width for each external area.
• The data bus width for each external area is set by the bus control signal select register (ECSR).
• The areas at "0000C0H" to "0000FFH", at "002000H" to "7FFFFFH", and at "800000H" to "FFFFFFH"
can be set.
• Access at the 8-bit data bus width uses the lower 8 bits of the data bus.
Figure 3.10-6 gives an example of the setting of the bus sizing function.
Figure 3.10-6 Example of Setting of Bus Sizing Function
000000 H
0000C0 H
Area 1
FF bank
FE bank
0000FF H
Set to 8-bit data bus width access
(ESCR: IOBS = 1)
002000 H
Set to 16-bit data bus width access
(ESCR: LMBS = 1)
Area 2
7FFFFFH
800000 H
Set to 8-bit data bus width access
(ESCR: HMBS = 1)
Area 3
FE0000 H
FF00000H
FFFFFF H
Note:
CM44-10114-7E
The data bus width is determined by the state of the mode pins (MD0 to MD2) and the settings of mode
data (M1, M0) immediately after reset.
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3.10 External Access
3.10.7
MB90495G Series
Ready Function
The bus access cycle can be extended to access low-speed external memory and
resources.
■ Ready Function
The ready function extends the access cycle with the operation in the wait state while a Low level is input
to the RDY pin. This function is enabled by setting the RYE bit in the bus control signal select register
(ECSR) to 1.
Figure 3.10-7 shows the bus operation using the ready function.
Figure 3.10-7 Bus Operation Using Ready Function (16-bit access mode)
Even address word read
Even address word write
CLK
WRH
WRL
RD
ALE
Read address
A23 to A16
Write address
AD15
to AD08
Read address
Read data
Write address
Write data
AD07
to /AD00
Read address
Read data
Write address
Write data
RDY
PDY pin fetch
Cycle expanded by ready
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CHAPTER 3 CPU
3.10 External Access
MB90495G Series
● Example of circuit with ready function
When the chip select signal (Low-level output) is connected to the shift inputs (H to B) of the shift register,
1 to 7 clock cycles of ready signals (wait) are generated. The following circuit shows three waits because
the chip select signal is connected to F, G and H: one wait when the signal is connected to H alone and two
waits when the signal is connected to G and H.
Figure 3.10-8 Example of Circuit with Ready Function
Low-speed external
memory or chip select
signal of resource
MB90495G series
AD00 to AD15
ALE
A16 to A23
RDY
CLK
High level
16
D
G
Q
Address
latch
4
A00 to A15
Address
decoder CS
A16 to A19
Lactch circuit
Shift register
A
B
C
D
E
F
G
H
S/L
QH
CLK
• Address decoder
- The address decoder decodes the address of the external area where low-speed external memory is
allocated. When the external area is accessed, the decoder goes Low to generate the chip select
signal.
• Shift register
- The chip select signals (Low level) connected to the shift inputs (H to A) of the shift register are
loaded on the rising edge of the address latch enable signal (ALE). When the ALE signal goes Low,
the shift register shifts starting with H to output a Low level to QH by the number of times it is loaded
in synchronization with the CLK signal. When this output signal is connected to the RDY pin, the
CPU extends the bus cycle for as long as the Low level continues.
• Address latch
- When the ALE signal is High, the data input (D) must be output to the latch output (Q). The low
addresses are held on the falling edge of the ALE signal.
Figure 3.10-9 gives an example of timing of ready signal generation.
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Figure 3.10-9 Example of Timing of Ready Signal Generation
CLK
ALE
High address
A16
to A23
AD00
to AD15
Low
address
Data
CS
QH
RDY
H
G
F
Load Low level of CS into F, G and H
(Starting of ready operation)
Note:
180
H
CS is High level
(Memory which doesn't
need ready operation)
The RDY signal requires setup time to rise the CLK signal, so it is recommended to read the latch signal
in synchronization with the CLK signal.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 3 CPU
3.10 External Access
MB90495G Series
■ Auto Ready Function
The auto ready function extends the access cycle by automatically inserting a wait cycle of one to three
machine cycles (1/φ to 3/φ) without any external circuit. The wait cycle is set for each external area by the
auto ready function select register (ARSR).
Table 3.10-7 Control Bits in Auto Ready Function
External Area
Address
Setting of Bits Auto Ready Function
Select Register (ARSR)*1
External higher memory area
"800000H" to "FFFFFH"
HMR1, CHMR0*2
External lower memory area
"002000H" to "7FFFFFH"
LMR1, CLMR0*2
External I/O area
"C000C0H" to "0000FFH"
IOR1, CIOR0*2
*1: Each control bit is used to set a wait cycle count of one to three machine clocks at "00H" to "11H".
*2: The address indicates the logic area.
Figure 3.10-10 shows the bus operation in the auto ready function.
Figure 3.10-10 Bus Operation in Auto Ready Function
Even address word write
Even address word read
CLK
WRH
WRL
RD
ALE
A23 to A16
Write address
Read address
AD15 to AD08
Write address
Write data
Read address
AD07 to AD00
Write address
Write data
Read address
Cycle extended by auto ready
Note:
CM44-10114-7E
When a Low level is input to the RDY pin with an external ready input enabled after the wait cycle is
terminated by the auto ready function, the wait cycle is continued.
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3.10 External Access
3.10.8
MB90495G Series
Hold Function
When a hold request is generated from resources, the hold function releases the
external bus from the CPU so that the resources can use the external bus.
■ Hold Function
When the hold function is enabled (ECSR:HDE = 1), hold function of the external bus by the HRQ and
HAK pins is enabled. When a High level is input to the HRQ pin, the CPU enters the hold state after
completion of instruction execution (after processing of one-element data is completed for the string
instruction), the HAK pin outputs a Low level and the following pins enter the high-impedance state.
• Address output pins (A16 to A23)
• Address/data input/output pins (AD00 to AD15)
• Bus control signal pins (ALE, RD, WRL, WRH)
The above processing enables the resources to use the external bus. When a Low level is input to the HRQ
pin with the external bus released, the HAK pin outputs a High level, each external pins return to its
original state, and the CPU resumes operation.
Note:
No hold request is accepted in the stop mode.
Figure 3.10-11 shows the bus operation in the hold function.
Figure 3.10-11 Bus Operation in Hold Function
Read cycle
Hold cycle
Write cycle
CLK
HRQ
HAK
WRH
WRL
RD
ALE
A23 to A16
182
Address
Address
AD15
to AD08
Read data
Address
AD07
to AD00
Read data
Address
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 3 CPU
3.10 External Access
MB90495G Series
■ Example of System Using Hold Function
Figure 3.10-12 gives an example of system using the hold function.
Figure 3.10-12 Example of System Using Hold Function
A00 to A23
D00 to D15
Memory
RD, WR
I/O
HRQ
DMA controller
HAK
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3.10 External Access
3.10.9
MB90495G Series
External Access Timing
This section shows the timing charts in the 8-bit and 16-bit access modes. If the ready
function is not used, an external memory is normally accessed in three machine cycles.
■ External Memory Access Control Signal
In the 16-bit access mode, access of an 8-bit bus width is provided to read and write peripheral chips of an
8-bit width when peripheral chips of an 8-bit width and a 16-bit width are connected to the external bus.
Access of an 8-bit bus width is performed using the lower 8 bits of the data bus, so the peripheral chip of an
8-bit width should be connected to the lower 8 bits of the data bus.
■ Access Timing in 8-bit Access Mode
Figure 3.10-13 Access Timing in 8-bit Access Mode (Read/Write)
Read
Write
Read
CLK
WRH*
(unused)
Port data
WRL
RD
ALE
A23 to A16
Read address
Write address
Read address
A15 to A08
Read address
Write address
Read address
AD07
to AD00
Read address
Read data
Write address
Write data
Read address
*: Higher 8 bits of external data bus (WRH) is not used in 8-bit access.
Note:
184
Only the address and ALE signal are output and the RD, WRL and WRH signals are not output, so no bus
operation may be performed actually. Do not access resources only by the ALE signal.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 3 CPU
3.10 External Access
MB90495G Series
■ Access Timing in 16-bit Access Mode
Figure 3.10-14 Access Timing in 16-bit Access Mode (Read/Write)
Even address byte read/write (8 bits)
Even address byte read
Even address byte write
CLK
WRH
WRL
RD
ALE
A23 to A16
AD15
to AD08
AD07
to AD00
Read address
Write address
Read address
Read address
Invalid
Write address
Undefined
Read address
Read address
Read data
Write address
Write data
Read address
Odd address byte read/write
Odd address byte read
Odd address byte write
CLK
WRH
WRL
RD
ALE
A23 to A16
AD15
to AD08
AD07
to AD00
Read address
Write address
Read address
Read address
Read data
Write address
Write data
Read address
Read address
Invalid
Write address
Undefined
Read address
Even address word read/write
Even address word read
Even address word write
CLK
WRH
WRL
RD
ALE
A23 to A16
AD15
to AD08
AD07
to AD00
Notes:
CM44-10114-7E
Read address
Write address
Read address
Read address
Read data
Write address
Write data
Read address
Read address
Read data
Write address
Write data
Read address
• Design the external circuit so that word reading can always be performed for access of a 16-bit bus
width in the 16-bit access mode.
• At word reading/writing at odd addresses, odd byte access and even byte access are made separately,
requiring a total of six machine cycles (6/φ).
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3.10 External Access
186
MB90495G Series
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 4
I/O PORT
This chapter describes the function and operation of the
I/O port.
4.1 Overview of I/O Port
4.2 Registers of I/O Port and Assignment of Pins Serving as External
Bus
4.3 Port 0
4.4 Port 1
4.5 Port 2
4.6 Port 3
4.7 Port 4
4.8 Port 5
4.9 Port 6
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CHAPTER 4 I/O PORT
4.1 Overview of I/O Port
4.1
MB90495G Series
Overview of I/O Port
I/O ports can be used as general-purpose I/O ports (parallel I/O ports). In the MB90495G
series, there are seven ports (49 pins).
Each port pin also serves as a resource I/O pins.
■ I/O Port Function
The I/O ports enable the port data register (PDR) to output data to the I/O pins from the CPU and fetch
signals input to the I/O pins. These also enable the port direction register (DDR) to set a direction for the I/
O pins in unit of bits.
The following shows the function of each port, and the resources that it also serves as:
• Port 0: Serves as both general-purpose I/O port and external address/data bus pin
• Port 1: Serves as both general-purpose I/O port and PPG timer output, input capture input, or external
address/data bus pin
• Port 2: Serves as both general-purpose I/O port and reload timer I/O, external interrupt input, or
external address bus pin
• Port 3: Serves as both general-purpose I/O port and UART0 I/O pin, free-run timer or A/D converter
start trigger pin
• Port 4: Serves as both general-purpose I/O port and UART1 I/O or CAN controller transmit/receive
pin
• Port 5: Serves as both general-purpose I/O port and analog input pin
• Port 6: Serves as both general-purpose I/O port and external interrupt input pin
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CHAPTER 4 I/O PORT
4.1 Overview of I/O Port
MB90495G Series
Table 4.1-1 List of Each Port Functions
Port
Name
Port 0
Port 1
Port 2
Port 3
Pin Name
Input Type
Outpu
t Type
PD00/AD00 to
P07/AD07
P10/IN0/
AD00 to P17/
PPG3/AD15
P20/TIN0/A16 CMOS
(hysteresis)
to P27/INT7/
A23
CMOS
Function
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Generalpurpose I/O
port
P07
P06
P05
P04
P03
P02
P01
P00
External bus
AD07
AD06
AD05
AD04
AD03
AD02
AD01
AD00
Generalpurpose I/O
port
P17
P16
P15
P14
P13
P12
P11
P10
External bus
AD15
AD14
AD13
AD12
AD11
AD10
AD09
AD08
Resource
PPG3
PPG2
PPG1
PPG0
IN3
IN2
IN1
IN0
Generalpurpose I/O
port
P27
P26
P25
P24
P23
P22
P21
P20
External bus
A23
A22
A21
A20
A19
A18
A17
A16
Resource
INT7
INT6
INT5
INT4
TOT1
TIN1
TOT0
TIN0
P37
P36
P35
P34
P33
P32
P31
P30
ADTG
FRCK
−
−
−
SIN0
SCK0
SOT0
Generalpurpose I/O
port
−
−
−
P44
P43
P42
P41
P40
Resource
−
−
−
RX
TX
SOT1
SCK1
SIN1
P57
P56
P55
P54
P53
P52
P51
P50
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
−
−
−
−
P63
P62
P61
P60
−
−
−
−
INT3
INT2
INT1
INT0
Generalpurpose I/O
port
P30/ALE to
P37/ADTG/
CLK
Resource
Port 4
Port 5
P40/SIN1 to
P44/RX
P50/AN0 to
P57/AN7
Analog/
CMOS
(hysteresis)
Generalpurpose I/O
CMOS port
Analog
input pin
Port 6
P60/INT0 to
P63/INT3
CMOS
(hysteresis)
Generalpurpose I/O
CMOS port
Resource
Note:
CM44-10114-7E
Port 5 also serve as analog input pins. When using these ports as general-purpose ports, always set each
bit of the analog input enable register (ADER) corresponding to each pin of the ports to 0. ADER bit is 1
at a reset.
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CHAPTER 4 I/O PORT
4.2 Registers of I/O Port and Assignment of Pins Serving as External Bus
4.2
MB90495G Series
Registers of I/O Port and Assignment of Pins Serving as
External Bus
The registers related to I/O port setting are listed as follows.
■ Registers of I/O Ports
Table 4.2-1 lists the registers of each port.
Table 4.2-1 Registers of Each Port
Register Name
Read/Write
Address
Reset Value
Port 0 data register (PDR0)
R/W
000000H
XXXXXXXXB
Port 1 data register (PDR1)
R/W
000001H
XXXXXXXXB
Port 2 data register (PDR2)
R/W
000002H
XXXXXXXXB
Port 3 data register (PDR3)
R/W
000003H
XXXXXXXXB
Port 4 data register (PDR4)
R/W
000004H
XXXXXXXXB
Port 5 data register (PDR5)
R/W
000005H
XXXXXXXXB
Port 6 data register (PDR6)
R/W
000006H
XXXXXXXXB
Port 0 direction register (DDR0)
R/W
000010H
00000000B
Port 1 direction register (DDR1)
R/W
000011H
00000000B
Port 2 direction register (DDR2)
R/W
000012H
00000000B
Port 3 direction register (DDR3)
R/W
000013H
00000000B
Port 4 direction register (DDR4)
R/W
000014H
XXX00000B
Port 5 direction register (DDR5)
R/W
000015H
00000000B
Port 6 direction register (DDR6)
R/W
000016H
XXXX0000B
Analog input enable register (ADER)
R/W
00001BH
11111111B
R/W: Read/Write
X: Undefined value
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MB90495G Series
CHAPTER 4 I/O PORT
4.2 Registers of I/O Port and Assignment of Pins Serving as External Bus
■ Assignment of External Bus Pins
Ports 0 to 3 in the MB90495G series serve both as external buses and pins, and the following pin functions
are selected.
Table 4.2-2 indicates the assignment of external bus pins in each mode.
Table 4.2-2 Assignment of External Bus Pins
Function
Pin Name
External Data Bus Width
Single-chip Mode
8 bits
P07 to P00
16 bits
AD07 to AD00
P17 to P10
A15 to A08
AD15 to AD08
Flash Memory
Programming
D07D to D00
–
P27 to P20
A23 to A16
A07 to A00
P30
ALE
A16
P31
RD
CE
WRL
OE
P32
General-purpose I/O ports
P33
WRH
P34
HRQ
P35
HAK
P36
RDY
P37
CLK
PGM
Unused
Note:
CM44-10114-7E
The high addresses (A16 to A23) and WRL, WRH, HAK, HRQ, RDY and CLK can be used as generalpurpose I/O ports by function selection.
For details, see Section "3.10 External Access".
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CHAPTER 4 I/O PORT
4.3 Port 0
4.3
MB90495G Series
Port 0
Port 0 is a general-purpose I/O port that serves as an external address/data bus pin and
functions as a general-purpose I/O port in the single-chip mode.
The function as a general-purpose I/O port is mainly explained here. The configuration,
pin assignment, block diagram and registers for port 0 are shown below.
■ Configuration of Port 0
Port 0 consists of the following three elements:
• General-purpose I/O port, resource I/O pins (P00/AD00 to P07/AD07)
• Port 0 data register (PDR0)
• Port 0 direction register (DDR0)
■ Pin Assignment of Port 0
• Port 0 serves as an external bus pin. Therefore, if the external bus mode is set, port 0 cannot be used as a
general-purpose I/O port.
• If the single-chip mode is set, port 0 functions as a general-purpose I/O port.
Table 4.3-1 indicates the pin assignment for port 0.
Table 4.3-1 Pin Assignment of Port 0
Port
Name
I/O Type
Pin Name
Port Function
External Bus Function
Input
P00/AD00
P00
AD00
P01/AD01
P01
AD01
P02/AD02
P02
AD02
P03/AD03
P03
P04/AD04
P04
P05/AD05
P05
AD05
P06/AD06
P06
AD06
P07/AD07
P07
AD07
Port 0
Gen.eralpurpose I/O
AD03
AD04
Low address/
data bus I/O
CMOS
(hysteresis)
Output
CMOS
Circuit
Type
D
For the circuit type, see Section "1.7 I/O Circuit".
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CHAPTER 4 I/O PORT
4.3 Port 0
MB90495G Series
■ Block Diagram of Port 0 Pins (in Single Chip Mode)
Figure 4.3-1 Block Diagram of Port 0 Pins
Internal data bus
PDR (port data register)
PDR read
Output latch
P ch
PDR write
DDR
Pin
(port direction register)
N ch
Direction latch
DDR write
Standby control (SPL = 1)
DDR read
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and watch mode (SPL = 1)
■ Registers for Port 0 (in Single Chip Mode)
• The registers for port 0 are PDR0 (port 0 data register) and DDR0 (port 0 direction register).
• Each registers bits correspond to the pins of port 0 one to one.
Table 4.3-2 shows the correspondence between the registers and pins for port 0.
Table 4.3-2 Correspondence between Registers and Pins for Port 0
Port
Name
Bits of Related Registers and Corresponding Pins
PDR0, DDR0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Corresponding pin
P07
P06
P05
P04
P03
P02
P01
P00
Port 0
For the pin block diagram when the external access mode is set, see Section "3.10 External Access".
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CHAPTER 4 I/O PORT
4.3 Port 0
4.3.1
MB90495G Series
Registers for Port 0 (PDR0, DDR0)
The registers for port 0 are explained.
■ Function of Registers for Port 0
● Port 0 data register (PDR0)
• The port 0 data register indicates the state of the pins.
● Port 0 direction register (DDR0)
• The port 0 direction register sets input/output directions.
• If the bit corresponding to the pin is set to 1, port 0 functions as an output port. If the bit is set to 0, port
0 functions as an input port.
Table 4.3-3 shows the functions of the port 0 direction register (DDR0).
Table 4.3-3 Function of Registers for Port 0
Register Name
Data
At Read
0
The pin
state is
Low level.
0 is set for the output latch. When
the pin is an output port pin, the
Low level is output to the pin.
1
The pin
state is
High level.
1 is set for the output latch. When
the pin is an output port pin, the
High level is output to the pin.
0
The
direction
latch is 0.
The output buffer is set to OFF, and
the pin becomes an input port pin.
1
The
direction
latch is 1.
Port 0 data
register (PDR0)
Port 0 direction
register (DDR0)
At Write
Read/
Write
Address
Reset Value
R/W
000000H
XXXXXXXXB
R/W
000010H
00000000B
The output buffer is set to ON, and
the pin becomes an output port pin.
R/W: Read/Write
X: Undefined value
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CHAPTER 4 I/O PORT
4.3 Port 0
MB90495G Series
4.3.2
Operation of Port 0
The operation of port 0 is explained.
■ Operation of Port 0 (in Single Chip Mode)
● Operation for output port
• If the bit in the port 0 direction register (DDR0) corresponding to the output pin is set to 1, port 0
functions as an output port.
• When the output buffer is turned ON and output data is written to the port 0 data register (PDR0), the
data is retained in the output latch and output from the pin.
• When the PDR0 is read, the state of the output latch in the PDR0 is read.
Note:
If read modify write instructions (such as the bit set instruction) are used to read the PDR0, the pin set as
an output port by the DDR0 outputs the desired data. However, the pin set as an input port outputs data
after the input state is written to the output latch. When switching from the input port to the output port,
write data to the PDR0 and set the pin as an output port in the DDR0.
● Operation for input port
• If the bit in the DDR0 corresponding to the input pin is set to 1, port 0 functions as an input port.
• When the pin is an input port pin, the output buffer is set to OFF and the pin is set to the highimpedance state.
• When data is written to the PDR0, data is retained in the output latch in the PDR0, but not output to the
pin.
• When the PDR0 is read, the level value (Low or High) of the pin is read.
● Operation at reset
• When the CPU is reset, the value of the DDR0 is cleared. Consequently, all output buffers are set to
OFF (the pin becomes an input port pin), and the pin enters a high-impedance state.
• The PDR0 is not initialized by a reset. Therefore, when using port 0 as an output port, it is necessary to
set output data in the PDR0, and then set the bit in the DDR0 corresponding to the output pin to 1.
● Operation in stop mode, timebase timer mode or watch mode
• When the pin state specification bit of the low power consumption mode control register (LPMCR:SPL)
is 1, at a transition to the stop mode, timebase timer mode or watch mode, the pin enters the highimpedance state. Because the output buffer is set forcibly to OFF irrespective of the value of the DDR0.
Input is fixed to prevent leakage due to opening of input.
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4.3 Port 0
MB90495G Series
Table 4.3-4 State of Port 1 Pins
Pin Name
Normal Operations
Sleep Mode
Stop Mode, Timebase Timer Mode or
Watch Mode
SPL=0
P00 to P07
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O
port
SPL=1
Input cutoff/output
Hi-Z (pull-up resistor
disconnected)
SPL: Pin state specification bit of low power consumption mode control register (LPMCR:SPL)
Hi-Z: High impedance
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CHAPTER 4 I/O PORT
4.4 Port 1
MB90495G Series
4.4
Port 1
Port 1 is a general-purpose I/O port that serves as the resource I/O pin and the external
address/data bus pin. When the single-chip mode is set, use port 1 by switching
between the resource pin and the general-purpose I/O port.
The function as a general-purpose I/O port is mainly described here. The configuration,
pin assignment, block diagram of the pins, and registers for port 1 are shown below.
■ Configuration of Port 1
Port 1 consists of the following three elements:
• General-purpose I/O port, resource I/O pin, external address/data bus pin (P10/IN0/AD08 to P17/PPG3/
AD15)
• Port 1 data register (PDR1)
• Port 1 direction register (DDR1)
■ Pin Assignment of Port 1
• When the single-chip mode is set, use port 1 by switching between the resource pin and the generalpurpose I/O port.
• Since port 1 serves as an external bus pin, it cannot be used as a general-purpose I/O port and resource
pin when the external bus mode is set.
• Since port 1 serves as a resource pin, it cannot be used as a general-purpose I/O port when used as
resources.
• When using port 1 as the input pin of the resource, set the pin corresponding to the resource in the
DDR1 as an input port.
• When using port 1 as the output of the resource, set the output of the corresponding resource to
"enabled". Port 1 functions as the output pin of the resource regardless of the settings of the DDR1
Table 4.4-1shows the pin assignment of port 1.
Table 4.4-1 Pin Assignment of Port 1
Port
Name
Pin Name
Port Function
I/O Type
External Bus
Function
Resource
Input
P10/IN0/AD08
P10
AD08
IN0
P11/IN1/AD09
P11
AD09
IN1
P12/IN2/AD10
P12
AD10
IN2
P13/IN3/AD11
P13
IN3
P14/PPG0/AD12
P14
AD11 High address
AD12 data bus I/O
PPG0
P15/PPG1/AD13
P15
AD13
PPG1
P16/PPG2/AD14
P16
AD14
PPG2
P17/PPG3/AD15
P17
AD15
PPG3
Port 1
Generalpurpose I/O
port
Output
Circuit
Type
Input capture
input
CMOS
(hysteresis)
CMOS
D
PPG timer
output
For the circuit type, see Section "1.7 I/O Circuit".
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4.4 Port 1
MB90495G Series
■ Block Diagram of Port 1 Pins (in Single Chip Mode)
Figure 4.4-1 Block Diagram of Port 1 Pins
Resource input
Resource output
Port data register (PDR)
Resource output enable
Internal data bus
PDR read
P ch
Output latch
PDR write
Pin
Port direction register (DDR)
N ch
Direction latch
DDR write
Standby control (SPL = 1)
DDR read
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and watch mode (SPL = 1)
■ Registers for Port 1 (in Single Chip Mode)
• The registers for port 1 are PDR1 and DDR1.
• The bits composing each register correspond to the pins of port 1 one-to-one.
Table 4.4-2shows the correspondence between the registers and pins of port 1.
Table 4.4-2 Correspondence between Registers and Pins for Port 1
Port
Name
Bits of Related Registers and Corresponding Pins
PDR1, DDR1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Corresponding pin
P17
P16
P15
P14
P13
P12
P11
P10
Port 1
For the pin block diagram in the external access mode, see Section "3.10 External Access".
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CHAPTER 4 I/O PORT
4.4 Port 1
MB90495G Series
4.4.1
Registers for Port 1 (PDR1, DDR1)
The registers for port 1 are explained.
■ Function of Registers for Port 1 (in Single Chip Mode)
● Port 1 data register (PDR1)
• Port 1 data register indicates the state of the pins.
● Port 1 direction register (DDR1)
• The port 1 direction register sets the input/output directions.
• When the bit corresponding to the pin is set to 1, port 1 functions as an output port. When the bit is set
to 0, port 1 functions as an input port.
Table 4.4-3shows the functions of the registers for port 1.
Table 4.4-3 Function of Registers for Port 1
Register Name
Data
At Read
0
The pin
state is
Low level.
0 is set for the output latch. When
the pin is an output port pin, the
Low level is output to the pin.
1
The pin
state is
High level.
1 is set for the output latch. When
the pin is an output port pin, the
High level is output to the pin.
0
The
direction
latch is 0.
The output buffer is set to OFF, and
the pin becomes an input port pin.
1
The
direction
latch is 1.
Port 1 data
register (PDR1)
Port 1 direction
register (DDR1)
At Write
Read/
Write
Register
Address
Reset Value
R/W
000001H
XXXXXXXXB
R/W
000011H
00000000B
The output buffer is set to ON, and
the pin becomes an output port pin.
R/W: Read/Write
X: Undefined value
References:
CM44-10114-7E
• When using port 1 as the input pin of the resource, clear the bit in the DDR1 corresponding to the
input pin of the resource to 0 and set the input pin as an input port.
• When using port 1 as the output pin of the resource, set the output of the corresponding resource to
"enabled". Port 1 functions as the output pin of the resource regardless of the settings of the DDR1.
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CHAPTER 4 I/O PORT
4.4 Port 1
4.4.2
MB90495G Series
Operation of Port 1
The operation of port 1 is explained.
■ Operation of Port 1 (in Single Chip Mode)
● Operation of output port
• When the bit in the port 1 direction register (DDR1) corresponding to the output pin is set to 1, port 0
functions as an output port.
• When the output buffer is turned ON and output data is written to the port 1 data register (PDR1), the
data is retained in the output latch and output from the pin.
• When the PDR1 is read, the state of the output latch in the PDR1 is read.
Note:
If read modify write instructions (such as the bit set instruction) are used to read the PDR, the pin set as
an output port by the DDR outputs the desired data. However, the pin set as an input port outputs data
after the input state is written to the output latch. When switching from the input port to the output port,
write data to the PDR and set the pin as an output port in the DDR.
● Operation of input port
• If the bit in the DDR corresponding to the input pin is set to 1, port 1 functions as an input port.
• The output buffer is turned OFF and the pin enters the high impedance state.
• When data is written to the PDR1, it is retained in the output latch in the PDR1 but not output to the pin.
• When the PDR1 is read, the level value (Low or High) of the pin is read.
● Operation of resource output
• When using port 1 as the output pin of the resource, set the resource output to "enabled".
• Since the resource output is preferred enabled, the resource output functions regardless of the settings of
the DDR1.
• When the resource output set to "enabled", the output latch value in the PDR1 or the output state of the
resource is read depending on the port 1 direction register (DDR1).
● Operation of resource input
• The state of the pin that serves as the resource input is input to the resource.
• When using port 1 as the input pin of the resource, clear the bit in the DDR1 corresponding to the input
pin of the resource to 0 and set the input pin as an input port.
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CHAPTER 4 I/O PORT
4.4 Port 1
MB90495G Series
● Reading value of the port data register (PDR)
The value obtained at the time of reading the port 1 data register (PDR1) depends on the state of port 1
direction register (DDR1) and the state of peripheral functions connected to the pins. Table 4.4-4 shows the
values obtained for each combination.
Table 4.4-4 Reading Value of the Port 1 Data Register (PDR1)
Output enable of peripheral
functions
DDR1
Read Value
0 (input)
Enabled
Output value from peripheral
functions
1 (output)
Enabled
Value of output latch (PDR1)
0 (input)
Disabled
Pin state (PORT input)
1 (output)
Disabled
Value of output latch (PDR1)
● Operation at reset
• When the CPU is reset, the value of the DDR1 is cleared to 0. Consequently, all output buffers are set to
OFF (the pin becomes an input port pin), and the pin enters the high-impedance state.
• The PDR1 is not initialized by reset. Therefore, when using port 1 as an output port, it is necessary to set
output data in the PDR1, and then set the bit in the DDR1 corresponding to the output pin to 1, and then,
to output.
● Operation in stop mode, timebase timer mode or watch mode
• When the pin state specification bit of the low power consumption mode control register (LPMCR:SPL)
is 1, at a transition to the stop mode, timebase timer mode or watch mode, the pin enters the highimpedance state. Because the output buffer is set forcibly to OFF irrespective of the value of the DDR1.
Input is fixed to prevent leakage due to opening of input.
Table 4.4-5shows the state of the port 1 pins.
Table 4.4-5 State of Port 1 Pins
Pin Name
Normal Operation
Sleep Mode
Stop Mode, Timebase Timer Mode or Watch
Mode
SPL=0
P10/IN0 to
P17/PPG3
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O
port
SPL=1
Input cut off, and
output becomes Hi-Z
(Pull-up resistor
disconnected)
SPL: Pin state specification bit of low power consumption mode control register (LPMCR:SPL)
Hi-Z: High impedance
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4.4 Port 1
Note:
202
MB90495G Series
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode,
watch mode or timebase timer mode, disable the output of peripheral functions, and set the STP bit of the
low-power consumption mode control register (LPMCR) to 1 or set the TMD bit to 0.
This applies to the following pins:
P14/PPGO/AD12, P15/PPG1/AD13, P16/PPG2/AD14, P17/PPG3/AD15
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CHAPTER 4 I/O PORT
4.5 Port 2
MB90495G Series
4.5
Port 2
Port 2 is a general-purpose I/O port that serves as the resource I/O pin and external
address bus pin. Use port 2 by switching between the resource pin and the generalpurpose I/O port.
The function as a general-purpose I/O port is mainly described here. The configuration,
pin assignment, block diagram of the pins, and registers for port 2 are shown below.
■ Configuration of Port 2
Port 2 consists of the following four elements:
• General-purpose I/O port, resource I/O pin, external address bus pin (P20/TIN0/A16 to P27/INT7/A23)
• Port 2 data register (PDR2)
• Port 2 direction register (DDR2)
• High address control register (HACR)
■ Pin Assignment of Port 2
• If the single-chip mode is set, use port 2 by switching between the resource pin or external address bus
pin and the general-purpose I/O port.
• Since port 2 serves as resource pin, when used as a resource pin port 2 cannot be used as an external
address bus pin and general-purpose I/O port.
• Since port 2 serves as an external bus pin, when set to the address output pin, port 2 cannot be used as
resource pin and a general-purpose I/O port.
• When using port 2 as the input pin of the resource, set the pin corresponding to the resource in the
DDR2 as an input port.
• When using port 2 as the output of the resource, set the output of the corresponding resource to
"enabled". Port 2 functions as the output pin of the resource regardless of the settings of the DDR2.
Table 4.5-1 shows the pin assignment for port 2.
Table 4.5-1 Pin Assignment of Port 2
Port
Name
Port 2
Pin Name
Port Function
I/O Type
External Bus
Function
Resource
Input
P20/TIN0/A16
P20
A16
TIN0
16-bit reload
timer 0 input
P21/TOT0/A17
P21
A17
TOT0
16-pit reload
timer 0 output
P22/TIN1/A18
P22
A18
TIN1
16-bit reload
timer 1 input
TOT1
CMOS
16-bit reload (hysteresis)
timer 1 output
Generalpurpose I/O
port
A19
Address bus
output
P23/TOT1/A19
P23
P24/INT4/A20
P24
A20
INT4
P25/INT5/A21
P25
A21
INT5
P26/INT6/A22
P26
A22
INT6
P27/INT7/A23
P27
A23
INT7
Output
CMOS
Circuit
Type
D
External
interrupt input
For the circuit type, see Section "1.7 I/O Circuit".
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4.5 Port 2
MB90495G Series
■ Block Diagram of Pins of Port 2 (General-purpose I/O Port)
Figure 4.5-1 Block Diagram of Pins of Port 2
Resource input
Resource output
Internal data bus
Port data register (PDR)
Resource output enable
PDR read
P ch
Output latch
PDR write
Pin
Port direction register (DDR)
N ch
Direction latch
DDR write
Standby control (SPL = 1)
DDR read
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and watch mode (SPL = 1)
■ Registers for Port 2
• The registers for port 2 are the port 2 data register (PDR2), port 2 direction register (DDR2) and high
address control register (HACR).
• The HACR sets the output of external addresses (A16 to A23) to enabled or disabled. If the output of
external addresses is set to "enabled", port 2 cannot be used as a resource pin and general-purpose I/O
port.
• shows the correspondence between the registers and pins of port 2.
Table 4.5-2 shows the correspondence between the registers and pins of port 2.
Table 4.5-2 Correspondence between Registers and Pins for Port 2
Port
Name
Bits of Related Registers and Corresponding Pins
PDR2, DDR2, HACR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Corresponding pin
P27
P26
P25
P24
P23
P22
P21
P20
Port 2
For the pin block diagram in the external access mode, see Section "3.10 External Access".
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CHAPTER 4 I/O PORT
4.5 Port 2
MB90495G Series
4.5.1
Registers for Port 2 (PDR2, DDR2)
The registers for port 2 are explained.
■ Function of Registers for Port 2
● Port 2 data register (PDR2)
Port 2 data register indicates the input/output state of the pins.
● Port 2 direction register (DDR2)
• The port 2 direction register sets the input/output directions.
• When the bit corresponding to the pin is set to 1, port 1 functions as an output port. When the bit is set
to 0, port 1 functions as an input port.
● High address control register (HACR)
• The high address control register (HACR) sets the resource pins, general-purpose I/O ports and external
address output pins (A16 to A23).
• If the bits corresponding to the external address output pins (A16 to A23) are set to 0, port 2 functions as
an external address output pin. If the bits are set to 1, port 2 functions as the output pin of the resource
and general-purpose I/O port.
Table 4.5-3 shows the functions of the registers for port 2.
Table 4.5-3 Function of Registers for Port 2
Register Name
Data
At Read
0
The pin
state is
Low level.
0 is set for the output latch, and
when the pin is an output port pin,
the Low level is output to the pin.
1
The pin
state is
High level.
1 is set for the output latch, and
when the pin is an output port pin,
the High level is output to the pin.
0
The
direction
latch is 0.
The output buffer is set to OFF, and
the pin becomes an input port pin.
1
The
direction
latch is 1.
0
External address output
1
General-purpose I/O port pin
Port 2 data
register (PDR2)
Port 2 direction
register (DDR2)
High address
control register
(HACR)
At Write
Read/
Write
Register
Address
Reset Value
R/W
000002H
XXXXXXXXB
R/W
000012H
00000000B
W
0000A6H
00000000B
The output buffer is set to ON, and
the pin becomes an output port pin.
R/W: Read/Write
X: Undefined value
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CHAPTER 4 I/O PORT
4.5 Port 2
References:
206
MB90495G Series
• When using port 2 as the input pin of the resource, clear the bit in the DDR2 corresponding to the
input pin of the resource to 0 and set the input pin as an input port.
• When using port 2 as the output pin of the resource, set the output of the corresponding resource to
"enabled". Port 2 functions as the output pin of the resource regardless of the settings of the DDR2.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 4 I/O PORT
4.5 Port 2
MB90495G Series
4.5.2
Operation of Port 2
The operation of port 2 is explained.
■ Operation of Port 2 (General-purpose I/O Port)
● Operation of output port
• When the bit in the port 2 direction register (DDR2) corresponding to the output pin is set to 1, port 0
functions as an output port.
• When the output buffer is turned ON and output data is written to the port 2 data register (PDR2), the
data is retained in the output latch and output from the pin.
• When the PDR2 is read, the state of the output latch in the PDR2 is read.
Note:
If read modify write instructions (such as the bit set instruction) are used to read the PDR, the pin set as
an output port by the DDR outputs the desired data. However, the pin set as an input port outputs data
after the input state is written to the output latch. When switching from the input port to the output port,
write data to the PDR and set the pin as an output port in the DDR.
● Operation of input port
• If the bit in the DDR2 corresponding to the input pin is set to 1, port 2 functions as an input port.
• The output buffer is turned OFF and the pin enters the high impedance state.
• When data is written to the PDR2, it is retained in the output latch in the PDR2 but not output to the pin.
• When the PDR2 is read, the level value (Low or High) of the pin is read.
● Operation of resource output
• When using port 2 as the output pin of the resource, set the resource output to "enabled".
• Since the resource output is preferred enabled, the resource output functions regardless of the settings of
the DDR2.
• When the resource output set to "enabled", the output latch value in the PDR2 or the output state of the
resource is read depending on the port 2 direction register (DDR2).
● Operation of resource input
• The state of the pin that serves as the input of the resource is input to the resource.
• When using port 2 as the input pin of the resource, clear the bit in the DDR2 corresponding to the input
pin of the resource to 0 and set the input pin to an input port.
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4.5 Port 2
MB90495G Series
● Reading value of the port data register (PDR)
The value obtained at the time of reading the port 2 data register (PDR2) depends on the state of port 2
direction register (DDR2) and the state of peripheral functions connected to the pins. Table 4.5-4 shows the
values obtained for each combination.
Table 4.5-4 Reading Value of the Port 2 Data Register (PDR2)
Output enable of peripheral
functions
DDR2
Read Value
0 (input)
Enabled
Output value from peripheral
functions
1 (output)
Enabled
Value of output latch (PDR2)
0 (input)
Disabled
Pin state (PORT input)
1 (output)
Disabled
Value of output latch (PDR2)
● Operation at reset
• When the CPU is reset, the value of the DDR2 is initialized to 0. Consequently, all output buffers are set
to OFF (the pin becomes an input port pin), and the pin enters the high-impedance state.
• The PDR2 is not initialized by reset. Therefore, when using port 2 as an output port, it is necessary to set
output data in the PDR2, and then set the bit in the DDR2 corresponding to the output pin to 1, and then,
to output.
● Operation in stop mode, timebase timer mode or watch mode
• When the pin state specification bit of the low power consumption mode control register (LPMCR:SPL)
is 1, at a transition to the stop mode, timebase timer mode or watch mode, the pin enters the highimpedance state. Because the output buffer is set forcibly to OFF irrespective of the value of the DDR2.
Table 4.5-5 shows the state of the port 2 pins.
Table 4.5-5 State of Port 2 Pins
Pin Name
Normal Operation
Sleep Mode
Stop Mode, Timebase Timer Mode or
Watch Mode
SPL=0
P20/TIN0 to
P27/INT7
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O
port
SPL=1
Input cut off, and
output becomes Hi-Z
SPL: Pin state specification bit of low power consumption mode control register (LPMCR:SPL)
Hi-Z: High impedance
Note:
208
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode,
watch mode or timebase timer mode, disable the output of peripheral functions, and set the STP bit of the
low-power consumption mode control register (LPMCR) to 1 or set the TMD bit to 0.
This applies to the following pins:
P21/TOT0/A17, P23/TOT1/A19
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CM44-10114-7E
CHAPTER 4 I/O PORT
4.6 Port 3
MB90495G Series
4.6
Port 3
Port 3 is a general-purpose I/O port that serves as the resource I/O pin and external bus
control pin. Use port 3 by switching between the resource pin or external bus control
pin and the general-purpose I/O port.
The function as a general-purpose I/O port is mainly described here. The configuration,
pin assignment, block diagram of the pins, and registers for port 3 are shown below.
■ Configuration of Port 3
Port 3 consists of the following four elements:
• General-purpose I/O port, resource I/O pin, external bus control pins (P30/SOT0/ALE to P37/ADTG/CLK)
• Port 3 data register (PDR3)
• Port 3 direction register (DDR3)
• Bus control signal select register (ECSR)
■ Pin Assignment of Port 3
• Use port 3 by switching between the resource pin external bus control pin and the general-purpose I/O
port.
• Since port 3 serves as a resource pin, when used as a resource pin, port 3 cannot be used as an external
bus control pin and general-purpose I/O port.
• Since port 3 serves as an external bus control pin, the pin set as bus control signal I/O in the ECSR
cannot be used as a resource pin general-purpose I/O port.
• When using port 3 as the resource input pin, set the pin corresponding to the resource in the DDR3 as an
input port.
• When using port 3 as the output pin of the resource, set the output of the corresponding resource to
"enabled". Port 3 functions as the output pin of the resource regardless of the settings of the DDR3.
Table 4.6-1 shows the pin assignment of port 3.
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CHAPTER 4 I/O PORT
4.6 Port 3
MB90495G Series
Table 4.6-1 Pin Assignment of Port 3
Port
Name
Pin Name
I/O Type
External Bus
Function
Port Function
Resource
Input
P30/SOT0/ALE
P30
ALE
Address
latch enable
output
SOT0
UART0 serial
data output
P31/SCK0/RD
P31
RD
Read strobe
output
SCK0
UART0 serial
clock I/O
WRL
Write strobe
output for
lower 8 bits
of data bus
SIN0
WRH
Write strobe
output for
higher 8 bits
of data bus
−
−
−
−
−
FRCK
Count clock
input for freerun timer
ADTG
External
trigger input
for A/D
converter
P32/SIN0/WRL
P33/WRH
P32
P33
Generalpurpose I/O
port
Port 3
P34/HRQ
P34
HRQ
Hold request
input
P35/HAK
P35
HAK
Hold
acknowledge
output
P36/FRCK/RDY
P36
RDY
Clock output
P37/ADTG/CLK P37
CLK
UART0 serial
data input
−
CMOS
(hysteresis)
Ready input
Output
Circuit
Type
CMOS
E
For the circuit type, see Section "1.7 I/O Circuit".
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CHAPTER 4 I/O PORT
4.6 Port 3
MB90495G Series
■ Block Diagram of Pins of Port 3
Figure 4.6-1 Block Diagram of Pins of Port 3
Resource input
Resource output
Port data register (PDR)
Resource output enable
Internal data bus
PDR read
P ch
Output latch
PDR write
Pin
Port direction register (DDR)
N ch
Direction latch
DDR write
Standby control (SPL = 1)
DDR read
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and watch mode (SPL = 1)
■ Registers for Port 3
• The registers for port 3 are PDR3 and DDR3.
• The ECSR sets the input/output of external bus control signals (WRL/WRH,HRQ/HAK,RDY,CLK)
"enabled" or "disabled". If the input/output of external bus control signals is set to "enabled", port 3
cannot be used as a resource pin and general-purpose I/O port.
• The bits composing each register correspond to the pins of port 3 one-to-one.
Table 4.6-2 shows the correspondence between the registers and pins of port 3.
Table 4.6-2 Correspondence between Registers and Pins for Port 3
Port
Name
Port 3
Bits of Related Registers and Corresponding Pin
PDR3, DDR3
bit 7
bit 6
ECSR
CKE
RYE
Corresponding pin
P37
P36
bit 5
bit 4
HDE
P35
bit 3
bit 2
bit 1
−
WRE
P34
P33
P32
bit 0
P31
P30
For the pin block diagram in the external access mode, see Section "3.10 External Access".
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CHAPTER 4 I/O PORT
4.6 Port 3
4.6.1
MB90495G Series
Registers for Port 3 (PDR3, DDR3)
The registers for port 3 are explained.
■ Function of Registers for Port 3
● Port 3 data register (PDR3)
• Port 3 data register indicates the state of the pins.
● Port 3 direction register (DDR3)
• The port 3 direction register sets the input/output directions.
• When the bit corresponding to the pin is set to 1, port 1 functions as an output port. When the bit is set
to 0, port 1 functions as an input port.
● Bus control signal select register (ECSR)
• The bus control signal select register (ECSR) sets the resource pins, general-purpose I/O ports and bus
control signal I/O pins (WRL/WRH, HRQ/HAK, RDY, CLK).
Table 4.6-3 shows the functions of the registers for port 3.
Table 4.6-3 Function of Registers for Port 3
Register Name
Data
At Read
0
The pin
state is
Low level.
0 is set for the output latch, and
when the pin is an output port pin,
the Low level is output to the pin.
1
The pin
state is
High level.
1 is set for the output latch, and
when the pin is an output port pin,
the High level is output to the pin.
0
The
direction
latch is 0.
The output buffer is set to OFF, and
the pin becomes an input port pin.
1
The
direction
latch is 1.
Port 3 data
register (PDR3)
Port 3 direction
register (DDR3)
At Write
Read/
Write
Register
Address
Reset Value
R/W
000003H
XXXXXXXXB
R/W
000013H
00000000B
The output buffer is set to ON, and
the pin becomes an output port pin
R/W: Read/Write
X: Undefined value
For details of the ECSR, see Section "3.10.3 Bus Control Signal Select Register (ECSR)".
References:
212
• When using port 3 as the input pin of the resource, clear the bit in the (DDR3) corresponding to the
input pin of the resource to 0 and set the input pin as an input port.
• When using port 3 as the output pin of the resource, set the output of the corresponding resource to
"enabled". Port 2 functions as the output pin of the resource regardless of the settings of the DDR3.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 4 I/O PORT
4.6 Port 3
MB90495G Series
4.6.2
Operation of Port 3
The operation of port 3 is explained.
■ Operation of Port 3
● Operation of output port
• When the bit in the port 3 direction register (DDR3) corresponding to the output pin is set to 1, port 3
functions as an output port.
• When the output buffer is turned ON and output data is written to the port 3 data register (PDR3), the
data is retained in the output latch and output from the pin.
• When the PDR3 is read, the state of the output latch in the PDR3 is read.
Note:
If read modify write instructions (such as the bit set instruction) are used to read the port data register
(PDR), the pin set as an output port by the port direction register (DDR) outputs the desired data.
However, the pin set as an input port outputs data after the input state is written to the output latch. When
switching from the input port to the output port, write data to the PDR and set the pin as an output port in
the DDR.
● Operation of input port
• If the bit in the DDR3 corresponding to the input pin is set to 0, port 3 functions as an input port.
• The output buffer is turned OFF and the pin enter the high impedance state.
• When data is written to the PDR3, it is retained in the output latch in the PDR3 but not output to the pin.
• When the PDR3 is read, the level value (Low or High) of the pin is read.
● Operation of resource output
• When using port 3 as the output pin of the resource, set the resource output to "enabled".
• Since the resource output is preferred enabled, the resource output functions regardless of the settings of
the DDR3.
• When the resource output set to "enabled", the output latch value in the PDR3 or the output state of the
resource is read depending on the port 3 direction register (DDR3).
● Operation of resource input
• The state of the pin that serves as a resource is input to the resource.
• When using port 3 as the input pin of the resource, clear the bit in the DDR3 corresponding to the input
pin of the resource to 0 and set the input pin as an input port.
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CHAPTER 4 I/O PORT
4.6 Port 3
MB90495G Series
● Reading value of the port data register (PDR)
The value obtained at the time of reading the port 3 data register (PDR3) depends on the state of port 3
direction register (DDR3) and the state of peripheral functions connected to the pins. Table 4.6-4 shows the
values obtained for each combination.
Table 4.6-4 Reading Value of the Port 3 Data Register (PDR3)
Output enable of peripheral
functions
DDR3
Read Value
0 (input)
Enabled
Output value from peripheral
functions
1 (output)
Enabled
Value of output latch (PDR3)
0 (input)
Disabled
Pin state (PORT input)
1 (output)
Disabled
Value of output latch (PDR3)
● Operation at reset
• When the CPU is reset, the value of the DDR3 is cleared to 0. Consequently, all output buffers are set to
OFF (the pin becomes an input port pin), and the pin enters the high-impedance state.
• The PDR3 is not initialized by reset. Therefore, when using port 3 as an output port, it is necessary to set
output data in the PDR3, and then set the bit in the DDR3 corresponding to the output pin to 1 and to
output.
● Operation in stop mode, timebase timer mode or watch mode
• When the pin state specification bit of the low power consumption mode control register (LPMCR:SPL)
is 1, at a transition to the stop mode, timebase timer mode or watch mode, the pin enters the highimpedance state. The output buffer is set forcibly to OFF irrespective of the value of the DDR3 register.
Table 4.6-5 shows the state of the port 3 pins.
Table 4.6-5 State of Port 3 Pins
Pin Name
Normal Operation
Sleep Mode
Stop Mode, Timebase Timer Mode or
Watch Mode
SPL=0
P30/SOT0 to
P37/ADTG
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O
port
SPL=1
Input cut off, and
output becomes Hi-Z
SPL: Pin state specification bit of low power consumption mode control register (LPMCR:SPL)
Hi-Z: High impedance
Note:
214
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode,
watch mode or timebase timer mode, disable the output of peripheral functions, and set the STP bit of the
low-power consumption mode control register (LPMCR) to 1 or set the TMD bit to 0.
This applies to the following pins:
P30/SOT0/ALE, P31/SCK0/RD
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 4 I/O PORT
4.7 Port 4
MB90495G Series
4.7
Port 4
Port 4 is a general-purpose I/O port that serves as the resource I/O. Use port 4 by
switching between the resource pin and the general-purpose I/O port.
The function as a general-purpose I/O port is mainly described here. The configuration,
pin assignment, block diagram of the pins, and registers for port 4 are shown below.
■ Configuration of Port 4
Port 4 consists of the following three elements:
• General-purpose I/O port, resource I/O pin (P40/SIN1 to P44/RX)
• Port 4 data register (PDR4)
• Port 4 direction register (DDR4)
■ Pin Assignment of Port 4
• Use port 4 by switching between the resource pin and the general-purpose I/O port.
• Since port 4 serves as a resource pin, it cannot be used as a general-purpose I/O port when used as a
resource.
• When using port 4 as the input pin of the resource, set the pin corresponding to the resource in the
DDR4 as an input port.
• When using port 4 as the output pin of the resource, set the output of the corresponding resource to
"enabled". Port 4 functions as the output pin of the resource regardless of the settings of the DDR4.
Table 4.7-1 shows the pin assignment of port 4.
Table 4.7-1 Pin Assignment of Port 4
Port
Name
I/O Type
Pin Name
Port Function
Resource
Input
P40/SIN1
P40
SIN1
UART1 serial
data input
P41/SCK1
P41
SCK1
UART1 serial
clock I/O
P42/SOT1
P42
SOT1
UART1 serial
data output
Port 4
Generalpurpose I/O
port
P43/TX
P43
TX
CAN
controller
send output
P44/RX
P44
RX
CAN
controller
receive input
CMOS
(hysteresis)
Output
CMOS
Circuit
Type
D
For the circuit type, see Section "1.7 I/O Circuit".
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CHAPTER 4 I/O PORT
4.7 Port 4
MB90495G Series
■ Block Diagram of Pins of Port 4
Figure 4.7-1 Block Diagram of Pins of Port 4
Resource input
Resource output
Internal data bus
Port data register (PDR)
Resource output enable
PDR read
P ch
Output latch
PDR write
Pin
Port direction register (DDR)
N ch
Direction latch
DDR write
Standby control (SPL = 1)
DDR read
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and watch mode (SPL = 1)
■ Registers for Port 4
• The registers for port 4 are PDR4 and DDR4.
• The bits composing each register correspond to the pins of port 4 one-to-one.
Table 4.7-2 shows the correspondence between the registers and pins of port 4.
Table 4.7-2 Correspondence between Registers and Pins for Port 4
Port
Name
Bits of Related Registers and Corresponding Pins
PDR4, DDR4
−
−
−
bit 4
bit 3
bit 2
bit 1
bit 0
Corresponding pin
−
−
−
P44
P43
P42
P41
P40
Port 4
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CHAPTER 4 I/O PORT
4.7 Port 4
MB90495G Series
4.7.1
Registers for Port 4 (PDR4, DDR4)
The registers for port 4 are explained.
■ Function of Registers for Port 4
● Port 4 data register (PDR4)
• Port 4 data register indicates the state of the pins.
● Port 4 direction register (DDR4)
• The port 4 direction register sets the input/output directions.
• When the bit corresponding to the pin is set to 1, port 4 functions as an output port. When the bit is set
to 0, port 4 functions as an input port.
Table 4.7-3 shows the functions of the registers for port 4.
Table 4.7-3 Function of Registers for Port 4
Register Name
Data
At Read
0
The pin
state is
Low level.
0 is set for the output latch. When
the pin is an output port pin, the
Low level is output to the pin.
1
The pin
state is
High level.
1 is set for the output latch. When
the pin is an output port pin, the
High level is output to the pin.
0
The
direction
latch is 0.
The output buffer is set to OFF, and
the pin becomes an input port pin.
1
The
direction
latch is 1.
Port 4 data
register (PDR4)
Port 4 direction
register (DDR4)
At Write
Read/
Write
Register
Address
Reset Value
R/W
000004H
XXXXXXXXB
R/W
000014H
XXX00000B
The output buffer is set to ON, and
the pin becomes an output port pin.
R/W: Read/Write
X: Undefined value
References:
CM44-10114-7E
• When using port 4 as the input pin of the resource, clear the bit in the DDR4 corresponding to the
input pin of the resource to 0 and set the input pin as an input port.
• When using port 4 as the output pin of the resource, set the output of the corresponding resource to
"enabled". Port 4 functions as the output pin of the resource regardless of the settings of the DDR4.
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CHAPTER 4 I/O PORT
4.7 Port 4
4.7.2
MB90495G Series
Operation of Port 4
The operation of port 4 is explained.
■ Operation of Port 4
● Operation of output port
• When the bit in the port 4 direction register (DDR4) corresponding to the output pin is set to 1, port 4
functions as an output port.
• When the output buffer is turned ON and output data is written to the port 4 data register (PDR4), the
data is retained in the output latch and output from the pin.
• When the port 4 data register (PDR4) is read, the state of the output latch in the port 4 data register
(PDR4) is read.
Note:
If read modify write instructions (such as the bit set instruction) are used to read the PDR, the pin set as
an output port by the DDR outputs the desired data. However, the pin set as an input port outputs data
after the input state is written to the output latch. When switching from the input port to the output port,
write data to the PDR and set the pin as an output port in the DDR.
● Operation of input port
• If the bit in the DDR4 corresponding to the input pin is set to 1, port 4 functions as an output port.
• The output buffer is turned OFF and the pin enters the high impedance state.
• When data is written to the PDR4, it is retained in the output latch in the PDR4 but not output to the pin.
• When the PDR4 is read, the level value (Low or High) of the pin is read.
● Operation of resource output
• When using port 4 as the output pin of the resource, set the output of the corresponding resource to
"enabled".
• Since the resource output is preferred enabled, the resource output functions regardless of the settings of
the DDR4.
• When the pin state is read with the resource output set to "enabled", the output state of the resource is
read
● Operation of resource input
• The state of the pin that serves as the input of the resource is input to the resource.
• When using port 4 as the input pin of the resource, clear the bit in the DDR4 corresponding to the input
pin of the resource to 0 and set the input pin as an input port.
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CHAPTER 4 I/O PORT
4.7 Port 4
MB90495G Series
● Reading value of the port data register (PDR)
The value obtained at the time of reading the port 4 data register (PDR4) depends on the state of port 4
direction register (DDR4) and the state of peripheral functions connected to the pins. Table 4.7-4 shows the
values obtained for each combination.
Table 4.7-4 Reading Value of the Port 4 Data Register (PDR4)
Output enable of peripheral
functions
DDR4
Read Value
0 (input)
Enabled
Output value from peripheral
functions
1 (output)
Enabled
Output value from peripheral
functions
0 (input)
Disabled
Pin state (PORT input)
1 (output)
Disabled
Value of output latch (PDR4)
● Operation at reset
• When the CPU is reset, the value of the DDR4 is initialized to 0. Consequently, all output buffers are set
to OFF (the pin becomes an input port pin), and the pin enters the high-impedance state.
• The PDR4 is not initialized by reset. Therefore, when using port 4 as an output port, it is necessary to set
output data in the PDR4, and then set the bit in the DDR4 corresponding to the output pin to 1 and to
output.
● Operation in stop mode, timebase timer mode and watch mode
If the pin state specify bit (SPL) of the low-power consumption mode control register (LPMCR) is set to
"1" when the CPU operation mode switches to stop mode, timebase timer mode or watch mode, the pin
enters the high-impedance state. In this case, the output buffer is forcibly set to "off" regardless of the
values of the Port 4 direction register (DDR4).
Table 4.7-5 shows the state of the port 4 pins.
Table 4.7-5 State of Port 4 Pins
Pin Name
Normal Operation
Sleep Mode
Stop Mode, Timebase Timer Mode or
Watch Mode
SPL=0
P40/SIN1/ to
P47/RX
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O
port
SPL=1
Input cut off, and
output becomes Hi-Z
(Pull-up resistor
disconnected)
SPL: Pin state specification bit of low power consumption mode control register (LPMCR:SPL)
Hi-Z: High impedance
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CHAPTER 4 I/O PORT
4.8 Port 5
4.8
MB90495G Series
Port 5
Port 5 is a general-purpose I/O port that serves as the analog input pin. Use port 5 by
switching between the analog input pin and the general-purpose I/O port.
The function as a general-purpose I/O port is mainly described here. The configuration,
pin assignment, block diagram of the pins, and registers for port 5 are shown below.
■ Configuration of Port 5
Port 5 consists of the following four elements:
• General-purpose I/O port, analog input pins (P50/AN0 to P57AN7)
• Port 5 data register (PDR5)
• Port 5 direction register (DDR5)
• Analog input enable register (ADER)
■ Pin Assignment of Port 5
• Use port 5 by switching between the analog input pin and the general-purpose I/O port.
• Since port 5 serves as an analog input pin, it cannot be used as a general-purpose I/O port when used as
an analog input pin.
• When using port 5 as an analog input pin, set the pin corresponding to the analog input in the DDR5 as
an input port.
• When using port 5 as a general-purpose I/O port, do not input any analog signal.
Table 4.8-1 shows the pin assignment of port 5.
Table 4.8-1 Pins Assignment of Port 5
Port
Name
Pin
Name
I/O Type
Port Function
Resource
P50/AN0
P50
AN0
Analog input channel 0
P51/AN1
P51
AN1
Analog input channel 1
P52/AN2
P52
AN2
Analog input channel 2
P53/AN3
P53
AN3
Analog input channel 3
P54/AN4
P54
AN4
Analog input channel 4
P55/AN5
P55
AN5
Analog input channel 5
P56/AN6
P56
AN6
Analog input channel 6
P57/AN7
P57
AN7
Analog input channel 7
Port 5
Generalpurpose I/O
port
Input
Output
CMOS
(hysteresis/
analog input)
CMOS
Circuit
Type
E
For the circuit type, see Section "1.7 I/O Circuit".
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CHAPTER 4 I/O PORT
4.8 Port 5
MB90495G Series
■ Block Diagram of Pins of Port 5
Figure 4.8-1 Block Diagram of Pins of Port 5
Analog input
ADER
Internal data bus
PDR (port data register)
PDR read
Output latch
P ch
PDR write
DDR
Pin
(port direction register)
N ch
Direction latch
DDR write
Standby control (SPL = 1)
DDR read
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and watch mode (SPL = 1)
■ Registers for Port 5
• The registers for port 5 are PDR5, DDR5, and ADER.
• The ADER sets input of an analog signal to the analog input pin to "enabled" or "disabled".
• The bits composing each register correspond to the pins of port 5 one-to-one.
Table 4.8-2 shows the correspondence between the registers and pins of port 1.
Table 4.8-2 Correspondence between Registers and Pins for Port 5
Port
Name
Bits of Related Registers and Corresponding Pins
PDR5, DDR5
Port 5
ADER
Corresponding pin
CM44-10114-7E
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
P57
P56
P55
P54
P53
P52
P51
P50
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CHAPTER 4 I/O PORT
4.8 Port 5
4.8.1
MB90495G Series
Registers for Port 5 (PDR5, DDR5, ADER)
The registers for port 5 are explained.
■ Function of Registers for Port 5
● Port 5 data register (PDR5)
• Port 5 data register indicates the state of the pins.
● Port 5 direction register (DDR5)
• The port 5 direction register sets the input/output directions.
• When the bit corresponding to the pin is set to 1, port 5 functions as an output port. When the bit is set
to 0, port 5 functions as an input port.
● Analog input enable register (ADER)
• The analog input enable register (ADER) sets the general-purpose I/O ports and analog input pin in unit
of ports.
• When the ADE bit corresponding to the analog input pin is set to 1, port 5 functions as an analog input
pin. When the bit is set to 0, port 5 functions as a general-purpose I/O port.
Table 4.8-3 shows the functions of the registers for port 5.
Note:
222
When a middle-level signal is input with port 5 set as an input port, input leakage current flows.
Therefore, when inputting an analog signal, set the corresponding ADE bit in the ADER to "analog input
enabled."
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 4 I/O PORT
4.8 Port 5
MB90495G Series
Table 4.8-3 Function of Registers for Port 5
Register Name
Data
At Read
0
The pin
state is
Low level.
0 is set for the output latch. When
the pin is an output port pin, the
Low level is output to the pin.
1
The pin
state is
High level.
1 is set for the output latch. When
the pin is an output port pin, the
High level is output to the pin.
0
The
direction
latch is 0.
The output buffer is set to OFF, and
the pin becomes an input port pin.
1
The
direction
latch is 1.
0
General-purpose I/O port
1
Analog input mode
Port 5 data
register (PDR5)
Port 5 direction
register (DDR5)
Analog input
enable register
(ADER)
At Write
Read/
Write
Register
Address
Reset Value
R/W
000005H
XXXXXXXXB
R/W
000015H
00000000B
R/W
00001BH
11111111B
The output buffer is set to ON, and
the pin becomes an output port pin.
R/W: Read/Write
X: Undefined value
References:
CM44-10114-7E
• When using port 5 as the analog input pin, clear the bit in the DDR5 corresponding to the analog input
pin to 0 and set the input pin as an input port.
• When using port 5 as the input pin of the resource, clear the bit in the DDR5 corresponding to the
input pin of the resource to 0 and set the input pin as an input port.
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CHAPTER 4 I/O PORT
4.8 Port 5
4.8.2
MB90495G Series
Operation of Port 5
The operation of port 5 is explained.
■ Operation of Port 5
● Operation of output port
• When the bit in the port 5 direction register (DDR5) corresponding to the output pin is set to 1, port 5
functions as an output port.
• When the output buffer is turned ON and output data is written to the port 5 data register (PDR5), the
data is retained in the output latch and output from the pin.
• When the port 5 data register (PDR5) is read, the state of the output latch in the PDR5 is read.
Note:
If read modify write instructions (such as the bit set instruction) are used to read the PDR, the pin set as
an output port by the DDR outputs the desired data. However, the pin set as an input port outputs data
after the input state is written to the output latch. When switching from the input port to the output port,
write data to the PDR and set the pin as an output port in the DDR
● Operation of input port
• If the bit in the DDR5 corresponding to the input pin is set to 0, port 5 functions as an input port.
• The output buffer is turned OFF and the pin enters the high impedance state.
• When data is written to the port 5 data register (PDR5), it is retained in the output latch in the PDR5 but
not output to the pin.
• When the PDR5 is read, the level value (Low or High) of the pin is read.
● Operation of analog input
• When using port 5 as an analog input pin, set the bit in the ADER corresponding to the analog input pin
to 1. Port 5 is disabled to operate as a general-purpose I/O port, and functions as an analog input pin.
• When the PDR5 is read with the bit set to "analog input enabled," the read value is 0.
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CHAPTER 4 I/O PORT
4.8 Port 5
MB90495G Series
● Reading value of the port data register (PDR)
The value obtained at the time of reading the port 5 data register (PDR5) depends on the state of port 5
direction register (DDR4) and analog input enable register (ADER). Table 4.8-4 shows the values obtained
for each combination.
Table 4.8-4 Reading Value of the Port 5 Data Register (PDR5)
DDR5
ADER
Read Value
0 (input)
1 (Enabled)
Pin state (PORT input)
1 (output)
1 (Enabled)
Pin state (PORT input)
0 (input)
0 (Disabled)
Pin state (PORT input)
1 (output)
0 (Disabled)
Value of output latch (PDR5)
● Operation at reset
• When the CPU is reset, the value of the DDR5 is initialized to 0. Consequently, all output buffers are set
to OFF (the pin becomes an input port pin), and the pin enters the high-impedance state.
• The PDR5 is not initialized by reset. Therefore, when using port 5 as an output port, it is necessary to set
output data in the PDR5, and then set the bit in the DDR5 corresponding to the output pin to 1 and to
output.
● Operation in stop mode, timebase timer mode or watch mode
• When the pin state specification bit of the low power consumption mode control register (LPMCR:SPL)
is 1, at a transition to the stop mode, timebase timer mode or watch mode, the pin enters the highimpedance state. The output buffer is set forcibly to OFF irrespective of the value of the DDR5.
Table 4.8-5shows the state of the port 5 pins.
Table 4.8-5 State of Port 5 Pins
Pine Name
Normal Operation
Sleep Mode
Stop Mode, Timebase Timer Mode or
Watch Mode
SPL=0
P50/AN0 to
P57/AN7
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O
port
SPL=1
Input cut off, and
output becomes Hi-Z
SPL: Pin state specification bit of low power consumption mode control register (LPMCR:SPL)
Hi-Z: High impedance
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CHAPTER 4 I/O PORT
4.9 Port 6
4.9
MB90495G Series
Port 6
Port 6 is a general-purpose I/O port that serves as the resource I/O pin. Use port 6 by
switching between the resource pin and the general-purpose I/O port.
The function as a general-purpose I/O port is mainly described here. The configuration,
pin assignment, block diagram of the pins, and registers for port 6 are shown below.
■ Configuration of Port 6
Port 6 consists of the following three elements:
• General-purpose I/O port, external interrupt input pins (P60/INT0 to P63/INT3)
• Port 6 data register (PDR6)
• Port 6 direction register (DDR6)
■ Pin Assignment of Port 6
• Use port 6 by switching between the resource pin and the general-purpose I/O port.
• Since port 6 serves as a resource pin, it cannot be used as a general-purpose I/O port when used as a
resource pin.
• When using port 6 as the input pin of the resource, set the pin corresponding to the resource in the
DDR6 as an input port
Table 4.9-1 shows the pin assignment for port 6.
Table 4.9-1 Pin Assignment of Port 6
Port
Name
I/O Type
Pin Name
Port Function
Resource
Input
P60/INT0
P60
P61/INT1
P61
Port 6
P62/INT2
P62
P63/INT3
P63
Generalpurpose I/O
port pin
INT0
External
interrupt input 0
INT1
External
interrupt input 1
INT2
External
interrupt input 2
INT3
External
interrupt input 3
CMOS
(hysteresis)
Output
CMOS
Circuit
Type
D
For the circuit type, see Section "1.7 I/O Circuit".
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CHAPTER 4 I/O PORT
4.9 Port 6
MB90495G Series
■ Block Diagram of Pins of Port 6
Figure 4.9-1 Block Diagram of Pins of Port 6
Resource input
PDR (port data register)
Internal data bus
PDR read
Output latch
P ch
PDR write
DDR
Pin
(port direction register)
N ch
Direction latch
DDR write
Standby control (SPL = 1)
DDR read
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and watch mode (SPL = 1)
■ Registers for Port 6
• The registers for port 6 are PDR6 and DDR6.
• The bits composing each register correspond to the pins of port 6 one-to-one.
Table 4.9-2 shows the correspondence between the registers and pins of port 6.
Table 4.9-2 Correspondence between Registers and Pins for Port 6
Port
Name
Bits of Related Registers and Corresponding Pins
PDR6, DDR6
Port 6
Corresponding pin
CM44-10114-7E
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
−
−
−
−
P63
P62
P61
P60
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CHAPTER 4 I/O PORT
4.9 Port 6
4.9.1
MB90495G Series
Registers for Port 6 (PDR6, DDR6)
The registers for port 6 are explained.
■ Function of Registers for Port 6
● Port 6 data register (PDR6)
• Port 6 data register indicates the state of the pins.
● Port 6 direction register (DDR6)
• The port 6 direction register sets the input/output directions of the pins.
• When the bit corresponding to the pin is set to 1, port 6 functions as an output port. When the bit is set
to 0, port 6 functions as an input port.
Table 4.9-3 shows the functions of the registers for port 6.
Table 4.9-3 Function of Registers for Port 6
Register Name
Data
At Read
0
The pin
state is
Low level.
0 is set for the output latch. When
the pin is an output port pin, the
Low level is output to the pin.
1
The pin
state is
High level
1 is set for the output latch. When
the pin is an output port pin, the
High level is output to the pin.
0
The
direction
latch is 0.
The output buffer is set to OFF, and
the pin becomes an input port pin.
1
The
direction
latch is 1.
Port 6 data
register (DDR6)
Port 6 direction
register (DDR6)
At Write
Read/
Write
Register
Address
Reset Value
R/W
000006H
XXXXXXXXB
R/W
000016H
XXXX0000B
The output buffer is set to ON, and
the pin becomes an output port pin
R/W: Read/Write
X: Undefined value
Reference:
228
When using port 6 as the input pin of the resource, clear the bit in the DDR6 corresponding to the input
pin of the resource to 0 and set the input pin as an input port.
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CHAPTER 4 I/O PORT
4.9 Port 6
MB90495G Series
4.9.2
Operation of Port 6
The operation of port 6 is explained.
■ Operation of Port 6
● Operation of output port
• When the bit in the port 6 direction register (DDR6) corresponding to the output pin is set to 1, port 6
functions as an output port.
• When the output buffer is turned ON and output data is written to the port 6 data register (PDR6), the
data is retained in the output latch and output from the pin.
• When the port 6 data register (PDR6) is read, the state of the output latch in the PDR6 is read.
Note:
If read modify write instructions (such as the bit set instruction) are used to read the PDR, the pin set as
an output port by the DDR outputs the desired data. However, the pin set as an input port outputs data
after the input state is written to the output latch. When switching from the input port to the output port,
write data to the PDR and set the pin as an output port in the DDR.
● Operation of input port
• If the bit in the DDR6 corresponding to the input pin is set to 0, port 6 functions as an input port.
• The output buffer is turned OFF and the pin enters the high impedance state.
• When data is written to the PDR6, it is retained in the output latch in the PDR6 but not output to the pin.
• When the PDR6 is read, the level value (0 or 1) of the pin is read.
● Operation of resource input
• The state of the pin that serves as the input of the resource is input to the resource.
• When using port 6 as the input pin of the resource, clear the bit in the DDR6 corresponding to the input
pin of the resource to 0 and set the input pin as an input port.
● Operation at reset
• When the CPU is reset, the value of the DDR6 is initialized to 0. Consequently, all output buffers are set
to OFF (the pin becomes an input port pin), and the pin enters the high-impedance state.
• The PDR6 is not initialized by reset. Therefore, when using port 6 as an output port, it is necessary to set
output data in the PDR6, and then set the bit in the DDR6 corresponding to the output pin to 1 and to
output.
● Operation in stop mode, timebase timer mode or watch mode
• When the pin state specification bit of the low power consumption mode control register (LPMCR:SPL)
is 1, at a transition to the stop mode, timebase timer mode or watch mode, the pin enters the highimpedance state. The output buffer is set forcibly to OFF irrespective of the value of the DDR6.
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CHAPTER 4 I/O PORT
4.9 Port 6
MB90495G Series
Table 4.9-4 shows the state of the port 6 pins.
Table 4.9-4 State of the Port 6 Pins
Pin Name
Normal Operation
Sleep Mode
Stop Mode, Timebase Timer Mode or
Watch Mode
SPL=0
P60/INT0 to
P63/INT3
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O
port
SPL=1
Input cut off, and
output becomes Hi-Z
SPL: Pin state specification bit of low power consumption mode control register (LPMCR:SPL)
Hi-Z: High impedance
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CM44-10114-7E
CHAPTER 5
TIMEBASE TIMER
This chapter describes the function and operation of the
timebase timer.
5.1 Overview of Timebase Timer
5.2 Block Diagram of Timebase Timer
5.3 Configuration of Timebase Timer
5.4 Timebase Timer Interrupt
5.5 Explanation of Operation of Timebase Timer
5.6 Precautions when Using Timebase Timer
5.7 Program Example of Timebase Timer
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CHAPTER 5 TIMEBASE TIMER
5.1 Overview of Timebase Timer
5.1
MB90495G Series
Overview of Timebase Timer
The timebase timer is an 18-bit free-run counter (timebase timer counter) that
increments in synchronization with the main clock (2-divided frequency of main
oscillation clock).
• Four interval times can be selected and an interrupt request can be generated for
each interval time.
• An operation clock is supplied to the oscillation stabilization wait time timer and
other resources.
■ Functions of Interval Timer
• When the timebase timer counter reaches the interval time set by the interval time select bits
(TBTC:TBC1, TBC0), an overflow occurs (TBTC:TBOF = 1) and an interrupt request is generated.
• When an interrupt is enabled when an overflow occurs (TBTC:TBIE = 1), an overflow occurs
(TBTC:TBOF = 1) and an interrupt is generated.
• The timebase timer has four interval times that can be selected. Table 5.1-1 shows the interval times of
the timebase timer.
Table 5.1-1 Interval Times of Timebase Timer
Count Clock
Interval Time
212/HCLK (approx. 1.0 ms)
2/HCLK(0.5 μs)
214/HCLK (approx. 4.1 ms)
216/HCLK (approx. 16.4 ms)
219/HCLK (approx. 131.1 ms)
HCLK: Oscillation clock
The parenthesized values are provided at 4-MHz oscillation clock.
■ Clock Supply
• The timebase timer supplies an operation clock to the resources such as an oscillation stabilization wait
time timer, PPG timer, and watchdog timer. Table 5.1-2 shows the clock cycles supplied from the
timebase timer.
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CHAPTER 5 TIMEBASE TIMER
5.1 Overview of Timebase Timer
MB90495G Series
Table 5.1-2 Clock Cycles Supplied from Timebase Timer
Where to Supply Clock
Oscillation stabilization wait time timer
Clock Cycle
210/HCLK (approx. 256 μs)
213/HCLK (approx. 2.0 ms)
215/HCLK (approx. 8.2 ms)
217/HCLK (approx. 32.8 ms)
212/HCLK (approx. 1.0 ms)
214/HCLK (approx. 4.1 ms)
Watchdog timer
216/HCLK (approx. 16.4 ms)
219/HCLK (approx. 131.1 ms)
PPG Timer
29/HCLK (approx. 128 μs)
HCLK: Oscillation clock
The parenthesized values are provided at 4-MHz oscillation clock.
Note:
Since the oscillation cycle is unstable immediately after oscillation starts, the oscillation
stabilization wait time values are given as a guide.
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CHAPTER 5 TIMEBASE TIMER
5.2 Block Diagram of Timebase Timer
5.2
MB90495G Series
Block Diagram of Timebase Timer
The timebase timer consists of the following blocks:
• Timebase timer counter
• Counter clear circuit
• Interval timer selector
• Timebase timer control register (TBTC)
■ Block Diagram of Timebase Timer
Figure 5.2-1 Block Diagram of Timebase Timer
To watchdog
timer
To PPG timer
Timebase timer counter
× 21 × 22 × 23
21/HCLK
. . .. . .
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
OF
OF
OF
OF
Power-on reset
Stop mode
CKSCR: MCS = 1 → 0*1
CKSCR: SCS = 0 → 1*2
To the oscillation
stabilization wait time
selector in the clock
control section
Counter
clesr circuit
Interval timer
selector
TBOF clear
Timebase timer control register
(TBTC)
Reserved
⎯
TBOF set
⎯
TBIE TBOF TBR TBC1 TBC0
Timebase timer interrupt signal
OF
HCLK
*1
*2
:
:
:
:
Overflow
Oscillation clock
Switching the machine clock from the main clock to the PLL clock
Switching the machine clock from the subclock to the main clock
The actual interrupt request number of the timebase timer is as follows:
Interrupt request number: #16 (10H)
● Timebase timer counter
The timebase timer counter is an 18-bit up counter that uses a clock with 2-divided frequency of the
oscillation clock (HCLK) as a count clock.
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CHAPTER 5 TIMEBASE TIMER
5.2 Block Diagram of Timebase Timer
MB90495G Series
● Counter clear circuit
The counter clear circuit clears the value of the timebase timer counter by the following factors:
• Timebase timer counter clear bit in the timebase timer control register (TBTC:TBR = 0)
• Power-on reset
• Transition to main stop mode or PLL stop mode (CKSCR:SCS = 1, LPMCR:STP = 1)
• Clock mode switching (from main clock mode to PLL clock mode, from subclock mode to PLL clock
mode, or from subclock mode to main clock mode)
● Interval timer selector
The time interval selector selects the output of the timebase timer counter from four types. When
incrementing causes the selected interval time bit to overflow, an interrupt request is generated.
● Timebase timer control register (TBTC)
The timebase timer control register (TBTC) selects the interval time, clears the timebase timer counter,
enables or disables interrupts, and checks and clears the state of an interrupt request.
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CHAPTER 5 TIMEBASE TIMER
5.3 Configuration of Timebase Timer
5.3
MB90495G Series
Configuration of Timebase Timer
This section explains the registers and interrupt factors of the timebase timer.
■ List of Registers and Reset Values of Timebase Timer
Figure 5.3-1 List of Registers and Reset Values of Timebase Timer
bit
Timebase timer control register (TBTC)
15
14
13
12
11
10
9
8
1
×
×
0
0
1
0
0
×: Undefined
■ Generation of Interrupt Request from Timebase Timer
When the selected timebase timer counter bit reaches the interval time, the overflow interrupt request flag
bit in the timebase timer control register (TBTC:TBOF) is set to 1. If the overflow interrupt request flag bit
is set (TBTC:TBOF = 1) when the interrupt is enabled (TBTC:TBIE = 1), the timebase timer generates an
interrupt request.
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CHAPTER 5 TIMEBASE TIMER
5.3 Configuration of Timebase Timer
MB90495G Series
5.3.1
Timebase Timer Control Register (TBTC)
The timebase timer control register (TBTC) provides the following settings:
• Selecting the interval time of the timebase timer
• Clearing the count value of the timebase timer
• Enabling or disabling the interrupt request when an overflow occurs
• Checking and clearing the state of the interrupt request flag when an overflow occurs
■ Timebase Timer Control Register (TBTC)
Figure 5.3-2 Timebase Timer Control Register (TBTC)
15
14
13
12
11
10
9
8
Reset value
1XX00100B
R/W ⎯
⎯ R/W R/W W R/W R/W
bit 9 bit 8
TBC1 TBC0
Interval time select bits
0
0
212/HCLK (Approx. 1.0ms)
0
1
214/HCLK (Approx. 4.1ms)
1
0
216/HCLK (Approx. 16.4ms)
1
1
219/HCLK (Approx. 131.1ms)
HCLK: Oscillation clock
The parenthesized values are provided at 4 MHz oscillation clock.
bit 10
Timebase timer counter clear bit
Read
Write
TBR
0
⎯
1
The read value is always 1
Clears the timebase timer
counter and TBOF bit
No effect
bit 11
TBOF
Overflow interrupt request flag bit
Read
Write
0
No overflow from the
selected count bit
Cleared
1
Overflow from the
selected count bit
No effect
bit 12
TBIE
0
1
Overflow interrupt enable bit
Overflow interrupt request disabled
Overflow interrupt request enabled
bit 15
Reserved
R/W : Read/Write
W
: Write only
X
: Undefined
: Reset value
⎯
: Unused
CM44-10114-7E
1
Reserved bit
Always write 1 to this bit
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CHAPTER 5 TIMEBASE TIMER
5.3 Configuration of Timebase Timer
MB90495G Series
Table 5.3-1 Functions of Timebase Timer Control Register (TBTC)
Bit Name
238
Function
bit 8
bit 9
TBC1, TBC0:
Interval time select bits
These bits set the cycle of the interval timer in the timebase timer counter.
• The interval time of the timebase timer is set according to the setting of the
TBC1 and TBC0 bits.
• Four interval times can be set.
bit 10
TBR:
Timebase timer counter
clear bit
This bit clears all the bits in the timebase timer counter.
When set to 0: All the bits in the timebase timer counter are cleared to 0. The
TBOF bit is also cleared.
When set to 1: Disabled. The state remains unchanged.
Read: 1 is always read.
bit 11
TBOF:
Overflow interrupt
request flag bit
This bit indicates an overflow (carrying) in the time interval bit in the timebase
timer counter.
When an overflow (carrying) occurs with interrupts enabled (TBIE = 1), an
interrupt request is generated.
When set to 0: The bit is cleared.
When set to 1: Disabled. The state remains unchanged.
Reading by read-modify-write type instructions always returns "1".
Notes:
1. To clear the TBOF bit, disable interrupts (TBIE = 0) or mask interrupts using
the interrupt mask register (ILM) in the processor status.
2. The TBOF bit is cleared when 0 is written to the bit, a transition to main stop
mode, a transition to PLL stop mode, a transition from subclock mode to
main clock mode, a transition from subclock mode to PLL clock mode, or a
transition from main clock mode to PLL clock mode occurs, 0 is written to
the timebase timer counter clear bit (TBR), or by a reset.
bit 12
TBIE:
Overflow interrupt
enable bit
This bit enables or disables an interrupt when the interval time bit in the timebase
timer counter overflows.
When set to 0: No interrupt request is generated at an overflow (TBOF = 1).
When set to 1: An interrupt request is generated at an overflow (TBOF = 1).
bit 13
bit 14
Unused bits
Read: The value is undefined.
Write: No effect
bit 15
Reserved bit
Always set this bit to 1.
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CM44-10114-7E
CHAPTER 5 TIMEBASE TIMER
5.4 Timebase Timer Interrupt
MB90495G Series
5.4
Timebase Timer Interrupt
The timebase timer generates an interrupt request when the interval time bit in the
timebase timer counter corresponding to the interval time set by the timebase timer
control register overflows (carries) (interval timer function).
■ Timebase Timer Interrupt
• The timebase timer continues incrementing for as long as the main clock (with 2-divided frequency of
the oscillation clock) is input.
• When the interval time set by the interval time select bits in the timebase timer control register
(TBTC:TBC1, TBC2) is reached, the interval time select bit corresponding to the interval time selected
in the timebase timer counter overflows.
• When the interval time select bit overflows, the overflow interrupt request flag bit in the timebase timer
control register (TBTC:TBOF) is set to 1.
• When the overflow interrupt request flag bit in the timebase timer control register is set (TBTC:TBOF =
1) with an interrupt enabled (TBTC:TBIE = 1), an interrupt request is generated.
• When the selected interval time is reached, the overflow interrupt request flag bit in the timebase timer
control register (TBTC:TBOF) is set regardless of whether an interrupt is enabled or disabled
(TBTC:TBIE)
• To clear the overflow interrupt request flag bit (TBTC:TBOF), disable a timebase timer interrupt at
interrupt processing or mask a timebase timer interrupt by using the ILM bit in the processor status (PS)
to write 0 to the TBOF bit.
Note:
When an interrupt is enabled (TBTC:TBIE = 1) with the overflow interrupt request flag bit in the
timebase timer control register set (TBTC:TBOF = 1), an interrupt request is generated immediately.
■ Correspondence between Timebase Timer Interrupt and EI2OS
• The timebase timer does not correspond to EI2OS.
• For details of the interrupt number, interrupt control register, and interrupt vector address, see "3.5
Interrupt".
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CHAPTER 5 TIMEBASE TIMER
5.5 Explanation of Operation of Timebase Timer
5.5
MB90495G Series
Explanation of Operation of Timebase Timer
The timebase timer operates as an interval timer or an oscillation stabilization wait time
timer, and supplies a clock to resources.
■ Interval Timer Function
Interrupt generation at every interval time enables the timebase timer to be used as an interval timer.
Operating the timebase timer as an interval timer requires the settings shown in Figure 5.5-1.
● Setting of timebase timer
Figure 5.5-1 Setting of Timebase Timer
bit 15 14
Timebase timer control register
(TBTC)
- :
:
0 :
1 :
Reserved
⎯
1
Unused bit
Used bit
Set 0
Set 1
13
12
11
10
9 bit 8
⎯ TBIE TBOF TBR TBC1TBC0
0
0
● Operation as interval timer function
The timebase timer can be used as an interval timer by generating an interrupt at every set interval time.
• The timebase timer continues incrementing in synchronization with the main clock (2-divided frequency
of the oscillation clock) while the oscillation clock is active.
• When the timebase timer counter reaches the interval time set by the interval time select bits in the
timebase timer control register (TBTC:TBC1, TBC0), it causes an overflow (carrying) and the overflow
interrupt request flag bit (TBTC:TBOF) is set to 1.
• When the overflow interrupt request flag bit is set (TBTC:TBOF = 1) with interrupts enabled
(TBTC:TBIE = 1), an interrupt request is generated.
Note:
The interval time may become longer than the one set by clearing the timebase timer counter.
● Example of operation of timebase timer
Figure 5.5-2 gives an example of the operation that the timebase timer performs under the following
conditions:
• A power-on reset occurs.
• The mode transits to the sleep mode during the operation of the interval timer.
• The mode transits to the stop mode during the operation of the interval timer.
• A request to clear the timebase timer counter is issued.
At transition to the stop mode, the timebase timer counter is cleared to stop counting. At return from the
stop mode, the timebase timer counts the oscillation stabilization wait time of the main clock.
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CHAPTER 5 TIMEBASE TIMER
5.5 Explanation of Operation of Timebase Timer
MB90495G Series
Figure 5.5-2 Example of Operation of Timebase Timer
Counter value
Cleared by transition
to stop mode
3FFFFH
Oscillation stabilization
wait overflow
00000 H
CPU operation starts
Power-on reset
Interval cycle
(TBTC: TBC1: TBC0 = 11B)
Cleared by interrupt processing
Counter clear
(TBTC: TBR = 0)
TBOF bit
TBIE bit
Sleep
SLP bit
(LPMCR register)
Releasing of sleep mode by interval
interrupt of timebase timer
Stop
STP bit
(LPMCR register)
When interval time selec bit (TBTC: TBC1, TBC0) is set to "11B" (219/HCLK)
: Oscillation stabilization wait time
HCLK : Oscillation clock
■ Operation as Oscillation Stabilization Wait Time Timer
The timebase timer can be used as the oscillation stabilization wait time timer of the main clock and PLL
clock.
• The oscillation stabilization wait time is the time elapsed from when the timebase timer counter
increments from 0 until the set oscillation stabilization wait time select bit overflows (carrying).
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CHAPTER 5 TIMEBASE TIMER
5.5 Explanation of Operation of Timebase Timer
MB90495G Series
Table 5.5-1 Clearing Conditions and Oscillation Stabilization Wait Time of Timebase Timer
Operation
Counter
Clear
TBOF
Clear
Writing 0 to timebase timer counter clear bit
(TBTC:T BR)
O
O
O
O
Transition to main clock mode after oscillation stabilization
wait time of main clock completed
Watchdog reset
X
O
Not provided
External reset
X
O
Not provided
Software reset
X
O
Not provided
Main clock --> PLL clock
(CKSCR:MCS = 1 --> 0)
O
O
Transition to PLL clock mode after oscillation stabilization wait
time of PLL clock completed
Main clock --> subclock
(CKSCR:SCS = 1 --> 0)
X
X
Transition to subclock mode after oscillation stabilization wait
time of subclock completed
Subclock --> main clock
(CKSCR:SCS = 0 --> 1)
O
O
Transition to main clock mode after oscillation stabilization
wait time of main clock completed
Subclock --> PLL clock
(CKSCR:MCS = 0, SCS = 0 --> 1)
O
O
Transition to PLL clock mode after oscillation stabilization wait
time of main clock completed
PLL clock --> main clock
(CKSCR:MCS = 0 --> 1)
X
X
PLL clock --> subclock
(CKSCR:MCS = 0, SCS = 1 --> 0)
X
X
O
O
Switch to main clock mode after oscillation stabilization wait
time of main clock completed
X
X
Switch to subclock mode after oscillation stabilization wait time
of subclock completed
O
O
Switch to PLL clock mode after oscillation stabilization wait
time of main clock completed
X
X
Not provided
Return to main clock mode
X
X
Not provided
Return to subclock mode
X
X
Not provided
Return to PLL clock mode
X
X
Not provided
Cancellation of main sleep mode
X
X
Not provided
Cancellation of sub-sleep mode
X
X
Not provided
Cancellation of PLL sleep mode
X
X
Not provided
Oscillation Stabilization Wait Time
Reset
Power on reset
Switching between clock modes
Not provided
Not provided
Cancellation of stop modes
Cancellation of main stop mode
Cancellation of sub-stop mode
Cancellation of PLL stop mode
Cancellation of timer mode
Cancellation of sub-timer mode
Cancellation of timebase timer modes
Cancellation of sleep modes
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CHAPTER 5 TIMEBASE TIMER
5.5 Explanation of Operation of Timebase Timer
MB90495G Series
■ Supply of Operation Clock
The timebase timer supplies an operation clock to the PPG timers (PPG01, PPG23) and the watchdog
timer.
Note:
Clearing the timebase timer counter may affect the operation of the resources such as the watchdog timer
and PPG timers using the output of the timebase timer.
For details of the PPG timers, see "CHAPTER 10 8-/16-BIT PPG TIMER".
For details of the watchdog timer, see "CHAPTER 6 WATCHDOG TIMER".
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CHAPTER 5 TIMEBASE TIMER
5.6 Precautions when Using Timebase Timer
5.6
MB90495G Series
Precautions when Using Timebase Timer
This section explains the precautions when using the timebase timer.
■ Precautions when Using Timebase Timer
● Clearing interrupt request
To clear the overflow interrupt request flag bit in the timebase timer control register (TBTC:TBOF = 0),
disable interrupts (TBTC:TBIE = 0) or mask the timebase timer interrupt by using the interrupt level mask
register in the processor status.
● Clearing timebase timer counter
Clearing the timebase timer counter affects the following operations:
• When the timebase timer is used as the interval timer (interval interrupt).
• When the watchdog timer is used.
• When the clock supplied from the timebase timer is used as the operation clock of the PPG timer.
● Using timebase timer as oscillation stabilization wait time timer
• After power on or in the main stop mode, PLL stop mode, and subclock mode, the oscillation clock
stops. Therefore, when oscillation starts, the timebase timer requires the oscillation stabilization wait
time of the main clock. An appropriate oscillation stabilization wait time must be selected according to
the types of oscillators connected to high-speed oscillation input pins.
For details of the oscillation stabilization wait time, see "3.7.5 Oscillation Stabilization Wait Time".
● Resources to which timebase timer supplies clock
• At transition to operation modes (PLL stop mode, subclock mode, and main stop mode) in which the
oscillation clock stops, the timebase timer counter is cleared and the timebase timer stops.
• When the timebase timer counter is cleared, an after-clearing interval time is needed. It may cause the
clock supplied from the timebase timer to have a short High level or a 1/2 cycle longer Low level.
• The watchdog timer performs normal counting because the watchdog timer counter and timebase timer
counter are cleared simultaneously.
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CHAPTER 5 TIMEBASE TIMER
5.7 Program Example of Timebase Timer
MB90495G Series
5.7
Program Example of Timebase Timer
This section gives a program example of the timebase timer.
■ Program Example of Timebase Timer
● Processing specification
The 212/HCLK (HCLK: oscillation clock) interval interrupt is generated repeatedly. In this case, the
interval time is approximately 1.0 ms (at 4-MHz operation).
● Coding example
ICR02
EQU 0000B2H
; Timebase timer interrupt control register
TBTC
EQU 0000A9H
; Timebase timer control register
TBOF
EQU TBTC:3
; Interrupt request flag bit
TBIE
EQU TBTC:2
; Interrupt enable bit
;-----Main program--------------------------------------------------------------CODE CSEG
START:
; Stack pointer (SP) already initialized
AND CCR,#0BFH
; Interrupts disabled
MOV I:ICR02 #00H
; Interrupt level 0 (highest)
MOV I:TBTC,#10000000B ; Upper 3 bits fixed
; TBOF cleared,
; Counter cleare interval time
; 212/HCLK selected
SETB I:TBIE
; Interrup enabled
MOV ILM,#07H
; ILM in PS set to level 7
OR
CCR,#40H
; Interrupts enabled
LOOP:
MOV A,#00H
; Infinite loop
MOV A,#01H
BRA LOOP
;-----Interrupt program---------------------------------------------------------WARI:
CLRB I:TBIE
; Interrupt enabled bit cleared
CLRB I:TBOF
; Interrupt request flag cleared
:
Processing by user
:
SETB I:TBIE
; Interrupt enabled
RETI
; Return from interrupt
CODE ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG 0FFBCH
; Vector set to interrupt #16 (10H)
DSL WARI
ORG 0FFDCH
; Reset vector set
DSL START
DB
00H
; Set to single-chip mode
VECT ENDS
END START
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CHAPTER 5 TIMEBASE TIMER
5.7 Program Example of Timebase Timer
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CHAPTER 6
WATCHDOG TIMER
This chapter describes the function and operation of the
watchdog timer.
6.1 Overview of Watchdog Timer
6.2 Configuration of Watchdog Timer
6.3 Watchdog Timer Registers
6.4 Explanation of Operation of Watchdog Timer
6.5 Precautions when Using Watchdog Timer
6.6 Program Examples of Watchdog Timer
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CHAPTER 6 WATCHDOG TIMER
6.1 Overview of Watchdog Timer
6.1
MB90495G Series
Overview of Watchdog Timer
The watchdog timer is a 2-bit counter that uses the timebase timer or watch timer as a
count clock. If the counter is not cleared within a set interval time, the CPU is reset.
■ Functions of Watchdog Timer
• The watchdog timer is a timer counter that is used to prevent program malfunction. When the watchdog
timer is started, the watchdog timer counter must continue to be cleared within a set interval time. If the
set time interval is reached without clearing the watchdog timer counter, the CPU is reset.
• The interval time of the watchdog timer depends on the clock cycle input as a count clock and a
watchdog reset occurs between the minimum and maximum times.
• The clock source output destination is set by the watchdog clock select bit in the watch timer control
register (WTC:WDCS).
• The interval time of the watchdog timer is set by the timebase timer output select bit/watch timer output
select bit in the watchdog timer control register (WDTC:WT1, WT0).
Table 6.1-1 lists the interval times of the watchdog timer.
Table 6.1-1 Interval Time of Watchdog Timer
Min.
Max.
Clock cycle
Min.
Max.
Clock cycle
Approx. 3.58 ms
Approx.4.61 ms
214 + 211/HCLK
Approx. 0.457 s
Approx. 0.576 s
212 + 29/SCLK
Approx. 14.33 ms
Approx. 18.3 ms
216 + 213/HCLK
Approx. 3.584 s
Approx. 4.608 s
215 + 212/SCLK
Approx. 57.23 ms
Approx. 73.73 ms
218 + 215/HCLK
Approx. 7.168 s
Approx. 9.216 s
216 + 213/SCLK
Approx. 458.75 ms
Approx. 589.82 ms
221 + 218/HCLK
Approx. 14.336 s
Approx. 18.432 s
217 + 214/SCLK
HCLK: Oscillation clock (4 MHz), SLCK: Subclock (8.192 kHz)
Notes:
248
• If the timebase timer output (carry signal) is used as a count clock to the watchdog timer, the timebase
timer is cleared and the time for the watchdog reset to occur may be long.
• If the subclock is used as a machine cock, always set the watchdog timer clock source select bit
(WDCS) in the watch timer control register (WTC) to 0 to select the watch timer output. If the mode
transits to the sub-clock mode with the WDCS bit setting to "1", the watchdog timer stops.
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CHAPTER 6 WATCHDOG TIMER
6.2 Configuration of Watchdog Timer
MB90495G Series
6.2
Configuration of Watchdog Timer
The watchdog timer consists of the following blocks:
• Count clock selector
• Watchdog timer counter (2-bit counter)
• Watchdog reset generator
• Counter clear controller
• Watchdog timer control register (WDTC)
■ Block Diagram of Watchdog Timer
Figure 6.2-1 Block Diagram of Watchdog Time
Watchdog timer control register (WDTC)
PONR
⎯
Watch timer control register (WTC)
WRST ERST SRST WTE WT1 WT0
Watchdog timer
WDCS
2
Started
Reset generated
Transits to sleep mode
Transits to
timebase timer mode
Transits to timer mode
Transits to stop mode
Counter claer
controller
Count clock
selector
2-bit
counter
Watchdog
reset
generator
To the internal
reset generator
Clear
4
4
(Timebase timer counter)
Main clock
(2-devided clock of HCLK)
× 21 × 22 . . . × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
(Watch counter)
Subclock
SCLK
× 21 × 22 . . . × 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215
HCLK: Oscillation clock
SCLK: Subclock
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CHAPTER 6 WATCHDOG TIMER
6.2 Configuration of Watchdog Timer
MB90495G Series
● Count clock selector
The count clock selector selects the timebase timer output or watch timer output as a count clock input to
the watchdog timer. Each timer output has four time intervals that can be set.
● Watchdog timer counter (2-bit counter)
The watchdog timer counter is a 2-bit counter that uses the timebase timer output or watch timer output as a
count clock. The clock source output destination is set by the watchdog clock select bit in the watch timer
control register (WTC:WDCS).
● Watchdog reset generator
The watchdog reset generation circuit generates a reset signal when the watchdog timer overflows.
● Counter clear controller
The counter clear controller clears the watchdog timer counter.
● Watchdog timer control register (WDTC)
The watchdog timer control register starts and clears the watchdog timer, sets the interval time, and holds
reset factors.
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CHAPTER 6 WATCHDOG TIMER
6.3 Watchdog Timer Registers
MB90495G Series
6.3
Watchdog Timer Registers
This section explains the registers used for setting the watchdog timer.
■ List of Registers and Reset Values of Watchdog Timer
Figure 6.3-1 List of Registers and Reset Values of Watchdog Time
bit
Watchdog timer control register
(WDTC)
7
6
5
4
3
2
1
0
×
×
×
×
×
1
1
1
×: Undefined
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CHAPTER 6 WATCHDOG TIMER
6.3 Watchdog Timer Registers
MB90495G Series
Watchdog Timer Control Register (WDTC)
6.3.1
The watchdog timer control register starts and clears the watchdog timer, sets the
interval time, and holds reset factors.
■ Watchdog Timer Control Register (WDTC)
Figure 6.3-2 Watchdog Timer Control Register (WDTC)
7
6
5
4
3
2
1
0
R
⎯
R
R
R
W
W
W
Reset value
XXXXX111 B
bit 1
bit 0
Interval time select bits (Timebase timer output selection)
Interval time
Clock cycle
Minimum
Maximum
0
0 Approx. 3.58 ms Approx. 4.61 ms
214 ± 211/HCLK
0
1 Approx. 14.33 ms Approx. 18.3 ms
216 ± 213/HCLK
1
0 Approx. 57.23 ms Approx. 73.73 ms 218 ± 215/HCLK
1
1 Approx. 458.75 ms Approx. 589.82 ms 221 ± 218/HCLK
HCLK: Oscillation clock
WT1 WT0
bit 1
bit 0
Interval time select bits (Watch timer output selection)
Interval time
WT1 WT0
Minimum
0
0 Approx. 0.457 s
0
1 Approx. 3.584 s
1
0 Approx. 7.168 s
1
1 Approx. 14.336 s
SCLK: Subclock
Maximum
Approx. 0.576 s
Approx. 4.608 s
Approx. 9.216 s
Approx. 18.432 s
Clock cycle
2 ± 2 /SCLK
215 ± 212/SCLK
12
9
216 ± 213/SCLK
217 ± 214/SCLK
bit 2
Watchdog timer control bit
WTE
First write after reset: starts the
Second or subsequent write after
0
watchdog timer
reset: clears of the watchdog timer
1
No effect
bit 7 bit 5 bit 4 bit 3
Reset factor bits
Reset factor
PONR WRST ERST SRST
R
W
*
×
252
:
:
:
:
Read only
Write only
Holds the previous status
Undefined
1
×
×
×
*
*
*
1
*
*
*
1
*
*
Power-on reset
Watchdog reset
External reset ("L" level input into RST pin)
*
1
Software reset (Write "1" to RST bit)
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CHAPTER 6 WATCHDOG TIMER
6.3 Watchdog Timer Registers
MB90495G Series
Table 6.3-1 Function of Watching Timer Control Register (WDTC)
Bit name
Function
bit 0,
bit 1
WT1, WT0:
Time interval select bits
These bits set the interval time of the watchdog timer.
The time interval when the watch timer is used as the clock source to the
watchdog timer (watchdog clock select bit WDCS = 0) is different from when
the main clock mode or the PLL clock mode is selected as the clock mode and
the WDCS bit in the watch timer control register (WTC) is set to 1 as shown in
Figure 6.3-2 according to the settings of the WTC register.
• Only data when the watchdog timer is started is enabled.
• Write data after the watchdog timer is started is ignored.
• These are write-only bits.
bit 2
WTE:
Watchdog timer control
bit
This bit starts or clears the watchdog timer.
When set to 0 (first time after reset): The watchdog timer is started.
When set to 0 (second or subsequent): The watchdog timer is cleared.
bit6
Unused bits
Read: The value is undefined.
Write: No effect
PONR, WRST, ERST,
SRST:
Reset factor bits
These bits indicate reset factors.
• When a reset occurs, the bit corresponding to the reset factor is set to 1. After
a reset, the reset factor can be checked by reading the watchdog timer control
register (WDTC).
• These bits are cleared after the watchdog timer control register (WDTC) is
read.
Note:
No bit value other than the PONR bit after power-on reset is assured. If the
PONR bit is set at read, other bit values should be ignored.
bit 3 to
bit 7
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CHAPTER 6 WATCHDOG TIMER
6.4 Explanation of Operation of Watchdog Timer
6.4
MB90495G Series
Explanation of Operation of Watchdog Timer
After starting, when the watchdog timer reaches the set interval time without the
counter being cleared, a watchdog reset occurs.
■ Operation of Watchdog Timer
The operation of the watchdog timer requires the settings shown in Figure 6.4-1.
Figure 6.4-1 Setting of Watchdog Time
bit 7
6
5
4
3
2
1
bit 0
Watchdog timer control register PONR ⎯ WRST ERST SRST WTE WT1 WT0
(WDTC)
0
bit 7
Watch timer control register
(WTC)
6
5
4
3
2
1
bit 0
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
: Used bit
0 : Set "0"
● Selecting clock input source
• The timebase timer or watch timer can be selected as the clock input source to the watchdog timer.
When the watchdog clock select bit (WTC:WDCS) is set to 1, the timebase timer is selected. When the
bit is set to 0, the watch timer is selected. After a reset, the bit returns to 1.
• During operation in the subclock mode, set the WDCS bit to 0 to select the watch timer. If the mode
transits to the subclock mode with the WDCS bit setting to "1", the watchdog timer stops.
● Setting interval time
• Set the interval time select bits (WDTS:WT1, WT0) to select the interval time for the watchdog timer.
• Set the interval time concurrently with starting the watchdog timer. Writing to the bit is ignored after the
watchdog timer is started.
● Starting watchdog timer
• When 0 is written to the watchdog timer control bit (WDTC:WTE) after a reset, the watchdog timer is
started and starts incrementing.
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6.4 Explanation of Operation of Watchdog Timer
MB90495G Series
● Clearing watchdog timer
• When 0 is written once again to the watchdog timer control bit (WDTC:WTE) within the interval time
after starting the watchdog timer, the watchdog timer is cleared. If the watchdog timer is not cleared
within the interval time, it overflows and the CPU is reset.
• A reset, or transitions to the standby modes (sleep mode, stop mode, watch mode, timebase timer mode)
clear the watchdog timer.
• During operation in the timebase timer mode or watch mode, the watchdog timer counter is cleared.
However, the watchdog timer remains in the activation state.
• Figure 6.4-2 shows the relationship between the clear timing and the interval time of the watchdog
timer. The interval time varies with the timing of clearing the watchdog timer.
● Checking reset factors
• The reset factor bits in the watchdog timer control register (WDTC:PONR, WRST, ERST, SRST) can
be read after a reset to check the reset factors.
For details of reset factor bits, see "3.6 Reset".
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CHAPTER 6 WATCHDOG TIMER
6.4 Explanation of Operation of Watchdog Timer
MB90495G Series
Figure 6.4-2 Relationship between Clear Timing and Interval Time of Watchdog Timer
[Watchdog timer block diagram]
2-bit counter
Clock
selector
a
2-devided b
clock circuit
Count enable
output circuit
WTE bit
2-devided
clock circuit
c
Reset circuit
d
Reset
signal
Count enabled and cleared
[Minimum interval time] When the WTE bit is cleared immediately before the count clock rises
Count starts
Counter cleared
Count clock a
2-devided clock value b
2-devided clock value c
Count enable
Reset signal d
7 × (count clock cycle/2)
WTE bit cleared
Watchdog reset occurs
[Maximum interval time] When the WTE bit is cleared immediately after the count clock rises
Count starts
Counter cleared
Count clock a
2-devided clock value b
2-devided clock value c
Count enable
Reset signal d
9 × (count clock cycle/2)
WTE bit cleared
256
Watchdog reset occurs
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CHAPTER 6 WATCHDOG TIMER
6.5 Precautions when Using Watchdog Timer
MB90495G Series
6.5
Precautions when Using Watchdog Timer
Take the following precautions when using the watchdog timer.
■ Precautions when Using Watchdog Timer
● Stopping watchdog timer
• The watchdog timer is stopped by all the reset sources.
● Interval time
• The interval time uses the carry signal of the time-base timer or watch timer as a count clock. If the
time-base timer or watch timer is cleared, the interval time of the watchdog timer may become long.
The time-base timer is also cleared by writing zero to the timebase timer counter clear bit (TBR) in the
time-base timer control register (TBTC); transition from main clock mode to PLL clock mode;
transition from subclock mode to main clock mode; and transition from subclock mode to PLL clock
mode.
• Set the interval time concurrently with starting the watchdog timer. Setting the time interval except
starting the watchdog timer is ignored.
● Precautions when creating program
• When clearing the watchdog timer repeatedly in the main loop, set a shorter processing time for the
main loop including interrupt processing than the interval time of watchdog timer.
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CHAPTER 6 WATCHDOG TIMER
6.6 Program Examples of Watchdog Timer
6.6
MB90495G Series
Program Examples of Watchdog Timer
Program example of watchdog timer is given below:
■ Program Example of Watchdog Timer
● Processing specification
• The watchdog timer is cleared each time in loop of the main program.
• The main program must be executed once within the minimum interval time of the watchdog timer.
● Coding example
WDTC
EQU 0000A8H
; Watchdog timer control register
WTE
EQU WDTC:2
; Watchdog control bit
;
;-----Main program--------------------------------------------------------------CODE
CSEG
START:
; Stack pointer (SP), already initialized
MOV I:WDTC,#00000011B ; Watchdog timer started
; Interval time of 221 + 218cycles selected
LOOP:
CLRB I:WTE
; Watchdog timer cleared
:
Processing by user
:
BRA LOOP
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG 00FFDCH
; Reset vector set
DSL START
DB
00H
; Set to single-chip mode
VECT
ENDS
END START
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CHAPTER 7
16-BIT INPUT/OUTPUT
TIMER
This chapter explains the function and operation of 16bit input/output timer.
7.1 Overview of 16-bit Input/Output Timer
7.2 Block Diagram of 16-bit Input/Output Timer
7.3 Configuration of 16-bit Input/Output Timer
7.4 Interrupts of 16-bit Input/Output Timer
7.5 Explanation of Operation of 16-bit Free-run Timer
7.6 Explanation of Operation of Input Capture
7.7 Precautions when Using 16-bit Input/Output Timer
7.8 Program Example of 16-bit Input/Output Timer
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CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.1 Overview of 16-bit Input/Output Timer
7.1
MB90495G Series
Overview of 16-bit Input/Output Timer
The 16-bit input/output timer is a complex module that consists of a 16-bit free-run timer
(x 1 unit) and an input capture (x 2 units/4 input pins). The clock cycle of an input signal
and a pulse width can be measured based on the 16-bit input/output timer.
■ Configuration of 16-bit Input/Output Timer
The 16-bit input/output timer consists of the following modules:
• 16-bit free-run timer (× 1 unit)
• Input capture (× 2 units with 2 input pins each)
■ Functions of 16-bit Input/Output Timer
● Functions of 16-bit free-run timer
The 16-bit free-run timer consists of a 16-bit up counter, a timer counter control status register, and a
prescaler. The 16-bit up counter increments in synchronization with the division ratio of the machine clock.
• Count clock is selected from eight machine clock division ratios(φ,φ/2,φ/4,φ/8,φ/16,φ/32,φ/64,φ/128).
The external clock signal input to the 16-bit free-run timer clock input pin (FRCK) can also be used as a
count clock.
• An overflow in the count value generates an interrupt.
• Interrupt generation starts the extended intelligent I/O service (EI2OS).
• Either a reset or software reset by the timer count clear bit (TCCS:CLR) clears the count value of the
16-bit free-run timer to "0000H".
• The count value of the 16-bit free-run timer is output to the input capture and can be used as the base
time for capture operation.
● Functions of input capture
When the input capture detects the edge of the external signal input to the input pins, it stores the count
value of the 16-bit free-run timer in the input capture data registers. The input capture consists of the input
capture data registers corresponding to four input pins, an input capture control status register, and an edge
detection circuit.
• The detected edge can be selected from among the rising edge, falling edge, and both edges.
• Detecting the edge of the input signal generates an interrupt request to the CPU.
• Interrupt generation starts the EI2OS.
• Four input pins and four input capture data registers of the input capture can be used to measure up to
four events.
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CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.2 Block Diagram of 16-bit Input/Output Timer
MB90495G Series
7.2
Block Diagram of 16-bit Input/Output Timer
The 16-bit input/output timer consists of the following modules:
• 16-bit free-run timer
• Input capture
■ Block Diagram of 16-bit Input/Output Timer
Figure 7.2-1 Block Diagram of 16-bit Input/Output Time
Internal data bus
Input capture
Dedicated bus
16-bit free-run
timer
● 16-bit free-run timer
The count value of the 16-bit free-run timer can be use as the base time for the input capture.
● Input capture
The input capture detects the rising edge, falling edge, or both edges of the external signal input to the input
pins to retain the count value of the 16-bit free-run timer. Detecting the edge of the input signal generates
an interrupt.
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CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.2 Block Diagram of 16-bit Input/Output Timer
7.2.1
MB90495G Series
Block Diagram of 16-bit Free-run Timer
The 16-bit free-run timer consists of the following blocks:
• Prescaler
• Timer counter data register (TCDT)
• Timer counter control status register (TCCS)
■ Block Diagram of 16-bit Free-run Timer
Figure 7.2-2 Block Diagram of 16-bit Free-run Time
Timer counter data register (TCDT)
16-bit free-run timer
Pin
OF
CLK
STOP
CLR
Internal data bus
FRCK
φ
Count value output
to input capture
Prescaler
2
Timer counter control
status register
(TCCS)
IVF
IVFE STOP Reserved CLR CLK2 CLK1 CLK0
Free-run timer
interrupt request
φ : Machine clock
OF : Overflow
■ Details of Pins in Block Diagram
The 16-bit input/output timer has one 16-bit free-run timer.
The interrupt request number of the 16-big free-run timer is as follows:
Interrupt request number: 19 (13H)
● Prescaler
The prescaler divides the frequency of machine clock to supply a count clock to the 16-bit up counter. Any
of four machine clock division ratios are selected by setting the timer counter control status register
(TCCS).
● Timer counter data register (TCDT)
The timer counter data register (TCDT) is a 16-bit up counter. At read, the current count value of the 16-bit
free-run timer can be read. Writing while the counter is stopped enables any count value to be set.
● Timer counter control status register (TCCS)
The timer counter control status register (TCCS) selects the division ratio of the machine clock, clears the
count value by software, enables or disables the count operation, checks and clears the overflow generation
flag, and enables or disables interrupts.
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CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.2 Block Diagram of 16-bit Input/Output Timer
MB90495G Series
7.2.2
Block Diagram of Input Capture
The input capture consist of the following blocks:
• Input capture data registers (IPCP0 to IPCP3)
• Input capture control status registers (ICS01, ICS23)
• Edge detection circuit
■ Block Diagram of Input Capture
Figure 7.2-3 Block Diagram of Input Capture
16-bit free-run timer
Edge detection circuit
IN3
Input capture data register 3 (IPCP3)
Pin
IN2
Pin
Input capture data register 2 (IPCP2)
2
/
/
2
Input capture
interrupt request
Input capture control
status register (ICS01)
Internal data bus
Input capture control
status register (ICS23) ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
2
/
/
2
IN1
Input capture data register 1 (IPCP1)
Pin
IN0
Input capture data register 0 (IPCP0)
Pin
Edge detection circuit
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CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.2 Block Diagram of 16-bit Input/Output Timer
MB90495G Series
■ Details of Pins in Block Diagram
The 16-bit input/output timer has four input capture input pins.
The actual pin names and interrupt request numbers of the input capture are shown in Table 7.2-1.
Table 7.2-1 Pins and Interrupt Request Numbers of 16-bit Input/Output Timer
Input Pin
Actual Pin Name
Interrupt Request Number
IN0
P10/IN0
#23 (17H)
IN1
P11/IN1
#25 (19H)
IN2
P12/IN2
IN3
P13/IN3
FRCK
P36/FRCK
#30 (1EH)
−
● Input capture data registers (IPCP0 to IPCP3)
The counter value of the 16-bit free-run timer actually read when the edge of the external signal input to the
input pins (IN0 to IN3) is detected is stored in the input capture data registers (IPC0 to IPC3)
corresponding to the input pins (IN0 to IN3) to which the signal is input.
● Input capture control status registers (ICS01, ICS23)
The input capture control status registers (ICS01, ICS23) start and stop the capture operation of each input
capture, check and clear the valid edge detection flag when the edge is detected, and enable or disable an
interrupt. The ICS01 register sets the input capture corresponding to the input pins IN0 and IN1, and the
ICS23 register sets the input capture corresponding to the input pins IN2 and IN3.
● Edge detector
The edge detection circuit detects the edge of the external signal input to the input pins. The detected edge
can be selected from the rising edge, falling edge, and both edges.
264
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CM44-10114-7E
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.3 Configuration of 16-bit Input/Output Timer
MB90495G Series
7.3
Configuration of 16-bit Input/Output Timer
This section explains the pins, registers, and interrupt factors of the 16-bit input/output
timer.
■ Pins of 16-bit Input/Output Timer
The pins of the 16-bit input/output timer serve as general-purpose I/O ports. Table 7.3-1 shows the pin
functions and the pin settings required to use the 16-bit input/output timer.
Table 7.3-1 Pins of 16-bit Input/Output Timer
Pin
Name
Pin Function
Pin Setting Required for Use of
16-bit Input/Output Timer
IN0
General-purpose I/O port, capture input,
external bus pin
Set as input port in port direction register
(DDR).
IN1
General-purpose I/O port, capture input,
external bus pin
Set as input port in port direction register
(DDR).
IN2
General-purpose I/O port, capture input,
external bus pin
Set as input port in port direction register
(DDR).
IN3
General-purpose I/O port, capture input,
external bus pin
Set as input port in port direction register
(DDR).
FRCK
General-purpose I/O port, 16-bit free-run
timer clock input, external bus pin
Set as input port in port direction register
(DDR).
■ Block Diagram of Pins for 16-bit Input/Output Timer
For the block diagram of the pins, see "CHAPTER 4 I/O PORT".
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CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.3 Configuration of 16-bit Input/Output Timer
MB90495G Series
■ List of Registers and Reset Values of 16-bit Input/Output Timer
Figure 7.3-1 List of Registers and Reset Values of 16-bit Input/Output Timer
bit
Timer counter control status register (High)
(TCCS: H)
bit
Timer counter control status register (Low)
(TCCS: L)
bit
Timer counter data register (High)
(TCDT: H)
bit
Timer counter data register (Low)
(TCDT: L)
bit
Input capture control status register
(ICS01)
bit
Input capture data register 0 (High)
(IPCP0: H)
bit
Input capture data register 0 (Low)
(IPCP0: L)
bit
Input capture data register 1 (High)
(IPCP1: H)
bit
Input capture data register 1 (Low)
(IPCP1: L)
bit
Input capture control status register
(ICS23)
bit
Input capture data register 2 (High)
(IPCP2: H)
bit
Input capture data register 2 (Low)
(IPCP2: L)
bit
Input capture data register 3 (High)
(IPCP3: H)
bit
Input capture data register 3 (Low)
(IPCP3: L)
15
14
13
12
11
10
9
8
0
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
×: Undefined
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CM44-10114-7E
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.3 Configuration of 16-bit Input/Output Timer
MB90495G Series
■ Generation of Interrupt Request from 16-bit Input/Output Timer
The 16-bit input/output timer can generate an interrupt request as a result of the following factors:
● Overflow in 16-bit free-run timer
In the 16-bit input/output timer, when the 16-bit free-run timer overflows, the overflow generation flag bit
in the timer counter control status register (TCCS:IVF) is set to 1. When an overflow interrupt is enabled
(TCCS:IVFE = 1), an interrupt request is generated.
● Edge detection by capture function
When the edge of the external signal input to the input pins (IN0 to IN3) is detected, the input capture valid
edge detection flag bit in the input capture control status register (ICS:ICP) corresponding to the input pin
as the signal edge is detected is set to 1. When the input capture interrupt corresponding to the channel
generating an interrupt request is enabled (ICS:ICE), an interrupt request is generated.
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CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.3 Configuration of 16-bit Input/Output Timer
MB90495G Series
Timer Counter Control Status Register (TCCS) (High)
7.3.1
The timer counter control status register (TCCS) (High) enables or disables input of an
external clock to the 16-bit free-run timer.
■ Timer Counter Control Status Register (TCCS) (High)
Figure 7.3-2 Timer Counter Control Status Register (TCCS) (High)
15
14
13
12
11
10
9
8
Reset value
0XXXXXXXB
R/W ⎯
⎯
⎯
⎯
⎯
R/W : Read/Write
X
: Undefined
⎯ : Unused
: Reset value
⎯
⎯
bit 15
Count clock input enable bit (FRCK pin)
ECKI
0
General-purpose I/O port
1
Count clock input pin of 16-bit free-run timer
Table 7.3-2 Functions of Timer Counter Control Status Register (TCCS) (High)
Bit Name
bit 15
268
ECKI:
Count clock input enable
bit
Function
This bit enables or disables input of an external count clock to the 16-bit free-run
timer.
When set to 0: FRCK pin set to general-purpose I/O port
When set to 1: FRCK pin set to input pin count clock to 16-bit free-run timer
Note:
When using the FRCK pin for input of a count clock to the 16-bit free-run
timer, set the pin to an input port in the port direction register (DDR).
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.3 Configuration of 16-bit Input/Output Timer
MB90495G Series
7.3.2
Timer Counter Control Status Register (TCCS) (Low)
The timer counter control status register (TCCS) (Low) selects the count clock and
conditions for clearing the counter, clears the counter, enables or disables the count
operation or interrupt, and checks the interrupt request flag.
■ Timer Counter Control Status Register (TCCS) (Low)
Figure 7.3-3 Timer Counter Control Status Register (TCCS) (Low)
7
6
5
4
3
2
1
0
Reset value
00000000
B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 2
bit 1 bit 0
Count clock setting bits
CLK2 CLK1 CLK0
0
0
Count clock φ = 16 MHz φ = 8 MHz
0
φ
0.125 μs 0.25 μs
φ = 4 MHz φ = 1 MHz
62.5 ns 0.125 μs 0.25 μs
1 μs
0
0
1
φ/2
0.5 μs
2 μs
0
1
0
φ/4
0.25 μs
0.5 μs
1 μs
4 μs
0
1
1
φ/8
0.5 μs
1 μs
2 μs
8 μs
1
0
0
φ/16
1 μs
2 μs
4 μs
16 μs
1
0
1
φ/32
2 μs
4 μs
8 μs
32 μs
1
1
0
φ/64
4 μs
8 μs
16 μs
64 μs
1
1
1
φ/128
8 μs
16 μs
32 μs
128 μs
φ: Machine clock
bit 3
CLR
0
1
Timer count clear bit
No effect
Initializes counter to "0000H"
bit 4
Reserved bit
Reserved
0
Always set to "0"
bit 5
Timer count bit
STOP
0
1
Counting enable
Counting disable
bit 6
Overflow interrupt enable bit
IVFE
0
Overflow interrupt disable
1
Overflow interrupt enable
bit 7
Overflow generation flag bit
IVF
R/W : Read/Write
: Reset value
CM44-10114-7E
0
1
Read
Write
No overflow
Clear
Overflow
No effect
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CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.3 Configuration of 16-bit Input/Output Timer
MB90495G Series
Table 7.3-3 Functions of Timer Counter Control Status Register (TCCS) (Low)
Bit Name
270
Function
bit 0
bit 1
bit 2
CLK2, CLK1, CLK0:
Count clock select bits
These bits set the count clock to the 16-bit free-run time.
Note:
1. Set the count clock after stopping the count operation (STOP = 1).
2. When rewriting the count clock, write 1 to the timer counter clear bit (CLR)
and clear the count value.
bit 3
CLR:
Timer count clear bit
This bit clears the count value of the 16-bit free-run timer.
When set to 1: Clears timer counter data register (TCDT) to "0000H"
When set to 0: No effect
Read: 0 is always read.
• When the count value changes, the CLR bit is cleared.
• When clearing the count value while stopping the count operation, write
"0000H" to the timer counter data register (TCDT).
bit 4
Reserved: Reserved bit
Always set this bit to 0.
bit 5
STOP:
Timer count bit
This bit enables or disables (stops) the count operation of the 16-bit free-run
timer.
When set to 0: Enables count operation
The 16-bit timer counter data register (TCDT) starts incrementing in
synchronization with the count clock selected by the count clock select bits
(CLK1 and CLK0).
When set to 1: Stops count operation
bit 6
IVFE:
Overflow interrupt
enable bit
This bit enables or disables an interrupt request generated when the 16-bit freerun timer overflows.
When set to 0: No interrupt request generated at overflow (IVF = 1)
When set to 1: Generates interrupt request at overflow (IVF = 1)
bit 7
IVF:
Overflow generation flag
bit
This bit indicates that the 16-bit free-run timer has overflowed.
• If the 16-bit free-run timer overflows or mode setting causes a compare match
with the compare register 0 to clear the counter, this bit is set to 1.
• When an overflow occurs with an overflow interrupt enabled (IVFE = 1), an
interrupt request is generated.
When set to 0: Clears bit
When set to 1: No effect
When EI2OS started: Bit cleared
Read by read modify write instructions: 1 is always read.
Note:
If "1" is set while at the same time "0" is written, "0" is registered.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.3 Configuration of 16-bit Input/Output Timer
MB90495G Series
7.3.3
Timer Counter Data Register (TCDT)
The timer counter data register (TCDT) is a 16-bit up counter. At read the register value
being counted is read. At write while the counter is stopped, any count value can be set.
■ Timer Counter Data Register (TCDT)
Figure 7.3-4 Timer Counter Data Register (TCDT)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
Timer counter data
register (TCDT): High
T15
T14
T13
T12
T11
T10
T9
Reset value
T8
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Timer counter data
register (TCDT): Low
T7
T6
T5
T4
T3
T2
T1
T0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W: Read/Write
■ Count Operation of Timer Counter Data Register (TCDT)
• When the timer counter data register (TCDT) is read during the count operation, the count value of the
16-bit free-run timer is read.
• When the count value of the timer counter data register (TCDT) increments from "FFFFH" to "0000H",
an overflow occurs and the overflow generation flag bit (TCCS:IVF) is also set to 1.
• When an overflow occurs (TCCS:IVF = 1) with an overflow interrupt enabled (TCCS:IVFE = 1), an
overflow interrupt request is generated.
• The count value of the timer counter data register (TCDT) is retained while the count operation is
stopped.
• When stopping the count operation of the timer counter data register (TCDT), write 1 to the timer count
operation bit (TCCS:STOP).
• When the count operation stops (TCCS:STOP = 1), the counter of the timer counter data register
(TCDT) can be set to any value.
● Factors clearing timer counter data register (TCDT)
The timer counter data register (TCDT) is cleared to "0000H" by the following factors:
• Reset
• Writing 1 to the timer count clear bit (TCCS:CLR) (possible even during count operation)
• Writing "0000H" to timer counter data register (TCDT) while count operation stopped
• Overflow in 16-bit free-run timer
Note:
CM44-10114-7E
Always use a word instruction (MOVW) to set the timer counter data register (TCDT).
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271
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.3 Configuration of 16-bit Input/Output Timer
MB90495G Series
Input Capture Control Status Registers (ICS01 and
ICS23)
7.3.4
The input capture control status registers sets the operation of input captures. The
ICS01 register sets the operation of input captures 0 and 1 and the ICS23 sets the
operation of input captures 2 and 3.
The input capture control status registers provides the following settings:
• Selecting the edge to be detected
• Enabling or disabling an interrupt when the edge is detected
• Checking and clearing the valid edge detection flag when the edge is detected
■ Input Capture Control Status Registers (ICS01 and ICS23)
Figure 7.3-5 Input Capture Control Status Registers (ICS01 and ICS23)
7
6
5
4
3
2
1
0
Reset value
0 0 0 0 0 0 0 0
B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 1 bit 0
EG01 EG00
Input capture 0 (2) Edge select bits
0
0
No edge detection
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
bit 3 bit 2
EG11 EG10
Operation disable
Operation enable
Input capture 1 (3) Edge select bit
0
0
No edge detection
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
Operation disable
Operation enable
bit 4
Input capture 0 (2) Interrupt enable bit
ICE0
0
Input capture 0 (2) Interrupt disable
1
Input capture 0 (2) Interrupt enable
bit 5
ICE1
0
1
Input capture 1 (3) Interrupt enable bit
Input capture 1 (3) Interrupt disable
Input capture 1 (3) Interrupt enable
bit 6
ICP0
Input capture 0 (2) Valid edge detection flag bit
0
Read
Input capture 0 (2)
Write
Clears ICP0 bit
1
No valid edge detected
Input capture 0 (2)
No effect
Valid edge detected
bit 7
ICP1
Input capture 1 (3) Valid edge detection flag bit
0
Read
Input capture 1 (3)
No valid edge detected
Write
Clears ICP1 bit
1
Input capture 1 (3)
No effect
R/W : Read/Write
Valid edge detected
: Reset value
The numbers in parentheses indicate channel number of ICS 23.
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CM44-10114-7E
MB90495G Series
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.3 Configuration of 16-bit Input/Output Timer
Table 7.3-4 Functions of Input Capture Control Status Register (1 / 2)
Bit Name
Function
bit0
bit1
EG01, CEG00:
Input capture 0 edge
select bits
These bits enable or disable the operation of input capture 0.
The edge detected by input capture 0 is selected when the operation of input
capture 0 is enabled.
EG01, EG00 = "00B":
The operation of input capture 0 is disabled and no edge is detected.
EG01, EG00 ≠ "00B":
The operation of input capture 0 is enabled and the edge is detected.
bit 2
bit 3
EG11, EG10:
Input capture 1 edge
select bits
These bits enable or disable the operation of input capture 1.
The edge detected by input capture 1 is selected when the operation of input
capture 1 is enabled.
EG01, EG00 = "00B":
The operation of input capture 1 is disabled and no edge is detected.
EG01, EG00 ≠ "00B":
The operation of input capture 1 is enabled and the edge is detected.
bit 4
ICE0:
Input capture 0 interrupt
enable bit
This bit enables or disables an interrupt when the edge is detected by input
capture 0.
When set to 0:
No interrupt is generated even when the valid edge is detected by input
capture 0.
When set to 1:
An interrupt is generated when the valid edge is detected by input capture 0.
bit 5
ICE1:
Input capture 1 interrupt
enable bit
This bit enables or disables an interrupt when the edge is detected by input
capture 1.
When set to 0:
No interrupt is generated even when the edge is detected by input capture 1.
When set to 1:
An interrupt is generated when the edge is detected by input capture 1.
bit 6
ICP0:
Input capture 0 valid
edge detection flag bit
This bit indicates the edge detection by input capture 0.
• When the valid edge selected by the input capture 0 edge select bits (EG01,
EG00) is detected, the ICP0 bit is set to 1.
• When the valid edge is detected by input capture 0 (ICP0 = 1) when an
interrupt due to the edge detection by input capture 0 is enabled (ICE0 = 1),
an interrupt is generated.
When set to 0:
The bit is cleared.
When set to 1:
No effect
When EI2OS started:
The bit is cleared.
Read by read modify write instructions:
1 is always read.
Note:
If "1" is set while at the same time "0" is written, "0" is registered.
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CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.3 Configuration of 16-bit Input/Output Timer
MB90495G Series
Table 7.3-4 Functions of Input Capture Control Status Register (2 / 2)
Bit Name
bit 7
274
ICP1:
Input capture 1 valid
edge detection flag bit
Function
This bit indicates the edge detection by input capture 1.
• When the valid edge selected by the input capture 1 edge select bits (EG11,
EG10) is detected, the ICP1 bit is set to 1.
• When the valid edge is detected by input capture 1 (ICP1 = 1) when an
interrupt due to the edge detection by input capture 1 is enabled (ICE1 = 1),
an interrupt is generated.
When set to 0:
The bit is cleared.
When set to 1:
No effect
When EI2OS started:
The bit is cleared.
Read by read modify write instructions:
1 is always read.
Note:
If "1" is set while at the same time "0" is written, "0" is registered.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.3 Configuration of 16-bit Input/Output Timer
MB90495G Series
7.3.5
Input Capture Data Registers 0 to 3 (IPCP0 to IPCP3)
The input capture data registers 0 to 3 (IPCP0 to IPCP3) store the counter value of the
16-bit free-run timer read in the timing with the edge detection by the input capture. The
counter value of the 16-bit free-run timer is stored in the input capture data registers
(IPCP0 to IPCP3) corresponding to the input pins (IN0 to IN3) to which an external signal
is input.
■ Input Capture Data Registers 0 to 3 (IPCP0 to IPCP3)
Figure 7.3-6 Input Capture Data Registers 0 to 3 (IPCP0 to IPCP3)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
Input capture data
register (IPCP): High
Input capture data
register (IPCP): Low
Reset value
CP15 CP14 CP13 CP12 CP11 CP10 CP9 CP8
R
R
R
R
R
R
R
XXXXXXXX B
R
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Reset value
CP7 CP6 CP5 CP4 CP3 CP2 CP1 CP0
XXXXXXXX B
R
R
R
R
R
R
R
R
R: Read only
X: Undefined
■ Operation of Input Capture Data Registers 0 to 3 (IPCP0 to IPCP3)
• At the same time that the edges of signals input from the input pins (IN0 to IN3) of the 16-bit input/
output timer are detected, the counter value of the 16-bit free-run timer is stored in the input capture data
registers 0 to 3 (IPCP0 to IPCP3) corresponding to the input pins (IN0 to IN3).
Note:
CM44-10114-7E
Always use a word instruction (MOVW) to read the input capture data registers 0 to 3 (IPCP0 to IPCP3).
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275
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.4 Interrupts of 16-bit Input/Output Timer
7.4
MB90495G Series
Interrupts of 16-bit Input/Output Timer
The interrupt factors of the 16-bit input/output timer include an overflow in the 16-bit
free-run timer and edge detection by the input capture. Interrupt generation starts
EI2OS.
■ Interrupt Control Bits and Interrupt Factors of 16-bit Input/Output Timer
Table 7.4-1 shows the interrupt control bits and interrupt factors of the 16-bit input/output timer.
Table 7.4-1 Interrupt Control Bits and Interrupt Factors of 16-bit Input/Output Timer
Interrupt Name
Overflow interrupt
Input Capture Interrupt
Overflow in counter
value of 16-bit freerun timer
Valid edge input to input pins (IN0 to IN3) of input capture
Interrupt factor
IN0
IN1
IN2
IN3
Interrupt request flag bit
TCCS:IVF
ICS01:ICP0
ICS01:ICP1
ICS23:ICP0
ICS23:ICP1
Interrupt enable bit
TCCS:IVFE
ICS01:ICE0
ICS01:ICE1
ICS23:ICE0
ICS23:ICE1
● 16-bit free-run timer interrupt
• When the counter value of the timer counter data register (TCDT) increments from "FFFFH" to
"0000H", an overflow occurs and the overflow generation flag bit (TCCS:IVF) is set simultaneously to
1.
• When an overflow occurs (TCCS:IVF = 1) with an overflow interrupt enabled (TCCS:IVFE = 1), an
overflow interrupt is generated.
● Input capture interrupt
• When the valid edge selected by the input capture edge select bit (ICS:EG) is detected, the input capture
interrupt request flag bits (ICS01, ICS23:ICP1, ICP0) corresponding to the input pins (IN0 to IN3) are
set to 1.
• When the valid edge is detected by the input captures corresponding to the input pins (IN0 to IN3) with
the input capture interrupts corresponding to the input pins (IN0 to IN3) enabled, an input capture
interrupt is generated.
■ Correspondence between 16-bit Input/Output Timer Interrupt and EI2OS
For details of the interrupt number, interrupt control register, and interrupt vector address, see "3.5
Interrupt".
■ Interrupts and EI2OS Function of 16-bit Input/Output Timer
The 16-bit input/output timer corresponds to the EI2OS function. The generation of enabled interrupt starts
the EI2OS. However, it is necessary to disable generation of interrupt requests by resources sharing the
interrupt control register (ICR) with the 16-bit input/output timer.
276
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.5 Explanation of Operation of 16-bit Free-run Timer
MB90495G Series
7.5
Explanation of Operation of 16-bit Free-run Timer
After a reset, the 16-bit free-run timer starts incrementing from "0000H". When the
counter value is incremented from "FFFFH" to "0000H", an overflow occurs.
■ Setting of 16-bit Free-run Timer
Operation of the 16-bit free-run timer requires the setting shown in Figure 7.5-1.
Figure 7.5-1 Setting of 16-bit Free-run Timer
bit 15 14
13
12
11
10
9
bit 8 bit 7
6
5
4
3
2
1
bit 0
IVF IVFE STOP Reserved CLR CLK2 CLK1 CLK0
TCCS
0
0
0
Counter value of 16-bit free-run timer
TCDT
: Used bit
0
: Set 0
Reserved : Always set to "0"
■ Operation of 16-bit Free-run Timer
• After a reset, the 16-bit free-run timer starts incrementing from "0000H" in synchronization with the
external clock signal or the count clock selected by the count clock select bits (TCCS:CLK2, CLK1,
CLK0).
• When the counter value of the timer counter data register (TCDT) is incremented from "FFFFH" to
"0000H", an overflow occurs. When an overflow occurs, the overflow generation flag bit (TCCS:IVF) is
set to 1 and the 16-bit free-run timer starts incrementing again from "0000H".
• When an overflow occurs (TCCS:IVF = 1) with an overflow interrupt enabled (TCCS:IVFE = 1), an
overflow interrupt is generated.
• When stopping the count operation of the timer counter data register (TCDT), write 1 to the timer count
bit (TCCS:STOP).
• Set the counter value in the timer counter data register (TCDT) after stopping the count operation of the
16-bit free-run timer. After completing setting of the count value, enable the count operation of the 16bit free-run timer (TCCS:STOP = 0).
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CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.5 Explanation of Operation of 16-bit Free-run Timer
MB90495G Series
■ Operation Timing of 16-bit Free-run Timer
Figure 7.5-2 shows counter clearing at an overflow.
Figure 7.5-2 Counter Clearing at an Overflow
Counter value
Overflow
FFFFH
BFFF H
7FFFH
3FFFH
0000H
Time
Reset
Overflow interrupt
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CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.6 Explanation of Operation of Input Capture
MB90495G Series
7.6
Explanation of Operation of Input Capture
When the input capture detects the edge of the external signal input to the input pin, it
stores the counter value of the 16-bit free-run timer in the input capture data register.
■ Setting of Input Capture
Operation of the input capture requires the setting shown in Figure 7.6-1.
Figure 7.6-1 Setting of Input Capture
bit 15 14
ICS
IPCP
DDR port
direction register
13
12
11
10
9
bit 8 bit 7
6
5
4
3
2
1
bit 0
ICP1ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
Retains counter value of 16-bit free-run timer
Set the bit corresponding to the pin
used as capture input pin to 0.
: Used bit
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CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.6 Explanation of Operation of Input Capture
MB90495G Series
■ Operation of Input Capture
• When the valid edges of the external signals input to the input pins (IN0 to IN3) are detected, the input
capture valid edge detection flag bit (ICS:ICP) corresponding to the input pin is set to 1. At the same
time, the count value of the 16-bit free-run timer is stored in the input capture data registers (IPCP)
corresponding to the input pins (IN0 to IN3).
• The edge to be detected can be selected from the rising edge, falling edge and both edges by setting the
input capture edge select bit in the input capture control status register (ICS:EG).
• When the effective edge is detected by the input captures corresponding to the input pins (IN0 to IN3)
when the input captures corresponding to the input pins (IN0 to IN3) are enabled for interrupts, an input
capture interrupt is generated.
• The input capture valid edge detection flag bit (ICS:ICP) is set when the valid edge is detected,
regardless of the interrupt enable settings (ICS01, ICS23:ICE1, ICE0).
• Table 7.6-1 shows the correspondence between the input pins and input captures.
Table 7.6-1 Correspondence between Input Pins and Input Captures
280
Input Pin
Interrupt Request Flag
Bit of Input Capture
Interrupt Output Enable
Bit of Input Capture
Input Capture Data
Register
IN0
ICS01:ICP0
ICS01:ICE0
IPCP0
IN1
ICS01:ICP1
ICS01:ICE1
IPCP1
IN2
ICS23:ICP0
ICS23:ICE0
IPCP2
IN3
ICS23:ICP1
ICS23:ICE1
IPCP3
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CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.6 Explanation of Operation of Input Capture
MB90495G Series
■ Operation Timing of Input Capture
Figure 7.6-2 shows the timing of reading the counter value of the 16-bit free-run timer.
Figure 7.6-2 Timing of Reading Counter Value of Input Capture
φ
Counter value
Input capture input
N
N+1
Valid edge
Capture signal
Input capture data
register (IPCP)
N+1
Input capture interrupt
φ: Machine clock
Reads counter value
Figure 7.6-3 shows the timing of the capture operation depending on the edge type.
Figure 7.6-3 Timing of Capture Operation Depending on Edge Type
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
IN0 (Rising edge)
IN1 (Falling edge)
IN2 (Both edges)
Input capture data
register 0 (IPCP0)
Undefined
Input capture data
register1 (IPCP1)
Undefined
Input capture data
register 2 (IPCP2)
Undefined
3FFFH
7FFFH
BFFFH
3FFFH
Input capture 0
interrupt
Input capture 1
interrupt
Input capture 2
interrupt
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CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.7 Precautions when Using 16-bit Input/Output Timer
7.7
MB90495G Series
Precautions when Using 16-bit Input/Output Timer
This section explains the precautions when using the 16-bit input/output timer.
■ Precautions when 16-bit Input/Output Timer
● Precautions when setting 16-bit free-run timer
• Do not change the count clock select bits (TCCS:CLK2, CLK1, CLK0) during the count operation
(TCCS:STOP = 0).
• The counter value of the 16-bit free-run timer is cleared to "0000H" by reset. The 16-bit free-run timer
can be set by writing any count value to the timer counter data register (TCDT) while the count
operation is stopped (TCCS:STOP = 1).
• Always use a word instruction (MOVW) to set the timer counter data register (TCDT).
● Precautions on interrupts
• When an overflow interrupt or an input capture interrupt is enabled, clear only the set bit of the overflow
generation flag bit or the input capture valid edge detection flag bit. For example, when clearing the flag
bit for the factor that accepted an interrupt, avoid unconditional clearing of the interrupt request flag bits
other than those for the factor accepting the interrupt, otherwise another input capture interrupt may be
generated.
• If the interrupt request flag bits in the 16-bit input/output timer (TCCS:IVF, ICS01, ICS23:ICP1, ICP0)
are set to 1 and interrupts corresponding to the set interrupt request flag bits are enabled (TCCS:IVFE =
1, ICS01, ICS23:ICE1 = 1, ICE0 = 1), it is impossible to return from interrupt processing. Always clear
the interrupt request flag bits. When using the EI2OS, the set interrupt request flag bits are cleared
automatically when the EI2OS, the set interrupt request flag bits are cleared automatically when the
EI2OS is started.
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7.8
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.8 Program Example of 16-bit Input/Output Timer
Program Example of 16-bit Input/Output Timer
This section gives a program example of the 16-bit input/output timer.
■ Processing of Program for Measuring Cycle Using Input Capture
• The cycle of a signal input to the IN0 pin is measured.
• The 16-bit free-run timer and input capture 0 are used.
• The rising edge is selected as the edge to be detected.
• The machine clock (φ) is 16 MHz and the count clock is φ/4 (0.25 μs).
• The overflow interrupt and input capture interrupt of input capture 0 are used.
• The overflow interrupt of the 16-bit free-run timer is counted beforehand and used for the cycle
calculation.
• The cycle can be determined from the following equation:
Cycle = (overflow count × 10000H+ nth IPCP0 value - (n-1)th IPCP0 value) × count clock cycle
= (overflow count × 10000H+ nth IPCP0 value - (n-1)th IPCP0 value) × 0.25μs
● Coding example
DDR1
TCCS
TCDT
ICS01
IPCP0
IVFE
ICP0
ICR04
ICR06
DATA
EQU 000001
; Port direction register
EQU 000058H
; Timer counter control status register
EQU 000056H
; Timer counter data register
EQU 000054H
; Input capture control status register 01
EQU 000050H
; Input capture data register 0
EQU TCCS:5
; Overflow interrupt enable bit
EQU ICS01:6
; Input capture 0 interrupt request flag bit
EQU 0000B4H
; 16-bit input capture interrupt control register
EQU 0000B6H
; 16-bit input capture interrupt control register
DSEG ABS=00H
ORG 0100H
OV_CNT RW
1
; Overflow counter
DATA
ENDS
;-----Main program--------------------------------------------------------------CODE
CSEG ABS=0FFH
START:
; Stack pointer (SP)
; already initialized
:
AND CCR,#0BFH
; Interrupt disabled
MOV I:ICR04,#00H
; Interrupt level 0 (higthest)
MOV I:ICR06,#00H
; Intrrupt level 0 (higthest)
MOV I:DDR1,#00000000B ; Pin set as input
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7.8 Program Example of 16-bit Input/Output Timer
MOV
MOV
I:TCCS,#00110100B
;
;
;
I:ICS01,#00010001B ;
;
;
;
;
ILM,#07
;
CCR,#40H
;
MB90495G Series
Count operation enabled, counter cleared
Overflow, interrupt enabled
Count clock of φ/4 selected
INO pin selected
IPCP0 set to rising edge
IPCP1 set to no edge detection
Each interrupt request flag cleared
Input capture interrupt request enabled
Interrupt mask level set and interrupt enabled
Interrupt enabled
MOV
OR
:
;-----Interrupt program---------------------------------------------------------WARI1
CLRB I:ICP0
; Input capture 0 interrupt request
; flag cleared
:
User Processing (such as cycle calculation)
:
MOV A,0
; Overflow because of next cycle measurement
; Counter cleared
MOV
D:OV_CNT,A
RETI
; Return from interrupt processing
WARI2
CLRB I:IVFE
; Overflow interrupt request flag cleared
INC D:OV_CNT
; Overflow counter incremented by one
RETI
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG 0FFA0
; Vector set to interrupt number #23 (17H)
DSL WARI1
; Input capture 0 interrupt
ORG 0FFB0
; Vectorset to interrupt number #19 (13H)
DSL WARI2
; Overflow interrupt
ORG 0FFDCH
; Reset vector set
DSL START
DB
00H
; Set to single-chip mode
VECT
ENDS
END START
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CHAPTER 8
16-BIT RELOAD TIMER
This chapter explains the functions and the operations
of 16-bit reload timer.
8.1 Overview of 16-bit Reload Timer
8.2 Block Diagram of 16-bit Reload Timer
8.3 Configuration of 16-bit Reload Timer
8.4 Interrupts of 16-bit Reload Timer
8.5 Explanation of Operation of 16-bit Reload Timer
8.6 Precautions when Using 16-bit Reload Timer
8.7 Program Example of 16-bit Reload Timer
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CHAPTER 8 16-BIT RELOAD TIMER
8.1 Overview of 16-bit Reload Timer
8.1
MB90495G Series
Overview of 16-bit Reload Timer
The 16-bit reload timer has the following functions:
• The count clock can be selected from three internal clocks and external event clocks.
• A software trigger or external trigger can be selected as the start trigger.
• If the 16-bit timer register (TMR) underflows, an interrupt can be generated to the
CPU. The 16-bit reload timer can be used as an interval timer by using an interrupt.
• If the TMR underflows, either the one-shot mode for stopping the TMR count
operation, or the reload mode for reloading the value of the 16-bit reload register
(TMRLR) to the TMR to continue the TMR count operation can be selected.
• The 16-bit reload timer corresponds to the EI2OS.
• The MB90495G series has two channels of 16-bit reload timers.
■ Operation Modes of 16-bit Reload Timer
Table 8.1-1 indicates the operation modes of the 16-bit reload timer.
Table 8.1-1 Operation Modes of 16-bit Reload Timer
Count Clock
Start Trigger
Operation Performed upon Underflow
Internal clock mode
Software trigger
External trigger
One-shot mode
Reload mode
Event count mode
Software trigger
One-shot mode
Reload mode
■ Internal Clock Mode
• When the count clock select bits in the timer control status register (TMCSR:CSL1, CSL0) are set to
"00B", "01B" or "10B", the 16-bit reload timer is set in the internal clock mode.
• In the internal clock mode, the 16-bit reload timer decrements in synchronization with the internal clock.
• The count clock select bits in the timer control status register (TMCSR:CSL1, CSL0) can be used to
select three count clock cycles.
• The start trigger sets the edge detection for a software trigger or an external trigger.
■ Event Count Mode
• When the count clock select bits in the timer control status register (TMCSR:CSL1, CSL0) are set to
"11B", the 16-bit reload timer is set to the event count mode.
• In the event count mode, the 16-bit reload timer decrements in synchronization with the edge detection
of the external event clock input to the TIN pin.
• A software trigger is selected as the start trigger.
• The 16-bit reload timer can be used as an interval timer by using a fixed cycle of the external clock.
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CHAPTER 8 16-BIT RELOAD TIMER
8.1 Overview of 16-bit Reload Timer
MB90495G Series
■ Operation at Underflow
When the start trigger is input, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit
timer register, starting decrementing in synchronization with the count clock. When the 16-bit timer
register (TMR) is decremented from "0000H" to "FFFFH", an underflow occurs.
• When an underflow occurs with an underflow interrupt enabled (TMCSR:INTE = 1), an underflow
interrupt is generated.
• The TMRLR operation when an underflow occurs is set by the reload select bit in the timer control
status register (TMCSR:RELD).
[One-shot mode (TMCSR:RELD = 0)]
When an underflow occurs, the TMR count operation is stopped. When the next start trigger is input, the
value set in the TMRLR is reloaded in the TMR, starting the TMR count operation.
• In the one-shot mode, during the TMR count operation, a High-level or Low-level rectangular wave is
output from the TOT pin.
• The pin output level select bit in the timer control status register (TMCSR:OUTL) can be set to select
the level (High or Low) of the rectangular wave.
[Reload mode (TMCSR:RELD = 1)]
When an underflow occurs, the value set in the TMRLR is reloaded to the TMR, continuing the TMR count
operation.
• In the reload mode, a toggle wave inverting the output level of the TOT pin is output each time an
underflow occurs during the TMR count operation.
• The pin output level select bit in the timer control status register (TMCSR:OUTL) can be set to select
the level (High or Low) of a toggle wave.
• The 16-bit reload timer can be used as an interval timer by using an underflow interrupt.
Table 8.1-2 Interval Time of 16-bit Reload Timer
Count Clock
Count Clock Cycle
Internal clock mode
Event count mode
Interval Time
21T (0.125 μs)
0.125 μs to 8.192 ms
23T (0.5 μs)
0.5 μs to 32.768 ms
25T (2.0 μs)
2.0 μs to 131.1 ms
23T or more
0.5 μs
T: Machine cycle
The values in Interval time and the parenthesized values are provided when the machine
clock operates at 16 MHz.
References:
CM44-10114-7E
• The 16-bit reload timer 0 can be used as the clock input source of the UART0.
• The 16-bit reload timer 1 can be used as the clock input source of the UART1 and the start trigger of
the A/D converter.
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CHAPTER 8 16-BIT RELOAD TIMER
8.2 Block Diagram of 16-bit Reload Timer
8.2
MB90495G Series
Block Diagram of 16-bit Reload Timer
The 16-bit reload timers 0 and 1 composed of the following seven blocks:
• Count clock generator
• Reload controller
• Output controller
• Operation controller
• 16-bit timer register (TMR)
• 16-bit reload register (TMRLR)
• Timer control status register (TMCSR)
■ Block Diagram of 16-bit Reload Timer
Figure 8.2-1 Block Diagram of 16-bit Reload Timer
Internal data bus
TMRLR
16-bit reload register
Reload signal
Reload
controller
TMR
16-bit timer register UF
CLK
Count clock generator
Machine
clock
φ
Prescaler
3
Gate
input
Valid
clock
detector
Wait signal
Output to
internal resource
Clear
Internal
clock
CLK
Input
controller
Pin
TIN
Clock
selector
External clock
3
2
Output controller
Output signal
generator
⎯
⎯
TOT
EN
Select
signal
Function selected
⎯
Pin
Operation
controller
⎯ CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG
Timer control status register (TMCSR)
Interrupt request
output
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CHAPTER 8 16-BIT RELOAD TIMER
8.2 Block Diagram of 16-bit Reload Timer
MB90495G Series
● Details of pins in block diagram
There are two channels for 16-bit reload timer.
The actual pin names, outputs to resources, and interrupt request numbers for each channel are as follows:
16-bit reload timer 0:
TIN pin: P20/TIN0
TOT pin: P21/TOT0
Output to resources: Clock input source of UART0
Interrupt request number: #17 (11H)
16-bit reload timer 1:
TIN pin: P22/TIN1
TOT pin: P23/TOT1
Output to resources: Clock input source of UART1 and start trigger of A/D converter
Interrupt request number: #36 (24H)
● Count clock generator
The count clock generator generates a count clock supplied to the 16-bit timer register (TMR) on the basis
of the machine clock or external event clock.
● Reload controller
When the 16-bit reload timer starts operation or the TMR underflows, the reload controller reloads the
value set in the 16-bit reload register (TMRLR) to the TMR.
● Output controller
The output controller inverts and enables or disables the output of the TOT pin at underflow.
● Operation controller
The operation controller starts or stops the 16-bit reload timer.
● 16-bit timer register (TMR)
The 16-bit timer register (TMR) is a 16-bit down counter. At read, the value being counted is read.
● 16-bit reload register (TMRLR)
The 16-bit reload register (TMRLR) sets the interval time of the 16-bit reload timer. When the 16-bit reload
timer starts operation or the 16-bit timer register (TMR) underflows, the value set in the TMRLR is
reloaded to the TMR.
● Timer control status register (TMCSR)
The timer control status register (TMCSR) selects the operation mode, sets the operation conditions, selects
the start trigger, performs a start using the software trigger, selects the reload operation mode, enables or
disables an interrupt request, sets the output level of the TOT pin, and sets the TOT output pin.
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CHAPTER 8 16-BIT RELOAD TIMER
8.3 Configuration of 16-bit Reload Timer
8.3
MB90495G Series
Configuration of 16-bit Reload Timer
This section explains the pins, registers, and interrupt factors of the 16-bit reload timer.
■ Pins of 16-bit Reload Timer
The pins of the 16-bit reload timer serve as general-purpose I/O ports. Table 8.3-1 shows the pin functions
and the pin settings required to use the 16-bit reload timer.
Table 8.3-1 Pins of 16-bit Reload Timer
Pin Name
Pin Function
Pin Setting Required for Use in
16-bit Reload Timer
TIN0
General-purpose I/O port,
16-bit reload timer input
Set as input port in port direction register (DDR).
TOT0
General-purpose I/O port,
16-bit reload timer output
Set timer output enable (TMCSR0:OUTE = 1).
TIN1
General-purpose I/O port,
16-bit reload timer input
Set as input port in port direction register (DDR).
TOT1
General-purpose I/O port,
16-bit reload timer output
Set timer output enable (TMCSR1:OUTE = 1).
■ Block Diagram for Pins of 16-bit Reload Timer
For details of the block diagram for pins, see "CHAPTER 4 I/O PORT".
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CHAPTER 8 16-BIT RELOAD TIMER
8.3 Configuration of 16-bit Reload Timer
MB90495G Series
■ List of Registers and Reset Values of 16-bit Reload Timer
● Registers of 16-bit reload timer 0
Figure 8.3-1 List of Registers and Reset Values of 16-bit Reload Timer 0
bit
Timer control status register (High)
(TMCSR0)
bit
Timer control status register (Low)
(TMCSR0)
bit
16-bit timer register (High)
(TMR0)
bit
16-bit timer register (Low)
(TMR0)
bit
16-bit reload register (High)
(TMRLR0)
bit
16-bit reload register (Low)
(TMRLR0)
15
14
13
12
11
10
9
8
×
×
×
×
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
×: Undefined
● Registers of 16-bit reload timer 1
Figure 8.3-2 List of Registers and Reset Values of 16-bit Reload Timer
bit
Timer control status register (High)
(TMCSR1)
bit
Timer control status register (Low)
(TMCSR1)
bit
16-bit timer register (High)
(TMR1)
bit
16-bit timer register (Low)
(TMR1)
bit
16-bit reload register (High)
(TMRLR1)
bit
16-bit reload register (Low)
(TMRLR1)
15
14
13
12
11
10
9
8
×
×
×
×
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
×: Undefined
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CHAPTER 8 16-BIT RELOAD TIMER
8.3 Configuration of 16-bit Reload Timer
MB90495G Series
■ Generation of Interrupt Request from 16-bit Reload Timer
When the 16-bit reload timer is started and the count value of the 16-bit timer register is decremented from
"0000H" to "FFFFH", an underflow occurs. When an underflow occurs, the UF bit in the timer control
status register is set to 1 (TMCSR:UF). If an underflow interrupt is enabled (TMCSR:INTE = 1), an
interrupt request is generated.
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CHAPTER 8 16-BIT RELOAD TIMER
8.3 Configuration of 16-bit Reload Timer
MB90495G Series
8.3.1
Timer Control Status Registers (High) (TMCSR0:H,
TMCSR1:H)
The timer control status registers (High) (TMCSR0:H, TMCSR1:H) set the operation
mode and count clock.
This section also explains the bit 7 in the timer control status registers (Low)
(TMCSR0:L, TMCSR1:L).
■ Timer Control Status Registers (High) (TMCSR0:H, TMCSR1:H)
Figure 8.3-3 Timer Control Status Registers (High) (TMCSR0:H, TMCSR1:H)
15
14
13
12
11
10
9
8
7
Reset value
XXXX00000B
⎯ ⎯ ⎯ ⎯ R/W R/W R/W R/W R/W
bit 9 bit 8 bit 7
MOD2 MOD1 MOD0
0
0
0
0
1
1
0
0
1
1
×
×
0
1
0
1
0
1
Operation mode select bits (internal clock mode)
(CSL1, 0 = "00B", "01B", "10B")
Function of input pin
Trigger diasble
Trigger input
Gate input
Valid edge, level
⎯
Rising edge
Falling edge
Both edges
Low level
High level
bit 9 bit 8 bit 7
MOD2 MOD1 MOD0
×
×
×
×
0
0
1
1
0
1
0
1
Operation mode select bits (event count mode)
(CSL1, 0="11B")
Function of input pin
Valid edge
⎯
⎯
Rising edge
Trigger input
Falling edge
Both edges
bit 11 bit 10
CSL1 CSL0
R/W :
×
:
⎯
:
:
CM44-10114-7E
Read/Write
Undefined
Unused
Reset value
Count clock select bits
Count clock
Count clock cycle
2 1T
23T
Internal clock mode
0
0
0
1
1
0
Event count mode
1
1
T: Machine cycle
FUJITSU SEMICONDUCTOR LIMITED
25T
External event clock
293
CHAPTER 8 16-BIT RELOAD TIMER
8.3 Configuration of 16-bit Reload Timer
MB90495G Series
Table 8.3-2 Functions of Timer Control Status Registers (High) (TMCSR0:H, TMCSR1:H)
Bit Name
bit 7 to bit 9
bit 10
bit 11
bit 12 to bit 15
294
Function
MOD2, MOD1, MOD0:
Operation mode select
bits
These bits set the operation conditions of the 16-bit reload timer.
[Internal clock mode]
The MOD2 bit is used to select the function of the input pin.
When MOD2 bit set to 0:
The input pin functions as a trigger input.
The MOD1 and MOD0 bits are used to select the edge to be detected.
When the edge is detected, the value set in the 16-bit reload register
(TMRLR) is reloaded in the 16-bit timer register (TMR), starting the count
operation of the TMR.
When MOD2 set to 1:
The input pin functions as a gate input.
The MOD1 bit is not used. The MOD0 bit is used to select the signal level
(High or Low) to be detected. The count operation of the 16-bit timer
register (TMR) is performed only when the signal level is input.
[Event count mode]
The MOD2 bit is not used. An external event clock is input from the input
pin. The MOD1 and MOD0 bits are used to select the edge to be detected.
CSL1, CSL0:
Count clock select bits
These bits select the count clock of the 16-bit reload timer.
When set to anything other than "11B":
The edge of the external event clock is counted (event count mode)
When set to "11B":
The edge of the external event clock is counted (event count mode)
Unused bits
Read: The value is undefined.
Write: No effect
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 8 16-BIT RELOAD TIMER
8.3 Configuration of 16-bit Reload Timer
MB90495G Series
8.3.2
Timer Control Status Registers (Low) (TMCSR0:L,
TMCSR1:L)
The timer control status registers (Low) (TMCSR0:L, TMCSR1:L) enables or disables the
timer operation, checks the generation of a software trigger or an underflow, enables or
disables an underflow interrupt, selects the reload mode, and sets the output of the TOT
pin.
■ Timer Control Status Registers (Low) (TMCSR0:L, TMCSR1:L)
Figure 8.3-4 Timer Control Status Registers (Low) (TMCSR0:L, TMCSR1:L)
7
6
5
4
3
2
1
0
Reset value
*
00000000B
R/W R/W R/W R/W R/W R/W R/W
bit 0
TRG
0
1
No effect
After reloading, starts counting
bit 1
CNTE
0
1
Timer operation disable
Timer operation enable (start trigger wait)
Software trigger bit
Timer operation enable bit
bit 2
UF
0
1
Underflow generaiton flag bit
Read
Write
No underflow
Underflow
Clears UF bit
No effect
bit 3
INTE
0
1
Underflow interrupt disable
Underflow interrupt enable
bit 4
RELD
0
1
One-shot mode
Reload mode
Underflow interrupt enable bit
Reload select bit
bit 5
OUTL
TOT pin output level select bit
One-shot mode
Reload mode
(RELD=0)
(RELD=1)
0
High rectangular wave output during counting
Low toggle output at starting reload timer
1
Low rectangular wave output during counting
High toggle output at starting reload timer
bit 6
TOT pin output enable bit
OUTE
0
R/W : Read/Write
1
: Reset value
section
8.3.1
:
For
MOD0
(bit
7),
see
*
CM44-10114-7E
Pin function
Register and pin corresponding to each channel
TMCSR0
TMCSR1
General-purpose I/O port General-purpose I/O port General-purpose I/O port
TOT output
TOT0
FUJITSU SEMICONDUCTOR LIMITED
TOT1
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CHAPTER 8 16-BIT RELOAD TIMER
8.3 Configuration of 16-bit Reload Timer
MB90495G Series
Table 8.3-3 Timer Control Status Registers (Low) (TMCSR0:L, TMCSR1:L)
Bit Name
296
Function
bit 0
TRG:
Software trigger bit
This bit starts the 16-bit reload timer by software.
The software trigger function works only when the timer operation is enabled
(CNTE = 1).
When set to 0: Disabled. The state remains unchanged.
When set to 1: Reloads value set in 16-bit reload register (TMRLR) to 16-bit
timer register (TMR), starting TMR count operation
Read: 0 is always read.
bit 1
CNTE:
Timer operation enable
bit
This bit enables or disables the operation of the 16-bit reload timer.
When set to1: 16-bit reload timer enters start trigger wait state.
When set to 0: Stops count operation
bit 2
UF:
Underflow generation
flag bit
This bit indicates that the TMR underflows.
When set to 0: Clears this bit
When set to 1: No effect
Read by read modify write instructions: 1 is always read.
bit 3
INTE:
Underflow interrupt
enable bit
This bit enables or disables an under flow interrupt.
When an underflow occurs (TMCSR:UF = 1) with an underflow interrupt
enabled (TMCSR:INTE = 1), an interrupt request is generated.
bit 4
RELD:
Reload select bit
This bit sets the reload operation at underflow.
When set to 1: At underflow, reloads value set in TMRLR to TMR, continuing
count operation (reload mode)
When set to 0: At underflow, stops count operation (one-shot mode)
bit 5
OUTL:
TOT Pin output level
select bit
This bit sets the output level of the output pin of the 16-bit reload timer.
<One-shot mode (RELD = 0)>
When set to 0: Outputs High-level rectangular wave during TMR count
operation
When set to 1: Outputs Low-level rectangular wave during TMR count
operation
<Reload mode (RELD = 1)>
When set to 0: Outputs Low-level toggle wave when 16-bit reload timer started
When set to 1: Outputs High-level toggle wave when 16-bit reload timer started
bit 6
OUTE:
TOT Output enable bit
This bit sets the function of the TOT pin of the 16-bit reload timer.
When set to 0: Functions as general-purpose I/O port
When set to 1: Functions TOT as pin of 16-bit reload timer
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 8 16-BIT RELOAD TIMER
8.3 Configuration of 16-bit Reload Timer
MB90495G Series
8.3.3
16-bit Timer Registers (TMR0, TMR1)
The 16-bit timer registers (TMR0, TMR1) are 16-bit down counters. At read, the value
being counted is read.
■ 16-bit Timer Registers (TMR0, TMR1)
Figure 8.3-5 16-bit Timer Registers (TMR0, TMR1)
15
TMR0
TMR1
14
D15 D14
R
TMR0
TMR1
R : Read only
X : Undefined
13
12
D13
D12 D11 D10
R
R
11
R
10
R
9
8
Reset value
D9
D8
XXXXXXXX B
R
R
R
7
6
5
4
3
2
1
0
Reset value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXX B
R
R
R
R
R
R
R
R
When the timer operation is enabled (TMCSR:CNTE = 1) and the start trigger is input, the value set in the
16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR), starting the TMR count
operation.
When the timer operation is disabled (TMCSR:CNTE = 0), the TMR value is retained.
When the TMR value is counted down from "0000H" to "FFFFH" during the TMR count operation, an
underflow occurs.
[Reload mode]
When the TMR underflows, the value set in the TMRLR is reloaded to the TMR, starting the TMR count
operation.
[One-shot mode]
When the TMR underflows, the TMR count operation is stopped, entering the start trigger input wait state.
The TMR value is retained to "FFFFH".
Notes:
CM44-10114-7E
• The TMR can be read during the TMR count operation. However, always use the word instruction
(MOVW).
• The TMR and the TMRLR are assigned to the same address. At write, the set value can be written to
the TMRLR without affecting the TMR. At read, the TMR value being counted can be read.
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CHAPTER 8 16-BIT RELOAD TIMER
8.3 Configuration of 16-bit Reload Timer
8.3.4
MB90495G Series
16-bit Reload Registers (TMRLR0, TMRLR1)
The 16-bit reload registers (TMRLR0, TMRLR1) set the value to be reloaded to the 16-bit
timer register (TMR). When the start trigger is input, the value set in the 16-bit reload
registers (TMRLR0, TMRLR1) is reloaded to the TMR, starting the TMR count operation.
■ 16-bit Reload Registers (TMRLR0, TMRLR1)
Figure 8.3-6 16-bit Reload Registers (TMRLR0, TMRLR1)
15
TMRLR0
TMRLR1
14
D15 D14
W
TMRLR0
TMRLR1
W : Write only
X : Undefined
13
12
D13
D12 D11 D10
W
W
11
W
10
W
W
9
8
Reset value
D9
D8
XXXXXXXX B
W
W
7
6
5
4
3
2
1
0
Reset value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXX B
W
W
W
W
W
W
W
W
Set the 16-bit reload registers (TMRLR0, TMRLR1) after disabling the timer operation (TMCSR:CNTE =
0). After completing setting of the 16-bit reload registers (TMRLR0, TMRLR1), enable the timer operation
(TMCSR:CNTE = 1).
When the start trigger is input, the value set in the TMRLR is reloaded to the TMR, starting the TMR count
operation.
Notes:
298
• Perform a write to the TMRLR after disabling the operation of the 16-bit reload timer (TMCSR:CNTE
= 0). Always use the word instruction (MOVW).
• The TMRLR and the TMR are assigned to the same address. At write, the set value can be written to
the TMRLR without affecting the TMR. At read, the TMR value being counted is read.
• Instructions, such as the INC/DEC instruction, which provide the read modify write (RMW) operation
cannot be used.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 8 16-BIT RELOAD TIMER
8.4 Interrupts of 16-bit Reload Timer
MB90495G Series
8.4
Interrupts of 16-bit Reload Timer
The 16-bit reload timer generates an interrupt request when the 16-bit timer register
(TMR) underflows.
■ Interrupts of 16-bit Reload Timer
When the value of the TMR is decremented from "0000H" to "FFFFH" during the TMR count operation, an
underflow occurs. When an underflow occurs, the underflow generation flag bit in the timer control status
register (TMCSR:UF) is set to l. When an underflow interrupt is enabled (TMCSR:INTE = 1), an interrupt
request is generated. If setting of UF bit to "1" and writing "0" occur simultaneously, the latter takes
precidence, and "0" is written.
Table 8.4-1 Interrupt Control Bits and Interrupt Factors of 16-bit Reload Timer
16-bit Reload Timer 0
16-bit Reload Timer 1
Interrupt request flag bit
TMCSR0:UF
TMCSR1:UF
Interrupt request enable bit
TMCSR0:INTE
TMCSR1:INTE
Interrupt factor
Underflow in TMR0
Underflow in TMR1
■ Correspondence between 16-bit Reload Timer Interrupt and EI2OS
For details of the interrupt number, interrupt control register, and interrupt vector address, see "3.5
Interrupt".
■ EI2OS Function of 16-bit Reload Timer
The 16-bit reload timer corresponds to the EI2OS function. An underflow in the TMR starts the EI2OS.
The EI2OS is available only when other resources sharing the interrupt control register (ICR) do not use
interrupts. When using the EI2OS in the 16-bit reload timers 0 and 1, it is necessary to disable generation of
interrupt requests by resources sharing the interrupt control register (ICR) with the 16-bit reload timers 0
and 1.
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CHAPTER 8 16-BIT RELOAD TIMER
8.5 Explanation of Operation of 16-bit Reload Timer
8.5
MB90495G Series
Explanation of Operation of 16-bit Reload Timer
This section explains the setting of the 16-bit reload timer and the operation state of the
counter.
■ Setting of 16-bit Reload Timer
● Setting of internal clock mode
Counting the internal clock requires the setting shown in Figure 8.5-1.
Figure 8.5-1 Setting of Internal Clock Mode
TMCSR
bit 15 14
13
12
⎯
⎯
⎯
⎯
11
10
9
8
7
6
5
4
3
2
1
bit 0
CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG
1
Except "11B"
Sets a reload value to 16-bit timer register
TMRLR
: Used bit
1 : Set 1
● Setting of event count mode
Inputting an external event to operate the 16-bit reload timer requires the setting shown in Figure 8.5-2.
Figure 8.5-2 Setting of Event Count Mode
TMCSR
bit 15 14
13
12
11
⎯
⎯
⎯
CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG
⎯
1
TMRLR
10
9
8
7
6
5
1
4
3
2
1
bit 0
1
Sets a reload value to 16-bit timer register
Set the bit of DDR (port direction register) corresponding to the pin to be used as TIN pin to "0".
: Used bit
1 : Set 1
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CM44-10114-7E
CHAPTER 8 16-BIT RELOAD TIMER
8.5 Explanation of Operation of 16-bit Reload Timer
MB90495G Series
■ Operating State of 16-bit Timer Register
The operating state of the 16-bit timer register is determined by the timer operation enable bit in the timer
control status register (TMCSR:CNTE) and the WAIT signal. The operating states include the stop state,
start trigger input wait state (WAIT state), and RUN state.
Figure 8.5-3 shows the state transition diagram for the 16-bit timer registers.
Figure 8.5-3 State Transition Diagram
STOP state CNTE = 0, WAIT = 1
TIN pin: input disable
TOUT pin: general-purpose I/O port
Reset
16-bit timer register: retain the value at stop
(the value immediately after resetting is undefined)
CNTE = 0
CNTE = 0
CNTE = 1
TRG = 0
WAIT state CNTE = 1, WAIT = 1
TIN pin: only trigger input is valid
TOUT pin: outputs value of 16-bit reload
register
RUN state
External trigger from TIN
:
:
WAIT :
TRG :
CNTE :
UF
:
RELD :
CM44-10114-7E
CNTE = 1, WAIT = 0
TIN pin: function as input pin of
16-bit reload timer
UF = 1 &
RELD = 0
16-bit timer register: retains the value at stop (one-shot mode)
(the value is undefined until loading immediately after resetting)
TRG = 1
(software trigger)
CNTE = 1
TRG = 1
TOUT pin: function as output pin of
16-bit reload timer
UF = 1 & 16-bit timer register : operation
RELD = 1
(reload mode)
TRG = 1
LOAD
CNTE = 1, WAIT = 0
Loads 16-bit reload register value to
16-bit timer register
(software trigger)
Load ended
State transition by hardware
State transition by register access
WAIT signal (internal signal)
Software trigger bit (TMCSR)
Timer operation enable bit (TMCSR)
Underflow generation flag bit (TMCSR)
Reload select bit (TMCSR)
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CHAPTER 8 16-BIT RELOAD TIMER
8.5 Explanation of Operation of 16-bit Reload Timer
8.5.1
MB90495G Series
Operation in Internal Clock Mode
In the internal clock mode, three operation modes can be selected by setting the
operation mode select bits in the timer control status register (TMCSR:MOD2 to MOD0).
When the operation mode and reload mode are set, a rectangular wave or a toggle wave
is output from the TOT pin.
■ Setting of Internal Clock Mode
• By setting the count clock select bits (CSL1, CSL0) in the timer control status register to "00B", "01B",
"10B", the 16-bit reload timer (TMRLR) is set to the internal clock mode.
• In the internal clock mode, the 16-bit timer register (TMR) decrements in synchronization with the
internal clock.
• In the internal clock mode, three count clock cycles can be selected by setting the count clock select bits
in the timer control status register (TMCSR:CSL1, CSL0).
[Setting a reload value to TMR]
After the 16-bit reload timer is started, the value set in the TMRLR is reloaded to the TMR.
1. Disables the timer operation (TMCSR:CNTE = 0).
2. Sets a reload value to the TMR in the TMRLR.
3. Enables the timer operation (TMCSR:CNTE = 1).
Note:
302
It takes 1 machine cycle (time) to load the value set in the TMRLR to the TMR after the start trigger is
input.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 8 16-BIT RELOAD TIMER
8.5 Explanation of Operation of 16-bit Reload Timer
MB90495G Series
■ Operation as 16-bit Timer Register Underflows
When the value of the 16-bit timer register (TMR) is decremented from "0000H" to "FFFFH" during the
TMR count operation, an underflow occurs.
• When an underflow occurs, the underflow generation flag bit in the timer control status register
(TMCSR:UF) is set to 1.
• When the underflow interrupt enable bit in the timer control status register (TMCSR:INTE) is set to 1,
an underflow interrupt is generated.
• The reload operation when an underflow occurs is set by the reload select bit in the timer control status
register (TMCSR:RELD).
[One-shot mode (TMCSR:RELD = 0)]
When an underflow occurs, the count operation of the TMR is stopped, entering the start trigger input wait
state. When the next start trigger is input, the TMR count operation is restarted.
In the one-shot mode, a rectangular wave is output from the TOT pin during the TMR count operation. The
pin output level select bit in the timer control status register (TMCSR:OUTL) can be set to select the level
(High or Low) of a rectangular wave.
[Reload mode (TMCSR:RELD = 1)]
When an underflow occurs, the value set in the 16-bit reload timer register (TMRLR) is reloaded to the
TMR, continuing the TMR count operation.
In the reload mode, a toggle wave inverting the output level of the TOT pin is output each time an
underflow occurs during the TMR count operation. The pin output level select bit in the timer control status
register (TMCSR:OUTL) can be set to select the level (High or Low) of a toggle wave as the 16-bit reload
timer is started.
■ Operation in Internal Clock Mode
In the internal clock mode, the operation mode select bits in the timer control status register
(TMCSR:MOD2 to MOD0) can be used to select the operation mode. Disable the timer operation by
setting the timer operation enable bit in the timer control status register (TMCSR:CNTE).
[Software trigger mode (MOD2 to MOD0 ="000B")]
If the software trigger mode is set, start the 16-bit reload timer by setting the software trigger bit in the
timer control status register (TMCSR:TRG) to 1. When the 16-bit reload timer is started, the value set in
the TMRLR is reloaded to the TMR, starting the TMR count operation.
Note:
CM44-10114-7E
When both the timer operation enable bit in the timer control status register (TMCSR:CNTE) and the
software trigger bit in the timer control status register (TMCSR:TRG) are set to 1, the 16-bit reload timer
and the count operation of the TMR are started simultaneously.
However, timer start-up during gate input operation can only be enabled by software triggering.
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CHAPTER 8 16-BIT RELOAD TIMER
8.5 Explanation of Operation of 16-bit Reload Timer
MB90495G Series
Figure 8.5-4 Count Operation in Software Trigger Mode (One-shot Mode)
Count clock
Reload data
Counter
-1
0000H FFFFH
Reload data
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
T*
TOT pin
Start trigger input wait
T : Machine cycle
* : It takes 1 machine cycle (time) to load data of reload register from trigger input.
Figure 8.5-5 Count Operation in Software Trigger Mode (Reload Mode)
Count clock
Reload data
Counter
-1
0000H Reload data
-1
0000H Reload data
-1
0000H Reload data
-1
Data load signal
UF bit
CNTE bit
TRG bit
T*
TOT pin
T : Machine cycle
* : It takes 1 machine cycle (time) to load data of reload register from trigger input.
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CM44-10114-7E
CHAPTER 8 16-BIT RELOAD TIMER
8.5 Explanation of Operation of 16-bit Reload Timer
MB90495G Series
[External trigger mode (MOD2 to MOD0 =" 001B", "010B", "011B")]
When the external trigger mode is set, the 16-bit reload timer is started by inputting the external valid edge
to the TIN pin. When the 16-bit reload timer is started, the value set in the 16-bit reload register (TMRLR)
is reloaded to the 16-bit timer register (TMR), starting the TMR count operation.
• By setting the operation mode select bits in the timer control status register (TMCSR:MOD2 to MOD0),
the detected edge can be selected from the rising edge, falling edge, and both edges.
Note:
For trigger pulse width to be input to the TIN pin, as well as the pulse width of the gate input, refer to the
specification values of data sheet.
Figure 8.5-6 Count Operation in External Trigger Mode (One-shot Mode)
Count clock
Counter
Reload data
-1
0000H FFFFH
Reload data
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TIN pin
2T to 2.5T*
TOT pin
Start trigger input wait
T : Machine cycle
* : It takes 2 to 2.5 machine cycles (time) to load data of reload register from external trigger input.
Figure 8.5-7 Count Operation in External Trigger Mode (Reload Mode)
Count clock
Counter
Reload data
-1
0000H Reload data
-1
0000H Reload data
-1
0000H Reload data
-1
Data load signal
UF bit
CNTE bit
TIN pin
TOT pin
2T to 2.5T*
T : Machine cycle
* : It takes 2 to 2.5 machine cycles (time) to load data of reload register from external trigger input.
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CHAPTER 8 16-BIT RELOAD TIMER
8.5 Explanation of Operation of 16-bit Reload Timer
MB90495G Series
[External gate input mode (MOD2 to MOD0 = "1x0B", "1x1B")]
When the external gate input mode is set, start the 16-bit reload timer by setting the software trigger bit in
the timer control status register (TMCSR:TRG) to 1. When the 16-bit reload timer is started, the value set
in the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR).
• After the 16-bit reload timer is started, the count operation of the TMR is performed while the set gate
input level is input to the TIN pin.
• The gate input level (High or Low) can be selected by setting the operation mode select bits in the timer
control status register (TMCSR:MOD2 to MOD0).
Figure 8.5-8 Count Operation in External Gate Input Mode (One-shot Mode)
Count clock
Reload data
Counter
-1
0000H
-1
FFFFH
Reload data
-1
-1
Data load signal
UF bit
CNTE bit
TRG bit
T*
T*
TIN pin
TOT pin
Start trigger input wait
T : Machine cycle
* : It takes 1 machine cycle (time) to load data of reload register from trigger input.
Figure 8.5-9 Count Operation in External Gate Input Mode (Reload Mode)
Count clock
Counter
Reload data
-1
-1
-1
0000H Reload data
-1
-1
Data load signal
UF bit
CNTE bit
TRG bit
T*
TIN pin
TOT pin
T : Machine cycle
* : It takes 1 machine cycle (time) to load data of reload register from trigger input.
306
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CM44-10114-7E
CHAPTER 8 16-BIT RELOAD TIMER
8.5 Explanation of Operation of 16-bit Reload Timer
MB90495G Series
8.5.2
Operation in Event Count Mode
In the event count mode, after the 16-bit reload timer is started, the edge of the signal
input to the TIN pin is detected to perform the count operation of the 16-bit timer
register (TMR). When the operation mode and the reload mode are set, a rectangular
wave or a toggle wave is output from the TOT pin.
■ Setting of Event Count Mode
• The 16-bit reload timer (TMRLR) is placed in the event count mode by setting the count clock select
bits in the timer control status register (TMCSR:CSL1, CSL0) to "11B".
• In the event count mode, the TMR decrements in synchronization with the edge detection of the external
event clock input to the TIN pin.
[Setting initial value of counter]
After the 16-bit timer is started, the value set in the TMRLR is reloaded to the TMR.
1. Disables the operation of the 16-bit reload timer (TMCSR:CNTE = 0).
2. Sets a reload value to the TMR in the TMRLR.
3. Enables the operation of the 16-bit reload timer (TMCSR:CNTE = 1).
Note:
CM44-10114-7E
It takes 1 machine cycle (time) to load the value set in the TMRLR to the TMR after the start trigger is
input.
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CHAPTER 8 16-BIT RELOAD TIMER
8.5 Explanation of Operation of 16-bit Reload Timer
MB90495G Series
■ Operation as 16-bit Timer Register Underflows
When the value of the 16-bit timer register (TMR) is decremented from "0000H" to "FFFFH" during the
TMR count operation, an underflow occurs.
• When an underflow occurs, the underflow generation flag bit in the timer control status register
(TMCSR:UF) is set to 1.
• When the underflow interrupt enable bit in the timer control status register (TMCSR:INTE) is set to 1,
an underflow interrupt is generated.
• The reload operation when an underflow occurs is set by the reload select bit in the timer control status
register (TMCSR:RELD).
[One-shot mode (TMCSR:RELD = 0)]
When an underflow occurs, the TMR count operation is stopped, entering the start trigger input wait state.
When the next start trigger is input, the TMR count operation is restarted.
In the one-shot mode, a rectangular wave is output from the TOT pin during the TMR count operation. The
pin output level select bit in the timer control status register (TMCSR:OUTL) can be set to select the level
(High or Low) of the rectangular wave.
[Reload mode (TMCSR:RELD = 1)]
When an underflow occurs, the value set in the TMRLR is reloaded to the TMR, continuing the TMR count
operation.
In the reload mode, a toggle wave inverting the output level of the TOT pin is output each time an
underflow occurs during the TMR count operation. The pin output level select bit in the timer control status
register (TMCSR:OUTL) can be set to select the level (High or Low) of the toggle wave when the TMRLR
is started.
308
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CM44-10114-7E
CHAPTER 8 16-BIT RELOAD TIMER
8.5 Explanation of Operation of 16-bit Reload Timer
MB90495G Series
■ Operation in Event Count Mode
The operation of the 16-bit reload timer is enabled by setting the timer operation enable bit in the timer
control status register (TMCSR:CNTE) to 1. When the software trigger bit in the timer control status
register (TMCSR:TRG) is set to 1, the 16-bit reload timer is started. When the 16-bit reload timer is started,
the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR), starting
the TMR count operation. After the 16-bit reload timer is started, the edge of the external event clock input
to the TIN pin is detected to perform the TMR count operation.
• By setting the operation mode select bits in the timer control status register (TMCSR:MOD2 to MOD0),
the detected edge can be selected from the rising edge, falling edge, and both edges.
Note:
For "H" and "L" clock widths to be input to the TIN pin, refer to the specification values of data sheet.
Figure 8.5-10 Count Operation in Event Count Mode (One-shot Mode)
TIN pin
Reload data
Counter
-1
0000H FFFFH
Reload data
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
T*
TOT pin
Start trigger input wait
T : Machine cycle
* : It takes 1 machine cycle (time) to load data of reload register from trigger input.
Figure 8.5-11 Count Operation in Event Count Mode (Reload Mode)
TIN pin
Reload data
Counter
-1
0000H Reload data
-1
0000H Reload data
-1
0000H Reload data
-1
Data load signal
UF bit
CNTE bit
TRG bit
T*
TOT pin
T : Machine cycle
* : It takes 1 machine cycle (time) to load data of reload register from trigger input.
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CHAPTER 8 16-BIT RELOAD TIMER
8.6 Precautions when Using 16-bit Reload Timer
8.6
MB90495G Series
Precautions when Using 16-bit Reload Timer
This section explains the precautions when using the 16-bit reload timer.
■ Precautions when Using 16-bit Reload Timer
● Precautions when setting by program
• Set the 16-bit reload register (TMRLR) after disabling the timer operation (TMCSR:CNTE = 0)
• The 16-bit timer register (TMR) can be read during the TMR count operation. However, always use the
word instruction (MOVW).
• Change the CSL1 and CSL0 bits in the TMCSR after disabling the timer operation (TMCSR:CNTE = 0)
● Precautions on interrupt
• When the UF bit in the TMCSR is set to 1 and the underflow interrupt output is enabled (TMCSR:INTE
= 1), it is impossible to return from interrupt processing. Always clear the UF bit. However, when the
EI2OS is used, the UF bit is cleared automatically.
• When using the EI2OS in the 16-bit reload timer, it is necessary to disable generation of interrupt
requests by resources that share the interrupt control register (ICR) with the 16-bit reload timer.
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CHAPTER 8 16-BIT RELOAD TIMER
8.7 Program Example of 16-bit Reload Timer
MB90495G Series
8.7
Program Example of 16-bit Reload Timer
This section gives a program example of the 16-bit reload timer operated in the internal
clock mode and the event count mode are given below:
■ Program Example in Internal Clock Mode
● Processing specification
• The 25-ms interval timer interrupt is generated by the 16-bit reload timer 0.
• The repeated interrupts are generated in the reload mode.
• The timer is started using the software trigger instead of the external trigger input.
• EI2OS is not used.
• The machine clock is 16 MHz; the count clock is 2 μs.
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CHAPTER 8 16-BIT RELOAD TIMER
8.7 Program Example of 16-bit Reload Timer
MB90495G Series
● Coding example
ICR03
EQU 0000B3H
; Interrupt control register for 16-bit reload timer
TMCSR0 EQU 000066H
; Timer control status register
TMR0
EQU 003900H
; 16-bit timer register
TMRLR0 EQU 003900H
; 16-bit reload register
UF0
EQU TMCSR0:2
; Interrupt request flag bit
CNTE0
EQU TMCSR0:1
; Counter operation enable bit
TRG0
EQU TMCSR0:0
; Software trigger bit
;-----Main program--------------------------------------------------------------CODE
CSEG
;
:
; Stack pointer (SP), already initialized
AND CCR,#0BFH
; Interrupts disabled
MOV I:ICR03,#00H
; Interrupt level 0 (highest)
CLRB I:CNTE0
; Counter suspended
MOVW I:TMRLR0,#30D3H
; Data set for 25-ms interval timer interrupt
MOVW I:TMCSR0,#0000100000011011B
; Operation of interval timer, clock = 2 ms.
; External trigger disabled, external output disabled
; Reload mode selected, interrupt enabled
; Interrupt flag cleared, count started
MOV ILM,#07H
; ILM in PS set to level 7
OR
CCR,#40H
; Interrupts enabled
LOOP:
:
Processing by user
:
BRA LOOP
;-----Interrupt program---------------------------------------------------------WARI:
CLR I:UF0
; Interrupt request flag cleared
:
Processing by user
:
RETI
; Return from interrupt
CODE
ENDS
;-----Vector
VECT
CSEG
ORG
DSL
ORG
DSL
DB
VECT
ENDS
END
312
setting------------------------------------------------------------ABS=0FFH
00FFB8H
; Vector set to interrupt #17 (11H)
WARI
00FFDCH
; Reset vector set
START
00H
; Set to single-chip mode
START
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CHAPTER 8 16-BIT RELOAD TIMER
8.7 Program Example of 16-bit Reload Timer
MB90495G Series
■ Program Example in Event Counter Mode
● Processing specification
• An interrupt is generated when rising edges of the pulse input to the external event input pin are counted
10000 times by the 16-bit reload timer/counter.
• Operation is performed in the one-shot mode.
• The rising edge is selected for the external trigger input.
• EI2OS is not used.
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CHAPTER 8 16-BIT RELOAD TIMER
8.7 Program Example of 16-bit Reload Timer
MB90495G Series
● Coding example
ICR03
EQU 0000B3H
; Interrupt control register for 16-bit reload timer
TMCSR0 EQU 000066H
; Timer control status register
TMR0
EQU 003900H
; 16-bit timer register
TMRLR0 EQU 003900H
; 16-bit reload register
DDR2
EQU 000012H
; Port data register
UF0
EQU TMCSR0:2
; Interrupt request flag bit
CNTE0
EQU TMCSR0:1
; Counter operation enable bit
TRG0
EQU TMCSR0:0
; Software trigger bit
;-----Main program--------------------------------------------------------------CODE
CSEG
;
:
; Stack pointer (SP), already initialized
AND CCR,#0BFH
; Interrupts disabled
MOV I:ICR03,#00H
; Interrupt level 0 (highest)
MOV I:DDR2,00H
; Sets P20/TIN0 pin to input
CLRB I:CNTE0
; Counter suspended
MOVW I:TMRLR0,#2710H; Reload value set to 10000 times
MOVW I:TMCSR0,#0000110000001011B
; Counter operation, external trigger,
; rising edge, and external output disabled
; One-shot mode selected, interrupt enabled
; Interrupt flag cleared, count started
MOV
ILM,#07H
; ILM in PS set to level 7
OR
CCR,#40H
; Interrupts enabled
LOOP:
:
Processing by user
:
BRA
LOOP
;-----Interrupt program---------------------------------------------------------WARI:
CLR I:UF0
; Interrupt request flag cleared
:
Processing by user
:
RETI
; Return from interrupt
CODE
ENDS
;-----Vector
VECT
CSEG
ORG
DSL
ORG
DSL
DB
VECT
ENDS
END
314
setting------------------------------------------------------------ABS=0FFH
00FFB8H
; Vector set to interrupt #17 (11H)
WARI
00FFDCH
; Reset vector set
START
00H
; Set to single-chip mode
START
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 9
WATCH TIMER
This section describes the functions and operations of
the watch timer.
9.1 Overview of Watch Timer
9.2 Block Diagram of Watch Timer
9.3 Configuration of Watch Timer
9.4 Watch Timer Interrupt
9.5 Explanation of Operation of Watch Timer
9.6 Program Example of Watch Timer
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CHAPTER 9 WATCH TIMER
9.1 Overview of Watch Timer
9.1
MB90495G Series
Overview of Watch Timer
The watch timer is a 15-bit free-run counter that increments in synchronization with the
subclock.
• Eight interval times can be selected and an interrupt request can be generated for
each interval time.
• An operation clock can be supplied to the oscillation stabilization wait time timer of
the subclock and the watchdog timer.
• The subclock is always used as a count clock regardless of the settings of the clock
select register (CKSCR).
■ Interval Timer Function
• When the watch timer reaches the interval time set by the interval time select bits (WTC:WTC2 to
WTC0), the bit corresponding to the interval time of the watch timer counter overflows carries and the
overflow flag bit is set (WTC:WTOF = 1).
• When the overflow flag bit is set (WTC:WTOF = 1) with interrupt enabled when an overflow occurs
(WTC:WTIE = 1), an interrupt request is generated.
• The interval time of the watch timer can be selected from eight types shown in Table 9.1-1.
Table 9.1-1 Interval Times of Watch Timer
Subclock Cycle
Interval Time
28/SCLK (31.25 ms)
29/SCLK (62.5 ms)
210/SCLK (125 ms)
SCLK (122 μs)
211/SCLK (250 ms)
212/SCLK (500 ms)
213/SCLK (1.0 s)
214/SCLK (2.0 s)
215/SCLK (4.0 s)
SCLK: Subclock
The parenthesized values are provided when the subclock operates at 8.192 kHz.
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CHAPTER 9 WATCH TIMER
9.1 Overview of Watch Timer
MB90495G Series
■ Cycle of Clock Supply
The watch timer supplies an operation clock to the oscillation stabilization wait time timer of the subclock
and the watchdog timer. Table 9.1-2 shows the cycles of clocks supplied from the watch timer.
Table 9.1-2 Cycle of Clock Supply from Watch Timer
Where to Supply Clock
Timer for oscillation stabilization wait time
of subclock
Clock Cycle
214/SCLK (2.000 s)
210/SCLK (125 ms)
213/SCLK (1.000 s)
Watchdog timer
214/SCLK (2.000 s)
215/SCLK (4.000 s)
SCLK: Subclock frequency
The parenthesized values are provided when the subclock operates at 8.192 kHz.
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CHAPTER 9 WATCH TIMER
9.2 Block Diagram of Watch Timer
9.2
MB90495G Series
Block Diagram of Watch Timer
The watch timer consists of the following blocks:
• Watch timer counter
• Counter clear circuit
• Time interval selector
• Watch timer control register (WTC)
■ Block Diagram of Watch Timer
Figure 9.2-1 Block Diagram of Watch Timer
To watchdog
timer
Watch timer counter
SCLK
× 21 × 22 × 23 × 24 × 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215
OF OF OF
OF
Power on reset
Transits to hardware standby
OF
OF
Counter
clear circuit
Transits to stop mode
OF
OF
To stabilization wait time
subclock oscillation
Interval timer
selector
Watch timer interrupt
OF: Overflow
SCLK: Subclock
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
Watch timer control register (WTC)
The actual interrupt request number of the watch timer is as follows:
Interrupt request number: #28 (1CH)
● Watch timer counter
The watch timer counter is a 15-bit up counter that uses the subclock (SCLK) as a count clock.
● Counter clear circuit
The counter-clear circuit clears the watch timer counter.
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CHAPTER 9 WATCH TIMER
9.2 Block Diagram of Watch Timer
MB90495G Series
● Interval timer selector
The interval timer selector sets the overflow flag bit when the watch timer counter reaches the interval time
set in the watch timer control register (WTC).
● Watch timer control register (WTC)
The watch timer control register (WTC) selects the interval time, clears the watch timer counter, enables or
disables an interrupt, checks the overflow state, and clears the overflow flag bit.
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CHAPTER 9 WATCH TIMER
9.3 Configuration of Watch Timer
9.3
MB90495G Series
Configuration of Watch Timer
This section explains the registers and interrupt factors of the watch timer.
■ List of Registers and Reset Values of Watch Timer
Figure 9.3-1 List of Registers and Reset Values of Watch Timer
bit
Watch timer control register (WTC)
×:
7
6
5
4
3
2
1
0
1
×
0
0
1
0
0
0
Undefined
■ Generation of Interrupt Request from Watch Timer
• When the interval time set by the interval time select bits (WTC:WTC2 to WTC0) is reached, the
overflow flag bit (WTC:WTOF) is set to 1.
• When the overflow flag bit is set (WTC:WTOF = 1) with interrupt enabled when the watch timer
counter overflows (carries) (WTC:WTIE = 1), an interrupt request is generated.
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CHAPTER 9 WATCH TIMER
9.3 Configuration of Watch Timer
MB90495G Series
9.3.1
Watch Timer Control Register (WTC)
This section explains the functions of the watch timer control register (WTC).
■ Watch Timer Control Register (WTC)
Figure 9.3-2 Watch Timer Control Register (WTC)
7
6
R/W
R
5
4
3
2
1
0
Reset value
1X001000B
R/W R/W R/W R/W R/W R/W
bit 2 bit 1 bit 0
WTC2 WTC1 WTC0
Interval time select bits
0
0
0
28/SCLK (31.25ms)
0
0
1
29/SCLK (62.5ms)
0
1
0
210/SCLK (125ms)
0
1
1
211/SCLK (250ms)
1
0
0
212/SCLK (500ms)
1
0
1
213/SCLK (1.0s)
1
1
0
214/SCLK (2.0s)
1
1
1
215/SCLK (4.0s)
bit 3
WTR
0
1
Watch timer clear bit
Read
Write
⎯
Clears watch timer counter
"1" always read
No effect
bit 4
WTOF
Overflow flag bit
Read
Write
0
No overflow of the bit
corresponding to set interval time
Clears WTOF bit
1
Overflow of the bit corresponding
to set interval time
No effect
bit 5
WTIE
0
1
Overflow interrupt enable bit
Interrupt request disable
Interrupt request enable
bit 6
Oscillation stabilization wait time end bit
SCE
Oscillstion stabilization wait state
0
Oscillstion stabilization wait time end
1
bit 7
WDCS
Watchdog clock select bit
(input clock of watchdog timer)
R/W : Read/Write
Main or PLL clock mode
Subclock mode
R
: Read only
Watch timer
Set "0"
0
X
: Undefined
1
Timebase timer
SCLK : Subclock
: Reset value
The parenthesized values are provided when subclock operates at 8.192 kHz.
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CHAPTER 9 WATCH TIMER
9.3 Configuration of Watch Timer
MB90495G Series
Table 9.3-1 Functions of Watch Timer Control Register (WTC)
Bit Name
bit 2 to bit
0
322
Function
WTC2, WTC1, WTC0:
Interval time select bits
These bits set the interval time of the watch timer.
• When the interval time set by the WTC2 to WTC0 bits is reached, the
corresponding bit of the watch timer counter overflows (carries) and the
overflow flag bit is set (WTC:WTOF = 1).
• To set the WTC2 to WTC0 bits, set the WTOF bit to 0.
bit 3
WTR:
Watch timer clear bit
This bit clears the watch timer counter.
When set to 0: Clears watch timer counter to "0000H"
When set to 1: No effect
Read: 1 is always read.
bit 4
WTOF:
Overflow flag bit
This bit is set to 1 when the counter value of the watch timer reaches the value
set by the interval time select bit.
When an overflow occurs (WTOF = 1) with interrupt request enabled (WTIE =
1), an interrupt request is generated.
When set to 0: Clears watch timer counter
When set to 1: No effect
• The overflow flag bit is set to 1 when the bit of the watch timer counter
corresponding to the interval time set by the interval time select bits (WTC2
to WTC0) overflows.
Note:
To clear the WTOF bit, disable interrupts (WTIE = 0) or mask interrupts
using the ILM bit in the processor status (PS).
Do not enable watch timer interrupt (WTC: WTIE = 1) and clear interrupt
flag (WTC: WTOF = 0) at the same time.
bit 5
WTIE:
Overflow interrupt
enable bit
This bit enables or disables generation of an interrupt request when the watch
timer counter overflows (carries).
When set to 0: Interrupt request not generated even at overflow (WTOF = 1)
When set to 1: Interrupt request generated at overflow (WTOF = 1)
bit 6
SCE:
Oscillation stabilization
wait time end bit
This bit indicates that the oscillation stabilization wait time of the subclock ends.
When cleared to 0: Subclock in oscillation stabilization wait state
When set to 1: Subclock oscillation stabilization wait time ends
• The oscillation stabilization wait time of the subclock is fixed at 214/SCLK
(SCLK: subclock frequency).
bit 7
WDCS:
Watchdog clock select
bit
This bit selects the operation clock of the watchdog timer.
<Main clock mode or PLL clock mode>
When set to 0: Selects output of watch timer as operation clock of watchdog
timer.
When set to 1: Selects output of timebase timer as operation clock of watchdog
timer.
<Subclock mode>
Always set this bit to 0 to select the output of the watch timer. If the mode
transits to the sub-clock mode with setting to "1", the watchdog timer stops.
Note:
The watch timer and the timebase timer operate asynchronously. When the
WDCS bit is changed from 0 to 1, the watchdog timer may run fast. The
watchdog timer must be cleared before and after changing the WDCS bit.
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CHAPTER 9 WATCH TIMER
9.4 Watch Timer Interrupt
MB90495G Series
9.4
Watch Timer Interrupt
When the interval time is reached with the watch timer interrupt enabled, the overflow
flag bit is set to 1 and an interrupt request is generated.
■ Watch Timer Interrupt
Table 9.4-1 shows the interrupt control bits and interrupt factors of the watch timer.
Table 9.4-1 Interrupt Control Bits of Watch Timer
Watch Timer
Interrupt factor
Interval time of watch timer counter
Interrupt request flag bit
WTC: WTOF (overflow flag bit)
Interrupt factor enable bit
WTC: WTIE
• When the value set by the interval time select bits (WTC2 to WTC0) in the watch timer control register
(WTC) is reached, the overflow flag bit in the WTC register is set to 1 (WTC:WTOF = 1).
• When the overflow flag bit is set (WTC:WTOF = 1) with the watch timer interrupt enabled
(WTC:WTIE = 1), an interrupt request is generated.
• At interrupt processing, set the WTOF bit to 0 and cancel the interrupt request.
■ Watch Timer Interrupt and EI2OS Function
• The watch timer does not correspond to the EI2OS function.
• For details of the interrupt number, interrupt control register, and interrupt vector address, see Section
"3.5 Interrupt".
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CHAPTER 9 WATCH TIMER
9.5 Explanation of Operation of Watch Timer
9.5
MB90495G Series
Explanation of Operation of Watch Timer
The watch timer operates as an interval timer or an oscillation stabilization wait time
timer of subclock. It also supplies an operation clock to the watchdog timer.
■ Watch Timer Counter
The watch timer counter continues incrementing in synchronization with the subclock (SCLK) while the
subclock (SCLK) is operating.
● Clearing watch timer counter
The watch timer counter is cleared to "0000H" when:
• A power-on reset occurs.
• The mode transits to the stop mode.
• The watch timer clear bit (WTR) in the watch timer control register (WTC) is set to 0.
Note:
When the watch timer counter is cleared, the interrupts of the watchdog timer and interval timer that use
the output of the watch timer counter are affected.
To clear the watch timer by writing zero to the watch timer clear bit (WTR) in the watch timer control
register (WTC), set the overflow interrupt enable bit (WTIE) to "0" and set the watch timer to interrupt
inhibited state. Before permitting an interrupt, clear the interrupt request issued by writing zero to the
overflow flag bit (WTOF) .
■ Interval Timer Function
The watch timer can be used as an interval timer by generating an interrupt at each interval time.
● Settings when using watch timer as interval timer
Operating the watch timer as an interval timer requires the settings shown in Figure 9.5-1.
Figure 9.5-1 Setting of Watch Timer
bit 7
WTC
6
5
4
3
2
1
bit0
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
×
×
: Used bit
× : Unused bit
• When the value set by the interval time select bits (WTC1, WTC0) in the watch timer control register
(WTC) is reached, the overflow flag bit in the WTC register is set to 1 (WTC:WTOF = 1).
• When the overflow flag bit is set (WTC:WTOF = 1) with the overflow interrupt of the watch timer
counter enabled (WTC:WTIE = 1), an interrupt request is generated.
• The overflow flag bit (WTC:WTOF) is set when the interval time is reached at the starting point of the
timing at which the watch timer is finally cleared.
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CHAPTER 9 WATCH TIMER
9.5 Explanation of Operation of Watch Timer
MB90495G Series
● Clearing overflow flag bit (WTC:WTOF)
• When the mode is switched to the stop mode, the watch timer is used as an oscillation stabilization wait
time timer of subclock. The WTOF bit is cleared concurrently with mode switching.
Note:
To clear the overflow interrupt request flag bit (WTC: WTOF), disable a watch timer overflow interrupt
(WTC:WIE=0) or mask interrupt by using the ILM bit in the processor status (PS) at interrupt processing.
Do not enable watch timer interrupt (WTC: WIE = 1) and clear interrupt flag (WTC: WTOF = 0) at the
same time.
■ Setting Operation Clock of Watchdog Timer
The watchdog clock select bit (WDCS) in the watch timer control register (WTC) can be used to set the
clock input source of the watchdog timer.
When using the subclock as the machine clock, always set the WDCS bit to 0 and select the output of the
watch timer. If the mode transits to the sub-clock mode with setting to "1", the watchdog timer stops.
■ Oscillation Stabilization Wait Time Timer of Subclock
When the watch timer returns from the power-on reset and the stop mode, it functions as an oscillation
stabilization wait time timer of subclock.
• The subclock oscillation stabilization wait time is fixed at 215/SCLK (SCLK: subclock frequency).
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CHAPTER 9 WATCH TIMER
9.6 Program Example of Watch Timer
9.6
MB90495G Series
Program Example of Watch Timer
This section gives a program example of the watch timer.
■ Program Example of Watch Timer
● Processing specifications
An interval interrupt at 213/SCLK (SCLK: subclock) is generated repeatedly. The internal time is
approximately 1.0s (when subclock operates at 8.192 kHz).
● Coding example
ICR07
EQU 0000B7H
; Interrupt control register
WTC
EQU 0000AAH
; Watch timer control register
WTOF
EQU WTC:4
; Overflow flag bit
;
;-----Main program--------------------------------------------------------------CODE
CSEG
START:
;
:
; Stack pointer (SP) already initialized
AND CCR,#0BFH
; Interrupt disabled
MOV I:ICR07,#00H
; Interrupt level 0 (highest)
MOV I:WTC, #10100101B ; Interrupt enabled
; Overflow flag bit cleared
; Watch timer counter cleared
; 213/SCLK (approx. 1.0 s)
MOV ILM,#07H
; ILM in PS set to level 7
OR
CCR,#40H
; Interrupt enabled
LOOP:
:
Processing by user
:
BRA
LOOP
;-----Interrupt program---------------------------------------------------------WARI:
CLRB I:WTOF
; Overflow flag bit cleared
:
Processing by user
:
RETI
; Return from interrupt
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG 00FFDCH
; Reset vector set #28 (1CH)
DSL WARI
ORG 00FFDCH
; Reset vector set
DSL START
DB
00H
; Set to single-chip mode
VECT
ENDS
END START
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CHAPTER 10
8-/16-BIT PPG TIMER
This section describes the functions and operations of
the 8-/16-bit PPG timer.
10.1 Overview of 8-/16-bit PPG Timer
10.2 Block Diagram of 8-/16-bit PPG Timer
10.3 Configuration of 8-/16-bit PPG Timer
10.4 Interrupts of 8-/16-bit PPG Timer
10.5 Explanation of Operation of 8-/16-bit PPG Timer
10.6 Precautions when Using 8-/16-bit PPG Timer
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CHAPTER 10 8-/16-BIT PPG TIMER
10.1 Overview of 8-/16-bit PPG Timer
10.1
MB90495G Series
Overview of 8-/16-bit PPG Timer
The 8-/16-bit PPG timer is a reload timer module with two channels (PPG0 and PPG1)
that outputs a pulse in any cycle and at any duty ratio. A combination of two channels
provides:
• 8-bit PPG output 2-channel independent operation mode
• 16-bit PPG output mode
• 8 + 8-bit PPG output mode
The MB90495G series has two 8-/16-bit PPG timers. This section explains the functions
of PPG0/1. PPG2/3 has the same functions as PPG0/1.
■ Functions of 8-/16-bit PPG Timer
The 8-/16-bit PPG timer consists of four 8-bit reload registers (PRLH0, PRLL0, PRLH1, and PRLL1) and
two PPG down counters (PCNT0 and PCNT1).
• Individual setting of High and Low widths in output pulse enables an output pulse of any cycle and duty
ratio.
• The count clock can be selected from six internal clocks.
• The 8-/16-bit PPG timer can be used as an interval timer by generating an interrupt request at each
interval time.
• An external circuit enables the 8-/16-bit PPG timer to be used as a D/A converter.
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CHAPTER 10 8-/16-BIT PPG TIMER
10.1 Overview of 8-/16-bit PPG Timer
MB90495G Series
■ Operation Modes of 8-/16-bit PPG Timer
● 8-bit PPG output 2-channel independent operation mode
The 8-bit PPG output 2-channel independent operation mode causes the 2-channel modules (PPG0 and
PPG1) to operate as each independent 8-bit PPG timer.
Table 10.1-1 shows the interval times in the 8-bit PPG output 2-channel independent operation mode.
Table 10.1-1 Interval Times in 8-bit PPG Output 2-channel Independent Operation Mode
PPG0, PPG1
Count Clock Cycle
Interval Time
Output Pulse Time
1/φ (62.5 ns)
1/φ to 28/φ
2/φ to 29/φ
2/φ (125 ns)
2/φ to 29/φ
22/φ to 210/φ
22/φ (250 ns)
22/φ to 210/φ
23/φ to 211/φ
23/φ (500 ns)
23/φ to 211/φ
24/φ to 212/φ
24/φ (1 μs)
24/φ to 212/φ
25/φ to 213/φ
29/HCLK (128 μs)
29/HCLK to 217/HCLK
210/HCLK to 218/HCLK
HCLK: Oscillation clock
φ: Machine clock
The parenthesized values are provided when the oscillation clock operates at 4 MHz and the
machine clock operates at 16 MHz.
● 16-bit PPG output mode
The 16-bit PPG output mode concatenates the 2-channel modules (PPG0 and PPG1) to operate as a 16-bit
1-channel PPG timer.
Table 10.1-2 shows the interval times in this mode.
Table 10.1-2 Interval Times in 16-bit PPG Output Operation Mode
Count clock cycle
Interval time
Output pulse time
1/φ (62.5 ns)
1/φ to 216/φ
2/φto 217/φ
2/φ (125 ns)
2/φ to 217/φ
22/φto 218/φ
22/φ (250 ns)
22/φ to 218/φ
23/φ to 219/φ
23/φ (500 ns)
23/φ to 219/φ
24/φ to 220/φ
24/φ (1 μs)
24/φ to 220/φ
25/φ to 221/φ
29/HCLK (128 μs)
29/HCLK to 225/HCLK
210/HCLK to 226/HCLK
HCLK: Oscillation clock
φ: Machine clock
The parenthesized values are provided when the oscillation clock operates at 4 MHz and the
machine clock operates at 16 MHz.
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CHAPTER 10 8-/16-BIT PPG TIMER
10.1 Overview of 8-/16-bit PPG Timer
MB90495G Series
● 8 + 8-bit PPG output mode
The 8 + 8-bit PPG output mode causes the PPG0 of the 2-channel modules (PPG0 and PPG1) to operate as
an 8-bit prescaler and the underflow output of the PPG0 to operate as the count clock of the PPG1.
Table 10.1-3 shows the interval times in this mode.
Table 10.1-3 Interval Times in 8+8-bit PPG Output Operation Mode
PPG0
Count
Clock Cycle
PPG1
Interval
Time
Output Pulse
Time
Interval
Time
Output Pulse
Time
1/φ (62.5 ns)
1/φ to 28/φ
2/φ to 29/φ
1/φ to 216/φ
2/φ to 217/φ
2/φ (125 ns)
2/φ to 29/φ
22/φ to 210/φ
2/φ to 217/φ
22/φ to 218/φ
22/φ (250 ns)
22/φ to 210/φ
23/φ to 211/φ
22/φ to 218/φ
23/φ to 219/φ
23/φ (500 ns)
23/φ to 211/φ
24/φ to 212/φ
23/φ to 219/φ
24/φ to 220/φ
24/φ (1 μs)
24/φ to 212/φ
25/φ to 213/φ
24/φ to 220/φ
25/φ to 221/φ
29/HCLK (128 μs)
29/HCLK to
217/HCLK
210/HCLK to
218/HCLK
29/HCLK to 225/
HCLK
210/HCLK to
226/HCLK
HCLK: Oscillation clock
φ: Machine clock
The parenthesized values are provided when the oscillation clock operates at 4 MHz and the
machine clock operates at 16 MHz.
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CHAPTER 10 8-/16-BIT PPG TIMER
10.2 Block Diagram of 8-/16-bit PPG Timer
MB90495G Series
10.2
Block Diagram of 8-/16-bit PPG Timer
One 8-/16-bit PPG timer consists of 8-bit PPG timers with two channels.
This section shows the block diagrams for the 8-/16-bit PPG timer 0 and 8-/16-bit PPG
timer 1.
The PPG2 has the same function as the PPG0, and PPG3 has the same function as
PPG1.
■ Channels and PPG Pins of PPG Timers
Figure 10.2-1 shows the relationship between the channels and the PPG pins of the 8-/16-bit PPG timers in
the MB90495G series.
Figure 10.2-1 Channels and PPG Pins of PPG Timers
Pin
PPG0/1
PPG0 output pin
Pin
PPG1 output pin
Pin
PPG2/3
PPG2 output pin
Pin
PPG3 output pin
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CHAPTER 10 8-/16-BIT PPG TIMER
10.2 Block Diagram of 8-/16-bit PPG Timer
10.2.1
MB90495G Series
Block Diagram for 8-/16-bit PPG Timer 0
The 8-/16-bit PPG timer 0 consists of the following blocks.
■ Block Diagram of 8-/16-bit PPG Timer 0
Figure 10.2-2 Block Diagram of 8-/16-bit PPG Timer 0
High level side data bus
Low level side data bus
PPG0 reload
register
PRLH0
(High level side)
PPG0 operation mode control register (PPGC0)
PRLL0
(Low level side)
PEN0
⎯
PE0 PIE0 PUF0
PPG0 temporary
buffer 0 (PRLBH0)
⎯
⎯
Interrupt
request output*
R
S
Q
2
Select signal
Reload register
L/H selector
Count start value
Reload
PPG0 down counter
(PCNT0)
Clear
Reserved
Pulse selector
Operation mode
control signal
PPG1 underflow
PPG0 underflow
(to PPG1)
Underflow
CLK
PPG0
Invert output latch
Pin
PPG0
PPG output control circuit
Timebase timer output
(512/HCLK)
Resource clock (1/φ)
Resource clock (2/φ)
Resource clock (4/φ)
Resource clock (8/φ)
Resource clock (16/φ)
Count clock
selector
3
Select signal
⎯
Reserved
HCLK
φ
*
332
:
:
:
:
:
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 ⎯
⎯
Unused
PPG0/1 count clock select register (PPG01)
Reserved bit
Oscillation clock
Machine clock
The interrupt output of 8-/16- bit PPG timer 0 is combined to one interrupt
by OR circuit with the interrupt request output of PPG timer 1.
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CHAPTER 10 8-/16-BIT PPG TIMER
10.2 Block Diagram of 8-/16-bit PPG Timer
MB90495G Series
● Details of pins in block diagram
Table 10.2-1 lists the actual pin names and interrupt request numbers of the 8-/16-bit PPG timer.
Table 10.2-1 Pins and Interrupt Request Numbers in Block Diagram
Channel
Output Pin
PPG0
P14/PPG0
PPG1
P15/PPG1
PPG2
P16/PPG2
PPG3
P17/PPG3
Interrupt Request Number
#22 (16H)
#26 (1AH)
● PPG operation mode control register 0 (PPGC0)
This register enables or disables operation of the 8-/16-bit PPG timer 0, the pin output, and an underflow
interrupt. It also indicates the occurrence of an underflow.
● PPG0/1 count clock select register (PPG01)
This register sets the count clock of the 8-/16-bit PPG timer 0.
● PPG0 reload registers (PRLH0 and PRLL0)
These registers set the High width or Low width of the output pulse. The values set in these registers are
reloaded to the PPG0 down counter (PCNT0) when the 8-/16-bit PPG timer 0 is started.
● PPG0 down counter (PCNT0)
This counter is an 8-bit down counter that alternately reloads the values set in the PPG0 reload registers
(PRLH0 and PRLL0) to decrement. When an underflow occurs, this counter is concatenated for use as a
single-channel 16-bit PPG down counter.
● PPG0 temporary buffer (PRLBH0)
This buffer prevents deviation of the output pulse width caused at writing to the PPG reload registers
(PRLH0 and PRLL0). This buffer stores the PRLH0 value temporarily and enables it in synchronization
with the timing of writing to the PRLL0.
● Reload register L/H selector
This selector detects the current pin output level to select which register value, Low reload register
(PRLL0) or High reload register (PRLH0), should be reloaded to the PPG0 down counter.
● Count clock selector
This selector selects the count clock to be input to the PPG0 down counter from five frequency-divided
clocks of the machine clock or the frequency-divided clocks of the timebase timer.
● PPG output control circuit
This circuit inverts the pin output level and the output when an underflow occurs.
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CHAPTER 10 8-/16-BIT PPG TIMER
10.2 Block Diagram of 8-/16-bit PPG Timer
10.2.2
MB90495G Series
Block Diagram of 8-/16-bit PPG Timer 1
The 8-/16-bit PPG timer 1 consists of the following blocks.
■ Block Diagram of 8-/16-bit PPG Timer 1
Figure 10.2-3 Block Diagram of 8-/16-bit PPG Timer 1
High level side data bus
Low level side data bus
PPG1 operation mode control register (PPGC1)
PPG1 reload
register
PRLH1
(High side)
PRLL1
(Low side)
PEN1
⎯
PE1 PIE1 PUF1 MD1 MD0
2
Operation mode
control signal
S
Reload register
L/H selector
Count start value
PPG0 underflow
(from PPG0)
Clear
Underflow
334
PPG1
Invert output latch
Pin
PPG1
CLK
PPG output control circuit
MD0
Timebase timer output
(512/HCLK)
Resource clock (1/φ)
Resource clock (2/φ)
Resource clock (4/φ)
Resource clock (8/φ)
Resource clock (16/φ)
Count clock
selector
:
:
:
:
:
Q
Select signal
Reload
PPG1 down counter
(PCNT1)
PPG1 underflow
(to PPG0)
Interrupt
request output*
R
PPG1 temporary
buffer (PRLBH1)
⎯
Reservation
HCLK
φ
*
Reserved
3
Select signal
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 ⎯
Unused
PPG0/1 count clock select register (PPG01)
Reserved bit
Oscillation clock
Machine clock
The interrupt output of 8-/16- bit PPG timer 1 is combined to one interrupt
by OR circuit with the interrupt request output of PPG timer 0.
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CHAPTER 10 8-/16-BIT PPG TIMER
10.2 Block Diagram of 8-/16-bit PPG Timer
MB90495G Series
● Details of pins in block diagram
Table 10.2-2 lists the actual pin names and interrupt request numbers of the 8-/16-bit PPG timer.
Table 10.2-2 Pins and Interrupt Request Numbers in Block Diagram
Channel
Output Pin
PPG0
P14/PPG0
PPG1
P15/PPG1
PPG2
P16/PPG2
PPG3
P17/PPG3
Interrupt Request Number
#22 (16H)
#26 (1AH)
● PPG operation mode control register 1 (PPGC1)
This register sets the operation mode of the 8-/16-bit PPG timer, enables or disables the operation of the 8-/
16-bit PPG timer 1, the pin output and an underflow interrupt, and also indicates the generation of an
underflow.
● PPG2/3 count clock select register (PPG23)
This register sets the count clock of the 8-/16-bit PPG timer 0.
● PPG1 reload registers (PRLH1 and PRLL1)
These registers set the High width or Low width of the output pulse. The values set in these registers are
reloaded to the PPG1 down counter (PCNT1) when the 8-/16-bit PPG timer 1 is started.
● PPG1 down counter (PCNT1)
This counter is an 8-bit down counter that alternately reloads the values set in the PPG1 reload registers
(PRLH1 and PRLL1) to. When an underflow occurs, the pin output is inverted. The 2-channel PPG down
counters (PPG0 and PPG1) can also be connected for use as a single-channel 16-bit PPG down counter.
● PPG1 temporary buffer (PRLBH1)
This buffer prevents deviation of the output pulse width caused at writing to the PPG reload registers
(PRLH1 and PRLL1). It stores the PRLH1 value temporarily and enables it in synchronization with the
timing of writing to the PRLL1.
● Reload register L/H selector
This selector detects the current pin output level to select which register value, Low reload register
(PRLL1) or High reload register (PRLH1), should be reloaded to the PPG1 down counter.
● Count clock selector
This selector selects the count clock to be input to the PPG1 down counter from five frequency-divided
clocks of the machine clock or the frequency-divided clocks of the timebase timer.
● PPG output control circuit
This circuit inverts the pin output level and the output when an underflow occurs.
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CHAPTER 10 8-/16-BIT PPG TIMER
10.3 Configuration of 8-/16-bit PPG Timer
10.3
MB90495G Series
Configuration of 8-/16-bit PPG Timer
This section explains the pins, registers and interrupt factors of the 8-/16-bit PPG timer.
■ Pins of 8-/16-bit PPG Timer
The pins of the 8-/16-bit PPG timer serve as general-purpose I/O ports. Table 10.3-1 indicates the pin
functions and pin settings required to use the 8-/16-bit PPG timer.
Table 10.3-1 Pins of 8-/16-bit PPG Timer
Pin Function
Pin Setting Required for Use of
8-/16-bit PPG Timer
Channel
Pin Name
PPG0
PPG0 output pin
General-purpose I/O port,
PPG0 output pin, external
bus pin
Set PPG0 pin output to "enabled"
(PPGC0:PE=1)
PPG1
PPG1 output pin
General-purpose I/O port,
PPG1 output pin, external
bus pin
Set PPG1 pin output to "enabled"
(PPGC1:PE1=1)
PPG2
PPG2 output pin
General-purpose I/O port,
PPG2 output pin, external
bus pin
Set PPG2 pin output to "enabled"
(PPGC2:PE0=1)
PPG3
PPG3 output pin
General-purpose I/O port,
PPG3 output pin, external
bus pin
Set PPG3 pin output to "enabled"
(PPGC3:PE1=1)
■ Block Diagram of 8-/16-bit PPG Timer Pins
CHAPTER 4 "I/O PORT" for the pin block diagram.
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CHAPTER 10 8-/16-BIT PPG TIMER
10.3 Configuration of 8-/16-bit PPG Timer
MB90495G Series
■ List of Registers and Reset Values of 8-/16-bit PPG Timer
Figure 10.3-1 List of Registers and Reset Values of 8-/16-bit PPG Timer
bit
PPG0 operation mode control register: H
(PPGC1)
bit
PPG0 operation mode control register: L
(PPGC0)
bit
PPG0/1 count clock select register
(PPG01)
bit
PPG0 reload register: H (PRLH0)
bit
PPG0 reload register: L (PRLL0)
bit
PPG1 reload register: H (PRLH1)
bit
PPG1 reload register: L (PRLL1)
15
14
13
12
11
10
9
8
0
⎯
0
0
0
0
0
1
7
6
5
4
3
2
1
0
0
⎯
0
0
0
⎯
⎯
1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
×
×
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
× : Undefined
■ Generation of Interrupt Request from 8-/16-bit PPG Timer
In the 8-/16-bit PPG timer, the underflow generation flag bits in the PPG operation mode control registers
(PPGC0:PUF0, PPGC1:PUF1) are set to 1 when an underflow occurs. If the underflow interrupts of
channels causing an underflow are enabled (PPGC0:PIF0, PPGC1:PIF1), an underflow interrupt request is
generated to the interrupt controller.
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CHAPTER 10 8-/16-BIT PPG TIMER
10.3 Configuration of 8-/16-bit PPG Timer
MB90495G Series
PPG0 Operation Mode Control Register (PPGC0)
10.3.1
The PPG0 operation mode control register (PPGC0) provides the following settings:
• Enabling or disabling operation of 8-/16-bit PPG timer
• Switching between pin functions (enabling or disabling pulse output)
• Enabling or disabling underflow interrupt
• Setting underflow interrupt request flag
■ PPG0 Operation Mode Control Register (PPGC0)
Figure 10.3-2 PPG0 Operation Mode Control Register (PPGC0)
7
6
5
4
3
2
1
0
Reset value
0X000XX1B
R/W ⎯ R/W R/W R/W ⎯
⎯
W
bit 0
Reserved bit
Reserved
1
Always set to "1"
bit 3
PUF0
0
1
R/W : Read/Write
X
: Undefined
⎯
: Unused
: Reset value
338
Underflow generation flag bit
Read
No underflow
Underflow
Write
Clears PUF0 bit
No effect
bit 4
PIE0
0
1
Interrupt request disable
Interrupt request enable
bit 5
PE0
0
1
General-purpose I/O port (pulse output disable)
PPG0 output (pulse output enable)
Underflow interrupt enable bit
PPG0 pin output enable bit
bit 7
PEN0
PPG0 operation enable bit
0
Couting disable (holds "L" level output)
1
Counting enable
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CHAPTER 10 8-/16-BIT PPG TIMER
10.3 Configuration of 8-/16-bit PPG Timer
MB90495G Series
Table 10.3-2 Functions of PPG0 Operation Mode Control Register (PPGC0)
Bit Name
Function
bit 1
Reserved: Reserved bit
Always set this bit to 1.
bit 2
Unused bits
Read: The value is undefined.
Write: No effect
bit 3
PUF0:
Underflow generation
flag bit
8-bit PPG output 2-channel independent operation mode,
8+8-bit PPG output operation mode:
When the value of the PPG0 down counter is decremented from "00H" to
"FFH", an underflow occurs (PUF0 = 1).
16-bit PPG output operation mode:
When the values of the PPG0 and PPG1 down counters are decremented from
"0000H" to "FFFFH", an underflow occurs (PUF0 = 1).
• When an underflow occurs (PUF0 = 1) with an underflow interrupt enabled
(PIE0 = 1), an interrupt request is generated.
When set to 0: Clears counter
When set to 1: No effect
Read by read modify write instructions: 1 read
bit 4
PIE0:
Underflow interrupt
enable bit
This bit enables or disables an interrupt.
When set to 0: No interrupt request generated even at underflow (PUF0 = 1).
When set to 1: Interrupt request generated at underflow (PUF0 = 1)
bit 5
PE0:
PPG0 pin output enable
bit
This bit switches between PPG0 pin functions and enables or disables the pulse
output.
When set to 0: PPG0 pin functions as general-purpose I/O port.
The pulse output is disabled.
When set to 1: PPG0 pin functions as PPG0 output pin.
The pulse output is enabled.
bit 6
Unused bit
Read: The value is undefined.
Write: No effect
bit 7
PEN0:
PPG0 operation enable
bit
This bit enables or disables the count operation of the 8-/16-bit PPG timer 0.
When set to 0: Count operation disabled
When set to 1: Count operation enabled
• When the count operation is disabled (PEN0 = 0), the output is held at a Low
level.
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CHAPTER 10 8-/16-BIT PPG TIMER
10.3 Configuration of 8-/16-bit PPG Timer
MB90495G Series
PPG1 Operation Mode Control Register (PPGC1)
10.3.2
The PPG1 operation mode control register (PPGC1) provides the following settings:
• Enabling or disabling operation of 8-/16-bit PPG timer
• Switching between pin functions (enabling or disabling pulse output)
• Enabling or disabling underflow interrupt
• Setting underflow interrupt request flag
• Setting the operation mode of the 8-/16-bit PPG timer
■ PPG1 Operation Mode Control Register (PPGC1)
Figure 10.3-3 PPG1 Operation Mode Control Register (PPGC1)
15
14
13
12
11
10
9
8
Reset value
0X000001
R/W ⎯ R/W R/W R/W R/W R/W
B
W
bit 8
Reserved bit
Reserved
1
Always set to "1"
bit 10 bit 9
MD1 MD0
0
0
0
1
1
0
1
1
Operation mode select bits
8-bit PPG output 2-ch independent operation mode
8 + 8-bit PPG output operation mode
Setting disable
16-bit PPG output operation mode
bit 11
PUF1
0
1
Underflow generation flag bit
Read
No underflow
Underflow
Write
Clears PUF1 bit
No effect
bit 12
Underflow interrupt enable bit
PIE1
0
Underflow interrupt request disable
1
Underflow interrupt request enable
bit 13
PPG1 pin output enable bit
PE1
0
General-purpose I/O port (pulse output disable)
1
PPG1 output (pulse output enable)
R/W : Read/Write
X
: Undefined
⎯
: Unused
: Reset value
340
bit 15
PPG1 operation enable bit
PEN1
Counting disable (holds "L" level output)
0
Counting enable
1
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CHAPTER 10 8-/16-BIT PPG TIMER
10.3 Configuration of 8-/16-bit PPG Timer
MB90495G Series
Table 10.3-3 Functions of PPG1 Operation Mode Control Register (PPGC1)
Bit Name
Function
bit 8
Reserved:
Reserved bit
Always set this bit to 1.
bit 9
bit 10
MD1, MD0:
Operation mode select
bits
These bits set the operation mode of the 8-/16-bit PPG timer.
[Any mode other than 8-bit PPG output 2-channel independent operation
mode]
• Use a word instruction to set the PPG operation enable bits (PEN0 and PEN1)
at one time.
• Do not set operation of only one of the two channels (PEN1 = 0/PEN0 = 1 or
PEN1 = 1/PEN0 = 0).
Note:
Do not set the MD1 and MD0 bits to "10B".
bit 11
PUF1:
Underflow generation
flag bit
8-bit PPG output 2-channel independent operation mode,
8+8-bit PPG output operation mode:
When the value of the PPG1 down counter is decremented from "00H" to
"FFH", an underflow occurs (PUF1 = 1).
16-bit PPG output operation mode:
When the values of the PPG0 and PPG1 down counters are decremented from
"0000H" to "FFFFH", an underflow occurs (PUF1 = 1).
• When an underflow occurs (PUF1 = 1) with an underflow interrupt enabled
(PIE1 = 1), an interrupt request is generated.
When set to 0: Clears counter
When set to 1: No effect
Read by read modify write instructions: 1 is read.
bit 12
PIE1:
Underflow interrupt
enable bit
This bit enables or disables an interrupt.
When set to 0: No interrupt request is generated even at underflow (PUF1 = 1)
When set to 1: Interrupt request is generated at underflow (PUF1 = 1)
bit 13
PE1:
PPG1 Pin output enable
bit
This bit enables or disables an interrupt.
When set to 0: No interrupt request is generated even at underflow (PUF1 = 1)
When set to 1: Interrupt request is generated at underflow (PUF1 = 1)
bit 14
Unused bit
Read: The value is undefined.
Write: No effect
bit 15
PEN1:
PPG1 operation enable
bit
This bit enables or disables the count operation of the 8-/16-bit PPG timer 1.
When set to 0: Count operation disabled
When set to 1: Count operation enabled
• When the count operation is disabled (PEN1 = 0), the output is held at a Low
level.
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CHAPTER 10 8-/16-BIT PPG TIMER
10.3 Configuration of 8-/16-bit PPG Timer
MB90495G Series
PPG0/1 Count Clock Select Register (PPG01)
10.3.3
The PPG0/1 count clock select register (PPG01) selects the count clock of the 8-/16-bit
PPG timer.
■ PPG0/1 Count Clock Select Register (PPG01)
Figure 10.3-4 PPG0/1 Count Clock Select Register (PPG01)
7
6
5
4
3
2
1
0
R/W R/W R/W R/W R/W R/W ⎯
⎯
Reset value
000000XX
bit 4 bit 3 bit 2
PCM2 PCM1 PCM0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
R/W
X
⎯
:
:
:
:
HCLK :
φ
:
Read/Write
Undefined
Unused
Reset value
Oscillation clock
Machine clock
bit 7 bit 6 bit 5
PCS2 PCS1 PCS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
B
PPG0 count clock select bits
1/φ (62.5 ns)
2/φ (125 ns)
22/φ (250 ns)
23/φ (500 ns)
24/φ (1 μs)
Setting disable
Setting disable
29/HCLK (128 μs)
PPG1 count clock select bits
1/φ (62.5 ns)
2/φ (125ns)
22/φ (250 ns)
23/φ (500 ns)
24/φ (1 μs)
Setting disable
Setting disable
29/HCLK (128 μs)
The parenthesized values are provided when the oscillation clock operates at 4 MHz and
the machine clock operates at 16 MHz.
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CHAPTER 10 8-/16-BIT PPG TIMER
10.3 Configuration of 8-/16-bit PPG Timer
MB90495G Series
Table 10.3-4 Functions of PPG0/1 Count Clock Select Register (PPG01)
Bit Name
bit 0
bit 1
Function
Unused bits
Read: The value is undefined.
Write: No effect
bit 2 to bit 4
PCM2 to PCM0:
PPG0 count clock select
bit
These bits set the count clock of the 8-/16-bit PPG timer 0.
• The count clock can be selected from five frequency-divided clocks of the
machine clock and the frequency-divided clocks of the timebase timer.
bit 5 to bit 7
PCS2 to PCS0:
PPG1 count clock select
bits
These bits set the count clock of the 8-/16-bit PPG timer 1.
• The count clock can be selected from five frequency-divided clocks of the
machine clock and the frequency-divided clocks of the timebase timer.
• The settings of the PPG1 count clock select bits (PCS2 to PCS0) are
enabled only in the 8-bit PPG output 2-channel independent mode
(PPGC1:MD1, MD0 = "00B").
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CHAPTER 10 8-/16-BIT PPG TIMER
10.3 Configuration of 8-/16-bit PPG Timer
10.3.4
MB90495G Series
PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1)
The value (reload value) from which the PPG down counter starts counting is set in the
PPG reload registers, which are an 8-bit register at Low level and an 8-bit register at
High level.
■ PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1)
Figure 10.3-5 PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
PRLH0/PRLH1
D15 D14
D13
D12 D11 D10
D9
Reset value
D8
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
D7
PRLL0/PRLL1
D6
D5
D4
D3
D2
D1
D0
Reset value
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
X
: Read/Write
: Undefined
Table 10.3-5 indicates the functions of the PPG reload registers.
Table 10.3-5 Functions of PPG Reload Registers
Notes:
344
Function
8-/16-bit PPG Timer 0
8-/16-bit PPG Timer 1
Retains reload value on
Low-level side
PRLL0
PRLL1
Retains reload value on
High-level side
PRLH0
PRLH1
• In the 16-bit PPG output operation mode (PPGC1:MD1, MD0 = "11B"), use a long-word instruction
to set the PPG reload registers or the word instruction to set the PPG0 and PPG1 in this order.
• In the 8 + 8-bit PPG output operation mode (PPGC1:MD1, MD0 = "01B"), set the same value in both
the Low-level and High-level PPG reload registers (PRTLL0/PRLH0) of the 8-/16-bit PPG timer 0.
Setting a different value in the Low-level and High-level PPG reload registers may cause the 8-/16-bit
PPG timer 1 to have different PPG output waveforms at each clock cycle.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 10 8-/16-BIT PPG TIMER
10.4 Interrupts of 8-/16-bit PPG Timer
MB90495G Series
10.4
Interrupts of 8-/16-bit PPG Timer
The 8-/16-bit PPG timer can generate an interrupt request when the PPG down counter
underflows. It corresponds to the EI2OS.
■ Interrupts of 8-/16-bit PPG Timer
Table 10.4-1 shows the interrupt control bits and interrupt factor of the 8-/16-bit PPG timer.
Table 10.4-1 Interrupt Control Bits of 8-/16-bit PPG Timer
PPG0
PPG1
Interrupt request flag bit
PPPGC0:PUF0
PPGC1:PUF1
Interrupt request enable bit
PPGC0:PIE0
PPGC1:PIE1
Interrupt factor
Underflow in PPG0 down counter
Underflow in PPG1 down counter
[8-bit PPG output 2-channel independent operation mode or 8 + 8-bit PPG output operation mode]
• In the 8-bit PPG output 2-channel independent operation mode or the 8 + 8-bit PPG output operation
mode, the PPG0 and PPG1 timers can generate an interrupt independently.
• When the value of the PPG0 or PPG1 down counter is decremented from "00H" to "FFH", an underflow
occurs. When an underflow occurs, the underflow generation flag bit in the channel causing an
underflow is set (PPGC0:PUF0 = 1 or PPGC1:PUF1 = 1).
• If an interrupt request from the channel that causes an underflow is enabled (PPGC0:PIE0 = 1 or
PPGC1:PIE1 = 1), an interrupt request is generated.
[16-bit PPG output operation mode]
• In the 16-bit PPG output operation mode, when the values of the PPG0 and PPG1 down counters are
decremented from "0000H" to "FFFFH", an underflow occurs. When an underflow occurs, the underflow
generation flag bits in the two channels are set at one time (PPGC0:PUF0 = 1 and PPGC1:PUF1 = 1).
• When an underflow occurs with either of the two channel of the interrupt requests enabled
(PPGC0:PIE1 = 0, PPGC1:PIE1 = 1 or PPGC0:PIE1 = 1, PPGC1:PIE1 = 0), an interrupt request is
generated.
• To prevent duplication of interrupt requests, disable either of the two channel of the underflow interrupt
enable bits (PPGC0:PIE1 = 0, PPGC1:PIE1 = 1 or PPGC0:PIE1 = 1, PPGC1:PIE1 = 0).
■
• When the two channels of the underflow generation flag bits are set (PPGC0:PUF0 = 1 and
PPGC1:PUF1 = 1), clear the two channels at the same time.
Correspondence between 8-/16-bit PPG Timer Interrupt and EI2OS
For details of the interrupt number, interrupt control register, and interrupt vector address, see "3.5
Interrupt".
■ 8-/16-bit PPG Timer Interrupt and EI2OS Function
The 8-/16-bit PPG timer does not correspond to the EI2OS function.
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CHAPTER 10 8-/16-BIT PPG TIMER
10.5 Explanation of Operation of 8-/16-bit PPG Timer
10.5
MB90495G Series
Explanation of Operation of 8-/16-bit PPG Timer
The 8-/16-bit PPG timer outputs a pulse width at any cycle and at any duty ratio
continuously.
■ Operation of 8-/16-bit PPG Timer
● Output operation of 8-/16-bit PPG timer
• The 8-/16-bit PPG timer has two (Low-level and High-level) 8-bit reload registers (PRLL0/PRLH0 and
PRLL1/PRLH1) for per channel.
• The values set in the 8-bit reload registers (PRLL0/PRLH0 and PRLL1/PRLH1) are reloaded alternately
to the PPG down counters (PCNT0 and PCNT1).
• After reloading the values in the PPG down counters, decrementing is performed in synchronization
with the count clocks set by the PPG count clock select bits (PPG01:PCM2 to PCM0 and PCS1 and
PCS0).
• If the values set in the reload registers are reloaded to the PPG down counters when an underflow
occurs, the pin output is inverted.
Figure 10.5-1 shows the output waveform of the 8-/16-bit PPG timer.
Figure 10.5-1 Output Waveform of 8-/16-bit PPG Timer
Operation start
Operation stop
PPG operation enable bit
(PEN)
PPG output pin
T × (L + 1)
T × (H + 1)
L : Value of PPG reload register (PRLL)
H : Value of PPG reload register (PRLH)
T : Count clock cycle
● Operation modes of 8-/16-bit PPG timer
As long as the operation of the 8-/16-bit PPG timer is enabled (PPGC0:PEN0 = 1, PPGC1:PEN1 = 1), a
pulse waveform is output continuously from the PPG output pin. A pulse width of any cycle and duty ratio
can be set.
The pulse output of the 8-/16-bit PPG timer is not stopped until operation of the 8-/16-bit PPG timer is
stopped (PPGC0:PEN0 = 0, PPGC1:PEN1 = 0).
• 8-bit PPG output 2-channel independent operation mode
• 16-bit PPG output operation mode
• 8 + 8-bit PPG output operation mode
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CHAPTER 10 8-/16-BIT PPG TIMER
10.5 Explanation of Operation of 8-/16-bit PPG Timer
MB90495G Series
10.5.1
8-bit PPG Output 2-channel Independent Operation Mode
In the 8-bit PPG output 2-channel independent operation mode, the 8-/16-bit PPG timer
is set as an 8-bit PPG timer with two independent channels. PPG output operation and
interrupt request generation can be performed independently for each channel.
■ Setting for 8-bit PPG Output 2-channel Independent Operation Mode
Operating the 8-/16-bit PPG timer in the 8-bit PPG output 2-channel independent operation mode requires
the setting shown in Figure 10.5-2.
Figure 10.5-2 Setting for 8-bit PPG Output 2-channel Independent Operation Mode
bit 15 14
2
1
bit 0
PPGC1/PPGC0 PEN1 ⎯ PE1 PIE1 PUF1 MD1 MD0 Reserved PEN0 ⎯ PE0 PIE0 PUF0 ⎯
0
0
1
1
1
⎯
Reserved
PPG01
13
12
11
10
(Reserved area)
9
bit 8 bit 7
6
5
4
3
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 ⎯
1
⎯
PRLH0/PRLL0 PPG0 Set High level side reload values. PPG0 Set Low level side reload values.
PRLH1/PRLL1 PPG1 Set High level side reload values. PPG1 Set Low level side reload values.
: Used bit
⎯ : Unused bit
1 : Set 1
0 : Set 0
Note:
CM44-10114-7E
Use the word instruction to set both High-level and Low-level PPG reload registers (PRLL0/PRLH0 and
PRLL1/PRLH1) at the same time.
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CHAPTER 10 8-/16-BIT PPG TIMER
10.5 Explanation of Operation of 8-/16-bit PPG Timer
MB90495G Series
● Operation in 8-bit PPG output 2-channel independent operation mode
• The 8-bit PPG timer with two channels performs an independent PPG operation.
• When the pin output is enabled (PPGC0:PE0 = 1, PPGC1:PE1 = 1), the PPG0 pulse wave is output from
the PPG0 pin and the PPG1 pulse wave is output from the PPG1 pin.
• When the reload value is set in the PPG reload registers (PRLL0/PRLH0 and PRLL1/PRLH1) to enable
the operation of the PPG timer (PPGC0:PEN0 = 1, PPGC1:PEN1 = 1), the PPG down counter of the
enabled channel starts counting.
• To stop the count operation of the PPG down counter, disable the operation of the PPG timer of the
channel to be stopped (PPGC0:PEN0 = 0, PPGC1:PEN1 = 0). The count operation of the PPG down
counter is stopped and the output of the PPG output pin is held at a Low level.
• When the PPG down counter of each channel underflows, the reload values set in the PPG reload
registers (PRLL0/PRLH0 and PRLL1/PRLH1) are reloaded to the PPG down counter that underflows.
• When an underflow occurs, the underflow generation flag bit in the channel that causes an underflow is
set (PPGC0:PUF0 = 1, PPGC1:PUF1 = 1). If an interrupt request is enabled at the channel that causes
an underflow (PPGC0:PIE0 = 1, PPGC1:PIE1 = 1), the interrupt request is generated.
● Output waveform in 8-bit PPG output 2-channel independent operation mode
• The High and Low pulse widths to be output are determined by adding 1 to the value in the PPG reload
register and multiplying it by the count clock cycle. For example, if the value in the PPG reload register
is "00H", the pulse width has one count clock cycle, and if the value is "FFH", the pulse width has 256
count clock cycles.
The equations for calculating the pulse width are shown below:
PL= T x (L + 1)
PH= T x (H + 1)
PL: Low width of output pulse
PH: High width of output pulse
L: Values of 8 bits in PPG reload register (PRLL0 or PRLL1)
H: Values of 8 bits in PPG reload register (PRLH0 or PRLH1)
T: Count clock cycle
Figure 10.5-3 shows the output waveform in the 8-bit PPG output 2-channel independent operation mode.
Figure 10.5-3 Output Waveform in 8-bit PPG Output 2-channel Independent Operation Mode
Operation start
Operation stop
PPG operation enable bit
(PEN)
PPG output pin
T × (L + 1)
T × (H + 1)
L : Value of PPG reload register (PRLL)
H : Value of PPG reload register (PRLH)
T : Count clock cycle
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CHAPTER 10 8-/16-BIT PPG TIMER
10.5 Explanation of Operation of 8-/16-bit PPG Timer
MB90495G Series
10.5.2
16-bit PPG Output Operation Mode
In the 16-bit PPG output operation mode, the 8-/16-bit PPG timer is set as a 16-bit PPG
timer with one channel.
■ Setting for 16-bit PPG Output Operation Mode
Operating the 8-/16-bit PPG timer in the 16-bit PPG output operation mode requires the setting shown in
Figure 10.5-4.
Figure 10.5-4 Setting for 16-bit PPG Output Operation Mode
bit15 14
13
12
11
10
9
PPGC1/PPGC0 PEN1 ⎯ PE1 PIE1 PUF1 MD1 MD0
1
1
1
PPG01
(Reserved area)
bit8 bit7
Reserved
1
2
1
bit0
PEN0 ⎯ PE0 PIE0 PUF0 ⎯
6
5
4
3
⎯
Reserved
1
1
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 ⎯
×
×
⎯
×
PRLH0/PRLL0 PPG0 Set high level side reload values of lower 8 bits. PPG0 Set low level side reload values of lower 8 bits.
PRLH1/PRLL1 PPG1 Set high level side reload values of upper 8 bits. PPG1 Set low level side reload values of upper 8 bits.
: Used bit
× : Undefined bit
⎯ : Unused bit
1 : Set 1
0 : Set 0
Note:
CM44-10114-7E
Use a long-word instruction to set the values in the PPG reload registers or a word instruction to set the
PPG0 and PPG1 (PRLL0 --> PRLL1 or PRLH0 --> PRLH1) in this order.
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CHAPTER 10 8-/16-BIT PPG TIMER
10.5 Explanation of Operation of 8-/16-bit PPG Timer
MB90495G Series
● Operation in 16-bit PPG output operation mode
• When either PPG0 pin output or PPG1 pin output is enabled (PPGC0:PE0 = 1, PPGC1:PE1 = 1), the
same pulse wave is output from both the PPG0 and PPG1 pins.
• When the reload value is set in the PPG reload registers (PRLL0/PRLH0 and PRLL1/PRLH1) to enable
operation of the PPG timer (PPGC0:PEN0 = 1 and PPGC1:PEN1 = 1), the PPG down counters start
counting as 16-bit down counters (PCNT0 + PCNT1).
• To stop the count operation of the PPG down counters, disable the operation of the PPG timers of both
channels (PPGC0:PEN0 = 0 and PPGC1:PEN1 = 0). The count operation of the PPG down counters is
stopped and the output of the PPG output pin is held at a Low level.
• If the PPG1 down counter underflows, the reload values set in the PPG0 and PPG1 reload registers
(PRLL0/PRLH0 and PRLL1/PRLH1) are reloaded simultaneously to the PPG down counters (PCNT0 +
PCNT1).
• When an underflow occurs, the underflow generation flag bits in both channels are set simultaneously
(PPGC0:PUF0 = 1, PPGC1:PUF1 = 1). If an interrupt request is enabled at either channel (PPGC0:PIE0
= 1, PPGC1:PIE1 = 1), an interrupt request is generated.
Notes:
350
• In the 16-bit PPG output operation mode, the underflow generation flag bits in the two channels are
set simultaneously when an underflow occurs (PPGC0:PUF0 = 1 and PPGC1:PUF1 = 1). To prevent
duplication of interrupt requests, disable either of the underflow interrupt enable bits in the two
channels (PPGC0:PIE0 = 0, PPGC1:PIE1 = 1 or PPGC0:PIE0 = 1, PPGC1:PIE1 = 0).
• If the underflow generation flag bits in the two channels are set (PPGC0:PUF0 = 0 and PPGC1:PUF1
= 0), clear the two channels at the same time.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 10 8-/16-BIT PPG TIMER
10.5 Explanation of Operation of 8-/16-bit PPG Timer
MB90495G Series
● Output waveform in 16-bit PPG output operation mode
The High and Low pulse widths to be output are determined by adding 1 to the value in the PPG reload
register and multiplying it by the count clock cycle. For example, if the value in the PPG reload register is
"0000H", the pulse width has one count clock cycle, and if the value is "FFFFH", the pulse width has 65,536
count clock cycles.
The equations for calculating the pulse width are shown below:
PL= T x (L + 1)
PH= T x (H + 1)
PL: Low width of output pulse
PH: High width of output pulse
L: Values of 16 bits in PPG reload register (PRLL0 + PRLL1)
H: Values of 16 bits in PPG reload register (PRLH0 + PRLH1)
T: Count clock cycle
Figure 10.5-5 shows the output waveform in the 16-bit PPG output operation mode.
Figure 10.5-5 Output Waveform in 16-bit PPG Output Operation Mode
Operation start
Operation stop
PPG operation enable bit
(PEN)
PPG output pin
T × (L + 1)
T × (H + 1)
L : Values of 16 bits in PPG reload register (PRLL1 + PRLL0)
H : Values of 16 bits in PPG reload register (PRLH1 + PRLH0)
T : Count clock cycle
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CHAPTER 10 8-/16-BIT PPG TIMER
10.5 Explanation of Operation of 8-/16-bit PPG Timer
10.5.3
MB90495G Series
8+8-bit PPG Output Operation Mode
In the 8 + 8-bit PPG output operation mode, the 8-/16-bit PPG timer is set as an 8-bit
PPG timer. The PPG0 operates as an 8-bit prescaler and the PPG1 operates using the
PPG output of the PPG0 as a clock source.
■ Setting for 8+8-bit PPG Output Operation Mode
Operating the 8-/16-bit PPG timer in the 8+8-bit PPG output operation mode requires the setting shown in
Figure 10.5-6.
Figure 10.5-6 Setting for 8+8-bit PPG Output Operation Mode
bit 15 14
13
12
11
10
9
PPGC1/PPGC0 PEN1 ⎯ PE1 PIE1 PUF1 MD1 MD0
0
1
1
PPG01
(Reserved area)
bit 8 bit 7
Reserved
1
6
5
4
3
2
1
bit 0
PEN0 ⎯ PE0 PIE0 PUF0 ⎯
⎯
Reserved
1
1
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 ⎯
×
×
⎯
×
PRLH0/PRLL0 PPG0 Set High level side reload values. PPG0 Set Low level side reload values.
PRLH1/PRLL1 PPG1 Set High level side reload values. PPG1 Set Low level side reload values.
: Used bit
× : Udefined bit
⎯ : Unused bit
1 : Set 1
0 : Set 0
Note:
352
Use the word instruction to set both High-level and Low-level PPG reload registers (PRLL0/PRLH0 and
PRLL1/PRLH1) at the same time.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 10 8-/16-BIT PPG TIMER
10.5 Explanation of Operation of 8-/16-bit PPG Timer
MB90495G Series
● Operation in 8+8-bit PPG output operation mode
• The PPG0 operates as the prescaler of the PPG timer and the PPG1 operates using the PPG0 output as a
clock source.
• When pin output is enabled (PPGC0:PE0 = 1, PPGC1:PE1 = 1), the PPG0 pulse wave is output from the
PPG0 pin and the PPG1 pulse wave is output form the PPG1 pin.
• The PPG0 pin and the PPG1 pulse wave is output form the PPG1 pin.
• When the reload value is set in the PPG reload registers (PRLL0/PRLH0, PRLL1/PRLH1) to enable
operation of the PPG timer (PPGC0:PEN0 = 1 and PPGC1:PEN1 = 1), the PPG down counter starts
counting.
• To stop the count operation of the PPG down counters, disable the operation of the PPG timers of both
channels (PPGC0:PEN0 = 0 and PPGC1:PEN1 = 0). The count operation of the PPG down counters is
stopped and the output of the PPG output pin is held at a Low level.
• If the PPG down counter of each channel underflows, the reload values set in the PPG reload registers
(PRLL0/PRLH0, PRLL1/PRLH1) are reloaded to the PPG down counter that underflows.
• When an underflow occurs, the underflow generation flag bit in the channel that causes an underflow
(PPGC0:PUF0 = 1, PPGC1:PUF1 = 1) is set. If an interrupt request is enabled at the channel that causes
an underflow (PPGC0:PIE0 = 1, PPGC1:PIE1 = 1), an interrupt request is generated.
Notes:
CM44-10114-7E
• Do not operate PPG1 (PPGC1:PEN1 = 1) when PPG0 is stopped (PPGC0:PEN0 = 0).
• It is recommended to set the same value in both Low-level and High-level PPG reload registers
(PRLL0/PRLH0, PRLL1/PRLH1).
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CHAPTER 10 8-/16-BIT PPG TIMER
10.5 Explanation of Operation of 8-/16-bit PPG Timer
MB90495G Series
● Output waveform in 8+8-bit PPG output operation mode
The High and Low pulse widths to be output are determined by adding 1 to the value in the PPG reload
register and multiplying it by the count clock cycle.
The equations for calculating the pulse width are shown below:
PL = T x (L0+ 1) x (L 1+ 1)
PH = T x (H0+ 1) x (H 1+ 1)
PL: Low width of output pulse of PPG1 pin
PH: High width of output pulse of PPG1 pin
L0: Values of 8 bits in PPG reload register (PRLL0)
H0: Values of 8 bits in PPG reload register (PRLH0)
L1: Values of 8 bits in PPG reload register (PRLL1)
H1: Values of 8 bits in PPG reload register (PRLH1)
T: Count clock cycle
Figure 10.5-7 shows the output waveform in the 8+8-bit PPG output operation mode.
Figure 10.5-7 Output Waveform in 8+8-bit PPG Output Operation Mode
Operation start
Operation stop
PPG operation enable bit
(PEN0, PEN1)
T × (L0 + 1)
T × (H0 + 1)
PPG0 output pin
PPG1 output pin
T × (L0 + 1) × (L1 + 1)
L0 :
H0 :
H1 :
L1 :
T :
354
T × (H0 + 1) × (H1 + 1)
Values of 8 bits in PPG reload register (PRLL0)
Values of 8 bits in PPG reload register (PRLH0)
Values of 8 bits in PPG reload register (PRLL1)
Values of 8 bits in PPG reload register (PRLH1)
Count clock cycle
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 10 8-/16-BIT PPG TIMER
10.6 Precautions when Using 8-/16-bit PPG Timer
MB90495G Series
10.6
Precautions when Using 8-/16-bit PPG Timer
This section explains the precautions when using the 8-/16-bit PPG timer.
■ Precautions when Using 8-/16-bit PPG Timer
● Effect on 8-/16-bit PPG timer when using timebase timer output
• If the output signal of the timebase timer is used as the input signal for the count clock of the 8-/16-bit
PPG timer (PPG01:PCM2 to PCM0 = "111B", PCS2 to PCS0 = "111B"), deviation may occur in the first
count cycle in which the PPG timer is started by trigger input or in the count cycle immediately after the
PPG timer is stopped.
• When the timebase timer counter is cleared during the count operation of the PPG down counter,
deviation may occur in the count cycle.
● Setting of PPG reload registers when using 8-bit PPG timer
• The Low-level and High-level pulse widths are determined at the timing of reloading the values in the
Low-level PPG reload registers (PRLL0, PRLL1) to the PPG down counter.
• If the 8-bit PPG timer is used in the 8-bit PPG output 2-channel independent operation mode or the 8 +
8-bit PPG output operation mode, use a word instruction to set both High-level and Low-level PPG
reload registers (PRLL0/PRLH0, PRLL1/PRLH1) at the same time.
Using a byte instruction may cause an unexpected pulse to be generated.
[Example of rewriting PPG reload registers using byte instruction]
Immediately before the signal level of the PPG pin switches from High to Low, if the value in the Highlevel PPG reload register (PRLH) is rewritten after the value in the Low-level PPG reload register (PRLL)
is rewritten using the byte instruction, a Low-level pulse width is generated after rewriting and a High-level
pulse width is generated before rewriting.
Figure 10.6-1 shows the waveform as the values in the PPG reload registers are rewritten using the byte
instruction.
Figure 10.6-1 Waveform when Values in PPG Reload Registers Rewritten Using Byte Instruction
PRLL
A
PRLH
B
C
D
A+B
A+B
B+C
C+D
B
B
C + D Timing of updating
reload value
C+D
PPG pin
A
B
A
C
C
D
C
D
<1> <2>
<1>: Change the value (A → C) of PPG reload register (PRLL)
<2>: Change the value (B → D) of PPG reload register (PRLH)
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CHAPTER 10 8-/16-BIT PPG TIMER
10.6 Precautions when Using 8-/16-bit PPG Timer
MB90495G Series
● Setting of PPG reload registers when using 16-bit PPG timer
• Use a long-word instruction to set the PPG reload registers (PRLL0/PRLH0, PRLL1/PRLH1) or a word
instruction to set the word instruction to set the PPG0 and PPG1 (PRLL0 --> PRLL1 or PRLH0 -->
PRLH1) in this order.
[Reload timing in 16-bit PPG output operation mode]
In the 16-bit PPG output operation mode, the reload values written to the PPG0 reload registers (PRLL0/
PRLH0) are written temporarily to the temporary latch, written to the PPG1 reload registers (PRLL1/
PRLH1), and then transferred to the PPG0 reload registers (PRLL0/PRLH0). Therefore, when setting the
reload value in the PPG1 reload registers (PRLL1/PRLH1), it is necessary to set the reload value in the
PPG0 reload registers (PRLL0/PRLH0) simultaneously or set the reload value in the PPG0 reload registers
(PRLL0/PRLH0) before setting it in the PPG1 reload registers (PRLL1/PRLH1).
Figure 10.6-2 shows the reload timing in the 16-bit PPG output operation mode.
Figure 10.6-2 Reload Timing in 16-bit PPG Output Operation Mode
Reload value
of PPG0
Only 16-bit PPG output operation mode
Temporary latch
Write to PPG0 except 16-bit
PPG output operation mode
Reload value
of PPG1
Write to PPG1
Transfers synchronously
with writing to PPG1
PPG reload register
(PRLL0, PRLH0)
356
PPG reload register
(PRLL1, PRLH1)
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 11
DELAYED INTERRUPT
GENERATION MODULE
This chapter explains the functions and operations of
the delayed interrupt generation module.
11.1 Overview of Delayed Interrupt Generation Module
11.2 Block Diagram of Delayed Interrupt Generation Module
11.3 Configuration of Delayed Interrupt Generation Module
11.4 Explanation of Operation of Delayed Interrupt Generation Module
11.5 Precautions when Using Delayed Interrupt Generation Module
11.6 Program Example of Delayed Interrupt Generation Module
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CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.1 Overview of Delayed Interrupt Generation Module
11.1
MB90495G Series
Overview of Delayed Interrupt Generation Module
The delayed interrupt generation module generates the interrupt for task switching.
The hardware interrupt request can be generated/cancelled by software.
■ Overview of Delayed Interrupt Generation Module
By using the delayed interrupt generation module, a hardware interrupt request can be generated or
cancelled by software.
Table 11.1-1 shows the block diagram of the delayed interrupt generation module
Table 11.1-1 Overview of Delayed Interrupt Generate Module
Function and Control
358
Interrupt factor
An interrupt request is generated by setting the R0 bit in the delayed interrupt
request generate/cancel register to 1 (DIRR:R0 = 1).
An interrupt request is cancelled by setting the R0 bit in the delayed interrupt
request generate/cancel register to 0 (DIRR:R0 = 0).
Interrupt number
#42 (2AH)
Interrupt control
An interrupt is not enabled by the DIRR register.
Interrupt flag
The interrupt flag is held in the R0 bit in the DIRR register.
EI2OS
The DIRR register does not correspond to the EI2OS.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.2 Block Diagram of Delayed Interrupt Generation Module
MB90495G Series
11.2
Block Diagram of Delayed Interrupt Generation Module
The delayed interrupt generation module consists of the following blocks:
• Interrupt request latch
• Delayed interrupt request generate/cancel register (DIRR)
■ Block Diagram of Delayed Interrupt Generation Module
Figure 11.2-1 Block Diagram of Delayed Interrupt Generation Module
Internal data bus
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R0
Delayed interrupt request generate/cancel register (DIRR)
S Interrupt request
R latch
⎯: Unused
Interrupt
request
signal
● Interrupt request latch
This latch keeps the settings (delayed interrupt request generation or cancellation) of the delayed interrupt
request generate/cancel register (DIRR).
● Delayed interrupt request generate/cancel register (DIRR)
This register generates or cancels a delayed interrupt request.
■ Interrupt Number
The interrupt number used in the delayed interrupt generation module is as follows:
Interrupt number #42 (2AH)
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CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.3 Configuration of Delayed Interrupt Generation Module
11.3
MB90495G Series
Configuration of Delayed Interrupt Generation Module
This section lists registers and reset values in the delayed interrupt generation module.
■ List of Registers and Reset Values in Delayed Interrupt Generation Module
Figure 11.3-1 List of Registers and Reset Values in Delayed Interrupt Generation Module
bit
Delayed interrupt request generate/cancel register (DIRR)
×:
360
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
0
Undefined
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.3 Configuration of Delayed Interrupt Generation Module
MB90495G Series
11.3.1
Delayed Interrupt Request Generate/Cancel Register
(DIRR)
The delayed interrupt request generate/cancel register (DIRR) generates or cancels a
delayed interrupt request.
■ Delayed Interrupt Request Generate/Cancel Register (DIRR)
Figure 11.3-2 Delayed Interrupt Request Generate/Cancel Register (DIRR)
15
14
13
12
11
10
9
⎯
⎯
⎯
⎯
⎯
⎯
⎯ R/W
8
Reset value
XXXXXXX0B
bit 8
R0
0
1
⎯
: Unused
R/W : Read/Write
: Reset value
Delayed interrupt request generate bit
Cancels delayed interruput request
Generates delayed interrupt request
Table 11.3-1 Functions of Delayed Interrupt Request Generate/Cancel Register (DIRR)
Bit Name
bit 8
bit 9 to bit 15
CM44-10114-7E
Function
R0:
Delayed interrupt request
generate bit
This bit generates or cancels a delayed interrupt request.
When set to 0: Cancels delayed interrupt request
When set to 1: Generates delayed interrupt request
Unused bits
Read: The value is undefined
Write: No effect
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CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.4 Explanation of Operation of Delayed Interrupt Generation Module
11.4
MB90495G Series
Explanation of Operation of Delayed Interrupt Generation
Module
The delayed interrupt generation module has a function for generating or canceling an
interrupt request by software.
■ Explanation of Operation of Delayed Interrupt Generation Module
Using the delayed interrupt generation module requires the setting shown in Figure 11.4-1.
Figure 11.4-1 Setting for Delayed Interrupt Generation Module
bit 15 14
DIRR
⎯
⎯
13
12
11
10
⎯
⎯
⎯ ⎯
9 bit 8
⎯ R0
⎯ : Unused bit
: Used bit
When the R0 bit in the delayed interrupt request generate/cancel register (DIRR) is set to 1 (DIRR:R0 = 1),
an interrupt request is generated. There is no interrupt request enable bit.
● Operation of delayed interrupt generation module
• When the R0 bit in the delayed interrupt request generate/cancel register (DIRR) is set to 1, the interrupt
request latch is set to 1 and an interrupt request is generated to the interrupt controller.
• When an interrupt request is preferred to other requests, by the interrupt controller the interrupt request
is generated to the CPU.
• When the level of an interrupt request (ICR:IL) is preferred to that of the interrupt level mask bit in the
condition code register (CCR:ILM), the CPU delays interrupt processing until completion of execution
of the current instruction.
• At interrupt processing, the user program sets the R0 bit to 0, cancels the interrupt request, and changes
the task.
Figure 11.4-2 shows the operation of the delayed interrupt generation module.
Figure 11.4-2 Operation of Delayed Interrupt Generation Module
Delayed interrupt generation module
Other request
DIRR
Interrupt controller
ICR YY
CPU
IL
CMP
CMP
ICR XX
362
ILM
FUJITSU SEMICONDUCTOR LIMITED
Interrupt
processing
CM44-10114-7E
MB90495G Series
11.5
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.5 Precautions when Using Delayed Interrupt Generation Module
Precautions when Using Delayed Interrupt Generation
Module
This section explains the precautions when using the delayed interrupt generation
module.
■ Precautions when Using Delayed Interrupt Generation Module
• The interrupt processing is restarted at return from interrupt processing without setting the R0 bit in the
delayed interrupt request generate/cancel register (DIRR) to 0 within the interrupt processing routine.
• Unlike software interrupts, interrupts in the delayed interrupt generation module are delayed.
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CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.6 Program Example of Delayed Interrupt Generation Module
11.6
MB90495G Series
Program Example of Delayed Interrupt Generation Module
This section gives a program example of the delayed interrupt generation module.
■ Program Example of Delayed Interrupt Generation Module
● Processing specifications
The main program writes 1 to the R0 bit in the delayed interrupt request generate/cancel register (DIRR),
generates a delayed interrupt request, and changes the task.
● Coding example
ICR15
EQU 0000BFH
; Interrupt control register
DIRR
EQU 00009FH
; Delayed interrupt request generate/cancel register
DIRR_R0 EQU DIRR:0
; Delayed interrupt request generate bit
;-----Main program--------------------------------------------------------------CODE
CSEG
START:
; Stack pointer (SP) already initialized
AND CCR,#0BFH
; Interrupt disabled
MOV I:ICR15,#00H
; Interrupt level 0 (highest)
MOV ILM,#07H
; ILM in PS set to level 7
CCR, #40H
; Interrupt enabled
SETB I:DIRR_R0
; Delayed interrupt request generated
LOOP
MOV A,#00H
; Infinite loop
MOV A,#01H
BRA LOOP
;-----Interrupt program---------------------------------------------------------WARI:
CLRB I:DIRR_R0
; Interrupt request flag cleared
:
;
Processing by user
;
:
RETI
; Return from interrupt
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG 00FF54H
; Vector set to interrupt #42 (2AH)
DSL WARI
ORG 0FFDCH
; Reset vector set
DSL START
DB
00H
; Set to single-chip mode
VECT
ENDS
END START
364
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 12
DTP/EXTERNAL INTERRUPT
This chapter explains the functions and operations of
DTP/external interrupt.
12.1 Overview of DTP/External Interrupt
12.2 Block Diagram of DTP/External Interrupt
12.3 Configuration of DTP/External Interrupt
12.4 Explanation of Operation of DTP/External Interrupt
12.5 Precautions when Using DTP/External Interrupt
12.6 Program Example of DTP/External Interrupt Function
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CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.1 Overview of DTP/External Interrupt
12.1
MB90495G Series
Overview of DTP/External Interrupt
The DTP/external interrupt sends interrupt requests from external peripheral devices or
data transfer requests to the CPU to generate an external interrupt request, or starts the
(EI2OS).
■ DTP/External Interrupt Function
The DTP/external interrupt follows the same procedure as resource interrupts to send interrupt requests
from external peripheral devices to the CPU to generate an external interrupt request, or starts the (EI2OS).
If the (EI2OS) is disabled in the interrupt control register (ICR:ISE = 0), the external interrupt function is
enabled, branching to interrupt processing.
If the EI2OS is enabled (ICR:ISE = 1), the DTP function is enabled and automatic data transfer is
performed, branching to interrupt processing after the completion of data transfer for the specified number
of times.
Table 12.1-1 shows an overview of the DTP/external interrupt.
Table 12.1-1 Overview of DTP/External Interrupt
External Interrupt
Input pin
DTP Function
8 pins (INT0 to INT7)
The interrupt factor is set in unit of pins using the detection level setting registers.
Interrupt factor
Input of High level, Low level,
rising edge, or falling edge
Interrupt number
#15 (0FH), #20 (14H), #24 (18H), #27 (1BH)
Interrupt control
The interrupt request output is enabled/disabled using the DTP/external interrupt enable register
(ENIR).
Interrupt flag
The interrupt factor is held using the DTP/external interrupt factor register (EIRR)
Processing selection
The EI2OS is disabled.
(ICR:ISE=0)
The EI2OS is enabled.
(ICR:ISE=0)
Processing contents
A branch is caused to the external interrupt
processing routine.
EI2OS performs auto data transfer and
completes the specified number of timer for
data transfers, causing a branch to the interrupt
processing.
366
Input of High level or Low level
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.2 Block Diagram of DTP/External Interrupt
MB90495G Series
12.2
Block Diagram of DTP/External Interrupt
The block diagram of the DTP/external interrupt is shown below.
■ Block Diagram of DTP/External Interrupt
Figure 12.2-1 Block Diagram of DTP/External Interrupt
Detection level setting register (ELVR)
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4
Level edge
selector
Pin
INT7
Internal data bus
INT6
INT5
Pin
Level edge
selector
Pin
Level edge
selector
INT1
Level edge
selector
Pin
Level edge
selector
INT2
Level edge
selector
Pin
Pin
INT3
Level edge
selector
Pin
LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
INT4
Pin
Level edge
selector
INT0
DTP/external interrupt input detector
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
Interrupt
request signal
Interrupt
request signal
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
CM44-10114-7E
DTP/external interrupt
factor register (EIRR)
FUJITSU SEMICONDUCTOR LIMITED
DTP/external interrupt
enable register (ENIR)
367
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.2 Block Diagram of DTP/External Interrupt
MB90495G Series
● DTP/external interrupt input detector
This circuit detects interrupt requests or data transfer requests generated from external peripheral devices.
The interrupt request flag bit corresponding to the pin whose level or edge set by the detection level setting
register (ELVR) is detected is set to 1 (EIRR:ER).
● Detection level setting register (ELVR)
This register sets the level or edge of input signals from external peripheral devices that cause DTP/external
interrupt factors.
● DTP/external interrupt factor register (EIRR)
This register holds DTP/external interrupt factors.
If an enable signal is input to the DTP/external interrupt pin, the corresponding DTP/external interrupt
request flag bit is set to 1.
● DTP/external interrupt enable register (ENIR)
This register enables or disables DTP/external interrupt requests from external peripheral devices.
■ Details of Pins and Interrupt Numbers
Table 12.2-1 shows the pins and interrupt numbers used in the DTP/external interrupt.
Table 12.2-1 Pins and Interrupt Numbers Used by DTP/External Interrupt
368
Pin
Channel
P60
INT0
P61
INT1
P62
INT2
P63
INT3
P24
INT4
P25
INT5
P26
INT6
P27
INT7
FUJITSU SEMICONDUCTOR LIMITED
Interrupt Number
#15 (0FH)
#20 (14H)
#24 (18H)
#27 (1BH)
CM44-10114-7E
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.3 Configuration of DTP/External Interrupt
MB90495G Series
12.3
Configuration of DTP/External Interrupt
This section lists and details the pins, interrupt factors, and registers in the DTP/
external interrupt.
■ Pins of DTP/External Interrupt
The pins used by the DTP/external interrupt serve as general-purpose I/0 ports.
Table 12.3-1 lists the pin functions and the pin setting required for use in the DTP/external interrupt
Table 12.3-1 Pins of DTP/External Interrupt
Pin Name
Pin Function
Pin Settings Required for Use in
DTP/External Interrupt
INT0
INT1
INT2
General-purpose I/O ports, DTP
external interrupt inputs
INT3
Set as input ports in port direction register (DDR)
INT4
INT5
INT6
General-purpose I/O ports, DTP
external interrupt inputs, address
bus outputs
INT7
■ Block Diagram of Pins
See "CHAPTER 4 I/O PORT" for the block diagram of pins.
■ List of Registers and Reset Values in DTP/External Interrupt
Figure 12.3-1 List of Registers and Reset Values in DTP/External Interrupt
bit
DTP/external interrupt factor register (EIRR)
bit
DTP/external interrupt enable register (ENIR)
bit
Detection level setting register: High (ELVR)
bit
Detection level setting register: Low (ELVR)
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
×: Undefined
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CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.3 Configuration of DTP/External Interrupt
MB90495G Series
DTP/External Interrupt Factor Register (EIRR)
12.3.1
The DTP/external interrupt factor register (EIRR) holds DTP/external interrupt factors.
When a valid signal is input to the DTP/external interrupt pin, the corresponding DTP/
external interrupt request flag bit is set to 1.
■ DTP/External Interrupt Factor Register (EIRR)
Figure 12.3-2 DTP/External Interrupt Factor Register (EIRR)
15
14
13
12
11
10
9
8
Reset value
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15 to bit 8
ER7 to ER0
R/W : Read/Write
X
: Undefined
0
1
DTP/external interrupt request flag bits
Read
Write
No DTP/external interrupt input Clears ER bit
DTP/ external interrupt input
No effect
Table 12.3-2 Function of DTP/External Interrupt Factor Register (EIRR)
Bit Name
bit 8 to bit 15
370
Function
ER7 to ER0:
DTP/External interrupt
request flag bits
These bits are set to 1 when the edges or level signals set by the detection
condition select bits in the detection level setting register (ELVR:LB, LA)
are to the DTP/external interrupt pins.
When set to 1: When the DTP/external interrupt request enable bit
(ENIR:EN) is set to 1, an interrupt request is generated to the
corresponding DTP/external interrupt channel.
When set to 0: Cleared
When set to 1: No effect
Note:
Reading by read-modify-write type instructions always returns "1".
If more than one DTP/external interrupt request is enabled (ENIR:EN =
1), clear only the bit in the channel that accepts an interrupt (EIRR:ER =
0). No other bits must be cleared unconditionally.
Reference:
When the (EI2OS) is started, the interrupt request flag bit is automatically
cleared after the completion of data transfer (EIRR:ER = 0)
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.3 Configuration of DTP/External Interrupt
MB90495G Series
12.3.2
DTP/External Interrupt Enable Register (ENIR)
The DTP/external interrupt enable register (ENIR) enables/disables the DTP/external
interrupt request in the external peripheral devices.
■ DTP/External Interrupt Enable Register (ENIR)
Figure 12.3-3 DTP/External Interrupt Enable Register (ENIR)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 to bit 0
EN7 to EN0
0
1
R/W : Read/Write
: Reset value
DTP/external interrupt request enable bits
DTP/external interrupt disable
DTP/external interrupt enable
Table 12.3-3 Functions of DTP/External Interrupt Enable Register (ENIR)
Bit Name
bit 0 to bit 7
Function
EN7 to EN0:
DTP/external interrupt
request enable bits
These bits enable or disable the DTP/external interrupt request to the DTP/
external interrupt channel.
If the DTP/external interrupt request enable bit (ENIR:EN) and the DTP/
external interrupt request flag bit (EIRR:ER) are set to 1, the interrupt request
is generated to the corresponding DTP/external interrupt pin.
Reference:
The state of the DTP/external interrupt pin can be read directly using the
port data register irrespective of the setting of the DTP/external interrupt
request enable bit.
Table 12.3-4 Correspondence between DTP/External Interrupt Pins, DTP/External Interrupt
Request Flag Bits, and DTP/External Interrupt Request Enable Bits
CM44-10114-7E
DTP/External Interrupt Pins
DTP/External Interrupt
Request Flag Bits
DTP/External Interrupt
Request Enable Bits
INT0
ER0
EN0
INT1
ER1
EN1
INT2
ER2
EN2
INT3
ER3
EN3
INT4
ER4
EN4
INT5
ER5
EN5
INT6
ER6
EN6
INT7
ER7
EN7
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371
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.3 Configuration of DTP/External Interrupt
MB90495G Series
Detection Level Setting Register (ELVR) (High)
12.3.3
The detection level setting register (High) sets the levels or edges of input signals that
cause interrupt factors in INT7 to INT4 of the DTP/external interrupt pins.
■ Detection Level Setting Register (ELVR) (High)
Figure 12.3-4 Detection Level Setting Register (ELVR) (High)
15
14
13
12
11
10
9
8
Reset value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15 to bit 8
LB7, LA7
LB6, LA6
LB5, LA5
LB4, LA4
0
0
0
1
1
0
1
1
R/W : Read/Write
: Reset value
Detection condition select bits
Detects Low level
Detects High level
Detects rising edge
Detects falling edge
Table 12.3-5 Functions of Detection Level Setting Register (ELVR) (High)
Bit Name
bit 8 to bit 15
Function
LB7, LA7 to LB4, LA4:
Detection condition
select bits
These bits set the levels or edges of input signals from external peripheral
devices that cause interrupt factors in the DTP/external interrupt pins.
• Two levels or two edges are selectable for external interrupts, and two
levels are selectable for the EI2OS.
Reference:
When the set detection signal is input to the DTP/external interrupt pins,
the DTP/external interrupt request flag bits are set to 1 even if DTP/
external interrupt requests are disabled (ENIR:EN = 0).
Table 12.3-6 Correspondence between Detection Level Setting Register (ELVR) (High) and
Channels
372
DTP/External Interrupt Pin
Bit Name
INT4
LB4, LA4
INT5
LB5, LA5
INT6
LB6, LA6
INT7
LB7, LA7
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.3 Configuration of DTP/External Interrupt
MB90495G Series
12.3.4
Detection Level Setting Register (ELVR) (Low)
The detection level setting register (ELVR) (Low) sets the levels or edges of input
signals that cause interrupt factors in INT3 to INT0 of the DTP/external interrupt pins.
■ Detection Level Setting Register (ELVR) (Low)
Figure 12.3-5 Detection Level Setting Register (ELVR) (Low)
7
6
5
4
3
2
1
0
Reset value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 to bit 0
LB3, LA3
LB2, LA2
LB1, LA1
LB0, LA0
0
0
1
1
R/W : Read/Write
: Reset value
0
1
0
1
Detection condition select bits
Detects Low level
Detects High level
Detects rising edge
Detects falling edge
Table 12.3-7 Functions of Detection Level Setting Register (ELVR) (Low)
Bit Name
bit 0 to bit 7
Function
LB3, LA3 to LB0, LA0:
Detection condition
select bits
These bits set the levels or edges of input signals from external peripheral
devices that cause interrupt factors in the DTP/external interrupt pins.
• Two levels or two edges are selectable for external interrupts, and two
levels are selectable for the EI2OS.
Reference:
When the set detection signal is input to the DTP/external interrupt pins,
the DTP/external interrupt request flag bits are set to 1 even if DTP/
external interrupt requests are disabled (ENIR:EN = 0).
Table 12.3-8 Correspondence between Detection Level Setting Register (ELVR) (Low) and
Channels
CM44-10114-7E
DTP/External Interrupt Pin
Bit Name
INT0
LB0, LA0
INT1
LB1, LA1
INT2
LB2, LA2
INT3
LB3, LA3
FUJITSU SEMICONDUCTOR LIMITED
373
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.4 Explanation of Operation of DTP/External Interrupt
12.4
MB90495G Series
Explanation of Operation of DTP/External Interrupt
The DTP/external interrupt circuit has an external interrupt function and a DTP function.
The setting and operation of each function are explained.
■ Setting of DTP/External Interrupt Circuit
Using the DTP/external interrupt requires, the setting shown in Figure 12.4-1.
Figure 12.4-1 Setting of DTP/External Interrupt
bit 15 14
ICR interrupt
control register
External interrupt
DTP
13
12
11
10
9 bit 8 bit 7 6
5
4
3
2
1 bit 0
ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0 ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0
⎯ ⎯
⎯
⎯
0
1
⎯ ⎯
⎯
⎯
0
1
EIRR/ENIR
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
ELVR
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
DDR port direction
register
⎯:
:
:
0 :
1 :
Set the bit corresponding to pin used for DTP/external interrupt input to 0.
Unused bit
Used bit
Set the bit corresponding to used pin to 1
Set 0
Set 1
● Setting procedure
To use the DTP/external interrupt, set each register by using the following procedure:
1. Set the interrupt request enable bit corresponding to the DTP/external interrupt channel to be used to 0
(ENIR:EN).
2. Use the detection condition select bit corresponding to the DTP/external interrupt pin to be used to set
the edge or level to be detected (ELVR:LA, LB).
3. Set the interrupt request flag bit corresponding to the DTP/external interrupt channel to be used to 0
(EIRR:ER).
4. Set the interrupt request enable bit corresponding to the DTP/external interrupt channel to be used to 1
(ENIR:EN).
• When setting the registers for the DTP/external interrupt, the external interrupt request must be disabled
in advance (ENIR:EN0 = 0).
• When enabling the DTP/external interrupt request (ENIR:EN = 1), the corresponding DTP/external
interrupt request flag bit must be cleared in advance (EIRR:ER = 0). These actions prevent the mistaken
interrupt request from occurring when setting the register.
374
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.4 Explanation of Operation of DTP/External Interrupt
MB90495G Series
● Selecting of DTP or external interrupt function
Whether the DTP function or the external interrupt function is executed depends on the setting of the
EI2OS enable bit in the corresponding interrupt control register (ICR:ISE).
If the ISE bit is set to 1, the EI2OS is enabled and the DTP function is executed.
If the ISE bit is set to 0, the EI2OS is disabled and the external interrupt function is executed.
Notes:
• All interrupt requests assigned to one interrupt control register have the same interrupt levels (IL2 to
IL0).
• If two or more interrupt requests are assigned to one interrupt control register and the EI2OS is used in
one of them, other interrupt requests cannot be used.
■ DTP/External Interrupt Operation
The control bits and the interrupt factors for the DTP/external interrupt are shown in Table 12.4-1.
Table 12.4-1 Control Bits and Interrupt Factors for DTP/External Interrupt
DTP/External Interrupt Circuit
Interrupt request flag bit
EIRR:ER7 to ER0
Interrupt request enable bit
ENIR:EN7 to EN0
Interrupt factor
Input of valid edge/level to INT7 to INT0 pins
If the interrupt request signal from the DTP/external interrupt is output to the interrupt controller and the
EI2OS enable bit in the interrupt control register (ICR:ISE) is set to 0, the interrupt processing is executed.
This bit is set to 1, the EI2OS is executed.
Figure 12.4-2 shows the operation of the DTP/external interrupt.
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CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.4 Explanation of Operation of DTP/External Interrupt
MB90495G Series
Figure 12.4-2 Operation of DTP/External Interrupt
DTP/external
interrupt circuit
Other request Interrupt controller
CPU
ELVR
ICR YY
EIRR
IL
CMP
CMP
ICR XX
ENIR
ILM
Interrupt
processing
Factor
EI2OS starts
DTP/external interrupt
request generated
Transfer data between
memory and resource
Update descriptor
Acceptance determined
by interrupt controller
Descriptor
data counter
Interrupt acceptance
determined by CPU
=0
Interrupt processing
≠0
Reset or stop
Return from DTP processing
Start interrupt
processing microprogram
Return from EI2OS
processing (DTP processing)
1
ICR : ISE
0
Start external interrupt
Clear processing and interrupt flag
Return from external interrupt
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CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.4 Explanation of Operation of DTP/External Interrupt
MB90495G Series
12.4.1
External Interrupt Function
The DTP/external interrupt has an external interrupt function for generating an interrupt
request by detecting the signal (edge or level) in the DTP/external interrupt pin.
■ External Interrupt Function
• When the signal (edge or level) set in the detection level setting register is detected in the DTP/external
interrupt pin, the interrupt request flag bit in the DTP/external interrupt factor register (EIRR:ER) is set
to 1.
• If the interrupt request enable bit in the DTP/external interrupt enable register is enabled (ENIR:EN = 1)
with the interrupt request flag bit set to 1, the interrupt request generation is posted to the interrupt
controller.
• If an interrupt request is preferred to other interrupt request by the interrupt controller the interrupt
request is generated.
• If the level of an interrupt request (ICR:IL) is higher than that of the interrupt level mask bit in the
condition code register (CCR:ILM) and the interrupt enable bit is enabled (PS:CCR:I = 1), the CPU
performs interrupt processing after completion of the current instruction execution and branches to
interrupt processing.
• At interrupt processing, set the corresponding DTP/external interrupt request flag bit to 0 and clear the
DTP/external interrupt request.
Notes:
CM44-10114-7E
• When the DTP/external interrupt start factor is generated, the DTP/external interrupt request flag bit
(EIRR:ER) is set to 1, regardless of the setting of the DTP/external interrupt request enable bit
(ENIR:EN).
• When the interrupt processing is started, clear the DTP/external interrupt request flag bit that caused
the start factor. Control cannot be returned from the interrupt while the DTP/external interrupt request
flag bit is set to 1. When clearing, do not clear any flag bit other than the accepted DTP/external
interrupt factor.
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CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.4 Explanation of Operation of DTP/External Interrupt
12.4.2
MB90495G Series
DTP Function
The DTP/external interrupt has the DTP function that detects the signal of the external
peripheral device from the DTP/external interrupt pin to start the EI2OS.
■ DTP Function
The DTP function detects the signal level set by the detection level setting register of the DTP/external
interrupt function to start the EI2OS.
• When the EI2OS operation is already enabled (ICR:ISE = 1) at the point when the interrupt request is
accepted by the CPU, the DTP function starts the EI2OS and starts data transfer.
• When transfer of one data item is completed, the descriptor is updated and the DTP/external interrupt
request flag bit is cleared to prepare for the next request from the DTP/external interrupt pin.
• When the EI2OS completes transfer of all the data, control branches to the interrupt processing.
Figure 12.4-3 Example of Interface with External Peripheral Device (in single chip mode)
High level request (ELVR : LB0, LA0 = 01B)
Input to INT0 pin
(DTP factor)
Internal operation of CPU
Descriptor
selected/read
Peripheral
device
externalconnected
Internal data bus
Read/Write
operation*2
DTP factor*1
Data transfer
request
Descriptor
updated
Interrupt
INT DTP/external request
interrupt circuit
CPU
(EI2OS)
Internal
memory
*1: This must be cancelled within three machine clocks after the start of data transfer.
*2: When EI2OS is "peripheral function → internal memory transfer".
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CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.5 Precautions when Using DTP/External Interrupt
MB90495G Series
12.5
Precautions when Using DTP/External Interrupt
This section explains the precautions when using the DTP/external interrupt.
■ Precautions when Using DTP/External Interrupt Circuit
● Condition of external-connected peripheral device when DTP function is used
• When using the DTP function, the peripheral device must automatically clear a data transfer request
when data transfer is performed.
• Inactivate the transfer request signal within three machine clocks after starting data transfer. If the
transfer request signal remains active, the DTP/external interrupt regards the transfer request signal as a
generation of next transfer request.
● External interrupt input polarity
• When the edge detection is set in the detection level setting register, the pulse width for edge detection
must be at least three machine clocks.
• When a level causing an interrupt factor is input with level detection set in the detection level setting
register, Interrupt request flag bit (EIRR:ER) in the DTP/external interrupt factor register is set to 1 and
the factor is held as shown in Figure 12.5-1.
With the factor held in Interrupt request flag bit (EIRR:ER), the request to the interrupt controller remains
active if the interrupt request is enabled (ENIR:EN = 1) even after the DTP/external interrupt factor is
cancelled. To cancel the request to the interrupt controller, clear the external interrupt request flag bit
(EIRR:ER) and clear the factor FF as shown in Figure 12.5-2.
Figure 12.5-1 Clearing interrupt request flag bit (EIRR:ER) when Level Set
DTP/external
interrupt factor
DTP/interrupt input
detector
Interrupt request flag bit
(EIRR:ER)
Enable gate
To interrupt
controller
(interrupt request)
The factor remains held unless cleared.
Figure 12.5-2 DTP/External Interrupt Factor and Interrupt Request Generated when Interrupt Request
Enabled
DTP/external interrupt factor
(when High level detected)
Interrupt factor cancelled
Interrupt request issued
to interrupt controller
The interrupt request is inactived by clearing
the interrupt request flag bit (EIRR:ER).
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CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.5 Precautions when Using DTP/External Interrupt
MB90495G Series
● Precautions on interrupts
• When the DTP/external interrupt is used as the external interrupt function, no return from interrupt
processing can be made with the DTP/external interrupt request flag bit set to 1 (EIRR:ER) and the
DTP/external interrupt request set to "enabled" (ENIR:EN = 1). Always set the DTP/external interrupt
request flag bit to 0 (EIRR:ER) at interrupt processing.
• When the level detection is set in the detection level setting register and the level that becomes the
interrupt factor remains input, the external interrupt request flag bit is reset immediately even when
cleared (EIRR:ER = 0). Disable the DTP/external interrupt request output as needed (ENIR:EN = 0), or
cancel the interrupt factor itself.
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12.6
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.6 Program Example of DTP/External Interrupt Function
Program Example of DTP/External Interrupt Function
This section gives a program example of the DTP/external interrupt function.
■ Program Example of DTP/External Interrupt Function
● Processing specifications
An external interrupt is generated by detecting the rising edge of the pulse input to the INT0 pin.
● Coding example
ICR02
EQU 0000B2H
; DTP/external interrupt control register
DDR6
EQU 000016H
; Port 6 direction register
ENIR
EQU 000030H
; DTP/external interrupt enable register
EIRR
EQU 000031H
; DTP/external interrupt factor register
ELVRL
EQU 000032H
; Detection level setting register: L
ELVRH
EQU 000033H
; Detection level setting register: H
ER0
EQU EIRR:0
; INT0 Interrupt request flag bit
EN0
EQU ENIR:0
; INT0 Interrupt request enable bit
;
;-----Main program--------------------------------------------------------------CODE
CSEG
START:
; Stack pointer (SP) already initialized
MOV I:DDR6,#00000000B ; DDR6 set to input port
AND CCR,#0BFH
; Interrupts disabled
MOVA I:ICR02,#00H
; Interrupt level 0 (highest)
CLRB I:ER0
; INT0 disabled using ENIR
MOV I:ELVRL,#00000010B ; Rising edge selected for INT0
CLRB I:ER0
; INT0 interrupt factor
; cleared using EIRR
SETB I:EN0
; INT0 interrupt request enabled using ENIR
MOV ILM, #07H
; ILM in PS set to level 7
OR
CCR, #40H
; Interrupts enabled
LOOP:
:
Processing by user
:
BRA LOOP
;-----Interrupt program---------------------------------------------------------WARI:
CLRB I:ER0
; Interrupt request flag cleared
:
Processing by user
:
RETI
; Return from interrupt
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG 00FFC0H
; Vector set to interrupt number #15 (0FH)
DSL WARI
ORG 00FFDCH
; Reset vector set
DSL START
DB
00H
; Set to single-chip mode
VECT
ENDS
END START
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CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.6 Program Example of DTP/External Interrupt Function
MB90495G Series
■ Program Example of DTP Function
● Processing specification
• Channel 0 of the EI2OS is started by detecting the High level of the signal input to the INT0 pin.
• RAM data is output to port 0 by performing DTP processing (EI2OS).
● Coding example
ICR02
EQU 0000B2H
; DTP/external interrupt control register
DDR0
EQU 000010H
; Port 0 direction register
DDR6
EQU 000011H
; Port 6 direction register
ENIR
EQU 000030H
; DTP/external interrupt enable register
EIRR
EQU 000031H
; DTP/external interrupt factor register
ELVRL
EQU 000032H
; Detection level setting register: L
ELVRH
EQU 000033H
; Detection level setting register: H
ER0
EQU EIRR:0
; INT0 interrupt request flag bit
EN0
EQU ENIR:0
; INT0 interrupt request enable bit
;
BAPL
EQU 000100H
; Buffer address pointer lower
BAPM
EQU 000101H
; Buffer address pointer middle
BAPH
EQU 000102H
; Buffer address pointer higher
ISCS
EQU 000103H
; EI2OS status register
IOAL
EQU 000104H
; I/O address register lower
IOAH
EQU 000105H
; I/O address register higher
DCTL
EQU 000106H
; Data counter lower
DCTH
EQU 000107H
; Data counter higher
;
;-----Main program--------------------------------------------------------------CODE
CSEG
START:
; Stack pointer (SP) already initialized
MOV I:DDR0,#11111111B ; DDR0 set to output port
MOV I:DDR6,#00000000B ; DDR6 set to input port
AND CCR,#0BFH
; Interrupts disabled
MOV I:ICR02,#08H
; Interrupt level 0 (highest) EI2OS
; Channel 0
;
; Deta bank register (DTB) = 00H
;
MOV BAPL,#00H
; Address for storing output data set
MOV BAPM,#06H
; (600H to 60AH used)
MOV BAPH,#00H
MOV ISCS,#12H
; Byte transfer, buffer address + 1
; I/O address fixed,
; transfer from memory to I/O
MOV IOAL,#00H
; Port 0 (PDR0) set as
MOV IOAH,#00H
; transfer destination address pointer
MOV DCTL,#0AH
; Transfer count set to 10
MOV DCTH,#00H
;
CLRB I:EN0
; INT0 disabled using ENIR
MOV I:ELVR,#00000001B ; H level detection set for INT0
CLRB I:ER0
; INT0 interrupt request flag cleared using EIRR
SETB I:EN0
; INT0 interrupt request enabled using ENIR
MOV ILM,#07H
; ILM in PS set to level 7
OR
CCR,#40H
; Interrupts enabled
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CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.6 Program Example of DTP/External Interrupt Function
LOOP:
:
Processing by user
:
BRA
LOOP
;-----Interrupt program---------------------------------------------------------WARI:
CLRB
I:ER0
; INTO interrupt request flag cleared
:
Processing by user
:
RETI
; Return from interrupt
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS = 0FFH
ORG 00FFC0H
; Vector set to interrupt number #15 (0FH)
DSL WARI
ORG 00FFDCH
; Reset vector set
DSL START
DB
00H
; Set to single-chip mode set
VECT
ENDS
END START
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CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.6 Program Example of DTP/External Interrupt Function
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CM44-10114-7E
CHAPTER 13
8-/10-BIT A/D CONVERTER
This chapter explains the functions and operation of 8-/
10-bit A/D converter.
13.1 Overview of 8-/10-bit A/D Converter
13.2 Block Diagram of 8-/10-bit A/D Converter
13.3 Configuration of 8-/10-bit A/D Converter
13.4 Interrupt of 8-/10-bit A/D Converter
13.5 Explanation of Operation of 8-/10-bit A/D Converter
13.6 Precautions when Using 8-/10-bit A/D Converter
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CHAPTER 13 8-/10-BIT A/D CONVERTER
13.1 Overview of 8-/10-bit A/D Converter
13.1
MB90495G Series
Overview of 8-/10-bit A/D Converter
The 8-/10-bit A/D converter converts the analog input voltage to a 8- or 10-bit digital
value by using the RC sequential-comparison converter system.
• An input signal can be selected from the input signals of the analog input pins for 8
channels.
• The start trigger can be selected from a software trigger, internal timer output, and an
external trigger.
■ Function of 8-/10-bit A/D Converter
The 8-/10-bit A/D converter converts the analog voltage (input voltage) input to the analog input pin into
an 8- or 10-bit digital value (A/D conversion).
The 8-/10-bit A/D converter has the following functions:
• A/D conversion time is a minimum of 6.12 μs*per channel including sampling time.
• Sampling time is a minimum of 2.0 μs per channel.*
• RC sequential-comparison converter system with sample & hold circuit
• Setting of 8-bit or 10-bit resolution enabled
• Analog input pin can be used up to 8 channels.
• Generates interrupt request by storing A/D conversion results in A/D data register
• Starts EI2OS if interrupt request generated. Use of the EI2OS prevents data loss even at continuous
conversion.
• Selects start trigger from software trigger, internal timer output, and external trigger (falling edge)
*: When the machine clock operates at 16 MHz
■ Conversion Modes of 8-/10-bit A/D Converter
There are conversion modes of 8-/10-bit A/D converter as shown below:
Table 13.1-1 Conversion Modes of 8-/10-bit A/D Converter
Conversion
Mode
386
Description
Single-shot
conversion mode
A/D conversion is performed sequentially from the start channel to the end
channel. When A/D conversion for the end channel is terminated, it stops.
Continuous
conversion mode
A/D conversion is performed sequentially from the start channel to the end
channel. When A/D conversion for the end channel is terminated, it is continued
after returning to the start channel.
Pause-conversion
mode
A/D conversion is performed sequentially from the start channel to the end
channel. When A/D conversion for the end channel is terminated, A/D conversion
and pause are repeated after returning to the start channel.
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CHAPTER 13 8-/10-BIT A/D CONVERTER
13.2 Block Diagram of 8-/10-bit A/D Converter
MB90495G Series
13.2
Block Diagram of 8-/10-bit A/D Converter
The 8-/10-bit A/D converter consists of following blocks.
■ Block Diagram of 8-/10-bit A/D Converter
Figure 13.2-1 Block Diagram of 8-/10-bit A/D Converter
A/D control
Interrupt request output
status register
(ADCS)
BUSY INT INTE PAUS STS1 STS0 STRT Reserved MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
2
2
Start selector
Decoder
Internal data bus
ADTG
TO
6
φ
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Sample & hold
circuit
Comparator
Controller
Analog
channel
selector
AVR
AVcc
AVss
D/A converter
2
2
A/D data
register
(ADCR) S10 ST1 ST0 CT1 CT0 ⎯
TO
:
⎯
:
Reserved :
φ
:
CM44-10114-7E
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Internal timer output
Unused
Always set to 0
Machine clock
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CHAPTER 13 8-/10-BIT A/D CONVERTER
13.2 Block Diagram of 8-/10-bit A/D Converter
MB90495G Series
● Details of pins in block diagram
Table 13.2-1 shows the actual pin names and interrupt request numbers of the 8-/10-bit A/D converter
Table 13.2-1 Pins and Interrupt Request Numbers in Block Diagram
Pin Name/Interrupt Request Number in Block
Diagram
Actual Pin Name/Interrupt Request
Number
ADTG
Trigger input pin
P37/ADTG
TO
Internal timer output
TO (16-bit reload timer, 16-bit free-run timer)
AN0
Analog input pin ch 0
P50/AN0
AN1
Analog input pin ch 1
P51/AN1
AN2
Analog input pin ch 2
P52/AN2
AN3
Analog input pin ch 3
P53/AN3
AN4
Analog input pin ch 4
P54/AN4
AN5
Analog input pin ch 5
P55/AN5
AN6
Analog input pin ch 6
P56/AN6
AN7
Analog input pin ch 7
P57/AN7
AVR
Vref+ Input pin
AVR
AVCC
A/D converter power supply pin
AVCC
AVSS
A/D converter analog GND pin
AVSS
Interrupt
request output
#18 (12H)
● A/D control status registers (ADCS)
This register starts the A/D conversion function by software, selects the start trigger for the A/D conversion
function, selects the conversion mode, enables or disables an interrupt request, checks and clears the
interrupt request flag, temporarily stops A/D conversion and checks the state during conversion, and sets
the start and end channels for A/D conversion.
● A/D data registers (ADCR)
This register stores the A/D conversion results, and selects the comparison time, sampling time, and
resolution of A/D conversion.
● Start selector
This selector selects the trigger to start A/D conversion. An internal timer output or external pin input can
be set as the start trigger.
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CHAPTER 13 8-/10-BIT A/D CONVERTER
13.2 Block Diagram of 8-/10-bit A/D Converter
● Decoder
This decoder sets the A/D conversion start channel select bits and the A/D conversion end channel select
bits in the A/D control status register (ADCS:ANS2 to ANS0 and ANE2 to ANE0) to select the analog
input pin to be used for A/D conversion.
● Analog channel selector
This selector selects the pin to be used for A/D conversion from the 8-channel analog input pins by
receiving a signal from the decoder.
● Sample & hold circuit
This circuit holds the input voltage selected by the analog channel selector. By holding the input voltage
immediately after A/D conversion is started, A/D conversion is performed without being affected by the
fluctuation of the input voltage during A/D conversion.
● D/A converter
This converter generates the reference voltage which is compared with the input voltage held in the sample
& hold circuit.
● Comparator
This comparator compares the D/A converter output voltage with input voltage held in the sample & hold
circuit to determine the mount of voltage.
● Controller
This circuit determines the A/D conversion value by receiving the signal indicating the amount of voltage
determined by the comparator. When the A/D conversion results are determined, the result data is stored in
the A/D data register. If an interrupt request is enabled, an interrupt is generated.
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CHAPTER 13 8-/10-BIT A/D CONVERTER
13.3 Configuration of 8-/10-bit A/D Converter
13.3
MB90495G Series
Configuration of 8-/10-bit A/D Converter
This section explains the pins, registers, and interrupt factors of the A/D converter.
■ Pins of 8-/10-bit A/D Converter
The pins of the 8-/10-bit A/D converter serve as general-purpose I/O ports. Table 13.3-1 shows the pin
functions and the setting required for use of the 8-/10-bit A/D converter.
Table 13.3-1 Pins of 8-/10-bit A/D Converter
Function
Used
Trigger input
Pin
Name
ADTG
Channel 0
AN0
Channel 1
AN1
Channel 2
AN2
Channel 3
AN3
Channel 4
AN4
Channel 5
AN5
Channel 6
AN6
Channel 7
AN7
Pin Function
Setting Required for Use of
8-/10-bit A/D Converter
General-purpose I/O port,
external trigger input
Set as input port in port direction register
(DDR).
General-purpose I/O ports,
analog inputs
Set as input ports in port direction
register (DDR).
Input of analog signal enabled
(ADER:ADE7 to ADE0 = 11111111B)
See "CHAPTER 4 I/O PORT" for the block diagram of pins.
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CHAPTER 13 8-/10-BIT A/D CONVERTER
13.3 Configuration of 8-/10-bit A/D Converter
MB90495G Series
■ List of Registers and Reset Values of 8-/10-bit A/D Converter
Figure 13.3-1 Register and Reset Value of 8-/10-bit A/D Converter
bit
A/D control status register (High)
(ADCS: H)
bit
A/D control status register (Low)
(ADCS: L)
bit
A/D data register (High)
(ADCR: H)
bit
A/D data register (Low)
(ADCR: L)
bit
Analog input enable register (ADER)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
1
0
1
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
×: Undefined
■ Generation of Interrupt from 8-/10-bit A/D Converter
In the 8-/10-bit A/D converter, when the A/D conversion results are stored in the A/D data register
(ADCR), the interrupt request flag bit in the A/D control status register (ADCS:INT) is set to 1. When an
interrupt request is enabled (ADCS:INTE = 1), an interrupt is generated.
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CHAPTER 13 8-/10-BIT A/D CONVERTER
13.3 Configuration of 8-/10-bit A/D Converter
MB90495G Series
A/D Control Status Register (High) (ADCS:H)
13.3.1
The A/D control status register (High) (ADCS:H) provides the following settings:
• Starting A/D conversion function by software
• Selecting start trigger for A/D conversion
• Storing A/D conversion results in A/D data register to enable or disable interrupt
request
• Storing A/D conversion results in A/D data register to check and clear interrupt
request flag
• Pausing A/D conversion and checking state during conversion
■ A/D Control Status Register (High) (ADCS:H)
Figure 13.3-2 A/D Control Status Register (High) (ADCS:H)
15
14
13
12
11
10
9
8
W
R/W
Reset value
00000000B
R/W R/W R/W R/W R/W R/W
bit 8
Reserved bit
Reserved
0
Always set to "0"
bit 9
A/D conversion software start bit
STRT
0
Does not start A/D conversion
1
Starts A/D conversion
bit 11 bit 10
STS1 STS0
0
0
0
1
1
0
1
1
A/D conversion start trigger select bit
Starts software
Starts software or external trigger
Starts software or internal timer
Starts software, external trigger, or internal timer
bit 12
PAUS
Pause flag bit
(This bit is enabled only when EI2OS is used)
0
A/D conversion does not pause
1
A/D conversion pauses
bit 13
Interrupt request enable bit
INTE
Interrupt
request
disable
0
Interrupt request enable
1
bit 14
INT
0
1
Interrupt request flag bit
Read
A/D conversion not terminated
A/D conversion terminated
Write
Clear to "0"
No effect
bit 15
BUSY
0
R/W : Read/Write
: Reset value
392
1
A/D conversion-on flag bit
Read
Write
A/D conversion terminated (inactive state) Terminates A/D conversion forcibly
A/D conversion in operation No effect
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CM44-10114-7E
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.3 Configuration of 8-/10-bit A/D Converter
MB90495G Series
Table 13.3-2 Function of Each Bit of A/D Control Status Register (High) (ADCS:H)
Bit Name
Function
bit 8
Reserved: Reserved bit
Always set this bit to 0.
bit 9
STRT:
A/D conversion software
start bit
This bits starts the 8-/10-bit A/D converter by software.
When set to 1: Starts 8-/10-bit A/D converter
• If A/D conversion pauses in the pause-conversion mode, it is resumed by writing 1 to
the STRT bit.
When set to 0: Invalid. The state remains unchanged.
Read: The byte/word command reads "1". The read-modify-write series commands read
"0".
Note:
Do not perform forcible termination (BUSY = 0) and software start (STRT = 1) of the
8-/10-bit A/D converter simultaneously.
bit 10
bit 11
STS1, STS0:
A/D conversion start trigger
select bits
These bits select the trigger to start the 8-/10-bit A/D converter.
If two or more start triggers are set (STS1, STS0 ≠ "00B"), the 8-/10-bit A/D converter is
started by the first-generated start trigger.
Note:
Start trigger setting should be changed when the operation of resource generating a
start trigger is stopped.
bit 12
PAUS:
Pause flag bit
This bit indicates the A/D conversion operating state when the EI2OS function is used.
• The PAUS bit is enabled only when the EI2OS function is used.
• A/D conversion pauses while the A/D conversion results are transferred from the A/D
data register (ADCR) to memory. When A/D conversion pauses, the PAUS bit is set to
1.
• After transfer of the A/D conversion results to memory, the 8-/10-bit A/D converter
automatically resumes A/D conversion. When A/D conversion is started, the PAUS bit
is cleared to 0.
bit 13
INTE:
Interrupt request enable bit
This bit enables or disables output of an interrupt request.
• When the interrupt request flag bit is set with an interrupt request enabled (INTE = 1),
an interrupt request is generated.
Note:
Always set this bit to 1 when the EI2OS function is used.
bit 14
INT:
Interrupt request flag bit
This bit indicates that an interrupt request is generated.
• When A/D conversion is terminated and its results are stored in the A/D data register
(ADCR), the INT bit is set to 1.
• When the interrupt request flag bit is set (INT = 1) with an interrupt request enabled
(INTE = 1), an interrupt request is generated.
When set to 0: Cleared
When set to 1: No effect
When EI2OS function started: Cleared
Note:
To clear the INT bit, write 0 when the 8-/10-bit A/D converter is stopped.
bit 15
BUSY:
A/D conversion-on flag bit
This bit forcibly terminates the 8-/10-bit A/D converter. When read, this bit indicates
whether the 8-/10-bit A/D converter is operating or stopped.
When set to 0: Forcibly terminates 8-/10-bit A/D converter
When set to 1: No effect
Read: 1 is read when the 8-/10-bit A/D converter is operating and 0 is written when the
converter is stopped.
Note:
Do not perform forcibly termination and software start of the 8-/10-bit A/D converter
simultaneously.
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CHAPTER 13 8-/10-BIT A/D CONVERTER
13.3 Configuration of 8-/10-bit A/D Converter
MB90495G Series
A/D Control Status Register (Low) (ADCS:L)
13.3.2
The A/D control status register (Low) (ADCS:L) provides the following settings:
• Selecting A/D conversion mode
• Selecting start channel and end channel of A/D conversion
■ A/D Control Status Register (Low) (ADCS:L)
Figure 13.3-3 A/D Control Status Register Low (ADCS:L)
7
6
5
4
3
2
1
0
Reset value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 2 bit 1 bit 0
ANE2 ANE1 ANE0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
0
1
1
1
0
1
1
1
1
A/D conversion end channel select bits
AN0 pin
AN1 pin
AN2 pin
AN3 pin
AN4 pin
AN5 pin
AN6 pin
AN7 pin
bit 5 bit 4 bit 3
A/D conversion start channel select bits
ANS2 ANS1 ANS0
0
0
0
0
1
1
1
1
R/W : Read/Write
: Reset value
394
0
0
1
1
0
0
1
1
bit 7 bit 6
MD1 MD0
0
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
Read during
Read during a pause in stop
a conversion conversion mode
Inactive state
AN0 pin
AN1 pin
AN2 pin
AN3 pin
AN4 pin
AN5 pin
AN6 pin
AN7 pin
Channel number Channel number
currently being just previously
converted
converted
A/D conversion mode select bits
Single-shot conversion mode 1 (restartable during conversion)
Single-shot conversion mode 2 (not-restartable during conversion)
Continuous conversion mode (not-restartable during conversion)
Pause-conversion mode (not-restartable during conversion)
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CM44-10114-7E
MB90495G Series
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.3 Configuration of 8-/10-bit A/D Converter
Table 13.3-3 Function of Each Bit of A/D Control Status Register (Low) (ADCS:L) (1 / 2)
Bit Name
Function
bit 0 to bit 2
ANE2 to ANE0:
A/D conversion end
channel select bits
These bits set the channel at which A/D conversion terminated.
Start channel < end channel:
A/D conversion starts at channel set by A/D conversion start channel select
bits (ANS2 to ANS0) and terminates channel set by A/D conversion end
channel select bits (ANE2 to ANE0)
Start channel = end channel:
A/D conversion is performed only for one channel set by A/D converter end (=
start) channel select bits (ANE2 to ANE0 = ANS2 to ANS0).
Start channel > end channel:
A/D conversion is performed from channel set by A/D conversion start
channel select bits (ANS2 to ANS0) to AN7, and from AN0 to channel set by
A/D conversion end channel select bits (ANE2 to ANE0).
Continuous conversion mode and pause-conversion mode:
When A/D conversion terminated at the channel set by the A/D conversion end
channel select bits (ANE2 to ANE0), it returns to the channel set by the A/D
conversion start channel select bits (ANS2 to ANS0).
Note:
Do not set the A/D conversion end channel select bits (ANE2 to ANE0)
during A/D conversion.
bit 3 to bit 5
ANS2 to ANS0:
A/D conversion start
channel select bits
These bits set the channel at which A/D conversion start. At read, the channel
number under A/D conversion or A/D-converted immediately before A/D
conversion pauses can be checked. And before A/D conversion starts, the
previous conversion channel will be read even if these bits have already been set
to the new value. These bits are initialized to "000B" at reset.
Start channel < end channel:
A/D conversion starts at channel set by A/D conversion start channel select
bits (ANS2 to ANS0) and terminates at channel set by A/D conversion end
channel select bits (ANE2 to ANE0)
Start channel = end channel:
A/D conversion is performed only for one channel set by A/D conversion (=
end) channel select bits (ANS2 to ANS0 = ANE2 to ANE0)
Start channel > end channel:
A/D conversion performed from channel set by A/D conversion start channel
select bits (ANS2 to ANS0) to AN7, and from AN0 to channel set by A/D
conversion end channel select bits (ANE2 to ANE0)
Continuous conversion mode and pause-conversion mode:
When A/D conversion terminates at the channel set by the A/D conversion end
channel select bits (ANE2 to ANE0), it returns to the channel set by the A/D
conversion start channel select bits (ANS2 to ANS0).
Read (During A/D conversion):
The channel numbers (7 to 0) under A/D conversion are read.
Read (During pause-conversion mode and temporary stop):
At read during a pause, the channel number A/D-converted immediately
before a pause is read.
Note:
Do not set the A/D conversion start channel bits (ANS2 to ANS0) during A/D
conversion.
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CHAPTER 13 8-/10-BIT A/D CONVERTER
13.3 Configuration of 8-/10-bit A/D Converter
MB90495G Series
Table 13.3-3 Function of Each Bit of A/D Control Status Register (Low) (ADCS:L) (2 / 2)
Bit Name
bit 6
bit 7
396
MD1, MD0:
A/D conversion
mode select bits
Function
These bits set the A/D conversion mode.
Single-shot conversion mode 1:
• The analog inputs from the start channel (ADCS:ANS2 to ANS0) to the end
channel (ADCS:ANE2 to ANE0) are A/D-converted continuously.
• The A/D conversion pauses after A/D conversion for the end channel.
• This mode can be restarted during A/D conversion.
Single-shot conversion mode 2:
• The analog inputs from the start channel (ADCS:ANS2 to ANS0) to the end
channel (ADCS:ANE2 to ANE0) are A/D-converted continuously.
• The A/D conversion after A/D conversion for the end channel.
• This mode cannot be restarted during A/D conversion.
Continuous conversion mode:
• The analog inputs from the start channel (ADCS:ANS2 to ANS0) to the end
channel (ADCS:ANE2 to ANE0) are A/D-converted continuously.
• When A/D conversion for the end channel is terminated, it is continued after
returning to the analog input for the start channel.
• To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag
bit in the A/D control status register (ADCS:BUSY).
• This mode cannot be restarted during A/D conversion.
Pause conversion mode:
• A/D conversion for the start channel (ADCS:ANS2 to ANS0) starts. The A/D
conversion pauses at termination of A/D conversion for a channel. When the
start trigger is input while A/D conversion pauses, A/D conversion for the
next channel is started.
• The A/D conversion pauses at the termination of A/D conversion for the end
channel. When the start trigger is input while A/D conversion pauses, A/D
conversion is continued after returning to the analog input for the start
channel.
• To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag
bit in the A/D control status register (ADCS:BUSY).
• This mode cannot be restarted during A/D conversion.
Note:
When the conversion mode is set to "not restartable" (MD1, MD0 ≠ "00B"), it
cannot be restarted with any start triggers (software trigger, internal timer,
and external trigger) during A/D conversion.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.3 Configuration of 8-/10-bit A/D Converter
MB90495G Series
13.3.3
A/D Data Register (High) (ADCR:H)
The higher five bits in the A/D data register (ADCR:H) select the compare time, sampling
time and resolution of A/D conversion.
Bits 9 and 8 in the A/D data register (ADCR) are explained in Section 13.3.4 "A/D Data
Register (Low) (ADCR:L)".
■ A/D Data Register (High) (ADCR:H)
Figure 13.3-4 A/D Data Register (High) (ADCR:H)
15
W
14
W
13
W
12
W
11
W
10
⎯
9
8
*
*
R
R
Reset value
00101XXX B
bit 12 bit 11
CT1 CT0
0
0
1
0
0
1
1
1
bit 14 bit 13
ST1 ST0
0
0
1
1
R
W
X
⎯
φ
CM44-10114-7E
:
:
:
:
:
:
Read only
Write only
Undefined
Unused
Machine clock
Reset value
0
1
0
1
Compare time select bits
44/φ (5.5 μs)*1
66/φ (4.12 μs)*2
88/φ (5.5 μs)*2
176/φ (11.0 μs)*2
Sampling time select bits
20/φ (2.5 μs)*1
32/φ (2.0 μs)*2
48/φ (3.0 μs)*2
128/φ (8.0 μs)*2
bit 15
Resolution select bits
S10
10 bits (D9 to D0)
0
8 bits (D7 to D0)
1
*1 : The parenthesized values are provided when the machine clock operates at 8-MHz.
*2 : The parenthesized values are provided when the machine clock operates at 16-MHz.
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CHAPTER 13 8-/10-BIT A/D CONVERTER
13.3 Configuration of 8-/10-bit A/D Converter
MB90495G Series
Table 13.3-4 Functions of A/D Data Register (High) (ADCR:H)
Bit Name
398
Function
bit 11
bit 12
CT1, CT0:
Compare time select bits
These bits set the A/D conversion compare time.
• These bits set the time required from when analog input is A/D-converted
until it is stored in the data bits (D9 to D0).
Note:
• The setting of CT1 and CT0 = "00B" is based on operation at 8 MHz.
Setting based on operation at 16 MHz does not assure normal operation.
When these bits are read, "00B" is read.
• Analog voltage may not be captured correctly if disallowed setting is
initiated.
bit 13
bit 14
ST1, ST0:
Sampling time select bits
These bits set the A/D conversion sampling time.
• These bits set the time required from when A/D conversion starts until the
input analog voltage is sampled and held by the sample & hold circuit.
Note:
• The setting of ST1 and ST0 = "00B" is based on operation at 8 MHz.
Setting based on operation at 16 MHz does not assure normal operation.
When these bits are read, "00B" is read.
• Analog voltage may not be captured correctly if disallowed setting is
initiated.
• Do not set the sampling time during A/D conversion.
bit 15
S10:
Resolution select bit
This bit selects the A/D conversion resolution.
When set to 0: Sets A/D conversion resolution in 10 bits from A/D conversion
data bits D9 to D0
When set to 1: Sets A/D conversion resolution in 8 bits from A/D conversion
data bits D7 to D0
Note:
Change the S10 bit in the pausing state before starting A/D conversion.
Changing the S10 bit after A/D conversion starts disables the A/D conversion
results stored in the A/D conversion data bits (D9 to D0).
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CM44-10114-7E
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.3 Configuration of 8-/10-bit A/D Converter
MB90495G Series
13.3.4
A/D Data Register (Low) (ADCR:L)
The A/D data register (Low) (ADCR:L) stores the A/D conversion results.
Bits 8 and 9 in the A/D data register (ADCR) in this section.
■ A/D Data Register (Low) (ADCR:L)
Figure 13.3-5 A/D Data Register Low (ADCR:L)
bit 9
8
7
6
5
4
3
2
1
0
Reset value
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXX B
R
R
R
R
R
R
R
R
R
R
R: Read only
X: Undefined
Table 13.3-5 Functions of A/D Data Register (Low) (ADCR:L)
Bit Name
bit 0 to bit 9
CM44-10114-7E
Function
D9 to D0:
A/D conversion data bits
These bits store the A/D conversion results.
When resolution set in 10 bits (S10 = 0):
Conversion data is stored in the 10 bits from D9 to D0.
When resolution set in 8 bits:
Conversion data is stored in the 8 bits from D7 to D0.
Note:
Use a word instruction (MOVW) to read the A/D conversion results
stored in the A/D conversion data bits (D9 to D0).
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CHAPTER 13 8-/10-BIT A/D CONVERTER
13.3 Configuration of 8-/10-bit A/D Converter
13.3.5
MB90495G Series
Analog Input Enable Register (ADER)
The analog input enable register (ADER) enables or disables the analog input pins to be
used in the 8-/10-bit A/D converter.
■ Analog Input Enable Register (ADER)
Figure 13.3-6 Analog Input Enable Register (ADER)
7
6
5
4
3
2
1
0
Reset value
11111111 B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
Analog input enable bit 0 (AN0)
ANE0
Analog input disable
0
Analog input enable
1
bit 1
Analog input enable bit 1 (AN1)
ANE1
Analog input disable
0
Analog input enable
1
bit 2
Analog input enable bit 2 (AN2)
ANE2
Analog input disable
0
Analog input enable
1
bit 3
Analog input enable bit 3 (AN3)
ANE3
Analog input disable
0
Analog input enable
1
bit 4
Analog input enable bit 4 (AN4)
ANE4
Analog input disable
0
Analog input enable
1
bit 5
Analog input enable bit 5 (AN5)
ANE5
Analog input disable
0
Analog input enable
1
bit 6
Analog input enable bit 6 (AN6)
ANE6
Analog
input
disable
0
Analog
input
enable
1
R/W : Read/Write
: Reset value
400
bit 7
Analog input enable bit 7 (AN7)
ANE7
Analog input disable
0
Analog input enable
1
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CM44-10114-7E
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.3 Configuration of 8-/10-bit A/D Converter
MB90495G Series
Table 13.3-6 Functions of Analog Input Enable Register (ADER)
Bit Name
bit 0 to bit 7
Notes:
CM44-10114-7E
Function
ADE7 to ADE0:
Analog input enable bits
These bits enable or disable the analog input of the pin to be used for A/D
conversion.
When set to 0: Disables analog input
When set to 1: Enables analog input
• The analog input pins serve as a general-purpose I/O port of the port 5. When using the pin as an
analog input pin, switch the pin to analog input pin according to the setting of the port 5 direction
register (DDR5) and the analog input enable register (ADER).
• When using the pin as an analog input pin, write 0 to the bit in the port 5 direction register (DDR5)
corresponding to the pin to be used and turn off the output transistor. Also write 1 to the bit in the
analog input enable register (ADER) corresponding to the pin to be used and set the pin to analog
input.
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CHAPTER 13 8-/10-BIT A/D CONVERTER
13.4 Interrupt of 8-/10-bit A/D Converter
13.4
MB90495G Series
Interrupt of 8-/10-bit A/D Converter
When A/D conversion is terminated and its results are stored in the A/D data register
(ADCR), the 8-/10-bit A/D converter generates an interrupt request. The EI2OS function
can be used.
■ Interrupt of A/D Converter
When A/D conversion of the analog input voltage is terminated and its results are stored in the A/D data
register (ADCR), the interrupt request flag bit in the A/D control status register (ADCS:INT) is set to 1.
When the interrupt request flag bit is set to 0 (ADCS:INT = 1) with an interrupt request output enabled
(ADCS:INTE = 1), an interrupt request is generated.
■ 8-/10-bit A/D Converter Interrupt and EI2OS
See Section "3.5 Interrupt" for details of the interrupt number, interrupt control register, and interrupt
vector address.
■ EI2OS Function of 8-/10-bit A/D Converter
In the 8-/10-bit A/D converter, the EI2OS function can be used to transfer the A/D conversion results from
the A/D data register (ADCR) to memory. If the EI2OS function is used, the A/D-converted data protection
function is activated to cause A/D conversion to pause during memory transfer and prevent data loss as A/
D conversion is performed continuously.
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CM44-10114-7E
MB90495G Series
13.5
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.5 Explanation of Operation of 8-/10-bit A/D Converter
Explanation of Operation of 8-/10-bit A/D Converter
The 8-/10-bit A/D converter has the following A/D conversion modes. Set each mode
according to the setting of the A/D conversion mode select bits in the A/D control status
register (ADCS:MD1, MD0).
• Single conversion mode (restartable/not-restartable during A/D conversion)
• Continuous conversion mode (not-restartable during A/D conversion)
• Pause conversion mode (not-restartable during A/D conversion)
■ Single-shot Conversion Mode (ADCS:MD1, MD0 = "00B" or "01B")
• When the start trigger is input, the analog inputs from the start channel (ADCS:ANS2 to ANS0) to the
end channel (ADCS:ANE2 to ANE0) are A/D-converted continuously.
• The A/D conversion stops at the termination of the A/D conversion for the end channel.
• To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D control
status register (ADCS:BUSY).
• When the A/D conversion mode select bits (MD1, MD0) are set to "00B", this mode can be restarted
during A/D conversion. If the bits are set to 01B, this mode cannot be restarted during A/D conversion.
■ Continuous Conversion Mode (ADCS:MD1, MD0 = "10B")
• When the start trigger is input, the analog inputs from the start channel (ADCS:ANS2 to ANS0) to the
end channel (ADCS:ANE2 to ANE0) are A/D-converted continuously.
• When A/D conversion for the end channel is terminated, it is continued after returning to the analog
input for the start channel.
• To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D control
status register (ADCS:BUSY).
• This mode cannot be restarted during A/D conversion.
■ Pause-conversion Mode (ADCS:MD1, MD0 = "11B")
• When the start trigger is input, A/D conversion starts for the start channel (ADCS:ANS2 to ANS0). The
A/D conversion pauses at the termination of A/D conversion for one channel. When the start trigger is
input while A/D conversion pauses, A/D conversion is performed for the next channel.
• The A/D conversion pauses at termination of A/D conversion for the end channel. When the start trigger
is input while A/D conversion pauses, A/D conversion is continued after returning to the analog input
for the start channel.
• To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D control
status register (ADCS:BUSY).
• This mode cannot be restarted during A/D conversion.
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CHAPTER 13 8-/10-BIT A/D CONVERTER
13.5 Explanation of Operation of 8-/10-bit A/D Converter
13.5.1
MB90495G Series
Single-shot Conversion Mode
In the single conversion mode, A/D conversion is performed sequentially from the start
channel to the end channel. The A/D conversion stops at the termination of A/D
conversion for the end channel.
■ Setting of Single-shot Conversion Mode
Operating the 8-/10-bit A/D converter in the single conversion mode requires the setting shown in Figure
13.5-1.
Figure 13.5-1 Setting of Single-shot Conversion Mode
bit 15 14 13 12 11 10
ADCS
9 bit 8 bit 7 6
4
3
2
1 bit 0
BUSY INT INTE PAUS STS1 STS0 STRT Reserved MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
0
ADCR
5
S10 ST1 ST0 CT1 CT0 ⎯
0
D9 to D0(Converted data stored)
ADER
⎯:
:
:
0 :
Unused
Used bit
Set the bit corresponding to pin to be used as analog input pin to 1.
Set 0
■ Operation of Single-shot Conversion Mode
• When the start trigger is input, A/D conversion starts from the channel set by the A/D conversion start
channel select bits (ANS2 to ANS0) and is performed continuously up to the channel set by the A/D
conversion end channel select bits (ANE2 to ANE0).
• The A/D conversion stops at the termination of the A/D conversion for the channel set by the A/D
conversion end channel select bits (ANE2 to ANE0).
• To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D control
status register (ADCS:BUSY).
• When the A/D conversion mode select bits (MD1, MD0) are set to "00B", this mode can be restarted
during A/D conversion. If the bits are set to "01B", this mode cannot be restarted during A/D
conversion.
[When start and end channels are the same]
• If the start and end channels have the same channel number (ADCS:ANS2 to ANS0 = ADCS:ANE2 to
ANE0), only one A/D conversion for one channel set as the start channel (= end channel) is performed
and terminated.
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CM44-10114-7E
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.5 Explanation of Operation of 8-/10-bit A/D Converter
MB90495G Series
[Conversion order in single-shot conversion mode]
Table 13.5-1 gives an example of the conversion order in the single-shot conversion mode.
Table 13.5-1 Conversion Order in Single-shot Conversion Mode
CM44-10114-7E
Start Channel
End Channel
Conversion Order
AN0 pin
(ADCS:ANS = "000B")
AN3 pin
(ADCS:ANE = "011B")
AN0 --> AN1 --> AN2 --> AN3 --> End
AN6 pin
(ADCS:ANS = "110B")
AN2 pin
(ADCS:ANE = "010B")
AN6 --> AN7 --> AN0 --> AN1 --> AN2 --> End
AN3 pin
(ADCS:ANS = "011B")
AN3 pin
(ADCS:ANE = "011B")
AN3 --> End
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CHAPTER 13 8-/10-BIT A/D CONVERTER
13.5 Explanation of Operation of 8-/10-bit A/D Converter
13.5.2
MB90495G Series
Continuous Conversion Mode
In the continuous conversion mode, A/D conversion is performed sequentially from the
start channel to the end channel.
When A/D conversion for the end channel is terminated, it is continued after returning
to the start channel.
■ Setting of Continuous Conversion Mode
Operating the 8-/10-bit A/D converter in the continuous conversion mode requires the setting shown in
Figure 13.5-2.
Figure 13.5-2 Setting of Continuous Conversion Mode
bit 15 14 13 12 11 10
ADCS
9 bit 8 bit 7 6
4
3
2
1 bit 0
BUSY NT INTE PAUS STS1 STS0 STRT Reserved MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
0
ADCR
5
S10 ST1 ST0 CT1 CT0 ⎯
1
0
D9 to D0 (Converted data stored)
ADER
⎯ :
:
:
1 :
0 :
Unused
Used bit
Set the bit corresponding to pin to be used as analog input pin to 1.
Set 1
Set 1
■ Operation of Continuous Conversion Mode
• When the start trigger is input, A/D conversion starts from the channel set by the A/D conversion start
channel select bits (ANS2 to ANS0) and is performed continuously up to the channel set by the A/D
conversion end channel select bits (ANE2 to ANE0).
• When A/D conversion for the channel set by the A/D conversion end channel select bits (ANE2 to
ANE0) is terminated, it is continued after returning to the channel set by the A/D conversion start
channel select bits (ANS2 to ANS0).
• To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D control
status register (ADCS:BUSY).
• This mode cannot be restarted during A/D conversion.
[When start and end channels are the same]
• If the start and end channels have the same channel number (ADCS:ANS2 to ANS0 = ADCS:ANE2 to
ANE0), A/D conversion for one channel set as the start channel (= end channel) is repeated.
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CM44-10114-7E
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.5 Explanation of Operation of 8-/10-bit A/D Converter
MB90495G Series
[Conversion order in continuous conversion mode]
Table 13.5-2 gives an example of the conversion order in the continuous conversion mode.
Table 13.5-2 Conversion Order in Continuous Conversion Mode
CM44-10114-7E
Start Channel
End Channel
Conversion Order
AN0 pin
(ADCS:ANS = "000B")
AN3 pin
(ADCS:ANE = "011B")
AN0 --> AN1 --> AN2 --> AN3 --> AN0 -->
Repeat
AN6 pin
(ADCS:ANS = "110B")
AN2 pin
(ADCS:ANE = "010B")
AN6 --> AN7 --> AN0 --> AN1 --> AN2 -->
AN6 --> Repeat
AN3 pin
(ADCS:ANS = "011B")
AN3 pin
(ADCS:ANE = "011B")
AN3 --> AN3 --> Repeat
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CHAPTER 13 8-/10-BIT A/D CONVERTER
13.5 Explanation of Operation of 8-/10-bit A/D Converter
13.5.3
MB90495G Series
Pause-conversion Mode
In the pause-conversion mode, A/D conversion starts and pauses repeatedly for each
channel. When the start trigger is input after the A/D conversion pauses at the
termination of the A/D conversion for the end channel, A/D conversion is continued
after returning to the start channel.
■ Setting of Pause-conversion Mode
Operating the 8-/10-bit A/D converter in the pause-conversion mode requires the setting shown in Figure
13.5-3.
Figure 13.5-3 Setting of Pause-conversion Mode
bit 15 14 13 12 11 10
ADCS
9 bit 8 bit 7 6
BUSY NT INTE PAUS STS1 STS0 STRT
Reserved
0
ADCR
S10 ST1 ST0 CT1 CT0 ⎯
5
4
3
2
1 bit 0
MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
1
1
D9 to D0 (Converted data stored)
ADER
⎯ :
:
:
1 :
0 :
Unused
Used bit
Set the bit corresponding to pin to be used as analog input pin to 1.
Set 1
Set 1
■ Operation of Pause-conversion Mode
• When the start trigger is input, A/D conversion starts at the channel set by the A/D conversion start
channel select bits (ANS2 to ANS0). The A/D conversion pauses at the termination of the A/D
conversion for one channel. When the start trigger is input while A/D conversion pauses, A/D
conversion for the next channel is performed.
• The A/D conversion pauses at the termination of the A/D conversion for the channel set by the A/D
conversion end channel select bits (ANE2 to ANE0). When the start trigger is input while A/D
conversion pauses, A/D conversion is continued after returning to the channel set by the A/D conversion
start channel select bits (ANS2 to ANS0).
• To restart this mode while A/D conversion pauses, input the start trigger set by the A/D start trigger
select bits in the A/D control status register (ADCS:STS1, STS0).
• To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D control
status register (ADCS:BUSY).
• This mode cannot be restarted during A/D conversion.
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CM44-10114-7E
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.5 Explanation of Operation of 8-/10-bit A/D Converter
MB90495G Series
[When start and end channels are the same]
• If the start and end channels have the same channel number (ADCS:ANS2 to ANS0 = ADCS:ANE2 to
ANE0), A/D conversion for one channel set as the start channel (= end channel), and pause are repeated.
[Conversion order in pause-conversion mode]
Table 13.5-3 gives an example of the conversion order in the pause-conversion mode.
Table 13.5-3 Conversion Order in Pause-conversion Mode
Start Channel
CM44-10114-7E
End Channel
Conversion Order
AN0 pin
(ADCS:ANS = "000B")
AN3 pin
(ADCS:ANE="011B")
AN0 --> Stop, Start --> AN1 --> Stop, Start -->
AN2 --> Stop, Start --> AN3 --> Stop, Start -->
AN0 --> Repeat
AN6 pin
(ADCS:ANS = "110B")
AN2 pin
(ADCS:ANE="010B")
AN6 --> Stop, Start --> AN7 --> Stop, Start -->
AN0 --> Stop, Start --> AN1 --> Stop, Start -->
AN2 --> Stop, Start --> AN6 --> Repeat
AN3 pin
(ADCS:ANS = "011B")
AN3 pin
(ADCS:ANE="011B")
AN3 --> Stop, Start --> AN3 --> Stop, Start -->
Repeat
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CHAPTER 13 8-/10-BIT A/D CONVERTER
13.5 Explanation of Operation of 8-/10-bit A/D Converter
13.5.4
MB90495G Series
Conversion Using EI2OS Function
The 8-/10-bit A/D converter can transfer the A/D conversion result to memory by using
the EI2OS function.
■ Conversion Using EI2OS
The use of the EI2OS enables the A/D-converted data protection function to transfer multiple data to
memory without the loss of converted data even if A/D conversion is performed continuously.
The conversion flow when the EI2OS is used is shown in Figure 13.5-4.
Figure 13.5-4 Flow of Conversion when Using EI2OS
A/D converter starts
Sample & hold
A/D conversion starts
A/D conversion terminates
Interrupt generated
EI2OS starts
Converted data transferred
Specified count
completed?*
NO
Interrupt cleared
YES
Interrupt processing
*: The specified count depends on the setting of the EI2OS.
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CM44-10114-7E
MB90495G Series
13.5.5
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.5 Explanation of Operation of 8-/10-bit A/D Converter
A/D-converted Data Protection Function
A/D conversion with the output an interrupt request enabled activates the A/D
conversion data protection function.
■ A/D-converted Data Protection Function in 8-/10-bit A/D Converter
The 8-/10-bit A/D converter has only one A/D data register (ADCR) where A/D-converted data is stored.
When the A/D conversion results are determined after the termination of A/D conversion, data in the A/D
data register is rewritten. Therefore, the A/D conversion results may be lost if the A/D conversion results
already stored are not read before data in the A/D data register is rewritten. The A/D-converted data
protection function in the 8-/10-bit A/D converter is activated to prevent data loss. This function
automatically causes A/D conversion to pause when an interrupt request is generated (ADCS:INT = 1) with
an interrupt request enabled (ADCS:INTE = 1).
● A/D-converted data protection function when EI2OS not used
• When the A/D conversion results are stored in the A/D data register (ADCR) after the analog input is A/
D-converted, the interrupt request flag bit in the A/D control status register (ADCS:INT) is set to 1.
• A/D conversion pauses for data protection while the interrupt request flag bit in the A/D control status
register (ADCS:INT) is set.
• When the INT bit is set with an interrupt request from the A/D control status register enabled
(ADCS:INTE = 1), an interrupt request is generated. When the INT bit is cleared by the generated
interrupt processing, the pause of A/D conversion is cancelled.
● A/D-converted data protection function when EI2OS used
• A/D conversion pauses for data protection while the EI2OS function is used to transfer the A/D
conversion results to memory from the A/D data register after A/D conversion. When A/D conversion
pauses, the pause flag bit in the A/D control status register (ADCS:PAUS) is set to 1.
• When the transfer of the A/D conversion results to memory by the EI2OS function is terminated, the
pause of A/D conversion is cancelled and the pause flag bit (ADCS:PAUS) is cleared to 0. If A/D
conversion is performed continuously, it is restarted.
● Processing flow of A/D conversion data protection function when EI2OS used
Figure 13.5-5 shows the processing flow of the A/D conversion data protection function when the EI2OS is
used.
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CHAPTER 13 8-/10-BIT A/D CONVERTER
13.5 Explanation of Operation of 8-/10-bit A/D Converter
MB90495G Series
Figure 13.5-5 Processing Flow of A/D Conversion Data Protection Function when Using EI2OS
EI2OS set
A/D continuous conversion starts
First conversion terminates
Data in A/D data register stored
EI2OS starts
Second conversion terminates
EI2OS terminates
NO
A/D pauses
YES
Data in A/D data register stored
Third conversion
EI2OS starts
Continued
Entire conversion terminates
EI2OS starts
Interrupt processing
A/D conversion pauses
End
Note: The operation flow of when the A/D converter is stopped is omitted.
Notes:
412
• The A/D conversion data protection function is activated only when an interrupt request is enabled.
Set the interrupt request enable bit in the A/D control status register (ADCS:INTE) to 1.
• When the EI2OS function is used to transfer the A/D conversion results to memory, do not disable
output of an interrupt request. If output of an interrupt request is disabled during a pause of A/D
conversion (ADCS:INTE = 0), A/D conversion may be restarted to rewrite data being transferred.
• When the EI2OS function is used to transfer the A/D conversion results to memory, do not restart.
Restarting during a pause of A/D conversion may cause loss of the A/D conversion results.
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CM44-10114-7E
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.6 Precautions when Using 8-/10-bit A/D Converter
MB90495G Series
13.6
Precautions when Using 8-/10-bit A/D Converter
Precautions when using the 8-/10-bit A/D converter are given below:
■ Precautions when Using 8-/10-bit A/D Converter
● Analog input pin
• The analog input pins serve as general-purpose I/O ports of port 5. When using the pin as an analog
input pin, switch the pin to "analog input pin" according to the setting of the port 5 direction register
(DDR5) and the analog input enable register (ADER).
• When using the pin as an analog input pin, write 0 to the bit in the DDR5 corresponding to the pin to be
used and turn off the output transistor. Also write 1 to the bit in the ADER corresponding to the pin to
be used and set the pin to "analog input enable."
• When an intermediate-level signal is input with the pin set as a general-purpose I/O port, the input
leakage current flows in the gate. When using the pin as an analog input pin, always set the pin to
"analog input enable".
● Precaution when starting by internal timer or external trigger
• The input value at which the 8-/10-bit A/D converter is started by the internal timer output or external
trigger should be set to "inactive" (High for external trigger). Holding the input value for the start trigger
active may cause the 8-/10-bit A/D converter to start concurrently with the setting of the A/D start
trigger select bits in the A/D control status register (ADCS:STS1, STS0).
● Procedure of 8-/10-bit A/D converter and analog input power-on
• Always apply a power to the 8-/10-bit A/D converter power (AVCC, AVR) and the analog input (AN0
to AN7) after or concurrently with the digital power (VCC)-on.
• Always turn off the 8-/10-bit A/D converter power and the analog input before or concurrently with the
digital power (VCC)-down.
• Note that AVR should not exceed AVCC at power on or power down.
● Power supply voltage of 8-/10-bit A/D converter
• To prevent latch up, note that the 8-/10-bit A/D converter power (AVCC) should not exceed the digital
power (VCC) voltage.
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CHAPTER 13 8-/10-BIT A/D CONVERTER
13.6 Precautions when Using 8-/10-bit A/D Converter
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MB90495G Series
CM44-10114-7E
CHAPTER 14
UART0
This chapter explains the function and operation of the
UART0.
14.1 Overview of UART0
14.2 Block Diagram of UART0
14.3 Configuration of UART0
14.4 Interrupt of UART0
14.5 Baud Rate of UART0
14.6 Operation of UART0
14.7 Precautions when Using UART0
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CHAPTER 14 UART0
14.1 Overview of UART0
14.1
MB90495G Series
Overview of UART0
The UART0 is a general-purpose serial-data communication interface for synchronous
or asynchronous communication with external devices.
• Incorporates a bidirectional communication function (clock synchronous and
asynchronous modes)
• Incorporates a master/slave type communication function (multiprocessor mode)
• Can generate an interrupt request at completion of transmitting and receiving, and at
detection of a receive error
• Supports expansion intelligent I/O service (EI2OS)
■ Function of UART0
● Function of UART0
The UART0 is a general-purpose serial-data communication interface, which transmits/receives serial data
with external devices. UART0 has functions listed in Table 14.1-1.
Table 14.1-1 Function of UART0
Function
Data buffer
Transfer mode
Full-duplicate double-buffer
• Synchronous to clock (without start bit/stop bit and parity bit)
• Asynchronous (start-stop synchronization to clock)
• Dedicated baud-rate generator (The baud rate can be selected from
among ten types.)
• Any baud rate can be set by external clock.
• A clock supplied from the internal clock (16-bit reload timer) can
be used.
Baud rate
Data length
• 7 bits (for asynchronous normal mode only)
• 8 bits
Signal type
NRZ (Non Return to Zero) type
Detection of receive error
Interrupt request
• Framing error
• Overrun error
• Parity error (not supported for operation mode 1)
• Receive interrupt (receive, detection of receive error)
• Transmit interrupt (transmit)
• Both the transmission and reception support EI2OS.
Master/slave type communication This function enables communications between 1 (only use master)
function (multiprocessor mode) and n (slave) (This function is used only as the master side)
Note:
416
At the clock synchronous transfer, the UART only transfers data, not affixing the start and stop bits.
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CM44-10114-7E
CHAPTER 14 UART0
14.1 Overview of UART0
MB90495G Series
Table 14.1-2 Operation Mode of UART0
Data Length
Operation Mode
With Parity
0
Normal mode
1
Multiprocessor
mode
2
Clock
synchronous
mode
No Parity
7 or 8 bits
8+1
8
*1
Synchronous/
Asynchronous
Length of Stop Bit
Asynchronous
−
Asynchronous
−
Clock synchronous
1 bit or 2 bits *2
None
−: Setting disabled
*1: +1 is the address/data select bit (SCR:A/D) used for controlling communications.
*2: During reception, only one bit can be detected as the stop bit.
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CHAPTER 14 UART0
14.2 Block Diagram of UART0
14.2
MB90495G Series
Block Diagram of UART0
The UART0 consists of the following block.
■ Block Diagram of UART0
Figure 14.2-1 Block Diagram of UART0
Control bus
Receive interrupt
request output
Dedicated baud
rate generator
16-bit
reload timer
Transmit interrupt
request output
Transmit clock
Clock
selector
Receive clock
Pin
SCK
Receive
controller
Transmit
controller
Start bit
detector
Transmit
start circuit
Receive bit
counter
Transmit bit
counter
Receive parity
counter
Transmit parity
counter
Pin
SOT
Receive shift
register
Pin
Transmit shift
register
SIN
Serial input
data register
Reception state
determine circuit
End
of
reception
Serial output
data register
Start of transmission
Receive error
generate signal
for EI2OS (to CPU)
Internal data bus
Communication
prescaler
control
register
Serial
edge
select
register
NEG
418
MD
DIV3
DIV2
DIV1
DIV0
Serial
mode
register
MD1
MD0
CS2
CS1
CS0
Serial
control
register
SCKE
SOE
FUJITSU SEMICONDUCTOR LIMITED
PEN
P
SBL
CL
A/D
REC
RXE
TXE
Serial
status
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
CM44-10114-7E
CHAPTER 14 UART0
14.2 Block Diagram of UART0
MB90495G Series
● Details of pins, etc., in block diagram
The actual pin names and interrupt request numbers used in the UART0 are as follows:
SCK pin: P31/SCK0/RD
SOT pin: P30/SOT0/ALE
SIN pin: P32/SIN0/WRL
Transmit interrupt number: #39 (27H)
Receive interrupt number: #40 (28H)
● Clock selector
The clock selector selects the transmit/receive clock from the dedicated baud rate generator, external input
clock, and internal clock (clock supplied from 16-bit reload timer 0).
● Receive controller
The receive controller is composed of receive bit counter, start bit detector and receive parity counter. The
receive bit counter counts the receive data, and outputs a receive interrupt request when reception of one
piece of data is completed.
The start bit detector detects the start bit from the serial input signal and writes the received data to the
serial input data register, on a bit-by-bit shift basis in accordance with the transfer rate.
● Transmit controller
The transmit controller is composed of the transmit bit counter, transmit start circuit, and transmit parity
counter. The transmit bit counter counts the transmit data, and outputs a transmit interrupt request when
transmission of one piece of data is completed. The transmit start circuit starts transmission when serial
output data register (SODR) is written. The transmit parity counter generates the parity bit when parity is
provided.
● Receive shift register
The receive shift register writes the receive data input from the SIN pin while shifting bit-by-bit, and when
the data reception is completed, it transfers the receive data to the serial input data register (SIDR).
● Transmit shift register
Data written to SODR is transferred to the transmit shift register, and then the data is output to the SOT pin
while shifting bit-by-bit.
● Serial mode register (SMR0)
The serial mode register (SMR0) selects the operation mode, the clock input source (baud rate), and
enables or disables the pin output of serial data and clock.
● Serial control register (SCR0)
The serial control register (SCR0) sets the parity, selects the type of parity, sets the stop bit length and data
length, selects the frame data format in operation mode 1, clears the error flag, and enables or disables
transmitting and receiving.
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CHAPTER 14 UART0
14.2 Block Diagram of UART0
MB90495G Series
● Serial status register (SSR0)
The status register checks the transmission/reception state and error state and sets enabling/disabling of the
transmit/receive interrupt request.
● Serial input data register (SIDR0)
The serial input data register retains the receive data. The serial input is converted and then stored in this
register.
● Serial output data register (SODR0)
The serial output data register sets the transmit data. Data written to this register is serial-converted and
then output.
● Communication prescaler control register (CDCR0)
The control register sets the baud rate of the baud rate generator, which sets the start/stop of the
communication prescaler and the division rate of machine clock.
● Serial edge select register (SES0)
The serial edge select register (SES0) is an inverter that inverts a clock signal. This register converts the
shift clock signal from Low level to High level or from High level to Low level.
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CHAPTER 14 UART0
14.3 Configuration of UART0
MB90495G Series
14.3
Configuration of UART0
The UART0 pins, interrupt factors, register list and details are shown.
■ UART0 Pin
The pins used in the UART0 serve as general-purpose I/O port.
Table 14.3-1 indicates the pin functions and the setting necessary for use in the UART0.
Table 14.3-1 UART0 Pin
Pin
Name
SOT0
SCK0
SIN0
Pin Function
General-purpose I/O port, address latch
enable output, serial data output
General-purpose I/O port, read strobe
output, serial clock output input/output
General-purpose I/O port, write strobe
output for lower 8 bits in data bus, serial
data input
Setting Necessary for Use in UART0
Set to output enable
(SMR0:SOE = 1).
In clock input, set pin as input port in port
direction register (DDR).
In clock output, set to output enable
(SMR0:SCKE =1).
Set pin as input port in DDR.
■ Block Diagram of Pins of UART0
See "CHAPTER 14 UART0" for the block diagram of pins.
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CHAPTER 14 UART0
14.3 Configuration of UART0
MB90495G Series
■ List of Registers in UART0
Figure 14.3-1 List of Registers and Reset Values in UART0
bit
Serial control register (SCR0)
bit
Serial mode register (SMR0)
bit
Serial status register (SSR0)
bit
Serial input data register (SIDR0)
/Serial output data register (SODR0)
Note: Function as SIDR0 when reading,
fnction as SODR0 when writing
bit
Serial edge select register (SES0)
bit
Communication prescaler control register (CDCR0)
15
14
13
12
11
10
9
8
0
0
0
0
0
1
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
1
×
0
0
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
0
7
6
5
4
3
2
1
0
0
×
×
×
1
1
1
1
×: Undefined
■ Interrupt Request Generation in UART0
● Receive interrupt
• When receive data is loaded to the serial input data register (SIDR0), the receive data load flag bit in the
serial status register (SSR0:RDRF) is set to 1. When a receive interrupt is enabled (SSR0:RIE = 1), a
receive interrupt request is generated.
• When either a framing error, overrun error, or parity error occurs, the framing error flag bit
(SSR0:FRE), the overrun error flag bit (SSR0:ORE), or parity error flag bit (SSR0:PE) in the serial
status register is set to 1 according to the error occurred. When a receive interrupt is enabled (SSR0:RIE
= 1), a receive interrupt is requested.
● Transmit interrupt
When transmit data is transferred from the serial output data register (SODR0) to the transmit shift register,
the transmit data empty flag bit in the serial status register (SSR0:TDRE) is set to 1. If a transmit interrupt
is enabled (SSR0:TIE = 1), a transmit interrupt is requested.
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CHAPTER 14 UART0
14.3 Configuration of UART0
MB90495G Series
14.3.1
Serial Control Register 0 (SCR0)
The serial control register 0 (SCR0) performs the following:
setting parity bit, selecting stop bit length and data length, selecting frame data format
in operation mode 1, clearing receive error flag, and enabling/disabling of transmitting/
receiving.
■ Serial Control Register 0 (SCR0)
Figure 14.3-2 Serial Control Register 0 (SCR0)
15
14
13
12
11
10
9
8
Reset value
00000100 B
R/W R/W R/W R/W R/W
W
R/W R/W
bit 8
TXE
0
1
Transmit disable
Transmit enable
bit 9
RXE
0
1
Receive disable
Receive enable
Transmit enable bit
Receive enable bit
bit 10
Receive error flag clear bit
REC
Clear
FRE
and
ORE, PE flags
0
No
effect
1
bit 11
A/D
Data frame
0
Address frame
1
bit 12
CL
7 bits
0
8 bits
1
bit 13
SBL
1-bit length
0
2-bit length
1
Address/data select bit
Data-length select bit
Stop-bit length select bit
bit 14
P
0
1
R/W : Read/Write
: Write only
W
: Reset value
CM44-10114-7E
Parity select bit
Enabled only when parity provided (PEN = 1)
Even parity
Odd parity
bit 15
PEN
No parity
0
With parity
1
Parity addition enable bit
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CHAPTER 14 UART0
14.3 Configuration of UART0
MB90495G Series
Table 14.3-2 Function of Serial Control Register 0 (SCR0)
Bit Name
424
Function
bit 8
TXE:
Transmit enable bit
Enable or disable the UART0 for sending.
When set to 0: Transmission disabled
When set to 1: Transmission enabled
Note:
When transmitting is disabled during transmitting, transmitting stops after
the data in the serial input data register being transmitted is completed in the
serial input data register.
To set this bit to 0, after writing data to the serial output data register 0
(SODR0), wait for a time of 1/16th of the baud rate in the asynchronous
mode and for a time equal to or more than the baud rate in the synchronous
mode.
bit 9
RXE:
Receive enable bit
Enable or disable the UART0 for receiving.
When set to 0: Reception disabled
When set to 1: Reception enabled
Note:
When receiving is disabled during receiving, receiving stops after the data
being received is stored in the serial input data register.
bit 10
REC:
Receive error flag clear
bit
Clear the receive error flags (SSR0:FRE, ORE and PE) of the serial status
register to 0.
When set to 0: Clears FRE, ORE and PE flags
When set to 1: No effect
When read: 1 always read
Note:
When a receive interrupt is enabled (SSR0:RIE = 1), set the REC bit to 0
only when any one of the FRE, DRE and PE flags is set to 1.
bit 11
A/D:
Address/data select bit
In operation mode 1, set the data format of the frame to be transmitted/received.
When set to 0: Data frame set
When set to 1: Address data frame set
bit 12
CL:
Data-length select bit
Specify the length of send and receive data.
Note:
A data length of 7 bits can be selected only in operation mode 0. In operation
modes 1 and 2, be sure to set a data length of 8 bits.
bit 13
SBL:
Stop-bit length select bit
Set the length of the stop bit (frame end mark of send data) in operation modes 0
and 1 (asynchronous).
Note:
At receiving, only the first bit of the stop bit is always detected.
bit 14
P:
Parity select bit
Select either odd or even parity when with parity (SCR0:PEN = 1) is set.
bit 15
PEN:
Parity addition enable bit
Specify whether to add (at sending) and detect (at receiving) a parity bit.
Note:
A parity bit is not added in operation modes 1 and 2. Be sure to set this bit to
0.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 14 UART0
14.3 Configuration of UART0
MB90495G Series
14.3.2
Serial Mode Register 0 (SMR0)
The serial mode register 0 (SMR0) performs selecting operation mode, selecting baud
rate clock, and disabling/enabling of output of serial data and clock to pin.
■ Serial Mode Register 0 (SMR0)
Figure 14.3-3 Serial Mode Register 0 (SMR0)
7
6
5
4
3
2
1
0
Reset value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
Serial data output enable bit (SOT0 pin)
SOE
Serves as general-purpose I/O port
0
Serves as serial-data output of UART0
1
bit 1
SCKE
Serial clock I/O enable bit (SCK0 pin)
Serves as general-purpose I/O port or clock input pin of UART0
0
1
Serves as serial clock output pin of UART0
bit 2
Reserved bit
Reserved
0
Be sure to set to "0"
bit 5 bit 4 bit 3
CS2 CS1 CS0
Clock input source select bit
"000B" to "100B" Baud rate by dedicated baud rate generator
Setting disable
"101B"
Baud rate by internal timer
"110B"
(16-bit reload timer 0)
"111B"
bit7
Baud rate by external clock
bit6
Operation mode select bit
MD1 MD0
Mode No.
R/W : Read/Write
: Reset value
CM44-10114-7E
Operation mode
0
0
0
Asynchronous normal mode
0
1
1
Asynchronous multiprocessor mode
1
0
2
Clock synchronous mode
1
1
⎯
Setting disable
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CHAPTER 14 UART0
14.3 Configuration of UART0
MB90495G Series
Table 14.3-3 Function of Serial Mode Register 0 (SMR0)
Bit Name
bit 0
SOE:
Serial-data output enable
bit
Enable or disable output of serial data.
When set to 0: General-purpose I/O port set
When set to 1: Serial data output pin set
bit 1
SCKE:
Serial clock I/O enable
bit
Switch between input and output of the serial clock.
When set to 0: General-purpose I/O port or serial clock input pin set
When set to 1: Serial clock output pin set
Notes:
1. When using the SCK0 pin as the serial clock input, set the pin to the input
port using the port direction register (DDR). Also select the external clock
(SMR:CS2 to CS0 = "111B") using the clock input source select bit.
2. When using the SCK pin as the serial clock output, set the clock input source
select bit to anything other than the external clock (SMR:CS2 to CS0 =
anything other than "111B").
bit 2
Reserved bit
Be sure to set this bit to 0.
CS2 to CS0:
Clock input source select
bits
Set the clock input source for the baud rate.
• Select the external clock (SCK0 pin), internal timer (16-bit reload timer 0), or
dedicated baud rate generator as the clock input source.
• Set the baud rate when selecting the dedicated baud rate generator.
MD1, MD0:
Operation mode select
bits
Select the operation mode.
Notes:
1. In operation mode 1, only the master can be used for master/slave
communication. In operation mode 1, the address/data bit on bit 9 cannot be
received, so the slave cannot be used.
2. In operation mode 1, the parity check function cannot be used, set the parity
addition enable bit to no parity (SCR0:PEN = 0).
bit 3 to bit
5
bit 6 and
bit 7
426
Function
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 14 UART0
14.3 Configuration of UART0
MB90495G Series
14.3.3
Serial Status Register 0 (SSR0)
The serial status register (SSR0) checks the transmission/reception status and error
status and enables/disables interrupts.
■ Serial Status Register 0 (SSR0)
Figure 14.3-4 Serial Status Register 0 (SSR0)
15
14
13
12
11
10
9
8
Reset value
00001X00 B
R
R
R
R
R
⎯
R/W R/W
bit 8
TIE
0
1
bit 9
RIE
0
1
bit 11
TDRE
0
1
Transmit interrupt enable bit
Disables transmit interrupt
Enables transmit interrupt
Receive interrupt enable bit
Disables receive interrupt
Enables receive interrupt
Transmit data write flag bit
With transmit data (write of transmit data disabled)
No transmit data (write of transmit data enabled)
bit 12
Receive data load flag bit
RDRF
No receive data
0
With receive data
1
bit 13
Framing error flag bit
FRE
No framing error
0
With framing error
1
bit 14
Overrun error flag bit
ORE
No overrun error
0
With overrun error
1
R/W
R
X
⎯
CM44-10114-7E
:
:
:
:
:
Read/Write
Read only
Undefined
Unused
Reset value
bit 15
PE
Parity error flag bit
0
No parity error
1
With parity error
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CHAPTER 14 UART0
14.3 Configuration of UART0
MB90495G Series
Table 14.3-4 Function of Serial Status Register 0 (SSR0)
Bit Name
428
Function
bit 8
TIE:
Transmit interrupt
request enable bit
Enable or disable send interrupt.
When set to 1: A send interrupt request is issued when data written to the serial
output data register 0 is sent to the transmit shift register
(SSR0:TDRE = 1).
bit 9
RIE:
Receive interrupt request
enable bit
Enable or disable receive interrupt.
When set to 1: A receive interrupt request is issued when receive data is loaded
to the serial input data register 0 (SSR0:RDRF = 1) or when a
receive error occurs (SSR0:PE = 1, DRE = 1, or FRE = 1).
bit 10
Unused bit
Read: The value is undefined.
Write: No effect
bit 11
TDRE:
Transmit data write flag
bit
Show the status of the serial output data register 0 (SODR).
• This bit is cleared to 0 when send data is written to the SODR0.
• This bit is set to 1 when data is loaded to the send shift register and
transmission starts.
• When a transmission interrupt is enabled (SSR0:TIE = 1), a transmit interrupt
request is issued when data written to the serial output data register (SODR0)
is transmitted to the transmit shift register (SSR0:TDRE = 1).
bit 12
RDRF:
Receive data load flag bit
Show the status of the serial input data register.
• This bit is set to 1 when receive data is loaded to the serial input register
(SIDR).
• This bit is cleared to 0 when data is read from the SIDR.
• When a receive interrupt is enabled (SSR0:RIE = 1), a receive interrupt
request is issued when receive data is loaded to the serial input data register
(SIDR0).
bit 13
FRE:
Framing error flag bit
Detect a framing error in receive data.
• This bit is set to 1 when a framing error occurs.
• This bit is cleared when 0 is written to the receive error flag clear bit
(SCR0:REC).
• When a receive interrupt is enabled (SSR0:RIE = 1), a receive interrupt
request is issued when a framing error occurs.
• When the framing error flag bit is set (SSR0:ORE = 1), data in the serial input
data register (SIDR) is invalid.
bit 14
ORE:
Overrun error flag bit
Detect an overrun error in receiving.
• This bit is set to 1 when an overrun error occurs.
• This bit is cleared when 0 is written to the receive error flag clear bit
(SCR0:REC).
• When a receive interrupt is enabled (SSR0:RIE = 1), a receive interrupt
request is issued when an overrun error occurs.
• When the overrun error flag bit is set (SSR0:ORE = 1), data in the serial input
data register 0 (SIDR0) is invalid.
bit 15
PE:
Parity error flag bit
Detect a parity error in receive data.
• This bit is set to 1 when a parity error occurs.
• This bit is cleared when 0 is written to the receive error flag clear bit
(SCR0:REC).
• When a receive interrupt is enabled (SSR0:RIE = 1), a receive interrupt
request is issued when a parity error occurs.
• When the parity error flag bit is set (SSR0:PE = 1), data in SIDR0 is invalid.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 14 UART0
14.3 Configuration of UART0
MB90495G Series
14.3.4
Serial Input Data Register 0 (SIDR0) and Serial Output
Data Register 0 (SODR0)
The serial input data register (SIDR) and serial output data register (SODR) are allocated
to the same address. At read, the register functions as SIDR. At write, the register
functions as SODR.
■ Serial Input Data Register 0 (SIDR0)
Figure 14.3-5 Serial Input Data Register 0 (SIDR0)
bit7
6
5
4
3
2
1
bit0
Reset value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXX B
R
R
R
R
R
R
R
R
R: Read only
X: Undefined
SIDR0 is a data buffer register for receiving serial data.
• The serial data signal transmitted to the serial input pin (SIN0) is converted by the shift register and
stored in SIDR0.
• When the data length is 7 bits, the upper one bit (SIDR0:D7) becomes invalid.
• When receive data is stored in the serial input data register 0 (SIDR0), the receive data load flag bit
(SSR0:RDRF) is set to 1. When a receive interrupt is enabled (SSR0:RIE = 1), a receive interrupt
request is issued.
• Read the SIDR0 when the receive data load flag bit (SSR0:RDRF) is set to 1. The receive data load flag
bit (SSR0:RDRF) is cleared to 0 automatically when the serial input data register 0 (SIDR0) is read.
• When a receive error occurs (any one of SSR0:PE, ORE and FRE is 1), the receive data in SIDR0
becomes invalid.
■ Serial Output Data Register 0 (SODR0)
Figure 14.3-6 Serial Output Data Register 0 (SODR0)
7
6
5
4
3
2
1
bit 0
Reset value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXX B
W
W
W
W
W
W
W
W
W : Write only
X : Undefined
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CHAPTER 14 UART0
14.3 Configuration of UART0
MB90495G Series
The serial output data register 0 (SODR0) is a data buffer register for transmitting serial data.
• When data to be transmitted is written to SODR0 when transmission is enabled (SCR0:TXE = 1), it is
transferred to the transmit shift register, converted to serial data, and transmit from the serial data output
pin (SOT0).
• When the data length is 7 bits, the upper one bit (SODR0:D7) becomes invalid.
• The transmit data write flag (SSR0:TDRE) is cleared to 0 when send data is written to SODR0.
• The transmit data write flag (SSR0:TDRE) is set to 1 at completion of data transfer to the transmit shift
register.
• When the transmit data write flag (SODR:TDRE) is 1, the succeeding transmit data can be written.
When a transmit interrupt is enabled (SSR0:TIE = 1), a transmit interrupt occurs. The succeeding
transmit bit data should be written with the transmit data write flag (SODR:TDRE) at 1.
Note:
430
Serial output data register is a write-only register and serial input data register is a read-only register.
However, since they are allocated to the same address, the write and read values are different. Therefore,
do not use instructions that perform read-modify-write (RMW) operation such as INC and DEC
instructions.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 14 UART0
14.3 Configuration of UART0
MB90495G Series
14.3.5
Communication Prescaler Control Register 0 (CDCR0)
The communication prescaler control register 0 (CDCR0) is used to set the baud rate of
the dedicated baud rate generator for the UART0.
• Starts/stop the communication prescaler
• Sets the division ratio for machine clock
■ Communication Prescaler Control Register 0 (CDCR0)
Figure 14.3-7 Communication Prescaler Control Register 0 (CDCR0)
7
6
5
4
3
2
1
0
R/W ⎯
⎯
⎯ R/W R/W R/W R/W
Reset value
0XXX1111 B
bit 3 bit 2 bit 1 bit 0
DIV3 DIV2 DIV1 DIV0 Communication prescaler division ratio (div) bits
1
1
1
1
Setting disabled
1
1
1
0
2-divided clock
1
1
0
1
3-divided clock
1
1
0
0
4-divided clock
1
0
1
1
5-divided clock
1
0
1
0
6-divided clock
1
0
0
1
7-divided clock
1
0
0
0
8-divided clock
bit 7
MD
R/W : Read/Write
X
: Undefined
⎯
: Unused
: Reset value
Communication prescaler control bit
0
Communication prescaler stopped
1
Communication prescaler enabled
Table 14.3-5 Functions of Communication Prescaler Control Register (CDCR0)
Bit Name
Function
bit 0 to bit 3
DIV3 to DIV0:
Communication
prescaler division ratio
bits
These bits set the machine clock division ratio.
Note:
When changing the division ratio, the time of at least one 1/2-frequency
division of the division clock should be allowed before the next
communication is started in order to stabilize the clock frequency.
bit 4 to bit 6
Unused bits
Read: The value is undefined
Write: No effect
MD:
Communication
prescaler control bit
This bit enables or disables the communication prescaler.
When set to 0: Stops communication prescaler
When set to 1: Operates communication prescaler
bit 7
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CHAPTER 14 UART0
14.3 Configuration of UART0
14.3.6
MB90495G Series
Serial Edge Select Register 0 (SES0)
The serial edge select register 0 (SES0) inverts the clock signal of the UART0 using an
inverter. It logically inverts the shift clock signal input to the UART0 from Low level to
High level, from falling edge to rising edge, or from High level to Low level and from
rising edge to falling edge. The inversion acts on the serial clock output, too.
■ Serial Edge Select Register 0 (SES0)
Figure 14.3-8 Serial Edge Select Register 0 (SES0)
15
14
13
12
11
10
9
⎯
⎯
⎯
⎯
⎯
⎯
⎯ R/W
8
Reset value
XXXXXXX0B
⎯
: Unused
R/W : Read/Write
: Reset value
bit 8
Clock inversion bit
NT
0
Normal
1
Inverts shift clock signal
Table 14.3-6 Functions of Serial Edge Select Register 0 (SES0)
Bit Name
bit 8
bit 9 to bit 15
432
Function
NT:
Clock inversion bit
This bit inverts the clock signal input to the UART0.
• The signal is inverted from Low level to High level or from High level to
Low level.
• The inversion acts on the serial clock output, too.
Unused bits
Read: The value is undefined.
Write: No effect
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 14 UART0
14.4 Interrupt of UART0
MB90495G Series
14.4
Interrupt of UART0
The UART0 has a receive and a transmit interrupts, and the following factors can issue
interrupt requests.
• Receive data is loaded to the serial input data register 0 (SIDR0).
• A receive error (parity error, overrun error, framing error) occurs.
• When send data transferred from the output data register 0 (SODR0) to transmit shift
register
Also, each of these interrupt factors supports the expansion intelligent I/O service
(EI2OS).
■ Interrupt of UART0
The UART0 interrupt control bits and interrupt factors are shown in Table 14.4-1.
Table 14.4-1 UART Interrupt Control Bit and Interrupt Factor
Trans-mission/
reception
Interruptrequest Flag Bit
Reception
Transmission
Operation
Mode
Interrupt Factor
0
1
2
SSR0:RDRF
Ο
Ο
Ο
Receive data
loaded into SIDR0
SSR0:ORE
Ο
Ο
Ο
Overrun error
SSR0:FRE
Ο
Ο
X
Framing error
SSR0:PE
Ο
X
X
Parity error
SSR0:TDRE
Ο
Ο
Ο
SODR0 vacant
Interrupt Factor
Enable Bit
Clear of Interruptrequest Flag
Reading receive
data
SSR0:RIE
SSR0:TIE
Writing 0 to
receive error flag
clear bit
(SSR0:REC)
Writing transmit
data
Ο: Used bit
X: Unused bit
● Receive interrupt
When a receive interrupt is enabled (SSR0:RIE = 1), a receive interrupt request is issued at completion of
data receiving or when any one of the overrun error (SSR0:ORE = 1), framing error (SSR0:FRE = 1), and
parity error (SSR0:PE = 1) occurs.
The receive data load flag (SSR0:RDRF) is cleared to 0 automatically when the serial input data register 0
(SIDR0) is read. Each receive error flag (SSR0:PE, ORE, FRE) is cleared to 0 when 0 is written to the
receive error flag clear bit (SCR0:REC).
Note:
CM44-10114-7E
If a receive error (parity error, overrun error, framing error) occurs, correct the error as necessary, and
then write 0 to the receive error flag clear bit (SCR0:REC) to clear each receive error flag.
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CHAPTER 14 UART0
14.4 Interrupt of UART0
MB90495G Series
● Transmit interrupt
When send data is transmitted from the serial output data register (SODR0) to the transmit shift register,
the transmit data write flag bit (SSR0:TDRE) is set to 1.
When a send interrupt is enabled (SSR0:TIE = 1), a transmit interrupt request is issued.
■ Interrupt Related to UART0 and EI2OS
See Section "3.5 Interrupt" for details of the interrupt numbers, interrupt control register, and interrupt
vector addresses.
■ EI2OS Function of UART0
The UART0 supports EI2OS. Consequently, EI2OS can be started separately for receive interrupts and
transmit interrupts.
● At reception:
Since the MB90495G series does not have any I2C interface, the interrupt vectors cannot be used.
● At transmission:
Since the interrupt control registers (ICR14) are shared with receive interrupts of UART0, EI2OS can be
started only when UART0 transmit interrupts are not used.
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CHAPTER 14 UART0
14.4 Interrupt of UART0
MB90495G Series
14.4.1
Generation of Receive Interrupt and Timing of Flag Set
Interrupts at receiving include the receive completion (SSR0:RDRF), and the receive
error (SSR0:PE, ORE, FRE).
■ Generation of Receive Interrupt and Timing of Flag Set
● Receive data load flag and each receive error flag sets
When data is received, it is stored in the serial input data register (SIDR) when the stop bit is detected (in
operation modes 0 and 1) or when the last bit of receive data (SIDR0:D7) is detected (in operation mode 2).
When a receive error occurs, the error flags (SSR0:PE, ORE, FRE) and receive data load flag
(SSR0:RDRF) are set. In each operation mode, the received data in the serial input data register 0 (SIDR0)
is invalid if either error flag is set.
Operation mode 0 (Asynchronous normal mode)
The receive data load flag bit (SSR0:RDRF) is set when the stop bit is detected. The error flags (SSR0:PE,
ORE, FRE) are set when a receive error occurs.
Operation mode 1 (Asynchronous multiprocessor mode)
The receive data load flag bit (SSR0:RDRF) is set when the stop bit is detected. The error flags
(SSR0:ORE, FRE) are set when a receive error occurs. A parity error (SSR0:PE) cannot be detected.
Operation mode 2 (Clock synchronous mode)
The receive data load flag bit (SSR0:RDRF) is set to 1 when the last bit of receive data (SIDR:D7) is
detected. The error flags (SSR0:ORE) are set when a receive error occurs. A parity error (SSR0:PE) and
framing error (SSR0:FRE) cannot be detected.
Reception and timing of flag set is shown is Figure 14.4-1.
Figure 14.4-1 Reception and Timing of Flag Set
Rceive data
(operation mode 0)
ST
D0
D1
D5
D6
D7
SP
Rceive data
(operation mode 1)
ST
D0
D1
D6
D7
A/D
SP
D0
D1
D4
D5
D6
D7
Rceive data
(operation mode 2)
SSR0: PE, ORE, FRE*
SSR0: RDRF
Receive interrupt occurs
*
: The PE flag cannot be detected in mode 1.
The PE and FRE flags cannot be detected in mode 2.
ST : Start bit
SP : Stop bit
A/D : Address/data select bit of operation mode 2
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CHAPTER 14 UART0
14.4 Interrupt of UART0
MB90495G Series
● Timing of receive interrupt request generation
With a receive interrupt enabled (SSR0:RIE = 1), when a receive interrupt request is issued when any one
of the receive data load flag (SSR0:RDRF), parity error flag (SSR0:PE), overrun error flag (SSR0:ORE)
and, framing error flag (SSR0:FRE) is set, reception interrupt is requested.
436
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CM44-10114-7E
CHAPTER 14 UART0
14.4 Interrupt of UART0
MB90495G Series
14.4.2
Generation of Transmit Interrupt and Timing of Flag Set
At transmission, the interrupt is generated in the state which the succeeding data can
be written to the serial output data register 0 (SODR0).
■ Generation of Transmit Interrupt and Timing of Flag Set
● Set and clear of transmit data empty flag bit
The send data write flag bit (SSR0:TDRE) is set when the send data written to the serial output data register
0 (SODR0) is transmitted to the send shift register and the next data is ready for writing. The send data
write flag bit (SODR0:TDRE) is cleared to 0 when the next send data is written to the serial output data
register 0 (SODR0).
Figure 14.4-2 Transmission and Timing of Flag Set
[Operation mode 0, 1]
Transmit interrupt requested
Transmit interrupt occured
Writing to SODR0
SSR0: TDRE
Output to SOT0
SP SP ST D0 D1 D2 D3
ST D0 D1 D2 D3 D4 D5 D6 D7 A/D
Transmit interrupt occured
Transmit interrupt occured
[Operation mode 2]
Writing to SODR0
SSR0: TDRE
Output to SOT0
ST
D0 to D7
SP
A/D
:
:
:
:
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Start bit
Data bits
Stop bit
Address/data select bit
● Timing of transmit interrupt request
When a transmit interrupt is enabled (SSR0:TIE = 1), a send interrupt request is issued when the transmit
data write flag bit (SSR0:TDRE) is set.
Note:
CM44-10114-7E
When sending is disabled during sending (SCR0:TXE = 0; receiving disable bit RXE included in
operation mode 1), the send data write flag bit is set (SSR0:TDRE = 1) and UART0 communications are
disabled after the shift operation of the send shift register stops. The send data written to the serial output
data register before the transmission stops (SODR) is sent.
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CHAPTER 14 UART0
14.5 Baud Rate of UART0
14.5
MB90495G Series
Baud Rate of UART0
One of the following can be selected as the UART0 transmit/receive clock.
• Dedicated baud rate generator
• Internal clock (16-bit reload timer 0 output)
• External clock (clock input to SCK pin)
■ Select of UART0 Baud Rate
The UART0 baud rate select circuit comprises as shown in Figure 14.5-1. The clock input source can be
selected from among the following three types:
● Baud rate by dedicated baud rate generator
• When using the dedicated baud rate generator incorporated into UART0 as a clock input source, set the
CS2 to CS0 bits in the serial mode register to "000B" to "100B" according to the baud rate. The baud
rate can be selected from five types.
● Baud rate by internal timer
• When using the internal clock supplied from the 16-bit reload timer 0 as a clock input source, set the
CS2 to CS0 bits in SMR0 to "110B".
• The baud rate is the value at which the frequency of the clock supplied from the 16-bit reload timer 0 is
divided by 2 in the clock synchronous mode, and the value at which the frequency of the supplied clock
is divided by 32 in the clock asynchronous mode.
• Any baud rate can be selected according to the settings value of the 16-bit reload timer 0.
● Baud rate by external clock
• When using the external clock supplied from the clock input pin (SCK0) in the UART0 as the clock
input source, set the CS2 to CS0 bits in SMR0 to "111B".
• The baud rate is the value at which the external clock is supplied in the clock synchronous mode and the
value at which the frequency of the input clock is divided by 16.
• Any baud rate can be used if the external clock frequency is 2 MHz or less.
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CHAPTER 14 UART0
14.5 Baud Rate of UART0
MB90495G Series
Figure 14.5-1 UART0 Baud Rate Selector
SMR0: CS2 to CS0
(Clock input source select bits)
Clock selector
CS2 to CS0 = "000B" to "100B"
[Dedicated baud rate generator]
φ/3, φ/4,
φ/5, φ/6,
φ/8
φ
Communication prescaler
(CDCR0: MD0, DIV3 to DIV0)
[Internal timer]
TMCSR0: CSL1, CSL0
Clock selector
φ
Decrement UF
counter
Oscillation dividing circuit
[Clock synchronous]
Any one of the 1/2, 1/4,
1/8, 1/16, 1/32 division
ratio is selected.
[Asynchronous]
The internal fixed division
ratio is selected.
CS2 to CS0 = "110B"
1/2 [Clock synchronous]
1/32 [Asynchronous]
Baud rate
φ/21 φ/23 φ/25
Prescaler
16-bit reload timer 0
CS2 to CS0 = "111B"
[External clock]
SCK0
Pin
φ : Machine clock
UF : Underflow
CM44-10114-7E
1/1 [Clock synchronous]
1/16 [Asynchronous]
SMR0: MD1, MD0
(Operation mode select bits)
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CHAPTER 14 UART0
14.5 Baud Rate of UART0
MB90495G Series
Baud Rate by Dedicated Baud Rate Generator
14.5.1
The baud rate that can be set when the output clock of the dedicated baud rate
generator is selected as the transmit/receive clock of the UART 0 is shown.
■ Baud Rate by Dedicated Baud Rate Generator
The baud rate based on the dedicated baud rate generator is set by setting the clock input source select bits
in the serial mode register (SMR0:CS2 to CS0) to "000B" to "100B".
When generating a transmit/receive clock using the dedicated baud rate generator, the division ratio for the
clock input source selected by the clock selector is selected to determine the baud rate after the machine
clock frequency is divided by the communication prescaler.
The division ratio at which the machine clock frequency is divided by the communication prescaler is the
same for the clock synchronous and asynchronous modes. The division ratio at which the baud rate is
determined is different for the clock synchronous and asynchronous modes.
Figure 14.5-2 shows the baud rate selector based on the dedicated baud rate generator.
Figure 14.5-2 Baud Rate Selector Based on Dedicated Baud Rate Generator
SMR0: CS2 to CS0
(Clock input source select bits)
Clock selector
φ
φ/3, φ/4,
φ/5, φ/6,
φ/8
Communication prescaler
(CDCR0: MD0, DIV3 to DIV0)
φ: Machine clock frequency
Oscillation dividing circuit
[Clock synchronous]
Any one of the 1/2, 1/4, 1/8,
1/16, 1/32 division ratio
is selected.
[Asynchronous]
The internal fixed division
ratio is selected.
Baud rate
SMR0: MD1, MD0
(Opration mode select bits)
● Calculation expression for baud rate
Baud rate in asynchronous mode = φ x div x (division ratio of transfer clock in asynchronous mode)
Baud rate in clock synchronous mode = φ x div x (division ratio of transfer clock in clock synchronous
mode)
φ: Machine clock frequency
div: Division ratio based on communication prescaler
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CHAPTER 14 UART0
14.5 Baud Rate of UART0
MB90495G Series
● Division ratio based on communication prescaler (common between asynchronous and clock
synchronous modes)
The division ratio of the machine clock is set by the division ratio select bits in the communication
prescaler control register (CDCR0:DIV3 to DIV0).
Table 14.5-1 Division Ratio Based on Communication Prescaler
Machine Clock
φ(MHz)
Division Ratio
div
Communication Prescaler Control
Register 0 (CDCR0)
DIV3
DIV2
DIV1
DIV0
4
4
1
1
0
0
6
6
1
0
1
0
8
8
1
0
0
0
6
3
1
1
0
1
8
4
1
1
0
0
10
5
1
0
1
1
12
6
1
0
1
0
14
7
1
0
0
1
16
8
1
0
0
0
8
2
1
1
1
0
12
3
1
1
0
1
16
4
1
1
0
0
16
2
1
1
1
0
Division Result
φ/div (MHz)
1
2
4
8
div: Division ratio based on communication prescaler
● Baud rate (asynchronous mode)
The baud rate in the asynchronous/clock synchronous mode is generated by dividing the frequency of the
output clock of the communication prescaler by 2, 4, 8, 16, and 32. The division ratio is set by the clock
input source select bits (SMR0:CS2 to CS0).
Table 14.5-2 Baud Rate (Asynchronous Mode)
Baud Rate Select Bit
Baud Rate (bps)
Calculation
CS2
CS1
CS0
φ/div = 2 MHz
φ/div = 4 MHz
φ/div = 8 MHz
0
0
0
9,615
19,230
38,460
(φ/div) / (8 x 13 x 2)
0
0
1
4,808
9,615
19,230
(φ/div) / (8 x 13 x 22)
0
1
0
2,404
4,808
9,615
(φ/div) / (8 x 13 x 23)
0
1
1
1,202
2,404
4,808
(φ/div) / (8 x 13 x 24)
1
0
0
31,250
62,500
−
(φ/div) / 26
φ: Machine clock frequency
div: Division ratio based on communication prescaler
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CHAPTER 14 UART0
14.5 Baud Rate of UART0
MB90495G Series
● Baud rate (clock synchronous)
Table 14.5-3 Baud Rate (Clock Synchronous)
Baud Rate Select Bit
Baud Rate (bps)
Calculation
CS2
CS1
CS0
φ/div = 2 MHz
φ/div = 4 MHz
φ/div = 8 MHz
0
0
0
1M
2M
Reserved
(φ/div) / 2
0
0
1
500K
1M
2M
(φ/div) / 22
0
1
0
250K
500K
1M
(φ/div) / 23
0
1
1
125K
250K
500K
(φ/div) / 24
1
0
0
62.5K
125K
250K
(φ/div) / 25
φ: Machine clock frequency
div: Division ratio based on communication prescaler
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CHAPTER 14 UART0
14.5 Baud Rate of UART0
MB90495G Series
14.5.2
Baud Rate by Internal Timer 0 (16-bit Reload Timer)
The setting when selecting the internal clock supplied from the 16-bit reload timer 0 as
the clock input source of the UART0 and the baud rate calculation are shown below.
■ Baud Rate by Internal Timer 0 (16-bit Reload Timer 0 Output)
The baud rate based on the internal timer (16-bit reload timer 0 output) is set by setting the clock input
source select bits (SMR0:CS2 to CS0) to "110B". Any baud rate can be set by selecting the division ratio of
the count clock and the reload value of the 16-bit reload timer.
Figure 14.5-3 shows the baud rate selector based on the internal timer.
• If the internal timer (16-bit reload timer) is selected as a clock input source (SMR0:CS2 to CS0), the 16bit reload timer 0 output pin (TOT) is connected internally and does not need to be connected externally
to the external clock input pin (SCK0).
• The 16-bit reload timer 0 output pin (TOT) can be used as a general-purpose I/O port when it is not
being used in other may.
Figure 14.5-3 Baud Rate Selector by Internal Timer (16-bit Reload Timer Output)
SMR0: CS2 to CS0 = "110B"
(Clock input source select bits)
Clock selector
1/2 [Clock synchronous]
1/32 [Asynchronous]
16-bit reload timer 0 output
(The frequency is specified by
the count clock division ratio
and the reload value)
Baud rate
SMR0: MD1, MD0
(Operation mode select bits)
● Baud Rate
Asynchronous baud rate =
Clock synchronous =
φ
bps
X (n+1) × 2 × 16
φ
X (n+1) × 2
bps
φ: machine clock frequency
X: count clock division ratio for 16-bit reload timer (2, 8, 32)
n: 16-bit reload register setting value for 16-bit timer (0 to 65,535)
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CHAPTER 14 UART0
14.5 Baud Rate of UART0
MB90495G Series
● Example of setting baud rates and reload register setting values (machine clock frequency: 7.3738
MHz)
Table 14.5-4 Baud Rate and Reload Value
Reload Value
Baud Rate
(bps)
Clock Asynchronous (start-stop
synchronization)
Clock Synchronous
X = 21(machine
cycle 2-divided)
X = 23(machine
cycle 8-divided)
X = 21(machine
cycle 2-divided)
X = 23(machine
cycle 8-divided)
38,400
2
−
47
11
19,200
5
−
95
23
9,600
11
2
191
47
4,800
23
5
383
95
2,400
47
11
767
191
1,200
95
23
1,535
383
600
191
47
3,071
767
300
383
95
6,143
1,535
X: Count clock division ratio for 16-bit reload timer
−: Setting disabled
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CHAPTER 14 UART0
14.5 Baud Rate of UART0
MB90495G Series
14.5.3
Baud Rate by External Clock
This section explains the setting when selecting the external clock as the transmit/
receive clock of the UART0.
■ Baud Rate by External Clock
To select a baud rate by the external clock input, the following settings are essential:
• Set the clock input source select bits in the serial mode register (SMR0:CS2 to CS0) to "111B".
• Set the SCK0 pin as the input port in the port direction register (DDR).
• To set the SCK0 pin as an external clock input pin, set the serial clock I/O enable bit (SMR0:SCKE) to
0.
• Set the baud rate on the basis of the external clock input from the SCK0 pin. Since the internal division
ratio is fixed, the cycle of the external input clock must be changed in changing the baud rate.
Figure 14.5-4 Baud Rate Selector by External Clock
SMR0: CS2 to CS0 = "111B"
(Clock input source select bits)
Clock selector
SCK0
1/1 [Clock synchronous]
1/16 [Asynchronous]
Pin
Baud rate
SMR0: MD1, MD0
(Operation mode select bits)
● Expressions to obtain baud rate
Asynchronous baud rate = f/16
Clock synchronous baud rate = f
f: External clock frequency (2 MHz max.)
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CHAPTER 14 UART0
14.6 Operation of UART0
14.6
MB90495G Series
Operation of UART0
The UART0 has master/slave type connection communication function (operation mode
1) in addition to bidirectional serial communication function (operation modes 0 and 2).
■ Operation of UART0
● Operation mode
The UART0 has three types of operation modes.
As shown in Table 14.6-1, they can set the inter-CPU connection mode or data communication mode.
Table 14.6-1 Operation Mode of UART0
Data Length
Operation Mode
No Parity
0
Normal mode
1
Multiprocessor
mode
2
Clock
synchronous
mode
With Parity
7 bits or 8 bits
Synchronous/
Asynchronous
Length of Stop Bit
Asynchronous
8 + 1 *1
−
Asynchronous
8
−
Synchronous
1 bit or 2 bits *2
None
−: Setting disabled
*1: +1 is the address/data bit (A/D) used for controlling communications.
*2: During reception, only one bit can be detected as the stop bit.
Note:
The UART0 operation mode 1 is only used as the master in the master/slave type connection.
● Inter-CPU connection mode
Either 1-to-1 connection or master/slave type connection can be selected for the inter-CPU connection. In
both cases, the data length, parity, synchronous or asynchronous mode, etc., must be the same for all CPUs.
The operation modes are selected as follows.
• For the 1-to-1 connection, the same operation mode (either operation mode 0 or 2) must be adopted for
the two CPUs. For the asynchronous mode, select operation mode 0 (SMR0:MD1, MD0 = "00B"); for
the clock synchronous mode, select operation mode 2 (SMR0:MD1, MD0 = "10B").
• For the master/slave type connection, operation mode 1 (SMR0:MD1, MD0 = "01B") is set; select
operation mode 1 and use it as the master. For this connection, select no parity 8-bit data length.
● Synchronous/asynchronous
For the operation modes, either the asynchronous mode (start-stop synchronization) or the clocksynchronous mode can be selected.
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CHAPTER 14 UART0
14.6 Operation of UART0
MB90495G Series
● Signal mode
The UART0 can only handle the NRZ (Non Return to Zero) data format.
● Start of transmission/reception
• Transmission starts when the transmission enable bit of the serial control register (SCR0:TXE) is set to
1.
• Reception starts when the reception enable bit of the serial control register (SCR0:RXE) is set to 1.
● Stop of transmission/reception
• Transmission stops when the transmission enable bit of the serial control register (SCR0:TXE) is set to
0.
• Reception stops when the reception enable bit of the serial control register (SCR0:RXE) is set to 0.
● Stop during transmission/reception
• When reception is disabled during receiving (during data input to reception shift register) (SCR0:RXE =
0), it stops after reception of the frame being received is completed and the receive data is stored to the
serial input data register 0 (SIDR0).
• When transmission is disabled during transmission (during data output from the transmission shift
register) (SCR0:TXE = 0), it stops after transmission of one frame to the transmission shift register from
the serial output data register 0 (SODR0) is completed.
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CHAPTER 14 UART0
14.6 Operation of UART0
14.6.1
MB90495G Series
Operation in Asynchronous Mode
(Operation Mode 0 or 1)
When the UART0 is used in operation mode 0 (normal mode) or operation mode 1
(multiprocessor mode), the asynchronous transfer mode is selected.
■ Operation in Asynchronous Mode
● Format of transmit/receive data
Transmission and reception always start with the start bit (Low level); transmission and reception are
performed at the specified data bit length on LSB first basis and end with the stop bit (High level).
• In operation mode 0, the data length can be set to 7 or 8 bits. Use of the parity bit can be specified.
• In operation mode 1, the data length is fixed to 8 bits. There is no parity bit. The address/data bit
(SMR0:A/D) is added to bit 9.
Figure 14.6-1 shows the transmit/receive data format in the asynchronous mode.
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CHAPTER 14 UART0
14.6 Operation of UART0
MB90495G Series
Figure 14.6-1 Format of Transmit/receive Data (Operation Mode 0 or 1)
[Operation mode 0]
ST
D0
D1
D2
D3
D4
D5
D7
D8
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
D8
SP
ST
D0
D1
D2
D3
D4
D5
D7
D8
P
P not
provided
Data 8 bits
SP SP
P provided
ST
D0
D1
D2
D3
D4
D5
D7
D8
P
SP
ST
D0
D1
D2
D3
D4
D5
D7
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
SP
ST
D0
D1
D2
D3
D4
D5
D7
P
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
P
SP
P not
provided
Data 7 bits
P provided
[Operation mode 1]
ST
D0
D1
D2
D3
D4
D5
D7
D8
A/D
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
D8
A/D
SP
Data 8 bits
ST :
SP :
P :
A/D :
Start bit
Stop bit
Parity bit
Address/data bit
● Transmission
• Transmit data is written to the serial output data register 0 (SODR0) with the transmit data write flag bit
(SSR0:TDRE) set to 1.
• Transmission starts when transmit data is written and the transmit enable bit of the serial control register
(SCR0:TXE) is set to 1.
• The transmit data write flag bit (SSR0:TDRE) is cleared to 0 temporarily when transmit data is written
to SODR0.
• The transmit data write flag bit (SSR0:TDRE) is set to 1 again once the transmit data is written to the
send shift register from the serial output data register 0 (SODR0).
• When the transmit interrupt enable bit (SSR0:TIE) is set to 1, a send interrupt request is issued once the
send data write flag bit (SSR0:TDRE) is set to 1. The succeeding send data can be written to the serial
output data register 0 (SODR0) at interrupt processing.
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CHAPTER 14 UART0
14.6 Operation of UART0
MB90495G Series
● Reception
• When reception is enabled (SCR:RXE = 1), receiving is always performed.
• When the start bit of receive data is detected, the serial input data register 0 (SIDR0) receives one frame
of data based on the data format set in the serial control register 0 (SCR0).
• At completion of receiving one frame of data, the receive data load flag bit (SSR0:RDRF) is set to 1.
• When the status of the error flag of the serial status register (SSR) is checked to find normal reception at
the completion of one frame of data, read the receive data. When a receive error occurs, perform error
processing.
• The receive data load flag bit (SSR0:RDRF) is cleared to 0 when receive data is read.
● Start bit detection method
Specify settings as follows for start bit detection:
• Immediately before the start of the communication period, be sure to set the communication line to H
(mark level added).
• Set receive ready (RXE=H) while the communication line is at H (mark level).
• Do not set receive ready (RXE=H) during the non-communication period (mark level removed).
Otherwise, data is not received correctly.
• After the stop bit is detected (the RDRF flag is set to 1), set receive not ready (RXE=L) while the
communication line is at H (mark level).
Figure 14.6-2 Normal Operation
Communication period
Non-communication period
Mark level
Start bit
SIN
Non-communication period
Stop bit
Data
ST
D0
D1
D0
D1
D3
D2
D4
D5
D7
D6
SP
(Sending 01010101b)
RXE
Receive clock
Sampling clock
Receive clock (8 pulse)
Recognition by the microcontroller
Generating sampling clocks by dividing the receive clock by 16
ST
D3
D2
D4
D5
D7
D6
SP
(Receiving 01010101b)
Note that if receive ready is set at the timing represented in the following example, input data (SIN) is not
recognized correctly by the microcontroller:
• Example of operation where receive ready (RXE=H) is set while the communication line is at L
Figure 14.6-3 Abnormal Operation
Communication period
Non-communication period
Mark level
SIN
(Sending 01010101b)
RXE
Start bit
Non-communication period
Stop bit
Data
ST
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
SP
SP
Receive clock
Sampling clock
Recognition by the microcontroller
ST recognition
(Receiving 10101010b)
PE,ORE,FRE
Occurrence of a reception error
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CHAPTER 14 UART0
14.6 Operation of UART0
MB90495G Series
● Stop bit
During transmission, one bit or two bits can be selected. However, the receive side always detects only the
first bit.
● Error detection
• In operation mode 0, parity, overrun, and frame errors can be detected.
• In operation mode 1, overrun and frame errors can be detected, but parity errors cannot be detected.
● Parity bit
A parity bit can be set only in operation mode 0. The parity addition enable bit (SCR0:PEN) is used to
specify whether there is parity or not, and the parity select bit (SCR0:P) is used to select odd or even parity.
There is no parity bit in operation modes 1 and 2.
The transmit/receive data when the parity bit enabled are shown in Figure 14.6-4.
Figure 14.6-4 Transmit/Receive Data when Parity Bit Enabled
When receiving
SIN0
ST
SP
1
When transmitting
SOT0
1
1
0
0
1
0
1
ST
1
When transmitting
SOT0
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
SP
Transmission with even parity
(SCR0: PEN = 1, P = 0)
SP
Transmission with odd parity
(SCR0: PEN = 1, P = 1)
0
ST
1
Parity error at reception
with even parity
(SCR0: PEN = 1, P = 0)
1
Data
Parity
ST : Start bit
SP : Stop bit
Note : Parity bit cannot be set in operation modes 1 and 2.
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CHAPTER 14 UART0
14.6 Operation of UART0
14.6.2
MB90495G Series
Operation in Clock Synchronous Mode
(Operation Mode 2)
When the UART0 is used in operation mode 2, the clock synchronous mode is used.
■ Operation in Clock Synchronous Mode (Operation Mode 2)
● Format of transmit/receive data
In the synchronous mode, 8-bit data is transmitted/received on LSB-first, and the start and stop bits are not.
Figure 14.6-5 shows the data format for the clock synchronous mode.
Figure 14.6-5 Format of Transmit/Receive Data (Operation Mode 2)
Outputting serial clock for transmitting
Mark level
SCK0 output
SOT0
(LSB)
1
0
1
1
0
0
1
0
(MSB)
Transmit data
Write transmit data
TXE
Inputting serial clock for receiving
Mark level
SCK0 input
SIN0
(LSB)
1
0
1
1
0
0
1
0
(MSB)
Receive data
RXE
Read receive data
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CHAPTER 14 UART0
14.6 Operation of UART0
MB90495G Series
● Clock supply
In the clock synchronous mode, count of clocks equal to the transmit and receive bits count must be
supplied.
• When the internal clock (dedicated baud rate generator or internal timer) has already selected
(CMR0:CS2 to CS0 = "000B" to "100B" or "110B") and data is transmitted, the synchronous clock for
data reception is generated automatically.
• When the external clock has already selected (SMR0:CS2 to CS0 = "111B"), the clock for exact one
byte must be supplied from outside after ensuring that data is present (SSR0:TDRE = 0) in the serial
output data register (SODR0). Also, before and after transmitting, always return to the mark level (High
level).
● Error detection
Only overrun errors can be detected; parity and framing errors cannot be detected.
● Setting of register
Table 14.6-2 shows the setting of the control register in transmitting serial data from the transmitting end to
the receiving end using the clock synchronous mode (operation mode 2).
Table 14.6-2 Setting of Control Register
Setting
Register
Name
Serial mode
register 0
(SMR0)
Serial status
register 0
(SSR0)
Bit Name
MD1, MD0
CM44-10114-7E
Receive End
(Input serial clock)
Set clock synchronous mode (MD1, MD0 = "10B").
CS2, CS1, CS0
Set clock input source.
• Dedicated baud rate generator (CS2
to CS0 = "000B" to "100B")
• Internal timer (CS2 to CS0 =
"110B")
Set clock input source.
• External clock (CS2 to CS0 =
"111B")
SCKE
Set serial clock output (SCKE = 1).
Set serial clock input (SCKE = 0).
SOE
Set serial data output pin (SOE = 1).
Set general-purpose I/O port (SOE = 0).
PEN
Do not add parity bit (PEN = 0).
CL
REC
Serial status
register 0
(SSR0)
Transmit End
(Output serial clock)
8-bit data length (CL = 1)
Initialize error flag (REC = 0).
TXE
Enable transmitting (TXE = 1).
Disable transmitting (TXE = 0).
RXE
Disable receiving (RXE = 0).
Enable receiving (RXE = 1).
TIE
Enable transmitting (TIE = 1).
Disable transmitting (TIE = 0).
RIE
Disable receiving (RIE = 0).
Enable receiving (RIE = 1).
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CHAPTER 14 UART0
14.6 Operation of UART0
MB90495G Series
● Starting communications
When send data is written to the serial output data register 0 (SODR0), communication starts. When
starting communication only in receiving, it is always necessary to write dummy send data to the serial
output data register 0 (SODR0).
● Terminating communications
After transmitting and receiving of one frame of data, the receive data load flag bit (SSR0:RDRF) is set to
1. When data is received, check the overrun error flag bit (SSR0:ORE) to ensure that the communication
has performed normally.
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CHAPTER 14 UART0
14.6 Operation of UART0
MB90495G Series
14.6.3
Bidirectional Communication Function
(Operation Modes 0 and 2)
In operation modes 0 and 2, serial bidirectional communications using 1-to-1
connection can be performed. For operation mode 0, the asynchronous mode is used;
for operation mode 2, the synchronous mode is used.
■ Bidirectional Communication Function
To operate the UART0 in the operation mode 0 or 2, the setting shown in Figure 14.6-6 is required.
Figure 14.6-6 Setting of Operation Modes 0 and 2
bit 15 14
13
12
11
10
9 bit 8 bit 7 6
5
4
3
2
1 bit 0
PEN P SBL CL AD REC RXE TXE MD1 MD0 CS2 CS1 CS0 Reserved SCKE SOE
SCR0, SMR0
Operation mode 0
Operation mode 2
SSR0,
SIDR0/SODR0
Operation mode 0
Operation mode 2
×
0
×
1
×
×
0
0
PE ORE FRE RDRFTDRE ⎯ RIE TIE
×
0
1
0
0
0
0
Setting of transmit data (at write)
/Retention of receive data (at read)
×
DDR port-direction register
⎯ :
:
× :
1 :
0 :
Unused bit
Used bit
Undefined bit
Set 1
Set 0
Set the bit to 0 corresponding to pin
used as SIN0 and SCK 0 input pins.
● Inter-CPU connect
Connect the two CPUs as shown in Figure 14.6-7.
Figure 14.6-7 Example of Bidirectional Communication Connect for UART0
SOT0
SOT0
SIN0
SCK0
SIN0
Output
Input
SCK0
CPU-1
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CPU-2
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CHAPTER 14 UART0
14.6 Operation of UART0
MB90495G Series
● Communication procedure
Communications start at any timing from the transmitting end when transmit data is provided. At the
transmitting end, set transmit data in the serial output data register 0 (SODR0) and set the transmitting
enable bit in the serial control register (SCR0:TXE) to 1 to start transmitting.
Figure 14.6-8 gives an example of transferring receive data to the transmitting end to inform the
transmitting end of normal reception.
Figure 14.6-8 Flowchart for Bidirectional Communication
(Transmit end)
(Receive end)
Start
Start
Set the operation mode
(0, 1 or 2)
Set the operation mode
(same as transmit end)
Set the 1-byte data in
SODR 0 to communicate
Data transmission
NO
Receive data
presence
YES
NO
Receive data
presence
Read and process
receive data
YES
Read and process
receive data
456
Data transmission
Transmit 1-byte data
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 14 UART0
14.6 Operation of UART0
MB90495G Series
14.6.4
Master/Slave Type Communication Function
(Multiprocessor Mode)
Operation mode 1 enables communications by the master/slave type connection of
more than one CPU. Only the master CPU functions.
■ Master/Slave Communication Function
To operate the UART0 in the operation mode 1, the setting shown in Figure 14.6-9 is required.
Figure 14.6-9 Setting of Operation Mode 1 for UART0
bit15 14
13
12
11
10
9 bit8 bit7 6
5
4
3
2
1 bit0
PEN P SBL CL AD REC RXE TXE MD1 MD0 CS2 CS1 CS0 Reserved SCKE SOE
SCR0, SMR0
0
SSR0,
SIDR0/SODR0
×
1
0
PE ORE FRE RDRFTDRE ⎯ RIE TIE
×
0
1
0
0
Setting of transmit data (at write)
/Retention of receive data (at read)
DDR port-direction register
⎯ :
:
× :
1 :
0 :
Unused bit
Used bit
Undefined bit
Set 1
Set 0
Set the bit to 0 corresponding to pin
used as SIN0 and SCK 0 input pins.
● Inter-CPU connect
One master CPU and more than one slave CPU are connected to two common communication lines to
compose the communication system. The UART0 can be used only as the master CPU.
Figure 14.6-10 Example of Master/Slave Communication Connect for UART0
SOT
SIN
Master CPU
SOT
SIN
Slave CPU #0
CM44-10114-7E
SOT
SIN
Slave CPU #1
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CHAPTER 14 UART0
14.6 Operation of UART0
MB90495G Series
● Function select
At master/slave type communication, select the operation mode and data transfer type.
Since the parity check function cannot be used in operation mode 1, set the parity enable bit (SCR0:PEN)
to 0.
Table 14.6-3 Select of Master/Slave Communication Function
Operation Mode
Master
CPU
Address
transmit/
receive
Data
transmit/
receive
458
Slave
CPU
Operation
mode 1
−
Data
A/D = 1
+
8-bit address
A/D = 0
+
8-bit data
Parity
Synchronous
System
Stop Bit
Not
provided
Asynchronous
1 bit or 2 bits
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CM44-10114-7E
CHAPTER 14 UART0
14.6 Operation of UART0
MB90495G Series
● Communication procedure
Communications start when the master CPU transmits address data.
The address data is data with the A/D bit set to 1. The address data bit (SCR0:A/D) is added to select the
slave CPU that the master CPU communicates with. When the program identifies address data and finds a
match with the allocated address, each slave CPU starts communications with the master CPU.
Figure 14.6-11 shows the flowchart for master/slave communications.
Figure 14.6-11 Flowchart for Master/Slave Communications
(Master CPU)
Start
Set operation mode to 1
Set the SIN pin
to serial data input
Set 1-byte data (address
data) that selects the
slave CPU to D0 to D7
to transmit (A/D = 1)
Set 0 to A/D
Reception enabled
Communicate
with slave CPU
Communication
ended?
NO
YES
Communication
with other slave
CPU
NO
YES
Reception disabled
End
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CHAPTER 14 UART0
14.7 Precautions when Using UART0
14.7
MB90495G Series
Precautions when Using UART0
Use of the UART0 requires the following cautions.
■ Precautions when Using UART0
● Enabling sending and receiving
The send enable bit (SCR0:TXE) and receive enable bit (SCR0:RXE) are provided for sending and
receiving.
• In the initial state after reset, both sending and receiving are disabled (SCR0:TXE = 0, RXE = 0).
Therefore, it is necessary to enable sending and receiving.
• Sending and receiving are disabled to stop (SCR0:TXE = 0, RXE = 0).
● Setting operation mode
Set the operation mode after disabling sending and receiving (SCR0:TXE = 0, RXE = 0). When the
operation mode is changed during sending and receiving, the sent and received data is not assured.
● Clock synchronous mode
Operation mode 2 is set as the clock synchronous mode. Send and receive data do not have the start and
stop bits.
● Timing of enabling send interrupt
Since the send data write flag bit (SSR0:TDRE) is set at 1 (no send data, send data write enabled).
Therefore, the send interrupt is enabled (SSR0:TIE = 1) and a send interrupt request is issued
simultaneously. Always prepare send data and enable a send interrupt (SSR0:TIE = 1).
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CM44-10114-7E
CHAPTER 15
UART1
This chapter explains the function and operation of the
UART1.
15.1 Overview of UART1
15.2 Block Diagram of UART1
15.3 Configuration of UART1
15.4 Interrupt of UART1
15.5 Baud Rate of UART1
15.6 Explanation of Operation of UART1
15.7 Precautions when Using UART1
15.8 Program Example for UART1
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CHAPTER 15 UART1
15.1 Overview of UART1
15.1
MB90495G Series
Overview of UART1
The UART1 is a general-purpose serial-data communication interface for synchronous
or asynchronous communication with external devices.
• Incorporates a bidirectional communication function
(clock synchronous and asynchronous modes)
• Incorporates a master/slave type communication function
(in multiprocessor mode: only master)
• Can generate an interrupt request at completion of transmitting and receiving, and at
detection of a receive error
• Supports expansion intelligent I/O service (EI2OS)
■ Function of UART1
● Function of UART1
The UART1 is a general-purpose serial-data communication interface, which transmits/receives serial data
with external devices. UART1 has functions listed in Table 15.1-1.
Table 15.1-1 Function of UART1
Function
Data buffer
Full-duplicate double-buffer
Transfer mode
• Synchronous to clock (without start bit/stop bit and parity bit)
• Asynchronous (start-stop synchronization to clock)
Baud rate
• Dedicated baud-rate generator (The baud rate can be selected
from among ten types.)
• Any baud rate can be set by external clock.
• A clock supplied from the internal clock (16-bit reload timer 1)
can be used.
Data length
• 7 bits (for asynchronous normal mode only)
• 8 bits
Signal type
NRZ (Non Return to Zero) type
Detection of receive error
Interrupt request
• Framing error
• Overrun error
• Parity error (not supported for operation mode 1)
• Receive interrupt (receive, detection of receive error)
• Transmit interrupt (transmit)
• Both the transmission and reception support EI2OS.
Master/slave type communication This function enables communications between 1 (only use master)
function (multiprocessor mode) and n (slave) (This function is used only as the master side)
Note:
462
At the clock synchronous transfer, the UART only transfers data, not affixing the start and stop bits.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 15 UART1
15.1 Overview of UART1
MB90495G Series
Table 15.1-2 Operation Mode of UART1
Data Length
Operation Mode
With Parity
0
Asynchronous mode
(Normal mode)
1
Multiprocessor mode
2
Synchronous mode
No Parity
7 or 8 bits
Synchronous/
Asynchronous
Length of
Stop Bit
Asynchronous
1 bit or 2 bits *2
8 + 1 *1
−
Asynchronous
8
−
Synchronous
None
−: Setting disabled
*1: +1 is the address/data select bit (SCR1 register bit 11: A/D) used for controlling communications.
*2: During reception, only one bit can be detected as the stop bit.
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CHAPTER 15 UART1
15.2 Block Diagram of UART1
15.2
MB90495G Series
Block Diagram of UART1
The UART1 consists of the following block.
■ Block Diagram of UART1
Figure 15.2-1 Block Diagram of UART1
Control bus
Dedicated baud
rate generator
16-bit reload
timer
Receive interrupt
request output
Transmit interrupt
request output
Transmit clock
Clock
selector
Receive clock
Pin
SCK1
Receive
controller
Transmit
controller
Start bit
detector
Transmit
start circuit
Receive bit
counter
Transmit bit
counter
Receive parity
counter
Transmit parity
counter
Pin
SOT1
Transmit
shift register
Receive
shift register
Pin
SIN1
Reception state
determine circuit
Serial input
data register 1
End of
reception
Serial output
data register 1
Start of reception
Receive-errorgenerate signal
for EI2OS (to CPU)
Internal data bus
Communication
prescaler
control
register
464
MD
DIV3
DIV2
DIV1
DIV0
Serial
mode
register 1
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
Serial
control
register 1
PEN
P
SBL
CL
A/D
REC
RXE
TXE
FUJITSU SEMICONDUCTOR LIMITED
Serial
status
register 1
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
CM44-10114-7E
CHAPTER 15 UART1
15.2 Block Diagram of UART1
MB90495G Series
● Details of pins, etc., in block diagram
The actual pin names and interrupt request numbers used in the UART1 are as follows:
SIN1 pin: P40/SIN1
SCK1 pin: P41/SCK1
SOT1 pin: P42/SOT1
Transmit interrupt number 1: #38 (26H)
Receive interrupt number 1: #37 (25H)
● Clock selector
The clock selector selects the transmit/receive clock from the dedicated baud rate generator, external input
clock, and internal clock (clock supplied from 16-bit reload timer).
● Receive controller
The receive controller is composed of receive bit counter, start bit detector and receive parity counter. The
receive bit counter counts the receive data, and outputs a receive interrupt request when reception of one
piece of data is completed.
The start bit detector detects the start bit from the serial input signal and writes the received data to the
serial input data register, on a bit-by-bit shift basis in accordance with the transfer rate.
● Transmit controller
The transmit controller is composed of the transmit bit counter, transmit start circuit, and transmit parity
counter. The transmit bit counter counts the transmit data, and outputs a transmit interrupt request when
transmission of one piece of data is completed according to the set data length. The transmit start circuit
starts transmission when serial output data register (SODR1) is written. The transmit parity counter
generates the parity bit of the data transferred when parity is provided.
● Receive shift register
The receive shift register writes the receive data input from the SIN pin while shifting bit-by-bit, and when
the data reception is completed, it transfers the receive data to the serial input data register (SIDR1).
● Transmit shift register
Data written to SODR1 is transferred to the transmit shift register itself, and then the data is output to the
SOT pin while shifting bit-by-bit.
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CHAPTER 15 UART1
15.2 Block Diagram of UART1
MB90495G Series
● Serial mode register 1 (SMR1)
This register:
• Selects operation mode
• Selects clock input source (baud rate)
• Sets dedicated baud rate generator
• Selects clock speed (clock division value) when using dedicated baud rate generator
• Enables or disables output of serial data and clock pins
• Initialize UART1
● Serial control register 1 (SCR1)
This register:
• Sets availability of parity
• Selects type of parity
• Sets stop bit length
• Sets data length
• Selects frame data format in operation mode 1 (asynchronous multiprocessor mode)
• Clears error flag
• Enables or disables transmitting
• Enables or disables receiving
● Serial status register 1 (SSR1)
The status register checks the transmission/reception state and error state and sets enabling/disabling of the
transmit/receive interrupt request.
● Serial input data register 1 (SIDR1)
The serial input data register retains the receive data. The serial input is converted and then stored in this
register.
● Serial output data register 1 (SODR1)
The serial output data register sets the transmit data. Data written to this register is serial-converted and
then output.
● Communication prescaler control register (CDCR)
The control register sets the baud rate of the baud rate generator, which sets the start/stop of the
communication prescaler and the division rate of machine clock.
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CHAPTER 15 UART1
15.3 Configuration of UART1
MB90495G Series
15.3
Configuration of UART1
The UART1 pins, interrupt factors, register list and details are shown.
■ UART1 Pin
The pins used in the UART1 serve as general-purpose I/O port.
Table 15.3-1 indicates the pin functions and the setting necessary for use in the UART1.
Table 15.3-1 UART1 Pin
Pin
Name
Pin Function
SOT1
General-purpose I/O port,
serial data output
SCK1
General-purpose I/O port,
serial clock output input/
output
SIN1
General-purpose I/O port,
serial data input
Setting Necessary for Use in UART1
Set to output enable. (SMR1 register bit 0: SOE=1)
In clock input, set pin as input port in port direction
register (DDR).
In clock output, set to output enable. (SMR register
bit 1: SCKE=1)
Set pin as input port in DDR.
■ Block Diagram of Pins of UART1
See "CHAPTER 4 I/O PORT" for the block diagram of pins.
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CHAPTER 15 UART1
15.3 Configuration of UART1
MB90495G Series
■ List of Registers in UART1
Figure 15.3-1 List of Registers and Reset Values in UART1
bit
Serial control register 1 (SCR1)
bit
Serial mode register 1 (SMR1)
bit
Serial status register 1 (SSR1)
bit
Serial input data register 1 (SIDR1)
/Serial output data register 1 (SODR1)
15
14
13
12
11
10
9
8
0
0
0
0
0
1
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
1
0
0
0
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
Note: Function as SIDR1 when reading, function as SODR1 when writing
bit
Communication prescaler control register 1
(CDCR1)
15
14
13
12
11
10
9
8
0
×
×
×
0
0
0
0
×: Undefined
■ Interrupt Request Generation by UART1
● Receive interrupt
• When receive data is loaded to the serial input data register (SIDR1), the receive data load flag bit
(bit12:RDRF) in the serial status register (SSR1) is set to 1. When a receive interrupt is enabled (bit
9:RIE = 1), a receive interrupt request is generated to the interrupt controller.
• When either a framing error, overrun error, or parity error occurs, the framing error flag bit (bit13:FRE),
the overrun error flag bit (bit14:ORE), or parity error flag bit (bit15:PE) in the serial status register
(SSR1) are set to 1 according to the error occurred. When a receive interrupt is enabled (bit9:RIE = 1), a
receive interrupt is requested to the interrupt controller.
● Transmit interrupt
When transmit data is transferred from the serial output data register (SODR1) to the transmit shift register,
the transmit data empty flag bit (bit11:TDRE) in the serial status register (SSR1) is set to 1. If a transmit
interrupt is enabled (bit8:TIE = 1), a transmit interrupt is requested.
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CM44-10114-7E
CHAPTER 15 UART1
15.3 Configuration of UART1
MB90495G Series
15.3.1
Serial Control Register 1 (SCR1)
The serial control register 1 (SCR1) performs the following:
setting parity bit, selecting stop bit length and data length, selecting frame data format
in operation mode 1, clearing receive error flag, and enabling/disabling of transmitting/
receiving.
■ Serial Control Register 1 (SCR1)
Figure 15.3-2 Serial Control Register 1 (SCR1)
15
14
13
12
11
10
9
8
Reset value
00000100 B
R/W R/W R/W R/W R/W
W
R/W R/W
bit 8
Transmit enable bit
TXE
Transmit disable
0
Transmit enable
1
bit 9
RXE
Receive disable
0
Receive enable
1
Receive enable bit
bit 10
Receive error flag clear bit
REC
Clear PE and ORE, FRE, bits
0
No effect
1
bit 11
Address/data select bit
A/D
Data frame
0
Address frame
1
bit 12
CL
7 bits
0
8 bits
1
bit 13
SBL
1-bit length
0
2-bit length
1
Data-length select bit
Stop-bit length select bit
bit 14
P
0
1
R/W : Read/Write
W
: Write only
: Reset value
CM44-10114-7E
Parity select bit
Enable only when parity provided (PEN = 1)
Even parity
Odd parity
bit 15
PEN
No parity
0
With parity
1
Parity addition enable bit
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CHAPTER 15 UART1
15.3 Configuration of UART1
MB90495G Series
Table 15.3-2 Function of Serial Control Register 1 (SCR1)
Bit Name
470
Function
bit 8
TXE:
Transmit enable bit
Enable or disable the UART1 for sending.
When set to 0: Transmission disabled
When set to 1: Transmission enabled
Note:
When transmitting is disabled during transmitting, transmitting stops after
the data in the serial input data register being transmitted is completed in the
serial input data register. To set this bit to 0, after writing data to SODR1,
wait for a time of 1/16th of the baud rate in the asynchronous mode and for a
time equal to or more than the baud rate in the synchronous mode.
bit 9
RXE:
Receive enable bit
Enable or disable the UART1 for receiving.
When set to 0: Reception disabled
When set to 1: Reception enabled
Note:
When receiving is disabled during receiving, receiving stops after the data
being received is stored in the serial input data register.
bit 10
REC:
Receive error flag clear
bit
Clear the receive error flags (bit15 to 13:PE, ORE and FRE) of the serial status
register (SSR1) to 0.
When set to 0: Clears PE, ORE and FRE flags
When set to 1: No effect
When read: 1 always read
Note:
When a receive interrupt is enabled (bit9:RIE = 1), set the bit10:REC bit to 0
only when any one of the PE, ORE and FRE flags is set to 1.
bit 11
A/D:
Address/data select bit
In operation mode 1 (asynchronous multiprocessor mode), set the data format of
the frame to be transmitted/received.
When bit set to 0: Data frame set
When bit set to 1: Address data frame set
bit 12
CL:
Data-length select bit
Specify the length of send and receive data.
Note:
A data length of 7 bits can be selected only in operation mode 0
(asynchronous normal mode). In operation modes 1 and 2 (asynchronous
multiprocessor mode, Clock synchronous mode), be sure to set a data length
of 8 bits.
bit 13
SBL:
Stop-bit length select bit
Set the length of the stop bit (frame end mark of send data) in operation modes 0
and 1 (multiprocessor mode, synchronous mode).
Note:
At receiving, only the first bit of the stop bit is always detected.
bit 14
P:
Parity select bit
Select either odd or even parity when with parity (PEN = 1) is set.
bit 15
PEN:
Parity addition enable bit
Specify whether to add (at sending) and detect (at receiving) a parity bit.
Note:
A parity bit is not added in operation modes 1 and 2 (Multiprocessor mode,
Synchronous mode). Be sure to set this bit to 0.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 15 UART1
15.3 Configuration of UART1
MB90495G Series
15.3.2
Serial Mode Register 1 (SMR1)
The serial mode register 1 (SMR1) performs selecting operation mode, selecting baud
rate clock, and disabling/enabling of output of serial data and clock to pin.
■ Serial Mode Register 1 (SMR1)
Figure 15.3-3 Serial Mode Register 1 (SMR1)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
Serial data output enable bit (SOT1 pin)
SOE
Serves as general-purpose I/O port
0
Serves as serial data output of UART1
1
bit 1
SCKE
Serial clock I/O enable bit (SCK1 pin)
0
1
Serves as general-purpose I/O port or clock input pin of UART 1
Serves as serial clock output pin of UART1
bit 2
URT
0
1
UART1 Reset bit
No effect on operation
Resets all registers in UART1
bit 5 bit 4 bit 3
CS2 CS1 CS0
Clock input source select bits
"000B" to "100B" Baud rate by dedicated baud rate generator
Setting disable
"101B"
Baud rate by internal timer
"110B"
(16-bit reload timer1)
"111B"
bit 7
MD1 MD0
R/W : Read/Write
: Reset value
CM44-10114-7E
Baud rate by external clock
bit6
Operation mode select bits
Mode No.
Operation mode
0
0
0
Asynchronous mode (normal mode)
0
1
1
Asynchronous multiprocessor mode
1
0
2
Clock synchronous mode
1
1
⎯
Setting disable
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CHAPTER 15 UART1
15.3 Configuration of UART1
MB90495G Series
Table 15.3-3 Function of Serial Mode Register 1 (SMR1)
Bit Name
Function
bit 0
SOE:
Serial-data output enable
bit
Enable or disable output of serial data.
When set to 0: General-purpose I/O port set
When set to 1: Serial data output pin set
bit 1
SCKE:
Serial clock I/O enable
bit
Switch between input and output of the serial clock.
When set to 0: General-purpose I/O port or serial clock input pin set
When set to 1: Serial clock output pin set
Notes:
1. When using the SCK1 pin as the serial clock input, set the pin to the input
port using the port direction register (DDR). Also select the external clock
(bit5 to 3:CS2 to CS0 = "111B") using the clock input source select bit.
2. When using the SCK pin as the serial clock output, set the clock input
source select bit to anything other than the external clock (bit5 to 3:CS2 to
CS0 = anything other than "111B").
bit 2
RST: UART1 Reset bit
This bit resets all registers in the UART1.
When set to 0: No effect on operation
When set to 1: Resets all registers in UART1
CS0 to CS2:
Clock input source select
bits
Set the clock input source for the baud rate.
• Select the external clock (SCK1 pin), internal timer (16-bit reload timer),
or dedicated baud rate generator as the clock input source.
• Set the baud rate when selecting the dedicated baud rate generator.
bit 6 and bit 7
MD0, MD1:
Operation mode select
bits
Select the UART1 operation mode.
Notes:
1. In operation mode 1 (asynchronous multiprocessor mode), only the
master can be used for master/slave communication. In operation mode 1,
the address/data bit on bit 9 cannot be received, so the slave cannot be
used.
2. In operation mode 1 (asynchronous multiprocessor mode), the parity
check function cannot be used, set the parity addition enable bit to no
parity (SCR1 register bit15:PEN = 0).
Note:
When 0 is written to the RST bit of Serial Mode Register, the interruption UART should be prohibited.
To prohibit the interruption, take one of the following procedures:
1. Before writing 0 to the RST bit, clear I flag to prohibit all interrupt factors.
2. Before writing 0 to the RST bit, prohibit the UART interruption with the ILM register.
3. When 0 is written to the RST bit, writing should be performed at the UART interruption level or the level
with higher priority than the UART interruption.
bit 3 to bit 5
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CM44-10114-7E
CHAPTER 15 UART1
15.3 Configuration of UART1
MB90495G Series
15.3.3
Serial Status Register 1 (SSR1)
The serial status register 1 (SSR1) checks the transmission/reception status and error
status and enables/disables interrupts.
■ Serial Status Register 1 (SSR1)
Figure 15.3-4 Serial Status Register 1 (SSR1)
15
14
13
12
11
R
R
R
R
R
10
9
8
Reset value
00001000 B
R/W R/W R/W
bit 8
TIE
0
1
Disables transmit interrupt
Enables transmit interrupt
bit 9
RIE
0
1
Disables receive interrupt
Enables receive interrupt
bit 10
BDS
0
1
bit 11
TDRE
0
1
bit 12
RDRF
0
1
Transmit interrupt enable bit
Receive interrupt enable bit
Transfer direction select bit
LSB first (transfer from least significant bit)
MSB first (transfer from most significant bit)
Transmit data writing flag bit
With transmit data (write of transmit data disabled)
No transmit data (write of transmit data enabled)
Receive data load flag bit
No receive data
With receive data
bit 13
Framing error flag bit
FRE
No framing error
0
With framing error
1
bit 14
Overrun error flag bit
ORE
0
No overrun error
1
With overrun error
bit 15
PE
0
No parity error
1
With parity error
Parity error flag bit
R/W : Read/Write
R
: Read only
: Reset value
CM44-10114-7E
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CHAPTER 15 UART1
15.3 Configuration of UART1
MB90495G Series
Table 15.3-4 Function of Serial Status Register 1 (SSR1)
Bit Name
474
Function
bit 8
TIE:
Transmit interrupt request
enable bit
Enable or disable send interrupt.
When set to 1: A receive interrupt request is issued when data written to the serial output
data register 1 (SODR1) is sent to the transmit shift register (bit 11:TDRE
= 1).
bit 9
RIE:
Receive interrupt request
enable bit
Enable or disable receive data.
When set to 1: A receive interrupt request is issued when receive data is loaded to the
serial input data register 1 (SIDR1) (bit12:RDRF = 1) or when a receive
error occurs (bit15:PE = 1, bit14:ORE = 1, or bit13:FRE = 1).
bit 10
BDS:
Transfer direction select bit
This bit sets the direction of serial data transfer.
When set to 0: Transfers data from least significant bit (LSB first)
When set to 1: Transfers data from most significant bit (MSB first)
Note:
At reading and writing data from and to the serial data register, data is written to the
serial output data register (SODR1) and then the transfer direction select bit (BDS) is
rewritten to switch between the upper bits and the lower bits of data. In this case, the
written data becomes invalid.
bit 11
TDRE:
Transmit data write flag bit
Show the status of the serial output data register 1.
• This bit is cleared to 0 when send data is written to the serial output register 1(SODR1).
• This bit is set to 1 when data is loaded to the send shift register and transmission starts.
• When a transmission interrupt is enabled (bit8:TIE = 1), a transmit interrupt request is
issued when data written to the serial output data register 1(SODR1) is transmitted to
the transmit shift register (bit11:TDRE=1).
bit 12
RDRF:
Receive data load flag bit
Show the status of the serial input data register 1 (SIDR1).
• This bit is set to 1 when receive data is loaded to the serial input register 1 (SIDR1).
• This bit is cleared to 0 when data is read from the SIDR1.
• When a receive interrupt is enabled (bit9:RIE = 1), a receive interrupt request is issued
when receive data is loaded to the serial input data register 1 (SIDR1).
bit 13
FRE:
Framing error flag bit
Detect a framing error in receive data.
• This bit is set to 1 when a framing error occurs.
• This bit is cleared when 0 is written to the receive error flag clear bit (SCR1 register
bit10:REC).
• When a receive interrupt is enabled (bit9:RIE = 1), a receive interrupt request is issued
when a framing error occurs.
• When the framing error flag bit is set (bit13:FRE = 1), data in the serial input data
register 1 (SIDR1) is invalid.
bit 14
ORE:
Overrun error flag bit
Detect an overrun error in receiving.
• This bit is set to 1 when an overrun error occurs.
• This bit is cleared when 0 is written to the receive error flag clear bit (SCR1 register
bit10:REC).
• When a receive interrupt is enabled (bit9:RIE = 1), a receive interrupt request is issued
when an overrun error occurs.
• When the overrun error flag bit is set (bit14:ORE = 1), data in the serial input data
register (SIDR1) is invalid.
bit 15
PE:
Parity error flag bit
Detect an overrun error in receiving.
• This bit is set to 1 when a parity error occurs.
• This bit is cleared when 0 is written to the receive error flag clear bit (SCR1 register
bit10:REC).
• When a receive interrupt is enabled (bit9:RIE = 1), a receive interrupt request is issued
when a parity error occurs.
• When the parity error flag bit is set (bit15:PE = 1), data in the serial input data register
1 (SIDR1) is invalid.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 15 UART1
15.3 Configuration of UART1
MB90495G Series
15.3.4
Serial Input Data Register 1 (SIDR1) and Serial Output
Data Register 1 (SODR1)
The serial input data register (SIDR1) and serial output data register (SODR1) are
allocated to the same address. At read, the register functions as SIDR1. At write, the
register functions as SODR1.
■ Serial Input Data Register 1 (SIDR1)
Figure 15.3-5 Serial Input Data Register 1 (SIDR1)
bit 7
6
5
4
3
2
1
bit 0
Reset value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXX B
R
R
R
R
R
R
R
R
R: Read only
X: Undefined
SIDR1 is a data buffer register for receiving serial data.
• The serial data signal transmitted to the serial input pin (SIN1) is converted by the shift register and
stored in SIDR1.
• When the data length is 7 bits, the upper one bit (SIDR1:D7) becomes invalid.
• When receive data is stored in the serial input data register 1 (SIDR1), the receive data load flag bit
(SSR1 register bit12:RDRF) is set to 1. When a receive interrupt is enabled (SSR1 register bit9:RIE =
1), a receive interrupt request is issued.
• Read SIDR1 when the receive data load flag bit (SSR1 register bit12:RDRF) is set to 1. The receive data
load flag bit (SSR1 register bit12:RDRF) is cleared to 0 automatically when SIDR1 is read.
• When a receive error occurs (any one of SSR1 register bit15, 14, 13:PE, ORE and FRE is 1), the receive
data in SIDR1 becomes invalid.
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CHAPTER 15 UART1
15.3 Configuration of UART1
MB90495G Series
■ Serial Output Data Register 1 (SODR1)
Figure 15.3-6 Serial Output Data Register 1 (SODR1)
7
6
5
4
3
2
1
bit 0
Reset value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXX B
W
W
W
W
W
W
W
W
W: Write only
X: Undefined
The serial output data register 1 (SODR1) is a data buffer register for transmitting serial data.
• When data to be transmitted is written to SODR1 when transmission is enabled (SCR1 register
bit8:TXE = 1), it is transferred to the transmit shift register, converted to serial data, and transmit from
the serial data output pin (SOT1).
• When the data length is 7 bits, the upper one bit (SODR1 register bit7:D7) becomes invalid.
• The transmit data write flag (SSR1 register bit11:TDRE) is cleared to 0 when send data is written to
SODR1.
• The transmit data write flag is set to 1 at completion of data transfer to the transmit shift register.
• When the transmit data write flag (SSR1 register bit11:TDRE) is 1, the transmit data can be written.
When a transmit interrupt is enabled (SSR1 register bit8:TIE=1), a transmit interrupt occurs. The
transmit bit data should be written with the transmit data write flag (SCR1 register bit11:TDRE) at 1.
Note:
476
Serial output data register is a write-only register and serial input data register is a read-only register.
However, since they are allocated to the same address, the write and read values are different. Therefore,
do not use instructions that perform read-modify-write (RMW) operation such as INC and DEC
instructions.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 15 UART1
15.3 Configuration of UART1
MB90495G Series
15.3.5
Communication Prescaler Control Register 1 (CDCR1)
The communication prescaler control register 1 (CDCR1) is used to set the baud rate of
the dedicated baud rate generator for the UART1.
• Starts/stop the communication prescaler
• Sets the division ratio for machine clock
■ Communication Prescaler Control Register 1 (CDCR1)
Figure 15.3-7 Communication Prescaler Control Register 1 (CDCR1)
15
14
13
12
11
10
9
8
R/W ⎯
⎯
⎯ R/W R/W R/W R/W
Reset value
0XXX0000 B
bit 10 bit 9 bit 8
DIV2 DIV1 DIV0
Communication prescaler division ratio (div) bits
0
0
0
1-divided clock
0
0
1
2-divided clock
0
1
0
3-divided clock
0
1
1
4-divided clock
1
0
0
5-divided clock
1
0
1
6-divided clock
1
1
0
7-divided clock
1
1
1
8-divided clock
bit 11
Reserved bit
Reserved
0
bit 15
MD
R/W : Read/Write
X
: Undefined
⎯
: Unused
: Reset value
CM44-10114-7E
0
1
Always set 0
Communication prescaler control bit
Communication prescaler stopped
Communication prescaler enabled
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CHAPTER 15 UART1
15.3 Configuration of UART1
MB90495G Series
Table 15.3-5 Functions of Communication Prescaler Control Register 1 (CDCR1)
Bit Name
Function
bit 8 to bit 10
DIV0 to DIV2:
Communication
prescaler division ratio
bits
• These bits set the machine clock division ratio.
Note:
When changing the division ratio, the time of at least one 1/2-frequency
division of the division clock should be allowed before the next
communication is started in order to stabilize the clock frequency.
bit 11
Reserved: Reserved bit
Be sure to set this bit to 0.
bit 12 to bit 14
Unused bits
Read: The value is not fixed.
Write: No effect
MD:
Communication
prescaler
control bit
This bit enables or disables the communication prescaler.
When set to 0: Stops communication prescaler
When set to 1: Operates communication prescaler
bit 15
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CHAPTER 15 UART1
15.4 Interrupt of UART1
MB90495G Series
15.4
Interrupt of UART1
The UART1 has a receive and a transmit interrupts, and the following factors can issue
interrupt requests.
• Receive data is loaded to the serial input data register 1 (SIDR1).
• A receive error (parity error, overrun error, framing error) occurs.
• When send data transferred from the output data register 1 (SODR1) to transmit shift
register
Also, each of these interrupt factors supports the expansion intelligent I/O service
(EI2OS).
■ Interrupt of UART1
The UART1 interrupt control bits and interrupt factors are shown in Table 15.4-1.
Table 15.4-1 UART1 Interrupt Control Bit and Interrupt Factor
Trans-mission/
Reception
Reception
Transmission
Interruptrequest Flag Bit
Operation
Mode
Interrupt Factor
0
1
2
SSR1:RDRF
Ο
Ο
Ο
Receive data loaded into
serial input data register
1 (SIDR1)
SSR1:ORE
Ο
Ο
Ο
Overrun error
SSR1:FRE
Ο
Ο
X
Framing error
SSR1:PE
Ο
X
X
Parity error
Ο
Transfer of transmit data
completed from serial
output data register
(SODR1)
SSR1:TDRE
Ο
Ο
Interrupt
Factor
Enable Bit
Clear of the
Interruptrequest Flag
Reading receive
data
SSR1:RIE
SSR1:TIE
Writing 0 to
receive error flag
clear bit (SCR1
register
bit10:REC)
Writing transmit
data
Ο: Used bit
X: Unused bit
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CHAPTER 15 UART1
15.4 Interrupt of UART1
MB90495G Series
● Receive interrupt
When a receive interrupt is enabled (SSR1 register bit9:RIE = 1), a receive interrupt request is issued at
completion of data receiving (SSR1 register bit12:RDRF = 1) or when any one of the overrun error (SSR1
register bit14:ORE = 1), framing error (SSR 1 register bit13:FRE = 1), and parity error (SSR 1 register
bit15:PE = 1) occurs.
The receive data load flag (SSR1 register bit12:RDRF) is cleared to 0 automatically when the serial input
data register 1 (SIDR1) is read. Each receive error flag (SSR1 register bit15, 14, 13:PE, ORE, FRE) is
cleared to 0 when 0 is written to the receive error flag clear bit (SCR1 register bit10:REC).
Note:
If a receive error (parity error, overrun error, framing error) occurs, correct the error as necessary, and
then write 0 to the receive error flag clear bit (SCR0:REC) to clear each receive error flag.
● Transmit interrupt
When send data is transmitted from the serial output data register 1 (SODR1) to the transmit shift register,
the transmit data write flag bit (SSR1 register bit11:TDRE) is set to 1.
When a transmit interrupt is enabled (SSR1 register bit8:TIE = 1), a send interrupt request is issued.
■ Interrupt Related to UART1 and EI2OS
See Section "3.5 Interrupt", interrupt control register, and interrupt vector addresses.
■ EI2OS Function of UART1
The UART1 supports EI2OS. Consequently, EI2OS can be started separately for receive interrupts and
transmit interrupts.
● At reception:
The EI2OS can be used regardless of the state of other resources.
● At transmission:
Since the interrupt control registers (ICR13, 14) are shared with receive interrupts of UART1, EI2OS can
be started only when UART1 transmit interrupts are not used.
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CM44-10114-7E
CHAPTER 15 UART1
15.4 Interrupt of UART1
MB90495G Series
15.4.1
Generation of Receive Interrupt and Timing of Flag Set
Interrupts at receiving include the receive completion (SSR1 register bit12:RDRF), and
the receive error (SSR1 register bit15, 14, 13:PE, ORE, FRE).
■ Generation of Receive Interrupt and Timing of Flag Set
● Receive data load flag and each receive error flag sets
When data is received, it is stored in the serial input data register (SIDR) when the stop bit is detected (in
operation modes 0 and 1: Asynchronous normal mode, Asynchronous multiprocessor mode) or when the
last bit of receive data (SIDR1 register bit7:D7) is detected (in operation mode 2: Clock synchronous
normal mode). When a receive error occurs, the error flags (SSR1 register bit15, 14, 13:PE, ORE, FRE)
and receive data load flag (SSR1 register bit12:RDRF) are set. In each operation mode, the received data in
the serial input data register 0 (SIDR1) is invalid if either error flag is set.
Operation mode 0 (Asynchronous normal mode)
The receive data load flag bit (SSR1 register bit12:RDRF) is set when the stop bit is detected. The error
flags (SSR1 register bit15, 14, 13:PE, ORE, FRE) are set when a receive error occurs.
Operation mode 1 (Asynchronous multiprocessor mode)
The receive data load flag bit (SSR1 register bit12:RDRF) is set to 1 when the stop bit is detected. The
error flags (SSR1 register bit14, 13:ORE, FRE) are set when a receive error occurs. A parity error (SSR1
register bit15:PE) cannot be detected.
Operation mode 2 (Clock synchronous mode)
The receive data load flag bit (SSR1 register bit12:RDRF) is set to 1 when the last bit of receive data
(SIDR1 register bit7:D7) is detected. The error flags (SSR1 register bit14:ORE) are set when a receive
error occurs. A parity error (SSR1 register bit15:PE) and framing error (SSR1 register bit13:FRE) cannot
be detected.
Reception and timing of flag set are shown in Figure 15.4-1.
Figure 15.4-1 Reception and Timing of Flag Set
Receive data
(operation mode 0)
ST
D0
D1
D5
D6
D7
SP
Receive data
(operation mode 1)
ST
D0
D1
D6
D7
A/D
SP
D0
D1
D4
D5
D6
D7
Receive data
(operation mode 2)
SSR1: PE, ORE, FRE*
SSR1: RDRF
*
: The PE flag cannot be detected in mode 1.
The PE and FRE flags cannot be detected in mode 2.
ST : Start bit
SP : Stop bit
A/D : Address/data select bit of operation mode 2
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
Receive interrupt occurs
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CHAPTER 15 UART1
15.4 Interrupt of UART1
MB90495G Series
● Timing of receive interrupt request generation
With a receive interrupt enabled (SSR1 register bit9:RIE = 1), when a receive interrupt request is issued
when any one of the receive data load flag (SSR1 register bit12:RDRF), parity error flag (SSR1 register
bit15:PE), and overrun error flag (SSR1 register bit14:ORE) and framing error flag (SSR1 register
bit13:FRE) is set, reception interrupt is requested to interrupt controller.
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CM44-10114-7E
CHAPTER 15 UART1
15.4 Interrupt of UART1
MB90495G Series
15.4.2
Generation of Transmit Interrupt and Timing of Flag Set
At transmission, the interrupt is generated in the state which the succeeding data can
be written to the serial output data register 1 (SODR1).
■ Generation of Transmit Interrupt and Timing of Flag Set
● Set and clear of transmit data empty flag bit
The send data write flag bit (SSR1 register bit11:TDRE) is set when the send data written to the serial
output data register 1 (SODR1) is loaded to the send shift register and the next data is ready for writing.
The send data write flag bit (SSR1 register bit11:TDRE) is cleared to 0 when the next send data is written
to the serial output data register 1 (SODR1).
Transmission and timing of flag set are shown in Figure 15.4-2.
Figure 15.4-2 Transmission and Timing of Flag Set
Transmit interrupt requested
[Operation modes 0 and 1]
Transmit interrupt occured
Writing to SODR1
SSR1: TDRE
Output to SOT1
SP SP ST D0 D1 D2 D3
ST D0 D1 D2 D3 D4 D5 D6 D7 A/D
Transmit interrupt occured
Transmit interrupt occured
[Operation mode 2]
Writing to SODR1
SSR1: TDRE
Output to SOT1
ST
D0 to D7
SP
A/D
:
:
:
:
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Start bit
Data bits
Stop bit
Address/data select bit
● Timing of transmit interrupt request
When a transmit interrupt is enabled (SSR1 register bit8:TIE = 1), a send interrupt request is issued to
interrupt controller when the transmit data load flag bit (SSR1 register bit11:TDRE) is set.
Note:
CM44-10114-7E
When sending is disabled during sending (SCR1 register bit8:TXE=0: and also in operation mode 1
(asynchronous multiprocessor mode), receiving disabled (also including bit9:RXE)), the send data write
flag bit is set (SSR1 register bit11:TDRF=1) and UART 1 communications are disabled after the shift
operation of the send shift register stops. The send data written to the serial output data register 1 before
the transmission stops (SODR1) is sent.
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CHAPTER 15 UART1
15.5 Baud Rate of UART1
15.5
MB90495G Series
Baud Rate of UART1
One of the following can be selected as the UART1 transmit/receive clock.
• Dedicated baud rate generator
• Internal clock (16-bit reload timer 0 output)
• External clock (clock input to SCK1 pin)
■ Select of UART1 Baud Rate
The UART1 baud rate select circuit comprises as shown in Figure 15.5-1. The clock input source can be
selected from among the following three types:
● Baud rate by dedicated baud rate generator
• When using the dedicated baud rate generator incorporated into UART1 as a clock input source, set the
CS2 to CS0 bits in the serial mode register (SMR1) to "000B" to "101B" according to the baud rate. The
baud rate can be selected from six types.
● Baud rate by internal timer
• When using the internal clock supplied from the 16-bit reload timer as a clock input source, set the CS2
to CS0 bits in SMR1 bit 5 to 3 to "110B".
• The baud rate is the value at which the frequency of the clock supplied from the 16-bit reload timer as it
is in the clock synchronous mode, and the value at which the frequency of the supplied clock is divided
by 16 in the clock asynchronous mode.
• Any baud rate can be selected according to the setting values of the 16-bit reload timer.
● Baud rate by external clock
• When using the external clock supplied from the clock input pin (SCK1) in the UART1 as the clock
input source, set the CS2 to CS0 bits in SMR1 bit 5 to 3 to "111B".
• The baud rate is the value at which the external clock is supplied in the clock synchronous mode and the
value at which the frequency of the input clock is divided by 16 in the clock asynchronous mode.
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CM44-10114-7E
CHAPTER 15 UART1
15.5 Baud Rate of UART1
MB90495G Series
Figure 15.5-1 UART1 Baud Rate Selector
SMR1: CS2 to CS0
(Clock input source select bits)
Clock selector
CS2 to CS0 = "000B" to "100B"
[Dedicated baud rate generator]
φ/3, φ/4,
φ/5, φ/6,
φ/8
φ
Communication prescaler
(CDCR1: MD0, DIV3 to DIV0)
[Internal timer]
TMCSR1: CSL1, CSL0
Clock selector
φ
Decrement UF
counter
Oscillation dividing circuit
[Clock synchronous]
Any one of the 1/2, 1/4, 1/8,
1/16, 1/32 division ratio is
selected
[Asynchronous]
The internal fixed
division ratio is selected
CS2 to CS0 = "110B"
1/2 [Clock synchronous]
1/32 [Asynchronous]
Baud rate
φ/21 φ/23 φ/25
Prescaler
16-bit reload timer 1
CS2 to CS0 = "111B"
[External clock]
SCK1
Pin
φ : Machine clock
UF : Underflow
CM44-10114-7E
1/1 [Clock synchronous]
1/16 [Asynchronous]
SMR1: MD1, MD0
(operation mode select bits)
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CHAPTER 15 UART1
15.5 Baud Rate of UART1
MB90495G Series
Baud Rate by Dedicated Baud Rate Generator
15.5.1
The baud rate that can be set when the output clock of the dedicated baud rate
generator is selected as the transfer clock of the UART1 is shown.
■ Baud Rate by Dedicated Baud Rate Generator
The baud rate based on the dedicated baud rate generator is set by setting the clock input source select bits
in the serial mode register (SMR1 register bit5 to 3:CS2 to CS0) to "000B" to "101B".
When generating a transmit/receive clock using the dedicated baud rate generator, the division ratio for the
clock input source selected by the clock selector is selected to determine the baud rate after the machine
clock frequency is divided by the communication prescaler.
The division ratio at which the machine clock frequency is divided by the communication prescaler is the
same for the clock synchronous and asynchronous modes. The division ratio at which the baud rate is
determined is different for the clock synchronous and asynchronous modes.
Figure 15.5-2 shows the baud rate selector based on the dedicated baud rate generator.
Figure 15.5-2 Baud Rate Selector Based on Dedicated Baud Rate Generator
SMR1: CS2 to CS0
(clock input source select bits)
Clock selector
φ
φ/1, φ/2, φ/3, φ/4,
φ/5, φ/6, φ/7, φ/8
Communication prescaler
(CDCR1: MD0, DIV3 to DIV0)
Oscillation dividing circuit
[Clock synchronous]
Any one of the 1/2, 1/4, 1/8,
1/16, 1/32 division ratio is
selected
[Asynchronous]
The internal fixed
division ratio is selected
Baud rate
SMR1: MD1, MD0
(operation mode select bits)
φ: Machine clock frequency
● Calculation expression for baud rate
Baud rate in asynchronous mode = φ x div x (division ratio of transfer clock in asynchronous mode)
Baud rate in clock synchronous mode = φ x div x (division ratio of transfer clock in clock synchronous
mode)
φ: Machine clock frequency
div: Division ratio based on communication prescaler
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CM44-10114-7E
CHAPTER 15 UART1
15.5 Baud Rate of UART1
MB90495G Series
● Division ratio based on communication prescaler (common between asynchronous and clock
synchronous modes)
The division ratio of the machine clock is set by the division ratio select bits in the communication
prescaler control register (CDCR1 register bit 10 to 8:DIV2 to DIV0).
Table 15.5-1 Division Ratio Based on Communication Prescaler
MD
DIV3
DIV2
DIV1
DIV0
div
0
−
−
−
−
Stop
1
0
0
0
0
1
1
0
0
0
1
2
1
0
0
1
0
3
1
0
0
1
1
4
1
0
1
0
0
5
1
0
1
0
1
6
1
0
1
1
0
7
1
0
1
1
1
8
div: Division ratio based on communication prescaler
● Baud rate (asynchronous mode)
The baud rate in the asynchronous mode is generated using output clock of the communication prescaler.
The division ratio is set by the clock input source select bits (SMR1 register bit 5 to 3:CS2 to CS0).
Table 15.5-2 Baud Rate (Asynchronous Mode)
CS2
CS1
CS0
Asynchronous Mode
(Start/Stop Synchronous)
Calculation
0
0
0
76,923 bps
(φ/div) / (8 x 13 x 2)
0
0
1
38,461 bps
(φ/div) / (8 x 13 x 4)
0
1
0
19,230 bps
(φ/div) / (8 x 13 x 8)
0
1
1
9,615 bps
(φ/div) / (8 x 13 x 16)
1
0
0
500 Kbps
(φ/div) / (8 x 2 x 2)
1
0
1
250 Kbps
(φ/div) / (8 x 2 x 4)
The baud rate is calculated based on the values of φ = 16 MHz and div = 1.
φ: Machine clock frequency
div: Division ratio based on communication prescaler
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CHAPTER 15 UART1
15.5 Baud Rate of UART1
MB90495G Series
● Baud rate (clock mode)
The baud rate in the synchronous mode is generated by dividing the output clock of the communication
prescaler by 1, 2, 4, 8, 16 and 32. Set the division ratio using the clock input source select bits (bits 5 to 3 in
SMR1 register: CS2 to CS0).
Table 15.5-3 Baud Rate (Clock Synchronous)
CS2
CS1
CS0
CLK Synchronous
Calculation
0
0
0
2 Mbps
(φ/div) / 1
0
0
1
1 Mbps
(φ/div) / 2
0
1
0
500 Kbps
(φ/div) / 4
0
1
1
250 Kbps
(φ/div) / 8
1
0
0
125 Kbps
(φ/div) / 16
1
0
1
62.5 Kbps
(φ/div) / 32
The baud rate is calculated based on the values of φ = 16 MHz and div = 8.
φ: Machine clock frequency
div: Division ratio based on communication prescaler
488
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CHAPTER 15 UART1
15.5 Baud Rate of UART1
MB90495G Series
15.5.2
Baud Rate by Internal Timer (16-bit Reload Timer)
The setting when selecting the internal clock supplied from the 16-bit reload timer 1 as
the clock input source of the UART1 and the baud rate calculation are shown below.
■ Baud Rate by Internal Timer (16-bit Reload Timer Output)
The baud rate based on the internal timer (16-bit reload timer output) is set by setting the clock input source
select bits (SMR1 register bit5 to 3:CS2 to CS0) to "110B". Any baud rate can be set by selecting the
division ratio of the count clock and the reload value of the 16-bit reload timer.
Figure 15.5-3 shows the baud rate selector based on the internal timer.
• If the internal timer (16-bit reload timer) is selected as a clock input source (SMR1 register bit5 to
3:CS2 to CS0), the 16-bit reload timer output pin (TOT) is connected internally and does not need to be
connected externally to the external clock input pin (SCK).
• The 16-bit reload timer output pin (TOT) can be used as a general-purpose I/O port when it is not being
used in other way.
Figure 15.5-3 Baud Rate Selector by Internal Timer (16-bit Reload Timer Output)
SMR1: CS2 to CS0 = "110B"
(Clock input source select bits)
Clock selector
16-bit reload timer output
(The frequency is specified by
the count-clock division ratio
and the reload value)
1/1 [Clock synchronous]
1/16 [Asynchronous]
Baud rate
SMR1: MD1, MD0
(Operation mode select bits)
● Baud Rate
φ/N
Asynchronous baud rate =
Clock synchronouse =
bps
16 × 2 × (n+1)
φ/N
bps
2 × (n+1)
φ: machine clock frequency
N: division ratio based on communication prescaler for 16-bit reload timer (21, 23, 25)
n: reload value for 16-bit reload timer (0 to 65,535)
● Example of setting baud rates and reload register setting values (machine clock frequency: 7.3728
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CHAPTER 15 UART1
15.5 Baud Rate of UART1
MB90495G Series
MHz)
Table 15.5-4 Baud Rate and Reload Value
Reload Value
Baud Rate
(bps)
Clock Asynchronous
(start-stop synchronization)
Clock Synchronous
N = 21(machine
cycle 2-divided)
N = 21(machine
cycle 8-divided)
N = 21(machine
cycle 2-divided)
N = 21(machine
cycle 8-divided)
38,400
2
−
47
11
19,200
5
−
95
23
9,600
11
2
191
47
4,800
23
5
383
95
2,400
47
11
767
191
1,200
95
23
1,535
383
600
191
47
3,071
767
300
383
95
6,143
1,535
N: Division ratio based on communication prescaler for 16-bit reload timer
−: Setting disabled
490
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CHAPTER 15 UART1
15.5 Baud Rate of UART1
MB90495G Series
15.5.3
Baud Rate by External Clock
This section explains the setting when selecting the external clock as the transmit/
receive clock of the UART1.
■ Baud Rate by External Clock
To select a baud rate by the external clock input, the following settings are essential:
• Set the CS2 to CS0 bits in the serial mode register (SMR1 register bit5 to 3:CS2 to CS0) to "111B".
• Set the SCK1 pin as the input port in the port direction register (DDR).
• Set the serial dock I/O enable bit (SMR1 register bit1:SCKE) to 0.
• Set the baud rate on the basis of the external clock input from the SCK1 pin. Since the internal division
ratio is fixed, the cycle of the external input clock must be changed in changing the baud rate.
Figure 15.5-4 Baud Rate Selector by External Clock
SMR1: CS2 to CS0 = "111B"
(Clock input source select bits)
Clock selector
SCK1
1/1 [Clock synchronous]
1/16 [Asynchronous]
Pin
Baud rate
SMR1: MD1, MD0
(Operation mode select bits)
● Expressions to obtain baud rate
Asynchronous baud rate = f/16 bps
Clock synchronous baud rate = f bps
f: External clock frequency (2 MHz max.)
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CHAPTER 15 UART1
15.6 Explanation of Operation of UART1
15.6
MB90495G Series
Explanation of Operation of UART1
The UART1 has master/slave type connection communication function (operation mode
1: asynchronous multiprocessor mode) in addition to bidirectional serial
communication function (operation modes 0 and 2: asynchronous normal mode and
clock synchronous mode).
■ Operation of UART1
● Operation mode
The UART1 has three types of operation modes, they can set the inter-CPU connection mode or data
communication mode.
Table 15.6-1 shows operation mode of UART1.
Table 15.6-1 Operation Mode of UART
Data Length
Operation Mode
No Parity
With Parity
0
Normal mode
7 bits or 8 bits
1
Multiprocessor
mode
*1
2
Clock
synchronous
mode
8+1
8
Synchronous/
Asynchronous
Length of Stop Bit
Asynchronous
−
Asynchronous
−
Synchronous
1 bit or 2 bits *2
None
−: Setting disabled
*1: +1 is the address/data select bit (SCR1 register bit11:A/D) used for controlling communications.
*2: During reception, only one bit can be detected as the stop bit.
Note:
492
The UART1 operation mode 1 (asynchronous multiprocessor mode) is only used as the master in the
master/slave type connection.
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CHAPTER 15 UART1
15.6 Explanation of Operation of UART1
MB90495G Series
● Inter-CPU connection mode
Either 1-to-1 connection or master/slave type connection can be selected for the inter-CPU controller. In
both cases, the data length, parity, synchronous or asynchronous mode, etc., must be the same for all CPUs.
The operation modes are selected as follows.
• For the 1-to-1 connection, the same operation mode (either operation mode 0 or 2: normal mode, clock
synchronous mode) must be adopted for the two CPUs. For the asynchronous mode, select operation
mode 1: asynchronous multiprocessor mode (SMR1 register bit 7, 6: MD1, MD0 = "00B"): for the
synchronous mode select operation mode 2: clock synchronous mode (SMR1 register bit7, 6:MD1,
MD0 = "10B").
• For the master/slave type connection, operation mode 1: asynchronous multiprocessor mode (SMR1
register bit7, 6:MD1, MD0 = "0B") is set; select operation mode 1 (asynchronous multiprocessor mode)
and use it as the master. For this connection, select no parity 8-bit data length.
● Synchronous/asynchronous
For the operation modes, either the asynchronous mode (start-stop synchronization) or the clocksynchronous mode can be selected.
● Signal mode
The UART1 can only handle the NRZ (Non Return to Zero) data format.
● Start of transmission/reception
• Transmission starts when the transmission enable bit of the serial control register (SCR1 register
bit8:TXE) is set to 1.
• Reception starts when the reception enable bit of the serial control register (SCR1 register bit9:RXE) is
set to 1.
● Stop of transmission/reception
• Transmission stops when the transmission enable bit of the serial control register (SCR1 register
bit8:TXE) is set to 0.
• Reception stops when the reception enable bit of the serial control register (SCR1 register bit9:RXE) is
set to 0.
● Stop during transmission/reception
• When reception is disabled during receiving (during data input to reception shift register) (SCR1
register bit9:RXE = 0), it stops after reception of the frame being received is completed and the receive
data is stored to the serial input data register 1 (SIDR1).
• When transmission is disabled during transmission (during data output from the transmission shift
register) (SCR1 register bit8:TXE = 0), it stops after transmission of one frame to the transmission shift
register from the serial output data register 1 (SODR1) is completed.
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CHAPTER 15 UART1
15.6 Explanation of Operation of UART1
15.6.1
MB90495G Series
Operation in Asynchronous Mode
(Operation Mode 0 or 1)
When the UART is used in operation mode 0 (asynchronous normal mode) or operation
mode 1 (asynchronous multiprocessor mode), the asynchronous transfer mode is
selected.
■ Operation in Asynchronous Mode
● Format of transmit/receive data
Transmission and reception always start with the start bit (Low level); transmission and reception are
performed at the specified data bit length on LSB first basis and end with the stop bit (High level).
• In operation mode 0 (Asynchronous normal mode), the data length can be set to 7 or 8 bits. Use of the
parity bit can be specified.
• In operation mode 1 (Asynchronous multiprocessor mode), the data length is fixed to 8 bits. There is no
parity bit. The address/data bit (SCR1 register bit11:A/D) is added to bit 9.
Figure 15.6-1 shows the transmit/receive data format in the asynchronous mode.
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CHAPTER 15 UART1
15.6 Explanation of Operation of UART1
MB90495G Series
Figure 15.6-1 Format of Transmit/Receive Data (Operation Mode 0 or 1)
[Operation mode 0]
ST
D0
D1
D2
D3
D4
D5
D7
D8
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
D8
SP
ST
D0
D1
D2
D3
D4
D5
D7
D8
P
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
D8
P
SP
ST
D0
D1
D2
D3
D4
D5
D7
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
SP
ST
D0
D1
D2
D3
D4
D5
D7
P
P not
provided
Data 8 bits
P
provided
P not
provided
Data 7 bits
ST
D0
SP SP
D1
D2
D3
D4
D5
D7
P
SP
P
provided
[Operation mode 1]
ST
D0
D1
D2
D3
D4
D5
D7
D8
A/D
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
D8
A/D
SP
Data 8 bits
ST
SP
P
A/D
:
:
:
:
Start bit
Stop bit
Parity bit
Address/data bit
● Transmission
• Transmit data is written to the serial output data register 1 (SODR1) with the transmit data write flag bit
(SSR1 register bit11:TDRE) set to 1.
• Transmission starts when transmit data is written and the transmit enable bit of the serial control register
(SCR1 register bit8:TXE) is set to 1.
• The transmit data write flag bit (SSR1 register bit11:TDRE) is cleared to 0 temporarily when transmit
data is written to SODR1.
• The transmit data write flag bit (SSR1 register bit11:TDRE) is set to 1 again once the transmit data is
written to the send shift register from the serial output data register 0 (SODR1).
• When the transmit interrupt enable bit (SSR1 register bit8:TIE) is set to 1, a send interrupt request is
issued once the send data write flag bit (SSR1 register bit11:TDRE) is set to 1. The succeeding send
data can be written to the serial output data register 1 (SODR1) at interrupt processing.
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CHAPTER 15 UART1
15.6 Explanation of Operation of UART1
MB90495G Series
● Reception
• When reception is enabled (SCR1 register bit9:RXE = 1), receiving is always performed.
• When the start bit of receive data is detected, the serial input data register 1 (SIDR1) receives one frame
of data and stores data to the serial input data register 1 (SIDR1) according to the data format specified
in the serial control register 1 (SCR1).
• At completion of receiving one frame of data, the receive data load flag bit (SSR1 register bit12:RDRF)
is set to 1.
• When the status of the error flag of the serial status register 1 (SSR1) is checked to find normal
reception at the completion of one frame of data, read the receive data. When a receive error occurs,
perform error processing.
• The receive data load flag bit (SSR1 register bit12:RDRF) is cleared to 0 when receive data is read.
● Start bit detection method
Specify settings as follows for start bit detection:
• Immediately before the start of the communication period, be sure to set the communication line to H
(mark level added).
• Set receive ready (RXE=H) while the communication line is at H (mark level).
• Do not set receive ready (RXE=H) during the non-communication period (mark level removed).
Otherwise, data is not received correctly.
• After the stop bit is detected (the RDRF flag is set to 1), set receive not ready (RXE=L) while the
communication line is at H (mark level).
Figure 15.6-2 Normal Operation
Communication period
Non-communication period
Mark level
Start bit
SIN
Non-communication period
Stop bit
Data
ST
D0
D1
D0
D1
D3
D2
D5
D4
D7
D6
SP
(Sending 01010101b)
RXE
Receive clock
Sampling clock
Receive clock (8 pulse)
Recognition by the microcontroller
Generating sampling clocks by dividing the receive clock by 16
ST
D3
D2
D5
D4
D7
D6
SP
(Receiving 01010101b)
Note that if receive ready is set at the timing represented in the following example, input data (SIN) is not
recognized correctly by the microcontroller:
• Example of operation where receive ready (RXE=H) is set while the communication line is at L
Figure 15.6-3 Abnormal Operation
Communication period
Non-communication period
Mark level
Start bit
SIN
(Sending 01010101b)
RXE
Non-communication period
Stop bit
Data
ST
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
SP
SP
Receive clock
Sampling clock
Recognition by the microcontroller
ST recognition
(Receiving 10101010b)
PE,ORE,FRE
Occurrence of a reception error
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CHAPTER 15 UART1
15.6 Explanation of Operation of UART1
MB90495G Series
● Stop bit
During transmission, one bit or two bits can be selected. However, the receive side always detects only the
first bit.
● Error detection
• In operation mode 0 (asynchronous normal mode), parity, overrun, and frame errors can be detected.
• In operation mode 1 (asynchronous multiprocessor mode), overrun and frame errors can be detected, but
parity errors cannot be detected.
● Parity bit
A parity bit can be set only in operation mode 0 (asynchronous normal mode). The parity addition enable
bit (SCR1 register bit 15:PEN) is used to specify whether there is parity or not, and the parity select bit
(SCR1 register bit 14:P) is used to select odd or even parity.
There is no parity bit in operation modes 1 (asynchronous multiprocessor mode).
The transmit/receive data when the parity bit enabled are shown in Figure 15.6-4.
Figure 15.6-4 Transmit/Receive Data when Parity Bit Enabled
When receiving
SIN1
ST
SP
1
When transmitting
SOT1
1
1
0
0
1
1
0
1
1
0
0
1
0
0
1
1
0
0
1
Data
ST : Start bit
SP : Stop bit
Note : Parity bit cannot be set in operation mode 1.
0
SP
Transmission with even parity
(SCR1: PEN = 1, P = 0)
SP
Transmission with odd parity
(SCR1: PEN = 1, P = 1)
0
ST
1
CM44-10114-7E
0
ST
1
When transmitting
SOT1
0
Parity error at reception
with even parity
(SCR1: PEN = 1, P = 0)
1
Parity
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CHAPTER 15 UART1
15.6 Explanation of Operation of UART1
15.6.2
MB90495G Series
Operation in Clock Synchronous Mode
(Operation Mode 2)
When the UART1 is used in operation mode 2, the transfer mode is clock synchronous.
■ Operation in Clock Synchronous Mode (Operation Mode 2)
● Format of transmit/receive data
In the synchronous mode, 8-bit data is transmitted/received on LSB-first, and the start and stop bits are not.
Figure 15.6-5 shows the data format for the clock synchronous mode.
Figure 15.6-5 Format of Transmit/Receive Data (Operation Mode 2)
Outputting serial clock for transmitting
Mark level
SCK1 output
SOT1
(LSB)
1
0
1
1
0
0
1
0
(MSB)
Transmit data
Write transmit data
TXE
Inputting serial clock for receiving
Mark level
SCK1 input
SIN1
(LSB)
1
0
1
1
0
0
1
0
(MSB)
Receive data
RXE
Read receive data
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CHAPTER 15 UART1
15.6 Explanation of Operation of UART1
MB90495G Series
● Clock supply
In the clock synchronous mode, count of clocks equal to the transmit and receive bits count must be
supplied.
• When the internal clock (dedicated baud rate generator or internal timer) has already selected (SMR1
register bit 5 to 3:CS2 to CS0 = "000B" to "101B" or "110B") and data is transmitted, the synchronous
clock for data reception is generated automatically.
• When the external clock has already selected (SMR1 register bit 5 to 3:CS2 to CS0 = "11B"), the clock
for exact one byte must be supplied from outside after ensuring that data is present (SSR1 register bit
11:TDRE = 0) in the serial output data register (SODR1). Also, before and after transmitting, always
return to the mark level (High level).
● Error detection
Only overrun errors can be detected; parity and framing errors cannot be detected.
● Setting of register
Table 15.6-2 shows the setting of the control register in transmitting serial data from the transmitting end to
the receiving end using the clock synchronous mode (operation mode 2).
Table 15.6-2 Setting of Control Register
Setting
Register Name
Serial mode
register 1 (SMR1)
Serial control
register 1 (SCR1)
Bit Name
MD1, MD0
CM44-10114-7E
Receive End
(input serial clock)
Set clock synchronous mode (MD1, MD0 = "10B").
CS2, CS1, CS0
Set clock input source.
• Dedicated baud rate generator (CS2
to CS0 = "000B" to "100B")
• Internal timer (CS2 to CS0 =
"110B")
Set clock input source.
• External clock
(CS2 to CS0 = "111B")
SCKE
Set serial clock output
(SCKE = 1).
Set serial clock input
(SCKE = 0).
SOE
Set serial data output pin
(SOE = 1).
Set general-purpose I/O port (SOE = 0).
PEN
Do not add parity bit (PEN = 0).
CL
REC
Serial status
register 1 (SSR1)
Transmit End
(output serial clock)
8-bit data length (CL = 1)
Initialize error flag (REC = 0).
TXE
Enable transmitting (TXE = 1).
Disable transmitting (TXE = 0).
RXE
Disable receiving (RXE = 0).
Enable receiving (RXE = 1).
TIE
Enable transmitting (TIE = 1)
Disable transmitting (TIE = 0)
RIE
Disable receiving (RIE = 0).
Enable receiving (RIE = 1).
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CHAPTER 15 UART1
15.6 Explanation of Operation of UART1
MB90495G Series
● Starting communications
When send data is written to the serial output data register 1 (SODR1), communication is starts. When
starting communication only in receiving, it is always necessary to write dummy send data to the serial
output data register 1 (SODR1).
● Terminating communications
After transmitting and receiving of one frame of data, the receive data load flag bit (SSR1 register bit
12:RDRF) is set to 1. When data is received, check the overrun error flag bit (SSR1 register bit 14:ORE) to
ensure that the communication has performed normally.
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CHAPTER 15 UART1
15.6 Explanation of Operation of UART1
MB90495G Series
15.6.3
Bidirectional Communication Function (Operation
Modes 0 and 2)
In operation modes 0 and 2 (asynchronous normal mode, clock synchronous mode),
normal serial bidirectional communications using 1-to-1 connection can be performed.
For operation mode 0 (asynchronous normal mode), the asynchronous mode is used;
for operation mode 2 (clock synchronous mode), the clock synchronous mode is used.
■ Bidirectional Communication Function
To operate the UART1 in the operation mode 0, 2 (asynchronous normal mode, clock synchronous mode),
shown in Figure 15.6-6 is required.
Figure 15.6-6 Setting of Operation Modes 0, 2 (Asynchronous Normal Mode and Clock Synchronous
Mode) for UART1
bit 15 14
13
12
11
10
9 bit 8 bit 7 6
5
4
3
PEN P SBL CL AD REC RXE TXE MD1 MD0 CS2 CS1 CS0
SCR1, SMR1
Operation mode 0
Operation mode 2
0
SSR1,
SIDR1/SODR1
Operation mode 0
Operation mode 2
×
×
1
×
×
0
0
PE ORE FRE RDRFTDRE ⎯ RIE TIE
×
0
1
0
0
2
Reserved
1 bit 0
SCKE SOE
0
0
Setting of transmit data (at write)
/ Retention of receive data (at read)
×
DDR port-direction register
⎯ :
:
× :
1 :
0 :
Unused bit
Used bit
Undefined bit
Set 1
Set 0
Set the bit to 0 corresponding to pin
used as SIN1 and SCK1 input pins.
● Inter-CPU connect
Connect the two CPUs as shown in Figure 15.6-7.
Figure 15.6-7 Example of Bidirectional Communication Connect for UART1
SOT1
SOT1
SIN1
SCK1
SIN1
Output
Input
SCK1
CPU-1
CM44-10114-7E
CPU-2
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CHAPTER 15 UART1
15.6 Explanation of Operation of UART1
MB90495G Series
● Communication procedure
Communications start at any timing from the transmitting end when transmit data is provided. At the
transmitting end, set transmit data in the serial output data register (SODR1) and set the transmitting enable
bit in the serial control register (SCR1 register bit 8:TXE) to 1 to start transmitting.
Figure 15.6-8 gives an example of transferring receive data to the transmitting end to inform the
transmitting end of normal reception.
Figure 15.6-8 Flowchart for Bidirectional Communication
(Transmit end)
(Receive end)
Start
Start
Set the operation mode
(0 or 2)
Set the operation mode
(same as transmit end)
Set the 1-byte data in
SODR1
Data transmission
NO
Receive data
presence
YES
NO
Receive data
presence
Read and process
receive data
YES
Read and process
receive data
502
Data transmission
Transmit 1-byte data
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CM44-10114-7E
CHAPTER 15 UART1
15.6 Explanation of Operation of UART1
MB90495G Series
15.6.4
Master/Slave Type Communication Function
(Multiprocessor Mode)
Operation mode 1 (asynchronous multiprocessor mode) enables communications by
the master/slave connection of more than one CPU. Only the master CPU functions.
■ Master/Slave Mode Communication Function
To operate the UART1 in operation mode 1 (asynchronous multiprocessor mode), the setting shown in
Figure 15.6-9 is required.
Figure 15.6-9 Setting of Operation Mode 1 (Asynchronous Multiprocessor Mode) for UART1
bit 15 14
13
12
11
10
9 bit 8 bit 7 6
5
4
3
PEN P SBL CL AD REC RXE TXE MD1 MD0 CS2 CS1 CS0
SCR1, SMR1
0
SSR1,
SIDR1/SODR1
×
1
0
PE ORE FRE RDRFTDRE ⎯ RIE TIE
×
0
1
2
Reserved
0
1 bit 0
SCKE SOE
0
Setting of transmit data (at write)
/ Retention of receive data (at read)
DDR port-direction register
⎯ :
:
× :
1 :
0 :
Unused bit
Used bit
Undefined bit
Set 1
Set 0
Set the bit to 0 corresponding to pin
used as SIN1 and SCK1 input pins.
● Inter-CPU connect
One master CPU and more than one slave CPU are connected to two common communication lines to
compose the communication system. The UART1 can be used only as the master CPU.
Figure 15.6-10 Example of Master/Slave Mode Communication Connect for UART1
SOT1
SIN1
Master CPU
SOT
SIN
Slave CPU #0
CM44-10114-7E
SOT
SIN
Slave CPU #1
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CHAPTER 15 UART1
15.6 Explanation of Operation of UART1
MB90495G Series
● Function select
At master/slave type communication, select the operation mode and data transfer type.
Since the parity check function cannot be used in operation mode 1 (asynchronous multiprocessor mode),
set the parity add enable bit (SCR1 register bit 15:PEN) to 0.
Table 15.6-3 Select of Master/Slave Communication Function
Operation Mode
Master
CPU
Address
transmit/receive
Data transmit/
receive
Operation
mode 1
Slave
CPU
Data
A/D = 1 +
8-bit address
−
A/D = 0 +
8-bit data
Parity
Synchronous
System
Stop Bit
Not
provided
Asynchronous
1 bit or 2 bits
● Communication procedure
Communications start when the master CPU transmits address data.
The address data is data with the A/D bit set to 1. The address/data select bit (SCR1 register bit 11:A/D) is
added to select the slave CPU that the master CPU communicates with. When the program identifies
address data and finds a match with the allocated address, each slave CPU starts communications with the
master CPU.
Figure 15.6-11 shows the flowchart for master/slave communications.
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CHAPTER 15 UART1
15.6 Explanation of Operation of UART1
MB90495G Series
Figure 15.6-11 Flowchart for Master/Slave Communications
(Master CPU)
Start
Select the operation
mode 1 (asynchronous
multiprocessor mode)
Set 1-byte data (address
data) that selects the
slave CPU to D0 to D7
to transmit (A/D = 1)
Set 0 to A/D
Reception enabled
Communicate
with slave CPU
Communication
ended?
NO
YES
Communicate
with other slave
CPU
NO
YES
Reception disabled
End
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CHAPTER 15 UART1
15.7 Precautions when Using UART1
15.7
MB90495G Series
Precautions when Using UART1
Use of the UART1 requires the following cautions.
■ Precautions when Using UART1
● Enabling sending and receiving
The send enable bit (SCR1 register bit 8:TXE) and receive enable bit (SCR1 register bit 9:RXE) are
provided for sending and receiving.
• In the initial state after reset, both sending and receiving are disabled (SCR1 register bit 8:TXE = 0, bit
9:RXE = 0). Therefore, it is necessary to enable sending and receiving.
• Sending and receiving are disabled to stop (SCR1 register bit 8:TXE = 0, bit 9:RXE = 0).
● Setting operation mode
Set the operation mode after disabling sending and receiving (SCR1 register bit 8:TXE = 0, bit 9:RXE = 0).
When the operation mode is changed during sending and receiving, the sent and received data is not
assured.
● Clock synchronous mode
Operation mode 2 (clock synchronous mode) is set as the clock synchronous mode. Send and receive data
do not have the start and stop bits.
● Timing of enabling send interrupt
The initial value after reset of the send data write flag bit (SSR1 register bit 11:TDRE) is set at 1 (no send
data, send data write enabled). Therefore, the send interrupt is enabled (SSR1 register bit 8:TIE = 1) and a
send interrupt request is issued simultaneously. Always prepare send data and enable a send interrupt
(SSR1 register bit 8:TIE = 1).
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CHAPTER 15 UART1
15.8 Program Example for UART1
MB90495G Series
15.8
Program Example for UART1
This section gives a program example for the UART1.
■ Program Example for UART1
● Processing
The bidirectional communication function (normal mode) of the UART1 is used to perform serial
transmission/reception.
• Set operation mode 0, asynchronous mode (normal), 8-bit data length, 2-bit stop bit length, and no
parity.
• Use the P40/SIN1 and PS/SOT1 pins for communications.
• Use the dedicated baud rate generator to set the baud rate to approximately 9600 bps.
• Transmit the character 13Hfrom the SOT1 pin and receive it at an interrupt.
• Assume the machine clock (φ) 16 MHz.
● Coding example
ICR13
EQU 0000BDH
; UART1 Transmit/receive control register
DDR1
EQU 000011H
; Port 1 data direction register
CDCR1
EQU 00001BH
; Communication prescaler register 1
SMR1
EQU 000024H
; Mode control register 1
SCR1
EQU 000025H
; Control register 1
SIDR1
EQU 000026H
; Input data register 1
SODR1
EQU 000026H
; Output data register 1
SSR1
EQU 000027H
; Status register 1
REC
EQU SCR1:2
; Receive error flag clear bit
;-----Main program--------------------------------------------------------------CODE
CSEG ABS=0FFH
START:
;
:
; Assume stack pointer (SP) already reset
AND CCR,#0BFH
; Disable interrupt
MOV I:ICR13,#00H
; Interrupt level 0 (highest priority)
MOV I:DDR1,#00000000B ; Set SIN1 as input pin.
MOV I:CDCR,#080H
; Enable communication prescaler
MOV I:SMR1,#00010001B ; Operation mode 0 (asynchronous)
; Use dedicated baud rate generator (9615 bps)
; Disable clock pulse output and enable data output
MOV I:SCR1,#00010011B ; Without N parity. 2-bit stop bit
; Clear 8-bit data bit and receive errorflag
; Enable transmitting/receiving
MOV I:SSR1,#00000010B ; Disable transmit interrupt and enable receive
; interrupt
MOV I:SODR1,#13H
; Write send data
MOV ILM,#07H
; Set ILM of PS to level 7
OR
CCR,#40H
; Enable interrupt
LOOP:
MOV A,#00H
; Infinite loop
MOV A,#01H
BRA LOOP
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CHAPTER 15 UART1
15.8 Program Example for UART1
MB90495G Series
;-----Interruption program------------------------------------------------------WARI:
MOV A,SIDR1
; Read receive data
CLRB I:REC
; Clear receive interrupt request flag
;
:
;
Processing by user
;
:
RETI
; Return from interrupt
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG 0FF68H
; Set interrupt #37 (25H) vector
DSL WARI
ORG 0FFDCH
; Set reset vector
DSL START
DB
00H
; Set single-chip mode
VECT
ENDS
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CHAPTER 16
CAN CONTROLLER
This chapter explains the functions and operations of
the CAN controller.
16.1 Overview of CAN Controller
16.2 Block Diagram of CAN Controller
16.3 Configuration of CAN Controller
16.4 Interrupts of CAN Controller
16.5 Explanation of Operation of CAN Controller
16.6 Precautions when Using CAN Controller
16.7 Program Example of CAN Controller
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CHAPTER 16 CAN CONTROLLER
16.1 Overview of CAN Controller
16.1
MB90495G Series
Overview of CAN Controller
The CAN (controller area network) is a serial communication protocol conformed to
CAN Ver. 2.0A and Ver. 2.0B. Transmitting and receiving can be performed in the
standard frame format and the extended frame format.
■ Overview of CAN Controller
• The CAN controller format conforms to CAN Ver. 2.0A and Ver. 2.0B.
• Transmitting and receiving can be performed in the standard frame format and the extended frame
format.
• Data frames can be transmitted automatically by remote frames receiving.
• The baud rate ranges from 10 kpbs to 1 Mbps (A minimum 8 MHz machine clock is required if 1 Mbps
is used).
Table 16.1-1 Data Transfer Baud Rate
Machine Clock
Baud Rate
16 MHz
1 Mbps
12 MHz
1 Mbps
8 MHz
1 Mbps
4 MHz
500 Kbps
2 MHz
250 Kbps
• The CAN controller equips eight transmit/receive message buffers.
• The standard frame format provides transmitting and receiving with 11-bit ID and the extended frame
format 29-bit ID.
• Message data can be set from 0 byte to 8 bytes.
• Message buffer configuration can be performed at a multilevel.
• The CAN controller has two acceptance mask registers. These registers can set masks independently for
the receive message ID.
• The two acceptance mask registers can receive in the format of standard frame and extended frame.
• Four masks can be set at all bit comparison and masking, and partially at acceptance mask registers 0
and 1.
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CHAPTER 16 CAN CONTROLLER
16.2 Block Diagram of CAN Controller
MB90495G Series
16.2
Block Diagram of CAN Controller
The CAN controller consists of two types of registers; one controls the CAN controller
and the other controls each message buffer.
■ Block Diagram of CAN Controller
Figure 16.2-1 Block Diagram of CAN Controller
2
Operation clock (TQ)
F MC-16LX bus
CPU
operation clock
BTR
CSR
PSC
TS1
TS2
RSJ
TOE
TS
RS
HALT
NIE
NT
NS1,0
Prescaler
(1 to 64-devided clock)
Bit timing generator
Bus state
determining
circuit
Node status transition Node status transition
interrupt signal
interrupt generator
Idle, interrupt, suspend,
transmit, receive, error,
overload
Error
controller
RTEC
Transmit/receive
sequencer
BVALR
TREQR
Sync segment
Time segment 1
Time segment 2
Transmit
buffer clear
Transmit buffer
determining circuit
Transmit
buffer
Error frame
generator
Overload
frame
generator
Acceptance
Data
counter filter controller
Transmit Receive ID select
DLC
DLC
Bit error, stuff error,
CRC error, frame error,
ACK error
Transmit buffer
TCANR
Arbitration lost
Output
driver
Pin TX
Input
latch
Pin RX
TRTRR
Transmission
shift register
RFWTR
TIER
Sets and clears transmit buffer
Transmission complete Transmission
complete
interrupt generator
interrupt signal
RCR
Sets receive buffer
TCR
RRTRR
Reception
Reception complete
complete
interrupt generator
interrupt signal
Sets and clears receive buffer and transmit buffer
ROVRR
Sets receive ID select
buffer
RIER
AMSR
AMR0
AMR1
IDR0 to 7
DLCR0 to 7
DTR0 to 7
RAM
0
1
Acceptance
filter
Receive buffer
determining circuit
Receive buffer
RAM address
generator
Stuffing
CRC
genertor
Transmit DLC
ACK
generator
CRC error
Receive DLC CRG generator/error check Stuff error
Reception
shift register
Destuffing/stuffing
error check
Arbitration lost
Arbitration check
Bit error
Bit error check
ACK error
Acknowledgement
check
Form error
Form error
check
Receive buffer, transmit buffer, receive DLC, transmit DLC, ID select
IDER
LEIR
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CHAPTER 16 CAN CONTROLLER
16.2 Block Diagram of CAN Controller
MB90495G Series
The pin names in the block diagram are as follows:
TX pin: P43/TX
RX pin: P44/RX
● Bit timing register (BTR)
This register sets the division ratio at which CAN bit timing is generated.
● Control status register (CSR)
This register controls the operation of the CAN controller. It indicates the state of transmitting/receiving
and the CAN bus, controls interrupts, and controls the bus halt and indicates its state.
● Receive/transmit error counter register (RTEC)
This register indicates the number of times transmit and receive errors have occurred. It counts up when an
error occurs in transmitting and receiving messages and counts down when transmitting and receiving are
performed normally.
● Message buffer validating register (BVALR)
This register enables or disables a specified message buffer, and also indicates the enabled/disabled status.
● IDE register (IDER)
This register sets the frame format of each message buffer. It sets the standard frame format or extended
frame format.
● Transmit request register (TREQR)
This register sets a transmit request to each message buffer.
● Transmit cancel register (TCANR)
This register cancels transmit requests held in each buffer message.
● Transmit RTR register (TRTRR)
This register selects a frame format transmitted to each message buffer. It selects the data frame or remote
frame.
● Remote frame receive waiting register (RFWTR)
This register sets the condition for transmitting start when a transmit request of the data frame is set.
● Transmit complete register (TCR)
The bit is set which is corresponding to the number of the message buffer that completes message
transmitting.
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CHAPTER 16 CAN CONTROLLER
16.2 Block Diagram of CAN Controller
MB90495G Series
● Transmit complete interrupt enable register (TIER)
This register controls the generation of an interrupt request when each message buffer completes
transmitting. When an interrupt is enabled, an interrupt request is generated when transmitting is
completed.
● Receive complete register (RCR)
This register sets the bit corresponding to the number of the message buffer that completes receiving
message.
● Receive complete interrupt enable register (RIER)
This register controls output of an interrupt request when each message buffer completes receiving. If
output of an interrupt request is enabled, an interrupt request is output at completion of receiving.
● Receive RTR register (RRTRR)
When a remote frame is stored in a message buffer, the bit corresponding to the number of the message
buffer is set.
● Receive overrun register (ROVRR)
This register sets the bit corresponding to the number of the buffer that overruns when the message is
received.
● Acceptance mask select register (AMSR)
This register sets the method for masking the receive message for each message buffer.
● Acceptance mask registers (AMR0 and AMR1)
These registers set a mask with the ID for filtering the message to be received.
● Last event indication register (LEIR)
This register indicates the operating state that last occurred. It indicates that either node status transition,
transmitting completion, or receiving completion occurred.
● Prescaler
The prescaler generates a bit timing clock at a frequency of 1/1 to 1/64 of the system clock.
It sets the operation clock (TQ).
● Bit timing generator
This generator detects a bit timing clock signal to generate a sync segment and time segments 1 and 2.
● Node status transition interrupt generator
This generates a node status transition interrupt signal when the node status transits.
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CHAPTER 16 CAN CONTROLLER
16.2 Block Diagram of CAN Controller
MB90495G Series
● Bus state identification circuit
This circuit identifies the CAN bus state from the bus halt bit (CSR:HALT) and the signal from the error
frame generator.
● Acceptance filter
This filter compares the receive message ID with the acceptance code to select the message to be received.
● Transmit message buffers/receive message buffers
There are 8 message buffers to store the message to be transmitted and received.
● CRC generator/ACK generator
This circuit generates a CRC field or an ACK field when a data frame or remote frame is transmitted.
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
16.3
Configuration of CAN Controller
This section explains the pins and, related registers, interrupt factors of the CAN
controller.
■ Pins of CAN Controller
Table 16.3-1 Pins of CAN Controller
Pin Name
Pin Function
Setting of Pin Used in CAN Controller
TX
Transmit output pin
General-purpose I/O port
Specify TX pin as transmit output pin
(when TOE bit in CSR register set to 1)
RX
Receive input pin
General-purpose I/O port
Specify RX pin as receive input pin
(when bit 4 in DDR4 register set to 0)
■ Block Diagram for Pins of CAN Controller
See "CHAPTER 4 I/O PORT" for details of the block diagram of pins.
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
■ CAN Controller Registers
Figure 16.3-1, Figure 16.3-2 and Figure 16.3-3 list the registers of the CAN controller.
Figure 16.3-1 Registers of CAN Controller (Control Registers)
CAN controller control register
bit 15
bit 8
bit 7
bit 0
Reset value
Reserved area*
BVALR (Message buffer enable register)
00000000
B
Reserved area*
TREQR (Transmission request register)
000000 00
B
Reserved area*
TCANR (Transmission cancel register)
000000 00
B
Reserved area*
TCR (Transmission complete register)
000000 00
B
Reserved area*
RCR (Reception complete register)
000000 00
B
Reserved area*
RRTRR (Reception RTR register)
000000 00
B
Reserved area*
ROVRR (Reception overrun register)
000000 00
B
Reserved area*
RIER (Reception complete interrupt enable register)
000000 00
B
bit 15
bit 8
bit 7
bit 0
CSR (Control status register)
Reserved area*
Reset value
00XXX000
B
LEIR (Last event indicate register)
0XXXX0 01
B
000XX0 00
B
RTEC (Receive/transmit error counter)
00000000
B
000000 00
B
BTR (Bit timing register)
X1111111
B
111111 11
B
Reserved area*
IDER (IDE register)
XXXXXXXX
B
Reserved area*
TRTRR(Transmission RTR register)
000000 00
B
Reserved area*
RFWTR (Remote frame receive waiting register)
XXXXXXXX
B
Reserved area*
TIER (Transmission complete interrupt enable register)
000000 00
B
XXXXXXXX
B
AMSR (Acceptance mask select register)
XXXXXXXX
B
Reserved area*
AMR0 (Acceptance mask register 0)
AMR1 (Acceptance mask register 1)
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
B
B
B
B
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
B
B
B
B
*: Reserved area cannot be used because address is used in the system.
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Figure 16.3-2 Registers of CAN Controller (ID Register and DLC Register)
Message buffer (ID register)
bit 15
bit 8
bit 7
bit 0
RAM (General-purpose RAM) (16 bytes)
XXXXXXXX
~
IDR0 (ID register 0)
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
IDR1 (ID register 1)
XXXXXXXX
XXXXXXXX
IDR2 (ID register 2)
IDR3 (ID register 3)
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
IDR4 (ID register 4)
IDR5 (ID register 5)
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
IDR6 (ID register 6)
XXXXXXXX
XXXXXXXX
IDR7 (ID register 7)
Message buffer (DLC register)
bit 15
bit 8
bit 7
Reset value
bit 0
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
~
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
Reset value
Reserved area*
DLC0 (DLC register 0)
XXXXXXXX B
Reserved area*
DLC1 (DLC register 1)
XXXXXXXX B
Reserved area*
DLC2 (DLC register 2)
XXXXXXXX B
Reserved area*
DLC3 (DLC register 3)
XXXXXXXX B
Reserved area*
DLC4 (DLC register 4)
XXXXXXXX B
Reserved area*
DLC5 (DLC register 5)
XXXXXXXX B
Reserved area*
DLC6 (DLC register 6)
XXXXXXXX B
Reserved area*
DLC7 (DLC register 7)
XXXXXXXX B
*: Reserved area cannot be used because address is used in the system.
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Figure 16.3-3 Registers of CAN Controller (DTR Register)
Message buffer (DTR register)
bit 15
bit 8
bit 7
bit 0
DTR0 (Data register 0) (8 bytes)
DTR1 (Data register 1) (8 bytes)
DTR2 (Data register 2) (8 bytes)
DTR3 (Data register 3) (8 bytes)
DTR4 (Data register 4) (8 bytes)
DTR5 (Data register 5) (8 bytes)
DTR6 (Data register 6) (8 bytes)
DTR7 (Data register 7) (8 bytes)
Reset value
XXXXXXXX
~
XXXXXXXX
~
XXXXXXXX
~
XXXXXXXX
~
XXXXXXXX
~
XXXXXXXX
~
XXXXXXXX
~
XXXXXXXX
~
B
B
B
B
B
B
B
B
~
XXXXXXXX
B
~
XXXXXXXX
B
~
XXXXXXXX
B
~
XXXXXXXX
B
~
XXXXXXXX
B
~
XXXXXXXX
B
~
XXXXXXXX
B
~
XXXXXXXX
B
Reserved area* (128 bytes)
*: Reserved area cannot be used because address is used in the system.
■ Generation of Interrupt Request by CAN Controller
The CAN controller has a transmit complete interrupt, receive complete interrupt, and node status interrupt.
Each interrupt request is generated as follows:
• When a transmit complete interrupt is enabled for the message buffer (x) (TIRE:TIEx = 1), the TCx bit
in the transmit complete register is set to 1 and a transmit complete interrupt request is generated after a
completion of message transmitting.
• When a receive complete interrupt is enabled for the message buffer (x) (RIRE:RIEx = 1), the RCx bit
in the receive complete register is set to 1 and a receive complete interrupt request is generated after a
completion of message receiving.
• When a node status transition interrupt is enabled (CSR:NIE = 1), the NT bit in the CAN status register
is set to 1 and a node status transition interrupt request is generated after the node status transits.
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
16.3.1
Control Status Register (High) (CSR:H)
The control status register (CSR) controls operation of the CAN controller. The control
status register (High) (CSR:H) transmits and receives the message and indicates the
node status.
■ Control Status Register (High) (CSR:H)
Figure 16.3-4 Control Status Register (High) (CSR:H)
15
14
13
12
11
10
9
8
Reset value
00XXX000B
R
R
⎯
⎯
⎯ R/W
R
R
bit 9 bit 8
NS1 NS0
0
0
0
1
1
0
1
1
Node status bits
Error active
Warning (error active)
Error passive
Bus off
bit 10
Node status transition flag
NT
No node status transition
0
Node status transition
1
bit 14
Receive status bit
RS
Message
is
not
received
0
Message is being received
1
R/W
R
X
⎯
Note:
CM44-10114-7E
:
:
:
:
:
Read/Write
Read only
Undefined
Unused
Reset value
bit 15
Transmit status bit
TS
Message is not transmittes
0
Message is being transmitted
1
It is prohibited to execute a bit operation (read-modify-write) instruction on the lower 8 bits of control
status register (CSR).
Only in the case of HALT bits unchanged, use any bit operation instructions without problems
(initialization of the macro instructions etc.).
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Table 16.3-2 Functions of Control Status Register (High) (CSR:H)
Bit Name
bit 8
bit 9
NS1, NS0:
Node status bits
The combination of the NS1 and NS0 bits indicates the current node status.
00B: Error active
01B: Warning (error active)
10B: Error passive
11B: Bus off
Note:
Warning is included in error active in the CAN specifications as a node
status.
bit 10
NT:
Node status transition
flag bit
This bit indicates that the node status transits.
When node status transits: Bit set to 1.
1. Error active (00B) --> Warning (01B)
2. Warning (01B) --> Error Passive (10B)
3. Error Passive (10B) --> Bus off (11B)
4. Bus off (11B) --> Error active (00B)
(The parenthesized values are those for the NS1 and NS0 bits.)
When set to 0: Clears this bit.
When set to 1: Disables bit setting.
Read using read modify write instructions: 1 always read
Unused bits
Read: Value not fixed
Write: No effect
RS:
Receive status bit
This bit indicates whether the message is being received.
Message being received: Bit set to 1.
• For example, if the message is on the bus, even during message
transmitting, this bit is set to 1 regardless of whether the receive message
passes the acceptance filter.
Error frame or overload frame on bus: Bit set to 0.
• When the RS bit is 0, the bus halt state (HALT = 1), bus intermission state
and bus idle state are also included.
TS:
Transmit status bit
This bit indicates whether the message is being transmitted.
Message being transmitted: Bit set to 1.
Error frame or overload frame being transmitted: Bit set to 0.
bit 11 to bit 13
bit 14
bit 15
520
Function
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
16.3.2
Control Status Register (Low) (CSR:L)
The control status register (CSR) controls operation of the CAN controller. The control
status register (Low) (CSR:L) enables and disables transmit interrupt and node status
transition interrupt and, controls bus halt and indicates the node status.
■ Control Status Register (Low) (CSR:L)
Figure 16.3-5 Control Status Register (Low) (CSR:L)
6
7
5
4
3
2
1
0
Reset value
0XXXX001B
R/W
⎯
⎯
⎯
⎯ R/W
W R/W
bit 0
HALT
0
1
Bus operation stop bit
Cancels bus operation stop
(bus operation not in stop mode)
Stops bus operation
(bus operation in stop state)
bit 1
Reserved
0
Reserved bit
Always set "0"
bit 2
NIE
0
1
Node status transition interrupt output enable bit
Interrupt output disable by node status transition
Interrupt output enable by node status transition
bit 7
R/W
W
X
⎯
Note:
CM44-10114-7E
:
:
:
:
:
Read/Write
Write only
Undefined
Unused
Reset value
TOE
0
1
Transmit output enable bit
Used as general-purpose I/O port
Used as transmit pin TX
It is prohibited to execute a bit operation (read-modify-write) instruction on the lower 8 bits of control
status register (CSR).
Only in the case of HALT bits unchanged, use any bit operation instructions without problems
(initialization of the macro instructions etc.).
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Table 16.3-3 Functions of Control Status Register (Low) (CSR:L) (1 / 2)
Bit Name
bit 0
522
HALT:
Bus halt bit
Function
This bit controls the bus halt. The halt state of the bus can be checked by
reading this bit.
Writing to this bit
0: Cancels bus operation stop
1: Sets bus operation stop
Reading this bit
0: Bus operation not in stop state
1: Bus operation in stop state
Note:
• When write 0 to this bit during the node status is Bus Off, ensure that 1 is
written to this bit.
Example program:
switch ( IO_CANCT0.CSR.bit.NS )
{
case 0 : /* error active */
break;
case 1 : /* warning */
break;
case 2 : /* error passive */
break;
default : /* bus off */
for ( i=0; ( i <= 500 ) && ( IO_CANCT0.CSR.bit.
HALT == 0); i++);
IO_CANCT0.CSR.word = 0x0084; /* HALT = 0 */
break;
}
* : The variable "i" is used for fail-safe.
[Conditions for halting bus]
• Hardware reset
• Node status transition to bus off
• Writing 1 to HALT bit
[Operation when bus halted]
Message being transmitted: Bus halted after completion of transmitting
Message being receiving: Bus halted immediately
Storing in message buffer: Bus halted after completion of storing
Notes:
• To check whether the bus is halted, read the value of the HALT bit.
• To switch to the low-power consumption, write 1 to the HALT bit, and then
read the HALT bit to check that the bus is completely halted (CSR:HALT =
1).
[Conditions for canceling bus halt]
• The state in which the bus is halted by a hardware reset or by writing 1 to
the HALT bit is cancelled after 0 is written to the HALT bit and an 11-bit
High level (receive) is input continuously to the receive input pin (RX).
• The state in the bus off is cancelled after 0 is written to the HALT bit and an
11-bit High level (receive) is input continuously 128 times to the receive
input pin (RX).
• The values of the transmit and receive error counters are both returned to 0
and the node status transits to error active.
• When write 0 to HALT during the node status is Bus Off, ensure that 1 is
written to this bit.
[State in which bus halted]
• Transmitting and receiving are not performed.
• A High level (receive) is output to the transmit output pin (TX).
• Values of other register and error counter remain unchanged.
Note:
• Set the bit timing register (BTR) after halting the bus.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Table 16.3-3 Functions of Control Status Register (Low) (CSR:L) (2 / 2)
Bit Name
Function
bit 1
Reserved: Reserved bit
bit 2
NIE:
This bit controls generation of a node status transition interrupt when the node
Node status transition
status transits (CSR:NT = 1).
interrupt output enable bit When set to 0: Disables interrupt generation
When set to 1: Enables interrupt generation
bit 3 to bit 6
bit 7
CM44-10114-7E
Unused bits
Always set this bit to 0.
Read: 0 is always read.
Read: Value not fixed
Write: No effect
TOE:
This bit switches between the general-purpose I/O port and the transmit pin
Transmit output enable bit (TX).
When set to 0: Functions as general-purpose I/O port
When set to 1: Functions as transmit pin (TX)
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
16.3.3
MB90495G Series
Last Event Indicate Register (LEIR)
This register indicates the state of the last event (LEIR).
■ Last Event Indicate Register (LEIR)
Figure 16.3-6 Last Event Indicate Register (LEIR)
bit 7
6
5
4
3
2
1
0
Reset value
000XX000
R/W R/W R/W ⎯
B
⎯ R/W R/W R/W
bit 2
MBP2
0
0
0
0
1
1
1
1
bit 1
MBP1
0
0
1
1
0
0
1
1
bit 0
MBP0
0
1
0
1
0
1
0
1
Message buffer pointer bits
Message buffer 0
Message buffer 1
Message buffer 2
Message buffer 3
Message buffer 4
Message buffer 5
Message buffer 6
Message buffer 7
bit 5
RCE
0
1
Last event = reception complete bit
Reception is not completed.
Reception is completed.
bit 6
TCE
0
1
Last event = transmission complete bit
Transmission is not completed.
Transmission is completed.
bit 7
R/W : Read/Write
X
: Undefined
⎯
: Unused
: Reset value
Note:
524
NTE
0
1
Last event = node status transition bit
No node status transition
Node status transition
When any of the node status transition bit (NTE), transmission complete bit (TCE), and reception
complete bit (RCE) corresponding to the last event is set to 1, other bits are set to 0.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Table 16.3-4 Functions of Last Event Indicate Register (LEIR)
Bit Name
bit 0 to bit 2
Function
MBP2 to MBP0:
Message buffer pointer
bits
These bits indicate the number (x) of the message buffer where the last event
occurs which is corresponding to each message buffer pointer bit.
Receiving completed:Indicates number (x) of message buffer that completes
receiving message
Transmitting completed: Indicates number (x) of message buffer that
completes transmitting message
Node status transition: The values of the MBP2 to MBP0 bits are invalid.
When set to 0: Cleared
When set to 1: No effect
Read by read modify write instruction: 1 always read
bit 3
bit 4
Unused bits
Read: Value not fixed
Write: No effect on operation
bit 5
RCE:
Last event reception
complete bit
This bit indicates that receiving the last event is completed.
Receiving of last event completed:
Sets bit to 1 when RCx bit in reception complete register set (RCR:RCx = 1)
• Nothing is related to the setting of the reception complete interrupt enable
register (RIER).
• The number (x) of the message buffer that completes receiving the
message is indicated as the last event in the MBP2 to MBP0 bits.
When set to 0: Cleared
When set to 1: No effect
Read using read modify write instructions: 1 always read
bit 6
TCE:
Last event transmission
complete bit
This bit indicates that the transmitting the last event is completed.
Transmitting of last event completed:
Sets bit to 1 when TCx bit in transmission complete register set (TCR:TCx =
1)
• Nothing is related to the setting of the transmission complete interrupt
enable register (TIER).
• The number (x) of the message buffer that completes receiving the
message is indicated as the last event in the MBP2 to MBP0 bits.
When set to 0: Cleared
When set to 1: No effect
Read using read modify write instruction: 1 always read
bit 7
NTE:
Last event node status
transition bit
This bit indicates that the last event refers to the node status transition.
Last event referring to node status transition:
Sets bit to 1 when NTx bit in control status register set (CSR:NTx = 1)
• The NTE bit is set to 1 at the same time that the TCx in the transmission
complete register (TCR) is set.
• Nothing is related to the setting of the NIE bit in the control status register
(CSR).
When set to 0: Cleared
When set to 1: No effect
Read by read modify write instruction: 1 always read
Note:
CM44-10114-7E
When the last event indicate register (LEIR) is accessed in interrupt processing of the CAN controller, the
event causing the interrupt does not always match the event indicated by the last event indicate register
(LEIR). Other event may occur before the last event indicate register (LEIR) is accessed in interrupt
processing after an interrupt request is generated.
FUJITSU SEMICONDUCTOR LIMITED
525
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Receive/Transmit Error Counter (RTEC)
16.3.4
The receive/transmit error counter (RTEC) indicates the number of times an error
occurs at transmitting and receiving the message. It counts up when transmit or receive
errors occurs and counts down when transmitting and receiving are performed
normally.
■ Receive/Transmit Error Counter (RTEC)
Figure 16.3-7 Receive/Transmit Error Counter (RTEC)
bit 15
14
13
12
11
10
9
8
Reset value
TEC7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
00000000B
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
Reset value
REC7
REC6
REC5
REC4
REC3
REC2
REC1
REC0
00000000B
R
R
R
R
R
R
R
R
R: Read only
Table 16.3-5 Functions of Receive/Transmit Error Counter (RTEC)
Bit Name
Function
bit 0 to bit 7
REC7 to REC0:
Receive error counter
bits
Receive error counter value = 96 or more:
Node status transits to warning (CSR:NS1, NS0 = 01B)
Receive error counter value = 128 or more:
Node status transits to error passive (CSR:NS1, NS0 = 10B)
Receive error counter value = 256 or more:
Stops counting up. The node status remains with error passive (CSR:NS1,
NS0=10B).
bit 8 to bit 15
TEC7 to TEC0:
Transmit error counter
bits
Transmit error counter value = 96:
Node status transits to warning (CSR:NS1, NS0 = 01B)
Transmit error counter value = 128:
Node status transits to error passive (CSR:NS1, NS0 = 10B)
Transmit error counter value = 256:
Stops counting up. The node status transits to bus off (CSR:NS1, NS0 =
11B).
526
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
■ Node Status Transition due to Error Occurrence
In the CAN controller, the node status transits according to the error count of the receive/transmit error
counter (RTEC). Figure 16.3-8 shows the node status transition.
Figure 16.3-8 Node Status Transition
Hardware reset
Cancellation of bus operation halt is necessary
Error active
REC: Receive error counter
TEC: Transmit error counter
REC ≥ 96
or TEC ≥ 96
REC < 96
besides TEC < 96
Warning
(error active)
After 0 was written to the HALT
bit of the control status register (CSR),
continuous 11-bit High levels
(recessive) are input 128 times to the
receive input pin (RX) to transit.
REC ≥ 128
or TEC ≥ 128
REC < 128
besides TEC < 128
Error passive
TEC ≥ 256
Bus off
(HALT = 1)
Table 16.3-6 Node Status
Node Status
Error active
State of CAN Bus
Normal state
Warning
A bus fault occurs
Error passive
Bus off
CM44-10114-7E
Communications are disabled. The CAN controller is completely isolated
from the CAN bus.
(To return to the normal state, perform the steps in the above figure.)
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
16.3.5
MB90495G Series
Bit Timing Register (BTR)
The bit timing register (BTR) sets the prescaler and bit timing. After halting the bus
(CSR:HALT = 1).
■ Bit Timing Register (BTR)
Figure 16.3-9 Bit Timing Register (BTR)
bit 15
14
13
12
11
10
9
8
Reset value
TS2.2
TS2.1
TS2.0
TS1.3
TS1.2
TS1.1
TS1.0
X1111111B
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Reset value
RSJ1
RSJ0
PSC5
PSC4
PSC3
PSC2
PSC1
PSC0
11111111B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Read/Write
X
: Undefined
⎯ : Unused
Table 16.3-7 Functions of Bit Timing Register (BTR)
Bit Name
Function
bit 0 to bit 5
PSC5 to PSC0:
Prescaler setting bits 5 to 0
• These bits divide the frequency of the system clock to determine the
time quantum (TQ) of the CAN controller.
bit 6 to bit 7
RSJ1, RSJ0:
Resynchronous jump
width setting bits 1, 0
• These bits set the resynchronous jump width (RSJW).
bit 8 to
bit 11
TS1.3 to TS1.0:
Time segment 1 setting
bits 3 to 0
• These bits set the time of time segment 1 (TSEG1). Time segment 1 is
equivalent to propagation segment (PROP_EG) and phase buffer
segment 1 (PHASE_SEG1) based on CAN specifications.
bit 12 to
bit 14
TS2.2 to TS2.0:
Time segment 2 setting
bits 2 to 0
• These bits set the time of time segment 2 (TSEG2). Time segment 2 is
equivalent to phase buffer segment 2 (PHASE_SEG2) based on CAN
specifications.
Note:
Set the bit timing register (BTR) after halting the bus (CSR:HALT = 1). After setting the bit timing register (BTR),
write 0 to the HALT bit in the control status register to cancel the bus halt.
528
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
■ Definition of Bit Timing Segment
Bit timing is set in the bit timing register (BTR). Figure 16.3-10 and Figure 16.3-11 show the segments of
the nominal bit time (one bit of time within message) and bit timing register (BTR).
● Bit time segments of general CAN specifications
Figure 16.3-10 Bit Time Segments of General CAN Specifications
Normal bit time
SYNC_SEG
(Sync segment)
PROP_SEG
(Propagation segment)
PHASE_SEG1
(Phase segment 1)
PHASE_SEG2
(Phase segment 2)
Sampling point
• SYNC_SEG (sync segment): Synchronization is performed to shorten or prolong the bit time.
• PROP_SEG (propagation segment): The physical delay among networks is adjusted.
• PHASE_SEG (phase segment): The phase shift due to oscillation errors is adjusted.
● Bit time segments of Fujitsu CAN controller
The propagation segment (PROP_SEG) and phase segment 1 (PHASE_SEG1) are used as the time
segment 1 (TSEG1). The phase segment 2 (PHASE_SEG2) is used as the time segment 2 (TSEG2).
Figure 16.3-11 Bit Time Segments of CAN Controller
Normal bit time
SYNC_SEG
(Sync segment)
TSEG1
(Time segment 1)
TSEG2
(Time segment 2)
Sampling point
• TSEG1 = PROP_SEG + PHASE_SEG1
• TSEG2 = PHASE_SEG2
CM44-10114-7E
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
■ Calculation of Bit Timing
Figure 16.3-12 and Figure 16.3-13 show the calculation example of bit timing, respectively, assuming input
clock (CLK), time quantum (TQ), bit time (BT), synchronous segment (SYNC_SEG), time segments 1 and
2 (TSEG1, TSEG2), resynchronous jump width (RSJW), and frequency division (PSC).
Figure 16.3-12 Calculation of Bit Timing
. TQ = (PSC + 1) × CLK
. BT = SYNC_SEG + TSEG1 + TSEG2
= (1 + (TS1 + 1) + (TS2 + 1) ) × TQ
= (3 + TS1 + TS2) × TQ
. RSJW = (RSJ + 1) × TQ
For each segment, the following conditions shoud be met.
. When PSC is 1 to 63 (2 to 64-devided clock)
TSEG1 ≥ 2TQ
TSEG1 ≥ RSJW
TSEG2 ≥ 2TQ
TSEG2 ≥ RSJW
. When PSC is 0 (1-devided clock)
TSEG1 ≥ 5TQ
TSEG2 ≥ 2TQ
TSEG2 ≥ RSJW
530
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Figure 16.3-13 Calculation Example of Bit Timing
Example: When 1TQ is 1/20 bit timing at 100 kbps (1/100 kbps/20)
Condition: (resynchronous jump width is 4TQ, delay time is 50 μs)
(1) Calculations of time quantum (TQ) [TQ = (PSC + 1) × CLK]
Machine clock (CLK)
4 MHz (0.25 μs)
8 MHz (0.125 μs)
16 MHz (0.0625 μs)
(unit: μs)
Frequency division of input clock (PSC+1)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75
0.13 0.25 0.38 0.5 0.63 0.75 0.88 1 1.13 1.25 1.38 1.5 1.63 1.75 1.88
0.06 0.13 0.19 0.25 0.31 0.38 0.44 0.5 0.56 0.63 0.69 0.75 0.81 0.88 0.94
(4) Conditions of bit timing (BT) [BT ≥ 8TQ]
Machine clock (CLK)
4 MHz (0.25 μs)
8 MHz (0.125 μs)
16 MHz (0.0625 μs)
2
1
0.5
4
2
1
(unit: μs)
6
3
1.5
8
4
2
10
5
2.5
12
6
3
8TQ
14 16 18
7
8
9
3.5
4
4.5
20
10
5
22
11
5.5
24
12
6
26
13
6.5
28
14
7
30
15
7.5
(3) Setting of resynchronous jump width (when resynchronous jump width is 4TQ)
RSJ+1 (frequency division of TQ) 1
0.5
RSJW = (RSJ + 1) × TQ
2
1
3
1.5
4
2
(unit: TQ)
(unit: μs)
2
2
1
3
3
1.5
4
4
2
(unit: TQ)
(unit: TQ)
(unit: μs)
(5) Conditions of TSEG2
RSJW = (RSJ + 1) × TQ
TSEG2 ≥ RSJW
TSEG2 ≥ RSJW
1
1
0.5
(6) Conditions of TSEG1
TSEG1 ≥ Delay time + RSJW (Assuming that delay time is 50ns) × 2 + 4TQ ≥ 5TQ
TSEG1
5 (unit: TQ)
(2) Calculation of bit time (BT) based on the above setting and conditions
BT = SYNC_SEG + TSEG1 + TSEG2
= (1 + (TS1 + 1) + (TS2+1)) × TQ
= (3 + TS1 + TS2) × TQ
1
2
3
4
Calculation of sampling point
5
Sampling
6
SYNC_SEG + (TSEG1 + 1) TSEG2 + 1
point
7
(1)
4
16
80%
TSEG1 + 1 8
(2)
5
15
75%
9
(3)
6
14
70%
10
(4)
7
13
65%
11
(5)
8
12
60%
12
13
SYNC_SEG TSEG 1 + 1 TSEG2 + 1
14
15
16
Sampling point
CM44-10114-7E
(unit: kbps)
1
667
500
400
333
286
250
222
200
182
167
154
143
133
125
118
111
2
500
400
333
286
250
222
200
182
167
154
143
133
125
118
111
105
3
400
333
286
250
222
200
182
167
154
143
133
125
118
111
105
100
FUJITSU SEMICONDUCTOR LIMITED
TSEG2 + 1
5
4
333 286
286 250
250 222
222 200
200 182
182 167
167 154
154 143
143 133
133 125
125 118
118 111
111 105
105 100
100 95.2
95.2 90.9
(1) (2)
6
250
222
200
182
167
154
143
133
125
118
111
105
100
95.2
90.9
87
(3)
7
222
200
182
167
154
143
133
125
118
111
105
100
95.2
90.9
87
83.3
(4)
8
200
182
167
154
143
133
125
118
111
105
100
95.2
90.9
87
83.3
80
(5)
531
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Message Buffer Valid Register (BVALR)
16.3.6
The message buffer valid register (BVALR) enables or disables the message buffers
and indicates their status.
■ Message Buffer Valid Register (BVALR)
Figure 16.3-14 Message Buffer Valid Register (BVALR)
7
6
5
4
3
2
1
0
Reset value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
BVAL0
0
1
bit 1
BVAL1
0
1
Message buffer enable bit 0
Disables message buffer 0
Enables message buffer 0
Message buffer enable bit 1
Disables message buffer 1
Enables message buffer 1
bit 2
Message buffer enable bit 2
BVAL2
Disables message buffer 2
0
Enables message buffer 2
1
bit 3
BVAL3
0
1
bit 4
BVAL4
0
1
bit 5
BVAL5
0
1
Message buffer enable bit 3
Disables message buffer 3
Enables message buffer 3
Message buffer enable bit 4
Disables message buffer 4
Enables message buffer 4
Message buffer enable bit 5
Disables message buffer 5
Enables message buffer 5
bit 6
Message buffer enable bit 6
BVAL6
Disables message buffer 6
0
Enables message buffer 6
1
bit 7
BVAL7
R/W : Read/Write
: Reset value
532
0
1
Message buffer enable bit 7
Disables message buffer 7
Enables message buffer 7
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Table 16.3-8 Functions of Message Buffer Enable Register
Bit Name
bit 0 to bit 7
Note:
CM44-10114-7E
Function
BVAL7 to BVAL0:
Message buffer enable
bits 7 to 0
These bits enable or disable transmitting and receiving of the message to and
from the message buffer (x).
When set to 0: No message can be transmitted and received to and from the
message buffer (x).
When set to 1: A message can be transmitted and received to and from the
message buffer (x).
[Message buffer disabled (BVALx = 0)]
During transmitting: Transmitting and receiving are disabled after message
transmitting is completed or a transmit error is
terminated.
During receiving: Transmitting and receiving are disabled immediately.
When the received message is stored in the message
buffer, transmitting and receiving are disabled after the
message is stored.
Note:
The read modify write instructions are disabled until the BVALx bit is
actually set to 0 after 0 is written to the bit.
To invalidate the message buffer (by setting the BVALR:BVAL bit to 0) while CAN Controller is
participating in CAN communication (the read value of the CSR:HALT bit is 0 and CAN Controller is
ready to receive or transmit messages), follow the cautions in Section 16.6 "Precautions when Using
CAN Controller".
FUJITSU SEMICONDUCTOR LIMITED
533
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
16.3.7
MB90495G Series
IDE Register (IDER)
The IDE register (IDER) sets the frame format of the message buffer used during
transmitting and receiving. Transmitting and receiving are enabled in the standard
frame format (ID11 bits) and the extended frame format (ID29 bits).
■ IDE Register (IDER)
Figure 16.3-15 IDE Register (IDER)
7
6
5
4
3
2
1
0
Reset value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
IDE0
0
1
bit 1
IDE1
0
1
bit 2
IDE2
0
1
bit 3
IDE3
0
1
bit 4
IDE4
0
1
bit 5
IDE5
0
1
bit 6
IDE6
0
1
bit 7
IDE7
X
: Undefined
R/W : Read/Write
534
0
1
ID format select bit 0 (message buffer 0)
Used in standard fomat (ID 11 bits)
Used in extended format (ID 29 bits)
ID format select bit 1 (message buffer 1)
Used in standard fomat (ID 11 bits)
Used in extended format (ID 29 bits)
ID format select bit 2 (message buffer 2)
Used in standard fomat (ID 11 bits)
Used in extended format (ID 29 bits)
ID format select bit 3 (message buffer 3)
Used in standard fomat (ID 11 bits)
Used in extended format (ID 29 bits)
ID format select bit 4 (message buffer 4)
Used in standard fomat (ID 11 bits)
Used in extended format (ID 29 bits)
ID format select bit 5 (message buffer 5)
Used in standard fomat (ID 11 bits)
Used in extended format (ID 29 bits)
ID format select bit 6 (message buffer 6)
Used in standard fomat (ID 11 bits)
Used in extended format (ID 29 bits)
ID format select bit 7 (message buffer 7)
Used in standard fomat (ID 11 bits)
Used in extended format (ID 29 bits)
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Table 16.3-9 Functions of IDE Register (IDER)
Bit Name
bit 0 to bit 7
Note:
CM44-10114-7E
Function
IDE7 to IDE0:
ID Format select bits 7 to 0
These bits set the ID format of the message buffer (x).
When set to 0: Uses message buffer (x) in standard format (ID11 bits)
When set to 1: Uses message buffer (x) in extended format (ID29 bits)
Note:
The IDE register (IDER) should be set after having the message buffer
(x) disabled (BVALR:BVALx = 0). Setting the IDE register (IDER)
with the message buffer (x) being enabled may store message
unnecessary received.
To invalidate the message buffer (by setting the BVALR:BVAL bit to 0) while CAN Controller is
participating in CAN communication (the read value of the CSR:HALT bit is 0 and CAN Controller is
ready to receive or transmit messages), follow the cautions in Section 16.6 "Precautions when Using
CAN Controller".
FUJITSU SEMICONDUCTOR LIMITED
535
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Transmission Request Register (TREQR)
16.3.8
The transmission request register (TREQR) sets a transmit request for each message
buffer and indicates its status.
■ Transmission Request Register (TREQR)
Figure 16.3-16 Transmission Request Register (TREQR)
7
6
5
4
3
2
1
0
Reset value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
TREQ0
Transmission request bit 0 (message buffer 0)
0
1
Does not request transmission (transmission is not requested)
Requests transmission (transmission is requested)
bit 1
TREQ1
0
1
R/W : Read/Write
: Reset value
536
Transmission request bit 1 (message buffer 1)
Does not request transmission (transmission is not requested)
Requests transmission (transmission is requested)
bit 2
TREQ2
Transmission request bit 2 (message buffer 2)
0
1
Does not request transmission (transmission is not requested)
Requests transmission (transmission is requested)
bit 3
TREQ3
Transmission request bit 3 (message buffer 3)
0
1
Does not request transmission (transmission is not requested)
Requests transmission (transmission is requested)
bit 4
TREQ4
Transmission request bit 4 (message buffer 4)
0
1
Does not request transmission (transmission is not requested)
Requests transmission (transmission is requested)
bit 5
TREQ5
Transmission request bit 5 (message buffer 5)
0
1
Does not request transmission (transmission is not requested)
Requests transmission (transmission is requested)
bit 6
TREQ6
Transmission request bit 6 (message buffer 6)
0
1
Does not request transmission (transmission is not requested)
Requests transmission (transmission is requested)
bit 7
TREQ7
Transmission request bit 7 (message buffer 7)
0
1
Does not request transmission (transmission is not requested)
Requests transmission (transmission is requested)
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Table 16.3-10 Functions of Transmission Request Register (TREQR)
Bit Name
bit 0 to bit7
TREQ7 to TREQ0:
Transmission request
bits 7 to 0
Function
These bits starts transmitting for the message buffer (x).
When set to 0: No effect
When set to 1: Starts transmitting for message buffer (x)
• If more than one transmit complete bit is set (TREQx = 1), transmitting is
started with the lower number of the message buffer (x) that accepts the
transmit request.
• These bits remain 1s during the transmit being requested and are cleared
to 0 when transmitting is completed or the transfer request is cancelled.
• Clearing a transmit request when transmitting is completed (TREQx = 0)
overrides setting of the transmit request bit when 0 is written (TREQx =
1) if both occur at the same time.
Read by read modify write instruction: 1 always read
[Setting of remote frame receive wait bit (RFWTR:RFWTx)]
RFWTx bit = 0: Starts transmitting immediately even if RRTRx bit in
receive RTR register = 1
RFWTx bit = 1: Starts transmitting after remote frame received.
• See "16.3.10 Remote Frame Receiving Wait Register (RFWTR)" for details of the remote frame
receive wait register (RFWTR).
• See "16.3.15 Reception RTR Register (RRTRR)" for details of the receive RTR register (RRTRR).
• See "16.3.11 Transmission Cancel Register (TCANR)" and "16.5.1 Transmission" for details about the
transmit cancellation.
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
16.3.9
MB90495G Series
Transmission RTR Register (TRTRR)
This register sets the frame format of transmit message for the message buffers (x).
■ Transmission RTR Register (TRTRR)
Figure 16.3-17 Transmission RTR Register (TRTRR)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
TRTR0
0
1
Remote frame setting bit 0
(message buffer 0)
Transmits as data frame
Transmits as remote frame
bit 1
TRTR1
0
1
Remote frame setting bit 1
(message buffer 1)
Transmits as data frame
Transmits as remote frame
bit 2
TRTR2
0
1
Remote frame setting bit 2
(message buffer 2)
Transmits as data frame
Transmits as remote frame
bit 3
TRTR3
0
1
Remote frame setting bit 3
(message buffer 3)
Transmits as data frame
Transmits as remote frame
bit 4
TRTR4
0
1
Remote frame setting bit 4
(message buffer 4)
Transmits as data frame
Transmits as remote frame
bit 5
TRTR5
0
1
Remote frame setting bit 5
(message buffer 5)
Transmits as data frame
Transmits as remote frame
bit 6
TRTR6
0
1
Remote frame setting bit 6
(message buffer 6)
Transmits as data frame
Transmits as remote frame
bit 7
TRTR7
R/W : Read/Write
: Reset value
538
0
1
Remote frame setting bit 7
(message buffer 7)
Transmits as data frame
Transmits as remote frame
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
• When 0 is written to each bit in the transmit RTR register (TRTRR), the data frame format is set. When
1 is written to each bit, the remote frame format is set.
Table 16.3-11 Functions of Transmission RTR Register (TRTRR)
Bit Name
bit 0 to bit 7
CM44-10114-7E
TRTR7 to TRTR0:
Remote frame setting
bits 7 to 0
Function
These bits set the transfer format of the message buffer (x) for transmitting or
receiving.
When set to 0: Sets data frame format
When set to 1: Sets remote frame format
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Remote Frame Receiving Wait Register (RFWTR)
16.3.10
Remote frame receiving wait register (RFWTR) sets whether this register waits remote
frame receiving when transmission request of data frame is set.
■ Remote Frame Receiving Wait Register (RFWTR)
Figure 16.3-18 Remote Frame Receive Wait Register (RFWTR)
7
6
5
4
3
2
1
0
Reset value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
RFWT0
0
1
Remote frame receiving wait bit 0
(message buffer 0)
Transmission starts immediately
Transmission starts after receiving remote frame
bit 1
RFWT1
0
1
Remote frame receiving wait bit 1
(message buffer 1)
Transmission starts immediately
Transmission starts after receiving remote frame
bit 2
RFWT2
0
1
Remote frame receiving wait bit 2
(message buffer 2)
Transmission starts immediately
Transmission starts after receiving remote frame
bit 3
RFWT3
0
1
Remote frame receiving wait bit 3
(message buffer 3)
Transmission starts immediately
Transmission starts after receiving remote frame
bit 4
RFWT4
0
1
Remote frame receiving wait bit 4
(message buffer 4)
Transmission starts immediately
Transmission starts after receiving remote frame
bit 5
RFWT5
0
1
bit 6
RFWT6
0
1
Remote frame receiving wait bit 5
(message buffer 5)
Transmission starts immediately
Transmission starts after receiving remote frame
Remote frame receiving wait bit 6
(message buffer 6)
Transmission starts immediately
Transmission starts after receiving remote frame
bit 7
RFWT7
R/W : Read/Write
: Reset vlaue
540
0
1
Remote frame receiving wait bit 7
(message buffer 7)
Transmission starts immediately
Transmission starts after receiving remote frame
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Table 16.3-12 Functions of Remote Frame Receiving Wait Register (RFWTR)
Bit Name
bit 0 to bit 7
Function
RFWT7 to RFWT0:
Remote frame receiving
wait bits 7 to 0
These bits set whether to wait for reception of a remote frame for the
message buffer (x) for which a request to transmit a data frame is set.
When set to 0: Starts transmitting immediately for message buffer (x) for
which a request to transmit data frame set
• Transmitting is started immediately even if the receive RTR register is
already set in the message buffer (x) (RRTRR:RRTRx = 1).
When set to 1: Starts transmitting after remote frame is received in message
buffer (x) in which a request to transmit a data frame
Note:
When transmitting a remote frame, do not write 1 to the RFWTx bit.
• See "16.3.8 Transmission Request Register (TREQR)" for details of the transmission request register
(TREQR).
• See "16.3.9
(TRTRR).
Transmission RTR Register (TRTRR)" for details of the transmission RTR register
• See "16.3.15 Reception RTR Register (RRTRR)" for details of the receive RTR register (RRTRR).
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Transmission Cancel Register (TCANR)
16.3.11
The transmission cancel register (TCANR) sets cancellation of a transmission request
for the message buffer in the transmit wait state.
■ Transmission Cancel Register (TCANR)
Figure 16.3-19 Transmission Cancel Register (TCANR)
7
6
5
4
3
2
1
0
W
W
W
W
W
W
W
W
Reset value
00000000 B
bit 0
TCAN0
0
1
bit 1
TCAN1
0
1
bit 2
TCAN2
0
1
bit 3
TCAN3
0
1
bit 4
TCAN4
0
1
bit 5
TCAN5
0
1
bit 6
TCAN6
0
1
bit 7
TCAN7
W
542
: Write only
: Reset value
0
1
Transmission cancel bit 0
No effect
Cancels transmission request of message buffer 0
Transmission cancel bit 1
No effect
Cancels transmission request of message buffer 1
Transmission cancel bit 2
No effect
Cancels transmission request of message buffer 2
Transmission cancel bit 3
No effect
Cancels transmission request of message buffer 3
Transmission cancel bit 4
No effect
Cancels transmission request of message buffer 4
Transmission cancel bit 5
No effect
Cancels transmission request of message buffer 5
Transmission cancel bit 6
No effect
Cancels transmission request of message buffer 6
Transmission cancel bit 7
No effect
Cancels transmission request of message buffer 7
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Table 16.3-13 Functions of Transmission Cancel Register (TCANR)
Bit Name
bit 0 to bit 7
CM44-10114-7E
Function
TCAN7 to TCAN0:
Transmission on cancel
bits 7 to 0
These bits cancel a transmission request for the message buffer (x) in the
transmit wait state.
When set to 0: No effect
When set to 1: Cancels transmission request for message buffer (x)
• When a transmission request is cancelled by setting 1 to the TCANx bit,
the TREQx bit corresponding to the message buffer (x) is cleared
(TREQx = 0) for which transmission request is cancelled.
Read: 0 always read
Note:
The transmission cancel register (TCANR) is a write-only register.
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
16.3.12
MB90495G Series
Transmission Complete Register (TCR)
The transmission complete register (TCR) indicates whether transmitting a data from
the message buffer completes. When an output of interrupt is enabled at completing
transmitting, an interrupt request is output when transmitting is completed.
■ Transmission Complete Register (TCR)
Figure 16.3-20 Transmission Complete Register (TCR)
7
6
5
4
3
2
1
0
Reset value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Read/Write
: Reset value
544
bit 0
TC0
0
1
Transmission is not completed/no transmission
Transmission is completed
bit 1
TC1
0
1
Transmission is not completed/no transmission
Transmission is completed
bit 2
TC2
0
1
Transmission is not completed/no transmission
Transmission is completed
bit 3
TC3
0
1
Transmission is not completed/no transmission
Transmission is completed
bit 4
TC4
0
1
Transmission is not completed/no transmission
Transmission is completed
bit 5
TC5
0
1
Transmission is not completed/no transmission
Transmission is completed
Transmission complete bit 0 (message buffer 0)
Transmission complete bit 1 (message buffer 1)
Transmission complete bit 2 (message buffer 2)
Transmission complete bit 3 (message buffer 3)
Transmission complete bit 4 (message buffer 4)
Transmission complete bit 5 (message buffer 5)
bit 6
TC6
0
1
Transmission is not completed/no transmission
Transmission is completed
bit 7
TC7
0
1
Transmission is not completed/no transmission
Transmission is completed
Transmission complete bit 6 (message buffer 6)
Transmission complete bit 7 (message buffer 7)
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Table 16.3-14 Functions of Transmission Complete Register (TCR)
Bit Name
bit 0 to bit 7
CM44-10114-7E
Function
TC7 to TC0:
Transmission complete
bits 7 to 0
These bits indicate whether the message buffer (x) completes transmitting
message.
When message transmitting completed:
1 is set to the TCx bit corresponding to the message buffer (x) that
completes transmitting.
When set to 0: Clears bits if transmitting already completed
When set to 1: No effect
Read by read modify write instruction: 1 always read
• Setting the TCx bit when transmitting is completed (TCx = 1) overrides
clearing of the TCx bit when 0 is written (TCx = 0) if both occur at the
same time.
• When the TREQx bit in the transmit request register (TREQR) is set
(TREQR:TREQx = 1), the TCx bit is cleared (TCx = 0).
[Generation of transmission complete interrupt]
• If the transmit complete interrupt enable register (TIER) is set
(TIER:TIEx = 1), a transmit complete interrupt is generated when
transmitting is completed (TCR:TCx = 1).
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Transmission Complete Interrupt Enable Register (TIER)
16.3.13
The transmission complete interrupt enable register (TIER) enables or disables a
transmit complete interrupt for each message buffer.
■ Transmission Interrupt Enable Register (TIER)
Figure 16.3-21 Transmission complete Interrupt Enable Register (TIER)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
TIE0
0
1
Transmission interrupt enable bit 0
(message buffer 0)
Disables transmission complete interrupt
Enables transmission complete interrupt
bit 1
TIE1
0
1
Transmission interrupt enable bit 1
(message buffer 1)
Disables transmission complete interrupt
Enables transmission complete interrupt
bit 2
TIE2
0
1
Transmission interrupt enable bit 2
(message buffer 2)
Disables transmission complete interrupt
Enables transmission complete interrupt
bit 3
TIE3
0
1
Transmission interrupt enable bit 3
(message buffer 3)
Disables transmission complete interrupt
Enables transmission complete interrupt
bit 4
TIE4
0
1
Transmission interrupt enable bit 4
(message buffer 4)
Disables transmission complete interrupt
Enables transmission complete interrupt
bit 5
TIE5
0
1
Transmission interrupt enable bit 5
(message buffer 5)
Disables transmission complete interrupt
Enables transmission complete interrupt
bit 6
TIE6
0
1
Transmission interrupt enable bit 6
(message buffer 6)
Disables transmission complete interrupt
Enables transmission complete interrupt
bit 7
TIE7
R/W : Read/Write
: Reset value
546
0
1
Transmission interrupt enable bit 7
(message buffer 7)
Disables transmission complete interrupt
Enables transmission complete interrupt
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Table 16.3-15 Functions of Transmission Complete Interrupt Enable Register (TIER)
Bit Name
bit 0 to bit 7
CM44-10114-7E
Function
TIE7 to TIE0:
Transmission complete
interrupt enable bits 7 to 0
These bits enable or disable a transmission complete interrupt for the
message buffer (x).
When set to 0: Disables transmit complete interrupt for message buffer (x)
When set to 1: Enables transmit complete interrupt for message buffer (x)
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
16.3.14
MB90495G Series
Reception Complete Register (RCR)
The reception complete register (RCR) indicates whether the reception a data to the
message buffer (x) completes receiving. When an interrupt is enabled at completion of
receiving, an interrupt request is generated.
■ Reception Complete Register (RCR)
Figure 16.3-22 Reception Complete Register (RCR)
7
6
5
4
3
2
1
0
Reset value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Read/Write
: Reset value
548
bit 0
RC0
0
1
Reception is not completed/no reception
Reception is completed
bit 1
RC1
0
1
Reception is not completed/no reception
Reception is completed
bit 2
RC2
0
1
Reception is not completed/no reception
Reception is completed
Reception complete bit 0 (message buffer 0)
Reception complete bit 1 (message buffer 1)
Reception complete bit 2 (message buffer 2)
bit 3
RC3
0
1
Reception is not completed/no reception
Reception is completed
bit 4
RC4
0
1
Reception is not completed/no reception
Reception is completed
bit 5
RC5
0
1
Reception is not completed/no reception
Reception is completed
bit 6
RC6
0
1
Reception is not completed/no reception
Reception is completed
bit 7
RC7
0
1
Reception complete bit 3 (message buffer 3)
Reception complete bit 4 (message buffer 4)
Reception complete bit 5 (message buffer 5)
Reception complete bit 6 (message buffer 6)
Reception complete bit 7 (message buffer 7)
Reception is not completed/no reception
Reception is completed
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Table 16.3-16 Functions of Reception Complete Register (RCR)
Bit Name
bit 0 to bit 7
CM44-10114-7E
Function
RC7 to RC0:
Reception complete bits
7 to 0
These bits indicate whether the message buffer (x) completes message
transmitting.
When message receiving completed:
1 is set to the RCx bit corresponding to the message buffer (x) that
completes receiving.
When set to 0: Clears bits when receiving already completed
When set to 1: No effect
Read by read modify write instruction: 1 always read.
• Setting the RCx bit when receiving is completed (TCx = 1) overrides
clearing of the RCx bit when 0 is written (RCx = 0) if both occur at the
same time.
[Generation of reception complete interrupt]
• If the transmit complete enable register is set (RIER:RIEx = 1), a
reception complete interrupt is generated when receiving is completed.
Note:
To clear the reception complete register (RCR), read the received
message after the completion of receiving and write 0.
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
16.3.15
MB90495G Series
Reception RTR Register (RRTRR)
The reception RTR register (RRTRR) indicates that the remote frame is stored in the
message buffer.
■ Reception RTR Register (RRTRR)
Figure 16.3-23 Reception RTR Register (RRTRR)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
RRTR0
0
1
Remote frame receive bit 0
(message buffer 0)
Remote frame is not received
Remote frame is received
bit 1
RRTR1
0
1
Remote frame receive bit 1
(message buffer 1)
Remote frame is not received
Remote frame is received
bit 2
RRTR2
0
1
Remote frame receive bit 2
(message buffer 2)
Remote frame is not received
Remote frame is received
bit 3
RRTR3
0
1
Remote frame receive bit 3
(message buffer 3)
Remote frame is not received
Remote frame is received
bit 4
RRTR4
0
1
Remote frame receive bit 4
(message buffer 4)
Remote frame is not received
Remote frame is received
bit 5
RRTR5
0
1
Remote frame receive bit 5
(message buffer 5)
Remote frame is not received
Remote frame is received
bit 6
RRTR6
0
1
Remote frame receive bit 6
(message buffer 6)
Remote frame is not received
Remote frame is received
bit 7
RRTR7
R/W : Read/Write
: Reset value
550
0
1
Remote frame receive bit 7
(message buffer 7)
Remote frame is not received
Remote frame is received
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Table 16.3-17 Functions of Reception RTR Register (RRTRR)
Bit Name
bit 0 to bit 7
CM44-10114-7E
Function
RRTR7 to RRTR0:
Remote frame receive
bits 7 to 0
These bits indicate that the message buffer (x) receives a remote frame.
When remote frame is received:
1 is set to the RRTRx bit corresponding to the message buffer (x) that
receives a remote frame.
When set to 0: Cleared when receiving completed
When set to 1: No effect
• Setting the RRTRx bit when a remote frame is received (RRTRx = 1)
overrides clearing of the RRTRx bit when 0 is written (RRTRx = 0) if
both occur at the same time.
• The RRTRx bit corresponding to the message buffer (x) that receives a
data frame is cleared (RRTRx = 0).
• If message transmitting is completed (TCR:TCx = 1), the RRTRx bit
corresponding to the message buffer (x) that transmits the message is
cleared (RRTRx = 0).
Read by read modify write instruction: 1 always read
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
16.3.16
MB90495G Series
Reception Overrun Register (ROVRR)
The reception overrun register (ROVRR) indicates that an overrun occurs (the
corresponding message buffer is in the receive complete state.) at storing the received
message in the message buffer.
■ Reception Overrun Register (ROVRR)
Figure 16.3-24 Reception Overrun Register (ROVRR)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
ROVR0
0
1
bit 1
ROVR1
0
1
bit 2
ROVR2
0
1
bit 3
ROVR3
0
1
bit 4
ROVR4
0
1
bit 5
ROVR5
0
1
bit 6
ROVR6
0
1
bit 7
ROVR7
R/W : Read/Write
: Reset value
552
0
1
Reception overrun bit 0 (message buffer 0)
Overrun is not occurred
Overrun is occurred
Reception overrun bit 1 (message buffer 1)
Overrun is not occurred
Overrun is occurred
Reception overrun bit 2 (message buffer 2)
Overrun is not occurred
Overrun is occurred
Reception overrun bit 3 (message buffer 3)
Overrun is not occurred
Overrun is occurred
Reception overrun bit 4 (message buffer 4)
Overrun is not occurred
Overrun is occurred
Reception overrun bit 5 (message buffer 5)
Overrun is not occurred
Overrun is occurred
Reception overrun bit 6 (message buffer 6)
Overrun is not occurred
Overrun is occurred
Reception overrun bit 7 (message buffer 7)
Overrun is not occurred
Overrun is occurred
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Table 16.3-18 Functions of Reception Overrun Register (ROVRR)
Bit Name
bit 0 to bit 7
CM44-10114-7E
Function
ROVR7 to ROVR0:
Reception overrun bits 7
to 0
These bits indicate that an overrun occurs at storing the received message in
the message buffer that had completed receiving.
At overrun: 1 is set to the ROVRx bit corresponding to the message buffer
(x) where an overrun occurs.
When set to 0: Cleared when 0 is set to after reception overrun occurred
When set to 1: No effect
Read by read modify write instruction: 1 always read
• Setting the ROVRx bit when an overrun occurs (ROVRx = 1) overrides
clearing of the ROVRx bit when 0 is written (ROVRx = 0) if both occur at
the same time.
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Reception Complete Interrupt Enable Register (RIER)
16.3.17
The reception complete interrupt enable register (RIER) enables or disables a reception
complete interrupt for each message buffer.
■ Reception Complete Interrupt Enable Register (RIER)
Figure 16.3-25 Reception Complete Interrupt Enable Register (RIER)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
RIE0
0
1
bit 1
RIE1
0
1
bit 2
RIE2
0
1
bit 3
RIE3
0
1
bit 4
RIE4
0
1
bit 5
RIE5
0
1
bit 6
RIE6
0
1
bit 7
RIE7
R/W
554
: Read/Write
: Reset value
0
1
Reception complete interrupt enable bit 0 (message buffer 0)
Disables reception complete interrupt
Enables reception complete interrupt
Reception complete interrupt enable bit 1 (message buffer 1)
Disables reception complete interrupt
Enables reception complete interrupt
Reception complete interrupt enable bit 2 (message buffer 2)
Disables reception complete interrupt
Enables reception complete interrupt
Reception complete interrupt enable bit 3 (message buffer 3)
Disables reception complete interrupt
Enables reception complete interrupt
Reception complete interrupt enable bit 4 (message buffer 4)
Disables reception complete interrupt
Enables reception complete interrupt
Reception complete interrupt enable bit 5 (message buffer 5)
Disables reception complete interrupt
Enables reception complete interrupt
Reception complete interrupt enable bit 6 (message buffer 6)
Disables reception complete interrupt
Enables reception complete interrupt
Reception complete interrupt enable bit 7 (message buffer 7)
Disables reception complete interrupt
Enables reception complete interrupt
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Table 16.3-19 Functions of Reception Complete Interrupt Enable Register (RIER)
Bit Name
bit 0 to bit 7
Function
RIE7 to RIE0:
Reception complete
interrupt enable bits 7 to 0
CM44-10114-7E
These bits enable or disable a reception complete interrupt for the message
buffer (x).
When set to 0: Disables reception complete interrupt for message buffer (x)
When set to 1: Enables reception complete interrupt for message buffer (x)
FUJITSU SEMICONDUCTOR LIMITED
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
16.3.18
MB90495G Series
Acceptance Mask Select Register (AMSR)
The acceptance mask select register (AMSR) selects the mask (acceptance mask)
format for comparison between the identifier (ID) of the received message and the
message buffer.
■ Acceptance Mask Select Register (AMSR)
Figure 16.3-26 Acceptance Mask Select Register (AMSR)
bit 15
14
13
12
11
10
9
8
AMS7.1 AMS7.0 AMS6.1 AMS6.0 AMS5.1 AMS5.0 AMS4.1 AMS4.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
AMS3.1 AMS3.0 AMS2.1 AMS2.0 AMS1.1 AMS1.0 AMS0.1 AMS0.0
R/W
R/W
AMSx.1
0
0
1
1
R/W
R/W
AMSx.0
0
1
0
1
R/W
R/W
R/W
Reset value
XXXXXXXXB
Reset value
XXXXXXXXB
R/W
Acceptance mask select bits (x = 7 to 0)
Full-bit comparison
Full-bit mask
Uses acceptance mask register 0 (AMR0)
Uses acceptance mask register 1 (AMR1)
x (7 to 0) is message buffer's number (x).
X
: Undefined
R/W : Read/Write
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Table 16.3-20 Functions of Acceptance Mask Select Register (AMSR)
Bit Name
Function
bit 0 to bit 15
AMS7.0 to AMS0.0,
AMS7.1 to AMS0.1:
Acceptance mask select
bits 7.0 to 0.0, 7.1 to 0.1
Note:
To invalidate the message buffer (by setting the BVALR:BVAL bit to 0) while CAN Controller is
participating in CAN communication (the read value of the CSR:HALT bit is 0 and CAN Controller is
ready to receive or transmit messages), follow the cautions in Section 16.6 "Precautions when Using
CAN Controller".
CM44-10114-7E
These bits select the mask (acceptance mask) format for comparison between
the received message ID and message buffer ID (IDR) for the message buffer
(x).
No comparison with masked bits is made.
Full-bit comparison: All bits are compared in collating the setting values of
the ID register (IDR) with the received message ID.
Full-bit masking: All bits for the setting values of the ID register (IDR) and
the received message ID are masked.
Using acceptance mask register 0 (or 1):
The acceptance mask register 0 or 1 (AMR0 or AMR1) is used as an
acceptance mask filter. At collating the setting values of the ID register
(IDR) with the received message ID, only the bits set to 0 and
corresponding to the AMx bit in the acceptance mask register are compared
and the bits set to 1 and corresponding to the AMx bit are masked.
• If the AMSx.1 and AMSx.0 bits are set to 10B or 11B, always set the
acceptance mask register (AMR0 or AMR1) to be used, too.
Note:
• The acceptance mask select register (AMSR) should be set after disabling
the message buffer (x) to be set (BVALR:BVALx = 0). Setting the
acceptance mask select register (AMSR) with the message buffer (x)
enabled may store a message unnecessary received.
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
16.3.19
MB90495G Series
Acceptance Mask Register (AMR)
The CAN controller has two acceptance mask registers (AMR0 and AMR1). Both of them
can be used in the standard frame format (ID11 bits, AM28 to AM18) and the extended
frame format (ID29 bits, AM28 to AM0).
■ Acceptance Mask Register (AMR)
Figure 16.3-27 Acceptance Mask Register (AMR)
BYTE0
BYTE1
BYTE2
BYTE3
bit7
6
5
4
3
2
1
0
Reset value
AM28
AM27
AM26
AM25
AM24
AM23
AM22
AM21
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit15
14
13
12
11
10
9
8
Reset value
AM20
AM19
AM18
AM17
AM16
AM15
AM14
AM13
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
6
5
4
3
2
1
0
Reset value
AM12
AM11
AM10
AM9
AM8
AM7
AM6
AM5
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
AM4
AM3
AM2
AM1
AM0
R/W
R/W
R/W
R/W
R/W
Reset value
XXXXXXXXB
⎯
⎯
⎯
R/W : Read/Write
X
: Undefined
⎯
: Unused
: Used bits in the standard frame format
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CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Table 16.3-21 Functions of Acceptance Mask Register (AMR)
Bit Name
Function
bit 0 to bit 7
AM21 to AM 28:
Acceptance mask bits 28
to 21 (BYTE0)
bit 8 to bit 15
AM20 to AM 13:
Acceptance mask bits 20
to 13 (BYTE1)
bit 0 to bit 7
AM12 to AM 5:
Acceptance mask bits 12
to 5 (BYTE2)
bit 11 to bit 15
AM4 to AM 0:
Acceptance mask bits 4
to 0 (BYTE3)
Note:
To invalidate the message buffer (by setting the BVALR:BVAL bit to 0) while CAN Controller is
participating in CAN communication (the read value of the CSR:HALT bit is 0 and CAN Controller is
ready to receive or transmit messages), follow the cautions in Section 16.6 "Precautions when Using
CAN Controller".
CM44-10114-7E
These bits set whether to compare or mask each bit at collating the
acceptance code set in the ID register (IDR:IDx) with the received message
ID.
• If the AMSx.1 or AMSx.0 bits of acceptance mask select registers are set
to 10B or 11 B, always set the acceptance mask register (AMR0 or AMR1)
to be used, too.
Standard frame format (IDER:IDEx = 0):
11 bits from AM28 to AM18 are used.
Extended frame format (IDER:IDEx = 1):
29 bits from AM28 to AM0 are used.
When AMx bit set to 0 (compare):
The bits corresponding to the AMx bit set to 0 are compared at collating
the acceptance code set in the ID register (IDR:IDx) with the received
message ID.
When AMx bit set to 1 (mask):
The bits corresponding to the AMx bit set to 1 are masked at collating the
acceptance code set in the ID register (IDR:IDx) with the received message
ID.
Note:
• The acceptance mask select register (AMSR) should be set after disabling
the message buffer (x) to be set (BVALR:BVALx = 0). Setting the
acceptance mask select register (AMSR) with the message buffer (x)
enabled may store a message unnecessary received.
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
16.3.20
MB90495G Series
Message Buffers
The eight message buffers are used for transmission/reception of the message.
■ Message Buffers
• There are 8 message buffers.
• One message register (x) (x = 0 to 7) consists of an ID register (IDRx), DLC register (DLCRx), and data
register (DTRx).
• The message buffer (x) is used to transmit and receive messages.
• Higher priority is given to smaller number message buffer.
- At transmitting, if a transmit request is generated to more than one message buffer, transmitting is
started with the message buffer with the smallest number.
- At receiving, if the received message ID passes the acceptance filter (which compares received
message ID with message buffer ID after acceptance masking) set in more than one message buffer, a
received message is stored in the message buffer with the smallest number.
• If the same acceptance filter is set in more than one message buffer, it can be used as multiple message
buffers. This provides sufficient time to perform receiving.
Notes:
Write by words to the message buffer area and general-purpose RAM area. At writing by bytes,
undefined data is written to the upper bytes and writing to the upper bytes is ignored when writing to the
lower bytes is performed.
The message buffer (x) area disabled by the message buffer enable register (BVALR:BVALx = 0) can be
used as a general-purpose RAM area. However, during transmitting or receiving, it may take up to 64
machine cycles to access the message buffer area and general-purpose RAM area.
• See "16.5.1 Transmission"
• See "16.5.2 Reception"
• See "16.5.4 Setting Multiple Message Receiving" for details of the configuration of the multiple
message buffer.
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CM44-10114-7E
CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
16.3.21
ID Register (IDRx, x = 7 to 0)
The ID register (IDR) sets the ID of the message buffer used for transmitting and
receiving. In the standard frame format 11 bits from ID28 to ID18 are used, and in the
extended frame format 29 bits from ID28 to ID0 are used.
■ ID Register (IDR)
Figure 16.3-28 ID Register (IDR)
BYTE0
BYTE1
BYTE2
BYTE3
bit7
6
5
4
3
2
1
0
Reset value
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
Reset value
ID20
ID19
ID18
ID17
ID16
ID15
ID14
ID13
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
Reset value
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit15
14
13
12
11
10
9
8
ID4
ID3
ID2
ID1
ID0
R/W
R/W
R/W
R/W
R/W
Reset value
XXXXXXXXB
⎯
⎯
⎯
R/W : Read/Write
X
: Undefined
⎯
: Unused
: Used bits in the standard frame format
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
Table 16.3-22 Functions of ID Register (IDR)
Bit Name
bit 0 to bit 7
ID28 to ID21:
ID bits 28 to 21
(BYTE0)
bit 8 to bit 15
ID20 to ID13:
ID bits 20 to 13
(BYTE1)
bit 0 to bit 7
ID12 to ID5:
ID bits 28 to 21
(BYTE2)
Function
These bits set the acceptance code or transmit message ID to be collated with
the received message ID.
Standard frame format (IDER:IDEx = 0):
11 bits from ID28 to ID18 are used.
• The old messages left in the receive shift register are stored in ID17 to
ID0. This will not affect the operation.
• All received message IDs are stored even if specific bits are masked.
Extended frame format (IDER:IDEx = 1):
29 bits from ID28 to ID0 are used.
Note:
• When using the standard frame format (IDER:IDEx = 0), the bits from
ID28 to ID22 cannot be all set to 1.
• When setting the ID register (IDR), perform writing by words. Writing by
bytes is disabled.
• The ID register (IDR) should be set after disabling the message buffer (x)
to be set (BVALR:BVALx = 0). Setting the ID register (IDR) with the
message buffer (x) enabled may store a message unnecessary received.
bit 11 to bit 15
ID4 to ID 0:
ID bits 4 to 0
(BYTE3)
Note:
To invalidate the message buffer (by setting the BVALR:BVAL bit to 0) while CAN Controller is
participating in CAN communication (the read value of the CSR:HALT bit is 0 and CAN Controller is
ready to receive or transmit messages), follow the cautions in Section 16.6 "Precautions when Using
CAN Controller".
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
● Setting example of ID register (IDR)
Table 16.3-23 gives a setting example of the ID register (IDR) in the standard and extended frame formats.
Table 16.3-23 Example of ID Setting in Standard and Extended Frame Formats
Standard Frame Format
ID (Dec)
ID (Hex) BYTE0
1
1
00
2
2
00
3
3
00
4
4
00
5
5
00
6
6
00
7
7
00
8
8
01
9
9
01
A
10
01
BYTE1
20
40
60
80
A0
C0
E0
00
20
40
ID (Dec)
1
2
3
4
5
6
7
8
9
10
Extended Frame Format
ID (Hex) BYTE0 BYTE1
1
00
00
2
00
00
3
00
00
4
00
00
5
00
00
6
00
00
7
00
00
8
00
00
9
00
00
A
00
00
BYTE2
00
00
00
00
00
00
00
00
00
00
BYTE3
08
10
18
20
28
30
38
40
48
50
30
31
32
1E
1F
20
03
03
04
C0
E0
00
30
31
32
1E
1F
20
00
00
00
00
00
00
00
00
01
F0
F8
00
100
101
64
65
0C
0C
80
A0
100
101
64
65
00
00
00
00
03
03
20
28
200
C8
19
00
200
C8
00
00
06
40
2043
2044
2045
2046
2047
7FB
7FC
7FD
7FE
7FF
FF
FF
FF
FF
FF
60
80
A0
C0
E0
2043
2044
2045
2046
2047
7FB
7FC
7FD
7FE
7FF
00
00
00
00
00
00
00
00
00
00
3F
3F
3F
3F
3F
D8
E0
E8
F0
F8
8190
8191
8192
1FFE
1FFF
2000
00
00
00
00
00
01
FF
FF
00
F0
F8
00
536870905
536870906
536870907
536870908
536870909
536870910
536870911
1FFFFFF9
1FFFFFFA
1FFFFFFB
1FFFFFFC
1FFFFFFD
1FFFFFFE
1FFFFFFF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FC
FD
FD
FE
FE
FF
FF
80
00
80
00
80
00
80
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
16.3.22
MB90495G Series
DLC Register (DLCR)
The DLC register (DLCR) sets the data length of the message to be transmitted or
received.
■ DLC Register (DLCR)
Figure 16.3-29 DLC Register (DLCR)
bit 7
bit 6
⎯
⎯
bit 5
bit 4
⎯
⎯
bit 3
bit 2
bit 1
bit 0
Reset value
DLC3
DLC2
DLC1
DLC0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W : Read/Write
X
: Undefined
⎯ : Unused
Table 16.3-24 Functions of DLC Register (DLCR)
Bit Name
bit 0 to bit 3
564
Function
DLC3 to DLC0:
Data length setting bits
These bits set the data length (byte count) of the message to be transmitted or
received.
When data frame transmitted: The data length (byte count) of the
transmit message is set.
When remote frame transmitted: The data length (byte count) of the
request message is set.
When data frame received:
The data length (byte count) of the
received message is stored.
When remote frame received:
The data length (byte count) of the
request message is stored.
Notes:
• The data length should be set within the range of 0 to 8 bytes.
• When setting the DLC register (DLCR), write by words. Writing by bytes
is disabled.
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CHAPTER 16 CAN CONTROLLER
16.3 Configuration of CAN Controller
MB90495G Series
16.3.23
Data Register (DTR)
The data register (DTR) sets the messages at transmitting or receiving a data frame. The
data length can be set from 0 to 8 bytes.
■ Data Register (DTR)
Figure 16.3-30 Data Register (DTR)
BYTE0
bit 7
6
5
4
3
2
1
0
Reset value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
14
13
12
11
10
9
8
Reset value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
to
BYTE7
X
: Undefined
R/W : Read/Write
Table 16.3-25 Functions of Data Register (DTR)
Bit Name
bit 0 to bit 15
CM44-10114-7E
D7 to D0 (BYTE7 to
BYTE0):
Data bits 7 to 0
Function
• The data register (DTRx) is used only for transmitting or receiving a data
frame, and is not used for a remote frame.
• The transmit message is set up to 8 bytes. The message is transmitted on
an MSB-first basis starting with the small message buffer number
(BYTE0 to BYTE7).
• The received message is stored on an MSB-first basis starting with the
small message buffer number (BYTE0 to BYTE7).
• If the received message is less than 8 bytes, undefined data is stored in the
rest of the bytes of the data register (DTRx). However this does not affect
the operation.
Note:
When setting the data register (DTR), write by words. Writing by bytes is
disabled.
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CHAPTER 16 CAN CONTROLLER
16.4 Interrupts of CAN Controller
16.4
MB90495G Series
Interrupts of CAN Controller
The CAN controller has a transmit complete interrupt, receive complete interrupt and
node state transition interrupt, and can generate interrupts when;
• The transmission complete bit (TCR:TCx) is set.
• The reception complete bit (RCR:RCx) is set.
• The node status transition flag (CSR:NT) is set.
■ Interrupts of CAN Controller
Table 16.4-1 shows the interrupt control bits and interrupt factors of the CAN controller.
Table 16.4-1 Interrupt Control Bits and Interrupt Factors of CAN Controller
Transmit/
Receive
Interrupt Flag Bit
Interrupt Factor
Interrupt Enable Bit
Clearing of Interrupt
Request Flag
Transmit
Transmission complete bit
TCR:TCx=1
Message transmitting
complete
Transmission complete
interrupt enable bit
TIER:TIEx = 1
Setting transmission
request bit
(TREQR:TREQx = 1)
Writing 0 to
transmission complete
bit (TCR:TCx)
Receive
Reception complete bit
RCR:RCx=1
Message receiving
complete
Reception complete
interrupt enable bit
RIER:RIEx=1
Writing 0 to reception
complete bit
(RCR:RCx)
Transmit
Node status transition flag
CSR:NT=1
Node status transition
Node status transition
interrupt enable bit
CSR:NIE=1
Writing 0 to node status
transition flag
(CSR:NT)
● Transmission complete interrupt
When message transmitting is completed, 1 is set to the TCx bit in the transmission complete register
(TCR). When a transmission complete interrupt is enabled (TIER:TIEx = 1) and when TCx = 1, a
transmission complete interrupt is generated. When a transmission request to the message buffer is set
(TREQR:TREQx = 1), the TCx bit in the transmission complete register (TCR) is automatically cleared to
0. When 0 is written to the TCx bit in the transmission complete register (TCR) after the completion of
message transmitting (TCR:TCx = 1), the TCx bit is cleared.
● Reception complete interrupt
When message receiving is completed, 1 is set to the RCx bit in the receive complete register (RCR). When
a reception complete interrupt is enabled (RIER:RIEx = 1) and when RCx = 1, a reception complete
interrupt is generated. When 0 is written to the RCx bit in the reception complete register (RCR) after the
completion of message receiving (RCR:RCx = 1), the RCx bit is cleared.
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CHAPTER 16 CAN CONTROLLER
16.4 Interrupts of CAN Controller
MB90495G Series
● Node status transition interrupt
When the node status of the CAN controller changes, 1 is set to the NT bit in the control status register
(CSR). If a node status transition interrupt is enabled (CSR:NIE = 1) when NT = 1, a node status transition
interrupt is generated. When 0 is written to the NT bit in the control status register (CSR) after the
completion of message receiving (RCR:RCx = 1), the NT bit is cleared.
■ Registers and Vector Tables Related to Interrupt of CAN Controller
See "3.5 Interrupt" for details of the interrupts.
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CHAPTER 16 CAN CONTROLLER
16.5 Explanation of Operation of CAN Controller
16.5
MB90495G Series
Explanation of Operation of CAN Controller
This section explains the procedures for transmitting and receiving messages and the
setting of bit timing, frame format, ID and acceptance filter.
■ Explanation of Operation of CAN Controller
The following sections provide more details of the operation of CAN controller.
• Transmission of message (See Section "16.5.1 Transmission")
• Reception of message (See Section "16.5.2 Reception")
• Procedures for transmission/reception of message (See Section "16.5.3 Procedures for Transmitting and
Receiving")
• Reception of multiple message (See Section "16.5.4 Setting Multiple Message Receiving")
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CHAPTER 16 CAN CONTROLLER
16.5 Explanation of Operation of CAN Controller
MB90495G Series
16.5.1
Transmission
Figure 16.5-1 shows a transmission flowchart.
■ Transmission
Figure 16.5-1 Transmission Flowchart
Set transmission request register
(TREQR : TREQx = 1)
Transmission complete register is cleared
(TCR : TCx = 0)
NO : 0
Transmission request set?
(TREQR : TREQx)
YES : 1
NO : 0
Remote frame receiving wait?
(RFWTR : RFWTx)
YES : 1
Remote frame received?
(RRTRR : RRTRx)
NO : 0
YES : 1
If there remains message buffer meeting
transmission conditions, the lowestnumbered message buffer is selected.
NO
Is bus idle state?
YES
TRTRx = 0
How is frame setting?
(TRTRR : TRTRx)
A data frame is transmitted
TRTRx = 1
A remote frame is transmitted
Is transmission successful?
NO
YES
Transmission cancelled?
(TCANR : TCANx)
Transmission request register is cleared (TREQR : TREQx = 0)
Reception RTR register is cleared (RRTRR : RRTRx = 0)
Transmission complete register is set (TCR : TCx = 1)
NO: 0
YES: 1
Transmisssion register is cleared
(TREQR : TREQx = 0)
Transmission
complete interrupt enabled?
(TIER : TIEx = 1)
NO : 0
YES : 1
Transmission complete interrupt
request is output
Transmission is completed
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CHAPTER 16 CAN CONTROLLER
16.5 Explanation of Operation of CAN Controller
MB90495G Series
● Starting transmitting
Setting of transmission request
To start transmitting, set the TREQx bit in the transmission request register to 1 which is corresponding
to the message buffer (x) that transmits the message. When the TREQx bit is set, the transmission
complete register is cleared (TCR:TCx = 0).
Presence or absence of remote frame receive wait
If the RFWTx bit in the remote frame receive wait register is set, transmitting is started after a remote
frame is received (RRTRR:RRTRx = 1).
If the remote frame receive wait register does not wait for receiving of a remote frame
(RFWTR:RFWTx = 0), transmitting is started immediately after the transmission request bit is set
(TREQR:TREQx = 1).
● Performing transmitting
Transmission request set in more than one message buffer
When a transmission request is set in more than one message buffer (TREQR:TREQx = 1), transmitting
is performed starting with the small-numbered message buffer (x = 7 to 0).
Transmitting to CAN bus
Transmitting message to the CAN bus from the transmit output pin (TX) is started when the CAN bus is
idle.
Arbitration
Arbitration is performed when a message buffer conflicts with transmitting from other CAN controllers
on the CAN bus. If arbitration fails or an error occurs during transmitting, retransmitting is performed
automatically until it succeeds after waiting until the bus goes idle again.
Selection of frame format
When 0 is set to the TRTRx bit in the transmit RTR register, a data frame is transmitted. When 1 is set
to the bit, a remote frame is transmitted.
● Canceling transmit request
Cancellation by transmission cancel register (TCANR)
During transmitting message, the transmission request set in the message buffer that is not transmitted
(held) can be cancelled by setting 1 in the transmission cancel register (TCANR).
When the transmission request is completely cancelled (TCANR:TCANx = 1), the transmission request
register is cleared (TREQx = 1).
Cancellation by receiving message
The message buffer can receive the message even during requesting a transmitting. However, the
transmission request is cancelled under the following conditions:
Request to transmit data frame:
When a data frame is received, the transmission request is cancelled. When a remote frame is
received, the transmission request is not cancelled.
Request to transmit remote frame:
The transmission request is cancelled even if either a data frame or remote frame is received.
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CHAPTER 16 CAN CONTROLLER
16.5 Explanation of Operation of CAN Controller
MB90495G Series
● Completing transmitting
Success of transmitting
When transmitting is terminated normally, the TCx bit in the transmission complete register is set. The
transmission request register and receive RTR register (TREQR:TREQx = 0, RRTRR:RRTRx = 0) are
cleared.
Generation of transmission interrupt
When the TIEx bit in the transmission complete interrupt enable register is set, an interrupt request is
generated when transmitting is completed (TCR:TCx = 1).
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CHAPTER 16 CAN CONTROLLER
16.5 Explanation of Operation of CAN Controller
16.5.2
MB90495G Series
Reception
Figure 16.5-2 shows a reception flowchart.
■ Reception
Figure 16.5-2 Reception Flowchart
Start-of-frame (SOF) of data frame or
remote frame is detected
Is any message buffer (x)
passing through the acceptance
filter found?
NO
YES
NO
Is reception successful?
YES
Determine message buffer (x) where
receive messages to be stored.
Received message is stored
in the message buffer (x).
Reception complete
register set? (RCR : RCx)
Reception overrun generation
(ROVRR : ROVRx = 1)
NO : 0
Data frame
YES : 1
Receiveing message?
Remote frame
Set reception RTR register
(RRTRR : RRTRx = 1)
Clear reception RTR register
(RRTRR : RRTRx = 0)
TRTRx = 1
Transmission request
of remote frame?
(TRTRR : TRTRx)
Transmission request register is cleared
(TREQR : TREQx = 0)
TRTRx = 0
Setting of reception complete register
(RCR : RCx = 1)
Reception
complete interrupt enabled?
(RIER : RIEx = 1)
YES : 1
Reception complete interrupt request is output
NO : 0
Transmission is completed
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CHAPTER 16 CAN CONTROLLER
16.5 Explanation of Operation of CAN Controller
MB90495G Series
● Starting receiving
Receiving is started when the start-of-frame (SOF) of a data frame or remote frame is detected on the CAN
bus.
● Acceptance filter
The received message in the standard frame format is compared with the message buffer (x) set in the
standard frame format (IDER:IDEx = 0). The received message in the extended frame format is compared
with the message buffer (x) set in the extended frame format (IDER:IDEx = 1).
Passing through acceptance filter
If all bits set to "compare" in the acceptance mask are matched after comparison between the received
message ID and acceptance code (IDR:IDx), the received message passes the acceptance filter in the
message buffer (x).
● Storing received message
If receiving message is successful, the received message is stored in the message buffer (x) that has the ID
that had passed the acceptance filter.
Data frame received
The received message is stored in the ID register (IDR) and DLC register (DLCR), data register (DTR).
If the received message is less than 8 bytes, undefined data is stored in the rest of the bytes in the data
register (DTR).
Remote frame received
The received message is stored in the ID register (IDR) and DLC register (DLCR). The data register
(DTR) remains unchanged.
More than one message buffer
If there is more than one message buffer with the ID that had passed the acceptance filter, the message
buffer (x) where the received message is stored is determined under the following conditions:
• Higher priority is given to the message buffer with a smaller number (x = 0 to 7). The priority of
message buffer 0 is the highest and 7 is the lowest.
• The received message is stored in preference to the message buffer that has not been completed
receiving (RCR:RCx = 0).
• If the bit in the acceptance mask select register is set to "full-bit comparison" (AMSx.1 = 0, 0 = 00B),
the received message is stored in the corresponding message buffer (x), regardless of the setting value of
the reception complete register (RCR:RCx).
• If there is more than one message buffer that has not been completed receiving, or if there is more than
one message buffer with the AMSx.1 and AMSx.0 bits in the acceptance mask select register set to 00B
(full-bit comparison), the received message is stored in the message buffer with the smallest number (x).
• If there is no message buffer that satisfies the above conditions, the received message is stored in the
message buffer with the lowest number (x).
• The message buffers should be arranged in order of ascending number (x) as follows;
- Smallest number (x): Acceptance mask set to "full-bit comparison"
- Middle number (x): Acceptance mask registers 0 and 1 used
- Largest number (x): Acceptance mask set to "full-bit masking"
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CHAPTER 16 CAN CONTROLLER
16.5 Explanation of Operation of CAN Controller
MB90495G Series
● Setting of acceptance mask select register
Table 16.5-1 Setting of Acceptance Mask Select Register
AMSx. 1
AMSx. 0
Acceptance Mask (x = 7 to 0)
0
0
Full-bit comparison is performed.
0
1
Full-bit masking is performed.
1
0
Acceptance mask register 0 (AMR0) is used.
1
1
Acceptance mask register 1 (AMR1) is used.
Figure 16.5-3 Flowchart of Determining Message Buffer that Stores Received Message
Start
Message is not received (RCR : RCx = 0),
or any message buffer set to "full-bit comparison"
(AMSR : AMSx.1 = 0, AMSx.0 = 0)?
No
Yes
Select the smallest-numbered message
buffer (x) from message buffers
corresponding to the above.
Select the smallest-numbered
message buffer (x).
End
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CHAPTER 16 CAN CONTROLLER
16.5 Explanation of Operation of CAN Controller
MB90495G Series
● Receive overrun
When another received message is stored in the message buffer that has completed receiving (RCR:RCx =
1), a receive overrun occurs. When a receive overrun occurs, 1 is set to the ROVRx bit in the receive
overrun register corresponding to the number of the message buffer (x) where the receive overrun occurs.
● Processing for reception of data frame and remote frame
Processing for reception of data frame
• The reception RTR register is cleared (RRTRR:RRTRx = 0).
• The transmission request register is cleared (TREQR:TREQx = 0) immediately before the received
message is stored. A transmission request to the message buffer (x) that does not perform transmitting is
cancelled.
Note:
Either the request to transmit a data frame or a remote frame is cancelled.
Processing for reception of remote frame
• The reception RTR register is set (RRTRR:RRTRx = 1).
• If the transmission RTR register is set (TRTRR:TRTRx = 1), the transmission request register is cleared
(TREQx = 0). The request to transmit a remote frame to the message buffer (x) that does not perform
transmitting is cancelled.
Note:
The request to transmit a data frame is not cancelled.
For details about how to cancel a transmit request, see "Canceling transmit request" in Section 16.5.1
"Transmission"
● Completing receiving
When the received message is stored, the reception complete register is set (RCR:RCx = 1). If the reception
complete interrupt enable register is set (RIER:RIEx = 1), an interrupt is generated when receiving is
completed (RCR:RCx = 1).
Note:
CM44-10114-7E
The CAN controller cannot receive any message transmitted by itself.
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CHAPTER 16 CAN CONTROLLER
16.5 Explanation of Operation of CAN Controller
16.5.3
MB90495G Series
Procedures for Transmitting and Receiving
The section explains the procedure for transmission/reception of massage.
■ Presetting
● Setting of bit timing
• Set the bit timing register (BTR) after halting the bus operation (CSR:HALT = 1).
● Setting of frame format
• Set the frame format used in the message buffer (x). When using the standard frame format, set the
IDEx bit in the IDE register (IDER) to 0. When using the extended frame format, set the IDEx bit to 1.
● Setting of ID
• Set the ID of the message buffer (x) to the ID28 to ID0 bits in the ID register (IDR). In the standard
frame format, it does not have to set the ID17 to ID0 bits. The ID of the message buffer (x) is used as
the transmit message ID at transmitting and as the acceptance code at receiving.
• Set the ID after disabling the message buffer (x) (BVALR:BVALx = 0). Setting the ID with the message
buffer (x) enabled may store a message unnecessary received.
● Setting of acceptance filter
• The acceptance filter used in the message buffer (x) is set by a combination of the acceptance code and
acceptance mask. Set the acceptance filter after disabling the message buffer (x) (BVALR:BVALx = 0).
Setting the acceptance filter with the message buffer (x) enabled may store a message unnecessary
received.
• The acceptance filter used for each message buffer (x) is selected by the acceptance mask select register
(AMSR). When using the acceptance mask registers (AMR0 and AMR1), set the acceptance mask
register (AMR0.1), too.
• Set the acceptance mask so that a transmission request will not be cancelled by storing a message
unnecessary received.
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CHAPTER 16 CAN CONTROLLER
16.5 Explanation of Operation of CAN Controller
MB90495G Series
■ Procedure for Transmitting Message Buffer (x)
Figure 16.5-4 shows a procedure for the transmit setting.
Figure 16.5-4 Flowchart of Procedure for Transmit Setting
Start
Set
Set
Set
Set
Bit timing register (BTR)
IDE register (IDER)
ID register (IDR)
Acceptance mask select register (AMSR)
Acceptance mask register (AMR0, 1)
bit timing
frame format
ID
acceptance filter
Select message buffer to be used
Message buffer enable register (BVALR)
Set transmission complete interrupt
Transmission complete interrupt enable register (TIER)
Data frame
Remote frame
Select frame type
Set frame type
Reception RTR register (TRTRx = 1)
Set frame type
Transmission RTR register (TRTRx = 0)
Set request data length
DLC register (DLCR)
Set of transmission data
length DLC register (DLCR)
Store transmission data in data register
Data register (DTR)
Yes
Remote frame
receiving wait
No
Remote frame receiving wait
RFWTx = 0
Remote frame receiving wait
RFWTx = 1
Cancel bus halt
HALT = 1
Message transmission
Set transmission request of data frame
Data frame transmission (TREQR)
Remote frame receiving wait
Communication error
N:0
N
Is transmission successful?
TCx
Transmission cancel?
Y:1
Y
Cancellation of transmission request
Transmission cancel register (TCANR)
TREQx
1
0
1
TCx
0
Transmission is completed
Transmission cancel
End
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CHAPTER 16 CAN CONTROLLER
16.5 Explanation of Operation of CAN Controller
MB90495G Series
● Procedure for transmission message buffer (x)
After completion of presetting, set the message buffer (x) enabled (BVALR:BVALx =1) by message buffer
enable register.
● Setting transmit data length code
• Set the transmit data length code (byte count) to the DLC3 to DLC0 bits in the DLC register (DLCR).
• When transmitting a data frame (TRTRR:TRTRx = 0), set the data length of the transmit message.
• When transmitting a remote frame (TRTRR:TRTRx = 1), set the data length (byte count) of the message
to be requested.
Note:
Setting other than "0000B" to "1000B" (0 to 8 bytes) is prohibited.
● Setting transmit data (only for transmission of data frame)
When transmitting a data frame (TRTRR:TRTRx = 0), set the data of byte count to be transmitted in the
data register (DTR).
Note:
Rewrite transmit data after setting the TREQx bit in the transmit request register to 0. There is no need to
set the bit disabled in the message buffer enable register (BVALR:BVALx = 0). When the bit is set to
disabled, no remote frame can be received.
● Setting transmission RTR register
• When transmitting a data frame, set the TRTRx bit in the transmission RTR register to 0.
• When transmitting a remote frame, set the TRTRx bit in the transmission RTR register to 1.
● Setting conditions for starting transmitting (only in transmitting data frame)
• When setting the request to transmit a data frame (TREQR:TREQx = 1 and TRTRR:TRTRx = 0) and
starting transmitting immediately, set the RFWTx bit in the remote frame wait register to 0.
• When setting the request to transmit a data frame (TREQR:TREQx = 1 and TRTRR:TRTRx = 0) and
starting transmitting after waiting until a remote frame is received (RRTRR:RRTRx = 1), set the
RFWTx bit in the remote frame wait register to 1.
Note:
When the RFWTx bit in the remote frame wait register is set to 1, no remote frame can be transmitted.
● Setting transmission complete interrupt
• When enabling an interrupt when transmitting is completed (TCR:TCx = 1), set the TIEx bit in the
transmit complete enable register to 1.
• When disabling an interrupt when transmitting is completed (TCR:TCx = 1), set the TIEx bit in the
transmission complete enable register to 0.
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CHAPTER 16 CAN CONTROLLER
16.5 Explanation of Operation of CAN Controller
MB90495G Series
● Canceling bus halt
After the completion of setting bit timing and transmitting, write 0 to the HALT bit in the control status
register (CSR:HALT) to cancel the bus halt.
● Setting transmission request
To set a transmission request, set the TREQx bit in the transmission request register to 1.
● Canceling transmission request
• To cancel the transmission request held in the message buffer (x), write 1 to the TCANx bit in the
transmission cancel register.
• Check the TREQx bit in the transmission request register (TREQR). When the TREQx bit is 0,
transmission cancel is terminated or transmitting is completed. After that, check the TCx bit in the
transmission complete register (TCR). If the TCx bit is 0, transmission cancel is terminated and if the
TCx bit is 1, transmitting is completed.
● Processing when transmitting completed
• When transmitting is successful, 1 is set to the TCx bit in the transmit complete register (TCR).
• When a transmission complete interrupt is enabled (TIER:TIEx = 1), an interrupt is generated.
• After checking the completion of transmitting, write 0 to the TCx bit in the transmission complete
register (TCR) to clear the transmission complete register (TCR). When the transmission complete
register (TCR) is cleared, the transmission complete interrupt is cancelled.
• When the message is received or stored, the held transmission requests are cancelled as follows:
- When a data frame is received, the request to transmit a data frame is cancelled.
- When a data frame is received, the request to transmit a remote frame is cancelled.
- When a remote frame is received, the request to transmit a remote frame is cancelled.
When a remote frame is received or stored, the request to transmit a data frame is not cancelled but the data
in the ID register and DLC register are rewritten to the data of the received remote frame. Therefore, the
data in the ID register and DLC register for the data frame to be transmitted are replaced by data in the
received remote frame.
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CHAPTER 16 CAN CONTROLLER
16.5 Explanation of Operation of CAN Controller
MB90495G Series
■ Procedure for Receiving Message Buffer (x)
Figure 16.5-5 shows the procedure for the receiving setting.
Figure 16.5-5 Flowchart of Procedure for Receive Setting
Start
Bit timing register (BTR)
IDE register (IDER)
ID register (IDR)
Acceptance mask select register (AMSR)
Acceptance mask register (AMR0, 1)
Set bit timing
Set frame format
Set ID
Set acceptance filter
Select message buffer to be used
Message buffer enable register (BVALR)
Set reception complete interrupt
Reception complete interrupt enable register (RIER)
Cancel bus halt?
HALT = 1
N
Message received?
RCx = 1 ?
Y
Received byte count reading
Message storing
(storing by reception complete interrupt)
Reception overrun bit clear
ROVRx = 0
Received message reading
Reception overrun?
ROVRx = 0?
N
Y
Reception complete bit clear
RCx=0
End
● Procedure for receiving message buffer (x)
After presetting, perform the following setting:
● Setting reception complete interrupt
• To generate a reception complete interrupt, set the RIEx bit in the reception complete interrupt enable
register (RIER) to 1.
• To disable a reception complete interrupt (RCR:RCx = 1), set the RIEx bit to 0.
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CHAPTER 16 CAN CONTROLLER
16.5 Explanation of Operation of CAN Controller
MB90495G Series
● Starting receiving
To start receiving after the completion of setting, set the BVALx bit in the message buffer enable register
(BVALR) to 1 and enable the message buffer (x).
● Canceling bus halt
After the completion of setting bit timing and transmitting, write 0 to the HALT bit in the control status
register (CSR:HALT) to cancel the bus halt.
● Processing when receiving completed
• If reception is successful after passing through the acceptance filter, the received message is stored in
the message buffer (x), 1 is set to the RCx of the reception complete register (RCR). For data frame
reception, RRTRx bit of the remote request receive register (RRTRR) is cleared to 0. For remote frame
reception, 1 is set to the RRTRx bit.
• If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is 1), an
interrupt is generated.
• Process the received message after checking the completion of receiving (RCR:RCx = 1).
• Check the ROVRx bit in the receive overrun register (ROVRR) after the completion of processing the
received message.
- If the ROVRx bit is set to 0, the received message is enabled. When 0 is written to the RCx bit (a
reception complete interrupt is also cancelled), receiving is terminated.
- If the ROVRx bit is set to 1, a receive overrun occurs and the new message may overwrite the
received message. When a receive overrun occurs, write 0 to the ROVRx bit and then process the
received message again.
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CHAPTER 16 CAN CONTROLLER
16.5 Explanation of Operation of CAN Controller
MB90495G Series
Figure 16.5-6 shows an example of reception interrupt processing.
Figure 16.5-6 Example of Reception Interrupt Processing
Interrupt generation
with RCx = 1
Received message
reading
A : = ROVRx
ROVRx : = 0
A = 0?
No
Yes
RCx : 0
Completion
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16.5.4
CHAPTER 16 CAN CONTROLLER
16.5 Explanation of Operation of CAN Controller
Setting Multiple Message Receiving
When there is insufficient time to receive messages such as frequently received
messages or messages with different IDs, more than one message buffer can be
combined to a multiple message buffer to give the CPU sufficient time to process
received messages.
To configure multiple message buffers, perform the same setting of acceptance filter of
the message buffers to be combined.
■ Setting Configuration of Multiple Message Buffer
When four messages in the standard frame format are received with doing the acceptance filter of message
buffers 5 and 6, 7 on the same settings, the multiple message buffer operates as shown in the figure.
Note:
CM44-10114-7E
When the acceptance mask select register is set to "full-bit comparison" (AMSR:AMSx.1, AMSx.0 =
00B), do not set the same acceptance code. When the register is set to "full-bit comparison", the messages
are always stored in the message buffer with the smaller number, so the message buffers cannot be
formed into a multiple message buffer.
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16.5 Explanation of Operation of CAN Controller
MB90495G Series
Figure 16.5-7 Example of Operation of Multiple Message Buffer
Initial setting
AMSR
AMS7
10
AMS6
10
AMS5
10
. .
Acceptance mask
register selection
AMR0
AM28 to AM18
0000 1111 111
Message buffer 5
ID28 to ID18
0101 0000 000
Message buffer 6
0101 0000 000
Message buffer 7
0101 0000 000
IDE7 IDE6 IDE5
. . .
0
0
0
IDER
IDE
0 . .
0 . .
0
RCR
ROVRR
. .
RC7
0
RC6
0
0
ROVR7
0
RC5
. . .
0
. . .
0
6
5
Mask
Message receiving → stored in message buffer 5
Received message
ID28 to ID18
0101 1111 000
IDE
0 . .
Message buffer 5
0101 1111 000
0
. .
RCR
0
0
1
. . .
Message buffer 6
0101 0000 000
0
. .
ROVRR
0
0
0
. . .
0
. .
Message buffer 7
0101 0000 000
Message receiving → stored in message buffer 6
Received message
ID28 to ID18
0101 1111 001
IDE
0 . .
Message buffer 5
0101 1111 000
0
. .
RCR
0
1
1
. . .
Message buffer 6
0101 1111 001
0
. .
ROVRR
0
0
0
. . .
0
. .
Message buffer 7
0101 0000 000
Message receiving → stored in message buffer 7
Received message
Message buffer 5
ID28 to ID18
0101 1111 010
0101 1111 000
IDE
0 . .
0
. .
RCR
1
1
1
. . .
ROVRR
0
0
0
. . .
Message buffer 6
0101 1111 001
0
. .
Message buffer 7
0101 1111 010
0
. .
Message receiving → reception overrun (ROVR5 =1) generated, stored in message buffer 5
Received message
Message buffer 5
584
ID28 to ID18
0101 1111 011
0101 1111 011
IDE
0 . .
0
. .
RCR
1
1
1
. . .
ROVRR
0
0
1
. . .
Message buffer 6
0101 1111 001
0
. .
Message buffer 7
0101 1111 010
0
. .
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CHAPTER 16 CAN CONTROLLER
16.6 Precautions when Using CAN Controller
MB90495G Series
16.6
Precautions when Using CAN Controller
Use of the CAN Controller requires the following cautions.
■ Caution for Disabling Message Buffers by BVAL bits
The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set disabled
while CAN Controller is participating in CAN communication (read value of HALT bit is 0 and CAN
Controller is ready to receive or transmit messages). This section shows the work around of this
malfunction.
● Condition
When following two conditions occur at the same time, CAN Controller will not perform to receive or
transmit messages normally.
• CAN Controller is participating in the CAN communication. (i.e. The read value of HALT bit is 0 and
CAN Controller is ready to receive or transmit messages)
• Message buffers are read or written when the message buffers are disabled by BVAL bits.
● Work around
Operation for re-configuring receiving message buffers
While CAN Controller is participating in CAN communication (the read value of HALT bit is 0 and
CAN Controller is ready to receive or transmit messages), it is necessary to following one from the two
operations described below to re-configure message buffers by ID, AMS and AMR0/1 register-settings.
• Use of HALT bit
- Write 1 to HALT bit and read it back for checking the result is 1. Then change the settings for ID/
AMS/AMR0/1 registers.
• No Use of Message Buffer 0
- Don't use the message buffer 0. In other words, disable message buffer (BVAL0=0), prohibit receive
interrupt (RIE0=0) and do not request transmission (TREQ0=0).
Operation for processing received message
Don't use the receiving prohibition by BVAL bit to avoid over-written of next message. Use the ROVR
bit for checking if over-write has been performed. For details, refer to section 16.3.16 "Reception
Overrun Register (ROVRR)" and 16.5.3 "Procedures for Transmitting and Receiving"
Operation for suppressing transmission request
Don't use BVAL bit for suppressing transmission request, use TCAN bit instead of it.
Operation for composing transmission message
For composing a transmission message, it is necessary to disable the message buffer by BVAL bit to
change contents of ID and IDE registers. In this case, BVAL bit should reset (BVAL=0) after checking
if TREQ bit is 0 or after completion of the previous message transmission (TC=1).
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CHAPTER 16 CAN CONTROLLER
16.7 Program Example of CAN Controller
16.7
MB90495G Series
Program Example of CAN Controller
This section shows the program example of CAN controller.
■ Program Example of CAN Transmission and Reception
● Processing specifications
• Set buffer 5 of CAN to data frame transmit mode and buffer 0 to data frame receive mode.
• Setting of frame format: Standard frame format
• Setting of ID: Buffer 0 ID = 0, Buffer 5 ID = 5
• Baud rate: 100 Kbps (machine clock = 16 MHz)
• Acceptance mask selection: full-bit comparison
• After entering the bus mode (HALT = 0), data A0A0H is transmitted.
• A transmission request is made within the transmission complete interrupt routine to transmit the same
data (When TREQx is set to start sending, the transmission complete interrupt bit is cleared).
• The reception interrupt bit is cleared within the reception interrupt routine.
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CHAPTER 16 CAN CONTROLLER
16.7 Program Example of CAN Controller
● Coding example
:
:
:
;//Setting of data format (CAN initialization)
MOVW BTR,#05CC7H
; Setting baud rate 100 Kbps
; (0: Standard, 1:Expanded)
MOVW IDR51,#0A000H
; Setting of data frame 5 ID (ID = 5)
MOVW IDR501,#2000H
; Setting of data frame 0 ID (ID = 1)
MOVW AMSR,#0000H
; Acceptance mask select register
; (full-bit comparison)
MOVW BVALR,#021H
; Message buffers 5 and 0 enabled
;//Transmit setting
MOVW DLCR5,#02H
; Setting of transmission data length
; (00H: 0-byte length, 08H: 8-byte length)
MOVW RFWTR,#0000H
; Remote frame receive wait register
MOVW TRTRR,#0000H
; Transmission RTR register (0: Data frame
; transmission, 1: Remote frame transmission)
MOVW TIER,#0020H
; Transmission complete interrupt enable register
;//Reception setting
MOVW RIER,#0001H
; Reception complete interrupt enable register
;//Bus operation start
MOV CSR0,#80H
; Control status register (HALT=0)
sthlt
BBS CSR0:0,sthlt
; Wait until HALT=0
;//Transmission data set
MOVW DTR5,#0A0A0H
; Write A0A0H to data register of message buffer 5.
MOVW TREQR,#0020H
; Transmission request register
; (1: Transmission start, 0: Transmission stop)
:
:
:
;//Reception complete interrupt
CANRX
MOVW RCR0,#0000H
; Reception complete register
RETI
;//Transmission complete interrupt
CANTX
MOVW TREQR,#0020H
; Transmission request register
; (1: Transmission start, 0: Transmission stop)
RETI
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CHAPTER 16 CAN CONTROLLER
16.7 Program Example of CAN Controller
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CHAPTER 17
8/16 ADDRESS MATCH
DETECTION FUNCTION
This chapter explains the address match detection
function and its operation.
17.1 Overview of Address Match Detection Function
17.2 Block Diagram of Address Match Detection Function
17.3 Configuration of Address Match Detection Function
17.4 Explanation of Operation of Address Match Detection Function
17.5 Program Example of Address Match Detection Function
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CHAPTER 17 8/16 ADDRESS MATCH DETECTION FUNCTION
17.1 Overview of Address Match Detection Function
17.1
MB90495G Series
Overview of Address Match Detection Function
If the address of the instruction to be processed next to the instruction currently
processed by the program matches the address set in the detect address setting
registers, the address match detection function forcibly replaces the next instruction to
be processed by the program with the INT9 instruction to branch to the interrupt
processing program. Since the address match detection function can use the INT9
interrupt for instruction processing, the program can be corrected by patch processing.
■ Overview of Address Match Detection Function
• The address of the instruction to be processed next to the instruction currently processed by the program
is always held in the address latch through the internal bus. The address match detection function always
compares the value of the address held in the address latch with that of the address set in the detect
address setting registers. When these compared values match, the next instruction to be processed by the
CPU is forcibly replaced by the INT9 instruction, and the interrupt processing program is executed.
• There are two detect address setting registers (PADR0 and PADR1), each of which has an interrupt
enable bit. The generation of an interrupt due to a match between the address held in the address latch
and the address set in the detect address setting registers can be enabled and disabled for each register.
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CHAPTER 17 8/16 ADDRESS MATCH DETECTION FUNCTION
17.2 Block Diagram of Address Match Detection Function
MB90495G Series
17.2
Block Diagram of Address Match Detection Function
The address match detection module consists of the following blocks:
• Address latch
• Address detection control register (PACSR)
• Detect address setting registers
■ Block Diagram of Address Match Detection Function
Figure 17.2-1 shows the block diagram of the address match detection function.
Figure 17.2-1 Block Diagram of the Address Match Detection Function
Internal data bus
PADR0 (24bit)
Detect address setting register 0
PADR1 (24bit)
Comparator
Address latch
INT9 instruction
(INT9 interrupt
generation)
Detect address setting register 1
PACSR
Reserved Reserved Reserved Reserved AD1E Reserved AD0E Reserved
Address detection control register (PACSR)
Reserved: Always set to "0"
● Address latch
The address latch stores the value of the address output to the internal data bus.
● Address detection control register (PACSR)
The address detection control register enables or disables output of an interrupt at an address match.
● Detect address setting registers
The detect address setting registers set the address that is compared with the value of the address latch.
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17.3 Configuration of Address Match Detection Function
17.3
MB90495G Series
Configuration of Address Match Detection Function
This section details the registers used by the address match detection function.
■ List of Registers and Reset Values of Address Match Detection Function
Figure 17.3-1 List of Registers and Reset Values of Address Match Detection Function
bit
Address detection control register (PACSR)
bit
Detect address setting register 0 (PADR0)
: High
bit
Detect address setting register 0 (PADR0)
: Middle
bit
Detect address setting register 0 (PADR0)
: Low
bit
Detect address setting register 1 (PADR1)
: High
bit
Detect address setting register 1 (PADR1)
: Middle
bit
Detect address setting register 1 (PADR1)
: Low
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
×: Undefined
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CHAPTER 17 8/16 ADDRESS MATCH DETECTION FUNCTION
17.3 Configuration of Address Match Detection Function
MB90495G Series
17.3.1
Address Detection Control Register (PACSR)
The address detection control register (PACSR) enables or disables output of an
interrupt at an address match. When an address match is detected when output of an
interrupt at an address match is enabled, the INT9 interrupt is generated.
■ Address Detection Control Register (PACSR)
Figure 17.3-2 Address Detection Control Register (PACSR)
7
6
5
4
3
2
1
0
Reset value
00000000
B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
Reserved bit
Reserved
0
Always set to "0"
bit 1
Address match detection enable bit 0
AD0E
0
Disables address match detection in PADR0
1
Enables address match detection in PADR0
bit 2
Reserved bit
Reserved
0
Always set to "0"
bit 3
Address match detection enable bit 1
AD1E
0
Disables address match detection in PADR1
1
Enables address match detection in PADR1
bit 4
Reserved bit
Reserved
0
Always set to "0"
bit 5
Reserved bit
Reserved
0
Always set to "0"
bit 6
Reserved bit
Reserved
0
Always set to "0"
bit 7
Reserved bit
Reserved
R/W : Read/Write
: Reset value
CM44-10114-7E
0
Always set to "0"
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17.3 Configuration of Address Match Detection Function
MB90495G Series
Table 17.3-1 Functions of Address Detection Control Register (PACSR)
Bit Name
bit 0
reserved: reserved bit
Always set to 0.
bit 1
AD0E:
Address match detection
enable bit 0
The address match detection operation with the detect address setting register
0 (PADR1) is enabled or disabled.
When set to 0: Disables the address match detection operation.
When set to 1: Enables the address match detection operation.
• When the value of detect address setting register 0 (PADR0) matches with
the value of address latch at enabling the address match detect operation
(AD0E = 1), the INT9 instruction is immediately executed.
bit 2
reserved: reserved bit
Always set to 0.
bit 3
AD1E:
Address match detection
enable bit 1
The address match detection operation with the detect address setting register
1 (PADR1) is enabled or disabled.
When set to 0: Disables the address match detection operation.
When set to 1: Enables the address match detection operation.
• When the value of detect address setting registers 1 (PADR1) matches
with the value of address latch at enabling the address match detection
operation (AD0E = 1), the INT9 instruction is immediately executed.
reserved: reserved bit
Always set to 0.
bit 4 to bit 7
594
Function
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CHAPTER 17 8/16 ADDRESS MATCH DETECTION FUNCTION
17.3 Configuration of Address Match Detection Function
MB90495G Series
17.3.2
Detect Address Setting Registers (PADR0 and PADR1)
The value of an address to be detected is set in the detect address setting registers.
When the address of the instruction processed by the program matches the address set
in the detect address setting registers, the next instruction is forcibly replaced by the
INT9 instruction, and the interrupt processing program is executed.
■ Detect Address Setting Registers
Figure 17.3-3 Detect Address Setting Registers (PADR0 and PADR1)
PADR0, PADR1: High
bit 7 bit 6 bit 5
bit 4 bit 3 bit 2 bit 1 bit 0
Reset value
D23 D22
D20 D19 D18
XXXXXXXX B
D21
D17
D16
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
PADR0, PADR1: Middle
D15 D14
D13
D12 D11 D10
D9
D8
Reset value
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PADR0, PADR1: Low
D7
D6
D5
D4
D3
D2
D1
D0
Reset value
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Read/Write
X
: Undefined
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CHAPTER 17 8/16 ADDRESS MATCH DETECTION FUNCTION
17.3 Configuration of Address Match Detection Function
MB90495G Series
■ Functions of Detect Address Setting Registers
• There are two detect address setting registers (PADR0 and PADR1) that consist of a high byte (bank),
middle byte, and low byte, totaling 24 bits.
Table 17.3-2 Address Setting of Detect Address Setting Registers
Register Name
Interrupt Output
Enable
Address Setting
High
Detect address setting
register 0 (PADR0)
Detect address setting
register 1 (PADR1)
PACSR:AD0E
PACSR:AD1E
Set the upper 8 bits of detect address 0
(bank).
Middle
Set the middle 8 bits of detect address 0.
Low
Set the lower 8 bits of detect address 0.
High
Set the upper 8 bits of detect address 1
(bank).
Middle
Set the middle 8 bits of detect address 1.
Low
Set the lower 8 bits of detect address 1.
• In the detect address setting registers (PADR0 and PADR1), starting address (first byte) of instruction to
be replaced by INT9 instruction should be set.
Figure 17.3-4 Setting of Starting Address of Instruction Code to be Replaced by INT9
Set to detect address (High : FFH, Middle : 00H, Low : 1FH)
Notes:
596
Address
Instruction code
FF001C :
FF001F :
FF0022 :
A8 00 00
4A 00 00
4A 80 08
Mnemonic
MOVW
MOVW
MOVW
RW0, #0000
A, #0000
A,#0880
• When an address of other than the first byte is set to the detect address setting register (PADR0 and
PADR1), the instruction code is not replaced by INT9 instruction and a program of an interrupt
processing is not be performed. When the address is set to the second byte or subsequent, the address
set by the instruction code is replaced by "01" (INT9 instruction code) and, which may cause
malfunction.
• The detect address setting registers (PADR0 and PADR1) should be set after disabling the address
match detection (PACSR:AD0E = 0 or AD1E = 0) of corresponding address match control registers.
If the detect address setting registers are changed without disabling the address match detection, the
address match detection function will work immediately after an address match occurs during writing
address, which may cause malfunction.
• The address match detection function can be used only for addresses of the internal ROM area. If
addresses of the external memory area are set, the address match detection function will not work and
the INT9 instruction will not be executed.
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CHAPTER 17 8/16 ADDRESS MATCH DETECTION FUNCTION
17.4 Explanation of Operation of Address Match Detection Function
MB90495G Series
17.4
Explanation of Operation of Address Match Detection
Function
If the addresses of the instructions executed in the program match those set in the
detection address setting registers (PADR0 and PADR1), the address match detection
function will replace the first instruction with the INT9 instruction (01H) to branch to the
interrupt processing program.
■ Operation of Address Match Detection Function
Figure 17.4-1 shows the operation of the address match detection function when the detect addresses are set
and an address match is detected.
Figure 17.4-1 Operation of Address Match Detection Function
Program execution
The instruction address to be
executed by program matches
detect address setting register 0
Address
Instruction code
FF001C :
FF001F :
FF0022 :
A8 00 00
4A 00 00
4A 80 08
Mnemonic
MOVW
MOVW
MOVW
RW0, #0000
A, #0000
A, #0880
Replaced by INT9 instruction (01H)
■ Setting Detect Address
1. Disable the detection address setting register 0 (PADR0) where the detect address is set for address
match detection (PACSR:AD0E = 0).
2. Set the detect address in the detection address setting register 0 (PADR0). Set "FFH" at the higher bits of
the detection address setting register 0 (PADR0), "00H" at the middle bits, and "1FH" at the lower bits.
3. Enable the detect address setting register 0 (PADR0) where the detect address is set for address match
detection (PACSR:AD0E = 1).
■ Program Execution
1. If the address of the instruction to be executed in the program matches the set detect address, the first
instruction code at the matched address is replaced by the INT9 instruction code (01H).
2. INT9 instruction is executed. INT9 interrupt is generated and then interrupt processing program is
executed.
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CHAPTER 17 8/16 ADDRESS MATCH DETECTION FUNCTION
17.4 Explanation of Operation of Address Match Detection Function
17.4.1
MB90495G Series
Example of using Address Match Detection Function
This section gives an example of patch processing for program correction using the
address match detection function.
■ System Configuration and E2PROM Memory Map
● System configuration
Figure 17.4-2 gives an example of the system configuration using the address match detection function.
Figure 17.4-2 Example of System Configuration using Address Match Detection Function
Serial E2PROM
Interface
MCU
F2MC16LX
E2PROM
Storing patch program
Pull up resistor
SIN
Connector (UART)
Storing patch program from the outside
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CHAPTER 17 8/16 ADDRESS MATCH DETECTION FUNCTION
17.4 Explanation of Operation of Address Match Detection Function
MB90495G Series
■ E2PROM Memory Map
Figure 17.4-3 shows the allocation of the patch program and data at storing the patch program in E2PROM.
Figure 17.4-3 Allocation of E2PROM Patch Program and Data
E2PROM
Address
PADR0
PADR1
0000H
Patch program byte count
0001H
Detect address 0 (Low)
0002H
Detect address 0 (Middle)
0003H
Detect address 0 (High)
0004H
Patch program byte count
0005H
Detect address 1 (Low)
0006H
Detect address 1 (Middle)
0007H
Detect address 1 (High)
0010H
Patch program 0
(main body)
0020H
Patch program 1
(main body)
For patch program 0
For patch program 1
● Patch program byte count
The total byte count of the patch program (main body) is stored. If the byte count is "00H", it indicates that
no patch program is provided.
● Detect address (24 bits)
The address where the instruction code is replaced by the INT9 instruction code due to program error is
stored. This address is set in the detection address setting registers (PADR0 and PADR1).
● Patch program (main body)
The program executed by the INT9 interrupt processing when the program address matches the detect
address is stored. Patch program 0 is allocated from any predetermined address. Patch program 1 is
allocated from the address indicating <starting address of patch program 0 + total byte count of patch
program 0>.
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CHAPTER 17 8/16 ADDRESS MATCH DETECTION FUNCTION
17.4 Explanation of Operation of Address Match Detection Function
MB90495G Series
■ Setting and Operating State
● Initialization
• E2PROM data are all cleared to "00H".
● Occurrence of program error
• By using the connector (UART), information about the patch program is transmitted to the MCU
(F2MC-16LX) from the outside according to the allocation of the E2PROM patch program and data.
• The MCU (F2MC-16LX) stores the information received from outside in the E2PROM.
● Reset sequence
• After reset, the MCU (F2MC-16LX) reads the byte count of the E2PROM patch program to check the
presence or absence of the correction program.
• If the byte count of the patch program is not "00H", the higher, middle and lower bits at detect addresses
0 and 1 are read and set in the detection address setting registers 0 and 1 (PADR0 and PADR1). The
patch program (main body) is read according to the byte count of the patch program and written to
RAM in the MCU (F2MC-16LX).
• The patch program (main body) is allocated to the address where the patch program is executed in the
INT9 interrupt processing by the address match detection function.
• Address match detection is enabled (PACSR:AD0E = 1, AD1E = 1)
● INT9 Interrupt processing
• Interrupt processing is performed by the INT9 instruction. The MB90495G series has no interrupt
request flag by address match detection. Therefore, if the stack information in the program counter is
discarded, the detect address cannot be checked. When checking the detect address, check the value of
program counter stacked in the interrupt processing routine.
• The patch program is executed, branching to the normal program.
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CHAPTER 17 8/16 ADDRESS MATCH DETECTION FUNCTION
17.4 Explanation of Operation of Address Match Detection Function
MB90495G Series
■ Operation of Address Match Detection Function at Storing Patch Program in
E2PROM
Figure 17.4-4 shows the operation of the address match detection function at storing the patch
program in E2PROM.
Figure 17.4-4 Operation of Address Match Detection Function at Storing Patch Program in
E2PROM
000000 H
(3)
Patch program
RAM
Detection address setting register
E2PROM
(1)
Detection address setting
(reset sequence)
Serial E2PROM
interface
. Patch program byte count
. Address for address detection
. Patch program
ROM
(2)
(4)
Program error
FFFFFF H
(1) Execution of detection address setting of reset sequence and normal program
(2) Branch to patch program which expanded in RAM with INT9 interrupt processing by address match detection
(3) Patch program execution by branching of INT9 processing
(4) Execution of nomal program which branches from patch program
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17.4 Explanation of Operation of Address Match Detection Function
MB90495G Series
■ Flow of Patch Processing
Figure 17.4-5 shows the flow of patch processing using the address match detection function.
Figure 17.4-5 Flow of Patch Processing
E2PROM
MB90497G
I/O area
000000H
000100H
Register/RAM area
000400H
Patch program
000480H
RAM area
RAM
Stack area
0000 H
Patch program byte count : 80H
0001 H
Detect address (Low) : 00H
0002 H
Detect address (Middle) : 80H
0003 H
Detect address (High) : FFH
0010 H
Patch program
000900H
Detection address setting register
0090 H
FFFFH
FF0000H
FF8000H
ROM
Program error
FF8050H
FFFFFF H
YES
Reset
INT9
Read the 00H
of E2PROM
Branch to patch program
JMP 000400H
Execution of patch program
000400H to 000480H
E2PROM : 0000H
=0
NO
End of patch program
JMP FF8050H
Read detect address
E2PROM : 0001H to 0003H
↓
MCU : Set to PADR0
Read patch program
E2PROM : 0010H to 008FH
↓
MCU : 000400H to 00047FH
Enable address match detection
(PACSR : AD0E = 1)
Execution of normal
program
NO
602
Program address
= PADR0
YES
INT9
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MB90495G Series
17.5
CHAPTER 17 8/16 ADDRESS MATCH DETECTION FUNCTION
17.5 Program Example of Address Match Detection Function
Program Example of Address Match Detection Function
This section gives a program example for the address match detection function.
■ Program Example for Address Match Detection Function
● Processing specifications
If the address of the instruction to be executed by the program matches the address set in the detection
address setting register (PADR0), the INT9 instruction is executed.
● Coding example
PACSR
EQU 00009EH
; Address detection control register
PADRL
EQU
001FF0H
; Detection address setting register 0 (Low)
PADRM
EQU
001FF1H
; Detection address setting register 0 (Middle)
PADRH
EQU
001FF2H
; Detection address setting register 0 (High)
;
;-----Main program--------------------------------------------------------------CODE
CSEG
START:
; Stack pointer (SP), etc.,
; already reset
MOV PADRL,#00H
; Set address detection register 0 (Low)
MOV PADRM,#00H
; Set address detection register 0 (Middle)
MOV PADRH,#00H
; Set address detection register 0 (High)
;
MOV I:PACSR,#00000010B ; Enable address match
:
processing by user
:
LOOP:
:
processing by user
:
BAR LOOP
;-----Interrupt program---------------------------------------------------------WARI:
:
processing by user
:
BETI
; Return from interrupt processing
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG 00FFDCH
DSL WARI
ORG 00FFDCH
; Set reset vector
DSL START
DB
00H
; Set to single-chip mode
VECT
ENDS
END START
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CHAPTER 17 8/16 ADDRESS MATCH DETECTION FUNCTION
17.5 Program Example of Address Match Detection Function
604
FUJITSU SEMICONDUCTOR LIMITED
MB90495G Series
CM44-10114-7E
CHAPTER 18
MIRRORING FUNCTION
SELECT MODULE
This chapter describes the functions and operations of
the ROM mirroring function select module.
18.1 Overview of ROM Mirroring Function Select Module
18.2 ROM Mirroring Function Select Register (ROMM)
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CHAPTER 18 MIRRORING FUNCTION SELECT MODULE
18.1 Overview of ROM Mirroring Function Select Module
18.1
MB90495G Series
Overview of ROM Mirroring Function Select Module
The ROM mirroring function select module provides a setting so that ROM data in the
FF bank can be read by access to the 00 bank.
■ Block Diagram of ROM Mirroring Function Select Module
Figure 18.1-1 Block Diagram of ROM Mirroring Function Select Module
ROM mirroring function select register (ROMM)
Reserved Reserved Reserved Reserved Reserved Reserved Reserved MI
Address
Internal data bus
Address area
00 bank
FF bank
Data
ROM
■ Access to FF Bank by ROM Mirroring Function
Figure 18.1-2 shows the location in memory when ROM mirroring function allows access to the 00 bank to
read ROM data in the FF bank.
Figure 18.1-2 Access to FF Bank by ROM Mirroring Function
004000 H
00 bank
ROM mirror area
00FFFFH
FBFFFF H
FC0000 H
MB90V495G
FE0000 H
FEFFFF H
MB90F498G
FF0000 H
FF4000 H
FF bank
(ROM mirror-target area)
MB90F497G
MB90497G
FFFFFFH
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CHAPTER 18 MIRRORING FUNCTION SELECT MODULE
18.1 Overview of ROM Mirroring Function Select Module
MB90495G Series
■ Memory Space when ROM Mirroring Function Enabled/Disabled
Figure 18.1-3 shows the availability of access to memory space when the ROM mirroring function is
enabled or disabled
Figure 18.1-3 Memory Space when ROM Mirroring Function Enabled/Disabled
000000 H
0000C0 H
000100 H
Address 1
003800 H
004000 H
I/O area
I/O area
RAM area
RAM area
Extend I/O area
Extend I/O area
ROM area
010000 H
Address 2
FFFFFFH
ROM area
ROM area
When ROM mirroring
function enabled
When ROM mirroring
function disabled
Product type MB90V495G MB90F497G
Address 1
Address 2
MB90497G
MB90498G
001900H
00900H
00900H
00900H
FC0000H
FF0000H
FF0000H
FE0000H
■ List of Registers and Reset Values of ROM Mirroring Function Select Module
Figure 18.1-4 List of Registers and Reset Values of ROM Mirroring Function Select Module
bit
15
14
13
12
11
10
9
8
ROM mirroring function select register (ROMM)
×
×
×
×
×
×
×
1
×: Undefined
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CHAPTER 18 MIRRORING FUNCTION SELECT MODULE
18.2 ROM Mirroring Function Select Register (ROMM)
18.2
MB90495G Series
ROM Mirroring Function Select Register (ROMM)
The ROM mirroring function select register (ROMM) enables or disables the ROM
mirroring function. When the ROM mirroring function is enabled, ROM data in the FF
bank can be read by access to the 00 bank.
■ ROM Mirror Function Select Register (ROMM)
Figure 18.2-1 ROM Mirroring Function Select Register (ROMM)
15
14
13
12
11
10
9
8
Reset value
XXXXXXX1B
⎯
⎯
W
X
⎯
:
:
:
:
⎯
⎯
⎯
⎯
⎯
W
bit 8
Write only
Undefined
Unused
Reset value
MI
0
1
ROM mirroring function select bit
ROM mirroring function disabled
ROM mirroring function enabled
Table 18.2-1 Functions of ROM Mirroring Function Select Register (ROMM)
Bit Name
bit 8
Function
MI:
ROM mirroring function
select bit
This bit enables or disables the ROM mirroring function.
When set to 0: Disables ROM mirroring function
When set to 1: Enables ROM mirroring function
• When the ROM mirroring function is enabled (MI = 1), data at ROM
addresses "FF4000H" to "FFFFFFH" can be read by accessing addresses
"004000H" to "00FFFFHH"
bit 9 to bit 15
Unused bits
Read: Value undefined
Write: No effect
Note:
While the ROM area at addresses "004000H" to "00FFFFH" is being used, access to the ROM mirroring
function select register (ROMM) is prohibited.
608
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 19
512 KBIT/1 MBIT
FLASH MEMORY
This chapter describes the function and operation of
512 Kbit/1 Mbit flash memory.
19.1 Overview of 512 Kbit/1 Mbit Flash Memory
19.2 Registers and Sector Configuration of Flash Memory
19.3 Flash Memory Control Status Register (FMCS)
19.4 How to Start Automatic Algorithm of Flash Memory
19.5 Check the Execution State of Automatic Algorithm
19.6 Details of Programming/Erasing Flash Memory
19.7 Sample Program for 512 Kbit Flash Memory
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.1 Overview of 512 Kbit/1 Mbit Flash Memory
19.1
MB90495G Series
Overview of 512 Kbit/1 Mbit Flash Memory
There are three ways of programming and erasing flash memory as follows:
1. Programming and erasing using parallel writer
2. Programming and erasing using serial writer
3. Programming and erasing by executing program
This chapter describes the above "3. Programming and Erasing by Executing Program".
■ Overview of 512 Kbit/1 Mbit Flash Memory
512 Kbit flash memory is placed in the FFHbanks on the CPU memory map. 1 Mbit flash memory is placed
in the FEH - FFH banks on the CPU memory map. The function of the flash memory I/F circuit provides
read access and program access from the CPU to flash memory.
Programming and erasing flash memory are enabled by an instruction from the CPU via the flash memory
I/F circuit. This allows reprogramming in the mounted state under CPU control and improvement of
programming data efficiency.
■ Features of 512 Kbit/1 Mbit Flash Memory
• 512 Kbit Flash Memory:64 Kword x 8 bits/32Kword x 16 bits (16 K + 8 K + 8 K + 32 K) sectors
1 Mbit Flash Memory: 128 Kword x 8 bits/64 Kword x 16 bits (16 K + 8 K + 8 K + 32 K + 64 K)
sectors
• Uses automatic program algorithm (Embedded Algorithm): the same manner as MBM29LV200
• Erase pause/restart function
• Detects completion of writing/erasing using data polling or toggle bit functions
• Detects completion of writing/erasing by CPU interrupts
• Sector erase function (any combination of sectors)
• Programming/erase count 10,000 (min.)
• Flash read cycle time (min.): 2 machine cycles
Note:
The function for reading the manufacture code and device code is unprovided.
These codes cannot be accessed by any command.
■ Programming and Erasing Flash Memory
• Programming and erasing flash memory cannot be performed at one time.
• Programming or erasing flash memory can be performed by copying the program in flash memory to
RAM and executing the program copied in RAM.
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.2 Registers and Sector Configuration of Flash Memory
MB90495G Series
19.2
Registers and Sector Configuration of Flash Memory
This section explains the registers and the sector configuration of flash memory.
■ List of Registers and Reset Values of Flash Memory
Figure 19.2-1 List of Registers and Reset Values of Flash Memory
bit
Flash memory control status
register (FMCS)
×: Undefined
7
6
5
4
3
2
1
0
0
0
0
×
0
0
0
0
■ Sector Configuration of 512 Kbit/1 Mbit Flash Memory
Figure 19.2-2 shows the sector configuration of 512 Kbit/1 Mbit flash memory. The upper and lower
addresses of each sector are given in the figure.
● Sector configuration
For access from the CPU, the FF bank register has SA0 to SA3 in case of 512 Kbit flash memory, and the
FE bank register has SA0 and the FF bank register has SA1 to SA4 in case of 1 Mbit flash memory.
Figure 19.2-2 Sector Configuration of 512 Kbit/1 Mbit Flash Memory
512 Kbit Flash memory
CPU address
Writer address*
SA0 (32 Kbytes)
FF0000H
FF7FFF H
70000H
77FFFH
SA1 (8 Kbytes)
FF8000H
FF9FFF H
78000H
79FFFH
SA2 (8 Kbytes)
FFA000H
FFBFFF H
7A000H
7BFFF H
SA3 (16 Kbytes)
FFC000 H
FFFFFF H
7C000H
7FFFFH
1 Mbit Flash memory
CPU address
Writer address*
SA0 (64 Kbytes)
FE0000H
FEFFFF H
60000H
6FFFFH
SA1 (32 Kbytes)
FF0000H
FF7FFF H
70000H
77FFFH
SA2 (8 Kbytes)
FF8000H
FF9FFF H
78000H
79FFFH
SA3 (8 Kbytes)
FFA000H
FFBFFF H
7A000H
7BFFF H
SA4 (16 Kbytes)
FFC000 H
FFFFFF H
7C000H
7FFFFH
*: The writer address is equivalent to the CPU address when data is
programmed to flash memory by a parallel writer. This address is
where programming and erasing are performed by a generalpurpose writer.
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.3 Flash Memory Control Status Register (FMCS)
19.3
MB90495G Series
Flash Memory Control Status Register (FMCS)
The flash memory control status register (FMCS) functions are shown in Figure 19.3-1.
■ Flash Memory Control Status Register (FMCS)
Figure 19.3-1 Flash Memory Control Status Register (FMCS)
7
6
5
4
3
2
1
0
Reset value
000X0000
R/W R/W R/W
R
W
R/W
W
B
R/W
bit 2 bit 0
LPM1 LPM0
Low-power consumption mode select bits
Power consumption mode
0
0
Normal-power consumption mode
0
1
Low-power consumption mode
1
0
1
1
Conditions of internal operating frequency
Operation at internal operating
frequency of 16 MHz or less
Operation at internal operating
frequency of 4 MHz or less
Operation at internal operating
frequency of 8 MHz or less
Operation at internal operating
frequency of 10 MHz or less
bit 1
Reserved bit
Reserved
0
Always set to "0"
bit 3
Reserved bit
Reserved
0
Always set to "0"
bit 4
Flash memory programming/erasing status bit
RDY
0
Programming/erasing (next data programming/erasing disabled)
1
Programming/erasing terminated (next data programming/erasing enabled)
bit 5
WE
0
1
Flash memory programming/erasing enable bit
Programming/erasing flash memory area disabled
Programming/erasing flash memory area enabled
bit 6
RDYINT
0
1
Flash memory operation flag bit
Read
Programming/erasing
Write
This RDYIN bit cleared
Programming/erasing terminated No effect
bit 7
R/W
R
W
X
612
:
:
:
:
:
Read/Write
Read only
Write only
Undefined
Reset value
INTE Flash memory programming/erasing interrupt enable bit
0
Interrupt disabled at end of programming/erasing
1
Interrupt enabled at end of programming/erasing
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.3 Flash Memory Control Status Register (FMCS)
MB90495G Series
Table 19.3-1 Functions of Flash Memory Control Status Register (FMCS)
Bit Name
Function
bit 0 and bit 2
LPM0, LPM1:
Low-power consumption
mode select bits
These bits control the current consumption of flash memory.
• Since the time for access to flash memory differs largely depending on the
operating frequency, set the operating frequency in reference to the
internal operating frequency of the CPU.
bit 1 and bit 3
Reserved: Reserved bits
Always set these bits to 0.
bit 4
RDY:
Flash memory
programming/erasing
status bit
This bit shows the programming/erasing status of flash memory.
• If the RDY bit is 0, programming/erasing flash memory is disabled.
• The suspend commands, such as the read/reset command and sector
erasing pause, can be accepted even if the RDY bit is 0. The RDY bit is
set to 1 when programming/erasing is completed.
bit 5
WE:
Flash memory
programming/erasing
enable bit
This bit enables or disables the programming/erasing of flash memory.
The WE bit should be set before starting the command to program/erase flash
memory.
When set to 0: No program/erase signal is generated even if the command to
program/erase the FF bank is input.
When set to 1: Programming/erasing flash memory is enabled after
inputting program/erase command to the FF bank.
• When not performing programming/erasing, the WE bit should be set to 0
so as not to accidentally program or erase flash memory.
bit 6
RDYINT:
Flash memory operation
flag bit
This bit shows the operating state of flash memory.
If programming/erasing flash memory is terminated, the RDYINT bit is set to
1 in timing of termination of the automatic flash memory algorithm.
• If the RDYINT bit is set to 1 when an interrupt as programming/erasing
flash memory is terminated is enabled (FMCS:INTE = 1), an interrupt is
requested.
• If the RDYINT bit is 0, programming/erasing flash memory is disabled.
When set to 0: Cleared.
When set to 1: Unaffected.
If the read-modify-write (RMW) instructions are used, 1 is always read.
bit 7
INTE:
Flash memory
programming/erasing
interrupt enable bit
This bit enables or disables an interrupt as programming/erasing flash
memory is terminated.
When set to 1:If the flash memory operation flag bit is set to 1
(FMCS:RDYINT = 1), an interrupt is requested.
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.3 Flash Memory Control Status Register (FMCS)
Note:
MB90495G Series
The flash memory operation flag bit (RDYINT) and flash memory programming/erasing status bit (RDY)
do not change simultaneously. A program should be created so that either RDYINT bit or RDY bit can
identify the termination of programming/erasing.
Automatic algorithm
end timing
RDYINT bit
RDY bit
1 Machine cycle
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.4 How to Start Automatic Algorithm of Flash Memory
MB90495G Series
19.4
How to Start Automatic Algorithm of Flash Memory
There are four commands for starting the automatic algorithm of flash memory: read/
reset, write, chip erase. The sector erase command controls suspension and
resumption of sector erase.
■ Command Sequence Table
Table 19.4-1 list the commands used in programming/erasing flash memory.
All data is written to command registers by byte access but should be written by word access in the normal
mode. Upper data bytes are ignored.
Table 19.4-1 Command Sequence Table
Write Cycle of
Command Bus
Write
First Bus
Sequence
Access Address Data
Read/
FFXXXX XXF0
1
Reset*
Read/
FFAAAA XXAA
4
Reset*
Write
FFAAAA XXAA
4
program
Chip
FFAAAA XXAA
6
erace
Sector
FFAAAA XXAA
6
erase
Write Cycle of Write Cycle of Write Cycle of Write Cycle of Write Cycle of
Second Bus
Third Bus
Fourth Bus
Fifth Bus
Sixth Bus
Address Data Address Data Address Data Address Data Address Data
−
−
−
−
−
−
−
−
−
−
FF5554
XX55 FFAAAA XXF0
RA
RD
−
−
−
−
FF5554
XX55 FFAAAA XXA0
PA
(even)
PD
(word)
−
−
−
−
FF5554
XX55 FFAAAA XX80 FFAAAA XXAA
FF5554
XX55 FFAAAA
FF5554
XX55 FFAAAA XX80 FFAAAA XXAA
FF5554
XX55
SA
(even)
Sector erase suspend
Input of address"FFXXXX"Data (xxB0H) suspends sector erasing.
Sector erase resume
Input address"FFXXXX"Data (xx30H) suspends and resume sector erasing.
Auto
Select
3
Notes:
CM44-10114-7E
FFAAAA XXAA
FF5554
XX55 FFAAAA XX90
−
−
−
−
−
XX10
XX30
−
• Addresses in the table are the values in the CPU memory map. All addresses and data are hexadecimal
values, where "x" is any value.
• RA: Read address
• PA: Program address. Only even addresses can be specified.
• SA: Sector address (See "19.2 Registers and Sector Configuration of Flash Memory")
• RD: Read data
• PD: Program data. Only word data can be specified.
*: Two kinds of read/reset commands can reset flash memory to the read mode.
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.4 How to Start Automatic Algorithm of Flash Memory
MB90495G Series
Auto Select in Table 19.4-1 is the command to check the state of sector protection. The addresses must be
set as indicated below together with the command in Table 19.4-1.
Table 19.4-2 Address Setting for Auto Select
Sector
protection
AQ13 to AQ15
AQ7
AQ2
AQ1
AQ7
DQ7 to DQ0
Sector address
L
H
L
L
CODE *
*: The output at the protected sector address is "01H".
The output at the unprotected sector address is "00H".
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.5 Check the Execution State of Automatic Algorithm
MB90495G Series
19.5
Check the Execution State of Automatic Algorithm
Since the programming/erasing flow is controlled by the automatic algorithm, hardware
sequence can check the internal operating state of flash memory.
■ Hardware Sequence Flags
● Overview of hardware sequence flag
The hardware sequence flag consists of the following 4-bit outputs:
• Data polling flag (DQ7)
• Toggle bit flag (DQ6)
• Timing limit over flag (DQ5)
• Sector erasing timer flag (DQ3)
These flags can be used to check whether programming, chip and sector erasing, and erase code writing are
enabled.
The hardware sequence flags can be referred by setting command sequences and performing read access to
the address of a target sector in flash memory. Table 19.5-1 gives the bit allocation of the hardware
sequence flags.
Table 19.5-1 Bit Allocation of Hardware Sequence Flags
Bit No.
Hardware sequence flag
7
6
5
4
3
2
1
0
DQ7
DQ6
DQ5
−
DQ3
−
−
−
• To identify whether automatic programming/chip and sector erasing is in execution or terminated, check
the hardware sequence flag or the flash memory programming/erasing status bit in the flash memory
control status register (FMCS:RDY). Programming/erasing is terminated, returning to the read/reset
state.
• To create a programming/erasing program, use the DQ7, DQ6, DQ5, and DQ3 flags to check that
automatic programming/erasing is terminated and read data.
• The hardware sequence flags can also be used to check whether the second and later sector erase code
writing is enabled.
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.5 Check the Execution State of Automatic Algorithm
MB90495G Series
● Explanation of hardware sequence flag
Table 19.5-2 lists the functions of the hardware sequence flag.
Table 19.5-2 List of Hardware Sequence Flag Functions
State
State change in
normal
operation
Abnormal
operation
618
DQ7
DQ6
DQ5
DQ3
Programming --> Completed
(when program address
specified)
DQ7 -->
DADATA:7
Toggle -->
DATA:6
0 -->
DATA:5
0 -->
DATA:3
Chip and sector erasing
--> Completed
0 --> 1
Toggle --> Stop
0 --> 1
1
Sector erasing wait
--> Started
0
Toggle
0
0 --> 1
Erasing --> Sector erasing
suspended
(Sector being erased)
0 --> 1
Toggle --> 1
0
1 --> 0
Sector erasing suspended -->
Resumed
(Sector being erased)
1 --> 0
1 --> Toggle
0
0 --> 1
Sector erasing being
suspended
(Sector not being erased)
DATA:7
DATA:6
DATA:5
DATA:3
Programming
DQ7
Toggle
1
0
Chip and sector erasing
0
Toggle
1
1
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.5 Check the Execution State of Automatic Algorithm
MB90495G Series
19.5.1
Data Polling Flag (DQ7)
The data polling flag (DQ7) is mainly used to notify that the automatic algorithm is
executing or has been completed using the data polling function.
■ Data Polling Flag (DQ7)
Table 19.5-3 and Table 19.5-4 give the state transition of the data polling flag.
Table 19.5-3 State Transition of Data Polling Flag (State Change at Normal Operation)
Programming
--> Completed
Operating State
DQ7 -->
DATA:7
DQ7
Chip and
Sector Erasing
--> Completed
Wait for Sector
Erasing -->
Started
Sector Erasing
--> Erasing
Suspended
(Sector being
Erased)
Sector Erasing
Suspended -->
Resume
(Sector being
Erased)
Sector Erasing
being
Suspended
(Sector not
being Erased)
0 --> 1
0
0 --> 1
1 --> 0
DATA:7
Table 19.5-4 State Transition of Data Polling (State Change at Abnormal Operation)
Operating
State
DQ7
Programming
Chip and
Sector Erasing
DQ7
0
● At programming
• Read access during execution of the auto-programming algorithm causes flash memory to output the
reversed data of bit 7 last written.
• Read access at the end of the auto-programming algorithm causes flash memory to output the value of
bit 7 at the address to which read access was performed.
● At chip/sector erasing
• During executing chip and sector erasing algorithms, when read access is made to the currently being
erasing sector, bit 7 of flash memory outputs 0. When chip erasing/sector erasing is terminated, bit 7 of
flash memory outputs 1.
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19.5 Check the Execution State of Automatic Algorithm
MB90495G Series
● At sector erasing suspension
• Read access during sector erasing suspension causes flash memory to output 1 if the address specified
by the address signal belongs to the sector being erased. Flash memory outputs bit 7 (DATA:7) of the
read value at the address specified by the signal address if the address specified by the address signal
does not belong to the sector being erased.
• Referring this flag together with the toggle bit flag (DQ6) permits a decision on whether flash memory
is in the erase suspended state and which sector is being erased.
Note:
620
Read access to the specified address while the automatic algorithm starts is ignored. At data reading,
other bits can be output at the end of data polling flag (DQ7). Data reading after the end of the automatic
algorithm should be performed following read access after completion of data polling has been checked.
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.5 Check the Execution State of Automatic Algorithm
MB90495G Series
19.5.2
Toggle Bit Flag (DQ6)
The toggle bit flag is used to notify that the automatic algorithm is being executed or in
the end state using the toggle bit function.
■ Toggle Bit Flag (DQ6)
Table 19.5-5 and Table 19.5-6 give the state transition of the toggle bit flag.
Table 19.5-5 State Transition of Toggle Bit Flag (State Change at Normal Operation)
Programming
--> Completed
Operating State
Toggle -->
DATA:6
DQ6
Chip and
Sector Erasing
--> Erasing
Completed
Wait for Sector
Erasing -->
Erasing
Started
Sector Erasing
--> Erasing
Suspended
(Sector being
Erased)
Sector Erasing
Suspended -->
Resume
(Sector being
Erased)
Sector Erasing
Suspended
(Sector not
being Erased)
Toggle --> Stop
Toggle
Toggle --> 1
1 --> Toggle
DATA:6
Table 19.5-6 State Transition of Toggle Bit Flag (State Change at Abnormal Operation)
Operating
State
DQ6
Programming
Chip and
Sector Erasing
Toggle
Toggle
● At programming and chip/sector erasing
• If a continuous read access is made during the execution of the automatic algorithm for programming
and chip erasing/sector erasing, flash memory toggle-outputs 1 and 0 alternately every reading.
• If a continuous read access is made after the completion of the automatic algorithm for programming
and chip erasing/sector erasing, flash memory outputs bit 6 (DATA:6) for the read value of the read
address every reading.
● At sector erasing suspension
If a read access is made in the sector erasing suspension state, flash memory outputs 1 when the read
address is the sector being erased and bit 6 (DATA:6) for the read value of the read address when the read
address is not the sector being erased.
Reference:
CM44-10114-7E
If the sector for programming is reprogram-protected, the toggle bit flag (DQ6) produces a toggle output
for approximately 2 µs, and then terminates it without reprogramming data.
If all sectors for erasing are reprogram-protected, the toggle bit flag (DQ6) produces a toggle output for
approximately 100 µs, and then returns to the read/reset state without reprogramming data.
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.5 Check the Execution State of Automatic Algorithm
19.5.3
MB90495G Series
Timing Limit Over Flag (DQ5)
The timing limit over flag (DQ5) is a hardware sequence flag that notifies flash memory
that the execution of the automatic algorithm has exceeded a prescribed time (the time
required for programming/erasing).
■ Timing Limit Over Flag (DQ5)
Table 19.5-7 and Table 19.5-8 give the state transition of the timing limit over flag.
Table 19.5-7 State Transition of Timing Limit Over Flag (State Change at Normal Operation)
Operating State
DQ5
Programming
--> Completed
0 --> DATA:5
Chip and
Sector Erasing
--> Completed
Wait for Sector
Erasing -->
Started
Sector Erasing
--> Erasing
Suspended
(Sector being
Erased)
Sector Erasing
Suspended -->
Resume
(Sector being
Erased)
Sector Erasing
being
Suspended
(Sector not
being Erased)
0 --> 1
0
0
0
DATA:5
Table 19.5-8 State Transition of Timing Limit Over Flag (State Change at Abnormal Operation)
Operating
State
DQ5
Programming
Chip and
Sector Erasing
1
1
● At programming and chip erasing/sector erasing
• If a read access made after starting the automatic algorithm for programming or chip erasing/sector
erasing is within a prescribed time (the time required for programming/erasing), the timing limit over
flag (DQ5) outputs 0. If it exceeds the prescribed time, the timing limit over flag (DQ5) outputs 1.
• The timing limit over flag (DQ5) can be used to identify the success or failure of programming/erasing,
regardless of whether the automatic algorithm is in progress or terminated. If the automatic algorithm by
the data polling or the toggle bit function is in execution when the timing limit over flag (DQ5) outputs
1, programming can be identified as a failure.
• For example, when 1 is set to the flash memory address with 1 set the flash memory, programming fails.
In this case, the flash memory will be locked and the automatic algorithm will not complete. Therefore,
no valid data is output from the data polling flag (DQ7). Also, the toggle bit flag (DQ6) does not stop
the toggle operation and exceeds the time limit, causing the timing limit over flag (DQ5) to output 1.
This state means that the flash memory is not being used correctly; it does not mean that the flash
memory is faulty. When this state occurs, execute the reset command.
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.5 Check the Execution State of Automatic Algorithm
MB90495G Series
19.5.4
Sector Erase Timer Flag (DQ3)
The sector erase timer flag is used to notify during the period of waiting for sector
erasing after the sector erase command has started.
■ Sector Erase Timer Flag (DQ3)
Table 19.5-9 and Table 19.5-10 give the state transition of the sector erase timer flag.
Table 19.5-9 State Transition of Sector Erase Timer Flag (State Change at Normal Operation)
Programming
--> Completed
Operating State
0 --> DATA3
DQ3
Chip and
Sector Erasing
--> Completed
Wait for Sector
Erasing -->
Started
Sector Erasing
--> Erasing
Suspended
(Sector being
Erased)
Sector Erasing
Suspended -->
Resume
(Sector being
Erased)
Sector Erasing
being
Suspended
(Sector not
being Erased)
1
0 --> 1
1 --> 0
0 --> 1
DATA:3
Table 19.5-10 State Transition of Sector Erase Timer Flag (State Change at Abnormal Operation)
Operating
State
DQ3
Programming
Chip and
Sector Erasing
0
1
● At sector erasing
• If a read access made after starting the sector erase command is within a sector erasing wait period, the
sector erasing timer flag (DQ3) outputs 0. If it exceeds the period, the sector erasing timer flag (DQ3)
outputs 1.
• If the sector erasing timer flag (DQ3) is 1, indicating that the automatic algorithm for sector erasing by
the data polling or toggle bit function is in progress (DQ = 0; DQ6 produces a toggle output), sector
erasing is performed. If any command other than the sector erasing suspension is set, it is ignored until
sector erasing is terminated.
• If the sector erasing timer flag (DQ3) is 0, flash memory can accept the sector erase command. To
program the sector erase command, check that the sector erasing timer flag (DQ3) is 0. If the flag is 1,
flash memory may not accept the sector erase command of suspending.
● At sector erasing suspension
• Read access during sector erasing suspension causes flash memory to output 1, if the read address is the
sector being erased. Flash memory outputs bit 3 (DATA:3) for the read value of the read address when
the read address is not the sector being erased.
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.6 Details of Programming/Erasing Flash Memory
19.6
MB90495G Series
Details of Programming/Erasing Flash Memory
This section explains the procedure for inputting commands starting the automatic
algorithm, and for read/reset of flash memory, programming, chip erasing, sector
erasing, sector erasing suspension and sector erasing resumption.
■ Detailed Explanation of Programming and Erasing Flash Memory
Automatic algorithm can be started by programming the command sequence of read/reset, programming,
chip erasing, sector erasing, sector erasing suspension and erasing resumption from CPU to flash memory.
Programming flash memory from the CPU should always be performed continuously. The termination of
the automatic algorithm can be checked by the data polling function. After normal termination, it returns to
the read/reset state.
Each operation is explained in the following order.
• Read/reset state
• Data programming
• All data erasing (chip all erase)
• All data erasing (chip all erase)
• Sector erasing suspension
• Sector erasing resumption
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.6 Details of Programming/Erasing Flash Memory
MB90495G Series
19.6.1
Read/Reset State in Flash Memory
This section explains the procedure for inputting the read/reset command to place flash
memory in the read/reset state.
■ Read/Reset State in Flash Memory
• Flash memory can be placed in the read/reset state by transmitting the read/reset command in the
command sequence table from CPU to flash memory.
• There are two kinds of read/reset commands: one is executed at one time bus operation, and the other is
executed at three times bus operations; the command sequence of both is essentially the same.
• Since the read/reset state is the initial state for flash memory, flash memory always enters this state after
power-on and at the normal termination of command. The read/reset state is also described as the wait
state for command input.
• In the read/reset state, a read access to flash memory enables data to be read. As is the case with mask
ROM, a program access from the CPU can be made. A read access to flash memory does not require the
read/reset command. If the command is not terminated normally, use the read/reset command to
initialize the automatic algorithm.
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.6 Details of Programming/Erasing Flash Memory
19.6.2
MB90495G Series
Data programming to flash memory
This section explains the procedure for inputting the program command to program
data to flash memory.
■ Data Programming to Flash Memory
• In order to start the data programming automatic algorithm, continuously transmit the program
command in the command sequence table from CPU to flash memory.
• At completion of data programming to a target address in the fourth cycle, the automatic algorithm starts
automatic programming.
● How to specify address
• The only even addresses can be specified for the programming address specified by programming data
cycle. Specifying odd addresses prevents correct writing. Writing to even addresses must be performed
in word data units.
• Programming is possible in any address order or even beyond sector boundaries. However, execution of
one programming command, permits programming of only one word for data.
● Notes on data programming
• Data 0 cannot be returned to data 1 by programming. When data 0 is programmed to data 1, the data
polling algorithm (DQ7) or toggling (DQ6) is not terminated and the flash memory is considered faulty;
the timing limit over flag (DQ5) is determined as an error.
• When data is read in the read/reset state, the bit data remains 0. To return the bit data to 1 from 0, erase
flash memory data.
• All commands are ignored during automatic programming. If a hardware reset occurs during
programming, data being programmed to addresses are not assured.
• Do not change to the sub clock mode or a standby mode (sleep mode, stop mode, watch mode, timebase timer mode) during data write operation.
■ Data Programming Procedure
• Figure 19.6-1 gives an example of the procedure for programming data into flash memory. The
hardware sequence flags can be used to check the operating state of the automatic algorithm in flash
memory. The data polling flag (DQ7) is used for checking the completion of programming to flash
memory in this example.
• Flag check data should be read from the address where data was last written.
• Because the data polling flag (DQ7) and the timing limit over flag (DQ5) change at the same time, the
data polling flag (DQ7) must be checked even when the timing limit over flag (DQ5) is 1.
• Similarly, since the toggle bit flag (DQ6) stops toggling at the same time the timing limit over flag
(DQ5) changes to 1, toggle bit flag (DQ6) must be checked.
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.6 Details of Programming/Erasing Flash Memory
MB90495G Series
Figure 19.6-1 Example of Data Programming Procedure
Start
FMCS : WE (bit 5)
Programming enabled
Program command sequence
(1) FFAAAA ← XXAA
(2) FF5554 ← XX55
(3) FFAAAA ← XXA0
(4) Program address ← Program data
Internal address read
Data polling
(DQ7)
Next address
Data
Data
0
Timing limit
(DQ5)
1
Internal address read
Data
Data polling
(DQ7)
Data
Programming error
Last address
NO
YES
FMCS : WE (bit 5)
Programming enabled
Completed
CM44-10114-7E
Check by hardware
sequence flag
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.6 Details of Programming/Erasing Flash Memory
19.6.3
MB90495G Series
Data Erase from Flash Memory (Chip Erase)
This section explains the procedure for inputting the chip erase command to erase all
data from flash memory.
■ All Data Erase from Flash Memory (Chip Erase)
• All data can be erased from flash memory by continuously transmitting the chip erase command in the
command sequence table from CPU to flash memory.
• The chip erase command is executed in six bus operations. Chip erasing is started at completion of the
sixth programming cycle.
• Before chip erasing, the user need not perform programming to flash memory. During execution of the
automatic erasing algorithm, flash memory automatically programs 0 before erasing all cells.
■ Note on Chip Erase
Do not change to the sub clock mode or a standby mode (sleep mode, stop mode, watch mode, time-base
timer mode) during chip erase operation.
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.6 Details of Programming/Erasing Flash Memory
MB90495G Series
19.6.4
Erasing Any Data in Flash Memory (Sector Erasing)
This section explains the procedure for inputting the sector erase command to erase
any data in flash memory. Sector-by-sector erasing is enabled and multiple sectors can
be specified at a time.
■ Erasing Any Data in Flash Memory (Sector Erasing)
Any sector in flash memory can be erased by continuously transmitting the sector erase command in the
command sequence table from CPU to flash memory.
● How to specify sector
• The sector erase command is executed in six bus operations. By setting the address on the sixth cycle in
the even address in the target sector and programming the sector erase code (30H) to data, a 50 μs sector
erasing wait is started
• When erasing more than one sector, the sector erase code (30H) is programmed to the sector address to
be erased, following the above.
● Notes on specifying multiple sectors
• Sector erasing is started after a 50 μs period waiting for sector erasing is completed after the last sector
erase code has been programmed.
• That is, when erasing more than one sector simultaneously, the address of erase sector address and the
sector code must be input within 50 μs. If the sector erase code is input 50 μs or later, it cannot be
accepted.
• Whether continuous programming of the sector erase code is enabled can be checked by the sector erase
timer flag (DQ3).
• In this case, the address from which the sector erase timer is flag (DQ3) read should correspond to the
sector to be erased.
■ Erasing Procedure for Flash Memory Sectors
• The state of the automatic algorithm in the flash memory can be determined using the hardware
sequence flag. Figure 19.6-2 gives an example of the flash memory sector erase procedure. In this
example, the toggle bit flag (DQ6) is used to check that erase ends.
• DQ6 terminates toggling concurrently with the change of the timing limit over flag (DQ5) to 1, so the
DQ6 must be checked even when DQ5 is 1.
• Similarly, the data polling flag (DQ7) changes concurrently with the transition of the DQ5, so DQ7
must be checked.
■ Note on Sector Erase
Do not change to the sub clock mode or a standby mode (sleep mode, stop mode, watch mode, time-base
timer mode) during Sector erase operation.
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.6 Details of Programming/Erasing Flash Memory
MB90495G Series
Figure 19.6-2 Example of Sector Erasing Procedure
Start
FMCS:WE(bit5)
Enable erasing to flash memory
Erase command sequence
(1) FxAAAAH
XXAAH
(2) Fx5554H
XX55H
(3) FxAAAAH
XX80H
(4) FxAAAAH
XXAAH
(5) Fx5554H
XX55H
(6) Sector address
Erase code (XX30H)
YES
Another erase sector?
NO
(6) Sector address
Erase code (XX30H)
Read internal address 1
Read internal address
Read internal address 2
1
Toggle bit (DQ6)
Data 1 (DQ6)=Data 2 (DQ6)
YES
0
Erase specification has not
been added within 50 μs.
Set remainder re-execution
flag, and
terminate erase once
NO
0
Secter erase timer
(DQ3)
Timing limit (DQ5)
1
Read internal address 1
Read internal address 2
NO
Toggle bit (DQ6)
Data 1 (DQ6)=Data 2 (DQ6)
YES
Erase error
Remainder
re-execution flag?
YES
NO
FMCS:WE(bit5)
Disable erasing to flash memory
X:
Any value
Completed
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CM44-10114-7E
CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.6 Details of Programming/Erasing Flash Memory
MB90495G Series
19.6.5
Sector Erase Suspension
This section explains the procedure for inputting the sector erase suspend command to
suspend sector erasing. Data can be read from the sector not being erased.
■ Sector Erase Suspension
• To cause flash memory sector erasing to suspend, continuously transmit the sector erasing suspend
command in the command sequence table from CPU to flash memory.
• The sector erasing suspend command suspends the sector erase currently being performed, enabling data
read from a sector that is currently not being erased. Only read can be performed when this command is
suspended; programming cannot be performed. This command is only enabled during the sector erasing
period including the erasing wait time; it is ignored during the chip erasing period or during
programming.
• The sector erasing suspend command is executed when the sector erasing suspend code (B0H) is
programmed. Arbitrary address in flash memory should be set for address. If the sector erasing suspend
command is executed during sector erasing pause, the command input again is ignored.
• When the sector erasing suspend command is input during the sector erasing wait period, the sector
erase wait state ends immediately, the erasing is interrupted, and the erase stop state occurs.
• When the erase suspend command is input during the sector erasing after the sector erase wait period,
the erase suspend state occurs after 15 μs max.
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.6 Details of Programming/Erasing Flash Memory
19.6.6
MB90495G Series
Sector Erase Resumption
This section explains the procedure for inputting the sector erase resume command to
resume erasing of the suspended flash memory sector.
■ Erase Resumption
• Suspended sector erasing can be resumed by continuously transmitting the sector erase resume
command in the command sequence table from CPU to flash memory.
• The sector erase resume command resumes sector erasing suspended by the sector erase suspend
command. This command is executed by writing the erase resume code (30H). In this case, address in
the flash memory area is specified.
• Inputting the sector erase resume command during sector erasing is ignored.
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.7 Sample Program for 512 Kbit Flash Memory
MB90495G Series
19.7
Sample Program for 512 Kbit Flash Memory
A sample program for the 512 Kbit flash memory is given below.
■ Sample Program for 512 Kbit Flash Memory
NAME
FLASHWE
TITLE
FLASHWE
;-------------------------------------------------------------------------------; 512 Kbit FLASH Sample Program
; 1: Transfer program in flash (address FFBC00 H,
;
sector SA2) to RAM (address 000700H).
; 2: Execute program on RAM.
; 3: Program PDR1 value to flash (address FF0000H, sector SA0).
; 4: Read programmed value (address FF0000H, sector SA0) and output to PDR2.
; 5: Erase programmed sector (SA0).
; 6: Output check that data is erased.
; Conditions
;
- Count of bytes transferred to RAM: 100H (256 bytes)
;
- Completion of programming and erasing checked by:
;
Timing limit over flag (DQ5)
;
Toggle bit flag (DQ6)
;
RDY (FMCS)
;
- Action taken at error
;
Output H to P00 to P07.
;
Issue reset command.
;-------------------------------------------------------------------------------;
RESOUS IOSEG ABS=00
; Definition of "RESOUS" I/O segment
ORG
0000H
PDR0
RB
1
PDR1
RB
1
PDR2
RB
1
PDR3
RB
1
ORG
0010H
DDR0
RB
1
DDR1
RB
1
DDR2
RB
1
DDR3
RB
1
ORG
00A1H
CKSCR
RB
1
ORG
00AEH
FMCS
RB
1
ORG
006FH
ROMM
RB
1
RESOUS ENDS
;
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.7 Sample Program for 512 Kbit Flash Memory
SSTA
STA_T
SSTA
;
DATA
SSEG
RW
RW
ENDS
MB90495G Series
0127H
1
DSEG ABS=0FFH
; FLASH command address
ORG
5554H
COMADR2 ORG
1
ORG
0AAAAH
COMADR1 ORG
1
DATA
ENDS
;-------------------------------------------------------------------------------; Main program (SA1)
;-------------------------------------------------------------------------------CODE
CSEG
START:
;-----------------------------------------------------------------------; Initialize
;-----------------------------------------------------------------------MOV
CKSCR,#0BAH
; Set to 3-multiplying count
MOV
RP,#0
MOV
A,#!STA_T
MOV
SSB,A
MOVW A,#!STA_T
MOVW SSB, A
MOV
ROMM,#00H
; Mirror OFF
MOV
ROMM,#00H
; For error check
MOV
DDR0,#0FFH
MOV
PDR1,#00H
; Data input port
MOV
DDR1,#00H
MOV
PDR2,#00H
; Data output port
MOV
DDR2,#0FF
;-----------------------------------------------------------------------; Transfer FLASH programming/erasing program (FFBC00H) to RAM
; (address 700H)
;-----------------------------------------------------------------------MOVW A,#0700H
; Transfer destination RAM area
MOVW A,#0BC00H
; Transfer source address
; (position where program exist)
MOVW RW0,#100H
; Count of bytes to be transferred
MOVS ADB,PCB
; Transfer 100Hfrom FFBC00Hto 000700H
CALLP 000700H
; Jump to address where transferred program exists
OUT
END
CODE
634
;-----------------------------------------------------------------------; Data output
;-----------------------------------------------------------------------MOV
A,#0FFH
MOV
ADB,A
MOVW RW2,#0000H
MOVW A,@RW2+00
MOV
PDR2,A
JMP
*
ENDS
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
MB90495G Series
CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.7 Sample Program for 512 Kbit Flash Memory
;-------------------------------------------------------------------------------Flash programming/erasing program (SA2)
;-------------------------------------------------------------------------------RAMPRG CSEG ABS=0FFH
ORG
0BC00H
;-----------------------------------------------------------------------; Initialize
;-----------------------------------------------------------------------MOVW RW0,#0500H
; RW0: RAM space for storage of input data
; 00:0500 to
MOVW RW2,#0000H
; RW2: Flash memory programming address
; FD:0000 to
MOV
A,#00H
; DTB change
MOV
DTB,A
; Specify bank for @RW0
MOV
A,#0FFH
; ADB change 1
MOV
ADB,A
; Specify bank for program mode specifying address
MOV
PDR3,#00H
; Initialize switch
MOV
DDR3,#00H
;
WAIT1
BBC
PDR3:0,WAIT1
; PDR3: 0 with High level, start programming
;
;-------------------------------------------------------------------------------; Program (SA0)
;-------------------------------------------------------------------------------MOV
A,PDR1
MOVW @RW0+00,A
; Save PDR1 data in RAM.
MOV
FMCS,#20H
; Set program mode.
MOVW ADB:COMADR1, #00AAH
; Flash program command 1
MOVW ADB:COMADR2, #0055H
; Flash program command 2
MOVW ADB:COMADR1, #00A0H
; Flash program command 3
;
MOVW A, @RW0+00
; Program input data (RW0) to flash memory (RW2).
;
MOVW @RW2+00, A
WRITE
; Waiting time check
;-----------------------------------------------------------------------;ERROR occurs when the time limit over check flag is set and toggling.
;-----------------------------------------------------------------------MOVW A,@RW2+00
AND
A,#20H
; DQ5 time limit check
BZ
NTOW
; Time limit over
MOVW A,@RW2+00
; AH
MOVW A,@RW2+00
; AL
XORW A
; XOR of AH and AL (1 if value is invalid
AND
A,#40H
; Is DQ6 toggle bit?
BNZ
ERROR
; If yes, go to ERROR.
;-----------------------------------------------------------------------;Programming end check (FMCS-RDY)
;-----------------------------------------------------------------------NTOW
MOVW A,FMCS
AND
A,#10H
; Extract RDY bit (bit 4) of FMCS.
BZ
WRITE
; Is programming ended?
MOV
FMCS,#00H
; Cancel program mode.
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CHAPTER 19 512 KBIT/1 MBIT FLASH MEMORY
19.7 Sample Program for 512 Kbit Flash Memory
MB90495G Series
;-----------------------------------------------------------------------;Program data output
;-----------------------------------------------------------------------MOVW RW2,#0000H
; Output program data
MOVW A, @RW2+00
MOV
PDR2,A
;
WAIT2
BBC
PDR3:1,WAIT2
; PDR3:1 With "H", start sector erasing.
;
;-------------------------------------------------------------------------------; Sector erasing (SA0)
;-------------------------------------------------------------------------------MOV
@RW2+00,#0000H
; Initialize address
MOV
FMCS,#20H
; Set erase mode
MOVW ADB:COMADR1,#00AAH ; Erase command 1
MOVW ADB:COMADR2,#0055H ; Erase command 2
MOVW ADB:COMADR1,#0080H ; Erase command 3
MOVW ADB:COMADR1,#00AAH ; Erase command 4
MOVW ADB:COMADR2,#0055H ; Erase command 5
MOV
@RW2+00,#0030H
; Issue erase command to sector to be erased 6.
ELS
; Waiting check
;-----------------------------------------------------------------------;ERROR occurs when time limit over check flag is set and toggling is underway.
;-------------------------------------------------------------------------------MOVW A,@RW2+0
AND
AND A,#20H
; DQ5 time limit check
BZ
NOTE
; Time limit over
MOVW A,@RW2+00
; During AH programming, "H/L" is output
MOVW A,@RW2+00
; alternately every time AL is read
XORW A
; XOR of AH and AL (1 if DQ6 value invalid,
; indicating programming underway)
AND
A, #40H
; Is DQ6 toggle bit "H"?
BNZ
ERROR
; If yes, go to ERROR
;-----------------------------------------------------------------------;Erasing end check (FMCS-RDY)
;-----------------------------------------------------------------------NTOE
MOVW A,FMCS
;
AND
A,#10H
; Extract RDY bit (bit 4) of FMCS
BZ
ELS
; Is erasing ended?
MOV
FMCS,#00H
; Cancel flash erase mode
RETP
; Return to main program
;-------------------------------------------------------------------------------;Error
;-------------------------------------------------------------------------------ERROR
MOV
ADB:COMADR1,#0F0H ; Reset command (read enabled)
MOV
FMCS,#00H
; Cancel flash mode
MOV
PDR0,#0FFH
; Check error processing
RETP
; Return to main program
RAMPRG ENDS
;------------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG
0FFDCH
DSL
START
DB
00H
VECT
ENDS
;
ENDS START
636
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CM44-10114-7E
CHAPTER 20
FLASH SERIAL
PROGRAMMING
CONNECTION
This chapter describes an example of serial
programming connection using the flash microcontroller
programmer made by Yokogawa Digital Computer
Corporation.
20.1 Basic Configuration of Serial Programming Connection for F2MC16LX MB90F497G/F498G
20.2 Connection Example in Single-chip Mode (User Power Supply)
20.3 Connection Example in Single-chip Mode (Writer Power Supply)
20.4 Example of Minimum Connection to Flash Microcontroller
Programmer (User Power Supply)
20.5 Example of Minimum Connection to Flash Microcontroller
Programmer (Writer Power Supply)
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CHAPTER 20 FLASH SERIAL PROGRAMMING CONNECTION
20.1 Basic Configuration of Serial Programming Connection for F2MC-16LX
MB90F497G/F498G
20.1
MB90495G Series
Basic Configuration of Serial Programming Connection for
F2MC-16LX MB90F497G/F498G
The MB90F497G/F498G supports the serial on-board programming of flash ROM
(Fujitsu standard). The specification for serial on-board programming are explained
below.
■ Basic Configuration of Serial Programming Connection for MB90F497G/F498G
The flash microcontroller programmer made by Yokogawa Digital Computer Corporation. is used for
Fujitsu standard serial on-board programming.
Figure 20.1-1 Basic Configuration of Serial Programming Connection
Host interface cable (AZ221)
General-purpose common cable
(AZ210)
RS232C
Flash
microcontroller
programmer
+
memory card
Clock synchronous serial MB90F497G/F498G
user system
Stand-alone operation enable
Note:
Inquire of Yokogawa Digital Computer Corporation for details about the functions and operations of the
AF220/AF210/AF120/AF110 flash microcontroller programmer, general-purpose common cable for
connection (AZ210), and connectors
Table 20.1-1 Pins Used for Fujitsu Standard Serial On-board Programming (1 / 2)
Pin
MD2, MD1,
MD0
Function
Supplementary Information
Mode pins
Writing 1 to MD2, 1 to MD1 and 0 to MD0 sets the flash serial program
mode.
X0, X1
Oscillation pins
In the flash serial program mode, the internal operating clock of the CPU has
a frequency one time that of the PLL clock, so the internal operating clock
frequency is the same as the oscillation clock frequency. Since the oscillation
clock frequency serves as an internal operation clock, the oscillator used for
serial programming have frequencies from 1 MHz to 16 MHz
P00, P01
Programming program
start pins
638
Input a Low level to P00 and a High level to P01.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 20 FLASH SERIAL PROGRAMMING CONNECTION
20.1 Basic Configuration of Serial Programming Connection for F2MC-16LX
MB90F497G/F498G
Table 20.1-1 Pins Used for Fujitsu Standard Serial On-board Programming (2 / 2)
MB90495G Series
Pin
Function
Supplementary Information
−
RST
Reset pin
SIN1
Serial data input pin
SOT1
Serial data output pin
SCK1
Serial clock input pin
C
C pin
This pin is a capacitance pin for stabilizing voltage. Connect the ceramic
capacitor approx. 0.1 μF externally
VCC
Supply voltage pin
If the program voltage (5 V ± 10%) is supplied from the user system, the
flash microcontroller programmer need not be connected.
VSS
GND pin
GND pin is common to the ground of the flash microcontroller programmer.
Note:
Even if the P00, SIN1, SOT1, and SCK1 pins are used for the user system, the controller shown in the
figure above is required. The TICS signal of the flash microcontroller programmer can be used to
disconnect the user circuit during serial programming.
UART is used in clock synchronous mode
See the following serial programming connection examples given in Sections "20.2 Connection Example
in Single-chip Mode (User Power Supply)" to "20.5 Example of Minimum Connection to Flash
Microcontroller Programmer (Writer Power Supply)".
• Connection example in single-chip mode (user power supply)
• Connection example in single-chip mode (write power supply)
• Example of minimum connection with flash microcontroller (user power supply)
• Example of minimum connection with flash microcontroller (writer power supply)
Figure 20.1-2 Control circuit
AF220/AF210/AF120/AF110
programming control pin
MB90F497G/F498G
programming control pin
10 kΩ
AF220/AF210/AF120/AF110
/TICS pin
User
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CHAPTER 20 FLASH SERIAL PROGRAMMING CONNECTION
20.1 Basic Configuration of Serial Programming Connection for F2MC-16LX
MB90F497G/F498G
MB90495G Series
■ Oscillation Clock Frequency and Serial Clock Input Frequency
The imputable serial clock frequency for the MB90F497G/F498G can be determined by the following
expression. Therefore, change the serial clock input frequency according to the setting of the programmer
of the flash microcontroller on the basis of the oscillation clock frequency.
Imputable serial clock frequency = 0.125 x oscillation clock frequency.
Table 20.1-2 Maximum Serial Clock Frequency
Oscillation
Clock
Frequency
Maximum serial clock
frequency that can be
input for the
microcomputer
Maximum serial clock
frequency that can be
set with AF220/AF210/
AF120/AF110
Maximum serial clock
frequency that can be
set with AF200
4 MHz
500 kHz
500 kHz
500 kHz
8 MHz
1 MHz
850 kHz
500 kHz
16 MHz
2 MHz
1.25 MHz
500 kHz
■ Flash Microcontroller Programmer System Configuration (Made by Yokogawa Digital
Computer Corporation)
Table 20.1-3 Flash Microcontroller Programmer System Configuration (Made by Yokogawa
Digital Computer Corporation)
Model
Function
AF220/AC4P
Model with internal Ethernet interface
/100 V to 220 V power adapter
AF210/AC4P
Standard model
/100 V to 220 V power adapter
AF120/AC4P
Single key internal Ethernet interface mode
/100 V to 220 V power adapter
AF110/AC4P
Single key model
/100 V to 220 V power adapter
Unit
Note:
640
AZ221
PC/AT RS232C cable for writer
AZ220
Standard target probe (a) length: 1 m
FF201
Control module for Fujitsu F2MC-16LX flash microcontroller control
module
/P2
2MB PC Card (Option) Flash memory corresponding Max. 128 KB
/P4
4MB PC Card (Option) Flash memory corresponding Max. 512 KB
The AF200 flash microcontroller programmer is an end product but is made available using the control
module FF201. Examples of serial programming connections can correspond to those in the next section.
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
CHAPTER 20 FLASH SERIAL PROGRAMMING CONNECTION
20.2 Connection Example in Single-chip Mode (User Power Supply)
MB90495G Series
20.2
Connection Example in Single-chip Mode (User Power
Supply)
When 1 is input to the mode pin MD2 of the user system placed in single-chip mode and
0 to the mode pin MD0 from the TAUX and TMODE pins of the AF220/AF210/AF120/
AF110, the system enters the flash memory serial programming mode. An connection
example using the user power supply is given below.
■ Connection Example in Single Chip Mode (User Power Supply Used)
Figure 20.2-1 Example of Serial Programming Connection for MB90F497G/F498G (User Power Supply
Used)
AF220/AF210/AF120/AF110
flash microcontroller
programmer
User system
Connector
DX10-28S
MB90F497G/F498G
(19)
TAUX3
MD2
10 kΩ
10 kΩ
MD1
10 kΩ
(12)
TMODE
MD0
X0
1MHz to 16MHz
X1
TAUX
(23)
/TICS
(10)
P00
10 kΩ
User
10 kΩ
10 kΩ
/TRES
RST
(5)
User
10 kΩ
0.1 μF
TTXD
TRXD
TCK
SIN1
SOT1
SCK1
(13)
(27)
(6)
TVcc
(2)
GND
(7, 8,
14, 15,
21, 22,
1, 28)
Vcc
User power supply
Vss
14 pin
Pins 3, 4, 9, 11, 16, 17, 18, 20, 24, 25 and 26 are OPEN
DX10-28S: Right-angle type
P01
C
1 pin
DX10-28S
28 pin
15 pin
Connector (made by Hirose Electric Co., Ltd.) pin assignment
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CHAPTER 20 FLASH SERIAL PROGRAMMING CONNECTION
20.2 Connection Example in Single-chip Mode (User Power Supply)
Note:
MB90495G Series
• Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the controller shown in the
figure above is required in the same as P00. The /TICS signal of the flash microcontroller programmer
can be used to disconnect the user circuit during serial programming.
• Connect the AF220/AF210/AF120/AF110 while the user power is off.
Figure 20.2-2 Control circuit
AF220/AF210/AF120/AF110
programming control pin
MB90F497G/F498G
programming control pin
10 kΩ
AF220/AF210/AF120/AF110
/TICS pin
User
642
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CM44-10114-7E
CHAPTER 20 FLASH SERIAL PROGRAMMING CONNECTION
20.3 Connection Example in Single-chip Mode (Writer Power Supply)
MB90495G Series
20.3
Connection Example in Single-chip Mode (Writer Power
Supply)
When 1 is input to the mode pin MD2 of the user system placed in single-chip mode and
0 to the mode pin MD0 from the TAUX and TMODE pins of the AF220/AF210/AF210/
AF120/AF110, the system enters the flash memory serial programming mode. An
connection example using the writer power supply is given below.
■ Connection Example in Single Chip Mode (Power Supplied from Flash Microcontroller
Programmer)
Figure 20.3-1 Example of Serial Programming Connection for MB90F497G/F498G (Power Supplied from
Flash Microcontroller Programmer)
AF220/AF210/AF120/AF110
flash microcontroller
programmer
Usersystem
Connector
DX10-28S
TAUX3
MB90F497G/F498G
MD2
(19)
10 kΩ
10 kΩ
MD1
10 kΩ
TMODE
(12)
MD0
X0
1MHz to 16MHz
X1
TAUX
(23)
/TICS
(10)
P00
10 kΩ
User
10 kΩ
10 kΩ
/TRES
RST
(5)
User
10 kΩ
0.1 μF
TTXD
TRXD
TCK
TVcc
Vcc
TVPP1
SIN1
SOT1
SCK1
(13)
(27)
(6)
(2)
(3)
(16)
Vcc
(7, 8,
14, 15,
21, 22,
1, 28)
GND
User power supply
14 pin
Pins 4, 9, 11, 17, 18, 20, 24, 25 and 26 are OPEN
DX10-28S: Right-angle type
CM44-10114-7E
P01
C
Vss
1 pin
DX10-28S
28 pin
15 pin
Connector (made by Hirose Electric Co., Ltd.) pin assignment
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CHAPTER 20 FLASH SERIAL PROGRAMMING CONNECTION
20.3 Connection Example in Single-chip Mode (Writer Power Supply)
Note:
MB90495G Series
• Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the controller shown in the
figure above is required in the same as P00 (Figure 20.3-2). The /TICS signal of the flash
microcontroller programmer can be used to disconnect the user circuit during serial programming
• Connect the AF220/AF210/AF120/AF110 while the user power is off.
• When supplying programming power from AF220/AF210/AF120/AF110, do not short-circuit the
programming power and user power.
Figure 20.3-2 Control circuit
AF220/AF210/AF120/AF110
programming control pin
MB90F497G/F498G
programming control pin
10 kΩ
AF220/AF210/AF120/AF110
/TICS pin
User
644
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CM44-10114-7E
CHAPTER 20 FLASH SERIAL PROGRAMMING CONNECTION
20.4 Example of Minimum Connection to Flash Microcontroller Programmer
(User Power Supply)
MB90495G Series
20.4
Example of Minimum Connection to Flash Microcontroller
Programmer (User Power Supply)
When each pin is set as shown below at programming to flash memory, there is no
need for connections between MD2, MD0, P00 and the flash microcontroller
programmer.
■ Example of Minimum Connection to Flash Microcontroller Programmer (User Power
Supply Used)
Figure 20.4-1 Example of Minimum Connection to the Flash Microcontroller Programmer
(User Power Supply Used)
AF220/AF210/AF120/AF110
flash microcontroller
programmer
User system
1 for serial programming
10 kΩ
MB90F497G/F498G
MD2
1 for serial programming
10 kΩ
10 kΩ
MD1
10 kΩ
10 kΩ
MD0
0 for serial programming
10 kΩ
X0
1MHz to 16MHz
X1
10 kΩ
P00
0 for serial programming
User circuit
1 for serial programming
10 kΩ
P01
User circuit
C
Connector
DX10-28S
0.1 μF
10 kΩ
/TRES
(5)
RST
TTXD
(13)
SIN1
TRXD
(27)
SOT1
(6)
SCK1
TCK
TVcc
(2)
GND
(7, 8,
14, 15,
21, 22,
1,28)
Vcc
User power supply
Vss
14 pin
Pins 3, 4, 9, 10, 11, 12, 16, 17, 18, 19, 20, 23, 24, 25
and 26 are OPEN
DX10-28S: Right-angle type
1 pin
DX10-28S
28 pin
15 pin
Connector (made by Hirose Electric Co., Ltd.) pin assignment
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CHAPTER 20 FLASH SERIAL PROGRAMMING CONNECTION
20.4 Example of Minimum Connection to Flash Microcontroller Programmer
(User Power Supply)
Note:
MB90495G Series
• Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the controller shown in the
figure above is required. The /TICS signal of the flash microcontroller programmer can be used to
disconnect the user circuit during serial programming.
• Connect the AF220/AF210/AF120/AF110 while the user power is off.
Figure 20.4-2 Control circuit
AF220/AF210/AF120/AF110
programming control pin
MB90F497G/F498G
programming control pin
10 kΩ
AF220/AF210/AF120/AF110
/TICS pin
User
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CM44-10114-7E
CHAPTER 20 FLASH SERIAL PROGRAMMING CONNECTION
20.5 Example of Minimum Connection to Flash Microcontroller Programmer
(Writer Power Supply)
MB90495G Series
20.5
Example of Minimum Connection to Flash Microcontroller
Programmer (Writer Power Supply)
When each pin is set as shown below at programming to flash memory, there is no
need for connections between MD2, MD0, P00 and the flash microcontroller
programmer.
■ Example of Minimum Connection to Flash Microcontroller Programmer (Power
Supplied from Flash Microcontroller Programmer)
Figure 20.5-1 Example of Minimum Connection to the Flash Microcontroller Programmer (Power Supplied
from Flash Microcontroller Programmer)
AF220/AF210/AF120/AF110
flash microcontroller
programmer
User system
1 for serial programming
10 kΩ
MB90F497G/F498G
MD2
1 for serial programming
10 kΩ
10 kΩ
MD1
10 kΩ
10 kΩ
MD0
0 for serial programming
10 kΩ
X0
1MHz to 16MHz
X1
10 kΩ
P00
0 for serial programming
User circuit
1 for serial programming
10 kΩ
P01
User circuit
C
Connector
DX10-28S
0.1 μF
10 kΩ
/TRES
(5)
RST
TTXD
(13)
SIN1
TRXD
(27)
SOT1
TCK
(6)
(2)
(3)
(16)
SCK1
TVcc
Vcc
(7, 8,
14, 15,
21,22,
1, 28)
GND
Vss
14 pin
Pins 4, 9, 10, 11, 12, 17, 18, 19, 20, 23, 24, 25
and 26 are OPEN
DX10-28S: Right-angle type
1 pin
DX10-28S
28 pin
15 pin
Connector (made by Hirose Electric Co., Ltd.) pin assignment
CM44-10114-7E
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CHAPTER 20 FLASH SERIAL PROGRAMMING CONNECTION
20.5 Example of Minimum Connection to Flash Microcontroller Programmer
(Writer Power Supply)
Note:
MB90495G Series
• Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the controller shown in the
figure above is required. The /TICS signal of the flash microcontroller programmer can be used to
disconnect the user circuit during serial programming.
• Connect the AF220/AF210/AF120/AF110 while the user power is off.
• When supplying programming power from AF220/AF210/AF120/AF110, do not short-circuit the
programming power and user power.
Figure 20.5-2 Control circuit
AF220/AF210/AF120/AF110
programming control pin
MB90F497G/F498G
programming control pin
10 kΩ
AF220/AF210/AF120/AF110
/TICS pin
User
648
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
APPENDIX
The appendices provide the I/O map and outline of
instructions.
APPENDIX A Instructions
APPENDIX B Register Index
APPENDIX C Pin Function Index
APPENDIX D Interrupt Vector Index
CM44-10114-7E
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APPENDIX
APPENDIX A Instructions
MB90495G Series
APPENDIX A Instructions
APPENDIX A describes the instructions used by the F2MC-16LX.
A.1 Instruction Types
A.2 Addressing
A.3 Direct Addressing
A.4 Indirect Addressing
A.5 Execution Cycle Count
A.6 Effective address field
A.7 How to Read the Instruction List
A.8 F2MC-16LX Instruction List
A.9 Instruction Map
Code: CM44-00202-4E
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APPENDIX
APPENDIX A Instructions
MB90495G Series
A.1
Instruction Types
The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an
effective address field of each instruction or using the instruction code itself.
■ Instruction Types
The F2MC-16LX supports the following 351 types of instructions:
•
41 transfer instructions (byte)
•
38 transfer instructions (word or long word)
•
42 addition/subtraction instructions (byte, word, or long word)
•
12 increment/decrement instructions (byte, word, or long word)
•
11 comparison instructions (byte, word, or long word)
•
11 unsigned multiplication/division instructions (word or long word)
•
11 signed multiplication/division instructions (word or long word)
•
39 logic instructions (byte or word)
•
6 logic instructions (long word)
•
6 sign inversion instructions (byte or word)
•
1 normalization instruction (long word)
•
18 shift instructions (byte, word, or long word)
•
50 branch instructions
•
6 accumulator operation instructions (byte or word)
•
28 other control instructions (byte, word, or long word)
•
21 bit operation instructions
•
10 string instructions
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APPENDIX
APPENDIX A Instructions
A.2
MB90495G Series
Addressing
With the F2MC-16LX, the address format is determined by the instruction effective
address field or the instruction code itself (implied). When the address format is
determined by the instruction code itself, specify an address in accordance with the
instruction code used. Some instructions permit the user to select several types of
addressing.
■ Addressing
The F2MC-16LX supports the following 23 types of addressing:
652
•
Immediate (#imm)
•
Register direct
•
Direct branch address (addr16)
•
Physical direct branch address (addr24)
•
I/O direct (io)
•
Abbreviated direct address (dir)
•
Direct address (addr16)
•
I/O direct bit address (io:bp)
•
Abbreviated direct bit address (dir:bp)
•
Direct bit address (addr16:bp)
•
Vector address (#vct)
•
Register indirect (@RWj j = 0 to 3)
•
Register indirect with post increment (@RWj+ j = 0 to 3)
•
Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
•
Long register indirect with displacement (@RLi + disp8 i = 0 to 3)
•
Program counter indirect with displacement (@PC + disp16)
•
Register indirect with base index (@RW0 + RW7, @RW1 + RW7)
•
Program counter relative branch address (rel)
•
Register list (rlst)
•
Accumulator indirect (@A)
•
Accumulator indirect branch address (@A)
•
Indirectly-specified branch address (@ear)
•
Indirectly-specified branch address (@eam)
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
APPENDIX
APPENDIX A Instructions
MB90495G Series
■ Effective Address Field
Table A.2-1 lists the address formats specified by the effective address field.
Table A.2-1 Effective Address Field
Code
Representation
00
R0
RW0
RL0
01
R1
RW1
(RL0)
02
R2
RW2
RL1
03
R3
RW3
(RL1)
04
R4
RW4
RL2
05
R5
RW5
(RL2)
06
R6
RW6
RL3
07
R7
RW7
(RL3)
08
@RW0
09
@RW1
Address format
Default bank
Register direct: Individual parts correspond to the
byte, word, and long word types in order from the
left.
None
DTB
DTB
Register indirect
0A
@RW2
ADB
0B
@RW3
SPB
0C
@RW0+
DTB
0D
@RW1+
DTB
Register indirect with post increment
0E
@RW2+
ADB
0F
@RW3+
SPB
10
@RW0+disp8
DTB
11
@RW1+disp8
DTB
Register indirect with 8-bit displacement
12
@RW2+disp8
ADB
13
@RW3+disp8
SPB
14
@RW4+disp8
DTB
15
@RW5+disp8
DTB
Register indirect with 8-bit displacement
16
@RW6+disp8
ADB
17
@RW7+disp8
SPB
18
@RW0+disp16
DTB
19
@RW1+disp16
DTB
Register indirect with 16-bit displacement
CM44-10114-7E
1A
@RW2+disp16
ADB
1B
@RW3+disp16
SPB
1C
@RW0+RW7
Register indirect with index
DTB
1D
@RW1+RW7
Register indirect with index
DTB
1E
@PC+disp16
PC indirect with 16-bit displacement
PCB
1F
addr16
Direct address
DTB
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APPENDIX
APPENDIX A Instructions
A.3
MB90495G Series
Direct Addressing
An operand value, register, or address is specified explicitly in direct addressing mode.
■ Direct Addressing
● Immediate addressing (#imm)
Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32).
Figure A.3-1 Example of Immediate Addressing (#imm)
MOVW A, #01212H (This instruction stores the operand value in A.)
Before execution
A 2233
4455
After execution
A 4455
1 2 1 2 (Some instructions transfer AL to AH.)
● Register direct addressing
Specify a register explicitly as an operand. Table A.3-1 lists the registers that can be specified. Figure A.3-2
shows an example of register direct addressing.
Table A.3-1 Direct Addressing Registers
General-purpose register
Special-purpose register
Byte
R0, R1, R2, R3, R4, R5, R6, R7
Word
RW0, RW1, RW2, RW3, RW4, RW5, RW6,
RW7
Long word
RL0, RL1, RL2, RL3
Accumulator
A, AL
Pointer
SP *
Bank
PCB, DTB, USB, SSB, ADB
Page
DPR
Control
PS, CCR, RP, ILM
*: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on
the value of the stack flag (S) in the condition code register (CCR). For branch instructions, the
program counter (PC) is not specified in an instruction operand but is specified implicitly.
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CM44-10114-7E
APPENDIX
APPENDIX A Instructions
MB90495G Series
Figure A.3-2 Example of Register Direct Addressing
MOV R0, A (This instruction transfers the eight low-order bits of A to the generalpurpose register R0.)
Before execution
A 0716
2534
Memory space
R0
After execution
A 0716
2564
??
Memory space
R0
34
● Direct branch addressing (addr16)
Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which
indicates the branch destination in the logical address space. Direct branch addressing is used for an
unconditional branch, subroutine call, or software interrupt instruction. Bit23 to bit16 of the address are
specified by the program counter bank register (PCB).
Figure A.3-3 Example of Direct Branch Addressing (addr16)
JMP 3B20H (This instruction causes an unconditional branch by direct branch
addressing in a bank.)
Before execution
After execution
CM44-10114-7E
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
62
4F3C21H
20
4F3C22H
3B
FUJITSU SEMICONDUCTOR LIMITED
JMP 3B20H
655
APPENDIX
APPENDIX A Instructions
MB90495G Series
● Physical direct branch addressing (addr24)
Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical
direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction.
Figure A.3-4 Example of Direct Branch Addressing (addr24)
JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit
addressing.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 3 3
Memory space
333B20H
Next instruction
4F3C20H
63
4F3C21H
20
4F3C22H
3B
4F3C23H
33
JMPP 333B20H
● I/O direct addressing (io)
Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the
physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB)
and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an
instruction using I/O direct addressing.
Figure A.3-5 Example of I/O Direct Addressing (io)
MOVW A, I:0C0H (This instruction reads data by I/O direct addressing and stores it in A.)
Before execution
After execution
A 0716
2534
Memory space
0000C0H
EE
0000C1H
FF
A 2534 FFEE
Note : "I:" is Addressing Specifier that shows the I/O Direct Addressing.
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FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
APPENDIX
APPENDIX A Instructions
MB90495G Series
● Abbreviated direct addressing (dir)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB).
Figure A.3-6 Example of Abbreviated Direct Addressing (dir)
MOV S:20H, A (This instruction writes the contents of the eight low-order bits of A in
abbreviated direct addressing mode.)
Before execution
A 4455
DPR 6 6
After execution
A 4455
DPR 6 6
1212
DTB 7 7
Memory space
776620H
1212
DTB 7 7
??
Memory space
776620H
12
Note : "S:" is Addressing Specifier that shows the Abbreviated Direct Addressing.
● Direct addressing (addr16)
Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are
specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for
this mode of addressing.
Figure A.3-7 Example of Direct Addressing (addr16)
MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.)
Before execution
After execution
CM44-10114-7E
A 2020
A AABB
AABB
0123
DTB 5 5
Memory space
553B21H
01
553B20H
23
DTB 5 5
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APPENDIX
APPENDIX A Instructions
MB90495G Series
● I/O direct bit addressing (io:bp)
Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp",
where the larger number indicates the most significant bit (MSB) and the lower number indicates the least
significant bit (LSB).
Figure A.3-8 Example of I/O Direct Bit Addressing (io:bp)
SETB I:0C1H:0 (This instruction sets bits by I/O direct bit addressing.)
Memory space
Before execution
00
0000C1H
Memory space
After execution
0000C1H
01
Note : "I:" is Addressing Specifier that shows the I/O Direct Addressing.
● Abbreviated direct bit addressing (dir:bp)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure A.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp)
SETB S:10H:0 (This instruction sets bits by abbreviated direct bit addressing.)
Memory space
Before execution
DTB 5 5
DPR 6 6
556610H
00
Memory space
After execution
DTB 5 5
DPR 6 6
01
556610H
Note : "S:" is Addressing Specifier that shows the Abbreviated Direct Addressing.
● Direct bit addressing (addr16:bp)
Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure A.3-10 Example of Direct Bit Addressing (addr16:bp)
SETB 2222H : 0 (This instruction sets bits by direct bit addressing.)
Memory space
Before execution
DTB 5 5
552222H
00
Memory space
After execution
658
DTB 5 5
552222H
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01
CM44-10114-7E
APPENDIX
APPENDIX A Instructions
MB90495G Series
● Vector Addressing (#vct)
Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector
numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction.
Figure A.3-11 Example of Vector Addressing (#vct)
CALLV #15 (This instruction causes a branch to the address indicated by the interrupt
vector specified in an operand.)
Before execution
PC 0 0 0 0
Memory space
PCB F F
After execution
FFC000H
EF
FFFFE0H
00
FFFFE1H
D0
CALLV #15
PC D 0 0 0
PCB F F
Table A.3-2 CALLV Vector List
Instruction
Vector address L *
Vector address H *
CALLV #0
XXFFFEH
XXFFFFH
CALLV #1
XXFFFCH
XXFFFDH
CALLV #2
XXFFFAH
XXFFFBH
CALLV #3
XXFFF8H
XXFFF9H
CALLV #4
XXFFF6H
XXFFF7H
CALLV #5
XXFFF4H
XXFFF5H
CALLV #6
XXFFF2H
XXFFF3H
CALLV #7
XXFFF0H
XXFFF1H
CALLV #8
XXFFEEH
XXFFEFH
CALLV #9
XXFFECH
XXFFEDH
CALLV #10
XXFFEAH
XXFFEBH
CALLV #11
XXFFE8H
XXFFE9H
CALLV #12
XXFFE6H
XXFFE7H
CALLV #13
XXFFE4H
XXFFE5H
CALLV #14
XXFFE2H
XXFFE3H
CALLV #15
XXFFE0H
XXFFE1H
* : XX is replaced by the value of the program counter bank register (PCB).
Note:
When the program counter bank register (PCB) is FFH, the vector area overlaps the vector area of
INT #vct8 (#0 to #7). Use vector addressing carefully (see Table A.3-2).
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FUJITSU SEMICONDUCTOR LIMITED
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APPENDIX
APPENDIX A Instructions
A.4
MB90495G Series
Indirect Addressing
In indirect addressing mode, an address is specified indirectly by the address data of an
operand.
■ Indirect Addressing
● Register indirect addressing (@RWj j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to
23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register
(SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when
RW2 is used.
Figure A.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3)
MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores
it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 0 F
DTB 7 8
● Register indirect addressing with post increment (@RWj+ j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. After operand
operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word).
Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system
stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank
register (ADB) when RW2 is used.
If the post increment results in the address of the register that specifies the increment, the incremented
value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to
writing by an instruction and, therefore, the register that would be incremented becomes write data.
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FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
APPENDIX
APPENDIX A Instructions
MB90495G Series
Figure A.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3)
MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post
increment and stores it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 1 1
DTB 7 8
● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
Memory is accessed using the address obtained by adding an offset to the contents of general-purpose
register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric
values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or
RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is
used, or additional data bank register (ADB) when RW2 or RW6 is used.
Figure A.4-3 Example of Register Indirect Addressing with Offset
(@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+10H)
RW1 D 3 0 F
After execution
78D31FH
EE
78D320H
FF
A 2534 FFEE
RW1 D 3 0 F
CM44-10114-7E
DTB 7 8
Memory space
DTB 7 8
FUJITSU SEMICONDUCTOR LIMITED
661
APPENDIX
APPENDIX A Instructions
MB90495G Series
● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the
contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value.
Figure A.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3)
MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+25H)
RL2 F 3 8 2
After execution
4B02
Memory space
824B27H
EE
824B28H
FF
A 2534 FFEE
RL2 F 3 8 2
4B02
● Program counter indirect addressing with offset (@PC + disp16)
Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one
word long. Address bits 16 to 23 are specified by the program counter bank register (PCB). Note that the
operand address of each of the following instructions is not deemed to be (next instruction address +
disp16):
•
DBNZ eam, rel
•
DWBNZ eam, rel
•
CBNE eam, #imm8, rel
•
CWBNE eam, #imm16, rel
•
MOV eam, #imm8
•
MOVW eam, #imm16
Figure A.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16)
MOVW A, @PC+20H (This instruction reads data by program counter indirect
addressing with an offset and stores it in A.)
Before execution
A 0716
2534
Memory space
PCB C 5 PC 4 5 5 6
After execution
A 2534
FFEE
PCB C 5 PC 4 5 5 A
662
+4
C54556H
73
C54557H
9E
C54558H
20
C54559H
00
MOVW
A, @PC+20H
C5455AH
.
.
.
+20H
C5457AH
EE
C5457BH
FF
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
APPENDIX
APPENDIX A Instructions
MB90495G Series
● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7)
Memory is accessed using the address determined by adding RW0 or RW1 to the contents of generalpurpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB).
Figure A.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7)
MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with
a base index and stores it in A.)
Before execution
A 0716
RW1 D 3 0 F
WR7 0 1 0 1
After execution
A 2534
RW1 D 3 0 F
2534
+
DTB 7 8
Memory space
78D410H
EE
78D411H
FF
FFEE
DTB 7 8
WR7 0 1 0 1
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
663
APPENDIX
APPENDIX A Instructions
MB90495G Series
● Program counter relative branch addressing (rel)
The address of the branch destination is a value determined by adding an 8-bit offset to the program
counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is
not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte
bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to
23 are indicated by the program counter bank register (PCB).
Figure A.4-7 Example of Program Counter Relative Branch Addressing (rel)
BRA 3C32H (This instruction causes an unconditional relative branch.)
Before execution
After execution
PC 3 C 2 0
PC 3 C 3 2
PCB 4 F
PCB 4 F
Memory space
4F3C32H
Next instruction
4F3C21H
10
4F3C20H
60
BRA 3C32H
● Register list (rlst)
Specify a register to be pushed onto or popped from a stack.
Figure A.4-8 Configuration of the Register List
MSB
LSB
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
A register is selected when the corresponding bit is 1 and deselected when the bit is 0.
664
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
APPENDIX
APPENDIX A Instructions
MB90495G Series
Figure A.4-9 Example of Register List (rlst)
POPW RW0, RW4 (This instruction transfers memory data indicated by the SP to
multiple word registers indicated by the register list.)
SP
34FA
SP
34FE
RW0
×× ××
RW0
02 01
RW1
×× ××
RW1
×× ××
RW2
×× ××
RW2
×× ××
RW3
×× ××
RW3
×× ××
RW4
×× ××
RW4
04 03
RW5
×× ××
RW5
×× ××
RW6
×× ××
RW6
×× ××
RW7
×× ××
RW7
×× ××
Memory space
SP
Memory space
01
34FAH
01
34FAH
02
34FBH
02
34FBH
03
34FCH
03
34FCH
04
34FDH
04
34FDH
34FEH
SP
Before execution
34FEH
After execution
● Accumulator indirect addressing (@A)
Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the
accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB).
Figure A.4-10 Example of Accumulator Indirect Addressing (@A)
MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.)
Before execution
A
0716
2534
DTB B B
After execution
A
0716
Memory space
BB2534H
EE
BB2535H
FF
FFEE
DTB B B
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
665
APPENDIX
APPENDIX A Instructions
MB90495G Series
● Accumulator indirect branch addressing (@A)
The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the
accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are
specified by the program counter bank register (PCB). For the Jump Context (JCTX) instruction, however,
address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for
unconditional branch instructions.
Figure A.4-11 Example of Accumulator Indirect Branch Addressing (@A)
JMP @A (This instruction causes an unconditional branch by accumulator indirect
branch addressing.)
Before execution
PC 3 C 2 0
A 6677
After execution
PC 3 B 2 0
A 6677
PCB 4 F
3B20
Memory space
4F3B20H
Next instruction
4F3C20H
61
JMP @A
PCB 4 F
3B20
● Indirect specification branch addressing (@ear)
The address of the branch destination is the word data at the address indicated by ear.
Figure A.4-12 Example of Indirect Specification Branch Addressing (@ear)
JMP @@RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
After execution
666
PC 3 C 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
PC 3 B 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
Memory space
217F48H
20
217F49H
3B
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
08
FUJITSU SEMICONDUCTOR LIMITED
JMP @@RW0
CM44-10114-7E
APPENDIX
APPENDIX A Instructions
MB90495G Series
● Indirect specification branch addressing (@eam)
The address of the branch destination is the word data at the address indicated by eam.
Figure A.4-13 Example of Indirect Specification Branch Addressing (@eam)
JMP @RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
PC 3 C 2 0
PCB 4 F
RW0 3 B 2 0
After execution
PC 3 B 2 0
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
00
JMP @RW0
RW0 3 B 2 0
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
667
APPENDIX
APPENDIX A Instructions
A.5
MB90495G Series
Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is
obtained by adding the number of cycles required for each instruction, "correction
value" determined by the condition, and the number of cycles for instruction fetch.
■ Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is obtained by adding the
number of cycles required for each instruction, "correction value" determined by the condition, and the
number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal
ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments.
Therefore, intervening in data access increases the execution cycle count.
Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the
program fetches every byte of an instruction being executed. Therefore, intervening in data access increases
the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register,
internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the
cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register.
Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add
the "access count x cycle count for the halt" as a correction value to the normal execution count.
668
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
APPENDIX
APPENDIX A Instructions
MB90495G Series
■ Calculating the Execution Cycle Count
Table A.5-1 lists execution cycle counts and Table A.5-2 and Table A.5-3 summarize correction value data.
Table A.5-1 Execution Cycle Counts in Each Addressing Mode
(a) *
Code
Operand
00H
|
07H
Ri
Rwi
RLi
08H
|
0BH
Execution cycle count in
each addressing mode
Register access count in
each addressing mode
See the instruction list.
See the instruction list.
@RWj
2
1
0CH
|
0FH
@RWj+
4
2
10H
|
17H
@RWi+disp8
2
1
18H
|
1BH
@RWi+disp16
2
1
1CH
1DH
1EH
1FH
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
4
4
2
1
2
2
0
0
*: (a) is used for ~ (cycle count) and B (correction value) in "A.8 F2MC-16LX Instruction List".
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
669
APPENDIX
APPENDIX A Instructions
MB90495G Series
Table A.5-2 Cycle Count Correction Values for Counting Execution Cycles
(b) byte *
Operand
(c) word *
(d) long *
Cycle
count
Access
count
Cycle
count
Access
count
Cycle
count
Access
count
Internal register
+0
1
+0
1
+0
2
Internal memory
Even address
+0
1
+0
1
+0
2
Internal memory
Odd address
+0
1
+2
2
+4
4
External data bus
16-bit even address
+1
1
+1
1
+2
2
External data bus
16-bit odd address
+1
1
+4
2
+8
4
External data bus
8-bits
+1
1
+4
2
+8
4
*: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in "A.8 F2MC-16LX Instruction
List".
Note:
When an external data bus is used, the cycle counts during which an instruction is made to wait by
ready input or automatic ready must also be added.
Table A.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
-
+2
External data bus 16-bits
-
+3
External data bus 8-bits
+3
-
Notes:
• When an external data bus is used, the cycle counts during which an instruction is made to wait
by ready input or automatic ready must also be added.
• Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the
correction values to calculate the worst case.
670
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
APPENDIX
APPENDIX A Instructions
MB90495G Series
A.6
Effective address field
Table A.6-1 shows the effective address field.
■ Effective Address Field
Table A.6-1 Effective Address Field (1/2)
Code
CM44-10114-7E
Representation
Address format
Byte count of
extended
address part *
Register direct: Individual parts correspond to
the byte, word, and long word types in order
from the left.
-
Register indirect
0
Register indirect with post increment
0
Register indirect with 8-bit displacement
1
Register indirect with 16-bit displacement
2
00H
R0
RW0
RL0
01H
R1
RW1
(RL0)
02H
R2
RW2
RL1
03H
R3
RW3
(RL1)
04H
R4
RW4
RL2
05H
R5
RW5
(RL2)
06H
R6
RW6
RL3
07H
R7
RW7
(RL3)
08H
@RW0
09H
@RW1
0AH
@RW2
0BH
@RW3
0CH
@RW0+
0DH
@RW1+
0EH
@RW2+
0FH
@RW3+
10H
@RW0+disp8
11H
@RW1+disp8
12H
@RW2+disp8
13H
@RW3+disp8
14H
@RW4+disp8
15H
@RW5+disp8
16H
@RW6+disp8
17H
@RW7+disp8
18H
@RW0+disp16
19H
@RW1+disp16
1AH
@RW2+disp16
1BH
@RW3+disp16
1CH
@RW0+RW7
Register indirect with index
0
1DH
@RW1+RW7
Register indirect with index
0
1EH
@PC+disp16
PC indirect with 16-bit displacement
2
FUJITSU SEMICONDUCTOR LIMITED
671
APPENDIX
APPENDIX A Instructions
MB90495G Series
Table A.6-1 Effective Address Field (1/2)
Code
1FH
Representation
addr16
Address format
Byte count of
extended
address part *
Direct address
2
*1: Each byte count of the extended address part applies to + in the # (byte count) column in "A.8 F
Instruction List".
672
FUJITSU SEMICONDUCTOR LIMITED
2MC-16LX
CM44-10114-7E
APPENDIX
APPENDIX A Instructions
MB90495G Series
A.7
How to Read the Instruction List
Table A.7-1 describes the items used in "A.8 F2MC-16LX Instruction List", and Table
A.7-2 describes the symbols used in the same list.
■ Description of Instruction Presentation Items and Symbols
Table A.7-1 Description of Items in the Instruction List (1/2)
Item
Mnemonic
Uppercase, symbol: Represented as is in the assembler.
Lowercase: Rewritten in the assembler.
Number of following lowercase: Indicates bit length in the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
See Table A.2-1 for the alphabetical letters in items.
RG
B
Operation
CM44-10114-7E
Description
Indicates the number of times a register access is performed during instruction
execution.
The number is used to calculate the correction value for CPU intermittent
operation.
Indicates the correction value used to calculate the actual number of cycles during
instruction execution.
The actual number of cycles during instruction execution can be determined by
adding the value in the ~ column to this value.
Indicates the instruction operation.
LH
Indicates the special operation for bit15 to bit08 of the accumulator.
Z: Transfers 0.
X: Transfers after sign extension.
-: No transfer
AH
Indicates the special operation for the 16 high-order bits of the accumulator.
*: Transfers from AL to AH.
-: No transfer
Z: Transfers 00 to AH.
X: Transfers 00H or FFH to AH after AL sign extension.
FUJITSU SEMICONDUCTOR LIMITED
673
APPENDIX
APPENDIX A Instructions
MB90495G Series
Table A.7-1 Description of Items in the Instruction List (1/2)
Item
Description
I
Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N
(negative), Z (zero), V (overflow), C (carry).
*: Changes upon instruction execution.
-: No change
S: Set upon instruction execution.
R: Reset upon instruction execution.
S
T
N
Z
V
C
RMW
Indicates whether the instruction is a Read Modify Write instruction (reading data
from memory by the I instruction and writing the result to memory).
*: Read Modify Write instruction
-: Not Read Modify Write instruction
Note:
Cannot be used for an address that has different meanings between read and
write operations.
Table A.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
A
674
Explanation
The bit length used varies depending on the 32-bit accumulator instruction.
Byte: Low-order 8 bits of byte AL
Word: 16 bits of word AL
Long word: 32 bits of AL and AH
AH
16 high-order bits of A
AL
16 low-order bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
program counter bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
APPENDIX
APPENDIX A Instructions
MB90495G Series
Table A.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
Ri
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
Direct addressing
addr24
Physical direct addressing
ad24 0-15
Bit0 to bit15 of addr24
ad24 16-23
Bit16 to bit23 of addr24
io
I/O area (000000H to 0000FFH)
#imm4
4-bit immediate data
#imm8
8-bit immediate data
#imm16
16-bit immediate data
#imm32
32-bit immediate data
ext (imm8)
16-bit data obtained by sign extension of 8-bit immediate data
disp8
8-bit displacement
disp16
16-bit displacement
bp
CM44-10114-7E
Explanation
Bit offset
vct4
Vector number (0 to 15)
vct8
Vector number (0 to 255)
( )b
Bit address
rel
PC relative branch
ear
Effective addressing (code 00H to 07H)
eam
Effective addressing (code 08H to 1FH)
rlst
Register list
FUJITSU SEMICONDUCTOR LIMITED
675
APPENDIX
APPENDIX A Instructions
A.8
MB90495G Series
F2MC-16LX Instruction List
Table A.8-1 to Table A.8-18 list the instructions used by the F2MC-16LX.
■ F2MC-16LX Instruction List
Table A.8-1 41 Transfer Instructions (Byte)
Mnemonic
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
XCH
XCH
XCH
XCH
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RLi+disp8
A,#imm4
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
Ri,A
ear,A
eam,A
io,A
@RLi+disp8,A
Ri,ear
Ri,eam
ear,Ri
eam,Ri
Ri,#imm8
io,#imm8
dir,#imm8
ear,#imm8
eam,#imm8
@AL,AH
A,ear
A,eam
Ri,ear
Ri,eam
#
~
RG
B
2
3
1
2
2+
2
2
2
3
1
2
3
1
2
2+
2
2
2
2
3
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
2
2+
2
2+
3
4
2
2
3 + (a)
3
2
3
10
1
3
4
2
2
3 + (a)
3
2
3
5
10
3
4
2
2
3 + (a)
3
10
3
4 + (a)
4
5 + (a)
2
5
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
0
0
1
1
0
0
0
0
2
0
0
0
1
1
0
0
0
0
1
2
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
2
0
4
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
0
2 × (b)
0
2 × (b)
Operation
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi)+disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
Z
Z
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
Note:
See Table A.5-1 and Table A.5-2 for information on (a) and (b) in the table.
676
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
APPENDIX
APPENDIX A Instructions
MB90495G Series
Table A.8-2 38 Transfer Instructions (Word, Long Word)
Mnemonic
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW
XCHW
XCHW
MOVL
MOVL
MOVL
MOVL
MOVL
A,dir
A,addr16
A,SP
A,RWi
A,ear
A,eam
A,io
A,@A
A,#imm16
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
SP,A
RWi,A
ear,A
eam,A
io,A
@RWi+disp8,A
@RLi+disp8,A
RWi,ear
RWi,eam
ear,RWi
eam,RWi
RWi,#imm16
io,#imm16
ear,#imm16
eam,#imm16
@AL,AH
A,ear
A,eam
RWi, ear
RWi, eam
A,ear
A,eam
A,#imm32
ear,A
eam,A
#
~
RG
B
2
3
1
1
2
2+
2
2
3
2
3
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
2
2
2+
2
2+
2
2+
5
2
2+
3
4
1
2
2
3 + (a)
3
3
2
5
10
3
4
1
2
2
3 + (a)
3
5
10
3
4 + (a)
4
5 + (a)
2
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
4
5 + (a)
3
4
5 + (a)
0
0
0
1
1
0
0
0
0
1
2
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
0
2
0
4
2
2
0
0
2
0
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
0
(c)
0
(c)
0
(c)
0
(c)
(c)
0
2 × (c)
0
2 × (c)
0
(d)
0
0
(d)
Operation
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi)+disp8)
word (A) ← ((RLi)+disp8)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
word ((RWi)+disp8) ← (A)
word ((RLi)+disp8) ← (A)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
word (ear) ← imm16
word (eam) ← imm16
word ((A)) ← (AH)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
long (ear) ← (A)
long(eam) ← (A)
LH
AH
I
S
T
N
Z
V
C
RMW
-
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
Note:
See Table A.5-1 and Table A.5-2 for information on (a), (c), and (d) in the table.
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
677
APPENDIX
APPENDIX A Instructions
MB90495G Series
Table A.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
ADDW
ADDW
ADDW
ADDW
ADDW
ADDW
ADDCW
ADDCW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBCW
SUBCW
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A,ear
A,eam
A,#imm32
A,ear
A,eam
A,#imm32
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
2+
5
2
2+
5
2
3
4+(a)
2
3
5+(a)
3
4+(a)
2
3
4+(a)
2
3
5+(a)
3
4+(a)
6
7+(a)
4
6
7+(a)
4
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
2
0
0
2
0
0
0
0
(c)
0
0
2 × (c)
0
(c)
0
0
(c)
0
0
2 × (c)
0
(c)
0
(d)
0
0
(d)
0
Operation
byte (A) ← (A) + imm8
byte (A) ← (A) + (dir)
byte (A) ← (A) + (ear)
byte (A) ← (A) + (eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear)+ (C)
byte (A) ← (A) + (eam)+ (C)
byte (A) ← (AH) + (AL) + (C)
(decimal)
byte (A) ← (A) - imm8
byte (A) ← (A) - (dir)
byte (A) ← (A) - (ear)
byte (A) ← (A) - (eam)
byte (ear) ← (ear) - (A)
byte (eam) ← (eam) - (A)
byte (A) ← (AH) - (AL) - (C)
byte (A) ← (A) - (ear) - (C)
byte (A) ← (A) - (eam) - (C)
byte (A) ← (AH) - (AL) - (C)
(decimal)
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) - (AL)
word (A) ← (A) - (ear)
word (A) ← (A) - (eam)
word (A) ← (A) - imm16
word (ear) ← (ear) - (A)
word (eam) ← (eam) - (A)
word (A) ← (A) - (ear) - (C)
word (A) ← (A) - (eam) - (C)
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
long (A) ← (A) - (ear)
long (A) ← (A) - (eam)
long (A) ← (A) - imm32
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (d) in the table.
678
FUJITSU SEMICONDUCTOR LIMITED
CM44-10114-7E
APPENDIX
APPENDIX A Instructions
MB90495G Series
Table A.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
INC
ear
2
3
2
0
INC
eam
2+
5+(a)
0
2 × (b)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
byte (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
byte (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DEC
ear
2
3
2
0
byte (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
DEC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
INCW
ear
2
3
2
0
word (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
INCW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DECW
ear
2
3
2
0
DECW
eam
2+
5+(a)
0
2 × (c)
INCL
ear
2
7
4
0
INCL
eam
2+
9+(a)
0
2 × (d)
DECL
ear
2
7
4
0
DECL
eam
2+
9+(a)
0
2 × (d)
word (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
word (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (d) in the table.
Table A.8-5 11 Compare Instructions (Byte, Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
CMP
Mnemonic
A
1
1
0
0
byte (AH) - (AL)
Operation
-
-
-
-
-
*
*
*
*
-
CMP
A,ear
2
2
1
0
byte (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMP
A,eam
2+
3+(a)
0
(b)
byte (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMP
A,#imm8
2
2
0
0
byte (A) - imm8
-
-
-
-
-
*
*
*
*
-
CMPW
A
1
1
0
0
word (AH) - (AL)
-
-
-
-
-
*
*
*
*
-
CMPW
A,ear
2
2
1
0
word (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPW
A,eam
2+
3+(a)
0
(c)
word (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPW
A,#imm16
3
2
0
0
word (A) - imm16
-
-
-
-
-
*
*
*
*
-
CMPL
A,ear
2
6
2
0
long (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPL
A,eam
2+
7+(a)
0
(d)
long (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPL
A,#imm32
5
3
0
0
long (A) - imm32
-
-
-
-
-
*
*
*
*
-
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (d) in the table.
CM44-10114-7E
FUJITSU SEMICONDUCTOR LIMITED
679
APPENDIX
APPENDIX A Instructions
MB90495G Series
Table A.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIVU
A
1
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
-
-
-
-
-
-
-
*
*
-
DIVU
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
-
-
-
-
-
-
-
*
*
-
DIVU
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MULU
A
1
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
MULU
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,eam
2+
*10
0
(b)
byte (A)