The following document contains information on Cypress products. CM44-10116-3E FUJITSU MICROELECTRONICS CONTROLLER MANUAL 2 F MC-16LX 16-BIT MICROCONTROLLER MB90M405 Series HARDWARE MANUAL 2 F MC-16LX 16-BIT MICROCONTROLLER MB90M405 Series HARDWARE MANUAL The information for microcontroller supports is shown in the following homepage. Be sure to refer to the "Check Sheet" for the latest cautions on development. "Check Sheet" is seen at the following support page "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development. http://edevice.fujitsu.com/micom/en-support/ FUJITSU MICROELECTRONICS LIMITED PREFACE ■ Objectives and Intended Reader Thank you for purchasing a Fujitsu semiconductor product. The MB90M405 series is a series of general-purpose 16-bit microcontrollers with 60 built-in high-tension-resistant output pins required for fluorescent display control. The MB90M405 series was developed for applications that require the control of a vacuum fluorescent tube panel. This manual, intended for engineers who design products using the MB90M405 series, describes the functions and operations of MB90M405 series products. ■ Trademark F2MC is the abbreviation of FUJITSU Flexible Microcontroller. Embedded Algorithm is a trademark of Advanced Micro Devices Corporation. Other system and product names used in this manual are trademarks of their respective companies or organizations. The symbols TM and ® are sometimes omitted in the text. ■ License Purchase of FUJITSU Ltd, I2C components conveys a license under the Philips I2C Patent Right to use. These components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. i ■ Organization of This Manual This manual consists of the following 24 chapters and an appendix: CHAPTER 1 "OVERVIEW" This chapter summarizes the features and basic specifications of the MB90M405 series of microcontrollers. CHAPTER 2 "CPU" This chapter describes the CPU and the memory space provided by the MB90M405 series CHAPTER 3 "RESETS" This chapter describes resets for the MB90M405 series. CHAPTER 4 "CLOCKS" This chapter describes the clocks used by MB90M405 series. CHAPTER 5 "LOW POWER CONSUMPTION MODE" This chapter describes the low power consumption mode of MB90M405 series. CHAPTER 6 "INTERRUPTS" This chapter explains the interrupts and extended intelligent I/O service (EI2OS) in the MB90M405 series. CHAPTER 7 "SETTING A MODE" This chapter describes the operating modes and the memory access modes of the MB90M405 series. CHAPTER 8 "I/O PORTS" This chapter describes the functions and operations of the MB90M405 series I/O ports. CHAPTER 9 "SERIAL I/O" This chapter describes the functions and operations of the serial I/O unit of the MB90M405 series. CHAPTER 10 "TIMEBASE TIMER" This chapter describes the functions and operation of the timebase timer of the MB90M405 series. CHAPTER 11 "WATCHDOG TIMER" This chapter describes the functions and operations of the watchdog timer of the MB90M405 series. CHAPTER 12 "16-BIT RELOAD TIMER" This chapter describes the functions and operations of the 16-bit reload timer of the MB90M405 series. CHAPTER 13 "16-BIT I/O TIMER" This chapter describes the functions and operations of the 16-bit I/O timer of the MB90M405 series. CHAPTER 14 "UART" This chapter describes the functions and operations of the MB90M405 series UART. CHAPTER 15 "DTP/EXTERNAL INTERRUPT CIRCUIT" This chapter describes the functions and operations of the DTP/external interrupt circuit of the MB90M405 series. ii CHAPTER 16 "I2C INTERFACE" This chapter describes the functions and operations of the I2C interface of the MB90M405 series. CHAPTER 17 "8/10-BIT A/D CONVERTER" This chapter describes the functions and operations of the MB90M405 series 8/10-bit A/D converter. CHAPTER 18 "FL CONTROL CIRCUIT" This chapter explains the functions and operation of the MB90M405 series FL control circuit. CHAPTER 19 "WATCH CLOCK OUTPUT" This chapter describes the functions and operations of MB90M405 series watch clock output. CHAPTER 20 "DELAYED INTERRUPT GENERATOR MODULE" This chapter describes the functions and operation of the MB90M405 series delayed interrupt generator module. CHAPTER 21 "ADDRESS MATCH DETECTION FUNCTION" This chapter describes the address match detection function of the MB90M405 series and its operations. CHAPTER 22 "ROM MIRRORING FUNCTION SELECTION MODULE" This chapter describes the function and operation of the MB90M405 series ROM mirroring function selection module. CHAPTER 23 "1M-BIT FLASH MEMORY" This chapter describes the functions and operations of the MB90M405 series 1M-bit flash memory. CHAPTER 24 "EXAMPLE OF MB90MF408 SERIAL PROGRAMMING CONNECTION" This chapter provides examples of connection for serial programming using the AF220 flash microcomputer programmer manufactured by YDC Corporation. APPENDIX This appendix includes I/O maps, instruction lists, and other information. iii • • • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Copyright ©2001-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved. iv CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 OVERVIEW ................................................................................................... 1 Features ................................................................................................................................................ 2 Product Lineup ...................................................................................................................................... 5 Block Diagram ....................................................................................................................................... 7 Package Dimensions ............................................................................................................................. 8 Pin Assignments .................................................................................................................................... 9 Pin Functions ....................................................................................................................................... 10 I/O Circuit Types .................................................................................................................................. 14 Notes on Handling Devices ................................................................................................................. 16 Clock Supply Map ................................................................................................................................ 19 Low Power Consumption Mode ........................................................................................................... 20 CHAPTER 2 CPU ............................................................................................................. 21 2.1 CPU ..................................................................................................................................................... 22 2.2 Memory Space ..................................................................................................................................... 23 2.3 Memory Maps ...................................................................................................................................... 26 2.4 Addressing ........................................................................................................................................... 28 2.4.1 Address Specification by Linear Addressing ................................................................................. 29 2.4.2 Address Specification by Bank Addressing ................................................................................... 30 2.5 Memory Location of Multibyte Data ..................................................................................................... 32 2.6 Registers .............................................................................................................................................. 34 2.7 Dedicated Registers ............................................................................................................................ 35 2.7.1 Accumulator (A) .............................................................................................................................. 37 2.7.2 Stack Pointers (USP, SSP) ............................................................................................................ 40 2.7.3 Processor Status (PS) .................................................................................................................... 42 2.7.4 Condition Code Register (PS: CCR) ............................................................................................. 43 2.7.5 Register Bank Pointer (PS: RP) .................................................................................................... 45 2.7.6 Interrupt Level Mask Register (PS: ILM) ....................................................................................... 46 2.7.7 Program Counter (PC) .................................................................................................................... 47 2.7.8 Direct Page Register (DPR) ........................................................................................................... 48 2.7.9 Bank Registers (PCB, DTB, USB, SSB, ADB) ............................................................................... 49 2.8 General-Purpose Registers ................................................................................................................. 50 2.9 Prefix Codes ........................................................................................................................................ 52 2.9.1 Bank Select Prefix (PCB, DTB, ADB, SPB) .................................................................................... 53 2.9.2 Common Register Bank Prefix (CMR) ............................................................................................ 55 2.9.3 Flag Change Suppression Prefix (NCC) ......................................................................................... 56 2.9.4 Restrictions on Prefix Codes .......................................................................................................... 57 v CHAPTER 3 3.1 3.2 3.3 3.4 3.5 3.6 CHAPTER 4 4.1 4.2 4.3 4.4 4.5 4.6 RESETS ...................................................................................................... 59 Resets ................................................................................................................................................. Reset Causes and Oscillation Stabilization Wait Time ....................................................................... External Reset Pin .............................................................................................................................. Reset Operation .................................................................................................................................. Reset Cause Bits ................................................................................................................................ Status of Pins in a Reset ..................................................................................................................... CLOCKS ..................................................................................................... 71 Clocks ................................................................................................................................................. Block Diagram of the Clock Generation Block .................................................................................... Clock Selection Register (CKSCR) ..................................................................................................... Clock Mode ......................................................................................................................................... Oscillation Stabilization Wait Time ...................................................................................................... Connection of an Oscillator or an External Clock to the Microcontroller ............................................. CHAPTER 5 82 84 86 89 90 91 93 94 96 98 99 INTERRUPTS ........................................................................................... 101 6.1 Interrupts ........................................................................................................................................... 6.2 Interrupt Causes and Interrupt Vectors ............................................................................................. 6.3 Interrupt Control Registers and Peripheral Functions ....................................................................... 6.3.1 Interrupt Control Registers (ICR00 to ICR15) .............................................................................. 6.3.2 Interrupt Control Register Functions ............................................................................................ 6.4 Hardware Interrupts .......................................................................................................................... 6.4.1 Operation of Hardware Interrupts ............................................................................................... 6.4.2 Processing for Interrupt Operation ............................................................................................... 6.4.3 Procedure for Using Hardware Interrupts .................................................................................... 6.4.4 Multiple Interrupts ........................................................................................................................ 6.4.5 Hardware Interrupt Processing Time ........................................................................................... 6.5 Software Interrupts ............................................................................................................................ 6.6 Interrupt of Extended Intelligent I/O Service (EI2OS) ........................................................................ 6.6.1 Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) .......................................................... 6.6.2 Registers of the Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) ................................ 6.6.3 Operation of the Extended Intelligent I/O Service (EI2OS) ......................................................... 6.6.4 Procedure for Using the Extended Intelligent I/O Service (EI2OS) ............................................. 6.6.5 Processing Time of the Extended Intelligent I/O Service (EI2OS) .............................................. vi 72 73 75 77 79 80 LOW POWER CONSUMPTION MODE ...................................................... 81 5.1 Low Power Consumption Mode .......................................................................................................... 5.2 Block Diagram of the Low Power Consumption Control Circuit .......................................................... 5.3 Low Power Consumption Mode Control Register (LPMCR) ............................................................... 5.4 CPU Intermittent Operation Mode ....................................................................................................... 5.5 Standby Mode ..................................................................................................................................... 5.5.1 Sleep Mode .................................................................................................................................... 5.5.2 Timebase Timer Mode ................................................................................................................... 5.5.3 Stop Mode ..................................................................................................................................... 5.6 Status Change Diagram ...................................................................................................................... 5.7 Pin Status in Standby Mode and during Reset ................................................................................... 5.8 Usage Notes on Low Power Consumption Mode ............................................................................... CHAPTER 6 60 62 63 64 66 69 102 104 106 108 110 113 116 118 119 121 123 125 127 129 131 134 135 136 6.7 6.8 6.9 Exception Processing Interrupt .......................................................................................................... 139 Stack Operations for Interrupt Processing ......................................................................................... 140 Sample Programs for Interrupt Processing ........................................................................................ 142 CHAPTER 7 7.1 7.2 7.3 SETTING A MODE .................................................................................... 147 Setting a Mode .................................................................................................................................. 148 Mode Pins (MD2 to MD0) .................................................................................................................. 149 Mode Data ......................................................................................................................................... 150 CHAPTER 8 I/O PORTS ................................................................................................. 153 8.1 Overview of I/O Ports ......................................................................................................................... 154 8.2 I/O Port Registers .............................................................................................................................. 156 8.3 Port 8 ................................................................................................................................................. 158 8.3.1 Port 8 Registers (PDR8 and DDR8) ............................................................................................. 160 8.3.2 Operation of Port 8 ....................................................................................................................... 161 8.4 Port 9 ................................................................................................................................................. 163 8.4.1 Port 9 Registers (PDR9 and DDR9) ............................................................................................. 165 8.4.2 Operation of Port 9 ....................................................................................................................... 166 8.5 Port A ................................................................................................................................................. 168 8.5.1 Port A Registers (PDRA, DDRA and ADER0) .............................................................................. 170 8.5.2 Operation of Port A ....................................................................................................................... 172 8.6 Port B ................................................................................................................................................. 174 8.6.1 Port B Registers (PDRB, DDRB and ADER1) .............................................................................. 176 8.6.2 Operation of Port B ....................................................................................................................... 178 8.7 Sample I/O Port Program .................................................................................................................. 180 CHAPTER 9 SERIAL I/O ................................................................................................ 181 9.1 Overview of the Serial I/O Unit .......................................................................................................... 182 9.2 Registers of the Serial I/O Unit .......................................................................................................... 183 9.2.1 Serial Mode Control Status Register (SMCR) .............................................................................. 184 9.2.2 Serial Shift Data Register (SDR) .................................................................................................. 188 9.3 Communication Prescaler Control Register (CDCR0/CDCR1) ......................................................... 189 9.4 Operation of the Serial I/O Unit .......................................................................................................... 191 9.4.1 Shift Clock .................................................................................................................................... 192 9.4.2 Operating States of the Serial I/O Unit ......................................................................................... 193 9.4.3 Start/Stop Timing of Shift Operation ............................................................................................. 195 9.4.4 Interrupt Function of the Serial I/O Unit ........................................................................................ 197 CHAPTER 10 TIMEBASE TIMER .................................................................................... 199 10.1 10.2 10.3 10.4 10.5 10.6 Overview of the Timebase Timer ....................................................................................................... 200 Configuration of the Timebase Timer ................................................................................................ 202 Timebase Timer Control Register (TBTC) ......................................................................................... 204 Timebase Timer Interrupts ................................................................................................................. 206 Operation of the Timebase Timer ...................................................................................................... 207 Usage Notes on the Timebase Timer ............................................................................................... 210 vii CHAPTER 11 WATCHDOG TIMER ................................................................................. 211 11.1 11.2 11.3 11.4 11.5 Overview of the Watchdog Timer ...................................................................................................... Configuration of the Watchdog Timer ............................................................................................... Watchdog Timer Control Register (WDTC) ...................................................................................... Operation of the Watchdog Timer ..................................................................................................... Usage Notes on the Watchdog Timer ............................................................................................... 212 213 215 217 219 CHAPTER 12 16-BIT RELOAD TIMER ........................................................................... 221 12.1 Overview of the 16-Bit Reload Timer ................................................................................................ 12.2 Configuration of the 16-Bit Reload Timer .......................................................................................... 12.3 16-Bit Reload Timer Pins .................................................................................................................. 12.4 16-Bit Reload Timer Registers .......................................................................................................... 12.4.1 Timer Control Status Register, Higher (TMCSR) ......................................................................... 12.4.2 Timer Control Status Register, Lower (TMCSR) .......................................................................... 12.4.3 16-bit Timer Register (TMR) ........................................................................................................ 12.4.4 16-bit Reload Register (TMRLR) ................................................................................................. 12.5 16-Bit Reload Timer Interrupts .......................................................................................................... 12.6 Operation of the 16-Bit Reload Timer ............................................................................................... 12.6.1 Internal Clock Mode (Reload Mode) ............................................................................................ 12.6.2 Internal Clock Mode (Single-shot Mode) ...................................................................................... 12.6.3 Event Count Mode ....................................................................................................................... 12.7 Usage Notes on the 16-Bit Reload Timer ......................................................................................... 222 225 227 228 229 231 233 234 235 236 238 240 242 244 CHAPTER 13 16-BIT I/O TIMER ..................................................................................... 245 13.1 Overview of the 16-Bit I/O Timer ....................................................................................................... 13.2 16-Bit I/O Timer Block Diagram ........................................................................................................ 13.3 16-Bit I/O Timer Registers ................................................................................................................ 13.3.1 16-Bit Free-Running Timer Registers (TCDT and TCCS) ........................................................... 13.3.2 Output Compare Registers (OCCP0 and OCS0) ......................................................................... 13.3.3 Input Capture Registers (IPC0/IPC1 and ICSSS0) ...................................................................... 13.4 16-Bit Free-Running Timer Operations ............................................................................................. 13.5 16-Bit Output Compare Operations .................................................................................................. 13.6 16-Bit Input Capture Operations ....................................................................................................... 246 247 248 249 252 255 258 260 261 CHAPTER 14 UART ........................................................................................................ 263 14.1 Overview of UART ........................................................................................................................... 14.2 Configuration of UART ..................................................................................................................... 14.3 UART Pins ........................................................................................................................................ 14.4 UART Registers ................................................................................................................................ 14.4.1 Control Register (SCR0/SCR1) ................................................................................................... 14.4.2 Mode Register (SMR0/SMR1) ..................................................................................................... 14.4.3 Status Register (SSR0/SSR1) ..................................................................................................... 14.4.4 Input Data Register (SIDR0/SIDR1) and Output Data Register (SODR0/SODR1) ..................... 14.4.5 Communication Prescaler Control Register (CDCR0/CDCR1) .................................................... 14.5 UART Interrupts ................................................................................................................................ 14.5.1 Reception Interrupt Generation and Flag Set Timing .................................................................. 14.5.2 Transmission Interrupt Generation and Flag Set Timing ............................................................. 14.6 UART Baud Rates ............................................................................................................................ viii 264 266 269 271 272 275 277 280 282 284 286 288 289 14.6.1 Baud Rates Determined Using the Dedicated Baud Rate Generator ........................................... 291 14.6.2 Baud Rates Determined Using the Internal Timer ....................................................................... 293 14.6.3 Baud Rates Determined Using the External Clock ....................................................................... 295 14.7 Operation of UART ............................................................................................................................ 296 14.7.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) .................................................... 298 14.7.2 Operation in Synchronous Mode (Operation Mode 2) .................................................................. 300 14.7.3 Bidirectional Communication Function (Normal Mode) ................................................................ 302 14.7.4 Master-slave Communication Function (Multiprocessor Mode) ................................................... 304 14.8 Notes on Using UART ....................................................................................................................... 307 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT .................................................. 309 15.1 Overview of the DTP/External Interrupt Circuit ................................................................................. 310 15.2 Configuration of the DTP/External Interrupt Circuit .......................................................................... 312 15.3 DTP/External Interrupt Circuit Pins ................................................................................................... 314 15.4 DTP/External Interrupt Circuit Registers ............................................................................................ 315 15.4.1 DTP/Interrupt Cause Register (EIRR) ......................................................................................... 316 15.4.2 DTP/Interrupt Enable Register (ENIR) ........................................................................................ 319 15.4.3 Request Level Setting Register (ELVR) ....................................................................................... 321 15.5 Operation of the DTP/External Interrupt Circuit ................................................................................ 323 15.5.1 External Interrupt Function ........................................................................................................... 326 15.5.2 DTP Function ............................................................................................................................... 327 15.6 Usage Notes on the DTP/External Interrupt Circuit .......................................................................... 328 CHAPTER 16 I2C INTERFACE ........................................................................................ 331 16.1 Overview of the I2C Interface ............................................................................................................. 332 16.2 Block Diagram and Configuration of the I2C Interface ....................................................................... 333 16.3 I2C Interface Registers ...................................................................................................................... 335 16.3.1 I2C Status Register (IBSR) ........................................................................................................... 336 16.3.2 I2C Control Register (IBCR) ......................................................................................................... 338 16.3.3 I2C Clock Control Register (ICCR) ............................................................................................... 341 16.3.4 I2C Address Register (IADR) ........................................................................................................ 344 16.3.5 I2C Data Register (IDAR) ............................................................................................................. 345 16.3.6 I2C Port Select Register (ISEL) .................................................................................................... 346 16.4 Operation of the I2C Interface ............................................................................................................ 347 16.4.1 Transfer Flow of the I2C Interface ................................................................................................ 349 16.4.2 Mode Flow of the I2C Interface ..................................................................................................... 351 16.4.3 Operation Flow of the I2C Interface .............................................................................................. 352 CHAPTER 17 8/10-BIT A/D CONVERTER ...................................................................... 355 17.1 Overview of the 8/10-Bit A/D Converter ............................................................................................. 356 17.2 Configuration of the 8/10-Bit A/D Converter ...................................................................................... 358 17.3 8/10-Bit A/D Converter Pins ............................................................................................................... 360 17.4 8/10-Bit A/D Converter Registers ...................................................................................................... 362 17.4.1 A/D Control Status Register 1 (ADCS1) ....................................................................................... 363 17.4.2 A/D Control Status Register 0 (ADCS0) ....................................................................................... 365 17.4.3 A/D Data Register (ADCR0/ADCR1) ............................................................................................ 367 17.4.4 A/D Conversion Channel Select Register (ADMR) ....................................................................... 369 17.5 8/10-Bit A/D Converter Interrupts ...................................................................................................... 371 ix 17.6 Operation of the 8/10-Bit A/D Converter ........................................................................................... 17.6.1 Conversion Using EI2OS ............................................................................................................. 17.6.2 A/D Conversion Data Protection Function ................................................................................... 17.7 Usage Notes on the 8/10-Bit A/D Converter ..................................................................................... 372 375 376 378 CHAPTER 18 FL CONTROL CIRCUIT ............................................................................ 379 18.1 Overview of FL Control Circuit .......................................................................................................... 18.2 Configuration of FL Control Circuit .................................................................................................... 18.3 FL Control Circuit Pins ...................................................................................................................... 18.3.1 Display Control Register 1 (FLC1) ............................................................................................... 18.3.2 Display Control Register 2 (FLC2) ............................................................................................... 18.3.3 Digit Setting Register (FLDG) ...................................................................................................... 18.3.4 Digit Count Register (FLDC) ........................................................................................................ 18.3.5 Port Register (FLPD) ................................................................................................................... 18.3.6 Status/Authorization Register (FLST) .......................................................................................... 18.3.7 Display RAM ................................................................................................................................ 18.3.8 Segment Dimmer Setting Register (SEGD) ................................................................................. 18.4 FL Control Circuit Operation ............................................................................................................. 380 382 383 385 387 389 391 393 394 396 397 398 CHAPTER 19 WATCH CLOCK OUTPUT ........................................................................ 403 19.1 Overview of the Watch Clock Output Circuit ..................................................................................... 404 19.2 Configuration of the Watch Clock Output Circuit .............................................................................. 405 19.3 Watch Clock Output Control Register (TMCS) ................................................................................. 406 CHAPTER 20 DELAYED INTERRUPT GENERATOR MODULE ................................... 407 20.1 20.2 20.3 20.4 Overview of the Delayed Interrupt Generator Module ...................................................................... Delayed Interrupt Cause/Cancel Register (DIRR) ............................................................................ Operation of the Delayed Interrupt Generator Module ...................................................................... Precautions to Follow when Using the Delayed Interrupt Generator Module ................................... 408 409 410 411 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION .......................................... 413 21.1 Overview of the Address Match Detection Function ......................................................................... 21.2 Registers of the Address Match Detection Function ......................................................................... 21.2.1 Program Address Detection Register for Upper, Middle, and Lower Parts of Address (PADR0/PADR1) ......................................................................................................................... 21.2.2 Program Address Detection Control Status Register (PACSR) ................................................... 21.3 Operation of the Address Match Detection Function ........................................................................ 21.4 Example of Using the Address Match Detection Function ................................................................ 414 415 416 417 418 419 CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE .......................... 423 22.1 Overview of the ROM Mirroring Function Selection Module ............................................................. 424 22.2 ROM Mirroring Function Selection Register (ROMM) ....................................................................... 425 CHAPTER 23 1M-BIT FLASH MEMORY ........................................................................ 427 23.1 23.2 23.3 23.4 x Overview of the 1M-Bit Flash Memory .............................................................................................. Registers and Sector Configuration of the Flash Memory ................................................................ Flash Memory Control Status Register (FMCS) ............................................................................... Starting the Automatic Algorithm of the Flash Memory ..................................................................... 428 429 430 433 23.5 Detailed Description of Flash Memory Writing and Deletion ............................................................. 434 23.5.1 Placing the Flash Memory in Read/Reset Status ......................................................................... 435 23.5.2 Writing Data to the Flash Memory ................................................................................................ 436 23.5.3 Deleting All Data Items from the Flash Memory (Chip Deletion) .................................................. 438 23.5.4 Deleting a Data Item from the Flash Memory (Sector Deletion) ................................................... 439 23.5.5 Temporarily Stopping Deletion of Sectors from the Flash Memory .............................................. 441 23.5.6 Resuming Flash Memory Sector Deletion .................................................................................... 442 CHAPTER 24 EXAMPLE OF MB90MF408/MF408A SERIAL PROGRAMMING CONNECTION ........................................................................................... 443 24.1 24.2 24.3 24.4 Standard Configuration for Serial Programming Connection to MB90MF408/MF408A .................... 444 Example of Connection for Serial Programming (Power Supplied by User) ...................................... 446 Example of Connection for Serial Programming (When Power Supplied from Programmer) ........... 448 Example of Minimum Connection with Flash Microcomputer Programmer (When Power Supplied from User) .................................................................................................... 450 24.5 Example of Minimum Connection with Flash Microcomputer Programmer (When Power Supplied from Programmer) ........................................................................................ 452 APPENDIX .......................................................................................................................... 455 APPENDIX A I/O Map ................................................................................................................................. 456 APPENDIX B Instructions ............................................................................................................................ 463 B.1 Instruction Types ............................................................................................................................. 464 B.2 Addressing ...................................................................................................................................... 465 B.3 Direct Addressing ............................................................................................................................ 467 B.4 Indirect Addressing ......................................................................................................................... 473 B.5 Execution Cycle Count .................................................................................................................... 481 B.6 Effective Address Field ................................................................................................................... 484 B.7 How to Read the Instruction List ..................................................................................................... 485 B.8 F2MC-16LX Instruction List ............................................................................................................. 488 B.9 Instruction Map ................................................................................................................................ 502 APPENDIX C Index of Registers ................................................................................................................. 524 APPENDIX D Index of Pin Functions .......................................................................................................... 528 INDEX .................................................................................................................................. 531 xi xii Main changes in this edition Page 463 to 523 Changes (For details, refer to main body.) Changed the entire part of "APPENDIX B Instructions" The vertical lines marked in the left side of the page show the changes. xiii xiv CHAPTER 1 OVERVIEW This chapter summarizes the features and basic specifications of the MB90M405 series of microcontrollers. 1.1 "Features" 1.2 "Product Lineup" 1.3 "Block Diagram" 1.4 "Package Dimensions" 1.5 "Pin Assignments" 1.6 "Pin Functions" 1.7 "I/O Circuit Types" 1.8 "Notes on Handling Devices" 1.9 "Clock Supply Map" 1.10 "Low Power Consumption Mode" 1 CHAPTER 1 OVERVIEW 1.1 Features The MB90M405 series of general-purpose 16-bit microcontrollers was developed for applications that require control of fluorescent display tube panels. The microcontrollers in this series have 60 high dielectric output pins for fluorescent display control. The instruction set inherits the AT architecture of the F2MC-8L and F2MC-16L, and has additional instructions that support the C language. In addition, the instruction set supports extended addressing mode, enhanced signed multiply/divide instructions, and more powerful bit manipulation instructions. The microcontrollers also have a 32bit accumulator that enables processing of long-word data. ■ MB90M405 Series Features ❍ Clocks • Built-in PLL clock multiplier circuit • Source oscillation Main clock that divides the source oscillation by two PLL clock that multiplies the source oscillation by 1 to 4 (2.1 to 16.8 MHz when the source oscillation is 4.2 MHz), which can be configured from the machine clock • Minimum instruction execution time: 59.5 ns (when the source oscillation is 4.2 MHz, the PLL clock is multiplied by 4, and VCC is 3 V) • The source oscillation can be divided by 16, 32, 64, or 128 for external clock output. ❍ Maximum memory address space: 16 M bytes 24-bit addressing can also be used. ❍ Optimum instruction set for controller applications • Many data types (bit, byte, and long word) can be handled. • As many as 23 addressing modes are available. • Efficient code (compiler) • Enhanced high-precision arithmetic operations with a 32-bit accumulator • Enhanced signed multiply/divide instructions and RETI instruction function ❍ Instruction set supporting the C language and multitasking • System stack pointer • Instruction set symmetry and barrel shift instructions ❍ Program patch function (two-address pointer) 2 1.1 Features ❍ Improved execution speed The built-in 4-byte instruction queue prereads instructions to improve execution speed. ❍ Interrupt function • Eight programmable priority levels can be set. • An enhanced interrupt function with 32 interrupt causes is supported. ❍ Data transfer function ❍ Extended intelligent I/O service function: Up to 16 channels can be set. ❍ Low-power mode • Sleep mode (in which the CPU operating clock stops) • Timebase timer mode (in which only the source oscillation clock and Timebase timer are active) • Stop mode (in which the source oscillation stops) • CPU intermittent operation mode (in which the CPU operates at every specified cycle) ❍ Package • QFP-100 (FPT-100P-M06: 0.65 mm pin pitch) ❍ Process CMOS technology ■ Internal Peripheral Functions (resources) ❍ I/O ports: Up to 26 ports (used also for internal resources) ❍ Timebase timer: 1 channel ❍ Watchdog timer: 1 channel ❍ 16-bit reload timer: 3 channels ❍ 16-bit free-running timer: 1 channel ❍ Output compare: 1 channel • When the counter value of the 16-bit free-running timer matches the value set in the compare register, an interrupt request can be output. 3 CHAPTER 1 OVERVIEW ❍ Input capture: 2 channels • When the effective edge of a signal that is output from an external input pin is detected, the counter value of the 16-bit free-running timer can be read into the input capture data register and an interrupt request can be output. ❍ Serial I/O: 2 channels ❍ UART: 2 channels • With full-duplex double buffer (8-bit length) • Capable of asynchronous or clock synchronous serial transfer (I/O extended serial) ❍ DTP/external interrupt (4 channels) • The input of an external interrupt can be used to activate the extended intelligent I/O service. • The input of an external interrupt can be used to cause an internal hardware interrupt. ❍ Delayed interrupt generator module Generates an interrupt request for task switching. ❍ 8/10-bit A/D converter (16 channels) Selectable resolution of 8 or 10 bits ❍ FL-control circuit • • Enables FL driver control (automatic display control of up to 32 digit lines and up to 59 segment lines) • Up to 32 digit lines (can be set line by line) • Dimmer setting Permits LED driver control (automatic display control of up to 16 lines) • Automatic display control of up to 16 lines with a 1/2 duty factor ❍ Clock output circuit • 4 Enables the source oscillation to be divided by 32, 64, 128, or 256 for clock output. 1.2 Product Lineup 1.2 Product Lineup Table 1.2-1 "MB90M405 Series Product Lineup" shows the MB90M405 series product lineup. ■ Product Lineup Table 1.2-1 MB90M405 Series Product Lineup Model MB90MV405 MB90MF408 (*1) MB90MF408A (*2) Type Evaluation device Built-in flash memory ROM size Not installed 128K bytes 96K bytes RAM size 4K bytes 4K bytes 4K bytes CPU function Port MB90M408 (*1) MB90M408A (*2) MB90M407 (*1) MB90M407A (*2) Built-in mask ROM Number of basic instructions: 351 Minimum instruction execution time: 59.5 ns/4.2 MHz (when PLL clock is multiplied by 4) Number of addressing modes: 23 Program patch function: 2-address pointer Maximum memory address space: 16M bytes I/O ports (CMOS): 26 (also used for resources) FL control circuit 60 FL output lines (43 FL output lines and 17 LED control lines in LED control mode) Capable of FL driver control and LED driver control Enables dimmer setting for both digit and segment lines in FL driver control mode Serial I/O (UART) With a full-duplex double buffer Capable of synchronous or asynchronous clock transfer Also can be used for clock synchronous extended serial I/O Dedicated built-in baud rate generator Four built-in channels (two channels are also used for the UART) 16-bit reload timer 16-bit reload timer operation (can be set for toggle or one-shot output) Supports an event count function Three built-in channels 16-bit freerunning timer 16-bit output compare x 1 channel (for clearing the free-running timer) 16-bit input capture x 2 channels 8/10-bit A/D converter 16 channels (input multiplexing) Capable of 8-bit or 10-bit resolution Conversion time: 5.9 μs (for an the operating machine clock of 16.8 MHz) Timing clock output circuit An external input clock frequency can be divided and output externally. Specifiable division ratio: Programmable to 1/16, 1/32, 1/64, or 1/128 I2C bus DTP/external interrupt One built-in I2C interface channel Four independent channels (can also be used for A/D input) Interrupt source: "L" --> "H" edge, "H" --> "L" edge, "L" level, or "H" level can be set. 5 CHAPTER 1 OVERVIEW Table 1.2-1 MB90M405 Series Product Lineup (Continued) Model Low-power mode MB90MV405 MB90MF408 (*1) MB90MF408A (*2) Operating voltage CMOS PGA256 QFP-100 (0.65 mm pitch) 3.3V 0.3V (16.8 MHz: 4.2 MHz multiplied by 4) *1: The FL output pins (FIP00 to FIP59) are output with a pull-down resistor. *2: The FL output pins (FIP00 to FIP16) are output without a pull-down resistor. The FL output pins (FIP17 to FIP59) are output with a pull-down resistor. 6 MB90M407 (*1) MB90M407A (*2) Sleep mode, Timebase timer mode, stop mode, and CPU intermittent mode Process Package MB90M408 (*1) MB90M408A (*2) 1.3 Block Diagram 1.3 Block Diagram Figure 1.3-1 "Block Diagram" shows a block diagram of the MB90M405 series of microcontrollers. ■ Block Diagram Figure 1.3-1 Block Diagram CPU control circuit ROM (96/128KB) RAM (4KB) FIP0/LED0 FL control circuit to FIP16/LED16 FIP17 to FIP59 V-RAM Internal data bus MD2,1,0 8/10-bit A/D converter Port A PA2/AN2 Clock control circuit RST PA1/AN1 Vcc/Vss PA4/AN4 PA6/AN6 Serial I/O (channel 2) PA7/AN7 External interrupt input controller 16-bit free-running timer PB0/AN8 PB1/AN9 PB2/AN10 16-bit input capture (channels 0 and 1) VKK PA3/AN3 PA5/AN5 Port B X0,X1 PA0/AN0/TMCK Timing clock output circuit PB3/AN11/SI2 PB4/AN12/SC2/TIN PB5/AN13/SO2/TO PB6/AN14/INT2 PB7/AN15/INT3 AVcc/AVss 16-bit output compare P90/SDA/SO3 P91/SCL/SC3 I2C interface UART (channels 0 and 1) P80/IC0/INT0 P81/IC1/INT1 Port 8 Port 9 Serial I/O (channel 3) 16-bit reload timer (channels 0 to 2) P82/SI0 P83/SC0 P84/SO0 P85/SI1 P86/SC1 P87/SO1 7 CHAPTER 1 OVERVIEW 1.4 Package Dimensions This section provides the dimensions of the MB90M405 series package. ■ FPT-100P-M06 Dimensions 100-pin plastic QFP Lead pitch 0.65 mm Package width package length 14.00 20.00 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.35 mm MAX (FPT-100P-M06) 100-pin plastic QFP (FPT-100P-M06) Note: Pins width and pins thickness include plating thickness. 23.90±0.40(.941±.016) 20.00±0.20(.787±.008) 80 51 81 50 0.10(.004) 17.90±0.40 (.705±.016) 14.00±0.20 (.551±.008) INDEX Details of "A" part 100 1 30 0.65(.026) "A" C 8 0.25(.010) +0.35 3.00 +.014 .118 (Mounting height) 31 2001 FUJITSU LIMITED F100008S-c-4-4 0.32±0.05 (.013±.002) 0.13(.005) M 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) Dimensions in mm (inches). 1.5 Pin Assignments 1.5 Pin Assignments Figure 1.5-1 "Pin Assignments" shows the MB90M405 series pin assignments. ■ Pin Assignments Figure 1.5-1 Pin Assignments Vss-CPU X0 X1 Vcc-CPU FIP0/LED0 FIP1/LED1 FIP2/LED2 FIP3/LED3 FIP4/LED4 FIP5/LED5 FIP6/LED6 FIP7/LED7 FIP8/LED8 FIP9/LED9 FIP10/LED10 FIP11/LED11 FIP12/LED12 FIP13/LED13 FIP14/LED14 FIP15/LED15 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 FIP16/LED16 FIP17 FIP18 FIP19 FIP20 FIP21 FIP22 FIP23 FIP24 FIP25 Vss-IO FIP26 FIP27 FIP28 FIP29 FIP30 FIP31 FIP32 FIP33 FIP34 FIP35 FIP36 VDD-FIP FIP37 FIP38 FIP39 FIP40 FIP41 FIP42 FIP43 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PB7/AN15/INT3 PB6/AN14/INT2 PB5/AN13/SO2/TO0 RST PB4/AN12/SC2/TIN0 PB3/AN11/SI2 PB2/AN10 PB1/AN9 PB0/AN8 PA7/AN7 PA6/AN6 PA5/AN5 PA4/AN4 PA3/AN3 PA2/AN2 PA1/AN1 PA0/AN0/TMCK AVss AVcc P91/SCL/SC3 P90/SDA/SO3 P87/SO1 P86/SC1 P85/SI1 P84/SO0 P83/SC0 P82/SI0 P81/IC1/INT1 P80/IC0/INT0 MD2 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 MD1 MD0 VKK FIP59 FIP58 FIP57 FIP56 FIP55 Vss-IO FIP54 FIP53 FIP52 FIP51 FIP50 FIP49 FIP48 FIP47 FIP46 FIP45 FIP44 9 CHAPTER 1 OVERVIEW 1.6 Pin Functions Table 1.6-1 "Pin Functions" summarizes the pin names and functions, as well as the related circuit types and states at reset. ■ Pin Functions Table 1.6-1 Pin Functions Pin number Pin name Circuit type State/function at reset 82, 23 X0, X1 A Oscillating Oscillation input pin When an external clock is connected, leave the X1 pin open. 77 RST B Reset input External reset input pin QFP-100M06 FIP0 to FIP15 Function Set when the FL driver is enabled 85 to 100 LED0 to LED15 FIP16 1 Set when the LED driver is enabled C LED16 2 to 10 12 to 19 20 to 22 24 to 41 43 to 47 FIP17 to FIP33 Set when the FL driver is enabled VKK pull-down output (when a Set when the LED driver is enabled pull-down resistor is set) Pin dedicated to FL driver output FIP34 to FIP59 D P80 I/O port IC0 External trigger input pin for input capture channel 0 52 External cause input pin for external interrupt input channel 0 Input is enabled when the EN0 bit enables this pin. INT0 E I/O port IC1 External trigger input pin for input capture channel 1 53 INT1 10 Port input (Hi-z) P81 External cause input pin for external interrupt input channel 1 Input is enabled when the EN1 bit enables this pin. 1.6 Pin Functions Table 1.6-1 Pin Functions (Continued) Pin number Pin name QFP-100M06 Circuit type State/function at reset Function P82 I/O port SI0 Serial data input pin for serial I/O channel 0 This pin is used occasionally while serial I/O channel 0 is performing an input operation. Do not use this pin for any other purpose during an input operation on serial I/O channel 0. P83 I/O port SC0 Serial clock I/O pin for serial I/O channel 0 This function is enabled when serial I/O channel 0 is enabled for serial clock output. P84 I/O port SO0 Serial data output pin for serial I/O channel 0 This function is enabled when serial I/O channel 0 is enabled for serial data output. 54 55 56 E P85 I/O port Serial data input pin for serial I/O channel1 This pin is used occasionally while serial I/O channel 1 is performing an input operation. Do Port input (Hi-z) not use this pin for any other purpose during an input operation on serial I/O channel 1. 57 SI1 P86 I/O port SC1 Serial clock I/O pin for serial I/O channel 1 This function is enabled when serial I/O channel 1 is enabled for serial clock output. P87 I/O port SO1 Serial data output pin for serial I/O channel 1 This function is enabled when serial I/O channel 1 is enabled for serial data output. P90 I/O port (N-channel open drain) SDA I2C interface data I/O pin. This function is enabled when I2C interface operation is enabled. Set the port to the input setting (DDR9 bit 8 = 0) while the I2C interface is active. 58 59 60 G SO3 Serial data output pin for serial I/O channel 3 This function is enabled when serial I/O channel 3 is enabled for serial data output. 11 CHAPTER 1 OVERVIEW Table 1.6-1 Pin Functions (Continued) Pin number Pin name QFP-100M06 Circuit type State/function at reset P91 I/O port (N-channel open drain) SCL I2C interface clock I/O pin. This function is effective when I2C interface operation is enabled. Set the port to the input setting (DDR9 bit 9 = 0) Port input (Hi-z) while the I2C interface is active. 61 G SC3 Serial clock I/O pin for serial I/O channel 3 This function is enabled when serial I/O channel 3 is enabled for serial clock output. PA0 I/O port AN0 Analog input pin channel 0 for the A/D converter This function is enabled when analog input is enabled (set by the ADER). TMCK Timing clock output pin. This function is enabled when output is enabled. The function is disabled when the ADER enables analog input. 64 PA1 to PB2 I/O port Analog input pin channels 1 to 10 for the A/D converter This function is enabled when analog input is enabled (set by the ADER). 65 to 74 AN1 to AN10 PB3 AN11 75 I/O port F Analog input Analog input pin channel 11 for the A/D converter This function is enabled when analog input is enabled (set by the ADER). SI2 Serial data input pin for serial I/O channel 2 This pin is used occasionally while serial I/O channel 2 is performing an input operation. Do not use this pin for any other purpose during an input operation on serial I/O channel 2. PB4 I/O port AN12 Analog input pin channel 12 for the A/D converter This function is enabled when analog input is enabled (set by the ADER). SC2 Serial clock I/O pin for serial I/O channel 2 This function is enabled when serial I/O channel 2 is enabled for serial clock output. TIN0 External clock input pin for reload timer channel 0 This function is enabled when external clock input is enabled (the ADER setting has precedence). 76 12 Function 1.6 Pin Functions Table 1.6-1 Pin Functions (Continued) Pin number Pin name QFP-100M06 Circuit type State/function at reset PB5 78 I/O port AN13 Analog input pin channel 13 for the A/D converter This function is enabled when analog input is enabled (set by the ADER). SO2 Serial data output pin for serial I/O channel 2 This function is enabled when serial I/O channel 2 is enabled for serial data output. TO0 External event output pin for reload timer channel 0 This function is enabled when external event output is enabled (the ADER setting has precedence). F Analog input PB6 to PB7 I/O port Analog input pin channels 14 and 15 for the A/D converter This function is enabled when analog input is enabled (set by the ADER). AN14 to AN15 79, 80 External cause input pin for external interrupt input channels 2 and 3 Input is enabled when the EN2 and EN3 bits enable these pins. INT2 to INT3 62 Function AVCC 63 AVSS 48 VKK 49 MD0 50 MD1 51 MD2 11, 42 VSS-IO 23 VDD-FIP VCC power input pin for analog macro H Power input VSS power input pin for analog macro Power pin on pull-down side in high dielectric output mode - Input pin for operation mode specification. Connect this pin to VCC. When a flash boot program is used, be sure to change the pin to VSS. B Mode pin Input pin for operation mode specification. Connect this pin to VCC. Input pin for operation mode specification. Connect this pin to VSS. When a flash boot program is used, be sure to change the pin to VCC. I/O power (0 V: GND) input pin - Power input FIP power (3 V: VCC) input pin 81 VSS-CPU Control circuit power (0 V: GND) input pin 84 VCC-CPU Control circuit power (3 V: VCC) input pin 13 CHAPTER 1 OVERVIEW 1.7 I/O Circuit Types Table 1.7-1 "I/O Circuit Types (continued next page)" summarizes the circuit types of individual pins. ■ I/O Circuit Types Table 1.7-1 I/O Circuit Types (continued next page) Classification Circuit type X1 Nch Remarks • Oscillation circuit Oscillation feedback resistance = about 1 MΩ • Hysteresis input pin Built-in pull-up resistor (Rp) • P-ch open drain output - High dielectric port output IOL = 25 mA Xout Pch A X0 Pch Nch Standby control signal B Rp Pch Pout C When this pin is used as an ordinary port, connect a diode clamp circuit to it to prevent VKK voltage from being applied to the pin when the "L" level is output. (See Section 1.8, "Notes on Handling Devices." RKK VKK • Pch Pout D RKK VKK 14 P-ch open drain output - High dielectric port output IOL = 12 mA When this pin is used as a normal port, connect a diode clamp circuit to it to prevent VKK voltage from being applied to the pin when the "L" level is output. (See Section 1.8 "Notes on Handling Devices." 1.7 I/O Circuit Types Table 1.7-1 I/O Circuit Types (continued next page) Classification E Circuit type Pch Pout Nch Nout Remarks • CMOS hysteresis I/O pin - CMOS output - CMOS hysteresis input (with standby control for input rejection) IOL = 4 mA • Analog/CMOS hysteresis I/O pin - CMOS output - CMOS hysteresis input (with standby control for input rejection) - Analog input (Analog input is enabled when the corresponding ADER bit is "1".) IOL = 4 mA • N-ch open drain output - CMOS hysteresis input (with standby control for input rejection) R Hysteresis input Standby control F Pch Pout Nch Nout R Hysteresis input Standby control Analog input Nout Pch G R Hysteresis input Standby control Unlike the CMOS I/O pin, this pin has no Pch transistor. Therefore, even when voltage is applied externally to this pin while the device power is off, no current flows into the device power supply (VCCIO/VCC-CPU). • Analog power input protection circuit Pch H IN Nch 15 CHAPTER 1 OVERVIEW 1.8 Notes on Handling Devices When handling devices, note the following: • Strict observation of maximum rated voltage (latchup prevention) • Stabilization of supply voltage • Note on power-on • Treatment of unused input pins • Note on external clocks • Power supply pins • Crystal oscillation circuit • Power-on sequence for A/D converter power supply analog input • Treating pins when the A/D converter is not used • Output of high dielectric output pin (circuit type C or D) • Note on during operation of PLL clock mode ■ Strict Observation of Maximum Rated Voltage (Latchup Prevention) • Do not apply a voltage higher than VCC or lower than VSS to CMOS IC input and output pins that are not medium or high dielectric pins. Also, do not apply a voltage higher than the rating between VCC and VSS. Disregard of these precautions may result in latchup. • A latchup rapidly increases supply current and may result in thermal damage to elements. Be careful not to apply voltage exceeding the maximum rating. • When turning power to analog circuits on or off, ensure that the analog power supply (AVCC) and analog input voltage do not exceed the digital supply voltage (VCC). ■ Stabilization of Supply Voltage Even within the operation guarantee range of the VCC supply voltage, a malfunction can be caused if the supply voltage changes abruptly. To prevent problems from occurring, stabilize the VCC supply voltage. As guidelines for voltage stabilization, the VCC ripple fluctuations (peak-to-peak value) at commercial frequencies (50 to 60 Hz) should be suppressed to 10% or less of the reference VCC value. During a momentary change such as when a supply voltage is switched, voltage functions should also be suppressed so that the transient fluctuation rate does not exceed 0.1 V/ms. ■ Note on Power-on To prevent a malfunction in the built-in voltage drop circuit during power-on, ensure 50 μs (between 0.2 V and 2.7 V) or more for the supply voltage (VCC) rise time. ■ Treatment of Unused Input Pins An unused input pin, if left open, may cause a malfunction or a permanent damage due to a latchup. Every unused input pin must be pulled up or down using resistance of 2 kΩ or more. An unused I/O pin must be either opened by setting it to output mode or handled in the same way as an input pin after it has been set to input mode. 16 1.8 Notes on Handling Devices ■ Note on External Clocks When an external clock is used, connect only the X0 pin; leave the X1 pin open. A sample application of the external clock is shown below: X0 MB90M405 series OPEN X1 ■ Power Supply Pins • When a device has two or more VCC or VSS pins, the pins that should have equal potential are connected within the device in order to prevent a latchup or other malfunction. To reduce extraneous emissions, to prevent a malfunction of the strobe signal due to an increase in the ground level, and to maintain the total output current rating, connect the VCC or VSS pins to the power supply or to ground. • Connect the current supply source to the VCC and VSS pins of the MB90M405 series device with minimum impedance. • As a measure against power supply noise in an MB90M405 series device, connect a bypass capacitor of about 0.1 μF between VCC and VSS near the VCC and VSS pins. ■ Crystal Oscillation Circuit Noise at the X0 and X1 pins can cause malfunctioning of MB90M405 series devices. Design the printed wiring board so that bypass capacitors to the X0 and X1 pins, crystal oscillator (or ceramic oscillator), and ground are provided near the X0 and X1 pins and that the X0 and X1 pin wirings do not cross other wirings. Printed wiring board artwork that encloses the X0 and X1 pins with ground should result in stable operation. ■ Power-on Sequence for A/D Converter Power Supply Analog Input • Before turning on power to the A/D converter power supply pin (AVCC) and analog input pins (AN0 to AN15), be sure power to the digital power supply pin (VCC) has already been turned on. • When turning off the power, turn off the power to the digital power supply pin (VCC) after turning off the power to the A/D converter and analog inputs. • When a pin that is used for analog input is also used as an input port, prevent the analog input voltage from exceeding AVCC. (The analog power and digital power can be simultaneously turned on or off with no problem.) ■ Treating Pins When the A/D Converter Is Not Used When the A/D converter is not used, connect AVCC and VCC, and AVSS and VSS. 17 CHAPTER 1 OVERVIEW ■ Output of High Dielectric Output Pin (Circuit Type C or D) When a high dielectric output pin (circuit type C or D) is used as an ordinary output port, the value obtained by pulling down the VKK pin voltage is output in "L" level output mode. In this case, the VKK pin level voltage is applied to the external circuit. Add a diode clamp circuit as shown in the figure below. Diode clamp circuit Pch Pout RKK VKK ■ Note on during Operation of PLL Clock Mode In the case of the PLL clock is selected as the machine clock, if an oscillator is off or if the clock input is stopped, the microcontroller may be continued to operation by the free running frequency of the internal PLL self oscillator circuit. This operation is warranted. 18 1.9 Clock Supply Map 1.9 Clock Supply Map Figure 1.9-1 "Clock Supply Map" shows a clock supply map of the MB90M405 series. ■ Clock Supply Map Figure 1.9-1 Clock Supply Map Timing clock divider Clock generation circuit Watchdog timer X0 Selector Oscillation circuit X1 Timebase timer 1 2 3 4 PLL multiplying circuit Built-in resources FFL controller 16-bit reload timer 8/10-bit A/D converter Serial I/O Free-running timer Input capture Output compare I2C communication interface PCLK Divide-bytwo circuit HCLK Selector MCLK CPU(F2MC-16LX) ROM/RAM (memory) HCLK : Oscillation clock frequency MCLK : Main clock frequency PCLK : PLL clock frequency 19 CHAPTER 1 OVERVIEW 1.10 Low Power Consumption Mode This section provides an overview of low-power mode. The MB90M405 series uses the operation modes listed in the table below, and functions and clocks stop differently depending on the mode. For more information, see CHAPTER 4 "CLOCKS." ■ Relationships between operation Modes and Power Table 1.10-1 Relationships between Operation Modes and Power Operation mode Main clock PLL clock CPU Built-in resources Timing clock PLL Run Operating Operating Operating Operating Operating Main Run Operating Stopped Operating Operating Operating PLL Sleep Operating Operating Stopped Operating (*1) Operating Main Sleep Operating Stopped Stopped Operating (*1) Operating Pseudo Clock Operating Stopped Stopped Stopped Operating Stop Stopped Stopped Stopped Stopped Stopped In the above table, the operation modes are arranged in descending order of power consumption In PLL Run mode, operation is performed based on PCLK obtained by multiplying the source oscillation by 1 to 4. In Main Run mode, operation is performed based on MCLK obtained by dividing the source clock by 2. *1: In Sleep mode, since the CPU has stopped, access to the built-in resources from the CPU is disabled. 20 CHAPTER 2 CPU This chapter describes the CPU and the memory space provided by the MB90M405 series. 2.1 "CPU" 2.2 "Memory Space" 2.3 "Memory Maps" 2.4 "Addressing" 2.5 "Memory Location of Multibyte Data" 2.6 "Registers" 2.7 "Dedicated Registers" 2.8 "General-Purpose Registers" 2.9 "Prefix Codes" 21 CHAPTER 2 CPU 2.1 CPU The F2MC-16LX CPU core is a 16-bit CPU designed for use in applications, such as welfare and mobile equipment, which require high-speed real-time processing. The instruction set of the F2MC-16LX was designed for controllers so that it can perform various types of control at high speeds and efficiencies. The F2MC-16LX CPU core processes 32-bit data using a built-in 32-bit accumulator. Memory space, which can be extended to up to 16M bytes, can be accessed in either linear or bank access mode. The instruction set inherits the AT architecture of the F2MC-8L and has additional instructions for supporting the C language. In addition, it has an extended addressing mode, enhanced multiply/divide instructions, and improved bit manipulation instructions. The features of the F2MC-16XL CPU are shown below: ■ CPU ❍ Minimum instruction execution time: 59.5 ns (source oscillation at 4.2 MHz and clock multiplication by 4) ❍ Maximum memory address space: 16M bytes. Can be accessed in linear or bank mode. ❍ Instruction set optimum for controller applications • Many data types (bit, byte, word, and long word) • As many as 23 addressing modes • Enhanced high-precision arithmetic operation by a 32-bit accumulator • Enhanced signed multiply/divide instructions and RETI instruction function ❍ Interrupt function Eight programmable priority levels ❍ Automatic transfer function independent to CPU Extended intelligent I/O service using up to 16 channels ❍ Instruction set supporting high-level language (C) and multi-tasking System stack pointer, instruction set symmetry, and barrel shift instructions ❍ Increased execution speed: 4-byte instruction queue 22 2.2 Memory Space 2.2 Memory Space All I/O, programs, and data are located in the 16M-byte memory space of the F2MC16LX. The RAM space is used for extended intelligent I/O service (EI2OS) descriptors, general-purpose registers, and vector tables. ■ Memory Space All I/O, programs, and data are located in the 16M-byte memory space of the F2MC-16LX CPU. The CPU is able to access each built-in peripheral function (resource) through a memory space address indicated by the 24-bit address bus. Figure 2.2-1 Sample Relationship between the F2MC-16LX System 2 F MC-16LX device FFFFFF H Vector table area FFFC00 H Programs F F 0 0 0 0 H *1 ROM area Program area 100000H F MC-16LX CPU External area (*4) Internal bus 2 010000H ROM area (FF bank image) 0 0 4 0 0 0 H *2 Data 002000H 0 0 0 D 0 0 H*3 000380H EI2OS Interrupts Peripheral circuits General-purpose ports *1 *2 *3 *4 000180H 000100H 0000C0H 0000B0H 000020H 000000H External area (*4) Data area General-purpose register RAM area EI2OS descriptor area External area (*4) Interrupt control register area Peripheral function control register area I/O area I/O port control register area The size of internal ROM differs for each model. The area accessible by the image differs for each model. The size of internal RAM differs for each model. There is no access in single-chip mode. 23 CHAPTER 2 CPU ■ ROM Area ❍ Vector table area (address: "FFFC00H to FFFFFFH") • This area is used as a vector table for vector call instructions, interrupt vectors, and reset vectors. • This area is allocated at the highest addresses of the ROM area. The start address of the corresponding processing routine is stored in each vector table address. ❍ Program area (address: Up to "FFFBFFH") • ROM is built in as an internal program area. • The size of the internal ROM differs for each model. ■ RAM Area ❍ Data area (address: From "000100H") • The static RAM is built in as an internal data area. • The size of internal RAM differs for each model. ❍ General-purpose register area (address: "000180H to 00037FH") • Auxiliary registers used for 8-bit, 16-bit, and 32-bit arithmetic operations and transfer are allocated in this area. • When this area is not used as a general purpose register, it can be used as ordinary RAM. • When this area is used as a general-purpose register, general-purpose register addressing enables high-speed access within a few instruction cycles. ❍ Extended intelligent I/O service (EI2OS) descriptor area (address: "000100H to 00017FH") 24 • This area retains the transfer modes, I/O addresses, transfer count, and buffer addresses of the Extended Intelligent I/O Service (EI2OS). • If the Extended Intelligent I/O Service (EI2OS) is not used, this area can be used as ordinary RAM. 2.2 Memory Space ■ I/O Area ❍ Interrupt control register area (address: "0000B0H to 0000BFH") The interrupt control registers (ICR00 to ICR15) correspond to the built-in peripheral functions that have an interrupt function. These registers set interrupt levels and control the extended intelligent I/O service (El2OS). ❍ Peripheral function control register area (address: "000020H to 0000AFH") This register controls the built-in peripheral functions (resources). ❍ I/O port control register area (address: "000000H to 00001FH") This register controls the I/O port. 25 CHAPTER 2 CPU 2.3 Memory Maps This section shows the memory map for each model of MB90M405 series. ■ Memory Maps Figure 2.3-1 Memory Maps Single chip mode (with mirror ROM function) FFFFFFH ROM area Address #1 010000H ROM area (FF bank image) Address #2 Address #3 RAM area Register 000100H 0000C0H Peripheral area : Access not allowed 000000H Model Address #1 Address #2 Address #3 MB90M407/M407A FE8000H 004000H 001100H MB90M408/M408A FE0000H 004000H 001100H MB90MF408/MF408A FE0000H 004000H 001100H MB90MV405 F80000H 004000H 001100H (*1) *1: V products have no built-in ROM. This area should be understood as the ROM decode area of the tool. 26 2.3 Memory Maps Reference: The ROM mirroring function allows the small model of the C compiler to be used. The low-order 16-bit address of FF bank becomes the same as the low-order 16-bit address of 00 bank. However, not all the data in the ROM area can be seen as a mirror image in 00 bank because the ROM area of FF bank exceeds 48K bytes. To use the small model of the C compiler, store the data table in "FF4000H to FFFFFFH" to show the data table as a mirror image in "004000H to 00FFFFH". Thus, the data table in the ROM area can be referenced without the "far" specification declared in the pointer. Note: • If the ROM mirroring function register is set, the data in the upper side of FF bank ("FF4000H to FFFFFFH") can be seen as a mirror image in the upper side of 00 bank ("004000H to 00FFFFH"). • For information on setting the ROM mirroring function, see Chapter 22 "ROM MIRRORING FUNCTION SELECTION MODULE". 27 CHAPTER 2 CPU 2.4 Addressing Addresses can be generated using linear addressing and bank addressing. In linear addressing, the 16M-byte space is directly specified using a continuous 24-bit address. In bank addressing, the 16M-byte space is divided into 256 64K-byte banks. The upper 8 bits of the address are specified by a bank register and the lower 16 bits of the address are directly specified by an instruction. The F2MC-16LX series basically uses bank addressing. ■ Linear Addressing and Bank Addressing Figure 2.4-1 Linear Addressing and Bank Addressing Memory Management Linear addressing FFFFFFH Bank addressing FFFFFFH FF0000 H FEFFFFH FE0000 H FDFFFFH FD0000 H 123456 H FF bank 64 K bytes FE bank FD bank 123456 H 12 bank 04FFFF H 040000 H 03FFFF H 030000 H 02FFFF H 020000 H 01FFFF H 010000 H 00FFFF H 000000 H 000000 H 123456 H 04 bank 03 bank 02 bank 01 bank 00 bank 123456 H Specified by an instruction Specified entirely by an instruction Specified by a bank register for the required purpose 28 2.4 Addressing 2.4.1 Address Specification by Linear Addressing The linear addressing has two types of address specified: • Specify 24-bit address directly in the instruction as operand • Specify 24-bit address in a 32-bit general-purpose registers, using the lower 24 bits ■ Linear Addressing by 24-Bit Operand Specification Figure 2.4-2 Example of Direct Specification of a 24-bit Physical Address in Linear Addressing JMPP 0123456H Old program counter + program bank 17 452D 17452DH New program counter + program bank 12 3456 123456H JMPP 123456H Next instruction ■ Addressing by Indirect Specification with a 32-Bit Register Figure 2.4-3 Example of Indirect Specification with a 32-bit General-Purpose Register in Linear Addressing MOV A,@RL1+7 Old AL XXXX 090700 H 3AH +7 New AL 003A RL1 240906F9H (Upper 8 bits are ignored) RL1: 32-bit (long-word) general-purpose register 29 CHAPTER 2 CPU 2.4.2 Address Specification by Bank Addressing In address specification by bank addressing, the 16M-byte space is divided into 256 64K-byte banks. The upper 8 bits of the address are specified by a bank register and the lower 16 bits of the address are directly specified by an instruction. The five types of bank registers classified by function are as follows: • Program bank register (PCB) • Data bank register (DTB) • User stack bank register (USB) • System stack bank register (SSB) • Additional bank register (ADB) ■ Bank Registers and Access Space Table 2.4-1 Access Space and Main Function of Each Bank Register Bank register name Access space Main function Initial value after a reset Program bank register (PCB) Program (PC) space Instruction codes, vector tables, and immediate-value data are stored. FFH Data bank register (DTB) Data (DT) space Read/write data is stored. Internal or external peripheral control registers and data registers are accessed. 00H User stack bank register (USB) Stack (SP) space This area is used for stack accesses such as when PUSH/POP instructions and interrupt registers are saved. The SSB is used when the stack flag in the condition register (CCR:S) is 1. The USB is used when the stack flag in the condition register (CCR:S) is 0. (*1) 00H Data that overflows from the data (DT) space is stored. 00H System stack bank register (SSB) (*1) Additional bank register (ADB) Additional (AD) space *1: The SSB is always used as an interrupt stack. See Section 2.7.9 "Bank Registers (PCB, DTB, USB, SSB, ADB)" for details. 30 00H 2.4 Addressing Figure 2.4-4 Sample Bank Addressing FFFFFFH Program space FF0000 H FFH : Program bank register (PCB) 0FFFFF H Additional space Physical address 0F0000 H 0FH : Additional bank register (ADB) 0DFFFFH User stack space 0D0000 H 0DH : User stack bank register (USB) 0BFFFFH Data space 0B0000 H 0BH : Data bank register (DTB) 07FFFF H System stack space 070000 H 07H : System stack bank register (SSB) 000000 H ■ Bank Addressing and Default Space To improve instruction coding efficiency, each instruction has a defined default space for each addressing method, as shown in Table 2.4-2 "Addressing and Default Spaces". To use a space other than the default space, specify a prefix code for a bank before the instruction. This enables the bank space that corresponds to the specified prefix code to be accessed.See Section 2.9 "Prefix Codes" for details about prefix codes. Table 2.4-2 Addressing and Default Spaces Default space Program space Addressing PC indirect, program access, branching Data space Addressing using @RW0, @RW1, @RW4, and @RW5, @A, addr16, dir Stack space Addressing using PUSHW, POPW, @RW3, and @RW7 Additional space Addressing using @RW2 and @RW6 31 CHAPTER 2 CPU 2.5 Memory Location of Multibyte Data Multibyte data is written to memory sequentially from the lower address. If multibyte data is 32-bit data, the lower 16 bits are transferred followed by the upper 16 bits. If a reset signal is input immediately after the low-order data is written, the high-order data may not be written. ■ Storage of Multibyte Data in RAM The lower 8 bits of the data is located at address n, and subsequent data is located at address n + 1, address n + 2, address n + 3, and so on, in this sequence. Figure 2.5-1 Storage of Multibyte Data in RAM MSB H LSB 01010101B 11001100B 11111111B 00010100B 01010101B 11001100B 11111111B Address n 00010100B L MSB : Most Significant Bit LSB : Least Significant Bit ■ Storage of Multibyte Operand Figure 2.5-2 Storage of a Multibyte Operand in RAM JMPP 123456H H JMPP 12H 34H 56H Address n L 32 63H 1 2 3 4 5 6H 2.5 Memory Location of Multibyte Data ■ Storage of Multibyte Data in a Stack Figure 2.5-3 Storage of Multibyte Data in a Stack PUSHW RW1,RW3 H PUSHW RW1, RW3 (35A4 H ) (6DF0 H ) SP 6DH F0H 35H A4H Address n L RW1: 35A4H RW3: 6DF0H *1 Stack status after execution of the PUSHW instruction ■ Multibyte Data Access Multibyte data is generally accessed within a bank. For an instruction that accesses multibyte data, the address "FFFFH" is followed by "0000H" in the same bank. Figure 2.5-4 Multibyte Data Access on a Bank Boundary H AL before execution 80FFFFH ?? ?? 23H 01H 01H MOVW A,080FFFFH 23H 800000H AL after execution L 33 CHAPTER 2 CPU 2.6 Registers F2MC-16LX registers are classified into internal dedicated CPU registers and built-in RAM general-purpose registers. ■ Dedicated Registers and General-Purpose Registers he dedicated registers are built-in hardware components of the CPU. Consequently, their use is limited by the CPU architecture. General-purpose registers are allocated together with RAM in the CPU address space. General-purpose registers are like dedicated registers in that they can be accessed without address specifications, but are like regular memory in that their use can be defined by the user. Figure 2.6-1 Dedicated Registers and General-Purpose Registers RAM RAM CPU Dedicated register General-purpose register Accumulator User stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register 34 Internal bus System stack pointer 2.7 Dedicated Registers 2.7 Dedicated Registers The following 11 registers are dedicated registers in the CPU. • Accumulator (A) • User stack pointer (USP) • System stack pointer (SSP) • Processor status (PS) • Program counter (PC) • Direct page register (DPR) • Program bank register (PCB) • Data bank register (DTB) • User stack bank register (USB) • System stack bank register (SSB) • Additional data bank register (ADB) ■ Configuration of Dedicated Registers Figure 2.7-1 Configuration of Dedicated Registers AH AL : Accumulator (A) Two 16-bit registers used for the storage of arithmetic operation results. The two registers can be combined as a contiguous 32-bit register. USP : User stack pointer (USP) 16-bit stack pointer that indicates the user stack address SSP : System stack pointer (SSP) 16-bit stack pointer that indicates the system stack address PS : Processor status (PS) 16-bit status register that indicates the system status PC : Program counter (PC) 16-bit count register that indicates the current instruction storage location DPR : Direct page register (DPR) 8-bit page register that specifies bits 8 to 15 of the operand address when the short direct addressing is executed PCB : Program bank register (PCB) 8-bit bank register that indicates the program space DTB : Data bank register (DTB) 8-bit bank register that indicates the data space USB : User stack bank register (USB) 8-bit bank register that indicates the user stack space SSB : System stack bank register (SSB) 8-bit bank register that indicates the system stack space ADB 8 bits : Additional data bank register (ADB) 8-bit bank register that indicates the additional space 16 bits 32 bits 35 CHAPTER 2 CPU Table 2.7-1 Initial Values of the Dedicated Registers Dedicated register Initial value Accumulator (A) Undefined User stack pointer (USP) Undefined System stack pointer (SSP) Undefined Processor status (PS) bit15 to bit13 bit12 0 Program counter (PC) Direct page register (DPR) Program bank register (PCB) to ILM PS 0 bit8 bit7 to 0 0 0 0 bit0 CCR RP 0 0 - 0 1 x x x x x Value in reset vector (contents of FFFFDCH, FFFFDDH) 01H Value in reset vector (contents of FFFFDEH) Data bank register (DTB) 00H User stack bank register (USB) 00H System stack bank register (SSB) 00H Additional data bank register (ADB) 00H Note: Shown above are the initial values for use in a device, not for use in an ICE (such as an emulator). 36 2.7 Dedicated Registers 2.7.1 Accumulator (A) The accumulator (A) consists of two 16-bit arithmetic operation registers (AH and AL). The accumulator is used to temporarily store the results of an arithmetic operation and data. The accumulator (A) can be used as a 32-bit, 16-bit, or 8-bit register. Arithmetic operations can be performed between memory and other registers or between the higher 16-bit arithmetic operation register (AH) and the lower 6-bit arithmetic operation register (AL). The A register has a data retention function: When data not longer than a word is transferred to the AL register, data stored in the AL register before the transfer is transferred to the AH register. (Data is not retained for some instructions.) ■ Accumulator (A) ❍ Data transfer to the accumulator The accumulator (A) can handle 32-bit (long word), 16-bit (word), and 8-bit (byte) data. The four-bit data transfer instruction (MOVN) is exceptionally provided but the data is processed in the same way as that for 8-bit data. • For 32-bit data processing, the AH and AL registers are used in combination. • For 16-bit and 8-bit data, the AL register is used while the AH register retains data in the AL register. • Data not longer than a byte, when transferred to the AL register, becomes 16 bits long through sign or zero extension and is stored in the AL register. Data stored in the AL register can be handled as 16-bit or 8-bit data. Figure 2.7-3 "Example of AL-AH Transfer in the Accumulator (A) (8-bit Immediate Value, Zero Extension)" to Figure 2.7-6 "Example of AL-AH Transfer in the Accumulator (A) (16 bits, Register Indirect)" show specific examples of transfer. 37 CHAPTER 2 CPU Figure 2.7-2 Data Transfer to the Accumulator 32-bit AH AL 32-bit data transfer Data transfer AH Data save 16-bit data transfer Data transfer AL Data transfer AH Data save 8-bit data transfer AL Data transfer "00H" or "FFH " (*1) (Zero extension or sign extension) *1 Becomes "000H" or "FFFH" for a 4-bit transfer instruction. ❍ Accumulator byte-processing arithmetic operation When a byte-processing arithmetic operation instruction is executed for the AL register, the upper 8 bits of the AL register before the arithmetic operation is executed are ignored. The upper 8 bits of the arithmetic operation results are all zeros. ❍ Initial value of the accumulator The initial value after a reset is undefined. Figure 2.7-3 Example of AL-AH Transfer in the Accumulator (A) (8-bit Immediate Value, Zero Extension) MOV A,3000H AH Before execution XXXXH (An instruction that zero-extends the contents at address 3000 result in the AL register) Memory space MSB LSB AL DTB After execution 38 2456H B53000H 2456H 0088H 77H 88H B5H X MSB LSB DTB : : : : Undefined Most Significant Bit Least Significant Bit Data bank register 2.7 Dedicated Registers Figure 2.7-4 Example of AL-AH Transfer in the Accumulator (A) (8-bit Immediate Value, Sign Extension) MOVW A,3000H (An instruction that stores the contents at address 3000H in the AL register) Memory space MSB AH Before execution XXXXH 2456H B53000H 2456H DTB After execution LSB AL 77H 88H B5H X MSB LSB DTB 7788H : : : : Undefined Most Significant Bit Least Significant Bit Data bank register Figure 2.7-5 Example of 32-bit Data Transfer to the Accumulator (A) (Register Indirect) MOVL A,@RW1+6 Before execution AH XXXXH (Instruction that performs a long-word-length read using the result of the RW1 contents + an 8-bit offset as the address and stores the read value in the A register) DTB After execution 8F74H Memory space MSB AL XXXXH A6H A61540H A6153EH 8FH 2BH 74H 52H RW1 15H 38H LSB +6 2B52H X MSB LSB DTB : : : : Undefined Most Significant Bit Least Significant Bit Data bank register Figure 2.7-6 Example of AL-AH Transfer in the Accumulator (A) (16 bits, Register Indirect) MOVW A,@RW1+6 AH Before execution XXXXH (Instruction that performs a word-length read using the result of the RW1 contents + an 8-bit offset as the address and stores the read value in the A register) Memory space MSB LSB AL 1234H DTB After execution 1234H 2B52H A6153EH 8FH 2BH 74H 52H RW1 15H 38H A61540H A6H +6 X MSB LSB DTB : : : : Undefined Most Significant Bit Least Significant Bit Data bank register 39 CHAPTER 2 CPU 2.7.2 Stack Pointers (USP, SSP) There are two types of stack pointers: a user stack pointer (USP) and a system stack pointer (SSP). Each stack pointer is a register that indicates the memory address of the location of the destination for saved data or a return address when PUSH instructions, POP instructions, and subroutines are executed. The upper 8 bits of the stack address are specified by the user stack bank register (USB) or system stack bank register (SSB). When the S flag of the condition code register (CCR) is 0, the USP and USB registers are valid. When the S flag is 1, the SSP and SSB registers are valid. ■ Stack Selection The F2MC-16LX uses two types of stack: a system stack and a user stack. The stack address is determined, as shown in Table 2.7-2 "Stack Address Specification", by the S flag in the processor status (PS:CCR). Table 2.7-2 Stack Address Specification Stack address S flag Upper 8 bits 0 1 (*1) Lower 16 bits User stack bank register (USB) User stack pointer (USP) System stack bank register (SSB) System stack pointer (SSP) *1: Initial value Since a reset initializes the S flag to "1", the system stack is used by default. When an interrupt is received, the stack flag (CCR:S) is set to "1" and the system stack pointer will be used. The user stack is used for all types of stack operations except those for interrupt routines. Unless the stack space is divided , the system stack should be used. 40 2.7 Dedicated Registers Figure 2.7-7 Stack Operation Instruction and Stack Pointer PUSHW A with the S flag set to 0 Before execution AL A624H USB C6H USP F328H 0 SSB 56H SSP 1234H A624H USB C6H USP F326H SSB 56H SSP 1234H S flag After execution AL MSB S flag 0 C6F326H LSB XXH XXH The user stack is used because the S flag is 0 C6F326H A6H 24H PUSHW A with the S flag set to 1 MSB Before execution AL USB C6H USP F328H 1 SSB 56H SSP 1234H A624H USB C6H USP F328H SSB 56H SSP 1232H A624H S flag After execution AL S flag 1 LSB 561232 H XXH XXH 561232 H A6H 24H The system stack is used because the S flag is 1 X : Undefined MSB : Most Significant Bit LSB : Least Significant Bit Note: • To set a stack address in the stack pointer, use an even-numbered address. If an oddnumbered address is used, a word is accessed in two separate operations, reducing access efficiency. • The initial values for the USP and SSP registers are undefined. • Allocate the system stack area, user stack area, and data area so that they do not overlap. ■ System Stack Pointer (SSP) To use the system stack pointer (SSP), set the S flag in the condition code register (CCR) to "1". If the S flag is set to "1", the upper 8 bits of the address to be used for the stack operation are indicated by the system stack bank register (SSB). For more information on the condition code register (CCR), see Section 2.7.4 "Condition Code Register (PS: CCR)". For more information on the system stack bank register (SSB), see Section 2.7.9 "Bank Registers (PCB, DTB, USB, SSB, ADB)". ■ User Stack Pointer (USP) To use the user stack pointer (USP), set the S flag in the condition code register (CCR) to "0". If the S flag is set to "0", the upper 8 bits of the address to be used for the stack operation are indicated by the user stack bank register (USB). For more information on the condition code register (CCR), see Section 2.7.4 "Condition Code Register (PS: CCR)". For more information on the system stack bank register (SSB), see Section 2.7.9 "Bank Registers (PCB, DTB, USB, SSB, ADB)". 41 CHAPTER 2 CPU 2.7.3 Processor Status (PS) The processor status register (PS) contains CPU control bits and bits that indicate the CPU status. The PS register consists of the following three registers: • Condition code register (CCR) • Register bank pointer (RP) • Interrupt level mask register (ILM) ■ Processor Status (PS) Configuration The processor status register (PS) contains CPU control bits and bits that indicate the CPU status. Figure 2.7-8 Processor Status (PS) Configuration ILM Bit PS RP 15 14 13 12 11 10 CCR 9 8 ILM2 ILM1 ILM0 B4 B3 B2 B1 B0 7 6 5 4 3 2 1 0 I S T N Z V C ❍ Condition Code Register (CCR) This register consists of flags that are set to "1" or reset to "0" in accordance with instruction execution results or interrupts. For more information on the flags, see Section 2.7.4 "Condition Code Register (PS: CCR)". ❍ Register Bank Pointer (RP) This pointer points to the first address of the memory block (register bank) used as the generalpurpose register in the RAM area. There are 32 banks for general-purpose registers. Set values "00H to 1FH" in the RP to specify a bank. For the setting method and more information on this pointer, see Section 2.7.5 "Register Bank Pointer (PS: RP)". ❍ Interrupt Level Mask Register (ILM) This register indicates the level of an interrupt currently accepted by the CPU. The value is compared with that of the interrupt level setting bits (ICR: IL0 to IL2) in the interrupt control register (ICR00 to ICR15) set so that an interrupt request corresponds to each peripheral function (resource). For the setting method and more information on this register, see Section 2.7.6 "Interrupt Level Mask Register (PS: ILM)". 42 2.7 Dedicated Registers 2.7.4 Condition Code Register (PS: CCR) The condition code register (CCR) is an 8-bit register that consists of the following bits: • Bits that indicate the result of an arithmetic operation and the contents of transfer data • Bits that control the acceptance of an interrupt request ■ Condition Code Register (CCR) Configuration Refer to the programming manual for details about the status of the condition code register (CCR) during instruction execution. Figure 2.7-9 Condition Code Register (CCR) Configuration ILM RP CCR Bit 15 14 13 12 11 10 9 8 PS ILM2 ILM1 ILM0 B4 B3 B2 B1 B0 7 6 5 4 3 2 1 0 I S T N Z V C CCR initial value X01XXXXXB Interrupt enable flag Stack flag Sticky bit flag Negative flag Zero flag Overflow flag Carry flag X : Not used - : Undefined ❍ Interrupt enable flag (I) Interrupts are enabled when the I flag is set to "1", or disabled when the I flag is reset to "0", in response to any interrupt request other than software interrupts. The I flag is reset to "0" by an external or software reset. ❍ Stack flag (S) This flag indicates the pointer used for a stack operation. The user stack pointer (USP) is valid if the S flag is reset to "0". The system stack pointer (SSP) is valid if the S flag is set to "1". The S flag is set to "1" when an interrupt is accepted or when an external or software reset is asserted. For more information on the stack pointers, see Section 2.7.2 "Stack Pointers (USP, SSP)" ❍ Sticky bit flag (T) The T flag is set to "1" if the data shifted out of by the carry contains "1" during execution of a logical or arithmetic right shift instruction. Otherwise, the T flag is reset to "0". The T flag is also reset to "0" if the shift amount is zero. 43 CHAPTER 2 CPU ❍ Negative flag (N) The N flag is set to "1" if the most significant bit (MSB) of the general-purpose registers (RL0 to RL3) that store the operation result is "1". Otherwise, the N flag is reset to "0". For more information on general-purpose registers, see Section 2.8 "General-Purpose Registers". ❍ Zero flag (Z) The Z flag is set to "1" if the general-purpose registers (RL0 to RL3) that store the operation result are "0000H". Otherwise, the Z flag is reset to "0". ❍ Overflow flag (V) The V flag is set to "1" if an overflow occurs in a signed numeric value. Otherwise, the V flag is reset to "0". ❍ Carry flag (C) The C flag is set to "1" if a carry from the most significant bit or a borrow to the least significant bit occurs during an arithmetic operation. Otherwise, the C flag is reset to "0". 44 2.7 Dedicated Registers 2.7.5 Register Bank Pointer (PS: RP) The register bank pointer (RP) is a five-bit register that points to the first address of the general-purpose register bank currently used. ■ Register Bank Pointer (RP) Figure 2.7-10 Configuration of the Register Bank Pointer (RP) ILM RP CCR Bit 15 14 13 12 11 10 9 8 PS ILM2 ILM1 ILM0 B4 B3 B2 B1 B0 7 6 5 4 3 2 1 0 I S T N Z V C RP initial value 00000 B ■ General-Purpose Register Area and Register Bank Pointer The register bank pointer (RP) points to the relationship between the general-purpose register of the F2MC-16LX and the address in internal RAM. The relationship between the contents of the RP register and the address follows the conversion rules shown in Figure 2.7-11 "Conversion Rules for Physical Address of General-Purpose Register Area". Figure 2.7-11 Conversion Rules for Physical Address of General-Purpose Register Area Conversion formula [000180H + (RP) × 10H] When RP = 10H 000370 H 000280 H 000180 H Register bank 31 Register bank 16 Register bank 0 • The register bank pointer (RP) can assume values from 00H to 1FH. The first address of a register bank can be set to a value from 000180H to 00037FH. • Although an assembler instruction can use an 8-bit immediate value transfer instruction for transfer to the register bank pointer (RP). However, only the lower 5 bits of the data are valid. • A reset initializes the register bank pointer (RP) to 00000B. 45 CHAPTER 2 CPU 2.7.6 Interrupt Level Mask Register (PS: ILM) The interrupt level mask register (ILM) is a 3-bit register that indicates the level of the interrupt currently accepted by the CPU. ■ Interrupt Level Mask Register (ILM) See CHAPTER 6 "INTERRUPTS" for details about interrupts. Figure 2.7-12 Configuration of the Interrupt Level Mask Register (ILM) ILM RP CCR Bit 15 14 13 12 11 10 9 8 PS ILM2 ILM1 ILM0 B4 B3 B2 B1 B0 7 6 5 4 3 2 1 0 ILM initial value I S T N Z V C 000B The interrupt level mask register (ILM) indicates the level of the interrupt currently accepted by the CPU. A level of the interrupt currently accepted by the CPU can be set in the ILM register. The CPU does not accept any interrupt with an interrupt level lower than that set in the ILM register. • A reset sets the highest interrupt level in the ILM register, causing no interrupt to be accepted. • Although an assembler instruction can use an 8-bit immediate value transfer instruction for transfer to the interrupt level mask register (ILM). However, only the lower 3 bits of the data are valid. Table 2.7-3 Interrupt Level Mask Register (ILM) and Interrupt Level Priority 46 ILM2 ILM1 ILM0 Interrupt level 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 Interrupt level priority Highest (interrupts disabled) Lowest 2.7 Dedicated Registers 2.7.7 Program Counter (PC) The program counter (PC) is a 16-bit counter that indicates the lower 16 bits of the address of the next instruction to be executed by the CPU. ■ Program Counter (PC) The program bank register (PCB) specifies the upper 8 bits, and the program counter (PC) specifies the lower 16 bits, of the address of the next instruction to be executed by the CPU. The address of the next instruction to be executed is as shown in Figure 2.7-13 "Program Counter (PC)". The contents of the PC are updated by conditional branch instructions, subroutine call instructions, interrupts, and resets. The PC can also be used as a base pointer for reading operands. For more information on the PCB, see Section 2.7.9 "Bank Registers (PCB, DTB, USB, SSB, ADB)". Figure 2.7-13 Program Counter (PC) Upper 8 bits PCB FEH Lower 16 bits PC ABCDH FEABCD H Next instruction to be executed Note: The PC and PCB cannot be rewritten directly by a program (instructions such as MOVPC and #0FFH). 47 CHAPTER 2 CPU 2.7.8 Direct Page Register (DPR) The direct page register (DPR) is an 8-bit register that specifies bits 8 to 15 (addr8 to addr15) of the operand address when a short direct addressing instruction is executed. A reset initializes the DPR to "01H". ■ Direct Page Register (DPR) Figure 2.7-14 Physical Address Generation by the Direct Page Register (DPR) DTB register DPR register AAAAAAAA BBBBBBBB Direct address during instruction CCCCCCCC MSB bit24 bit16 bit15 bit8 24-bit AAAAAAAA BBBBBBBB Physical address LSB bit7 bit0 CCCCCCCC MSB : Most Significant Bit LSB : Least Significant Bit Figure 2.7-15 Example of Direct Page Register (DPR) Setting and Data Access MOV S:56H #5AH Instruction execution results Upper 8 bits Lower 8 bits DTB register 12H DPR register 34H 123458 H MSB : Most Significant Bit LSB : Least Significant Bit 48 123456 H 5AH 123454 H MSB LSB 2.7 Dedicated Registers 2.7.9 Bank Registers (PCB, DTB, USB, SSB, ADB) Bank registers specify the highest 8-bit address by bank addressing. The five bank registers are as follows: • Program bank register (PCB) • Data bank register (DTB) • User stack bank register (USB) • System stack bank register (SSB) • Additional bank register (ADB) The PCB, DTB, USB, SSB, and ADB registers indicate the individual memory banks where the program space, data space, user stack space, system stack space, and additional space are located. ■ Bank Registers (PCB, DTB, USB, SSB, ADB) ❍ Program bank register (PCB) The PCB is a bank register that specifies the program (PC) space. The PCB is rewritten whenever a JMPP, CALLP, RETP, or RETI instruction causes a branch anywhere within the 16M-byte space, when an software interrupt instruction is executed, when a hardware interrupt occurs, or when an exception occurs. ❍ Data bank register (DTB) The DTB is a bank register that specifies the data (DT) space. ❍ User stack bank register (USB), system stack bank register (SSB) The USB and SSB are bank registers that specify the stack (SP) space. Either the USB or SSB is used depending on the value of the S flag in the processor status register (PS:CCR). For more information, see Section 2.7.2 "Stack Pointer (USP, SSP)". ❍ Additional bank register (ADB) The ADB is a bank register that specifies the additional (AD) space. ❍ Bank settings and data access All bank registers are 8 bits in length. A reset initializes the PCB to "FFH" and the DTB, USB, SSB, and ADB to "00H". The PCB can be read but cannot be written to. Bank registers other than the PCB can be read and written to. Note: The MB90M405 series supports up to the memory space contained in the device. See Section 2.4.2 "Address Specification by Bank Addressing" for the operation of each register. 49 CHAPTER 2 CPU 2.8 General-Purpose Registers The general-purpose registers are a memory block allocated in RAM at 000180H to 00037FH as register banks, each of which consists of eight 16-bit segments. The general-purpose registers can be used as general-purpose 8-bit registers (byte registers R0 to R7), 16-bit registers (word registers RW0 to RW7), or 32-bit registers (long-word registers RL0 to RL7). General-purpose registers can access RAM with a short instruction at high speed. Since general-purpose registers are blocked into register banks, protection of register contents and division into function units can readily be performed. When a generalpurpose register is used as a long-word register, it can be used as a linear pointer that directly accesses the entire space. ■ Configuration of a General-Purpose Register General-purpose registers exist in RAM at "000180H" to "00037FH" and are configured as 32 banks. The register bank pointer (RP) specifies the bank. The RP determines the first address of each bank as shown in the following equation. 16 bits multiplied by 8 are defined as one register bank. First address of general-purpose register = 000180H + RP x 10H For more information on the PR, see Section 2.7.5 "Register Bank Pointer (PS: RP)". Figure 2.8-1 Location and Configuration of the General-Purpose Register Banks in the Memory Space Built-in RAM 02CEH R6 R7 Byte address 02CF H RW7 02CCH R4 R5 02CDH RW6 Byte address 000380 H Register bank 31 000370 H Register bank 30 000360 H 02CAH R2 R3 02CBH RW5 0002E0 H Register bank 21 0002D0 H 02C8 H 02C9 H RW4 0002C0 H Register bank 19 0002B0 H 02C6 H R1 R0 RW3 02C4 H RW2 02C5 H 02C2 H RW1 02C3 H 02C0 H RW0 02C1 H Register bank 20 RP 14H LSB 0001B0 H Register bank 2 0001A0 H Register bank 1 000190 H Register bank 0 000180 H 50 16 bits 02C7 H RL3 RL2 RL1 RL0 MSB Conversion formula [000180H + RP × 10H] R0 to R7 RW0 to RW7 RL0 to L3 MSB LSB : : : : : Byte registers Word registers Long-word registers Most Significant Bit Least Significant Bit 2.8 General-Purpose Registers Note: The register bank pointer (RP) is initialized to 00H after a reset. ■ Register Bank Register banks can be used as general-purpose registers (byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3) for various arithmetic operations and pointers. Long word registers can be used also as linear pointers that directly access all the memory space. A reset does not initialize the contents of the register bank as with RAM but the status before reset is retained. A power-on reset, however, makes the contents undefined. Table 2.8-1 Typical Functions of General-Purpose Registers Register name Function R0 to R7 Used as an operand in various instructions Note: R0 is also used as a barrel shift counter and an instruction normalization counter RW0 to RW7 Used as a pointer Used as an operand in various instructions Note: RW0 is used also as a string instruction counter RL0 to RL3 Used as a long pointer Used as an operand in various instructions 51 CHAPTER 2 CPU 2.9 Prefix Codes Prefix codes are placed before an instruction to partially change the operation of the instruction. The three types of prefix codes are as follows: • Bank select prefix (PCB, DTB, ADB, SPB) • Common register bank prefix (CMR) • Flag change suppression prefix (NCC) ■ Prefix Codes ❍ Bank select prefix (PCB, DTB, ADB, SPB) A bank select prefix is placed before an instruction to select the memory space to be accessed by the instruction regardless of the addressing method. For more information, see Section 2.9.1 "Bank Select Prefix (PCB, DTB, ADB, SPB)". ❍ Common register bank prefix (CMR) The common register bank prefix is placed before an instruction that accesses a register bank to change the register accessed by the instruction to the common bank (register bank selected when RP = 0) at 000180H to 00018FH regardless of the current register bank pointer (RP) value. For more information, see Section 2.9.2 "Common Register Bank Prefix (CMR)". ❍ Flag change suppression prefix (NCC) The flag change suppression prefix code is placed before an instruction to suppress a flag change accompanying the execution of the instruction. For more information, see Section 2.9.3 "Flag Change Suppression Prefix (NCC)". 52 2.9 Prefix Codes 2.9.1 Bank Select Prefix (PCB, DTB, ADB, SPB) Memory space used for data access is determined for each addressing method. However, placing a bank select prefix before an instruction selects the memory space to be accessed by the instruction regardless of the addressing method. ■ Bank Select Prefixes (PCB, DTB, ADB, SPB) Table 2.9-1 Bank Select Prefix Codes Bank select prefix Selected space PCB Program space DTB Data space ADB Additional space SPB When the value of the S flag in the condition code register (CCR) is 0 and the user stack space is 1, the system stack space is used. If a bank select prefix is used, some instructions perform an unexpected operation. Table 2.9-2 Instructions Not Affected by Bank Select Prefix Codes Instruction type String instruction Instruction MOVS SCEQ FILS Stack operation instruction PUSHW I/O access instruction MOV MOVW MOV MOV MOVB SETB BBC WBTC Interrupt return instruction RETI A,io A,io io, A io,#imm8 A,io:bp io:bp io:bp, rel io,bp Effect of bank select prefix MOVSW SCWEQ FILSW The bank register specified by the operand is used irrespective of whether a prefix is used. POPW When the S flag is 0, the user stack bank (USB) is used whether or not there is a prefix. When the S flag is 1, the system stack bank (SSB) is used regardless of whether a prefix is used. MOVX A,io MOVW MOVW MOVB CLRB BBS WBTS io, A io,#imm16 io:bp,A io:bp io:bp, rel io:bp The I/O space (000000H to 0000FFH) is accessed whether or not there is a prefix. The system stack bank (SSB) is used whether or not a prefix is used. 53 CHAPTER 2 CPU Table 2.9-3 Instructions Whose Use Requires Caution When Bank Select Prefix 54 Instruction type Instruction Explanation Flag change instruction ANDCCR, #imm8 ORCCR, #imm8 The effect of the prefix extends to the next instruction. ILM setting instruction MOVILM, #imm8 The effect of the prefix extends to the next instruction. PS return instruction POPWPS Do not place a bank select prefix before the PS return instruction. 2.9 Prefix Codes 2.9.2 Common Register Bank Prefix (CMR) Placing the common register bank prefix (CMR) before an instruction that accesses a register bank changes the register accessed by it to the common bank at "000180H" to "00018FH" (register bank selected when RP = "00H") regardless of the current register bank pointer (RP) value. ■ Common Register Bank Prefix (CMR) To facilitate data exchange between multiple tasks, the F2MC-16LX provides a common bank that can be commonly used by these tasks. The common bank is located at addresses "000180H" to "00018FH". However, be careful when you use this prefix with the instructions listed in Table 2.9-4 "Instructions Whose Use Requires Caution When the Common Register Bank Prefix (CMR) Is Used ". Table 2.9-4 Instructions Whose Use Requires Caution When the Common Register Bank Prefix (CMR) Is Used Instruction type Instruction Explanation MOVSMOVSW String instruction SCEQ FILS Flag change instruction Do not place the CMR prefix before the string instruction. SCWEQ FILSW OR CCR,#imm8 The effect of the prefix extends to the next instruction. AND CCR,#imm8 PS return instruction POPW PS The effect of the prefix extends to the next instruction. ILM setting instruction MOV ILM,#imm8 The effect of the prefix extends to the next instruction. 55 CHAPTER 2 CPU 2.9.3 Flag Change Suppression Prefix (NCC) The flag change suppression prefix (NCC) code is set before an instruction to suppress a flag change accompanying the execution of the instruction. ■ Flag Change Suppression Prefix (NCC) Use the flag change suppression prefix (NCC) to suppress unnecessary flag changes. Changes in the T, N, Z, V, and C flags can be suppressed. Be careful when you use this prefix with the instructions listed in Table 2.9-5 "Instructions Whose Use Requires Caution When the Flag Change Suppression Prefix (NCC) Is Used ". For more information on the T, N, Z, V, and C flags, see Section 2.7.4 "Condition Code Register (PS: CCR)". Table 2.9-5 Instructions Whose Use Requires Caution When the Flag Change Suppression Prefix (NCC) Is Used Instruction type String instruction Instruction MOVS SCEQ FILS MOVSW SCWEQ FILSW Explanation Do not place the NCC prefix before the string instruction. AND CCR, #imm8 OR CCR, #imm8 The condition code register (CCR) changes as defined in the instruction specification whether or not a prefix is used. The effect of prefix extends to the next instruction. PS return instruction POPW PS The condition code register (CCR) changes as defined in the instruction specification whether or not a prefix is used. The effect of prefix extends to the next instruction. ILM setting instruction MOV ILM, #imm8 The effect of prefix extends to the next instruction. Flag change instruction Interrupt instruction Interrupt return instruction Context switch instruction 56 INT #vct8 INT adder16 RETI JCTX @A INT9 INTP addr24 The condition code register (CCR) changes as defined in the instruction specification whether or not a prefix is used. The condition code register (CCR) changes as defined in the instruction specification whether or not a prefix is used. 2.9 Prefix Codes 2.9.4 Restrictions on Prefix Codes The following restrictions are imposed on the use of prefix codes: • Interrupt requests are not accepted during the execution of prefix codes and interrupt suppression instructions. • If a prefix code is placed before an interrupt instruction, the effect of the prefix code is delayed. • If consecutively placed prefix codes conflict, the last prefix code is valid. ■ Prefix Codes and Interrupt Suppression Instructions Table 2.9-6 Prefix Codes and Interrupt Suppression Instructions Interrupt suppression instructions (instructions that delay the effect of prefix codes) Prefix codes PCB DTB ADB SPB CMR NCC Instructions that do not accept interrupt requests MOV OR AND POPW ILM, #imm8 CCR, #imm8 CCR, #imm8 PS ❍ Interrupt Suppression As shown in Figure 2.9-1 "Interrupt Suppression", an interrupt request generated during the execution of prefix codes and interrupt instructions is not accepted. The interrupt is not processed until the first instruction that is not governed by a prefix code or that is not an interrupt suppression instruction is executed. Figure 2.9-1 Interrupt Suppression Interrupt suppression instruction (a) (a) Ordinary instruction Interrupt request generated Interrupt accepted 57 CHAPTER 2 CPU ❍ Delay of the effect of prefix codes If a prefix code is placed before an interrupt/hold suppression instruction as shown in Figure 2.9-2 "Interrupt Suppression Instructions and Prefix Codes", the prefix code takes effect on the first instruction executed after the interrupt/hold suppression instruction. Figure 2.9-2 Interrupt Suppression Instructions and Prefix Codes Interrupt suppression instruction MOV A,FFH NCC MOV ILM,#imm8 ADD A,01H CCR:XXX10XXB CCR:XXX10XXB NCC does not cause the CCR to change. ■ Consecutive Prefix Codes When consecutive conflicting prefix codes (PCB, ADB, DTB, and SPB) are specified, the last prefix code is valid. Figure 2.9-3 Consecutive Prefix Codes Prefix code ADB DTB PCB ADD A,01H Prefix code PCB is valid. 58 CHAPTER 3 RESETS This chapter describes resets for the MB90M405 series. 3.1 "Resets" 3.2 "Reset Causes and Oscillation Stabilization Wait Time" 3.3 "External Reset Pin" 3.4 "Reset Operation" 3.5 "Reset Cause Bits" 3.6 "Status of Pins in a Reset" 59 CHAPTER 3 RESETS 3.1 Resets If a reset cause is generated, the CPU stops the current execution process and waits for the reset to be cleared. When the reset is cleared, the CPU begins processing at the address indicated by the reset vector. There are four causes of a reset: • Power-on reset (at power-on) • Watchdog timer overflow (during the use of a watchdog timer) • External reset input via the RST pin • Setting "0" in the internal reset signal generation bit (RST) of the low power consumption mode control register (software reset) ■ Reset Causes Table 3.1-1 Reset Causes Machine clock Watchdog timer Oscillation stabilization wait Main clock frequency (MCLK) Stop No Software "0" written to the internal reset signal generation bit (RST) of the low power consumption mode control register (LPMCR) Main clock frequency (MCLK) Stop No Watchdog timer Watchdog timer overflow Main clock frequency (MCLK) Stop No Power-on Power-on Main clock frequency (MCLK) Stop Yes Type of reset Cause "L" level input to RST pin External pin MCLK: Main clock frequency (oscillation clock frequency divided by 2: 2/HCLK) ❍ External reset An external reset is generated if the external reset terminal (RST terminal) is set to the "L" level. The "L" level must be input at least for 16 machine cycles (16/φ). While the machine clock is used, no oscillation stabilization wait time is placed even if a reset occurs due to the "L" level input to the external reset pin. 60 3.1 Resets Reference: If the external reset pin is set to the "L" level while an instruction is being executed (while a transfer instruction such as MOV is being executed), the external reset input becomes valid after the completion of processing by the instruction being executed. For a string-processing instruction (such as MOVS), however, the reset input may become valid before the transfer resulting from the specified counter value is completed. If the external reset pin is set to the "L" level, the port pin enters the reset status regardless of the instruction execution cycle (if set to the "L" level, the operation is asynchronous). ❍ Software reset A software reset is a reset for three machine cycles (3/φ) generated by writing "0" to the internal reset signal generation bit (RST) of the low power consumption mode control register (LPMCR). The oscillation stabilization wait time is not required for software resets. ❍ Watchdog timer reset A watchdog timer reset is generated unless "0" is written to the watchdog timer control bit (WTE) of the watchdog timer control register (WDTC) within the time specified in the interval time setting bits (WT1, WT0) of the WDTC after the watchdog timer is activated. ❍ Power-on reset A power-on reset is generated when the power is turned on. The oscillation stabilization wait time is fixed at 217/HCLK (about 31.25 ms if the source oscillation is 4.194 MHz). A reset occurs after the oscillation stabilization wait time has elapsed. Information: Definition of clocks HCLK: Oscillation clock frequency (Clock supplied from the oscillation pin) MCLK: Main clock frequency (Clock obtained by dividing the source oscillation by two) φ : Machine clock (CPU operating clock) 1/φ: Machine cycle (CPU operating clock cycle) See Section 4.1 "Clocks" for details about clocks. 61 CHAPTER 3 RESETS 3.2 Reset Causes and Oscillation Stabilization Wait Time The F2MC-16LX has four reset causes. The oscillation stabilization wait time for a reset depends on the reset cause. ■ Reset Causes and Oscillation Stabilization Wait Time Table 3.2-1 Reset Causes and Oscillation Stabilization Wait Time Reset cause Oscillation stabilization wait time The corresponding time interval for an oscillation clock frequency of 4 MHz is given in parentheses. Power-on reset 217/HCLK (about 31.25 ms) Watchdog timer None. (The WS1 and WS0 bits are initialized to "11B".) External reset from RST pin None. (The WS1 and WS0 bits are initialized to "11B".) Software reset None. (The WS1 and WS0 bits are initialized to "11B".) HCLK: Oscillation clock frequency (MHz) Table 3.2-2 Oscillation Stabilization Wait Time Depending on Settings of Clock Selection Register (CKSCR) WS1 WS0 Oscillation stabilization wait time The corresponding time interval for an oscillation clock frequency of 4.194 MHz is given in parentheses. 0 0 210/HCLK (about 244 μs) 0 1 213/HCLK (about 1.95 ms) 1 0 215/HCLK (about 7.81 ms) 1 1 217/HCLK (about 31.25 ms) HCLK: Oscillation clock frequency (MHz) Note: Oscillation clock oscillators generally require an oscillation stabilization wait time from the start of oscillation until they stabilize at their natural frequency. Be sure to set a proper oscillation stabilization wait time for the oscillator to be used. ■ Oscillation Stabilization Wait Reset Status For a power-on reset or an external reset in stop mode, the reset operation occurs after the oscillation stabilization wait time generated by the timebase timer elapses. Unless the external reset input is released, the reset operation occurs after the external reset is released. 62 3.3 External Reset Pin 3.3 External Reset Pin An internal reset occurs if an "L" level signal is input to the external reset pin (RST pin). In the MB90M405 series, a reset occurs in synchronization with the CPU operating clock. However, resets of external pins (I/O ports) occur asynchronously. ■ Block Diagrams of the External Reset Pin ❍ Block diagram of components related to internal resets Figure 3.3-1 Block Diagram of Components Related to Internal Resets Rp RST Pch Pin Nch CPU operating clock (PLL multiplier circuit with a frequency of HCLK divided by two) Synchronization circuit HCLK: Oscillation clock frequency Internal reset signal Input buffer Note: The machine clock is required to initialize the internal circuit. When a reset signal is input, the clock must be supplied from the oscillation pin. ❍ Block diagram of components related to internal resets for external pins (I/O ports) Figure 3.3-2 Block Diagram of Components Related to Internal Resets for External Pins Rp RST Pch Pin Nch Reset signal to external pin HCLK: Oscillation clock frequency Input buffer 63 CHAPTER 3 RESETS 3.4 Reset Operation When a reset is cleared, the mode data and the reset vector stored in the internal or external memory are fetched. The mode data register determines the CPU operating mode. The reset vector determines the execution start address used after a reset sequence ends. ■ Overview of Reset Operation Figure 3.4-1 Reset Operation Flow Power-on reset Stop mode During a reset External reset Software reset Watchdog timer reset Oscillation stabilization wait and reset state Fetching the mode data Pin setting in bus mode Reset sequence Fetching the reset vector Program operation CPU executes an instruction, fetching instruction codes from the address indicated by the reset vector. ■ Mode Pins Setting the mode pins (MD0 to MD2) specifies how to fetch the mode data and the reset vector. Fetching the mode data and the reset vector is performed in the reset sequence. See Section 7.2 "Mode Pins (MD2 to MD0)" for details about mode pins. 64 3.4 Reset Operation ■ Mode Data Fetch When a reset is cleared, the CPU transfers mode data to the mode data register. After the mode data is transferred, the reset vector is transferred to the program counter (PC) and the program counter bank register (PCB). The mode data register can determine the bus mode and the bus width. The reset vector can determine the program start address. For more information, see CHAPTER 7 "SETTING A MODE". Figure 3.4-2 Transfer of Reset Vector and Mode Data Memory space F2MC-16LX CPU core Mode register FFFFDF H Mode data FFFFDE H Bits 23 to 16 of the reset vector FFFFDD H Bits 15 to 8 of the reset vector FFFFDC H Bits 7 to 0 of the reset vector Micro ROM Reset sequence PCB PC ❍ Mode data register (address: FFFFDFH) The mode data register setting can be changed while a reset sequence is executed. The mode data register setting is valid after a reset vector is fetched. No new contents can be written to the mode data register even if an instruction is used to specify mode data at "FFFFDF H". For more information, see Section 7.3 "Mode Data Register". ❍ Reset vector (address: "FFFFDCH" to "FFFFDEH") The reset vector determines the program start address used after a reset is cleared. A program is executed from the address specified in the reset vector. 65 CHAPTER 3 RESETS 3.5 Reset Cause Bits Read the watchdog timer control register (WDTC) to identify a reset cause. ■ Reset Cause Bits Read the reset cause flag bits PONR, WRST, ERST, and SRST of the watchdog timer control register (WDTC) to identify a reset cause. If a reset cause needs to be identified after a reset is cleared, read the reset cause flag bits PONR, WRST, ERST, and SRST of the watchdog timer control register (WDTC). The PONR, WRST, ERST, and SRST bits are cleared to "0" if the watchdog timer control register (WDTC) is read. Figure 3.5-1 Block Diagram of Reset Cause Bits RST pin Power-on No periodic clear RST=L External reset request detection circuit Power-on detection circuit Watchdog timer reset generation detection circuit Watchdog timer control register (WDTC) R S F/F Q R S F/F Q PONR R Q ERST 66 S F/F R F/F Q WRST F2MC 16LX Internal bus Set Reset Output Flip Flop LPMCR, RST bit writing detection circuit Clear S S : R : Q : F/F : Clear of software reset bit SRST Delay circuit Reading of watchdog timer control register (WDTC) 3.5 Reset Cause Bits ■ Correspondence between Reset Cause FLAG Bits and Reset Causes Figure 3.5-2 Configuration of Reset Cause Bits (Watchdog Timer Control Register) Watchdog timer control register (WDTC) Address Bit 0000A8 H 7 6 PONR - R - 5 4 3 2 WRST ERST SRST WTE R R R W 1 0 WT1 WT0 W Initial value 1XXXX111B W Reset cause flag bit R W X - : : : : Read only Write only Undefined Undefined bit Table 3.5-1 Correspondence between Reset Cause Bits and Reset Causes Reset cause PONR WRST ERST SRST Power-on reset 1 X X X Watchdog timer overflow * 1 * * External reset request via RST pin * * 1 * Software reset request (LPMCR:RST) * * * 1 *: Previous state retained X: Undefined 67 CHAPTER 3 RESETS ■ Notes about Reset Cause Bits ❍ Multiple reset causes generated at the same time When multiple reset causes are detected, the corresponding reset cause bits of the watchdog timer control register (WDTC) are set to "1". For example, if an external reset and a watchdog timer reset occur at the same time, the reset cause flag bits (ERST, WRST) of the watchdog timer control register (WDTC) are set to "1". ❍ Power-on reset If a power-on reset occurs, the PONR bit of the watchdog timer control register (WDTC) is set to "1" and the WRST, ERST, and SRST bits are undefined. If the PONR bit is set to "1", the contents of the WRST, ERST, and SRST bits should be ignored. ❍ Clearing the reset cause bits The PONR, WRST, ERST, and SRST bits are cleared to "0" if the watchdog timer control register (WDTC) is read. In other words, these reset cause flag bits are not cleared to "0" unless the watchdog timer control register (WDTC) is read even if a reset occurs. Note: The value of the WDTC register cannot be assured if the power is turned on under conditions where a power-on reset does not occur. 68 3.6 Status of Pins in a Reset 3.6 Status of Pins in a Reset This section describes the status of pins when a reset occurs. ■ Status of Pins during a Reset The status of pins during a reset is determined by the settings of the mode pins (MD2 to MD0 = 011B). ❍ When internal vector mode is specified All the I/O pins are set to high impedance output, and the mode data is read from the internal ROM. ■ Status of Pins after Mode Data is Read The status of pins after mode data is read is determined by the mode data (M1 and M0 = 00B). ❍ When single-chip mode is specified (M1 and M0 = 00B) All the I/O pins become high impedance output, and the mode data is read from the internal ROM. Note: Specify an external pin level that disables external circuits. 69 CHAPTER 3 RESETS 70 CHAPTER 4 CLOCKS This chapter describes the clocks used by MB90M405 series. 4.1 "Clocks" 4.2 "Block Diagram of the Clock Generation Block" 4.3 "Clock Selection Register (CKSCR)" 4.4 "Clock Mode" 4.5 "Oscillation Stabilization Wait Time" 4.6 "Connection of an Oscillation or an External Clock to the Microcontroller" 71 CHAPTER 4 CLOCKS 4.1 Clocks The clock generation block controls the operating clock of the CPU and peripheral functions (resources). The following four clocks are available: • Oscillation clock • Main clock • PLL clock • Machine clock ■ Clocks The clock generation block contains the oscillation circuit and the PLL clock multiplier circuit. The clock generation block controls the oscillation stabilization wait time and PLL clock multiplication as well as controls the operation of switching the clock with a clock selector. ❍ Oscillation clock frequency (HCLK) The oscillation clock is generated either from an oscillator connected to the X0 and X1 pins or by input of an external clock. ❍ Main clock (MCLK) The main clock, which is the oscillation clock divided by 2, supplies the clock input to the timebase timer and the clock selector. ❍ PLL clock (PCLK) The PLL clock is obtained by multiplying the oscillation clock in the internal PLL clock multiplier circuit. Four different clocks (multiplied by 1 through 4) can be generated. ❍ Machine clock(φ) The machine clock is the operating clock of the CPU and peripheral functions (resources). One machine clock cycle is called a machine cycle. Either the main clock or a PLL clock can be selected. Reference: PLL oscillation, which may be from 3 to 16.8 MHz, varies depending on the operating voltage and the frequency multiplier. For more information, see the "data sheet". Note: The maximum operating frequency of the CPU and the peripheral function circuits is 16.8 MHz. If a frequency multiplier is specified that results in a frequency higher than the maximum operating frequency, devices will not operate normally. For example, if an oscillation clock of 16.8 MHz is generated, a multiplier of 1 or division by 2 can be specified. 72 4.2 Block Diagram of the Clock Generation Block 4.2 Block Diagram of the Clock Generation Block The clock generation block consists of the following five blocks: • System clock generation circuit • PLL multiplier circuitS • Clock selector • Clock selection register (CKSCR) • oscillation stabilization wait time selector ■ Block Diagram of the Clock Generation Block Figure 4.2-1 Block Diagram of the Clock Generation Block Standby control circuit Low power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 Reserved CPU intermittent operation cycles selector RST INT Reset/interrupt control circuit Operating clock control circuit CPU clock control circuit Peripheral clock control circuit Operating clock selector CPU operating clock Peripheral function operating clock Oscillation stabilization wait time selector PLL multiplier circuit Reserved MCM WS1 WS0 Reserved MCS CS0 CS1 Clock selection register (CKSCR) X1 X0 Oscillation circuit Divide-by-2 Timebase timer Watchdog timer Reference: Figure 4.2-1 "Block Diagram of the Clock Generation Block" includes the standby control circuit and the timebase timer circuit. ❍ System clock generation circuit The system clock generation circuit generates an oscillation clock from an oscillator connected to the X0 and X1 pins or by input of an external clock. Reference: Figure 4.2-1 "Block Diagram of the Clock Generation Block" includes the standby control circuit and the timebase timer circuit. 73 CHAPTER 4 CLOCKS ❍ PLL multiplier circuit The PLL multiplier circuit multiplies the oscillation clock and supplies the resultant clock to the clock selector. ❍ Clock selector The clock selector selects the clock to be supplied to the CPU and peripheral clock control circuits from among the main clock and the PLL clock. ❍ Clock selection register (CKSCR) The clock selection register selects the machine clock and determines the oscillation stabilization wait time and the PLL clock multiplier, etc. ❍ oscillation stabilization wait time selector The oscillation stabilization wait time selector selects the oscillation stabilization wait time of the oscillation clock when the stop mode is cleared. One of the four time-base timer outputs is selected to determine the oscillation stabilization wait time. 74 4.3 Clock Selection Register (CKSCR) 4.3 Clock Selection Register (CKSCR) The clock selection register (CKSCR) switches the machine clock and sets the oscillation stabilization wait time and the PLL clock multiplier, etc. ■ Configuration of the Clock Selection Register (CKSCR) Figure 4.3-1 Configuration of the Clock Selection Register (CKSCR) Bit CKSCR 15 14 13 12 11 10 09 08 RESV MCM WS1 WS0 RESV MCS CS0 CS1 R/W R/W R/W R/W R/W Initial value 11111100B Multiplier selection bit CS1 CS0 The value in parenthesis is the clock resulting from the oscillation clock of 4.2 MHz. 0 0 1 1 0 1 0 1 1 × HCLK (4.2MHz) 2 × HCLK (8.4MHz) 3 × HCLK (12.6MHz) 4 × HCLK (16.8MHz) Machine clock set PLL clock is set. Main clock is set. MCS 0 1 Oscillation stabilization wait time set bits The corresponding time interval for an WS1 WS0 oscillation clock frequency of 4.2 MHz is given in parentheses. 0 0 1 1 0 1 0 1 210/ HCLK (Approx. 243.8 μs) 213/ HCLK (Approx. 1.95 ms) 215/ HCLK (Approx. 7.81 ms) 217/ HCLK (Approx. 31.25 ms) Machine clock indication bit MCM A PLL clock is being as the machine clock. 0 1 The main clock is being as the machine clock. Reserved bit RESV 0 must always be written to these bits. HCLK R/W R - : : : : : Oscillation clock frequency Read/write Read only Undefined bit Initial value Reference: A reset initializes the machine clock selection bit to the main clock setting. 75 CHAPTER 4 CLOCKS Table 4.3-1 Function Description of Each Bit of the Clock Selection Register (CKSCR) Bit name Function bit 15 bit 11 RESV: Reserved bit Note: Always set "0". bit 14 MCM: Machine clock indication bit • bit 13 bit 12 WS1, WS0: oscillation stabilization wait time selection bits • • • • • • This bit indicates whether the main clock or a PLL clock has been selected as the machine clock. When this bit is set to "0", a PLL clock has been selected. When this bit is set to "1", the main clock has been selected. If the machine clock selection bit (MCS) is set to "0" and MCM is set to "1", the PLL clock oscillation stabilization wait time is in effect. These bits select the oscillation stabilization wait time for the oscillation clock after the stop mode has been cleared due to an external interrupt. A reset cause initializes these bits to "11B". Specify an oscillation stabilization wait time appropriate for the oscillator used. bit 10 MCS: Machine clock selection bit • This bit specifies whether the main clock or a PLL clock is selected as the machine clock. • When this bit is set to "0", a PLL clock is selected. • When this bit is set to "1", the main clock is selected. • If this bit has been set to "1" and is reset to "0", the oscillation stabilization wait time for the PLL clock starts. As a result, the time-base timer counter and the interrupt request flag bit (TBOF) of the time-base timer counter control register (TBTC) are cleared to "0". • For PLL clocks, the oscillation stabilization wait time is fixed to 214/ HCLK. The oscillation stabilization wait time is about 3.9 ms if the oscillation clock frequency is 4.194 MHz.) • When the main clock has been selected, the oscillation clock divided by 2 is used as the machine clock. The machine clock frequency is 2 MHz if the oscillation clock frequency is 4 MHz. • A reset initializes this bit to 1. Note: The MCS bit set to "1" can be reset to "0" while the interrupt request enable bit (TBIE) of the time-base timer counter control register (TBTC) or the interrupt level mask register (ILM) are set to disable timer-base timer interrupt requests. bit 9 bit 8 CS1, CS0: Multiplier selection bits • These bits select a PLL clock multiplier. • One of the four multipliers can be selected. • A reset initializes these bits to "00B". Note: These bits cannot be set while the machine clock selection bit (MCS) or the machine clock indication bit (MCM) is set to "0". Set these bits only after setting the MCS bit to "1". HCLK: Oscillation clock frequency 76 4.4 Clock Mode 4.4 Clock Mode Two clock modes are provided: main clock mode and PLL clock mode. ■ Main Clock Mode and PLL Clock Mode ❍ Main clock mode In main clock mode, the main clock is used as the operating clock of the CPU and peripheral resources while the PLL clocks are disabled. ❍ PLL clock mode In PLL clock mode, a PLL clock is used as the machine clock of the CPU and peripheral functions (resources). Specify a PLL clock multiplier in the multiplier selection bits (CS1 and CS0) of the clock selection register (CKSCR). ■ Clock Mode Transition Setting the machine clock selection bit (MCS) of the clock selection register (CKSCR) causes switching between main clock mode and PLL clock mode. ❍ Switching from main clock mode to PLL clock mode When the MCS bit of the CKSCR that is set to "1" is reset to "0", switching from the main clock to a PLL clock occurs after the PLL clock oscillation stabilization wait time (214/HCLK) has elapsed. ❍ Switching from PLL clock mode to main clock mode When the MCS bit of the CKSCR that is set to "0" is reset to "1", switching from a PLL clock to the main clock occurs when the edges of the PLL clock and the main clock coincide (after 1 to 8 PLL clocks). Note: Before setting the peripheral functions (resources) after the machine clock switching, make sure that the machine clock has been switched by referring to the MCM bit of the CKSCR. ■ Selection of a PLL Clock Multiplier Set the multiplier selection bits (CS1 and CS0) of the CKSCR to "00B" and "11B" to set one of the four PLL clock multipliers (1 through 4). 77 CHAPTER 4 CLOCKS ■ Machine Clock Either the main clock or a PLL clock is used as the machine clock. The machine clock is an operating clock of the CPU and peripheral functions (resources). Set either the main clock or a PLL clock in the MCS bit of the CKSCR. Figure 4.4-1 Status Change Diagram for Machine Clock Selection Power-on Main MCS = "1" MCM = "1" CS1, CS0 = "XX" (1) (6) (7) (7) (7) Main → PLLx MCS = "0" MCM = "1" CS1, CS0 = "XX" PLL1 → Main MCS = "1" MCM = "1" CS1, CS0 = "00B" (6) PLL2 → Main MCS = "1" MCM = "0" CS1, CS0 = "01B" (6) PLL3 → Main MCS = "1" MCM = "0" CS1, CS0 = "10B" (7) (6) PLL4→ Main MCS = "1" MCM = "0" CS1, CS0 = "11B" (6) (2) (3) (4) (5) PLL1: Multiplied of 1 MCS = "0" MCM = "0" CS1, CS0 = "00B" PLL2: Multiplied of 2 MCS = "0" MCM = "0" CS1, CS0 = "01B" PLL3: Multiplied of 3 MCS = "0" MCM = "0" CS1, CS0 = "10B" PLL4: Multiplied of 4 MCS = "0" MCM = "0" CS1, CS0 = "11B" (1) The MCS bit is cleared. (2) The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 00B. (3) The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 01B. (4) The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 10B. (5) The PLL clock oscillation stabilization wait ends with CS1 and CS0 = 11B. (6) The MCS bit is set (including hardware standby and watchdog timer resets). (7) PLL clock and main clock frequency synchronization timing MCS : Machine clock set bit of CKSCR MCM : Machine clock indication bit of CKSCR CS1, CS0 : Multiplier set bits of CKSCR Note: The initial value for the machine clock setting is main clock (CKSCR:MCS = 1). 78 4.5 Oscillation Stabilization Wait Time 4.5 Oscillation Stabilization Wait Time Whenever the power is turned on, or whenever stop mode is cleared, oscillation begins following a state in which there was no oscillation. Accordingly, an oscillation stabilization wait time is required. Also, whenever the switching from the main clock to a PLL clock occurs, an oscillation stabilization wait time is required after the oscillation of the PLL clock starts. ■ Oscillation Stabilization Wait Time Specify an oscillation stabilization wait time appropriate for the oscillator used because the oscillation stabilizes in different lengths of time depending on the oscillator type. Specify an appropriate oscillation stabilization wait time in the oscillation stabilization wait time selection bits (WS1 and WS0) of the clock selection register (CKSCR). When switching from the main clock to a PLL clock occurs, the CPU operates on the main clock during an oscillation stabilization wait time and starts to operate on a PLL clock. The timebase timer counts the specified oscillation stabilization wait time. Figure 4.5-1 Operation When Oscillation Starts Oscillator-activated oscillation time Oscillation stabilization wait time Normal operation start or change to PLL clock X1 Start of oscillation Stable oscillation 79 CHAPTER 4 CLOCKS 4.6 Connection of an Oscillator or an External Clock to the Microcontroller The MB90M405 series contains a system clock generation circuit. An oscillator can be connected to the X0 and X1 pins. Alternatively, pulses from an external clock may be input. ■ Connection of an Oscillator or an External Clock to the Microcontroller ❍ Example of connecting a crystal or ceramic oscillator to the microcontroller Connect a crystal or ceramic oscillator as shown in the example in Figure 4.6-1 "Example of Connecting a Crystal or Ceramic Oscillator to the Microcontroller". Figure 4.6-1 Example of Connecting a Crystal or Ceramic Oscillator to the Microcontroller C1 X0 X'tal MB90M405 Series X1 C2 ❍ Example of connecting an external clock to the microcontroller As shown in Figure 4.6-2 "Example of Connecting an External Clock to the Microcontroller", connect an external clock to pin X0. Pin X1 must be open. Figure 4.6-2 Example of Connecting an External Clock to the Microcontroller X0 MB90M405 Series Open 80 X1 CHAPTER 5 LOW POWER CONSUMPTION MODE This chapter describes the low power consumption mode of MB90M405 series. 5.1 "Low Power Consumption Mode" 5.2 "Block Diagram of the Low Power Consumption Control Circuit" 5.3 "Low Power Consumption Mode Control Register (LPMCR)" 5.4 "CPU Intermittent Operation Mode" 5.5 "Standby Mode" 5.6 "Status Change Diagram" 5.7 "Pin Status in Standby Mode and during Reset" 5.8 "Usage Notes on Low Power Consumption Mode" 81 CHAPTER 5 LOW POWER CONSUMPTION MODE 5.1 Low Power Consumption Mode The MB90M405 series has the following low power consumption modes, one of which can be selected depending on the operating clock setting and the clock operation control. • CPU intermittent operation mode (PLL clock intermittent operation mode and main clock intermittent operation mode) • Standby mode (sleep mode, timebase timer mode) All modes other than PLL clock mode are low power consumption modes. ■ CPU Operating Modes and Current Consumption Figure 5.1-1 CPU Operating Modes and Current Consumption Current consumption Several tens of mA CPU operating mode PLL clock mode Multiplied-by-four clock Multiplied-by-three clock Multiplied-by-two clock Multiplied-by-1 clock PLL clock intermittent operation mode Multiplied-by-four clock Multiplied-by-three clock Multiplied-by-two clock Multiplied-by-1 clock Main clock mode (1/2 clock mode) Main clock intermittent operation mode Several mA Standby mode Sleep mode Timebase timer mode Stop mode Several µA Low power consumption mode Note: This figure is only an indication of the degree of power consumption for each mode. Actual current consumption values may not agree with those in the figure. 82 5.1 Low Power Consumption Mode ■ Clock Mode ❍ PLL clock mode The CPU and peripheral functions (resources) operate on a PLL clock. ❍ Main clock mode The CPU and peripheral functions (resources) operate on the main clock. In the main clock mode, the PLL multiplier circuit is disabled. See Section 4.4 "Clock Mode", for details about clock mode. ■ CPU Intermittent Operation Mode The CPU operates intermittently while the machine clock is supplied to the peripheral functions (resources). ■ Standby Mode ❍ PLL sleep mode The CPU operating clock is stopped. Other components continue to operate on a PLL clock. ❍ Main sleep mode The CPU operating clock is stopped. Other components continue to operate on the main clock. ❍ Timebase timer mode All the components but the oscillation clock and the timebase timer are stopped. ❍ Stop mode The oscillation clock is stopped. All the functions are stopped. Note: In stop mode, data can be retained at the minimum power consumption because the oscillation clock has stopped. 83 CHAPTER 5 LOW POWER CONSUMPTION MODE 5.2 Block Diagram of the Low Power Consumption Control Circuit The low power consumption control circuit consists of the following circuits and register: • CPU intermittent operation selector • Standby clock control circuit • CPU clock control circuit • Peripheral clock control circuit • Pin high-impedance control circuit • Internal reset generation circuit • Low power consumption mode control register (LPMCR) ■ Block Diagram of the Low Power Consumption Control Circuit Figure 5.2-1 Block Diagram of the Low Power Consumption Control Circuit Low power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 RESV Pin high impedance control circuit RST Pin high impedance control Internal reset generation circuit Pin Internal reset I/O pin reset Select intermittent cycles CPU intermittent operation selector CPU clock control circuit 2 Stop and sleep signals Standby control circuit Clear interrupt CPU clock Stop signal Machine clock Clock generation block Clear oscillation stabilization wait Peripheral clock control circuit Peripheral clock Oscillation stabilization wait interval selector Clock selector 2 2 PLL multiplier circuit X0 Pin X1 Pin RESV MCM WS1 WS0 RESV MCS CS1 CS0 Clock selection register (CKSCR) System clock generation circuit HCLK Divideby-2 MCLK 21 29 210 211 212 213 214 215 216 217 218 Timebase timer 84 5.2 Block Diagram of the Low Power Consumption Control Circuit ❍ CPU intermittent operation selector This selector selects the number of clock pulses during which the CPU is halted in CPU intermittent operation mode. ❍ Standby control circuit This circuit controls the CPU clock control circuit, the peripheral clock control circuit, and the pin high-impedance control circuit to switch to, or release low power consumption mode. ❍ CPU clock control circuit This circuit control the clocks supplied to the CPU. ❍ Peripheral clock control circuit This circuit control the clocks supplied to the peripheral functions (resources). ❍ Pin high-impedance control circuit A setting of this circuit to timebase timer mode or stop mode causes the I/O pins to enter a high impedance state. For those I/O pins configured to accept the connection of a pull-up resistor, this circuit disconnects the pull-up resistor in stop mode. ❍ Internal reset generation circuit If the RST bit of the low power consumption mode control register (LPMCR:RST) is set to "0" by software, this circuit generates a three-cycle reset signal to the internal circuit. ❍ Low power consumption mode control register (LPMCR) This register selects either switching to or release of low power consumption mode and the number of clock pulses during which the CPU is halted in CPU intermittent operation mode. 85 CHAPTER 5 LOW POWER CONSUMPTION MODE 5.3 Low Power Consumption Mode Control Register (LPMCR) The low power consumption mode control register (LPMCR) selects the switching to, or release of low power consumption mode and the number of clock pulses during which the CPU is halted in CPU intermittent operation mode. ■ Low Power Consumption Mode Control Register (LPMCR) Figure 5.3-1 Configuration of the Low Power Consumption Mode Control Register (LPMCR) Bit 7 6 5 4 3 2 1 0 Initial value STP SLP SPL RST TMD CG1 CG0 RESV W W R/W W 00011000B R/W R/W R/W R/W Reserved bit RESV 1 must always be written to these bits. CG1 CG0 CPU halt clock pulses set bits 0 0 0 cycle 0 1 8 cycle 1 0 16 cycle 1 1 32 cycle Timebase timer mode bit TMD 0 Switching to timebase timer mode 1 No effect on operation RST 0 Generates an internal reset signal of 3 machine cycles. 1 No effect on operation SPL Retained 1 High-impedance 86 Sleep bit 0 No effect on operation 1 Switching to sleep mode STP : Read/write : Write-only : Initial value Pin state setting bit (Valid in timebase timer mode and stop mode) 0 SLP R/W W Internal reset signal generation bit Stop bit 0 No effect on operation 1 Switching to stop mode 5.3 Low Power Consumption Mode Control Register (LPMCR) Table 5.3-1 Function Description of Each Bit of the Low Power Consumption Mode Control Register (LPMCR) Bit name Function bit 7 STP: Stop bit • • • • • This bit selects the stop mode. When this bit is set to "1", the microcontroller enters stop mode. When this bit is set to "0", there is no effect on operation. An external reset or the output of a hardware interrupt resets this bit to "0". The read value of this bit is "0". bit 6 SLP: Sleep bit • • • • • This bit selects sleep mode. When this bit is set to "1", the microcontroller enters sleep mode. When this bit is set to "0", there is no effect on operation. An external reset or the output of a hardware interrupt resets this bit to "0". The read value of this bit is "0". bit 5 SPL: Pin state setting bit valid in timebase timer mode or stop mode) • • • • This bit selects a pin state in timebase timer mode or stop mode. When this bit is set to "0", an I/O pin has a retained level. When this bit is set to "1", an I/O pin has high impedance. An external reset resets this bit to "0". bit 4 RST: Internal reset signal generation bit • • • • This bit selects an internal reset. When this bit is set to "0", an internal reset signal of three machine cycles is generated. When this bit is set to "1", there is no effect on operation. The read value of this bit is "1". bit 3 TMD: Timebase timer mode bit • • • • • This bit selects the switching to timebase timer mode. When this bit is set to "0", the microcontroller enters timebase timer mode. When this bit is set to "1", there is no effect on operation. An external reset or a hardware interrupt return sets this bit to "1". The read value of this bit is "1". bit 2 bit 1 CG1, CG0: CPU halt clock pulses selection bits • • • These bits set the number of CPU halt clock pulses in CPU intermittent operation mode. The clock supplied to the CPU is stopped for the specified number of clock cycles every time after an instruction is executed. These bits select one of the four clock pulses. A reset initializes these bits to "00B". • This bit must be set to "0". bit 0 RESV: Reserved bit • ■ Access to the Low Power Consumption Mode Control Register Use one of the instructions listed in Table 5.3-2 "Instructions to Be Used for Switching to Low Power Consumption Mode" to set low power consumption mode control register. The operation is not assured if any instruction other than that listed in Table 5.3-2 "Instructions to Be Used for Switching to Low Power Consumption Mode" is used to enter low power consumption mode. Any instruction may be used provided it is not an instruction that controls switching to low power consumption mode via the low power consumption mode control register. When using word access to set the low power consumption mode control register, use an evennumbered address. A malfunction may occur if an odd-numbered address is used to enter low power consumption mode. 87 CHAPTER 5 LOW POWER CONSUMPTION MODE Table 5.3-2 Instructions to Be Used for Switching to Low Power Consumption Mode MOV io, #imm8 MOV dir, #imm8 MOV eam, #imm8 MOV eam, Ri MOV io, A MOV dir, A MOV addr, A MOV eam, A MOV @RLi+disp8, A MOVP addr24, A MOVW io, #imm16 MOVW dir, #imm16 MOVW eam, #imm16 MOVW eam, RWi MOVW io, A MOVW dir, A MOVW addr16, MOVW eam, A MOVW @RLi+disp8, A MOVPW addr24, A ■ Priority of STP, SLP and TMD bits If stop mode (LPMCR: STP), sleep mode (LPMCR: SLP), and timebase timer mode (LPMCR: TMD) are simultaneously specified, the microcontroller enters the following order of priority: stop mode, timebase timer mode, or sleep mode 88 5.4 CPU Intermittent Operation Mode 5.4 CPU Intermittent Operation Mode In CPU intermittent operation mode, the CPU operates intermittently while the peripheral functions (resources) operate on the machine clock. ■ CPU Intermittent Operation Mode In CPU intermittent operation mode, the machine clock to be supplied to the CPU is halted for a certain period every time after an instruction is executed, so that the activation of an internal bus cycle is delayed. Reducing the CPU speed while supplying a fast peripheral clock to the peripheral function circuits allows processing with low power consumption. • Use the CG1 and CG0 bits of the low power consumption mode control register (LPMCR) to specify the number of cycles during which the clock supplied to the CPU is halted. • For external bus operation, use the same clock as that for the peripheral functions. • You can calculate the instruction execution time required when CPU intermittent operation mode is used as follows: Multiply the instruction execution count required to access registers, built-in memory, built-in peripheral functions (resources), and external buses by the halt cycle count, and add this correction value to the regular execution time. Figure 5.4-1 Clock Pulses during CPU Intermittent Operation Peripheral clock CPU clock Halt cycle count One instruction execution cycle Internal bus activation 89 CHAPTER 5 LOW POWER CONSUMPTION MODE 5.5 Standby Mode Standby mode includes the sleep mode (PLL sleep mode and main sleep mode), timebase timer mode, and stop mode. ■ Operating Status during Standby Mode Table 5.5-1 Operation Statuses in Standby Mode Standby mode PLL sleep Sleep mode mode Main sleep mode Timebase Time- timer mode base (SPL = 0) timer Timebase mode timer mode Condition for switch Oscillation MCS = 0 SLP = 1 Active Stop mode In-active Active Release event Active Active TMD = 0 Hold Inactive TMD = 0 Hi-z In-active In-active STP = 1 Hold Inactive Inactive STP = 1 SPL: Pin state setting bit of low power consumption mode control register (LPMCR) SLP: Sleep bit of low power consumption mode control register (LPMCR) STP: Timebase timer or stop bit of low power consumption mode control register (LPMCR) TMD: Timebase timer mode bit of low power consumption mode control register (LPMCR) MCS: Machine clock selection bit of clock set register (CKSCR) Hi-z: High-impedance 90 Pin Active In-active Stop mode (SPL = 1) CPU MCS = 1 SLP = 1 (SPL = 1) Stop mode (SPL = 0) Clock Timebase timer Peripheral Watchdog timer Hi-z External reset or hardware interrupt 5.5 Standby Mode 5.5.1 Sleep Mode In sleep mode, the CPU operating clock is halted while components other than the CPU continue to operate. When switching to sleep mode is specified, the microcontroller enters PLL sleep mode if PLL clock mode has been specified or the main sleep mode if the main clock mode has been specified. ■ Switching to Sleep Mode Set the sleep mode bit (SLP) of the low power consumption mode control register (LPMCR) to "1", the timebase timer mode bit (TMD) to "1", and the stop mode bit (STP) to "0" to enter sleep mode. When switching to sleep mode is specified, the microcontroller enters PLL sleep mode if the machine clock setting bit (MCS) of the clock selection register (CKSCR) is set to "0". Alternatively, the microcontroller enters main sleep mode if the MCS is set to "1". Note: If you make the stop mode bit (STP), sleep mode bit (SLP), and timebase timer mode bit (TMD) effective at the same time, the stop mode bit (STP) has precedence. If you make the sleep mode bit (SLP) and timebase timer mode bit (TMD) effective at the same time, the timebase timer mode bit (TMD) has precedence. The order of priority is as follows: Stop mode > Timebase timer mode > Sleep mode ❍ Data retention function In sleep mode, the contents of both the dedicated registers and internal RAM are retained. For more information on dedicated registers, see Section 2.7 "Dedicated Registers". ❍ Operation during output of an interrupt request While an interrupt request is output, the microcontroller does not enter sleep mode but executes the next instruction even if the sleep mode bit (SLP) of the low power consumption mode control register (LPMCR) is set to "1". ❍ Pin state In sleep mode, the pin state existing just before sleep mode is entered is retained. ■ Release of Sleep Mode An external reset or the output of a hardware interrupt releases sleep mode. ❍ Release by a reset For more information, see Section 3.4 "Reset Operation". ❍ Release by a hardware interrupt An interrupt request with an interrupt level higher than 7 (Interrupt control register ICR: IL2, IL1, IL0 = "000B" to "110B") is required to cause a hardware interrupt to release sleep mode. 91 CHAPTER 5 LOW POWER CONSUMPTION MODE Figure 5.5-1 Release of Sleep Mode upon Occurrence of a Hardware Interrupt A peripheral function issues an interrupt to set the enable flag. Has INT occurred (for IL < 7)? YES I=0 NO YES Sleep mode continues Sleep mode continued Next instruction executed Sleep mode released NO ILM < IL YES Next instruction executed NO Interrupt executed Note: To handle an interrupt, the microcontroller normally starts with interrupt processing after executing the instruction following the instruction that specifies sleep mode. However, the microcontroller may start interrupt processing before executing the next instruction if a sleep mode request and an external bus hold request are accepted at the same time. 92 5.5 Standby Mode 5.5.2 Timebase Timer Mode In timebase timer mode, all of the operations other than the source oscillation and the timebase timer are stopped. ■ Switching to Timebase Timer Mode If the timebase timer mode bit (TMD) of the low power consumption mode control register (LPMCR) is set to "0", the microcontroller enters timebase timer mode. ❍ Data retention function In timebase timer mode, the contents of both the dedicated registers and internal RAM are retained. For more information on dedicated registers, see Section 2.7 "Dedicated Registers". ❍ Operation during output of an interrupt request While an interrupt request is output, the microcontroller does not enter timebase timer mode even if the timebase timer mode bit (TMD) of the low power consumption mode control register (LPMCR) is set to "0". ❍ Status of pins The I/O pins in timebase timer mode can be set to retain a previous level or have high impedance in the pin status setting bit (SPL) of the low power consumption mode control register (LPMCR). ■ Release of Timebase Timer Mode Timebase timer mode is released by an external reset, timebase timer interrupt, or hardware interrupt resulting from input of an external interrupt. ❍ Release by a reset For more information, see Section 3.4 "Reset Operation". ❍ Release by a hardware interrupt An interrupt request with an interrupt level higher than 7 (IL2, IL1 and IL0 of the interrupt control register (ICR) are 000B to 110B) is required to release timebase timer mode with a hardware interrupt. Note: When interrupt processing is executed, the microcontroller normally enters interrupt processing after executing the instruction after the instruction that specifies timebase timer mode. 93 CHAPTER 5 LOW POWER CONSUMPTION MODE 5.5.3 Stop Mode In stop mode, the source oscillation is stopped. Since all the functions are stopped, data can be retained while minimum power is consumed. ■ Switching to Stop Mode If the stop mode bit (STP) of the low power consumption mode control register (LPMCR) is set to "1", the microcontroller enters stop mode. ❍ Data retention function In stop mode, the contents of both the dedicated registers and RAM are retained. For more information on dedicated registers, see Section 2.7 "Dedicated Registers". ❍ Operation during acceptance or execution of an interrupt request While an interrupt request is being accepted or executed, the microcontroller does not enter stop mode even though the stop mode bit (STP) of the low power consumption mode control register (LPMCR) is set to "1". ❍ Status of pins The I/O pins in stop mode can be set to retain a previous level or have high impedance in the pin status setting bit (SPL) of the low power consumption mode control register (LPMCR). ■ Release of Stop Mode Stop mode is released by an external reset or hardware interrupt resulting from input of an external interrupt. ❍ Release by a reset For more information, see Section 3.4 "Reset Operation". ❍ Release by a hardware interrupt An interrupt request with an interrupt level higher than 7 (IL2, IL1 and IL0 of the interrupt control register (ICR) are 000B to 110B) is required to release stop mode with an external interrupt. Note: To handle an interrupt, the microcontroller enters interrupt processing in ordinary cases after executing the instruction following the instruction that specifies stop mode. However, the microcontroller may enter interrupt processing before executing the next instruction if a request to enter stop mode and an external bus hold request are received at the same time. 94 5.5 Standby Mode Figure 5.5-2 Release of Stop Mode (External Reset) RST pin Stop mode Oscillation clock Main clock PLL clock Oscillation Oscillation stabilization wait Stopped CPU clock CPU operation Oscillation Main clock Stopped Reset sequence Instruction executed Release of reset Release of stop mode 95 CHAPTER 5 LOW POWER CONSUMPTION MODE 5.6 Status Change Diagram Figure 5.6-1 "Status Change Diagram" shows the CPU operation modes of the MB90M405 series and a state transition diagram. ■ Status Change Diagram Figure 5.6-1 Status Change Diagram External reset, Watchdog timer reset, Software reset Power-on Reset Oscillation stabilization wait MCS="1" Main mode PLL mode MCS="0" SLP="1" Interrupt Main sleep TMD="0" Interrupt Timebase timer mode STP="1" Interrupt PLL mode TMD="0" Interrupt Timebase timer mode STP="1" Main sleep External interrupt Oscillation stabilization wait Main oscillation wait 96 SLP="1" PLL mode External interrupt Oscillation stabilization wait PLL oscillation wait 5.6 Status Change Diagram ■ Operating States in Low Power Consumption Mode Table 5.6-1 Operating States in Low Power Consumption Mode Low power consumption mode Entry condition Main sleep Oscillation Machine clock CPU Peripheral Pin Release method MCS="1" SLP="1" Running Running Stopped Running Running Reset interrupt PLL sleep MCS="0" SLP="1" Running Running Stopped Running Running Reset interrupt Timebase timer (SPL="0") TMD="0" Running Stopped Stopped Stopped Retained Reset interrupt Timebase timer (SPL="1") TMD="0" Running Stopped Stopped Stopped Hi-z Reset interrupt Stop (SPL="0") MCS="1" STP="1" Stopped Stopped Stopped Stopped Retained Reset interrupt Stop (SPL="1") MCS="1" STP="1" Stopped Stopped Stopped Stopped Hi-z Reset interrupt 97 CHAPTER 5 LOW POWER CONSUMPTION MODE 5.7 Pin Status in Standby Mode and during Reset Table 5.7-1 "State of Pins in Single-Chip Mode" shows the status of pins in standby mode and during a reset. ■ Software Pull-Up Resistor For I/O pins configured in software to accept the connection of a pull-up resistor, set the port to an output setting that disconnects the pull-up resistor. ■ Status of Pins in Single-Chip Mode Table 5.7-1 State of Pins in Single-Chip Mode Standby mode Pin name Stop mode Reset Sleep mode P82 to P87 P90 to P91 PA0 to PA7 PB0 to PB5 P80, P81 PB6, PB7 The preceding status is retained. (*2) SPL=0 SPL=1 The preceding status is retained. (*2) Input shut off (*3) /output Hi-z Output Hi-z (*4) Input enabled (*1) *1: "Input enabled" means that the input function is enabled. However, the input function is enabled only if an external interrupt is enabled. These pins, when used as output ports, conform to the setting of the pin status setting bit (SPL) of the low power consumption mode control register (LPMCR). *2: "The preceding status is retained" means that the output status of the pin immediately before switching to standby mode is retained (*5). However, note that the input is disabled (*6) if the pin was in the input status. *3: "Input shut off" means that the input to the pin is inhibited. *4: "Output Hi-Z" means that the pin-driving transistor is disabled and that the pin is made to have high impedance. *5: "the output status is retained as is" means that the output value of a peripheral function (resource) or a port is retained. *6: "the input is disabled" means that a value input to the pin cannot be accepted internally because an internal circuit is not running. 98 5.8 Usage Notes on Low Power Consumption Mode 5.8 Usage Notes on Low Power Consumption Mode Note the following items when using low power consumption mode: • Switching to standby mode and interrupts • Release of standby mode by an interrupt • Release of stop mode by an external interrupt • Oscillation stabilization wait time ■ Switching to Standby Mode and Interrupts While an interrupt request is output, the microcontroller does not enter standby mode even if the stop mode bit (STP) of the low power consumption mode control register (LPMCR) is set to "1", the sleep mode bit (SLP) is set to "1", or the timebase timer mode bit (TMD) is set to "0". ■ Release of Standby Mode by an Interrupt Standby mode is released if an interrupt request with an interrupt level higher than 7 (Interrupt control register ICR: IL2, IL1, IL0 = "000B" to "110B") is output in sleep mode, timebase timer mode, or stop mode. If the interrupt level setting bit (ICR: IL2, IL1, IL0) corresponding to an interrupt request has a priority higher than the interrupt level mask register (ILM) and the interrupt enable flag of the condition code register is enabled (CCR:I = 1), the interrupt is accepted and the interrupt processing routine is executed. Unless the interrupt is accepted, the processing starts again from the next instruction to the one that set standby mode. Note: Interrupt disable setting is required before the setting of standby mode unless an interrupt processing routine is executed immediately after standby mode is released. ■ Release of Stop Mode by an External interrupt To release stop mode by an external interrupt, set the DTP/interrupt enable register (ENIR) and the request level setting register (ELVR) before the microcontroller enters stop mode. Select one of the "H" level, "L" level, rising edge, and falling edge as an input cause. 99 CHAPTER 5 LOW POWER CONSUMPTION MODE ■ Oscillation Stabilization Wait Time ❍ Source clock oscillation stabilization wait time An oscillation stabilization wait time is required after stop mode is released because the source oscillation has been halted in stop mode. The oscillation stabilization wait time can be set in the oscillation stabilization wait time setting bits (WS1, WS0) of the clock selection register (CKSCR). On a return due to a reset, the registers are set to the initial value. The clock cycle is therefore fixed to 217/HCLK. ❍ PLL clock oscillation stabilization wait time A PLL clock oscillation stabilization wait time is required after the operating clock is changed from the main clock to the PLL clock because the PLL clock is halted while the CPU operates on the main clock. While waiting for PLL clock oscillation stabilization, the CPU operates on the main clock. The PLL clock oscillation stabilization wait time is fixed at 214/HCLK (HCLK: clock oscillation frequency). 100 CHAPTER 6 INTERRUPTS This chapter explains the interrupts and extended intelligent I/O service (EI2OS) in the MB90M405 series. 6.1 "Interrupts" 6.2 "Interrupt Causes and Interrupt Vectors" 6.3 "Interrupt Control Registers and Peripheral Functions" 6.4 "Hardware Interrupts" 6.5 "Software Interrupts" 6.6 "Interrupt of Extended Intelligent I/O Service (EI2OS)" 6.7 "Exception Processing Interrupt" 6.8 "Stack Operations for Interrupt Processing" 6.9 "Sample Programs for Interrupt Processing" 101 CHAPTER 6 INTERRUPTS 6.1 Interrupts The MB90M405 series has the following interrupt functions and exception processing function: • Hardware interrupts • Software interrupts • Interrupts from extended intelligent I/O service (EI2OS) • Exception processing ■ Interrupt Types and Functions ❍ Hardware interrupt A hardware interrupt transfers control to an interrupt processing program in response to an interrupt request from a peripheral function (resource). For more information, see Section 6.4 "Hardware Interrupts". ❍ Software interrupt A software interrupt transfers control to an interrupt processing program if a software interrupt instruction (INT instruction) is executed on a program. For more information, see Section 6.5 "Software Interrupts". ❍ Interrupt from extended intelligent I/O service (EI2OS) The extended intelligent I/O service (EI2OS) can transfer data between a register contained in a peripheral function (resource) and internal memory if settings are made in the interrupt control registers (ICR00 to ICR15) and the extended intelligent I/O service descriptor (ISD). When the data transfers have been terminated, the interrupt processing program is executed. For more information, see Section 6.6 "Interrupt of Extended Intelligent I/O Service (EI2OS)". ❍ Exception processing Exception processing is performed if an undefined instruction code is executed. If exception processing is performed, the register value currently processed is saved to the system stack and the processing branches to the exception processing routine. For more information, see Section 6.7 "Exception Processing Interrupt". 102 6.1 Interrupts ■ Interrupt Operation Figure 6.1-1 Overall Flow of Interrupt Operation START Main program Is there a valid hardware interrupt request? String type (*1) instruction being NO executed YES Interrupt activation/return processing YES EI2OS? Fetch the next instruction and decode EI2OS NO YES INT instruction? NO Software interrupt/ exception processing Save the dedicated register on the system stack EI2OS processing Hardware Interrupt Disable acceptance of hardware interrupts (I = "0") YES Save the dedicated register on the system stack Specified count terminated? Alternatively, is there an end request from the peripheral function? NO Update the CPU interrupt processing level (ILM) YES RETI instruction? NO Execute ordinary instruction NO Return processing Return the dedicated register from the system stack, call the interrupt routine, and return to the previous routine Read the interrupt vector, update PC and PCB, and branch to the interrupt routine Repetition of string type (*1) instruction completed? YES Move the pointer to the next instruction by PC update *1 When a string type instruction is being executed, the interrupt is evaluated in each step. 103 CHAPTER 6 INTERRUPTS 6.2 Interrupt Causes and Interrupt Vectors The MB90M405 series have functions for handling 256 types of interrupt cause. The 256 interrupt vector tables are allocated to the memory at the highest addresses. Software interrupts can use 256 interrupt instructions (INT0 to INT255). Note that INT8 is shared with a reset vector interrupt and that INT10 is shared with exception processing. INT11 to INT42 are shared with an interrupt from a peripheral function (resource). ■ Interrupt Vectors Interrupt vector tables referenced during interrupt processing are allocated to the highest addresses in the memory area (FFFC00H to FFFFFEH). Interrupt vectors share the same area with EI2OS, exception processing, hardware, and software interrupts. Table 6.2-1 "Interrupt Vectors" shows the assignment of software interrupt instructions, interrupt numbers, and interrupt vectors. Table 6.2-1 Interrupt Vectors Software interrupt instruction Vector address L Vector address M Vector address H Mode data Interrupt No. Hardware interrupt INT0 FFFFFCH FFFFFDH FFFFFEH Not used #0 None : : : : : : : INT7 FFFFE0H FFFFE1H FFFFE2H Not used #7 None INT8 FFFFDCH FFFFDDH FFFFDEH FFFFDFH #8 (RESET Vector) INT9 FFFFD8H FFFFD9H FFFFDAH Not used #9 None INT10 FFFFD4H FFFFD5H FFFFD6H Not used #10 <Exception processing> INT11 FFFFD0H FFFFD1H FFFFD2H Not used #11 Hardware interrupt #0 INT12 FFFFCCH FFFFCDH FFFFCEH Not used #12 Hardware interrupt #1 INT13 FFFFC8H FFFFC9H FFFFCAH Not used #13 Hardware interrupt #2 INT14 FFFFC4H FFFFC5H FFFFC6H Not used #14 Hardware interrupt #3 : : : : : : : INT254 FFFC04H FFFC05H FFFC06H Not used #254 None INT255 FFFC00H FFFC01H FFFC02H Not used #255 None Note: Interrupt vectors not defined during software design should be set at the exception processing address. 104 6.2 Interrupt Causes and Interrupt Vectors ■ Interrupt Causes and Interrupt Vectors/Interrupt Control Registers Table 6.2-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers Interrupt cause EI2OS support Interrupt vector Interrupt control register Priority Number *1 Address ICR Address Reset X #08 08H FFFFDCH - - INT9 instruction X #09 09H FFFFD8H - - Exception processing X #10 0AH FFFFD4H - - DTP/external interrupt channel 0 O #11 0BH FFFFD0H ICR00 0000B0H DTP/external interrupt channel 1 O #13 0DH FFFFC8H ICR01 0000B1H #15 0FH FFFFC0H #16 10H FFFFBCH ICR02 0000B2H Serial I/O channel 3 #17 11H FFFFB8H #18 12H FFFFB4H ICR03 16-bit free-running timer 0000B3H #20 - FFFFACH ICR04 0000B4H 16-bit reload timer channel 2 #21 15H FFFFA8H ICR05 0000B5H 16-bit reload timer channel 0 #23 17H FFFFA0H #24 18H FFFF9CH ICR06 16-bit reload timer channel 1 0000B6H Input capture channel 0 #25 19H FFFF98H #26 1AH FFFF94H ICR07 Input capture channel 1 0000B7H Serial I/O channel 2 DTP/external interrupt channels 2/3 Reserved O - Reserved - #27 - FFFF90H ICR08 0000B8H Output compare match X #29 1DH FFFF88H ICR09 0000B9H Reserved - #31 - FFFF80H ICR10 0000BAH Timebase timer X #33 21H FFFF78H - #34 - FFFF74H ICR11 Reserved 0000BBH UART0 receive end #35 23H FFFF70H #36 24H FFFF6CH ICR12 UART0 send end 0000BCH #37 25H FFFF68H I2C interface #38 26H FFFF64H ICR13 0000BDH UART1 receive end #39 27H FFFF60H #40 28H FFFF5CH ICR14 UART1 send end 0000BEH ICR15 0000BFH End of A/D conversion O Flash memory status X #41 29H FFFF58H Delayed interrupt generator module X #42 2AH FFFF54H High Low O: Can be used. X: Cannot be used. : Usable if used with the EI2OS stop function. : Usable when an interrupt cause that shares the ICR is not used. *1: If multiple interrupts of the same level are output simultaneously, an interrupt cause with a smaller interrupt vector number takes precedence. 105 CHAPTER 6 INTERRUPTS 6.3 Interrupt Control Registers and Peripheral Functions The interrupt control registers ICR00 to ICR15 correspond to all peripheral functions that have the interrupt function. These registers control interrupts and the extended intelligent I/O service (EI2OS). ■ Interrupt Control Registers Table 6.3-1 Interrupt Control Registers Address Register Abbreviation Corresponding peripheral function (Resource) 0000B0H Interrupt control register 00 ICR00 DTP/external interrupt channel 0 0000B1H Interrupt control register 01 ICR01 DTP/external interrupt channel 1 0000B2H Interrupt control register 02 ICR02 Serial I/O channel 2 DTP/external interrupt channels 2/3 0000B3H Interrupt control register 03 ICR03 Serial I/O channel 3 16-bit free-running timer 0000B4H Interrupt control register 04 ICR04 Reserved 0000B5H Interrupt control register 05 ICR05 16-bit reload timer channel 2 0000B6H Interrupt control register 06 ICR06 16-bit reload timer channels 0/1 0000B7H Interrupt control register 07 ICR07 Input capture channels 0/1 0000B8H Interrupt control register 08 ICR08 Reserved 0000B9H Interrupt control register 09 ICR09 Output compare 0000BAH Interrupt control register 10 ICR10 Reserved 0000BBH Interrupt control register 11 ICR11 Timebase timer 0000BCH Interrupt control register 12 ICR12 UART0 receive end UART0 send end 0000BDH Interrupt control register 13 ICR13 A/D converter I2C bus interface 0000BEH Interrupt control register 14 ICR14 UART1 receive end UART1 send end 0000BFH Interrupt control register 15 ICR15 Flash memory status Delayed interrupt generator module The following four settings can be made in an interrupt control register (ICR). 106 • Set the interrupt level of the corresponding peripheral function (resource). • Set an interrupt of the peripheral function (resource) either as an interrupt or as the extended intelligent I/O service. • Set the descriptor address of the extended intelligent I/O service (EI2OS). 6.3 Interrupt Control Registers and Peripheral Functions • Display the status of the extended intelligent I/O service (EI2OS) Interrupt control registers (ICRs) have different functions during the writing and reading of data. Note: When interrupt control registers (ICRs) are set, a read-modify-write instruction of SETB and CLRB cannot be used to access it. 107 CHAPTER 6 INTERRUPTS 6.3.1 Interrupt Control Registers (ICR00 to ICR15) Interrupt control registers can determine the interrupt processing or the extended intelligent I/O service processing when an interrupt request is output. Interrupt control registers (ICRs) have different bit functions during the writing and reading of data. ■ Interrupt Control Registers (ICR00 to ICR15) Figure 6.3-1 Interrupt Control Registers (ICR00 to ICR15) during Writing Writing Bit 7 6 5 4 3 2 1 0 Initial value IL2 IL1 IL0 00000111B ICR00 to ICR15 ICS3 ICS2 ICS1 ICS0 ISE W W W W R/W R/W R/W R/W IL2 IL1 IL0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Interrupt level setting bit Interrupt level 0 (highest) Interrupt level 7 (no interrupt) EI2OS enable bit ISE 0 Activates the interrupt sequence when an interrupt occurs 1 Activates EI2OS when an interrupt occurs ICS3 ICS2 ICS1 ICS0 R/W : Read/write W : Write only : Initial value 108 EI2OS channel setting bit Channel Descriptor address 0 0 0 0 0 000100 H 0 0 0 1 1 000108 H 0 0 1 0 2 000110 H 0 0 1 1 3 000118 H 0 1 0 0 4 000120 H 0 1 0 1 5 000128 H 0 1 1 0 6 000130 H 0 1 1 1 7 000138 H 1 0 0 0 8 000140 H 1 0 0 1 9 000148 H 1 0 1 0 10 000150 H 1 0 1 1 11 000158 H 1 1 0 0 12 000160 H 1 1 0 1 13 000168 H 1 1 1 0 14 000170 H 1 1 1 1 15 000178 H 6.3 Interrupt Control Registers and Peripheral Functions Figure 6.3-2 Interrupt Control Registers (ICR00 to ICR15) during Reading Reading Bit 7 6 ICR00 to ICR15 - - 5 4 3 2 1 0 Initial value S1 S0 ISE IL2 IL1 IL0 XX000111B R R R/W R/W R/W R/W IL2 IL1 IL0 Interrupt level setting bit 0 0 0 Interrupt level 0 (highest) 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 EI2OS enable bit ISE 0 R/W R X Interrupt level 7 (no interrupt) 1 Activates the interrupt sequence when an interrupt occurs Activates EI2OS when an interrupt occurs S1 S0 EI2OS status 0 0 EI2OS operation in progress or EI2OS not activated 0 1 Stopped status due to count termination 1 0 Reserved 1 1 Stopped status due to a request from the peripheral function : Read/write : Read only : Undefined bit : Undefined : Initial value 109 CHAPTER 6 INTERRUPTS 6.3.2 Interrupt Control Register Functions The interrupt control registers (ICR00 to ICR15) can specify the following settings: • Interrupt level setting • Extended intelligent I/O service (EI2OS) enable setting • Extended intelligent I/O service (EI2OS) descriptor address setting • Extended intelligent I/O service (EI2OS) operation status display ■ Configuration of Interrupt Control Registers (ICR) Figure 6.3-3 Configuration of Interrupt Control Registers (ICR) Writing to interrupt control register (ICR) Bit 7 6 5 ICR00 to ICR15 4 - 1 0 Initial value IL2 IL1 IL0 00000111B 3 2 1 0 Initial value ISE IL2 IL1 IL0 XX000111B ICS3 ICS2 ICS1 ICS0 ISE Reading of interrupt control register (ICR) 7 6 5 4 Bit ICR00 to ICR15 2 3 S1 S0 : Undefined bit Reference: Set the EI2OS descriptor address setting bits (ICS3 to ICS0) to start the extended intelligent I/O service (EI2OS). Set the EI2OS enable bit (ISE) to "1" to activate it. Alternatively, set the ISE to "0" to refrain from activating it. If EI2OS is not activated, the ICS3 to ICS0 bits need not be set. 110 6.3 Interrupt Control Registers and Peripheral Functions ■ Interrupt Control Register Functions ❍ Interrupt level setting bits (IL2 to IL0) These bits can set the interrupt level of the corresponding peripheral function (resource). A reset initializes these bits to level 7 (no interrupts). (No interrupts can be generated at level 7.) Table 6.3-2 Correspondence between the Interrupt Level Setting Bits and Interrupt Levels IL2 IL1 IL0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Interrupt level 0 (highest priority) 6 (lowest priority) 7 (no interrupts) ❍ Extended intelligent I/O service (EI2OS) enable bit (ISE) When an interrupt request is output, EI2OS is started if the EI2OS enable bit (ISE) is set to "1". Alternatively, an interrupt sequence is started if the EI2OS enable bit (ISE) is set to "0". When EI2OS processing is completed, the ISE bit is reset to "0". If a peripheral function (resource) has no EI2OS function, set the ISE bit to "0" using software. A reset initializes the ISE bit to "0". ❍ Extended intelligent I/O service (EI2OS) channel setting bits (ICS3 to ICS1) The EI2OS descriptor address setting bits (ICS3 to ICS1) are valid when a descriptor is set. Set the EI2OS descriptor address in these bits. Set values in the EI2OS descriptor address setting bits to set the EI2OS descriptor address. A reset initializes the ICS3 to ICS0 bits to 0000B. 111 CHAPTER 6 INTERRUPTS Table 6.3-3 Correspondence between EI2OS Channel Setting Bits and Descriptor Addresses ICS3 ICS2 ICS1 ICS0 Selected channel Descriptor address 0 0 0 0 0 000100H 0 0 0 1 1 000108H 0 0 1 0 2 000110H 0 0 1 1 3 000118H 0 1 0 0 4 000120H 0 1 0 1 5 000128H 0 1 1 0 6 000130H 0 1 1 1 7 000138H 1 0 0 0 8 000140H 1 0 0 1 9 000148H 1 0 1 0 10 000150H 1 0 1 1 11 000158H 1 1 0 0 12 000160H 1 1 0 1 13 000168H 1 1 1 0 14 000170H 1 1 1 1 15 000178H ❍ Extended intelligent I/O service (EI2OS) status bits (S1 and S0) The EI2OS status bits (S1 and S0) are valid during reading. Read the S1 and S0 bits while EI2OS is activated to determine whether EI2OS is running or terminated. A reset initializes the S1 and S0 bits to "00B". Table 6.3-4 Relationship between EI2OS Status Bits and the EI2OS Status 112 S1 S0 0 0 EI2OS operation in progress or EI2OS not activated 0 1 Stopped status due to count termination 1 0 Reserved 1 1 Stopped status due to a request from the peripheral function (resource) EI2OS status 6.4 Hardware Interrupts 6.4 Hardware Interrupts A hardware interrupt operates as follows: an interrupt request that is output by a peripheral function (resource) temporarily interrupts a program being executed by the CPU and transfers control to a user-defined interrupt processing program. The extended intelligent I/O service (EI2OS) is also handled as a hardware interrupt. ■ Hardware Interrupts ❍ Hardware interrupt function The hardware interrupt function determines whether an interrupt can be accepted. To do so, it compares the interrupt level of an interrupt request that is output by a peripheral function (resource) with the interrupt level mask register (PS: ILM) while referring to the contents of the I flag (PS: I). If a hardware interrupt is accepted, the contents of the direct page register (DPR), accumulator (A), program counter (PC), processor status register (PS), and bank registers (ADB, DTB, and PCB) are saved to the system stack. An interrupt level stored in the ICR register is then stored in the interrupt level mask register (ILM). Finally, the processing branches to the interrupt vector and the interrupt processing program is executed. ❍ Multiple interrupts A hardware interrupt can be activated while the interrupt processing program is being executed. ❍ Extended intelligent I/O service (EI2OS) EI2OS is a data transfer function between memory and I/O registers. When the transfer of data to the extended intelligent I/O service descriptor is completed, a hardware interrupt is activated. EI2OS cannot be activated in duplicate. While EI2OS is being processed, no interrupt request or EI2OS request is accepted. When the processing of EI2OS is completed, interrupt request or EI2OS request is accepted. ❍ External interrupt An external interrupt is accepted as a hardware interrupt if a circuit that can output an interrupt request from an external terminal (DTP/external interrupt circuit) detects an interrupt request. ❍ Interrupt vector Interrupt vector tables referenced during interrupt processing are allocated to memory at FFFC00H to FFFFFFH. Reference: See Section 6.2 "Interrupt causes and Interrupt Vectors", for more information about the allocation of interrupt numbers and interrupt vectors. 113 CHAPTER 6 INTERRUPTS ■ Hardware Interrupt Structure The mechanisms shown in Table 6.4-1 "Mechanisms Used for Hardware Interrupts" are used for hardware interrupts. These mechanisms must be configured in a user program before hardware interrupts can be used. Table 6.4-1 Mechanisms Used for Hardware Interrupts Mechanism Function Peripheral function (resource) Interrupt enable bit, interrupt request bit Controls interrupt requests from a peripheral function (resource) Interrupt controller Interrupt control register (ICR) Sets the interrupt level and controls EI2OS Interrupt enable flag (I) Identifies the interrupt enable status Interrupt level mask register (ILM) Compares the request interrupt level and current interrupt level Microcode Executes the interrupt processing routine Interrupt vector table Stores the branch destination address for interrupt processing CPU FFFC00H to FFFFFFH in memory ■ Hardware Interrupt Disable Acceptance of a hardware interrupt request is disabled under the following conditions: ❍ Hardware interrupt acceptance disable during writing to the peripheral function (resource) control register No hardware interrupt request is accepted while data is written to the peripheral function (resource) control register. Figure 6.4-1 Hardware Interrupt Request While Writing to the Peripheral Function Control Register Area Instruction that writes to the peripheral function control register area ..... MOV A, #08 MOV io,A An interrupt request is generated here 114 MOV A,2000H Does not branch to the interrupt Interrupt processing Branches to the interrupt 6.4 Hardware Interrupts ❍ Hardware interrupt acceptance disable by interrupt suppression instructions The hardware interrupt suppression instructions listed in Table 6.4-2 "Hardware Interrupt Suppression Instruction" ignore interrupt requests without detecting whether a hardware interrupt request exists. If a hardware interrupt request is output while a hardware interrupt suppression instruction is being executed, the interrupt is accepted and processed after completion of the hardware interrupt suppression instruction and the subsequent execution of an instruction other than the hardware interrupt suppression instruction. Table 6.4-2 Hardware Interrupt Suppression Instruction Prefix code Instructions that do not accept interrupts and hold requests PCB DTB ADB SPB CMR NCC Interrupts/hold suppression instructions (instructions that delay the effect of the prefix code) MOV OR AND POPW ILM, #imm8 CCR, #imm8 CCR, #imm8 PS ❍ Hardware interrupt acceptance disable during execution of a software interrupt When a software interrupt is activated, the I flag is cleared to 0. In this state, other interrupt requests cannot be accepted. 115 CHAPTER 6 INTERRUPTS 6.4.1 Operation of Hardware Interrupts This section explains hardware interrupt operation from generation of a interrupt request to the completion of interrupt processing. ■ Hardware Interrupt Activation ❍ Peripheral function (resource) operation (generation of an interrupt request) A peripheral function (resource) that has a hardware interrupt request function has an "interrupt request flag bit" and an "interrupt enable flag" in the corresponding peripheral function (resource) control registers. The interrupt request flag bit indicates the presence of an interrupt request. The interrupt enable flag determines whether a CPU interrupt request is enabled or disabled. When an interrupt cause defined in a peripheral function is detected, an interrupt request is output to an interrupt controller as long as the interrupt request flag bit is set to "1" and the interrupt enable bit is set to enable an interrupt request to the CPU. ❍ Interrupt controller operation (interrupt request control) The interrupt controller compares the interrupt levels (ILs) to accept the request having the highest level. If multiple interrupts of the same level are output simultaneously, an interrupt request with the smallest number takes precedence (see Table 6.2-1 "Interrupt Vectors"). ❍ CPU operation (interrupt request acceptance and interrupt processing) The CPU compares the received interrupt level (ICR: IL2 to IL0) and the interrupt level mask register (ILM). If IL2 to IL0 are greater than ILM and interrupts are enabled (PS: CCR: I = "1"), the CPU terminates the instruction being executed and performs the interrupt processing. If the EI2OS enable bit (ISE) of the interrupt control register (ICR) is set to "0", the CPU performs the interrupt processing. If the ISE is set to "1", the CPU starts EI2OS and then performs the interrupt processing. Interrupt processing saves the contents of the dedicated registers (12 bytes including A, DPR, ADB, DTB, PCB, PC, and PS) on the system stack (the system stack space indicated by the SSB and SSP). The CPU then loads data into the interrupt vector program counters (PCB and PC), updates the ILM, and sets the stack flag (S) (sets CCR: S = 1 and activates the system stack). ■ Returning from a Hardware Interrupt If an interrupt processing program writes "0" to the interrupt request flag bit of a peripheral function (resource) that output an interrupt cause and the RETI instruction is executed, data saved on the system stack is restored to the dedicated registers and the program processing that was executed before branching due to an interrupt is resumed. 116 6.4 Hardware Interrupts ■ Hardware Interrupt Operation Figure 6.4-2 Hardware Interrupt Operation Internal bus F2MC-16LX CPU PS PS,PC (7) I ILM IR Microcode Comparator Check (6) (5) (4) (3) Other peripheral functions Peripheral function that generated the interrupt request Level comparator Enable FF AND Factor FF (8) Interrupt level IL (2) (1) Interrupt controller RAM IL PS I ILM IR : Interrupt level setting bit in the interrupt control register (ICR) : Processor status : Interrupt enable flag : Interrupt level mask register : Instruction register 1. An interrupt cause is output within the peripheral functions (resources). 2. If the interrupt enable bit in the peripheral functions (resources) is set to enable interrupts, interrupt requests are output from the peripheral functions (resources) to the interrupt controller. 3. The interrupt controller that receives interrupt requests from the peripheral functions (resources) checks the priorities of interrupt requests simultaneously received and transfers the interrupt level (IL) of an interrupt request with the highest priority to the CPU. 4. The CPU compares the interrupt level (IL) requested by the interrupt controller with the interrupt level mask register (ILM). 5. If the comparison indicates a higher priority than the current interrupt processing level, the CPU checks the contents of the I flag in the condition code register (CCR). 6. If, in the check, the I flag in the CCR is found to be set to Enabled (CCR: I = "1"), the CPU waits until the execution of an instruction being executed is terminated. When it is terminated, the CPU sets the requested level (IL2 to IL0) in the ILM. 7. The values in the dedicated registers are saved to the system stack. branches to the interrupt processing routine. The processing 8. If a program in the interrupt processing routine sets the interrupt request flag bit of a peripheral function (resource) to "0" and the RETI instruction is executed, data saved on the system stack is restored to the dedicated registers and the interrupt processing is terminated. 117 CHAPTER 6 INTERRUPTS 6.4.2 Processing for Interrupt Operation When a peripheral function (resource) outputs an interrupt request and the CPU accepts it, the interrupt processing is performed after the instruction currently being executed is terminated. If the EI2OS enable bit (ISE) of the interrupt control register (ICR) is set to "0", the CPU performs the interrupt processing. If the ISE is set to "1", the CPU activates the extended intelligent I/O service (EI2OS). If a software interrupt is output by the INT instruction, the instruction currently being executed is suspended, the interrupt processing routine is performed, and hardware interrupts are disabled. ■ Processing for Interrupt Operation Figure 6.4-3 Flow of Interrupt Processing START Main program I&IF&IE = "1" AND ILM > IL String type (*1) instruction in progress YES Interrupt activation/return processing NO YES ISE = "1" Fetch the next instruction and decode EI2OS NO INT instruction? YES NO EI2OS processing Software interrupt/exception processing Hardware instruction Save the dedicated registers to the system stack YES I="0" (Disable hardware interrupts) Save the dedicated registers to the system stack Specified count terminated? Alternatively, is there a termination request from the peripheral function? NO ILM IL (Transfer the interrupt level of the accepted interrupt request to the ILM) RETI instruction? YES NO Execute ordinary instruction (including interrupt processing) NO Return processing Return the dedicated registers from the system stack, call the interrupt routine, and return to the previous routine S "1" (Activates the system stack) PCB, PC interrupt vector (Branch to the interrupt processing routine) Repetition of string type (*1) instruction completed? YES Move the pointer to the next instruction by PC update *1 When a string type instruction is being executed, the interrupt is evaluated in each step. I : Interrupt enable flag of the condition code register (CCR) IF : Interrupt request flag of the peripheral function IE : Interrupt enable flag of the peripheral function ILM : Interrupt level mask register (in the PS) ISE : EI2OS enable flag of the interrupt control register (ICR) 118 IL : Interrupt level setting bit of the interrupt control register (ICR) S : Stack flag of the condition code register (CCR) PCB : Program bank register PC : Program counter: 6.4 Hardware Interrupts 6.4.3 Procedure for Using Hardware Interrupts Before hardware interrupts can be used, the system stack area, peripheral function (resource), and interrupt control register (ICR) must be set. ■ Procedure for Using Hardware Interrupts Figure 6.4-4 Procedure for Using Hardware Interrupts Start (1) Set the system stack area (2) Initialize the peripheral function (3) Set the ICR in the interrupt controller Interrupt processing program Stack processing branches to the interrupt vector (8) Processing for interrupt to the peripheral function (execute the interrupt processing routine) (9) Clear the interrupt cause (10) Interrupt return instruction (RETI) (7) (4) (5) Set operation start for the peripheral function. Set the interrupt enable bit to enable Hardware processing Set the ILM and I in the PS Main program (6) Interrupt request generated Main program 1. Set the system stack area. 2. Set the operation of a peripheral function (resource). 3. Set the interrupt control register (ICR). 4. Set the interrupt enable bit of the peripheral function (resource) to enable the output of interrupt requests. 5. Set the interrupt level mask register (ILM) and interrupt enable flag (I) to interrupt acceptable. 6. If an interrupt request of the peripheral function (resource) is detected, a hardware interrupt request is output. 7. The interrupt processing hardware saves the dedicated register values to the system stack. The processing then branches to the interrupt processing program. 119 CHAPTER 6 INTERRUPTS 8. The interrupt processing program processes the peripheral function (resource) in response to the generated interrupt. 9. Clear the peripheral function (resource) interrupt request. 10.Execute the interrupt return instruction (RETI instruction), and return to the program before branching. 120 6.4 Hardware Interrupts 6.4.4 Multiple Interrupts Multiple hardware interrupts can be implemented in response to multiple interrupt requests from peripheral functions (resources). However, multiple extended intelligent I/O services cannot be activated. ■ Multiple Interrupts ❍ Operation of multiple interrupts If an interrupt request with an interrupt level that is higher than the one being executed is output, the current interrupt processing is suspended and the higher-priority interrupt request is executed. When the processing of the higher-priority interrupt ends, the previous interrupt processing resumes. If, during execution of interrupt processing, an interrupt request with a level equal to or lower than the current interrupt processing is output, the new interrupt request is suspended until the current interrupt processing ends, unless the I flag of the condition code register (ICR) or the interrupt level mask register (ILM) is changed. When the current interrupt processing ends, the suspended interrupt request is executed. Other multiple interrupts to be activated during an interrupt can be temporarily disabled by setting the I flag in the condition code register (CCR) in the interrupt processing routine to interrupts not allowed (CCR: I = 0) or the interrupt level mask register (ILM) to interrupts not allowed (ILM = 000B). Note: • 0 to 7 can be set as the interrupt level. If level 7 is set, the CPU does not accept interrupt requests. • The extended intelligent I/O service (EI2OS) cannot be used for the activation of multiple interrupts. During processing of the extended intelligent I/O service (EI2OS), all other interrupt requests and extended intelligent I/O service requests are held. 121 CHAPTER 6 INTERRUPTS ❍ Example of multiple interrupts This example of multiple interrupt processing assumes that a timer interrupt is given a priority that is higher than an A/D converter interrupt. In this example, the A/D converter interrupt level is set to 2, and the timer interrupt level is set to 1. If a timer interrupt is generated during processing of the A/D converter interrupt, the processing shown in Figure 6.4-5 "Example of Multiple Interrupt" is performed. Figure 6.4-5 Example of Multiple Interrupt Main program A/D interrupt processing Interrupt level 2 (ILM = 010B) Timer interrupt processing Interrupt level 1 ILM = 001B) Peripheral initialization (1) (3) Timer interrupt generated A/D interrupt generated (2) (4) Timer interrupt processing Interrupted Restart Main processing restarts (8) (6) A/D interrupt processing (5) Timer interrupt return (7) A/D interrupt return 122 • At the start of A/D converter interrupt processing, the value in the interrupt level mask register (ILM) indicates the A/D converter interrupt level (ICR:IL2 to IL0) (2 in this example). If an interrupt request with level 1 or 0 is generated, the interrupt processing for level 1 or 0 takes precedence. • When the interrupt processing ends and the return instruction (RETI) is executed, the values of the dedicated registers (A, DPR, ADB, DTB, PCB, PC, and PS) saved to the stack are restored and the interrupt mask register (ILM) is set back to the value that it had before the interruption. 6.4 Hardware Interrupts 6.4.5 Hardware Interrupt Processing Time The time for completion of the currently executed instruction and the interrupt handling time apply from the output of a hardware interrupt request until the interrupt processing routine is executed. ■ Hardware Interrupt Processing Time The interrupt request sampling wait time and the interrupt handling time (time required to prepare for interrupt processing) are required from the output of a hardware interrupt request until the interrupt processing routine is executed. Figure 6.4-6 Interrupt Processing Time CPU operation Interrupt wait time Ordinary instruction execution Interrupt request sampling wait time Interrupt handling Interrupt processing routine Interrupt handling time ( θ machine cycle) (*1) Interrupt request generation * : The final instruction cycle samples the interrupt request here. : One machine cycle corresponds to one machine clock ( φ ). ❍ Interrupt request sampling wait time The interrupt request sampling wait time refers to the time required from the output of an interrupt request by a peripheral function (resource) until the instruction being executed terminates. The CPU checks through sampling whether an interrupt request is output in the final cycle of an instruction being executed. The interrupt request sampling wait time is required because no interrupt request can be recognized while an instruction is being executed. Reference: The maximum interrupt request sampling wait time applies when an interrupt request is output immediately after execution of the POPW RW0, ... RW7 instruction (45 machine cycles) with the longest execution cycle is started. 123 CHAPTER 6 INTERRUPTS ❍ Interrupt handling time (φ machine cycle) After accepting an interrupt request, the CPU saves the values of dedicated registers to the system stack and fetches the interrupt vector. The interrupt handling time is therefore required. Obtain the interrupt handling time by using the following equations: When an interrupt starts to be processed: φ =24 + 6 x Z machine cycles When control is returned from an interrupt: φ =11 + 6 x Z machine cycles (RETI instruction) The interrupt handling time varies depending on the address of the stack pointer. Table 6.4-3 Interpolation Values (Z) for the Interrupt Handling Time Address pointed to by the stack pointer Interpolation value (Z) External 8-bit +4 External even-numbered address +1 External odd-numbered address +4 Internal even-numbered address 0 Internal odd-numbered address +2 Reference: One machine cycle equals one clock cycle of the machine clock (φ). 124 6.5 Software Interrupts 6.5 Software Interrupts When the software interrupt instruction is executed, control is transferred from the main program to the interrupt processing program. Hardware interrupts are disabled while the software interrupt instruction is being executed. ■ Software Interrupt Activation ❍ Software interrupt activation The INT instruction is used to activate a software interrupt. A software interrupt does not have an interrupt request flag bit or enable flag like that of a hardware interrupt. Thus, an interrupt request is output whenever the INT instruction is executed. ❍ Hardware interrupt suppression Since the INT instruction does not have interrupt levels, the interrupt level mask register (ILM) is not updated. During the execution of the INT instruction, the I flag of the condition code register (CCR) is set to 0, and hardware interrupts are masked. To enable hardware interrupts during software interrupt processing, set the I flag of the condition code register (CCR) to "1" in the software interrupt processing routine. ❍ Software interrupt operation When the CPU fetches the INT instruction, the software interrupt processing microcode is activated. This microcode saves the internal CPU registers on the system stack, masks hardware interrupts (CCR: I = 0), and branches to the corresponding interrupt vector. Reference: See Section 6.2 "Interrupt Causes and Interrupt Vectors", in CHAPTER 6 "INTERRUPTS" for more information about the allocation of interrupt numbers and interrupt vectors. ■ Returning from a Software Interrupt In the interrupt processing program, when the interrupt return instruction (RETI instruction) is executed, the data saved to the system stack is restored to the dedicated registers and the processing that was being executed before branching for the interrupt is resumed. 125 CHAPTER 6 INTERRUPTS ■ Software Interrupt Operation Figure 6.5-1 Software Interrupt Operation Internal bus PS,PC (2) Microcode (1) PS I S IR Queue Fetch RAM PS I S IR : Processor status : Interrupt enable flag : Stack flag : Instruction register 1. A software interrupt instruction is (INT instruction) executed. 2. The values of the dedicated registers are saved to the system stack. Hardware interrupts are masked. The processing branches to the interrupt vector. 3. The RETI instruction in the user interrupt processing routine terminates the interrupt processing. Note: When the program bank register (PCB) is "FFH", the vector area of the CALLV instruction overlaps the INT #vct8 instruction table. When you create software, watch for duplicated addresses of the CALLV and INT #vct8 instructions. 126 6.6 Interrupt of Extended Intelligent I/O Service (EI2OS) 6.6 Interrupt of Extended Intelligent I/O Service (EI2OS) The extended intelligent I/O service (El2OS) automatically transfers data between a peripheral function (resource) and memory. When the data transfer terminates, a hardware interrupt is generated. ■ Extended Intelligent I/O Service (EI2OS) The extended intelligent I/O service (EI2OS) is a type of hardware interrupt. EI2OS transfers data between a peripheral function (resource) and memory. The user should create program to activate and terminate EI2OS but need not create a data transfer program. ❍ Advantages of extended intelligent I/O service (EI2OS) Compared to data transfer performed by the interrupt processing routine, EI2OS has the following advantages. • Coding a transfer program is not necessary, reducing program size. • Since transfer can be activated due to an interrupt cause of a peripheral function (resource), there is no need of polling for a data transfer cause. • Incrementing of a transfer address can be selected. • Incrementing or no update can be selected for the I/O register address. ❍ Extended intelligent I/O service (EI2OS) termination interrupt The processing branches to the interrupt processing routine when data transfer by EI2OS terminates. An interrupt processing program can determine the EI2OS termination cause by checking the EI2OS status bits (S1 and S0) of the interrupt control register (ICR). Reference: Interrupt numbers and interrupt vectors are permanently set for each peripheral. See Section 6.2 "Interrupt Causes and Interrupt Vectors", in CHAPTER 6 "INTERRUPTS" for more information. ❍ Interrupt control register (ICR) This register, which is located in the interrupt controller, activates EI2OS, specifies the EI2OS channel, and displays the EI2OS termination status. 127 CHAPTER 6 INTERRUPTS ❍ Extended intelligent I/O service (EI2OS) descriptor (ISD) This descriptor, which is located in RAM at 000100H to 00017FH, is an eight-byte data that retains the transfer mode, resource address, transfer count, and buffer address. The descriptor handles 16 channels. The channel is specified by the interrupt control register (ICR). Note: When the extended intelligent I/O service (EI2OS) is operating, execution of the CPU program stops. ■ Operation of the Extended Intelligent I/O Service (EI2OS) Figure 6.6-1 Extended Intelligent I/O Service (EI2OS) Operation Memory space Peripheral function (resource) by I/OA Resource register Resource register (5) CPU Interrupt request (3) ISD by ICS (2) (3) (1) Interrupt control register (ICR) Interrupt controller by BAP (4) Buffer by DCT ISD : EI2OS OS descriptor I/OA : I/O address pointer BAP : Buffer address pointer ICS : EI2OS channel setting bit in the interrupt control register (ICR) DCT: Data counter 1. A peripheral function (resource) outputs an interrupt request. 2. The interrupt controller selects the EI2OS descriptor in accordance with the setting in the interrupt control register (ICR). 3. The transfer source and transfer destination are read from the descriptor. 4. Transfer is performed between resource and memory. 5. After data transfer is completed, the interrupt request flag bit of the peripheral function (resource) is cleared to "0". 128 6.6 Interrupt of Extended Intelligent I/O Service (EI2OS) 6.6.1 Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) The extended intelligent I/O service (EI2OS) descriptor (ISD) resides in internal RAM at 000100H to 00017FH. The ISD consists of 8 bytes x 16 channels. ■ Configuration of the Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) The ISD consists of 8 bytes x 16 channels. Figure 6.6-2 Configuration of El2OS Descriptor (ISD) MSB LSB Data counter upper 8 bits (DCTH) H Data counter lower 8 bits (DCTL) I/O register address pointer upper 8 b its (I/OAH) I/O register address pointer lower 8 b its (I/OAL) EI2OS status register (ISCS) Buffer address pointer upper 8 bits (BAPH) Buffer address pointer middle 8 bits (BAPM) First ISD address (000100H + 8 x ICS) Buffer address pointer lower 8 bits (BAPL) L MSB : Most significant bit LSB : Least significant bit 129 CHAPTER 6 INTERRUPTS Table 6.6-1 EI2OS descriptor area 130 Channel Descriptor address 0 000100H 1 000108H 2 000110H 3 000118H 4 000120H 5 000128H 6 000130H 7 000138H 8 000140H 9 000148H 10 000150H 11 000158H 12 000160H 13 000168H 14 000170H 15 000178H 6.6 Interrupt of Extended Intelligent I/O Service (EI2OS) Registers of the Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) 6.6.2 The extended intelligent I/O service (EI2OS) descriptor (ISD) consists of the following registers, which account for a total of eight bytes: • Data counter (DCT: 2 bytes) • I/O register address pointer (I/OA: 2 bytes) • EI2OS status register (ISCS: 1 byte) • Buffer address pointer (BAP: 3 bytes) The initial values of these registers are undefined. ■ Data Counter (DCT) The DCT is a 16-bit register in which a transfer data byte count can be set. Every time one byte of data is transferred, the counter is decremented by one. EI2OS terminates when the data counter reaches "0000H". Figure 6.6-3 Configuration of DCT DCTH Bit 15 14 13 12 11 DCTL 10 9 8 7 6 5 4 3 2 1 0 DCT B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 Initial value XXXXXXXXXXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: Read-write X : Undefined ■ I/O Register Address Pointer (IOA) The IOA is a 16-bit register that indicates the lower address (A15 to A0) of the I/O register used to transfer data to and from the buffer. The upper address (A23 to A16) is 00H. Any I/O from 0000H to FFFFH can be specified by address. Figure 6.6-4 Configuration of I/O Register Address Pointer (IOA) I/OAH Bit IOA 15 14 13 12 11 I/OAL 10 9 8 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 Initial value XXXXXXXXXXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: Read-write X : Undefined 131 CHAPTER 6 INTERRUPTS ■ Extended Intelligent I/O Service (EI2OS) Status Register (ISCS) The ISCS is an 8-bit register. The ISCS indicates the update/fixed for the buffer address pointer and I/O register address pointer, transfer data format (byte or word), and transfer direction. Figure 6.6-5 Configuration of EI2OS Status Register (ISCS) Bit 7 6 5 RESV RESV RESV R/W R/W R/W 4 3 2 1 0 Initial value IF BW BF DIR SE XXXXXXXX B R/W R/W R/W R/W R/W SE EI2OS termination control bit 0 Not terminated by a request from the peripheral function. Terminated by a request from the peripheral function 1 Data transfer direction specification bit DIR 0 1 I/O register address pointer -> buffer address pointer. Buffer address pointer -> I/O register address pointer BAP update/fixed selection bit BF 0 After data transfer, the buffer address pointer is updated. (*1) 1 After data transfer, the buffer address pointer is not updated. BW Transfer data length specification bit 0 Byte 1 Word IF IOA update/fixed selection bit 0 After data transfer, the I/O register address pointer is updated. (*2) 1 After data transfer, the buffer address pointer is not updated. RESV Reserved bits 0 must be written to these bits. R/W : Read-write X : Undefined *1 : Only the lower 16 bits of the buffer address pointer change. The buffer address pointer can only be incremented. *2 : The address pointer can only be incremented. 132 6.6 Interrupt of Extended Intelligent I/O Service (EI2OS) ■ Buffer Address Pointer (BAP) The buffer address pointer (BAP) is a 24-bit register in which a memory address of the data transfer source can be set in the EI2OS operation. Data can be transferred between a 16M-byte memory address and a peripheral function (resource) address because a BAP exists in every channel of EI2OS. If the BAP update/fixed selection bit (BF) of the EI2OS status register (ISCS) is set to "0", only the lower 16 bits (BAPM and BAPL) are incremented and the upper 8 bits (BAPH) are not incremented. Figure 6.6-6 Configuration of Buffer Address Pointer (BAP) bit23 BAP to bit16 bit15 to bit8 bit7 to BAPH BAPM BAPL (R/W) (R/W) (R/W) bit0 Initial value XXXXXXB R/W : Read-write X : Undefined Note: • The maximum transfer count that can be specified by the data counter (DCT) is 65,536 (64 K bytes). • The area that can be specified by the I/O address pointer (IOA) extends from 000000H to 00FFFFH. • The area that can be specified with the buffer address pointer (BAP) extends from 000000H to FFFFFFH. 133 CHAPTER 6 INTERRUPTS 6.6.3 Operation of the Extended Intelligent I/O Service (EI2OS) The CPU uses EI2OS to transfer data if a peripheral function (resource) outputs an interrupt request while the corresponding interrupt control register (ICR) is set to enable the activation of EI2OS. When the EI2OS processing terminates, the hardware interrupt processing is performed. ■ Operation Flow of the Extended Intelligent I/O Service (EI2OS) Figure 6.6-7 Flow of Extended Intelligent I/O Service (El2OS) Operation Interrupt request generated by peripheral function ISE="1" NO YES Interrupt sequence Read ISD/ISCS Termination request from peripheral function YES DIR="1" YES SE="1" NO NO YES NO Data indicated by BAP (data transfer) memory indicated by I/OA Data indicated by I/OA (data transfer) memory indicated by BAP IF="0" YES NO BF="0" DCT="00B" NO Update I/OA Update value by BW Update BAP YES NO Decrement DCT Update value by BW (-1) YES Set S1 and S0 to "00B" EI2OS termination processing Set S1 and S0 to "01B" Clear interrupt request from the peripheral function Clear ISE to "0" Return to CPU operation EI2OS ISD : descriptor ISCS : EI2OS status register IF : I/OA update/fixed selection bit in the EI2OS status register (ISCS) BW : Transfer data length specification bit in the EI2OS status register (ISCS) BF : BAP update/fixed selection bit in the EI2OS status register (ISCS) 134 Set S1 and S0 to "11B" Interrupt sequence DIR : Data transfer direction specification bit in the EI2OS status register (ISCS) SE : EI2OS termination control bit in the EI2OS status register (ISCS) DCT : Data counter I/OA : I/O register address pointer BAP : Buffer address pointer ISE : EI2OS enable bit in the interrupt control register (ICR) S1, S0: EI2OS status in the interrupt control register (ICR) 6.6 Interrupt of Extended Intelligent I/O Service (EI2OS) 6.6.4 Procedure for Using the Extended Intelligent I/O Service (EI2OS) Before the extended intelligent I/O service (EI2OS) can be used, the system stack area, extended intelligent I/O service (EI2OS) descriptor, peripheral function (resource), and interrupt control register (ICR) must be set. ■ Procedure for Using the Extended Intelligent I/O Service (EI2OS) Figure 6.6-8 Procedure for Using the Extended Intelligent I/O Service (EI2OS) Software processing Hardware processing Start Initialization Set the system stack area Set the EI2OS descriptor Initialize the peripheral function Set the interrupt control register (ICR) Set the built-in resource to start operation. Set the interrupt enable bit Set the ILM and I in the PS Execute the user program (Interrupt request) and (ISE = "1") S1, S0 = "00B" Transfer data NO Decide whether to end counting or to branch to an interrupt requested by the resource (Branch to interrupt vector) YES S1, S0 = "01B" or S1, S0 = "11B" Set the extended intelligent I/O service again (switch channels) Process data in the buffer RETI ISE : EI2OS enable bit in the interrupt control register (ICR) S1, S0 : EI2OS status of the interrupt control register (ICR) 135 CHAPTER 6 INTERRUPTS 6.6.5 Processing Time of the Extended Intelligent I/O Service (EI2OS) The time required to process the extended intelligent I/O service (EI2OS) varies with the settings for the EI2OS descriptor (ISD): • • • • • Setting in the EI2OS status register (ISCS) Address pointed to by the I/O register address pointer (I/OA) Address pointed to by the buffer address pointer (BAP) External data bus length for external access Transfer data length Because the hardware interrupt is activated when data transfer by El2OS terminates, the interrupt handling time is added. ■ Processing Time (one transfer time) of the Extended Intelligent I/O Service (EI2OS) ❍ When data transfer continues The EI2OS processing time for data transfer continuation is shown in Table 6.6-2 "Extended Intelligent I/O Service Execution Time" based on the EI2OS status register (ISCS) setting. Table 6.6-2 Extended Intelligent I/O Service Execution Time EI2OS termination control bit (SE) setting I/OA update/fixed selection bit (IF) setting BAP address update/fixed selection bit (BF) setting Terminates due to termination request from the peripheralI Ignores termination request from the peripheral Fixed Update Fixed Update Fixed 32 34 33 35 Update 34 36 35 37 Unit: Machine cycle (One machine cycle corresponds to one clock cycle of the machine clock (φ). As shown in Table 6.3-3 "Correspondence between the EI2OS Channel Selection Bits and Descriptor Addresses", interpolation is necessary depending on the El2OS execution condition. 136 6.6 Interrupt of Extended Intelligent I/O Service (EI2OS) Table 6.6-3 Data Transfer Interpolation Value for EI2OS Execution Time I/O register address pointer Buffer address pointer Internal access External access B/Even Odd B/Even 8/Odd 0 +2 +1 +4 Internal access B/Even Odd +2 +4 +3 +6 External access B/Even +1 +3 +2 +5 8/Odd +4 +6 +5 +8 B: Byte data transfer 8: External bus using the 8-bit word transfer Even: Even-numbered address word transfer Odd: Odd-numbered address word transfer ❍ When the data counter (DCT) count terminates (final data transfer) Interrupt handling time is added because the hardware interrupt is activated when data transfer by EI2OS terminates. The EI2OS processing time when counting terminates is calculated by using the equation below. Z in this equation is a correction value for the interrupt handling time. EI2OS processing time when counting terminates = EI2OS processing time when data is transferred + (21 + 6 x Z) machine cycles Interrupt handling time The interrupt handling time is different for each address pointed to by the stack pointer. Table 6.6-4 Interpolation Value (Z) for the Interrupt Handling Time Address pointed to by the stack pointer Interpolation value (Z) External 8-bit +4 External even-numbered address +1 External odd-numbered address +4 Internal even-numbered address 0 Internal odd-numbered address +2 137 CHAPTER 6 INTERRUPTS ❍ For termination by a termination request from the peripheral function (resource) When data transfer by EI2OS is terminated before completion due to a termination request from the peripheral function (resource) (ICR: S1, S0 = 11B), the data transfer is not performed and a hardware interrupt is activated. The EI2OS processing time is calculated with the following formula. Z in the formula indicates the interpolation value for the interrupt handling time (Table 6.6-4 "Interpolation Value (Z) for the Interrupt Handling Time"). EI2OS processing time for termination before completion = 36 + 6 x Z) machine cycles One machine cycle corresponds to one clock cycle of the machine clock (φ). 138 6.7 Exception Processing Interrupt 6.7 Exception Processing Interrupt In the MB90M405 series, exception processing occurs if an undefined instruction is executed. Exception processing is basically the same as an interrupt. When an exception occurs between instructions, program processing is interrupted and the processing branches to the exception processing routine. Exception processing, occurring due to an unexpected operation, can be used to execute an undefined instruction and detect a CPU runaway status during debugging. ■ Exception Processing ❍ Exception processing operation In the MB90M405 series, the processing branches to the exception processing routine if an instruction undefined in the instruction map is executed. The following processing is executed before exception processing branches to the interrupt routine: • The A, DPR, ADB, DTB, PCB, PC, and PS registers are saved to the system stack. • The I flag of the condition code register (CCR) is cleared to 0, and hardware interrupts are masked. • The S flag of the condition code register (CCR) is set to 1, and the system stack is activated The program counter (PC) value saved to the stack is the exact address where the undefined instruction is stored. For 2-byte or longer instruction codes, the code identified as undefined is stored at this address. When the exception factor type must be determined within the exception processing routine, use this PC value. ❍ Return from exception processing If the RETI instruction is used to return control from exception processing, a branch to the exception processing routine occurs again because the PC is pointing to an undefined instruction. Use a software reset or input the "L" level from the RST pin (an external reset). 139 CHAPTER 6 INTERRUPTS 6.8 Stack Operations for Interrupt Processing Once an interrupt is accepted, the contents of the dedicated registers are saved to the system stack before a branch to interrupt processing. Execute the interrupt return instruction after the interrupt processing terminates to restore the values saved on the system stack to the dedicated registers. ■ Stack Operations at the Start of Interrupt Processing Once an interrupt is accepted, the CPU saves the contents of the current dedicated registers to the system stack in the order given below: • Accumulator (A) • Direct page register (DPR) • Additional data bank register (ADB) • Data bank register (DTB) • Program bank register (PCB) • Program counter (PC) • Processor status (PS) Figure 6.8-1 Stack Operations at the Start of Interrupt Processing Immediately before interrupt SSB 00H 08FE H A 0000 H 08FE H AH AL DPR 0 1 H ADB 0 0 H DTB PCB F F H PC 803FH PS 20E0H SSB 08FFH 08FE SSP 00H Immediately after interrupt Address Memory 08F2H Address Memory 00H 08FFH 08FE H SP XX H XX H XX H XX H XX H XX H XX H XX H XX H XX H XX H XX H H SSP 08F2H A 0000 H 08FE H AH AL DPR 0 1 H ADB 0 0 H DTB PCB F F H 00H L PC 803FH PS 20E0H Byte 08F2H SP 00H 00H 08H FE H 01H 00H 00H FFH 80H 3FH 20H E0H Byte AH AL DPR ADB DTB PCB PC PS SP after update ■ Stack Operations on Return from Interrupt Processing When the interrupt return instruction (RETI) is executed at the termination of interrupt processing, the PS, PC, PCB, DTB, ADB, DPR, and A values are returned from the stack in reverse order from the order they were placed on the stack. The dedicated registers are restored to the status they had immediately before the start of interrupt processing. 140 6.8 Stack Operations for Interrupt Processing ■ Stack Area ❍ Stack area allocation The stack area is used for saving and restoring the program counter (PC) when the subroutine call instruction (CALL) and vector call instruction (CALLV) are executed in addition to interrupt processing. The stack area is used for temporary saving and restoring of registers by the PUSHW and POPW instructions. The stack area is allocated together with the data area in RAM. Figure 6.8-2 Stack Area Vector table (interrupt vector call instruction for a reset) FFFFFF H FFFC00 H ROM area FF0000H *1 000D00H *2 Built-in RAM area Stack area 000380 H 000180 H General-purpose register bank area 000100 H 0000C0H 000000 H Built-in I/O area *1 The internal ROM is different for each model. *2 The internal RAM is different for each model. Note: • Generally set an even-numbered address in the stack pointers (SSP and USP). If an oddnumbered address is set, one extra cycle is required to save data to, and restore data from the stack. • Allocate the system stack area, user stack area, and data area so that they do not overlap. ❍ System stack and user stack The system stack area is used for interrupt processing. When an interrupt is output, the user area being used is switched to the system stack. Use only the system stack unless the stack space needs to be divided in particular. 141 CHAPTER 6 INTERRUPTS 6.9 Sample Programs for Interrupt Processing This section contains sample programs for interrupt processing. ■ Sample Programs for Interrupt Processing ❍ Processing specifications The following is a sample program for an interrupt that uses external interrupt 0 (INT0). 142 6.9 Sample Programs for Interrupt Processing ❍ Sample coding DDR1 ENIR EIRR ELVR ICR00 STACK EQU 000011H ;Port 1 direction register EQU 000028H ;DTP/interrupt permission register EQU 000029H ;DTP/interrupt cause register EQU 00002AH ;Request level setting register EQU 0000B0H ;Interrupt control register 00 SSEG ;Stack RW 100 STACK_T RW 1 STACK ENDS ;-------- Main program ---------------------------------------------------------CODE CSEG START: MOV RP,#0 ;General-purpose registers use the first bank. MOV ILM, #07H ;Sets ILM in PS to level 7. MOV A, #!STACK_T ;Sets system stack. MOV SSB, A MOVW A, #STACK_T ;Sets stack pointer, then MOVW SP, A ;Sets SSP because S flag = 1. MOV DDR1, #00000000B ;Sets P10/INT0 pin to input. OR CCR, #040H ;Sets I flag of CCR in PS, enables interrupts. MOV I:ICR00, #00H ;Sets interrupt level to 0 (highest priority). MOV I:ELVR, #00000001B ;Requests that INT0 be made level H. MOV I:EIRR, #00H ;Clears INT0 interrupt cause. MOV I:ENIR, #01H ;Enables INT0 input. LOOP: NOP ;Dummy loop NOP NOP NOP BRA LOOP ;Unconditional jump ---------Interrupt program -----------------------------------------------------ED_INT1: MOV I:EIRR, #00H ;Acceptance of new INT0 not allowed NOP NOP NOP NOP NOP NOP RETI ;Return from interrupt CODE ENDS ;--------Vector setting---------------------------------------------------------VECT CSEG ABS=0FFH ORG 0FFDH ;Sets vector for interrupt #11 (0BH). DSL ED_INT1 ORG 0FFDCH ;Sets reset vector. DSL START DB 00H ;Sets single-chip mode. VECT ENDS END START 143 CHAPTER 6 INTERRUPTS ■ Processing Specifications of Sample Program for Extended Intelligent I/O Service (EI2OS) ❍ Processing Specifications • This program detects the H level signal input to the INT0 pin and activates the extended intelligent I/O service (EI2OS). • When the H level is input to the INT0 pin, El2OS is activated. Data is transferred from port 0 to the memory at the 3000H address. • The number of transfer data bytes is 100 bytes. After 100 bytes are transferred, an interrupt is generated because EI2OS transfer has terminated. ❍ Sample coding DDR1 ENIR EIRR ELVR ICR00 BAPL BAPM BAPH ISCS I/OAL I/OAH DCTL DCTH ER0 STACK EQU 000011H ;Port 1-direction register EQU 000028H ;DTP/interrupt permission register EQU 000029H ;DTP/interrupt cause register EQU 00002AH ;Request level setting register EQU 0000B0H ;Interrupt control register 00 EQU 000100H ;Lower buffer address pointer EQU 000101H ;Middle buffer address pointer EQU 000102H ;Upper buffer address pointer EQU 000103H ;EI2OS status EQU 000104H ;Lower I/O address pointer EQU 000105H ;Upper I/O address pointer EQU 000106H ;Low-order data counter EQU 000107H ;High-order data counter EQU EIRR:0 ;Definition of external interrupt request flag bit SSEG ;Stack RW 100 STACK_T RW 1 STACK ENDS ;-------------------Main program------------------------------------------------CODE CSEG START: AND CCR, #0BFH ;Clears the I flag of the CCR in the PS and ;prohibits interrupts. MOV RP, #00 ;Sets the register bank pointer. MOV A, #!STACK_T ;Sets the system stack. MOV SSB, A MOVW A, #STACK_T ;Sets the stack pointer, then MOVW SP, A ;Sets SSP because the S flag = 1. MOV I:DDR1, #00000000B ;Sets the P10/INT0 pin to input. MOV BAPL, #00H ;Sets the buffer address (003000H). MOV BAPM, #30H MOV BAPH, #00H MOV ISCS, #00010001B ;No I/O address update, byte transfer, buffer ;address updated, I/O -> buffer transfer, ;terminated by the peripheral function. MOV IOAL, #00H ;Sets the transfer source address ;(port 0:000000H). MOV IOAH, #00H MOV DCTL, #64H ;Sets the number of transfer bytes (100 bytes). MOV DCTH, #00H 144 6.9 Sample Programs for Interrupt Processing MOV MOV MOV MOV MOV OR I:ICR00,#00001000B ;EI2OS channel 0, EI2OS enable, interrupt level 0 ;(highest priority) I:ELVR, #00000001B ;Requests that INT0 be made H level. I:EIRR, #00H ;Clears the INT0 interrupt cause. I:ENIR, #01H ;Enables INT0 interrupts. ILM, #07H ;Sets the ILM in the PS to level 7. CCR, #040H ;Sets the I flag of the CCR in the PS and ;enables interrupts. : LOOP BRA LOOP ;Infinite loop ;---------------Interrupt program-----------------------------------------------WARI CLRB ER0 ;Clears interrupt/DTP request flag. : User processing ;Checks EI2OS termination factor, : ;processes data in buffer, sets EI2OS again. RETI CODE ENDS ;---------------Vector processing-----------------------------------------------VECT CSEG ABS=0FFH ORG 0FFD0H ;Sets vector for interrupt #11 (0BH). DSL WARI ORG 0FFDCH ;Sets reset vector. DSL START DB 00H ;Sets single-chip mode. VECT ENDS END START 145 CHAPTER 6 INTERRUPTS 146 CHAPTER 7 SETTING A MODE This chapter describes the operating modes and the memory access modes of the MB90M405 series. 7.1 "Setting a Mode" 7.2 "Mode Pins (MD2 to MD0)" 7.3 "Mode Data" 147 CHAPTER 7 SETTING A MODE 7.1 Setting a Mode Set the mode pin level used after a reset and the mode data in the mode register to determine the operating mode. ■ Mode Setting Operating mode RUN mode FLASH WRITE mode Bus mode Single-chip mode ■ Operating Modes An operating mode can be specified by the mode pins (MD2 to MD0) and the bus mode setting bits (M1 and M0) of the mode data registers. The microcontroller performs an ordinary start of operation and writes to FLASH memory in the specified operating mode. Note: Set single-chip mode for the MB90M405 series. To set single-chip mode, set the MD2 to MD0 pins to "011B" and the M1 and M0 bits of the mode data register to "00B", respectively. ■ Bus Mode The bus mode varies depending on whether the memory into which the reset vector should be read is internal or external. Set the MD2 to MD0 pins and the M1 and M0 bits of the mode data register to specify a bus mode. Set the MD2 to MD0 pins to determine a bus mode in which a reset vector and mode data should be read. Additionally, set the M1 and M0 bits of the mode data register to specify a bus mode. Reference: The term RUN mode refers to the current mode in which the CPU operates. RUN modes include main clock mode, in which the CPU operates based on the main clock; PLL clock mode, in which the CPU operates based on the PLL clock; and low power consumption mode. For more information, see Chapter 5 "Low Power Consumption Mode". Note: For the MB90M405 series, specify single-chip mode. To specify single-chip mode, set the MD2 to MD0 pins to 011B and the bus mode setting bits (M1 and M0) of the mode data register to 00B. 148 7.2 Mode Pins (MD2 to MD0) 7.2 Mode Pins (MD2 to MD0) Three external pins, MD2 to MD0, are supported as the mode pins. These are used to specify how the reset vector and mode data are fetched. ■ Mode Pins (MD2 to MD0) Use the mode pins to specify whether a reset vector should be read from external or internal memory. Use the mode data register to specify the external data bus width if a reset vector should be read from external memory. For a built-in flash memory type, use the mode pins to specify the flash memory write mode in which a program should be written to the built-in flash memory. Table 7.2-1 Mode Pin Settings MD2 MD2 MD0 0 0 0 0 0 1 0 1 0 Mode name Reset vector access area External data bus width Remarks Setting not allowed Internal vector mode Specified in the mode data register The reset sequence and subsequent sequences are controlled by mode data. 0 1 1 1 0 0 1 0 1 1 1 0 Flash serial write mode (*1) - - - 1 1 1 Flash memory mode - - - Internal memory Setting not allowed MD2 to MD0: Connect the pins to VSS for 0 and to VCC for 1. *1: The flash memory serial write cannot be executed just by setting the mode terminal. The settings for other pins must be made as well. For more information, see "Example of a Serial Write Connection". Note: For the MB90M405 series, specify single-chip mode. To specify single-chip mode, set the MD2 to MD0 pins to 011B and the bus mode setting bits (M1 and M0) of the mode data register to 00B. 149 CHAPTER 7 SETTING A MODE 7.3 Mode Data The mode data register is at memory location FFFFDFH, and is used to specify the operation after a reset sequence. ■ Mode Data The mode data at address "FFFFDFH" can be fetched to the mode data register while a reset sequence is being executed. The contents of the mode data register can be changed while a reset sequence is being executed. They cannot be changed using an instruction. The mode data setting takes effect after a reset sequence. Figure 7.3-1 Mode Data Configuration Bit Mode data register 7 6 5 4 3 2 1 0 M1 M0 0 0 S0 0 0 0 Function extension bits (reserved area) Bus mode setting bits ■ Bus Mode Setting Bits The bus mode setting bits specify operating mode after a reset sequence. Table 7.3-1 Bus Mode Setting Bits and Functions 150 M1 M0 0 0 0 1 1 0 1 1 Function Single-chip mode (Setting not allowed) Remarks Described in this manual - 7.3 Mode Data Figure 7.3-2 Memory Map in Single-Chip Mode FFFFFFH ROM #1 for each model FE0000H 00FFFFH ROM mirror If ROM mirroring function is specified #2 for each model #3 for each model RAM : Access disabled I/O : Internal access 000100H 0000C0H 000000H Note: "#x for each model" is an address that depends on the model. For more information, see the memory map. ■ Relationship between Mode Pins and Mode Data Table 7.3-2 Relationship between Access Areas and Physical Addresses in Single-chip Mode Mode Single-chip mode MD2 MD1 MD0 M1 M0 0 1 1 0 0 Note: For the MB90M405 series, specify single-chip mode. To specify single-chip mode, set the MD2 to MD0 pins to 011B and the bus mode setting bits (M1 and M0) of the mode data register to 00B. 151 CHAPTER 7 SETTING A MODE 152 CHAPTER 8 I/O PORTS This chapter describes the functions and operations of the MB90M405 series I/O ports. 8.1 "Overview of I/O Ports" 8.2 "I/O Port Registers" 8.3 "Port 8" 8.4 "Port 9" 8.5 "Port A" 8.6 "Port B" 8.7 "Sample I/O Port Program" 153 CHAPTER 8 I/O PORTS 8.1 Overview of I/O Ports A maximum of 26 I/O ports (parallel I/O ports) are available. These ports can also be used as resource I/O pins (I/O pins of peripheral functions). ■ I/O Port Function I/O ports include port direction registers (DDR) and port data registers (PDR). Each bit in the DDR specifies input or output for a port pin. The PDR specifies the output data for a port pin. If the DDR sets an I/O port pin to input, the level value of the port pin is made ready by reading the PDR. If the DDR sets an I/O port pin to output, the value of the PDR is output to the port pin. The following lists the resources that are also used to function as I/O ports: • Port 8: Used as an I/O port and also as resource pins (external interrupt input pin, ICU, and UART) • Port 9: Used as an I/O port and also as resource pins (I2C and serial I/O ch3) • Port A: Used as an I/O port and also as resource pins (A/D converter and timing clock output) • Port B: Used as an I/O port and also as resource pins (A/D converter, serial I/O ch2, external interrupt input pin, and reload timer ch0) Table 8.1-1 Functions of Each Port I/O port Port 8 Port 9 Pin Input form P80 to P87 Output form I/O port P87 P86 P85 P84 P83 P82 Resource SO1 SC1 SI1 SO0 SC0 SI0 CMOS P90/SDA/SO3 to P91/SCL/SC3 Nch open drain CMOS (hysteresis) Port A Function PA0/AN0/TMCK to PA7/AN7 I/O port - - - - - - Resource - - - - - - P81 P80 IC1 IC0 INT1 INT0 P91 P90 SCL SDA SC3 SO3 PA0 I/O port PA7 PA6 PA5 PA4 PA3 PA2 PA1 Resource AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 TMCK CMOS Port B PB0/AN8 to PB7/AN15/INT3 I/O port PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 SO2 SC2 INT3 INT2 SI2 - - - TO TIN Resource Note: Ports A and B are also used as analog input pins. When using them as I/O ports, set port A and port B direction registers (DDRA and DDRB), the data registers (PDRA and PDRB), and analog input enable registers 0 and 1 (ADER0 and ADER1) to 00H. A reset initializes analog input enable registers 0 and 1 (ADER0 and ADER1) to FFH. 154 8.1 Overview of I/O Ports ■ Operation of an I/O Port Also Used for Resources When DDR Is Set to Port Output Figure 8.1-1 Pin Status of a Port Also Used for Resources When Resource Operation is Enabled or Disabled Resource operation enable/disable setting Pin status of a port also used for resources Resource operation enabled Dependent on resource operation Resource operation disabled Output of value set in the PDR 155 CHAPTER 8 I/O PORTS 8.2 I/O Port Registers This section lists the registers related to I/O port settings. ■ I/O Port Registers Table 8.2-1 Port Registers Register Read/Write Address Initial value Port 8 data register (PDR8) R/W 000008H XXXXXXXXB Port 9 data register (PDR9) R/W 000009H XXXXXXXXB Port A data register (PDRA) R/W 00000AH XXXXXXXXB Port B data register (PDRB) R/W 00000BH XXXXXXXXB Port 8 direction register (DDR8) R/W 000018H 00000000B Port 9 direction register (DDR9) R/W 000019H XXXXXX00B Port A direction register (DDRA) R/W 00001AH 00000000B Port B direction register (DDRB) R/W 00001BH 00000000B Analog input enable register 0 (ADER0) R/W 00001EH 11111111B Analog input enable register 1 (ADER1) R/W 00001FH 11111111B R/W: Read/write enabled X: Undefined -: Unused Notes: • If an RMW instruction is executed for a port data register (PDR) in port input mode, the pin level is read when a READ instruction is executed. Note that the bit value used for the same type of input port other than the one subject to bit operations may be changed. • If an RMW instruction is executed for a port data register (PDR) that is also used for resources in resource operation mode, the pin level is read for a pin that operates as a resource pin when a READ instruction is executed. Note that the bit value used for the same type of input port other than the one subject to bit operations may be changed. Table 8.2-2 What Is Read by READ after RMW Instruction Executed for a PDR 156 Resource operation enabled Resource operation disabled Port input mode (DDR = 00H) Pin level Pin level Port output mode (DDR = FFH) Pin level PDR value 8.2 I/O Port Registers Resource operation enable/disable setting Pin status of a port also used for resources Resource operation enabled Dependent on resource operation Input mode (DDR = 00H) : Hi-z Output mode (DDR = FFH) : A changed PDR value is output. Execution of RMW instruction RMW instruction execution timing for PDRA PDRA value Resource operation disabled Previous data Changes depending on the pin level when an RMW instruction is executed 157 CHAPTER 8 I/O PORTS 8.3 Port 8 Port 8 is an I/O port. This section describes the configuration and registers of Port 8 and provides a block diagram of the pins. ■ Port 8 Configuration Port 8 consists of the following: • I/O port pins/resource I/O pins (P80, IC0, INT0 to P87, and SO1) • Port 8 data register (PDR8) • Port 8 direction register (DDR8) ■ Port 8 Pins Table 8.3-1 Port 8 Pins Port name I/O form Pin name Port function P80/IC0/ INT0 IC0 P80 INT0 P81/IC1/ INT1 Port 8 IC1 P81 I/O port Output CMOS (hysteresis) CMOS E Trigger input for input capture 0 External interrupt 0 Trigger input for input capture 1 INT1 External interrupt 1 SI0 Serial data input 0 P82/SI0 P82 P83/SC0 P83 SC0 Serial clock I/O 0 P84/SO0 P84 SO0 Serial data output 0 P85/SI1 P85 SI1 Serial data input 1 P86/SC1 P86 SC1 Serial clock I/O 1 P87/SO1 P87 SO1 Serial data output 1 Note: For the circuit type, see Section 1.7 "I/O Circuit Types." 158 Input Circuit type Resource function 8.3 Port 8 ■ Block Diagram of the Port 8 Pins Figure 8.3-1 Block Diagram of the Port 8 Pins Internal data bus Resource input PDR8 read Input buffer I/O check circuit PDR8 Output buffer PDR8 write DDR8 Port 8 pin Standby control (LPMCR:SPL = "1") I/O control circuit Resource output ■ Port 8 Registers The Port 8 registers are the Port 8 data register (PDR8) and the Port 8 direction register (DDR8). The bits of each register correspond to the Port 8 pins on a one-to-one basis. Table 8.3-2 Port 8 Pins and Corresponding Register Bits Port name Register bits and corresponding port pins PDR8, DDR8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Corresponding pin P87 P86 P85 P84 P83 P82 P81 P80 Port 8 159 CHAPTER 8 I/O PORTS 8.3.1 Port 8 Registers (PDR8 and DDR8) This section describes the Port 8 registers. ■ Functions of the Port 8 Registers ❍ Port 8 data register (PDR8) The PDR8 register specifies the output value for each Port 8 pin. ❍ Port 8 direction register (DDR8) The DDR8 register specifies the I/O direction for each Port 8 pin. A pin functions as an output port when the bit corresponding to the pin is set to 1. A pin functions as an input port when the bit corresponding to the pin is set to 0. Table 8.3-3 Functions of the Port 8 Registers Register name Bit value 160 Output port Input port Address Initial value 000008H XXXXXXXXB 000018H 00000000B Output port The corresponding bit of PDR8 is set to 0. The The "L" level is corresponding output from bit of PDR8 is the pin. 0. 1 The pin is at the "H" level. The corresponding bit of PDR8 is set to 1. The The "H" level corresponding is output from bit of PDR8 is the pin. 1. 0 The corresponding bit of PDR8 is set to 0. The pin functions as an input port. 1 The corresponding bit of PDR8 is set to 1. The pin functions as an output port. 0 X: Undefined Input port Write mode The pin is at the "L" level. Port 8 data register (PDR8) Port 8 direction register (DDR8) Read mode 8.3 Port 8 8.3.2 Operation of Port 8 This section describes the operation of Port 8. ■ Operation of Port 8 ❍ When Port 8 is set as an output port in the Port 8 direction register (DDR8) • The value stored in the Port 8 data register (PDR8) is output to the Port 8 pins. • When the Port 8 data register (PDR8) is read, the value stored in PDR8 is output. ❍ When Port 8 is set as an input port in the Port 8 direction register (DDR8) • The Port 8 pins have high impedance. • When a value is set in the Port 8 data register (PDR8), the value is retained but is not output to the pin. • When the PDR8 register is read, the pin input level (0 for "L" or 1 for "H") is output. Note: If a read-modify-write instruction (such as the bit set instruction) is used to access the PDR8 register, none of the bits specified for output in the DDR8 register are affected. For a bit specified for input in the DDR8 register, however, the pin input level is written to the PDR8 register. Therefore, to change a bit specified for input to output, first write an output value to the PDR8 register and then specify the DDR8 register as an output port. ❍ Port operation after a reset • When the CPU is reset, the DDR8 and RDR8 registers are initialized to 00H and the Port 8 pins have high impedance. • The PDR8 register is not initialized when the CPU is reset. To use the PDR8 as an output port, first write an output value to the PDR8 register and then specify the DDR8 register as an output port. ❍ Port operation in stop or time-base timer mode When the port switches to stop mode or time-base timer mode while the pin status setting bit (SPL) of the low-power mode control register (LPMCR) is set to 1, the pins have high impedance regardless of the value in the Port 8 direction register (DDR8). Note that the input buffer is forcibly blocked off to prevent leakage due to an open circuit. 161 CHAPTER 8 I/O PORTS Table 8.3-4 States of the Port 8 Pins Pin name Normal operation P80 to P87 I/O port I/O port I/O port IC0 Trigger input for input capture 0 Trigger input for input capture 0 Trigger input for input capture 0 IC1 Trigger input for input capture 1 Trigger input for input capture 1 Trigger input for input capture 1 SI0 Serial data input 0 Serial data input 0 Serial data input 0 SC0 Serial clock I/O 0 Serial clock I/O 0 Serial clock I/O 0 SO0 Serial data output 0 Serial data output 0 Serial data output 0 SI1 Serial data input 1 Serial data input 1 Serial data input 1 SC1 Serial clock I/O 1 Serial clock I/O 1 Serial clock I/O 1 SO1 Serial data output 1 Serial data output 1 Serial data output 1 INT0, INT1 External interrupt request 0, 1 Sleep mode Stop mode or timebase timer mode (SPL = 0) External interrupt request 0, 1 External interrupt request 0, 1 Stop mode or time-base timer mode (SPL = 1, RDR = 0) Stop mode or time-base timer mode (SPL = 1, RDR = 1) Input blocking: Output at Hi-z Input blocking: Held at the "H" level Input blocking: Output held (Input is enabled when an external interrupt is enabled.) SPL: Pin status specification bit of the low-power mode control register (LPMCR:SPL) Hi-z: High impedance 162 Input blocking: Output at Hi-z (Input is enabled when an external interrupt is enabled.) 8.4 Port 9 8.4 Port 9 Port 9 is an I/O port that can also be used for resource I/O. Each of the port pins can be switched between a resource and an I/O port according to the value of the corresponding bit. This section describes the configuration and registers of Port 9 and provides a block diagram of the pins. The focus is on I/O ports. ■ Port 9 Configuration Port 9 consists of the following: • I/O port pins/resource I/O pins (P90, SDA, SO3 to P91, SCL, and SC3) • Port 9 data register (PDR9) • Port 9 direction register (DDR9) ■ Port 9 Pins The I/O pins of Port 9 also function as resource I/O pins. The I/O pins cannot be used as an I/O port when they are being used as resource I/O pins. Table 8.4-1 Port 9 Pins Port name I/O form Pin name Port function P90 P90 Port 9 P91 P91 I/O port Resource function SDA/SO3 I2C and serial I/O SCL/SC3 Input Output CMOS (hysteresis) Nch open drain Circuit type G Note: For the circuit type, see Section 1.7 "I/O Circuit Types." 163 CHAPTER 8 I/O PORTS ■ Block Diagram of the Port 9 Pins Internal data bus Figure 8.4-1 Block Diagram of the Port 9 Pins PDR9 read I/O check circuit PDR9 Output buffer PDR9 write DDR9 Port 9 pin Standby control (LPMCR:SPL = "1") ■ Port 9 Registers The Port 9 registers are the Port 9 data register (PDR9) and the Port 9 direction register (DDR9). The bits of each register correspond to the Port 9 pins on a one-to-one basis. Table 8.4-2 Port 9 Pins and Corresponding Register Bits Port name Register bits and corresponding port pins PDR9, DDR9 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 - - - - - - P91 P90 Port 9 Corresponding pin 164 8.4 Port 9 8.4.1 Port 9 Registers (PDR9 and DDR9) This section describes the Port 9 registers. ■ Functions of the Port 9 Registers ❍ Port 9 data register (PDR9) The PDR9 register specifies the output value for each Port 9 pin. ❍ Port 9 direction register (DDR9) The DDR9 register specifies the I/O direction for each Port 9 pin. A pin functions as an output port when the bit corresponding to the pin is set to 1. A pin functions as an input port when the bit corresponding to the pin is set to 0. Table 8.4-3 Functions of the Port 9 Registers Register name Bit value Input port Output port Write mode Input port The corresponding bit of PDR9 is set to 0. The The "L" level is corresponding output from bit of PDR9 is the pin. 0. 1 The pin is at the "H" level. The corresponding bit of PDR9 is set to 1. The corresponding bit of PDR9 is 1. 0 The corresponding bit of DDR9 is set to 0. 1 The corresponding bit of DDR9 is set to 1. Port 9 data register (PDR9) Address Initial value 000009H XXXXXXXXB 000019H 00000000B Output port The pin is at the "L" level. 0 Port 9 direction register (DDR9) Read mode Because of Nch open drain, pull-up is required to output the "H" level. Functions as an input port. Functions as an output port. X: Undefined 165 CHAPTER 8 I/O PORTS 8.4.2 Operation of Port 9 This section describes the operation of Port 9. ■ Operation of Port 9 ❍ When Port 9 is set as an output port in the Port 9 direction register (DDR9) • The value stored in the Port 9 data register (PDR9) is output to the Port 9 pins. • When Port 9 data register (PDR9) is read, the value stored in the PDR9 is output. ❍ When Port 9 is set as an input port in the Port 9 direction register (DDR9) • The Port 9 pins have high impedance. • When a value is set in the Port 9 data register (PDR9), the value is retained but is not output to the pin. • When the PDR9 register is read, the pin input level (0 for "L" or 1 for "H") is output. Note: If a read-modify-write instruction (such as the bit set instruction) is used to access the PDR9 register, none of the bits specified for output in the DDR9 register are affected. For a bit specified for input in the DDR9 register, however, the pin input level is written to the PDR9 register. Therefore, to change a bit specified for input to output, first write an output value to the PDR9 register and then specify the DDR9 register as an output port. ❍ Port operation after a reset 166 • When the CPU is reset, the DDR9 register is initialized to 00H and the Port 9 pins have high impedance. • The PDR9 register is not initialized when the CPU is reset. To use the Port 9 as an output port, first write an output value to the PDR9 register and then specify the DDR9 register as an output port. 8.4 Port 9 ❍ Port operation in stop or time-base timer mode When the port switches to stop mode or time-base timer mode while the pin status setting bit (SPL) of the low-power mode control register (LPMCR) is set to 1, the pins have high impedance regardless of the value in the Port 9 direction register (DDR9). Note that the input buffer is forcibly blocked off to prevent leakage due to an open circuit. Table 8.4-4 States of the Port 9 Pins Pin name Normal operation Sleep mode P90, P91 I/O port I/O port SDA/SO3 SCL/SC3 I2C and serial I/O I2C and serial I/O Stop mode or time-base timer mode (SPL = 0) Stop mode or time-base timer mode (SPL = 1) Input blocking: Output at Hi-z Input blocking: Held at the "H" level SPL: Pin status specification bit of the low-power mode control register (LPMCR:SPL) Hi-z: High impedance 167 CHAPTER 8 I/O PORTS 8.5 Port A Port A is an I/O port that can also be used for A/D converter analog input. Each of the port pins can be switched between analog input and an I/O port according to the value of the corresponding bit. This section describes the configuration and registers of Port A and provides a block diagram of the pins. The focus is on I/O ports. ■ Port A Configuration Port A consists of the following: • I/O port pins and A/D converter analog input pins (PA0, AN0, TMCK to PA7, and AN7) • Port A data register (PDRA) • Port A direction register (DDRA) • Analog input enable register 0 (ADER0) ■ Port A Pins The I/O pins of Port A are also used for A/D converter analog input. The I/O pins cannot be used as an I/O port when they are being used for A/D converter analog input. Conversely, the I/ O pins cannot be used for A/D converter analog input when they are being used as an I/O port. Table 8.5-1 Port A Pins Port name Port A I/O form Pin name Port function PA0/ AN0/ TMCK PA0 PA1/AN1 PA1 PA2/AN2 PA2 AN0 TMCK I/O port Output CMOS (hysteresis) CMOS F Analog input 0 Timing clock output AN1 Analog input 1 AN2 Analog input 2 AN3 Analog input 3 PA3/AN3 PA3 PA4/AN4 PA4 AN4 Analog input 4 PA5/AN5 PA5 AN5 Analog input 5 PA6/AN6 PA6 AN6 Analog input 6 PA7/AN7 PA7 AN7 Analog input 7 Note: For the circuit type, see Section 1.7 "I/O Circuit Types." 168 Input Circuit type Resource function 8.5 Port A ■ Block Diagram of the Port A Pins Figure 8.5-1 Block Diagram of the Port A Pins A/D converter analog input signal Internal data bus ADER0 PDRA read PDRA Input buffer I/O check circuit Output buffer PDRA write DDRA Port A pin Standby control (LPMCR:SPL = "1") Note: To use a port pin as an input port, set the corresponding bit of the Port A direction register (DDRA) to 0 and the corresponding bit of analog input enable register 0 (ADER0) to 0. To use a port pin as an analog input pin, set the corresponding bit of the Port A direction register (DDRA) to 0 and the corresponding bit of analog input enable register 0 (ADER0) to 1. ■ Port A Registers The Port A registers are the Port A data register (PDRA), the Port A direction register (DDRA), and analog input enable register 0 (ADER0). The bits of each register correspond to the Port A pins on a one-to-one basis. Table 8.5-2 Port A Pins and Corresponding Register Bits Port name Register bits and corresponding port pins PDRA, DDRA, ADER0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Corresponding pin PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port A 169 CHAPTER 8 I/O PORTS 8.5.1 Port A Registers (PDRA, DDRA and ADER0) This section describes the Port A registers. ■ Functions of the Port A Registers ❍ Port A data register (PDRA) The PDRA register specifies the output value for each Port A pin. ❍ Port A direction register (DDRA) The DDRA register specifies the I/O direction for each Port A pin. A pin functions as an output port when the bit corresponding to the pin is set to 1. A pin functions as an input port when the bit corresponding to the pin is set to 0. ❍ Analog input enable register 0 (ADER0) Each bit of the ADER0 register can be set as an I/O port or as analog input to the A/D converter. A pin is used for analog input when the bit corresponding to the port (pin) is set to 1, and is used as an I/O port when the bit is set to 0. Note: If a signal at an intermediate level is input when a pin is set as an I/O port, input leakage current flows. To use a pin for analog input, therefore, be sure to set the corresponding bit of the ADER0 register for analog input to the A/D converter. Reference: When reset, the DDRA register is initialized to 00H, the ADER0 register is initialized to FFH, and the A/D converter is set to analog input. 170 8.5 Port A Table 8.5-3 Functions of the Port A Registers Register name Bit value Output port Input port Address Initial value 00000AH XXXXXXXXB 00001AH 00000000B 00001EH 11111111B Output port The corresponding bit of PDRA is set to 0. The The "L" level is corresponding output from bit of PDRA is the pin. 0. 1 The pin is at the "H" level. The corresponding bit of PDRA is 1. The The "H" level corresponding is output from bit of PDRA is the pin. set to 1. 0 The corresponding bit of PDRA is set to 0. The pin functions as an input port. 1 The corresponding bit of PDRA is set to 1. The pin functions as an output port. 0 The corresponding bit of ADER0 is set to 0. I/O port 1 The corresponding bit of ADER0 is set to 1. A/D converter analog input 0 to 7 0 Analog input enable register 0 (ADER0) Input port Write mode The pin is at the "L" level. Port A data register (PDRA) Port A direction register (DDRA) Read mode X: Undefined 171 CHAPTER 8 I/O PORTS 8.5.2 Operation of Port A This section describes the operation of Port A. ■ Operation of Port A ❍ When Port A is set as an output port in the Port A direction register (DDRA) and analog input enable register 0 (ADER0) • The value stored in the Port A data register (PDRA) is output to the Port A pin. • When Port A data register (PDRA) is read, the value stored in PDRA is output. ❍ When Port A is set as an input port in the Port A direction register (DDRA) and analog input enable register 0 (ADER0) • The Port A pins have high impedance. • When a value is set in the Port A data register (PDRA), the value is retained but is not output to the pin. • When the PDRA register is read, the pin input level (0 for "L" or 1 for "H") is output. • If a read-modify-write instruction (such as the bit set instruction) is used to access the PDRA register, none of the bits specified for output in the DDRA register are affected. For a bit specified for input in the DDRA register, however, the pin input level is written to the PDRA register. Therefore, to change a bit specified for input to output, first write an output value to the PDRA register and then specify the DDRA register as an output port. ❍ When Port A is set for analog input to the A/D converter To use a port pin for analog input to the A/D converter, set the bit of analog input enable register 0 (ADER0) corresponding to the analog input pin to 1. When the corresponding PDRA bit is read while a pin is set for A/D converter analog input, 0 is read. ❍ Port operation after a reset When the CPU is reset, the DDRA register is initialized to 00H and the ADER0 register is initialized to FFH so that it can be used for analog input to the A/D converter. To use Port A as an I/O port, set the ADER0 register to 00H to set the port to port I/O mode. 172 8.5 Port A ❍ Port operation in stop or time-base timer mode When the port switches to stop mode or time-base timer mode while the pin status setting bit (SPL) of the low-power mode control register (LPMCR) is set to 1, the pins have high impedance regardless of the value in the Port A direction register (DDRA). Note that the input buffer is forcibly blocked off to prevent leakage due to an open circuit. Table 8.5-4 States of the Port A pins Pin name Normal operation Sleep mode PA0 to PA7 I/O port I/O port AN0 to AN7 Analog input of A/D converter 0 to 7 Analog input of A/D converter 0 to 7 Stop mode or time-base timer mode (SPL = 0) Stop mode or time-base timer mode (SPL = 1) Input blocking: Out held Input blocking: Output at Hi-z SPL: Pin status specification bit of low-power mode control register (LPMCR:SPL) Hi-z: High impedance 173 CHAPTER 8 I/O PORTS 8.6 Port B Port B is an I/O port that can also be used for A/D converter analog input, a serial interface, and external interrupt input. Each of the port pins can be switched between analog input and an I/O port according to the value of the corresponding bit. This section describes the configuration and registers of Port B and provides a block diagram of the pins. The focus is on I/O ports. ■ Port B Configuration Port B consists of the following: • I/O port pins, A/D converter analog input pins, and resource input pins (PB0, AN8 to PB7, AN15, and INT3) • Port B data register (PDRB) • Port B direction register (DDRB) • Analog input enable register 1 (ADER1) ■ Port B Pins The I/O pins of Port B are also used for A/D converter analog input and resource I/O. The I/O pins cannot be used as an I/O port when they are being used for A/D converter analog input or resource I/O. Conversely, the I/O pins cannot be used for A/D converter analog input or resource I/O when they are being used as an I/O port. Table 8.6-1 Port B Pins Port name Port B I/O form Pin name PB0 AN8 Analog input 8 PB1/AN9 PB1 AN9 Analog input 9 PB2/AN10 PB2 AN10 Analog input 10 PB3/ AN11/SI2 AN11 Analog input 11 PB3 PB4/ AN12/ SC2/TIN SI2 I/O port PB4 PB5 Input Output Circuit type CMOS (hysteresis) CMOS F Resource function PB0/AN8 PB5/ AN13/ SO2/TO 174 Port function Serial data input 2 AN12 Analog input 12 SC2 Serial clock output 2 TIN Reload timer input 1 AN13 Analog input 13 SO2 Serial data output 2 TO Reload timer output 1 8.6 Port B Table 8.6-1 Port B Pins (Continued) Port name I/O form Pin name PB6/ AN14/ INT2 Port function Output AN14 Analog input 14 INT2 External interrupt 2 CMOS (hysteresis) AN15 Analog input 15 CMOS F INT3 External interrupt 3 PB6 I/O port Port B PB7/ AN15/ INT3 Input Circuit type Resource function PB7 Note: For the circuit type, see Section 1.7 "I/O Circuit Types." ■ Block Diagram of the Port B Pins Figure 8.6-1 Block Diagram of the Port B Pins Resource input A/D converter analog input signal Internal data bus ADER1 PDRB read PDRB I/O check circuit PDRB write DDRB I/O control circuit Input buffer Output buffer Port B pin Standby control (LPMCR:SPL = "1") Resource output Note: To use a port pin as an input port, set the corresponding bit of the Port B direction register (DDRB) to 0 and the corresponding bit of analog input enable register 1 (ADER1) to 0. To use a port pin as an analog input pin, set the corresponding bit of the Port B direction register (DDRB) to 0 and the corresponding bit of analog input enable register 1 (ADER1) to 1. ■ Port B Registers The Port B registers are the Port B data register (PDRB), Port B direction register (DDRB), and analog input enable register 1 (ADER1). The bits of each register correspond to the Port B pins on a one-to-one basis. Table 8.6-2 Port B Pins and Corresponding Register Bits Port name Register bits and corresponding port pins PDRB, DDRB, DER1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Corresponding pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Port B 175 CHAPTER 8 I/O PORTS 8.6.1 Port B Registers (PDRB, DDRB and ADER1) This section describes the Port B registers. ■ Functions of the Port B Registers ❍ Port B data register (PDRB) The PDRB register specifies the output value for each Port B pin. ❍ Port B direction register (DDRB) The DDRB register specifies the I/O direction for each Port B pin. A pin functions as an output port when the bit corresponding to the pin is set to 1. A pin functions as an input port when the bit corresponding to the pin is set to 0. ❍ Analog input enable register 0 (ADER1) Each bit of the ADER1 register can be set as an I/O port or as analog input to the A/D converter. A pin is used for analog input when the bit corresponding to the port (pin) is set to 1, and is used as an I/O port when the bit is set to 0. Note: If a signal at an intermediate level is input when a pin is set as an I/O port, input leakage current flows. To use a pin for analog input, therefore, be sure to set the corresponding bit of the ADER1 register for analog input to the A/D converter. Reference: When reset, the DDRB register is initialized to 00H, the ADER1 register is initialized to FFH, and the A/D converter is set to analog input. 176 8.6 Port B Table 8.6-3 Functions of the Port B Registers Register name Bit value Output port Input port Address Initial value 00000BH XXXXXXXXB 00001BH 00000000B 00001FH 11111111B Output port The corresponding bit of PDRB is set to 0. The The "L" level is corresponding output from bit of PDRB is the pin. 0. 1 The pin is at the "H" level. The corresponding bit of PDRB is set to 1. The The "H" level corresponding is output from bit of PDRB is the pin. 1. 0 The corresponding bit of DDRB is set to 0. The pin functions as an input port. 1 The corresponding bit of DDRB is set to 1. The pin functions as an output port. 0 The corresponding bit of ADER1 is set to 0. I/O port 1 The corresponding bit of ADER1 is set to 1. 0 Analog input enable register 1 (ADER1) Input port Write mode The pin is at the "L" level. Port B data register (PDRB) Port B direction register (DDRB) Read mode A/D converter analog input X: Undefined 177 CHAPTER 8 I/O PORTS 8.6.2 Operation of Port B This section describes the operation of Port B. ■ Operation of Port B ❍ When Port B is set as an output port for the Port B direction register (DDRB) and analog input enable register 1 (ADER1) • The value stored in the Port B data register (PDRB) is output to the Port B pin. • When Port B data register (PDRB) is read, the value stored in PDRB is output. ❍ When Port B is set as an input port in the Port B direction register (DDRB) and analog input enable register 1 (ADER1) • The Port B pins have high impedance. • When a value is set in the Port B data register (PDRB), the value is retained but is not output to the pin. • When the PDRB register is read, the pin input level (0 for "L" or 1 for "H") is output. Note: If a read-modify-write instruction (such as the bit set instruction) is used to access the PDRB register, none of the bits specified for output in the DDRB register are affected. For a bit specified for input in the DDRB register, however, the pin input level is written to the PDRB register. Therefore, to change a bit specified for input to output, first write an output value to the PDRB register and then specify the DDRB register as an output port. ❍ When Port B is set for analog input to the A/D converter To use a port pin for analog input to the A/D converter, set the bit of analog input enable register 1 (ADER1) corresponding to the analog input pin to 1. When the corresponding PDRB bit is read while a pin is set for A/D converter analog input, 0 is read. ❍ Port operation after a reset When the CPU is reset, the DDRB register is initialized to 00H and the ADER1 register is initialized to FFH so that it can be used for analog input to the A/D converter. To use Port B as an I/O port, set the ADER1 register to 00H to set the port to port I/O mode. 178 8.6 Port B ❍ Port operation in stop or time-base timer mode When the port switches to stop mode or time-base timer mode while the pin status setting bit (SPL) of the low-power mode control register (LPMCR) is set to 1, the pins have high impedance regardless of the value in the Port B direction register (DDRB). Note that the input buffer is forcibly blocked off to prevent leakage due to an open circuit. Table 8.6-4 States of the Port B Pins Pin name Normal operation Sleep mode PB0 to PB7 I/O port I/O port AN8 to AN15 Analog input of A/ D converter 8 to 15 Analog input of A/ D converter 8 to 15 SI2 Serial data input 2 Serial data input 2 SC2 Serial clock I/O 2 Serial clock I/O 2 SO2 Serial data output 2 Serial data output 2 TIN Reload timer input 1 Reload timer input 1 TO Reload timer output 1 Reload timer output 1 INT2, INT3 External interrupt request 2, 3 External interrupt request 2, 3 Stop mode or time-base timer mode (SPL = 0) IInput blocking: Output held Input blocking: Output held (Input is enabled when an external interrupt is enabled.) Stop mode or time-base timer mode (SPL = 1) Input blocking: Output at Hi-z Input blocking: Output at Hi-z (Input is enabled when an external interrupt is enabled.) SPL: Pin status specification bit of low-power mode control register (LPMCR:SPL) Hi-z: High impedance 179 CHAPTER 8 I/O PORTS 8.7 Sample I/O Port Program This section provides a sample program that uses I/O ports. ■ Sample I/O Port Program ❍ Processing specifications • Ports 8 and A are used to turn on all segments of a seven-segment (eight-segment if the decimal point is included) LED. • Pin PA0 corresponds to the anode common pin of the LED, and pins P80 to P87 correspond to the segment pins. MB90M405 series PA0 P87 P86 P85 P84 P83 P82 P81 P80 ❍ Coding example PDR8 EQU 000008H PDRA EQU 00000AH DDR8 EQU 000018H DDRA EQU 00001AH ;-------- Main program ---------------------------------------------------------CODE CSEG START: ; Already initialized MOV I:PDRA, #00000000B ; Sets PA0 to the "L" level ; (#xxxxxxx0B) MOV I:DDRA, #11111111B ; Sets all port-A bits to output mode. MOV I:PDR8, #11111111B ; Sets all port-8 bits to 1. MOV I:DDR8, #11111111B ; Sets all port-8 bits to output mode. CODE ENDS ;-------------------------------------------------------------------------------END START 180 CHAPTER 9 SERIAL I/O This chapter describes the functions and operations of the serial I/O unit of the MB90M405 series. 9.1 "Overview of the Serial I/O Unit" 9.2 "Registers of the Serial I/O Unit" 9.3 "Serial I/O Prescaler (CDCR)" 9.4 "Operations of the Serial I/O Unit" 181 CHAPTER 9 SERIAL I/O 9.1 Overview of the Serial I/O Unit The serial I/O unit is a serial I/O interface that can transfer data in an 8-bit/2-channel configuration in clock synchronous mode. Moreover, selection between LSB-first and MSB-first transfer for data transfer is possible. ■ Overview of Serial I/O Unit The two types of serial I/O operating modes are as follows: ❍ Internal shift clock mode: Transfers data in synchronization with the internal clock (communication prescaler). ❍ External shift clock mode: Transfers data in synchronization with the clock input from an external pin (SC). In this mode, general-purpose ports that share the external pin (SC) can perform transfer operations using CPU instructions (based on the timing of execution of the port reversal instruction). ■ Block Diagram of the Serial I/O Unit Figure 9.1-1 Block Diagram of the Serial I/O Unit Internal data bus (MSB first) D0 to D7 D7 to D0 (LSB first) Bit direction select SI0,1 Read Write Serial data register (SDR) SO0,1 SC0,1 Control circuit Shift clock counter Internal clock (Serial I/O prescaler [CDCR]) 2 1 0 SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT MODE BDS Interrupt request Internal data bus 182 SOE SCOE 9.2 Registers of the Serial I/O Unit 9.2 Registers of the Serial I/O Unit The operations of the serial I/O unit can be specified using the following registers: • Serial mode control status register (SMCR), higher • Serial mode control status register (SMCR), lower • Serial shift data register (SDR) ■ Registers of the Serial I/O Unit Figure 9.2-1 Registers of the Serial I/O Unit bit 15 bit 8 bit 7 bit 0 Serial mode control status register (SMCR) Serial data register (SDR) 183 CHAPTER 9 SERIAL I/O 9.2.1 Serial Mode Control Status Register (SMCR) The serial mode control status register (SMCR) controls the operating mode for serial I/O transfer. ■ Serial Mode Control Status Register, Higher (SMCR) Figure 9.2-2 Serial Mode Control Status Register, Higher (SMCR) Bit 15 14 13 12 11 10 9 8 Initial value SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT R/W R/W R/W R/W R/W R 00000010B R/W R/W STRT Start bit 0 Stop of serial transfer 1 Start of serial transfer Stop bit STOP 0 Normal operation 1 Stop of transfer Transfer status bit BUSY 0 Stopped or serial data register R/W wait 1 Serial transfer Serial I/O interrupt request flag bit SIR Read No interrupt request exists. Clears an interrupt request. 1 An interrupt request exists. Does not affect operation. Serial I/O interrupt request enable bit SIE 0 Disables interrupt requests. 1 Enables interrupt requests. SMD2 SMD1 SMD0 184 Serial shift clock mode setting bit φ = 16MHz(div = 8) φ = 8MHz(div = 4) φ = 4MHz(div = 4) 0 0 0 1 MHz 1 MHz 500 KMHz 0 0 1 500 KMHz 0 1 0 125 KMHz 500 KMHz 125 KMHz 250 KMHz 62.5 KMHz 0 1 1 62.5 KMHz 62.5 KMHz 31.25 KMHz 1 0 0 31.25 KMHz 31.25 KMHz 15.625 KMHz 1 0 1 1 0 1 1 1 1 R/W : Read/write enabled R : Read only : Initial value φ : Machine clock frequency Write 0 External shift clock mode Reserved Reserved 9.2 Registers of the Serial I/O Unit Table 9.2-1 Functional Description of High Order Bits in Serial Mode Control Status Register (SMCR) No. Bit name Function • • bit15 to bit13 SMD2, SMD1, SMD0: Serial shift clock mode setting bits • • • • bit12 SIE: Serial I/O interrupt request enable bit • • • • • • bit11 • • • • • This bit is "1" while a serial transfer is being executed. A reset initializes this bit to "0". • • This bit forcibly stops serial transfer. Setting this bit to "1" puts serial transfer into the stopped state with STOP set to "1". A reset initializes this bit to "1". • • bit10 BUSY: Transfer status bit bit9 STOP: Stop bit • bit8 STRT: Start bit This bit enables serial I/O interrupt requests. When this bit is set to "1", setting the serial I/O interrupt request flag bit (SIR) to "1" outputs an interrupt request. A reset initializes this bit to "0". This is a flag bit for an interrupt request to the serial I/O. This bit is set to "1" when serial data transfer ends. While the serial I/O interrupt request enable bit (SIE) is "1", set this bit to "1" to output an interrupt request to the CPU. When the MODE bit is "0", set this bit to "0" to clear the interrupt request. When the MODE bit is "1", reading or writing the SDR register clears the interrupt flag bit to "0". Regardless of the value of the MODE bit, a reset or setting of the STOP bit to "1" clears the interrupt flag bit to "0". Setting this bit to "0" clears the interrupt flag bit to "0". Setting this bit to "1" does not affect operation. The read value is always "1". • SIR: Serial I/O interrupt request flag bit Selects a serial shift clock mode. The settings of the serial shift clock mode setting bits (SMD2, SMD1 and SMD0) and Communication Prescaler Control Register (CDCR0/ CDCR1) determine the transfer speed of the shift clock. A reset initializes these bits to 000B. Writing to these bits during transfer is prohibited (Do not write these bits). One of five internal shift clocks or an external shift clock can be specified. Do not set SMD2 to SMD0 to 110B or 111B because these settings are reserved. When SCOE is set to "0" for clock selection, shift operations manipulate ports that share the SC pin to allow shift operations for each instruction. • • • • • This bit starts serial transfer. Setting this bit to "1" in the stopped state starts transfer. Setting this bit to "1" during serial transfer or in the serial shift register R/W wait state causes the written value to be ignored. Setting this bit to "0" does not affect operation. The read value is always "0". 185 CHAPTER 9 SERIAL I/O ■ Serial Mode Control Status Register Lower (SMCR) Figure 9.2-3 Serial Mode Control Status Register Lower (SMCR) Bit SMCR 7 6 5 4 - - - - - - - - 3 2 MODE BDS R/W R/W 1 0 Initial value SOE SC0E XXXX0000B R/W R/W SC0E 0 Shift clock output enable bit I/O port pin 1 Serial data output SOE 0 Serial output enable bit I/O port pin 1 Shift clock output pin BDS 0 Bit direction selection bit LSB first (transfer from the least significant bit) 1 MSB first (transfer from the most significant bit) MODE 0 1 R/W 186 : Read/write enabled : Initial value Serial mode selection bit Started when STRT is "1" Started by read or write access to the serial data register (SDR) 9.2 Registers of the Serial I/O Unit Table 9.2-2 Functional Description of Lower Bits in Serial Mode Control Status Register (SMCR) No. bit7 to bit4 bit3 bit2 Bit name -: Undefined bit MODE: Serial mode selection bit BDS: Bit direction selection bit Function • • The read value is undefined. Setting this bit does not affect the transfer operation. • Use this bit to select the condition for resuming operation from the stopped state. If this bit is "0", starting is performed by setting STRT to "1". If this bit is "1", reading or writing the serial data register (SDR) starts the transfer operation. Rewriting this bit during transfer is prohibited. A reset initializes this bit to "0". Set this bit to "1" to start the extended intelligent I/O service. • • • • • • • • • • bit1 SOE: Serial output enable bit • • • • bit0 SCOE: Shift clock output enable bit • • • • This bit selects the serial data transfer direction. If this bit is "0", data is transferred starting with the least significant bit (LSB first). If this bit is "1", data is transferred starting with the most significant bit (MSB first). Set the BDS bit before writing data to the SDR register. This bit controls the output of the serial I/O output external pins (SO2 and SO3). If this bit is "0", the pin serves as the I/O port pin. If this bit is "1", the pin serves as the serial data output pin. A reset initializes this bit to "0". This bit controls the output of the shift clock I/O external pins (SC2 and SC3). If this bit is "0", the pin serves as the I/O port pin. If this bit is "1", the pin serves as the serial data output pin. Set this bit to "0" to perform transfer for each instruction in external shift clock mode. A reset initializes this bit to "0". 187 CHAPTER 9 SERIAL I/O 9.2.2 Serial Shift Data Register (SDR) The serial shift data register (SDR) retains serial I/O transfer data. Writing to and reading the SDR is prohibited during transfer. ■ Serial Shift Data Register (SDR) Figure 9.2-4 Serial Shift Data Register (SDR) Bit 188 7 6 5 4 3 2 1 0 Initial value D7 D6 D5 D4 D3 D2 D1 D0 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W 9.3 Communication Prescaler Control Register (CDCR0/CDCR1) 9.3 Communication Prescaler Control Register (CDCR0/ CDCR1) The Communication Prescaler Control Register (CDCR0/CDCR1) provides a serial I/O shift clock. The operation clock for serial I/O operation can be obtained by dividing the output of the machine clock. The serial I/O unit is designed to obtain a fixed baud rate for each of the machine clocks in the system. The Communication Prescaler Control Register (CDCR0/CDCR1) controls division of the machine clock. ■ Communication Prescaler Control Register (CDCR0/CDCR1) 15 14 13 12 11 MD - - - R/W R/W R/W R/W Bit 10 9 8 Initial value Reserved DIV2 DIV1 DIV0 0XXX0000B R/W R/W R/W R/W Table 9.3-1 Functional Description of Bits in Communication Prescaler Control Register (CDCR0/ CDCR1) No. Bit name Function bit15 MD: Communication prescaler operation enable bit • • • Use this bit to enable operation of the communication prescaler. If this bit is set to "1", the communication prescaler is enabled. If this bit is set to "0", the communication prescaler is disabled. bit14 bit13 bit12 -: Undefined bit • • The read value is undefined. The value of this bit does not affect operation. bit11 Reserved: Reserved bit • Be sure to set this bit to "0". bit10 bit9 bit8 DIV2 to DIV0: Division ratio setting bit • • Use this bit to set the division ratio of the machine clock. For information on the setting values, see Table 9.3-2 "Communication Prescaler." 189 CHAPTER 9 SERIAL I/O Table 9.3-2 Machine Clock Division Ratio MD DIV2 DIV1 DIV0 div 0 - - - Stopped 1 0 0 0 1 1 0 0 1 2 1 0 1 0 3 1 0 1 1 4 1 1 0 0 5 1 1 0 1 6 1 1 1 0 7 1 1 1 1 8 div: Machine clock division ratio Note: If the division ratio has been changed, wait one cycle of the divide-by-two machine clock for clock stabilization before performing transfer. The CDCR0 is a prescaler for the serial I/O channel 2 (also serve as the UART channel 0). The CDCR1 is a prescaler for the serial I/O channel 3 (also serve as the UART channel 1). 190 9.4 Operation of the Serial I/O Unit 9.4 Operation of the Serial I/O Unit The serial I/O unit consists of the serial mode control status register (SMCR) and the shift data register (SDR). The serial I/O unit is used to input and output 8-bit serial data. ■ Operation of the Serial I/O Unit The following explains how serial data is input and output. The contents of the shift data register are output to the serial output pin (SO pin) in bit serial mode in synchronization with a falling edge of the serial shift clock (external or internal clock). Data is input from the serial input pin (SI pin) in bit serial mode in synchronization with a rising edge of the clock. The shift direction (transfer from the MSB or LSB) can be selected using the bit direction bit (BDS) in the serial mode control status register lower (SMCR). When transfer ends, the serial I/O unit enters the stopped state or data register R/W wait state according to the setting of the serial mode selection bit (MODE) in the serial mode control status register lower (SMCR). To enter the transfer state from the various states, do the following: • To return from the stopped state, set the stop bit (STOP) to "0" and the start bit (STRT) to "0" (The settings for STOP and STRT can be made simultaneously). • To return from the serial data register (SDR) wait state, read or write the data register. 191 CHAPTER 9 SERIAL I/O 9.4.1 Shift Clock The shift clock operates in two modes: internal shift clock mode and external shift clock mode. A mode can be specified in the serial mode control status register (SMCR). Switch the mode while the serial I/O unit is stopped. Check for the stopped state by reading the transfer status bit (BUSY). ■ Internal Shift Clock Mode In internal shift clock mode, the shift clock with a 50% duty cycle can be supplied for synchronous timing output from the SC pin. One-bit data is transferred for each clock. Calculate the transfer rate as follows: transfer-rate (s) = div × A machine-clock-frequency (Hz) A, the divide factor specified in the serial shift clock mode setting bits (SMD0 to SMD2), is 2, 4, 16, or 32. ■ External Shift Clock Mode In external shift clock mode, one-bit data is transferred for each clock in synchronization with the external shift clock that is input from the SC pin. A transfer rate up to 1/5 machine cycles is available. For example, a transfer rate up to 2 MHz is available when one machine cycle is 0.1 μs. Data can also be transferred for each instruction. Transfer data for each instruction as follows: 1. Select the external shift clock mode and set the shift clock output enable bit (SCOE) in the serial mode control status register (SMCR) to "0". 2. Then, set the direction register for one of the ports that share the ISC pin to "1" to set the port to output mode. After making the above settings, set the port data register (PDR) to "1" and then "0". The port value that is output to the SC pin is then fetched as the external clock and data is transferred. Start the shift clock at the "H" level. Note: Writing to the serial mode control register (SMCR) and the serial shift data register (SDR) is prohibited during serial I/O operation. 192 9.4 Operation of the Serial I/O Unit 9.4.2 Operating States of the Serial I/O Unit The serial I/O unit operates in the following four states: • STOP state • Stopped state • R/W wait state of the SDR register • Transfer state ■ STOP State When a reset occurs or the stop bit (STOP) in the serial mode control status register (SMCR) is set to "1", the shift counter is initialized and SIR is set to "0". Have the serial I/O unit return from the STOP state by setting STOP to "0" and STRT to "1" (the settings for these bits can be made simultaneously). No transfer operation occurs when the stop bit (STOP) is set to "1" and the start bit (STRT) is set to "1" because STOP has a higher priority than STRT. ■ Stopped State While the serial mode selection bit (MODE) is set to "0", BUSY is set to "0" and SIR is set to "1" in the serial mode control status register (SMCR) at the end of transfer. After that, the counter is initialized and the serial I/O enters the stopped state. Set STRT to "1" to have the serial I/O unit return from the stopped state and resume transfer. ■ R/W Wait State of the Serial Data Register While the serial mode selection bit (MODE) is set to "1", BUSY is set to "0" and SIR is set to "1" in the serial mode control status register (SMCR) at the end of serial transfer. After that, the serial I/O unit enters the SDR register R/W wait state. If the setting in the interrupt enable register is Enabled, this block outputs an interrupt signal. To have the serial I/O unit return from the R/W wait state and resume transfer, read or write the SDR register to set BUSY to "1". 193 CHAPTER 9 SERIAL I/O ■ Transfer State While BUSY is set to "1", the serial I/O unit is transferring serial data. Depending on the setting of the serial mode selection bit (MODE), the serial I/O enters either the stopped or the R/W wait state. Figure 9.4-1 State Transition Diagram of Serial I/O Operation Reset End of transfer STOP = "0" & STRT = "0" STRT = "0", BUSY = "0" MODE = "0" MODE = "0" STOP = "0" & & STOP = "0" & STRT = "1" END Transfer operation STRT = "1", BUSY = "1" STOP STOP = "1" STOP = "1" STRT = "0", BUSY = "0" STOP = "0" & STRT = "1" MODE = "1" & End & STOP = "1" STOP = "1" Serial data register R/W wait R/W of SDR & MODE = "1" STRT = "1", BUSY = "0" MODE = "1" Serial data Figure 9.4-2 Concept of Reading from and Writing to the Serial Data Register SO0,SO1 Data bus Read Write SI0,SO1 Interrupt output Serial I/O interface Data bus Read Write CPU Interrupt input Interrupt controller Data bus 1. When MODE is set to "1", transfer is completed according to the shift clock counter. Then, SIR is set to "1" and the serial I/O enters the read/write wait state. When the serial I/O interrupt enable bit (SIE) is set to "1", an interrupt signal is generated. However, no interrupt signal is generated if SIE is inactive or transfer is interrupted by setting of the stop bit (STOP) to "1". 2. When the serial shift data register (SDR) is read or written, the interrupt request is cleared and serial transfer is resumed. 194 9.4 Operation of the Serial I/O Unit 9.4.3 Start/Stop Timing of Shift Operation To start the shift operation, set the stop bit (STOP) to "0" and the start bit (STRT) to "1" in the serial mode control status register (SMCR). The shift operation stops if STOP is set to "1" or when transfer terminates. • Stop by setting STOP to "1": The shift operation stops while SIR remains at "0" regardless of the value the serial mode selection bit (MODE) is set to. • Stop at the end of transfer: The shift operation stops after SIR is set to "1" regardless of the value the serial mode selection bit (MODE) is set to. The transfer status bit (BUSY) is set to "1" in serial transfer state or "0" in stopped or R/W wait state regardless of the value the serial mode selection bit (MODE) is set to. To check the transfer state, read the BUSY bit. ■ Start/Stop Timing of Shift Operation ❍ Internal shift clock mode (LSB first) Figure 9.4-3 Timing of Shift Operation (Internal Clock) SC0,SC1 STRT "1" is output. (Start of transfer) (End of transfer) When MODE is "0" BUSY SO0,SO1 DO0 DO7 (Data is retained.) ❍ Internal shift clock mode (LSB first) Figure 9.4-4 Timing of Shift Operation (External Clock) SC0,SC1 STRT (Start of transfer) (End of transfer) When MODE is "0" BUSY SO0,SO1 DO0 DO7 (Data is retained.) 195 CHAPTER 9 SERIAL I/O ❍ When shift operation is performed in accordance with instructions in external shift clock mode (LSB first) Figure 9.4-5 Timing of Shift Operation (When a Shift Operation Is Performed in Accordance with Instructions in External Shift Clock Mode) The SC bit in PDR is "0". SC0,SC1 The SC bit in PDR is "0". The SC bit in PDR is "1" (End of transfer). STRT When MODE is "0" BUSY SO0,SO1 DO6 DO7 (Data is retained.) ❍ Stop by setting STOP to "1" (LSB first, internal clock mode) Figure 9.4-6 Stop Timing When the Stop Bit (STOP) Is Set to "1" SC0,SC1 "1" is output. (Start of transfer) STRT (End of transfer) When MODE is "0" BUSY STOP SO0,SO1 DO3 DO4 DO5 (Data is retained.) Note: DO7 to DO0 represent output data. ■ Serial Data I/O Timings During serial data transfer, data is output from the serial output pin (SO) on a falling edge of the shift clock and data is input from the serial input pin (SI) on a rising or falling edge (determined beforehand). Figure 9.4-7 Timing of Serial Data I/O Shift LSB first (when the BDS bit is "0") SC0,SC1 SI0,SI1 SI input DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DO3 DO4 DO5 DO6 DO7 SO output SO0,SO1 DO0 DO1 DO2 MSB first (when the BDS bit is "1") SC0,SC1 SI input SI0,SI1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO4 DO3 DO2 DO1 DO0 SO output SO0,SO1 196 DO7 DO6 DO5 9.4 Operation of the Serial I/O Unit 9.4.4 Interrupt Function of the Serial I/O Unit The serial I/O unit can output interrupt requests to the CPU. If, at the end of data transfer, the serial I/O interrupt request flag bit (SIR), which is an interrupt flag, is set to "1" and the serial I/O interrupt enable bit (SIE) in the serial mode control status register (SMCR) is set to "1", the serial I/O outputs an interrupt request to the CPU. ■ Interrupt Function of the Serial I/O Unit Figure 9.4-8 Timing of Serial I/O Interrupt Signal Output SC0,SC1 (End of transfer) BUSY * When Mode is "1" SIE = '1' SIR RD/WR of SDR SO0,SO1 DO6 DO7 (Data is retained.) 197 CHAPTER 9 SERIAL I/O 198 CHAPTER 10 TIMEBASE TIMER This chapter describes the functions and operation of the timebase timer of the MB90M405 series. 10.1 "Overview of the Timebase Timer" 10.2 "Configuration of the Timebase Timer" 10.3 "Timebase Timer Control Register (TBTC)" 10.4 "Timebase Timer Interrupts" 10.5 "Operation of the Timebase Timer" 10.6 "Usage Notes on the Timebase Timer" 199 CHAPTER 10 TIMEBASE TIMER 10.1 Overview of the Timebase Timer The timebase timer is an 18-bit free-running counter that counts up in synchronization with the main clock. The timer has two functions: An interval timer function that can select one of four intervals and a function for supplying clocks to the oscillation stabilization interval timer and the watchdog timer. ■ Interval Timer Function The interval timer function repeatedly generates an interrupt request at a given interval. • An interrupt request is generated when the interval timer bit for the timebase counter overflows. • The interval timer bit (interval) can be selected from four types. Table 10.1-1 Intervals for the Timebase Timer Main clock cycle Interval cycle 212/HCLK (Approx. 0.97 ms) 214/HCLK (Approx. 3.90 ms) 2/HCLK (0.5 µs) 216/HCLK (Approx. 15.62 ms) 219/HCLK (Approx. 125.00 ms) HCLK: Oscillation clock frequency Values in parentheses are for a 4.194 MHz oscillation clock. ■ Clock Supply Function The clock supply function supplies clocks to the oscillation settling time timer and to some peripheral functions. Table 10.1-2 Clock Cycle Time Supplied from the Timebase Timer Clock destination Clock cycle time 213/HCLK (Approx. 1.95 ms) Oscillation setting time Remarks Oscillation settling time for ceramic vibrator 215/HCLK (Approx. 7.81 ms) 218/HCLK (Approx. 62.50 ms) Oscillation settling time for crystal vibrator 212/HCLK (Approx. 0.97 ms) 214/HCLK (Approx. 3.90 ms) Watchdog timer 216/HCLK (Approx. 15.62 ms) Count-up clock for watchdog timer 219/HCLK (Approx. 125.00 ms) HCLK: Oscillation clock frequency Values in parentheses occurs during operation of the 4.194 MHz oscillation clock. 200 10.1 Overview of the Timebase Timer Reference: The oscillation settling time is the yardstick because the oscillation cycle time is unstable as soon as oscillation starts. 201 CHAPTER 10 TIMEBASE TIMER 10.2 Configuration of the Timebase Timer The timebase timer consists of the following four blocks: • Timebase timer counter • Counter clear circuit • Interval timer selector • Timebase timer control register (TBTC) ■ Block Diagram of the Timebase Timer Figure 10.2-1 Block Diagram of the Timebase Timer To the watchdog timer To the PPG timer Timebase timer counter x21 x22 x23 Main clock x28 x29 x210 x211 x212 x213 x214 x215 x216 x217 x218 OF OF OF OF To the oscillation settling time selector in the clock control section Power-on reset Stop mode start CKSCR:MCS="1" "0" (*1) Counter clear circuit Interval timer selector TBOF set TBOF clear Timebase timer control register RESV (TBTC) TBIE TBOF TBR TBC1 TBC0 Timebase timer interrupt signal #34 (22H) (*2) - : Undefined bit OF : Overflow *1 Switching of the machine clock from the oscillation clock to the PLL clock *2 Interrupt number ❍ Timebase timer counter An 18-bit up counter that uses the main clock as the count clock ❍ Counter clear circuit Clears the timebase timer counter by setting the timebase timer initialization bit (TBR) of the timebase timer control register (TBTC) to "0", performing a power-on reset, sending the CPU into stop mode (LPMCR: STP = "1"), and changing the machine clock from the main clock to the PLL clock (CKSCR: MCS = "1" -> "0"). ❍ Interval timer selector Selects one of four outputs of the timebase timer counter. An overflow of the selected bit becomes an interrupt cause. 202 10.2 Configuration of the Timebase Timer ❍ Timebase timer control register (TBTC) Selects the interval, clears the timebase timer counter, controls an interrupt request, and checks the status. 203 CHAPTER 10 TIMEBASE TIMER 10.3 Timebase Timer Control Register (TBTC) The timebase timer control register (TBTC) selects the interval, clears the timebase timer counter, controls an interrupt request, and checks the status. ■ Timebase Timer Control Register (TBTC) Figure 10.3-1 Timebase Timer Control Register (TBTC) Bit 15 14 13 RESV R/W 12 11 10 9 8 TBIE TBOF TBR TBC1 TBC0 - - R/W R/W W R/W Initial value 1XX00100B R/W TBC1 TBC0 Interval selection bit 0 0 212/HCLK (Approx. 0.97 ms) 0 1 214/HCLK (Approx. 3.90 ms) 1 0 216/HCLK (Approx. 15.62 ms) 219/HCLK (Approx. 125.00 ms) Values in parentheses are for a 4.194 MHz oscillation clock. 1 TBR 1 Timebase timer initialization bit 0 Clearing of the timebase timer counter and an interrupt request 1 No effect on operation TBOF Interrupt request flag bit During reading During writing 0 No interrupt request made Clearing of an interrupt request 1 Interrupt request made TBIE No effect on operation Interrupt request enable bit 0 Interrupt request output disabled 1 Interrupt request output enabled Reserved bit Be sure to write 1 to this bit. RESV R/W W X - : : : : : HCLK : 204 Read/write Write only Undefined Not used Initial value Oscillation clock frequency 10.3 Timebase Timer Control Register (TBTC) Table 10.3-1 Function Description of Each Bit in the Timebase Timer Control Register (TBTC) Bit name Function bit15 RESV: Reserved bit • Be sure to write 1 to this bit. bit14 bit13 Not used • • When read, the value is undefined. Writing has no effect on operation. bit12 TBIE: Interrupt request enable bit • • This bit enables interrupt requests. When this bit and the interrupt request flag bit (TBOF) are 1, an interrupt request is output. bit11 TBOF: Interrupt request flag bit • • bit10 TBR: Timebase timer initialization bit • • Used to clear the timebase timer counter. When this bit is set to "0", the timebase timer counter is cleared to 00000H and the interrupt request flag bit (TBOF) is cleared to "0". • Writing 1 does not affect operation. [Reference] The read value is always 1. bit9 bit8 TBC1, TBC0: Interval selection bit • • • TBOF is a flag bit for an interrupt request. This bit is set to "1" when the interval timer bit selected for the timebase timer counter overflows. • When the interrupt request enable bit (TBIE) is set to "1", an interrupt request is output. • Set this bit to "0" to clear an interrupt request. • When this bit is set to "1", there is no effect on operation. Note: • To set this bit to "0", set the interrupt request enable bit (TBIE) or the interrupt level mask register (ILM) of the processor status (PS) to Disabled. • This bit is cleared to "0" when a transition to stop mode occurs, the timebase timer is cleared due to the timebase timer initialization bit (TBR), or a reset occurs. Used to select an interval timer cycle. The bit for the interval timer of the timebase timer counter is specified. Four types of interval can be selected. 205 CHAPTER 10 TIMEBASE TIMER 10.4 Timebase Timer Interrupts The timebase timer can output an interrupt request when an overflow of the interval counter selected with the interval time setting bit occurs (interval timer function). ■ Timebase Timer Interrupts The interrupt request flag bit (TBOF) of the timebase timer control register (TBTC) is set to "1" when the timebase timer counter counts up on the main clock and an overflow of the specified interval timer occurs. If the TBOF bit is set to "1" while the interrupt request enable bit is set to Enabled (TBTC:TBIE="1"), an interrupt request (interrupt number #34) is output to the CPU and the interrupt processing routine is executed. In the interrupt processing routine, set the TBOF bit to "0" to clear the interrupt request. When the specified interval timer bit overflows, the TBOF bit is set to "1" regardless of the value in the TBIE bit. Reference: • The timebase timer cannot use the extended intelligent I/O service (EI2OS). ■ Timebase Timer Interrupts and EI2OS Table 10.4-1 Timebase Interrupts and EI2OS Interrupt level setting register Vector table address Interrupt number #33 (21H) x: Not available 206 Register name Address Lower Upper Bank ICR11 0000BBH FFFF78H FFFF79H FFFF7AH EI2OS x 10.5 Operation of the Timebase Timer 10.5 Operation of the Timebase Timer This section describes the operation of the interval timer function, the oscillation stabilization interval timer function, and the clock supply function. ■ Operation of the Interval Timer Function (Timebase Timer) The interval timer function generates an interrupt request for each interval The stabilization in Figure 10.5-1 "Stabilization of the Timebase Timer" is required to all the timer to operate as an interval timer. Figure 10.5-1 Setting of the Timebase Timer Bit TBTC 15 14 13 RESV 1 12 11 10 9 8 TBIE TBOF TBR TBC1 TBC0 - - 0 0 : Used 0 : Set 0. 1 : Set 0. - : Undefined bit • The timebase timer continues counting up as long as the clock oscillates. • If the timebase timer counter is cleared (TBTC: TBR = "0"), the counter counts up from "000000000000000000B". When the specified interval timer bit overflows, the interrupt request flag bit (TBOF) of the timebase timer control register (TBTC) is set to "1". If the overflow occurs while the interrupt request enable bit is set to Enabled (TBIE = "1"), interrupt requests are output at every specified interval based on the time when the counter was cleared. • The interval may become longer than the time set because of timebase timer clearing. ■ Oscillation Stabilization Wait Time Timer Function The timebase timer is also used as the oscillation time timer for oscillation and the PLL clocks. The timebase timer is also used for the oscillation stabilization interval of the oscillation clock and the PLL clock. The timebase timer counts up the oscillation stabilization interval since it has the value "000000000000000000B" (counter cleared) and until it detects the oscillation stabilization interval. When the timebase timer returns from timebase timer mode to PLL clock mode, the oscillation stabilization interval indicates only the portion from the middle of counting because the timebase timer counter has not been cleared. 207 CHAPTER 10 TIMEBASE TIMER Table 10.5-1 Timebase Timer Counter Clearing and Oscillation Stabilization Wait Time Operation Counter clear TBOF clear Oscillation Stabilization Wait Time TBTC: Writing of 0 to TBR O O - Power-on reset O O Watchdog reset O O O O Transition from oscillation clock mode to PLL clock mode (MCS = 1 to 0) O O Releasing of timebase timer mode X X Releasing of sleep mode X X Releasing of stop mode Oscillation clock oscillation stabilization wait time Oscillation clock oscillation stabilization wait time (at return to main clock mode) PLL clock oscillation stabilization wait time PLL clock oscillation stabilization wait time (at return to PLL clock mode) - O: Available X: Not available ■ Clock Supply Function The timebase timer supplies clocks to the watchdog timer. Clearing of the timebase counter affects operation of the watchdog timer. For more information, see Section 10.6 "Usage Notes on the Timebase Timer". 208 10.5 Operation of the Timebase Timer ■ Timebase Timer Operation Statuses Figure 10.5-2 "Timebase Timer Operations" shows the following operation statuses. • When a power-on reset occurs • When the CPU enters sleep mode while the interval timer function is operating • When the CPU enters stop mode • When the timebase timer counter clear request is issued When the CPU enters stop mode, the timebase timer counter is cleared and the timebase timer counter stops. To release stop mode, use the timebase timer counter to count the oscillation stabilization interval. Figure 10.5-2 Timebase Timer Operations Counter value 3FFFFH Cleared by transition to stop mode Oscillation stabilization interval bit overflow 00000H Power-on reset (optional) Interval cycle CPU (TBTC:TBC1,TBC0="11B") operation started Cleared by an interrupt processing routine Counter cleared (TBTC:TBR="0") TBOF bit TBIE bit Sleep SLP bit (LPMCR register) Sleep released by an interval interrupt Stop STP bit (LPMCR register) Stop released by an external interrupt If the interval time setting bits of the timebase timer control register (TBC: TBC, TBC0) is set to "11B" (219/HCLK) HCLK : Oscillation stabilization interval : Oscillation clock frequency 209 CHAPTER 10 TIMEBASE TIMER 10.6 Usage Notes on the Timebase Timer This section provides notes on how clearing of an interrupt request or clearing of the timebase timer counter affects the functions. ■ Timebase Timer Usage Notes ❍ Clearing interrupt requests Clear the interrupt request flag bit (TBOF) of the timebase timer control register (TBTC) to "0" while the interrupt request enable bit (TBIE) or the interrupt level mask register (ILM) of the processor status (PS) is set to disabled. ❍ Functions affected by clearing of the timebase timer counter • Interval timer function (interval interrupt) • When the watchdog timer is being used • Clock output circuit ❍ Use of the timebase timer as the oscillation settling time timer In stop mode in which the operating clock stops, the timebase timer counter is cleared and stopped. When the timebase timer counter is cleared, the clock supplied from it starts to be supplied again from the initial state. As a result, the H level may be shortened or the L level may be prolonged by half a cycle at the maximum. Although the clock for the watchdog timer also starts to be supplied again from the initial state, the watchdog timer operates in normal cycles because the watchdog timer counter is cleared at the same time. ❍ Notes on peripheral functions to which clocks are supplied from the timebase timer At power-on or in stop mode, the source oscillation is stopped. Thus, the timebase timer counter places the oscillation stabilization interval for the operating clock using the clock supplied from the oscillator. Depending on the oscillator type, an appropriate oscillation stabilization interval must be specified. For more information, see Section 4.5 "Oscillation Stabilization Wait Time". 210 CHAPTER 11 WATCHDOG TIMER This chapter describes the functions and operations of the watchdog timer of the MB90M405 series. 11.1 "Overview of the Watchdog Timer" 11.2 "Configuration of the Watchdog Timer" 11.3 "Watchdog Timer Control Register (WDTC)" 11.4 "Operation of the Watchdog Timer" 11.5 "Usage Notes on the Watchdog Timer" 211 CHAPTER 11 WATCHDOG TIMER 11.1 Overview of the Watchdog Timer The watchdog timer is a 2-bit counter that uses the output of the timebase timer as the count clock. After the watchdog timer is activated, the CPU is reset within a specified interval unless the watchdog timer is cleared. ■ Watchdog Timer Function The watchdog timer is provided to detect whether a program is running out of control. The watchdog timer, once activated, must continue to be cleared within every specified interval. If the program results in an endless loop and the watchdog timer is not cleared within the minimum time shown in Table 11.1-1 "Intervals for the Watchdog Timer" a watchdog reset is issued to the CPU, sending it into the reset status. Specify the watchdog timer interval in the interval setting bits (WT1, WT0) of the watchdog timer control register (WDTC). Table 11.1-1 Intervals for the Watchdog Timer Interval WT1 WT0 Minimum (*1) Maximum (*1) Oscillation clock cycle count 0 0 Approx. 3.58 ms Approx. 4.61 ms 214 211 cycle 0 1 Approx. 14.33 ms Approx. 18.3 ms 216 213 cycle 1 0 Approx. 57.23 ms Approx. 73.73 ms 218 215 cycle 1 1 Approx. 458.75 ms Approx. 589.82 ms 221 218 cycle *1: Value during operation of the 4.19 MHz oscillation clock For more information on a watchdog timer interval, see Section 11.4 "Operation of the Watchdog Timer". Reference: The watchdog timer, after being activated, can be stopped using a power-on reset or a reset from the watchdog timer. The watchdog timer can be cleared with an external reset, an internal reset, writing to the watchdog control bit (WTE) of the watchdog timer control register (WDTC), or transition to sleep or stop mode. However, the watchdog function is enabled and not stopped. Note: The watchdog counter consists of a 2-bit counter that uses the carry signals of the timebase timer as count clocks. Since the watchdog timer uses a carry signal of the timebase timer, the watchdog reset interval time may become longer than the specified time if the timebase timer is cleared. 212 11.2 Configuration of the Watchdog Timer 11.2 Configuration of the Watchdog Timer The watchdog timer consists of the following blocks: • Count clock selector • Watchdog timer (2-bit counter) • Watchdog reset generator • Counter clear control circuit • Watchdog timer control register (WDTC) ■ Block Diagram of the Watchdog Timer Figure 11.2-1 Block Diagram of the Watchdog Timer Watchdog timer control register (WDTC) PONR WRST ERST SRST WTE Watchdog timer WT1 WT0 2 Activation with CLR Start of sleep mode Start of hold status mode Start of stop mode Counter clear control circuit Count clock selector 2-bit counter Clear Overflow Watchdog reset generator To the internal reset generator Clear 4 Clear (Timebase timer counter) Main clock x21 x22 x28 x29 x210 x211 x212 x213 x214 x215 x216 x217 x218 - : Undefined bit ❍ Count clock selector Used to select one of the four timebase timer output clocks as the count clock of the watchdog timer. Setting the count clock of the watchdog timer determines a watchdog reset interval. ❍ Watchdog counter (2-bit counter) The watchdog timer is a 2-bit timer that counts the clock specified by the count clock selector. ❍ Watchdog reset generator Used to generate the reset signal by an overflow of the watchdog counter. ❍ Counter clear circuit Used to clear the watchdog counter and to control the operation or stopping of the counter. 213 CHAPTER 11 WATCHDOG TIMER ❍ Watchdog timer control register (WDTC) Used to set the interval, activate and clear the watchdog timer, and hold the reset generation cause. 214 11.3 Watchdog Timer Control Register (WDTC) 11.3 Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) is used to set an interval time, start the watchdog timer, clear a setting, and indicate a reset generation cause. ■ Watchdog Timer Control Register (WDTC) Figure 11.3-1 Watchdog Timer Control Register (WDTC) Bit WDTC 7 6 4 3 2 WRST ERST SRST WTE PONR R 5 - R R R WT1 WT0 0 0 0 1 1 1 0 1 1 0 WT1 WT0 W W W 1 XXXXX111B Interval selection bit (for 4.19 MHz HCLK) Interval Oscillation clock cycle count Maximum Minimum Approx. 3.58ms 214 211 cycle Approx. 18.3ms 16 2 213 cycle Approx. 73.73ms 218 215 cycle 21 218 cycle Approx. 4.61ms Approx. 14.33ms Approx. 57.23ms Approx. 458.75ms Approx. 589.82ms WTE 0 Initial value Watchdog control bit - Activation of the watchdog timer (At first write after reset) - Clearing of the watchdog timer (At second or subsequent write after reset) No operation Reset cause bit Reset cause PONR WRST ERST SRST R W X - : : : : : * : HCLK : 2 1 X X X Power-on * * * 1 * Watchdog timer * * 1 * * * 1 Software reset (LPMCR: RST) External reset (RST pin input) Read only Write only Undefined Undefined bit Initial value Retains the previous status. Oscillation clock frequency 215 CHAPTER 11 WATCHDOG TIMER Table 11.3-1 Function Description of Each Bit of the Watchdog Timer Control Register (WDTC) Bit name Function • bit7 bit5 bit4 bit3 PONR, WRST, ERST, SRST: Reset cause bits • • • bit6 bit2 -: Undefined bit WTE: Watchdog timer control bit • • The value of this bit is not defined if it is read. The set value does not affect the operation. • The watchdog timer is activated when this bit is set to "0" in the first write operation after a power-on reset or a reset from the watchdog timer. The watchdog timer is cleared when this bit is set to "0" in write operations after the first after a power-on reset or a reset from the watchdog timer. Writing 1 does not affect operation. • • bit1 bit0 WT1, WT0: Interval selection bit • • • 216 Read-only bits for indicating the reset cause. If more than one reset cause occurs, the bit for each reset cause occurring is set to 1. These bits are all cleared to 0 after the watchdog timer control register (WDTC) is read. A power-on reset sets the reset cause flag bit PONR to "1" and sets the reset cause flag bits WRST, ERST, and SRST to an undefined value. If the PONR bit is set to "1", the contents of the WRST, ERST, and SRST bits should be ignored. Used to select the watchdog timer interval. Data in these bits is valid when the watchdog timer is activated. Data can be written to this bit and the watchdog control bit (WTE) at the same time. Data written to these bits after the watchdog timer is activated is invalid. These bits are write-only. 11.4 Operation of the Watchdog Timer 11.4 Operation of the Watchdog Timer The watchdog timer generates a watchdog reset by an overflow of the watchdog counter. ■ Watchdog Timer Operation Figure 11.4-1 Setting of the Watchdog Timer Bit WDTC 7 PONR 6 5 4 3 2 1 0 WRST ERST SRST WTE WT1 WT0 0 : Used 0 : Set 0. ❍ Activating the watchdog timer • To activate the watchdog timer, set the watchdog control bit (WTE) of the watchdog timer control register (WDTC) to "0" for the first time after a reset from the watchdog timer is generated after a power-on reset. The interval can be set in the interval setting bits (WT1, WT0) of the watchdog timer control register (WDTC). • The watchdog timer, after being activated, can be stopped using a power-on reset or a reset from the watchdog timer. The watchdog timer cannot be stopped by an external reset, a software reset, writing to the watchdog control bit (WTE) of the watchdog timer control register (WDTC), or transition to sleep or timebase timer mode. ❍ Clearing the watchdog timer • To clear the watchdog timer, set the watchdog control bit (WTE) of the watchdog timer control register (WDTC) to "0". • The watchdog timer can be cleared also by input of an external reset or an internal reset or transition to sleep mode. • Transition to timebase timer mode clears and stops the watchdog timer. ❍ Intervals for the watchdog timer Figure 11.4-2 "Clear Timing and Watchdog Timer Intervals" shows the relationship between the clear timing of the watchdog timer and intervals. ❍ Checking a reset cause A reset cause can be determined by checking the PONR, WRST, ERST, and SRST bits of the watchdog timer control register (WDTC) after a reset. 217 CHAPTER 11 WATCHDOG TIMER Figure 11.4-2 Clear Timing and Watchdog Timer Intervals [WDG timer block diagram] 2-bit counter Clock selector a WTE bit Divide-bytwo circuit Count enable output circuit b Divide-bytwo circuit c Reset circuit d Reset signal Count enabling and clearing [Minimum interval] When the WTE bit is cleared immediately before the count clock rises: Count start Counter clearing Count clock a Divide-by-two value b Divide-by-two value c Count enabling Reset signal d 7 x (count clock cycle/2) WTE bit clearing Watchdog reset generation [Maximum interval] When the WTE bit is cleared immediately after the count clock rises: Count start Counter clearing Count clock a Divide-by-two value b Divide-by-two value c Count enabling Reset signal 9 x (count clock cycle/2) WTE bit clearing 218 Watchdog reset generation 11.5 Usage Notes on the Watchdog Timer 11.5 Usage Notes on the Watchdog Timer Notes on using the watchdog timer are given below. ■ Usage Notes on the Watchdog Timer ❍ Stopping the watchdog timer Once the watchdog timer is activated, it cannot stop until a power-on or watchdog reset occurs. ❍ Interval setting The interval setting becomes valid when the watchdog timer is activated. The interval setting is ignored unless the watchdog timer is activated. ❍ Interval time The interval time of the watchdog timer may become longer than the specified value when the timebase timer is cleared because a carry signal of the timebase timer is used as the count clock. ❍ Notes on program creation If the watchdog timer is repetitiously cleared in a program, the processing time of the program including the interrupt processing must be equal to or less than the minimum interval. ❍ Watchdog timer operation in timebase timer mode In timebase timer mode, the watchdog timer is cleared and stopped. The watchdog timer is restarted when the CPU returns from timebase timer mode to main clock mode or PLL clock mode. 219 CHAPTER 11 WATCHDOG TIMER 220 CHAPTER 12 16-BIT RELOAD TIMER This chapter describes the functions and operations of the 16-bit reload timer of the MB90M405 series. 12.1 "Overview of the 16-Bit Reload Timer" 12.2 "Configuration of the 16-Bit Reload Timer" 12.3 "16-Bit Reload Timer Pins" 12.4 "16-Bit Reload Timer Registers" 12.5 "16-Bit Reload Timer Interrupts" 12.6 "Operation of the 16-Bit Reload Timer" 12.7 "Usage Notes on the 16-Bit Reload Timer" 221 CHAPTER 12 16-BIT RELOAD TIMER 12.1 Overview of the 16-Bit Reload Timer The MB90M405 series has three 16-bit reload timer channels. The following clock modes and the following counter operation modes can be specified. Clock modes • Internal clock mode: The timer counts down in synchronization with the internal clock. • Event count mode: The timer counts down in synchronization with the external input pulse. Counter operation modes • Reload mode: The timer repeats counting by reloading the count setting value. • One-shot mode: The timer stops counting when an underflow occurs. ■ 16-bit reload timer operating modes Table 12.1-1 16-Bit Reload Timer Operating Modes Clock mode Internal clock mode Event count mode (external clock mode) Counter operation Reload mode Operation of 16-bit reload timer One-shot mode Software trigger operation External trigger operation External gate input operation Reload mode Software trigger operation One-shot mode ■ Internal Clock Mode The 16-bit reload timer is in internal clock mode if the count clock setting bits (CSL1, CSL0) of the timer control status register (TMCSR) are set to "00B", "01B", or "10B". For internal clock mode, select one of the following three operations: ❍ Software trigger operation Counting starts when the software trigger bit (TRG) is set to "1" while the count enable bit (CNTE) of the TMCSR register is set to "1". ❍ External trigger operation Counting starts when a valid edge (rising, falling, or both edges) of trigger input specified in the operation mode setting bits (MOD2, MOD1, and MOD0) is input to the TIN pins while the CNTE bit of the TMCSR register is set to "1". ❍ External gate input operation Counting continues while a valid level of gate input ("L" or "H") specified in the operation mode setting bits (MOD2, MOD1, and MOD0) is input to the TIN pins while the CNTE bit of the TMCSR register is set to "1". 222 12.1 Overview of the 16-Bit Reload Timer ■ Event Count Mode (External Clock Mode) The 16-bit reload timer is in event count mode (external clock) if the count clock setting bits (CSL1, CSL0) of the timer control status register (TMCSR) are set to "11B". Counting starts when a valid edge (rising, falling, or both edges) of trigger input specified in the operation mode setting bits (MOD2, MOD1, and MOD0) is input to the TIN pins while the CNTE bit is set to "1". The 16-bit reload timer can also be used as an interval timer if external clock is input periodically. ■ Counter Operation ❍ Reload mode Counting starts when an underflow of the 16-bit down counter (change from "0000H" to "FFFFH") loads the values of the 16-bit reload register (TMRLR) into the 16-bit down counter. Since the 16-bit reload timer causes an interrupt request to occur for an underflow condition, it can be used as an interval timer. Every time an underflow occurs, a reversed toggle waveform can be output from the T0 pin. Table 12.1-2 Intervals for the 16-Bit Reload Timer Count clock Internal clock External clock Count clock period Interval 21/φ (0.125 μs) 0.125 μs to 8.192 ms 23/φ (0.5 μs) 0.5 μs to 32.768 ms 25/φ (2.0 μs) 2.0 μs to 131.1 ms 23/φ or more (0.5 μs) 0.5 μs or more φ : Machine clock Values in parentheses are for a 16 MHz machine clock. ❍ Single-shot mode An underflow of the 16-bit down counter (change from "0000H" to "FFFFH") stops counting. Reference: • 16-bit reload timer 0 can be used to create the baud rate of UART. • 16-bit reload timer 1 can be used to provide a start trigger of the A/D converter. 223 CHAPTER 12 16-BIT RELOAD TIMER ■ 16-Bit Reload Timer Interrupts and EI2OS An underflow of the 16-bit down counter (change from "0000H" to "FFFFH") outputs an interrupt request. Table 12.1-3 16-Bit Reload Timer Interrupts and EI2OS Channel 16-bit reload timer 0 Interrupt number #23 (17H) 16-bit reload timer 1 #24 (18H) 16-bit reload timer 2 #21 (15H) Interrupt control register Register name Address ICR06 0000B6H ICR05 0000B5H Vector table address EI2OS Lower Upper Bank FFFFA0H FFFFA1H FFFFA2H FFFF9CH FFFF9DH FFFF9EH FFFFA8H FFFFA9H FFFFAAH : Usable when an interrupt cause that shares the ICR is not used. 224 12.2 Configuration of the 16-Bit Reload Timer 12.2 Configuration of the 16-Bit Reload Timer Each of the 16-bit reload timers 0 to 2 consists of the following blocks: • Count clock generation circuit • Reload control circuit • Output control circuit • Operation control circuit • 16-bit timer register (TMR) • 16-bit reload register (TMRLR) • Timer control status register (TMCSR) ■ Block Diagram of the 16-Bit Reload Timer Figure 12.2-1 Block Diagram of the 16-Bit Reload Timer Internal data bus TMRLR 16-bit reload register Reload signal Reload control circuit TMR 16-bit timer register (down counter) UF CLK Count clock generation circuit Machine clock φ Prescaler 3 Gate input Valid clock judgment circuit Clear Pin Input control circuit Wait signal To UART *1 To A/D converter *2 CLK Output control circuit Internal clock Clock selector Output signal generation circuit Invert Pin EN External clock 3 2 Select signal Function selection Operation control circuit CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG Timer control status register (TMCSR) *1 Channel 0 *2 Channel 1 Interrupt request signal 225 CHAPTER 12 16-BIT RELOAD TIMER ❍ Count clock generation circuit This circuit generates the count clock for the 16-bit reload timer from the machine clock or external input clock. ❍ Reload control circuit This circuit controls starting of the 16-bit down counter and, if an underflow (change from 0000H to FFFFH) is detected, the load operation for loading a value into the 16-bit down counter. ❍ Output control circuit This circuit controls the inversion of the TO pin output through an underflow of the 16-bit down counter (change from "0000H" to "FFFFH") and enabling and disabling of TO pin output. ❍ Operation control circuit This circuit controls activation and stop of the 16-bit down counter. ❍ 16-bit timer register (TMR) This register is a 16-bit down counter. The current counter value is read from this register during a read operation. ❍ 16-bit reload register (TMRLR) This register stores a value to be loaded to the 16-bit down counter. The setting value of this register is loaded to the 16-bit down counter, which then starts counting down. ❍ Timer control status register (TMCSR) This register selects the operation mode of the 16-bit reload timer, the count clock, and the operating conditions, enables and disables counting, controls interrupts, and checks the statuses of interrupt requests. 226 12.3 16-Bit Reload Timer Pins 12.3 16-Bit Reload Timer Pins This section describes the pins of the 16-bit reload timer and provides a pin block diagram. ■ 16-Bit Reload Timer Pins The pins of the 16-bit reload timer are shared with the general-purpose ports. Table 12.3-1 16-Bit Reload Timer Pins Pin name Pin function PB4/TIN0 Port B input-output/ timer input PB5/TO0 I/O format Port B input-output/ timer output CMOS output/ CMOS hysteresis input Pull-up option Standby control Settings required for pins Setting for the input port (DDRB: bit12=0) Not available Available Setting for timer output enable (TMCR0:OUTE=1) ■ Block Diagram of the 16-Bit Reload Timer Pins Figure 12.3-1 Block Diagram of the 16-Bit Reload Timer Pins Internal data bus Resource input PDR read PDR I/O decision circuit Input buffer Output buffer PDR write DDR Port pin Standby control (LPMCR: SPL = "1") I/O control circuit Resource output 227 CHAPTER 12 16-BIT RELOAD TIMER 12.4 16-Bit Reload Timer Registers The 16-bit reload timer registers are as follows. ■ 16-Bit Reload Timer Registers Figure 12.4-1 16-Bit Reload Timer Registers bit 15 bit 8 bit 7 bit 0 Timer control status register (TMCSR) 16-bit timer register/16-bit reload register (TMR/TMRLR) (*1) *1 This register functions as a 16-bit timer register (TMR) during reading, and functions as a 16-bit reload register (TMRLR) during writing. 228 12.4 16-Bit Reload Timer Registers 12.4.1 Timer Control Status Register, Higher (TMCSR) The timer control status register (TMCSR) is used to select the operating mode and the count clock of the 16-bit reload timer. ■ Timer Control Status Register, Higher (TMCSR) Figure 12.4-2 Timer Control Status Register, Higher (TMCSR) Bit 15 14 13 12 11 10 9 8 7 CSL1 CSL0 MOD2 MOD1 MOD0 - - - Initial value XXXX00000 B R/W R/W R/W R/W R/W - MOD2 MOD1 MOD0 0 0 0 0 0 1 0 1 0 0 1 1 1 X 0 1 X 1 MOD2 MOD1 MOD0 Operating mode selection bit (in the internal clock mode) Input terminal function Valid edge, level Trigger inhibit - Trigger input Falling edge Rising edge Both edges Gate input Operating mode selection bit (in the event count mode) Input terminal function X 0 0 X 0 1 X 1 0 X 1 1 CSL1 CSL0 0 0 0 1 1 0 1 1 "L" level "H" level Valid edge - - Rising edge Trigger input Falling edge Both edges Count clock selection bit Function Count clock 21/ φ (0.125 μs) Internal clock mode 23/ φ (0.5 μs) 25/ φ (2.0 μs) Event count mode External event input R/W : Read/write : Undefined bit X : Indefinite : Initial value φ : Machine clock, the value in the parentheses ( ) indicates the value when the machine clock is operated at 16MHz. 229 CHAPTER 12 16-BIT RELOAD TIMER Table 12.4-1 Function Description of Each Bit of the Higher of the Timer Control Status Register (TMCSR) Bit name Function bit15 bit14 bit13 bit12 Not used Undefined bit • • When these bits are read, their values are undefined. Writing to these bits has no effect on operation. bit11 bit10 CSL1, CSL0: Count clock selection bits • • These bits select the count clock of the 16-bit reload timer. When these bits are set to "00B", "01B", and "10B", internal clock mode is selected. When these bits are set to 11B, event count mode is set. • bit9 bit8 bit7 230 MOD2, MOD1, MOD0: Operating mode selection bits • These bits select operation mode. In internal clock mode: • The MOD2 bit is used to select input pin functions. • When the MOD2 bit is set to "0", the input pin is used as a trigger input pin. Whenever a valid edge is input, the value in the 16-bit reload register (TMRLR) is loaded into the counter and counting starts. The MOD1 and MOD0 bits select the type of valid edge. • When the MOD2 bit is set to "1", the input pin becomes a gate. Counting continues as long as a valid level specified in the MOD0 bit is input. • The value specified in the MOD1 bit has no effect on operation. In event count mode: • The MOD2 bit is not affected. • In event count mode, the input pin becomes a trigger input pin. Counting starts when a valid edge specified in the MOD1 and MOD0 bits is input. 12.4 16-Bit Reload Timer Registers 12.4.2 Timer Control Status Register, Lower (TMCSR) The timer control status register (TMCSR) is used to set the operating conditions of the 16-bit reload timer, enable and disable counting, control interrupts, and check the status of interrupt requests. ■ Timer Control Status Register, Lower (TMCSR) Figure 12.4-3 Timer Control Status Register, Lower (TMCSR) Bit 7 6 5 4 3 * MOD0 OUTE OUTL RELD INTE 2 1 UF 0 Initial value CNTE TRG 00000000B R/W R/W R/W R/W R/W R/W R/W R/W TRG Software trigger bit 0 No change, no effect on other bits 1 Counting starts after data loading Count enable bit CNTE 0 Counting stopped 1 Counting enabled (wait for the start trigger)) UF Underflow interrupt request flag bit During writing During reading 0 No interrupt request issued Clearing the interrupt request 1 Interrupt request issued No effect on operation INTE Underflow interrupt request enable bit 0 Interrupt request output disabled 1 Interrupt request output enabled RELD Reload selection bit 0 One-shot mode (reload disabled) 1 Reload mode (reload enabled) Pin output level selection bit OUTL In single-shot mode (RELD="0") In reload mode (RELD="1") 0 Square wave of H during counting Toggle output of L when counting is started. 1 Square wave of L during counting Toggle output of H when counting is started. OUTE 0 Pin functions I/O port Timer output enable bit Registers and pins corresponding to each channel TMCR PB5 TO0 Timer output 1 R/W : Read/write : Initial value * : See Section 12.4.1, "Timer Control Status Register, Higher (TMCSR)," for MOD0 (bit 7) 231 CHAPTER 12 16-BIT RELOAD TIMER Table 12.4-2 Function Description of Each Bit of the Lower of the Timer Control StatusRegister (TMCSR) Bit name Function bit6 OUTE: Timer output enable bit • • This bit enables or disables output to the timer output pin. When this bit is set to "0", the pin serves as an I/O port. When this bit is set to "1", the pin serves as a timer output pin. bit5 OUTL: Pin output level setting bit • • This bit selects the output level of the timer output pin. The timer output pin outputs a toggle waveform in reload mode or a square wave indicating that counting is in progress in one-shot mode. Opposite output levels are output from the pin depending on whether this bit is set to "0" or "1". • bit4 RELD: Reload selection bit • • • This bit enables reloading. When this bit is set to "1", the timer is in reload mode. When an underflow of the 16-bit down counter occurs, the value stored in the 16-bit reload register is loaded into the 16-bit down counter and counting continues. When this bit is set to "0", the timer is in one-shot mode. When an underflow of the 16-bit down counter occurs, counting stops. bit3 INTE: Underflow interrupt request enable bit • • This bit enables interrupt requests. When this bit and the interrupt request flag (UF) bit are 1, the timer outputs an interrupt request. bit2 UF: Underflow interrupt request flag bit • • • This is a flag bit for an interrupt request. This bit is set to "1" when an underflow of the 16-bit down counter occurs. An interrupt request is output when this bit is set to "1" while the underflow interrupt request enable bit (INTE) is set to "1". Setting this bit to "0" clears an interrupt request. Setting this bit to "1" has no effect on operation. This bit is also cleared when EI2OS is activated. • • • bit1 CNTE: Count enable bit • • • bit0 TRG: Software trigger bit • • • • 232 This bit enables or disables counting. When this bit is set to "1", the counter is placed in trigger standby mode. Counting starts when the software trigger bit (TRG) is set to "1" or a valid edge (rising, falling, or both edges) of trigger input specified in the operation mode setting bits (MOD2, MOD1, and MOD0) is input to the TIN pins. When this bit is set to "0", counting stops. This bit starts the interval timer function or counter function with software. When this bit is set to "1" while the count enable bit (CNTE) is set to "1", the value stored in the 16-bit reload register is loaded into the 16-bit down counter and counting starts. When this bit is set to "0", there is no effect on operation. The read value is "0". 12.4 16-Bit Reload Timer Registers 12.4.3 16-bit Timer Register (TMR) The 16-bit timer register (TMR) is always able to read the count value from the 16-bit down counter. ■ 16-bi t Timer Register (TMR) Figure 12.4-4 16-Bit Timer Register (TMR) Bit Bit 9 8 Initial value D9 D8 XXXXXXXX B R R R 3 2 1 0 Initial value D4 D3 D2 D1 D0 XXXXXXXX B R R R R R 15 14 13 12 11 D15 D14 D13 D12 R R R R R 7 6 5 4 D7 D6 D5 R R R 10 D11 D10 R: Read only X: Undefined The 16-bit timer register is a 16-bit down counter. When the software trigger bit (TRG) is set to "1" while the count enable bit (CNTE) of the timer control status register (TMCSR) is set to "1" or a valid edge (rising, falling, or both edges) of trigger input specified in the operation mode setting bits (MOD2, MOD1, and MOD0) is input to the TIN pins, the values stored in the 16-bit reload register (TMRLR) are loaded into the 16-bit down counter and counting starts. This register holds the value of the 16-bit timer register (TMR) while counting is stopped (TMCSR: CNTE = "0"). Notes: • Be sure to use a word transfer instruction (MOVW A, 003AH) to read data from the 16-bit timer register (TMR). • Although 16-bit timer register (TMR) is read-only and the 16-bit reload register (TMRLR) is write-only, they are placed at the same address. Thus, writing a value to the 16-bit timer register has no effect on this register because the value is written to the 16-bit reload register. 233 CHAPTER 12 16-BIT RELOAD TIMER 12.4.4 16-bit Reload Register (TMRLR) The 16-bit reload register (TMRLR) sets a reload value in the 16-bit down counter. The value written to this register is loaded into the down counter, and the value is counted down. ■ 16-Bit Reload Register (TMRLR) Figure 12.4-5 16-Bit Reload Register (TMRLR) Bit Bit 15 14 13 12 11 10 9 8 Initial value D15 D14 D13 D12 D11 D10 D9 D8 XXXXXXXX B W W W W W W W W 7 6 5 4 3 2 1 0 Initial value D7 D6 D5 D4 D3 D2 D1 D0 XXXXXXXX B W W W W W W W W W: Write only X: Undefined When a value is written to the 16-bit reload register (TMRLR), counting must be stopped (TMCSR:CNTE="0") regardless of the operating mode of the 16-bit reload register. While the count enable bit (CNTE) of the timer control status register (TMCSR) is set to "1", a value stored in the 16-bit reload register is loaded into the 16-bit down counter and countdown starts in one of two cases: the software trigger bit (TRG) is set to "1" or a valid edge (rising, falling, or both edges) of the trigger input specified in the operation mode setting bits (MOD2, MOD1, and MOD0) is input to the TIN pins. In reload mode, when an underflow of the 16-bit down counter occurs (change from "0000H" to "FFFFH"), a value stored in the 16-bit reload register (TMRLR) is loaded into the 16-bit down counter and countdown continues. In one-shot mode, when an underflow of the 16-bit down counter occurs, the 16-bit down counter stops at the value "FFFFH". Notes: 234 • Counting must be stopped (TMCSR: CNTE = "0") when a value is written to the 16-bit reload register (TMRLR). • Use a word transfer instruction (MOVW 003AH, A) to write a value to the 16-bit reload register (TMRLR). • Although the 16-bit reload register (TMRLR) is write-only and the 16-bit timer register (TMR) is read-only, they are placed at the same address. Since different values are written to, and read from these registers, none of the INC/DEC and other instructions that result in readmodify-write (RMW) operations can be used. 12.5 16-Bit Reload Timer Interrupts 12.5 16-Bit Reload Timer Interrupts The 16-bit reload timer outputs an interrupt request when an underflow of the 16-bit down counter occurs. The 16-bit reload timer also supports the extended intelligent I/ O service (EI2OS). ■ 16-Bit Reload Timer Interrupts Table 12.5-1 Interrupt Control Bits and Interrupt Causes of the 16-Bit Reload Timer 16-bit reload timer 0 16-bit reload timer 1 Interrupt request flag bit TMCSR0: UF TMCSR1: UF Interrupt request enable bit TMCSR0: INTE TMCSR1: INTE Interrupt cause Underflow of the 16-bit down counter (TMR0) Underflow of the 16-bit down counter (TMR1) In the 16-bit reload timer, the underflow interrupt request flag bit (UF) of the timer control status register (TMCSR) is set to "1" when an underflow of the 16-bit down counter occurs (change from "0000H" to "FFFFH"). If, at this time, the underflow interrupt request enable bit is set to Enabled (TMSCR: INTE = "1"), an interrupt request is output. ■ 16-Bit Reload Timer Interrupts and EI2OS Table 12.5-2 16-Bit Reload Timer Interrupts and EI2OS Channel 16-bit reload timer 0 Interrupt number #23 (17H) 16-bit reload timer 1 #24 (18H) 16-bit reload timer 2 #21 (15H) Interrupt control register Register name Address ICR06 0000B6H ICR05 0000B5H Vector table address EI2OS Lower Upper Bank FFFFA0H FFFFA1H FFFFA2H FFFF9CH FFFF9DH FFFF9EH FFFFA8H FFFFA9H FFFFAAH : Usable when an interrupt cause that shares the ICR is not used. ■ EI2OS Function of the 16-Bit Reload Timer The 16-bit reload timer allows the use of the extended intelligent I/O service (EI2OS) when an underflow of the 16-bit down counter occurs (change from "0000H" to "FFFFH"). 235 CHAPTER 12 16-BIT RELOAD TIMER 12.6 Operation of the 16-Bit Reload Timer This section describes the 16-bit reload timer settings and counter operating status. ■ 16-Bit Reload Timer Settings ❍ Internal clock mode setting The setting shown in Figure 12.6-1 "Internal Clock Mode Setting" is required to operate this timer as an interval timer. Figure 12.6-1 Internal Clock Mode Setting Bit 15 14 13 12 TMCSR 11 10 9 8 7 6 5 4 3 2 1 0 CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG 1 Other than 11 Set the initial value (reload value) of the counter. TMRL : Used 1 : Set 1. ❍ Event counter mode setting he setting shown in Figure 12.6-2 "Event Counter Mode Setting" is required to operate this timer as an event counter. Figure 12.6-2 Event Counter Mode Setting Bit TMCSR 15 14 13 12 11 1 TMRL 10 9 7 6 5 4 3 2 1 Set the initial value (reload value) of the counter. DDRB : Used 1 : Set 1 : Set the corresponding to the pin used to 0. 236 8 1 0 CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG 1 12.6 Operation of the 16-Bit Reload Timer ■ Counter Operating Status The 16-bit down counter status is determined by the count enable bit (CNTE) values of the timer control status register (TMCSR) and the internal trigger wait signal value (WAIT). Figure 12.6-3 "Counter Status Transition" shows the relationship between the count enable bit (CNTE) values and the internal trigger wait signal (WAIT) values in the stop status (STOP status), trigger wait status (WAIT status), and running status (RUN status) Figure 12.6-3 Counter Status Transition CNTE = "0", WAIT = "1" STOP TIN: Input disabled TO: I/O port Reset Counter: The counter value is retained when the counter stops. Immediately after a reset, it is undefined. CNTE = "0" CNTE = "1" TRG = "0" CNTE = "1" TRG = "1" CNTE = "1", WAIT = "1" WAIT TIN: Only trigger input enabled TO: Output initial value Counter: The counter value is retained when the counter stops. Immediately after a reset, it is undefined and remains so until a value is loaded. TRG = "1" (Software trigger) External trigger from TIN WAIT TRG CNTE UF RELD : : : : : : : CNTE = "0" RUN CNTE = "1", WAIT = "0" TIN: Functions as TIN UF = "1" RELD = "0" (Single-shot mode) TO: Functions as TO Counter: Run UF = "1" RELD = "1" (Reload mode) LOAD CNTE = "1", WAIT = "0" The value of the 16-bit reload register is loaded into the 16-bit down counter. TRG = "1" (Software trigger) Loading ends. State transition by hardware State transition by register access Wait signal (internal signal) Software trigger bit of timer control status register (TMCSR) Count enable bit of timer control status register (TMCSR) Underflow interrupt request flag bit of timer control status register (TMCSR) Reload selection bit of timer control status register (TMCSR) 237 CHAPTER 12 16-BIT RELOAD TIMER 12.6.1 Internal Clock Mode (Reload Mode) The 16-bit reload timer count downs the 16-bit down counter in synchronization with the internal count clock and outputs an interrupt request when an underflow occurs (change from "0000H" to "FFFFH"). It can also output a toggle waveform from the timer output pin. ■ Operation in Internal Clock Mode (Reload Mode) While the count enable bit (CNTE) of the timer control status register (TMCSR) is set to "1", a value stored in the 16-bit reload register (TMRLR) is loaded into the 16-bit down counter, and then countdown starts in one of the following cases: the software trigger bit (TRG) is set to "1", or a valid edge (rising, falling, or both edges) of the trigger input specified in the operation mode setting bits (MOD2, MOD1, and MOD0) is input to the TIN pins. When the CNTE bit and the software trigger bit are set to "1" simultaneously, countdown starts as soon as counting is enabled. When an underflow of the 16-bit down counter occurs (change from "0000H" to "FFFFH"), a value stored in the 16-bit reload register (TMRLR) is loaded into the 16-bit down counter and countdown continues. An interrupt request is output to the CPU when an underflow of the 16-bit down counter occurs while the underflow interrupt request flag bit (UF) of the timer control status register (TMCSR) is "1" and the underflow interrupt request enable bit (INTE) is "1". The timer can also output from the TO pin a toggle waveform, which is inverted for each underflow. ❍ Software trigger operation Counting starts when the software trigger bit (TRG) is set to "1" while the count enable bit (CNTE) of the timer control status register (TMCSR) is set to "1". Figure 12.6-4 Count Operation in Reload Mode (Software Trigger Operation) Count clock Counter -1 0000H Reload data Data load signal -1 0000H Reload data UF bit CNTE bit TRG bit TO pin T* T: Machine cycle (one cycle of the machine clock) * It takes 1T time from trigger input to loading of the reload data. 238 -1 0000H Reload data -1 Reload data 12.6 Operation of the 16-Bit Reload Timer ❍ External trigger operation Counting starts when a valid edge (rising, falling, or both edges) of trigger input specified in the operation mode setting bits (MOD2, MOD1, and MOD0) is input to the TIN pins while the count enable bit (CNTE) of the timer control status register (TMCSR) is set to "1". Figure 12.6-5 Count Operation in Reload Mode (External Trigger Operation) Count clock Counter -1 -1 0000H Reload data Data load signal -1 0000H Reload data 0000H Reload data -1 Reload data UF bit CNTE bit TIN pin 2T to 2.5T* TO pin T: Machine cycle (one cycle of the machine clock) * It takes 2T to 2.5T time from external trigger input to loading of the reload data. Note: Specify 2/φ (φ : machine clock frequency) or more for the width of a trigger pulse to be input to the TIN pin. ❍ Gate input operation Counting starts when the software trigger bit (TRG) is set to "1" while the count enable bit (CNTE) of the timer control status register (TMCSR) is set to "1". Counting continues while a valid level of gate input ("L" or "H") specified in the operation mode setting bits (MOD2, MOD1, and MOD0) is input to the TIN pin. Figure 12.6-6 Count Operation in Reload Mode (Software Trigger, Gate Input Operation) Count clock Counter Reload data -1 -1 -1 0000H -1 -1 Reload data Data load signal UF bit CNTE bit TRG bit TIN pin T* TO pin T: Machine cycle (one cycle of the machine clock) * It takes 1T time from trigger input to loading of the reload data. Note: Specify 2/φ (φ : machine clock frequency) or more for the width of a gate input pulse to be input to the TIN pin. 239 CHAPTER 12 16-BIT RELOAD TIMER 12.6.2 Internal Clock Mode (Single-shot Mode) The 16-bit reload timer count downs the 16-bit down counter in synchronization with the internal count clock and outputs an interrupt request when an underflow occurs (change from "0000H" to "FFFFH"). It can also output a square waveform from the T0 pin. ■ Internal Clock Mode (Single-Shot Mode) When the software trigger bit (TRG) is set to "1" while the count enable bit (CNTE) of the timer control status register (TMCSR) is set to "1" or a valid edge (rising, falling, or both edges) of trigger input specified in the operation mode setting bits (MOD2, MOD1, and MOD0) is input to the TIN pins, a value stored in the 16-bit reload register (TMRLR) is loaded into the 16-bit down counter and countdown starts. When both the CNTE bit and the software trigger bit (TMCSR: TRG) are set to "1", countdown starts as soon as counting is enabled. When an underflow of the 16-bit down counter occurs (change from "0000H" to "FFFFH"), the 16-bit down counter stops counting at the value "FFFFH". An interrupt request is output when an underflow of the 16-bit down counter occurs while the underflow interrupt request flag bit (UF) of the timer control status register (TMCSR) is set to "1" and the underflow interrupt request enable bit (INTE) is set to "1". The timer can also output from the TO pin a rectangular waveform indicating that counting is in progress. ❍ Software trigger operation Counting starts when the software trigger bit (TRG) is set to "1" while the count enable bit (CNTE) of the timer control status register (TMCSR) is set to "1". Figure 12.6-7 Count Operation in Single-Shot Mode (Software Trigger Operation) Count clock -1 Counter 0000H FFFFH Reload data Data load signal UF bit CNTE bit TRG bit T* TO pin Wait for trigger input T: Machine cycle (one cycle of the machine clock) * It takes 1T time from trigger input to loading of the reload data. 240 -1 Reload data 0000H FFFFH 12.6 Operation of the 16-Bit Reload Timer ❍ External trigger input operation Counting starts when a valid edge (rising, falling, or both edges) of trigger input specified in the operation mode setting bits (MOD2, MOD1, and MOD0) is input to the TIN pins while the count enable bit (CNTE) of the timer control status register (TMCSR) is set to "1". Figure 12.6-8 Count Operation in Single-Shot Mode (External Trigger Operation) Count clock Counter -1 0000H FFFFH Reload data Data load signal -1 0000H FFFFH Reload data UF bit CNTE bit TIN bit 2T to 2.5T* TO pin Wait for trigger input T: Machine cycle (one cycle of the machine clock) * It takes 2T to 2.5T time from external trigger input to loading of the reload data. Note: Specify 2/φ or more for the width of the trigger pulse input to the TIN pin. ❍ External Gate input operation Counting starts when the software trigger bit (TRG) is set to "1" while the count enable bit (CNTE) of the timer control status register (TMCSR) is set to "1". Counting continues while a valid level of gate input ("L" or "H") specified in the operation mode setting bits (MOD2, MOD1, and MOD0) is input to the TIN pin. Figure 12.6-9 Count Operation in Single-Shot Mode (Software Trigger Gate Input Operation) Count clock Reload data Counter -1 0000H FFFFH -1 -1 Reload data Data load signal UF bit CNTE bit TRG bit T* Tin pin TO pin Wait for trigger input T: Machine cycle (one cycle of the machine clock) * It takes 1T time from trigger input to loading of the reload data. Note: Specify 2/φ (φ : machine clock frequency) or more for the width of a gate input pulse to be input to the TIN pin. 241 CHAPTER 12 16-BIT RELOAD TIMER 12.6.3 Event Count Mode The 16-bit reload timer count downs the 16-bit down counter every time it detects a valid edge of pulse input to the TIN pin and outputs an interrupt request when an underflow occurs (change from "0000H" to "FFFFH"). It can also output a toggle or square waveform from the T0 pin. ■ Event Count Mode When the software trigger bit (TRG) is set to "1" while the count enable bit (CNTE) of the timer control status register (TMCSR) is set to "1", a value stored in the 16-bit reload register (TMRLR) is loaded into the 16-bit down counter and countdown occurs every time a valid edge (rising, falling, or both edges) of pulse input to the TIN pin (external count clock) is detected. When both the CNTE bit and the software trigger bit (TRG) are set to "1", countdown starts as soon as counting is enabled. ❍ Operation in reload mode When an underflow of the 16-bit down counter occurs (change from "0000H" to "FFFFH"), a value stored in the 16-bit reload register (TMRLR) is loaded into the 16-bit down counter and countdown continues. An interrupt request is output to the CPU when an underflow of the 16-bit down counter (change from 0000H to FFFFH) occurs while the underflow interrupt request flag bit (UF) of the timer control status register (TMCSR) is set to "1" and the underflow interrupt request enable bit (INTE) is set to "1". The timer can also output from the TO pin a toggle waveform, which is inverted for each underflow. Figure 12.6-10 Count Operation in Reload Mode (Event Count Mode) TIN pin -1 Counter Reload data Data load signal 0000H -1 Reload data 0000H -1 Reload data 0000H -1 Reload data UF bit CNTE bit TRG bit TO pin T* T: Machine cycle (one cycle of the machine clock) * It takes 1T time from trigger input to loading of the reload data. Note: Specify 22/φ or more for the H and L widths of the pulse input to the TIN pin. 242 12.6 Operation of the 16-Bit Reload Timer ❍ Operation in single-shot mode When an underflow of the 16-bit down counter occurs (change from "0000H" to "FFFFH"), the 16-bit down counter stops counting at the value "FFFFH". An interrupt request is output to the CPU when an underflow of the 16-bit down counter (change from 0000H to FFFFH) occurs while the underflow interrupt request flag bit (UF) of the timer control status register (TMCSR) is "1" and the underflow interrupt request enable bit (INTE) is "1". The timer can also output from the TO pin a rectangular waveform indicating that count. Figure 12.6-11 Counter Operation in Single-Shot Mode (Event Count Mode) TIN pin -1 Counter 0000H FFFFH Reload data Data load signal -1 0000H FFFFH Reload data UF bit CNTE bit TRG bit T* TO pin Wait for trigger input T: Machine cycle (one cycle of the machine clock) * It takes 1T time from trigger input to loading of the reload data. Note: Specify 22/φ or more for the H and L widths of the pluse input to the TIN pin. 243 CHAPTER 12 16-BIT RELOAD TIMER 12.7 Usage Notes on the 16-Bit Reload Timer Notes on using the 16-bit reload timer are given below. ■ Usage Notes on the 16-Bit Reload Timer ❍ Notes on using a program for setting • Write a value to the 16-bit reload register (TMRLR) when counting stops (TMCSR: CNTE = 0). Also, a value can be read from the 16-bit timer register (TMR) even during counting, but always be sure to use a word transfer instruction (MOVW A, dir, etc.). • Counting must be stopped (TMCSR: CNTE = "0") when the count clock setting bits (CSL1 and CSL0) of the timer control register (TMCSR) are changed. ❍ Notes about interrupts 244 • When the UF bit of the timer control status register (TMCSR) is set to 1 and an interrupt request is enabled (TMCSR: INTE = 1), control cannot be returned from interrupt processing. Always clear the UF bit. • The 16-bit reload timer shares the interrupt control register with the 8/16-bit PPG timers. Therefore, if multiple interrupts of the same level are output, the interrupt with a smaller interrupt vector number has precedence. CHAPTER 13 16-BIT I/O TIMER This chapter describes the functions and operations of the 16-bit I/O timer of the MB90M405 series. 13.1 "Overview of the 16-Bit I/O Timer" 13.2 "16-Bit I/O Timer Block Diagram" 13.3 "16-Bit I/O Timer Registers" 13.4 "16-Bit Free-Running Timer Operations" 13.5 "16-Bit Output Compare Operations" 13.6 "16-Bit Input Capture Operations" 245 CHAPTER 13 16-BIT I/O TIMER 13.1 Overview of the 16-Bit I/O Timer The 16-bit I/O timer, which is based on a 16-bit free-running timer, can output two independent waveforms and measure an input pulse width and an external clock cycle. ■ 16-bit Free-Running Timer (One Channel) The 16-bit free-running timer consists of a 16-bit up counter (timer data register [TCDT]), timer control status register (TCCS), and prescaler. The counter output value of the 16-bit free-running timer is used as the basic time (base timer) for output compare and input capture. ❍ Counter operation clock (one of four types) Internal clock types: φ/4, φ/16, φ/32, φ/64 φ: Machine clock frequency ❍ Interrupt An interrupt is issued to the CPU when a counter overflow occurs or the counter value matches the value of compare register 0. ❍ Initialization The counter value is initialized to 0000H when a reset occurs, the software reset bit is cleared to "0", or the value of compare register 0 matches the count value of the free-running timer. ■ Output Compare (One Channel) The output compare module consists of a 16-bit compare register and a control register. When the value of the 16-bit free-running timer matches the compare register value, an interrupt is issued to the CPU. ■ Input Capture (Two Channels) The input capture module consists of a capture register and a control register, each of which corresponds to two independent external input pins. The capture register stores the value of the 16-bit free-running timer. It can also issue an interrupt to the CPU when an edge of the signal input from an external pin is detected. • The edge to be detected (rising, falling, or both edges) of an external input signal can be selected. • Two input capture modules can operate independently. • An interrupt can be issued upon detection of a valid edge of an external input signal. An input capture interrupt can be used to start the extended intelligent I/O service. 246 13.2 16-Bit I/O Timer Block Diagram 13.2 16-Bit I/O Timer Block Diagram Figure 13.2-1 "16-Bit I/O Timer Block Diagram" shows a block diagram of the 16-bit I/O timer. ■ 16-Bit I/O Timer Block Diagram Figure 13.2-1 16-Bit I/O Timer Block Diagram φ Interrupt request IVF IVFE STOP MODE CLR CLK1 CLK0 (TCCS) Divider Comparator 0 Clock 16-bit free-running timer (data register [TCDT]) Count value output (T15 to T00) Internal data bus Compare control Compare register 0 (2) - ICP0 - ICE0 Control section Compare 0 (2) interrupt Each control block Capture data register 0 Edge detection IC0 EG11 EG10 EG01 EG00 Capture data register 1 Edge detection ICP1 ICP0 ICE1 IC1 ICE0 Capture interrupt Capture interrupt 247 CHAPTER 13 16-BIT I/O TIMER 13.3 16-Bit I/O Timer Registers The 16-bit I/O timer has the following six types of registers: • Timer counter data register (TCDT) • Timer counter control status register (TCCS) • Output compare register (OCCP0) • Output compare control status register (OCS0) • Input capture data register (IPC0 and IPC1) • Input capture control status register (ICS01) ■ 16-Bit I/O Timer Registers Figure 13.3-1 16-Bit I/O Timer Registers bit15 bit8 bit7 Timer counter data register upper (TCDT) bit0 Timer counter data register lower (TCDT) Timer counter control status register (TCCS) Output compare register upper (OCCP) Output compare register lower (OCCP) Output compare control status register (OCS0) Input capture data register upper (IPC) Input capture data register lower (IPC) Input capture control status register (ICS01) 248 13.3 16-Bit I/O Timer Registers 13.3.1 16-Bit Free-Running Timer Registers (TCDT and TCCS) The 16-bit free-running timer has the following registers: • Timer counter data register (TCDT) • Timer counter control status register (TCCS) ■ Timer Counter Data Register (TCDT) The count value of the 16-bit free-running timer can be read from the timer counter data register (TCDT). A reset clears the counter value to 0000B. You can set the timer value via the timer counter data register. The setting must be made in stop state (STOP="1"). The 16-bit free-running timer is initialized by any of the following events: • Reset • Initialization due to the clear bit (CLR) of the control status register • Initialization due to a match between compare register 0 for output compare and the timer counter value (mode setting is required) Figure 13.3-2 Timer Counter Data Register (TCDT) Bit 15 14 13 12 11 10 9 8 T15 T14 T13 T12 T11 T10 T09 T08 Initial value 00000000 B R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 T07 T06 T05 4 3 T04 T03 2 1 0 T02 T01 T00 Initial value 00000000 B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Read/write enabled Note: The timer counter data register (TCDT) requires word access. 249 CHAPTER 13 16-BIT I/O TIMER ■ Timer Counter Control Status Register (TCCS) Figure 13.3-3 Timer Counter Control Status Register (TCCS) Bit 7 6 Reserve IVF 5 4 3 2 1 0 Initial value IVFE STOPMODE CLR CLK1 CLK0 R/W R/W R/W R/W 00000000B R/W R/W R/W R/W CLK1 CLK0 Count clock selection bit Count clock φ = 16MHz φ = 8MHz φ/4 0.25ns 0.5 ns 1 ns 4 μs 0 1 φ/16 1 ns 2 ns 4 ns 16 μs 1 0 φ/64 4 ns 8 ns 16 μs 64 μs 1 1 φ/256 16 ns 32 μs 32 μs 256 μs Clear bit 0 No effect on operation 1 Counter initialized to 0000H MODE Free-running timer initialization condition setting bit 0 Initialization occurs due to a reset or the clear bit. 1 Initialization occurs due to a reset, the clear bit, or compare register 0. Count stop bit STOP 0 Counting enabled (The counter is operating.) 1 Counting disabled (The counter is stopped.) IVFE φ 250 Free-running timer interrupt request enable bit 0 Interrupt requests disabled 1 Interrupt requests enabled IVF : Read/write enabled : Initial value : Machine clock frequency φ = 1MHz 0 CLR R/W φ = 4MHz 0 Free-running timer interrupt request flag bit Read Write 0 No interrupt request present Interrupt request cleared 1 Interrupt request present No effect on operation 13.3 16-Bit I/O Timer Registers Table 13.3-1 Functions of the Timer Counter Control Status Register (TCCS) Bits Bit name bit 7 bit 6 bit 5 bit 4 Reserved: Reserved bit IVF: Free-running timer interrupt request flag bit IVFE: Free-running timer interrupt request enable bit STOP: Count stop bit Function • Be sure to set this bit to "0". • • This bit is a flag bit for an interrupt request. This bit is set to "1" if the counter value of the 16-bit free-running timer overflows. An interrupt is output if this bit is set to "1" while the free-running timer interrupt enable bit (IVFE) is "1". An interrupt request is cleared if this bit is set to "0". Setting this bit to "1" does not effect operation. Read-modify-write instructions return "1" for this bit. • • • • • • This bit enables interrupt requests. An interrupt is output if the free-running timer interrupt request flag bit (IVF) is set to "1" while this bit is "1". • This bit stops the 16-bit free-running timer counter. • If this bit is set to "0", the 16-bit free-running timer counter runs. • If this bit is set to "1", the 16-bit free-running timer counter stops. Note: • When the 16-bit free-running timer counter stops, the output compare operation also stops. • MODE: Free-running timer initialization condition setting bit This bit sets the initialization condition of the 16-bit free-running timer counter value. • If this bit is set to "0", a reset or setting the clear bit (CLR="1") initializes the counter value to 0000H. • If this bit is set to "1", a reset, setting the clear bit (CLR="1"), or a match between the 16-bit free-running timer counter value and the compare clear register (CPCLR) value initializes the counter value to 0000H. Note: • The counter value is cleared at the next counting operation after the detection of an initialization condition as specified in the MODE bit. bit 2 CLR: Clear bit The CLR bit clears the counter value to 0000H while the 16-bit freerunning timer counter is running. • If this bit is set to "0", operation is not affected. • If this bit is set to "1", the counter value is cleared to 0000H. • The read value of this bit is always "0". Note: • To clear the counter value to 0000H while the 16-bit free-running timer counter is stopped (STOP="1"), set the timer data register (TCDT) to 0000H. bit 1 bit 0 CLK1 and CLK0: Count clock selection bits bit 3 • • • These bits select the count clock of the 16-bit free-running timer. Set these bits while output compare and input capture are stopped, since the count clock changes as soon as these bits are set. 251 CHAPTER 13 16-BIT I/O TIMER 13.3.2 Output Compare Registers (OCCP0 and OCS0) The output compare unit uses the following registers: • Output compare register (OCCP0) • Output compare control status register (OCS0) ■ Output Compare Register (OCCP0) The output compare register (OCCP0) is a 16-bit register whose value is compared with the 16bit free-running timer. Because the initial value of this register is undefined, set an initial value before enabling timer operation. When the output compare register value matches the 16-bit free-running timer value, a compare signal that sets the output compare interrupt request flag bit to "1" is generated. Figure 13.3-4 Output Compare Register (OCCP0) Bit 15 14 C15 C14 13 12 11 10 C13 C12 C11 C10 9 8 C09 C08 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W 7 6 C07 C06 5 C05 4 3 2 C04 C03 C02 1 0 C01 C00 R/W R/W R/W R/W R/W R/W R/W R/W R/W : Read/write enabled X : Undefined Note: The output compare register (OCCP0) requires word access. 252 Initial value XXXXXXXXB 13.3 16-Bit I/O Timer Registers ■ Output Compare Control Status Register (OCS0) Figure 13.3-5 Output Compare Control Status Register (OCS0) Bit 7 6 5 4 3 2 1 0 - IOP0 - IOE0 - - - CST0 - R/W - R/W - - - R/W CST0 Compare operation enabled 1 Compare operation disabled R/W X - : : : : Output compare interrupt request enable bit 0 Interrupt requests disabled 1 Interrupt requests enabled IOP0 XX00XXX0B Compare operation enable bit 0 IOE0 Initial value Output compare interrupt request flag bit Read Write 0 No interrupt request present Interrupt request cleared 1 Interrupt request present No effect on operation Read/write enabled Undefined Undefined bit Initial value 253 CHAPTER 13 16-BIT I/O TIMER Table 13.3-2 Functions of the Output Compare Control Status Register (OCS0) Bits Bit name bit 7 bit 6 -: Undefined bit IOP0: Output compare interrupt request flag bit bit 5 -: Undefined bit bit 4 IOE0: Output compare interrupt request enable bit bit 3 bit 2 -: Undefined bit bit 1 bit 0 CST1, CST0: Compare operation enable bit Function • • The value read from this bit is undefined. Setting this bit to a new value does not affect operation. • • • • • This bit is a flag bit for interrupt requests. This bit is set to "1" if the compare register (OCCP) value matches the value of the 16-bit free-running timer counter. An interrupt is output to the CPU if this bit is set to "1" while the output compare interrupt enable bit (IOE0) is "1". An interrupt request is cleared if this bit is set to "0". Setting this bit to "1" does not affect operation. Read-modify-write instructions return "1" for this bit. • • The value read from this bit is undefined. Setting this bit to a new value does not affect operation. • • This bit enables interrupt requests. An interrupt request is output to the CPU if the output compare interrupt request flag bit (IOP0) is set to "1" while this bit is "1". • • The value read from this bit is undefined. Setting this bit to a new value does not affect operation. • This bit enables a compare operation between the output compare register (OCCP0) value and the 16-bit free-running timer counter value. Set the output compare register (OCCP0) value before enabling the compare operation. If this bit is set to "1", the compare operation is enabled. • • • Note: Since output compare is synchronized with the 16-bit free-running timer clock, the compare operation stops when the 16-bit free-running timer stops (TCCS:STOP="1"). 254 13.3 16-Bit I/O Timer Registers 13.3.3 Input Capture Registers (IPC0/IPC1 and ICSSS0) The input capture unit has the following registers: • Input capture data registers (IPC0/IPC1) • Input capture control status register (ICS01) ■ Input Capture Data Registers (IPC0/IPC1) The input capture data registers (IPC0/IPC1) retain the value of the 16-bit free-running timer when a valid edge of the corresponding external pin input waveform is detected. Figure 13.3-6 Input Capture Data Registers (IPC0/IPC1) Bit 15 14 13 12 11 10 9 8 CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 Bit R R R R R R R R 7 6 5 4 3 2 1 0 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 R R R R R R R Initial value XXXXXXXX B Initial value XXXXXXXX B R R : Read only X : Undefined Note: The input capture data registers (IPC0/IPC1) require word access. Writing to these registers is disabled. 255 CHAPTER 13 16-BIT I/O TIMER ■ Input Capture Control Status Register (ICS01) Figure 13.3-7 Input Capture Control Status Register (ICS01) Bit 7 6 5 4 3 2 1 0 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 R/W R/W R/W R/W 00000000B R/W R/W R/W R/W EG01 EG00 Valid edge polarity selection bits 0 0 No edge detected (operation disabled) 0 1 Rising edge detected ↑ (operation enabled) 1 0 Falling edge detected ↓ (operation enabled) 1 1 Both edges detected ↑↓ (operation enabled) EG11EG10 Valid edge polarity selection bits 0 0 No edge detected (operation disabled) 0 1 Rising edge detected ↑ (operation enabled) 1 0 Falling edge detected ↓ (operation enabled) 1 1 Both edges detected ↑↓ (operation enabled) ICE0 Input capture interrupt request enable bit 0 Interrupt requests disabled 1 Interrupt requests enabled ICE1 Input capture interrupt request enable bit 0 Interrupt requests disabled 1 Interrupt requests enabled ICP0 Input capture interrupt request flag bit Read Write 0 No interrupt request present Interrupt request present 1 Interrupt request cleared No effect on operation ICP1 R/W Initial value Input capture interrupt request flag bit Read Write 0 No interrupt request present Interrupt request present 1 Interrupt request cleared No effect on operation : Read/write enabled : Initial value Note: The input capture data register (ICS01) requires byte access. 256 13.3 16-Bit I/O Timer Registers Table 13.3-3 Functions of the Input Capture Control Status Register (ICS01) Bits Bit name bit 7 bit 6 ICP1, ICP0: Input capture interrupt request flag bit bit 5 bit 4 ICE1, ICE0: Input capture interrupt request enable bit bit 3 to bit 0 EG11, EG10, EG01, EG00: Valid edge polarity selection bits Function • • • • • • This bit is a flag bit for interrupt requests. This bit is set to "1" if a valid edge of an external input pin is detected. An interrupt request is output if this bit is set to "1" while the input capture interrupt enable bits (ICE1 and ICE0) are "1". An interrupt request is cleared if this bit is set to "0". Setting this bit to "1" does not affect operation. Read-modify-write instructions return "1" for this bit. • • This bit enables interrupt requests. An interrupt request is output if the input capture interrupt request flag bits (ICP1, ICP0) are set to "1" while this bit is "1". • These bits select the polarity of a valid edge of the input waveform and enable or disable the input capture operation. The input capture operation is enabled if these bits are set to 01B to 11B. The polarity of a valid edge of the input waveform can be selected as rising edge, falling edge, or both edges. If these bits are set to 00B, input capture operation and edge detection are disabled. • • 257 CHAPTER 13 16-BIT I/O TIMER 13.4 16-Bit Free-Running Timer Operations The 16-bit free-running timer starts counting from the counter value 0000B after a reset is released. The counter value is used as the reference time for16-bit output compare and 16-bit input capture. ■ 16-Bit Free-Running Timer Operations A counter value is cleared in the following cases: • The counter value overflows. • The counter value matches the value of output compare register 0. (A mode must be set.) • The clear bit (CLR) of the timer counter control status register (TCCS) is set to "1". • The timer counter data register (TCDC) is set to 0000B during a stop. • A reset occurs. An interrupt can be output to the CPU if the free-running timer overflows or if the counter is cleared when the free-running timer value matches the value of compare register 0 (A mode must be set for the compare match interrupt). Figure 13.4-1 Counter Cleared by an Overflow Counter value Overflow FFFFH BFFFH 7FFFH 3FFFH Time 0000H Reset Interrupt Figure 13.4-2 Counter Cleared by a Compare Match with Output Compare Register 0 Value Counter value FFFFH BFFFH Match Match 7FFFH 3FFFH 0000H Time Reset Compare register value Interrupt 258 BFFFH 13.4 16-Bit Free-Running Timer Operations ■ 16-bit Free-Running Timer Count Timing The 16-bit free-running timer counts up based on the specified internal clock. Figure 13.4-3 Count Timing of the Free-Running Timer φ Count clock N Counter value N+1 The counter can be cleared using a reset, software clear, or match with compare register 0. A reset or software clears the counter immediately. A match with compare register 0 clears the counter in synchronization with the count timing. Figure 13.4-4 Clear Timing of the Free-Running Timer (Match with Compare Register 0) φ N Compare register value Compare match Counter value N 0000 259 CHAPTER 13 16-BIT I/O TIMER 13.5 16-Bit Output Compare Operations A 16-bit output compare compares the specified compare register value with the value of the 16-bit free-running timer. If a match occurs, the interrupt request flag bit is set to "1". ■ 16-bit Output Compare Operations Output compare outputs an interrupt when the free-running timer value matches the specified compare register value and a compare match signal is generated. Figure 13.5-1 Compare Operation When Compare Register Rewritten Compare register 0 value N+1 N+2 No match signal is generated. N+1 N Counter value M Compare register 0 write Compare 0 stops. Figure 13.5-2 Interrupt Timing of Output Compare φ Counter value Compare register value Compare match Interrupt 260 N+1 N N N+3 13.6 16-Bit Input Capture Operations 13.6 16-Bit Input Capture Operations The 16-bit input capture can capture the 16-bit free-running timer value in the capture register for outputting an interrupt when the specified valid edge is detected. ■ 16-bit Input Capture Operations Figure 13.6-1 Example of Input Capture Timing Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset IN0 IN1 ININ example Capture 0 Capture 1 Capture example Undefined 3FFFH Undefined Undefined 7FFFH BFFFH 7FFFH Capture 0 interrupt Capture 1 interrupt Capture interrupt Capture0 = Rising edge Capture1 = Falling edge Capture example = Both edges (example) 261 CHAPTER 13 16-BIT I/O TIMER ■ Input Capture Input Timing Figure 13.6-2 Capture Timing for Input Signals φ Counter value Input capture input N N+1 Valid edge Capture signal Capture register Interrupt 262 N+1 CHAPTER 14 UART This chapter describes the functions and operations of the MB90M405 series UART. 14.1 "Overview of UART" 14.2 "Configuration of UART" 14.3 "UART Pins" 14.4 "UART Registers" 14.5 "UART Interrupts" 14.6 "UART Baud Rates" 14.7 "Operation of UART" 14.8 "Notes on Using UART" 263 CHAPTER 14 UART 14.1 Overview of UART UART is a general-purpose serial data communication interface for performing synchronous or asynchronous (start-stop synchronization) communication with external devices. The UART has a bidirectional communication function (normal mode), additionally the master-slave communication function (multiprocessor mode) is only available for the master system. ■ UART Functions ❍ UART Functions UART is a general-purpose serial data communication interface for transmitting serial data to and receiving data from another CPU and peripheral devices. It has the functions listed in Table 14.1-1 "UART Functions". Table 14.1-1 UART Functions Function Data buffer Full-duplex, double buffering Transfer mode • • Clock synchronous (using start and stop bits) Clock asynchronous (start-stop synchronization) Baud rate • • • • • Up to 2MHz (when the machine clock is operated at 16MHz) A dedicated baud rate generator is provided. Baud rate by an external clock (clock input through the SCK pins) Internal clock (internal clocks supplied from 16-bit reload timer 0 can be used.) The baud rate can be selected from a total of eight types Data length • • 7 bits (in asynchronous normal mode only) 8 bits Signal mode Non-return to zero (NRZ) Reception error detection • • • Framing error Overrun error Parity error (cannot be detected in multiprocessor mode.) Interrupt request • • • Reception interrupt (reception completion and reception error detection) Transmission interrupt (transmission completion) Extended intelligent I/O service (EI20S) is available for both transmission and reception interrupts. Master-slave communication function (multiprocessor mode) One-to-n communication (one master to n slaves) can be performed. (This function is supported only for the master system.) 264 14.1 Overview of UART Note: During clock synchronous transfer, start and stop bits are not added so only data is transferred in UART. Table 14.1-2 UART Operation Mode Data length Operation mode When parity is disabled Synchronization on mode When parity is enabled 0 Normal mode 7 or 8 bits 1 Multiprocessor 8+1 (*1) - Asynchronous 2 Normal mode 8 - Synchronous Stop bit length 1 or 2 bits (*2) Asynchronous None -: Setting not possible *1: "+1" indicates the address/data selection bit (A/D) for communication control. *2: During reception, only one stop bit can be detected. ■ UART Interrupt and EI2OS Table 14.1-3 UART Interrupt and El2OS Interrupt cause UART0 reception interrupt Interrupt number Interrupt control register Register name Address #35(23H) ICR12 Vector table address EI2OS Lower Upper Bank FFFF70H FFFF71H FFFF72H 0000BCH UART0 transmission interrupt #36(24H) FFFF6CH FFFF6DH FFFF6EH UART1 reception interrupt #39(27H) FFFF60H FFFF61H FFFF62H FFFF5CH FFFF5DH FFFF5EH ICR14 UART1 transmission interrupt #40(28H) 0000BEH : Provided with a function that detects a UART reception error and stops EI2OS : Usable when ICR12 and ICR14 or interrupt causes that share an interrupt vector are not used 265 CHAPTER 14 UART 14.2 Configuration of UART UART consists of the following 11 blocks: • Clock Selector • Reception Control Circuit • Transmission Control Circuit • Reception Status Detection Circuit • Reception Shift Register • Transmission Shift Register • Mode Control Register (SMR0/1) • Control Register (SCR0/1) • Status Register (SSR0/1) • Input Data Register (SIDR0/1) • Output Data Register (SODR0/1) ■ Block Diagram of UART 266 14.2 Configuration of UART Figure 14.2-1 Block Diagram of UART Control bus Reception interrupt signal Dedicated baud rate generator 16-bit reload timer Transmission clock Clock selector Reception clock Pin Reception control circuit Transmission interrupt signal Transmission control circuit Start bit detection circuit Transmission start circuit Received bit counter Transmission bit counter Received parity counter Transmission parity counter Reception shift register Transmission shift register Pin Completion of reception SIDR0/SIDR1 SODR0/SODR1 Pin Start of transmission Reception status detection circuit Reception error reception signal for EI²OS (to CPU) Internal data bus SMR0/ SMR1 register MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR0/ SCR1 register PEN P SBL CL A/D REC RXE TXE SSR0 /SSR1 register PE ORE FRE RDRF TDRE BDS RIE TIE ❍ Clock Selector The clock selector selects the sending/receiving clock from the dedicated baud rate generator, external input clock (clock input through the SCK0/SCK1 pins), and internal clock (clock supplied from the 16-bit reload timer). ❍ Reception Control Circuit The reception control circuit consists of a received bit counter, start bit detection circuit, and received parity counter.The received bit counter counts receive data bits. When reception of one data item for the specified data length is complete, the received bit counter generates a reception interrupt request. The start bit detection circuit detects start bits from the serial input signal. When the circuit detects a start bit, it writes data in the SIDR0/1 register by shifting at the specified transfer rate. The received parity counter calculates the parity of the receive data. 267 CHAPTER 14 UART ❍ Transmission Control Circuit The transmission control circuit consists of a transmission bit counter, transmission start circuit, and transmission parity counter.The transmission bit counter counts transmission data bits. When transmission of one data item of the specified data length is complete, the transmission bit counter generates a transmission interrupt request. The transmission start circuit starts transmission when send data is written to the output data register (SODR0/SODR1). The transmission parity counter generates the parity bits for data when transmitting data with parity. ❍ Reception Shift Register The reception shift register fetches receive data input from the SIN0/1 pin, shifting the data bit by bit. When reception is complete, the reception shift register transfers receive data to the SIDR0/1 register. ❍ Transmission Shift Register The transmission shift register transfers data written to the SODR0/1 register to itself and outputs the data to the SOT0/1 pin, shifting the data bit by bit. ❍ Mode Control Register (SMR0/1) The mode register performs the operations of the operation mode setting, baud rate clock setting, serial clock I/O control, and output enable setting of serial data to pins. ❍ Control Register (SCR0/1) The control register performs the operations of the parity presence/absence setting, parity setting, stop bit length/data length settings, frame data format setting in operation mode 1, clearing of received error flag bits, and enable/disable setting of send/receive operations. ❍ Status Register (SSR0/1) The status register performs the operations of status check for transmission/reception and errors, transfer direction setting of serial data, and enable/disable setting of send/receive interrupt requests. ❍ Input Data Register (SIDR0/1) This register retains receive data. ❍ Output Data Register (SODR0/1) This register sets transmission data. Data written to this register is converted to serial data and output. 268 14.3 UART Pins 14.3 UART Pins This section describes the UART pins and provides a pin block diagram. ■ UART Pins The UART pins also serve as I/O ports. Table 14.3-1 UART Pins Pin name Pin function I/O format Pull-up Standby control Setting required to use pin SI0 Port I/O or serial data input Set as an input port (DDR8: bit2 = 0) SO0 Port I/O or serial data output Set to serial data output enable mode (SMR0: SOE = 1) Set as an input port (DDR8: bit3 = 0) SC0 Port I/O or serial clock input/output SI1 Port I/O or serial data input SO1 Port I/O or serial data output CMOS output and CMOS hysteresis input Set to serial clock output enable mode (SMR0:SCKE = 1) Nothing Provided Set as an input port (DDR8: bit5 = 0) Set to serial data output enable mode (SMR1: SOE = 1) Set as an input port (DDR8: bit6 = 0) SC1 Port I/O or serial clock input/output Set to serial clock output enable mode (SMR1:SCKE = 1) 269 CHAPTER 14 UART ■ Block Diagram of UART Pins Figure 14.3-1 Block Diagram of UART Pins Internal data bus Resource input PDR read PDR I/O evaluation circuit PDR write DDR Output buffer Standby control (LPMCR: SPL="1") I/O control circuit Resource output 270 Input buffer Port pin 14.4 UART Registers 14.4 UART Registers The following figure shows the UART registers. ■ UART Registers Figure 14.4-1 UART Registers bit15 bit8 bit7 Control register (SCR) Status register (SSR) bit0 Mode control register (SMR) Input/output data register (SIDR/SODR) Communication prescaler control register (CDCR) 271 CHAPTER 14 UART 14.4.1 Control Register (SCR0/SCR1) The control register (SCR0/SCR1) is a register for performing the operations of the parity presence/absence setting, parity setting, stop bit length/data length settings, frame data format setting in operation mode 1, clearing of received error flag bits, and enable/disable setting of send/receive operations. ■ Control Register (SCR0/SCR1) Figure 14.4-2 Control Register (SCR0/SCR1) Bit 15 14 13 12 11 PEN P SBL CL A/D R/W R/W R/W R/W R/W 10 9 8 Initial value REC RXE TXE W 0 0 0 0 0 1 0 0B R/W R/W TXE Transmission enable bit 0 Disables transmission. 1 Enables transmission. RXE Reception enable bit 0 Disables reception. 1 Enables reception. REC Reception error flag clear bit 0 Clears the FRE, ORE, and PE flags. 1 Has no effect on the others. A/D Address/data setting bit 0 Data frame 1 Address frame CL 7 bits 1 8 bits SBL 1-bit length 1 2-bit length Parity setting bit Enabled only when parity is provided (PEN=1) 0 Even parity 1 Odd parity PEN 272 Stop bit length setting bit 0 P R/W : Read/Write W : Write only : Initial value Data length setting bit 0 Parity enable bit 0 Provides no parity bit. 1 Provides a parity. 14.4 UART Registers Table 14.4-1 Functions of Bits for Control Register (SCR0/SCR1) Bit name Function bit15 PEN: Parity enable bit This bit selects whether to add a parity bit during transmission in serial data input-output mode or to detect it during reception. Note: No parity can be used in operation modes 1 and 2. Therefore, fix this bit to 0. bit14 P: Parity selection bit This bit specifies the odd parity/even parity. Note: Valid only when parity presence (PEN="1") is selected. bit13 SBL: Stop bit length selection bit This bit selects the length of the stop bits or the frame end mark of send data in asynchronous transfer mode. Note: During reception, only the first bit of the stop bits is detected. bit12 CL: Data length selection bit This bit specifies the length of send and receive data. Note: Seven bits can be selected in operation mode 0 (asynchronous) only. Be sure to select eight bits (CL=1) in operation mode 1 (multiprocessor mode) and operation mode 2 (synchronous). bit11 A/D: Address/ data selection bit • • bit10 REC: Reception error flag clear bit • bit9 RXE: Reception enable bit • • Specify the data format of a frame to be sent or received in multiprocessor mode (mode 1). Select usual data when this bit is 0, and select address data when the bit is 1. This bit clears the FRE, ORE, and PE flags of the status register (SSR0/1). • Write 0 to this bit to clear the FRE, ORE, and PE flag. Writing 1 to this bit has no effect on the others. Note: If UART is active and a reception interrupt is enabled, clear the REC bit only when the FRE, DRE, or PE flag indicates 1. This bit controls UART reception. When this bit is 0, reception is disabled. When it is 1, reception is enabled. Note: If reception operation is disabled during reception, reception of data currently being received is finished and the received data is stored in the input data register (SIDR0/SIDR1), and then the reception operation is stopped. 273 CHAPTER 14 UART Table 14.4-1 Functions of Bits for Control Register (SCR0/SCR1) (Continued) Bit name bit8 274 TXE: Transmission enable bit Function • • This bit controls UART transmission. When this bit is 0, transmission is disabled. When the bit is 1, transmission is enabled. Note: When transmission operation is disabled during transmission, wait until there is no data in the send data buffers (SODR0/1) before stopping the transmission operation. If transmission operation is disabled during transmission, transmission operation is stopped after all data in the output data register (SODR0/ SODR1) is sent out. When setting "0", write data to the output data register (SODR0/SODR1) and then wait for at least 1/16 period of the baud rate for the clock asynchronous transfer mode and the same period as the baud rate for the clock synchronous transfer mode. 14.4 UART Registers 14.4.2 Mode Register (SMR0/SMR1) The mode register (SMR0/SMR1) is a register for performing the operations of the operation mode setting, baud rate clock setting, serial clock I/O control, and output enable setting of serial data to pins. ■ Mode Control Register (SMR0/SMR1) Figure 14.4-3 Mode Control Register (SMR0/SMR1) Bit 7 6 5 4 3 2 1 0 Initial value MD1 MD0 CS2 CS1 CS0 - SCKE SOE R/W R/W R/W R/W R/W - R/W R/W SOE 00000X00B 0 Serial data output enable bit (P37/SOT0, P61/SOT1 pin) Uses the pin as an I/O port. 1 Uses the pin as the serial data output pin. SCKE Serial clock output enable bit (P40/SCK0, P62/SCK1 pin) 0 1 Uses the pin as an I/O port or clock input pin of UART0/1 Uses the pin as the clock output pin. CS2 to 0 Clock selection bit "000B" to "101B" "110B" "111B" Operation mode selection bit MD1 MD0 R/W : Enables read and write. X : Undefined - : Undefined bit : Initial value Baud rate by dedicated baud rate generator Baud rate by internal timer (16-bit reload timer) Baud rate by external clock (SCK0/SCK1 pins) Operation mode 0 0 0 Asynchronous (normal mode) 0 1 1 1 0 2 Asynchronous (multiprocessor mode) Synchronous (normal mode) 1 1 - Disables setting. 275 CHAPTER 14 UART Table 14.4-2 Functions of Bits for Mode Register (SMR0/SMR1) Bit name Function bit7 bit6 MD1 and MD0: Operation mode selection bits These bits select an operation mode. Note: Operation mode 1 (multiprocessor mode) can be used only from the master system during master-slave communication. UART cannot be used from the slave system because it has no address/data detection function during reception. bit5 bit4 bit3 CS2 to CS0: Clock selection bits • • • This bit selects a baud rate clock source. When the dedicated baud rate generator is selected, the baud rate is determined at the same time. When the dedicated baud rate generator is selected, eight baud rates can be selected: 6 types for the dedicated baud rate generator selected, 1 type for the internal timer selected, and 1 type for the external clock selected. Clock input can be selected from external clocks (SCK0/SCK1 pin input), the internal clock (16-bit reload timer0), and the dedicated baud rate generator. bit2 -: Undefined bit • • bit1 SCKE: Serial clock output enable bit • • This bit controls the serial clock input-output ports. When this bit is 0, the SC pins operate as input-output ports or serial clock input pins. When this bit is 1, the pins operate as serial clock output pins. Note: - To use the SC pins as serial clock input (SCKE="0") pins, set them as input pins. Also, select an external clock (SMR0/SMR1: CS2 to CS0="111B") using the clock setting bits. - To use the SC pins as serial clock output (SCKE="1"), select the dedicated baud rate generator (SMR0/SMR1:CS2 to CS0=000B to 101B) or internal clock (SMR0/SMR1:CS2 to CS0=110B). Reference: When the SCK0/1 pin is assigned to serial clock output (SCKE=1), it functions as the serial clock output pin regardless of the status of the inputoutput ports. bit0 SOE: Serial data output enable bit • This bit enables the output of serial data. • When this bit "0", the SO pins operate as an I/O port. • When this bit is "1", the SO pins operate as a serial data output pin. Reference: When the serial data output (SOE="1") is selected, the pins operate as a serial data output pin regardless of the state of the I/O port. 276 When this bit is read, the value is undefined. The value set to this bit does not affect operation. 14.4 UART Registers 14.4.3 Status Register (SSR0/SSR1) The status register (SSR0/SSR1) is a register for performing the operations of status check for transmission/reception and errors, transfer direction setting of serial data, and enable/disable setting of send/receive interrupts. ■ Status Register (SSR0/SSR1) Figure 14.4-4 Status Register (SSR0/SSR1) Bit 15 PE R 14 13 12 11 10 9 ORE FRE RDRF TDRE BDS RIE R R R R 8 TIE Initial value 00001000B R/W R/W R/W TIE Transmission interrupt request enable bit 0 Disables output of transmission interrupt request. 1 Enables output of transmission interrupt request. RIE Reception enable bit 0 Disables output of reception interrupt request. 1 Enables output of reception interrupt request. BDS Transfer direction selection bit 0 LSB first (transfer from the least significant bit) 1 MSB first (transfer from the most significant bit) TDRE Transmission data empty flag bit 0 Transmission data exists. (Writing transmission data is not allowed.) 1 Transmission data does not exist. (Writing transmission data is allowed.) RDRF Receive data full flag bit 0 No receive data exists. 1 Receive data exists. Framing error flag bit FRE 0 No framing error occurred. 1 ORE A framing error occurred. Overrun error flag bit 0 No overrun error occurred. 1 An overrun error occurred. PE Parity error flag bit 0 No parity error occurred. 1 A parity error occurred. R/W : Read/Write R : Read only : Initial value 277 CHAPTER 14 UART Table 14.4-3 Functions of Bits for Status Register (SSR0/SSR1) No. bit15 Bit name PE: Parity error flag bit Function • • • • bit14 ORE: Overrun error flag bit • • • • bit13 FRE: Framing error flag bit • • • • bit12 RDRF: Receive data full flag bit • • • • This bit is set to "1" when a parity error occurs during reception. This bit is cleared to "0" when "0" is written to the reception error flag clear bit (REC) of the control register (SCR0/SCR1). When this bit is set to "1" while the reception interrupt request enable bit (RIE) is 1, a reception interrupt request is output. When this bit is set to "1", data in the input data register (SIDR0/SIDR1) will be invalid. This bit is set to "1" when an overrun error occurs during reception. This bit is cleared to "0" when "0" is written to the reception error flag clear bit (REC) of the control register (SCR0/SCR1). When this bit is set to "1" while the reception interrupt request enable bit (RIE) is 1, a reception interrupt request is output. When this bit is set to "1", data in the input data register (SIDR0/SIDR1) will be invalid. This bit is set to "1" when a framing error occurs during reception. This bit is cleared to "0" when "0" is written to the reception error flag clear bit (REC) of the control register (SCR0/SCR1). When this bit is set to "1" while the reception interrupt request enable bit (RIE) is 1, a reception interrupt request is output. When this bit is set to "1", data in the input data register (SIDR0/SIDR1) will be invalid. This bit indicates the status of the input data register (SIDR0/SIDR1). This bit is set to "1" when the receive data is stored in the input data register (SIDR0/SIDR1). This bit is cleared to "0" when the input data register (SIDR0/SIDR1) is read. When the reception interrupt request enable bit (RIE) is set to 1 while this bit is "1", a reception interrupt request is output. bit11 TDRE: Transmission data empty flag bit This bit indicates the status of the output data register (SODR0/SODR1). This bit is cleared to "0" when transmission data is written to the output data register (SODR0/SODR1). • This bit is set to "1" when data is sent after loading it into the transmission shift register. • When the transmission interrupt request enable bit (TIE) is set to 1 while this bit is "1", a transmission interrupt request is output. Note: "1" is set in the initial state. bit10 BDS: Transfer direction selection bit • • 278 • • This bit specifies the transfer direction of serial data. When this bit is set to "0", transfer starts with the lowest-order bit (LSB first). • When this bit is set to "1", transfer starts with the highest-order bit (MSB first). Note: The upper bits and lower bits of data are exchanged during reading from or writing to the serial data register. Written data therefore becomes invalid if the bit direction selection bit (BDS) is rewritten after the data was written to the output data register (SODR0/SODR1). 14.4 UART Registers Table 14.4-3 Functions of Bits for Status Register (SSR0/SSR1) (Continued) No. Bit name Function bit9 RIE: Reception interrupt request enable bit • • This bit enables a reception interrupt request. When the reception data full flag enable bit (RDRF) is set to "1" or one of the reception error flag bits (PE, ORE, and FRE) is set to "1" while this bit is "1", a reception interrupt request is output. bit8 TIE: Transmission interrupt request enable bit • • This bit enables a transmission interrupt request. When the transmission data empty flag bit (TDRE) is set to "1" while this bit is "1", a transmission interrupt request is output. 279 CHAPTER 14 UART 14.4.4 Input Data Register (SIDR0/SIDR1) and Output Data Register (SODR0/SODR1) The input data register (SIDR0/SIDR1) is a serial data reception register. The output data register (SODR0/SODR1) is a serial data transmission register. ■ Input Data Register (SIDR0/SIDR1) Figure 14.4-5 Input Data Register (SIDR0/SIDR1) Bit 7 6 5 4 3 2 1 0 Initial value D7 D6 D5 D4 D3 D2 D1 D0 XXXXXXXXB R R R R R R R R R : Read only X : Indefinite The input data register (SIDR0/SIDR1) is a register to store receive data. The serial data signal transmitted to the SI0/SI1 pin is converted in the shift register and then stored in the input data register (SIDR0/SIDR1). When the data length is 7 bits long in operation mode 0, bit7 (D7) becomes invalid. When receive data is stored in this register, the reception data full flag bit (RDRF) of the status register (SSR0/SSR1) is set to "1". If the reception interrupt request output is enabled (SSR0/SSR1: RIE="1"), a reception interrupt is output. Read the input data register (SIDR0/SIDR1) when the reception data full flag bit (RDRF) of the status register (SSR0/SSR1) is set to "1". The reception data full flag bit (RDRF) is cleared to "0" when the input data register (SIDR0/SIDR1) is read. When a reception error occurs (one of SSR0/SSR1: PE, ORE, FRE is "1"), data in the input data register (SIDR0/SIDR1) becomes invalid. 280 14.4 UART Registers ■ Output Data Register (SODR0/SODR1) Figure 14.4-6 Output Data Register (SODR0/SODR1) Bit 7 6 5 4 3 2 1 0 Initial value D7 D6 D5 D4 D3 D2 D1 D0 XXXXXXXXB W W W W W W W W W : Write only X : Indefinite When data to be transmitted is written to the output data register (SODR0/SODR1), if transmission is enabled, the send data is transferred to the transmission shift register, converted into serial data, and then transmitted from the serial data output pin (SO0/SO1 pin). When the data length is 7 bits long in operation mode 0, bit7 (D7) becomes invalid. When the transmission data is written to the output data register, the transmission data empty flag bit (TDRE) of the status register (SSR0/SSR1) is cleared to "0". When transfer to the transmission shift register is completed, the status register is set to "1". If the transmission data empty flag bit (TDRE) is "1", the next send data can be written. When the transmission data empty flag bit (TDRE) is set to "1" while the transmission interrupt request output is enabled (SSR0/SSR1: TIE="1"), a transmission interrupt is output. When a transmission interrupt is output, write the next transmission data after the transmission data empty flag bit (TDRE) is set to "1". Note: The output data register (SODR0/SODR1) is a write-only register and the input data register (SIDR0/SIDR1) is a read-only register. These registers are located at the same address, and so the read value is different from the write value. Therefore, instructions that perform a read-modify-write (RMW) operation such as the INC/DEC instruction cannot be used. 281 CHAPTER 14 UART 14.4.5 Communication Prescaler Control Register (CDCR0/ CDCR1) The communication prescaler control register (CDCR0/CDCR1) is a register that controls the division of machine clocks. ■ Communication Prescaler Control Register (CDCR0/CDCR1) The operation clocks of UART can be obtained by dividing machine clocks. UART is designed to obtain certain baud rates for various machine cycles. Output from the communication prescaler is used for the operation clocks of serial I/O. 15 14 13 12 11 10 9 8 MD - - - RESV R/W - - - R/W R/W R/W R/W DIV2 DIV1 DIV0 Initial value 0XXX0000B R/W : Read/write X : Undefined - : Undefined bit Table 14.4-4 Functions of Bits for Communication Prescaler Control Register (CDCR0/CDCR1) No. Bit name bit15 MD: Communication prescaler operation enable bit • • • This bit enables a communication prescaler operation. If this bit is "1", the communication prescaler operates. If this bit is "0", the communication prescaler stops. bit14 bit13 bit12 -: Undefined bit • • When these bits are read, values are undefined. Values set to these bits do not affect operation. bit11 RESV: Reservation bit • Always set "0". bit10 bit9 bit8 DIV2 to DIV0: Frequency division ratio setting bit • • These bits are used to set the frequency division ratio of the machine clock. For the set values, see Table 14.4-5 "Machine Clock Division Ratio". 282 Function 14.4 UART Registers Table 14.4-5 Machine Clock Division Ratio MD DIV2 DIV1 DIV0 div 0 - - - Stopped 1 0 0 0 1 1 0 0 1 2 1 0 1 0 3 1 0 1 1 4 1 1 0 0 5 1 1 0 1 6 1 1 1 0 7 1 1 1 1 8 div: Machine clock division ratio Note: If a division ratio is changed, wait two time cycles as clock stabilization time before starting communication. The CDCR0 is a prescaler for the UART channel 0 (also serve as the serial I/O channel 2). The CDCR1 is a prescaler for the UART channel 1 (also serve as the serial I/O channel 3). 283 CHAPTER 14 UART 14.5 UART Interrupts UART uses both reception and transmission interrupts and outputs an interrupt request for either of the following causes: • A reception interrupt is output when receive data is set to the input data register (SIDR0/SIDR1) or a reception error occurs. • A transmission interrupt is output when send data is transferred from the output data register (SODR0/SODR1) to the transmission shift register. The extended intelligent I/O service (EI2OS) is available for these interrupts. ■ UART Interrupts Table 14.5-1 Interrupt Control Bits and Interrupt Causes of UART Reception/ transmission Reception Transmission Operation mode Interrupt request flag bit 0 1 2 RDRF O O O Loading receive data into buffers (SIDR0/1) ORE O O O Overrun error FRE O O X Framing error PE O X X Parity error O Send data transfer from the output data register (SODR0/SODR1) completed TDRE O O Interrupt cause Interrupt cause enable bit When interrupt request flag is cleared Receive data is read. SSR0/SSR1: RIE 0 is written to the reception error flag clear bit (SCR0/ 1:REC). SSR0/ SSR1:TIE Transmission data is written O: Used X: Not used ❍ Reception Interrupt In reception mode, "1" is set to the reception data full flag bit (RDRF) or one of the reception error flag bits (ORE, FRE, PE) in the status register (SSR0/SSR1) when data reception is completed, or an overrun error, framing error, or parity error occurs. If the reception interrupt is enabled (SSR0/SSR1: RIE="1"), a reception interrupt request is output. The reception data full flag bit (RDRF) of the status register (SSR0/SSR1) is cleared to "0" when the input data register (SIDR0/SIDR1) is read. All reception error flag bits (PE, ORE, FRE) of the status register (SSR0/SSR1) are cleared to "0" when the reception error flag clear bit (REC) of the status register (SCR0/SCR1) is set to "0". ❍ Transmission Interrupt The transmission data empty flag bit (TDRE) of the status register (SSR0/SSR1) is set to "1" when send data is transferred from the output data register (SODR0/SODR1) to the transfer shift register. If the transmission interrupt is enabled (SSR0/SSR1: TIE="1"), a transmission interrupt request is output. 284 14.5 UART Interrupts ■ UART Interrupts and EI2OS Table 14.5-2 UART Interrupts and EI2OS Interrupt cause UART0 reception interrupt Interrupt number Interrupt control register Register name Address #35(23H) ICR12 Vector table address EI2OS Lower Upper Bank FFFF70H FFFF71H FFFF72H 0000BCH UART0 transmission interrupt #36(24H) FFFF6CH FFFF6DH FFFF6EH UART1 reception interrupt #39(27H) FFFF60H FFFF61H FFFF62H FFFF5CH FFFF5DH FFFF5EH ICR14 UART1 transmission interrupt #40(28H) 0000BEH : Provided with a function that detects a UART reception error and stops El2OS : Usable when interrupt causes that share the ICR12 and ICR14 or the interrupt vectors are not used ■ UART EI2OS Functions UART has a circuit for operating EI2OS, which can be started up for either reception or transmission interrupts. ❍ For Reception EI2OS can be used regardless of the status of other resources. ❍ For Transmission UART shares the interrupt registers (ICR14) with the UART reception interrupts. Therefore, EI2OS can be started up only when no UART reception interrupts are used. 285 CHAPTER 14 UART 14.5.1 Reception Interrupt Generation and Flag Set Timing The following are reception interrupt causes: completion of reception (SSR0/SSR1: RDRF="1") and occurrence of a reception error (one of SSR0/SSR1: PE, ORE, and FRE is "1"). ■ Reception Interrupt Generation and Flag Set Timing Receive data is stored in the input data register (SIDR0/SIDR1) and the reception data full flag bit (RDRF) of the status register (SSR0/SSR1) is set to "1" when a stop bit is detected (in operation mode 0 or 1) or the last bit of data (D7) is detected (in operation mode 2). When a reception error occurs, one of the reception error flags (PE, ORE, FRE) is set to "1". If any of the reception error flag bits in each operation mode is set to "1", the value contained in the input data register (SIDR0/SIDR1) becomes invalid. ❍ Operation Mode 0 (Asynchronous, Normal Mode) The reception data full flag bit (RDRF) of the status register (SSR0/SSR1) is set to "1" when a stop bit is detected. If a reception error is detected, "1" is set to one of the reception error flag bits (PE, ORE, FRE). ❍ Operation Mode 1 (Asynchronous, Multiprocessor Mode) The reception data full flag bit (RDRF) of the status register (SSR0/SSR1) is set to "1" when a stop bit is detected. If a reception error is detected, "1" is set to either of the reception error flag bits (ORE, FRE). Parity errors cannot be detected. ❍ Operation Mode 2 (Synchronous, Normal Mode) The reception data full flag bit (RDRF) of the status register (SSR0/SSR1) is set to "1" when the last bit (D7) of receive data is detected. If a reception error is detected, "1" is set to the reception error flag bit (ORE). Parity and framing errors cannot be detected. Figure 14.5-1 Reception Operation and Flag Set Timing Receive data (operation mode 0) ST D0 D1 D5 D6 D7/P SP Receive data (operation mode 1) ST D0 D1 D6 D7 A/D SP D0 D1 D4 D5 D6 D7 Receive data (operation mode 2) PE, ORE, FRE* RDRF A reception interrupt occurs. * : The PE flag cannot be used in mode 1. The PE and PRE flags cannot be used in mode 2. ST : Start bit SP : Stop bit A/D : Mode 2 (multiprocessor mode) address/data selection bit 286 14.5 UART Interrupts ❍ Reception Interrupt Output Timing When the reception data full flag bit (RDRF) of the status register (SSR0/SSR1) or the one of the reception error flag bits (PE, ORE, FRE) is set to "1" while the reception interrupt is enabled (SSR0/SSR1: RIE="1"), a reception interrupt request is output. 287 CHAPTER 14 UART 14.5.2 Transmission Interrupt Generation and Flag Set Timing A transmission interrupt is output when the output data register (SODR0/SODR1) is ready to accept writing of the next data item. ■ Transmission Interrupt Output and Flag Set Timing The transmission data empty flag bit (TDRE) of the status register (SSR0/SSR1) is set to "1" when data written to the output data register (SODR0/SODR1) is transferred to the transmission shift register and the next piece of data is ready to be written. The transmission data empty flag bit (TDRE) is cleared to "0" when send data is written to the output data register (SODR0/ SODR1). Figure 14.5-2 Transmission Operation and Flag Set Timing A transmission interrupt occurs. [Operation modes 0 and 1] A transmission interrupt occurs. SODR writing TDRE SOT0/1 output ST D0 D1 D2 A transmission interrupt occurs. D3 D4 D5 D6 SP D7 A/D SP ST D0 D1 D2 D3 A transmission interrupt occurs. [Operation modes 2] SODR writing TDRE SOT0/ output D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 : Start bit ST D0 to D7: Data bit : Stop bit SP : Address/data selection bit A/D ❍ Transmission Interrupt Request Output Timing When the transmission data empty flag bit (TDRE) of the status register (SSR0/SSR1) is set to "1" while the transmission interrupt is enabled (SSR0/SSR1: TIE="1"), a transmission interrupt request is output. Note: Because the transmission data empty flag bit (TDRE) of the status register (SSR0/SSR1) is set to "1" in the initial state, a transmission interrupt request is output when the transmission interrupt is enabled (SSR0/SSR1: TIE="1"). The transmission data empty flag bit (TDRE) is a read-only bit. Accordingly, the only way to clear it is to write new data to the output data register (SODR0/SODR1). Specify carefully the timing for enabling a transmission interrupt. 288 14.6 UART Baud Rates 14.6 UART Baud Rates One of the following can be selected as the UART transmitting/receiving block: • Dedicated baud rate generator • Internal clock (16-bit reload timer 0) • External clock (clock input to the SCK pin) ■ UART Baud Rate Selection The baud rate selection circuit is designed as shown below. One of the following three types of baud rates can be selected: ❍ Baud Rates Determined Using the Dedicated Baud Rate Generator UART has an internal dedicated baud rate generator. One of six baud rates can be selected using the mode control register (SMR0/1). An asynchronous or clock synchronous baud rate is selected using the machine clock and CS2 to CS0 bits of the mode control register (SMR0/1). ❍ Baud Rates Determined Using the Internal Timer The internal clock supplied from 16-bit reload timer is used as is (synchronous) or by dividing it by 16 (asynchronous) for the baud rate. Any baud rate can be set by setting the reload value. ❍ Baud Rates Determined Using the External Clock The clock input from the UART clock input pin (SCK) is used as is as the baud rate in synchronous mode or as the divide-by-16 input clock in asynchronous mode. Note, however, that the frequency of the input external clock must be 2 MHz or less. 289 CHAPTER 14 UART Figure 14.6-1 Baud Rate Selection Circuit SMR0/SMR1 : CS2 to CS0 (clock selection bits) [Dedicated baud rate generator] Clock selector 4 Frequency divider (Synchronous) Selects one of 1/2, 1/4, and 1/8. (Asynchronous) Selects the internal fixed division ratio. 0 : φ/4 φ When the bits are 000B to 100B 1 : φ/5 Prescaler [Internal clock] TMCR : CSL, CSL0 2 Clock selector φ When the bits are 110B Down counter UF 1/1 (synchronous) 1/16 (asynchronous) φ/21 φ/2 3 φ/2 5 Prescaler 16-bit reload timer 0 [External clock] When the bits are 111B 1/1 (synchronous) 1/16 (asynchronous) Pin SMR0/SMR1 : MD1 (Clock synchronous/asynchronous selection) φ : Machine clock 290 Baud rate 14.6 UART Baud Rates 14.6.1 Baud Rates Determined Using the Dedicated Baud Rate Generator This section describes the baud rates that can be set when the clock from the dedicated baud rate generator is selected as the UART transfer clock. ■ Baud Rates Determined Using the Dedicated Baud Rate Generator When the clock setting bits of the mode register (SMR0/SMR1) are set to "000B-101B", the baud rate is set by the dedicated baud rate generator. When the transfer clock is generated by the dedicated baud rate generator, the machine clock is divided by the machine clock prescaler and then divided by using the transfer clock division ratio set by the clock selector. The machine clock division ratios are common to the asynchronous and synchronous baud rates, but the transfer clock division ratio is set by the clock setting bits (CS2 to CS0) of the mode register (SMR0/SMR1) separately for the asynchronous and synchronous baud rates. The actual transfer ratio can be calculated by using the following formulas: asynchronous baud rate = φ / (prescaler division ratio) / (asynchronous transfer clock division ratio) synchronous baud rate = φ / (prescaler division ratio) / (synchronous transfer clock division ratio) φ : Machine clock frequency ❍ Division Ratios for the Prescaler (Common to Asynchronous and Synchronous Baud Rates) As listed in Table 14.6-1 "Setting of Each Division Ratio by the Machine Clock Prescaler", the machine clock division ratio is set by the division ratio setting bits (DIV2 to DIV0) of the communication prescaler control register (CDCR0/CDCR1). Table 14.6-1 Setting of Each Division Ratio by the Machine Clock Prescaler MD DIV2 DIV1 DIV0 div 0 - - - Stopped 1 0 0 0 1 1 0 0 1 2 1 0 1 0 3 1 0 1 1 4 1 1 0 0 5 1 1 0 1 6 1 1 1 0 7 1 1 1 1 8 div: Machine clock division ratio 291 CHAPTER 14 UART ❍ Synchronous Transfer Clock The synchronous baud rate is set, as listed in Table 14.6-2 "Synchronous Baud Rate Division Ratio Setting", by the clock setting bits (CS2 to CS0) of the mode register (SMR0/SMR1). Table 14.6-2 Synchronous Baud Rate Division Ratio Setting CS2 CS1 CS0 Division ratio for CLK synchronization Calculation formula SC0/SC1 0 0 0 16 Mbps (φ / div)/1 (φ / div)/1 0 0 1 8 Mbps (φ / div)/2 (φ / div)/2 0 1 0 4 Mbps (φ / div)/4 (φ / div)/4 0 1 1 2 Mbps (φ / div)/8 (φ / div)/8 1 0 0 1 Mbps (φ / div)/16 (φ / div)/16 1 0 1 500 kbps (φ / div)/32 (φ / div)/32 This calculation assumes a machine cycle frequency φ = 16 MHz and div = 4. ❍ Asynchronous Transfer Clock Division Ratios Asynchronous baud rates is selected using the CS2 to CS0 bits of the mode control register (SMR0/1) as listed in Table 14.6-3 "Asynchronous Baud Rate Division Ratio Setting". Table 14.6-3 Asynchronous Baud Rate Division Ratio Setting CS2 CS1 CS0 Asynchronus (start-stop synchronization) Calculation formula SC0/SC1 0 0 0 76,923 bps (φ / div)/(8 x 13 x 2) (φ / div)/(13 x 1) 0 0 1 38,461 bps (φ / div)/(8 x 13 x 4) (φ / div)/(13 x 2) 0 1 0 19,230 bps (φ / div)/(8 x 13 x 8) (φ / div)/(13 x 4) 0 1 1 9,615 bps (φ / div)/(8 x 13 x 16) (φ / div)/(13 x 8) 1 0 0 500 kbps (φ / div)/(8 x 2 x 2) (φ / div)/2 1 0 1 250 kbps (φ / div)/(8 x 2 x 4) (φ / div)/4 However, the baud rate is calculated based on the values of φ (machine clock) = 16MHz and div (machine clock division ratio) = 1. 292 14.6 UART Baud Rates 14.6.2 Baud Rates Determined Using the Internal Timer This section describes the settings used when the internal clock supplied from 16-bit reload timer is selected as the UART transfer clock. It also shows the baud rate calculation formulas. ■ Baud Rates Determined Using the Internal Timer (16-bit Reload Timer 0) If the clock setting bits (CS2 to CS0) of the mode register (SMR0/SMR1) are set to "110B", the baud rate is set by the internal clock. The baud rate can be set by specifying the prescaler division ratio and reload value of the 16-bit reload timer. Figure 14.6-2 Baud Rate Selection Circuit for the Internal Timer (16-bit Reload Timer 0) SMR0/SMR1 : CS2 to CS0 = "110B" (Selects the internal timer.) Clock selector 16-bit reload timer output (the frequency is specified with a prescaler division ratio and reload value.) 1/1 (synchronous) 1/16 (asynchronous) Baud rate SMR0/SMR1 : MD1 (Clock synchronous/asynchronous selection) ❍ Baud Rate Calculation Formulas Asynchronous baud rate = (φ / N)/(16x2x (n+1)) bps Synchronous baud rate = (φ / N)/(2x (n+1)) bps φ: Machine clock N: Division ratio for the prescaler of 16-bit reload timer 0 (21, 23, or 25) n: Reload value for 16-bit reload timer 0 (0 to 65535) 293 CHAPTER 14 UART ❍ Examples of Setting Reload Values (Machine Clock: 7.3728 MHz) Table 14.6-4 Baud Rates and Reload Values Reload value (n) Baud rate Clock asynchronous (start-stop synchronization) Clock synchronous N=21(machine cycle divided by 2) N=23 (machine cycle divided by 8) N=21(machine cycle divided by 2) N=23 (machine cycle divided by 8) 38400 2 - 47 11 19200 5 - 95 23 9600 11 2 191 47 4800 23 5 383 95 2400 47 11 767 191 1200 95 23 1535 383 600 191 47 3071 767 300 383 95 6143 1535 N: Division ratio for the prescaler of 16-bit reload timer 0 -: Setting not allowed 294 14.6 UART Baud Rates 14.6.3 Baud Rates Determined Using the External Clock This section describes the settings used when the external clock is selected as the UART transfer clock. It also shows the baud rate calculation formulas. ■ Baud Rates Determined Using the External Clock The following three settings are required to select the baud rate determined by using the external clock: • Write 111B to the CS2 to CS0 bits of the mode control register (SMR0/1) to select the baud rate determined by using the external clock input. • Set the SC pin to be used as an input port. • Write 0 to the SCKE bit of the mode control register (SMR0/1) to set the pin as an external clock input pin. As shown in Figure 14.6-3 "Baud Rate Selection Circuit for the External Clock", a baud rate is selected using the external clock input from the SC pin. To change the baud rate, the external input clock cycle must be changed because the internal division ratio is fixed. Figure 14.6-3 Baud Rate Selection Circuit for the External Clock SMR0/SMR1 : CS2 to CS0="111B" (Select the external clock.) Clock selector SC 1/1 (synchronous) 1/16 (asynchronous) Pin Baud rate SMR0/SMR1 : MD1 (Synchronous/asynchronous selection) ❍ Baud Rate Calculation Formulas asynchronous baud rate = f/16 bps synchronous baud rate = f bps f: External clock (up to 2 MHz) 295 CHAPTER 14 UART 14.7 Operation of UART UART operates in operation modes 0 and 2 for normal bidirectional serial communication and in operation mode 1 for master-slave communication. ■ Operation of UART ❍ Operation modes There are three UART operation modes: modes 0 to 2. As listed in Table 14.7-1 "UART Operation Mode", an operation mode can be selected according to the inter-CPU connection method and data transfer mode. Table 14.7-1 UART Operation Mode Data length When parity is enabled When parity is disabled Operation mode Synchronization mode 0 Normal mode 7 or 8 bits Asynchronous 1 Multiprocessor mode 8+1*1 - Asynchronous 2 Normal mode 8 - Synchronous Stop bit length 1 or 2 bits*2 None -: Setting not possible *1: "+1" indicates the address/data selection bit (A/D) for communication control. *2: During reception, only one stop bit can be detected. Note: Operation mode 1 of UART is used only from the master system during master-slave connection. ❍ Inter-CPU Connection Method One-to-one connection (normal mode) and master-slave connection (multiprocessor mode) can be selected. For either connection method, the data length, whether to enable parity, and the synchronization method must be common to all CPU. Select an operation mode as follows: • In the one-to-one connection method, operation mode 0 or 2 must be used in the two CPUs. Select operation mode 0 for asynchronous transfer mode and operation mode 2 for synchronous transfer mode. • Select operation mode 1 for the master-slave connection method and use it from the master system. Select "When parity is disabled" for this connection method. ❍ Synchronization Method Asynchronous mode (start-stop synchronization) or clock synchronous mode can be selected in any operation mode. 296 14.7 Operation of UART ❍ Signal Method UART can treat data only in non-return to zero (NRZ) format. ❍ Operation Enable UART controls both transmission and reception using the control register (SCR0/SCR1) with its transmission enable bit (TXE) and reception enable bit (RXE). If any of the operations is disabled during operation, the following will occur: • If reception operation is disabled during reception (data is input to the reception shift register), finish frame reception and store the received data in the input data register (SIDR0/ 1). Then stop the reception operation. • If the transmission operation is disabled during transmission (data is output from the transmission shift register), wait until there is no data in the output data register (SODR0/1) before stopping the transmission operation. • When mode 1 is selected for URAT, the received data bit 9 is ignored. 297 CHAPTER 14 UART 14.7.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) When UART is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), asynchronous transfer mode is selected. ■ Operation in Asynchronous Mode ❍ Transfer Data Format Transfer data always starts with the start bit ("L" level) and ends with the stop bit ("H" level). The data of the specified data bit length is transferred in "LSB first." • In operation mode 0, data without a parity bit is always seven bits long and data with a parity bit is always eight bits long. • In operation mode 1, the data is fixed to eight bits with an address/data setting bit (A/D) bit instead of a parity bit. Figure 14.7-1 Transfer Data Format (Operation Modes 0 and 1) [Operation mode 0] ST D0 D1 D2 D3 D4 D5 D6 * D7/P SP [Operation mode 1] ST D0 D1 D2 D3 D4 D5 D6 D7 A/D SP * : D7(bit7)........When no parity bit is added P(parity)........When a parity bit is added ST : Start bit SP : Stop bit A/D : Address/data setting bit of operation mode 1 (multiprocessor mode) ❍ Transmission Operation When the transmission data empty flag bit (TDRE) of the status register (SSR0/SSR1) is set to "1", send data is written to the output data register (SODR0/SODR1). If the transmission is enabled (SCR0/SCR1: TXE="1"), data is sent. When the send data is transferred to the transmission shift register and transmission is started, the transmission data empty flag bit (TDRE) of the status register (SSR0/SSR1) is set to "1" again so that the next piece of send data can be set. If the transmission interrupt request output is enabled (SSR0/SSR1: TIE="1"), a transmission interrupt request is output so that send data is set to the output data register (SODR0/SODR1). The transmission data empty flag bit (TDRE) is cleared to "0" after writing the send data to the output data register (SODR0/SODR1). 298 14.7 Operation of UART ❍ Reception Operation If the reception is enabled (SCR0/SCR1: RXE="1"), reception operation is always performed. When a start bit is detected, one frame of data is received in accordance with the data format specified in the control register (SCR0/SCR1). When reception of one frame is completed, if a reception error occurs, one of the reception error flag bits (PE, ORE, FRE) of the status register (SSR0/SSR1) is set to "1" and then the reception data full flag bit (RDRF) is set to "1". If the reception interrupt request output is enabled (SSR0/SSR1: RIE="1"), a reception interrupt request is output. Check each of the reception error flag bits (PE, ORE, FRE) of the status register (SSR0/SSR1). If no error occurred in reception, read the input data register (SIDR0/ SIDR1). If an error has occurred, take the appropriate measures to deal with the error. The reception data full flag bit (RDRF) is cleared to "0" after reading receive data from the input data register (SIDR0/SIDR1). ❍ Stop Bit One or two stop bits can be set for transmission. The receiving side always evaluates the first one bit. ❍ Error Detection • In operation mode 0, parity, overrun, and framing errors can be detected. • In operation mode 1, overrun and framing errors can be detected, but parity errors cannot be detected. ❍ Parity Parity can be used only in operation mode 0. The parity presence/absence can be set in the parity enable bit (PEN) of the control register (SCR0/SCR1) and even parity/odd parity can be set in the parity setting bit (P). Parity cannot be used in operation mode 1. Figure 14.7-2 Transmission Data when Parity is Enabled SI1 ST SP 1 0 1 1 0 0 0 SO1 ST A parity error occurred when receiving data with even parity (SCR1: P="0") SP Transmission with even parity (SCR1: P="0") SP Transmission with odd parity (SCR1: P="1") 1 0 1 1 0 0 1 SO1 ST 1 0 1 1 0 0 0 Data Parity ST: Start bit SP: Stop bit Note: Parity cannot be used in operation modes 1 and 2. 299 CHAPTER 14 UART 14.7.2 Operation in Synchronous Mode (Operation Mode 2) When UART is used in operation mode 2 (normal mode), the synchronous transfer mode is selected. ■ Operation in Synchronous Mode (Operation Mode 2) ❍ Transfer Data Format In synchronous mode, 8-bit data is transferred in LSB first mode. Figure 14.7-3 Transfer Data Format (Operation Mode 2) Transmission data writing Mark level Transmission/reception clock RXE, TXE Send/receive data 1 LSB 0 1 1 0 0 Data 1 0 MSB ❍ Clock Supply In clock synchronous (I/O extended serial) mode, as many clocks as the number of transmission/reception bits need to be supplied. • If the internal clock is selected, a data reception synchronous clock is generated when data is received. • If an external clock is selected, a clock for exactly one byte needs to be supplied from an external source after making sure that the output data register (SODR0/SODR1) on the sending side UART contains data (SSR0/SSR1: TDRE="0"). The mark level "H" must be retained before transmission starts and after it is completed. ❍ Error Detection Only overrun errors can be detected, and parity and framing errors cannot be detected. ❍ Initialization The following shows the values to be set to use synchronous mode: [Mode register (SMR0/SMR1)] MD1, MD0: Set "10B". CS2, CS1, CS0: Specify the clock input of the clock selector. SCKE: Set "1" for the dedicated baud rate generator or the internal clock. Set "0" for the clock output or an external clock. SOE: Set "1" for transmission. Set "0" for reception. 300 14.7 Operation of UART [Control register (SCR0/SCR1)] PEN: Set "0". P, SBL, A/D: These bits make no sense. CL: Set "1" (8-bit data). REC: Set "0" (Clear all error flags for initialization). RXE, TXE: Set "1" to either of the bits. [Status register (SSR0/SSR1)] RIE: Set "1" to use interrupts and "0" to not use interrupts. TIE: Set "1" to use interrupts and "0" to not use interrupts. ❍ Communication Start Write data to the output data register (SODR0/SODR1) start communication. Note that the receiving side must also write send data to the output data register (SODR0/SODR1) to start communication. ❍ Communication End The reception data full flag bit (RDRF) of the status register (SSR0/SSR1) is set to "1" when transmission or reception of one frame of data is completed. When receiving data, check the overrun error flag bit (ORE) to see if the communication has been normally executed. 301 CHAPTER 14 UART 14.7.3 Bidirectional Communication Function (Normal Mode) In operation mode 0 or 2, serial bidirectional communication (one-to-one connection) is available. Select operation mode 0 for asynchronous communication and operation mode 2 for synchronous communication. ■ Bidirectional Communication Function The settings shown in Figure 14.7-4 "Settings for UART1 Operation Mode 0" are required to operate UART1 in normal mode (operation mode 0 or 2). Figure 14.7-4 Settings for UART1 Operation Mode 0 Bit SCR1, SMR1 Mode 0 Mode 2 SSR1,SIDR0/SIDR1 15 14 13 12 11 PEN P SBL CL AD REC RXE TXE MD1 MD0 CS2 CS1 CS0 0 1 PE 10 9 8 0 0 ORE FRE RDRFTDRE BDS RIE 7 6 0 1 TIE 5 4 0 0 3 2 - 1 0 SCKE SOE - Set conversion data (during writing). Retain receive data (during reading). Mode 0 Mode 2 DDR : : 1 : 0 : : bit used Bit not used Set 1. Set 0. Set 0 to use an input pin. ❍ Inter-CPU Connection As shown in Figure 14.7-5 "Connection Example of UART1 Bidirectional Communication", interconnect two CPU. Figure 14.7-5 Connection Example of UART1 Bidirectional Communication SO SO SI SC SI Output CPU-1 Input SC CPU-2 ❍ Communication Procedure Communication starts from the transmitting system when transmission data has been prepared. An ANS is returned periodically (byte by byte in this example) when the receiving system receives transmission data. 302 14.7 Operation of UART Figure 14.7-6 Example of Bidirectional Communication Flowchart (Transmitting system) (Receiving system) Start Start Set operation mode (0 or 2) Set operation mode (same mode as that for the transmitting side) Set 1-byte data in SODR and perform communication Data transmission NO Any received data? YES NO Any received data? Read and process received data. YES Read and process received data. Data transmission Transmit 1-byte data (ANS) 303 CHAPTER 14 UART 14.7.4 Master-slave Communication Function (Multiprocessor Mode) With UART, communication with multiple CPU connected in master-slave mode is available. However, UART can be used only from the master system. ■ Master-slave Communication Function The settings shown in Figure 14.7-7 "Settings for UART1 Operation Mode 1" are required to operate UART1 in multiprocessor mode (operation mode 1). Figure 14.7-7 Settings for UART1 Operation Mode 1 Bit SCR1, SMR1 15 14 13 12 11 PEN P SBL CL AD REC RXE TXE MD1 MD0 CS2 CS1 CS0 0 SSR1, SIDR1, SODR1 10 1 9 8 0 PE ORE FRE RDRF TDRE BDS RIE 7 6 0 TIE 5 4 3 2 - 1 1 0 SCKE SOE 0 Set transmission data (during writing). Retain receive data (during reading). DDR : : 1 : 0 : : Bit used Bit not used Set 1. Set 0. Set 0 to use an input pin. ❍ Inter-CPU Connection As shown in Figure 14.7-8 "Connection Example of UART1 Master-Slave Communication", a communication system consists of one master CPU and multiple slave CPU connected to two communication lines. UART1 can be used only from the master CPU. Figure 14.7-8 Connection Example of UART1 Master-Slave Communication SO SI Master CPU SO SI Slave CPU #0 304 SO SI Slave CPU #1 14.7 Operation of UART ❍ Function Selection Select the operation mode and data transfer mode for master-slave communication as shown in Table 14.7-2 "Selection of the Master-Slave Communication Function". Table 14.7-2 Selection of the Master-Slave Communication Function Operation mode Master CPU Slave CPU Parity Synchronization method Stop bit A/D="1" + 8-bit address Address transmission and reception Operation mode 1 Data - Data transmission and reception None Asynchronous 1 or 2 bits A/D="0" + 8-bit address ❍ Communication Procedure When the master CPU transmits address data, communication starts. The A/D bit in the address data is set to 1, and the communication destination slave CPU is selected. Each slave CPU checks the address data using a program. When the address data indicates the address assigned to a slave CPU, the slave CPU communicates with the master CPU (ordinary data). 305 CHAPTER 14 UART Figure 14.7-9 Master-Slave Communication Flowchart (Master CPU) Start Set operation mode to 1 Set SIN pin as the serial data input pin Set 1-byte data for selecting the slave CPU (address data) in D0 to D7,and transmit data (A/D = 1) Set 0 in A/D Enable reception operation Communicate with slave CPU Is communication complete? NO YES Communicating with another slave CPU? NO YES Disable reception operation End 306 14.8 Notes on Using UART 14.8 Notes on Using UART Notes on using UART are given below. ■ Notes on Using UART ❍ Enabling Operations UART has the transmission enable bit (TXE) and reception enable bit (RXE) in the control register (SCR0/SCR1). Both transmission and reception operations need to be enabled before starting transfer because the transmission/reception enable bits (TXE/RXE) are set to "0" in the initial state. The transfer can also be canceled by disabling the transmission/reception as required. ❍ Communication Mode Setting Set the communication mode while the system is not operating. If the mode is set during transmission or reception, the transmission or reception data is not guaranteed. ❍ Synchronous Mode UART clock synchronous mode (operation mode 2) uses clock control (I/O extended serial) mode, in which start and stop bits are not added to the data. ❍ Transmission Interrupt Enabling Timing The default (initial value) of the transmission data empty flag bit (SSR0/1: TDRE) is 1 (no transmission data and transmission data write enable state). A transmission interrupt request is generated as soon as the transmission interrupt requests are enabled (SSR0/1: TIE=1). Be sure to set the TIE flag to 1 after setting the transmission data. ❍ Reception in Operation Mode 1 (Multiprocessor Mode) In operation mode 1 (multiprocessor mode) of UART, the 9-bit receive operation cannot be performed. 307 CHAPTER 14 UART 308 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT This chapter describes the functions and operations of the DTP/external interrupt circuit of the MB90M405 series. 15.1 "Overview of the DTP/External Interrupt Circuit" 15.2 "Configuration of the DTP/External Interrupt Circuit" 15.3 "DTP/External Interrupt Circuit Pins" 15.4 "DTP/External Interrupt Circuit Registers" 15.5 "Operation of the DTP/External Interrupt Circuit" 15.6 "Usage Notes on the DTP/External Interrupt Circuit" 309 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.1 Overview of the DTP/External Interrupt Circuit The data transfer peripheral (DTP)/external interrupt circuit detects interrupt request input from an external interrupt input pin in order to generate an interrupt request. ■ DTP/External Interrupt Functions The DTP/external interrupt circuit function outputs an interrupt request when it detects an edge or level signal input to the external interrupt input pins. When an interrupt request is accepted by the CPU and the extended intelligent I/O service (EI2OS) is enabled, the automatic data transfer (DTP function) is performed by EI2OS before branching to the interrupt processing routine. If EI2OS is disabled, the automatic data transfer (DTP function) by EI2OS is not activated; instead, direct branching to the interrupt processing routine takes place. Table 15.1-1 Overview of the DTP/External Interrupt Circuit External interrupt function Input pins DTP function Four (P80/INT0, P81/INT1, PB6/INT2, and PB7/INT3) By using the request level setting register (ELVR), the detection level or edge type can be set for each pin. Interrupt cause Input of the "L" level/"H" level Interrupt number #11 (0BH), #13 (0DH), #16 (10H) Interrupt control The output of interrupt requests is enabled and disabled using the DTP/interrupt enable register (ENIR). Interrupt flag Interrupt causes are stored in the DTP/interrupt cause register (EIRR). Processing selection EI2OS is disabled (ICR: ISE = 0). EI2OS is enabled (ICR: ISE = 1). Processing The circuit branches to an external interrupt processing routine. Branching to the interrupt processing routine after automatic data transfer by EI2OS ICR: Interrupt control register 310 Input of the rising edge/falling edge 15.1 Overview of the DTP/External Interrupt Circuit ■ Interrupt of the DTP/external interrupt circuit and EI2OS Table 15.1-2 Interrupt of the DTP/External Interrupt Circuit and EI2OS Interrupt control register Vector table address Interrupt number Register name Address Lower Upper Bank INT0 #11 (0BH) ICR00 0000B0H FFFFD0H FFFFD1H FFFFD2H INT1 #13 (0DH) ICR01 0000B1H FFFFC8H FFFFC9H FFFFCAH #16 (10H) ICR02 0000B2H FFFFBCH FFFFBDH FFFFBEH Channel EI2OS O INT2 INT3 311 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.2 Configuration of the DTP/External Interrupt Circuit The DTP/external interrupt circuit consists of the following blocks: • DTP/interrupt input detection circuit • Request level setting register (ELVR) • DTP/interrupt cause register (EIRR) • DTP/interrupt enable register (ENIR) ■ Block Diagram of the DTP/External Interrupt Circuit Figure 15.2-1 Block Diagram of the DTP/External Interrupt Circuit Request level setting register (ELVR) - - - - - - - - LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 Selector Pin INT0 Selector Pin INT1 Selector Pin Internal data bus INT2 Pin Selector INT3 - - - - ER3 ER2 ER1 ER0 Interrupt request - 312 - - - EN3 EN2 EN1 EN0 15.2 Configuration of the DTP/External Interrupt Circuit ❍ DTP/external interrupt input detection circuit Upon detecting a match of the signal input to an external interrupt input pin and the level or edge specified in the request level setting register (ELVR), the DTP/external interrupt cause flag bit (EIRR: ER3 to ER0) corresponding to the external interrupt input pin is set to "1". ❍ Request level setting register (ELVR) This register sets the detection condition (level or edge) of interrupt requests for each external interrupt input pin. ❍ DTP/interrupt cause register (EIRR) This register retains and clears interrupt causes. ❍ DTP/interrupt enable register (ENIR) This register enables/disables interrupt requests for each external interrupt input pin. 313 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.3 DTP/External Interrupt Circuit Pins This section describes the DTP/external interrupt circuit pins and provides a pin block diagram. ■ DTP/External Interrupt Circuit Pins The DTP/external interrupt circuit pins are also used as I/O ports. Table 15.3-1 DTP/External Interrupt Circuit Pins Pin name INT0 INT1 INT2 INT3 Function Port 8 inputoutput/external interrupt input Port B inputoutput/external interrupt input Pull-up resistor I/O format Standby control Setting required to use pins Set the pin as an input port (DDR8: bit0 = 0) CMOS output/ CMOS hysteresis input Set the pin as an input port (DDR8: bit9 = 0) Not provided Not provided Set the pin as an input port (DDRB: bit16 = 0) Set the pin as an input port (DDRB: bit17 = 0) ■ Block Diagram of the DTP/External Interrupt Circuit Pins Internal data bus Figure 15.3-1 Block Diagram of the DTP/External Interrupt Circuit Pins PDR read PDR PDR write DDR 314 I/O evaluation circuit Input buffer Output buffer Standby control (LPMCR:SPL="1") Port pin 15.4 DTP/External Interrupt Circuit Registers 15.4 DTP/External Interrupt Circuit Registers This section describes lDTP/external interrupt circuit registers. ■ DTP/External Interrupt Circuit register Figure 15.4-1 DTP/External Interrupt Circuit Registers bit15 bit8 bit7 DTP/interrupt cause register (EIRR) bit0 DTP/interrupt enable register (ENIR) Request level setting register (ELVR) 315 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.4.1 DTP/Interrupt Cause Register (EIRR) The DTP/interrupt cause register (EIRR) stores and clears interrupt causes. ■ DTP/Interrupt Cause Register (EIRR) Figure 15.4-2 DTP/Interrupt Cause Register (EIRR) Bit 15 14 13 12 11 - - - - ER3 ER2 ER1 ER0 - - - - R/W R/W R/W R/W ER3 to ER0 R/W : Read/write enabled X : Undefined : Undefined bit 316 0 1 10 9 8 Initial value XXXXXXXX B External interrupt request flag bit Reading Writing Clear interrupt requests No interrupt request No effect on operation Interrupt request present 15.4 DTP/External Interrupt Circuit Registers Table 15.4-1 Function Description of Each Bit of the DTP/Interrupt Cause Register (EIRR) Bit name bit15 to bit12 bit11 ER7: to ER4: ER3: Function • Setting of any of these bits is invalid because the external input pins are INT0 through INT3. • • This bit is a flag that requests an interrupt. This bit is set to "1" when the level or edge signal set in the external interrupt request detection condition setting bit (LB3, LA3) of the request level setting register (ELVR) is detected in the external interrupt input pin (INT3). When this bit is set to "1" while the external interrupt request enable bit (EN3) of the DTP/external interrupt enable register (ENIR) is set to "1", an interrupt request is output. When this bit is "0", the interrupt request is cleared. When this bit is "1", operation is not affected. • • • • • bit10 ER2: • External interrupt request flag bit • • • • bit9 ER1: • • • • • bit8 ER0: • • • This bit is a flag that requests an interrupt. This bit is set to "1" when the level or edge signal set in the external interrupt request detection condition setting bit (LB2, LA2) of the request level setting register (ELVR) is detected in the external interrupt input pin (INT2). When this bit is set to "1" while the external interrupt request enable bit (EN2) of the DTP/external interrupt enable register (ENIR) is set to "1", an interrupt request is output. When this bit is "0", the interrupt request is cleared. When this bit is "1", operation is not affected. This bit is a flag that requests an interrupt. This bit is set to "1" when the level or edge signal set in the external interrupt request detection condition setting bit (LB1, LA1) of the request level setting register (ELVR) is detected in the external interrupt input pin (INT1). When this bit is set to "1" while the external interrupt request enable bit (EN1) of the DTP/external interrupt enable register (ENIR) is set to "1", an interrupt request is output. When this bit is "0", the interrupt request is cleared. When this bit is "1", operation is not affected. This bit is a flag that requests an interrupt. This bit is set to "1" when the level or edge signal set in the external interrupt request detection condition setting bit (LB0, LA0) of the request level setting register (ELVR) is detected in the external interrupt input pin (INT0). When this bit is set to "1" while the external interrupt request enable bit (EN0) of the DTP/external interrupt enable register (ENIR) is set to "1", an interrupt request is output. When this bit is "0", the interrupt request is cleared. When this bit is "1", operation is not affected. Reference: When the extended intelligent I/O service (EI2OS) is activated as a DTP function, the corresponding external interrupt request flag bit (ER3 to ER0) is cleared to "0" when the transfer of one piece of data is completed. 317 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT Note: Reading by read-modify-write type instructions always returns "1". If multiple external interrupt request outputs are enabled (ENIR: EN3 to EN0=1), only the bits for which the CPU accepts an interrupt (bits for which "1" was set in ER3 to ER0) are cleared. No other bits must be cleared unconditionally. 318 15.4 DTP/External Interrupt Circuit Registers 15.4.2 DTP/Interrupt Enable Register (ENIR) The DTP/interrupt enable register (ENIR) enables/disables an external interrupt request for each external interrupt pin (INT7 to INT0). ■ DTP/Interrupt Enable Register (ENIR) Figure 15.4-3 DTP/Interrupt Enable Register (ENIR) Bit 7 6 5 4 - - - - EN3 EN2 EN1 EN0 - - - - R/W R/W R/W R/W X : Undefined R/W : Read/write enabled : Initial value - : Undefined bit 3 2 1 0 Initial value XXXX0000B EN3 to EN0 0 An interrupt request is disabled. 1 An interrupt request is enabled. External interrupt request enable bits Table 15.4-2 Function Description of Each Bit of the DTP/Interrupt Enable Register (ENIR) Bit name bit7 to bit4 bit3 bit2 bit1 bit0 EN7: to EN4: EN3: EN2: EN1: EN0: External Interrupt request enable bit Function • Setting of any of these bits is invalid because the external input pins are INT0 through INT3. • • This bit enables an interrupt request. When the external interrupt request flag bit (ER3) of the DTP/interrupt cause register (EIRR) is set to "1" while this bit is set to "1", an interrupt request is output. • • This bit enables an interrupt request. When the external interrupt request flag bit (ER2) of the DTP/interrupt cause register (EIRR) is set to "1" while this bit is set to "1", an interrupt request is output. • • This bit enables an interrupt request. When the external interrupt request flag bit (ER1) of the DTP/interrupt cause register (EIRR) is set to "1" while this bit is set to "1", an interrupt request is output. • • This bit enables an interrupt request. When the external interrupt request flag bit (ER0) of the DTP/interrupt cause register (EIRR) is set to "1" while this bit is set to "1", an interrupt request is output. 319 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT Reference: To use an external interrupt input pin that also serves as an I/O port, set the bit that also serves the corresponding I/O port of the port direction register (DDR) to "0" to use the pin as an input port. The states of the external interrupt input pins can be read directly using the port data register (PDR) regardless of the states of the external interrupt request enable bits (ENIR: EN3 to EN0). External interrupt request flag bits (ER3 to ER0) of the DTP/interrupt cause register (EIRR) are set to "1" regardless of the values of the external interrupt request enable bits (ENIR: EN3 to EN0) when a DTP/external interrupt request signal is detected. Table 15.4-3 Correspondence between the DTP/Interrupt Control Registers (EIRR and ENIR) and Each Channel DTP/external interrupt pin Interrupt number INT3 INT2 320 #16 (10H) External interrupt request flag bit External interrupt request enable bit ER3 EN3 ER2 EN2 INT1 #13 (0DH) ER1 EN1 INT0 #11 (0BH) ER0 EN0 15.4 DTP/External Interrupt Circuit Registers 15.4.3 Request Level Setting Register (ELVR) The request level setting register (ELVR) sets the detection condition (level or edge) for interrupt requests for each external interrupt input pin. ■ Request Level Setting Register (ELVR) Figure 15.4-4 Request Level Setting Register (ELVR) Bit 15 14 13 12 11 10 9 8 7 6 - - - - - - - - LB3 LA3 - - - - - - - - X : Undefined R/W : Read/write enabled : Initial value - : Undefined bit 5 4 3 2 1 LA1 LB0 0 Initial value (Upper) X X X X 0 0 0 0 B LB2 LA2 LB1 LB7 to LB0 0 LA7 to LA0 0 The L level is to be detected. 0 1 The H level is to be detected. 1 0 A rising edge is to be detected. 1 1 A falling edge is to be detected. LA0 (Lower) X X X X 0 0 0 0 B R/W R/W R/W R/W R/W R/W R/W R/W External interrupt request detection selection bits Table 15.4-4 Function Description of Each Bit of the Request Level Setting Register (ELVR) Bit name Bit15 to bit8 LB7: to LB4: LA7: to LA4: bit7 LB3: bit6 LA3: bit5 LB2: bit4 LA2: bit3 LB1: bit2 LA1: bit1 LB0: bit0 LA0: External interrupt request detection condition setting bit Function • Setting of any of these bits is invalid because the external input pins are INT0 through INT3. • This bit is used to set the detection condition (level or edge) for interrupt requests from the signal input to the external interrupt input pin (INT3). • This bit is used to set the detection condition (level or edge) for interrupt requests from the signal input to the external interrupt input pin (INT2). • This bit is used to set the detection condition (level or edge) for interrupt requests from the signal input to the external interrupt input pin (INT1). • This bit is used to set the detection condition (level or edge) for interrupt requests from the signal input to the external interrupt input pin (INT0). 321 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT Reference: When the detection signal set in the request level setting register (ELVR) is input to an external interrupt input pin, the external interrupt request flag bit (EIRR: ER7 to ER0) of the corresponding pin is set to "1" regardless of the setting in the DTP/interrupt enable register (ENIR). Table 15.4-5 Correspondence between Request Level Setting Register (ELVR) and Each Channel External interrupt input pin Interrupt number LB3, LA3 INT3 INT2 322 Bit name #16 (10H) LB2, LA2 INT1 #13 (0DH) LB1, LA1 INT0 #11 (0BH) LB0, LA0 15.5 Operation of the DTP/External Interrupt Circuit 15.5 Operation of the DTP/External Interrupt Circuit The DTP/external interrupt circuit provides the external interrupt function and the DTP function. This section describes the settings required for each function and the operation of the circuit. ■ Setting the DTP/External Interrupt Circuit Figure 15.5-1 "DTP/External Interrupt Circuit" shows the settings required to operate the DTP/ external interrupt circuit. Figure 15.5-1 DTP/External Interrupt Circuit Bit 15 14 13 12 11 10 9 EIRR /ENIR 6 5 4 3 2 1 0 0 0 For the external interrupt function 1 1 For the DTP function ER3 ER2 ER1 ER0 ELVR : : : 0 : 1 : 7 ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0 ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0 ICR DDR 8 EN3 EN2 EN1 EN0 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 PB7 PB6 P81 P80 Used Set the bit corresponding to the bit used to 1. Set the bit corresponding to the bit used to 0. Specifies 0. Specifies 1. Set the DTP/external interrupt circuit registers in accordance with the following procedure because an interrupt request may be generated erroneously when setting them. 1. Set the DTP/interrupt enable register (ENIR) to "00H" to disable interrupt requests. 2. Set the interrupt detection condition to the external interrupt request detection condition setting bit (LB3 to LB0, LA3 to LA0) corresponding to the external interrupt input pin of the request level setting register (ELVR). 3. Set the external interrupt request flag bit (ER3 to ER0) corresponding to the external interrupt input pin of the DTP/interrupt cause register (EIRR) to "0" to clear the interrupt request. 4. To enable an interrupt request, set the external interrupt request enable bit (EN3 to EN0) corresponding to the external interrupt input pin of the DTP/interrupt enable register (ENIR) to "1". 323 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT ❍ Switching between the external interrupt function and the DTP function Switching between the external interrupt function and the DTP function is set by the EI2OS enable bit (ISE) of the interrupt control register (ICR) corresponding to the interrupt cause to be used. When the EI2OS enable bit (ISE) is set to "1", the extended intelligent I/O service (EI2OS) is enabled, operating as the DTP function. When the EI2OS enable bit (ISE) is set to "0", the extended intelligent I/O service (EI2OS) is disabled, and the register operates as the external interrupt function. ■ Operation of the DTP/External Interrupt Circuit Table 15.5-1 Control Bit and Interrupt Cause of the DTP/External Interrupt Circuit DTP/external interrupt circuit External interrupt request flag bit EIRR: ER3 to ER0 External interrupt request enable bit ENIR: EN3 to EN0 Interrupt cause Input of an effective edge or level to pin INT3 to INT0 The DTP/external interrupt circuit outputs an interrupt request to the interrupt controller when, after operations are set to the request level setting register (ELVR), DTP/interrupt cause register (EIRR), and DTP/interrupt enable register (ENIR), the detection condition set in the request level setting register (ELVR) is input to the corresponding external interrupt input pin. When the EI2OS enable bit (ICR: ISE) of the interrupt control register is "0", interrupt processing is performed. When the EI2OS enable bit (ICR: ISE) of the interrupt control register is "1", interrupt processing is performed after the extended intelligent I/O service processing (DTP processing) is executed. 324 15.5 Operation of the DTP/External Interrupt Circuit Figure 15.5-2 Operation of the DTP/External Interrupt Circuit DTP/external interrupt circuit Another request Interrupt controller ELVR ICR YY EIRR CMP ICR XX ENIR CPU IL CMP ILM Interrupt processing microprogram Cause DTP processing routine (EI2OS activation) Generation of DTP/external interrupt request Transfer data between memory and peripheral Update descriptor Accepted by interrupt controller? Descriptor data counter Accepted by CPU? 0 Execute interrupt processing routine 0 Return from DTP processing Start interrupt processing microprogram ICR : ISE Set again or stop Return from CPU processing 1 0 Start external interrupt routine Clear interrupt flag Return from external interrupt 325 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.5.1 External Interrupt Function The DTP/external interrupt circuit has an external interrupt function that outputs an interrupt request when the input signal is input to an external interrupt input pin. ■ External Interrupt Function When the detection condition (level or edge) set in the request level setting register (ELVR) is input to an external interrupt input pin, the external interrupt request flag bit (ER3 to ER0) corresponding to the pin of the DTP/external interrupt cause register (EIRR) is set to "1". If the external interrupt request enable bit (EN3 to EN0) corresponding to the external interrupt input pin of the DTP/external enable register (ENIR) is set to "1", an interrupt request is output to the interrupt controller. The interrupt controller determines the interrupt level (ICR: IL2 to IL0) of interrupt requests from peripheral functions (resources) and priorities when interrupt requests are output simultaneously. The CPU determines whether to accept an interrupt request based on the interrupt level mask register (PS: ILM) and interrupt enable flag (PS: CCR: I). When the CPU accepts an interrupt request, it performs interrupt processing before branching to the interrupt processing routine. In the interrupt processing program, set the corresponding external interrupt request flag bit (ER3 to ER0) to "0" and clear the interrupt request before returning from the interrupt using an interrupt return instruction. Note: When the interrupt processing program is activated, be sure to set the external interrupt request flag bit (EIRR: EN3 to EN0) that caused the activation to "0". It is not possible to return from an interrupt while the external interrupt request flag bit (EIRR: EN3 to EN0) is set to "1". 326 15.5 Operation of the DTP/External Interrupt Circuit 15.5.2 DTP Function The DTP/external interrupt circuit has a DTP (Data Transfer Peripheral) function that detects the data transfer request signal input to an external interrupt input pin from external peripheral devices and activates the extended intelligent I/O service. ■ Operation of the DTP Function The DTP function is a function for detecting the data transfer request signal input to an external interrupt input pin from external peripheral devices to automatically transfer data between memory and the peripheral devices. The extended intelligent I/O service is activated by the external interrupt function. The operation of the DTP function is the same as that of the external interrupt function until an interrupt request is accepted by the CPU. If the EI2OS operation is enabled (ICR: ISE="1"), EI2OS is activated when an interrupt request is accepted to start data transfer. When the data transfer is completed, the descriptor is updated and the external interrupt request flag bit (EIRR: ER3 to ER0) is cleared to "0" to operate as the external interrupt function again. When the transfer by EI2OS is completed, branching to the interrupt processing routine pointed to by the vector address of the external interrupt occurs. Peripheral devices that are externally connected should remove the cause input of the data transfer request signal (DTP cause) within three machine cycles after the first transfer started. Figure 15.5-3 Example of Interfacing with External Peripheral Devices H-level request (ELVR: LB0, LA0 = "01B") Input to the INT0 pin (DTP external interrupt cause) Internal operation of the CPU (microprogram) Descriptor updating Descriptor selection and reading Address bus pin Read address Data bus pin Read signal Write address Read data Write address Write signal *1 External peripheral Internal data bus Read operation(*1) Register Data transfer request DTP external interrupt cause (*2) INT DTP/external interrupt circuit Interrupt request Write operation (*3) CPU (EI2OS) Internal memory *1 Three machine cycles *2 Must be removed within three machine cycles of transfer. *3 If the extended intelligent I/O service is in peripheral memory transfer mode. 327 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 15.6 Usage Notes on the DTP/External Interrupt Circuit Notes on the signal to be input to the DTP/external interrupt circuit, release from standby mode, and interrupts are given below. ■ Usage Notes on the DTP/External Interrupt Circuit ❍ Conditions for external peripherals using the DTP function To support the DTP function, peripheral devices that are externally connected must be able to automatically clear data transfer requests after transfer is carried out. If an externally connected peripheral device continues to output a transfer request longer than three machine cycles after the CPU started the transfer operation, the DTP/external interrupt circuit interprets the request as another transfer request and performs the data transfer operation again. ❍ Input polarities of external interrupts • If the request level setting register (ELVR) is set for edge detection, the pulse width of at least three machine cycles is required from the point of change of the input level to detect the input of an edge that is to become an interrupt request. • If the request level setting register (ELVR) is set for level detection, and the level for interrupt request is input, the cause flip-flop in the DTP/interrupt cause register (EIRR) is set to "1" and retains the cause, as shown in Figure 15.6-1 "Clearing the Cause Retention Circuit When a Level is Specified". Thus, even if the interrupt cause is removed, the request to the interrupt controller remains active. To cancel the request to the interrupt controller, set the external interrupt request flag bits (EIRR: ER3 to ER0) to "0" to clear the cause flip-flop to "0", as shown in Figure 15.6-2 "DTP/External Interrupt Cause and Interrupt Request When the Output of Interrupt Requests is Enabled". Figure 15.6-1 Clearing the Cause Retention Circuit When a Level is Specified DTP/external interrupt cause DTP/interrupt input detection circuit Cause FF (in the EIRR register) Enable gate The cause is stored until the register is cleared. 328 To the interrupt controller (interrupt request) 15.6 Usage Notes on the DTP/External Interrupt Circuit Figure 15.6-2 DTP/External Interrupt Cause and Interrupt Request When the Output of Interrupt Requests is Enabled DTP/external interrupt cause (when the H level is detected) Removal of the interrupt cause Interrupt request to the interrupt controller Becomes inactive by clearing cause FF. ❍ Notes about interrupts When the external interrupt function is used to branch to an interrupt processing routine, it is not possible to return from the interrupt processing program if an external interrupt request flag bit (EIRR: ER3 to ER0) is "1" and an external interrupt request enable bit (ENIR: EN3 to EN0) is "1". Be sure to clear the external interrupt request flag bits (EIRR: ER3 to ER0) to "0" in the processing program. (When using the DTP function, the external interrupt request flag bits (EIRR: ER3 to ER0) are cleared to "0" by EI2OS.) If the register is set for level detection, it is not possible to return from the interrupt processing program when the level signal of an interrupt request is input to an external interrupt input pin (INT3 to INT0) because, even if an external interrupt request flag bit (EIRR: ER3 to ER0) is set to "0", it is set to "1" again. Thus, disable an interrupt request or remove the level signal for an interrupt request. 329 CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT 330 CHAPTER 16 I2C INTERFACE This chapter describes the functions and operations of the I2C interface of the MB90M405 series. 16.1 "Overview of the I2C Interface" 16.2 "Block Diagram and Configuration of the I2C Interface" 16.3 "I2C Interface Registers" 16.4 "Operation of the I2C Interface" 331 CHAPTER 16 I2C INTERFACE 16.1 Overview of the I2C Interface The I2C interface operates as a master or slave device on the I2C bus at the serial I/O port that supports an inter-IC bus. ■ Features of the I2C Interface MB90M405 series microcontrollers use one channel for the I2C built-in interface. The I2C interface has the following features: 332 • Master/slave transmission • Arbitration function • Clock synchronization function • Function for detecting a slave address and a general call address • Function for detecting the transfer direction • Function for repeated generation and detection of the start condition • Bus error detection function • Support of a transfer rate up to 100 kbps 16.2 Block Diagram and Configuration of the I2C Interface 16.2 Block Diagram and Configuration of the I2C Interface Figure 16.2-1 "Block Diagram of the I2C Interface" shows a block diagram of the I2C interface. Figure 16.2-2 "Configuration of the I2C Interface" shows the configuration of the I2C interface. ■ Block Diagram of the I2C Interface Figure 16.2-1 Block Diagram of the I2C Interface ICCR I2C enable EN Clock division 1 5 6 7 8 ICCR CS4 Clock selection 1 CS3 Clock division 2 2 4 8 16 32 64 128 256 CS2 Internal data bus CS1 CS0 Clock selection 2 IBSR BB RSC Sync Shift clock generation Timing of shift clock edge change Bus busy Repeat start Start and stop condition detection Last Bit LRB TRX Machine clock Error Send/Receive FBT First Byte AL Arbitration lost detection IBCR BER SCL BEIE Interrupt request INTE IRQ SDA INT IBCR SCC MSS ACK GCAA End Start Master ACK enable Start and stop condition generation GC-ACK enable IDAR IBSR AAS GCA Slave Global call Slave address compare IADR 333 CHAPTER 16 I2C INTERFACE ■ Configuration of the I2C Interface Figure 16.2-2 Configuration of the I2C Interface SCL R SDA R Nch I2C interface Nch MB90M405 series 334 External I2C interface 16.3 I2C Interface Registers 16.3 I2C Interface Registers The I2C interface uses the following six types of registers: • I2C status register (IBSR) • I2C control register (IBCR) • I2C clock control register (ICCR) • I2C address register (IADR) • I2C data register (IDAR) • I2C port select register (ISEL) ■ I2C Interface Registers Figure 16.3-1 I2C Interface Registers bit15 bit8 bit7 I2C port select register (ISEL) bit0 I2C status register (IBSR) I2C control register (IBCR) I2C clock control register (ICCR) I2C address register (IADR) I2C data register (IDAR) 335 CHAPTER 16 I2C INTERFACE 16.3.1 I2C Status Register (IBSR) The I2C status register (IBSR) has the following functions: • Detection of a repeated start condition • Detection of arbitration lost • Storage of acknowledgements • Detection of the first byte • Detection of addressing • Detection of the general call address • Data transfer ■ I2C Status Register (IBSR) Figure 16.3-2 I2C Status Register (IBSR) Bit 7 6 5 4 3 2 1 0 Initial value BB RSC AL LRB TRX AAS GCA FBT 00000000B R R R R R R R R FBT 0 First byte detection bit Received byte is not the first byte. 1 Received byte is the first byte. GCA 0 General call address detection bit General call address not received in slave mode 1 General call address received in slave mode AAS 0 Addressing detection bit Addressing in other than slave mode 1 Addressing in slave mode TRX 0 Transfer status setting bit Receiving 1 Sending AL 0 Arbitration lost detection bit Arbitration lost not detected Either arbitration lost occurred during transfer 1 by the master or the MSS bit was set to "1" while another system was using the bus RSC Repeated start condition not detected 1 Repeated start condition detected BB 0 1 R 336 : Read only : Initial value Repeated start condition bit 0 Bus status setting bit Stop condition not detected Start condition detected (indicating that the bus is in use) 16.3 I2C Interface Registers Table 16.3-1 Functions of the I2C Status Register (IBSR) Bits Bit name bit7 BB: Bus status bit bit6 RSC: Repeated start condition detection bit bit5 AL: Arbitration lost detection bit Function • • • This bit shows the I2C bus status. "0" is read from this bit if the stop condition is detected. "1" is read from this bit if the start condition is detected. • • This bit shows whether the repeated start condition is detected. "1" is read from this bit if the start condition is detected again while the bus is in use. This bit is cleared to "0" if the start condition or the stop condition is detected during the bus stop status while the INT bit is set to "0" and addressing is not in slave mode. • • • • This bit shows whether arbitration lost is detected. "1" is read from this bit if arbitration lost has occurred during transfer by the master or if the MSS bit is set to "1" while another system is using the bus. This bit is cleared to "0" if the INT bit is set to "0". bit4 LRB: Acknowledge storage bit • • This bit stores an acknowledgement from the receiving system. This bit is cleared if a start or stop condition is detected. bit3 TRX: Transfer status bit • • • This bit shows the data transfer send or receive status "0" is read from this bit during receiving "1" is read from this bit during sending. bit2 AAS: Address detection bit • • • This bit shows whether addressing is detected. "1" is read from this bit if addressing was in slave mode. This bit is cleared to "0" if the start or stop condition is detected. bit1 GCA: General call address detection bit • • This bit shows whether the general call address (00H) is detected. "1" is read from this bit if the general call address is received in slave mode. This bit is cleared to "0" if the start or stop condition is detected. • • • bit0 FBT: First byte detection bit • This bit shows whether the first byte is detected. Read operations return "1" for this bit if the received byte is the first byte (address data). Even if this bit has been set to "1" due to detection of a start condition, it will be cleared to "0" if the INT bit is set to "0" or addressing was in other than slave mode. 337 CHAPTER 16 I2C INTERFACE 16.3.2 I2C Control Register (IBCR) The I2C control register (IBCR) has the following functions: • Interrupt request and interrupt enable • Generation of the start condition • Setting a system as the master or slave • Enabling of generation of acknowledgements ■ I2C Control Register (IBCR) Figure 16.3-3 I2C Control Register (IBCR) Bit 15 14 13 12 11 10 9 8 BER BEIE SCC MSS ACK GCAA INTE INT R/W R/W R/W R/W 0 1 Transfer end interrupt request flag bit Read Interrupt request enable bit 0 Interrupt requests disabled 1 Interrupt requests enabled GCAA Acknowledgement generation enable bit 0 No acknowledgement generated 1 Acknowledgement generated ACK Acknowledgement generation enable bit 0 No acknowledgement generated 1 Acknowledgement generated MSS Master/slave setting bit 0 Slave mode entered after stop condition is generated and transfer ends Transfer of address data starts after start condition is generated again during transfer by the master 1 SCC Start condition generation bit 0 No effect on operation 1 Start condition generated again during transfer by the master; transfer of address data restarted BEIE Bus error interrupt enable bit 0 Bus error interrupt requests disabled 1 Bus error interrupt requests enabled BER 338 Write Transfer not ended yet Interrupt request cleared After the transfer ends, this bit is No effect on operation set according to the conditions shown in the following table. INTE : Read/write enabled : Initial value 00000000B R/W R/W R/W R/W INT R/W Initial value Bus error interrupt request flag bit Read Write 0 No interrupt request present Interrupt request cleared 1 Interrupt request present No effect on operation 16.3 I2C Interface Registers Table 16.3-2 Functions of the I2C Control Register (IBCR) Bits Bit name Function • • bit15 BER: Bus error interrupt request flag bit • • • bit14 BEIE: Bus error interrupt request enable bit bit13 SCC: Start condition generation bit • • This is a bus error interrupt enable bit. An interrupt is generated if the bus error interrupt request flag bit (BER) is set to "1" while this bit is "1". • • This is a start condition generation bit. If this bit is set to "1", the start condition is generated again during transfer by the master and address data transfer is started. The read value is always "0". • • • bit12 MSS: Master/slave setting bit. This is a bus error interrupt request flag bit. An interrupt request is output if this bit is set to "1" while the bus error interrupt request enable bit (BEIE) is "1". If this bit is set to "1", the EN bit of the CCR register is cleared, the I2C interface is stopped, and data transfer is halted. If this bit is set to "0", the interrupt request is cleared. Setting this bit to "1" does not effect operation. • • • This bit sets either master or slave mode. If this bit is set to "0", slave mode is entered after the stop condition is generated and the transfer ends. If this bit is set to "1", address data transfer is started after master mode is entered and the start condition is generated again. This bit is cleared to "0" and slave mode starts if arbitration lost occurs during transfer by the master. This bit enables generation of an acknowledgement when data is received. If this bit is set to "1", an acknowledgement is generated. This bit is invalid if address data is received in slave mode. bit11 ACK: Acknowledgement generation enable bit GCAA: Acknowledgement generation enable bit • bit10 INTE: Interrupt request enable bit • • This bit enables interrupts. An interrupt is generated if the transfer end interrupt request flag bit (INT) is set to "1" while this bit is set to "1". • • • This is the transmission end interrupt request flag bit. If this bit is set to "1", the SCL line is kept at the "L" level. If this bit is set to "0", the interrupt request is cleared, the SCL line is released, and the next byte is transferred. This bit is cleared to "0" if the start or stop condition is generated in master mode. bit9 bit8 INT: Transfer end interrupt request flag bit • • • • This bit enables generation of an acknowledgement when the general call address is received. If this bit is set to "1", an acknowledgement is generated. 339 CHAPTER 16 I2C INTERFACE ■ Notes on Competition among the SCC, MSS and INT Bits When simultaneous writing to the SCC, MSS, and INT bits occurs, there is competition for transmission of the next byte or generation of the start or stop condition. The priority is determined as explained below. 1) Transmission of the next byte or generation of the stop condition When the INT bit is set to "0" and the MSS bit is set to "0", the "0" setting of the MSS bit takes precedence, and the stop condition is generated. 2) Transmission of the next byte or generation of the start condition When the INT bit is set to "0" and the SCC bit is set to "1", the "1" setting of the SCC bit takes precedence, and the start condition is generated. 3) Generation of the start or stop condition Setting the SCC bit to "1" and the MSS bit to "0" at the same time is prohibited. 340 16.3 I2C Interface Registers 16.3.3 I2C Clock Control Register (ICCR) The I2C clock control register (ICCR) has the following functions: • Enabling operation of the I2C interface • Setting the frequency of the serial clock ■ I2C Clock Control Register (ICCR) Figure 16.3-4 Clock Control Register (ICCR) Bit 7 6 5 4 3 2 1 0 - - EN - - R/W R/W R/W R/W R/W R/W CS4 CS3 CS2 CS1 CS0 Initial value XX0XXXXXB I2C interface operation enable bit EN R/W X 0 Operation disabled 1 Operation enabled : Read/write enabled : Undefined : Initial value Table 16.3-3 Functions of the I2C Clock Control Register (ICCR) Bits Bit name bit7 bit6 bit5 bit4 to bit0 -: Undefined bit EN: I2C interface operation enable bit Function • • The read value of this bit is undefined. The value set for this bit does not affect operation. • • • This bit enables operation of the I2C interface. If this bit is set to "0", the bits of the I2C bus status register (IBSR) and the I2C bus control register (IBCR), except for the BER and BEIE bits, are cleared. This bit is cleared to "0" if the BER bit is set to "1". • • These bits set the frequency of the serial clock The frequency of the shift clock (fsck) is set as follows: CS4 to CS0: Serial clock frequency setting bits fsck = φ m×n+4 φ: Machine clock frequency • For information on the serial clock frequency setting value, see Table 16.3-5 "Serial Clock Frequency Settings (CS2 to CS0)". 341 CHAPTER 16 I2C INTERFACE Table 16.3-4 Serial Clock Frequency Settings (CS4 and CS3) m CS4 CS3 5 0 0 6 0 1 7 1 0 8 1 1 Table 16.3-5 Serial Clock Frequency Settings (CS2 to CS0) n CS2 CS1 CS0 4 0 0 0 8 0 0 1 16 0 1 0 32 0 1 1 64 1 0 0 128 1 0 1 256 1 1 0 512 1 1 1 If, for example, m = 5 and n = 32 are selected when φ = 16 MHz, the resulting serial clock frequency is 97.561 kHz. Notes: • The addition of four cycles is the minimum overhead required to check whether the output level of the SCL pin has changed. More cycles are required if the rising edge delay on the SCPL pin is greater or the clock period on the slave device is prolonged. • According to the setting of the I2C operation enable bit (EN bit), the output from the I2C common port pin varies as follows: • 342 • When the EN bit is set to 1 (operation is enabled): An I2C output signal is output from the SDA/D90 and SCL/P91 pins regardless of the setting values (input or output settings) of bit 8 of DDR9 bit 9 of DDR9. • When the EN bit is set to 0 (operation is disabled): The P90 and P91 setting values of the PDR9 register are output from the SDA/D90 and SCL/P91 pins if bit 8 of the DDR9 is "1" and bit 9 of DDR9 is also "1" (output setting). While the I2C is in operation, execution of an RMW instruction for the port data register (PDR9) reflecting the setting of the I2C pin reads the pin level into bit 8 and bit 9 of PDR9 during reads operations. Accordingly, note that the values of bit 8 and bit 9 of PDR9 may change depending on the level of the P91/SCL and P90/SDA pins. 16.3 I2C Interface Registers Figure 16.3-5 Change Timing for the I2C Common Port I2C operation enabled/disabled I2C operation enabled: EN bit=1 SCL/P91 I2C operation disabled: EN bit = 0 DDR9: bit9 = 0: Hi-z for input setting DDR9: bit9 = 1: New PDRA value is output SDA/P90 DDR9: bit8 = 0: Hi-z for input setting DDR9: bit8 = 1: New PDRA value is output Timing for executing an RMW instruction for the PDRA register PDRA register value RMW instruction executed Previous data Varies depending on the pin level at the time the RMW instruction is executed 343 CHAPTER 16 I2C INTERFACE 16.3.4 I2C Address Register (IADR) The I2C address register (IADR) specifies the slave address. ■ I2C Address Register (IADR) Figure 16.3-6 I2C Address Register (IADR) Bit 15 14 13 12 11 10 9 8 - A6 A5 A4 A3 A2 A1 A0 R/W X Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W : Read/write enabled : Undefined This register specifies the slave address. In slave mode, received address data is compared with the DAR register, and if a match occurs, an acknowledgement is sent to the master. 344 16.3 I2C Interface Registers 16.3.5 I2C Data Register (IDAR) The I2C data register (IDAR) is used for serial transfer. ■ I2C Data Register (IDAR) Figure 16.3-7 I2C Data Register (IDAR) Bit 7 6 5 4 3 2 1 0 Initial value D7 D6 D5 D4 D3 D2 D1 D0 XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W X : Read/write enabled : Undefined The data register is used for serial transfer. Data is transferred starting from the MSB. The data output value is "1" if data is being received (TRX="0"). The writing side of this register is double-buffered. While the bus is in use (BB="1"), the write data is loaded into the register for serial transfer for each byte is transferred. During reading, data is read directly from the register for serial transfer. Thus, the received data is valid only while the INT bit is set. 345 CHAPTER 16 I2C INTERFACE 16.3.6 I2C Port Select Register (ISEL) The I2C port select register (ISEL) contains the settings for the I2C. ■ I2C Port Select Register (ISEL) Figure 16.3-8 I2C Port Select Register (ISEL) Bit R/W X - 15 14 13 12 11 10 9 8 - - - - - - - SEL - - - - - - - R/W Initial value XXXXXXX0B : Read/write enabled : Undefined : Undefined bit Table 16.3-6 Functions of the I2C Port Select Register (ISEL) Bits Bit name bit15 to bit9 bit8 346 Function -: Undefined bit • • SEL: I2C setting bit Set this bit to use the I2C pin functions. If this bit is set to "0", the port or UART ch.3 is enabled. If this bit is set to "1" and the I2C interface operation enable bit (EN) of the I2C clock control register (ICCR) is set to "1", the pins become the I2C I/O pins. Note: Be sure to set this bit to "1" to use the I2C interface. • • • The value read from this bit is undefined. Setting this bit to a new value does not affect operation. 16.4 Operation of the I2C Interface 16.4 Operation of the I2C Interface The I2C bus, which serves as a bidirectional bus line for communications, consists of a serial data line (SDA) and a serial clock line (SCL). As the I2C interface, SDA and SCL can be used as open drain I/O pins (SDA and SCL), enabling wired logic. The input withstand voltage is 5 V (Typ.). ■ Start Condition If the MSS bit is set to "1" while the bus is free (BB="0" and MSS="1"), the I2C interface enters master mode and generates the start condition at the same time. In master mode, you can generate the start condition again by setting the SCC bit to "1" even though the bus line is in use (BB="1"). The start condition is generated for either of the following conditions: 1. The MSS bit is set to "1" while the bus is free (MSS="0", BB="0", INT="0", AL="0"). 2. The SCC bit is set to "1" in an interrupt state in bus master mode (MSS="1", BB="1", INT="1", AL="0"). If the MSS bit is set to "1" while the bus is being used by another system (idle state), the AL bit is set to "1". Under conditions other than (1) and (2), the "1" setting in the MSS and SCC bits is ignored. ■ Stop Condition In master mode, setting the MSS bit to "0" generates a stop condition, causing the I2C interface to enter slave mode. The stop condition is generated under the following condition: • The MSS bit is set to "0" in an interrupt state in bus master mode (MSS="1", BB="1", INT="1", AL="0"). Under conditions other than the above, an MSS bit setting of "0" is ignored. ■ Addressing If, in master mode, a start condition is generated, the BB bit is set to "1", the TRX bit is set to "1", and the contents of the IDAR register are output starting from the MSB. If, after the address data is sent, an acknowledgement is received from the slave, bit 0 of the send data (IDAR bit 0 after sending) is inverted and stored in the TRX bit. If, in slave mode, the start condition is generated, the BB bit is set to "1", the TRX bit is cleared to "0", and the send data from the master is received in the IDAR register. After the address data is received, the IDAR and IADR registers are compared. If the register values match, AAS is set to "1" and an acknowledgement is sent to the master. Then, bit 0 of the receive data (IDAR bit 0 after receiving) is stored in the TRX bit. 347 CHAPTER 16 I2C INTERFACE ■ Arbitration Arbitration occurs if data is sent in master mode and another master sends data at the same time. If the send data is "1" and the data on the SDA line is at the "L level", the sender assumes that it has lost the arbitration and sets the AL bit to "1". The AL bit is set to "1" also if the start condition is generated while the bus is in use. If the AL bit is set to "1", both the MSS and TRX bits are set to "0", causing the I2C interface to enter slave receive mode. ■ Acknowledgement An acknowledgement is sent from the receiver to the sender. While data is being received, the ACK bit is used to set whether an acknowledgement should be used. While data is being sent, an acknowledgement is stored in the LRB bit. If, in slave send mode, no acknowledgement is received from the master receiver, the TRX bit is set to "0", causing the I2C interface to enter slave receive mode. Thus, the master can generate the stop condition when the slave frees the SCL line. ■ Bus Error If any of the following conditions occurs, a bus error is assumed and the I2C interface is stopped. • A basic specification violation is detected on the I2C bus during data transfer (including the ACK bit). • The stop condition is detected in master mode. • A basic specification violation is detected on the I2C bus when the bus is idle. ■ Execution of Start Condition Generation Instruction While SDA=LOW and SCL=LOW When the start condition generation instruction (which writes 1 to the MSS bit) is executed while SDA=LOW and SCL=LOW, this results in BB=0 and AL=1. In this case, the transfer end interrupt request flag (INT bit) is not set because the transfer is not completed. Consequently, detect this status by monitoring the BB and AL bits from the program. Figure 16.4-1 Change Timing for Flags When the Start Condition Generation Instruction is Executed While SDA=LOW and SCL=LOW SCL "L" "L" SDA Start condition Arbitration Interrupt Bus busy 348 Setting the MSS bit to "1" AL bit of IBSR INT bit of IBCR "L" BB bit of IBSR "L" 16.4 Operation of the I2C Interface 16.4.1 Transfer Flow of the I2C Interface Figure 16.4-2 "One-byte Transfer Flow from the Master to the Slave" shows the flow of a one-byte transfer from the master to the slave. Figure 16.4-3 "One-byte Transfer Flow from the Slave to the Master" shows the flow of a one-byte transfer from the slave to the master. ■ Transfer Flow of the I2C Interface Figure 16.4-2 One-byte Transfer Flow from the Master to the Slave Master Slave Start DAR: Writing MSS: Writing 1 Start condition BB set, TRX set BB set, TRX set Address data transfer AAS set Acknowledgement LBR reset INT set,TRX set DAR: Writing INT: Writing 0 Interrupt INT set,TRX set ACK: Writing 1 INT: Writing 0 Data transfer Acknowledgement LBR rest INT set Interrupt MSS: Writing 0 INT reset BB reset,TRX reset Stop condition INT set DAR: Reading INT: Writing 0 BB reset,TRX reset AAS reset End 349 CHAPTER 16 I2C INTERFACE Figure 16.4-3 One-byte Transfer Flow from the Slave to the Master Master Slave Start DAR: Writing MSS: Writing 1 Start condition BB set,TRX set BB set,TRX set Address data transfer AAS reset Acknowledgement LBR reset INT set,TRX reset Interrupt INT: Writing 0 INT set,TRX set DAR: Writing INT: Writing 0 Data transfer Negative acknowledgement INT set DAR: Reading LBR set,TRX set INT set Interrupt INT: Writing 0 MSS: Writing 0 INT reset BB reset,TRX reset Stop condition End 350 BB reset,TRX reset AAS reset 16.4 Operation of the I2C Interface 16.4.2 Mode Flow of the I2C Interface Figure 16.4-4 "I2C Mode Flow" shows the flow of mode transitions for the I2C interface. ■ Flow of I2C Interface Mode Transitions Figure 16.4-4 I2C Mode Flow Slave receive mode STC NO YES TRX,AAS,LRB:reset FBT:set YES STC&BB=1 RSC:set NO BB:set 8 bits received Address comparison RSC,FBT:reset Match AAS:set Acknowledgement output INT:set SCL line retained at "L" NO TRX=1 Slave receive mode YES YES SPC Slave send mode AAS,LRB,BB,RSC :reset NO INT: 0 write FBT:reset SCL line freed Send/receive YES Acknowledgement received? NO TRX:reset 351 CHAPTER 16 I2C INTERFACE 16.4.3 Operation Flow of the I2C Interface Figure 16.4-5 "Operation Flow of the Master Send/Receive Program (with Interrupts) for the I2C Interface" shows the operation flow of a master send/receive program (with interrupts) for the I2C interface. Figure 16.4-6 "Operation Flow of the Slave Program (with Interrupts) for the I2C Interface" shows the operation flow of the slave program (with interrupts) for the I2C interface. ■ Operation Flow of the I2C Interface Figure 16.4-5 Operation Flow of the Master Send/Receive Program (with Interrupts) for the I2C Interface Main routine Interrupt routine Start Start Stop condition generated Set the slave address Bus error occurred? I2C operation enabled No I2C initial setting Send the slave address set (Data direction bit=0) Receive the slave address set (Data direction bit=1) Yes Yes Master? No To the slave program interrupt routine Yes Was ACK returned? No Yes BBbit = 1? No Generate the start condition while sending the slave address Generate the start condition while sending the slave address Wait for a certain amount of time Wait for a certain amount of time No Is the data direction bit (TRX) 1? LOOP Is the number Yes of remaining bytes to be received 0? No Yes Is the number of remaining bytes to be sent 0? Yes No Decrement the number of BB bit = 0 and Yes BB bit = 0 and Yes bytes to be sent AL bit = 1? AL bit = 1? I2C operation disabled No I2C operation disabled Set the send data No LOOP RETI Acknowledge occurrence enabled No Master receive Set the number of bytes to be sent for each time that data is written No I2C operation enabled AL occurred? Set the number of bytes to be sent for each time that data is written BBbit = 1? RETI No Master receive operation? Master send Clear the bus error interrupt source Yes Clear the end interrupt factor Is the number of remaining bytes to be received 1? Yes No Acknowledge occurrence enabled Acknowledge occurrence enabled Is the first byte Yes being received? No RETI Decrement the number of bytes to be received Store the receive data to the RAM Clear the end interrupt factor RETI 352 16.4 Operation of the I2C Interface Figure 16.4-6 Operation Flow of the Slave Program (with Interrupts) for the I2C Interface Main routine Interrupt routine Start Start Set the slave address I2C operation enabled Set slave mode LOOP Bus error occurred? YES No Is addressing completed? Clear the end interrupt source Clear the bus error interrupt factor RETI I2C operation enabled No I2C initial setting RETI Yes Is the data direction bit (TRX) 1? No Yes Is ACK returned? No Is the receive data an address? Yes No Store the receive data in RAM Yes Set the send data Clear the end interrupt source Clear the end interrupt source RETI RETI 353 CHAPTER 16 I2C INTERFACE 354 CHAPTER 17 8/10-BIT A/D CONVERTER This chapter describes the functions and operations of the MB90M405 series 8/10-bit A/D converter. 17.1 "Overview of the 8/10-Bit A/D Converter" 17.2 "Configuration of the 8/10-Bit A/D Converter" 17.3 "8/10-Bit A/D Converter Pins" 17.4 "8/10-Bit A/D Converter Registers" 17.5 "8/10-Bit A/D Converter Interrupts" 17.6 "Operation of the 8/10-Bit A/D Converter" 17.7 "Usage Notes on the 8/10-Bit A/D Converter" 355 CHAPTER 17 8/10-BIT A/D CONVERTER 17.1 Overview of the 8/10-Bit A/D Converter The 8/10-bit A/D converter has a function for converting the analog input voltage into a 10-bit or 8-bit value using the RC-type successive approximation conversion method. ■ Functions of the 8/10-Bit A/D Converter The following shows the functions of the 8/10-bit A/D converter: • The minimum conversion time is 5.9 μs (for a machine clock of 16.8 MHz; includes the sampling time). • The minimum sampling time is 2.1 μs (for a machine clock of 16.8 MHz). • The converter uses the RC-type successive approximation conversion method with a sample hold circuit. • A resolution of 10 bits or 8 bits can be selected. • The input signal can be set using a program from the 8-channel analog input pins. • At the end of A/D conversion, an interrupt request can be generated and EI2OS can be activated. • If A/D conversion is performed while an interrupt is enabled, the conversion data protection function is activated. • The conversion can be activated by software, 16-bit reload timer 1 output (rising edge), and 16-bit free-running timer zero detection edge. Table 17.1-1 "8/10-bit A/D Converter Conversion Modes" lists four types of conversion modes. Table 17.1-1 8/10-bit A/D Converter Conversion Modes Conversion mode Single conversion Scan conversion Single conversion mode 1 Single conversion mode 2 Converts the input of a specified channel (single channel) just once. Converts the inputs of two or more consecutive channels (up to 16 channels) just once. Continuous conversion mode Converts the input of a specified channel (single channel) repeatedly. Repeatedly converts the inputs of two or more consecutive channels (up to 16 channels). Stop conversion mode Converts the input of a specified channel (single channel), after which it is on standby for the next activation. Converts the inputs of two or more consecutive channels (up to 16 channels) once, then enters standby mode and waits for the next start. 356 17.1 Overview of the 8/10-Bit A/D Converter ■ 8/10-Bit A/D Converter Interrupts and EI2OS Table 17.1-2 8/10-Bit A/D Converter Interrupts and El2OS Interrupt control register Interrupt No. #37 (25H) Vector table address Register name Address Lower Upper Bank ICR13 0000BDH FFFF68H FFFF69H FFFF6AH El2OS O O: Available 357 CHAPTER 17 8/10-BIT A/D CONVERTER 17.2 Configuration of the 8/10-Bit A/D Converter The 8/10-bit A/D converter consists of the following blocks: • A/D control status register (ADCS0/ADCS1) • A/D data register (ADCR0/ADCR1) • A/D conversion channel select register (ADMR) • Clock selector (Input clock selector for activating A/D conversion) • Decoder • Analog channel selector • Sample hold circuit • D/A converter • Comparator • Control circuit ■ Block Diagram of the 8/10-Bit A/D Converter Figure 17.2-1 Block Diagram of the 8/10-Bit A/D Converter Interrupt request signal #37 (25H) A/D conversion channel select register (ADMR) A/D control status register (ADCS0/ADCS1) BUSY INT INTE PAUS STS1 STS0 STRT RESV MD1 MD0 ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0 8 2 Clock selector Sample holding circuit PB15/AN15 to PA0/AN0 A/D data register (ADCR0/ADCS1) : Machine clock * : Interrupt signal 358 Analog channel selector S10 ST1 ST0 CT1 CT0 AVR AVcc AVss Decoder Internal data bus 16-bit reload timer 1 output Comparator Control circuit 2 D/A converter 2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 17.2 Configuration of the 8/10-Bit A/D Converter ❍ A/D control status register (ADCS0/ADCS1) The A/D control status register (ADCS0) sets the A/D conversion mode. The A/D control status register (ADCS1) sets the A/D conversion activation trigger and enable/ disable of interrupt requests and checks the interrupt request status and whether the A/D conversion has halted/is in progress. ❍ A/D data register (ADCR0/ADCR1) This register stores the results of A/D conversion. It also sets the resolution for A/D conversion, sampling time during A/D conversion, and compare time during A/D conversion. ❍ A/D conversion channel select register (ADMR) A/D conversion channel select register (ADMR) sets the A/D conversion start/end channel. ❍ Clock selector The clock selector selects the clock for starting A/D conversion. The 16-bit reload timer 1 output can be used as the start clock. ❍ Decoder This circuit sets the analog input pin to be used based on the A/D conversion end channel setting bits (ANE0 to ANE3) and A/D conversion start channel setting bits (ANS0 to ANS3) of the A/D control status register (ADCS0). ❍ Analog channel selector This circuit selects the pin to be used from among 16 analog input pins. ❍ Sample hold circuit This circuit maintains the input voltage from the pin set by the analog channel selector. By maintaining the input voltage just after starting A/D conversion, it is not affected by input voltage variations during A/D conversion (during comparison). ❍ D/A converter This circuit generates a reference voltage for comparison with the input voltage maintained by the sample hold circuit. ❍ Comparator This circuit compares the input voltage maintained by the sample hold circuit with the output voltage of the D/A converter to determine which is greater. ❍ Control circuit This circuit determines the A/D conversion value based on the decision signal generated by the comparator. When the A/D conversion has been completed, the circuit sets the conversion result in the A/D data register (ADCR0/ADCR1) and generates an interrupt request. 359 CHAPTER 17 8/10-BIT A/D CONVERTER 17.3 8/10-Bit A/D Converter Pins This section describes the 8/10-bit A/D converter pins and provides pin block diagrams. ■ 8/10-Bit A/D Converter Pins The A/D converter pins are also used as I/O ports. Table 17.3-1 8/10-bit A/D Converter Pins Function Pin name Channel 0 PA0/AN0 Channel 1 PA1/AN1 Channel 2 PA2/AN2 Channel 3 PA3/AN3 Channel 4 PA4/AN4 Channel 5 PA5/AN5 Channel 6 PA6/AN6 Channel 7 PA7/AN7 Channel 8 PB0/AN8 Channel 9 PB1/AN9 Channel 10 PB2/AN10 Channel 11 PB3/AN11 Channel 12 PB4/AN12 Channel 13 PB5/AN13 Channel 14 PB6/AN14 Channel 15 PB7/AN15 360 Pin function Port A inputoutput or analog input Port B inputoutput or analog input Input-output signal type CMOS output/ CMOS hysteresis input or analog input CMOS output/ CMOS hysteresis input or analog input Pull-up option Not selectable Not selectable Standby control Setting for using the pin Not selectable Set Port A as an input port (DDRA:bit0 to bit7="0"). Set as an analog port (ADER0:bit0 to bit7="1") Not selectable Set Port B as an input port (DDRB:bit0 to bit7="0"). Set as an analog port (ADER1:bit0 to bit7="1") 17.3 8/10-Bit A/D Converter Pins ■ Block Diagrams of the 8/10-Bit A/D Converter Pins Figure 17.3-1 Block Diagram of the PA0/AN0 to PB7/AN15 Pins A/D converter analog input signal Internal data bus ADER PDR read PDR I/O evaluation circuit Input buffer Output buffer PDR write DDR Port pin Standby control (LPMCR: SPL="1") Standby control: Stop mode and LPMCR: SPL="1" Notes: • To use a pin as an input port, set the corresponding bit (bit7 to bit0) of the port direction registers (DDRA and DDRB) to "0" and the corresponding bit (bit15 to bit0) of the analog input enable registers (ADER0 and ADER1) to "0". • To use a pin as an analog input pin, set the corresponding bit (bit15 to bit0) of the analog input enable registers (ADER0 and ADER1) to "1". The value read from each of the port data registers (PDRA and PDRB) is 00H. 361 CHAPTER 17 8/10-BIT A/D CONVERTER 17.4 8/10-Bit A/D Converter Registers This section lists the 8/10-bit A/D converter registers. ■ 8/10-Bit A/D Converter Registers Figure 17.4-1 List of Registers of the 8/10-Bit A/D Converter bit15 bit8 bit7 bit0 A/D control status register (ADCS1) A/D control status register (ADCS0) A/D data register (ADCR1) A/D conversion channel select register (ADMR) 362 A/D data register (ADCR0) 17.4 8/10-Bit A/D Converter Registers 17.4.1 A/D Control Status Register 1 (ADCS1) The A/D control status register (ADCS1) sets the A/D conversion activation trigger and enable/disable of interrupt requests and checks the interrupt request status and whether the A/D conversion has halted/is in progress. ■ A/D Control Status Register 1 (ADCS1) Figure 17.4-2 A/D Control Status Register 1 (ADCS1) Bit 15 14 13 12 11 10 9 8 BUSY INT INTE PAUS STS1 STS0 STRT RESV R/W R/W R/W R/W R/W R/W W Initial value 00000000B R/W RESV Reserved bit Always write 0 to this bit. STRT 0 1 A/D conversion activation bit (valid only when activated by software (ADC2: EXT= 0)) Does not activate the A/D conversion. Activate the A/D conversion function. A/D activation select bit STS1 STS0 0 0 0 1 1 0 Activation by 16-bit reload timer1 or 1 1 activation of software Activation by software. Halt flag bit (valid only when EI2OS is used) PAUS 0 A/D conversion is active 1 A/D conversion is halted. INTE 0 1 INT Interrupt request enable bit Disables interrupt request output. A/D conversion is halted. Interrupt request flag bit Reading Writing 0 A/D conversion has not been completed. Clears interrupt request 1 A/D conversion has been completed. BUSY No effect on operation Busy bit Reading Writing 0 A/D conversion is halted. Stops the A/D conversion. 1 A/D conversion is in progress. No change,no effect on other bits. R/W : Read/write W : Write only : Initial value 363 CHAPTER 17 8/10-BIT A/D CONVERTER Table 17.4-1 Function Description of Each Bit of A/D Control Status Register 1 (ADCS1) Bit name Function bit15 BUSY: Busy bit • This bit indicates the operating status of the A/D converter • When this bit is "0", the A/D conversion has halted. • When this bit is "1", the A/D conversion is in progress. • When this bit is set to "0", the A/D conversion is forced to halt. • When this bit is set to "1", operation is not affected. Note: Do not set the forced A/D conversion stop and the activation (BUSY="0", STRT="1") simultaneously. bit14 INT: Interrupt request flag bit • • bit13 INTE: Interrupt request enable bit • • This bit is a flag that requests an interrupt. This bit is set to "1" when A/D conversion results are stored in the A/D data register (ADCR0/ADCR1). • When this bit is set to "1" while the interrupt request enable bit (INTE) is "1", an interrupt request is output. • When this bit is set to "0", the interrupt request is cleared. • When this bit is set to "1", operation is not affected. • When EI2OS is used, this bit is cleared to "0". Note: To clear the interrupt requests, stop the A/D conversion. • This bit enables an interrupt request. When the interrupt request flag bit (INT) is set to "1" while this bit is set to "1", an interrupt request is output. To use EI2OS, set this bit to "1". bit12 PAUS: Halt flag bit This bit is set to "1" when the A/D conversion stops temporarily. When EI2OS is used in continuous conversion mode, this bit is set to "1" if transfer of the last piece of data to memory has not been completed even though A/D conversion is completed. Thus, the A/D conversion is stopped temporarily and conversion data is not stored in the A/D data register (ADCR0/ ADCR1). • When data transfer of the last piece of data to memory is completed, this bit is cleared to "0" and the A/D conversion is then restarted. Note: This bit is valid when EI2OS is used. bit11 bit10 STS1, STS0: A/D activation select bit • • bit9 STRT: A/D conversion activation bit • This bit allows software to start A/D conversion. • Writing 1 to this bit activates A/D conversion. • In stop conversion mode, conversion cannot be reactivated with this bit. Note: Never perform the forced stop and activation (BUSY="0", STRT="1") of the A/D conversion simultaneously. bit8 RESV: Reserved bit Note: Always write 0 to this bit. 364 • • These bits select how A/D conversion is to be activated. When two or more activation causes are shared, activation is the result of the cause that occurs first. Note: Change the setting during A/D conversion only while there is no corresponding activation cause, since the change becomes effective immediately. 17.4 8/10-Bit A/D Converter Registers 17.4.2 A/D Control Status Register 0 (ADCS0) The A/D control status register (ADCS0) sets the A/D conversion mode. ■ A/D Control Status Register 0 (ADCS0) Figure 17.4-3 A/D Control Status Register 0 (ADCS0) Bit 7 6 5 4 3 2 1 0 Initial value MD1 MD0 - - - - - - 00XXXXXXB R/W R/W - - - - - - MD1 MD0 0 0 0 1 1 0 1 1 A/D conversion mode setting bit Single conversion mode 1 (reactivation allowed during operation) Single conversion mode 2 (reactivation not allowed during operation) Continuous conversion mode (reactivation not allowed during operation) Stop conversion mode (reactivation not allowed during operation) R/W : Read/write enabled : Undefined bit : Initial value 365 CHAPTER 17 8/10-BIT A/D CONVERTER Table 17.4-2 Function Description of Each Bit of A/D Control Status Register 0 (ADCS0) Bit name Function • • bit7 bit6 366 MD1, MD0: A/D conversion mode setting bit This bit is used to set the A/D conversion mode. Single conversion mode 1, single conversion mode 2, continuous conversion mode, and stop conversion mode can be set. Single conversion mode 1: A/D conversion is performed from the channel specified by the A/D conversion start channel setting bits (ANS3 to ANS0) to that specified by the A/D conversion end channel setting bits (ANE3 to ANE0) before terminating. Reactivation during operation is allowed. Single conversion mode 2: A/D conversion is performed from the channel specified by the A/D conversion start channel setting bits (ANS3 to ANS0) to that specified by the A/D conversion end channel setting bits (ANE3 to ANE0) before terminating. Reactivation during operation is not allowed. Continuous conversion mode: A/D conversion is performed from the channel specified by the A/D conversion start channel setting bits (ANS3 to ANS0) to that specified by the A/D conversion end channel setting bits (ANE3 to ANE0) is repeated until the conversion stop is forcibly implemented by the Converting bit (BUSY). Reactivation during operation is not allowed. Stop conversion mode: A/D conversion is performed from the channel specified by the A/D conversion start channel setting bits (ANS3 to ANS0) to that specified by the A/D conversion end channel setting bits (ANE3 to ANE0) is repeated by making a pause for each channel until the conversion stop is forcibly implemented by the Converting bit (BUSY). Reactivation during operation is not allowed. Reactivation during the pause depends on the activation trigger set in the A/D activation trigger setting bits (STS1, STS0). Note: The impossibility of reactivation of each conversion mode (simple, continuous, and stop) is applied to the 16-bit free-running timer 0 detection, 16-bit reload timer1, and activation of all software. 17.4 8/10-Bit A/D Converter Registers 17.4.3 A/D Data Register (ADCR0/ADCR1) The A/D data register (ADCR0/ADCR1) stores the results of A/D conversion. It also sets the resolution for A/D conversion, sampling time during A/D conversion, and compare time during A/D conversion. ■ A/D Data Register (ADCR0/ADCR1) Figure 17.4-4 A/D Data Register (ADCR0/ADCR1) Bit 15 14 13 12 11 S10 ST1 ST0 CT1 CT0 W W W W W 10 9 8 7 6 5 4 3 2 1 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R R R R R R R R R D9 to D0 Initial 00000XXXB (Upper) XXXXXXXXB (Lower) R A/D data bit Stores conversion data CT1 CT0 0 44 machine cycles (5.50 µs when φ = 8 MHz) 0 1 66 machine cycles (4.12 µs when φ = 16 MHz) 1 0 88 machine cycles (5.50 µs when φ = 16 MHz) 1 1 176 machine cycles (11.0 µs when φ = 16 MHz) ST1 ST0 0 20 machine cycles (2.5 µs when φ = 8 MHz) 0 1 32 machine cycles (2.0 µs when φ = 16 MHz) 1 0 48 machine cycles (3.0 µs when φ = 16 MHz) 1 1 128 machine cycles (8.0 µs when φ = 16 MHz) 0 1 φ : : : : : : Sampling time setting bit 0 S10 R/W W X - Comparison time setting bit 0 A/D conversion resolution setting bit 10-bit resolution mode (D9 to D0) 8-bit resolution mode (D7 to D0) Read-only Write-only Undefined Undefined bit Initial value Machine clock frequency 367 CHAPTER 17 8/10-BIT A/D CONVERTER Table 17.4-3 Function Description of Each Bit of A/D Control Status Register (ADCR0/ADCR1) Bit name Function bit15 S10: A/D conversion resolution setting bit • This bit is used to set the resolution for A/D conversion. • When this bit is "0", the 10-bit resolution is set. • When this bit is "1", the 8-bit resolution is set. Note: A/D data bits to be used depend on the resolution. In 10-bit resolution mode, the D9 to D0 bits are used. In 8-bit resolution mode, the D7 to D0 bits are used. bit14 bit13 ST1, ST0: Sampling time setting bit • • This bit is used to set the sampling time for A/D conversion. When A/D conversion is activated, the analog input is captured for the time interval specified by the sampling time setting bits (ST1, ST0). Note: • When "00B" is set, the machine clock frequency should be equal to or less than 8 MHz. • If "00B" is set when the machine clock frequency is 16 MHz, normal analog conversion values may not be obtained. bit12 bit11 CT1, CT0: Comparison time setting bit • • This bit is used to set the compare time for A/D conversion. The A/D conversion result is determined after the analog input is captured (sampling time passed) and the compare time interval specified by the compare time setting bits (CT1, CT0). In 10-bit resolution mode, the result is stored in the A/D data bits (D9 to D0). In 8-bit resolution mode, the result is stored in the A/D data bits (D7 to D0). Note: • When "00B" is set, the machine clock frequency should be equal to or less than 8 MHz. • If "00B" is set when the machine clock frequency is 16 MHz, normal analog conversion values may not be obtained. vit10 -: Undefined bit • • bit9 - bit0 D9 - D0: A/D data bit • The value read from this bit is undefined. The value set to this bit does not affect operation. These bits are used to store A/D conversion results. They are rewritten after each A/D conversion is completed. • Normally, the final conversion value is stored. • The initial value is undefined. Note: The A/D conversion data protection function is available (For details, see Section 17.6 "Operation of the 8/10-Bit A/D Converter"). Do not write data to the A/D data bits during A/D conversion. Notes: 368 • Be sure to stop the A/D conversion before rewriting the A/D conversion resolution setting bit (S10). If the bit is rewritten after the A/D conversion started, the A/D data register (ADCR0/ ADCR1) contents are undefined. • To read the A/D data register (ADCR0/ADCR1), be sure to use the word transfer instructions (such as MOVW A and 002EH) when 10-bit resolution mode is specified. 17.4 8/10-Bit A/D Converter Registers 17.4.4 A/D Conversion Channel Select Register (ADMR) The A/D Conversion Channel Select Register (ADMR) selects an A/D conversion channel. ■ A/D Conversion Channel Select Register (ADMR) Figure 17.4-5 A/D Conversion Channel Select Register (ADMR) Bit 15 14 13 12 11 10 9 8 ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0 Initial value 0000000B R/W R/W R/W R/W R/W R/W R/W R/W ANE3 ANE2 ANE1 ANE0 A/D conversion end channel selection bit AN0 0 0 0 0 AN1 0 0 0 1 AN2 0 0 1 0 AN3 0 0 1 1 AN4 0 1 0 0 AN5 0 1 0 1 AN6 0 1 1 0 AN7 0 1 1 1 AN8 1 0 0 0 AN9 1 0 0 1 AN10 1 0 1 0 AN11 1 0 1 1 AN12 1 1 0 0 AN13 1 1 0 1 AN14 1 1 1 0 AN15 1 1 1 1 ANS3 ANS2 ANS1 ANS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A/D conversion start channel selection bit Reading Reading during temporary stop in Stopped during conversion stop conversion mode AN0 AN1 AN2 AN3 AN4 AN5 Channel Channel number AN6 number converted just being AN7 before halting converted AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 R/W : Read/write enabled : Initial value 369 CHAPTER 17 8/10-BIT A/D CONVERTER Table 17.4-4 Functions of the A/D Conversion Channel Selection Register (ADMR) Bits Bit name Function • bit7 bit6 bit5 bit4 ANS3, ANS2, ANS1, ANS0: A/D conversion start channel selection bits • • • • • bit3 bit2 bit1 bit0 370 ANE3, ANE2, ANE1, ANE0: A/D conversion end channel selection bits • These bits are used to select an A/D conversion start channel and check a channel number being converted. A/D conversion starts from the channel selected via the A/D conversion start channel selection bits (ANS3 to ANS0). During A/D conversion, a channel number that is being converted is read. During temporary stop in stop conversion mode, a channel number converted just before the temporary stop is read. These bits are used to select an A/D conversion end channel. A/D conversion ends with the channel selected by the A/D conversion end channel selection bits (ANE3 to ANE0). If the same channel is selected both by the A/D conversion start channel selection bits (ANS3 to ANS0) and by the A/D conversion end channel selection bits, A/D conversion is performed on the specified channel. If continuous conversion mode or stop conversion mode is specified, A/D conversion ends with the channel selected by the A/D conversion end channel selection bits (ANE3 to ANE0) and conversion is then repeated starting with the start channel selected by the A/D conversion start channel selection bits (ANS3 to ANS0). If the value specifying the start channel is greater than the value specifying the end channel, A/D conversion is performed on the start channel through AN15 and then on AN0 through the end channel, completing the first phase of conversion operation. 17.5 8/10-Bit A/D Converter Interrupts 17.5 8/10-Bit A/D Converter Interrupts The 8/10-bit A/D converter can generate an interrupt request when the data for the A/D conversion is set in the A/D data register. This function supports the extended intelligent I/O service (EI2OS). ■ 8/10-bit A/D Converter Interrupts Table 17.5-1 Interrupt Control Bits of the 8/10-Bit A/D Converter and the Interrupt Cause 8/10-bit A/D converter Interrupt request flag bit ADCS: INT="1" Interrupt request enable bit ADCS: INTE="1" Interrupt cause Writing the A/D conversion result to the A/D data register When A/D conversion is started and the A/D conversion result is stored in the A/D data register (ADCR0 and ADCR1), the interrupt request flag bit (INT) of the A/D control status register (ADCS1) is set to "1". If the interrupt request enable bit (INTE) has been set to "1", an interrupt request is output to the CPU. ■ 8/10-Bit A/D Converter Interrupts and EI2OS Table 17.5-2 8/10-Bit A/D Converter Interrupts and El2OS Interrupt control register Vector table address Interrupt No. Register name Address Lower Upper Bank #37 (25H) ICR13 0000BDH FFFF68H FFFF69H FFFF6AH EI2OS o o: Available ■ EI2OS Function of the 8/10-Bit A/D Converter The 10-bit A/D converter can transfer A/D conversion results to memory using the EI2OS function. When the EI2OS function is used, the conversion data protection function is activated to temporarily stop A/D conversion until A/D conversion data has been transferred to memory and the interrupt request flag bit (INT) of the A/D control status register (ADCS1) is cleared to "0". This function is useful for preventing the omission of data. 371 CHAPTER 17 8/10-BIT A/D CONVERTER 17.6 Operation of the 8/10-Bit A/D Converter The 8/10-bit A/D converter has four conversion modes: single conversion mode 1, single conversion mode 2, continuous conversion mode, and stop conversion mode. This section explains each of these modes. ■ Operation in Single Conversion Mode In single conversion mode, analog input specified by the ANS and ANE bits is converted in sequence. A/D conversion ends when it is performed on an end channel specified by the ANE bits. If the start channel and the end channel are the same (ANS=ANE), only one channel specified by the ANS bits is converted. To use single conversion mode, make settings as shown in Figure 17.6-1 "Settings for Single Conversion Mode". Figure 17.6-1 Settings for Single Conversion Mode Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCS0/ADCS1 BUSY INT INTE PAUS STS1 STS0 STRT RESV MD1 MD0 0 ADCR0/ADCR1 S10 ST1 ST0 CT1 CT0 ADMR ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0 Stores conversion data : Used : Set to 1 the bit corresponding to the pin used. 0 : Set 0. The following are sample conversion sequences in single conversion mode: ANS = 0000B, ANE = 0011B:AN0 --> AN1 --> AN2 --> AN3 --> End ANS = 1110B, ANE = 0010B:AN14 --> AN15 --> AN0 --> AN1 --> AN2 --> End ANS = 0011B, ANE = 0011B:AN3 --> END 372 17.6 Operation of the 8/10-Bit A/D Converter ■ Operation in Continuous Conversion Mode In continuous conversion mode, analog input from the start channel specified by the A/D conversion start channel setting bits (ANS3 to ANS0) of the A/D control status register (ADCS0) to the end channel specified by the A/D conversion end channel setting bits (ANE3 to ANE0) is A/D converted to return to the analog input specified by the A/D conversion start channel setting bits (ANS3 to ANS0) to repeat the A/D conversion. If the start channel and the end channel are the same, the A/D conversion of the channel specified by the A/D conversion start channel setting bits (ANS3 to ANS0) is repeated. The A/D conversion does not stop until the Converting bit (BUSY) of the A/D control status register (ADCS1) is set to "0". Reactivation during operation is not possible. For operation in continuous conversion mode, the settings shown in Figure 17.6-2 "Settings for Continuous Conversion Mode" are required. Figure 17.6-2 Settings for Continuous Conversion Mode Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCS0/ADCS1 BUSY INT INTE PAUS STS1 STS0 STRT RESV MD1 MD0 0 ADCR0/ADCR1 S10 ST1 ST0 CT1 CT0 ADMR ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0 1 0 Stores conversion data : Used : Set to 1 the bit corresponding to the pin used. 1 : Set 1. 0 : Set 0. The following are sample conversion sequences in continuous conversion mode: ANS = 0000B, ANE = 0011B:AN0 --> AN1 --> AN2--> AN3--> AN0--> Repeat ANS = 1110B, ANE = 0010B:AN14 --> AN15 --> AN0--> AN1--> AN2 --> AN14 --> Repeat ANS = 0011B, ANE = 0011B:AN3 --> AN3 --> Repeat 373 CHAPTER 17 8/10-BIT A/D CONVERTER ■ Operation in Stop Conversion Mode In stop conversion mode, analog input from the start channel specified by the A/D conversion start channel setting bits (ANS3 to ANS0) of the A/D control status register (ADCS0) to the end channel specified by the A/D conversion end channel setting bits (ANE3 to ANE0) is A/D converted by making a pause for each channel before returning to the analog input specified by the A/D conversion start channel setting bits (ANS3 to ANS0) to repeat the A/D conversion and pause. If the start channel and the end channel are the same, the A/D conversion of the channel specified by the A/D conversion start channel setting bits (ANS3 to ANS0) is repeated. In the pause state, reactivation method of the A/D conversion depends on the activation cause specified in the activation cause set bit (STS1, STS0) in the A/D control status register (ADCS1). The A/D conversion does not stop until the Converting bit (BUSY) of the A/D control status register (ADCS1) is set to "0". Reactivation during operation is not possible. For operation in stop conversion mode, the settings shown in Figure 17.6-3 "Settings for Stop Conversion Mode" are required. Figure 17.6-3 Settings for Stop Conversion Mode Bit ADCS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUSY INT INTE PAUS STS1 STS0 STRT RESV MD1 MD0 0 ADCR S10 ST1 ST0 CT1 CT0 ADMR ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0 1 1 Stores conversion data : Used : Set to 1 the bit corresponding to the pin used. 1 : Set 1. 0 : Set 0. The following are sample conversion sequences in stop conversion mode: ANS = 0000B, ANE = 0011B: AN0 --> Pause --> AN1 --> Pause --> AN2 --> Pause --> AN3 --> Pause --> AN0 --> Repeat ANS = 1100B, ANE = 0001B: AN14 --> Pause --> AN15 --> Pause --> AN0 --> Pause --> AN1 --> Pause --> AN14 --> Repeat ANS = 0011B, ANE = 0011B: AN3 --> Pause --> AN3 --> Pause --> Repeat 374 17.6 Operation of the 8/10-Bit A/D Converter 17.6.1 Conversion Using EI2OS The 8/10-bit A/D converter can use EI2OS transfer the A/D conversion result to memory. ■ Conversion Using EI2OS Figure 17.6-4 Sample Operation Flowchart When EI2OS is Used Start A/D conversion Sample and hold EI2OS started Conversion End conversion Generate an interrupt Transfer data Has the data transfer been repeated for the specified number of times? (*1) YES Interrupt processing NO Interrupt cleared *1 The number of times is determined by an EI2OS setting. When EI2OS is used, the conversion data protection function prevents any part of the data from being lost even in continuous conversion. Multiple data items can be safely transferred to memory. 375 CHAPTER 17 8/10-BIT A/D CONVERTER 17.6.2 A/D Conversion Data Protection Function When A/D conversion is performed in the interrupt enabled state, the conversion data protection function operates. ■ A/D Conversion Data Protection Function The 8/10-bit A/D converter has only one data register for conversion data storage. Thus, when A/D conversion is performed, the data stored in the data register is rewritten when the conversion is completed. In continuous conversion mode, if conversion data is transferred to memory too late, part of the stored data will be missing. As measures against such data omission, the data protection function works as shown below if an interrupt request is enabled (ADCS1: INTE="1"). ❍ Data protection function when EI2OS is not used When conversion data is stored in the A/D data register (ADCR0/ADCR1), the interrupt request flag bit (INT) of the A/D control status register 1 (ADCS1) is set to "1" and the A/D conversion is halted. The A/D conversion is restarted after transferring the A/D data register (ADCR0/ ADCR1) values to memory in the interrupt routine and the interrupt request flag bit (INT) is cleared to "0". ❍ Data protection function when EI2OS is used In continuous conversion mode, the pause flag bit (PAUS) of the A/D control status register 1 (ADCS1) is set to "1" if EI2OS is used and A/D conversion is completed, but the transfer of the last piece of data to memory is not completed so that the A/D conversion is halted and conversion data is not stored in the A/D data register (ADCR0/ADCR1). When the transfer of the last piece of data to memory is completed, the pause flag bit (PAUS) is cleared to "0" and the A/D conversion is restarted. 376 17.6 Operation of the 8/10-Bit A/D Converter Figure 17.6-5 Flow of the Data Protection Function when EI2OS is Used Set EI2OS Start continuous A/D conversion End the first conversion Store data in the data register Activate EI2OS End the second conversion End EI2OS NO Halt A/D YES Store data in the data register End the third conversion Activate EI2OS Continue All conversions complete Continue Store data in the data register Activate EI2OS Interrupt processing routine Initialize or stop A/D End <Caution> The steps followed while the A/D converter is stopped are omitted. Notes: • The conversion data protection function operates only in the interrupt enabled state (ADCS1: INTE = 1). • If interrupts are disabled during a pause of A/D conversion while EI2OS is operating, the A/D conversion may be reactivated. This will cause new data to be written before the old data is transferred. • Reactivation attempted during a pause will destroy the standby data. 377 CHAPTER 17 8/10-BIT A/D CONVERTER 17.7 Usage Notes on the 8/10-Bit A/D Converter Notes on using the 8/10-bit A/D converter. ■ Usage Notes on the 8/10-Bit A/D Converter ❍ Analog input pin The analog input pins of the A/D converter are used also as the I/O pins of ports A and B. Use these pins by switching the port direction registers (DDRA and DDRB) and the analog input enable registers (ADER0 and ADER1). To use a pin as an analog input pin of the A/D converter, set the corresponding bit (bit 7 to bit 0) of the port direction registers (DDRA and DDRB) to "0" (set it as an input port) and then set the corresponding bit (bit 7 to bit 0 and bit 15 to bit 8) of the analog input enable registers 0 and 1 (ADER0 and ADER1) to "1" to permanently select the input gate on the port side. In port I/O mode (bit 7 to bit 0 of ADER0 and ADER1 ="0" and bit7 to bit0="0"), the input of an intermediate-level signal causes an input leakage current to flow through the gate. ❍ Note on using an internal timer To activate the A/D converter with the internal timer, set the A/D activation trigger setting bits (STS1, STS0) of the A/D control status register (ADCS1). Set the internal timer to the inactive level ("L" for the internal clock). If the internal clock remains at the active level and data is written to the A/D control status register (ADCS0/ADCS1), the A/D converter may be activated. ❍ Sequence of turning on the A/D converter and analog input Be sure to apply the voltage to the power supply pins (AVCC, AVR, and AVSS) of the A/D converter and the analog input pins (AN0 to AN15) after turning on the digital power supply (VCC). Turn off the digital power supply (VCC) after turning off the A/D converter and the analog input power supply. Turn on and turn off the voltage so that AVR does not exceed AVCC. ❍ Supply voltage to the A/D converter The supply voltage to the A/D converter (AVCC) must not exceed the digital power supply (VCC); otherwise, latchup may occur. 378 CHAPTER 18 FL CONTROL CIRCUIT This chapter explains the functions and operation of the MB90M405 series FL control circuit. 18.1 "Overview of FL Control Circuit" 18.2 "Configuration of FL Control Circuit" 18.3 "FL Control Circuit Pins" 18.4 "FL Control Circuit Operation" 379 CHAPTER 18 FL CONTROL CIRCUIT 18.1 Overview of FL Control Circuit The FL control circuit provides functions for automatic display on fluorescent tube and LED displays. The automatic fluorescent display function provides up to 32 points for displaying digits and up to 60 points for displaying digits and segments. The automatic LED display function can output data at a 1/2-duty cycle from the LED01 to LED16 pins while using the LED00 pin as common output. ■ High Dielectric Output Pins • 60 high dielectric output pins (FIP0 to FIP59) are provided. • 34 high-current output pins (FIP0 to FIP33) and 26 medium-current output pins (FIP34 to FIP59) are provided. • Use of pull-down resistors can be set for all high dielectric outputs as well as for combinations of high dielectric outputs. ■ Automatic Fluorescent Tube Display Function 380 • A display RAM area of 32 x 60 bits is provided. • The display timing can be specified with a value from 1 to 32. • For each point of the timing, 60 bits can be used for specifying a combination of digits and segments. • The digit pins from FIP0 to FIP31 can be consecutively set according to the numbers stored in the digit count register, starting with the pin for which start of display is specified. • Output control of up to 59 segments is supported. • Four types of display scan cycles (segment widths) are supported. • In segment output, digit dimmer control is performed during the two T periods that apply to each digit output, as shown in Figure 18.1-1 "Digit Dimmer Control". Seven steps of adjustment are supported. (Dimming is effective for all digits.) • The output level of all digits and segments can be inverted from "H" to "L" or "L" to "H". • Gradation display (use of a segment dimmer) can be applied to segment output with an arbitrary timing. As shown in Figure 18.1-2 "Segment Dimmer Control", control is performed for the two T periods that apply to each segment output. 18.1 Overview of FL Control Circuit Figure 18.1-1 Digit Dimmer Control Digit output Segment output T T T T T Figure 18.1-2 Segment Dimmer Control Digit output H output Example of segment dimmer output Dimming can be set for a specified segment at a specified timing. L output T T T ■ Automatic LED Display Function • Any LED pin from LED00 to LED16 can be set, provided it has not already been set. • As shown in Figure 18.1-3 "Timing Chart of Automatic LED Display", pin LED00 becomes a common pin, while the 16 pins from LED01 to LED16 become LED segment outputs. • When pin LED00 is at the "H" level, the corresponding value is output to pins LED01 to LED16 at the point "T1" of the timing stored in the display RAM. When pin LED00 is at the "L" level, the corresponding value is output to pins LED01 to LED16 at the point "T2". • By inverting the output level of common pin LED00 externally, LED output with 1/2-duty cycle can be obtained. • Figure 18.1-3 "Timing Chart of Automatic LED Display" shows the output time for pins LED01 to LED16 as determined by pin LED00 and its inverting signal. Pin LED00 has an output time of 5.12 ms, and pins LED01 to LED16 have an output time of 4.096 ms each (for a machine clock [peripheral operation clock] frequency of 16 MHz). Figure 18.1-3 Timing Chart of Automatic LED Display 5.12 ms 5.12 ms 4.096 ms 1.024 ms 4.096 ms LED00 pin (common output) Inverted output is created externally. LED segment output from pin LED01 to pin LED16 T1 T2 T1 T2 381 CHAPTER 18 FL CONTROL CIRCUIT 18.2 Configuration of FL Control Circuit The FL control circuit consists of the following blocks: • Control circuit for automatic fluorescent tube display • Control circuit for automatic LED display • Display RAM • Display control register (FLC1) • Display control register (FLC2) • Digit setting register (FLDG) • Digit count register (FLDC) • Segment dimmer setting register (SEGD0 to SEGD7) • Port register (FLPD0 to FLPD2) • Status/authorization register (FLST) ■ Block Diagram of the FL Control Circuit Figure 18.2-1 Block Diagram 1 of the FL Control Circuit FLST FLC1 SW SW Control circuit LED controller FLC2 FIP controller Width setting Inverting of output, timing value setting Digit FLDG Dimmer width setting Setting of start pin for display FLDC Count setting SEGD FLDC FLDC Display RAM 32 x 60 bits Selection of segment dimmer setup timing SEGDT 32 x 1 bit FLPD FLDC FLDC 382 Segment Dimmer width setting Setting of segment for which dimming is set High current Pch Tr x 34 Medium current Pch Tr x 2 x 24 18.3 FL Control Circuit Pins 18.3 FL Control Circuit Pins This section describes the FL control circuit pins and provides a block diagram. ■ Block Diagram of FL Control Circuit Pins Figure 18.3-1 Block Diagram of the FL Control Circuit Pins (FIP00 to FIP16) For automatic LED display: "1" Writing for LED output LED output latch FL output latch Pch FIP00 to FIP16 FL output writing At start of automatic fluorescent tube display: "1" "0" when digit or segment pin "1" for standby is specified mode and reset Pull-down resistor Data bus in FL control circuit Figure 18.3-2 Block Diagram of the FL Control Circuit Pins (FIP17 to FIP35) Writing for FL output FL output latch Pch FIP17 to FIP35 At start of automatic fluorescent tube display: "1" "1" for standby mode and reset Pull-down resistor Data bus on FL control circuit 383 CHAPTER 18 FL CONTROL CIRCUIT Figure 18.3-3 Block Diagram of the FL Control Circuit Pins (FIP36 to FIP59) Writing for FL output FL output latch Pch FIP36 to FIP59 At start of automatic fluorescent tube display: "1" Port output latch Data bus on FL control circuit 384 "1" for standby mode and reset 18.3 FL Control Circuit Pins 18.3.1 Display Control Register 1 (FLC1) This register is used to start, stop, and set up the automatic fluorescent tube and LED display. This register is a write-only register and does not support bit operations. Byte access to this register is supported. ■ Display Control Register 1 (FLC1) Figure 18.3-4 Display Control Register 1 (FLC1) Bit 7 6 5 4 3 2 1 0 Initial value - - - - - - FLLE FLFE XXXXXX00B - - - - - - W W Bit for starting automatic fluorescent tube FLFE display W : Write only - : Unused bit : Initial value 0 Stops automatic fluorescent tube display. 1 Starts automatic fluorescent tube display. FLLE Bit for starting automatic LED display 0 Stops automatic LED display. 1 Starts automatic LED display. 385 CHAPTER 18 FL CONTROL CIRCUIT Table 18.3-1 Functions of the Display Control Register 1 (FLC1) Bits Bit name Bit 7 to Bit 2 Bit 1 Bit 0 386 -: Unused bits FLLE: Bit for starting automatic LED display FLFE: Bit for starting automatic fluorescent tube display Function • • Read value is undefined. Setting a value has no effect on operation. • • • • This bit specifies the start of automatic LED display. When this bit is set to 1, automatic LED display starts. When this bit is set to 0, automatic LED display stops. When automatic LED display starts, LED00 outputs the "H" level and the display RAM value for T1 is output. • When automatic LED display stops, all LED outputs are switched off even during display. Note: After the required display settings have been made, set display control register 2, the digit setting register, and the digit count register to "1". • • • • This bit specifies the start of automatic fluorescent tube display. When this bit is set to "1", automatic fluorescent tube display starts. When this bit is set to "0", automatic fluorescent tube display stops. When automatic fluorescent tube display starts, output starts with the display RAM value for T1. • When automatic fluorescent tube display stops, the output is set to off after output for the current timing value has ended. Note: After the required display settings have been made, set display control register 2, the digit setting register, the digit count register, the display RAM digits, and the segment dimmer (SEGD) to "1". 18.3 FL Control Circuit Pins 18.3.2 Display Control Register 2 (FLC2) This register is used to set inverted output and to specify a segment width and timing value. This register is a write-only register and does not support bit operations. Byte access to this register is supported. ■ Display Control Register 2 (FLC2) Figure 18.3-5 Display Control Register 2 (FLC2) 7 6 5 4 3 2 1 FLDX FLS1 FLS0 FLT4 FLT3 FLT2 FLT1 FLT0 W W W W W Bit W W W 0 Initial value 0000000B Display timing FLT4 FLT3 FLT2 FLT1 FLT0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 Repetition of T1, T2, T1, T2, .. Repetition of T1,T2,T3,T1,T2, .. Repetition of T1,T2,..T4,T1,T2, .. Repetition of T1,T2,..T5,T1,T2, .. Repetition of T1,T2,..T6,T1,T2, .. 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 Repetition of T1,T2,..T29,T1,T2, .. Repetition of T1,T2,..T30,T1,T2, .. Repetition of T1,T2,..T31,T1,T2, .. Repetition of T1,T2,..T32,T1,T2, .. FLS1 FLS0 Repetition of T1 timing Segment width setting bit 0 0 211/MCLK(128 μs) 0 1 1 1 0 1 212/MCLK(256 μs) 213/MCLK(512 μs) 214/MCLK(1024 μs) For operation with a machine clock (peripheral operation clock) of 16 MHz FLDX Bits for digit and segment output inversion 0 W : Write only : Initial value 1 Not inverted Inverted 387 CHAPTER 18 FL CONTROL CIRCUIT Table 18.3-2 Functions of the Display Control Circuit 2 (FLC2) Bits Bit name Bit 7 FLDX: Bit for digit and segment output inversion Function • • When this bit is set to "1", the digit and segment output levels for automatic fluorescent tube display are inverted. (*1) The output level for automatic LED display is not inverted. Bit 6 Bit 5 FLS1, FLS0: Segment width setting bit • Sets a segment width. Bit 4 to Bit 0 FLT4 to FLT0: Display timing setting bit • Sets a display timing value. (*1) (*1) *1: Make the settings while the automatic fluorescent tube and LED display are stopped. 388 18.3 FL Control Circuit Pins 18.3.3 Digit Setting Register (FLDG) This register is used to set the digit dimmer and digit display starting pin. This register is a write-only register and does not support bit operations. Byte access to this register is supported. ■ Digit Setting Register (FLDG) Figure 18.3-6 Digit Setting Register (FLDG) Bit 7 6 5 4 3 2 1 0 FLDM2 FLDM1 FLDM0 FLDS4 FLDS3 FLDS2 FLDS1 FLDS0 W W W W W W FLDS4 FLDS3 FLDS2 FLDS1 FLDS0 W Initial value 00000000B W Bit for specifying the start pin of digit display 0 0 0 0 0 Starts digit display from FIP00. 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 Starts digit display from FIP01. Starts digit display from FIP02. Starts digit display from FIP03. Starts digit display from FIP04. Starts digit display from FIP05. Starts digit display from FIP06. 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 FLDM2 FLDM1 FLDM0 Starts digit display from FIP29. Starts digit display from FIP30. Starts digit display from FIP31. Digit dimmer setting bit 0 0 0 2/16 0 0 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 4/16 6/16 8/16 10/16 12/16 14/16 W : Write only : Initial value 389 CHAPTER 18 FL CONTROL CIRCUIT Table 18.3-3 Functions of the Digit Setting Register (FLDG) Bits Bit name Function • • • Bit 7 to Bit 5 These bits specify the digit dimmer width. (*1) When set to 000B (2/16), the following waveform is generated. Digit output FLDM2, FLDM1, FLDM0: Digit dimmer setting bits 2/16 Bit 4 to Bit 0 FLDS4 to FLDS0: Setting bits for digit display start pin Segment width These bits specify the digit display start pin. *1: Make the settings while the automatic fluorescent tube and LED display is stopped. 390 (*1) 18.3 FL Control Circuit Pins 18.3.4 Digit Count Register (FLDC) The digit count register is used to set the segment dimmer and digit pin count. This register is a write-only register and does not support bit operations. Byte access to this register is supported. ■ Digit Count Register (FLDC) Figure 18.3-7 Digit Count Register (FLDC) Bit 7 6 5 4 3 2 1 0 Initial value FLSD2 FLSD1 FLSD0 FLDC4 FLDC3 FLDC2 FLDC1 FLDC0 00000000B W W W W W W W FLDC4 FLDC3 FLDC2 FLDC1 FLDC0 W Digit count setting bit 0 0 0 0 0 Setting for digit count 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 Setting for digit count 2 Setting for digit count 3 Setting for digit count 4 Setting for digit count 5 Setting for digit count 6 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 Setting for digit count 29 Setting for digit count 30 Setting for digit count 31 Setting for digit count 32 FLSD2 FLSD1 FLSD0 Segment dimmer setting bits 0 0 0 2/16 0 0 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 0 4/16 6/16 8/16 10/16 12/16 14/16 W : Write only : Initial value 391 CHAPTER 18 FL CONTROL CIRCUIT Table 18.3-4 Functions of the Digit Count Register (FLDC) Bits Bit name Bit 7 to Bit 5 FLSD2 to FLSD0: Segment dimmer setting bits Function Holds the settings for the segment dimmer waveform. (*1) SEGDT (bit 7 of address 0E0H to 0FFH) in the display RAM specifies the display timing that is to be applied to the segment dimmer. The segment dimmer register (SEGD) specifies segments. When the segment dimmer settings have not been made, set the segment dimmer register (SEGD) or SEGDT to all zeros. When value 000B (2/16) is set, the following waveform is generated. Output when the segment dimmer is set • • Bit 4 to Bit 0 FLDC4 to FLDC0: Digit count setting bit 2/16 Segment width when the dimmer is not set Specify a digit count. (*1) The settings of the digit display start bits (bit 0 to bit 4 of FLDG) take priority over the digit count settings. 32 pins (FIP00 to FIP31) can be specified by the digit count value. If the digit display start bit is set for FIP30, the maximum digit count becomes 2, and 2 will be assumed if a digit count of 3 or more is set. *1: Make the settings while the automatic fluorescent tube and LED display is stopped. Reference: The segment dimmer is set only for the segment output at specific times (T01 to T32). This makes it possible to set the dimmer for the segment in a specific digit; in other words, control of dimmer operation for a specific character is supported. 392 18.3 FL Control Circuit Pins 18.3.5 Port Register (FLPD) The 24 pins from FIP36 to FIP59 can be used as output ports by setting a value in the port register. When a pin is used as an output port, "0" must be set for that pin in the display RAM for all times before automatic fluorescent tube display is started. This register is a write-only register and does not support bit operations. Byte access to this register is supported. ■ Port Register (FLPD) Figure 18.3-8 Port Register (FLPD) Bit FLPD0 FLPD1 FLPD2 7 6 5 4 3 2 1 0 FIP43 FIP42 FIP41 FIP40 FIP39 FIP38 FIP37 FIP36 00000000B FIP51 FIP50 FIP49 FIP48 FIP47 FIP46 FIP45 FIP44 00000000B FIP59 FIP58 FIP57 FIP56 FIP55 FIP54 FIP53 FIP52 00000000B W W W W W W W W Initial value W: Write only ■ Port Register ❍ When a pin is used as a port Before automatic fluorescent tube display is started, "0" must be set for that pin in the display RAM for all times. When FLDX (bit for inverted digit/segment output) is set to specify display in reverse video, "1" must be set for that pin in the display RAM for all times before automatic fluorescent tube display is started. When the port register (FLPD) is set to "0", the Pch high dielectric output is switched off, and the VKK pin voltage is connected via the pull-down resistor. We recommend the addition of a diode clamping circuit. When the port register (FLPD) is set to "1", the Pch high dielectric output is switched on. ❍ When a pin is used for automatic fluorescent tube display A "0" must be set in the port register (FLPD) for the pin. Because the initial value of the port register (FLPD) is 0 at power-on and reset, automatic fluorescent tube display is assumed unless the register is set to another value. 393 CHAPTER 18 FL CONTROL CIRCUIT 18.3.6 Status/Authorization Register (FLST) This register includes the following types of bits: Bits for confirming fluorescent tube and automatic LED display, write authorization bits for display RAM and registers (display control register 1, display control register 2, digit setting register, digit count register, and segment dimmer setting register), and bits for preventing access to the display RAM and registers. Bit 7 and bit 6 are write-only, while bit 5, bit 1, and bit 0 are read-only bits. Bit operations are not supported for this register, but byte access is. ■ Status/Authorization Register (FLST) Figure 18.3-9 Status/Authorization Register (FLST) Bit 7 6 5 FLINI FL1WR FLDNE W W R 4 3 2 1 0 Initial value - - - FLFS FLLS 001XXX00B - - - R R FLLS Automatic LED display status bit 0 Stops automatic LED display. 1 Automatic LED display is in progress. FLFS Status bit for automatic fluorescent tube display 0 Stops automatic fluorescent tube display. 1 Automatic fluorescent tube display is in progress. FLDNE Bit for preventing display RAM and register access W R - 394 : : : : Read only Write only Undefined Initial value 0 Disables display RAM and register access. 1 Enables display RAM and register access. FL1WR Bit for authorizing writing of one byte to display RAM or registers. 0 Does not affect operation. 1 Authorizes writing of one byte to the display RAM or a register. FLINI Bit for authorizing writing to display RAM or registers. 0 Does not affect operation. 1 Authorizes writing to the display RAM and a register 18.3 FL Control Circuit Pins Table 18.3-5 Functions of the Status/Authorization Register Bits Bit name Bit 7 FLINI: Bit for authorizing writing to display RAM or registers Function • • • • • This bit authorizes writing to the display RAM or a register. When setting a value in the display RAM or a registers (display control register 1, display control register 2, digit setting register, digit count register, or segment dimmer setting register), the respective value changes after this bit is set to "1". Setting this bit to "0" has no effect on operation. This bit authorizes writing of one byte to the display RAM or a register. When setting a one-byte value in the display RAM or a register (display control register 1, display control register 2, digit setting register, digit count register, or segment dimmer setting register), the respective value changes after this bit is set to "1". Setting this bit to "0" has no effect on operation. When FLFS=1 or FLLS=1, writing of any new value to display control register 2, the digit setting register, the digit count register, or the segment dimmer setting register is not authorized. To authorize a write operation for these registers, select FLFE=0 and FLLE=0. Bit 6 FL1WR: Bit for authorizing writing of one byte to display RAM or registers • • Bit 5 FLDNE: Bit for preventing display RAM and register access Bit 4 to Bit 2 -: Undefined • • The value read from this bit is undefined. Setting this bit has no effect on operation. Bit 1 FLFS: Status bit for automatic fluorescent tube display • • • This bit indicates the status of automatic fluorescent tube display. When this bit is "1", automatic fluorescent tube display is active. When this bit is "0", automatic fluorescent tube display is inactive. Bit 0 FLLS: Automatic LED display status bit • • • This bit indicates the status of automatic LED display. When this bit is "1", automatic LED display is active. When this bit is "0", automatic LED display is inactive. • • • This bit prevents access to the display RAM and registers. When this bit is set to "1", reading from or writing to the display RAM and reading from or writing to any of the registers is allowed. When this bit is set to "0", access to the display RAM and all registers is prohibited (with the exception of reading from the status/authorization register). 395 CHAPTER 18 FL CONTROL CIRCUIT 18.3.7 Display RAM The display RAM contains the settings for digit and segment data based on the timing for automatic fluorescent tube display. Make settings for automatic LED display using the bits for the T01 and TP2 timing LED pins. Specify the time at which the segment dimmer operates in bit 7 of the addresses 1E0H to 11FFH. ■ Display RAM Figure 18.3-10 Display RAM Timing T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 Pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1100 H FL000 1101 H FL001 1102 H FL002 1103 H FL003 1104 H FL004 1105 H FL005 1106 H FL006 1107 H FL007 1108 H FL008 1109 H FL009 110A H FL010 110B H FL011 110C H FL012 110D H FL013 110E H FL014 110F H FL015 1110 H FL016 1111 H FL017 1112 H FL018 1113 H FL019 1114 H FL020 1115 H FL021 1116 H FL022 1117 H FL023 1118 H FL024 1119 H FL025 111A H FL026 111B H FL027 111C H FL028 111D H FL029 111E H FL030 111F H FL031 FIP08 FIP09 FIP10 FIP11 FIP12 FIP13 FIP14 FIP15 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 1120 H FL032 1121 H FL033 1122 H FL034 1123 H FL035 1124 H FL036 1125 H FL037 1126 H FL038 1127 H FL039 1128 H FL040 1129 H FL041 112A H FL042 112B H FL043 112C H FL044 112D H FL045 112E H FL046 112F H FL047 1130 H FL048 1131 H FL049 1132 H FL050 1133 H FL051 1134 H FL052 1135 H FL053 1136 H FL054 1137 H FL055 1138 H FL056 1139 H FL057 113A H FL058 113B H FL059 113C H FL060 113D H FL061 113F H FL062 1140 H FL063 FIP16 FIP17 FIP18 FIP19 FIP20 FIP21 FIP22 FIP23 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 FIP24 FIP25 FIP26 FIP27 FIP28 FIP29 FIP30 FIP31 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 117F H FL127 FIP32 FIP33 FIP34 FIP35 FIP36 FIP37 FIP38 FIP39 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 119F H FL159 FIP40 FIP41 FIP42 FIP43 FIP44 FIP45 FIP46 FIP47 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 FIP48 FIP49 FIP50 FIP51 FIP52 FIP53 FIP54 FIP55 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 11DF H FL223 FIP56 FIP57 FIP58 FIP59 bit0 bit1 bit2 bit3 11FF H FL255 FL064 FL065 FL066 FL067 1160 H FL096 1161 H FL097 1180 H FL128 1181 H FL129 11A0 H FL160 11A1 H FL161 11BF H FL191 11E0 H FL224 11E1 H FL225 See Figure 18.4.8, "Segment Dimmer-Register (SEGD)." Set a time for dimmer operation. The time is set with a value of "1". The initial value is undefined. 11C0 H FL192 11C1 H FL193 396 115F H FL095 SEGDT bit7 1140 H 1141 H 1142 H 1143 H FIP00 FIP01 FIP02 FIP03 FIP04 FIP05 FIP06 FIP07 Also used for LED display. Display RAM can be read and written, but bit operations are not supported. Byte access to the display RAM is supported. 18.3 FL Control Circuit Pins 18.3.8 Segment Dimmer Setting Register (SEGD) Dimming can be set for any time and any segment of the fluorescent tube. Using the segment dimmer setting register, set a timing for the segment with bit 7 of 11E0H to 11FFH in the display RAM. This register is a write-only register and does not support bit operations. Write data to this register while automatic fluorescent tube and LED display are stopped. Byte access is supported for this register. ■ Segment Dimmer Setting Register (SEGD) Figure 18.3-11 Segment Dimmer Setting Register (SEGD) Bit 7 SEGD0 FIP07 SEGD1 6 5 4 3 2 1 0 FIP06 FIP05 FIP04 FIP03 FIP02 FIP01 FIP00 XXXXXXXXB FIP15 FIP14 FIP13 FIP12 FIP11 FIP10 FIP09 FIP08 XXXXXXXXB SEGD2 FIP23 FIP22 FIP21 FIP20 FIP19 FIP18 FIP17 FIP16 XXXXXXXXB SEGD3 FIP31 FIP30 FIP29 FIP28 FIP27 FIP26 FIP25 FIP24 XXXXXXXXB SEGD4 FIP39 FIP38 FIP37 FIP36 FIP35 FIP34 FIP33 FIP32 XXXXXXXXB SEGD5 FIP47 FIP46 FIP45 FIP44 FIP43 FIP42 FIP41 FIP40 XXXXXXXXB SEGD6 FIP55 FIP54 FIP53 FIP52 FIP51 FIP50 FIP49 FIP48 XXXXXXXXB SEGD7 - - - - FIP59 FIP58 FIP57 FIP56 XXXXXXXXB W W W W W W W W Initial value W: Write only ■ Segment Gradation Display (Segment Dimmer) Specify a segment using registers SEGD0 to SEGD7. Specify the segment by setting a value of "1". Set a timing with bit 7 of 11E0H to 11FFH in the display RAM. Specify the timing by writing a value of "1". The SEGD0 to SEGD7 bits for digit pins are ignored. Dimmer operation can be specified more than once. Note: Because the initial values of SEGD0 to SEGD7 and 11E0H to 11FFH of the display RAM are undefined, set these values before starting with display. 397 CHAPTER 18 FL CONTROL CIRCUIT 18.4 FL Control Circuit Operation This section explains the operation of automatic fluorescent tube and LED display. ■ Assignment of Automatic Fluorescent Tube Display Digits and Segments and Automatic LED Display Pins Automatic fluorescent tube display digits can be specified using pins FIP0 to FIP31. These digits are consecutively set according to the count specified in the digit count setting bits of the digit count register, starting with the pin that is specified in the digit display starting pin setting bits of the digit setting register. Figure 18.4-1 "Example of assignment for LED, Digit, and Segment Display" shows an example of the resulting assignment. When both the digit display start setting bit and digit count setting bit are set, the digit display start setting bit has priority. (In item [3] of Figure 18.4-1 "Example of assignment for LED, Digit, and Segment Display", the digit count setting bits are set to 1FH (32 digits), but 16 digit pins are used in the actual operation.) All pins after pins that are used for setting digits become segment pins. When the value expressed in the digit display pin setting bits is larger than 17H, all pins from FIP17 to the one before the pin specified in the digit display starting pin selection bit are used for segments. (See item [4] in Figure 18.4-1 "Example of assignment for LED, Digit, and Segment Display.") The automatic LED display pins are set in the LED00 to LED16 registers that are not used for automatic fluorescent tube display. Figure 18.4-1 Example of assignment for LED, Digit, and Segment Display FIP48 FIP47 FIP56 FIP55 FIP59 FIP40 FIP39 FIP48 FIP47 FIP56 FIP55 FIP59 FIP56 FIP55 FIP59 FIP56 FIP55 FIP59 FIP56 FIP55 FIP59 FIP32 FIP31 FIP24 FIP23 FIP48 FIP47 28 segments FIP48 FIP47 4 digits FIP40 FIP39 FIP32 FIP31 FIP24 FIP23 FIP17 FIP16 LED15 FIP17 to FIP27 are used for segments. 28 segments Segment pin FIP48 FIP47 FIP40 FIP39 FIP32 FIP31 FIP28 FIP24 FIP23 FIP17 LED16 LED15 LED10 Digit pin FIP40 FIP39 FIP32 FIP31 FIP24 FIP23 FIP17 FIP16 FIP15 LED10 LED07 LED06 FIP40 FIP39 FIP32 FIP31 FIP24 FIP23 FIP17 FIP16 FIP15 FIP10 LED07 LED06 LED output pin 398 16 digits 1 LED common 16 segments LED01 LED00 Digit display starting 1C H pin selection bit Digit count 03 H setting bit FIP07 FIP06 [4] 28 segments 1 LED common 15 segments LED01 LED00 Digit display starting 10H pin selection bit Digit count 1FH setting bit 52 segments 32 digits FIP01 FIP00 [3] FIP17 FIP16 FIP15 FIP10 [2] Digit display starting 00H pin selection bit Digit count 1FH setting bit FIP10 4 digits FIP07 LED06 1 LED common 6 LED segments LED01 LED00 Digit display starting 07 H pin selection bit Digit count 03H setting bit FIP07 FIP06 FIP01 FIP00 [1] 18.4 FL Control Circuit Operation ■ Reading from/Writing to Registers or Display RAM in the FL Control Circuit Display RAM and the following registers support byte access, but not bit operations. • Registers in the FL control circuit • Display control register 1 (FLC1) • Display control register 2 (FLC2) • Digit setting register (FLDG) • Digit count register (FLDC) • Segment dimmer setting registers (SEGD0 to SEGD7) • Port registers (FLPD0 to FLPD2) • Status/authorization register (FLST) Writing to the display RAM and the registers in the FL control circuit can only be performed when a "1" is set in the status/authorization register (FLST) display RAM and the bit for preventing register access (FLDNE). Reading from the display RAM can be performed even when the bit for preventing register access (FLDNE) is set to "1". After writing to the display RAM and any register other than the status/authorization register (FLST), the display RAM/register write authorization bit (FLINI) in the status/authorization register (FLST) must be set to "1". The following diagram explains the operation. ❍ At initialization Figure 18.4-2 At Initialization After reset is canceled ↓ Initial value ="1" Confirm the setting of "1" Initial setting Write to register display RAM 1 FLDNE bit 0 Authorized in descending order of address value. Therefore, operation starts after write operations for the FLCI register have been authorized. Set FLINI Set FLINI in the FLST in the FLST register to register to "1" "1" Writing is prohibited, and any attempts to write are ignored. About 137 μs for 16 MHz machine clock Authorization of writing to display RAM and all registers FL display LED display Port operation started *1 In this interval, writing to all registers and the display RAM is prohibited. Reading of display RAM is also prohibited. The FLST register can only be accessed for reading. 399 CHAPTER 18 FL CONTROL CIRCUIT ❍ When segment data (multiple bytes) is overwritten during automatic fluorescent tube display Figure 18.4-3 When Segment Data Is Overwritten During Automatic Fluorescent Tube Display (for Multiple Bytes) Confirm the setting of "1" Overwrite display RAM segment data or data of FLPD0 to FLPD2 Set FLINI of FLST to "1" 1 FLDNE bit 0 Up to 153μs for 16 MHz machine clock Authorization of writing to display RAM FL LED changed Port operation *1 *2 After operation (FL or LED) has started, writing to FLC2, FLDG, FLDC, and SEGD0 to SEGD7 cannot be authorized. The last one-byte writing operation to the FLST register FL1WR is authorized. The following diagram explains this operation. ❍ Stop while operation is in progress or start from stop state (for 1 byte) Figure 18.4-4 Stop While Operation Is in Progress or Start from Stop State (for 1 Byte) Confirm the setting of "1" 1 FLDNE bit 0 Overwrite FLC1 register data Set FL1WR of FLST to "1" From operation From stop to to stop state operating state Maximum of 10 μs Maximum of 1 μs for 16 MHz for 16 MHz machine clock machine clock Authorization of writing to FLCI register FL Operation start/stop LED *1 The following diagram provides an example for combined setting of FL1WR of the FLST register and FLINI of the FLST register. Note that the value of FLINI can only be changed after a reset. 400 18.4 FL Control Circuit Operation ❍ Setting FL1WR after setting FLINI Figure 18.4-5 Setting FL1WR after Setting FLINI Confirm the setting of "1" Overwrite register or display RAM Set FLINI of the FLST register to "1" Confirm the setting of "1" Set FL1WR of the FLST register to "1" 1 FLDNE bit 0 When both FLINI and FL1WR are set to "1", FLINI has priority. Maximum of 153 μs Maximum of for 16 MHz 10 μs for 16 MHz machine clock machine clock Authorization of writing to all of the display RAM When FL or LED is inactive, writing to all registers is authorized. Only the last one-byte write operation is authorized. *1 ■ Start and Stop Timings of Automatic Fluorescent Tube Display Automatic fluorescent tube display starts with timing point T1. When automatic fluorescent tube display is stopped, output stops after the output of the current segment output has been completed. Figure 18.4-6 Example of Start and Stop Timing of Automatic Fluorescent Tube Display T1 T2 Digit T3 T4 Segment FLFS FLDNE FLC1 register FLFE starts FL display and FLST register FL1WR authorizes it. FLC1 register FLFE stops FL display and FLST register FL1WR authorizes it. Starting of automatic Stopping of automatic fluorescent tube display fluorescent tube display FLC1 register FLFE starts FL display and FLST register FL1WR authorizes it. Starting of automatic fluorescent tube display 401 CHAPTER 18 FL CONTROL CIRCUIT ■ Start and Stop Timing of Automatic LED Display Up to the first 5 milliseconds after the start of automatic LED display, "L" level (the Pch open drain output is off) is output from common and segment output. Next, the data for the timing point of T1 is output as segment output when the common output (LED0) is at the "H" level. When automatic LED display stops, the common and segment output switch to "L" level after authorization of writing to the registers. Figure 18.4-7 Start and Stop Timings of Automatic LED Display Maximum time 5 ms LEC1 to 16 output T 1 T 2 LDE0 (common output) FLLS FLDNE FLC1 register FLLE starts LED display and FLST register FL1WR authorizes it. Starting of automatic LED display FLC1 register FLFE stops LED display and FLST register FL1WR authorizes it. FLC1 register FLLE starts LED display and FLST register FL1WR authorizes it. Stopping of automatic Starting of automatic LED display LED display ■ Operation in Stop Mode and Sleep Mode ❍ In stop mode The FL control circuit is reset in stop mode. (All Pch high dielectric outputs are switched off.) After stop mode is released, initialization must be performed. ❍ In sleep mode The FL control circuit is operational in sleep mode. To enter low-power mode, such operations as stopping automatic display must be performed before sleep mode is set. 402 CHAPTER 19 WATCH CLOCK OUTPUT This chapter describes the functions and operations of MB90M405 series watch clock output. 19.1 "Overview of the Watch Clock Output Circuit" 19.2 "Configuration of the Watch Clock Output Circuit" 19.3 "Watch Clock Output Control Register (TMCS)" 403 CHAPTER 19 WATCH CLOCK OUTPUT 19.1 Overview of the Watch Clock Output Circuit The watch clock output circuit divides the oscillation clock by the timebase timer and outputs the specified divided clock externally. One of the divisions 32, 64, 128, and 256 of the oscillation clock can be selected. ■ Watch Clock Output Circuit The watch clock output circuit is disabled during a reset or in stop mode and in enabled in normal run mode, sleep mode, and pseudo watch mode. Table 19.1-1 Watch Clock Output Modes PLL_Run Main_Run Sleep Pseudo watch STOP Reset o o o o x x Operating status Notes: The clock cannot be output correctly if the timebase timer is cleared while the watch clock output circuit is in use. For information about the conditions for clearing the timebase timer, see Chapter 10, "Timebase Timer". 404 19.2 Configuration of the Watch Clock Output Circuit 19.2 Configuration of the Watch Clock Output Circuit The watch clock output circuit consists of the following blocks: • Watch clock selection circuit • Watch clock output control register (TMCS) ■ Block Diagram of the Watch Clock Selection Circuit Figure 19.2-1 Block Diagram of the Watch Clock Selection Circuit Watch clock selection circuit Selector X0 Watch clock output Oscillation circuit X1 Timebase timer Divide-by-2 circuit 405 CHAPTER 19 WATCH CLOCK OUTPUT 19.3 Watch Clock Output Control Register (TMCS) The watch clock output control register (TMCS) sets the watch clock division ratio. ■ Watch Clock Output Control Register (TMCS) Figure 19.3-1 Watch Clock Output Control Register (TMCS) Bit 15 14 13 12 11 10 9 8 Initial value - - - - - TEN TS1 TS0 XXXXX000B - - - - - R/W R/W R/W TS1 TS0 0 0 1 1 0 1 0 1 Watch clock division ratio setting bit Divide by 32 Divide by 64 Divide by 128 Divide by 256 Output cycle for HCLK = 4.19 MHz TEN Watch clock output enable bit 0 Output disabled 1 Output enabled 7.45 ns 3.72 ns 1.86 ns 0.93 ns R/W : Read/write enabled : Undefined bit : Initial value HCLK : Oscillation clock frequency Table 19.3-1 Functions of the I2C Status Register (IBSR) Bits Bit name bit15 to bit11 -: Undefined bit bit10 TEN: Watch clock output enable bit bit9 bit8 TS1, TS0: Time clock division ratio setting bit Function • • The reading value read from this bit is undefined. The value set for this bit does not affect operation. • This bit enables watch clock output. To use this function, be sure to specify a port in ADER0 and to specify output from the port in DDRA. • Set TS1 and TS2, and specify output from the port to output the clock for the watch clock. Note: The first waveform that is output when the TEN bit is set to Enabled may be different from the actually specified output waveform because the watch clock is started asynchronously with the timebase timer. 406 CHAPTER 20 DELAYED INTERRUPT GENERATOR MODULE This chapter describes the functions and operation of the MB90M405 series delayed interrupt generator module. 20.1 "Overview of the Delayed Interrupt Generator Module" 20.2 "Delayed Interrupt Cause/Cancel Register (DIRR)" 20.3 "Operation of the Delayed Interrupt Generator Module" 20.4 "Precautions to Follow when Using the Delayed Interrupt Generator Module" 407 CHAPTER 20 DELAYED INTERRUPT GENERATOR MODULE 20.1 Overview of the Delayed Interrupt Generator Module The delayed interrupt generator module outputs interrupt requests for task switching. By using this module, interrupt requests for task switching can be output and canceled for the MB90M405 series CPU via software. ■ Block Diagram of the Delayed Interrupt Generator Module Internal data bus Figure 20.1-1 Block Diagram of the Delayed Interrupt Generator Module 408 Delayed interrupt request register/decoder Interrupt cause latch 20.2 Delayed Interrupt Cause/Cancel Register (DIRR) 20.2 Delayed Interrupt Cause/Cancel Register (DIRR) This section explains the delayed interrupt cause/cancel register (DIRR). ■ Delayed Interrupt Cause/Cancel Register (DIRR) Figure 20.2-1 Delayed Interrupt Cause/Cancel Register (DIRR) Bit 15 14 13 12 11 10 9 8 Initial value R0 XXXXXXX0B R/W R/W X - : Read/write : Undefined : Undefined bit Table 20.2-1 Functional Explanation of Each Bit of the Delayed Interrupt Cause/Cancel Register (DIRR) Bit name Function bit15 to bit9 -: Undefined bit • • When these bits are read, the values are undefined. Writing to these bits does not affect operation. bit8 R0: Delayed interrupt request output bit • • • • This bit sets the generation/cancel of a delayed interrupt request. When this bit is "1", a delayed interrupt request is output. When this bit is "0", the delayed interrupt request is cleared. When a reset is specified, interrupt causes are canceled (cleared to "0"). 409 CHAPTER 20 DELAYED INTERRUPT GENERATOR MODULE 20.3 Operation of the Delayed Interrupt Generator Module When the delayed interrupt request output bit (R0) of the delayed interrupt cause/ cancel register (DIRR) is set to "1" using software, a delayed interrupt request is output to the interrupt controller. ■ Operation of the Delayed Interrupt Generator Module When the delayed interrupt request output bit (R0) of the delayed interrupt cause/cancel register (DIRR) is set to "1" using software, an interrupt request is output to the interrupt controller. If interrupt requests other than the delayed interrupt have lower priorities or there is no interrupt request other than the delayed interrupt request, the interrupt controller outputs an interrupt request to the CPU. The CPU compares the interrupt request level with the interrupt level mask register (ILM) in the processor status register (PS). If the interrupt request level is higher than the interrupt level mask register (ILM), the hardware imbedded processing microprogram is activated after the instruction currently being executed is completed, to execute the delayed interrupt processing routine. If the delayed interrupt request output bit (R0) of the delayed interrupt cause/cancel register (DIRR) is set to "0" in the interrupt processing routine, the delayed interrupt cause is cleared and the task is switched. Figure 20.3-1 Operation of the Delayed Interrupt Generator Module Delayed interrupt generator module Interrupt controller WRITE MB90M405 series CPU Other requests ICRyy IL CMP DIRR CMP ICRxx ILM NTA DIRR IL ILM CMP ICR 410 : : : : : Delayed interrupt cause/cancel register Interrupt level setting bit in the interrupt control register (ICR) Interrupt level mask register in PS Comparator Interrupt control register 20.4 Precautions to Follow when Using the Delayed Interrupt Generator Module 20.4 Precautions to Follow when Using the Delayed Interrupt Generator Module This section explains the precautions to follow when using the delayed interrupt generator module. ■ Precautions to Follow when Using the Delayed Interrupt Generator Module ❍ Delayed interrupt request If the delayed interrupt request output bit (R0) of the delayed interrupt cause/cancel register (DIRR) is not set to "0" after interrupt processing is completed using an interrupt processing routine or while an interrupt processing routine is being executed, it is not possible to return from the interrupt processing. 411 CHAPTER 20 DELAYED INTERRUPT GENERATOR MODULE 412 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION This chapter describes the address match detection function of the MB90M405 series and its operations. 21.1 "Overview of the Address Match Detection Function" 21.2 "Registers of the Address Match Detection Function" 21.3 "Operation of the Address Match Detection Function" 21.4 "Example of Using the Address Match Detection Function" 413 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.1 Overview of the Address Match Detection Function If the program address matches the value set in the address match detection register, the instruction code to be read by the CPU is replaced with an INT9 instruction code. By performing processing using an INT #9 interrupt routine, a program patch application function can be implemented. ■ Block Diagram of the Address Match Detection Function Internal data bus Address latch 414 Address detection register MB90M405 series CPU core Enable bit Detection bit Reset Comparison Figure 21.1-1 Block Diagram of the Address Match Detection Function Set 21.2 Registers of the Address Match Detection Function 21.2 Registers of the Address Match Detection Function This section shows a list of registers of the address match detection function. ■ List of Registers of the Address Match Detection Function Figure 21.2-1 List of Registers of the Address Match Detection Function bit23 bit8 bit7 bit0 PADR0 (program address detection register; upper/middle/lower) PADR1 (program address detection register; upper/middle/lower) PACSR (program address detection control status register) 415 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.2.1 Program Address Detection Register for Upper, Middle, and Lower Parts of Address (PADR0/PADR1) The program address detection register for upper, middle, and lower parts of an address (PADR0/PADR1) is used to set an address for comparison. ■ Program Address Detection Register for Upper, Middle and Lower Parts of an Address (PADR0/ PADR1) Figure 21.2-2 Program Address Detection Register for Upper, Middle, and Lower Parts of an Address (PADR0/PADR1) PADR0 bit23 bit16 bit15 bit8 bit7 bit0 Upper Middle Lower R/W PADR1 R/W Initial value XXXXXXXXXH R/W bit23 bit16 bit15 bit8 bit7 bit0 Upper Middle Lower R/W R/W XXXXXXXXXH R/W R/W : Read/write enabled X : Undefined If the corresponding interrupt enable bit of the program address detection control status register (ACSR) is set to "1", the program address is compared with the value stored in the program address detection register for the upper, middle, and lower parts of an address (PADR0/ PADR1). If the program address value (PC value) matches the value stored in the program address detection register for upper, middle, and lower parts of an address (PADR0/PADR1), the corresponding interrupt flag bit is set to "1" and an INT9 instruction is output. If the interrupt enable bit is set to "0", no INT9 instruction is output. The following table lists the correspondence between the program address detection control status register (PASCR) and the interrupt request enable bits and the interrupt request flag bits. 416 Address detection register Interrupt enable bit Interrupt request flag bit PADR0 AD0E AD0D PADR1 AD1E AD1D 21.2 Registers of the Address Match Detection Function 21.2.2 Program Address Detection Control Status Register (PACSR) The program address detection control status register (PACSR) is used to perform the interrupt control of the address match detection function. ■ Program Address Detection Control Status Register (PACSR) Figure 21.2-3 Program Address Detection Control Status Register (PACSR) Bit 7 6 5 4 3 RESV RESV RESV RESV AD1E R/W R/W X R/W R/W R/W R/W 2 1 0 AD1D AD0E AD0D R/W R/W R/W Initial value 00000000B : Read/write : Undefined Table 21.2-1 Functional Explanation of Each Bit of the Program Address Detection Control Status Register (PACSR) Bit name bit7 to bit4 RESV: Reserved bit bit3 AD1E: PADR1 interrupt request enable bit bit2 AD1D: PADR1 interrupt request flag bit Function • Always set "0". • • This bit enables an interrupt of PADR1. When this bit is "1", the program address detection register (PADR1) and the program address are compared. If the program address detection register (PADR1) matches the program address, the PADR1 interrupt flag bit (AD1D) is set to "1" and an INT9 instruction is output. • • This bit enables an interrupt request of PADR1. This bit is set to "1" when the program address detection register (PADR1) and the program address are compared and match. While the PAD1 request enable bit (AD1E) is "1", setting this bit to "1" outputs an INT9 instruction. Setting this bit to "0"clears it to "0". Setting this bit to "1" has no effect on operation. • • • bit1 bit0 AD0E: PADR0 interrupt request enable bit AD0D: PADR0 interrupt request flag bit • • This bit enables an interrupt of PADR0. When this bit is "1", the program address detection register (PADR0) value and the program address are compared. If both match, the interrupt flag bit (AD0D) of the PADR0 is set to "1" and an INT9 instruction is output. • • This bit enables an interrupt request of PADR0. This bit is set to "1" when the program address detection register (PADR1) and the program address are compared and match. While the PAD0 request enable bit (AD0E) is "1", setting this bit to "1" outputs an INT9 instruction. Setting this bit to "0" clears it to "0". Setting this bit to "1" does not affect operation. • • • 417 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 21.3 Operation of the Address Match Detection Function This section explains the operation of the address match detection function. ■ Operation of the Address Match Detection Function If the program address matches the value set in the address match detection register, the instruction code to be read by the CPU is replaced with an INT9 instruction code (01H). When the CPU executes the instruction at the specified program address, the INT9 instruction is executed. By performing processing using an INT #9 interrupt routine, a program patch application function can be implemented. There are two program address detection registers (PADR0/PADR1), each of which has an interrupt enable bit (AD1E, AD0E) and an interrupt flag bit (AD1D, AD0D). If the interrupt enable bit (AD1E, AD0E) is set to "1", the value stored in the address detection register and the program address are compared. If they match, the interrupt flag bit (AD1D, AD0D) is set to "1", and the instruction code to be read by the CPU is replaced with an INT9 instruction code. Setting the interrupt flag bit (AD1D, AD0D) to "0"clears it to "0". Note: The address detection function does not work correctly if a program address after the 1st byte of the instruction is set in the address detection register. Change the address detection register after setting the interrupt enable bit to "0". If the setting of the address detection register is changed while the interrupt enable bit is set to "1", an address detection may be mistakenly performed while making settings. 418 21.4 Example of Using the Address Match Detection Function 21.4 Example of Using the Address Match Detection Function This section contains example of Using the Address Match Detection Function. ■ System Configuration Figure 21.4-1 System Configuration Example MCU E2PROM MB90M405 series SIN ■ E2PROM Memory Map Table 21.4-1 E2PROM Memory Map Address Meaning 0000H Number of bytes of patch program No. 0 (0 for no program error) 0001H Bit 7 to bit 0 of program address No. 0 0002H Bit 15 to bit 8 of program address No. 0 0003H Bit 24 to bit 16 of program address No. 0 0004H Number of bytes of patch program No. 1 (0 for no program error) 0005H Bit 7 to bit 0 of program address No. 1 0006H Bit 15 to bit 8 of program address No. 1 0007H Bit 24 to bit 16 of program address No. 1 0010H+ Number of bytes of patch program No. 0 Original of patch program No. 0 ■ Initial State The contents of E2PROM are all 0s. 419 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION ■ INT9 Interrupt An interrupt routine finds the address detection cause for which an interrupt request was output by referencing the interrupt flag bits (AD1D, AD0D) of the detection control status register (PACSR). The routine then causes a branch to the program from which the interrupt request was output. If a branch to the program is caused, information saved on the stack due to the interrupt becomes invalid, and the interrupt flag bits (AD1D, AD0D) are cleared to "0". Figure 21.4-2 System Configuration Example FFFFFFH ROM PC = generated address Abnormal program External E2PROM Number of program bytes Register set for program patch Interrupt-generated address Modification program address Data transfer using UART Modification program RAM 000000H 420 21.4 Example of Using the Address Match Detection Function Figure 21.4-3 Flowchart of Program Patch Processing Reset INT9 Read 0000H of 0000H=00H E2PROM To patch program JMP000400H 2 0000H(E PROM) 0000H Execute patch program 000400H to 000480H 00H Read address 0001H to 0003H(E2PROM) MOV PADR0(MCU) End patch program JMP FF0050H Read patch program 0010H to 0090H(E2PROM) MOV 000400H to 000480H(MCU) Enable patch processing MOV PACSR,#02H Executes the normal program NO PC=PADR0 YES INT9 FFFFFFH FF8050H E2 PROM ROM Abnormal program FF8000H FFFFH FF0000H 0090H Patch program 0010H 001100H Stack area 0003H Middle program address: 80H 0002H 0001H RAM area Lower program address: 50H 000480H Patch program RAM 000400H Upper program address:FFH RAM/register area 000100H Number of bytes of patch program: 80H 0000H I/O area 000000H 421 CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION 422 CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE This chapter describes the function and operation of the MB90M405 series ROM mirroring function selection module. 22.1 "Overview of the ROM Mirroring Function Selection Module" 22.2 "ROM Mirroring Function Selection Register (ROMM)" 423 CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE 22.1 Overview of the ROM Mirroring Function Selection Module The ROM mirroring function selection module can access ROM data in bank FF from bank 00 by setting its register. The ROM mirroring function enables access from the target area (FF4000H to FFFFFFH) to the I/O area or the RAM area without bank accesses. ■ Block diagram of the ROM mirroring function selection module Figure 22.1-1 Block Diagram Internal data bus ROM mirroring function selection Address Address area FF bank 00 bank Data ROM 424 22.2 ROM Mirroring Function Selection Register (ROMM) 22.2 ROM Mirroring Function Selection Register (ROMM) This section explains the register in the ROM mirroring function selection module. ■ ROM Mirroring Function Selection Register (ROMM) Figure 22.2-1 ROM Mirroring Function Selection Register (ROMM) Bit 15 14 13 12 -11 10 9 8 Initial value - - - - - - - MI XXXXXXX1B - - - - - - - W W : Write only X : Undefined - : Undefined bit Note: Do not set the ROM mirroring function selection register while accessing the addresses "004000H to 00FFFFH". Table 22.2-1 Functional Explanation of the ROM Mirroring Function Selection Register (ROMM) Bit name bit15 to bit9 bit8 Function -: Undefined bit • • The values read from these bits are undefined. Setting these bits to a new value does not affect operation. MI: ROM mirroring function setting bit • • • This bit is used to set the ROM mirroring function. When this bit is "1", ROM data in bank FF can be read from bank 00. When this bit is "0", ROM data in bank FF cannot be read from bank 00. Note: The ROM mirroring function accesses addresses 004000H to 00FFFFH from addresses FF4000H to FFFFFH. Therefore, addresses FF0000H to FF3FFFH cannot be accessed when use of the ROM mirroring function is set. MB90M407/M407A MB90M408/M408A MB90MF408/MF408A MB90MV405 Address 1 FE8000H FE0000H FE0000H FE0000H Address 2 001100H 001100H 001100H 001100H 425 CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE Figure 22.2-2 Memory Space Address FFFFFFH FF4000H Address 1 001000H 004000H Address 2 000100H 0000C0H 000000H 426 ROM area ROM area ROM mirroring area RAM area RAM area I/O area I/O area When MI="1" When MI="0" Internal area CHAPTER 23 1M-BIT FLASH MEMORY This chapter describes the functions and operations of the MB90M405 series 1M-bit flash memory. 23.1 "Overview of the 1M-Bit Flash Memory" 23.2 "Registers and Sector Configuration of the Flash Memory" 23.3 "Flash Memory Control Status Register (FMCS)" 23.4 "Starting the Automatic Algorithm of the Flash Memory" 23.5 "Detailed Description of Flash Memory Writing and Deletion" 427 CHAPTER 23 1M-BIT FLASH MEMORY 23.1 Overview of the 1M-Bit Flash Memory The 1M-bit flash memory is allocated in banks FEH and FFH on the CPU memory map. Like mask ROM, it does support read access and program access from the CPU because of the flash memory interface circuit function. Data can be written to or deleted from the flash memory via the flash memory interface circuit using CPU instructions. Because this approach enables rewriting the flash memory when it is installed under control of the built-in CPU, programs and data can be changed more efficiently. ■ Writing Data to or Deleting Data from the Flash Memory You can write data to or delete data from the flash memory in one of the following two ways: 1. Dedicated serial programmer (AF220 manufactured by YDC) 2. Writing and deletion using a program This section describes the second option of executing a program. ■ Features of the 1M-bit Flash Memory • Configuration of 128K words x 8K or 64K words x 16 bits (16K + 8K + 8K + 32K + 64K) sector • Automatic program algorithm (equivalent to Embedded Algorithm: MBM29F400TA) • Function for temporarily stopping and restarting deletion • Detection of the completion of writing and deletion using CPU interrupts • Compatibility with JEDEC standard commands • Sector-by-sector deletion (Any combination of sectors) • 10,000 writes and deletes guaranteed Embedded Algorithm is a trademark of Advanced Micro Devices Corporation. ■ Writing to and Deletion from the Flash Memory Writing to and deletion from the flash memory must not be performed at the same time. To write data to or delete data from the flash memory, first copy the program to RAM and then execute the copied program in RAM. For more information, see Section 23.5.2 "Writing Data to the Flash Memory". 428 23.2 Registers and Sector Configuration of the Flash Memory 23.2 Registers and Sector Configuration of the Flash Memory Figure 23.2-1 "Sector Configuration of the 1M-bit Flash Memory" shows the registers and sector configuration of the flash memory. ■ Registers of the Flash Memory ❍ Flash memory control status register (FMCS) Bit 7 6 5 INTE RDYINT WE R/W R/W R/W 4 3 2 1 0 RDY Reserved LPM1 Reserved LPM0 R W R/W W Initial value 00000000B R/W R/W : Read/write enabled R : Read only W : Write only ■ Sector Configuration Figure 23.2-1 "Sector Configuration of the 1M-bit Flash Memory" shows the sector configuration of the 1M-bit flash memory. In this figure, high-order and low-order addresses are shown for each sector. For access from the CPU, SA0 is stored in the FE bank register and SA1 to SA4 are stored in the FF bank register. Figure 23.2-1 Sector Configuration of the 1M-bit Flash Memory Flash memory CPU address High order SA4(16 KB) Low order High order SA3(8 KB) Low order High order SA2(8 KB) Low order High order SA1(32 KB) Low order High order SA0(64 KB) Low order FFFFFFH FFC000H FFBFFFH FFA000H FF9FFFH FF8000H FF7FFFH FF0000H FEFFFFH FE0000H 429 CHAPTER 23 1M-BIT FLASH MEMORY 23.3 Flash Memory Control Status Register (FMCS) This section describes the functions of the flash memory control status register (FMCS). ■ Flash Memory Control Status Register (FMCS) Figure 23.3-1 Flash Memory Control Status Register (FMCS) Bit 7 6 5 INTE RDYINT WE R/W R/W R/W 4 3 2 1 0 Initial value RDY Reserved LPM1 Reserved LPM0 R W R/W W 00000000B R/W LPM1 LPM0 Low power consumption mode setting bits 0 0 0 0 1 1 0 0 Ordinary power consumption mode (internal operating frequency of 16 MHz or less) Power consumption mode 1 (internal operating frequency of 4 MHz or less) Power consumption mode 2 (internal operating frequency of 8 MHz or less) Power consumption mode 3 (internal operating frequency of 10 MHz or less) Reserved bit Reserved Set this bit to "0". RDY Write/delete operation in progress 1 Write/delete operation completed (write/delete operation enabled) WE Write/delete operation disabled 1 Write/delete operation enabled 430 Read/write enabled Read only Write only Initial value Write/delete operation completion flag bit 0 Write/delete operation in progress 1 Write/delete operation completed (interrupt request generated) INTE : : : : Write/delete operation enable bit 0 RDYINT R/W R W Write/delete status bit 0 Interrupt request enable bit 0 Interrupt disabled when writing or deletion is completed 1 Interrupt enabled when writing or deletion is completed 23.3 Flash Memory Control Status Register (FMCS) Table 23.3-1 Functions of the Flash Memory Control Status Register (FMCS) Bits Bit name Function • bit7 INTE: Interrupt request enable bit • • • • bit6 RDYINT: Write/delete operation completion flag bit • • • • bit5 WE: Write/delete operation enable bit • This bit enables the output of an interrupt request to the CPU when a flash memory write or delete operation is completed. An interrupt request is output if this bit is set to "1" and the RDYINT bit is set to "1". No interrupt request is output if this bit is set to "0" and the RDYINT bit is set to "1". When a flash memory write or delete operation is completed, this bit is set to "1", enabling a flash memory write or delete operation. If this bit is set to "0", this bit is cleared to "0", disabling flash memory write or delete operations. Setting this bit to "1" does not affect operation. This bit is also set to "1" when the automatic algorithm (see Section 23.4 "Starting the Automatic Algorithm of the Flash Memory") of the flash memory has been completed. Read-modify-write (RMW) instructions always return "1" for this bit. If this bit is set to "1", writing to or deletion from the flash memory is enabled after the write/delete command sequence to the FF bank is completed (see Section 23.4 "Startting the Automatic Algorithm of the Flash Memory"). If this bit is set to "0", the execution of the write/delete command sequence to the FF bank does not generate a write or a delete signal. • Note: • Set this bit to "0" if neither a write nor a delete operation will be used. • bit4 RDY: Write/delete operation enable bit bit3 bit1 Reserved: Reserved bit bit2 bit0 LPM1, LPM0: Low power consumption mode setting bits • • When this bit is "0", writing to or deletion from the flash memory is disabled. When this bit is "0", read, reset and suspend commands, such as during temporary stop of sector deletion, can be accepted. This bit is set to "1" when a write or delete operation has been completed. • Be sure to set this bit to "0". • These bits allow power consumption of the flash memory to be controlled from the CPU. The values that can be specified in these bits vary depending on the internal operating frequency. The lower the internal operating frequency, the lower the power consumption of the flash memory. • • Note: The operation completion flag bit (RDYINT) and the write/delete status bit (RDY) do not change at the same time. Create a program so that the completion of writing or deletion is determined using the RDYINT or the RDY bit. 431 CHAPTER 23 1M-BIT FLASH MEMORY Automatic algorithm completion timing RDYINT bit RDY bit One machine cycle 432 23.4 Starting the Automatic Algorithm of the Flash Memory 23.4 Starting the Automatic Algorithm of the Flash Memory Four types of commands are supported to start the automatic algorithm of the flash memory: read/reset, write, chip deletion, and sector deletion. Temporary stop and restart can be controlled for sector deletion. ■ Command Sequence Table Table 23.4-1 "Command Sequence Table" lists the commands used to write data to and delete data from the flash memory. Although all the data items to be written to the command register have a length of bytes, use word access to write data. The data in the upper bytes written during word access will be ignored. Table 23.4-1 Command Sequence Table Command sequence Bus write access 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle Address Data Address Data Address Data Address Data Address Data Address Data Read/ reset (*1) 1 FxXXXXH XXF0H - - - - - - - - - - Read/ reset (*1) 4 FxAAAAH XXAAH Fx5554H XX55H FxAAAAH XXF0H RA RD - - - - Write program 4 FxAAAAH XXAAH Fx5554H XX55H FxAAAAH XXA0H PA(even) PD (word) - - - - Chip deletion 6 FxAAAAH XXAAH Fx5554H XX55H FxAAAAH XX80H FxAAAAH XXAAH Fx5554H XX55H FxAAAAH XX10H Sector deletion 6 FxAAAAH XXAAH Fx5554H XX55H FxAAAAH XX80H FxAAAAH XXAAH Fx5554H XX55H SA(even) XX30H Sector deletion temporary stop Enter the data (XXB0H) at address FXXXXXH to temporarily stop sector deletion. Sector deletion restart Enter the data (XX30H) at address FXXXXXH to resume sector deletion after temporarily stop. *1: These two types of read/reset commands can reset the flash memory to read mode. Notes: • Address Fx in the table means FF and FE. Use the address for the bank to be accessed during address-related operations. • The address in the table is a value in the CPU memory map. "X" stands for an arbitrary value. • RA: Read address • PA: Write address. An even-numbered address can be specified. • SA: Sector address. See Section 23.2 "Registers and Sector Configuration of the Flash Memory". An even-numbered address can be specified. • RD: Read data • PD: Write data. Word data can be specified. 433 CHAPTER 23 1M-BIT FLASH MEMORY 23.5 Detailed Description of Flash Memory Writing and Deletion This section describes the procedures for issuing commands that start the automatic algorithm to perform read/reset, write, chip deletion, sector deletion, temporary stop of sector deletion, or restart of sector deletion for the flash memory. ■ Detailed Description of Flash Memory Writing and Deletion The automatic algorithm can start read/reset, write, chip deletion, sector deletion, sector deletion temporary stop, or sector deletion restart operations by writing a command sequence (see Section 23.4 "Starting the Automatic Algorithm of the Flash Memory") from the CPU to the flash memory. Writing from the CPU to the flash memory must be performed continuously. When writing ends normally, the status returns to the read or reset status. The subsequent sections describe the details of the deletion restart operation in the following order: 434 • Placing the flash memory in read/reset status • Writing data • Deleting all data items (all chip deletion) • Deleting a data item (sector deletion) • Temporarily stopping sector deletion • Restarting sector deletion 23.5 Detailed Description of Flash Memory Writing and Deletion 23.5.1 Placing the Flash Memory in Read/Reset Status This section describes the procedure for executing the read/reset command to place the flash memory in read/reset status. ■ Placing Flash Memory in Read/Reset Status To place the flash memory in read/reset status, continuously send the read/reset command listed in the command sequence table (Table 23.4-1 "Command Sequence Table") from the CPU to the flash memory. There are two command sequences for the read/reset command, the results of which are the same. Read/reset status is the initial status of the flash memory. The flash memory is always in read/ reset status immediately after power is turned on or a command ends normally. In read/reset status, the system waits for input of a new command. In read/reset status, perform read access to the flash memory to read flash memory data. Like the mask ROM, flash memory does support program access from the CPU. No read/reset command is required to perform read access to the flash memory. If a command does not end normally, use the read/reset command to initialize the automatic algorithm. 435 CHAPTER 23 1M-BIT FLASH MEMORY 23.5.2 Writing Data to the Flash Memory This section describes the procedure for executing the write command to write data to the flash memory. Figure 23.5-1 "Example of the Procedure for Flash Memory Writing" shows an example of the procedure for flash memory writing. ■ Writing Data to the Flash Memory To start the automatic algorithm for writing data to the flash memory, continuously send the write command listed in the command sequence table (Table 23.4-1 "Command Sequence Table"), from the CPU to the flash memory. When data writing to the target address ends after the fourth cycle, the automatic algorithm is started to start automatic writing. ■ Addressing Only an even-numbered address can be specified as the write address in the write data cycle. If an odd-numbered address is specified, data cannot be written correctly. Use word access to write to an even-numbered address in word units. Writing is enabled in any order of addresses and across sector boundaries. However, only one word of data is written each time the write command is executed. ■ Notes on Writing Data The data of a bit cannot be changed from "0" to "1" by write operations. When there is an attempt to overwrite "0" by "1", the data polling algorithm or the toggle operation does not end, the flash memory component will be assumed to be faulty. IN this case, it will only appear as if "1" had been written, but "0" will be returned when the data is read in read/reset status. To change a bit from "0" to "1", perform a delete operation. All other commands are ignored while automatic writing is in progress. Data at a write address cannot be assured if a hardware reset occurs during writing. 436 23.5 Detailed Description of Flash Memory Writing and Deletion Figure 23.5-1 Example of the Procedure for Flash Memory Writing Start of writing FMCS: WE (bit5) Flash memory writing enabled Write command sequence FXAAAAH XXAAH FX5554H XX55H FXAAAAH XXA0H Write address Write data Next address Write/delete operation completion flag bit 0 "0" output is long. RDYINT 1 NO Write error Last address YES FMCS: WE (bit5) Flash memory writing disabled Start of writing 437 CHAPTER 23 1M-BIT FLASH MEMORY 23.5.3 Deleting All Data Items from the Flash Memory (Chip Deletion) This section describes the procedure for executing the chip deletion command to delete all data items from the flash memory. ■ Deleting All Data Items from the Flash Memory (Chip Deletion) To delete all data items from the flash memory, continuously send the chip deletion command listed in the command sequence table (Table 23.4-1 "Command Sequence Table") from the CPU to the flash memory. The chip deletion command starts the chip deletion operation when writing completes after the sixth cycle. Writing to the flash memory before chip deletion is not required. During the processing for the automatic deletion function, the flash memory performs verification by writing "0" before deleting all bits of the data. 438 23.5 Detailed Description of Flash Memory Writing and Deletion 23.5.4 Deleting a Data Item from the Flash Memory (Sector Deletion) This section describes the procedure for executing the sector deletion command to delete a data item from the flash memory (sector deletion). Data in any sector can be deleted. More than one sector can be specified for deletion. Figure 23.5-2 "Example of the Sector Deletion Procedure for the Flash Memory" shows an example of the procedure for flash memory sector deletion. ■ Deleting a Data Item from the Flash Memory (Sector Deletion) To delete data in any sector of the flash memory, continuously send the sector deletion command listed in the command sequence table (Table 23.4-1 "Command Sequence Table") from the CPU to the flash memory. ■ Specifying a Sector The sector deletion command starts a sector deletion wait of 50 μs by writing in the sixth cycle the sector deletion code (30H) to any even-numbered address in the target sector that can be accessed. To delete more than one sector, write the deletion code (30H) to the addresses of additional sectors to be deleted. ■ Notes on Specifying More Than One Sector Deletion starts upon completion of the 50 μs sector deletion wait period since the last sector deletion code was written. To delete more than one sector at the same time, input the deletion sector address and the deletion code (in the sixth cycle of the command sequence) within 50 μs. The address and the code are accepted only if they are input within 50 μs. 439 CHAPTER 23 1M-BIT FLASH MEMORY Figure 23.5-2 Example of the Sector Deletion Procedure for the Flash Memory Start of deletion FMCS: WE (bit5) Flash memory deletion enabled Delete command sequence FXAAAAH XXAAH FX5554H XX55H FXAAAAH XX80H FXAAAAH XXAAH FX5554H XX55H Deletion sector code input (30H) NO Write/delete operation completion flag bit 0 RDYINT "0" output takes too long. Deletion error NO Last address YES FMCS: WE (bit5) Flash memory deletion disabled End of deletion 440 Next sector 1 23.5 Detailed Description of Flash Memory Writing and Deletion 23.5.5 Temporarily Stopping Deletion of Sectors from the Flash Memory This section describes the procedure for executing the sector deletion temporary stop command to temporarily stop the deletion of sectors from the flash memory. Data can be read from sectors that are not being deleted. ■ Temporarily Stopping Sector Deletion To temporarily stop the deletion of sectors from the flash memory, continuously send the sector deletion temporary stop command listed in the command sequence table (Table 23.4-1 "Command Sequence Table") from the CPU to the flash memory. The sector deletion temporary stop command temporarily stops the deletion of sectors and the reading of data from sectors that are not being deleted. In sector deletion temporary stop status, reading is enabled and writing is disabled. The sector deletion temporary stop command is valid only during sector deletion (including the deletion wait time) and is ignored during chip deletion or writing. To execute the sector deletion temporary stop command, write the deletion temporary stop code (B0H). Specify any address in the flash memory. During deletion temporary stop, the deletion temporary stop command is ignored if it is executed. If the sector deletion temporary stop command is input during the sector deletion wait period, the sector deletion wait ends and deletion is suspended, causing the system to enter deletion stop status. If the deletion temporary stop command is input during sector deletion after the sector deletion wait period, the system enters deletion temporary stop status after waiting for a maximum of 15 μs. 441 CHAPTER 23 1M-BIT FLASH MEMORY 23.5.6 Resuming Flash Memory Sector Deletion This section describes the procedure for issuing the sector deletion restart command to resume a flash memory sector deletion that has been temporarily stopped. ■ Resuming the Flash Memory Sector Deletion To resume a sector deletion that has been temporarily stopped, continuously send the sector deletion restart command listed in the command sequence table (Table 23.4-1 "Command Sequence Table") from the CPU to the flash memory. The sector deletion restart command is used to restart sector deletion that has been temporarily stopped by execution of the sector deletion temporary stop command. To execute the sector deletion restart command, write the sector deletion restart code (30H). Specify any address in the flash memory. During sector deletion, the sector deletion restart command is ignored if it is executed. 442 CHAPTER 24 EXAMPLE OF MB90MF408/MF408A SERIAL PROGRAMMING CONNECTION This chapter provides examples of connection for serial programming using the AF220 flash microcomputer programmer manufactured by YDC Corporation. 24.1 "Standard Configuration for Serial Programming Connection to MB90MF408/MF408A" 24.2 "Example of Connection for Serial Programming (Power Supplied by User)" 24.3 "Example of Connection for Serial Programming (Power Supplied from Programmer)" 24.4 "Example of Minimum Connection to Flash Microcomputer Programmer (Power Supplied by User)" 24.5 "Example of Minimum Connection to Flash Microcomputer Programmer (Power Supplied from Programmer)" 443 CHAPTER 24 EXAMPLE OF MB90MF408/MF408A SERIAL PROGRAMMING CONNECTION 24.1 Standard Configuration for Serial Programming Connection to MB90MF408/MF408A MB90MF408/MF408A supports serial on-board writing (Fujitsu standard) to flash ROM. This describes the specifications for serial on-board writing. ■ Standard Configuration for Serial Programming Connection to MB90MF408/MF408A The AF220 flash microcomputer programmer, manufactured by YDC, is used for Fujitsu standard serial on-board writing. Host interface cable (AZ201) RS232C AF220 flash microcomputer programmer + memory card General-purpose common cable (AZ210) Clock synchronous serial MB90MF408 user system Operable in stand-alone mode Note: Contact YDC for information about the functions and operations of the AF220 flash microcomputer programmer and information about the general-purpose common connection cable (AZ210) and connectors. Table 24.1-1 Pins Used for Fujitsu Standard Serial on-board Programming Pin Function Description MD2,MD1, MD0 Mode pin Switches to programming mode from the flash microcomputer programmer. X0, X1 Oscillator pin Since the internal operating clock of the CPU is set to the same clock cycle as the PLL clock, the oscillation clock frequency is used as the internal operation clock. An oscillation clock from 1 MHz to 16 MHz is therefore used for serial on-board programming. P80, P81 Programming start pin - RST Reset pin - SI1 Serial data input pin The UART is used in clock synchronous mode. SO1 Serial data output pin SC0 Serial clock input pin C C terminal 444 Capacitor terminal for stabilizing the power supply. Connect an external ceramic capacitor of about 0.1 μF. 24.1 Standard Configuration for Serial Programming Connection to MB90MF408/MF408A Table 24.1-1 Pins Used for Fujitsu Standard Serial on-board Programming (Continued) Pin Function Description VCC Power supply pin The flash microcomputer programmer does not need to be connected to supply the programming voltage (5 V 10%) from the user system. When you connect this pin, make sure that no short-circuit occurs between it and the userside power supply. VSS Ground pin Also use this pin as the ground pin for the flash microcomputer programmer. When the P80, SI0, SO0, and SC0 pins are also used by the user system, the control circuit shown in Figure 24.1-1 "Control Circuit" is required. (The TCIS signal of the flash microcomputer programmer can separate the user circuit during serial writing. See the connection example shown later.) Figure 24.1-1 Control Circuit MB90MF408/MF408A AF220 write control pin write control pin 10 K AF220 TICS pin User Circuit Refer to the following four serial writing examples in Sections 24.2 to 24.5. • Example of serial programming connection • • Example of serial programming connection • • When power is supplied from the programmer Example of minimum connection to flash microcomputer programmer • • When power supplied by user When power supplied from user Example of minimum connection to flash microcomputer programmer • When power is supplied from the programmer Table 24.1-2 System Configuration of AF220 Flash Microcomputer Programmer (Manufactured by YDC) Model Function AF220 Advanced flash microcomputer programmer AF200 ACP AC adapter (center +) (optional) AZ201 Host interface cable (RS232C cable for PCAT) AZ210 Standard target probe (Type A) Length: 1 m FF001 Fujitsu F2MC-16LX flash microcomputer control module FF001 P2 2 MB PC card (optional) FF001 P4 4 MB PC card (optional) For additional information, contact: YDC Corporation Telephone number: (81)-42-333-6224 445 CHAPTER 24 EXAMPLE OF MB90MF408/MF408A SERIAL PROGRAMMING CONNECTION 24.2 Example of Connection for Serial Programming (Power Supplied by User) Figure 24.2-1 "Example of Connection for Serial Programming by MB90MF408/MF408A (Power Supplied by User)" shows an example of connection when microcomputer power is supplied by the user. The mode pins are set to single-chip mode (MD0=1, MD1=1, and MD2=0). ■ Example of Connection for Serial Programming (When Power Supplied by User) Figure 24.2-1 Example of Connection for Serial Programming by MB90MF408/MF408A (Power Supplied by User) AF220 flash microcomputer programmer User system Connector MB90MF408/MF408A DX10-28S TAUX3 (19) MD2 10 K 10 K MD1 10 K TMODE MD0 X0 (12) 1 MHz to16 MHz X1 TAUX (23) P80 10 K TICS (10) User circuit 10 K TRES RST (5) 10 K P81 C User circuit 0.1 F TTXD TRXD (13) (27) SI0 SO0 TCK (6) SC0 TVcc (2) GND (1, 7, 8, 14, 15, 21, 22, 28) Vcc User power supply Vss Pin 14 Pins 3, 4, 9, 11, 16, 17, 18, 20, 24, 25, and 26 are open. Pin 1 DX10-28S Pin 28 Pin 15 DX10-28, right-angle type Connector (Hirose Electronics) pin layout 446 24.2 Example of Connection for Serial Programming (Power Supplied by User) • When the user system also uses the P80, SI0, SO0, and SC0 pins, the following control circuit is necessary. During serial programming, disconnect the user circuit using the TCIS signal of the flash microcomputer programmer. AF220 write control pin MB90MF408/MF408A write control pin 10 K AF220 TICS pin User circuit • Before connecting to AF220, turn off the user power. 447 CHAPTER 24 EXAMPLE OF MB90MF408/MF408A SERIAL PROGRAMMING CONNECTION 24.3 Example of Connection for Serial Programming (When Power Supplied from Programmer) Figure 24.3-1 "Example of Connection for Serial Programming by MB90MF408/MF408A (Power Supplied by Programmer)" shows an example of connection when microcomputer power is supplied by the programmer. The mode pins are set to single-chip mode (MD0=1, MD1=1, and MD2=0). ■ Example of Connection for Serial Programming (When Power Supplied from Programmer) Figure 24.3-1 Example of Connection for Serial Programming by MB90MF408/MF408A (Power Supplied by Programmer) AF220 flash microcomputer programmer User system Connector MB90MF408/MF408A DX10-28S TAUX3 (19) MD2 10 K 10 K MD1 10 K TMODE MD0 X0 (12) 1 MHz to 16 MHz X1 TAUX (23) P80 10 K TICS (10) User circuit 10 K TRES RST (5) 10 K P81 C User circuit 0.1 F TTXD TRXD (13) (27) SI0 SO0 TCK (6) (2) (3) (16) SC0 TVcc Vcc TVPP1 GND (1, 7, 8, 14, 15, 21, 22, 28) Vcc User power supply Vss Pin 14 Pins 4, 9, 11, 17, 18, 20, 24, 25, and 26 are open. Pin 1 DX10-28S Pin 28 Pin 15 DX10-28, right-angle type Connector (made by Hirose Electronics) pin layout 448 24.3 Example of Connection for Serial Programming (When Power Supplied from Programmer) • When the user system also uses the P80, SI0, SO0, and SC0 pins, the following control circuit is necessary. During serial programming, disconnect the user circuit using the TCIS signal of the flash microcomputer programmer. MB90MF408/MF408A write control pin AF220 write control pin 10 KΩ AF220 TICS pin User circuit • Before connecting the AF220, turn off the power supplied by the user. • When supplying power from the AF220, do not create a short circuit to the power supplied by the user. 449 CHAPTER 24 EXAMPLE OF MB90MF408/MF408A SERIAL PROGRAMMING CONNECTION 24.4 Example of Minimum Connection with Flash Microcomputer Programmer (When Power Supplied from User) Figure 24.4-1 "Example of Minimum Connection with Flash Microcomputer Programmer (When Power Supplied by User)" shows an example of minimum connection with the flash microcomputer programmer. ■ Example of Minimum Connection with Flash Microcomputer Programmer (When Power Supplied by User) If the pins are set as shown in Figure 24.4-1 "Example of Minimum Connection with Flash Microcomputer Programmer (When Power Supplied by User)" for writing data to the flash memory, then MD2, MD1, MD0, and P80 do not need to be connected to the flash microcomputer programmer. 450 24.4 Example of Minimum Connection with Flash Microcomputer Programmer (When Power Supplied from User) Figure 24.4-1 Example of Minimum Connection with Flash Microcomputer Programmer (When Power Supplied by User) AF220 flash microcomputer programmer User system Set MD2 to "1" during serial rewriting MB90MF408/MF408A 10 K MD2 Set MD1 to "1" during serial rewriting 10 K 10 K MD1 10 K 10 K MD0 Set MD0 to "0" during serial rewriting 10 K X0 1 MHz to 16 MHz X1 P80 10 K Set P80 to "0" during serial rewriting 10 K User circuit Set P81 to "1" during serial rewriting P81 User circuit C 0.1 F Connector DX10-28S 10 K TRES (5) RST TTXD (13) TRXD (27) SO0 TCK (6) SC0 TVcc (16) Vcc GND (1, 7, 8, 14, 15, 21, 22, 28) SI0 User power supply Vss Pin 14 Pins 3, 4, 9, 10, 11, 12, 16, 17, 18, 19, 20, 23, 24, 25, and 26 are open. DX10-28S: right-angle type Pin 1 DX10-28S Pin 28 Pin 15 Connector (made by Hirose Electronics) pin layout • Turn off the user circuit power before connecting to the AF220. 451 CHAPTER 24 EXAMPLE OF MB90MF408/MF408A SERIAL PROGRAMMING CONNECTION 24.5 Example of Minimum Connection with Flash Microcomputer Programmer (When Power Supplied from Programmer) Figure 24.5-1 "Example of Minimum Connection with Flash Microcomputer Programmer (When Power Supplied from programmer)" shows an example of minimum connection with the flash microcomputer programmer. ■ Example of Minimum Connection with Flash Microcomputer Programmer (When Power Supplied from programmer) If data is written to the flash memory with the pin settings as shown in Figure 24.5-1 "Example of Minimum Connection with Flash Microcomputer Programmer (When Power Supplied from programmer)", MD2, MD1, MD0, and P80 do not need to be connected to the flash microcomputer programmer. 452 24.5 Example of Minimum Connection with Flash Microcomputer Programmer (When Power Supplied from Programmer) Figure 24.5-1 Example of Minimum Connection with Flash Microcomputer Programmer (When Power Supplied from programmer) AF220 flash microcomputer programmer User system MB90MF408/MF408A Set MD2 to "1" during serial rewriting 10 K MD2 Set MD1 to "1" during serial rewriting 10 K 10 K MD1 10 K 10 K MD0 Set MD0 to "0" during serial rewriting 10 K X0 1 MHz to 16 MHz X1 10 K Set P80 to "0" during serial rewriting P80 10 K User circuit P81 Set P81 to "1" during serial rewriting User circuit C 0.1 F Connector DX10-28S 10 K TRES (5) TTXD (13) SI0 TRXD (27) SO0 TCK TTXD TRXD TVcc (6) (2) (3) (16) SC0 GND (1, 7, 8, 14, 15, 21, 22, 28) RST Vcc User power supply Vss Pin 14 Pins 4, 9, 10, 11, 12, 16, 17, 18, 19, 20, 23, 24, 25, and 26 are open. DX10-28S, right-angle type Pin 1 DX10-28S Pin 28 Pin 15 Connector (made by Hirose Electronics) pin layout • Before connecting the AF220, turn off the power supplied by the user. • When power is supplied from the AF220, do not create a short circuit to the power supplied by the user. 453 CHAPTER 24 EXAMPLE OF MB90MF408/MF408A SERIAL PROGRAMMING CONNECTION 454 APPENDIX This appendix includes I/O maps, instruction lists, and other information. APPENDIX A "I/O Map" APPENDIX B "Instructions" APPENDIX C "Index of Registers" APPENDIX D "Index of Pin Functions" 455 APPENDIX A I/O Map APPENDIX A I/O Map Table A-1 lists the addresses assigned to the registers for peripheral functions in the MB90M405 series. ■ I/O Map Table A-1 I/O Map Address Abbreviation Register 000000H to 000007H Read/write Resource name Initial value Prohibited area 000008H PDR8 Port 8 data register R/W Port 8 XXXXXXXXB 000009H PDR9 Port 9 data register R/W Port 9 XXXXXXXXB 00000AH PDRA Port A data register R/W Port A XXXXXXXXB 00000BH PDRB Port B data register R/W Port B XXXXXXXXB 00000CH to 000017H Prohibited area 000018H DDR8 Port 8 direction register R/W Port 8 00000000B 000019H DDR9 Port 9 direction register R/W Port 9 XXXXXX00B 00001AH DDRA Port A direction register R/W Port A 00000000B 00001BH DDRB Port B direction register R/W Port B 00000000B 00001CH to 00001DH Prohibited area 00001EH ADER0 Analog input enable register 0 R/W Port A, A/D 11111111B 00001FH ADER1 Analog input enable register 1 R/W Port B, A/D 11111111B 000020H SMR0 Mode register ch0 R/W 00000X00B 000021H SCR0 Control register ch0 R/W 00000100B SIDR0 Input data register ch0 R SODR0 Output data register ch0 W 000022H 000023H 456 SSR0 Status register ch0 R/W UART ch0 XXXXXXXXB 00001000B APPENDIX A I/O Map Table A-1 I/O Map (Continued) Address Abbreviation 000024H SMR1 Mode register ch1 R/W 00000X00B 000025H SCR1 Control register ch1 R/W 00000100B SIDR1 Input data register ch1 R SODR1 Output data register ch1 W 000026H 000027H SSR1 000028H Register Read/write Resource name Initial value UART ch1 XXXXXXXXB Status register ch1 R/W CDCR0 Communication prescaler control register ch0 R/W Communication prescaler 0 0XXX0000B 000029H CDCR1 Communication prescaler control register ch1 R/W Communication prescaler 1 0XXX0000B 00002AH IBSR I2C status register R 00000000B 00002BH IBCR I2C control register R/W 00000000B 00002CH ICCR I2C clock control register R/W 00002DH IADR I2C address register R/W XXXXXXXXB 00002EH IDAR I2C data register R/W XXXXXXXXB 00002FH ISEL I2C port selection register R/W XXXXXXX0B 000030H ENIR DTP/interrupt enable register R/W 000031H EIRR DTP/interrupt cause register R/W 000032H ELVR Request level setting register R/W 000033H 00001000B I2C interface XX0XXXXXB XXXX0000B DTP/external interrupt XXXXXXXXB 00000000B Prohibited area 000034H ADCS0 A/D control status register 0 (lower) R/W 000035H ADCS1 A/D control status register 1 (upper) R/W 000036H ADCR0 A/D data register 0 (lower) R/W XXXXXXXXB 000037H ADCR1 A/D data register 1 (upper) R/W 00000XXXB 000038H 000039H 000041H A/D converter 00000000B Prohibited area ADMR 00003AH to 00003FH 000040H 00XXXXXXB A/D conversion channel select register R/W A/D converter 00000000B 16-bit freerunning timer 00000000B Prohibited area TCCS Timer counter control status register R/W Prohibited area 457 APPENDIX A I/O Map Table A-1 I/O Map (Continued) Address 000042H Abbreviation TCDT Register Timer counter data register Read/write Resource name Initial value R/W 16-bit freerunning timer 00000000B 000043H 000044H IPC0 Input capture data register ch0 XXXXXXXXB R 000045H 000046H XXXXXXXXB IPC1 Input capture data register ch1 R Input capture 000047H 000048H ICSO1 Input capture control status register R/W OCCP0 Output compare register Output compare OCS0 Output compare control status register R/W Reserved area 00004EH to 00004FH Prohibited area TMCSR0 Timer control status register ch0 R/W 000051H 000052H 000053H 000054H TMR0/ TMRLR0 16-bit timer register ch0 (R) 16-bit reload register ch0 (W) TMCSR1 Timer control status register ch1 TMR0: R TMRLR0: W R/W 000055H 000056H 000057H 000058H TMR1/ TMRLR1 16-bit timer register ch1 (R) 16-bit reload register ch1 (W) TMCSR2 Timer control status register ch2 TMR1: R TMRLR1: W R/W 000059H 00005AH 00005BH 00005CH to 00005FH 458 XXXXXXXXB R/W 00004DH 000050H 00000000B Prohibited area 00004BH 00004CH XXXXXXXXB XXXXXXXXB 000049H 00004AH 00000000B TMR2/ TMRLR2 16-bit timer register ch2 (R) 16-bit reload register ch2 (W) TMR2: R TMRLR2: W Prohibited area XXXXXXXXB XX00XXX0B 00000000B 16-bit reload timer XXXX0000B ch0 XXXXXXXXB XXXXXXXXB 00000000B 16-bit reload timer XXXX0000B ch1 XXXXXXXXB XXXXXXXXB 00000000B 16-bit reload timer XXXX0000B ch2 XXXXXXXXB XXXXXXXXB APPENDIX A I/O Map Table A-1 I/O Map (Continued) Address 000060H Abbreviation Register Read/write SMCS2 Serial mode control status register ch2 R/W Serial shift data register ch2 R/W 000061H 000062H SDR2 000063H 000064H Initial value XXXX0000B Serial I/O ch2 00000010B XXXXXXXXB Prohibited area SMCS3 000065H 000066H Resource name SDR3 Serial mode control status register ch3 R/W Serial shift data register ch3 R/W 000067H XXXX0000B Serial I/O ch3 00000010B XXXXXXXXB Prohibited area 000068H FLC1 Display control register 1 W 000069H FLC2 Display control register 2 W 00006AH FLDG Digit setting register W 00000000B 00006BH FLDC Digit count register W 00000000B FL control circuit 00006CH 00006DH XXXXXX00B 00000000B Prohibited area FLST Status register/establishment register 00006EH R FL control circuit W XX1XXX00B 00XXXXXXB Prohibited area 00006FH ROMM ROM mirroring function selection register W 000070H to 000077H SEGD0 to 7 Segment dimmer setting register W 000078H FLPD0 000079H FLPD1 00007AH FLPD2 Port register ROM mirroring function selection module XXXXXXX1B XXXXXXXXB FL control circuit FIP36 to 43 W FIP44 to 51 W 00000000B FIP52 to 59 W 00000000B 00007BH to 00009DH 00000000B Prohibited area Program address detection control status register R/W Delayed interrupt cause generation/release register R/W Delayed interrupt XXXXXXX0B LPMCR Low power consumption mode control register R/W CKSCR Clock selection register R/W Low power consumption control circuit 00009EH PACSR 00009FH DIRR 0000A0H 0000A1H Address match detection circuit 00000000B 00011000B 11111100B 459 APPENDIX A I/O Map Table A-1 I/O Map (Continued) Address Abbreviation 0000A2H to 0000A7H Register Read/write Resource name Initial value Prohibited area 0000A8H WDTC Watchdog timer control register R/W Watchdog timer XXXXX111B 0000A9H TBTC Timebase timer control register R/W Timebase timer 1XX00100B 0000AAH to 0000ADH Prohibited area 0000AEH FMCS Flash memory control status register R/W 1M-bit flash memory 00000000B 0000AFH TMCS Watch clock output control register R/W Watch clock division XXXXX000B 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 460 Interrupt control register 00 (for writing) W, R/W 00000111B Interrupt control register 00 (for reading) R, R/W XX000111B Interrupt control register 01 (for writing) W, R/W 00000111B Interrupt control register 01 (for reading) R, R/W XX000111B Interrupt control register 02 (for writing) W, R/W 00000111B Interrupt control register 02 (for reading) R, R/W XX000111B Interrupt control register 03 (for writing) W, R/W 00000111B ICR00 ICR01 ICR02 Interrupt ICR03 Interrupt control register 03 (for reading) R, R/W XX000111B Interrupt control register 04 (for writing) W, R/W 00000111B Interrupt control register 04 (for reading) R, R/W XX000111B Interrupt control register 05 (for writing) W, R/W 00000111B Interrupt control register 05 (for reading) R, R/W XX000111B Interrupt control register 06 (for writing) W, R/W 00000111B Interrupt control register 06 (for reading) R, R/W XX000111B ICR04 ICR05 ICR06 APPENDIX A I/O Map Table A-1 I/O Map (Continued) Address 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H to 0000FFH Abbreviation Register Read/write Resource name Initial value Interrupt control register 07 (for writing) W, R/W 00000111B Interrupt control register 07 (for reading) R, R/W XX000111B Interrupt control register 08 (for writing) W, R/W 00000111B Interrupt control register 08 (for reading) R, R/W XX000111B Interrupt control register 09 (for writing) W, R/W 00000111B Interrupt control register 09 (for reading) R, R/W XX000111B Interrupt control register 10 (for writing) W, R/W 00000111B Interrupt control register 10 (for reading) R, R/W XX000111B Interrupt control register 11 (for writing) W, R/W 00000111B ICR07 ICR08 ICR09 ICR10 ICR11 Interrupt Interrupt control register 11 (for reading) R, R/W XX000111B Interrupt control register 12 (for writing) W, R/W 00000111B Interrupt control register 12 (for reading) R, R/W XX000111B Interrupt control register 13 (for writing) W, R/W 00000111B Interrupt control register 13 (for reading) R, R/W XX000111B Interrupt control register 14 (for writing) W, R/W 00000111B Interrupt control register 14 (for reading) R, R/W XX000111B Interrupt control register 15 (for writing) W, R/W 00000111B Interrupt control register 15 (for reading) R, R/W XX000111B ICR12 ICR13 ICR14 ICR15 Unused area 461 APPENDIX A I/O Map Table A-1 I/O Map (Continued) Address Abbreviation Register Read/write 000100H to #H 001100H to 0011FFH Resource name Initial value FL control circuit XXXXXXXXB RAM area FL000 to 255 Display data RAM 001200H to 001FEFH R/W Reserved area Program address detection register (lower) R/W XXXXXXXXB Program address detection register (middle) R/W XXXXXXXXB 001FF2H Program address detection register (upper) R/W 001FF3H Program address detection register (lower) R/W XXXXXXXXB Program address detection register (middle) R/W XXXXXXXXB Program address detection register (upper) R/W XXXXXXXXB 001FF0H 001FF1H 001FF4H 001FF5H PADR0 PADR1 001FF6H to 001FFFH Address match detection function Unused area ❍ Meaning of abbreviations used for reading and writing R/W: Read/write enabled R: Read only W: Write only ❍ Explanation of initial values 0: The initial value is 0. 1: The initial value is 1. X: The initial value is undefined. 462 XXXXXXXXB APPENDIX B Instructions APPENDIX B Instructions APPENDIX B describes the instructions used by the F2MC-16LX. B.1 Instruction Types B.2 Addressing B.3 Direct Addressing B.4 Indirect Addressing B.5 Execution Cycle Count B.6 Effective address field B.7 How to Read the Instruction List B.8 F2MC-16LX Instruction List B.9 Instruction Map Code: CM44-00202-1E 463 APPENDIX B Instructions B.1 Instruction Types The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself. ■ Instruction Types The F2MC-16LX supports the following 351 types of instructions: 464 • 41 transfer instructions (byte) • 38 transfer instructions (word or long word) • 42 addition/subtraction instructions (byte, word, or long word) • 12 increment/decrement instructions (byte, word, or long word) • 11 comparison instructions (byte, word, or long word) • 11 unsigned multiplication/division instructions (word or long word) • 11 signed multiplication/division instructions (word or long word) • 39 logic instructions (byte or word) • 6 logic instructions (long word) • 6 sign inversion instructions (byte or word) • 1 normalization instruction (long word) • 18 shift instructions (byte, word, or long word) • 50 branch instructions • 6 accumulator operation instructions (byte or word) • 28 other control instructions (byte, word, or long word) • 21 bit operation instructions • 10 string instructions APPENDIX B Instructions B.2 Addressing With the F2MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used. Some instructions permit the user to select several types of addressing. ■ Addressing The F2MC-16LX supports the following 23 types of addressing: • Immediate (#imm) • Register direct • Direct branch address (addr16) • Physical direct branch address (addr24) • I/O direct (io) • Abbreviated direct address (dir) • Direct address (addr16) • I/O direct bit address (io:bp) • Abbreviated direct bit address (dir:bp) • Direct bit address (addr16:bp) • Vector address (#vct) • Register indirect (@RWj j = 0 to 3) • Register indirect with post increment (@RWj+ j = 0 to 3) • Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) • Long register indirect with displacement (@RLi + disp8 i = 0 to 3) • Program counter indirect with displacement (@PC + disp16) • Register indirect with base index (@RW0 + RW7, @RW1 + RW7) • Program counter relative branch address (rel) • Register list (rlst) • Accumulator indirect (@A) • Accumulator indirect branch address (@A) • Indirectly-specified branch address (@ear) • Indirectly-specified branch address (@eam) 465 APPENDIX B Instructions ■ Effective Address Field Table B.2-1 lists the address formats specified by the effective address field. Table B.2-1 Effective Address Field Code Representation 00 R0 RW0 RL0 01 R1 RW1 (RL0) 02 R2 RW2 RL1 03 R3 RW3 (RL1) 04 R4 RW4 RL2 05 R5 RW5 (RL2) 06 R6 RW6 RL3 07 R7 RW7 (RL3) 08 @RW0 09 @RW1 Address format Default bank Register direct: Individual parts correspond to the byte, word, and long word types in order from the left. None DTB DTB Register indirect 0A @RW2 ADB 0B @RW3 SPB 0C @RW0+ DTB 0D @RW1+ DTB Register indirect with post increment 0E @RW2+ ADB 0F @RW3+ SPB 10 @RW0+disp8 DTB 11 @RW1+disp8 DTB Register indirect with 8-bit displacement 12 @RW2+disp8 ADB 13 @RW3+disp8 SPB 14 @RW4+disp8 DTB 15 @RW5+disp8 DTB Register indirect with 8-bit displacement 16 @RW6+disp8 ADB 17 @RW7+disp8 SPB 18 @RW0+disp16 DTB 19 @RW1+disp16 DTB Register indirect with 16-bit displacement 466 1A @RW2+disp16 ADB 1B @RW3+disp16 SPB 1C @RW0+RW7 Register indirect with index DTB 1D @RW1+RW7 Register indirect with index DTB 1E @PC+disp16 PC indirect with 16-bit displacement PCB 1F addr16 Direct address DTB APPENDIX B Instructions B.3 Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. ■ Direct Addressing ● Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of Immediate Addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.) Before execution A 2233 4455 After execution A 4455 1 2 1 2 (Some instructions transfer AL to AH.) ● Register direct addressing Specify a register explicitly as an operand. Table B.3-1 lists the registers that can be specified. Figure B.3-2 shows an example of register direct addressing. Table B.3-1 Direct Addressing Registers General-purpose register Special-purpose register Byte R0, R1, R2, R3, R4, R5, R6, R7 Word RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 Long word RL0, RL1, RL2, RL3 Accumulator A, AL Pointer SP * Bank PCB, DTB, USB, SSB, ADB Page DPR Control PS, CCR, RP, ILM *: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on the value of the S flag bit in the condition code register (CCR). For branch instructions, the program counter (PC) is not specified in an instruction operand but is specified implicitly. 467 APPENDIX B Instructions Figure B.3-2 Example of Register Direct Addressing MOV R0, A (This instruction transfers the eight low-order bits of A to the generalpurpose register R0.) Before execution A 0716 2534 Memory space R0 After execution A 0716 2564 ?? Memory space R0 34 ● Direct branch addressing (addr16) Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which indicates the branch destination in the logical address space. Direct branch addressing is used for an unconditional branch, subroutine call, or software interrupt instruction. Bit23 to bit16 of the address are specified by the program counter bank register (PCB). Figure B.3-3 Example of Direct Branch Addressing (addr16) JMP 3B20H (This instruction causes an unconditional branch by direct branch addressing in a bank.) Before execution After execution 468 PC 3 C 2 0 PC 3 B 2 0 PCB 4 F PCB 4 F Memory space 4F3B20H Next instruction 4F3C20H 62 4F3C21H 20 4F3C22H 3B JMP 3B20H APPENDIX B Instructions ● Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction. Figure B.3-4 Example of Direct Branch Addressing (addr24) JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit addressing.) Before execution After execution PC 3 C 2 0 PC 3 B 2 0 PCB 4 F PCB 3 3 Memory space 333B20H Next instruction 4F3C20H 63 4F3C21H 20 4F3C22H 3B 4F3C23H 33 JMPP 333B20H ● I/O direct addressing (io) Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB) and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an instruction using I/O direct addressing. Figure B.3-5 Example of I/O Direct Addressing (io) MOVW A, i : 0C0H (This instruction reads data by I/O direct addressing and stores it in A.) Before execution After execution A 0716 2534 Memory space 0000C0H EE 0000C1H FF A 2534 FFEE 469 APPENDIX B Instructions ● Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB). Figure B.3-6 Example of Abbreviated Direct Addressing (dir) MOV S : 20H, A (This instruction writes the contents of the eight low-order bits of A in abbreviated direct addressing mode.) Before execution A 4455 DPR 6 6 After execution A 4455 DPR 6 6 1212 DTB 7 7 Memory space 776620H 1212 DTB 7 7 ?? Memory space 776620H 12 ● Direct addressing (addr16) Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for this mode of addressing. Figure B.3-7 Example of Direct Addressing (addr16) MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.) Before execution After execution 470 A 2020 A AABB AABB 0123 DTB 5 5 DTB 5 5 Memory space 553B21H 01 553B20H 23 APPENDIX B Instructions ● I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp) SETB i : 0C1H : 0 (This instruction sets bits by I/O direct bit addressing.) Memory space Before execution 0000C1H 00 Memory space After execution 0000C1H 01 ● Abbreviated direct bit addressing (dir:bp) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp) SETB S : 10H : 0 (This instruction sets bits by abbreviated direct bit addressing.) Memory space Before execution DTB 5 5 DPR 6 6 556610H 00 Memory space After execution DTB 5 5 DPR 6 6 556610H 01 ● Direct bit addressing (addr16:bp) Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-10 Example of Direct Bit Addressing (addr16:bp) SETB 2222H : 0 (This instruction sets bits by direct bit addressing.) Memory space Before execution DTB 5 5 552222H 00 Memory space After execution DTB 5 5 552222H 01 471 APPENDIX B Instructions ● Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction. Figure B.3-11 Example of Vector Addressing (#vct) CALLV #15 (This instruction causes a branch to the address indicated by the interrupt vector specified in an operand.) Before execution PC 0 0 0 0 Memory space PCB F F After execution FFC000H EF FFFFE0H 00 FFFFE1H D0 CALLV #15 PC D 0 0 0 PCB F F Table B.3-2 CALLV Vector List Instruction Vector address L Vector address H CALLV #0 XXFFFEH XXFFFFH CALLV #1 XXFFFCH XXFFFDH CALLV #2 XXFFFAH XXFFFBH CALLV #3 XXFFF8H XXFFF9H CALLV #4 XXFFF6H XXFFF7H CALLV #5 XXFFF4H XXFFF5H CALLV #6 XXFFF2H XXFFF3H CALLV #7 XXFFF0H XXFFF1H CALLV #8 XXFFEEH XXFFEFH CALLV #9 XXFFECH XXFFEDH CALLV #10 XXFFEAH XXFFEBH CALLV #11 XXFFE8H XXFFE9H CALLV #12 XXFFE6H XXFFE7H CALLV #13 XXFFE4H XXFFE5H CALLV #14 XXFFE2H XXFFE3H CALLV #15 XXFFE0H XXFFE1H Note: A PCB register value is set in XX. Note: When the program counter bank register (PCB) is FFH, the vector area overlaps the vector area of INT #vct8 (#0 to #7). Use vector addressing carefully (see Table B.3-2). 472 APPENDIX B Instructions B.4 Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. ■ Indirect Addressing ● Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used. Figure B.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3) MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores it in A.) Before execution A 0716 2534 Memory space RW1 D 3 0 F After execution DTB 7 8 78D30FH EE 78D310H FF A 2534 FFEE RW1 D 3 0 F DTB 7 8 ● Register indirect addressing with post increment (@RWj+ j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. After operand operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word). Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used. If the post increment results in the address of the register that specifies the increment, the incremented value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to writing by an instruction and, therefore, the register that would be incremented becomes write data. 473 APPENDIX B Instructions Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3) MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post increment and stores it in A.) Before execution A 0716 2534 Memory space RW1 D 3 0 F After execution DTB 7 8 78D30FH EE 78D310H FF A 2534 FFEE RW1 D 3 1 1 DTB 7 8 ● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) Memory is accessed using the address obtained by adding an offset to the contents of general-purpose register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is used, or additional data bank register (ADB) when RW2 or RW6 is used. Figure B.4-3 Example of Register Indirect Addressing with Offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with an offset and stores it in A.) Before execution A 0716 2534 (+10H) RW1 D 3 0 F After execution A 2534 FFEE RW1 D 3 0 F 474 DTB 7 8 DTB 7 8 Memory space 78D31FH EE 78D320H FF APPENDIX B Instructions ● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3) Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value. Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3) MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with an offset and stores it in A.) Before execution A 0716 2534 (+25H) RL2 F 3 8 2 After execution 4B02 Memory space 824B27H EE 824B28H FF A 2534 FFEE RL2 F 3 8 2 4B02 ● Program counter indirect addressing with offset (@PC + disp16) Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one word long. Address bits 16 to 23 are specified by the program counter bank register (PCB). Note that the operand address of each of the following instructions is not deemed to be (next instruction address + disp16): • DBNZ eam, rel • DWBNZ eam, rel • CBNE eam, #imm8, rel • CWBNE eam, #imm16, rel • MOV eam, #imm8 • MOVW eam, #imm16 Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16) MOVW A, @PC+20H (This instruction reads data by program counter indirect addressing with an offset and stores it in A.) Before execution A 0716 2534 Memory space PCB C 5 PC 4 5 5 6 After execution A 2534 FFEE PCB C 5 PC 4 5 5 A +4 C54556H 73 C54557H 9E C54558H 20 C54559H 00 MOVW A, @PC+20H C5455AH . . . +20H C5457AH EE C5457BH FF 475 APPENDIX B Instructions ● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7) Memory is accessed using the address determined by adding RW0 or RW1 to the contents of generalpurpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB). Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7) MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with a base index and stores it in A.) Before execution A 0716 RW1 D 3 0 F WR7 0 1 0 1 After execution A 2534 RW1 D 3 0 F WR7 0 1 0 1 476 2534 + DTB 7 8 FFEE DTB 7 8 Memory space 78D410H EE 78D411H FF APPENDIX B Instructions ● Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to 23 are indicated by the program counter bank register (PCB). Figure B.4-7 Example of Program Counter Relative Branch Addressing (rel) BRA 10H (This instruction causes an unconditional relative branch.) Before execution After execution PC 3 C 2 0 PC 3 C 3 2 PCB 4 F PCB 4 F Memory space 4F3C32H Next instruction 4F3C21H 10 4F3C20H 60 BRA 10H ● Register list (rlst) Specify a register to be pushed onto or popped from a stack. Figure B.4-8 Configuration of the Register List MSB LSB RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0 A register is selected when the corresponding bit is 1 and deselected when the bit is 0. 477 APPENDIX B Instructions Figure B.4-9 Example of Register List (rlist) POPW, RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.) SP 34FA SP 34FE RW0 ×× ×× RW0 02 01 RW1 ×× ×× RW1 ×× ×× RW2 ×× ×× RW2 ×× ×× RW3 ×× ×× RW3 ×× ×× RW4 ×× ×× RW4 04 03 RW5 ×× ×× RW5 ×× ×× RW6 ×× ×× RW6 ×× ×× RW7 ×× ×× RW7 ×× ×× Memory space SP Memory space 01 34FAH 01 34FAH 02 34FBH 02 34FBH 03 34FCH 03 34FCH 04 34FDH 04 34FDH 34FEH SP Before execution 34FEH After execution ● Accumulator indirect addressing (@A) Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB). Figure B.4-10 Example of Accumulator Indirect Addressing (@A) MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.) Before execution A 0716 2534 DTB B B After execution A 0716 DTB B B 478 FFEE Memory space BB2534H EE BB2535H FF APPENDIX B Instructions ● Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program counter bank register (PCB). For the Jump Context (JCTX) instruction, however, address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for unconditional branch instructions. Figure B.4-11 Example of Accumulator Indirect Branch Addressing (@A) JMP @A (This instruction causes an unconditional branch by accumulator indirect branch addressing.) Before execution PC 3 C 2 0 A 6677 After execution PC 3 B 2 0 A 6677 PCB 4 F 3B20 Memory space 4F3B20H Next instruction 4F3C20H 61 JMP @A PCB 4 F 3B20 ● Indirect specification branch addressing (@ear) The address of the branch destination is the word data at the address indicated by ear. Figure B.4-12 Example of Indirect Specification Branch Addressing (@ear) JMP @@RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution After execution PC 3 C 2 0 PCB 4 F RW0 7 F 4 8 DTB 2 1 PC 3 B 2 0 RW0 7 F 4 8 PCB 4 F Memory space 217F48H 20 217F49H 3B 4F3B20H Next instruction 4F3C20H 73 4F3C21H 08 JMP @@RW0 DTB 2 1 479 APPENDIX B Instructions ● Indirect specification branch addressing (@eam) The address of the branch destination is the word data at the address indicated by eam. Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam) JMP @RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution PC 3 C 2 0 PCB 4 F RW0 3 B 2 0 After execution PC 3 B 2 0 RW0 3 B 2 0 480 PCB 4 F Memory space 4F3B20H Next instruction 4F3C20H 73 4F3C21H 00 JMP @RW0 APPENDIX B Instructions B.5 Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. ■ Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments. Therefore, intervening in data access increases the execution cycle count. Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the program fetches every byte of an instruction being executed. Therefore, intervening in data access increases the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register, internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register. Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add the "access count x cycle count for the halt" as a correction value to the normal execution count. 481 APPENDIX B Instructions ■ Calculating the Execution Cycle Count Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data. Table B.5-1 Execution Cycle Counts in Each Addressing Mode (a) * Code Operand 00 | 07 Ri Rwi RLi 08 | 0B Execution cycle count in each addressing mode Register access count in each addressing mode See the instruction list. See the instruction list. @RWj 2 1 0C | 0F @RWj+ 4 2 10 | 17 @RWi+disp8 2 1 18 | 1B @RWi+disp16 2 1 1C 1D 1E 1F @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 4 4 2 1 2 2 0 0 *: (a) is used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List". 482 APPENDIX B Instructions Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles (b) byte * Operand (c) word * (d) long * Cycle count Access count Cycle count Access count Cycle count Access count Internal register +0 1 +0 1 +0 2 Internal memory Even address +0 1 +0 1 +0 2 Internal memory Odd address +0 1 +2 2 +4 4 External data bus 16-bit even address +1 1 +1 1 +2 2 External data bus 16-bit odd address +1 1 +4 2 +8 4 External data bus 8-bits +1 1 +4 2 +8 4 *: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List". Note: When an external data bus is used, the cycle counts during which an instruction is made to wait by ready input or automatic ready must also be added. Table B.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles Instruction Byte boundary Word boundary Internal memory - +2 External data bus 16-bits - +3 External data bus 8-bits +3 - Notes: • When an external data bus is used, the cycle counts during which an instruction is made to wait by ready input or automatic ready must also be added. • Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the correction values to calculate the worst case. 483 APPENDIX B Instructions B.6 Effective address field Table B.6-1 shows the effective address field. ■ Effective Address Field Table B.6-1 Effective Address Field Code Representation Address format Byte count of extended address part * Register direct: Individual parts correspond to the byte, word, and long word types in order from the left. - Register indirect 0 Register indirect with post increment 0 Register indirect with 8-bit displacement 1 Register indirect with 16-bit displacement 2 00 01 R0 R1 RW0 RW1 RL0 (RL0) 02 03 R2 R3 RW2 RW3 RL1 (RL1) 04 05 R4 R5 RW4 RW5 RL2 (RL2) 06 07 R6 R7 RW6 RW7 RL3 (RL3) 08 09 @RW0 @RW1 0A 0B @RW2 @RW3 0C 0D @RW0+ @RW1+ 0E 0F @RW2+ @RW3+ 10 11 @RW0+disp8 @RW1+disp8 12 13 @RW2+disp8 @RW3+disp8 14 15 @RW4+disp8 @RW5+disp8 16 17 @RW6+disp8 @RW7+disp8 18 19 @RW0+disp16 @RW1+disp16 1A 1B @RW2+disp16 @RW3+disp16 1C 1D @RW0+RW7 @RW1+RW7 Register indirect with index Register indirect with index 0 0 1E 1F @PC+disp16 addr16 PC indirect with 16-bit displacement Direct address 2 2 *1: Each byte count of the extended address part applies to + in the # (byte count) column in "B.8 F2MC-16LX Instruction List". 484 APPENDIX B Instructions B.7 How to Read the Instruction List Table B.7-1 describes the items used in "B.8 F2MC-16LX Instruction List", and Table B.7-2 describes the symbols used in the same list. ■ Description of Instruction Presentation Items and Symbols Table B.7-1 Description of Items in the Instruction List (1/2) Item Mnemonic Description Uppercase, symbol: Represented as is in the assembler. Lowercase: Rewritten in the assembler. Number of following lowercase: Indicates bit length in the instruction. # Indicates the number of bytes. ~ Indicates the number of cycles. See Table B.2-1 for the alphabetical letters in items. RG B Operation Indicates the number of times a register access is performed during instruction execution. The number is used to calculate the correction value for CPU intermittent operation. Indicates the correction value used to calculate the actual number of cycles during instruction execution. The actual number of cycles during instruction execution can be determined by adding the value in the ~ column to this value. Indicates the instruction operation. LH Indicates the special operation for bit15 to bit08 of the accumulator. Z: Transfers 0. X: Transfers after sign extension. -: No transfer AH Indicates the special operation for the 16 high-order bits of the accumulator. *: Transfers from AL to AH. -: No transfer Z: Transfers 00 to AH. X: Transfers 00H or FFH to AH after AL sign extension. I S T N Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), C (carry). *: Changes upon instruction execution. -: No change S: Set upon instruction execution. R: Reset upon instruction execution. Z V C 485 APPENDIX B Instructions Table B.7-1 Description of Items in the Instruction List (1/2) Item Description RMW Indicates whether the instruction is a Read Modify Write instruction (reading data from memory by the I instruction and writing the result to memory). *: Read Modify Write instruction -: Not Read Modify Write instruction Note: Cannot be used for an address that has different meanings between read and write operations. Table B.7-2 Explanation on Symbols in the Instruction List (1/2) Symbol A The bit length used varies depending on the 32-bit accumulator instruction. Byte: Low-order 8 bits of byte AL Word: 16 bits of word AL Long word: 32 bits of AL and AH AH 16 high-order bits of A AL 16 low-order bits of A SP Stack pointer (USP or SSP) PC Program counter PCB program counter bank register DTB Data bank register ADB Additional data bank register SSB System stack bank register USB User stack bank register SPB Current stack bank register (SSB or USB) DPR Direct page register brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB brg2 DTB, ADB, SSB, USB, DPR, SPB Ri R0, R1, R2, R3, R4, R5, R6, R7 RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RWj RW0, RW1, RW2, RW3 RLi RL0, RL1, RL2, RL3 dir Abbreviated direct addressing addr16 Direct addressing addr24 Physical direct addressing ad24 0-15 486 Explanation Bit0 to bit15 of addr24 APPENDIX B Instructions Table B.7-2 Explanation on Symbols in the Instruction List (1/2) Symbol ad24 16-23 io Explanation Bit16 to bit23 of addr24 I/O area (000000H to 0000FFH) #imm4 4-bit immediate data #imm8 8-bit immediate data #imm16 16-bit immediate data #imm32 32-bit immediate data ext (imm8) 16-bit data obtained by sign extension of 8-bit immediate data disp8 8-bit displacement disp16 16-bit displacement bp Bit offset vct4 Vector number (0 to 15) vct8 Vector number (0 to 255) ( )b Bit address rel PC relative branch ear Effective addressing (code 00 to 07) eam Effective addressing (code 08 to 1F) rlst Register list 487 APPENDIX B Instructions B.8 F2MC-16LX Instruction List Table B.8-1 to Table B.8-18 list the instructions used by the F2MC-16LX. ■ F2MC-16LX Instruction List Table B.8-1 41 Transfer Instructions (Byte) Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV XCH XCH XCH XCH A,dir A,addr16 A,Ri A,ear A,eam A,io A,#imm8 A,@A A,@RLi+disp8 A,#imm4 A,dir A,addr16 A,Ri A,ear A,eam A,io A,#imm8 A,@A A,@RWi+disp8 A,@RLi+disp8 dir,A addr16,A Ri,A ear,A eam,A io,A @RLi+disp8,A Ri,ear Ri,eam ear,Ri eam,Ri Ri,#imm8 io,#imm8 dir,#imm8 ear,#imm8 eam,#imm8 @AL,AH A,ear A,eam Ri,ear Ri,eam # ~ RG B 2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ 3 4 2 2 3 + (a) 3 2 3 10 1 3 4 2 2 3 + (a) 3 2 3 5 10 3 4 2 2 3 + (a) 3 10 3 4 + (a) 4 5 + (a) 2 5 5 2 4 + (a) 3 4 5 + (a) 7 9 + (a) 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2 × (b) 0 2 × (b) Operation byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← imm8 byte (A) ← ((A)) byte (A) ← ((RLi)+disp8) byte (A) ← imm4 byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← imm8 byte (A) ← ((A)) byte (A) ← ((RWi)+disp8) byte (A) ← ((RLi)+disp8) byte (dir) ← (A) byte (addr16) ← (A) byte (Ri) ← (A) byte (ear) ← (A) byte (eam) ← (A) byte (io) ← (A) byte ((RLi)+disp8) ← (A) byte (Ri) ← (ear) byte (Ri) ← (eam) byte (ear) ← (Ri) byte (eam) ← (Ri) byte (Ri) ← imm8 byte (io) ← imm8 byte (dir) ← imm8 byte (ear) ← imm8 byte (eam) ← imm8 byte ((A)) ← (AH) byte (A) ↔ (ear) byte (A) ↔ (eam) byte (Ri) ↔ (ear) byte (Ri) ↔ (eam) LH AH I S T N Z V C RMW Z Z Z Z Z Z Z Z Z Z X X X X X X X X X X Z Z - * * * * * * * * * * * * * * * * * * - - - - * * * * * * * * * R * * * * * * * * * * * * * * * * * * * * * * * * - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - Note: See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table. 488 APPENDIX B Instructions Table B.8-2 38 Transfer Instructions (Word, Long Word) Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW XCHW XCHW XCHW XCHW MOVL MOVL MOVL MOVL MOVL A,dir A,addr16 A,SP A,RWi A,ear A,eam A,io A,@A A,#imm16 A,@RWi+disp8 A,@RLi+disp8 dir,A addr16,A SP,A RWi,A ear,A eam,A io,A @RWi+disp8,A @RLi+disp8,A RWi,ear RWi,eam ear,RWi eam,RWi RWi,#imm16 io,#imm16 ear,#imm16 eam,#imm16 @AL,AH A,ear A,eam RWi, ear RWi, eam A,ear A,eam A,#imm32 ear,A eam,A # ~ RG B 2 3 1 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 2 2+ 5 2 2+ 3 4 1 2 2 3 + (a) 3 3 2 5 10 3 4 1 2 2 3 + (a) 3 5 10 3 4 + (a) 4 5 + (a) 2 5 2 4 + (a) 3 4 5 + (a) 7 9 + (a) 4 5 + (a) 3 4 5 + (a) 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 2 0 0 2 0 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) 0 2 × (c) 0 2 × (c) 0 (d) 0 0 (d) Operation word (A) ← (dir) word (A) ← (addr16) word (A) ← (SP) word (A) ← (RWi) word (A) ← (ear) word (A) ← (eam) word (A) ← (io) word (A) ← ((A)) word (A) ← imm16 word (A) ← ((RWi)+disp8) word (A) ← ((RLi)+disp8) word (dir) ← (A) word (addr16) ← (A) word (SP) ← (A) word (RWi) ← (A) word (ear) ← (A) word (eam) ← (A) word (io) ← (A) word ((RWi)+disp8) ← (A) word ((RLi)+disp8) ← (A) word (RWi) ← (ear) word (RWi) ← (eam) word (ear) ← (RWi) word (eam) ← (RWi) word (RWi) ← imm16 word (io) ← imm16 word (ear) ← imm16 word (eam) ← imm16 word ((A)) ← (AH) word (A) ↔ (ear) word (A) ↔ (eam) word (RWi) ↔ (ear) word (RWi) ↔ (eam) long (A) ← (ear) long (A) ← (eam) long (A) ← imm32 long (ear) ← (A) long(eam) ← (A) LH AH I S T N Z V C RMW - * * * * * * * * * * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - Note: See Table B.5-1 and Table B.5-2 for information on (a), (c), and (d) in the table. 489 APPENDIX B Instructions Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word) Mnemonic # ~ RG B ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4 + (a) 3 5 + (a) 2 3 4 + (a) 3 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 × (b) 0 0 (b) 0 SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4 + (a) 3 5 + (a) 2 3 4 + (a) 3 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 × (b) 0 0 (b) 0 ADDW ADDW ADDW ADDW ADDW ADDW ADDCW ADDCW SUBW SUBW SUBW SUBW SUBW SUBW SUBCW SUBCW ADDL ADDL ADDL SUBL SUBL SUBL A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A,ear A,eam A,#imm32 A,ear A,eam A,#imm32 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 2+ 5 2 2+ 5 2 3 4+(a) 2 3 5+(a) 3 4+(a) 2 3 4+(a) 2 3 5+(a) 3 4+(a) 6 7+(a) 4 6 7+(a) 4 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0 0 0 (c) 0 0 2 × (c) 0 (c) 0 0 (c) 0 0 2 × (c) 0 (c) 0 (d) 0 0 (d) 0 Operation byte (A) ← (A) + imm8 byte (A) ← (A) + (dir) byte (A) ← (A) + (ear) byte (A) ← (A) + (eam) byte (ear) ← (ear) + (A) byte (eam) ← (eam) + (A) byte (A) ← (AH) + (AL) + (C) byte (A) ← (A) + (ear)+ (C) byte (A) ← (A) + (eam)+ (C) byte (A) ← (AH) + (AL) + (C) (decimal) byte (A) ← (A) - imm8 byte (A) ← (A) - (dir) byte (A) ← (A) - (ear) byte (A) ← (A) - (eam) byte (ear) ← (ear) - (A) byte (eam) ← (eam) - (A) byte (A) ← (AH) - (AL) - (C) byte (A) ← (A) - (ear) - (C) byte (A) ← (A) - (eam) - (C) byte (A) ← (AH) - (AL) - (C) (decimal) word (A) ← (AH) + (AL) word (A) ← (A) + (ear) word (A) ← (A) + (eam) word (A) ← (A) + imm16 word (ear) ← (ear) + (A) word (eam) ← (eam) + (A) word (A) ← (A) + (ear) + (C) word (A) ← (A) + (eam) + (C) word (A) ← (AH) - (AL) word (A) ← (A) - (ear) word (A) ← (A) - (eam) word (A) ← (A) - imm16 word (ear) ← (ear) - (A) word (eam) ← (eam) - (A) word (A) ← (A) - (ear) - (C) word (A) ← (A) - (eam) - (C) long (A) ← (A) + (ear) long (A) ← (A) + (eam) long (A) ← (A) + imm32 long (A) ← (A) - (ear) long (A) ← (A) - (eam) long (A) ← (A) - imm32 LH AH I S T N Z V C RMW Z Z Z Z Z Z Z Z Z - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - Z Z Z Z Z Z Z Z - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 490 APPENDIX B Instructions Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word) # ~ RG B INC Mnemonic ear 2 3 2 0 INC eam 2+ 5+(a) 0 2 × (b) DEC ear 2 3 2 0 DEC eam 2+ 5+(a) 0 2 × (b) INCW ear 2 3 2 0 INCW eam 2+ 5+(a) 0 2 × (c) DECW ear 2 3 2 0 DECW eam 2+ 5+(a) 0 2 × (c) INCL ear 2 7 4 0 INCL eam 2+ 9+(a) 0 2 × (d) DECL ear 2 7 4 0 DECL eam 2+ 9+(a) 0 2 × (d) LH AH I S T N Z V C byte (ear) ← (ear) + 1 Operation - - - - - * * * - RMW - byte (eam) ← (eam) + 1 - - - - - * * * - * byte (ear) ← (ear) - 1 - - - - - * * * - - byte (eam) ← (eam) - 1 - - - - - * * * - * word (ear) ← (ear) + 1 - - - - - * * * - - word (eam) ← (eam) + 1 - - - - - * * * - * word (ear) ← (ear) - 1 - - - - - * * * - - word (eam) ← (eam) - 1 - - - - - * * * - * long (ear) ← (ear) + 1 - - - - - * * * - - long (eam) ← (eam) + 1 - - - - - * * * - * long (ear) ← (ear) - 1 - - - - - * * * - - long (eam) ← (eam) - 1 - - - - - * * * - * Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. Table B.8-5 11 Compare Instructions (Byte, Word, Long Word) Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW CMP A 1 1 0 0 byte (AH) - (AL) - - - - - * * * * - CMP A,ear 2 2 1 0 byte (A) - (ear) - - - - - * * * * - CMP A,eam 2+ 3+(a) 0 (b) byte (A) - (eam) - - - - - * * * * - CMP A,#imm8 2 2 0 0 byte (A) - imm8 - - - - - * * * * - CMPW A 1 1 0 0 word (AH) - (AL) - - - - - * * * * - CMPW A,ear 2 2 1 0 word (A) - (ear) - - - - - * * * * - CMPW A,eam 2+ 3+(a) 0 (c) word (A) - (eam) - - - - - * * * * - CMPW A,#imm16 3 2 0 0 word (A) - imm16 - - - - - * * * * - CMPL A,ear 2 6 2 0 long (A) - (ear) - - - - - * * * * - CMPL A,eam 2+ 7+(a) 0 (d) long (A) - (eam) - - - - - * * * * - CMPL A,#imm32 5 3 0 0 long (A) - imm32 - - - - - * * * * - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 491 APPENDIX B Instructions Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word) # ~ RG B LH AH I S T N Z V C RMW DIVU Mnemonic A 1 *1 0 0 word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) Operation - - - - - - - * * - DIVU A,ear 2 *2 1 0 word (A) / byte (ear) quotient → byte (A) remainder → byte (ear) - - - - - - - * * - DIVU A,eam 2+ *3 0 *6 word (A) / byte (eam) quotient → byte (A) remainder → byte (eam) - - - - - - - * * - DIVUW A,ear 2 *4 1 0 long (A) / word (ear) quotient → word (A) remainder → word (ear) - - - - - - - * * - DIVUW A,eam 2+ *5 0 *7 long (A) / word (eam) quotient → word (A) remainder → word (eam) - - - - - - - * * - MULU A 1 *8 0 0 byte (AH) * byte (AL) → word (A) - - - - - - - - - - MULU A,ear 2 *9 1 0 byte (A) * byte (ear) → word (A) - - - - - - - - - - MULU A,eam 2+ *10 0 (b) byte (A) * byte (eam) → word (A) - - - - - - - - - - MULUW A 1 *11 0 0 word (AH) * word (AL) → Long (A) - - - - - - - - - - MULUW A,ear 2 *12 1 0 word (A) * word (ear) → Long (A) - - - - - - - - - - MULUW A,eam 2+ *13 0 (c) word (A) * word (eam) → Long (A) - - - - - - - - - - *1: 3: Division by 0 7: Overflow 15: Normal *2: 4: Division by 0 8: Overflow 16: Normal *3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal *4: 4: Division by 0 7: Overflow 22: Normal *5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal *6: (b): Division by 0 or overflow 2 × (b): Normal *7: (c): Division by 0 or overflow 2 × (c): Normal *8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0. *9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0. *10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0. *11: 3: Word (AH) is 0. 11: Word (AH) is not 0. *12: 4: Word (ear) is 0. 12: Word (ear) is not 0. *13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0. Note: See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table. 492 APPENDIX B Instructions Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word) # ~ RG B LH AH I S T N Z V C RMW DIV Mnemonic A 2 *1 0 0 word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) Operation Z - - - - - - * * - DIV A,ear 2 *2 1 0 word (A) / byte (ear) quotient → byte (A) remainder → byte (ear) Z - - - - - - * * - DIV A,eam 2+ *3 0 *6 word (A) / byte (eam) quotient → byte (A) remainder → byte (eam) Z - - - - - - * * - DIVW A,ear 2 *4 1 0 long (A) / word (ear) quotient → word (A) remainder → word (ear) - - - - - - - * * - DIVW A,eam 2+ *5 0 *7 long (A) / word (eam) quotient → word (A) remainder → word (eam) - - - - - - - * * - MUL A 2 *8 0 0 byte (AH) * byte (AL) → word (A) - - - - - - - - - - MUL A,ear 2 *9 1 0 byte (A) * byte (ear) → word (A) - - - - - - - - - - MUL A,eam 2+ *10 0 (b) byte (A) * byte (eam) → word (A) - - - - - - - - - - MULW A 2 *11 0 0 word (AH) * word (AL) → Long (A) - - - - - - - - - - MULW A,ear 2 *12 1 0 word (A) * word (ear) → Long (A) - - - - - - - - - - MULW A,eam 2+ *13 0 (c) word (A) * word (eam) → Long (A) - - - - - - - - - - *1: *2: *3: *4: 3: Division by 0, 8 or 18: Overflow, 18: Normal 4: Division by 0, 11 or 22: Overflow, 23: Normal 5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal *5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal *6: (b): Division by 0 or overflow, 2 × (b): Normal *7: (c): Division by 0 or overflow, 2 × (c): Normal *8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative *9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative *10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative *11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative *12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative *13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative Notes: • The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a pre-operation count or a post-operation count depending on the detection timing. • When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed. • See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table. 493 APPENDIX B Instructions Table B.8-8 39 Logic 1 Instructions (Byte, Word) Mnemonic # ~ RG B Operation LH AH I S T N Z V C AND A,#imm8 2 2 0 0 byte (A) ← (A) and imm8 - - - - - * * R - RMW - AND A,ear 2 3 1 0 byte (A) ← (A) and (ear) - - - - - * * R - - AND A,eam 2+ 4+(a) 0 (b) byte (A) ← (A) and (eam) - - - - - * * R - - AND ear,A 2 3 2 0 byte (ear) ← (ear) and (A) - - - - - * * R - - AND eam,A 2+ 5+(a) 0 2 × (b) byte (eam) ← (eam) and (A) - - - - - * * R - * OR A,#imm8 2 2 0 0 byte (A) ← (A) or imm8 - - - - - * * R - - OR A,ear 2 3 1 0 byte (A) ← (A) or (ear) - - - - - * * R - - OR A,eam 2+ 4+(a) 0 (b) byte (A) ← (A) or (eam) - - - - - * * R - - OR ear,A 2 3 2 0 byte (ear) ← (ear) or (A) - - - - - * * R - - OR eam,A 2+ 5+(a) 0 2 × (b) byte (eam) ← (eam) or (A) - - - - - * * R - * XOR A,#imm8 2 2 0 0 byte (A) ← (A) xor imm8 - - - - - * * R - - XOR A,ear 2 3 1 0 byte (A) ← (A) xor (ear) - - - - - * * R - - XOR A,eam 2+ 4+(a) 0 (b) byte (A) ← (A) xor (eam) - - - - - * * R - - XOR ear,A 2 3 2 0 byte (ear) ← (ear) xor (A) - - - - - * * R - - XOR eam,A 2+ 5+(a) 0 2 × (b) byte (eam) ← (eam) xor (A) - - - - - * * R - * NOT A 1 2 0 0 byte (A) ← not (A) - - - - - * * R - - NOT ear 2 3 2 0 byte (ear) ← not (ear) - - - - - * * R - - NOT eam 2+ 5+(a) 0 2 × (b) byte (eam) ← not (eam) - - - - - * * R - * ANDW A 1 2 0 0 word (A) ← (AH) and (A) - - - - - * * R - - ANDW A,#imm16 3 2 0 0 word (A) ← (A) and imm16 - - - - - * * R - - ANDW A,ear 2 3 1 0 word (A) ← (A) and (ear) - - - - - * * R - - ANDW A,eam 2+ 4+(a) 0 (c) word (A) ← (A) and (eam) - - - - - * * R - - ANDW ear,A 2 3 2 0 word (ear) ← (ear) and (A) - - - - - * * R - - ANDW eam,A 2+ 5+(a) 0 2 × (c) word (eam) ← (eam) and (A) - - - - - * * R - * ORW A 1 2 0 0 word (A) ← (AH) or (A) - - - - - * * R - - ORW A,#imm16 3 2 0 0 word (A) ← (A) or imm16 - - - - - * * R - - ORW A,ear 2 3 1 0 word (A) ← (A) or (ear) - - - - - * * R - - ORW A,eam 2+ 4+(a) 0 (c) word (A) ← (A) or (eam) - - - - - * * R - ORW ear,A 2 3 2 0 word (ear) ← (ear) or (A) - - - - - * * R - - ORW eam,A 2+ 5+(a) 0 2 × (c) word (eam) ← (eam) or (A) - - - - - * * R - * XORW A 1 2 0 0 word (A) ← (AH) xor (A) - - - - - * * R - - XORW A,#imm16 3 2 0 0 word (A) ← (A) xor imm16 - - - - - * * R - - XORW A,ear 2 3 1 0 word (A) ← (A) xor (ear) - - - - - * * R - - XORW A,eam 2+ 4+(a) 0 (c) word (A) ← (A) xor (eam) - - - - - * * R - - XORW ear,A 2 3 2 0 word (ear) ← (ear) xor (A) - - - - - * * R - - XORW eam,A 2+ 5+(a) 0 2 × (c) word (eam) ← (eam) xor (A) - - - - - * * R - * NOTW A 1 2 0 0 word (A) ← not (A) - - - - - * * R - - NOTW ear 2 3 2 0 word (ear) ← not (ear) - - - - - * * R - - NOTW eam 2+ 5+(a) 0 2 × (c) word (eam) ← not (eam) - - - - - * * R - * Note: See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table. 494 APPENDIX B Instructions Table B.8-9 6 Logic 2 Instructions (Long Word) Mnemonic # ~ RG B LH AH I S T N Z V C RMW ANDL A,ear 2 6 2 0 long (A) ← (A) and (ear) Operation - - - - - * * R - - ANDL A,eam 2+ 7+(a) 0 (d) long (A) ← (A) and (eam) - - - - - * * R - - ORL A,ear 2 6 2 0 long (A) ← (A) or (ear) - - - - - * * R - - ORL A,eam 2+ 7+(a) 0 (d) long (A) ← (A) or (eam) - - - - - * * R - - XORL A,ear 2 6 2 0 long (A) ← (A) xor (ear) - - - - - * * R - - XORL A,eam 2+ 7+(a) 0 (d) long (A) ← (A) xor (eam) - - - - - * * R - - Note: See Table B.5-1 and Table B.5-2 for information on (a) and (d) in the table. Table B.8-10 6 Sign Inversion Instructions (Byte, Word) Mnemonic NEG A # ~ RG B LH AH I S T N Z V C RMW 1 2 0 0 byte (A) ← 0 - (A) X - - - - * * * * - byte (ear) ← 0 - (ear) - - - - - * * * * - byte (eam) ← 0 - (eam) - - - - - * * * * * word (A) ← 0 - (A) - - - - - * * * * - word (ear) ← 0 - (ear) - - - - - * * * * - word (eam) ← 0 - (eam) - - - - - * * * * * NEG ear 2 3 2 0 NEG eam 2+ 5+(a) 0 2 × (b) NEGW A 1 2 0 0 NEGW ear 2 3 2 0 NEGW eam 2+ 5+(a) 0 2 × (c) Operation Note: See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table. Table B.8-11 1 Normalization Instruction (Long Word) Mnemonic NRML A,R0 # ~ RG B 2 *1 1 0 Operation long (A) ← Shift left to the position where '1' is set for the first time. byte (R0) ← Shift count at that time LH AH I S T N Z V C RMW - - - - - - * - - - *1: 4 when all accumulators have a value of 0; otherwise, 6+(R0) 495 APPENDIX B Instructions Table B.8-12 18 Shift Instructions (Byte, Word, Long Word) # ~ RG B LH AH I S T N Z V C RORC Mnemonic A 2 2 0 0 byte (A) ← Right rotation with carry Operation - - - - - * * - * RMW - ROLC A 2 2 0 0 byte (A) ← Right rotation with carry - - - - - * * - * - RORC ear 2 3 2 0 byte (ear) ← Right rotation with carry - - - - - * * - * - RORC eam 2+ 5+(a) 0 2 × (b) byte (eam) ← Right rotation with carry - - - - - * * - * * ROLC ear 2 3 2 0 byte (ear) ← Left rotation with carry - - - - - * * - * - ROLC eam 2+ 5+(a) 0 2 × (b) byte (eam) ← Left rotation with carry - - - - - * * - * * ASR A,R0 2 *1 1 0 byte (A) ← Arithmetic right shift (A, 1 bit) - - - - * * * - * - LSR A,R0 2 *1 1 0 byte (A) ← Logical right barrel shift (A, R0) - - - - * * * - * - LSL A,R0 2 *1 1 0 byte (A) ← Logical left barrel shift (A, R0) - - - - - * * - * - ASRW A 1 2 0 0 word (A) ← Arithmetic right shift (A, 1 bit) - - - - * * * - * - LSRW A/SHRW A 1 2 0 0 word (A) ← Logical right shift (A, 1 bit) - - - - * R * - * - LSLW A/SHLW A 1 2 0 0 word (A) ← Logical left shift (A, 1 bit) - - - - - * * - * - ASRW A,R0 2 *1 1 0 word (A) ← Arithmetic right barrel shift (A, R0) - - - - * * * - * - LSRW A,R0 2 *1 1 0 word (A) ← Logical right barrel shift (A, R0) - - - - * * * - * - LSLW A,R0 2 *1 1 0 word (A) ← Logical left barrel shift (A, R0) - - - - - * * - * - ASRL A,R0 2 *2 1 0 long (A) ← Arithmetic right barrel shift (A, R0) - - - - * * * - * - LSRL A,R0 2 *2 1 0 long (A) ← Logical right barrel shift (A, R0) - - - - * * * - * - LSLL A,R0 2 *2 1 0 long (A) ← Logical left barrel shift (A, R0) - - - - - * * - * - *1: 6 when R0 is 0; otherwise, 5 + (R0) *2: 6 when R0 is 0; otherwise, 6 + (R0) Note: See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table. 496 APPENDIX B Instructions Table B.8-13 31 Branch 1 Instructions # ~ RG B LH AH I S T N Z V C RMW BZ/BEQ Mnemonic rel 2 *1 0 0 Branch on (Z) = 1 Operation - - - - - - - - - - BNZ/ BNE rel 2 *1 0 0 Branch on (Z) = 0 - - - - - - - - - - BC/BLO rel 2 *1 0 0 Branch on (C) = 1 - - - - - - - - - - BNC/ BHS rel 2 *1 0 0 Branch on (C) = 0 - - - - - - - - - - BN rel 2 *1 0 0 Branch on (N) = 1 - - - - - - - - - - BP rel 2 *1 0 0 Branch on (N) = 0 - - - - - - - - - - BV rel 2 *1 0 0 Branch on (V) = 1 - - - - - - - - - - BNV rel 2 *1 0 0 Branch on (V) = 0 - - - - - - - - - - BT rel 2 *1 0 0 Branch on (T) = 1 - - - - - - - - - - BNT rel 2 *1 0 0 Branch on (T) = 0 - - - - - - - - - - BLT rel 2 *1 0 0 Branch on (V) xor (N) = 1 - - - - - - - - - - BGE rel 2 *1 0 0 Branch on (V) xor (N) = 0 - - - - - - - - - - BLE rel 2 *1 0 0 Branch on ((V) xor (N)) or (Z) = 1 - - - - - - - - - - BGT rel 2 *1 0 0 Branch on ((V) xor (N)) or (Z) = 0 - - - - - - - - - - BLS rel 2 *1 0 0 Branch on (C) or (Z) = 1 - - - - - - - - - - BHI rel 2 *1 0 0 Branch on (C) or (Z) = 0 - - - - - - - - - - BRA rel 2 *1 0 0 Unconditional branch - - - - - - - - - - JMP @A 1 2 0 0 word (PC) ← (A) - - - - - - - - - - JMP addr16 3 3 0 0 word (PC) ← addr16 - - - - - - - - - - JMP @ear 2 3 1 0 word (PC) ← (ear) - - - - - - - - - - JMP @eam 2+ 4+(a) 0 (c) word (PC) ← (eam) - - - - - - - - - - JMPP @ear *3 2 5 2 0 word (PC) ← (ear), (PCB) ← (ear+2) - - - - - - - - - - JMPP @eam *3 2+ 6+(a) 0 (d) word (PC) ← (eam), (PCB) ← (eam+2) - - - - - - - - - - JMPP addr24 4 4 0 0 word (PC) ← ad24 0-15, (PCB) ← ad24 16-23 - - - - - - - - - - CALL @ear *4 2 6 1 (c) word (PC) ← (ear) - - - - - - - - - - CALL @eam *4 2+ 7+(a) 0 2 × (c) word (PC) ← (eam) - - - - - - - - - - CALL addr16 *5 3 6 0 (c) word (PC) ← addr16 - - - - - - - - - - CALLV #vct4 *5 1 7 0 2 × (c) Vector call instruction - - - - - - - - - - CALLP @ear *6 2 10 2 2 × (c) word (PC) ← (ear), (PCB) ← (ear+2) - - - - - - - - - - CALLP @eam *6 2+ 11+(a) 0 *2 CALLP addr24 *7 4 10 0 2 × (c) word (PC) ← (eam), (PCB) ← (eam+2) - - - - - - - - - - word (PC) ← ad24 0-15, (PCB) ← ad24 16-23 - - - - - - - - - - *1: 4 when a branch is made; otherwise, 3 *2: 3 × (c) + (b) *3: Read (word) of branch destination address *4: W: Save to stack (word) R: Read (word) of branch destination address *5: Save to stack (word) *6: W: Save to stack (long word), R: Read (long word) of branch destination address *7: Save to stack (long word) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 497 APPENDIX B Instructions Table B.8-14 19 Branch 2 Instructions Mnemonic # ~ RG B LH AH I S T N Z V C CBNE A,#imm8,rel 3 *1 0 0 Branch on byte (A) not equal to imm8 Operation - - - - - * * * * RMW - CWBNE A,#imm16,rel 4 *1 0 0 Branch on word (A) not equal to imm16 - - - - - * * * * - CBNE ear,#imm8,rel 4 *2 1 0 Branch on byte (ear) not equal to imm8 - - - - - * * * * - CBNE eam,#imm8,rel *9 4+ *3 0 (b) Branch on byte (eam) not equal to imm8 - - - - - * * * * - CWBNE ear,#imm16,rel 5 *4 1 0 Branch on word (ear) not equal to imm16 - - - - - * * * * - CWBNE eam,#imm16,rel*9 5+ *3 0 (c) Branch on word (eam) not equal to imm16 - - - - - * * * * - ear,rel 3 *5 2 eam,rel 3+ *6 2 DWBNZ ear,rel 3 *5 2 - - - - - * * * - - DWBNZ eam,rel 3+ *6 2 2 × (c) word (eam) ← (eam) - 1, Branch on (eam) not equal to 0 - - - - - * * * - * INT #vct8 2 20 0 8 × (c) Software interrupt - - R S - - - - - - INT addr16 3 16 0 6 × (c) Software interrupt - - R S - - - - - - INTP addr24 4 17 0 6 × (c) Software interrupt - - R S - - - - - - INT9 1 20 0 8 × (c) Software interrupt - - R S - - - - - - RETI 1 *8 0 *7 Return from interrupt - - * * * * * * * - 2 6 0 (c) Saves the old frame pointer in the stack upon entering the function, then sets the new frame pointer and reserves the local pointer area. - - - - - - - - - - 1 5 0 (c) Recovers the old frame pointer from the stack upon exiting the function. - - - - - - - - - - LINK #imm8 UNLINK 0 byte (ear) ← (ear) - 1, Branch on (ear) not equal to 0 DBNZ DBNZ 2 × (b) byte (eam) ← (eam) - 1, Branch on (eam) not equal to 0 0 word (ear) ← (ear) - 1, Branch on (ear) not equal to 0 - - - - - * * * - - - - - - - * * * - * RET *10 1 4 0 (c) Return from subroutine - - - - - - - - - - RETP *11 1 6 0 (d) Return from subroutine - - - - - - - - - - *1: 5 when a branch is made; otherwise, 4 *2: 13 when a branch is made; otherwise, 12 *3: 7+(a) when a branch is made; otherwise, 6+(a) *4: 8 when a branch is made; otherwise, 7 *5: 7 when a branch is made; otherwise, 6 *6: 8+(a) when a branch is made; otherwise, 7+(a) *7: 3 × (b) + 2 × (c) when jumping to the next interruption request; 6 × (c) when returning from the current interruption *8: 15 when jumping to the next interruption request; 17 when returning from the current interruption *9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction. *10: Return from stack (word) *11: Return from stack (long word) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 498 APPENDIX B Instructions Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word) # ~ RG B LH AH I S T N Z V C RMW PUSHW Mnemonic A 1 4 0 (c) word (SP) ← (SP) - 2, ((SP)) ← (A) Operation - - - - - - - - - - PUSHW AH 1 4 0 (c) word (SP) ← (SP) - 2, ((SP)) ← (AH) - - - - - - - - - - PUSHW PS 1 4 0 (c) word (SP) ← (SP) - 2, ((SP)) ← (PS) - - - - - - - - - - PUSHW rlst 2 *3 *5 *4 (SP) ← (SP) - 2n, ((SP)) ← (rlst) - - - - - - - - - - POPW A 1 3 0 (c) word (A) ← ((SP)), (SP) ← (SP) + 2 - * - - - - - - - - POPW AH 1 3 0 (c) word (AH) ← ((SP)), (SP) ← (SP) + 2 - - - - - - - - - - POPW PS 1 4 0 (c) word (PS) ← ((SP)), (SP) ← (SP) + 2 - - * * * * * * * - POPW rlst 2 *2 *5 *4 (rlst) ← ((SP)), (SP) ← (SP) + 2n - - - - - - - - - - JCTX @A 1 14 0 6 × (c) Context switch instruction - - * * * * * * * - AND CCR,#imm8 2 3 0 0 byte (CCR) ← (CCR) and imm8 - - * * * * * * * - OR CCR,#imm8 2 3 0 0 byte (CCR) ← (CCR) or imm8 - - * * * * * * * - MOV RP,#imm8 2 2 0 0 byte (RP) ← imm8 - - - - - - - - - - MOV ILM,#imm8 2 2 0 0 byte (ILM) ← imm8 - - - - - - - - - - MOVEA RWi,ear 2 3 1 0 word (RWi) ← ear - - - - - - - - - - MOVEA RWi,eam 2+ 2+(a) 1 0 word (RWi) ← eam - - - - - - - - - - MOVEA A,ear 2 1 0 0 word (A) ← ear - * - - - - - - - - MOVEA A,eam 2+ 1+(a) 0 0 word (A) ← eam - * - - - - - - - - ADDSP #imm8 2 3 0 0 word (SP) ← (SP) + ext(imm8) - - - - - - - - - - ADDSP #imm16 3 3 0 0 word (SP) ← (SP) + imm16 - - - - - - - - - - MOV A,brg1 2 *1 0 0 byte (A) ← (brg1) Z * - - - * * - - - MOV brg2,A 2 1 0 0 byte (brg2) ← (A) - - - - - * * - - - NOP 1 1 0 0 No operation - - - - - - - - - - ADB 1 1 0 0 Prefix code for AD space access - - - - - - - - - - DTB 1 1 0 0 Prefix code for DT space access - - - - - - - - - - PCB 1 1 0 0 Prefix code for PC space access - - - - - - - - - - SPB 1 1 0 0 Prefix code for SP space access - - - - - - - - - - NCC 1 1 0 0 Prefix code for flag no-change - - - - - - - - - - CMR 1 1 0 0 Prefix code for common register bank - - - - - - - - - - *1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2 *2: 7 + 3 × (POP count) + 2 × (POP last register number), 7 when RLST = 0 (no transfer register) *3: 29 + 3 × (PUSH count) - 3 × (PUSH last register number), 8 when RLST = 0 (no transfer register) *4: (POP count) × (c) or (PUSH count) × (c) *5: (POP count) or (PUSH count) Note: See Table B.5-1 and Table B.5-2 for information on (a) and (c) in the table. 499 APPENDIX B Instructions Table B.8-16 21 Bit Operand Instructions Mnemonic # ~ RG B LH AH I S T N Z V C RMW MOVB A,dir:bp 3 5 0 (b) byte (A) ← (dir:bp)b Operation Z * - - - * * - - - MOVB A,addr16:bp 4 5 0 (b) byte (A) ← (addr16:bp)b Z * - - - * * - - - MOVB A,io:bp 3 4 0 (b) byte (A) ← (io:bp)b Z * - - - * * - - - MOVB dir:bp,A 3 7 0 2 × (b) bit (dir:bp)b ← (A) - - - - - * * - - * MOVB addr16:bp,A 4 7 0 2 × (b) bit (addr16:bp)b ← (A) - - - - - * * - - * MOVB io:bp,A 3 6 0 2 × (b) bit (io:bp)b ← (A) - - - - - * * - - * SETB dir:bp 3 7 0 2 × (b) bit (dir:bp)b ← 1 - - - - - - - - - * SETB addr16:bp 4 7 0 2 × (b) bit (addr16:bp)b ← 1 - - - - - - - - - * SETB io:bp 3 7 0 2 × (b) bit (io:bp)b ← 1 - - - - - - - - - * CLRB dir:bp 3 7 0 2 × (b) bit (dir:bp)b ← 0 - - - - - - - - - * CLRB addr16:bp 4 7 0 2 × (b) bit (addr16:bp)b ← 0 - - - - - - - - - * CLRB io:bp 3 7 0 2 × (b) bit (io:bp)b ← 0 - - - - - - - - - * BBC dir:bp,rel 4 *1 0 (b) Branch on (dir:bp) b = 0 - - - - - - * - - - BBC addr16:bp,rel 5 *1 0 (b) Branch on (addr16:bp) b = 0 - - - - - - * - - - BBC io:bp,rel 4 *2 0 (b) Branch on (io:bp) b = 0 - - - - - - * - - - BBS dir:bp,rel 4 *1 0 (b) Branch on (dir:bp) b = 1 - - - - - - * - - - BBS addr16:bp,rel 5 *1 0 (b) Branch on (addr16:bp) b = 1 - - - - - - * - - - BBS io:bp,rel 4 *2 0 (b) Branch on (io:bp) b = 1 - - - - - - * - - - SBBS addr16:bp,rel 5 *3 0 2 × (b) Branch on (addr16:bp) b = 1, bit (addr16:bp) b ← 1 - - - - - - * - - * WBTS io:bp 3 *4 0 *5 Waits until (io:bp) b = 1 - - - - - - - - - - WBTC io:bp 3 *4 0 *5 Waits until (io:bp) b = 0 - - - - - - - - - - AH I S T N Z V C RMW *1: 8 when a branch is made; otherwise, 7 *2: 7 when a branch is made; otherwise, 6 *3: 10 when the condition is met; otherwise, 9 *4: Undefined count *5: Until the condition is met Note: See Table B.5-1 and Table B.5-2 for information on (b) in the table. Table B.8-17 6 Accumulator Operation Instructions (Byte, Word) Mnemonic # ~ RG B Operation LH SWAP 1 3 0 0 byte (A)0-7 ↔ (A)8-15 - - - - - - - - - - SWAPW 1 2 0 0 word (AH) ↔ (AL) - * - - - - - - - - EXT 1 1 0 0 Byte sign extension X - - - - * * - - - EXTW 1 2 0 0 Word sign extension - X - - - * * - - - ZEXT 1 1 0 0 Byte zero extension Z - - - - R * - - - ZEXTW 1 1 0 0 Word zero extension - Z - - - R * - - - 500 APPENDIX B Instructions Table B.8-18 10 String Instructions # ~ RG B MOVS / MOVSI Mnemonic 2 *2 *5 *3 byte transfer @AH+ ← @AL+, counter = RW0 Operation LH AH - - I S T N Z V C RMW - - - - - - - - MOVSD 2 *2 *5 *3 byte transfer @AH- ← @AL-, counter = RW0 - - - - - - - - - - SCEQ / SCEQI 2 *1 *8 *4 byte search @AH+ ← AL, counter = RW0 - - - - - * * * * - SCEQD 2 *1 *8 *4 byte search @AH- ← AL, counter = RW0 - - - - - * * * * FILS / FILSI 2 6m+6 *8 *3 byte fill @AH+ ← AL, counter = RW0 - - - - - * * - - - MOVSW / MOVSWI 2 *2 *5 *6 word transfer @AH+ ← @AL+, counter = RW0 - - - - - - - - - - MOVSWD 2 *2 *5 *6 word transfer @AH- ← @AL-, counter = RW0 - - - - - - - - - - SCWEQ / SCWEQI 2 *1 *8 *7 word search @AH+ - AL, counter = RW0 - - - - - * * * * - SCWEQD 2 *1 *8 *7 word search @AH- - AL, counter = RW0 - - - - - * * * * - FILSW / FILSWI 2 6m+6 *8 *6 word fill @AH+ ← AL, counter = RW0 - - - - - * * - - - *1: 5 when RW0 is 0, 4 + 7 × (RW0) when the counter expires, or 7n + 5 when a match occurs *2: 5 when RW0 is 0; otherwise, 4 + 8 × (RW0) *3: (b) × (RW0) + (b) × (RW0) When the source and destination access different areas, calculate the (b) item individually. *4: (b) × n *5: 2 × (b) × (RW0) *6: (c) × (RW0) + (c) × (RW0) When the source and destination access different areas, calculate the (c) item individually. *7: (c) × n *8: (b) × (RW0) Note: m: RW0 value (counter value), n: Loop count See Table B.5-1 and Table B.5-2 for information on (b) and (c) in the table. 501 APPENDIX B Instructions B.9 Instruction Map Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F2MC-16LX instruction map. ■ Structure of Instruction Map Figure B.9-1 Structure of Instruction Map Basic page map Bit operation instructions Character string operation instructions 2-byte instructions : Byte 1 ea instructions × 9 : Byte 2 An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it references byte 1, and can check the following one byte by referencing the map for byte 2. Figure B.9-2 shows the correspondence between an actual instruction code and instruction map. 502 APPENDIX B Instructions Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map Some instructions do not contain byte 2. Instruction code Length varies depending on the instruction. Byte 1 Byte 2 Operand Operand ... [Basic page map] XY +Z [Extended page map]* UV +W *: The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte instructions, and ea instructions. Actually, there are multiple extended page maps for each type of instructions. An example of an instruction code is shown in Table B.9-1. Table B.9-1 Example of an Instruction Code Byte 1 (from basic page map) Byte 2 (from extended page map) NOP 00 +0=00 - AND A, #8 30 +4=34 - MOV A, ADB 60 +F=6F 00 +0=00 @RW2+d8, #8, rel 70 +0=70 F0 +2=F2 Instruction 503 504 +F +E +D +C +B +A +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 A ZEXT SWAP ADDSP DTB ADB SPB #8 A, #8 dir, A A, dir io, A A, io JMP BRA 60 MULU DIVU ea @A instruction 2 A MOVW MOVX RET SP, A A, addr16 A0 B0 C0 ea instruction 8 D0 E0 rel rel LSRW ASRW LSLW SWAPW ZEXTW XORW ORW ANDW A A MOVW RWi, ea PUSHW POPW 2-byte XCHW A rlst rlst instruction RWi, ea Character XORW PUSHW POPW XCH operation A, #16 PS PS string Ri, ea instruction MOVW ea, RWi Bit operation MOV A instruction ea, Ri ORW PUSHW POPW A, #16 AH AH ANDW PUSHW POPW A A, #16 A CMPW MOVL MOVW RETI A, #16 A, #32 addr16, A ADDSP MULUW NOTW A #16 A A A EXTW A BHI BLS BGT BLE rel rel rel rel rel BGE CMPL CMPW A, #32 NEGW A rel rel rel rel rel rel BLT BT BNV BV BP BN BNC/BHS rel BC/BLO BNZ/BNE rel BZ/BEQ MOV MOV CBNE A, CWBNE A, MOVW MOVW INTP MOV RP, #8 ILM, #8 #8, rel #16, rel A, #16 A,addr16 addr24 Ri, ea #4 F0 rel ADDW MOVW MOVW INT ea MOVW MOVW MOVW MOV A, MOVW A, #16 A, dir A, io #vct8 instruction 9 A, RWi RWi, A RWi, #16 @RWi+d8 @RWi+d8, A NOT ea instruction 7 MOVX MOVX CALLP ea A, dir A, io addr24 instruction 6 MOVW MOVW RETP A, #8 A, SP io, #16 A, #8 90 BNT SUBL SUBW A, #32 A A A XOR OR OR CCR, #8 80 ea MOV MOV MOV MOV MOVX A, MOV CALL rel instruction 1 A, Ri Ri, A Ri, #8 A, Ri @RWi+d8 A, #4 70 MOV JMP ea A, addr16 addr16 instruction 3 MOV MOV 50 MOVX MOV JMPP ea A, #8 A, #8 addr16, A addr24 instruction 4 MOV MOV MOV 40 SUBW MOVW MOVW INT MOVEA A A, #16 dir, A io, A addr16 RWi, ea UNLINK A CMP A A, #8 A, #8 SUBC SUB ADD 30 AND AND MOV MOV CALL ea CCR, #8 A, #8 dir, #8 io, #8 addr16 instruction 5 CMP A A, dir A, dir ADDC SUB ADD 20 LINK ADDL ADDW #imm8 A, #32 EXT @A PCB A JCTX SUBDC ADDDC NEG NCC INT9 A CMR 10 NOP 00 APPENDIX B Instructions Table B.9-2 Basic Page Map +F +E +D +C +B +A +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 10 MOVB io:bp, A 20 30 CLRB io:bp 40 50 SETB io:bp 60 70 BBC io;bp, rel 80 90 BBS io:bp, rel A0 B0 MOVB MOVB A, MOVB MOVB CLRB CLRB SETB SETB BBC BBC BBS BBS A, dir:bp addr16:bp dir:bp, A addr16:bp,A dir:bp addr16:bp dir:bp addr16:bp dir:bp, rel addr16:bp,rel dir:bp, rel addr16:bp,rel MOVB A, io:bp 00 WBTS io:bp C0 D0 WBTC io:bp E0 SBBS addr16:bp F0 APPENDIX B Instructions Table B.9-3 Bit Operation Instruction Map (First Byte = 6CH) 505 506 MOVSI MOVSD PCB, PCB PCB, DTB PCB, ADB PCB, SPB DTB, PCB DTB, DTB DTB, ADB DTB, SPB ADB, PCB ADB, DTB ADB, ADB ADB, SPB SPB, PCB SPB, DTB SPB, ADB SPB, SPB +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F 10 +0 00 MOVSWI 20 MOVSWD 30 40 50 60 70 90 A0 B0 C0 SPB ADB DTB SPB ADB DTB SPB ADB DTB SPB ADB DTB SPB ADB DTB SCEQI SCEQD SCWEQI SCWEQD FILSI PCB PCB PCB PCB PCB 80 D0 FILSI SPB ADB DTB PCB E0 F0 APPENDIX B Instructions Table B.9-4 Character String Operation Instruction Map (First Byte = 6EH) LSLW LSLL LSL MOVW MOVW A, R0 A, R0 A, R0 @RL2+d8, A A, @RL2+d8 MOVW MOVW NRML A, @A @AL, AH A, R0 ASRW ASRL ASR MOVW MOVW A, R0 A, R0 A, R0 @RL3+d8, A A, @RL3+d8 LSRW LSRL LSR A, R0 A, R0 A, R0 +D +E +F MOVW MOVW @RL1+d8, A A, @RL1+d8 MOVW MOVW @RL0+d8, A A, @RL0+d8 +C +B +A +9 +8 A MOV MOV MOVX MOV MOV A, PCB A, @A A, @RL3+d8 @RL3+d8, A A, @RL3+d8 +6 ROLC MOV MOV A, @A @AL, AH +5 A MOV MOV MOVX MOV MOV A, DPR DPR, A A, @RL2+d8 @RL2+d8, A A, @RL2+d8 +4 ROLC MOV MOV A, USB USB, A +3 +7 MOV MOV MOVX MOV MOV A, SSB SSB, A A, @RL1+d8 @RL1+d8, A A, @RL1+d8 +2 40 MOV MOV A, ADB ADB, A 30 +1 20 MOV MOV MOVX MOV MOV A, DTB DTB, A A, @RL0+d8 @RL0+d8, A A, @RL0+d8 10 +0 00 50 DIVU MULW MUL 60 A A A 70 80 90 A0 B0 C0 D0 E0 F0 APPENDIX B Instructions Table B.9-5 2-byte Instruction Map (First Byte = 6FH) 507 508 50 90 B0 D0 @RW1, @RW1+d16 CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, #16, rel #16, rel A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW2, @RW2+d16 CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, #16, rel #16, rel A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW3, @RW3+d16 CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, #16, rel #16, rel A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 SUBL SUBL A, A, RL2 @RW5+d8 SUBL SUBL A, A, RL3 @RW6+d8 SUBL SUBL A, A, RL3 @RW7+d8 ADDL ADDL A, A, RL2 @RW5+d8 ADDL ADDL A, A, RL3 @RW6+d8 ADDL ADDL A, A, RL3 @RW7+d8 ADDL ADDL A, SUBL SUBL A, A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 ADDL ADDL A, SUBL SUBL A, A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 ADDL ADDL A, SUBL SUBL A, A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 ADDL ADDL A, SUBL SUBL A, A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 ADDL ADDL A, SUBL SUBL A, Use @RW0+RW7 CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, Use @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited #16, rel A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited ,#8, rel ADDL ADDL A, SUBL SUBL A, Use @RW1+RW7 CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, Use @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited #16, rel A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited ,#8, rel ADDL ADDL A, A,@RW2+ @PC+d16 ADDL ADDL A, SUBL SUBL A, Use A,@RW3+ addr16 A,@RW3+ addr16 prohibited +5 +6 +7 +8 +9 +A +B +C +D +E +F SUBL SUBL A, A,@RW2+ @PC+d16 @RW0, @RW0+d16 CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, #16, rel #16, rel A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 SUBL SUBL A, A, RL2 @RW4+d8 Use prohibited ANDL ANDL A, A,@RW2+ @PC+d16 ANDL ANDL A, A, RL3 @RW7+d8 ANDL ANDL A, A, RL3 @RW6+d8 ANDL ANDL A, A, RL2 @RW5+d8 ANDL ANDL A, A, RL2 @RW4+d8 ORL ORL A, A,@RW2+ @PC+d16 ORL ORL A, A, RL3 @RW7+d8 ORL ORL A, A, RL3 @RW6+d8 ORL ORL A, A, RL2 @RW5+d8 ORL ORL A, A, RL2 @RW4+d8 XORL XORL A, A,@RW2+ @PC+d16 XORL XORL A, A, RL3 @RW7+d8 XORL XORL A, A, RL3 @RW6+d8 XORL XORL A, A, RL2 @RW5+d8 XORL XORL A, A, RL2 @RW4+d8 XORL XORL A, A, RL1 @RW3+d8 addr16, ,#8, rel Use @PC+d16, prohibited ,#8, rel @RW3, @RW3+d16 #8, rel ,#8, rel @RW2, @RW2+d16 #8, rel ,#8, rel @RW1, @RW1+d16 #8, rel ,#8, rel @RW0, @RW0+d16 #8, rel ,#8, rel R7, @RW7+d8, #8, rel #8, rel R6, @RW6+d8, #8, rel #8, rel R5, @RW5+d8, #8, rel #8, rel R4, @RW4+d8, #8, rel #8, rel R3, @RW3+d8, #8, rel #8, rel addr16, CMPL CMPL A, ANDL ANDL A, ORL ORL A, XORL XORL A, Use #16, rel A,@RW3+ addr16 A,@RW3+ addr16 A,@RW3+ addr16 A,@RW3+ addr16 prohibited @PC+d16, CMPL CMPL A, #16, rel A,@RW2+ @PC+d16 RW7, @RW7+d8 CMPL CMPL A, #16, rel #16, rel A, RL3 @RW7+d8 RW6, @RW6+d8 CMPL CMPL A, #16, rel #16, rel A, RL3 @RW6+d8 RW5, @RW5+d8 CMPL CMPL A, #16, rel #16, rel A, RL2 @RW5+d8 RW4, @RW4+d8 CMPL CMPL A, #16, rel #16, rel A, RL2 @RW4+d8 ORL ORL A, A, RL1 @RW3+d8 R2, @RW2+d8, #8, rel #8, rel R1, @RW1+d8, #8, rel #8, rel ADDL ADDL A, A, RL2 @RW4+d8 ANDL ANDL A, A, RL1 @RW3+d8 XORL XORL A, A, RL1 @RW2+d8 XORL XORL A, A, RL0 @RW1+d8 +4 RW3, @RW3+d8 CMPL CMPL A, #16, rel #16, rel A, RL1 @RW3+d8 ORL ORL A, A, RL1 @RW2+d8 ORL ORL A, A, RL0 @RW1+d8 SUBL SUBL A, A, RL1 @RW3+d8 ANDL ANDL A, A, RL1 @RW2+d8 ANDL ANDL A, A, RL0 @RW1+d8 ADDL ADDL A, A, RL1 @RW3+d8 RW2, @RW2+d8 CMPL CMPL A, #16, rel #16, rel A, RL1 @RW2+d8 RW1, @RW1+d8 CMPL CMPL A, #16, rel #16, rel A, RL0 @RW1+d8 +3 CBNE ↓ F0 R0, @RW0+d8, #8, rel #8, rel CBNE ↓ E0 SUBL SUBL A, A, RL1 @RW2+d8 XORL XORL A, A, RL0 @RW0+d8 C0 ADDL ADDL A, A, RL1 @RW2+d8 ORL ORL A, A, RL0 @RW0+d8 A0 +2 ANDL ANDL A, A, RL0 @RW0+d8 80 SUBL SUBL A, A, RL0 @RW1+d8 70 ADDL ADDL A, A, RL0 @RW1+d8 60 RW0, @RW0+d8 CMPL CMPL A, #16, rel #16, rel A, RL0 @RW0+d8 CWBNE ↓ CWBNE ↓ 40 +1 30 +0 20 SUBL SUBL A, A, RL0 @RW0+d8 10 ADDL ADDL A, A, RL0 @RW0+d8 00 APPENDIX B Instructions Table B.9-6 ea Instruction 1 (First Byte = 70H) JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL3 @@RW7+d8 @RL3 @@RW7+d8 RL3 @RW7+d8 RL3 @RW7+d8 A, RL3 @RW7+d8 RL3, A @RW7+d8,A R7, #8 @RW7+d8,#8 A, RW7 @RW7+d8 JMPP JMPP @ CALLP CALLP @ INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW0 @RW0+d16 @@RW0 @RW0+d16 @RW0 @RW0+d16 @RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #8 @RW0+d16,#8 A,@RW0 @RW0+d16 JMPP JMPP @ CALLP CALLP @ INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW1 @RW1+d16 @@RW1 @RW1+d16 @RW1 @RW1+d16 @RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1,A @RW1+d16,A @RW1, #8 @RW1+d16,#8 A,@RW1 @RW1+d16 JMPP JMPP @ CALLP CALLP @ INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW2 @RW2+d16 @@RW2 @RW2+d16 @RW2 @RW2+d16 @RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2,A @RW2+d16,A @RW2, #8 @RW2+d16,#8 A,@RW2 @RW2+d16 JMPP JMPP @ CALLP CALLP @ INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW3 @RW3+d16 @@RW3 @RW3+d16 @RW3 @RW3+d16 @RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3,A @RW3+d16,A @RW3, #8 @RW3+d16,#8 A,@RW3 @RW3+d16 JMPP JMPP @ CALLP CALLP @ INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+,A @RW0+RW7,A @RW0+, #8 @RW0+RW7,#8 A,@RW0+ @RW0+RW7 JMPP JMPP @ CALLP CALLP @ INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+,A @RW1+RW7,A @RW1+, #8 @RW1+RW7,#8 A,@RW1+ @RW1+RW7 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW2+ @@PC+d16 @@RW2+ @@PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+,A @PC+d16, A @RW2+, #8 @PC+d16, #8 A,@RW2+ @PC+d16 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @@RW3+ @addr16 @@RW3+ @addr16 @RW3+ addr16 @RW3+ addr16 A,@RW3+ addr16 @RW3+,A addr16, A @RW3+, #8 addr16, #8 A,@RW3+ addr16 +8 +9 +A +B +C +D +E +F F0 +7 E0 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL3 @@RW6+d8 @RL3 @@RW6+d8 RL3 @RW6+d8 RL3 @RW6+d8 A, RL3 @RW6+d8 RL3, A @RW6+d8,A R6, #8 @RW6+d8,#8 A, RW6 @RW6+d8 D0 +6 C0 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL2 @@RW5+d8 @RL2 @@RW5+d8 RL2 @RW5+d8 RL2 @RW5+d8 A, RL2 @RW5+d8 RL2, A @RW5+d8,A R5, #8 @RW5+d8,#8 A, RW5 @RW5+d8 B0 +5 A0 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL2 @@RW4+d8 @RL2 @@RW4+d8 RL2 @RW4+d8 RL2 @RW4+d8 A, RL2 @RW4+d8 RL2, A @RW4+d8,A R4, #8 @RW4+d8,#8 A, RW4 @RW4+d8 90 +4 80 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL1 @@RW3+d8 @RL1 @@RW3+d8 RL1 @RW3+d8 RL1 @RW3+d8 A, RL1 @RW3+d8 RL1, A @RW3+d8,A R3, #8 @RW3+d8,#8 A, RW3 @RW3+d8 70 +3 60 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL1 @@RW2+d8 @RL1 @@RW2+d8 RL1 @RW2+d8 RL1 @RW2+d8 A, RL1 @RW2+d8 RL1, A @RW2+d8,A R2, #8 @RW2+d8,#8 A, RW2 @RW2+d8 50 +2 40 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL0 @@RW1+d8 @RL0 @@RW1+d8 RL0 @RW1+d8 RL0 @RW1+d8 A, RL0 @RW1+d8 RL0, A @RW1+d8,A R1, #8 @RW1+d8,#8 A, RW1 @RW1+d8 30 +1 20 JMPP JMPP CALLP CALLP INCL INCL DECL DECL MOVL MOVL A, MOVL MOVL MOV MOV MOVEA MOVEA A, @RL0 @@RW0+d8 @RL0 @@RW0+d8 RL0 @RW0+d8 RL0 @RW0+d8 A, RL0 @RW0+d8 RL0, A @RW0+d8,A R0, #8 @RW0+d8,#8 A, RW0 @RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-7 ea Instruction 2 (First Byte = 71H) 509 510 D0 E0 F0 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 A,@RW3+ addr16 @RW3+, A addr16, A A,@RW3+ addr16 A,@RW3+ addr16 +D +E +F DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R7 @RW7+d8 A, R7 @RW7+d8 R7, A @RW7+d8,A A, R7 @RW7+d8 A, R7 @RW7+d8 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R6 @RW6+d8 A, R6 @RW6+d8 R6, A @RW6+d8,A A, R6 @RW6+d8 A, R6 @RW6+d8 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R5 @RW5+d8 A, R5 @RW5+d8 R5, A @RW5+d8,A A, R5 @RW5+d8 A, R5 @RW5+d8 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R4 @RW4+d8 A, R4 @RW4+d8 R4, A @RW4+d8,A A, R4 @RW4+d8 A, R4 @RW4+d8 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R3 @RW3+d8 A, R3 @RW3+d8 R3, A @RW3+d8,A A, R3 @RW3+d8 A, R3 @RW3+d8 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R2 @RW2+d8 A, R2 @RW2+d8 R2, A @RW2+d8,A A, R2 @RW2+d8 A, R2 @RW2+d8 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R1 @RW1+d8 A, R1 @RW1+d8 R1, A @RW1+d8,A A, R1 @RW1+d8 A, R1 @RW1+d8 +C INC DEC R7 @RW7+d8 C0 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW3 @RW3+d16 @RW3 @RW3+d16 @RW3 @RW3+d16 @RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 ROLC RORC RORC INC R7 @RW7+d8 R7 @RW7+d8 ROLC INC DEC R6 @RW6+d8 B0 +B ROLC RORC RORC INC R6 @RW6+d8 R6 @RW6+d8 ROLC INC DEC R5 @RW5+d8 A0 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW2 @RW2+d16 @RW2 @RW2+d16 @RW2 @RW2+d16 @RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 ROLC RORC RORC INC R5 @RW5+d8 R5 @RW5+d8 ROLC INC DEC R4 @RW4+d8 90 +A ROLC RORC RORC INC R4 @RW4+d8 R4 @RW4+d8 ROLC INC DEC R3 @RW3+d8 INC DEC R2 @RW2+d8 INC DEC R1 @RW1+d8 80 DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, R0 @RW0+d8 A, R0 @RW0+d8 R0, A @RW0+d8,A A, R0 @RW0+d8 A, R0 @RW0+d8 70 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW1 @RW1+d16 @RW1 @RW1+d16 @RW1 @RW1+d16 @RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 ROLC RORC RORC INC R3 @RW3+d8 R3 @RW3+d8 ROLC 60 INC DEC R0 @RW0+d8 50 +9 ROLC RORC RORC INC R2 @RW2+d8 R2 @RW2+d8 ROLC 40 ROLC ROLC RORC RORC INC INC DEC DEC MOV MOV A, MOV MOV MOVX MOVX A, XCH XCH A, @RW0 @RW0+d16 @RW0 @RW0+d16 @RW0 @RW0+d16 @RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0, A @RW0+d16,A A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 ROLC RORC RORC INC R1 @RW1+d8 R1 @RW1+d8 ROLC 30 ROLC RORC RORC INC R0 @RW0+d8 R0 @RW0+d8 20 ROLC 10 +8 +7 +6 +5 +4 +3 +2 +1 +0 00 APPENDIX B Instructions Table B.9-8 ea Instruction 3 (First Byte = 72H) CALL CALL RW5 @@RW5+d8 CALL CALL RW6 @@RW6+d8 CALL CALL RW7 @@RW7+d8 JMP JMP @RW5 @@RW5+d8 JMP JMP @RW6 @@RW6+d8 JMP JMP @RW7 @@RW7+d8 JMP JMP @ CALL CALL @ INCW INCW @ DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW0 @RW0+d16 @@RW0 @RW0+d16 @RW0 @RW0+d16 @RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #16 @RW0+d16,#16 A,@RW0 @RW0+d16 JMP JMP @ CALL CALL @ INCW INCW @ DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW1 @RW1+d16 @@RW1 @RW1+d16 @RW1 @RW1+d16 @RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, #16 @RW1+d16,#16 A,@RW1 @RW1+d16 JMP JMP @ CALL CALL @ INCW INCW @ DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW2 @RW2+d16 @@RW2 @RW2+d16 @RW2 @RW2+d16 @RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, #16 @RW2+d16,#16 A,@RW2 @RW2+d16 JMP JMP @ CALL CALL @ INCW INCW @ DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW3 @RW3+d16 @@RW3 @RW3+d16 @RW3 @RW3+d16 @RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, #16 @RW3+d16,#16 A,@RW3 @RW3+d16 JMP JMP @ CALL CALL @ INCW INCW @ DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, #16 @RW0+RW7,#16 A,@RW0+ @RW0+RW7 JMP JMP @ CALL CALL @ INCW INCW @ DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, #16 @RW1+RW7,#16 A,@RW1+ @RW1+RW7 JMP JMP CALL CALL INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW2+ @@PC+d16 @@RW2+ @@PC+d16 @RW2+ @@PC+d16 @RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A @RW2+, #16 @PC+d16, #16 A,@RW2+ @PC+d16 JMP JMP CALL CALL INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW MOVW MOVW XCHW XCHW A, @@RW3+ @addr16 @@RW3+ @addr16 @RW3+ addr16 @RW3+ addr16 A,@RW3+ addr16 @RW3+, A addr16, A @RW3+, #16 addr16, #16 A,@RW3+ addr16 +5 +6 +7 +8 +9 +A +B +C +D +E +F INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW7 @RW7+d8 RW7 @RW7+d8 A, RW7 @RW7+d8 RW7, A @RW7+d8,A INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW6 @RW6+d8 RW6 @RW6+d8 A, RW6 @RW6+d8 RW6, A @RW6+d8,A INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW5 @RW5+d8 RW5 @RW5+d8 A, RW5 @RW5+d8 RW5, A @RW5+d8,A INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW4 @RW4+d8 RW4 @RW4+d8 A, RW4 @RW4+d8 RW4, A @RW4+d8,A MOVW MOVW RW7, #16 @RW7+d8,#16 MOVW MOVW RW6, #16 @RW6+d8,#16 MOVW MOVW RW5, #16 @RW5+d8,#16 MOVW MOVW RW4, #16 @RW4+d8,#16 XCHW XCHW A, A, RW7 @RW7+d8 XCHW XCHW A, A, RW6 @RW6+d8 XCHW XCHW A, A, RW5 @RW5+d8 XCHW XCHW A, A, RW4 @RW4+d8 XCHW XCHW A, A, RW3 @RW3+d8 XCHW XCHW A, A, RW2 @RW2+d8 XCHW XCHW A, A, RW1 @RW1+d8 CALL CALL RW4 @@RW4+d8 MOVW MOVW RW3, #16 @RW3+d8,#16 MOVW MOVW RW2, #16 @RW2+d8,#16 MOVW MOVW RW1, #16 @RW1+d8,#16 JMP JMP @RW4 @@RW4+d8 INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW3 @RW3+d8 RW3 @RW3+d8 A, RW3 @RW3+d8 RW3, A @RW3+d8,A INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW2 @RW2+d8 RW2 @RW2+d8 A, RW2 @RW2+d8 RW2, A @RW2+d8,A INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW1 @RW1+d8 RW1 @RW1+d8 A, RW1 @RW1+d8 RW1, A @RW1+d8,A +4 F0 XCHW XCHW A, A, RW0 @RW0+d8 E0 CALL CALL RW3 @@RW3+d8 D0 MOVW MOVW RW0, #16 @RW0+d8,#16 C0 JMP JMP @RW3 @@RW3+d8 B0 +3 A0 CALL CALL RW2 @@RW2+d8 90 JMP JMP @RW2 @@RW2+d8 80 +2 70 CALL CALL RW1 @@RW1+d8 60 JMP JMP @RW1 @@RW1+d8 50 INCW INCW DECW DECW MOVW MOVW A, MOVW MOVW RW0 @RW0+d8 RW0 @RW0+d8 A, RW0 @RW0+d8 RW0, A @RW0+d8,A 40 +1 30 CALL CALL RW0 @@RW0+d8 20 JMP JMP @RW0 @@RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-9 ea Instruction 4 (First Byte = 73H) 511 512 ADD A, SUB SUB SUB ADDC A, ADDC A, ADDC ADDC A, A, CMP CMP CMP CMP A, A, A, AND AND AND AND AND AND A, A, A, OR OR A, XOR XOR A, DBNZ DBNZ @ A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r PC+d16, r +F A,@RW3+ ADD ADD SUB SUB ADDC ADDC CMP CMP AND AND OR OR XOR XOR DBNZ DBNZ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 @RW3+, r addr16, r +E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 ADD SUB CMP XOR XOR A, DBNZ DBNZ @R A,@RW1+ @RW1+RW7 @RW1+, r W1+RW7, r A, CMP OR OR A, A,@RW1+ @RW1+RW7 ADD ADD ADDC A, +D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 ADDC XOR XOR A, DBNZ DBNZ @R A,@RW0+ @RW0+RW7 @RW0+, r W0+RW7, r A, OR OR A, A,@RW0+ @RW0+RW7 SUB +C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 SUB XOR XOR A, DBNZ DBNZ @R A,@RW3 @RW3+d16 @RW3, r W3+d16, r ADD ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 +B A, XOR XOR A, DBNZ DBNZ @R A,@RW2 @RW2+d16 @RW2, r W2+d16, r ADD ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 +A ADD XOR XOR A, DBNZ DBNZ @R A,@RW1 @RW1+d16 @RW1, r W1+d16, r ADD ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 +9 ADD XOR XOR A, DBNZ DBNZ @R A,@RW0 @RW0+d16 @RW0, r W0+d16, r ADD ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R7 @RW7+d8 A, R7 @RW7+d8 A, R7 @RW7+d8 A, R7 @RW7+d8 A, R7 @RW7+d8 A, R7 @RW7+d8 A, R7 @RW7+d8 R7, r RW7+d8, r ADD F0 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R6 @RW6+d8 A, R6 @RW6+d8 A, R6 @RW6+d8 A, R6 @RW6+d8 A, R6 @RW6+d8 A, R6 @RW6+d8 A, R6 @RW6+d8 R6, r RW6+d8, r E0 ADD D0 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R5 @RW5+d8 A, R5 @RW5+d8 A, R5 @RW5+d8 A, R5 @RW5+d8 A, R5 @RW5+d8 A, R5 @RW5+d8 A, R5 @RW5+d8 R5, r RW5+d8, r C0 ADD B0 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R4 @RW4+d8 A, R4 @RW4+d8 A, R4 @RW4+d8 A, R4 @RW4+d8 A, R4 @RW4+d8 A, R4 @RW4+d8 A, R4 @RW4+d8 R4, r RW4+d8, r A0 ADD 90 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R3 @RW3+d8 A, R3 @RW3+d8 A, R3 @RW3+d8 A, R3 @RW3+d8 A, R3 @RW3+d8 A, R3 @RW3+d8 A, R3 @RW3+d8 R3, r RW3+d8, r 80 ADD 70 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R2 @RW2+d8 A, R2 @RW2+d8 A, R2 @RW2+d8 A, R2 @RW2+d8 A, R2 @RW2+d8 A, R2 @RW2+d8 A, R2 @RW2+d8 R2, r RW2+d8, r 60 ADD 50 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R1 @RW1+d8 A, R1 @RW1+d8 A, R1 @RW1+d8 A, R1 @RW1+d8 A, R1 @RW1+d8 A, R1 @RW1+d8 A, R1 @RW1+d8 R1, r RW1+d8, r 40 ADD 30 ADD A, SUB SUB A, ADDC ADDC A, CMP CMP A, AND AND A, OR OR A, XOR XOR A, DBNZ DBNZ @ A, R0 @RW0+d8 A, R0 @RW0+d8 A, R0 @RW0+d8 A, R0 @RW0+d8 A, R0 @RW0+d8 A, R0 @RW0+d8 A, R0 @RW0+d8 R0, r RW0+d8, r 20 ADD 10 +8 +7 +6 +5 +4 +3 +2 +1 +0 00 APPENDIX B Instructions Table B.9-10 ea Instruction 5 (First Byte = 74H) NOT NOT R2 @RW2+d8 SUB SUB SUB SUB SUB SUB @RW2+, A @PC+d16,A SUB SUB @RW3+, A addr16, A ADD ADD @RW2+, A @PC+d16,A ADD ADD @RW3+, A addr16, A +F @RW1+RW7,A @RW1+, A @RW1+RW7,A ADD @R @RW0+RW7,A @RW0+, A @RW0+RW7,A ADD @R +E +D @RW1+, A ADD +C @RW0+, A ADD NOT NOT @RW1+ @RW1+RW7 NOT NOT @RW0+ @RW0+RW7 SUBC SUBC A, NEG NEG A, AND AND A,@RW3+ addr16 @RW3+ addr16 @RW3+, A addr16, A OR OR @RW3+, A addr16, A XOR XOR @RW3+, A addr16, A NOT NOT @RW3+ addr16 SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR NOT NOT A,@RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+ @PC+d16 SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A NOT NOT @RW3 @RW3+d16 ADD ADD @R SUB SUB SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16 @RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A +B XOR NOT NOT R7, A @RW7+d8, A R7 @RW7+d8 XOR NOT NOT R6, A @RW6+d8, A R6 @RW6+d8 XOR NOT NOT R5, A @RW5+d8, A R5 @RW5+d8 XOR NOT NOT R4, A @RW4+d8, A R4 @RW4+d8 XOR NOT NOT R3, A @RW3+d8, A R3 @RW3+d8 XOR R2, A @RW2+d8,A XOR NOT NOT R1, A @RW1+d8, A R1 @RW1+d8 NOT NOT @RW2 @RW2+d16 XOR F0 ADD ADD @R SUB SUB SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16 @RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A NEG A, AND AND OR OR R7 @RW7+d8 R7, A @RW7+d8, A R7, A @RW7+d8, A XOR XOR XOR XOR XOR XOR E0 XOR NOT NOT R0, A @RW0+d8, A R0 @RW0+d8 D0 +A ADD SUB SUB SUBC SUBC A, NEG R7, A @RW7+d8, A R7, A @RW7+d8, A A, R7 @RW7+d8 ADD NEG A, AND AND OR OR R6 @RW6+d8 R6, A @RW6+d8, A R6, A @RW6+d8, A NEG A, AND AND OR OR R5 @RW5+d8 R5, A @RW5+d8, A R5, A @RW5+d8, A NEG A, AND AND OR OR R4 @RW4+d8 R4, A @RW4+d8, A R4, A @RW4+d8, A NEG A, AND AND OR OR R3 @RW3+d8 R3, A @RW3+d8, A R3, A @RW3+d8, A NEG A, AND AND OR OR R2 @RW2+d8 R2, A @RW2+d8,A R2, A @RW2+d8,A NEG A, AND AND OR OR R1 @RW1+d8 R1, A @RW1+d8, A R1, A @RW1+d8, A XOR C0 NOT NOT @RW1 @RW1+d16 ADD SUB SUB SUBC SUBC A, NEG R6, A @RW6+d8, A R6, A @RW6+d8, A A, R6 @RW6+d8 ADD B0 ADD ADD @R SUB SUB SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16 @RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A ADD SUB SUB SUBC SUBC A, NEG R5, A @RW5+d8, A R5, A @RW5+d8, A A, R5 @RW5+d8 ADD A0 +9 ADD SUB SUB SUBC SUBC A, NEG R4, A @RW4+d8, A R4, A @RW4+d8, A A, R4 @RW4+d8 ADD 90 NOT NOT @RW0 @RW0+d16 ADD SUB SUB SUBC SUBC A, NEG R3, A @RW3+d8, A R3, A @RW3+d8, A A, R3 @RW3+d8 ADD 80 NEG A, AND AND OR OR R0 @RW0+d8 R0, A @RW0+d8, A R0, A @RW0+d8, A 70 ADD ADD SUB SUB SUBC SUBC A, NEG NEG A, AND AND OR OR XOR XOR @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16 @RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A ADD SUB SUB SUBC SUBC A, NEG R2, A @RW2+d8,A R2, A @RW2+d8,A A, R2 @RW2+d8 60 ADD 50 ADD SUB SUB SUBC SUBC A, NEG R1, A @RW1+d8, A R1, A @RW1+d8, A A, R1 @RW1+d8 40 ADD 30 ADD SUB SUB SUBC SUBC A, NEG R0, A @RW0+d8, A R0, A @RW0+d8, A A, R0 @RW0+d8 20 ADD 10 +8 +7 +6 +5 +4 +3 +2 +1 +0 00 APPENDIX B Instructions Table B.9-11 ea Instruction 6 (First Byte = 75H) 513 514 ADDW A, SUBW ADDW ADDCW CMPW ADDCW A, CMPW ADDCW A, ANDW CMPW A, ANDW CMPW A, ORW ORW ANDW A, ORW ANDW A, ANDW A, ORW ORW ORW A, A, A, XORW XORW A, DWBNZ DWBNZ +F A,@RW3+ ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ addr 16 A,@RW3+ addr 16 A,@RW3+ addr 16 A,@RW3+ addr 16 A,@RW3+ addr 16 A,@RW3+ addr16 A,@RW3+ addr 16 @RW3+, r addr16, r +E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r @PC+d16,r SUBW A, ADDCW SUBW A, ANDW XORW XORW A, DWBNZ DWBNZ A,@RW1+ @RW1+RW7 @RW1+, r @RW1+RW7,r SUBW ADDW A, ADDW CMPW A, +D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 CMPW XORW XORW A, DWBNZ DWBNZ A,@RW0+ @RW0+RW7 @RW0+, r @RW0+RW7,r ADDCW A, +C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 ADDCW XORW XORW A, DWBNZ DWBNZ A,@RW3 @RW3+d16 @RW3, r @RW3+d16,r ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 +B SUBW A, XORW XORW A, DWBNZ DWBNZ A,@RW2 @RW2+d16 @RW2, r @RW2+d16,r ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 +A SUBW XORW XORW A, DWBNZ DWBNZ A,@RW1 @RW1+d16 @RW1, r @RW1+d16,r ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 +9 ADDW A, XORW XORW A, DWBNZ DWBNZ A,@RW0 @RW0+d16 @RW0, r @RW0+d16,r ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 +8 ADDW ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW7 @RW7+d8 A, RW7 @RW7+d8 A, RW7 @RW7+d8 A, RW7 @RW7+d8 A, RW7 @RW7+d8 A, RW7 @RW7+d8 A, RW7 @RW7+d8 RW7, r @RW7+d8,r F0 +7 E0 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW6 @RW6+d8 A, RW6 @RW6+d8 A, RW6 @RW6+d8 A, RW6 @RW6+d8 A, RW6 @RW6+d8 A, RW6 @RW6+d8 A, RW6 @RW6+d8 RW6, r @RW6+d8,r D0 +6 C0 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW5 @RW5+d8 A, RW5 @RW5+d8 A, RW5 @RW5+d8 A, RW5 @RW5+d8 A, RW5 @RW5+d8 A, RW5 @RW5+d8 A, RW5 @RW5+d8 RW5, r @RW5+d8,r B0 +5 A0 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW4 @RW4+d8 A, RW4 @RW4+d8 A, RW4 @RW4+d8 A, RW4 @RW4+d8 A, RW4 @RW4+d8 A, RW4 @RW4+d8 A, RW4 @RW4+d8 RW4, r @RW4+d8,r 90 +4 80 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW3 @RW3+d8 A, RW3 @RW3+d8 A, RW3 @RW3+d8 A, RW3 @RW3+d8 A, RW3 @RW3+d8 A, RW3 @RW3+d8 A, RW3 @RW3+d8 RW3, r @RW3+d8,r 70 +3 60 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW2 @RW2+d8 A, RW2 @RW2+d8 A, RW2 @RW2+d8 A, RW2 @RW2+d8 A, RW2 @RW2+d8 A, RW2 @RW2+d8 A, RW2 @RW2+d8 RW2, r @RW2+d8,r 50 +2 40 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW1 @RW1+d8 A, RW1 @RW1+d8 A, RW1 @RW1+d8 A, RW1 @RW1+d8 A, RW1 @RW1+d8 A, RW1 @RW1+d8 A, RW1 @RW1+d8 RW1, r @RW1+d8,r 30 +1 20 ADDW ADDW A, SUBW SUBW A, ADDCW ADDCW A, CMPW CMPW A, ANDW ANDW A, ORW ORW A, XORW XORW A, DWBNZ DWBNZ A, RW0 @RW0+d8 A, RW0 @RW0+d8 A, RW0 @RW0+d8 A, RW0 @RW0+d8 A, RW0 @RW0+d8 A, RW0 @RW0+d8 A, RW0 @RW0+d8 RW0, r @RW0+d8,r 10 +0 00 APPENDIX B Instructions Table B.9-12 ea Instruction 7 (First Byte = 76H) NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW @RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3 @RW3+d16 SUBW SUBW @RW3+, A addr16, A ADDW ADDW @RW3+, A addr16, A +F SUBCW SUBCW A, NEGW NEGW ANDW ANDW A,@RW3+ addr16 @RW3+ addr16 @RW3+, A addr16, A ORW ORW @RW3+, A addr16, A XORW XORW @RW3+, A addr16, A NOTW NOTW @RW3+ addr16 SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW A,@RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+ @PC+d16 SUBW SUBW @RW2+, A @PC+d16,A ADDW ADDW @RW2+, A @PC+d16,A +E SUBCW A, ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+ @RW1+RW7 SUBCW +D SUBW SUBCW A, ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+ @RW0+RW7 SUBW SUBCW +C ADDW ADDW SUBW SUBCW A, +B @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16 SUBW SUBCW NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW @RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2 @RW2+d16 ADDW ADDW SUBW +A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16 SUBW NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW @RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1 @RW1+d16 ADDW ADDW SUBCW A, +9 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16 SUBCW NEGW NEGW ANDW ANDW ORW ORW XORW XORW NOTW NOTW @RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0 @RW0+d16 SUBW NOTW NOTW RW7 @RW7+d8 NOTW NOTW RW6 @RW6+d8 NOTW NOTW RW5 @RW5+d8 +8 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16 SUBW XORW XORW RW7, A @RW7+d8, A ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW7, A @RW7+d8, A RW7, A @RW7+d8, A A, RW7 @RW7+d8 RW7 @RW7+d8 RW7, A @RW7+d8, A RW7, A @RW7+d8, A +7 ADDW XORW XORW RW6, A @RW6+d8, A ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW6, A @RW6+d8, A RW6, A @RW6+d8, A A, RW6 @RW6+d8 RW6 @RW6+d8 RW6, A @RW6+d8, A RW6, A @RW6+d8, A +6 ADDW XORW XORW RW5, A @RW5+d8, A ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW5, A @RW5+d8, A RW5, A @RW5+d8, A A, RW5 @RW5+d8 RW5 @RW5+d8 RW5, A @RW5+d8, A RW5, A @RW5+d8, A +5 NOTW NOTW RW4 @RW4+d8 XORW XORW RW4, A @RW4+d8, A ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW4, A @RW4+d8, A RW4, A @RW4+d8, A A, RW4 @RW4+d8 RW4 @RW4+d8 RW4, A @RW4+d8, A RW4, A @RW4+d8, A +4 F0 NOTW NOTW RW0 @RW0+d8 E0 NOTW NOTW RW3 @RW3+d8 D0 XORW XORW RW3, A @RW3+d8, A C0 ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW3, A @RW3+d8, A RW3, A @RW3+d8, A A, RW3 @RW3+d8 RW3 @RW3+d8 RW3, A @RW3+d8, A RW3, A @RW3+d8, A B0 +3 A0 NOTW NOTW RW2 @RW2+d8 90 ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW XORW XORW RW2, A @RW2+d8,A RW2, A @RW2+d8,A A, RW2 @RW2+d8 RW2 @RW2+d8 RW2, A @RW2+d8,A RW2, A @RW2+d8,A RW2, A @RW2+d8,A 80 +2 70 NOTW NOTW RW1 @RW1+d8 60 XORW XORW RW1, A @RW1+d8, A 50 ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW1, A @RW1+d8, A RW1, A @RW1+d8, A A, RW1 @RW1+d8 RW1 @RW1+d8 RW1, A @RW1+d8, A RW1, A @RW1+d8, A 40 +1 30 XORW XORW RW0, A @RW0+d8, A 20 ADDW ADDW SUBW SUBW SUBCW SUBCW A, NEGW NEGW ANDW ANDW ORW ORW RW0, A @RW0+d8, A RW0, A @RW0+d8, A A, RW0 @RW0+d8 RW0 @RW0+d8 RW0, A @RW0+d8, A RW0, A @RW0+d8, A 10 +0 00 APPENDIX B Instructions Table B.9-13 ea Instruction 8 (First Byte = 77H) 515 516 DIV DIV A, DIVW DIVW A, A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 DIV DIV A, DIVW DIVW A, A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, A, @RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, A, @RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, A, @RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 MULU MULU A, MULUW MULUW A, A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 MULU MULU A, MULUW MULUW A, A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 MULU MULU A, MULUW MULUW A, A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 +9 +A +B +C +D +E +F A, @RW3+ MULU DIV DIV A, DIVW DIVW A, A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, A, @RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 MULU MULU A, MULUW MULUW A, A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 +8 MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV addr16 A,@RW3+ addr16 A,@RW3+ addr16 A,@RW3+ addr16 A,@RW3+ addr16 A,@RW3+ addr16 A,@RW3+ A, DIVW DIVW A, addr16 A,@RW3+ addr16 DIV DIV A, DIVW DIVW A, A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 DIV DIV A, DIVW DIVW A, A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 DIV DIV A, DIVW DIVW A, A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R7 @RW7+d8 A, RW7 @RW7+d8 A, R7 @RW7+d8 A, RW7 @RW7+d8 A, R7 @RW7+d8 A, RW7 @RW7+d8 A, R7 @RW7+d8 A, RW7 @RW7+d8 F0 +7 E0 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R6 @RW6+d8 A, RW6 @RW6+d8 A, R6 @RW6+d8 A, RW6 @RW6+d8 A, R6 @RW6+d8 A, RW6 @RW6+d8 A, R6 @RW6+d8 A, RW6 @RW6+d8 D0 +6 C0 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R5 @RW5+d8 A, RW5 @RW5+d8 A, R5 @RW5+d8 A, RW5 @RW5+d8 A, R5 @RW5+d8 A, RW5 @RW5+d8 A, R5 @RW5+d8 A, RW5 @RW5+d8 B0 +5 A0 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R4 @RW4+d8 A, RW4 @RW4+d8 A, R4 @RW4+d8 A, RW4 @RW4+d8 A, R4 @RW4+d8 A, RW4 @RW4+d8 A, R4 @RW4+d8 A, RW4 @RW4+d8 90 +4 80 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R3 @RW3+d8 A, RW3 @RW3+d8 A, R3 @RW3+d8 A, RW3 @RW3+d8 A, R3 @RW3+d8 A, RW3 @RW3+d8 A, R3 @RW3+d8 A, RW3 @RW3+d8 70 +3 60 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R2 @RW2+d8 A, RW2 @RW2+d8 A, R2 @RW2+d8 A, RW2 @RW2+d8 A, R2 @RW2+d8 A, RW2 @RW2+d8 A, R2 @RW2+d8 A, RW2 @RW2+d8 50 +2 40 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R1 @RW1+d8 A, RW1 @RW1+d8 A, R1 @RW1+d8 A, RW1 @RW1+d8 A, R1 @RW1+d8 A, RW1 @RW1+d8 A, R1 @RW1+d8 A, RW1 @RW1+d8 30 +1 20 MULU MULU A, MULUW MULUW A, MUL MUL A, MULW MULW A, DIVU DIVU A, DIVUW DIVUW A, DIV DIV A, DIVW DIVW A, A, R0 @RW0+d8 A, RW0 @RW0+d8 A, R0 @RW0+d8 A, RW0 @RW0+d8 A, R0 @RW0+d8 A, RW0 @RW0+d8 A, R0 @RW0+d8 A, RW0 @RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-14 ea Instruction 9 (First Byte = 78H) MOVEA MOVEA RW1 RW1,RW4 ,@RW4+d8 MOVEA MOVEA RW1 RW1,RW5 ,@RW5+d8 MOVEA MOVEA RW1 RW1,RW6 ,@RW6+d8 MOVEA MOVEA RW1 RW1,RW7 ,@RW7+d8 MOVEA MOVEA RW1 RW1,@RW0 ,@RW0+d16 MOVEA MOVEA RW1 RW1,@RW1 ,@RW1+d16 MOVEA MOVEA RW1 RW1,@RW2 ,@RW2+d16 MOVEA MOVEA RW1 RW1,@RW3 ,@RW3+d16 MOVEA MOVEA RW0 RW0,RW4 ,@RW4+d8 MOVEA MOVEA RW0 RW0,RW5 ,@RW5+d8 MOVEA MOVEA RW0 RW0,RW6 ,@RW6+d8 MOVEA MOVEA RW0 RW0,RW7 ,@RW7+d8 MOVEA RW0 MOVEA RW0 MOVEA RW0 MOVEA RW0 MOVEA RW0 MOVEA RW0 MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA +4 +5 +6 +7 50 70 90 B0 C0 D0 F0 MOVEA MOVEA RW3 RW3,@RW2+ ,@PC+d16 MOVEA MOVEA RW4 RW4,@RW2+ ,@PC+d16 MOVEA MOVEA RW7 RW7,@RW2+ ,@PC+d16 MOVEA MOVEA MOVEA MOVEA RW6,@RW3+ RW6, addr16 RW7@RW3+ RW7, addr16 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,@RW2+ ,@PC+d16 RW6,@RW2+ ,@PC+d16 MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA MOVEA RW0,@RW3+ RW0, addr16 RW1,@RW3+ RW1, addr16 RW2,@RW3+ RW2, addr16 RW3,@RW3+ RW3, addr16 RW4,@RW3+ RW4, addr16 RW5,@RW3+ RW5, addr16 MOVEA MOVEA RW2 RW2,@RW2+ ,@PC+d16 +F MOVEA MOVEA RW1 RW1,@RW2+ ,@PC+d16 MOVEA MOVEA RW0 RW0,@RW2+ ,@PC+d16 MOVEA RW1 +E MOVEA MOVEA MOVEA RW5 MOVEA MOVEA RW6 MOVEA MOVEA RW7 RW5,@RW1+ ,@RW1+RW7 RW6,@RW1+ ,@RW1+RW7 RW7,@RW1+ ,@RW1+RW7 MOVEA MOVEA RW7 RW7,@RW3 ,@RW3+d16 MOVEA MOVEA RW7 RW7,@RW2 ,@RW2+d16 MOVEA MOVEA RW7 RW7,@RW1 ,@RW1+d16 MOVEA MOVEA RW7 RW7,@RW0 ,@RW0+d16 MOVEA MOVEA RW7 RW7,RW7 ,@RW7+d8 MOVEA MOVEA RW7 RW7,RW6 ,@RW6+d8 MOVEA MOVEA RW7 RW7,RW5 ,@RW5+d8 MOVEA MOVEA RW7 RW7,RW4 ,@RW4+d8 MOVEA MOVEA RW7 RW7,RW3 ,@RW3+d8 MOVEA MOVEA RW7 RW7,RW2 ,@RW2+d8 MOVEA MOVEA RW7 RW7,RW1 ,@RW1+d8 MOVEA MOVEA RW7 RW7,RW0 ,@RW0+d8 E0 MOVEA MOVEA RW2 MOVEA MOVEA RW3 MOVEA MOVEA RW4 RW2,@RW1+ ,@RW1+RW7 RW3,@RW1+ ,@RW1+RW7 RW4,@RW1+ ,@RW1+RW7 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,@RW3 ,@RW3+d16 RW6,@RW3 ,@RW3+d16 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,@RW2 ,@RW2+d16 RW6,@RW2 ,@RW2+d16 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,@RW1 ,@RW1+d16 RW6,@RW1 ,@RW1+d16 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,@RW0 ,@RW0+d16 RW6,@RW0 ,@RW0+d16 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW7 ,@RW7+d8 RW6,RW7 ,@RW7+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW6 ,@RW6+d8 RW6,RW6 ,@RW6+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW5 ,@RW5+d8 RW6,RW5 ,@RW5+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW4 ,@RW4+d8 RW6,RW4 ,@RW4+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW3 ,@RW3+d8 RW6,RW3 ,@RW3+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW2 ,@RW2+d8 RW6,RW2 ,@RW2+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW1 ,@RW1+d8 RW6,RW1 ,@RW1+d8 MOVEA MOVEA RW5 MOVEA MOVEA RW6 RW5,RW0 ,@RW0+d8 RW6,RW0 ,@RW0+d8 A0 +D RW0,@RW1+ ,@RW1+RW7 RW1,@RW1+ ,@RW1+RW7 MOVEA MOVEA RW4 RW4,@RW3 ,@RW3+d16 MOVEA MOVEA RW4 RW4,@RW2 ,@RW2+d16 MOVEA MOVEA RW4 RW4,@RW1 ,@RW1+d16 MOVEA MOVEA RW4 RW4,@RW0 ,@RW0+d16 MOVEA MOVEA RW4 RW4,RW7 ,@RW7+d8 MOVEA MOVEA RW4 RW4,RW6 ,@RW6+d8 MOVEA MOVEA RW4 RW4,RW5 ,@RW5+d8 MOVEA MOVEA RW4 RW4,RW4 ,@RW4+d8 MOVEA MOVEA RW4 RW4,RW3 ,@RW3+d8 MOVEA MOVEA RW4 RW4,RW2 ,@RW2+d8 MOVEA MOVEA RW4 RW4,RW1 ,@RW1+d8 MOVEA MOVEA RW4 RW4,RW0 ,@RW0+d8 80 MOVEA MOVEA RW5 MOVEA MOVEA RW6 MOVEA MOVEA RW7 RW5,@RW0+ ,@RW0+RW7 RW6,@RW0+ ,@RW0+RW7 RW7,@RW0+ ,@RW0+RW7 MOVEA MOVEA RW3 RW3,@RW3 ,@RW3+d16 MOVEA MOVEA RW3 RW3,@RW2 ,@RW2+d16 MOVEA MOVEA RW3 RW3,@RW1 ,@RW1+d16 MOVEA MOVEA RW3 RW3,@RW0 ,@RW0+d16 MOVEA MOVEA RW3 RW3,RW7 ,@RW7+d8 MOVEA MOVEA RW3 RW3,RW6 ,@RW6+d8 MOVEA MOVEA RW3 RW3,RW5 ,@RW5+d8 MOVEA MOVEA RW3 RW3,RW4 ,@RW4+d8 MOVEA MOVEA RW3 RW3,RW3 ,@RW3+d8 MOVEA MOVEA RW3 RW3,RW2 ,@RW2+d8 MOVEA MOVEA RW3 RW3,RW1 ,@RW1+d8 MOVEA MOVEA RW3 RW3,RW0 ,@RW0+d8 60 MOVEA MOVEA RW2 MOVEA MOVEA RW3 MOVEA MOVEA RW4 RW2,@RW0+ ,@RW0+RW7 RW3,@RW0+ ,@RW0+RW7 RW4,@RW0+ ,@RW0+RW7 MOVEA MOVEA RW2 RW2,@RW3 ,@RW3+d16 MOVEA MOVEA RW2 RW2,@RW2 ,@RW2+d16 MOVEA MOVEA RW2 RW2,@RW1 ,@RW1+d16 MOVEA MOVEA RW2 RW2,@RW0 ,@RW0+d16 MOVEA MOVEA RW2 RW2,RW7 ,@RW7+d8 MOVEA MOVEA RW2 RW2,RW6 ,@RW6+d8 MOVEA MOVEA RW2 RW2,RW5 ,@RW5+d8 MOVEA MOVEA RW2 RW2,RW4 ,@RW4+d8 MOVEA MOVEA RW2 RW2,RW3 ,@RW3+d8 MOVEA MOVEA RW2 RW2,RW2 ,@RW2+d8 MOVEA MOVEA RW2 RW2,RW1 ,@RW1+d8 MOVEA MOVEA RW2 RW2,RW0 ,@RW0+d8 40 +C RW0,@RW0+ ,@RW0+RW7 RW1,@RW0+ ,@RW0+RW7 +B RW0,@RW3 ,@RW3+d16 +A RW0,@RW2 ,@RW2+d16 +9 RW0,@RW1 ,@RW1+d16 MOVEA RW1 MOVEA MOVEA RW1 RW1,RW3 ,@RW3+d8 MOVEA MOVEA RW0 RW0,RW3 ,@RW3+d8 +3 MOVEA MOVEA MOVEA RW1 RW1,RW2 ,@RW2+d8 MOVEA MOVEA RW0 RW0,RW2 ,@RW2+d8 +2 +8 RW0,@RW0 ,@RW0+d16 MOVEA MOVEA RW1 RW1,RW1 ,@RW1+d8 MOVEA MOVEA RW0 RW0,RW1 ,@RW1+d8 +1 30 MOVEA MOVEA RW1 RW1,RW0 ,@RW0+d8 20 MOVEA MOVEA RW0 RW0,RW0 ,@RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-15 MOVEA RWi, ea Instruction (First Byte = 79H) 517 518 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R7 @RW7+d8 R1, R7 @RW7+d8 R2, R7 @RW7+d8 R3, R7 @RW7+d8 R4, R7 @RW7+d8 R5, R7 @RW7+d8 R6, R7 @RW7+d8 R7, R7 @RW7+d8 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0,@RW2 @RW2+d16 R1,@RW2 @RW2+d16 R2,@RW2 @RW2+d16 R3,@RW2 @RW2+d16 R4,@RW2 @RW2+d16 R5,@RW2 @RW2+d16 R6,@RW2 @RW2+d16 R7,@RW2 @RW2+d16 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16 MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7, @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7, @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7, @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 @RW2+ @PC+d16 MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7, @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 @RW3+ addr16 +8 +9 +A +B +C +D +E +F F0 +7 E0 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R6 @RW6+d8 R1, R6 @RW6+d8 R2, R6 @RW6+d8 R3, R6 @RW6+d8 R4, R6 @RW6+d8 R5, R6 @RW6+d8 R6, R6 @RW6+d8 R7, R6 @RW6+d8 D0 +6 C0 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R5 @RW5+d8 R1, R5 @RW5+d8 R2, R5 @RW5+d8 R3, R5 @RW5+d8 R4, R5 @RW5+d8 R5, R5 @RW5+d8 R6, R5 @RW5+d8 R7, R5 @RW5+d8 B0 +5 A0 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R4 @RW4+d8 R1, R4 @RW4+d8 R2, R4 @RW4+d8 R3, R4 @RW4+d8 R4, R4 @RW4+d8 R5, R4 @RW4+d8 R6, R4 @RW4+d8 R7, R4 @RW4+d8 90 +4 80 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R3 @RW3+d8 R1, R3 @RW3+d8 R2, R3 @RW3+d8 R3, R3 @RW3+d8 R4, R3 @RW3+d8 R5, R3 @RW3+d8 R6, R3 @RW3+d8 R7, R3 @RW3+d8 70 +3 60 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R2 @RW2+d8 R1, R2 @RW2+d8 R2, R2 @RW2+d8 R3, R2 @RW2+d8 R4, R2 @RW2+d8 R5, R2 @RW2+d8 R6, R2 @RW2+d8 R7, R2 @RW2+d8 50 +2 40 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R1 @RW1+d8 R1, R1 @RW1+d8 R2, R1 @RW1+d8 R3, R1 @RW1+d8 R4, R1 @RW1+d8 R5, R1 @RW1+d8 R6, R1 @RW1+d8 R7, R1 @RW1+d8 30 +1 20 MOV MOV R0, MOV MOV R1, MOV MOV R2, MOV MOV R3, MOV MOV R4, MOV MOV R5, MOV MOV R6, MOV MOV R7, R0, R0 @RW0+d8 R1, R0 @RW0+d8 R2, R0 @RW0+d8 R3, R0 @RW0+d8 R4, R0 @RW0+d8 R5, R0 @RW0+d8 R6, R0 @RW0+d8 R7, R0 @RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-16 MOV Ri, ea Instruction (First Byte = 7AH) MOVW MOVW RW5, RW5,@RW3 @RW3+d16 MOVW MOVW MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW0,@RW1 @RW1+d16 RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16 RW3,@RW1 @RW1+d16 RW4,@RW1 @RW1+d16 MOVW MOVW MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW0,@RW2 @RW2+d16 RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16 RW3,@RW2 @RW2+d16 RW4,@RW2 @RW2+d16 MOVW MOVW MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW0,@RW3 @RW3+d16 RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16 RW3,@RW3 @RW3+d16 RW4,@RW3 @RW3+d16 MOVW MOVW MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, MOVW MOVW RW5, MOVW MOVW RW6, MOVW MOVW RW7, RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, @RW2+ @PC+d16 RW2, @RW2+ @PC+d16 RW3, @RW2+ @PC+d16 RW4, @RW2+ @PC+d16 MOVW MOVW RW1, @RW3+ RW1, addr16 MOVW RW0, @RW1+ MOVW MOVW RW0, @RW2+ @PC+d16 MOVW MOVW RW0, @RW3+ RW0, addr16 +9 +A +B +C +D +E +F MOVW MOVW RW2, @RW3+ RW2, addr16 MOVW MOVW RW3, @RW3+ RW3, addr16 MOVW MOVW RW5, @RW3+ RW5, addr16 MOVW MOVW RW5, @RW2+ @PC+d16 MOVW MOVW RW6, @RW3+ RW6, addr16 MOVW MOVW RW6, RW6, @RW2+ @PC+d16 MOVW MOVW RW7, @RW3+ RW7, addr16 MOVW MOVW RW7, RW7, @RW2+ @PC+d16 MOVW RW7, @RW1+RW7 MOVW MOVW RW7, RW7,@RW3 @RW3+d16 MOVW MOVW RW7, RW7,@RW2 @RW2+d16 MOVW MOVW RW7, RW7,@RW1 @RW1+d16 MOVW MOVW RW7, RW7,@RW0 @RW0+d16 MOVW MOVW RW7, RW7, RW7 @RW7+d8 MOVW MOVW RW7, RW7, RW6 @RW6+d8 MOVW MOVW RW7, RW7, RW5 @RW5+d8 MOVW MOVW RW7, RW7, RW4 @RW4+d8 MOVW RW6, MOVW @RW1+RW7 RW7, @RW1+ MOVW MOVW RW6, RW6,@RW3 @RW3+d16 MOVW MOVW RW6, RW6,@RW2 @RW2+d16 MOVW MOVW RW6, RW6,@RW1 @RW1+d16 MOVW MOVW RW6, RW6,@RW0 @RW0+d16 MOVW MOVW RW6, RW6, RW7 @RW7+d8 MOVW MOVW RW6, RW6, RW6 @RW6+d8 MOVW MOVW RW6, RW6, RW5 @RW5+d8 MOVW MOVW RW6, RW6, RW4 @RW4+d8 MOVW MOVW @RW1+RW7 RW6, @RW1+ MOVW MOVW RW5, RW5, RW6 @RW6+d8 MOVW MOVW RW5, RW5, RW5 @RW5+d8 MOVW RW4, MOVW @RW1+RW7 RW5, @RW1+ MOVW MOVW RW4, @RW3+ RW4, addr16 MOVW RW3, MOVW @RW1+RW7 RW4, @RW1+ MOVW MOVW RW5, RW5,@RW2 @RW2+d16 MOVW MOVW MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW0,@RW0 @RW0+d16 RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16 RW3,@RW0 @RW0+d16 RW4,@RW0 @RW0+d16 +8 MOVW RW2, MOVW @RW1+RW7 RW3, @RW1+ MOVW MOVW RW5, RW5,@RW1 @RW1+d16 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW7 @RW7+d8 RW2, RW7 @RW7+d8 RW3, RW7 @RW7+d8 RW4, RW7 @RW7+d8 MOVW MOVW RW0, RW7 @RW7+d8 +7 MOVW RW1, MOVW @RW1+RW7 RW2, @RW1+ MOVW MOVW RW5, RW5,@RW0 @RW0+d16 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW6 @RW6+d8 RW2, RW6 @RW6+d8 RW3, RW6 @RW6+d8 RW4, RW6 @RW6+d8 MOVW MOVW RW0, RW6 @RW6+d8 +6 MOVW MOVW @RW1+RW7 RW1, @RW1+ MOVW MOVW RW5, RW5, RW7 @RW7+d8 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW5 @RW5+d8 RW2, RW5 @RW5+d8 RW3, RW5 @RW5+d8 RW4, RW5 @RW5+d8 MOVW MOVW RW0, RW5 @RW5+d8 +5 MOVW MOVW RW5, RW5, RW4 @RW4+d8 MOVW MOVW RW7, RW7, RW3 @RW3+d8 MOVW MOVW RW7, RW7, RW2 @RW2+d8 MOVW MOVW RW7, RW7, RW1 @RW1+d8 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW4 @RW4+d8 RW2, RW4 @RW4+d8 RW3, RW4 @RW4+d8 RW4, RW4 @RW4+d8 MOVW MOVW RW6, RW6, RW3 @RW3+d8 MOVW MOVW RW6, RW6, RW2 @RW2+d8 MOVW MOVW RW6, RW6, RW1 @RW1+d8 MOVW MOVW RW0, RW4 @RW4+d8 MOVW MOVW RW5, RW5, RW3 @RW3+d8 MOVW MOVW RW5, RW5, RW2 @RW2+d8 MOVW MOVW RW5, RW5, RW1 @RW1+d8 +4 F0 MOVW MOVW RW7, RW7, RW0 @RW0+d8 E0 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW3 @RW3+d8 RW2, RW3 @RW3+d8 RW3, RW3 @RW3+d8 RW4, RW3 @RW3+d8 D0 MOVW MOVW RW6, RW6, RW0 @RW0+d8 C0 MOVW MOVW RW0, RW3 @RW3+d8 B0 MOVW MOVW RW5, RW5, RW0 @RW0+d8 A0 +3 90 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW2 @RW2+d8 RW2, RW2 @RW2+d8 RW3, RW2 @RW2+d8 RW4, RW2 @RW2+d8 80 MOVW MOVW RW0, RW2 @RW2+d8 70 +2 60 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW1 @RW1+d8 RW2, RW1 @RW1+d8 RW3, RW1 @RW1+d8 RW4, RW1 @RW1+d8 50 MOVW MOVW RW0, RW1 @RW1+d8 40 +1 30 MOVW MOVW RW1, MOVW MOVW RW2, MOVW MOVW RW3, MOVW MOVW RW4, RW1, RW0 @RW0+d8 RW2, RW0 @RW0+d8 RW3, RW0 @RW0+d8 RW4, RW0 @RW0+d8 20 MOVW MOVW RW0, RW0 @RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-17 MOVW RWi, ea Instruction (First Byte = 7BH) 519 520 +F +E +D +C +B +A +9 +8 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R1 addr16, R1 MOV MOV @RW3+, R0 addr16, R0 MOV MOV MOV @RW2+, R1 @PC+d16, R1 @RW2+, R0 @PC+d16, R0 MOV MOV MOV MOV MOV @RW0+, R1 @RW0+RW7, R1 MOV @RW3, R1 @RW3+d16, R1 MOV @RW2, R1 @RW2+d16, R1 MOV @RW1, R1 @RW1+d16, R1 MOV @RW1+, R1 @RW1+RW7, R1 MOV MOV @RW0, R1 @RW0+d16, R1 MOV @RW1+, R0 @RW1+RW7, R0 MOV @RW0+, R0 @RW0+RW7, R0 MOV @RW3, R0 @RW3+d16, R0 MOV @RW2, R0 @RW2+d16, R0 MOV @RW1, R0 @RW1+d16, R0 MOV @RW0, R0 @RW0+d16, R0 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R2 addr16, R2 MOV @RW2+, R2 @PC+d16, R2 MOV @RW1+, R2 @RW1+RW7, R2 MOV @RW0+, R2 @RW0+RW7, R2 MOV @RW3, R2 @RW3+d16, R2 MOV @RW2, R2 @RW2+d16, R2 MOV @RW1, R2 @RW1+d16, R2 MOV @RW0, R2 @RW0+d16, R2 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R3 addr16, R3 MOV @RW2+, R3 @PC+d16, R3 MOV @RW1+, R3 @RW1+RW7, R3 MOV @RW0+, R3 @RW0+RW7, R3 MOV @RW3, R3 @RW3+d16, R3 MOV @RW2, R3 @RW2+d16, R3 MOV @RW1, R3 @RW1+d16, R3 MOV @RW0, R3 @RW0+d16, R3 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R4 addr16, R4 MOV @RW2+, R4 @PC+d16, R4 MOV @RW1+, R4 @RW1+RW7, R4 MOV @RW0+, R4 @RW0+RW7, R4 MOV @RW3, R4 @RW3+d16, R4 MOV @RW2, R4 @RW2+d16, R4 MOV @RW1, R4 @RW1+d16, R4 MOV @RW0, R4 @RW0+d16, R4 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R5 addr16, R5 MOV @RW2+, R5 @PC+d16, R5 MOV @RW1+, R5 @RW1+RW7, R5 MOV @RW0+, R5 @RW0+RW7, R5 MOV @RW3, R5 @RW3+d16, R5 MOV @RW2, R5 @RW2+d16, R5 MOV @RW1, R5 @RW1+d16, R5 MOV @RW0, R5 @RW0+d16, R5 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R6 addr16, R6 MOV @RW2+, R6 @PC+d16, R6 MOV @RW1+, R6 @RW1+RW7, R6 MOV @RW0+, R6 @RW0+RW7, R6 MOV @RW3, R6 @RW3+d16, R6 MOV @RW2, R6 @RW2+d16, R6 MOV @RW1, R6 @RW1+d16, R6 MOV @RW0, R6 @RW0+d16, R6 MOV MOV MOV MOV MOV MOV MOV MOV MOV @RW3+, R7 addr16, R7 MOV @RW2+, R7 @PC+d16, R7 MOV @RW1+, R7 @RW1+RW7, R7 MOV @RW0+, R7 @RW0+RW7, R7 MOV @RW3, R7 @RW3+d16, R7 MOV @RW2, R7 @RW2+d16, R7 MOV @RW1, R7 @RW1+d16, R7 MOV @RW0, R7 @RW0+d16, R7 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R7, R0 @RW7+d8, R0 R7, R1 @RW7+d8, R1 R7, R2 @RW7+d8, R2 R7, R3 @RW7+d8, R3 R7, R4 @RW7+d8, R4 R7, R5 @RW7+d8, R5 R7, R6 @RW7+d8, R6 R7, R7 @RW7+d8, R7 F0 +7 E0 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R6, R0 @RW6+d8, R0 R6, R1 @RW6+d8, R1 R6, R2 @RW6+d8, R2 R6, R3 @RW6+d8, R3 R6, R4 @RW6+d8, R4 R6, R5 @RW6+d8, R5 R6, R6 @RW6+d8, R6 R6, R7 @RW6+d8, R7 D0 +6 C0 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R5, R0 @RW5+d8, R0 R5, R1 @RW5+d8, R1 R5, R2 @RW5+d8, R2 R5, R3 @RW5+d8, R3 R5, R4 @RW5+d8, R4 R5, R5 @RW5+d8, R5 R5, R6 @RW5+d8, R6 R5, R7 @RW5+d8, R7 B0 +5 A0 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R4, R0 @RW4+d8, R0 R4, R1 @RW4+d8, R1 R4, R2 @RW4+d8, R2 R4, R3 @RW4+d8, R3 R4, R4 @RW4+d8, R4 R4, R5 @RW4+d8, R5 R4, R6 @RW4+d8, R6 R4, R7 @RW4+d8, R7 90 +4 80 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R3, R0 @RW3+d8, R0 R3, R1 @RW3+d8, R1 R3, R2 @RW3+d8, R2 R3, R3 @RW3+d8, R3 R3, R4 @RW3+d8, R4 R3, R5 @RW3+d8, R5 R3, R6 @RW3+d8, R6 R3, R7 @RW3+d8, R7 70 +3 60 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R2, R0 @RW2+d8, R0 R2, R1 @RW2+d8, R1 R2, R2 @RW2+d8, R2 R2, R3 @RW2+d8, R3 R2, R4 @RW2+d8, R4 R2, R5 @RW2+d8, R5 R2, R6 @RW2+d8, R6 R2, R7 @RW2+d8, R7 50 +2 40 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R1, R0 @RW1+d8, R0 R1, R1 @RW1+d8, R1 R1, R2 @RW1+d8, R2 R1, R3 @RW1+d8, R3 R1, R4 @RW1+d8, R4 R1, R5 @RW1+d8, R5 R1, R6 @RW1+d8, R6 R1, R7 @RW1+d8, R7 30 +1 20 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV R0, R0 @RW0+d8, R0 R0, R1 @RW0+d8, R1 R0, R2 @RW0+d8, R2 R0, R3 @RW0+d8, R3 R0, R4 @RW0+d8, R4 R0, R5 @RW0+d8, R5 R0, R6 @RW0+d8, R6 R0, R7 @RW0+d8, R7 10 +0 00 APPENDIX B Instructions Table B.9-18 MOV ea, Ri Instruction (First Byte = 7CH) MOVW MOVW@RW2 @RW2, RW1 +d16, RW1 MOVW MOVW@RW3 @RW3, RW1 +d16, RW1 MOVW MOVW@RW0 @RW0+, RW1 +RW7,RW1 MOVW MOVW@RW1 @RW1+,RW1 +RW7,RW1 MOVW MOVW@PC @RW2+,RW1 +d16, RW1 MOVW MOVW @RW3+,RW1 addr16, RW1 MOVW MOVW@RW2 @RW2, RW0 +d16, RW0 MOVW MOVW@RW3 @RW3, RW0 +d16, RW0 MOVW MOVW@RW0 @RW0+,RW0 +RW7,RW0 MOVW MOVW@RW1 @RW1+,RW0 +RW7,RW0 MOVW MOVW@PC @RW2+,RW0 +d16, RW0 MOVW MOVW @RW3+,RW0 addr16, RW0 +B +C +D +E +F MOVW MOVW @RW3+,RW2 addr16, RW2 MOVW MOVW@PC @RW2+,RW2 +d16, RW2 MOVW MOVW@RW1 @RW1+,RW2 +RW7,RW2 MOVW MOVW@RW0 @RW0+,RW2 +RW7,RW2 MOVW MOVW@RW3 @RW3, RW2 +d16, RW2 MOVW MOVW@RW2 @RW2, RW2 +d16, RW2 MOVW MOVW @RW3+,RW3 addr16, RW3 MOVW MOVW@PC @RW2+,RW3 +d16, RW3 MOVW MOVW@RW1 @RW1+,RW3 -+RW7,RW3 MOVW MOVW@RW0 @RW0+,RW3 +RW7,RW3 MOVW MOVW@RW3 @RW3, RW3 +d16, RW3 MOVW MOVW@RW2 @RW2, RW3 +d16, RW3 MOVW MOVW@RW1 @RW1, RW3 +d16, RW3 MOVW MOVW @RW3+,RW4 addr16, RW4 MOVW MOVW@PC @RW2+,RW4 +d16, RW4 MOVW MOVW@RW1 @RW1+,RW4 +RW7,RW4 MOVW MOVW@RW0 @RW0+,RW4 +RW7,RW4 MOVW MOVW@RW3 @RW3, RW4 +d16, RW4 MOVW MOVW@RW2 @RW2, RW4 +d16, RW4 MOVW MOVW@RW1 @RW1, RW4 +d16, RW4 MOVW MOVW @RW3+,RW5 addr16, RW5 MOVW MOVW@PC @RW2+,RW5 +d16, RW5 MOVW MOVW@RW1 @RW1+,RW5 +RW7,RW5 MOVW MOVW@RW0 @RW0+,RW5 +RW7,RW5 MOVW MOVW@RW3 @RW3, RW5 +d16, RW5 MOVW MOVW@RW2 @RW2, RW5 +d16, RW5 MOVW MOVW@RW1 @RW1, RW5 +d16, RW5 MOVW MOVW @RW3+,RW6 addr16, RW6 MOVW MOVW @PC @RW2+,RW6 +d16, RW6 MOVW MOVW@RW1 @RW1+,RW6 +RW7,RW6 MOVW MOVW@RW0 @RW0+,RW6 +RW7,RW6 MOVW MOVW@RW3 @RW3, RW6 +d16, RW6 MOVW MOVW@RW2 @RW2, RW6 +d16, RW6 MOVW MOVW@RW1 @RW1, RW6 +d16, RW6 MOVW MOVW @RW3+,RW7 addr16, RW7 MOVW MOVW@PC @RW2+,RW7 +d16, RW7 MOVW MOVW@RW1 @RW1+,RW7 +RW7,RW7 MOVW MOVW@RW0 @RW0+,RW7 +RW7,RW7 MOVW MOVW@RW3 @RW3, RW7 +d16, RW7 MOVW MOVW@RW2 @RW2, RW7 +d16, RW7 MOVW MOVW@RW1 @RW1, RW7 +d16, RW7 MOVW MOVW@RW0 @RW0, RW7 +d16, RW7 +A MOVW MOVW@RW1 @RW1, RW2 +d16, RW2 MOVW MOVW@RW0 @RW0, RW6 +d16, RW6 MOVW MOVW@RW1 @RW1, RW1 +d16, RW1 MOVW MOVW@RW0 @RW0, RW5 +d16, RW5 MOVW MOVW@RW1 @RW1, RW0 +d16, RW0 MOVW MOVW@RW0 @RW0, RW4 +d16, RW4 +9 MOVW MOVW@RW0 @RW0, RW3 +d16, RW3 MOVW MOVW@RW0 @RW0, RW1 +d16, RW1 MOVW MOVW@RW0 @RW0, RW0 +d16, RW0 +8 MOVW MOVW@RW0 @RW0, RW2 +d16, RW2 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW7, RW0 @RW7+d8, RW0 RW7, RW1 @RW7+d8, RW1 RW7, RW2 @RW7+d8, RW2 RW7, RW3 @RW7+d8, RW3 RW7, RW4 @RW7+d8, RW4 RW7, RW5 @RW7+d8, RW5 RW7, RW6 @RW7+d8, RW6 RW7, RW7 @RW7+d8, RW7 F0 +7 E0 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW6, RW0 @RW6+d8, RW0 RW6, RW1 @RW6+d8, RW1 RW6, RW2 @RW6+d8, RW2 RW6, RW3 @RW6+d8, RW3 RW6, RW4 @RW6+d8, RW4 RW6, RW5 @RW6+d8, RW5 RW6, RW6 @RW6+d8, RW6 RW6, RW7 @RW6+d8, RW7 D0 +6 C0 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW5, RW0 @RW5+d8, RW0 RW5, RW1 @RW5+d8, RW1 RW5, RW2 @RW5+d8, RW2 RW5, RW3 @RW5+d8, RW3 RW5, RW4 @RW5+d8, RW4 RW5, RW5 @RW5+d8, RW5 RW5, RW6 @RW5+d8, RW6 RW5, RW7 @RW5+d8, RW7 B0 +5 A0 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW4, RW0 @RW4+d8, RW0 RW4, RW1 @RW4+d8, RW1 RW4, RW2 @RW4+d8, RW2 RW4, RW3 @RW4+d8, RW3 RW4, RW4 @RW4+d8, RW4 RW4, RW5 @RW4+d8, RW5 RW4, RW6 @RW4+d8, RW6 RW4, RW7 @RW4+d8, RW7 90 +4 80 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW3, RW0 @RW3+d8, RW0 RW3, RW1 @RW3+d8, RW1 RW3, RW2 @RW3+d8, RW2 RW3, RW3 @RW3+d8, RW3 RW3, RW4 @RW3+d8, RW4 RW3, RW5 @RW3+d8, RW5 RW3, RW6 @RW3+d8, RW6 RW3, RW7 @RW3+d8, RW7 70 +3 60 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW2, RW0 @RW2+d8, RW0 RW2, RW1 @RW2+d8, RW1 RW2, RW2 @RW2+d8, RW2 RW2, RW3 @RW2+d8, RW3 RW2, RW4 @RW2+d8, RW4 RW2, RW5 @RW2+d8, RW5 RW2, RW6 @RW2+d8, RW6 RW2, RW7 @RW2+d8, RW7 50 +2 40 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW1, RW0 @RW1+d8, RW0 RW1, RW1 @RW1+d8, RW1 RW1, RW2 @RW1+d8, RW2 RW1, RW3 @RW1+d8, RW3 RW1, RW4 @RW1+d8, RW4 RW1, RW5 @RW1+d8, RW5 RW1, RW6 @RW1+d8, RW6 RW1, RW7 @RW1+d8, RW7 30 +1 20 MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW RW0, RW0 @RW0+d8, RW0 RW0, RW1 @RW0+d8, RW1 RW0, RW2 @RW0+d8, RW2 RW0, RW3 @RW0+d8, RW3 RW0, RW4 @RW0+d8, RW4 RW0, RW5 @RW0+d8, RW5 RW0, RW6 @RW0+d8, RW6 RW0, RW7 @RW0+d8, RW7 10 +0 00 APPENDIX B Instructions Table B.9-19 MOVW ea, Rwi Instruction (First Byte = 7DH) 521 522 XCH XCH XCH XCH R1, XCH XCH R1, R1,@RW2 W2+d16, A XCH XCH R2, XCH XCH R2, R2,@RW2 W2+d16, A XCH XCH R3, XCH XCH R3, R3,@RW2 W2+d16, A XCH XCH R4, XCH XCH R4, R4,@RW2 W2+d16, A XCH XCH R5, XCH XCH R5, R5,@RW2 W2+d16, A XCH XCH R6, XCH XCH R6, R6,@RW2 W2+d16, A XCH XCH R7, XCH XCH R7, R7,@RW2 W2+d16, A XCH XCH XCH XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, +F R0,@RW3+ R0, addr16 XCH XCH R1,@RW3+ R1, addr16 XCH XCH R2,@RW3+ R2, addr16 XCH XCH R3,@RW3+ R3, addr16 XCH XCH R4,@RW3+ R4, addr16 XCH XCH R5,@RW3+ R5, addr16 XCH XCH R6,@RW3+ R6, addr16 XCH XCH R7,@RW3+ R7, addr16 +E R0,@RW2+ @PC+d16 R1,@RW2+ @PC+d16 R2,@RW2+ @PC+d16 R3,@RW2+ @PC+d16 R4,@RW2+ @PC+d16 R5,@RW2+ @PC+d16 R6,@RW2+ @PC+d16 R7,@RW2+ @PC+d16 R0, XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, @RW1+RW7 R1,@RW1+ @RW1+RW7 R2,@RW1+ @RW1+RW7 R3,@RW1+ @RW1+RW7 R4,@RW1+ @RW1+RW7 R5,@RW1+ @RW1+RW7 R6,@RW1+ @RW1+RW7 R7,@RW1+ @RW1+RW7 +D R0,@RW1+ XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, @RW0+RW7 R1,@RW0+ @RW0+RW7 R2,@RW0+ @RW0+RW7 R3,@RW0+ @RW0+RW7 R4,@RW0+ @RW0+RW7 R5,@RW0+ @RW0+RW7 R6,@RW0+ @RW0+RW7 R7,@RW0+ @RW0+RW7 XCH +C R0,@RW0+ +B R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16 R0, +A R0,@RW2 W2+d16, A R0, XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16 +9 XCH XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16 +8 XCH XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R7 @RW7+d8 R1, R7 @RW7+d8 R2, R7 @RW7+d8 R3, R7 @RW7+d8 R4, R7 @RW7+d8 R5, R7 @RW7+d8 R6, R7 @RW7+d8 R7, R7 @RW7+d8 F0 +7 E0 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R6 @RW6+d8 R1, R6 @RW6+d8 R2, R6 @RW6+d8 R3, R6 @RW6+d8 R4, R6 @RW6+d8 R5, R6 @RW6+d8 R6, R6 @RW6+d8 R7, R6 @RW6+d8 D0 +6 C0 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R5 @RW5+d8 R1, R5 @RW5+d8 R2, R5 @RW5+d8 R3, R5 @RW5+d8 R4, R5 @RW5+d8 R5, R5 @RW5+d8 R6, R5 @RW5+d8 R7, R5 @RW5+d8 B0 +5 A XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R4 @RW4+d8 R1, R4 @RW4+d8 R2, R4 @RW4+d8 R3, R4 @RW4+d8 R4, R4 @RW4+d8 R5, R4 @RW4+d8 R6, R4 @RW4+d8 R7, R4 @RW4+d8 90 +4 80 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R3 @RW3+d8 R1, R3 @RW3+d8 R2, R3 @RW3+d8 R3, R3 @RW3+d8 R4, R3 @RW3+d8 R5, R3 @RW3+d8 R6, R3 @RW3+d8 R7, R3 @RW3+d8 70 +3 60 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R2 @RW2+d8 R1, R2 @RW2+d8 R2, R2 @RW2+d8 R3, R2 @RW2+d8 R4, R2 @RW2+d8 R5, R2 @RW2+d8 R6, R2 @RW2+d8 R7, R2 @RW2+d8 50 +2 40 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R1 @RW1+d8 R1, R1 @RW1+d8 R2, R1 @RW1+d8 R3, R1 @RW1+d8 R4, R1 @RW1+d8 R5, R1 @RW1+d8 R6, R1 @RW1+d8 R7, R1 @RW1+d8 30 +1 20 XCH XCH R0, XCH XCH R1, XCH XCH R2, XCH XCH R3, XCH XCH R4, XCH XCH R5, XCH XCH R6, XCH XCH R7, R0, R0 @RW0+d8 R1, R0 @RW0+d8 R2, R0 @RW0+d8 R3, R0 @RW0+d8 R4, R0 @RW0+d8 R5, R0 @RW0+d8 R6, R0 @RW0+d8 R7, R0 @RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH) XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW2+ @PC+d16 RW1,@RW2+ @PC+d16 RW2,@RW2+ @PC+d16 RW3,@RW2+ @PC+d16 RW4,@RW2+ @PC+d16 RW5,@RW2+ @PC+d16 RW6,@RW2+ @PC+d16 RW7,@RW2+ @PC+d16 XCHW XCHW RW0,@RW3+ RW0, addr16 +E +F XCHW XCHW RW7,@RW3+ RW7, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW1+ @RW1+RW7 RW1,@RW1+ @RW1+RW7 RW2,@RW1+ @RW1+RW7 RW3,@RW1+ @RW1+RW7 RW4,@RW1+ @RW1+RW7 RW5,@RW1+ @RW1+RW7 RW6,@RW1+ @RW1+RW7 RW7,@RW1+ @RW1+RW7 +D XCHW XCHW RW6,@RW3+ RW6, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7 +C XCHW XCHW RW5,@RW3+ RW5, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW3 @RW3+d16 RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16 RW3,@RW3 @RW3+d16 RW4,@RW3 @RW3+d16 RW5,@RW3 @RW3+d16 RW6,@RW3 @RW3+d16 RW7,@RW3 @RW3+d16 +B XCHW XCHW RW4,@RW3+ RW4, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW2 @RW2+d16 RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16 RW3,@RW2 @RW2+d16 RW4,@RW2 @RW2+d16 RW5,@RW2 @RW2+d16 RW6,@RW2 @RW2+d16 RW7,@RW2 @RW2+d16 +A XCHW XCHW RW3,@RW3+ RW3, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW1 @RW1+d16 RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16 RW3,@RW1 @RW1+d16 RW4,@RW1 @RW1+d16 RW5,@RW1 @RW1+d16 RW6,@RW1 @RW1+d16 RW7,@RW1 @RW1+d16 +9 XCHW XCHW RW2,@RW3+ RW2, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0,@RW0 @RW0+d16 RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16 RW3,@RW0 @RW0+d16 RW4,@RW0 @RW0+d16 RW5,@RW0 @RW0+d16 RW6,@RW0 @RW0+d16 RW7,@RW0 @RW0+d16 +8 XCHW XCHW RW1,@RW3+ RW1, addr16 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW7 @RW7+d8 RW1, RW7 @RW7+d8 RW2, RW7 @RW7+d8 RW3, RW7 @RW7+d8 RW4, RW7 @RW7+d8 RW5, RW7 @RW7+d8 RW6, RW7 @RW7+d8 RW7, RW7 @RW7+d8 F0 +7 E0 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW6 @RW6+d8 RW1, RW6 @RW6+d8 RW2, RW6 @RW6+d8 RW3, RW6 @RW6+d8 RW4, RW6 @RW6+d8 RW5, RW6 @RW6+d8 RW6, RW6 @RW6+d8 RW7, RW6 @RW6+d8 D0 +6 C0 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW5 @RW5+d8 RW1, RW5 @RW5+d8 RW2, RW5 @RW5+d8 RW3, RW5 @RW5+d8 RW4, RW5 @RW5+d8 RW5, RW5 @RW5+d8 RW6, RW5 @RW5+d8 RW7, RW5 @RW5+d8 B0 +5 A0 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW4 @RW4+d8 RW1, RW4 @RW4+d8 RW2, RW4 @RW4+d8 RW3, RW4 @RW4+d8 RW4, RW4 @RW4+d8 RW5, RW4 @RW4+d8 RW6, RW4 @RW4+d8 RW7, RW4 @RW4+d8 90 +4 80 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW3 @RW3+d8 RW1, RW3 @RW3+d8 RW2, RW3 @RW3+d8 RW3, RW3 @RW3+d8 RW4, RW3 @RW3+d8 RW5, RW3 @RW3+d8 RW6, RW3 @RW3+d8 RW7, RW3 @RW3+d8 70 +3 60 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW2 @RW2+d8 RW1, RW2 @RW2+d8 RW2, RW2 @RW2+d8 RW3, RW2 @RW2+d8 RW4, RW2 @RW2+d8 RW5, RW2 @RW2+d8 RW6, RW2 @RW2+d8 RW7, RW2 @RW2+d8 50 +2 40 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW1 @RW1+d8 RW1, RW1 @RW1+d8 RW2, RW1 @RW1+d8 RW3, RW1 @RW1+d8 RW4, RW1 @RW1+d8 RW5, RW1 @RW1+d8 RW6, RW1 @RW1+d8 RW7, RW1 @RW1+d8 30 +1 20 XCHW XCHW RW0, XCHW XCHW RW1, XCHW XCHW RW2, XCHW XCHW RW3, XCHW XCHW RW4, XCHW XCHW RW5, XCHW XCHW RW6, XCHW XCHW RW7, RW0, RW0 @RW0+d8 RW1, RW0 @RW0+d8 RW2, RW0 @RW0+d8 RW3, RW0 @RW0+d8 RW4, RW0 @RW0+d8 RW5, RW0 @RW0+d8 RW6, RW0 @RW0+d8 RW7, RW0 @RW0+d8 10 +0 00 APPENDIX B Instructions Table B.9-21 XCHW RWi, ea Instruction (First Byte = 7FH) 523 APPENDIX C Index of Registers APPENDIX C Index of Registers This section provides an index for finding the page containing the description of an MB90M405 series register from the register address, peripheral resource name, abbreviation, or register name. ■ Index of Registers Table C-1 Index of Registers Peripheral resource Page number Port 8 data register Port 8 158 PDR9 Port 9 data register Port 9 163 00000AH PDRA Port A data register Port A 168 00000BH PDRB Port B data register Port B 174 000018H DDR8 Port 8 direction register Port 8 158 000019H DDR9 Port 9 direction register Port 9 163 00001AH DDRA Port A direction register Port A 168 00001BH DDRB Port B direction register Port B 174 00001EH ADER0 Analog input enable register 0 Port A, A/D 168 00001FH ADER1 Analog input enable register 1 Port B, A/D 174 000020H SMR(0) Mode register ch0 275 000021H SCR(0) Control register ch0 272 000022H SIDR(0)/ SODR(0) 000023H SSR(0) Status register ch0 277 000024H SMR(1) Mode register ch1 275 000025H SCR(1) Control register ch1 272 000026H SIDR(1)/ SODR(1) 000027H SSR(1) 000028H CDCR(0) Communication prescaler control register ch0 Communication prescaler 0 282 000029H CDCR(1) Communication prescaler control register ch1 Communication prescaler 1 282 Address Abbreviation 000008H PDR8 000009H 524 Register Input data register ch0/Output data register ch0 Input data register ch0/Output data register ch1 UART ch0 280, 280 UART ch1 280, 280 Status register ch1 277 APPENDIX C Index of Registers Table C-1 Index of Registers (Continued) Register Peripheral resource Page number Address Abbreviation 00002AH IBSR I2C status register 336 00002BH IBCR I2C control register 338 00002CH ICCR I2C clock control register 00002DH IADR I2C address register 00002EH IDAR I2C data register 345 00002FH ISEL I2C port selection register 346 000030H ENIR DTP/Interrupt enable register 000031H EIRR DTP/interrupt cause register 000032H ELVR Request level setting register 000034H ADCS0 000035H ADCS1 000036H ADCR0 000037H ADCR1 000039H 000040H 000042H I2C interface 341 344 319 DTP/external interrupt 316 321 365 A/D control status register 363 A/D converter A/D data register 367 ADMR A/D conversion channel setting register 369 TCCS Timer counter control status register 250 16-bit freerunning timer TCDT Timer counter data register 249 IPC(0) Input capture data register ch0 IPC(1) Input capture data register ch1 255 ICSO1 Input capture control status register 256 OCCP0 Output compare register ch0 000043H 000044H 255 000045H 000046H Input capture 000047H 000048H 00004AH 00004BH 00004CH 000050H OCS0 TMCSR(0) Output compare control status register ch0 000053H TMR(0)/ TMRLR(0) 253 Timer control status register ch0 000051H 000052H 252 Output compare 16-bit timer register/16-bit reload register ch0 229 to 231 16-bit reload timer ch0 233 to 234 525 APPENDIX C Index of Registers Table C-1 Index of Registers (Continued) Address 000054H Abbreviation TMCSR(1) Peripheral resource Register Timer control status register ch1 000055H 000056H 000057H 000058H TMR(1)/ TMRLR(1) 16-bit timer register/16-bit reload register ch1 TMCSR(2) Timer control status register ch2 000059H 00005AH 00005BH 000060H TMR(2)/ TMRLR(2) 16-bit timer register/16-bit reload register ch2 SMCR(2) Serial mode control status register ch2 000061H 000062H 000064H Page number 229 to 231 16-bit reload timer ch1 233 to 234 229 to 231 16-bit reload timer ch2 233 to 234 184 Serial I/O ch2 SDR(2) SMCR(3) Serial shift data register ch2 188 Serial mode control status register ch3 000065H 184 Serial I/O ch3 000066H SDR(3) Serial shift data register ch3 188 000068H FLC1 Display control register 1 385 000069H FLC2 Display control register 2 387 FL control circuit 00006AH FLDG Digit setting register 00006BH FLDC Digit count register 391 00006DH FLST Status/settlement register 394 00006FH ROMM 000070H to 000070H SEGD0 to SEGD7 000078H FLPD0 000079H FLPD1 00007AH FLPD2 00009EH PACSR 00009FH DIRR 526 ROM mirroring function selection register ROM mirroring function selection module Segment dimmer setting register FIP36 to 43 Port register 389 425 397 FL control circuit 393 FIP44 to 51 FIP52 to 59 Program address detection control status register Delayed interrupt cause generation/release register Address match detection circuit 417 Delayed interrupt 409 APPENDIX C Index of Registers Table C-1 Index of Registers (Continued) Peripheral resource Page number Low power consumption control circuit 86 Watchdog timer control register Watchdog timer 215 TBTC Timebase timer control register Timebase timer 204 0000AEH FMCS Flash memory control status register 1M-bit flash memory 430 0000AFH TMCS Watch clock output control register Watch clock division 406 0000B0H to 0000BFH ICR00 to ICR15 Interrupt control register ch0 to ch15 Interrupt controller 108 000100H to 0010FFH RAM area RAM memory 001100H to 0011FFH FL000 to FL255 Display data RAM Address Abbreviation 0000A0H LPMCR Low power consumption mode control register 0000A1H CKSCR Clock selection register 0000A8H WDTC 0000A9H PADR0 Program address detection register (upper) 001FF3H Program address detection register (lower) PADR1 FL control circuit 396 Address match detection function 416 Program address detection register (middle) Program address detection register (upper) 001FF5H FE0000H (FE8000H) to FFFFFFH RAM Program address detection register (middle) 001FF2H 001FF4H 75 Program address detection register (lower) 001FF0H 001FF1H Register ROM area ROM ROM 527 APPENDIX D Index of Pin Functions APPENDIX D Index of Pin Functions This section provides an index for finding the page containing a block diagram and description from the MB90M405 series package pin number, pin name, circuit type, or peripheral resource name. ■ Index of Pin Functions Table D-1 Index of Index of Pin Functions Pin number 82, 83 77 85 to 100 1 Pin name Functional description Block diagram A Oscillation pin 10 14 RST B Reset input 10 14 383 383 383 383 383 383 FL control circuit 384 384 P80 General-purpose I/O port 8 bit 0 158 159 IC0 Input capture ch0 158 159 INT0 External interrupt input ch0 314 314 P81 General-purpose I/O port 8 bit 1 158 159 IC1 Input capture ch0 158 159 INT1 External interrupt input ch1 314 314 General-purpose I/O port 8 bit 2 158 159 SI0 UART data input ch0 269 270 P83 General-purpose I/O port 8 bit 3 158 159 SC0 UART clock I/O ch0 269 270 P84 General-purpose I/O port 8 bit 4 158 159 SO0 UART data output ch0 269 270 P85 General-purpose I/O port 8 bit 5 158 159 SI1 UART data input ch1 269 270 FIP0 to FIP16 LED0 to LED16 FIP17 to FIP33 20 to 22 24 to 41 43 to 47 FIP34 to FIP59 53 Peripheral resource name and function name X0, X1 2 to 10 12 to 19 52 Circuit type C D P82 54 FL control circuit E 55 56 57 528 APPENDIX D Index of Pin Functions Table D-1 Index of Index of Pin Functions (Continued) Pin number Functional description Block diagram General-purpose I/O port 8 bit 6 158 159 UART clock I/O ch1 269 270 P87 General-purpose I/O port 8 bit 7 158 159 SO1 UART data output ch1 269 270 P90 General-purpose I/O port 9 bit 0 163 164 SDA I2C 333 333 Serial I/O data output ch3 163 164 P91 General-purpose I/O port 9 bit 1 163 164 SCL I2C 333 333 SC3 Serial I/O clock I/O ch3 163 164 PA0 General-purpose I/O port A bit 0 168 169 AN0 A/D converter analog input ch0 360 361 TMCK Watch clock output pin - 169 PA1 to PA7 General-purpose I/O port A bit 1 to bit 7 168 169 AN1 to AN7 A/D converter analog input ch1 to ch7 360 361 PB0 to PB2 General-purpose I/O port B bit 0 to bit 2 172 172 AN8 to AN10 A/D converter analog input ch8 to ch10 358 359 PB3 General-purpose I/O port B bit 3 174 175 A/D converter analog input ch11 360 361 SI2 Serial I/O data input ch2 174 175 PB4 General-purpose I/O port B bit 4 174 175 AN12 A/D converter analog input ch12 360 361 SC2 Serial I/O clock I/O ch2 174 175 TIN0 Reload timer event input ch0 227 227 PB5 General-purpose I/O port B bit 5 174 175 AN13 A/D converter analog input ch13 360 361 SO2 Serial I/O data output ch2 174 175 PB6 to PB7 General-purpose I/O port B bit 6 to bit 7 174 175 A/D converter analog input ch14 to ch15 360 361 External interrupt input ch2 to ch3 314 314 Pin name Circuit type P86 Peripheral resource name and function name 58 SC1 E 59 60 SO3 G 61 64 65 to 71 72 to 74 75 AN11 F 76 78 79, 80 AN14 to AN15 INT2 to INT3 F 529 APPENDIX D Index of Pin Functions Table D-1 Index of Index of Pin Functions (Continued) Pin number 62 Pin name AVCC Circuit type H Peripheral resource name and function name Functional description Block diagram Analog VCC power input pin 10 15 Analog VSS power input pin 10 15 63 AVSS 48 VKK - High withstand voltage output pull-down power pin 10 - 49 MD0 - Power mode specification input pin 0 10 - 50 MD1 - Power mode specification input pin 1 10 - 51 MD2 - Operating mode specification input pin 2 10 - 11, 42 VSS-IO - I/O power (GND) input pin 10 - 23 VDD-FIP - FIP power (3V) input pin 10 - 81 VSS-CPU - Control circuit power (GND) input pin 10 - 84 VCC-CPU - Control circuit power (3V) input pin 10 - 530 INDEX INDEX The index follows on the next page. This is listed in alphabetic order. 531 INDEX Index Numerics 16-bit free-running timer (one channel) ................ 246 16-bit Free-running timer count timing ................. 259 16-bit free-running timer operation ....................... 258 16-bit I/O timer block diagram .............................. 247 16-bit I/O timer register ........................................ 248 16-bit input capture operation .............................. 261 16-bit output compare operation .......................... 260 16-bit reload register (TMRLR)............................. 234 16-bit reload timer interrupt .................................. 235 16-bit reload timer interrupt and EI2OS........ 224, 235 16-bit reload timer operating mode ...................... 222 16-bit reload timer pin .......................................... 227 16-bit reload timer pin, block diagram of .............. 227 16-bit reload timer register ................................... 228 16-bit reload timer setting..................................... 236 16-bit reload timer, block diagram of.................... 225 16-bit reload timer, EI2OS function of .................. 235 16-bit reload timer, usage note on ....................... 244 16-bit timer register (TMR) ................................... 233 1M-bit flash memory, feature of............................ 428 24-bit operand specification, linear addressing by............................................... 29 8/10-bit A/D converter interrupt ............................ 371 8/10-bit A/D converter interrupt and EI2OS .................................................357, 371 8/10-bit A/D converter pin .................................... 360 8/10-bit A/D converter pin, block diagram of ........ 361 8/10-bit A/D converter register ............................. 362 8/10-bit A/D converter, block diagram of.............. 358 8/10-bit A/D converter, EI2OS function of ............371 8/10-bit A/D converter, function of........................ 356 8/10-bit A/D converter, usage note on ................. 378 A A/D control status register 0 (ADCS0).................. 365 A/D control status register 1 (ADCS1).................. 363 A/D conversion channel select register (ADMR) .. 369 A/D conversion data protection function .............. 376 A/D converter power supply analog input, power-on sequence for ................................ 17 A/D data register (ADCR0/ADCR1)...................... 367 access to low power consumption mode control register ......................................................... 87 532 accumulator (A)...................................................... 37 acknowledgement ................................................ 348 address match detection function, block diagram of.................................................. 414 address match detection function, list of registers of ................................................. 415 address match detection function, operation of ... 418 Addressing .......................................................... 465 addressing ................................................... 347, 436 arbitration ............................................................. 348 asynchronous mode, operation in........................ 298 automatic fluorescent tube display digits and segments and automatic LED display pin, assignment of ............................................ 398 automatic fluorescent tube display function ......... 380 automatic fluorescent tube display, start and stop timings of............................................ 401 automatic LED display function............................ 381 automatic LED display pin ................................... 398 automatic LED display, start and stop timing of ..................................................... 402 B bank addressing..................................................... 28 bank addressing and default space ....................... 31 bank register (PCB, DTB, USB, SSB, ADB) .......... 49 bank register and access space ............................ 30 bank select prefixe (PCB, DTB, ADB, SPB) .......... 53 bidirectional communication function ................... 302 block diagram........................................................... 7 block diagram of low power consumption control circuit................................................ 84 buffer address pointer (BAP) ............................... 133 bus error............................................................... 348 bus mode ............................................................. 148 bus mode setting bit............................................. 150 C calculating execution cycle count......................... 482 clock....................................................................... 72 clock generation block, block diagram of ............... 73 clock mode............................................................. 83 clock mode transition ............................................. 77 clock selection register (CKSCR), configuration of ............................................ 75 INDEX clock supply function.................................... 200, 208 clock supply map ................................................... 19 command sequence table.................................... 433 common register bank prefix (CMR) ...................... 55 communication prescaler control register (CDCR0/CDCR1)............................... 189, 282 competition among SCC, MSS and INT bit, note on....................................................... 340 condition code register (CCR) configuration .......... 43 configuration of extended intelligent I/O service (El2OS) descriptor (ISD) ............................ 129 configuration of interrupt control register (ICR).... 110 consecutive prefix code ......................................... 58 continuous conversion mode, operation in .......... 373 control register (SCR0/SCR1).............................. 272 conversion using EI2OS....................................... 375 correspondence between reset cause flag bit ....... 67 counter operating status ...................................... 237 counter operation ................................................. 223 CPU ....................................................................... 22 CPU intermittent operation mode..................... 83, 89 CPU operating mode and current consumption..... 82 crystal oscillation circuit ......................................... 17 D data counter (DCT) .............................................. 131 dedicated baud rate generator, baud rate determined using ....................................... 291 dedicated register and general-purpose register ... 34 dedicated register, configuration of........................ 35 delayed interrupt cause/cancel register (DIRR) ... 409 delayed interrupt generator module, operation of................................................ 410 delayed interrupt generator module, block diagram of.................................................. 408 delayed interrupt generator module, precautions to follow when using .................................. 411 Description of Instruction Presentation Items and Symbols .................................................... 485 digit count register (FLDC)................................... 391 digit setting register (FLDG) ................................. 389 Direct Addressing ................................................ 467 direct page register (DPR) ..................................... 48 display control register 1 (FLC1) .......................... 385 display control register 2 (FLC2) .......................... 387 display RAM......................................................... 396 DTP function, operation of ................................... 327 DTP/external interrupt circuit and EI2OS, interrupt of.................................................. 311 DTP/external interrupt circuit pin.......................... 314 DTP/external interrupt circuit pin, block diagram of ..................................................314 DTP/external interrupt circuit register ...................315 DTP/external interrupt circuit, block diagram of....312 DTP/external interrupt circuit, usage note on .......328 DTP/external interrupt function.............................310 DTP/interrupt cause register (EIRR).....................316 DTP/interrupt enable register (ENIR) ...................319 E E2PROM memory map.........................................419 Effective Address Field ................................466, 484 event count mode .................................................242 event count mode (external clock mode)..............223 exception processing............................................139 execution cycle count ...........................................481 extended intelligent I/O service (EI2OS) ...............127 extended intelligent I/O service (EI2OS) status register (ISCS)............................................132 extended intelligent I/O service (EI2OS), processing specification of sample program for .................................................144 external clock, baud rate determined using..........295 external clock, note on............................................17 external interrupt function .....................................326 external reset pin, block diagram of........................63 external shift clock mode ......................................192 F F2MC-16LX instruction list....................................488 FL control circuit pin .............................................383 FL control circuit pin, block diagram of .................383 FL control circuit, reading from/writing to registers or display RAM in ........................399 FL control circuit ...................................................382 FL control circuit, block diagram of.......................382 flag change suppression prefix (NCC)....................56 flash memory (chip deletion), deleting all data item from ....................................................438 flash memory (sector deletion), deleting a data item from ....................................................439 flash memory control status register (FMCS) .......430 flash memory sector deletion, resuming...............442 flash memory writing and deletion, detailed description of ..............................................434 flash memory, register of ......................................429 flash memory, writing data to................................436 flash memory, writing data to or deleting data from ....................................................428 flash memory, writing to and deletion from...........428 533 INDEX flash microcomputer programmer (when power supplied by user), example of minimum connection with .......................................... 450 flash microcomputer programmer (when power supplied from programmer), example of minimum connection with........................... 452 FPT-100P-M06 Dimension....................................... 8 G general-purpose register ........................................ 34 general-purpose register area and register bank pointer ................................................. 45 general-purpose register, configuration of.............. 50 H hardware interrupt ................................................ 113 hardware interrupt activation................................ 116 hardware interrupt disable.................................... 114 hardware interrupt operation ................................ 117 hardware interrupt processing time ...................... 123 hardware interrupt structure ................................. 114 high dielectric output pin ......................................380 high dielectric output pin (circuit type C or D), output of ....................................................... 18 I I/O area .................................................................. 25 I/O circuit type ........................................................ 14 I/O map ................................................................456 I/O port also used for resource when DDR is set to port output, operation of ...................155 I/O port function.................................................... 154 I/O port register .................................................... 156 I/O register address pointer (IOA) ........................ 131 I2C address register (IADR) ................................. 344 I2C clock control register (ICCR) .......................... 341 I2C control register (IBCR) ................................... 338 I2C data register (IDAR) ....................................... 345 I2C interface mode transition, flow of ...................351 I2C interface register ............................................335 I2C interface, block diagram of ............................. 333 I2C interface, configuration of............................... 334 I2C interface, feature of ........................................ 332 I2C interface, operation flow of ............................. 352 I2C interface, transfer flow of................................ 349 I2C port select register (ISEL) .............................. 346 I2C status register (IBSR)..................................... 336 index of pin function ............................................. 528 index of register.................................................... 524 534 Indirect Addressing ............................................. 473 indirect specification with 32-bit register, addressing by .............................................. 29 initial state ............................................................ 419 input capture (two channel).................................. 246 input capture control status register (ICS01) ....... 256 input capture data register (IPC0/IPC1)............... 255 input capture input timing..................................... 262 input data register (SIDR0/SIDR1)....................... 280 Instruction Types ................................................. 464 INT9 interrupt ....................................................... 420 internal clock mode .............................................. 222 internal clock mode (reload mode), operation in ................................................ 238 internal clock mode (single-shot mode) ............... 240 internal peripheral function (resources) ................... 3 internal shift clock mode ...................................... 192 internal timer (16-bit reload timer), baud rate determined using ....................................... 293 interrupt cause and interrupt vector/interrupt control register ........................................... 105 interrupt control register ............................... 105, 106 interrupt control register (ICR00 to ICR15) .......... 108 interrupt control register function ......................... 111 interrupt control registers (ICR)............................ 110 interrupt level mask register (ILM) ......................... 46 interrupt operation................................................ 103 interrupt suppression instruction ............................ 57 interrupt type and function ................................... 102 interrupt vector ............................................. 104, 105 interval timer function........................................... 200 interval timer function (timebase timer), operation of................................................ 207 L linear addressing and bank addressing ................. 28 low power consumption mode control register (LPMCR)...................................................... 86 low power consumption mode, operating state in.. 97 M machine clock ........................................................ 78 main clock mode and PLL clock mode .................. 77 master-slave communication function.................. 304 maximum rated voltage (latchup prevention), strict observation of...................................... 16 MB90M405 series features ...................................... 2 memory map .......................................................... 26 memory space ....................................................... 23 INDEX mode control register (SMR0/SMR1) ................... 275 mode data ............................................................ 150 mode data fetch ..................................................... 65 mode pin ................................................................ 64 mode pin (MD2 to MD0)....................................... 149 mode setting ........................................................ 148 multibyte data access ............................................ 33 multibyte data in RAM, storage of.......................... 32 multibyte data in stack, storage of ......................... 33 multibyte operand, storage of ................................ 32 multiple interrupt .................................................. 121 O operating mode .................................................... 148 operating status during standby mode................... 90 operation flow of extended intelligent I/O service (EI2OS) ...................................................... 134 operation in synchronous mode (operation mode 2)...................................................... 300 operation of DTP/external interrupt circuit ........... 324 operation of extended intelligent I/O service (EI2OS) ...................................................... 128 oscillation stabilization wait reset status ................ 62 oscillation stabilization wait time .............. 62, 79, 100 oscillation stabilization wait time timer function.... 207 oscillator or external clock to microcontroller, connection of ............................................... 80 output compare (one channel) ............................. 246 output compare control status register (OCS0) ... 253 output compare register (OCCP0) ....................... 252 output data register (SODR0/SODR1)................. 281 P pin after mode data being read, status of .............. 69 pin assignment......................................................... 9 pin during reset, status of....................................... 69 pin function............................................................. 10 placing flash Memory in read/reset status ........... 435 PLL clock mode ..................................................... 77 PLL clock mode, note on during operation of ........ 18 PLL clock multiplier, selection of............................ 77 port 8 configuration .............................................. 158 port 8 pin .............................................................. 158 port 8 pin, block diagram of.................................. 159 port 8 register....................................................... 159 Port 8 Register, function of .................................. 160 port 8, operation of............................................... 161 port 9 configuration .............................................. 163 port 9 pin .............................................................. 163 port 9 pin, block diagram of ..................................164 Port 9 register .......................................................164 port 9 register, function of.....................................165 port 9, operation of ...............................................166 port A configuration ..............................................168 port A pin ......................................................168, 169 port A pin, block diagram of..................................169 port A register .......................................................169 port A register, function of ....................................170 port A, operation of ...............................................172 port B configuration ..............................................174 port B pin ......................................................174, 175 port B pin, block diagram of..................................175 port B register .......................................................175 port B register, function of ....................................176 port B, operation of ...............................................178 port register ..........................................................393 port register (FLPD)..............................................393 power supply pin.....................................................17 power-on, note on...................................................16 prefix code ..............................................................52 prefix code and interrupt suppression instruction ...57 procedure for using extended intelligent I/O service (EI2OS) ..........................................135 procedure for using hardware interrupt ................119 processing for interrupt operation.........................118 processing time (one transfer time) of extended intelligent I/O service (EI2OS) ....................136 processor status (PS) configuration .......................42 product lineup ...........................................................5 program address detection control status register (PACSR)........................................417 program address detection register for upper, middle and lower part of address (PADR0/PADR1) ........................................416 program counter (PC).............................................47 R RAM area ...............................................................24 reception interrupt generation and flag set timing 286 register bank...........................................................51 register bank pointer...............................................45 register bank pointer (RP) ......................................45 relationship between mode pin and mode data....151 relationship between operation mode and power...20 release of sleep mode ............................................91 release of stop mode ..............................................94 release of timebase timer mode .............................93 request level setting register (ELVR)....................321 535 INDEX reset cause....................................................... 60, 67 reset cause and oscillation stabilization wait time .. 62 reset cause bit........................................................ 66 reset cause bit, note about..................................... 68 reset operation, overview of ................................... 64 returning from hardware interrupt.........................116 returning from software interrupt .......................... 125 ROM area............................................................... 24 ROM mirroring function selection module, block diagram of .................................................. 424 ROM mirroring function selection register (ROMM) ..................................................... 425 S sample I/O port program ......................................180 sample programs for interrupt processing............142 sector configuration.............................................. 429 segment dimmer setting register (SEGD) ............397 segment gradation display (segment dimmer) ..... 397 serial data I/O timing ............................................196 serial data register, R/W wait state of...................193 serial I/O unit, block diagram of............................ 182 serial I/O unit, interrupt function of ....................... 197 serial I/O unit, operation of ................................... 191 serial I/O unit, overview of .................................... 182 serial I/O unit, registers of .................................... 183 serial mode control status register lower (SMCR) ...................................................... 186 serial mode control status register, higher (SMCR) ...................................................... 184 serial programming (when power supplied by user), example of connection for................ 446 serial programming (when power supplied from programmer), example of connection for ... 448 serial programming connection to MB90MF408/ MF408A, standard configuration for........... 444 serial shift data register (SDR) ............................. 188 setting DTP/external interrupt circuit .................... 323 shift operation, start/stop timing of ....................... 195 single conversion mode, operation in...................372 software interrupt activation ................................. 125 software interrupt operation ................................. 126 software pull-up resistor ......................................... 98 specifying more than one sector, note on ............439 specifying sector .................................................. 439 stack area............................................................. 141 stack operation at start of interrupt processing .... 140 stack operation on return from interrupt processing.................................................. 140 stack selection........................................................ 40 536 standby mode ........................................................ 83 standby mode by interrupt, release of.................... 99 start condition....................................................... 347 start condition generation instruction while SDA=LOW and SCL=LOW, execution of .. 348 status change diagram........................................... 96 status of pin in single-chip mode............................ 98 status register (SSR0/SSR1) ............................... 277 status/authorization register (FLST)..................... 394 stop condition....................................................... 347 stop conversion mode, operation in ..................... 374 stop mode and sleep mode, operation in............. 402 stop mode by external interrupt, release of............ 99 STOP state .......................................................... 193 stopped state ....................................................... 193 STP, SLP and TMD bit, priority of.......................... 88 Structure of Instruction Map ................................ 502 supply voltage, stabilization of ............................... 16 switching to sleep mode......................................... 91 switching to standby mode and interrupt ............... 99 switching to stop mode .......................................... 94 switching to timebase timer mode.......................... 93 system configuration ............................................ 419 system stack pointer (SSP).................................... 41 T temporarily stopping sector deletion .................... 441 timebase timer control register (TBTC)................ 204 timebase timer interrupt ....................................... 206 timebase timer interrupt and EI2OS ..................... 206 timebase timer operation status........................... 209 timebase timer usage note................................... 210 timebase timer, block diagram of ......................... 202 timer control status register, higher (TMCSR) ..... 229 timer control status register, low part (TMCSR)... 231 timer counter control status register (TCCS) ....... 250 timer counter data register (TCDT) ...................... 249 transfer state ........................................................ 194 transmission interrupt output and flag set timing ......................................................... 288 treating pin when the A/D converter is not used .... 17 type of instruction................................................. 464 U UART baud rate selection.................................... 289 UART EI2OS function .......................................... 285 UART function...................................................... 264 UART interrupt ..................................................... 284 UART interrupt and EI2OS........................... 265, 285 INDEX UART pin ............................................................. 269 UART pin, block diagram of ................................. 270 UART register ...................................................... 271 UART, block diagram of....................................... 266 UART, note on using............................................ 307 UART, operation of .............................................. 296 unused input pin, treatment of ............................... 16 user stack pointer (USP)........................................ 41 W watch clock output circuit......................................404 watch clock output control register (TMCS)..........406 watch clock selection circuit, block diagram of .....405 watchdog timer control register (WDTC) ..............215 watchdog timer function........................................212 watchdog timer operation .....................................217 watchdog timer, block diagram of.........................213 watchdog timer, usage note on ............................219 writing data, note on .............................................436 537 INDEX 538 CM44-10116-3E FUJITSU MICROELECTRONICS •CONTROLLER MANUAL F2MC-16LX 16-BIT MICROCONTROLLER MB90M405 Series HARDWARE MANUAL July 2008 the third edition Published FUJITSU MICROELECTRONICS LIMITED Edited Business & Media Promotion Dept.