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FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
CM44-10117-3E
2
F MC-16LX
16-BIT MICROCONTROLLER
MB90440G Series
HARDWARE MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90440G Series
HARDWARE MANUAL
The information for microcontroller supports is shown in the following homepage.
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page
"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU MICROELECTRONICS LIMITED
PREFACE
■ Objectives and Intended Reader
Thank you for your continued use of Fujitsu microelectronics products.
The MB90440G series has been developed as a general-purpose version of the F2MC-16LX
family, which is an original 16-bit single-chip microcontroller compatible with Application Specific
ICs (ASICs).
This manual describes the functions and operation of the MB90440G series for designers who
will use the MB90440G series to design products. Read this manual before starting to design
products.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ Trademark
The company names and brand names herein are the trademarks or registered trademarks of
their respective owners.
■ Structure of This Manual
This manual has 25 chapters and an appendix:
CHAPTER 1 OVERVIEW
This chapter explains the features and basic specifications of the MB90440G series products.
CHAPTER 2 CPU
This chapter explains the CPU.
CHAPTER 3 INTERRUPTS
This chapter explains the interrupt functions and operations.
CHAPTER 4 CLOCKS
This chapter explains the clocks used by MB90440G series microcontrollers.
CHAPTER 5 LOW-POWER CONSUMPTION MODE
This chapter explains the low-power consumption mode of MB90440G series microcontrollers.
CHAPTER 6 RESETS
This chapter explains resets for the MB90440G series microcontrollers.
CHAPTER 7 MEMORY ACCESS MODES
This chapter explains the functions and operations of the memory access modes.
CHAPTER 8 I/O PORTS
This chapter explains the functions and operations of the I/O ports.
CHAPTER 9 TIME-BASE TIMER
This chapter explains the functions and operations of the time-base timer.
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CHAPTER 10 WATCHDOG TIMER
This chapter explains the functions and operations of the watchdog timer.
CHAPTER 11 WATCH TIMER
This chapter explains the functions and operations of the watch timer.
CHAPTER 12 16-BIT I/O TIMER
This chapter explains the functions and operations of the 16-bit I/O timer.
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
This chapter explains the functions and operations of the 16-bit reload timer (with the event
count function).
CHAPTER 14 8/16-BIT PPG
This chapter explains the functions and operation of the 8/16-bit PPG.
CHAPTER 15 DELAYED INTERRUPT
This chapter explains the functions and operations of the delayed interrupt.
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
This chapter explains the functions and operations of the DTP/external interrupts.
CHAPTER 17 A/D CONVERTER
This chapter explains the functions and operations of the A/D converter.
CHAPTER 18 UART0
This chapter explains the UART0 functions and operations.
CHAPTER 19 UART1 (SCI)
This chapter explains the UART1 (SCI) functions and operation.
CHAPTER 20 SERIAL I/O
This chapter explains the functions and operations of the serial I/O.
CHAPTER 21 CAN CONTROLLER
This chapter explains the functions and operations of the CAN controller.
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
This chapter explains the address match detection function and operation.
CHAPTER 23 ROM MIRRORING FUNCTION SELECTION MODULE
This chapter explains the ROM mirroring function selection module.
CHAPTER 24 1M-BIT FLASH MEMORY
This chapter explains the functions and operation of the 1M-bit flash memory.
CHAPTER 25 EXAMPLES OF MB90F443G SERIAL PROGRAMMING CONNECTION
This chapter provides examples of serial programming connection with the AF220/AF210/
AF120/AF110 flash microcontroller programmer manufactured by Yokogawa Digital Computer
Corporation.
APPENDIX
The appendix provides I/O maps and outlines instructions.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©2001-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
CHAPTER 2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.8
2.9
2.10
CPU ............................................................................................................ 19
Outline of CPU ..................................................................................................................................
Memory Space ..................................................................................................................................
Memory Space Map ..........................................................................................................................
Linear Addressing .............................................................................................................................
Bank Addressing Types ....................................................................................................................
Multi-byte Data in Memory Space .....................................................................................................
Registers ...........................................................................................................................................
Accumulator (A) ...........................................................................................................................
User Stack Pointer (USP) and System Stack Pointer (SSP) .......................................................
Processor Status (PS) .................................................................................................................
Program Counter (PC) .................................................................................................................
Register Bank ...................................................................................................................................
Prefix Codes .....................................................................................................................................
Interrupt Disable Instructions ............................................................................................................
CHAPTER 3
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.7
OVERVIEW ................................................................................................... 1
Product Overview ............................................................................................................................... 2
Features .............................................................................................................................................. 3
Block Diagram .................................................................................................................................... 5
Package Dimensions .......................................................................................................................... 6
Pin Assignment ................................................................................................................................... 7
Pin Functions ...................................................................................................................................... 8
I/O Circuits ........................................................................................................................................ 13
Handling the Device .......................................................................................................................... 16
20
21
22
23
24
26
27
30
31
32
35
36
38
41
INTERRUPTS ............................................................................................. 43
Outline of Interrupts ..........................................................................................................................
Interrupt Sources ..............................................................................................................................
Interrupt Vector .................................................................................................................................
Hardware Interrupts ..........................................................................................................................
Hardware Interrupt Operation ......................................................................................................
Flow of Hardware Interrupt Operation .........................................................................................
Software Interrupts ...........................................................................................................................
Extended Intelligent I/O Service (EI2OS) ..........................................................................................
Interrupt Control Register (ICR) ...................................................................................................
Extended Intelligent I/O Service Descriptor (ISD) .......................................................................
Operation of Extended Intelligent I/O Service (EI2OS) ................................................................
Execution Time of the Extended Intelligent I/O Service (EI2OS) .................................................
Exception Due to Execution of an Undefined Instruction ..................................................................
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49
51
53
54
56
58
61
64
66
68
CHAPTER 4
4.1
4.2
4.3
4.4
4.5
4.6
Clocks ...............................................................................................................................................
Block Diagram of the Clock Generation Block ..................................................................................
Clock Selection Register (CKSCR) ...................................................................................................
Clock Mode .......................................................................................................................................
Oscillation Stabilization Wait Interval ................................................................................................
Connection of an Oscillator or an External Clock to the Microcontroller ...........................................
CHAPTER 5
5.1
5.2
5.3
5.4
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.6
5.7
5.8
LOW-POWER CONSUMPTION MODE ..................................................... 87
RESETS .................................................................................................... 117
Resets .............................................................................................................................................
Reset Cause and Oscillation Stabilization Wait Intervals ...............................................................
External Reset Pin ..........................................................................................................................
Reset Operation ..............................................................................................................................
Reset Cause Bits ............................................................................................................................
Status of Pins in a Reset ................................................................................................................
CHAPTER 7
CHAPTER 8
118
120
122
123
125
127
MEMORY ACCESS MODES .................................................................... 129
7.1
Outline of Memory Access Modes ..................................................................................................
7.1.1
Mode Pins ..................................................................................................................................
7.1.2
Mode Data .................................................................................................................................
7.1.3
Memory Space in Each Bus Mode ............................................................................................
7.2
External Memory Access (Bus Pin Control Circuit) ........................................................................
7.2.1
External Memory Access (External Bus Pin Control Circuit) Registers .....................................
7.2.2
Automatic Ready Function Selection Register (ARSR) .............................................................
7.2.3
External Address Output Control Register (HACR) ...................................................................
7.2.4
Bus Control Signal Selection Register (ECSR) .........................................................................
7.3
External Memory Access Control Signal Operation ........................................................................
7.3.1
Ready Function .........................................................................................................................
7.3.2
Hold Function ............................................................................................................................
8.1
8.2
70
73
75
79
83
84
Overview of Low-Power Consumption Mode .................................................................................... 88
Block Diagram of the Low-Power Consumption Control Circuit ....................................................... 91
Low-Power Consumption Mode Control Register (LPMCR) ............................................................. 93
CPU Intermittent Operation Mode .................................................................................................... 96
Standby Mode ................................................................................................................................... 97
Sleep Mode ................................................................................................................................. 98
Time-Base Timer Mode ............................................................................................................. 101
Watch Mode .............................................................................................................................. 103
Stop Mode ................................................................................................................................. 106
Status Change Diagram ................................................................................................................. 109
Status of Pins in Standby Mode and during Hold and Reset .......................................................... 111
Usage Notes on Low-Power Consumption Mode ........................................................................... 114
CHAPTER 6
6.1
6.2
6.3
6.4
6.5
6.6
CLOCKS ..................................................................................................... 69
130
131
132
133
135
136
137
139
140
143
145
147
I/O PORTS ................................................................................................ 149
I/O Ports .......................................................................................................................................... 150
Input Levels of I/O Ports ................................................................................................................. 151
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8.3
I/O Port Registers ...........................................................................................................................
8.3.1
Port Data Register (PDR) ..........................................................................................................
8.3.2
Port Input Level Register (PILR) ................................................................................................
8.3.3
Port Direction Register (DDR) ...................................................................................................
8.3.4
Pull-up Control Register (PUCR) ...............................................................................................
8.3.5
Analog Input Enable Register (ADER) ......................................................................................
CHAPTER 9
9.1
9.2
9.3
152
153
154
155
156
158
TIME-BASE TIMER .................................................................................. 159
Outline of Time-base Timer ............................................................................................................ 160
Time-Base Timer Control Register (TBTC) .................................................................................... 162
Operations of Time-base Timer ...................................................................................................... 164
CHAPTER 10 WATCHDOG TIMER ................................................................................ 165
10.1
10.2
10.3
Outline of Watchdog Timer ............................................................................................................. 166
Watchdog Timer Control Register (WDTC) .................................................................................... 168
Watchdog Timer Operation ............................................................................................................. 170
CHAPTER 11 WATCH TIMER ........................................................................................ 171
11.1
11.2
11.3
Outline of Watch Timer ................................................................................................................... 172
Watch Timer Control Register (WTC) ............................................................................................. 174
Watch Timer Operation ................................................................................................................... 176
CHAPTER 12 16-BIT I/O TIMER ..................................................................................... 177
12.1 Outline of 16-Bit I/O Timer ..............................................................................................................
12.2 16-bit I/O Timer Registers ...............................................................................................................
12.3 16-bit Free-run Timer ......................................................................................................................
12.3.1 16-bit Free-run Timer Registers ................................................................................................
12.3.2 Timer Control Status Register ...................................................................................................
12.3.3 16-bit Free-run Timer Operation ................................................................................................
12.4 Output Compare .............................................................................................................................
12.4.1 Output Compare Register ..........................................................................................................
12.4.2 Control Status Register of Output Compare ..............................................................................
12.4.3 16-bit Output Compare Operation .............................................................................................
12.5 Input Capture ..................................................................................................................................
12.5.1 Input Capture Register ..............................................................................................................
12.5.2 16-bit Input Capture Operation ..................................................................................................
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180
181
182
183
186
188
189
190
193
196
198
200
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) ................ 203
13.1 Outline of 16-Bit Reload Timer (with Event Count Function) ..........................................................
13.2 16-Bit Reload Timer (with Event Count Function) ..........................................................................
13.2.1 Timer Control Status Register (TMCSR) ...................................................................................
13.2.2 Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR) ...................
13.3 Internal Clock and External Clock Operations of 16-bit Reload Timer ...........................................
13.4 Underflow Operation of 16-bit Reload Timer ..................................................................................
13.5 Output Pin Functions of 16-bit Reload Timer ..................................................................................
13.6 Counter Operation State .................................................................................................................
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206
207
210
211
213
214
215
CHAPTER 14 8/16-BIT PPG ........................................................................................... 217
14.1 Outline of 8/16-bit PPG ...................................................................................................................
14.2 Block Diagram of 8/16-bit PPG .......................................................................................................
14.3 8/16-bit PPG Registers ...................................................................................................................
14.3.1 PPG0 Operation Mode Control Register (PPGC0) ....................................................................
14.3.2 PPG1 Operation Mode Control Register (PPGC1) ....................................................................
14.3.3 PPG0/1 Clock Selection Register (PPG01) ...............................................................................
14.3.4 Reload Register (PRLL/PRLH) ..................................................................................................
14.4 Operations of 8/16-bit PPG .............................................................................................................
14.5 Selecting a Count Clock for 8/16-bit PPG .......................................................................................
14.6 Controlling Pin Output of 8/16-bit PPG Pulses ...............................................................................
14.7 8/16-bit PPG Interrupts ...................................................................................................................
14.8 Initial Values of 8/16-bit PPG Hardware .........................................................................................
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219
221
222
224
227
229
230
232
233
234
235
CHAPTER 15 DELAYED INTERRUPT ........................................................................... 237
15.1
15.2
15.3
Outline of Delayed Interrupt Module ............................................................................................... 238
Delayed Interrupt Register .............................................................................................................. 239
Delayed Interrupt Operation ........................................................................................................... 240
CHAPTER 16 DTP/EXTERNAL INTERRUPTS .............................................................. 241
16.1
16.2
16.3
16.4
16.5
Outline of DTP/External Interrupts ..................................................................................................
DTP/External Interrupt Registers ....................................................................................................
Operations of DTP/External Interrupts ............................................................................................
Switching between External Interrupt and DTP Requests ..............................................................
Notes on Using DTP/External Interrupts .........................................................................................
242
244
246
248
249
CHAPTER 17 A/D CONVERTER .................................................................................... 251
17.1 Features of A/D Converter ..............................................................................................................
17.2 Block Diagram of A/D Converter .....................................................................................................
17.3 A/D Converter Registers .................................................................................................................
17.3.1 A/D Control Status Registers (ADCS0) .....................................................................................
17.3.2 A/D Control Status Register (ADCS1) .......................................................................................
17.3.3 Data Registers (ADCR1 and ADCR0) .......................................................................................
17.4 Operations of A/D Converter ..........................................................................................................
17.5 Conversion Using EI2OS ................................................................................................................
17.5.1 Starting EI2OS in Single Mode ..................................................................................................
17.5.2 Starting EI2OS in Continuous Mode ..........................................................................................
17.5.3 Starting EI2OS in Stop Mode .....................................................................................................
17.6 Conversion Data Protection ............................................................................................................
252
254
255
256
259
262
264
266
267
269
271
273
CHAPTER 18 UART0 ...................................................................................................... 275
18.1 Feature of UART0 ...........................................................................................................................
18.2 UART0 Block Diagram ....................................................................................................................
18.3 UART0 Registers ............................................................................................................................
18.3.1 Serial Mode Control Register 0 (UMC0) ....................................................................................
18.3.2 Status Register 0 (USR0) ..........................................................................................................
18.3.3 Input Data Register 0 (UIDR0) and Output Data Register 0 (UODR0) ......................................
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276
277
278
279
281
283
18.3.4 Rate and Data Register 0 (URD0) .............................................................................................
18.4 UART0 Operation ...........................................................................................................................
18.5 Baud Rate .......................................................................................................................................
18.6 Internal and External Clock .............................................................................................................
18.7 Transfer Data Format .....................................................................................................................
18.8 Parity Bit .........................................................................................................................................
18.9 Interrupt Generation and Flag Set Timings .....................................................................................
18.9.1 Flag Set Timings for a Receive Operation (in Mode 0, 1, or 3) .................................................
18.9.2 Flag Set Timings for a Receive Operation (in Mode 2) .............................................................
18.9.3 Flag Set Timings for a Transmit Operation ................................................................................
18.9.4 Status Flag During Transmit and Receive Operation ................................................................
18.10 UART0 Application Example ..........................................................................................................
284
286
287
290
291
292
293
294
295
296
297
298
CHAPTER 19 UART1 (SCI) ............................................................................................. 301
19.1 Features of UART1 .........................................................................................................................
19.2 Block Diagram of UART1 ................................................................................................................
19.3 UART1 Registers ............................................................................................................................
19.3.1 Serial Mode Register 1 (SMR1) .................................................................................................
19.3.2 Serial Control Register 1 (SCR1) ..............................................................................................
19.3.3 Serial Input Data Register 1 (SIDR1) / Serial Output Data Register 1 (SODR1) .......................
19.3.4 Serial Status Register 1 (SSR1) ................................................................................................
19.3.5 UART1 Prescaler Control Register (U1CDCR) .........................................................................
19.4 UART1 Operating Modes and Clock Selection ...............................................................................
19.4.1 Asynchronous (Start-Stop Synchronized) Mode .......................................................................
19.4.2 CLK Synchronous Mode ............................................................................................................
19.5 UART1 Flags and Interrupt Sources ...............................................................................................
19.6 UART1 Interrupts and Flag Set Timing ...........................................................................................
19.7 Negative Clock Operation ...............................................................................................................
19.8 UART1 Sample Applications and Precautionary Information .........................................................
302
303
304
305
307
309
310
312
313
317
318
320
321
324
325
CHAPTER 20 SERIAL I/O ............................................................................................... 327
20.1 Outline of Serial I/O ........................................................................................................................
20.2 Serial I/O Registers .........................................................................................................................
20.2.1 Serial Mode Control Status Register (SMCS) ...........................................................................
20.2.2 Serial Data Register (SDR) .......................................................................................................
20.2.3 Serial I/O Prescaler (SCDCR) ...................................................................................................
20.3 Serial I/O Operation ........................................................................................................................
20.3.1 Shift Clock .................................................................................................................................
20.3.2 Serial I/O Operation ...................................................................................................................
20.3.3 Shift Operation Start/Stop Timing ..............................................................................................
20.3.4 Interrupt Function of the Serial I/O Interface .............................................................................
20.4 Negative Clock Operation ...............................................................................................................
328
330
331
335
336
337
338
339
341
344
345
CHAPTER 21 CAN CONTROLLER ................................................................................ 347
21.1
21.2
21.3
Features of CAN Controller ............................................................................................................ 348
Block Diagram of CAN Controller ................................................................................................... 349
List of Overall Control Registers ..................................................................................................... 350
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21.4 List of Message Buffers (ID Registers) ...........................................................................................
21.5 List of Message Buffers (DLC Registers and Data Registers) ........................................................
21.6 Classifying the CAN Controller Registers .......................................................................................
21.6.1 Control Status Register (CSR) ..................................................................................................
21.6.2 Bus Operation Stop Bit (HALT = 1) ...........................................................................................
21.6.3 Last Event Indicator Register (LEIR) .........................................................................................
21.6.4 Receive and Transmit Error Counters (RTEC) ..........................................................................
21.6.5 Bit Timing Register (BTR) ..........................................................................................................
21.6.6 Message Buffer Valid Register (BVALR) ...................................................................................
21.6.7 IDE register (IDER) ....................................................................................................................
21.6.8 Transmission Request Register (TREQR) ................................................................................
21.6.9 Transmission RTR Register (TRTRR) .......................................................................................
21.6.10 Remote Frame Receiving Wait Register (RFWTR) ...................................................................
21.6.11 Transmission Cancel Register (TCANR) ...................................................................................
21.6.12 Transmission Complete Register (TCR) ....................................................................................
21.6.13 Transmission Interrupt Enable Register (TIER) .........................................................................
21.6.14 Reception Complete Register (RCR) ........................................................................................
21.6.15 Remote Request Receiving Register (RRTRR) ........................................................................
21.6.16 Receive Overrun Register (ROVRR) .........................................................................................
21.6.17 Reception Interrupt Enable Register (RIER) .............................................................................
21.6.18 Acceptance Mask Select Register (AMSR) ...............................................................................
21.6.19 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) ..........................................................
21.6.20 Message Buffers ........................................................................................................................
21.6.21 ID Register x (x = 0 to 15) (IDRx) ..............................................................................................
21.6.22 DLC Register x (x = 0 to 15) (DLCRx) .......................................................................................
21.6.23 Data Register x (x = 0 to 15) (DTRx) .........................................................................................
21.7 Transmission of CAN Controller .....................................................................................................
21.8 Reception of CAN Controller ..........................................................................................................
21.9 Reception Flowchart of CAN Controller ..........................................................................................
21.10 How to Use the CAN Controller ......................................................................................................
21.11 Procedure for Transmission by Message Buffer (x) .......................................................................
21.12 Procedure for Reception by Message Buffer (x) .............................................................................
21.13 Setting Configuration of Multi-level Message Buffer .......................................................................
21.14 Setting the redirection of CAN2 RX/TX pin .....................................................................................
21.15 Precautions when Using CAN Controller ........................................................................................
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359
360
363
364
366
367
369
370
371
372
373
374
375
376
377
378
379
380
381
383
385
386
388
389
391
394
397
398
400
402
404
406
407
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ......................................... 409
22.1
22.2
22.3
22.4
Overview of the Address Match Detection Function .......................................................................
Registers of the Address Match Detection Function .......................................................................
Operation of the Address Match Detection Function ......................................................................
Example of the Address Match Detection Function ........................................................................
410
411
413
414
CHAPTER 23 ROM MIRRORING FUNCTION SELECTION MODULE .......................... 417
23.1
23.2
Outline of ROM Mirroring Function Selection Module .................................................................... 418
ROM Mirroring Function Selection Register (ROMM) .................................................................... 419
x
CHAPTER 24 1M-BIT FLASH MEMORY ........................................................................ 421
24.1 Outline of 1M-bit Flash Memory ......................................................................................................
24.2 Sector Configuration of the Flash Memory .....................................................................................
24.3 Write/Erase Modes .........................................................................................................................
24.4 Flash Memory Control Status Register (FMCS) .............................................................................
24.5 Starting the Flash Memory Automatic Algorithm ............................................................................
24.6 Confirming the Automatic Algorithm Execution State .....................................................................
24.6.1 Data Polling Flag (DQ7) ............................................................................................................
24.6.2 Toggle Bit Flag (DQ6) ................................................................................................................
24.6.3 Timing Limit Exceeded Flag (DQ5) ...........................................................................................
24.6.4 Sector Erase Timer Flag (DQ3) .................................................................................................
24.6.5 Toggle Bit-2 Flag (DQ2) ............................................................................................................
24.7 Detailed Explanation of Writing to and Erasing Flash Memory .......................................................
24.7.1 Setting The Read/Reset State ...................................................................................................
24.7.2 Writing Data ...............................................................................................................................
24.7.3 Erasing All Data (Erasing Chips) ...............................................................................................
24.7.4 Erasing Optional Data (Erasing Sectors) ...................................................................................
24.7.5 Suspending Sector Erase ..........................................................................................................
24.7.6 Restarting Sector Erase ............................................................................................................
24.8 Notes on using 1M-bit Flash Memory .............................................................................................
24.9 Flash Security Feature ....................................................................................................................
24.10 Example of Programming 1M-bit Flash Memory ............................................................................
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423
424
426
428
430
432
434
435
436
438
440
441
442
444
445
447
448
449
451
452
CHAPTER 25 EXAMPLES OF MB90F443G SERIAL PROGRAMMING CONNECTION 457
25.1
25.2
25.3
25.4
25.5
Basic Configuration of MB90F443G Serial Programming Connection ...........................................
Example of Serial Programming Connection (User Power Supply Used) ......................................
Example of Serial Programming Connection (Power Supplied from the Programmer) ..................
Example of Minimum Connection to the Flash Microcontroller Programmer
(User Power Supply Used) .............................................................................................................
Example of Minimum Connection to the Flash Microcontroller Programmer
(Power Supplied from the Programmer) .........................................................................................
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464
466
468
APPENDIX ......................................................................................................................... 471
APPENDIX A I/O Maps .............................................................................................................................
APPENDIX B Instructions ...........................................................................................................................
B.1 Instruction Types ............................................................................................................................
B.2 Addressing .....................................................................................................................................
B.3 Direct Addressing ...........................................................................................................................
B.4 Indirect Addressing ........................................................................................................................
B.5 Execution Cycle Count ...................................................................................................................
B.6 Effective address field ....................................................................................................................
B.7 How to Read the Instruction List ....................................................................................................
B.8 F2MC-16LX Instruction List ............................................................................................................
B.9 Instruction Map ...............................................................................................................................
472
481
482
483
485
491
499
502
503
506
520
INDEX................................................................................................................................... 543
xi
xii
Main changes in this edition
Page
Changes (For details, refer to main body.)
-
-
"FAR" is deleted.
(FAR/ceramic oscillators → ceramic oscillators)
-
-
The product name is changed.
(MB90443G (under development) → MB90443G)
-
-
The pin name is changed.
(TOUT → TOT)
8
CHAPTER 1 OVERVIEW
1.6 Pin Functions
"Table 1.6-1 Pin Functions" is changed.
"● Crystal oscillator circuit" is changed.
("Please ask the crystal maker to evaluate the oscillational characteristics
of the crystal and this device." is added.)
18
CHAPTER 1 OVERVIEW
1.8 Handling the Device
"● Turning-on sequence of power supply to A/D converter and analog
inputs" is changed.
("(turning on/off the analog and digital power supplies simultaneously is
acceptable) " is deleted.)
"● Notes on during operation of PLL clock mode " is changed.
"● Stabilization of power supply voltage" is added.
58
CHAPTER 3 INTERRUPTS
3.6.1 Interrupt Control Register (ICR)
"Note" under "Figure 3.6-2 Interrupt Control Register(ICR)" is changed.
("For ICS3 and ICS2, "1" is always read." is deleted.)
71
CHAPTER 4 CLOCKS
4.1 Clocks
The first line of "Note" under "● Machine clock (φ)" is changed.
(3 MHz to 5 MHz → 3 MHz to16 MHz)
75
CHAPTER 4 CLOCKS
4.3 Clock Selection Register
(CKSCR)
76
"Access of bit 15 SCM" in "Figure 4.3-1 Configuration of the Clock
Selection Register" is changed.
(R/W → R)
"Each function of bit 15 SCM and bit 14 MCM" in "Table 4.3-1 Function
Description of Each Bit of the Clock Selection Register(CKSCR)" is
changed.
("• Writing to this bit has no effect on opetion" is added.)
91
CHAPTER 5 LOW-POWER
CONSUMPTION MODE
5.2 Block Diagram of the
Low-Power Consumption
Control Circuit
"Figure 5.2-1 Block Diagram of the Low-Power Consumption Control
Circuit " is changed.
(The part related to the pins of X0, X1, X0A and X1A is changed.)
"■ Access to the Low-power Consumption Mode Control Register" is
changed.
95
CHAPTER 5 LOW-POWER
CONSUMPTION MODE
5.3 Low-Power Consumption
Mode Control Register
(LPMCR)
"Table 5.3-2 Instructions to Be Used for Switching to a Low-Power
Consumption Mode" is changed.
xiii
Page
109
110
Changes (For details, refer to main body.)
"Figure 5.6-1 Status Change Diagram" is changed.
CHAPTER 5 LOW-POWER
CONSUMPTION MODE
5.6 Status Change Diagram
"Table 5-6-1 Operation Status in Each Operating Mode" is changed.
(Time-base timer (*1) → PLL time-base timer (*1))
(Time-base timer (*2) → Main time-base timer (*2))
111
CHAPTER 5 LOW-POWER
CONSUMPTION MODE
5.7 Status of Pins in Standby
Mode and during Hold and
Reset
"Table 5.7-1 Status of Each Pin in the Single Chip Mode" is changed.
(*3: "Input disabled" means that operation of the input gate that is closest to
the pin is enabled...." → *3: During input interrupted, input is masked, and
the "L" level will be sent inwardly if CMOS is selected and "H" level will be
sent inwardly if TTL is selected.)
114
CHAPTER 5 LOW-POWER
CONSUMPTION MODE
5.8 Usage Notes on LowPower Consumption Mode
The style of "Note" in "■ Switching to a Standby Mode and Interrupt" is
changed.
CHAPTER 13 16-BIT
RELOAD TIMER (WITH
EVENT COUNT FUNCTION)
13.1 Outline of 16-Bit Reload
Timer (with Event Count
Function)
The pin name is changed.
(TOUT → TOT)
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.2 DTP/External Interrupt
Registers
"Note" is added to "■ DTP/Interrupt Enable Register (ENIR: Interrupt
Request Enable Register).
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.5 Notes on Using DTP/
External Interrupts
"● External interrupt/DTP operation procedure" is changed.
("1. Set the general-purpose I/O port shared with the pin for using the
external interrupt input as the input port." is added.)
257
CHAPTER 17 A/D CONVERTER
17.3.1 A/D Control Status
Registers (ADCS0)
The contents of "Note" are divided into 3 items. As the result, "Note" is
changed to "Notes".
325
CHAPTER 19 UART1 (SCI)
19.8 UART1 Sample Applications and Precautionary Information
"Figure 19.8-1 Sample System Configuration in Mode 1" is changed.
(SO → SOT1)
(SIN → SIN1)
204
205
244
245
249
360
362
"■ 16-bit Reload Timer" is added.
"Note" is changed to "Notes" by itemizing. in "■ DTP/Interrupt Flags (EIRR:
External Interrupt Request Register)
"● External interrupt request level" is changed.
The summary of "21.6-1 Control Status Register (CSR) is changed.
CHAPTER 21 CAN CONTROLLER
21.6.1 Control Status Register
(CSR)
"■ Control Status Register (CSR)" is changed.
("writing to this bit" and "Reading to this bit", "Note" and "Example
program" are added to [bit0] HALT: Bus operation stop bit.)
"Example program" is changed.
(for (i=0; ( i<=500 ) || ( IO_CANCT0.CSR.bit.HALT==0); i++); →
for (i=0; ( i<=500 ) && ( IO_CANCT0.CSR.bit.HALT==0); i++);)
xiv
Page
Changes (For details, refer to main body.)
363
CHAPTER 21 CAN CONTROLLER
21.6.2 Bus Operation Stop Bit
(HALT = 1)
"Note" of "■ Conditions for Canceling Bus Operation Stop (HALT=0)" is
changed.
("When write "0" to HALT during the node status is Bus Off, ensure the "1"
is written to this bit." is added.)
All the initial values of "Figure 21.6-12 Remote Frame Receiving Wait
Regiter(RFWTR) are changed from "0" to "X".
373
CHAPTER 21 CAN CONTROLLER
21.6.10 Remote Frame
Receiving Wait Register
(RFWTR)
428
CHAPTER 24 1M-BIT
FLASH MEMORY
24.5 Starting the Flash Memory Automatic Algorithm
"Summary" of "24.5 Starting the Flash Memory Automatic Algorithm" is
changed.
(Read/Reset, Write, and Chip Erase → Read/Reset, Write, Chip Erase, and
Sector Erase)
446
CHAPTER 24 1M-BIT
FLASH MEMORY
24.7.4 Erasing Optional Data
(Erasing Sectors)
"Figure 24.7-2 Example of the Flash Memory Sector Erase Procedure" is
changed.
447
CHAPTER 24 1M-BIT
FLASH MEMORY
24.7.5 Suspending Sector
Erase
"■ Suspending Erasing of Flash Memory Sectors" is changed.
( after a maximum period of 15 µs has elapsed. →
after a maximum period of 20 µs has elapsed. Sector Erase Suspend
command should be entered more than 20 µs after Sector Erase Reset Restart
command is issued.)
450
CHAPTER 24 1M-BIT
FLASH MEMORY
24.8 Notes on using 1M-bit
Flash Memory
"● Applying VID " is changed.
(Applying VID required for the sector protect operation should always be
started and terminated when the supply voltage is on. →
Applying VID required for the sector protect operation should always be
started and terminated when the power supply is ON.
458, 459
481
to
542
CHAPTER 25 EXAMPLES
OF MB90F443G SERIAL
PROGRAMMING CONNECTION
25.1 Basic Configuration of
MB90F443G Serial Programming Connection
"■ Basic Configuration of MB90F443G Serial Programming Connection" is
changed.
The pins in "Figure25.1-1 Pins Used for Fujitsu Standard Onboard Program"
are changed.
(Additional information of P00, P01, and VCC pins are changed.)
The entire part of "APPENDIX B Instructions" is changed.
APPENDIX B Instruction
The vertical lines marked in the left side of the page show the changes.
xv
xvi
CHAPTER 1
OVERVIEW
This chapter explains the features and basic
specifications of the MB90440G series products.
1.1 Product Overview
1.2 Features
1.3 Block Diagram
1.4 Package Dimensions
1.5 Pin Assignment
1.6 Pin Functions
1.7 I/O Circuits
1.8 Handling the Device
1
CHAPTER 1 OVERVIEW
1.1
Product Overview
The following table provides a quick outlook of the MB90440G Series.
■ Overview of MB90440G Series Products
Table 1.1-1 Overview
Features
MB90V440G
MB90F443G
MB90443G
F2MC-16LX CPU
CPU
On-chip PLL clock multiplier (x1, x2, x3, x4, 1/2 when PLL stop)
Minimum instruction execution time: 62.5 ns (4 MHz osc. PLL x4)
System clock
ROM capacity
External
128 Kbytes of Flash memory
128 Kbytes MASK ROM
RAM capacity
14 Kbytes
6Kbytes
6 Kbytes
Package
PGA-256
QFP100
None
-
Emulatorspecific power
supply *
*: It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.
Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details.
2
CHAPTER 1 OVERVIEW
1.2
Features
Table 1.2-1 lists the features of the MB90440G series.
■ Features
Table 1.2-1 MB90440G Features (1/2)
Function
Feature
UART0
Full duplex double buffer
Supports asynchronous/synchronous (with start/stop bit) transfer
Baud rate: 4808/5208/9615/10417/19230/38460/62500/500000bps
(asynchronous)
500k/1M/2Mbps (synchronous) at System clock = 16MHz
UART1
(SCI)
Full duplex double buffer
Asynchronous (start-stop synchronized) and CLK-synchronous communication
Baud rate: 601bps to 250kbps (asynchronous)
31.25kbps to 2Mbps (synchronous)
Serial I/O
Transfer can be started from MSB or LSB
Supports internal clock synchronized transfer and external clock synchronized
transfer
Supports positive-edge and negative-edge clock synchronization
Baud rate: 31.25k/62.5k/125k/500k/1M/2Mbps at System clock = 16MHz
A/D
Converter
10-bit or 8-bit resolution
8 input channels
Conversion time: 6.12µs (per one channel)
16-bit Reload Timer
(2 channels)
Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = System clock
frequency)
Supports External Event Count function
16-bit
I/O Timer
Signals an interrupt when overflow
Supports Timer Clear when a match with Output Compare (Channel 0)
Operation clock freq.: fsys/22, fsys/24, fsys/26, fsys/28
(fsys = System clock freq.)
16-bit
Output Compare
(4 channels)
Signals an interrupt when a match with 16-bit I/O Timer
Four 16-bit compare registers
A pair of compare registers can be used to generate an output signal
16-bit
Input Capture
(8 channels)
Rising edge, falling edge or rising & falling edge sensitive
Four 16-bit Capture registers
Signals an interrupt upon external event
3
CHAPTER 1 OVERVIEW
Table 1.2-1 MB90440G Features (2/2)
4
Function
Feature
8/16-bit
Programmable Pulse
Generator
(4 channels)
Supports 8-bit and 16-bit operation modes
Eight 8-bit reload counters
Eight 8-bit reload registers for "L" pulse width
Eight 8-bit reload registers for "H" pulse width
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or
as 8-bit prescaler plus 8-bit reload counter
4 output pins
Operation clock freq.: fsys, fsys/21, fsys/22, fsys/23, fsys/24 or
128µ[email protected]=4MHz
(fsys = System clock frequency, fosc = Oscillation clock frequency)
CAN Interface
(3 channels)
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Flexible configuration of acceptance filtering: Full bit compare / Full bit mask /
Two partial bit masks
Supports up to 1Mbps
External Interrupt
Can be programmed edge sensitive or level sensitive
External bus interface
External access using the selectable 8-bit or 16-bit bus is enabled (external bus
mode).
I/O Ports
Virtually all external pins can be used as general purpose I/O
All push-pull outputs and schmitt trigger inputs
Bit-wise programmable as input/output or peripheral signal
32 kHz sub clock
Sub clock for low-power operation
Flash Memory
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles: 10,000 times
Data retention time: 10 years
Boot block configuration
Erase can be performed on each block
Block protection by externally programmed voltage
CHAPTER 1 OVERVIEW
1.3
Block Diagram
Figure 1.3-1 shows a block diagram of the MB90440G series.
■ Block Diagram
Figure 1.3-1 Block Diagram
X0, X1
X0A, X1A
RST
Clock
Controller
16LX
CPU
I/O Timer
RAM
6K/14K
Input
Capture
8ch
IN[7:6]/OUT[3:2]
SOT0
SCK0
SIN0
UART0
Prescaler
SOT1
SCK1
SIN1
UART1
(SCI)
Internal data bus
ROM
128K/256K
Prescaler
IN[5:0]
Output
Compare
4ch
OUT[1:0]
8/16-bit
PPG
4ch
PPG[3:0]
CAN
Controller
16-bit Reload
Timer 2ch
RX[2:0]
TX[2:0]
TIN[1:0]
TOT[1:0]
Prescaler
SOT2
SCK2
SIN2
AVCC
AVSS
AN[7:0]
AVRH
AVRL
ADTG
AD[15:00]
A[23:16]
Serial I/O
External
bus
interface
10-bit
ADC 8ch
ALE
RD
WR
WRL
WRH
HRQ
HAK
RDY
CLK
External
Interrupt
8 ch
INT[7:0]
5
CHAPTER 1 OVERVIEW
1.4
Package Dimensions
Figure 1.4-1 shows the package dimensions of the FPT-100P-M06.
Note that the dimensions show below are reference dimensions.
For formal dimensions of each package, contact us.
■ FPT-100P-M06 Package Dimensions
Figure 1.4-1 FPT-100P-M06 Package Dimensions
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP100-14×20-0.65
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8˚
31
1
30
0.65(.026)
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
"A"
©2002-2008
FUJITSU MICROELECTRONICS LIMITED F100008S-c-5-6
C
2002 FUJITSU LIMITED F100008S-c-5-5
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
6
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
CHAPTER 1 OVERVIEW
1.5
Pin Assignment
Figure 1.5-1 shows the pin assignments of the FPT-100P-M06.
■ Pin Assignment
M D2
P70/ IN0
n.c.
P7 1/IN1
P7 2/IN2
P7 3/IN3
P7 4/IN4
P7 5/IN5
P7 6/OUT 2/IN 6
P7 7/OUT 3/IN 7
P8 0/PPG0
P8 1/PPG1
P8 2/PPG2
P8 3/PPG3
P8 4/OUT 0
P8 5/OUT 1
P8 6/TI N1
P8 7/TOT1
P9 0/INT 0
P9 1/INT 1
P9 2/TX 2
P9 3/RX2
P9 4/TX 0
P9 5/INT 2//R X0
P9 6/TX 1
P9 7/RX1
R ST
PA0 /INT 3
X1 A
X0 A
Figure 1.5-1 Pin Assignment of FPT-100P-M06
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
Vss
81
50
MD1
X0
82
49
MD0
X1
83
48
P57/TOT0
Vcc
84
47
P56/TIN0
46
P67/AN7
45
P66/AN6
44
P65/AN5
43
P64/AN4
42
Vss
MB90440G series
P00/AD00
85
P01/AD01
86
P02/AD02
87
P03/AD03
88
P04/AD04
89
P05/AD05
90
41
P63/AN3
P06/AD06
91
40
P62/AN2
P07/AD07
92
39
P61/AN1
P10/AD08
93
38
P60/AN0
P11/AD09
94
37
AVss
P12/AD10
95
36
AVR-
P13/AD11
96
35
AVR+
P14/AD12
97
34
AVcc
P15/AD13
98
33
P55/ADTG
P16/AD14
99
32
P54/INT7
P17/AD15
100
31
P53/INT6
QFP - 100
P52/IN T5
P51/IN T4
P50 /SIN2
C
P30/ALE
P47 /SCK2
P27/A23
P46 /SOT 2
P26/A22
P45 /SOT 1
P25/A21
Vcc
P24/A20
P44 /SCK1
P23/A19
P43 /SIN1
P22/A18
P42 /SIN0
P21/A17
P41 /SCK0
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P40 /SOT 0
8
P37 /CLK
7
P36/R DY
6
P3 5/HAK
5
P34 /HR Q
4
P32/WR L/WR
P33/W RH
3
Vss
2
P31/ RD
1
P20/A16
Package code (mold)
FPT-100P-M06
7
CHAPTER 1 OVERVIEW
1.6
Pin Functions
Table 1.6-1 lists pin names, circuit types, and pin functions.
■ Pin Functions
Table 1.6-1 Pin Functions (1/5)
No.
Pin name
82
X0
83
X1
80
X0A
79
Circuit type
A
(Oscillation)
Pins for high-speed oscillation
X1A
A
(Oscillation)
Pins for low-speed oscillation. If no oscillator is connected, apply pulldown processing to the X0A pin and leave the X1A pin open.
77
RST
B
External reset request input
52
n.c.
--
not connected
General I/O port with programmable pull-up. This function is enabled in
the single-chip mode.
P00 to P07
85 to 92
H
AD00 to AD07
I/O pins for 8 lower bits of the external address/data bus. This function is
enabled when the external bus is enabled.
P10 to P17
General I/O port with programmable pull-up. This function is enabled in
the single-chip mode.
93 to 100
H
AD08 to AD15
I/O pins for 8 higher bits of the external address/data bus. This function is
enabled when the external bus is enabled.
P20 to P27
General I/O port with programmable pull-up. Functions as the generalpurpose input/output port in the external bus mode if the bit corresponding
to external address output control register (HACR) is set to "1".
1 to 8
H
A16 to A23
Output pins for A16 to A23 of the external address bus. Functions as the
output pin of anaddress in the external bus mode if the bit corresponding
to external address output control register (HACR) is set to "0".
P30
General I/O port with programmable pull-up. This function is enabled in
the single-chip mode.
9
H
ALE
Address latch enable output pin. This function is enabled when the
external bus is enabled.
P31
General I/O port with programmable pull-up. This function is enabled in
the single-chip mode.
10
H
RD
8
Function
Read strobe output pin for the data bus. This function is enabled when the
external bus is enabled.
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Functions (2/5)
No.
Pin name
Circuit type
General I/O port with programmable pull-up. This function is enabled in
the single-chip mode or when the WR/WRL pin output is disabled.
P32
12
WRL
H
WR
Write strobe output pin for the data bus. This function is enabled when
both the external bus and the WR/WRL pin output are enabled. WRL is
used to write-strobe 8 lower bits of the data bus in 16-bit access while WR
is used to write-strobe 8 bits of the data bus in 8-bit access.
General I/O port with programmable pull-up. This function is enabled in
the single-chip mode or external bus 8-bit mode or when WRH pin output
is disabled.
P33
13
Function
H
WRH
Write strobe output pin for the 8 higher bits of the data bus. This function
is enabled when the external bus is enabled, when the external bus 16-bit
mode is selected, and when the WRH output pin is enabled.
P34
General I/O port with programmable pull-up. This function is enabled in
the single-chip mode or when hold function is disabled.
14
H
HRQ
Hold request input pin. This function is enabled when both the external
bus and the hold function are enabled.
P35
General I/O port with programmable pull-up. This function is enabled in
the single-chip mode or when hold function is disabled.
15
H
HAK
Hold acknowledge output pin. This function is enabled when both the
external bus and the hold function are enabled.
P36
General I/O port with programmable pull-up. This function is enabled in
the single-chip mode or when the external ready function is disabled.
16
H
RDY
Ready input pin. This function is enabled when both the external bus and
the external ready function are enabled.
P37
General I/O port with programmable pull-up. This function is enabled in
the single-chip mode or when the clock output is disabled.
17
H
CLK
CLK output pin. This function is enabled when both the external bus and
CLK output are enabled.
P40
General I/O port. This function is enabled when UART0 disables serial
data output.
18
G
SOT0
Serial data output pin for UART0. This function is enabled when UART0
enables serial data output.
P41
General I/O port. This function is enabled when UART0 disables clock
output.
19
G
SCK0
Clock I/O pin for UART0. This function is enabled when UART0 enables
clock output.
P42
General I/O port. This function is always enabled.
20
G
SIN0
Serial data input pin for UART0. See the corresponding DDR register to
input if this function is used.
9
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Functions (3/5)
No.
Pin name
Circuit type
P43
21
General I/O port. This function is always enabled.
G
SIN1
Serial data input pin for UART1. See the corresponding DDR register to
input if this function is used.
P44
General I/O port. This function is enabled when UART1 disables clock
output.
22
G
SCK1
Clock pulse input/output pin for UART1. This function is enabled when
UART1 enables clock output.
P45
General I/O port. This function is enabled when UART1 disables serial
data output.
24
G
SOT1
Serial data output pin for UART1. This function is enabled when UART1
enables serial data output.
P46
General I/O port. This function is enabled when the Serial I/O disables
serial data output.
25
G
SOT2
Serial data output pin for the Serial I/O. This function is enabled when the
Serial I/O enables serial data output.
P47
General I/O port. This function is enabled when the Serial I/O disables
clock output.
26
G
SCK2
Clock pulse input/output pin for the Serial I/O. This function is enabled
when the Serial I/O enables clock output.
P50
General I/O port. This function is always enabled.
28
D
SIN2
Serial data input pin for the Serial I/O. See the corresponding DDR
register to input if this function is used.
P51 to P54
General I/O port. This function is always enabled.
29 to 32
D
INT4 to INT7
External interrupt request input pins for INT4 to INT7. See the
corresponding DDR register to input if this function is used.
P55
General I/O port. This function is always enabled.
33
D
ADTG
Trigger input pin for the A/D converter. See the corresponding DDR
register to input if this function is used.
P60 to P63
General I/O port. The function is enabled when the analog input enable
register specifies port.
38 to 41
E
AN0 to AN3
Analog input pins for the A/D converter. This function is enabled when
the analog input enable register specifies AD.
P64 to P67
General I/O port. The function is enabled when the analog input enable
register specifies port.
43 to 46
E
AN4 to AN7
Analog input pins for the A/D converter. This function is enabled when
the analog input enable register specifies AD.
P56
General I/O port. This function is always enabled.
47
D
TIN0
10
Function
Event input pin for the reload timers 0. See the corresponding DDR
register to input if this function is used.
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Functions (4/5)
No.
Pin name
Circuit type
General I/O port. This function is enabled when the reload
timers 0 disables output.
P57
48
D
TOT0
Output pin for the reload timers 0. This function is enabled when the
reload timers 0 enables output.
P70 to P75
General I/O ports. This function is always enabled.
53 to 58
59, 60
Function
D
IN0 to IN5
Data sample input pins for input captures ICU0 to ICU5. See the
corresponding DDR register to input if this function is used.
P76, P77
General I/O ports. This function is enabled when the OCU disables
waveform output.
OUT2, OUT3
D
Waveform output pins for output compares OCU2 and OCU3. This
function is enabled when the OCU enables waveform output.
IN6, IN7
Data sample input pin for input captures ICU6 and ICU7. See the
corresponding DDR register to input and disable the OCU waveform
output if this function is used.
P80 to P83
General I/O ports. This function is enabled when PPG disables waveform
output.
61 to 64
D
PPG0 to PPG3
Output pins for PPGs. This function is enabled when PPG enables
waveform output.
P84, P85
General I/O ports. This function is enabled when the OCU disables
waveform output.
65, 66
D
OUT0, OUT1
Waveform output pins for output compares OCU0 and OCU1. This
function is enabled when the OCU enables waveform output.
P86
General I/O port. This function is always enabled.
67
D
TIN1
Event input pin for the reload timers 1. See the corresponding DDR
register to input if this function is used.
P87
General I/O port. This function is enabled when the reload
timers 0 disables output.
68
D
TOT1
Output pin for the reload timers 1 This function is enabled when the
reload timers 1 enables output.
P90, P91
General I/O port. This function is always enabled.
69, 70
D
INT0, INT1
External interrupt request input pins for INT0 and INT1. See the
corresponding DDR register to input if this function is used.
P92
General I/O port. This function is enabled when CAN2 disables output.
71
D
TX2
TX Output pin for CAN2. This function is enabled when CAN2 enables
output.
P93
General I/O port. This function is always enabled.
72
D
RX2
RX input pin for CAN2 Interface. When the CAN function is used, output
from the other functions must be stopped.
11
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Functions (5/5)
No.
Pin name
Circuit type
P94
73
74
Function
General I/O port. This function is enabled when CAN0 disables output.
D
TX0
TX Output pin for CAN0. This function is enabled when CAN0 enables
output.
P95
General I/O port. This function is always enabled.
RX0
D
RX input pin for CAN0 Interface. When the CAN function is used, output
from the other functions must be stopped.
INT2
External interrupt request input pins for INT2. See the corresponding
DDR register to input if this function is used.
P96
General I/O port. This function is enabled when CAN1 disables output.
75
D
TX1
TX Output pin for CAN1. This function is enabled when CAN1 enables
output.
P97
General I/O port. This function is always enabled.
76
D
RX1
RX input pin for CAN1 Interface. When the CAN function is used, output
from the other functions must be stopped.
PA0
General I/O port. This function is always enabled.
78
D
INT3
External interrupt request input pins for INT3. See the corresponding
DDR register to input if this function is used.
34
AVCC
Power
supply
Power supply for the A/D Converter. This power supply must be turned on
or off while a voltage higher than or equal to AVCC is applied to VCC.
37
AVSS
Power
supply
Dedicated ground pin for the A/D Converter
35
AVR+
Power
supply
Reference voltage input for the A/D Converter. This power supply must be
turned on or off while a voltage higher than or equal to AVR+ is applied to
AVCC.
36
AVR-
Power
supply
Lower reference voltage input for the A/D Converter
49
MD0
C
Input pins for specifying the operating mode. The pins must be directly
connected to VCC or VSS.
50
MD1
51
MD2
F
Input pin for specifying the operating mode. The pin must be directly
connected to VCC or VSS.
27
C
--
This is the power supply stabilization capacitor pin. It should be
connected externally to a 0.1 µF ceramic capacitor.
23, 84
VCC
Power
supply
Power supply for digital circuits
11, 42, 81
VSS
Power
supply
Ground for digital circuits
12
CHAPTER 1 OVERVIEW
1.7
I/O Circuits
Table 1.7-1 shows input/output circuits.
■ I/O Circuits
Table 1.7-1 I/O Circuits (1/3)
Circuit type
Diagram
Remarks
A
• Oscillation feedback resistor:
1 MΩ approx. (High speed oscillator)
10 MΩ approx. (Low speed oscillator)
X1, X1A
Clock
pulse
input
X0, X0A
HARD, SOFT
STANDBY
CONTROL
B
• Hysteresis input.
Pull-up resistor: 50 KΩ approx.
R (pull-up)
R
HYS
C
• Hysteresis input.
R
HYS
13
CHAPTER 1 OVERVIEW
Table 1.7-1 I/O Circuits (2/3)
Circuit type
Diagram
Remarks
D
• CMOS output
• Automotive input
• CMOS input
P-ch
N-ch
R
CMOS HYS
R
AUTOM. HYS
E
•
•
•
•
P-ch
CMOS output
Automotive input
CMOS input
Analog input
N-ch
P-ch
Analog input
N-ch
R
CMOS HYS
R
AUTOM. HYS
F
R
R (pull-down)
14
HYS
• Hysteresis input
• Pull-down resistor: 50 KΩ approx.
(except FLASH devices)
CHAPTER 1 OVERVIEW
Table 1.7-1 I/O Circuits (3/3)
Circuit type
Diagram
Remarks
G
P-ch
•
•
•
•
CMOS output
Automotive input
CMOS input
TTL input (FLASH devices in flash write
mode only)
•
•
•
•
CMOS output
Hysteresis input
TTL input
Programmable pull-up resistor:
50 KΩ approx.
N-ch
R
CMOS HYS
R
AUTOM. HYS
R
TTL
T
H
CNTL
P-ch
N-ch
R
HYS
R
TTL
T
15
CHAPTER 1 OVERVIEW
1.8
Handling the Device
When handling devices, be careful about the following:
• Preventing latch-up
• Treatment of unused pins
• Using external clock
• Notes to follow in cases when sub clock mode is not used
• Power supply pins (VCC/VSS)
•
•
•
•
•
•
•
•
•
•
Pull-up/down resistors
Crystal oscillator circuit
Turning-on sequence of power supply to A/D converter and analog inputs
Connection of unused pins of A/D converter
N.C. pin
Notes on energization
Initialization
Using REALOS
Notes on during operation of PLL clock mode
Stabilization of Power supply voltage
■ Handling the Device
● Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin.
• A voltage higher than the rated voltage is applied between VCC and VSS.
• The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not let the analog power-supply voltage (AVCC, AVRH) exceed the
digital power-supply voltage.
● Treatment of unused pins
Unused input pins left open may cause abnormal operation, or latch-up leading to permanent damage.
Unused input pins should be pulled down through at least 2kΩ resistance.
Unused input/output pins may be left open in output state, but if such pins are in input state they should be
handled in the same way as input pins.
16
CHAPTER 1 OVERVIEW
● Using external clock
To use external clock, drive X0 pin only and leave X1 pin open.
Below is a diagram of how to use external clock.
Figure 1.8-1 Example of Using External Clock
MB90440G series
X0
Open
X1
● Notes to follow in cases when sub clock mode is not used
If no oscillator is connected to the X0A and X1A pins, apply pull-down processing to the X0A pin and
leave the X1A pin open.
● Power supply pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the
device to avoid abnormal operations including latch-up. However connect the pins to external power and
ground line to lower the electro-magnetic emission level, to prevent abnormal operation of signals caused
by the rise in the ground level, and to conform to the total current rating.
Make sure to connect VCC and VSS pins via the lowest impedance to power lines.
It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pins near the
device.
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90440G
Series
Vcc
Vss
Vss
Vcc
17
CHAPTER 1 OVERVIEW
● Pull-up/down resistors
The MB90440G Series does not support internal pull-up/down resistors (except Port0 to Port3:pull-up
resistors). Use external components where needed.
● Crystal oscillator circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via the shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground
lines, and make sure, to the utmost effort, that lines of oscillation circuits do not cross the lines of other
circuits.
It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a
ground area for stabilizing the operation.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
● Turning-on sequence of power supply to A/D converter and analog inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to
AN7) after turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make
sure that the voltage does not exceed AVRH or AVCC.
● Connection of unused pins of A/D converter
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.
● N.C. Pin
The N.C. (internally connected) pin must be opened for use.
● Notes on energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization
at 50 µs or more (0.2 V to 2.7 V).
● Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these
registers, please turn on the power again.
● Using REALOS
The use of (EI2OS) is not possible with the REALOS real time operating system.
● Notes on during operation of PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops
while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its
operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such
failure occurs.
● Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation assurance range of the VCC power
supply voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized.
As stabilization guidelines, stabilize the power supply voltage so that VCC ripple fluctuations (peak to peak
value) in the commercial frequencies (50Hz to 60 Hz) fall within 10% of the standard VCC power supply
voltage and the transient fluctuation rate becomes 0.1V/ms or less in instantaneous fluctuation for power
supply switching.
18
CHAPTER 2
CPU
This chapter explains the CPU.
2.1 Outline of CPU
2.2 Memory Space
2.3 Memory Space Map
2.4 Linear Addressing
2.5 Bank Addressing Types
2.6 Multi-byte Data in Memory Space
2.7 Registers
2.8 Register Bank
2.9 Prefix Codes
2.10 Interrupt Disable Instructions
19
CHAPTER 2 CPU
2.1
Outline of CPU
The F2MC-16LX CPU core is a 16-bit CPU designed for applications that require highspeed real-time processing, such as home-use or vehicle-mounted electronic
appliances. The F2MC-16LX instruction set is designed for controller applications, and
is capable of high-speed, highly efficient control processing.
■ Outline of CPU
In addition to 16-bit data, the F2MC-16LX CPU core can process 32-bit data by using an internal 32-bit
accumulator (32-bit data can be processed by some instructions). Memory space of up to 16 megabytes
(expandable) can be accessed by either the linear or bank method. The instruction set, based on the F2MC8L A-T architecture, has been made richer by adding instructions that are compatible with high-level
languages, expanding addressing modes, improving the multiplication and division instructions, and
enhancing bit processing.
The features of the F2MC-16LX CPU are explained below.
● Minimum instruction execution time: 62.5 ns (at 4-MHz oscillation, 4 times clock multiplication)
● Maximum memory space: 16 Mbytes, accessed in linear or bank mode
● Instruction set optimized for controller applications
• Rich data types: Bit, byte, word, long word
• Extended addressing modes: 23 types
• High-precision operation (32-bit length) based on 32-bit accumulator
● Powerful interrupt functions
Eight priority levels (programmable)
● CPU-independent automatic transfer
Up to 16 channels of the extended intelligent I/O service
● Instruction set compatible with high-level language (C)/multitasking
System stack pointer/instruction set symmetry/barrel-shift instructions
● Improved execution speed: 4-byte queue
20
CHAPTER 2 CPU
2.2
Memory Space
An F2MC-16LX CPU has a 16-megabyte memory space. All data items, programs, and
input-outputs managed by F2MC-16LX CPU are located in this 16-megabyte memory
space. The CPU can access resources by indicating their addresses using a 24-bit
address bus.
■ Outline of CPU Memory Space
Figure 2.2-1 shows a sample relationship between the F2MC-16LX system and memory map.
Figure 2.2-1 Sample Relationship between F2MC-16LX System and Memory Map
Program
FFFFFF H
FF8000H
Data
810000H
Interrupt
800000H
F2MC-16LX
CPU
Program area
Data area
Peripheral
circuits
[Device]
Generalpurpose ports
0000C0H
0000B0 H
000020H
Interrupt controller
Peripheral circuits
General-purpose ports
000000H
■ Address Generation Types
The F2MC-16LX has the following two addressing:
● Linear addressing
An entire 24-bit address is specified by an instruction.
● Bank addressing
The eight high-order bits of an address are specified by an appropriate bank register, and the remaining 16
low-order bits are specified by an instruction.
21
CHAPTER 2 CPU
2.3
Memory Space Map
The memory space of the MB90440G Series is shown in Figure 2.3-1 .
■ Memory Space Map
The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C
compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without
using the far specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF4000H and FFFFFFH is visible in bank 00, while the image between FF0000H and
FF3FFFH is visible only in bank FF.
Figure 2.3-1 Memory Space Map
MB90F443G
MB90443G
MB90V440G
FFFFFFH
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
ROM (FF bank)
ROM (FE bank)
FF0000H
FEFFFFH
FE0000H
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
External
ROM (FC bank)
External
00FFFFH
004000H
003FFFH
ROM (Image of
FF bank)
00FFFFH
004000H
003FFFH
Peripheral
Peripheral
003900H
003900H
001FF5H
001FF0H
002000H
ROM correction
RAM 6K
000100H
000100H
External
External
22
External
0018FFH
RAM 14K
0000BFH
000000H
ROM (Image of
FF bank)
Peripheral
0000BFH
000000H
Peripheral
CHAPTER 2 CPU
2.4
Linear Addressing
There are two types of linear addressing:
• 24-bit operand specification: Directly specifies a 24-bit address using operands.
• 32-bit register indirect specification: Indirectly specifies the 24 low-order bits of a 32bit general-purpose register value as the address.
■ 24-bit Operand Specification
Figure 2.4-1 shows an example of 24-bit operand specification. Figure 2.4-2 shows an example of 32-bit
register indirect specification.
Figure 2.4-1 Example of Linear Method (24-bit Register Operand Specification)
JMPP 123456H
Old program counter
+ program bank
17
17452D H
452D
JMPP 123456H
123456 H
New program counter
+ program bank
12
Next instruction
3456
■ 32-bit Register Indirect Specification
Figure 2.4-2 Example of Linear Method (32-bit Register Indirect Specification)
MOV A, @RL1+7
Old AL
090700 H
XXXX
3A
+7
RL1
240906F9
(The high-order eight bits are ignored.)
New AL
003A
23
CHAPTER 2 CPU
2.5
Bank Addressing Types
In the bank method, the 16-Mbyte space is divided into 256 64Kbyte banks. The
following five bank registers are used to specify the banks corresponding to each
space:
• Program counter bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional data bank register (ADB)
■ Bank Addressing Types
● Program counter bank register (PCB)
The 64Kbyte bank specified by the PCB is called a program (PC) space. The PC space contains instruction
codes, vector tables, and immediate value data, for example.
● Data bank register (DTB)
The 64Kbyte bank specified by the DTB is called a data (DT) space. The DT space contains readable/
writable data, and control/data registers for internal and external resources.
● User stack bank register (USB)/system stack bank register (SSB)
The 64Kbyte bank specified by the USP or SSP is called a stack (SP) space. The SP space is accessed when
a stack access occurs during a push/pop instruction or interrupt register saving. The S flag in the condition
code register determines the stack space to be accessed.
● Additional data bank register (ADB)
The 64Kbyte bank specified by the ADB is called an additional (AD) space. The AD space, for example,
contains data that cannot fit into the DT space.
Table 2.5-1 lists the default spaces used in each addressing mode, which are pre-determined to improve
instruction coding efficiency. To use a non-default space for an addressing mode, specify a prefix code
corresponding to a bank before the instruction. This enables access to the bank space corresponding to the
specified prefix code.
After reset, the DTB, USB, SSB, and ADB are initialized to "00H". The PCB is initialized to a value
specified by the reset vector. After reset, the DT, SP, and AD spaces are allocated in bank 00 (000000H to
00FFFFH), and the PC space is allocated in the bank specified by the reset vector.
24
CHAPTER 2 CPU
Table 2.5-1 Default Space
Default space
Program space
Addressing mode
PC indirect, program access, branch
Data space
Addressing mode using @RW0, @RW1, @RW4, or @RW5, @A, addr16, and dir
Stack space
Addressing mode using PUSHW, POPW, @RW3, or @RW7
Additional space
Addressing mode using @RW2 or @RW6
Figure 2.5-1 is an example of a memory space divided into register banks.
Figure 2.5-1 Physical Addresses of Each Space
FFFFFF H
Program space
FF0000 H
FF H
:
PCB (Program counter bank register)
B3 H
: ADB (Additional data bank register)
92 H
: USB (User stack bank register)
68 H
: DTB (Data bank register)
4B H
: SSB (System stack bank register)
B3FFFF H
Additional space
Physical address
B30000 H
92FFFF H
User stack space
920000 H
68FFFF H
680000 H
Data space
4BFFFF H
System stack space
4B0000 H
000000 H
25
CHAPTER 2 CPU
2.6
Multi-byte Data in Memory Space
Data is written to memory from the low-order addresses. Therefore, for a 32-bit data
item, the low-order 16 bits are transferred before the high-order 16 bits.
If a reset signal is input immediately after the low-order bits are written, the high-order
bits might not be written.
■ Multi-byte Data Allocation in Memory Space
Figure 2.6-1 is a diagram of multi-byte data configuration in memory. The low-order eight bits of a data
item are stored at address n, then address n+1, address n+2, address n+3, etc.
Figure 2.6-1 Sample Allocation of Multi-byte Data in Memory
MSB
H
01010101
LSB
11001100
11111111
00010100
01010101
11001100
11111111
Address n
00010100
L
■ Accessing Multi-byte Data
Fundamentally, accesses are made within a bank. For an instruction accessing a multi-byte data item,
address FFFFH is followed by address 0000H of the same bank. Figure 2.6-2 is an example of an instruction
accessing multi-byte data.
Figure 2.6-2 Execution of MOVW A, 080FFFFH
H
80FFFF H
AL before execution
??
AL after execution
23 H
??
01H
·
·
·
23 H
800000 H
L
26
01H
CHAPTER 2 CPU
2.7
Registers
The F2MC-16LX registers are largely classified into two types: special registers in the
CPU and general-purpose registers in memory. The special registers are dedicated
internal hardware of the CPU, and they have specific use defined by the CPU
architecture. The general-purpose registers share the CPU address space with RAM.
The general-purpose registers are the same as the special registers in that they can be
accessed without using an address. The applications of the general-purpose registers
can be specified by the user however, as is ordinary memory space.
■ Special Registers
The F2MC-16LX CPU core has the following 13 special registers:
• Accumulator (A=AH:AL):
Two 16-bit accumulators
(Can be used as a single 32-bit accumulator.)
• User stack pointer (USP):
16-bit pointer indicating the user stack area
• System stack pointer (SSP):
16-bit pointer indicating the system stack area
• Processor status (PS):
16-bit register indicating the system status
• Program counter (PC):
16-bit register holding the address of the program
• Program counter bank register (PCB): 8-bit register indicating the PC space
• Data bank register (DTB):
8-bit register indicating the DT space
• User stack bank register (USB):
8-bit register indicating the user stack space
• System stack bank register (SSB):
8-bit register indicating the system stack space
• Additional data bank register (ADB):
8-bit register indicating the AD space
• Direct page register (DPR):
8-bit register indicating a direct page
27
CHAPTER 2 CPU
Figure 2.7-1 is a diagram of the special registers.
Figure 2.7-1 Special Registers
AH
AL
Accumulator
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
DPR
Direct page register
PCB
Program counter bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8 bit
16 bit
32 bit
28
CHAPTER 2 CPU
■ General-purpose Registers
The F2MC-16LX general-purpose registers are located from addresses 000180H to 00037FH (maximum
configuration) of main storage. The register bank pointer (RP) indicates which of the above addresses are
currently being used as a register bank. Each bank has the following three types of registers. These registers
are mutually dependent as described in Figure 2.7-2 .
• R0 to R7:
8-bit general-purpose register
• RW0 to RW7: 16-bit general-purpose register
• RL0 to RL3:
32-bit general-purpose register
Figure 2.7-2 General-purpose Registers
MSB
LSB
16 bit
000180 H + RP×10H
RW0
Low-order
RL0
First address of
general-purpose register
RW1
RW2
RL1
RW3
R1
R0
RW4
R3
R2
RW5
R5
R4
RW6
R7
R6
RW7
RL2
RL3
High-order
The relationship between the high-order and low-order bytes of a byte or word register is expressed as
follows:
RW (i+4) = R (i*2+1)× 256+R (i*2) [i=0 to 3]
The relationship between the high-order and low-order bytes of RLi and RW can be expressed as follows:
RL (i) = RW (i*2+1)× 65536+RW (i*2) [i=0 to 3]
29
CHAPTER 2 CPU
2.7.1
Accumulator (A)
The accumulator (A) register consists of two 16-bit arithmetic operation registers (AH
and AL), and is used as a temporary storage for operation results and transfer data.
■ Accumulator (A)
In 32-bit data processing, AH and AL are used together. Only AL is used for word processing in 16-bit data
processing mode or for byte processing in 8-bit data processing mode (see Figure 2.7-3 and Figure 2.7-4 ).
The data in the A register can be operated upon with data in memory or with registers (Ri, RWi, or RLi).
As with the F2MC-8L, when a word or shorter data item is transferred to AL, the previous data item in AL
is automatically transferred to AH (data save function). The data save function and the operations between
AL and AH help to improve processing efficiency.
When a byte or shorter data item is transferred to AL, the data is sign-extended or zero-extended and stored
as a 16-bit data item in AL. The data in AL can be handled either as word or byte long.
When a byte-processing arithmetic operation instruction is executed on AL, the high-order eight bits of AL
before operation are ignored. The high-order eight bits of the operation result all become zeroes.
The A register is not initialized by a reset. The A register holds an undefined value immediately after a
reset.
Figure 2.7-3 32-bit Data Transfer
MOVL A,@R W1+6
(Instruction that performs a long-word-length read using the result of
RW1 + an 8-bit offset as the address and stores the read value in the A register)
Memory space
MSB
Old A
XXXX H
XXXX H
DTB
New A
8F74 H
A6 H
LSB
A61540 H
8FH
74H
A6153E H
2B H
52H
15H
38H
+6
2B52 H
RW1
AHAL
Figure 2.7-4 AL-AH Transfer
(Instruction that performs a word-length read using the result of RW1 + an
8-bit offset as the address and stores the read value in the A register)
MOVW A,@R W1+6
MSB
Old A
XXXX H
1234 H
DTB
A6 H
Memory space
LSB
A61540 H
8F H
74 H
A6153E H
2B H
52 H
15 H
38 H
+6
New A
30
1234H
1234 H
RW1
CHAPTER 2 CPU
2.7.2
User Stack Pointer (USP) and System Stack Pointer
(SSP)
USP and SSP are 16-bit registers that indicate the memory addresses for saving and
restoring data when a push/pop instruction or subroutine is executed.
■ User Stack Pointer (USP) and System Stack Pointer (SSP)
USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data in the
event of a push/pop instruction or subroutine execution. The USP and SSP registers are used by stack
instructions. The USP register is enabled when the S flag in the processor status register is "0", and the SSP
register is enabled when the S flag is "1" (see Figure 2.7-5 ). Since the S flag is set when an interrupt is
accepted, register values are always saved in the memory area indicated by SSP during interrupt
processing. SSP is used for stack processing in an interrupt routine, while USP is used for stack processing
outside an interrupt routine. If the stack space is not divided, use only the SSP.
During stack processing, the high-order eight bits of an address are indicated by SSB (for SSP) or USB (for
USP). USP and SSP are not initialized by a reset. Instead, they hold undefined values.
Figure 2.7-5 Stack Manipulation Instruction and Stack Pointer
Example 1 PUSHW A when the S flag is "0"
Before execution
AL
S flag
After execution
AL
S flag
MSB
C6F326 H
LSB
A624 H
USB
C6 H
USP
F328 H
0
SSB
56 H
SSP
1234 H
A624 H
USB
C6 H
USP
F326 H
0
SSB
56 H
SSP
1234 H
C6F326 H
A6 H
24 H
A624 H
USB
C6 H
USP
F328 H
561232 H
XX
XX
1
SSB
56 H
SSP
1234 H
A624 H
USB
C6 H
USP
F328 H
561232 H
A6 H
24 H
1
SSB
56 H
SSP
1232 H
XX
XX
User stack is used because
the S flag is "0".
Example 2 PUSHW A when the S flag is "1"
Before execution
AL
S flag
After execution
AL
S flag
System stack is used because
the S flag is "1".
Note:
Specify an even-numbered address in the stack pointer whenever possible.
31
CHAPTER 2 CPU
2.7.3
Processor Status (PS)
The PS register consists of the bits controlling the CPU Operation and the bits
indicating the CPU status.
■ Processor Status (PS)
As shown in Figure 2.7-6 , the high-order byte of the PS register consists of a register bank pointer (RP)
and an interrupt level mask register (ILM). The RP indicates the start address of a register bank. The loworder byte of the PS register is a condition code register (CCR), containing the flags to be set or reset
depending on the results of instruction execution or interrupt occurrences.
Figure 2.7-6 Processor Status (PS) Structure
13 12
bit 15
8
PS
ILM
RP
Initial value
000
00000
0
7
CCR
-01XXXXX
X:Undefined
■ Condition Code Register (CCR)
Figure 2.7-7 is a diagram of condition code register configuration.
Figure 2.7-7 Condition Code Register (CCR) Configuration
bit
Initial value
7
6
5
4
3
2
1
0
-
I
S
T
N
Z
V
C
: CCR
-
0
1
X
X
X
X
X
X: Undefined
● I: Interrupt enable flag:
Interrupts other than software interrupts are enabled when the I flag is "1" and are masked when the I flag is
"0". The I flag is cleared by a reset.
● S: Stack flag:
When the S flag is "0", USP is enabled as the stack manipulation pointer.
When the S flag is "1", SSP is enabled as the stack manipulation pointer.
The S flag is set by an interrupt reception or a reset.
● T: Sticky bit flag:
"1" is set in the T flag when there is at least one "1" in the data shifted out from the carry after execution of
a logical right/arithmetic right shift instruction. Otherwise, "0" is set in the T flag. In addition, "0" is set in
the T flag when the shift amount is zero.
● N: Negative flag:
The N flag is set when the MSB of the operation result is "1", and is otherwise cleared.
32
CHAPTER 2 CPU
● Z: Zero flag:
The Z flag is set when the operation result is all zeroes, and is otherwise cleared.
● V: Overflow flag:
The V flag is set when an overflow of a signed value occurs as a result of operation execution and is
otherwise cleared.
● C: Carry flag:
The C flag is set when a carry-up or carry-down from the MSB occurs as a result of operation execution,
and is otherwise cleared.
■ Register Bank Pointer (RP)
The RP register indicates the relationship between the general-purpose registers of the F2MC-16LX and the
internal RAM addresses. Specifically, the RP register indicates the first memory address of the currently
used register bank in the following conversion expression: [00180H + (RP) × 10H] (see Figure 2.7-8 ). The
RP register consists of five bits, and can take a value between "00H" and "1FH". Register banks can be
allocated at addresses from 000180H to 00037H in memory.
Even within that range, however, the register banks cannot be used as general-purpose registers if the banks
are not in internal RAM. The RP register is initialized to all zeroes by a reset. An instruction may transfer
an eight-bit immediate value to the RP register; however, only the low-order five bits of that data are used.
Figure 2.7-8 Register Bank Pointer (RP)
Initial value
B4
B3
B2
0
0
0
B1
B0
0
0
: RP
■ Interrupt Level Mask Register (ILM)
The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt request is
accepted only when the level of the interrupt is higher than that indicated by these three bits. Level 0 is the
highest priority interrupt, and level 7 is the lowest priority interrupt (see Table 2.7-1 ). Therefore, for an
interrupt to be accepted, its level value must be smaller than the current ILM value. When an interrupt is
accepted, the level value of that interrupt is set in ILM. Thus, an interrupt of the same or lower level cannot
be accepted subsequently. ILM is initialized to all zeroes by a reset. An instruction may transfer an eightbit immediate value to the ILM register, but only the low-order three bits of that data are used.
Figure 2.7-9 Interrupt Level Register (ILM)
Initial value
ILM2
ILM1
ILM0
0
0
0
: ILM
33
CHAPTER 2 CPU
Table 2.7-1 Levels Indicated by the Interrupt Level Mask (ILM) Register
34
ILM2
ILM1
ILM0
Level value
Acceptable interrupt level
0
0
0
0
Interrupt disabled
0
0
1
1
0 only
0
1
0
2
Level value smaller than 1
0
1
1
3
Level value smaller than 2
1
0
0
4
Level value smaller than 3
1
0
1
5
Level value smaller than 4
1
1
0
6
Level value smaller than 5
1
1
1
7
Level value smaller than 6
CHAPTER 2 CPU
2.7.4
Program Counter (PC)
The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory
address of an instruction code to be executed by the CPU. The high-order eight bits of
the address are indicated by the PCB. The PC register is updated by a conditional
branch instruction, subroutine call instruction, interrupt, or reset.
The PC register can also be used as a base pointer for operand access.
■ Program Counter (PC)
Figure 2.7-10 shows the program counter.
Figure 2.7-10 Program Counter
PCB
FE H
PC
ABCD H
Next instruction to be executed
FEABCDH
35
CHAPTER 2 CPU
2.8
Register Bank
A register bank consists of eight words. The register bank can be used as the following
general-purpose registers for arithmetic operations: byte registers R0 to R7, word
registers RW0 to RW7, and long word registers RL0 to RL3. In addition, the register
bank can be used as instruction pointers.
■ Register Bank
Table 2.8-1 lists the functions of the registers. Table 2.8-2 indicates the relationship between the registers.
In the same manner as for an ordinary RAM area, the register bank values are not initialized by a reset. The
status before a reset is maintained. When the power is turned on, however, the register bank will have an
undefined value.
Table 2.8-1 Register Functions
R0 to R7
Used as operands of instructions.
(Note)
R0 is also used as a counter for barrel shift or normalization instructions.
RW0 to RW7
Used as pointers.
Used as operands of instructions.
(Note)
RW0 is used as a counter for string instructions.
RL0 to RL3
Used as long pointers.
Used as operands of instructions.
Table 2.8-2 Relationship between Registers
RW0
RL0
RW1
RW2
RL1
RW3
R0
RW4
R1
RL2
R2
RW5
R3
R4
RW6
R5
RL3
R6
RW7
R7
36
CHAPTER 2 CPU
● Direct page register (DPR) <Initial value: 01H>
DPR specifies addr8 to addr15 of the instruction operands in direct addressing mode as shown in Figure
2.8-1 . DPR is eight bits long, and is initialized to "01H" by a reset. DPR can be read or written to by an
instruction.
Figure 2.8-1 Generating a Physical address in Direct Addressing Mode
DTB register
Direct address during instruction
DPR register
MSB
LSB
24-bit physical
address
● Program counter bank register (PCB) <Initial value: Value in reset vector>
● Data bank register(DTB) <Initial value: 00H>
● User stack bank register(USB) <Initial value: 00H>
● System stack bank register(SSB) <Initial value: 00H>
● Additional data bank register(ADB) <Initial value: 00H>
Each bank register indicates the memory bank where the PC, DT, SP (user), SP (system), or AD space is
allocated. All bank registers are one byte long. PCB is initialized to 00H by a reset. Bank registers other
than PCB can be read or written to. PCB can be read but cannot be written to.
PCB is updated when the JMPP, CALLP, RETP, RETI, or RETF instruction branching to the entire 16Mbyte space is executed or when an interrupt occurs. For operation of each register, see Section "2.2
Memory Space".
37
CHAPTER 2 CPU
2.9
Prefix Codes
Placing a prefix code before an instruction partially changes the operation of the
instruction. Three types of prefix codes can be used: bank select prefix, common
register bank prefix, and flag change disable prefix.
■ Bank Select Prefix
The memory space used for accessing data is determined for each addressing mode.
When a bank select prefix is placed before an instruction, the memory space used for accessing data by that
instruction can be selected regardless of the addressing mode.
Table 2.9-1 lists the bank select prefixes and the corresponding memory spaces.
Table 2.9-1 Bank Select Prefix
Bank select prefix
Space selected
PCB
PC space
DTB
Data space
ADB
AD space
SPB
Either the SSP or USP space is used according to the stack flag value.
Use the following instructions with care:
● String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW)
The bank register specified by an operand is used regardless of the prefix.
● Stack manipulation instructions (PUSHW, POPW)
SSB or USB is used according to the S flag regardless of the prefix.
● I/O access instructions
MOV A, io / MOV io, A /MOVX A, io / MOVW A, io /MOVW io, A / MOV io, #imm8
MOV io, #imm16 / MOVB A, io:bp / MOB io:bp, A /SETB io:bp / CLRB io:bp
BBC io:bp, rel / BBS io:bp, rel WBTC, WBTS
The I/O space of the bank is used regardless of the prefix.
● Flag change instructions (AND CCR,#imm8, OR CCR,#imm8)
The instruction is executed normally, but the prefix affects the next instruction.
● POPW PS
SSB or USB is used according to the S flag regardless of the prefix. The prefix affects the next instruction.
38
CHAPTER 2 CPU
● MOV ILM,#imm8
The instruction is executed normally, but the prefix affects the next instruction.
● RETI
SSB is used regardless of the prefix.
■ Common Register Bank Prefix (CMR)
To simplify data exchange between multiple tasks, the same register bank must be accessed relatively
easily regardless of the RP value. When CMR is placed before an instruction that accesses a register bank,
that instruction accesses the common bank (the register bank selected when RP=0) at addresses from
000180H to 00018FH regardless of the current RP value. When using the common register bank prefix
(CMR), use the following instructions carefully:
● String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW)
If an interrupt request occurs during execution of a string instruction with a prefix code, the prefix code
becomes invalid when the string instruction is resumed after the interrupt is processed. Thus, the string
instruction is executed falsely after the interrupt is processed. Do not prefix any of the above string
instructions with CMR.
● Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS)
The instruction is executed normally, but the prefix affects the next instruction.
● MOV ILM,#imm8
The instruction is executed normally, but the prefix affects the next instruction.
39
CHAPTER 2 CPU
■ Flag Change Disable Prefix (NCC)
To disable flag changes, use the flag change disable prefix code (NCC). Placing NCC before an instruction
disables flag changes associated with that instruction. When using the flag change disable prefix (NCC),
use the following instructions carefully:
● String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW)
If an interrupt request occurs during execution of a string instruction with a prefix code, the prefix code
becomes invalid when the string instruction is resumed after the interrupt is processed. Thus, the string
instruction is executed incorrectly after the interrupt is processed. Do not prefix any of the above string
instructions with NCC.
● Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS)
The instruction is executed normally, but the prefix affects the next instruction.
● Interrupt instructions (INT #vct8, INT9, INT addr16, INTP addr24, RETI)
CCR changes according to the instruction specifications regardless of the prefix.
● JCTX @A
CCR changes according to the instruction specifications regardless of the prefix.
● MOV ILM,#imm8
The instruction is executed normally, but the prefix affects the next instruction.
40
CHAPTER 2 CPU
2.10
Interrupt Disable Instructions
Interrupt requests are not sampled for the following ten instructions:
- MOV ILM,#imm8
- PCB
- SPB
- OR
CCR,#imm8
- AND CCR,#imm8
- ADB
- CMR
- POPW PS
- NCC
- DTB
■ Interrupt Disable Instructions
If a valid interrupt request occurs during execution of any of the above instructions, the interrupt can be
processed only when an instruction other than the above is executed. For details, see Figure 2.10-1 .
Figure 2.10-1 Interrupt Disable Instruction
Interrupt disable instruction
••••••••
(a)
•••
(a) Ordinary
instruction
Interrupt request
Interrupt acceptance
■ Restrictions on Interrupt Disable Instructions and Prefix Instructions
When a prefix code is placed before an interrupt disable instruction, the prefix code affects the first
instruction after the code other than the interrupt disable instruction.
Figure 2.10-2 Interrupt Disable Instructions and Prefix Codes
Interrupt disable instruction
MOV A, FFH
NCC
••••
MOV ILM,#imm8
ADD A,01H
CCR:XXX10XX
CCR:XXX10XX
CCR does not change with NCC.
■ Consecutive Prefix Codes
When competitive prefix codes are placed consecutively, the latter becomes valid.
In the figure below, competitive prefix codes are PCB, ADB, DTB, and SPB.
Figure 2.10-3 Consecutive Prefix Codes
Prefix code
• • • • •• • •
ADB
DTB
PCB
ADD A,01H
•
PCB is valid as the prefix code
41
CHAPTER 2 CPU
42
CHAPTER 3
INTERRUPTS
This chapter explains the interrupt functions and
operations.
3.1 Outline of Interrupts
3.2 Interrupt Sources
3.3 Interrupt Vector
3.4 Hardware Interrupts
3.5 Software Interrupts
3.6 Extended Intelligent I/O Service (EI2OS)
3.7 Exception Due to Execution of an Undefined Instruction
43
CHAPTER 3 INTERRUPTS
3.1
Outline of Interrupts
The F2MC-16LX has interrupt functions that, when an event occurs, terminate the
processing being currently executed and transfer control to a separately defined
program.
■ Outline of Interrupts
There are four types of interrupt functions:
• Hardware interrupt: Interrupt processing due to an internal resource event
• Software interrupt: Interrupt processing due to an instruction causing a software event
• Extended intelligent I/O service (EI2OS): Transfer processing due to an internal resource event
• Exception: Termination due to an operation exception
This section explains these four types
44
CHAPTER 3 INTERRUPTS
3.2
Interrupt Sources
Table 3.2-1 lists the interrupt sources, interrupt vectors, and interrupt control registers
in the MB90440G series.
■ Interrupt Sources
Table 3.2-1 Interrupt Sources, Interrupt Vectors, and Interrupt Control Registers (1/2)
Interrupt vector
Interrupt source
Interrupt control register
EI2OS clear
Number
Address
Number
Address
Reset
X
#08
FFFFDCH
-
-
INT9 instruction
X
#09
FFFFD8H
-
-
Exception
X
#10
FFFFD4H
-
-
CAN0 Receive
X
#11
FFFFD0H
ICR00
X
#12
FFFFCCH
0000B0H
CAN0 Transmit/Node status
CAN1 Receive
X
#13
FFFFC8H
ICR01
X
#14
FFFFC4H
0000B1H
CAN1 Transmit/Node status
External interrupt INT0/INT1
O
#15
FFFFC0H
ICR02
X
#16
FFFFBCH
0000B2H
Time-base timer
16-bit reload timer 0
O
#17
FFFFB8H
ICR03
O
#18
FFFFB4H
0000B3H
A/D converter
Input/output timer
X
#19
FFFFB0H
ICR04
O
#20
FFFFACH
0000B4H
External interrupt INT2/INT3
Serial I/O
O
#21
FFFFA8H
ICR05
X
#22
FFFFA4H
0000B5H
PPG0 to PPG3
Input capture 0
O
#23
FFFFA0H
ICR06
O
#24
FFFF9CH
0000B6H
External interrupt INT4/INT5
CAN2 Receive
X
#25
FFFF98H
ICR07
X
#26
FFFF94H
0000B7H
CAN2 Transmit/Node status
External interrupt INT6/INT7
O
#27
FFFF90H
ICR08
X
#28
FFFF8CH
0000B8H
Monitoring timer
45
CHAPTER 3 INTERRUPTS
Table 3.2-1 Interrupt Sources, Interrupt Vectors, and Interrupt Control Registers (2/2)
Interrupt vector
Interrupt source
Interrupt control register
EI2OS clear
Number
Address
Input capture 1
O
#29
FFFF88H
Input capture 2/3
O
#30
FFFF84H
PPG4 to PPG7
X
#31
FFFF80H
Output compare 0
O
#32
FFFF7CH
Output compare 1
O
#33
FFFF78H
Input capture 4/5
O
#34
FFFF74H
Output compare 2/3,
Input capture 6/7
O
#35
FFFF70H
16-bit reload timer 1
O
#36
FFFF6CH
UART0 Receive
*
#37
FFFF68H
UART0 Transmit
O
#38
FFFF64H
UART1 Receive
*
#39
FFFF60H
UART1 Transmit
O
#40
FFFF5CH
Flash memory
X
#41
FFFF58H
Delayed interrupt
X
#42
FFFF54H
Number
Address
ICR09
0000B9H
ICR10
0000BAH
ICR11
0000BBH
ICR12
0000BCH
ICR13
0000BDH
ICR14
0000BEH
ICR15
0000BFH
*: An EI2OS interrupt clear signal clears the interrupt request flag. A stop request is issued.
O: An EI2OS interrupt clear signal clears the interrupt request flag.
X: An EI2OS interrupt clear signal does not clear the interrupt request flag.
Note:
In a peripheral module in which two interrupt sources are assigned to the same interrupt number, an
EI2OS interrupt clear signal clears both interrupt request flags.
At EI2OS termination, an EI2OS clear signal is issued to all interrupt flags assigned to the same
interrupt number. If an interrupt flag starts EI2OS and another interrupt flag is set by a hardware
event, the flag is cleared by the EI2OS clear signal issued by the first event and the latter event is
lost. Do not use EI2OS for this interrupt number.
When EI2OS is enabled, one of two interrupt signals in the same interrupt control register (ICR) is
issued to start EI2OS. Although an individual EI2OS descriptor should be provided for each interrupt
source, the two interrupt sources actually share the same EI2OS descriptor. While one interrupt
source is using EI2OS, therefore, the other interrupt source must be disabled.
46
CHAPTER 3 INTERRUPTS
3.3
Interrupt Vector
Table 3.3-1 lists MB90440G series interrupt vectors.
■ Interrupt Vector
Table 3.3-1 Interrupt Vector (1/2)
Software
interrupt
instruction
INT 0
:
INT 7
Vector
address L
FFFFFCH
:
FFFFE0H
Vector
address M
Vector
address H
Mode
register
Interrupt
No.
FFFFFDH
FFFFFEH
Not used
#0
:
:
:
:
FFFFE1H
FFFFE2H
Not used
#7
None
Hardware interrupt
None
:
INT 8
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDFH
#8
(RESET vector)
INT 9
FFFFD8H
FFFFD9H
FFFFDAH
Not used
#9
ROM correction
INT 10
FFFFD4H
FFFFD5H
FFFFD6H
Not used
#10
<Exception>
INT 11
FFFFD0H
FFFFD1H
FFFFD2H
Not used
#11
CAN0 Receive
INT 12
FFFFCCH
FFFFCDH
FFFFCEH
Not used
#12
CAN0 Transmit/
Node status
INT 13
FFFFC8H
FFFFC9H
FFFFCAH
Not used
#13
CAN1 Receive
INT 14
FFFFC4H
FFFFC6H
Not used
#14
CAN1 Transmit/
Node status
INT 15
FFFFC0H
FFFFC1H
FFFFC2H
Not used
#15
External interrupt INT0/
INT1
INT 16
FFFFBCH
FFFFBDH
FFFFBEH
Not used
#16
Time-base timer
INT 17
FFFFB8H
FFFFB9H
FFFFBAH
Not used
#17
16-bit reload timer 0
INT 18
FFFFB4H
FFFFB5H
FFFFB6H
Not used
#18
A/D converter
INT 19
FFFFB0H
FFFFB1H
FFFFB2H
Not used
#19
I/O timer
INT 20
FFFFACH
FFFFADH
FFFFAEH
Not used
#20
External interrupt INT2/
INT3
INT 21
FFFFA8H
FFFFA9H
FFFFAAH
Not used
#21
Serial I/O
INT 22
FFFFA4H
FFFFA5H
FFFFA6H
Not used
#22
PPG0 to PPG3
INT 23
FFFFA0H
FFFFA1H
FFFFA2H
Not used
#23
Input capture 0
FFFFC5H
47
CHAPTER 3 INTERRUPTS
Table 3.3-1 Interrupt Vector (2/2)
48
Software
interrupt
instruction
Vector
address L
Vector
address M
Vector
address H
Mode
register
Interrupt
No.
INT 24
FFFF9CH
FFFF9DH
FFFF9EH
Not used
#24
External interrupt INT4/
INT5
INT 25
FFFF98H
FFFF99H
FFFF9AH
Not used
#25
CAN2 Receive
INT 26
FFFF94H
FFFF95H
FFFF96H
Not used
#26
CAN2 Transmit/
Node status
INT 27
FFFF90H
FFFF91H
FFFF92H
Not used
#27
External interrupt INT6/
INT7
INT 28
FFFF8CH
FFFF8DH
FFFF8EH
Not used
#28
Monitoring timer
INT 29
FFFF88H
FFFF89H
FFFF8AH
Not used
#29
Input capture 1
INT 30
FFFF84H
FFFF85H
FFFF86H
Not used
#30
Input capture 2/3
INT 31
FFFF80H
FFFF81H
FFFF82H
Not used
#31
PPG4 to PPG7
INT 32
FFFF7CH
FFFF7DH
FFFF7EH
Not used
#32
Output compare 0
INT 33
FFFF78H
FFFF79H
FFFF7AH
Not used
#33
Output compare 1
INT 34
FFFF74H
FFFF75H
FFFF76H
Not used
#34
Input capture 4/5
INT 35
FFFF70H
FFFF71H
FFFF72H
Not used
#35
Output compare 2/3
Input capture 6/7
INT 36
FFFF6CH
FFFF6DH
FFFF6EH
Not used
#35
16-bit reload timer 1
INT 37
FFFF68HH
FFFF69H
FFFF6AH
Not used
#36
UART 0 Receive
INT 38
FFFF64H
FFFF65H
FFFF66H
Not used
#37
UART 0 Transmit
INT 39
FFFF60H
FFFF61H
FFFF62H
Not used
#38
UART 1 Receive
INT 40
FFFF5CH
FFFF5DH
FFFF5EH
Not used
#39
UART 1 Transmit
INT 41
FFFF58H
FFFF59H
FFFF5AH
Not used
#40
Flash memory
INT 42
FFFF54H
FFFF55H
FFFF56H
Not used
#41
Delayed interrupt
INT 43
FFFF50H
FFFF51H
FFFF52H
Not used
#42
None
:
:
:
:
:
:
INT 254
FFFC04H
FFFC05H
FFFC06H
Not used
#254
None
INT 255
FFFC00H
FFFC01H
FFFC02H
Not used
#255
None
Hardware interrupt
:
CHAPTER 3 INTERRUPTS
3.4
Hardware Interrupts
In response to an interrupt request signal from an internal resource, the CPU pauses
current program execution and transfers control to the interrupt processing program
defined by the user. This function is called the hardware interrupt function.
■ Hardware Interrupts
A hardware interrupt occurs when the relevant conditions are satisfied as a result of two operations:
comparison between the interrupt request level and the value in the interrupt level mask register (ILM) of
PS in the CPU, and hardware reference to the I flag value of PS.
The CPU performs the following processing when a hardware interrupt occurs:
• Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system
stack.
• Sets ILM in the PS register. The currently requested interrupt level is automatically set.
• Fetches the corresponding interrupt vector value and branches to the processing indicated by that value.
■ Structure of Hardware Interrupt
Hardware interrupts are handled by the following three sections:
● Internal resources
Interrupt enable and request bits: Used to control interrupt requests from resources.
● Interrupt controller
ICR: Assigns interrupt levels and determines the priority levels of simultaneously requested interrupts.
● CPU
I and ILM: Used to compare the requested and current interrupt levels and to identify the interrupt enable
status.
Microcode: Interrupt processing step
The status of these sections are indicated by the resource control registers for internal resources, the ICR
for the interrupt controller, and the CCR value for the CPU. To use a hardware interrupt, set the three
sections beforehand by using software.
The interrupt vector table referenced during interrupt processing is assigned to addresses FFFC00H to
FFFFFFH in memory. These addresses are shared with software interrupts.
■ Hardware Interrupt Request during Writing to the Input-Output Area
When data is being written to the input-output area, hardware interrupt requests are not accepted. This
prevents the CPU from making operational mistakes, which could be caused if an interrupt request were
generated while data was being rewritten to the interrupt control registers for each source.
49
CHAPTER 3 INTERRUPTS
■ Multiple Interrupts
The F2MC-16LX CPU supports multiple interrupts. If an interrupt of a higher level occurs while another
interrupt is being processed, control is transferred to the higher-level interrupt after the current instruction
completes execution. After the higher-level interrupt terminates, the CPU returns to processing of the
previous interrupt. If an interrupt of the same or lower level occurs while another interrupt is being
processed, the new interrupt request is kept pending until termination of the current interrupt processing
unless the ILM value or I flag is changed by an instruction. The extended intelligent I/O service cannot be
used for the activation of multiple interrupts. During processing of the extended intelligent I/O service, all
other interrupt requests or extended intelligent I/O service requests are kept pending.
■ Register Saving onto the Stack
Figure 3.4-1 shows the order of the registers saved in the stack.
Figure 3.4-1 Registers Saved on the Stack
Word (16 bits)
MSB
LSB
H
SSP
(SSP value before interrupt)
AH
AL
DPR
ADB
DTB
PCB
PC
PS
L
50
SSP
(SSP value after interrupt)
CHAPTER 3 INTERRUPTS
3.4.1
Hardware Interrupt Operation
An internal resource that has the hardware interrupt request function has an interrupt
request flag and interrupt enable flag. The interrupt request flag indicates whether an
interrupt request exists, and the interrupt enable flag indicates whether the relevant
internal resource requests an interrupt to the CPU. The interrupt request flag is set
when an event occurs that is unique to the internal resource. When the interrupt enable
flag indicates "enable", the resource issues an interrupt request to the interrupt
controller.
■ Hardware Interrupt Operation
When two or more interrupt requests are received at the same time, the interrupt controller compares the
interrupt levels (IL) in ICR, selects the request at the highest level (the smallest IL value), then reports that
request to the CPU. If multiple requests are at the same level, the interrupt controller selects the request
with the lowest interrupt number. The relationship between the interrupt requests and ICRs is determined
by the hardware.
The CPU compares the received interrupt level and the ILM in the PS register. If the interrupt level is
smaller than the ILM value and the I bit of the PS register is set to "1", the CPU activates the interrupt
processing microcode after the currently executing instruction is completed. The CPU references the ISE
bit of the ICR of the interrupt controller at the beginning of the interrupt processing microcode, checks that
the ISE bit is "0" (interrupt), and activates the interrupt processing body.
The interrupt processing body saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area
indicated by SSB and SSP, fetches three bytes of interrupt vector and loads them onto PC and PCB,
updates the ILM of PS to a level value of the received interrupt, sets the S flag, then performs branch
processing. As a result, the interrupt processing program defined by the user is executed next.
Figure 3.4-2 illustrates the flow from the occurrence of a hardware interrupt until there is no interrupt
request in the interrupt processing program.
Figure 3.4-2 Occurrence and Release of Hardware Interrupt
PS
Register file
Internal data bus
Microcode
IR
(6)
I
ILM
Check
F 2 M C - 1 6 LX · C P U
AND
(1)
(2)
Interrupt level IL
Enable FF
Level comparator
··
··
·
Cause FF
: Processor status
: Interrupt enable flag in CCR
: Interrupt level in PS
: Instruction register
(4)
(3)
Peripheral
(7)
Comparator
(5)
PS
I
ILM
IR
Interrupt
controller
Peripheral
51
CHAPTER 3 INTERRUPTS
Operations (1) to (7) in Figure 3.4-2 are explained below.
(1) An interrupt cause occurs in a peripheral.
(2) The interrupt enable bit in the peripheral is referenced. If interrupts are enabled, the peripheral issues an
interrupt request to the interrupt controller.
(3) Upon reception of the interrupt request, the interrupt controller determines the priority levels of
simultaneously requested interrupts. Then, the interrupt controller transfers the interrupt level of the
corresponding interrupt to the CPU.
(4) The CPU compares the interrupt level requested by the interrupt controller with the ILM bit of the
processor status register.
(5) If the comparison shows that the requested level is higher than the current interrupt processing level, the
I flag value of the same processor status register is checked.
(6) If the check in step 5. shows that the I flag indicates interrupt enable status, the requested level is
written to the ILM bit. Interrupt processing is performed as soon as the currently executing instruction
is completed, then control is transferred to the interrupt processing routine.
(7) When the interrupt cause of step 1. is cleared by software in the user interrupt processing routine, the
interrupt request is completed.
The time required for the CPU to execute the interrupt processing in steps 6. and 7. is shown below.
Interrupt start: 24 + 6 × (Table 3.4-1 machine cycles)
Interrupt return: 15 + 6 × (Table 3.4-1 machine cycles) RETI instruction
Table 3.4-1 Compensation Values for Interrupt Processing Cycle Count
Address indicated by the stack pointer
Cycle count compensation value
External area, 8-bit data bus
+4
External area, even-numbered address
+1
External area, odd-numbered address
+4
Internal area, even-numbered address
0
Internal area, odd-numbered address
+2
52
CHAPTER 3 INTERRUPTS
3.4.2
Flow of Hardware Interrupt Operation
Figure 3.4-3 shows the flow of hardware interrupt operation.
■ Flow of Hardware Interrupt Operation
Figure 3.4-3 Flow of Hardware Interrupt Operation
I
ILM
IF
IE
ISE
IL
S
I&IF&IE=1
AND
ILM > IL
:
:
:
:
:
:
:
Interrupt enable flag in CCR
Interrupt level mask register in PS
Interrupt request for internal resource
Interrupt enable flag for internal resource
EI2OS enable flag
Interrupt request level for internal resource
Flag in CCR
YES
NO
NO
Fetch the next instruction
and decode
Save PS, PC, PCB, DTB,
ADB, DPR, and A to the
SSP stack, then set ILM = IL
INT instruction?
Execute an ordinary instruction
Repetition of
string type instruction
completed?
Extended intelligent I/O
service processing
YES
NO
NO
YES
ISE = 1
Save PS, PC, PCB, DTB, ADB,
DPR, and A to the SSP stack,
then set I = 0 and ILM = IL
S
1
(fetch interrupt vector)
YES
Update PC
53
CHAPTER 3 INTERRUPTS
3.5
Software Interrupts
The software interrupt function returns control from the program being executed by the
CPU to the user-defined interrupt processing program in response to execution of a
special instruction.
■ Software Interrupts
A software interrupt is always activated when the software interrupt instruction is executed.
The CPU performs the following processing when a software interrupt occurs:
• Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system
stack.
• Sets I in the PS register. Interrupts are automatically disabled.
• Fetches the corresponding interrupt vector value, then branches to the processing indicated by that
value.
A software interrupt request issued by the INT instruction has no interrupt request or enable flag. A
software interrupt request is always issued by executing the INT instruction.
The INT instruction does not have an interrupt level. Therefore, the INT instruction does not update ILM.
The INT instruction clears the I flag to suspend subsequent interrupt requests.
■ Structure of Software Interrupts
Software interrupts are handled within the CPU:
CPU.....Microcode: Interrupt processing step
As shown in Table 3.3-1 , software interrupts share the same interrupt vector area with hardware interrupts.
For example, interrupt request number INT 15 is used for external interrupt #0 (hardware interrupt) as well
as for INT #15 (software interrupt). Therefore, external interrupts #0 and INT #15 call the same interrupt
processing routine.
■ Software Interrupt Operation
When the CPU fetches and executes the software interrupt instruction, the software interrupt processing
microcode is activated. The software interrupt processing microcode saves 12 bytes (PS, PC, PCB, DTB,
ADB, DPR, and A) to the memory area indicated by SSB and SSP. The microcode then fetches three bytes
of interrupt vector and loads them onto PC and PCB, resets the I flag, and sets the S flag. Then, the
microcode performs branch processing. As a result, the interrupt processing program defined by the user
application program is executed next.
Figure 3.5-1 illustrates the flow from the occurrence of a software interrupt until there is no interrupt
request in the interrupt processing program.
54
CHAPTER 3 INTERRUPTS
Figure 3.5-1 Occurrence and Release of Software Interrupt
(1)
PS
Internal data bus
Register file
I
(2)
Microcode
F 2 M C - 1 6 LX • C P U
S
B unit
IR
Queue
Fetch
PS
I
S
IR
B unit
: Processor status
: Interrupt enable flag in CCR
: IInterrupt level in PS
: Instruction register
: Bus interface unit
Save
Instruction bus
RAM
Figure 3.5-1 illustrates the flow from the occurrence of a software interrupt until there is no interrupt
request in the interrupt processing program.
(1) The software interrupt instruction is executed.
(2) Special CPU registers in the register file are saved according to the microcode corresponding to the
software interrupt instruction.
(3) The interrupt processing is completed with the RETI instruction in the user interrupt processing routine.
■ Note on Software Interrupt
When the program counter bank register (PCB) is "FFH", the CALLV instruction vector area overlaps the
table of the INT #vct8 instruction. When designing software, ensure that the CALLV instruction does not
use the same address as that of the #vct8 instruction.
55
CHAPTER 3 INTERRUPTS
3.6
Extended Intelligent I/O Service (EI2OS)
The EI2OS function automatically transfers data between input and output and memory.
An interrupt processing program was conventionally used for such processing, but
EI2OS enables data transfer to be performed like DMA (direct memory access).
Note:
The use of EI2OS is not possible with the REALOS real time operating system.
■ Extended Intelligent I/O Service (EI2OS)
The extended intelligent I/O service (EI2OS) has the following advantages over the conventional interrupt
processing method:
• The program size can be small because it is not necessary to write a transfer program.
• No internal register is used for transfer, eliminating the need for register saving and increasing the
transfer speed.
• Transfer can be terminated from I/O, preventing unnecessary data from being transferred.
• Incrementing, decrementing, or no update can be selected for the buffer address.
• Incrementing, decrementing, or no update can be selected for the I/O register address (if the buffer
address is updated).
At the end of EI2OS, processing automatically branches to an interrupt processing routine after the end
condition is set. Thus, the user can identify the end condition.
Figure 3.6-1 provides an overview of EI2OS.
56
CHAPTER 3 INTERRUPTS
Figure 3.6-1 Outline of Extended Intelligent I/O Service
Memory space
by IOA
I/O register
I/O register
Peripheral
CPU
Interrupt request
(3)
(1)
by ICS
ISD
(3)
(2)
Interrupt control register
Interrupt controller
I/O requests transfer.
The interrupt controller selects the
descriptor.
(3) The transfer source and destination
by
are read from the descriptor.
DCT
(4) Data is transferred between I/O and
memory.
(5) The interrupt source is automatically cleared.
(1)
by BAP
(2)
(4)
Buffer
Note:
The area that can be specified by IOA is between 000000H and 00FFFFH.
The area that can be specified by BAP is between 000000H and FFFFFFH.
The maximum transfer count that can be specified by DCT is 65536.
■ Structure
EI2OS is handled by the following four sections:
Internal resources
Interrupt enable and request bits: Used to control interrupt requests from resources.
Interrupt controller
ICR: Assigns interrupt levels, determines the priority levels of simultaneously requested interrupts, and
selects the EI2OS operation.
CPU
I and ILM: Used to compare the requested and current interrupt levels and to identify the interrupt
enable status
Microcode: EI2OS processing step
RAM
Descriptor: Describes the EI2OS transfer information.
57
CHAPTER 3 INTERRUPTS
3.6.1
Interrupt Control Register (ICR)
The interrupt control register, located in the interrupt controller, handles the interrupts
corresponding to all I/Os that have an interrupt function. The interrupt control register
has the following three functions:
• Setting an interrupt level for each related peripheral
• Selecting whether to use an ordinary interrupt or extended intelligent I/O service for a
related peripheral
• Selecting the extended intelligent I/O service channel
Do not access an interrupt control register with a read-modify-write instruction, since
an erroneous operation will result.
■ Interrupt Control Register (ICR)
Figure 3.6-2 shows the bit configuration of the interrupt control register.
Figure 3.6-2 Interrupt Control Register (ICR)
Interrupt control register (ICR)
bit 15/7
Address : B0H to BFH
Read/write
Initial value
13/5
12/4
11/3
10/2
9/1
8/0
ICS3 ICS2 ICS1 ICS0 ISE
IL2
IL1
IL0
(W)
(0)
(W)
(1)
(W)
(1)
(W)
(1)
bit 15/7
Address : B0H to BFH
Read/write
Initial value
R:Read only
W:Write only
14/6
(-)
(-)
(W)
(0)
(W)
(0)
(W)
(0)
14/6
13/5
12/4
11/3
10/2
S1
S0
ISE
IL2
IL1
IL0
(R)
(0)
(R)
(1)
(R)
(1)
(R)
(1)
(-)
(-)
(R)
(0)
(R)
(0)
(W)
(0)
9/1
During writing
8/0
During reading
Note:
ICS3 to ICS0 are valid only when EI2OS is activated. Set ISE to "1" to activate EI2OS and to "0" not
to activate it. When EI2OS is not to be activated, any value can be set in ICS3 to ICS0.
ICS1 and ICS0 can only be written to. S1 and S0 can only be read.
[bit15 to bit12, bit7 to bit4]: ICS3 to ICS0
The ICS3 to ICS0 bits specify the EI2OS channel.
They are write only bits. The values set for these bits determine the extended intelligent I/O service
descriptor addresses in memory. The ICS bits are initialized by a reset.
Table 3.6-1 lists the correspondence between ICS bits, channel numbers, and descriptor addresses.
58
CHAPTER 3 INTERRUPTS
Table 3.6-1 ICS Bits, Channel Numbers, and Descriptor Addresses
ICS3
ICS2
ICS1
ICS0
Selected channel
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
[bit13, bit12, bit5, bit4]: S1, S0
The S0 and S1 bits indicate the EI2OS termination status.
They are read-only bits. When the values in these bits are checked at EI2OS termination, a termination
condition can be identified. These bits are initialized to "00B" by a reset.
Table 3.6-2 shows the relationship between the S bits and termination conditions.
Table 3.6-2 S Bits and Termination Conditions
S1
S0
Termination condition
0
0
EI2OS running or not activated
0
1
Stopped status due to count termination
1
0
Reserved
1
1
Stopped status due to a request from the internal resource
59
CHAPTER 3 INTERRUPTS
[bit11, bit3]: ISE
The ISE bit enables EI2OS. This bit can be read and written to.
If this bit is "1" when an interrupt request is generated, EI2OS is activated. If this bit is "0" when an
interrupt request is generated, the interrupt sequence is activated. When the EI2OS termination
condition is met (when the S1 and S0 bits are not "00B"), the ISE bit is cleared to "0". If the
corresponding peripheral function does not have the EI2OS function, the ISE bit must be set to "0" by
software. The ISE bit is initialized to "0" by a reset.
[bit10 to bit8, bit2 to bit0]: IL0 to IL2
The IL0, IL1, and IL2 bits set the interrupt level.
These bits specify the interrupt level of the corresponding internal resources. These bits can be read and
written to. These bits are initialized to level 7 (no interrupt) by a reset. Table 3.6-3 shows the
relationship between the interrupt level setting bits and interrupt levels.
Table 3.6-3 Interrupt Level Setting Bits and Interrupt Levels
60
IL2
IL1
IL0
Interrupt level
0
0
0
0 (highest interrupt)
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6 (lowest interrupt)
1
1
1
7 (no interrupt)
CHAPTER 3 INTERRUPTS
3.6.2
Extended Intelligent I/O Service Descriptor (ISD)
The extended intelligent I/O service descriptor exists between 000100H and 00017FH in
internal RAM, and consists of the following items:
• Data transfer control data
• Status data
• Buffer address pointer
■ Extended Intelligent I/O Service Descriptor (ISD)
Figure 3.6-3 shows the configuration of the extended intelligent I/O service descriptor.
Figure 3.6-3 Extended Intelligent I/O Service Descriptor Configuration
H
High-order 8 bits of data counter (DCTH)
Low-order 8 bits of data counter (DCTL)
High-order 8 bits of I/O address pointer (IOAH)
Low-order 8 bits of I/O address pointer (IOAL)
EI 2OS status (ISCS)
High-order 8 bits of buffer address pointer (BAPH)
000100 H + 8 × ICS
Medium-order 8 bits of buffer address pointer (BAPM)
ISD start address
Low-order 8 bits of buffer address pointer (BAPL)
L
■ Data Counter (DCT)
This is a 16-bit register that works as a counter corresponding to the number of data items transferred. This
counter is decremented by one before data transfer. EI2OS is terminated when this counter reaches 0.
Figure 3.6-4 is a diagram of the data counter configuration.
Figure 3.6-4 Data Counter Configuration
Data counter (upper)
Initial value
Data counter (lower)
Initial value
bit
15
14
13
12
11
10
B15
B14
B13
B12
B11
B10
(X)
bit
(X)
(X)
(X)
(X)
(X)
9
8
B09
B08
(X)
DCTH
(X)
7
6
5
4
3
2
1
0
B07
B06
B05
B04
B03
B02
B01
B00
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
DCTL
■ I/O Register Address Pointer (IOA)
This is a 16-bit register that indicates the low-order address (A15 to A00) of the buffer and I/O register
used for data transfer. The high-order address (A23 to A16) are all zeroes, and any I/O between addresses
000000H and 00FFFFH can be specified. Figure 3.6-5 is a diagram of the IOA configuration.
61
CHAPTER 3 INTERRUPTS
Figure 3.6-5 I/O Register Address Pointer Configuration
I/O address pointer (upper) bit 15
14
13
12
11
10
9
8
A15
A14
A13
A12
A11
A10
A09
A08
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
bit 7
6
5
4
3
2
1
0
A07
A06
A05
A04
A03
A02
A01
A00
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Initial value
I/O address pointer (lower)
Initial value
IOAH
IOAL
■ EI2OS Status Register (ISCS)
The EI2OS status register (ISCS) is eight bits, and indicates the update direction (increment/decrement),
transfer data format (byte/word), and transfer direction of the buffer address pointer and I/O register
address pointer. This register also indicates whether the buffer address pointer or I/O register address
pointer is updated or fixed. Figure 3.6-6 shows the ISCS configuration.
Figure 3.6-6 EI2OS Status Register (ISCS) Configuration
bit
7
6
5
Reserved Reserved Reserved
Initial value
(X)
(X)
(X)
4
3
2
1
0
IF
BW
BF
DIR
SE
(X)
(X)
(X)
(X)
* Always write "0" to bit7 to bit5 of ISCS.
[bit4]: IF
The IF bit specifies whether the I/O register address pointer is updated or fixed.
Table 3.6-4 I/O Register Address Pointer Update/Fixed Selection Bit (IF)
IF
Function
0
After data transfer, the I/O register address pointer is updated.
1
After data transfer, the I/O register address pointer is not updated.
[bit3]: BW
The BW bit specifies the transfer data length.
Table 3.6-5 Transfer Data Length Specification Bit (BW)
BW
62
Function
0
Byte
1
Word
(X)
ISCS
CHAPTER 3 INTERRUPTS
[bit2]: BF
The BF bit specifies whether the buffer address pointer is updated or fixed.
Table 3.6-6 Buffer Address Pointer Update/Fixed Selection Bit (BF)
BF
Function
0
After data transfer, the buffer address pointer is updated.
1
After data transfer, the buffer address pointer is not updated.
Note:
Only the lower 16 bits of the buffer address pointer are updated. Only incrementing is allowed.
[bit1]: DIR
The DIR bit specifies the data transfer direction.
Table 3.6-7 Data Transfer Direction Specification Bit (DIR)
DIR
Setting
0
I/O -> buffer
1
Buffer -> I/O
[bit0]: SE
The SE bit controls the termination of the extended intelligent I/O service based on resource requests.
Table 3.6-8 EI2OS Termination Control Bit
SE
Setting
0
Not terminated by a resource request.
1
Terminated by a resource request.
■ Buffer Address Pointer (BAP)
This 24-bit register holds the address used for the next EI2OS transfer. BAP exists for each EI2OS channel.
Therefore, each EI2OS channel can be used for transfer with anywhere in the 16-Mbyte space.
Note:
If the BF bit of ISCS is set to "0" (update enabled), only the low-order 16 bits of BAP changes and
BAPH does not change.
63
CHAPTER 3 INTERRUPTS
3.6.3
Operation of Extended Intelligent I/O Service (EI2OS)
Figure 3.6-7 shows the operation flow of the extended intelligent I/O service (EI2OS).
Figure 3.6-8 shows the procedure for using the extended intelligent I/O service (EI2OS).
■ Operation Flow of the Extended Intelligent I/O Service (EI2OS)
Figure 3.6-7 Operation Flow of the Extended Intelligent I/O Service (EI2OS)
Interrupt request
generated
by internal resource
ISE
1
NO
YES
Read ISD/ISCS
Termination
request from
resource?
Interrupt sequence
YES
SE
NO
DIR
1
NO
BF
0
NO
0
Data indicated by BAP
(Data transfer)
Memory indicated by BAP
YES
DCT
00
NO
Set S1 and S0 to 00
Update value
by BW
Update IOA
Update value
by BW
Update BAP
YES
NO
Decrement DCT
-1
YES
EI2 OS termination processing
Set S1 and S0 to 01
Clear interrupt request
from internal resource
Return to CPU operation
ISD : EI2OS descriptor
ISCS : EI2OS status register
IF
: IOA update/fixed selection bit in the
EI2OS status register (ISCS)
BW : Transfer data length specification
bit in the EI2OS status register (ISCS)
BF
: BAP update/fixed selection bit in the
EI2OS status register (ISCS)
DIR : Data transfer direction specification
bit in the EI2OS status register (ISCS)
SE
: EI2OS termination control bit in the
EI2OS status register (ISCS)
64
YES
YES
Data indicated by IOA
(Data transfer)
Memory indicated by BAP
IF
1
NO
Set S1 and S0 to 11
Clear ISE to 0
Interrupt sequence
DCT
IOA
BAP
ISE
S1,S0
: Data counter
: I/O register address pointer
: Buffer address pointer
: EI2OS enable bit in the interrupt control register (ICR)
: EI2OS status in the interrupt control register (ICR)
CHAPTER 3 INTERRUPTS
Figure 3.6-8 Procedure for Using the Extended Intelligent I/O Service (EI2OS)
Software processing
Hardware processing
Start
Initialization
Set the system stack area
Set the EI2OS descriptor
Initialize the internal resource
Set the interrupt
control register (ICR)
Set the internal resource
to start operation. Set the
interrupt enable bit (ICR)
Set the ILM and I in the PS
S1, S0=00
Execute the user program
(Interrupt request)and (ISE=1)
Transfer data
Decide whether to end counting or to NO
branch to an interrupt by termination
request from resource
(Branch to interrupt vector)
Set the extended
intelligent I/O service
again (switch channels)
YES
S1, S0=01 or
S1, S0=11
Process data in the buffer
RETI
ISE: EI2OS enable bit in the interrupt control register (ICR)
S1, S0: EI2OS status of the interrupt control register (ICR)
65
CHAPTER 3 INTERRUPTS
3.6.4
Execution Time of the Extended Intelligent I/O Service
(EI2OS)
The time required for executing the extended intelligent I/O service (EI2OS) changes in
the following cases:
• When data transfer continues (when the stop condition is not satisfied)
• When a stop request is issued from a resource
• When the counting is completed
■ Execution Time of the Extended Intelligent I/O Service (EI2OS)
● When data transfer continues (when the stop condition is not satisfied)
(Table 3.6-9 + Table 3.6-10 ) machine cycles
Table 3.6-9 Execution Time When the Extended EI2OS Continues
ISCS SE bit
Set to "0"
I/O address pointer
Set to "1"
Fixed
Updated
Fixed
Updated
Fixed
32
34
33
35
Updated
34
36
35
37
Buffer address pointer
● When a stop request is issued from a resource
(36 + 6 × Table 3.4-1 ) machine cycles
● When the counting is completed
(Table 3.6-9 + Table 3.6-10 + (21 + 6 × Table 3.4-1 )) machine cycles
66
CHAPTER 3 INTERRUPTS
Table 3.6-10 Data Transfer Compensation Values for Extended EI2OS Execution Time
Internal access
External access
I/O address pointer
B/E
O
B/E
8/O
B/E
0
+2
+1
+4
O
+2
+4
+3
+6
B/E
+1
+3
+2
+5
8/O
+4
+6
+5
+8
Internal access
Buffer address
pointer
External
access
B: Byte data transfer
8: 8-bit external bus word transfer
E: Even address word transfer
O: Odd address word transfer
67
CHAPTER 3 INTERRUPTS
3.7
Exception Due to Execution of an Undefined Instruction
In the F2MC-16LX, an exception occurs when an undefined instruction is executed and
exception processing is performed.
Exception processing is fundamentally the same as interrupt processing. When an
exception is detected between instructions, exception processing is performed
separately from ordinary processing. In general, exception processing is performed as
the result of an unexpected operation. It is recommended that exception processing be
used only for debugging or for activating emergency recovery software.
■ Exception Due to Execution of an Undefined Instruction
The F2MC-16LX handles all codes that are not defined in the instruction map as undefined instructions.
When an undefined instruction is executed, processing equivalent to the INT 10 software interrupt
instruction is performed.
Specifically, the AL, AH, DPR, DTB, ADB, PCB, PC, and PS values are saved onto the system stack, and
processing branches to the routine indicated by the interrupt number 10 vector. In addition, the I flag is
cleared and the S flag is set. The PC value saved on the stack is the address at which the undefined
instruction is stored. Although processing can be restored with the RETI instruction, this is pointless
because the same exception occurs again.
68
CHAPTER 4
CLOCKS
This chapter explains the clocks used by MB90440G
series microcontrollers.
4.1 Clocks
4.2 Block Diagram of the Clock Generation Block
4.3 Clock Selection Register (CKSCR)
4.4 Clock Mode
4.5 Oscillation Stabilization Wait Interval
4.6 Connection of an Oscillator or an External Clock to the
Microcontroller
69
CHAPTER 4 CLOCKS
4.1
Clocks
The clock generation block controls the operation of the internal clock that controls
operation of the CPU and peripheral functions. This internal clock is called the machine
clock. One internal clock cycle is called one machine cycle. Other clocks include a clock
generated by source oscillation, called an oscillation clock, and a clock generated by
the internal PLL oscillation, called a PLL clock.
■ Clocks
The clock generation block contains the oscillation circuit that generates the oscillation clock. An external
oscillator is attached to this circuit. The oscillation clock can also be supplied by inputting an external clock
to the clock generation block. The clock generation block also contains the PLL clock multiplier circuit,
which generates four clocks whose frequencies are multiples of the oscillation clock frequency. The clock
generation block controls the oscillation stabilization wait interval and PLL clock multiplication as well as
internal clock operation by changing the clock with a clock selector.
● Oscillation clock (HCLK)
The oscillation clock is generated either from an external oscillator attached to the oscillation circuit or by
the input of an external clock.
● Sub clock (SCLK)
The sub clock runs the clock timer and can also be used as a low-speed machine clock.
The sub clock is generated either from an external oscillator attached to the oscillation circuit or by the
input of an external clock.
● Main clock (MCLK)
The main clock, whose frequency is the oscillation clock frequency divided by 2, supplies the clock input
to the time-base timer and the clock selector.
● PLL clock (PCLK)
The PLL clock is obtained by multiplying the oscillation clock frequency with the internal PLL clock
multiplier circuit (PLL oscillation circuit). Selection can be made from among four different PLL clocks.
70
CHAPTER 4 CLOCKS
● Machine clock (φ)
The machine clock controls the operation of the CPU and peripheral functions. One clock cycle is regarded
as one machine cycle (1/φ). An operating machine clock can be selected from among the main clock (whose
frequency is the source clock frequency divided by 2) and the other four clocks (whose frequencies are
multiples of the source clock frequency).
Note:
When the operating voltage is 5V, the oscillation clock can oscillate at 3 MHz to 16 MHz. The
maximum operating frequency of the CPU or resources is 16 MHz. If a multiplication rate that
exceeds the maximum operating frequency is set, the device does not operating normally. If the
oscillation clock is 16 MHz, the multiplication rate of PLL clock can only be set to x1. The PLL
oscillator oscillates in the range of 3 MHz to 16 MHz, which varies depending on the operating
voltage and multiplication rate.
■ Clock Supply Map
Since the machine clock generated in the clock generation block is supplied as the clock that controls the
operation of the CPU and peripheral functions, the operation of the CPU and the peripheral functions is
affected by switching between the main clock and the PLL clock (clock mode) and by a change in the PLL
clock multiplier. Since some peripheral functions receive frequency-divided output from the time-base
timer, a peripheral unit can select the clock best suited for this operation. Figure 4.1-1 shows the clock
supply map.
71
CHAPTER 4 CLOCKS
Figure 4.1-1 Clock supply map
Peripheral function
4
4
Watchdog timer
8/16-bit PPG
timer 0/1/2/3
PPG0 to PPG3
Pin
TIN0
Clock generation block
Watch timer
16-bit reload
timer 0
Time-base timer
Pin
TOT0
Pin
Prescaler
SCK0,SIN0
X0A
Pin
X1A
Pin
Pin
Sub clock
generation
circuit
1 2 3 4
X1
Pin
System
clock
generation
circuit
HCLK
Divideby-4
Divideby-2
Pin
Oscillation
clock
PCLK
SCK1,SIN1
Pin
PLL
clock
UART1
Clock selecter
MCLK
Main clock
SOT0
Prescaler
PLL multiplier circuit
X0
Pin
UART0
SOT1
Pin
Machine
clock
Prescaler
SIO
SCK2,SIN2
Pin
SOT2
Pin
RX0 to RX2
CPU
Pin
CAN
TX0 to TX2
Pin
TIN1
Pin
16-bit reload timer 1
TOT1
Pin
OUT0 to OUT3
16-bit output
compare
Pin
16-bit free-run timer
IN0 to IN7
16-bit input capture
Pin
AN0 to AN7
Pin
HCLK:
MCLK:
PCLK:
:
72
Oscillation clock
Main clock
PLL clock
Machine clock
10-bit A/D converter
ADTG
Pin
4
Oscillation stabilization wait control
CHAPTER 4 CLOCKS
4.2
Block Diagram of the Clock Generation Block
The clock generation block consists of five blocks:
• System clock generation circuit
• PLL multiplier circuit
• Clock selector
• Clock selection register (CKSCR)
• Oscillation stabilization wait interval selector
■ Block Diagram of the Clock Generation Block
Figure 4.2-1 shows a block diagram of the clock generation block, including the standby control circuit and
the time-base timer circuit.
Figure 4.2-1 Block Diagram of the Clock Generation Block
Standby control circuit
Low Power Consumption Mode Control Register (LPMCR)
STP SLP SPL RST TMD CG1 CG0 RESV
CPU intermittend
operation cycle
selector
2
Stop signal
CPU clock
control circuit
Sleep signal
Peripheral clock
control circuit
S
Q
S
R
Reset
S
CPU operation
clock
Peripheral function
operation clock
Q
R
Q
S
Q
Interrupt
R
R
Standart Control Circuit
Clock
Selector
Oscillation
stabilization
wait time
interval selector
2
2
SCM MCM WS1 WS0 SCS MCS CS1 CS0
PLL multiplier circuit
Clock Selection register (CKSCR)
Mainclock
X0
Pin
HCLK
X1
Divideby-2
Pin
Divideby-512
Divideby-2
Divideby-2
Divideby-2
Divideby-2
Divideby-2
Divideby-4
Time-base Timer
System clock
generation circuit
Watchdog Timer
Sub clock generation circuit
X0A Pin
Divideby-4
Divideby-4
Clocktimer
Sub clock
Divideby-1024
Divideby-8
Divideby-2
Divideby-2
X1A Pin
73
CHAPTER 4 CLOCKS
● System clock generation circuit
The system clock generation circuit generates an oscillation clock (HCLK) from an external oscillator
attached to it. Alternatively, an external clock can be input to this circuit.
● Sub clock generation circuit
The sub clock generation circuit generates a sub clock (SCLK) from an external oscillator attached to it. An
external clock can be also input to this circuit.
● PLL multiplier circuit
The PLL multiplier circuit multiplies the oscillation clock frequency through PLL oscillation and supplies a
clock whose frequency is a multiple of the oscillation clock frequency to the CPU clock selector.
● Clock selector
From among the main clock and four different PLL clocks, the clock selector selects the clock that is
supplied to the CPU and peripheral clock control circuits.
● Clock selection register (CKSCR)
The clock selection register is used to switch between the oscillation clock and a PLL clock and is also used
to select an oscillation stabilization wait interval and a PLL clock multiplier.
● Oscillation stabilization wait interval selector
This oscillation stabilization wait interval selector selects an oscillation stabilization wait interval for the
oscillation clock when the stop mode is released or when a watchdog timer reset occurs. Selection is made
from among three different time-base timer outputs. In all other cases, an oscillation stabilization wait
interval is not selected.
74
CHAPTER 4 CLOCKS
4.3
Clock Selection Register (CKSCR)
The clock selection register (CKSCR) is used to switch between the main clock and a
PLL clock and is also used to select an oscillation stabilization wait interval and a PLL
clock multiplier.
■ Configuration of the Clock Selection Register (CKSCR)
Figure 4.3-1 shows the configuration of the clock selection register (CKSCR). Table 4.3-1 describes the
function of each bit of the clock selection register (CKSCR).
Figure 4.3-1 Configuration of the Clock Selection Register (CKSCR)
Address
0000A1H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
SCM
MCM WS1
WS0
SCS
MCS
CS1
CS0
R/W
R/W
R/W
R/W
R/W
R
R
R/W
CS1 CS0
bit7
bit0 Initial value
(LPMCR)
Multiplier selection bits
The resulting clock for an oscillation clock
of 4 MHz is given in parentheses.
0
0
1 x HCLK (4MHz)
0
1
2 x HCLK (8MHz)
1
0
3 x HCLK (12MHz)
1
1
4 x HCLK (16MHz)
Machine clock selection bit
MCS
0
PLL clock selected.
1
Main clock selected.
Machine clock selection bit (sub)
SCS
0
1
11111100B
Sub clock selected.
Main clock selected.
Oscillation stabilization wait interval selection bits
WS1 WS0 The corresponding time interval for an oscillation
clock of 4 MHz is given in parentheses.
0
0
0
1
213/ HCLK (aprox. 2.05 ms)
1
0
215/ HCLK (aprox. 8.19 ms)
1
1
217/ HCLK (aprox. 32.77 ms)*1
*1 When a power-on reset occurs, the oscillation
stabilization wait time is 218/HCLK (aprox. 65.54 ms).
MCM
0
Machine clock indication bit
Running on a PLL clock.
1
Running on the main clock.
SCM
HCLK : Oscillation clock
R/W : Readable/Writable
: Read only
R
: Unused
: Initial value
0
1
Machine clock indication bit (sub)
Running on the sub clock.
Running on the main clock.
75
CHAPTER 4 CLOCKS
Note:
The machine clock selection bit is initialized to main clock selection at a reset.
Table 4.3-1 Function Description of Each Bit of the Clock Selection Register (CKSCR) (1/3)
Bit name
Function
•
bit15
SCM:
Machine clock
indication bit (sub)
This bit indicates whether the main clock or sub clock has been
selected as the machine clock.
• When this bit is "0", the sub clock has been selected. When it is
"1", the main clock has been selected.
• If SCS = 1 and SCM = 0, the main clock oscillation stabilization
wait interval is in effect.
• Writing to this bit has no effect on operation.
•
bit14
MCM:
Machine clock
indication bit
This bit indicates whether the main clock or a PLL clock has
been selected as the machine clock.
• When this bit is "0", a PLL clock has been selected. When it is
"1", the main clock has been selected.
• If MCS = 0 and MCM = 1, the PLL clock oscillation
stabilization wait interval is in effect.
• Writing to this bit has no effect on operation.
•
bit13,
bit12
76
WS1, WS0:
Oscillation
stabilization wait
interval selection
bits
These bits select an oscillation stabilization wait interval of the
oscillation clock when stop mode was released, when transition
occurred from sub clock mode to main clock mode, or when
transition occurred from sub clock mode to PLL clock mode.
• These bits are initialized to "11B" by all reset causes.
(Note)
The oscillation stabilization wait interval must be set to a value
appropriate for the oscillator used. See Section "6.2 Reset Cause
and Oscillation Stabilization Wait Intervals". These bits can be
reset to "00B" only for main clock mode.
(Reference)
When main clock mode is switched to PLL clock mode, the
oscillation stabilization wait interval is fixed at 214/HCLK (that
is, the oscillation stabilization wait interval is approximately 4.1
ms when the oscillation clock frequency is 4 MHz). When sub
clock mode is switched to PLL clock mode or when PLL stop
mode is released, the oscillation stabilization wait interval uses
the specified values in the WS1 and WS0 bits. For PLL
oscillation stabilization, at least 214/HCLK is required.
Accordingly, when sub clock mode is switched to PLL clock
mode, or when PLL clock mode is switched to PLL stop mode,
set WS1 and WS0 bits to "10B" or "11B".
CHAPTER 4 CLOCKS
Table 4.3-1 Function Description of Each Bit of the Clock Selection Register (CKSCR) (2/3)
Bit name
Function
•
bit11
SCS:
Machine clock
selection bit (sub)
This bit specifies whether the main clock or sub clock is selected
as the machine clock.
• If "0" is written when this bit is "1", the mode is switched to the
sub clock mode by synchronizing with the sub clock (about 130
µs).
• If this bit has been set to "0" and "1" is written to it, the
oscillation stabilization wait interval for the main clock starts.
As a result, the time-base timer is automatically cleared.
• When the sub clock has been selected, the operating clock
frequency is the sub clock frequency divided by 4 (that is, the
machine clock frequency is 8 kHz when the sub clock oscillation
frequency is 32 kHz).
• If both the SCS and MCS bits are "0", the SCS bit takes
precedence, that is, the sub clock is selected.
• This bit is initialized to "1" by all reset causes.
(Note)
The oscillation stabilization wait time of the sub clock (about 2s)
is generated when the power is turned on or the stop mode is
canceled. Thus, if the mode is switched from the main cock
mode to the sub clock mode during this period, an oscillation
stabilization wait time is generated.
•
bit10
MCS:
Machine clock
selection bit
This bit specifies whether the main clock or a PLL clock is
selected as the machine clock.
• When this bit is "0", a PLL clock is selected. When it is "1", the
main clock is selected.
• If this bit has been set to "1" and "0" is written to it, the
oscillation stabilization wait interval for the PLL clock starts. As
a result, the time-base timer is automatically cleared, and the
TBOF bit of the time-base timer control register (TBTC) is also
cleared.
• When main clock mode is switched to PLL clock mode, the
oscillation stabilization wait interval is fixed at 214/HCLK (that
is, the oscillation stabilization wait interval is approximately 4.1
ms when the oscillation clock frequency is 4 MHz). When sub
clock mode is switched to PLL clock mode or when PLL stop
mode is released, the oscillation stabilization wait interval uses
the specified values in the WS1 and WS0 bits. For PLL
oscillation stabilization, at least 214/HCLK is required.
Accordingly, when sub clock mode is switched to PLL clock
mode, or when PLL clock mode is switched to PLL stop mode,
set the WS1 and WS0 bits to "10B" or "11B".
• When the main clock has been selected, the operating clock
frequency is the oscillation clock frequency divided by 2 (that is,
the operating clock is 2 MHz when the oscillation clock
frequency is 4 MHz).
• This bit is initialized to "1" by all reset causes.
(Note)
When the MCS bit is "1", write "0" to it only when the time-base
timer interrupt is masked by the TBIE bit of the time-base timer
control register (TBTC) or the interrupt level register (ILM).
77
CHAPTER 4 CLOCKS
Table 4.3-1 Function Description of Each Bit of the Clock Selection Register (CKSCR) (3/3)
Bit name
bit9,
bit8
CS1, CS0:
Multiplier selection
bits
HCLK: Oscillation clock
78
Function
• These bits select a PLL clock multiplier.
• Selection can be made from among four different multipliers.
• These bits are initialized to "00B" by all reset causes.
(Note)
When the MCS or MCM bit is "0", writing to these bits is not
allowed. Write to the CS1 and CS0 bits only after setting the
MCS bit to "1" (main clock mode).
CHAPTER 4 CLOCKS
4.4
Clock Mode
Three clock modes are provided: main clock mode, PLL clock mode and sub clock
mode.
■ Main Clock Mode, PLL Clock Mode and Sub Clock Mode
● Main clock mode
In main clock mode, a clock whose frequency is the oscillation clock frequency divided by 2 is used as the
operating clock for the CPU and peripheral resources, and the PLL clocks are disabled.
● PLL clock mode
In PLL clock mode, a PLL clock is used as the operating clock for the CPU and peripheral resources. A
PLL clock multiplier is selected with the clock selection register (CKSCR: CS1 and CS0).
● Sub clock mode
In sub clock mode, a clock whose frequency is the sub clock frequency divided by 4 is used as the
operating clock for the CPU and peripheral resources, and the main clock and PLL clocks are disabled.
■ Clock Mode Transition
Transition among main clock mode, PLL clock mode, and sub clock mode is performed by writing to the
MCS and SCS bits of the clock selection register (CKSCR).
● Transition from main clock mode to PLL clock mode
When the MCS bit of the clock selection register (CKSCR) is rewritten from "1" to "0" in main clock
mode, switching from the main clock to a PLL clock occurs after the PLL clock oscillation stabilization
wait interval (214/HCLK).
● Transition from PLL clock mode to main clock mode
When the MCS bit of the clock selection register (CKSCR) is rewritten from "0" to "1" in PLL clock mode,
switching from the PLL clock to the main clock occurs when the edges of the PLL clock and the main
clock coincide (after 1 to 8 PLL clocks).
● Transition from main clock mode to sub clock mode
When the SCS bit of the clock selection register (CKSCR) is rewritten from "1" to "0" in main clock mode,
switching from the main clock to a sub clock occurs by synchronizing with the sub clock (about 130µs).
79
CHAPTER 4 CLOCKS
● Transition from sub clock mode to main clock mode
When the SCS bit of the clock selection register (CKSCR) is rewritten from "0" to "1" in sub clock mode,
switching from the sub clock to the main clock occurs after the main clock oscillation stabilization wait
interval. The oscillation stabilization wait interval is selected based on the WS1 and WS0 bits of the clock
selection register (CKSCR).
Note:
When the sub clock mode is switched to main clock mode using an external reset pin (RST pin),
input level "L" for at least the oscillation time of the oscillator * + 100 µs + 16 machine cycles.
* : The oscillation time of the oscillator is the time required to reach 90% of amplitude. It takes
several to dozens of ms for crystal oscillators, hundreds of µs to several ms for ceramic
oscillators, and 0 ms for external clocks.
● Transition from PLL clock mode to sub clock mode
When the SCS bit of the clock selection register (CKSCR) is rewritten from "1" to "0" in PLL clock mode,
switching from the PLL clock to the sub clock occurs.
● Transition from sub clock mode to PLL clock mode
When the SCS bit of the clock selection register (CKSCR) is rewritten from "0" to "1" in sub clock mode,
switching from the sub clock to a PLL clock occurs after the main clock oscillation stabilization wait
interval. The oscillation stabilization wait interval is selected based on the WS1 and WS0 bits of the clock
selection register (CKSCR).
Notes:
• Even though the MCS and SCS bits of the clock selection register (CKSCR) are rewritten,
machine clock switching does not occur immediately. When operating a resource that depends on
the machine clock, confirm that machine clock switching has been performed by referring to the
MCM and SCM bits of the clock selection register (CKSCR) before operating the resource.
• When the clock mode is switched, do not switch to other clock mode and low power consumption
mode before this switching is completed. Confirm the completion of clock mode switching by
referring to the MCM and SCM bits of the clock selection register (CKSCR).
• If both the SCS and MCS bits are "0", the SCS bit takes precedence, that is, sub clock mode is
selected.
■ Selection of a PLL Clock Multiplier
Writing a value from "00B" to "11B" to the CS1 and CS0 of the clock selection register (CKSCR) selects a
PLL clock multiplier of 1 to 4.
■ Machine Clock
The machine clock may be a PLL clock output from the PLL multiplier circuit, a clock whose frequency is
the source oscillation frequency divided by 2, or a clock whose frequency is the sub clock frequency
divided by 4. This machine clock is supplied to the CPU and peripheral functions. The main clock, PLL
clock, or sub clock can be selected by writing to the MCS or SCS bit of the clock selection register
(CKSCR).
80
CHAPTER 4 CLOCKS
Figure 4.4-1 shows the status change caused by machine clock switching.
Figure 4.4-1 Status Change Diagram for Machine Clock Selection
Main
MCS = 1
MCM = 1
SCS = 1
SCM = 1
CS1, CS0 = xx
(8)
(10)
(16)
(7)
(7)
(10)
(11)
Main
PLLx
MCS = 0
MCM = 1
SCS = 1
SCM = 1
CS1, CS0 = xx
(7)
(9)
(1)
(6)
(7)
Main
Sub
MCS = 1
MCM = 1
SCS = 0
SCM = 1
CS1, CS0 = xx
(2)
Sub
Main
MCS = 1
MCM = 1
SCS = 1
SCM = 0
CS1, CS0 = xx
Sub
MCS = X
MCM = 1
SCS = 0
SCM = 0
CS1, CS0 = xx
(9)
(8)
(12)
(3)
(13)
(4)
(14)
(5)
(15)
Sub
PLL
MCS = 0
MCM = 1
SCS = 1
SCM = 0
CS1, CS0 = xx
PLL1
Main
MCS = 1
MCM = 0
SCS = 1
SCM = 1
CS1, CS0 = 00
PLL1: Multiplied
MCS = 0
MCM = 0
SCS = 1
SCM = 1
(8)
(6)
CS1, CS0 = 00
PLL1
Sub
MCS = 1
MCM = 0
SCS = 0
SCM = 1
CS1, CS = 00
(17)
PLL2
Main
MCS = 1
MCM = 0
SCS = 1
SCM = 1
CS1, CS0 = 01
PLL2: Multiplied
MCS = 0
MCM = 0
SCS = 1
(6) SCM = 1
(8)
CS1, CS0 = 01
PLL2
Sub
MCS = 1
MCM = 0
SCS = 0
SCM = 1
CS1, CS0 = 01
(17)
PLL3
Main
MCS = 1
MCM = 0
SCS = 1
SCM = 1
CS1, CS0 = 10
PLL3: Multiplied
MCS = 0
MCM = 0
SCS = 1
(8)
SCM = 1
CS1, CS0 = 10
PLL3
Sub
MCS = 1
MCM = 0
SCS = 0
SCM = 1
CS1, CS0 =10
(17)
PLL4
Sub
MCS = 1
MCM = 0
SCS = 0
SCM = 1
CS1, CS0 = 11
(17)
PLL4
Main
MCS = 1
MCM = 0
SCS = 1
SCM= 1
CS1, CS0 = 11
(6)
PLL4: Multiplied
MCS = 0
MCM = 0
SCS = 1
(8)
(6) SCM = 1
CS1, CS0 = 11
81
CHAPTER 4 CLOCKS
(1)
Writing "0" to the MCS bit
(2)
End of PLL clock oscillation stabilization wait & CS1 and CS0 = 00
(3)
End of PLL clock oscillation stabilization wait & CS1 and CS0 = 01
(4)
End of PLL clock oscillation stabilization wait & CS1 and CS0 = 10
(5)
End of PLL clock oscillation stabilization wait & CS1 and CS0 = 11
(6)
Writing "1" to the MCS bit (including reset)
(7)
Timing of synchronization between the PLL clock and the main clock
(8)
Writing "0" to the SCS bit
(9)
Timing of synchronization between the main clock and the sub clock.
(10)
Writing "1" to the SCS bit (MCS = 1)
(11)
End of main clock oscillation stabilization wait
(12)
End of main clock oscillation stabilization wait & CS1 and CS0 = 00
(13)
End of main clock oscillation stabilization wait & CS1 and CS0 = 01
(14)
End of main clock oscillation stabilization wait & CS1 and CS0 = 10
(15)
End of main clock oscillation stabilization wait & CS1 and CS0 = 11
(16)
Writing "1" to the SCS bit (MCS = 0)
(17)
Timing of synchronization between the PLL clock and the sub clock
MCS
: Machine clock selection bit of the clock selection register (CKSCR)
MCM
: Machine clock indication bit of the clock selection register (CKSCR)
SCS
: Machine clock selection bit of the clock selection register (CKSCR) (sub)
SCM
: Machine clock indication bit of the clock selection register (CKSCR) (sub)
CS1, CS0
: Multiplier selection bits of the clock selection register (CKSCR)
Notes:
• The initial value for the machine clock setting is main clock (MCS and SCS of CKSCR = 1).
• If both the SCS and MCS bits are "0", the SCS bit takes precedence, that is, the sub clock is
selected.
• When sub clock mode is switched to PLL clock mode, set the WS1 and WS0 bits of CKSCR to
"10B" or "11B".
82
CHAPTER 4 CLOCKS
4.5
Oscillation Stabilization Wait Interval
When the power is turned on, when stop mode is released, or switching from the sub
clock to the main clock or from sub clock to the PLL clock occurs, an oscillation
stabilization wait interval is required after oscillation begins because there is no
oscillation. When switching from the main clock to the PLL clock or from the main clock
to the sub clock occurs, an oscillation stabilization wait interval is required.
■ Oscillation Stabilization Wait Interval
Ceramic and crystal oscillators generally require several to dozens of ms to stabilize at their natural
frequency (oscillation frequency) when oscillation starts. For this reason, CPU operation is not allowed
immediately after oscillation starts but is allowed only after full oscillation stabilization. After the
oscillation stabilization wait interval has elapsed, the clock is supplied to the CPU. Because the oscillation
stabilization time depends on the type of oscillator (crystal, ceramic, etc.), the proper oscillation
stabilization wait interval for the oscillator used must be selected. An oscillation stabilization wait interval
is selected by setting the clock selection register (CKSCR).
When clock mode is switched from main clock to PLL clock, main clock to sub clock, sub clock to main
clock, or sub clock to PLL clock, the CPU runs in the clock mode set before switching for the oscillation
stabilization wait time. After the oscillation stabilization wait time has elapsed, the CPU changes to the
specified clock mode.
Figure 4.5-1 shows the operation immediately after oscillation starts.
Figure 4.5-1 Operation Immediately after Oscillation Starts
Oscillator-activated
oscillation time
Start of oscillation
Oscillation stabilization wait interval
Normal operation start or
switching to PLL clock/sub clock
Stable oscillation
83
CHAPTER 4 CLOCKS
4.6
Connection of an Oscillator or an External Clock to the
Microcontroller
The MB90440G series microcontroller contains a system clock generation circuit.
Connecting an external oscillator to this circuit generates the system clock.
Alternatively, an externally generated clock can be input to the microcontroller.
■ Connection of an Oscillator or an External Clock to the Microcontroller
● Example of connecting a crystal or ceramic oscillator to the microcontroller
Connect a crystal or ceramic oscillator as shown in the example in Figure 4.6-1 .
Figure 4.6-1 Example of Connecting a Crystal or Ceramic Oscillator to the Microcontroller
MB90440G series
X0(X0A)
X1(X1A)
● Example of connecting an external clock to the microcontroller
As shown in the example in Figure 4.6-2 , connect an external clock to pin X0 (X0A). Pin X1 (X1A) must
be open.
84
CHAPTER 4 CLOCKS
Figure 4.6-2 Example of Connecting an External Clock to the Microcontroller
MB90440G series
X0(X0A)
X1(X1A)
Open
85
CHAPTER 4 CLOCKS
86
CHAPTER 5
LOW-POWER
CONSUMPTION MODE
This chapter explains the low-power consumption mode
of MB90440G series microcontrollers.
5.1 Overview of Low-Power Consumption Mode
5.2 Block Diagram of the Low-Power Consumption Control Circuit
5.3 Low-Power Consumption Mode Control Register (LPMCR)
5.4 CPU Intermittent Operation Mode
5.5 Standby Mode
5.6 Status Change Diagram
5.7 Status of Pins in Standby Mode and during Hold and Reset
5.8 Usage Notes on Low-Power Consumption Mode
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CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.1
Overview of Low-Power Consumption Mode
The MB90440G series has the following CPU operating modes, any of which can be
used depending on operating clock selection and clock operation control:
• Clock mode (PLL clock mode, main clock mode, or sub clock mode)
• CPU intermittent operating mode (PLL clock intermittent operating mode, main clock
intermittent operating mode, or sub clock intermittent operating mode)
• Standby mode (sleep mode, time-base timer mode, stop mode, or watch mode)
■ CPU Operating Modes and Current Consumption
Figure 5.1-1 shows the relationship between the CPU operating modes and current consumption.
Figure 5.1-1 CPU Operating Mode and Current Consumption
Current consumption
Several tens
of mA
CPU operating
mode
PLL clock mode
Multiplied-by-four clock
Multiplied-by-three clock
Multiplied-by-two clock
Multiplied-by-one clock
Multiplied-by-four clock
PLL clock intermittent
operating mode
Multiplied-by-three clock
Multiplied-by-two clock
Multiplied-by-one clock
Main clock mode (1/2HCLK)
Main clock intermittent operating mode
Sub clock mode
Sub clock intermittent operating mode
Several mA
Standby mode
Sleep mode
Time-base timer mode
Watch mode
Stop mode
Several
Hardware standby mode
A
Low-power consumption mode
Note:
This figure is only an indication of the degree of power consumption for each mode. Actual current
consumption values may not agree with those in the figure.
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CHAPTER 5 LOW-POWER CONSUMPTION MODE
■ Clock Mode
● PLL clock mode
In this mode, a PLL clock that is a multiple of the oscillation clock (HCLK) is used to operate the CPU and
peripheral functions.
● Main clock mode
In this mode, the main clock, with the oscillation clock (HCLK) frequency divided by 2 is used to operate
the CPU and peripheral functions. In the main clock mode, the PLL multiplier circuit is inactive.
● Sub clock mode
In this mode, the sub clock, with the sub clock (SCLK) frequency divided by 4 is used to operate the CPU
and peripheral functions. In the sub clock mode, the main clock and PLL multiplier circuit are inactive.
Reference:
For the clock mode, see Section "4.4 Clock Mode".
■ CPU Intermittent Operating Mode
In this mode, the CPU is operated intermittently while high-speed clock pluses are supplied to peripheral
functions, thereby reducing power consumption. In this mode, intermittent clock pulses are supplied only to
the CPU while it is accessing a register, internal memory, peripheral
function, or external unit.
■ Standby Mode
In this mode, the low-power consumption control circuit stops supplying the clock to the CPU (sleep mode)
or the CPU and peripheral functions (time-base timer mode) or stops the oscillation clock itself (stop
mode), thereby reducing power consumption.
● PLL sleep mode
The PLL sleep mode is activated to stop the CPU operating clock in the PLL clock mode. Components
excluding the CPU operate on the PLL clock.
● Main sleep mode
The main sleep mode is activated to stop the CPU operating clock in the main clock mode. Components
excluding the CPU operate on the main clock.
● Sub-sleep mode
The sub-sleep mode activated to stop the CPU operating clock in the sub clock mode. Components
excluding the CPU operate on the divided-by-four sub clock.
● Time-base timer mode
The time-base timer mode causes the operation of functions, excluding the oscillation clock, time-base
timer, and clock timer, to stop. All functions other than the time-base timer and clock timer are inactivated.
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CHAPTER 5 LOW-POWER CONSUMPTION MODE
● Watch mode
The watch mode operates the clock timer only. The sub clock operates and the main clock and PLL
multiplier circuit stop.
● Stop mode
The stop mode cause the oscillation to stop. All functions are inactivated.
Note:
Because the stop mode turns the oscillation clock off, data can be retained by the lowest power
consumption.
When the clock mode is switched, do not switch to other clock mode and low-power consumption
mode before this switching is completed. Confirm the completion of clock mode switching by
referring to the MCM and SCM bits of the clock selection register (CKSCR).
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CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.2
Block Diagram of the Low-Power Consumption Control
Circuit
The low-power consumption control circuit consists of the following seven blocks:
• CPU intermittent operation selector
• Standby control circuit
• CPU clock control circuit
• Peripheral clock control circuit
• Pin high-impedance control circuit
• Internal reset generation circuit
• Low-power consumption mode control register (LPMCR)
■ Block Diagram of the Low-Power Consumption Control Circuit
Figure 5.2-1 shows a block diagram of the low-power consumption control circuit.
Figure 5.2-1 Block Diagram of the Low-Power Consumption Control Circuit
Low power consumption mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0
SSR
Pin highimpedance
control circuit
RST
Internal reset
Internal reset
generation
circuit
Intermittent cycle
selection
Pin
CPU intermittent
operation selector
CPU clock
control circuit
Standby
control circuit
2
Interrupt clearing
Pin Hi-Z control
CPU clock pulse
Stop and sleep signals
Stop signal
HCLK : Oscillation clock
MCLK : Main clock
SCLK : Sub clock
Peripheral clock
control circuit
Machine clock
Peripheral clock
Sub clock oscillation stabilization wait time
Clock generation part
Main clock oscillation stabilization wait time Oscillation
stabilization
wait time
2
selector
Clock selector
2
PLL multiplier circuit
System clock
generation
circuit
X0 Pin
HCLK
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock selection register (CKSCR)
Divide
by 2
MCLK
Divide
by 512
Divide
by 4
Divide
by 2
Divide
by 2
Divide
by 2
Divide
by 2
Divide
by 2
Divide
by 4
Time-base timer
X1 Pin
to Watchdog timer
SCLK
X0A Pin
Divide
by 4
X1A Pin
Sub clock oscillation
generation circuit
Watch timer
Divide by
1024
Divide
by 8
Divide
by 2
Divide
by 2
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CHAPTER 5 LOW-POWER CONSUMPTION MODE
● CPU intermittent operation selector
This selector selects the number of clock pulses to halt the CPU during the CPU intermittent operation
mode.
● Standby control circuit
The standby control circuit controls the CPU clock control and the peripheral clock control circuits and
turns the low-power consumption mode on and off.
● CPU clock control circuit
This circuit controls clocks supplied to the CPU. This circuit controls clocks supplied to peripheral
functions for the peripheral clock control circuit.
● Peripheral clock control circuit
This circuit controls clocks supplied to peripheral functions.
● Pin high-impedance control circuit
This circuit makes external pins high-impedance in the time-base timer mode and stop mode. For pins with
the pull-up option, this circuit disconnects the pull-up resistor in the stop mode.
● Internal reset generation circuit
This circuit generates an internal reset signal.
● Low-power consumption mode control register (LPMCR)
This register is used to switch to and release the standby mode and to set the CPU intermittent operation
function.
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CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.3
Low-Power Consumption Mode Control Register (LPMCR)
This register switches to or releases the low-power consumption mode. This register
also sets the number of CPU clock pulses to halt during the CPU intermittent operation
mode.
■ Low-Power Consumption Mode Control Register (LPMCR)
Figure 5.3-1 shows the configuration of the low-power consumption mode control register (LPMCR).
Figure 5.3-1 Configuration of the Low-Power Consumption Mode Control Register (LPMCR)
bit15
Address
0000A0H
(CKSCR)
bit8
bit7
bit7
bit6
bit6
bit5
bit5
bit4
bit4
bit3
bit2
bit1
STP
SLP
SPL
RST
TMD
CG1
CG0 RESV
SSR
W
W
R/W
W
R/W
R/W
R/W
SSR
RESV
0
00011000B
R/W
DRAM
self refresh control bit
Reserved
Count bit for CPU clock temporary halt cycle
0
0
0 cycles (CPU clock = Resource clock)
0
1
8 cycles (CPU clock:Resource clock = 1:3 to 4 approx.)
1
0
16 cycles (CPU clock:Resource clock = 1:5 to 6 approx.)
1
1
32 cycles (CPU clock:Resource clock = 1:9 to 10 approx.)
TMD
Time-base timer mode bit
0
Switches to the time-base timer mode.
1
No change, no effect on operation
RST
Internal reset signal generation bit
0
Generates an internal reset signal of three machine cycles.
1
No change, no effect on operation
Watch and pin state setting bit
(for time-base timer mode and stop mode)
SPL
0
Retained
1
High impedance
SLP
Sleep mode bit
0
No change, no effect on operation
1
Switches to sleep mode.
STP
: Readable/Writable
: Write only
: nitial value
Initial value
Does
notwrite
control
Always
"0"DRAMC
to this self
bit refresh in the sleep mode.
CG1 CG0
R/W
W
bit0
Stop mode bit
0
No change, no effect on operation
1
Switches to stop mode.
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CHAPTER 5 LOW-POWER CONSUMPTION MODE
Table 5.3-1 Function Description of Each Bit of the Low-power Consumption Mode Control Register
(LPMCR)
Bit name
STP:
Stop mode bit
•
•
•
•
•
This bit indicates switching to the stop mode.
When "1" is written to this bit, a switch to the stop mode is performed.
Writing "0" in this bit has no effect on operation.
This bit is cleared to "0" by a reset or when an interrupt request occurs.
The read value of this bit is always"0".
bit6
SLP:
Sleep mode bit
•
•
•
•
•
This bit indicates switching to a sleep mode.
When "1" is written to this bit, a switch to a sleep mode is performed.
Writing "0" in this bit has no effect on operation.
This bit is cleared to "0" by a reset or when an interrupt request occurs.
The read value of this bit is always "0".
bit5
SPL:
Pin state setting bit
(for watch mode,
time-base timer
mode, and stop
mode)
•
•
•
•
This bit is enabled only in the watch mode, time-base timer mode, and stop mode.
When this bit is "0", the level of the external pins is retained.
When this bit is "1", the status of the external pins changes to high-impedance.
This bit is initialized to "0" by a reset.
bit4
RST:
Internal reset signal
generation bit
• When "0" is written to this bit, an internal reset signal of three machine cycles is
generated.
• Writing "1" in this bit has no effect on operation.
• The read value of this bit is always "1".
bit3
TMD:
Watch/time-base
timer mode bit
• This bit indicates switching to the watch mode or time-base timer mode.
• When "0" is written to this bit in the main clock mode or PLL clock mode, a switch
to time-base timer mode is performed.
• When "0" is written to this bit in the sub clock mode, a switch to the watch mode is
performed.
• This bit is cleared to "1" by a reset or when an interrupt request occurs.
• The read value of this bit is always "1".
bit2,
bit1
CG1, CG0:
Bits for selecting
clock count for
CPU temporary
halt cycle
• These bits set the number of CPU clock pulses per cycle to halt the CPU for the
CPU intermittent operation function.
• The clock supplied to the CPU is stopped for the specified number of pulses after
the execution of each instruction.
• Four types of clock counts are selectable.
• These bits are initialized to "00B" by a reset.
bit0
RESV:
Reserved bit
bit7
94
Function
Always write "0" to this bit.
CHAPTER 5 LOW-POWER CONSUMPTION MODE
■ Access to the Low-Power Consumption Mode Control Register
Switching to a low-power consumption mode (including the stop mode, sleep mode, time-base timer mode,
and watch mode) is performed by writing the low-power consumption mode control register. Only the
instructions listed in Table 5.3-2 should be used for this purpose.
The low-power consumption mode transition instruction in Table 5.3-2 must always be followed by an
array of instructions highlighted by a line below.
MOV LPMCR,#Hxx ;the low-power consumption mode transition instruction in Table 5.3-2
NOP
NOP
JMP $+3
; jump to next instruction
MOV A,#H'10
; any instruction
The devices does not guarantee its operation after returning from the low-power consumption mode if you
place an array of instructions other than the one enclosed in the dotted line. To access the low-power
consumption mode control register (LPMCR) with C language, refer to "■ Notes on Accessing the LowPower Consumption Mode Control Register (LPMCR) to Enter the Standby Mode" in the section "5.8
Usage Notes on Low-Power Consumption Mode". To control functions not listed in Table 5.3-1 , any
instruction can be used.
When word-length is used for writing the low-power consumption mode control register, even addresses
must be used. Using odd addresses to switch to a low-power consumption mode may result in a
malfunction.
Table 5.3-2 Instructions to Be Used for Switching to a Low-Power Consumption Mode
MOV io,#imm8
MOV dir,#imm8
MOV eam,#imm8
MOV eam,Ri
MOV io,A
MOV dir,A
MOV addr16,A
MOV eam,A
MOVW io,#imm16
MOVW dir,#imm16
MOVW eam,#imm16
MOVW eam,RWi
MOVW io,A
MOVW dir,A
MOVW addr16,A
AMOVW eam,A
SETB io:bp
SETB dir:bp
SETB addr16:bp
CLRB io:bp
CLRB dir:bp
CLRB addr16:bp
MOV @RLi+disp8,A
MOVW @RLi+disp8,A
■ Priorities of the STP, SLP, and TMD Bits
If the stop mode, sleep mode, and time-base timer mode are requested concurrently, the stop mode request,
time-base timer mode request, and sleep mode request are given priorities in this order for processing.
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CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.4
CPU Intermittent Operation Mode
This mode is used for intermittent operation of the CPU while external buses and
peripheral functions continue to operate at high speeds. The purpose of this mode is to
reduce power consumption.
■ CPU Intermittent Operation Mode
This mode halts the supply of the clock pulse to the CPU for a certain period. The halt occurs after the
execution of every instruction that accesses a register, internal memory (ROM and RAM), I/O, peripheral
functions, or the external bus. Internal bus cycle activation is therefore delayed. While high-speed
peripheral clock pulses are supplied to peripheral functions, the execution speed of the CPU is reduced,
thereby enabling low-power consumption processing.
• The low-power consumption mode control register (LPMCR: CG1 and CG0) is used to select the
number of clock pulses per halt cycle of the clock supplied to the CPU.
• External bus operation uses the same clock as that used for peripheral functions.
• Instruction execution time in the CPU intermittent mode can be calculated. A correction value should be
obtained by multiplying the execution count of instructions that access a register, internal memory,
internal peripheral functions, or the external bus by the number of clock pulses per halt cycle. Add this
corrective value to the normal execution time. Figure 5.4-1 shows the operating clock pulses during the
CPU intermittent operation mode.
Figure 5.4-1 Clock Pulses during the CPU Intermittent Operation
Peripheral clock
CPU clock
Halt cycle
Execution
cycle of one
instruction
Internal bus activation
96
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.5
Standby Mode
The standby mode includes the sleep (PLL sleep, main sleep, sub-sleep), watch, and
stop modes.
■ Operation Status during Standby Mode
Table 5.5-1 shows operation statuses during standby mode.
Table 5.5-1 Operation Statuses during Standby Mode
Standby mode
Condition
for switch
PLL sleep mode
SCS=1
MCS=0
SLP=1
Main sleep mode
SCS=1
MCS=1
SLP=1
Sub-sleep mode
SCS=0
SLP=1
MCS=X
Time-base timer
mode
(SPL=0)
SCS=1
MCS=X
TMD=0
Time-base timer
mode
(SPL=1)
SCS=1
MCS=X
TMD=0
Watch mode
(SPL=0)
TMD=0
MCS=X
SCS=0
Main
clock
Sub
Clock
Machine
clock
CPU
Peripheral
Pin
Release
event
Active
Sleep mode
Time-base
timer mode
Active
Active
Active
Stop mode
(SPL=0)
STP=1
Inactive
Inactive
Stop mode
(SPL=1)
External
reset
Interrupt
Hi-Z
(*3)
Retained
External
reset
Interrupt
Hi-Z
(*4)
(*1)
Inactive
(*2)
Inactive
Retained
Inactive
Stop mode
Retained
Inactive
Watch mode
TMD=0
MCS=X
SCS=0
External
reset
Interrupt
Inactive
Active
Watch mode
(SPL=1)
Active
STP=1
Inactive
Hi-Z
External
reset
Interrupt
(*5)
*1: The time-base timer and clock timer operate.
*2: The clock timer operates.
*3: Watch timer, time-base timer and external interrupt
*4: Watch timer and external interrupt
*5 :External interrupt
SPL: Pin state setting bit of low-power consumption mode control register (LPMCR)
SLP: Sleep mode bit of low-power consumption mode control register (LPMCR)
STP: Stop mode bit of low-power consumption mode control register (LPMCR)
TMD: Watch and time-base timer mode bit of low-power consumption mode control register (LPMCR)
MCS: Machine clock selection bit of clock selection register (CKSCR)
SCS: Machine clock selection bit (sub) of clock selection register (CKSCR)
Hi-Z: High-impedance
97
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.5.1
Sleep Mode
This mode causes the CPU operating clock to stop while other components continue to
operate. When the low-power consumption mode control register (LPMCR) indicates a
switch to a sleep mode, a switch to the PLL sleep mode occurs if the PLL clock mode
has been set. A switch to the main clock mode occurs if the main clock mode has been
set. A switch to the sub-sleep mode occurs if the sub clock mode has been set.
■ Switching to Sleep Mode
Writing "1" in the SLP bit and the TMD bit and "0" in the STP bit of the low-power consumption mode
control register (LPMCR) triggers a switch to a sleep mode. At this time, if the MCS bit is "0" and the SCS
bit is "1" in the clock selection register (CKSCR), a switch to the PLL sleep mode is triggered. If the MCS
bit and the SCS bit are "1", a switch to the main sleep mode is triggered. If the SCS bit is "0", a switch to
the sub-sleep mode is triggered.
Note:
When "1" is written to the SLP and STP bits at the same time, the STP bit setting overrides the SLP
bit setting and the mode switches to the stop mode. When "1" is written to the SLP bit and "0" is
written to the TMD bit at the same time, the TMD bit setting overrides the SLP bit setting and the
mode switches to the time-base timer mode or watch mode.
● Data retention function
In a sleep mode, the contents of dedicated registers, such as accumulators, and the internal RAM are
retained.
● Hold function
During a sleep mode, the external bus hold function is active. This function sets the hold status when
requested to do so.
● Operation during an interrupt request
Writing "1" in the SLP bit of the low-power consumption mode control register during an interrupt request
does not trigger a switch to a sleep mode. If the CPU does not accept the interrupt, the CPU executes the
next instruction. If the CPU accepts the interrupt, CPU operation immediately branches to the interrupt
processing routine.
● Status of pins
During a sleep mode, all pins (excluding those used for bus I/O or bus control) retain their previous status.
■ Release of Sleep Mode
The low-power consumption control circuit releases sleep modes when a reset is input or an interrupt
occurs.
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CHAPTER 5 LOW-POWER CONSUMPTION MODE
● Return by a reset
A sleep mode is initialized to the main clock mode by a reset.
Note:
When the sub-sleep mode is switched to main clock mode using an external reset pin (RST pin),
input level "L" for at least the oscillation time of the oscillator * + 100 µs + 16 machine cycles.
* : The oscillation time of the oscillator is the time required to reach 90% of amplitude. It takes
several to dozens of ms for crystal oscillators, hundreds of µs to several ms for ceramic
oscillators, and 0 ms for external clocks.
● Return by an interrupt
If an interrupt request of level seven or higher is issued from a peripheral circuit during a sleep mode, the
sleep mode is released. After the mode is released, the interrupt is handled as an ordinary interrupt. If the
interrupt is accepted according to the setting of the I flag of the condition code register (CCR), interrupt
level mask register (ILM), and interrupt control register (ICR), the CPU executes the interrupt processing.
If the interrupt is not accepted, the CPU executes the instruction following the instruction specifying the
sleep mode.
Figure 5.5-1 shows the release of a sleep mode when an interrupt occurs.
Figure 5.5-1 Release of Sleep Mode by Interrupt Occurrence
Interrupt from peripheral function
Set the enable flag.
IL smaller than 7
INT occurrence?
(IL smaller than 7)
Sleep mode is
not released.
Next instruction
is executed.
ILM smaller than IL
Sleep mode is
not released.
Sleep mode is
released.
Next instruction
is executed.
Interrupt is executed.
Note:
When interrupt processing is executed, the CPU normally executes the instruction that follows the
instruction in which switching to a sleep mode has been specified. The CPU then proceeds to
interrupt processing. If the switching to sleep mode and acceptance of an external bus hold request
occur at the same time, however, the CPU may proceed to interrupt processing before executing the
next instruction.
Figure 5.5-2 shows a return from the Sleep mode.
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CHAPTER 5 LOW-POWER CONSUMPTION MODE
Figure 5.5-2 Release of the Sleep Mode (External Reset)
RST pin
Sleep mode
Main clock
Oscillating
PLL clock
Oscillating
CPU clock
PLL clock
CPU operation
inactive
Sleep mode release
100
Reset sequence
Reset cleared
Execution
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.5.2
Time-Base Timer Mode
This mode causes all functions, excluding oscillation, the time-base timer, and the clock
timer, to stop. In this mode, only the time-base timer and clock timer operate.
■ Switching to the Time-base Timer Mode
When "0" is written to the TMD bit of the low-power consumption mode control register (LPMCR) in the
PLL clock mode or main clock mode (CKSCR: SCS = 1), switching to the time-base timer mode occurs.
● Data retention function
In the time-base timer mode, the contents of dedicated registers, such as accumulators, and the internal
RAM are retained.
● Hold function
During the time-base timer mode, because the external bus hold function is inactive, a hold request is not
accepted even if it is input. If a hold request is input during switching to the time-base timer mode, the bus
may remain at high-impedance and prevent the HAK signal from going low.
● Operation during an interrupt request
Writing "0" in the TMD bit of the low-power consumption mode control register (LPMCR) during an
interrupt request does not trigger a switch to the time-base timer mode.
● Status of pins
Whether the external pins in the time-base timer mode retain the state they had immediately before
switching to the time-base timer mode or go to the high-impedance state can be controlled by the lowpower consumption mode control register (LPMCR: SPL).
■ Release of Time-base Timer Mode
The low-power consumption control circuit releases the time-base timer mode when a reset is input or an
interrupt occurs.
● Return by a reset
The time-base timer mode is initialized to the main clock mode by a reset.
● Return by an interrupt
If a watch timer, time-base timer, or external interrupt generates an interrupt request at an interrupt level
higher than 7 during the time-base timer mode (IL2, IL1, and IL0 of the interrupt control register (ICR) do
not indicate "111B"), the low-power consumption mode control circuit releases the time-base timer mode.
After the mode is released, the interrupt is handled as an ordinary interrupt. If the interrupt is accepted
according to the setting of the I flag of the condition code register (CCR), interrupt level mask register
(ILM), or interrupt control register (ICR), the CPU executes the interrupt processing. If the interrupt is not
accepted, the CPU executes the instruction following the instruction specifying the time-base timer mode.
101
CHAPTER 5 LOW-POWER CONSUMPTION MODE
Note:
When interrupt processing is executed, the CPU normally executes the instruction following the
instruction in which switching to the time-base timer mode has been specified. The CPU then
proceeds to interrupt processing. If the switching to the time-base timer mode and acceptance of an
external bus hold request occur at the same time, however, the CPU may proceed to interrupt
processing before executing the next instruction.
Figure 5.5-3 shows a return from the time-base timer mode.
Figure 5.5-3 Release of the time-base timer mode (External Reset)
RST pin
Time-base
timer mode
Main clock
Oscillating
PLL clock
Oscillation stabilization wait time
Main clock
CPU clock
CPU operation
inactive
Time-base timer mode release
102
Reset sequence
Reset cleared
Oscillating
PLL clock
Execution
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.5.3
Watch Mode
This mode causes all functions, excluding the sub clock and clock timer, to stop. In this
mode almost all chip functions stop.
■ Switching to the Watch Mode
When "0" is written to the TMD bit of the low-power consumption mode control register (LPMCR) in the
sub clock run mode (CKSCR: SCS = 0), switching to the watch mode occurs.
● Data retention function
In the watch mode, the contents of the dedicated registers, such as accumulators, and the internal RAM are
retained.
● Hold function
During the watch mode, because the external bus hold function is inactive, a hold request is not accepted
even if it is input. If a hold request is input during switching to the watch mode, the bus may remain at
high-impedance and prevent the HAK signal from going low.
● Operation during an interrupt request
Writing "1" in the TMD bit of the low-power consumption mode control register (LPMCR) during an
interrupt request does not trigger a switch to the watch mode.
● Status of pins
Whether the external pins in the watch mode retain the state they had immediately before switching to the
watch mode or go to the high-impedance state can be controlled by the SPL bit of the low-power
consumption mode control register (LPMCR).
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CHAPTER 5 LOW-POWER CONSUMPTION MODE
■ Release of Watch Mode
The low-power consumption control circuit releases the watch mode when a reset is input or an interrupt
occurs.
● Return by a reset
The watch mode is released by a reset to the oscillation stabilization wait reset state. The reset sequence is
executed after the oscillation stabilization wait time.
The period of reset assertion depends on quality of main clock crystal oscillator.
Note:
When the watch mode is switched to main clock mode using an external reset pin (RST pin), input
level "L" for at least the oscillation time of oscillator * + 100 µs + 16 machine cycles.
* : The oscillation time of the oscillator is the time required to reach 90% of amplitude. It takes
several to dozens of ms for crystal oscillators, hundreds of µs to several ms for ceramic
oscillators, and 0 ms for external clocks.
● Return by an interrupt
If a watch timer or external interrupt generates an interrupt request at an interrupt level higher than 7 during
the watch mode (IL2, IL1, and IL0 of the interrupt control register (ICR) do not indicate "111B"), the lowpower consumption mode control circuit releases the watch mode and causes switching to the sub clock
mode immediately. After the switching, the interrupt is handled as an ordinary interrupt. If the interrupt is
accepted according to the setting of the I flag of the condition code register (CCR), interrupt level mask
register (ILM), and interrupt control register (ICR), the CPU executes the interrupt processing. If the
interrupt is not accepted, the CPU executes the instruction following the instruction specifying the watch
mode.
Note:
When interrupt processing is executed, the CPU normally executes the instruction following the
instruction in which switching to the watch mode has been specified. The CPU then proceeds to
interrupt processing. If the switching to the watch mode and acceptance of an external bus hold
request occur at the same time, however, the CPU may proceed to interrupt processing before
executing the next instruction.
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CHAPTER 5 LOW-POWER CONSUMPTION MODE
Figure 5.5-4 shows a return from the watch mode.
Figure 5.5-4 Release of the Watch Mode (External Reset)
RST pin
Watch mode
Main clock
Oscillation stabilization wait
Oscillating
PLL clock
Inactive
Sub clock
Oscillating
CPU clock
Inactive
Main clock
CPU operation
Inactive
Reset sequence Execution
Reset cleared.
Watch mode released.
105
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.5.4
Stop Mode
Because this mode causes oscillation to stop and inactivates all functions, data can be
retained by the lowest power consumption.
■ Switching to the Stop Mode
When "1" is written to the STP bit of the low-power consumption mode control register (LPMCR),
switching to the stop mode occurs.
● Data retention function
In the stop mode, the contents of the dedicated registers, such as accumulators, and the internal RAM are
retained.
● Hold function
During the stop mode, because the external bus hold function is inactive, a hold request is not accepted
even if it is input. If a hold request is input during switching to the stop mode, the bus may remain at highimpedance and prevent the HAK signal from going low.
● Operation during an interrupt request
Writing "1" in the STP bit of the low-power consumption mode control register (LPMCR) does not trigger
a switch to the stop mode.
● Status of pins
Whether the external pins in the stop mode retain the state they had immediately before switching to the
stop mode or go to the high-impedance state can be controlled by the SPL bit of the low-power
consumption mode control register (LPMCR). It is recommended, that SPL is set to "1". If SPL=0, assure
that Port 4 and 6 have defined levels.
Note:
If "1" is specified for both the STP bit and the SLP bit of the low-power consumption mode control
(LPMCR) simultaneously, the STP bit takes precedence, and a transition to stop mode occurs.
106
CHAPTER 5 LOW-POWER CONSUMPTION MODE
■ Release of Stop Mode
The low-power consumption control circuit releases the stop mode when a reset is input or an interrupt
occurs. Because the oscillation clock (HCLK) and sub clock (SCLK) are halted, the stop mode is released
after the oscillation stabilization wait interval of the main clock or sub clock.
● Return by a reset
After the stop mode is released by a reset, the oscillation stabilization wait state is set. The reset sequence is
executed after the oscillation stabilization wait time.
The period of reset assertion depends on quality of main clock crystal oscillator.
Note:
When the stop mode is switched to main clock mode using an external reset pin (RST pin), input
level "L" for at least the oscillation time of oscillator * + 100 µs + 16 machine cycles.
* : The oscillation time of the oscillator is the time required to reach 90% of amplitude. It takes
several to dozens of ms for crystal oscillators, hundreds of µs to several ms for ceramic
oscillators, and 0 ms for external clocks.
● Return by an interrupt
If an external interrupt generates an interrupt request at interrupt level higher than 7 during the stop mode
(IL2, IL1, and IL0 of the interrupt control register (ICR) do not indicate "111B"), the low-power
consumption mode control circuit releases the stop mode. The interrupt is then handled as an ordinary
interrupt after the oscillation stabilization wait time of the main clock specified by the WS1 and WS0 bits
of the clock selection register (CKSCR). If the interrupt is accepted according to the setting of the I flag of
the condition code register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR),
the CPU executes the interrupt processing. If the interrupt is not accepted, the CPU executes the instruction
following the instruction specifying the stop mode.
Notes:
• When interrupt processing is executed, the CPU normally executes the instruction following the
instruction in which switching to the stop mode has been specified. The CPU then proceeds to
interrupt processing. If the switching to the stop mode and acceptance of an external bus hold
request occur at the same time, however, the CPU may proceed to interrupt processing before
executing the next instruction.
• In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL
stop mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock
oscillation stabilization wait time. The oscillation stabilization wait times for the main clock and
PLL clock are counted simultaneously according to the value specified in the oscillation
stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register. The
oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register
must be selected accordingly to account for the longer of main clock and PLL clock oscillation
stabilization wait time. The PLL clock oscillation stabilization wait time, however, requires
214/HCLK or more. Set the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in
the clock selection register to "10B" or "11B".
107
CHAPTER 5 LOW-POWER CONSUMPTION MODE
Figure 5.5-5 shows a return from the stop mode.
Figure 5.5-5 Release of the Stop Mode (External Reset)
RST pin
Stop mode
Main clock
PLL clock
Oscillation stabilization wait
Inactive
Main clock
CPU clock
CPU operation
Inactive
Reset cleared.
Stop mode released.
108
Oscillating
Reset sequence Execution
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.6
Status Change Diagram
Figure 5.6-1 shows the status change diagram of the MB90440G series.
■ Status Change Diagram
Figure 5.6-1 Status Change Diagram
External reset, watchdog timer
reset, software reset
Power-on
Reset
Power-on reset
SCS=0
Oscillation stabilization
wait end
SCS=1
MCS=0
Main clock mode
PLL clock mode
MCS=1
SLP=1
Interrupt
Main sleep mode
InterTMD=0
rupt
Main time-base
timer mode
STP=1
Main stop
mode
Inter- Oscillation
rupt
stabilization
wait end
Main clock oscillation
stabilization wait
SCS=0
Sub clock mode
SCS=1
SLP=1
Interrupt
PLL sleep mode
TMD=0
Interrupt
PLL time-base
timer mode
Interrupt
Sub-sleep mode
InterTMD=0
rupt
Watch mode
STP=1
STP=1
PLL stop mode
Interrupt
SLP=1
Oscillation
stabilization
wait end
PLL clock oscillation
stabilization wait
Sub clock
stop mode
Interrupt
Oscillation
stabilization
wait end
Sub clock oscillation
stabilization wait
Note:
When the clock mode is switched, do not switch to other clock mode and low-power consumption
mode before this switching is completed. Confirm the completion of clock mode switching by
referring to the MCM and SCM bits of the clock selection register (CKSCR).
109
CHAPTER 5 LOW-POWER CONSUMPTION MODE
■ Operation Status in Each Operating Mode Table
Table 5.6-1 lists the operation status in each operating mode.
Table 5.6-1 Operation Status in Each Operating Mode
Operation status
Main
clock
Sub clock
PLL
clock
PLL
CPU
Peripheral
Watch
Time-base
timer
Active
Active
Clock
source
Active
Active
PLL sleep
Active
Active
Active
PLL time-base
timer (*1)
PLL clock
Inactive
PLL stop
Inactive
Inactive
Inactive
PLL oscillation
stabilization wait
Active
Active
Active
Main
Inactive
Inactive
Inactive
Active
Active
Active
Active
Active
Active
Main sleep
Active
Active
Main time-base
timer (*2)
Inactive
Main clock
Inactive
Main stop
Inactive
Inactive
Main oscillation
stabilization wait
Active
Active
Inactive
Inactive
Inactive
Active
Active
Active
Sub
Active
Sub-sleep
Active
Active
Watch
Sub clock stop
Inactive
Inactive
Inactive
Inactive
Inactive
Sub clock
Active
Main clock
Inactive
Sub clock
oscillation
stabilization wait
Active
Power-on reset
Active
Inactive
Active
Reset
*1: During the PLL clock mode
*2: During the main clock mode
110
Inactive
Active
Inactive
Active
Inactive
Active
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.7
Status of Pins in Standby Mode and during Hold and Reset
The status of pins in the standby mode and during hold and reset are described for
each memory access mode.
■ Status of Each Pin in the Single Chip Mode
Table 5.7-1 shows the Status of Each Pin in the Single Chip Mode.
Table 5.7-1 Status of Each Pin in the Single Chip Mode
Standby mode
Stop (*6)
Pin name
Reset
Sleep
SPL = 0
SPL = 1
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P47,
P50, P55 to P57,
P60 to P67,
Status before the mode
retained (*2)
Input interrupted (*3) /
Status before the mode
retained (*2)
Input interrupted (*3) /
output Hi-Z (*5)
Input disabled (*4) /
output Hi-Z (*5)
P70 to P77,
P80 to P87,
P92 to P94, P96, P97
P51 to P54,
Input enabled (*1)
P90, P91, P95, PA0
*1: "Input enabled" means that the input function is available. The pull-up or pull-down option or external input is required. When the
pin is used as an output port, the status is the same as other ports.
*2: "Status before the mode retained" means that the status output immediately before the mode is output as is or input is
enabled.Outputting the status output immediately before the mode as is means that output is performed according to the internal
peripheral with output when it is operating or output as a port is retained.
*3: During input interrupted, input is masked, and the "L" level will be sent inwardly if CMOS is selected and "H" level
will be sent inwardly if TTL is selected.
*4: "Input interrupted" indicates the status in which operation of the input gate directly connected to the pin is prohibited.
*5: "Output Hi-Z" means that the pin driving transistor is placed in the drive prohibited state to set the pin to high impedance.
*6: The pull-up option is disconnected from each port pin in stop mode.
Note:
In the stop mode up to eight external signals can be input and the frequency of each signal must be
1 kHz or less.
111
CHAPTER 5 LOW-POWER CONSUMPTION MODE
■ Status of Each Pin in External BUS 16-bit Data Bus Mode
Table 5.7-2 shows the Status of Each Pin in the External Bus 16-bit Data Bus Mode.
Table 5.7-2 Status of Each Pin in the Single Chip Mode
Standby mode
Pin name
Stop
Hold
Reset
Sleep
SPL = 0
P00 to P07
(AD00 to AD07),
P10 to P17
(AD08 to AD15)
Input disabled /
output Hi-Z
Input interrupted /
output Hi-Z
P20 to P27
(A16 to A23)
Output state (*1)
Output state (*1)
P37(CLK)
Input disabled /
output enabled
Input disabled /
output state (*1)
SPL = 1
Input disabled /
output Hi-Z
Output state (*1)
Input disabled /
output enabled
(*2)
P36(RDY)
P35(HAK)
Status before the
mode retained
Input disabled /
output Hi-Z
(*2)
Input interrupted /
Status before the
mode retained
P34(HRQ)
Input disabled /
output Hi-Z
Input interrupted /
output Hi-Z
"L" output
Input disabled /
output Hi-Z
"1" input
P33(WRH)
P32(WRL)
"H" output
"H" output
P31(RD)
P30(ALE)
P40 to P47,
P50, P55 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
P92 to P94,
P96, P97
P51 to P54,
P90, P91, P95, PA0
"L" output
Status before the
mode retained
Input disabled /
output Hi-Z
"L" output
Input interrupted /
Status before the
mode retained
"H" output
"L" output
Status before the
mode retained
Input disabled /
output Hi-Z
Input enabled
*1: "Output state" means that the driving pin transistor is placed in the drive enabled state, but a fixed value, "H" or "L", is
output because internal circuit operation stops. When the internal peripheral circuit is operating and the output function
is used, output changes.
*2: "Output enabled" means that the driving pin transistor is placed in the drive enabled state and the operation status
appears at the pin because internal circuit operation is enabled.
112
CHAPTER 5 LOW-POWER CONSUMPTION MODE
■ Status of Each Pin in External BUS 8-bit Data Bus Mode
Table 5.7-3 shows the Status of Each Pin in the External Bus 8-bit Data Bus Mode.
Table 5.7-3 Status of Each Pin in the External Bus 8-bit Data Bus Mode
Standby mode
Pin name
Stop
Hold
Reset
Sleep
SPL = 0
P00 to P07
(AD00 to AD07),
P10 to P17
(AD08 to AD15)
Input disabled /
output Hi-Z
Input interrupted /
output Hi-Z
P20 to P27
(A16 to A23)
Output state
Output state
P37(CLK)
Input disabled /
output enabled
Input disabled /
output state
SPL = 1
Input disabled /
output Hi-Z
Output state
Input disabled /
output enabled
Input disabled /
output Hi-Z
P36(RDY)
P35(HAK)
P34(HRQ)
Input disabled /
output Hi-Z
Status before the
mode retained
Input interrupted /
Status before the
mode retained
P33(WRH)
"L" output
Input interrupted /
output Hi-Z
Input disabled /
output Hi-Z
"1" input
Status before the
mode retained
P32(WRL)
"H" output
"H" output
P31(RD)
P30(ALE)
P40 to P47,
P50,P55 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
P92 to P94,
P96,P97
P51 to P54,
P90, P91, P95, PA0
"L" output
Status before the
mode retained
Input disabled /
output Hi-Z
"L" output
Input interrupted /
Status before the
mode retained
"H" output
"L" output
Status before the
mode retained
Input disabled /
output Hi-Z
Input enabled
113
CHAPTER 5 LOW-POWER CONSUMPTION MODE
5.8
Usage Notes on Low-Power Consumption Mode
Note the following six items when using the low-power consumption mode:
• Switching to a standby mode and interrupt
• Release of a standby mode by an interrupt
• Release of the stop mode
• Oscillation stabilization wait time Oscillation
• Clock mode switching
• Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to
Enter the Standby Mode
■ Switching to a Standby Mode and Interrupt
During an interrupt request to the CPU from a peripheral function, the CPU ignores the setting of the lowpower consumption mode control register (LPMCR) even if "1" is written to the STP and SLP bits or if "0"
is written to the TMD bit. Thus, switching to each standby mode is disabled (even after processing of the
interrupt is completed, there is no switch to a standby mode). If the interrupt level is seven or a higher
priority, this action does not depend on whether the interrupt request is accepted by the CPU. However,
during execution of interrupt processing by the CPU, if the interrupt request flag for the interrupt is cleared
and no other interrupt requests have been issued, switching to a standby mode can be performed.
● Release of the Standby Mode by an Interrupt
If an interrupt request of interrupt level seven or a higher priority is issued from a peripheral function
during the sleep, time-base timer, or stop mode, the standby mode is released, which does not depend on
whether the CPU accepts the interrupt.
After the release of the standby mode by an interrupt, normal processing is performed. The CPU branches
to the interrupt handling routine provided that the priority of the interrupt request indicated by the interrupt
level setting bits (IL2, IL1, and IL0 of ICR) is higher than the interrupt level mask register (ILM) and the
interrupt enable flag ((I) of the condition code register (CCR) is set to "1" (enabled).
If the interrupt is not accepted, the CPU starts the execution with the instruction following the instruction in
which switching to the standby mode has been specified.
When interrupt processing is executed normally, the CPU first executes the instruction following the
instruction in which switching to the standby mode has been specified. The CPU then proceeds to interrupt
processing.
Depending on the condition when switching to a standby mode was performed, however, the CPU may
proceed to interrupt processing before executing the next instruction.
Note:
If the CPU does not branch to the interrupt processing routine immediately after a return, action such
as interrupt disabling must be taken before a standby mode is set.
● Release of the Stop Mode
The stop mode can be released by an input that has been set as an external interrupt input cause before the
system enters the stop mode. As an input cause, an H-level signal, L-level signal, rising edge, or falling
edge can be selected.
114
CHAPTER 5 LOW-POWER CONSUMPTION MODE
■ Oscillation Stabilization Wait Time
● Clock oscillation stabilization wait time
Because the oscillator for oscillation is halted in the stop mode, an oscillation stabilization wait time is
required. A time period selected by the WS1 and WS0 bits of the clock selection register (CKSCR) is used
as the oscillation stabilization wait time. The WS1 and WS0 bits can be set to "00B" only in the main clock
mode.
● PLL clock oscillation stabilization wait time
In main clock mode, the PLL multiplication circuit stops. When changing to PLL clock mode, it is
necessary to reserve the PLL clock oscillation stabilization wait time. The CPU runs in main clock mode
till the PLL clock oscillation stabilization wait time has elapsed. When the main clock is switched to PLL
clock mode, the PLL clock oscillation stabilization wait time is fixed at 214/HCLK (HCLK: oscillation
clock).
In sub clock mode, the main clock and PLL multiplication circuit stop. When changing to PLL clock mode,
it is necessary to reserve the main clock oscillation stabilization wait time and PLL clock oscillation
stabilization wait time. The oscillation stabilization wait times for main clock and PLL clock are counted
simultaneously according to the value specified in the oscillation stabilization wait time selection bits
(CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection bits
(CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the longer
of the main clock and PLL clock oscillation stabilization wait times. The PLL clock oscillation stabilization
wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time selection bits
(CKSCR: WS1, WS0) in the clock selection register to "10B" or "11B".
In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL stop
mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock oscillation
stabilization wait time. The oscillation stabilization wait times for the main clock and PLL clock are
counted simultaneously according to the value specified in the oscillation stabilization wait time selection
bits (CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection
bits (CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the
longer of main clock and PLL clock oscillation stabilization wait time. The PLL clock oscillation
stabilization wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time
selection bits (CKSCR: WS1, WS0) in the clock selection register to "10B" or "11B".
■ Clock Mode Switching
When the clock mode is switched, do not switch to other clock mode and low-power consumption mode
before this switching is completed. Confirm the completion of clock mode switching by referring to the
MCM and SCM bits of the clock selection register (CKSCR).
115
CHAPTER 5 LOW-POWER CONSUMPTION MODE
■ Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to
Enter the Standby Mode
● To access the low-power consumption mode control register (LPMCR) with assembler language
- To set the low-power consumption mode control register (LPMCR) to enter the standby mode, use the
instruction listed in Table 5.3-2 .
- The low-power consumption mode transition instruction in Table 5.3-2 must always be followed by an
array of instructions highlighted by a line below.
MOV LPMCR,#H’xx ;the low-power consumption mode transition instruction in Table 5.3-2
NOP
NOP
JMP $+3
; jump to next instruction
MOV A,#H'10
; any instruction
The devices does not guarantee its operation after returning from the low-power consumption mode if you
place an array of instructions other than the one enclosed in the line.
● To access the low-power consumption mode (LPMCR) with C language
To enter the standby mode using the low-power consumption mode control register (LPMCR), use one of
the following methods (1) to (3) to access the register:
(1) Specify the standby mode transition instruction as a function and insert two _wait_nop() built-in
functions after that instruction. If any interrupt other than the interrupt to return from the standby mode
can occur within the function, optimize the function during compilation to suppress the LINK and
UNLINK instructions from occurring.
Example: Watch mode or time-base timer mode transition function
Void enter_watch(){
IO_LPMCR_byte = 0x10;
/* Set LPMCR TMD bit to "0" */
_wait_nop();
_wait_nop();
}
(2) Define the standby mode transition instruction using _asm statements and insert two NOP and JMP
instructions after that instruction.
Example: Transition to sleep mode
_asm(" MOVI: _IO_LPMCR,#H’58");
/* Set LPMCR SLP bit to "1" */
_asm(" NOP");
_asm(" NOP");
_asm(" JMP $+3");
/* Jump to next instruction */
(3) Define the standby mode transition instruction between #pragma asm and #pragma endasm and insert
two NOP and JMP instructions after that instruction.
Example: Transition to stop mode
#pragma asm
MOV I: _IO_LPMCR,#H’98
/* Set LPMCR STP bit to "1" */
NOP
NOP
JMP $+3
/* Jump to next instruction */
#pragma endasm
116
CHAPTER 6
RESETS
This chapter explains resets for the MB90440G series
microcontrollers.
6.1 Resets
6.2 Reset Cause and Oscillation Stabilization Wait Intervals
6.3 External Reset Pin
6.4 Reset Operation
6.5 Reset Cause Bits
6.6 Status of Pins in a Reset
117
CHAPTER 6 RESETS
6.1
Resets
If a reset is generated, the CPU immediately stops the current execution process and
waits for the reset to be cleared. The CPU then begins processing at the address
indicated by the reset vector.
The four causes of a reset are as follows
• Power-on reset
• External reset request via the RST pin
• Software reset request
• Watchdog timer overflow
■ Causes of a Reset
Table 6.1-1 lists the causes of a reset.
Table 6.1-1 Causes of a Reset
Type of reset
Cause
Machine clock
Watchdog
timer
Oscillation
stabilization
wait
Power-on
When the power is turned
on
Main clock
(MCLK)
Stop
Yes
External pin
L level input to RST pin
Main clock
(MCLK)
Stop
No
Software
A "0" is written to the
RST bit of the low-power
consumption mode
control register
(LPMCR).
Main clock
(MCLK)
Stop
No
Watchdog
timer
Watchdog timer overflow
Main clock
(MCLK)
Stop
No
Main clock: Oscillation clock frequency divided by 2
● Power-on reset
A power-on reset is generated when the power is turned on. The oscillation stabilization wait intervals are
fixed at 218/HCLK (approx. 65.54 ms). When the oscillation stabilization wait interval has elapsed, the
reset is executed.
● External reset
An external reset is generated by the "L" level input to an external reset pin (RST pin). The minimum
required period of the "L" level is 16 machine cycles. The oscillation stabilization wait interval is not
required for external resets.
118
CHAPTER 6 RESETS
Notes:
• If the reset cause is generated during a write operation (during the execution of a transfer
instruction such as MOV), the CPU waits for the reset to be cleared after completion of the
instruction only for reset requests via the RST pin. Therefore, the normal write operation is
completed even though a reset is input concurrently. Note that a reset may prevent the data
transfer requested by a string-processing instruction (such as MOVS) from being completed
because the reset is accepted before a specified number of bytes are transferred.
• When the stop mode, sub clock mode, sub-sleep mode, or watch mode is switched to main clock
mode using an external reset pin (RST pin), input level "L" for at least the oscillation time of the
oscillator * + 100 µs + 16 machine cycles.
* : The oscillation time of the oscillator is the time required to reach 90% of amplitude. It takes
several to dozens of ms for crystal oscillators, hundreds of µs to several ms for ceramic
oscillators, and 0 ms for external clocks.
● Software reset
A software reset is an internal reset generated by writing "0" to the RST bit of the low power consumption
mode control register (LPMCR). The oscillation stabilization wait interval is not required for a software
reset.
● Watchdog timer reset
A watchdog timer reset is generated by a watchdog timer overflow that occurs when "0" is written to the
WTE bit of the watchdog timer control register (WDTC) within a given time after the watchdog timer is
activated. The oscillation stabilization wait interval can be set by the clock selection register (CKSCR).
Definition of clocks
HCLK: Oscillation clock
MCLK: Main clock
SCLK: Sub clock
φ:
Machine clock (CPU operating clock)
1/φ:
Machine cycle (CPU operating clock period)
See Section "4.1 Clocks" for details on machine clocks.
Note:
If a reset occurs in stop or sub clock mode, an oscillation stabilization wait interval of 217/HCLK
(approx. 32.77 ms) is required.
See Section "4.4 Clock Mode" for details on clock modes.
119
CHAPTER 6 RESETS
6.2
Reset Cause and Oscillation Stabilization Wait Intervals
The MB90440G has four reset causes. The oscillation stabilization wait interval for a
reset depends on the reset cause.
■ Reset Causes and Oscillation Stabilization Wait Intervals
Table 6.2-1 summarizes reset causes and oscillation stabilization wait intervals.
Table 6.2-1 Reset Causes and Oscillation Stabilization Wait Intervals
Reset
Oscillation stabilization wait interval
The corresponding time interval for an oscillation clock
frequency of 4 MHz is given in parentheses.
Cause
Power-on reset
When the power is turned on
218/HCLK (approx. 65.54 ms)
Watchdog timer
Watchdog timer overflow
None; though bits WS1 and WS0 are initialized to "11B".
External reset via the RST
pin
"L" level input to RST pin
None; though bits WS1 and WS0 are initialized to "11B".
Software reset
"0" written to the RST bit in
the Low-power consumption
mode control register
(LPMCR)
None; though bits WS1 and WS0 are initialized to "11B".
HCLK: Oscillation clock
WS1 and WS0: Oscillation stabilization wait interval selection bits of the clock selection register (CKSCR)
Figure 6.2-1 shows the oscillation stabilization wait intervals at a power-on reset.
Figure 6.2-1 Oscillation Stabilization Wait Intervals at Power-on Reset
Vcc
217/HCLK
217/HCLK
CLK
CPU operation
Voltage step-down Oscillation
circuit stabilisation stabilisation wait
wait time
time
120
CHAPTER 6 RESETS
Note:
Ceramic and crystal oscillators generally require an oscillation stabilization wait interval of several to
dozens of ms, until stabilization at a natural frequency is attained. A proper oscillation stabilization
wait interval must be set for the particular oscillator used.
See Section "4.5 Oscillation Stabilization Wait Interval" for details about oscillation stabilization wait
intervals.
■ Oscillation Stabilization Wait and Reset State
A reset operation in response to a power-on reset and other resets during stop mode and sub clock mode is
performed after the oscillation stabilization wait interval has elapsed. This time interval is generated by the
time-base timer. If the external reset has not been cleared after the interval, the reset operation is performed
after the external reset is cleared.
121
CHAPTER 6 RESETS
6.3
External Reset Pin
The external reset pin (RST pin) is an input pin used exclusively for a reset. Inputting an
"L" level signal generates an internal reset. For the MB90440G series, resets are
generated in synchronization with the CPU operating clock. However, a reset generated
via the external pin is asynchronous with the CPU operating clock.
■ Block Diagram of the External Reset Pin
Figure 6.3-1 Block Diagram of Internal Reset
RST
P-ch
Pin
N-ch
CPU operating clock
(PLL multiplier circuit with a frepuency of HCLK frequency divided by 2)
Synchronization
circuit
HCLK: Oscillation clock
CPU, Peripheral
function (resources)
Input buffer
External pin
Note:
Inputs to the RST are accepted during cycles in which memory is not affected to prevent memory
from being destroyed by a reset during a write operation.
A clock is required to initialize the internal circuit. In particular, an operation with an external clock
requires clock input together with reset input.
122
CHAPTER 6 RESETS
6.4
Reset Operation
When a reset is cleared, the memory locations from which the mode data and the reset
vectors are read are selected according to the setting of the mode pins, and a mode
fetch is performed. Mode setting data determines the CPU operating mode and the
execution start address after a reset operation ends. For power-on or recovery from sub
clock mode or stop mode by a reset, a mode fetch is performed when the oscillation
stabilization wait interval elapses.
■ Overview of Reset Operation
Figure 6.4-1 shows the reset operation flow.
Figure 6.4-1 Reset Operation Flow
Power-on reset
Stop mode
Sub clock mode
External reset
Software reset
Watchdog timer reset
During a reset
Oscillation stabilization wait
and reset state
Fetching the mode data
Mode fetch
(Reset operation)
Normal operation
(Run state)
Pin state and function
change associated with
external bus mode
Fetching the reset vector
CPU executes an instruction,
fetching instruction codes from
the address indicated by the
reset vector.
■ Mode Pins
Setting the mode pins (MD0 to MD2) specifies how to fetch the reset vector and the mode data. Fetching
the reset vector and the mode data is performed in the reset sequence. See Section "7.1.1 Mode Pins" for
details on mode pins.
123
CHAPTER 6 RESETS
■ Mode Fetch
When the reset is cleared, the CPU transfers the reset vector and the mode data to the appropriate registers
in the CPU core by hardware. The reset vector and mode data are allocated to the four bytes from
FFFFDCH to FFFFDFH. The CPU outputs these addresses to the bus immediately after the reset is cleared
and then fetches the reset vector and mode data. Using mode fetching, the CPU can begin processing at the
address indicated by the reset vector.
Figure 6.4-2 shows the transfer of the reset vector and mode data.
Figure 6.4-2 Transfer of Reset Vector and Mode Data
Memory space
F2MC-16LX CPU core
Mode data
FFFFDFH
Mode data
FFFFDEH
Bit23 to bit16 of the reset vector
FFFFDDH
Bit15 to bit8 of the reset vector
FFFFDCH
Bit7 to bit0 of the reset vector
Micro-ROM
Reset sequence
PCB
PC
● Mode data (address: FFFFDFH)
Only a reset operation changes the contents of the mode register. The mode register setting is valid after a
reset operation. See Section "7.1.2 Mode Data" for details on mode data.
● Reset vector (address: FFFFDCH to FFFFDEH)
The execution start address after the reset operation ends is written as the reset vector. Execution starts at
the address contained in the reset vector.
124
CHAPTER 6 RESETS
6.5
Reset Cause Bits
A reset cause can be identified by reading the watchdog timer control register (WDTC).
■ Reset Cause Bits
As shown in Figure 6.5-1 , a flip-flop is associated with each reset cause. The contents of the flip-flops are
obtained by reading the watchdog timer control register (WDTC). If the cause of a reset must be identified
after the reset has been cleared, the value read from the WDTC should be processed by the software and a
branch made to the appropriate program. Figure 6.5-1 describes general F2MC16-LX reset function. Please
note that MB90440G series MCU does not have HST pin. Functionality is as if HST is permanently
asserted to H.
Figure 6.5-1 Block Diagram of Reset Cause Bits
HST = "H" internal fix
(without hardware standby mode)
Power-on
Hardware
standby release
detection
circuit
Power-on
detection
circuit
RST pin
No periodic clear
RST=L
External reset
request
detection cirtuit
Watchdog timer
reset generation
detection cirtuit
Watchdog timer
control register
(WDTC)
RST bit set
LPMCR : RST
bit write
detection circuit
Clear
S
R
S
F/F
Q
R
S
Q
R
S
Q
R
Q
R
S
F/F
F/F
F/F
F/F
Delay
circuit
Q
Reading of
watchdog timer
control register
(WDTC)
Internal data bus
S :
R :
Q :
F/F:
Set
Reset
Output
Flip Flop
■ Correspondence between Reset Cause Bits and Reset Causes
Figure 6.5-2 shows the configuration of the reset cause bits of the watchdog timer control register (WDTC).
Table 6.5-1 maps the correspondence between the reset cause bits and reset causes. See Section "10.2
Watchdog Timer Control Register (WDTC)" for details.
125
CHAPTER 6 RESETS
Figure 6.5-2 Configuration of Reset Cause Bits (Watchdog Timer Control Register)
Watchdog timer control register (WDTC)
Address
bit15
0000A8H
bit8 bit7
(TBTC)
bit6
PONR
--
R
--
bit5
bit4
bit0
Initial value
WRST ERST SRST WTE WT1 WT0
X-XXX111B
R
R
bit3
R
bit2
W
bit1
W
W
R : Read only
W : Write only
X : Undefined
Table 6.5-1 Correspondence between Reset Cause Bits and Reset Causes
Reset cause
PONR
WRST
ERST
SRST
Power-on reset
1
X
X
X
Watchdog timer overflow
*
1
*
*
External reset request via RST pin
*
*
1
*
Software reset request
*
*
*
1
*: Previous state defined
X: Undefined
■ Notes about Reset Cause Bits
● Multiple reset causes generated at the same time
When multiple reset causes are generated at the same time, the corresponding reset cause bits of the
watchdog timer control register (WDTC) are also set to "1". If, for example, an external reset request via
the RST pin and the watchdog timer overflow occur at the same time, the ERST and the WRST bits are
both set to "1".
● Power-on reset
For a power-on reset, because the PONR bit is set to "1" but all other reset cause bits are undefined, the
software should be programmed so that it will ignore all reset cause bits except the PONR bit when it is
"1".
● Clearing the reset cause bits
The reset cause bits are cleared only when the watchdog timer control register (WDTC) is read. Any bit
corresponding to a reset cause that has already been generated is not cleared even though another reset is
generated (a setting of "1" is retained).
Note:
If the power is turned on under conditions where no power-on reset occurs, the value in this register
may not be guaranteed.
126
CHAPTER 6 RESETS
6.6
Status of Pins in a Reset
This section describes the status of pins when a reset occurs.
■ Status of Pins during a Reset
The status of pins during a reset depends on the settings of mode pins (MD2 to MD0 = 011B).
See section "5.7 Status of Pins in Standby Mode and during Hold and Reset" for the status of pins during a
reset.
● When internal vector mode has been set:
All I/O pins (resource pins) are high impedance, and mode data is read from the internal ROM.
■ Status of Pins after Mode Data is Read
The status of pins after mode data has been read depends on the mode data (M1 and M0 = 00B).
● When single-chip mode has been selected (M1 and M0 = 00B):
All I/O pins (resource pins) are high impedance, and mode data is read from the internal ROM.
Note:
For those pins that change to high impedance when a reset cause is generated, confirm that devices
connected to the pins do not malfunction.
127
CHAPTER 6 RESETS
128
CHAPTER 7
MEMORY ACCESS MODES
This chapter explains the functions and operations of
the memory access modes.
7.1 Outline of Memory Access Modes
7.2 External Memory Access (Bus Pin Control Circuit)
7.3 External Memory Access Control Signal Operation
129
CHAPTER 7 MEMORY ACCESS MODES
7.1
Outline of Memory Access Modes
In the F2MC-16LX, various modes are provided for access methods and access areas.
■ Memory Access Modes
Table 7.1-1 Mode Pins and Modes
Operation mode
Bus mode
Access mode
Single chip
8 bits
Internal ROM, external bus
RUN
16 bits
8 bits
External ROM, external bus
16 bits
Flash programming
-
-
● Operation mode
Operation mode means the mode for controlling the device operation status. The operation mode is
specified by the MDx mode setting pin and the Mx bit in mode data. By selecting an operation mode,
normal operation activation or flash serial programming can be performed.
● Bus mode
Bus mode means the mode for controlling the internal ROM operation and external access function. The
bus mode is specified by the MDx mode setting pin and the Mx bit in mode data. The MDx mode setting
pin specifies the bus mode for reading the reset vector and mode data, and the Mx bit in mode data
specifies the bus mode for normal operation.
● Access mode
Access mode means the mode for controlling the external data bus width. The access mode is specified by
the MDx mode setting pin and the S0 bit in mode data. By selecting an access mode, an 8- or 16-bit
external data bus is specified.
130
CHAPTER 7 MEMORY ACCESS MODES
7.1.1
Mode Pins
Table 7.1-2 lists the operations that can be specified by combining the three external
pins MD2 to MD0.
■ Mode Pins
Table 7.1-2 Mode Pins and Modes
Mode pin setting
Mode name
Reset vector
access area
External data
bus width
Remarks
MD2
MD1
MD0
0
0
0
External vector mode 0
External
8 bits
0
0
1
External vector mode 1
External
16 bits
Reset vector,
16-bit bus width access
0
1
0
0
1
1
(Mode data)
Reset sequence and later
segments are controlled
based on mode data.
1
0
0
1
0
1
1
1
0
Flash memory serial
programming *
--
--
1
1
1
Flash memory
--
--
Reserved
Internal vector mode
Internal
Reserved
-Mode when parallel
writer is used
*: Data can not be written only by setting the flash serial programming mode by mode pins.
Other must be set. For details, see the examples of flash memory serial programming connection.
131
CHAPTER 7 MEMORY ACCESS MODES
7.1.2
Mode Data
Mode data is stored at FFFFDFH of main memory and used for controlling the CPU
operation. This data is fetched during a reset sequence and stored in the mode register
inside the device. The mode register value can be changed only by a reset sequence.
The setting of this register is valid after the reset sequence.
Always set the reserved bits to "0".
■ Mode Data
Figure 7.1-1 Mode Data Configuration
Mode data
bit
Address: FFFFDFH
7
6
M1
M0
5
4
3
Reserved Reserved
S0
2
1
0
Reserved Reserved Reserved
[bit7, bit6] M1, M0 (bus mode setting bits)
The M1 and M0 bits are used to specify the operation mode after the reset sequence is completed. Table
7.1-3 shows the relationship between the M1 and M0 bits and the functions.
Table 7.1-3 M1 and M0 (Bus Mode Setting Bit) Functions
M1
M0
Function
0
0
Single-chip mode
0
1
Internal ROM, external bus mode
1
0
External ROM, external bus mode
1
1
Setting prohibited
Remarks
[bit3] S0 (mode setting bit)
The S0 bit is used to specify the bus mode or access mode after the reset sequence is completed. Table
7.1-4 shows the relationship between the S0 bit and the functions.
Table 7.1-4 S0 (Mode Setting Bit) Functions
S0
132
Function
0
External 8-bit data bus mode
1
External 16-bit data bus mode
Remarks
CHAPTER 7 MEMORY ACCESS MODES
7.1.3
Memory Space in Each Bus Mode
Figure 7.1-2 shows the correspondence between the access areas and physical
addresses for each bus mode.
■ Memory Space in Each Bus Mode
Figure 7.1-2 Relationship between Access Areas and Physical Addresses for Each Bus Mode
FFFFFFH
ROM area
ROM area
ROM area
(FF bank image)
ROM area
(FF bank image)
I/O
I/O
I/O
RAM
RAM
RAM
Address #1
010000H
004000H
003900H
Address #2
Address #3
: Internal
: External
000100H
0000C0H
000000H
Model
I/O
I/O
Single chip
Internal ROM, external bus
I/O
: No access
External ROM, external bus
Address #1
Address #2
Address #3
MB90F443G
FE0000H
002000H
001900H
MB90V440G
(FC0000H)
n/a, 14Kbytes RAM
n/a, 14Kbytes RAM
133
CHAPTER 7 MEMORY ACCESS MODES
■ Recommended Setting
Table 7.1-5 lists an example of recommended settings for mode pins and mode data.
Table 7.1-5 Example of Recommended Settings for Mode Pins and Mode Data
Sample setting
MD2
MD1
MD0
M1
M0
S0
Single chip
0
1
1
0
0
x
Internal ROM and external bus mode, 16-bit bus
0
1
1
0
1
1
Internal ROM and external bus mode, 8-bit bus
0
1
1
0
1
0
External ROM and external bus mode, 16-bit bus, vector
16 bus width
0
0
1
1
0
1
External ROM and external bus mode, 8-bit bus
0
0
0
1
0
0
External pins have signal functions that depend on each mode.
Table 7.1-6 External Pin Functions for Each Mode
Function
External bus expansion
Pin name
Single chip
Flash programming
8 bits
P07 to P00
16 bits
AD07 to AD00
P17 to P10
A15 to A08
D07 to D00
AD15 to AD08
A15 to A08
P27 to P20
A23 to A16*
A07 to A00
P30
ALE
A16
P31
RD
CEX
P32
P33
Port
WR
WRL
OEX
Port
WRH *
PGMX
P34
HRQ*
P35
HAK *
P36
RDY*
P37
CLK*
Unused
*: The upper address output pins and the WRL/WR, WRH, HRQ, HAK, RDY, and CLK pins can be used as ports through
function selection. See Section "7.2 External Memory Access (Bus Pin Control Circuit)" for details.
134
CHAPTER 7 MEMORY ACCESS MODES
7.2
External Memory Access (Bus Pin Control Circuit)
The external bus pin control circuit controls the external bus pins for external
expansion of the CPU address and data buses.
■ External Memory Access (Bus Pin Control Circuit)
The following address, data, and control signals are used to access external memory and peripherals of the
MB90440G device:
•
CLK (P37):
Machine cycle clock (KBP) output pin
•
RDY (P36):
External ready input pin
•
WRH (P33):
Write signal for upper 8 bits of data bus
•
WRL/WR (P32): Write signal for lower 8 bits of data bus
•
RD (P31):
Read signal
•
ALE (P30):
Address latch enable signal
The external bus pin control circuit is used to control the external bus pins to enable external expansion of
the CPU address and data buses.
■ Block Diagram of External Memory Access
Figure 7.2-1 External Bus Controller
P0
P0 data
P1
P2
P3
P3
P0
P0 direction
RB
Data control
Address control
Access control
Access control
135
CHAPTER 7 MEMORY ACCESS MODES
7.2.1
External Memory Access (External Bus Pin Control
Circuit) Registers
External memory access (external bus pin control circuit) uses the following three types
of registers:
• Automatic ready function selection register
• External address output control register
• Bus control signal selection register
■ External Memory Access Registers
Figure 7.2-2 External Memory Access (External Bus Pin Control Circuit) Registers
Automatic ready function selection register
15
bit
Address:0000A5H
14
13
12
11
10
IOR1 IOR0 HMR1 HMR0
Read/write
Initial value
(W)
(0)
(W)
(0)
(W)
(1)
(W)
(1)
7
6
5
E23
E22
E21
9
8
LMR1 LMR0
(-)
(-)
(-)
(-)
(W)
(0)
(W)
(0)
4
3
2
1
0
E20
E19
E18
E17
E16
ARSR
External address output control register
bit
Address:0000A6H
Read/write
Initial value
(W)
(0)
Bus control signal selection register
bit 15
136
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
14
13
12
11
10
9
8
Address:0000A7H
CKE
RYE
HDE
Read/write
Initial value
(W)
(0)
(W)
(0)
(W)
(0)
IOBS HMBS WRE LMBS
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
HACR
ECSR
(-)
(-)
CHAPTER 7 MEMORY ACCESS MODES
7.2.2
Automatic Ready Function Selection Register (ARSR)
The automatic ready function selection register (ARSR) is used to set the automatic
wait time for memory access for each area during external access.
■ Automatic Ready Function Selection Register (ARSR)
Figure 7.2-3 Automatic Ready Function Selection Register Configuration
Automatic ready function selection register
bit
Address:0000A5H
Read/write
Initial value
15
14
13
12
11
10
IOR1 IOR0 HMR1 HMR0
(W)
(0)
(W)
(0)
(W)
(1)
(W)
(1)
9
8
LMR1 LMR0
(-)
(-)
(-)
(-)
(W)
(0)
ARSR
(W)
(0)
[bit15, bit14] IOR1, IOR0
The IOR1 and IOR0 bits are used to specify the automatic wait function for external access to the area
from 0000C0H to 0000FFH. Table 7.2-1 lists the settings that can be specified by combining the IOR1
and IOR0 bits.
Table 7.2-1 IOR1 and IOR0 (Automatic Wait Function Specification Bit) Functions
IOR1
IOR0
Function
0
0
Automatic wait disabled [initial value]
0
1
Automatic wait of 1 cycle is inserted for external access
1
0
Automatic wait of 2 cycles is inserted for external access
1
1
Automatic wait of 3 cycles is inserted for external access
[bit13, bit12] HMR1, HMR0
The HMR1 and HMR0 bits are used to specify the automatic wait function for external access to the
area from 800000H to FFFFFFH. Table 7.2-2 lists the settings that can be specified by combining the
HMR1 and HMR0 bits.
Table 7.2-2 HMR1 and HMR0 (Automatic Wait Function Specification Bit) Functions
HMR1
HMR0
Function
0
0
Automatic wait disabled
0
1
Automatic wait of 1 cycle is inserted for external access
1
0
Automatic wait of 2 cycles is inserted for external access
1
1
Automatic wait of 3 cycles is inserted for external access [initial
value]
137
CHAPTER 7 MEMORY ACCESS MODES
[bit9, bit8] LMR1, LMR0
The LMR1 and LMR0 bits are used to specify the automatic wait function for external access to the
areas between 002000H and 7FFFFFH. Table 7.2-3 lists the settings that can be specified by combining
the LMR1 and LMR0 bits.
Table 7.2-3 LMR1 and LMR0 (Automatic Wait Function Specification Bit) Functions
138
LMR1
LMR0
Function
0
0
Automatic wait disabled [initial value]
0
1
Automatic wait of 1 cycle is inserted for external access
1
0
Automatic wait of 2 cycles is inserted for external access
1
1
Automatic wait of 3 cycles is inserted for external access
CHAPTER 7 MEMORY ACCESS MODES
7.2.3
External Address Output Control Register (HACR)
The external address output control register (HACR) controls the external output of
addresses (A23 to A16). The bits correspond to addresses A23 to A16, which control
address output pins, as shown in Figure 7.2-4 .
■ External Address Output Control Register (HACR)
Figure 7.2-4 External Address Output Control Address Configuration
External address output control register
7
6
5
4
3
2
1
0
Address:0000A6H
E23
E22
E21
E20
E19
E18
E17
E16
Read/write
Initial value
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
bit
HACR
The HACR register controls output of addresses (A23 to A16) to the external circuit. The address output
pin is controlled as follows with the eight bits that correspond to address bits A23 to A16.
The HACR register cannot be accessed when the device is in single-chip mode, since all pins function as I/O
ports whatever the value of this register.
All bits of this register are write only bits, and the value read from the bits is "1".
Table 7.2-4 External Address Output Control Register (E23 to E16 bits) Functions
0
The corresponding pin is used for address output (A23 to A16) [initial value].
1
The corresponding pin is used as an I/O port (P27 to A20).
139
CHAPTER 7 MEMORY ACCESS MODES
7.2.4
Bus Control Signal Selection Register (ECSR)
The bus control signal selection register sets the bus operation control function in
external bus mode. This register cannot be accessed when the device is in single-chip
mode, since all pins function as I/O ports whatever the value of this register. All bits of
the bus control signal selection register are write only bits, and the value from the bits
is "1".
■ Bus Control Signal Selection Register (ECSR)
Figure 7.2-5 Bus Control Signal Selection Register Configuration
Bus control signal selection register
15
14
Address:0000A7H
CKE
RYE
Read/write
Initial value
(W)
(0)
(W)
(0)
bit
13
12
11
10
9
8
HDE IOBS HMBS WRE LMBS
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
ECSR
(-)
(-)
[bit15] CKE
The CKE bit controls output of the external clock signal pin (CLK), as shown in Table 7.2-5 .
Table 7.2-5 CKE (External Clock (CLK) Output Control Bit) Functions
0
I/O port (P37) operation (clock output disabled) [initial value]
1
Clock signal (CLK) output enabled
[bit14] RYE
The RYE bit controls input of the external ready (RDY) signal pin, as shown in Table 7.2-6 .
Table 7.2-6 RYE (External Ready (RDY) Input Control Bit) Functions
0
I/O port (P36) operation (external RDY input disabled) [initial value]
1
External ready (RDY) input enabled
[bit13] HDE
The HDE bit specifies that input-output of hold signals is enabled. The hold request input signal (HRQ)
and hold acknowledge output signal (HAK) are controlled according to the setting of the HDE bit, as
shown in Table 7.2-7 .
Table 7.2-7 HDE (Hold Signal Input-Output Enable Specification Bit) Functions
140
0
I/O port (P35, P34) operation (hold function input-output disabled) [initial value]
1
Hold request (HRQ) input/hold acknowledge (HAK) output enabled
CHAPTER 7 MEMORY ACCESS MODES
[bit12] IOBS
The IOBS bit is used to specify the bus width for external access to the area from 0000C0H to 0000FFH
in external 16-bit data bus mode. Control is based on the setting of this bit, as shown in Table 7.2-8 .
Table 7.2-8 IOBS (Bus Width Specification Bit)
0
16-bit bus width access [initial value]
1
8-bit bus width access
[bit11] HMBS
The HMBS bit is used to specify the bus width for external access to the area from 800000H to
FFFFFFH in external 16-bit data bus mode. Control is based on the setting of this bit, as shown in Table
7.2-9 .
Table 7.2-9 HMBS (Bus Width Specification Bit)
0
16-bit bus width access [initial value]
1
8-bit bus width access
[bit10] WRE
The WRE bit controls output of external write signals (both WRH and WRL pins in external 16-bit data
bus mode and WR pin in external 8-bit data bus mode), as shown in Table 7.2-10 .
In external 8-bit data bus mode, P33 functions as the I/O port regardless of the setting value of this bit.
Table 7.2-10 WRE (External Write Signal Output Control Bit) Functions
0
I/O port (P33, P32) operation (write signal output disabled) [initial value]
1
Write strobe signal (WRH/WRL or WR only) output enabled
141
CHAPTER 7 MEMORY ACCESS MODES
[bit9] LMBS
The LMBS bit is used to specify the bus width for external access to the area from 002000H to
7FFFFFH in external 16-bit data bus mode. Control is based on the setting of this bit, as shown in Table
7.2-11 .
Table 7.2-11 LMBS (Bus Width Specification Bit)
0
16-bit bus width access [initial value]
1
8-bit bus width access
Notes:
• To use the WRE bit to enable the WR, WRH and WRL functions in external 16-bit data bus mode,
place P33 and P32 in input mode (set bit3 and bit2 of the DDR3 register to "0").
• To use the WRE bit to enable the WR function in external 8-bit data bus mode, place P32 in input
mode (set bit2 of the DDR3 register to "0").
• If the RYE and HDE bits are used to enable the RDY and HRQ signals, the I/O port function of the
port is also enabled. Be sure to write "0" (input mode) to the DDR3 register that corresponds to
the port.
142
CHAPTER 7 MEMORY ACCESS MODES
7.3
External Memory Access Control Signal Operation
If the ready function is not used, external memory is accessed in three cycles. The 8-bit
bus width access function is used to read and write the 8-bit width peripheral chip when
the 8- and 16-bit width peripheral chips are connected together to the external bus.
■ External Memory Access Control Signal
The HMBS, LMBS, and IOBS bits of the ECSR register are used to specify whether 16-bit bus width
access or 8-bit bus width access is to be used in external 16-bit data bus mode.
Actually, bus operation may not be performed by providing only address output and assert output of the
ALE signal without asserting RD, WRL/WR, and WRH. Be sure that access to a peripheral chip using only
the ALE signal is not executed.
Figure 7.3-1 Access Timing Chart for External 8-bit Data Bus Mode)
Read
Read
Write
P37/CLK
P33/WRH
(Port data)
P32/WRL/WR
P31/RD
P30/ALE
P27/A23 to P20/A16
Read address
Write address
Read address
P17/AD15 to P10/AD08
Read address
Write address
Read address
P07/AD07 to P00/AD00
Write
address
Read
address
Read data
Read address
Write data
143
CHAPTER 7 MEMORY ACCESS MODES
Figure 7.3-2 Access Timing Chart for External 16-bit Data Bus Mode
(16-bit bus width access, 8-bit bus width access)
8-bit bus width byte read
Even address byte read
8-bit bus width byte write
Even address byte write
P37/CLK
P33/WRH
P32/WRL/WR
P31/RD
P30/ALE
P27/A23 to P20/A16
Read address
P17/AD15 to P10/AD08
Read address
P07/AD07 to P00/AD00
Read address
Read address
Write address
Invalid
(Undefined)
Write address
Read address
Write address
Read data
Odd address byte read
Read address
Write data
Odd address byte write
P37/CLK
P33/WRH
P32/WRL/WR
P31/RD
P30/ALE
P27/A23 to P20/A16
Read address
P17/AD15 to P10/AD08
Read address
P07/AD07 to P00/AD00
Read address
Invalid
Write address
Read address
Write address
Read address
Read data
Even address word read
(Undefined)
Write address
Read address
Write data
Even address word write
P37/CLK
P33/WRH
P32/WRL/WR
P31/RD
P30/ALE
P27/A23 to P20/A16
Read address
Write address
Read address
P17/AD15 to P10/AD08
Read address
Write address
Read address
P07/AD07 to P00/AD00
Read address
Write address
Read address
Read data
Write data
Note:
Set the external circuit so that data is always read in word mode.
The setting of P36/RDY pin or the automatic ready function selection register (ARSR) enables access to low-speed
memory and peripheral circuits.
144
CHAPTER 7 MEMORY ACCESS MODES
7.3.1
Ready Function
The setting of P36/RDY pin or the automatic ready function selection register (ARSR)
enables access to the low-speed memory and peripheral circuits.
If the RYE bit of the bus control signal selection register (ECSR) is set to "1", the wait
cycle is entered to enable extension of the access cycle while the L level is input to P36/
RDY signal during access to the external circuit.
■ Ready Function
Figure 7.3-3 Timing Chart for Ready Function
Even address word read
Even address word write
P37/CLK
P33/WRH
P32/WRL/WR
P31/RD
P30/ALE
P27/A23 to P20/A16
Read address
Write address
P17/AD15 to P10/AD08
Read address
Write address
P07/AD07 to P00/AD00
Read address
Write address
P36/RDY
RDY pin fetch
Even address word write
Read data
Write data
Even address word read
P37/CLK
P33/WRH
P32/WRL/WR
P31/RD
P30/ALE
P27/A23 to P20/A16
Write address
Read address
P17/AD15 to P10/AD08
Write address
Read address
P07/AD07 to P00/AD00
Write address
Read address
Write data
Cycle extended by auto ready
145
CHAPTER 7 MEMORY ACCESS MODES
The MB90440G has two types of auto ready functions for external memory access. The auto ready function
can automatically insert 1 to 3 wait cycles to extend the access cycle without an external circuit for access
to the external areas at lower addresses 002000H to 7FFFFFH and at upper addresses 800000H to FFFFFFH.
This function is activated according to the setting of the LMR1 and LMR0 bits (external areas at lower
addresses) of ARSR and the HMR1 and HMR0 bits (external area at upper addresses) of ARSR.
The MB90440G also has an auto ready function for I/O that is independent of the auto ready function for
memory. When the IOR1 and IOR0 bits of the ARSR register are set to "0", 1 to 3 wait cycles can be
automatically inserted to extend the access cycle without an external circuit for access to the external area
from addresses 0000C0H to 0000FFH.
If the RYE bit of the ECSR is set to "1" and the "L" level is continues to be input to P36/RDY pin after the
wait cycle using the auto ready function for external memory and for external I/O is completed, the wait
cycle continues.
146
CHAPTER 7 MEMORY ACCESS MODES
7.3.2
Hold Function
If the HDE bit in the bus control signal selection register (ECSR) is set to "1", the
external bus hold function specified by the P34/HRQ and P35/HAK pins is enabled.
■ Hold Function
If the high level is applied to the P34/HRQ pin, the hold state is set up at termination of a CPU instruction
(for a string instruction, at termination of 1-element data processing). The P35/HAK pin outputs the low
level to place the following pins in a high-impedance state:
•
Address output: P27/A23 to P20/A16
•
Address/data I/O: P17/AD15 to P10/AD08, P07/AD07 to P00/AD00
•
Bus control signal: P30/ALE, P31/RD, P32/WRL/WR, P33/WRH
Thus, an external bus can be used from a device external circuit. When the low level is input to the P34/
HRQ pin, the P35/HAK pin outputs the high-level, thereby restoring the external pin state and restarting the
CPU operation. In the stop status, hold request input is not accepted.
Figure 7.3-4 shows the hold timing.
Figure 7.3-4 Hold Timing
Read cycle
Hold cycle
Write cycle
P37/CLK
P34/HRQ
P35/HAK
P33/WRH
P32/WRL
P31/RD
P30/ALE
P27/A23 to P20/A16
(Address)
(Address)
P17/AD15 to P10/AD08
(Address)
P07/AD07 to P00/AD00
(Address)
Read data
Write data
147
CHAPTER 7 MEMORY ACCESS MODES
148
CHAPTER 8
I/O PORTS
This chapter explains the functions and operations of
the I/O ports.
8.1 I/O Ports
8.2 Input Levels of I/O Ports
8.3 I/O Port Registers
149
CHAPTER 8 I/O PORTS
8.1
I/O Ports
Each pin of the ports can be specified as input or output using the port direction
register (DDR) if the corresponding peripheral does not use the pin.
■ Outline of I/O Ports
When a pin is specified as input, the logic level at the pin is read. When a pin is specified as output, the
data register value is read. The above also applies to a read operation for the read-modify-write
instructions.
However, When a pin is used as an output for another peripheral, the logic level at the pin is read regardless
of the value of the data register.
It is generally recommended that the read-modify-write instructions not be used for setting the data register
before a port is set for output and the output of the peripheral resource is switched off. The reason is that a
read-modify-write instruction in this case reads the logic level at the port instead of the register value.
Figure 8.1-1 is a block diagram of the I/O ports.
Figure 8.1-1 Block Diagram of I/O Port
Internal data bus
Data register read
Data register
Data register write
Direction register
Direction register write
Direction register read
150
Pin
CHAPTER 8 I/O PORTS
8.2
Input Levels of I/O Ports
The input level of the I/O ports can be selected by register (PILR)
■ Input Levels
Devices of the MB90440G series are operating with TTL input levels on ports P07 to P00, P17 to P10, P27
to P20, P37 to P30 and CMOS levels on all other ports by default.
The input levels can be changed for ports P07 to P00, P17 to P10, P27 to P20, P37 to P30 to CMOS levels,
this can be done using the PILR register (refer to "8.3 I/O Port Registers").
For all other ports the input levels can be changed to AUTOMOTIVE levels port by port, this can be done
using the PILR register (refer to "8.3 I/O Port Registers").
Note:
The settings of the PILR register will be cleared to default values with every reset. If you want to use
input levels different to the default levels, please take this fact into consideration.
151
CHAPTER 8 I/O PORTS
8.3
I/O Port Registers
Figure 8.3-1 shows the bit configuration of the I/O port registers.
■ I/O Port Registers
Figure 8.3-1 I/O Port Registers
bit
15/7
14/6
13/5
12/4
11/3
10/2
9/1
8/0
Address : 000000H
P07
P06
P05
P04
P03
P02
P01
P00
Port 0 data register (PDR0)
Address : 000001H
P17
P16
P15
P14
P13
P12
P11
P10
Port 1 data register (PDR1)
Address : 000002H
P27
P26
P25
P24
P23
P22
P21
P20
Port 2 data register (PDR2)
Address : 000003H
P37
P36
P35
P34
P33
P32
P31
P30
Port 3 data register (PDR3)
Address : 000004H
P47
P46
P45
P44
P43
P42
P41
P40
Port 4 data register (PDR4)
Address : 000005H
P57
P56
P55
P54
P53
P52
P51
P50
Port 5 data register (PDR5)
Address : 000006H
P67
P66
P65
P64
P63
P62
P61
P60
Port 6 data register (PDR6)
Address : 000007H
P77
P76
P75
P74
P73
P72
P71
P70
Port 7 data register (PDR7)
Address : 000008H
P87
P86
P85
P84
P83
P82
P81
P80
Port 8 data register (PDR8)
Address : 000009H
P97
P96
P95
P94
P93
P92
P91
P90
Port 9 data register (PDR9)
PA0
Port A data register (PDRA)
Address : 00000AH
bit
15
14
13
12
11
10
9
8
Address : 00000BH
L7
L6
L5
L4
L3
L2
L1
L0
bit
15/7
14/6
13/5
12/4
11/3
10/2
9/1
8/0
Address : 000010H
D07
D06
D05
D04
D03
D02
D01
D00
Port 0 direction register (DDR0)
Address : 000011H
D17
D16
D15
D14
D13
D12
D11
D10
Port 1 direction register (DDR1)
Address : 000012H
D27
D26
D25
D24
D23
D22
D21
D20
Port 2 direction register (DDR2)
Address : 000013H
D37
D36
D35
D34
D33
D32
D31
D30
Port 3 direction register (DDR3)
Address : 000014H
D47
D46
D45
D44
D43
D42
D41
D40
Port 4 direction register (DDR4)
Address : 000015H
D57
D56
D55
D54
D53
D52
D51
D50
Port 5 direction register (DDR5)
Address : 000016H
D67
D66
D65
D64
D63
D62
D61
D60
Port 6 direction register (DDR6)
Address : 000017H
D77
D76
D75
D74
D73
D72
D71
D70
Port 7 direction register (DDR7)
Address : 000018H
D87
D86
D85
D84
D83
D82
D81
D80
Port 8 direction register (DDR8)
Address : 000019H
D97
D96
D95
D94
D93
D92
D91
D90
Port 9 direction register (DDR9)
DA0
Port A direction register (DDRA)
Address : 00001AH
bit
14/6
13/5
12/4
11/3
10/2
9/1
8/0
Address : 00001CH PU07 PU06 PU05 PU04 PU03 PU02 PU01 PU00
Port 0 pull-up control register (PUCR0)
Address : 00001DH PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10
Port 1 pull-up control register (PUCR1)
Address : 00001EH
PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20
Port 2 pull-up control register (PUCR2)
Address : 00001EH
PU37 PU36 PU35 PU34 PU33 PU32 PU31 PU30
Port 3 pull-up control register (PUCR3)
bit
Address : 00001BH
152
15/7
Port input level register (PILR)
15
14
13
12
11
10
9
8
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
Port 6 analog input enable register (ADER)
CHAPTER 8 I/O PORTS
8.3.1
Port Data Register (PDR)
Figure 8.3-2 shows the detailed bit configuration of the port data register (PDR).
■ Port data Register (PDR)
Figure 8.3-2 Port Data Registers (PDR)
bit
PDR0
Address : 000000H
bit
PDR1
Address : 000001H
bit
PDR2
Address : 000002H
bit
PDR3
Address : 000003H
bit
PDR4
Address : 000004H
bit
PDR5
Address : 000005H
bit
PDR6
Address : 000006H
bit
PDR7
Address : 000007H
bit
PDR8
Address : 000008H
bit
PDR9
Address : 000009H
bit
PDRA
Address : 00000AH
7
6
5
4
3
2
1
0
Initial value
P07
P06
P05
P04
P03
P02
P01
P00
Undefined
R/W *
15
14
13
12
11
10
9
8
P17
P16
P15
P14
P13
P12
P11
P10
Undefined
R/W *
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
Undefined
R/W *
15
14
13
12
11
10
9
8
P37
P36
P35
P34
P33
P32
P31
P30
Undefined
R/W *
7
6
5
4
3
2
1
0
P47
P46
P45
P44
P43
P42
P41
P40
Undefined
R/W *
15
14
13
12
11
10
9
8
P57
P56
P55
P54
P53
P52
P51
P50
Undefined
R/W *
7
6
5
4
3
2
1
0
P67
P66
P65
P64
P63
P62
P61
P60
Undefined
R/W *
15
14
13
12
11
10
9
8
P77
P76
P75
P74
P73
P72
P71
P70
Undefined
R/W *
7
6
5
4
3
2
1
0
P87
P86
P85
P84
P83
P82
P81
P80
Undefined
R/W *
15
14
13
12
11
10
9
8
P97
P96
P95
P94
P93
P92
P91
P90
Undefined
R/W *
7
6
5
4
3
2
1
0
Undefined
R/W *
PA0
Access
*: Note the following differences between R/W for the I/O ports and R/W for memory:
- Input mode
Read: The level at the corresponding pin is read.
Write: Data is written to an output latch.
- Output mode
Read: The pin output value is read.
Write: Data is written to an output latch and output to the corresponding pin.
153
CHAPTER 8 I/O PORTS
8.3.2
Port Input Level Register (PILR)
Figure 8.3-3 shows the bit configuration of the port input level register (PILR).
■ Port Input Level Register (PILR)
Figure 8.3-3 Port Input Level Registers (PILR)
bit
PILR
Address : 00000BH
15
L7
14
L6
13
L5
12
L4
11
L3
10
L2
9
8
Initial value
Access
L1
L0
00000000B
R/W
Table 8.3-1 shows the possible bit settings of PILR and the corresponding input levels of the ports.The
settings of the PILR register will be cleared to default values with every reset. If you want to use input
levels different to the default levels, please take this fact into consideration.
Table 8.3-1 Details of Port Input Level Register (PILR)
Bit
154
Corresponding ports
L0
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37
L1
P40 to P47
L2
P50 to P57
L3
P60 to P67
L4
P70 to P77
L5
P80 to P87
L6
P90 to P97
L7
PA0
Input levels of ports
0: TTL level
1: CMOS hysteresis input level
0: CMOS hysteresis input level
1: AUTOMOTIVE input level
0: CMOS hysteresis input level
1: AUTOMOTIVE input level
0: CMOS hysteresis input level
1: AUTOMOTIVE input level
0: CMOS hysteresis input level
1: AUTOMOTIVE input level
0: CMOS hysteresis input level
1: AUTOMOTIVE input level
0: CMOS hysteresis input level
1: AUTOMOTIVE input level
0: CMOS hysteresis input level
1: AUTOMOTIVE input level
Initial value
0
0
0
0
0
0
0
0
CHAPTER 8 I/O PORTS
8.3.3
Port Direction Register (DDR)
Figure 8.3-4 shows the bit configuration of the port direction register (DDR).
■ Port Direction Register (DDR)
Figure 8.3-4 Port Direction Registers (DDR)
7
bit
DDR0
D07
Address : 000010H
bit
DDR1
Address : 000011H
bit
DDR2
Address : 000012H
bit
DDR3
Address : 000013H
6
5
4
3
2
1
D06
D05
D04
D03
D02
D01
15
14
13
12
11
10
D17
D16
D15
D14
D13
D12
7
D23
D22
15
14
13
12
11
10
D37
D36
D35
D34
D33
D32
bit 7
D67
bit 15
D77
bit 7
DDR8
Address : 000018H
D87
bit 15
DDR9
Address : 000019H
D97
bit 7
DDRA
Address : 00001AH
2
D24
D57
DDR7
Address : 000017H
3
D25
bit 15
DDR6
Address : 000016H
4
D26
D47
DDR5
Address : 000015H
5
D27
bit 7
DDR4
Address : 000014H
6
6
5
4
3
2
D46
D45
D44
D43
D42
14
13
12
11
10
D56
D55
D54
D53
D52
6
5
4
3
2
D66
D65
D64
D63
D62
14
13
12
11
10
D76
D75
D74
D73
D72
6
5
4
3
2
D86
D85
D84
D83
D82
14
13
12
11
10
D96
D95
D94
D93
D92
6
5
4
3
2
9
D11
1
D21
9
D31
1
D41
9
D51
1
D61
9
D71
1
D81
9
D91
1
0
D00
Initial value
Access
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
- - - - - - - 0B
R/W
8
D10
0
D20
8
D30
0
D40
8
D50
0
D60
8
D70
0
D80
8
D90
0
DA0
When a pin functions as a port, the corresponding pin is controlled as follows:
0: Input mode
1: Output mode
The bits are set to "0" by a reset.
155
CHAPTER 8 I/O PORTS
8.3.4
Pull-up Control Register (PUCR)
Figure 8.3-5 shows the bit configuration of the pull-up control register (PUCR), and
Figure 8.3-6 is the block diagram.
■ Pull-up Control Register (PUCR)
Figure 8.3-5 Bit Configuration of Pull-up Control Register (PUCR)
Pull-up control register
bit 7
5
4
3
2
1
0
Address : 00001CH
PU07 PU06 PU05 PU04 PU03 PU02 PU01 PU00
Read/write
Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
bit 15
14
13
12
11
10
9
PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10
Read/write
Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
6
5
4
3
2
1
PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20
Read/write
Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
14
13
12
11
10
9
PUCR1
0
Address : 00001EH
bit 15
PUCR0
8
Address : 00001DH
bit 7
156
6
PUCR2
8
Address : 00001FH
PU37 PU36 PU35 PU34 PU33 PU32 PU31 PU30
Read/write
Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
PUCR3
CHAPTER 8 I/O PORTS
■ Block Diagram of Pull-up Control Register (PUCR)
Figure 8.3-6 Block Diagram of Pull-up Control Register (PUCR)
Pull-up resistor (about 50K )
P-ch
Data register
Port input-output
Direction register
Pull-up Control Register
Internal data bus
Note:
In input mode, the pull-up resistor is controlled.
0: No pull-up resistor in input mode
1: Pull-up resistor in input mode
In output mode, this register has no meaning (no pull-up resistor).
The direction register (DDR) determines the input-output mode.
In stop mode (SPL=1), the state with no pull-up resistor is entered (high impedance).
If the port is used as an external bus, this function is disabled and data is not written to the register.
157
CHAPTER 8 I/O PORTS
8.3.5
Analog Input Enable Register (ADER)
Figure 8.3-7 shows the bit configuration of the analog input enable register (ADER).
■ Analog Input Enable Register (ADER)
Figure 8.3-7 Bit Configuration of Analog Input Enable Register (ADER)
Analog Input Enable Register
bit 15
Address : 00001BH
Read/write
Initial value
14
13
12
11
10
9
8
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
ADER
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
The analog input enable register (ADER) controls the pins of port 6 as follows:
• 0: Port input mode
• 1: Analog input mode
If an external pin is used as analog input of the A/D converter, set the corresponding bit to "1".
158
CHAPTER 9
TIME-BASE TIMER
This chapter explains the functions and operations of
the time-base timer.
9.1 Outline of Time-base Timer
9.2 Time-Base Timer Control Register (TBTC)
9.3 Operations of Time-base Timer
159
CHAPTER 9 TIME-BASE TIMER
9.1
Outline of Time-base Timer
The time-base timer consists of an 18-bit timer and a circuit that controls an interval
interrupt. The time-base timer uses the main clock signal regardless of the MCS and
SCS bits of the clock selection register (CKSCR).
■ Time-base Timer Registers
Figure 9.1-1 Time-base Timer Registers
Time-base timer control register
bit
Address : 0000A9H
Read/write
Initial value
160
15
14
13
Reserved
(R/W)
(1)
(-)
(-)
(-)
(-)
12
11
10
9
8
TBIE
TBOF
TBR
TBC1
TBC0
(R/W)
(0)
(R/W)
(0)
(R/W)
(R/W)
(0)
(R/W)
(0)
(1)
TBTC
CHAPTER 9 TIME-BASE TIMER
■ Block Diagram of Time-base Timer
Figure 9.1-2 Block Diagram of Time-base Timer
Main clock
TBTC
TBC1
Selector
TBC0
Clock input
212
214
16
2
Time-base timer
219
212 214 216 219
TBTRES
TBR
TBIE
AND
Q
TBOF
S
R
Time-base
interrupt
WDTC
WT1
Selector
WT0
2-bit counter
OF
CLR
Watchdog reset
generation circuit
CLR
Internal data bus
WTE
WDGRST
To internal reset
generation circuit
WTC
WDCS
AND
SCE
Q
SCM
Power-on reset*
Sub clock stop
S
R
210
WTC2
WTC1
WTC0
WTOF
214
215
Watch timer
WTR
WTIE
213
Selector
WTRES
AND
Q
S
R
Clock input
Sub clock/4
Watch
interrupt
WDTC
PONR
From power-on generation
WRST
ERST
RST pin
SRST
From RST bit of
LPMCR register
161
CHAPTER 9 TIME-BASE TIMER
9.2
Time-Base Timer Control Register (TBTC)
The time-base timer control register (TBTC) controls the operation of the time-base
timer and the interval interrupt time.
■ Time-base Timer Control Register (TBTC)
Figure 9.2-1 Time-base Timer Control Register (TBTC)
Time-base timer control register
bit
Address : 0000A9H
15
14
13
Reserved
Read/write
Initial value
(R/W)
(1)
(-)
(-)
(-)
(-)
12
11
10
9
8
TBIE
TBOF
TBR
TBC1
TBC0
(R/W)
(0)
(R/W)
(0)
(R/W)
(R/W)
(0)
(R/W)
(0)
(1)
TBTC
[bit15] Reserved : Reserved bit
Ensure that "1" is always written to this bit.
[bit14, bit13] Undefined bits
Bit14 and bit13 are undefined.
[bit12] TBIE
This bit is used to enable interval interrupts based on the time-base timer. Writing "1" to this bit enables
interrupts, and writing "0" disables interrupts. This bit is initialized to "0" upon a reset. This bit is
readable and writable.
[bit11] TBOF
This is an interrupt request flag for the time-base timer. While the TBIE bit is "1", an interrupt request is
issued when "1" is written to TBOF. This bit is set to "1" for each interval specified with the TBC1 and
TBC0 bits.
This bit is cleared by writing "0", transition to main stop mode, PLL stop mode, from sub clock mode to
main clock mode, and from the sub clock mode to the PLL clock mode, from main clock mode to PLL
clock mode, or writing "0" to the TBR bit or a reset. Writing "1" has no effect.
"1" is always read by a read-modify-write instruction.
Note:
To clear the TBOF bit, specify the time-base timer interrupt inhibited state in the interrupt level mask
register (ILM) of processor status (PS) or the TBIE bit.
[bit10] TBR
This bit clears all bits of the time-base timer counter to "0".
Writing "0" clears the time-base counter.
Writing "1" has no effect.
"1" is always read from this bit.
162
CHAPTER 9 TIME-BASE TIMER
[bit9, bit8] TBC1 and TBC0
These bits are used to set the time-base timer interval. These bits are initialized to "00B" by a reset.
These bits can be read and written to.
Table 9.2-1 lists the settings for the time-base timer interval.
Table 9.2-1 Settings for Time-base Timer Interval
TBC1
TBC0
Interval at 4 MHz source oscillation
0
0
1.024 ms
0
1
4.096 ms
1
0
16.384 ms
1
1
131.072 ms
163
CHAPTER 9 TIME-BASE TIMER
9.3
Operations of Time-base Timer
The time-base timer functions as a watchdog timer clock source, timer for waiting for
main clock and PLL clock oscillation to stabilize, and interval timer for generating
interrupts at specified intervals.
■ Time-base Timer
The time-base timer consists of an 18-bit counter that counts the pulses of the oscillation clock used to
generate the machine clock. While the oscillation clock is input, the time-base timer keeps counting.
The time-base timer is cleared by a power-on reset, transition to main stop mode, transition to PLL stop
mode, or transition from the main clock mode to the PLL clock mode. The time-base timer is also cleared
by transition from the sub clock mode to the main clock mode, transition from the sub clock mode to the
PLL clock mode, or writing "0" to the TBR bit of the time-base timer control register (TBTC).
The watchdog counter and interval interrupt function using output from the time-base timer are affected by
clearing the time-base counter.
■ Interval Interrupt Function of Time-base Timer
Interrupts are generated at specified intervals according to the carry signals of the time-base counter. The
TBOF flag is set at the intervals specified with the TBC1 and TBC0 bits of the time-base timer control
register (TBTC). This flag is set by using as a reference the last time that the time-base timer was cleared.
On transition from main clock mode to PLL clock mode, the time-base timer is cleared because the timebase timer is used as a timer that waits for PLL clock oscillation to stabilize.
On transition from sub clock mode to main clock mode, the time-base timer is cleared because the timebase timer is used as a timer that waits for oscillation of the oscillation clock to stabilize.
On transition to main stop mode, PLL stop mode, the TBOF flag is immediately cleared when mode
transition is complete because the time-base timer is used as a timer that waits until oscillation to stabilize
upon recovery.
164
CHAPTER 10
WATCHDOG TIMER
This chapter explains the functions and operations of
the watchdog timer.
10.1 Outline of Watchdog Timer
10.2 Watchdog Timer Control Register (WDTC)
10.3 Watchdog Timer Operation
165
CHAPTER 10 WATCHDOG TIMER
10.1
Outline of Watchdog Timer
The watchdog timer consists of a 2-bit watchdog counter that uses the carry signal of
the 18-bit time-base timer or 15-bit watch timer as a clock source, control register, and
watchdog reset controller.
■ Watchdog Timer Register
Figure 10.1-1 Watchdog Timer Register
Watchdog timer control register
bit
Address : 0000A8H
Read/write
Initial value
166
7
6
PONR
--
(R)
(X)
(-)
(-)
5
4
3
2
WRST ERST SRST WTE
(R)
(X)
(R)
(X)
(R)
(X)
(W)
(1)
1
0
WT1
WT0
(W)
(1)
(W)
(1)
WDTC
CHAPTER 10 WATCHDOG TIMER
■ Block Diagram of Watchdog Timer
Figure 10.1-2 Block Diagram of Watchdog Timer
Main clock
TBTC
TBC1
Selector
TBC0
212
Clock input
214
16
2
Time-base timer
219
212 214 216 219
TBTRES
TBR
TBIE
AND
Q
TBOF
S
R
Internal data bus
Time-base
interrupt
WDTC
WT1
Selector
WT0
2-bit counter
OF
CLR
Watchdog reset
generation circuit
CLR
WTE
WDGRST
To internal reset
generation circuit
WTC
WDCS
AND
SCE
Q
SCM
Power-on reset
Sub clock stop
S
R
210
WTC2
WTC1
WTC0
WTOF
214
215
Selector
Watch timer
WTR
WTIE
213
WTRES
AND
Q
S
R
Clock input
Sub clock/4
Watch
interrupt
WDTC
PONR
From power-on generation
WRST
ERST
RST pin
SRST
From RST bit of
LPMCR register
167
CHAPTER 10 WATCHDOG TIMER
10.2
Watchdog Timer Control Register (WDTC)
The watchdog timer control register (WDTC) consists of the bits that control the
watchdog timer and bits that identify reset causes.
■ Watchdog Timer Control Register (WDTC)
Figure 10.2-1 Watchdog Timer Control Register (WDTC)
Watchdog timer control register
7
6
PONR
--
bit
Address : 0000A8H
Read/write
Initial value
(R)
(X)
(-)
(-)
5
4
3
2
WRST ERST SRST WTE
(R)
(X)
(R)
(X)
(R)
(X)
(W)
(1)
1
0
WT1
WT0
(W)
(1)
(W)
(1)
WDTC
[bit7 and bit5 to bit3] PONR, WRST, ERST, and SRST
These flags indicate the reset causes. The flags are set upon a reset as described in Table 10.2-1 .
All bits are cleared to "0" after the WDTC register is read. These bits are read only bits. At power-on,
the values of reset cause bits other than PONR bit are undefined. When the PONR bit is "1", ensure that
the values of the bits other than PONR bit are ignored.
Table 10.2-1 Reset Cause Bits and Reset Causes
Reset cause
PONR
WRST
ERST
SRST
Power-on
1
-
-
-
Watchdog timer
*
1
*
*
External pin
*
*
1
*
RST bit
*
*
*
1
(*: The previous value is maintained.)
[bit2] WTE
While the watchdog timer is stopped, writing "0" to this bit activates the watchdog timer. Subsequently,
writing "0" clears the watchdog timer counter. Writing "1" has no effect.
The watchdog timer is stopped by reset. "1" is always read from this bit.
168
CHAPTER 10 WATCHDOG TIMER
[bit1, bit0] WT1 and WT0
These bits are used to select the watchdog timer interval.
Only the data items written during watchdog timer activation are valid. Data items that are written at
any other time are ignored. In the two clocks system parts, the clock signal input to the watchdog timer
is selected according to the result of adding the values of the WDCS bit of the watch timer control
register (WTC) and SCM bit of the clock selection register (CKSCR). If WDCS=1 (main clock and
PLL clock are selected as the machine clock), the time-base timer output time and sub clock interval
setting listed in Table 10.2-2 are selected.
Table 10.2-2 Access to WT1 and WT0 (Read only)
Interval *
WDCS
SCM
WT1
1
0
1
WT0
Minimum
Maximum
0
About 3.58ms
About 4.61ms
0
1
About 14.33ms
About 18.43ms
1
1
0
About 57.23ms
About 73.73ms
1
1
1
About 458.75ms
About 589.82ms
0
0
0
About 0.457s
About 0.576s
0
0
1
About 3.584s
About 4.608s
0
1
0
About 7.167s
About 9.216s
0
1
1
About 14.336s
About 18.432s
*: For a source oscillation of 4 MHz. For a sub-oscillation clock of 32 kHz.
Note:
The interval time uses the carry signal of the time-base timer or clock timer as a count clock. If the
time-base timer or clock timer is cleared, the interval time of the watchdog timer may become long.
The time-base timer is also cleared by writing "0" to the TBR bit in the time-base timer control
register (TBTC), transition from main clock mode to PLL clock mode, transition from sub clock mode
to main clock mode and transition from sub clock mode to PLL clock mode.
169
CHAPTER 10 WATCHDOG TIMER
10.3
Watchdog Timer Operation
The watchdog timer function enables detection of program surge. If "0" is not written to
the WTE bit of the watchdog timer within the specified time due to a program surge, the
watchdog timer issues a watchdog reset request.
■ Activating the Watchdog Timer
The watchdog timer is activated by writing "0" to the WTE bit of the watchdog timer control register
(WDTC) while the watchdog timer is stopped. At the same time, the WT1 and WT0 bits are used to set the
watchdog timer interval. Only the interval setting specified during activation is valid.
■ Resetting the Watchdog Timer
When the watchdog timer is activated, the 2-bit watchdog counter must be program-cleared. Specifically,
"0" must be periodically written to the WTE bit of the watchdog timer control register (WDTC). The
watchdog timer consists of a 2-bit counter that uses the carry signals of the time-base timer as a clock
source. When the time-base timer is cleared, the watchdog reset interval may exceed the setting.
Figure 10.3-1 is a diagram of the watchdog timer operation.
Figure 10.3-1 Watchdog Timer Operation
Time-base
00
Watchdog
01
10
00
01
10
11
00
WTE write
Watchdog activation
Watchdog clear
Watchdog reset occurs
■ Stopping the Watchdog Counter
Once activated, the watchdog timer is initialized and stopped only by power-on or reset by watchdog. Reset
by an external pin or software merely clears the watchdog counter without stopping the watchdog function.
■ Clearing the Watchdog Counter
The watchdog counter is cleared by writing "0" to the WTE bit of the watchdog timer control register
(WDTC), occurrence of a reset, or transition to sleep mode, stop mode, or hold acknowledge signal.
170
CHAPTER 11
WATCH TIMER
This chapter explains the functions and operations of
the watch timer.
11.1 Outline of Watch Timer
11.2 Watch Timer Control Register (WTC)
11.3 Watch Timer Operation
171
CHAPTER 11 WATCH TIMER
11.1
Outline of Watch Timer
The watch timer consists of a 15-bit timer and a circuit that controls an interval
interrupt. The watch timer uses sub clock signals regardless of the MCS bit and SCS bit
of the clock selection register (CKSCR).
■ Watch Timer Register
Figure 11.1-1 Watch Timer Control Register (WTC)
Watch timer control register
bit
6
5
4
3
2
1
0
WDCS SCE
WTIE WTOF WTR WTC2 WTC1 WTC0
Read/write
(R/W)
(R)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(1)
(X)
Address: 0000AAH
172
7
(0)
(0)
(1)
(0)
(0)
(0)
WTC
CHAPTER 11 WATCH TIMER
■ Block Diagram of Watch Timer
Figure 11.1-2 Block Diagram of Watch Timer
Main clock
TBTC
TBC1
Selector
TBC0
212
214
216
219
TBTRES
Clock input
Time-base timer
212
214
216
219
TBR
TBIE
AND
Q
S
R
TBOF
Time-base
interrupt
WDTC
OF
Selector
WT0
Internal data bus
Watchdog reset
generation circuit
2-bit counter
WT1
CLR
CLR
WDGRST
To internal reset
generation circuit
WTE
WTC
WDCS
AND
SCE
Q
SCM
Power-on reset
Sub clock stop
S
R
210
WTC2
WTC1
WTC0
Selector
WTR
WTIE
WTOF
Q
S
R
214
215
Watch timer
WTRES
AND
213
Clock input
Sub clock/4
Watch
interrupt
WDTC
PONR
From power-on generation
WRST
ERST
RST pin
SRST
From RST bit of
LPMCR register
173
CHAPTER 11 WATCH TIMER
11.2
Watch Timer Control Register (WTC)
The watch timer control register (WTC) controls the operation of the watch timer and the
interval interrupt time.
■ Watch Timer Control Register (WTC)
Figure 11.2-1 Watch Timer Control Register (WTC)
Watch timer control register
bit
7
6
5
4
3
2
1
0
WDCS SCE
WTIE WTOF WTR WTC2 WTC1 WTC0
Read/write
(R/W)
(R)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(1)
(X)
Address: 0000AAH
(0)
(0)
(1)
(0)
(0)
WTC
(0)
[bit7] WDCS
The WDCS bit is used to specify whether the clock signal of the watch timer or time-base timer is used
as the input clock of the watchdog timer when the main clock or PLL clock is selected as the machine
clock. When WDCS=0, the clock signal of the watch timer can be selected. When WDCS=1, the clock
signal of the time-base timer can be selected. When "1" is set in WDCS, the function that selects the
main clock or PLL clock uses the time-base timer output. Functions that include the sub clock use
output from the watch timer.
This bit is initialized to "1" by reset.
Note:
If WDCS is set to "1", the watchdog timer counter may be incremented because the time-base timer
output and watch timer output are asynchronous. If WDCS is set to "1", the watchdog timer must be
cleared before and after the clock mode is changed.
[bit6] SCE
The SCE bit indicates that the sub clock oscillation stabilization wait time has elapsed. When this bit is
"0", the oscillation stabilization is currently in progress. The oscillation stabilization time is fixed at 214
cycles (sub clock). This bit is initialized to "0" by a power-on reset and stop.
[bit5] WTIE
The WTIE bit enables an interval interrupt by the watch timer. When this bit is "1", the interrupt is
enabled. When this bit is "0", the interrupt is disabled. This bit is initialized to "0" by a reset. This bit
can be read and written to.
[bit4] WTOF
The WTOF bit is the watch timer interrupt flag. When the WTIE bit is "1" and WTOF is set to "1", an
interrupt request is issued. This bit is set to "1" at each interval specified by the WTC1 and WTC0 bits.
This bit is cleared by writing "0", transition to stop mode or a reset. Writing "1" has no effect.
During read operation using a read-modify-write instruction, "1" is always read from this bit.
174
CHAPTER 11 WATCH TIMER
[bit3] WTR
The WTR bit clears all bits of the watch timer counter to "0". Writing "0" to this bit clears the timer
counter. Writing "1" has no effect. The value read from this bit is always "1".
[bit2 to bit0] WTC2 to WTC0
The WTC2, WTC1, and WTC0 bits set the watch timer interval. Table 11.2-1 lists the settings for the
interval. These bits are initialized to "000B" by a reset. These bits can be read and written to.
When data is written to these bits, bit4 (WTOF) should be cleared.
Table 11.2-1 Settings for the Watch Timer Interval
WTC2
WTC1
WTC0
Interval (sub clock: 32kHz)
0
0
0
31.25 ms
0
0
1
62.5 ms
0
1
0
125 ms
0
1
1
250 ms
1
0
0
500 ms
1
0
1
1.000 s
1
1
0
2.000 s
1
1
1
4.000 s
175
CHAPTER 11 WATCH TIMER
11.3
Watch Timer Operation
The watch timer functions as a watchdog counter clock source, timer for waiting for the
sub clock oscillation to stabilize, and interval timer for generating interrupts at specified
intervals.
■ Watch Timer
The watch timer consists of a 15-bit counter that counts oscillation inputs generated by the sub clock.
While the sub clock is input, the watch timer keeps counting. The watch timer is cleared by a power-on
reset or writing "0" to the WTR bit of the watch timer control register (WTC).
Notes:
• Clearing the clock counter affects the watchdog counter and interval interrupts that use clock
timer output.
• To clear the clock timer by writing "0" to the WTR bit in the clock timer control register (WTC), set
the WTIE bit to "0" and set the clock timer to interrupt inhibited state. Before permitting an
interrupt, clear the interrupt request issued by writing "0" to the WTOF flag.
■ Interval Interrupt Function of Watch Timer
The interval interrupt function generates interrupts at specified intervals according to the carry signals of
the timer counter. The WTOF flag is set at the intervals specified by the WTC1 and WTC0 bits of the
watch timer control register (WTC). This flag is set by using as a reference the last time that the watch
timer was cleared.
On transition to stop, the watch timer is used as a timer for sub clock oscillation to stabilize upon recovery,
and the WTOF flag is immediately cleared upon mode transition.
176
CHAPTER 12
16-BIT I/O TIMER
This chapter explains the functions and operations of
the 16-bit I/O timer.
12.1 Outline of 16-Bit I/O Timer
12.2 16-bit I/O Timer Registers
12.3 16-bit Free-run Timer
12.4 Output Compare
12.5 Input Capture
177
CHAPTER 12 16-BIT I/O TIMER
12.1
Outline of 16-Bit I/O Timer
MB90440G series products contain one 16-bit free-run timer module, two output
compare modules, and four input capture modules, and support eight input channels
and four output channels. The following sections only describes the 16-bit free-run
timer, Output Compare 0/1 and Input Capture 0/1.
The remaining modules have the identical functions and the register addresses should
be found in the I/O map.
■ 16-bit Free-run Timer
The 16-bit free-run timer consists of a 16-bit up counter, control register, and prescaler. The values output
from this timer counter are used as the base timer for input capture and output compare.
• Four counter clocks are available.
- Internal clock: φ/4, φ/16, φ/64, φ/256
• An interrupt can be generated upon a counter overflow or a match with compare register 0.
• The counter value can be initialized to "0000H" upon a reset, software clear, or match with compare
register 0.
■ Output Compare (2 Channels per One Module)
The output compare module consists of two 16-bit compare registers, compare output latch, and control
register.
When the 16-bit free-run timer value matches the compare register value, the output level is reversed and
an interrupt is issued.
● The two compare registers can be used independently.
Output pins and interrupt flags corresponding to compare registers
● Output pins can be controlled based on pairs of the two compare registers.
Output pins can be reversed by using the two compare registers.
● Initial values for output pins can be set.
● Interrupts can be generated upon a compare match.
178
CHAPTER 12 16-BIT I/O TIMER
■ Input Capture (2 Channels per one Module)
The input capture module consists of two 16-bit capture registers and control registers corresponding to two
independent external input pins. The 16-bit free-run timer value can be stored in the capture register and an
interrupt is issued simultaneously upon detection of an edge of a signal input from an external input pin.
● The detection edge of an external input signal can be specified.
Rising, falling, or both edges
● Two input channels can operate independently.
● An interrupt can be issued upon a valid edge of an external input signal.
The intelligent I/O service can be activated upon an input capture interrupt.
■ Block Diagram of 16-bit I/O Timer
Figure 12.1-1 shows a block diagram of the 16-bit I/O timer.
Figure 12.1-1 Block Diagram of 16-bit I/O Timer
Control logic
To each block
Interrupt
16-bit free-run timer
16-bit timer 1
Internal data bus
Clear
Output compare 0
Compare register 0
T
Q
OUT0
T
Q
OUT1
Edge selection
IN0
Edge selection
IN1
Output compare 1
Compare register 1
Input capture 0
Capture register 0
Input capture 1
Capture register 1
179
CHAPTER 12 16-BIT I/O TIMER
12.2
16-bit I/O Timer Registers
The 16-bit I/O timer has the following three registers:
• 16-bit free-run timer register
• 16-bit output compare register
• 16-bit input capture register
■ 16-bit I/O Timer Registers
Figure 12.2-1 16-bit I/O Timer Registers
16-bit free-run timer register
bit15
bit0
TCDT
Address : 00006CH
bit7
Address : 00006EH
Timer counter data
registers 1 and 2
bit0
TCCS
Timer counter control
status register
16-bit output compare register
bit15
bit0
Address : 003928H
00392AH
OCCP0/OCCP1
Compare registers 0 and 1
bit0
bit15
Address : 000058H
OCS1
Compare control status
registers 0 and 1
OCS0
16-bit input capture register
bit0
bit15
Address : 003920H
003922H
Input capture data
registers 0 and 1
IPCP0/IPCP1
bit7
Address : 00004CH
180
bit0
ICS01
Input capture control status
registers 0 and 1
CHAPTER 12 16-BIT I/O TIMER
12.3
16-bit Free-run Timer
The 16-bit free-run timer consists of a 16-bit up counter and a control status register.
The count values are used as the base timer for the output compares and input
captures.
• Four counter clock frequencies are available.
• An interrupt can be generated upon a counter vBlock Diagramalue overflow.
• The counter value can be initialized upon a match with compare register 0, depending
on the mode.
■ Block Diagram of 16-bit Free-run Timer
Figure 12.3-1 Block Diagram of 16-bit Free-run Timer
Internal data bus
Interrupt request
IVF
IVFE
STOP MODE CLR
CLK1
Machine clock
Divider
CLK0
(TCCS)
Comparator 0
16-bit free-run time
Clock
Count value output
T15
to
T00
181
CHAPTER 12 16-BIT I/O TIMER
12.3.1
16-bit Free-run Timer Registers
The data register can read the count value of the 16-bit free-run timer. The counter value
is cleared to "0000H" upon a reset. The timer value can be set by writing a value to this
register. However, ensure that the value is written while the operation is stopped
(STOP=1).
The data register must be accessed by the word access instructions.
■ Data Register (TCDT)
Figure 12.3-2 Data Register (TCDT)
Data register
bit 15
Address : 00006DH
Read/write
Initial value
T15
Read/write
Initial value
13
12
11
10
9
8
T14
T13
T12
T11
T10
T09
T08
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
bit
Address : 00006CH
14
7
6
5
4
3
2
1
0
T07
T06
T05
T04
T03
T02
T01
T00
TCDT
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
The 16-bit free-run timer is initialized upon the following factors:
• Reset
• Clear bit (CLR) of control status register
• A match between compare register 0 and the timer counter value (Setting the mode is required).
182
CHAPTER 12 16-BIT I/O TIMER
12.3.2
Timer Control Status Register
The timer control status register sets the operation mode of the 16-bit free-run timer,
starts and stops the 16-bit free-run timer, and controls interrupts.
■ Timer Control Status Register
Figure 12.3-3 Timer Control Status Register
Timer Control Status Register (TCCS)
7
6
5
4
3
2
1
Reserved
IVF
IVFE
STOP
MODE
CLR
CLK1
CLK0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
bit
Address : 00006EH
0
TCCS
[bit7]Reserved: Reserved bit
Always write "0" to this bit.
[bit6] IVF
This bit is an interrupt request flag of the 16-bit free-run timer.
If the 16-bit free-run timer overflows, or if the counter is cleared by a match with compare register 0,
"1" is set to this bit.
An interrupt is issued if the interrupt request enable bit (bit5: IVFE) is set.
This bit is cleared by writing "0". Writing "1" has no effect.
"1" is always read by a read-modify-write instruction.
0
No interrupt request [initial value]
1
Interrupt request
[bit5] IVFE
IVFE is an interrupt enable bit of the 16-bit free-run timer. While this bit is "1", an interrupt is issued if
"1" is set to the interrupt flag (bit6: IVF).
0
Interrupt disabled [initial value]
1
Interrupt enabled
183
CHAPTER 12 16-BIT I/O TIMER
[bit4] STOP
The STOP bit is used to stop the 16-bit free-run timer.
Writing "1" to this bit stops the timer. Writing "0" starts the timer.
0
Counter enabled (operation) [initial value]
1
Counter disabled (stop)
Note:
The output compare operation stops when the 16-bit free-run timer stops.
[bit3] MODE
The MODE bit is used to set the reset condition of the 16-bit free-run timer.
When "0" is set, the counter value can be initialized by RESET or a clear bit (bit2: CLR).
When "1" is set, the counter value can be initialized by a match with compare register 0 in addition to
RESET and a clear bit (bit2: CLR).
0
Initialization by reset or clear bit [initial value]
1
Initialization by reset, clear bit, or compare register 0
Note:
The clear bit and a match with the compare register initialize the timer when the timer value
changes.
[bit2] CLR
The CLR bit initializes the operating 16-bit free-run timer value to "0000H".
When "1" is set, the counter value is initialized to "0000H". Writing "0" has no effect. "0" is always read
from this bit. The counter value is initialized when the count value changes.
0
No effect [initial value]
1
The counter value is initialized to "0000H".
Note:
To initialize the counter value while the timer is stopped, write "0000H" to the data register.
184
CHAPTER 12 16-BIT I/O TIMER
[bit1, bit0] CLK1, CLK0
CLK1 and CLK0 are used to select the count clock for the 16-bit free-run timer. The clock is updated
immediately after a value is written to these bits. Therefore, ensure that the output compare and input
capture operations are stopped before a value is written to these bits.
CLK1
CLK0
Count clock
φ=16 MHz
φ=8 MHz
φ=4 MHz
φ=2 MHz
0
0
φ/4
0.25 µs
0.5 µs
1 µs
2 µs
0
1
φ/16
1 µs
2 µs
4 µs
8 µs
1
0
φ/64
4 µs
8 µs
16 µs
32 µs
1
1
φ/256
16 µs
32 µs
64 µs
128 µs
φ = Machine clock
185
CHAPTER 12 16-BIT I/O TIMER
12.3.3
16-bit Free-run Timer Operation
The 16-bit free-run timer starts counting from counter value "0000H" after the reset is
released. The counter value is used as the reference time for the 16-bit output compare
and 16-bit input capture operations.
■ 16-bit Free-run Timer Operation
The counter value is cleared in the following conditions:
• When an overflow occurs.
• When a match with the output compare register 0 occurs. (This depends on the mode.)
• When "1" is written to the CLR bit of the TCCS register during operation.
• When "0000H" is written to the TCDC register during stop.
• Reset
An interrupt can be generated when an overflow occurs or when the counter is cleared by a match with the
compare register 0. (Compare match interrupts can be used only in an appropriate mode.)
Figure 12.3-4 Clearing the Counter by an Overflow
Counter value
Overflow
FFFF H
BFFF H
7FFF H
3FFF H
Time
0000 H
Reset
Interrupt
Figure 12.3-5 Clearing the Counter upon a Match with Output Compare Register 0
Counter value
FFFF H
BFFF H
Match
Match
7FFF H
3FFF H
Time
0000 H
Reset
Compare
register value
Interrupt
186
BFFFH
CHAPTER 12 16-BIT I/O TIMER
■ 16-bit Free-run Timer Timing
As shown in Figure 12.3-6 , the 16-bit free-run timer is incremented according to the timing of input clock
(internal or external clock). If an external clock is selected, counting is performed at the rising edge↑.
Figure 12.3-6 Count Timing of 16-bit Free-run Timer
Machine clock (φ)
External clock input
Cuont clock
Counter value
N+1
N
As shown in Figure 12.3-7 , the counter can be cleared by a reset, software clear, or match with compare
register 0. For a reset or software clear, the counter is immediately cleared. For a match with compare
register 0, the counter is cleared synchronously with the count timing.
Figure 12.3-7 16-bit Free-run Timer Clear Timing (Match with the Compare Register 0)
Machine clock φ
N
Compare
register value
Compare match
Counter value
N
0000
187
CHAPTER 12 16-BIT I/O TIMER
12.4
Output Compare
The output compare module consists of two 16-bit compare registers, two compare
output pins, and control register. If the value written to the compare register of this
module matches the 16-bit free-run timer value, the output level of the pin can be
reversed and an interrupt can be issued.
■ Output Compare
• Two compare registers exist that can be used independently. Depending on the setting, the two compare
registers can be used to control pin outputs.
• The initial value for the pin output can be specified.
• An interrupt can be issued upon a match as a result of comparison.
■ Block Diagram of Output Compare
Figure 12.4-1 Block Diagram of Output Compare
16-bit timer counter value (T15 to T00)
T
Compare control
Q
OTE0
OUT0
OTE1
OUT1
Internal data bus
Compare register 0
16-bit timer counter value (T15 to T00)
CMOD
T
Compare control
Q
Compare register 1
ICP1 ICP0 ICE1 ICE0
Controller
Control blocks
188
Compare 1
interrupt
Compare 0
interrupt
CHAPTER 12 16-BIT I/O TIMER
12.4.1
Output Compare Register
These 16-bit compare registers are compared with the 16-bit free-run timer. Since the
initial register values are undefined, set appropriate value before enabling the
operation. These registers must be accessed by the word access instructions. When the
value of the register matches that of the 16-bit free-run timer, a compare signal is
generated and the output compare interrupt flag is set. If output is enabled, the output
level corresponding to the compare register is reversed.
■ Output Compare Register
Figure 12.4-2 Output Compare Register
Compare register (OCCP0 and OCCP1)
14
13
12
11
10
9
8
bit 15
Address : 003929H
C15 C14 C13 C12 C11 C10 C09 C08
00392BH
Read/write
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X)
(X)
(X)
(X)
(X)
(X)
Initial value
(X)
bit
Address : 003928H
00392AH
Read/write
Initial value
7
6
5
4
3
2
1
0
C07
C06
C05
C04
C03
C02
C01
C00
OCCP0, OCCP1
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X)
(X)
(X)
(X)
(X)
(X)
(X)
189
CHAPTER 12 16-BIT I/O TIMER
12.4.2
Control Status Register of Output Compare
The control status register sets the operation mode of output compare, starts and stops
output compare, controls interrupts, and sets the external output pins.
■ Control Status Register of Output Compare
Figure 12.4-3 Control Status Register
Compare control status register (0/1)
bit
15
14
13
Address : 000059H
Read/write
Initial value
(-)
(-)
bit
Address : 000058H
Read/write
Initial value
12
11
10
9
8
CMOD
OTE1
OTE0
OTD1
OTD0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(-)
(-)
(-)
(-)
7
6
5
4
ICP1
ICP0
ICE1
ICE0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
3
(-)
(-)
2
(-)
(-)
OCS1
1
0
CST1
CST0
(R/W)
(0)
(R/W)
(0)
OCS0
[bit15 to bit13]-: Unused bits
[bit12] CMOD
CMOD is used to switch the pin output level reverse mode upon a match while pin output is enabled
(OTE1=1 or OTE0=1).
• When CMOD=0 (initial value), the output level of the pin corresponding to the compare register is
reversed.
- OUT0: The level is reversed upon a match with compare register 0.
- OUT1: The level is reversed upon a match with compare register 1.
• When CMOD=1, the output level is reversed for the compare register 0 in the same manner as for
CMOD=0. The output level of the pin corresponding to compare register 1 (OUT1), however, is
reversed upon a match with compare register 0 or 1. If compare registers 0 and 1 have the same value,
the same operation as with a single compare register is performed.
- OUT0: The level is reversed upon a match with compare register 0.
- OUT1: The level is reversed upon a match with compare register 0 or 1.
[bit11, bit10] OTE1, OTE0
These bits are used to enable the output compare output pins. The initial value for these bits is "0".
190
0
General-purpose port [initial value]
1
Output compare pin output
CHAPTER 12 16-BIT I/O TIMER
Note:
OTE1: Corresponds to output compare 1 (OUT1).
OTE0: Corresponds to output compare 0 (OUT0).
[bit9, bit8] OTD1, OTD0
These bits are used to change the pin output level when the output compare pin output is enabled. The
initial value of the compare pin output is "0". Ensure that the compare operation is stopped before a
value is written. When read, these bits indicate the output compare pin output value.
0
Sets "0" for the compare pin output. [initial value]
1
Sets "1" for the compare pin output.
Note:
OTD1: Corresponds to output compare 1.
OTD0: Corresponds to output compare 0.
[bit7, bit6] ICP1, ICP0
These bits are used as output compare interrupt flags. "1" is set to these bits when the compare register
value matches the 16-bit free-run timer value. While the interrupt request bits (ICE1 and ICE0) are
enabled, an output compare interrupt occurs when the ICP1 and ICP0 bits are set. These bits are cleared
by writing "0".
Writing "1" has no effect. "1" is always read by a read-modify-write instruction.
0
No compare match [initial value]
1
Compare match
Note:
ICP1: Corresponds to output compare 1.
ICP0: Corresponds to output compare 0.
[bit5, bit4] ICE1, ICE0
These bits are used as output compare interrupt enable flags. While the "1" is written to these bits, an
output compare interrupt occurs when an interrupt flag (ICP1 or ICP0) is set.
0
Output compare interrupt disabled [initial value]
1
Output compare interrupt enabled
191
CHAPTER 12 16-BIT I/O TIMER
Note:
ICE1: Corresponds to output compare 1.
ICE0: Corresponds to output compare 0.
[bit3, bit2]-: Unused bits
[bit1, bit0] CST1, CST0
These bits are used to enable the comparison with 16-bit free-run timer.
0
Compare operation disabled [initial value]
1
Compare operation enabled
Ensure that a value is written to the compare register before the compare operation is enabled.
Note:
CST1: Corresponds to output compare 1.
CST0: Corresponds to output compare 0.
Note:
Since output compare is synchronized with the 16-bit free-run timer clock, stopping the 16-bit freerun timer stops compare operation.
192
CHAPTER 12 16-BIT I/O TIMER
12.4.3
16-bit Output Compare Operation
In the 16-bit output compare operation, an interrupt request flag can be set and the
output level can be reversed when the specified compare register value matches the 16bit free-run timer value.
■ Sample of Output Waveform when Compare Registers 0 and 1 are Used (The Initial
Output Value is "0".)
Figure 12.4-4 Sample of Output Waveform when Compare Registers 0 and 1 are Used
Counter value
FFFFH
BFFF H
7FFFH
3FFFH
Time
0000H
Reset
Compare register
0 value
Compare register
1 value
OUT0
BFFFH
7FFFH
OUT1
Compare 0
interrupt
Compare 1
interrupt
Using compare registers 0 and 1, the output level can be changed (when CMOD=0).
193
CHAPTER 12 16-BIT I/O TIMER
■ Sample of a Output Waveform with Two Compare Registers (The Initial Output Value is
"0".)
Figure 12.4-5 Sample of a Output Waveform with Two Compare Registers (The Initial Output Value is "0".)
Counter value
FFFFH
BFFF H
7FFFH
3FFFH
0000H
Time
Reset
BFFFH
Compare register
0 value
Compare register
1 value
OUT0
7FFFH
Corresponds to compare 0
Corresponds to
compare 0 and 1
OUT1
Compare 0
interrupt
Compare 1
interrupt
The output level can be changed using two compare registers (when CMOD=1).
■ Output Compare Timing
In output compare operation, a compare match signal is generated when the free-run timer value matches
the specified compare register value. The output value can be reversed and an interrupt can be issued. The
output reverse timing upon a compare match is synchronized with the counter count timing.
When the compare register is updated, comparison with the counter value is not performed.
As shown in Figure 12.4-6 , when the compare register is updated, comparison with the counter value is not
performed.
Figure 12.4-6 Compare Operation upon Update of Compare Register
N
Counter value
N+1
N+2
N+3
No match signal is generated.
Compare register
0 value
Compare register
0 write
M
Compare register
1 value
Compare register
1 write
M
N+1
N+3
Compare 0 stop
Compare 1 stop
Figure 12.4-7 shows the output compare interrupt timing, and Figure 12.4-8 shows the output compare
output pin change timing.
194
CHAPTER 12 16-BIT I/O TIMER
Figure 12.4-7 Interrupt Timing
Machine clock φ
N
Counter value
N+1
N
Compare register
value
Compare match
Interrupt
Figure 12.4-8 Output Pin Change Timing
Counter value
Compare register
value
N
N+1
N
N+1
N
Compare match
signal
Pin output
195
CHAPTER 12 16-BIT I/O TIMER
12.5
Input Capture
Input capture detects a rising or falling edge or both edges of an external input signal
and stores a 16-bit free-run timer value at that time in a register. In addition, input
capture can generate an interrupt upon detection of an edge. Input capture consists of
an input capture data register and a control register.
■ Input Capture
Each input capture has a corresponding external input pin.
● The valid edge of an external input can be selected from the following three types:
• Rising edge (
)
• Falling edge (
)
• Both edges (
)
● An interrupt can be generated upon detection of a valid edge of an external input.
196
CHAPTER 12 16-BIT I/O TIMER
■ Block Diagram of Input Capture
Figure 12.5-1 Block Diagram of Input Capture
Internal data bus
IN0
Edge detection
Capture data register 0
EG11 EG10 EG01 EG00
16-bit timer counter value (T15 to T00)
Edge detection
Capture data register 1
ICP1
ICP0
ICE1
IN1
ICE0
Interrupt
Interrupt
197
CHAPTER 12 16-BIT I/O TIMER
12.5.1
Input Capture Register
Input capture has the two registers listed. These registers store a value from the 16-bit
timer when a valid edge of the corresponding external pin input waveform is detected.
(The registers must be accessed in word mode. No values can be written to the
registers.)
■ Input Capture Data Register
Figure 12.5-2 Input Capture Data Register
Input capture data register 0/1
15
bit
Address : 003919H
00391BH
Read/write
14
13
12
11
10
9
8
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08
Initial value
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
bit
Address : 003918H
00391AH
Read/write
7
6
5
4
3
2
1
0
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00
Initial value
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
IPCP0/IPCP1
■ Input Capture Control Status Register
Figure 12.5-3 Input Capture Control Status Register
Input capture control status register 0/1
bit
7
6
5
4
3
2
1
0
Address : 00004CH
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
Read/write
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Initial value
ICS01
[bit7, bit6] ICP1, ICP0
These bits are used as input capture interrupt flags. "1" is set to this bit upon detection of a valid edge of
an external input pin. While the interrupt enable bits (ICE0 and ICE1) are set, an interrupt can be
generated upon detection of a valid edge.
These bits are cleared by writing "0". Writing "1" has no effect. "1" is always read by a read-modifywrite instruction.
198
0
No valid edge detection [initial value]
1
Valid edge detection
CHAPTER 12 16-BIT I/O TIMER
Note:
ICP0: Corresponds to input capture 0.
ICP1: Corresponds to input capture 1.
[bit5, bit4] ICE1, ICE0
These bits are used to enable input capture interrupts. While these bits are "1", an input capture interrupt
is generated when the interrupt flag (ICP0 or ICP1) is set.
0
Interrupt disabled [initial value]
1
Interrupt enabled
Note:
ICE0: Corresponds to input capture 0.
ICE1: Corresponds to input capture 1.
[bit3 to bit0] EG11, EG10, EG01, EG00
These bits are used to specify the valid edge polarity of the external inputs. These bits are also used to
enable input capture operation.
EG11
EG01
EG10
EG00
0
0
No edge detection (stop) [initial value]
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edge detection
Edge detection polarity
Note:
EG01 and EG00: Correspond to input capture 0.
EG11 and EG10: Correspond to input capture 1.
199
CHAPTER 12 16-BIT I/O TIMER
12.5.2
16-bit Input Capture Operation
In 16-bit input capture operation, an interrupt can be generated upon detection of at the
specified edge, fetching the 16-bit free-run timer value and writing it to the capture
register.
■ Sample of Input Capture Fetch Timing
• Capture 0: Rising edge
• Capture 1: Falling edge
• Capture example: Both edges
Figure 12.5-4 Sample of Input Capture Fetch Timing
Counter value
FFFF H
BFFF H
7FFF H
3FFF H
0000 H
Time
Reset
IN0
IN1
IN example
Capture 0
Capture 1
Capture
example
Capture 0
interrupt
Capture 1
interrupt
Capture
interrupt
200
Undefined
3FFFH
Undefined
Undefined
7FFFH
BFFFH
Capture 0= Rising edge
Capture 1= Falling edge
Capture example= Both edges (as an example)
3FFFH
CHAPTER 12 16-BIT I/O TIMER
■ Input Capture Input Timing
Figure 12.5-5 Capture timing for input signals
Machine clock
φ
Counter value
Input capture
input
N
N+1
Valid edge
Capture signal
Capture register
N+1
Interrupt
201
CHAPTER 12 16-BIT I/O TIMER
202
CHAPTER 13
16-BIT RELOAD TIMER
(WITH EVENT COUNT
FUNCTION)
This chapter explains the functions and operations of
the 16-bit reload timer (with the event count function).
13.1 Outline of 16-Bit Reload Timer (with Event Count Function)
13.2 16-Bit Reload Timer (with Event Count Function)
13.3 Internal Clock and External Clock Operations of 16-bit Reload
Timer
13.4 Underflow Operation of 16-bit Reload Timer
13.5 Output Pin Functions of 16-bit Reload Timer
13.6 Counter Operation State
203
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.1
Outline of 16-Bit Reload Timer (with Event Count Function)
The 16-bit reload timer consists of a 16-bit down-counter, a 16-bit reload register, one
input pin (TIN) and one output pin (TOT), and a control register. The input clock can be
selected from one external clock and three types of internal clock.
■ Outline of 16-bit Reload Timer (with Event Count Function)
The output pin (TOT) outputs a toggle output waveform in reload mode and outputs a square waveform
indicating counting in one-shot mode. The input pin (TIN) is used for event input in event count mode, and
can be used for trigger input or gate input in internal clock mode.
MB90440G series products have two 16-bit reload timers.
■ Intelligent I/O Service (EI2OS) Function and Interrupts
The timer includes a circuit that supports EI2OS. The timer can activate EI2OS when an underflow occurs.
EI2OS can be used with both timers on this product.
■ Block Diagram of 16-bit Reload Timer
Figure 13.1-1 shows a block diagram of the 16-bit reload timer.
Figure 13.1-1 Block Diagram of 16-bit Reload Timer
16
16-bit reload register
8
Reload
Internal data bus
RELD
16-bit down-counter
16
UF
OUTE
OUTL
2
INTE
OUT
CTL.
GATE
UF
CSL1
Clock selector
CNTE
CSL0
TRG
Re-trigger
2
EXCK
2
1
2
3
5
2
Prescaler
clear
Output enable
Port (TOT)
MOD2
MOD1
Machine clock
3
Clear
EI2OS CLR
Port (TIN)
IN CTL
3
204
IRQ
MOD0
UART baud rate (ch.0 only)
A/D converter (ch.1 only)
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
■ 16-bit Reload Timer
MB90440G series has two 16-bit reload timers. The input pin name (TIN) and output pin name (TOT) in
the timers are shown below.
Input pin name(TIN)
Output pin name(TOT)
Timer 1
TIN0
TOT0
Timer 2
TIN1
TOT1
205
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.2
16-Bit Reload Timer (with Event Count Function)
The 16-bit reload timer has the following two types of registers:
• Timer control register (TMCSR)
• 16-bit timer register (TMR)/16-bit reload register (TMRLR)
■ 16-bit Reload Timer Register
Figure 13.2-1 16-bit Reload Timer Register
Timer control status register (upper)
Address:ch.0 000051H
ch.1 000055 H
⎫
⎬
⎭
Read/write
Initial value
15
bit
⎫
⎬
⎭
Read/write
Initial value
16-bit timer register (upper)/
16-bit reload register (upper)
Address: ch.0 000053H
ch.1 000057H
11
10
9
8
—
—
—
CSL1
CSL0
MOD2
MOD1
(—)
(—)
(—)
(—)
(R/W)
(R/W)
(R/W)
(R/W)
(—)
(—)
(—)
(—)
(0)
(0)
(0)
(0)
7
6
5
4
3
2
1
OUTE
OUTL
RELD
INTE
UF
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
10
9
bit
MOD0
(R/W)
(0)
CNTE
0
TMCSR
TRG
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
bit 15
14
13
12
11
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
6
5
4
3
2
1
(R/W)
(X)
(R/W)
(X)
bit
(R/W)
(0)
8
7
0
⎫
⎬
⎭
Read/write
Initial value
206
12
⎫
⎬
⎭
Read/write
Initial value
16-bit timer register (lower)/
16-bit reload register (lower)
Address:ch.0 000052H
ch.1
ch1 000056
00003EHH
13
—
Timer control status register (lower)
Address: ch.0 000050 H
ch.1 000054 H
14
TMR/
TMRLR
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.2.1
Timer Control Status Register (TMCSR)
Controls the operation mode and interrupts for the 16-bit timer. Only modify bits other
than UF, CNTE, and TRG when CNTE = 0.
■ Timer Control Status Register (TMCSR)
Figure 13.2-2 Timer Control Status Register (TMCSR)
Timer control status register (upper)
Address: ch.0 000051H
ch1 000055
00003DHH
ch.1
⎫
⎬
⎭
Read/write
Initial value
Timer control status register (lower)
Address: ch.0 000050 H
ch1 000054
00003CHH
ch.1
⎫
⎬
⎭
Read/write
Initial value
bit 15
14
13
12
11
10
9
8
CSL0
MOD2
MOD1
—
—
—
—
CSL1
(—)
(—)
(—)
(—)
(R/W)
(R/W)
(R/W)
(R/W)
(—)
(—)
(—)
(—)
(0)
(0)
(0)
(0)
6
5
4
INTE
(R/W)
(0)
7
bit
MOD0
OUTE
OUTL
RELD
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
3
2
1
UF
CNTE
TRG
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
0
TMCSR
[bit11, bit10] CSL1, CSL0 (Clock Select 1, 0)
The count clock select bits. Table 13.2-1 lists the selected clock sources.
Table 13.2-1 Clock Sources for CSL Bit Settings
CSL1
CSL0
Clock Source (Machine cycle φ = 16 MHz)
0
0
φ/21 (0.125 µs)
0
1
φ/23 (0.5 µs)
1
0
φ/25 (2.0 µs)
1
1
External event count mode
[bit9 to bit7] MOD2 to MOD0
These bits set the operation mode and I/O pin functions.
The MOD2 bit selects the I/O functions. When MOD2 = 0, the input pin functions as a trigger input. In
this case, the reload register contents is loaded to the counter when an active edge is input to the input
pin and count operation proceeds. When MOD2 =1, the timer operates in gate counter mode and the
input pin functions as a gate input. In this mode, the counter only counts while an active level is input to
the input pin.
207
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
The MOD1 and MOD0 bits set the pin functions for each mode. Table 13.2-2 and Table 13.2-3 list the
MOD2 to MOD0 bit settings.
Table 13.2-2 MOD2 to MOD0 Bit Settings (1)
MOD2
MOD1
MOD0
Input Pin Function
Active Edge or Level
0
0
0
Trigger disabled
-
0
0
1
0
1
0
0
1
1
1
×
0
Rising edge
Trigger input
Falling edge
Both edges
"L" level
Gate input
1
×
1
"H" level
• Internal clock mode (CSL0, CSL1=00B, 01B, or 10B)
• Bits marked as x in the table can be set to any value.
Table 13.2-3 MOD2 to MOD0 Bit Settings (2)
MOD2
MOD1
MOD0
Input Pin Function
Active Edge or Level
0
0
-
-
0
1
1
0
1
1
Rising edge
×
Trigger input
Falling edge
Both edges
• Event counter mode (CSL0, CSL1=11B)
• Bits marked as × in the table can be set to any value.
[bit6] OUTE
Output enable bit. The TOT pin functions as a general-purpose port when this bit is "0" and as the timer
output pin when this bit is "1". In reload mode, the output waveform toggles. In one-shot mode, TOT
outputs a square waveform that indicates that counting is in progress.
208
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
[bit5] OUTL
This bit sets the output level for the TOT pin.
Table 13.2-4 OUTE, RELD, and OUTL Settings
OUTE
RELD
OUTL
Output Waveform
0
×
×
General-purpose port
1
0
0
Output an "H" level square waveform during counting.
1
0
1
Output an "L" level square waveform during counting.
1
1
0
Toggle output. Starts with "L" level output.
1
1
1
Toggle output. Starts with "H" level output.
[bit4] RELD (Reload)
This bit enables reload operations. When RELD is "1", the timer operates in reload mode. In this mode,
the timer loads the reload register contents into the counter and continues counting whenever an
underflow occurs (when the counter value changes from "0000H" to "FFFFH"). When RELD is "0", the
timer operates in one-shot mode. In this mode, the count operation stops when an underflow occurs due
to the counter value changing from "0000H" to "FFFFH".
[bit3] INTE (Interrupt enable)
Timer interrupt request enable bit. When INTE is "1", an interrupt request is generated when the UF bit
changes to "1". When INTE is "0", no interrupt request is generated, even when the UF bit changes to
"1".
[bit2] UF (Underflow)
Timer interrupt request flag. UF is set to "1" when an underflow occurs (when the counter value
changes from "0000H" to "FFFFH"). Cleared by writing "0" or by the intelligent I/O service. Writing
"1" to this bit has no meaning. Read as "1" by read-modify-write instructions.
[bit1] CNTE (Count enable)
Timer count enable bit. Writing "1" to CNTE sets the timer to wait for a trigger. Writing "0" stops count
operation.
[bit0] TRG (Trigger)
Software trigger bit. Writing "1" to TRG applies a software trigger, causing the timer to load the reload
register contents to the counter and start counting. Writing "0" has no meaning. Reading always returns
"0". Applying a trigger using this register is only valid when CNTE = 1. Writing "1" has no effect if
CNTE =0.
209
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.2.2
Register Layout of 16-bit Timer Register (TMR)/16-bit
Reload Register (TMRLR)
TMR contents (for reading)
Reading this register reads the count value of the 16-bit timer. The initial value is
undefined. Always read this register using the word access instructions.
TMRLR contents (for writing)
The 16-bit reload register holds the initial count value. The initial value is undefined.
Always write to this register using the word access instructions.
■ 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR)
Figure 13.2-3 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR)
16-bit timer register (upper)/
16-bit reload register (upper)
Address: ch.0 000053H
ch1 000057
00003DHH
ch.1
bit 15
Read/write
Initial value
16-bit timer register (lower)/
16-bit reload register (lower)
Address: ch.0 000052 H
ch1 000056
00003CHH
ch.1
13
12
11
10
9
8
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
3
2
1
bit
7
6
5
4
0
⎫
⎬
⎭
Read/write
Initial value
210
14
⎫
⎬
⎭
TMR/
TMRLR
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
(X)
(X)
(R/W)
(X)
(R/W)
(R/W)
(X)
(X)
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.3
Internal Clock and External Clock Operations of 16-bit
Reload Timer
The machine clock divided by 21, 23, or 25 can be selected as the clock sources for
operating the timer from an internal divide clock. The external input pin can be selected
as either a trigger input or gate input by a register setting.
If an external clock is selected, the TIN pin functions as an external event input pin to
count the number of valid edges set in the register.
■ Internal Clock Operation of 16-bit Reload Timer
Writing "1" to both the CNTE and TRG bits in the control register enables and starts counting at one time.
Using the TRG bit as a trigger input is always available when the timer is enabled (CNTE = 1), regardless
of the operation mode.
Figure 13.3-1 shows counter activation and counter operation. A time period T (T: machine cycle) is
required from the counter start trigger being input until the reload register data is loaded into counter.
Figure 13.3-1 Activation and Operation of 16-bit Reload Timer Counter
Count clock
Counter
Reload data
-1
-1
-1
Data load
CNTE (bit)
TRG (bit)
T
211
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
■ Input Pin Functions of 16-bit Reload Timer (in Internal Clock Mode)
The TIN pin can be used as either a trigger input or a gate input when an internal clock is selected as the
clock source. When used as a trigger input, input of an active edge causes the timer to load the reload
register contents to the counter and then start count operation after clearing the internal prescaler. Input a
pulse width of at least 2T (T is the machine cycle) to TIN.
Figure 13.3-2 shows the operation of trigger input.
Figure 13.3-2 Trigger Input Operation of 16-bit Reload Timer
Count clock
Rising edge detected
TIN pin
Prescaler clear
Counter
0000H
Reload data
-1
-1
-1
Load
2T to
2.5T
When used as a gate input, the counter only counts while the active level specified by the MOD0 bit of the
control register is input to the TIN pin. In this case, the count clock continues to operate unless stopped.
The software trigger can be used in gate mode, regardless of the gate level. Input a pulse width of at least
2T (T is the machine cycle) to the TIN pin. Figure 13.3-3 shows the operation of gate input.
Figure 13.3-3 Gate Input Operation of 16-bit Reload Timer
Count clock
When MOD0 = 1 (Count when "H" is input)
TIN pin
-1
Counter
-1
-1
■ External Event Counter
The TIN pin functions as an external event input pin when an external clock is selected. The counter counts
on the active edge specified in the register. Input a pulse width of at least 4T (T is the machine cycle) to the
TIN pin.
212
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.4
Underflow Operation of 16-bit Reload Timer
An underflow is defined for this timer as the time when the counter value changes from
"0000H" to "FFFFH". Therefore, an underflow occurs after (reload register setting + 1)
counts.
■ Underflow Operation of 16-bit Reload Timer
If the RELD bit in the control register is "1" when the underflow occurs, the contents of the reload register
is loaded into the counter and counting continues. When RELD is "0", counting stops with the counter at
FFFFH.
The UF bit in the control register is set when the underflow occurs. If the INTE bit is "1" at this time, an
interrupt request is generated.
Figure 13.4-1 and Figure 13.4-2 show the operation when an underflow occurs.
Figure 13.4-1 Underflow Operation of 16-bit Reload Timer [RELD=1]
Count clock
Counter
0000H
Reload data
-1
-1
-1
Data load
Underflow set
Figure 13.4-2 Underflow Operation of 16-bit Reload Timer [RELD=0]
Count clock
Counter
0000H
FFFFH
Underflow set
213
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.5
Output Pin Functions of 16-bit Reload Timer
In reload mode, the TOT pin performs toggle output (inverts at each underflow). In oneshot mode, the TOT pin functions as a pulse output that outputs a particular level while
the count is in progress.
■ Output Pin Functions of 16-bit Reload Timer
The OUTL bit of the control register sets the output polarity. When OUTL = 0, the initial value for toggle
output is "0" and the one-shot pulse output is "1" while the count is in progress. The output waveforms are
opposite when OUTL =1.
Figure 13.5-1 and Figure 13.5-2 show the output pin functions.
Figure 13.5-1 Output Pin Function of 16-bit Reload Timer (RELD=1, OUTL=0)
Count start
Underflow
TOT
General-purpose port
Level is opposite
when OUTL = 1.
CNTE
Trigger
Figure 13.5-2 Output Pin Function of 16-bit Reload Timer (RELD=0, OUTL=0)
Underflow
TOT
Level is opposite
when OUTL = 1.
General-purpose port
CNTE
Trigger
Waiting for a trigger
214
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.6
Counter Operation State
The counter state is determined by the CNTE bit in the control register and the internal
WAIT signal. Available states are: CNTE = 0 and WAIT = 1 (STOP state), CNTE = 1 and
WAIT = 1 (WAIT state for trigger), and CNTE = 1 and WAIT = 0 (RUN state).
■ Counter Operation State
Figure 13.6-1 shows the transitions between each state.
Figure 13.6-1 Counter State Transitions
Reset
State transitions by hardware
STOP
CNTE=0, WAIT=1
State transitions by register access
TIN pin: Input disabled
TOT pin: General-purpose port
Counter: Retains the value while
counting stopped.
Value undefined after reset.
CNTE=0
CNTE=0
CNTE=1
TRG=1
CNTE=1
TRG=0
WAIT
RUN
CNTE=1, WAIT=1
CNTE=1, WAIT=0
TIN pin: Only trigger input enabled
TIN pin: Functions as TIN pin
TOT pin: Initial value output
TOT pin: Functions as TOT pin
RELD·UF
Counter: Retains the value while
counting stopped.
Value undefined after reset until
load.
TRG=1
Counter: Running
TRG=1
RELD·UF
Start from TIN
LOAD
CNTE=1, WAIT= 0
Load complete
Load contents of the reload
register to the counter.
215
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
216
CHAPTER 14
8/16-BIT PPG
This chapter explains the functions and operation of the
8/16-bit PPG.
14.1 Outline of 8/16-bit PPG
14.2 Block Diagram of 8/16-bit PPG
14.3 8/16-bit PPG Registers
14.4 Operations of 8/16-bit PPG
14.5 Selecting a Count Clock for 8/16-bit PPG
14.6 Controlling Pin Output of 8/16-bit PPG Pulses
14.7 8/16-bit PPG Interrupts
14.8 Initial Values of 8/16-bit PPG Hardware
217
CHAPTER 14 8/16-BIT PPG
14.1
Outline of 8/16-bit PPG
The 8/16-bit Programable Pulse Generator (PPG) consists of two eight-bit down
counters, four eight-bit reload registers, one 16-bit control register, two external pulse
output signals, and two interrupt outputs. The following functions are implemented:
■ Function of 8/16-bit PPG
● 8-bit PPG output, 2-channel independent operation mode:
Two independent channels of PPG output operation are implemented.
● 16-bit PPG output operation mode:
One channel of 16-bit PPG output operation is implemented.
● 8+8-bit PPG output operation mode:
8-bit PPG output operation is implemented at specifies intervals, using channel 0 output as channel 1 clock
input.
● PPG output operation:
Pulse waves are output at specified intervals and duty ratio. With an external circuit, this module can be
used as a D/A converter.
Note:
The MB90440G series contains four PPG´s. The following sections only describe the functionality of
the PPG 0/1. The remaining PPG´s have the identical function and the register addresses could be
found in the I/O map. The channel 0 PPG output signal is not connected to any external pin.
218
CHAPTER 14 8/16-BIT PPG
14.2
Block Diagram of 8/16-bit PPG
Figure 14.2-1 shows a block diagram of the 8/16-bit PPG (ch.0). Figure 14.2-2 shows a
block diagram of the 8/16-bit PPG (ch.1).
■ Block Diagram of 8/16-bit PPG
Figure 14.2-1 Block Diagram of 8-bit PPG ch.0
PPG00 output enable
PPG00
Peripheral clock 16-division
Peripheral clock 8-division
Peripheral clock 4-division
Peripheral clock 2-division
Peripheral clock
In MB90440G Series, this signal is not
connected to any external pin.
PPG0
Output latch
Invert
Clear
PEN0
Count clock
selection
Time-base counter output
512-division of main clock
L/H selection
S
RQ
PCNT
(down counter)
In MB90440G Series, this IRQ signal
merged with the Channel 1 IRQ signal
by OR logic.
IRQ
Reload
ch.1-borrow
L/H selector
PRLL0
PRLBH0
PIE0
PRLH0
PUF0
L data bus
H data bus
PPGC0
(Operation mode control)
219
CHAPTER 14 8/16-BIT PPG
Figure 14.2-2 Block Diagram of 8-bit PPG ch.1
PPG10 output enable
PPG10
Peripheral clock 16-division
Peripheral clock 8-division
Peripheral clock 4-division
Peripheral clock 2-division
Peripheral clock
In MB90440G Series this pin is connected to
the "PPG0" external pin.
PPG1
Output latch
Invert
Count clock
selection
Clear
PEN1
In MB90440G Series, this IRQ signal
merged with the Channel 0 IRQ signal
by OR logic.
ch.0 borrow
S
RQ
PCNT
(down counter)
Time-base counter output
512-division of main clock
IRQ
Reload
L/H selection
L/H selector
PRLL1
PRLBH1
PIE
PRLH1
PUF
L data bus
H data bus
PPGC1
(Operation mode control)
Figure 14.2-3 Relationship between PPG Modules and External pins
PPG 0/1
PPG0
PPG 2/3
PPG1
PPG 4/5
PPG2
PPG 6/7
PPG3
External pin
220
CHAPTER 14 8/16-BIT PPG
14.3
8/16-bit PPG Registers
The 8/16-bit PPG has the following five types of registers:
• PPG0 operation mode control register
• PPG1 operation mode control register
• PPG0 and PPG1 clock selection register
• Reload register H
• Reload register L
■ 8/16-bit PPG Registers
Figure 14.3-1 8/16 bit PPG Registers
PPG0 operation mode control register
bit
Address: ch.0 000038H
7
6
5
PEN0
PE00
4
3
2
PIE0
PUF0
1
0
Reserved
PPGC0
(R/W)
(0)
Read/write
Initial value
PPG1 operation mode control register
bit 15
Address: ch.0 000039H
PEN1
Read/write
Initial value
(-)
(-)
(R/W) (R/W) (R/W)
(0)
(0)
(0)
14
(-)
(-)
(-)
(-)
(W)
(1)
13
12
11
10
9
8
PE10
PIE1
PUF1
MD1
MD0
Reserved
PPGC1
(R/W)
(0)
(-)
(-)
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(W)
(1)
PPG0/1 clock selection register
bit
7
6
5
4
3
2
1
0
(-)
(-)
(-)
(-)
Address: ch.0, 1 003AH
PCS2
Read/write
Initial value
PCS1 PCS0 PCM2 PCM1 PCM0
PPG01
(R/W)
(0)
(R/W)
(0)
(R/W) (R/W)
(0)
(0)
(R/W) (R/W)
(0)
(0)
Reload register H
bit
1 5
1 4
1 3
1 2
1 1
1 0
9
8
Address: ch.0 003901H
ch.1 003903H
Read/write
Initial value
Reload register L
PRLH0/1
(R/W) (R/W) (R/W) (R/W) (R/W)
(X)(X)
(X)
(X)
(X)
(R/W) (R/W)
(X)
(X)
(R/W)
(X)
bit
3
1
7
6
5
4
2
Address: ch.0 003900H
ch.1 003902H
Read/write
Initial value
0
PRLL0/1
(R/W)(R/W)
(X)(X)
(R/W) (R/W) (R/W)
(X)
(X)
(X)
(R/W) (R/W)
(X)
(X)
(R/W)
(X)
221
CHAPTER 14 8/16-BIT PPG
14.3.1
PPG0 Operation Mode Control Register (PPGC0)
The operation mode control register (PPGC0) is a 4-bit control register that selects the
operation mode of the block, controls pin outputs, selects a count clock, and controls
triggers.
■ PPG0 Operation Mode Control Register (PPGC0)
Figure 14.3-2 PPG0 Operation Mode Control Register (PPGC0)
PPG0 operation mode control register
bit 7
Address: ch.0, 000038H
PEN0
Read/write
Initial value
(R/W)
(0)
6
5
4
3
2
1
-
PE00
PIE0
PUF0
-
-
(-)
(-)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(-)
(-)
(-)
(-)
[bit7] PEN0 (PPG enable): Operation enable bit
This bit enables PPG count operation.
PEN0
Operation
0
Stop ("L" level output maintained)
1
PPG operation enabled
Setting this bit to "1" enables the counter operation.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit5] PE00 (PPG output enable 00): PPG00 pin output enable bit
This bit controls the PPG00 pulse output external pin as described below.
PE00
Operation
0
General-purpose port pin (pulse output disabled)
1
PPG00 = pulse output pin (pulse output enabled)
This bit is initialized to "0" upon a reset. This bit is readable and writable.
For MB90440G Series, this bit should always be set to "0".
222
0
Reserved
(W)
(1)
PPGC0
CHAPTER 14 8/16-BIT PPG
[bit4] PIE0 (PPG interrupt enable): PPG interrupt enable bit
This bit controls PPG interrupt as described below.
PIE0
Operation
0
Interrupt disabled
1
Interrupt enabled
While this bit is "1", an interrupt request is issued as soon as PUF0 is set to "1". No interrupt request is
issued while this bit is set to "0".
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit3] PUF0 (PPG underflow flag): PPG counter underflow bit
This bit indicates the PPG counter underflow as described below.
PUF0
Operation
0
PPG counter underflow is not detected.
1
PPG counter underflow is detected.
In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" when an
underflow occurs as a result of the ch.0 counter value becoming from 00H to FFH. In 16-bit PPG mode,
this bit is set to "1" when an underflow occurs as a result of the Channel 0 and 1 counter value
becoming from "0000H" to "FFFFH". To set this bit to "0", write "0". Writing "1" to this bit has not
effect. Upon a read operation during a read-modify-write instruction, "1" is read.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit0] Reserved: Reserved bit
This is a reserved bit. When setting PPGC0, always set this bit to "1".
The value read from this bit is always "1".
223
CHAPTER 14 8/16-BIT PPG
14.3.2
PPG1 Operation Mode Control Register (PPGC1)
The PPG1 operation mode control register (PPGC1) is a 6-bit control register that
selects the operation mode of the block, controls pin outputs, selects a count clock,
and controls triggers.
■ PPG1 Operation Mode Control Register (PPGC1)
Figure 14.3-3 PPG1 Operation Mode Control Register (PPGC1)
PPG1 operation mode control register
bit
Address: ch.1 000039H
Read/write
Initial value
1 5
1 4
1 3
1 2
PEN1
-
PE10
PIE1
(R/W)
(0)
(-)
(-)
(R/W)
(0)
(R/W)
(0)
1 1
1 0
PUF1
(R/W)
(0)
MD1
(R/W)
(0)
9
MD0
(R/W)
(0)
[bit15] PEN1 (PPG enable): Operation enable bit
This bit enables the counter operation of the PPG.
PEN1
Operation
0
Stop ("L" level output maintained)
1
PPG operation enabled
Setting this bit to "1" enables the counter operation.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit13] PE10 (PPG output enable 10): PPG10 pin output enable bit
This bit controls the PPG10 pulse output external pin as described below.
PE10
Operation
0
General-purpose port pin (pulse output disabled)
1
PPG10 = pulse output pin (pulse output enabled)
This bit is initialized to "0" upon a reset. This bit is readable and writable.
For MB90440G Series, the pulse signal is output to the "PPG0" external pin.
224
8
Reserved
(W)
(1)
PPGC1
CHAPTER 14 8/16-BIT PPG
[bit12] PIE1 (PPG interrupt enable): PPG interrupt enable bit
This bit controls PPG interrupt as described below.
PIE1
Operation
0
Interrupt disabled
1
Interrupt enabled
While this bit is "1", an interrupt request is issued as soon as PUF1 is set to "1". No interrupt request is
issued while this bit is set to "0".
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit11] PUF1 (PPG underflow flag): PPG counter underflow bit
This bit indicates the PPG counter underflow as described below.
PUF1
Operation
0
PPG counter underflow is not detected.
1
PPG counter underflow is detected.
In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" when an
underflow occurs as a result of the Channel 1 counter value becoming from "00H" to "FFH". In 16-bit
PPG mode, this bit is set to "1" when an underflow occurs as a result of the Channel 0 and 1 counter
value becoming from "0000H" to "FFFFH". To set this bit to "0", write "0". Writing "1" to this bit has
not effect. Upon a read operation during a read-modify-write instruction, "1" is read.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit10, bit9] MD1, MD0 (PPG count mode): Operation mode selection bit
These bits selects the PPG timer operation mode as described below.
MD1
MD0
Operation mode
0
0
8-bit PPG 2ch independent mode
0
1
8-bit prescaler + 8-bit PPG 1ch mode
1
0
Reserved (setting prohibited)
1
1
16-bit PPG 1ch mode
These bits are initialized to "00B" upon a reset. These bits are readable and writable.
Note:
Do not set "10" in MD1 and MD0 bits.
To write "01" to MD1 and MD0 bits, ensure that "01" is not written to the PEN0 bit of PPGC0 or
PEN1 bit of PPGC1. Write "11" or "00" in both the PEN0 and PEN1 bits simultaneously.
To write "11" to MD1 and MD0 bits, update PPGC0 and PPGC1 by word transfer and write "11" or
"00" to both the PEN0 and PEN1 bits simultaneously.
225
CHAPTER 14 8/16-BIT PPG
[bit8] Reserved : Reserved bit
When setting PPGC1, always write "1" to this bit.
The value read from this bit is always "1".
226
CHAPTER 14 8/16-BIT PPG
14.3.3
PPG0/1 Clock Selection Register (PPG01)
The PPG0/1 clock selection register (PPG01) is an 8-bit control register that controls the
PPG operation clock.
■ PPG0/1 Clock Selection Register (PPG01)
Figure 14.3-4 PPG0/1 Clock Selection Register (PPG01)
PPG0/1 Clock Selection register
Address: ch.0/1 003AH
Read/write
Initial value
bit
7
6
5
4
PCS2
PCS1
PCS0
PCM2
PCM1
PCM0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
3
2
1
0
PPG01
(-)
(-)
(-)
(-)
[bit7 to bit5] PCS2 to PCS0 (PPG count select): Count clock selection bit
These bits select the operation clock for the down counter of Channel 1 as described below.
PCS2
PCS1
PCS0
Operation mode
0
0
0
Peripheral clock (62.5 ns machine clock, 16 MHz)
0
0
1
Peripheral clock/2 (125 ns machine clock, 16 MHz)
0
1
0
Peripheral clock/4 (250 ns machine clock, 16 MHz)
0
1
1
Peripheral clock/8 (500 ns machine clock, 16 MHz)
1
0
0
Peripheral clock/16 (1 µs machine clock, 16 MHz)
1
0
1
Clock input from the time-base timer (128 µs, 4 MHz source oscillation)
These bits are initialized to "000B" upon a reset. These bits are readable and writable.
Note:
In 8-bit prescaler + 8-bit PPG mode or in 16-bit PPG mode, ch.1 PPG operates in response to a
counter clock from ch.0. Therefore, the setting in these bits has no effect.
227
CHAPTER 14 8/16-BIT PPG
[bit4 to bit2] PCM2 to PCM0 (PPG count mode): Count clock selection bit
These bits select the operation clock for the down counter of Channel 0 as described below.
PCM2
PCM1
PCM0
Operation mode
0
0
0
Peripheral clock (62.5 ns machine clock, 16 MHz)
0
0
1
Peripheral clock/2 (125 ns machine clock, 16 MHz)
0
1
0
Peripheral clock/4 (250 ns machine clock, 16 MHz)
0
1
1
Peripheral clock/8 (500 ns machine clock, 16 MHz)
1
0
0
Peripheral clock/16 (1 µs machine clock, 16 MHz)
1
0
1
Clock input from the time-base timer (128 µs, 4 MHz source
oscillation)
These bits are initialized to "000B" upon a reset. These bits are readable and writable.
228
CHAPTER 14 8/16-BIT PPG
14.3.4
Reload Register (PRLL/PRLH)
The reload registers (PRLL and PRLH) are 8-bit registers that store reload values for the
PCNT down counters. The PRLL and PRLH registers are readable and writable.
■ Reload Register (PRLL/PRLH)
Figure 14.3-5 Reload Register (PRLL/PRLH)
Reload register H
Address: ch.0 003901H
ch.1 003903H
Read/write
Initial value
Reload register L
Address: ch.0 003900H
ch.1 003902H
Read/write
Initial value
bit
15
14
13
12
11
10
9
8
PRLH0/PRLH1
(R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
bit
7
6
5
4
(R/W) (R/W)
(X)
(X)
(R/W)
(X)
3
1
2
0
PRLL0/PRLL1
(R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
Register name
(R/W) (R/W)
(X)
(X)
(R/W)
(X)
Function
PRLL
Holds the L side reload value.
PRLH
Holds the H side reload value.
Note:
In 8-bit prescaler + 8-bit PPG mode, different values in PRLL and PRLH of Channel 0 may cause the
PPG waveform of ch.1 to vary in each cycle. Write the same value to PRLL and PRLH of ch.0.
229
CHAPTER 14 8/16-BIT PPG
14.4
Operations of 8/16-bit PPG
One 8/16-bit PPG consists of two channels of 8-bit PPG units. These two channels can
be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG
mode, and single-channel 16-bit PPG mode.
■ Operations of 8/16-bit PPG
Each of the 8-bit PPG units has two eight-bit reload registers. One reload register is for the "L" pulse width
(PRLL) and the other is for the "H" pulse width (PRLH). The values stored in these registers are reloaded
into the 8-bit down counter (PCNT), from the PRLL and PRLH in turn. The pin output value is inverted
upon a reload caused by counter borrow. This operation results in the pulses of the specified "L" pulse
width and "H" pulse width.
Table 14.4-1 lists the relationship between the reload operation and pulse outputs.
Table 14.4-1 Reload Operation and Pulse Output
Reload operation
Pin output change
PRLH --> PCNT
PPG0/1 [0 --> 1]
Rise
PRLL --> PCNT
PPG0/1 [1 --> 0]
Fall
When "1" is set in bit4 (PIE0) of PPGC0 or in bit12 (PIE1) of PPGC1, an interrupt request is output upon a
borrow from "00H" to "FFH" (from "0000H" to "FFFFH" in 16-bit PPG mode) of each counter.
■ Operation Modes of 8/16-bit PPG
This block can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG mode,
and single-channel 16-bit PPG mode.
● Independent two-channel mode
The two channels of 8-bit PPG units operate independently. The PPG00 pin is connected to the ch.0 PPG
output, while the PPG10 pin is connected to the ch.1 PPG output.
● 8-bit prescaler + 8-bit PPG mode
ch.0 is used as an 8-bit prescaler while the count in ch.1 is based on borrow outputs from ch.0. Thus, 8-bit
PPG waveforms can be output with arbitrary length of cycle time. The PPG00 pin is connected to the ch.0
prescaler output, while the PPG10 pin is connected to the ch.1 PPG output.
230
CHAPTER 14 8/16-BIT PPG
● 16-bit PPG 1ch mode
ch.0 and ch.1 are connected and used as a single 16-bit PPG. The PPG00 and PPG10 pins are connected to
the 16-bit PPG output.
For the MB90440G Series, the output signal from the Channel 0 PPG is not connected to any external pin.
■ 8/16-bit PPG Output Operation
The 8/16-bit channel 0 PPG is activated by setting bit7 (PEN0) of the PPGC0 (PWM operation mode
control) register to "1". The 8/16-bit channel 1 PPG is activated by setting bit15 (PEN1) of the PPGC1
register to "1". After operation is started, counting is stopped by writing "0" to bit7 (PEN0) of PPGC0 or
bit15 (PEN1) of PPGC1. After counting is stopped, the pulse output is maintained at the "L" level. In the
MB90440G series, the output signal from the channel 0 PPG is not connected to any external pin.
In 8-bit prescaler + 8-bit PPG mode, do not set ch.1 to be in operation while ch.0 operation is stopped.
In 16-bit PPG mode, ensure that bit7 (PEN0) of PPGC0 register and bit15 (PEN1) of PPGC1 register are
started or stopped simultaneously. The figure below is a diagram of PPG output operation. During PPG
operation, a pulse wave is continuously output at a frequency and duty ratio (the ratio of the "H" level
period of the pulse wave to the "L" level period). PPG continues operation until stop is specified explicitly.
Figure 14.4-1 PPG Output Operation, Output Waveform
PEN
Starts operation based on PEN (from Lside).
Output pin
PPG
T
(L+1)
(Start)
T
(H+1)
L :PRLL value
H :PRLH value
T :Input from peripheral clock(
or timer base counter (depending on the
clock selection by PPGC)
■ Relationship Between 8/16-bit PPG Reload Value and Pulse Width
The width of the output pulse is determined by adding "1" to the reload register value and multiplying it by
the count clock cycle. Note that when the reload register value is "00H" during 8-bit PPG operation or
"0000H" during 16-bit PPG operation, the pulse width is equivalent to one count clock cycle. In addition,
note that when the reload register value is "FFH" during 8-bit PPG operation, the pulse width is equivalent
to 256 count clock cycles. When the reload register value is "FFFFH" during 16-bit PPG operation, the
pulse width is equivalent to 65536 count clock cycles. The following is an example of calculating the pulse
width:
Pl =T
Ph=T
(L+1)
(H+1)
L : PRLL value
H : PRLH value
T : Input clock cycle
Ph: High pulse width
Pl : Low pulse width
231
CHAPTER 14 8/16-BIT PPG
14.5
Selecting a Count Clock for 8/16-bit PPG
The count clock used for the operation is supplied from the peripheral clock or the timebase timer. The count clock can be selected from six choices.
■ Selecting a Count Clock for 8/16-bit PPG
Select ch.0 clock at bit4 to bit2 (PCM2 to PCM0) of the PPG01 register, and ch.1 clock at bit7 to bit5
(PCS2 to PCS0) of the PPG01 register.
The clock is selected from a peripheral clock 1/16, 1/4 or 1 time higher than a machine clock or an input
clock from the time-base timer.
In 8-bit prescaler + 8-bit PPG mode or 16-bit PPG mode, however, the setting in the PCS2 to PCS0 has no
effect.
When the time-base timer input is used, the first count cycle after a trigger or a stop may be shifted. The
cycle may also be shifted if the time-base counter is cleared during operation of this module.
In 8-bit prescaler + 8-bit PPG mode, if ch.1 is activated while ch.0 is in operation and ch.1 is stopped, the
first count cycle may be shifted.
232
CHAPTER 14 8/16-BIT PPG
14.6
Controlling Pin Output of 8/16-bit PPG Pulses
The pulses generated by this module can be output from external pins PPG00 and
PPG10.
■ Controlling Pin Output of 8/16-bit PPG Pulses
To output the pulses from an external pin, write "1" to the bit corresponding to each pin (PPG0 =PE00,
PPG1=PE10). When "0" is written to these bits (default), the pulses are not output from the corresponding
external pins; the pins work as general-purpose ports.
In 16-bit PPG mode, the same waveform is output from PPG00 and PPG10. Thus, the same output can be
obtained by enabling both external pin.
In 8-bit prescaler + 8-bit PPG mode, the 8-bit prescaler toggle output waveform is output from PPG00,
while the 8-bit PPG waveform is output from PPG10. Figure 14.6-1 is a diagram of output waveforms in
this mode.
For the MB90440G Series, the output signal from the Channel 0 PPG is not connected to any external pin.
Figure 14.6-1 8+8 PPG Output Operation Waveform
Ph0
Pl0
PPG0
PPG1
Ph1
Pl1
Pl0 = T
(L0+1)
Ph0 = T
(L0+1)
Pl1 = T
(L0+1)
(Ll+1)
Ph1 = T
(L0+1)
(Hl+1)
L0 :ch.0 PRLL value and ch.0 PRLH value
L1 :ch.1 PRLL value
H1 :ch.1 PRLH value
T : Input clock cycle
Ph0 :PPG00 high pulse width
Pl0 :PPG00 low pulse width
Ph1 :PPG10 high pulse width
Pl1 :PPG10 low pulse width
Note:
Set the same value in ch.0 PRLL and ch.0 PRLH.
233
CHAPTER 14 8/16-BIT PPG
14.7
8/16-bit PPG Interrupts
For the 8/16-bit PPG, an interrupt becomes active when the reload value counts out and
a borrow occurs.
■ 8/16-bit PPG Interrupts
In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, an interrupt is requested by a borrow in each
counter. In 16-bit PPG mode, PUF0 and PUF1 are simultaneously set by a borrow in the 16-bit counter.
Therefore, enable only PIE0 or PIE1 to unify the interrupt causes. In addition, simultaneously clear the
interrupt flags for PUF0 and PUF1.
234
CHAPTER 14 8/16-BIT PPG
14.8
Initial Values of 8/16-bit PPG Hardware
The hardware components of this block are initialized to the following values when
reset:
■ Initial Values of 8/16-bit PPG Hardware
● <Registers>
• PPGC0 --> 0X000001B
• PPGC1 --> 00000001B
• PPG10 --> XXXXXX00B
● <Pulse outputs>
• PPG00 --> "L"
• PPG10 --> "L"
• PE00
-->
PPG00 output disabled
• PE10
-->
PPG10 output disabled
● <Interrupt requests>
• IRQ0 --> "L"
• IRQ1 --> "L"
Hardware components other than the above are not initialized.
Note:
Write timing for 8/16-bit PPG reload registers (PRLL and PRLH)
In a mode other than 16-bit PPG mode, it is recommended to use a word transfer instruction to write
data in reload registers PRLL and PRLH. If two byte transfer instructions are used to write a data
item to these registers, a pulse of unexpected cycle time may be output depending on the timing.
Figure 14.8-1 Write Timing for 8/16-bit PPG Reload Registers (PRLL and PRLH)
PPG0
B
B
A
A
C
B
C
C
D
D
Assume that PRLL is updated from A to C before point 1 in the time chart above, and PRLH is updated
from B to D after point 1. Since the PRL values at point 1 are PRLL=C and PRLH=B, a pulse of L side
count value C and H side count value B is output only once.
235
CHAPTER 14 8/16-BIT PPG
Similarly, to write data in PRL of ch.0 and ch.1 in 16-bit PPG mode, use a long word transfer instruction,
or use word transfer instructions in the order of ch.0 and then ch.1. In this mode, the data is only
temporarily written to ch.0 PRL. Then, the data is actually written into ch.0 PRL when the ch.1 PRL is
written to.
As shown in Figure 14.8-2 in a mode other than 16-bit PPG mode, channel 0 PRL and channel 1 PRL can
be written independently.
Figure 14.8-2 PRL Write Operation Block Diagram
ch.0 PRL write data
ch.1 PRL write data
Transferred in synchronization
with ch.1 write in 16-bit
Temporary latch
PPG mode
ch.0 write in a mode other
than 16-bit PPG mode
ch.1 write
ch.0 PRL
236
ch.1 PRL
CHAPTER 15
DELAYED INTERRUPT
This chapter explains the functions and operations of
the delayed interrupt.
15.1 Outline of Delayed Interrupt Module
15.2 Delayed Interrupt Register
15.3 Delayed Interrupt Operation
237
CHAPTER 15 DELAYED INTERRUPT
15.1
Outline of Delayed Interrupt Module
The delayed interrupt source module is used to generate interrupts for switching tasks.
Using this module, interrupt requests to the F2MC-16LX CPU can be issued and
canceled by software.
■ Block Diagram of Delayed Interrupt
Figure 15.1-1 is a block diagram of the delayed interrupt source module.
Internal data bus
Figure 15.1-1 Block Diagram of Delayed Interrupt
Delayed interrupt cause issuance/cancellation register
Cause latch
■ Notes on Operation
This lock is set by writing "1" to the corresponding bit of DIRR, and is cleared by writing "0" to the same
bit. Therefore, interrupt processing is reactivated immediately after control returns from interrupt
processing, unless the software is designed so that the cause of the interrupt is cleared within the interrupt
processing routine.
238
CHAPTER 15 DELAYED INTERRUPT
15.2
Delayed Interrupt Register
DIRR controls issuance and cancellation of delayed interrupt requests. Writing "1" to
this register issues a delayed interrupt request, and writing "0" cancels the delayed
interrupt request. Upon a reset, the request is canceled.
■ Delayed Interrupt Cause Issuance/Cancellation Register (DIRR)
In DIRR, either "0" or "1" can be written to the reserved bit area. However, it is recommended that a set bit
or clear bit instruction be used to access this register for future expansions.
Figure 15.2-1 Delayed Interrupt Cause Issuance/Cancellation Register (DIRR)
Delayed Interrupt Cause Issuance/Cancellation Register
bit 15
14
13
12
11
10
9
Address : 00009FH
8
R0
Read/write
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(R/W)
Initial value
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(0)
DIRR
239
CHAPTER 15 DELAYED INTERRUPT
15.3
Delayed Interrupt Operation
When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the
delayed interrupt source module is set and an interrupt request is issued to the
interrupt controller.
■ Delayed Interrupt Occurrence
When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the delayed interrupt
source module is set and an interrupt request is issued to the interrupt controller. If this interrupt has the
highest priority or if there is no other interrupt request, the interrupt controller issues an interrupt request to
the F2MC-16LX CPU. The F2MC-16LX CPU compares the ILM bit of its internal CCR register and the
interrupt request, and starts the hardware interrupt processing microprogram as soon as the current
instruction is completed if the interrupt level of the request is higher than that of the ILM bit. The interrupt
processing routine for this interrupt is thus executed.
Figure 15.3-1 Delayed Interrupt Issuance
Delayed interrupt source module
Interrupt controller
WRITE
F 2 MC-16LX CPU
Other requests
ICR yy
IL
CMP
CMP
DIRR
ICR xx
ILM
INTA
Writing "0" to the relevant DIRR bit in the interrupt processing routine clears the cause of this interrupt and
switches between tasks.
240
CHAPTER 16
DTP/EXTERNAL
INTERRUPTS
This chapter explains the functions and operations of
the DTP/external interrupts.
16.1 Outline of DTP/External Interrupts
16.2 DTP/External Interrupt Registers
16.3 Operations of DTP/External Interrupts
16.4 Switching between External Interrupt and DTP Requests
16.5 Notes on Using DTP/External Interrupts
241
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.1
Outline of DTP/External Interrupts
The data transfer peripheral (DTP) is located between an external peripheral and the
F2MC-16LX CPU. The DTP receives a DMA request or interrupt request from the external
peripheral, transfers the request to the F2MC-16LX CPU to activate the intelligent I/O
service or interrupt processing.
■ Outline of DTP/External Interrupts
For the intelligent I/O service, "H" and "L" request levels are available. For an external interrupt request,
four request levels are available: "H", "L", rising edge, and falling edge.
■ Block Diagram of DTP/External Interrupts
Figure 16.1-1 Block Diagram of DTP/External Interrupts
Internal data bus
8
8
8
16
242
DTP/Interrupt enable register
Gate
Cause F/F
Edge detection circuit
DTP/Interrupt cause register
Request level setting register
8
Request input
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
■ DTP/External Interrupts Registers
Figure 16.1-2 DTP/External Interrupts Registers
DTP/Interrupt enable register
3
2
1
0
EN3
EN2
EN1
EN0
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(R/W)
(0)
bit
Address : 000030H
Read/write
Initial value
7
6
5
EN7
EN6
EN5
4
EN4
ENIR
(R/W) (R/W)
(0)
(0)
DTP/Interrupt cause register
bit
Address : 000031H
Read/write
Initial value
15
14
13
12
11
10
9
8
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
(R/W)
(X)
(R/W) (R/W)
(X)
(X)
(R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
EIRR
Request level setting register
bit
Address : 000033H
Read/write
Initial value
bit
Address : 000032H
Read/write
Initial value
15
14
13
12
11
10
9
8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(R/W)
(0)
7
6
5
LB3
LA3
LB2
4
LA2
(R/W) (R/W)
(0)
(0)
3
2
1
0
LB1
LA1
LB0
LA0
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(R/W)
(0)
ELVR
(R/W) (R/W)
(0)
(0)
243
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.2
DTP/External Interrupt Registers
The DTP/external interrupts has the following three types of registers:
• DTP/Interrupt enable register (ENIR: Interrupt request enable register)
• DTP/Interrupt flag (EIRR: External interrupt request register)
• Request level setting register (ELVR: External level register)
■ DTP/Interrupt Enable Register (ENIR: Interrupt Request Enable Register)
Figure 16.2-1 DTP/Interrupt Enable Register (ENIR)
DTP/Interrupt Enable Register
bit
Address : 000030H
Read/write
Initial value
7
6
5
EN7
EN6
EN5
4
3
2
1
EN4
EN3
EN2
EN1
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(R/W)
(0)
0
EN0
ENIR
(R/W) (R/W)
(0)
(0)
ENIR enables the function to issue a request to the interrupt controller using a device pin as an DTP/
external interrupt request input. A pin corresponding to a "1" bit of this register is used as an DTP/external
interrupt request input. A pin corresponding to a "0" bit holds the DTP/external interrupt request input
cause, but does not issue a request to the interrupt controller.
Note:
Clear the corresponding external interrupt request flag bit (EIRR: ER) right before DTP/external
interrupt is allowed (ENIR: EN=1).
■ DTP/Interrupt Flags (EIRR: External Interrupt Request Register)
Figure 16.2-2 DTP/Interrupt Flag (EIRR)
DTP/Interrupt flag
bit 15
Address : 000031 H
Read/write
Initial value
ER7
14
13
12
11
10
9
8
ER6
ER5
ER4
ER3
ER2
ER1
ER0
(R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
(R/W)
(X)
EIRR
(R/W) (R/W)
(X)
(X)
The EIRR indicates the presence of DTP/external interrupt requests at the pins corresponding to the "1" bits
of this register. Writing "0" to a bit of this register clears the corresponding request flag. Writing "1" has no
effect. "1" is always read from this register by a read-modify-write instruction.
244
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
Notes:
• If multiple external interrupt request outputs are enabled (ENIR: EN7 to EN0=1), only the bits for
which the CPU accepts an interrupt (bits for which "1" is set in ER7 to ER0) are cleared to "0". No
other bits must be cleared unconditionally.
• The value of external interrupt request flag bit (EIRR: ER) is valid only when the corresponding
external interrupt request enable bit (ENIR: EN) is set to "1". In the case that DTP/external
interrupt is not allowed (ENIR: EN=0), DTP/external interrupt cause bit could be set regardless of
the possibility of DTP/external interrupt cause.
• Clear the corresponding external interrupt request flag bit (EIRR: ER) right before DTP/external
interrupt is allowed (ENIR: EN=1).
■ Request Level Setting Register (ELVR: External level register)
Figure 16.2-3 Request Level Setting Register (ELVR)
Register Level Setting Register
bit
Address : 000033 H
Read/write
Initial value
Read/write
Initial value
14
13
12
11
10
9
8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
bit
Address : 000032 H
15
7
6
5
LB3
LA3
LB2
4
3
LA2
LB1
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(R/W)
(0)
(R/W) (R/W)
(0)
(0)
2
1
LA1
LB0
(R/W)
(0)
0
LA0
ELVR
(R/W) (R/W)
(0)
(0)
ELVR defines the request event at the external pin. Each pin is assigned two bits as described in Table
16.2-1 . If a request is detected by the input level, the interrupt flag is set as long as the input is at the
specified level even after the flag is reset by software.
Table 16.2-1 Interrupt Request Detection Factor for the Setting Values and Pins of LBx
and LAx
LBx
LAx
0
0
1
1
0
1
0
1
Interrupt request detection factor
"L" level pin input
"H" level pin input
Rising edge pin input
Falling edge pin input
245
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.3
Operations of DTP/External Interrupts
When the interrupt flag is set, this block signals an interrupt to the interrupt controller.
The interrupt controller judges the priority levels of the simultaneous interrupts, and
issues an interrupt request to the F2MC-16LX CPU if the interrupt from this block has
the highest priority. The F2MC-16LX CPU compares the ILM bits of its internal CCR
register and the interrupt request. If the interrupt level of the request is higher than that
indicated by the ILM bits, the F2MC-16LX CPU activates the hardware interrupt
processing microprogram as soon as the currently executing instruction is terminated.
■ External Interrupt Operation
In the hardware interrupt processing microprogram, the CPU reads the ISE bit information from the
interrupt controller, identifies that the request is for interrupt processing based on that information, and
branches to the interrupt processing microprogram. The interrupt processing microprogram reads the
interrupt vector area and issues an interrupt acknowledgment signal for the interrupt controller. Then, the
microprogram transfers the jump destination address of the macro instruction generated from the vector to
the program counter, and executes the user interrupt processing program.
Figure 16.3-1 External Interrupt
DTP/External interrupt
Interrupt controller
F2MC-16LX CPU
ICR yy
IL
Other request
ELVR
EIRR
ENIR
Cause
CMP
ICR xx
CMP
ILM
INTA
■ DTP operation
To activate the intelligent I/O service, the user program initially sets the address of a register, assigned
between 000000H and 0000FFH, in the I/O address pointer of the intelligent I/O service descriptor. Then,
the user program sets the start address of the memory buffer in the buffer address pointer.
The DTP operation sequence is almost the same as for external interrupts. The operation is identical until
the CPU activates the hardware interrupt processing microprogram. Then, for the DTP, control is
transferred to the intelligent I/O service processing microprogram, since the ISE bit read by the CPU within
the hardware interrupt processing microprogram indicates the DTP. Once the intelligent I/O service is
activated, a read or write signal is sent to the addresses external peripheral, and data is transferred between
the peripheral and the chip. The external peripheral must cancel the interrupt request to this chip within
three machine cycles after the transfer is made. When the transfer is completed, the descriptor is updated,
and the interrupt controller generates a signal that clears the transfer cause. Upon receiving the signal to
clear the transfer cause, this resource clears the flip-flop holding the cause and prepares for the next request
from the pin. For details of the intelligent I/O service processing, refer to the MB90500 Programming
Manual.
246
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
Figure 16.3-2 Timing to Cancel the External Interrupt at the End of DTP Operation
Edge request or H level request
Interrupt cause
Internal operation
Selecting and
reading
descriptor
* When data is transferred from the I/O register to memory
in the intelligent I/O service
Read address
Address bus pin
Data bus pin
Write address
Read data
Read signal
Write data
➀
Write signal
➁
Cancel within three machine cycles.
Data, address
bus
Internal bus
Register
External peripheral
Figure 16.3-3 Sample Interface to the External Peripheral and DTP
➀
INT
IRQ
DTP
Cancel within three machine
cycles after transfer.
➁
CORE
MEMORY
MB90440G Series
247
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.4
Switching between External Interrupt and DTP Requests
To switch between external interrupt and DTP requests, use the ISE bit in the ICR
register corresponding to this block, which is in the interrupt controller. Each pin is
individually assigned ICR. Thus, a pin is used for a DTP request if "1" is written to the
ISE bit of the corresponding ICR, and is used for an external interrupt request if "0" is
written to the bit.
■ Switching Between External Interrupt and DTP Requests
Figure 16.4-1 Switching Between External Interrupt and DTP Requests
Interrupt controller
0
ICR xx
ICR yy
1
F 2 MC-16 LX CPU
Pin
DTP/
External interrupt
DTP
External interrupt
248
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.5
Notes on Using DTP/External Interrupts
Note carefully the following items when using DTP/external interrupts:
• Conditions on the externally connected peripheral when DTP is used
• Recovery from standby
• External interrupt/DTP operation procedure
• External interrupt request level
■ Notes on Using DTP/External Interrupts
● Conditions on the externally connected peripheral when DTP is used
DTP supports only external peripherals that automatically clear a request once a transfer is completed. The
system must be designed so that a transfer request is canceled within three machine cycles (provisional)
after transfer operation starts. Otherwise, this resource assumes that a transfer request is issued.
● External interrupt/DTP operation procedure
To set registers in the external interrupt/DTP, follow the steps below:
1. Set the general-purpose I/O port shared with the pin for using the external interrupt input as the input
port.
2. Disable the bits corresponding to the enable register.
3. Set the bits corresponding to the request level setting register.
4. Clear the bits corresponding to the cause register.
5. Enable the bits corresponding to the enable register.
(Steps 4. and 5. can be simultaneously performed by word specification.)
To set a register in this resource, ensure that the enable register is disabled. Before enabling the enable
register, ensure that the cause register is cleared. Clearing the cause register prevents a false interrupt cause
from being determined while registers are set or interrupts are enabled.
● External interrupt request level
To detect an edge for an edge request level, the pulse width must be at least three machine cycles.
When the request input level is set to "level setting", the pulse width must be at least 3 machine cycles.
Even if the external interrupt cause register is cleared, the interrupt request to the interrupt controller is
continuously generated as long as the interrupt input pin remains active level.
As shown in Figure 16.5-1 , when the request input level is related to the level setting, a request that is
input from an external device to the interrupt controller is kept active even if the request is later canceled
because a cause hold circuit has been installed. To cancel the request to the interrupt controller, the cause
hold circuit must be cleared as shown in Figure 16.5-2 .
249
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
Figure 16.5-1 Clearing the Cause Hold Circuit Upon Level Set
Interrupt cause
Level detection
Cause F/F (cause hold circuit)
Enable gate
To interrupt
controller
The cause is kept held unless cleared.
Figure 16.5-2 Interrupt Cause and Interrupt Request to the Interrupt Controller While Interrupts are
Enabled
Interrupt cause
H level
Interrupt request to
the interrupt controller
Set inactive when the cause F/F is cleared.
250
CHAPTER 17
A/D CONVERTER
This chapter explains the functions and operations of
the A/D converter.
17.1 Features of A/D Converter
17.2 Block Diagram of A/D Converter
17.3 A/D Converter Registers
17.4 Operations of A/D Converter
17.5 Conversion Using EI2OS
17.6 Conversion Data Protection
251
CHAPTER 17 A/D CONVERTER
17.1
Features of A/D Converter
The A/D converter converts analog input voltages into digital values. The A/D converter
has the following features:
■ Features of A/D Converter
● Conversion time:
6.12 µs min. per channel (at 16 MHz machine clock)
● RC sequential compare conversion with sample and hold circuit
● 10-bit or 8-bit resolution
● Analog input selected from eight channels by programming
Single conversion mode:
One channel is selected for conversion.
Scan conversion mode:
Voltages in multiple consecutive channels are converted. Up to eight
channels can be programmed.
Continuous conversion mode: Voltages at the specified channel are converted repeatedly.
Stop conversion mode:
Voltages at the one channel is converted, then the system pauses and stands
by for the next activation. (The conversion start points can be synchronized.)
● Interrupt request
At the end of A/D conversion, a relevant interrupt request can be issued to the CPU. This interrupt can be
used to activate the EI2OS, which automatically transfers A/D conversion result to memory. This feature is
suitable for continuous processing.
● Selectable activation cause
The activation can be done by software, external trigger (falling edge), or timer (rising edge).
252
CHAPTER 17 A/D CONVERTER
■ Analog Input Enable Register
Always write "1" to the ADER bit corresponding to a pin used as analog input.
Figure 17.1-1 Analog Input Enable Register
Analog Input Enable Register
15
14
13
12
11
10
9
8
Address: 00001BH
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
Read/write
Initial value
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
bit
ADER
Port 6 pins are controlled as described below.
0: Port input/output mode
1: Analog input mode
"1" is set upon a reset.
■ Input Impedance
The sampling circuit of the A/D Converter can be represented with the equivalent circuit shown below.
3.2 k
Analog input
ADC
30 pF max.
Driving impedance to an analog input should be lower than 5 kΩ when the sampling time is set 2µs (ST1=0
and ST0=1 at 16MHz machine clock). Otherwise the conversion accuracy will be worsened. If this is the
case, set the sampling time longer or add external capacitor in order to compensate the driving impedance.
253
CHAPTER 17 A/D CONVERTER
17.2
Block Diagram of A/D Converter
Figure 17.2-1 shows a block diagram of the A/D converter.
■ Block Diagram of A/D Converter
Figure 17.2-1 Block Diagram of A/D Converter
AVCC
AVRL/AVRLH
AVSS
D/A converter
Sequential compare register
Comparator
Decoder
Sample and hold circuit
Data register
ADCR0/ADCR1
ADCS0/ADCS1
A/D control register 0
A/D control register 1
Activation by external trigger
ADTG pin
Activation by timer
16-bit Reload Timer 1
Operation clock
Prescaler
254
Internal data bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Input circuit
MPX
CHAPTER 17 A/D CONVERTER
17.3
A/D Converter Registers
The A/D converter has the following two types of registers:
• A/D Control status register
• Data register
■ A/D Converter Registers
The A/D converter has the following registers:
Figure 17.3-1 A/D Converter Register Configuration
bit
15
8
7
0
ADCS1
ADCS0
ADCR1
ADCR0
8SSR
bits
8 bits
Figure 17.3-2 A/D Converter Registers
A/D control status register (upper)
bit
Address : 000035H
Read/write
Initial value
15
14
BUSY
INT
(R/W) (R/W)
(0)
(0)
A/D control status register (lower)
7
6
bit
MD1
Address : 000034H
12
11
10
9
8
INTE PAUS STS1
STS0
STRT
reserved
(R/W) (R/W) (R/W)
(R/W)
(W)
(R/W)
(0)
(0)
(0)
(0)
(0)
(0)
5
4
3
2
1
0
MD0 ANS2 ANS1 ANS0
(R/W) (R/W)
Read/write
Initial value
13
(R/W) (R/W) (R/W)
ANE2
ANE1 ANE0
(R/W)
(R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
15
14
13
12
11
10
9
8
Address : 000037H
SI0
ST1
ST0
CT1
CT0
D9
D8
Read/write
Initial value
(W)
(W)
(W)
(W)
(W)
(-)
(R)
(R)
(0)
(0)
(1)
(0)
(1)
(-)
(X)
(X)
7
6
5
4
3
2
1
0
Address : 000036H
D7
D6
D5
D4
D3
D2
D1
D0
Read/write
Initial value
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
ADCS1
ADCS0
Data register (upper)
bit
ADCR1
Data register (lower)
bit
ADCR0
255
CHAPTER 17 A/D CONVERTER
17.3.1
A/D Control Status Registers (ADCS0)
The A/D control status register (ADCS0) controls the A/D converter and indicates the
status. Do not rewrite ADCS0 during A/D conversion.
■ A/D Control Status Registers (ADCS0)
Figure 17.3-3 A/D Control Status Register (ADCS0)
A/D control status register (lower)
7
6
5
4
3
2
1
0
Address: 000034 H
MD1
MD0
ANS2
ANS1
ANS0
ANE2
ANE1
ANE0
Read/write
Initial value
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
bit
ADCS0
[bit7, bit6] MD1, MD0 (A/D converter mode set)
Use the MD1 and MD0 bits to set the operation mode.
MD1
MD0
Operation mode
0
0
Single mode. Reactivation during operation is allowed.
0
1
Single mode. Reactivation during operation is not allowed.
1
0
Continuous mode. Reactivation during operation is not allowed.
1
1
Stop mode. Reactivation during operation is not allowed.
• Single mode:
- A/D conversion is continuously performed from the channel specified with ANS2 to ANS0 to the
channel specified with ANE2 to ANE0. The conversion stops once it has been done for all these
channels.
• Continuous mode:
- A/D conversion is repeatedly performed from the channel specified with ANS2 to ANS0 to the
channel specified with ANE2 to ANE0.
• Stop mode:
- A/D conversion is performed from the channel specified with ANS2 to ANS0 to the channel
specified with ANE2 to ANE0, pausing for each channel. The A/D conversion is resumed upon an
activation.
Upon a reset, these bits are initialized to "00B".
256
CHAPTER 17 A/D CONVERTER
Notes:
• When activated in the continuous or stop mode, A/D conversion continues until it is stopped by
the BUSY bit.
• The conversion is stopped by writing "0" to the BUSY bit.
• Reactivation disabled in single mode, continuous mode, and stop mode applies to all kinds of
activation by software, an external trigger, and a timer.
[bit5 to bit3] ANS2 to ANS0 (Analog start channel set)
Use these bits to specify the start channel for A/D conversion.
When the A/D converter is activated, A/D conversion starts from the channel selected with these bits.
ANS2
ANS1
ANS0
Start channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
Notes:
• When read:
During A/D conversion, the current conversion channel is read from these bits. If the system is
stopped in the stop mode, the last conversion channel is read.
• Upon a reset, these bits are initialized to "000B".
257
CHAPTER 17 A/D CONVERTER
[bit2 to bit0] ANE2 to ANE0 (Analog end channel set)
Use these bits to set the A/D conversion end channel.
ANE2
ANE1
ANE0
End channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
Notes:
• Do not set the bits in this resister using the read-modify-write instruction after the start channels
are set for analog start channel set bits (ANS2, ANS1, and ANS0).
• For ANS2, ANS1, and ANS0 bits their previous conversion channels are read until A/D conversion
operation starts, therefore, if you set the bits in this resister using the read-modify-write instruction
after the start channels are set for ANS2,ANS1, and ANS0 bits, the values of ANE2, ANE1, and
ANE0 bits may be rewritten.
• When the same channel is written to ANE2 to ANE0 and ANS2 to ANS0, conversion is performed
for one channel only (single conversion).
• In the continuous or stop mode, operation returns to the start channel specified in ANS2 to ANS0
after the conversion is completed for the channel specified in ANE2 to ANE0.
• If the ANS value is greater than the ANE value, conversion starts from the ANS channel. Then,
once conversion is complete up to channel 7, operation returns to channel 0 and conversion is
performed up to the ANE channel.
•
Upon a reset, these bits are initialized to "000B".
Example: ANS=6ch, ANE=3ch, single mode
Conversion is performed in the following sequence: ch.6,→ ch.7,→ ch.0,→ ch.1,→ ch.2,→ ch.3
258
CHAPTER 17 A/D CONVERTER
17.3.2
A/D Control Status Register (ADCS1)
The A/Dcontrol status register (ADCS1) controls the A/D converter and indicates the
status.
■ A/D Control Status Register (ADCS1)
Figure 17.3-4 A/D Control Status Register (ADCS1)
A/D control status register (upper)
15
14
13
12
11
10
9
8
Address: 000035 H
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
reserved
Read/write
Initial value
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(W)
(0)
(R/W)
(0)
bit
ADCS1
[bit15] BUSY (busy flag and stop)
- Read
This bit indicates the A/D converter operation.
This bit is set when A/D conversion starts and is cleared when the conversion ends.
- Write
Writing "0" to this bit during A/D conversion forces the conversion to terminate.
The above feature is used for forced stop in continuous or stop mode.
"1" cannot be written to the BUSY bit. With a read-modify-write (RMW) instruction, "1" is read from
this bit. In single mode, this bit is cleared at the end of A/D conversion.
In continuous or stop mode, this bit is not cleared until conversion is stopped by writing "0".
This bit is initialized to "0" upon a reset.
Do not perform a forced stop and activation by software simultaneously (BUSY = 0, STRT = 1).
[bit14] INT (Interrupt)
This bit is set when conversion data is written to ADCR.
An interrupt request is issued if this bit is set while bit5 (INTE) is "1". In addition, the EI2OS is
activated if it is enabled. Writing "1" has no effect.
This bit is cleared by writing "0" or by the EI2OS interrupt clear signal.
Note:
To clear this bit by writing "0", ensure that A/D conversion is not in progress.
This bit initialized to "0" upon a reset.
259
CHAPTER 17 A/D CONVERTER
[bit13] INTE (Interrupt enable)
This bit is used to enable or disable interrupts at the end of conversion.
- 0: Interrupts are disabled.
- 1: Interrupts are enabled.
Set this bit when using the EI2OS. The EI2OS is activated when an interrupt request is issued.
Upon a reset, this bit is initialized to "0".
[bit12] PAUS (A/D conversion pause)
This bit is set when the A/D conversion is paused.
Only one register is available for storing the A/D conversion result. Therefore, unless the conversion
results are transferred by the EI2OS, the result data would be continuously updated and destroyed in
continuous conversion.
To prevent the above condition, the system is designed so that a data register value must be transferred
by the EI2OS before the next conversion data is saved. A/D conversion pauses during that period. A/D
conversion is resumed at the end of transfer by the EI2OS.
This register is valid only when the EI2OS is used.
Notes:
• For the conversion data protection function, see Section "17.6 Conversion Data Protection".
• Upon a reset, this bit is initialized to "0".
[bit11, bit10] STS1, STS0 (Start source select)
Upon a reset, these bits are initialized to "00B".
These bits are used to select the A/D conversion activation source.
STS1
STS0
Function
0
0
Activation by software
0
1
Activation by external pin trigger and software
1
0
Activation by timer and software
1
1
Activation by external pin trigger, timer, and software
In a mode allowing two or more activation factors, A/D conversion is activated by the source that
occurs first.
The activation source setting changes as soon as it is updated. Thus, take care when updating it during
A/D conversion.
Note:
The external pin trigger is detected by the falling edge. If this bit is updated to external trigger
activation while the external trigger input level is "L", A/D may be activated at once.
When timer is selected, the 16-bit Reload Timer 1 is selected.
260
CHAPTER 17 A/D CONVERTER
[bit9] STRT (Start)
A/D conversion is activated when "1" is written to this bit.
To reactivate A/D conversion, write "1" to this bit again.
Upon a reset, this bit is initialized to "0".
In the stop mode, a reactivation during the operation is not supported. Check the BUSY bit before
writing "1".
Do not perform a forced stop and activation by software simultaneously. (BUSY=0, STRT=1)
[bit8]Reserved: Reserved bit
Always write "0" to this bit.
261
CHAPTER 17 A/D CONVERTER
17.3.3
Data Registers (ADCR1 and ADCR0)
These registers are used to store the digital values produced as a result of the
conversion. ADCR1 stores the most significant two bits of the conversion result, while
ADCR0 stores the lower eight bits. These register values are updated each time
conversion is completed. Usually, the final conversion value is stored in these bits.
■ Data Registers (ADCR1 and ADCR0)
Figure 17.3-5 Data Registers (ADCR1 and ADCR0)
Data register (lower)
7
6
5
4
3
2
1
0
Address : 000036 H
D7
D6
D5
D4
D3
D2
D1
D0
Read/write
Initial value
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
15
14
13
12
11
10
9
8
Address : 000037 H
S10
ST1
ST0
CT1
CT0
D9
D8
Read/write
Initial value
(W)
(0)
(W)
(0)
(W)
(1)
(W)
(0)
(W)
(1)
(R)
(X)
(R)
(X)
bit
ADCR0
Data register (upper)
bit
(-)
(-)
ADCR1
"0" is always read from the bit10 to bit15 of ADCR1.
The conversion data protection function is available. See Section "17.4 Operations of A/D Converter" for
details. Ensure that no data is written to these registers during A/D conversion.
[bit15] S10
This bit specifies the resolution of the conversion. When it is set to "0", the 10-bit A/D conversion is
performed. Otherwise the 8-bit A/D conversion is performed and the result is stored in the D7 to D0.
Reading this bit always returns "0".
262
CHAPTER 17 A/D CONVERTER
[bit14, bit13] ST1, ST0 (Sampling time):
ST1
ST0
Function
0
0
20 machine cycles (2.5µs at 8MHz)
0
1
32 machine cycles (2.0µs at 16MHz)
1
0
48 machine cycles (3.0µs at 16MHz)
1
1
128 machine cycles (8.0µs at 16MHz)
These bits determines the duration of the voltage sampling time at the input.
Do not set to "00B" unless the machine clock is 8MHz. Otherwise the conversion accuracy is not
guaranteed. Reading these bits always returns "00B".
[bit12, bit11] CT1, CT0 (Compare time):
CT1
CT0
Function
0
0
44 machine cycles (5.5µs at 8MHz)
0
1
66 machine cycles (4.12µs at 16MHz)
1
0
88 machine cycles (5.5µs at 16MHz)
1
1
176 machine cycles (11.0µs at 16MHz)
These bits determines the duration of the compare operation time.
Do not set to "00B" unless the machine clock is 8MHz. Otherwise the conversion accuracy is not
guaranteed.
Reading these bits always returns "00B".
263
CHAPTER 17 A/D CONVERTER
17.4
Operations of A/D Converter
The A/D converter operates employs the sequential compare technique, and has a 10-bit
resolution.
Since the A/D converter has only one register (16 bits) for storing the conversion result,
the conversion data registers (ADCR0 and ADCR1) are updated each time conversion is
completed. Thus, the A/D converter alone must not be used for the continuous
conversion. Use the F2MC-16 intelligent I/O service (EI2OS) function to transfer
converted data to memory while conversion is in progress.
The operation modes are explained below.
■ Single Mode
In this mode, the converter sequentially converts the analog inputs specified with the ANS and ANE bits.
The converter stops operation after the conversion is completed for the end channel specified with the ANE
bits. If the start and end channels are the same (ANS=ANE), conversion is performed only for one channel.
Example:
ANS = 0 0 0, ANE = 0 1 1
Start -> AN0 -> AN1 -> AN2 -> AN3 -> End
ANS = 0 1 0, ANE = 0 1 0
Start -> AN2 -> End
■ Continuous Mode
In this mode, the converter sequentially converts the analog inputs specified with the ANS and ANE bits.
After the conversion is completed for the end channel specified with the ANE bits, conversion is repeated
from the analog inputs of the ANS. If the start and end channels are the same (ANS=ANE), conversion for
one channel is repeated.
Example:
ANS = 0 0 0, ANE = 0 1 1
Start -> AN0 -> AN1 -> AN2 -> AN3 -> AN0 -> Repeat
ANS = 0 1 0, ANE = 0 1 0
Start -> AN2 -> AN2 -> AN2 -> Repeat
In continuous mode, conversion is repeated until "0" is written to the BUSY bit. (Writing "0" to the BUSY
bit forces the operation to end.) If the operation is terminated forcibly, conversion stops before conversion
is completed. (Upon a forced stop, the conversion register stores the last data that has been converted
completely.)
264
CHAPTER 17 A/D CONVERTER
■ Stop Mode
In this mode, the converter sequentially converts the analog inputs specified with the ANS and ANE bits,
pausing each time conversion for one channel is completed. To release pausing, activate the converter
again.
After the conversion is completed for the end channel specified with the ANE bits, conversion is repeated
from the analog inputs of the ANS. If the start and end channels are the same (ANS=ANE), conversion is
performed only for one channel.
Example:
ANS = 0 0 0, ANE = 0 1 1
Start -> AN0 -> End -> Restart -> AN1 -> End -> Restart -> AN2 -> End ->
-> Restart -> AN3 -> End -> Restart --->AN0
Repeat
ANS = 0 1 0, ANE = 0 1 0
Start -> AN2 -> End -> Restart -> AN2 -> End -> Restart -> AN2 Repeat
Only the activation sources specified with STS1 and STS0 are used.
Using this mode, start of conversion can be synchronized with the activation source.
265
CHAPTER 17 A/D CONVERTER
17.5
Conversion Using EI2OS
Figure 17.5-1 shows the processing flow from the start of A/D conversion to the transfer
of converted data (in continuous mode).
■ Conversion Using EI2OS
Figure 17.5-1 A/D Conversion Processing Flow from the Start to Converted Data Transfer
(in Continuous Mode)
Starting A/D conversion
Sample and hold
Starting EI2OS
Conversion
Transferring data
Interrupt processing
End of conversion
Issuing interrupt
The portion indicated by the star (
266
Clearing interrupt
) is determined according to the EI2 OS setting.
CHAPTER 17 A/D CONVERTER
17.5.1
Starting EI2OS in Single Mode
Follow the steps below to start the EI2OS in single mode.
• To terminate conversion after analog inputs AN1 to AN3 are converted
• To transfer conversion data sequentially to addresses 200H to 205H
• To start conversion by software
• To use the highest interrupt level
■ Starting EI2OS in Single Mode
Table 17.5-1 Example of Starting EI2OS in Single Mode
Settings
Sample program
MOV ICR03, #08H
Function
Specifies the highest interrupt level, EI2OS activation
upon an interrupt, and the descriptor address.
MOV BAPL, #00H
MOV BAPM, #02H
Specifies the transfer destination address of converted
data.
MOV BAPH, #00H
EI2OS setting
MOV ISCS, #18H
Specifies word data transfer. The transfer destination
address is incremented after transfer. Data is transferred
from I/O to memory. Transfer is not terminated in
response to a request from a resource.
MOV IOA, #36H
MOV DCT, #03H
EI2OS transfer is performed three times. This count is
the same as the conversion count.
MOV ADCS0, #0BH
Specifies single mode, start channel AN1, and end
channel AN3.
MOV ADCS1, #A2H
Specifies activation by software and start of A/D
conversion.
RET
Specifies return from an interrupt.
A/D converter
setting
Interrupt sequence
ICR03:
BAPL:
BAPM:
BAPH:
ISCS:
IOA:
DCT:
Interrupt control register
Buffer address pointer, low-order
Buffer address pointer, medium-order
Buffer address pointer, high-order
EI2OS status register
I/O address counter
Data counter
267
CHAPTER 17 A/D CONVERTER
Figure 17.5-2 Example of Starting EI2OS in Single Mode
Activation
AN1
Interrupt
EI2 OS transfer
AN2
Interrupt
EI 2OS transfer
AN3
Interrupt
EI 2OS transfer
End
Interrupt sequence
Parallel processing
268
CHAPTER 17 A/D CONVERTER
17.5.2
Starting EI2OS in Continuous Mode
Follow the steps below to start the EI2OS in continuous mode.
• To convert analog inputs AN3 to AN5 and obtain two conversion data items for each
channel
• To transfer conversion data sequentially to addresses 600H to 60BH
• To start conversion by external edge input
• To use the highest interrupt level
■ Starting EI2OS in Continuous Mode
Table 17.5-2 Example of Starting EI2OS in Continuous Mode
Settings
Sample program
MOV ICR03, #08H
Function
Specifies the highest interrupt level, EI2OS
activation upon an interrupt, and the descriptor
address.
MOV BAPL, #00H
MOV BAPM, #06H
Specifies the transfer destination address of
converted data.
MOV BAPH, #00H
2
EI OS setting
MOV ISCS, #18H
Specifies word data transfer. The transfer destination
address is incremented after transfer. Data is
transferred from I/O to memory. Transfer is not
terminated in response to a request from a resource.
MOV IOA, #36H
Transfer source address
MOV DCT, #06H
EI2OS transfer is performed six times. Data is
transferred for three channels x 2.
MOV ADCS0, #9DH
Specifies continuous mode, start channel AN3, and
end channel AN5.
MOV ADCS1, #A4H
Specifies activation by external edge and start of A/
D conversion.
MOV ADCS1, #00H
Specifies return from an interrupt.
A/D converter setting
Interrupt sequence
ICR03:
BAPL:
BAPM:
BAPH:
ISCS:
IOA:
DCT:
RET
Interrupt control register
Buffer address pointer, low-order
Buffer address pointer, medium-order
Buffer address pointer, high-order
EI2OS status register
I/O address counter
Data counter
269
CHAPTER 17 A/D CONVERTER
Figure 17.5-3 Example of Starting EI2OS in Continuous Mode
Activation
AN3
Interrupt
EI 2 OS transfer
AN4
Interrupt
EI 2 OS transfer
After six transfers
AN5
Interrupt
EI 2 OS transfer
Interrupt sequence
End
270
CHAPTER 17 A/D CONVERTER
17.5.3
Starting EI2OS in Stop Mode
Follow the steps below to start the EI2OS in stop mode.
• To convert analog input AN3 12 times at fixed intervals
• To transfer conversion data sequentially to addresses 600H to 617H
• To start conversion by external edge input
• To use the highest interrupt level
■ Starting EI2OS in Stop Mode
Table 17.5-3 Example of Starting EI2OS in Stop Mode
Settings
Sample program
MOV ICR03, #08H
Function
Specifies the highest interrupt level, EI2OS
activation upon an interrupt, and the descriptor
address.
MOV BAPL, #00H
MOV BAPM, #06H
Specifies the transfer destination address of
converted data.
MOV BAPH, #00H
EI2OS setting
MOV ISCS, #18H
Specifies word data transfer. The transfer
destination address is incremented after transfer.
Data is transferred from I/O to memory. Transfer
is not terminated in response to a request from a
resource.
MOV IOA, #36H
Transfer source address
MOV DCT, #0CH
EI2OS transfer is performed 12 times.
MOV ADCS0, #DBH
Specifies stop mode, start channel AN3, and end
channel AN3 (one-channel conversion).
MOV ADCS1, #A4H
Specifies activation by external edge and start of
A/D conversion.
MOV ADCS1, #00H
Specifies return from an interrupt.
A/D converter setting
Interrupt sequence for
terminating
EI2OS
ICR03:
BAPL:
BAPM:
BAPH:
ISCS:
IOA:
DCT:
RET
Interrupt control register
Buffer address pointer, low-order
Buffer address pointer, medium-order
Buffer address pointer, high-order
EI2OS status register
I/O address counter
Data counter
271
CHAPTER 17 A/D CONVERTER
Figure 17.5-4 Example of Starting EI2OS in Stop Mode
Activation
AN3
Interrupt
EI2OS transfer
After 12 transfers
Stop
Activation by external edge
Interrupt sequence
End
272
CHAPTER 17 A/D CONVERTER
17.6
Conversion Data Protection
The A/D converter has a conversion data protection function that enables continuous
conversion and preservation of multiple data items using EI2OS.
One conversion data register is provided, and its value is updated after conversion.
When continuous A/D conversion is performed, conversion data is stored upon
completion of each conversion and the previous data is lost. To prevent this situation,
the A/D converter pauses without storing conversion data in the register if the previous
data has not been transferred to memory by EI2OS, even though conversion has been
completed.
■ Conversion Data Protection
The pause is released after data is transferred to memory by EI2OS.
If the previous data has been transferred to memory, the A/D converter continues operation without
pausing.
Note:
This function is related to the INT and INTE bits of ADCS1.
The data protection function operates only when interrupts are enabled (INTE=1).
If interrupts are disabled (INTE=0), this function is disabled. Continuous A/D conversion results in
loss of previous data, since the converted data items are saved to the register one after another.
If EI2OS is not used while interrupts are enabled (INTE=1), the INT bit is not cleared. Thus, the data
protection function works and the A/D converter pauses. In this case, clearing the INT bit in the
interrupt sequence releases the pause.
If the A/D converter is pausing during EI2OS operation, disabling interrupts may restart the A/D
converter. In this case, the value in the conversion data register may be changed without being
transferred.
Restarting the A/D converter while it is pausing destroys the standby data.
273
CHAPTER 17 A/D CONVERTER
■ Flow of Data Protection Function (When EI2OS is Used)
Figure 17.6-1 Flow of Data Protection Function (When EI2OS Is Used)
Setting EI 2OS
Starting continuous A/D conversion
Ending first conversion
Saving the result in the data register
Starting EI2 OS
Ending second conversion
End EI 2 OS?
NO
Pausing A/D conversion *
YES
YES
Saving the result in the data register
End EI2OS?
NO
Starting EI 2OS
Ending third conversion
Continued
Starting EI 2 OS
Ending the last conversion
Interrupt routine
End
Stooping A/D conversion
*: If the converter is restarted when it is pausing, standby conversion data is lost.
■ Notes on Using the Conversion Data Protection Function
To start the A/D converter upon an external trigger or internal timer, A/D activation factor bits STS1 and
STS0 of the ADCS2 register are used. Ensure that the input values of the external trigger or internal timer
are inactive. If the values are active, A/D conversion may start immediately.
When setting STS1 and STS0, ensure that "1" (input) is specified for ADTG and "0" (output) is specified
for the internal timer (timer 2).
274
CHAPTER 18
UART0
This chapter explains the UART0 functions and
operations.
18.1 Feature of UART0
18.2 UART0 Block Diagram
18.3 UART0 Registers
18.4 UART0 Operation
18.5 Baud Rate
18.6 Internal and External Clock
18.7 Transfer Data Format
18.8 Parity Bit
18.9 Interrupt Generation and Flag Set Timings
18.10 UART0 Application Example
275
CHAPTER 18 UART0
18.1
Feature of UART0
UART0 is a serial I/O port for asynchronous (start-stop) or CLK synchronous
communication with external devices.
■ Feature of UART0
UART0 has the following features.
• Full duplex double buffer
• Supports CLK synchronous and CLK asynchronous start-stop data transfer.
• Multiprocessor mode support (mode 2)
• Internally dedicated baud rate generator (12 types)
• Supports flexible baud rate setting using an external clock input or internal timer.
• Variable data length (7 to 9 bits, [no parity]; 6 to 8 bits [with parity]).
• Error detect function (framing, overrun, and parity)
• Interrupt function (receive and transmit interrupts)
• NRZ type transfer format
276
CHAPTER 18 UART0
18.2
UART0 Block Diagram
Figure 18.2-1 shows a block diagram of the UART0.
■ UART0 Block Diagram
Figure 18.2-1 Overall Block Diagram
Control signal
Receive interrupt
(to CPU)
Dedicated baud rate clock
SCK0
Transmit interrupt
(to CPU)
Transmit clock
16-bit reload timer 0
Clock select
circuit
Receive clock
SCK0
SIN0
Receive control circuit
Transmit control circuit
Start bit detect
circuit
Transmit start circuit
Receive bit counter
Transmit bit counter
Receive parity
counter
Transmit parity
counter
SOT0
Receive status
evaluation circuit
Transmit shifter
Receive shifter
Receive
complete
Transmit start
UIDR0
UODR0
Receive error
indication signal
for EI2OS (to CPU)
Internal data bus
UMC0
register
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
USR0
register
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
URD0
register
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
Control signal
277
CHAPTER 18 UART0
18.3
UART0 Registers
The UART0 has the following four registers:
• Serial mode control register
• Status register
• Input data register/output data register
• Rate and data register
■ UART0 Registers
Figure 18.3-1 UART0 Register
Serial mode control register 0
7
bit
PEN
Address: 000020H
Read/write
Initial value
Status register 0
bit
Read/write
Initial value
Input data register 0/
Output data register 0
278
2
1
0
SMDE
RFC
SCKE
SOE
(R/W) (R/W)
(0)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(W)
(1)
(R/W)
(0)
(R/W)
(0)
13
12
11
10
9
8
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
(R)
(R)
(0)
(0)
(R)
(0)
(R)
(1)
(R/W)
(0)
(R/W)
(0)
(R)
(0)
(R)
(0)
14
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
14
13
BCH
RC3
(R/W)
(0)
(R/W)
(0)
(R/W)
(X)
12
11
RC2
RC1
RC0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
10
UMC0
USR0
7
(R/W)
(X)
Read/write
Initial value
Read/write
Initial value
3
MC0
15
Address: 000022H
Address: 000023 H
4
MC1
bit
bit
5
SBL
RDRF
Address: 000021H
Rate and data register 0
6
9
8
BCH0
P
D8
(R/W)
(0)
(R/W)
(0)
(R/W)
(X)
UIDR0 (read)
UODR0 (write)
URD0
CHAPTER 18 UART0
18.3.1
Serial Mode Control Register 0 (UMC0)
UMC0 specifies the operation mode of UART0. Set the operation mode while operation
is halted. However, the RFC bit can be accessed during operation.
■ Serial Mode Control Register 0 (UMC0)
Figure 18.3-2 Serial Mode Control Register 0 (UMC0)
Serial mode control register 0
bit
7
6
5
4
3
2
1
0
Address: 000020 H
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(1)
(0)
UMC0
(0)
[bit7] PEN (Parity enable)
Specifies whether to add (for transmit) or detect (for receive) a parity bit in serial data I/O. Set to "0" in
mode 2.
0: Do not use parity
1: Use parity
[bit6] SBL (Stop bit length)
Specifies the number of stop bits for transmit data. For receive data, the first stop bit only is recognized
and any second stop bit is ignored.
0: 1 bit length
1: 2 bits length
[bit5, bit4] MC1, MC0 (Mode control)
These bits control the length of the transferred data. Table 18.3-1 lists the four transfer modes (data
lengths) selectable by these bits.
Table 18.3-1 UART0 Operation Modes
Mode
MC1
MC0
Data Length*1
0
0
0
7 (6)
1
0
1
8 (7)
2*2
1
0
8+1
3
1
1
9 (8)
*1: The figures enclosed in parentheses indicate the data length with parity.
*2: Mode 2 is used when a number of slave CPUs are connected to a single host CPU.
As the receive parity check function cannot be used, set PEN in the UMC0 register to "0"
(see Section "18.4 UART0 Operation" for details). The transmit data length is 9 bits and
no parity bit can be added.
279
CHAPTER 18 UART0
[bit3] SMDE (Synchronous mode enable)
This bit selects the transfer method.
0:Start-stop CLK synchronous transfer (clocked synchronous transfer using start and stop bits.)
1:Start-stop CLK asynchronous transfer
[bit2] RFC (Receiver flag clear)
Writing "0" to this bit clears the RDRF, ORFE, and PE flags in the USR0 register. Writing "1" has no
effect. Reading always returns "1".
Note:
When receive interrupts are enabled during UART0 operation, only write "0" to RFC when either
RDRF, ORFE, or PE is "1".
[bit1] SCKE (SCLK enable)
Writing "1" to this bit in CLK synchronous mode switches the port pin to the UART0 serial clock
output pin and outputs the synchronizing clock. Set to "0" in CLK asynchronous mode or external clock
mode.
0: The pin functions as a general purpose I/O port and does not output the serial clock. The pin
functions as the external clock input pin when the port is set to input mode (DDR=0) and RC3 to
RC0 are set to "1111B".
1: The pin functions as the UART0 serial clock output pin.
[bit0] SOE (Serial Output Enable)
Writing "1" to this bit switches the port pin to the UART0 serial data output pin, enabling serial output.
0: The pin functions as a port pin and does not output serial data.
1: The pin functions as the UART0 serial data output pin (SOT).
280
CHAPTER 18 UART0
18.3.2
Status Register 0 (USR0)
USR0 indicates the current state of the UART0 port.
■ Status Register 0 (USR0)
Figure 18.3-3 Status Register 0 (USR0)
Status register 0
bit
Address: 000021H
Read/write
Initial value
15
14
13
12
11
10
9
8
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
(R)
(R)
(0)
(0)
(R)
(0)
(R)
(1)
(R/W)
(0)
(R/W)
(0)
(R)
(0)
(R)
(0)
USR0
[bit15] RDRF (Receiver data register full)
This flag indicates the state of the UIDR0 (input data register). The flag is set when the receive data is
loaded into UIDR0. Reading UIDR0 or writing "0" to RFC in the UMC0 register clears the flag. If RIE
is active, a receive interrupt request is generated when RDRF is set.
0: No data in UIDR0
1: Data present in UIDR0
[bit14] ORFE (Over-run/framing error)
The flag is set when an overrun or framing error occurs in receiving. Writing "0" to RFC in the UMC0
register clears the flag. When this flag is set, the data in UIDR0 is invalid and the load from the receive
shifter to UIDR0 is not performed. If RIE is active, a receive interrupt request is generated when ORFE
is set.
0: No error
1: Error
Table 18.3-2 lists the UIDR0 states after receive completion by RDRF or ORFE.
Table 18.3-2 UIDR0 State after Receive Completion
RDRF
ORFE
UIDR0 Data State
0
0
Empty
0
1
Framing error
1
0
Valid data
1
1
Overrun error
The data in UIDR0 is invalid if an overrun or framing error has occurred. Next data can be received
after clearing the flag(s).
281
CHAPTER 18 UART0
[bit13] PE (Parity error)
The flag is set when a receive parity error occurs. Writing "0" to RFC in the UMC0 register clears the
flag. When this flag is set, the data in UIDR0 is invalid and the load from the receive shifter to UIDR0
is not performed. If RIE is active, a receive interrupt request is generated when PE is set.
0: No parity error
1: Parity error
[bit12] TDRE (Transmitter data register empty)
This flag indicates the state of the UODR0 (output data register). Writing transmit data to the UODR0
register clears the flag. The flag is set when the data is loaded to the transmit shifter and the
transmission is started. If TIE is active, a transmit interrupt request is generated when TDRE is set.
0: Data present in UODR0
1: No data in UODR0
[bit11] RIE (Receiver interrupt enable)
Enables receive interrupt requests.
0: Disable interrupts.
1: Enable interrupts.
[bit10] TIE (Transmitter interrupt enable)
Enables transmit interrupt requests. A transmit interrupt is generated immediately if transmit interrupts
are enabled when TDRE is "1".
0: Disable interrupts.
1: Enable interrupts.
[bit9] RBF (Receiver busy flag)
This flag indicates that UART0 is receiving input data. The flag is set when the start bit is detected and
cleared when the stop bit is detected.
0: Receiver idle
1: Receiver busy
[bit8] TBF (Transmitter busy flag)
This flag indicates that UART0 is transmitting input data. The flag is set when transmit data is written
to the UODR0 register and cleared when transmission completes.
0: Transmitter idle
1: Transmitter busy
282
CHAPTER 18 UART0
18.3.3
Input Data Register 0 (UIDR0) and Output Data Register 0
(UODR0)
UIDR0 (input data register 0) is the serial data input register. UODR0 (output data
register 0) is the serial data output register.
The most significant two bits (D7 and D6) are ignored if the data length is 6 bits and the
most significant bit (D7) is ignored if the data length is 7 bits. Write to UODR0 only
when TDRE = 1 in the USR0 register. Read UIDR0 only when RDRF = 1 in the USR0
register.
■ Input Data Register 0 (UIDR0) and Output Data Register 0 (UODR0)
Figure 18.3-4 Input Data Register 0 (UIDR0) and Output Register 0 (UODR0)
Serial input data register 0
Serial output data register 0
bit
Address: 000022 H
Read/write
Initial value
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
UIDR0 (read)
UODR0 (write)
283
CHAPTER 18 UART0
18.3.4
Rate and Data Register 0 (URD0)
URD0 selects the data transfer speed (baud rate) for UART0. The register also holds the
most significant bit (bit8) of the data when the transmit data length is 9 bits. Set the
baud rate and parity when UART0 is halted.
■ Rate and Data Register 0 (URD0)
Figure 18.3-5 Rate and Data Register 0 (URD0)
Rate and data register 0
bit
Address: 000023H
Read/write
Initial value
15
14
13
12
11
10
9
8
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(X)
URD0
[bit15, bit10] BCH, BCH0 (Baud rate clock change)
Specifies the machine cycles for the baud rate clock (see Section "18.4 UART0 Operation" for details).
Table 18.3-3 Clock Input Selection
BCH
BCH0
Divider ratio
Setting Example for Each Machine Cycle
0
0
-
- Prohibited setting -
0
1
Divide by 4
For a 16 MHz machine cycle: 16/4 = 4 MHz
1
0
Divide by 3
For a 12 MHz machine cycle: 12/3 = 4 MHz
1
1
Divide by 5
For a 10 MHz machine cycle: 10/5 = 2 MHz
Note:
Do not set BCH and BCH0 to "00B".
[bit14 to bit11] RC3 to RC0 (Rate control)
Selects the clock input for the UART0 port (see Section "18.4 UART0 Operation" for details).
Table 18.3-4 Clock Input Selection
RC3 to RC0
"0000B" to "1011B"
284
Clock Input
Dedicated baud rate generator
"1101B"
16-bit Reload Timer 0
"1111B"
External clock
CHAPTER 18 UART0
Note:
Do not set the rate control bits to "1100B" or "1110B".
[bit9] P
Sets even or odd parity when parity is active (PEN = 1).
0: Even parity
1: Odd parity
[bit8] D8
Holds the bit8 of the transfer data in mode 2 or 3 (9-bit data length) and no parity. Treated as bit8 of the
UIDR0 register for reading. Treated as bit8 of the UODR0 register for writing. The bit has no meaning
in the other modes. Write to D8 only when TDRE =1 in the USR0 register.
285
CHAPTER 18 UART0
18.4
UART0 Operation
Table 18.4-1 lists the operating modes for UART0. Set the UMC0 register to switch
between modes.
■ UART0 Operation Modes
Table 18.4-1 UART0 Operating Modes
Mode
Parity
Data Length
On
6
Off
7
On
7
Off
8
Off
8+1
On
8
Off
9
Clock Mode
Length of Stop Bits*
0
1
2
CLK asynchronous or CLK
synchronous
1 bit or 2 bits
3
*: The number of stop bits can only be set for transmission. The number of receive stop bits is always set to one.
Do not set modes other than those listed above. UART0 does not operate if an invalid mode is set.
Note:
UART0 uses start-stop clock synchronous transfer. Therefore, a start and stop bit are added to the
data even in clock synchronous transfer.
286
CHAPTER 18 UART0
18.5
Baud Rate
When the dedicated baud rate generator is used, the following two types of baud rates
are available:
• CLK synchronous baud rate
• CLK asynchronous baud rate
■ CLK Synchronous Baud Rate
The following 5 bits of URD0 register, BCH, BCH0, RC3, RC2 and RC1, select the baud rate for CLK
synchronous transfer.
First select the machine clock divider ratio using BCH and BCH0.
BCH
BCH0
0
1
=>
Divide by 4 [For example, at 16 MHz: 16/4 = 4 MHz]
1
0
=>
Divide by 3 [For example, at 12 MHz: 12/3 = 4 MHz]
1
1
=>
Divide by 5 [For example, at 10 MHz: 10/5 = 2 MHz]
Then, set the division ratio for the clock selected above in RC3, RC2, and RC1. The following three
settings are available for CLK synchronous transfer. Other settings are prohibited.
RC3
RC2
RC1
0
1
0
=>
Divide by 2 [For example, at 4 MHz: 4/2 = 2.0 M (bps)]
0
1
1
=>
Divide by 4 [For example, at 4 MHz: 4/4 = 1.0 M (bps)]
1
0
0
=>
Divide by 8 [For example, at 4 MHz: 4/8 = 0.5 M (bps)]
(At 2 MHz, the speed becomes half the above examples.)
287
CHAPTER 18 UART0
■ CLK Asynchronous Baud Rate
The following 6 bits of URD0 register, BCH, BCH0, RC3, RC2, RC1 and RC0, select the baud rate for
CLK asynchronous transfer.
First select the machine clock divider ratio using BCH and BCH0.
BCH
BCH0
0
1
=>
Divide by 4 [For example, at 16 MHz: 16/4 = 4 MHz]
1
0
=>
Divide by 3 [For example, at 12 MHz: 12/3 = 4 MHz]
1
1
=>
Divide by 5 [For example, at 10 MHz: 10/5 = 2 MHz]
Then, set the asynchronous transfer clock division ratio for the clock selected above in RC3, RC2, RC1,
and RC0. The following settings are available.
0
0
0
⇒ Divide by 8 × 1
0
1
0
⇒ Divide by 8 × 2
0
1
1
⇒ Divide by 8 × 4
1
0
0
⇒ Divide by 8 × 8
0
0
1
⇒ Not divided
1
0
1
⇒ Divide by 8
⎧
⎪
⎪
⎨
⎪
⎩
⎧
⎪
⎨
⎪
⎪
⎩
RC0
×
×
⎧
⎪
⎨ 0 ⇒ Divide by 12
⎪ 1 ⇒ Divide by 13
⎪
⎩
⎧
⎪
⎪
⎨
⎪
⎩
RC3 RC2 RC1
0 ⇒ Prohibited setting
1 ⇒ Divide by 8
The above 12 baud rates can be selected. The following formula shows how to calculate the CLK
synchronous baud rate.
Baud rate =
Baud rate =
Baud rate =
φ /4
2 m-1
φ/3
2 m-1
φ/5
2 m-1
[bps] (machine cycle = 16 MHz)
[bps] (machine cycle = 12 MHz)
[bps] (machine cycle = 10 MHz)
where φ is a machine cycle and m is in decimal notation for RC3 to 1.
Note:
The above formula for m=0 or m=1 cannot be calculated.
Data transfer is possible if the CLK asynchronous baud rate is in the range -1% to +1%. The baud
rate is the CLK synchronous baud rate divided by 8 x 13, 8 x 12, or 8.
Table 18.5-1 shows examples for 16 MHz, 12 MHz, and 10 MHz machine cycles. However, do not
use the settings marked as "-" in the table.
288
CHAPTER 18 UART0
Table 18.5-1 Baud Rate
CLK asynchronous (µs/Baud)
RC3
RC2
RC1
RC0
16 MHz
12 MHz
10 MHz
BCH/BCH0
=01
BCH/BCH0
=10
BCH/BCH0
=11
CLK synchronous (µs/Baud)
CLK
asynchronous
divider ratio
16 MHz
12 MHz
10 MHz
BCH/BCH0
=01
BCH/BCH0
=10
BCH/BCH0
=11
0
0
0
0
-
-
48/ 20833
8 x 12
-
-
-
0
0
0
1
26/ 38460
26/ 38460
52/ 19230
8 x 13
-
-
-
0
0
1
0
-
-
-
8
-
-
-
0
0
1
1
2/500000
2/500000
4/250000
8
-
-
-
0
1
0
0
48/ 20833
48/ 20833
96/10417
8 x 12
-
-
-
0
1
0
1
52/ 19230
52/ 19230
104/ 9615
8 x 13
0.5 / 2M
0.5 / 2M
1 / 1M
0
1
1
0
96/10417
96/10417
192/ 5208
8 x 12
-
-
-
0
1
1
1
104/ 9615
104/ 9615
208/ 4808
8 x 13
1 / 1M
1 / 1M
2 / 500k
1
0
0
0
192/ 5208
192/ 5208
-
8 x 12
-
-
-
1
0
0
1
208/ 4808
208/ 4808
416/ 2404
8 x 13
2 / 500k
2 / 500k
4 / 250k
1
0
1
0
-
-
-
8
-
-
-
1
0
1
1
16/ 62500
16/ 62500
32/ 31250
8
-
-
-
289
CHAPTER 18 UART0
18.6
Internal and External Clock
Setting RC3 to RC0 to "1101B" selects the clock signal from the 16-bit Reload Timer.
Setting RC3 to RC0 to "1111B" selects the external clock. The external clock frequency
has a maximum value of 2MHz.
■ Internal and External Clock
The CLK asynchronous baud rate is the CLK synchronous baud rate divided by 8. Also, data transfer is
possible if the CLK asynchronous baud rate is in the range -1% to +1% of the selected baud rate. Table
18.6-1 lists the baud rates when the internal timer is selected as the clock. The values in this table are
calculated for a machine cycle of 7.3728 MHz. However, do not use the settings marked as "-" in the table.
Baud rate=
φ/X
8 × 2 (n+1)
[bps]
⎛ φ: Machine cycle
⎜
⎜ X: Divider ratio for the count clock source for
⎜
the internal timer
⎜
⎝ n: Reload value (decimal)
⎞
⎟
⎟
⎟
⎟
⎠
Table 18.6-1 Baud Rate and Reload Value
Reload Value
Baud Rate
X = 21
(divide machine cycle by 2)
X = 23
(divide machine cycle by 8)
76800
2
-
38400
5
-
19200
11
2
9600
23
5
4800
47
11
2400
95
23
1200
191
47
600
383
95
300
767
191
The values in the table are the reload values (decimal) for reload count operation of the 16-bit Reload
Timer.
290
CHAPTER 18 UART0
18.7
Transfer Data Format
UART0 only handles NRZ (non-return-to-zero) type data. Figure 18.7-1 shows the
relationship between the transmit/receive clock and the data for CLK synchronous
mode.
■ Transfer Data Format
Figure 18.7-1 Transfer Data Format
SCK0
SIN0, SOT0
0
Start
1
LSB
0
1
1
0
0
1
0
MSB
1
1
⎫
Stop
Depends
D8 Stop ⎬ on the mode.
⎭
The transferred data is 01001101B (mode 1) or 101001101B (mode 3).
As shown in Figure 18.7-1 , the transfer data always starts with the start bit ("L" level data), the specified
number of data bits are transmitted with the LSB first, then transmission ends with the stop bit ("H" level
data). Always input a clock if external clock operation is selected. When an internal clock (the dedicated
baud rate generator or 16-bit Reload Timer) is selected, the clock is output continuously. When using CLK
synchronous transfer, do not start data transfer until the selected baud rate clock has stabilized (for two
baud rate clock cycles).
When using CLK asynchronous transfer, set the SCKE bit in the UMC0 register to "0" to disable clock
output. The transfer data format of SIN0 and SOT0 is the same as shown in Figure 18.7-1 .
291
CHAPTER 18 UART0
18.8
Parity Bit
The P bit in the URD0 register specifies whether to use even or odd parity when parity is
enabled. The PEN bit in the UMC0 register enables parity.
■ Parity Bit
Inputting the data shown in Figure 18.8-1 to SIN0 when even parity is set causes a receive parity error.
Figure 18.8-1 also shows the data transmitted when sending "001101B" with even parity and odd parity.
Figure 18.8-1 Serial Data with Parity Enabled
SIN0
(Receive parity error occurs P = 0)
0
Start
1
LSB
0
1
1
0
0
MSB
0
1
Stop
(Parity)
SOT0
(Even parity transmission P = 0)
0
Start
1
LSB
0
1
1
0
0
MSB
1
1
Stop
(Parity)
SOT0
(Odd parity transmission P = 1)
0
Start
1
LSB
0
1
1
0
0
MSB
0
(Parity)
292
1
Stop
CHAPTER 18 UART0
18.9
Interrupt Generation and Flag Set Timings
UART0 has two interrupt causes and six flags. The two interrupt causes are the receive
and transmit interrupts. The six flags are RDRF, ORFE, PE, TDRE, RBF, and TBF. For
reception, the RDRF, ORFE, and PE flags request an interrupt. For transmission, the
TDRE flag requests an interrupt.
■ Set Timings of the Six Flags
● RDRF flag
The RDRF flag is set when receive data is loaded into the UIDR0 register. The flag is cleared by writing
"0" to RFC in the UMC0 register or by reading the UIDR0 register.
● ORFE flag
The ORFE flag is an overrun or framing error flag. The flag is set when a receive error occurs and is
cleared by writing "0" to RFC in the UMC0 register.
● PE flag
The PE flag is a reception parity error flag. The flag is set when a receive parity error occurs and is cleared
by writing "0" to RFC in the UMC0 register. Note that the parity detect function is not available in mode 2.
● TDRE flag
The TDRE flag is set when the UODR0 register becomes empty and is available for writing. The flag is
cleared by writing to the UODR0 register. The above four flags (RDRF, ORFE, PE, and TDRE) trigger
transmit or receive interrupts.
● RBF and TBF flags
The RBF and TBF flags indicate that reception or transmission is in progress. The RBF flag becomes active
during reception, and the TBF flag becomes active during transmission.
293
CHAPTER 18 UART0
18.9.1
Flag Set Timings for a Receive Operation
(in Mode 0, 1, or 3)
The RDRF, ORFE, and PE flags are set and an interrupt request to the CPU generated
when the final stop bit is detected indicating the end of reception transfer. The data in
UIDR0 is invalid when either the ORFE or PE bit is active.
■ Flag Set Timings for a Receive Operation (in Mode 0, 1, or 3)
Figure 18.9-1 , Figure 18.9-2 , and Figure 18.9-3 show the set timings of the RDRF, ORFE, and PE flags
respectively.
Figure 18.9-1 RDRF Set Timing (Mode 0, 1, or 3)
Data
Stop
(Stop)
RDRF
Receive interrupt
Figure 18.9-2 ORFE Set Timing (Mode 0, 1, or 3)
Data
Stop
Data
RDRF = 1
RDRF = 0
ORFE
ORFE
Receive interrupt
Stop
Receive interrupt
(Overrun error)
(Framing error)
Figure 18.9-3 PE Set Timing (Mode 0, 1, or 3)
Data
PE
Receive interrupt
294
Stop
(Stop)
CHAPTER 18 UART0
18.9.2
Flag Set Timings for a Receive Operation (in Mode 2)
The RDRF flag is set when the final stop bit is detected and reception transfer ends with
the last data bit (D8) having the value "1".
The ORFE flag is set when the final stop bit is detected, irrespective of the value of the
last data bit (D8). The data in UIDR0 is invalid when the ORFE bit is active.
The interrupt request to the CPU is generated when either of the flags are set (see
Section "18.10 UART0 Application Example" for details on using mode 2).
■ Flag Set Timings for a Receive Operation (in Mode 2)
Figure 18.9-4 RDRF Set Timing (Mode 2)
Data
D7
D6
D8
Stop
(Stop)
RDRF
Receive interrupt
Figure 18.9-5 ORFE Set Timing (Mode 2)
Data
D7
D8
Stop
Data
RDRF = 1
RDRF = 0
ORFE
ORFE
Receive interrupt
D7
D8
Stop
Receive interrupt
(Overrun error)
(Framing error)
295
CHAPTER 18 UART0
18.9.3
Flag Set Timings for a Transmit Operation
TDRE is set and an interrupt request to the CPU is generated when the data written in
UODR0 register is transferred to the internal shift register and the next data can be
written to UODR0.
■ Flag Set Timings for a Transmit Operation
Figure 18.9-6 TDRE Set Timing (Mode 0)
UODR0 write
TDRE
Interrupt request to the CPU
Transmit interrupt
SOT0 output
ST D0
D1
ST: Start bit
296
D2 D3
D4
D5 D6
D0 to D7: Data bits
D7
SP SP
SP: Stop bit
ST D0
D1
D2 D3
CHAPTER 18 UART0
18.9.4
Status Flag During Transmit and Receive Operation
RBF is set when the start bit is detected and cleared when a stop bit is detected. The
receive data in UIDR0 at the RBF clear timing is not yet valid. The data in UIDR0
becomes valid at the RDRF set timing.
■ Status Flag during Transmit and Receive Operation
Figure 18.9-7 shows the relationship between the RBF and receive interrupt flag timing.
Figure 18.9-7 RBF Set Timing (Mode 0)
SIN0 input
ST D0
D1
D2 D3
D4
D5 D6
D7
SP
RBF
RDRF, PE, ORFE
Writing the transmission data to UODR0 sets TBF. TBF is cleared when transmission completes.
Figure 18.9-8 TBF Set Timing (Mode 0)
UODR write
SOT0 output
ST D0
D1
D2 D3
D4
D5 D6
D7
SP SP
TBF
Note:
Receive operation starts after releasing a reset unless the SIN0 input pin is fixed at "1". Therefore,
before setting the mode, write "0" to RFC in the UMC0 register to clear any receive flags that have
been set.
Set the communication mode when the RBF and TBF flags in the USR0 register are "0". The data
transmitted and received during mode setting cannot be guaranteed.
■ EI2OS (Extended Intelligent I/O Service)
See Section "3.6 Extended Intelligent I/O Service (EI2OS)" for details about the extended intelligent I/O
service (EI2OS).
297
CHAPTER 18 UART0
18.10
UART0 Application Example
Mode 2 is used when a number of slave CPUs are connected to a host CPU (see Figure
18.10-1 .)
■ Application Example of UART0
As shown in Figure 18.10-1 , communication starts with the host CPU transmitting address data. The ninth
bit (D8) of the address data is set to "1". The address selects the slave CPU with which communication will
be established. The selected slave CPU communicates with the host CPU using a protocol determined by
the user. In normal data, D8 is set to "0". Unselected slave CPUs wait in standby until the next
communication session starts. Figure 18.10-2 shows a flowchart of operation in this mode.
Because the parity check function is not available in this mode, set the PEN bit in the UMC0 register to "0".
Figure 18.10-1 Example System Configuration Using Mode 2
SOT0
SIN0
Host CPU
SOT0
SIN0
Slave CPU #0
298
SOT0
SIN0
Slave CPU #1
CHAPTER 18 UART0
Figure 18.10-2 Communication Flowchart for Mode 2 Operation
(Host CPU)
Start
(Slave CPU)
Start
Set the transfer mode to "3"
Set the transfer mode to "2"
Set the slave CPU selection
in D0 to D7. Set D8 to "1".
Transfer the byte.
Receive a byte
NO
Selected?
Set D8 to "0" and perform
communications
End
YES
Set the transfer mode to "3"
and enable SOT0 output
Perform communications
with the master CPU
Use the status flag to
confirm transfer completion,
then set the transfer mode to
"2" and disable SOT0 output
299
CHAPTER 18 UART0
300
CHAPTER 19
UART1 (SCI)
This chapter explains the UART1 (SCI) functions and
operation.
19.1 Features of UART1
19.2 Block Diagram of UART1
19.3 UART1 Registers
19.4 UART1 Operating Modes and Clock Selection
19.5 UART1 Flags and Interrupt Sources
19.6 UART1 Interrupts and Flag Set Timing
19.7 Negative Clock Operation
19.8 UART1 Sample Applications and Precautionary Information
301
CHAPTER 19 UART1 (SCI)
19.1
Features of UART1
The UART1 is a serial I/O port used for asynchronous (start-stop synchronized)
communication as well as for CLK-synchronized communication.
■ Features of UART1
UART provides the following features.
• Full-duplex double buffer
• Asynchronous (start-stop synchronized) and CLK-synchronous communication capability
• Multi-processor mode support
• On-chip dedicated baud rate generator
• Automatic baud rate setting from external clock input or internal timer
• Error detection function (parity, framing, overrun)
• Transfer communication in NRZ transfer format
• Intelligent I/O service support
302
CHAPTER 19 UART1 (SCI)
19.2
Block Diagram of UART1
Figure 19.2-1 shows block diagram of the UART1.
■ Block Diagram of UART1
Figure 19.2-1 Block Diagram of UART1
Control signals
Receive interrupt
(to CPU)
Dedicated baud
rate generator
16-bit reload timer 0
SCK1
Transmit clock
Clock
selector
circuit
Transmit
interrupt
(to CPU)
Receive clock
External clock
SIN1
Receive control circuit
Transmit control circuit
Start bit detect circuit
Transmit start circuit
Receive bit counter
Transmit bit counter
Receive parity counter
Transmit parity counter
SOT1
Receive status decision circuit
Receive shifter
Transmit shifter
Receive
complete
Transmit
Start
SIDR1
SODR1
2 OS
receive error
EI
indication signal (to CPU)
Internal data bus
SMR1
register
MD1
MD0
CS2
CS1
CS0
UPCL
SCKE
SOE
SCR1
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR1
register
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
Control bus
303
CHAPTER 19 UART1 (SCI)
19.3
UART1 Registers
Figure 19.3-1 lists the UART1 registers.
■ UART1 Registers
Figure 19.3-1 UART1 Register Configuration
bit
15
8
7
0
SCR1
SMR1
(R/W)
SSR1
SIDR1(R)/SODR1(W)
(R/W)
–
U1CDCR
8bit
8bit
(R/W)
Figure 19.3-2 UART1 Registers
Serial mode register 1
Address: 000024H
7
MD1
6
MD0
5
CS2
4
CS1
3
CS0
2
1
SCKE
UPCL
0
SOE
Read/write
Initial value
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
13
SBL
12
CL
11
A/D
10
REC
9
RXE
8
TXE
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(W)
(1)
(R/W)
(0)
(R/W)
(0)
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
Address: 000027H
15
PE
14
ORE
13
FRE
12
11
RDRF TDRE
10
BDS
9
RIE
8
TIE
Read/write
Initial value
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(1)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
UART1 Prescaler control register
bit 7
6
MD
–
Address: 000028H
5
–
4
–
3
DIV3
2
DIV2
1
DIV1
0
DIV0
(-)
(-)
(-)
(-)
(-)
(-)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
bit
Serial control register 1
bit 15
Address: 000025H
PEN
Read/write
Initial value
(R/W)
(0)
Serial input data register 1/
Serial output data register 1
bit 7
Address: 000026H
D7
Read/write
Initial value
Serial status register 1
bit
Read/write
Initial value
304
(R/W)
(0)
14
P
SMR1
SCR1
SIDR1(Read)
SODR1(Write)
SSR1
U1CDCR
CHAPTER 19 UART1 (SCI)
19.3.1
Serial Mode Register 1 (SMR1)
The serial mode register 1 (SMR1) sets the operating mode of the UART1. Operating
mode settings should be entered when the unit is not in operation. Do not write to this
register during operation.
■ Serial Mode Register 1 (SMR1)
The SMR1 register has the following bit configuration.
Figure 19.3-3 Serial Mode Register 1(SMR1)
Serial Mode Register 1
bit
Address: 000024H
Read/write
Initial value
7
MD1
6
MD0
5
CS2
4
CS1
3
CS0
2
UPCL
1
SCKE
0
SOE
(R/W) (R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
SMR1
[bit7, bit6] MD1, MD0 (MoDe select)
These bits select the UART1 operation mode, according to the settings listed in Table 19.3-1 .
Table 19.3-1 Operating Mode Selections
Mode
MD1
MD0
Operating mode
0
0
0
Asynchronous (start-stop synchronized) normal mode
1
0
1
Asynchronous (start-stop synchronized) multi-processor mode
2
1
0
CLK synchronous mode
—
1
1
Prohibited
Note:
Mode 1, Asynchronous (start-stop synchronized) multi-processor mode, is used when one host CPU
is connected to multiple slave CPUs. This UART1 resource is not able to determine the data format
of incoming data, and therefore in asynchronous (start-stop synchronized) multi-processor mode
supports only the master processor.
Also, in this configuration the receive parity check function cannot be used, and therefore the PEN
bit in the UMC1 register should be set to "0".
305
CHAPTER 19 UART1 (SCI)
[bit5 to bit3] CS2 to CS0 (Clock Select)
These bits select the baud rate clock source. The baud rate is determined at the same time as selection of
the baud rate generator. Table 19.3-2 shows the clock input selection settings.
Table 19.3-2 Clock Input Selection Settings
CS2 to CS0
Clock input
000B to 101B
Dedicated baud rate generator
110B
Internal timer *
111B
External clock
*: When the internal timer is selected, the MB90440G series selects 16-bit reload timer 0 output.
[bit2] UPCL (UART programmable clear)
If "1" is written to this bit, all registers of UART1 will be reset. Writing "0" has no effect.
[bit1] SCKE (SCLK Enable)
For communication in CLK synchronous mode (mode 2), this bit determines whether the SCK1 pin is
used as a clock input pin or a clock output pin.
In CLK asynchronous modes or external clock mode, this bit should be set to "0".
0: SCK1 pin functions as clock input pin
1: SCK1 pin functions as clock output pin
Note:
When the pin functions as a clock input, an external clock source must be selected.
[bit0] SOE (Serial Output Enable)
This bit determines whether external pins that also can be used as general purpose I/O port pins will
function as serial output pins (SOT1) or as I/O port pins.
0: General purpose I/O port pin function
1: Serial data output pin (SOT1) function
306
CHAPTER 19 UART1 (SCI)
19.3.2
Serial Control Register 1 (SCR1)
The serial control register 1 (SCR1) register controls the transfer protocol used for
serial transmission.
■ Serial Control Register 1 (SCR1)
The SCR1 register has the following bit configuration.
Figure 19.3-4 Serial Control Register 1 (SCR1)
Serial Control Register 1
Address: 000025H
bit 15
PEN
Read/write
Initial value
(R/W)
(0)
14
P
(R/W)
(0)
13
SBL
12
CL
(R/W) (R/W)
(0)
(0)
11
A/D
10
REC
9
RXE
8
TXE
(R/W)
(0)
(W)
(1)
(R/W)
(0)
(R/W)
(0)
SCR1
[bit15] PEN (Parity Enable)
This bit determines whether parity bits are attached to data in serial transmission.
0: No parity
1: Parity
Note:
Parity bit attachment is available only in asynchronous (start-stop synchronized) normal mode (mode
0). In asynchronous (start-stop synchronized) multi-processor mode (mode 1) and all CLKsynchronous mode (mode 2), no parity bits may be attached.
[bit14] P (Parity)
This bit selects even or odd parity for data communications in which a parity bit is used.
0: Even parity
1: Odd parity
[bit13] SBL (Stop Bit Length)
This bit sets the length of the stop bit that marks the frame end in asynchronous (start-stop
synchronized) communication.
0: 1 stop bit
1: 2 stop bits
[bit12] CL (Character Length)
This bit sets the data length of one frame.
0: 7-bit data
1: 8-bit data
307
CHAPTER 19 UART1 (SCI)
Note:
7-bit data handling is available only in asynchronous (start-stop synchronized) normal mode (mode
0). In asynchronous (start-stop syncronized) multi-processor mode (mode 1) and CLK-synchronous
mode (mode 2), 8-bit data should be used.
[bit11] A/D (Address/Data)
This bit determines the data format of transmit frames in asynchronous (start-stop synchronized)
communication in multi-processor mode (mode 1).
0: Data frame
1: Address frame
[bit10] REC (Receiver Error Clear)
This bit clears the error flags (PE, ORE, FRE) in the SSR1 register.
A write value of "1" is not valid, and the read value is "1" at all times.
[bit9] RXE (Receiver Enable)
This bit controls UART1 receiver operations.
0: Receiver operation prohibited
1: Receiver operation enabled
Note:
If receiver operation is prohibited while reception is in progress (while data is present in the receive
shift register), the receiver will not stop operating until reception of the current frame is completed,
and the data has been stored in the receive data buffer SIDR1 register.
[bit8] TXE (Transmit Enable)
This bit controls UART1 transmit operation.
0: Transmit operation prohibited
1: Transmit operation enabled
Note:
If transmit operation is prohibited while transmission is in progress (while data is being output from
the transmit register), the transmitter will not stop operating until there is no more data remaining in
the transmit data buffer SODR1 register.
After data is written into SODR1 register, wait for the time described in the following before writing
"0". The wait time should be one sixteenth that of the baud-rate when in clock asynchronous transfer
mode, and equivalent to that of the baud-rate when in clock synchronous transfer mode.
308
CHAPTER 19 UART1 (SCI)
19.3.3
Serial Input Data Register 1 (SIDR1) / Serial Output Data
Register 1 (SODR1)
These registers function as receive and transmit data buffer registers.
■ Serial Input Data Register 1 (SIDR1) / Serial Output Data Register 1 (SODR1)
The SIDR1 and SODR1 registers have the following bit configuration.
Figure 19.3-5 Serial Input Data Register 1 (SIDR1)/Serial Output Data Register 1 (SODR1)
Serial input data register 1/
Serial output data register 1
7
bit
Address: 000026H
D7
Read/write
Initial value
(R/W)
(X)
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(R/W)
(X)
(X)
(R/W)
(X)
SIDR1 (read)/
SODR1 (write)
The serial input data register 1 (SIDR1) functions as a data buffer register for receiving serial data. The
serial output data register 1 (SODR1) functions as a data buffer register for transmitting serial data. When
using 7-bit data length, the top bit (D7) contains invalid data. Be sure the TDRE bit in the SSR1 register is
set to "1" before writing to the SODR1 register.
Note:
Writing to these addresses refers to writing to the SODR1 register, and reading refers to reading
from the SIDR1 register.
309
CHAPTER 19 UART1 (SCI)
19.3.4
Serial Status Register 1 (SSR1)
The serial status register 1 (SSR1) is composed of flags that indicate the operating
status of the UART1.
■ Serial Status Register 1 (SSR1)
The SSR1 register has the following bit configuration.
Figure 19.3-6 Serial Status Register 1 (SSR1)
Serial Status Register 1
bit 15
PE
Address: 000027H
Read/write
Initial value
(R)
(0)
14
ORE
13
FRE
12
RDRF
11
TDRE
10
BDS
9
RIE
8
TIE
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(1)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
SSR1
[bit15] PE (Parity Error)
This interrupt request flag is set when a parity error occurs during receive. Once set, this flag is cleared
by writing "0" to the REC bit (bit10) in the SCR1 register.
When this bit is set, data in the SIDR1 register is invalid.
0: No parity error
1: Parity error occurred
[bit14] ORE (Over Run Error)
This interrupt request flag is set when an overrun error occurs during receive. Once set, this flag is
cleared by writing ‘0" to the REC bit (bit10) in the SCR1 register.
When this bit is set, data in the SIDR1 register is invalid.
0: No overrun error
1: Overrun error occurred
[bit13] FRE (Framing Error)
This interrupt request flag is set when a framing error occurs during receive. Once set, this flag is
cleared by writing ‘0" to the REC bit (bit10) in the SCR1 register.
When this bit is set, data in the SIDR1 register is invalid.
0: No framing error
1: Framing error occurred
[bit12] RDRF (Receiver Data Register Full)
This interrupt request flag is set to indicate that data is present in the SIDR1 register.
This flag is set when receive data is loaded into the SIDR1 register, and is automatically cleared when
the data is read from the SIDR1 register.
0: No receive data
1: Receive data present
310
CHAPTER 19 UART1 (SCI)
[bit11] TDRE (Transmit Data Register Empty)
This interrupt request flag is set to indicate that outgoing data can be written to the SODR1 register.
This flag is cleared when outgoing data is written to the SODR1 register. It is then reset when the
written data starts loading into the transmit shifter to indicate that the next data can be written to the
SODR1 register.
0: Prohibits writing of send data
1: Enables writing of send data
[bit10] BDS (Transfer direction selection)
This bit selects whether to transfer serial data from the last significant bit (LSB first, BDS=0) or the
most significant bit (MSB first, BDS=1).
0: LSB first
1: MSB first
Note:
The high-order and low-order sides of serial data are interchanged with each other during reading
from or writing to the serial data register. If this bit is set to another value after the data is written to
the SIDR1 register, the data becomes invalid.
[bit9] RIE (Receiver Interrupt Enable)
This bit controls receiver interrupts.
0: Interrupt prohibited
1: Interrupt enabled
Note:
Receiver interrupt sources include PE, ORE and FRE errors, as well as normal receive as indicated
by the RDRF flag.
[bit8] TIE (Transmit Interrupt Enable)
This bit controls transmit interrupts.
0: Interrupt prohibited
1: Interrupt enabled
Note:
Transmit interrupt sources include transmission requests indicated by the TDRE flag.
311
CHAPTER 19 UART1 (SCI)
19.3.5
UART1 Prescaler Control Register (U1CDCR)
The prescaler control register (U1CDCR) controls the machine clock frequency divider.
The UART1 operating clock signal can be generated by dividing the machine clock
signal pulse. The prescaler is designed to enable constant baud rates from a variety of
machine clock speeds.
The output from the prescaler is used by the I/O expanded serial interface.
■ UART1 Prescaler Control Register (U1CDCR)
The U1CDCR register has the following bit configuration.
Prescaler control register
7
6
5
4
3
2
1
0
MD
–
–
–
DIV3
DIV2
DIV1
DIV0
(R/W)
(0)
(-)
(-)
(-)
(-)
(-)
(-)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
bit
Address: 000028 H
Read/write
Initial value
U1CDCR
[bit7] MD (Machine clock divide Mode select)
This bit enables the prescaler operation.
0: Prescaler stopped
1: Prescaler operating
[bit3 to bit0] DIV3 to DIV0 (DIVide 3 to DIVide0)
These bits determine the division of the machine clock frequency as shown in Table 19.3-3 .
Table 19.3-3 Machine Clock Division Ratios
DIV3
DIV2
DIV1
DIV0
Division ratio*
0
0
0
0
Divide by 1
0
0
0
1
Divide by 2
0
0
1
0
Divide by 3
0
0
1
1
Divide by 4
0
1
0
0
Divide by 5
0
1
0
1
Divide by 6
0
1
1
0
Divide by 7
0
1
1
1
Divide by 8
*: After changing the division ratio, allow an interval of two cycles for the clock frequency to stabilize
before starting communication.
312
CHAPTER 19 UART1 (SCI)
19.4
UART1 Operating Modes and Clock Selection
The UART1 has two types of operating mode, asynchronous mode and CLKsynchronous mode. Changes of mode are controlled by settings in the SMR1 register
and SCR1 register.
■ UART1 Operating Modes
Table 19.4-1 shows the UART1 operating modes.
Table 19.4-1 UART1 Operating Modes
Mode
Parity bit
Data
length
Y/N
7
Y/N
8
0
Operating mode
Stop bit length
Asynchronous (start-stop
synchronized) normal
mode
1-bit or 2-bit
1
N
8+1
Asynchronous (start-stop
synchronized) multiprocessor mode
2
N
8
CLK synchronous mode
N
Note:
In asynchronous (start-stop synchronized) normal mode, stop bit length can be set for outgoing
transmission only. For receive, the setting is always 1-bit length. The unit does not operate in modes
other than those shown, and only these settings should be used.
313
CHAPTER 19 UART1 (SCI)
■ UART1 Clock Selection
● Dedicated baud rate generator
When the dedicated baud rate generator is selected, the baud rate settings listed in Table 19.4-2 and Table
19.4-3 are available. Also, prescaler settings are shown in Table 19.4-4 .
φ in the tables indicates the machine clock.
Table 19.4-2 Baud Rates (Asynchronous communication)
CS2
CS1
CS0
φ/div=1MHz
φ/div=2MHz
φ/div=4MHz
φ/div=8MHz
Calculation formula
0
0
0
4808
9615
19230
38460
(φ/div) / (8×13×2)
0
0
1
2404
4808
9615
19230
(φ/div) / (8× 3×22)
0
1
0
1202
2404
4808
9615
(φ/div) / (8×13×23)
0
1
1
601
1202
2404
4808
(φ/div) / (8×13×24)
1
0
0
31250
62500
125k
250k
(φ/div) / 25
1
0
1
15625
31250
62.5k
125k
(φ/div) / 26
Table 19.4-3 Baud Rates (CLK-synchronized communication)
CS2
CS1
CS0
φ/div=1MHz
φ/div=2MHz
φ/div=4MHz
φ/div=8MHz
Calculation formula
0
0
0
1M
2M
-
-
(φ/div) / 20
0
0
1
500k
1M
2M
-
(φ/div) / 21
0
1
0
250k
500k
1M
2M
(φ/div) / 22
0
1
1
125k
250k
500k
1M
(φ/div) / 23
1
0
0
62500
125k
250k
500k
(φ/div) / 24
1
0
1
31250
62500
125k
250k
(φ/div) / 25
314
CHAPTER 19 UART1 (SCI)
Table 19.4-4 Prescaler Settings
Recommended machine
clock speed φ (MHz)
div
DIV3
DIV2
DIV1
DIV0
4
4
0
0
1
1
6
6
0
1
0
1
8
8
0
1
1
1
6
3
0
0
1
0
8
4
0
0
1
1
10
5
0
1
0
0
12
6
0
1
0
1
14
7
0
1
1
0
16
8
0
1
1
1
8
2
0
0
0
1
12
3
0
0
1
0
16
4
0
0
1
1
16
2
0
0
0
1
φ/div (MHz)
1
2
4
8
315
CHAPTER 19 UART1 (SCI)
● Internal timer
When bits CS2 to CS0 are set to "110B", the internal timer signal is selected, and the 16-bit (timer0)
operates in reload mode. In this case, baud rates are determined as follows.
Asynchronous (start-stop synchronized): (φ / N) / (16 × 2 × (n + 1))
CLK synchronous: (φ / N) / (2 × (n + 1))
N: timer count clock source
n: timer reload value
Table 19.4-5 shows the relation between baud rates and reload values (decimal values) at a machine cycle
speed of 7.3728MHz.
Table 19.4-5 Baud Rates and Reload Values
Reload value
Baud rate
N=21
(machine cycle division by 2)
N=23
(machine cycle division by 8)
38400
2
—
19200
5
—
9600
11
2
4800
23
5
2400
47
11
1200
95
23
600
191
47
300
383
95
When selecting the internal timer (16-bit timer0) as the baud rate clock source, note that the 16-bit timer0
output signal TOT0 is already connected to the MB90440G controller internally. Therefore, it is not
necessary to make an external connection from the 16-bit timer0 external output pins TOT0 to the UART1
external clock input pin SCK1. Also, this means that unless used in some other fashion, the timer pins are
available for use as I/O port pins.
● External clock
When bits CS2 to CS0 are set to "111B" the external clock source is selected and baud rates are determined
by the following formula, in which f represents the external clock frequency.
Asynchronous (start-stop synchronized) mode: f/16
CLK synchronous: f
Note that f has a maximum value of 2MHz.
316
CHAPTER 19 UART1 (SCI)
19.4.1
Asynchronous (Start-Stop Synchronized) Mode
The UART1 handles only data in NRZ (non-return to zero) format.
■ Asynchronous (Start-Stop Synchronized) Mode Data Transfer Format
Figure 19.4-1 shows transfer data format.
Figure 19.4-1 Asynchronous (Start-Stop Synchronized) Mode Data Transfer Format (Mode 0, 1)
SIN1,SOT1
0 1 0
Start LSB
1
1
0
0
1
0 1 1
MSB Stop
........(Mode 0)
A/D Stop........(Mode 1)
Transferred data "01001101B "
As shown in Figure 19.4-1 , transfer data must begin with a start bit ("L" level data value), followed by data
of the designated bit-length, and ending with a stop bit ("H" level data value). When an external clock
signal is selected, the clock should be input at all times.
In normal mode (mode 0), data length may be set to 7 bits or 8 bits, however in multi-processor mode
(mode 1) the data length must be 8 bits. Also, no parity bit may be attached in multi-processor mode.
Instead, an A/D bit must be attached.
■ Asynchronous (Start-Stop Synchronized) Mode Receive Operation
Whenever the RXE bit (bit9) in the SCR1 register is set to "1", UART1 is receiving.
Appearance of a start bit on the receive line allows one frame of data to be received in the data format
determined by the SCR1 register. After the frame is received, error flags are set if the corresponding errors
have occurred, and then the RDRF flag (SST register bit12) is set. If the RIE bit (bit9) in the SSR1 register
is set to "1", a receive interrupt is sent to the CPU. The CPU checks each flag in the SSR1 register and
reads the SIDR1 register to see if the data has been received correctly. If any errors have occurred, take the
required action.
The RDRF flag is cleared when the SIDR1 register is read.
■ Asynchronous (Start-Stop Synchronized) Mode Transmit Operation
Whenever the TDRE flag (bit11) in the SSR1 register is set to "1" the UART1 is writing outgoing data to
the SODR1 register. If the TXE bit (bit8) is set to "1" transmit operation is in progress.
As soon as data in the SODR1 register starts to be transferred to the transmit shift register for transmission,
the TDRE flag is reset. This enables the next unit of outgoing data to be placed in the SODR1 register. At
this time if the TIE bit (bit8) in the SSR1 register is set to "1" a transmission interrupt is sent to the CPU,
causing outgoing data to be placed into the SODR1 register.
The TDRE flag is momentarily cleared each time data is placed into the SODR1 register.
317
CHAPTER 19 UART1 (SCI)
19.4.2
CLK Synchronous Mode
The UART1 handles only data in NRZ (non-return to zero) format.
■ CLK Synchronous Mode Data Transfer Format
Figure 19.4-2 shows the relation between the transmit and receive clock and data in CLK synchronous
mode.
Figure 19.4-2 CLK Synchronous Mode Data Transfer Format (Mode 2)
SODR1 write
Mark
SCLK
RXE,TXE
SIN1,SOT1
1
LSB
0
1
1
0
0
1
0
MSB...................(Mode 2)
Transferred data "01001101B"
When an internal clock signal source (dedicated baud rate generator or internal timer) is selected, a receive
clock signal is automatically generated each time data is transmitted.
When an external clock source is selected it is necessary to provide an accurate 1-byte clock signal after
data is confirmed present in the transmit data buffer register SODR1 (indicated by the TDRE flag =0). Note
also that the signal must return to mark level before and after transmit operation.
Data length is 8-bit only, and no parity bit may be attached. Also, there is no start/stop bit so that no error
detection is enabled except for overrun errors.
318
CHAPTER 19 UART1 (SCI)
■ Control Register Settings for CLK Synchronous Mode
When using CLK synchronous mode, the following settings are made to each of the control registers.
● SMR1 register
MD1, MD0:
10B
CS2, CS1, CS0: Indicate clock input
SCKE:
"1" for dedicated baud rate generator or internal timer, "0" for external clock
SOE:
"1" to send, "0" to receive only
● SCR1 register
PEN:
"0"
P, SBL, A/D: These bits have no significance
CL:
"1"
REC:
"0" (to initialize)
RXE, TXE: At least one must be "1"
● SSR1 Register
RIE: "1" if interrupts are used, "0" if interrupts are not used
TIE: "0"
■ Start of Communication in CLK Synchronous Mode
Communication starts by writing to the SODR1 register. Even if data is to be only received (not sent), it is
first necessary to write dummy data to the SODR1 register.
■ End of Communication in CLK Synchronous Mode
The end of communication can be verified by the change of the RDRF flag in the SSR1 register to "1". To
determine whether the communication was performed normally, read the ORE bit in the SSR1 register.
319
CHAPTER 19 UART1 (SCI)
19.5
UART1 Flags and Interrupt Sources
The UART1 has five flags, PE, ORE, FRE, RDRF and TDRE, and two interrupt sources,
one for transmit and one for receive.
■ UART1 Flags
The five flags are the PE, ORE, FRE, RDRF and TDRE flags. The first three are set when transmit errors
occur, the PE flag for a parity error, the ORE flag for an overrun error, and the FRE flag for a framing
error, and are released by writing "0" to the REC bit in the SCR1 register. The RDRF flag is set when
receive data is loaded into the SIDR1 register, and cleared when the data is read out of the SIDR1 register.
Note however that there is no parity detect function in mode 1, and no parity detect function or framing
error detect function in mode 2. The TDRE flag is set when the SODR1 register is empty and ready for data
write access, and is cleared when data is written to the SODR1 register.
■ UART1 Interrupt Sources
The UART1 has two interrupt sources, one for receive and one for transmit. During receive, interrupt
requests are initiated by setting the PE, ORE, FRE or RDRF flags. During transmit, interrupt requests are
initiated by setting the TDRE flag.
Interrupt flag set timing in each operating mode is described in section "19.6 UART1 Interrupts and Flag
Set Timing".
320
CHAPTER 19 UART1 (SCI)
19.6
UART1 Interrupts and Flag Set Timing
This section describes the timing of interrupts and flag setting in each UART1 operating
mode.
■ UART1 Interrupts and Flag Set Timing
● Mode 0 Receive
The PE, ORE, FRE and RDRF flags are set and the interrupt request signal is sent to the CPU following the
end of a receive transfer, when the final stop bit is detected. If any one of the PE, ORE or FRE flags is
active, the data in the SIDR1 register will be invalid.
Figure 19.6-1 shows the timing of the PE, ORE, FRE, and RDRF flags (mode 0).
Figure 19.6-1 PE, ORE, FRE, RDRF Flag Set Timing (Mode 0)
Data
D6
D7
Stop
PE,ORE,FRE
RDRF
Receiving interrupt
● Mode 1 Receive
The ORE, FRE and RDRF flags are set and the interrupt request signal is sent to the CPU after the end of a
receive transfer, when the final stop bit is detected. Also, if the receive data length is 8 bits, the 9th bit
indicating address/data will be invalid. If either the ORE or FRE flags is active, the data in the SIDR1
register will be invalid.
Figure 19.6-2 shows the timing of the ORE, FRE, and RDRF flags (mode 1).
Figure 19.6-2 ORE, FRE, RDRF Flag Set Timing (Mode 1)
Data
D7
Address/data
Stop
ORE,FRE
RDRF
Receiving interrupt
321
CHAPTER 19 UART1 (SCI)
● Mode 2 Receive
The ORE and RDRF flags are set and the interrupt request signal is sent to the CPU after the end of a
receive transfer, when the final data (D7) is detected. If the ORE flag is active, the data in the SIDR1
register will be invalid.
Figure 19.6-3 shows the timing of the ORE and RDRF flags (mode 2).
Figure 19.6-3 ORE, RDRF Flag Set Timing (Mode 2)
Data
D5
D6
D7
ORE
RDRF
Receiving interrupt
● Mode 0, Mode 1, and Mode 2 Transmit
The TDRE flag is cleared when data is written to the SODR1 register. The TDRE flag is set (and an
interrupt request sent to the CPU) as soon as the data in the SODR1 register is transferred to the internal
shift register, to ready the SODR1 register for the next data write cycle. During a transmit operation, if "0"
is written to the TXE bit in the SCR1 register (including the RXE bit in mode 2), the TDRE bit in the SSR1
register will be set to "1" and the UART1 transmit operation will be disabled as soon as the transmit shifter
stops. The data written to the SODR1 register will be sent, however, between the writing of "0" to the TXE
bit in the SCR1 register (including the RXE bit in mode 2), and the end of the transmit operation. Figure
19.6-4 shows the timing of the TDRE flag (mode 0, 1), and Figure 19.6-5 shows the timing of the TDRE
flag (mode 2).
Figure 19.6-4 TDRE Flag Set Timing (Mode 0, 1)
SODR write
TDRE
Interrupt request to CPU
SOT1 interrupt
SOT1 output
322
ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3
A/D
ST: Start bit D0 to D7: Data bits SP: Stop bit A/D: Address/data multiplexer
CHAPTER 19 UART1 (SCI)
Figure 19.6-5 TDRE Flag Set Timing (Mode 2)
SODR write
TDRE
Interrupt request to CPU
SOT1 interrupt
SOT1 output
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
D0 to D7: Data bits
323
CHAPTER 19 UART1 (SCI)
19.7
Negative Clock Operation
The MB90440G series supports the negative clock operation of UART1. In this
operation, the shift clock signal can be inverted. The definition for the shift clock signal
in an active section in UART1 is inverted from the logic "L" level to the logic "H" level,
from the negative edge to the positive edge, or vice versa. This is the same for serial
clock input and output. Thus, the edge selector register is prepared.
■ Negative Clock Operation
Figure 19.7-1 Serial Edge Select Register (SES1)
Serial Edge Select Register
bit
7
6
5
4
3
Address:000029H
Read/Write
Initial value
1
0
NEG
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(0)
Table 19.7-1 Setting the NEG Bit
NEG
324
2
Operation
0
Normal operation [default]
1
The shift clock signal is inverted
SES1
CHAPTER 19 UART1 (SCI)
19.8
UART1 Sample Applications and Precautionary
Information
This section presents a sample system configuration and communication flow chart as
a sample application of the UART1 used in Mode 1.
■ UART1 Sample Application (System Configuration in Mode 1)
Mode 1 is used when one host CPU is connected to multiple slave CPU's (see Figure 19.8-1 ). This UART1
resource supports only communication interface with the host-side unit.
Figure 19.8-1 Sample System Configuration in Mode 1
SOT1
SIN1
Host CPU
SOT1
SIN1
Slave CPU #0
SOT1
SIN1
Slave CPU #1
■ UART1 Communication Flowchart
Transmission begins with the transfer of address data by the host CPU. Address data is data handled while
the A/D bit in the SCR1 register is set to "1" and is used to select the slave CPU that is to receive the
transmission, and to enable communication with the host CPU. In normal data, the A/D bit in the SCR1
register is set to "0". Figure 19.8-2 illustrates the flow of this process.
No parity check function is available in mode 2, so that the PEN bit in the SCR1 register should be set to
"0".
325
CHAPTER 19 UART1 (SCI)
Figure 19.8-2 Communications Flowchart Using Mode 1
(Host CPU)
START
Set transfer mode to "1"
Set D0 to D7 to data selecting slave
CPU, set A/D to "1" and transfer 1 byte
Set A/D to "0"
Enable the receiving operation
Communicate with the slave CPU
Communication
ended?
NO
YES
Communicate with
other slave CPU?
NO
YES
Disable receiving operation
END
■ Intelligent I/O Service (EI2OS)
For information about EI2OS, see section "3.6 Extended Intelligent I/O Service (EI2OS)".
■ Precautions for UART1 Use
Always make communications mode settings when the UART1 is not operating. Transmit and receive data
values are not assured during mode setting.
326
CHAPTER 20
SERIAL I/O
This chapter explains the functions and operations of
the serial I/O.
20.1 Outline of Serial I/O
20.2 Serial I/O Registers
20.3 Serial I/O Operation
20.4 Negative Clock Operation
327
CHAPTER 20 SERIAL I/O
20.1
Outline of Serial I/O
The serial I/O interface operates in two modes:
• Internal shift clock mode: Data is transferred in synchronization with the internal
clock.
• External shift clock mode: Data is transferred in synchronization with the clock
supplied via the external pin (SCK2). By manipulating the general-purpose port
sharing the external pin (SCK2), data can also be transferred by a CPU instruction in
this mode.
■ Serial I/O Block Diagram
This block is a serial I/O interface that allows data transfer using clock synchronization. The interface
consists of a single eight-bit channel. Data can be transferred from the LSB or MSB.
328
CHAPTER 20 SERIAL I/O
Figure 20.1-1 Extended Serial I/O Interface Block Diagram
Internal data bus
(MSB first) D7 to D0
D7 to D0 (LSB first)
Transfer direction selection
SIN2
Read
SDR (Serial data register)
Write
SOT2
SCK2
Control circuit
Shift clock counter
Internal clock
(Prescaler)
2
1
0
SMD2SMD1SMD0SIESIRBUSYSTOPSTRTMODEBDSSOESCOE
Interrupt
request
Internal data bus
329
CHAPTER 20 SERIAL I/O
20.2
Serial I/O Registers
The serial I/O has the following three registers:
• Serial mode control status register (SMCS)
• Serial data register (SDR)
• Serial I/O prescaler (SCDCR)
■ Serial I/O Registers
Figure 20.2-1 Serial I/O Registers
Serial Mode Control Status Register
bit 15
14
13
SMD2 SMD1 SMD0
Address : 00002D H
12
11
SIE
SIR
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
Read/write
Initial value
bit
Address : 00002CH
Read/write
Initial value
7
6
5
4
10
9
8
BUSY
STOP STRT
(R)
(0)
(R/W) (R/W)
(0)
(1)
3
2
1
0
MODE
BDS
SOE
SCOE
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(R/W)
(0)
(R/W)
(0)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
SMCS
SMCS
(R/W) (R/W)
(0)
(0)
Serial data register
bit
Address : 00002E H
Read/write
Initial value
Serial I/O prescaler
Address : 00002B H
Read/write
Initial value
330
(R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
bit
15
MI
14
13
12
11
DIV3
(R/W) (R/W) (R/W) (R/W) (R/W)
(-)
(0)
(-)
(-)
(1)
(R/W)
(X)
SDR
(R/W) (R/W)
(X)
(X)
10
9
8
DIV2
DIV1
DIV0
(R/W)
(1)
(R/W) (R/W)
(1)
(1)
SCDCR
CHAPTER 20 SERIAL I/O
20.2.1
Serial Mode Control Status Register (SMCS)
The serial mode control status register (SMCS) controls the serial I/O transfer mode.
■ Serial Mode Control Status Register (SMCS)
Figure 20.2-2 Serial Mode Control Status Register (SMCS)
Serial Mode Control Status Register
bit
15
14
13
SMD2 SMD1 SMD0
Address: 00002D H
Read/write
Initial value
12
11
10
SIE
SIR
BUSY
STOP STRT
(R)
(0)
(R/W) (R/W)
(1)
(0)
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
bit
7
6
5
*1
3
4
Address: 00002CH
(-)
(-)
(-)
Read/write
Initial value
(-)
(-)
(-)
*1: Only "0" can be written.
*2: Only "1" can be written. "0" is always read.
(-)
(-)
2
MODE
BDS
(R/W)
(0)
(R/W)
(0)
9
8
1
*2
0
SOE
SCOE
SMCS
(R/W) (R/W)
(0)
(0)
[bit15 to bit13] Shift clock selection bits (SMD2 to SMD0: Serial shift clock mode)
These bits are used to select the serial shift clock mode, as shown in Table 20.2-1 .
Table 20.2-1 Setting the Serial Shift Clock Mode
SMD2
SMD1
SMD0
φ/div=4 MHz
φ/div=2 MHz
φ/div=1 MHz
0
0
0
2 MHz
1 MHz
500 kHz
0
0
1
1 MHz
500 kHz
250 kHz
0
1
0
250 kHz
125 kHz
62.5 kHz
0
1
1
125 kHz
62.5 kHz
31.25 kHz
1
0
0
62.5 kHz
31.25 kHz
15.625 kHz
1
0
1
External shift clock mode
1
1
0
Reserved
1
1
1
Reserved
331
CHAPTER 20 SERIAL I/O
div
M1
DIV3
DIV2
DIV1
DIV0
Recommended machine
cycle
3
1
1
1
0
1
6 MHz
4
1
1
1
0
0
8 MHz
5
1
1
0
1
1
10 MHz
6
1
1
0
1
0
12 MHz
7
1
1
0
0
1
14 MHz
8
1
1
0
0
0
16 MHz
Note:
For details, see "20.2.3 Serial I/O Prescaler (SCDCR)".
These bits are initialized to "000B" upon a reset. These bits must not be updated during data
transfer.
Five types of internal shift clock and an external shift clock are available. Do not set "110B" or "111B"
in SMD2, SMD1, and SMD0 as these values are reserved.
When external shift clock mode is selected, changing the output levels of the general-purpose I/O
devices sharing the shift clock input will also enable bit shifting.
[bit12] Serial I/O interrupt enable bit (SIE: Serial I/O interrupt enable)
This bit controls the serial I/O interrupt request as shown in Table 20.2-2 .
Table 20.2-2 Setting the Interrupt Request Enable Bit
SEE
Operation
0
Serial I/O interrupt disabled [initial value]
1
Serial I/O interrupt enabled
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit11] Serial I/O interrupt request bit (SIR: Serial I/O interrupt request)
When serial data transfer is completed, "1" is set to this bit. If this bit is set while interrupts are enabled
(SIE=1), an interrupt request is issued to the CPU. The clear condition varies with the MODE bit.
When "0" is written to the MODE bit, the SIR bit is cleared by writing "0". When "1" is written to the
MODE bit, the SIR bit is cleared by reading or writing to SDR. When the system is reset or "1" is
written to the STOP bit, the SIR bit is cleared regardless of the MODE bit value.
Writing "1" to the SIR bit has no effect. "1" is always read by a read operation of a read-modify-write
instruction.
332
CHAPTER 20 SERIAL I/O
[bit10] Transfer status bit (BUSY)
The transfer status bit indicates whether serial transfer is being executed.
Table 20.2-3 Setting the Transfer Status Bit
BUSY
Operating
0
Stopped, or standing by for serial data register R/W [initial value]
1
Serial transfer
This bit is initialized to "0" upon a reset. This is a read-only bit.
[bit 9]Stop bit (STOP)
The stop bit forcibly terminates serial transfer. When "1" is written to this bit, the transfer is stopped.
Table 20.2-4 Setting the Stop Bit
STOP
Operating
0
Normal operation
1
Transfer stop by STOP=1 [initial value]
This bit is initialized to "1" upon a reset. This bit is readable and writable.
[bit8] Start bit (STRT: Start)
The start bit activates serial transfer. Writing "1" to this bit starts the data transfer when the MODE bit
is set to "0". When the MODE bit is set to "1" and the STRT bit is set to "1", writing the data into serial
data register starts the transfer.
Writing "1" is ignored while the system is performing serial transfer or standing by for a serial shift
register read or write. Writing "0" has no effect. "0" is always read.
[bit3] Serial mode selection bit (MODE)
The serial mode selection bit is used to select the conditions to start the transfer operation from the stop
state. This bit must not be updated during operation.
Table 20.2-5 Setting the Serial Mode Selection Bit
MODE
Operation
0
Transfer starts when STRT=1. [initial value]
1
Transfer starts when the serial data register is read or written to.
This bit is initialized to a "0" upon a reset, and can be read or written to. To activate the intelligent I/O
service, ensure that "1" is written to this bit.
333
CHAPTER 20 SERIAL I/O
[bit2] Bit direction select bit (BDS)
When serial data is input or output, this bit determines from which bit data is to be transferred first, the
least significant bit (LSB first) or the most significant bit (MSB first), as shown in Table 20.2-6 .
Table 20.2-6 Setting the Transfer Direction Selection Bit
BDS
Operation
0
LSB first [initial value]
1
MSB first
Note:
Specify the bit ordering before any data is written to SDR.
[bit1] Serial output enable bit (SOE: Serial out enable)
This bit controls the output from the serial I/O output external pins (SOT2) as shown in Table 20.2-7 .
Table 20.2-7 Setting the Serial Output Enable Bit
SOE
Operation
0
General-purpose port pin [initial value]
1
Serial data output
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit0] Shift clock output enable bit (SCOE: SCK2 output enable)
This bit controls the output from the shift clock I/O output external pins (SCK2) as shown in Table
20.2-8 .
Table 20.2-8 Setting the Shift Clock Output Enable Bit
SCOE
Operation
0
General-purpose port pin, transfer for each instruction [initial value]
1
Shift clock output pin
Ensure that "0" is written to this bit when data is transferred for each instruction in external shift clock
mode.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
334
CHAPTER 20 SERIAL I/O
20.2.2
Serial Data Register (SDR)
This serial data register stores the serial I/O transfer data. During transfer, the SDR must
not be read or written to.
■ Serial Data Register (SDR)
Figure 20.2-3 Serial Data Register (SDR)
Serial Data Register
bit
Address : 00002EH
Read/write
Initial value
7
6
D7
D6
5
4
D5
D4
3
D3
(R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
2
D2
(R/W)
(X)
1
D1
0
D0
SDR
(R/W) (R/W)
(X)
(X)
335
CHAPTER 20 SERIAL I/O
20.2.3
Serial I/O Prescaler (SCDCR)
The Serial I/O Prescaler provides the shift clock for the Serial I/O.
The operation clock for the Serial I/O is obtained by dividing the machine clock. The
Serial I/O is designed so that a constant baud rate can be obtained for a variety of
machine clocks by the user of the communication prescaler. The SCDCR register
controls the machine clock division.
■ Serial I/O Prescaler (SCDCR)
Figure 20.2-4 Serial I/O Prescaler (SCDCR)
Serial I/O Prescaler
bit
Address: 00002B H
Read/write
Initial value
15
14
13
12
11
10
9
8
MD
DIV3
DIV2
DIV1
DIV0
(R/W)
(0)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
SCDCR
[bit15] MD (Machine clock divide mode select):
This bit is used to control the operation of the communication prescaler.
0: The Serial I/O Prescaler is disabled.
1: The Serial I/O Prescaler is enabled.
[bit11 to bit8] DIV3 to DIV0 (Divide 3 to Divide 0):
These bits are used to determine the machine clock division ratio.
Table 20.2-9 Machine Clock Division Ratio
DIV3 to DIV0
Division ratio
1101B
3
1100B
4
1011B
5
1010B
6
1001B
7
1000B
8
Note:
When the division ratio is changed, allow two cycles for the clock to stabilize before starting
communication.
336
CHAPTER 20 SERIAL I/O
20.3
Serial I/O Operation
The serial I/O consists of the serial mode control status register (SMCS) and serial data
register (SDR), and is used for input and output of 8-bit serial data.
■ Serial I/O Operation
The bits in the serial data register are serially output via the serial output pin (SOT2 pin) at the falling edge
of the serial shift clock (external clock or internal clock). The bits are serially input to the serial data
register (SDR) via the serial input pin (SIN2 pin) at the rising edge of the serial shift clock. The shift
direction (transfer from MSB or LSB) is specified by the direction specification bit (BDS) of the serial
mode control status register (SMCS).
At the end of serial data transfer, this block is stopped or stands by for a read or write of the data register
according to the MODE bit of the serial mode control status register (SMCS). To start transfer from the
stop or standby state, follow the procedure below.
• To resume operation from the stop state, write "0" to the STOP bit and "1" to the STRT bit. (The STOP
and STRT bits can be set simultaneously.)
• To resume operation from the serial data register R/W standby state, read or write to the serial data
register.
337
CHAPTER 20 SERIAL I/O
20.3.1
Shift Clock
There are two modes of shift clock: internal or external shift clock. These two modes are
selected by setting the SMCS. To switch the modes, ensure that serial I/O transfer is
stopped. To check whether the serial I/O transfer is stopped, read the BUSY bit.
■ Internal Shift Clock Mode
In internal clock mode, the internal clock determines operation, and shift clocks with a duty ratio of 50%
can be output from the SCK2 pin. One bit of data is transferred for each clock. The transfer speed (baud
rate) is shown below:
Baud rate =
φ / div
A
A is a frequency-division ratio and is 21, 22, 24, 25, or 26 indicated by the SMCS SMD bits.
Table 20.3-1 Formulas for Calculating Baud Rate in Internal Shift Clock Mode
SMD2
SMD1
SMD0
φ/div=4MHz
φ/div=2MHz
φ/div=1MHz
Formula
0
0
0
2 MHz
1 MHz
500 kHz
(φ/div)/21
0
0
1
1 MHz
500 kHz
250 kHz
(φ/div)/22
0
1
0
250 kHz
125 kHz
62.5 Hz
(φ/div)/24
0
1
1
125 kHz
62.5 kHz
31.25 kHz
(φ/div)/25
1
0
0
62.5 kHz
31.2 kHz
15.625 kHz
(φ/div)/26
See Table 20.2-9 , for the div values.
■ External Shift Clock Mode
In external shift clock mode, the data transfer is based on the external clock supplied via the SCK2 pin.
Data is transferred at one bit per clock.
The transfer speed can be between DC and 1/(8 machine cycles). For example, the transfer speed can be up
to 2 MHz when 1 machine cycle is equal to 62.5 ns.
A data bit can also be transferred by software, which is enabled as described below.
Select external shift clock mode, and write "0" to the SCOE bit of SMCS. Then, write "1" to the direction
register for the port sharing the SCK2 pin, and place the port in output mode. Then, when "1" and "0" are
written to the data register (PDR) of the port, the port value output via the SCK2 pin is fetched as the
external clock and transfer starts. Ensure that the shift clock starts from "H".
Note:
The SMCS or SDR must not be written to during serial I/O operation.
338
CHAPTER 20 SERIAL I/O
20.3.2
Serial I/O Operation
There are four serial I/O operation statuses:
• STOP
• Halt
• SDR R/W standby
• Transfer
■ Serial I/O Operation
● STOP
The STOP state is initiated upon RESET or when "1" is written to the STOP bit of SMCS. The shift
counter is initialized, and "0" is written to SIR.
To resume operation from the STOP state, write "0" to STOP and "1" to STRT. (These two bits can be
written to simultaneously.) Since the STOP bit overrides the STRT bit, transfer cannot be started by writing
"1" to STRT while "1" is written to STOP.
● Halt
When transfer is completed while the MODE bit is "0", "0" is set to BUSY and "1" is set to SIR of the
SMCS, the counter is initialized, and the system stops. To resume operation from the stop state, write "1" to
STRT.
● Serial data register R/W standby
When transfer is completed while the MODE bit is "1", "0" is set to BUSY and "1" is set to SIR of the
SMCS, and the system enters the serial data register R/W standby state. If the interrupt enable flag is set, an
interrupt signal is output from this block.
To resume operation from R/W standby state, read or write to the serial data register. This sets the BUSY
bit to "1" and starts data transfer.
339
CHAPTER 20 SERIAL I/O
● Transfer
"1" is set to the BUSY bit and serial transfer is being performed. According to the MODE bit, the halt state
or R/W standby state comes next.
Figure 20.3-1 is diagrams of the operation transitions.
Figure 20.3-1 Extended I/O Serial Interface Operation Transitions
End of transfer
STOP
STRT=0, BUSY=0
MODE=0
STRT=0, BUSY=0
STOP=1
MODE=0
&
STOP=0
&
END
STOP=0
&
STRT=1
Reset
STOP=0 & STRT=0
STOP=1
STOP=0
&
STRT=1
Transfer
STOP=1
Serial data register R/W standby
MODE=1 & END & STOP=0
STRT=1, BUSY=1
STRT=1, BUSY=0
MODE=1
SDR R/W & MODE=1
Serial data
Figure 20.3-2 Serial Data Register Read/write
Data bus
Data bus
Read
Write
Interrupt output
SOT2
SIN2
Extended I/O
serial interface
Read
Write
2.
CPU
1.
Interrupt input
Data bus Interrupt controller
1. If "1" is written to MODE, transfer ends according to the shift clock counter. The read/write standby
state starts when "1" is written to SIR. If "1" is written to the SIE bit, an interrupt signal is generated. No
interrupt signal is generated when SIE is inactive or transfer has been terminated by writing "1" to
STOP.
2. Reading or writing to the serial data register clears the interrupt request and starts serial transfer.
340
CHAPTER 20 SERIAL I/O
20.3.3
Shift Operation Start/Stop Timing
To start the shift operation, set the STOP bit to "0" and the STRT bit to "1" in SMCS.
The system may stop the shift operation at the end of transfer or when "1" is set in the
STOP bit.
• Stop by STOP=1 -> The system stops with SIR=0 regardless of the MODE bit.
• Stop by end of transfer -> The system stops with SIR=1 regardless of the MODE bit.
Regardless of the MODE bit, the BUSY bit becomes "1" during serial transfer and
becomes "0" during stop or R/W standby state. To check the transfer status, read this
bit.
■ Shift Operation Start/Stop Timing
● Internal shift clock mode (LSB first)
Figure 20.3-3 Shift Operation Start/Stop Timing (Internal Clock)
"1" output
SCK2
(Transfer start)
STRT
(Transfer end)
If MODE=0
BUSY
SOT2
DO0
DO7 (Data maintained)
● External shift clock mode (LSB first)
Figure 20.3-4 Shift Operation Start/Stop Timing (External Clock)
SCK2
(Transfer start)
STRT
(Transfer end)
If MODE=0
BUSY
SOT2
DO0
DO7 (Data maintained)
341
CHAPTER 20 SERIAL I/O
● External shift clock mode with instruction shift (LSB first)
Figure 20.3-5 Shift Operation Start/Stop Timing (External Shift Clock Mode with Instruction Shift)
PDR bit corresponding to SCK2 : 0
SCK2
STRT
PDR bit corresponding to SCK2 : 1
(Transfer end)
PDR bit corresponding to SCK2 : 0
If MODE=0
BUSY
DO7 (Data maintained)
DO6
SOT2
Note:
For an instruction shift, "H" is output when "1" is written to the PDR bit corresponding to SCK2, and
"L" is output when "0" is written. (When SCOE=0 in external shift clock mode)
● Stop by STOP=1 (LSB first, internal clock)
Figure 20.3-6 Stop Timing when "1" is Written to the STOP Bit
"1" output
SCK2
(Transfer start)
(Transfer stop)
If MODE=0
STRT
BUSY
STOP
SOT2
DO3
DO4
DO5 (Data maintained)
Note:
DO7 to DO0 indicate output data.
During serial data transfer, data is output from the serial output pin (SOT2) at the falling edge of the shift
clock, and input from the serial input pin (SIN2) at the rising edge.
342
CHAPTER 20 SERIAL I/O
● LSB first (When the BDS bit is "0")
Figure 20.3-7 Serial Data I/O Shift Timing 1
SCK2
SIN2
SIN2 Input
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DO4
DO5
DO6
DO7
DI3
DI2
DI1
DI0
DO3
DO2
DO1
DO0
SOT2 Output
SOT2
DO0
DO1
DO2
DO3
● MSB first (When the BDS bit is "1")
Figure 20.3-8 Serial Data I/O Shift Timing 2
SCK2
SIN2
SIN2 Input
DI7
DI6
DI5
DI4
SOT2 Output
SOT2
DO7
DO6
DO5
DO4
343
CHAPTER 20 SERIAL I/O
20.3.4
Interrupt Function of the Serial I/O Interface
This block can issue an interrupt request to the CPU. At the end of data transfer, the SIR
bit is set as an interrupt flag. When "1" is written to the interrupt enable bit (SIE bit) of
SMCS, an interrupt request is issued to the CPU.
■ Interrupt Function of the Serial I/O Interface
Figure 20.3-9 Interrupt Signal Output Timing of the Extended Serial I/O Interface
SCK2
(Transfer end)
BUSY
SIE=1
SIR
SDR RD/WR
SOT2
344
DO6
DO7 (Data is maintained.)
* When MODE=1
CHAPTER 20 SERIAL I/O
20.4
Negative Clock Operation
The MB90440G Series supports the negative clock operation of the Serial I/O. In this
operation, the shift clock signal is simply negated by a inverter. Therefore the definition
of the shift clock signal in the preceding sections of the Serial I/O is inverted from the
logic low level to logic high level, from the negative edge to the positive edge and viseversa. This is the same for both the serial clock input and output. The edge select
register is installed for this purpose.
■ Negative Clock Operation
Figure 20.4-1 Serial Edge Select Register (SES2)
bit
7
6
5
4
3
2
1
NEG
Address : 00002FH
Read/write
Initial value
0
(R/W) (R/W) (R/W)
(-)
(-)
(-)
(R/W) (R/W)
(-)
(-)
(R/W)
(-)
SES2
(R/W) (R/W)
(-)
(0)
Table 20.4-1 Setting the NEG Bit
NEG
Operation
0
Normal operation [initial value]
1
The shift clock signal is inverted
345
CHAPTER 20 SERIAL I/O
346
CHAPTER 21
CAN CONTROLLER
This chapter explains the functions and operations of
the CAN controller.
21.1 Features of CAN Controller
21.2 Block Diagram of CAN Controller
21.3 List of Overall Control Registers
21.4 List of Message Buffers (ID Registers)
21.5 List of Message Buffers (DLC Registers and Data Registers)
21.6 Classifying the CAN Controller Registers
21.7 Transmission of CAN Controller
21.8 Reception of CAN Controller
21.9 Reception Flowchart of CAN Controller
21.10 How to Use the CAN Controller
21.11 Procedure for Transmission by Message Buffer (x)
21.12 Procedure for Reception by Message Buffer (x)
21.13 Setting Configuration of Multi-level Message Buffer
21.14 Setting the redirection of CAN2 RX/TX pin
21.15 Precautions when Using CAN Controller
347
CHAPTER 21 CAN CONTROLLER
21.1
Features of CAN Controller
The MB90440G series has three CAN controllers (CAN0, CAN1,CAN2)
The CAN controller is a module built into a 16-bit microcomputer (F2MC-16LX). The CAN
(Controller Area Network) is the standard protocol for serial communication between
automobile controllers and is used widely in industrial applications.
■ Features of CAN Controller
The CAN controller has the following features:
● Conforms to CAN Specification Version 2.0 Part A and B
Supports transmission/reception in standard frame and extended frame formats
● Supports transmitting of data frames by receiving remote frames
● 16 transmitting/receiving message buffers
29-bit ID and 8-byte data
Multi-level message buffer configuration
● Acceptance register0/1 for each message buffer for full-bit comparison, full-bit mask, and ID
acceptance mask
Two acceptance mask registers in either standard frame format or extended frame formats
● Bit rate programmable from 10 kbps to 1 Mbps (A minimum 8 MHz machine clock is required if 1 Mbps
is used)
348
CHAPTER 21 CAN CONTROLLER
21.2
Block Diagram of CAN Controller
Figure 21.2-1 shows a block diagram of the CAN controller.
■ Block Diagram of CAN Controller
Figure 21.2-1 Block Diagram of CAN Controller
TQ (Operating clock)
Internal data bus
Prescaler
1 to 64 frequency division
Clock
Bit timing generation
SYNC, TSEG1, TSEG2
PSC
TS1
BTR
TS2
RSJ
TOE
TS
RS
CSR
HALT
NIE
NT
Node status change
interrupt generation
IDLE, INT, SUSPND,
transmit, receive,
ERR, OVRLD
Bus state
machine
Node status
change interrupt
NS1, 0
Error
control
RTEC
Transmitting/receiving
sequencer
BVALR
TREQR
TBFx, clear
Transmitting
buffer x decision
TBFx
Data
counter
Error frame
generation
Acceptance
filter control
Overload
frame
generation
TDLC RDLC
TBFx
IDSEL
BITER, STFER,
CRCER, FRMER,
ACKER
TCANR
Output
driver
ARBLOST
TX
TRTRR
TCR
Stuffing
Transmission
shift register
RFWTR
TBFx, set, clear
Transmission
complete
interrupt
Transmission complete
interrupt generation
TDLC
TIER
CRC
generation
ACK
generation
CRCER
RBFx, set
RDLC
RCR
Reception
complete
interrupt
Reception complete
interrupt generation
RIER
RBFx, TBFx, set, clear
CRC generation/error
check
Receive shift
register
STFER
Destuffing/stuffing
error check
RRTRR
RBFx, set
IDSEL
ROVRR
ARBLOST
AMSR
AMR0
0
1
Acceptance
filter
Receiving buffer x
decision
BITER
Bit error
check
ACKER
Acknowledgment
error check
AMR1
RBFx
IDR0 to 15
DLCR0 to 15
DTR0 to 15
RAM
RAM address
generation
Arbitration
check
FRMER
Form error
check
PH1
Input
latch
RX
RBFx, TBFx, RDLC, TDLC, IDSEL
LEIR
LDER
349
CHAPTER 21 CAN CONTROLLER
21.3
List of Overall Control Registers
Table 21.3-1 lists overall control registers.
■ List of Overall Control Registers
Table 21.3-1 List of Overall Control Registers (1/2)
Address
Register
CAN0
CAN1
CAN2
000070H
000080H
00005CH
000071H
000081H
00005DH
000072H
000082H
00005EH
000073H
000083H
00005FH
000074H
000084H
000060H
000075H
000085H
000061H
000076H
000086H
000062H
000077H
000087H
000063H
000078H
000088H
000064H
000079H
000089H
000065H
00007AH
00008AH
000066H
00007BH
00008BH
000067H
00007CH
00008CH
000068H
00007DH
00008DH
000069H
00007EH
00008EH
00006AH
00007FH
00008FH
00006BH
003B00H
003D00H
003F00H
003B01H
003D01H
003F01H
003B02H
003D02H
003F02H
003B03H
003D03H
003F03H
003B04H
003D04H
003F04H
003B05H
003D05H
003F05H
350
Abbreviation
Access
Initial Value
Message buffer valid register
BVALR
R/W
00000000 00000000
Transmit request register
TREQR
R/W
00000000 00000000
Transmit cancel register
TCANR
W
00000000 00000000
Transmit complete register
TCR
R/W
00000000 00000000
Receive complete register
RCR
R/W
00000000 00000000
Remote request receiving
register
RRTRR
R/W
00000000 00000000
Receive overrun register
ROVRR
R/W
00000000 00000000
Receive interrupt enable
register
RIER
R/W
00000000 00000000
Control status register
CSR
R/W, R
00---000 0----0-1
Last event indicator register
LEIR
R/W
-------- 000-0000
Receive/transmit error counter
RTEC
R
00000000 00000000
CHAPTER 21 CAN CONTROLLER
Table 21.3-1 List of Overall Control Registers (2/2)
Address
Register
CAN0
CAN1
CAN2
003B06H
003D06H
003F06H
003B07H
003D07H
003F07H
003B08H
003D08H
003F08H
003B09H
003D09H
003F09H
003B0AH
003D0AH
003F0AH
003B0BH
003D0BH
003F0BH
003B0CH
003D0CH
003F0CH
003B0DH
003D0DH
003F0DH
003B0EH
003D0EH
003F0EH
003B0FH
003D0FH
003F0FH
003B10H
003D10H
003F10H
003B11H
003D11H
003F11H
003B12H
003D12H
003F12H
003B13H
003D13H
003F13H
003B14H
003D14H
003F14H
003B15H
003D15H
003F15H
003B16H
003D16H
003F16H
003B17H
003D17H
003F17H
003B18H
003D18H
003F18H
003B19H
003D19H
003F19H
003B1AH
003D1AH
003F1AH
003B1BH
003D1BH
003F1BH
--
--
00000CH
Abbreviation
Access
Initial Value
Bit timing register
BTR
R/W
-1111111 11111111
IDE register
IDER
R/W
XXXXXXXX
XXXXXXXX
Transmit RTR register
TRTRR
R/W
00000000 00000000
Remote frame receive waiting
register
RFWTR
R/W
XXXXXXXX
XXXXXXXX
Transmit interrupt enable
register
TIER
R/W
00000000 00000000
XXXXXXXX
XXXXXXXX
Acceptance mask select
register
AMSR
R/W
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Acceptance mask register 0
AMR0
R/W
XXXXX--- XXXXXXXX
XXXXXXXX
XXXXXXXX
Acceptance mask register 1
AMR1
R/W
XXXXX--- XXXXXXXX
CAN2 RX/TX pin switching
register
CANSWR
R/W
------00
351
CHAPTER 21 CAN CONTROLLER
21.4
List of Message Buffers (ID Registers)
Table 21.4-1 lists message buffers (ID registers).
■ List of Message Buffers (ID registers)
Table 21.4-1 List of Message Buffers (ID Registers) (1/3)
Address
Register
CAN0
CAN1
CAN2
003A00H
to
003A1FH
003C00H
to
003C1FH
003E00H
to
003E1FH
003A20H
003C20H
003E20H
003A21H
003C21H
003E21H
003A22H
003C22H
003E22H
003A23H
003C23H
003E23H
003A24H
003C24H
003E24H
003A25H
003C25H
003E25H
003A26H
003C26H
003E26H
003A27H
003C27H
003E27H
003A28H
003C28H
003E28H
003A29H
003C29H
003E29H
003A2AH
003C2AH
003E2AH
003A2BH
003C2BH
003E2BH
003A2CH
003C2CH
003E2CH
003A2DH
003C2DH
003E2DH
003A2EH
003C2EH
003E2EH
003A2FH
003C2FH
003E2FH
003A30H
003C30H
003E30H
003A31H
003C31H
003E31H
003A32H
003C32H
003E32H
003A33H
003C33H
003E33H
General-purpose RAM
Abbreviation
--
Access
R/W
Initial Value
XXXXXXXX
to
XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 0
IDR0
R/W
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 1
IDR1
R/W
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 2
IDR2
R/W
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 3
IDR3
R/W
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 4
IDR4
R/W
XXXXX--- XXXXXXXX
352
CHAPTER 21 CAN CONTROLLER
Table 21.4-1 List of Message Buffers (ID Registers) (2/3)
Address
Register
CAN0
CAN1
CAN2
003A34H
003C34H
003E34H
003A35H
003C35H
003E35H
003A36H
003C36H
003E36H
003A37H
003C37H
003E37H
003A38H
003C38H
003E38H
003A39H
003C39H
003E39H
003A3AH
003C3AH
003E3AH
003A3BH
003C3BH
003E3BH
003A3CH
003C3CH
003E3CH
003A3DH
003C3DH
003E3DH
003A3EH
003C3EH
003E3EH
003A3FH
003C3FH
003E3FH
003A40H
003C40H
003E40H
003A41H
003C41H
003E41H
003A42H
003C42H
003E42H
003A43H
003C43H
003E43H
003A44H
003C44H
003E44H
003A45H
003C45H
003E45H
003A46H
003C46H
003E46H
003A47H
003C47H
003E47H
003A48H
003C48H
003E48H
003A49H
003C49H
003E49H
003A4AH
003C4AH
003E4AH
003A4BH
003C4BH
003E4BH
003A4CH
003C4CH
003E4CH
003A4DH
003C4DH
003E4DH
003A4EH
003C4EH
003E4EH
003A4FH
003C4FH
003E4FH
Abbreviation
Access
Initial Value
XXXXXXXX XXXXXXXX
ID register 5
IDR5
R/W
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 6
IDR6
R/W
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 7
IDR7
R/W
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 8
IDR8
R/W
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 9
IDR9
R/W
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 10
IDR10
R/W
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 11
IDR11
R/W
XXXXX--- XXXXXXXX
353
CHAPTER 21 CAN CONTROLLER
Table 21.4-1 List of Message Buffers (ID Registers) (3/3)
Address
Register
CAN0
CAN1
CAN2
003A50H
003C50H
003E50H
003A51H
003C51H
003E51H
003A52H
003C52H
003E52H
003A53H
003C53H
003E53H
003A54H
003C54H
003E54H
003A55H
003C55H
003E55H
003A56H
003C56H
003E56H
003A57H
003C57H
003E57H
003A58H
003C58H
003E58H
003A59H
003C59H
003E59H
003A5AH
003C5AH
003E5AH
003A5BH
003C5BH
003E5BH
003A5CH
003C5CH
003E5CH
003A5DH
003C5DH
003E5DH
003A5EH
003C5EH
003E5EH
003A5FH
003C5FH
003E5FH
Abbreviation
Access
Initial Value
XXXXXXXX XXXXXXXX
ID register 12
IDR12
R/W
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 13
IDR13
R/W
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 14
IDR14
R/W
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 15
IDR15
R/W
XXXXX--- XXXXXXXX
354
CHAPTER 21 CAN CONTROLLER
21.5
List of Message Buffers
(DLC Registers and Data Registers)
Table 21.5-1 lists message buffers (DLC registers), and Table 21.5-2 lists message
buffers (data registers).
■ List of Message Buffers (DLC Registers and Data Registers)
Table 21.5-1 List of Message Buffers (DLC Registers and Data Registers) (1/2)
Address
Register
CAN0
CAN1
CAN2
003A60H
003C60H
003E60H
003A61H
003C61H
003E61H
003A62H
003C62H
003E62H
003A63H
003C63H
003E63H
003A64H
003C64H
003E64H
003A65H
003C65H
003E65H
003A66H
003C66H
003E66H
003A67H
003C67H
003E67H
003A68H
003C68H
003E68H
003A69H
003C69H
003E69H
003A6AH
003C6AH
003E6AH
003A6BH
003C6BH
003E6BH
003A6CH
003C6CH
003E6CH
003A6DH
003C6DH
003E6DH
003A6EH
003C6EH
003E6EH
003A6FH
003C6FH
003E6FH
003A70H
003C70H
003E70H
003A71H
003C71H
003E71H
003A72H
003C72H
003E72H
003A73H
003C73H
003E73H
Abbreviation
Access
Initial Value
DLC register 0
DLCR0
R/W
----XXXX
DLC register 1
DLCR1
R/W
----XXXX
DLC register 2
DLCR2
R/W
----XXXX
DLC register 3
DLCR3
R/W
----XXXX
DLC register 4
DLCR4
R/W
----XXXX
DLC register 5
DLCR5
R/W
----XXXX
DLC register 6
DLCR6
R/W
----XXXX
DLC register 7
DLCR7
R/W
----XXXX
DLC register 8
DLCR8
R/W
----XXXX
DLC register 9
DLCR9
R/W
----XXXX
355
CHAPTER 21 CAN CONTROLLER
Table 21.5-1 List of Message Buffers (DLC Registers and Data Registers) (2/2)
Address
Register
CAN0
CAN1
CAN2
003A74H
003C74H
003E74H
003A75H
003C75H
003E75H
003A76H
003C76H
003E76H
003A77H
003C77H
003E77H
003A78H
003C78H
003E78H
003A79H
003C79H
003E79H
003A7AH
003C7AH
003E7AH
003A7BH
003C7BH
003E7BH
003A7CH
003C7CH
003E7CH
003A7DH
003C7DH
003E7DH
003A7EH
003C7EH
003E7EH
003A7FH
003C7FH
003E7FH
356
Abbreviation
Access
Initial Value
DLC register 10
DLCR10
R/W
----XXXX
DLC register 11
DLCR11
R/W
----XXXX
DLC register 12
DLCR12
R/W
----XXXX
DLC register 13
DLCR13
R/W
----XXXX
DLC register 14
DLCR14
R/W
----XXXX
DLC register 15
DLCR15
R/W
----XXXX
CHAPTER 21 CAN CONTROLLER
■ List of Message Buffers (Data Registers)
Table 21.5-2 List of Message Buffers (Data Registers) (1/2)
Address
Register
Abbreviation
Access
Initial Value
CAN0
CAN1
CAN2
003A80H
to
003A87H
003C80H
to
003C87H
003E80H
to
003E87H
Data register 0 (8 bytes)
DTR0
R/W
XXXXXXXX
to
XXXXXXXX
003A88H
to
003A8FH
003C88H
to
003C8FH
003E88H
to
003E8FH
Data register 1 (8 bytes)
DTR1
R/W
XXXXXXXX
to
XXXXXXXX
003A90H
to
003A97H
003C90H
to
003C97H
003E90H
to
003E97H
Data register 2 (8 bytes)
DTR2
R/W
XXXXXXXX
to
XXXXXXXX
003A98H
to
003A9FH
003C98H
to
003C9FH
003E98H
to
003E9FH
Data register 3 (8 bytes)
DTR3
R/W
XXXXXXXX
to
XXXXXXXX
003AA0H
to
003AA7H
003CA0H
to
003CA7H
003EA0H
to
003EA7H
Data register 4 (8 bytes)
DTR4
R/W
XXXXXXXX
to
XXXXXXXX
003AA8H
to
003AAFH
003CA8H
to
003CAFH
003EA8H
to
003EAFH
Data register 5 (8 bytes)
DTR5
R/W
XXXXXXXX
to
XXXXXXXX
003AB0H
to
003AB7H
003CB0H
to
003CB7H
003EB0H
to
003EB7H
Data register 6 (8 bytes)
DTR6
R/W
XXXXXXXX
to
XXXXXXXX
003AB8H
to
003ABFH
003CB8H
to
003CBFH
003EB8H
to
003EBFH
Data register 7 (8 bytes)
DTR7
R/W
XXXXXXXX
to
XXXXXXXX
003AC0H
to
003AC7H
003CC0H
to
003CC7H
003EC0H
to
003EC7H
Data register 8 (8 bytes)
DTR8
R/W
XXXXXXXX
to
XXXXXXXX
003AC8H
to
003ACFH
003CC8H
to
003CCFH
003EC8H
to
003ECFH
Data register 9 (8 bytes)
DTR9
R/W
XXXXXXXX
to
XXXXXXXX
003AD0H
to
003AD7H
003CD0H
to
003CD7H
003ED0H
to
003ED7H
Data register 10 (8 bytes)
DTR10
R/W
XXXXXXXX
to
XXXXXXXX
003AD8H
to
003ADFH
003CD8H
to
003CDFH
003ED8H
to
003EDFH
Data register 11 (8 bytes)
DTR11
R/W
XXXXXXXX
to
XXXXXXXX
357
CHAPTER 21 CAN CONTROLLER
Table 21.5-2 List of Message Buffers (Data Registers) (2/2)
Address
Register
Abbreviation
Access
Initial Value
CAN0
CAN1
CAN2
003AE0H
to
003AE7H
003CE0H
to
003CE7H
003EE0H
to
003EE7H
Data register 12 (8 bytes)
DTR12
R/W
XXXXXXXX
to
XXXXXXXX
003AE8H
to
003AEFH
003CE8H
to
003CEFH
003EE8H
to
003EEFH
Data register 13 (8 bytes)
DTR13
R/W
XXXXXXXX
to
XXXXXXXX
003AF0H
to
003AF7H
003CF0H
to
003CF7H
003EF0H
to
003EF7H
Data register 14 (8 bytes)
DTR14
R/W
XXXXXXXX
to
XXXXXXXX
003AF8H
to
003AFFH
003CF8H
to
003CFFH
003EF8H
to
003EFFH
Data register 15 (8 bytes)
DTR15
R/W
XXXXXXXX
to
XXXXXXXX
358
CHAPTER 21 CAN CONTROLLER
21.6
Classifying the CAN Controller Registers
There are three types of CAN controller registers:
• Overall control registers
• Message buffer control registers
• Message buffers
■ Overall Control Registers
The overall control registers are the following four registers:
• Control status register (CSR)
• Last event indicator register (LEIR)
• Receive and transmit error counter (RTEC)
• Bit timing register (BTR)
• CAN2 RX/TX pin switching register (CANSWR)
■ Message Buffer Control Registers
The message buffer control registers are the following 14 registers:
• Message buffer valid register (BVALR)
• IDE register (IDER)
• Transmission request register (TREQR)
• Transmission RTR register (TRTRR)
• Remote frame receiving wait register (RFWTR)
• Transmission cancel register (TCANR)
• Transmission complete register (TCR)
• Transmission interrupt enable register (TIER)
• Reception complete register (RCR)
• Remote request receiving register (RRTRR)
• Receive overrun register (ROVRR)
• Reception interrupt enable register (RIER)
• Acceptance mask select register (AMSR)
• Acceptance mask registers 0 and 1 (AMR0 and AMR1)
■ Message Buffers
The message buffers are the following three registers:
• ID register x (x = 0 to 15) (IDRx)
• DLC register x (x = 0 to 15) (DLCRx)
• Data register x (x = 0 to 15) (DTRx)
359
CHAPTER 21 CAN CONTROLLER
21.6.1
Control Status Register (CSR)
The lower 8 bits with the control status register (CSR) are prohibited from executing any
bit manipulation instructions (Read-Modify-Write instructions).
Only in the case of HALT bits unchanged, use any bit manipulation instructions without
problems (initialization of the macro instructions e.t.c.).
■ Control Status Register (CSR)
Figure 21.6-1 Control Status Register (CSR)
Control Status Register
bit
15
14
13
12
11
10
9
8
TS
RS
—
—
—
NT
NS1
NS0
Read/write
(R)
(R)
(-)
(-)
(-)
(R/W)
(R)
(R)
Initial value
(0)
(0)
(-)
(-)
(-)
(0)
(0)
(0)
7
6
5
4
3
2
1
0
TOE
—
—
—
—
NIE
Reserved
HALT
Read/write
(R/W)
(-)
(-)
(-)
(-)
(R/W)
(W)
(R/W)
Initial value
(0)
(-)
(-)
(-)
(-)
(0)
(0)
(1)
Address: 003B01 H (CAN0)
003D01H (CAN1)
003F01 H (CAN2)
Address: 003B00 H (CAN0)
003D00H (CAN1)
003F00 H (CAN2)
bit
CSR
CSR
[bit15] TS: Transmit status bit
This bit indicates whether a message is being transmitted.
0: Message not being transmitted
1: Message being transmitted
This bit is "0" even while error and overload frames are transmitted.
[bit14] RS: Receive status bit
This bit indicates whether a message is being received.
0: Message not being received
1: Message being received
While a message is on the bus, this bit becomes "1". Therefore, this bit is also "1" while a message is
being transmitted. This bit does not necessarily indicates whether a receiving message passes through
the acceptance filter.
As a result, when this bit is "0", it implies that the bus operation is stopped (HALT = 0); the bus is in
the intermission/bus idle or a error/overload frame is on the bus.
360
CHAPTER 21 CAN CONTROLLER
[bit10] NT: Node status transition flag
If the node status is changed to increment, or from Bus Off to Error Active, this bit is set to "1".
In other words, the NT bit is set to "1" if the node status is changed from Error Active (00) to Warning
(01), from Warning (01) to Error Passive (10), from Error Passive (10) to Bus Off (11), and from Bus
Off (11) to Error Active (00). Numbers in parentheses indicate the values of NS1 and NS0 bits.
When the node status transition interrupt enable bit (NIE) is "1", an interrupt is generated. Writing "0"
sets the NT bit to "0". Writing "1" to the NT bit is ignored. "1" is read when a Read Modify Write
instruction is performed.
[bit9, bit8] NS1 and NS0: Node status bits 1 and 0
These bits indicate the current node status.
Table 21.6-1 Correspondence between NS1 and NS0 and Node Status
NS1
NS0
Node Status
0
0
Error active
0
1
Warning (error active)
1
0
Error passive
1
1
Bus off
Note:
Warning (error active) is included in the error active in CAN Specification 2.0B for the node status,
however, indicates that the transmit error counter or receive error counter has exceeded "96". The
node status change diagram is shown in Figure 21.6-2 .
Figure 21.6-2 Node Status Transition Diagram
Hardware reset
REC: Receive error counter
TEC: Transmit error counter
Error active
REC 96
or
TEC 96
After 0 has been written to the HALT bit of
the register (CSR), continuous 11-bit High
levels (recessive bits) are input 128 times
to the receive input pin (RX).
REC < 96
and
TEC < 96
Warning
(Error active)
REC
128
or
TEC 128
REC < 128
and
TEC < 128
Bus off
Error passive
TEC
256
361
CHAPTER 21 CAN CONTROLLER
[bit7] TOE: Transmit output enable bit
Writing "1" to this bit switches from a general-purpose port pin to a transmit pin of the CAN controller.
0: General-purpose port pin
1: Transmit pin of CAN controller
[bit2] NIE: Node status transition interrupt enable bit
This bit enables or disables a node status transition interrupt (when NT = 1).
0: Node status transition interrupt disabled
1: Node status transition interrupt enabled
[bit1] Reserved: Reserved bit
Always write "0" to this bit. The read value is always "0".
[bit0] HALT: Bus operation stop bit
This bit controls the bus halt. The halt state of the bus can be checked by reading this bit.
Writing to this bit
0:Cancels bus operation stop
1:Sets bus operation stop
Reading this bit
0:Bus operation not in stop state
1:Bus operation in stop state
Note:
When write "0" to this bit during the node status is Bus Off, ensure that "1" is written to this bit.
Example program:
switch ( IO_CANCT0.CSR.bit.NS )
{
case 0 : /* error active */
break;
case 1 : /* warning */
break;
case 2 : /* error passive */
break;
default : /* bus off */
for ( i=0; ( i<=500 ) && ( IO_CANCT0.CSR.bit.HALT==0); i++);
IO_CANCT0.CSR.word = 0x0084; /* HALT = 0 */
break;
}
* The variable " i" is used for fail-safe.
362
CHAPTER 21 CAN CONTROLLER
21.6.2
Bus Operation Stop Bit (HALT = 1)
The bus operation stop bit sets or cancels stopping of bus operation, or indicates its
status
■ Conditions for Setting Bus Operation Stop (HALT=1)
There are three conditions for setting bus operation stop (HALT = 1):
• After hardware reset
• When node status changed to bus off
• By writing "1" to HALT
Note:
The bus operation should be stopped by writing "1" to HALT before the F2MC-16LX is changed in
low-power consumption mode (stop mode, timer mode).
If transmission is in progress when "1" is written to HALT, the bus operation is stopped (HALT = 1)
after transmission is terminated. If reception is in progress when "1" is written to HALT, the bus
operation is stopped immediately (HALT = 1). If received messages are being stored in the message
buffer (x), stop the bus operation (HALT = 1) after storing the messages.
To check whether the bus operation has stopped, always read the HALT bit.
■ Conditions for Canceling Bus Operation Stop (HALT = 0)
• By writing "0" to HALT
Note:
Canceling the bus operation stop after hardware reset or by writing "1" to HALT as above conditions
is performed after "0" is written to HALT and continuous 11-bit High levels (recessive bits) have been
input to the receive input pin (RX) (HALT = 0).
Canceling the bus operation stop when the node status is changed to bus off as above conditions is
performed after "0" is written to HALT and continuous 11-bit High levels (recessive bits) have been
input 128 times to the receive input pin (RX) (HALT = 0). Then, the values of both transmit and
receive error counters reach "0" and the node status is changed to error active.
When write "0" to HALT during the node status is Bus Off, ensure the "1" is written to this bit.
■ State during Bus Operation Stop (HALT = 1)
• The bus does not perform any operation, such as transmission and reception.
• The transmit output pin (TX) outputs a High level (recessive bit).
• The values of other registers and error counters are not changed.
Note:
The bit timing register (BTR) should be set during bus operation stop (HALT = 1).
363
CHAPTER 21 CAN CONTROLLER
21.6.3
Last Event Indicator Register (LEIR)
This register indicates the last event.
The NTE, TCE, and RCE bits are exclusive. When the corresponding bit of the last event
is set to "1", other bits are set to 0s.
■ Last Event Indicator Register (LEIR)
Figure 21.6-3 Last Event Indicator Register (LEIR)
Last Event Indicator Register
Address: 003B02 H (CAN0)
003D02H (CAN1)
003F02 H (CAN2)
bit
7
6
5
4
3
NTE
TCE
RCE
—
MBP3
2
1
0
MBP2
MBP1
MBP0
Read/write
(R/W)
(R/W)
(R/W)
(-)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(-)
(0)
(0)
(0)
(0)
LEIR
[bit7] NTE: Node status transition event bit
When this bit is "1", node status transition is the last event.
This bit is set to "1" at the same time the NT bit of the control status register (CSR) is set.
This bit is also set to "1" irrespective of the setting of the node status transition interrupt enable bit
(NIE) of CSR.
Writing "0" to this bit sets the NTE bit to "0". Writing "1" to this bit is ignored.
"1" is read when a Read Modify Write instruction is executed.
[bit6] TCE: Transmit completion event bit
When this bit is "1", it indicates that transmit completion is the last event.
This bit is set to "1" at the same time as any one of the bits of the transmit completion register (TCR).
This bit is also set to "1", irrespective of the settings of the bits of the transmit interrupt enable register
(TIER).
Writing "0" sets this bit to "0". Writing "1" to this bit is ignored.
"1" is read when a Read Modify Write instruction is performed.
When this bit is set to "1", the MBP3 to MBP0 bits are used to indicate the message buffer number
completing the transmit operation.
364
CHAPTER 21 CAN CONTROLLER
[bit5] RCE: Receive completion event bit
When this bit is "1", it indicates that receive completion is the last event.
This bit is set to "1" at the same time as any one of the bits of the receive complete register (RCR). This
bit is also set to "1" irrespective of the settings of the bits of the receive interrupt enable register (RIER).
Writing "0" sets this bit to "0". Writing "1" to this bit is ignored.
"1" is read when a Read Modify Write instruction is performed.
When this bit is set to "1", the MBP3 to MBP0 bits are used to indicate the message buffer number
completing the receive operation.
[bit3 to bit0] MBP3 to MBP0: Message buffer pointer bits
When the TCE or RCE bit is set to "1", these bits indicate the corresponding numbers of the message
buffers (0 to 15). If the NTE bit is set to "1", these bits have no meaning.
Writing "0" sets these bits to 0s. Writing "1" to these bits is ignored.
"1"s are read when a Read Modify Write instruction is performed.
If LEIR is accessed within an CAN interrupt handler, the event causing the interrupt is not neccessarily
the same as indicated by LEIR. In the time from interrupt request to the LEIR access by the interrupt
handler there may occur other CAN events.
365
CHAPTER 21 CAN CONTROLLER
21.6.4
Receive and Transmit Error Counters (RTEC)
The receive and transmit error counters indicate the counts for transmission errors and
reception errors defined in the CAN specifications. These registers can only be read.
■ Receive and Transmit Error Counters (RTEC)
Figure 21.6-4 Receive and Transmit Error Counters (RTEC)
Receive and transmit error counter register
15
14
13
12
11
10
9
8
TEC7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
Read/write
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
7
6
5
4
3
2
1
0
REC7
REC6
REC5
REC4
REC3
REC2
REC1
REC0
Address: 003B05 H (CAN0)
003D05H (CAN1)
003F05 H (CAN2)
Address: 003B04 H (CAN0)
003D04H (CAN1)
003F04 H (CAN2)
bit
bit
Read/write
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
RTEC
RTEC
[bit15 to bit8] TEC7 to TEC0: Transmit error counter
These are transmit error counters.
TEC7 to TEC0 values indicate 0 to 7 when the counter value is more than 256, and the subsequent
increment is not counted for counter value. In this case, Bus Off is indicated for the node status (NS1
and NS0 of control status register CSR = 11).
[bit7 to bit0] REC7 to REC0: Receive error counter
These are receive error counters.
REC7 to REC0 values indicate 0 to 7 when the counter value is more than 256, and the subsequent
increment is not counted for counter value. In this case, Error Passive is indicated for the node status
(NS1 and NS0 of control status register CSR = 10).
366
CHAPTER 21 CAN CONTROLLER
21.6.5
Bit Timing Register (BTR)
Bit timing register (BTR) stores the prescaler and bit timing setting.
■ Bit Timing Register (BTR)
Figure 21.6-5 Bit Timing Register (BTR)
Bit Timing Register
Address: 003B07 H (CAN0)
003D07H (CAN1)
bit
15
—
14
13
12
11
TS2.2
TS2.1
TS2.0
TS1.3
10
9
8
TS1.2
TS1.1
TS1.0
BTR
003F07 H (CAN2)
Read/write
(-)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(-)
(1)
(1)
(1)
(1)
(1)
(0)
(0)
7
6
5
4
3
2
1
0
RSJ1
RSJ0
PSC5
PSC4
PSC3
PSC2
PSC1
PSC0
Address: 003B06 H (CAN0)
003D06H (CAN1)
bit
BTR
003F06 H (CAN2)
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Note:
This register should be set during bus operation stop (HALT = 1).
[bit14 to bit12] TS2.2 to TS2.0: Time segment 2 setting bits 2 to 0
These bits define the number of the time quanta (TQ’s) for the time segment 2 (TSEG2). The time
segment 2 is equal to the phase buffer segment 2 (PHASE_SEG2) in the CAN specification.
[bit11 to bit8] TS1.3 to TS1.0: Time segment 1 setting bits 3 to 0
These bits define the number of the time quanta (TQ’s) for the time segment 1 (TSEG1). The time
segment 1 is equal to the propagation segment (PROP_SEG) + phase buffer segment 1 (PHASE_SEG1)
in the CAN specification.
[bit7, bit6] RSJ1, RSJ0: Resynchronization jump width setting bits 1 and 0
These bits define the number of the time quanta (TQ’s) for the resynchronization jump width.
[bit5 to bit0] PSC5 to PSC0: Prescaler setting bits 5 to 0
These bits define the time quanta (TQ) of the CAN controller.
The bit time segments defined in the CAN specification, and the CAN controller are shown in Figure
21.6-6 and Figure 21.6-7 respectively.
367
CHAPTER 21 CAN CONTROLLER
Figure 21.6-6 Bit Time Segment in CAN Specification
Nominal bit time
SYNC_SEG
PROP_SEG
PHASE_SEG1 PHASE_SEG2
Sample point
Figure 21.6-7 Bit Time Segment in CAN Controller
Nominal bit time
SYNC_SEG
TSEG1
TSEG2
Sample point
The relationship between PSC = PSC5 to PSC0, TSI = TS1.3 to TS1.0, TS2 = TS2.2 to TS1.0, and RSJ =
RSJ1 and RSJ0 when the input clock (CLK), time quanta (TQ), bit time (BT), synchronous segment
(SYNC_SEG), time segment 1 and 2 (TSEG1 and TSEG2), and resynchronization jump width [(RSJ1 and
RSJ0) +1] frequency division is shown below.
The input clock is supplied with the machine clock.
TQ
BT
= (PSC + 1) x CLK
= SYNC_SEG + TSEG1 + TSEG2
(1 + (TS1 + 1) + (TS2 +1)) x TQ
= (3 + TS1 +TS2) x TQ
RSJW = (RSJ + 1) x TQ
For correct operation, the following conditions should be met.
For 1
PSC
TSEG1
TSEG1
TSEG2
TSEG2
For PSC = 0:
TSEG1
TSEG2
TSEG2
63:
2TQ
RSJW
2TQ
RSJW
5TQ
2TQ
RSJW
In order to meet the bit timing requirements defined in the CAN specification, additions have to be met,
e.g. the propagation delay has to be considered.
368
CHAPTER 21 CAN CONTROLLER
21.6.6
Message Buffer Valid Register (BVALR)
Message buffer valid register (BVALR) stores the validity of the message buffers or
displays their state.
■ Message Buffer Valid Register (BVALR)
Figure 21.6-8 Message Buffer Valid Register (BVALR)
Message Buffer Valid Register
Address: 000071H (CAN0)
000081H (CAN1)
bit 15
14
13
12
11
10
9
8
BVAL15
BVAL14
BVAL13
BVAL12
BVAL11
BVAL10
BVAL9
BVAL8
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
7
6
5
4
3
2
1
0
BVAL7
BVAL6
BVAL5
BVAL4
BVAL3
BVAL2
BVAL1
BVAL0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
BVALR
00005DH (CAN2)
Address: 000070 H (CAN0)
000080H (CAN1)
00005CH (CAN2)
bit
BVALR
0: Message buffer (x) invalid
1: Message buffer (x) valid
If the message buffer (x) is set to invalid, it will not transmit or receive messages.
If the buffer is set to invalid during transmission operating, it becomes invalid (BVALx = 0) after the
transmission is completed or terminated by an error.
If the buffer is set to invalid during reception operating, it immediately becomes invalid (BVALx = 0). If
received messages are stored in a message buffer (x), the message buffer (x) is invalid after storing the
messages.
Note:
x indicates a message buffer number (x = 0 to 15).
When invaliding a message buffer (x) by writing "0" to a bit (BVALx), execution of a bit manipulation
instruction is prohibited until the bit is set to "0" .
To invalidate the message buffer (by setting the BVALR: BVAL bit to "0" ) while the CAN controller is
operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN
controller is operating for CAN bus communication to enable transmission and reception), follow the
procedure in Section "21.15 Precautions when Using CAN Controller".
369
CHAPTER 21 CAN CONTROLLER
21.6.7
IDE register (IDER)
This register stores the frame format used by the message buffers (x) during
transmission/reception.
■ IDE Register (IDER)
Figure 21.6-9 IDE Register (IDER)
IDE Register
Address: 003B09 H (CAN0)
003D09H (CAN1)
003F09 H (CAN2)
bit 15
14
13
12
11
10
9
8
IDE15
IDE14
IDE13
IDE12
IDE11
IDE10
IDE9
IDE8
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
6
5
4
3
2
1
0
IDE7
IDE6
IDE5
IDE4
IDE3
IDE2
IDE1
IDE0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Address: 003B08 H (CAN0)
003D08H (CAN1)
003F08 H (CAN2)
bit 7
IDER
IDER
0: The standard frame format (ID consisting of 11 bits) is used for the message buffer (x).
1: The extended frame format (ID consisting of 29 bits) is used for the message buffer (x).
Note:
This register should be set when the message buffer (x) is invalid (BVALx of the message buffer
valid register (BVALR) = 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary
received messages to be stored.
To invalidate the message buffer (by setting the BVALR: BVAL bit to "0" ) while the CAN controller is
operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN controller
is operating for CAN bus communication to enable transmission and reception), follow the procedure
in Section "21.15 Precautions when Using CAN Controller".
370
CHAPTER 21 CAN CONTROLLER
21.6.8
Transmission Request Register (TREQR)
Transmission request register (TREQR) stores transmission requests to the message
buffers (x) or displays their state.
■ Transmission Request Register (TREQR)
Figure 21.6-10 Transmission Request Register (TREQR)
Transmission Request Register
14
13
12
11
10
9
8
TREQ15
TREQ14
TREQ13
TREQ12
TREQ11
TREQ10
TREQ9
TREQ8
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
7
6
5
4
3
2
1
0
TREQ7
TREQ6
TREQ5
TREQ4
TREQ3
TREQ2
TREQ1
TREQ0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Address: 000073H (CAN0)
000083H (CAN1)
00005FH (CAN2)
Address: 000072H (CAN0)
000082H (CAN1)
00005EH (CAN2)
bit 15
bit
TREQR
TREQR
When "1" is written to TREQx, transmission to the message buffer (x) starts. If RFWTx of the remote
frame receiving wait register (RFWTR)*1 is "0", transmission starts immediately. However, if RFWTx = 1,
transmission starts after waiting until a remote frame is received (RRTRx of the remote request receiving
register (RRTRR)*1 becomes "1"). Transmission starts*2 immediately even when RFWTx = 1, if RRTRx
is already "1" when "1" is written to TREQx.
*1: For RFWTR and TRTRR, see Section "21.6.9 Transmission RTR Register (TRTRR)" and Section
"21.6.10 Remote Frame Receiving Wait Register (RFWTR)".
*2: For cancellation of transmission, see Section "21.6.11 Transmission Cancel Register (TCANR)" and
Section "21.6.12 Transmission Complete Register (TCR)".
Writing "0" to TREQx is ignored.
"0" is read when a Read Modify Write instruction is performed.
If clearing (to "0") at completion of the transmit operation and setting by writing "1" are concurrent,
clearing is preferred.
If "1" is written to more than one bit, transmission is performed, starting with the lower-numbered message
buffer (x).
TREQx is "1 while transmission is pending, and becomes "0" when transmission is completed or canceled.
371
CHAPTER 21 CAN CONTROLLER
21.6.9
Transmission RTR Register (TRTRR)
This register stores the RTR (Remote Transmission Request) bits for the message
buffers (x).
■ Transmission RTR Register (TRTRR)
Figure 21.6-11 Transmission RTR Register (TRTRR)
Transmission RTR Register
15
14
13
11
10
9
8
TRTR15
TRTR14
TRTR13
TRTR12
TRTR11
TRTR10
TRTR9
TRTR8
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
bit 7
6
5
4
3
2
1
0
TRTR7
TRTR6
TRTR5
TRTR4
TRTR3
TRTR2
TRTR1
TRTR0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
bit
Address: 003B0B H (CAN0)
003D0BH (CAN1)
003F0B H (CAN2)
Address: 003B0A H (CAN0)
003D0AH (CAN1)
003F0A H (CAN2)
0: Data frame
1: Remote frame
372
12
TRTRR
TRTRR
CHAPTER 21 CAN CONTROLLER
21.6.10
Remote Frame Receiving Wait Register (RFWTR)
Remote frame receiving wait register (RFWTR) stores the conditions for starting
transmission when a request for data frame transmission is set (TREQx of the
transmission request register (TREQR) is "1" and TRTRx of the transmitting RTR
register (TRTRR) is "0").
• 0: Transmission starts immediately
• 1: Transmission starts after waiting until remote frame received (RRTRx of remote
request receiving register (RRTRR) becomes "1")
■ Remote Frame Receiving Wait Register (RFWTR)
Figure 21.6-12 Remote Frame Receiving Wait Register (RFWTR)
Remote Frame Receiving Wait Register
Address: 003B0D H (CAN0)
003D0DH (CAN1)
003F0D H (CAN2)
bit 15
14
13
12
11
10
9
8
RFWT15
RFWT14
RFWT13
RFWT12
RFWT11
RFWT10
RFWT9
RFWT8
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
7
6
5
4
3
2
1
0
RFWT7
RFWT6
RFWT5
RFWT4
RFWT3
RFWT2
RFWT1
RFWT0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Address: 003B0C H (CAN0)
003D0CH (CAN1)
003F0C H (CAN2)
bit
RFWTR
RFWTR
Note:
Transmission starts immediately if RRTRx is already "1" when a request for transmission is set.
For remote frame transmission, do not set RFWTx to "1".
373
CHAPTER 21 CAN CONTROLLER
21.6.11
Transmission Cancel Register (TCANR)
When "1" is written to TCANx, this register cancels a pending request for transmission
to the message buffer (x).
At completion of cancellation, TREQx of the transmission request register (TREQR)
becomes "0". Writing "0" to TCANx is ignored.
This is a write only register and its read value is always "0".
■ Transmission Cancel Register (TCANR)
Figure 21.6-13 Transmission Cancel Register (TCANR)
Transmission Cancel Register
Address: 000075H (CAN0)
000085H (CAN1)
000061H (CAN2)
15
14
13
12
11
9
8
TCAN10
TCAN9
TCAN8
TCAN14
TCAN13
TCAN12
Read/write
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
7
6
5
4
3
2
1
0
TCAN7
TCAN6
TCAN5
TCAN4
TCAN3
TCAN2
TCAN1
TCAN0
Read/write
(W)
(W)
(W)
(W)
(W)
(W)
(W)
(W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
bit
TCAN11
10
TCAN15
Address: 000074H (CAN0)
000084H (CAN1)
000060H (CAN2)
374
bit
TCANR
TCANR
CHAPTER 21 CAN CONTROLLER
21.6.12
Transmission Complete Register (TCR)
At completion of transmission by the message buffer (x), the corresponding TCx
becomes "1".
If TIEx of the transmission complete interrupt enable register (TIER) is "1", an interrupt
occurs.
■ Transmission Complete Register (TCR)
Figure 21.6-14 Transmission Complete Register (TCR)
Transmission Complete Register
14
13
12
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
7
6
5
4
3
2
1
0
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Address: 000077H (CAN0)
000087H (CAN1)
000063H (CAN2)
Address: 000076H (CAN0)
000086H (CAN1)
000062H (CAN2)
bit
bit
15
11
10
9
8
TCR
TCR
● Conditions for TCx = 0
• Write"0" to TCx.
• Write "1" to TREQx of the transmission request register (TREQR).
After the completion of transmission, write "0" to TCx to set it to "0". Writing "1" to TCx is ignored.
"1" is read when a Read Modify Write instruction is performed.
Note:
If setting to "1" by completion of the transmit operation and clearing to "0" by writing occur at the
same time, the bit is set to "1".
375
CHAPTER 21 CAN CONTROLLER
21.6.13
Transmission Interrupt Enable Register (TIER)
This register enables or disables the transmission interrupt by the message buffer (x).
The transmission interrupt is generated at transmission completion (when TCx of the
transmission complete register (TCR) is "1").
■ Transmission Interrupt Enable Register (TIER)
Figure 21.6-15 Transmission Interrupt Register (TIER)
Transmission Interrupt Enable Register
Address: 003B0F H (CAN0)
003D0FH (CAN1)
003F0F H (CAN2)
bit 15
14
12
11
10
9
8
TIE15
TIE14
TIE13
TIE12
TIE11
TIE10
TIE9
TIE8
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
7
6
5
4
3
2
1
0
TIE7
TIE6
TIE5
TIE4
TIE3
TIE2
TIE1
TIE0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Address: 003B0EH (CAN0)
003D0EH (CAN1)
003F0E H (CAN2)
bit
0: Transmission interrupt disabled
1: Transmission interrupt enabled
376
13
TIER
TIER
CHAPTER 21 CAN CONTROLLER
21.6.14
Reception Complete Register (RCR)
At completion of storing received message in the message buffer (x), RCx becomes "1".
If RIEx of the reception complete interrupt enable register (RIER) is "1", an interrupt
occurs.
■ Reception Complete Register (RCR)
Figure 21.6-16 Reception Complete Register (RCR)
Reception Complete Register
bit
15
14
13
12
RC15
RC14
RC13
RC12
Read/write
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
7
6
RC7
Read/write
Initial value
Address: 000079H (CAN0)
000089H (CAN1)
000065H (CAN2)
Address: 000078H (CAN0)
000088H (CAN1)
000064H (CAN2)
bit
11
10
9
RC11
RC10
RC9
RC8
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(0)
(0)
5
4
3
2
RC6
RC5
RC4
RC3
RC2
RC1
RC0
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
1
8
RCR
0
RCR
● Conditions for RCx = 0
Write "0" to RCx.
After completion of handling received message, write "0" to RCx to set it to "0". Writing "1" to RCx is
ignored.
"1" is read when a Read Modify Write instruction is performed.
Note:
If setting to "1" by completion of the receive operation and clearing to "0" by writing occur at the
same time, the bit is set to "1".
377
CHAPTER 21 CAN CONTROLLER
21.6.15
Remote Request Receiving Register (RRTRR)
After a remote frame is stored in the message buffer (x), RRTRx becomes "1" (at the
same time as RCx setting to "1").
■ Remote Request Receiving Register (RRTRR)
Figure 21.6-17 Remote Request Receiving Register
Remote Request Receiving Register
Address: 00007BH (CAN0)
00008BH (CAN1)
000067 H (CAN2)
bit 15
14
13
12
11
10
9
8
RRTR12
RRTR11
RRTR10
RRTR9
RRTR8
RRTR15
RRTR14
RRTR13
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
7
6
5
4
3
2
1
0
RRTR7
RRTR6
RRTR5
RRTR4
RRTR3
RRTR2
RRTR1
RRTR0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Address: 00007AH (CAN0)
00008AH (CAN1)
000066 H (CAN2)
bit
RRTRR
RRTRR
● Conditions for RRTRx = 0
• Write "0" to RRTRx.
• After a received data frame is stored in the message buffer (x) (at the same time as RCx setting to "1").
• Transmission by the message buffer (x) is completed (TCx of the transmission complete register (TCR)
is "1").
Writing "1" to RRTRx is ignored.
"1" is read when a Read Modify Write instruction is performed.
Note:
If setting to "1" by completion of the receive operation and clearing to "0" by writing occur at the
same time, the bit is set to "1".
378
CHAPTER 21 CAN CONTROLLER
21.6.16
Receive Overrun Register (ROVRR)
If RCx of the reception complete register (RCR) is "1" when completing storing of a
received message in the message buffer (x), ROVRx becomes "1", indicating that
reception has overrun.
■ Receive Overrun Register (ROVRR)
Figure 21.6-18 Receive Overrun Register (ROVRR)
Receive Overrun Register
Address: 00007DH (CAN0)
00008DH (CAN1)
000069 H (CAN2)
bit 15
ROVR15
14
ROVR14
13
12
11
10
9
8
ROVR13
ROVR12
ROVR11
ROVR10
ROVR9
ROVR8
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
7
6
5
4
3
2
1
0
ROVR7
ROVR6
ROVR5
ROVR3
ROVR2
ROVR1
ROVR0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Address: 00007CH (CAN0)
00008CH (CAN1)
000068 H (CAN2)
bit
ROVR4
ROVRR
ROVRR
Writing "0" to ROVRx results in ROVRx = 0. Writing "1" to ROVRx is ignored. After checking that
reception has overrun, write "0" to ROVRx to set it to "0".
"1" is read when a Read Modify Write instruction is performed.
Note:
If setting to "1" by completion of the receive operation and clearing to "0" by writing occur at the
same time, the bit is set to "1".
379
CHAPTER 21 CAN CONTROLLER
21.6.17
Reception Interrupt Enable Register (RIER)
Reception interrupt enable register (RIER) enables or disables the reception interrupt by
the message buffer (x).
The reception interrupt is generated at reception completion (when RCx of the reception
completion register (RCR) is "1").
■ Reception Interrupt Enable Register (RIER)
Figure 21.6-19 Reception Interrupt Enable Register
Reception Interrupt Enable Register
bit 15
14
13
12
11
10
9
8
RIE15
RIE14
RIE13
RIE12
RIE11
RIE10
RIE9
RIE8
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
7
6
5
4
3
2
1
0
RIE7
RIE6
RIE5
RIE4
RIE3
RIE2
RIE1
RIE0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Address: 00007FH (CAN0)
00008FH (CAN1)
00006BH (CAN2)
Address: 00007EH (CAN0)
00008EH (CAN1)
00006AH (CAN2)
bit
0: Reception interrupt disabled
1: Reception interrupt enabled
380
RIER
RIER
CHAPTER 21 CAN CONTROLLER
21.6.18
Acceptance Mask Select Register (AMSR)
This register selects masks (acceptance mask) for comparison between the received
message ID’s and the message buffer ID’s.
■ Acceptance Mask Select Register (AMSR)
Figure 21.6-20 Acceptance Mask Select Register (AMSR)
Acceptance Mask Select Register
Type 1
bit
7
6
5
4
3
2
1
0
AMS3.1
AMS3.0
AMS2.1
AMS2.0
AMS1.1
AMS1.0
AMS0.1
AMS0.0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
bit 15
14
13
12
11
10
9
8
AMS7.0
AMS6.1
AMS6.0
AMS5.1
AMS5.0
Address: 003B10 H (CAN0)
003D10H (CAN1)
003F10 H (CAN2)
AMSR BYTE0
Type 2
Address: 003B11 H (CAN0)
003D11H (CAN1)
003F11 H (CAN2)
AMS7.1
AMS4.1
AMS4.0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
7
6
5
4
3
2
1
0
AMS11.1
AMS11.0
AMS10.1
AMS10.0
AMS9.1
AMS9.0
AMS8.1
AMS8.0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
15
14
13
12
11
10
9
8
AMSR BYTE1
Type 3
Address: 003B13 H (CAN0)
003D13H (CAN1)
003F13 H (CAN2)
bit
AMSR BYTE2
Type 4
Address: 003B14 H (CAN0)
003D14H (CAN1)
003F14 H (CAN2)
bit
AMS15.1
AMS15.0
Read/write
(R/W)
(R/W)
Initial value
(X)
(X)
AMS14.1
AMS14.0
AMS13.1
AMS13.0
AMS12.1
AMS12.0
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
(X)
(X)
(X)
AMSR BYTE3
381
CHAPTER 21 CAN CONTROLLER
Table 21.6-2 Selection of Acceptance Mask
AMSx.1
AMSx.0
Acceptance Mask
0
0
Full-bit comparison
0
1
Full-bit mask
1
0
Acceptance mask register 0 (AMR0)
1
1
Acceptance mask register 1 (AMR1)
Note:
AMSx.1 and AMSx.0 should be set when the message buffer (x) is invalid (BVALx of the message
buffer valid register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause
unnecessary received messages to be stored
To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while the CAN controller is
operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN controller
is operating for CAN bus communication to enable transmission and reception), follow the procedure
in Section "21.15 Precautions when Using CAN Controller".
382
CHAPTER 21 CAN CONTROLLER
21.6.19
Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)
There are two acceptance mask registers, AMR0 and AMR1, both of which are available
either in the standard frame format or extended frame format.
AM28 to AM18 (11 bits) are used for acceptance masks in the standard frame format and
AM28 to AM0 (29 bits) are used for acceptance masks in the extended format.
■ Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)
Figure 21.6-21 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)
Acceptance Mask Register 0/1
bit 7
6
5
4
3
2
1
0
AM28
AM27
AM26
AM25
AM24
AM23
AM22
AM21
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
15
14
13
12
11
10
9
8
AM20
AM19
AM17
AM16
AM15
AM14
AM13
Address: 003B14 H (CAN0)
003D14H (CAN1)
003F14 H (CAN2)
Address: 003B15 H (CAN0)
003D15H (CAN1)
003F15 H (CAN2)
bit
AM18
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
7
6
5
4
3
AM12
AM11
AM10
AM9
AM8
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
15
14
13
12
11
AM4
AM3
AM2
AM1
AM0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
Address: 003B16 H (CAN0)
003D16H (CAN1)
003F16 H (CAN2)
Address: 003B17 H (CAN0)
003D17H (CAN1)
003F17 H (CAN2)
bit
bit
2
1
0
AM7
AM6
AM5
(R/W)
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
(X)
10
9
8
—
—
—
(-)
(-)
(-)
(-)
(-)
(-)
AMR0 BYTE0
AMR0 BYTE1
AMR0 BYTE2
AMR0 BYTE3
(Continued)
383
CHAPTER 21 CAN CONTROLLER
(Continued)
bit
7
6
5
4
3
2
1
0
AM28
AM27
AM26
AM25
AM24
AM23
AM22
AM21
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Address: 003B19 H (CAN0)
003D19H (CAN1)
003F19 H (CAN2)
bit 15
14
13
12
11
10
9
Address: 003B18 H (CAN0)
003D18H (CAN1)
003F18 H (CAN2)
AM20
AM19
AM18
AM17
AM16
AM15
8
AM14
AM13
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
7
6
5
4
3
2
1
0
AM12
AM11
AM10
AM9
AM8
AM6
AM5
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
bit 15
14
13
12
11
10
9
8
AM4
AM3
AM2
AM1
AM0
—
—
—
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(-)
(-)
(-)
Initial value
(X)
(X)
(X)
(X)
(X)
(-)
(-)
(-)
Address: 003B1AH (CAN0)
003D1AH (CAN1)
003F1AH (CAN2)
Address: 003B1BH (CAN0)
003D1BH (CAN1)
003F1BH (CAN2)
bit
AM7
AMR1 BYTE0
AMR1 BYTE1
AMR1 BYTE2
AMR1 BYTE3
● 0: Compare
Compare the bit of the acceptance code (ID register IDRx for comparing with the received message ID)
corresponding to this bit with the bit of the received message ID. If there is no match, no message is
received.
● 1: Mask
Mask the bit of the acceptance code ID register (IDRx) corresponding to this bit. No comparison is made
with the bit of the received message ID.
Note:
AMR0 and AMR1 should be set when all the message buffers (x) selecting AMR0 and AMR1 are
invalid (BVALx of the message buffer valid register (BVALR) is "0"). Setting when the buffers are
valid (BVALx = 1) may cause unnecessary received messages to be stored.
To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while the CAN controller is
operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN controller
is operating for CAN bus communication to enable transmission and reception), follow the procedure
in Section "21.15 Precautions when Using CAN Controller".
384
CHAPTER 21 CAN CONTROLLER
21.6.20
Message Buffers
There are 16 message buffers. Message buffer x (x = 0 to 15) consists of an ID register
(IDRx), DLC register (DLCRx), and data register (DTRx).
■ Message Buffers
● The message buffer (x) is used both for transmission and reception.
● The lower-numbered message buffers are assigned higher priority.
• At transmission, when a request for transmission is made to more than one message buffer, transmission
is performed, starting with the lowest-numbered message buffer (See Section "21.7 Transmission of
CAN Controller").
• At reception, when the received message ID passes through the acceptance filter (mechanism for
comparing the acceptance-masked ID of received message and message buffer) of more than one
message buffer, the received message is stored in the lowest-numbered message buffer (See Section
"21.8 Reception of CAN Controller").
● When the same acceptance filter is set in more than one message buffer, the message buffers can be
used as a multi-level message buffer. This provides allowance for receiving time.
(See Section "21.12 Procedure for Reception by Message Buffer (x)").
Note:
A write operation to message buffers and general-purpose RAM areas should be performed in words
to even addresses only. A write operation in bytes causes undefined data to be written to the upper
byte at writing to the lower byte. Writing to the upper byte is ignored.
When the BVALx bit of the message buffer valid register (BVALR) is "0" (Invalid), the message
buffers x (IDRx, DLCRx, and DTRx) can be used as general-purpose RAM.
During the receive/transmit operation of the CAN controller, the CAN Controller write/read to/from the
message buffers. If the CPU tries to write/read to/from the message buffers in this period, the CPU
has to wait a maximum time of 64 machine cycles.
This is also true for general-purpose RAM (Addresses 003A00H to 003A1FH, 003C00H to 003C1FH
and 003E00H to 003E1FH).
385
CHAPTER 21 CAN CONTROLLER
21.6.21
ID Register x (x = 0 to 15) (IDRx)
ID Register x (x = 0 to 15) (IDRx) is the ID register for message buffer (x).
■ ID Register x (x = 0 to 15) (IDRx)
Figure 21.6-22 ID Register x (x = 0 to 15) (IDRx)
ID Register x (x = 0 to 15)
Address: 003A20H + 4x (CAN0)
003C20H + 4x (CAN1)
bit
7
6
5
4
3
2
1
0
ID26
ID25
ID24
ID23
ID22
ID21
(R/W)
ID28
ID27
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
15
14
13
12
11
9
8
ID20
ID19
ID18
ID17
ID16
ID15
ID14
ID13
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
7
6
5
4
3
2
1
0
ID10
ID9
ID8
ID7
ID6
ID5
(R/W)
003E20H + 4x (CAN2)
Address: 003A21H + 4x (CAN0)
003C21H + 4x (CAN1)
bit
10
IDRx BYTE0
IDRx BYTE1
003E21H + 4x (CAN2)
Address: 003A22H + 4x (CAN0)
003C22H + 4x (CAN1)
bit
(X)
ID12
ID11
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
14
13
12
11
10
9
8
ID4
ID3
ID2
ID1
ID0
—
—
—
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(-)
(-)
(-)
Initial value
(X)
(X)
(X)
(X)
(X)
(-)
(-)
(-)
IDRx BYTE2
003E22H + 4x (CAN2)
Address: 003A23H + 4x (CAN0)
003C23H + 4x (CAN1)
bit 15
IDRx BYTE3
003E23H + 4x (CAN2)
When using the message buffer (x) in the standard frame format (IDEx of the IDE register (IDER) = 0), use
11 bits of ID28 to ID18. When using the buffer in the extended frame format (IDEx = 1), use 29 bits of
ID28 to ID0.
ID28 to ID0 have the following functions:
• Set acceptance code.
- ID for comparing with the received message ID.
• Set transmitted message ID.
• Store the received message ID.
386
CHAPTER 21 CAN CONTROLLER
Notes:
• In the standard frame format, setting 1s to all bits of ID28 to ID22 is prohibited.
• All received message ID bits are stored (even if bits are masked). In the standard frame format,
ID17 to ID0 stores the undefined value, a part of messages received in the last time that are left in
the received shift register.
• A write operation to ID register x (x = 0 to 15) (IDRx) should be performed in words. A write
operation in bytes causes undefined data to be written to the upper byte at writing to the lower
byte. Writing to the upper byte is ignored.
• This register should be set when the message buffer (x) is invalid (BVALx of the message buffer
valid register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause
unnecessary received messages to be stored.
• To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while the CAN controller
is operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN
controller is operating for CAN bus communication to enable transmission and reception), follow
the procedure in Section "21.15 Precautions when Using CAN Controller".
387
CHAPTER 21 CAN CONTROLLER
21.6.22
DLC Register x (x = 0 to 15) (DLCRx)
DLC register x (x = 0 to 15) (DLCRx) stores DLC values for message buffer x.
■ DLC Register x (x = 0 to 15) (DLCRx)
Figure 21.6-23 DLC Register x (x = 0 to 15) (DLCRx)
DLC Register x (x = 0 to 15)
7
6
5
4
3
2
1
0
—
—
—
—
DLC3
DLC2
DLC1
DLC0
Read/write
(-)
(-)
(-)
(-)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(-)
(-)
(-)
(-)
(X)
(X)
(X)
Address: 003A60 H + 2x (CAN0)
003C60 H+ 2x (CAN1)
003E60 H+ 2x (CAN2)
bit
IDRx BYTE0
(X)
● Transmission
• Set the data length (byte count) of a transmitted message when a data frame is transmitted (TRTRx of
the transmitting RTR register (TRTRR) is "0").
• Set the data length (byte count) of a requested message when a remote frame is transmitted (TRTRx =
1).
Note:
Setting other than "0000" to "1000" (0 to 8 bytes) is prohibited.
● Reception
• Store the data length (byte count) of a received message when a data frame is received (RRTRx of the
remote frame request receiving register (RRTRR) is "0").
• Store the data length (byte count) of a requested message when a remote frame is received (RRTRx =
1).
Note:
A write operation to this register should be performed in words. A write operation in bytes causes
undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is
ignored.
388
CHAPTER 21 CAN CONTROLLER
21.6.23
Data Register x (x = 0 to 15) (DTRx)
Data register x (x = 0 to 15) (DTRx) is the data register for message buffer (x).
This register is used only in transmitting and receiving a data frame but not in
transmitting and receiving a remote frame.
■ Data Register x (x = 0 to 15) (DTRx)
Figure 21.6-24 Data Register x (x = 0 to 15) (DTRx)
Data Register x (x = 0 to 15)
Address: 003A80 H + 8x (CAN0)
003C80 H + 8x (CAN1)
003E80 H + 8x (CAN2)
bit
7
D7
6
5
4
3
2
1
0
D6
D5
D4
D3
D2
D1
D0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
15
14
13
12
11
10
9
8
D7
D6
D5
D4
D3
D2
D1
Address: 003A81 H + 8x (CAN0)
003C81 H + 8x (CAN1)
003E81 H + 8x (CAN2)
bit
D0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
7
6
5
4
3
2
1
0
D6
D5
D4
D3
D2
D1
D0
Address: 003A82 H + 8x (CAN0)
003C82 H + 8x (CAN1)
003E82 H + 8x (CAN2)
bit
D7
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
bit
15
14
D7
D6
Read/write
(R/W)
Initial value
(X)
Address: 003A83 H + 8x (CAN0)
003C83 H + 8x (CAN1)
003E83 H + 8x (CAN2)
13
12
11
D5
D4
D3
(R/W)
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
(X)
10
9
8
D1
D0
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
D2
DTRx BYTE0
DTRx BYTE1
DTRx BYTE2
DTRx BYTE3
(Continued)
389
CHAPTER 21 CAN CONTROLLER
(Continued)
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
bit 15
14
13
12
11
10
9
8
D7
D6
D5
D4
D3
D2
D1
D0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
15
14
13
12
11
10
9
8
D7
D6
D5
D4
D3
D2
D1
D0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Address:003A84 H + 8x (CAN0)
003C84H + 8x (CAN1)
003E84H + 8x (CAN2)
Address:003A85 H + 8x (CAN0)
003C85H + 8x (CAN1)
003E85H + 8x (CAN2)
Address:003A86 H + 8x (CAN0)
003C86H + 8x (CAN1)
003E86H + 8x (CAN2)
Address:003A87 H + 8x (CAN0)
003C87H + 8x (CAN1)
003E87H + 8x (CAN2)
7
bit
bit
bit
DTRx BYTE4
DTRx BYTE5
DTRx BYTE6
DTRx BYTE7
● Sets transmitted message data (any of 0 to 8 bytes).
Data is transmitted in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB.
● Stores received message data.
Data is stored in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB.
Even if the received message data is less than 8 bytes, the remaining bytes of the data register (DTRx), to
which data are stored, are undefined.
Note:
A write operation to this register should be performed in words. A write operation in bytes causes
undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is
ignored.
390
CHAPTER 21 CAN CONTROLLER
21.7
Transmission of CAN Controller
When "1" is written to TREQx of the transmission request register (TREQR),
transmission by the message buffer (x) starts. At this time, TREQx becomes "1" and
TCx of the transmission complete register (TCR) becomes "0".
■ Starting Transmission of the CAN Controller
If RFWTx of the remote frame receiving wait register (RFWTR) is "0", transmission starts immediately. If
RFWTx is "1", transmission starts after waiting until a remote frame is received (RRTRx of the remote
request receiving register (RRTRR) becomes "1").
If a request for transmission is made to more than one message buffer (more than one TREQx is "1"),
transmission is performed, starting with the lowest-numbered message buffer.
Message transmission to the CAN bus (by the transmit output pin TX) starts when the bus is idle.
If TRTRx of the transmission RTR register (TRTRR) is "0", a data frame is transmitted. If TRTRx is "1", a
remote frame is transmitted.
If the message buffer competes with other CAN controllers on the CAN bus for transmission and
arbitration fails, or if an error occurs during transmission, the message buffer waits until the bus is idle and
repeats retransmission until it is successful.
■ Canceling a Transmission Request from the CAN Controller
● Canceling by transmission cancel register (TCANR)
A transmission request for message buffer (x) having not executed transmission during transmission
pending can be canceled by writing "1" to TCANx of the transmission cancel register (TCANR). At
completion of cancellation, TREQx becomes "0".
● Canceling by storing received message
The message buffer (x) having not executed transmission despite transmission request also performs
reception.
If the message buffer (x) has not executed transmission despite a request for transmission of a data frame
(TRTRx = 0 or TREQx = 1), the transmission request is canceled after storing received data frames passing
through the acceptance filter (TREQx = 0).
Note:
A transmission request is not canceled by storing remote frames (TREQx = 1 remains unchanged).
If the message buffer (x) has not executed transmission despite a request for transmission of a remote frame
(TRTRx = 1 or TREQx = 1), the transmission request is canceled after storing received remote frames
passing through the acceptance filter (TREQx = 0).
391
CHAPTER 21 CAN CONTROLLER
Note:
The transmission request is canceled by storing either data frames or remote frames.
■ Completing Transmission of the CAN Controller
When transmission is successful, RRTRx becomes "0", TREQx becomes "0", and TCx of the transmission
complete register (TCR) becomes "1".
If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt enable
register (TIER) is "1"), an interrupt occurs.
■ Transmission Flowchart of the CAN Controller
Figure 21.7-1 shows a transmission flowchart of the CAN controller.
392
CHAPTER 21 CAN CONTROLLER
Figure 21.7-1 Transmission Flowchart of the CAN Controller
Transmission request
(TREQx:= 1)
TCx := 0
0
TREQx?
1
0
RFWTx?
1
0
RRTRx?
1
If there are any other message buffers
meeting the above conditions, select
the lowest-numbered message buffer.
NO
Is the bus idle?
YES
0
1
TRTRx?
A data frame is transmitted.
A remote frame is transmitted.
NO
Is transmission
successful?
YES
TCANx ?
1
RRTRx:= 0
TREQx:= 0
TCx := 1
TREQx:= 0
1
TIEx ?
0
0
A transmission complete
interrupt occurs.
End of transmission
393
CHAPTER 21 CAN CONTROLLER
21.8
Reception of CAN Controller
Reception starts when the start of data frame or remote frame (SOF) is detected on the
CAN bus.
■ Acceptance Filtering
The received message in the standard frame format is compared with the message buffer (x) set in the
standard frame format (IDEx of the IDE register (IDER) is "0"). The received message in the extended
frame format is compared with the message buffer (x) set (IDEx is "1") in the extended frame format.
If all the bits set to Compare by the acceptance mask agree after comparison between the received message
ID and acceptance code (ID register (IDRx) for comparing with the received message ID), the received
message passes to the acceptance filter of the message buffer (x).
■ Storing Received Message
When the receive operation is successful, received messages are stored in a message buffer x including IDs
passed through the acceptance filter.
When receiving data frames, received messages are stored in the ID register (IDRx), DLC register
(DLCRx), and data register (DTRx).
Even if received message data is less than 8 bytes, some data is stored in the remaining bytes of the DTRx
and its value is undefined.
When receiving remote frames, received messages are stored only in the IDRx and DLCRx, and the DTRx
remains unchanged.
If there is more than one message buffer including IDs passed through the acceptance filter, the message
buffer x in which received messages are to be stored is determined according to the following rules.
• The order of priority of the message buffer x (x = 0 to 15) rises as its number lower; in other words,
message buffer 0 is given the highest and the message buffer 15 is given the lowest priority.
• Basically, message buffers with the RCx bit of "0" in the receive completion register (RCR) are
preferred in storing received messages.
• If the bits of the acceptance mask select register (AMSR) are set to All Bits Compare (for message
buffers with the AMSx.1 and AMSx.0 bits set to "00"), received messages are stored irrespective of the
value of the RCx bit of the RCR.
• If there are message buffers with the RCx bit of the RCR set to "0", or with the bits of the AMSR set to
All Bits Compare, received messages are stored in the lowest-number (highest-priority) message buffer
x.
• If there are no message buffers above-mentioned, received messages are stored in a lower-number
message buffer x.
• Message buffers should be arranged in ascending numeric order. The lowest message buffers should be
with All Bits Compare, then AMR0 or AMR1 masks. And The highest message buffers should be with
All Bits Mask.
394
CHAPTER 21 CAN CONTROLLER
Figure 21.8-1 shows a flowchart for determining the message buffer (x) where received messages are to be
stored. It is recommended that message buffers be arranged in the following order: message buffers in
which each AMSR bit is set to All Bits Compare, message buffers using AMR0 or AMR1, and message
buffers in which each AMSR bit is set to All Bits Mask.
Figure 21.8-1 Flowchart Determining Message Buffer (x) where Received Messages Stored
Start
Are message buffers with RCx set to "0"
orwith AMSx.1 and AMSx.0 set to "00"
found?
NO
YES
Select the lowest-numbered
message buffer (of applicable
message buffers with RCx set
to "0" or with AMSx.1 and
AMSx.0 set to "00").
Select the lowest-numbered
message buffer (of applicable
message buffers).
End
■ Receive Overrun
The ROVRx bit in the receive overrun register (ROVRR) is set to "1", indicating receive overrun when
storage of a received message is completed in message buffer x with the RCR register RCx bit
corresponding to message buffer x already set to "1".
■ Processing for Reception of Data Frame and Remote Frame
● Processing for reception of data frame
RRTRx of the remote request receiving register (RRTRR) becomes "0".
TREQx of the transmission request register (TREQR) becomes "0" (immediately before storing the
received message). A transmission request for message buffer (x) having not executed transmission will be
canceled.
Note:
A request for transmission of either a data frame or remote frame is canceled.
395
CHAPTER 21 CAN CONTROLLER
● Processing for reception of remote frame
RRTRx becomes "1".
If TRTRx of the transmitting RTR register (TRTRR) is "1", TREQx becomes "0". As a result, the request
for transmitting remote frame to message buffer having not executed transmission will be canceled.
Note:
A request for data frame transmission is not canceled.
For cancellation of a transmission request, see Figure 21.7-1 .
■ Completing Reception
RCx of the reception complete register (RCR) becomes "1" after storing the received message.
If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is "1"), an
interrupt occurs.
Note:
This CAN controller will not receive any messages transmitted by itself.
396
CHAPTER 21 CAN CONTROLLER
21.9
Reception Flowchart of CAN Controller
Figure 21.9-1 shows a reception flowchart of the CAN controller.
■ Reception Flowchart of the CAN Controller
Figure 21.9-1 Reception Flowchart of the CAN Controller
Detection of start of data frame
or remote frame (SOF)
NO
Is any message buffer (x ) passing to
the acceptance filter found?
YES
NO
Is reception
successful?
YES
Determine message buffer (x ) where received messages to be stored.
Store the received message
in the message buffer (x).
1
RCx?
0
Data frame
ROVRx := 1
Remote frame
Received message?
RRTRx:= 0
RRTRx := 1
1
TRTRx?
0
TREQx:= 0
RCx := 1
RIEx ?
0
1
A reception interrupt
occurs.
End of reception
397
CHAPTER 21 CAN CONTROLLER
21.10
How to Use the CAN Controller
The following settings are required to use the CAN controller:
• Bit timing
• Frame format
• ID
• Acceptance filter
• Low-power consumption mode
■ Setting Bit Timing
The bit timing register (BTR) should be set during bus operation stop (when the bus operation stop bit
(HALT) of the control status register (CSR) is "1").
After the setting completion, write "0" to HALT to cancel bus operation stop.
■ Setting Frame Format
Set the frame format used by the message buffer (x). When using the standard frame format, set IDEx of
the IDE register (IDER) to "0". When using the extended frame format, set IDEx to "1".
This setting should be made when the message buffer (x) is invalid (BVALx of the message buffer valid
register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received
messages to be stored.
■ Setting ID
Set the message buffer (x) ID to ID28 to ID0 of ID register (IDRx). The message buffer (x) ID need not be
set to ID17 to ID0 in the standard frame format. The message buffer (x) ID is used as a transmission
message at transmission and is used as an acceptance code at reception.
This setting should be made when the message buffer (x) is invalid (BVALx of the message buffer valid
register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received
messages to be stored.
■ Setting Acceptance Filter
The acceptance filter of the message buffer (x) is set by an acceptance code and acceptance mask set. It
should be set when the acceptance message buffer (x) is invalid (BVALx of the message buffer enable
register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received
messages to be stored.
Set the acceptance mask used in each message buffer (x) by the acceptance mask select register (AMSR).
The acceptance mask registers (AMR0 and AMR1) should also be set if used (For the setting details, see
Section "21.6.18 Acceptance Mask Select Register (AMSR)" and Section "21.6.19 Acceptance Mask
Registers 0 and 1 (AMR0 and AMR1)").
The acceptance mask should be set so that a transmission request may not be canceled when unnecessary
received messages are stored. For example, it should be set to a full-bit comparison if only one specific ID
is used for the transmission.
398
CHAPTER 21 CAN CONTROLLER
■ Setting Low-power Consumption Mode
To set the F2MC-16LX in a low-power consumption mode (Stop, Watch, etc.), write "1" to the bus
operation stop bit (HALT) of the control status register (CSR), and then check that the bus operation has
stopped (HALT = 1).
399
CHAPTER 21 CAN CONTROLLER
21.11
Procedure for Transmission by Message Buffer (x)
After setting the bit timing, frame format, ID, and acceptance filter, set BVALx to "1" to
activate the message buffer (x).
■ Procedure for Transmission by Message Buffer (x)
● Setting transmit data length code
Set the transmit data length code (byte count) to DLC3 to DLC0 of the DLC register (DLCRx).
For data frame transmission (when TRTRx of the transmission RTR register (TRTRR) is 0), set the data
length of the transmitted message.
For remote frame transmission (when TRTRx = 1), set the data length (byte count) of the requested
message.
Note:
Setting other than "0000" to "1000" (0 to 8 bytes) is prohibited.
● Setting transmit data (only for transmission of data frame)
For data frame transmission (when TRTRx of the transmission register (TRTRR) is 0), set data as the count
of byte transmitted in the data register (DTRx).
Note:
Transmit data should be rewritten while the TREQx bit of the transmission request register (TREQR)
set to "0". There is no need for setting the BVALx bit of the message buffer valid register (BVALR) to
"0". Setting the BVALx bit to "0" may cause incoming remote frame to be lost.
● Setting transmission RTR register
For data frame transmission, set TRTRx of the transmission RTR register (TRTRR) to "0".
For remote frame transmission, set TRTRx to "1".
● Setting conditions for starting transmission (only for transmission of data frame)
Set RFWTx of the remote frame receiving wait register (RFWTR) to "0" to start transmission immediately
after a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is
"1" and TRTRx of the transmission RTR register (TRTRR) is "0").
Set RFWTx to "1" to start transmission after waiting until a remote frame is received (RRTRx of the
remote request receiving register (RRTRR) becomes "1") after a request for data frame transmission is set
(TREQx = 1 and TRTRx = 0).
400
CHAPTER 21 CAN CONTROLLER
Note:
Remote frame transmission can not be made, if RFWTx is set to "1".
● Setting transmission complete interrupt
When generating a transmission complete interrupt, set TIEx of the transmission complete interrupt enable
register (TIER) to "1".
When not generating a transmission complete interrupt, set TIEx to "0".
● Setting transmission request
For a transmission request, set TREQx of the transmission request register (TREQR) to "1".
● Canceling transmission request
When canceling a pending request for transmission to the message buffer (x), write "1" to TCANx of the
transmission cancel register (TCANR).
Check TREQx. For TREQx = 0, transmission cancellation is terminated or transmission is completed.
Check TCx of the transmission complete register (TCR). For TCx = 0, transmission cancellation is
terminated. For TCx = 1, transmission is completed.
● Processing for completion of transmission
If transmission is successful, TCx of the transmission complete register (TCR) becomes "1".
If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt enable
register (TIER) is "1"), an interrupt occurs.
After checking the transmission completion, write "0" to TCx to set it to "0". This cancels the transmission
complete interrupt.
In the following cases, the pending transmission request is canceled by receiving and storing a message.
• Request for data frame transmission by reception of data frame
• Request for remote frame transmission by reception of data frame
• Request for remote frame transmission by reception of remote frame
Request for data frame transmission is not canceled by receiving and storing a remote frame. ID and DLC,
however, are changed by the ID and DLC of the received remote frame. Note that the ID and DLC of data
frame to be transmitted become the value of received remote frame.
401
CHAPTER 21 CAN CONTROLLER
21.12
Procedure for Reception by Message Buffer (x)
After setting the bit timing, frame format, ID, and acceptance filter, make the settings
described below.
■ Procedure for Reception by Message Buffer (x)
● Setting reception interrupt
To enable reception interrupt, set RIEx of the reception interrupt enable register (RIER) to "1".
To disable reception interrupt, set RIEx to "0".
● Starting reception
When starting reception after setting, set BVALx of the message buffer valid register (BVALR) to "1" to
make the message buffer (x) valid.
● Processing for reception completion
If reception is successful after passing to the acceptance filter, the received message is stored in the
message buffer (x) and RCx of the reception complete register (RCR) becomes "1". For data frame
reception, RRTRx of the remote request receiving register (RRTRR) becomes "0". For remote frame
reception, RRTRx becomes "1".
If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is "1"), an
interrupt occurs.
After checking the reception completion (RCx = 1), process the received message.
After completion of processing the received message, check ROVRx of the reception overrun register
(ROVRR).
If ROVRx = 0, the processed received message is valid. Write "0" to RCx to set it to "0" (the reception
complete interrupt is also canceled) to terminate reception.
If ROVRx = 1, a reception overrun occurred and the next message may have overwritten the processed
message. In this case, received messages should be processed again after setting the ROVRx bit to "0" by
writing "0" to it.
Figure 21.12-1 shows an example of receive interrupt handling.
402
CHAPTER 21 CAN CONTROLLER
Figure 21.12-1 Example of Receive Interrupt Handling
Interrupt with RCx = 1
Read received messages.
A := ROVRx
ROVRx:= 0
A = 0?
NO
YES
RCx := 0
End
403
CHAPTER 21 CAN CONTROLLER
21.13
Setting Configuration of Multi-level Message Buffer
If the receptions are performed frequently, or if several different ID’s of messages are
received, in other words, if there is insufficient time for handling messages, more than
one message buffer can be combined into a multi-level message buffer to provide
allowance for processing time of the received message by CPU.
■ Setting Configuration of Multi-level Message Buffer
To provide a multi-level message buffer, the same acceptance filter must be set in the combined message
buffers.
If the bits of the acceptance mask select register (AMSR) are set to All Bits Compare ((AMSx.1, AMSx.0)
= (0, 0)), multi-level message configuration of message buffers is not allowed. This is because All Bits
Compare causes received messages to be stored irrespective of the value of the RCx bit of the receive
completion register (RCR), so received messages are always stored in lower-numbered (lower-priority)
message buffers even if All Bits Compare and identical acceptance code (ID register (IDRx)) are specified
for more than one message buffer. Therefore, All Bits Compare and identical acceptance code should not
be specified for more than one message buffer.
Figure 21.13-1 shows operational examples of multi-level message buffers.
404
CHAPTER 21 CAN CONTROLLER
Figure 21.13-1 Examples of Operation of Multi-level Message Buffer
: Initialization
AMS15, AMS14, AMS13
AMSR 10 10 10
Select AMR0.
...
AM28 to AM18
AMS0
ID28 to ID18
0000 1111 111
RC15, RC14, RC13
IDE
...
Message buffer 13
0101 0000 000
0
...
RCR 0
0
0
...
Message buffer 14
0101 0000 000
0
...
ROVRR 0
0
0
...
Message buffer 15
0101 0000 000
0
...
ROVR15, ROVR14, ROVR13
Mask
Message receiving
"The received message is stored in message buffer 13.
IDE
ID28 to ID18
Message receiving
0101 1111 000
0
...
Message buffer 13
0101 1111 000
0
...
RCR 0
0
1
...
ROVRR 0
0
0
...
Message buffer 14
0101 0000 000
0
...
Message buffer 15
0101 0000 000
0
...
Message receiving
"The received message is stored in message buffer 14.
Message receiving
0101 1111 001
0
...
Message buffer 13
0101 1111 000
0
...
RCR 0
1
1
...
Message buffer 14
0101 1111 001
0
...
ROVRR 0
0
0
...
Message buffer 15
0101 0000 000
0
...
Message receiving
"The received message is stored in message buffer 15.
Message receiving
0101 1111 010
0
...
Message buffer 13
0101 1111 000
0
...
RCR 1
1
1
...
ROVRR 0
0
0
...
Message buffer 14
0101 1111 001
0
...
Message buffer 15
0101 1111 010
0
...
Message receiving "An overrun occurs (ROVR13=1) and the received message is stored in message buffer 13.
Message receiving
0101 1111 011
0
...
Message buffer 13
0101 1111 011
0
...
RCR 1
1
1
...
Message buffer 14
0101 1111 001
0
...
ROVRR 0
0
1
...
0
...
Message buffer 15
0101 1111 010
Note:
Four messages are received with the same acceptance filter set in message buffers 13, 14 and 15.
405
CHAPTER 21 CAN CONTROLLER
21.14
Setting the redirection of CAN2 RX/TX pin
CAN2 can be changed the redirection CAN2 RX/TX pin (RX2/TX2) to RX1/TX1 pin by
CANSWR register.
■ CAN2 RX/TX Pin Switching Register (CANSWR)
Figure 21.14-1 CAN2 RX/TX pin switching register (CANSWR)
CAN2 RX/TX pin switching register
bit
Address : 00000CH
Read/write
Initial value
7
6
5
4
3
2
1
0
--
--
--
--
--
--
RXS
TXS
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
CANSWR
(R/W) (R/W)
(0)
(0)
[bit1] RXS
If "0" is written to this bit, input of CAN2 is inputted from RX2 pin. If "1" is written to this bit, input of
CAN2 is inputted from RX1 pin.
[bit0] TXS
If "0" is written to this bit, output of CAN2 is outputted from TX2 pin. If "1" is written to this bit,
output of CAN2 is outputted from TX1 pin.
CAN2 can be changed the redirection CAN2 RX/TX pin, and shared with CAN1, as shown in Figure 21.142 . Therefore this feature allows the saving of one external CAN transceiver. This function is selected by
CANSWR register.
Figure 21.14-2 Redirection of CAN2 RX/TX
CAN1
TX
TX1
RX1
RX
CAN1
RX
CAN2
switched by RXS
of CANSWR
switched by TXS
of CANSWR
VCC
CAN2
406
TX
TX2
RX2
CHAPTER 21 CAN CONTROLLER
21.15
Precautions when Using CAN Controller
Use of the CAN Controller requires the following cautions.
■ Caution for Disabling Message Buffers by BVAL bits
The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set disabled
while CAN Controller is participating in CAN communication (read value of HALT bit is "0" and CAN
Controller is ready to receive or transmit messages). This section shows the work around of this
malfunction.
● Condition
When following two conditions occur at the same time, CAN Controller will not perform to receive or
transmit messages normally.
• CAN Controller is participating in the CAN communication. (i.e. The read value of HALT bit is "0" and
CAN Controller is ready to receive or transmit messages)
• Message buffers are read or written when the message buffers are disabled by BVAL bits.
● Work around
Operation for re-configuring receiving message buffers
While CAN Controller is participating in CAN communication (the read value of HALT bit is "0" and
CAN Controller is ready to receive or transmit messages), it is necessary to following one from the two
operations described below to re-configure message buffers by ID, AMS and AMR0/AMR1 registersettings.
• Use of HALT bit
- Write "1" to HALT bit and read it back for checking the result is "1". Then change the settings for
ID/AMS/AMR0/AMR1 registers.
• No Use of Message Buffer 0
- Don't use the message buffer 0. In other words, disable message buffer (BVAL0=0), prohibit receive
interrupt (RIE0=0) and do not request transmission (TREQ0=0).
Operation for processing received message
Don't use the receiving prohibition by BVAL bit to avoid over-written of next message. Use the ROVR
bit for checking if over-write has been performed. For details, refer to Section "21.6.16 Receive
Overrun Register (ROVRR)" and Section "21.12 Procedure for Reception by Message Buffer (x)".
Operation for suppressing transmission request
Don't use BVAL bit for suppressing transmission request, use TCAN bit instead of it.
Operation for composing transmission message
For composing a transmission message, it is necessary to disable the message buffer by BVAL bit to
change contents of ID and IDE registers. In this case, BVAL bit should reset (BVAL=0) after checking
if TREQ bit is "0" or after completion of the previous message transmission (TC=1).
407
CHAPTER 21 CAN CONTROLLER
408
CHAPTER 22
ADDRESS MATCH
DETECTION FUNCTION
This chapter explains the address match detection
function and operation.
22.1 Overview of the Address Match Detection Function
22.2 Registers of the Address Match Detection Function
22.3 Operation of the Address Match Detection Function
22.4 Example of the Address Match Detection Function
409
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
22.1
Overview of the Address Match Detection Function
When an address matches the value set in the address detection register, the
instruction code to be read by the CPU is replaced with the INT9 instruction code (01H).
Consequently, the CPU executes the INT9 instruction when executing a specified
instruction. The address match detection function can be achieved using the INT9
interrupt routine for processing.
There are two address detection registers, each with an interrupt permission bit. When
an address matches the value set in the address detection register and the interrupt
permission bit is "1", the instruction code to be read by the CPU is replaced with the
INT9 instruction code.
■ Block Diagram of the Address Match Detection Function
Address latch
Address detection
register
Permission bit
F2MC-16LX bus
410
Comparison
Figure 22.1-1 Block Diagram of the Address Match Detection Function
INT9
instruction
F2MC-16LX
CPU core
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
22.2
Registers of the Address Match Detection Function
The two types of registers for the address match detection function are as follows:
• Program address detection registers (PADR0 and PADR1)
• Program address detection control status register (PACSR)
■ Program Address Detection Registers (PADR0 and PADR1)
The program address detection registers 0 and 1 (PADR0 and PADR1) compare the address with the value
written in each register. If they match when the interrupt permission bit corresponding to PACSR is "1", the
CPU is requested to issue the INT9 instruction.
When the corresponding interrupt bit is "0", nothing occurs.
Figure 22.2-1 Program Address Detection Registers (PADR0 and PADR1)
Program address detection registers
byte
byte
byte
Access
Initial value
PADR0 1FF2H/1FF1H/1FF0H
R/W
Not defined
PADR1 1FF5H/1FF4H/1FF3H
R/W
Not defined
Table 22.2-1 lists the correspondence between the program address detection registers (PADR0 and
PADR1) and PACSR.
Table 22.2-1 Correspondence between PADR0 and PADR1 Registers and PACSR
Program Address detection register
Interrupt permission bit
PADR0
AD0E
PADR1
AD1E
■ Program Address Detection Control Status Register (PACSR)
The program address detection control status register (PACSR) controls the operation of the address
detection function.
Figure 22.2-2 Program Address Detection Control Status Register (PACSR)
Program address detection
control status register
Address: 009EH
Read/write
Initial value
bit
7
6
5
4
Reserved Reserved Reserved Reserved
(R/W)
(0)
(R/W) (R/W)
(0)
(0)
3
AD1E
2
Reserved
1
AD0E
0
Reserved
PACSR
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
[bit7 to bit4] Reserved bits
Bit7 to bit4 are reserved. Set these bits to "0" before setting PACSR.
[bit3] AD1E (Address detect register 1 enable)
The AD1E bit is the operation permission bit of PADR1.
When this bit is "1", the address is compared with the PADR1 register. If they match, the INT9
instruction is issued.
411
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
[bit2] Reserved bit
Bit2 is reserved. Set this bit to "0" before setting PACSR.
[bit1] AD0E (Address Detect register 0 Enable)
The AD0E bit is the operation permission bit of PADR0.
When this bit is "1", the address is compared with the PADR0 register. If they match, the INT9
instruction is issued.
[bit0] Reserved bit
Bit0 is reserved. Set this bit to "0" before setting PACSR.
412
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
22.3
Operation of the Address Match Detection Function
If the program counter specifies the same address as the address match detection
register, the INT9 instruction is executed. The address match detection function can be
achieved by processing the INT9 instruction routine.
■ Operation of the Address Match Detection Function
There are two address detection registers with a compare enable bit. When the value set in the address
detection register and the value of the program counter match and the compare enable bit is set to "1", the
CPU executes the INT9 instruction.
Note:
If the value of the address detection register and the value of the program counter match, the
contents of internal data bus is changed to 01H. Consequently, the INT9 instruction is executed.
Before changing the contents of the address detection register, always set the compare enable bit to
"0". While the compare enable bit is set to "1", changing the contents of the address detection
register may result in a malfunction.
413
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
22.4
Example of the Address Match Detection Function
Figure 22.4-1 shows a system configuration example of the address match detection
function. Table 22.4-1 lists the E2PROM memory map.
■ System Configuration Example of the Address Match Detection Function
Figure 22.4-1 System Configuration Example of the Address Match Detection Function
E2PROM
MCU
F2MC-16LX
Pull-up resistor
Connector (UART)
SIN
Table 22.4-1 E2PROM Memory Map
Address
Description
0000H
Number of bytes of patch program No.0 (If 0, no program error exists.)
0001H
Program address No.0 bit7 to bit0
0002H
Program address No.0 bit15 to bit8
0003H
Program address No.0 bit24 to bit16
0004H
Number of bytes of patch program No.1 (If 0, no program error exists.)
0005H
Program address No.1 bit7 to bit0
0006H
Program address No.1 bit15 to bit8
0007H
Program address No.1 bit24 to bit16
0010H or higher
Main body of patch program No. 0
● Initial status
E2PROM is set to all "0"s.
● When a program error occurs:
The main body of the patch program and program address are transferred to the MCU through the
connector (UART). The MCU writes the information to E2PROM.
414
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
● Reset sequence
The MCU reads the value of E2PROM after reset. If the number of bytes of the patch program is not 0, the
main body of the patch program is read from E2PROM and written to RAM. The MCU then uses either
PADR0 or PADR1 to set the patch address and sets the compare enable bit. If the relocatable patch
program is required, the first address of the patched program can be written to the RAM area. In this case,
the INT9 routine accesses this user-defined RAM area and jumps to the patched program.
● INT9 interrupt
The interrupt routine can know the address where the interrupt occurs by checking the value of the stack
program counter. The information that has been placed on the stack during the interrupt is discarded.
■ Example of program patch processing
Figure 22.4-2 Example of program patch processing
FFFFFFH
Abnormal program
PC = address in error
ROM
External E2PROM
Register set for
program patch
Number of program bytes
Address where the interrupt occurs
Corrected program
Data transfer using UART
Corrected program
RAM
000000H
415
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION
Figure 22.4-3 Flow of program patch processing
Reset
Reads 00H of E2PROM
INT9
YES
0000H (E2PROM)=0
To patch program
JMP 000400H
NO
Read address
0001H to 0003H (E2PROM)
MOV
PADR0 (MCU)
Execute patch program
000400H to 000480H
Read patch program
0010H to 0090H (E2PROM)
MOV
000400H to 000480H (MCU)
Terminate patch program
JMP FF0050H
Enable compare
MOV PACSR, #02H
Execute normal program
NO
PC=PADR0
YES
INT9
FFFFFFH
FF0050H
ROM
E2PROM
Abnormal program
FF0000H
FFFFH
FE0000H
0090H
Patch program
0010H
001100H
Stack area
0003H
0002H
0001H
0000H
416
Program address
low-order:
Program address
middle-order:
Program address
high-order:
Number of bytes of
the patch program:
RAM area
00
00
FF
80
000480H
Patch program
RAM
000400H
RAM and register area
000100H
I/O area
000000H
CHAPTER 23
ROM MIRRORING FUNCTION
SELECTION MODULE
This chapter explains the ROM mirroring function
selection module.
23.1 Outline of ROM Mirroring Function Selection Module
23.2 ROM Mirroring Function Selection Register (ROMM)
417
CHAPTER 23 ROM MIRRORING FUNCTION SELECTION MODULE
23.1
Outline of ROM Mirroring Function Selection Module
The ROM Mirroring function selection module switches whether to mirror the image of
the FF bank of the ROM to the 00 bank.
■ Block Diagram of ROM Mirroring Function Selection Module
Figure 23.1-1 Block Diagram of ROM Mirroring Function Selection Module
Internal data bus
ROM Mirrroring Function Selection Register
Address Area
Address
FF bank
00 bank
Data
ROM
418
CHAPTER 23 ROM MIRRORING FUNCTION SELECTION MODULE
23.2
ROM Mirroring Function Selection Register (ROMM)
Do not access the ROM mirroring function selection register (ROMM) when addresses
004000H to 00FFFFH are being accessed.
■ ROM Mirroring Function Selection Register (ROMM)
Figure 23.2-1 ROM Mirroring Function Selection Register (ROMM)
ROM Mirroring Function Selection Module
bit
Address : 0006FH
Read/write
Initial value
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
MI
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(–)
(W)
(1)
ROMM
[bit8]: MI
The image of the ROM data in the FF bank can also be found in the 00 bank when "1" is written to this
bit. However, this memory mapping will not be done when this bit is written to "0". This bit is write
only.
Note:
Only FF4000H to FFFFFFH is mirrored to 004000H to 00FFFFH when ROM mirroring function is
activated. Therefore, addresses FF0000H to FF3FFFH will not be mirrored to 00 bank.
419
CHAPTER 23 ROM MIRRORING FUNCTION SELECTION MODULE
420
CHAPTER 24
1M-BIT FLASH MEMORY
This chapter explains the functions and operation of the
1M-bit flash memory. The following three methods are
available for writing data to and erasing data from the
flash memory:
• Parallel programmer
• Serial programmer
• Executing programs to write/erase data
This chapter explains "Executing programs to write/
erase data".
24.1 Outline of 1M-bit Flash Memory
24.2 Sector Configuration of the Flash Memory
24.3 Write/Erase Modes
24.4 Flash Memory Control Status Register (FMCS)
24.5 Starting the Flash Memory Automatic Algorithm
24.6 Confirming the Automatic Algorithm Execution State
24.7 Detailed Explanation of Writing to and Erasing Flash Memory
24.8 Notes on using 1M-bit Flash Memory
24.9 Flash Security Feature
24.10 Example of Programming 1M-bit Flash Memory
421
CHAPTER 24 1M-BIT FLASH MEMORY
24.1
Outline of 1M-bit Flash Memory
The 1M-bit flash memory is mapped to the FE to FF bank in the CPU memory map. The
functions of the flash memory interface circuit enable read-access and program-access
from the CPU in the same way as mask ROM. Instructions from the CPU can be used via
the flash memory interface circuit to write data to and erase data from the flash memory.
Internal CPU control therefore enables rewriting of the flash memory while it is
mounted. As a result, improvements in programs and data can be performed efficiently.
■ 1M-bit Flash Memory Features
• Use of automatic program algorithm (Embedded Algorithm: Equivalent to MBM29LV200)
• Erase pause/restart functions provided
• Detection of completion of writing/erasing using data polling or toggle bit functions
• Detection of completion of writing/erasing using CPU interrupts
• Sector erase function (any combination of sectors)
• Minimum of 10,000 write/erase operations
• Flash read cycle time (min.) = 2 machine cycles
Note:
The manufacturer code and device code do not have the reading function. These codes cannot be
accessed by the command.
■ Writing to/Erasing Flash Memory
The flash memory cannot be written to and read at the same time. That is, when data is written to or erased
data from the flash memory, the program in the flash memory must first be copied to RAM. The entire
process is then executed in RAM so that data is simply written to the flash memory. This eliminates the
need for the program to access the flash memory from the flash memory itself.
■ Flash Memory Register
Figure 24.1-1 Flash Memory Control Status Register (FMCS)
bit
7
6
5
4
3
2
1
0
Address: 0000AEH
INTE
RDYINT
WE
RDY
Reserved
LPM1
Reserved
LPM0
Read/write
⇒
(R/W)
(R/W)
(R/W)
(R)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
⇒
(0)
(0)
(0)
(X)
(0)
(0)
(0)
(0)
422
FMCS
CHAPTER 24 1M-BIT FLASH MEMORY
24.2
Sector Configuration of the Flash Memory
Figure 24.2-1 shows the sector configuration of the flash memory.
■ Sector Configuration of the 1M-bit Flash Memory
Figure 24.2-1 shows the sector configuration of the 1M-bit flash memory. The addresses in the figure
indicate the high-order and low-order addresses of each sector.
Figure 24.2-1 Sector Configuration of the 1M-bit Flash Memory
Flash memory
SA4 (16K bytes)
SA3 (8K bytes)
CPU address
Programmer address*
FFFFFFH
7FFFFH
FFBFFFH
7BFFFH
FF9FFFH
79FFFH
FF7FFFH
77FFFH
FEFFFFH
6FFFFH
FE0000 H
60000 H
SA2 (8K bytes)
SA1 (32K bytes)
SA0 (64K bytes)
*: The programmer address is equivalent to the CPU address when data
is written to the flash memory using a parallel programmer. When a general
programmer is used for writing/erasing, this address is used for writing/erasing.
423
CHAPTER 24 1M-BIT FLASH MEMORY
24.3
Write/Erase Modes
The flash memory can be accessed in two different ways: Flash memory mode and
alternative mode. Flash memory mode enables data to be directly written to or erased
from the external pins. Alternative mode enables data to be written to or erased from the
CPU via the internal bus. Use the mode external pins to select the mode.
■ Flash Memory Mode
The CPU stops when the mode pins are set to "111" while the reset signal is asserted. The flash memory
interface circuit is connected directly to ports 0, 2, 3, and 4, enabling direct control from the external pins.
This mode makes the MCU seem like a standard flash memory to the external pins, and write/erase can be
performed using a flash memory programmer.
In flash memory mode, all operations supported by the flash memory automatic algorithm can be used.
■ Alternative Mode
The flash memory is located in the FE to FF banks in the CPU memory space, and like ordinary mask
ROM, can be read-accessed and program-accessed from the CPU via the flash memory interface circuit.
Since writing/erasing the flash memory is performed by instructions from the CPU via the flash memory
interface circuit, this mode allows rewriting even when the MCU is soldered on the target board.
Sector protect operations cannot be performed in these modes.
■ Flash Memory Control Signals
Table 24.3-1 lists the flash memory control signals in flash memory mode.
There is almost a one-to-one correspondence between the flash memory control signals and the external
pins of the MBM29LV200. The VID (12 V) pins required by the sector protect operations are MD0, MD1,
and MD2 instead of A9, RESET, and OE for the MBM29LV200.
In flash memory mode, the external data bus signal width is limited to 8 bits, enabling only one-byte
access. The DQ15 to DQ8 pins are not supported. The BYTE pin should always be set to "0".
424
CHAPTER 24 1M-BIT FLASH MEMORY
Table 24.3-1 Flash Memory Control Signals
MB90F443G
MBM29LV200
Pin number
Normal function
Flash memory mode
1 to 8
P20 to P27
AQ0 to AQ7
A-1, A0 to A6
9
P30
AQ16
A15
10
P31
CE
CE
12
P32
OE
OE
13
P33
WE
WE
16
P36
BYTE
BYTE
17
P37
RY/BY
RY/BY
18 to 22
P40 to P44
AQ8 to AQ12
A7 to A11
24 to 26
P45 to P47
AQ13 to AQ15
A12 to A14
49
MD0
MDO
A9 (VID)
50
MD1
MD1
RESET (VID)
51
MD2
MD2
OE (VID)
85 to 92
P00 to P07
DQ0 to DQ7
DQ0 to DQ7
77
RST
RESET
RESET
Not supported
DQ8 to DQ15
425
CHAPTER 24 1M-BIT FLASH MEMORY
24.4
Flash Memory Control Status Register (FMCS)
The flash memory control status register (FMCS), together with the flash memory
interface circuit, is used to write data to and erase data from the flash memory.
■ Flash Memory Control Status Register (FMCS)
Figure 24.4-1 Flash Memory Control Status Register (FMCS)
Flash Memory Control Status Register (FMCS)
bit
7
6
5
4
3
2
1
0
Address: 0000AEH
INTE
RDYINT
WE
RDY
Reserved
LPM1
Reserved
LPM0
Read/write
(R/W)
(R/W)
(R/W)
(R)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(X)
(0)
(0)
(0)
(0)
FMCS
[bit7] INTE (interrupt enable)
This bit generates an interrupt to the CPU when flash memory write/erase terminates.
An interrupt to the CPU is generated when the INTE and RDYINT bits are "1". No interrupt is
generated when the INTE bit is "0".
• 0: Disables interrupts when write/erase terminates.
• 1: Enables interrupts when write/erase terminates.
[bit6] RDYINT (ready interrupt)
This bit indicates the operating state of the flash memory.
This bit is set to "1" when flash memory write/erase terminates. Data cannot be written to or erased
from the flash memory while this bit is "0" after a flash memory write/erase. Flash memory write/erase
is enabled when write/erase terminates and this bit is set to "1".
Writing "0" clears this bit to "0". Writing "1" is ignored. This bit is set to "1" at the termination timing
of the flash memory automatic algorithm (see Section "24.5 Starting the Flash Memory Automatic
Algorithm"). When the read-modify-write (RMW) instruction is used, "1" is always read.
• 0: Write/erase is being executed.
• 1: Write/erase has terminated (interrupt request generated).
[bit5] WE (write enable)
This bit enables writing to the flash memory area.
When this bit is "1", writing after the command sequence (see Section "24.5 Starting the Flash Memory
Automatic Algorithm") is issued to the FE to FF bank writes to the flash memory area. When this bit is
"0", the write/erase signal is not generated. This bit is used when the flash memory Write/Erase
command is started.
If write/erase is not performed, it is recommended that this bit be set to "0" to prevent data from being
mistakenly written to the flash memory.
• 0: Disables flash memory write/erase.
• 1: Enables flash memory write/erase.
426
CHAPTER 24 1M-BIT FLASH MEMORY
[bit4] RDY (ready)
This bit enables flash memory write/erase.
Flash memory write/erase is disabled while this bit is "0". However, Suspend commands, such as the
Read/Reset command and Sector Erase Suspend command, can be accepted even if this bit is "0".
• 0: Write/erase is being executed (next data write/erase disabled).
• 1: Write/erase has terminated (next data write/erase enabled).
[bit3] Reserved : Reserved bit
These bits are reserved for testing. During regular use, they should always be set to "0".
[bit1] Reserved : Reserved bit
During regular use, this bit should always be set to "0".
[bit2, bit0] LPM1, LPM0 (low power mode)
These bits control the current consumed by the flash memory when the flash memory is accessed. Since
the access time to the flash memory from the CPU is largely dependent on this setting, select a setting
value based on the operating frequency of the CPU.
•
01B: Low power consumption mode (Operates at an internal operating frequency up to 4 MHz.)
•
10B: Low power consumption mode (Operates at an internal operating frequency up to 8 MHz.)
•
11B: Low power consumption mode (Operates at an internal operating frequency up to 10 MHz.)
•
00B: Regular power consumption mode (Operates at an internal operating frequency up to 16 MHz.)
Note:
The RDYINT and RDY bits cannot be changed at the same time. Create a program so that decisions
are made using one or the other of these bits.
Figure 24.4-2 RDYINT and RDY Bit Change Timing
Automatic algorithm
Termination timing
RDYINT bit
RDY bit
1 machine cycle
427
CHAPTER 24 1M-BIT FLASH MEMORY
24.5
Starting the Flash Memory Automatic Algorithm
Four types of commands are available for starting the flash memory automatic
algorithm: Read/Reset, Write, Chip Erase, and Sector Erase. Control of suspend and
restart is enabled for sector erase.
■ Command Sequence Table
Table 24.5-1 lists the commands used for flash memory write/erase. All of the data written to the command
register is in bytes, but use word access to write. The data of the high-order bytes at this time is ignored.
Table 24.5-1 Command Sequence Table
1st bus write cycle
2nd bus write cycle
3rd bus write cycle
4th bus write cycle
5th bus write cycle
6th bus write cycle
Data
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
FxXXXX
XXF0
-
-
-
-
-
-
-
-
-
-
4
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XXF0
RA
RD
-
-
-
-
Write program
4
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XXA0
PA
(even)
PD
(word)
-
-
-
-
Chip Erase
6
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX80
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX10
Sector Erase
6
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX80
FxAAAA
XXAA
Fx5554
XX55
SA
(even)
XX30
-
-
Bus
write
access
Address
Read/Reset *
1
Read/Reset *
Command
sequence
Sector Erase Suspend
Entering address FxXXXX data (xxB0H) suspends erasing during sector erase.
Sector Erase Restart
Entering address FxXXXX data (xx30H) restarts erasing after erasing is suspended during sector erase.
Auto-select
3
FxAAA
XXAAA
Fx5554
XX55
FxAAAA
XX90
-
-
-
-
Notes: • The addresses Fx in the table mean FF and FE for 1M-bit flash memory. Use these addresses as the access target
bank values for operations.
• The addresses in the table are the values in the CPU memory map. All addresses and data are represented using
hexadecimal notation. However, the letter X is an optional value.
• RA: Read address
• PA: Write address. Only even addresses can be specified.
• SA: Sector address. See Section "24.2 Sector Configuration of the Flash Memory".
• RD: Read data
• PD: Write data. Only word data can be specified.
*: Both of the two types of Read/Reset commands can reset the flash memory to read mode.
The Auto-select command shown in Table 24.5-2 is used to know the state of sector protection. When
using the Auto-select command, set the address as follows.
428
CHAPTER 24 1M-BIT FLASH MEMORY
Table 24.5-2 Address Setting at Auto-select
Sector protection
AQ13 to AQ16
AQ7
AQ2
AQ1
AQ0
DQ7 to DQ0
Sector Address
L
H
L
L
CODE*
*: When the sector address is protected, the output is "01H".
When the sector address is not protected, the output is "00H".
429
CHAPTER 24 1M-BIT FLASH MEMORY
24.6
Confirming the Automatic Algorithm Execution State
Because the write/erase flow of the flash memory is controlled using the automatic
algorithm, the flash memory has hardware for posting its internal operating state and
completion of operation. This automatic algorithm enables confirmation of the
operating state of the built-in flash memory using the following hardware sequences.
■ Hardware Sequence Flags
The hardware sequence flags are configured from the five-bit output of DQ7, DQ6, DQ5, DQ3 and DQ2.
The functions of these bits are those of the data polling flag (DQ7), toggle bit flag (DQ6), timing limit
exceeded flag (DQ5), sector erase timer flag (DQ3) and toggle bit 2 flag (DQ2). The hardware sequence
flags can therefore be used to confirm that writing or chip sector erase has been completed or that erase
code write is valid.
The hardware sequence flags can be accessed by read-accessing the addresses of the target sectors in the
flash memory after setting of the command sequence (see Table 24.5-1 in Section "24.5 Starting the Flash
Memory Automatic Algorithm". Table 24.6-1 lists the bit assignments of the hardware sequence flags.
Table 24.6-1 Bit Assignments of Hardware Sequence Flags
Bit No.
Hardware sequence flag
7
6
5
4
3
2
1
0
DQ7
DQ6
DQ5
-
DQ3
DQ2
-
-
To determine whether automatic writing or chip sector erase is being executed, the hardware sequence flags
can be checked or the status can be determined from the RDY bit of the flash memory control register
(FMCS) that indicates whether writing has been completed. After writing/erasing has terminated, the state
returns to the read/reset state. When creating a program, use one of the flags to confirm that automatic
writing/erasing has terminated. Then, perform the next processing operation, such as data read. In addition,
the hardware sequence flags can be used to confirm whether the second or subsequent sector erase code
write is valid. The following sections describe each hardware sequence flag separately. Table 24.6-2 lists
the functions of the hardware sequence flags.
430
CHAPTER 24 1M-BIT FLASH MEMORY
Table 24.6-2 Hardware Sequence Flag Functions
State
Write --> Write completed (write
address specified)
Abnormal
operation
DQ7 -->
DATA:7
DQ6
Toggle -->
DATA:6
DQ5
0 -->
DATA:5
DQ3
0 -->
DATA:3
DQ2
1 -->
DATA:2
0 --> 1
Toggle -->
Stop
0 --> 1
1
Toggle -->
Stop
Sector erase wait --> Erase started
0
Toggle
0
0 --> 1
Toggle
Erase --> Sector erase suspended
(sector being erased)
0 --> 1
Toggle -->
1
0
1 --> 0
Toggle
Sector erase suspend --> Erase restarted
(sector being erased)
1 --> 0
1 -->
Toggle
0
0 --> 1
Toggle
Sector erase suspended (sector not
being erased)
DATA:7
DATA:6
DATA:5
DATA:3
DATA:2
DQ7
Toggle
1
0
1
0
Toggle
1
1
*
Chip/sector erase --> Erase completed
State
change for
normal
operation
DQ7
Write
Chip/sector erase
*: If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2 to toggle.
DQ2 does not toggle when the successive reads are executed from other sectors.
431
CHAPTER 24 1M-BIT FLASH MEMORY
24.6.1
Data Polling Flag (DQ7)
The data polling flag (DQ7) uses the data polling function to post that the automatic
algorithm is being executed or has terminated
■ Data Polling Flag (DQ7)
Table 24.6-3 and Table 24.6-4 list the state transitions of the data polling flag.
Table 24.6-3 Data Polling Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
Chip/sector
erase -->
Completed
DQ7
DQ7 -->
DATA:7
0 --> 1
Sector
erase wait
--> Started
Sector erase -->
Erase suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
0
0 --> 1
1 --> 0
DATA:7
Table 24.6-4 Data Polling Flag State Transitions (State Change for Abnormal Operation)
Operating state
Write
Chip/sector erase
DQ7
DQ7
0
● Write
Read-access during execution of the automatic write algorithm causes the flash memory to output the
opposite data of bit7 last written, regardless of the value at the address specified by the address signal.
Read-access at the end of the automatic write algorithm causes the flash memory to output bit7 of the read
value of the address specified by the address signal.
● Chip/sector erase
For a sector erase, read-access during execution of the chip erase/sector erase algorithm causes the flash
memory to output "0" from the sector currently being erased. For a chip erase, read-access causes the flash
memory to output "0" regardless of the value at the address specified by the address signal. Read-access at
the end of the automatic write algorithm causes the flash memory to output "1" in the same way.
432
CHAPTER 24 1M-BIT FLASH MEMORY
● Sector erase suspend
Read-access during a sector erase suspend causes the flash memory to output "1" if the address specified by
the address signal belongs to the sector being erased. The flash memory outputs bit7 (DATA: 7) of the read
value at the address specified by the address signal if the address specified by the address signal does not
belong to the sector being erased. Referencing this flag together with the toggle bit flag (DQ6) enables a
decision to be made on whether the flash memory is in the erase suspended state and which sector is being
erased.
Note:
When the automatic algorithm is being started, read-access to the specified address is ignored.
Since termination of the data polling flag (DQ7) can be accepted for a data read and other bits
output, data read after the automatic algorithm has terminated should be performed after readaccess has confirmed that data polling has terminated.
433
CHAPTER 24 1M-BIT FLASH MEMORY
24.6.2
Toggle Bit Flag (DQ6)
Like the data polling flag (DQ7), the toggle bit flag (DQ6) uses the toggle bit function to
post that the automatic algorithm is being executed or has terminated.
■ Toggle Bit Flag (DQ6)
Table 24.6-5 and Table 24.6-6 list the state transitions of the toggle bit flag.
Table 24.6-5 Toggle Bit Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
Chip/sector
erase -->
Completed
DQ6
Toggle -->
DATA:6
Toggle -->
Stop
Sector
erase wait
--> Started
Sector erase -->
Erase suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
Toggle
Toggle --> 1
1 --> Toggle
DATA:6
Table 24.6-6 Toggle Bit Flag State Transitions (State Change for Abnormal Operation)
Operating state
Write
Chip/sector erase
DQ6
Toggle
Toggle
● Write/chip sector erase
Continuous read-access during execution of the automatic write algorithm and chip/sector erase algorithm
causes the flash memory to toggle the "1" or "0" state for every read cycle, regardless of the value at the
address specified by the address signal. Continuous read-access at the end of the automatic write algorithm
and chip/sector erase algorithm causes the flash memory to stop toggling bit6 and output bit6 (DATA: 6) of
the read value of the address specified by the address signal.
● Sector erase suspend
Read-access during a sector erase suspend causes the flash memory to output 1 if the address specified by
the address signal belongs to the sector being erased. The flash memory outputs bit6 (DATA: 6) of the read
value at the address specified by the address signal if the address specified by the address signal does not
belong to the sector being erased.
Note:
For a write, if the sector where data is to be written is rewrite-protected, the toggle bit terminates the
toggle operation after approximately 2µs without any data being rewritten. For an erase, if all of the
selected sectors are write-protected, the toggle bit performs toggling for approximately 100µs and
then returns to the read/reset state without any data being rewritten.
434
CHAPTER 24 1M-BIT FLASH MEMORY
24.6.3
Timing Limit Exceeded Flag (DQ5)
The timing limit exceeded flag (DQ5) is used to post that execution of the automatic
algorithm has exceeded the time (internal pulse count) prescribed in the flash memory.
■ Timing Limit Exceeded Flag (DQ5)
Table 24.6-7 and Table 24.6-8 list the state transitions of the timing limit exceeded flag.
Table 24.6-7 Timing Limit Exceeded Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
Chip/sector
erase -->
Completed
DQ5
0 -->
DATA:5
0 --> 1
Sector
erase wait
--> Started
Sector erase -->
Erase suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
0
0
0
DATA:5
Table 24.6-8 Timing Limit Exceeded Bit Flag State Transitions
(State Change for Abnormal Operation)
Operating state
Write
Chip/sector erase
DQ5
1
1
● Write/chip sector erase
Read-access after write or chip/sector erase automatic algorithm activation causes the flash memory to
output "0" if the time is within the prescribed time (time required for write/erase) or to output "1" if the
prescribed time has been exceeded. Because this is done regardless of whether the automatic algorithm is
being executed or has terminated, it is possible to determine whether write/erase was successful or
unsuccessful. That is, when this flag outputs "1", writing can be determined to have been unsuccessful if
the automatic algorithm is still being executed by the data polling function or toggle bit function.
For example, writing "1" to a flash memory address where "0" has been written will cause the fail state to
occur. In this case, the flash memory will lock and execution of the automatic algorithm will not terminate.
As a result, valid data will not be output from the data polling flag (DQ7). In addition, the toggle bit flag
(DQ6) will exceed the time limit without stopping the toggle operation and the timing limit exceeded flag
(DQ5) will output "1". Note that this state indicates that the flash memory is not faulty, but has been used
correctly. When this state occurs, execute the Reset command.
435
CHAPTER 24 1M-BIT FLASH MEMORY
24.6.4
Sector Erase Timer Flag (DQ3)
The sector erase timer flag (DQ3) is used to post whether the automatic algorithm is
being executed during the sector erase wait period after the Sector Erase command has
been started.
■ Sector Erase Timer Flag (DQ3)
Table 24.6-9 and Table 24.6-10 list the state transitions of the sector erase timer flag.
Table 24.6-9 Sector Erase Timer Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
Chip/sector
erase -->
Completed
DQ3
0 -->
DATA:3
1
Sector
erase wait
--> Started
Sector erase -->
Erase suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
0 --> 1
1 --> 0
0 --> 1
DATA:3
Table 24.6-10 Sector Erase Timer Flag State Transitions
(State Change for Abnormal Operation)
Operating state
Write
Chip/sector erase
DQ3
0
1
● Sector erase
Read-access after the Sector Erase command has been started causes the flash memory to output "0" if the
automatic algorithm is being executed during the sector erase wait period, regardless of the value at the
address specified by the address signal of the sector that issued the command. The flash memory outputs
"1" if the sector erase wait period has been exceeded.
If the data polling function or toggle bit function indicates that the erase algorithm is being executed,
internally controlled erase has already started if this flag is "1". Continuous write of the sector erase codes
or commands other than the Sector Erase Suspend command will be ignored until erase is terminated.
If this flag is "0", the flash memory will accept write of additional sector erase codes. To confirm this, it is
recommended that the state of this flag be checked before continuing to write sector erase codes. If this flag
is "1" after the second state check, it is possible that additional sector erase codes may not be accepted.
436
CHAPTER 24 1M-BIT FLASH MEMORY
● Sector erase
Read-access during execution of sector erase suspend causes the flash memory to output "1" if the address
specified by the address signal belongs to the sector being erased. The flash memory outputs bit3 (DATA:
3) of the read value of the address specified by the address signal if the address specified by the address
signal does not belong to the sector being erased.
437
CHAPTER 24 1M-BIT FLASH MEMORY
24.6.5
Toggle Bit-2 Flag (DQ2)
The toggle bit-2 flag (DQ2) is a flag that uses the toggle bit function to indicate that the
sector is in the erase-suspended state.
■ Toggle Bit-2 Flag (DQ2)
Table 24.6-11 and Table 24.6-12 list the state transitions of the toggle bit flag.
Table 24.6-11 Toggle Bit-2 Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
Chip/sector
erase -->
Completed
DQ2
1 -->
DATA:2
Toggle -->
Stop
Sector
erase wait
--> Started
Sector erase -->
Erase suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
Toggle
Toggle
Toggle
DATA:2
Table 24.6-12 Toggle Bit-2 Flag State Transitions (State Change for Abnormal Operation)
Operating state
Write
Chip/sector erase
DQ2
1
*
* : If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2 to toggle.
DQ2 does not toggle when the successive reads are executed from other sectors.
● During a sector erase operation
If successive reads are executed during the execution of the chip sector erase algorithm, a flash memory
toggles to output "1" and "0" to addresses alternately at every read access regardless of the location
indicated by the addresses. If successive reads are executed after the chip sector erase algorithm is
completed, the flash memory stops the toggle operation of the bit2 and outputs the read value of the bit2
(DATA: 2) to the location indicated by the address.
438
CHAPTER 24 1M-BIT FLASH MEMORY
● While a sector erase operation is suspended
If successive reads are executed while a sector erase operation is suspended, and if the address indicates the
sector to be erased, the flash memory toggles to alternately output "1" and "0". If the address indicates the
sector is not to be erased, the flash memory outputs the read value of the bit2 (DATA: 2) to the location
indicated by the address.
In the erase-suspend-program mode, successive reads from the non-erase suspended sector causes the flash
memory to output "1".
Both DQ2 and DQ6 are used for detecting an erase-suspended sector (DQ2 toggles, but DQ6 does not).
DQ2 is also used for detecting an erasing sector. While erasing a sector, if a read access is executed from
the erasing sector, DQ2 toggles.
Reference:
If all sectors selected for erasing are write-protected, the toggle bit-2 toggles for about 100µs, and
then returns to the read/reset mode without writing the data.
439
CHAPTER 24 1M-BIT FLASH MEMORY
24.7
Detailed Explanation of Writing to and Erasing Flash
Memory
This section describes each operation procedure of flash memory Read/Reset, Write,
Chip Erase, Sector Erase, Sector Erase Suspend, and Sector Erase Restart when a
command that starts the automatic algorithm is issued.
■ Detailed Explanation of Flash Memory Write/Erase
The flash memory executes the automatic algorithm by issuing a command sequence (see Table 24.5-1 in
Section "24.5 Starting the Flash Memory Automatic Algorithm") for a write cycle to the bus to perform
Read/Reset, Write, Chip Erase, Sector Erase, Sector Erase Suspend, or Sector Erase Restart operations.
Each bus write cycle must be performed continuously. In addition, whether the automatic algorithm has
terminated can be determined using the data polling or other function. At normal termination, the flash
memory is returned to the read/reset state.
Each operation of the flash memory is described in the following order:
• Setting the read/reset state
• Writing data
• Erasing all data (erasing chips)
• Erasing optional data (erasing sectors)
• Suspending sector erase
• Restarting sector erase
440
CHAPTER 24 1M-BIT FLASH MEMORY
24.7.1
Setting The Read/Reset State
This section describes the procedure for issuing the Read/Reset command to set the
flash memory to the read/reset state.
■ Setting the Flash Memory to the Read/Reset State
The flash memory can be set to the read/reset state by sending the Read/Reset command in the command
sequence table (see Table 24.5-1 in Section "24.5 Starting the Flash Memory Automatic Algorithm")
continuously to the target sector in the flash memory.
The Read/Reset command has two types of command sequences that execute the first and third bus
operations. However, there are no essential differences between these command sequences.
The read/reset state is the initial state of the flash memory. When the power is turned on and when a
command terminates normally, the flash memory is set to the read/reset state. In the read/reset state, other
commands wait for input.
In the read/reset state, data is read by regular read-access. As with the mask ROM, program access from the
CPU is enabled. The Read/Reset command is not required to read data by a regular read. The Read/Reset
command is mainly used to initialize the automatic algorithm in such cases as when a command does not
terminate normally.
441
CHAPTER 24 1M-BIT FLASH MEMORY
24.7.2
Writing Data
This section describes the procedure for issuing the Write command to write data to the
flash memory.
■ Writing Data to the Flash Memory
The data write automatic algorithm of the flash memory can be started by sending the Write command in
the command sequence table (see Table 24.5-1 in Section "24.5 Starting the Flash Memory Automatic
Algorithm") continuously to the target sector in the flash memory. When data write to the target address is
completed in the fourth cycle, the automatic algorithm and automatic write are started.
● Specifying addresses
Only even addresses can be specified as the write addresses specified in a write data cycle. Odd addresses
cannot be written correctly. That is, writing to even addresses must be done in units of word data.
Writing can be done in any order of addresses or even if the sector boundary is exceeded. However, the
Write command writes only data of one word for each execution.
● Notes on writing data
Writing cannot return data 0 to data 1. When data "1" is written to data "0", the data polling algorithm
(DQ7) or toggle operation (DQ6) does not terminate and the flash memory elements are determined to be
faulty. If the time prescribed for writing is thus exceeded, the timing limit exceeded flag (DQ5) is
determined to be an error. Otherwise, the data is viewed as if dummy data "1" had been written. However,
when data is read in the read/reset state, the data remains "0". Data "0" can be set to data "1" only by erase
operations.
All commands are ignored during execution of the automatic write algorithm. If a hardware reset is started
during writing, the data of the written addresses will be unpredictable.
■ Writing to the Flash Memory
Figure 24.7-1 is an example of the procedure for writing to the flash memory. The hardware sequence flags
(see Section "24.6 Confirming the Automatic Algorithm Execution State") can be used to determine the
state of the automatic algorithm in the flash memory. Here, the data polling flag (DQ7) is used to confirm
that writing has terminated.
The data read to check the flag is read from the address written to last.
The data polling flag (DQ7) changes at the same time that the timing limit exceeded flag (DQ5) changes.
For example, even if the timing limit exceeded flag (DQ5) is "1", the data polling flag bit (DQ7) must be
rechecked.
Also for the toggle bit flag (DQ6), the toggle operation stops at the same time that the timing limit
exceeded flag bit (DQ5) changes to "1". The toggle bit flag (DQ6) must therefore be rechecked.
442
CHAPTER 24 1M-BIT FLASH MEMORY
Figure 24.7-1 Example of the Flash Memory Write Procedure
Start writing
FMCS: WE (bit5)
Enable flash memory write
Write command sequence
(1) FxAAAA <-- XXAA
(2) Fx5554 <-- XX55
(3) FxAAAA <-- XXA0
(4) Write address <-- Write data
Read internal address
Data polling (DQ7)
Next address
Data
Data
0
Timing limit (DQ5)
1
Read internal address
Data
Data polling (DQ7)
Data
Write error
Final address
FMCS: WE (bit5)
Disable flash memory write
Complete writing
Confirm with the hardware
sequence flags.
443
CHAPTER 24 1M-BIT FLASH MEMORY
24.7.3
Erasing All Data (Erasing Chips)
This section describes the procedure for issuing the Chip Erase command to erase all
data in the flash memory.
■ Erasing all Data in the Flash Memory (Erasing Chips)
All data can be erased from the flash memory by sending the Chip Erase command in the command
sequence table (see Table 24.5-1 in Section "24.5 Starting the Flash Memory Automatic Algorithm")
continuously to the target sector in the flash memory.
The Chip Erase command is executed in six bus operations. When writing of the sixth cycle is completed,
the chip erase operation is started. For chip erase, the user need not write to the flash memory before
erasing. During execution of the automatic erase algorithm, the flash memory writes "0" for verification
before all of the cells are erased automatically.
444
CHAPTER 24 1M-BIT FLASH MEMORY
24.7.4
Erasing Optional Data (Erasing Sectors)
This section describes the procedure for issuing the Sector Erase command to erase
optional data (erase sector) in the flash memory. Individual sectors can be erased.
Multiple sectors can also be specified at one time.
■ Erasing Optional Data (Erasing Sectors) in the Flash Memory
Optional sectors in the flash memory can be erased by sending the Sector Erase command in the command
sequence table (see Table 24.5-1 in Section "24.5 Starting the Flash Memory Automatic Algorithm")
continuously to the target sector in the flash memory.
● Specifying sectors
The Sector Erase command is executed in six bus operations. Sector erase wait of 50µs is started by writing
the sector erase code (30H) to an accessible even-numbered address in the target sector in the sixth cycle.
To erase multiple sectors, write the erase code (30H) to the addresses in the target sectors after the above
processing operation.
● Notes on specifying multiple sectors
Erase is started when the sector erase wait period of 50µs terminates after the final sector erase code has
been written. That is, to erase multiple sectors at one time, an erase code (sixth cycle of the command
sequence) must be written within 50µs of writing of the address of a sector and the address of the next
sector must be written within 50µs of writing of the previous erase code. Otherwise, the address and erase
code may not be accepted. The sector erase timer (hardware sequence flag DQ3) can be used to check
whether writing of the subsequent sector erase code is valid. At this time, specify so that the address used
for reading the sector erase timer indicates the sector to be erased.
■ Erasing Sectors in the Flash Memory
The hardware sequence flags (see Section "24.6 Confirming the Automatic Algorithm Execution State")
can be used to determine the state of the automatic algorithm in the flash memory. Figure 24.7-2 is an
example of the procedure for erasing sectors in the flash memory. Here, the toggle bit flag (DQ6) is used to
confirm that erasing has terminated.
The data that is read to check the flag is read from the sector to be erased.
The toggle bit flag (DQ6) stops the toggle operation at the same time that the timing limit exceeded flag
(DQ5) is changed to "1". For example, even if the timing limit exceeded flag (DQ5) is "1", the toggle bit
flag (DQ6) must be rechecked.
The data polling flag (DQ7) also changes at the same time that the timing limit exceeded flag bit (DQ5)
changes. As a result, the data polling flag (DQ7) must be rechecked.
445
CHAPTER 24 1M-BIT FLASH MEMORY
Figure 24.7-2 Example of the Flash Memory Sector Erase Procedure
Start erasing
FMCS: WE (bit5)
Enable flash memory erase
Erase command sequence
(1) FxAAAA <-- XXAA
(2) Fx5554 <-- XX55
(3) FxAAAA <-- XX80
(4) Fx5554 <-- XX55
(5) Sector address <-Erase code (30H)
(6) Sector address <-Erase code (30H)
YES
Another erase sector
NO
Read internal address 1
YES
Next sector
Read internal address 2
NO
Toggle bit (DQ6)
data 1(DQ6) = data 2(DQ6)
Sector Erase Completed ?
YES
NO
0
Timing limit (DQ5)
1
Read internal address 1
Read internal address 2
NO
Toggle bit (DQ6)
data 1(DQ6) = data 2(DQ6)
YES
Erase error
Final sector
NO
YES
FMCS: WE (bit5)
Disable flash memory erase
Confirm with the hardware
sequence flags.
Complete erasing
446
CHAPTER 24 1M-BIT FLASH MEMORY
24.7.5
Suspending Sector Erase
This section describes the procedure for issuing the Sector Erase Suspend command
to suspend erasing of flash memory sectors. Data can be read from sectors that are not
being erased.
■ Suspending Erasing of Flash Memory Sectors
Erasing of flash memory sectors can be suspended by sending the Sector Erase Suspend command in the
command sequence table (see Table 24.5-1 in Section "24.5 Starting the Flash Memory Automatic
Algorithm") to the target sector in the flash memory.
The Sector Erase Suspend command suspends the sector erase operation being executed and enables data to
be read from sectors that are not being erased. In this state, only reading is enabled; data cannot be written.
This command is valid only during sector erase operations that include the erase wait time. The command
will be ignored during chip erase or write operations.
This command is implemented by writing the erase suspend code (B0H). At this time, specify an optional
address in the flash memory for the address. An Erase Suspend command issued again during erasing of
sectors will be ignored.
Entering the Sector Erase Suspend command during the sector erase wait period will immediately terminate
sector erase wait, cancel the erase operation, and set the erase stop state. Entering the Erase Suspend
command during the erase operation after the sector erase wait period has terminated will set the erase
suspend state after a maximum period of 20µs has elapsed. Sector Erase Suspend command should be
entered more than 20µs after Sector Erase command or Sector Erase Restart command is issued.
447
CHAPTER 24 1M-BIT FLASH MEMORY
24.7.6
Restarting Sector Erase
This section describes the procedure for issuing the Sector Erase Restart command to
restart suspended erasing of flash memory sectors.
■ Restarting Erasing of Flash Memory Sectors
Suspended erasing of flash memory sectors can be restarted by sending the Sector Erase Restart command
in the command sequence table (see Table 24.5-1 in Section "24.5 Starting the Flash Memory Automatic
Algorithm") to the target sector in the flash memory.
The Sector Erase Restart command is used to restart erasing of sectors from the sector erase suspend state
set using the Sector Erase Suspend command. The Sector Erase Restart command is implemented by
writing the erase restart code (30H). At this time, specify an optional address in the flash memory area for
the address.
If a Sector Erase Restart command is issued during sector erase, the command will be ignored.
448
CHAPTER 24 1M-BIT FLASH MEMORY
24.8
Notes on using 1M-bit Flash Memory
This section contains notes on using 1M-bit flash memory.
■ Notes on using Flash Memory
● Input of a hardware reset (RST)
To input a hardware reset when the automatic algorithm has not been started and reading is in progress, a
minimum low-level width of 500 ns must be maintained. In this case, a maximum of 500 ns is required
until data can be read from the flash memory after a hardware reset has been activated.
Similarly, to input a hardware reset when the automatic algorithm has been activated and writing or erasing
is in progress, a minimum low-level width of 50 ns must be maintained. In this case, 20 µs are required
until data can be read after the operation for initializing the flash memory has terminated.
A hardware reset during writing the data being written to be undefined. A hardware reset during erasing
may make the sector being erased unusable.
● Canceling of a software reset, watchdog timer reset
When the flash memory is being written to or erased with CPU access and if reset conditions occur while
the automatic algorithm is active, the CPU may run out of control. This occurs because these reset
conditions cause the automatic algorithm to continue without initializing the flash memory unit, possibly
preventing the flash memory unit from entering the read state when the CPU starts the sequence after the
reset has been deserted. These reset conditions must be disabled during writing to or erasing of the flash
memory.
● Program access to flash memory
When the automatic algorithm is operating, read access to the flash memory is disabled. With the memory
access mode of the CPU set to internal ROM mode, writing or erasing must be started after the program
area is switched to another area such as RAM. In this case, when sectors (SA4) containing interrupt vectors
are erased, writing or erasing interrupt processing cannot be executed. For the same reason, all interrupt
sources other than the flash memory are disabled while the automatic algorithm is operating.
Also, while the automatic algorithm is being executed, all interrupt sources except flash memory are
disabled.
● Hold function
When the CPU accepts a hold request, the Write signal WE of the flash memory unit may be skewed,
causing erroneous writing or erasing due to an erroneous write. When the acceptance of a hold request is
enabled (HDE bit of ECSR set to "1"), ensure that the WE bit of the control status register (FMCS) is "0".
● Extended intelligent I/O service (EI2OS)
Because write and erase interrupts issued to the CPU from the flash memory interface circuit cannot be
accepted by the EI2OS, they should not be used.
449
CHAPTER 24 1M-BIT FLASH MEMORY
● Applying VID
Applying VID required for the sector protect operation should always be started and terminated when the
power supply is ON.
450
CHAPTER 24 1M-BIT FLASH MEMORY
24.9
Flash Security Feature
The Flash security Controller provides possibilities to protect the content of the flash
memory from being read from external pins.
■ Flash Security Feature
One predefined address of the flash memory is assigned to the Flash Security Controller (1M-bit flash
memory: FE0001). If the protection code of "01H" is written is this address, access to the flash memory is
restricted. Once the flash memory is protected, performing the chip erase operation only can unlock the
function otherwise read/write access to the flash memory from any external pins is not generally possible.
This function is suitable for applications requiring security of self-containing and data stored in the flash
memory. If the target application requires any part of program to locate outside the microcontroller, the
Flash Security Controller can not offer the intended features. For this reason, the External Vector Fetch
mode should not be used when the protection code is set.
Programming of the flash microcontroller by standard parallel programmer may require unique set-up. For
example, with the programmer from Minato Electronics the device checking should be turned off. Writing
the protection code is generally recommended to take place at the end of the flash programming. This is to
avoid unnecessary protection during the programming.
In order to re-program the once protected flash memory, the chip erase operation should be performed.
For further information, please contact Fujitsu.
451
CHAPTER 24 1M-BIT FLASH MEMORY
24.10
Example of Programming 1M-bit Flash Memory
This section presents a programming example of 1M-bit flash memory.
■ Programming example of 1M-bit Flash Memory
NAME
FLASHWE
TITLE FLASHWE
;----------------------------------------------------------------------------------;1M-bit-FLASH sample program
;
;1: Transmits the program (address: FFC000H, sector: SA4) from FLASH to RAM
;
(address: 000700H).
;2: Executes the program on RAM.
;3: Writes the PDR1 value to FLASH (address: FE0000H, sector: SA0).
;4: Reads the written value (address: FE0000H, sector: SA0) and outputs it to PDR2.
;5: Erases the written sector (SA0).
;6: Checks and outputs erase data.
;Conditions
; - Number of bytes transmitted to RAM: 100H (256B)
; - Write/erase termination judgment
;
Judgment according to DQ5 (timing limit excess flag)
;
Judgment according to DQ6 (toggle bit flag)
;
Judgment according to RDY (FMCS)
; - Error handling
;
Hi output to P00 to P07
;
Reset command issuance
;----------------------------------------------------------------------------------;
RESOUS IOSEG
ABS=00
;"RESOUS" I/O segment definition
ORG
0000H
PDR0
RB
1
PDR1
RB
1
PDR2
RB
1
PDR3
RB
1
ORG
0010H
DDR0
RB
1
DDR1
RB
1
DDR2
RB
1
DDR3
RB
1
ORG
00A1H
CKSCR
RB
1
ORG
00AEH
FMCS
RB
1
ORG
006FH
ROMM
RB
1
RESOUS ENDS
;
SSTA
SSEG
RW
0127H
STA_T
RW
1
SSTA
ENDS
;
DATA
DSEG
ABS=0FFH
;FLASH command address
ORG
5554H
COMADR2 RW
1
ORG
0AAAAH
COMADR1 RW
1
DATA
ENDS
452
CHAPTER 24 1M-BIT FLASH MEMORY
;/////////////////////////////////////////////////////////////
;Main program (SAI)
;/////////////////////////////////////////////////////////////
CODE
CSEG
START:
;/////////////////////////////////////////////////////
; Initialization
;/////////////////////////////////////////////////////
MOV
CKSCR,#0BAH
;3-multiple setting
MOV
RP,#0
MOV
A,#!STA_T
MOV
SSB,A
MOVW
A,#STA_T
MOVW
SP,A
MOV
ROMM,#00H
;Mirror OFF
MOV
PDR0,#00H
;For error check
MOV
DDR0,#0FFH
MOV
PDR1,#00H
;Port for data input
MOV
DDR1,#00H
MOV
PDR2,#00H
;Port for data output
MOV
DDR2,#0FFH
;
///////////////////////////////////////////////////////////////////////
;
Transfer of "FLASH write erase program (FFBC00H)" to RAM (700H address)
;
///////////////////////////////////////////////////////////////////////
MOVW
A,#0700H
;Transfer destination RAM area
MOVW
A,#0C000H
;Transfer source address (program position)
MOVW
RW0,#100H
;Number of bytes to be transferred
MOVS
ADB,PCB
;Transfer of 100H from FFBC00H to 00700H
CALLP
000700H
;Jump to the address containing the transferred
;
program
;
/////////////////////////////////////////////////////
;
Data output
;
/////////////////////////////////////////////////////
OUT
MOV
A,#0FEH
MOV
ADB,A
MOVW
RW2,#0000H
MOVW
A,@RW2+00
MOV
PDR2,A
END
JMP
*
CODE
ENDS
;////////////////////////////////////////////////////////////
;FLASH write erase program (SA4)
;////////////////////////////////////////////////////////////
RAMPRG CSEG
ABS=0FFH
ORG
0C000H
;
/////////////////////////////////////////////////////
Initialization
;
/////////////////////////////////////////////////////
MOVW
RW0,#0500H
;RW0:RAM space for input data acquisition 00:0500 to
MOVW
RW2,#0000H
;RW2:Flash memory write address
FD:0000 to
MOV
A,#00H
;DTB modification
MOV
DTB,A
;Bank specification for @RW0
MOV
A,#0FDH
;ADB modification 1
MOV
ADB,A
;Bank specification for write mode specification
;
address
MOV
PDR3,#00H
;Switch initialization
MOV
DDR3,#00H
;
WAIT1
BBC
PDR3:0,WAIT1
;PDR3: 0(write start at high level)
;
453
CHAPTER 24 1M-BIT FLASH MEMORY
;////////////////////////////////////////////////
;Write (SA0)
;////////////////////////////////////////////////
MOV
A,PDR1
MOVW
@RW0+00,A
;PDR1 data allocation to RAM
MOV
FMCS,#20H
;Write mode setting
MOVW
ADB:COMADR1,#00AAH
;Flash write command 1
MOVW
ADB:COMADR2,#0055H
;Flash write command 2
MOVW
ADB:COMADR1,#00A0H
;Flash write command 3
;
MOVW
A,@RW0+00
;Input data (RW0) write to flash memory (RW2)
MOVW
@RW2+00,A
WRITE
;Wait time check
;
///////////////////////////////////////////////////////////////////////////
;
ERROR when the time limit excess check flag is set and toggle operation is
;
in progress
;
///////////////////////////////////////////////////////////////////////////
MOVW
A,@RW2+00
AND
A,#20H
;DQ5 time limit check
BZ
NTOW
;Time limit over
MOVW
A,@RW2+00
;AH
MOVW
A,@RW2+00
;AL
XORW
A
;XOR of AH and AL (1 when the values differ)
AND
A,#40H
;Is the DQ6 toggle bit different?
BNZ
ERROR
;To ERROR when the DQ6 toggle bit is different
;
///////////////////////////////////////
;
Write termination check (FMCS-RDY)
;
///////////////////////////////////////
NTOW
MOVW
A,FMCS
AND
A,#10H
;Extraction of FMCS RDY bit (bit 4)
BZ
WRITE
;End of write?
MOV
FMCS,#00H
;Write mode release
;
///////////////////////////////////////
;
Write data output
;
///////////////////////////////////////
MOVW
RW2,#0000H
;Write data output
MOVW
A,@RW2+00
MOV
PDR2,A
;
WAIT2
BBC
PDR3:1,WAIT2
;PDR3: 1(sector erase start at high level)
;
;/////////////////////////////////////////////
;Sector erase (SA0)
;/////////////////////////////////////////////
MOV
@RW2+00,#0000H
;Address initialization
MOV
FMCS,#20H
;Erase mode setting
MOVW
ADB:COMADR1,#00AAH
;Flash erase command 1
MOVW
ADB:COMADR2,#0055H
;Flash erase command 2
MOVW
ADB:COMADR1,#0080H
;Flash erase command 3
MOVW
ADB:COMADR1,#00AAH
;Flash erase command 4
MOVW
ADB:COMADR2,#0055H
;Flash erase command 5
MOV
@RW2+00,#0030H
;Issuance of erase command 6 to the sector
to be erased
ELS
;Wait time check
454
CHAPTER 24 1M-BIT FLASH MEMORY
;
;
;
;
///////////////////////////////////////////////////////////////////////////
ERROR when the time limit excess check flag is set and toggle operation is
in progress
///////////////////////////////////////////////////////////////////////////
MOVW
A,@RW2+00
AND
A,#20H
;DQ5 time limit check
BZ
NTOE
;Time limit over
MOVW
A,@RW2+00
;AH High and Low are alternately output from
MOVW
A,@RW2+00
;AL DQ6 per read during write operation.
XORW
A
;XOR of AH and AL (If the DQ6 value differs,
;
write operation is in progress (1)).
AND
A,#40H
;Is the DQ6 toggle bit High?
BNZ
ERROR
;ERROR when the DQ6 toggle bit is High
;
///////////////////////////////////////
;
Erase termination check (FMCS-RDY)
;
///////////////////////////////////////
NTOE
MOVW
A,FMCS
;
AND
A,#10H
;Extraction of FMCS RDY bit (bit 4)
BZ
ELS
;End of sector erase?
MOV
FMCS,#00H
;FLASH erase mode release
RETP
;Return to the main program
;//////////////////////////////////////////////
;Error
;//////////////////////////////////////////////
ERROR
MOV
ADB:COMADR1,#0F0H
;Reset command (read is enabled)
MOV
FMCS,#00H
;FLASH mode release
MOV
PDR0,#0FFH
;Error handling check
RETP
;Return to the main program
RAMPRG ENDS
;/////////////////////////////////////////////
VECT
CSEG
ABS=0FFH
ORG
0FFDCH
DSL
START
DB
00H
VECT
ENDS
;
END
START
455
CHAPTER 24 1M-BIT FLASH MEMORY
456
CHAPTER 25
EXAMPLES OF MB90F443G
SERIAL PROGRAMMING
CONNECTION
This chapter provides examples of serial programming
connection with the AF220/AF210/AF120/AF110 flash
microcontroller programmer manufactured by Yokogawa
Digital Computer Corporation.
25.1 Basic Configuration of MB90F443G Serial Programming Connection
25.2 Example of Serial Programming Connection (User Power Supply
Used)
25.3 Example of Serial Programming Connection (Power Supplied from
the Programmer)
25.4 Example of Minimum Connection to the Flash Microcontroller
Programmer (User Power Supply Used)
25.5 Example of Minimum Connection to the Flash Microcontroller
Programmer (Power Supplied from the Programmer)
457
CHAPTER 25 EXAMPLES OF MB90F443G SERIAL PROGRAMMING CONNECTION
25.1
Basic Configuration of MB90F443G Serial Programming
Connection
The MB90F443G supports flash ROM serial on-board programming (Fujitsu standard).
This section describes the specifications.
■ Basic Configuration of MB90F443G Serial Programming Connection
The AF220/AF210/AF120/AF110 flash microcontroller programmer manufactured by Yokogawa Digital
Computer Corporation is used for Fujitsu standard serial on-board programming. You can use either
program running in the single-chip mode or program running in the internal ROM/external bus mode.
Figure 25.1-1 shows the basic configuration of the MB90F443G serial programming connection.
Figure 25.1-1 Basic Configuration of MB90F443G Serial Programming Connection
Host interface cable
RS232C
General-purpose
common cable (AZ210)
AF220/AF210/
AF120/AF110
flash
microcontroller
programmer
+
memory card
CLK synchronous
serial
MB90F443G
user system
Stand-alone operation enabled
Note:
Ask Yokogawa Digital Computer Corporation for information about the functions and operations of
the AF220/AF210/AF120/AF110 flash microcontroller programmer, general-purpose common cable
(AZ210) for connection, and connectors.
Table 25.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming (1/2)
Pin
MD2, MD1
MD0
Function
Additional information
Mode pins
Controls programming mode from the flash microcontroller
programmer.
X0, X1
Oscillation pins
In programming mode, the CPU internal operation clock signal is
one multiple of the PLL clock signal frequency. Therefore, because
the oscillation clock frequency becomes the internal operation clock
signal, the resonator used for serial reprogramming is 3 MHz to 16
MHz.
P00, P01
Programming activation pins
Input "L" level to P00 and "H" level to P01.
RST
Reset pin
458
-
CHAPTER 25 EXAMPLES OF MB90F443G SERIAL PROGRAMMING CONNECTION
Table 25.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming (2/2)
Pin
Function
Additional information
SIN1
Serial data input pin
SOT1
Serial data output pin
SCK1
Serial clock input pin
C
C pin
This external capacitor pin is used to stabilize the power supply.
Connect a ceramic capacitor of approximately 0.1µF to the outside.
VCC
Power voltage supply pin
Programming voltage (5 V
VSS
GND pin
Common to the ground of the flash microcontroller programmer.
The UART1 is used in CLK synchronous mode.
10%)
Even if the P00, SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the
figure below is required. (The /TICS signal of the flash microcontroller programmer can be used to
disconnect the user circuit during serial programming).
Figure 25.1-2 Control Circuit
AF220/AF210/AF120/AF110
write control pin
MB90F443G
write control pin
10k
AF220/AF210/AF120/AF110
/TICS pin
User
Section "25.2 Example of Serial Programming Connection (User Power Supply Used)" to Section "25.5
Example of Minimum Connection to the Flash Microcontroller Programmer (Power Supplied from the
Programmer)" present examples the following four types of serial programming connection. See each
Section as required.
• Serial programming connection in MB90F443G internal vector mode (user power supply used)
• Serial programming connection in MB90F443G internal vector mode (power supplied from the
Programmer)
• Example of minimum connection to the flash microcontroller programmer (user power supply used)
• Example of minimum connection to the flash microcontroller programmer (power supplied from the
Programmer)
Table 25.1-2 Flash microcontroller Programmer System Configuration
(Manufactured by Yokogawa Digital Computer Corporation) (1/2)
Model
Function
AF220/AC4P
Model with Ethernet interface built in/100 to 220 V power adapter
AF210/AC4P
Standard model/100 to 220 V power adapter
AF120/AC4P
Single-key Ethernet interface model/100 to 220 V power adapter
AF110/AC4P
Single-key model/100 to 220 V power adapter
Mainframe
459
CHAPTER 25 EXAMPLES OF MB90F443G SERIAL PROGRAMMING CONNECTION
Table 25.1-2 Flash microcontroller Programmer System Configuration
(Manufactured by Yokogawa Digital Computer Corporation) (2/2)
Model
Function
AZ221
PC/AT RS232C cable only for Programmer
AZ210
Standard target probe (a), length: 1 m
FF201
Fujitsu F2MC-16LX flash microcontroller control model
AZ290
Remote controller
/P2
2 MB PC card (option) for flash memory sizes of up to 128 KB
/P4
4 MB PC card (option) for flash memory sizes of up to 512 KB
Inquiries: Yokogawa Digital Computer Corporation
Telephone number: (81)-42-333-6224
Note:
The AF200 flash microcontroller programmer, which is not supported now, can be used by using
control module FF201. For the serial programming connection information, see the following section,
"■ Oscillation Clock Frequency and Serial Clock Input Frequency".
460
CHAPTER 25 EXAMPLES OF MB90F443G SERIAL PROGRAMMING CONNECTION
■ Oscillation Clock Frequency and Serial Clock Input Frequency
The formula shown below can be used to calculate the maximum serial clock frequency that can be input to
the MB90F443G.
Maximum serial clock frequency that can be input = 0.125 x oscillation clock frequency
Consequently, change the serial clock input frequency by setting the serial clock frequency of the flash
microcontroller programmer according to the current oscillation clock frequency.
Table 25.1-3 Examples of the Maximum Serial Clock Frequency That Can Be Input
Oscillation or
External clock
frequency
Maximum serial clock
frequency that can be input
for the microcontroller
Maximum serial clock
frequency that can be set
with AF220/AF210/AF120/
AF110
Maximum serial clock
frequency that can be set
with AF200
4 MHz
500 kHz
500 kHz
500 kHz
8 MHz
1 MHz
850 kHz
500 kHz
16 MHz
2 MHz
1.25 MHz
500 kHz
461
CHAPTER 25 EXAMPLES OF MB90F443G SERIAL PROGRAMMING CONNECTION
25.2
Example of Serial Programming Connection
(User Power Supply Used)
Figure 25.2-1 shows an example of serial programming connection when the
microcontroller power voltage is supplied from the user power supply. The values 1 and
0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/
AF120/AF110 programmer.
Serial reprogramming mode: MD2, MD1, MD0 = 110B
■ Example of Serial Programming Connection (User Power Supply Used)
Figure 25.2-1 Example of Serial Programming Connection for MB90F443G Single-chip Modes
(User Power Supply Used)
AF220/AF210/AF120/AF110
flash microcontroller
programmer
TAUX3
User system
MB90F443G
Connector
DX10-28S
(19)
MD2
10k
10k
MD1
10k
TMODE
MD0
X0
(12)
3 MHz to 16 MHz
X1
TAUX
(23)
TICS
(10)
P00
10k
User
10k
User
HST
10k
TRES
RST
(5)
10k
P01
C
User
TTXD
TRXD
TCK
(13)
(27)
(6)
TVcc
(2)
GND
(7,8,
14,15,
21, 22
1, 28)
SIN1
SOT1
SCK1
Vcc
User power
supply
Vss
Pin 14
Pins 3, 4, 9, 11, 16, 17, 18, 20,
24, 25, and 26 are open.
DX10-28S: Right-angle type
462
Pin 1
DX10-28S
Pin 28
Pin 15
Connector (Hirose Electronics Ltd.)
pin arrangement
CHAPTER 25 EXAMPLES OF MB90F443G SERIAL PROGRAMMING CONNECTION
•
Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the
figure below is required in the same way that it is for P00. (The /TICS signal of the flash
microcontroller programmer can be used to disconnect the user circuit during serial programming.)
AF220/AF210/
AF120/AF110
write control pin
MB90F443G
write control pin
10k
AF220/AF210/
AF120/AF110
/TICS pin
User
• Connect the AF220/AF210/AF120/AF110 while the user power is off.
463
CHAPTER 25 EXAMPLES OF MB90F443G SERIAL PROGRAMMING CONNECTION
25.3
Example of Serial Programming Connection
(Power Supplied from the Programmer)
Figure 25.3-1 shows an example of serial programming connection when the
microcontroller power voltage is supplied from the programmer. The values 1 and 0 are
input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/AF120/
AF110 programmer.
Serial reprogramming mode: MD2, MD1, MD0 = 110B
■ Example of Serial Programming Connection (Power Supplied from the Programmer)
Figure 25.3-1 Example of Serial Programming Connection for MB90F443G Single-chip Modes (Power
Supplied from the Programmer)
AF220/AF210/AF120/AF110
flash microcontroller
programmer
TAUX3
User system
MB90F443G
Connector
DX10-28S
(19)
MD2
10k
10k
MD1
10k
TMODE
MD0
X0
(12)
3 MHz to 16 MHz
X1
TAUX
(23)
P00
10k
TICS
(10)
User
10k
User
HST
10k
10k
TRES
(5)
RST
10k
P01
C
User
TTXD
TRXD
TCK
TVcc
Vcc
TVPP1
GND
(13)
(27)
(6)
(2)
(3)
(16)
SIN1
SOT1
SCK1
Vcc
(7, 8,
14,15,
21, 22
1, 28)
Pins 4, 9, 11, 17, 18, 20,
24, 25, and 26 are open.
Vss
Pin 14
Pin 1
Pin 28
Pin 15
DX10-28S
DX10-28S: Right-angle type
Connector (Hirose Electronics Ltd.)
pin arrangement
464
CHAPTER 25 EXAMPLES OF MB90F443G SERIAL PROGRAMMING CONNECTION
• Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the
figure below is required in the same way that it is for P00. (The /TICS signal of the flash microcontroller
programmer can be used to disconnect the user circuit during serial programming.)
AF220/AF210/
AF120/AF110
write control pin
MB90F443G
write control pin
10k
AF220/AF210/
AF120/AF110
/TICS pin
User
• Connect the AF220/AF210/AF120/AF110 while the user power is off.
• When the programming power is supplied from the AF220/AF210/AF120/AF110, be careful not to
short-circuit the user power supply.
465
CHAPTER 25 EXAMPLES OF MB90F443G SERIAL PROGRAMMING CONNECTION
25.4
Example of Minimum Connection to the Flash
Microcontroller Programmer (User Power Supply Used)
Figure 25.4-1 is an example of the minimum connection to the flash microcontroller
programmer when the user power supply is used.
Serial reprogramming mode: MD2, MD1, MD0 = 110B
■ Example of Minimum Connection to the Flash Microcontroller Programmer
(User Power Supply Used)
For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcontroller programmer need
not be connected if the pins are set as described below.
Figure 25.4-1 Example of Minimum Connection to the MB90F443G Flash Microcontroller Programmer
(User Power Supply Used)
AF220/AF210/AF120/AF110 User system
flash microcontroller
1 for serial
reprogramming
programmer
MB90F443G
10k
MD2
1 for serial
reprogramming
10k
10k
MD1
10k
10k
MD0
0 for serial rewrite
10k
X0
3 MHz to 16 MHz
X1
0 for serial
reprogramming
P00
10k
10k
User circuit
P01
1 for serial reprogramming
User
10k
circuit
10k
Connector
DX10-28S
GND
10k
(5)
(13)
(27)
(6)
(2)
TRES
TTXD
TRXD
TCK
TVcc
(7,8,
14,15,
21,22,
1,28)
RST
SIN1
SOT1
SCK1
Vcc
User power supply
Pins 3, 4, 9, 10, 11, 12, 16, 17, 18, 19,
20, 23, 24, 25, and 26 are open.
DX10-28S: Right-angle type
HST
C
Vss
Pin 14
Pin 1
Pin 28
Pin 15
DX10-28S
Connector (Hirose Electronics Ltd.)
pin arrangement
466
CHAPTER 25 EXAMPLES OF MB90F443G SERIAL PROGRAMMING CONNECTION
•
Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the
figure below is required. (The /TICS signal of the flash microcontroller programmer can be used to
disconnect the user circuit during serial programming.)
AF220/AF210/
AF120/AF110
write control pin
MB90F443G
write control pin
10k
AF220/AF210/
AF120/AF110
/TICS pin
User
• Connect the AF220/AF210/AF120/AF110 while the user power is off.
467
CHAPTER 25 EXAMPLES OF MB90F443G SERIAL PROGRAMMING CONNECTION
25.5
Example of Minimum Connection to the Flash
Microcontroller Programmer
(Power Supplied from the Programmer)
Figure 25.5-1 is an example of the minimum connection to the flash microcontroller
programmer when power is supplied from the programmer.
Serial reprogramming mode: MD2, MD1, MD0 = 110B
■ Example of Minimum Connection to the Flash Microcontroller Programmer
(Power Supplied from the Programmer)
For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcontroller programmer need
not be connected if the pins are set as described below.
Figure 25.5-1 Example of Minimum Connection to the MB90F443G Flash Microcontroller Programmer
(Power Supplied from the Programmer)
AF220/AF210/AF120/AF110 User system
flash microcontroller
1 for serial
programmer
reprogramming
MB90F443G
10k
MD2
1 for serial
reprogramming
10k
10k
10k
10k
MD1
MD0
0 for serial rewrite
10k
X0
3 MHz to 16 MHz
X1
0 for serial
reprogramming
P00
10k
10k
User circuit
P01
1 for serial reprogramming
User
10k
circuit
Connector
DX10-28S
TRES
TTXD
TRXD
TCK
TVcc
Vu
TVPP1
GND
(5)
(13)
(27)
(6)
(2)
(3)
(16)
HST
C
10k
RST
SIN1
SOT1
SCK1
Vcc
(7,8,
14,15,
21,22,
1,28)
Pins 4, 9, 10, 11, 12, 17, 18, 19,
20, 23, 24, 25, and 26 are open.
DX10-28S: Right-angle type
Vss
Pin 14
Pin 1
Pin 28
Pin 15
DX10-28S
Connector (Hirose Electronics Ltd.)
pin arrangement
468
CHAPTER 25 EXAMPLES OF MB90F443G SERIAL PROGRAMMING CONNECTION
•
Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the
figure below is required. (The /TICS signal of the flash microcontroller programmer can be used to
disconnect the user circuit during serial programming.)
AF220/AF210/
AF120/AF110
write control pin
MB90F443G
write control pin
10k
AF220/AF210/
AF120/AF110
/TICS pin
User
• Connect the AF220/AF210/AF120/AF110 while the user power is off.
• When the programming power is supplied from the AF220/AF210/AF120/AF110, be careful not to
short-circuit the user power supply.
469
CHAPTER 25 EXAMPLES OF MB90F443G SERIAL PROGRAMMING CONNECTION
470
APPENDIX
The appendix provides I/O maps and outlines
instructions.
APPENDIX A I/O Maps
APPENDIX B Instructions
471
APPENDIX
APPENDIX A
I/O Maps
Table A-1 lists addresses to be assigned to the registers in the peripheral blocks.
■ I/O Maps
Table A-1 I/O Map (1/8)
Address
Register
Abbreviation
Access
Peripheral
Initial value
000000H
Port 0 data register
PDR0
R/W
Port 0
XXXXXXXX
000001H
Port 1 data register
PDR1
R/W
Port 1
XXXXXXXX
000002H
Port 2 data register
PDR2
R/W
Port 2
XXXXXXXX
000003H
Port 3 data register
PDR3
R/W
Port 3
XXXXXXXX
000004H
Port 4 data register
PDR4
R/W
Port 4
XXXXXXXX
000005H
Port 5 data register
PDR5
R/W
Port 5
XXXXXXXX
000006H
Port 6 data register
PDR6
R/W
Port 6
XXXXXXXX
000007H
Port 7 data register
PDR7
R/W
Port 7
XXXXXXXX
000008H
Port 8 data register
PDR8
R/W
Port 8
XXXXXXXX
000009H
Port 9 data register
PDR9
R/W
Port 9
XXXXXXXX
00000AH
Port A data register
PDRA
R/W
Port A
-------0
00000BH
Port input levels select register
PILR
R/W
Ports
00000000
00000CH
CAN2 RX/TX pin switching
register
CANSWR
R/W
CAN1/2
------00
00000DH
to
00000FH
Reserved
000010H
Port 0 direction register
DDR0
R/W
Port 0
00000000
000011H
Port 1 direction register
DDR1
R/W
Port 1
00000000
000012H
Port 2 direction register
DDR2
R/W
Port 2
00000000
000013H
Port 3 direction register
DDR3
R/W
Port 3
00000000
000014H
Port 4 direction register
DDR4
R/W
Port 4
00000000
000015H
Port 5 direction register
DDR5
R/W
Port 5
00000000
000016H
Port 6 direction register
DDR6
R/W
Port 6
00000000
000017H
Port 7 direction register
DDR7
R/W
Port 7
00000000
000018H
Port 8 direction register
DDR8
R/W
Port 8
00000000
472
APPENDIX A I/O Maps
Table A-1 I/O Map (2/8)
Address
Register
Abbreviation
Access
Peripheral
Initial value
000019H
Port 9 direction register
DDR9
R/W
Port 9
00000000
00001AH
Port A direction register
DDRA
R/W
Port A
-------0
00001BH
Analog Input Enable
ADER
R/W
Port 6, A/D
11111111
00001CH
Port 0 Pullup control register
PUCR0
R/W
Port 0
00000000
00001DH
Port 1 Pullup control register
PUCR1
R/W
Port 1
00000000
00001EH
Port 2 Pullup control register
PUCR2
R/W
Port 2
00000000
00001FH
Port 3 Pullup control register
PUCR3
R/W
Port 3
00000000
000020H
Serial Mode Control Register 0
UMC0
R/W
000021H
Status Register 0
USR0
R/W
00000100
00010000
UART0
UIDR0/
UODR0
R/W
XXXXXXXX
Rate and Data Register 0
URD0
R/W
0000000X
000024H
Serial Mode Register 1
SMR1
R/W
00000000
000025H
Serial Control Register 1
SCR1
R/W
00000100
000026H
Input/Output Data Register 1
SIDR1/
SODR1
R/W
XXXXXXXX
000027H
Serial Status Register 1
SSR1
R/W
00001000
000028H
UART1 Prescaler Control
Register
U1CDCR
R/W
0---0000
000029H
Edge Selector
SES1
R/W
-------0
000022H
Input/Output Data Register 0
000023H
00002AH
UART1
Reserved
00002BH
Serial I/O Prescaler
00002CH
SCDCR
R/W
0---1111
Serial Mode Control register
SMCS
R/W
----0000
00002DH
Serial Mode Control register
SMCS
R/W
00002EH
Serial Data register
SDR
R/W
XXXXXXXX
00002FH
Edge Selector
SES2
R/W
-------0
000030H
External Interrupt Enable register
ENIR
R/W
00000000
000031H
External Interrupt Request
register
EIRR
R/W
External Interrupt Level register
ELVR
000032H
000033H
Serial I/O
00000010
XXXXXXXX
External Interrupt
00000000
R/W
00000000
473
APPENDIX
Table A-1 I/O Map (3/8)
Address
Register
Abbreviation
Access
Peripheral
Initial value
000034H
A/D Control Status register 0
ADCS0
R/W
000035H
A/D Control Status register 1
ADCS1
R/W
000036H
A/D Data register 0
ADCR0
R
XXXXXXXX
000037H
A/D Data register 1
ADCR1
R/W
00001-XX
000038H
PPG0 operation mode control
register
PPGC0
R/W
0-000--1
000039H
PPG1 operation mode control
register
PPGC1
R/W
00003AH
PPG0 and PPG1 clock selection
register
PPG01
R/W
00000000
00000000
A/D Converter
00003BH
16-bit Programable
Pulse Generator 0/1
0-000001
000000--
Reserved
00003CH
PPG2 operation mode control
register
PPGC2
R/W
00003DH
PPG3 operation mode control
register
PPGC3
R/W
00003EH
PPG2 and PPG3 clock selection
register
PPG23
R/W
00003FH
0-000--1
16-bit Programable
Pulse Generator 2/3
0-000001
000000--
Reserved
000040H
PPG4 operation mode control
register
PPGC4
R/W
000041H
PPG5 operation mode control
register
PPGC5
R/W
000042H
PPG4 and PPG5 clock selection
register
PPG45
R/W
000043H
0-000--1
16-bit Programable
Pulse Generator 4/5
0-000001
000000--
Reserved
000044H
PPG6 operation mode control
register
PPGC6
R/W
000045H
PPG7 operation mode control
register
PPGC7
R/W
000046H
PPG6 and PPG7 clock selection
register
PPG67
R/W
000047H
to
00004BH
0-000--1
16-bit Programable
Pulse Generator 6/7
0-000001
000000--
Reserved
00004CH
Input Capture Control Status 0/1
ICS01
R/W
Input Capture 0/1
00000000
00004DH
Input Capture Control Status 2/3
ICS23
R/W
Input Capture 2/3
00000000
00004EH
Input Capture Control Status 4/5
ICS45
R/W
Input Capture 4/5
00000000
00004FH
Input Capture Control Status 6/7
ICS67
R/W
Input Capture 6/7
00000000
474
APPENDIX A I/O Maps
Table A-1 I/O Map (4/8)
Address
000050H
000051H
000052H
000053H
000054H
000055H
000056H
000057H
Register
Abbreviation
Access
TMCSR0
R/W
Peripheral
Initial value
00000000
Timer Control Status register 0
----0000
16-bit Reload Timer 0
Timer register 0/Reload register 0
XXXXXXXX
TMR0/
TMRLR0
R/W
TMCSR1
R/W
XXXXXXXX
00000000
Timer Control Status register 1
----0000
16-bit Reload Timer 1
Timer register 1/Reload register 1
XXXXXXXX
TMR1/
TMRLR1
R/W
XXXXXXXX
000058H
Output Compare Control Status
register 0
OCS0
R/W
000059H
Output Compare Control Status
register 1
OCS1
R/W
---00000
00005AH
Output Compare Control Status
register 2
OCS2
R/W
0000--00
00005BH
Output Compare Control Status
register 3
OCS3
R/W
00005CH
to
00006BH
00006CH
00006DH
0000--00
Output Compare 0/1
Output Compare 2/3
---00000
Reserved for CAN 2 Interface . Refer to "CHAPTER 21 CAN CONTROLLER"
00000000
Timer Data register
TCDT
R/W
I/O Timer
00006EH
Timer Control register
00006FH
ROM Mirror function selection
register
TCCS
R/W
ROMM
R/W
00000000
ROM Mirror
000070H
to
00007FH
Reserved for CAN 0 Interface . Refer to "CHAPTER 21 CAN CONTROLLER"
000080H
to
00008FH
Reserved for CAN 1 Interface . Refer to "CHAPTER 21 CAN CONTROLLER"
000090H
to
00009DH
Reserved
00009EH
Program address detection
control status register
00009FH
0000A0H
00000000
-------1
PACSR
R/W
Address match
detection function
00000000
Delayed Interrupt/release register
DIRR
R/W
Delayed Interrupt
-------0
Low-power Mode control register
LPMCR
R/W
Low Power Controller
00011000
475
APPENDIX
Table A-1 I/O Map (5/8)
Address
0000A1H
Register
Clock selection register
Abbreviation
Access
Peripheral
Initial value
CKSCR
R/W
Low Power Controller
11111100
0000A2H
to
0000A4H
Reserved
0000A5H
Automatic ready function select
reg.
ARSR
W
0000A6H
External address output control
reg.
HACR
W
0000A7H
Bus control signal selection
register
ECSR
W
0000A8H
Watchdog Timer Control register
WDTC
R/W
Watchdog Timer
XXXXX111
0000A9H
Time-Base Timer Control register
TBTC
R/W
Time-Base Timer
1--00100
0000AAH
Watch timer control register
WTC
R/W
Watch Timer
1X001000
Flash Memory
000X0000
0000ABH
to
0000ADH
0000AEH
0000AFH
476
0011--00
External Memory
Access
00000000
0000000-
Reserved
Flash memory Control Status
register
(Flash only, otherwise reserved)
FMCS
R/W
Reserved
APPENDIX A I/O Maps
Table A-1 I/O Map (6/8)
Address
Register
Abbreviation
Access
Peripheral
Initial value
0000B0H
Interrupt control register 00
ICR00
R/W
00000111
0000B1H
Interrupt control register 01
ICR01
R/W
00000111
0000B2H
Interrupt control register 02
ICR02
R/W
00000111
0000B3H
Interrupt control register 03
ICR03
R/W
00000111
0000B4H
Interrupt control register 04
ICR04
R/W
00000111
0000B5H
Interrupt control register 05
ICR05
R/W
00000111
0000B6H
Interrupt control register 06
ICR06
R/W
00000111
0000B7H
Interrupt control register 07
ICR07
R/W
0000B8H
Interrupt control register 08
ICR08
R/W
00000111
0000B9H
Interrupt control register 09
ICR09
R/W
00000111
0000BAH
Interrupt control register 10
ICR10
R/W
00000111
0000BBH
Interrupt control register 11
ICR11
R/W
00000111
0000BCH
Interrupt control register 12
ICR12
R/W
00000111
0000BDH
Interrupt control register 13
ICR13
R/W
00000111
0000BEH
Interrupt control register 14
ICR14
R/W
00000111
0000BFH
Interrupt control register 15
ICR15
R/W
00000111
00000111
Interrupt controller
0000C0H
to
0000FFH
External
001FF0H
Program address detection
register 0
001FF1H
Program address detection
register 0
001FF2H
Program address detection
register 0
R/W
001FF3H
Program address detection
register 1
R/W
001FF4H
Program address detection
register 1
001FF5H
Program address detection
register 1
003900H
Reload L
003901H
PADR0
PADR1
R/W
XXXXXXXX
R/W
XXXXXXXX
Address match
detection function
XXXXXXXX
XXXXXXXX
R/W
XXXXXXXX
R/W
XXXXXXXX
PRLL0
R/W
XXXXXXXX
Reload H
PRLH0
R/W
003902H
Reload L
PRLL1
R/W
003903H
Reload H
PRLH1
R/W
16-bit Programable
Pulse Generator 0/1
XXXXXXXX
XXXXXXXX
XXXXXXXX
477
APPENDIX
Table A-1 I/O Map (7/8)
Address
Register
Abbreviation
Access
Peripheral
Initial value
003904H
Reload L
PRLL2
R/W
003905H
Reload H
PRLH2
R/W
003906H
Reload L
PRLL3
R/W
003907H
Reload H
PRLH3
R/W
XXXXXXXX
003908H
Reload L
PRLL4
R/W
XXXXXXXX
003909H
Reload H
PRLH4
R/W
00390AH
Reload L
PRLL5
R/W
00390BH
Reload H
PRLH5
R/W
XXXXXXXX
00390CH
Reload L
PRLL6
R/W
XXXXXXXX
00390DH
Reload H
PRLH6
R/W
00390EH
Reload L
PRLL7
R/W
00390FH
Reload H
PRLH7
R/W
003910H
to
003917H
XXXXXXXX
16-bit Programable
Pulse Generator 2/3
16-bit Programable
Pulse Generator 4/5
16-bit Programable
Pulse Generator 6/7
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Reserved
003918H
Input Capture 0
IPCP0
R
003919H
Input Capture 0
IPCP0
R
00391AH
Input Capture 1
IPCP1
R
XXXXXXXX
00391BH
Input Capture 1
IPCP1
R
XXXXXXXX
00391CH
Input Capture 2
IPCP2
R
XXXXXXXX
00391DH
Input Capture 2
IPCP2
R
00391EH
Input Capture 3
IPCP3
R
XXXXXXXX
00391FH
Input Capture 3
IPCP3
R
XXXXXXXX
003920H
Input Capture 4
IPCP4
R
XXXXXXXX
003921H
Input Capture 4
IPCP4
R
003922H
Input Capture 5
IPCP5
R
XXXXXXXX
003923H
Input Capture 5
IPCP5
R
XXXXXXXX
003924H
Input Capture 6
IPCP6
R
XXXXXXXX
003925H
Input Capture 6
IPCP6
R
003926H
Input Capture 7
IPCP7
R
XXXXXXXX
003927H
Input Capture 7
IPCP7
R
XXXXXXXX
478
XXXXXXXX
XXXXXXXX
Input Captue 0/1
XXXXXXXX
Input Captue 2/3
XXXXXXXX
Input Captue 4/5
XXXXXXXX
Input Captue 6/7
APPENDIX A I/O Maps
Table A-1 I/O Map (8/8)
Address
Register
Abbreviation
Access
Peripheral
Initial value
003928H
Output Compare 0
OCCP0
R/W
003929H
Output Compare 0
OCCP0
R/W
00392AH
Output Compare 1
OCCP1
R/W
XXXXXXXX
00392BH
Output Compare 1
OCCP1
R/W
XXXXXXXX
00392CH
Output Compare 2
OCCP2
R/W
XXXXXXXX
00392DH
Output Compare 2
OCCP2
R/W
00392EH
Output Compare 3
OCCP3
R/W
XXXXXXXX
00392FH
Output Compare 3
OCCP3
R/W
XXXXXXXX
XXXXXXXX
XXXXXXXX
Output Compare 0/1
XXXXXXXX
Output Compare 2/3
003930H
to
0039FFH
Reserved
003A00H
to
003AFFH
Reserved for CAN 0 Interface. Refer to"CHAPTER 21 CAN CONTROLLER"
003B00H
to
003BFFH
Reserved for CAN 0 Interface. Refer to "CHAPTER 21 CAN CONTROLLER"
003C00H
to
003CFFH
Reserved for CAN 1 Interface. Refer to"CHAPTER 21 CAN CONTROLLER"
003D00H
to
003DFFH
Reserved for CAN 1 Interface. Refer to "CHAPTER 21 CAN CONTROLLER"
003E00H
to
003EFFH
Reserved for CAN 2 Interface. Refer to "CHAPTER 21 CAN CONTROLLER"
003F00H
to
003FFFH
Reserved for CAN 2 Interface. Refer to "CHAPTER 21 CAN CONTROLLER"
• Expression of initial value 0: Initial value "0"/1: Initial value "1"/X: Initial value is undefined/"-": Initial value is
undefined (none).
• The address under 0000FFH is a reserved area. The external bus access signal cannot be used.
• The boundary(#H) between RAM area and reserved area changes depending on each product.
Note: As to a writable bit, the initialized value by reset is described as an initial value. It is not the read value and you
need the care.
And, as to LPMCR/CKSCR/WDTC, the initialized case and the case that is not initialized are available. Here, the
inial value when initialized is described.
• Compare registers 0 to 3 use free-run timer 2, and compare registers 4 to 7 use free-run timer 1. And, free-run timer 1
is used in input capture.
479
APPENDIX
● Explanation of Read/Write
R/W: Readable/writable
R:
Read only
W:
Write only
● Explanation of initial value
0: the initial value of this bit is "0".
1: the initial value of this bit is "1".
X: the initial value of this bit is undefined.
-: this bit is unused. the initial value is undefined.
Note:
Address 00000DH to 0000FFH are a reserved area. When read accessing to these addresses, "X" is
read. However, it is disabled to execute write accessing to these addresses.
480
APPENDIX B Instructions
APPENDIX B Instructions
APPENDIX B describes the instructions used by the F2MC-16LX.
B.1 Instruction Types
B.2 Addressing
B.3 Direct Addressing
B.4 Indirect Addressing
B.5 Execution Cycle Count
B.6 Effective address field
B.7 How to Read the Instruction List
B.8 F2MC-16LX Instruction List
B.9 Instruction Map
Code: CM44-00202-1E
481
APPENDIX
B.1
Instruction Types
The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an
effective address field of each instruction or using the instruction code itself.
■ Instruction Types
The F2MC-16LX supports the following 351 types of instructions:
482
•
41 transfer instructions (byte)
•
38 transfer instructions (word or long word)
•
42 addition/subtraction instructions (byte, word, or long word)
•
12 increment/decrement instructions (byte, word, or long word)
•
11 comparison instructions (byte, word, or long word)
•
11 unsigned multiplication/division instructions (word or long word)
•
11 signed multiplication/division instructions (word or long word)
•
39 logic instructions (byte or word)
•
6 logic instructions (long word)
•
6 sign inversion instructions (byte or word)
•
1 normalization instruction (long word)
•
18 shift instructions (byte, word, or long word)
•
50 branch instructions
•
6 accumulator operation instructions (byte or word)
•
28 other control instructions (byte, word, or long word)
•
21 bit operation instructions
•
10 string instructions
APPENDIX B Instructions
B.2
Addressing
With the F2MC-16LX, the address format is determined by the instruction effective
address field or the instruction code itself (implied). When the address format is
determined by the instruction code itself, specify an address in accordance with the
instruction code used. Some instructions permit the user to select several types of
addressing.
■ Addressing
The F2MC-16LX supports the following 23 types of addressing:
•
Immediate (#imm)
•
Register direct
•
Direct branch address (addr16)
•
Physical direct branch address (addr24)
•
I/O direct (io)
•
Abbreviated direct address (dir)
•
Direct address (addr16)
•
I/O direct bit address (io:bp)
•
Abbreviated direct bit address (dir:bp)
•
Direct bit address (addr16:bp)
•
Vector address (#vct)
•
Register indirect (@RWj j = 0 to 3)
•
Register indirect with post increment (@RWj+ j = 0 to 3)
•
Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
•
Long register indirect with displacement (@RLi + disp8 i = 0 to 3)
•
Program counter indirect with displacement (@PC + disp16)
•
Register indirect with base index (@RW0 + RW7, @RW1 + RW7)
•
Program counter relative branch address (rel)
•
Register list (rlst)
•
Accumulator indirect (@A)
•
Accumulator indirect branch address (@A)
•
Indirectly-specified branch address (@ear)
•
Indirectly-specified branch address (@eam)
483
APPENDIX
■ Effective Address Field
Table B.2-1 lists the address formats specified by the effective address field.
Table B.2-1 Effective Address Field
Code
Representation
00
R0
RW0
RL0
01
R1
RW1
(RL0)
02
R2
RW2
RL1
03
R3
RW3
(RL1)
04
R4
RW4
RL2
05
R5
RW5
(RL2)
06
R6
RW6
RL3
07
R7
RW7
(RL3)
08
@RW0
09
@RW1
Address format
Default bank
Register direct: Individual parts correspond to the
byte, word, and long word types in order from the
left.
None
DTB
DTB
Register indirect
0A
@RW2
ADB
0B
@RW3
SPB
0C
@RW0+
DTB
0D
@RW1+
DTB
Register indirect with post increment
0E
@RW2+
ADB
0F
@RW3+
SPB
10
@RW0+disp8
DTB
11
@RW1+disp8
DTB
Register indirect with 8-bit displacement
12
@RW2+disp8
ADB
13
@RW3+disp8
SPB
14
@RW4+disp8
DTB
15
@RW5+disp8
DTB
Register indirect with 8-bit displacement
16
@RW6+disp8
ADB
17
@RW7+disp8
SPB
18
@RW0+disp16
DTB
19
@RW1+disp16
DTB
Register indirect with 16-bit displacement
484
1A
@RW2+disp16
ADB
1B
@RW3+disp16
SPB
1C
@RW0+RW7
Register indirect with index
DTB
1D
@RW1+RW7
Register indirect with index
DTB
1E
@PC+disp16
PC indirect with 16-bit displacement
PCB
1F
addr16
Direct address
DTB
APPENDIX B Instructions
B.3
Direct Addressing
An operand value, register, or address is specified explicitly in direct addressing mode.
■ Direct Addressing
● Immediate addressing (#imm)
Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32).
Figure B.3-1 Example of Immediate Addressing (#imm)
MOVW A, #01212H (This instruction stores the operand value in A.)
Before execution
A 2233
4455
After execution
A 4455
1 2 1 2 (Some instructions transfer AL to AH.)
● Register direct addressing
Specify a register explicitly as an operand. Table B.3-1 lists the registers that can be specified. Figure B.32 shows an example of register direct addressing.
Table B.3-1 Direct Addressing Registers
General-purpose register
Special-purpose register
Byte
R0, R1, R2, R3, R4, R5, R6, R7
Word
RW0, RW1, RW2, RW3, RW4, RW5, RW6,
RW7
Long word
RL0, RL1, RL2, RL3
Accumulator
A, AL
Pointer
SP *
Bank
PCB, DTB, USB, SSB, ADB
Page
DPR
Control
PS, CCR, RP, ILM
*: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on
the value of the S flag bit in the condition code register (CCR). For branch instructions, the program
counter (PC) is not specified in an instruction operand but is specified implicitly.
485
APPENDIX
Figure B.3-2 Example of Register Direct Addressing
MOV R0, A (This instruction transfers the eight low-order bits of A to the generalpurpose register R0.)
Before execution
A 0716
2534
Memory space
R0
After execution
A 0716
2564
??
Memory space
R0
34
● Direct branch addressing (addr16)
Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which
indicates the branch destination in the logical address space. Direct branch addressing is used for an
unconditional branch, subroutine call, or software interrupt instruction. Bit23 to bit16 of the address are
specified by the program counter bank register (PCB).
Figure B.3-3 Example of Direct Branch Addressing (addr16)
JMP 3B20H (This instruction causes an unconditional branch by direct branch
addressing in a bank.)
Before execution
After execution
486
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
62
4F3C21H
20
4F3C22H
3B
JMP 3B20H
APPENDIX B Instructions
● Physical direct branch addressing (addr24)
Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical
direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction.
Figure B.3-4 Example of Direct Branch Addressing (addr24)
JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit
addressing.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 3 3
Memory space
333B20H
Next instruction
4F3C20H
63
4F3C21H
20
4F3C22H
3B
4F3C23H
33
JMPP 333B20H
● I/O direct addressing (io)
Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the
physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB)
and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an
instruction using I/O direct addressing.
Figure B.3-5 Example of I/O Direct Addressing (io)
MOVW A, i : 0C0H (This instruction reads data by I/O direct addressing and stores it
in A.)
Before execution
After execution
A 0716
2534
Memory space
0000C0H
EE
0000C1H
FF
A 2534 FFEE
487
APPENDIX
● Abbreviated direct addressing (dir)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB).
Figure B.3-6 Example of Abbreviated Direct Addressing (dir)
MOV S : 20H, A (This instruction writes the contents of the eight low-order bits of A in
abbreviated direct addressing mode.)
Before execution
A 4455
DPR 6 6
After execution
A 4455
DPR 6 6
1212
DTB 7 7
Memory space
776620H
1212
DTB 7 7
??
Memory space
776620H
12
● Direct addressing (addr16)
Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are
specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for
this mode of addressing.
Figure B.3-7 Example of Direct Addressing (addr16)
MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.)
Before execution
After execution
488
A 2020
A AABB
AABB
0123
DTB 5 5
DTB 5 5
Memory space
553B21H
01
553B20H
23
APPENDIX B Instructions
● I/O direct bit addressing (io:bp)
Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp",
where the larger number indicates the most significant bit (MSB) and the lower number indicates the least
significant bit (LSB).
Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp)
SETB i : 0C1H : 0 (This instruction sets bits by I/O direct bit addressing.)
Memory space
Before execution
0000C1H
00
Memory space
After execution
0000C1H
01
● Abbreviated direct bit addressing (dir:bp)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure B.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp)
SETB S : 10H : 0 (This instruction sets bits by abbreviated direct bit addressing.)
Memory space
Before execution
DTB 5 5
DPR 6 6
556610H
00
Memory space
After execution
DTB 5 5
DPR 6 6
556610H
01
● Direct bit addressing (addr16:bp)
Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure B.3-10 Example of Direct Bit Addressing (addr16:bp)
SETB 2222H : 0 (This instruction sets bits by direct bit addressing.)
Memory space
Before execution
DTB 5 5
552222H
00
Memory space
After execution
DTB 5 5
552222H
01
489
APPENDIX
● Vector Addressing (#vct)
Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector
numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction.
Figure B.3-11 Example of Vector Addressing (#vct)
CALLV #15 (This instruction causes a branch to the address indicated by the interrupt
vector specified in an operand.)
Before execution
PC 0 0 0 0
Memory space
PCB F F
After execution
FFC000H
EF
FFFFE0H
00
FFFFE1H
D0
CALLV #15
PC D 0 0 0
PCB F F
Table B.3-2 CALLV Vector List
Instruction
Vector address L
Vector address H
CALLV #0
XXFFFEH
XXFFFFH
CALLV #1
XXFFFCH
XXFFFDH
CALLV #2
XXFFFAH
XXFFFBH
CALLV #3
XXFFF8H
XXFFF9H
CALLV #4
XXFFF6H
XXFFF7H
CALLV #5
XXFFF4H
XXFFF5H
CALLV #6
XXFFF2H
XXFFF3H
CALLV #7
XXFFF0H
XXFFF1H
CALLV #8
XXFFEEH
XXFFEFH
CALLV #9
XXFFECH
XXFFEDH
CALLV #10
XXFFEAH
XXFFEBH
CALLV #11
XXFFE8H
XXFFE9H
CALLV #12
XXFFE6H
XXFFE7H
CALLV #13
XXFFE4H
XXFFE5H
CALLV #14
XXFFE2H
XXFFE3H
CALLV #15
XXFFE0H
XXFFE1H
Note: A PCB register value is set in XX.
Note:
When the program counter bank register (PCB) is FFH, the vector area overlaps the vector area of
INT #vct8 (#0 to #7). Use vector addressing carefully (see Table B.3-2 ).
490
APPENDIX B Instructions
B.4
Indirect Addressing
In indirect addressing mode, an address is specified indirectly by the address data of
an operand.
■ Indirect Addressing
● Register indirect addressing (@RWj j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to
23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register
(SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when
RW2 is used.
Figure B.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3)
MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores
it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 0 F
DTB 7 8
● Register indirect addressing with post increment (@RWj+ j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. After operand
operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word).
Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system
stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank
register (ADB) when RW2 is used.
If the post increment results in the address of the register that specifies the increment, the incremented
value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to
writing by an instruction and, therefore, the register that would be incremented becomes write data.
491
APPENDIX
Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3)
MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post
increment and stores it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 1 1
DTB 7 8
● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
Memory is accessed using the address obtained by adding an offset to the contents of general-purpose
register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric
values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or
RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is
used, or additional data bank register (ADB) when RW2 or RW6 is used.
Figure B.4-3 Example of Register Indirect Addressing with Offset
(@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+10H)
RW1 D 3 0 F
After execution
A 2534 FFEE
RW1 D 3 0 F
492
DTB 7 8
DTB 7 8
Memory space
78D31FH
EE
78D320H
FF
APPENDIX B Instructions
● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the
contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value.
Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3)
MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+25H)
RL2 F 3 8 2
After execution
4B02
Memory space
824B27H
EE
824B28H
FF
A 2534 FFEE
RL2 F 3 8 2
4B02
● Program counter indirect addressing with offset (@PC + disp16)
Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one
word long. Address bits 16 to 23 are specified by the program counter bank register (PCB). Note that the
operand address of each of the following instructions is not deemed to be (next instruction address +
disp16):
•
DBNZ eam, rel
•
DWBNZ eam, rel
•
CBNE eam, #imm8, rel
•
CWBNE eam, #imm16, rel
•
MOV eam, #imm8
•
MOVW eam, #imm16
Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16)
MOVW A, @PC+20H (This instruction reads data by program counter indirect
addressing with an offset and stores it in A.)
Before execution
A 0716
2534
Memory space
PCB C 5 PC 4 5 5 6
After execution
A 2534
FFEE
PCB C 5 PC 4 5 5 A
+4
C54556H
73
C54557H
9E
C54558H
20
C54559H
00
MOVW
A, @PC+20H
C5455AH
.
.
.
+20H
C5457AH
EE
C5457BH
FF
493
APPENDIX
● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7)
Memory is accessed using the address determined by adding RW0 or RW1 to the contents of generalpurpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB).
Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7)
MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with
a base index and stores it in A.)
Before execution
A 0716
RW1 D 3 0 F
WR7 0 1 0 1
After execution
A 2534
RW1 D 3 0 F
WR7 0 1 0 1
494
2534
+
DTB 7 8
FFEE
DTB 7 8
Memory space
78D410H
EE
78D411H
FF
APPENDIX B Instructions
● Program counter relative branch addressing (rel)
The address of the branch destination is a value determined by adding an 8-bit offset to the program
counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is
not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte
bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to
23 are indicated by the program counter bank register (PCB).
Figure B.4-7 Example of Program Counter Relative Branch Addressing (rel)
BRA 10H (This instruction causes an unconditional relative branch.)
Before execution
After execution
PC 3 C 2 0
PC 3 C 3 2
PCB 4 F
PCB 4 F
Memory space
4F3C32H
Next instruction
4F3C21H
10
4F3C20H
60
BRA 10H
● Register list (rlst)
Specify a register to be pushed onto or popped from a stack.
Figure B.4-8 Configuration of the Register List
MSB
LSB
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
A register is selected when the corresponding bit is 1 and deselected when the bit is 0.
495
APPENDIX
Figure B.4-9 Example of Register List (rlist)
POPW, RW0, RW4 (This instruction transfers memory data indicated by the SP to
multiple word registers indicated by the register list.)
SP
34FA
SP
34FE
RW0
×× ××
RW0
02 01
RW1
×× ××
RW1
×× ××
RW2
×× ××
RW2
×× ××
RW3
×× ××
RW3
×× ××
RW4
×× ××
RW4
04 03
RW5
×× ××
RW5
×× ××
RW6
×× ××
RW6
×× ××
RW7
×× ××
RW7
×× ××
Memory space
SP
Memory space
01
34FAH
01
34FAH
02
34FBH
02
34FBH
03
34FCH
03
34FCH
04
34FDH
04
34FDH
34FEH
SP
Before execution
34FEH
After execution
● Accumulator indirect addressing (@A)
Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the
accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB).
Figure B.4-10 Example of Accumulator Indirect Addressing (@A)
MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.)
Before execution
A
0716
2534
DTB B B
After execution
A
0716
DTB B B
496
FFEE
Memory space
BB2534H
EE
BB2535H
FF
APPENDIX B Instructions
● Accumulator indirect branch addressing (@A)
The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the
accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are
specified by the program counter bank register (PCB). For the Jump Context (JCTX) instruction, however,
address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for
unconditional branch instructions.
Figure B.4-11 Example of Accumulator Indirect Branch Addressing (@A)
JMP @A (This instruction causes an unconditional branch by accumulator indirect
branch addressing.)
Before execution
PC 3 C 2 0
A 6677
After execution
PC 3 B 2 0
A 6677
PCB 4 F
3B20
Memory space
4F3B20H
Next instruction
4F3C20H
61
JMP @A
PCB 4 F
3B20
● Indirect specification branch addressing (@ear)
The address of the branch destination is the word data at the address indicated by ear.
Figure B.4-12 Example of Indirect Specification Branch Addressing (@ear)
JMP @@RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
After execution
PC 3 C 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
PC 3 B 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
Memory space
217F48H
20
217F49H
3B
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
08
JMP @@RW0
497
APPENDIX
● Indirect specification branch addressing (@eam)
The address of the branch destination is the word data at the address indicated by eam.
Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam)
JMP @RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
PC 3 C 2 0
PCB 4 F
RW0 3 B 2 0
After execution
PC 3 B 2 0
RW0 3 B 2 0
498
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
00
JMP @RW0
APPENDIX B Instructions
B.5
Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is
obtained by adding the number of cycles required for each instruction, "correction
value" determined by the condition, and the number of cycles for instruction fetch.
■ Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is obtained by adding the
number of cycles required for each instruction, "correction value" determined by the condition, and the
number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal
ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments.
Therefore, intervening in data access increases the execution cycle count.
Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the
program fetches every byte of an instruction being executed. Therefore, intervening in data access increases
the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register,
internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the
cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register.
Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add
the "access count x cycle count for the halt" as a correction value to the normal execution count.
499
APPENDIX
■ Calculating the Execution Cycle Count
Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value
data.
Table B.5-1 Execution Cycle Counts in Each Addressing Mode
(a) *
Code
Operand
00
|
07
Ri
Rwi
RLi
08
|
0B
Execution cycle count in
each addressing mode
Register access count in
each addressing mode
See the instruction list.
See the instruction list.
@RWj
2
1
0C
|
0F
@RWj+
4
2
10
|
17
@RWi+disp8
2
1
18
|
1B
@RWi+disp16
2
1
1C
1D
1E
1F
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
4
4
2
1
2
2
0
0
*: (a) is used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List".
500
APPENDIX B Instructions
Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles
(b) byte *
Operand
(c) word *
(d) long *
Cycle
count
Access
count
Cycle
count
Access
count
Cycle
count
Access
count
Internal register
+0
1
+0
1
+0
2
Internal memory
Even address
+0
1
+0
1
+0
2
Internal memory
Odd address
+0
1
+2
2
+4
4
External data bus
16-bit even address
+1
1
+1
1
+2
2
External data bus
16-bit odd address
+1
1
+4
2
+8
4
External data bus
8-bits
+1
1
+4
2
+8
4
*: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction
List".
Note:
When an external data bus is used, the cycle counts during which an instruction is made to wait by
ready input or automatic ready must also be added.
Table B.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
-
+2
External data bus 16-bits
-
+3
External data bus 8-bits
+3
-
Notes:
• When an external data bus is used, the cycle counts during which an instruction is made to wait
by ready input or automatic ready must also be added.
• Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the
correction values to calculate the worst case.
501
APPENDIX
B.6
Effective address field
Table B.6-1 shows the effective address field.
■ Effective Address Field
Table B.6-1 Effective Address Field
Code
Representation
00
01
02
03
04
05
06
07
08
09
0A
R0
R1
R2
R3
R4
R5
R6
R7
@RW0
@RW1
@RW2
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
0B
0C
0D
0E
0F
10
11
12
13
14
15
@RW3
@RW0+
@RW1+
@RW2+
@RW3+
@RW0+disp8
@RW1+disp8
@RW2+disp8
@RW3+disp8
@RW4+disp8
@RW5+disp8
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Address format
Byte count of
extended
address part *
Register direct: Individual parts correspond to
the byte, word, and long word types in order
from the left.
-
Register indirect
0
Register indirect with post increment
0
Register indirect with 8-bit displacement
1
16
@RW6+disp8
17
@RW7+disp8
18
@RW0+disp16
19
@RW1+disp16
Register indirect with 16-bit displacement
2
1A
@RW2+disp16
1B
@RW3+disp16
1C
@RW0+RW7
Register indirect with index
0
1D
@RW1+RW7
Register indirect with index
0
1E
@PC+disp16
PC indirect with 16-bit displacement
2
1F
addr16
Direct address
2
*1: Each byte count of the extended address part applies to + in the # (byte count) column in "B.8 F2MC-16LX
Instruction List".
502
APPENDIX B Instructions
B.7
How to Read the Instruction List
Table B.7-1 describes the items used in "B.8 F2MC-16LX Instruction List", and Table
B.7-2 describes the symbols used in the same list.
■ Description of Instruction Presentation Items and Symbols
Table B.7-1 Description of Items in the Instruction List (1/2)
Item
Mnemonic
Description
Uppercase, symbol: Represented as is in the assembler.
Lowercase: Rewritten in the assembler.
Number of following lowercase: Indicates bit length in the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
See Table B.2-1 for the alphabetical letters in items.
RG
B
Operation
Indicates the number of times a register access is performed during instruction
execution.
The number is used to calculate the correction value for CPU intermittent
operation.
Indicates the correction value used to calculate the actual number of cycles during
instruction execution.
The actual number of cycles during instruction execution can be determined by
adding the value in the ~ column to this value.
Indicates the instruction operation.
LH
Indicates the special operation for bit15 to bit08 of the accumulator.
Z: Transfers 0.
X: Transfers after sign extension.
-: No transfer
AH
Indicates the special operation for the 16 high-order bits of the accumulator.
*: Transfers from AL to AH.
-: No transfer
Z: Transfers 00 to AH.
X: Transfers 00H or FFH to AH after AL sign extension.
503
APPENDIX
Table B.7-1 Description of Items in the Instruction List (1/2)
Item
Description
I
Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N
(negative), Z (zero), V (overflow), C (carry).
*: Changes upon instruction execution.
-: No change
S: Set upon instruction execution.
R: Reset upon instruction execution.
S
T
N
Z
V
C
RMW
Indicates whether the instruction is a Read Modify Write instruction (reading data
from memory by the I instruction and writing the result to memory).
*: Read Modify Write instruction
-: Not Read Modify Write instruction
Note:
Cannot be used for an address that has different meanings between read and
write operations.
Table B.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
A
504
Explanation
The bit length used varies depending on the 32-bit accumulator instruction.
Byte: Low-order 8 bits of byte AL
Word: 16 bits of word AL
Long word: 32 bits of AL and AH
AH
16 high-order bits of A
AL
16 low-order bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
program counter bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
APPENDIX B Instructions
Table B.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
Ri
Explanation
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
Direct addressing
addr24
Physical direct addressing
ad24 0-15
Bit0 to bit15 of addr24
ad24 16-23
Bit16 to bit23 of addr24
io
I/O area (000000H to 0000FFH)
#imm4
4-bit immediate data
#imm8
8-bit immediate data
#imm16
16-bit immediate data
#imm32
32-bit immediate data
ext (imm8)
16-bit data obtained by sign extension of 8-bit immediate data
disp8
8-bit displacement
disp16
16-bit displacement
bp
Bit offset
vct4
Vector number (0 to 15)
vct8
Vector number (0 to 255)
( )b
Bit address
rel
PC relative branch
ear
Effective addressing (code 00 to 07)
eam
Effective addressing (code 08 to 1F)
rlst
Register list
505
APPENDIX
B.8
F2MC-16LX Instruction List
Table B.8-1 to Table B.8-18 list the instructions used by the F2MC-16LX.
■ F2MC-16LX Instruction List
Table B.8-1 41 Transfer Instructions (Byte)
Mnemonic
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
XCH
XCH
XCH
XCH
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RLi+disp8
A,#imm4
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
Ri,A
ear,A
eam,A
io,A
@RLi+disp8,A
Ri,ear
Ri,eam
ear,Ri
eam,Ri
Ri,#imm8
io,#imm8
dir,#imm8
ear,#imm8
eam,#imm8
@AL,AH
A,ear
A,eam
Ri,ear
Ri,eam
#
~
RG
B
2
3
1
2
2+
2
2
2
3
1
2
3
2
2
2+
2
2
2
2
3
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
2
2+
2
2+
3
4
2
2
3 + (a)
3
2
3
10
1
3
4
2
2
3 + (a)
3
2
3
5
10
3
4
2
2
3 + (a)
3
10
3
4 + (a)
4
5 + (a)
2
5
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
0
0
1
1
0
0
0
0
2
0
0
0
1
1
0
0
0
0
1
2
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
2
0
4
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
0
2 × (b)
0
2 × (b)
Operation
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi)+disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
Z
Z
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table.
506
APPENDIX B Instructions
Table B.8-2 38 Transfer Instructions (Word, Long Word)
Mnemonic
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW
XCHW
XCHW
MOVL
MOVL
MOVL
MOVL
MOVL
A,dir
A,addr16
A,SP
A,RWi
A,ear
A,eam
A,io
A,@A
A,#imm16
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
SP,A
RWi,A
ear,A
eam,A
io,A
@RWi+disp8,A
@RLi+disp8,A
RWi,ear
RWi,eam
ear,RWi
eam,RWi
RWi,#imm16
io,#imm16
ear,#imm16
eam,#imm16
@AL,AH
A,ear
A,eam
RWi, ear
RWi, eam
A,ear
A,eam
A,#imm32
ear,A
eam,A
#
~
RG
B
2
3
1
1
2
2+
2
2
3
2
3
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
2
2
2+
2
2+
2
2+
5
2
2+
3
4
1
2
2
3 + (a)
3
3
2
5
10
3
4
1
2
2
3 + (a)
3
5
10
3
4 + (a)
4
5 + (a)
2
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
4
5 + (a)
3
4
5 + (a)
0
0
0
1
1
0
0
0
0
1
2
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
0
2
0
4
2
2
0
0
2
0
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
0
(c)
0
(c)
0
(c)
0
(c)
(c)
0
2 × (c)
0
2 × (c)
0
(d)
0
0
(d)
Operation
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi)+disp8)
word (A) ← ((RLi)+disp8)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
word ((RWi)+disp8) ← (A)
word ((RLi)+disp8) ← (A)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
word (ear) ← imm16
word (eam) ← imm16
word ((A)) ← (AH)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
long (ear) ← (A)
long(eam) ← (A)
LH
AH
I
S
T
N
Z
V
C
RMW
-
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a), (c), and (d) in the table.
507
APPENDIX
Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
ADDW
ADDW
ADDW
ADDW
ADDW
ADDW
ADDCW
ADDCW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBCW
SUBCW
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A,ear
A,eam
A,#imm32
A,ear
A,eam
A,#imm32
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
2+
5
2
2+
5
2
3
4+(a)
2
3
5+(a)
3
4+(a)
2
3
4+(a)
2
3
5+(a)
3
4+(a)
6
7+(a)
4
6
7+(a)
4
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
2
0
0
2
0
0
0
0
(c)
0
0
2 × (c)
0
(c)
0
0
(c)
0
0
2 × (c)
0
(c)
0
(d)
0
0
(d)
0
Operation
byte (A) ← (A) + imm8
byte (A) ← (A) + (dir)
byte (A) ← (A) + (ear)
byte (A) ← (A) + (eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear)+ (C)
byte (A) ← (A) + (eam)+ (C)
byte (A) ← (AH) + (AL) + (C)
(decimal)
byte (A) ← (A) - imm8
byte (A) ← (A) - (dir)
byte (A) ← (A) - (ear)
byte (A) ← (A) - (eam)
byte (ear) ← (ear) - (A)
byte (eam) ← (eam) - (A)
byte (A) ← (AH) - (AL) - (C)
byte (A) ← (A) - (ear) - (C)
byte (A) ← (A) - (eam) - (C)
byte (A) ← (AH) - (AL) - (C)
(decimal)
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) - (AL)
word (A) ← (A) - (ear)
word (A) ← (A) - (eam)
word (A) ← (A) - imm16
word (ear) ← (ear) - (A)
word (eam) ← (eam) - (A)
word (A) ← (A) - (ear) - (C)
word (A) ← (A) - (eam) - (C)
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
long (A) ← (A) - (ear)
long (A) ← (A) - (eam)
long (A) ← (A) - imm32
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
508
APPENDIX B Instructions
Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
INC
ear
2
3
2
0
INC
eam
2+
5+(a)
0
2 × (b)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
byte (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
byte (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DEC
ear
2
3
2
0
byte (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
DEC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
INCW
ear
2
3
2
0
word (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
INCW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DECW
ear
2
3
2
0
DECW
eam
2+
5+(a)
0
2 × (c)
INCL
ear
2
7
4
0
INCL
eam
2+
9+(a)
0
2 × (d)
DECL
ear
2
7
4
0
DECL
eam
2+
9+(a)
0
2 × (d)
word (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
word (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
Table B.8-5 11 Compare Instructions (Byte, Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
CMP
Mnemonic
A
1
1
0
0
byte (AH) - (AL)
Operation
-
-
-
-
-
*
*
*
*
-
CMP
A,ear
2
2
1
0
byte (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMP
A,eam
2+
3+(a)
0
(b)
byte (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMP
A,#imm8
2
2
0
0
byte (A) - imm8
-
-
-
-
-
*
*
*
*
-
CMPW
A
1
1
0
0
word (AH) - (AL)
-
-
-
-
-
*
*
*
*
-
CMPW
A,ear
2
2
1
0
word (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPW
A,eam
2+
3+(a)
0
(c)
word (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPW
A,#imm16
3
2
0
0
word (A) - imm16
-
-
-
-
-
*
*
*
*
-
CMPL
A,ear
2
6
2
0
long (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPL
A,eam
2+
7+(a)
0
(d)
long (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPL
A,#imm32
5
3
0
0
long (A) - imm32
-
-
-
-
-
*
*
*
*
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
509
APPENDIX
Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIVU
A
1
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
-
-
-
-
-
-
-
*
*
-
DIVU
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
-
-
-
-
-
-
-
*
*
-
DIVU
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MULU
A
1
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
MULU
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A
1
*11
0
0
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
MULUW
A,ear
2
*12
1
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,eam
2+
*13
0
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
*1: 3: Division by 0 7: Overflow 15: Normal
*2: 4: Division by 0 8: Overflow 16: Normal
*3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal
*4: 4: Division by 0 7: Overflow 22: Normal
*5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal
*6: (b): Division by 0 or overflow 2 × (b): Normal
*7: (c): Division by 0 or overflow 2 × (c): Normal
*8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0.
*9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0.
*10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0.
*11: 3: Word (AH) is 0. 11: Word (AH) is not 0.
*12: 4: Word (ear) is 0. 12: Word (ear) is not 0.
*13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0.
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
510
APPENDIX B Instructions
Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIV
A
2
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
Z
-
-
-
-
-
-
*
*
-
DIV
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
Z
-
-
-
-
-
-
*
*
-
DIV
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
Z
-
-
-
-
-
-
*
*
-
DIVW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MUL
A
2
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,eam
2+
*10
0
(b)
MULW
A
2
*11
0
0
MULW
A,ear
2
*12
1
MULW
A,eam
2+
*13
0
*1:
*2:
*3:
*4:
3: Division by 0, 8 or 18: Overflow, 18: Normal
4: Division by 0, 11 or 22: Overflow, 23: Normal
5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal
When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal
When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal
*5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal
When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal
*6: (b): Division by 0 or overflow, 2 × (b): Normal
*7: (c): Division by 0 or overflow, 2 × (c): Normal
*8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative
*9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative
*10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative
*11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative
*12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative
*13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative
Notes:
• The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a
pre-operation count or a post-operation count depending on the detection timing.
• When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed.
• See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
511
APPENDIX
Table B.8-8 39 Logic 1 Instructions (Byte, Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
AND
A,#imm8
2
2
0
0
byte (A) ← (A) and imm8
-
-
-
-
-
*
*
R
-
AND
A,ear
2
3
1
0
byte (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
AND
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
byte (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
byte (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
AND
ear,A
2
3
2
0
AND
eam,A
2+
5+(a)
0
2 × (b)
OR
A,#imm8
2
2
0
0
byte (A) ← (A) or imm8
-
-
-
-
-
*
*
R
-
-
OR
A,ear
2
3
1
0
byte (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
OR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
OR
ear,A
2
3
2
0
byte (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
OR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XOR
A,#imm8
2
2
0
0
byte (A) ← (A) xor imm8
-
-
-
-
-
*
*
R
-
-
XOR
A,ear
2
3
1
0
byte (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XOR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XOR
ear,A
2
3
2
0
byte (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XOR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOT
A
1
2
0
0
byte (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOT
ear
2
3
2
0
byte (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOT
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
ANDW
A
1
2
0
0
word (A) ← (AH) and (A)
-
-
-
-
-
*
*
R
-
-
ANDW
A,#imm16
3
2
0
0
word (A) ← (A) and imm16
-
-
-
-
-
*
*
R
-
-
ANDW
A,ear
2
3
1
0
word (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
word (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
word (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
0
word (A) ← (AH) or (A)
-
-
-
-
-
*
*
R
-
-
0
word (A) ← (A) or imm16
-
-
-
-
-
*
*
R
-
-
1
0
word (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
4+(a)
0
(c)
word (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
2
3
2
0
word (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XORW
A
1
2
0
0
word (A) ← (AH) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
A,#imm16
3
2
0
0
word (A) ← (A) xor imm16
-
-
-
-
-
*
*
R
-
-
XORW
A,ear
2
3
1
0
word (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
ear,A
2
3
2
0
ANDW
eam,A
2+
5+(a)
0
2 × (c)
ORW
A
1
2
0
ORW
A,#imm16
3
2
0
ORW
A,ear
2
3
ORW
A,eam
2+
ORW
ear,A
ORW
XORW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
XORW
ear,A
2
3
2
0
word (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOTW
A
1
2
0
0
word (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOTW
ear
2
3
2
0
word (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOTW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
512
APPENDIX B Instructions
Table B.8-9 6 Logic 2 Instructions (Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
ANDL
A,ear
2
6
2
0
long (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
ORL
A,ear
2
6
2
0
long (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
ORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
XORL
A,ear
2
6
2
0
long (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (d) in the table.
Table B.8-10 6 Sign Inversion Instructions (Byte, Word)
Mnemonic
NEG
A
#
~
RG
B
1
2
0
0
byte (A) ← 0 - (A)
byte (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
byte (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
word (A) ← 0 - (A)
-
-
-
-
-
*
*
*
*
-
NEG
ear
2
3
2
0
NEG
eam
2+
5+(a)
0
2 × (b)
NEGW
A
1
2
0
0
NEGW
ear
2
3
2
0
NEGW
eam
2+
5+(a)
0
2 × (c)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
X
-
-
-
-
*
*
*
*
-
word (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
word (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
Table B.8-11 1 Normalization Instruction (Long Word)
Mnemonic
NRML
A,R0
#
~
RG
B
2
*1
1
0
Operation
long (A) ← Shift left to the position where '1' is set
for the first time.
byte (R0) ← Shift count at that time
LH
AH
I
S
T
N
Z
V
C
RMW
-
-
-
-
-
-
*
-
-
-
*1: 4 when all accumulators have a value of 0; otherwise, 6+(R0)
513
APPENDIX
Table B.8-12 18 Shift Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
RORC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
ear
2
3
2
0
byte (ear) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
*
ROLC
ear
2
3
2
0
byte (ear) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
*
ASR
A,R0
2
*1
1
0
byte (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSR
A,R0
2
*1
1
0
byte (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSL
A,R0
2
*1
1
0
byte (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRW
A
1
2
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSRW
A/SHRW A
1
2
0
0
word (A) ← Logical right shift (A, 1 bit)
-
-
-
-
*
R
*
-
*
-
LSLW
A/SHLW A
1
2
0
0
word (A) ← Logical left shift (A, 1 bit)
-
-
-
-
-
*
*
-
*
-
ASRW
A,R0
2
*1
1
0
word (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRW
A,R0
2
*1
1
0
word (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLW
A,R0
2
*1
1
0
word (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRL
A,R0
2
*2
1
0
long (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRL
A,R0
2
*2
1
0
long (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLL
A,R0
2
*2
1
0
long (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
*1: 6 when R0 is 0; otherwise, 5 + (R0)
*2: 6 when R0 is 0; otherwise, 6 + (R0)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table.
514
APPENDIX B Instructions
Table B.8-13 31 Branch 1 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
BZ/BEQ
rel
2
*1
0
0
Branch on (Z) = 1
-
-
-
-
-
-
-
-
-
-
BNZ/
BNE
rel
2
*1
0
0
Branch on (Z) = 0
-
-
-
-
-
-
-
-
-
-
BC/BLO
rel
2
*1
0
0
Branch on (C) = 1
-
-
-
-
-
-
-
-
-
-
BNC/
BHS
rel
2
*1
0
0
Branch on (C) = 0
-
-
-
-
-
-
-
-
-
-
BN
rel
2
*1
0
0
Branch on (N) = 1
-
-
-
-
-
-
-
-
-
-
BP
rel
2
*1
0
0
Branch on (N) = 0
-
-
-
-
-
-
-
-
-
-
BV
rel
2
*1
0
0
Branch on (V) = 1
-
-
-
-
-
-
-
-
-
-
BNV
rel
2
*1
0
0
Branch on (V) = 0
-
-
-
-
-
-
-
-
-
-
BT
rel
2
*1
0
0
Branch on (T) = 1
-
-
-
-
-
-
-
-
-
-
BNT
rel
2
*1
0
0
Branch on (T) = 0
-
-
-
-
-
-
-
-
-
-
BLT
rel
2
*1
0
0
Branch on (V) xor (N) = 1
-
-
-
-
-
-
-
-
-
-
BGE
rel
2
*1
0
0
Branch on (V) xor (N) = 0
-
-
-
-
-
-
-
-
-
-
BLE
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BGT
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BLS
rel
2
*1
0
0
Branch on (C) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BHI
rel
2
*1
0
0
Branch on (C) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BRA
rel
2
*1
0
0
Unconditional branch
-
-
-
-
-
-
-
-
-
-
JMP
@A
1
2
0
0
word (PC) ← (A)
-
-
-
-
-
-
-
-
-
-
JMP
addr16
3
3
0
0
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
JMP
@ear
2
3
1
0
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
JMP
@eam
2+
4+(a)
0
(c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
JMPP
@ear *3
2
5
2
0
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
JMPP
@eam *3
2+
6+(a)
0
(d)
JMPP
addr24
4
4
0
0
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
CALL
@ear *4
2
6
1
(c)
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
CALL
@eam *4
2+
7+(a)
0
2 × (c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
CALL
addr16 *5
3
6
0
(c)
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
CALLV
#vct4 *5
1
7
0
2 × (c)
Vector call instruction
-
-
-
-
-
-
-
-
-
-
CALLP
@ear *6
2
10
2
2 × (c)
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
CALLP
@eam *6
2+
11+(a)
0
*2
CALLP
addr24 *7
4
10
0
2 × (c)
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
*1: 4 when a branch is made; otherwise, 3
*2: 3 × (c) + (b)
*3: Read (word) of branch destination address
*4: W: Save to stack (word) R: Read (word) of branch destination address
*5: Save to stack (word)
*6: W: Save to stack (long word), R: Read (long word) of branch destination address
*7: Save to stack (long word)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
515
APPENDIX
Table B.8-14 19 Branch 2 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S T N Z V C
RMW
CBNE
A,#imm8,rel
3
*1
0
0
Branch on byte (A) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
A,#imm16,rel
4
*1
0
0
Branch on word (A) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CBNE
ear,#imm8,rel
4
*2
1
0
Branch on byte (ear) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CBNE
eam,#imm8,rel *9
4+
*3
0
(b)
Branch on byte (eam) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
ear,#imm16,rel
5
*4
1
0
Branch on word (ear) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CWBNE
eam,#imm16,rel*9
5+
*3
0
(c)
Branch on word (eam) not equal to imm16
-
-
-
-
-
*
*
*
*
-
DBNZ
ear,rel
3
*5
2
0
byte (ear) ← (ear) - 1, Branch on (ear) not equal to 0
-
-
-
-
-
*
*
*
-
*
DBNZ
eam,rel
3+
*6
2
DWBNZ
ear,rel
3
*5
2
DWBNZ
eam,rel
3+
*6
2
2 × (b) byte (eam) ← (eam) - 1, Branch on (eam) not equal to 0
-
-
-
-
-
*
*
*
-
-
-
-
-
-
*
*
*
-
-
2 × (c) word (eam) ← (eam) - 1, Branch on (eam) not equal to 0
-
-
-
-
-
*
*
*
-
*
0
word (ear) ← (ear) - 1, Branch on (ear) not equal to 0
INT
#vct8
2
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT
addr16
3
16
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INTP
addr24
4
17
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
1
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT9
RETI
LINK
#imm8
UNLINK
1
*8
0
*7
Return from interrupt
-
-
*
*
*
*
*
*
*
-
2
6
0
(c)
Saves the old frame pointer in the stack upon entering the
function, then sets the new frame pointer and reserves the
local pointer area.
-
-
-
-
-
-
-
-
-
-
1
5
0
(c)
Recovers the old frame pointer from the stack upon exiting
the function.
-
-
-
-
-
-
-
-
-
-
RET
*10
1
4
0
(c)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
RETP
*11
1
6
0
(d)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
*1: 5 when a branch is made; otherwise, 4
*2: 13 when a branch is made; otherwise, 12
*3: 7+(a) when a branch is made; otherwise, 6+(a)
*4: 8 when a branch is made; otherwise, 7
*5: 7 when a branch is made; otherwise, 6
*6: 8+(a) when a branch is made; otherwise, 7+(a)
*7: 3 × (b) + 2 × (c) when jumping to the next interruption request; 6 × (c) when returning from the current interruption
*8: 15 when jumping to the next interruption request; 17 when returning from the current interruption
*9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction.
*10: Return from stack (word)
*11: Return from stack (long word)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
516
APPENDIX B Instructions
Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
PUSHW
A
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (A)
-
-
-
-
-
-
-
-
-
-
PUSHW
AH
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (AH)
-
-
-
-
-
-
-
-
-
-
PUSHW
PS
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (PS)
-
-
-
-
-
-
-
-
-
-
PUSHW
rlst
2
*3
*5
*4
(SP) ← (SP) - 2n, ((SP)) ← (rlst)
-
-
-
-
-
-
-
-
-
-
POPW
A
1
3
0
(c)
word (A) ← ((SP)), (SP) ← (SP) + 2
-
*
-
-
-
-
-
-
-
-
POPW
AH
1
3
0
(c)
word (AH) ← ((SP)), (SP) ← (SP) + 2
-
-
-
-
-
-
-
-
-
-
POPW
PS
1
4
0
(c)
word (PS) ← ((SP)), (SP) ← (SP) + 2
-
-
*
*
*
*
*
*
*
-
POPW
rlst
2
*2
*5
*4
(rlst) ← ((SP)), (SP) ← (SP) + 2n
-
-
-
-
-
-
-
-
-
-
JCTX
@A
1
14
0
6 × (c)
Context switch instruction
-
-
*
*
*
*
*
*
*
-
AND
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) and imm8
-
-
*
*
*
*
*
*
*
-
OR
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) or imm8
-
-
*
*
*
*
*
*
*
-
MOV
RP,#imm8
2
2
0
0
byte (RP) ← imm8
-
-
-
-
-
-
-
-
-
-
MOV
ILM,#imm8
2
2
0
0
byte (ILM) ← imm8
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,ear
2
3
1
0
word (RWi) ← ear
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,eam
2+
2+(a)
1
0
word (RWi) ← eam
-
-
-
-
-
-
-
-
-
-
MOVEA
A,ear
2
1
0
0
word (A) ← ear
-
*
-
-
-
-
-
-
-
-
MOVEA
A,eam
2+
1+(a)
0
0
word (A) ← eam
-
*
-
-
-
-
-
-
-
-
ADDSP
#imm8
2
3
0
0
word (SP) ← (SP) + ext(imm8)
-
-
-
-
-
-
-
-
-
-
ADDSP
#imm16
3
3
0
0
word (SP) ← (SP) + imm16
-
-
-
-
-
-
-
-
-
-
MOV
A,brg1
2
*1
0
0
byte (A) ← (brg1)
Z
*
-
-
-
*
*
-
-
-
MOV
brg2,A
-
2
1
0
0
byte (brg2) ← (A)
-
-
-
-
-
*
*
-
-
NOP
1
1
0
0
No operation
-
-
-
-
-
-
-
-
-
-
ADB
1
1
0
0
Prefix code for AD space access
-
-
-
-
-
-
-
-
-
-
DTB
1
1
0
0
Prefix code for DT space access
-
-
-
-
-
-
-
-
-
-
PCB
1
1
0
0
Prefix code for PC space access
-
-
-
-
-
-
-
-
-
-
SPB
1
1
0
0
Prefix code for SP space access
-
-
-
-
-
-
-
-
-
-
NCC
1
1
0
0
Prefix code for flag no-change
-
-
-
-
-
-
-
-
-
-
CMR
1
1
0
0
Prefix code for common register bank
-
-
-
-
-
-
-
-
-
-
*1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2
*2: 7 + 3 × (POP count) + 2 × (POP last register number), 7 when RLST = 0 (no transfer register)
*3: 29 + 3 × (PUSH count) - 3 × (PUSH last register number), 8 when RLST = 0 (no transfer register)
*4: (POP count) × (c) or (PUSH count) × (c)
*5: (POP count) or (PUSH count)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (c) in the table.
517
APPENDIX
Table B.8-16 21 Bit Operand Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
MOVB
A,dir:bp
3
5
0
(b)
byte (A) ← (dir:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,addr16:bp
4
5
0
(b)
byte (A) ← (addr16:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,io:bp
3
4
0
(b)
byte (A) ← (io:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
dir:bp,A
3
7
0
2 × (b)
bit (dir:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
addr16:bp,A
4
7
0
2 × (b)
bit (addr16:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
io:bp,A
3
6
0
2 × (b)
bit (io:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
SETB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
*
CLRB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 0
-
-
-
-
-
-
-
-
-
CLRB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
CLRB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
BBC
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
io:bp,rel
4
*2
0
(b)
Branch on (io:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBS
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
io:bp,rel
4
*2
0
(b)
SBBS
addr16:bp,rel
5
*3
0
2 × (b)
Branch on (io:bp) b = 1
-
-
-
-
-
-
*
-
-
-
Branch on (addr16:bp) b = 1,
bit (addr16:bp) b ← 1
-
-
-
-
-
-
*
-
-
*
WBTS
io:bp
3
*4
0
WBTC
io:bp
3
*4
0
*5
Waits until (io:bp) b = 1
-
-
-
-
-
-
-
-
-
-
*5
Waits until (io:bp) b = 0
-
-
-
-
-
-
-
-
-
-
RMW
*1: 8 when a branch is made; otherwise, 7
*2: 7 when a branch is made; otherwise, 6
*3: 10 when the condition is met; otherwise, 9
*4: Undefined count
*5: Until the condition is met
Note:
See Table B.5-1 and Table B.5-2 for information on (b) in the table.
Table B.8-17 6 Accumulator Operation Instructions (Byte, Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
SWAP
Mnemonic
1
3
0
0
byte (A)0-7 ↔ (A)8-15
-
-
-
-
-
-
-
-
-
-
SWAPW
1
2
0
0
word (AH) ↔ (AL)
-
*
-
-
-
-
-
-
-
-
EXT
1
1
0
0
Byte sign extension
X
-
-
-
-
*
*
-
-
-
EXTW
1
2
0
0
Word sign extension
-
X
-
-
-
*
*
-
-
-
ZEXT
1
1
0
0
Byte zero extension
Z
-
-
-
-
R
*
-
-
-
ZEXTW
1
1
0
0
Word zero extension
-
Z
-
-
-
R
*
-
-
-
518
Operation
APPENDIX B Instructions
Table B.8-18 10 String Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
MOVS / MOVSI
2
*2
*5
*3
byte transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
MOVSD
2
*2
*5
*3
byte transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCEQ / SCEQI
2
*1
*8
*4
byte search @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCEQD
2
*1
*8
*4
byte search @AH- ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
FILS / FILSI
2
6m+6
*8
*3
byte fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
MOVSW / MOVSWI
2
*2
*5
*6
word transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
-
MOVSWD
2
*2
*5
*6
word transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCWEQ / SCWEQI
2
*1
*8
*7
word search @AH+ - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCWEQD
2
*1
*8
*7
word search @AH- - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
FILSW / FILSWI
2
6m+6
*8
*6
word fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
*1: 5 when RW0 is 0, 4 + 7 × (RW0) when the counter expires, or 7n + 5 when a match occurs
*2: 5 when RW0 is 0; otherwise, 4 + 8 × (RW0)
*3: (b) × (RW0) + (b) × (RW0) When the source and destination access different areas, calculate the (b) item individually.
*4: (b) × n
*5: 2 × (b) × (RW0)
*6: (c) × (RW0) + (c) × (RW0) When the source and destination access different areas, calculate the (c) item individually.
*7: (c) × n
*8: (b) × (RW0)
Note:
m: RW0 value (counter value), n: Loop count
See Table B.5-1 and Table B.5-2 for information on (b) and (c) in the table.
519
APPENDIX
B.9
Instruction Map
Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction
map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F2MC-16LX
instruction map.
■ Structure of Instruction Map
Figure B.9-1 Structure of Instruction Map
Basic page map
Bit operation
instructions
Character string
operation
instructions
2-byte
instructions
: Byte 1
ea instructions × 9 : Byte 2
An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An
instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it
references byte 1, and can check the following one byte by referencing the map for byte 2. Figure B.9-2
shows the correspondence between an actual instruction code and instruction map.
520
APPENDIX B Instructions
Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map
Some instructions do
not contain byte 2.
Instruction
code
Length varies
depending on the
instruction.
Byte 1
Byte 2
Operand
Operand
...
[Basic page map]
XY
+Z
[Extended page map]*
UV
+W
*: The extended page map is a generic name of maps for bit operation instructions, character
string operation instructions, 2-byte instructions, and ea instructions. Actually, there are
multiple extended page maps for each type of instructions.
An example of an instruction code is shown in Table B.9-1 .
Table B.9-1 Example of an Instruction Code
Byte 1
(from basic page map)
Byte 2
(from extended page map)
NOP
00 +0=00
-
AND A, #8
30 +4=34
-
MOV A, ADB
60 +F=6F
00 +0=00
@RW2+d8, #8, rel
70 +0=70
F0 +2=F2
Instruction
521
522
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
A
ZEXT
SWAP
ADDSP
DTB
ADB
SPB
#8
A, #8
dir, A
A, dir
io, A
A, io
JMP
BRA
60
MULU
DIVU
ea
@A instruction 2
A
MOVW
MOVX
RET
SP, A A, addr16
A0
B0
C0
ea
instruction 8
D0
E0
rel
rel
LSRW
ASRW
LSLW
SWAPW
ZEXTW
XORW
ORW
ANDW
ORW
PUSHW
POPW
A, #16
AH
AH
MOVW
ea, RWi
Bit operation MOV
A instruction
ea, Ri
MOVW
RWi, ea
PUSHW
POPW
2-byte
XCHW
A
rlst
rlst instruction
RWi, ea
Character
XORW
PUSHW
POPW
XCH
operation
A
A, #16
PS
PS string
Ri, ea
instruction
A
ANDW
PUSHW
POPW
A
A, #16
A
CMPW
MOVL
MOVW
RETI
A, #16
A, #32 addr16, A
ADDSP
MULUW
NOTW
A
#16
A
A
A
EXTW
A
BHI
BLS
BGT
BLE
rel
rel
rel
rel
rel
BGE
CMPL
CMPW
A, #32
NEGW
A
rel
rel
rel
rel
rel
rel
BLT
BT
BNV
BV
BP
BN
BNC/BHS
rel
BC/BLO
BNZ/BNE
rel
BZ/BEQ
MOV
MOV
CBNE A, CWBNE A, MOVW
MOVW
INTP
MOV
RP, #8
ILM, #8
#8, rel
#16, rel
A, #16 A,addr16
addr24
Ri, ea
#4
F0
rel
ADDW
MOVW
MOVW
INT
ea
MOVW
MOVW
MOVW
MOV A,
MOVW
A, #16
A, dir
A, io
#vct8 instruction 9
A, RWi
RWi, A RWi, #16 @RWi+d8 @RWi+d8, A
NOT
ea
instruction 7
MOVX
MOVX
CALLP
ea
A, dir
A, io
addr24 instruction 6
MOVW
MOVW
RETP
A, #8
A, SP
io, #16
A, #8
90
BNT
SUBL
SUBW
A, #32
A
A
A
XOR
OR
OR
CCR, #8
80
ea
MOV
MOV
MOV
MOV
MOVX A, MOV
CALL
rel instruction 1
A, Ri
Ri, A
Ri, #8
A, Ri @RWi+d8
A, #4
70
MOV
JMP
ea
A, addr16
addr16 instruction 3
MOV
MOV
50
MOVX
MOV
JMPP
ea
A, #8
A, #8 addr16, A
addr24 instruction 4
MOV
MOV
MOV
40
SUBW
MOVW
MOVW
INT
MOVEA
A
A, #16
dir, A
io, A
addr16
RWi, ea
UNLINK
A
CMP
A
A, #8
A, #8
SUBC
SUB
ADD
30
AND
AND
MOV
MOV
CALL
ea
CCR, #8
A, #8
dir, #8
io, #8
addr16 instruction 5
CMP
A
A, dir
A, dir
ADDC
SUB
ADD
20
LINK
ADDL
ADDW
#imm8
A, #32
EXT
@A
PCB
A
JCTX
SUBDC
ADDDC
NEG
NCC
INT9
A
CMR
10
NOP
00
APPENDIX
Table B.9-2 Basic Page Map
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
10
MOVB
io:bp, A
20
30
CLRB
io:bp
40
50
SETB
io:bp
60
70
BBC
io;bp, rel
80
90
BBS
io:bp, rel
A0
B0
MOVB
MOVB A, MOVB
MOVB
CLRB
CLRB
SETB
SETB
BBC
BBC
BBS
BBS
A, dir:bp addr16:bp
dir:bp, A addr16:bp,A
dir:bp addr16:bp
dir:bp addr16:bp dir:bp, rel addr16:bp,rel dir:bp, rel addr16:bp,rel
MOVB
A, io:bp
00
WBTS
io:bp
C0
D0
WBTC
io:bp
E0
SBBS
addr16:bp
F0
APPENDIX B Instructions
Table B.9-3 Bit Operation Instruction Map (First Byte = 6CH)
523
524
MOVSI
MOVSD
PCB, PCB
PCB, DTB
PCB, ADB
PCB, SPB
DTB, PCB
DTB, DTB
DTB, ADB
DTB, SPB
ADB, PCB
ADB, DTB
ADB, ADB
ADB, SPB
SPB, PCB
SPB, DTB
SPB, ADB
SPB, SPB
+1
+2
+3
+4
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
10
+0
00
MOVSWI
20
MOVSWD
30
40
50
60
70
90
A0
B0
C0
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SCEQI
SCEQD
SCWEQI SCWEQD FILSI
PCB
PCB
PCB
PCB
PCB
80
D0
FILSI
SPB
ADB
DTB
PCB
E0
F0
APPENDIX
Table B.9-4 Character String Operation Instruction Map (First Byte = 6EH)
LSLW
LSLL
LSL
MOVW
MOVW
A, R0
A, R0
A, R0 @RL2+d8, A A, @RL2+d8
MOVW
MOVW
NRML
A, @A @AL, AH
A, R0
ASRW
ASRL
ASR
MOVW
MOVW
A, R0
A, R0
A, R0 @RL3+d8, A A, @RL3+d8
LSRW
LSRL
LSR
A, R0
A, R0
A, R0
+D
+E
+F
MOVW
MOVW
@RL1+d8, A A, @RL1+d8
MOVW
MOVW
@RL0+d8, A A, @RL0+d8
+C
+B
+A
+9
+8
A
MOV
MOV
MOVX
MOV
MOV
A, PCB
A, @A A, @RL3+d8 @RL3+d8, A A, @RL3+d8
+6
ROLC
MOV
MOV
A, @A @AL, AH
+5
A
MOV
MOV
MOVX
MOV
MOV
A, DPR
DPR, A A, @RL2+d8 @RL2+d8, A A, @RL2+d8
+4
ROLC
MOV
MOV
A, USB
USB, A
+3
+7
MOV
MOV
MOVX
MOV
MOV
A, SSB
SSB, A A, @RL1+d8 @RL1+d8, A A, @RL1+d8
+2
40
MOV
MOV
A, ADB
ADB, A
30
+1
20
MOV
MOV
MOVX
MOV
MOV
A, DTB
DTB, A A, @RL0+d8 @RL0+d8, A A, @RL0+d8
10
+0
00
50
DIVU
MULW
MUL
60
A
A
A
70
80
90
A0
B0
C0
D0
E0
F0
APPENDIX B Instructions
Table B.9-5 2-byte Instruction Map (First Byte = 6FH)
525
526
50
90
B0
D0
@RW1, @RW1+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
@RW2, @RW2+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
@RW3, @RW3+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
SUBL
SUBL A,
A, RL2 @RW5+d8
SUBL
SUBL A,
A, RL3 @RW6+d8
SUBL
SUBL A,
A, RL3 @RW7+d8
ADDL
ADDL A,
A, RL2 @RW5+d8
ADDL
ADDL A,
A, RL3 @RW6+d8
ADDL
ADDL A,
A, RL3 @RW7+d8
ADDL
ADDL A, SUBL
SUBL A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ADDL
ADDL A, SUBL
SUBL A, Use
@RW0+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW0+RW7
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
#16, rel A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
,#8, rel
ADDL
ADDL A, SUBL
SUBL A, Use
@RW1+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW1+RW7
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
#16, rel A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
,#8, rel
ADDL
ADDL A,
A,@RW2+ @PC+d16
ADDL
ADDL A, SUBL
SUBL A, Use
A,@RW3+
addr16 A,@RW3+
addr16 prohibited
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
SUBL
SUBL A,
A,@RW2+ @PC+d16
@RW0, @RW0+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
SUBL
SUBL A,
A, RL2 @RW4+d8
Use
prohibited
ANDL
ANDL A,
A,@RW2+ @PC+d16
ANDL
ANDL A,
A, RL3 @RW7+d8
ANDL
ANDL A,
A, RL3 @RW6+d8
ANDL
ANDL A,
A, RL2 @RW5+d8
ANDL
ANDL A,
A, RL2 @RW4+d8
ORL
ORL A,
A,@RW2+ @PC+d16
ORL
ORL A,
A, RL3 @RW7+d8
ORL
ORL A,
A, RL3 @RW6+d8
ORL
ORL A,
A, RL2 @RW5+d8
ORL
ORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A,@RW2+ @PC+d16
XORL
XORL A,
A, RL3 @RW7+d8
XORL
XORL A,
A, RL3 @RW6+d8
XORL
XORL A,
A, RL2 @RW5+d8
XORL
XORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A, RL1 @RW3+d8
addr16,
,#8, rel
Use
@PC+d16,
prohibited
,#8, rel
@RW3, @RW3+d16
#8, rel
,#8, rel
@RW2, @RW2+d16
#8, rel
,#8, rel
@RW1, @RW1+d16
#8, rel
,#8, rel
@RW0, @RW0+d16
#8, rel
,#8, rel
R7, @RW7+d8,
#8, rel
#8, rel
R6, @RW6+d8,
#8, rel
#8, rel
R5, @RW5+d8,
#8, rel
#8, rel
R4, @RW4+d8,
#8, rel
#8, rel
R3, @RW3+d8,
#8, rel
#8, rel
addr16, CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
#16, rel A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 prohibited
@PC+d16, CMPL
CMPL A,
#16, rel A,@RW2+ @PC+d16
RW7, @RW7+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW7+d8
RW6, @RW6+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW6+d8
RW5, @RW5+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW5+d8
RW4, @RW4+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW4+d8
ORL
ORL A,
A, RL1 @RW3+d8
R2, @RW2+d8,
#8, rel
#8, rel
R1, @RW1+d8,
#8, rel
#8, rel
ADDL
ADDL A,
A, RL2 @RW4+d8
ANDL
ANDL A,
A, RL1 @RW3+d8
XORL
XORL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW1+d8
+4
RW3, @RW3+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW3+d8
ORL
ORL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW1+d8
SUBL
SUBL A,
A, RL1 @RW3+d8
ANDL
ANDL A,
A, RL1 @RW2+d8
ANDL
ANDL A,
A, RL0 @RW1+d8
ADDL
ADDL A,
A, RL1 @RW3+d8
RW2, @RW2+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW2+d8
RW1, @RW1+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW1+d8
+3
CBNE ↓
F0
R0, @RW0+d8,
#8, rel
#8, rel
CBNE ↓
E0
SUBL
SUBL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW0+d8
C0
ADDL
ADDL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW0+d8
A0
+2
ANDL
ANDL A,
A, RL0 @RW0+d8
80
SUBL
SUBL A,
A, RL0 @RW1+d8
70
ADDL
ADDL A,
A, RL0 @RW1+d8
60
RW0, @RW0+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW0+d8
CWBNE ↓ CWBNE ↓
40
+1
30
+0
20
SUBL
SUBL A,
A, RL0 @RW0+d8
10
ADDL
ADDL A,
A, RL0 @RW0+d8
00
APPENDIX
Table B.9-6 ea Instruction 1 (First Byte = 70H)
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW7+d8
@RL3 @@RW7+d8
RL3 @RW7+d8
RL3 @RW7+d8
A, RL3 @RW7+d8
RL3, A @RW7+d8,A
R7, #8 @RW7+d8,#8
A, RW7 @RW7+d8
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #8 @RW0+d16,#8
A,@RW0 @RW0+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1,A @RW1+d16,A @RW1, #8 @RW1+d16,#8
A,@RW1 @RW1+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2,A @RW2+d16,A @RW2, #8 @RW2+d16,#8
A,@RW2 @RW2+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3,A @RW3+d16,A @RW3, #8 @RW3+d16,#8
A,@RW3 @RW3+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+,A @RW0+RW7,A @RW0+, #8 @RW0+RW7,#8 A,@RW0+ @RW0+RW7
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+,A @RW1+RW7,A @RW1+, #8 @RW1+RW7,#8 A,@RW1+ @RW1+RW7
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+,A @PC+d16, A @RW2+, #8 @PC+d16, #8 A,@RW2+ @PC+d16
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+,A
addr16, A @RW3+, #8
addr16, #8 A,@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW6+d8
@RL3 @@RW6+d8
RL3 @RW6+d8
RL3 @RW6+d8
A, RL3 @RW6+d8
RL3, A @RW6+d8,A
R6, #8 @RW6+d8,#8
A, RW6 @RW6+d8
D0
+6
C0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW5+d8
@RL2 @@RW5+d8
RL2 @RW5+d8
RL2 @RW5+d8
A, RL2 @RW5+d8
RL2, A @RW5+d8,A
R5, #8 @RW5+d8,#8
A, RW5 @RW5+d8
B0
+5
A0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW4+d8
@RL2 @@RW4+d8
RL2 @RW4+d8
RL2 @RW4+d8
A, RL2 @RW4+d8
RL2, A @RW4+d8,A
R4, #8 @RW4+d8,#8
A, RW4 @RW4+d8
90
+4
80
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW3+d8
@RL1 @@RW3+d8
RL1 @RW3+d8
RL1 @RW3+d8
A, RL1 @RW3+d8
RL1, A @RW3+d8,A
R3, #8 @RW3+d8,#8
A, RW3 @RW3+d8
70
+3
60
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW2+d8
@RL1 @@RW2+d8
RL1 @RW2+d8
RL1 @RW2+d8
A, RL1 @RW2+d8
RL1, A @RW2+d8,A
R2, #8 @RW2+d8,#8
A, RW2 @RW2+d8
50
+2
40
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW1+d8
@RL0 @@RW1+d8
RL0 @RW1+d8
RL0 @RW1+d8
A, RL0 @RW1+d8
RL0, A @RW1+d8,A
R1, #8 @RW1+d8,#8
A, RW1 @RW1+d8
30
+1
20
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW0+d8
@RL0 @@RW0+d8
RL0 @RW0+d8
RL0 @RW0+d8
A, RL0 @RW0+d8
RL0, A @RW0+d8,A
R0, #8 @RW0+d8,#8
A, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-7 ea Instruction 2 (First Byte = 71H)
527
528
D0
E0
F0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A A,@RW3+
addr16 A,@RW3+
addr16
+D
+E
+F
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R7 @RW7+d8
A, R7 @RW7+d8
R7, A @RW7+d8,A
A, R7 @RW7+d8
A, R7 @RW7+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R6 @RW6+d8
A, R6 @RW6+d8
R6, A @RW6+d8,A
A, R6 @RW6+d8
A, R6 @RW6+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R5 @RW5+d8
A, R5 @RW5+d8
R5, A @RW5+d8,A
A, R5 @RW5+d8
A, R5 @RW5+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R4 @RW4+d8
A, R4 @RW4+d8
R4, A @RW4+d8,A
A, R4 @RW4+d8
A, R4 @RW4+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R3 @RW3+d8
A, R3 @RW3+d8
R3, A @RW3+d8,A
A, R3 @RW3+d8
A, R3 @RW3+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R2 @RW2+d8
A, R2 @RW2+d8
R2, A @RW2+d8,A
A, R2 @RW2+d8
A, R2 @RW2+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R1 @RW1+d8
A, R1 @RW1+d8
R1, A @RW1+d8,A
A, R1 @RW1+d8
A, R1 @RW1+d8
+C
INC
DEC
R7 @RW7+d8
C0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ROLC
RORC
RORC
INC
R7 @RW7+d8
R7 @RW7+d8
ROLC
INC
DEC
R6 @RW6+d8
B0
+B
ROLC
RORC
RORC
INC
R6 @RW6+d8
R6 @RW6+d8
ROLC
INC
DEC
R5 @RW5+d8
A0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ROLC
RORC
RORC
INC
R5 @RW5+d8
R5 @RW5+d8
ROLC
INC
DEC
R4 @RW4+d8
90
+A
ROLC
RORC
RORC
INC
R4 @RW4+d8
R4 @RW4+d8
ROLC
INC
DEC
R3 @RW3+d8
INC
DEC
R2 @RW2+d8
INC
DEC
R1 @RW1+d8
80
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R0 @RW0+d8
A, R0 @RW0+d8
R0, A @RW0+d8,A
A, R0 @RW0+d8
A, R0 @RW0+d8
70
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ROLC
RORC
RORC
INC
R3 @RW3+d8
R3 @RW3+d8
ROLC
60
INC
DEC
R0 @RW0+d8
50
+9
ROLC
RORC
RORC
INC
R2 @RW2+d8
R2 @RW2+d8
ROLC
40
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0, A @RW0+d16,A
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ROLC
RORC
RORC
INC
R1 @RW1+d8
R1 @RW1+d8
ROLC
30
ROLC
RORC
RORC
INC
R0 @RW0+d8
R0 @RW0+d8
20
ROLC
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX
Table B.9-8 ea Instruction 3 (First Byte = 72H)
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16 @RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, #16 @RW3+d16,#16 A,@RW3 @RW3+d16
+B
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A @RW3+, #16
addr16, #16 A,@RW3+
addr16
INCW @
+F
INCW
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16 @RW2+ @@PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A @RW2+, #16 @PC+d16, #16 A,@RW2+ @PC+d16
CALL @
+E
CALL
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, #16 @RW1+RW7,#16 A,@RW1+ @RW1+RW7
XCHW
XCHW A,
A, RW7 @RW7+d8
XCHW
XCHW A,
A, RW6 @RW6+d8
XCHW
XCHW A,
A, RW5 @RW5+d8
+D @@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7
INCW @
MOVW
MOVW
RW7, #16 @RW7+d8,#16
MOVW
MOVW
RW6, #16 @RW6+d8,#16
MOVW
MOVW
RW5, #16 @RW5+d8,#16
XCHW
XCHW A,
A, RW4 @RW4+d8
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, #16 @RW0+RW7,#16 A,@RW0+ @RW0+RW7
INCW
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW7 @RW7+d8
RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, A @RW7+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW6 @RW6+d8
RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, A @RW6+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW5 @RW5+d8
RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, A @RW5+d8,A
MOVW
MOVW
RW4, #16 @RW4+d8,#16
+C @@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7
JMP @
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16 @RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, #16 @RW2+d16,#16 A,@RW2 @RW2+d16
+A
JMP
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16 @RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, #16 @RW1+d16,#16 A,@RW1 @RW1+d16
+9
CALL @
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16 @RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #16 @RW0+d16,#16 A,@RW0 @RW0+d16
+8
CALL
CALL
CALL
RW7 @@RW7+d8
JMP
JMP
@RW7 @@RW7+d8
+7
JMP @
CALL
CALL
RW6 @@RW6+d8
JMP
JMP
@RW6 @@RW6+d8
+6
JMP
CALL
CALL
RW5 @@RW5+d8
JMP
JMP
@RW5 @@RW5+d8
+5
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW4 @RW4+d8
RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, A @RW4+d8,A
XCHW
XCHW A,
A, RW3 @RW3+d8
XCHW
XCHW A,
A, RW2 @RW2+d8
XCHW
XCHW A,
A, RW1 @RW1+d8
CALL
CALL
RW4 @@RW4+d8
MOVW
MOVW
RW3, #16 @RW3+d8,#16
MOVW
MOVW
RW2, #16 @RW2+d8,#16
MOVW
MOVW
RW1, #16 @RW1+d8,#16
JMP
JMP
@RW4 @@RW4+d8
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW3 @RW3+d8
RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, A @RW3+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW2 @RW2+d8
RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, A @RW2+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW1 @RW1+d8
RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, A @RW1+d8,A
+4
F0
XCHW
XCHW A,
A, RW0 @RW0+d8
E0
CALL
CALL
RW3 @@RW3+d8
D0
MOVW
MOVW
RW0, #16 @RW0+d8,#16
C0
JMP
JMP
@RW3 @@RW3+d8
B0
+3
A0
CALL
CALL
RW2 @@RW2+d8
90
JMP
JMP
@RW2 @@RW2+d8
80
+2
70
CALL
CALL
RW1 @@RW1+d8
60
JMP
JMP
@RW1 @@RW1+d8
50
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW0 @RW0+d8
RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, A @RW0+d8,A
40
+1
30
CALL
CALL
RW0 @@RW0+d8
20
JMP
JMP
@RW0 @@RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-9 ea Instruction 4 (First Byte = 73H)
529
530
ADD
A, SUB
SUB
SUB
ADDC
A, ADDC
A,
ADDC
ADDC A,
A, CMP
CMP
CMP
CMP
A,
A,
A, AND
AND
AND
AND
AND
AND
A,
A,
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r PC+d16, r
+F A,@RW3+
ADD
ADD
SUB
SUB
ADDC
ADDC
CMP
CMP
AND
AND
OR
OR
XOR
XOR
DBNZ
DBNZ
A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+
A, addr16 A,@RW3+ A, addr16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ADD
SUB
CMP
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW1+ @RW1+RW7 @RW1+, r W1+RW7, r
A,
CMP
OR
OR
A,
A,@RW1+ @RW1+RW7
ADD
ADD
ADDC A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ADDC
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW0+ @RW0+RW7 @RW0+, r W0+RW7, r
A,
OR
OR
A,
A,@RW0+ @RW0+RW7
SUB
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
SUB
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW3 @RW3+d16 @RW3, r W3+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
A,
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW2 @RW2+d16 @RW2, r W2+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW1 @RW1+d16 @RW1, r W1+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW0 @RW0+d16 @RW0, r W0+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
R7, r RW7+d8, r
ADD
F0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
R6, r RW6+d8, r
E0
ADD
D0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
R5, r RW5+d8, r
C0
ADD
B0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
R4, r RW4+d8, r
A0
ADD
90
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
R3, r RW3+d8, r
80
ADD
70
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
R2, r RW2+d8, r
60
ADD
50
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
R1, r RW1+d8, r
40
ADD
30
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
R0, r RW0+d8, r
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX
Table B.9-10 ea Instruction 5 (First Byte = 74H)
NOT
NOT
R2 @RW2+d8
SUB
SUB
SUB
SUB
ADD
SUB
SUB
@RW1+RW7,A @RW1+, A @RW1+RW7,A
ADD @R
@RW0+RW7,A @RW0+, A @RW0+RW7,A
ADD @R
+F
ADD
ADD
@RW3+, A addr16, A
SUB
SUB
@RW3+, A addr16, A
+E @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
ADD
+D @RW1+, A
ADD
+C @RW0+, A
ADD
NOT
NOT
@RW1+ @RW1+RW7
NOT
NOT
@RW0+ @RW0+RW7
SUBC
SUBC A, NEG
NEG A,
AND
AND
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
OR
OR
@RW3+, A addr16, A
XOR
XOR
@RW3+, A addr16, A
NOT
NOT
@RW3+
addr16
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
NOT
NOT
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+ @PC+d16
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A
NOT
NOT
@RW3 @RW3+d16
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
+B
XOR
NOT
NOT
R7, A @RW7+d8, A
R7 @RW7+d8
XOR
NOT
NOT
R6, A @RW6+d8, A
R6 @RW6+d8
XOR
NOT
NOT
R5, A @RW5+d8, A
R5 @RW5+d8
XOR
NOT
NOT
R4, A @RW4+d8, A
R4 @RW4+d8
XOR
NOT
NOT
R3, A @RW3+d8, A
R3 @RW3+d8
XOR
R2, A @RW2+d8,A
XOR
NOT
NOT
R1, A @RW1+d8, A
R1 @RW1+d8
NOT
NOT
@RW2 @RW2+d16
XOR
F0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
NEG A,
AND
AND
OR
OR
R7 @RW7+d8
R7, A @RW7+d8, A
R7, A @RW7+d8, A
XOR
XOR
XOR
XOR
XOR
XOR
E0
XOR
NOT
NOT
R0, A @RW0+d8, A
R0 @RW0+d8
D0
+A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R7, A @RW7+d8, A
R7, A @RW7+d8, A
A, R7 @RW7+d8
ADD
NEG A,
AND
AND
OR
OR
R6 @RW6+d8
R6, A @RW6+d8, A
R6, A @RW6+d8, A
NEG A,
AND
AND
OR
OR
R5 @RW5+d8
R5, A @RW5+d8, A
R5, A @RW5+d8, A
NEG A,
AND
AND
OR
OR
R4 @RW4+d8
R4, A @RW4+d8, A
R4, A @RW4+d8, A
NEG A,
AND
AND
OR
OR
R3 @RW3+d8
R3, A @RW3+d8, A
R3, A @RW3+d8, A
NEG A,
AND
AND
OR
OR
R2 @RW2+d8
R2, A @RW2+d8,A
R2, A @RW2+d8,A
NEG A,
AND
AND
OR
OR
R1 @RW1+d8
R1, A @RW1+d8, A
R1, A @RW1+d8, A
XOR
C0
NOT
NOT
@RW1 @RW1+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R6, A @RW6+d8, A
R6, A @RW6+d8, A
A, R6 @RW6+d8
ADD
B0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R5, A @RW5+d8, A
R5, A @RW5+d8, A
A, R5 @RW5+d8
ADD
A0
+9
ADD
SUB
SUB
SUBC
SUBC A, NEG
R4, A @RW4+d8, A
R4, A @RW4+d8, A
A, R4 @RW4+d8
ADD
90
NOT
NOT
@RW0 @RW0+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R3, A @RW3+d8, A
R3, A @RW3+d8, A
A, R3 @RW3+d8
ADD
80
NEG A,
AND
AND
OR
OR
R0 @RW0+d8
R0, A @RW0+d8, A
R0, A @RW0+d8, A
70
ADD
ADD
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R2, A @RW2+d8,A
R2, A @RW2+d8,A
A, R2 @RW2+d8
60
ADD
50
ADD
SUB
SUB
SUBC
SUBC A, NEG
R1, A @RW1+d8, A
R1, A @RW1+d8, A
A, R1 @RW1+d8
40
ADD
30
ADD
SUB
SUB
SUBC
SUBC A, NEG
R0, A @RW0+d8, A
R0, A @RW0+d8, A
A, R0 @RW0+d8
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX B Instructions
Table B.9-11 ea Instruction 6 (First Byte = 75H)
531
532
ADDW A, SUBW
ADDW
ADDCW
CMPW
ADDCW A, CMPW
ADDCW A,
ANDW
CMPW A, ANDW
CMPW A,
ORW
ORW
ANDW A, ORW
ANDW A,
ANDW A,
ORW
ORW
ORW
A,
A,
A, XORW
XORW A, DWBNZ
DWBNZ
+F A,@RW3+
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
addr 16 A,@RW3+ addr 16
A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr16 A,@RW3+
addr 16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r @PC+d16,r
SUBW A, ADDCW
SUBW A,
ANDW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW1+ @RW1+RW7 @RW1+, r @RW1+RW7,r
SUBW
ADDW A,
ADDW
CMPW A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
CMPW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW0+ @RW0+RW7 @RW0+, r @RW0+RW7,r
ADDCW A,
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ADDCW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW3 @RW3+d16 @RW3, r @RW3+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
SUBW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW2 @RW2+d16 @RW2, r @RW2+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
SUBW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW1 @RW1+d16 @RW1, r @RW1+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADDW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW0 @RW0+d16 @RW0, r @RW0+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
ADDW
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, r @RW7+d8,r
F0
+7
E0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, r @RW6+d8,r
D0
+6
C0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, r @RW5+d8,r
B0
+5
A0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, r @RW4+d8,r
90
+4
80
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, r @RW3+d8,r
70
+3
60
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, r @RW2+d8,r
50
+2
40
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, r @RW1+d8,r
30
+1
20
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, r @RW0+d8,r
10
+0
00
APPENDIX
Table B.9-12 ea Instruction 7 (First Byte = 76H)
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
@RW3 @RW3+d16
SUBW
SUBW
@RW3+, A addr16, A
ADDW
ADDW
@RW3+, A addr16, A
+F
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
ORW
ORW
@RW3+, A addr16, A
XORW
XORW
@RW3+, A addr16, A
NOTW
NOTW
@RW3+
addr16
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
@RW2+ @PC+d16
SUBW
SUBW
@RW2+, A @PC+d16,A
ADDW
ADDW
@RW2+, A @PC+d16,A
+E
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+ @RW1+RW7
SUBCW
+D
SUBW
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+ @RW0+RW7
SUBW
SUBCW
+C
ADDW
ADDW
SUBW
SUBCW A,
+B @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
SUBW
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
@RW2 @RW2+d16
ADDW
ADDW
SUBW
+A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
SUBW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
@RW1 @RW1+d16
ADDW
ADDW
SUBCW A,
+9 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
@RW0 @RW0+d16
SUBW
NOTW
NOTW
RW7 @RW7+d8
NOTW
NOTW
RW6 @RW6+d8
NOTW
NOTW
RW5 @RW5+d8
+8 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
SUBW
XORW
XORW
RW7, A @RW7+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
A, RW7 @RW7+d8
RW7 @RW7+d8
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
+7
ADDW
XORW
XORW
RW6, A @RW6+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
A, RW6 @RW6+d8
RW6 @RW6+d8
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
+6
ADDW
XORW
XORW
RW5, A @RW5+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
A, RW5 @RW5+d8
RW5 @RW5+d8
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
+5
NOTW
NOTW
RW4 @RW4+d8
XORW
XORW
RW4, A @RW4+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
A, RW4 @RW4+d8
RW4 @RW4+d8
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
+4
F0
NOTW
NOTW
RW0 @RW0+d8
E0
NOTW
NOTW
RW3 @RW3+d8
D0
XORW
XORW
RW3, A @RW3+d8, A
C0
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
A, RW3 @RW3+d8
RW3 @RW3+d8
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
B0
+3
A0
NOTW
NOTW
RW2 @RW2+d8
90
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
A, RW2 @RW2+d8
RW2 @RW2+d8
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
80
+2
70
NOTW
NOTW
RW1 @RW1+d8
60
XORW
XORW
RW1, A @RW1+d8, A
50
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
A, RW1 @RW1+d8
RW1 @RW1+d8
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
40
+1
30
XORW
XORW
RW0, A @RW0+d8, A
20
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
A, RW0 @RW0+d8
RW0 @RW0+d8
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
10
+0
00
APPENDIX B Instructions
Table B.9-13 ea Instruction 8 (First Byte = 77H)
533
534
DIV
DIV
A, DIVW
DIVW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
DIV
DIV
A, DIVW
DIVW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW MULUW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MULU
MULU A, MULUW MULUW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MULU
MULU A, MULUW MULUW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
+9
+A
+B
+C
+D
+E
+F A, @RW3+
MULU
DIV
DIV
A, DIVW
DIVW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
addr16 A,@RW3+ addr16
A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
A, DIVW
DIVW A,
addr16 A,@RW3+
addr16
DIV
DIV
A, DIVW
DIVW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
F0
+7
E0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
D0
+6
C0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
B0
+5
A0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
90
+4
80
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
70
+3
60
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
50
+2
40
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
30
+1
20
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
10
+0
00
APPENDIX
Table B.9-14 ea Instruction 9 (First Byte = 78H)
MOVEA
MOVEA RW1
RW1,RW4 ,@RW4+d8
MOVEA
MOVEA RW1
RW1,RW5 ,@RW5+d8
MOVEA
MOVEA RW1
RW1,RW6 ,@RW6+d8
MOVEA
MOVEA RW1
RW1,RW7 ,@RW7+d8
MOVEA
MOVEA RW1
RW1,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,@RW1 ,@RW1+d16
MOVEA
MOVEA RW1
RW1,@RW2 ,@RW2+d16
MOVEA
MOVEA RW1
RW1,@RW3 ,@RW3+d16
MOVEA
MOVEA RW0
RW0,RW4 ,@RW4+d8
MOVEA
MOVEA RW0
RW0,RW5 ,@RW5+d8
MOVEA
MOVEA RW0
RW0,RW6 ,@RW6+d8
MOVEA
MOVEA RW0
RW0,RW7 ,@RW7+d8
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
+4
+5
+6
+7
50
70
90
B0
C0
D0
F0
MOVEA
MOVEA RW3
RW3,@RW2+ ,@PC+d16
MOVEA
MOVEA RW4
RW4,@RW2+ ,@PC+d16
MOVEA
MOVEA RW7
RW7,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
RW6,@RW3+ RW6, addr16 [email protected]+ RW7, addr16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2+ ,@PC+d16
RW6,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
RW0,@RW3+ RW0, addr16 RW1,@RW3+ RW1, addr16 RW2,@RW3+ RW2, addr16 RW3,@RW3+ RW3, addr16 RW4,@RW3+ RW4, addr16 RW5,@RW3+ RW5, addr16
MOVEA
MOVEA RW2
RW2,@RW2+ ,@PC+d16
+F
MOVEA
MOVEA RW1
RW1,@RW2+ ,@PC+d16
MOVEA
MOVEA RW0
RW0,@RW2+ ,@PC+d16
MOVEA RW1
+E
MOVEA
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW5,@RW1+ ,@RW1+RW7 RW6,@RW1+ ,@RW1+RW7 RW7,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW7
RW7,@RW3 ,@RW3+d16
MOVEA
MOVEA RW7
RW7,@RW2 ,@RW2+d16
MOVEA
MOVEA RW7
RW7,@RW1 ,@RW1+d16
MOVEA
MOVEA RW7
RW7,@RW0 ,@RW0+d16
MOVEA
MOVEA RW7
RW7,RW7 ,@RW7+d8
MOVEA
MOVEA RW7
RW7,RW6 ,@RW6+d8
MOVEA
MOVEA RW7
RW7,RW5 ,@RW5+d8
MOVEA
MOVEA RW7
RW7,RW4 ,@RW4+d8
MOVEA
MOVEA RW7
RW7,RW3 ,@RW3+d8
MOVEA
MOVEA RW7
RW7,RW2 ,@RW2+d8
MOVEA
MOVEA RW7
RW7,RW1 ,@RW1+d8
MOVEA
MOVEA RW7
RW7,RW0 ,@RW0+d8
E0
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4
RW2,@RW1+ ,@RW1+RW7 RW3,@RW1+ ,@RW1+RW7 RW4,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW3 ,@RW3+d16 RW6,@RW3 ,@RW3+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2 ,@RW2+d16 RW6,@RW2 ,@RW2+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW1 ,@RW1+d16 RW6,@RW1 ,@RW1+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW0 ,@RW0+d16 RW6,@RW0 ,@RW0+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW7 ,@RW7+d8
RW6,RW7 ,@RW7+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW6 ,@RW6+d8
RW6,RW6 ,@RW6+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW5 ,@RW5+d8
RW6,RW5 ,@RW5+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW4 ,@RW4+d8
RW6,RW4 ,@RW4+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW3 ,@RW3+d8
RW6,RW3 ,@RW3+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW2 ,@RW2+d8
RW6,RW2 ,@RW2+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW1 ,@RW1+d8
RW6,RW1 ,@RW1+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW0 ,@RW0+d8
RW6,RW0 ,@RW0+d8
A0
+D RW0,@RW1+ ,@RW1+RW7 RW1,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW4
RW4,@RW3 ,@RW3+d16
MOVEA
MOVEA RW4
RW4,@RW2 ,@RW2+d16
MOVEA
MOVEA RW4
RW4,@RW1 ,@RW1+d16
MOVEA
MOVEA RW4
RW4,@RW0 ,@RW0+d16
MOVEA
MOVEA RW4
RW4,RW7 ,@RW7+d8
MOVEA
MOVEA RW4
RW4,RW6 ,@RW6+d8
MOVEA
MOVEA RW4
RW4,RW5 ,@RW5+d8
MOVEA
MOVEA RW4
RW4,RW4 ,@RW4+d8
MOVEA
MOVEA RW4
RW4,RW3 ,@RW3+d8
MOVEA
MOVEA RW4
RW4,RW2 ,@RW2+d8
MOVEA
MOVEA RW4
RW4,RW1 ,@RW1+d8
MOVEA
MOVEA RW4
RW4,RW0 ,@RW0+d8
80
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW5,@RW0+ ,@RW0+RW7 RW6,@RW0+ ,@RW0+RW7 RW7,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW3
RW3,@RW3 ,@RW3+d16
MOVEA
MOVEA RW3
RW3,@RW2 ,@RW2+d16
MOVEA
MOVEA RW3
RW3,@RW1 ,@RW1+d16
MOVEA
MOVEA RW3
RW3,@RW0 ,@RW0+d16
MOVEA
MOVEA RW3
RW3,RW7 ,@RW7+d8
MOVEA
MOVEA RW3
RW3,RW6 ,@RW6+d8
MOVEA
MOVEA RW3
RW3,RW5 ,@RW5+d8
MOVEA
MOVEA RW3
RW3,RW4 ,@RW4+d8
MOVEA
MOVEA RW3
RW3,RW3 ,@RW3+d8
MOVEA
MOVEA RW3
RW3,RW2 ,@RW2+d8
MOVEA
MOVEA RW3
RW3,RW1 ,@RW1+d8
MOVEA
MOVEA RW3
RW3,RW0 ,@RW0+d8
60
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4
RW2,@RW0+ ,@RW0+RW7 RW3,@RW0+ ,@RW0+RW7 RW4,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW2
RW2,@RW3 ,@RW3+d16
MOVEA
MOVEA RW2
RW2,@RW2 ,@RW2+d16
MOVEA
MOVEA RW2
RW2,@RW1 ,@RW1+d16
MOVEA
MOVEA RW2
RW2,@RW0 ,@RW0+d16
MOVEA
MOVEA RW2
RW2,RW7 ,@RW7+d8
MOVEA
MOVEA RW2
RW2,RW6 ,@RW6+d8
MOVEA
MOVEA RW2
RW2,RW5 ,@RW5+d8
MOVEA
MOVEA RW2
RW2,RW4 ,@RW4+d8
MOVEA
MOVEA RW2
RW2,RW3 ,@RW3+d8
MOVEA
MOVEA RW2
RW2,RW2 ,@RW2+d8
MOVEA
MOVEA RW2
RW2,RW1 ,@RW1+d8
MOVEA
MOVEA RW2
RW2,RW0 ,@RW0+d8
40
+C RW0,@RW0+ ,@RW0+RW7 RW1,@RW0+ ,@RW0+RW7
+B RW0,@RW3 ,@RW3+d16
+A RW0,@RW2 ,@RW2+d16
+9 RW0,@RW1 ,@RW1+d16
MOVEA RW1
MOVEA
MOVEA RW1
RW1,RW3 ,@RW3+d8
MOVEA
MOVEA RW0
RW0,RW3 ,@RW3+d8
+3
MOVEA
MOVEA
MOVEA RW1
RW1,RW2 ,@RW2+d8
MOVEA
MOVEA RW0
RW0,RW2 ,@RW2+d8
+2
+8 RW0,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,RW1 ,@RW1+d8
MOVEA
MOVEA RW0
RW0,RW1 ,@RW1+d8
+1
30
MOVEA
MOVEA RW1
RW1,RW0 ,@RW0+d8
20
MOVEA
MOVEA RW0
RW0,RW0 ,@RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-15 MOVEA RWi, ea Instruction (First Byte = 79H)
535
536
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW2 @RW2+d16 R1,@RW2 @RW2+d16 R2,@RW2 @RW2+d16 R3,@RW2 @RW2+d16 R4,@RW2 @RW2+d16 R5,@RW2 @RW2+d16 R6,@RW2 @RW2+d16 R7,@RW2 @RW2+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW3+
addr16 @RW3+
addr16
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16
@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX
Table B.9-16 MOV Ri, ea Instruction (First Byte = 7AH)
MOVW
MOVW RW5,
RW5,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW1 @RW1+d16 RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16 RW3,@RW1 @RW1+d16 RW4,@RW1 @RW1+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW2 @RW2+d16 RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16 RW3,@RW2 @RW2+d16 RW4,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW3 @RW3+d16 RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16 RW3,@RW3 @RW3+d16 RW4,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4, MOVW
MOVW RW5, MOVW
MOVW RW6, MOVW
MOVW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, @RW2+ @PC+d16
RW2, @RW2+ @PC+d16
RW3, @RW2+ @PC+d16
RW4, @RW2+ @PC+d16
MOVW
MOVW
RW1, @RW3+ RW1, addr16
MOVW
RW0, @RW1+
MOVW
MOVW
RW0, @RW2+ @PC+d16
MOVW
MOVW
RW0, @RW3+ RW0, addr16
+9
+A
+B
+C
+D
+E
+F
MOVW
MOVW
RW2, @RW3+ RW2, addr16
MOVW
MOVW
RW3, @RW3+ RW3, addr16
MOVW
MOVW
RW5, @RW3+ RW5, addr16
MOVW
MOVW
RW5, @RW2+ @PC+d16
MOVW
MOVW
RW6, @RW3+ RW6, addr16
MOVW
MOVW RW6,
RW6, @RW2+ @PC+d16
MOVW
MOVW
RW7, @RW3+ RW7, addr16
MOVW
MOVW RW7,
RW7, @RW2+ @PC+d16
MOVW RW7,
@RW1+RW7
MOVW
MOVW RW7,
RW7,@RW3 @RW3+d16
MOVW
MOVW RW7,
RW7,@RW2 @RW2+d16
MOVW
MOVW RW7,
RW7,@RW1 @RW1+d16
MOVW
MOVW RW7,
RW7,@RW0 @RW0+d16
MOVW
MOVW RW7,
RW7, RW7 @RW7+d8
MOVW
MOVW RW7,
RW7, RW6 @RW6+d8
MOVW
MOVW RW7,
RW7, RW5 @RW5+d8
MOVW
MOVW RW7,
RW7, RW4 @RW4+d8
MOVW RW6, MOVW
@RW1+RW7 RW7, @RW1+
MOVW
MOVW RW6,
RW6,@RW3 @RW3+d16
MOVW
MOVW RW6,
RW6,@RW2 @RW2+d16
MOVW
MOVW RW6,
RW6,@RW1 @RW1+d16
MOVW
MOVW RW6,
RW6,@RW0 @RW0+d16
MOVW
MOVW RW6,
RW6, RW7 @RW7+d8
MOVW
MOVW RW6,
RW6, RW6 @RW6+d8
MOVW
MOVW RW6,
RW6, RW5 @RW5+d8
MOVW
MOVW RW6,
RW6, RW4 @RW4+d8
MOVW
MOVW
@RW1+RW7 RW6, @RW1+
MOVW
MOVW RW5,
RW5, RW6 @RW6+d8
MOVW
MOVW RW5,
RW5, RW5 @RW5+d8
MOVW RW4, MOVW
@RW1+RW7 RW5, @RW1+
MOVW
MOVW
RW4, @RW3+ RW4, addr16
MOVW RW3, MOVW
@RW1+RW7 RW4, @RW1+
MOVW
MOVW RW5,
RW5,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW0 @RW0+d16 RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16 RW3,@RW0 @RW0+d16 RW4,@RW0 @RW0+d16
+8
MOVW RW2, MOVW
@RW1+RW7 RW3, @RW1+
MOVW
MOVW RW5,
RW5,@RW1 @RW1+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
MOVW
MOVW
RW0, RW7 @RW7+d8
+7
MOVW RW1, MOVW
@RW1+RW7 RW2, @RW1+
MOVW
MOVW RW5,
RW5,@RW0 @RW0+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
MOVW
MOVW
RW0, RW6 @RW6+d8
+6
MOVW
MOVW
@RW1+RW7 RW1, @RW1+
MOVW
MOVW RW5,
RW5, RW7 @RW7+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
MOVW
MOVW
RW0, RW5 @RW5+d8
+5
MOVW
MOVW RW5,
RW5, RW4 @RW4+d8
MOVW
MOVW RW7,
RW7, RW3 @RW3+d8
MOVW
MOVW RW7,
RW7, RW2 @RW2+d8
MOVW
MOVW RW7,
RW7, RW1 @RW1+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
MOVW
MOVW RW6,
RW6, RW3 @RW3+d8
MOVW
MOVW RW6,
RW6, RW2 @RW2+d8
MOVW
MOVW RW6,
RW6, RW1 @RW1+d8
MOVW
MOVW
RW0, RW4 @RW4+d8
MOVW
MOVW RW5,
RW5, RW3 @RW3+d8
MOVW
MOVW RW5,
RW5, RW2 @RW2+d8
MOVW
MOVW RW5,
RW5, RW1 @RW1+d8
+4
F0
MOVW
MOVW RW7,
RW7, RW0 @RW0+d8
E0
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
D0
MOVW
MOVW RW6,
RW6, RW0 @RW0+d8
C0
MOVW
MOVW
RW0, RW3 @RW3+d8
B0
MOVW
MOVW RW5,
RW5, RW0 @RW0+d8
A0
+3
90
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
80
MOVW
MOVW
RW0, RW2 @RW2+d8
70
+2
60
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
50
MOVW
MOVW
RW0, RW1 @RW1+d8
40
+1
30
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
20
MOVW
MOVW
RW0, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-17 MOVW RWi, ea Instruction (First Byte = 7BH)
537
538
+F
+E
+D
+C
+B
+A
+9
+8
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R1 addr16, R1
MOV
MOV
@RW3+, R0 addr16, R0
MOV
MOV
MOV
@RW2+, R1 @PC+d16, R1
@RW2+, R0 @PC+d16, R0
MOV
MOV
MOV
MOV
MOV
@RW0+, R1 @RW0+RW7, R1
MOV
@RW3, R1 @RW3+d16, R1
MOV
@RW2, R1 @RW2+d16, R1
MOV
@RW1, R1 @RW1+d16, R1
MOV
@RW1+, R1 @RW1+RW7, R1
MOV
MOV
@RW0, R1 @RW0+d16, R1
MOV
@RW1+, R0 @RW1+RW7, R0
MOV
@RW0+, R0 @RW0+RW7, R0
MOV
@RW3, R0 @RW3+d16, R0
MOV
@RW2, R0 @RW2+d16, R0
MOV
@RW1, R0 @RW1+d16, R0
MOV
@RW0, R0 @RW0+d16, R0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R2 addr16, R2
MOV
@RW2+, R2 @PC+d16, R2
MOV
@RW1+, R2 @RW1+RW7, R2
MOV
@RW0+, R2 @RW0+RW7, R2
MOV
@RW3, R2 @RW3+d16, R2
MOV
@RW2, R2 @RW2+d16, R2
MOV
@RW1, R2 @RW1+d16, R2
MOV
@RW0, R2 @RW0+d16, R2
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R3 addr16, R3
MOV
@RW2+, R3 @PC+d16, R3
MOV
@RW1+, R3 @RW1+RW7, R3
MOV
@RW0+, R3 @RW0+RW7, R3
MOV
@RW3, R3 @RW3+d16, R3
MOV
@RW2, R3 @RW2+d16, R3
MOV
@RW1, R3 @RW1+d16, R3
MOV
@RW0, R3 @RW0+d16, R3
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R4 addr16, R4
MOV
@RW2+, R4 @PC+d16, R4
MOV
@RW1+, R4 @RW1+RW7, R4
MOV
@RW0+, R4 @RW0+RW7, R4
MOV
@RW3, R4 @RW3+d16, R4
MOV
@RW2, R4 @RW2+d16, R4
MOV
@RW1, R4 @RW1+d16, R4
MOV
@RW0, R4 @RW0+d16, R4
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R5 addr16, R5
MOV
@RW2+, R5 @PC+d16, R5
MOV
@RW1+, R5 @RW1+RW7, R5
MOV
@RW0+, R5 @RW0+RW7, R5
MOV
@RW3, R5 @RW3+d16, R5
MOV
@RW2, R5 @RW2+d16, R5
MOV
@RW1, R5 @RW1+d16, R5
MOV
@RW0, R5 @RW0+d16, R5
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R6 addr16, R6
MOV
@RW2+, R6 @PC+d16, R6
MOV
@RW1+, R6 @RW1+RW7, R6
MOV
@RW0+, R6 @RW0+RW7, R6
MOV
@RW3, R6 @RW3+d16, R6
MOV
@RW2, R6 @RW2+d16, R6
MOV
@RW1, R6 @RW1+d16, R6
MOV
@RW0, R6 @RW0+d16,
R6
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R7 addr16, R7
MOV
@RW2+, R7 @PC+d16, R7
MOV
@RW1+, R7 @RW1+RW7, R7
MOV
@RW0+, R7 @RW0+RW7, R7
MOV
@RW3, R7 @RW3+d16, R7
MOV
@RW2, R7 @RW2+d16, R7
MOV
@RW1, R7 @RW1+d16, R7
MOV
@RW0, R7 @RW0+d16, R7
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R7, R0 @RW7+d8, R0
R7, R1 @RW7+d8, R1
R7, R2 @RW7+d8, R2
R7, R3 @RW7+d8, R3
R7, R4 @RW7+d8, R4
R7, R5 @RW7+d8, R5
R7, R6 @RW7+d8, R6
R7, R7 @RW7+d8, R7
F0
+7
E0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R6, R0 @RW6+d8, R0
R6, R1 @RW6+d8, R1
R6, R2 @RW6+d8, R2
R6, R3 @RW6+d8, R3
R6, R4 @RW6+d8, R4
R6, R5 @RW6+d8, R5
R6, R6 @RW6+d8, R6
R6, R7 @RW6+d8, R7
D0
+6
C0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R5, R0 @RW5+d8, R0
R5, R1 @RW5+d8, R1
R5, R2 @RW5+d8, R2
R5, R3 @RW5+d8, R3
R5, R4 @RW5+d8, R4
R5, R5 @RW5+d8, R5
R5, R6 @RW5+d8, R6
R5, R7 @RW5+d8, R7
B0
+5
A0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R4, R0 @RW4+d8, R0
R4, R1 @RW4+d8, R1
R4, R2 @RW4+d8, R2
R4, R3 @RW4+d8, R3
R4, R4 @RW4+d8, R4
R4, R5 @RW4+d8, R5
R4, R6 @RW4+d8, R6
R4, R7 @RW4+d8, R7
90
+4
80
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R3, R0 @RW3+d8, R0
R3, R1 @RW3+d8, R1
R3, R2 @RW3+d8, R2
R3, R3 @RW3+d8, R3
R3, R4 @RW3+d8, R4
R3, R5 @RW3+d8, R5
R3, R6 @RW3+d8, R6
R3, R7 @RW3+d8, R7
70
+3
60
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R2, R0 @RW2+d8, R0
R2, R1 @RW2+d8, R1
R2, R2 @RW2+d8, R2
R2, R3 @RW2+d8, R3
R2, R4 @RW2+d8, R4
R2, R5 @RW2+d8, R5
R2, R6 @RW2+d8, R6
R2, R7 @RW2+d8, R7
50
+2
40
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R1, R0 @RW1+d8, R0
R1, R1 @RW1+d8, R1
R1, R2 @RW1+d8, R2
R1, R3 @RW1+d8, R3
R1, R4 @RW1+d8, R4
R1, R5 @RW1+d8, R5
R1, R6 @RW1+d8, R6
R1, R7 @RW1+d8, R7
30
+1
20
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R0, R0 @RW0+d8, R0
R0, R1 @RW0+d8, R1
R0, R2 @RW0+d8, R2
R0, R3 @RW0+d8, R3
R0, R4 @RW0+d8, R4
R0, R5 @RW0+d8, R5
R0, R6 @RW0+d8, R6
R0, R7 @RW0+d8, R7
10
+0
00
APPENDIX
Table B.9-18 MOV ea, Ri Instruction (First Byte = 7CH)
MOVW
[email protected]
@RW2, RW1 +d16, RW1
MOVW
[email protected]
@RW3, RW1 +d16, RW1
MOVW
[email protected]
@RW0+, RW1 +RW7,RW1
MOVW
[email protected]
@RW1+,RW1 +RW7,RW1
MOVW
[email protected]
@RW2+,RW1 +d16, RW1
MOVW
MOVW
@RW3+,RW1 addr16, RW1
MOVW
[email protected]
@RW2, RW0 +d16, RW0
MOVW
[email protected]
@RW3, RW0 +d16, RW0
MOVW
[email protected]
@RW0+,RW0 +RW7,RW0
MOVW
[email protected]
@RW1+,RW0 +RW7,RW0
MOVW
[email protected]
@RW2+,RW0 +d16, RW0
MOVW
MOVW
@RW3+,RW0 addr16, RW0
+B
+C
+D
+E
+F
MOVW
MOVW
@RW3+,RW2 addr16, RW2
MOVW
[email protected]
@RW2+,RW2 +d16, RW2
MOVW
[email protected]
@RW1+,RW2 +RW7,RW2
MOVW
[email protected]
@RW0+,RW2 +RW7,RW2
MOVW
[email protected]
@RW3, RW2 +d16, RW2
MOVW
[email protected]
@RW2, RW2 +d16, RW2
MOVW
MOVW
@RW3+,RW3 addr16, RW3
MOVW
[email protected]
@RW2+,RW3 +d16, RW3
MOVW
[email protected]
@RW1+,RW3 -+RW7,RW3
MOVW
[email protected]
@RW0+,RW3 +RW7,RW3
MOVW
[email protected]
@RW3, RW3 +d16, RW3
MOVW
[email protected]
@RW2, RW3 +d16, RW3
MOVW
[email protected]
@RW1, RW3 +d16, RW3
MOVW
MOVW
@RW3+,RW4 addr16, RW4
MOVW
[email protected]
@RW2+,RW4 +d16, RW4
MOVW
[email protected]
@RW1+,RW4 +RW7,RW4
MOVW
[email protected]
@RW0+,RW4 +RW7,RW4
MOVW
[email protected]
@RW3, RW4 +d16, RW4
MOVW
[email protected]
@RW2, RW4 +d16, RW4
MOVW
[email protected]
@RW1, RW4 +d16, RW4
MOVW
MOVW
@RW3+,RW5 addr16, RW5
MOVW
[email protected]
@RW2+,RW5 +d16, RW5
MOVW
[email protected]
@RW1+,RW5 +RW7,RW5
MOVW
[email protected]
@RW0+,RW5 +RW7,RW5
MOVW
[email protected]
@RW3, RW5 +d16, RW5
MOVW
[email protected]
@RW2, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW5 +d16, RW5
MOVW
MOVW
@RW3+,RW6 addr16, RW6
MOVW
MOVW @PC
@RW2+,RW6 +d16, RW6
MOVW
[email protected]
@RW1+,RW6 +RW7,RW6
MOVW
[email protected]
@RW0+,RW6 +RW7,RW6
MOVW
[email protected]
@RW3, RW6 +d16, RW6
MOVW
[email protected]
@RW2, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW6 +d16, RW6
MOVW
MOVW
@RW3+,RW7 addr16, RW7
MOVW
[email protected]
@RW2+,RW7 +d16, RW7
MOVW
[email protected]
@RW1+,RW7 +RW7,RW7
MOVW
[email protected]
@RW0+,RW7 +RW7,RW7
MOVW
[email protected]
@RW3, RW7 +d16, RW7
MOVW
[email protected]
@RW2, RW7 +d16, RW7
MOVW
[email protected]
@RW1, RW7 +d16, RW7
MOVW
[email protected]
@RW0, RW7 +d16, RW7
+A
MOVW
[email protected]
@RW1, RW2 +d16, RW2
MOVW
[email protected]
@RW0, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW1 +d16, RW1
MOVW
[email protected]
@RW0, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW0 +d16, RW0
MOVW
[email protected]
@RW0, RW4 +d16, RW4
+9
MOVW
[email protected]
@RW0, RW3 +d16, RW3
MOVW
[email protected]
@RW0, RW1 +d16, RW1
MOVW
[email protected]
@RW0, RW0 +d16, RW0
+8
MOVW
[email protected]
@RW0, RW2 +d16, RW2
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW7, RW0 @RW7+d8, RW0
RW7, RW1 @RW7+d8, RW1 RW7, RW2 @RW7+d8, RW2 RW7, RW3 @RW7+d8, RW3 RW7, RW4 @RW7+d8, RW4 RW7, RW5 @RW7+d8, RW5 RW7, RW6 @RW7+d8, RW6 RW7, RW7 @RW7+d8, RW7
F0
+7
E0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW6, RW0 @RW6+d8, RW0
RW6, RW1 @RW6+d8, RW1 RW6, RW2 @RW6+d8, RW2 RW6, RW3 @RW6+d8, RW3 RW6, RW4 @RW6+d8, RW4 RW6, RW5 @RW6+d8, RW5 RW6, RW6 @RW6+d8, RW6 RW6, RW7 @RW6+d8, RW7
D0
+6
C0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW5, RW0 @RW5+d8, RW0
RW5, RW1 @RW5+d8, RW1 RW5, RW2 @RW5+d8, RW2 RW5, RW3 @RW5+d8, RW3 RW5, RW4 @RW5+d8, RW4 RW5, RW5 @RW5+d8, RW5 RW5, RW6 @RW5+d8, RW6 RW5, RW7 @RW5+d8, RW7
B0
+5
A0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW4, RW0 @RW4+d8, RW0
RW4, RW1 @RW4+d8, RW1 RW4, RW2 @RW4+d8, RW2 RW4, RW3 @RW4+d8, RW3 RW4, RW4 @RW4+d8, RW4 RW4, RW5 @RW4+d8, RW5 RW4, RW6 @RW4+d8, RW6 RW4, RW7 @RW4+d8, RW7
90
+4
80
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW3, RW0 @RW3+d8, RW0
RW3, RW1 @RW3+d8, RW1 RW3, RW2 @RW3+d8, RW2 RW3, RW3 @RW3+d8, RW3 RW3, RW4 @RW3+d8, RW4 RW3, RW5 @RW3+d8, RW5 RW3, RW6 @RW3+d8, RW6 RW3, RW7 @RW3+d8, RW7
70
+3
60
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW2, RW0 @RW2+d8, RW0
RW2, RW1 @RW2+d8, RW1 RW2, RW2 @RW2+d8, RW2 RW2, RW3 @RW2+d8, RW3 RW2, RW4 @RW2+d8, RW4 RW2, RW5 @RW2+d8, RW5 RW2, RW6 @RW2+d8, RW6 RW2, RW7 @RW2+d8, RW7
50
+2
40
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW1, RW0 @RW1+d8, RW0
RW1, RW1 @RW1+d8, RW1 RW1, RW2 @RW1+d8, RW2 RW1, RW3 @RW1+d8, RW3 RW1, RW4 @RW1+d8, RW4 RW1, RW5 @RW1+d8, RW5 RW1, RW6 @RW1+d8, RW6 RW1, RW7 @RW1+d8, RW7
30
+1
20
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW0, RW0 @RW0+d8, RW0
RW0, RW1 @RW0+d8, RW1 RW0, RW2 @RW0+d8, RW2 RW0, RW3 @RW0+d8, RW3 RW0, RW4 @RW0+d8, RW4 RW0, RW5 @RW0+d8, RW5 RW0, RW6 @RW0+d8, RW6 RW0, RW7 @RW0+d8, RW7
10
+0
00
APPENDIX B Instructions
Table B.9-19 MOVW ea, Rwi Instruction (First Byte = 7DH)
539
540
XCH
XCH
XCH
XCH
R1,
XCH
XCH R1,
R1,@RW2 W2+d16, A
XCH
XCH
R2,
XCH
XCH R2,
R2,@RW2 W2+d16, A
XCH
XCH
R3,
XCH
XCH R3,
R3,@RW2 W2+d16, A
XCH
XCH
R4,
XCH
XCH R4,
R4,@RW2 W2+d16, A
XCH
XCH
R5,
XCH
XCH R5,
R5,@RW2 W2+d16, A
XCH
XCH
R6,
XCH
XCH R6,
R6,@RW2 W2+d16, A
XCH
XCH
R7,
XCH
XCH R7,
R7,@RW2 W2+d16, A
XCH
XCH
XCH
XCH
XCH
R1, XCH
XCH
R2, XCH
XCH
R3, XCH
XCH
R4, XCH
XCH
R5, XCH
XCH
R6, XCH
XCH
R7,
+F R0,@RW3+ R0, addr16
XCH
XCH
R1,@RW3+ R1, addr16
XCH
XCH
R2,@RW3+ R2, addr16
XCH
XCH
R3,@RW3+ R3, addr16
XCH
XCH
R4,@RW3+ R4, addr16
XCH
XCH
R5,@RW3+ R5, addr16
XCH
XCH
R6,@RW3+ R6, addr16
XCH
XCH
R7,@RW3+ R7, addr16
+E R0,@RW2+ @PC+d16 R1,@RW2+ @PC+d16 R2,@RW2+ @PC+d16 R3,@RW2+ @PC+d16 R4,@RW2+ @PC+d16 R5,@RW2+ @PC+d16 R6,@RW2+ @PC+d16 R7,@RW2+ @PC+d16
R0, XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW1+RW7 R1,@RW1+ @RW1+RW7 R2,@RW1+ @RW1+RW7 R3,@RW1+ @RW1+RW7 R4,@RW1+ @RW1+RW7 R5,@RW1+ @RW1+RW7 R6,@RW1+ @RW1+RW7 R7,@RW1+ @RW1+RW7
+D R0,@RW1+
XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW0+RW7 R1,@RW0+ @RW0+RW7 R2,@RW0+ @RW0+RW7 R3,@RW0+ @RW0+RW7 R4,@RW0+ @RW0+RW7 R5,@RW0+ @RW0+RW7 R6,@RW0+ @RW0+RW7 R7,@RW0+ @RW0+RW7
XCH
+C R0,@RW0+
+B R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
R0,
+A R0,@RW2 W2+d16, A
R0,
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
+9
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
+8
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
F0
+7
E0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX
Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH)
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2+ @PC+d16
RW1,@RW2+ @PC+d16
RW2,@RW2+ @PC+d16
RW3,@RW2+ @PC+d16
RW4,@RW2+ @PC+d16
RW5,@RW2+ @PC+d16
RW6,@RW2+ @PC+d16
RW7,@RW2+ @PC+d16
XCHW
XCHW
RW0,@RW3+ RW0, addr16
+E
+F
XCHW
XCHW
RW7,@RW3+ RW7, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW1+ @RW1+RW7 RW1,@RW1+ @RW1+RW7 RW2,@RW1+ @RW1+RW7 RW3,@RW1+ @RW1+RW7 RW4,@RW1+ @RW1+RW7 RW5,@RW1+ @RW1+RW7 RW6,@RW1+ @RW1+RW7 RW7,@RW1+ @RW1+RW7
+D
XCHW
XCHW
RW6,@RW3+ RW6, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
+C
XCHW
XCHW
RW5,@RW3+ RW5, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW3 @RW3+d16
RW1,@RW3 @RW3+d16
RW2,@RW3 @RW3+d16
RW3,@RW3 @RW3+d16
RW4,@RW3 @RW3+d16
RW5,@RW3 @RW3+d16
RW6,@RW3 @RW3+d16
RW7,@RW3 @RW3+d16
+B
XCHW
XCHW
RW4,@RW3+ RW4, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2 @RW2+d16
RW1,@RW2 @RW2+d16
RW2,@RW2 @RW2+d16
RW3,@RW2 @RW2+d16
RW4,@RW2 @RW2+d16
RW5,@RW2 @RW2+d16
RW6,@RW2 @RW2+d16
RW7,@RW2 @RW2+d16
+A
XCHW
XCHW
RW3,@RW3+ RW3, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW1 @RW1+d16
RW1,@RW1 @RW1+d16
RW2,@RW1 @RW1+d16
RW3,@RW1 @RW1+d16
RW4,@RW1 @RW1+d16
RW5,@RW1 @RW1+d16
RW6,@RW1 @RW1+d16
RW7,@RW1 @RW1+d16
+9
XCHW
XCHW
RW2,@RW3+ RW2, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW0 @RW0+d16
RW1,@RW0 @RW0+d16
RW2,@RW0 @RW0+d16
RW3,@RW0 @RW0+d16
RW4,@RW0 @RW0+d16
RW5,@RW0 @RW0+d16
RW6,@RW0 @RW0+d16
RW7,@RW0 @RW0+d16
+8
XCHW
XCHW
RW1,@RW3+ RW1, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW7 @RW7+d8
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
RW5, RW7 @RW7+d8
RW6, RW7 @RW7+d8
RW7, RW7 @RW7+d8
F0
+7
E0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW6 @RW6+d8
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
RW5, RW6 @RW6+d8
RW6, RW6 @RW6+d8
RW7, RW6 @RW6+d8
D0
+6
C0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW5 @RW5+d8
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
RW5, RW5 @RW5+d8
RW6, RW5 @RW5+d8
RW7, RW5 @RW5+d8
B0
+5
A0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW4 @RW4+d8
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
RW5, RW4 @RW4+d8
RW6, RW4 @RW4+d8
RW7, RW4 @RW4+d8
90
+4
80
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW3 @RW3+d8
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
RW5, RW3 @RW3+d8
RW6, RW3 @RW3+d8
RW7, RW3 @RW3+d8
70
+3
60
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW2 @RW2+d8
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
RW5, RW2 @RW2+d8
RW6, RW2 @RW2+d8
RW7, RW2 @RW2+d8
50
+2
40
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW1 @RW1+d8
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
RW5, RW1 @RW1+d8
RW6, RW1 @RW1+d8
RW7, RW1 @RW1+d8
30
+1
20
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW0 @RW0+d8
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
RW5, RW0 @RW0+d8
RW6, RW0 @RW0+d8
RW7, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-21 XCHW RWi, ea Instruction (First Byte = 7FH)
541
APPENDIX
542
INDEX
INDEX
The index follows on the next page.
This is listed in alphabetic order.
543
INDEX
Index
Numerics
16-bit Data Bus
Status of Each Pin in External BUS 16-bit Data
Bus Mode .......................................... 112
16-bit Free-run Timer
16-bit Free-run Timer ....................................... 178
16-bit Free-run Timer Operation ........................ 186
16-bit Free-run Timer Timing............................ 187
Block Diagram of 16-bit Free-run Timer ............ 181
16-bit I/O Timer
16-bit I/O Timer Registers................................. 180
Block Diagram of 16-bit I/O Timer .................... 179
16-bit Reload Register
16-bit Timer Register (TMR)/16-bit Reload
Register (TMRLR) ............................. 210
16-bit Reload Timer
16-bit Reload Timer ......................................... 205
16-bit Reload Timer Register............................. 206
Block Diagram of 16-bit Reload Timer............... 204
Input Pin Functions of 16-bit Reload Timer
(in Internal Clock Mode) ..................... 212
Internal Clock Operation of 16-bit
Reload Timer ...................................... 211
Outline of 16-bit Reload Timer (with Event
Count Function) ................................. 204
Output Pin Functions of 16-bit Reload Timer ...... 214
Underflow Operation of 16-bit Reload Timer...... 213
544
16-bit Timer Register
16-bit Timer Register (TMR)/16-bit Reload
Register (TMRLR) ............................. 210
1M-bit Flash Memory
1M-bit Flash Memory Features ......................... 422
Programming example of 1M-bit
Flash Memory .................................... 452
Sector Configuration of the 1M-bit
Flash Memory .................................... 423
24-bit Operand
24-bit Operand Specification............................... 23
32-bit Register
32-bit Register Indirect Specification ................... 23
8/16-bit PPG
8/16-bit PPG Interrupts..................................... 234
8/16-bit PPG Output Operation ......................... 231
8/16-bit PPG Registers ..................................... 221
Block Diagram of 8/16-bit PPG......................... 219
Controlling Pin Output of 8/16-bit PPG
Pulses ................................................ 233
Function of 8/16-bit PPG .................................. 218
Initial Values of 8/16-bit PPG Hardware ............ 235
Operation Modes of 8/16-bit PPG...................... 230
Operations of 8/16-bit PPG ............................... 230
Relationship Between 8/16-bit PPG Reload Value
and Pulse Width................................. 231
Selecting a Count Clock for 8/16-bit PPG .......... 232
8-bit Data Bus
Status of Each Pin in External BUS 8-bit Data
Bus Mode.......................................... 113
INDEX
A
A
Accumulator (A)................................................ 30
A/D Control Status Register
A/D Control Status Register (ADCS1) ............... 259
A/D Control Status Registers (ADCS0).............. 256
A/D Converter
A/D Converter Registers................................... 255
Block Diagram of A/D Converter ...................... 254
Features of A/D Converter ................................ 252
Acceptance Filter
Setting Acceptance Filter .................................. 398
Acceptance Filtering
Acceptance Filtering ........................................ 394
Acceptance Mask Register
Acceptance Mask Registers 0 and 1 (AMR0 and
AMR1) ............................................. 383
Acceptance Mask Select Register
Acceptance Mask Select Register (AMSR)......... 381
Accumulator
Accumulator (A)................................................ 30
ADCR
Data Registers (ADCR1 and ADCR0)................ 262
ADCS
A/D Control Status Register (ADCS1) ............... 259
A/D Control Status Registers (ADCS0).............. 256
Address Generation
Address Generation Types .................................. 21
Address Match Detection
Block Diagram of the Address Match Detection
Function ............................................ 410
Operation of the Address Match Detection
Function............................................. 413
System Configuration Example of the Address
Match Detection Function ................... 414
Addressing
Addressing ...................................................... 483
Direct Addressing ............................................ 485
Indirect Addressing .......................................... 491
ADER
Analog Input Enable Register (ADER)............... 158
Alternative Mode
Alternative Mode ............................................. 424
AMR
Acceptance Mask Registers 0 and 1 (AMR0 and
AMR1) ............................................. 383
AMSR
Acceptance Mask Select Register (AMSR)......... 381
Analog Input Enable Register
Analog Input Enable Register............................ 253
Analog Input Enable Register (ADER)............... 158
ARSR
Automatic Ready Function Selection Register
(ARSR) .............................................137
Asynchronous
Asynchronous (Start-Stop Synchronized) Mode
Data Transfer Format ...........................317
Asynchronous (Start-Stop Synchronized) Mode
Receive Operation ..............................317
Asynchronous (Start-Stop Synchronized) Mode
Transmit Operation .............................317
Automatic Ready Function Selection Register
Automatic Ready Function Selection Register
(ARSR) .............................................137
B
Bank
Register Bank.....................................................36
Bank Addressing
Bank Addressing Types.......................................24
Bank Select Prefix
Bank Select Prefix ..............................................38
BAP
Buffer Address Pointer (BAP) .............................63
Basic Configuration
Basic Configuration of MB90F443G Serial
Programming Connection .....................458
Baud Rate
CLK Asynchronous Baud Rate ..........................288
CLK Synchronous Baud Rate ............................287
Bit Timing Register
Bit Timing Register (BTR) ................................367
Block Diagram
Block Diagram .....................................................5
Block Diagram of 16-bit Free-run Timer.............181
Block Diagram of 16-bit I/O Timer ....................179
Block Diagram of 16-bit Reload Timer ...............204
Block Diagram of 8/16-bit PPG .........................219
Block Diagram of A/D Converter.......................254
Block Diagram of CAN Controller .....................349
Block Diagram of Delayed Interrupt...................238
Block Diagram of DTP/External Interrupts .........242
Block Diagram of External Memory Access........135
Block Diagram of Input Capture ........................197
Block Diagram of Output Compare ....................188
Block Diagram of Pull-up Control Register
(PUCR) ..............................................157
Block Diagram of ROM Mirroring Function
Selection Module................................418
Block Diagram of the Address Match Detection
Function ............................................410
Block Diagram of the Clock Generation Block ......73
Block Diagram of the External Reset Pin ............122
Block Diagram of the Low-Power Consumption
Control Circuit .....................................91
Block Diagram of Time-base Timer ...................161
545
INDEX
Block Diagram of UART1 ................................ 303
Block Diagram of Watch Timer......................... 173
Block Diagram of Watchdog Timer ................... 167
Serial I/O Block Diagram.................................. 328
UART0 Block Diagram .................................... 277
BTR
Bit Timing Register (BTR)................................ 367
Buffer Address Pointer
Buffer Address Pointer (BAP) ............................. 63
Bus Control Signal Selection Register
Bus Control Signal Selection Register
(ECSR) .............................................. 140
Bus Mode
Memory Space in Each Bus Mode ..................... 133
Bus Operation
Conditions for Canceling Bus Operation Stop
(HALT=0) ......................................... 363
Conditions for Setting Bus Operation Stop
(HALT=1) .......................................... 363
State during Bus Operation Stop (HALT=1) ....... 363
Bus Pin Control Circuit
External Memory Access
(Bus Pin Control Circuit) ..................... 135
BVAL
Caution for Disabling Message Buffers by BVAL
bits..................................................... 407
BVALR
Message Buffer Valid Register (BVALR)........... 369
C
Calculating
Calculating the Execution Cycle Count .............. 500
CAN Controller
Block Diagram of CAN Controller..................... 349
Canceling a Transmission Request from the CAN
Controller .......................................... 391
Completing Transmission of the
CAN Controller................................... 392
Features of CAN Controller............................... 348
Reception Flowchart of the CAN Controller ....... 397
Starting Transmission of the
CAN Controller................................... 391
Transmission Flowchart of the
CAN Controller................................... 392
CAN2 RX/TX Pin Switching Register
CAN2 RX/TX Pin Switching Register
(CANSWR) ........................................ 406
CANSWR
CAN2 RX/TX Pin Switching Register
(CANSWR) ........................................ 406
CCR
Condition Code Register (CCR)........................... 32
546
CDCR
UART1 Prescaler Control Register
(U1CDCR) ......................................... 312
Chips
Erasing all Data in the Flash Memory
(Erasing Chips)................................... 444
Circuit
Block Diagram of the Low-Power Consumption
Control Circuit..................................... 91
External Memory Access
(Bus Pin Control Circuit) ..................... 135
CKSCR
Configuration of the Clock Selection Register
(CKSCR) ............................................ 75
CLK Asynchronous Baud Rate
CLK Asynchronous Baud Rate.......................... 288
CLK Synchronous Baud Rate
CLK Synchronous Baud Rate............................ 287
CLK Synchronous Mode
CLK Synchronous Mode Data Transfer
Format ............................................... 318
Control Register Settings for CLK Synchronous
Mode ................................................. 319
End of Communication in CLK Synchronous
Mode ................................................. 319
Start of Communication in CLK Synchronous
Mode ................................................. 319
Clock
Clock Mode....................................................... 89
Clock Mode Switching ..................................... 115
Clock Mode Transition ....................................... 79
Clocks .............................................................. 70
External Shift Clock Mode................................ 338
Input Pin Functions of 16-bit Reload Timer
(in Internal Clock Mode)..................... 212
Internal and External Clock............................... 290
Internal Clock Operation of 16-bit
Reload Timer...................................... 211
Internal Shift Clock Mode................................. 338
Machine Clock .................................................. 80
Main Clock Mode,PLL Clock Mode and Sub Clock
Mode .................................................. 79
Negative Clock Operation......................... 324, 345
Oscillation Clock Frequency and Serial Clock Input
Frequency ......................................... 461
Selecting a Count Clock for 8/16-bit PPG .......... 232
Selection of a PLL Clock Multiplier .................... 80
UART1 Clock Selection ................................... 314
Clock Generation Block
Block Diagram of the Clock Generation Block ..... 73
Clock Mode
Clock Mode....................................................... 89
Clock Mode Switching ..................................... 115
Clock Mode Transition ....................................... 79
INDEX
Clock Selection Register
Configuration of the Clock Selection Register
(CKSCR) ............................................ 75
Clock Supply Map
Clock Supply Map ............................................. 71
CMR
Common Register Bank Prefix (CMR)................. 39
Command
Command Sequence Table................................ 428
Command Sequence Table
Command Sequence Table................................ 428
Common Register Bank Prefix
Common Register Bank Prefix (CMR)................. 39
Communication
End of Communication in CLK Synchronous
Mode ................................................. 319
Start of Communication in CLK Synchronous
Mode ................................................. 319
UART1 Communication Flowchart ................... 325
Compare Register
Sample of a Output Waveform with Two Compare
Registers (The Initial Output Value is
"0".)................................................... 194
Sample of Output Waveform when Compare
Registers 0 and 1 are Used (The Initial
Output Value is "0".) .......................... 193
Condition Code Register
Condition Code Register (CCR) .......................... 32
Continuous Mode
Continuous Mode............................................. 264
Starting EI2OS in Continuous Mode .................. 269
Control Status Register
Control Status Register (CSR) ........................... 360
Control Status Register of Output Compare ........ 190
Conversion
Conversion Using EI2OS .................................. 266
Conversion Data
Conversion Data Protection............................... 273
Notes on Using the Conversion Data Protection
Function ............................................ 274
Count Clock
Selecting a Count Clock for 8/16-bit PPG........... 232
Counter Operation State
Counter Operation State.................................... 215
CPU
CPU Intermittent Operating Mode ....................... 89
CPU Intermittent Operation Mode ....................... 96
CPU Operating Modes and Current
Consumption ........................................ 88
Outline of CPU .................................................. 20
CPU Intermittent Operating Mode
CPU Intermittent Operating Mode ....................... 89
CPU Intermittent Operation Mode
CPU Intermittent Operation Mode ....................... 96
CPU Memory Space
Outline of CPU Memory Space............................21
CPU Operating Mode
CPU Operating Modes and Current
Consumption.........................................88
CSR
Control Status Register (CSR) ...........................360
Current Consumption
CPU Operating Modes and Current
Consumption.........................................88
D
Data Counter
Data Counter (DCT) ...........................................61
Data Format
Transfer Data Format ........................................291
Data Frame
Processing for Reception of Data Frame and
Remote Frame ....................................395
Data Polling Flag
Data Polling Flag (DQ7) ...................................432
Data Register
Data Register (TCDT).......................................182
Data Register x (x=0 to 15) (DTRx) ...................389
Data Registers (ADCR1 and ADCR0) ................262
List of Message Buffers (Data Registers) ............357
List of Message Buffers (DLC Registers and Data
Registers)...........................................355
DCT
Data Counter (DCT) ...........................................61
DDR
Port Direction Register (DDR) ...........................155
Delayed Interrupt
Block Diagram of Delayed Interrupt...................238
Delayed Interrupt Occurrence ............................240
Delayed Interrupt Cause Issuance/Cancellation
Register
Delayed Interrupt Cause Issuance/Cancellation
Register (DIRR) .................................239
Description
Description of Instruction Presentation Items and
Symbols.............................................503
Device
Handling the Device ...........................................16
Dimensions
FPT-100P-M06 Package Dimensions .....................6
Direct Addressing
Direct Addressing .............................................485
DIRR
Delayed Interrupt Cause Issuance/Cancellation
Register (DIRR) .................................239
DLC Register
DLC Register x (x=0 to 15) (DLCRx).................388
547
INDEX
List of Message Buffers (DLC Registers and Data
Registers) .......................................... 355
DLCRx
DLC Register x (x=0 to 15) (DLCRx) ................ 388
DQ
Data Polling Flag (DQ7) ................................... 432
DQ2
Toggle Bit-2 Flag (DQ2)................................... 438
DQ3
Sector Erase Timer Flag (DQ3) ......................... 436
DQ5
Timing Limit Exceeded Flag (DQ5) ................... 435
DQ6
Toggle Bit Flag (DQ6)...................................... 434
DTP
DTP operation.................................................. 246
Switching Between External Interrupt and DTP
Requests ............................................ 248
DTP/External Interrupt
Block Diagram of DTP/External Interrupts ......... 242
DTP/External Interrupts Registers...................... 243
Notes on Using DTP/External Interrupts............. 249
Outline of DTP/External Interrupts .................... 242
DTP/Interrupt Flags
DTP/Interrupt Flags (EIRR: External Interrupt
Request Register) ............................... 244
DTRx
Data Register x (x=0 to 15) (DTRx) ................... 389
E
ECSR
Bus Control Signal Selection Register
(ECSR) .............................................. 140
Effective Address Field
Effective Address Field............................. 484, 502
EI2OS
Conversion Using EI2OS .................................. 266
EI2OS (Extended Intelligent I/O Service) ........... 297
Execution Time of the Extended Intelligent I/O
Service (EI2OS) ................................... 66
Extended Intelligent I/O Service (EI2OS) ............. 56
Flow of Data Protection Function (When EI2OS is
Used) ................................................ 274
Intelligent I/O Service (EI2OS) .......................... 326
Intelligent I/O Service (EI2OS) Function and
Interrupts ........................................... 204
Operation Flow of the Extended Intelligent I/O
Service (EI2OS) ................................... 64
Starting EI2OS in Continuous Mode................... 269
Starting EI2OS in Single Mode .......................... 267
Starting EI2OS in Stop Mode............................. 271
EI2OS Status Register
EI2OS Status Register (ISCS) .............................. 62
548
EIRR
DTP/Interrupt Flags (EIRR: External Interrupt
Request Register) ............................... 244
ELVR
Request Level Setting Register (ELVR: External
level register)..................................... 245
ENIR
DTP/Interrupt Enable Register (ENIR: Interrupt
Request Enable Register) .................... 244
Erase
Detailed Explanation of Flash Memory
Write/Erase ........................................ 440
Erasing
Erasing all Data in the Flash Memory
(Erasing Chips)................................... 444
Erasing Optional Data (Erasing Sectors) in the
Flash Memory ................................... 445
Erasing Sectors in the Flash Memory ................. 445
Restarting Erasing of Flash Memory Sectors ...... 448
Writing to/Erasing Flash Memory...................... 422
Event Count Function
Outline of 16-bit Reload Timer (with Event Count
Function)........................................... 204
Exception
Exception Due to Execution of an Undefined
Instruction ........................................... 68
Execution Cycle Count
Calculating the Execution Cycle Count .............. 500
Execution Cycle Count..................................... 499
Extended Intelligent I/O Service
EI2OS (Extended Intelligent I/O Service) ........... 297
Execution Time of the Extended Intelligent I/O
Service (EI2OS) ................................... 66
Extended Intelligent I/O Service (EI2OS) ............. 56
Operation Flow of the Extended Intelligent I/O
Service (EI2OS) ................................... 64
Extended Intelligent I/O Service Descriptor
Extended Intelligent I/O Service Descriptor
(ISD) ................................................... 61
External Address Output Control Register
External Address Output Control Register
(HACR) ............................................. 139
External BUS
Status of Each Pin in External BUS 16-bit Data
Bus Mode.......................................... 112
Status of Each Pin in External BUS 8-bit Data
Bus Mode.......................................... 113
External Clock
Connection of an Oscillator or an External Clock
to the Microcontroller........................... 84
Internal and External Clock............................... 290
External Event Counter
External Event Counter .................................... 212
INDEX
External Interrupt
External Interrupt Operation.............................. 246
Switching Between External Interrupt and DTP
Requests............................................ 248
External Interrupt Request Register
DTP/Interrupt Flags (EIRR: External Interrupt
Request Register) ............................... 244
External level register
Request Level Setting Register (ELVR: External
level register)..................................... 245
External Memory Access
Block Diagram of External Memory Access ....... 135
External Memory Access
(Bus Pin Control Circuit) ..................... 135
External Memory Access Control Signal ............ 143
External Memory Access Registers.................... 136
External Reset
Block Diagram of the External Reset Pin............ 122
External Shift Clock Mode
External Shift Clock Mode................................ 338
F
F2MC-16LX Instruction List
F2MC-16LX Instruction List ............................. 506
Fetch
Mode Fetch ..................................................... 124
Sample of Input Capture Fetch Timing............... 200
Filter
Setting Acceptance Filter .................................. 398
Flag
Data Polling Flag (DQ7)................................... 432
Flag Set Timings for a Receive Operation
(in Mode 0,1,or 3) .............................. 294
Flag Set Timings for a Receive Operation
(in Mode 2) ........................................ 295
Flag Set Timings for a Transmit Operation ......... 296
Hardware Sequence Flags ................................. 430
Sector Erase Timer Flag (DQ3) ......................... 436
Set Timings of the Six Flags ............................. 293
Status Flag during Transmit and Receive
Operation ........................................... 297
Timing Limit Exceeded Flag (DQ5)................... 435
Toggle Bit Flag (DQ6) ..................................... 434
Toggle Bit-2 Flag (DQ2) .................................. 438
UART1 Flags .................................................. 320
UART1 Interrupts and Flag Set Timing.............. 321
Flag Change Disable Prefix
Flag Change Disable Prefix (NCC) ...................... 40
Flash Memory
1M-bit Flash Memory Features ......................... 422
Detailed Explanation of Flash Memory
Write/Erase ........................................ 440
Erasing all Data in the Flash Memory
(Erasing Chips) ................................... 444
Erasing Optional Data (Erasing Sectors) in the
Flash Memory ....................................445
Erasing Sectors in the Flash Memory..................445
Flash Memory Control Signals...........................424
Flash Memory Register .....................................422
Notes on using Flash Memory............................449
Programming example of 1M-bit Flash
Memory..............................................452
Restarting Erasing of Flash Memory Sectors .......448
Sector Configuration of the 1M-bit
Flash Memory .....................................423
Setting the Flash Memory to the
Read/Reset State..................................441
Suspending Erasing of Flash Memory
Sectors................................................447
Writing Data to the Flash Memory .....................442
Writing to the Flash Memory .............................442
Writing to/Erasing Flash Memory ......................422
Flash Memory Control Status Register
Flash Memory Control Status Register
(FMCS) ..............................................426
Flash Memory Mode
Flash Memory Mode.........................................424
Flash Microcontroller Programmer
Example of Minimum Connection to the Flash
Microcontroller Programmer (Power
Supplied from the Programmer) ............468
Example of Minimum Connection to the Flash
Microcontroller Programmer (User Power
Supply Used)......................................466
Flash Security
Flash Security Feature.......................................451
Flow
Flow of Data Protection Function (When EI2OS is
Used).................................................274
Flowchart
Reception Flowchart of the CAN Controller........397
Transmission Flowchart of the
CAN Controller ...................................392
UART1 Communication Flowchart ....................325
FMCS
Flash Memory Control Status Register
(FMCS) ..............................................426
Format
Asynchronous (Start-Stop Synchronized) Mode
Data Transfer Format ...........................317
CLK Synchronous Mode Data Transfer
Format................................................318
Setting Frame Format........................................398
FPT-100P-M06
FPT-100P-M06 Package Dimensions .....................6
Frame
Processing for Reception of Data Frame and
Remote Frame ....................................395
Setting Frame Format........................................398
549
INDEX
Free-run Timer
16-bit Free-run Timer ....................................... 178
16-bit Free-run Timer Operation ........................ 186
16-bit Free-run Timer Timing............................ 187
Block Diagram of 16-bit Free-run Timer ............ 181
Frequency
Oscillation Clock Frequency and Serial Clock
Input Frequency ................................. 461
G
General-purpose Register
General-purpose Registers................................... 29
H
HACR
External Address Output Control Register
(HACR) ............................................. 139
HALT
Conditions for Canceling Bus Operation Stop
(HALT=0) ......................................... 363
Conditions for Setting Bus Operation Stop
(HALT=1) .......................................... 363
State during Bus Operation Stop (HALT=1) ....... 363
Hardware
Hardware Sequence Flags ................................. 430
Hardware Interrupt
Flow of Hardware Interrupt Operation.................. 53
Hardware Interrupt Operation.............................. 51
Hardware Interrupt Request during Writing to the
Input-Output Area ................................ 49
Hardware Interrupts............................................ 49
Structure of Hardware Interrupt ........................... 49
Hardware Sequence Flags
Hardware Sequence Flags ................................. 430
Hold Function
Hold Function .................................................. 147
I
I/O
I/O Circuits........................................................ 13
I/O Maps
I/O Maps ......................................................... 472
I/O Port
I/O Port Registers............................................. 152
Outline of I/O Ports .......................................... 150
I/O Register Address Pointer
I/O Register Address Pointer (IOA) ..................... 61
I/O Timer
16-bit I/O Timer Registers................................. 180
Block Diagram of 16-bit I/O Timer .................... 179
ICR
Interrupt Control Register (ICR) .......................... 58
550
ID
Setting ID........................................................ 398
ID Register
ID Register x (x=0 to 15) (IDRx)....................... 386
List of Message Buffers (ID registers)................ 352
IDE Register
IDE Register (IDER) ........................................ 370
IDER
IDE Register (IDER) ........................................ 370
IDRx
ID Register x (x=0 to 15) (IDRx)....................... 386
ILM
Interrupt Level Mask Register (ILM) ................... 33
Impedance
Input Impedance .............................................. 253
Indirect Addressing
Indirect Addressing .......................................... 491
Indirect Specification
32-bit Register Indirect Specification ................... 23
Input Capture
Block Diagram of Input Capture........................ 197
Input Capture................................................... 196
Input Capture (2 Channels per one Module) ....... 179
Input Capture Input Timing............................... 201
Sample of Input Capture Fetch Timing............... 200
Input Capture Control Status Register
Input Capture Control Status Register ................ 198
Input Capture Data Register
Input Capture Data Register .............................. 198
Input Data Register
Input Data Register 0 (UIDR0) and Output Data
Register 0 (UODR0)........................... 283
Input Impedance
Input Impedance .............................................. 253
Instruction
Description of Instruction Presentation Items and
Symbols ............................................ 503
Exception Due to Execution of an Undefined
Instruction ........................................... 68
F2MC-16LX Instruction List............................. 506
Instruction Types ............................................. 482
Interrupt Disable Instructions .............................. 41
Restrictions on Interrupt Disable Instructions and
Prefix Instructions ................................ 41
Structure of Instruction Map ............................. 520
Instruction Presentation Items and Symbols
Description of Instruction Presentation Items and
Symbols ............................................ 503
Intelligent I/O Service
Intelligent I/O Service (EI2OS).......................... 326
Intelligent I/O Service (EI2OS) Function and
Interrupts........................................... 204
INDEX
Interface
Interrupt Function of the Serial I/O Interface ...... 344
Internal
Internal and External Clock............................... 290
Internal Clock
Internal Clock Operation of 16-bit
Reload Timer...................................... 211
Internal Clock Mode
Input Pin Functions of 16-bit Reload Timer
(in Internal Clock Mode)..................... 212
Internal Shift Clock Mode
Internal Shift Clock Mode................................. 338
Interrupt
8/16-bit PPG Interrupts..................................... 234
Block Diagram of Delayed Interrupt .................. 238
Delayed Interrupt Occurrence............................ 240
Flow of Hardware Interrupt Operation ................. 53
Hardware Interrupt Operation.............................. 51
Hardware Interrupts ........................................... 49
Intelligent I/O Service (EI2OS) Function and
Interrupts........................................... 204
Interrupt Disable Instructions .............................. 41
Interrupt Function of the Serial I/O Interface ...... 344
Interrupt Sources................................................ 45
Interrupt Vector ................................................. 47
Interval Interrupt Function of Time-base
Timer................................................. 164
Interval Interrupt Function of Watch Timer ........ 176
Multiple Interrupts ............................................. 50
Note on Software Interrupt.................................. 55
Outline of Interrupts ........................................... 44
Restrictions on Interrupt Disable Instructions and
Prefix Instructions ................................ 41
Software Interrupt Operation............................... 54
Software Interrupts............................................. 54
Structure of Hardware Interrupt ........................... 49
Structure of Software Interrupts........................... 54
Switching to a Standby Mode and Interrupt ........ 114
UART1 Interrupt Sources ................................. 320
UART1 Interrupts and Flag Set Timing.............. 321
Interrupt Control Register
Interrupt Control Register (ICR) .......................... 58
Interrupt Disable Instruction
Interrupt Disable Instructions .............................. 41
Restrictions on Interrupt Disable Instructions and
Prefix Instructions ................................ 41
Interrupt Level Mask Register
Interrupt Level Mask Register (ILM) ................... 33
Interrupt Request Enable Register
DTP/Interrupt Enable Register (ENIR: Interrupt
Request Enable Register) .................... 244
Interrupt Sources
Interrupt Sources................................................ 45
UART1 Interrupt Sources ................................. 320
Interrupt Vector
Interrupt Vector ..................................................47
Interval Interrupt
Interval Interrupt Function of Time-base
Timer .................................................164
Interval Interrupt Function of Watch Timer .........176
IOA
I/O Register Address Pointer (IOA)......................61
ISCS
EI2OS Status Register (ISCS) ..............................62
ISD
Extended Intelligent I/O Service Descriptor
(ISD) ....................................................61
L
Last Event Indicator Register
Last Event Indicator Register (LEIR)..................364
LEIR
Last Event Indicator Register (LEIR)..................364
Low-Power Consumption Control Circuit
Block Diagram of the Low-Power Consumption
Control Circuit .....................................91
Low-power Consumption Mode
Setting Low-power Consumption Mode..............399
Low-Power Consumption Mode Control Register
Access to the Low-Power Consumption Mode
Control Register ...................................95
Low-Power Consumption Mode Control Register
(LPMCR).............................................93
Notes on Accessing the Low-Power Consumption
Mode Control Register (LPMCR) to
Enter the Standby Mode ......................116
LPMCR
Low-Power Consumption Mode Control Register
(LPMCR).............................................93
Notes on Accessing the Low-Power Consumption
Mode Control Register (LPMCR) to
Enter the Standby Mode ......................116
M
Machine Clock
Machine Clock ...................................................80
Main Clock Mode
Main Clock Mode,PLL Clock Mode and Sub Clock
Mode ...................................................79
MB90440G Series
Overview of MB90440G Series Products................2
MB90F443G
Basic Configuration of MB90F443G Serial
Programming Connection .....................458
Memory Access Mode
Memory Access Modes .....................................130
551
INDEX
Memory Space
Memory Space in Each Bus Mode ..................... 133
Memory Space Map ........................................... 22
Multi-byte Data Allocation in Memory Space ....... 26
Outline of CPU Memory Space ........................... 21
Message Buffer
Caution for Disabling Message Buffers by BVAL
bits..................................................... 407
List of Message Buffers (Data Registers)............ 357
List of Message Buffers (DLC Registers and Data
Registers) .......................................... 355
List of Message Buffers (ID registers) ................ 352
Message Buffers....................................... 359, 385
Procedure for Reception by Message Buffer
(x)...................................................... 402
Procedure for Transmission by Message Buffer
(x)...................................................... 400
Setting Configuration of Multi-level Message
Buffer ................................................ 404
Message Buffer Control Register
Message Buffer Control Registers...................... 359
Message Buffer Valid Register
Message Buffer Valid Register (BVALR)........... 369
Microcontroller
Connection of an Oscillator or an External Clock to
the Microcontroller ............................... 84
Minimum Connection
Example of Minimum Connection to the Flash
Microcontroller Programmer (Power
Supplied from the Programmer)............ 468
Example of Minimum Connection to the Flash
Microcontroller Programmer (User Power
Supply Used) ..................................... 466
Mode
Alternative Mode ............................................. 424
Asynchronous (Start-Stop Synchronized) Mode
Data Transfer Format........................... 317
Asynchronous (Start-Stop Synchronized) Mode
Receive Operation .............................. 317
Asynchronous (Start-Stop Synchronized) Mode
Transmit Operation............................. 317
CLK Synchronous Mode Data Transfer
Format ............................................... 318
Clock Mode ....................................................... 89
Clock Mode Switching ..................................... 115
Clock Mode Transition ....................................... 79
Continuous Mode ............................................. 264
Control Register Settings for CLK Synchronous
Mode ................................................. 319
CPU Intermittent Operating Mode ....................... 89
CPU Intermittent Operation Mode ....................... 96
CPU Operating Modes and Current
Consumption ........................................ 88
End of Communication in CLK Synchronous
Mode ................................................. 319
552
External Shift Clock Mode................................ 338
Flag Set Timings for a Receive Operation
(in Mode 0,1,or 3) .............................. 294
Flag Set Timings for a Receive Operation
(in Mode 2) ........................................ 295
Flash Memory Mode ........................................ 424
Input Pin Functions of 16-bit Reload Timer
(in Internal Clock Mode)..................... 212
Internal Shift Clock Mode................................. 338
Main Clock Mode,PLL Clock Mode and Sub Clock
Mode .................................................. 79
Memory Access Modes .................................... 130
Memory Space in Each Bus Mode ..................... 133
Mode Data ...................................................... 132
Mode Fetch ..................................................... 124
Mode Pins ............................................... 123, 131
Notes on Accessing the Low-Power Consumption
Mode Control Register (LPMCR) to
Enter the Standby Mode...................... 116
Operation Status during Standby Mode ................ 97
Operation Status in Each Operating Mode
Table ................................................. 110
Release of Sleep Mode ....................................... 98
Release of Stop Mode....................................... 107
Release of Time-base Timer Mode .................... 101
Release of Watch Mode.................................... 104
Setting Low-power Consumption Mode ............. 399
Single Mode .................................................... 264
Standby Mode ................................................... 89
Start of Communication in CLK Synchronous
Mode ................................................. 319
Starting EI2OS in Continuous Mode .................. 269
Starting EI2OS in Single Mode.......................... 267
Starting EI2OS in Stop Mode ............................ 271
Status of Each Pin in External BUS 16-bit Data
Bus Mode.......................................... 112
Status of Each Pin in External BUS 8-bit Data
Bus Mode.......................................... 113
Status of Each Pin in the Single Chip Mode........ 111
Stop Mode....................................................... 265
Switching to Sleep Mode .................................... 98
Switching to the Stop Mode .............................. 106
Switching to the Time-base Timer Mode............ 101
Switching to the Watch Mode ........................... 103
UART0 Operation Modes ................................. 286
UART1 Operating Modes ................................. 313
UART1 Sample Application (System Configuration
in Mode 1)......................................... 325
Mode Data
Status of Pins after Mode Data is Read............... 127
Mode Fetch
Mode Fetch ..................................................... 124
Multi-byte Data
Accessing Multi-byte Data.................................. 26
Multi-byte Data Allocation in Memory Space....... 26
INDEX
Multi-level Message Buffer
Setting Configuration of Multi-level Message
Buffer ................................................ 404
Multiple Interrupt
Multiple Interrupts ............................................. 50
Multiplier
Selection of a PLL Clock Multiplier .................... 80
N
NCC
Flag Change Disable Prefix (NCC) ...................... 40
Negative Clock Operation
Negative Clock Operation......................... 324, 345
O
Operand
24-bit Operand Specification............................... 23
Operating Mode
Operation Status in Each Operating Mode
Table ................................................. 110
UART1 Operating Modes ................................. 313
Operation
Status Flag during Transmit and Receive
Operation ........................................... 297
Operation Flow
Operation Flow of the Extended Intelligent I/O
Service (EI2OS) ................................... 64
Operation Mode
UART0 Operation Modes ................................. 286
Operation Mode Control Register
PPG1 Operation Mode Control Register
(PPGC1) ............................................ 224
Oscillation Clock Frequency
Oscillation Clock Frequency and Serial Clock
Input Frequency ................................. 461
Oscillation Stabilization Wait
Oscillation Stabilization Wait and Reset State..... 121
Oscillation Stabilization Wait Interval.................. 83
Reset Causes and Oscillation Stabilization Wait
Intervals ............................................ 120
Oscillation Stabilization Wait Time
Oscillation Stabilization Wait Time ................... 115
Oscillator
Connection of an Oscillator or an External Clock to
the Microcontroller............................... 84
Output Compare
Block Diagram of Output Compare.................... 188
Control Status Register of Output Compare ........ 190
Output Compare .............................................. 188
Output Compare (2 Channels per One
Module) ............................................. 178
Output Compare Register.................................. 189
Output Compare Timing....................................194
Output Data Register
Input Data Register 0 (UIDR0) and Output Data
Register 0 (UODR0) ...........................283
Output Waveform
Sample of a Output Waveform with Two Compare
Registers (The Initial Output Value is
"0".) ...................................................194
Sample of Output Waveform when Compare
Registers 0 and 1 are Used (The Initial
Output Value is "0".)...........................193
Overall Control Register
List of Overall Control Registers........................350
Overall Control Registers ..................................359
Overrun
Receive Overrun...............................................395
P
Package
FPT-100P-M06 Package Dimensions .....................6
PACSR
Program Address Detection Control Status Register
(PACSR) ...........................................411
PADR
Program Address Detection Registers (PADR0 and
PADR1).............................................411
Parity Bit
Parity Bit .........................................................292
PC
Program Counter (PC).........................................35
PDR
Port data Register (PDR) ...................................153
PILR
Port Input Level Register (PILR)........................154
Pin
Status of Pins after Mode Data is Read ...............127
Pin Assignment
Pin Assignment ....................................................7
Pin Functions
Pin Functions .......................................................8
PLL Clock
Selection of a PLL Clock Multiplier .....................80
PLL Clock Mode
Main Clock Mode,PLL Clock Mode and Sub Clock
Mode ...................................................79
Port data Register
Port data Register (PDR) ...................................153
Port Direction Register
Port Direction Register (DDR) ...........................155
Port Input Level Register
Port Input Level Register (PILR)........................154
553
INDEX
Power Supply
Example of Minimum Connection to the Flash
Microcontroller Programmer (Power
Supplied from the Programmer)............ 468
Example of Minimum Connection to the Flash
Microcontroller Programmer (User Power
Supply Used) ..................................... 466
PPG
8/16-bit PPG Interrupts ..................................... 234
8/16-bit PPG Output Operation.......................... 231
8/16-bit PPG Registers...................................... 221
Block Diagram of 8/16-bit PPG ......................... 219
Controlling Pin Output of 8/16-bit PPG
Pulses................................................. 233
Function of 8/16-bit PPG .................................. 218
Initial Values of 8/16-bit PPG Hardware............. 235
Operation Modes of 8/16-bit PPG ...................... 230
Operations of 8/16-bit PPG ............................... 230
PPG0/1 Clock Selection Register (PPG01) ......... 227
Relationship Between 8/16-bit PPG Reload Value
and Pulse Width ................................. 231
Selecting a Count Clock for 8/16-bit PPG ........... 232
PPG0 Operation Mode Control Register
PPG0 Operation Mode Control Register
(PPGC0)............................................. 222
PPG0/1 Clock Selection Register
PPG0/1 Clock Selection Register (PPG01) ......... 227
PPG1
PPG1 Operation Mode Control Register
(PPGC1)............................................. 224
PPGC
PPG0 Operation Mode Control Register
(PPGC0)............................................. 222
PPG1 Operation Mode Control Register
(PPGC1)............................................. 224
Prefix
Bank Select Prefix.............................................. 38
Common Register Bank Prefix (CMR) ................. 39
Flag Change Disable Prefix (NCC) ...................... 40
Prefix Codes
Consecutive Prefix Codes ................................... 41
Prefix Instruction
Restrictions on Interrupt Disable Instructions and
Prefix Instructions ................................ 41
PRLH
Reload Register (PRLL/PRLH) ......................... 229
PRLL
Reload Register (PRLL/PRLH) ......................... 229
Processor Status
Processor Status (PS).......................................... 32
Program Address Detection Control Status Register
Program Address Detection Control Status Register
(PACSR) ........................................... 411
554
Program Address Detection Register
Program Address Detection Registers (PADR0 and
PADR1) ............................................ 411
Program Counter
Program Counter (PC) ........................................ 35
program patch processing
Example of program patch processing................ 415
Programming example
Programming example of 1M-bit
Flash Memory .................................... 452
Protection
Conversion Data Protection .............................. 273
Flow of Data Protection Function (When EI2OS is
Used) ................................................ 274
Notes on Using the Conversion Data Protection
Function............................................ 274
PS
Processor Status (PS) ......................................... 32
PUCR
Block Diagram of Pull-up Control Register
(PUCR).............................................. 157
Pull-up Control Register (PUCR) ...................... 156
Pull-up Control Register
Block Diagram of Pull-up Control Register
(PUCR).............................................. 157
Pull-up Control Register (PUCR) ...................... 156
Pulse Width
Relationship Between 8/16-bit PPG Reload Value
and Pulse Width................................. 231
Pulses
Controlling Pin Output of 8/16-bit PPG
Pulses ................................................ 233
R
Rate and Data Register
Rate and Data Register 0 (URD0)...................... 284
RCR
Reception Complete Register (RCR).................. 377
Read
Setting the Flash Memory to the
Read/Reset State ................................. 441
Ready Function
Ready Function................................................ 145
Receive and Transmit Error Counters
Receive and Transmit Error Counters
(RTEC) .............................................. 366
Receive Operation
Asynchronous (Start-Stop Synchronized) Mode
Receive Operation.............................. 317
Flag Set Timings for a Receive Operation
(in Mode 0,1,or 3) .............................. 294
Flag Set Timings for a Receive Operation
(in Mode 2) ........................................ 295
INDEX
Status Flag during Transmit and Receive
Operation ........................................... 297
Receive Overrun Register
Receive Overrun Register (ROVRR) ................. 379
Received Message
Storing Received Message ................................ 394
Reception
Completing Reception ...................................... 396
Procedure for Reception by Message Buffer
(x) ..................................................... 402
Processing for Reception of Data Frame and
Remote Frame ................................... 395
Reception Flowchart of the CAN Controller ....... 397
Reception Complete Register
Reception Complete Register (RCR).................. 377
Reception Interrupt Enable Register
Reception Interrupt Enable Register (RIER) ....... 380
Recommended Setting
Recommended Setting...................................... 134
Register
16-bit Timer Register (TMR)/16-bit Reload Register
(TMRLR) .......................................... 210
A/D Control Status Register (ADCS1) ............... 259
A/D Control Status Registers (ADCS0).............. 256
Acceptance Mask Select Register (AMSR)......... 381
Access to the Low-Power Consumption Mode
Control Register................................... 95
Analog Input Enable Register............................ 253
Analog Input Enable Register (ADER)............... 158
Automatic Ready Function Selection Register
(ARSR) ............................................. 137
Bit Timing Register (BTR) ............................... 367
Block Diagram of Pull-up Control Register
(PUCR).............................................. 157
Bus Control Signal Selection Register
(ECSR) .............................................. 140
CAN2 RX/TX Pin Switching Register
(CANSWR)........................................ 406
Condition Code Register (CCR) .......................... 32
Configuration of the Clock Selection Register
(CKSCR) ............................................ 75
Control Status Register (CSR) ........................... 360
Control Status Register of Output Compare ........ 190
Data Register (TCDT) ...................................... 182
Data Register x (x=0 to 15) (DTRx)................... 389
Delayed Interrupt Cause Issuance/Cancellation
Register (DIRR)................................. 239
DLC Register x (x=0 to 15) (DLCRx) ................ 388
DTP/Interrupt Enable Register (ENIR: Interrupt
Request Enable Register) .................... 244
DTP/Interrupt Flags (EIRR: External Interrupt
Request Register) ............................... 244
External Address Output Control Register
(HACR) ............................................. 139
Flash Memory Control Status Register
(FMCS).............................................. 426
ID Register x (x=0 to 15) (IDRx) .......................386
IDE Register (IDER).........................................370
Input Capture Control Status Register.................198
Input Capture Data Register...............................198
Input Data Register 0 (UIDR0) and Output Data
Register 0 (UODR0) ...........................283
Interrupt Control Register (ICR) ..........................58
Interrupt Level Mask Register (ILM)....................33
Last Event Indicator Register (LEIR)..................364
Low-Power Consumption Mode Control Register
(LPMCR).............................................93
Message Buffer Valid Register (BVALR) ...........369
Port data Register (PDR) ...................................153
Port Direction Register (DDR) ...........................155
Port Input Level Register (PILR)........................154
PPG0 Operation Mode Control Register
(PPGC0) .............................................222
PPG0/1 Clock Selection Register (PPG01)..........227
PPG1 Operation Mode Control Register
(PPGC1) .............................................224
Program Address Detection Control Status Register
(PACSR) ...........................................411
Pull-up Control Register (PUCR) .......................156
Rate and Data Register 0 (URD0) ......................284
Receive Overrun Register (ROVRR) ..................379
Reception Interrupt Enable Register (RIER)........380
Register Saving onto the Stack.............................50
Reload Register (PRLL/PRLH)..........................229
Remote Frame Receiving Wait Register
(RFWTR) ...........................................373
Remote Request Receiving Register
(RRTRR) ............................................378
Request Level Setting Register (ELVR: External
level register) .....................................245
ROM Mirroring Function Selection Register
(ROMM)............................................419
Serial Data Register (SDR) ................................335
Serial Input Data Register 1 (SIDR1)/Serial Output
Data Register 1 (SODR1) ....................309
Serial Mode Control Status Register (SMCS) ......331
Serial Mode Register 1 (SMR1) .........................305
Serial Status Register 1 (SSR1) ..........................310
Time-base Timer Control Register (TBTC) .........162
Timer Control Status Register ............................183
Timer Control Status Register (TMCSR) ............207
Transmission Cancel Register (TCANR) ............374
Transmission Complete Register (TCR)..............375
Transmission Interrupt Enable Register
(TIER)................................................376
Transmission Request Register (TREQR) ...........371
Transmission RTR Register (TRTRR) ................372
UART1 Prescaler Control Register
(U1CDCR)..........................................312
Watch Timer Control Register (WTC) ................174
Watchdog Timer Control Register (WDTC) ........168
Register Bank
Register Bank.....................................................36
555
INDEX
Register Bank Pointer
Register Bank Pointer (RP) ................................. 33
Reload Register
Reload Register (PRLL/PRLH) ......................... 229
Reload Timer
16-bit Reload Timer ......................................... 205
16-bit Reload Timer Register............................. 206
Block Diagram of 16-bit Reload Timer............... 204
Input Pin Functions of 16-bit Reload Timer
(in Internal Clock Mode) ..................... 212
Internal Clock Operation of 16-bit
Reload Timer ...................................... 211
Outline of 16-bit Reload Timer (with Event Count
Function) ........................................... 204
Output Pin Functions of 16-bit Reload Timer ...... 214
Underflow Operation of 16-bit Reload Timer...... 213
Reload Value
Relationship Between 8/16-bit PPG Reload Value and
Pulse Width ........................................ 231
Remote Frame
Processing for Reception of Data Frame and Remote
Frame................................................. 395
Remote Frame Receiving Wait Register
Remote Frame Receiving Wait Register
(RFWTR) ........................................... 373
Remote Request Receiving Register
Remote Request Receiving Register
(RRTRR)............................................ 378
Request Level Setting Register
Request Level Setting Register (ELVR: External
level register) ..................................... 245
Reset
Block Diagram of the External Reset Pin ............ 122
Causes of a Reset ............................................. 118
Correspondence between Reset Cause Bits and
Reset Causes...................................... 125
Notes about Reset Cause Bits ............................ 126
Oscillation Stabilization Wait and Reset State ..... 121
Overview of Reset Operation............................. 123
Reset Cause Bits .............................................. 125
Reset Causes and Oscillation Stabilization Wait
Intervals ............................................ 120
Setting the Flash Memory to the
Read/Reset State ................................. 441
Status of Pins during a Reset ............................. 127
Reset Cause
Correspondence between Reset Cause Bits and
Reset Causes...................................... 125
Notes about Reset Cause Bits ............................ 126
Reset Cause Bits
Correspondence between Reset Cause Bits and
Reset Causes...................................... 125
Notes about Reset Cause Bits ............................ 126
556
RFWTR
Remote Frame Receiving Wait Register
(RFWTR)........................................... 373
RIER
Reception Interrupt Enable Register (RIER) ....... 380
ROM Mirroring Function Selection Module
Block Diagram of ROM Mirroring Function Selection
Module .............................................. 418
ROM Mirroring Function Selection Register
ROM Mirroring Function Selection Register
(ROMM)........................................... 419
ROMM
ROM Mirroring Function Selection Register
(ROMM)........................................... 419
ROVRR
Receive Overrun Register (ROVRR) ................. 379
RP
Register Bank Pointer (RP) ................................. 33
RRTRR
Remote Request Receiving Register
(RRTRR) ........................................... 378
RTEC
Receive and Transmit Error Counters
(RTEC) .............................................. 366
S
Sample Application
UART1 Sample Application (System Configuration
in Mode 1)......................................... 325
SCDCR
Serial I/O Prescaler (SCDCR) ........................... 336
SCR
Serial Control Register 1 (SCR1)....................... 307
SDR
Serial Data Register (SDR) ............................... 335
Sector
Erasing Optional Data (Erasing Sectors) in the
Flash Memory ................................... 445
Erasing Sectors in the Flash Memory ................. 445
Restarting Erasing of Flash Memory Sectors ...... 448
Sector Configuration of the 1M-bit
Flash Memory .................................... 423
Suspending Erasing of Flash Memory
Sectors ............................................... 447
Sector Configuration
Sector Configuration of the 1M-bit
Flash Memory .................................... 423
Sector Erase Timer Flag
Sector Erase Timer Flag (DQ3) ......................... 436
Serial Clock Input Frequency
Oscillation Clock Frequency and Serial Clock Input
Frequency ......................................... 461
INDEX
Serial Control Register
Serial Control Register 1 (SCR1)....................... 307
Serial Data Register
Serial Data Register (SDR) ............................... 335
Serial I/O
Interrupt Function of the Serial I/O Interface ...... 344
Serial I/O Block Diagram ................................. 328
Serial I/O Operation ................................. 337, 339
Serial I/O Registers .......................................... 330
Serial I/O Prescaler
Serial I/O Prescaler (SCDCR) ........................... 336
Serial Input Data Register
Serial Input Data Register 1 (SIDR1)/Serial Output
Data Register 1 (SODR1).................... 309
Serial Mode Control Register
Serial Mode Control Register 0 (UMC0) ............ 279
Serial Mode Control Status Register
Serial Mode Control Status Register (SMCS) ..... 331
Serial Mode Register
Serial Mode Register 1 (SMR1)......................... 305
Serial Output Data Register
Serial Input Data Register 1 (SIDR1)/Serial Outpu
t Data Register 1 (SODR1)................... 309
Serial Programming Connection
Basic Configuration of MB90F443G Serial
Programming Connection .................... 458
Example of Serial Programming Connection (Power
Supplied from the Programmer)........... 464
Example of Serial Programming Connection
(User Power Supply Used) .................. 462
Serial Status Register
Serial Status Register 1 (SSR1) ......................... 310
Shift Clock
External Shift Clock Mode................................ 338
Internal Shift Clock Mode................................. 338
Shift Operation
Shift Operation Start/Stop Timing ..................... 341
SIDR
Serial Input Data Register 1 (SIDR1)/Serial Output
Data Register 1 (SODR1).................... 309
Single Chip Mode
Status of Each Pin in the Single Chip Mode........ 111
Single Mode
Single Mode .................................................... 264
Starting EI2OS in Single Mode.......................... 267
Sleep Mode
Release of Sleep Mode ....................................... 98
Switching to Sleep Mode .................................... 98
SLP
Priorities of the STP,SLP,and TMD Bits .............. 95
SMCS
Serial Mode Control Status Register (SMCS) ..... 331
SMR
Serial Mode Register 1 (SMR1) .........................305
SODR
Serial Input Data Register 1 (SIDR1)/Serial Output
Data Register 1 (SODR1) ....................309
Software Interrupt
Note on Software Interrupt ..................................55
Software Interrupt Operation ...............................54
Software Interrupts .............................................54
Structure of Software Interrupts ...........................54
Special Register
Special Registers ................................................27
SSP
User Stack Pointer (USP) and System Stack Pointer
(SSP) ...................................................31
SSR
Serial Status Register 1 (SSR1) ..........................310
Stack
Register Saving onto the Stack.............................50
Standby Mode
Notes on Accessing the Low-Power Consumption
Mode Control Register (LPMCR) to Enter
the Standby Mode ...............................116
Operation Status during Standby Mode.................97
Standby Mode ....................................................89
Switching to a Standby Mode and Interrupt.........114
Start-Stop Synchronized
Asynchronous (Start-Stop Synchronized) Mode
Data Transfer Format ...........................317
Asynchronous (Start-Stop Synchronized) Mode
Receive Operation ..............................317
Asynchronous (Start-Stop Synchronized) Mode
Transmit Operation .............................317
Status Change Diagram
Status Change Diagram .....................................109
Status Register
Status Register 0 (USR0)...................................281
Stop Mode
Release of Stop Mode .......................................107
Starting EI2OS in Stop Mode .............................271
Stop Mode .......................................................265
Switching to the Stop Mode...............................106
STP
Priorities of the STP,SLP,and TMD Bits ...............95
Structure
Structure of Instruction Map ..............................520
Sub Clock Mode
Main Clock Mode,PLL Clock Mode and Sub Clock
Mode ...................................................79
System Configuration
System Configuration Example of the Address
Match Detection Function....................414
UART1 Sample Application (System Configuration
in Mode 1) .........................................325
557
INDEX
System Stack Pointer
User Stack Pointer (USP) and System Stack Pointer
(SSP)................................................... 31
T
TBTC
Time-base Timer Control Register (TBTC)......... 162
TCANR
Transmission Cancel Register (TCANR) ............ 374
TCDT
Data Register (TCDT) ...................................... 182
TCR
Transmission Complete Register (TCR) ............. 375
TIER
Transmission Interrupt Enable Register
(TIER) ............................................... 376
Time-base Timer
Block Diagram of Time-base Timer ................... 161
Interval Interrupt Function of Time-base
Timer ................................................. 164
Time-base Timer .............................................. 164
Time-base Timer Registers................................ 160
Time-base Timer Control Register
Time-base Timer Control Register (TBTC)......... 162
Time-base Timer Mode
Release of Time-base Timer Mode..................... 101
Switching to the Time-base Timer Mode ............ 101
Timer Control Status Register
Timer Control Status Register............................ 183
Timer Control Status Register (TMCSR) ............ 207
Timing Limit Exceeded Flag
Timing Limit Exceeded Flag (DQ5) ................... 435
TMCSR
Timer Control Status Register (TMCSR) ............ 207
TMD
Priorities of the STP,SLP,and TMD Bits............... 95
TMR
16-bit Timer Register (TMR)/16-bit Reload Register
(TMRLR) .......................................... 210
TMRLR
16-bit Timer Register (TMR)/16-bit Reload Register
(TMRLR) .......................................... 210
Toggle Bit Flag
Toggle Bit Flag (DQ6)...................................... 434
Toggle Bit-2 Flag
Toggle Bit-2 Flag (DQ2)................................... 438
Transfer
Transfer Data Format........................................ 291
Transfer Format
Asynchronous (Start-Stop Synchronized) Mode
Data Transfer Format........................... 317
558
CLK Synchronous Mode Data Transfer
Format ............................................... 318
Transition
Clock Mode Transition ....................................... 79
Transmission
Canceling a Transmission Request from the CAN
Controller.......................................... 391
Completing Transmission of the
CAN Controller .................................. 392
Procedure for Transmission by Message Buffer
(x) ..................................................... 400
Starting Transmission of the
CAN Controller .................................. 391
Transmission Flowchart of the
CAN Controller .................................. 392
Transmission Cancel Register
Transmission Cancel Register (TCANR)............ 374
Transmission Complete Register
Transmission Complete Register (TCR) ............. 375
Transmission Interrupt Enable Register
Transmission Interrupt Enable Register
(TIER) ............................................... 376
Transmission Request Register
Transmission Request Register (TREQR)........... 371
Transmission RTR Register
Transmission RTR Register (TRTRR) ............... 372
Transmit
Status Flag during Transmit and Receive
Operation ........................................... 297
Transmit Operation
Asynchronous (Start-Stop Synchronized) Mode
Transmit Operation ............................ 317
Flag Set Timings for a Transmit Operation ......... 296
TREQR
Transmission Request Register (TREQR)........... 371
TRTRR
Transmission RTR Register (TRTRR) ............... 372
U
UART
Application Example of UART0 ....................... 298
Block Diagram of UART1 ................................ 303
Feature of UART0 ........................................... 276
Features of UART1 .......................................... 302
Precautions for UART1 Use.............................. 326
UART0 Block Diagram .................................... 277
UART0 Operation Modes ................................. 286
UART0 Registers............................................. 278
UART1 Clock Selection ................................... 314
UART1 Communication Flowchart ................... 325
UART1 Flags .................................................. 320
UART1 Interrupt Sources ................................. 320
UART1 Interrupts and Flag Set Timing.............. 321
UART1 Operating Modes ................................. 313
INDEX
UART1 Registers............................................. 304
UART1 Sample Application (System Configuration
in Mode 1)......................................... 325
UART1 Prescaler Control Register
UART1 Prescaler Control Register
(U1CDCR) ......................................... 312
UIDR
Input Data Register 0 (UIDR0) and Output Data
Register 0 (UODR0)........................... 283
UMC
Serial Mode Control Register 0 (UMC0) ............ 279
Undefined Instruction
Exception Due to Execution of an Undefined
Instruction ........................................... 68
Underflow Operation
Underflow Operation of 16-bit Reload Timer ..... 213
UODR
Input Data Register 0 (UIDR0) and Output Data
Register 0 (UODR0)........................... 283
URD
Rate and Data Register 0 (URD0) ...................... 284
User Power Supply
Example of Minimum Connection to the Flash
Microcontroller Programmer (User Power
Supply Used) ..................................... 466
Example of Serial Programming Connection (User
Power Supply Used) ........................... 462
User Stack Pointer
User Stack Pointer (USP) and System Stack Pointer
(SSP) .................................................. 31
USP
User Stack Pointer (USP) and System Stack Pointer
(SSP) .................................................. 31
USR
Status Register 0 (USR0) .................................. 281
W
Watch Mode
Release of Watch Mode ....................................104
Switching to the Watch Mode ............................103
Watch Timer
Block Diagram of Watch Timer .........................173
Interval Interrupt Function of Watch Timer .........176
Watch Timer ....................................................176
Watch Timer Register .......................................172
Watch Timer Control Register
Watch Timer Control Register (WTC) ................174
Watchdog Counter
Clearing the Watchdog Counter .........................170
Stopping the Watchdog Counter.........................170
Watchdog Timer
Activating the Watchdog Timer .........................170
Block Diagram of Watchdog Timer....................167
Resetting the Watchdog Timer ...........................170
Watchdog Timer Register..................................166
Watchdog Timer Control Register
Watchdog Timer Control Register (WDTC) ........168
WDTC
Watchdog Timer Control Register (WDTC) ........168
Write
Detailed Explanation of Flash Memory
Write/Erase .........................................440
Writing
Writing Data to the Flash Memory .....................442
Writing to the Flash Memory .............................442
Writing to/Erasing Flash Memory ......................422
WTC
Watch Timer Control Register (WTC) ................174
559
INDEX
560
CM44-10117-3E
FUJITSU MICROELECTRONICS • CONTROLLER MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90440G Series
HARDWARE MANUAL
July 2008 the third edition
Published
FUJITSU MICROELECTRONICS LIMITED
Edited
Business & Media Promotion Dept.