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The following document contains information on Cypress products.
CM44-10117-3ET2
Errata
This errata sheet is for MB90440G Series Hardware Manual Rev. 3 (CM44-10117-3E).
F2MC-16LX
16-BIT MICROCONTROLLER
MB90440G Series
HARDWARE MANUAL
2009.1.5
Date
2009/
1/5
Page
540
Item
APPENDIX
B
Description
■Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH) is changed.
・Error
Item "A"
Line of +A
"W2+d16,A"
・Correct
Item "A0"
Line of +A "@RW2+d16"
1/1
Corrections of Hardware Manual
MB90440G
hm90440g-cm44-10117-3e-corr-x1-06
© Fujitsu Microelectronics Europe GmbH
Addendum, MB90440G Hardware Manual (CM44-10117-3E)
This is the Addendum for the Hardware Manual CM44-10117-3E of the MB90440G
Microcontroller series. It describes all known discrepancies of the
MB90440G Microcontroller series Hardware Manual.
Ref. Number Date
Version Chapter/Page
No.
Description/Correction
(Text Link) dd.mm.yy
HWM90440001 03.07.02 1.00
21.15
HWM90440002 03.12.02 1.01
HWM90440003 15.01.03 1.02
4.1
HWM90440004 22.09.03 1.03
Chapter 14.3
HWM90440012 24.10.06 1.05
9.2, 9.3
HWM90440013 02.05.07 1.06
11.2, 11.3
hm90440g-cm44-10117-3e-corr-x1-06
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CAN, ‘Hit and Away’ description
added
Transition to standby mode,
Standby Cancel failure behavior
added
Clocks, machine clock description
corrected
PPG, wrong Bit setting for
timebase timer Mode
Notes on time base timer (TBOF
bit)
Notes on Watch timer (WTOF bit)
HWM90440001
TOP
Chapter 21 CAN
‘Hit and Away’ description
Affected Parts:
MB90V440G, MB90443G, MB90F443G
Caution for disabling Message Buffers by BVAL bits
1 Caution for
Reception
1.1 Behaviour
If there is a complete (no error until 6th bit of EOF) incoming message that
have passed the acceptance filter, then this message is stored into a
message buffer x (with x=0…15). If this store operation coincides with
reset operation of the corresponding BVAL bit (BVALx=0), the received
message will be stored into the message buffer 0 regardless of register
settings. Note that this coincidence has to happen within a specific CANclock cycle (see event 2 in figures). Hence, the probability is very low.
If transmission request of buffer 0 is set (TREQ0=1), the above-mentioned
behaviour will lead to the following transmission of a message. This
message consists of the received ID, DLC and Data together with original
IDE and RTR bits set of the message buffer 0.
However, if there are two or more message buffers with passing acceptance
filers for the incoming message and only buffer x is disabled, the message
will be stored into the 2nd prioritised message buffer.
If there are two or more message buffers with passing acceptance filers for
the incoming message and all those buffers are disabled, the message will
be stored into buffer 0.
1.2 Operation to avoid
When disabling message buffers by the BVAL register, it must be avoided
that the write operation to the BVAL register coincides with the store
operation of the received message in the CAN Controller.
The following diagram illustrates the timing to be avoided for the BVAL
write operation.
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Id-Arbitration
DLC
Data
dlc
data
CRC
ACK
ID
RTR
ID
SRR
IDE
SOF
idle
EOF
ITM
ID, DLC and DTR are copied to
buffer 0
no RX-flags are set
LEIR (buffer pointer) set to 0
determine one or more
buffers with Hit
16 cycles
64 cycles
3 4
Away
1 Hit
ACK
SYNC_SEG
DEL
idle
EOF6 EOF5 EOF4 EOF3 EOF2 EOF1 EOF0
TSEG1
TSEG2
sample point
RS=1? 0
2
disable all buffers x to y with hit exactly one
CAN-clock cycle after sample point (BVALx..y=0)
CAN-controller determines buffers, which can store the message, because
their acceptance filters had been passed.
Software disable all buffers with hit exactly one CAN-clock cycle after the
sample point of EOF1.
CAN-controller stores received ID, DLC and data in buffer 0 regardless of
the buffers determined in c.
CAN-Controller sets LEIR to point to buffer 0 but RX-flags (RCR, ROVR,
RRTRR) are not set.
2. Caution for
Transmission
2.1 Behaviour
When there is a pending transmission of buffer x and the CAN bus status is
in Intermission or in Bus Idle, the CAN-controller will load the message
from buffer x in order to send it. If this load operation coincides with
disabling the pending message buffer x by clearing the BVAL bit, this
results in transmission of a Standard message. This message consists of
RTR=0, IDE=0, DLC, 11 ID bits and Data stored in the message buffer 0.
Note that this coincidence has to happen with in a specific CAN-clock cycle.
Hence, the probability is very low. The position of that cycle depends also
on previous frame reception and occurrence of error frames.
2.2 Operation to avoid
When disabling message buffers by the BVAL register, it must be avoided
that the write operation to the BVAL register coincides with the
preparation for the next transmission in the CAN Controller.
The following diagram illustrates the timing to be avoided for the BVAL
write operation.
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DLC
Data
dlc
data
CRC
ACK
ID
RTR
ID
SRR
IDE
SOF
idle
...
EOF
ITM
idle
5
Id-Arbitration
TREQx=1
TREQx=1
6
EOF-SOF
BVALx=0
BVALx=0
Hit
7
8
Away
LEIR set to buffer 0
TCR remains unchanged
transmit standard data frame with
ID, DLC and data of buffer 0
Software requests transmission of buffer x by setting TREQx.
h
Software disables the buffer x by clearing BVALx.
CAN-controller transmits a standard data frame with ID, length code and
data of buffer 0.
After completion of frame only LEIR is updated for buffer 0. However, TCR
is not set (neither for buffer 0 nor for buffer x).
3. Correct Operation
3.1 Operation for re-configuring receive message buffers
Depending on CAN applications, it may be necessary to re-configure message
buffers after receiving messages through the already active CAN
communication.
While the CAN bus is active, it is necessary to follow one of the two
operations described below to re-configure message buffers by ID, AMS and
AMR0/1 register settings. "Active" means that read value of the HALT bit is
0 and the CAN Controller is ready to receive and transmit messages.
1.1.1 Use of HALT bit
Write 1 to the HALT bit and read it back for checking the result is 1. Then
change settings for the ID/AMS/AMR0/1 registers.
1.1.2 No use of Message Buffer 0
Do not use the message buffer 0. In other words, disable message buffer
(BVAL=0), prohibit receive interrupt (RIE=0) and do not request
transmission
(TREQ=0).
3.2 Operation for processing received message.
When reading a received message from a message buffer, consideration must
be given for possible over-write operation by next incoming messages.
Disabling receive operation by the BVAL bit must not be used for this
purpose.
Use the ROVR bit for checking, if over-writing has been performed. For
details, refer to description of ROVR in the hardware manual.
3.3 Cancellation of transmission request
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Do not use the BVAL bit for suppressing/cancellation of transmission
request. The TCANR bit is prepared for this purpose.
3.4 Composing transmission message
When composing a transmission message by writing to ID, data and other
registers, the message buffer should be disabled by the BVAL bit.
In this case, the BVAL bit should reset (BVAL=0) after checking if the TREQ
bit is 0 or after completion of the previous message transmission (TC=1).
4. Example of avoiding Hit-And-Away
Do not use message buffer 0. Keep it always disabled (BVAL0 = 0).
By not using buffer 0 the processing of wrongly received messages in buffer
0 is avoided. Even if data are received in this buffer, they have no
influence.
Set an unused 11-Bit identifier in buffer 0.
"Unused" means that the identifier has no meaning to any node in the
network. If an invalid standard data frame is sent according to the
condition described in "0
2. Caution for Transmission", that frame must not cause misoperation of
other nodes.
Use overrun test while processing a received message.
After temporarily saving received message, test for overrun (ROVRR). If
overrun occurred, read the buffer again, because the read data before
overrun could be inconsistent.
Wait for completion of transmission.
A buffer must not be disabled by clearing the BVAL-flag, as long as there
is a pending transmission. Easiest way to wait for transmission completion
is to use transmission interrupt but polling of TREQ is also possible.
TOP
HWM90440002
Transition to standby mode
The definition of Standby Cancel Failure is that the CPU will execute wrong
instructions when an interrupt is executed during transition to Standby
mode *0 at a certain time. Fujitsu can reproduce this phenomenon Fujitsu
internally and has found the cause.
*0:Definition of Standby mode
Main sleep mode, PLL sleep mode, Sub-sleep mode
Time base timer mode, Watch mode, Main watch mode
Main stop mode, PLL stop mode, Sub-stop mode
*Main watch mode is only for MB90370 series.
In the following cases, no problem occurs:
-Standby mode is not used
-Standby mode is released only by external reset
For further information refer to ‘F2MC16-LX Standby Cancel Failure’
document.
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HWM90440003
TOP
Chapter 4.1 Clocks
Machine Clock, wrong NOTE text.
See correction below:
Machine Clock: …
NOTE: When the operating voltage is 5 V, the oscillation clock can
oscillate at 3 MHz to 16 MHz. The maximum operating frequency of the CPU or
resources is 16 MHz. If a multiplication rate that exceeds the maximum
operating frequency is set, the device does not operate normally. If the
oscillation clock is 16 MHz, the multiplication rate of PLL clock can only
be set to x1. The PLL oscillator oscillates in the range of 3 MHz to 16 MHz,
which varies depending on the operating voltage and multiplication rate.
HWM90440004
TOP
Chapter 14 8/16-BIT PPG
Chapter 14.3.3 PPG0,1 Clock Selection Register (PPG0/1)
Wrong Bit Settings for timebase timer mode.
Correction:
PCS2
1
PCS1
1
PCS0
1
Operation mode
Clock input from the timebase timer
PCM2
1
PCM1
1
PCM0
1
Operation mode
Clock input from the timebase timer
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HWM90440012
TOP
Notes on time base timer (TBOF bit)
===================================
Chapter 9.2, table 9.2-1 bit 11 (TBOF)
Note:
To clear the TBOF bit, disable interrupts (TBIE = 0) or mask interrupts
using the interrupt mask register (ILM) in the processor status.
Chapter 9.3
Note:
To clear the overflow interrupt request flag bit (TBTC: TBOF), disable a
timebase timer interrupt at interrupt processing (TBTC: TBIE = 0) or mask a
timebase timer interrupt by using the ILM bit in the processor status (PS)
to write "0" to the TBOF bit. Do not enable timebase timer interrupt (TBTC:
TBIE = 1) and clear interrupt flag (TBTC: TBOF = 0) at the same time!
(HWe, KDi)
HWM90440013
TOP
Notes on Watch timer (WTOF bit)
===============================
Chapter 11.2, [Bit 4] WTOF
Note:
To clear the WTOF bit, disable interrupts (WTIE = 0) or mask interrupts
using the interrupt mask register (ILM) in the processor status.
Chapter 11.3 Watch Timer Operation
Note:
To clear the overflow interrupt request flag bit (WTC: WTOF), disable a
watch timer interrupt at interrupt processing (WTC: WIE = 0) or mask watch
timer interrupt by using the ILM bit in the processor status (PS) to write
"0" to the WTOF bit. Do not enable watch timer interrupt (WTC: WIE = 1) and
clear interrupt flag (WTC: WTOF = 0) at the same time!
(HWe, SJa)
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