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FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
CM44-10118-5E
F2MC-16LX
16-BIT MICROCONTROLLER
MB90385 Series
HARDWARE MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90385 Series
HARDWARE MANUAL
The information for microcontroller supports is shown in the following homepage.
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page
"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU MICROELECTRONICS LIMITED
PREFACE
■ Manual Objectives and Readers
Thank you very much for your continued patronage of Fujitsu semiconductor products.
The MB90385 series is one of the general-purpose products in the F2MC-16LX family of 16-bit single-chip
microcontrollers that is developed by using an application-specific integrated circuit (ASIC).
This manual covers the functions and operations of the MB90385 series for engineers to develop LSIs using
this series.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ Trademarks
The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
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•
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you
develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use
of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of
the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of
the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability
for any infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and
manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e.,
nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support
system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and
artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages
arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©2006-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
i
HOW TO READ THIS MANUAL
■ Page Structure
Each section content can be read easily because it is mentioned within one page or double spread.
A summary under the title in each section outlines the section contents.
The top-level title at the top of a double spread indicates where you are reading without returning to the table
of contents or the chapter title page.
■ How to Find Information
To find information in each section, use the following index in addition to general table of contents and
index.
● Register index
This index helps you find the page containing the explanation of the corresponding register from a register
name or related resource name. You can also check the mapped addresses on memory and reset values.
● Pin function index
This index helps you find the page containing the explanation or block diagram of the corresponding pin
from a pin number, pin name, or related resource name. You can also check the circuit types.
● Interrupt vector index
This index helps you find the page containing the explanation of a corresponding interrupt from a name of
resource generating the interrupt or an interrupt number. You can also check the names and addresses of
interrupt control registers (ICRs), and the interrupt vector addresses.
ii
■ Representation of Register Name and Pin Name
● Representation of register name and bit name
By writing 1 to the sleep bit of the standby control register (STBC: SLP), .......
Bit name
Register name
Abbreviation of bit name
Abbreviation of register name
Disable the timebase timer for output of an interrupt request (TBTC: TBIE = 0).
Set data
Abbreviation of bit name
Abbreviation of register name
If an interrupt is enabled (CCR: I = 1), an interrupt can be accepted.
Current state
Abbreviation of bit name
Abbreviation of register name
● Representation of dual-purpose pin
P25/SCK pin
Some pins are dual-purpose pins which functions can be switched by the setting of program. A slash (/)
separates and represents the names corresponding to the functions of the dual-purpose pins.
■ Register Representation
The F2MC-16LX family is a CPU with a 16-bit bus width. The bit position of each control register and data
register is given in 16 bits.
In 16-bit registers, bits 15 to 8 are allocated to odd addresses and bits 7 to 0 even addresses.
Even in 8-bit registers, the position of bits allocated to odd addresses is given in bits 15 to 8.
The F2MC-16LX family enables access to 8-bit data in order to increase the efficiency of programs. So, if
odd-address registers are accessed in 8 bits, bits 7 to 0 in data correspond to bits 15 to 8 in the manual
representation.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
CHAPTER 2
2.1
HANDLING DEVICES ................................................................................ 17
Precautions when Handling Devices ................................................................................................ 18
CHAPTER 3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
OVERVIEW ................................................................................................... 1
Features of MB90385 Series .............................................................................................................. 2
Product Lineup for MB90385 Series ................................................................................................... 5
Block Diagram of MB90385 Series ..................................................................................................... 8
Pin Assignment ................................................................................................................................... 9
Package Dimension .......................................................................................................................... 10
Pin Description .................................................................................................................................. 11
I/O Circuit .......................................................................................................................................... 14
CPU ............................................................................................................ 21
Memory Space ..................................................................................................................................
Mapping of and Access to Memory Space ..................................................................................
Memory Map ................................................................................................................................
Addressing ...................................................................................................................................
Linear Addressing ........................................................................................................................
Bank Addressing .........................................................................................................................
Allocation of Multi-byte Data on Memory .....................................................................................
Dedicated Registers .........................................................................................................................
Dedicated Registers and General-purpose Register ...................................................................
Accumulator (A) ...........................................................................................................................
Stack Pointer (USP, SSP) ...........................................................................................................
Processor Status (PS) .................................................................................................................
Program Counter (PC) .................................................................................................................
Direct Page Register (DPR) ........................................................................................................
Bank Register (PCB, DTB, USB, SSB, and ADB) .......................................................................
General-purpose Register ................................................................................................................
Prefix Codes .....................................................................................................................................
Bank Select Prefix (PCB, DTB, ADB, and SPB) ..........................................................................
Common Register Bank Prefix (CMR) .........................................................................................
Flag Change Inhibit Prefix (NCC) ................................................................................................
Restrictions on Prefix Code .........................................................................................................
Interrupt ............................................................................................................................................
Interrupt Factor and Interrupt Vector ...........................................................................................
Interrupt Control Registers and Resources .................................................................................
Interrupt Control Register (ICR00 to ICR15) ...............................................................................
Function of Interrupt Control Register .........................................................................................
Hardware Interrupt .......................................................................................................................
Operation of Hardware Interrupt ..................................................................................................
Procedure for Use of Hardware Interrupt ....................................................................................
Multiple Interrupts ........................................................................................................................
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22
24
26
27
28
29
31
33
35
36
39
42
47
48
49
50
52
53
55
56
57
59
61
64
66
68
71
74
76
77
3.5.9
Software Interrupt ........................................................................................................................ 79
3.5.10 Interrupt by EI2OS ....................................................................................................................... 80
3.5.11 EI2OS Descriptor (ISD) ................................................................................................................ 82
3.5.12 Each Register of EI2OS Descriptor (ISD) .................................................................................... 84
3.5.13 Operation of EI2OS ...................................................................................................................... 87
3.5.14 Procedure for Use of EI2OS ........................................................................................................ 88
3.5.15 EI2OS Processing Time ............................................................................................................... 89
3.5.16 Exception Processing Interrupt .................................................................................................... 91
3.5.17 Time Required to Start Interrupt Processing ............................................................................... 92
3.5.18 Stack Operation for Interrupt Processing .................................................................................... 94
3.5.19 Program Example of Interrupt Processing ................................................................................... 95
3.6
Reset ................................................................................................................................................ 99
3.6.1
Reset Factors and Oscillation Stabilization Wait Time .............................................................. 101
3.6.2
External Reset Pin ..................................................................................................................... 103
3.6.3
Reset Operation ........................................................................................................................ 104
3.6.4
Reset Factor Bit ......................................................................................................................... 106
3.6.5
State of Each Pin at Reset ........................................................................................................ 108
3.7
Clocks ............................................................................................................................................. 109
3.7.1
Block Diagram of Clock Generation Section ............................................................................. 112
3.7.2
Register in Clock Generation Section ........................................................................................ 114
3.7.3
Clock Select Register (CKSCR) ................................................................................................ 115
3.7.4
Clock Mode ................................................................................................................................ 118
3.7.5
Oscillation Stabilization Wait Time ............................................................................................ 122
3.7.6
Connection of Oscillator and External Clock ............................................................................. 123
3.8
Low-power Consumption Mode ...................................................................................................... 124
3.8.1
Block Diagram of Low-power Consumption Circuit ................................................................... 127
3.8.2
Registers for Setting Low-power Consumption Modes ............................................................. 129
3.8.3
Low-power Consumption Mode Control Register (LPMCR) ...................................................... 130
3.8.4
CPU Intermittent Operation Mode ............................................................................................. 133
3.8.5
Standby Mode ........................................................................................................................... 134
3.8.6
State Transition in Standby Mode ............................................................................................. 144
3.8.7
Pin State in Standby Mode, at Reset ......................................................................................... 145
3.8.8
Precautions when Using Low-power Consumption Mode ......................................................... 146
3.9
CPU Mode ...................................................................................................................................... 149
3.9.1
Mode Pins (MD2 to MD0) .......................................................................................................... 150
3.9.2
Mode Data ................................................................................................................................. 152
3.9.3
Memory Access Mode ............................................................................................................... 154
3.9.4
Selection of Memory Access Mode ........................................................................................... 155
CHAPTER 4
4.1
4.2
4.3
4.3.1
4.3.2
4.4
4.4.1
I/O PORT .................................................................................................. 157
Overview of I/O Port .......................................................................................................................
Registers of I/O Port .......................................................................................................................
Port 1 ..............................................................................................................................................
Registers for Port 1 (PDR1, DDR1) ...........................................................................................
Operation of Port 1 ....................................................................................................................
Port 2 ..............................................................................................................................................
Registers for Port 2 (PDR2, DDR2) ...........................................................................................
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158
160
161
163
164
166
168
4.4.2
Operation of Port 2 .................................................................................................................... 169
4.5
Port 3 .............................................................................................................................................. 171
4.5.1
Registers for Port 3 (PDR3, DDR3) ........................................................................................... 173
4.5.2
Operation of Port 3 .................................................................................................................... 174
4.6
Port 4 .............................................................................................................................................. 176
4.6.1
Registers for Port 4 (PDR4, DDR4) ........................................................................................... 178
4.6.2
Operation of Port 4 .................................................................................................................... 179
4.7
Port 5 .............................................................................................................................................. 181
4.7.1
Registers for Port 5 (PDR5, DDR5, ADER) ............................................................................... 183
4.7.2
Operation of Port 5 .................................................................................................................... 185
CHAPTER 5
5.1
5.2
5.3
5.3.1
5.4
5.5
5.6
5.7
CHAPTER 6
6.1
6.2
6.3
6.3.1
6.4
6.5
6.6
188
190
192
193
195
196
200
201
WATCHDOG TIMER ................................................................................ 203
Overview of Watchdog Timer .........................................................................................................
Configuration of Watchdog Timer ...................................................................................................
Watchdog Timer Registers .............................................................................................................
Watchdog Timer Control Register (WDTC) ...............................................................................
Explanation of Operation of Watchdog Timer .................................................................................
Precautions when Using Watchdog Timer ......................................................................................
Program Examples of Watchdog Timer ..........................................................................................
CHAPTER 7
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.4
7.5
7.6
7.7
7.8
TIMEBASE TIMER ................................................................................... 187
Overview of Timebase Timer ..........................................................................................................
Block Diagram of Timebase Timer .................................................................................................
Configuration of Timebase Timer ...................................................................................................
Timebase Timer Control Register (TBTC) .................................................................................
Timebase Timer Interrupt ...............................................................................................................
Explanation of Operation of Timebase Timer .................................................................................
Precautions when Using Timebase Timer ......................................................................................
Program Example of Timebase Timer ............................................................................................
204
205
207
208
210
213
214
16-BIT INPUT/OUTPUT TIMER ............................................................... 215
Overview of 16-bit Input/Output Timer ............................................................................................
Block Diagram of 16-bit Input/Output Timer ...................................................................................
Block Diagram of 16-bit Free-run Timer ....................................................................................
Block Diagram of Input Capture ................................................................................................
Configuration of 16-bit Input/Output Timer .....................................................................................
Timer Counter Control Status Register (TCCS) ........................................................................
Timer Counter Data Register (TCDT) ........................................................................................
Input Capture Control Status Registers (ICS01 and ICS23) .....................................................
Input Capture Data Registers 0 to 3 (IPCP0 to IPCP3) .............................................................
Interrupts of 16-bit Input/Output Timer ............................................................................................
Explanation of Operation of 16-bit Free-run Timer .........................................................................
Explanation of Operation of Input Capture .....................................................................................
Precautions when Using 16-bit Input/Output Timer ........................................................................
Program Example of 16-bit Input/Output Timer ..............................................................................
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216
217
218
220
222
225
227
228
231
232
233
235
238
239
CHAPTER 8
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.4
8.5
8.5.1
8.5.2
8.6
8.7
Overview of 16-bit Reload Timer ....................................................................................................
Block Diagram of 16-bit Reload Timer ............................................................................................
Configuration of 16-bit Reload Timer ..............................................................................................
Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H) ...........................................
Timer Control Status Registers (Low) (TMCSR0: L, TMCSR1: L) .............................................
16-bit Timer Registers (TMR0, TMR1) ......................................................................................
16-bit Reload Registers (TMRLR0, TMRLR1) ...........................................................................
Interrupts of 16-bit Reload Timer ....................................................................................................
Explanation of Operation of 16-bit Reload Timer ............................................................................
Operation in Internal Clock Mode ..............................................................................................
Operation in Event Count Mode ................................................................................................
Precautions when Using 16-bit Reload Timer ................................................................................
Program Example of 16-bit Reload Timer ......................................................................................
CHAPTER 9
9.1
9.2
9.3
9.3.1
9.4
9.5
9.6
16-BIT RELOAD TIMER ........................................................................... 241
242
244
246
249
251
253
254
255
256
258
263
266
267
WATCH TIMER ........................................................................................ 271
Overview of Watch Timer ...............................................................................................................
Block Diagram of Watch Timer .......................................................................................................
Configuration of Watch Timer .........................................................................................................
Watch Timer Control Register (WTC) ........................................................................................
Watch Timer Interrupt .....................................................................................................................
Explanation of Operation of Watch Timer .......................................................................................
Program Example of Watch Timer ..................................................................................................
272
274
276
277
279
280
282
CHAPTER 10 8-/16-BIT PPG TIMER .............................................................................. 283
10.1 Overview of 8-/16-bit PPG Timer ....................................................................................................
10.2 Block Diagram of 8-/16-bit PPG Timer ...........................................................................................
10.2.1 Block Diagram for 8-/16-bit PPG Timer 0 ..................................................................................
10.2.2 Block Diagram of 8-/16-bit PPG Timer 1 ...................................................................................
10.3 Configuration of 8-/16-bit PPG Timer .............................................................................................
10.3.1 PPG0 Operation Mode Control Register (PPGC0) ....................................................................
10.3.2 PPG1 Operation Mode Control Register (PPGC1) ....................................................................
10.3.3 PPG0/1 Count Clock Select Register (PPG01) .........................................................................
10.3.4 PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1) ..........................................................
10.4 Interrupts of 8-/16-bit PPG Timer ....................................................................................................
10.5 Explanation of Operation of 8-/16-bit PPG Timer ...........................................................................
10.5.1 8-bit PPG Output 2-channel Independent Operation Mode .......................................................
10.5.2 16-bit PPG Output Operation Mode ..........................................................................................
10.5.3 8+8-bit PPG Output Operation Mode ........................................................................................
10.6 Precautions when Using 8-/16-bit PPG Timer ................................................................................
284
287
288
290
292
294
296
298
300
301
303
304
306
309
312
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE .................................. 315
11.1 Overview of Delayed Interrupt Generation Module .........................................................................
11.2 Block Diagram of Delayed Interrupt Generation Module ................................................................
11.3 Configuration of Delayed Interrupt Generation Module ..................................................................
11.3.1 Delayed Interrupt Request Generate/Cancel Register (DIRR) ..................................................
11.4 Explanation of Operation of Delayed Interrupt Generation Module ................................................
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316
317
318
319
320
11.5
11.6
Precautions when Using Delayed Interrupt Generation Module ..................................................... 321
Program Example of Delayed Interrupt Generation Module ........................................................... 322
CHAPTER 12 DTP/EXTERNAL INTERRUPT ................................................................. 323
12.1 Overview of DTP/External Interrupt ................................................................................................
12.2 Block Diagram of DTP/External Interrupt ........................................................................................
12.3 Configuration of DTP/External Interrupt ..........................................................................................
12.3.1 DTP/External Interrupt Factor Register (EIRR) .........................................................................
12.3.2 DTP/External Interrupt Enable Register (ENIR) ........................................................................
12.3.3 Detection Level Setting Register (ELVR) (High) ........................................................................
12.3.4 Detection Level Setting Register (ELVR) (Low) ........................................................................
12.4 Explanation of Operation of DTP/External Interrupt .......................................................................
12.4.1 External Interrupt Function ........................................................................................................
12.4.2 DTP Function .............................................................................................................................
12.5 Precautions when Using DTP/External Interrupt ............................................................................
12.6 Program Example of DTP/External Interrupt Circuit .......................................................................
324
325
327
328
329
331
332
333
336
337
338
340
CHAPTER 13 8-/10-BIT A/D CONVERTER .................................................................... 343
13.1 Overview of 8-/10-bit A/D Converter ...............................................................................................
13.2 Block Diagram of 8-/10-bit A/D Converter ......................................................................................
13.3 Configuration of 8-/10-bit A/D Converter ........................................................................................
13.3.1 A/D Control Status Register (High) (ADCS: H) ..........................................................................
13.3.2 A/D Control Status Register (Low) (ADCS: L) ...........................................................................
13.3.3 A/D Data Register (High) (ADCR: H) .........................................................................................
13.3.4 A/D Data Register (Low) (ADCR: L) ..........................................................................................
13.3.5 Analog Input Enable Register (ADER) ......................................................................................
13.4 Interrupt of 8-/10-bit A/D Converter ................................................................................................
13.5 Explanation of Operation of 8-/10-bit A/D Converter ......................................................................
13.5.1 Single Conversion Mode ...........................................................................................................
13.5.2 Continuous Conversion Mode ...................................................................................................
13.5.3 Pause-conversion Mode ............................................................................................................
13.5.4 Conversion Using EI2OS Function ............................................................................................
13.5.5 A/D-converted Data Protection Function ...................................................................................
13.6 Precautions when Using 8-/10-bit A/D Converter ...........................................................................
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345
348
350
352
355
357
358
360
361
362
364
366
368
369
371
CHAPTER 14 UART1 ...................................................................................................... 373
14.1 Overview of UART1 ........................................................................................................................
14.2 Block Diagram of UART1 ................................................................................................................
14.3 Configuration of UART1 ..................................................................................................................
14.3.1 Serial Control Register 1 (SCR1) ..............................................................................................
14.3.2 Serial Mode Register 1 (SMR1) .................................................................................................
14.3.3 Serial Status Register 1 (SSR1) ................................................................................................
14.3.4 Serial Input Data Register 1 (SIDR1) and Serial Output Data Register 1 (SODR1) ..................
14.3.5 Communication Prescaler Control Register 1 (CDCR1) ............................................................
14.4 Interrupt of UART1 ..........................................................................................................................
14.4.1 Generation of Receive Interrupt and Timing of Flag Set ...........................................................
14.4.2 Generation of Transmit Interrupt and Timing of Flag Set ..........................................................
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374
376
379
381
383
385
387
389
391
393
395
14.5 Baud Rate of UART1 ......................................................................................................................
14.5.1 Baud Rate by Dedicated Baud Rate Generator ........................................................................
14.5.2 Baud Rate by Internal Timer (16-bit Reload Timer) ...................................................................
14.5.3 Baud Rate by External Clock .....................................................................................................
14.6 Explanation of Operation of UART1 ...............................................................................................
14.6.1 Operation in Asynchronous Mode (Operation Mode 0 or 1) ......................................................
14.6.2 Operation in Clock Synchronous Mode (Operation Mode 2) .....................................................
14.6.3 Bidirectional Communication Function (Operation Modes 0 and 2) ..........................................
14.6.4 Master/Slave Type Communication Function (Multiprocessor Mode) .......................................
14.7 Precautions when Using UART1 ....................................................................................................
14.8 Program Example for UART1 .........................................................................................................
396
398
401
403
404
406
410
413
415
418
419
CHAPTER 15 CAN CONTROLLER ................................................................................ 421
15.1 Overview of CAN Controller ............................................................................................................
15.2 Block Diagram of CAN Controller ...................................................................................................
15.3 Configuration of CAN Controller .....................................................................................................
15.3.1 Control Status Register (High) (CSR: H) ...................................................................................
15.3.2 Control Status Register (Low) (CSR: L) ....................................................................................
15.3.3 Last Event Indicate Register (LEIR) ..........................................................................................
15.3.4 Receive/Transmit Error Counter (RTEC) ...................................................................................
15.3.5 Bit Timing Register (BTR) ..........................................................................................................
15.3.6 Message Buffer Valid Register (BVALR) ...................................................................................
15.3.7 IDE Register (IDER) ..................................................................................................................
15.3.8 Transmission Request Register (TREQR) ................................................................................
15.3.9 Transmission RTR Register (TRTRR) .......................................................................................
15.3.10 Remote Frame Receiving Wait Register (RFWTR) ...................................................................
15.3.11 Transmission Cancel Register (TCANR) ...................................................................................
15.3.12 Transmission Complete Register (TCR) ....................................................................................
15.3.13 Transmission Complete Interrupt Enable Register (TIER) ........................................................
15.3.14 Reception Complete Register (RCR) ........................................................................................
15.3.15 Reception RTR Register (RRTRR) ............................................................................................
15.3.16 Reception Overrun Register (ROVRR) ......................................................................................
15.3.17 Reception Complete Interrupt Enable Register (RIER) .............................................................
15.3.18 Acceptance Mask Select Register (AMSR) ...............................................................................
15.3.19 Acceptance Mask Register (AMR) ............................................................................................
15.3.20 Message Buffers ........................................................................................................................
15.3.21 ID Register (IDR7 to IDR0) ........................................................................................................
15.3.22 DLC Register (DLCR) ................................................................................................................
15.3.23 Data Register (DTR) ..................................................................................................................
15.4 Interrupts of CAN Controller ...........................................................................................................
15.5 Explanation of Operation of CAN Controller ...................................................................................
15.5.1 Transmission .............................................................................................................................
15.5.2 Reception ..................................................................................................................................
15.5.3 Procedures for Transmitting and Receiving ..............................................................................
15.5.4 Setting Multiple Message Receiving ..........................................................................................
15.6 Precautions when Using CAN Controller ........................................................................................
15.7 Program Example of CAN Controller ..............................................................................................
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423
427
431
433
436
438
440
444
446
448
450
452
454
456
458
460
462
464
466
468
470
472
473
476
477
478
480
481
484
488
495
497
499
CHAPTER 16 8/16 ADDRESS MATCH DETECTION FUNCTION ................................. 501
16.1 Overview of Address Match Detection Function .............................................................................
16.2 Block Diagram of Address Match Detection Function ....................................................................
16.3 Configuration of Address Match Detection Function ......................................................................
16.3.1 Address Detection Control Register (PACSR) ..........................................................................
16.3.2 Detect Address Setting Registers (PADR0 and PADR1) ..........................................................
16.4 Explanation of Operation of Address Match Detection Function ....................................................
16.4.1 Example of using Address Match Detection Function ...............................................................
16.5 Program Example of Address Match Detection Function ...............................................................
502
503
504
505
507
509
510
515
CHAPTER 17 ROM MIRRORING FUNCTION SELECT MODULE ................................ 517
17.1
17.2
Overview of ROM Mirroring Function Select Module ...................................................................... 518
ROM Mirroring Function Select Register (ROMM) ......................................................................... 520
CHAPTER 18 512 KBIT FLASH MEMORY .................................................................... 521
18.1 Overview of 512 Kbit Flash Memory ...............................................................................................
18.2 Registers and Sector Configuration of Flash Memory ....................................................................
18.3 Flash Memory Control Status Register (FMCS) .............................................................................
18.4 How to Start Automatic Algorithm of Flash Memory .......................................................................
18.5 Check the Execution State of Automatic Algorithm ........................................................................
18.5.1 Data Polling Flag (DQ7) ............................................................................................................
18.5.2 Toggle Bit Flag (DQ6) ................................................................................................................
18.5.3 Timing Limit Over Flag (DQ5) ....................................................................................................
18.5.4 Sector Erase Timer Flag (DQ3) .................................................................................................
18.5.5 Toggle Bit 2 Flag (DQ2) ............................................................................................................
18.6 Details of Programming/Erasing Flash Memory .............................................................................
18.6.1 Read/Reset State in Flash Memory ...........................................................................................
18.6.2 Data Programming to Flash Memory .........................................................................................
18.6.3 Data Erase from Flash Memory (Chip Erase) ...........................................................................
18.6.4 Erasing Any Data in Flash Memory (Sector Erasing) ................................................................
18.6.5 Sector Erase Suspension in Flash Memory ..............................................................................
18.6.6 Sector Erase Resumption in Flash Memory ..............................................................................
18.7 Program Example of 512 Kbit Flash Memory .................................................................................
522
523
524
527
529
531
533
534
535
536
538
539
540
542
543
545
546
547
CHAPTER 19 FLASH SERIAL PROGRAMMING CONNECTION ................................. 551
19.1
19.2
19.3
19.4
19.5
Basic Configuration of Serial Programming Connection for F2MC-16LX MB90F387/S .................
Connection Example in Single-chip Mode (User Power Supply) ....................................................
Connection Example in Single-chip Mode (Writer Power Supply) ..................................................
Example of Minimum Connection to Flash Microcontroller Programmer (User Power Supply)
.........................................................................................................................................................
Example of Minimum Connection to Flash Microcontroller Programmer (Writer Power Supply)
.........................................................................................................................................................
552
555
557
559
561
APPENDIX ......................................................................................................................... 563
APPENDIX A Instructions ........................................................................................................................... 564
A.1 Instruction Types ............................................................................................................................ 565
A.2 Addressing ..................................................................................................................................... 566
xi
A.3 Direct Addressing ...........................................................................................................................
A.4 Indirect Addressing ........................................................................................................................
A.5 Execution Cycle Count ...................................................................................................................
A.6 Effective address field ....................................................................................................................
A.7 How to Read the Instruction List ....................................................................................................
A.8 F2MC-16LX Instruction List ............................................................................................................
A.9 Instruction Map ...............................................................................................................................
APPENDIX B Register Index ......................................................................................................................
APPENDIX C Pin Function Index ...............................................................................................................
APPENDIX D Interrupt Vector Index ..........................................................................................................
568
574
582
585
586
589
603
625
634
636
INDEX ................................................................................................................................. 639
xii
Main changes in this edition
Page
564 to 624
Changes (For details, refer to main body.)
Changed the entire part of "APPENDIX A Instructions"
The vertical lines marked in the left side of the page show the changes.
xiii
xiv
CHAPTER 1
OVERVIEW
This chapter describes the features and basic
specifications of the MB90385 series.
1.1 Features of MB90385 Series
1.2 Product Lineup for MB90385 Series
1.3 Block Diagram of MB90385 Series
1.4 Pin Assignment
1.5 Package Dimension
1.6 Pin Description
1.7 I/O Circuit
1
CHAPTER 1 OVERVIEW
1.1
Features of MB90385 Series
The MB90385 series is a general-purpose, high-performance 16-bit microcontroller
designed for control of processors such as consumer products requiring high-speed
real-time processing. This series has a full CAN interface.
The instruction system is based on the architecture of the F2MC family and provides
additional high-level language instructions, extended addressing modes, enhanced
multiply/divide instructions, and enriched bit processing instructions. A 32-bit
accumulator enables long-word data (32 bits) processing.
■ Features of MB90385 Series
● Clock
• Built-in PLL clock multiplying circuit
• Machine clock (PLL clock) selectable from 1/2 frequency of oscillation clock or 1 to 4-multiplied
oscillation clock (4 MHz to 16 MHz when oscillation clock is 4 MHz)
• Subclock operation (8.192 kHz) (MB90387, MB90F387)
• Minimum instruction execution time: 62.5 ns (4-MHz oscillation clock, 4-multiplied PLL clock)
● 16-MB CPU memory space
• Internal 24-bit addressing
● Instruction system optimized for controllers
• Various data types (bit, byte, word, long word)
• 23 types of addressing modes
• Enhanced signed instructions of multiplication/division and RETI instruction function
• High-accuracy operations enhanced by 32-bit accumulator
● Instruction system for high-level language (C language)/multitask
• System stack pointer
• Enhanced pointer indirect instructions
• Barrel shift instructions
● Higher execution speed
• 4-byte instruction queue
● Powerful interrupt function
• Powerful interrupt function with 8 levels and 34 factors
2
CHAPTER 1 OVERVIEW
● CPU-independent automatic data transfer function
• Extended intelligent I/O service (EI2OS): Maximum 16 channels
● Lower-power consumption (standby) modes
• Sleep mode (stops CPU clock)
• Timebase timer mode (operates only oscillation clock and subclock, timebase timer and watch timer)
• Watch mode (operates only subclock and watch timer)
• Stop mode (stops oscillation clock and subclock)
• CPU Intermittent operation mode
● Process
• CMOS Technology
● I/O ports
• General-purpose I/O ports (CMOS output): 34 ports (for M90387 or M90F387) (included 4 output ports
for high current)
Note: 36 ports (for MB90387S or MB90F387S) on condition of unusing subclock.
● Timers
• Timebase timer, watch timer, watchdog timer: 1 channel
• 8/16-bit PPG timer: 8 bits × 4 channels or 16 bits × 2 channels
• 16-bit reload timer: 2 channels
• 16-bit I/O timer
- 16-bit free-run timer: 1 channel
- 16-bit input capture (ICU): 4 channels
By detecting the edge of the pin input, the count value of the 16-bit free-run timer is latched to generate an
interrupt request.
● CAN Controller: 1 channel
• Conforms to CAN Specification Ver. 2.0A and Ver. 2.0B.
• Built-in 8 message buffers
• Transfer rate: 10 kbps to 1 Mbps (at 16-MHz machine clock frequency)
• CAN wake-up
● UART1 (SCI): 1 channel
• Full-duplex double buffer
• Clock asynchronous or clock synchronous serial transfer
● DTP/external interrupt: 4 channels
• External input to start EI2OS and external interrupt generation module
3
CHAPTER 1 OVERVIEW
● Delayed interrupt generation module
• Generates interrupt request for task switching
● 8-/10-bit A/D converter: 8 channels
• 8-bit and 10-bit resolutions
• Start by external trigger input
• Conversion time: 6.125μs (including sampling time at 16-MHz machine clock frequency)
● Program patch function
• Detects address match for two address pointers
4
CHAPTER 1 OVERVIEW
1.2
Product Lineup for MB90385 Series
The MB90385 series is available in three types. This section provides the product
lineup, CPU, and resources.
■ Product Lineup for MB90385 Series
Table 1.2-1 Product Lineup for MB90385 Series
Classification
MB90V495G
MB90F387/S
MB90387/S
Evaluation product
Flash ROM
Mask ROM
ROM Size
--
64 KB
RAM Size
6 KB
2 KB
Clock
Dual system products
Process
Package
MB90F387: dual system
products
MB90F387S: single system
product
MB90387: dual system
products
MB90387S:single system
product
CMOS
PGA256
LQFP-48 (with 0.50-mm pin pitch),
Operating supply voltage
4.5 V to 5.5 V
3.5 V to 5.5 V
Power supply for emulator *
Not provided
--
*: Setting of DIP Switch (S2) when using emulation pod (MB2145-507). For details, refer to the MB2145-507 Hardware
Manual (Section 2.7 Emulator-specific Power Supply).
5
CHAPTER 1 OVERVIEW
■ CPU and Resources for MB90385 Series
Table 1.2-2 CPU and Resources for MB90385 Series (1/2)
MB90V495G
CPU Function
MB90F387/S
MB90387/S
Basic instruction count: 351
Instruction bit length: 8 or 16 bits
Instruction length: 1 to 7 bytes
Data bit length: 1, 8, or 16 bits
Minimum instruction execution time: 62.5 ns (at 16-MHz machine clock frequency)
Interrupt processing time: 1.5 μs (at 16-MHz machine clock frequency)
Low-power consumption
(standby) modes
Sleep mode, watch mode, timebase timer mode, stop mode, CPU intermittent
operation mode
I/O Ports
General-purpose I/O ports (CMOS output):34 ports (36 ports *)
included 4 output ports for high current
(P14 to P17)
Timebase timer
18-bit free-run counter
Interrupt cycle: 1.024, 4.096, 16.834, 131.072 ms
(at 4-MHz oscillation clock frequency)
Watchdog timer
Reset cycle: 3.58, 14.33, 57.23, 458.75 ms
(at 4-MHz oscillation clock frequency)
16-bit I/O timers
6
16-bit freerun timer
Channel count: 1
Overflow interrupt
Input capture
Channel count: 4
Free-run timer values saved by pin input (rising edge, falling edge, both edges)
16-bit reload timer
Channel count: 2
Operation of 16-bit reload timer
Count clock cycle: 0.25μs, 0.5μs, 2.0μs
(at 16-MHz machine clock frequency)
External event countable
Watch timer
15-bit free-run counter
Interrupt cycle: 31.25, 62.5, 12, 250, 500 ms, and 1.0 s, 2.0 s (at 8.192-kHz subclock
frequency)
8-/16-bit PPG timer
Channel count: 2 (operable with 8 bits × 4 channels)
PPG operable with 8 bits × 4 channels or 16 bits × 2 channels
Pulse waveform output at arbitrary cycle and duty
Count clock: 62.5 ns to 1μs
(at 16-MHz machine clock frequency)
Delayed interrupt generation
module
Interrupt generation module for switching task
Used for Real-time OS
DTP/external interrupt
Input count: 4
Start on rising or falling edges and by High- or Low-level inputs
External interrupts or extended intelligent I/O service (EI2OS)
CHAPTER 1 OVERVIEW
Table 1.2-2 CPU and Resources for MB90385 Series (2/2)
MB90V495G
MB90F387/S
MB90387/S
8-/10-bit A/D converter
Channel count: 8
Resolution: 10 or 8 bits
Conversion time: 6.125μs (including sampling time at 16-MHz machine clock
frequency)
Two or more continuous channels can be converted sequentially (up to 8 channels)
Single conversion mode: Selected channel converted once only
Continuous conversion mode: Selected channel converted continuously
Stop conversion mode: Selected channel converted and temporary stopped alternately
UART 1
Channel count: 1
Clock synchronous transfer: 62.5 kbps to 2 Mbps
Clock asynchronous transfer: 9,615 bps to 500 kbps
Two-way serial communication function, master/slave-connected communication
CAN
Conforms to CAN Specification Ver. 2.0A and Ver. 2.0B
Transmit/receive message buffer: 8
Transfer bit rate: 10 kbps to 1 Mbps (at 16-MHz machine clock)
CAN wake-up
*: MB90387S, MB90F387S
7
CHAPTER 1 OVERVIEW
1.3
Block Diagram of MB90385 Series
Block diagram of the MB90385 series is shown in the figure below.
■ Block Diagram of MB90385 Series
Figure 1.3-1 Block Diagram of MB90385 Series
X0,X1
RST
X0A,X1A
Clock control circuit
CPU
F2MC-16LX core
Watch timer
16-bit free-run timer
Timebase timer
Input capture
(4 ch)
ROM/Flash
Prescaler
SOT1
SCK1
SIN1
Internal data bus
RAM
16-bit PPG timer
(2 ch)
CAN
IN0 to IN3
PPG0 to PPG3
RX
TX
UART1
DTP/external interrupt
INT4 to INT7
AVcc
AVss
AN0 to AN7
AVR
ADTG
8
8-/10-bit
A/D converter
(8 ch)
16-bit reload timer
(2 ch)
TIN0, TIN1
TOT0, TOT1
CHAPTER 1 OVERVIEW
1.4
Pin Assignment
Pin assignment of the MB90385 series is shown in the figure below.
■ Pin Assignment (FPT-48P-M26)
48
47
46
45
44
43
42
41
40
39
38
37
AV SS
X1A/ P36*
X0A/ P35*
P33
P32
P31
P30
P44/ RX
P43/ TX
P42/ SOT1
P41/ SCK1
P40/ SIN1
Figure 1.4-1 Pin Assignment (FPT-48P-M26)
TOP VIEW
36
35
34
33
32
31
30
29
28
27
26
25
P17/ PPG3
P16/ PPG2
P15/ PPG1
P14/ PPG0
P13/ IN3
P12/ IN2
P11/ IN1
P10/ IN0
X1
X0
C
V SS
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
P21/ TOT0
P22/ TIN1
P23/ TOT1
P24/ INT4
P25/ INT5
P26/ INT6
P27/ INT7
MD2
MD1
MD0
RST
V CC
AV CC
AVR
P50/ AN 0
P51/ AN 1
P52/ AN 2
P53/ AN 3
P54/ AN 4
P55/ AN 5
P56/ AN 6
P57/ AN 7
P37/ ADTG
P20/ TINO
*:MB90387, MB90F387 : X1A, X0A
MB90387S, MB90F387S : P36, P35
9
CHAPTER 1 OVERVIEW
1.5
Package Dimension
The MB90385 series is available in one type of package.
The package dimensions below are for reference only. Contact Fujitsu for the nominal
package dimensions.
■ Package Dimension of FPT-48P-M26
48-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
7 × 7 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.17 g
Code
(Reference)
P-LFQFP32-7×7-0.50
(FPT-48P-M26)
48-pin plastic LQFP
(FPT-48P-M26)
Note 1) * : These dimensions include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00±0.20(.354±.008)SQ
+0.40
+.016
* 7.00 –0.10 .276 –.004 SQ
0.145±0.055
(.006±.002)
25
36
37
24
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
48
13
"A"
0˚~8˚
LEAD No.
1
0.50(.020)
(Mounting height)
.059 –.004
INDEX
0.10±0.10
(.004±.004)
(Stand off)
12
0.20±0.05
(.008±.002)
0.08(.003)
0.25(.010)
M
0.60±0.15
(.024±.006)
C
2003 FUJITSU LIMITED F48040S-c-2-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
10
CHAPTER 1 OVERVIEW
1.6
Pin Description
This section describes the I/O pins and their functions of the MB90385 series.
■ Pin Description
Table 1.6-1 Pin Description (1/3)
Pin No.
Pin Name
LQFP
Circuit
Type
Function
1
AVCC
--
VCC power input pin for A/D converter
2
AVR
--
Power (Vref+) input pin for A/D converter. The power
supply should not be input exceeding
P50 to P57
3 to 10
General-purpose I/O port
E
AN0 to AN7
Analog input pin for A/D converter. These pins work when
the analog input is set to "enable."
P37
General-purpose I/O port.
11
D
ADTG
External trigger input pin for A/D converter. This pin should
be set to "input port".
P20
General-purpose I/O port.
12
D
TIN0
Event input pin for reload timer 0. This pin should be set to
"input port."
P21
General-purpose I/O port.
13
D
TOT0
Event output pin for reload timer 0. This pin is enabled only
when the output setting is "enabled".
P22
General-purpose I/O port.
14
D
TIN1
Event input pin for reload timer 1. This pin should be set to
"input port".
P23
General-purpose I/O port.
15
D
TOT1
Event output pin for reload timer 1. This pin is enabled only
when the output setting is "enabled".
P24 to P27
General-purpose I/O port.
16 to 19
D
External interrupt input pins. These pins should be set to
"input port".
INT4 to INT7
20
MD2
F
Input pin for selecting operation mode
21
MD1
C
Input pin for selecting operation mode
22
MD0
C
Input pin for selecting operation mode
11
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Description (2/3)
Pin No.
Pin Name
LQFP
Circuit
Type
Function
23
RST
B
Input pin for external reset
24
VCC
--
Power (5 V) input pin.
25
VSS
--
Power (0 V) input pin
26
C
--
Capacity pin for stabilizing power supply. This pin should
be connected to a ceramic capacitor of approx. 0.1μF.
27
X0
A
High-speed oscillation pin
28
X1
A
High-speed oscillation pin
P10 to P13
29 to 32
General-purpose I/O ports.
D
IN0 to IN3
Trigger input pins for input capture channels 0 to 3. These
pins should be set to "input port".
P14 to P17
General-purpose I/O ports. High current output port.
33 to 36
G
PPG0 to PPG3
Output pins for PPG timers 01 and 23. These pins are
enabled when the output setting is "enabled".
P40
General-purpose I/O port
37
D
SIN1
Serial data input pin for UART1. This pin should be set to
"input port".
P41
General-purpose I/O port.
38
D
SCK1
Serial clock I/O pin for UART1. This pin is enabled only
when the serial clock I/O setting of the UART1 is "enabled".
P42
General-purpose I/O port.
SOT1
Serial data output pin for UART1. This pin functions only
when the serial data output setting of the UART1 is
"enabled".
P43
General-purpose I/O port.
39
D
40
D
TX
CAN transmission output pin. This pin is enabled only when
the output setting is "enabled".
P44
General-purpose I/O port.
41
D
CAN reception input pin. This pin should be set to "input
port".
P30 to P33
D
General-purpose I/O port.
X0A*
A
Low-speed oscillation pin.
P35*
D
General-purpose I/O port.
RX
42 to 45
46
12
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Description (3/3)
Pin No.
Pin Name
LQFP
Circuit
Type
Function
X1A*
A
Low-speed oscillation pin.
P36*
D
General-purpose I/O port.
AVSS
--
VSS power input pin for A/D converter
47
48
*: MB90387, MB90F387 : X1A, X0A
MB90387S, MB90F387S : P36, P35
13
CHAPTER 1 OVERVIEW
1.7
I/O Circuit
I/O circuit of the MB90385 series is shown in the figure below.
■ I/O Circuit
Table 1.7-1 I/O Circuit (1/2)
Classification
Circuit
Remark
A
X1
Clock input
X1A
X0
X0A
• Approximately 1 MΩ high speed
oscillation feedback resistor.
• Oscillation feedback resistor for low speed
approximately 10 MΩ
Standby mode control signal
B
• Hysteresis input with pull-up resistor
• Pull-up resistor: about 50kΩ
Vcc
R
R
Hysteresis input
C
• Hysteresis input
R
Hysteresis input
D
• CMOS hysteresis input
• CMOS-level output
• Standby control provided
Vcc
P-ch
R
N-ch
Vss
Digital output
Digital output
Hysteresis input
Standby mode control
E
•
•
•
•
Vcc
P-ch
R
N-ch
Vss
Digital output
Digital output
Hysteresis input
Standby mode control
Analog input
14
CMOS hysteresis input
CMOS-level output
Also used as analog input pin
Standby control provided
CHAPTER 1 OVERVIEW
Table 1.7-1 I/O Circuit (2/2)
Classification
Circuit
Remark
F
R
Hysteresis input
• Hysteresis input with pull-down resistor
• Pull-down resistor: about 50kΩ
• There is no pull-down resistor in FLASH
product
R
Vss
G
• CMOS hysteresis input
• CMOS-level output (for high current
output)
• Standby control provided
Vcc
P-ch
R
N-ch
Vss
High current output
High current output
Hysteresis input
Standby mode control
15
CHAPTER 1 OVERVIEW
16
CHAPTER 2
HANDLING DEVICES
This chapter describes the precautions when handling
general-purpose one chip microcontroller.
2.1 Precautions when Handling Devices
17
CHAPTER 2 HANDLING DEVICES
2.1
Precautions when Handling Devices
This section describes the precautions against the power supply voltage of the device
and processing of pin.
■ Precautions when Handling Devices
● Preventing latch-up
• For a CMOS IC, latch-up may occur when a voltage higher than VCC or a voltage lower than VSS is
impressed to the I/O pin other than medium-/high-voltage withstand I/O pins, or when a voltage that
exceeds the rated voltage is impressed between VCC and VSS.
• Latch-up may cause a sudden increase in power supply current, resulting in thermal damage to the
device. Therefore, the maximum voltage ratings must not be exceeded.
• When turning the analog power supply on and off, the analog power supply voltage (AVCC and AVR)
and the analog input voltage should not exceed the digital power supply voltage (VCC).
● Handling not-used pins
If unused input pins remain open, a malfunction or latch-up may cause permanent damage, so take
countermeasures such as pull-up or pull-down using a 2 kΩ or larger resistor.
Leave unused input pins open in the output state or, if left in the input state, treat them in the same manner
as for input pins in use.
● Precautions of using external clock
When an external clock is used, drive only the X0 pin and open the X1 pin. Figure 2.1-1 shows a use
example of external clock.
Figure 2.1-1 Example of Using External Clock
X0
Open
X1
MB90385 series
● Precautions of non-use of subclock
If an oscillator is not connected to the X0A and X1A pins, connect the X0A pin to Pull-down and leave the
X1A pin open.
18
CHAPTER 2 HANDLING DEVICES
● Precautions during operation of PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops
while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its
operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such
failure occurs.
● Power pins
• When plural VCC pins and VSS pins are provided, pins designed to be at the same electric potential are
internally connected to the device to prevent malfunctions such as latch-up. However, always connect
all same electric potential pins to power supply and ground outside the device to prevent decrease of
unnecessary radiation, the malfunction of the strobe signal due to a rise of ground level, and follow the
standards of total output current.
• The power pins should be connected to VCC and VSS of the MB90385 series device at the lowest
possible impedance from the current supply source.
• It is best to connect approximately 0.1μF capacitor between VCC and VSS as a bypass capacitor near the
pins of the MB90385 series device.
● Crystal oscillator circuit
• Noise near the X0 and X1 pins may cause the MB90385 series to malfunction. Design the PC board so
that the X0 and X1 pins, the crystal (or ceramic) oscillator, and the bypass capacitor to ground are as
close as possible to each other, and so the wiring of the X0 and X1 pins and other wiring do not cross.
• For stable operation, the PC board is recommended to have the artwork with the X0 and X1 pins
enclosed by a ground line.
• Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
● Procedure of A/D converter/analog input power-on
• Always apply a power to the A/D converter power and the analog input (AN0 to AN7 pins) after or
concurrently with the digital power (VCC)-on.
• Always turn off the A/D converter power and the analog input before or concurrently with the digital
power-down.
• Note that AVR should not exceed AVCC at turn on or off. (The analog power and digital power can be
simultaneously turned on or off with no problem.)
● Handling pins when not using A/D converter
When not using the A/D converter, the pins should be connected so that AVCC = AVR = VCC and AVSS =
VSS.
● Precautions at power on
To prevent a malfunction of the internal step-down circuit, the voltage rise time at power-on should be
50 μs or more (between 0.2 V and 2.7 V).
19
CHAPTER 2 HANDLING DEVICES
● Stabilization of supply voltage
If the power supply voltage varies acutely even within the operation assurance range of the VCC power
supply voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized.
As stabilization guidelines, stabilize the power supply voltage so that VCC ripple fluctuations (peak to peak
value) in the commercial frequencies (50 Hz to 60 Hz) fall within 10% of the standard VCC power supply
voltage and the transient fluctuation rate becomes 0.1V/ms or less in instantaneous fluctuation for power
supply switching.
20
CHAPTER 3
CPU
This chapter explains the CPU function of the MB90385
series.
3.1 Memory Space
3.2 Dedicated Registers
3.3 General-purpose Register
3.4 Prefix Codes
3.5 Interrupt
3.6 Reset
3.7 Clocks
3.8 Low-power Consumption Mode
3.9 CPU Mode
21
CHAPTER 3 CPU
3.1
Memory Space
The memory space of the F2MC-16LX is 16 MB and is allocated to I/O, programs, and
data. Part of the memory space is used for specific uses such as the expansion
intelligent I/O service (EI2OS) descriptors, the general-purpose registers, and the vector
tables.
■ Memory Space
I/O, programs and data are all allocated somewhere in the 16-MB memory space of the F2MC-16LX CPU.
The CPU can indicate their addresses in the 24-bit address bus to access each resource.
Figure 3.1-1 shows an example of the relationships between the F2MC-16LX and the memory map.
Figure 3.1-1 Example of Relationships between F2MC-16LX System and Memory Map
F2MC-16LX Device
Generalpurpose port
Resource
Interrupt
2OS
F2MC-16LX
CPU
Internal data bus
EI
Data
000000 H
000020 H
0000B0 H
0000C0 H
000100 H
000180 H
000380 H
000900 H *1
003900 H
004000 H
010000 H
FE0000 H
FF0000 H*2
I/O port control register area
Resource control register area
EI2OS
descriptor area
General-purpose register
RAM area
Data area
Peripheral function control register area
Extended I/O area
ROM area
(image of FF bank)
ROM area
(The same data as FF bank)
Program area
Program
ROM area
FFFC00 H
Vector table area
FFFFFF H
*1: The capacity of the internal RAM depends on the product.
*2: The capacity of the internal ROM depends on the product.
22
I/O area
Interrupt control register area
CHAPTER 3 CPU
■ ROM Area
● Vector table area (address: "FFFC00H" to "FFFFFFH")
• The vector table is provided for reset and interrupts.
• This area is allocated at the top of the ROM area. The starting address of the corresponding processing
routine is set to the address of each vector table as data.
● Program area (address: to "FFFBFFH")
• ROM is contained as the internal program area.
• The capacity of the internal ROM depends on the product.
■ RAM Area
● Data area (address: "000100H" to "000900H")
• Static RAM is contained as the internal data area.
• The capacity of the internal RAM depends on the product.
● General-purpose register area (address: "000180H" to "00037FH")
• Auxiliary registers for operations or transfer of the 8-bit, 16-bit, or 32-bit data are allocated in this area.
• This area is allocated to part of the RAM area, and can also be used as ordinary RAM.
• When this area is used as general-purpose registers, they can be accessed quickly using a short
instruction through general-purpose register addressing.
● Expanded intelligent I/O service (EI2OS) descriptor area (address: "000100H" to "00017FH")
• This area holds the transfer mode, I/O address, transfer count, and buffer address.
• This area is allocated to part of the RAM area, and can also be used as ordinary RAM.
■ I/O Area
● Interrupt control register area (address: "0000B0H" to "0000BFH")
The interrupt control registers (ICR00 to ICR15) correspond to all resources with an interrupt function, and
control the setting of interrupt level and EI2OS.
● Resource control register area (address: "000020H" to "0000AFH")
This area controls the resource function and data I/O.
● I/O port control register area (address: "000000H" to "00001FH")
This area controls the I/O ports and data I/O.
■ Extended I/O Area
● Peripheral function control register area (address: "003900H" to "003FFFH")
The registers control peripheral functions and input/output data.
23
CHAPTER 3 CPU
3.1.1
Mapping of and Access to Memory Space
In the MB90385 series, the single-chip mode can be set as memory access modes.
■ Memory Map for MB90385 Series
In the MB90385 series, the internal address bus is output up to a width of 24 bits and the external address
bus is output up to a width of 24 bits; the external access memory can access up to the 16-MB memory
space.
Figure 3.1-2 shows the memory map when the ROM mirroring function is enabled and disabled.
Figure 3.1-2 Memory Map for MB90385 Series
When ROM mirror function is enabled
000000H
0000C0H
000100H
When ROM mirror function is disabled
Resource
Resource
RAM area
Register
RAM area
Register
Extend I/O area
Extend I/O area
Address#1
003900H
004000H
ROM area
(image of FF bank)
010000H
FE0000H
ROM area *
ROM area *
ROM area
ROM area
FF0000H
FFFFFFH
Product
Address#1
MB90V495G
001900H
MB90F387/S
000900H
MB90387/S
000900H
: Internal access memory
: Access disabled
* : When the area from "FE0000H" to "FEFFFFH" of MB90387/S or MB90F387/S
is read out, the data "FF0000H" to "FFFFFFH" can be read.
24
CHAPTER 3 CPU
■ Image Access to Internal ROM
In the F2MC-16LX family, with the internal ROM in operation, ROM data in the FF bank can be seen as an
image in the top 00 bank. This function is called ROM mirroring and enables effective use of a small C
compiler.
In the F2MC-16LX family, the lower 16-bit addresses of the FF bank are the same as the lower 16-bit
addresses of the 00 bank, so the table in ROM can be referenced without specifying "far" with a pointer.
For example, if "00C000H" is accessed, data in ROM at "FFC000H" is actually accessed. However, the
ROM area in the FF bank exceeds 48 KB and all areas cannot be seen as images in the 00 bank. Therefore,
ROM data from "FF4000H" to "FFFFFFH" is see as an image from "004000H" to "00FFFFH" so the ROM
data table should be stored in the area from "FF4000H" to "FFFFFH".
Reference:
To disable the ROM mirroring function (ROMM: MI = 0), see Section "17.1 Overview of ROM
Mirroring Function Select Module".
25
CHAPTER 3 CPU
3.1.2
Memory Map
The MB90385 series memory map is shown for each product.
■ Memory Map
Figure 3.1-3 shows the memory map for the MB90385 series.
Figure 3.1-3 Memory Map for MB90385 Series
MB90387/S
MB90F387/S
single chip
single chip
I/O
I/O
RAM
RAM
general-purpose
register
general-purpose
register
Extend I/O area
Extend I/O area
ROM area *2
ROM area *2
(image of
FF bank)
(image of
FF bank)
ROM*3
ROM*3
ROM
ROM
MB90V495G
single chip
internal ROM
external bus
external ROM
external bus
I/O
I/O
I/O
RAM
general-purpose
register
RAM
general-purpose
register
Extend I/O area
Extend I/O area
Extend I/O area
ROM area *2
ROM area *2
(image of
FF bank)
(image of
FF bank)
ROM*1
26
RAM
general-purpose
register
ROM*1
: Internal access memory
: External access memory
: Access disabled
*1 : The ROM is not built in the MB90V945G.
Only the dedicated development tool can
be operated in the same way as the internal
ROM products.
*2 : The area from "FF4000H" to "FFFFFFH" of
MB90387/S, MB90F387/S and MB90V495G
can be seen as image in the 00 bank.
*3: When the FE bank of MB90387/S or
MB90F387/S is read out, the data of the FF
bank can be read.
CHAPTER 3 CPU
3.1.3
Addressing
Linear and bank types are available for addressing.
The F2MC-16LX family uses basically bank addressing.
• Linear type: direct-addressing all 24 bits by instruction
• Bank type:addressing higher 8 bits by bank registers suitable for the use, and lower
16 bits by instruction
■ Linear Addressing and Bank Addressing
The linear addressing is to access the 16-MB memory space by direct-addressing. The bank addressing is to
access the 16-MB memory space which divided into 256 banks of 64KB, by specifying banks and
addresses in banks.
Figure 3.1-4 shows overview of memory management in linear and bank type.
Figure 3.1-4 Memory Management in Linear and Bank Types
Linear addressing
000000 H
Bank addressing
000000 H
00FFFF H
010000 H
01FFFF H
020000H
02FFFF H
123456H
123456H
FFFFFF H
FD0000 H
FDFFFF H
FE0000 H
FEFFFF H
FF0000 H
FFFFFF H
123456H
Specified by instruction
00 bank
64 KB
01 bank
02 bank
12 bank
FD bank
FE bank
FF bank
123456 H
Specified by instruction
Specified by bank register
27
CHAPTER 3 CPU
3.1.4
Linear Addressing
The linear addressing has the following two types:
• Direct-addressing 24 bits by instruction
• Using lower 24 bits of 32-bit general-purpose register for address
■ Linear Addressing by Specifying 24-bit Operand
Figure 3.1-5 Example of 24-bit Physical Direct Addressing in Linear Type
JMPP 123456H
Old program bank
+ program counter
10
452D
10452D H
New program bank
+ program counter
12
3456
123456 H
JMPP 123456H
Next instruction
■ Addressing by Indirect-specifying 32-bit Register
Figure 3.1-6 Example of indirect-specifying 32-bit General-purpose Register in Linear Type
MOV A,@RL1+7
Upper 8 bits ignored
Old accumulator
RL1
XXXX
FFFF06F9H
+7
New accumulator
003A
RL1 : 32-bit (long word) general-purpose register
28
FF0700H
3AH
CHAPTER 3 CPU
3.1.5
Bank Addressing
The bank addressing is a type of addressing each of 256 banks of 64-KB into which the
16-MB memory space is divided, using the bank register, and the lower 16 bits by an
instruction.
Bank register has the following five types depending on the use.
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional bank register (ADB)
■ Bank Registers and Access Space
Table 3.1-1 shows the access space for each bank register and the major use of it.
Table 3.1-1 Access Space for Each Bank Register and Major Use of Access Space
Bank Register Name
Access Space
Major Use
Reset Value
Program bank register
(PCB)
Program (PC)
space
Stores instruction code, vector
tables, immediate data.
FFH
Data bank register
(DTB)
Data (DT)
space
Stores data that can be read/written
and can access resource control
registers and data registers.
00H
User stack bank
register (USB)
System stack bank
register (SSB)*
Additional data bank
register (ADB)
Stack (SP)
space
These are used for the stack
accessing such as the PUSH/POP
instruction and the register saving at
an interrupt. When the stack flag
(CCR: S) is "1", SSB is used. When
the stack flag is "0", USB is used*.
Additional
(AD) space
Stores data that cannot be stored in
data (DT) space.
00H
00H
00H
*: SSB is always used for the stack at an interrupt.
29
CHAPTER 3 CPU
Figure 3.1-7 shows the relationships between the memory space divided into banks and each register.
Figure 3.1-7 Example of Bank Addressing
000000H
070000H
System stack space
07H
: SSB (System stack bank register)
Data space
0BH
: DTB (Data bank register)
User stack space
0DH
: USB (User stack bank register)
Additional space
0FH
: ADB (Additional bank register)
Program space
FFH
: PCB (Program bank register)
07FFFFH
Physical address
0B0000H
0BFFFFH
0D0000H
0DFFFFH
0F0000H
0FFFFFH
FF0000H
FFFFFFH
Reference:
For details, see Section "3.2 Dedicated Registers".
■ Bank Addressing and Default Space
To improve the instruction code efficiency, the default space shown in Table 3.1-2 is determined for each
instruction in each addressing type. To use any bank space other than the default space, specify the prefix
code for that bank space before the instruction, which makes the arbitrary bank space corresponding to the
prefix code accessible.
Table 3.1-2 Addressing and Default Spaces
Default Spaces
Addressing
Program space
PC indirect addressing, program-access addressing, branch instruction
addressing
Data space
Addressing with @RW0, @RW1, @RW4, @RW5, @A, addr16, and dir
Stack space
Addressing with PUSHW, POPW, @RW3, and @RW7
Additional space
Addressing with @RW2 and @RW6
Reference:
For details of the prefix codes, see Section "3.4 Prefix Codes".
30
CHAPTER 3 CPU
3.1.6
Allocation of Multi-byte Data on Memory
Multi-byte data is written to memory in sequence starting from the low address. For 32bit length data, the lower 16 bits are written first, and then the higher 16 bits are written.
If a reset signal is output immediately after the lower 16 bits is written, the higher 16 bit
may not be written.
■ Store of Multi-byte Data in RAM
Figure 3.1-8 shows the order in which multi-byte data is stored. Lower 8 bits are allocated to n address, and
in order of n+1, n+2, n+3 and so on.
Figure 3.1-8 Storage of Multi-byte Data in RAM
Low address
Address n
00010100B
n+1
11111111B
n+2
n+3
11001100B
01010101B
MSB
High address
LSB
01010101B 11001100B 11111111B 00010100B
MSB: Most significant bit
LSB: Least significant bit
■ Storage of Multi-byte Length Operand
Figure 3.1-9 shows the configuration of a multi-byte length operand in memory.
Figure 3.1-9 Storage of Multi-byte Operand
JMPP 123456H
Low address
Address n
n+1
n+2
n+3
JMPP 1 2 3 4 5 6H
63H
56H
34H
12H
High address
31
CHAPTER 3 CPU
■ Storage of Multi-byte Data in Stack
Figure 3.1-10 shows the order in which multi-byte data is stored in the stack.
Figure 3.1-10 Storage of Multi-byte Data in Stack
PUSHW RW1,RW3
Low address
PUSHW RW1,
RW3
(35A4H) (6DF0H)
A4H
35H
F0H
6DH
SP
High address
RW1: 35A4H
RW3: 6DF0H
*:
State of stack after execution of PUSHW instruction
■ Access to Multi-byte Data
All accesses are basically made inside the bank. Consequently, for an instruction that accesses multi-byte
data, the address after the "FFFFH" address is the "0000H" address of the same bank.
Figure 3.1-11 shows an example of access instruction for multi-byte data on the bank boundary.
Figure 3.1-11 Access to Multi-byte Data on Bank Boundary
Low address
AL before execution
800000H
:
:
80FFFFH
High address
32
??
??
23H
01H
MOVW A, 080FFFFH
AL after execution
23H
01H
CHAPTER 3 CPU
3.2
Dedicated Registers
The CPU has the following dedicated registers.
• Accumulator
• User stack pointer
• System stack pointer
• Processor status
• Program counter
• Direct page register
• Bank registers (program bank register, data bank register, user stack bank register,
system stack bank register, additional data bank register)
■ Configuration of Dedicated Registers
Figure 3.2-1 Configuration of Dedicated Registers
AH
AL
USP
: Accumulator (A)
The accumulator is two 16-bit registers, and is used to store operation results.
It can also be used as one 32-bit register.
: User stack pointer (USP)
This is a 16-bit pointer that indicates the user stack address.
SSP
: System stack pointer (SSP)
This is a 16-bit pointer that indicates the system stack address.
PS
: Processor status (PS)
PC
: Program counter (PC)
This is a 16-bit register that indicates the system status.
This is a 16-bit register that indicates the current instruction store location.
DPR : Direct page register (DPR)
This is an 8-bit register that sets bits 8 to 15 of 24 bits of addresses when using abbreviated direct addressing.
PCB : Program bank register (PCB)
This is an 8-bit register that indicates the program space.
DTB : Data bank register (DTB)
This is an 8-bit register that indicates the data space.
USB : User stack bank register (USB)
This is an 8-bit register that indicates the user stack space.
SSB : System stack bank register (SSB)
This is an 8-bit register that indicates the system stack space.
ADB : Additional data bank register (ADB)
This is an 8-bit register that indicates the additional space.
8 bits
16 bits
32 bits
33
CHAPTER 3 CPU
Table 3.2-1 Reset Values of Dedicated Registers
Dedicated Register
Reset Value
Accumulator (A)
Undefined
User stack pointer (USP)
Undefined
System stack pointer (SSP)
Undefined
Processor status (PS)
PS
bit15 to bit13 bit12 to
bit8 bit7
to
bit0
CCR
RP
ILM
0 0 0 0 0 0 0 0
0 1 x x x x x
− : Unused
X : Undefined
Program counter (PC)
Direct page register (DPR)
Program bank register (PCB)
Value of reset vector (data at "FFFFDCH" and "FFFFDDH")
01H
Value of reset vector (data at "FFFFDEH")
Data bank register (DTB)
00H
User stack bank register (USB)
00H
System stack bank register (SSB)
00H
Additional data bank register (ADB)
00H
Note:
The above reset values are the reset values for the device. The reset values for the ICE (such as
emulator) are different from those of the device.
34
CHAPTER 3 CPU
3.2.1
Dedicated Registers and General-purpose Register
The F2MC-16LX family has two types of registers: dedicated registers in the CPU and
general-purpose register in the internal RAM.
■ Dedicated Registers and General-purpose Register
The dedicated registers are limited to the use in the hardware architecture of the CPU.
The general-purpose registers are in the internal RAM in the CPU address space. As with the dedicated
registers, these registers can be used for addressing and the use of these register is not limited.
Figure 3.2-2 shows the allocation of the dedicated registers and the general-purpose registers.
Figure 3.2-2 Dedicated Registers and General-purpose Register
CPU
Internal RAM
Dedicated register
General-purpose register
Accumulator
User stack pointer
Processor status
Program counter
Direct page register
Program bank register
Internal bus
System stack pointer
Data bank register
User stack bank register
System stack bank register
Additional data bank register
35
CHAPTER 3 CPU
3.2.2
Accumulator (A)
An accumulator (A) consists of two 16-bit length operation registers (AH and AL) used
for temporary storage of the operation result or data.
Accumulator can be used as a 32-, 16-, or 8-bit register. Various operations can be
performed between the register and memory or the other register, or between the AH
register and the AL register.
■ Accumulator (A)
● Data transfer to accumulator
The accumulator can process 32-bit data (long word), 16-bit data (word), and 8-bit data (byte).
• When processing 32-bit data, the AH register and the AL register are concatenated and used.
• When processing 16- or 8-bit data, only the AL register is used.
Data retention function
When data of word length or less is transferred to the AL register, data stored in the AL register is
transferred automatically to the AH register.
Code-extended function and zero-extended function
When transferring data of byte length or less to the AL register, the data is code-extended (MOVX
instruction) or zero-extended (MOVX instruction) to be the 16-bit length and stored in the AL register.
Data in the AL register can also be treated in word and byte lengths.
Figure 3.2-3 shows data transfer to the accumulator and a concrete example.
Figure 3.2-3 Data Transfer to Accumulator
32 bits
AH
AL
32-bit data transfer
Data transfer Data transfer
AH
16-bit data transfer
AL
Data saving
Data transfer
AH
8-bit data transfer
AL
Data saving
00H or FFH* Data transfer
(* : zero-extended or code-extended)
36
CHAPTER 3 CPU
● Byte processing arithmetic operation of accumulator
When the arithmetic operation instruction for byte processing is executed for the AL register, the higher 8
bits of the AL register in pre-operation are ignored, and the higher 8 bits of the operation result become all
"0".
● Reset value of accumulator
The reset value is undefined.
Figure 3.2-4 Example of 8-bit Data Transfer to Accumulator (A) (Data Saving)
MOVW A,3000H
(Instruction that stores the data at address "3000H" in the AL register.)
Memory space
MSB
Before execution
AH
AL
XXXXH
2456H
DTB
After execution
2456H
B53001 H
77H
LSB
B53000 H
88H
B5H
X
MSB
LSB
DTB
7788H
:
:
:
:
Undefined
Most Significant Bit
Least Significant Bit
Data bank register
Figure 3.2-5 Example of 8-bit Data Transfer to Accumulator (A) (Data Saving, Zero-extended)
(Instruction that zero-extends the data at address "3000H"
and stores the extended data in the AL register.)
MOV A,3000H
MSB Memory space
Before
execution
AH
AL
XXXXH
2456H
DTB
After
execution
2456H
0088H
B53001 H
77H
LSB
88H
B53000 H
B5H
X
MSB
LSB
DTB
:
:
:
:
Undefined
Most significant bit
Least significant bit
Data bank register
37
CHAPTER 3 CPU
Figure 3.2-6 Example of 16-bit Data Transfer to Accumulator (A) (Data Saving)
MOVW A,@RW1+6
Before
execution
AH
XXXXH
(Instruction that performs word length read using the result obtained
by adding the 8-bit length offset to data of RW1 as an address, and then
stores the read value in the A register.)
1234H
DTB
After
execution
1234H
Memory space
MSB
AL
A6H
RW1
15H
38H
A6153FH
A61541H
2BH
8FH
52H
74H
LSB
+6
2B52H
X
MSB
LSB
DTB
:
:
:
:
A6153EH
A61540H
Undefined
Most significant bit
Least significant bit
Data bank register
Figure 3.2-7 Example of 32-bit Data Transfer to Accumulator (A) (Register Indirect)
MOVL A,@RW1+6
Before
execution
AH
XXXXH
(Instruction that performs long-word length read using the result obtained
by adding the 8-bit length offset to data of RW1 as an address, and then
stores the read value in the A register.)
DTB
After
execution
8F74H
2B52H
A6H
RW1
15H
38H
A6153FH
A61541H
2BH
8FH
52H
74H
LSB
+6
X
MSB
LSB
DTB
38
Memory space
MSB
AL
XXXXH
:
:
:
:
A6153EH
A61540H
Undefined
Most significant bit
Least significant bit
Data bank register
CHAPTER 3 CPU
3.2.3
Stack Pointer (USP, SSP)
The stack pointers include a user stack pointer (USP) and a system stack pointer (SSP).
Both these pointers indicate the address where saved data and return data are stored
when the PUSH instruction, the POP instruction, and the subroutine is executed.
• The higher 8 bits of the stack address are set by the user stack bank register (USB) or
the system stack bank register (SSB).
• When the stack flag (PS: CCR: S) is "0", the USP and USB register are enabled. When
the stack flag is "1", the SSP and SSB register are enabled.
■ Stack Selection
For the F2MC-16LX family, two types of stack pointer can be used: system stack, and user stack.
The addresses of the stack pointers are set by the stack flag of the condition code register (CCR: S) as
shown in Table 3.2-2.
Table 3.2-2 Stack Address Specification
Stack Address
S Flag
Higher 8 Bits
Lower 16 Bits
0
User stack bank register (USB)
User stack pointer (USP)
1*
System stack bank register (SSB)
System stack pointer (SSP)
*: Reset value
Since the stack flag (CCR: S) is set to "1" by a reset, the system stack pointer is used after reset.
Ordinarily, the system stack pointer is used in processing the stack at the interrupt routine, and the user
stack pointer is used in processing the stack other than interrupt routine. When it is not necessary to divide
the stack space, use only the system stack pointer.
Note:
When an interrupt is accepted, the stack flag (CCR: S) is set and the system stack pointer is always
used.
39
CHAPTER 3 CPU
Figure 3.2-8 shows an example of the stack operation using the system stack.
Figure 3.2-8 Stack Operation Instructions and Stack Pointers
PUSHW A when S flag = 0
Before
Execution
After
Execution
MSB
AL A624H
USB C6H
USP F328H
0
SSB 56H
SSP 1234H
AL A624H
USB C6H
USP F326H
S flag
SSB 56H
SSP 1234H
S flag
0
C6F327 H
LSB
XXH
C6F326 H
XXH
User stack pointer used
because S flag = 0
C6F327 H
A6H
24H
C6F326 H
PUSHW A when S flag = 1
MSB
Before
Execution
After
Execution
AL A624H
USB C6H
USP F328H
S flag
1
SSB 56H
SSP 1234H
AL A624H
USB C6H
USP F328H
S flag
SSB 56H
SSP 1232H
1
LSB
561233 H
XXH
XXH
561232 H
561233 H
A6H
24H
561232 H
System stack pointer used
because S flag = 1
X
: Undefined
MSB : Most significant bit
LSB : Least significant bit
Notes:
• Use even addresses for setting value to the stack pointer. Setting an odd address divides the
word access into two accesses, decreasing the efficiency.
• The reset values of the USP and SSP registers are undefined.
■ System Stack Pointer (SSP)
When using the system stack pointer (SSP), the stack flag (CCR: S) is set to "1". The higher 8 bits of the
address used in processing the stack are set by the system stack bank register (SSB).
■ User Stack Pointer (USP)
When using the user stack pointer (USP), the stack flag (CCR: S) is set to "0". The higher 8 bits of the
address used in processing the stack are set by the user stack bank register (USB).
40
CHAPTER 3 CPU
■ Stack Area
● Securing stack area
The stack area is used to save and return the program counter (PC) at execution of the interrupt processing,
subroutine call instruction (CALL) and vector call instruction (CALLV). It is also used to save and return
temporary registers using the PUSHW and POPW instructions.
The stack area is secured with the data area in RAM.
The stack area is as shown below:
Figure 3.2-9 Stack Area
000000 H
I/O area
0000C0 H
000100 H
000180 H
Stack area
000380 H
Generalpurpose
register bank area
Internal RAM area
000900 H
~
~
~
~
FF0000H *
ROM area
Vector table
(reset, interrupt vector
call instruction)
FFFC00H
FFFFFFH
*: Internal ROM capacity depends on devices.
Note:
As a general rule, even addresses should be set in the stack pointers (SSP and USP).
Each of the system stack area, user stack area, and data area should not overlap.
● System stack area and user stack area
The system stack area is used for interrupt processing. When an interrupt occurs, even if the user stack area
is used, it is switched forcibly to the system stack area. Therefore, in systems mainly using the user stack
area also, the system stack area must be set correctly.
In particular, only the system stack area should be used unless it is necessary to divide the stack space.
41
CHAPTER 3 CPU
3.2.4
Processor Status (PS)
The processor status (PS) consists of the bits controlling CPU and various bits
indicating the CPU status. The PS consists of the following three registers.
• Interrupt level mask register (ILM)
• Register bank pointer (RP)
• Condition code register (CCR)
■ Configuration of Processor Status (PS)
The processor status (PS) consists of bits controlling CPU and various bits indicating the CPU status.
Figure 3.2-10 shows the configuration of the processor status (PS).
Figure 3.2-10 Processor Status (PS)
RP
ILM
bit 15 14 13 12 11 10
PS
CCR
6
5
ILM2 ILM1 ILM0 B4 B3 B2 B1 B0 ⎯
I
⎯
0
Reset value 0
0
0
0
0
0
9
0
8
0
7
2
1 bit 0
4
3
S
T
N
Z
V
C
1
X
X
X
X
X
⎯ : Unused
X : Undefined
● Interrupt level mask register (ILM)
This register indicates the level of the interrupt that the CPU is currently accepting. The value of this
register is compared to the value of the interrupt level setting bits of the interrupt control register (ICR: IL0
to IL2) corresponding to the interrupt request of each resource.
● Register bank pointer (RP)
This register set the memory block (register bank) to be used for the general-purpose registers allocated in
the internal RAM.
General-purpose registers can be set for up to 32 banks. The general-purpose register banks to be used are
set by setting "0" to "31" in the register bank pointer (RP).
● Condition code register (CCR)
This register consists of various flags that are set ("1") or cleared ("0") by instruction execution result or
acceptance of an interrupt.
42
CHAPTER 3 CPU
3.2.4.1
Condition Code Register (PS: CCR)
The condition code register (CCR) is an 8-bit register consisting of bits indicating the
result of instruction execution, and the bits enabling or disabling the interrupt request.
■ Configuration of Condition Code Register (CCR)
Figure 3.2-11 shows the configuration of the CCR register.
Figure 3.2-11 Configuration of Condition Code Register (CCR)
RP
ILM
bit 15 14 13 12 11 10
PS
CCR
7
6
5
4
3
2
1 bit 0 CCR reset value
ILM2 ILM1 ILM0 B4 B3 B2 B1 B0 ⎯
I
S
T
N
Z
V
C
⎯
0
1
X
X
X
X
X
0
⎯ : Unused
X : Undefined
0
0
0
0
0
9
0
8
0
-01XXXXXB
Interrupt enable flag
Stack flag
Sticky-bit flag
Negative flag
Zero flag
Overflow flag
Carry flag
● Interrupt enable flag (I)
All interrupts except software interrupts are enabled when the interrupt enable flag (CCR: I) is set to "1",
and are disabled when the interrupt enable flag is set to "0". This flag is cleared to "0" by a reset.
● Stack flag (S)
This flag sets the pointer for stack processing.
When the stack flag (CCR: S) is "0", the user stack pointer (USP) is enabled. When the stack flag is "1", the
system stack pointer (SSP) is enabled. If an interrupt is accepted or a reset occurs, the flag is set to "1".
● Sticky-bit flag (T)
If either one of the data shifted out of the carry is "1" when the logic right-shift instruction or arithmetic
right-shift instruction is executed, this flag is set to "1". If all the shifted-out data is "0" or the shift amount
is "0", this flag is set to "0".
● Negative flag (N)
If the most significant bit (MSB) of the operation result is "1", this flag is set to "1". If the MSB is "0", the
flag is cleared to "0".
● Zero flag (Z)
If all the bits of the operation result are "0", this flag is set to "1". If any bit is "1", the flag is cleared to "0".
43
CHAPTER 3 CPU
● Overflow flag (V)
If an overflow occurs as a signed numeric value at the execution of operation, this flag is set to "1". If no
overflow occurs, the flag is cleared to "0".
● Carry flag (C)
If a carry from the MSB or to the least significant bit (LSB) occurs at the execution of operation, this flag is
set to "1". If no carry occurs, this flag is cleared to "0".
Reference:
For the state of the condition code register (CCR) at instruction execution, refer to the Programming
Manual.
44
CHAPTER 3 CPU
3.2.4.2
Register Bank Pointer (PS: RP)
The register bank pointer (RP) is a 5-bit register that indicates the starting address of
the currently used general-purpose register bank.
■ Register Bank Pointer (RP)
Figure 3.2-12 shows the configuration of the register bank pointer (RP).
Figure 3.2-12 Configuration of Register Bank Pointer (RP)
ILM
RP
bit 15 14 13 12 11 10
PS
CCR
9
8
7
6
5
4
3
2
1 bit 0
ILM2 ILM1 ILM0 B4 B3 B2 B1 B0 ⎯
I
S
T
N
Z
V
RP reset value
C
00000B
■ General-purpose Register Area and Register Bank Pointer
The register bank pointer (RP) indicates the allocation of general-purpose registers used in the internal
RAM. The relationship between the values of PR and the actual addresses should conform to the
conversion rule shown in Figure 3.2-13.
Figure 3.2-13 Physical Address Conversion Rules in General-purpose Register Area
Conversion expression [000180H + (RP) × 10H]
When RP = 10H
000180 H
Register bank 0
:
:
000280 H
Register bank 16
:
:
000370 H
Register bank 31
• The register bank pointer (RP) can take the values from "00H" to "1FH" so that the starting address of
the register bank can be set within the range of "000180H" to "00037FH".
• The assembler instruction can use the 8-bit immediate value transfer instruction that is transferred to the
register bank pointer (RP), but only the lower 5 bits of that data is actually used.
• The reset value of the register bank pointer (RP) is set to "00H" after a reset.
45
CHAPTER 3 CPU
3.2.4.3
Interrupt Level Mask Register (PS: ILM)
The interrupt level mask register (ILM) is a 3-bit register indicating the interrupt level
accepted by the CPU.
■ Interrupt Level Mask Register (ILM)
Figure 3.2-14 shows the configuration of the interrupt level mask register (ILM).
Figure 3.2-14 Configuration of Interrupt Level Mask Register (ILM)
ILM
RP
bit 15 14 13 12 11 10
PS
CCR
9
8
7
6
5
4
3
2
1 bit 0
ILM2 ILM1 ILM0 B4 B3 B2 B1 B0 ⎯
I
S
T
N
Z
V
C
ILM reset value
000B
The interrupt level mask register (ILM) indicates the level of an interrupt that the CPU is accepting for
comparison with the values of the interrupt level setting bits (ICR: IL2 to IL0) set according to interrupt
requests from each resource. The CPU performs interrupt processing only when an interrupt with a lower
value (interrupt level) than that indicated by the interrupt level mask register (ILM) is requested with an
interrupt enabled (CCR: I = 1).
• When an interrupt is accepted, its interrupt level value is set in the interrupt level mask register (ILM).
Thereafter, an interrupt with a level value lower than the set level value is not accepted.
• At a reset, the interrupt level mask register (ILM) is always set to "0" to enter the interrupt-disabled
(highest interrupt level) state.
• The assembler instruction can use the 8-bit immediate value transfer instruction that is transferred to the
interrupt level mask register (ILM), but only the lower 3 bits of that data is actually used.
Table 3.2-3 Interrupt Level Mask Register (ILM) and Interrupt Level (High/Low)
ILM2
ILM1
ILM0
Interrupt
Level
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Reference:
For details of the interrupts, see Section "3.5 Interrupt".
46
Interrupt Level (High/Low)
High (Interrupts Disabled)
Low
CHAPTER 3 CPU
3.2.5
Program Counter (PC)
The program counter (PC) is a 16-bit counter indicating the lower 16 bits of the address
for the next instruction code to be executed by the CPU.
■ Program Counter (PC)
The program bank register (PCB) indicates the higher 8 bits of addresses where the next instruction code to
be executed by the CPU is stored; the program counter (PC) indicates the lower 16 bits. As shown in Figure
3.2-15, the actual addresses are combined into 24 bits.
The program counter (PC) is updated by the execution of the conditional branch instruction, the subroutine
call instruction, by an interrupt or reset, etc.
The program counter (PC) can also be used as the base pointer when reading the operand.
Figure 3.2-15 Program Counter (PC)
Upper 8 bits
PCB FEH
Lower 16 bits
PC ABCDH
FEABCDH
Next instruction to
be executed
Note:
Neither the program counter (PC) nor the program bank register (PCB) can be rewritten directly by a
program (such as MOV PC and #FF).
47
CHAPTER 3 CPU
3.2.6
Direct Page Register (DPR)
The direct page register (DPR) sets bit 8 to bit 15 (addr 15 to addr 8) for the 8 bits of the
low address directly specified using the operand when executing the instruction by the
abbreviated direct addressing.
■ Direct Page Register (DPR)
The direct page register (DPR) sets bit 8 to bit 15 (addr 15 to addr 8) for the 8 bits of the low address
directly specified using the operand when executing the instruction by the abbreviated direct addressing.
The direct page register (DPR) is 8 bits long and is set to "01H" at a reset. It is a read and write register.
Figure 3.2-16 Generation of Physical Address in Direct Page Register (DPR)
DTB register
AAAAAAAA
DPR register
BBBBBBBB
Direct address during instruction
CCCCCCCC
24-bit
MSB
physical address
AAAAAAAA
LSB
BBBBBBBB
CCCCCCCC
bit 16 bit 15
bit 8 bit 7
bit 0
bit 24
MSB : Most significant bit
LSB : Least significant bit
Figure 3.2-17 shows the setting of direct page register (DPR) and an example of data access.
Figure 3.2-17 Setting of Direct Page Register (DPR) and Data Access Example
Result from executing instruction
MOV S:56H, #5AH
Higher 8 bits Lower 8 bits
DTB register
12H
DPR register
34H
MSB : Most significant bit
LSB : Least significant bit
48
123455H
123457H
123459H
MSB
123454H
5AH
123456H
123458H
LSB
CHAPTER 3 CPU
3.2.7
Bank Register (PCB, DTB, USB, SSB, and ADB)
The bank register sets the MSB 8 bit of the 24-bit address using bank addressing and
consists of the following five registers:
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional data bank register (ADB)
Each of the above registers indicate the memory bank to which the program, data, user
stack, system stack, or additional is allocated.
■ Program Bank Register (PCB)
The program bank register (PCB) sets the program (PC) space.
This register is rewritten at execution of the JMPP, CALLP, RETP, or RETI instruction that branches to the
entire 16-MB space, at executing a software interrupt instruction, or at a hardware interrupt or exception
interrupt.
■ Data Bank Register (DTB)
The data bank register (DTB) sets the data (DT) space.
■ User Stack Bank Register (USB) and System Stack Bank Register (SSB)
The user stack bank register (USB) and system stack bank register (SSB) set the stack (SP) space. The bank
register that is used is determined by the value of the stack flag (CCR: S).
■ Additional Data Bank Register (ADB)
The additional bank register (ADB) sets the additional (AD) space.
■ Setting of Each Bank and Data Access
Each bank register is 8 bits long. At a reset, the program bank register (PCB) is set to "FFH" and other bank
registers are set to "00H".
The program bank register (PCB) is a read-only register and other bank registers are read and write
registers.
Reference:
For the operation of each bank register, see Section "3.1 Memory Space".
49
CHAPTER 3 CPU
3.3
General-purpose Register
The general-purpose register is a memory block allocated to addresses "000180H" to
"00037FH" in the internal RAM in bank units of 16 bits x 8. It is configured as follows:
• General-purpose 8-bit register (byte registers R0 to R7)
• 16-bit register (word registers RW0 to RW7)
• 32-bit register (long-word registers RL0 to RL7)
■ Configuration of General-purpose Register
General-purpose registers are provided as 32 banks in the internal RAM from "000180H" to "00037FH".
The banks that are used are set by the register bank pointer (RP). The current banks are indicated by
reading the register bank pointer (RP).
The register bank pointer (RP) determines the starting address of each bank as the following expression.
Starting address of general-purpose register = 000180H + RP × 10H
Figure 3.3-1 shows the allocation and configuration of the general-purpose register banks in memory space.
Figure 3.3-1 Allocation and Configuration of General-Purpose Register Banks in Memory Space
Internal RAM
:
000180 H Register bank 0
000190 H
Register bank 1
0001A0H
Register bank 2
0001B0H
Byte
address
0002B0H Register bank 19
0002C0H
Register bank 20
0002D0H
0002E0H Register bank 21
:
:
:
:
:
:
:
000360H
Register bank 30
000370H
Register bank 31
000380H
:
RP
14H
Byte
address
02C0H
RW0
02C1H
02C2H
RW1
02C3H
02C4H
RW2
02C5H
02C6H
02C7H
02C8H
RW3
R1
R0
02CAH
R2
R3
02CCH
R4
R5
02CBH RW5
02CDH RW6
02CEH
R6
R7
02CFH RW7
LSB
16bit
RL1
RL2
RL3
MSB
Conversion expression [000180H + RP × 10H]
R0 to R7
: Byte register
RW0 to RW7 : Word register
RL0 to RL3 : Long-word register
MSB : Most significant bit
LSB : Least significant bit
Note:
The register bank pointer (RP) is initialized to "00000B" by a reset.
50
02C9H RW4
RL0
CHAPTER 3 CPU
■ Register Bank
The register bank can be used as a general-purpose register (byte registers R0 to R7, word registers RW0 to
RW7, and long-word registers RL0 to RL3) to perform various operations or to serve as a pointer. The
long- word register can also be used as a linear addressing to directly access the entire memory space.
In the same way as ordinary RAM, the value in the general-purpose register is unchanged by a reset,
meaning that the state before the reset is held. However, at power-on, the value is undefined.
Table 3.3-1 shows the typical function of the general-purpose register.
Table 3.3-1 Typical Function of the General-purpose Register
Register Name
Function
R0 to R7
Used as operands for various instructions
Note: R0 can also be used as the barrel shift counter or the normalized instruction
counter.
RW0 to RW7
Used as addressing
Used as operands for various instructions
Note: RW0 can also be used as the string instruction counter.
RL0 to RL3
Used as linear addressing
Used as operands for various instructions
51
CHAPTER 3 CPU
3.4
Prefix Codes
When prefix code is inserted prior to an instruction, the operation of the instruction can
be changed partially. The prefix code has the following three types:
• Bank select prefix (PCB, DTB, ADB, and SPB)
• Common register bank prefix (CMR)
• Flag change inhibit prefix (NCC)
■ Prefix Code
● Bank select prefix (PCB, DTB, ADB, and SPB)
When the bank select prefix (PCB, DTB, ADB, SPB) codes precede an instruction, any memory space to
be accessed by the instruction can be selected, regardless of the addressing types.
● Common register bank prefix (CMR)
When the common register bank prefix (CMR) code precedes an instruction for accessing a generalpurpose register, the general-purpose register to be accessed by the instruction can be changed to a common
bank (register bank selected when the register bank pointer (RP) is "0") at "000180H" to "00018FH",
regardless of the current value of the register bank pointer (RP).
● Flag change inhibit prefix (NCC)
When the flag change inhibit (NCC) code precedes an instruction for changing various flags of the
condition code register (CCR), a flag change with instruction execution can be inhibited.
52
CHAPTER 3 CPU
3.4.1
Bank Select Prefix (PCB, DTB, ADB, and SPB)
When the bank select prefix (PCB, DTB, ADB, SPB) codes precede an instruction, any
memory space accessed by the instruction can be set, regardless of the addressing
types.
■ Bank Select Prefix (PCB, DTB, ADB, SPB)
Memory space used at data access is predetermined for each addressing type. However, when the bank
select prefix (PCB, DTB, ADB, SPB) codes precede an instruction statement, any memory space accessed
by the instruction statement can be set, regardless of the addressing types. Table 3.4-1 shows the bank
select prefix code and the memory space to be selected.
Table 3.4-1 Bank Select Prefix
Bank Select Prefix
Selected Space
PCB
Program space
DTB
Data space
ADB
Additional space
SPB
When the stack flag (CCR: S) is "0", user stack space is selected.
When the stack flag is "1", system stack space is selected.
The use of the bank select prefix (PCB, DTB, ADB, SPB) codes causes some instructions to perform
exceptional operations as explained below.
Table 3.4-2 shows the instructions not affected by the bank select prefix code, and Table 3.4-3 shows the
instructions requiring precaution when using the bank select prefix.
53
CHAPTER 3 CPU
Table 3.4-2 Instructions Unaffected by Bank Select Prefix
Instruction Type
Instruction
Effect
String instruction
MOVS
SCEQ
FILS
MOVSW
SCWEQ
FILSW
The bank register specified for the operand
is used irrespective of the presence or
absence of the bank select prefix code.
Stack instruction
PUSHW
POPW
Irrespective of the presence or absence of the
bank select prefix code, the user stack bank
(USB) is used when the S flag is "0"; and the
system stack bank (SSB) is used when the S
flag is "1".
I/O access instruction
MOV A,io
MOVX A, io
The I/O space ("000000H" to "0000FFH") is
accessed irrespective of the presence or
absence of the bank select prefix code.
MOVW A,io
Interrupt return
instruction
MOV io,A
MOVW io,A
MOV io,#imm8
MOVW io,#imm16
MOVB A,io:bp
MOVB io:bp,A
SETB io:bp
CLRB io:bp
BBC io:bp,rel
BBS io:bp,rel
WBTC io,bp
WBTS io:bp
The system stack bank (SSB) is used
irrespective of the presence or absence of the
bank select prefix code.
RETI
Table 3.4-3 Instructions Requiring Precaution When Using Bank Select Prefix
Instruction Type
Instruction
Explanation
Flag change
instruction
AND
OR
CCR,#imm8
CCR,#imm8
The bank select prefix code affects up to the next
instruction.
ILM setting
instruction
MOV
ILM,#imm8
The bank select prefix code affects up to the next
instruction.
PS return instruction
POPW
PS
Do not add the bank select prefix code to the PS
return instruction.
54
CHAPTER 3 CPU
3.4.2
Common Register Bank Prefix (CMR)
When the common register bank prefix (CMR) code precedes an instruction for
accessing a general-purpose register, the general-purpose register to be accessed by
the instruction can be changed to a common bank register bank selected when the
register bank pointer (RP) is "0" at "000180H" to "00018FH", regardless of the current
value of the register bank pointer (RP).
■ Common Register Bank Prefix (CMR)
The F2MC-16LX family provides common banks at "000180H" to "00018FH" as register banks that can be
commonly accessed by each task, regardless of the values of the register bank pointer (RP).
The use of the common banks facilitates data exchange between two or more tasks.
When the common register bank prefix (CMR) code precedes an instruction for accessing a generalpurpose register, the general-purpose register accessed by the instruction can be changed to a common bank
(register bank to be selected when the register bank pointer (RP) is "0") at "000180H" to "00018FH",
regardless of the current value of the register bank pointer (RP).
Table 3.4-4 shows the instructions requiring care when using the common register bank prefix.
Table 3.4-4 Instructions Requiring Precaution When Using Common Register Bank Prefix (CMR)
Instruction Type
Instruction
Explanation
String instruction
MOVS
SCEQ
FILS
MOVSW
SCWEQ
FILSW
Do not add the CMR code to string instructions.
Flag change
instruction
AND
OR
CCR,#imm8
CCR,#imm8
The CMR code affects up to the next instruction.
PS return instruction
POPW
PS
The CMR code affects up to the next instruction.
ILM setting
instruction
MOV
ILM,#imm8
The CMR code affects up to the next instruction.
55
CHAPTER 3 CPU
3.4.3
Flag Change Inhibit Prefix (NCC)
When the flag change inhibit prefix (NCC) code precedes an instruction for changing
various flags of the condition code register (CCR), a flag change caused by instruction
execution can be inhibited.
■ Flag Change Inhibit Prefix (NCC)
The flag change inhibit prefix (NCC) code is used to inhibit an unnecessary flag change.
When the flag change inhibit prefix (NCC) code precedes an instruction for changing various flags of the
condition code register (CCR), a flag change caused by instruction execution can be inhibited. The
inhibited flags are:
• Sticky-bit flag (CCR: T)
• Negative flag (CCR: N)
• Zero flag (CCR: Z)
• Overflow flag (CCR: V)
• Carry flag (CCR: C)
Table 3.4-5 shows the instructions requiring precaution when using the flag change inhibit prefix.
Table 3.4-5 Instructions Requiring Precaution When Using Flag Change Inhibit Prefix (NCC)
Instruction Type
Instruction
Explanation
Do not add the NCC code to the string instruction.
String instruction
MOVS
SCEQ
FILS
Flag change
instruction
AND CCR,#imm8
OR CCR,#imm8
The CCR changes by execution of an instruction,
regardless of the presence or absence of the NCC
code.
The NCC code affects the next instruction.
PS return instruction
POPW PS
The CCR changes by execution of an instruction,
regardless of the presence or absence of the NCC
code.
The NCC code affects the next instruction.
ILM setting
instruction
MOV ILM,#imm8
The NCC code affects the next instruction.
Interrupt instruction
Interrupt return
instruction
INT #vct8
INT
addr16
RETI
Context
switch instruction
JCTX @ A
56
MOVSW
SCWEQ
FILSW
INT9
INTP
addr24
The CCR changes by execution of an instruction
statement, regardless of the presence or absence of
the NCC code.
The CCR changes by execution of an instruction
statement, regardless of the presence or absence of
the NCC code.
CHAPTER 3 CPU
3.4.4
Restrictions on Prefix Code
The use of the prefix codes is restricted as follows:
• No interrupt request is accepted during execution of a prefix code and interrupt
inhibit instruction.
• When a prefix code precedes an interrupt inhibit instruction, the effect of the prefix
code is delayed.
• When conflicting prefix codes are used in succession, the last prefix code is enabled.
■ Prefix Code and Interrupt Inhibit Instruction
The interrupt inhibit instruction and prefix code are restricted as shown below.
Table 3.4-6 Prefix Code and Interrupt Inhibit Instruction
Prefix Code
Instruction that does not
accept interrupt request
PCB
DTB
ADB
SPB
CMR
NCC
Interrupt/Hold Inhibit Instruction
(instruction that delays effect of prefix code)
MOV
OR
AND
POPW
ILM,#imm8
CCR,#imm8
CCR,#imm8
PS
● Interrupt Inhibition
Even if an interrupt request is generated, it is not accepted during execution of a prefix code and interrupt
inhibit instruction. When other instructions are executed after execution of a prefix code and interrupt
inhibit instruction, an interrupt is processed.
Figure 3.4-1 Interrupt Inhibition
Interrupt inhibit instruction
. . . . . . . . . . . . . . .
Interrupt request generated
(a)
Interrupt accepted
. . .
(a) Ordinary
instruction
57
CHAPTER 3 CPU
● Delay of the effect of the prefix code
When a prefix code precedes an interrupt inhibit instruction, it affects an instruction next to the interrupt
inhibit instruction.
Figure 3.4-2 Interrupt Inhibit Instruction and Prefix Code
Interrupt inhibit instruction
MOV A,FFH
NCC
. . . .
MOV ILM,#imm8
ADD A,01H
CCR: XXX10XXB
CCR: XXX10XXB
CCR does not change by the NCC.
■ Array of Prefix Codes
For array of conflicting prefix codes (PCB, ADB, DTB, SPB), the last one is enabled.
Figure 3.4-3 Array of Prefix Codes
Prefix codes
...
ADB
DTB
PCB
ADD A,01H
...
PCB is valid for the prefix code.
58
CHAPTER 3 CPU
3.5
Interrupt
The F2MC-16LX family has four interrupt functions for suspending the current
processing to transfer control to a program which is defined separately at generation of
event.
• Hardware interrupt
• Software interrupt
• Interrupts by extended intelligent I/O service (EI2OS)
• Exception processing
■ Type and Function of Interrupt
● Hardware interrupt
This transits control to the interrupt processing program defined by user in response to the interrupt request
from resources.
● Software interrupt
This transfers control to the interrupt processing program defined by user by executing an instruction (such
as INT instruction) dedicated to the software interrupt.
● Interrupt by extended intelligent I/O service (EI2OS)
The extended intelligent I/O service (EI2OS) provides automatic data transfer between resources and
memory. Data can be transferred just by creating the startup-setting program and end program of the
EI2OS. At completion of data transfer, the interrupt processing program is executed automatically.
An interrupt generated by the EI2OS is a type of the above hardware interrupt.
● Exception processing
If an exception (execution of an undefined instruction) is detected among instructions, ordinary processing
is suspended to perform exception processing. This is equivalent to the above software interrupt instruction
INT10.
59
CHAPTER 3 CPU
■ Interrupt Operation
Figure 3.5-1 shows interrupt start and return processing.
Figure 3.5-1 General Flow of Interrupt Operation
START
Main program
YES
Interrupt request
enabled?
Executing of
string instruction*
Interrupt start/return processing
NO
Start EI2OS?
Fetch and decode
next instruction
YES
EI2OS
NO
YES
INT instruction?
NO
EI2OS processing
Software
interrupt/
exception
processing
Save dedicated registers
to system stack
Hardware
interrupt
Disable acceptance of
hardware interrupt (I = 0)
Specified count
YES ended? Or termination
request from
resource?
Save dedicated registers
to system stack
Updating of CPU interrupt
processing level (ILM)
YES
RETI instruction?
NO
Executing of
ordinary instruction
NO
Return to
processing
due to interrupt
Dedicated registers from
system stack return, and return
to previous processing which
is the one before calling
interrupt processing
Read interrupt vector,
update PC and PCB,
and branch to
interrupt processing
Repetitive execution
of string* instruction
completed?
YES
Move pointer to next
instruction by updating PC
*:
60
Interrupt determination is performed by the step during execution of string instruction
NO
CHAPTER 3 CPU
3.5.1
Interrupt Factor and Interrupt Vector
The F2MC-16LX family has vector tables corresponding to 256 types of interrupt factor.
■ Interrupt Vector
The interrupt vector tables referenced at interrupt processing are allocated to the most significant addresses
("FFFC00H" to "FFFFFFH") of the memory area. The interrupt vectors share the same area with the EI2OS,
exception processing, and hardware and software interrupts.
• Interrupts (INT0 to INT255) are used as software interrupts.
• At hardware interrupts, the interrupt vectors and interrupt control register (ICR) are fixed for each
resource.
Table 3.5-1 shows the interrupt number and allocation of interrupt vector.
Table 3.5-1 List of Interrupt Vectors
Software
Interrupt
Instruction
Vector
Address
(Low)
Vector
Address
(Middle)
Vector
Address
(High)
Mode
Data
Interrupt
Number
Hardware Interrupt
INT0
FFFFFCH
FFFFFDH
FFFFFEH
Unused
#0
None
:
:
:
:
:
:
:
INT7
FFFFE0H
FFFFE1H
FFFFE2H
Unused
#7
None
INT8
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDFH
#8
(RESET vector)
INT9
FFFFD8H
FFFFD9H
FFFFDAH
Unused
#9
None
INT10
FFFFD4H
FFFFD5H
FFFFD6H
Unused
#10
<Exception processing>
INT11
FFFFD0H
FFFFD1H
FFFFD2H
Unused
#11
Resource interrupt #0
INT12
FFFFCCH
FFFFCDH
FFFFCEH
Unused
#12
Resource interrupt #1
INT13
FFFFC8H
FFFFC9H
FFFFCAH
Unused
#13
Resource interrupt #2
INT14
FFFFC4H
FFFFC5H
FFFFC6H
Unused
#14
Resource interrupt #3
:
:
:
:
:
:
:
INT254
FFFC04H
FFFC05H
FFFC06H
Unused
#254
None
INT255
FFFC00H
FFFC01H
FFFC02H
Unused
#255
None
Reference:
It is recommended to set the unused interrupt vectors to the addresses for exception processing.
61
CHAPTER 3 CPU
■ Interrupt Factor, Interrupt Vector, and Interrupt Control Register
Table 3.5-2 shows the relationships between the interrupt factor except software interrupt, interrupt vector,
and interrupt control register.
Table 3.5-2 Interrupt Factor, Interrupt Vector, and Interrupt Control Register (1/2)
Interrupt Factor
EI2OSCorrespo
nded
Interrupt Vector
Number
Interrupt Control
Register
Address
ICR
Address
Reset
X
#08
08H
FFFFDCH
−
−
INT9 instruction
X
#09
09H
FFFFD8H
−
−
Exception processing
X
#10
0AH
FFFFD4H
−
−
CAN controller receive
completion (RX)
X
#11
0BH
FFFFD0H
ICR00
0000B0H(*1)
ICR01
0000B1H
ICR02
0000B2H(*3)
ICR03
0000B3H(*1)
ICR04
0000B4H
ICR05
0000B5H
ICR06
0000B6H(*1)
ICR07
0000B7H(*2)
ICR08
0000B8H(*1)
CAN controller transmit
completion (TX)/node status
transition (NS)
X
#12
0CH
FFFFCCH
Reserved
X
#13
0DH
FFFFC8H
Reserved
X
#14
0EH
FFFFC4H
#15
0FH
FFFFC0H
CAN wake-up
Timebase timer
X
16-bit reload timer 0
#16
10H
FFFFBCH
#17
11H
FFFFB8H
8-/10-bit A/D converter
#18
12H
FFFFB4H
16-bit free-run timer overflow
#19
13H
FFFFB0H
Reserved
X
#20
14H
FFFFACH
Reserved
X
#21
15H
FFFFA8H
PPG timer ch 0/1 underflow
X
#22
16H
FFFFA4H
#23
17H
FFFFA0H
Input capture 0 fetched
External interrupt (INT4/INT5)
#24
18H
FFFF9CH
Input capture 1 fetched
#25
19H
FFFF98H
PPG timer ch 2/3 underflow
External interrupt (INT6/INT7)
Watch timer
62
X
#26
1AH
FFFF94H
#27
1BH
FFFF90H
#28
1CH
FFFF8CH
Priority(*4)
Highest
CHAPTER 3 CPU
Table 3.5-2 Interrupt Factor, Interrupt Vector, and Interrupt Control Register (2/2)
Interrupt Factor
EI2OSCorrespo
nded
Interrupt Vector
Number
Address
Reserved
X
#29
1DH
FFFF88H
Input capture 2 fetched
Input capture 3 fetched
X
#30
1EH
FFFF84H
Reserved
X
#31
1FH
FFFF80H
Reserved
X
#32
20H
FFFF7CH
Reserved
X
#33
21H
FFFF78H
Reserved
X
#34
22H
FFFF74H
Reserved
X
#35
23H
FFFF70H
16-bit reload timer 1
O
#36
24H
FFFF6CH
UART1 receive
#37
25H
FFFF68H
UART1 transmit
#38
26H
FFFF64H
Reserved
X
#39
27H
FFFF60H
Reserved
X
#40
28H
FFFF5CH
Flash memory
X
#41
29H
FFFF58H
Delayed interrupt generation
module
X
#42
2AH
FFFF54H
Interrupt Control
Register
ICR
Address
ICR09
0000B9H
ICR10
0000BAH
ICR11
0000BBH
ICR12
0000BCH
ICR13
0000BDH(*1)
ICR14
0000BEH
ICR15
0000BFH(*1)
Priority(*4)
Lowest
O: Interrupt factor corresponds to EI2OS
X: Interrupt factor does not correspond to EI2OS
: Interrupt factor corresponds to EI2OS and has EI2OS stop function
: Interrupt factor can be used when not using interrupt sources sharing ICR register
*1:
• The interrupt level for resources sharing an ICR register become the same.
• When two resources share an ICR register, only one can use the EI2OS.
• When two resources share an ICR register and one specifies the EI2OS, the remaining resource cannot use the interrupt.
*2: The only input capture1 corresponds to the EI2OS function and the PPG does not correspond to the EI2OS function.
Therefore, if the EI2OS function is used by the input capture1, the PPG is set to disable generation of interrupt requests.
*3: The only CAN wake-up corresponds to the EI2OS function and the timebase timer dose not correspond to the EI2OS
function. Therefore, if the EI2OS function is used by the CAN wake-up, the timebase timer is set to disable generation
of interrupt requests.
*4: The priority is given when plural interrupts with the same level are generated simultaneously.
63
CHAPTER 3 CPU
3.5.2
Interrupt Control Registers and Resources
The interrupt control registers (ICR00 to ICR15) are allocated in the interrupt controller,
and correspond to all resources with interrupt functions. The registers control the
interrupt and extended intelligent I/O service (EI2OS).
■ Interrupt Control Register List
Table 3.5-3 lists the resources corresponding to the interrupt control registers.
Table 3.5-3 Interrupt Control Register List
64
Address
Register
Abbreviation
Corresponding Resource
0000B0H
Interrupt control register 00
ICR00
CAN controller
0000B1H
Interrupt control register 01
ICR01
Reserved
0000B2H
Interrupt control register 02
ICR02
CAN wake-up
Timebase timer
0000B3H
Interrupt control register 03
ICR03
16-bit reload timer 0
A/D converter
0000B4H
Interrupt control register 04
ICR04
16-bit free-run timer overflow
0000B5H
Interrupt control register 05
ICR05
PPG 0/1
0000B6H
Interrupt control register 06
ICR06
Input capture 0
External interrupt INT4/INT5
0000B7H
Interrupt control register 07
ICR07
Input capture 1
PPG 2/3
0000B8H
Interrupt control register 08
ICR08
External interrupt INT6/INT7
Watch timer
0000B9H
Interrupt control register 09
ICR09
Input capture 2/3
0000BAH
Interrupt control register 10
ICR10
Reserved
0000BBH
Interrupt control register 11
ICR11
Reserved
0000BCH
Interrupt control register 12
ICR12
16-bit reload timer 1
0000BDH
Interrupt control register 13
ICR13
UART1
0000BEH
Interrupt control register 14
ICR14
Reserved
0000BFH
Interrupt control register 15
ICR15
Flash memory, delayed interrupt
CHAPTER 3 CPU
The interrupt control register (ICR) has the following four functions.
Some functions of the interrupt control register (ICR) are different at write and read.
• Setting of interrupt level of corresponding resource
• Selection of whether to perform normal interrupt or EI2OS for corresponding resource
• Selection of channel of EI2OS
• Display of end state of EI2OS
Note:
Do not access the interrupt control register (ICR) using the read modify write (RMW) instruction
because it causes a malfunction.
65
CHAPTER 3 CPU
3.5.3
Interrupt Control Register (ICR00 to ICR15)
The functions of the interrupt control registers are shown below.
■ Interrupt Control Register (ICR00 to ICR15)
Part of functions differ depending on whether data is written to or read from the interrupt control registers.
Figure 3.5-2 Interrupt Control Register (ICR00 to ICR15) at Write
At write
7
6
5
4
3
2
1
0
Reset value
00000111B
W
W
W
W R/W R/W R/W R/W
bit 2 bit 1 bit 0
IL2 IL1 IL0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
bit 3
ISE
0
1
Interrupt level setting bits
Interrupt level 0 (highest)
Interrupt level 7 (no interrupt)
EI2OS enable bit
Starts normal interrupt processing at an interrupt
Starts EI2OS at an interrupt
bit 7 bit 6 bit 5 bit 4
ICS3 ICS2 ICS1 ICS0
R/W : Readable/Writable
W
: Write only
: Reset value
66
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EI2OS channel select bit
Channel
Descriptor address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
000100H
000108H
000110H
000118H
000120H
000128H
000130H
000138H
000140H
000148H
000150H
000158H
000160H
000168H
000170H
000178H
CHAPTER 3 CPU
Figure 3.5-3 Interrupt Control Register (ICR00 to ICR15) at Read
At read
7
6
5
4
⎯
⎯
R
R
3
2
1
0
Reset value
XX000111B
R/W R/W R/W R/W
bit 2 bit 1 bit 0
IL2 IL1 IL0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
bit 3
ISE
0
1
Interrupt level setting bits
Interrupt level 0 (highest)
Interrupt level 7 (no interrupt)
EI2OS enable bit
Starts normal interrupt processing at an interrupt
Starts EI2OS at an interrupt
bit 5 bit 4
R/W
W
⎯
X
:
:
:
:
:
Readable/Writable
Write only
Unused
Undefined
Reset value
S1
0
0
1
1
S0
0
1
0
1
EI2OS status bits
When EI2OS in operation or not started
Stop state by end of counting
Reserved
Stop state by request from resource
67
CHAPTER 3 CPU
3.5.4
Function of Interrupt Control Register
The interrupt control registers (ICR00 to ICR15) consist of the following bits with four
functions.
• Interrupt level setting bits (IL2 to IL0)
• EI2OS enable bit (ISE)
• EI2OS channel select bits (ICS3 to ICS0)
• EI2OS status bits (S1 and S0)
■ Bit Configuration of Interrupt Control Register (ICR)
The bit configuration of the interrupt control registers (ICR) is show below.
Figure 3.5-4 Configuration of Interrupt Control Register (ICR)
Configuration of interrupt control register (ICR) at write
bit 7
6
5
4
3
2
1
bit 0
ICS3
W
ICS2
W
ICS1
W
ICS0
W
ISE
W
IL2
W
IL1
W
IL0
W
Reset value
00000111B
Configuration of interrupt control register (ICR) at read
bit 7
6
5
4
3
2
1
bit 0
-
-
S1
R
S0
R
ISE
R
IL2
R
IL1
R
IL0
R
Reset value
XX000111B
R: Read only
W: Write only
-: Unused
References:
• The setting of the channel select bits (ICR: ICS3 to ICS0) is enabled only when starting the
EI2OS. When starting the EI2OS, set the EI2OS enable bit (ICR: ISE) to "1". When not starting the
EI2OS, set the bit to "0".
• The channel select bits (ICR: ICS3 to ICS0) are enabled only at write, and the EI2OS status bits
(ICR: S1, S0) are enabled only at read.
68
CHAPTER 3 CPU
■ Function of Interrupt Control Register
● Interrupt level setting bits (IL2 to IL0)
These bits set the interrupt levels of the corresponding resources. At reset, the bits are set to level 7 (IL2 to
IL0 = 111B: no interrupt).
Table 3.5-4 shows the relationship between the interrupt level setting bits and interrupt levels.
Table 3.5-4 Relationship between Interrupt Level Setting Bits and Interrupt Levels
IL2
IL1
IL0
Interrupt Level
0
0
0
0 (Highest)
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
6 (Lowest)
1
1
1
7 (No interrupt)
● EI2OS enable bit (ISE)
When an interrupt occurs with the ISE bit set to "1", the EI2OS is started. When an interrupt occurs with the
ISE bit set to "0", ordinary interrupt processing is started. If the EI2OS end condition is satisfied (when the
status bits S1 and S0 are not "00B"), the ISE bit is cleared. When the corresponding resources have no
EI2OS function, this bit must be set to "0" by the program. At reset, the ISE bit is set to "0".
● EI2OS channel select bits (ICS3 to ICS0)
These bits select EI2OS channels. The EI2OS descriptor addresses are set according to the setting values of
the ICS3 to ICS0 bits. At reset, the ICS3 to ICS0 are set to "0000B".
Table 3.5-5 shows the correspondence between the EI2OS channel select bits and descriptor addresses.
Table 3.5-5 Correspondence between EI2OS Channel Select Bits and Descriptor Addresses (1/2)
ICS3
ICS2
ICS1
ICS0
Channel to be Selected
Descriptor Address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
69
CHAPTER 3 CPU
Table 3.5-5 Correspondence between EI2OS Channel Select Bits and Descriptor Addresses (2/2)
ICS3
ICS2
ICS1
ICS0
Channel to be Selected
Descriptor Address
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
● EI2OS status bits (S1 and S0)
When the S1 and S0 bits are read at the termination of the EI2OS, the operating and end states can be
checked. At reset, the S1 and S0 bits are set to "00B".
Table 3.5-6 shows the relationship between the EI2OS status bits (ICR: S1, S0) and the EI2OS status.
Table 3.5-6 Relationships Between EI2OS Status Bits and EI2OS Status
70
S1
S0
0
0
When EI2OS in operation or not started
0
1
Stop state by end of counting
1
0
Reserved
1
1
Stop state by request from resource
EI2OS Status
CHAPTER 3 CPU
3.5.5
Hardware Interrupt
The hardware interrupt responds to the interrupt request from a resource, suspends the
current-executing program and transfers control to the interrupt processing program
defined by user.
The hardware interrupt corresponds to the EI2OS.
■ Hardware Interrupt
● Function of hardware interrupt
When a hardware interrupt is generated, the interrupt level (IR: IL) of an interrupt request from a resource
is compared with the interrupt level mask register (PS: ILM) and the state of the interrupt enable flag
(CCR: I) is referenced to determine whether to accept the hardware interrupt.
When the hardware interrupt is accepted, registers in the CPU are automatically saved in the system stack.
The interrupt level of the accepted interrupt is stored in the interrupt level mask register (ILM), then
branches to the corresponding interrupt vector.
● Multiple interrupts
Multiple hardware interrupts can be started.
● EI2OS
When the EI2OS function ends, normal interrupt processing is performed. No multiple EI2OSs are started.
Other interrupt requests and EI2OS requests are held during EI2OS processing.
● External interrupt
The external interrupt (wake-up interrupt included) is accepted as a hardware interrupt via the resource
(interrupt request detector).
● Interrupt vector
The interrupt vector tables referenced during interrupt processing are allocated to "FFFC00H" to
"FFFFFFH" in the memory and shared with software interrupts.
71
CHAPTER 3 CPU
■ Mechanism of Hardware Interrupt
The mechanism related to the hardware interrupt consists of the four sections.
When starting the hardware interrupt, these four sections must be set by the program.
Table 3.5-7 Mechanism Related to Hardware Interrupt
Mechanism Related to
Hardware Interrupt
Function
Resource
Interrupt enable bit, interrupt
request bit
Controls interrupt request from
resource
Interrupt controller
Interrupt control register (ICR)
Sets interrupt level and controls EI2OS
Interrupt enable flag (I)
Identifies interrupt enable state
Interrupt level mask register
(ILM)
Compares requested interrupt level and
current interrupt level
Microcode
Executes interrupt routine
Interrupt vector table
Stores branch destination address at
interrupt processing
CPU
"FFFC00H to
"FFFFFFH" in memory
■ Hardware Interrupt Inhibition
No hardware interrupt requests are inhibited under following conditions.
● Hardware interrupt inhibition during write to resource control register in I/O area
No hardware interrupt requests are accepted during write to resource control register. This prevents the
CPU from malfunctioning with respect to interrupt requests generated during rewrite related to interrupt
control registers of each resource.
Figure 3.5-5 shows the hardware interrupt operation during write to the resource control register.
Figure 3.5-5 Hardware Interrupt Request During Write to the Resource Control Register
Write instruction to resource control register
. . . . .
MOV A,#08
MOV io,A
Interrupt request
generated here
72
MOV A,2000H
Does not transit to
interrupt processing
Interrupt processing
Transits to interrupt
processing
CHAPTER 3 CPU
● Hardware interrupt inhibition by interrupt inhibit instruction
Table 3.5-8 shows the hardware interrupt inhibit instructions.
If a hardware interrupt is generated during execution of a hardware interrupt inhibit instruction, it is
processed after execution of the hardware interrupt inhibit instruction, then and other instruction.
Table 3.5-8 Hardware Interrupt Inhibit Instructions
Prefix code
Instruction that does not
accept interrupt request
PCB
DTB
ADB
SPB
CMR
NCC
Interrupt Inhibit Instruction
MOV
OR
AND
POPW
ILM,#imm8
CCR,#imm8
CCR,#imm8
PS
● Hardware interrupt inhibition during execution of software interrupt
When a software interrupt is started, the interrupt enable flag (CCR: I) is cleared to "0" and the interrupt is
disabled.
73
CHAPTER 3 CPU
3.5.6
Operation of Hardware Interrupt
The operation from the generation of hardware interrupt request to the completion of
interrupt processing is explained below.
■ Start of Hardware Interrupt
● Operation of resource (generation of interrupt request)
The resources with a hardware interrupt request function have an interrupt request flag indicating the
generation of an interrupt request, as well as an interrupt enable flag selecting between enabling and
disabling an interrupt request. The interrupt request flag is set when events inherent to resources occur.
When the interrupt enable flag is set to "enabled", an interrupt request is generated to the interrupt
controller.
● Operation of interrupt controller (control of interrupt request)
The interrupt controller compares the interrupt level (ICR: IL2 to IL0) of simultaneously generated
interrupt requests, selects the request with the highest level (with the smallest IL setting value), and posts it
to the CPU. If there are two or more interrupt requests with the same level, the interrupt request with the
smallest interrupt number is preferred.
● Operation of CPU (interrupt request acceptance and interrupt processing)
The CPU compares the received interrupt level (ICR: IL2 to IL0) with the value of the interrupt level mask
register (ILM) and generates an interrupt processing microcode after end of the current instruction
execution if the interrupt level (IL) is smaller than the value of the interrupt level mask register (ILM) and
an interrupt is enabled (CCR: I = 1).
The EI2OS enable bit (ICR: ISE) is referenced at the beginning of the interrupt processing microcode.
When the EI2OS enable bit (ICR: ISE) is set to "0", ordinary interrupt processing is performed. If the bit is
set to "1", the EI2OS starts.
At interrupt processing, the values of the dedicated registers (A, DPR, ADB, DTB, PCB, PC and PS) are
saved in the system stack (system stack space indicated by SSB and SSP) first.
Next, the address of the vector table corresponding to the generated interrupt is loaded to the program
counter (PCB, PC), the interrupt level mask register (ILM) is updated, and the stack flag (CCR: S) is set to
"1".
■ Return from Hardware Interrupt
When the interrupt processing program clears the interrupt request flag in the resource that causes the
interrupt to execute the RETI instruction, the values of the dedicated registers saved in the system stack are
returned to each register and the operation returns to the processing executed before transition to interrupt
processing.
The interrupt request output to the interrupt controller by the resource is cleared by clearing the interrupt
request flag.
74
CHAPTER 3 CPU
■ Operation of Hardware Interrupt
Figure 3.5-6 shows the operation from the generation of hardware interrupt to the completion of interrupt
processing.
Figure 3.5-6 Operation of Hardware Interrupt
Internal bus
(7)
PS,PC . .
Microcode
F2MC-16LX
PS
IR
CPU
(6)
I
ILM
Comparator
Check
(5)
(4)
(3)
Other resources
..
.
Resource that generates the interrupt request
Enable FF
AND
Factor FF
(8)
Level
Interrupt
comparator level IL
(2)
(1)
Interrupt controller
RAM
IL
PS
I
ILM
IR
FF
:
:
:
:
:
:
Interrupt level setting bit of interrupt control register (ICR)
Processor status
Interrupt enable flag
Interrupt level mask register
Instruction register
Flip-flop
1. The resource generates an interrupt request.
2. When the interrupt enable bit in the resource is set to "enabled", the resource generates an interrupt
request to the interrupt controller.
3. The interrupt controller that is received the interrupt request determines the priority of interrupts
simultaneously requested and posts the interrupt level (IL) corresponding to the appropriate interrupt
request to the CPU.
4. The CPU compares the interrupt level (IL) requested from the interrupt controller with the value of the
interrupt level mask register (ILM).
5. If the interrupt request is preferred to the interrupt level mask register (ILM), the interrupt enable flag
(CCR: I) is checked.
6. When an interrupt is enabled by the interrupt enable flag (CCR: I = 1), the requested interrupt level (IL)
is set to the interrupt level mask register (ILM) after completion of the current instruction execution.
7. The values of the dedicated registers are saved, and processing transits to interrupt processing.
8. The program clears the interrupt request generated from the resource and executes the interrupt return
instruction (RETI) to terminate interrupt processing.
75
CHAPTER 3 CPU
3.5.7
Procedure for Use of Hardware Interrupt
The settings of the system stack area, resources, interrupt control registers (ICR) are
required for using the hardware interrupt.
■ Procedure for Use of Hardware Interrupt
Figure 3.5-7 shows an example of the procedure for use of the hardware interrupt.
Figure 3.5-7 Procedure for Use of Hardware Interrupt
Start
(1)
Set system stack area
(2)
Set interrupt of resource
(3)
Set ICR in
interrupt controller
(4)
Set resource to start
operation and interrupt
enable bit to "enabled"
(5)
Interrupt processing program
Stack processing and
(8)
branching to interrupt vector
(7)
Processing
by hardware
Set ILM and I in PS
(9)
Processing interrupt
to resource
(Execute the interruptprocessing)
Clear interrupt request
(10) Execute interrupt return instruction (RETI)
Main program
(6)
Interrupt request generated
Main program
1. Set the system stack area.
2. Set an interrupt of the resource with the interrupt request function.
3. Set the interrupt control register (ICR) in the interrupt controller.
4. Set the resource to start operation and the interrupt enable bit to "enabled".
5. Set the interrupt level mask register (ILM) and the interrupt enable flag (CCR: I) ready to accept an
interrupt (CCR: I = 1).
6. An interrupt generated from the resource generates a hardware interrupt request.
7. The interrupt controller saves data in the dedicated registers, and processing transits to interrupt
processing.
8. Execute the program for interrupt generation at interrupt processing.
9. Clear the interrupt request from the resource.
10.Execute the interrupt return instruction (RETI) to return to the program executed before transition to
interrupt processing.
76
CHAPTER 3 CPU
3.5.8
Multiple Interrupts
Multiple hardware interrupts can be generated by setting different interrupt levels in the
interrupt level setting bits of the interrupt control register (ICR: ILO to IL2) in response
to plural interrupt requests from the resource. However, multiple EI2OS cannot be
started.
■ Multiple Interrupts
● Operation of multiple interrupts
If an interrupt request with a higher priority than the interrupt level of the current interrupt processing is
generated during interrupt processing, the current interrupt processing is suspended to accept the generated
higher-level interrupt request. When the higher-level interrupt processing is terminated, the suspended
interrupt processing is resumed. The interrupt level (IL) can be set to "0" to "7". The interrupt request set to
level 7 is never accepted.
If an interrupt request with a priority equal to or lower than the interrupt level of the current-executing
interrupt is generated during interrupt processing, unless the setting of the interrupt enable flag (CCR: I) or
the interrupt level mask register (ILM) is changed, the new interrupt request is held until the current
interrupt processing is completed.
Starting of multiple interrupts generated during interrupt processing can be disabled temporarily by setting
the interrupt enable flag (CCR: I) to "disabled" (CCR: 1= 0) or the interrupt level mask register (ILM) to
"disabled" (ILM = 000).
Note:
Multiple EI2OS cannot be started. During EI2OS processing, other interrupt requests and other
EI2OS requests are all held.
77
CHAPTER 3 CPU
● Example of multiple interrupts
As an example of multiple interrupt processing, assuming that a timer interrupt is preferred to an A/D
converter interrupt, set the interrupt level of the A/D converter to "2" and the interrupt level of the timer to
"1". Figure 3.5-8 shows the processing of the timer interrupt generated during processing of the A/D converter
interrupt.
Figure 3.5-8 Example of Multiple Interrupts
Main program
(ILM = "111B")
Set interrupt
A/D interrupt
generated
A/D Interrupt processing (ILM = "010B")
Interrupt level 2
Timer interrupt processing (ILM = "001B")
(IL = "010B")
(1)
Interrupt level 1
(IL = "001B")
(3) Timer interrupt
(2)
generated
(4) Timer interrupt
Suspended
processing
Resumed
Resumption of (8)
main processing
(6) A/D interrupt processing
(5) Return from timer
interrupt
(7) Return from A/D interrupt
• When processing of the A/D converter interrupt is started, the interrupt level mask register (ILM) is
automatically set to the value ("2" in example) of the interrupt level (ICR: IL2 to IL0) of the A/D
converter. When an interrupt request with an interrupt level of 1 or 0 is generated under this condition,
processing the generated interrupt is preferred.
• When the interrupt return instruction (RETI) is executed after the completion of interrupt processing, the
values of the dedicated registers (A, DPR, ADB, DTB, PCB, PC, PS) saved in the system stack are
returned to each register and the interrupt level mask register (ILM) is returned to the value before
interrupt processing was suspended.
78
CHAPTER 3 CPU
3.5.9
Software Interrupt
The software interrupt is a function for transiting control from the current-executing
program to the interrupt processing program defined by user by execution of a software
interrupt instruction (INT instruction). The hardware interrupt is held during execution
of a software interrupt.
■ Start and Operation of Software Interrupt
● Start of software interrupt
A software interrupt is started by executing the INT instruction. It does not have an interrupt request flag or
an interrupt enable flag. An interrupt request is generated immediately after the INT instruction is executed.
● Hardware interrupt inhibition
Interrupts by the INT instruction have no interrupt level and the interrupt level mask register (ILM) is not
updated. During execution of the INT instruction, the interrupt enable flag (CCR: I) is set to "0" and a
hardware interrupt is masked.
When enabling a hardware interrupt during software interrupt processing, set the interrupt enable flag
(CCR: I) to "1" during software interrupt processing.
● Operation of software interrupt
When the INT instruction is executed, the software interrupt processing microcode in the CPU is started.
The software interrupt processing microcode saves the values of the dedicated registers in the system stack;
branching to the address of the corresponding interrupt vector table after a hardware interrupt is masked
(CCR: I = 0).
■ Return from Software Interrupt
When the interrupt return instruction (RETI) is executed in the interrupt processing program, the values of
the dedicated registers saved in the system stack are returned to each register and the operation is returned
to the processing performed before branching to interrupt processing.
Note:
When the program bank register (PCB) is "FFH", the vector area for the CALLV instruction overlaps
the table for the INT #vct8 instruction. A CALLV and INT #vct8 instructions can not use the same
address in creating a software.
79
CHAPTER 3 CPU
3.5.10
Interrupt by EI2OS
EI2OS is a function to automatically transfer data between the resources (I/O) and
memory. It generates the hardware interrupt at termination of data transfer.
■ EI2OS
The EI2OS provides automatic data transfer between the I/O area and memory. When data transfer is
terminated, the termination factor (end condition) is set, branching automatically to the interrupt processing
routine. Data can be transferred just by creating a setup program for starting the EI2OS and an end
program.
● Advantages of EI2OS
Compared to data transfer using the interrupt-processing routine, EI2OS has the following advantages.
• Since the creation of transfer program is not required, the program size can be reduced.
• The transfer count can be set to prevent transfer of unnecessary data.
• Whether to update the buffer address pointer can be specified.
• Whether to update the I/O address pointer can be specified.
● Interrupt by EI2OS termination
At completion of data transfer by the EI2OS, the end condition is set in the EI2OS status bits (ICR: S1, S0),
and then the processing automatically transits to interrupt processing.
The EI2OS termination factor can be determined by checking the EI2OS status bits (ICR: S1, S0) using the
interrupt processing program.
● Interrupt control register (ICR)
This register is within the interrupt controller, and displays the states at starting, setting channel, and
terminating the EI2OS.
● EI2OS descriptor (ISD)
The EI2OS descriptor (ISD), which is allocated between "000100H" and "00017FH" in internal RAM, is 8byte data that is used to set the transfer mode, addresses, transfer count and buffer addresses. It has 16
channels, and a channel number is allocated to each of these channels by the interrupt control register
(ICR).
Note:
The CPU stops while the EI2OS is in operation.
80
CHAPTER 3 CPU
■ Operation of EI2OS
Figure 3.5-9 shows the operation of the EI2OS.
Figure 3.5-9 Operation of EI2OS
Memory space
By IOA
I/O area
00 bank area
(5)
CPU
(2)
(3)
Interrupt request
(1)
By ICS
ISD
Interrupt control register (ICR)
(3)
Interrupt controller
By BAP
(4)
ISD
IOA
BAP
ICS
DCT
:
:
:
:
:
Buffer
Count by DCT
EI2OS descriptor
I/O address pointer
Buffer address pointer
EI2OS channel select bit of ICR
Data counter
1. An interrupt request is generated and the EI2OS is started.
2. The interrupt controller selects the EI2OS descriptor.
3. The transfer-source and transfer-destination address pointers are read from the EI2OS descriptor.
4. Data is transferred according to the transfer-source and transfer-destination address pointers.
5. An interrupt factor is cleared automatically.
81
CHAPTER 3 CPU
3.5.11
EI2OS Descriptor (ISD)
The EI2OS descriptor (ISD) is allocated to the addresses "000100H" to "00017FH" in the
internal RAM, and consists of 8 bytes × 16 channels.
■ Configuration of EI2OS Descriptor (ISD)
ISD consists of 8 bytes × 16 channels, and each ISD is composed as shown in Figure 3.5-10. Table 3.5-9
shows the correspondence between the channel number and ISD address.
Figure 3.5-10 Configuration of EI2OS Descriptor (ISD)
MSB
Higher 8 bits of data counter (DCTH)
LSB
H
Lower 8 bits of data counter (DCTL)
Higher 8 bits of I/O address pointer (IOAH)
Lower 8 bits of I/O address pointer (IOAL)
EI2O status register (ISCS)
Higher 8 bits of buffer address pointer (BAPH)
Middle 8 bits of buffer address pointer (BAPM)
ISD starting address
(000100H + 8 × ICS)
Lower 8 bits of buffer address pointer (BAPL)
ICS: EI2OS channel select bit (ICR: ICS3 to ICS0)
82
L
CHAPTER 3 CPU
Table 3.5-9 EI2OS Descriptor (ISD) Area
Channel
(ICR: ICS3 to ICS0)
Descriptor Starting Address
0
000100H
1
000108H
2
000110H
3
000118H
4
000120H
5
000128H
6
000130H
7
000138H
8
000140H
9
000148H
10
000150H
11
000158H
12
000160H
13
000168H
14
000170H
15
000178H
83
CHAPTER 3 CPU
Each Register of EI2OS Descriptor (ISD)
3.5.12
The EI2OS descriptor (ISD) consists of the following registers.
• Data counter (DCT)
• I/O address pointer (IOA)
• EI2OS status register (ISCS)
• Buffer address pointer (BAP)
The reset value of each register is undefined and a reset should be performed carefully.
■ Data Counter (DCT)
The data counter (DCT) is a 16-bit register, and corresponds to the transfer data count. It decrements by
one each time data is transferred. When the data counter (DCT) reaches 0, the EI2OS is terminated and then
the processing transits to interrupt processing.
Figure 3.5-11 shows the bit configuration of the data counter (DCT).
Figure 3.5-11 Configuration of Data Counter (DCT)
DCTL
DCTH
bit 15 14
13
12
11
10
9
bit 8 bit 7
6
5
4
3
2
1
bit 0
DCT B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00
Reset value
XXXXXXXX XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable/Writable
X
: Undefined
■ I/O Address Pointer (IOA)
The I/O address pointer (IOA) is a 16-bit register that sets the low addresses (A15 to A0) of the 00 bank
area where data is transferred to or from the buffer. The high addresses (A23 to A16) are set all to "0" and
the area between "000000H" and "00FFFFH" can be addressed.
Figure 3.5-12 shows the bit configuration of I/O address pointer (IOA).
Figure 3.5-12 Configuration of I/O Address Pointer (IOA)
IOAL
IOAH
bit 15 14
IOA
13
12
11
10
9
bit 8 bit 7
6
5
4
3
2
1
bit 0
A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable/Writable
X
: Undefined
84
Reset value
XXXXXXXX XXXXXXXXB
CHAPTER 3 CPU
■ EI2OS Status Register (ISCS)
The EI2OS status register (ISCS) is an 8-bit register that sets the method to update the buffer address
pointer and I/O address pointer, transfer data format (byte/word), and transfer direction.
Figure 3.5-13 shows the bit configuration of the EI2OS status register (ISCS).
Figure 3.5-13 Configuration of EI2OS Status Register (ISCS)
7
6
5
4
3
2
1
0
Reset value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
SE
0
1
EI2OS termination control bit
Not terminated by a request from resource
Terminated by a request from resource
bit 1
DIR
0
1
Data transfer direction specify bit
I/O address pointer → Buffer address pointer
Buffer address pointer → I/O address pointer
bit 2
BF
0
1
BAP updating/fixing select bit
Buffer address pointer updated after data transfer *1
Buffer address pointer not updated after data transfer
bit 3
BW
0
1
Byte
Word
bit 4
IF
0
1
Transfer data length specify bit
IOA updating/fixing select bit
I/O address pointer updated after data transfer *2
I/O address pointer not updated after data transfer
bit 7 bit 6 bit 5
Reserved Reserved Reserved
R/W
X
*1
*2
:
:
:
:
0
0
0
Reserved bits
Always write 0
Readable/Writable
Undefined
The buffer address pointer changes only in lower 16 bits, and can only be incremented.
I/O address pointer can only be incremented.
85
CHAPTER 3 CPU
■ Buffer Address Pointer (BAP)
The buffer address pointer (BAP) is a 24-bit register and sets the 16-MB addresses where data is transferred
to or from I/O area. When the BAP updating/fixing select bit of the EI2OS status register (ISCS: BF) is set
to "updated", the buffer address pointer (BAP) changes only in the lower 16 bits (BAPH, BAPL) and does
not change in the higher 8 bits (BAPH). Figure 3.5-14 shows the bit configuration of the buffer address
pointer (BAP).
Figure 3.5-14 Configuration of Buffer Address Pointer (BAP)
bit 23
BAP
bit 16 bit 15
BAPH
R/W
bit 8 bit 7
bit 0
BAPM
BAPL
R/W
R/W
Reset value
XXXXXX H
R/W : Readable/Writable
X
: Undefined
References:
• The area that can be set by the I/O address pointer (IOA) is "000000H" to "00FFFFH".
• The area that can be set by the buffer address pointer (BAP) is "000000H" to "FFFFFFH".
• The maximum transfer count that can be set by the data counter (DCT) is "65,536".
86
CHAPTER 3 CPU
3.5.13
Operation of EI2OS
The flowchart of operation of the EI2OS using the microcode in the CPU is shown
below:
■ Operation of EI2OS
Figure 3.5-15 Flowchart of Operation of EI2OS
Interrupt request
generated from resource
NO
ISE = 1
YES
Read ISD/ISCS
Interrupt processing
Termination
request from
resource?
YES
NO
YES
Address set to BAP
(Data transfer)
(Data transfer)
Address set to BAP
IF=0?
NO
Address set to IOA
YES
Updating value
depends on BW
IOA updated
YES
BF = 0?
NO
YES
SE = 1?
NO
DIR = 1?
NO
Address set to IOA
: EI2OS descriptor
: EI2OS status register
: IOA updating/fixing
select bit
BW
: Transfer data length
specify bit
BF
: BAP updating/fixing
select bit
DIR
: Data transfer direction
specify bit
SE
: EI2OS termination control
bit
DCT : Data counter
IOA
: I/O register address
pointer
BAP : Buffer address pointer
ISE
: EI2OS enable bit (ICR)
S1, S0 : EI2OS status (ICR)
ISD
ISCS
IF
Updating value
depends on BW
Decrement DCT
DCT = "00H"?
NO
Set S1 and S0 to "00B"
BAP updated
(-1)
YES
EI2OS termination processing
Set S1 and S0 to "01B"
Set S1 and S0 to "11B"
Clear resource
interrupt request
Clear ISE to "0"
Return of CPU operation
Interrupt processing
87
CHAPTER 3 CPU
3.5.14
Procedure for Use of EI2OS
The procedure for using the EI2OS is shown below:
■ Procedure for Use of EI2OS
Figure 3.5-16 Procedure for Use of EI2OS
Processing by software
Processing by hardware
Start
Initial Setting
Set system stack area
Set EI2OS descriptor
Set resource interrupt
Set interrupt control register
(ICR)
Set start operation of
internal resource and
interrupt enable bit
Set ILM and I in PS
S1, S0 = "00B"
Execute user program
(Interrupt request) and (ISE = 1)
Data transfer
Determine transition to interrupt
by specified times transfer
termination or termination
request from resources.
Transits to interrupt processing
Reset EI2OS
(channel switching)
Data processing in buffer
RETI
ISE
: EI2OS enable bit (ICR)
S1, S0 : EI2OS status (ICR)
88
YES
S1, S0 = "01B"or
S1, S0 = "11B"
NO
CHAPTER 3 CPU
3.5.15
EI2OS Processing Time
The time required for EI2OS processing depends on the following factors:
• Setting of EI2OS status register (ISCS)
• Data length of transfer data
Some interrupt handling time is required at the transition to hardware interrupt
processing after completion of data transfer.
■ EI2OS Processing Time (time for one transfer)
● At continuing data transfer (DCT
0, ISCS: SE=0)
The EI2OS processing time at continuing data transfer is determined by the setting of the EI2OS status
register (ISCS) as shown in Table 3.5-10.
Table 3.5-10 EI2OS Execution Time
Termination by
Termination Request
from Resource
Setting of EI2OS Termination
Control Bit (SE)
Setting of IOA Updating/Fixing
Select Bit (IF)
Setting of BAP address
updating/fixing select bit (BF)
Ignores Termination
Request from Resource
Fixed
Updated
Fixed
Updated
Fixed
32
34
33
35
Updated
34
36
35
37
Unit: Machine cycle (one machine cycle is equal to one clock cycle of the machine clock (φ).)
In addition, compensation is required depending on the conditions at executing EI2OS as shown in Table
3.5-11.
Table 3.5-11 Compensation Value for Data Transfer at EI2OS Processing Time
Internal Access
I/O Register Address Pointer
Buffer address pointer
Internal access
B/even
Odd
B/even
0
+2
Odd
+2
+4
B: Byte data transfer
Even: Word transfer at even address
Odd: Word transfer at odd address
89
CHAPTER 3 CPU
● At end of data counter (DCT) (DCT
0, ISCS: SE=0)
At completion of data transfer by the EI2OS, since the hardware interrupt is started, the interrupt handling
time is added. The EI2OS processing time at the end of counting is calculated by the following expression.
El2OS processing time at end of counting = El2OS processing time at continuing data transfer + (21 + 6 × Z)
machine cycles
Interrupt handling time
(Z: Compensation value of interrupt handling time)
The interrupt handling time depends on the address set by the stack pointer. Table 3.5-12 shows the
compensation value (Z) of the interrupt handling time.
Table 3.5-12 Compensation Value (Z) of Interrupt Handling Time
Address Set by Stack Pointer
Compensation Value (Z)
For internal area (even address)
0
For internal area (odd address)
+2
● At termination by termination request from resource (DCT
0, ISCS=1)
If data transfer by the EI2OS is terminated during its processing by the termination request from a resource
(ICR: S1, S0 = 11B), processing transits to interrupt processing. The EI2OS processing time at a
termination request from a resource is calculated as follows:
El2OS processing time at termination during processing = 36 + 6 × Z
machine cycles
(Z: Compensation value of interrupt handling time)
Reference:
One machine cycle is equal to one clock cycle of the machine clock (φ).
90
CHAPTER 3 CPU
3.5.16
Exception Processing Interrupt
The F2MC-16LX family performs exception processing when an undefined instruction is
executed.
Exception processing is basically the same as interrupt. When an exception is detected
between instructions, normal processing is suspended to perform exception
processing.
Exception processing is performed when an unexpected operation is performed, and
should be used only for starting recovery software at debugging or in an emergency.
■ Exception Processing
● Operation of exception processing
The F2MC-16LX family treats all instruction codes not defined in the instruction map as undefined
instructions. If an undefined instruction is executed, the processing equal to the software interrupt
instruction INT # 10 is performed.
At exception processing, the following processing is performed before the transition to interrupt
processing:
• The values of dedicated registers (A, DPR, ADB, DTB, PCB, PC, PS) saved to the system stack
• The interrupt enable flag (CCR: I) cleared to "0" and an interrupt disabled
• The stack flag (CCR: S) set to "1"
The value of the program counter (PC) saved in the stack is a value of the address where undefined
instructions are stored. For instruction codes of 2 bytes or more, the value of the program counter (PC) is a
value of the address where instruction codes that can be identified as undefined are stored. When the type
of exception factor must be determined at exception processing, use the saved program counter (PC).
● Return from exception processing
When the program counter (PC) indicates an undefined instruction, the interrupt return instruction (RETI)
from exception processing is executed to return to exception processing. Some measures such as
performing a software reset should be taken when returning from exception processing.
91
CHAPTER 3 CPU
3.5.17
Time Required to Start Interrupt Processing
The time for terminating the currently executing instruction plus the interrupt handling
time is required from generation of the hardware interrupt request to execution of the
interrupt-processing.
■ Time Required to Start Interrupt Processing
The interrupt request sampling wait time and the interrupt handling time (time required for preparation for
interrupt processing) are required from generation of the interrupt request and acceptance of interrupt, to
execution of the interrupt processing. Figure 3.5-17 shows the interrupt processing time.
Figure 3.5-17 Interrupt Processing Time
Operation of CPU
Execution of normal instruction
Interrupt request
sampling wait time
Interrupt wait time
Interrupt handling
Interrupt processing
Interrupt handling time
(θ machine cycle)*
Interrupt request generated
: Last instruction cycle where sampling interrupt request.
*
: One machine cycle is equal to one clock cycle of the machine clock (φ).
● Interrupt request sampling wait time
It indicates a time from the generation of the interrupt request to the termination of the currently executing
instruction.
Whether the interrupt request is generated or not is determined by sampling the interrupt request in the last
cycle of each instruction. The CPU cannot recognize the interrupt request during execution of each
instruction, as a result wait time occurs.
Reference:
The interrupt request sampling wait time is longest when the interrupt request is generated
immediately after starting execution of the POPW, RW0, …RW7 instructions with the longest
execution cycle (45 machine cycles).
92
CHAPTER 3 CPU
● Interrupt handling time (θ machine cycles)
The CPU requires an interrupt handling time of θ machine cycles to save the dedicated registers to the
system stack and fetch the interrupt vector table address after accepting the interrupt request. The interrupt
handling time (θ) is obtained using the following equations.
θ = 24 + 6 × Z machine cycles (Z: compensation value of interrupt handling time)
The interrupt handling time depends on the address set by the stack pointer. Table 3.5-13 shows the
compensation value (Z) of the interrupt handling time.
Table 3.5-13 Compensation Value (Z) of Interrupt Handling Time
Address Set by Stack Pointer
Compensation Value (Z)
For internal area (even address)
0
For internal area (odd address)
+2
Reference:
One machine cycle is equal to one clock cycle of the machine clock (φ).
93
CHAPTER 3 CPU
3.5.18
Stack Operation for Interrupt Processing
When an interrupt is accepted, the values of dedicated registers are automatically saved
to the system stack before transition to interrupt processing. At completion of interrupt
processing, the values of the dedicated registers are automatically returned from the
system stack.
■ Stack Operation at Starting Interrupt Processing
When an interrupt is accepted, the CPU automatically saves the values of the current-dedicated registers in
the system stack in the following order.
• Accumulator (AH, AL)
• Direct page register (DPR)
• Additional data bank register (ADB)
• Data bank register (DTB)
• Program bank register (PCB)
• Program counter (PC)
• Processor status (PS)
Figure 3.5-18 shows the stack operation at starting interrupt processing.
Figure 3.5-18 Stack Operation at Starting Interrupt Processing
Immediately before interrupt
SSB
00 H
SSP
08FEH
A
0000 H
AH
08F2H
08FEH
AL
DPR 01 H
ADB 00 H
00 H
PCB FF H
DTB
PC
803FH
PS
20E0H
Immediately after interrupt
Address Memory
XX H
XX H
XX H
XX H
XX H
XX H
XX H
XX H
XX H
XX H
XX H
XX H
08FEH
08FF H
Low
SSB
00 H
SSP
08F2H
A
0000H
AH
08F2H
08FEH
AL
DPR 01 H
ADB 00 H
00 H
PCB FF H
DTB
PC
803FH
PS
20E0H
SP
Byte
Address Memory
High
E0 H
20H
3F H
80H
FF H
00H
00H
01H
FEH
08H
00H
00H
08FEH
08FF H
SP after
updating
PS
PC
PCB
DTB
ADB
DPR
AL
AH
SP
Byte
■ Stack Operation at Return from Interrupt Processing
When the interrupt return instruction (RETI) is executed after completion of interrupt processing, the
values of the dedicated registers (PS, PC, PCB, DTB, ADB, DPR, AL, AH) are returned to each register
from the system stack, and the dedicated registers are returned to the state before interrupt processing was
started.
94
CHAPTER 3 CPU
3.5.19
Program Example of Interrupt Processing
This section gives a program example of interrupt processing.
■ Program Example of Interrupt Processing
● Processing specification
This is an example of interrupt program using external interrupt 4 (INT4).
● Coding example
DDR2
EQU 000012H
; Port 2 direction register
ENIR
EQU 030H
; Interrupt/DTP enable register
EIRR
EQU 031H
; Interrupt/DTP flag
ELVR
EQU 032H
; Request level setting register
ICR00
EQU 0B0H
; Interrupt control register
STACK
SSEG
; Stack
RW
100
STACK_T RW
1
STACK
ENDS
;-----Main program--------------------------------------------------------------CODE
CSEG
;
START:
MOV RP,#0
; The general-purpose register uses the starting bank.
MOV ILM,#07H
; ILM in PS set to level 7
MOV A,#!STACK_T
; System stack set
MOV SSB,A
MOVW A,#STACK_T
; Stack pointer set
MOVW SP,A
; In this case, S flag = 1, so set to SSP
MOV DDR2,#00000000B
; The P24/INT4 pin set to input.
OR
CCR,#40H
; I flag of CCR in PS set to interrupt enabled
MOV I:ICR00,#00H
; Interrupt level 0 (highest)
MOV I:ELVR,#00010000B ; INT4 as an High level request
MOV I:EIRR,#00H
; INT4 interrupt factor cleared
MOV I:ENIR,#10H
; INT4 input enabled
:
LOOP:
NOP
; Dummy loop
NOP
NOP
NOP
BRA LOOP
; Unconditional jump
95
CHAPTER 3 CPU
;-----Interrupt program---------------------------------------------------------ED_INT1:
MOV I:EIRR,#00H
; New acceptance of INT4 disabled
NOP
NOP
NOP
NOP
NOP
NOP
RETI
; Return from interrupt
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS = OFFH
ORG OFFDOH
; Vector set to interrupt #11 (OBH)
DSL ED_INT1
ORG OFFDCH
; Reset vector set
DSL START
DB
00H
; Set to single-chip mode
VECT
ENDS
END
START
96
CHAPTER 3 CPU
■ Program Example of EI2OS
● Processing specification
• The EI2OS is started by detecting the High level of the signal to be input to the INT4 pin.
• When the High level is input to the INT4 pin, EI2OS is started and the data of port 2 is transferred to
memory address "3000H".
• The transfer data is 100 bytes. After 100 bytes are transferred, an interrupt is generated at completion of
transfer by the EI2OS transfer.
● Coding example
DDR2
ENIR
EIRR
ELVR
ICR00
BAPL
BAPM
BAPH
ISCS
IOAL
IOAH
DCTL
DCTH
ER0
STACK
EQU 000012H
; Port 2 direction register
EQU 000030H
; Interrupt/DTP enable register
EQU 000031H
; Interrupt/DTP factor register
EQU 000032H
; Request level setting register
EQU 0000B0H
; Interrupt control register
EQU 000100H
; Lower of buffer address pointer
EQU 000101H
; Middle of buffer address pointer
EQU 000102H
; Higher of buffer address pointer
EQU 000103H
; EI2OS status
EQU 000104H
; Lower of I/O address pointer
EQU 000105H
; Higher of I/O address pointer
EQU 000106H
; Lower of data counter
EQU 000107H
; Higher of data counter
EQU EIRR:0
; External interrupt request flag bit defined
SSEG
; Stack
RW
100
STACK_T RW 1
STACK
ENDS
;-----Main program--------------------------------------------------------------CODE
CSEG
START:
AND CCR,#0BFH
; I flag of CCR in PS cleared to interrupt disabled
MOV RP,#00
; Register bank pointer set
MOV A,#!STACK_T
; System stack set
MOV SSB,A
MOVW A,#STACK_T
; Stack pointer
; in this case, S flag = 1, so set to SSP
MOVW SP,A
MOV I:DDR2,#00000000B ; P24/INT4 pin set to input
MOV BAPL,#00H
; Buffer address set (003000H)
MOV BAPM,#30H
MOV BAPH,#00H
97
CHAPTER 3 CPU
MOV
ISCS,#00010001B
;
;
;
;
;
;
MOV
IOAL,#00H
MOV
MOV
MOV
MOV
IOAH,#00H
DCTL,#64H
;
DCTH,#00H
I:ICR00,#00001000B;
;
I:ELVR,#00010000B ;
I:EIRR,#00H
;
I:ENIR,#01H
;
ILM,#07H
;
CCR,#40H
;
I/O Address not updated, byte transfer performed,
and buffer address updated
Data transferred from I/O to buffer,
and termination by resource
Transfer source address set
(port 2: 0000002H)
Transfer byte count set (100 bytes)
EI2OS channel 0, EI2OS enabled,
and interrupt level 0 (highest)
INT4 set as an High level request
INT4 interrupt factor cleared
INT4 interrupt enabled
ILM in PS set to level 7
I flag of CCR in PS set to interrupt enabled
MOV
MOV
MOV
MOV
OR
:
LOOP:
BRA LOOP
; Infinite loop
;-----Interrupt program---------------------------------------------------------WARI
CLRB ER0
; Interrupt/DTP request flag cleared
:
Processing by user
; EI2OS termination factor checked,
:
; data processing during buffering
; EI2OS reset
RETI
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS = OFFH
ORG OFFDOH
; Vector set to interrupt #11 (0BH).
DSL WARI
ORG OFFDCH
; Reset vector set
DSL START
DB
00H
; Set to single-chip mode
VECT
ENDS
END START
98
CHAPTER 3 CPU
3.6
Reset
When a reset factor occurs, the CPU immediately suspends the current processing and
starts the reset operation.
The reset factors are as follows:
• Power-on reset
• Overflow of watchdog timer
• Software reset request
• Generation of external reset request (RST pin)
■ Reset Factors
Table 3.6-1 Reset Factor
Reset
Factor
Machine
Clock
Watchdog
Timer
Oscillation
Stabilization
Waiting
Power on reset
At power on
MCLK
Stops
Generated
Watchdog timer reset
Watchdog timer overflow
MCLK
Stops
None
Software reset
"0" is written to the RST bit
MCLK
Stops
None
External reset
Input L level to RST pin
MCLK
Stops
None
MCLK: Main clock
● Power on reset
• The power on reset occurs at power on.
• The reset operation is executed after the oscillation stabilization wait time of 218/HCLK has elapsed.
● Watchdog timer reset
• Unless the watchdog timer is periodically cleared at the interval time to be repeatedly counted after
starting, an overflow occurs, causing a reset.
• The oscillation stabilization wait time is not generated by a watchdog timer reset.
Reference:
For the details of the watchdog timer, see "CHAPTER 6 WATCHDOG TIMER".
99
CHAPTER 3 CPU
● Software reset
• The software reset occurs when "0" is written to the internal reset signal generate bit (LPMCR: RST) in
the low-power consumption mode control register.
• The oscillation stabilization wait time is not generated by a software reset.
● External reset
• The external reset occurs when a Low level is input to the external reset pin (RST pin). The time for
inputting Low level from the RST pin requires at least 16 machine cycles (main clock).
• An external reset does not require the oscillation stabilization wait time.
Notes:
• If an external reset request is generated from the RST pin during writing by a transfer instruction
(such as MOV), the reset cancel wait state is set after completion of the transfer instruction, so
writing is terminated normally. For a string instruction (such as MOVS), the reset cancel wait state
may be set before completion of transfer by a specified counter value.
• When stop mode, subclock mode, sub-sleep mode and watch mode are returned to main clock
mode using an external reset pin (RST pin), input level "L" for at least "the oscillation time of the
oscillator(*) + 100μs + 16 machine cycles (main clock)".
*: The oscillation time of the oscillator is the time required to reach 90% of amplitude. It takes several to
dozens of ms for crystal oscillators, hundreds of μs to several ms for ceramic oscillators, and 0s for
external clocks.
100
CHAPTER 3 CPU
3.6.1
Reset Factors and Oscillation Stabilization Wait Time
The oscillation stabilization wait time after reset varies depending on the reset factors.
■ Reset Sources and Oscillation Stabilization Wait Time
Table 3.6-2 Reset Factors and Oscillation Stabilization Wait Times
Oscillation Stabilization Wait Time
(The parenthesized value is a calculation example
at 4 MHz oscillation clock frequency.)
Reset Factor
Power on reset
218/HCLK (approx. 65.54 ms)
Watchdog reset
None
Software reset
None
External reset
None
HCLK: Oscillation clock
Figure 3.6-1 Oscillation Stabilization Wait time for the MB90385 Series during a Power-on Reset
Vcc
CLK
CPU operation
2 17 /HCLK
Voltage step-down circuit
stabilization wait time
2 18 /HCLK
Oscillation stabilization wait time
HCLK: Oscillation clock
101
CHAPTER 3 CPU
Table 3.6-3 Oscillation Stabilization Wait Time by Clock Select Register (CKSCR)
Clock Select Bit
Oscillation Stabilization Wait Time
(The parenthesized value is a calculation example
at 4 MHz oscillation clock frequency.)
WS1
WS0
0
0
210/HCLK (256 μs)
0
1
213/HCLK (approx. 2.048 ms)
1
0
215/HCLK (approx. 8.192 ms)
1
1
217/HCLK (approx. 32.77 ms) *
HCLK: Oscillation clock
*: At power on, the oscillation stabilization wait time is fixed at 218/HCLK (approximately 65.54 ms).
Note:
Ceramic or crystal oscillators require the oscillation stabilization wait time of several milliseconds to
some tens of milliseconds to stabilize oscillation. Set the oscillation stabilization wait time required for
the oscillator to be used.
For the details of the clock, see "3.7 Clocks".
102
CHAPTER 3 CPU
3.6.2
External Reset Pin
The external reset pin (RST pin) is a reset input pin. Input of an external Low level
generates a reset factor. The MB90385 series starts the reset operation in
synchronization between the CPU and clock.
■ Block Diagram of External Reset Pin
Figure 3.6-2 Block Diagram of External Reset Pin
RST
P-ch
Pin
N-ch
CPU operating clock
(PLL multiplying circuit, 2 frequency division of HCLK)
Synchronization
circuit
HCLK: Oscillation clock
Internal reset signal
Input buffer
Notes:
• To prevent damage to memory due to a reset during writing to memory, a Low level is input to the
RST pin in a machine cycle in which memory is not damaged.
• The CPU operation clock is required to initialize internal circuits. In particular, at operation on an
external clock, the reset signal and CPU operation clock signal must be input.
103
CHAPTER 3 CPU
3.6.3
Reset Operation
During reset operation, the mode for reading mode data and reset vectors is set
according to the settings of the mode pins (MD0 to MD2) and a mode fetch is executed.
When the oscillation clock is returned from stop states (power on, stop mode) by a
reset, a mode fetch is executed after the elapse of the main clock oscillation
stabilization wait time.
■ Flowchart of Reset Operation
Figure 3.6-3 shows the flowchart of reset operation.
Figure 3.6-3 Flowchart of Reset Operation
Power-on reset
Software reset
External reset (RST pin)
Watchdog timer reset
Reset operation
Oscillation stabilization wait time
Reset cleared
Mode data fetched
Sets pin state
related to bus mode
Reset sequence
Reset vector fetched
Normal operation
(RUN state)
Processing from address indicated
by reset vector executed
■ Oscillation Stabilization Wait Time in Standby Mode
When a reset occurs during operation in a stop mode or subclock mode in which the oscillation clock is
stopped, and oscillation stabilization wait time of 217/HCLK (approximately 32.77 ms when the oscillation
clock operates at 4 MHz) is generated.
Reference:
For standby mode operation, see Section "3.8 Low-power Consumption Mode".
104
CHAPTER 3 CPU
■ Mode Pin
The MD0 to MD2 mode pins are external pins. They are used to set the mode for reading data and reset
vectors.
Reference:
For the details of the mode pins (MD0 to MD2), see Section "3.9.3 Memory Access Mode".
■ Mode Fetch
At transition to the reset operation, the CPU automatically transfers mode data and reset vectors by
hardware to the appropriate register in the CPU core. The mode data and reset vector are allocated to four
bytes of addresses "FFFFDCH" to "FFFFDFH". After a reset factor is generated (or after the elapse of the
oscillation stabilization wait time), the CPU immediately outputs the addresses of the mode data and reset
vectors to the bus to fetch the mode data and reset vectors. This operation is called "mode fetch." At
completion of mode fetch, the CPU starts processing from the address indicated by the reset vector.
Figure 3.6-4 Transfer of Mode Data and Reset Vectors
Memory space
F2MC-16LX CPU core
PC
FFFFDCH
Reset vector bits 7 to 0
FFFFDDH
Reset vector bits 15 to 8
FFFFDEH
FFFFDFH
PCB
Reset vector bits 23 to 16
CPU mode data
Reset sequence
Micro ROM
Mode
register
Note:
To read the mode data and reset vectors from internal ROM is set by the mode pins (MD0 to MD2).
For use in the single-chip mode, the mode pins should be set to the internal vector mode.
● Mode data
The mode data is used to set a memory access type or a memory access area after completion of the reset
operation. It is allocated to address "FFFFDFH". During the reset operation, this data is read automatically
by a mode fetch and stored in the mode register.
● Reset vectors
The reset vectors are the start addresses of execution after completion of the reset operation. They are
allocated to addresses "FFFFDCH" to "FFFFDEH". During the reset operation, these vectors are read
automatically by a mode fetch and transferred to the program counter.
105
CHAPTER 3 CPU
3.6.4
Reset Factor Bit
To check reset factors, read the value of the watchdog timer control register (WDTC).
■ Reset Factor Bit
Each reset factor provides a flip-flop circuit corresponding to each factor. The state of the flip-flop circuit
can be checked by reading the value of the watchdog timer control register (WDTC). If it is necessary to
identify reset factors after completion of the reset operation, read the value of the watchdog timer control
register (WDTC) by software to branch the value to the appropriate program.
Figure 3.6-5 Block Diagram of Reset Factor Bits
RST pin
Power-on
Power-on
detector
Watchdog timer
control register
(WDTC)
No clear during
interval time
RST = L
External reset
request detector
Watchdog timer
reset detector
RST bit set
LPMCR register
RST bit write
detector
Clear
S
R
S
F/F
Q
R
S
F/F
Q
R
S
F/F
Q
R
F/F
Q
Delay
circuit
The watchdog timer
control register
(WDTC) is read
F2MC-16LX Internal bus
S :
R :
Q :
F/F :
106
Set
Reset
Output
Flip-flop circuit
CHAPTER 3 CPU
■ Correspondence of Reset Factor Bit and Reset Factor
Figure 3.6-6 shows the configuration of the reset factor bits in the watchdog timer control register (WDTC:
PONR, WRST, ERST, SRST).
Figure 3.6-6 Configuration of Reset Factor Bit
Watchdog timer
control register (WDTC)
bit 7
bit 6
PONR
-
R
-
bit 5
bit 2
bit 1
bit 0
WRST ERST SRST WTE
WT1
WT0 XXXXX111B
R
bit 4
R
bit 3
R
W
W
Reset value
W
R: Read only
W: Write only
X: Undefined
Table 3.6-4 Correspondence of Reset Factor Bit Value and Reset Factor
Reset Factor
PONR
WRST
ERST
SRST
Power on reset
1
X
X
X
Watchdog timer reset
*
1
*
*
Input of external reset signal to RST pin
*
*
1
*
Software reset (RST bit)
*
*
*
1
*: The previous state is held
X: Undefined
■ Notes on Reset Factor Bit
● Power on reset
When a power on reset is executed, the PONR bit is set to "1" after completion of the reset operation. Any
reset factor bit other than the PONR bit is undefined. When the PONR bit is "1" after completion of the
reset operation, ignore the value of any bit other than the PONR bit.
● At two or more reset factors
The reset factor bit is set to "1" according to each reset factor even when two or more reset factors are
generated. For example, if the watchdog timer overflows and an external reset request is generated from the
RST pin at the same time, both WRST and ERST bits are set to "1" after completion of the reset operation.
● Clearing of reset factor bit
Once set, the reset factor bit is not cleared even if any reset factor other than the set factor is generated. The
reset factor bit is cleared after the completion of reading the watchdog timer control register (WDTC).
Reference:
For the watchdog timer, see "CHAPTER 6 WATCHDOG TIMER".
107
CHAPTER 3 CPU
3.6.5
State of Each Pin at Reset
This section explains the state of each pin at reset.
■ State of Pins at Reset
The state of the pins during reset operation is determined by the settings of the mode pins (MD0 to MD2).
● When internal vector mode set:
If the internal vector mode is set, all I/O pins enter the high-impedance state and mode data is read to
internal ROM.
■ State of Pins after Mode Data Read
The I/O pins are all set to the high-impedance state, and the mode data read destination is the internal
ROM.
Note:
Don’t let the device connected to pins that enter the high-impedance state malfunction when the
reset factor is generated.
108
CHAPTER 3 CPU
3.7
Clocks
The clock generation section controls the internal clock that is an operating clock for
the CPU or resources. The clock generated by the clock generation section is called a
"machine clock" and one cycle of the machine clock is a machine cycle. The clock to be
supplied from a high-speed oscillator is called an "oscillation clock" and the 2frequency division of the oscillation clock is called a "main clock". The 4-frequency
division of a clock to be supplied from a low-speed oscillator is called a "subclock" and
the clock to be supplied from the PLL oscillation is called a "PLL clock".
■ Clock
The clock generation section has oscillators and generates an oscillation clock by connecting an oscillator
to oscillation pins. External clocks that are input to the oscillation pins can be used as oscillation clocks.
The PLL clock multiplying circuit can be used to generate four clocks for multiplying the oscillation clock.
The clock generation section controls the oscillation stabilization wait time, PLL clock multiplying, and
selects internal clock by the clock selector.
● Oscillation clock (HCLK)
This clock is generated by connecting an oscillator or inputting an external clock to the high-speed
oscillation pins (X0 and X1).
● Main clock (MCLK)
This clock is 2-frequency division of oscillation clock, and is an input clock to the timebase timer and clock
selector.
● Subclock (SCLK)
This clock is a clock with 4-frequency division of the clock generated by connecting an oscillator or
inputting an external clock to the low-speed oscillation pins (X0A and X1A). It can also be used as an
operating clock for the watch timer or as a low-speed machine clock.
● PLL clock (PCLK)
This clock is multiplied by the PLL clock multiplying circuit (PLL oscillator). It can be selected from four
types of clock according to the setting of the multiplication rate select bits (CKSCR: CS1, CS0).
109
CHAPTER 3 CPU
● Machine clock
This clock is an operating clock for the CPU and the resources. One cycle of the machine clock is a
machine cycle (1/φ). One clock can be selected from the main clock, subclock, and four types of PLL
clock.
Notes:
• When the operating voltage is 5 V, the oscillation clock can oscillate at 3 MHz to 16 MHz. The
maximum operating frequency of the CPU or resources is 16 MHz. If a multiplication rate that
exceeds the maximum operating frequency is set, the device does not operate normally. If the
oscillation clock is 16 MHz, the multiplication rate of PLL clock can only be set to x1. The PLL
oscillator oscillates in the range of 3 MHz to 16 MHz, which varies depending on the operating
voltage and multiplication rate.
• There is no subclock in MB90F387S and MB90387S.
■ Clock Supply Map
Machine clocks generated by the clock generation section are supplied as operating clocks of the CPU and
resources. The operation of the CPU and resources is affected by switching among the main clock,
subclock, and PLL clock (clock mode) or by switching the multiplication rate of PLL clock. The clockdivided output of the timebase timer is supplied to some resources, and the operating clock can be selected
for each resource.
Figure 3.7-1 shows the clock supply map.
110
CHAPTER 3 CPU
Figure 3.7-1 Clock Supply Map
Resources
4
4
Watchdog timer
Watch timer
8-/16- bit
PPG timer 0, 1
Timebase timer
8-/16- bit
PPG timer 2, 3
Clock generation section
X0A
Pin
1 2 3 4
16-bit reload
timer 0
PLL multiplying circuit
X0
Pin
X1
Pin
PPG2,3
Pin
TIN0
Pin
Subclock
generator
X1A
Pin
PPG0,1
Pin
4-divided
clock
SCLK PCLK
Oscillation
2-divided
clock
Clock selector
clock
generator HCLK
MCLK
TOT0
Pin
Communication prescaler 1
φ
UART1
SCK1
Pin
SOT1
Pin
SIN1
Pin
CPU intermittent
operation
TIN1
Pin
16-bit reload
timer 1
CPU
TOT1
Pin
ADTG
Pin
8-/10- bit
A/D converter
IN0,1,2,3
Pin
Input capture unit
16-bit free-run timer
RX
Pin
HCLK
MCLK
PCLK
SCLK
φ
:
:
:
:
:
Oscillation clock
Main clock
PLL clock
Subclock
Machine clock
CAN controller
3
TX
Pin
Oscillation stabilization
wait control
111
CHAPTER 3 CPU
3.7.1
Block Diagram of Clock Generation Section
The clock generation section consists of the following five blocks:
• Oscillation clock generator/subclock generator
• PLL multiplying circuit
• Clock selector
• Clock select register (CKSCR)
• Oscillation stabilization wait time selector
■ Block Diagram of Clock Generation Section
Figure 3.7-2 shows the block diagram of the clock generation section.
It also includes the standby controller and timebase timer circuit.
Figure 3.7-2 Block Diagram of Clock Generation Section
Standby controller
Low-power consumption mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0
CPU intermittent
operation cycle
selector
Reserved
2
CPU clock
controller
CPU
operating
clock
Watch mode
Sleep signal
Stop signal
Resource clock
controller
S
Q
S
R
S
Reset
Interrupt
Machine clock
R
S
Q
Resource
operating
clock
Q
Q
R
R
Operating
clock
selector
2
Oscillation
stabilization wait
time selector
2
PLL multiplying
circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock select register (CKSCR)
X0
Pin
X1
Pin
Oscillation
clock
Oscillation clock (HCLK)
generator
X0A
Pin
X1A
Pin
112
1024-divided
clock
Main
clock
2-divided
clock
4-divided
clock
2-divided
clock
2-divided
clock
2-divided
clock
2-divided
clock
Timebase timer
Subclock
4-divided
clock
To watchdog timer
1024-divided
clock
Watch timer
Subclock generator
S: Set
R: Reset
Q: Output
2-divided
clock
8-divided
clock
2-divided
clock
2-divided
clock
2-divided
clock
CHAPTER 3 CPU
● Oscillation clock generator
This generator generates an oscillation clock (HCLK) by connecting an oscillator or inputting an external
clock to the high-speed oscillation pins.
● Subclock generator
This generator generates a subclock (SCLK) by connecting an oscillator or inputting an external clock to
the low-speed oscillation pins (X0A, X1A).
● PLL multiplying circuit
This circuit multiplies the oscillation clock and supplies it as a PLL clock (PCLK) to the clock selector.
● Clock selector
This selector selects the clock that is supplied to the CPU or resources from the main clock, subclock, and
four types of PLL clock.
● Clock select register (CKSCR)
This register switches between the oscillation clock and the PLL clock, and between the main clock and the
subclock, selects the oscillation stabilization wait time, and the multiplication rate of the PLL clock.
● Oscillation stabilization wait time selector
This selector selects the oscillation stabilization wait time of the oscillation clock. There are four timebase
timer outputs to select.
Note:
There is no subclock in MB90F387S and MB90387S.
113
CHAPTER 3 CPU
3.7.2
Register in Clock Generation Section
This section explains the register in the clock generation section.
■ Register in Clock Generation Section and List of Reset Values
Figure 3.7-3 Clock Select Register and List of Reset Values
bit
Clock select register (CKSCR)
114
15
1
14
1
13
1
12
1
11
1
10
1
9
0
8
0
CHAPTER 3 CPU
3.7.3
Clock Select Register (CKSCR)
The clock select register (CKSCR) switches between the main clock, subclock, and PLL
clock, selects the oscillation stabilization wait time and the multiplication rate of PLL
clock.
■ Configuration of Clock Select Register (CKSCR)
Figure 3.7-4 Clock Select Register (CKSCR)
15
14
R
R
13
12
11
10
9
8
Reset value
11111100 B
R/W R/W R/W R/W R/W R/W
bit 9 bit 8
CS1 CS0
Multiplication rate select bits
The parenthesized values are provided when the oscillation clock (HCLK) operates at 4 MHz
0
0
1 × HCLK (4 MHz)
0
1
2 × HCLK (8 MHz)
1
0
3 × HCLK (12 MHz)
1
1
4 × HCLK (16 MHz)
bit 10
MCS
PLL clock select bit
The PLL clock selected
0
1
The main clock selected
bit 11
SCS
Subclock select bit
0
The subclock selected
1
The main clock selected
bit 13 bit 12
WS1 WS0
Oscillation stabilization wait time select bits
The parenthesized values are provided when the oscillation clock (HCLK) operates at 4 MHz
0
0
210/HCLK (approx. 256 μs)
0
1
213/HCLK (approx. 2.05 ms)
1
0
215/HCLK (approx. 8.19 ms)
1
1
217/HCLK (approx.32.77 ms, except power on reset)
218/HCLK (approx. 65.54 ms, only power on reset)
bit 14
PLL clock operation bit
MCM
0
Operating on the PLL clock
1
Operating on the main clock or subclock
HCLK : Oscillation clock
R/W : Read/Write
R
: Read only
: Reset value
bit 15
Subclock operation bit
SCM
0
Operating on the subclock
1
Operating on the main clock or PLL clock
115
CHAPTER 3 CPU
Table 3.7-1 Function of Each Bit of Clock Select Register (CKSCR) (1/2)
Bit Name
SCM:
Subclock operation bit
This bit indicates whether to select main clock or the subclock as the machine clock.
• If the subclock operation flag bit (CKSCR: SCM) is "0" and the subclock select bit
(CKSCR: SCS) is "1", it indicates that the subclock switches to the main clock. If the
subclock operation flag bit (CKSCR: SCM) is "1" and the subclock select bit
(CKSCR: SCS) is "0", it indicates that the main clock switches to the subclock.
• Writing has no effect.
MCM:
PLL clock operation bit
This bit indicates whether to select main clock or PLL clock as machine clock.
• If the PLL clock operation flag bit (CKSCR: MCM) is "1" and the PLL clock select bit
(CKSCR: MCS) is "0", it indicates that the oscillation stabilization wait time of the
PLL clock is taken.
• Writing has no effect.
WS1, WS0:
Oscillation stabilization
wait time select bits
These bits select an oscillation stabilization wait time of the oscillation clock when stop
mode was released, when transition occurred from subclock mode to main clock mode, or
when transition occurred from subclock mode to PLL clock mode.
• These bits are used to select from four timebase timer outputs.
When reset, they all return to their reset value.
Note: 1. Set an oscillation stabilization wait time appropriate for an oscillator. For details,
see Section "3.6.1 Reset Factors and Oscillation Stabilization Wait Time".
bit 15
bit14
2. When the main clock mode is switched to PLL clock mode, the
oscillation stabilization wait time is fixed to 214/HCLK (approximately
4.1 ms when the oscillation clock operates at 4 MHz). When subclock
mode is switched to PLL clock mode or when PLL stop mode is
returned to PLL clock mode, the oscillation stabilization wait time uses
the specified values in the WS1 and WS0 bits. For PLL clock oscillation
stabilization wait time, at least 214 /HCLK is required.
3. Accordingly, when subclock mode is switched to PLL clock mode, or
when PLL clock mode is switched to PLL stop mode, set WS1 and WS0
bits to "10B" or "11B".
bit 13,
bit 12
SCS:
Subclock select bit
bit 11
Function
This bit sets whether to select main clock or subclock as machine clock.
• When the machine clock is switched from the main clock to the subclock (CKSCR:
SCS = 1 → 0), the main clock mode transits to the subclock mode in synchrony with
the subclock (approximately 130 μs).
• When the machine clock is switched from the subclock to the main clock (CKSCR:
SCS = 0 → 1), the subclock mode transits to the main clock mode after the main clock
oscillation stabilization wait time is generated. The timebase timer is automatically
cleared.
When reset, this bit returns to its reset value.
Notes: 1. If both the MCS and SCS bits are "0", the SCS bit is preferred and the subclock
mode is set.
2. If both the subclock select bit (CKSCR: MCS) and PLL clock select bit
(CKSCR: SCS) are "0", the subclock is preferred.
3. When switching the machine clock from the main clock to the subclock
(CKSCR: SCS = 1 → 0), use the interrupt enable bit of the timebase timer
(TBTC: TBIE) or the interrupt level mask register (ILM: ILM2 to ILM0) to
disable the timebase timer.
4. At power on or when the stop mode is canceled, the subclock oscillation
stabilization wait time (approximately 2 s) is generated. Therefore, if the mode
is switched from the main clock mode to the subclock mode, the oscillation
stabilization wait time is generated.
5. There is no subclock in MB90F387S and MB90387S. This bit should
be set to initial values.
116
CHAPTER 3 CPU
Table 3.7-1 Function of Each Bit of Clock Select Register (CKSCR) (2/2)
Bit Name
MCS:
PLL clock select bit
bit 10
Function
This bit sets where to select the main clock or PLL clock as a machine clock.
If the machine clock is switched from the main clock to the PLL clock (CKSCR: MCS = 1
→ 0), the oscillation stabilization wait time of the PLL clock is generated and then the
mode transits to the PLL clock mode. The timebase timer is automatically cleared. When
the main clock mode is switched to PLL clock, the oscillation stabilization wait time is
fixed to 214/HCLK (approximately 4.1 ms when the oscillation clock operates at 4 MHz).
When subclock mode is switched to PLL clock, the oscillation stabilization wait time uses
the specified values in the oscillation stabilization wait time selection bits (CKSCR: WS1,
WS0).
When reset, this bit returns to its reset value.
Notes: 1. If both the MCS and SCS bits are "0", the SCS bit is preferred and the
subclock mode is set.
2. When switching the machine clock from the main clock to the PLL clock
(CKSCR: MCS = 1 → 0), use the interrupt enable bit of the timebase timer
(TBTC: TBIE) or the interrupt level mask register (ILM: ILM2 to ILM0) to
disable the timebase timer interrupts.
bit 9,
bit 8
CS1, CS0:
Multiplication rate select
bits
These bits are used to select the multiplication rate of the PLL clock from four types.
When reset, they all return to their reset value.
Note: When the PLL clock is selected (CKSCR: MCS = 0), writing is inhibited. When
changing the multiplication rate, write 1 to the PLL clock select bit (CKSCR:
MCS), rewrite the multiplication rate select bits (CKSCR: CS1, CS0), and then
return the PLL clock select bit (CKSCR: MCS) to "0".
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CHAPTER 3 CPU
3.7.4
Clock Mode
Clock modes have a main clock mode, subclock mode, and PLL clock mode.
■ Clock Mode
● Main clock mode
In the main clock mode, a clock with 2-frequency division of the clock generated by connecting an
oscillator or inputting an external clock to the high-speed oscillation pins (X0, X1) is used as the operating
clock for the CPU or resources.
● Subclock mode
In the subclock mode, a clock with 4-frequency division of the clock generated by connecting an oscillator
or inputting an external clock to the low-speed oscillation pins (X0A, X1A) is used as the operating clock
for the CPU or resources.
● PLL clock mode
In the PLL clock mode, the oscillation clock multiplied by the PLL clock multiplying circuit (PLL
oscillator circuit) is used as the operating clock for the CPU or resources. The PLL clock multiplication rate
can be set using the clock select register (CKSCR: CS1, CS0).
Note:
There is no subclock in MB90F387S and MB90387S.
■ Transition of Clock Mode
In clock modes, the setting of the PLL clock select bit (CKSCR: MCS) and subclock select bit (CKSCR:
SCS) transits to the main clock mode, subclock mode or PLL clock mode.
● Transition from main clock mode to PLL clock mode
If the PLL clock select bit (CKSCR: MCS) is rewritten from "1" to "0", the main clock switches to the PLL
clock after the PLL oscillation stabilization wait time (214/HCLK) has elapsed.
● Transition from PLL clock mode to main clock mode
If the PLL clock select bit (CKSCR: MCS) is rewritten from "0" to "1", the PLL clock switches to the main
clock when the edge of the PLL clock matches the edge of the main clock (after 1 to 8 PLL clocks).
● Transition from main clock mode to subclock mode
If the subclock select bit (CKSCR: SCS) is rewritten from "1" to "0", the main clock switches to the
subclock synchronizing the subclock (approx.130 μs).
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CHAPTER 3 CPU
● Transition from subclock mode to main clock mode
When the subclock select bit (CKSCR: SCS) is rewritten from "0" to "1", the subclock switches to the main
clock after the main clock oscillation stabilization wait time has elapsed.
Notes:
• When subclock mode are returned to main clock mode using an external reset pin (RST pin),
input level "L" for at least "the oscillation time of the oscillator* + 100μs + 16 machine cycles (main
clock)".
*: The oscillation time of the oscillator is the time required to reach 90% of amplitude. It takes
several to dozens of ms for crystal oscillators, hundreds of μs to several ms for ceramic
oscillators, and 0s for external clocks.
• There is no subclock in MB90F387S and MB90387S.
● Transition from PLL clock mode to subclock mode
When the subclock select bit (CKSCR: SCS) is rewritten from "1" to "0", the PLL clock switches to the
subclock.
● Transition from subclock mode to PLL clock mode
When the subclock select bit (CKSCR: SCS) is rewritten from "0" to "1", the subclock switches to the PLL
clock after the main clock oscillation stabilization wait time has elapsed.
■ Selection of PLL Clock Multiplication Rate
The PLL clock multiplication rate can be set from ×1 to × 4 by writing values of "00B" to "11B" to the
multiplication rate select bits (CKSCR: CS1, CS0).
■ Machine Clock
The PLL clock, main clock, and subclock output from the PLL multiplying circuit are used as machine
clocks supplied to the CPU or resources.
Any of the main clock, PLL clock, and subclock can be selected by writing to the subclock select bit
(CKSCR: SCS) and the PLL clock select bit (CKSCR: MCS).
Notes:
• The machine clock is not switched immediately even when the PLL clock select bit (CKSCR:
MCS) and the subclock select bit (CKSCR: SCS) are rewritten. When running resources that
depend on the machine clock, after switching the machine clock, refer the value of the PLL clock
operation flag bit (CKSCR: MCM) or the subclock operation flag bit (CKSCR:SCM) to check that
the machine clock has been switched.
• When the PLL clock select bit (CKSCR: MCS) is "0" (PLL clock mode) and the subclock select bit
(CKSCR: SCS) is "0" (subclock mode), the SCS bit is preferred, transiting to the subclock mode.
• When transiting a clock mode, do not transit a clock mode to any other clock mode or a low-power
consumption mode until the completion of transition. Refer the MCM and SCM bits in the clock
select register (CKSCR) to check that the transition of a clock mode is completed. If the mode is
switched to another clock mode or low-power-consumption mode before completion of switching,
the mode may not be switched.
• There is no subclock in MB90F387S and MB90387S.
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CHAPTER 3 CPU
Figure 3.7-5 shows the transition of a clock mode.
Figure 3.7-5 Clock Mode Transition
Main
MCS = 1
MCM = 1
SCS = 1
SCM = 1
CS1,CS0 = xx
Main → Sub
MCS = 1
MCM = 1
(9)
(10) SCS = 0
SCM = 1
CS1,CS0 = xx
(8)
(1)
(11)
(6)
Main → PLLx
MCS = 0
MCM = 1
SCS = 1
SCM = 1
CS1,CS0 = xx
(2)
(3)
(4)
(5)
Sub
MCS = 1
MCM = 1
(16) SCS = 0
(10) SCM = 0
CS1,CS0 = xx
Sub → Main
MCS = 1
(8)
MCM = 1
SCS = 1
(8)
SCM = 0
(12) Sub → PLL
CS1,CS0 = xx
(13) MCS = 0
MCM = 1
(14)
SCS = 1
(15) SCM = 0
CS1,CS0 = xx
PLL1 → Main
MCS = 1
(7) MCM = 0
SCS = 1
SCM = 1
CS1,CS0 = 00
PLL1 multiplication
MCS = 0
MCM = 0
(6) SCS = 1
(8)
SCM = 1
CS1,CS0 = 00
PLL1 → Sub
MCS = 1
(17)
MCM = 0
SCS = 0
SCM = 1
CS1,CS0 = 00
PLL2 → Main
MCS = 1
(7) MCM = 0
SCS = 1
SCM = 1
CS1,CS0 = 01
PLL2 multiplication
MCS = 0
MCM = 0
(6) SCS = 1
(8)
SCM = 1
CS1,CS0 = 01
PLL2 → Sub
MCS = 1
(17)
MCM = 0
SCS = 0
SCM = 1
CS1,CS0 = 01
PLL3 → Main
MCS = 1
(7) MCM = 0
SCS = 1
SCM = 1
CS1,CS0 = 10
PLL3 multiplication
MCS = 0
MCM = 0
(6) SCS = 1
(8)
SCM = 1
CS1,CS0 = 10
PLL3 → Sub
MCS = 1
(17)
MCM = 0
SCS = 0
SCM = 1
CS1,CS0 = 10
PLL4 → Main
MCS = 1
(7) MCM = 0
SCS = 1
SCM = 1
CS1,CS0 = 11
PLL4 multiplication
MCS = 0
MCM = 0
(6) SCS = 1
(8)
SCM = 1
CS1,CS0 = 11
PLL4 → Sub
MCS = 1
(17)
MCM = 0
SCS = 0
SCM = 1
CS1,CS0 = 11
(1) 0 write to MCS bit
(2) PLL clock oscillation stabilization waiting termination & CS1, CS0 = 00
(3) PLL clock oscillation stabilization waiting termination & CS1, CS0 = 01
(4) PLL clock oscillation stabilization waiting termination & CS1, CS0 = 10
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CHAPTER 3 CPU
(5) PLL clock oscillation stabilization waiting termination & CS1, CS0 = 11
(6) 1 write to MCS bit (hardware standby and the watchdog reset included)
(7) Synchronous timing of PLL clock and main clock
(8) 0 write to SCS bit
(9) Subclock oscillation stabilization wait time termination (maximum 214/SCLK)
(10) 1 write to SCS bit
(11) Main clock oscillation stabilization waiting termination
(12) Main clock oscillation stabilization waiting termination & CS1, CS0 = 00
(13) Main clock oscillation stabilization waiting termination & CS1, CS0 = 01
(14) Main clock oscillation stabilization waiting termination & CS1, CS0 = 10
(15) Main clock oscillation stabilization waiting termination & CS1, CS0 = 11
(16) 1 write to SCS bit and 0 to MCS bit
(17) Synchronous timing of PLL clock and subclock
MCS
: PLL clock select bit of clock select register (CKSCR)
MCM
: PLL clock display bit of clock select register (CKSCR)
SCS
: Subclock select bit of clock select register (CKSCR)
SCM
: Subclock display bit of clock select register (CKSCR)
CS1, CS0 : Multiplication rate select bit of clock select register (CKSCR)
Notes:
• The reset value of the machine clock is in the main clock mode (MCS = 1, SCS = 1).
• When SCS and MCS are both 0, SCS is preferred, and the subclock is selected.
• When transiting from the subclock mode to the PLL clock mode, set the oscillation stabilization
wait time select bit of the CKSCR register (WS1, WS0) to "10B " or "11B".
• There is no subclock in MB90F387S and MB90387S.
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CHAPTER 3 CPU
3.7.5
Oscillation Stabilization Wait Time
At power on or return from the stop mode, when the oscillation clock is stopped, a time
taken until the oscillation clock stabilizes (oscillation stabilization wait time) is required
after starting an oscillation. The oscillation stabilization wait time is also required for
switching the clock mode from main clock mode to PLL clock mode, from main clock
mode to subclock mode, from subclock mode to main clock mode, and from subclock
mode to PLL clock mode.
■ Operation During Oscillation Stabilization Wait Time
Ceramic and crystal oscillators require several to some tens of ms to reach a stable oscillation frequency
after starting oscillation. Therefore when, immediately after an oscillation starts, once the CPU operation is
disabled and then an oscillation stabilizes after the elapse of oscillation stabilization wait time, the machine
clock is supplied to the CPU.
The oscillation stabilization wait time varies with the type of oscillator (ceramic, crystal, etc.).
It is necessary to select a oscillation stabilization wait time appropriate to an oscillator to be used.
The oscillation stabilization wait time can be selected using the clock select register (CKSCR).
When clock mode is switched from main clock to PLL clock, main clock to subclock, subclock to main
clock, or subclock to PLL clock, the CPU runs in the clock mode set before switching for the oscillation
stabilization wait time. After the oscillation stabilization wait time has elapsed, the CPU changes to the
specified clock mode. Figure 3.7-6 shows the oscillating operation immediately after it starts.
Figure 3.7-6 Operation after Oscillation Stabilization Wait Time
Oscillation time
of oscillator
Oscillation
stabilization wait time
X1
The oscillation started
The oscillation stabilized
Note:
There is no subclock in MB90F387S and MB90387S.
122
Starting of normal
operation or transiting to
PLL clock/subclock
CHAPTER 3 CPU
3.7.6
Connection of Oscillator and External Clock
The MB90385 series has a system clock generator and generates an internal clock by
connecting an oscillator to the oscillation pins. External clocks input to the oscillation
pins can be used as oscillation clocks.
■ Connection of Oscillator and External Clock
● Example of connection of crystal oscillator or ceramic oscillator
Figure 3.7-7 Example of Connection of Crystal Oscillator or Ceramic Oscillator
X0
X1
C1
C2
MB90385 series
X0A
X1A
C3
C4
● Example of connection of external clock
Figure 3.7-8 Example of Connection of External Clock
X0
~
Open
X1
MB90385 series
X0A
~
Open
X1A
Note:
There is no subclock in MB90F387S and MB90387S.
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CHAPTER 3 CPU
3.8
Low-power Consumption Mode
The CPU operation modes are classified as follows according to the selection of the
operation clock and the oscillation control of a clock. All the operation modes except
the PLL clock mode are low-power consumption modes.
• Clock modes (main clock, PLL clock and subclock modes)
• CPU intermittent operation modes (main clock, PLL clock, and subclock modes)
• Standby modes (sleep, stop, watch, and timebase timer modes)
■ CPU Operation Modes and Current Consumption
Figure 3.8-1 shows the relationships between the CPU operation mode and current consumption.
Figure 3.8-1 CPU Operation Mode and Current Consumption
Current consumption
High
CPU operation
mode
PLL clock mode
4-multiplied clock
3-multiplied clock
2-multiplied clock
1-multiplied clock
PLL clock intermittent operation mode
4-multiplied clock
3-multiplied clock
2-multiplied clock
1-multiplied clock
Main clock mode (21/HCLK)
Main clock intermittent operation mode
Subclock mode (SCLK)
Subclock intermittent operation mode
Standby mode
Sleep mode
Watch mode
Timebase timer mode
Stop mode
Low
Low-power consumption mode
Note: This figure shows an image of operation mode.
So the current consumption shown above may be different from the actual one .
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CHAPTER 3 CPU
■ Clock Mode
● PLL clock mode
In PLL clock mode, the CPU and resources operate on a PLL multiplying clock of oscillation clock
(HCLK).
● Main clock mode
In main clock mode, the CPU and resources operate on a clock with 2-frequency division of oscillation
clock (HCLK). In this mode, the PLL multiplying circuit stops.
● Subclock mode
In subclock mode, the CPU and resources operate on a subclock (SCLK). In this mode, the main clock and
PLL multiplying circuit stop.
The subclock oscillation stabilization wait time (approximately 2 s) is generated at power on or at
cancellation of the stop mode. Therefore, if the clock mode transits from the main clock mode to the
subclock mode during that period, the oscillation stabilization wait time is generated.
Note:
There is no subclock in MB90F387S and MB90387S.
Reference:
For the clock mode, see Section "3.7 Clocks".
■ CPU Intermittent Operation Mode
In CPU intermittent operation mode, the CPU performs the intermittent operation with the high-speed clock
supplied to the resource to reduce the power consumption. In this mode, the intermittent clock is input to
only the CPU at accessing registers, internal memory, or resources.
■ Standby Mode
The standby mode causes the standby control circuit to stop the supply of an operation clock to the CPU or
resources or to stop the oscillation clock (HCLK) in order to reduce power consumption.
● Sleep mode
The sleep mode stops supply of an operation clock to the CPU during operation in each clock mode. The
CPU stops and the resources operate in the clock mode before the transition to the sleep mode. The sleep
mode is divided into the main sleep mode, PLL sleep mode, and sub-sleep mode according to the clock
mode before the transition to the sleep mode.
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CHAPTER 3 CPU
● Watch mode
The watch mode operates only the subclock (SCLK) and watch timer. The main clock and PLL clock stop.
All resources except the watch timer stop.
● Timebase timer mode
The timebase timer mode operates only the oscillation clock (HCLK), subclock (SCLK), timebase timer,
and watch timer. Resources other than the timebase timer and watch timer stop.
● Stop mode
The stop mode stops the oscillation clock (HCLK) and subclock (SCLK) during operation in each clock
mode. It enables data to be retained with the least power consumption.
Notes:
• When transiting a clock mode, do not transit a clock mode to any other clock mode or a low-power
consumption mode until the completion of transition. Refer the MCM and SCM bits in the clock
select register (CKSCR) to check that the transition of a clock mode is completed. If the mode is
switched to another clock mode or low-power-consumption mode before completion of switching,
the mode may not be switched.
• There is no subclock in MB90F387S and MB90387S.
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CHAPTER 3 CPU
3.8.1
Block Diagram of Low-power Consumption Circuit
This section shows block diagram of low-power consumption circuit.
■ Block Diagram of Low-power Consumption Circuit
Figure 3.8-2 Block Diagram of Low-power Consumption Circuit
Low-power consumption mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0
Reserved
Pin high
impedance
controller
Pin Hi-Z control
Internal reset
generator
RST Pin
CPU intermittent
operation
cycle selector
Intermittent cycle selected
CPU clock
controller
Reset
(cancellation)
CPU operating clock
Watch and sleep, stop signal
Standby
controller
2
Internal reset
Watch and stop signal
Resource
Resource
clock
operating clock
controller
Interrupt
(cancellation)
Clock
generation
section
Subclock oscillation stabilization waiting cancelled
Main clock oscillation stabilization waiting cancelled
Operating
clock
selector
Machine clock
Oscillation
stabilization wait
time selector
2
2
PLL multiplying
circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock select register (CKSCR)
X0 Pin
X1 Pin
2-divided
clock
1024-divided
2-divided
clock
clock
Main
Oscillator
clock
clock (HCLK)
Timebase timer
Oscillation clock
Subclock
oscillator
(SCLK)
4-divided
clock
X0A Pin
1024-divided
clock
4-divided
clock
2-divided
clock
2-divided
clock
2-divided
clock
2-divided
clock
2-divided
clock
To watchdog timer
8-divided
clock
2-divided
clock
2-divided
clock
Watch timer
X1A Pin
Subclock oscillator
127
CHAPTER 3 CPU
● CPU intermittent operation selector
This selector selects the halt cycle count of the CPU clock in the CPU intermittent operation mode.
● Standby controller
This controller causes the CPU clock controller and resource clock controller to switch between the CPU
operating clock and the resource operating clock, and to transits a clock mode to and cancel the standby
mode.
● CPU clock controller
This controller supplies an operating clock to the CPU.
● Pin high-impedance controller
This controller causes the input/output pins to become high impedance in the watch mode, timebase timer
mode, and stop mode.
● Internal reset generator
This generator generates the internal reset signal.
● Low-power consumption mode control register (LPMCR)
This register transits a clock mode to and cancels the standby mode, and sets the CPU intermittent
operation mode.
Note:
There is no subclock in MB90F387S and MB90387S.
128
CHAPTER 3 CPU
3.8.2
Registers for Setting Low-power Consumption Modes
This section explains the registers to be used to set lower-power consumption modes.
■ Low-power Consumption Mode Control Register and Reset Values
Figure 3.8-3 Low-power Consumption Mode Control Register and Reset Values
bit
Low-power consumption mode
control register (LPMCR)
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0
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CHAPTER 3 CPU
3.8.3
Low-power Consumption Mode Control Register
(LPMCR)
The low-power consumption mode control register (LPMCR) transits an operation mode
to and cancels the low-power consumption modes, generates an internal reset signal,
and sets the halt cycle count in the CPU intermittent operation mode.
■ Low-power Consumption Mode Control Register (LPMCR)
Figure 3.8-4 Low-power Consumption Mode Control Register (LPMCR)
7
6
5
4
3
2
1
0
Reset value
00011000 B
W
W
R/W
W
W
R/W R/W R/W
bit 0
Reserved bit
Reserved
0
Always set to "0"
bit 2 bit 1
CG1 CG0
0
0 cycle (CPU clock = resource clock)
0
1
8 cycles (CPU clock: resource clock = 1: approx. 3 to 4)
1
0
16 cycles (CPU clock: resource clock = 1: approx. 5 to 6)
1
1
32 cycles (CPU clock: resource clock = 1: approx. 9 to 10)
bit 3
TMD
0
1
Transits to watch mode or timebase timer mode
No effect
bit 4
RST
0
1
Generates internal reset signal of 3 machine cycles
No effect
bit 5
SPL
0
1
bit 6
SLP
0
1
bit 7
STP
R/W : Read/Write
W
: Write only
: Reset value
130
CPU halt cycle count select bits
0
0
1
watch mode bit
Internal reset signal generate bit
Pin state specify bit
Holds input/output pin state
High impedance
Only in the timebase timer, watch, and stop modes
Sleep mode bit
No effect
Transits to sleep mode
Stop mode bit
No effect
Transits to stop mode
CHAPTER 3 CPU
Table 3.8-1 Function of Each Bit of Low-power Consumption Mode Control Register (LPMCR)
Bit Name
Function
bit 7
STP:
Stop mode bit
This bit is used to transit the mode to the stop mode.
When set to "0": No effect
When set to "1": The mode is transits to the stop mode.
When read: "1" is always read.
• This bit is initialized to "0" by a reset or external interrupt.
bit 6
SLP:
Sleep mode bit
This bit is used to transit the mode to the sleep mode.
When set to "0": No effect
When set to "1": The mode transits to the sleep mode.
• This bit is initialized to "0" by a reset or external interrupt.
• When both the STP and SLP bits are set to "1" simultaneously, the STP bit is
preferred and the mode transits to the stop mode.
bit 5
SPL:
Pin state specify bit
This bit is used to set the state of input/output pins in transiting to the stop mode,
watch mode or timebase timer mode.
When set to "0": The current level of input/output pins is held.
When set to "1": The input/output pins are set to high impedance.
• This bit is initialized to "0" by a reset.
bit 4
RST:
Internal reset signal
generate bit
This bit is used to generate a software reset.
When set to "0": Three machine cycles of internal reset signals are generated.
When set to "1": No effect
Read: "1" is always read.
bit 3
TMD:
Watch mode bit
This bit is used to transit the operation mode to the watch mode or the timebase
timer mode.
When set to "0": The mode transits to the watch mode.
When set to "1":Not effect
• This bit is set to "1" by a reset or interrupt.
Read: "1" is always read.
bit 2,
bit 1
CG1, CG0:
CPU halt cycle count
select bit
These bits are used to set the halt cycle count of the CPU clock in the CPU
intermittent operation mode.
• Any reset causes the bit to return to the reset value.
bit 0
Reserved bit
Always set this bit to "0".
131
CHAPTER 3 CPU
Notes:
• When transiting to a low-power consumption mode using the low-power consumption mode
control register (LPMCR), use the instructions listed in Table 3.8-2.
• The low-power consumption mode transition instruction in Table 3.8-2must always be followed by
an array of instructions highlighted by a dotted line below.
MOV LPMCR,#H'XX ; the low-power consumption mode transition instruction in Table 3.8-2
NOP
NOP
JMP $+3
; jump to next instruction
MOV A,#H'10
; any instruction
The devices do not guarantee its operation after returning from the standby mode if you place an
array of instructions other than the one enclosed in the dotted line.
• To access the low-power consumption mode control register (LPMCR) with C language, refer to
"■ Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to Enter
the Standby Mode" in the section "3.8.8 Precautions when Using Low-power Consumption
Mode".
• When word-length is used for writing the low-power consumption mode control register, even
addresses must be used. Using odd addresses to switch to a low-power consumption mode may
result in a malfunction.
• To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop
mode, watch mode or timebase timer mode, disable the output of peripheral functions, and set the
STP bit of the low-power consumption mode control register (LPMCR) to "1" or set the TMD bit to
"0".
This applies to the following pins:
P14/PPG0, P15/PPG1, P16/PPG2, P17/PPG3, P21/TOT0, P23/TOT1
• There is no subclock in MB90F387S and MB90387S.
Table 3.8-2 Instructions at Transition to Low-power Consumption Mode
MOV io,#imm8
MOV dir,#imm8
MOV eam,#imm8
MOV eam,Ri
MOV io,A
MOV dir,A
MOV addr16,A
MOV eam,A
MOVW io,#imm16
MOVW dir,#imm16
MOVW eam,#imm16
MOVW eam,RWi
MOVW io,A
MOVW dir,A
MOVW addr16,A
MOVW eam,A
SETB io:bp
SETB dir:bp
SETB addr16:bp
CLRB io:bp
CLRB dir:bp
CLRB addr16:bp
MOV @RLi+disp8,A
MOVW @RLi+disp8,A
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CHAPTER 3 CPU
3.8.4
CPU Intermittent Operation Mode
The CPU intermittent operation mode causes the CPU to operate intermittently with an
operating clock supplied to the CPU or resources to reduce power consumption.
■ Operation in CPU Intermittent Operation Mode
The CPU intermittent operation mode halts the clock supplied to the CPU at every instruction execution
when the CPU accesses registers, internal memory, I/O, or resources delaying to start the internal bus.
Decreasing the CPU processing speed while supplying a high-speed clock to resources reduces the power
consumption.
• The count of machine cycles in which clock supply to the CPU halts is set by the CG1 and CG0 bits in
the low-power consumption mode control register (LPMCR).
• The instruction execution time in the CPU intermittent operation mode is determined by adding the
"normal execution time" to the "compensation value" obtained by multiplying "count of accesses to
registers, internal memory, and resources " by "halt cycle count".
Figure 3.8-5 shows the clock operation in the CPU intermittent operation mode.
Figure 3.8-5 Clock Operation in CPU Intermittent Operation Mode
Resource clock
CPU clock
Halt cycle
A instruction
execution
cycle
Starting of internal bus
133
CHAPTER 3 CPU
3.8.5
Standby Mode
The standby mode causes the standby control circuit to either stop supplying an
operation clock to the CPU and resources, or to stop the oscillation clock (HCLK) to
reduce power consumption.
■ Operating State in Each Standby Mode
Table 3.8-3 shows the operating state in each standby mode.
Table 3.8-3 Operating State in Each Standby Mode
Mode Name
Sleep mode
Transition
Condition
Oscillation
Clock (HCLK)
Subclock
(SCLK)
Machine
Clock
CPU
Resource
Pin
Cancellation
Main sleep
mode
MCS = 1
SCS = 1
SLP = 1
O
O
O
X
O
O
External reset or
interrupt
Sub-sleep
mode
MCS = X
SCS = 0
SLP = 1
X
O
O
X
O
O
External reset or
interrupt
PLL sleep
mode
MCS = 0
SCS = 1
SLP = 1
O
O
O
X
O
O
External reset or
interrupt
SPL = 0
MCS = X
SCS = 1
TMD = 0
O
O
X
X
X ∗1
SPL = 1
MCS = X
SCS = 1
TMD = 0
O
O
X
X
X ∗1
SPL = 0
MCS =X
SCS = 0
TMD = 0
X
O
X
X
X ∗2
SPL = 1
MCS = X
SCS = 0
TMD = 0
X
O
X
X
X ∗2
SPL = 0
STP = 1
X
X
X
X
X
SPL = 1
STP = 1
X
X
X
X
X
Timebase
timer mode
Watch mode
External reset or
interrupt ∗4
Hi-Z ∗3
External reset or
interrupt ∗5
Hi-Z ∗3
Note:
There is no subclock in MB90F387S and MB90387S.
134
External reset or
interrupt ∗5
External reset or
interrupt ∗6
Stop mode
O: Operate X: Stop
: Pre-transition state held Hi-Z: High-impedance
∗1: The timebase timer and the watch timer operate.
*2: The watch timer operates.
*3: DTP/external interrupt input pins operates
*4: Watch timer, timebase timer, and external interrupt
*5: Watch timer and external interrupt.
*6: External interrupt
MCS: PLL clock select bit of clock select register (CKSCR)
SCS: Subclock select bit of CKSCR
SPL: Pin state specify bit of low-power consumption mode control register (LPMCR)
SLP: Sleep mode bit of LPMCR
STP: Stop mode bit of LPMCR
TMD: Watch mode bit of LPMCR
External reset or
interrupt∗4
Hi-Z ∗3
External reset or
interrupt ∗6
CHAPTER 3 CPU
3.8.5.1
Sleep Mode
The sleep mode stops the operating clock to the CPU during an operation in each clock
mode. The CPU stops and the resources continue to operate.
■ Transition to Sleep Mode
When the mode transits to the sleep mode by setting the low-power consumption mode control register
(LPMCR: SLP = 1, STP = 0), the mode transits to the sleep mode according to the settings of the MCS and
SCS bits in the clock select register (CKSCR).
Table 3.8-4 shows the settings of the MCS and SCS bits in the clock select register (CKSCR) and the sleep
modes.
Table 3.8-4 Settings of MCS and SCS Bits in Clock Select Register (CKSCR) and Sleep
Modes
Clock Select Register (CKSCR)
Sleep Mode to be transited
MCS
SCS
1
1
Main sleep mode
0
1
PLL sleep mode
1
0
0
0
Sub-sleep mode
Notes:
• If both the STP and SLP bits in the low-power consumption mode control register (LPMCR) are
set to "1" simultaneously, the STP bit is preferred and the mode transits to the stop mode.
If the SLP bit is set to "1" and the TMD bit is set to "0" at the same time, the TMD bit is preferred
and the mode transits to the timebase timer mode or the watch mode.
• There is no subclock in MB90F387S and MB90387S.
● Data hold function
In the sleep mode, data in the dedicated registers such as accumulators and internal RAM are held.
● Operation when interrupt request generated
If an interrupt request is generated when the SLP bit in the low-power consumption mode control register
(LPMCR) is set to "1", the mode does not transit to the sleep mode. If the CPU is not ready to accept any
interrupt request, the instruction next to the currently executing instruction is executed. If the CPU is ready
to accept any interrupt request, an interrupt operation immediately branches to the interrupt processing
routine.
● Pin state
In the sleep mode, pins other than those used for bus input/output or bus control are held in the state before
transiting to the sleep mode.
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■ Return from Sleep Mode
The sleep mode is canceled by a reset factor or when an interrupt is generated.
● Return by reset factor
When the sleep mode is canceled by a reset factor, the mode transits to the main clock mode after the sleep
mode is canceled, transiting to the reset sequence.
Notes:
• When sub-sleep mode are returned to main clock mode using an external reset pin (RST pin),
input level "L" for at least "the oscillation time of the oscillator(*) + 100μs + 16 machine cycles".
*: The oscillation time of the oscillator is the time required to reach 90% of amplitude. It takes
several to dozens of ms for crystal oscillators, hundreds of μs to several ms for ceramic
oscillators, and 0s for external clocks.
• There is no subclock in MB90F387S and MB90387S.
● Return by interrupt
When a higher interrupt request than the interrupt level (IL) of 7 is generated from the resources in the
sleep mode, the sleep mode is canceled. After the sleep mode is canceled, as with normal interrupt
processing, the generated interrupt request is identified according to the settings of the I flag in the
condition code register (CCR), the interrupt level mask register (ILM), and the interrupt control register
(ICR).
• When the CPU is not ready to accept any interrupt request, the instruction next to the currently
executing instruction is executed.
• When the CPU is ready to accept any interrupt request, it branches immediately to the interrupt
processing routine.
Figure 3.8-6 shows the cancellation of sleep mode by an interrupt.
Figure 3.8-6 Cancellation of Sleep Mode by Interrupt
Set interrupt flag of resource
INT generated
(IL<7)
YES
I=0
NO
Sleep mode not cancelled
Sleep mode not cancelled
Sleep mode cancelled
YES
Next instruction executed
NO
ILM<IL
YES
NO
Interrupt processing
executed
Note:
When an interrupt processing is executed, the CPU usually proceeds to the interrupt processing
after executing the instruction next to the one specifying the sleep mode.
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CHAPTER 3 CPU
3.8.5.2
Watch mode
The watch mode operates only the subclock (SCLK) and the watch timer. The main
clock and PLL clock stop.
■ Transition to Watch Mode
In the subclock mode, when "0" is written to the TMD bit in the LPMCR register according to the settings
of the low-power consumption mode control register (LPMCR), the mode transits to the watch mode.
● Data hold function
In the watch mode, data in the dedicated registers such as an accumulator and internal RAM are held.
● Operation when interrupt request generated
When interrupt request is generated with the TMD bit of the low-power consumption mode control register
(LPMCR) set to "0", the mode does not transit to the watch mode. If the CPU is not ready to accept any
interrupt request, the instruction next to the currently executing instruction is executed. If the CPU is ready
to accept any interrupt request, it immediately branches to the interrupt processing routine.
● Pin state
In the watch mode, the input/output pins can be set to the high-impedance state or held in the state before
transiting to the watch mode according to the setting of the SPL bit in the low-power consumption mode
control register (LPMCR).
Notes:
• To set a pin to high impedance when the pin is shared by a peripheral function and a port in
watch mode, disable the output of peripheral functions, and set the TMD bit to "0".
This applies to the following pins:
P14/PPG0, P15/PPG1, P16/PPG2, P17/PPG3, P21/TOT0, P23/TOT1
• There is no subclock in MB90F387S and MB90387S.
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■ Return from Watch Mode
The watch mode is canceled by a reset factor or when an interrupt is generated.
● Return by reset factor
When the watch mode is canceled by a reset factor, the mode transits to the main clock mode after the
watch mode is canceled, transiting to the reset sequence.
Notes:
• When watch mode are returned to main clock mode using an external reset pin (RST pin), input
level "L" for at least "the oscillation time of the oscillator(*) + 100μs + 16 machine cycles (main
clock)".
*: The oscillation time of the oscillator is the time required to reach 90% of amplitude. It takes
several to some tens of ms for crystal oscillators, some hundreds of μs to several ms for
ceramic oscillators, and 0s for external clocks.
• There is no subclock in MB90F387S and MB90387S.
● Return by an interrupt
When an interrupt request higher than the interrupt level (IL) of 7 is generated from the watch timer and
external interrupt in the watch mode, the watch mode is canceled. After the watch mode is canceled, as
with normal interrupt processing, the generated interrupt request is identified according to the settings of
the I flag in the condition code register (CCR), the interrupt level mask register (ILM), and the interrupt
control register (ICR). In the sub-watch mode, no oscillation stabilization wait time is generated and the
interrupt request is identified immediately after return from the watch mode.
• When the CPU is not ready to accept any interrupt request, the instruction next to the currently
executing instruction is executed.
• When the CPU is ready to accept any interrupt request, it branches immediately to the interrupt
processing routine.
Notes:
• When an interrupt processing is executed, the CPU usually proceeds to the interrupt processing
after executing the instruction next to the one specifying the watch mode.
• There is no subclock in MB90F387S and MB90387S.
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CHAPTER 3 CPU
3.8.5.3
Timebase Timer Mode
The timebase timer mode operates only the oscillation clock (HCLK), subclock (SCLK),
timebase timer, and watch timer. Resources other than the timebase timer and watch
timer stop.
■ Transition to Timebase Timer Mode
The mode transits to the timebase timer mode when "0" is written to the TMD bit of the low-power
consumption mode control register (LPMCR) during operation in the PLL clock mode or the main clock
mode (CKSCR: SCM = 1).
● Data hold function
In the timebase timer mode, data in the dedicated registers such as an accumulator and internal RAM are
held.
● Operation when interrupts request generated
When an interrupt request is generated with the TMD bit of the low-power consumption mode control
register (LPMCR) set to "0", the mode does not transit to the timebase timer mode. When the CPU is not
ready to accept any interrupt request, the instruction next to the currently executing instruction is executed.
When the CPU is ready to accept any interrupt request, it branches immediately to the interrupt processing
routine.
● Pin state
In the timebase timer mode, the input/output pins can be set to the high-impedance state or held in the state
before transiting to the timebase timer mode according to the setting of the SPL bit in the low-power
consumption mode control register (LPMCR).
Note:
To set a pin to high impedance when the pin is shared by a peripheral function and a port in
timebase timer mode, disable the output of peripheral functions, and set the TMD bit to "0".
This applies to the following pins:
P14/PPG0, P15/PPG1, P16/PPG2, P17/PPG3, P21/TOT0, P23/TOT1
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CHAPTER 3 CPU
■ Return from Timebase Timer Mode
The timebase timer mode is canceled by a reset factor or when an interrupt is generated.
● Return by reset factor
When the timebase timer mode is canceled by a reset factor, the mode transits to the main clock mode after
the timebase timer mode is canceled, transiting to the reset sequence.
Note:
When the timebase timer mode is returned to main clock mode using an external reset pin (RST pin),
input level "L" for at least 100μs.
● Return by an interrupt
When an interrupt request higher than interrupt level (IL) of 7 is generated from the watch timer, timebase
timer, and external interrupt in the timebase timer mode, the timebase timer mode is canceled. After the
timebase timer mode is canceled, as with normal interrupt processing, the generated interrupt request is
identified according to the settings of the I flag in the condition code register (CCR), the interrupt level
mask register (ILM), and the interrupt control register (ICR).
• When the CPU is not ready to accept any interrupt request, the instruction next to the currently
executing instruction is executed.
• When the CPU is ready to accept any interrupt request, it branches immediately to the interrupt
processing routine.
• The following two timebase timer modes are available:
- Main clock ↔ timebase timer mode
- PLL clock ↔ timebase timer mode
Notes:
• At interrupt processing, the CPU usually proceeds to the interrupt processing after executing the
instruction next to the one specifying the timebase timer mode.
• When the timebase timer mode is returned by an interrupt, the interrupt processing is performed
after the maximum 80 μs after the interrupt request is accepted.
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CHAPTER 3 CPU
3.8.5.4
Stop Mode
The stop mode stops the oscillation clock (HCLK) and subclock (SCLK) during
operation in each clock mode. Data can be held with the minimum power consumption.
■ Stop Mode
When "1" is written to the STP bit of the low-power consumption mode control register (LPMCR) during
operation in the PLL clock mode (CKSCR : MCS=1, SCS=0), the mode transits to the stop mode according
to the settings of the MCS bit and SCS bit in the clock select register (CKSCR).
Table 3.8-5 shows the settings of the MCS and SCS bits in the clock select register (CKSCR) and the stop
modes.
Table 3.8-5 Settings of MCS and SCS Bits in Clock Select Register (CKSCR) and Stop Modes
Clock Select Register (CKSCR)
Stop Mode to be Transited
MCS
SCS
1
1
Main stop mode
0
1
PLL stop mode
1
0
0
0
Sub-stop mode
Notes:
• If both the STP and SLP bits in the low-power consumption mode control register (LPMCR) are
set to "1" simultaneously, the STP bit is preferred and the mode transits to the stop mode.
• There is no subclock in MB90F387S and MB90387S.
● Data hold function
In the stop mode, data in the dedicated registers such as accumulators and internal RAM are held.
● Operation when interrupt request generated
When an interrupt request is generated with the STP bit in the low-power consumption mode control
register (LPMCR) set to "1", the mode does not transit to the stop mode. When the CPU is not ready to
accept any interrupt request, the instruction next to the currently executing instruction is executed. If the
CPU is ready to accept any interrupt request, it immediately branches to the interrupt processing routine.
● Pin state
In the stop mode, the input/output pins can be set to the high-impedance state or held in the state before
transiting to the stop mode according to the setting of the SPL bit in the low-power consumption mode
control register (LPMCR).
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CHAPTER 3 CPU
Note:
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop
mode, disable the output of peripheral functions, and set the STP bit to "1".
This applies to the following pins:
P14/PPG0, P15/PPG1, P16/PPG2, P17/PPG3, P21/TOT0, P23/TOT1
■ Return from Stop Mode
The stop mode is canceled by a reset factor or when an interrupt is generated. At return from the stop mode,
the oscillation clock (HCLK) and the subclock (SCLK) stop, so the stop mode is canceled after the elapse
of the main clock oscillation stabilization wait time or the subclock oscillation stabilization wait time.
● Return by reset factor
When the stop mode is canceled by a reset factor, the main clock oscillation stabilization wait time is
generated. After the termination of the main clock oscillation stabilization wait time, the stop mode is
canceled, transiting to the reset sequence.
Figure 3.8-7 shows the return from the sub-stop mode by an external reset.
Figure 3.8-7 Return from the Sub-stop Mode by an External Reset
RST pin
Stop mode
Main clock
Oscillation stabilization wait
Oscillating
Subclock
Oscillation stabilization wait
Oscillating
PLL clock
CPU operation clock
CPU operation
Subclock
Stop
Reset sequence
Oscillation
stabilization wait
Oscillating
Main clock
PLL clock
Normal processing
Stop mode cancelled
Reset cancelled
Notes:
• When stop mode are returned from sub-sleep mode to main clock mode using an external reset
pin (RST pin), input level "L" for at least "the oscillation time of the oscillator(*) + 100μs + 16
machine cycles (main clock)".
*: The oscillation time of the oscillator is the time required to reach 90% of amplitude. It takes
several to some tens of ms for crystal oscillators, some hundreds of μs to several ms for
ceramic oscillators, and 0s for external clocks.
• There is no subclock in MB90F387S and MB90387S.
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CHAPTER 3 CPU
● Return by an interrupt
When an interrupt request higher than the interrupt level (IL) of 7 is generated from external interrupt in the
stop mode, the stop mode is canceled. In the stop mode, the main clock oscillation stabilization wait time or
the subclock oscillation stabilization wait time is generated after the stop mode is canceled. After the main
clock oscillation stabilization wait time or the subclock oscillation stabilization wait time is terminated, as
with normal interrupt processing, the generated interrupt request is identified according to the settings of
the I flag in the condition code register (CCR), the interrupt level mask register (ILM), and the interrupt
control register (ICR).
• When the CPU is not ready to accept any interrupt request, the instruction next to the currently
executing instruction is executed.
• When the CPU is ready to accept any interrupt request, it branches immediately to the interrupt
processing routine.
Notes:
• At interrupt processing, the CPU usually proceeds to the interrupt processing after executing the
instruction next to the one specifying the stop mode.
• In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL
stop mode, it is necessary to secure the main clock oscillation stabilization wait time and PLL
clock oscillation stabilization wait time. The oscillation stabilization wait times for the main clock
and PLL clock are counted simultaneously according to the value specified in the oscillation
stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register. The
oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register
must be selected accordingly to account for the longer of main clock and PLL clock oscillation
stabilization wait time. The PLL clock oscillation stabilization wait time, however, requires 214/
HCLK or more. Set the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the
clock selection register to "10B" or "11B".
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CHAPTER 3 CPU
3.8.6
State Transition in Standby Mode
The operating state and state transition in the clock mode and standby mode in the
MB90385 series are shown in the diagram.
■ State Transition Diagram
Figure 3.8-8 State Transition Diagram
Power-on
External reset, watchdog timer reset, and software reset
Power-on reset
Reset
SCS=0
SCS=1
Oscillation stabilization
waiting terminated
Main clock mode
MCS=0
PLL clock mode
MCS=1
SLP=1
Interrupt
Main sleep mode
TMD=0
Interrupt
Main timebase
timer mode
STP=1
Oscillation stabilization
waiting terminated
Main clock oscillation
stabilization waiting
Subclock mode
SCS=1
SLP=1
Interrupt
PLL sleep mode
TMD=0
Interrupt
PLL timebase
timer mode
STP=1
Main stop mode
Interrupt
SCS=0
Interrupt
Sub-sleep mode
TMD=0
Interrupt
Watch mode
STP =1
PLL stop mode
Interrupt
SLP=1
Oscillation stabilization
waiting terminated
Main clock oscillation
stabilization waiting
Sub-stop mode
Interrupt
Oscillation stabilization
waiting terminated
Subclock oscillation
stabilization waiting
Notes:
• In attempting to switch the clock mode, do not attempt to switch to another clock mode or lowpower consumption mode until the first switching is completed. The MCM and SCM bits of the
clock selection register (CKSCR) indicate that switching is completed. If the mode is switched to
another clock mode or low-power-consumption mode before completion of switching, the mode
may not be switched.
• There is no subclock in MB90F387S and MB90387S.
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CHAPTER 3 CPU
3.8.7
Pin State in Standby Mode, at Reset
The state of input/output pins in the standby mode and at reset is shown in each access
mode.
■ State of Input/Output Pins (Single-chip Mode)
Table 3.8-6 State of Input/Output Pins (Single-chip Mode)
Stop/Watch/Timebase timer
Pin Name
Sleep
Reset
SPL = 0
SPL = 1
P07 to P10
P27 to P20
P37 to P35, p33 to p30
Immediately-preceding
state held *1
P44 to P40
Input cut off/
immediately-preceding
state held*1
Input cut off/
output Hi-Z *2
Input disabled/
output Hi-Z
P57 to P50
*1: Indicates that state of pins output immediately before entering each standby mode is output as it is or "input disabled".
"State of pins output is output as it is" means that if the resource output is in operation, the state of pins is output
according to the state of the resource and if the state of output pins is output, it is held. "Input disabled" means that no
pin value can be accepted internally because the operation of the input gates of pins is enabled but the internal circuit
stops.
*2: In the input shutoff state, the input is masked and the "L" level is passed to the internal. The "output Hi-Z" means that
the driving of pin driving transistors is disabled to set pins to the high-impedance state.
Note:
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop
mode, watch mode or timebase timer mode, disable the output of peripheral functions, and set the
STP bit to "1" or set the TMD bit to "0".
This applies to the following pins:
P14/PPG0, P15/PPG1, P16/PPG2, P17/PPG3, P21/TOT0, P23/TOT1
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CHAPTER 3 CPU
3.8.8
Precautions when Using Low-power Consumption Mode
This section explains the precautions when using the low-power consumption modes.
■ Transition to Standby Mode
When an interrupt request is generated from the resource to the CPU, the mode does not transit to each
standby mode even after setting the STP and SLP bits in the low-power consumption mode control register
(LPMCR) to "1" and the TMD bit to "0" (and also even after interrupt processing).
If the CPU is in interrupt processing, the interrupt request flag during interrupt processing is cleared and the
mode can transit to each standby mode if no other interrupt requests are generated.
■ Cancellation of Standby Mode by Interrupt
When an interrupt request higher than the interrupt level (IL) of 7 is generated from the resource and
external interrupt during operation in the sleep mode, watch mode, timebase timer mode, or stop mode, the
standby mode is canceled. The standby mode is canceled by an interrupt regardless of whether the CPU
accept interrupts or not.
Notes:
• Take measures, such as disabling interrupts, not to branch to the interrupt processing
immediately after return from the standby mode.
• There is no subclock in MB90F387S and MB90387S.
■ Notes on the Transition to Standby Mode
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode,
watch mode, or timebase timer mode, use the following procedure:
1. Disable the output of peripheral functions.
2. Set the SPL bit to "1", STP bit to "1", or TMD bit to "0" in the low-power consumption mode control
register (LPMCR).
Note:
There is no subclock in MB90F387S and MB90387S.
■ Note on Cancelling Standby Mode
The standby mode can be canceled by an input according to the settings of an input factor of an external
interrupt. The system enters the stop mode. The input factor can be selected from High level, Low level,
rising edge, and falling edge.
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CHAPTER 3 CPU
■ Oscillation Stabilization Wait Time
● Oscillation stabilization wait time of main clock
In the subclock mode, watch mode, or stop mode, the oscillation of the main clock stops and the oscillation
stabilization wait time of the main clock is required. The oscillation stabilization wait time of the main
clock is set by the WS1 and WS0 bits in the clock select register (CKSCR).
● Oscillation stabilization wait time of subclock
In the sub-stop mode, the oscillation of the subclock stops and the oscillation stabilization wait time of the
subclock is required. The oscillation stabilization wait time of the subclock is fixed at 214/SCLK (SCLK:
subclock).
● Oscillation stabilization wait time of PLL clock
In main clock mode, the PLL multiplication circuit stops. When changing to PLL clock mode, it is
necessary to reserve the PLL clock oscillation stabilization wait time. The CPU runs in main clock mode
till the PLL clock oscillation stabilization wait time has elapsed. When the main clock is switched to PLL
clock mode, the PLL clock oscillation stabilization wait time is fixed at 214/HCLK (HCLK: oscillation
clock).
In subclock mode, the main clock and PLL multiplication circuit stop. When changing to PLL clock mode,
it is necessary to reserve the main clock oscillation stabilization wait time and PLL clock oscillation
stabilization wait time. The oscillation stabilization wait times for main clock and PLL clock are counted
simultaneously according to the value specified in the oscillation stabilization wait time selection bits
(CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection bits
(CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the longer
of the main clock and PLL clock oscillation stabilization wait times. The PLL clock oscillation
stabilization wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time
selection bits (CKSCR: WS1, WS0) in the clock selection register to "10B" or "11B".
In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL stop
mode, it is necessary to secure the main clock oscillation stabilization wait time and PLL clock oscillation
stabilization wait time. The oscillation stabilization wait times for the main clock and PLL clock are
counted simultaneously according to the value specified in the oscillation stabilization wait time selection
bits (CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection
bits (CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the
longer of main clock and PLL clock oscillation stabilization wait time. The PLL clock oscillation
stabilization wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time
selection bits (CKSCR: WS1, WS0) in the clock selection register to "10B" or "11B".
■ Transition of Clock Mode
When transiting a clock mode, do not transit a clock mode to any other clock mode or a low-power
consumption mode until the completion of transition. Refer the MCM and SCM bits in the clock select
register (CKSCR) to check that the transition of a clock mode is completed. If the mode is switched to
another clock mode or low-power-consumption mode before completion of switching, the mode may not be
switched.
Note:
There is no subclock in MB90F387S and MB90387S.
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CHAPTER 3 CPU
■ Notes on Accessing the Low-power Consumption Mode Control Register (LPMCR) to
Enter the Standby Mode
• To access the low-power consumption mode control register (LPMCR) with assembler language
- To set the low-power consumption mode control register (LPMCR) to enter the standby mode, use
the instruction listed in Table 3.8-2.
- The low-power consumption mode transition instruction in Table 3.8-2 must always be followed
by an array of instructions highlighted by a dotted line below.
MOV LPMCR,#H’XX ; the low-power consumption mode transition instruction in Table 3.8-2
NOP
NOP
JMP
$+3
MOV A,#H’10
; jump to next instruction
; any instruction
The devices do not guarantee its operation after returning from the standby mode if you place an array
of instructions other than the one enclosed in the dotted line.
• To access the low-power consumption mode (LPMCR) with C language
To enter the standby mode using the low-power consumption mode control register (LPMCR), use one
of the following methods (1) to (3) to access the register:
(1) Specify the standby mode transition instruction as a function and insert two _wait_nop() built-in
functions after that instruction. If any interrupt other than the interrupt to return from the standby
mode can occur within the function, optimize the function during compilation to suppress the
LINK and UNLINK instructions from occurring.
Example: Watch mode or timebase timer mode transition function
void enter_watch(){
IO_LPMCR.byte = 0x10;
/* Set LPMCR TMD bit to "0" */
_wait_nop();
_wait_nop();
}
(2) Define the standby mode transition instruction using _asm statements and insert two NOP and JMP
instructions after that instruction.
Example: Transition to sleep mode
_asm(" MOVI: _IO_LPMCR,#H’58); /* Set LPMCR SLP bit to "1" */
_asm(" NOP");
_asm(" NOP");
_asm(" JMP
$+3");
/* Jump to next instruction */
(3) Define the standby mode transition instruction between #pragma asm and #pragma endasm and
insert two NOP and JMP instructions after that instruction.
Example: Transition to stop mode
#pragma asm
MOV I: _IO_LPMCR,#H’98
/* Set LPMCR STP bit to "1" */
NOP
NOP
JMP $+3
#pragma endasm
148
/* Jump to next instruction */
CHAPTER 3 CPU
3.9
CPU Mode
The F2MC-16LX family enables the transition of operation modes and memory access
modes to set the CPU operation and access modes and areas.
■ Classification of Modes
Table 3.9-1 shows the classification of operation modes and memory access modes for the F2MC-16LX
family. Each mode is set by mode pins (MD2 to MD0) in reset and mode-fetched mode data.
Table 3.9-1 Classification of Modes
Memory Access Modes
Operation Modes
Bus Modes
RUN modes
Single-chip mode (Internal-ROM internal-bus mode)
Flash serial programming mode
−
Flash memory mode
−
■ Operation Mode
The operation modes control the operating state of the device and are set by the mode pins (MD2 to MD0).
● RUN mode
The RUN mode is the normal CPU operation mode. It provides various low-power consumption modes,
such as the main clock mode, PLL clock mode, and subclock mode.
Reference:
For details of the low-power consumption modes, see Section "3.8 Low-power Consumption Mode".
● Flash serial programming mode and flash memory mode
Some products in the MB90385 series have user-programmable flash memory.
The flash serial programming mode is that for serially programming data to flash memory.
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CHAPTER 3 CPU
3.9.1
Mode Pins (MD2 to MD0)
The mode pins are three external pins of MD2 to MD0, and enable a combination of
these pins to set the following:
• Operation modes (RUN mode, flash serial programming mode, flash memory mode)
• Reading reset vectors and mode data
■ Setting of Mode Pins (MD2 to MD0)
Table 3.9-2 shows the settings of the mode pins.
Table 3.9-2 Setting of Mode Pins
Mode Pin*
Mode Name
MD2
MD1
MD0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
Flash serial programming mode
1
1
1
Flash memory mode
Setting disabled
Internal vector mode
Setting disabled
*: Set MD2 to MD0: 0 = VSS or 1 = VCC.
● Internal vector mode
Reset vectors are read from internal ROM.
● Flash serial programming mode
Flash serial programming C cannot be performed just by the settings of the mode pins.
Reference:
For details of flash serial programming, see "CHAPTER 19
CONNECTION".
● Flash memory mode
This mode is set when using a parallel writer.
150
FLASH SERIAL PROGRAMMING
CHAPTER 3 CPU
■ Setting Mode Pins
Set the mode pins as shown in Figure 3.9-1.
Figure 3.9-1 Flow of Mode Pin Setting
Set mode pin
Data programmed
to flash memory
NO
YES
Flash
programming
mode
Internal vector
mode
MD2 MD1 MD0 MD2 MD1 MD0
"1" "1" "1"
"0" "1" "1"
MD0 to MD2: Set 0 = Vss and 1 = Vcc.
Do not set value except the value described above.
151
CHAPTER 3 CPU
3.9.2
Mode Data
Mode data is used to set the memory access mode. It is automatically read to the CPU
by mode fetch.
■ Mode Data
The values of the mode register can be changed only in the reset sequence. The changed mode register
values are enabled after the reset sequence.
Figure 3.9-2 Mode Data
7
6
5
4
3
2
1
0
bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Reserved bits
Reserved
0
R/W : Read/Write
X
: Undefined
: Reset value
Always set to "0"
bit 7
M1
bit 6
M0
0
0
0
1
1
0
1
1
Bus mode setting bits
Single-chip mode
Setting disable
Table 3.9-3 Function of Mode Register
Bit Name
bit 7,
bit 6
bit 5 to bit 0
152
Function
M1, M0:
Bus mode setting bit
Always set these bits to "00B".
Reserved: Reserved bits
Always write "0" to these bits.
CHAPTER 3 CPU
■ Setting Mode Data
Set mode data according to Figure 3.9-3.
Figure 3.9-3 Flow of Mode Data Setting
Set mode data
Single-chip
mode
Single-chip
mode
Mode data "00H"
Do not set mode data to value
except the value described above.
153
CHAPTER 3 CPU
3.9.3
Memory Access Mode
The memory access mode is the following one mode: bus mode and external access mode.
• Bus mode: Sets access area (internal)
■ Bus Mode
Figure 3.9-4 shows the memory map in the mode.
Figure 3.9-4 Memory map in the mode
When ROM mirror function is enabled
000000H
0000C0H
000100H
Resource
RAM area
Register
Address#1
003900H
Extend I/O area
004000H
ROM area
(image of FF bank)
010000H
FE0000H
ROM area *
FF0000H
ROM area
FFFFFFH
: Internal access memory
: Access disabled
* : When the area from "FE0000H" to "FEFFFFH" of MB90387 or MB90F387
is read out, the data "FF0000H" to "FFFFFFH" can be read.
Reference:
For details of the access area, see Section "3.1 Memory Space".
● Single-chip mode (internal-ROM internal-access)
• Only internal ROM and internal RAM are used and no external access occurs.
• Ports 1 to 3 can be used as general-purpose I/O ports.
154
CHAPTER 3 CPU
3.9.4
Selection of Memory Access Mode
This section explains selection of the memory access mode in the reset sequence.
■ Selection of Memory Access Mode
After reset is canceled, the CPU selects the memory access mode according to the procedure shown in
Figure 3.9-5 by referencing the settings of the mode pins and mode data.
Figure 3.9-5 Selection of Memory Access Mode
Reset factor
How mode pins
(MD2, MD1, and MD0)
are set?
Check of mode pin
Internal data read
to internal ROM
All I/O pins in highimpedance state
Reset factor
cancellation waiting
(External reset or
oscillation stabilization wait time)
Reset operating?
YES
NO
Fetch mode data and reset
vector from internal ROM
Mode fetch
(M1,M0="00B")
M1 and M0 bits
of mode data
Check mode data
Set to single-chip mode
155
CHAPTER 3 CPU
156
CHAPTER 4
I/O PORT
This chapter describes the function and operation of the
I/O port.
4.1 Overview of I/O Port
4.2 Registers of I/O Port
4.3 Port 1
4.4 Port 2
4.5 Port 3
4.6 Port 4
4.7 Port 5
157
CHAPTER 4 I/O PORT
4.1
Overview of I/O Port
I/O ports can be used as general-purpose I/O ports (parallel I/O ports). In the MB90385
series, there are five ports (34 pins).
Each port also serves as a resource I/O pins.
■ I/O Port Function
The I/O ports enable the port data register (PDR) to output data to the I/O pins from the CPU and fetch
signals input to the I/O ports. These also enable the port direction register (DDR) to set a direction for the I/O
pins in unit of bits.
The following shows the function of each port, and the resources that it also serves as:
• Port 1: Serves as both general-purpose I/O port and PPG timer output, or input capture input
• Port 2: Serves as both general-purpose I/O port and reload timer I/O, or external interrupt input pin
• Port 3: Serves as both general-purpose I/O port or A/D converter start trigger pin
• Port 4: Serves as both general-purpose I/O port and UART1 I/O or CAN controller transmit/receive pin
• Port 5: Serves as both general-purpose I/O port and analog input pin
Table 4.1-1 List of Each Port Functions
Port
Name
Output
Type
Function
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
P10/IN0 to
P13/IN3
CMOS
Generalpurpose I/O
port
P17
P16
P15
P14
P13
P12
P11
P10
P14/PPG0 to
P17/PPG3
CMOS
high
current
Resource
PPG3
PPG2
PPG1
PPG0
IN3
IN2
IN1
IN0
P27
P26
P25
P24
P23
P22
P21
P20
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
P37
P36* /
X1A
P35* /
X0A
−
P33
P32
P31
P30
ADTG
−
−
−
−
−
−
−
Generalpurpose I/O
port
−
−
−
P44
P43
P42
P41
P40
Resource
−
−
−
RX
TX
SOT1
SCK1
SIN1
Generalpurpose I/O
port
P57
P56
P55
P54
P53
P52
P51
P50
Analog
input pin
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Pin Name
Input Type
Port 1
Port 2
Port 3
P20/TIN0 to
P27/INT7
Generalpurpose I/O
port
CMOS
(hysteresis)
Resource
Generalpurpose I/O
port
P30 to P33
P35/X0A to
P37/ADTG
Resource
CMOS
Port 4
Port 5
P40/SIN1 to
P44/RX
P50/AN0 to
P57/AN7
Analog/
CMOS
(hysteresis)
*: If the low-speed oscillation pin is selected (for MB90387 or MB90F387), P35 and P36 pins cannot be used.
158
CHAPTER 4 I/O PORT
Note:
Port 5 also serves as analog input pins. When using these ports as general-purpose ports, always
set each bit of the analog input enable register (ADER) corresponding to each pin of the ports to "0".
ADER bit is "1" at a reset.
159
CHAPTER 4 I/O PORT
4.2
Registers of I/O Port
The registers related to I/O port setting are listed as follows.
■ Registers of I/O Ports
Table 4.2-1 lists the registers of each port.
Table 4.2-1 Registers of Each Port
Register Name
Read/Write
Address
Initial Value
Port 1 data register (PDR1)
R/W
000001H
XXXXXXXXB
Port 2 data register (PDR2)
R/W
000002H
XXXXXXXXB
Port 3 data register (PDR3)
R/W
000003H
XXXXXXXXB
Port 4 data register (PDR4)
R/W
000004H
XXXXXXXXB
Port 5 data register (PDR5)
R/W
000005H
XXXXXXXXB
Port 1 direction register (DDR1)
R/W
000011H
00000000B
Port 2 direction register (DDR2)
R/W
000012H
00000000B
Port 3 direction register (DDR3)
R/W
000013H
000X0000B
Port 4 direction register (DDR4)
R/W
000014H
XXX00000B
Port 5 direction register (DDR5)
R/W
000015H
00000000B
Analog input enable register (ADER)
R/W
00001BH
11111111B
R/W: Readable/Writable
X: Undefined value
160
CHAPTER 4 I/O PORT
4.3
Port 1
Port 1 is a general-purpose I/O port that serves as the resource I/O pin. When the singlechip mode is set, use port 1 by switching between the resource pin and the generalpurpose I/O port.
The function as a general-purpose I/O port is mainly described here. The configuration,
pin assignment, block diagram of the pins, and registers for port 1 are shown below.
■ Configuration of Port 1
Port 1 consists of the following three elements:
• General-purpose I/O port, resource I/O pin (P10/IN0 to P17/PPG3)
• Port 1 data register (PDR1)
• Port 1 direction register (DDR1)
■ Pin Assignment of Port 1
• When the single-chip mode is set, use port 1 by switching between the resource pin and the generalpurpose I/O port.
• Since port 1 serves as a resource pin, it cannot be used as a general-purpose I/O port when used as
resources.
• When using port 1 as the input pin of the resource, set the pin corresponding to the resource in the
DDR1 as an input port.
• When using port 1 as the output pin of the resource, set the output of the corresponding resource to
"enabled". Port 1 functions as the output pin of the resource regardless of the settings of the DDR1
Table 4.3-1 shows the pin assignment of port 1.
Table 4.3-1 Pin Assignment of Port 1
Port
Name
I/O Type
Pin Name
Port Function
Resource
Input
P10/IN0
P10
IN0
P11/IN1
P11
IN1
P12/IN2
P12
IN2
P13/IN3
P13
P14/PPG0
P14
P15/PPG1
P15
Port 1
Generalpurpose I/O
port
Input capture
input
IN3
P16/PPG2
P16
PPG2
P17/PPG3
P17
PPG3
CMOS
D
CMOS
(hysteresis)
PPG0
PPG1
Output
Circuit
Type
PPG timer
output
CMOS
high current
G
Reference:
For the circuit type, see Section "1.7 I/O Circuit".
161
CHAPTER 4 I/O PORT
■ Block Diagram of Port 1 Pins (in Single Chip Mode)
Figure 4.3-1 Block Diagram of Port 1 Pins
Resource input
Resource output
Internal data bus
Port data register (PDR)
Resource output enable
PDR read
P-ch
Output latch
PDR write
Pin
Port direction register (DDR)
N-ch
Direction latch
DDR write
Standby control (SPL = 1)
DDR read
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and watch mode (SPL = 1)
■ Registers for Port 1 (in Single Chip Mode)
• The registers for port 1 are PDR1 and DDR1.
• The bits composing each register correspond to the pins of port 1 one-to-one.
Table 4.3-2 shows the correspondence between the registers and pins of port 1.
Table 4.3-2 Correspondence between Registers and Pins for Port 1
Port
Name
Bits of Related Registers and Corresponding Pins
PDR1, DDR1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Corresponding pin
P17
P16
P15
P14
P13
P12
P11
P10
Port 1
162
CHAPTER 4 I/O PORT
4.3.1
Registers for Port 1 (PDR1, DDR1)
The registers for port 1 are explained.
■ Function of Registers for Port 1 (in Single Chip Mode)
● Port 1 data register (PDR1)
• Port 1 data register indicates the state of the pins.
● Port 1 direction register (DDR1)
• The port 1 direction register sets the input/output directions.
• When the bit corresponding to the pin is set to "1", port 1 functions as an output port. When the bit is set
to "0", port 1 functions as an input port.
Table 4.3-3 shows the functions of the registers for port 1.
Table 4.3-3 Function of Registers for Port 1
Register Name
Data
At Read
At Write
0
"0" is set for the output latch. When
The pin state
the pin is an output port pin, the Low
is Low level.
level is output to the pin.
1
"1" is set for the output latch. When
The pin state
the pin is an output port pin, the High
is High level.
level is output to the pin.
0
The direction The output buffer is set to OFF, and
latch is "0". the pin becomes an input port pin.
1
The direction The output buffer is set to ON, and
latch is "1". the pin becomes an output port pin.
Port 1 data register
(PDR1)
Port 1 direction
register (DDR1)
Read/
Write
Register
Address
Reset Value
R/W
000001H
XXXXXXXXB
R/W
000011H
00000000B
R/W: Read/Write
X: Undefined value
References:
• When using port 1 as the input pin of the resource, clear the bit in the DDR1 corresponding to the
input pin of the resource to "0" and set the input pin as an input port.
• When using port 1 as the output pin of the resource, set the output of the corresponding resource
to "enabled". Port 1 functions as the output pin of the resource regardless of the settings of the
DDR1.
163
CHAPTER 4 I/O PORT
4.3.2
Operation of Port 1
The operation of port 1 is explained.
■ Operation of Port 1 (in Single Chip Mode)
● Operation of output port
• When the bit in the port 1 direction register (DDR1) corresponding to the output pin is set to "1", port 1
functions as an output port.
• When the output buffer is turned ON and output data is written to the port 1 data register (PDR1), the
data is retained in the output latch and output from the pin.
• When the PDR1 is read, the state of the output latch in the PDR1 is read.
Note:
If read modify write (RMW) instructions (such as the bit set instruction) are used to read the PDR, the
pin set as an output port by the DDR outputs the desired data. However, the pin set as an input port
outputs data after the input state is written to the output latch. When switching from the input port to
the output port, write data to the PDR and set the pin as an output port in the DDR.
● Operation of input port
• If the bit in the DDR corresponding to the input pin is set to "0", port 1 functions as an input port.
• The output buffer is turned OFF and the pin enters the high impedance state.
• When data is written to the PDR1, it is retained in the output latch in the PDR1 but not output to the pin.
• When the PDR1 is read, the level value (Low or High) of the pin is read.
● Operation of resource output
• When using port 1 as the output pin of the resource, set the resource output to "enabled".
• Since the resource output is preferred enabled, the resource output functions regardless of the settings of
the DDR1.
• When the pin state is read with the resource output set to "enabled", the output state of the resource is
read.
● Operation of resource input
• The state of the pin that serves as the resource input is input to the resource.
• When using port 1 as the input pin of the resource, clear the bit in the DDR1 corresponding to the input
pin of the resource to "0" and set the input pin as an input port.
164
CHAPTER 4 I/O PORT
● Operation at reset
• When the CPU is reset, the value of the DDR1 is cleared to "0". Consequently, all output buffers are set
to OFF (the pin becomes an input port pin), and the pin enters the high-impedance state.
• The PDR1 is not initialized by reset. Therefore, when using port 1 as an output port, it is necessary to set
output data in the PDR1, and then set the bit in the DDR1 corresponding to the output pin to "1", and
then, to output.
● Operation in stop mode, timebase timer mode or watch mode
When the pin state specification bit of the low power consumption mode control register (LPMCR: SPL) is
"1", at a transition to the stop mode, timebase timer mode or watch mode, the pin enters the highimpedance state. Because the output buffer is forcibly set to OFF irrespective of the value of the DDR1.
Table 4.3-4 shows the state of the port 1 pins.
Table 4.3-4 State of Port 1 Pins
Pin Name
Normal Operation
Sleep Mode
Stop Mode, Timebase Timer Mode or Watch
Mode
SPL=0
P10/IN0 to
P17/PPG3
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O
port
SPL=1
Input cut off, and output
becomes Hi-Z (Pull-up
resistor disconnected)
SPL: Pin state specification bit of low power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
Note:
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop
mode, watch mode or timebase timer mode, disable the output of peripheral functions, and set the
STP bit to "1" or set the TMD bit to "0".
This applies to the following pins:
P14/PPG0, P15/PPG1, P16/PPG2, P17/PPG3
165
CHAPTER 4 I/O PORT
4.4
Port 2
Port 2 is a general-purpose I/O port that serves as the resource I/O pin. Use port 2 by
switching between the resource pin and the general-purpose I/O port.
The function as a general-purpose I/O port is mainly described here. The configuration,
pin assignment, block diagram of the pins, and registers for port 2 are shown below.
■ Configuration of Port 2
Port 2 consists of the following four elements:
• General-purpose I/O port, resource I/O pin (P20/TIN0 to P27/INT7)
• Port 2 data register (PDR2)
• Port 2 direction register (DDR2)
• High address control register (HACR)
■ Pin Assignment of Port 2
• Use port 2 by switching between the resource pin and the general-purpose I/O port.
• Since port 2 serves as resource pin, when used as a resource pin, port 2 cannot be used as generalpurpose I/O port.
• When using port 2 as the input pin of the resource, set the pin corresponding to the resource in the
DDR2 as an input port.
• When using port 2 as the output pin of the resource, set the output of the corresponding resource to
"enabled". Port 2 functions as the output pin of the resource regardless of the settings of the DDR2.
Table 4.4-1 shows the pin assignment for port 2.
Table 4.4-1 Pin Assignment of Port 2
Port
Name
I/O Type
Pin Name
Port Function
Resource
Input
P20/TIN0
P20
TIN0
16-bit reload timer 0 input
P21/TOT0
P21
TOT0
16-bit reload timer 0 output
P22/TIN1
P22
TIN1
16-bit reload timer 1 input
TOT1
16-bit reload timer 1 output
Generalpurpose I/O
port
P23/TOT1
P23
P24/INT4
P24
P25/INT5
P25
INT5
P26/INT6
P26
INT6
P27/INT7
P27
INT7
Port 2
INT4
External interrupt input
Reference:
For the circuit type, see Section "1.7 I/O Circuit".
166
CMOS
(hysteresis)
Output
CMOS
Circuit
Type
D
CHAPTER 4 I/O PORT
■ Block Diagram of Pins of Port 2 (General-purpose I/O Port)
Figure 4.4-1 Block Diagram of Pins of Port 2
Resource input
Resource output
Internal data bus
Port data register (PDR)
Resource output enable
PDR read
P-ch
Output latch
PDR write
Pin
Port direction register (DDR)
N-ch
Direction latch
DDR write
Standby control (SPL = 1)
DDR read
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and watch mode (SPL = 1)
■ Registers for Port 2
• The registers for port 2 are PDR2 and DDR2.
• The bits composing each register correspond to the pins of port 2 one-to-one.
Table 4.4-2 shows the correspondence between the registers and pins of port 2.
Table 4.4-2 Correspondence between Registers and Pins for Port 2
Port
Name
Bits of Related Registers and Corresponding Pins
PDR2, DDR2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Corresponding pin
P27
P26
P25
P24
P23
P22
P21
P20
Port 2
167
CHAPTER 4 I/O PORT
4.4.1
Registers for Port 2 (PDR2, DDR2)
The registers for port 2 are explained.
■ Function of Registers for Port 2
● Port 2 data register (PDR2)
Port 2 data register indicates the input/output state of the pins.
● Port 2 direction register (DDR2)
• The port 2 direction register sets the input/output directions.
• When the bit corresponding to the pin is set to "1", port 2 functions as an output port. When the bit is set
to "0", port 2 functions as an input port.
Table 4.4-3 shows the functions of the registers for port 2.
Table 4.4-3 Function of Registers for Port 2
Register Name
Data
At Read
At Write
0
"0" is set for the output latch, and
The pin state
when the pin is an output port pin, the
is Low level.
Low level is output to the pin.
1
The pin state "1" is set for the output latch, and
is High
when the pin is an output port pin, the
level.
High level is output to the pin.
0
The
direction
latch is "0".
1
The
direction
latch is "1".
Port 2 data register
(PDR2)
Port 2 direction
register (DDR2)
Read/
Write
Register
Address
Reset Value
R/W
000002H
XXXXXXXXB
R/W
000012H
00000000B
The output buffer is set to OFF, and
the pin becomes an input port pin.
The output buffer is set to ON, and
the pin becomes an output port pin.
R/W: Read/Write
X: Undefined value
References:
• When using port 2 as the input pin of the resource, clear the bit in the DDR2 corresponding to the
input pin of the resource to "0" and set the input pin as an input port.
• When using port 2 as the output pin of the resource, set the output of the corresponding resource
to "enabled". Port 2 functions as the output pin of the resource regardless of the settings of the
DDR2.
168
CHAPTER 4 I/O PORT
4.4.2
Operation of Port 2
The operation of port 2 is explained.
■ Operation of Port 2 (General-purpose I/O Port)
● Operation of output port
• When the bit in the port 2 direction register (DDR2) corresponding to the output pin is set to "1", port 2
functions as an output port.
• When the output buffer is turned ON and output data is written to the port 2 data register (PDR2), the
data is retained in the output latch and output from the pin.
• When the PDR2 is read, the state of the output latch in the PDR2 is read.
Note:
If read modify write (RMW) instructions (such as the bit set instruction) are used to read the PDR, the
pin set as an output port by the DDR outputs the desired data. However, the pin set as an input port
outputs data after the input state is written to the output latch. When switching from the input port to
the output port, write data to the PDR and set the pin as an output port in the DDR.
● Operation of input port
• If the bit in the DDR2 corresponding to the input pin is set to "0", port 2 functions as an input port.
• The output buffer is turned OFF and the pin enters the high impedance state.
• When data is written to the PDR2, it is retained in the output latch in the PDR2 but not output to the pin.
• When the PDR2 is read, the level value (Low or High) of the pin is read.
● Operation of resource output
• When using port 2 as the output pin of the resource, set the resource output to "enabled".
• Since the resource output is preferred enabled, the resource output functions regardless of the settings of
the DDR2.
• When the pin state is read with the resource output set to "enabled," the output state of the resource is
read.
● Operation of resource input
• The state of the pin that serves as the input of the resource is input to the resource.
• When using port 2 as the input pin of the resource, clear the bit in the DDR2 corresponding to the input
pin of the resource to "0" and set the input pin to an input port.
169
CHAPTER 4 I/O PORT
● Operation at reset
• When the CPU is reset, the value of the DDR2 is initialized to "0". Consequently, all output buffers are
set to OFF (the pin becomes an input port pin), and the pin enters the high-impedance state.
• The PDR2 is not initialized by reset. Therefore, when using port 2 as an output port, it is necessary to set
output data in the PDR2, and then set the bit in the DDR2 corresponding to the output pin to "1", and
then, to output.
● Operation in stop mode, timebase timer mode or watch mode
When the pin state specification bit of the low power consumption mode control register (LPMCR: SPL) is
"1", at a transition to the stop mode, timebase timer mode or watch mode, the pin enters the highimpedance state. Because the output buffer is set forcibly to OFF irrespective of the value of the DDR2.
Table 4.4-4 shows the state of the port 2 pins.
Table 4.4-4 State of Port 2 Pins
Pin Name
Normal Operation
Sleep Mode
Stop Mode, Timebase Timer Mode or
Watch Mode
SPL=0
P20/TIN0 to
P27/INT7
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O
port
SPL=1
Input cut off, and output
becomes Hi-Z
SPL: Pin state specification bit of low power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
Note:
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop
mode, watch mode or timebase timer mode, disable the output of peripheral functions, and set the
STP bit to "1" or set the TMD bit to "0".
This applies to the following pins:
P21/TOT0, P23/TOT1
170
CHAPTER 4 I/O PORT
4.5
Port 3
Port 3 is a general-purpose I/O port that serves as the resource I/O pin. Use port 3 by
switching between the resource pin and the general-purpose I/O port.
The function as a general-purpose I/O port is mainly described here. The configuration,
pin assignment, block diagram of the pins, and registers for port 3 are shown below.
■ Configuration of Port 3
Port 3 consists of the following three elements:
• General-purpose I/O port, resource input pin (P30 to P33, P35*/X0A, P36*/X1A, P37/ADTG)
• Port 3 data register (PDR3)
• Port 3 direction register (DDR3)
■ Pin Assignment of Port 3
• Use port 3 by switching between the resource pin and the general-purpose I/O port.
• Since port 3 serves as a resource pin, when used as a resource pin, port 3 cannot be used as generalpurpose I/O port.
• When using port 3 as the resource input pin, set the pin corresponding to the resource in the DDR3 as an
input port.
Table 4.5-1 shows the pin assignment of port 3.
Table 4.5-1 Pin Assignment of Port 3
I/O Type
Port
Name
Port 3
Pin Name
Port Function
Resource
Input
Output
Circuit
Type
P30
P30
−
−
P31
P31
−
−
P32
P32
−
−
P33
P33
−
−
P35/X0A
P35*
−
−
P36/X1A
P36*
−
−
D/A
P37/ADTG
P37
ADTG
External trigger input
for A/D converter
D
General-purpose I/O
port
D
CMOS
(hysteresis)
CMOS
D/A
*: If the low-speed oscillation pin is selected (for MB90387 or MB90F387), P35 and P36 pins cannot be used.
Reference:
For the circuit type, see Section "1.7 I/O Circuit".
171
CHAPTER 4 I/O PORT
■ Block Diagram of Pins of Port 3
Figure 4.5-1 Block Diagram of Pins of Port 3
Resource input
Resource output
Internal data bus
Port data register (PDR)
Resource output enable
PDR read
P-ch
Output latch
PDR write
Pin
Port direction register (DDR)
N-ch
Direction latch
DDR write
Standby control (SPL = 1)
DDR read
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and watch mode (SPL = 1)
■ Registers for Port 3
• The registers for port 3 are PDR3 and DDR3.
• The bits composing each register correspond to the pins of port 3 one-to-one.
Table 4.5-2 shows the correspondence between the registers and pins of port 3.
Table 4.5-2 Correspondence between Registers and Pins for Port 3
Port
Name
Bits of Related Registers and Corresponding Pin
PDR3, DDR3
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Corresponding pin
P37
P36*
P35*
−
P33
P32
P31
P30
Port 3
*: There are no P35 and P36 pins in MB90387 and MB90F387.
172
CHAPTER 4 I/O PORT
4.5.1
Registers for Port 3 (PDR3, DDR3)
The registers for port 3 are explained.
■ Function of Registers for Port 3
● Port 3 data register (PDR3)
• Port 3 data register indicates the state of the pins.
● Port 3 direction register (DDR3)
• The port 3 direction register sets the input/output directions.
• When the bit corresponding to the pin is set to "1", port 3 functions as an output port. When the bit is set
to "0", port 3 functions as an input port.
Table 4.5-3 shows the functions of the registers for port 3.
Table 4.5-3 Function of Registers for Port 3
Register Name
Data
At Read
At Write
0
"0" is set for the output latch, and
The pin state
when the pin is an output port pin, the
is Low level.
Low level is output to the pin.
1
The pin state "1" is set for the output latch, and
is High
when the pin is an output port pin, the
level.
High level is output to the pin.
0
The
direction
latch is "0".
1
The
direction
latch is "1".
Port 3 data register
(PDR3)
Port 3 direction
register (DDR3)
Read/
Write
Register
Address
Reset Value
R/W
000003H
XXXXXXXXB
R/W
000013H
000X0000B
The output buffer is set to OFF, and
the pin becomes an input port pin.
The output buffer is set to ON, and
the pin becomes an output port pin
R/W: Read/Write
X: Undefined value
References:
• When using port 3 as the input pin of the resource, clear the bit in the DDR3 corresponding to the
input pin of the resource to "0" and set the input pin as an input port.
• When using port 3 as the output pin of the resource, set the output of the corresponding resource
to "enabled". Port 3 functions as the output pin of the resource regardless of the settings of the
DDR3.
173
CHAPTER 4 I/O PORT
4.5.2
Operation of Port 3
The operation of port 3 is explained.
■ Operation of Port 3 (General - purpose I/O Port)
● Operation of output port
• When the bit in the port 3 direction register (DDR3) corresponding to the output pin is set to "1", port 3
functions as an output port.
• When the output buffer is turned ON and output data is written to the port 3 data register (PDR3), the
data is retained in the output latch and output from the pin.
• When the PDR3 is read, the state of the output latch in the PDR3 is read.
Note:
If read modify write (RMW) instructions (such as the bit set instruction) are used to read the port data
register (PDR), the pin set as an output port by the port direction register (DDR) outputs the desired
data. However, the pin set as an input port outputs data after the input state is written to the output
latch. When switching from the input port to the output port, write data to the PDR and set the pin as
an output port in the DDR.
● Operation of input port
• If the bit in the DDR3 corresponding to the input pin is set to "0", port 3 functions as an input port.
• The output buffer is turned OFF and the pin enter the high impedance state.
• When data is written to the PDR3, it is retained in the output latch in the PDR3 but not output to the pin.
• When the PDR3 is read, the level value ("Low" or "High") of the pin is read.
● Operation of resource input
• The state of the pin that serves as a resource is input to the resource.
• When using port 3 as the input pin of the resource, clear the bit in the DDR3 corresponding to the input
pin of the resource to "0" and set the input pin as an input port.
● Operation at reset
• When the CPU is reset, the value of the DDR3 is cleared to "0". Consequently, all output buffers are set
to OFF (the pin becomes an input port pin), and the pin enters the high-impedance state.
• The PDR3 is not initialized by reset. Therefore, when using port 3 as an output port, it is necessary to set
output data in the PDR3, and then set the bit in the DDR3 corresponding to the output pin to "1" and to
output.
174
CHAPTER 4 I/O PORT
● Operation in stop mode, timebase timer mode or watch mode
• When the pin state specification bit of the low power consumption mode control register (LPMCR:
SPL) is "1", at a transition to the stop mode, timebase timer mode or watch mode, the pin enters the
high-impedance state. The output buffer is forcibly set to OFF irrespective of the value of the DDR3
register.
Table 4.5-4 shows the state of the port 3 pins.
Table 4.5-4 State of Port 3 Pins
Pin Name
Normal Operation
Sleep Mode
Stop Mode, Timebase Timer Mode or
Watch Mode
SPL=0
P30 to P33,
P35/X0A to P37/
ADTG
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O
port
SPL=1
Input cut off, and
output becomes Hi-Z
SPL: Pin state specification bit of low power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
175
CHAPTER 4 I/O PORT
4.6
Port 4
Port 4 is a general-purpose I/O port that serves as the resource I/O pin. Use port 4 by
switching between the resource pin and the general-purpose I/O port.
The function as a general-purpose I/O port is mainly described here. The configuration,
pin assignment, block diagram of the pins, and registers for port 4 are shown below.
■ Configuration of Port 4
Port 4 consists of the following three elements:
• General-purpose I/O port, resource I/O pin (P40/SIN1 to P44/RX)
• Port 4 data register (PDR4)
• Port 4 direction register (DDR4)
■ Pin Assignment of Port 4
• Use port 4 by switching between the resource pin and the general-purpose I/O port.
• Since port 4 serves as a resource pin, it cannot be used as a general-purpose I/O port when used as a
resource.
• When using port 4 as the input pin of the resource, set the pin corresponding to the resource in the
DDR4 as an input port.
• When using port 4 as the output pin of the resource, set the output of the corresponding resource to
"enabled". Port 4 functions as the output pin of the resource regardless of the settings of the DDR4.
Table 4.6-1 shows the pin assignment of port 4.
Table 4.6-1 Pin Assignment of Port 4
Port
Name
I/O Type
Pin Name
Port Function
Input
P40/SIN1
P40
SIN1
UART1 serial
data input
P41/SCK1
P41
SCK1
UART1 serial
clock I/O
P42/SOT1
P42
SOT1
UART1 serial
data output
Port 4
Generalpurpose I/O
port
P43/TX
P43
TX
CAN
controller
send output
P44/RX
P44
RX
CAN
controller
receive input
Reference:
For the circuit type, see Section "1.7 I/O Circuit".
176
Output
Circuit
Type
CMOS
D
Resource
CMOS
(hysteresis)
CHAPTER 4 I/O PORT
■ Block Diagram of Pins of Port 4
Figure 4.6-1 Block Diagram of Pins of Port 4
Resource input
Resource output
Internal data bus
Port data register (PDR)
Resource output enable
PDR read
P-ch
Output latch
PDR write
Pin
Port direction register (DDR)
N-ch
Direction latch
DDR write
Standby control (SPL = 1)
DDR read
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and watch mode (SPL = 1)
■ Registers for Port 4
• The registers for port 4 are PDR4 and DDR4.
• The bits composing each register correspond to the pins of port 4 one-to-one.
Table 4.6-2 shows the correspondence between the registers and pins of port 4.
Table 4.6-2 Correspondence between Registers and Pins for Port 4
Port
Name
Bits of Related Registers and Corresponding Pins
PDR4, DDR4
−
−
−
bit 4
bit 3
bit 2
bit 1
bit 0
Corresponding pin
−
−
−
P44
P43
P42
P41
P40
Port 4
177
CHAPTER 4 I/O PORT
4.6.1
Registers for Port 4 (PDR4, DDR4)
The registers for port 4 are explained.
■ Function of Registers for Port 4
● Port 4 data register (PDR4)
• Port 4 data register indicates the state of the pins.
● Port 4 direction register (DDR4)
• The port 4 direction register sets the input/output directions.
• When the bit corresponding to the pin is set to "1", port 4 functions as an output port. When the bit is set
to "0", port 4 functions as an input port.
Table 4.6-3 shows the functions of the registers for port 4.
Table 4.6-3 Function of Registers for Port 4
Register Name
Data
At Read
At Write
0
"0" is set for the output latch. When
The pin state
the pin is an output port pin, the Low
is Low level.
level is output to the pin.
1
The pin state "1" is set for the output latch. When
is High
the pin is an output port pin, the High
level.
level is output to the pin.
0
The
direction
latch is "0".
1
The
direction
latch is "1".
Port 4 data register
(PDR4)
Port 4 direction
register (DDR4)
Read/
Write
Register
Address
Reset Value
R/W
000004H
XXXXXXXXB
R/W
000014H
XXX00000B
The output buffer is set to "OFF", and
the pin becomes an input port pin.
The output buffer is set to "ON", and
the pin becomes an output port pin.
R/W: Read/Write
X: Undefined value
References:
• When using port 4 as the input pin of the resource, clear the bit in the DDR4 corresponding to the
input pin of the resource to "0" and set the input pin as an input port.
• When using port 4 as the output pin of the resource, set the output of the corresponding resource
to "enabled". Port 4 functions as the output pin of the resource regardless of the settings of the
DDR4.
178
CHAPTER 4 I/O PORT
4.6.2
Operation of Port 4
The operation of port 4 is explained.
■ Operation of Port 4
● Operation of output port
• When the bit in the port 4 direction register (DDR4) corresponding to the output pin is set to "1", port 4
functions as an output port.
• When the output buffer is turned "ON" and output data is written to the port 4 data register (PDR4), the
data is retained in the output latch and output from the pin.
• When the port 4 data register (PDR4) is read, the state of the output latch in the port 4 data register
(PDR4) is read.
Note:
If read modify write (RMW) instructions (such as the bit set instruction) are used to read the PDR, the
pin set as an output port by the DDR outputs the desired data. However, the pin set as an input port
outputs data after the input state is written to the output latch. When switching from the input port to
the output port, write data to the PDR and set the pin as an output port in the DDR.
● Operation of input port
• If the bit in the DDR4 corresponding to the input pin is set to "0", port 4 functions as an input port.
• The output buffer is turned "OFF" and the pin enters the high impedance state.
• When data is written to the PDR4, it is retained in the output latch in the PDR4 but not output to the pin.
• When the PDR4 is read, the level value ("Low" or "High") of the pin is read.
● Operation of resource output
• When using port 4 as the output pin of the resource, set the output of the corresponding resource to
"enabled".
• Since the resource output is preferred enabled, the resource output functions regardless of the settings of
the DDR4.
• When the pin state is read with the resource output set to "enabled", the output state of the resource is
read
● Operation of resource input
• The state of the pin that serves as the input of the resource is input to the resource.
• When using port 4 as the input pin of the resource, clear the bit in the DDR4 corresponding to the input
pin of the resource to "0" and set the input pin as an input port.
179
CHAPTER 4 I/O PORT
● Operation at reset
• When the CPU is reset, the value of the DDR4 is initialized to "0". Consequently, all output buffers are
set to OFF (the pin becomes an input port pin), and the pin enters the high-impedance state.
• The PDR4 is not initialized by reset. Therefore, when using port 4 as an output port, it is necessary to set
output data in the PDR4, and then set the bit in the DDR4 corresponding to the output pin to "1" and to
output.
● Operation in stop mode, timebase timer mode and watch mode
If the pin state specify bit (SPL) of the low-power consumption mode control register (LPMCR) is set to
"1" when the CPU operation mode switches to stop mode, timebase timer mode or watch mode, the pin
enters the high-impedance state. In this case, the output buffer is forcibly set to "OFF" regardless of the
values of the Port 4 direction register (DDR4).
Table 4.6-4 shows the state of the port 4 pins.
Table 4.6-4 State of Port 4 Pins
Pin Name
Normal Operation
Sleep Mode
Stop Mode, Timebase Timer Mode or
Watch Mode
SPL=0
P40/SIN1 to
P47/RX
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O
port
SPL: Pin state specification bit of low power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
180
SPL=1
Input cut off, and output
becomes Hi-Z (Pull-up
resistor disconnected)
CHAPTER 4 I/O PORT
4.7
Port 5
Port 5 is a general-purpose I/O port that serves as the analog input pin. Use port 5 by
switching between the analog input pin and the general-purpose I/O port.
The function as a general-purpose I/O port is mainly described here. The configuration,
pin assignment, block diagram of the pins, and registers for port 5 are shown below.
■ Configuration of Port 5
Port 5 consists of the following four elements:
• General-purpose I/O port, analog input pins (P50/AN0 to P57AN7)
• Port 5 data register (PDR5)
• Port 5 direction register (DDR5)
• Analog input enable register (ADER)
■ Pin Assignment of Port 5
• Use port 5 by switching between the analog input pin and the general-purpose I/O port.
• Since port 5 serves as an analog input pin, it cannot be used as a general-purpose I/O port when used as
an analog input pin.
• When using port 5 as an analog input pin, set the pin corresponding to the analog input in the DDR5 as
an input port.
• When using port 5 as a general-purpose I/O port, do not input any analog signal.
Table 4.7-1 shows the pin assignment of port 5.
Table 4.7-1 Pin Assignment of Port 5
Port
Name
Port 5
I/O Type
Pin Name
Port Function
P50/AN0
P50
AN0
Analog input channel 0
P51/AN1
P51
AN1
Analog input channel 1
P52/AN2
P52
AN2
Analog input channel 2
P53/AN3
P53
AN3
Analog input channel 3
P54/AN4
P54
AN4
Analog input channel 4
P55/AN5
P55
AN5
Analog input channel 5
P56/AN6
P56
AN6
Analog input channel 6
P57/AN7
P57
AN7
Analog input channel 7
Generalpurpose
I/O port
Input
Output
Circuit
Type
CMOS
(hysteresis/
analog input)
CMOS
E
Resource
Reference:
For the circuit type, see Section "1.7 I/O Circuit".
181
CHAPTER 4 I/O PORT
■ Block Diagram of Pins of Port 5
Figure 4.7-1 Block Diagram of Pins of Port 5
Analog input
ADER
Internal data bus
PDR (port data register)
PDR read
Output latch
P-ch
PDR write
DDR
Pin
(port direction register)
N-ch
Direction latch
DDR write
Standby control (SPL = 1)
DDR read
Standby control: Control of stop mode (SPL = 1), timebase timer mode (SPL = 1), and watch mode (SPL = 1)
■ Registers for Port 5
• The registers for port 5 are PDR5, DDR5, and ADER.
• The ADER sets input of an analog signal to the analog input pin to "enabled" or "disabled".
• The bits composing each register correspond to the pins of port 5 one-to-one.
Table 4.7-2 shows the correspondence between the registers and pins of port 5.
Table 4.7-2 Correspondence between Registers and Pins for Port 5
Port
Name
Bits of Related Registers and Corresponding Pins
PDR5, DDR5
Port 5
ADER
Corresponding pin
182
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
P57
P56
P55
P54
P53
P52
P51
P50
CHAPTER 4 I/O PORT
4.7.1
Registers for Port 5 (PDR5, DDR5, ADER)
The registers for port 5 are explained.
■ Function of Registers for Port 5
● Port 5 data register (PDR5)
• Port 5 data register indicates the state of the pins.
● Port 5 direction register (DDR5)
• The port 5 direction register sets the input/output directions.
• When the bit corresponding to the pin is set to "1", port 5 functions as an output port. When the bit is set
to "0", port 5 functions as an input port.
● Analog input enable register (ADER)
• The analog input enable register (ADER) sets the general-purpose I/O ports and analog input pin in unit
of ports.
• When the ADE bit corresponding to the analog input pin is set to "1", port 5 functions as an analog input
pin. When the bit is set to "0", port 5 functions as a general-purpose I/O port.
Table 4.7-3 shows the functions of the registers for port 5.
Note:
When a middle-level signal is input with port 5 set as an input port, input leakage current flows.
Therefore, when inputting an analog signal, set the corresponding ADE bit in the ADER to "analog
input enabled".
183
CHAPTER 4 I/O PORT
Table 4.7-3 Function of Registers for Port 5
Register Name
Data
At Write
0
"0" is set for the output latch. When
The pin state
the pin is an output port pin, the Low
is Low level.
level is output to the pin.
1
The pin state "1" is set for the output latch. When
is High
the pin is an output port pin, the High
level.
level is output to the pin.
0
The
direction
latch is "0".
1
The
direction
latch is "1".
0
General-purpose I/O port
1
Analog input mode
Port 5 data register
(PDR5)
Port 5 direction
register (DDR5)
Analog input enable
register (ADER)
At Read
Read/
Write
Register
Address
Initial Value
R/W
000005H
XXXXXXXXB
R/W
000015H
00000000B
R/W
00001BH
11111111B
The output buffer is set to "OFF", and
the pin becomes an input port pin.
The output buffer is set to "ON", and
the pin becomes an output port pin.
R/W: Readable/Writable
X: Undefined value
References:
• When using port 5 as the analog input pin, clear the bit in the DDR5 corresponding to the analog
input pin to "0" and set the input pin as an input port.
• When using port 5 as the input pin of the resource, clear the bit in the DDR5 corresponding to the
input pin of the resource to "0" and set the input pin as an input port.
184
CHAPTER 4 I/O PORT
4.7.2
Operation of Port 5
The operation of port 5 is explained.
■ Operation of Port 5
● Operation of output port
• When the bit in the port 5 direction register (DDR5) corresponding to the output pin is set to "1", port 5
functions as an output port.
• When the output buffer is turned "ON" and output data is written to the port 5 data register (PDR5), the
data is retained in the output latch and output from the pin.
• When the port 5 data register (PDR5) is read, the state of the output latch in the PDR5 is read.
Note:
If read modify write (RMW) instructions (such as the bit set instruction) are used to read the PDR, the
pin set as an output port by the DDR outputs the desired data. However, the pin set as an input port
outputs data after the input state is written to the output latch. When switching from the input port to
the output port, write data to the PDR and set the pin as an output port in the DDR.
● Operation of input port
• If the bit in the DDR5 corresponding to the input pin is set to "0", port 5 functions as an input port.
• The output buffer is turned "OFF" and the pin enters the high impedance state.
• When data is written to the port 5 data register (PDR5), it is retained in the output latch in the PDR5 but
not output to the pin.
• When the PDR5 is read, the level value ("Low" or "High") of the pin is read.
● Operation of analog input
• When using port 5 as an analog input pin, set the bit in the ADER corresponding to the analog input pin
to "1". Port 5 is disabled to operate as a general-purpose I/O port, and functions as an analog input pin.
• When the PDR5 is read with the bit set to "analog input enabled," the read value is "0".
● Operation at reset
• When the CPU is reset, the value of the DDR5 is initialized to "0". Consequently, all output buffers are
set to OFF (the pin becomes an input port pin), and the pin enters the high-impedance state.
• The PDR5 is not initialized by reset. Therefore, when using it as the output port 2, it is necessary to set
output data in the PDR5, and then set the bit in the DDR5 corresponding to the output pin to "1" and to
output.
185
CHAPTER 4 I/O PORT
● Operation in stop mode, timebase timer mode or watch mode
When the pin state specification bit of the low power consumption mode control register (LPMCR: SPL) is
"1", at a transition to the stop mode, timebase timer mode or watch mode, the pin enters the highimpedance state. The output buffer is set forcibly to "OFF" irrespective of the value of the DDR5.
Table 4.7-4 shows the state of the port 5 pins.
Table 4.7-4 State of Port 5 Pins
Pine Name
Normal Operation
Sleep Mode
Stop Mode, Timebase Timer Mode or
Watch Mode
SPL=0
P50/AN0 to
P57/AN7
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O
port
SPL: Pin state specification bit of low power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
186
SPL=1
Input cut off, and output
becomes Hi-Z
CHAPTER 5
TIMEBASE TIMER
This chapter describes the function and operation of the
timebase timer.
5.1 Overview of Timebase Timer
5.2 Block Diagram of Timebase Timer
5.3 Configuration of Timebase Timer
5.4 Timebase Timer Interrupt
5.5 Explanation of Operation of Timebase Timer
5.6 Precautions when Using Timebase Timer
5.7 Program Example of Timebase Timer
187
CHAPTER 5 TIMEBASE TIMER
5.1
Overview of Timebase Timer
The timebase timer is an 18-bit free-run counter (timebase timer counter) that
increments in synchronization with the main clock (2-divided frequency of main
oscillation clock).
• Four interval times can be selected and an interrupt request can be generated for
each interval time.
• An operation clock is supplied to the oscillation stabilization wait time timer and
other resources.
■ Functions of Interval Timer
• When the timebase timer counter reaches the interval time set by the interval time select bits (TBTC:
TBC1, TBC0), an overflow occurs (TBTC: TBOF = 1) and an interrupt request is generated.
• When an interrupt is enabled due to an overflow (carry) (TBTC: TBIE = 1), an overflow occurs (TBTC:
TBOF = 1) and an interrupt is generated.
• The timebase timer has four interval times that can be selected. Table 5.1-1 shows the interval times of
the timebase timer.
Table 5.1-1 Interval Times of Timebase Timer
Count Clock
Interval Time
212/HCLK (approx. 1.0 ms)
2/HCLK(0.5 μs)
214/HCLK (approx. 4.1 ms)
216/HCLK (approx. 16.4 ms)
219/HCLK (approx. 131.1 ms)
HCLK: Oscillation clock
The parenthesized values are provided at 4-MHz oscillation clock.
188
CHAPTER 5 TIMEBASE TIMER
■ Clock Supply
The timebase timer supplies an operation clock to the resources such as an oscillation stabilization wait
time timer, PPG timer, and watchdog timer. Table 5.1-2 shows the clock cycles supplied from the timebase
timer.
Table 5.1-2 Clock Cycles Supplied from Timebase Timer
Where to Supply Clock
Clock Cycle
210/HCLK (approx. 256 μs)
213/HCLK (approx. 2.0 ms)
Oscillation stabilization wait time
215/HCLK (approx. 8.2 ms)
217/HCLK (approx. 32.8 ms)
212/HCLK (approx. 1.0 ms)
214/HCLK (approx. 4.1 ms)
Watchdog timer
216/HCLK (approx. 16.4 ms)
219/HCLK (approx. 131.1 ms)
PPG Timer
29/HCLK (approx. 128 μs)
HCLK: Oscillation clock
The parenthesized values are provided at 4-MHz oscillation clock.
Note: Since the oscillation cycle is unstable immediately after oscillation starts, the oscillation
stabilization wait time values are given as a guide.
189
CHAPTER 5 TIMEBASE TIMER
5.2
Block Diagram of Timebase Timer
The timebase timer consists of the following blocks:
• Timebase timer counter
• Counter clear circuit
• Interval timer selector
• Timebase timer control register (TBTC)
■ Block Diagram of Timebase Timer
Figure 5.2-1 Block Diagram of Timebase Timer
To watchdog
timer
To PPG timer
Timebase timer counter
× 21 × 22 × 23
21/HCLK
. . .. . .
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
OF
OF
OF
OF
Power-on reset
Stop mode
CKSCR: MCS = 1 → 0*1
CKSCR: SCS = 0 → 1*2
To the oscillation
stabilization wait time
selector in the clock
control section
Counter
clear circuit
Interval timer
selector
TBOF clear
Timebase timer control register
(TBTC)
Reserved
⎯
TBOF set
⎯
TBIE TBOF TBR TBC1 TBC0
Timebase timer interrupt signal
OF
HCLK
*1
*2
:
:
:
:
Overflow
Oscillation clock
Switching the machine clock from the main clock to the PLL clock
Switching the machine clock from the subclock to the main clock
The actual interrupt request number of the timebase timer is as follows:
Interrupt request number: #16 (10H)
190
CHAPTER 5 TIMEBASE TIMER
● Timebase timer counter
The timebase timer counter is an 18-bit up counter that uses a clock with 2-divided frequency of the
oscillation clock (HCLK) as a count clock.
● Counter clear circuit
The counter clear circuit clears the value of the timebase timer counter by the following factors:
• Timebase timer counter clear bit in the timebase timer control register (TBTC: TBR = 0)
• Power-on reset
• Transition to main stop mode or PLL stop mode (CKSCR: SCS = 1, LPMCR: STP = 1)
• Clock mode switching (from main clock mode to PLL clock mode, from subclock mode to PLL clock
mode, or from subclock mode to main clock mode)
● Interval timer selector
The interval timer selector selects the output of the timebase timer counter from four types. When
incrementing causes the selected interval time bit to overflow (carry), an interrupt request is generated.
● Timebase timer control register (TBTC)
The timebase timer control register (TBTC) selects the interval time, clears the timebase timer counter,
enables or disables interrupts, and checks and clears the state of an interrupt request.
191
CHAPTER 5 TIMEBASE TIMER
5.3
Configuration of Timebase Timer
This section explains the registers and interrupt factors of the timebase timer.
■ List of Registers and Reset Values of Timebase Timer
Figure 5.3-1 List of Registers and Reset Values of Timebase Timer
bit
Timebase timer control
register (TBTC)
X: Undefined
15
14
13
12
11
10
9
8
1
X
X
0
0
1
0
0
■ Generation of Interrupt Request from Timebase Timer
When the selected interval timer counter bit reaches the interval time, the overflow interrupt request flag bit
in the timebase timer control register (TBTC: TBOF) is set to "1". If the overflow interrupt request flag bit
is set (TBTC: TBOF = 1) when the interrupt is enabled (TBTC: TBIE = 1), the timebase timer generates an
interrupt request.
192
CHAPTER 5 TIMEBASE TIMER
5.3.1
Timebase Timer Control Register (TBTC)
The timebase timer control register (TBTC) provides the following settings:
• Selecting the interval time of the timebase timer
• Clearing the count value of the timebase timer
• Enabling or disabling the interrupt request when an overflow occurs
• Checking and clearing the state of the interrupt request flag when an overflow occurs
■ Timebase Timer Control Register (TBTC)
Figure 5.3-2 Timebase Timer Control Register (TBTC)
Address:
0000A9H
15
14
13
12
11
10
9
8
Reset value
1XX00100B
R/W ⎯
⎯ R/W R/W W R/W R/W
bit 9 bit 8
TBC1 TBC0
Interval time select bits
0
0
212/HCLK (Approx. 1.0ms)
0
1
214/HCLK (Approx. 4.1ms)
1
0
216/HCLK (Approx. 16.4ms)
1
1
219/HCLK (Approx. 131.1ms)
HCLK: Oscillation clock
The parenthesized values are provided at 4 MHz oscillation clock.
bit 10
TBR
0
1
Timebase timer counter clear bit
Read
Write
Clears the timebase timer
counter and TBOF bit
⎯
The read value is always 1
No effect
bit 11
TBOF
Overflow interrupt request flag bit
Read
Write
0
No overflow from the
selected count bit
Cleared
1
Overflow from the
selected count bit
No effect
bit 12
TBIE
0
1
Overflow interrupt enable bit
Overflow interrupt request disabled
Overflow interrupt request enabled
bit 15
Reserved
R/W : Read/Write
W
: Write only
X
: Undefined
: Reset value
⎯
: Unused
1
Reserved bit
Always write 1 to this bit
193
CHAPTER 5 TIMEBASE TIMER
Table 5.3-1 Functions of Timebase Timer Control Register (TBTC)
Bit Name
bit 15
Reserved: Reserved bit
Always set this bit to "1".
bit 14
bit 13
Unused bits
Read: The value is undefined.
Write: No effect
TBIE:
Overflow interrupt
enable bit
This bit enables or disables an interrupt when the interval timer bit in the
timebase timer counter overflows.
When set to "0": No interrupt request is generated at an overflow (TBOF = 1).
When set to "1": An interrupt request is generated at an overflow (TBOF = 1).
TBOF:
Overflow interrupt
request flag bit
This bit indicates an overflow (carry) in the interval timer bit in the timebase
timer counter.
When an overflow (carry) occurs (TBOF = 1) with interrupts enabled (TBIE = 1), an
interrupt request is generated.
When set to "0": The bit is cleared.
When set to "1": Disabled. The state remains unchanged.
Reading by read-modify-write (RMW) type instructions always reads "1".
Notes: 1. To clear the TBOF bit, disable interrupts (TBIE = 0) or mask interrupts
using the interrupt mask register (ILM) in the processor status.
2. The TBOF bit is cleared when "0" is written to the bit, a transition to
main stop mode, a transition to PLL stop mode, a transition from
subclock mode to main clock mode, a transition from subclock mode
to PLL clock mode, or a transition from main clock mode to PLL
clock mode occurs, "0" is written to the timebase timer counter clear
bit (TBR), or by a reset.
TBR:
Timebase timer counter
clear bit
This bit clears all the bits in the timebase timer counter.
When set to "0":All the bits in the timebase timer counter are cleared to "0".
The TBOF bit is also cleared.
When set to "1":Disabled. The state remains unchanged.
Read: "1" is always read.
TBC1, TBC0:
Interval time select bits
These bits set the cycle of the interval timer in the timebase timer counter.
• The interval time of the timebase timer is set according to the setting of the
TBC1 and TBC0 bits.
• Four interval times can be set.
bit 12
bit 11
bit 10
bit 9
bit 8
194
Function
CHAPTER 5 TIMEBASE TIMER
5.4
Timebase Timer Interrupt
The timebase timer generates an interrupt request when the interval time bit in the
timebase timer counter corresponding to the interval time set by the timebase timer
control register overflows (carries) (interval timer function).
■ Timebase Timer Interrupt
• The timebase timer continues incrementing for as long as the main clock (with 2-divided frequency of
the oscillation clock) is input.
• When the interval time set by the interval time select bits in the timebase timer control register (TBTC:
TBC1, TBC2) is reached, the interval time select bit corresponding to the interval time selected in the
timebase timer counter carries, and then overflows.
• When the interval time select bit overflows, the overflow interrupt request flag bit in the timebase timer
control register (TBTC: TBOF) is set to "1".
• When the overflow interrupt request flag bit in the timebase timer control register is set (TBTC: TBOF = 1)
with an interrupt enabled (TBTC: TBIE = 1), an interrupt request is generated.
• When the selected interval time is reached, the overflow interrupt request flag bit in the timebase timer
control register (TBTC: TBOF) is set regardless of whether an interrupt is enabled or disabled (TBTC:
TBIE).
• To clear the overflow interrupt request flag bit (TBTC: TBOF), disable a timebase timer interrupt at
interrupt processing (TBTC : TBIE=0) or mask a timebase timer interrupt by using the ILM bit in the
processor status (PS) to write 0 to the TBOF bit.
Note:
When an interrupt is enabled (TBTC: TBIE = 1) with the overflow interrupt request flag bit in the
timebase timer control register set (TBTC: TBOF = 1), an interrupt request is generated immediately.
■ Correspondence between Timebase Timer Interrupt and EI2OS
• The timebase timer does not correspond to EI2OS.
• For details of the interrupt number, interrupt control register, and interrupt vector address, see "3.5
Interrupt".
195
CHAPTER 5 TIMEBASE TIMER
5.5
Explanation of Operation of Timebase Timer
The timebase timer operates as an interval timer or an oscillation stabilization wait time
timer, and supplies a clock to resources.
■ Interval Timer Function
Interrupt generation at every interval time enables the timebase timer to be used as an interval timer.
Operating the timebase timer as an interval timer requires the settings shown in Figure 5.5-1.
● Setting of timebase timer
Figure 5.5-1 Setting of Timebase Timer
bit 15
Timebase timer control
Reserved
register (TBTC)
1
- : Unused bit
: Used bit
0 : Set 0
1 : Set 1
14
13
12
11
10
9
8
-
-
TBIE
TBOF
TBR
TBC1
TBC0
0
0
● Operation as interval timer function
The timebase timer can be used as an interval timer by generating an interrupt at every set interval time.
• The timebase timer continues incrementing in synchronization with the main clock (2-divided frequency
of the oscillation clock) while the oscillation clock is active.
• When the timebase timer counter reaches the interval time set by the interval time select bits in the
timebase timer control register (TBTC:TBC1, TBC0), it causes an overflow (carry) and the overflow
interrupt request flag bit (TBTC:TBOF) is set to "1".
• When the overflow interrupt request flag bit is set (TBTC:TBOF = 1) with interrupts enabled (TBTC:
TBIE = 1), an interrupt request is generated.
Note:
The interval time may become longer than the one set by clearing the timebase timer counter.
196
CHAPTER 5 TIMEBASE TIMER
● Example of operation of timebase timer
Figure 5.5-2 gives an example of the operation that the timebase timer performs under the following
conditions:
• A power-on reset occurs.
• The mode transits to the sleep mode during the operation of the interval timer.
• The mode transits to the stop mode during the operation of the interval timer.
• A request to clear the timebase timer counter is issued.
At transition to the stop mode, the timebase timer counter is cleared to stop counting. At return from the
stop mode, the timebase timer counts the oscillation stabilization wait time of the main clock.
Figure 5.5-2 Example of Operation of Timebase Timer
Counter value
Cleared by transition
to stop mode
3FFFFH
Oscillation stabilization
wait overflow
00000 H
CPU operation starts
Power-on reset
Interval cycle
(TBTC: TBC1: TBC0 = 11B)
Cleared by interrupt processing
Counter clear
(TBTC: TBR = 0)
TBOF bit
TBIE bit
Sleep
SLP bit
(LPMCR register)
Releasing of sleep mode by interval
interrupt of timebase timer
Stop
STP bit
(LPMCR register)
When interval time select bit (TBTC: TBC1, TBC0) is set to "11B" (219/HCLK)
: Oscillation stabilization wait time
HCLK : Oscillation clock
■ Operation as Oscillation Stabilization Wait Time Timer
The timebase timer can be used as the oscillation stabilization wait time timer of the main clock and PLL
clock.
• The oscillation stabilization wait time is the time elapsed from when the timebase timer counter
increments from 0 until the set oscillation stabilization wait time select bit overflows (carries).
197
CHAPTER 5 TIMEBASE TIMER
Table 5.5-1 shows clearing conditions and oscillation stabilization wait time of timebase timer.
Table 5.5-1 Clearing Conditions and Oscillation Stabilization Wait Time of Timebase Timer
Operation
Counter
Clear
TBOF
Clear
Writing 0 to timebase timer counter clear bit
(TBTC: T BR)
O
O
O
O
Transition to main clock mode after oscillation stabilization
wait time of main clock completed
Watchdog reset
X
O
Not provided
External reset
X
O
Not provided
Software reset
X
O
Not provided
Main clock → PLL clock
(CKSCR: MCS = 1 → 0)
O
O
Transition to PLL clock mode after oscillation stabilization wait
time of PLL clock completed
Main clock → subclock
(CKSCR: SCS = 1 → 0)
X
X
Transition to subclock mode after oscillation stabilization wait
time of subclock completed
Subclock → main clock
(CKSCR: SCS = 0 → 1)
O
O
Transition to main clock mode after oscillation stabilization
wait time of main clock completed
Subclock → PLL clock
(CKSCR: MCS = 0, SCS = 0 → 1)
O
O
Transition to PLL clock mode after oscillation stabilization wait
time of main clock completed
PLL clock → main clock
(CKSCR: MCS = 0 → 1)
X
X
Not provided
PLL clock → subclock
(CKSCR: MCS = 0, SCS = 1 → 0)
X
X
Not provided
O
O
Transition to main clock mode after oscillation stabilization
wait time of main clock completed
X
X
Transition to subclock mode after oscillation stabilization wait
time of subclock completed
O
O
Transition to PLL clock mode after oscillation stabilization wait
time of main clock completed
X
X
Not provided
Return to main clock mode
X
X
Not provided
Return to subclock mode
X
X
Not provided
Return to PLL clock mode
X
X
Not provided
Cancellation of main sleep mode
X
X
Not provided
Cancellation of sub-sleep mode
X
X
Not provided
Cancellation of PLL sleep mode
X
X
Not provided
Oscillation Stabilization Wait Time
Reset
Power on reset
Switching between clock modes
Cancellation of stop modes
Cancellation of main stop mode
Cancellation of sub-stop mode
Cancellation of PLL stop mode
Cancellation of watch mode
Cancellation of sub-watch mode
Cancellation of timebase timer modes
Cancellation of sleep modes
198
CHAPTER 5 TIMEBASE TIMER
■ Supply of Operation Clock
The timebase timer supplies an operation clock to the PPG timers (PPG01, PPG23) and the watchdog
timer.
Note:
Clearing the timebase timer counter may affect the operation of the resources such as the watchdog
timer and PPG timers using the output of the timebase timer.
Reference:
For details of the PPG timers, see "CHAPTER 10 8-/16-BIT PPG TIMER".
For details of the watchdog timer, see "CHAPTER 6 WATCHDOG TIMER".
199
CHAPTER 5 TIMEBASE TIMER
5.6
Precautions when Using Timebase Timer
This section explains the precautions when using the timebase timer.
■ Precautions when Using Timebase Timer
● Clearing interrupt request
To clear the overflow interrupt request flag bit in the timebase timer control register (TBTC:TBOF = 0),
disable interrupts (TBTC:TBIE = 0) or mask the timebase timer interrupt by using the interrupt level mask
register in the processor status.
● Clearing timebase timer counter
Clearing the timebase timer counter affects the following operations:
• When the timebase timer is used as the interval timer (interval interrupt).
• When the watchdog timer is used.
• When the clock supplied from the timebase timer is used as the operation clock of the PPG timer.
● Using timebase timer as oscillation stabilization wait time timer
• After power on or in the main stop mode, PLL stop mode, and subclock mode, the oscillation clock
stops. Therefore, when oscillation starts, the timebase timer requires the oscillation stabilization wait
time of the main clock. An appropriate oscillation stabilization wait time must be selected according to
the types of oscillators connected to high-speed oscillation input pins.
Reference:
For details of the oscillation stabilization wait time, see "3.7.5 Oscillation Stabilization Wait Time".
● Resources to which timebase timer supplies clock
• At transition to operation modes (PLL stop mode, subclock mode, and main stop mode) in which the
oscillation clock stops, the timebase timer counter is cleared and the timebase timer stops.
• When the timebase timer counter is cleared, an after-clearing interval time is needed. It may cause the
clock supplied from the timebase timer to have a short High level or a 1/2 cycle longer Low level.
• The watchdog timer performs normal counting because the watchdog timer counter and timebase timer
counter are cleared simultaneously.
200
CHAPTER 5 TIMEBASE TIMER
5.7
Program Example of Timebase Timer
This section gives a program example of the timebase timer.
■ Program Example of Timebase Timer
● Processing specification
The 212/HCLK (HCLK: oscillation clock) interval interrupt is generated repeatedly. In this case, the
interval time is approximately 1.0 ms (at 4-MHz operation).
● Coding example
ICR02
EQU 0000B2H
; Timebase timer interrupt control register
TBTC
EQU 0000A9H
; Timebase timer control register
TBOF
EQU TBTC:3
; Interrupt request flag bit
TBIE
EQU TBTC:2
; Interrupt enable bit
;-----Main program--------------------------------------------------------------CODE
CSEG
START:
; Stack pointer (SP) already initialized
AND CCR,#0BFH
; Interrupts disabled
MOV I:ICR02 #00H
; Interrupt level 0 (highest)
MOV I:TBTC,#10000000B ; Upper 3 bits fixed
; TBOF cleared,
; Counter clear interval time
; 212/HCLK selected
SETB I:TBIE
; Interrupts enabled
MOV ILM,#07H
; ILM in PS set to level 7
OR
CCR,#40H
; Interrupts enabled
LOOP:
MOV A,#00H
; Infinite loop
MOV A,#01H
BRA LOOP
;-----Interrupt program---------------------------------------------------------WARI:
CLRB I:TBIE
; Interrupt enabled bit cleared
CLRB I:TBOF
; Interrupt request flag cleared
:
Processing by user
:
SETB I:TBIE
; Interrupt enabled
RETI
; Return from interrupt
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG 0FFBCH
; Vector set to interrupt #16 (10H)
DSL WARI
ORG 0FFDCH
; Reset vector set
DSL START
DB
00H
; Set to single-chip mode
VECT
ENDS
END START
201
CHAPTER 5 TIMEBASE TIMER
202
CHAPTER 6
WATCHDOG TIMER
This chapter describes the function and operation of the
watchdog timer.
6.1 Overview of Watchdog Timer
6.2 Configuration of Watchdog Timer
6.3 Watchdog Timer Registers
6.4 Explanation of Operation of Watchdog Timer
6.5 Precautions when Using Watchdog Timer
6.6 Program Examples of Watchdog Timer
203
CHAPTER 6 WATCHDOG TIMER
6.1
Overview of Watchdog Timer
The watchdog timer is a 2-bit counter that uses the timebase timer or watch timer as a
count clock. If the counter is not cleared within a set interval time, the CPU is reset.
■ Functions of Watchdog Timer
• The watchdog timer is a timer counter that is used to prevent program malfunction. When the watchdog
timer is started, the watchdog timer counter must continue to be cleared within a set interval time. If the
set interval time is reached without clearing the watchdog timer counter, the CPU is reset.
• The interval time of the watchdog timer depends on the clock cycle input as a count clock and a
watchdog reset occurs between the minimum and maximum times.
• The clock source output destination is set by the watchdog clock select bit in the watch timer control
register (WTC: WDCS).
• The interval time of the watchdog timer is set by the timebase timer output select bit/watch timer output
select bit in the watchdog timer control register (WDTC: WT1, WT0).
Table 6.1-1 lists the interval times of the watchdog timer.
Table 6.1-1 Interval Time of Watchdog Timer
Min.
Max.
Clock cycle
Min.
Max.
Clock cycle
Approx. 3.58 ms
Approx.4.61 ms
214 ± 211/HCLK
Approx. 0.457 s
Approx. 0.576 s
212 ± 29/SCLK
Approx. 14.33 ms
Approx. 18.3 ms
216 ± 213/HCLK
Approx. 3.584 s
Approx. 4.608 s
215 ± 212/SCLK
Approx. 57.23 ms
Approx. 73.73 ms
218 ± 215/HCLK
Approx. 7.168 s
Approx. 9.216 s
216 ± 213/SCLK
Approx. 458.75 ms
Approx. 589.82 ms
221 ± 218/HCLK
Approx. 14.336 s
Approx. 18.432 s
217 ± 214/SCLK
HCLK: Oscillation clock (4 MHz), SLCK: Subclock (8.192 kHz)
Notes:
• If the timebase timer output (carry signal) is used as a count clock to the watchdog timer, the
timebase timer is cleared and the time for the watchdog reset to occur may be long.
• If the subclock is used as a machine clock, always set the watchdog timer clock source select bit
(WDCS) in the watch timer control register (WTC) to "0" to select the watch timer output.
204
CHAPTER 6 WATCHDOG TIMER
6.2
Configuration of Watchdog Timer
The watchdog timer consists of the following blocks:
• Count clock selector
• Watchdog timer counter (2-bit counter)
• Watchdog reset generator
• Counter clear controller
• Watchdog timer control register (WDTC)
■ Block Diagram of Watchdog Timer
Figure 6.2-1 Block Diagram of Watchdog Timer
Watchdog timer control register (WDTC)
PONR
⎯
Watch timer control register (WTC)
WRST ERST SRST WTE WT1 WT0
Watchdog timer
WDCS
2
Started
Reset generated
Transits to sleep mode
Transits to
timebase timer mode
Transits to watch mode
Transits to stop mode
Counter clear
controller
Count clock
selector
2-bit
counter
Watchdog
reset
generator
To the internal
reset generator
Clear
4
4
(Timebase timer counter)
Main clock
(2-divided clock of HCLK)
× 21 × 22 . . . × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
(Watch counter)
Subclock
SCLK
× 21 × 22 . . . × 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215
HCLK: Oscillation clock
SCLK: Subclock
205
CHAPTER 6 WATCHDOG TIMER
● Count clock selector
The count clock selector selects the timebase timer output or watch timer output as a count clock input to
the watchdog timer. Each timer output has four time intervals that can be set.
● Watchdog timer counter (2-bit counter)
The watchdog timer counter is a 2-bit up counter that uses the timebase timer output or watch timer output
as a count clock. The clock source output destination is set by the watchdog clock select bit in the watch
timer control register (WTC: WDCS).
● Watchdog reset generator
The watchdog reset generator generates a reset signal when the watchdog timer overflows (carries).
● Counter clear controller
The counter clear controller clears the watchdog timer counter.
● Watchdog timer control register (WDTC)
The watchdog timer control register starts and clears the watchdog timer, sets the interval time, and holds
reset factors.
206
CHAPTER 6 WATCHDOG TIMER
6.3
Watchdog Timer Registers
This section explains the registers used for setting the watchdog timer.
■ List of Registers and Reset Values of Watchdog Timer
Figure 6.3-1 List of Registers and Reset Values of Watchdog Timer
bit
Watchdog timer control
register (WDTC)
X: Undefined
7
6
5
4
3
2
1
0
X
X
X
X
X
1
1
1
207
CHAPTER 6 WATCHDOG TIMER
6.3.1
Watchdog Timer Control Register (WDTC)
The watchdog timer control register starts and clears the watchdog timer, sets the
interval time, and holds reset factors.
■ Watchdog Timer Control Register (WDTC)
Figure 6.3-2 Watchdog Timer Control Register (WDTC)
Address:
0000A8H
7
6
5
4
3
2
1
0
Reset value
XXXXX111 B
⎯
R
R
R
R
W
W
W
bit 1
bit 0
Interval time select bits (Timebase timer output selection)
Interval time
Clock cycle
Minimum
Maximum
0
0 Approx. 3.58 ms Approx. 4.61 ms
214 ± 211/HCLK
0
1 Approx. 14.33 ms Approx. 18.3 ms
216 ± 213/HCLK
1
0 Approx. 57.23 ms Approx. 73.73 ms 218 ± 215/HCLK
1
1 Approx. 458.75 ms Approx. 589.82 ms 221 ± 218/HCLK
HCLK: Oscillation clock
The parenthesized values are interval time when operates at HCLK 4MHz.
WT1 WT0
bit 1
bit 0
Interval time select bits (Watch timer output selection)
Interval time
Clock cycle
Minimum
Maximum
0
0 Approx. 0.457 s Approx. 0.576 s 212 ± 29/SCLK
0
1 Approx. 3.584 s Approx. 4.608 s 215 ± 212/SCLK
1
0 Approx. 7.168 s Approx. 9.216 s 216 ± 213/SCLK
1
1 Approx. 14.336 s Approx. 18.432 s 217 ± 214/SCLK
SCLK: Subclock
The parenthesized values are interval time when operates at SCLK 8.192kHz.
WT1 WT0
bit 2
Watchdog timer control bit
WTE
First write after reset: starts the
Second or subsequent write after
0
watchdog timer
reset: clears of the watchdog timer
1
No effect
bit 7 bit 5 bit 4 bit 3
Reset factor bits
PONR WRST ERST SRST
R
W
*
×
208
:
:
:
:
Read only
Write only
Holds the previous status
Undefined
Reset factor
1
×
×
×
*
*
*
1
*
*
*
1
*
*
Power-on reset
Watchdog reset
External reset ("L" level input into RST pin)
*
1
Software reset (Write "1" to RST bit)
CHAPTER 6 WATCHDOG TIMER
Table 6.3-1 Function of Watching Timer Control Register (WDTC)
Bit name
Function
bit 7
to
bit 3
PONR, WRST, ERST,
SRST:
Reset factor bits
These bits indicate reset factors.
• When a reset occurs, the bit corresponding to the reset factor is set to "1".
After a reset, the reset factor can be checked by reading the watchdog timer
control register (WDTC).
• These bits are cleared after the watchdog timer control register (WDTC) is
read.
Note: No bit value other than the PONR bit after power-on reset is assured. If the
PONR bit is set at read, other bit values should be ignored.
bit6
Unused bits
Read: The value is undefined.
Write: No effect
bit 2
WTE:
Watchdog timer control
bit
This bit starts or clears the watchdog timer.
When set to "0" (first time after reset): The watchdog timer is started.
When set to "0" (second or subsequent after reset):
The watchdog timer is cleared.
bit 1,
bit 0
WT1, WT0:
Interval time select bits
These bits set the interval time of the watchdog timer.
The time interval when the watch timer is used as the clock source to the
watchdog timer (watchdog clock select bit WDCS = 0) is different from when
the main clock mode or the PLL clock mode is selected as the clock mode and
the WDCS bit in the watch timer control register (WTC) is set to "1" as shown in
Figure 6.3-2 according to the settings of the WTC register.
Notes: • Only data when the watchdog timer is started is enabled.
• Write data after the watchdog timer is started is ignored.
• These are write-only bits.
209
CHAPTER 6 WATCHDOG TIMER
6.4
Explanation of Operation of Watchdog Timer
After starting, when the watchdog timer reaches the set interval time without the
counter being cleared, a watchdog reset occurs.
■ Operation of Watchdog Timer
The operation of the watchdog timer requires the settings shown in Figure 6.4-1.
Figure 6.4-1 Setting of Watchdog Timer
bit 7
Watchdog timer control register
PONR
(WDTC)
6
5
4
3
2
1
bit 0
-
WRST
ERST
SRST
WTE
WT1
WT0
0
Watch timer control register
(WTC)
bit 7
6
5
4
3
2
1
bit 0
WDCS
SCE
WTIE
WTOF
WTR
WTC2
WTC1
WTC0
: Used bit
0 : Set "0"
● Selecting clock input source
• The timebase timer or watch timer can be selected as the clock input source of the count clock to the
watchdog timer. When the watchdog clock select bit (WTC: WDCS) is set to "1", the timebase timer is
selected. When the bit is set to "0", the watch timer is selected. After a reset, the bit returns to "1".
• During operation in the subclock mode, set the WDCS bit to "0" to select the watch timer.
Note:
When the watch timer is set as the watchdog clock of the single system product, the watchdog timer
cannot be used.
● Setting interval time
• Set the interval time select bits (WDTC: WT1, WT0) to select the interval time for the watchdog timer.
• Set the interval time concurrently with starting the watchdog timer. Writing to the bit is ignored after the
watchdog timer is started.
● Starting watchdog timer
• When "0" is written to the watchdog timer control bit (WDTC: WTE) after a reset, the watchdog timer
is started and starts incrementing.
210
CHAPTER 6 WATCHDOG TIMER
● Clearing watchdog timer
• When "0" is written once again to the watchdog timer control bit (WDTC: WTE) within the interval
time after starting the watchdog timer, the watchdog timer is cleared. If the watchdog timer is not
cleared within the interval time, it overflows and the CPU is reset.
• A reset, or transitions to the standby modes (sleep mode, stop mode, watch mode, timebase timer mode)
clear the watchdog timer.
• During operation in the timebase timer mode or watch mode, the watchdog timer counter is cleared.
However, the watchdog timer remains in the activation state.
• Figure 6.4-2 shows the relationship between the clear timing and the interval time of the watchdog
timer. The interval time varies with the timing of clearing the watchdog timer.
211
CHAPTER 6 WATCHDOG TIMER
● Checking reset factors
The reset factor bits in the watchdog timer control register (WDTC: PONR, WRST, ERST, SRST) can be
read after a reset to check the reset factors.
Reference:
For details of reset factor bits, see "3.6 Reset".
Figure 6.4-2 Relationship between Clear Timing and Interval Time of Watchdog Timer
[Watchdog timer block diagram]
2-bit counter
Clock
selector
a
b
2-divided
clock circuit
Count enable
output circuit
WTE bit
2-divided
clock circuit
c
Reset circuit
d
Reset
signal
Count enabled and cleared
[Minimum interval time] When the WTE bit is cleared immediately before the count clock rises
Count starts
Counter cleared
Count clock a
2-divided clock value b
2-divided clock value c
Count enable
Reset signal d
7 × (count clock cycle/2)
WTE bit cleared
Watchdog reset occurs
[Maximum interval time] When the WTE bit is cleared immediately after the count clock rises
Count starts
Counter cleared
Count clock a
2-divided clock value b
2-divided clock value c
Count enable
Reset signal
9 × (count clock cycle/2)
WTE bit cleared
212
Watchdog reset occurs
CHAPTER 6 WATCHDOG TIMER
6.5
Precautions when Using Watchdog Timer
Take the following precautions when using the watchdog timer.
■ Precautions when Using Watchdog Timer
● Stopping watchdog timer
The watchdog timer is stopped by all the reset sources.
● Interval time
• The interval time uses the carry signal of the timebase timer or watch timer as a count clock. If the
timebase timer or watch timer is cleared, the interval time of the watchdog timer may become long.
The timebase timer is also cleared by writing zero to the timebase timer counter clear bit (TBR) in the
timebase timer control register (TBTC); transition from main clock mode to PLL clock mode; transition
from subclock mode to main clock mode; and transition from subclock mode to PLL clock mode.
• Set the interval time concurrently with starting the watchdog timer. Setting the interval time except
starting the watchdog timer is ignored.
● Precautions when creating program
When clearing the watchdog timer repeatedly in the main loop, set a shorter processing time for the main
loop including interrupt processing than the interval time of watchdog timer.
213
CHAPTER 6 WATCHDOG TIMER
6.6
Program Examples of Watchdog Timer
Program example of watchdog timer is given below:
■ Program Example of Watchdog Timer
● Processing specification
• The watchdog timer is cleared each time in loop of the main program.
• The main program must be executed once within the minimum interval time of the watchdog timer.
● Coding example
WDTC
EQU 0000A8H
; Watchdog timer control register
WTE
EQU WDTC:2
; Watchdog control bit
;
;-----Main program---------------------------------------------------------CODE
CSEG
START:
; Stack pointer (SP), already initialized
MOV I:WDTC,#00000011B ; Watchdog timer started
; Interval time of 221 + 218cycles selected
LOOP:
CLRB I:WTE
; Watchdog timer cleared
:
Processing by user
:
BRA LOOP
;-----Vector setting-------------------------------------------------------VECT
CSEG ABS=0FFH
ORG 00FFDCH
; Reset vector set
DSL START
DB
00H
; Set to single-chip mode
VECT
ENDS
END START
214
CHAPTER 7
16-BIT INPUT/OUTPUT
TIMER
This chapter explains the function and operation of 16bit input/output timer.
7.1 Overview of 16-bit Input/Output Timer
7.2 Block Diagram of 16-bit Input/Output Timer
7.3 Configuration of 16-bit Input/Output Timer
7.4 Interrupts of 16-bit Input/Output Timer
7.5 Explanation of Operation of 16-bit Free-run Timer
7.6 Explanation of Operation of Input Capture
7.7 Precautions when Using 16-bit Input/Output Timer
7.8 Program Example of 16-bit Input/Output Timer
215
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.1
Overview of 16-bit Input/Output Timer
The 16-bit input/output timer is a complex module that consists of a 16-bit free-run timer
(× 1 unit) and an input capture (× 2 units/4 input pins). The clock cycle of an input signal
and a pulse width can be measured based on the 16-bit free-run timer.
■ Configuration of 16-bit Input/Output Timer
The 16-bit input/output timer consists of the following modules:
• 16-bit free-run timer (× 1 unit)
• Input capture (× 2 units with 2 input pins each)
■ Functions of 16-bit Input/Output Timer
● Functions of 16-bit free-run timer
The 16-bit free-run timer consists of a 16-bit up counter, a timer counter control status register, and a
prescaler. The 16-bit up counter increments in synchronization with the division ratio of the machine clock.
• Count clock is selected from eight machine clock division ratios.
Count clock : φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128
• An overflow in the count value generates an interrupt.
• Interrupt generation starts the extended intelligent I/O service (EI2OS).
• Either a reset or software reset by the timer count clear bit (TCCS: CLR) clears the count value of the
16-bit free-run timer to "0000H".
• The count value of the 16-bit free-run timer is output to the input capture and can be used as the base
time for capture operation.
● Functions of input capture
When the input capture detects the edge of the external signal input to the input pins, it stores the count
value of the 16-bit free-run timer in the input capture data registers. The input capture consists of the input
capture data registers corresponding to four input pins, an input capture control status register, and an edge
detection circuit.
• The detected edge can be selected from among the rising edge, falling edge, and both edges.
• Detecting the edge of the input signal generates an interrupt request to the CPU.
• Interrupt generation starts the EI2OS.
• Four input pins and four input capture data registers of the input capture can be used to measure up to
four events.
216
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.2
Block Diagram of 16-bit Input/Output Timer
The 16-bit input/output timer consists of the following modules:
• 16-bit free-run timer
• Input capture
■ Block Diagram of 16-bit Input/Output Timer
Figure 7.2-1 Block Diagram of 16-bit Input/Output Timer
Internal data bus
Input capture
Dedicated bus
16-bit free-run
timer
● 16-bit free-run timer
The count value of the 16-bit free-run timer can be use as the base time for the input capture.
● Input capture
The input capture detects the rising edge, falling edge, or both edges of the external signal input to the input
pins to retain the count value of the 16-bit free-run timer. Detecting the edge of the input signal generates
an interrupt.
217
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.2.1
Block Diagram of 16-bit Free-run Timer
The 16-bit free-run timer consists of the following blocks:
• Prescaler
• Timer counter data register (TCDT)
• Timer counter control status register (TCCS)
■ Block Diagram of 16-bit Free-run Timer
Figure 7.2-2 Block Diagram of 16-bit Free-run Timer
Timer counter data register (TCDT)
Count value output
to input capture
16-bit free-run timer
φ
CLK
STOP
CLR
Internal data bus
OF
Prescaler
2
Timer counter control
status register
(TCCS)
IVF
IVFE STOP Reserved CLR CLK2 CLK1 CLK0
φ : Machine clock
OF : Overflow
Free-run timer
interrupt request
■ Details of Pins in Block Diagram
The 16-bit input/output timer has one 16-bit free-run timer.
The interrupt request number of the 16-bit free-run timer is 19 (13H).
● Prescaler
The prescaler divides the frequency of machine clock to supply a count clock to the 16-bit up counter. Any
of eight machine clock division ratios are selected by setting the timer counter control status register
(TCCS).
● Timer counter data register (TCDT)
The timer counter data register (TCDT) is a 16-bit up counter. At read, the current count value of the 16-bit
free-run timer can be read. Writing while the counter is stopped enables any count value to be set.
218
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
● Timer counter control status register (TCCS)
The timer counter control status register (TCCS) selects the division ratio of the machine clock, clears the
count value by software, enables or disables the count operation, checks and clears the overflow generation
flag, and enables or disables interrupts.
219
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.2.2
Block Diagram of Input Capture
The input capture consist of the following blocks:
• Input capture data registers (IPCP0 to IPCP3)
• Input capture control status registers (ICS01, ICS23)
• Edge detection circuit
■ Block Diagram of Input Capture
Figure 7.2-3 Block Diagram of Input Capture
16-bit free-run timer
Edge detection circuit
IN3
Input capture data register 3 (IPCP3)
Pin
IN2
Pin
Input capture data register 2 (IPCP2)
2
/
/
2
Input capture
interrupt request
Input capture control
status register (ICS01)
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
2
/
/
2
IN1
Input capture data register 1 (IPCP1)
Pin
IN0
Input capture data register 0 (IPCP0)
Pin
Edge detection circuit
220
Internal data bus
Input capture control
status register (ICS23) ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
■ Details of Pins in Block Diagram
The 16-bit input/output timer has four input capture input pins.
The actual pin names and interrupt request numbers of the input capture are shown in Table 7.2-1.
Table 7.2-1 Pins and Interrupt Request Numbers of 16-bit Input/Output Timer
Input Pin
Actual Pin Name
Interrupt Request Number
IN0
P10/IN0
#23 (17H)
IN1
P11/IN1
#25 (19H)
IN2
P12/IN2
IN3
P13/IN3
#30 (1EH)
● Input capture data registers 0 to 3 (IPCP0 to IPCP3)
The counter value of the 16-bit free-run timer actually read when the edge of the external signal input to the
input pins (IN0 to IN3) is detected is stored in the input capture data registers (IPCP0 to IPCP3)
corresponding to the input pins (IN0 to IN3) to which the signal is input.
● Input capture control status registers (ICS01, ICS23)
The input capture control status registers (ICS01, ICS23) start and stop the capture operation of each input
capture, check and clear the valid edge detection flag when the edge is detected, and enable or disable an
interrupt. The ICS01 register sets the input capture corresponding to the input pins IN0 and IN1, and the
ICS23 register sets the input capture corresponding to the input pins IN2 and IN3.
● Edge detector
The edge detection circuit detects the edge of the external signal input to the input pins. The detected edge
can be selected from the rising edge, falling edge, and both edges.
221
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.3
Configuration of 16-bit Input/Output Timer
This section explains the pins, registers, and interrupt factors of the 16-bit input/output
timer.
■ Pins of 16-bit Input/Output Timer
The pins of the 16-bit input/output timer serve as general-purpose I/O ports. Table 7.3-1 shows the pin
functions and the pin settings required to use the 16-bit input/output timer.
Table 7.3-1 Pins of 16-bit Input/Output Timer
Pin
Name
Pin Function
IN0
General-purpose I/O port, capture input
Set as input port in port direction register (DDR).
IN1
General-purpose I/O port, capture input
Set as input port in port direction register (DDR).
IN2
General-purpose I/O port, capture input
Set as input port in port direction register (DDR).
IN3
General-purpose I/O port, capture input
Set as input port in port direction register (DDR).
Pin Setting Required for Use of
16-bit Input/Output Timer
■ Block Diagram of Pins for 16-bit Input/Output Timer
For the block diagram of the pins, see "CHAPTER 4 I/O PORT".
222
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
■ List of Registers and Reset Values of 16-bit Input/Output Timer
Figure 7.3-1 List of Registers and Reset Values of 16-bit Input/Output Timer
bit
Timer counter control status register
(TCCS)
bit
Timer counter data register (High)
(TCDT: H)
bit
Timer counter data register (Low)
(TCDT: L)
bit
Input capture control status register
(ICS01)
bit
Input capture data register 0 (High)
(IPCP0: H)
bit
Input capture data register 0 (Low)
(IPCP0: L)
bit
Input capture data register 1 (High)
(IPCP1: H)
bit
Input capture data register 1 (Low)
(IPCP1: L)
bit
Input capture control status register
(ICS23)
bit
Input capture data register 2 (High)
(IPCP2: H)
bit
Input capture data register 2 (Low)
(IPCP2: L)
bit
Input capture data register 3 (High)
(IPCP3: H)
bit
Input capture data register 3 (Low)
(IPCP3: L)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X: Undefined
223
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
■ Generation of Interrupt Request from 16-bit Input/Output Timer
The 16-bit input/output timer can generate an interrupt request as a result of the following factors:
● Overflow in 16-bit free-run timer
In the 16-bit input/output timer, when the 16-bit free-run timer overflows, the overflow generation flag bit
in the timer counter control status register (TCCS: IVF) is set to "1". When an overflow interrupt is enabled
(TCCS: IVFE = 1), an interrupt request is generated.
● Edge detection by capture function
When the edge of the external signal input to the input pins (IN0 to IN3) is detected, the input capture valid
edge detection flag bit in the input capture control status register (ICS: ICP) corresponding to the input pin
as the edge is detected is set to "1". When the input capture interrupt corresponding to the channel
generating an interrupt request is enabled (ICS: ICE), an interrupt request is generated.
224
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.3.1
Timer Counter Control Status Register (TCCS)
The timer counter control status register (TCCS) selects the count clock and conditions
for clearing the counter, clears the counter, enables the count operation or interrupt,
and checks the interrupt request flag.
■ Timer Counter Control Status Register (TCCS)
Figure 7.3-2 Timer Counter Control Status Register (TCCS)
Address:
000058H
7
6
5
4
3
2
1
0
Reset value
00000000
B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 2 bit 1 bit 0
Count clock setting bits
CLK2 CLK1 CLK0
Count clock φ = 16 MHz φ = 8 MHz
0
0
0
φ
0
0
1
φ = 4 MHz φ = 1 MHz
62.5 ns 0.125 μs 0.25 μs
1 μs
φ/2
0.125 μs 0.25 μs
0.5 μs
2 μs
1 μs
4 μs
0
1
0
φ/4
0.25 μs
0.5 μs
0
1
1
φ/8
0.5 μs
1 μs
2 μs
8 μs
1
0
0
φ/16
1 μs
2 μs
4 μs
16 μs
1
0
1
φ/32
2 μs
4 μs
8 μs
32 μs
1
1
0
φ/64
4 μs
8 μs
16 μs
64 μs
1
1
1
φ/128
8 μs
16 μs
32 μs
128 μs
φ: Machine clock
bit 3
CLR
0
1
Timer count clear bit
No effect
Initializes counter to "0000H"
bit 4
Reserved bit
Reserved
0
Always set to "0"
bit 5
STOP
0
1
Timer count bit
Counting enable
Counting disable (stop)
bit 6
Overflow interrupt enable bit
IVFE
0
1
Overflow interrupt disable
Overflow interrupt enable
bit 7
Overflow generation flag bit
IVF
R/W : Read/Write
: Reset value
Read
Write
0
No overflow
Clear
1
Overflow
No effect
225
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
Table 7.3-2 Functions of Timer Counter Control Status Register (TCCS)
Bit Name
226
Function
bit 7
IVF:
Overflow generation flag
bit
This bit indicates that the 16-bit free-run timer has overflowed.
• If the 16-bit free-run timer overflows or mode setting causes a compare match
with the compare register 0 to clear the counter, this bit is set to "1".
• When an overflow occurs (IVF=1) with an overflow interrupt enabled
(IVFE = 1), an interrupt request is generated.
When set to "0": Clears bit
When set to "1": No effect
When EI2OS started: Bit cleared
Read by read modify write (RMW) instructions: "1" is always read.
bit 6
IVFE:
Overflow interrupt
enable bit
This bit enables or disables an interrupt request generated when the 16-bit freerun timer overflows.
When set to "0": No interrupt request generated at overflow (IVF = 1)
When set to "1": Generates interrupt request at overflow (IVF = 1)
bit 5
STOP:
Timer count bit
This bit enables or disables (stops) the count operation of the 16-bit free-run
timer.
When set to "0": Enables count operation
The 16-bit timer counter data register (TCDT) starts incrementing in
synchronization with the count clock selected by the count clock select bits
(CLK1 and CLK0).
When set to "1": Stops count operation
bit 4
Reserved: Reserved bit
Always set this bit to "0".
bit 3
CLR:
Timer count clear bit
This bit clears the counter value of the 16-bit free-run timer.
When set to "1": Clears timer counter data register (TCDT) to "0000H"
When set to "0": No effect
Read: "0" is always read.
• When the counter value changes, the CLR bit is cleared.
• When clearing the counter value while stopping the count operation, write
"0000H" to the timer counter data register (TCDT).
Note: After 1 is written, if 0 is written to this bit by the next count clock, counter
value is not initialized.
bit 2,
bit 1,
bit 0
CLK2, CLK1, CLK0:
Count clock select bits
These bits set the count clock to the 16-bit free-run time.
Note: 1. Set the count clock after stopping the count operation (STOP = 1).
2. When rewriting the count clock, write 1 to the timer count clear bit
(CLR) and clear the counter value.
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.3.2
Timer Counter Data Register (TCDT)
The timer counter data register (TCDT) is a 16-bit up counter. At read, the register value
being counted is read. At write, while the counter is stopped, any counter value can be set.
■ Timer Counter Data Register (TCDT)
Figure 7.3-3 Timer Counter Data Register (TCDT)
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
Timer counter data
register (TCDT): High
Address: 000056H
Timer counter data
register (TCDT): Low
Address: 000057H
R/W: Read/Write
bit 8
Reset value
00000000B
T15
T14
T13
T12
T11
T10
T9
T8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reset value
T7
T6
T5
T4
T3
T2
T1
T0
00000000B
R
R
R/W
R/W
R/W
R/W
R/W
R/W
■ Count Operation of Timer Counter Data Register (TCDT)
• When the timer counter data register (TCDT) is read during the count operation, the counter value of the
16-bit free-run timer is read.
• When the counter value of the timer counter data register (TCDT) increments from "FFFFH" to
"0000H", an overflow occurs and the overflow generation flag bit (TCCS: IVF) is also set to "1".
• When an overflow occurs (TCCS: IVF = 1) with an overflow interrupt enabled (TCCS: IVFE = 1), an
overflow interrupt request is generated.
• The counter value of the timer counter data register (TCDT) is retained while the count operation is
stopped.
• When stopping the count operation of the timer counter data register (TCDT), write 1 to the timer count
operation bit (TCCS: STOP).
• When the count operation stops (TCCS: STOP = 1), the counter value of the timer counter data register
(TCDT) can be set to any value.
● Factors clearing timer counter data register
The timer counter data register (TCDT) is cleared to "0000H" by the following factors:
of the following events, the overflow clears the register in synchronization with the count clock and each of
the other events clears the register on occurrence of that event.
• Reset
• Writing "1" to the timer count clear bit (TCCS: CLR) (possible even during count operation)
• Writing "0000H" to timer counter data register (TCDT) while count operation stopped
• Overflow in 16-bit free-run timer
Note:
Always use a word instruction (MOVW) to set the timer counter data register (TCDT).
227
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.3.3
Input Capture Control Status Registers (ICS01 and
ICS23)
The input capture control status registers sets the operation of input captures. The
ICS01 register sets the operation of input captures 0 and 1 and the ICS23 sets the
operation of input captures 2 and 3.
The input capture control status registers provides the following settings:
• Selecting the edge to be detected
• Enabling or disabling an interrupt when the edge is detected
• Checking and clearing the valid edge detection flag when the edge is detected
■ Input Capture Control Status Registers (ICS01 and ICS23)
Figure 7.3-4 Input Capture Control Status Registers (ICS01 and ICS23)
Addresses:
ch.0, ch.1 000054H
ch.2, ch.3 000055H
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 1 bit 0
EG01 EG00
Input capture 0 (2) Edge select bits
0
0
No edge detection
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
bit 3 bit 2
EG11 EG10
Operation disable
Operation enable
Input capture 1 (3) Edge select bit
0
0
No edge detection
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
Operation disable
Operation enable
bit 4
ICE0
0
1
Input capture 0 (2) Interrupt enable bit
Input capture 0 (2) Interrupt disable
Input capture 0 (2) Interrupt enable
bit 5
ICE1
0
1
Input capture 1 (3) Interrupt enable bit
Input capture 1 (3) Interrupt disable
Input capture 1 (3) Interrupt enable
bit 6
ICP0
0
1
Input capture 0 (2) Valid edge detection flag bit
Read
Write
Input capture 0 (2)
Clears ICP0 bit
No valid edge detected
Input capture 0 (2)
No effect
Valid edge detected
bit 7
ICP1
0
Input capture 1 (3) Valid edge detection flag bit
Read
Input capture 1 (3)
No valid edge detected
Input capture 1 (3)
Valid edge detected
1
R/W : Read/Write
: Reset value
The numbers in parentheses indicate channel number of ICS 23.
228
Write
Clears ICP1 bit
No effect
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
Table 7.3-3 Functions of Input Capture Control Status Register (ICS01) (1/2)
Bit Name
Function
bit 7
ICP1:
Input capture 1 valid
edge detection flag bit
This bit indicates the edge detection by input capture 1.
• When the valid edge selected by the input capture 1 edge select bits (EG11,
EG10) is detected, the ICP1 bit is set to "1".
• When the valid edge is detected by input capture 1 (ICP1 = 1) when an
interrupt due to the edge detection by input capture 1 is enabled (ICE1 = 1),
an interrupt is generated.
When set to "0":
The bit is cleared.
When set to "1":
No effect
When EI2OS started:
The bit is cleared.
Read by read modify write (RMW) instructions:
"1" is always read.
bit 6
ICP0:
Input capture 0 valid
edge detection flag bit
This bit indicates the edge detection by input capture 0.
• When the valid edge selected by the input capture 0 edge select bits (EG01,
EG00) is detected, the ICP0 bit is set to "1".
• When the valid edge is detected by input capture 0 (ICP0 = 1) when an
interrupt due to the edge detection by input capture 0 is enabled (ICE0 = 1),
an interrupt is generated.
When set to "0":
The bit is cleared.
When set to "1":
No effect
When EI2OS started:
The bit is cleared.
Read by read modify write (RMW) instructions:
"1" is always read.
bit 5
ICE1:
Input capture 1 interrupt
enable bit
This bit enables or disables an interrupt when the edge is detected by input
capture 1.
When set to "0":
No interrupt is generated even when the edge is detected by input capture 1.
When set to "1":
An interrupt is generated when the edge is detected by input capture 1.
bit 4
ICE0:
Input capture 0 interrupt
enable bit
This bit enables or disables an interrupt when the edge is detected by input
capture 0.
When set to "0":
No interrupt is generated even when the valid edge is detected by input
capture 0.
When set to "1":
An interrupt is generated when the valid edge is detected by input capture 0.
229
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
Table 7.3-3 Functions of Input Capture Control Status Register (ICS01) (2/2)
Bit Name
230
Function
bit 3,
bit 2,
EG11, EG10:
Input capture 1 edge
select bits
These bits enable or disable the operation of input capture 1.
The edge detected by input capture 1 is selected when the operation of input
capture 1 is enabled.
EG01, EG00 = 00B:
The operation of input capture 1 is disabled and no edge is detected.
EG01, EG00 = 00B:
The operation of input capture 1 is enabled and the edge is detected.
bit 1,
bit 0,
EG00, CEG01:
Input capture 0 edge
select bits
These bits enable or disable the operation of input capture 0.
The edge detected by input capture 0 is selected when the operation of input
capture 0 is enabled.
EG01, EG00 = 00B:
The operation of input capture 0 is disabled and no edge is detected.
EG01, EG00 = 00B:
The operation of input capture 0 is enabled and the edge is detected.
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.3.4
Input Capture Data Registers 0 to 3 (IPCP0 to IPCP3)
The input capture data registers 0 to 3 (IPCP0 to IPCP3) store the counter value of the
16-bit free-run timer read in the timing with the edge detection by the input capture. The
counter value of the 16-bit free-run timer is stored in the input capture data registers
(IPCP0 to IPCP3) corresponding to the input pins (IN0 to IN3) to which an external signal
is input.
■ Input Capture Data Registers 0 to 3 (IPCP0 to IPCP3)
Figure 7.3-5 Input Capture Data Registers 0 to 3 (IPCP0 to IPCP3)
Input capture data
register (IPCP): High
Addresses:
ch.0 000050H
ch.1 000052H
ch.2 00005AH
ch.3 00005CH
Input capture data
register (IPCP): Low
Addresses:
ch.0 000051H
ch.1 000053H
ch.2 00005BH
ch.3 00005DH
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
CP15
CP14 CP13 CP12 CP11 CP10
CP9
CP8
R
R
R
R
R
R
R
R
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CP7
CP6
CP5
CP4
CP3
CP2
CS1
CP0
R
R
R
R
R
R
R
R
Reset value
XXXXXXXXB
Reset value
XXXXXXXXB
R: Read only
X: Undefined
■ Operation of Input Capture Data Registers 0 to 3 (IPCP0 to IPCP3)
• At the same time that the edges of signals input from the input pins (IN0 to IN3) of the 16-bit input/
output timer are detected, the counter value of the 16-bit free-run timer is stored in the input capture data
registers 0 to 3 (IPCP0 to IPCP3) corresponding to the input pins (IN0 to IN3).
Note:
Always use a word instruction (MOVW) to read the input capture data registers 0 to 3 (IPCP0 to
IPCP3).
231
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.4
Interrupts of 16-bit Input/Output Timer
The interrupt factors of the 16-bit input/output timer include an overflow in the 16-bit
free-run timer and edge detection by the input capture. Interrupt generation starts
EI2OS.
■ Interrupt Control Bits and Interrupt Factors of 16-bit Input/Output Timer
Table 7.4-1 shows the interrupt control bits and interrupt factors of the 16-bit input/output timer.
Table 7.4-1 Interrupt Control Bits and Interrupt Factors of 16-bit Input/Output Timer
Interrupt Name
Overflow Interrupt
Input Capture Interrupt
Overflow in counter value of
16-bit free-run timer
Valid edge input to input pins (IN0 to IN3) of input capture
IN0
IN1
IN2
IN3
Interrupt request flag bit
TCCS: IVF
ICS01: ICP0
ICS01: ICP1
ICS23: ICP0
ICS23: ICP1
Interrupt enable bit
TCCS: IVFE
ICS01: ICE0
ICS01: ICE1
ICS23: ICE0
ICS23: ICF
Interrupt factor
● 16-bit free-run timer interrupt
• When the counter value of the timer counter data register (TCDT) increments from "FFFFH" to
"0000H", an overflow occurs and the overflow generation flag bit (TCCS: IVF) is set simultaneously to
"1".
• When an overflow occurs (TCCS: IVF = 1) with an overflow interrupt enabled (TCCS: IVFE = 1), an
overflow interrupt is generated.
● Input capture interrupt
• When the valid edge selected by the input capture edge select bit (ICS: EG) is detected, the input
capture interrupt request flag bits (ICS01, ICS23: ICP1, ICP0) corresponding to the input pins (IN0 to
IN3) are set to "1".
• When the valid edge is detected by the input captures corresponding to the input pins (IN0 to IN3) with
the input capture interrupts corresponding to the input pins (IN0 to IN3) enabled, an input capture
interrupt is generated.
■ Correspondence between 16-bit Input/Output Timer Interrupt and EI2OS
For details of the interrupt number, interrupt control register, and interrupt vector address, see "3.5
Interrupt".
■ 16-bit Input/Output Timer Interrupts and EI2OS Function
The 16-bit input/output timer corresponds to the EI2OS function. The generation of enabled interrupt starts
the EI2OS. However, it is necessary to disable generation of interrupt requests by resources sharing the
interrupt control register (ICR) with the 16-bit input/output timer.
232
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.5
Explanation of Operation of 16-bit Free-run Timer
After a reset, the 16-bit free-run timer starts incrementing from "0000H". When the
counter value is incremented from "FFFFH" to "0000H", an overflow occurs.
■ Setting of 16-bit Free-run Timer
Operation of the 16-bit free-run timer requires the setting shown in Figure 7.5-1.
Figure 7.5-1 Setting of 16-bit Free-run Timer
bit15
14
13
12
11
10
TCCS
9
bit8
bit7
6
5
4
3
2
1
bit0
IVF
IVFE
STOP
Reserved
CLR
CLK2
CLK1
CLK0
0
0
0
TCDT
Counter value of 16-bit free-run timer
: Used bit
0
: Set 0
Reserved : Always set to "0"
■ Operation of 16-bit Free-run Timer
• After a reset, the 16-bit free-run timer starts incrementing from "0000H" in synchronization with the
count clock selected by the count clock select bits (TCCS: CLK2, CLK1, CLK0).
• When the counter value of the timer counter data register (TCDT) is incremented from "FFFFH" to
"0000H", an overflow occurs. When an overflow occurs, the overflow generation flag bit (TCCS: IVF)
is set to "1" and the 16-bit free-run timer starts incrementing again from "0000H".
• When an overflow occurs (TCCS: IVF = 1) with an overflow interrupt enabled (TCCS: IVFE = 1), an
overflow interrupt is generated.
• When stopping the count operation of the timer counter data register (TCDT), write 1 to the timer count
bit (TCCS: STOP).
• Set the counter value in the timer counter data register (TCDT) after stopping the count operation of the
16-bit free-run timer. After completing setting of the counter value, enable the count operation of the
16-bit free-run timer (TCCS: STOP = 0).
233
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
■ Operation Timing of 16-bit Free-run Timer
Figure 7.5-2 shows counter clearing at an overflow.
Figure 7.5-2 Counter Clearing at an Overflow
Counter value
Overflow
FFFFH
BFFF H
7FFFH
3FFFH
0000H
Reset
Overflow interrupt
234
Time
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.6
Explanation of Operation of Input Capture
When the input capture detects the edge of the external signal input to the input pin, it
stores the counter value of the 16-bit free-run timer in the input capture data register.
■ Setting of Input Capture
Operation of the input capture requires the setting shown in Figure 7.6-1.
Figure 7.6-1 Setting of Input Capture
bit15
14
13
12
ICS
IPCP
11
10
9
bit8
bit7
6
5
4
ICP1
ICP0
ICE1
ICE0
3
2
1
bit0
EG11 EG10 EG01 EG00
Retains counter value of 16-bit free-run timer
DDR (port direction register)
Set the bit corresponding to the pin
used as capture input pin to "0".
: Used bit
235
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
■ Operation of Input Capture
• When the valid edges of the external signals input to the input pins (IN0 to IN3) are detected, the input
capture valid edge detection flag bit (ICS: ICP) corresponding to the input pin is set to "1". At the same
time, the counter value of the 16-bit free-run timer is stored in the input capture data registers (IPCP)
corresponding to the input pins (IN0 to IN3).
• The edge to be detected can be selected from the rising edge, falling edge and both edges by setting the
input capture edge select bit in the input capture control status register (ICS: EG).
• When the effective edge is detected by the input captures corresponding to the input pins (IN0 to IN3)
when the input captures corresponding to the input pins (IN0 to IN3) are enabled for interrupts, an input
capture interrupt is generated.
• The input capture valid edge detection flag bit (ICS: ICP) is set when the valid edge is detected,
regardless of the interrupt enable settings (ICS01, ICS23: ICE1, ICE0).
• Table 7.6-1 shows the correspondence between the input pins and input captures.
Table 7.6-1 Correspondence between Input Pins and Input Captures
236
Input Pin
Interrupt Request Flag
Bit of Input Capture
Interrupt Output Enable
Bit of Input Capture
Input Capture Data
Register
IN0
ICS01: ICP0
ICS01: ICE0
IPCP0
IN1
ICS01: ICP1
ICS01: ICE1
IPCP1
IN2
ICS23: ICP0
ICS23: ICE0
IPCP2
IN3
ICS23: ICP1
ICS23: ICE1
IPCP3
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
■ Operation Timing of Input Capture
Figure 7.6-2 shows the timing of reading the counter value of the 16-bit free-run timer.
Figure 7.6-2 Timing of Reading Counter Value of Input Capture
φ
Counter value
N+1
N
Input capture input
Valid edge
Capture signal
Input capture data
register (IPCP)
N+1
Input capture interrupt
φ: Machine clock
Reads counter value
Figure 7.6-3 shows the timing of the capture operation depending on the edge type.
Figure 7.6-3 Timing of Capture Operation Depending on Edge Type
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
IN0 (Rising edge)
IN1 (Falling edge)
IN2 (Both edges)
Input capture data
register 0 (IPCP0)
Undefined
Input capture data
register1 (IPCP1)
Undefined
Input capture data
register 2 (IPCP2)
Undefined
3FFFH
7FFFH
BFFFH
3FFFH
Input capture 0
interrupt
Input capture 1
interrupt
Input capture 2
interrupt
237
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.7
Precautions when Using 16-bit Input/Output Timer
This section explains the precautions when using the 16-bit input/output timer.
■ Precautions when 16-bit Input/Output Timer
● Precautions when setting 16-bit free-run timer
• Do not change the count clock select bits (TCCS: CLK2, CLK1, CLK0) during the count operation
(TCCS: STOP = 0).
• The counter value of the 16-bit free-run timer is cleared to "0000H" by reset. The 16-bit free-run timer
can be set by writing any count value to the timer counter data register (TCDT) while the count
operation is stopped (TCCS: STOP = 1).
• Always use a word instruction (MOVW) to set the timer counter data register (TCDT).
● Precautions on interrupts
• When an overflow interrupt or an input capture interrupt is enabled, clear only the set bit of the overflow
generation flag bit or the input capture valid edge detection flag bit. For example, when clearing the flag
bit for the factor that accepted an interrupt, avoid unconditional clearing of the interrupt request flag bits
other than those for the factor accepting the interrupt, otherwise another input capture interrupt may be
generated.
• If the interrupt request flag bits in the 16-bit input/output timer (TCCS: IVF, ICS01, ICS23: ICP1, ICP0) are
set to "1" and interrupts corresponding to the set interrupt request flag bits are enabled (TCCS: IVFE = 1,
ICS01, ICS23: ICE1 = 1, ICE0 = 1), it is impossible to return from interrupt processing. Always clear
the interrupt request flag bits. When using the EI2OS, the set interrupt request flag bits are cleared
automatically when the EI2OS is started.
238
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
7.8
Program Example of 16-bit Input/Output Timer
This section gives a program example of the 16-bit input/output timer.
■ Processing of Program for Measuring Cycle Using Input Capture
• The cycle of a signal input to the IN0 pin is measured.
• The 16-bit free-run timer and input capture 0 are used.
• The rising edge is selected as the edge to be detected.
• The machine clock (φ) is 16 MHz and the count clock is φ/4 (0.25 μs).
• The overflow interrupt and input capture interrupt of input capture 0 are used.
• The overflow interrupt of the 16-bit free-run timer is counted beforehand and used for the cycle
calculation.
• The cycle can be determined from the following equation:
Cycle = (overflow count × 10000H+ nth IPCP0 value - (n-1)th IPCP0 value) × count clock cycle
= (overflow count × 10000H+ nth IPCP0 value - (n-1)th IPCP0 value) × 0.25μs
● Coding example
DDR1
TCCS
TCDT
ICS01
IPCP0
IVFE
ICP0
ICR04
ICR06
DATA
EQU 000011H
; Port direction register
EQU 000058H
; Timer counter control status register
EQU 000056H
; Timer counter data register
EQU 000054H
; Input capture control status register 01
EQU 000050H
; Input capture data register 0
EQU TCCS:5
; Overflow interrupt enable bit
EQU ICS01:6
; Input capture 0 interrupt request flag bit
EQU 0000B4H
; 16-bit free-run timer interrupt control register
EQU 0000B6H
; 16-bit input capture interrupt control register
DSEG ABS=00H
ORG 0100H
OV_CNT RW
1
; Overflow counter
DATA
ENDS
;-----Main program--------------------------------------------------------------CODE
CSEG ABS=0FFH
START:
; Stack pointer (SP)
; already initialized
:
AND CCR,#0BFH
; Interrupt disabled
MOV I:ICR04,#00H
; Interrupt level 0 (highest)
MOV I:ICR06,#00H
; Interrupt level 0 (highest)
MOV I:DDR1,#00000000B ; Pin set as input
239
CHAPTER 7 16-BIT INPUT/OUTPUT TIMER
MOV
MOV
I:TCCS,#00110100B
;
;
;
I:ICS01,#00010001B ;
;
;
;
;
ILM,#07
;
CCR,#40H
;
Count operation enabled, counter cleared,
Overflow, interrupt enabled
Count clock of φ/4 selected
INO pin selected
IPCP0 set to rising edge
IPCP1 set to no edge detection
Each interrupt request flag cleared
Input capture interrupt request enabled
Interrupt mask level set and interrupt enabled
Interrupt enabled
MOV
OR
:
;-----Interrupt program---------------------------------------------------------WARI1
CLRB I:ICP0
; Input capture 0 interrupt request
; flag cleared
:
User Processing (such as cycle calculation)
:
MOV A,0
; Overflow because of next cycle measurement
; Counter cleared
MOV
D:OV_CNT,A
RETI
; Return from interrupt
WARI2
CLRB I:IVFE
; Overflow interrupt request flag cleared
INC D:OV_CNT
; Overflow counter incremented by one
RETI
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG 0FFA0
; Vector set to interrupt number #23 (17H)
DSL WARI1
; Input capture 0 interrupt
ORG 0FFB0
; Vector set to interrupt number #19 (13H)
DSL WARI2
; Overflow interrupt
ORG 0FFDCH
; Reset vector set
DSL START
DB
00H
; Set to single-chip mode
VECT
ENDS
END START
240
CHAPTER 8
16-BIT RELOAD TIMER
This chapter explains the functions and the operations
of 16-bit reload timer.
8.1 Overview of 16-bit Reload Timer
8.2 Block Diagram of 16-bit Reload Timer
8.3 Configuration of 16-bit Reload Timer
8.4 Interrupts of 16-bit Reload Timer
8.5 Explanation of Operation of 16-bit Reload Timer
8.6 Precautions when Using 16-bit Reload Timer
8.7 Program Example of 16-bit Reload Timer
241
CHAPTER 8 16-BIT RELOAD TIMER
8.1
Overview of 16-bit Reload Timer
The 16-bit reload timer has the following functions:
• The count clock can be selected from three internal clocks and external event clocks.
• A software trigger or external trigger can be selected as the start trigger.
• If the 16-bit timer register (TMR) underflows, an interrupt can be generated to the
CPU. The 16-bit reload timer can be used as an interval timer by using an interrupt.
• If the TMR underflows, either the one-shot mode for stopping the TMR count
operation, or the reload mode for reloading the value of the 16-bit reload register
(TMRLR) to the TMR to continue the TMR count operation can be selected.
• The 16-bit reload timer corresponds to the EI2OS.
• The MB90385 series has two channels of 16-bit reload timers.
■ Operation Modes of 16-bit Reload Timer
Table 8.1-1 indicates the operation modes of the 16-bit reload timer.
Table 8.1-1 Operation Modes of 16-bit Reload Timer
Count Clock
Start Trigger
Operation Performed upon Underflow
Internal clock mode
Software trigger
External trigger
One-shot mode
Reload mode
Event count mode
Software trigger
One-shot mode
Reload mode
■ Internal Clock Mode
• When the count clock select bits in the timer control status register (TMCSR: CSL1, CSL0) are set to
"00B", "01B" or "10B", the 16-bit reload timer is set in the internal clock mode.
• In the internal clock mode, the 16-bit reload timer decrements in synchronization with the internal clock.
• The count clock select bits in the timer control status register (TMCSR: CSL1, CSL0) can be used to
select three count clock cycles.
• The start trigger sets the edge detection for a software trigger or an external trigger.
■ Event Count Mode
• When the count clock select bits in the timer control status register (TMCSR: CSL1, CSL0) are set to
"11B", the 16-bit reload timer is set to the event count mode.
• In the event count mode, the 16-bit reload timer decrements in synchronization with the edge detection
of the external event clock input to the TIN pin.
• A software trigger is selected as the start trigger.
• The 16-bit reload timer can be used as an interval timer by using a fixed cycle of the external clock.
242
CHAPTER 8 16-BIT RELOAD TIMER
■ Operation at Underflow
When the start trigger is input, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit
timer register, starts decrementing in synchronization with the count clock. When the 16-bit timer register
(TMR) is decremented from "0000H" to "FFFFH", an underflow occurs.
• When an underflow occurs with an underflow interrupt enabled (TMCSR: INTE = 1), an underflow
interrupt is generated.
• The 16-bit reload timer operation when an underflow occurs is set by the reload select bit in the timer
control status register (TMCSR: RELD).
[One-shot mode (TMCSR: RELD = 0)]
When an underflow occurs, the TMR count operation is stopped. When the next start trigger is input, the
value set in the TMRLR is reloaded in the TMR, starting the TMR count operation.
• In the one-shot mode, during the TMR count operation, a High-level or Low-level rectangular wave is
output from the TOT pin.
• The pin output level select bit in the timer control status register (TMCSR: OUTL) can be set to select
the level (High or Low) of the rectangular wave.
[Reload mode (TMCSR: RELD = 1)]
When an underflow occurs, the value set in the TMRLR is reloaded to the TMR, continuing the TMR count
operation.
• In the reload mode, a toggle wave inverting the output level of the TOT pin is output each time an
underflow occurs during the TMR count operation.
• The pin output level select bit in the timer control status register (TMCSR: OUTL) can be set to select
the level (High or Low) of a toggle wave.
• The 16-bit reload timer can be used as an interval timer by using an underflow interrupt.
Table 8.1-2 Interval Time of 16-bit Reload Timer
Count Clock
Internal clock mode
Event count mode
Count Clock Cycle
Interval Time
21T (0.125 μs)
0.125 μs to 8.192 ms
23T (0.5 μs)
0.5 μs to 32.768 ms
25T (2.0 μs)
2.0 μs to 131.1 ms
23T or more
0.5 μs
T: Machine cycle
The values in interval time and the parenthesized values are provided when the machine clock operates at
16 MHz.
Reference:
The 16-bit reload timer 1 can be used as the clock input source of the UART1 and the start trigger of
the A/D converter.
243
CHAPTER 8 16-BIT RELOAD TIMER
8.2
Block Diagram of 16-bit Reload Timer
The 16-bit reload timers 0 and 1 are composed of the following seven blocks:
• Count clock generator
• Reload controller
• Output controller
• Operation controller
• 16-bit timer register (TMR)
• 16-bit reload register (TMRLR)
• Timer control status register (TMCSR)
■ Block Diagram of 16-bit Reload Timer
Figure 8.2-1 Block Diagram of 16-bit Reload Timer
Internal data bus
TMRLR
16-bit reload register
Reload signal
Reload
controller
TMR
16-bit timer register UF
CLK
Count clock generator
Machine
clock φ
Prescaler
3
Gate
input
Valid
clock
detector
Wait signal
Output to
internal resource
Clear
Internal
clock
CLK
Input
controller
Pin
TIN
Clock
selector
External clock
3
2
⎯
⎯
Output signal
generator
Pin
TOT
EN
Select
signal
Function selected
⎯
Output controller
Operation
controller
⎯ CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG
Timer control status register (TMCSR)
Interrupt request
output
244
CHAPTER 8 16-BIT RELOAD TIMER
● Details of pins in block diagram
There are two channels for 16-bit reload timer.
The actual pin names, outputs to resources, and interrupt request numbers for each channel are as follows:
16-bit reload timer 0:
TIN pin: P20/TIN0
TOT pin: P21/TOT0
Interrupt request number: #17 (11H)
16-bit reload timer 1:
TIN pin: P22/TIN1
TOT pin: P23/TOT1
Output to resources: Clock input source of UART1 and start trigger of A/D converter
Interrupt request number: #36 (24H)
● Count clock generator
The count clock generator generates a count clock supplied to the 16-bit timer register (TMR) on the basis
of the machine clock or external event clock.
● Reload controller
When the 16-bit reload timer starts operation or the TMR underflows, the reload controller reloads the
value set in the 16-bit reload register (TMRLR) to the TMR.
● Output controller
The output controller inverts and enables or disables the output of the TOT pin at underflow.
● Operation controller
The operation controller starts or stops the 16-bit reload timer.
● 16-bit timer register (TMR)
The 16-bit timer register (TMR) is a 16-bit down counter. At read, the value being counted is read.
● 16-bit reload register (TMRLR)
The 16-bit reload register (TMRLR) sets the interval time of the 16-bit reload timer. When the 16-bit reload
timer starts operation or the 16-bit timer register (TMR) underflows, the value set in the TMRLR is
reloaded to the TMR.
● Timer control status register (TMCSR)
The timer control status register (TMCSR) selects the operation mode, sets the operation conditions, selects
the start trigger, performs a start using the software trigger, selects the reload operation mode, enables or
disables an interrupt request, sets the output level of the TOT pin, and sets the TOT output pin.
245
CHAPTER 8 16-BIT RELOAD TIMER
8.3
Configuration of 16-bit Reload Timer
This section explains the pins, registers, and interrupt factors of the 16-bit reload timer.
■ Pins of 16-bit Reload Timer
The pins of the 16-bit reload timer serve as general-purpose I/O ports. Table 8.3-1 shows the pin functions
and the pin settings required to use the 16-bit reload timer.
Table 8.3-1 Pins of 16-bit Reload Timer
Pin Name
Pin Function
Pin Setting Required for Use in
16-bit Reload Timer
TIN0
General-purpose I/O port,
16-bit reload timer input
Set as input port in port direction register (DDR).
TOT0
General-purpose I/O port,
16-bit reload timer output
Set timer output enable (TMCSR0: OUTE = 1).
TIN1
General-purpose I/O port,
16-bit reload timer input
Set as input port in port direction register (DDR).
TOT1
General-purpose I/O port,
16-bit reload timer output
Set timer output enable (TMCSR1: OUTE = 1).
■ Block Diagram for Pins of 16-bit Reload Timer
Reference:
Refer to "CHAPTER 4 I/O PORT" for the block diagrams of pins.
246
CHAPTER 8 16-BIT RELOAD TIMER
■ List of Registers and Reset Values of 16-bit Reload Timer
● Registers of 16-bit reload timer 0
Figure 8.3-1 List of Registers and Reset Values of 16-bit Reload Timer 0
bit
Timer control status register (High)
(TMCSR0)
bit
Timer control status register (Low)
(TMCSR0)
bit
16-bit timer register (High)
(TMR0)
bit
16-bit timer register (Low)
(TMR0)
bit
16-bit reload register (High)
(TMRLR0)
bit
16-bit reload register (Low)
(TMRLR0)
15
14
13
12
11
10
9
8
X
X
X
X
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X: Undefined
● Registers of 16-bit reload timer 1
Figure 8.3-2 List of Registers and Reset Values of 16-bit Reload Timer 1
bit
Timer control status register (High)
(TMCSR1)
bit
Timer control status register (Low)
(TMCSR1)
bit
16-bit timer register (High)
(TMR1)
bit
16-bit timer register (Low)
(TMR1)
bit
16-bit reload register (High)
(TMRLR1)
bit
16-bit reload register (Low)
(TMRLR1)
15
14
13
12
11
10
9
8
X
X
X
X
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X: Undefined
247
CHAPTER 8 16-BIT RELOAD TIMER
■ Generation of Interrupt Request from 16-bit Reload Timer
When the 16-bit reload timer is started and the count value of the 16-bit timer register is decremented from
"0000H" to "FFFFH", an underflow occurs. When an underflow occurs, the UF bit in the timer control
status register is set to "1" (TMCSR: UF). If an underflow interrupt is enabled (TMCSR: INTE = 1), an
interrupt request is generated.
248
CHAPTER 8 16-BIT RELOAD TIMER
8.3.1
Timer Control Status Registers (High) (TMCSR0: H,
TMCSR1: H)
The timer control status registers (High) (TMCSR0: H, TMCSR1: H) set the operation
mode and count clock.
This section also explains the bit 7 in the timer control status registers (Low) (TMCSR0:
L, TMCSR1: L).
■ Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H)
Figure 8.3-3 Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H)
15 14 13 12 11 10 9
7
8
Addresses:
ch.0 000067H
ch.1 000069H
⎯ ⎯ ⎯ ⎯ R/W R/W R/W R/W R/W
Reset value
XXXX00000B
bit 9 bit 8 bit 7
MOD2 MOD1 MOD0
0
0
0
0
1
1
0
0
1
1
×
×
0
1
0
1
0
1
Operation mode select bits (internal clock mode)
(CSL1, 0 = "00B", "01B", "10B")
Function of input pin
Trigger disable
Trigger input
Gate input
Valid edge, level
⎯
Rising edge
Falling edge
Both edges
Low level
High level
bit 9 bit 8 bit 7
MOD2 MOD1 MOD0
×
×
×
×
0
0
1
1
0
1
0
1
Operation mode select bits (event count mode)
(CSL1, 0="11B")
Function of input pin
Valid edge
⎯
⎯
Rising edge
Trigger input
Falling edge
Both edges
bit 11 bit 10
CSL1 CSL0
R/W :
×
:
⎯
:
:
Read/Write
Undefined
Unused
Reset value
Count clock select bits
Count clock
Count clock cycle
21T
Internal clock mode
23T
0
0
0
1
1
0
Event count mode
1
1
T: Machine cycle
25T
External event clock
249
CHAPTER 8 16-BIT RELOAD TIMER
Table 8.3-2 Functions of Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H)
Bit Name
bit 15 to bit 12
bit 11,
bit 10
bit 9 to bit 7
250
Function
Unused bits
Read: The value is undefined.
Write: No effect
CSL1, CSL0:
Count clock select bits
These bits select the count clock of the 16-bit reload timer.
When set to anything other than "11B": This bits count by the internal
clock (internal clock mode).
When set to "11B": The edge of the external event clock is counted
(event count mode)
MOD2, MOD1, MOD0:
Operation mode select
bits
These bits set the operation conditions of the 16-bit reload timer.
[Internal clock mode]
The MOD2 bit is used to select the function of the input pin.
When MOD2 bit set to "0":
The input pin functions as a trigger input.
The MOD1 and MOD0 bits are used to select the edge to be detected.
When the edge is detected, the value set in the 16-bit reload register
(TMRLR) is reloaded in the 16-bit timer register (TMR), starting the count
operation of the TMR.
When MOD2 set to "1":
The input pin functions as a gate input.
The MOD1 bit is not used. The MOD0 bit is used to select the signal level
(High or Low) to be detected. The count operation of the 16-bit timer register
(TMR) is performed only when the signal level is input.
[Event count mode]
The MOD2 bit is not used. An external event clock is input from the input
pin. The MOD1 and MOD0 bits are used to select the edge to be detected.
CHAPTER 8 16-BIT RELOAD TIMER
8.3.2
Timer Control Status Registers (Low) (TMCSR0: L,
TMCSR1: L)
The timer control status registers (Low) (TMCSR0: L, TMCSR1: L) enables or disables
the timer operation, checks the generation of a software trigger or an underflow,
enables or disables an underflow interrupt, selects the reload mode, and sets the output
of the TOT pin.
■ Timer Control Status Registers (Low) (TMCSR0: L, TMCSR1: L)
Figure 8.3-4 Timer Control Status Registers (Low) (TMCSR0: L, TMCSR1: L)
Addresses:
ch.0 000066H
ch.1 000068H
7
6
5
4
3
2
1
0
Reset value
*
00000000B
R/W R/W R/W R/W R/W R/W R/W
bit 0
TRG
0
1
Software trigger bit
No effect
After reloading, starts counting
bit 1
CNTE
0
1
Timer operation enable bit
Timer operation disable
Timer operation enable (start trigger wait)
bit 2
UF
0
1
bit 3
INTE
0
1
Underflow generation flag bit
Read
Write
No underflow
Underflow
Clears UF bit
No effect
Underflow interrupt enable bit
Underflow interrupt disable
Underflow interrupt enable
bit 4
RELD
0
1
Reload select bit
One-shot mode
Reload mode
bit 5
OUTL
0
1
TOT pin output level select bit
One-shot mode
Reload mode
(RELD=0)
(RELD=1)
High rectangular wave output during counting
Low toggle output at starting reload timer
Low rectangular wave output during counting
High toggle output at starting reload timer
bit 6
TOT pin output enable bit
OUTE
0
1
Pin function
Register and pin corresponding to each channel
TMCSR0
TMCSR1
General-purpose I/O port General-purpose I/O port General-purpose I/O port
R/W : Read/Write
TOT0
TOT1
TOT output
: Reset value
: For MOD0 (bit 7), see section 8.3.1 "Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H)".
*
251
CHAPTER 8 16-BIT RELOAD TIMER
Table 8.3-3 Timer Control Status Registers (Low) (TMCSR0: L, TMCSR1: L)
Bit Name
252
Function
bit 6
OUTE:
TOT Output enable bit
This bit sets the function of the TOT pin of the 16-bit reload timer.
When set to "0": Functions as general-purpose I/O port
When set to "1": Functions as TOT pin of 16-bit reload timer
bit 5
OUTL:
TOT Pin output level
select bit
This bit sets the output level of the output pin of the 16-bit reload timer.
<One-shot mode (RELD = 0)>
When set to "0":Outputs "H" level rectangular wave during TMR count
operation
When set to "1":Outputs "L" level rectangular wave during TMR count
operation
<Reload mode (RELD = 1)>
When set to "0": Outputs "L" level toggle wave when 16-bit reload timer
started
When set to "1": Outputs "H" level toggle wave when 16-bit reload timer
started
bit 4
RELD:
Reload select bit
This bit sets the reload operation at underflow.
When set to "1": At underflow, reloads value set in TMRLR to TMR,
continuing count operation (reload mode)
When set to "0": At underflow, stops count operation (one-shot mode)
bit 3
INTE:
Underflow interrupt
enable bit
This bit enables or disables an underflow interrupt.
When an underflow occurs (TMCSR: UF = 1) with an underflow interrupt
enabled (TMCSR: INTE = 1), an interrupt request is generated.
bit 2
UF:
Underflow generation
flag bit
This bit indicates that the TMR underflows.
When set to "0": Clears this bit
When set to "1": No effect
Read by read modify write instructions: "1" is always read.
bit 1
CNTE:
Timer operation enable
bit
This bit enables or disables the operation of the 16-bit reload timer.
When set to "1": 16-bit reload timer enters start trigger wait state.
When the start trigger is input, the timer register restarts count operation.
When set to "0": Stops count operation
bit 0
TRG:
Software trigger bit
This bit starts the 16-bit reload timer by software.
The software trigger function works only when the timer operation is enabled
(CNTE = 1).
When set to "0": Disabled. The state remains unchanged.
When set to "1": Reloads value set in 16-bit reload register (TMRLR) to 16-bit
timer register (TMR), starting TMR count operation
Read: "0" is always read.
CHAPTER 8 16-BIT RELOAD TIMER
8.3.3
16-bit Timer Registers (TMR0, TMR1)
The 16-bit timer registers (TMR0, TMR1) are 16-bit down counters. At read, the value
being counted is read.
■ 16-bit Timer Registers (TMR0, TMR1)
Figure 8.3-5 16-bit Timer Registers (TMR0, TMR1)
TMR0
TMR1
TMR0
TMR1
15
14
13
12
11
10
9
8
D15
D14
D13
D12
D11
D10
D9
D8
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
Reset value
XXXXXXXXB
Reset value
XXXXXXXXB
R: Read only
X: Undefined
When the timer operation is enabled (TMCSR: CNTE = 1) and the start trigger is input, the value set in the
16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR), starting the TMR count
operation.
When the timer operation is disabled (TMCSR: CNTE = 0), the TMR value is retained.
When the TMR value is counted down from "0000H" to "FFFFH" during the TMR count operation, an
underflow occurs.
[Reload mode]
When the TMR underflows, the value set in the TMRLR is reloaded to the TMR, starting the TMR count
operation.
[One-shot mode]
When the TMR underflows, the TMR count operation is stopped, entering the start trigger input wait state.
The TMR value is retained to "FFFFH".
Notes:
• The TMR can be read during the TMR count operation. However, always use the word instruction
(MOVW).
• The TMR and the TMRLR are assigned to the same address. At write, the set value can be
written to the TMRLR without affecting the TMR. At read, the TMR value being counted can be
read.
253
CHAPTER 8 16-BIT RELOAD TIMER
8.3.4
16-bit Reload Registers (TMRLR0, TMRLR1)
The 16-bit reload registers (TMRLR0, TMRLR1) set the value to be reloaded to the 16-bit
timer register (TMR). When the start trigger is input, the value set in the 16-bit reload
registers (TMRLR0, TMRLR1) is reloaded to the TMR, starting the TMR count operation.
■ 16-bit Reload Registers (TMRLR0, TMRLR1)
Figure 8.3-6 16-bit Reload Registers (TMRLR0, TMRLR1)
TMRLR0
TMRLR1
Addresses:
ch.0 003901H
ch.1 003903H
TMRLR0
TMRLR1
Addresses:
ch.0 003900H
ch.1 003902H
15
14
13
12
11
10
9
8
D15
D14
D13
D12
D11
D10
D9
D8
W
W
W
W
W
W
W
W
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
Reset value
XXXXXXXXB
Reset value
XXXXXXXXB
W: Write only
X: Undefined
Set the 16-bit reload registers (TMRLR0, TMRLR1) after disabling the timer operation (TMCSR: CNTE = 0).
After completing setting of the 16-bit reload registers (TMRLR0, TMRLR1), enable the timer operation
(TMCSR: CNTE = 1).
When the start trigger is input, the value set in the TMRLR is reloaded to the TMR, starting the TMR count
operation.
Notes:
• Perform a write to the TMRLR after disabling the operation of the 16-bit reload timer (TMCSR:
CNTE = 0). Always use the word instruction (MOVW).
• The TMRLR and the TMR are assigned to the same address. At write, the set value can be
written to the TMRLR without affecting the TMR. At read, the TMR value being counted is read.
• Instructions, such as the INC/DEC instruction, which provide the read modify write (RMW)
operation cannot be used.
254
CHAPTER 8 16-BIT RELOAD TIMER
8.4
Interrupts of 16-bit Reload Timer
The 16-bit reload timer generates an interrupt request when the 16-bit timer register
(TMR) underflows.
■ Interrupts of 16-bit Reload Timer
When the value of the TMR is decremented from "0000H" to "FFFFH" during the TMR count operation, an
underflow occurs. When an underflow occurs, the underflow generation flag bit in the timer control status
register (TMCSR: UF) is set to "l". When an underflow interrupt is enabled (TMCSR: INTE = 1), an
interrupt request is generated.
Table 8.4-1 Interrupt Control Bits and Interrupt Factors of 16-bit Reload Timer
16-bit Reload Timer 0
16-bit Reload Timer 1
Interrupt request flag bit
TMCSR0: UF
TMCSR1: UF
Interrupt request enable bit
TMCSR0: INTE
TMCSR1: INTE
Interrupt factor
Underflow in TMR0
Underflow in TMR1
■ Correspondence between 16-bit Reload Timer Interrupt and EI2OS
For details of the interrupt number, interrupt control register, and interrupt vector address, see "3.5
Interrupt".
■ EI2OS Function of 16-bit Reload Timer
The 16-bit reload timer corresponds to the EI2OS function. An underflow in the TMR starts the EI2OS.
The EI2OS is available only when other resources sharing the interrupt control register (ICR) do not use
interrupts. When using the EI2OS in the 16-bit reload timers 0 and 1, it is necessary to disable generation of
interrupt requests by resources sharing the interrupt control register (ICR) with the 16-bit reload timers 0
and 1.
255
CHAPTER 8 16-BIT RELOAD TIMER
8.5
Explanation of Operation of 16-bit Reload Timer
This section explains the setting of the 16-bit reload timer and the operation state of the
counter.
■ Setting of 16-bit Reload Timer
● Setting of internal clock mode
Counting the internal clock requires the setting shown in Figure 8.5-1.
Figure 8.5-1 Setting of Internal Clock Mode
TMCSR
bit15
14
13
12
11
10
9
bit8
bit7
6
5
4
3
2
1
bit0
⎯
⎯
⎯
⎯
CSL1
CSL0
MOD2
MOD1
MOD0
OUTE
OUTL
RELD
INTE
UF
CNTE
TRG
1
Except "11B"
TMRLR
Sets a reload value to 16-bit timer register
: Used bit
1 : Set 1
● Setting of event count mode
Inputting an external event to operate the 16-bit reload timer requires the setting shown in Figure 8.5-2.
Figure 8.5-2 Setting of Event Count Mode
TMCSR
bit 15 14
13
12
11
⎯
⎯
⎯
CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG
⎯
1
TMRLR
10
9
8
7
6
5
1
4
3
2
1
bit 0
1
Sets a reload value to 16-bit timer register
Set the bit of DDR (port direction register) corresponding to the pin to be used as TIN pin to "0".
: Used bit
1 : Set 1
256
CHAPTER 8 16-BIT RELOAD TIMER
■ Operating State of 16-bit Timer Register
The operating state of the 16-bit timer register is determined by the timer operation enable bit in the timer
control status register (TMCSR: CNTE) and the WAIT signal. The operating states include the stop state,
start trigger input wait state (WAIT state), and RUN state.
Figure 8.5-3 shows the state transition diagram for the 16-bit timer registers.
Figure 8.5-3 State Transition Diagram
STOP state CNTE = 0, WAIT = 1
TIN pin: input disable
TOT pin: general-purpose I/O port
Reset
16-bit timer register: retain the value at stop
(the value immediately after resetting is undefined)
CNTE = 0
CNTE = 0
CNTE = 1
TRG = 0
WAIT state CNTE = 1, WAIT = 1
TIN pin: only trigger input is valid
TOT pin: outputs value of 16-bit reload
register
RUN state
External trigger from TIN
:
:
WAIT :
TRG :
CNTE :
UF
:
RELD :
CNTE = 1, WAIT = 0
TIN pin: function as input pin of
16-bit reload timer
UF = 1 &
RELD = 0
16-bit timer register: retains the value at stop (one-shot mode)
(the value is undefined until loading immediately after resetting)
TRG = 1
(software trigger)
CNTE = 1
TRG = 1
TOT pin: function as output pin of
16-bit reload timer
UF = 1 & 16-bit timer register : operation
RELD = 1
(reload mode)
TRG = 1
LOAD
CNTE = 1, WAIT = 0
Loads 16-bit reload register value to
16-bit timer register
(software trigger)
Load ended
State transition by hardware
State transition by register access
WAIT signal (internal signal)
Software trigger bit (TMCSR)
Timer operation enable bit (TMCSR)
Underflow generation flag bit (TMCSR)
Reload select bit (TMCSR)
257
CHAPTER 8 16-BIT RELOAD TIMER
8.5.1
Operation in Internal Clock Mode
In the internal clock mode, three operation modes can be selected by setting the
operation mode select bits in the timer control status register (TMCSR: MOD2 to MOD0).
When the operation mode and reload mode are set, a rectangular wave or a toggle wave
is output from the TOT pin.
■ Setting of Internal Clock Mode
• By setting the count clock select bits (CSL1, CSL0) in the timer control status register to "00B", "01B"
or "10B", the 16-bit reload timer (TMRLR) is set to the internal clock mode.
• In the internal clock mode, the 16-bit timer register (TMR) decrements in synchronization with the
internal clock.
• In the internal clock mode, three count clock cycles can be selected by setting the count clock select bits
in the timer control status register (TMCSR: CSL1, CSL0).
[Setting a reload value to TMR]
After the 16-bit reload timer is started, the value set in the TMRLR is reloaded to the TMR.
1. Disables the timer operation (TMCSR: CNTE = 0).
2. Sets a reload value to the TMR in the TMRLR.
3. Enables the timer operation (TMCSR: CNTE = 1).
Note:
It takes 1 machine cycle (time) to reload the value set in the TMRLR to the TMR after the start trigger
is input.
258
CHAPTER 8 16-BIT RELOAD TIMER
■ Operation as 16-bit Timer Register Underflows
When the value of the 16-bit timer register (TMR) is decremented from "0000H" to "FFFFH" during the
TMR count operation, an underflow occurs.
• When an underflow occurs, the underflow generation flag bit in the timer control status register
(TMCSR: UF) is set to "1".
• When the underflow interrupt enable bit in the timer control status register (TMCSR: INTE) is set to
"1", an underflow interrupt is generated.
• The reload operation when an underflow occurs is set by the reload select bit in the timer control status
register (TMCSR: RELD).
[One-shot mode (TMCSR: RELD = 0)]
When an underflow occurs, the count operation of the TMR is stopped, entering the start trigger input wait
state. When the next start trigger is input, the TMR count operation is restarted.
In the one-shot mode, a rectangular wave is output from the TOT pin during the TMR count operation. The
pin output level select bit in the timer control status register (TMCSR: OUTL) can be set to select the level
("H" or "L") of a rectangular wave.
[Reload mode (TMCSR: RELD = 1)]
When an underflow occurs, the value set in the 16-bit reload timer register (TMRLR) is reloaded to the
TMR, continuing the TMR count operation.
In the reload mode, a toggle wave inverting the output level of the TOT pin is output each time an
underflow occurs during the TMR count operation. The pin output level select bit in the timer control status
register (TMCSR: OUTL) can be set to select the level ("H" or "L") of a toggle wave as the 16-bit reload
timer is started.
■ Operation in Internal Clock Mode
In the internal clock mode, the operation mode select bits in the timer control status register (TMCSR:
MOD2 to MOD0) can be used to select the operation mode. Disable the timer operation by setting the timer
operation enable bit in the timer control status register (TMCSR: CNTE).
[Software trigger mode (MOD2 to MOD0 = 000B)]
If the software trigger mode is set, start the 16-bit reload timer by setting the software trigger bit in the
timer control status register (TMCSR: TRG) to "1". When the 16-bit reload timer is started, the value set in
the TMRLR is reloaded to the TMR, starting the TMR count operation.
Note:
When both the timer operation enable bit in the timer control status register (TMCSR: CNTE) and the
software trigger bit in the timer control status register (TMCSR: TRG) are set to "1", the 16-bit reload
timer and the count operation of the TMR are started simultaneously.
259
CHAPTER 8 16-BIT RELOAD TIMER
Figure 8.5-4 Count Operation in Software Trigger Mode (One-shot Mode)
Count clock
Reload data
Counter
-1
0000H FFFFH
Reload data
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
T*
TOT pin
Start trigger input wait
T : Machine cycle
* : It takes 1 machine cycle (time) to load data of reload register from trigger input.
Figure 8.5-5 Count Operation in Software Trigger Mode (Reload Mode)
Count clock
Reload data
Counter
-1
0000H Reload data
-1
0000H Reload data
-1
0000H Reload data
Data load signal
UF bit
CNTE bit
TRG bit
T*
TOT pin
T : Machine cycle
* : It takes 1 machine cycle (time) to load data of reload register from trigger input.
260
-1
CHAPTER 8 16-BIT RELOAD TIMER
[External trigger mode (MOD2 to MOD0 = 001B, 010B, 011B)]
When the external trigger mode is set, the 16-bit reload timer is started by inputting the external valid edge
to the TIN pin. When the 16-bit reload timer is started, the value set in the 16-bit reload register (TMRLR)
is reloaded to the 16-bit timer register (TMR), starting the TMR count operation.
• By setting the operation mode select bits in the timer control status register (TMCSR: MOD2 to
MOD0), the detected edge can be selected from the rising edge, falling edge, and both edges.
Note:
The trigger pulse width of the edge to be input to the TIN pin should be 2 machine cycles (time) or
more.
Figure 8.5-6 Count Operation in External Trigger Mode (One-shot Mode)
Count clock
Counter
Reload data
-1
0000H FFFFH
Reload data
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TIN pin
2T to 2.5T*
TOT pin
Start trigger input wait
T : Machine cycle
* : It takes 2 to 2.5 machine cycles (time) to load data of reload register from external trigger input.
Figure 8.5-7 Count Operation in External Trigger Mode (Reload Mode)
Count clock
Counter
Reload data
-1
0000H Reload data
-1
0000H Reload data
-1
0000H Reload data
-1
Data load signal
UF bit
CNTE bit
TIN pin
TOT pin
2T to 2.5T*
T : Machine cycle
* : It takes 2 to 2.5 machine cycles (time) to load data of reload register from external trigger input.
261
CHAPTER 8 16-BIT RELOAD TIMER
[External gate input mode (MOD2 to MOD0 = 1x0B, 1x1B)]
When the external gate input mode is set, start the 16-bit reload timer by setting the software trigger bit in
the timer control status register (TMCSR: TRG) to "1". When the 16-bit reload timer is started, the value
set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR).
• After the 16-bit reload timer is started, the count operation of the TMR is performed while the set gate
input level is input to the TIN pin.
• The gate input level ("H" or "L") can be selected by setting the operation mode select bits in the timer
control status register (TMCSR: MOD2 to MOD0).
Figure 8.5-8 Count Operation in External Gate Input Mode (One-shot Mode)
Count clock
Reload data
Counter
-1
0000H
-1
FFFFH
Reload data
-1
-1
Data load signal
UF bit
CNTE bit
TRG bit
T*
T*
TIN pin
TOT pin
Start trigger input wait
T : Machine cycle
* : It takes 1 machine cycle (time) to load data of reload register from trigger input.
Figure 8.5-9 Count Operation in External Gate Input Mode (Reload Mode)
Count clock
Counter
Reload data
-1
-1
-1
0000H Reload data
-1
-1
Data load signal
UF bit
CNTE bit
TRG bit
T*
TIN pin
TOT pin
T : Machine cycle
* : It takes 1 machine cycle (time) to load data of reload register from trigger input.
262
CHAPTER 8 16-BIT RELOAD TIMER
8.5.2
Operation in Event Count Mode
In the event count mode, after the 16-bit reload timer is started, the edge of the signal
input to the TIN pin is detected to perform the count operation of the 16-bit timer
register (TMR). When the operation mode and the reload mode are set, a rectangular
wave or a toggle wave is output from the TOT pin.
■ Setting of Event Count Mode
• The 16-bit reload timer is placed in the event count mode by setting the count clock select bits in the
timer control status register (TMCSR: CSL1, CSL0) to "11B".
• In the event count mode, the TMR decrements in synchronization with the edge detection of the external
event clock input to the TIN pin.
[Setting initial value of counter]
After the 16-bit reload timer is started, the value set in the TMRLR is reloaded to the TMR.
1. Disables the operation of the 16-bit reload timer (TMCSR: CNTE = 0).
2. Sets a reload value to the TMR in the TMRLR.
3. Enables the operation of the 16-bit reload timer (TMCSR: CNTE = 1).
Note:
It takes 1 machine cycle (time) to load the value set in the TMRLR to the TMR after the start trigger
is input.
263
CHAPTER 8 16-BIT RELOAD TIMER
■ Operation as 16-bit Timer Register Underflows
When the value of the 16-bit timer register (TMR) is decremented from "0000H" to "FFFFH" during the
TMR count operation, an underflow occurs.
• When an underflow occurs, the underflow generation flag bit in the timer control status register
(TMCSR: UF) is set to "1".
• When the underflow interrupt enable bit in the timer control status register (TMCSR: INTE) is set to
"1", an underflow interrupt is generated.
• The reload operation when an underflow occurs is set by the reload select bit in the timer control status
register (TMCSR: RELD).
[One-shot mode (TMCSR: RELD = 0)]
When an underflow occurs, the TMR count operation is stopped, entering the start trigger input wait state.
When the next start trigger is input, the TMR count operation is restarted.
In the one-shot mode, a rectangular wave is output from the TOT pin during the TMR count operation. The
pin output level select bit in the timer control status register (TMCSR: OUTL) can be set to select the level
("H" or "L") of the rectangular wave.
[Reload mode (TMCSR: RELD = 1)]
When an underflow occurs, the value set in the TMRLR is reloaded to the TMR, continuing the TMR count
operation.
In the reload mode, a toggle wave inverting the output level of the TOT pin is output each time an
underflow occurs during the TMR count operation. The pin output level select bit in the timer control status
register (TMCSR: OUTL) can be set to select the level ("H" or "L") of the toggle wave when the 16-bit
reload timer is started.
264
CHAPTER 8 16-BIT RELOAD TIMER
■ Operation in Event Count Mode
The operation of the 16-bit reload timer is enabled by setting the timer operation enable bit in the timer
control status register (TMCSR: CNTE) to "1". When the software trigger bit in the timer control status
register (TMCSR: TRG) is set to "1", the 16-bit reload timer is started. When the 16-bit reload timer is
started, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR),
starting the TMR count operation. After the 16-bit reload timer is started, the edge of the external event
clock input to the TIN pin is detected to perform the TMR count operation.
• By setting the operation mode select bits in the timer control status register (TMCSR: MOD2 to
MOD0), the detected edge can be selected from the rising edge, falling edge, and both edges.
Note:
The level width of external event clock to be input to the TIN pin should be 4 machine cycles (time)
or more.
Figure 8.5-10 Count Operation in Event Count Mode (One-shot Mode)
TIN pin
Reload data
Counter
-1
0000H FFFFH
Reload data
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
T*
TOT pin
Start trigger input wait
T : Machine cycle
* : It takes 1 machine cycle (time) to load data of reload register from trigger input.
Figure 8.5-11 Count Operation in Event Count Mode (Reload Mode)
TIN pin
Reload data
Counter
-1
0000H Reload data
-1
0000H Reload data
-1
0000H Reload data
-1
Data load signal
UF bit
CNTE bit
TRG bit
T*
TOT pin
T : Machine cycle
* : It takes 1 machine cycle (time) to load data of reload register from trigger input.
265
CHAPTER 8 16-BIT RELOAD TIMER
8.6
Precautions when Using 16-bit Reload Timer
This section explains the precautions when using the 16-bit reload timer.
■ Precautions when Using 16-bit Reload Timer
● Precautions when setting by program
• Set the 16-bit reload register (TMRLR) after disabling the timer operation (TMCSR: CNTE = 0)
• The 16-bit timer register (TMR) can be read during the TMR count operation. However, always use the
word instruction (MOVW).
• Change the CSL1 and CSL0 bits in the TMCSR after disabling the timer operation (TMCSR: CNTE = 0).
● Precautions on interrupt
• When the UF bit in the TMCSR is set to "1" and the underflow interrupt output is enabled (TMCSR:
INTE = 1), it is impossible to return from interrupt processing. Always clear the UF bit. However, when
the EI2OS is used, the UF bit is cleared automatically.
• When using the EI2OS in the 16-bit reload timer, it is necessary to disable generation of interrupt
requests by resources that share the interrupt control register (ICR) with the 16-bit reload timer.
266
CHAPTER 8 16-BIT RELOAD TIMER
8.7
Program Example of 16-bit Reload Timer
This section gives a program example of the 16-bit reload timer operated in the internal
clock mode and the event count mode:
■ Program Example in Internal Clock Mode
● Processing specification
• The 25-ms interval timer interrupt is generated by the 16-bit reload timer 0.
• The repeated interrupts are generated in the reload mode.
• The timer is started using the software trigger instead of the external trigger input.
• EI2OS is not used.
• The machine clock is 16 MHz; the count clock is 2 μs.
267
CHAPTER 8 16-BIT RELOAD TIMER
● Coding example
ICR03
EQU 0000B3H
; Interrupt control register for 16-bit reload timer
TMCSR0 EQU 000066H
; Timer control status register
TMR0
EQU 003900H
; 16-bit timer register
TMRLR0 EQU 003900H
; 16-bit reload register
UF0
EQU TMCSR0:2
; Interrupt request flag bit
CNTE0
EQU TMCSR0:1
; Counter operation enable bit
TRG0
EQU TMCSR0:0
; Software trigger bit
;-----Main program--------------------------------------------------------------CODE
CSEG
;
:
; Stack pointer (SP), already initialized
AND CCR,#0BFH
; Interrupts disabled
MOV I:ICR03,#00H
; Interrupt level 0 (highest)
CLRB I:CNTE0
; Counter suspended
MOVW I:TMRLR0,#30D3H
; Data set for 25-ms timer
MOVW I:TMCSR0,#0000100000011011B
; Operation of interval timer, clock = 2 ms.
; External trigger disabled, external output disabled
; Reload mode selected, interrupt enabled
; Interrupt flag cleared, count started
MOV ILM,#07H
; ILM in PS set to level 7
OR
CCR,#40H
; Interrupts enabled
LOOP:
:
Processing by user
:
BRA LOOP
;-----Interrupt program---------------------------------------------------------WARI:
CLR I:UF0
; Interrupt request flag cleared
:
Processing by user
:
RETI
; Return from interrupt
CODE
ENDS
;-----Vector
VECT
CSEG
ORG
DSL
ORG
DSL
DB
VECT
ENDS
END
268
setting------------------------------------------------------------ABS=0FFH
00FFB8H
; Vector set to interrupt #17 (11H)
WARI
00FFDCH
; Reset vector set
START
00H
; Set to single-chip mode
START
CHAPTER 8 16-BIT RELOAD TIMER
■ Program Example in Event Count Mode
● Processing specification
• An interrupt is generated when rising edges of the pulse input to the external event input pin are counted
10000 times by the 16-bit reload timer 0.
• Operation is performed in the one-shot mode.
• The rising edge is selected for the external trigger input.
• EI2OS is not used.
269
CHAPTER 8 16-BIT RELOAD TIMER
● Coding example
ICR03
EQU 0000B3H
; Interrupt control register for 16-bit reload timer
TMCSR0 EQU 000066H
; Timer control status register
TMR0
EQU 003900H
; 16-bit timer register
TMRLR0 EQU 003900H
; 16-bit reload register
DDR2
EQU 000012H
; Port data register
UF0
EQU TMCSR0:2
; Interrupt request flag bit
CNTE0
EQU TMCSR0:1
; Counter operation enable bit
TRG0
EQU TMCSR0:0
; Software trigger bit
;-----Main program--------------------------------------------------------------CODE
CSEG
;
:
; Stack pointer (SP), already initialized
AND CCR,#0BFH
; Interrupts disabled
MOV I:ICR03,#00H
; Interrupt level 0 (highest)
MOV I:DDR2,00H
; Sets P20/TIN0 pin to input
CLRB I:CNTE0
; Counter suspended
MOVW I:TMRLR0,#2710H; Reload value set to 10000 times
MOVW I:TMCSR0,#0000110000001011B
; Counter operation, external trigger,
; rising edge, and external output disabled
; One-shot mode selected, interrupt enabled
; Interrupt flag cleared, count started
MOV
ILM,#07H
; ILM in PS set to level 7
OR
CCR,#40H
; Interrupts enabled
LOOP:
:
Processing by user
:
BRA
LOOP
;-----Interrupt program---------------------------------------------------------WARI:
CLR I:UF0
; Interrupt request flag cleared
:
Processing by user
:
RETI
; Return from interrupt
CODE
ENDS
;-----Vector
VECT
CSEG
ORG
DSL
ORG
DSL
DB
VECT
ENDS
END
270
setting------------------------------------------------------------ABS=0FFH
00FFB8H
; Vector set to interrupt #17 (11H)
WARI
00FFDCH
; Reset vector set
START
00H
; Set to single-chip mode
START
CHAPTER 9
WATCH TIMER
This section describes the functions and operations of
the watch timer.
9.1 Overview of Watch Timer
9.2 Block Diagram of Watch Timer
9.3 Configuration of Watch Timer
9.4 Watch Timer Interrupt
9.5 Explanation of Operation of Watch Timer
9.6 Program Example of Watch Timer
271
CHAPTER 9 WATCH TIMER
9.1
Overview of Watch Timer
The watch timer is a 15-bit free-run counter that increments in synchronization with the
subclock.
• 8 interval times can be selected and an interrupt request can be generated for each
interval time.
• An operation clock can be supplied to the oscillation stabilization wait time timer of
the subclock and the watchdog timer.
• The subclock is always used as a count clock regardless of the settings of the clock
select register (CKSCR).
■ Interval Timer Function
• When the watch timer reaches the interval time set by the interval time select bits (WTC: WTC2 to
WTC0), the bit corresponding to the interval time of the watch timer counter overflows (carries) and the
overflow flag bit is set (WTC: WTOF = 1).
• When the overflow flag bit is set (WTC: WTOF = 1) with interrupt enabled when an overflow occurs
(WTC: WTIE = 1), an interrupt request is generated.
• The interval time of the watch timer can be selected from 8 types shown in Table 9.1-1.
Table 9.1-1 Interval Times of Watch Timer
Subclock Cycle
Interval Time
28/SCLK (31.25 ms)
29/SCLK (62.5 ms)
210/SCLK (125 ms)
SCLK (122 μs)
211/SCLK (250 ms)
212/SCLK (500 ms)
213/SCLK (1.0 s)
214/SCLK (2.0 s)
215/SCLK (4.0 s)
SCLK: Subclock frequency
The parenthesized values are provided when the subclock operates at 8.192 kHz.
272
CHAPTER 9 WATCH TIMER
■ Cycle of Clock Supply
The watch timer supplies an operation clock to the oscillation stabilization wait time timer of the subclock
and the watchdog timer. Table 9.1-2 shows the cycles of clocks supplied from the watch timer.
Table 9.1-2 Cycle of Clock Supply from Watch Timer
Where to Supply Clock
Timer for oscillation stabilization wait time
of subclock
Clock Cycle
214/SCLK (2.000 s)
210/SCLK (125 ms)
213/SCLK (1.000 s)
Watchdog timer
214/SCLK (2.000 s)
215/SCLK (4.000 s)
SCLK: Subclock frequency
The parenthesized values are provided when the subclock operates at 8.192 kHz.
273
CHAPTER 9 WATCH TIMER
9.2
Block Diagram of Watch Timer
The watch timer consists of the following blocks:
• Watch timer counter
• Counter clear circuit
• Interval timer selector
• Watch timer control register (WTC)
■ Block Diagram of Watch Timer
Figure 9.2-1 Block Diagram of Watch Timer
To watchdog
timer
Watch timer counter
SCLK
× 21 × 22 × 23 × 24 × 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215
OF OF OF
OF
Power on reset
Transits to hardware standby
Transits to stop mode
OF
Counter
clear circuit
OF
OF OF
To subclock oscillation
stabilization wait time
Interval timer
selector
Watch timer interrupt
OF
: Overflow
SCLK : Subclock
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
Watch timer control register (WTC)
The actual interrupt request number of the watch timer is #28 (1CH).
● Watch timer counter
The watch timer counter is a 15-bit up counter that uses the subclock (SCLK) as a count clock.
● Counter clear circuit
The counter-clear circuit clears the watch timer counter.
274
CHAPTER 9 WATCH TIMER
● Interval timer selector
The interval timer selector sets the overflow flag bit when the watch timer counter reaches the interval time
set in the watch timer control register (WTC).
● Watch timer control register (WTC)
The watch timer control register (WTC) selects the interval time, clears the watch timer counter, enables or
disables an interrupt, checks the overflow (carries) state, and clears the overflow flag bit.
275
CHAPTER 9 WATCH TIMER
9.3
Configuration of Watch Timer
This section explains the registers and interrupt factors of the watch timer.
■ List of Registers and Reset Values of Watch Timer
Figure 9.3-1 List of Registers and Reset Values of Watch Timer
bit
Watch timer control register
WTC
7
6
5
4
3
2
1
0
1
X
0
0
0
0
0
0
X: Undefined
■ Generation of Interrupt Request from Watch Timer
• When the interval time set by the interval time select bits (WTC: WTC2 to WTC0) is reached, the
overflow flag bit (WTC: WTOF) is set to "1".
• When the overflow flag bit is set (WTC: WTOF = 1) with interrupt enabled when the watch timer
counter overflows (carries) (WTC: WTIE = 1), an interrupt request is generated.
276
CHAPTER 9 WATCH TIMER
9.3.1
Watch Timer Control Register (WTC)
This section explains the functions of the watch timer control register (WTC).
■ Watch Timer Control Register (WTC)
Figure 9.3-2 Watch Timer Control Register (WTC)
Address:
0000AAH
7
6
5
4
3
2
1
0
Reset value
1X001000B
R/W
R
R/W R/W R/W R/W R/W R/W
bit 2 bit 1 bit 0
WTC2 WTC1 WTC0
Interval time select bits
0
0
0
28/SCLK (31.25ms)
0
0
1
29/SCLK (62.5ms)
0
1
0
210/SCLK (125ms)
0
1
1
211/SCLK (250ms)
1
0
0
212/SCLK (500ms)
1
0
1
213/SCLK (1.0s)
1
1
0
214/SCLK (2.0s)
1
1
1
215/SCLK (4.0s)
bit 3
WTR
0
1
Watch timer clear bit
Read
Write
⎯
Clears watch timer counter
"1" always read
No effect
bit 4
WTOF
Overflow flag bit
Read
Write
0
No overflow of the bit
corresponding to set interval time
Clears WTOF bit
1
Overflow of the bit corresponding
to set interval time
No effect
bit 5
Overflow interrupt enable bit
WTIE
Interrupt request disable
0
Interrupt request enable
1
bit 6
Oscillation stabilization wait time end bit
SCE
Oscillation stabilization wait state
0
Oscillation stabilization wait time end
1
bit 7
WDCS
Watchdog clock select bit
(input clock of watchdog timer)
R/W : Read/Write
Main or PLL clock mode
Subclock mode
R
: Read only
Watch timer
Set "0"
0
X
: Undefined
1
Timebase timer
SCLK : Subclock
: Reset value
The parenthesized values are provided when subclock operates at 8.192 kHz.
277
CHAPTER 9 WATCH TIMER
Table 9.3-1 Functions of Watch Timer Control Register (WTC)
Bit Name
bit 7
WDCS:
Watchdog clock select
bit
This bit selects the operation clock of the watchdog timer.
<Main clock mode or PLL clock mode>
When set to "0":Selects output of watch timer as operation clock of watchdog
timer.
When set to "1":Selects output of timebase timer as operation clock of
watchdog timer.
<Subclock mode>
Always set this bit to "0" to select the output of the watch timer.
Note: The watch timer and the timebase timer operate asynchronously. When
the WDCS bit is changed from "0" to "1", the watchdog timer may run
fast. The watchdog timer must be cleared before and after changing the
WDCS bit.
bit 6
SCE:
Oscillation stabilization
wait time end bit
This bit indicates that the oscillation stabilization wait time of the subclock ends.
When cleared to "0": Subclock in oscillation stabilization wait state
When set to "1": Subclock oscillation stabilization wait time ends
• The oscillation stabilization wait time of the subclock is fixed at 214/SCLK
(SCLK: subclock frequency).
bit 5
WTIE:
Overflow interrupt
enable bit
This bit enables or disables generation of an interrupt request when the watch
timer counter overflows (carries).
When set to "0": Interrupt request not generated even at overflow (WTOF = 1)
When set to "1": Interrupt request generated at overflow (WTOF = 1)
bit 4
WTOF:
Overflow flag bit
This bit is set to "1" when the counter value of the watch timer reaches the value
set by the interval time select bit.
When an overflow (carries) occurs (WTOF = 1) with interrupt request enabled
(WTIE = 1), an interrupt request is generated.
When set to "0": Clears this bit
When set to "1": No effect
• The overflow flag bit is set to "1" when the bit of the watch timer counter
corresponding to the interval time set by the interval time select bits (WTC2
to WTC0) overflows (carries).
bit 3
WTR:
Watch timer clear bit
This bit clears the watch timer counter.
When set to "0": Clears watch timer counter to "0000H"
When set to "1": No effect
Read: "1" is always read.
WTC2, WTC1, WTC0:
Interval time select bits
These bits set the interval time of the watch timer.
• When the interval time set by the WTC2 to WTC0 bits is reached, the
corresponding bit of the watch timer counter overflows (carries) and the
overflow flag bit is set (WTC: WTOF = 1).
• To set the WTC2 to WTC0 bits, set the WTOF bit to "0".
bit 2 to
bit 0
278
Function
CHAPTER 9 WATCH TIMER
9.4
Watch Timer Interrupt
When the interval time is reached with the watch timer interrupt enabled, the overflow
flag bit is set to "1" and an interrupt request is generated.
■ Watch Timer Interrupt
Table 9.4-1 shows the interrupt control bits and interrupt factors of the watch timer.
Table 9.4-1 Interrupt Control Bits of Watch Timer
Watch Timer
Interrupt factor
Interval time of watch timer counter
Interrupt request flag bit
WTC: WTOF (overflow flag bit)
Interrupt factor enable bit
WTC: WTIE
• When the value set by the interval time select bits (WTC2 to WTC0) in the watch timer control register
(WTC) is reached, the overflow flag bit in the WTC register is set to "1" (WTC: WTOF = 1).
• When the overflow flag bit is set (WTC: WTOF = 1) with the watch timer interrupt enabled (WTC:
WTIE = 1), an interrupt request is generated.
• At interrupt processing, set the WTOF bit to "0" and cancel the interrupt request.
■ Watch Timer Interrupt and EI2OS Function
• The watch timer does not correspond to the EI2OS function.
• For details of the interrupt number, interrupt control register, and interrupt vector address, see Section
"3.5 Interrupt".
279
CHAPTER 9 WATCH TIMER
9.5
Explanation of Operation of Watch Timer
The watch timer operates as an interval timer or an oscillation stabilization wait time
timer of subclock. It also supplies an operation clock to the watchdog timer.
■ Watch Timer Counter
The watch timer counter continues incrementing in synchronization with the subclock (SCLK) while the
subclock (SCLK) is operating.
● Clearing watch timer counter
The watch timer counter is cleared to "0000H" when:
• A power-on reset occurs.
• The mode transits to the stop mode.
• The watch timer clear bit (WTR) in the watch timer control register (WTC) is set to "0".
Note:
When the watch timer counter is cleared, the interrupts of the watchdog timer and interval timer that
use the output of the watch timer counter are affected.
To clear the watch timer by writing zero to the watch timer clear bit (WTR) in the watch timer control
register (WTC), set the overflow interrupt enable bit (WTIE) to "0" and set the watch timer to interrupt
inhibited state. Before permitting an interrupt, clear the interrupt request issued by writing zero to the
overflow flag bit (WTOF) in the WTC register.
■ Interval Timer Function
The watch timer can be used as an interval timer by generating an interrupt at each interval time.
● Settings when using watch timer as interval timer
Operating the watch timer as an interval timer requires the settings shown in Figure 9.5-1.
Figure 9.5-1 Setting of Watch Timer
WTC
bit7
WDCS
X
6
SCE
X
5
WTIE
4
WTOF
3
WTR
2
WTC2
1
WTC1
bit0
WTC0
: Used bit
X : Undefined
• When the value set by the interval time select bits (WTC1, WTC0) in the watch timer control register
(WTC) is reached, the overflow flag bit in the WTC register is set to "1" (WTC: WTOF = 1).
• When the overflow flag bit is set (WTC: WTOF = 1) with the overflow interrupt of the watch timer
counter enabled (WTC: WTIE = 1), an interrupt request is generated.
• The overflow flag bit (WTC: WTOF) is set when the interval time is reached at the starting point of the
timing at which the watch timer is finally cleared.
280
CHAPTER 9 WATCH TIMER
● Clearing overflow flag bit (WTC: WTOF)
When the mode is switched to the stop mode, the watch timer is used as an oscillation stabilization wait
time timer of subclock. The WTOF bit is cleared concurrently with mode switching.
■ Setting Operation Clock of Watchdog Timer
The watchdog clock select bit (WDCS) in the watch timer control register (WTC) can be used to set the
clock input source of the watchdog timer.
When using the subclock as the machine clock, always set the WDCS bit to "0" and select the output of the
watch timer.
■ Oscillation Stabilization Wait Time Timer of Subclock
When the watch timer returns from the power-on reset and the stop mode, it functions as an oscillation
stabilization wait time timer of subclock.
• The subclock oscillation stabilization wait time is fixed at 214/SCLK (SCLK: subclock frequency).
281
CHAPTER 9 WATCH TIMER
9.6
Program Example of Watch Timer
This section gives a program example of the watch timer.
■ Program Example of Watch Timer
● Processing specifications
An interval interrupt at 213/SCLK (SCLK: subclock) is generated repeatedly. The interval time is
approximately 1.0s (when subclock operates at 8.192 kHz).
● Coding example
ICR07
EQU 0000B7H
; Interrupt control register
WTC
EQU 0000AAH
; Watch timer control register
WTOF
EQU WTC:4
; Overflow flag bit
;
;-----Main program--------------------------------------------------------------CODE
CSEG
START:
;
:
; Stack pointer (SP) already initialized
AND CCR,#0BFH
; Interrupt disabled
MOV I:ICR07,#00H
; Interrupt level 0 (highest)
MOV I:WTC, #10100101B ; Interrupt enabled
; Overflow flag bit cleared
; Watch timer counter cleared
; 213/SCLK (approx. 1.0 s)
MOV ILM,#07H
; ILM in PS set to level 7
OR
CCR,#40H
; Interrupt enabled
LOOP:
.
Processing by user
.
BRA
LOOP
;-----Interrupt program---------------------------------------------------------WARI:
CLRB I:WTOF
; Overflow flag cleared
.
Processing by user
.
RETI
; Return from interrupt processing
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG 00FF8CH
; Vector set to interrupt #28 (1CH)
DSL WARI
ORG 00FFDCH
; Reset vector set
DSL START
DB
00H
; Set to single-chip mode
VECT
ENDS
END START
282
CHAPTER 10
8-/16-BIT PPG TIMER
This section describes the functions and operations of
the 8-/16-bit PPG timer.
10.1 Overview of 8-/16-bit PPG Timer
10.2 Block Diagram of 8-/16-bit PPG Timer
10.3 Configuration of 8-/16-bit PPG Timer
10.4 Interrupts of 8-/16-bit PPG Timer
10.5 Explanation of Operation of 8-/16-bit PPG Timer
10.6 Precautions when Using 8-/16-bit PPG Timer
283
CHAPTER 10 8-/16-BIT PPG TIMER
10.1
Overview of 8-/16-bit PPG Timer
The 8-/16-bit PPG timer is a reload timer module with two channels (PPG0 and PPG1)
that outputs a pulse in any cycle and at any duty ratio. A combination of two channels
provides:
• 8-bit PPG output 2-channel independent operation mode
• 16-bit PPG output operation mode
• 8 + 8-bit PPG output operation mode
The MB90385 series has two 8-/16-bit PPG timers. This section explains the functions of
PPG0/1. PPG2/3 has the same functions as PPG0/1.
■ Functions of 8-/16-bit PPG Timer
The 8-/16-bit PPG timer consists of four 8-bit reload registers (PRLH0, PRLL0, PRLH1, and PRLL1) and
two PPG down counters (PCNT0 and PCNT1).
• Individual setting of High and Low widths in output pulse enables an output pulse of any cycle and duty
ratio.
• The count clock can be selected from six internal clocks.
• The 8-/16-bit PPG timer can be used as an interval timer by generating an interrupt request at each
interval time.
• An external circuit enables the 8-/16-bit PPG timer to be used as a D/A converter.
■ Operation Modes of 8-/16-bit PPG Timer
● 8-bit PPG output 2-channel independent operation mode
The 8-bit PPG output 2-channel independent operation mode causes the 2-channel modules (PPG0 and
PPG1) to operate as each independent 8-bit PPG timer.
Table 10.1-1 shows the interval times in the 8-bit PPG output 2-channel independent operation mode.
284
CHAPTER 10 8-/16-BIT PPG TIMER
Table 10.1-1 Interval Times in 8-bit PPG Output 2-channel Independent Operation Mode
PPG0, PPG1
Count Clock Cycle
Interval Time
Output Pulse Time
1/φ (62.5 ns)
1/φ to 28/φ
2/φ to 29/φ
2/φ (125 ns)
2/φ to 29/φ
22/φ to 210/φ
22/φ (250 ns)
22/φ to 210/φ
23/φ to 211/φ
23/φ (500 ns)
23/φ to 211/φ
24/φ to 212/φ
24/φ (1 μs)
24/φ to 212/φ
25/φ to 213/φ
29/HCLK to 217/HCLK
210/HCLK to 218/HCLK
29/HCLK (128 μs)
HCLK: Oscillation clock
φ: Machine clock frequency
The parenthesized values are provided when the oscillation clock operates at 4 MHz and the machine
clock operates at 16 MHz.
● 16-bit PPG output operation mode
The 16-bit PPG output operation mode concatenates the 2-channel modules (PPG0 and PPG1) to operate as
a 16-bit 1-channel PPG timer.
Table 10.1-2 shows the interval times in this mode.
Table 10.1-2 Interval Times in 16-bit PPG Output Operation Mode
Count clock cycle
Interval time
Output pulse time
1/φ (62.5 ns)
1/φ to 216/ φ
2/φ to 217/φ
2/φ (125 ns)
2/φ to 217/φ
22/φ to 218/φ
22/φ (250 ns)
22/φ to 218/φ
23/φ to 219/φ
23/φ (500 ns)
23/φ to 219/φ
24/φ to 220/φ
24/φ (1 μs)
24/φ to 220/φ
25/φ to 221/φ
29/HCLK to 225/HCLK
210/HCLK to 226/HCLK
29/HCLK (128 μs)
HCLK: Oscillation clock
φ: Machine clock frequency
The parenthesized values are provided when the oscillation clock operates at 4 MHz and the machine
clock operates at 16 MHz.
285
CHAPTER 10 8-/16-BIT PPG TIMER
● 8 + 8-bit PPG output operation mode
The 8 + 8-bit PPG output operation mode causes the PPG0 of the 2-channel modules (PPG0 and PPG1) to
operate as an 8-bit prescaler and the underflow output of the PPG0 to operate as the count clock of the
PPG1.
Table 10.1-3 shows the interval times in this mode.
Table 10.1-3 Interval Times in 8+8-bit PPG Output Operation Mode
PPG0
Count
Clock Cycle
PPG1
Interval
Time
Output Pulse
Time
Interval
Time
Output Pulse
Time
1/φ (62.5 ns)
1/φ to 28/φ
2/φ to 29/φ
1/φ to 216/φ
2/φ to 217/φ
2/φ (125 ns)
2/φ to 29/φ
22/φ to 210/φ
2/φ to 217/φ
22/φ to 218/φ
22/φ (250 ns)
22/φ to 210/φ
23/φ to 211/φ
22/φ to 218/φ
23/φ to 219/φ
23/φ (500 ns)
23/φ to 211/φ
24/φ to 212/φ
23/φ to 219/φ
24/φ to 220/φ
24/φ (1 μs)
24/φ to 212/φ
25/φ to 213/φ
24/φ to 220/φ
25/φ to 221/φ
29/HCLK (128 μs)
29/HCLK to
217/HCLK
210/HCLK to
218/HCLK
29/HCLK to
225/HCLK
210/HCLK to
226/HCLK
HCLK: Oscillation clock
φ: Machine clock frequency
The parenthesized values are provided when the oscillation clock operates at 4 MHz and the machine
clock operates at 16 MHz.
286
CHAPTER 10 8-/16-BIT PPG TIMER
10.2
Block Diagram of 8-/16-bit PPG Timer
The MB90385 series contains two 8/16-bit PPG timer (each with two channels).
One 8-/16-bit PPG timer consists of 8-bit PPG timers with two channels.
This section shows the block diagrams for the 8-/16-bit PPG timer 0 and 8-/16-bit PPG
timer 1.
The PPG2 has the same function as the PPG0, and PPG3 has the same function as
PPG1.
■ Channels and PPG Pins of PPG Timers
Figure 10.2-1 shows the relationship between the channels and the PPG pins of the 8-/16-bit PPG timers in
the MB90385 series.
Figure 10.2-1 Channels and PPG Pins of PPG Timers
PPG0/1
Pin
PPG0 output pin
Pin
PPG1 output pin
PPG2/3
Pin
PPG2 output pin
Pin
PPG3 output pin
287
CHAPTER 10 8-/16-BIT PPG TIMER
10.2.1
Block Diagram for 8-/16-bit PPG Timer 0
The 8-/16-bit PPG timer 0 consists of the following blocks.
■ Block Diagram of 8-/16-bit PPG Timer 0
Figure 10.2-2 Block Diagram of 8-/16-bit PPG Timer 0
"H" level side data bus
"L" level side data bus
PPG0 reload
register
PRLH0
("H" level side)
PPG0 operation mode control register (PPGC0)
PRLL0
("L" level side)
PEN0
⎯
PE0 PIE0 PUF0
PPG0 temporary
buffer 0 (PRLBH0)
⎯
⎯
Interrupt
request output*
R
S
Q
2
Select signal
Reload register
L/H selector
Count start value
Reserved
Reload
PPG0 down counter
(PCNT0)
Clear
Operation mode
control signal
PPG1 underflow
PPG0 underflow
(to PPG1)
Pulse selector
Underflow
CLK
PPG0
Invert output latch
Pin
PPG0
PPG output control circuit
Timebase timer output
(512/HCLK)
Count clock
selector
3
Select signal
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
⎯
PPG0/1 count clock select register (PPG01)
288
⎯
CHAPTER 10 8-/16-BIT PPG TIMER
● Details of pins in block diagram
Table 10.2-1 lists the actual pin names and interrupt request numbers of the 8-/16-bit PPG timer.
Table 10.2-1 Pins and Interrupt Request Numbers in Block Diagram
Channel
Output Pin
PPG0
P14/PPG0
PPG1
P15/PPG1
PPG2
P16/PPG2
PPG3
P17/PPG3
Interrupt Request Number
#22 (16H)
#26 (1AH)
● PPG operation mode control register 0 (PPGC0)
This register enables or disables operation of the 8-/16-bit PPG timer 0, the pin output, and an underflow
interrupt. It also indicates the occurrence of an underflow.
● PPG0/1 count clock select register (PPG01)
This register sets the count clock of the 8-/16-bit PPG timer 0.
● PPG0 reload registers (PRLH0 and PRLL0)
These registers set the "H" width or "L" width of the output pulse. The values set in these registers are
reloaded to the PPG0 down counter (PCNT0) when the 8-/16-bit PPG timer 0 is started.
● PPG0 down counter (PCNT0)
This counter is an 8-bit down counter that alternately reloads the values set in the PPG0 reload registers
(PRLH0 and PRLL0) to decrement. When an underflow occurs, the pin output is inverted. This counter is
concatenated for use as a single-channel 16-bit PPG down counter.
● PPG0 temporary buffer (PRLBH0)
This buffer prevents deviation of the output pulse width caused at writing to the PPG reload registers
(PRLH0 and PRLL0). This buffer stores the PRLH0 value temporarily and enables it in synchronization
with the timing of writing to the PRLL0.
● Reload register L/H selector
This selector detects the current pin output level to select which register value, Low reload register
(PRLL0) or High reload register (PRLH0), should be reloaded to the PPG0 down counter.
● Count clock selector
This selector selects the count clock to be input to the PPG0 down counter from five frequency-divided
clocks of the machine clock or the frequency-divided clocks of the timebase timer.
● PPG output control circuit
This circuit inverts the pin output level and the output when an underflow occurs.
289
CHAPTER 10 8-/16-BIT PPG TIMER
10.2.2
Block Diagram of 8-/16-bit PPG Timer 1
The 8-/16-bit PPG timer 1 consists of the following blocks.
■ Block Diagram of 8-/16-bit PPG Timer 1
Figure 10.2-3 Block Diagram of 8-/16-bit PPG Timer 1
"H" level side data bus
"L" level side data bus
PPG1 operation mode control register (PPGC1)
PPG1 reload
register
PRLH1
("H" side)
PRLL1
("L" side)
PEN1
⎯
PE1 PIE1 PUF1 MD1 MD0
2
Operation mode
control signal
S
Reload register
L/H selector
Count start value
PPG0 underflow
(from PPG0)
Q
Select signal
Reload
PPG1 down counter
(PCNT1)
PPG1 underflow
(to PPG0)
Interrupt
request output*
R
PPG1 temporary
buffer (PRLBH1)
Clear
Underflow
PPG1
Invert output latch
Pin
PPG1
CLK
PPG output control circuit
MD0
Timebase timer output
(512/HCLK)
Count clock
selector
3
Select signal
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
⎯
PPG0/1 count clock select register (PPG01)
290
Reserved
⎯
CHAPTER 10 8-/16-BIT PPG TIMER
● Details of pins in block diagram
Table 10.2-2 lists the actual pin names and interrupt request numbers of the 8-/16-bit PPG timer.
Table 10.2-2 Pins and Interrupt Request Numbers in Block Diagram
Channel
Output Pin
PPG0
P14/PPG0
PPG1
P15/PPG1
PPG2
P16/PPG2
PPG3
P17/PPG3
Interrupt Request Number
#22 (16H)
#26 (1AH)
● PPG operation mode control register 1 (PPGC1)
This register sets the operation mode of the 8-/16-bit PPG timer, enables or disables the operation of the 8-/
16-bit PPG timer 1, the pin output and an underflow interrupt, and also indicates the generation of an
underflow.
● PPG2/3 count clock select register (PPG23)
This register sets the count clock of the 8-/16-bit PPG timer 1.
● PPG1 reload registers (PRLH1 and PRLL1)
These registers set the "H" width or "L" width of the output pulse. The values set in these registers are
reloaded to the PPG1 down counter (PCNT1) when the 8-/16-bit PPG timer 1 is started.
● PPG1 down counter (PCNT1)
This counter is an 8-bit down counter that alternately reloads the values set in the PPG1 reload registers
(PRLH1 and PRLL1) to decrement. When an underflow occurs, the pin output is inverted. The 2-channel
PPG down counters (PPG0 and PPG1) can also be connected for use as a single-channel 16-bit PPG down
counter.
● PPG1 temporary buffer (PRLBH1)
This buffer prevents deviation of the output pulse width caused at writing to the PPG reload registers
(PRLH1 and PRLL1). It stores the PRLH1 value temporarily and enables it in synchronization with the
timing of writing to the PRLL1.
● Reload register L/H selector
This selector detects the current pin output level to select which register value, Low reload register
(PRLL1) or High reload register (PRLH1), should be reloaded to the PPG1 down counter.
● Count clock selector
This selector selects the count clock to be input to the PPG1 down counter from five frequency-divided
clocks of the machine clock or the frequency-divided clocks of the timebase timer.
● PPG output control circuit
This circuit inverts the pin output level and the output when an underflow occurs.
291
CHAPTER 10 8-/16-BIT PPG TIMER
10.3
Configuration of 8-/16-bit PPG Timer
This section explains the pins, registers and interrupt factors of the 8-/16-bit PPG timer.
■ Pins of 8-/16-bit PPG Timer
The pins of the 8-/16-bit PPG timer serve as general-purpose I/O ports. Table 10.3-1 indicates the pin
functions and pin settings required to use the 8-/16-bit PPG timer.
Table 10.3-1 Pins of 8-/16-bit PPG Timer
Pin Function
Pin Name
PPG0
PPG0 output pin
General-purpose I/O port,
PPG0 output pin
Set PPG0 pin output to "enabled"
(PPGC0: PE=1)
PPG1
PPG1 output pin
General-purpose I/O port,
PPG1 output pin
Set PPG1 pin output to "enabled"
(PPGC1: PE1=1)
PPG2
PPG2 output pin
General-purpose I/O port,
PPG2 output pin
Set PPG2 pin output to "enabled"
(PPGC2: PE0=1)
PPG3
PPG3 output pin
General-purpose I/O port,
PPG3 output pin
Set PPG3 pin output to "enabled"
(PPGC3: PE1=1)
■ Block Diagram of 8-/16-bit PPG Timer Pins
See "CHAPTER 4 I/O PORT" for the pin block diagram.
292
Pin Setting Required for Use of
8-/16-bit PPG Timer
Channel
CHAPTER 10 8-/16-BIT PPG TIMER
■ List of Registers and Reset Values of 8-/16-bit PPG Timer
Figure 10.3-1 List of Registers and Reset Values of 8-/16-bit PPG Timer
bit
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
bit
7
6
5
4
3
2
1
0
PPG0 OPERATION MODE CONTROL REGISTER: L
(PPGC0)
0
0
0
0
0
0
0
0
bit
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
PPG0 operation mode control register: H
(PPGC1)
PPG0/1 COUNT CLOCK SELECT REGISTER
(PPG01)
bit
PPG0 reload register: H (PRLH0)
bit
PPG0 reload register: L (PRLL0)
bit
PPG1 reload register: H (PRLH1)
bit
PPG1 reload register: L (PRLL1)
X: Undefined
■ Generation of Interrupt Request from 8-/16-bit PPG Timer
In the 8-/16-bit PPG timer, the underflow generation flag bits in the PPG operation mode control registers
(PPGC0:PUF0, PPGC1:PUF1) are set to "1" when an underflow occurs. If the underflow interrupts of
channels causing an underflow are enabled (PPGC0:PIE0=1, PPGC1:PIE1=1), an underflow interrupt
request is generated to the interrupt controller.
293
CHAPTER 10 8-/16-BIT PPG TIMER
10.3.1
PPG0 Operation Mode Control Register (PPGC0)
The PPG0 operation mode control register (PPGC0) provides the following settings:
• Enabling or disabling operation of 8-/16-bit PPG timer
• Switching between pin functions (enabling or disabling pulse output)
• Enabling or disabling underflow interrupt
• Setting underflow interrupt request flag
■ PPG0 Operation Mode Control Register (PPGC0)
Figure 10.3-2 PPG0 Operation Mode Control Register (PPGC0)
Address:
000040H
7
6
5
4
3
2
1
0
Reset value
0X000XX1B
R/W ⎯ R/W R/W R/W ⎯
⎯
W
bit 0
Reserved bit
Reserved
1
Always set to "1"
bit 3
PUF0
0
1
R/W : Read/Write
X
: Undefined
⎯
: Unused
: Reset value
294
Underflow generation flag bit
Read
No underflow
Underflow
Write
Clears PUF0 bit
No effect
bit 4
PIE0
0
1
Interrupt request disable
Interrupt request enable
bit 5
PE0
0
1
General-purpose I/O port (pulse output disable)
PPG0 output (pulse output enable)
Underflow interrupt enable bit
PPG0 pin output enable bit
bit 7
PEN0
PPG0 operation enable bit
0
Counting disable (holds "L" level output)
1
Counting enable
CHAPTER 10 8-/16-BIT PPG TIMER
Table 10.3-2 Functions of PPG0 Operation Mode Control Register (PPGC0)
Bit Name
Function
bit 7
PEN0:
PPG0 operation enable
bit
This bit enables or disables the count operation of the 8-/16-bit PPG timer 0.
When set to "0": Count operation disabled
When set to "1": Count operation enabled
• When the count operation is disabled (PEN0 = 0), the output is held at a "L"
level.
bit 6
Unused bit
Read: The value is undefined.
Write: No effect
bit 5
PE0:
PPG0 pin output enable
bit
This bit switches between PPG0 pin functions and enables or disables the pulse
output.
When set to "0":PPG0 pin functions as general-purpose I/O port.
The pulse output is disabled.
When set to "1":PPG0 pin functions as PPG0 output pin.
The pulse output is enabled.
bit 4
PIE0:
Underflow interrupt
enable bit
This bit enables or disables an interrupt.
When set to "0": No interrupt request generated even at underflow (PUF0 = 1).
When set to "1": Interrupt request generated at underflow (PUF0 = 1)
bit 3
PUF0:
Underflow generation
flag bit
8-bit PPG output 2-channel independent operation mode, 8+8-bit PPG
output operation mode: When the value of the PPG0 down counter is
decremented from "00H" to "FFH", an underflow
occurs (PUF0 = 1).
16-bit PPG output operation mode:
When the values of the PPG0 and PPG1 down
counters are decremented from "0000H" to" FFFFH",
an underflow occurs (PUF0 = 1).
• When an underflow occurs (PUF0 = 1) with an underflow interrupt enabled
(PIE0 = 1), an interrupt request is generated.
When set to "0": Clears this bit
When set to "1": No effect
Read by read modify write (RMW) instructions: "1" is read.
bit 2,
bit 1
Unused bits
Read: The value is undefined.
Write: No effect
bit 0
Reserved: Reserved bit
Always set this bit to "1".
295
CHAPTER 10 8-/16-BIT PPG TIMER
10.3.2
PPG1 Operation Mode Control Register (PPGC1)
The PPG1 operation mode control register (PPGC1) provides the following settings:
• Enabling or disabling operation of 8-/16-bit PPG timer
• Switching between pin functions (enabling or disabling pulse output)
• Enabling or disabling underflow interrupt
• Setting underflow interrupt request flag
• Setting the operation mode of the 8-/16-bit PPG timer
■ PPG1 Operation Mode Control Register (PPGC1)
Figure 10.3-3 PPG1 Operation Mode Control Register (PPGC1)
Address:
000041H
15
14
13
12
11
10
9
8
Reset value
0X000001
R/W ⎯ R/W R/W R/W R/W R/W
B
W
bit 8
Reserved bit
Reserved
1
Always set to "1"
bit 10 bit 9
MD1 MD0
0
0
0
1
1
0
1
1
Operation mode select bits
8-bit PPG output 2-ch independent operation mode
8 + 8-bit PPG output operation mode
Setting disable
16-bit PPG output operation mode
bit 11
PUF1
0
1
Underflow generation flag bit
Read
No underflow
Underflow
Write
Clears PUF1 bit
No effect
bit 12
Underflow interrupt enable bit
PIE1
0
Underflow interrupt request disable
1
Underflow interrupt request enable
bit 13
PPG1 pin output enable bit
PE1
0
General-purpose I/O port (pulse output disable)
1
PPG1 output (pulse output enable)
R/W : Read/Write
X
: Undefined
⎯
: Unused
: Reset value
296
bit 15
PPG1 operation enable bit
PEN1
Counting disable (holds "L" level output)
0
Counting enable
1
CHAPTER 10 8-/16-BIT PPG TIMER
Table 10.3-3 Functions of PPG1 Operation Mode Control Register (PPGC1)
Bit Name
Function
bit 15
PEN1:
PPG1 operation enable
bit
This bit enables or disables the count operation of the 8-/16-bit PPG timer 1.
When set to "0": Count operation disabled
When set to "1": Count operation enabled
• When the count operation is disabled (PEN1 = 0), the output is held at a "L"
level.
bit 14
Unused bit
Read: The value is undefined.
Write: No effect
bit 13
PE1:
PPG1 Pin output enable
bit
This bit switches between PPG1 pin functions and enables or disables the pulse
output.
When set to"0":PPG1 pin functions as general-purpose I/O port. The pulse
output is disabled.
When set to "1":PPG1 pin functions as PPG1 output pin. The pulse output is
enabled.
bit 12
PIE1:
Underflow interrupt
enable bit
This bit enables or disables an interrupt.
When set to "0": No interrupt request is generated even at underflow
(PUF1 = 1)
When set to "10": Interrupt request is generated at underflow (PUF1 = 1)
bit 11
PUF1:
Underflow generation
flag bit
8-bit PPG output 2-channel independent operation mode, 8+8-bit PPG
output operation mode: When the value of the PPG1 down counter is
decremented from "00H" to "FFH", an underflow
occurs (PUF1 = 1).
16-bit PPG output operation mode:
When the values of the PPG0 and PPG1 down
counters are decremented from "0000H" to "FFFF H",
an underflow occurs (PUF1 = 1).
• When an underflow occurs (PUF1 = 1) with an underflow interrupt enabled
(PIE1 = 1), an interrupt request is generated.
When set to "0": Clears this bit
When set to "1": No effect
Read by read modify write instructions: "1" is read.
bit 10,
bit 9
MD1, MD0:
Operation mode select
bits
These bits set the operation mode of the 8-/16-bit PPG timer.
[Any mode other than 8-bit PPG output 2-channel independent operation
mode]
• Use a word instruction to set the PPG operation enable bits (PEN0 and PEN1)
at one time.
• Do not set operation of only one of the two channels (PEN1 = 0/PEN0 = 1 or
PEN1 = 1/PEN0 = 0).
Note: Do not set the MD1 and MD0 bits to "10B".
Reserved:
Reserved bit
Always set this bit to "1".
bit 8
297
CHAPTER 10 8-/16-BIT PPG TIMER
10.3.3
PPG0/1 Count Clock Select Register (PPG01)
The PPG0/1 count clock select register (PPG01) selects the count clock of the 8-/16-bit
PPG timer.
■ PPG0/1 Count Clock Select Register (PPG01)
Figure 10.3-4 PPG0/1 Count Clock Select Register (PPG01)
Address:
000042H
7
6
5
4
3
2
1
0
Reset value
000000XX
R/W R/W R/W R/W R/W R/W ⎯
bit 4 bit 3 bit 2
PCM2 PCM1 PCM0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
R/W
X
⎯
:
:
:
:
HCLK :
φ
:
Read/Write
Undefined
Unused
Reset value
Oscillation clock
Machine clock frequency
B
⎯
bit 7 bit 6 bit 5
PCS2 PCS1 PCS0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
0
1
1
1
0
1
1
1
1
PPG0 count clock select bits
1/φ (62.5 ns)
2/φ (125 ns)
22/φ (250 ns)
23/φ (500 ns)
24/φ (1 μs)
Setting disable
Setting disable
29/HCLK (128 μs)
PPG1 count clock select bits
1/φ (62.5 ns)
2/φ (125ns)
22/φ (250 ns)
23/φ (500 ns)
24/φ (1 μs)
Setting disable
Setting disable
29/HCLK (128 μs)
The parenthesized values are provided when the oscillation clock operates at 4 MHz and
the machine clock operates at 16 MHz.
298
CHAPTER 10 8-/16-BIT PPG TIMER
Table 10.3-4 Functions of PPG0/1 Count Clock Select Register (PPG01)
Bit Name
Function
bit 7 to bit 5
PCS2 to PCS0:
PPG1 count clock select
bits
These bits set the count clock of the 8-/16-bit PPG timer 1.
• The count clock can be selected from five frequency-divided clocks of the
machine clock and the frequency-divided clocks of the timebase timer.
• The settings of the PPG1 count clock select bits (PCS2 to PCS0) are
enabled only in the 8-bit PPG output 2-channel independent mode
(PPGC1: MD1, MD0 = 00B).
bit 4 to bit 2
PCM2 to PCM0:
PPG0 count clock select
bit
These bits set the count clock of the 8-/16-bit PPG timer 0.
• The count clock can be selected from five frequency-divided clocks of the
machine clock and the frequency-divided clocks of the timebase timer.
Unused bits
Read: The value is undefined.
Write: No effect
bit 1,
bit 0
299
CHAPTER 10 8-/16-BIT PPG TIMER
10.3.4
PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1)
The value (reload value) from which the PPG down counter starts counting is set in the
PPG reload registers, which are an 8-bit register at "L" level and an 8-bit register at "H"
level.
■ PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1)
Figure 10.3-5 PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1)
PRLH0/PRLH1
PRLL0/PRLL1
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Reset value
D15
D14
D13
D12
D11
D10
D9
D8
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reset value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Read/Write
X
: Undefined
Table 10.3-5 indicates the functions of the PPG reload registers.
Table 10.3-5 Functions of PPG Reload Registers
Function
8-/16-bit PPG Timer 0
8-/16-bit PPG Timer 1
Retains reload value on "L" level side
PRLL0
PRLL1
Retains reload value on "H" level side
PRLH0
PRLH1
Notes:
• In the 16-bit PPG output operation mode (PPGC1: MD1, MD0 = 11B), use a long-word instruction
to set the PPG reload registers or the word instruction to set the PPG0 and PPG1 in this order.
• In the 8 + 8-bit PPG output operation mode (PPGC1: MD1, MD0 = 01B), set the same value in
both the "L" level and "H" level PPG reload registers (PRLL0/PRLH0) of the 8-/16-bit PPG timer 0.
Setting a different value in the "L" level and "H" level PPG reload registers may cause the 8-/16bit PPG timer 1 to have different PPG output waveforms at each clock cycle.
300
CHAPTER 10 8-/16-BIT PPG TIMER
10.4
Interrupts of 8-/16-bit PPG Timer
The 8-/16-bit PPG timer can generate an interrupt request when the PPG down counter
underflows. It corresponds to the EI2OS.
■ Interrupts of 8-/16-bit PPG Timer
Table 10.4-1 shows the interrupt control bits and interrupt factor of the 8-/16-bit PPG timer.
Table 10.4-1 Interrupt Control Bits of 8-/16-bit PPG Timer
PPG0
PPG1
Interrupt request flag bit
PPPGC0: PUF0
PPGC1: PUF1
Interrupt request enable bit
PPGC0: PIE0
PPGC1: PIE1
Interrupt factor
Underflow in PPG0 down counter
Underflow in PPG1 down counter
[8-bit PPG output 2-channel independent operation mode or 8 + 8-bit PPG output operation mode]
• In the 8-bit PPG output 2-channel independent operation mode or the 8 + 8-bit PPG output operation
mode, the PPG0 and PPG1 timers can generate an interrupt independently.
• When the value of the PPG0 or PPG1 down counter is decremented from "00H" to "FFH", an underflow
occurs. When an underflow occurs, the underflow generation flag bit in the channel causing an
underflow is set (PPGC0: PUF0 = 1 or PPGC1: PUF1 = 1).
• If an interrupt request from the channel that causes an underflow is enabled (PPGC0: PIE0 = 1 or
PPGC1: PIE1 = 1), an interrupt request is generated.
[16-bit PPG output operation mode]
• In the 16-bit PPG output operation mode, when the values of the PPG0 and PPG1 down counters are
decremented from "0000H" to "FFFFH", an underflow occurs. When an underflow occurs, the underflow
generation flag bits in the two channels are set at one time (PPGC0: PUF0 = 1 and PPGC1: PUF1 = 1).
• When an underflow occurs with either of the two channel of the interrupt requests enabled (PPGC0:
PIE1 = 0, PPGC1: PIE1 = 1 or PPGC0: PIE1 = 1, PPGC1: PIE1 = 0), an interrupt request is generated.
• To prevent duplication of interrupt requests, disable either of the two channel of the underflow interrupt
enable bits (PPGC0: PIE1 = 0, PPGC1: PIE1 = 1 or PPGC0: PIE1 = 1, PPGC1: PIE1 = 0).
• When the two channels of the underflow generation flag bits are set (PPGC0: PUF0 = 1 and PPGC1:
PUF1 = 1), clear the two channels at the same time.
■ Correspondence between 8-/16-bit PPG Timer Interrupt and EI2OS
For details of the interrupt number, interrupt control register, and interrupt vector address, see "3.5
Interrupt".
301
CHAPTER 10 8-/16-BIT PPG TIMER
■ 8-/16-bit PPG Timer Interrupt and EI2OS Function
The 8-/16-bit PPG timer not correspond.
302
CHAPTER 10 8-/16-BIT PPG TIMER
10.5
Explanation of Operation of 8-/16-bit PPG Timer
The 8-/16-bit PPG timer outputs a pulse width at any frequency and at any duty ratio
continuously.
■ Operation of 8-/16-bit PPG Timer
● Output operation of 8-/16-bit PPG timer
• The 8-/16-bit PPG timer has two (Low-level and High-level) 8-bit reload registers (PRLL0/PRLH0 and
PRLL1/PRLH1) for each channel.
• The values set in the 8-bit reload registers (PRLL0/PRLH0 and PRLL1/PRLH1) are reloaded alternately
to the PPG down counters (PCNT0 and PCNT1).
• After reloading the values in the PPG down counters, decrementing is performed in synchronization
with the count clocks set by the PPG count clock select bits (PPG01: PCM2 to PCM0 and PCS1 and
PCS0).
• If the values set in the reload registers are reloaded to the PPG down counters when an underflow
occurs, the pin output is inverted.
Figure 10.5-1 shows the output waveform of the 8-/16-bit PPG timer.
Figure 10.5-1 Output Waveform of 8-/16-bit PPG Timer
Operation start
Operation stop
PPG operation enable bit
(PEN)
PPG output pin
T × (L + 1)
T × (H + 1)
L : Value of PPG reload register (PRLL)
H : Value of PPG reload register (PRLH)
T : Count clock cycle
● Operation modes of 8-/16-bit PPG timer
As long as the operation of the 8-/16-bit PPG timer is enabled (PPGC0: PEN0 = 1, PPGC1: PEN1 = 1), a
pulse waveform is output continuously from the PPG output pin. A pulse width of any frequency and duty
ratio can be set.
The pulse output of the 8-/16-bit PPG timer is not stopped until operation of the 8-/16-bit PPG timer is
stopped (PPGC0: PEN0 = 0, PPGC1: PEN1 = 0).
• 8-bit PPG output 2-channel independent operation mode
• 16-bit PPG output operation mode
• 8 + 8-bit PPG output operation mode
303
CHAPTER 10 8-/16-BIT PPG TIMER
10.5.1
8-bit PPG Output 2-channel Independent Operation Mode
In the 8-bit PPG output 2-channel independent operation mode, the 8-/16-bit PPG timer
is set as an 8-bit PPG timer with two independent channels. PPG output operation and
interrupt request generation can be performed independently for each channel.
■ Setting for 8-bit PPG Output 2-channel Independent Operation Mode
Operating the 8-/16-bit PPG timer in the 8-bit PPG output 2-channel independent operation mode requires
the setting shown in Figure 10.5-2.
Figure 10.5-2 Setting for 8-bit PPG Output 2-channel Independent Operation Mode
bit15
PPGC1/PPGC0
PEN1
14
−
13
12
PE1
PIE1
11
PUF1
10
MD1
MD0
0
0
1
PPG01
9
bit8
bit7
Reser
PEN0
ved
(Reserved area)
1
6
−
5
PE0
4
PIE0
3
PUF0
2
−
1
bit0
−
Reser
ved
1
1
PCS2 PCS1 PCS0
PCM
2
PCM
1
PCM
0
−
PRLH0/PRLL0
PPG0 Set High level side reload values.
PPG0 Set Low level side reload values.
PRLH1/PRLL1
PPG1 Set High level side reload values.
PPG1 Set Low level side reload values.
:
:
1 :
0 :
−
−
Used bit
Unused bit
Set 1
Set 0
Note:
Use the word instruction to set both High-level and Low-level PPG reload registers (PRLL0/PRLH0
and PRLL1/PRLH1) at the same time.
304
CHAPTER 10 8-/16-BIT PPG TIMER
● Operation in 8-bit PPG output 2-channel independent operation mode
• The 8-bit PPG timer with two channels performs an independent PPG operation.
• When the pin output is enabled (PPGC0: PE0 = 1, PPGC1: PE1 = 1), the PPG0 pulse wave is output
from the PPG0 pin and the PPG1 pulse wave is output from the PPG1 pin.
• When the reload value is set in the PPG reload registers (PRLL0/PRLH0 and PRLL1/PRLH1) to enable
the operation of the PPG timer (PPGC0: PEN0 = 1, PPGC1: PEN1 = 1), the PPG down counter of the
enabled channel starts counting.
• To stop the count operation of the PPG down counter, disable the operation of the PPG timer of the
channel to be stopped (PPGC0: PEN0 = 0, PPGC1: PEN1 = 0). The count operation of the PPG down
counter is stopped and the output of the PPG output pin is held at a Low level.
• When the PPG down counter of each channel underflows, the reload values set in the PPG reload
registers (PRLL0/PRLH0 and PRLL1/PRLH1) are reloaded to the PPG down counter that underflows.
• When an underflow occurs, the underflow generation flag bit in the channel that causes an underflow is
set (PPGC0: PUF0 = 1, PPGC1: PUF1 = 1). If an interrupt request is enabled at the channel that causes
an underflow (PPGC0: PIE0 = 1, PPGC1: PIE1 = 1), the interrupt request is generated.
● Output waveform in 8-bit PPG output 2-channel independent operation mode
• The "H" and "L" pulse widths to be output are determined by adding 1 to the value in the PPG reload
register and multiplying it by the count clock cycle. For example, if the value in the PPG reload register
is "00H", the pulse width has one count clock cycle, and if the value is "FFH", the pulse width has 256
count clock cycles.
The equations for calculating the pulse width are shown below:
PL= T × (L + 1)
PH= T × (H + 1)
PL: "L" width of output pulse
PH: "H" width of output pulse
L: Values of 8 bits in PPG reload register (PRLL0 or PRLL1)
H: Values of 8 bits in PPG reload register (PRLH0 or PRLH1)
T: Count clock cycle
Figure 10.5-3 shows the output waveform in the 8-bit PPG output 2-channel independent operation mode.
Figure 10.5-3 Output Waveform in 8-bit PPG Output 2-channel Independent Operation Mode
Operation start
Operation stop
PPG operation enable bit
(PEN)
PPG output pin
T × (L + 1)
T × (H + 1)
L : Value of PPG reload register (PRLL)
H : Value of PPG reload register (PRLH)
T : Count clock cycle
305
CHAPTER 10 8-/16-BIT PPG TIMER
10.5.2
16-bit PPG Output Operation Mode
In the 16-bit PPG output operation mode, the 8-/16-bit PPG timer is set as a 16-bit PPG
timer with one channel.
■ Setting for 16-bit PPG Output Operation Mode
Operating the 8-/16-bit PPG timer in the 16-bit PPG output operation mode requires the setting shown in
Figure 10.5-4.
Figure 10.5-4 Setting for 16-bit PPG Output Operation Mode
bit15
PPGC1/PPGC0
PEN1
14
−
13
12
PE1
PIE1
11
PUF1
10
MD1
1
1
9
bit8
1
1
(Reserved area)
PPG01
bit7
ReMD0
PEN0
served
6
5
4
3
2
1
bit0
−
PE0
PIE0
PUF0
−
−
Reserved
1
1
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
X
X
−
−
X
PRLH0/PRLL0
PPG0 Set "H" level side reload values of lower 8 bits.
PPG0 Set "L" level side reload values of lower 8 bits.
PRLH1/PRLL1
PPG1 Set "H" level side reload values of upper 8 bits.
PPG1 Set "L" level side reload values of upper 8 bits.
: Used bit
X: Undefined bit
−: Unused bit
1: Set 1
0: Set 0
Note:
Use a long-word instruction to set the values in the PPG reload registers or a word instruction to set
the PPG0 and PPG1 (PRLL0 --> PRLL1 or PRLH0 --> PRLH1) in this order.
306
CHAPTER 10 8-/16-BIT PPG TIMER
● Operation in 16-bit PPG output operation mode
• When either PPG0 pin output or PPG1 pin output is enabled (PPGC0: PE0 = 1, PPGC1: PE1 = 1), the
same pulse wave is output from both the PPG0 and PPG1 pins.
• When the reload value is set in the PPG reload registers (PRLL0/PRLH0 and PRLL1/PRLH1) to enable
operation of the PPG timer (PPGC0: PEN0 = 1 and PPGC1: PEN1 = 1) simultaneously, the PPG down
counters start counting as 16-bit down counters (PCNT0 + PCNT1).
• To stop the count operation of the PPG down counters, disable the operation of the PPG timers of both
channels (PPGC0: PEN0 = 0 and PPGC1: PEN1 = 0) simultaneously. The count operation of the PPG
down counters is stopped and the output of the PPG output pin is held at a Low level.
• If the PPG1 down counter underflows, the reload values set in the PPG0 and PPG1 reload registers
(PRLL0/PRLH0 and PRLL1/PRLH1) are reloaded simultaneously to the PPG down counters (PCNT0 +
PCNT1).
• When an underflow occurs, the underflow generation flag bits in both channels are set simultaneously
(PPGC0: PUF0 = 1, PPGC1: PUF1 = 1). If an interrupt request is enabled at either channel (PPGC0:
PIE0 = 1, PPGC1: PIE1 = 1), an interrupt request is generated.
Notes:
• In the 16-bit PPG output operation mode, the underflow generation flag bits in the two channels
are set simultaneously when an underflow occurs (PPGC0: PUF0 = 1 and PPGC1: PUF1 = 1). To
prevent duplication of interrupt requests, disable either of the underflow interrupt enable bits in the
two channels (PPGC0: PIE0 = 0, PPGC1: PIE1 = 1 or PPGC0: PIE0 = 1, PPGC1: PIE1 = 0).
• If the underflow generation flag bits in the two channels are set (PPGC0: PUF0 = 0 and
PPGC1: PUF1 = 0), clear the two channels at the same time.
307
CHAPTER 10 8-/16-BIT PPG TIMER
● Output waveform in 16-bit PPG output operation mode
• The "H" and "L" pulse widths to be output are determined by adding 1 to the value in the PPG reload
register and multiplying it by the count clock cycle. For example, if the value in the PPG reload register
is "0000H", the pulse width has one count clock cycle, and if the value is "FFFFH", the pulse width has
65536 count clock cycles.
The equations for calculating the pulse width are shown below:
PL= T × (L + 1)
PH= T × (H + 1)
PL: "L" width of output pulse
PH: "H" width of output pulse
L: Values of 16 bits in PPG reload register (PRLL0 + PRLL1)
H: Values of 16 bits in PPG reload register (PRLH0 + PRLH1)
T: Count clock cycle
Figure 10.5-5 shows the output waveform in the 16-bit PPG output operation mode.
Figure 10.5-5 Output Waveform in 16-bit PPG Output Operation Mode
Operation start
Operation stop
PPG operation enable bit
(PEN)
PPG output pin
T × (L + 1)
T × (H + 1)
L : Values of 16 bits in PPG reload register (PRLL1 + PRLL0)
H : Values of 16 bits in PPG reload register (PRLH1 + PRLH0)
T : Count clock cycle
308
CHAPTER 10 8-/16-BIT PPG TIMER
10.5.3
8+8-bit PPG Output Operation Mode
In the 8+8-bit PPG output operation mode, the 8-/16-bit PPG timer is set as an 8-bit PPG
timer. The PPG0 operates as an 8-bit prescaler and the PPG1 operates using the PPG
output of the PPG0 as a clock source.
■ Setting for 8+8-bit PPG Output Operation Mode
Operating the 8-/16-bit PPG timer in the 8+8-bit PPG output operation mode requires the setting shown in
Figure 10.5-6.
Figure 10.5-6 Setting for 8+8-bit PPG Output Operation Mode
PPGC1/PPGC0
bit15
14
13
12
11
10
9
PEN1
−
PE1
PIE1
PUF1
MD1
MD0
0
1
1
bit8
(Reserved area)
PPG01
bit7
Re- PEN0
served
1
6
5
4
3
2
1
bit0
−
PE0
PIE0
PUF0
−
−
Reserved
1
1
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
X
X
−
X
PRLH0/PRLL0
PPG0 Set High level side reload values.
PPG0 Set Low level side reload values.
PRLH1/PRLL1
PPG1 Set High level side reload values.
PPG1 Set Low level side reload values.
X:
−:
1:
0:
−
: Used bit
Undefined bit
Unused bit
Set 1
Set 0
Note:
Use the word instruction to set both High-level and Low-level PPG reload registers (PRLL0/PRLH0
and PRLL1/PRLH1) at the same time.
309
CHAPTER 10 8-/16-BIT PPG TIMER
● Operation in 8+8-bit PPG output operation mode
• The PPG0 operates as the prescaler of the PPG1 timer and the PPG1 operates using the PPG0 output as
a count clock.
• When pin output is enabled (PPGC0: PE0 = 1, PPGC1: PE1 = 1), the PPG0 pulse wave is output from
the PPG0 pin and the PPG1 pulse wave is output form the PPG1 pin.
• When the reload value is set in the PPG reload registers (PRLL0/PRLH0, PRLL1/PRLH1) to enable
operation of the PPG timer (PPGC0: PEN0 = 1 and PPGC1: PEN1 = 1), the PPG down counter starts
counting.
• To stop the count operation of the PPG down counters, disable the operation of the PPG timers of both
channels (PPGC0: PEN0 = 0 and PPGC1: PEN1 = 0) at the same time. The count operation of the PPG
down counters is stopped and the output of the PPG output pin is held at a Low level.
• If the PPG down counter of each channel underflows, the reload values set in the PPG reload registers
(PRLL0/PRLH0, PRLL1/PRLH1) are reloaded to the PPG down counter that underflows.
• When an underflow occurs, the underflow generation flag bit in the channel that causes an underflow
(PPGC0: PUF0 = 1, PPGC1: PUF1 = 1) is set. If an interrupt request is enabled at the channel that
causes an underflow (PPGC0: PIE0 = 1, PPGC1: PIE1 = 1), an interrupt request is generated.
Notes:
• Do not operate PPG1 (PPGC1: PEN1 = 1) when PPG0 is stopped (PPGC0: PEN0 = 0).
• It is recommended to set the same value in both Low-level and High-level PPG reload registers
(PRLL0/PRLH0, PRLL1/PRLH1).
310
CHAPTER 10 8-/16-BIT PPG TIMER
● Output waveform in 8+8-bit PPG output operation mode
• The "H" and "L" pulse widths to be output are determined by adding 1 to the value in the PPG reload
register and multiplying it by the count clock cycle.
The equations for calculating the pulse width are shown below:
PL = T × (L0+ 1) × (L 1+ 1)
PH = T × (H0+ 1) × (H 1+ 1)
PL: "L" width of output pulse of PPG1 pin
PH: "H" width of output pulse of PPG1 pin
L0: Values of 8 bits in PPG reload register (PRLL0)
H0: Values of 8 bits in PPG reload register (PRLH0)
L1: Values of 8 bits in PPG reload register (PRLL1)
H1: Values of 8 bits in PPG reload register (PRLH1)
T: Count clock cycle
Figure 10.5-7 shows the output waveform in the 8+8-bit PPG output operation mode.
Figure 10.5-7 Output Waveform in 8+8-bit PPG Output Operation Mode
Operation start
Operation stop
PPG operation enable bit
(PEN0, PEN1)
T × (L0 + 1)
T × (H0 + 1)
PPG0 output pin
PPG1 output pin
T × (L0 + 1) × (L1 + 1)
L0 :
H0 :
H1 :
L1 :
T :
T × (H0 + 1) × (H1 + 1)
Values of 8 bits in PPG reload register (PRLL0)
Values of 8 bits in PPG reload register (PRLH0)
Values of 8 bits in PPG reload register (PRLL1)
Values of 8 bits in PPG reload register (PRLH1)
Count clock cycle
311
CHAPTER 10 8-/16-BIT PPG TIMER
10.6
Precautions when Using 8-/16-bit PPG Timer
This section explains the precautions when using the 8-/16-bit PPG timer.
■ Precautions when Using 8-/16-bit PPG Timer
● Effect on 8-/16-bit PPG timer when using timebase timer output
• If the output signal of the timebase timer is used as the input signal for the count clock of the 8-/16-bit
PPG timer (PPG01: PCM2 to PCM0 = 111B, PCS2 to PCS0 = 111B), deviation may occur in the first
count cycle in which the PPG timer is started by trigger input or in the count cycle immediately after the
PPG timer is stopped.
• When the timebase timer counter is cleared during the count operation of the PPG down counter,
deviation may occur in the count cycle.
● Setting of PPG reload registers when using 8-bit PPG timer
• The "L" level and "H" level pulse widths are determined at the timing of reloading the values in the "L"
level PPG reload registers (PRLL0, PRLL1) to the PPG down counter.
• If the 8-bit PPG timer is used in the 8-bit PPG output 2-channel independent operation mode or the 8 +
8-bit PPG output operation mode, use a word instruction to set both "H" level and "L" level PPG reload
registers (PRLL0/PRLH0, PRLL1/PRLH1) at the same time.
Using a byte instruction may cause an unexpected pulse to be generated.
[Example of rewriting PPG reload registers using byte instruction]
Immediately before the signal level of the PPG pin switches from "H" to "L", if the value in the "H" level
PPG reload register (PRLH) is rewritten after the value in the "L" level PPG reload register (PRLL) is
rewritten using the byte instruction, a "L" level pulse width is generated after rewriting and a "H" level
pulse width is generated before rewriting.
Figure 10.6-1 shows the waveform as the values in the PPG reload registers are rewritten using the byte
instruction.
Figure 10.6-1 Waveform when Values in PPG Reload Registers Rewritten Using Byte Instruction
PRLL
A
PRLH
B
A+B
C
D
A+B
B+C
C+D
B
B
C + D Timing of updating
reload value
C+D
PPG pin
A
B
A
C
<1> <2>
<1>: Change the value (A → C) of PPG reload register (PRLL)
<2>: Change the value (B → D) of PPG reload register (PRLH)
312
C
D
C
D
CHAPTER 10 8-/16-BIT PPG TIMER
● Setting of PPG reload registers when using 16-bit PPG timer
• Use a long-word instruction to set the PPG reload registers (PRLL0/PRLH0, PRLL1/PRLH1) or a word
instruction to set the PPG0 and PPG1 (PRLL0 → PRLL1 or PRLH0 → PRLH1) in this order.
[Reload timing in 16-bit PPG output operation mode]
In the 16-bit PPG output operation mode, the reload values written to the PPG0 reload registers (PRLL0/
PRLH0) are written temporarily to the temporary latch, written to the PPG1 reload registers (PRLL1/
PRLH1), and then transferred to the PPG0 reload registers (PRLL0/PRLH0). Therefore, when setting the
reload value in the PPG1 reload registers (PRLL1/PRLH1), it is necessary to set the reload value in the
PPG0 reload registers (PRLL0/PRLH0) simultaneously or set the reload value in the PPG0 reload registers
(PRLL0/PRLH0) before setting it in the PPG1 reload registers (PRLL1/PRLH1).
Figure 10.6-2 shows the reload timing in the 16-bit PPG output operation mode.
Figure 10.6-2 Reload Timing in 16-bit PPG Output Operation Mode
Reload value
of PPG0
Only 16-bit PPG output operation mode
Write to PPG0 except 16-bit
PPG output operation mode
Temporary latch
Reload value
of PPG1
Write to PPG1
Transfers synchronously
with writing to PPG1
PPG reload register
(PRLL0, PRLH0)
PPG reload register
(PRLL1, PRLH1)
313
CHAPTER 10 8-/16-BIT PPG TIMER
314
CHAPTER 11
DELAYED INTERRUPT
GENERATION MODULE
This chapter explains the functions and operations of
the delayed interrupt generation module.
11.1 Overview of Delayed Interrupt Generation Module
11.2 Block Diagram of Delayed Interrupt Generation Module
11.3 Configuration of Delayed Interrupt Generation Module
11.4 Explanation of Operation of Delayed Interrupt Generation Module
11.5 Precautions when Using Delayed Interrupt Generation Module
11.6 Program Example of Delayed Interrupt Generation Module
315
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.1
Overview of Delayed Interrupt Generation Module
The delayed interrupt generation module generates the interrupt for task switching.
The hardware interrupt request can be generated by software.
■ Overview of Delayed Interrupt Generation Module
By using the delayed interrupt generation module, a hardware interrupt request can be generated or
canceled by software.
Table 11.1-1 shows the overview of the delayed interrupt generation module.
Table 11.1-1 Overview of Delayed Interrupt Generate Module
Function and Control
316
Interrupt factor
An interrupt request is generated by setting the R0 bit in the delayed interrupt
request generate/cancel register to "1" (DIRR: R0 = 1).
An interrupt request is canceled by setting the R0 bit in the delayed interrupt
request generate/cancel register to "0" (DIRR: R0 = 0).
Interrupt number
#42 (2AH)
Interrupt control
An interrupt is not enabled by the DIRR register.
Interrupt flag
The interrupt flag is held in the R0 bit in the DIRR register.
EI2OS
The DIRR register does not correspond to the EI2OS.
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.2
Block Diagram of Delayed Interrupt Generation Module
The delayed interrupt generation module consists of the following blocks:
• Interrupt request latch
• Delayed interrupt request generate/cancel register (DIRR)
■ Block Diagram of Delayed Interrupt Generation Module
Figure 11.2-1 Block Diagram of Delayed Interrupt Generation Module
Internal data bus
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R0
Delayed interrupt request generate/cancel register (DIRR)
⎯: Unused
S Interrupt request
R latch
Interrupt
request
signal
● Interrupt request latch
This latch keeps the settings (delayed interrupt request generation or cancellation) of the delayed interrupt
request generate/cancel register (DIRR).
● Delayed interrupt request generate/cancel register (DIRR)
This register generates or cancels a delayed interrupt request.
■ Interrupt Number
The interrupt number used in the delayed interrupt generation module is #42 (2AH).
317
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.3
Configuration of Delayed Interrupt Generation Module
This section lists registers and reset values in the delayed interrupt generation module.
■ List of Registers and Reset Values in Delayed Interrupt Generation Module
Figure 11.3-1 List of Registers and Reset Values in Delayed Interrupt Generation Module
bit
Delayed interrupt request generate/
cancel register (DIRR)
X: Undefined
318
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
0
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.3.1
Delayed Interrupt Request Generate/Cancel Register
(DIRR)
The delayed interrupt request generate/cancel register (DIRR) generates or cancels a
delayed interrupt request.
■ Delayed Interrupt Request Generate/Cancel Register (DIRR)
Figure 11.3-2 Delayed Interrupt Request Generate/Cancel Register (DIRR)
Address:
00009FH
15
14
13
12
11
10
9
8
Reset value
XXXXXXX0B
⎯
⎯
⎯
⎯
⎯
⎯
⎯ R/W
bit 8
⎯
: Unused
R/W : Read/Write
: Reset value
R0
0
1
Delayed interrupt request generate bit
Cancels delayed interrupt request
Generates delayed interrupt request
Table 11.3-1 Functions of Delayed Interrupt Request Generate/Cancel Register (DIRR)
Bit Name
bit 15 to bit 9
bit 8
Function
Unused bits
Read: The value is undefined
Write: No effect
R0:
Delayed interrupt request
generate bit
This bit generates or cancels a delayed interrupt request.
When set to "0": Cancels delayed interrupt request
When set to "1": Generates delayed interrupt request
319
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.4
Explanation of Operation of Delayed Interrupt Generation
Module
The delayed interrupt generation module has a function for generating or canceling an
interrupt request by software.
■ Explanation of Operation of Delayed Interrupt Generation Module
Using the delayed interrupt generation module requires the setting shown in Figure 11.4-1.
Figure 11.4-1 Setting for Delayed Interrupt Generation Module
DIRR
-
bit15
-
14
-
13
-
12
-
11
-
10
-
9
-
bit8
R0
: Unused bit
: Used bit
When the R0 bit in the delayed interrupt request generate/cancel register (DIRR) is set to "1" (DIRR: R0 =
1), an interrupt request is generated. There is no interrupt request enable bit.
● Operation of delayed interrupt generation module
• When the R0 bit in the delayed interrupt request generate/cancel register (DIRR) is set to "1", the
interrupt request latch is set to "1" and an interrupt request is generated to the interrupt controller.
• When an interrupt request is preferred to other requests by the interrupt controller, the interrupt request
is generated to the CPU.
• When the level of an interrupt request (ICR: IL) is preferred to that of the interrupt level mask bit (ILM)
in the processor status (PS), the CPU delays interrupt processing until completion of execution of the
current instruction.
• At interrupt processing, the user program sets the R0 bit to "0", cancels the interrupt request, and
changes the task.
Figure 11.4-2 shows the operation of the delayed interrupt generation module.
Figure 11.4-2 Operation of Delayed Interrupt Generation Module
Delayed interrupt generation module
Other request
DIRR
Interrupt controller
CPU
IL
ICR YY
CMP
CMP
ICR XX
320
ILM
Interrupt
processing
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.5
Precautions when Using Delayed Interrupt Generation
Module
This section explains the precautions when using the delayed interrupt generation
module.
■ Precautions when Using Delayed Interrupt Generation Module
• The interrupt processing is restarted at return from interrupt processing without setting the R0 bit in the
delayed interrupt request generate/cancel register (DIRR) to "0" within the interrupt processing routine.
• Unlike software interrupts, interrupts in the delayed interrupt generation module are delayed.
321
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.6
Program Example of Delayed Interrupt Generation Module
This section gives a program example of the delayed interrupt generation module.
■ Program Example of Delayed Interrupt Generation Module
● Processing specifications
The main program writes "1" to the R0 bit in the delayed interrupt request generate/cancel register (DIRR),
generates a delayed interrupt request, and changes the task.
● Coding example
ICR15
EQU 0000BFH
; Interrupt control register
DIRR
EQU 00009FH
; Delayed interrupt request generate/cancel register
DIRR_R0 EQU DIRR:0
; Delayed interrupt request generate bit
;-----Main program--------------------------------------------------------------CODE
CSEG
START:
; Stack pointer (SP) already initialized
AND CCR,#0BFH
; Interrupt disabled
MOV I:ICR15,#00H
; Interrupt level 0 (highest)
MOV ILM,#07H
; ILM in PS set to level 7
OR
CCR, #40H
; Interrupt enabled
SETB I:DIRR_R0
; Delayed interrupt request generated
LOOP
MOV A,#00H
; Infinite loop
MOV A,#01H
BRA LOOP
;-----Interrupt program---------------------------------------------------------WARI:
CLRB I:DIRR_R0
; Interrupt request flag cleared
:
;
Processing by user
;
:
RETI
; Return from interrupt
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG 00FF54H
; Vector set to interrupt #42 (2AH)
DSL WARI
ORG 0FFDCH
; Reset vector set
DSL START
DB
00H
; Set to single-chip mode
VECT
ENDS
END START
322
CHAPTER 12
DTP/EXTERNAL INTERRUPT
This chapter explains the functions and operations of
DTP/external interrupt.
12.1 Overview of DTP/External Interrupt
12.2 Block Diagram of DTP/External Interrupt
12.3 Configuration of DTP/External Interrupt
12.4 Explanation of Operation of DTP/External Interrupt
12.5 Precautions when Using DTP/External Interrupt
12.6 Program Example of DTP/External Interrupt Circuit
323
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.1
Overview of DTP/External Interrupt
The DTP/external interrupt sends interrupt requests from external peripheral devices or
data transfer requests to the CPU to generate an external interrupt request, or starts the
EI2OS. RX input of CAN controller can be used as external interrupt input.
■ DTP/External Interrupt Function
The interrupt request inputted to external interrupt input pins (INT7 to INT4) and RX input from external
peripheral devices generates an external interrupt request, or starts the EI2OS as an interrupt request from
peripheral function.
If the EI2OS is disabled in the interrupt control register (ICR: ISE = 0), the external interrupt function is
enabled, branching to interrupt processing.
If the EI2OS is enabled (ICR: ISE = 1), the DTP function is enabled and automatic data transfer is
performed, branching to interrupt processing after the completion of data transfer for the specified number
of times.
Table 12.1-1 shows an overview of the DTP/external interrupt.
Table 12.1-1 Overview of DTP/External Interrupt
External Interrupt
Input pin
DTP Function
5 pins (RX, INT4 to INT7)
The interrupt factor is set in unit of pins using the detection level setting registers (ELVR).
Interrupt factor
Input of "H" level, "L" level,
rising edge, or falling edge
Interrupt number
#15 (0FH), #24 (18H), #27 (1BH)
Interrupt control
The interrupt request output is enabled/disabled using the DTP/external interrupt enable register
(ENIR).
Interrupt flag
The interrupt factor is held using the DTP/external interrupt factor register (EIRR)
Processing selection
The EI2OS is disabled.
(ICR: ISE=0)
The EI2OS is enabled.
(ICR: ISE=1)
A branch is caused to the external interrupt
processing.
EI2OS performs auto data transfer and
completes the specified number of timer for
data transfers, causing a branch to the interrupt
processing.
Processing contents
324
Input of "H" level or "L" level
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.2
Block Diagram of DTP/External Interrupt
The block diagram of the DTP/external interrupt is shown below.
■ Block Diagram of DTP/External Interrupt
Figure 12.2-1 Block Diagram of DTP/External Interrupt
Detection level setting register (ELVR)
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4
Pin
ReReReReReReserved served served served served served
LB0 LA0
Level edge
selector
INT7
Pin
Level edge
selector
Internal data bus
INT6
Pin
Level edge
selector
INT5
Pin
Level edge
selector
Pin
INT4
Level edge
selector
RX
DTP/external interrupt input detector
Re-
Re-
Re-
ER7 ER6 ER5 ER4 served served served ER0
Interrupt
request signal
DTP/external interrupt
factor register (EIRR)
Interrupt
request signal
Re-
Re-
Re-
EN7 EN6 EN5 EN4 served served served EN0
DTP/external interrupt
enable register (ENIR)
325
CHAPTER 12 DTP/EXTERNAL INTERRUPT
● DTP/external interrupt input detector
This circuit detects interrupt requests or data transfer requests generated from external peripheral devices.
The interrupt request flag bit corresponding to the pin whose level or edge set by the detection level setting
register (ELVR) is detected is set to "1" (EIRR: ER).
● Detection level setting register (ELVR)
This register sets the level or edge of input signals from external peripheral devices that cause DTP/external
interrupt factors.
● DTP/external interrupt factor register (EIRR)
This register holds DTP/external interrupt factors.
If an enable signal is input to the DTP/external interrupt pin, the corresponding DTP/external interrupt
request flag bit is set to "1".
● DTP/external interrupt enable register (ENIR)
This register enables or disables DTP/external interrupt requests from external peripheral devices.
■ Details of Pins and Interrupt Numbers
Table 12.2-1 shows the pins and interrupt numbers used in the DTP/external interrupt.
Table 12.2-1 Pins and Interrupt Numbers Used by DTP/External Interrupt
326
Pin
Channel
Interrupt Number
P44/RX
RX
#15 (0FH)
P24/INT4
4
P25/INT5
5
P26/INT6
6
P27/INT7
7
#24 (18H)
#27 (1BH)
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.3
Configuration of DTP/External Interrupt
This section lists and details the pins, interrupt factors, and registers in the DTP/
external interrupt.
■ Pins of DTP/External Interrupt
The pins used by the DTP/external interrupt serve as general-purpose I/O ports.
Table 12.3-1 lists the pin functions and the pin setting required for use in the DTP/external interrupt
Table 12.3-1 Pins of DTP/External Interrupt
Pin Name
P44/RX
Pin Settings Required for Use in
DTP/External Interrupt
Pin Function
General-purpose I/O ports,
CAN reception input
P24/INT4
P25/INT5
P26/INT6
Set as input ports in port direction register (DDR)
General-purpose I/O ports,
DTP external interrupt inputs
P27/INT7
■ Block Diagram of Pins
See "CHAPTER 4 I/O PORT" for the block diagram of pins.
■ List of Registers and Reset Values in DTP/External Interrupt
Figure 12.3-1 List of Registers and Reset Values in DTP/External Interrupt
bit
DTP/external interrupt factor register (EIRR)
bit
DTP/external interrupt enable register (ENIR)
bit
Detection level setting register: High (ELVR)
bit
Detection level setting register: Low (ELVR)
15
X
7
0
15
0
7
0
14
X
6
0
14
0
6
0
13
X
5
0
13
0
5
0
12
X
4
0
12
0
4
0
11
X
3
0
11
0
3
0
10
X
2
0
10
0
2
0
9
X
1
0
9
0
1
0
8
X
0
0
8
0
0
0
X: Undefined
327
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.3.1
DTP/External Interrupt Factor Register (EIRR)
The DTP/external interrupt factor register (EIRR) holds DTP/external interrupt factors.
When a valid signal is input to the DTP/external interrupt pin and the RX pin, the
corresponding interrupt request flag bit is set to "1".
■ DTP/External Interrupt Factor Register (EIRR)
Figure 12.3-2 DTP/External Interrupt Factor Register (EIRR)
Address:
000031H
15
14
13
12
11
10
9
8
-
-
-
R/W
Reset value
XXXXXXXXB
R/W R/W R/W R/W
bit 15 to bit 12, bit 8
ER7 to ER4, ER0
R/W : Read/Write
X
: Undefined
: Unused
0
1
DTP/external interrupt request flag bits
Read
Write
No DTP/external interrupt input Clears ER bit
DTP/ external interrupt input
No effect
Table 12.3-2 Function of DTP/External Interrupt Factor Register (EIRR)
Bit Name
Function
bit 15 to
bit12,
bit 8
ER7 to ER4, ER0:
DTP/External interrupt
request flag bits
These bits are set to "1" when the edges or level signals set by the detection
condition select bits in the detection level setting register (ELVR: LB, LA) are input
to the DTP/external interrupt pins and RX pin.
When set to "1": When the DTP/external interrupt request enable bit (ENIR: EN)
is set to "1", an interrupt request is generated to the
corresponding DTP/external interrupt channel.
When set to "0": Cleared
When set to "1": No effect
Note: Reading by read-modify-write (RMW) type instructions always reads "1".
If more than one DTP/external interrupt request is enabled (ENIR:
EN = 1), clear only the bit in the channel that accepts an interrupt (EIRR: ER
= 0). No other bits must be cleared unconditionally.
Reference: When the EI2OS is started, the interrupt request flag bit is automatically
cleared after the completion of data transfer (EIRR: ER = 0).
bit 11 to
bit 9
Unused bit
Read: The value is undefined.
Write: No effect
Notes:
• DTP/external interrupt request flag bit (EIRR=ER) value is valid only when the DTP/external
interrupt request enabled bit (ENIR=EN) are set to "1". The DTP/external interrupt request flag
bits can be set in a state where DTP/external interrupt is not enabled regardless of the DTP/
external interrupt causes.
• Clear the corresponding DTP/external interrupt request flag bit (EIRR=ER) immediately before
enabling the DTP/external interrupt (ENIR=EN=1).
328
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.3.2
DTP/External Interrupt Enable Register (ENIR)
The DTP/external interrupt enable register (ENIR) enables/disables the DTP/external
interrupt request for external interrupt pins (INT7 to INT4) and the RX pin respectively.
■ DTP/External Interrupt Enable Register (ENIR)
Figure 12.3-3 DTP/External Interrupt Enable Register (ENIR)
Address:
000030H
7
6
5
4
3
2
1
0
ReReReserved served served
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 3 to bit 1
Reserved
bit 7 to bit 4, bit 0
EN7 to EN4, EN0
R/W : Read/Write
: Reset value
Reserved bits
Always set these bits to 0
0
DTP/external interrupt request enable bits
DTP/external interrupt disable
DTP/external interrupt enable
0
1
Table 12.3-3 Functions of DTP/External Interrupt Enable Register (ENIR)
Bit Name
bit 7 to bit 4,
bit 0
Function
EN7 to EN4, EN0:
DTP/external
interrupt request
enable bits
The DTP/external interrupt enable register (ENIR) enables/disables the DTP/
external interrupt request for DTP/external interrupt pins (INT7 to INT4) and the
RX pin.
If the DTP/external interrupt request enable bit (ENIR: EN) and the DTP/external
interrupt request flag bit (EIRR: ER) are set to "1", the interrupt request is generated
to the corresponding DTP/external interrupt pins or the RX pin.
Reference: The state of the DTP/external interrupt pin and the RX pin can be read
directly using the port data register irrespective of the setting of the
DTP/external interrupt request enable bit.
Table 12.3-4 Correspondence among DTP/External Interrupt Pins, DTP/External Interrupt
Request Flag Bits, and DTP/External Interrupt Request Enable Bits
DTP/External Interrupt Pins
DTP/External Interrupt
Request Flag Bits
DTP/External Interrupt
Request Enable Bits
RX
ER0
EN0
INT4
ER4
EN4
INT5
ER5
EN5
INT6
ER6
EN6
INT7
ER7
EN7
329
CHAPTER 12 DTP/EXTERNAL INTERRUPT
Note:
Clear the corresponding DTP/external interrupt request flag bit (EIRR=EN) immediately before
enabling the DTP/external interrupt (ENIR=EN=1).
330
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.3.3
Detection Level Setting Register (ELVR) (High)
The detection level setting register (High) sets the levels or edges of input signals that
cause interrupt factors in INT7 to INT4 of the DTP/external interrupt pins.
■ Detection Level Setting Register (ELVR) (High)
Figure 12.3-4 Detection Level Setting Register (ELVR) (High)
Address: 15
000033H
14
13
12
11
10
9
8
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 15 to bit 8
LB7, LA7
LB6, LA6
LB5, LA5
LB4, LA4
0
0
0
1
1
0
1
1
R/W : Read/Write
: Reset value
Detection condition select bits
Detects "L" level
Detects "H" level
Detects rising edge
Detects falling edge
Table 12.3-5 Functions of Detection Level Setting Register (ELVR) (High)
Bit Name
bit 15 to bit 8
Function
LB7, LA7 to LB4, LA4:
Detection condition
select bits
These bits set the levels or edges of input signals from external peripheral
devices that cause interrupt factors in the DTP/external interrupt pins.
Two levels or two edges are selectable for external interrupts, and two levels
are selectable for the EI2OS.
Reference: When the set detection signal is input to the DTP/external
interrupt pins, the DTP/external interrupt request flag bits are set
to "1" even if DTP/external interrupt requests are disabled
(ENIR: EN = 0).
Table 12.3-6 Correspondence between Detection Level Setting Register (ELVR) (High) and
Channels
DTP/External Interrupt Pin
Bit Name
INT4
LB4, LA4
INT5
LB5, LA5
INT6
LB6, LA6
INT7
LB7, LA7
331
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.3.4
Detection Level Setting Register (ELVR) (Low)
The detection level setting register (ELVR) (Low) sets the levels or edges of input
signals that cause interrupt factors in the RX pin.
■ Detection Level Setting Register (ELVR) (Low)
Figure 12.3-5 Detection Level Setting Register (ELVR) (Low)
Address:
000032H
7
6
5
4
3
2
1
0
Reset value
ReReReReReReserved served served served served served
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit1 bit0
LB0, LA1
0
0
1
1
0
1
0
1
Detection condition select bits
Detects "L" level
Detects "H" level
Detects rising edge
Detects falling edge
bit 7 to bit 2
Reserved
R/W : Read/Write
: Reset value
0
Reserved bits
Always set these bits to 0
Table 12.3-7 Functions of Detection Level Setting Register (ELVR) (Low)
Bit Name
bit 1 to bit 0
Function
LB3, LA0:
Detection condition
select bits
These bits set the levels or edges of input signals from external peripheral
devices that cause interrupt factors in the RX pin.
• Two levels or two edges are selectable for external interrupts, and two
levels are selectable for the EI2OS.
Reference: When the set detection signal is input to the RX pin, the DTP/
external interrupt request flag bits are set to "1" even if DTP/
external interrupt requests are disabled (ENIR: EN = 0).
Table 12.3-8 Correspondence between Detection Level Setting Register (ELVR) (Low) and
Channels
332
DTP/External Interrupt Pin
Bit Name
RX
LB0, LA0
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.4
Explanation of Operation of DTP/External Interrupt
The DTP/external interrupt has an external interrupt function and a DTP function. The
setting and operation of each function are explained.
■ Setting of DTP/External Interrupt
Using the DTP/external interrupt requires, the setting shown in Figure 12.4-1.
Figure 12.4-1 Setting of DTP/External Interrupt
bit15
14
13
12
ICR interrupt
ICS3 ICS2 ICS1 ICS0
control register
External interrupt DTP
EIRR/ENIR
ER7
ELVR
LB7
ER6
LA7
ER5
LB6
ER4
LA6
11
10
9
bit8
bit7
6
5
4
3
2
1
bit0
ISE
IL2
IL1
IL0
ICS3
ICS2
ICS1
ICS0
ISE
IL2
IL1
IL0
-
-
-
-
0
1
EN7
EN6
EN5
EN4
0
1
-
-
-
-
-
-
LB5
LA5
LB4
ER0
ReReReEN0
served served served
0
LA4
0
0
ReReReReReReLB0
served served served served served served
0
0
0
0
0
LA0
0
DDR port direction
register
− :
:
:
0 :
1 :
Set the bit corresponding to the pin used for DTP/external interrupt input to "0".
Unused bit
Used bit
Set the bit corresponding to used pin to "1"
Set 0
Set 1
● Setting procedure
To use the DTP/external interrupt, set each register by using the following procedures:
1. Set the pin used as the external interrupt pin and the general-purpose I/O port to the input port.
2. Set the interrupt request enable bit corresponding to the DTP/external interrupt channel to be used to "0"
(ENIR: EN).
3. Use the detection condition select bit corresponding to the DTP/external interrupt pin and the RX pin to
be used to set the edge or level to be detected (ELVR: LA, LB).
4. Set the interrupt request flag bit corresponding to the DTP/external interrupt channel to be used to "0"
(EIRR: ER).
5. Set the interrupt request enable bit corresponding to the DTP/external interrupt channel to be used to "1"
(ENIR: EN).
• When setting the registers for the DTP/external interrupt, the external interrupt request must be disabled
in advance (ENIR: EN = 0).
333
CHAPTER 12 DTP/EXTERNAL INTERRUPT
• To prevent the mistaken interrupt request from occurring when setting the register, the corresponding
DTP/external interrupt request flag bit must be cleared in advance (EIRR: ER = 0) when enabling the
DTP/external interrupt request (ENIR: EN = 1).
● Selecting of DTP or external interrupt function
Whether the DTP function or the external interrupt function is executed depends on the setting of the
EI2OS enable bit in the corresponding interrupt control register (ICR: ISE).
If the ISE bit is set to "1", the EI2OS is enabled and the DTP function is executed.
If the ISE bit is set to "0", the EI2OS is disabled and the external interrupt function is executed.
Notes:
• All interrupt requests assigned to one interrupt control register have the same interrupt levels (IL2
to IL0).
• If two or more interrupt requests are assigned to one interrupt control register and the EI2OS is
used in one of them, other interrupt requests cannot be used.
■ DTP/External Interrupt Operation
The control bits and the interrupt factors for the DTP/external interrupt are shown in Table 12.4-1.
Table 12.4-1 Control Bits and Interrupt Factors for DTP/External Interrupt
DTP/External Interrupt
Interrupt request flag bit
EIRR: ER7 to ER4, ER0
Interrupt request enable bit
ENIR: EN7 to EN4, EN0
Interrupt factor
Input of valid edge/level to INT7 to INT4, RX pins
If the interrupt request from the DTP/external interrupt is output to the interrupt controller and the EI2OS
enable bit in the interrupt control register (ICR: ISE) is set to "0", the interrupt processing is executed. This
bit is set to "1", the EI2OS is executed.
334
CHAPTER 12 DTP/EXTERNAL INTERRUPT
Figure 12.4-2 shows the operation of the DTP/external interrupt.
Figure 12.4-2 Operation of DTP/External Interrupt
DTP/external
interrupt circuit
Other request Interrupt controller
CPU
ELVR
ICR YY
EIRR
IL
CMP
CMP
ICR XX
ENIR
ILM
Interrupt
processing
Factor
EI2OS starts
DTP/external interrupt
request generated
Transfer data between
memory and resource
Update descriptor
Acceptance determined
by interrupt controller
Descriptor
data counter
Interrupt acceptance
determined by CPU
=0
Interrupt processing
≠0
Reset or stop
Return from DTP processing
Start interrupt
processing microprogram
ICR : ISE
Return from EI2OS
processing (DTP processing)
1
0
Start external interrupt
Clear processing and interrupt flag
Return from external interrupt
335
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.4.1
External Interrupt Function
The DTP/external interrupt has an external interrupt function for generating an interrupt
request by detecting the signal (edge or level) in the DTP/external interrupt pin and the
RX pin.
■ External Interrupt Function
• When the signal (edge or level) set in the detection level setting register is detected in the DTP/external
interrupt pin and the RX pin, the interrupt request flag bit in the DTP/external interrupt factor register
(EIRR: ER) is set to "1".
• If the interrupt request enable bit in the DTP/external interrupt enable register is enabled (ENIR: EN =
1) and the interrupt request flag bit set to "1", the interrupt is implemented to the interrupt controller.
• If an interrupt request is preferred to other interrupt request by the interrupt controller, the interrupt
request is generated.
• If the level of an interrupt request (ICR: IL) is higher than that of the interrupt level mask bit (TLM) in
the processor status (PS) and the interrupt enable bit is enabled (PS: CCR: I = 1), the CPU performs
interrupt processing after completion of the current instruction execution and branches to interrupt
processing.
• At interrupt processing, set the corresponding DTP/external interrupt request flag bit to "0" and clear the
DTP/external interrupt request.
Notes:
• When the DTP/external interrupt start factor is generated, the DTP/external interrupt request flag
bit (EIRR: ER) is set to "1", regardless of the setting of the DTP/external interrupt request enable
bit (ENIR: EN).
• When the interrupt processing is started, clear the DTP/external interrupt request flag bit that
caused the start factor. Control cannot be returned from the interrupt while the DTP/external
interrupt request flag bit is set to "1". When clearing, do not clear any flag bit other than the
accepted DTP/external interrupt factor.
336
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.4.2
DTP Function
The DTP/external interrupt has the DTP function that detects the signal of the external
peripheral device from the DTP/external interrupt pin and the RX pin to start the EI2OS.
■ DTP Function
The DTP function detects the signal level set by the detection level setting register of the DTP/external
interrupt function to start the EI2OS.
• When the EI2OS operation is already enabled (ICR: ISE = 1) at the point when the interrupt request is
accepted by the CPU, the DTP function starts the EI2OS and starts data transfer.
• When transfer of one data item is completed, the descriptor is updated and the DTP/external interrupt
request flag bit is cleared to prepare for the next request from the DTP/external interrupt pin and the RX
pin.
• When the EI2OS completes transfer of all the data, control branches to the interrupt processing.
Figure 12.4-3 Example of Interface with External Peripheral Device
High level request (ELVR : LB4, LA4 = 01B)
Input to INT4 pin
(DTP factor)
Internal operation of CPU
Descriptor
selected/read
Peripheral
device
externalconnected
Internal data bus
Read/Write
operation*2
DTP factor*1
Data transfer
request
Descriptor
updated
Interrupt
INT DTP/external request
interrupt circuit
CPU
(EI2OS)
Internal
memory
*1: This must be cancelled within three machine cycles after the start of data transfer.
*2: When EI2OS is "peripheral function → internal memory transfer".
337
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.5
Precautions when Using DTP/External Interrupt
This section explains the precautions when using the DTP/external interrupt.
■ Precautions when Using DTP/External Interrupt
● Condition of external-connected peripheral device when DTP function is used
• When using the DTP function, the peripheral device must automatically clear a data transfer request
when data transfer is performed.
• Inactivate the transfer request signal within three machine cycles after starting data transfer. If the
transfer request signal remains active, the DTP/external interrupt regards the transfer request signal as a
generation of next transfer request.
● External interrupt input polarity
• When the edge detection is set in the detection level setting register, the pulse width for edge detection
must be at least three machine cycles.
• When a level causing an interrupt factor is input with level detection set in the detection level setting
register, the interrupt request flag bit (EIRR:ER) of the DTP/external interrupt factor register is set to
"1" and the factor is held as shown in Figure 12.5-1.
With the factor held in the interrupt request flag bit (EIRR:ER), the request to the interrupt controller
remains active if the interrupt request is enabled (ENIR: EN = 1) even after the DTP/external interrupt
factor is canceled. To cancel the request to the interrupt controller, clear the interrupt request flag bit
(EIRR:ER) as shown in Figure 12.5-2.
Figure 12.5-1 Clearing Interrupt Request Flag Bit (EIRR:ER) when Level Set
DTP/external
interrupt factor
DTP/interrupt input
detector
Interrupt Request
Flag Bit (EIRR:ER)
Enable gate
To interrupt
controller
(interrupt request)
The factor remains held unless cleared.
Figure 12.5-2 DTP/External Interrupt Factor and Interrupt Request Generated when
Interrupt Request Enabled
DTP/external interrupt factor
(when "H" level detected)
Interrupt factor canceled
Interrupt request issued
to interrupt controller
The interrupt request is inactived by clearing
the interrupt request flag bit (EIRR:ER)
338
CHAPTER 12 DTP/EXTERNAL INTERRUPT
● Precautions on interrupts
• When the DTP/external interrupt is used as the external interrupt function, no return from interrupt
processing can be made with the DTP/external interrupt request flag bit set to "1" (EIRR: ER) and the
DTP/external interrupt request set to "enabled" (ENIR: EN = 1). Always set the DTP/external interrupt
request flag bit to "0" (EIRR: ER) at interrupt processing.
• When the level detection is set in the detection level setting register and the level that becomes the
interrupt factor remains input, the DTP/external interrupt request flag bit is reset immediately even when
cleared (EIRR: ER = 0). Disable the DTP/external interrupt request output as needed (ENIR: EN = 0), or
cancel the interrupt factor itself.
339
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.6
Program Example of DTP/External Interrupt Circuit
This section gives a program example of the DTP/external interrupt function.
■ Program Example of DTP/External Interrupt Function
● Processing specifications
An external interrupt is generated by detecting the rising edge of the pulse input to the INT4 pin.
● Coding example
ICR06
EQU 0000B6H
; DTP/external interrupt control register
DDR2
EQU 000012H
; Port 2 direction register
ENIR
EQU 000030H
; DTP/external interrupt enable register
EIRR
EQU 000031H
; DTP/external interrupt factor register
ELVRL
EQU 000032H
; Detection level setting register: L
ELVRH
EQU 000033H
; Detection level setting register: H
ER0
EQU EIRR:0
; INT4 Interrupt request flag bit
EN0
EQU ENIR:0
; INT4 Interrupt request enable bit
;
;-----Main program--------------------------------------------------------------CODE
CSEG
START:
; Stack pointer (SP) already initialized
MOV I:DDR2,#00000000B ; DDR2 set to input port
AND CCR,#0BFH
; Interrupts disabled
MOV I:ICR06,#00H
; Interrupt level 0 (highest)
CLRB I:ER4
; INT4 disabled using ENIR
MOV I:ELVRL,#00000010B ; Rising edge selected for INT4
CLRB I:ER4
; INT4 interrupt request flag
; cleared using EIRR
SETB I:EN4
; INT4 interrupt request enabled using ENIR
MOV ILM, #07H
; ILM in PS set to level 7
OR
CCR, #40H
; Interrupts enabled
LOOP:
·
Processing by user
·
BRA LOOP
;-----Interrupt program---------------------------------------------------------WARI:
CLRB I:ER4
; Interrupt request flag cleared
·
Processing by user
·
RETI
; Return from interrupt processing
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG 00FFC0H
; Vector set to interrupt number #15 (0FH)
DSL WARI
ORG 00FFDCH
; Reset vector set
DSL START
DB
00H
; Set to single-chip mode
VECT
ENDS
END START
340
CHAPTER 12 DTP/EXTERNAL INTERRUPT
■ Program Example of DTP Function
● Processing specification
• Ch. 0 of the EI2OS is started by detecting the "H" level of the signal input to the INT4 pin.
• RAM data is output to port 1 by performing DTP processing (EI2OS).
● Coding example
ICR06
EQU 0000B6H
; DTP/external interrupt control register
DDR1
EQU 000011H
; Port 1 direction register
DDR5
EQU 000015H
; Port 5 direction register
ENIR
EQU 000030H
; DTP/external interrupt enable register
EIRR
EQU 000031H
; DTP/external interrupt factor register
ELVRL
EQU 000032H
; Detection level setting register: L
ELVRH
EQU 000033H
; Detection level setting register: H
ER4
EQU EIRR:0
; INT4 interrupt request flag bit
EN4
EQU ENIR:0
; INT4 interrupt request enable bit
;
BAPL
EQU 000100H
; Buffer address pointer lower
BAPM
EQU 000101H
; Buffer address pointer middle
BAPH
EQU 000102H
; Buffer address pointer higher
ISCS
EQU 000103H
; EI2OS status register
IOAL
EQU 000104H
; I/O address register lower
IOAH
EQU 000105H
; I/O address register higher
DCTL
EQU 000106H
; Data counter lower
DCTH
EQU 000107H
; Data counter higher
;
;-----Main program--------------------------------------------------------------CODE
CSEG
START:
; Stack pointer (SP) already initialized
MOV I:DDR1,#11111111B ; DDR1 set to output port
MOV I:DDR5,#00000000B ; DDR5 set to input port
AND CCR,#0BFH
; Interrupts disabled
MOV I:ICR06,#08H
; Interrupt level 0 (highest) EI2OS
; Channel 0
;
; Data bank register (DTB) = 00H
;
MOV BAPL,#00H
; Address for storing output data set
MOV BAPM,#06H
; (600H to 60AH used)
MOV BAPH,#00H
MOV ISCS,#12H
; Byte transfer, buffer address + 1
; I/O address fixed,
; transfer from memory to I/O
MOV IOAL,#00H
; Port 0 (PDR0) set as
MOV IOAH,#00H
; transfer destination address pointer
MOV DCTL,#0AH
; Transfer count set to 10
MOV DCTH,#00H
;
CLRB I:EN4
; INT4 disabled using ENIR
MOV I:ELVRL,#00010000B; H level detection set for INT4
CLRB I:ER4
; INT4 interrupt request flag cleared using EIRR
SETB I:EN4
; INT4 interrupt request enabled using ENIR
MOV ILM,#07H
; ILM in PS set to level 7
OR
CCR,#40H
; Interrupts enabled
341
CHAPTER 12 DTP/EXTERNAL INTERRUPT
LOOP:
·
Processing by user
·
BRA
LOOP
;-----Interrupt program---------------------------------------------------------WARI:
CLRB
I:ER4
; INT4 interrupt request flag cleared
·
Processing by user
·
RETI
; Return from interrupt processing
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS = 0FFH
ORG 00FF9CH
; Vector set to interrupt number #24 (18H)
DSL WARI
ORG 00FFDCH
; Reset vector set
DSL START
DB
00H
; Set to single-chip mode set
VECT
ENDS
END START
342
CHAPTER 13
8-/10-BIT A/D CONVERTER
This chapter explains the functions and operation of
8-/10-bit A/D converter.
13.1 Overview of 8-/10-bit A/D Converter
13.2 Block Diagram of 8-/10-bit A/D Converter
13.3 Configuration of 8-/10-bit A/D Converter
13.4 Interrupt of 8-/10-bit A/D Converter
13.5 Explanation of Operation of 8-/10-bit A/D Converter
13.6 Precautions when Using 8-/10-bit A/D Converter
343
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.1
Overview of 8-/10-bit A/D Converter
The 8-/10-bit A/D converter converts the analog input voltage to a 8- or 10-bit digital
value by using the RC sequential-comparison converter system.
• An input signal can be selected from the input signals of the analog input pins for 8
channels.
• The start trigger can be selected from a software trigger, internal timer output, and an
external trigger.
■ Function of 8-/10-bit A/D Converter
The 8-/10-bit A/D converter converts the analog voltage (input voltage) input to the analog input pin into
an 8- or 10-bit digital value (A/D conversion).
The 8-/10-bit A/D converter has the following functions:
• A/D conversion time is a minimum of 6.12 μs*per channel including sampling time.
• Sampling time is a minimum of 2.0 μs per channel.*
• RC sequential-comparison converter system with sample & hold circuit
• Setting of 8-bit or 10-bit resolution enabled
• Analog input pin can be used up to 8 channels.
• Generates interrupt request by storing A/D conversion results in A/D data register
• Starts EI2OS if interrupt request generated. Use of the EI2OS prevents data loss even at continuous
conversion.
• Selects start trigger from software trigger, internal timer output, and external trigger (falling edge)
*: When the machine clock frequency operates at 16 MHz
■ Conversion Modes of 8-/10-bit A/D Converter
There are conversion modes of 8-/10-bit A/D converter as shown below:
Table 13.1-1 Conversion Modes of 8-/10-bit A/D Converter
344
Conversion
Mode
Description
Single conversion
mode
A/D conversion is performed sequentially from the start channel to the end channel.
When A/D conversion for the end channel is terminated, it stops.
Continuous
conversion mode
A/D conversion is performed sequentially from the start channel to the end channel.
When A/D conversion for the end channel is terminated, it is continued after
returning to the start channel.
Pause-conversion
mode
A/D conversion is performed sequentially from the start channel to the end channel.
When A/D conversion for the end channel is terminated, A/D conversion and pause
are repeated after returning to the start channel.
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.2
Block Diagram of 8-/10-bit A/D Converter
The 8-/10-bit A/D converter consists of following blocks.
■ Block Diagram of 8-/10-bit A/D Converter
Figure 13.2-1 Block Diagram of 8-/10-bit A/D Converter
A/D control
Interrupt request output
status register
(ADCS)
BUSY INT INTE PAUS STS1 STS0 STRT Reserved MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
2
2
Start selector
Decoder
Internal data bus
ADTG
TO
6
φ
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Sample & hold
circuit
Comparator
Controller
Analog
channel
selector
AVR
AVcc
AVss
D/A converter
2
2
A/D data
register
(ADCR) S10 ST1 ST0 CT1 CT0 ⎯
TO
:
⎯
:
Reserved :
φ
:
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Internal timer output
Unused
Always set to 0
Machine clock
345
CHAPTER 13 8-/10-BIT A/D CONVERTER
● Details of pins in block diagram
Table 13.2-1 shows the actual pin names and interrupt request numbers of the 8-/10-bit A/D converter
Table 13.2-1 Pins and Interrupt Request Numbers in Block Diagram
Pin Name/Interrupt Request Number in
Block Diagram
ADTG
Actual Pin Name/Interrupt Request Number
Trigger input pin
P37/ADTG
Internal timer output
TO (16-bit reload timer, 16-bit free-run timer)
AN0
Analog input pin ch. 0
P50/AN0
AN1
Analog input pin ch. 1
P51/AN1
AN2
Analog input pin ch. 2
P52/AN2
AN3
Analog input pin ch. 3
P53/AN3
AN4
Analog input pin ch. 4
P54/AN4
AN5
Analog input pin ch. 5
P55/AN5
AN6
Analog input pin ch. 6
P56/AN6
AN7
Analog input pin ch. 7
P57/AN7
AVR
Vref+ Input pin
AVR
AVCC
VCC Input pin
AVCC
AVSS
VSS Input pin
AVSS
TO
Interrupt
request output
#18 (12H)
● A/D control status registers (ADCS)
This register starts the A/D conversion function by software, selects the start trigger for the A/D conversion
function, selects the conversion mode, enables or disables an interrupt request, checks and clears the
interrupt request flag, temporarily stops A/D conversion and checks the state during conversion, and sets
the start and end channels for A/D conversion.
● A/D data registers (ADCR)
This register stores the A/D conversion results, and selects the comparison time, sampling time, and
resolution of A/D conversion.
● Start selector
This selector selects the trigger to start A/D conversion. An internal timer output or external pin input can
be set as the start trigger.
346
CHAPTER 13 8-/10-BIT A/D CONVERTER
● Decoder
This decoder sets the A/D conversion start channel select bits and the A/D conversion end channel select
bits in the A/D control status register (ADCS: ANS2 to ANS0 and ANE2 to ANE0) to select the analog
input pin to be used for A/D conversion.
● Analog channel selector
This selector selects the pin to be used for A/D conversion from the 8-channel analog input pins by
receiving a signal from the decoder.
● Sample & hold circuit
This circuit holds the input voltage selected by the analog channel selector. By holding the input voltage
immediately after A/D conversion is started, A/D conversion is performed without being affected by the
fluctuation of the input voltage during A/D conversion.
● D/A converter
This converter generates the reference voltage which is compared with the input voltage held in the sample
& hold circuit.
● Comparator
This comparator compares the D/A converter output voltage with input voltage held in the sample & hold
circuit to determine the mount of voltage.
● Controller
This circuit determines the A/D conversion value by receiving the signal indicating the amount of voltage
determined by the comparator. When the A/D conversion results are determined, the result data is stored in
the A/D data register. If an interrupt request is enabled, an interrupt is generated.
347
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.3
Configuration of 8-/10-bit A/D Converter
This section explains the pins, registers, and interrupt factors of the A/D converter.
■ Pins of 8-/10-bit A/D Converter
The pins of the 8-/10-bit A/D converter serve as general-purpose I/O ports. Table 13.3-1 shows the pin
functions and the setting required for use of the 8-/10-bit A/D converter.
Table 13.3-1 Pins of 8-/10-bit A/D Converter
Function
Used
Pin
Name
Trigger input
ADTG
ch. 0
AN0
ch. 1
AN1
ch. 2
AN2
ch. 3
AN3
ch. 4
AN4
ch. 5
AN5
ch. 6
AN6
ch. 7
AN7
Pin Function
General-purpose I/O port,
external trigger input
Set as input port in port direction register
(DDR).
General-purpose I/O ports,
analog inputs
Set as input ports in port direction register
(DDR).
Input of analog signal enabled
(ADER: ADE7 to ADE0 = 11111111B)
Reference:
See CHAPTER 4 "I/O PORT" for the block diagram of pins.
348
Setting Required for Use of
8-/10-bit A/D Converter
CHAPTER 13 8-/10-BIT A/D CONVERTER
■ List of Registers and Reset Values of 8-/10-bit A/D Converter
Figure 13.3-1 Register and Reset Value of 8-/10-bit A/D Converter
bit
A/D control status register (High)
(ADCS: H)
bit
A/D control status register (Low)
(ADCS: L)
bit
A/D data register (High)
(ADCR: H)
bit
A/D data register (Low)
(ADCR: L)
bit
Analog input enable register (ADER)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
1
0
1
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
X: Undefined
■ Generation of Interrupt from 8-/10-bit A/D Converter
In the 8-/10-bit A/D converter, when the A/D conversion results are stored in the A/D data register
(ADCR), the interrupt request flag bit in the A/D control status register (ADCS: INT) is set to "1". When an
interrupt request is enabled (ADCS: INTE = 1), an interrupt is generated.
349
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.3.1
A/D Control Status Register (High) (ADCS: H)
The A/D control status register (High) (ADCS: H) provides the following settings:
• Starting A/D conversion function by software
• Selecting start trigger for A/D conversion
• Storing A/D conversion results in A/D data register to enable or disable interrupt
request
• Storing A/D conversion results in A/D data register to check and clear interrupt
request flag
• Pausing A/D conversion and checking state during conversion
■ A/D Control Status Register (High) (ADCS: H)
Figure 13.3-2 A/D Control Status Register (High) (ADCS: H)
Address:
000035H
15
14
13
12
11
10
9
8
Reset value
00000000 B
R/W R/W R/W R/W R/W R/W
W R/W
bit 8
Reserved bit
Reserved
0
Always set to "0"
bit 9
A/D conversion software start bit
STRT
0
Does not start A/D conversion
1
Starts A/D conversion
bit 11 bit 10
STS1 STS0
0
0
1
0
0
1
1
1
A/D conversion start trigger select bit
Starts software
Starts software or external trigger
Starts software or internal timer
Starts software, external trigger, or internal timer
bit 12
PAUS
0
1
Pause flag bit
(This bit is enabled only when EI2OS is used)
A/D conversion does not pause
A/D conversion pauses
bit 13
Interrupt request enable bit
INTE
Interrupt request disable
0
Interrupt request enable
1
bit 14
INT
0
1
Interrupt request flag bit
Read
A/D conversion not terminated
A/D conversion terminated
Write
Clear to "0"
No effect
bit 15
BUSY
R/W : Read/Write
: Reset value
350
0
1
A/D conversion-on flag bit
Read
Write
A/D conversion terminated (inactive state) Terminates A/D conversion forcibly
A/D conversion in operation No effect
CHAPTER 13 8-/10-BIT A/D CONVERTER
Table 13.3-2 Function of Each Bit of A/D Control Status Register (High) (ADCS: H)
Bit Name
Function
bit 15
BUSY:
A/D conversion-on flag bit
This bit forcibly terminates the 8-/10-bit A/D converter. When read, this bit indicates
whether the 8-/10-bit A/D converter is operating or stopped.
When set to "0": Forcibly terminates 8-/10-bit A/D converter
When set to "1": No effect
Read: "1" is read when the 8-/10-bit A/D converter is operating and "0" is written when the
converter is stopped.
Note: Do not perform forcibly termination (BUSY=0) and software start (STRT=1) of the
8-/10-bit A/D converter simultaneously.
bit 14
INT:
Interrupt request flag bit
This bit indicates that an interrupt request is generated.
• When A/D conversion is terminated and its results are stored in the A/D data register
(ADCR), the INT bit is set to "1".
• When the interrupt request flag bit is set (INT = 1) with an interrupt request enabled
(INTE = 1), an interrupt request is generated.
When set to "0": Cleared
When set to "1": No effect
When EI2OS function started: Cleared
Note: To clear the INT bit, write 0 when the 8-/10-bit A/D converter is stopped.
bit 13
INTE:
Interrupt request enable bit
This bit enables or disables output of an interrupt request.
• When the interrupt request flag bit is set (INT=1) with an interrupt request enabled
(INTE = 1), an interrupt request is generated.
Note: Always set this bit to "1" when the EI2OS function is used.
bit 12
PAUS:
Pause flag bit
This bit indicates the A/D conversion operating state when the EI2OS function is used.
• The PAUS bit is enabled only when the EI2OS function is used.
• A/D conversion pauses while the A/D conversion results are transferred from the A/D
data register (ADCR) to memory. When A/D conversion pauses, the PAUS bit is set to
"1".
• After transfer of the A/D conversion results to memory, the 8-/10-bit A/D converter
automatically resumes A/D conversion. Even if state of temporary stop is released, this
bit is not cleared. Please write "0" to clear this bit.
bit 11,
bit 10
STS1, STS0:
A/D conversion start trigger
select bits
These bits select the trigger to start the 8-/10-bit A/D converter.
If two or more start triggers are set (STS1, STS0 = "00B"), the 8-/10-bit A/D converter is
started by the first-generated start trigger.
Note: Start trigger setting should be changed when the operation of resource generating a
start trigger is stopped.
STRT:
A/D conversion software
start bit
This bit starts the 8-/10-bit A/D converter by software.
When set to "1": Starts 8-/10-bit A/D converter
bit 9
If A/D conversion pauses in the pause-conversion mode, it is resumed by writing
1 to the STRT bit.
When set to "0": Invalid. The state remains unchanged.
Read: The byte/word command reads "1". The read-modify-write (RMW) instructions
read "0".
Note: Do not perform forcible termination (BUSY = 0) and software start (STRT = 1) of
the 8-/10-bit A/D converter simultaneously.
bit 8
Reserved: Reserved bit
Always set this bit to "0".
351
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.3.2
A/D Control Status Register (Low) (ADCS: L)
The A/D control status register (Low) (ADCS: L) provides the following settings:
• Selecting A/D conversion mode
• Selecting start channel and end channel of A/D conversion
■ A/D Control Status Register (Low) (ADCS: L)
Figure 13.3-3 A/D Control Status Register Low (ADCS: L)
Address:
000034H
7
6
5
4
3
2
1
0
Reset value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 2 bit 1 bit 0
ANE2 ANE1 ANE0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
A/D conversion end channel select bits
AN0 pin
AN1 pin
AN2 pin
AN3 pin
AN4 pin
AN5 pin
AN6 pin
AN7 pin
bit 5 bit 4 bit 3
A/D conversion start channel select bits
ANS2 ANS1 ANS0
R/W : Read/Write
: Reset value
352
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
bit 7 bit 6
MD1 MD0
0
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
Inactive state
AN0 pin
AN1 pin
AN2 pin
AN3 pin
AN4 pin
AN5 pin
AN6 pin
AN7 pin
Read during
Read during a pause in stop
a conversion conversion mode
Channel number Channel number
currently being just previously
converted
converted
A/D conversion mode select bits
Single conversion mode 1 (restartable during conversion)
Single conversion mode 2 (not-restartable during conversion)
Continuous conversion mode (not-restartable during conversion)
Pause-conversion mode (not-restartable during conversion)
CHAPTER 13 8-/10-BIT A/D CONVERTER
Table 13.3-3 Function of Each Bit of A/D Control Status Register (Low) (ADCS: L) (1/2)
Bit Name
bit 7,
bit 6
MD1, MD0:
A/D conversion mode
select bits
Function
These bits set the A/D conversion mode.
Single conversion mode 1:
• The analog inputs from the start channel (ADCS: ANS2 to ANS0) to the end channel
(ADCS: ANE2 to ANE0) are A/D-converted continuously.
• The A/D conversion pauses after A/D conversion for the end channel.
• This mode can be restarted during A/D conversion.
Single conversion mode 2:
• The analog inputs from the start channel (ADCS: ANS2 to ANS0) to the end channel
(ADCS: ANE2 to ANE0) are A/D-converted continuously.
• The A/D conversion after A/D conversion for the end channel.
• This mode cannot be restarted during A/D conversion.
Continuous conversion mode:
• The analog inputs from the start channel (ADCS: ANS2 to ANS0) to the end channel
(ADCS: ANE2 to ANE0) are A/D-converted continuously.
• When A/D conversion for the end channel is terminated, it is continued after returning to
the analog input for the start channel.
• To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D
control status register (ADCS: BUSY).
• This mode cannot be restarted during A/D conversion.
Pause conversion mode:
• A/D conversion for the start channel (ADCS: ANS2 to ANS0) starts. The A/D conversion
pauses at termination of A/D conversion for a channel. When the start trigger is input while
A/D conversion pauses, A/D conversion for the next channel is started.
• The A/D conversion pauses at the termination of A/D conversion for the end channel.
When the start trigger is input while A/D conversion pauses, A/D conversion is continued
after returning to the analog input for the start channel.
• To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D
control status register (ADCS: BUSY).
• This mode cannot be restarted during A/D conversion.
Note: When the conversion mode is set to "not restartable" (MD1, MD0 = 00B), it cannot be
restarted with any start triggers (software trigger, internal timer, and external trigger)
during A/D conversion.
353
CHAPTER 13 8-/10-BIT A/D CONVERTER
Table 13.3-3 Function of Each Bit of A/D Control Status Register (Low) (ADCS: L) (2/2)
Bit Name
Function
bit 5 to bit 3
ANS2 to ANS0:
A/D conversion start
channel select bits
These bits set the channel at which A/D conversion start. At read, the channel number under A/
D conversion or A/D-converted immediately before A/D conversion pauses can be checked.
And before A/D conversion starts, the previous conversion channel number will be read even if
these bits have been already set to the new value. These bits are initialized to "000B" at reset.
Start channel < end channel: A/D conversion starts at channel set by A/D conversion start
channel select bits (ANS2 to ANS0) and terminates at channel
set by A/D conversion end channel select bits (ANE2 to
ANE0).
Start channel = end channel: A/D conversion is performed only for one channel set by A/D
conversion (= end) channel select bits (ANS2 to ANS0 =
ANE2 to ANE0).
Start channel > end channel: A/D conversion is performed from channel set by A/D
conversion start channel select bits (ANS2 to ANS0) to AN7,
and from AN0 to channel set by A/D conversion end channel
select bits (ANE2 to ANE0).
Continuous conversion mode and pause-conversion mode:
When A/D conversion terminates at the channel set by the A/D conversion end channel
select bits (ANE2 to ANE0), it returns to the channel set by the A/D conversion start
channel select bits (ANS2 to ANS0).
Read (During A/D conversion):The channel numbers (7 to 0) under A/D conversion are read.
Read (During Pause-conversion mode and temporary stop):
At read during a pause, the channel number A/D-converted immediately before a pause is
read.
Note: • Do not set the A/D conversion start channel bits (ANS2 to ANS0) during A/D
conversion.
• Do not set this register bit by the read modify write instructions after setting the start
channel in the A/D conversion start channel select bits (ANS2, ANS1, ANS0). The
last conversion channels are read until the A/D conversion starts operating. Therefore,
if this register bit is set by the read modify write instructions, the bit values of ANE2,
ANE1, ANE0 could be rewritten.
bit 2 to bit 0
ANE2 to ANE0:
A/D conversion end
channel select bits
These bits set the channel at which A/D conversion is terminated.
Start channel < end channel: A/D conversion starts at channel set by A/D conversion start
channel select bits (ANS2 to ANS0) and terminates channel
set by A/D conversion end channel select bits (ANE2 to
ANE0)
Start channel = end channel: A/D conversion is performed only for one channel set by A/D
converter end (= start) channel select bits (ANE2 to ANE0 =
ANS2 to ANS0).
Start channel > end channel: A/D conversion is performed from channel set by A/D
conversion start channel select bits (ANS2 to ANS0) to AN7,
and from AN0 to channel set by A/D conversion end channel
select bits (ANE2 to ANE0).
Continuous conversion mode and pause-conversion mode:
When A/D conversion terminated at the channel set by the A/D conversion end channel
select bits (ANE2 to ANE0), it returns to the channel set by the A/D conversion start
channel select bits (ANS2 to ANS0).
Note: Do not set the A/D conversion end channel select bits (ANE2 to ANE0) during A/D
conversion.
354
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.3.3
A/D Data Register (High) (ADCR: H)
The higher five bits in the A/D data register (ADCR: H) select the compare time,
sampling time and resolution of A/D conversion.
Bits 9 and 8 in the A/D data register (ADCR) are explained in Section "13.3.4 A/D Data
Register (Low) (ADCR: L)".
■ A/D Data Register (High) (ADCR: H)
Figure 13.3-4 A/D Data Register (High) (ADCR: H)
Address: 15
000037H
14
13
12
11
10
9
*
*
W
W
W
W
W
⎯
R
R
8
Reset value
00101XXX B
bit 12 bit 11
CT1 CT0
0
0
0
1
1
0
1
1
bit 14 bit 13
ST1 ST0
0
0
1
1
R
W
X
⎯
φ
:
:
:
:
:
:
Read only
Write only
Undefined
Unused
Machine clock
Reset value
0
1
0
1
Compare time select bits
44/φ (5.5 μs)*1
66/φ (4.12 μs)*2
88/φ (5.5 μs)*2
176/φ (11.0 μs)*2
Sampling time select bits
20/φ (2.5 μs)*1
32/φ (2.0 μs)*2
48/φ (3.0 μs)*2
128/φ (8.0 μs)*2
bit 15
Resolution select bits
S10
10
bits
(D9
to
D0)
0
8 bits (D7 to D0)
1
*1 : The parenthesized values are provided when the machine clock operates at 8-MHz.
*2 : The parenthesized values are provided when the machine clock operates at 16-MHz.
* : Bit 8 and bit 9 are explained in "A/D Data Register (Low) (ADCR: L)".
355
CHAPTER 13 8-/10-BIT A/D CONVERTER
Table 13.3-4 Functions of A/D Data Register (High) (ADCR: H)
Bit Name
Function
bit 15
S10:
Resolution select bit
This bit selects the A/D conversion resolution.
When set to "0":Sets A/D conversion resolution in 10 bits from A/D conversion
data bits D9 to D0.
When set to "1":Sets A/D conversion resolution in 8 bits from A/D conversion
data bits D7 to D0.
Note: Change the S10 bit in the pausing state before starting A/D conversion.
Changing the S10 bit after A/D conversion starts disables the A/D
conversion results stored in the A/D conversion data bits (D9 to D0).
bit 14,
bit 13
ST1, ST0:
Sampling time select bits
These bits set the A/D conversion sampling time.
These bits set the time required from when A/D conversion starts until the input
analog voltage is sampled and held by the sample & hold circuit.
Note: The setting of ST1 and ST0 = 00B is based on operation at 8 MHz. Setting
based on operation at 16 MHz does not assure normal operation. When
these bits are read, "00B" is read.
bit 12,
bit 11
CT1, CT0:
Compare time select bits
These bits set the A/D conversion compare time.
These bits set the time required from when analog input is A/D-converted until it
is stored in the data bits (D9 to D0).
Note: The setting of CT1 and CT0 = 00B is based on operation at 8 MHz. Setting
based on operation at 16 MHz does not assure normal operation. When
these bits are read, "00B" is read.
356
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.3.4
A/D Data Register (Low) (ADCR: L)
The A/D data register (Low) (ADCR: L) stores the A/D conversion results.
Bits 8 and 9 in the A/D data register (ADCR) are explained in this section.
■ A/D Data Register (Low) (ADCR: L)
Figure 13.3-5 A/D Data Register (Low) (ADCR: L)
Address:
000036H
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
D9
R
D8
R
D7
R
D6
R
D5
R
D4
R
D3
R
D2
R
D1
R
D0
R
Reset value
XXXXXXXXB
R: Read only
X: Undefined
Table 13.3-5 Functions of A/D Data Register (Low) (ADCR: L)
Bit Name
bit 9 to bit 0
D9 to D0:
A/D conversion data bits
Function
These bits store the A/D conversion results.
When resolution set in 10 bits (S10 = 0):Conversion data is stored in the 10
bits from D9 to D0.
When resolution set in 8 bits (S10 = 1): Conversion data is stored in the 8
bits from D7 to D0.
Note: Use a word instruction (MOVW) to read the A/D conversion results
stored in the A/D conversion data bits (D9 to D0).
357
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.3.5
Analog Input Enable Register (ADER)
The analog input enable register (ADER) enables or disables the analog input pins to be
used in the 8-/10-bit A/D converter.
■ Analog Input Enable Register (ADER)
Figure 13.3-6 Analog Input Enable Register (ADER)
Address:
00001BH
7
6
5
4
3
2
1
0
Reset value
11111111 B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
Analog input enable bit 0 (AN0)
ANE0
Analog input disable
0
Analog input enable
1
bit 1
Analog input enable bit 1 (AN1)
ANE1
Analog input disable
0
Analog input enable
1
bit 2
Analog input enable bit 2 (AN2)
ANE2
Analog input disable
0
Analog input enable
1
bit 3
Analog input enable bit 3 (AN3)
ANE3
Analog input disable
0
Analog input enable
1
bit 4
Analog input enable bit 4 (AN4)
ANE4
Analog input disable
0
Analog input enable
1
bit 5
Analog input enable bit 5 (AN5)
ANE5
Analog input disable
0
Analog input enable
1
bit 6
Analog input enable bit 6 (AN6)
ANE6
Analog
input
disable
0
Analog
input
enable
1
R/W : Read/Write
: Reset value
358
bit 7
Analog input enable bit 7 (AN7)
ANE7
Analog input disable
0
Analog input enable
1
CHAPTER 13 8-/10-BIT A/D CONVERTER
Table 13.3-6 Functions of Analog Input Enable Register (ADER)
Bit Name
bit 7 to bit 0
ADE7 to ADE0:
Analog input enable bits
Function
These bits enable or disable the analog input of the pin to be used for A/D
conversion.
When set to "0": Disables analog input
When set to "1": Enables analog input
Notes:
• The analog input pins serve as a general-purpose I/O port of the port 5. When using the pin as an
analog input pin, switch the pin to analog input pin according to the setting of the port 5 direction
register (DDR5) and the analog input enable register (ADER).
• When using the pin as an analog input pin, write 0 to the bit in the port 5 direction register (DDR5)
corresponding to the pin to be used and turn off the output transistor. Also write 1 to the bit in the
analog input enable register (ADER) corresponding to the pin to be used and set the pin to analog
input.
359
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.4
Interrupt of 8-/10-bit A/D Converter
When A/D conversion is terminated and its results are stored in the A/D data register
(ADCR), the 8-/10-bit A/D converter generates an interrupt request. The EI2OS function
can be used.
■ Interrupt of A/D Converter
When A/D conversion of the analog input voltage is terminated and its results are stored in the A/D data
register (ADCR), the interrupt request flag bit in the A/D control status register (ADCS: INT) is set to "1".
When the interrupt request flag bit is set (ADCS: INT = 1) with an interrupt request output enabled (ADCS:
INTE = 1), an interrupt request is generated.
■ 8-/10-bit A/D Converter Interrupt and EI2OS
See Section "3.5 Interrupt" for details of the interrupt number, interrupt control register, and interrupt
vector address.
■ EI2OS Function of 8-/10-bit A/D Converter
In the 8-/10-bit A/D converter, the EI2OS function can be used to transfer the A/D conversion results from
the A/D data register (ADCR) to memory. If the EI2OS function is used, the A/D-converted data protection
function is activated to cause A/D conversion to pause during memory transfer and prevent data loss as A/D
conversion is performed continuously.
360
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.5
Explanation of Operation of 8-/10-bit A/D Converter
The 8-/10-bit A/D converter has the following A/D conversion modes. Set each mode
according to the setting of the A/D conversion mode select bits in the A/D control status
register (ADCS: MD1, MD0).
• Single conversion mode (restartable/not-restartable during A/D conversion)
• Continuous conversion mode (not-restartable during A/D conversion)
• Pause conversion mode (not-restartable during A/D conversion)
■ Single Conversion Mode (ADCS: MD1, MD0 = 00B or 01B)
• When the start trigger is input, the analog inputs from the start channel (ADCS: ANS2 to ANS0) to the
end channel (ADCS: ANE2 to ANE0) are A/D-converted continuously.
• The A/D conversion stops at the termination of the A/D conversion for the end channel.
• To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D control
status register (ADCS: BUSY).
• When the A/D conversion mode select bits (MD1, MD0) are set to "00B", this mode can be restarted
during A/D conversion. If the bits are set to "00B", this mode cannot be restarted during A/D conversion.
■ Continuous Conversion Mode (ADCS: MD1, MD0 = 10B)
• When the start trigger is input, the analog inputs from the start channel (ADCS: ANS2 to ANS0) to the
end channel (ADCS: ANE2 to ANE0) are A/D-converted continuously.
• When A/D conversion for the end channel is terminated, it is continued after returning to the analog
input for the start channel.
• To terminate A/D conversion forcibly, write "0" to the A/D conversion-on flag bit in the A/D control
status register (ADCS: BUSY).
• This mode cannot be restarted during A/D conversion.
■ Pause-conversion Mode (ADCS: MD1, MD0 = 11B)
• When the start trigger is input, A/D conversion starts for the start channel (ADCS: ANS2 to ANS0). The
A/D conversion pauses at the termination of A/D conversion for one channel. When the start trigger is
input while A/D conversion pauses, A/D conversion is performed for the next channel.
• The A/D conversion pauses at termination of A/D conversion for the end channel. When the start trigger
is input while A/D conversion pauses, A/D conversion is continued after returning to the analog input
for the start channel.
• To terminate A/D conversion forcibly, write "0" to the A/D conversion-on flag bit in the A/D control
status register (ADCS: BUSY).
• This mode cannot be restarted during A/D conversion.
361
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.5.1
Single Conversion Mode
In the Single conversion mode, A/D conversion is performed sequentially from the start
channel to the end channel. The A/D conversion stops at the termination of A/D
conversion for the end channel.
■ Setting of Single Conversion Mode
Operating the 8-/10-bit A/D converter in the Single conversion mode requires the setting shown in Figure
13.5-1.
Figure 13.5-1 Setting of Single Conversion Mode
bit15
ADCS
ADCR
BUSY
14
INT
13
INTE
12
PAUS
11
STS1
S10 ST1 ST0 CT1 CT0
10
9
STS0 STRT
bit 8
bit 7
6
Reserved
MD1
MD0
0
0
−
5
4
3
2
1
bit0
ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
D9 to D0(Converted data stored)
ADER
−: Undefined
: Used bit
: Set the bit corresponding to pin to be used as analog input pin to "1".
0: Set 0
■ Operation of Single Conversion Mode
• When the start trigger is input, A/D conversion starts from the channel set by the A/D conversion start
channel select bits (ANS2 to ANS0) and is performed continuously up to the channel set by the A/D
conversion end channel select bits (ANE2 to ANE0).
• The A/D conversion stops at the termination of the A/D conversion for the channel set by the A/D
conversion end channel select bits (ANE2 to ANE0).
• To terminate A/D conversion forcibly, write 0 to the A/D conversion-on flag bit in the A/D control
status register (ADCS: BUSY).
• When the A/D conversion mode select bits (MD1, MD0) are set to "00B", this mode can be restarted
during A/D conversion. If the bits are set to "01B", this mode cannot be restarted during A/D
conversion.
[When start and end channels are the same]
If the start and end channels have the same channel number (ADCS: ANS2 to ANS0 = ADCS: ANE2 to
ANE0), only one A/D conversion for one channel set as the start channel (= end channel) is performed and
terminated.
362
CHAPTER 13 8-/10-BIT A/D CONVERTER
[Conversion order in single conversion mode]
Table 13.5-1 gives an example of the conversion order in the single conversion mode.
Table 13.5-1 Conversion Order in Single Conversion Mode
Start Channel
End Channel
Conversion Order
AN0 pin
(ADCS: ANS = 000B)
AN3 pin
(ADCS: ANE = 011B)
AN0 --> AN1 --> AN2 --> AN3 --> End
AN6 pin
(ADCS: ANS = 110B)
AN2 pin
(ADCS: ANE = 010B)
AN6 --> AN7 --> AN0 --> AN1 --> AN2 --> End
AN3 pin
(ADCS: ANS = 011B)
AN3 pin
(ADCS: ANE = 011B)
AN3 --> End
363
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.5.2
Continuous Conversion Mode
In the continuous conversion mode, A/D conversion is performed sequentially from the
start channel to the end channel.
When A/D conversion for the end channel is terminated, it is continued after returning to
the start channel.
■ Setting of Continuous Conversion Mode
Operating the 8-/10-bit A/D converter in the continuous conversion mode requires the setting shown in
Figure 13.5-2.
Figure 13.5-2 Setting of Continuous Conversion Mode
bit15
ADCS
ADCR
BUSY
14
INT
13
INTE
12
PAUS
11
STS1
S10 ST1 ST0 CT1 CT0
10
9
STS0 STRT
bit 8
bit 7
6
Reserved
MD1
MD0
0
1
0
−
5
4
3
2
1
bit0
ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
D9 to D0 (Converted data stored)
ADER
−: Undefined
: Used bit
: Set the bit corresponding to pin to be used as analog input pin to "1".
1: Set 1
0: Set 1
■ Operation of Continuous Conversion Mode
• When the start trigger is input, A/D conversion starts from the channel set by the A/D conversion start
channel select bits (ANS2 to ANS0) and is performed continuously up to the channel set by the A/D
conversion end channel select bits (ANE2 to ANE0).
• When A/D conversion for the channel set by the A/D conversion end channel select bits (ANE2 to
ANE0) is terminated, it is continued after returning to the channel set by the A/D conversion start
channel select bits (ANS2 to ANS0).
• To terminate A/D conversion forcibly, write "0" to the A/D conversion-on flag bit in the A/D control
status register (ADCS: BUSY).
• This mode cannot be restarted during A/D conversion.
[When start and end channels are the same]
• If the start and end channels have the same channel number (ADCS: ANS2 to ANS0 = ADCS: ANE2 to
ANE0), A/D conversion for one channel set as the start channel (= end channel) is repeated.
364
CHAPTER 13 8-/10-BIT A/D CONVERTER
[Conversion order in continuous conversion mode]
Table 13.5-2 gives an example of the conversion order in the continuous conversion mode.
Table 13.5-2 Conversion Order in Continuous Conversion Mode
Start Channel
End Channel
Conversion Order
AN0 pin
(ADCS: ANS = 000B)
AN3 pin
(ADCS: ANE = 011B)
AN0 → AN1 → AN2 → AN3 → AN0 →
Repeat
AN6 pin
(ADCS: ANS = 110B)
AN2 pin
(ADCS: ANE = 010B)
AN6 → AN7 → AN0 → AN1 → AN2 → AN6
-→ Repeat
AN3 pin
(ADCS: ANS = 011B)
AN3 pin
(ADCS: ANE = 011B)
AN3 → AN3 →
Repeat
365
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.5.3
Pause-conversion Mode
In the pause-conversion mode, A/D conversion starts and pauses repeatedly for each
channel. When the start trigger is input after the A/D conversion pauses at the
termination of the A/D conversion for the end channel, A/D conversion is continued after
returning to the start channel.
■ Setting of Pause-conversion Mode
Operating the 8-/10-bit A/D converter in the pause-conversion mode requires the setting shown in Figure
13.5-3.
Figure 13.5-3 Setting of Pause-conversion Mode
bit15
ADCS
ADCR
BUSY
14
INT
13
INTE
12
PAUS
11
STS1
S10 ST1 ST0 CT1 CT0
10
9
STS0 STRT
−
bit 8
bit 7
6
Reserved
MD1
MD0
0
1
1
5
4
3
2
1
bit0
ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
D9 to D0 (Converted data stored)
ADER
−: Undefined
: Used bit
: Set the bit corresponding to pin to be used as analog input pin to "1".
1: Set 1
0: Set 0
■ Operation of Pause-conversion Mode
• When the start trigger is input, A/D conversion starts at the channel set by the A/D conversion start
channel select bits (ANS2 to ANS0). The A/D conversion pauses at the termination of the A/D
conversion for one channel. When the start trigger is input while A/D conversion pauses, A/D
conversion for the next channel is performed.
• The A/D conversion pauses at the termination of the A/D conversion for the channel set by the A/D
conversion end channel select bits (ANE2 to ANE0). When the start trigger is input while A/D
conversion pauses, A/D conversion is continued after returning to the channel set by the A/D conversion
start channel select bits (ANS2 to ANS0).
• To restart this mode while A/D conversion pauses, input the start trigger set by the A/D start trigger
select bits in the A/D control status register (ADCS: STS1, STS0).
• To terminate A/D conversion forcibly, write "0" to the A/D conversion-on flag bit in the A/D control
status register (ADCS: BUSY).
• This mode cannot be restarted during A/D conversion.
366
CHAPTER 13 8-/10-BIT A/D CONVERTER
[When start and end channels are the same]
If the start and end channels have the same channel number (ADCS: ANS2 to ANS0 = ADCS: ANE2 to
ANE0), A/D conversion for one channel set as the start channel (= end channel), and pause are repeated.
[Conversion order in pause-conversion mode]
Table 13.5-3 gives an example of the conversion order in the pause-conversion mode.
Table 13.5-3 Conversion Order in Pause-conversion Mode
Start Channel
End Channel
Conversion Order
AN0 pin
(ADCS: ANS = 000B)
AN3 pin
(ADCS: ANE= 011B)
AN0 → Stop, Start → AN1 → Stop, Start →
AN2 → Stop, Start → AN3 → Stop, Start →
AN0 → Repeat
AN6 pin
(ADCS: ANS = 110B)
AN2 pin
(ADCS: ANE= 010B)
AN6 → Stop, Start → AN7 → Stop, Start →
AN0 → Stop, Start → AN1 → Stop, Start →
AN2 -→ Stop, Start → AN6 → Repeat
AN3 pin
(ADCS: ANS = 011B)
AN3 pin
(ADCS: ANE= 011B)
AN3 → Stop, Start → AN3 → Stop, Start →
Repeat
367
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.5.4
Conversion Using EI2OS Function
The 8-/10-bit A/D converter can transfer the A/D conversion result to memory by using
the EI2OS function.
■ Conversion Using EI2OS
The use of the EI2OS enables the A/D-converted data protection function to transfer multiple data to
memory without the loss of converted data even if A/D conversion is performed continuously.
The conversion flow when the EI2OS is used is shown in Figure 13.5-4.
Figure 13.5-4 Flow of Conversion when Using EI2OS
A/D converter starts
Sample & hold
A/D conversion starts
A/D conversion terminates
Interrupt generated
EI2OS starts
Converted data transferred
Specified count
completed? *
NO
Interrupt cleared
YES
Interrupt processing
* : The specified count depends on the setting of the EI2OS.
368
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.5.5
A/D-converted Data Protection Function
A/D conversion with the output an interrupt request enabled activates the A/D
conversion data protection function.
■ A/D-converted Data Protection Function in 8-/10-bit A/D Converter
The 8-/10-bit A/D converter has only one A/D data register (ADCR) where A/D-converted data is stored.
When the A/D conversion results are determined after the termination of A/D conversion, data in the A/D
data register is rewritten. Therefore, the A/D conversion results may be lost if the A/D conversion results
already stored are not read before data in the A/D data register is rewritten. The A/D-converted data
protection function in the 8-/10-bit A/D converter is activated to prevent data loss. This function
automatically causes A/D conversion to pause when an interrupt request is generated (ADCS: INT = 1)
with an interrupt request enabled (ADCS: INTE = 1).
● A/D-converted data protection function when EI2OS not used
• When the A/D conversion results are stored in the A/D data register (ADCR) after the analog input is
A/D-converted, the interrupt request flag bit in the A/D control status register (ADCS: INT) is set to "1".
• A/D conversion pauses for data protection while the interrupt request flag bit in the A/D control status
register (ADCS: INT) is set.
• When the INT bit is set with an interrupt request from the A/D control status register enabled (ADCS:
INTE = 1), an interrupt request is generated. When the INT bit is cleared by the generated interrupt
processing, the pause of A/D conversion is canceled.
● A/D-converted data protection function when EI2OS used
• A/D conversion pauses for data protection while the EI2OS function is used to transfer the A/D
conversion results to memory from the A/D data register after A/D conversion. When A/D conversion
pauses, the pause flag bit in the A/D control status register (ADCS: PAUS) is set to "1".
• When the transfer of the A/D conversion results to memory by the EI2OS function is terminated, the
stop state of A/D conversion is released, At this time, the pause flag bit in the A/D control status register
(ADCS:PAUS) is not automatically cleared to "0". Please write "0" in the pause flag bit (ADCS:PAUS)
to clear. If A/D conversion is performed continuously, it is restarted.
● Processing flow of A/D conversion data protection function when EI2OS used
Figure 13.5-5 shows the processing flow of the A/D conversion data protection function when the EI2OS is
used.
369
CHAPTER 13 8-/10-BIT A/D CONVERTER
Figure 13.5-5 Processing Flow of A/D Conversion Data Protection Function when Using EI2OS
Start
EI2OS set
A/D continuous conversion starts
First conversion terminates
Data in A/D data register stored
EI2OS starts
Second conversion terminates
EI2OS terminates
NO
A/D pauses
YES
Data in A/D data register stored
Third conversion
EI2OS starts
Continued
Entire conversion terminates
EI2OS starts
Interrupt processing
A/D conversion pauses
End
Note: The operation flow at the time of which the A/D converter is stopped is omitted.
Notes:
• The A/D conversion data protection function is activated only when an interrupt request is
enabled. Set the interrupt request enable bit in the A/D control status register (ADCS: INTE) to
"1".
• When the EI2OS function is used to transfer the A/D conversion results to memory, do not disable
output of an interrupt request. If output of an interrupt request is disabled during a pause of A/D
conversion (ADCS: INTE = 0), A/D conversion may be restarted to rewrite data being transferred.
• When the EI2OS function is used to transfer the A/D conversion results to memory, do not restart.
Restarting during a pause of A/D conversion may cause loss of the A/D conversion results.
370
CHAPTER 13 8-/10-BIT A/D CONVERTER
13.6
Precautions when Using 8-/10-bit A/D Converter
Precautions when using the 8-/10-bit A/D converter are given below:
■ Precautions when Using 8-/10-bit A/D Converter
● Analog input pin
• The analog input pins serve as general-purpose I/O ports of port 5. When using the pin as an analog
input pin, switch the pin to "analog input pin" according to the setting of the port 5 direction register
(DDR5) and the analog input enable register (ADER).
• When using the pin as an analog input pin, write "0" to the bit in the DDR5 corresponding to the pin to
be used and turn off the output transistor. Also write 1 to the bit in the ADER corresponding to the pin
to be used and set the pin to "analog input enable."
• When an intermediate-level signal is input with the pin set as a general-purpose I/O port, the input
leakage current flows in the gate. When using the pin as an analog input pin, always set the pin to
"analog input enable".
● Precaution when starting by internal timer or external trigger
The input value at which the 8-/10-bit A/D converter is started by the internal timer output or external
trigger should be set to "inactive" ("H" side for external trigger). Holding the input value for the start
trigger active may cause the 8-/10-bit A/D converter to start concurrently with the setting of the A/D start
trigger select bits in the A/D control status register (ADCS: STS1, STS0).
● Procedure of 8-/10-bit A/D converter and analog input power-on
• Always apply a power to the A/D converter power (AVCC, AVR) and the analog input (AN0 to AN7)
after or concurrently with the digital power (VCC)-on.
• Always turn off the A/D converter power and the analog input before or concurrently with the digital
power (VCC)-down. Note that AVR should not exceed AVCC at power on or power down. (There is no
problem to turn on or off the analog power and digital power concurrently.)
● Power supply voltage of 8-/10-bit A/D converter
To prevent latch up, note that the 8-/10-bit A/D converter power (AVCC) should not exceed the digital
power (VCC) voltage.
371
CHAPTER 13 8-/10-BIT A/D CONVERTER
372
CHAPTER 14
UART1
This chapter explains the function and operation of the
UART.
14.1 Overview of UART1
14.2 Block Diagram of UART1
14.3 Configuration of UART1
14.4 Interrupt of UART1
14.5 Baud Rate of UART1
14.6 Explanation of Operation of UART1
14.7 Precautions when Using UART1
14.8 Program Example for UART1
373
CHAPTER 14 UART1
14.1
Overview of UART1
The UART1 is a general-purpose serial-data communication interface for synchronous
or asynchronous communication with external devices.
• Incorporates a bidirectional communication function
(clock synchronous and asynchronous modes)
• Incorporates a master/slave type communication function
(in multiprocessor mode: only master)
• Capable of generating an interrupt request at completion of transmit completion and
receive completion, and at detection of a receive error
• Supports expansion intelligent I/O service (EI2OS)
■ Function of UART1
● Function of UART1
The UART1 is a general-purpose serial-data communication interface, which transmits/receives serial data
with external devices. UART1 has functions listed in Table 14.1-1.
Table 14.1-1 Function of UART1
Function
Data buffer
Transfer mode
Baud rate
Full-duplicate double-buffer
• Synchronous to clock (without start bit/stop bit and parity bit)
• Asynchronous (start-stop synchronization to clock)
• Dedicated baud-rate generator (The baud rate can be selected from
among eight types.)
• Any baud rate can be set by external clock.
• A clock supplied from the internal clock (16-bit reload timer 1) can be
used.
Data length
• 7 bits (for asynchronous normal mode only)
• 8 bits
Signal type
NRZ (Non Return to Zero) type
Detection of receive error
Interrupt request
Master/slave type communication function
(asynchronous multiprocessor mode)
• Framing error
• Overrun error
• Parity error (not supported for operation mode 1, multiprocessor mode)
• Receive interrupt (receive, detection of receive error)
• Transmit interrupt (transmit)
• Both the transmission and reception support EI2OS.
This function enables communications between 1 (only use master) and n
(slave) (This function is used only as the master).
Note:
At the clock synchronous transfer, the UART only transfers data, not affixing the start and stop bits.
374
CHAPTER 14 UART1
Table 14.1-2 Operation Mode of UART1
Data Length
Operation Mode
With Parity
0
Asynchronous mode
(Normal mode)
1
Multiprocessor mode
2
Synchronous mode
No Parity
7 or 8 bits
Synchronous/
Asynchronous
Length of
Stop Bit
Asynchronous
1 bit or 2 bits *2
8 + 1 *1
−
Asynchronous
8
−
Synchronous
None
−: Setting disabled
*1: +1 is the address/data select bit (SCR1 register bit 11: A/D) used for controlling communications.
*2: During reception, only one bit can be detected as the stop bit.
375
CHAPTER 14 UART1
14.2
Block Diagram of UART1
The UART1 consists of the following block.
■ Block Diagram of UART1
Figure 14.2-1 Block Diagram of UART1
Control bus
Dedicated baud
rate generator
16-bit reload
timer
Receive interrupt
request output
Transmit interrupt
request output
Transmit clock
Clock
selector
Receive clock
Pin
SCK1
Receive
controller
Transmit
controller
Start bit
detector
Transmit
start circuit
Receive bit
counter
Transmit bit
counter
Receive parity
counter
Transmit parity
counter
Pin
SOT1
Transmit
shift register
Receive
shift register
Pin
SIN1
Reception state
determine circuit
Serial input
data register 1
End of
reception
Serial output
data register 1
Start of reception
Receive-errorgenerate signal
for EI2OS (to CPU)
Internal data bus
Communication
prescaler
control
register
376
MD
DIV2
DIV1
DIV0
Serial
mode
register 1
MD1
MD0
CS2
CS1
CS0
RST
SCKE
SOE
Serial
control
register 1
PEN
P
SBL
CL
A/D
REC
RXE
TXE
Serial
status
register 1
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
CHAPTER 14 UART1
● Details of pins, etc., in block diagram
The actual pin names and interrupt request numbers used in the UART1 are as follows:
SIN1 pin: P40/SIN1
SCK1 pin: P41/SCK1
SOT1 pin: P42/SOT1
Transmit interrupt number 1: #38 (26H)
Receive interrupt number 1: #37 (25H)
● Clock selector
The clock selector selects the transmit/receive clock from the dedicated baud rate generator, external input
clock, and internal clock (clock supplied from 16-bit reload timer).
● Receive controller
The receive controller is composed of receive bit counter, start bit detector and receive parity counter. The
receive bit counter counts the receive data, and outputs a receive interrupt request when reception of one
piece of data is completed according to the specified data length.
The start bit detector detects the start bit from the serial input signal and writes the received data to the
serial input data register (SIDR1), on a bit-by-bit shift basis in accordance with the transfer rate.
The receive parity counter detects parity bit of the receive data.
● Transmit controller
The transmit controller is composed of the transmit bit counter, transmit start circuit, and transmit parity
counter. The transmit bit counter counts the transmit data, and outputs a transmit interrupt request when
transmission of one piece of data is completed according to the set data length. The transmit start circuit
starts transmission when serial output data register (SODR1) is written. The transmit parity counter
generates the parity bit of the data transferred when parity is provided.
● Receive shift register
The receive shift register writes the receive data input from the SIN pin while shifting bit-by-bit, and when
the data reception is completed, it transfers the receive data to the serial input data register (SIDR1).
● Transmit shift register
Data written to SODR1 is transferred to the transmit shift register itself, and then the data is output to the
SOT pin while shifting bit-by-bit.
377
CHAPTER 14 UART1
● Serial mode register 1 (SMR1)
This register executes the following operations:
• Selects operation mode
• Selects clock input source (baud rate)
• Sets dedicated baud rate generator
• Selects clock speed (clock division value) when using dedicated baud rate generator
• Enables or disables output of serial data and clock pins
• Initialize UART
● Serial control register 1 (SCR1)
This register executes the following operations:
• Sets availability of parity
• Selects type of parity
• Sets stop bit length
• Sets data length
• Selects frame data format in operation mode 1 (asynchronous multiprocessor mode)
• Clears error flag
• Enables or disables transmitting
• Enables or disables receiving
● Serial status register 1 (SSR1)
The status register checks the transmission/reception state and error state and sets enabling/disabling of the
transmit/receive interrupt request.
● Serial input data register 1 (SIDR1)
The serial input data register retains the receive data. The serial input data is converted and then stored in
this register.
● Serial output data register 1 (SODR1)
The serial output data register sets the transmit data. Data written to this register is serial-converted and
then output.
● Communication prescaler control register (CDCR)
The control register sets the baud rate of the baud rate generator, which sets the start/stop of the
communication prescaler and the division rate of machine clock.
378
CHAPTER 14 UART1
14.3
Configuration of UART1
The UART1 pins, interrupt factors, register list and details are shown.
■ UART1 Pin
The pins used in the UART1 serve as general-purpose I/O port.
Table 14.3-1 indicates the pin functions and the setting necessary for use in the UART1.
Table 14.3-1 UART1 Pin
Pin Name
SOT1
SCK1
SIN1
Pin Function
Setting Necessary for Use in UART1
General-purpose I/O port,
serial data output
General-purpose I/O port,
serial clock input/output
General-purpose I/O port,
serial data input
Set to output enable. (SMR1 register bit 0: SOE=1)
In clock input, set pin as input port in port direction
register (DDR).
In clock output, set to output enable. (SMR1 register
bit 1: SCKE=1)
Set pin as input port in DDR.
■ Block Diagram of Pins of UART1
Reference:
Refer to "CHAPTER 4 I/O PORT" for the block diagram of pins.
■ List of Registers in UART1
Figure 14.3-1 List of Registers and Reset Values in UART1
bit
Serial control register 1 (SCR1)
bit
Serial mode register 1 (SMR1)
bit
Serial status register 1 (SSR1)
bit
15
0
7
0
15
0
7
14
0
6
0
14
0
6
13
0
5
0
13
0
5
12
0
4
0
12
0
4
11
0
3
0
11
1
3
Serial input data register 1 (SIDR1)/
X
X
X
X
X
Serial output data register 1 (SODR1)
Note: Function as SIDR1 when reading, function as SODR1 when writing
bit 15
14
13
12
11
Communication prescaler control register
O
X
X
X
O
1 (CDCR1)
10
1
2
0
10
0
2
9
0
1
0
9
0
1
8
0
0
0
8
0
0
X
X
X
10
9
8
O
O
O
X: Undefined
379
CHAPTER 14 UART1
■ Interrupt Request Generation by UART1
● Receive interrupt
• When receive data is loaded to the serial input data register (SIDR1), the receive data load flag bit (bit
12: RDRF) in the serial status register (SSR1) is set to "1". When a receive interrupt is enabled (bit 9:
RIE = 1), a receive interrupt request is generated to the interrupt controller.
• When either a framing error, overrun error, or parity error occurs, the framing error flag bit (bit 13:
FRE), the overrun error flag bit (bit 14: ORE), or parity error flag bit (bit 15: PE) in the serial status
register (SSR1) are set to "1" according to the error occurred. When a receive interrupt is enabled (bit 9:
RIE = 1), a receive interrupt is requested to the interrupt controller.
● Transmit interrupt
When transmit data is transferred from the serial output data register (SODR1) to the transmit shift register,
the transmit data empty flag bit (bit 11: TDRE) in the serial status register (SSR1) is set to "1". If a transmit
interrupt is enabled (bit 8: TIE = 1), a transmit interrupt is requested to the interrupt controller.
380
CHAPTER 14 UART1
14.3.1
Serial Control Register 1 (SCR1)
The serial control register 1 (SCR1) performs the following: setting parity bit, selecting
stop bit length and data length, selecting frame data format in operation mode 1
(asynchronous multiprocessor mode), clearing receive error flag, and enabling/
disabling of transmitting/receiving.
■ Serial Control Register 1 (SCR1)
Figure 14.3-2 Serial Control Register 1 (SCR1)
Address:
000027H
15
14
13
12
11
10
9
8
Reset value
00000100 B
R/W R/W R/W R/W R/W
W
R/W R/W
bit 8
Transmit enable bit
TXE
Transmit disable
0
Transmit enable
1
bit 9
RXE
Receive disable
0
Receive enable
1
Receive enable bit
bit 10
Receive error flag clear bit
REC
Clear PE and ORE, FRE, bits
0
No effect
1
bit 11
Address/data select bit
A/D
Data frame
0
Address frame
1
bit 12
CL
0
1
Data-length select bit
7 bits
8 bits
bit 13
SBL
1-bit length
0
2-bit length
1
Stop-bit length select bit
bit 14
P
0
1
R/W : Read/Write
W
: Write only
: Reset value
Parity select bit
Enable only when parity provided (PEN = 1)
Even parity
Odd parity
bit 15
PEN
No parity
0
With parity
1
Parity addition enable bit
381
CHAPTER 14 UART1
Table 14.3-2 Function of Serial Control Register 1 (SCR1)
Bit Name
382
Function
bit 15
PEN:
Parity addition enable bit
Specify whether to add (at sending) and detect (at receiving) a parity bit.
Note: A parity bit is not added in operation modes 1 and 2 (multiprocessor
mode, synchronous mode). Be sure to set this bit to "0".
bit 14
P:
Parity select bit
Select either odd or even parity when "with parity (PEN = 1)" is set.
bit 13
SBL:
Stop-bit length select bit
Set the length of the stop bit (frame end mark of send data) in operation modes 0
and 1 (multiprocessor mode, synchronous mode).
Note: At receiving, only the first bit of the stop bit is always detected.
bit 12
CL:
Data-length select bit
Specify the length of send and receive data.
Note: A data length of 7 bits can be selected only in operation mode 0
(asynchronous normal mode). In operation modes 1 and 2 (asynchronous
multiprocessor mode, Clock synchronous mode), be sure to set a data
length of 8 bits.
bit 11
A/D:
Address/data select bit
In operation mode 1 (asynchronous multiprocessor mode), set the data format of
the frame to be transmitted/received.
When bit set to "0": Data frame set
When bit set to "1": Address frame set
bit 10
REC:
Receive error flag clear
bit
Clear the receive error flags (bit15 to bit13: PE, ORE and FRE) of the serial
status register (SSR1) to "0".
When set to "0": Clears PE, ORE and FRE bits
When set to "1": No effect
When read: "1" is always read
Note: When a receive interrupt is enabled (bit 9: RIE = 1), set the bit10: REC bit
to "0" only when any one of the PE, ORE and FRE bits is set to "1".
bit 9
RXE:
Receive enable bit
Enable or disable the UART1 for receiving.
When set to "0": Reception disabled
When set to "1": Reception enabled
Note: When receiving is disabled during receiving, receiving stops after the data
being received is stored in the serial input data register.
bit 8
TXE:
Transmit enable bit
Enable or disable the UART1 for sending.
When set to "0": Transmission disabled
When set to "1": Transmission enabled
Note: When transmitting is disabled during transmitting, transmitting stops after
the data in the serial output data register (SODR1) being transmitted is
completed. To set this bit to "0", after writing data to SODR1, wait for a
time of 1/16th of the baud rate in the asynchronous mode and for a time
equal to or more than the baud rate in the synchronous mode.
CHAPTER 14 UART1
14.3.2
Serial Mode Register 1 (SMR1)
The serial mode register 1 (SMR1) performs selecting operation mode, selecting baud
rate clock, and disabling/enabling of output of serial data and clock to pin.
■ Serial Mode Register 1 (SMR1)
Figure 14.3-3 Serial Mode Register 1 (SMR1)
Address:
000026H
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
Serial data output enable bit (SOT1 pin)
SOE
Serves as general-purpose I/O port
0
Serves as serial data output of UART1
1
bit 1
Serial clock I/O enable bit (SCK1 pin)
SCKE
Serves
as
general-purpose
I/O port or clock input pin of UART 1
0
Serves
as
serial
clock
output
pin of UART1
1
bit 2
RST
0
1
UART reset bit
No effect
Initialize all registers of UART1
bit 5 bit 4 bit 3
CS2 CS1 CS0
Clock input source select bits
000B to 101B
Baud rate by dedicated baud rate generator
Baud rate by internal timer
110B
(16-bit reload timer1)
Baud rate by external clock
111B
bit 7
bit6
MD1 MD0
R/W : Read/Write
: Reset value
Operation mode select bits
Mode No.
Operation mode
0
0
0
Asynchronous mode (normal mode)
0
1
1
Asynchronous multiprocessor mode
1
0
2
Clock synchronous mode
1
1
⎯
Setting disabled
383
CHAPTER 14 UART1
Table 14.3-3 Function of Serial Mode Register 1 (SMR1)
Bit Name
bit 7 and bit 6
Function
MD0, MD1:
Operation mode select
bits
Select the UART1 operation mode.
Notes: 1. In operation mode 1 (asynchronous multiprocessor mode), only the
master can be used for master/slave communication. In operation
mode 1, the address/data bit on bit 9 cannot be received, so the
slave cannot be used.
2. In operation mode 1 (asynchronous multiprocessor mode), the
parity check function cannot be used, set the parity addition enable
bit to no parity (SCR1 register bit 15: PEN = 0).
CS0 to CS2:
Clock input source select
bits
Set the clock input source for the baud rate.
• Select the external clock (SCK1 pin), internal timer (16-bit reload timer),
or dedicated baud rate generator as the clock input source.
• Set the baud rate when selecting the dedicated baud rate generator.
bit 2
RST: UART Reset bit
This bit resets all registers in the UART1.
When set to "0": No effect on operation
When set to "1": Resets all registers in UART1
bit 1
SCKE:
Serial clock I/O enable
bit
Switch between input and output of the serial clock.
When set to "0": General-purpose I/O port or serial clock input pin set
When set to "1": Serial clock output pin set
Notes: 1. When using the SCK1 pin as the serial clock input, set the pin to
the input port using the port direction register (DDR). Also select
the external clock (bit 5 to 3: CS2 to CS0 = 111B) using the clock
input source select bit.
2. When using the SCK pin as the serial clock output, set the clock
input source select bit to anything other than the external clock (bit
5 to 3: CS2 to CS0 = anything other than 111B).
bit 0
SOE:
Serial-data output enable
bit
Enable or disable output of serial data.
When set to "0": General-purpose I/O port set
When set to "1": Serial data output pin set
bit 5 to bit 3
Note:
When "0" is written to the RST bit of Serial Mode Register, the UART interruption should be
prohibited. To prohibit the interruption, take one of the following procedures:
How to prohibit the interruption
1. Before writing "0" to the RST bit, clear I flag to prohibit all interrupt factors.
2. Before writing "0" to the RST bit, prohibit the UART interruption with the ILM register.
3. When "0" is written to the RST bit, writing should be performed at the UART interruption level or
the level with higher priority than the UART interruption.
384
CHAPTER 14 UART1
14.3.3
Serial Status Register 1 (SSR1)
The serial status register 1 (SSR1) checks the transmission/reception status and error
status and enables/disables interrupts.
■ Serial Status Register 1 (SSR1)
Figure 14.3-4 Serial Status Register 1 (SSR1)
Address:
000029H
15
14
13
12
11
10
9
8
Reset value
00001000 B
R
R
R
R
R
R/W R/W R/W
bit 8
TIE
0
1
Disables transmit interrupt
Enables transmit interrupt
bit 9
RIE
0
1
Disables receive interrupt
Enables receive interrupt
bit 10
BDS
0
1
bit 11
TDRE
0
1
bit 12
RDRF
0
1
Transmit interrupt enable bit
Receive interrupt enable bit
Transfer direction select bit
LSB first (transfer from least significant bit)
MSB first (transfer from most significant bit)
Transmit data writing flag bit
With transmit data (write of transmit data disabled)
No transmit data (write of transmit data enabled)
Receive data load flag bit
No receive data
With receive data
bit 13
Framing error flag bit
FRE
No framing error
0
With framing error
1
bit 14
Overrun error flag bit
ORE
0
No overrun error
1
With overrun error
bit 15
PE
0
No parity error
1
With parity error
Parity error flag bit
R/W : Read/Write
R
: Read only
: Reset value
385
CHAPTER 14 UART1
Table 14.3-4 Function of Serial Status Register 1 (SSR1)
Bit Name
386
Function
bit 15
PE:
Parity error flag bit
Detect a parity error in receiving.
• This bit is set to "1" when a parity error occurs.
• This bit is cleared when "0" is written to the receive error flag clear bit (SCR1 register
bit 10: REC).
• When a receive interrupt is enabled (bit 9: RIE = 1), a receive interrupt request is issued
when a parity error occurs.
• When the parity error flag bit is set (bit 15: PE = 1), data in the serial input data register
1 (SIDR1) is invalid.
bit 14
ORE:
Overrun error flag bit
Detect an overrun error in receiving.
• This bit is set to "1" when an overrun error occurs.
• This bit is cleared when "0" is written to the receive error flag clear bit (SCR1 register
bit 10: REC).
• When a receive interrupt is enabled (bit 9: RIE = 1), a receive interrupt request is issued
when an overrun error occurs.
• When the overrun error flag bit is set (bit 14: ORE = 1), data in the serial input data
register 1 (SIDR1) is invalid.
bit 13
FRE:
Framing error flag bit
Detect a framing error in receive data.
• This bit is set to "1" when a framing error occurs.
• This bit is cleared when "0" is written to the receive error flag clear bit (SCR1 register
bit 10: REC).
• When a receive interrupt is enabled (bit 9: RIE = 1), a receive interrupt request is issued
when a framing error occurs.
• When the framing error flag bit is set (bit 13: FRE = 1), data in the serial input data
register 1 (SIDR1) is invalid.
bit 12
RDRF:
Receive data load flag bit
Show the status of the serial input data register 1 (SIDR1).
• This bit is set to "1" when receive data is loaded to the serial input register 1 (SIDR1).
• This bit is cleared to "0" when data is read from the SIDR1.
• When a receive interrupt is enabled (bit 9: RIE = 1), a receive interrupt request is issued
when receive data is loaded to the serial input data register 1 (SIDR1).
bit 11
TDRE:
Transmit data write flag bit
Show the status of the serial output data register 1.
• This bit is cleared to "0" when send data is written to the serial output register 1(SODR1).
• This bit is set to "0" when data is loaded to the send shift register and transmission starts.
• When a transmission interrupt is enabled (bit 8: TIE = 1), a transmit interrupt request is
issued when data written to the serial output data register 1(SODR1) is transmitted to
the transmit shift register (bit 11: TDRE=1).
bit 10
BDS:
Transfer direction select bit
This bit sets the direction of serial data transfer.
When set to "0": Transfers data from least significant bit (LSB first)
When set to "1": Transfers data from most significant bit (MSB first)
Note: At reading and writing data from and to the serial data register, data is written to the
serial output data register (SODR1) and then the transfer direction select bit (BDS)
is rewritten to switch between the upper bits and the lower bits of data. In this case,
the written data becomes invalid.
bit 9
RIE:
Receive interrupt enable bit
Enable or disable receive data.
When set to "1": A receive interrupt request is issued when receive data is loaded to the
serial input data register 1 (SIDR1) (bit 12: RDRF = 1) or when a
receive error occurs (bit 15: PE = 1, bit 14: ORE = 1, or bit 13: FRE = 1).
bit 8
TIE:
Transmit interrupt enable bit
Enable or disable send interrupt.
When set to "1": A receive interrupt request is issued when data written to the serial
output data register 1 (SODR1) is loaded to the transmit shift register
(bit 11: TDRE = 1).
CHAPTER 14 UART1
14.3.4
Serial Input Data Register 1 (SIDR1) and Serial Output
Data Register 1 (SODR1)
The serial input data register (SIDR1) and serial output data register (SODR1) are
allocated to the same address. At read, the register functions as SIDR1. At write, the
register functions as SODR1.
■ Serial Input Data Register 1 (SIDR1)
Figure 14.3-5 Serial Input Data Register 1 (SIDR1)
Address:
000028H
bit 7
6
5
4
3
2
1
bit 0
D7
R
D6
R
D5
R
D4
R
D3
R
D2
R
D1
R
D0
R
Reset value
XXXXXXXXB
R: Read only
X: Undefined
SIDR1 is a data buffer register for receiving serial data.
• The serial data signal transmitted to the serial data input pin (SIN1) is converted by the shift register and
stored in SIDR1.
• When the data length is 7 bits, the upper one bit (SIDR1: D7) becomes invalid.
• When receive data is stored in the serial input data register 1 (SIDR1), the receive data load flag bit
(SSR1 register bit 12: RDRF) is set to "1". When a receive interrupt is enabled (SSR1 register bit 9: RIE
= 1), a receive interrupt request is issued to the interrupt controller.
• Read SIDR1 when the receive data load flag bit (SSR1 register bit 12: RDRF) is set to "1". The receive
data load flag bit (SSR1 register bit 12: RDRF) is cleared to "0" automatically when SIDR1 is read.
• When a receive error occurs (any one of SSR1 register bit 15, 14, 13: PE, ORE and FRE is "1"), the
receive data in SIDR1 becomes invalid.
387
CHAPTER 14 UART1
■ Serial Output Data Register 1 (SODR1)
Figure 14.3-6 Serial Output Data Register 1 (SODR1)
Address:
000028H
7
D7
W
6
D6
W
5
D5
W
4
D4
W
3
D3
W
2
D2
W
1
D1
W
bit 0
D0
W
Reset value
XXXXXXXXB
W: Write only
X: Undefined
The serial output data register 1 (SODR1) is a data buffer register for transmitting serial data.
• When data to be transmitted is written to SODR1 when transmission is enabled (SCR1 register bit 8:
TXE = 1), it is transferred to the transmit shift register, converted to serial data, and transmit from the
serial data output pin (SOT1).
• When the data length is 7 bits, the upper one bit (SODR1 register bit 7: D7) becomes invalid.
• The transmit data write flag (SSR1 register bit 11: TDRE) is cleared to "0" when send data is written to
SODR1.
• The transmit data write flag is set to "1" at completion of data transfer to the transmit shift register.
• When the transmit data write flag (SSR1 register bit 11: TDRE) is "1", the next transmit data can be
written. When a transmit interrupt is enabled (SSR1 register bit 8: TIE=1), a transmit interrupt occurs to
the interrupt controller. The next transmit bit data should be written with the transmit data write flag
(SCR1 register bit 11: TDRE) at 1.
Note:
Serial output data register is a write-only register and serial input data register is a read-only register.
However, since they are allocated to the same address, the write and read values are different.
Therefore, do not use instructions that perform read-modify-write (RMW) operation such as INC and
DEC instructions.
388
CHAPTER 14 UART1
14.3.5
Communication Prescaler Control Register 1 (CDCR1)
The communication prescaler control register 1 (CDCR1) is used to set the baud rate of
the dedicated baud rate generator for the UART1.
• Starts/stop the communication prescaler
• Sets the division ratio for machine clock
■ Communication Prescaler Control Register 1 (CDCR1)
Figure 14.3-7 Communication Prescaler Control Register 1 (CDCR1)
Address: 15
00002BH
14
13
12
11
10
9
8
Reset value
0XXX0000B
R/W ⎯
⎯
⎯ R/W R/W R/W R/W
bit 10 bit 9 bit 8
DIV2 DIV1 DIV0
Communication prescaler division ratio (div) bits
0
0
0
1-divided clock
0
0
1
2-divided clock
0
1
0
3-divided clock
0
1
1
4-divided clock
1
0
0
5-divided clock
1
0
1
6-divided clock
1
1
0
7-divided clock
1
1
1
8-divided clock
bit 11
Reserved bit
Reserved
0
bit 15
MD
R/W : Read/Write
X
: Undefined
⎯
: Unused
: Reset value
0
1
Always set 0
Communication prescaler control bit
Communication prescaler stopped
Communication prescaler enabled
389
CHAPTER 14 UART1
Table 14.3-5 Functions of Communication Prescaler Control Register 1 (CDCR1)
Bit Name
Function
bit 15
MD:
Communication
prescaler control bit
This bit enables or disables the communication prescaler.
When set to "0": Stops communication prescaler
When set to "1": Operates communication prescaler
bit 14 to bit 12
Unused bits
Read: The value is not fixed.
Write: No effect
bit 11
Reserved: Reserved bit
Be sure to set this bit to "0".
bit 10 to bit 8
DIV2 to DIV0:
Communication
prescaler division ratio
bits
These bits set the machine clock division ratio.
Note: When changing the division ratio, the time of at least 2 cycles division
of the division clock should be allowed before the next communication
is started in order to stabilize the clock frequency.
390
CHAPTER 14 UART1
14.4
Interrupt of UART1
The UART1 has a receive and a transmit interrupts, and the following factors can issue
interrupt requests.
• Receive data is loaded to the serial input data register 1 (SIDR1).
• A receive error (parity error, overrun error, framing error) occurs.
• When send data is transferred from the serial output data register 1 (SODR1) to
transmit shift register
Also, each of these interrupt factors supports the extended intelligent I/O service
(EI2OS).
■ Interrupt of UART1
The UART1 interrupt control bits and interrupt factors are shown in Table 14.4-1.
Table 14.4-1 UART1 Interrupt Control Bit and Interrupt Factor
Transmission/
Reception
Reception
Transmission
Interrupt
request
Flag Bit
Operation
Mode
Interrupt Factor
0
1
2
SSR1: RDRF
Ο
Ο
Ο
Receive data loaded into
serial input data register 1
(SIDR1)
SSR1:ORE
Ο
Ο
Ο
Overrun error
SSR1:FRE
Ο
Ο
X
Framing error
SSR1:PE
Ο
X
X
Parity error
Ο
Transfer of transmit data
completed from serial
output data register 1
(SODR1)
SSR1: TDRE
Ο
Ο
Interrupt
Factor
Enable Bit
Clear of the Interrupt
request Flag
Reading receive data
SSR1: RIE
Writing 0 to receive error
flag clear bit (SCR1
register bit 10: REC)
SSR1: TIE
Writing transmit data
Ο: Available
X: Not available
391
CHAPTER 14 UART1
● Receive interrupt
When a receive interrupt is enabled (SSR1 register bit 9: RIE = 1), a receive interrupt request is issued to
the interrupt controller at completion of data receiving (SSR1 register bit 12: RDRF = 1) or when any one
of the overrun error (SSR1 register bit 14: ORE = 1), framing error (SSR 1 register bit 13: FRE = 1), and
parity error (SSR 1 register bit 15: PE = 1) occurs.
The receive data load flag (SSR1 register bit 12: RDRF) is cleared to "0" automatically when the serial
input data register 1 (SIDR1) is read. Each receive error flag (SSR1 register bit 15, 14, 13: PE, ORE, FRE)
is cleared to "0" when "0" is written to the receive error flag clear bit (SCR1 register bit 10: REC).
Note:
If a receive error (parity error, overrun error, framing error) occurs, correct the error as necessary,
and then write 0 to the receive error flag clear bit (SCR1 register bit 10: REC) to clear each receive
error flag.
● Transmit interrupt
When send data is transmitted from the serial output data register 1 (SODR1) to the transmit shift register,
the transmit data write flag bit (SSR1 register bit 11: TDRE) is set to "1".
When a transmit interrupt is enabled (SSR1 register bit 8: TIE = 1), a send interrupt request is issued to the
interrupt controller.
■ Interrupt Related to UART1 and EI2OS
Note:
See Section "3.5 Interrupt" for the interrupt number, interrupt control register, and interrupt vector
addresses.
■ EI2OS Function of UART1
The UART1 supports EI2OS. Consequently, EI2OS can be started separately for receive interrupts and
transmit interrupts.
● At reception:
The EI2OS can be used regardless of the state of other resources.
● At transmission:
Since the interrupt control registers (ICR13, 14) are shared with transmit interrupts of UART1, EI2OS can
be started only when UART1 receive interrupts are not used.
392
CHAPTER 14 UART1
14.4.1
Generation of Receive Interrupt and Timing of Flag Set
Interrupts at receiving include the receive completion (SSR1 register bit 12: RDRF), and
the receive error (SSR1 register bit 15, 14, 13: PE, ORE, FRE).
■ Generation of Receive Interrupt and Timing of Flag Set
● Receive data load flag and each receive error flag sets
When data is received, it is stored in the serial input data register 1 (SIDR1) when the stop bit is detected
(in operation modes 0 and 1: Asynchronous normal mode, Asynchronous multiprocessor mode) or when
the last bit of receive data (SIDR1 register bit 7: D7) is detected (in operation mode 2: Clock synchronous
mode). When a receive error occurs, the error flags (SSR1 register bit 15, 14, 13: PE, ORE, FRE) and
receive data load flag (SSR1 register bit 12: RDRF) are set. In each operation mode, the received data in
the serial input data register 1 (SIDR1) is invalid if either error flag is set.
Operation mode 0 (Asynchronous normal mode)
The receive data load flag bit (SSR1 register bit 12: RDRF) is set when the stop bit is detected. The error
flags (SSR1 register bit 15, 14, 13: PE, ORE, FRE) are set when a receive error occurs.
Operation mode 1 (Asynchronous multiprocessor mode)
The receive data load flag bit (SSR1 register bit 12: RDRF) is set when the stop bit is detected. The error
flags (SSR1 register bit 14, 13: ORE, FRE) are set when a receive error occurs. A parity error (SSR1
register bit 15: PE) cannot be detected.
Operation mode 2 (Clock synchronous mode)
The receive data load flag bit (SSR1 register bit 12: RDRF) is set to "1" when the last bit of receive data
(SIDR1 register bit 7: D7) is detected. The error flags (SSR1 register bit 14: ORE) are set when a receive
error occurs. A parity error (SSR1 register bit 15: PE) and framing error (SSR1 register bit 13: FRE) cannot
be detected.
Reception and timing of flag set are shown in Figure 14.4-1.
393
CHAPTER 14 UART1
Figure 14.4-1 Reception and Timing of Flag Set
Receive data
(operation mode 0)
ST
D0
D1
D5
D6
D7
SP
Receive data
(operation mode 1)
ST
D0
D1
D6
D7
A/D
SP
D0
D1
D4
D5
D6
D7
Receive data
(operation mode 2)
SSR1: PE, ORE, FRE*
SSR1: RDRF
*
: The PE flag cannot be detected in operation mode 1.
The PE and FRE flags cannot be detected in operation mode 2.
ST : Start bit
SP : Stop bit
A/D : Address/data select bit of operation mode 2
Receive interrupt occurs
● Timing of receive interrupt request generation
With a receive interrupt enabled (SSR1 register bit 9: RIE = 1), when any one of the receive data load flag
(SSR1 register bit 12: RDRF), parity error flag (SSR1 register bit 15: PE), overrun error flag (SSR1 register
bit 14: ORE) and framing error flag (SSR1 register bit 13: FRE) is set, reception interrupt is requested to
interrupt controller.
394
CHAPTER 14 UART1
14.4.2
Generation of Transmit Interrupt and Timing of Flag Set
At transmission, the interrupt is generated in the state which the serial output data
register 1 (SODR1) is empty and the succeeding data can be written to the serial output
data register 1 (SODR1).
■ Generation of Transmit Interrupt and Timing of Flag Set
● Set and clear of transmit data empty flag bit
The send data write flag bit (SSR1 register bit 11: TDRE) is set when the send data written to the serial
output data register 1 (SODR1) is loaded to the send shift register and the next data is ready for writing.
The send data write flag bit (SSR1 register bit 11: TDRE) is cleared to "0" when the next send data is
written to the serial output data register 1 (SODR1).
Transmission and timing of flag set are shown in Figure 14.4-2.
Figure 14.4-2 Transmission and Timing of Flag Set
Transmit interrupt requested
[Operation modes 0 and 1]
Transmit interrupt occurred
Writing to SODR1
SSR1: TDRE
Output to SOT1
SP SP ST D0 D1 D2 D3
ST D0 D1 D2 D3 D4 D5 D6 D7 A/D
Transmit interrupt occurred
Transmit interrupt occurred
[Operation mode 2]
Writing to SODR1
SSR1: TDRE
Output to SOT1
ST
D0 to D7
SP
A/D
:
:
:
:
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Start bit
Data bits
Stop bit
Address/data select bit
● Timing of transmit interrupt request
When a transmit interrupt is enabled (SSR1 register bit 8: TIE = 1), a send interrupt request is issued to
interrupt controller when the transmit data write flag bit (SSR1 register bit 11: TDRE) is set.
Note:
When sending is disabled during sending (SCR1 register bit 8: TXE=0: and also in operation mode 1
(asynchronous multiprocessor mode), receiving disabled (also including bit 9: RXE), the send data
write flag bit is set (SSR1 register bit 11: TDRF=1) and UART 1 communications are disabled after
the shift operation of the send shift register stops. The send data written to the serial output data
register 1 before the transmission stops (SODR1) is sent.
395
CHAPTER 14 UART1
14.5
Baud Rate of UART1
One of the following can be selected as the UART1 transmit/receive clock.
• Dedicated baud rate generator
• Internal clock (16-bit reload timer output)
• External clock (clock input to SCK1 pin)
■ Select of UART1 Baud Rate
The UART1 baud rate select circuit comprises as shown in Figure 14.5-1. The clock input source can be
selected from among the following three types:
● Baud rate by dedicated baud rate generator
When using the dedicated baud rate generator incorporated into UART1 as a clock input source, set the
CS2 to CS0 bits in the serial mode register (SMR1) bit 5 to 3 to "000B" to "101B" according to the baud
rate. The baud rate can be selected from six types.
● Baud rate by internal timer
• When using the internal clock supplied from the 16-bit reload timer as a clock input source, set the CS2
to CS0 bits in SMR1 bit 5 to 3 to "110B".
• The baud rate is the value at which the clock supplied from the 16-bit reload timer as it is in the clock
synchronous mode, and the value at which the frequency of the supplied clock is divided by 16 in the
clock asynchronous mode.
• Any baud rate can be selected according to the setting values of the 16-bit reload timer.
● Baud rate by external clock
• When using the external clock supplied from the clock input pin (SCK1) in the UART1 as the clock
input source, set the CS2 to CS0 bits in SMR1 bit 5 to 3 to "111B".
• The baud rate is the value at which the external clock is supplied in the clock synchronous mode and the
value at which the frequency of the input clock is divided by 16 in the clock asynchronous mode.
396
CHAPTER 14 UART1
Figure 14.5-1 UART1 Baud Rate Selector
SMR1: CS2 to CS0
(Clock input source select bits)
Clock selector
CS2 to CS0 = 000B to 101B
[Dedicated baud rate generator]
Communication prescaler
(CDCR1: MD0, DIV2 to DIV0)
[Internal timer]
TMCSR1: CSL1, CSL0
Clock selector
Decrement UF
counter
Oscillation dividing circuit
[Clock synchronous]
Any one of the 1/1, 1/2, 1/4,
1/8, 1/16, 1/32 division
ratio is selected
[Asynchronous]
The internal fixed
division ratio is selected
CS2 to CS0 = 110B
1/1 [Clock synchronous]
1/16 [Asynchronous]
Baud rate
Prescaler
16-bit reload timer 1
CS2 to CS0 = 111B
[External clock]
SCK1
Pin
1/1 [Clock synchronous]
1/16 [Asynchronous]
SMR1: MD1, MD0
(operation mode select bits)
397
CHAPTER 14 UART1
14.5.1
Baud Rate by Dedicated Baud Rate Generator
The baud rate that can be set when the output clock of the dedicated baud rate
generator is selected as the transmit/receive clock of the UART1 is shown.
■ Baud Rate by Dedicated Baud Rate Generator
The baud rate based on the dedicated baud rate generator is set by setting the clock input source select bits
in the serial mode register (SMR1 register bit 5 to 3: CS2 to CS0) to "000B" to "101B".
When generating a transmit/receive clock using the dedicated baud rate generator, the division ratio for the
clock input source selected by the clock selector is selected to determine the baud rate after the machine
clock frequency is divided by the communication prescaler.
The division ratio at which the machine clock frequency is divided by the communication prescaler is the
same for the clock synchronous and asynchronous modes. The division ratio at which the baud rate is
determined is different for the clock synchronous and asynchronous modes.
Figure 14.5-2 shows the baud rate selector based on the dedicated baud rate generator.
Figure 14.5-2 Baud Rate Selector Based on Dedicated Baud Rate Generator
SMR1: CS2 to CS0
(clock input source select bits)
Clock selector
φ
φ/1, φ/2, φ/3, φ/4,
φ/5, φ/6, φ/7, φ/8
Communication prescaler
(CDCR1: MD0, DIV2 to DIV0)
Dividing circuit
[Clock synchronous]
Any one of the 1/1, 1/2, 1/4,
1/8, 1/16, 1/32 division ratio
is selected
[Asynchronous]
The internal fixed
division ratio is selected
Baud rate
SMR1: MD1, MD0
(operation mode select bits)
φ: Machine clock frequency
● Calculation expression for baud rate
Baud rate in asynchronous mode = φ × div × (division ratio of transfer clock in asynchronous mode)
Baud rate in clock synchronous mode = φ × div × (division ratio of transfer clock in clock synchronous
mode)
φ: Machine clock frequency
div: Division ratio based on communication prescaler
398
CHAPTER 14 UART1
● Division ratio based on communication prescaler (common between asynchronous and clock
synchronous modes)
The division ratio of the machine clock is set by the division ratio select bits in the communication
prescaler control register (CDCR1 register bit 10 to 8: DIV2 to DIV0).
Table 14.5-1 Division Ratio Based on Communication Prescaler
MD
DIV2
DIV1
DIV0
div
0
−
−
−
Stop
1
0
0
0
1
1
0
0
1
2
1
0
1
0
3
1
0
1
1
4
1
1
0
0
5
1
1
0
1
6
1
1
1
0
7
1
1
1
1
8
div: Division ratio based on communication prescaler
● Baud rate (asynchronous mode)
The baud rate in the asynchronous mode is generated using output clock of the communication prescaler.
The division ratio is set by the clock input source select bits (SMR1 register bit 5 to 3: CS2 to CS0).
Table 14.5-2 Baud Rate (Asynchronous Mode)
CS2
CS1
CS0
Asynchronous Mode
(Start/Stop Synchronous)
Calculation
0
0
0
76,923 bps
(φ/div) / (8 × 13 × 2)
0
0
1
38,461 bps
(φ/div) / (8 × 13 × 4)
0
1
0
19,230 bps
(φ/div) / (8 × 13 × 8)
0
1
1
9,615 bps
(φ/div) / (8 × 13 × 16)
1
0
0
500 kbps
(φ/div) / (8 × 2 × 2)
1
0
1
250 kbps
(φ/div) / (8 × 2 × 4)
φ: Machine clock frequency
div: Division ratio based on communication prescaler
399
CHAPTER 14 UART1
● Baud rate (synchronous mode)
The baud rate in the synchronous mode is generated by dividing the output clock of the communication
prescaler by 1, 2, 4, 8, 16 and 32. Set the division ratio using the clock input source select bits (bits 5 to 3 in
SMR1 register: CS2 to CS0).
Table 14.5-3 Baud Rate (Clock Synchronous)
CS2
CS1
CS0
CLK Synchronous
Calculation
0
0
0
2 Mbps
(φ/div) / 1
0
0
1
1 Mbps
(φ/div) / 2
0
1
0
500 kbps
(φ/div) / 4
0
1
1
250 kbps
(φ/div) / 8
1
0
0
125 kbps
(φ/div) / 16
1
0
1
62.5 kbps
(φ/div) / 32
φ: Machine clock frequency
div: Division ratio based on communication prescaler
400
CHAPTER 14 UART1
14.5.2
Baud Rate by Internal Timer (16-bit Reload Timer)
The setting when selecting the internal clock supplied from the 16-bit reload timer 1 as
the clock input source of the UART1 and the baud rate calculation are shown below.
■ Baud Rate by Internal Timer (16-bit Reload Timer Output)
The baud rate based on the internal timer (16-bit reload timer output) is set by setting the clock input source
select bits (SMR1 register bit 5 to 3: CS2 to CS0) to "110B". Any baud rate can be set by selecting the
division ratio of the count clock and the reload value of the 16-bit reload timer freely.
Figure 14.5-3 shows the baud rate selector based on the internal timer.
• If the internal timer (16-bit reload timer) is selected as a clock input source (SMR1 register bit 5 to 3:
CS2 to CS0), the 16-bit reload timer output pin (TOT) is connected internally and does not need to be
connected externally to the external clock input pin (SCK).
• The 16-bit reload timer output pin (TOT) can be used as a general-purpose I/O port when it is not being
used in other way.
Figure 14.5-3 Baud Rate Selector by Internal Timer (16-bit Reload Timer Output)
SMR1: CS2 to CS0 = 110 B
(Clock input source select bits)
Clock selector
1/1 [Clock synchronous]
1/16 [Asynchronous]
16-bit reload timer output
(The frequency is specified by
the count-clock division ratio
and the reload value)
Baud rate
SMR1: MD1, MD0
(Operation mode select bits)
● Calculation expression for baud rate
φ/N
Asynchronous baud rate =
bps
16 × 2 × (n+1)
φ/N
Clock synchronous baud rate =
bps
2
× (n+1)
φ: machine clock frequency
N: division ratio based on communication prescaler for 16-bit reload timer (21, 23, 25)
n: reload value for 16-bit reload timer (0 to 65,535)
401
CHAPTER 14 UART1
● Example of setting baud rates and reload register setting values (machine clock frequency: 7.3728
MHz)
Table 14.5-4 Baud Rate and Reload Value
Reload Value
Baud Rate
(bps)
Clock Asynchronous
(start-stop synchronization)
Clock Synchronous
N = 21(machine
clock 2-divided)
N = 23(machine
clock 8-divided)
N = 21(machine
clock 2-divided)
N = 23(machine
clock 8-divided)
38,400
2
−
47
11
19,200
5
−
95
23
9,600
11
2
191
47
4,800
23
5
383
95
2,400
47
11
767
191
1,200
95
23
1,535
383
600
191
47
3,071
767
300
383
95
6,143
1,535
N: Division ratio based on communication prescaler for 16-bit reload timer
−: Setting disabled
402
CHAPTER 14 UART1
14.5.3
Baud Rate by External Clock
This section explains the setting when selecting the external clock as the transmit/
receive clock of the UART1.
■ Baud Rate by External Clock
To select a baud rate by the external clock input, the following settings are required:
• Set the clock input source select bits in the serial mode register (SMR1 register bit 5 to 3: CS2 to CS0)
to "111B".
• Set the SCK1 pin as the input port in the port direction register (DDR).
• Set the serial clock I/O enable bit (SMR1 register bit 1: SCKE) to "0".
• Set the baud rate on the basis of the external clock input from the SCK1 pin. Since the internal division
ratio is fixed, the external input clock must be changed in changing the baud rate.
Figure 14.5-4 Baud Rate Selector by External Clock
SMR1: CS2 to CS0 = 111B
(Clock input source select bits)
Clock selector
SCK1
Pin
1/1 [Clock synchronous]
1/16 [Asynchronous]
Baud rate
SMR1: MD1, MD0
(Operation mode select bits)
● Expressions to obtain baud rate
Asynchronous baud rate = f/16 bps
Clock synchronous baud rate = f bps
f: External clock frequency (2 MHz max.)
403
CHAPTER 14 UART1
14.6
Explanation of Operation of UART1
The UART1 has master/slave type connection communication function (operation mode
1: asynchronous multiprocessor mode) in addition to bidirectional serial
communication function (operation modes 0 and 2: asynchronous normal mode and
clock synchronous mode).
■ Operation of UART1
● Operation mode
The UART1 has three types of operation modes, they can set the inter-CPU connection mode or data
communication mode.
Table 14.6-1 shows operation mode of UART1.
Table 14.6-1 Operation Mode of UART 1
Data Length
Operation Mode
No Parity
0
Normal mode
1
Multiprocessor mode
2
Clock synchronous mode
With Parity
7 bits or 8 bits
Synchronous/
Asynchronous
Length of Stop Bit
Asynchronous
8 + 1 *1
−
Asynchronous
8
−
Synchronous
1 bit or 2 bits *2
None
−: Setting disabled
*1: +1 is the address/data select bit (SCR1 register bit 11: A/D) used for controlling communications.
*2: During reception, only one bit can be detected as the stop bit.
Note:
The UART1 operation mode 1 (asynchronous multiprocessor mode) is only used as the master in
the master/slave type connection.
● Inter-CPU connection mode
Either 1-to-1 connection or master/slave type connection can be selected for the inter-CPU connection
mode. In both cases, the data length, parity, synchronous or asynchronous mode, etc., must be the same for
all CPUs. The operation modes are selected as follows.
• For the 1-to-1 connection, the same operation mode (either operation mode 0 or 2: normal mode, clock
synchronous mode) must be adopted for the two CPUs. For the asynchronous mode, select operation
mode 1: asynchronous multiprocessor mode (SMR1 register bit 7, 6: MD1, MD0 = "00B"): for the
synchronous mode select operation mode 2: clock synchronous mode (SMR1 register bit 7, 6: MD1,
MD0 = "10B").
• For the master/slave type connection, operation mode 1: asynchronous multiprocessor mode (SMR1
register bit 7, 6: MD1, MD0 = "01B" is set; select operation mode 1 (asynchronous multiprocessor
mode) and use it as the master. For this connection, select no parity and 8-bit data length.
404
CHAPTER 14 UART1
● Synchronous/asynchronous
For the operation modes, either the asynchronous mode (start-stop synchronization) or the clocksynchronous mode can be selected.
● Signal mode
The UART1 can only handle the NRZ (Non Return to Zero) data format.
● Start of transmission/reception
• Transmission starts when the transmission enable bit of the serial control register (SCR1 register bit 8:
TXE) is set to "1".
• Reception starts when the reception enable bit of the serial control register (SCR1 register bit 9: RXE) is
set to "1".
● Stop of transmission/reception
• Transmission stops when the transmission enable bit of the serial control register (SCR1 register bit 8:
TXE) is set to "0".
• Reception stops when the reception enable bit of the serial control register (SCR1 register bit 9: RXE) is
set to "0".
● Stop during transmission/reception
• When reception is disabled during receiving (during data input to reception shift register) (SCR1
register bit 9: RXE = 0), it stops after reception of the frame being received is completed and the receive
data is stored to the serial input data register 1 (SIDR1).
• When transmission is disabled during transmission (during data output from the transmission shift
register) (SCR1 register bit 8: TXE = 0), it stops after transmission of one frame to the transmission shift
register from the serial output data register 1 (SODR1) is completed.
405
CHAPTER 14 UART1
14.6.1
Operation in Asynchronous Mode
(Operation Mode 0 or 1)
When the UART 1 is used in operation mode 0 (asynchronous normal mode) or
operation mode 1 (asynchronous multiprocessor mode), the asynchronous transfer
mode is selected.
■ Operation in Asynchronous Mode
● Format of transmit/receive data
Transmission and reception always start with the start bit (Low level); transmission and reception are
performed at the specified data bit length on LSB first basis and end with the stop bit ("H" level).
• In operation mode 0 (Asynchronous normal mode), the data length can be set to "7" or 8 bits. Use of the
parity bit can be specified.
• In operation mode 1 (Asynchronous multiprocessor mode), the data length is fixed to 8 bits. There is no
parity bit. The address/data bit (SCR1 register bit 11: A/D) is added to bit 9.
Figure 14.6-1 shows the transmit/receive data format in the asynchronous mode.
406
CHAPTER 14 UART1
Figure 14.6-1 Format of Transmit/Receive Data (Operation Mode 0 or 1)
[Operation mode 0]
ST
D0
D1
D2
D3
D4
D5
D7
D8
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
D8
SP
P not
provided
Data 8 bits
ST
D0
D1
D2
D3
D4
D5
D7
D8
P
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
D8
P
SP
ST
D0
D1
D2
D3
D4
D5
D7
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
SP
ST
D0
D1
D2
D3
D4
D5
D7
P
P
provided
P not
provided
Data 7 bits
ST
D0
SP SP
D1
D2
D3
D4
D5
D7
P
SP
P
provided
[Operation mode 1]
ST
D0
D1
D2
D3
D4
D5
D7
D8
A/D
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
D8
A/D
SP
Data 8 bits
ST
SP
P
A/D
:
:
:
:
Start bit
Stop bit
Parity bit
Address/data bit
● Transmission
• Transmit data is written to the serial output data register 1 (SODR1) with the transmit data write flag bit
(SSR1 register bit 11: TDRE) set to "1".
• Transmission starts when transmit data is written and the transmit enable bit of the serial control register
(SCR1 register bit 8: TXE) is set to "1".
• The transmit data write flag bit (SSR1 register bit 11: TDRE) is cleared to "0" temporarily when
transmit data is written to SODR1.
• The transmit data write flag bit (SSR1 register bit 11: TDRE) is set to "1" again once the transmit data is
written to the send shift register from the serial output data register 1 (SODR1).
• When the transmit interrupt enable bit (SSR1 register bit 8: TIE) is set to "", a send interrupt request is
issued once the send data write flag bit (SSR1 register bit 11: TDRE) is set to "1". The succeeding send
data can be written to the serial output data register 1 (SODR1) at interrupt processing.
407
CHAPTER 14 UART1
● Reception
• When reception is enabled (SCR1 register bit 9: RXE = 1), receiving is always performed.
• When the start bit of receive data is detected, the serial input data register 1 (SIDR1) receives one frame
of data and stores data to the serial input data register 1 (SIDR1) according to the data format specified
in the serial control register 1 (SCR1).
• At completion of receiving one frame of data, the receive data load flag bit (SSR1 register bit 12:
RDRF) is set to "1".
• When the status of the error flag of the serial status register 1 (SSR1) is checked to find normal
reception at the completion of one frame of data, read the receive data from the serial input data register
1 (SIDR1). When a receive error occurs, perform error processing.
• The receive data load flag bit (SSR1 register bit 12: RDRF) is cleared to "0" when receive data is read.
● Detecting the start bit
Implement the following settings to detect the start bit:
• Set the communication line level to H (attach the mark level) before the communication period.
• Specify reception permission (RXE = H) while the communication line level is H (mark level).
• Do not specify reception permission (RXE = H) for periods other than the communication period
(without mark level). Otherwise, data is not received correctly.
• After the stop bit is detected (the RDRF flag is set to "1"), specify reception inhibition (RXE = L) while
the communication line level is H (mark level).
Figure 14.6-2 Example of normal operation
Communication period
Non-communication period
Mark level
SIN
Start bit
ST
Non-communication period
Stop bit
Data
D0
D1
D0
D1
D2
D3
D4
D5
D6
D7
SP
(Sending 01010101B)
RXE
Receive clock
Sampling clock
Receive clock (8 pulse)
Recognition by the microcontroller
ST
Generating sampling clocks by dividing the receive clock by 16
D2
D3
D4
D5
D6
D7
SP
(Receiving 01010101B)
Note that specifying reception permission at the timing shown below obstructs the correct recognition of
the input data (SIN) by the microcontroller.
• Example of operation if reception permission (RXE = H) is specified while the communication line
level is L.
408
CHAPTER 14 UART1
Figure 14.6-3 Example of abnormal operation
Communication period
Non-communication period
Mark level
Start bit
SIN
(Sending 01010101B)
RXE
Non-communication period
Stop bit
Data
ST
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
SP
SP
Receive clock
Sampling clock
Recognition by the microcontroller
ST recognition
(Receiving 10101010B)
PE,ORE,FRE
Occurrence of a reception error
● Stop bit
During transmission, one bit or two bits can be selected. However, the receive side always detects only the
first bit.
● Error detection
• In operation mode 0 (asynchronous normal mode), parity, overrun, and frame errors can be detected.
• In operation mode 1 (asynchronous multiprocessor mode), overrun and frame errors can be detected, but
parity errors cannot be detected.
● Parity bit
A parity bit can be set only in operation mode 0 (asynchronous normal mode). The parity addition enable
bit (SCR1 register bit 15: PEN) is used to specify whether there is parity or not, and the parity select bit
(SCR1 register bit 14: P) is used to select odd or even parity.
There is no parity bit in operation modes 1 (asynchronous multiprocessor mode).
The transmit/receive data when the parity bit enabled are shown in Figure 14.6-4.
Figure 14.6-4 Transmit/Receive Data when Parity Bit Enabled
When receiving
SIN1
ST
SP
1
When transmitting
SOT1
1
1
0
0
1
0
1
ST
1
When transmitting
SOT1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
Data
ST : Start bit
SP : Stop bit
Note : Parity bit cannot be set in operation mode 1.
0
SP
Transmission with even parity
(SCR1: PEN = 1, P = 0)
SP
Transmission with odd parity
(SCR1: PEN = 1, P = 1)
0
ST
1
Parity error at reception
with even parity
(SCR1: PEN = 1, P = 0)
1
Parity
409
CHAPTER 14 UART1
14.6.2
Operation in Clock Synchronous Mode
(Operation Mode 2)
When the UART1 is used in operation mode 2, the transfer mode is clock synchronous.
■ Operation in Clock Synchronous Mode (Operation Mode 2)
● Format of transmit/receive data
In the clock synchronous mode, 8-bit data is transmitted/received on LSB-first, and the start and stop bits
are not added.
Figure 14.6-5 shows the transmit/receive data format for the clock synchronous mode.
Figure 14.6-5 Format of Transmit/Receive Data (Operation Mode 2)
Outputting serial clock for transmitting
Mark level
SCK1 output
SOT1
(LSB)
1
0
1
1
0
0
1
0
(MSB)
Transmit data
Write transmit data
TXE
Inputting serial clock for receiving
Mark level
SCK1 input
SIN1
(LSB)
1
0
1
1
0
0
Receive data
RXE
Read receive data
410
1
0
(MSB)
CHAPTER 14 UART1
● Clock supply
In the clock synchronous mode, count of clocks equal to the transmit and receive bits count must be
supplied.
• When the internal clock (dedicated baud rate generator or internal timer) has already selected (SMR1
register bit 5 to 3: CS2 to CS0 = 000B to 101B or 110B) and data is transmitted, the synchronous clock
for data reception is generated automatically.
• When the external clock has already selected (SMR1 register bit 5 to 3: CS2 to CS0 = 111B), the clock
for exact one byte must be supplied from outside after ensuring that data is present (SSR1 register bit
11: TDRE = 0) in the serial output data register 1 (SODR1). Also, before and after transmitting, always
return to the mark level ("H" level).
● Error detection
Only overrun errors can be detected; parity and framing errors cannot be detected.
● Setting of register
Table 14.6-2 shows the setting of the control register in transmitting serial data from the transmitting end to
the receiving end using the clock synchronous mode (operation mode 2).
Table 14.6-2 Setting of Control Register
Setting
Register Name
Serial mode
register 1 (SMR1)
Serial control
register 1 (SCR1)
Bit Name
MD1,
MD0
Receive End
(input serial clock)
Set clock synchronous mode (MD1, MD0 = 10B).
CS2, CS1,
CS0
Set clock input source.
• Dedicated baud rate generator
(CS2 to CS0 = 000B to 101B)
• Internal timer (CS2 to CS0 = 110B)
Set clock input source.
• External clock
(CS2 to CS0 = 111Bx)
SCKE
Set serial clock output
(SCKE = 1).
Set serial clock input
(SCKE = 0).
SOE
Set serial data output pin
(SOE = 1).
Set general-purpose I/O port (SOE = 0).
PEN
Do not add parity bit (PEN = 0).
CL
REC
Serial status
register 1 (SSR1)
Transmit End
(output serial clock)
8-bit data length (CL = 1)
Initialize error flag (REC = 0).
TXE
Enable transmitting (TXE = 1).
Disable transmitting (TXE = 0).
RXE
Disable receiving (RXE = 0).
Enable receiving (RXE = 1).
TIE
Enable transmitting interrupt (TIE = 1)
Disable transmitting interrupt (TIE = 0)
RIE
Disable receiving interrupt (RIE = 0).
Enable receiving interrupt (RIE = 1).
411
CHAPTER 14 UART1
● Starting communications
When send data is written to the serial output data register 1 (SODR1), communication is started. When
starting communication only in receiving, it is always necessary to write dummy send data to the serial
output data register 1 (SODR1).
● Terminating communications
After transmitting and receiving of one frame of data, the receive data load flag bit (SSR1 register bit 12:
RDRF) is set to "1". When data is received, check the overrun error flag bit (SSR1 register bit 14: ORE) to
ensure that the communication has performed normally.
412
CHAPTER 14 UART1
14.6.3
Bidirectional Communication Function (Operation
Modes 0 and 2)
In operation modes 0 and 2 (asynchronous normal mode, clock synchronous mode),
normal serial bidirectional communications using 1-to-1 connection can be performed.
For operation mode 0 (asynchronous normal mode), the asynchronous mode is used;
for operation mode 2 (clock synchronous mode), the clock synchronous mode is used.
■ Bidirectional Communication Function
To operate the UART1 in the operation mode 0, 2 (asynchronous normal mode, clock synchronous mode),
shown in Figure 14.6-6 is required.
Figure 14.6-6 Setting of Operation Modes 0, 2 (Asynchronous Normal Mode and Clock Synchronous
Mode) for UART1
SCR1, SMR1
Operation mode 0 →
Operation mode 2 →
bit15
14
13
12
11
10
9
bit8
bit7
6
5
4
PEN
P
SBL
CL
AD
REC
RXE
TXE
MD1
MD0
CS2
CS1
0
X
X
1
X
X
0
0
0
1
0
0
ORE
FRE
RDRF
TDRE
−
PE
SSR1,
SIDR1/SODR1
Operation mode 0 →
Operation mode 2 → X
RIE
TIE
3
2
1
CS0 Reser SCKE
ved
bit0
SOE
0
0
Setting of transmit data (at write) /
Retention of receive data (at read)
X
DDR Port direction register
−: Unused bit
: Used bit
X: Undefined bit
1: Set 1
0: Set 0
Set the bit to "0" corresponding to pin
used as SIN1 and SCK1 input pins.
● Inter-CPU connect
Connect the two CPUs as shown in Figure 14.6-7.
Figure 14.6-7 Example of Bidirectional Communication Connect for UART1
SOT1
SOT
SIN1
SCK1
CPU-1
SIN
Output
Input
SCK
CPU-2
413
CHAPTER 14 UART1
● Communication procedure
Communications start at any timing from the transmitting end when transmit data is provided. At the
transmitting end, set transmit data in the serial output data register (SODR1) and set the transmitting enable
bit in the serial control register (SCR1 register bit 8: TXE) to "1" to start transmitting.
Figure 14.6-8 gives an example of transferring receive data to the transmitting end to inform the
transmitting end of normal reception.
Figure 14.6-8 Flowchart for Bidirectional Communication
(Transmit end)
(Receive end)
Start
Start
Set the operation mode
(0 or 2)
Set the operation mode
(same as transmit end)
Set the 1-byte data in
SODR1
Data transmission
NO
Receive data
presence
YES
NO
Receive data
presence
Read and process
receive data
YES
Read and process
receive data
414
Data transmission
Transmit 1-byte data
CHAPTER 14 UART1
14.6.4
Master/Slave Type Communication Function
(Multiprocessor Mode)
Operation mode 1 (asynchronous multiprocessor mode) enables communications by
the master/slave type connection of more than one CPU. Only the master CPU functions.
■ Master/Slave Type Communication Function
To operate the UART1 in operation mode 1 (asynchronous multiprocessor mode), the setting shown in
Figure 14.6-9 is required.
Figure 14.6-9 Setting of Operation Mode 1 (Asynchronous Multiprocessor Mode) for UART1
bit15
SCR1, SMR1
SSR1,
SIDR1/SODR1
14
PEN
P
0
X
PE
ORE
13
12
SBL
CL
11
10
AD
REC
1
FRE
RDRF
9
RXE
bit8
TXE
0
TDRE
−
RIE
TIE
bit7
6
MD1
MD0
0
1
5
CS2
4
CS1
3
2
1
ReSCKE
CS0
served
0
bit0
SOE
0
Setting of transmit data (at write)/
Retention of receive data (at read)
X
DDR Port direction register
−: Unused bit
: Used bit
X: Undefined bit
1: Set 1
0: Set 0
Set the bit to "0" corresponding to pin
used as SIN1 and SCK1 input pins.
● Inter-CPU connect
One master CPU and more than one slave CPU are connected to two common communication lines to
compose the communication system. The UART1 can be used only as the master CPU.
Figure 14.6-10 Example of Master/Slave Type Communication Connect for UART1
SOT1
SIN1
Master CPU
SOT
SIN
Slave CPU #0
SOT
SIN
Slave CPU #1
415
CHAPTER 14 UART1
● Function select
At master/slave type communication, select the operation mode and data transfer type.
Since the parity check function cannot be used in operation mode 1 (asynchronous multiprocessor mode),
set the parity add enable bit (SCR1 register bit 15: PEN) to "0".
Table 14.6-3 Select of Master/Slave Type Communication Function
Operation Mode
Master
CPU
Address
transmit/
receive
Data
transmit/
receive
Operation
mode 1
Slave
CPU
−
Data
A/D = 1
+
8-bit address
A/D = 0
+
8-bit data
Parity
Synchronous
System
Stop Bit
Not
provided
Asynchronous
1 bit or 2 bits
● Communication procedure
Communications start when the master CPU transmits address data.
The address data is data with the A/D bit set to "1". The address/data select bit (SCR1 register bit 11: A/D)
is added to select the slave CPU that the master CPU communicates with. When the program identifies
address data and finds a match with the allocated address, each slave CPU starts communications with the
master CPU.
Figure 14.6-11 shows the flowchart for master/slave type communications.
416
CHAPTER 14 UART1
Figure 14.6-11 Flowchart for Master/Slave Type Communications
(Master CPU)
Start
Select the operation
mode 1 (asynchronous
multiprocessor mode)
Set 1-byte data (address
data) that selects the
slave CPU to D0 to D7
to transmit (A/D = 1)
Set 0 to A/D
Reception enabled
Communicate
with slave CPU
Communication
ended?
NO
YES
Communicate
with other slave
CPU
NO
YES
Reception disabled
End
417
CHAPTER 14 UART1
14.7
Precautions when Using UART1
Use of the UART1 requires the following cautions.
■ Precautions when Using UART1
● Enabling sending and receiving
The send enable bit (SCR1 register bit 8: TXE) and receive enable bit (SCR1 register bit 9: RXE) are
provided for sending and receiving.
• In the initial state after reset, both sending and receiving are disabled (SCR1 register bit 8: TXE = 0, bit
9: RXE = 0). Therefore, it is necessary to enable sending and receiving.
• Sending and receiving are disabled to stop (SCR1 register bit 8: TXE = 0, bit 9: RXE = 0).
● Setting operation mode
Set the operation mode after disabling sending and receiving (SCR1 register bit 8: TXE = 0, bit 9: RXE =
0). When the operation mode is changed during sending and receiving, the sent and received data is not
assured.
● Clock synchronous mode
Operation mode 2 (clock synchronous mode) is set as the clock synchronous mode. Send and receive data
do not have the start and stop bits.
● Timing of enabling send interrupt
The initial value after reset of the send data write enable flag bit (SSR1 register bit 11: TDRE) is set at 1
(no send data, send data write enabled). Therefore, the send interrupt is enabled (SSR1 register bit 8: TIE =
1) and a send interrupt request is issued simultaneously. Always prepare send data and enable a send
interrupt (SSR1 register bit 8: TIE = 1).
418
CHAPTER 14 UART1
14.8
Program Example for UART1
This section gives a program example for the UART1.
■ Program Example for UART1
● Processing
The bidirectional communication function (normal mode) of the UART1 is used to perform serial
transmission/reception.
• Set operation mode 0, asynchronous mode (normal), 8-bit data length, 2-bit stop bit length, and no
parity.
• Use the P40/SIN1 and P42/SOT1 pins for communications.
• Use the dedicated baud rate generator to set the baud rate to approximately 9600 bps.
• Transmit the character 13H from the SOT1 pin and receive it at an interrupt.
• Assume the machine clock (φ) 16 MHz.
419
CHAPTER 14 UART1
● Coding example
ICR13
EQU 0000BDH
; UART Transmit/receive interrupt control register
DDR1
EQU 000011H
; Port 1 data direction register
CDCR1
EQU 00001BH
; Communication prescaler register 1
SMR1
EQU 000024H
; Mode control register 1
SCR1
EQU 000025H
; Control register 1
SIDR1
EQU 000026H
; Input data register 1
SODR1
EQU 000026H
; Output data register 1
SSR1
EQU 000027H
; Status register 1
REC
EQU SCR1:2
; Receive error flag clear bit
;-----Main program--------------------------------------------------------------CODE
CSEG ABS=0FFH
START:
;
:
; Assume stack pointer (SP) already reset
AND CCR,#0BFH
; Disable interrupt
MOV I:ICR13,#00H
; Interrupt level 0 (highest priority)
MOV I:DDR1,#00000000B ; Set SIN1 as input pin.
MOV I:CDCR1,#080H
; Enable communication prescaler
MOV I:SMR1,#00010001B ; Operation mode 0 (asynchronous)
; Use dedicated baud rate generator (9615 bps)
; Disable clock pulse output and enable data output
MOV I:SCR1,#00010011B ; Without N parity. 2-bit stop bit
; Clear 8-bit data bit and receive error flag
; Enable transmitting/receiving
MOV I:SSR1,#00000010B ; Disable transmit interrupt and enable receive
; interrupt
MOV I:SODR1,#13H
; Write send data
MOV ILM,#07H
; Set ILM of PS to level 7
OR
CCR,#40H
; Enable interrupt
LOOP:
MOV A,#00H
; Infinite loop
MOV A,#01H
BRA LOOP
;-----Interruption program------------------------------------------------------WARI:
MOV A,SIDR1
; Read receive data
CLRB I:REC
; Clear receive interrupt request flag
;
:
;
Processing by user
;
:
RETI
; Return from interrupt
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG 0FF68H
; Set interrupt #37 (25H) vector
DSL WARI
ORG 0FFDCH
; Set reset vector
DSL START
DB
00H
; Set single-chip mode
VECT
ENDS
420
CHAPTER 15
CAN CONTROLLER
This chapter explains the functions and operations of
the CAN controller.
15.1 Overview of CAN Controller
15.2 Block Diagram of CAN Controller
15.3 Configuration of CAN Controller
15.4 Interrupts of CAN Controller
15.5 Explanation of Operation of CAN Controller
15.6 Precautions when Using CAN Controller
15.7 Program Example of CAN Controller
421
CHAPTER 15 CAN CONTROLLER
15.1
Overview of CAN Controller
The CAN (controller area network) is a serial communication protocol conformed to
CAN Ver. 2.0A and Ver. 2.0B. Transmitting and receiving can be performed in the
standard frame format and the extended frame format.
■ Overview of CAN Controller
• The CAN controller format conforms to CAN Ver. 2.0A and Ver. 2.0B.
• Transmitting and receiving can be performed in the standard frame format and the extended frame
format.
• Data frames can be transmitted automatically by remote frames receiving.
• The baud rate ranges from 10 kpbs to 1 Mbps (at 16-MHz machine clock frequency).
Table 15.1-1 Data Transfer Baud Rate
Machine Clock
Baud Rate
16 MHz
1 Mbps
12 MHz
1 Mbps
8 MHz
1 Mbps
4 MHz
500 kbps
2 MHz
250 kbps
• The CAN controller equips eight transmit/receive message buffers.
• The standard frame format provides transmitting and receiving with 11-bit ID and the extended frame
format 29-bit ID.
• Message data can be set from 0 byte to 8 bytes.
• Message buffer configuration can be performed at a multilevel.
• The CAN controller has two acceptance mask registers. These registers can set masks independently for
the receive message ID.
• The two acceptance mask registers can receive in the format of standard frame and extended frame.
• Four masks can be set at all bit comparison and masking, and partially at acceptance mask registers 0
and 1.
422
CHAPTER 15 CAN CONTROLLER
15.2
Block Diagram of CAN Controller
The CAN controller consists of two types of registers; one controls the CAN controller
and the other controls each message buffer.
■ Block Diagram of CAN Controller
Figure 15.2-1 Block Diagram of CAN Controller
2
Operation clock (TQ)
F MC-16LX bus
CPU
operation clock
BTR
CSR
PSC
TS1
TS2
RSJ
TOE
TS
RS
HALT
NIE
NT
NS1,0
Prescaler
(1 to 64-divided clock)
Bit timing generator
Bus state
determining
circuit
Node status transition Node status transition
interrupt signal
interrupt generator
Idle, interrupt, suspend,
transmit, receive, error,
overload
Error
controller
RTEC
Transmit/receive
sequencer
BVALR
TREQR
Sync segment
Time segment 1
Time segment 2
Transmit
buffer clear
Transmit buffer
determining circuit
Transmit
buffer
Error frame
generator
Overload
frame
generator
Acceptance
Data
counter filter controller
Transmit Receive ID select
DLC
DLC
Bit error, stuff error,
CRC error, frame error,
ACK error
Transmit buffer
TCANR
Arbitration lost
Output
driver
Pin TX
Input
latch
Pin RX
TRTRR
Transmission
shift register
RFWTR
TIER
Sets and clears transmit buffer
Transmission complete Transmission
complete
interrupt generator
interrupt signal
RCR
Sets receive buffer
TCR
RRTRR
Reception
complete
interrupt signal
Sets and clears receive buffer and transmit buffer
ROVRR
Sets receive ID select
buffer
RIER
Reception complete
interrupt generator
AMSR
AMR0
AMR1
IDR0 to 7
DLCR0 to 7
DTR0 to 7
RAM
0
1
Acceptance
filter
Receive buffer
determining circuit
Receive buffer
RAM address
generator
Stuffing
CRC
generator
Transmit DLC
ACK
generator
CRC error
Receive DLC CRC generator/error check Stuff error
Reception
shift register
Destuffing/stuffing
error check
Arbitration lost
Arbitration check
Bit error
Bit error check
ACK error
Acknowledgement
error check
Form error
Form error
check
Receive buffer, transmit buffer, receive DLC, transmit DLC, ID select
IDER
LEIR
423
CHAPTER 15 CAN CONTROLLER
The pin names in the block diagram are as follows:
TX pin: P43/TX
RX pin: P44/RX
● Bit timing register (BTR)
This register sets the division ratio at which CAN bit timing is generated.
● Control status register (CSR)
This register controls the operation of the CAN controller. It indicates the state of transmitting/receiving
and the CAN bus, controls interrupts, and controls the bus halt and indicates its state.
● Receive/transmit error counter register (RTEC)
This register indicates the number of times transmit and receive errors have occurred. It counts up when an
error occurs in transmitting and receiving messages and counts down when transmitting and receiving are
performed normally.
● Message buffer validating register (BVALR)
This register enables or disables a specified message buffer, and also indicates the enabled/disabled status.
● IDE register (IDER)
This register sets the frame format of each message buffer. It sets the standard frame format or extended
frame format.
● Transmit request register (TREQR)
This register sets a transmit request to each message buffer.
● Transmit cancel register (TCANR)
This register cancels transmit requests held in each message buffer.
● Transmit RTR register (TRTRR)
This register selects a frame format transmitted to each message buffer. It selects the data frame or remote
frame.
● Remote frame receive waiting register (RFWTR)
This register sets the condition for transmitting start when a transmit request of the data frame is set.
● Transmit complete register (TCR)
The bit is set which is corresponding to the number of the message buffer that completes message
transmitting.
424
CHAPTER 15 CAN CONTROLLER
● Transmit complete interrupt enable register (TIER)
This register controls the generation of an interrupt request when each message buffer completes
transmitting. When an interrupt is enabled, an interrupt request is generated when transmitting is
completed.
● Receive complete register (RCR)
This register sets the bit corresponding to the number of the message buffer that completes receiving
message.
● Receive complete interrupt enable register (RIER)
This register controls output of an interrupt request when each message buffer completes receiving. If
output of an interrupt request is enabled, an interrupt request is output at completion of receiving.
● Receive RTR register (RRTRR)
When a remote frame is stored in a message buffer, the bit corresponding to the number of the message
buffer is set.
● Receive overrun register (ROVRR)
This register sets the bit corresponding to the number of the message buffer that overruns when the
message is received.
● Acceptance mask select register (AMSR)
This register sets the method for masking the receive message for each message buffer.
● Acceptance mask registers (AMR0 and AMR1)
These registers set a mask with the ID for filtering the message to be received.
● Last event indication register (LEIR)
This register indicates the operating state that last occurred. It indicates that either node status transition,
transmitting completion, or receiving completion occurred.
● Prescaler
The prescaler generates a bit timing clock at a frequency of 1/1 to 1/64 of the system clock.
It sets the operation clock (TQ).
● Bit timing generator
This generator detects a bit timing clock signal to generate a sync segment and time segments 1 and 2.
● Node status transition interrupt generator
This generates a node status transition interrupt signal when the node status transits.
425
CHAPTER 15 CAN CONTROLLER
● Bus state identification circuit
This circuit identifies the CAN bus state from the bus halt bit (CSR: HALT) and the signal from the error
frame generator.
● Acceptance filter
This filter compares the receive message ID with the acceptance code to select the message to be received.
● Transmit message buffers/receive message buffers
There are 8 message buffers to store the message to be transmitted and received.
● CRC generator/ACK generator
This circuit generates a CRC field or an ACK field when a data frame or remote frame is transmitted.
426
CHAPTER 15 CAN CONTROLLER
15.3
Configuration of CAN Controller
This section explains the pins and, related registers, interrupt factors of the CAN
controller.
■ Pins of CAN Controller
Table 15.3-1 Pins of CAN Controller
Pin Name
Pin Function
Setting of Pin Used in CAN Controller
TX
Transmit output pin
General-purpose I/O port
Specify TX pin as transmit output pin
(when TOE bit in CSR register set to "1")
RX
Receive input pin
General-purpose I/O port
Specify RX pin as receive input pin
(when bit 4 in DDR4 register set to "1")
■ Block Diagram for Pins of CAN Controller
See "CHAPTER 4 I/O PORT" for details of the block diagram of pins.
427
CHAPTER 15 CAN CONTROLLER
■ CAN Controller Registers
Figure 15.3-1, Figure 15.3-2 and Figure 15.3-3 list the registers of the CAN controller.
Figure 15.3-1 Registers of CAN Controller (Control Registers)
CAN controller control register
bit 15
bit 8
bit 7
bit 0
Reset value
00000000 B
Reserved area*
BVALR (Message buffer enable register)
Reserved area*
TREQR (Transmission request register)
00000000 B
Reserved area*
TCANR (Transmission cancel register)
00000000 B
Reserved area*
TCR (Transmission complete register)
00000000 B
Reserved area*
RCR (Reception complete register)
00000000 B
Reserved area*
RRTRR (Reception RTR register)
00000000 B
Reserved area*
ROVRR (Reception overrun register)
00000000 B
Reserved area*
RIER (Reception complete interrupt enable register)
00000000 B
bit 15
bit 8
bit 7
bit 0
CSR (Control status register)
Reserved area*
Reset value
00XXX000 B
0XXXX001B
000XX000B
LEIR (Last event indicate register)
RTEC (Receive/transmit error counter)
00000000 B
00000000 B
BTR (Bit timing register)
X1111111 B
11111111 B
Reserved area*
IDER (IDE register)
XXXXXXXXB
Reserved area*
TRTRR(Transmission RTR register)
00000000 B
Reserved area*
RFWTR (Remote frame receive waiting register)
XXXXXXXXB
Reserved area*
TIER (Transmission complete interrupt enable register)
00000000 B
AMSR (Acceptance mask select register)
XXXXXXXXB
XXXXXXXXB
AMR0 (Acceptance mask register 0)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
AMR1 (Acceptance mask register 1)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Reserved area*
*: Reserved area cannot be used because address is used in the system.
428
CHAPTER 15 CAN CONTROLLER
Figure 15.3-2 Registers of CAN Controller (ID Register and DLC Register)
Message buffer (ID register)
bit 15
bit 8
bit 7
bit 0
~
XXXXXXXXB
IDR0 (ID register 0)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IDR1 (ID register 1)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IDR2 (ID register 2)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IDR3 (ID register 3)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IDR4 (ID register 4)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IDR5 (ID register 5)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IDR6 (ID register 6)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IDR7 (ID register 7)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
RAM (General-purpose RAM) (16 bytes)
Message buffer (DLC register)
bit 15
Reset value
XXXXXXXXB
~
bit 8
bit 7
bit 0
Reserved area*
DLC0 (DLC register 0)
Reset value
XXXXXXXXB
Reserved area*
DLC1 (DLC register 1)
XXXXXXXXB
Reserved area*
DLC2 (DLC register 2)
XXXXXXXXB
Reserved area*
DLC3 (DLC register 3)
XXXXXXXXB
Reserved area*
DLC4 (DLC register 4)
XXXXXXXXB
Reserved area*
DLC5 (DLC register 5)
XXXXXXXXB
Reserved area*
DLC6 (DLC register 6)
XXXXXXXXB
Reserved area*
DLC7 (DLC register 7)
XXXXXXXXB
*: Reserved area cannot be used because address is used in the system .
429
CHAPTER 15 CAN CONTROLLER
Figure 15.3-3 Registers of CAN Controller (DTR Register)
Message buffer (DTR register)
bit 15
bit 8
bit 7
bit 0
Reset value
DTR0 (Data register 0) (8 bytes)
XXXXXXXXB
~
~
XXXXXXXXB
DTR1 (Data register 1) (8 bytes)
XXXXXXXXB
~
~
XXXXXXXXB
DTR2 (Data register 2) (8 bytes)
XXXXXXXXB
~
~
XXXXXXXXB
DTR3 (Data register 3) (8 bytes)
XXXXXXXXB
~
~
XXXXXXXXB
DTR4 (Data register 4) (8 bytes)
XXXXXXXXB
~
~
XXXXXXXXB
DTR5 (Data register 5) (8 bytes)
XXXXXXXXB
~
~
XXXXXXXXB
DTR6 (Data register 6) (8 bytes)
XXXXXXXXB
~
~
XXXXXXXXB
DTR7 (Data register 7) (8 bytes)
XXXXXXXXB
~
~
XXXXXXXXB
Reserved area* (128 bytes)
*: Reserved area cannot be used because address is used in the system .
■ Generation of Interrupt Request by CAN Controller
The CAN controller has a transmit complete interrupt, receive complete interrupt, and node status interrupt.
Each interrupt request is generated by the following causes:
• When a transmit complete interrupt is enabled for the message buffer (x) (TIER: TIEx = 1), the TCx bit
in the transmit complete register is set to "1" and a transmit complete interrupt request is generated after
a completion of message transmitting.
• When a receive complete interrupt is enabled for the message buffer (x) (RIER: RIEx = 1), the RCx bit
in the receive complete register is set to "1" and a receive complete interrupt request is generated after a
completion of message receiving.
• When a node status transition interrupt is enabled (CSR: NIE = 1), the NT bit in the CAN status register
is set to "1" and a node status transition interrupt request is generated after the node status transits.
430
CHAPTER 15 CAN CONTROLLER
15.3.1
Control Status Register (High) (CSR: H)
The control status register (CSR) controls operation of the CAN controller. The control
status register (High) (CSR: H) transmits and receives the message and indicates the
node status.
■ Control Status Register (High) (CSR: H)
Figure 15.3-4 Control Status Register (High) (CSR: H)
Address:
003D01H
15
14
13
12
11
10
9
8
Reset value
00XXX000B
R
R
⎯
⎯
⎯ R/W
R
R
bit 9 bit 8
NS1 NS0
0
0
0
1
1
0
1
1
Node status bits
Error active
Warning (error active)
Error passive
Bus off
bit 10
Node status transition flag
NT
No node status transition
0
Node status transition
1
bit 14
Receive status bit
RS
Message is not received
0
Message is being received
1
R/W
R
X
⎯
:
:
:
:
:
Read/Write
Read only
Undefined
Unused
Reset value
bit 15
Transmit status bit
TS
Message is not transmitted
0
Message is being transmitted
1
Note:
It is prohibited to execute a bit operation (read-modify-write; RMW) instruction on the lower 8 bits of
control status register (CSR). Only in the case of HALT bits unchanged, use any bit operation
instructions without problems (initialization of the macro instructions, etc.).
431
CHAPTER 15 CAN CONTROLLER
Table 15.3-2 Functions of Control Status Register (High) (CSR: H)
Bit Name
Function
bit 15
TS:
Transmit status bit
This bit indicates whether the message is being transmitted.
Message being transmitted: Bit is set to "1".
Error frame or overload frame being transmitted: Bit is set to "0".
bit 14
RS:
Receive status bit
This bit indicates whether the message is being received.
Message being received: Bit is set to "1".
For example, if the message is on the bus, even during message transmitting,
this bit is set to "1" regardless of whether the receive message passes the
acceptance filter.
Error frame or overload frame on bus: Bit is set to "0".
• When the RS bit is "0", the bus halt state (HALT = 1), bus intermission
state and bus idle state are also included.
bit 13 to bit 11
432
Unused bits
Read: Value not fixed
Write: No effect
bit 10
NT:
Node status transition
flag bit
This bit indicates that the node status transits.
When node status transits: Bit is set to "1"
1. Error active (00B) --> Warning (01B)
2. Warning (01B) --> Error Passive (10B)
3. Error Passive (10B) --> Bus off (11B)
4. Bus off (11B) --> Error active (00B)
(The parenthesized values are those for the NS1 and NS0 bits.)
When set to "0": Clears this bit.
When set to "1": Disables bit setting
Read using read modify write (RMW) instructions: "1" is always read.
bit 9,
bit 8
NS1, NS0:
Node status bits
The combination of the NS1 and NS0 bits indicates the current node status.
00B: Error active
01B: Warning (error active)
10B: Error passive
11B: Bus off
Note: Warning is included in error active in the CAN specifications as a node
status.
CHAPTER 15 CAN CONTROLLER
15.3.2
Control Status Register (Low) (CSR: L)
The control status register (CSR) controls operation of the CAN controller. The control
status register (Low) (CSR: L) enables and disables transmit interrupt and node status
transition interrupt, controls bus halt and indicates the node status.
■ Control Status Register (Low) (CSR: L)
Figure 15.3-5 Control Status Register (Low) (CSR: L)
Address:
003D00H
7
6
5
4
3
R/W
⎯
⎯
⎯
⎯ R/W
2
1
0
Reset value
0XXXX001B
W R/W
bit 0
HALT
Bus operation stop bit
0
Cancels bus operation stop
(bus operation not in stop state)
1
Stops bus operation
(bus operation in stop state)
bit 1
Reserved
0
Reserved bit
Always set "0"
bit 2
NIE
0
1
Node status transition interrupt output enable bit
Interrupt output disable by node status transition
Interrupt output enable by node status transition
bit 7
R/W
W
X
⎯
:
:
:
:
:
Read/Write
Write only
Undefined
Unused
Reset value
TOE
0
1
Transmit output enable bit
Used as general-purpose I/O port
Used as transmit pin TX
Note:
It is prohibited to execute a bit operation (read-modify-write; RMW) instruction on the lower 8 bits of
control status register (CSR). Only in the case of HALT bits unchanged, use any bit operation
instructions without problems (initialization of the macro instructions, etc.).
433
CHAPTER 15 CAN CONTROLLER
Table 15.3-3 Functions of Control Status Register (Low) (CSR: L) (1/2)
Bit Name
bit 7
TOE:
Transmit output enable
bit
This bit switches between the general-purpose I/O port and the transmit pin
(TX).
When set to "0": Functions as general-purpose I/O port
When set to "1": Functions as transmit pin (TX)
Unused bits
Read: Value is undefined
Write: No effect
bit 2
NIE:
Node status transition
interrupt output enable
bit
This bit controls generation of a node status transition interrupt when the
node status transits (CSR: NT = 1).
When set to "0": Disables interrupt generation
When set to "1": Enables interrupt generation
bit 1
Reserved: Reserved bit
Always set this bit to "0".
Read: "0" is always read.
bit 6 to bit 3
434
Function
CHAPTER 15 CAN CONTROLLER
Table 15.3-3 Functions of Control Status Register (Low) (CSR: L) (2/2)
Bit Name
bit 0
HALT:
Bus halt bit
Function
This bit controls the bus halt. The halt state of the bus can be checked by
reading this bit.
Writing to this bit
0: Cancels bus operation stop
1: Sets bus operation stop
Reading this bit
0: Bus operation not in stop state
1: Bus operation in stop state
Note: When write 0 to this bit during the node status is Bus Off, ensure that
"1" is written to this bit.
Example program:
switch ( IO_CANCT0.CSR.bit.NS )
{
case 0 : /* error active */
break;
case 1 : /* warning */
break;
case 2 : /* error passive */
break;
default : /* bus off */
for ( i=0; ( i <= 500 ) && ( IO_CANCT0.CSR.bit.
HALT == 0); i++);
IO_CANCT0.CSR.word = 0x0084; /* HALT = 0 */
break;
}
Note: The variable "i" is used for fail-safe.
[Condition of stopping Bus operation]
•
•
•
Hardware reset
Transition to mode status of bus
Writing of "1" in HALT bit
[About the operation when the bus operation is stopped]
In message transmission: After the transmission operation ends, it stops.
While receiving the message: It stops at once.
While storing the message buffer: After the storage of the message ends, it stops.
(Notes)
• Please read the value of the HALT bit to confirm whether the bus operation has
stopped.
• Please change after confirming the HALT bit is read after "1" is written in the
HALT bit and the bus operation on stopped completely when changing to the low
power consumption mode.
[Conditions for canceling bus halt]
• The state in which the bus is halted by a hardware reset or by writing 1 to
the HALT bit is canceled after "0" is written to the HALT bit and an 11-bit
"H" level (receive) is input continuously to the receive input pin (RX).
• The state in the bus off is canceled after "0" is written to the HALT bit and
an 11-bit "H" level (receive) is input continuously 128 times to the receive
input pin (RX).
• The values of the transmit and receive error counters are both returned to
"0" and the node status transits to error active.
• When you write "0" to this bit during Bus Off, ensure that "1" is read from
this bit and then write "0".
[State in which bus halted]
• Transmitting and receiving are not performed.
• A "H" level (receive) is output to the transmit output pin (TX).
• Values of other register and error counter remain unchanged.
Note: Set the bit timing register (BTR) after halting the bus.
435
CHAPTER 15 CAN CONTROLLER
15.3.3
Last Event Indicate Register (LEIR)
This register indicates the state of the last event.
■ Last Event Indicate Register (LEIR)
Figure 15.3-6 Last Event Indicate Register (LEIR)
Address: bit 7
003D02H
6
5
4
R/W R/W R/W ⎯
3
2
1
0
Reset value
000XX000B
⎯ R/W R/W R/W
bit 2
MBP2
0
0
0
0
1
1
1
1
bit 1
MBP1
0
0
1
1
0
0
1
1
bit 0
MBP0
0
1
0
1
0
1
0
1
Message buffer pointer bits
Message buffer 0
Message buffer 1
Message buffer 2
Message buffer 3
Message buffer 4
Message buffer 5
Message buffer 6
Message buffer 7
bit 5
RCE
0
1
Last event = reception complete bit
Reception is not completed.
Reception is completed.
bit 6
TCE
0
1
Last event = transmission complete bit
Transmission is not completed.
Transmission is completed.
bit 7
R/W : Read/Write
X
: Undefined
⎯
: Unused
: Reset value
NTE
0
1
Last event = node status transition bit
Not node status transition
Node status transition
Note:
When any of the node status transition bit (NTE), transmission complete bit (TCE), and reception
complete bit (RCE) corresponding to the last event is set to "1", other bits are set to "0".
436
CHAPTER 15 CAN CONTROLLER
Table 15.3-4 Functions of Last Event Indicate Register (LEIR)
Bit Name
Function
bit 7
NTE:
Last event node status
transition bit
This bit indicates that the last event refers to the node status transition.
Last event referring to node status transition:
Sets bit to "1" when NTx bit in control status register set (CSR: NTx = 1)
• The NTE bit is set to "1" at the same time that the TCx in the transmission
complete register (TCR) is set.
• Nothing is related to the setting of the NIE bit in the control status register
(CSR).
When set to "0": Cleared
When set to "1": No effect
Read by read modify write (RMW) instruction: "1" is always read.
bit 6
TCE:
Last event transmission
complete bit
This bit indicates that the transmitting the last event is completed.
Transmitting of last event completed:
Sets bit to "1" when TCx bit in transmission complete register set (TCR: TCx = 1)
• Nothing is related to the setting of the transmission complete interrupt enable
register (TIER).
• The number (x) of the message buffer that completes receiving the message is
indicated as the last event in the MBP2 to MBP0 bits.
When set to "0": Cleared
When set to "1": No effect
Read using read modify write (RMW) instruction: "1" is always read.
bit 5
RCE:
Last event reception
complete bit
This bit indicates that receiving the last event is completed.
Receiving of last event completed:
Sets bit to "1" when RCx bit in reception complete register set (RCR: RCx = 1)
• Nothing is related to the setting of the reception complete interrupt enable
register (RIER).
• The number (x) of the message buffer that completes receiving the message is
indicated as the last event in the MBP2 to MBP0 bits.
When set to "0": Cleared
When set to "1": No effect
Read using read modify write (RMW) instructions: "1" always read
bit 4,
bit 3
Unused bits
Read: Value is not fixed.
Write: No effect on operation
MBP2 to MBP0:
Message buffer pointer
bits
These bits indicate the number (x) of the message buffer where the last event
occurs which is corresponding to each message buffer pointer bit.
Receiving completed:
Indicates number (x) of message buffer that completes
receiving message
Transmitting completed: Indicates number (x) of message buffer that completes
transmitting message
Node status transition: The values of the MBP2 to MBP0 bits are invalid.
When set to "0": Cleared
When set to "1": No effect
Read by read modify write (RMW) instruction: "1" is always read.
bit 2 to bit 0
Note:
When the last event indicate register (LEIR) is accessed in interrupt processing of the CAN
controller, the event causing the interrupt does not always match the event indicated by the last
event indicate register (LEIR). Other event may occur before the last event indicate register (LEIR) is
accessed in interrupt processing after an interrupt request is generated.
437
CHAPTER 15 CAN CONTROLLER
15.3.4
Receive/Transmit Error Counter (RTEC)
The receive/transmit error counter (RTEC) indicates the number of times an error
occurs at transmitting and receiving the message. It counts up when transmit or receive
errors occurs and counts down when transmitting and receiving are performed
normally.
■ Receive/Transmit Error Counter (RTEC)
Figure 15.3-7 Receive/Transmit Error Counter (RTEC)
Address:
003D05H
Address:
003D04H
bit 15
14
13
12
11
10
9
8
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
R
R
R
R
R
R
R
R
Reset value
00000000B
Reset value
00000000B
R: Read only
Table 15.3-5 Functions of Receive/Transmit Error Counter (RTEC)
Bit Name
Function
bit 15 to bit 8
TEC7 to TEC0:
Transmit error counter
bits
Transmit error counter value = 96 or more :
Node status transits to warning (CSR: NS1, NS0 = 01B)
Transmit error counter value = 128 or more :
Node status transits to error passive (CSR: NS1, NS0 = 10B)
Transmit error counter value = 256 or more :
Stops counting up. The node status transits to bus off
(CSR: NS1, NS0 = 11B).
bit 7 to bit 0
REC7 to REC0:
Receive error counter
bits
Receive error counter value = 96 or more:
Node status transits to warning (CSR: NS1, NS0 = 01B)
Receive error counter value = 128 or more:
Node status transits to error passive (CSR: NS1, NS0 = 10B)
Receive error counter value = 256 or more:
Stops counting up. The node status remains with error passive (CSR:
NS1, NS0= 10B).
438
CHAPTER 15 CAN CONTROLLER
■ Node Status Transition due to Error Occurrence
In the CAN controller, the node status transits according to the error count of the receive/transmit error
counter (RTEC). Figure 15.3-8 shows the node status transition.
Figure 15.3-8 Node Status Transition
Hardware reset
Cancellation of bus operation halt is necessary for transition
Error active
REC: Receive error counter
TEC: Transmit error counter
REC ≥ 96
or TEC ≥ 96
REC < 96
besides TEC < 96
Warning
(error active)
After 0 was written to the HALT
bit of the control status register (CSR),
continuous 11-bit "H" levels (receive)
are input 128 times to the receive input
pin (RX) to transit.
REC ≥ 128
or TEC ≥ 128
REC < 128
besides TEC < 128
Error passive
TEC ≥ 256
Bus off
(HALT = 1)
Table 15.3-6 Node Status
Node Status
Error active
State of CAN Bus
Normal state
Warning
A bus fault occurs
Error passive
Bus off
Communications are disabled. The CAN controller is completely isolated
from the CAN bus.
(To return to the normal state, perform the steps in the above figure.)
439
CHAPTER 15 CAN CONTROLLER
15.3.5
Bit Timing Register (BTR)
The bit timing register (BTR) sets the prescaler and bit timing after halting the bus
(CSR: HALT = 1).
■ Bit Timing Register (BTR)
Figure 15.3-9 Bit Timing Register (BTR)
Address:
003D07H
Address:
003D06H
bit 15
Reset value
X1111111B
-
14
13
12
11
10
9
8
TS2.2 TS2.1 TS2.0 TS1.3 TS1.2 TS1.1 TS1.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
RSJ1
R/W
6
5
4
3
2
1
0
RSJ0 PSC5 PSC4 PSC3 PSC2 PSC1 PSC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
11111111B
R/W: Read/Write
X : Undefined
: Unused
Table 15.3-7 Functions of Bit Timing Register (BTR)
Bit Name
Function
bit 14
to
bit 12
TS2.2 to TS2.0:
Time segment 2 setting
bits 2 to 0
These bits set the time of time segment 2 (TSEG2). Time segment "2" is
equivalent to phase buffer segment 2 (PHASE_SEG2) based on CAN
specifications.
bit 11
to
bit 8
TS1.3 to TS1.0:
Time segment 1 setting
bits 3 to 0
These bits set the time of time segment 1 (TSEG1). Time segment "1" is
equivalent to propagation segment (PROP_SEG) and phase buffer segment
1 (PHASE_SEG1) based on CAN specifications.
bit 7,
bit 6
RSJ1, RSJ0:
Resynchronous jump
width setting bits 1, 0
These bits set the resynchronous jump width (RSJW).
PSC5 to PSC0:
Prescaler setting bits 5 to 0
These bits divide the frequency of the system clock to determine the time
quantum (TQ) of the CAN controller.
bit 5 to bit 0
Note: Set the bit timing register (BTR) after halting the bus (CSR: HALT = 1). After setting the bit timing register (BTR),
write 0 to the HALT bit in the control status register to cancel the bus halt.
440
CHAPTER 15 CAN CONTROLLER
■ Definition of Bit Timing Segment
Bit timing is set in the bit timing register (BTR). Figure 15.3-10 and Figure 15.3-11 show the segments of
the nominal bit time (one bit of time within message) and bit timing register (BTR).
● Bit time segments of general CAN specifications
Figure 15.3-10 Bit Time Segments of General CAN Specifications
Nominal bit time
SYNC_SEG
(Sync segment)
PROP_SEG
(Propagation segment)
PHASE_SEG1
(Phase segment 1)
PHASE_SEG2
(Phase segment 2)
Sampling point
• SYNC_SEG (sync segment): Synchronization is performed to shorten or prolong the bit time.
• PROP_SEG (propagation segment): The physical delay among networks is adjusted.
• PHASE_SEG (phase segment): The phase shift due to oscillation errors is adjusted.
● Bit time segments of Fujitsu CAN controller
The propagation segment (PROP_SEG) and phase segment 1 (PHASE_SEG1) are used as the time
segment 1 (TSEG1). The phase segment 2 (PHASE_SEG2) is used as the time segment 2 (TSEG2).
Figure 15.3-11 Bit Time Segments of CAN Controller
Nominal bit time
SYNC_SEG
(Sync segment)
TSEG1
(Time segment 1)
TSEG2
(Time segment 2)
Sampling point
• TSEG1 = PROP_SEG + PHASE_SEG1
• TSEG2 = PHASE_SEG2
441
CHAPTER 15 CAN CONTROLLER
■ Calculation of Bit Timing
Figure 15.3-12 and Figure 15.3-13 show the calculation example of bit timing, respectively, assuming input
clock (CLK), time quantum (TQ), bit time (BT), synchronous segment (SYNC_SEG), time segments 1 and
2 (TSEG1, TSEG2), resynchronous jump width (RSJW), and frequency division (PSC).
Figure 15.3-12 Calculation of Bit Timing
. TQ = (PSC + 1) × CLK
. BT = SYNC_SEG + TSEG1 + TSEG2
= (1 + (TS1 + 1) + (TS2 + 1) ) × TQ
= (3 + TS1 + TS2) × TQ
. RSJW = (RSJ + 1) × TQ
For each segment, the following conditions should be met.
. When PSC is 1 to 63 (2 to 64-divided clock)
TSEG1 ≥ 2TQ
TSEG1 ≥ RSJW
TSEG2 ≥ 2TQ
TSEG2 ≥ RSJW
. When PSC is 0 (1-divided clock)
TSEG1 ≥ 5TQ
TSEG2 ≥ 2TQ
TSEG2 ≥ RSJW
442
CHAPTER 15 CAN CONTROLLER
Figure 15.3-13 Calculation Example of Bit Timing
(1) Calculations of time quantum (TQ) [TQ = (PSC + 1) × CLK]
Frequency division of input clock (PSC+1)
10 11 12 13 14 15
9
8
7
6
5
4
3
2
1
0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75
0.13 0.25 0.38 0.5 0.63 0.75 0.88 1 1.13 1.25 1.38 1.5 1.63 1.75 1.88
0.06 0.13 0.19 0.25 0.31 0.38 0.44 0.5 0.56 0.63 0.69 0.75 0.81 0.88 0.94
(4) Conditions of bit timing (BT) [BT ≥ 8TQ]
2
1
0.5
4
2
1
6
3
1.5
8
4
2
10
5
2.5
12
6
3
14
7
3.5
8TQ
16 18
9
8
4.5
4
20
10
5
22
11
5.5
24
12
6
26
13
6.5
28
14
7
30
15
7.5
(3) Setting of resynchronous jump width (when resynchronous jump width is 4TQ)
RSJ+1 (frequency division of TQ) 1
0.5
RSJW = (RSJ + 1) × TQ
2
1
3
1.5
4
2
2
2
1
3
3
1.5
4
4
2
(5) Conditions of TSEG2
RSJW = (RSJ + 1) × TQ
TSEG2 ≥ RSJW
TSEG2 ≥ RSJW
1
1
0.5
(unit: kbps)
Calculation of sampling point
SYNC_SEG + (TSEG1 + 1) TSEG2 + 1
(1)
(2)
(3)
(4)
(5)
16
15
14
13
12
4
5
6
7
8
SYNC_SEG TSEG 1 + 1 TSEG2 + 1
Sampling point
Sampling
point
80%
TSEG1 + 1
75%
70%
65%
60%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
667
500
400
333
286
250
222
200
182
167
154
143
133
125
118
111
2
500
400
333
286
250
222
200
182
167
154
143
133
125
118
111
105
3
400
333
286
250
222
200
182
167
154
143
133
125
118
111
105
100
TSEG2 + 1
5
4
333 286
286 250
250 222
222 200
200 182
182 167
167 154
154 143
143 133
133 125
125 118
118 111
111 105
105 100
100 95.2
95.2 90.9
(1) (2)
6
250
222
200
182
167
154
143
133
125
118
111
105
100
95.2
90.9
87
(3)
7
222
200
182
167
154
143
133
125
118
111
105
100
95.2
90.9
87
83.3
(4)
8
200
182
167
154
143
133
125
118
111
105
100
95.2
90.9
87
83.3
80
(5)
443
CHAPTER 15 CAN CONTROLLER
15.3.6
Message Buffer Valid Register (BVALR)
The message buffer valid register (BVALR) enables or disables the message buffers and
indicates their status.
■ Message Buffer Valid Register (BVALR)
Figure 15.3-14 Message Buffer Valid Register (BVALR)
Address:
000080H
7
6
5
4
3
2
1
0
Reset value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
BVAL0
0
1
bit 1
BVAL1
0
1
bit 2
BVAL2
0
1
Message buffer enable bit 0
Disables message buffer 0
Enables message buffer 0
Message buffer enable bit 1
Disables message buffer 1
Enables message buffer 1
Message buffer enable bit 2
Disables message buffer 2
Enables message buffer 2
bit 3
Message buffer enable bit 3
BVAL3
Disables message buffer 3
0
Enables message buffer 3
1
bit 4
BVAL4
0
1
bit 5
BVAL5
0
1
bit 6
BVAL6
0
1
bit 7
BVAL7
R/W : Read/Write
: Reset value
444
0
1
Message buffer enable bit 4
Disables message buffer 4
Enables message buffer 4
Message buffer enable bit 5
Disables message buffer 5
Enables message buffer 5
Message buffer enable bit 6
Disables message buffer 6
Enables message buffer 6
Message buffer enable bit 7
Disables message buffer 7
Enables message buffer 7
CHAPTER 15 CAN CONTROLLER
Table 15.3-8 Functions of Message Buffer Enable Register
Bit Name
bit 7 to bit 0
BVAL7 to BVAL0:
Message buffer enable
bits 7 to 0
Function
These bits enable or disable transmitting and receiving of the message to and
from the message buffer (x).
When set to "0":No message can be transmitted and received to and from
the message buffer (x).
When set to "1":A message can be transmitted and received to and from the
message buffer (x).
[Message buffer disabled (BVALx = 0)]
During transmitting: Transmitting and receiving are disabled after message
transmitting is completed or a transmit error is
terminated.
During receiving:
Transmitting and receiving are disabled immediately.
When the received message is stored in the message
buffer, transmitting and receiving are disabled after
the message is stored.
Note: The read modify write (RMW) instructions are disabled until the
BVALx bit is actually set to "0" after "0" is written to the bit.
Note:
To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while CAN Controller is
participating in CAN communication (the read value of the CSR: HALT bit is "0" and CAN Controller
is ready to receive or transmit messages), follow the cautions in Section "15.6 Precautions when
Using CAN Controller".
445
CHAPTER 15 CAN CONTROLLER
15.3.7
IDE Register (IDER)
The IDE register (IDER) sets the frame format of the message buffer used during
transmitting and receiving. Transmitting and receiving are enabled in the standard
frame format (ID11 bits) and the extended frame format (ID29 bits).
■ IDE Register (IDER)
Figure 15.3-15 IDE Register (IDER)
Address:
003D08H
7
6
5
4
3
2
1
0
Reset value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
IDE0
0
1
bit 1
IDE1
0
1
bit 2
IDE2
0
1
bit 3
IDE3
0
1
bit 4
IDE4
0
1
bit 5
IDE5
0
1
bit 6
IDE6
0
1
bit 7
IDE7
X
: Undefined
R/W : Read/Write
446
0
1
ID format select bit 0 (message buffer 0)
Used in standard format (ID 11 bits)
Used in extended format (ID 29 bits)
ID format select bit 1 (message buffer 1)
Used in standard format (ID 11 bits)
Used in extended format (ID 29 bits)
ID format select bit 2 (message buffer 2)
Used in standard format (ID 11 bits)
Used in extended format (ID 29 bits)
ID format select bit 3 (message buffer 3)
Used in standard format (ID 11 bits)
Used in extended format (ID 29 bits)
ID format select bit 4 (message buffer 4)
Used in standard format (ID 11 bits)
Used in extended format (ID 29 bits)
ID format select bit 5 (message buffer 5)
Used in standard format (ID 11 bits)
Used in extended format (ID 29 bits)
ID format select bit 6 (message buffer 6)
Used in standard format (ID 11 bits)
Used in extended format (ID 29 bits)
ID format select bit 7 (message buffer 7)
Used in standard format (ID 11 bits)
Used in extended format (ID 29 bits)
CHAPTER 15 CAN CONTROLLER
Table 15.3-9 Functions of IDE Register (IDER)
Bit Name
bit 7 to bit 0
IDE7 to IDE0:
ID Format select bits 7 to 0
Function
These bits set the ID format of the message buffer (x).
When set to "0": Uses message buffer (x) in standard format (ID11 bits)
When set to "1": Uses message buffer (x) in extended format (ID29 bits)
Note: The IDE register (IDER) should be set after having the message
buffer (x) disabled (BVALR: BVALx = 0). Setting the IDE register
(IDER) with the message buffer (x) being enabled may store
message unnecessary received.
Note:
To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while CAN Controller is
participating in CAN communication (the read value of the CSR: HALT bit is "0" and CAN Controller
is ready to receive or transmit messages), follow the cautions in Section "15.6 Precautions when
Using CAN Controller".
447
CHAPTER 15 CAN CONTROLLER
15.3.8
Transmission Request Register (TREQR)
The transmission request register (TREQR) sets a transmit request for each message
buffer and indicates its status.
■ Transmission Request Register (TREQR)
Figure 15.3-16 Transmission Request Register (TREQR)
Address:
000082H
7
6
5
4
3
2
1
0
Reset value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
TREQ0
Transmission request bit 0 (message buffer 0)
0
1
Does not request transmission (transmission is not requested)
Requests transmission (transmission is requested)
bit 1
TREQ1
0
1
Transmission request bit 1 (message buffer 1)
Does not request transmission (transmission is not requested)
Requests transmission (transmission is requested)
bit 2
Transmission request bit 2 (message buffer 2)
TREQ2
Does not request transmission (transmission is not requested)
0
Requests transmission (transmission is requested)
1
bit 3
TREQ3
Transmission request bit 3 (message buffer 3)
0
1
Does not request transmission (transmission is not requested)
Requests transmission (transmission is requested)
bit 4
Transmission request bit 4 (message buffer 4)
TREQ4
Does
not
request transmission (transmission is not requested)
0
Requests
transmission (transmission is requested)
1
bit 5
TREQ5
Transmission request bit 5 (message buffer 5)
0
1
Does not request transmission (transmission is not requested)
Requests transmission (transmission is requested)
bit 6
Transmission request bit 6 (message buffer 6)
TREQ6
Does not request transmission (transmission is not requested)
0
Requests transmission (transmission is requested)
1
R/W : Read/Write
: Reset value
448
bit 7
Transmission request bit 7 (message buffer 7)
TREQ7
Does not request transmission (transmission is not requested)
0
Requests transmission (transmission is requested)
1
CHAPTER 15 CAN CONTROLLER
Table 15.3-10 Functions of Transmission Request Register (TREQR)
Bit Name
bit 7 to bit 0
Function
TREQ7 to TREQ0:
Transmission request
bits 7 to 0
These bits starts transmitting for the message buffer (x).
When set to "0": No effect
When set to "1": Starts transmitting for message buffer (x)
• If more than one transmit complete bit is set (TREQx = 1), transmitting is
started with the lower number of the message buffer (x) that accepts the
transmit request.
• These bits remain 1s during the transmit being requested and are cleared to
"0" when transmitting is completed or the transfer request is canceled.
• Clearing a transmit request when transmitting is completed (TREQx = 0)
overrides setting of the transmit request bit when "0" is written (TREQx = 1)
if both occur at the same time.
Read by read modify write (RMW) instruction: "1" is always read.
[Setting of remote frame receive wait bit (RFWTR: RFWTx)]
RFWTx bit = 0: Starts transmitting immediately even if RRTRx bit in receive
RTR register = 1
RFWTx bit = 1: Starts transmitting after remote frame received.
References:
• See "15.3.10 Remote Frame Receiving Wait Register (RFWTR)" for details of the remote frame
receive wait register (RFWTR).
• See "15.3.15
(RRTRR).
Reception RTR Register (RRTRR)" for details of the receive RTR register
• See "15.3.11 Transmission Cancel Register (TCANR)" and "15.5.1 Transmission" for details
about the transmit cancellation.
449
CHAPTER 15 CAN CONTROLLER
15.3.9
Transmission RTR Register (TRTRR)
This register sets the frame format of transmit message for the message buffers.
■ Transmission RTR Register (TRTRR)
Figure 15.3-17 Transmission RTR Register (TRTRR)
Address:
003D0AH
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
TRTR0
0
1
Remote frame setting bit 0
(message buffer 0)
Transmits as data frame
Transmits as remote frame
bit 1
TRTR1
0
1
Remote frame setting bit 1
(message buffer 1)
Transmits as data frame
Transmits as remote frame
bit 2
TRTR2
0
1
Remote frame setting bit 2
(message buffer 2)
Transmits as data frame
Transmits as remote frame
bit 3
TRTR3
0
1
Remote frame setting bit 3
(message buffer 3)
Transmits as data frame
Transmits as remote frame
bit 4
TRTR4
0
1
Remote frame setting bit 4
(message buffer 4)
Transmits as data frame
Transmits as remote frame
bit 5
TRTR5
0
1
Remote frame setting bit 5
(message buffer 5)
Transmits as data frame
Transmits as remote frame
bit 6
TRTR6
0
1
Remote frame setting bit 6
(message buffer 6)
Transmits as data frame
Transmits as remote frame
bit 7
TRTR7
R/W : Read/Write
: Reset value
450
0
1
Remote frame setting bit 7
(message buffer 7)
Transmits as data frame
Transmits as remote frame
CHAPTER 15 CAN CONTROLLER
• When "0" is written to each bit in the transmit RTR register (TRTRR), the data frame format is set.
When "1" is written to each bit, the remote frame format is set.
Table 15.3-11 Functions of Transmission RTR Register (TRTRR)
Bit Name
bit 7 to bit 0
TRTR7 to TRTR0:
Remote frame setting
bits 7 to 0
Function
These bits set the transfer format of the message buffer (x) for transmitting or
receiving.
When set to "0": Sets data frame format
When set to "1": Sets remote frame format
451
CHAPTER 15 CAN CONTROLLER
15.3.10
Remote Frame Receiving Wait Register (RFWTR)
Remote frame receiving wait register (RFWTR) sets whether this register waits remote
frame receiving when transmission request of data frame is set.
■ Remote Frame Receiving Wait Register (RFWTR)
Figure 15.3-18 Remote Frame Receive Wait Register (RFWTR)
Address:
003D0CH
7
6
5
4
3
2
1
0
Reset value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
RFWT0
0
1
Remote frame receiving wait bit 0
(message buffer 0)
Transmission starts immediately
Transmission starts after receiving remote frame
bit 1
RFWT1
0
1
Remote frame receiving wait bit 1
(message buffer 1)
Transmission starts immediately
Transmission starts after receiving remote frame
bit 2
RFWT2
0
1
Remote frame receiving wait bit 2
(message buffer 2)
Transmission starts immediately
Transmission starts after receiving remote frame
bit 3
RFWT3
0
1
Remote frame receiving wait bit 3
(message buffer 3)
Transmission starts immediately
Transmission starts after receiving remote frame
bit 4
RFWT4
0
1
Remote frame receiving wait bit 4
(message buffer 4)
Transmission starts immediately
Transmission starts after receiving remote frame
bit 5
RFWT5
0
1
bit 6
RFWT6
0
1
Remote frame receiving wait bit 5
(message buffer 5)
Transmission starts immediately
Transmission starts after receiving remote frame
Remote frame receiving wait bit 6
(message buffer 6)
Transmission starts immediately
Transmission starts after receiving remote frame
bit 7
RFWT7
R/W : Read/Write
: Reset value
452
0
1
Remote frame receiving wait bit 7
(message buffer 7)
Transmission starts immediately
Transmission starts after receiving remote frame
CHAPTER 15 CAN CONTROLLER
Table 15.3-12 Functions of Remote Frame Receiving Wait Register (RFWTR)
Bit Name
bit 7 to bit 0
Function
RFWT7 to RFWT0:
Remote frame receiving
wait bits 7 to 0
These bits set whether to wait for reception of a remote frame for the
message buffer (x) for which a request to transmit a data frame is set.
When set to "0":Starts transmitting immediately for message buffer (x) for
which a request to transmit data frame is set
Transmitting is started immediately even if the receive RTR register is
already set in the message buffer (x) (RRTRR: RRTRx = 1).
When set to "1":Starts transmitting after remote frame is received in
message buffer (x) in which a request to transmit a data
frame is set.
Note: When transmitting a remote frame, do not write 1 to the RFWTx bit.
References:
• See "15.3.8 Transmission Request Register (TREQR)" for details of the transmission request
register (TREQR).
• See "15.3.9 Transmission RTR Register (TRTRR)" for details of the transmission RTR register
(TRTRR).
• See "15.3.15
(RRTRR).
Reception RTR Register (RRTRR)" for details of the receive RTR register
453
CHAPTER 15 CAN CONTROLLER
15.3.11
Transmission Cancel Register (TCANR)
The transmission cancel register (TCANR) sets cancellation of a transmission request
for the message buffer in the transmit wait state.
■ Transmission Cancel Register (TCANR)
Figure 15.3-19 Transmission Cancel Register (TCANR)
Address:
000084H
7
6
5
4
3
2
1
0
W
W
W
W
W
W
W
W
Reset value
00000000 B
bit 0
TCAN0
0
1
bit 1
TCAN1
0
1
bit 2
TCAN2
0
1
bit 3
TCAN3
0
1
bit 4
TCAN4
0
1
bit 5
TCAN5
0
1
bit 6
TCAN6
0
1
bit 7
TCAN7
W
454
: Write only
: Reset value
0
1
Transmission cancel bit 0
No effect
Cancels transmission request of message buffer 0
Transmission cancel bit 1
No effect
Cancels transmission request of message buffer 1
Transmission cancel bit 2
No effect
Cancels transmission request of message buffer 2
Transmission cancel bit 3
No effect
Cancels transmission request of message buffer 3
Transmission cancel bit 4
No effect
Cancels transmission request of message buffer 4
Transmission cancel bit 5
No effect
Cancels transmission request of message buffer 5
Transmission cancel bit 6
No effect
Cancels transmission request of message buffer 6
Transmission cancel bit 7
No effect
Cancels transmission request of message buffer 7
CHAPTER 15 CAN CONTROLLER
Table 15.3-13 Functions of Transmission Cancel Register (TCANR)
Bit Name
bit 7 to bit 0
TCAN7 to TCAN0:
Transmission cancel bits
7 to 0
Function
These bits cancel a transmission request for the message buffer (x) in the
transmit wait state.
When set to "0": No effect
When set to "1": Cancels transmission request for message buffer (x)
When a transmission request is canceled by setting 1 to the TCANx bit, the
TREQx bit corresponding to the message buffer (x) is cleared (TREQx = 0)
for which transmission request is canceled.
Read: "0" is always read.
Note: The transmission cancel register (TCANR) is a write-only register.
455
CHAPTER 15 CAN CONTROLLER
15.3.12
Transmission Complete Register (TCR)
The transmission complete register (TCR) indicates whether transmitting a data from
the message buffer completes. When an output of interrupt request is enabled at
completing transmitting, an interrupt request is output when transmitting is completed.
■ Transmission Complete Register (TCR)
Figure 15.3-20 Transmission Complete Register (TCR)
Address:
000086H
7
6
5
4
3
2
1
0
Reset value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Read/Write
: Reset value
456
bit 0
TC0
0
1
Transmission is not completed/no transmission
Transmission is completed
bit 1
TC1
0
1
Transmission is not completed/no transmission
Transmission is completed
bit 2
TC2
0
1
Transmission is not completed/no transmission
Transmission is completed
bit 3
TC3
0
1
Transmission is not completed/no transmission
Transmission is completed
Transmission complete bit 0 (message buffer 0)
Transmission complete bit 1 (message buffer 1)
Transmission complete bit 2 (message buffer 2)
Transmission complete bit 3 (message buffer 3)
bit 4
TC4
0
1
Transmission is not completed/no transmission
Transmission is completed
bit 5
TC5
0
1
Transmission is not completed/no transmission
Transmission is completed
bit 6
TC6
0
1
Transmission is not completed/no transmission
Transmission is completed
bit 7
TC7
0
1
Transmission is not completed/no transmission
Transmission is completed
Transmission complete bit 4 (message buffer 4)
Transmission complete bit 5 (message buffer 5)
Transmission complete bit 6 (message buffer 6)
Transmission complete bit 7 (message buffer 7)
CHAPTER 15 CAN CONTROLLER
Table 15.3-14 Functions of Transmission Complete Register (TCR)
Bit Name
bit 7 to bit 0
TC7 to TC0:
Transmission complete
bits 7 to 0
Function
These bits indicate whether the message buffer (x) completes transmitting
message.
When message transmitting completed:
"1" is set to the TCx bit corresponding to the message buffer (x) that
completes transmitting.
When set to "0": Clears bits if transmitting is already completed.
When set to "1": No effect
Read by read modify write (RMW) instruction: "1" is always read.
• Setting the TCx bit when transmitting is completed (TCx = 1) overrides
clearing of the TCx bit when "0" is written (TCx = 0) if both occur at the
same time.
• When the TREQx bit in the transmit request register (TREQR) is set
(TREQR: TREQx = 1), the TCx bit is cleared (TCx = 0).
[Generation of transmission complete interrupt]
If the transmit complete interrupt enable register (TIER) is set (TIER: TIEx = 1),
a transmit complete interrupt is generated when transmitting is completed
(TCR: TCx = 1).
457
CHAPTER 15 CAN CONTROLLER
15.3.13
Transmission Complete Interrupt Enable Register (TIER)
The transmission complete interrupt enable register (TIER) enables or disables a
transmit complete interrupt for each message buffer.
■ Transmission Complete Interrupt Enable Register (TIER)
Figure 15.3-21 Transmission complete Interrupt Enable Register (TIER)
Address:
003D0EH
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
TIE0
0
1
Transmission interrupt enable bit 0
(message buffer 0)
Disables transmission complete interrupt
Enables transmission complete interrupt
bit 1
TIE1
0
1
Transmission interrupt enable bit 1
(message buffer 1)
Disables transmission complete interrupt
Enables transmission complete interrupt
bit 2
TIE2
0
1
Transmission interrupt enable bit 2
(message buffer 2)
Disables transmission complete interrupt
Enables transmission complete interrupt
bit 3
TIE3
0
1
Transmission interrupt enable bit 3
(message buffer 3)
Disables transmission complete interrupt
Enables transmission complete interrupt
bit 4
TIE4
0
1
Transmission interrupt enable bit 4
(message buffer 4)
Disables transmission complete interrupt
Enables transmission complete interrupt
bit 5
TIE5
0
1
Transmission interrupt enable bit 5
(message buffer 5)
Disables transmission complete interrupt
Enables transmission complete interrupt
bit 6
TIE6
0
1
Transmission interrupt enable bit 6
(message buffer 6)
Disables transmission complete interrupt
Enables transmission complete interrupt
bit 7
TIE7
R/W : Read/Write
: Reset value
458
0
1
Transmission interrupt enable bit 7
(message buffer 7)
Disables transmission complete interrupt
Enables transmission complete interrupt
CHAPTER 15 CAN CONTROLLER
Table 15.3-15 Functions of Transmission Complete Interrupt Enable Register (TIER)
Bit Name
bit 7 to bit 0
TIE7 to TIE0:
Transmission complete
interrupt enable bits 7 to 0
Function
These bits enable or disable a transmission complete interrupt for the
message buffer (x).
When set to "0": Disables transmit complete interrupt for message buffer
(x)
When set to "1": Enables transmit complete interrupt for message buffer
(x)
459
CHAPTER 15 CAN CONTROLLER
15.3.14
Reception Complete Register (RCR)
The reception complete register (RCR) indicates whether the reception a data to the
message buffer (x) completes receiving. When an interrupt is enabled at completion of
receiving, an interrupt request is generated.
■ Reception Complete Register (RCR)
Figure 15.3-22 Reception Complete Register (RCR)
Address:
000088H
7
6
5
4
3
2
1
0
Reset value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
RC0
0
1
Reception is not completed/no reception
Reception is completed
bit 1
RC1
0
1
Reception is not completed/no reception
Reception is completed
bit 2
RC2
0
1
Reception is not completed/no reception
Reception is completed
bit 3
RC3
0
1
Reception is not completed/no reception
Reception is completed
bit 4
RC4
0
1
R/W : Read/Write
: Reset value
460
Reception complete bit 0 (message buffer 0)
Reception complete bit 1 (message buffer 1)
Reception complete bit 2 (message buffer 2)
Reception complete bit 3 (message buffer 3)
Reception complete bit 4 (message buffer 4)
Reception is not completed/no reception
Reception is completed
bit 5
RC5
0
1
Reception is not completed/no reception
Reception is completed
bit 6
RC6
0
1
Reception is not completed/no reception
Reception is completed
bit 7
RC7
0
1
Reception is not completed/no reception
Reception is completed
Reception complete bit 5 (message buffer 5)
Reception complete bit 6 (message buffer 6)
Reception complete bit 7 (message buffer 7)
CHAPTER 15 CAN CONTROLLER
Table 15.3-16 Functions of Reception Complete Register (RCR)
Bit Name
bit 7 to bit 0
RC7 to RC0:
Reception complete bits
7 to 0
Function
These bits indicate whether the message buffer (x) completes message
receiving.
When message receiving completed:
"1" is set to the RCx bit corresponding to the message buffer (x) that
completes receiving.
When set to "0": Clears bits when receiving is already completed.
When set to "1": No effect
Read by read modify write (RMW) instruction: "1" is always read.
Setting the RCx bit when receiving is completed (RCx = 1) overrides clearing
of the RCx bit when"0" is written (RCx = 0) if both occur at the same time.
[Generation of reception complete interrupt]
If the reception complete enable register is set (RIER: RIEx = 1), a reception
complete interrupt is generated when receiving is completed.
Note: To clear the reception complete register (RCR), read the received
message after the completion of receiving and write 0.
461
CHAPTER 15 CAN CONTROLLER
15.3.15
Reception RTR Register (RRTRR)
The reception RTR register (RRTRR) indicates that the remote frame is stored in the
message buffer.
■ Reception RTR Register (RRTRR)
Figure 15.3-23 Reception RTR Register (RRTRR)
Address:
00008AH
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
RRTR0
0
1
Remote frame receive bit 0
(message buffer 0)
Remote frame is not received
Remote frame is received
bit 1
RRTR1
0
1
Remote frame receive bit 1
(message buffer 1)
Remote frame is not received
Remote frame is received
bit 2
RRTR2
0
1
Remote frame receive bit 2
(message buffer 2)
Remote frame is not received
Remote frame is received
bit 3
RRTR3
0
1
Remote frame receive bit 3
(message buffer 3)
Remote frame is not received
Remote frame is received
bit 4
RRTR4
0
1
Remote frame receive bit 4
(message buffer 4)
Remote frame is not received
Remote frame is received
bit 5
RRTR5
0
1
Remote frame receive bit 5
(message buffer 5)
Remote frame is not received
Remote frame is received
bit 6
RRTR6
0
1
Remote frame receive bit 6
(message buffer 6)
Remote frame is not received
Remote frame is received
bit 7
RRTR7
R/W : Read/Write
: Reset value
462
0
1
Remote frame receive bit 7
(message buffer 7)
Remote frame is not received
Remote frame is received
CHAPTER 15 CAN CONTROLLER
Table 15.3-17 Functions of Reception RTR Register (RRTRR)
Bit Name
bit 7 to bit 0
RRTR7 to RRTR0:
Remote frame receive
bits 7 to 0
Function
These bits indicate that the message buffer (x) receives a remote frame.
When remote frame is received:
"1" is set to the RRTRx bit corresponding to the message buffer (x) that
receives a remote frame.
When set to "0": Cleared when receiving is completed.
When set to "1": No effect
• Setting the RRTRx bit when a remote frame is received (RRTRx = 1)
overrides clearing of the RRTRx bit when "0" is written (RRTRx = 0) if
both occur at the same time.
• The RRTRx bit corresponding to the message buffer (x) that receives a
data frame is cleared (RRTRx = 0).
• If message transmitting is completed (TCR: TCx = 1), the RRTRx bit
corresponding to the message buffer (x) that transmits the message is
cleared (RRTRx = 0).
Read by read modify write (RMW) instruction: "1" is always read.
463
CHAPTER 15 CAN CONTROLLER
15.3.16
Reception Overrun Register (ROVRR)
The reception overrun register (ROVRR) indicates that an overrun occurs (the
corresponding message buffer is in the receive complete state.) at storing the received
message in the message buffer.
■ Reception Overrun Register (ROVRR)
Figure 15.3-24 Reception Overrun Register (ROVRR)
Address:
00008CH
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
ROVR0
0
1
bit 1
ROVR1
0
1
bit 2
ROVR2
0
1
bit 3
ROVR3
0
1
bit 4
ROVR4
0
1
bit 5
ROVR5
0
1
bit 6
ROVR6
0
1
bit 7
ROVR7
R/W : Read/Write
: Reset value
464
0
1
Reception overrun bit 0 (message buffer 0)
Overrun is not occurred
Overrun is occurred
Reception overrun bit 1 (message buffer 1)
Overrun is not occurred
Overrun is occurred
Reception overrun bit 2 (message buffer 2)
Overrun is not occurred
Overrun is occurred
Reception overrun bit 3 (message buffer 3)
Overrun is not occurred
Overrun is occurred
Reception overrun bit 4 (message buffer 4)
Overrun is not occurred
Overrun is occurred
Reception overrun bit 5 (message buffer 5)
Overrun is not occurred
Overrun is occurred
Reception overrun bit 6 (message buffer 6)
Overrun is not occurred
Overrun is occurred
Reception overrun bit 7 (message buffer 7)
Overrun is not occurred
Overrun is occurred
CHAPTER 15 CAN CONTROLLER
Table 15.3-18 Functions of Reception Overrun Register (ROVRR)
Bit Name
bit 7 to bit 0
ROVR7 to ROVR0:
Reception overrun bits 7
to 0
Function
These bits indicate that an overrun occurs at storing the received message in
the message buffer that had completed receiving.
At overrun: "1" is set to the ROVRx bit corresponding to the message buffer
(x) where an overrun occurs.
When set to "0": Cleared when "0" is set to after reception overrun occurred
When set to "1": No effect
Read by read modify write (RMW) instruction: "1" is always read.
Setting the ROVRx bit when an overrun occurs (ROVRx = 1) overrides
clearing of the ROVRx bit when "0" is written (ROVRx = 0) if both occur at
the same time.
465
CHAPTER 15 CAN CONTROLLER
15.3.17
Reception Complete Interrupt Enable Register (RIER)
The reception complete interrupt enable register (RIER) enables or disables a reception
complete interrupt for each message buffer.
■ Reception Complete Interrupt Enable Register (RIER)
Figure 15.3-25 Reception Complete Interrupt Enable Register (RIER)
Address:
00008EH
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
RIE0
0
1
bit 1
RIE1
0
1
bit 2
RIE2
0
1
bit 3
RIE3
0
1
bit 4
RIE4
0
1
bit 5
RIE5
0
1
bit 6
RIE6
0
1
bit 7
RIE7
R/W
466
: Read/Write
: Reset value
0
1
Reception complete interrupt enable bit 0 (message buffer 0)
Disables reception complete interrupt
Enables reception complete interrupt
Reception complete interrupt enable bit 1 (message buffer 1)
Disables reception complete interrupt
Enables reception complete interrupt
Reception complete interrupt enable bit 2 (message buffer 2)
Disables reception complete interrupt
Enables reception complete interrupt
Reception complete interrupt enable bit 3 (message buffer 3)
Disables reception complete interrupt
Enables reception complete interrupt
Reception complete interrupt enable bit 4 (message buffer 4)
Disables reception complete interrupt
Enables reception complete interrupt
Reception complete interrupt enable bit 5 (message buffer 5)
Disables reception complete interrupt
Enables reception complete interrupt
Reception complete interrupt enable bit 6 (message buffer 6)
Disables reception complete interrupt
Enables reception complete interrupt
Reception complete interrupt enable bit 7 (message buffer 7)
Disables reception complete interrupt
Enables reception complete interrupt
CHAPTER 15 CAN CONTROLLER
Table 15.3-19 Functions of Reception Complete Interrupt Enable Register (RIER)
Bit Name
bit 7 to bit 0
RIE7 to RIE0:
Reception complete
interrupt enable bits 7 to 0
Function
These bits enable or disable a reception complete interrupt for the message
buffer (x).
When set to "0": Disables reception complete interrupt for message buffer
(x)
When set to "1": Enables reception complete interrupt for message buffer
(x)
467
CHAPTER 15 CAN CONTROLLER
15.3.18
Acceptance Mask Select Register (AMSR)
The acceptance mask select register (AMSR) selects the mask (acceptance mask)
format for comparison between the identifier (ID) of the received message and the
message buffer.
■ Acceptance Mask Select Register (AMSR)
Figure 15.3-26 Acceptance Mask Select Register (AMSR)
Address:
003D11H
Address:
003D10H
bit 15
14
13
12
11
10
9
8
AMS7.1
AMS7.0
AMS6.1
AMS6.0
AMS5.1
AMS5.0
AMS4.1
AMS4.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
AMS3.1
AMS3.0
AMS2.1
AMS2.0
AMS1.1
AMS1.0
AMS0.1
AMS0.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AMS7.1 to AMS0.1 AMS7.0 to AMS0.0
0
0
0
1
1
0
1
1
x (7 to 0) is message buffer's number (x).
X
: Undefined
R/W : Read/Write
468
Reset value
XXXXXXXXB
Reset value
XXXXXXXXB
Acceptance mask select bit
Full-bit comparison
Full-bit mask
Uses acceptance mask register 0 (AMR0)
Uses acceptance mask register 1 (AMR1)
CHAPTER 15 CAN CONTROLLER
Table 15.3-20 Functions of Acceptance Mask Select Register (AMSR)
Bit Name
bit 15 to bit 0
AMS7.0 to AMS0.0,
AMS7.1 to AMS0.1:
Acceptance mask select
bits 7.0 to 0.0, 7.1 to 0.1
Function
These bits select the mask (acceptance mask) format for comparison between
the received message ID and message buffer ID (IDR) for the message buffer
(x).
No comparison with masked bits is made.
Full-bit comparison: All bits are compared in collating the setting values of
the ID register (IDR) with the received message ID.
Full-bit masking:
All bits for the setting values of the ID register (IDR)
and the received message ID are masked.
Using acceptance mask register 0 (or 1):
The acceptance mask register 0 or 1 (AMR0 or AMR1) is used as an
acceptance mask filter. At collating the setting values of the ID register
(IDR) with the received message ID, only the bits set to "0" and
corresponding to the AMx bit in the acceptance mask register are
compared and the bits set to "1" and corresponding to the AMx bit are
masked.
If the AMSx.1 and AMSx.0 bits are set to "10B" or "11B", always set the
acceptance mask register (AMR0 or AMR1) to be used, too.
Note: The acceptance mask select register (AMSR) should be set after
disabling the message buffer (x) to be set (BVALR: BVALx = 0).
Setting the acceptance mask select register (AMSR) with the message
buffer (x) enabled may store a message unnecessary received.
Note:
To invalidate the message buffer (by setting the BVALR: BVALx bit to "0") while CAN Controller is
participating in CAN communication (the read value of the CSR: HALT bit is "0" and CAN Controller
is ready to receive or transmit messages), follow the cautions in Section "15.6 Precautions when
Using CAN Controller".
469
CHAPTER 15 CAN CONTROLLER
15.3.19
Acceptance Mask Register (AMR)
The CAN controller has two acceptance mask registers (AMR0 and AMR1). Both of them
can be used in the standard frame format (ID11 bits, AM28 to AM18) and the extended
frame format (ID29 bits, AM28 to AM0).
■ Acceptance Mask Register (AMR)
Figure 15.3-27 Acceptance Mask Register (AMR)
Addresses:
ch.0 003D14H
to
003D17H
bit 7
BYTE0
ch.1 003D18H
to
003D1BH
BYTE3
R/W:
X :
- :
:
470
4
3
2
1
0
14
13
12
11
10
9
8
AM20 AM19 AM18 AM17 AM16 AM15 AM14 AM13
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
BYTE2
5
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
BYTE1
6
6
5
AM12 AM11 AM10
R/W
R/W
R/W
4
3
2
1
0
AM9
R/W
AM8
R/W
AM7
R/W
AM6
R/W
AM5
R/W
15
14
13
12
11
10
9
8
AM4
R/W
AM3
R/W
AM2
R/W
AM1
R/W
AM0
R/W
−
−
−
Read/Write
Undefined
Unused
Used bits in the standard frame format
Reset value
XXXXXXXXB
Reset value
XXXXXXXXB
Reset value
XXXXXXXXB
Reset value
XXXXXXXXB
CHAPTER 15 CAN CONTROLLER
Table 15.3-21 Functions of Acceptance Mask Register (AMSR)
Bit Name
bit 15 to bit 11
AM4 to AM0:
Acceptance mask bits 4
to 0 (BYTE3)
bit 7 to bit 0
AM12 to AM5:
Acceptance mask bits 12
to 5 (BYTE2)
bit 15 to bit 8
AM20 to AM13:
Acceptance mask bits 20
to 13 (BYTE1)
bit 7 to bit 0
AM28 to AM21:
Acceptance mask bits 28
to 21 (BYTE0)
Function
These bits set whether to compare or mask each bit at collating the
acceptance code set in the ID register (IDR: IDx) with the received message
ID.
If the AMSx.1 or AMSx.0 bits of acceptance mask select registers are set
to "10B" or "11 B", always set the acceptance mask register (AMR0 or
AMR1) to be used, too.
Standard frame format (IDER: IDEx = 0):11 bits from AM28 to AM18
are used.
Extended frame format (IDER: IDEx = 1):29 bits from AM28 to AM0 are
used.
When AMx bit is set to "0" (compare):
The bits corresponding to the AMx bit set to "0" are compared at collating
the acceptance code set in the ID register (IDR: IDx) with the received
message ID.
When AMx bit set to "1" (mask):
The bits corresponding to the AMx bit set to "1" are masked and not
compared, at collating the acceptance code set in the ID register (IDR:
IDx) with the received message ID.
Note: The acceptance mask register (AMR0, AMR1) should be set after
disabling the message buffer (x) to be set (BVALR: BVALx = 0).
Setting the acceptance mask select register (AMR) with the message
buffer (x) enabled may store a message unnecessary received.
Note:
To invalidate the message buffer (by setting the BVALR: BVALx bit to "0") while CAN Controller is
participating in CAN communication (the read value of the CSR: HALT bit is "0" and CAN Controller
is ready to receive or transmit messages), follow the cautions in Section "15.6 Precautions when
Using CAN Controller".
471
CHAPTER 15 CAN CONTROLLER
15.3.20
Message Buffers
The message buffers consist of ID register, DLC register, and data register are used for
transmission/reception of the message.
■ Message Buffers
• There are 8 message buffers.
• One message buffer (x) (x = 0 to 7) consists of an ID register (IDRx), DLC register (DLCRx), and data
register (DTRx).
• The message buffer (x) is used to transmit and receive messages.
• Higher priority is given to smaller number message buffer.
- At transmitting, if a transmit request is generated to more than one message buffer, transmitting is
started from the message buffer with the smallest number.
- At receiving, if the received message ID passes the acceptance filter (which compares received
message ID with message buffer ID after acceptance masking) set in more than one message buffer, a
received message is stored in the message buffer with the smallest number.
• If the same acceptance filter is set in more than one message buffer, it can be used as multiple message
buffers. This provides sufficient time to perform receiving.
Notes:
• Write by words to the message buffer area and general-purpose RAM area. At writing by bytes,
undefined data is written to the upper bytes and writing to the upper bytes is ignored when writing
to the lower bytes is performed.
• The message buffer (x) area disabled by the message buffer enable register (BVALR: BVALx = 0)
can be used as a general-purpose RAM area. However, during transmitting or receiving, it may
take up to 64 machine cycles to access the message buffer area and general-purpose RAM area.
References:
• See "15.5.1 Transmission" for details of transmission.
• See "15.5.2 Reception" for details of reception.
• See "15.5.4 Setting Multiple Message Receiving" for details of the configuration of the multiple
message buffer.
472
CHAPTER 15 CAN CONTROLLER
15.3.21
ID Register (IDR7 to IDR0)
The ID register (IDR) sets the ID of the message buffer used for transmitting and
receiving. In the standard frame format, 11 bits from ID28 to ID18 are used, and in the
extended frame format, 29 bits from ID28 to ID0 are used.
■ ID Register (IDR)
Figure 15.3-28 ID Register (IDR)
Addresses
bit 7
ch.0 003C10H to 003C13H BYTE0 ID28
ch.1 003C14H to 003C17H
R/W
ch.2 003C18H to 003C1BH
ch.3 003C1CH to 003C1FH
6
5
4
ID27
R/W
ID26
R/W
ID25
R/W
14
13
12
ID19
R/W
ID18
R/W
ID17
R/W
6
5
4
3
2
1
0
ID11
R/W
ID10
R/W
ID9
R/W
ID8
R/W
ID7
R/W
ID6
R/W
ID5
R/W
XXXXXXXXB
bit 15
14
13
12
11
10
9
8
ID4
R/W
ID3
R/W
ID2
R/W
ID1
R/W
ID0
R/W
Reset value
XXXXXXXXB
−
−
−
bit 15
ch.4 003C20H to 003C23H BYTE1 ID20
ch.5 003C24H to 003C27H
R/W
ch.6 003C28H to 003C2BH
ch.7 003C2CH to 003C2FH
bit 7
BYTE2 ID12
R/W
BYTE3
R/W:
X :
- :
:
3
2
1
ID24 ID23 ID22
R/W R/W R/W
11
10
9
ID16 ID15 ID14
R/W R/W R/W
0
ID21
R/W
8
ID13
R/W
Reset value
XXXXXXXXB
Reset value
XXXXXXXXB
Reset value
Read/Write
Undefined
Unused
Used bits in the standard frame format
473
CHAPTER 15 CAN CONTROLLER
Table 15.3-22 Functions of ID Register (IDR)
Bit Name
bit 15 to bit 11
ID4 to ID 0:
ID bits 4 to 0
(BYTE3)
bit 7 to bit 0
ID12 to ID5:
ID bits 12 to 5
(BYTE2)
bit 15 to bit 8
ID20 to ID13:
ID bits 20 to 13
(BYTE1)
bit 7 to bit 0
ID28 to ID21:
ID bits 28 to 21
(BYTE0)
474
Function
These bits set the acceptance code or transmit message ID to be collated with the
received message ID.
Standard frame format (IDER: IDEx = 0): 11 bits from ID28 to ID18 are used.
• The old messages left in the receive shift register are stored in ID17 to ID0. This
will not affect the operation.
• All received message IDs are stored even if specific bits are masked.
Extended frame format (IDER: IDEx = 1): 29 bits from ID28 to ID0 are used.
Notes: • When using the standard frame format (IDER: IDEx = 0), the bits from
ID28 to ID22 cannot be all set to "1".
• When setting the ID register (IDR), perform writing by words. Writing by
bytes is disabled.
• The ID register (IDR) should be set after disabling the message buffer (x)
to be set (BVALR: BVALx = 0). Setting the ID register (IDR) with the
message buffer (x) enabled may store a message unnecessary received.
CHAPTER 15 CAN CONTROLLER
● Setting example of ID register (IDR)
Table 15.3-23 gives a setting example of the ID register (IDR) in the standard and extended frame formats.
Table 15.3-23 Example of ID Setting in Standard and Extended Frame Formats
Standard Frame Format
ID (Dec)
ID (Hex) BYTE0
1
1
00H
2
2
00H
3
3
00H
4
4
00H
5
5
00H
6
6
00H
7
7
00H
8
8
01H
9
9
01H
A
10
01H
BYTE1
20H
40H
60H
80H
A0H
C0H
E0H
00H
20H
40H
ID (Dec)
1
2
3
4
5
6
7
8
9
10
Extended Frame Format
ID (Hex) BYTE0 BYTE1
1
00H
00H
2
00H
00H
3
00H
00H
4
00H
00H
5
00H
00H
6
00H
00H
7
00H
00H
8
00H
00H
9
00H
00H
A
00H
00H
BYTE2
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
BYTE3
08H
10H
18H
20H
28H
30H
38H
40H
48H
50H
30
31
32
1E
1F
20
03H
03H
04H
C0H
E0H
00H
30
31
32
1E
1F
20
00H
00H
00H
00H
00H
00H
00H
00H
01H
F0H
F8H
00H
100
101
64
65
0CH
0CH
80H
A0H
100
101
64
65
00H
00H
00H
00H
03H
03H
20H
28H
200
C8
19H
00H
200
C8
00H
00H
06H
40H
2043
2044
2045
2046
2047
7FB
7FC
7FD
7FE
7FF
FFH
FFH
FFH
FFH
FFH
60H
80H
A0H
C0H
E0H
2043
2044
2045
2046
2047
7FB
7FC
7FD
7FE
7FF
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
3FH
3FH
3FH
3FH
3FH
D8H
E0H
E8H
F0H
F8H
8190
8191
8192
1FFE
1FFF
2000
00H
00H
00H
00H
00H
01H
FFH
FFH
00H
F0H
F8H
00H
536870905
536870906
536870907
536870908
536870909
536870910
536870911
1FFFFFF9
1FFFFFFA
1FFFFFFB
1FFFFFFC
1FFFFFFD
1FFFFFFE
1FFFFFFF
FFH
FFH
FFH
FF
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FCH
FDH
FDH
FEH
FEH
FFH
FFH
80H
00H
80H
00H
80H
00H
80H
475
CHAPTER 15 CAN CONTROLLER
15.3.22
DLC Register (DLCR)
The DLC register (DLCR) sets the data length of the message to be transmitted or
received.
■ DLC Register (DLCR)
Figure 15.3-29 DLC Register (DLCR)
Addresses
ch.0 003C30H, 003C31H
ch.1 003C32H, 003C33H
ch.2 003C34H, 003C35H
ch.3 003C36H, 003C37H
ch.4 003C38H, 003C39H
ch.5 003C3AH, 003C3BH
ch.6 003C3CH, 003C3DH
ch.7 003C3EH, 003C3FH
bit 7
bit 6
bit 5
bit 4
-
-
-
-
bit 3
bit 2
bit 1
bit 0
DLC3 DLC2 DLC1 DLC0
R/W R/W R/W R/W
Reset value
XXXXXXXXB
R/W: Read/Write
X : Undefined
- : Unused
Table 15.3-24 Functions of DLC Register (DLCR)
Bit Name
bit 3 to bit 0
476
DLC3 to DLC0:
Data length setting bits
Function
These bits set the data length (byte count) of the message to be transmitted or
received.
When data frame transmitted: The data length (byte count) of the
transmit message is set.
When remote frame transmitted: The data length (byte count) of the
request message is set.
When data frame received:
The data length (byte count) of the
received message is stored.
When remote frame received:
The data length (byte count) of the
request message is stored.
Notes: • The data length should be set within the range of 0 to 8 bytes.
• When setting the DLC register (DLCR), write by words. Writing by
bytes is disabled.
CHAPTER 15 CAN CONTROLLER
15.3.23
Data Register (DTR)
The data register (DTR) sets the messages at transmitting or receiving a data frame.
The data length can be set from 0 to 8 bytes.
■ Data Register (DTR)
Figure 15.3-30 Data Register (DTR)
Addresses
ch.0 003C40H to 003C47H BYTE0
ch.1 003C48H to 003C4FH
ch.2 003C50H to 003C57H
to
bit 7
6
5
4
3
2
1
0
D7
R/W
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
ch.3 003C58H to 003C5FH
bit 15
14
13
12
11
10
9
8
ch.4
ch.5
ch.6
ch.7
D7
R/W
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
003C60H to 003C67H BYTE7
003C68H to 003C6FH
003C70H to 003C77H
003C78H to 003C7FH
Reset value
XXXXXXXXB
Reset value
XXXXXXXXB
R/W: Read/Write
X : Undefined
Table 15.3-25 Functions of Data Register (DTR)
Bit Name
bit 15 to bit 0
D7 to D0 (BYTE7 to
BYTE0):
Data bits 7 to 0
Function
• The data register (DTRx) is used only for transmitting or receiving a data
frame, and is not used for a remote frame.
• The transmit message is set up to 8 bytes. The message is transmitted on
an MSB-first basis starting with the small message buffer number
(BYTE0 to BYTE7).
• The received message is stored on an MSB-first basis starting with the
small message buffer number (BYTE0 to BYTE7).
• If the received message is less than 8 bytes, undefined data is stored in the
rest of the bytes of the data register (DTRx). However this does not affect
the operation.
Note: When setting the data register (DTR), write by words. Writing by bytes
is disabled.
477
CHAPTER 15 CAN CONTROLLER
15.4
Interrupts of CAN Controller
The CAN controller has a transmit complete interrupt, receive complete interrupt and
node status transition interrupt, and can generate interrupts when;
• Transmission complete bit (TCR: TCx) is set.
• Reception complete bit (RCR: RCx) is set.
• Node status transition flag (CSR: NT) is set.
■ Interrupts of CAN Controller
Table 15.4-1 shows the interrupt control bits and interrupt factors of the CAN controller.
Table 15.4-1 Interrupt Control Bits and Interrupt Factors of CAN Controller
Transmit/
Receive
Interrupt Flag Bit
Interrupt Factor
Interrupt Enable Bit
Clearing of Interrupt Request
Flag
Transmit
Transmission
complete bit
TCR: TCx=1
Message transmitting
complete
Transmission
complete interrupt
enable bit
TIER: TIEx = 1
Setting transmission request bit
(TREQR: TREQx = 1)
Writing 0 to transmission
complete bit (TCR: TCx)
Receive
Reception complete
bit
RCR: RCx=1
Message receiving
complete
Reception complete
interrupt enable bit
RIER: RIEx=1
Writing 0 to reception complete
bit (RCR: RCx)
Transmit
Node status transition
flag
CSR: NT=1
Node status transition
Node status transition
interrupt enable bit
CSR: NIE=1
Writing 0 to node status transition
flag (CSR: NT)
● Transmission complete interrupt
When message transmitting is completed, "1" is set to the TCx bit in the transmission complete register
(TCR). When a transmission complete interrupt is enabled (TIER: TIEx = 1) and when TCx = 1, a
transmission complete interrupt is generated. When a transmission request to the message buffer is set
(TREQR: TREQx = 1), the TCx bit in the transmission complete register (TCR) is automatically cleared to
"0". When "0" is written to the TCx bit in the transmission complete register (TCR) after the completion of
message transmitting (TCR: TCx = 1), the TCx bit is cleared.
● Reception complete interrupt
When message receiving is completed, "1" is set to the RCx bit in the receive complete register (RCR).
When a reception complete interrupt is enabled (RIER: RIEx = 1) and when RCx = 1, a reception complete
interrupt is generated. When "0" is written to the RCx bit in the reception complete register (RCR) after the
completion of message receiving (RCR: RCx = 1), the RCx bit is cleared.
478
CHAPTER 15 CAN CONTROLLER
● Node status transition interrupt
When the node status of the CAN controller changes, "1" is set to the NT bit in the control status register
(CSR). If a node status transition interrupt is enabled (CSR: NIE = 1) when NT = 1, a node status transition
interrupt is generated. When "0" is written to the NT bit in the control status register, the NT bit is cleared.
■ Registers and Vector Tables Related to Interrupt of CAN Controller
See "3.5 Interrupt" for details of the interrupts.
479
CHAPTER 15 CAN CONTROLLER
15.5
Explanation of Operation of CAN Controller
This section explains the procedures for transmitting and receiving messages and the
setting of bit timing, frame format, ID and acceptance filter.
■ Explanation of Operation of CAN Controller
The following sections provide more details of the operation of CAN controller.
• Transmission of message (See Section "15.5.1 Transmission")
• Reception of message (See Section "15.5.2 Reception")
• Procedures for transmission/reception of message (See Section "15.5.3 Procedures for Transmitting and
Receiving")
• Reception of multiple message (See Section "15.5.4 Setting Multiple Message Receiving")
480
CHAPTER 15 CAN CONTROLLER
15.5.1
Transmission
Figure 15.5-1 shows a transmission flowchart.
■ Transmission
Figure 15.5-1 Transmission Flowchart
Set transmission request register
(TREQR : TREQx = 1)
Transmission complete register is cleared
(TCR : TCx = 0)
NO : 0
Transmission request set?
(TREQR : TREQx)
YES : 1
NO : 0
Remote frame receiving wait?
(RFWTR : RFWTx)
YES : 1
Remote frame received?
(RRTRR : RRTRx)
NO : 0
YES : 1
If there remains message buffer meeting
transmission conditions, the lowestnumbered message buffer is selected.
NO
Is bus idle state?
YES
TRTRx = 0
How is frame setting?
(TRTRR : TRTRx)
A data frame is transmitted
TRTRx = 1
A remote frame is transmitted
Is transmission successful?
NO
YES
Transmission request register is cleared (TREQR : TREQx = 0)
Reception RTR register is cleared (RRTRR : RRTRx = 0)
Transmission complete register is set (TCR : TCx = 1)
Transmission cancelled?
(TCANR : TCANx)
NO: 0
YES: 1
Transmission register is cleared
(TREQR : TREQx = 0)
Transmission
complete interrupt enabled?
(TIER : TIEx = 1)
NO : 0
YES : 1
Transmission complete interrupt
request is output
Transmission is completed
481
CHAPTER 15 CAN CONTROLLER
● Starting transmitting
Setting of transmission request
To start transmitting, set the TREQx bit in the transmission request register to "1" which is corresponding
to the message buffer (x) that transmits the message. When the TREQx bit is set, the transmission
complete register is cleared (TCR: TCx = 0).
Presence or absence of remote frame receive wait
If the RFWTx bit in the remote frame receive wait register is set, transmitting is started after a remote
frame is received (RRTRR: RRTRx = 1).
If the remote frame receive wait register does not wait for receiving of a remote frame (RFWTR:
RFWTx = 0), transmitting is started immediately after the transmission request bit is set (TREQR:
TREQx = 1).
● Performing transmitting
Transmission request set in more than one message buffer
When a transmission request is set in more than one message buffer (TREQR: TREQx = 1),
transmitting is performed starting with the small-numbered message buffer (x = 7 to 0).
Transmitting to CAN bus
Transmitting message to the CAN bus from the transmit output pin (TX) is started when the CAN bus is
idle.
Arbitration
Arbitration is performed when a message buffer conflicts with transmitting from other CAN controllers
on the CAN bus. If arbitration fails or an error occurs during transmitting, retransmitting is performed
automatically until it succeeds after waiting until the bus goes idle again.
Selection of frame format
When "0" is set to the TRTRx bit in the transmit RTR register, a data frame is transmitted. When "1" is
set to the bit, a remote frame is transmitted.
● Canceling transmit request
Cancellation by transmission cancel register (TCANR)
During transmitting message, the transmission request set in the message buffer that is not transmitted
(held) can be canceled by setting 1 in the transmission cancel register (TCANR).
When the transmission request is completely canceled (TCANR: TCANx = 1), the transmission request
register is cleared (TREQx = 1).
Cancellation by receiving message
The message buffer can receive the message even during requesting a transmitting. However, the
transmission request is canceled under the following conditions:
Request to transmit data frame:
When a data frame is received, the transmission request is canceled. When a remote frame is received,
the transmission request is not canceled.
Request to transmit remote frame:
The transmission request is canceled even if either a data frame or remote frame is received.
482
CHAPTER 15 CAN CONTROLLER
● Completing transmitting
Success of transmitting
When transmitting is terminated normally, the TCx bit in the transmission complete register is set. The
transmission request register and receive RTR register (TREQR: TREQx = 0, RRTRR: RRTRx = 0) are
cleared.
Generation of transmission interrupt
When the TIEx bit in the transmission complete interrupt enable register is set, an interrupt request is
generated when transmitting is completed (TCR: TCx = 1).
483
CHAPTER 15 CAN CONTROLLER
15.5.2
Reception
Figure 15.5-2 shows a reception flowchart.
■ Reception
Figure 15.5-2 Reception Flowchart
Start-of-frame (SOF) of data frame or
remote frame is detected
Is any message buffer (x)
passing through the acceptance
filter found?
NO
YES
NO
Is reception successful?
YES
Determine message buffer (x) where
receive messages to be stored.
Received message is stored
in the message buffer (x).
Reception complete
register set? (RCR : RCx)
Reception overrun generation
(ROVRR : ROVRx = 1)
NO : 0
Data frame
YES : 1
Receiving message?
Remote frame
Set reception RTR register
(RRTRR : RRTRx = 1)
Clear reception RTR register
(RRTRR : RRTRx = 0)
TRTRx = 1
Transmission request
of remote frame?
(TRTRR : TRTRx)
Transmission request register is cleared
(TREQR : TREQx = 0)
TRTRx = 0
Setting of reception complete register
(RCR : RCx = 1)
Reception
complete interrupt enabled?
(RIER : RIEx = 1)
YES : 1
Reception complete interrupt request is output
NO : 0
Transmission is completed
484
CHAPTER 15 CAN CONTROLLER
● Starting receiving
Receiving is started when the start-of-frame (SOF) of a data frame or remote frame is detected on the CAN
bus.
● Acceptance filter
The received message in the standard frame format is compared with the message buffer (x) set in the
standard frame format (IDER: IDEx = 0). The received message in the extended frame format is compared
with the message buffer (x) set in the extended frame format (IDER: IDEx = 1).
Passing through acceptance filter
If all bits set to "compare" in the acceptance mask are matched after comparison between the received
message ID and acceptance code (IDR: IDx), the received message passes the acceptance filter in the
message buffer (x).
● Storing received message
If receiving message is successful, the received message is stored in the message buffer (x) that has the ID
that had passed the acceptance filter.
Data frame received
The received message is stored in the ID register (IDR) and DLC register (DLCR), data register (DTR).
If the received message is less than 8 bytes, undefined data is stored in the rest of the bytes in the data
register (DTR).
Remote frame received
The received message is stored in the ID register (IDR) and DLC register (DLCR). The data register
(DTR) remains unchanged.
More than one message buffer
If there is more than one message buffer with the ID that had passed the acceptance filter, the message
buffer (x) where the received message is stored is determined under the following conditions:
• Higher priority is given to the message buffer with a smaller number (x = 0 to 7). The priority of
message buffer "0" is the highest and "7" is the lowest.
• The received message is stored in preference to the message buffer that has not been completed
receiving (RCR: RCx = 0).
• If the bit in the acceptance mask select register is set to "full-bit comparison" (AMSx.1 = 0, 0 = 00B),
the received message is stored in the corresponding message buffer (x), regardless of the setting value of
the reception complete register (RCR: RCx).
• If there is more than one message buffer that has not been completed receiving, or if there is more than
one message buffer with the AMSx.1 and AMSx.0 bits in the acceptance mask select register set to
"00B" (full-bit comparison), the received message is stored in the message buffer with the smallest
number (x).
• If there is no message buffer that satisfies the above conditions, the received message is stored in the
message buffer with the lowest number (x).
• The message buffers should be arranged in order of ascending number (x) as follows;
- Smallest number (x): Acceptance mask set to "full-bit comparison"
- Middle number (x): Acceptance mask registers 0 and 1 used
485
CHAPTER 15 CAN CONTROLLER
- Largest number (x): Acceptance mask set to "full-bit masking"
● Setting of acceptance mask select register
Table 15.5-1 Setting of Acceptance Mask Select Register
AMSx. 1
AMSx. 0
Acceptance Mask (x = 7 to 0)
0
0
Full-bit comparison is performed.
0
1
Full-bit masking is performed.
1
0
Acceptance mask register 0 (AMR0) is used.
1
1
Acceptance mask register 1 (AMR1) is used.
Figure 15.5-3 Flowchart of Determining Message Buffer that Stores Received Message
Start
Message is not received (RCR : RCx = 0),
or any message buffer set to "full-bit comparison"
(AMSR : AMSx.1 = 0, AMSx.0 = 0)?
NO
YES
Select the smallest-numbered message
buffer (x) from message buffers
corresponding to the above.
End
486
Select the smallest-numbered
message buffer (x).
CHAPTER 15 CAN CONTROLLER
● Receive overrun
When another received message is stored in the message buffer that has completed receiving (RCR: RCx =
1), a receive overrun occurs. When a receive overrun occurs, "1" is set to the ROVRx bit in the receive
overrun register corresponding to the number of the message buffer (x) where the receive overrun occurs.
● Processing for reception of data frame and remote frame
Processing for reception of data frame
• The reception RTR register is cleared (RRTRR: RRTRx = 0).
• The transmission request register is cleared (TREQR: TREQx = 0) immediately before the received
message is stored. A transmission request to the message buffer (x) that does not perform transmitting is
canceled.
Note:
Either the request to transmit a data frame or a remote frame is canceled.
Processing for reception of remote frame
• The reception RTR register is set (RRTRR: RRTRx = 1).
• If the transmission RTR register is set (TRTRR: TRTRx = 1), the transmission request register is cleared
(TREQx = 0). The request to transmit a remote frame to the message buffer (x) that does not perform
transmitting is canceled.
Note:
The request to transmit a data frame is not canceled.
For details about how to cancel a transmit request, see "Canceling transmit request" in Section
"15.5.1 Transmission".
● Completing receiving
When the received message is stored, the reception complete register is set (RCR: RCx = 1). If the
reception complete interrupt enable register is set (RIER: RIEx = 1), an interrupt is generated when
receiving is completed (RCR: RCx = 1).
Note:
The CAN controller cannot receive any message transmitted by itself.
487
CHAPTER 15 CAN CONTROLLER
15.5.3
Procedures for Transmitting and Receiving
The section explains the procedure for transmission/reception of message.
■ Presetting
● Setting of bit timing
Set the bit timing register (BTR) after halting the bus operation (CSR: HALT = 1).
● Setting of frame format
Set the frame format used in the message buffer (x). When using the standard frame format, set the IDEx
bit in the IDE register (IDER) to "0". When using the extended frame format, set the IDEx bit to "1".
● Setting of ID
• Set the ID of the message buffer (x) to the ID28 to ID0 bits in the ID register (IDR). In the standard
frame format, it does not have to set the ID17 to ID0 bits. The ID of the message buffer (x) is used as
the transmit message ID at transmitting and as the acceptance code at receiving.
• Set the ID after disabling the message buffer (x) (BVALR: BVALx = 0). Setting the ID with the
message buffer (x) enabled may store an unnecessary received message.
● Setting of acceptance filter
• The acceptance filter used in the message buffer (x) is set by a combination of the acceptance code and
acceptance mask. Set the acceptance filter after disabling the message buffer (x) (BVALR: BVALx = 0).
Setting the acceptance filter with the message buffer (x) enabled may store a message unnecessary
received.
• The acceptance mask used for each message buffer (x) is selected by the acceptance mask select register
(AMSR). When using the acceptance mask registers (AMR0 and AMR1), set the acceptance mask
register (AMR0.1), too.
• Set the acceptance mask so that a transmission request will not be canceled by storing an unnecessary
received message.
488
CHAPTER 15 CAN CONTROLLER
■ Procedure for Transmitting Message Buffer (x)
Figure 15.5-4 shows a procedure for the transmit setting.
Figure 15.5-4 Flowchart of Procedure for Transmit Setting
Start
Set bit timing
Set frame format
Set ID
Set acceptance filter
Bit timing register (BTR)
IDE register (IDER)
ID register (IDR)
Acceptance mask select register (AMSR)
Acceptance mask register (AMR0, 1)
Select message buffer to be used
Message buffer enable register (BVALR)
Set transmission complete interrupt
Transmission complete interrupt enable register (TIER)
Data frame
Remote frame
Select frame type
Set frame type
Reception RTR register (TRTRx = 1)
Set frame type
Transmission RTR register (TRTRx = 0)
Set request data length
DLC register (DLCR)
Set of transmission data length
DLC register (DLCR)
Store transmission data in data register
Data register (DTR)
Remote frame
receiving wait
YES
NO
Remote frame receiving wait
RFWTx = 0
Remote frame receiving wait
RFWTx = 1
Cancel bus halt
HALT = 1
Message transmission
Set transmission request of data frame
Data frame transmission (TREQR)
Remote frame receiving wait
Communication error
N:0
Is transmission successful?
TCx
Transmission cancel?
NO
YES
Y:1
Cancellation of transmission request
Transmission cancel register (TCANR)
TREQx
1
0
1
TCx
0
Transmission is completed
Transmission cancel
End
489
CHAPTER 15 CAN CONTROLLER
● Procedure for transmission message buffer (x)
After completion of presetting, set the message buffer (x) enabled (BVALR: BVALx =1) by message
buffer enable register.
● Setting transmit data length code
• Set the transmit data length code (byte count) to the DLC3 to DLC0 bits in the DLC register (DLCR).
• When transmitting a data frame (TRTRR: TRTRx = 0), set the data length of the transmit message.
• When transmitting a remote frame (TRTRR: TRTRx = 1), set the data length (byte count) of the
message to be requested.
Note:
Setting other than "0000B" to "1000B" (0 to 8 bytes) is prohibited.
● Setting transmit data (only for transmission of data frame)
When transmitting a data frame (TRTRR: TRTRx = 0), set the data of byte count to be transmitted in the
data register (DTR).
Note:
Rewrite transmit data after setting the TREQx bit in the transmit request register to "0". There is no
need to set the bit disabled in the message buffer enable register (BVALR: BVALx = 0). When the bit
is set to disabled, no remote frame can be received.
● Setting transmission RTR register (TRTRR)
• When transmitting a data frame, set the TRTRx bit in the transmission RTR register to "0".
• When transmitting a remote frame, set the TRTRx bit in the transmission RTR register to "1".
● Setting conditions for starting transmitting (only in transmitting data frame)
• When setting the request to transmit a data frame (TREQR: TREQx = 1 and TRTRR: TRTRx = 0) and
starting transmitting immediately, set the RFWTx bit in the remote frame wait register to "0".
• When setting the request to transmit a data frame (TREQR: TREQx = 1 and TRTRR: TRTRx = 0) and
starting transmitting after waiting until a remote frame is received (RRTRR: RRTRx = 1), set the
RFWTx bit in the remote frame wait register to "1".
Note:
When the RFWTx bit in the remote frame wait register is set to "1", no remote frame can be
transmitted.
490
CHAPTER 15 CAN CONTROLLER
● Setting transmission complete interrupt
• When enabling an interrupt when transmitting is completed (TCR: TCx = 1), set the TIEx bit in the
transmit complete enable register to "1".
• When disabling an interrupt when transmitting is completed (TCR: TCx = 1), set the TIEx bit in the
transmission complete enable register to "0".
● Canceling bus halt
After the completion of setting bit timing and transmitting, write 0 to the HALT bit in the control status
register (CSR: HALT) to cancel the bus halt.
● Setting transmission request
To set a transmission request, set the TREQx bit in the transmission request register to "1".
● Canceling transmission request
• To cancel the transmission request held in the message buffer (x), write 1 to the TCANx bit in the
transmission cancel register.
• Check the TREQx bit in the transmission request register (TREQR). When the TREQx bit is "0"
transmission cancel is terminated or transmitting is completed. After that, check the TCx bit in the
transmission complete register (TCR). If the TCx bit is "0", transmission cancellation is terminated and
if the TCx bit is "1", transmitting is completed.
● Processing when transmitting completed
• When transmitting is successful, "1" is set to the TCx bit in the transmit complete register (TCR).
• When a transmission complete interrupt is enabled (TIER: TIEx = 1), an interrupt is generated.
• After checking the completion of transmitting, write 0 to the TCx bit in the transmission complete
register (TCR) to clear the transmission complete register (TCR). When the transmission complete
register (TCR) is cleared, the transmission complete interrupt is canceled.
• When the message is received or stored, the held transmission requests are canceled as follows:
- When a data frame is received, the request to transmit a data frame is canceled.
- When a data frame is received, the request to transmit a remote frame is canceled.
- When a remote frame is received, the request to transmit a remote frame is canceled.
When a remote frame is received or stored, the request to transmit a data frame is not canceled but the data
in the ID register and DLC register are rewritten to the data of the received remote frame. Therefore, the
data in the ID register and DLC register for the data frame to be transmitted are replaced by data in the
received remote frame.
491
CHAPTER 15 CAN CONTROLLER
■ Procedure for Receiving Message Buffer (x)
Figure 15.5-5 shows the procedure for the receiving setting.
Figure 15.5-5 Flowchart of Procedure for Receive Setting
Start
Set bit timing
Set frame format
Set ID
Set acceptance filter
Bit timing register (BTR)
IDE register (IDER)
ID register (IDR)
Acceptance mask select register (AMSR)
Acceptance mask register (AMR0, 1)
Select message buffer to be used
Message buffer enable register (BVALR)
Set reception complete interrupt
Reception complete interrupt enable register (RIER)
Cancel bus halt
HALT = 1
NO
Message received?
RCx = 1 ?
YES
Received byte count reading
Message storing
(storing by reception complete interrupt)
Reception overrun bit clear
ROVRx = 0
Received message reading
Reception overrun?
ROVRx = 0?
NO
YES
Reception complete bit clear
RCx=0
End
● Procedure for receiving message buffer (x)
After presetting, perform the following setting:
● Setting reception complete interrupt
• To generate a reception complete interrupt, set the RIEx bit in the reception complete interrupt enable
register (RIER) to "1".
• To disable a reception complete interrupt (RCR: RCx = 1), set the RIEx bit to "0".
492
CHAPTER 15 CAN CONTROLLER
● Starting receiving
To start receiving after the completion of setting, set the BVALx bit in the message buffer enable register
(BVALR) to "1" and enable the message buffer (x).
● Canceling bus halt
After the completion of setting bit timing and transmitting, write 0 to the HALT bit in the control status
register (CSR: HALT) to cancel the bus halt.
● Processing when receiving completed
• If reception is successful after passing through the acceptance filter, the received message is stored in
the message buffer (x), "1" is set to the RCx of the reception complete register (RCR). For data frame
reception, RRTRx bit of the remote request receive register (RRTRR) is cleared to "0". For remote
frame reception, "1" is set to the RRTRx bit.
• If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is "1"), an
interrupt is generated.
• Process the received message after checking the completion of receiving (RCR: RCx = 1).
• Check the ROVRx bit in the receive overrun register (ROVRR) after the completion of processing the
received message.
- If the ROVRx bit is set to "0", the received message is enabled. When "0" is written to the RCx bit (a
reception complete interrupt is also canceled), receiving is terminated.
- If the ROVRx bit is set to "1", a receive overrun occurs and the new message may overwrite the
received message. When a receive overrun occurs, write 0 to the ROVRx bit and then process the
received message again.
493
CHAPTER 15 CAN CONTROLLER
Figure 15.5-6 shows an example of reception interrupt processing.
Figure 15.5-6 Example of Reception Interrupt Processing
Interrupt generation
with RCx = 1
Received message
reading
A : = ROVRx
ROVRx : = 0
A = 0?
YES
RCx : 0
Completion
494
NO
CHAPTER 15 CAN CONTROLLER
15.5.4
Setting Multiple Message Receiving
When there is insufficient time to receive messages such as frequently received
messages or messages with different IDs, more than one message buffer can be
combined to a multiple message buffer to give the CPU sufficient time to process
received messages.
To configure multiple message buffers, perform the same setting of acceptance filter of
the message buffers to be combined.
■ Setting Configuration of Multiple Message Buffer
When four messages in the standard frame format are received with doing the acceptance filter of message
buffers 5, 6 and 7 on the same settings, the multiple message buffer operates as shown in the figure.
Note:
When the acceptance mask select register is set to "full-bit comparison" (AMSR: AMSx.1, AMSx.0 =
00B), do not set the same acceptance code. When the register is set to "full-bit comparison", the
messages are always stored in the message buffer with the smaller number, so the message buffers
cannot be formed into a multiple message buffer.
495
CHAPTER 15 CAN CONTROLLER
Figure 15.5-7 Example of Operation of Multiple Message Buffer
AMS7
10
AMSR
Initial setting
AMS6
10
AMS5
10
. .
Acceptance mask
register selection
AMR0
AM28 to AM18
0000 1111 111
Message buffer 5
ID28 to ID18
0101 0000 000
Message buffer 6
0101 0000 000
IDE
0 . .
0 . .
0101 0000 000
. .
Message buffer 7
0
IDER
IDE7 IDE6 IDE5
. . .
0
0
0
RCR
RC7
0
RC6
0
0
ROVR7
0
ROVRR
RC5
. . .
0
. . .
0
6
5
Mask
Message receiving → stored in message buffer 5
Received message
ID28 to ID18
0101 1111 000
IDE
0 . .
Message buffer 5
0101 1111 000
0
. .
RCR
0
0
1
. . .
Message buffer 6
0101 0000 000
0
. .
ROVRR
0
0
0
. . .
Message buffer 7
0101 0000 000
0
. .
Message receiving → stored in message buffer 6
Received message
Message buffer 5
ID28 to ID18
0101 1111 001
0101 1111 000
IDE
0 . .
0
. .
RCR
0
1
1
. . .
ROVRR
0
0
0
. . .
Message buffer 6
0101 1111 001
0
. .
Message buffer 7
0101 0000 000
0
. .
Message receiving → stored in message buffer 7
Received message
Message buffer 5
ID28 to ID18
0101 1111 010
0101 1111 000
IDE
0 . .
0
. .
RCR
1
1
1
. . .
ROVRR
0
0
0
. . .
Message buffer 6
0101 1111 001
0
. .
Message buffer 7
0101 1111 010
0
. .
Message receiving → reception overrun (ROVR5 =1) generated, stored in message buffer 5
Received message
IDE
0 . .
Message buffer 5
0101 1111 011
0
. .
RCR
1
1
1
. . .
Message buffer 6
0101 1111 001
0
. .
ROVRR
0
0
1
. . .
0
. .
Message buffer 7
496
ID28 to ID18
0101 1111 011
0101 1111 010
CHAPTER 15 CAN CONTROLLER
15.6
Precautions when Using CAN Controller
Use of the CAN Controller requires the following cautions.
■ Caution for Disabling Message Buffers by BVAL bits
The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set disabled
while CAN Controller is participating in CAN communication (read value of HALT bit is "0" and CAN
Controller is ready to receive or transmit messages). This section shows the work around of this
malfunction.
● Condition
When following two conditions occur at the same time, CAN Controller will not perform to receive or
transmit messages normally.
• CAN Controller is participating in the CAN communication. (i.e. The read value of HALT bit is "0" and
CAN Controller is ready to receive or transmit messages)
• Message buffers are read or written when the message buffers are disabled by BVAL bits.
● Work around
Operation for re-configuring receiving message buffers
While CAN Controller is participating in CAN communication (the read value of HALT bit is "0" and
CAN Controller is ready to receive or transmit messages), it is necessary to following one from the two
operations described below to re-configure message buffers by ID, AMS and AMR0/1 register-settings.
• Use of HALT bit
- Write "1" to HALT bit and read it back for checking the result is "1". Then change the settings for
ID/AMS/AMR0/1 registers.
• No Use of Message Buffer 0
- Don't use the message buffer 0. In other words, disable message buffer (BVAL0=0), prohibit receive
interrupt (RIE0=0) and do not request transmission (TREQx=0).
Operation for processing received message
When the receive message is read from the message buffer, the next message can be overwritten. Don't
use the receiving prohibition (BVALR:BVALx=0) by BVALx bit of the message buffer valid register to
avoid over-written of next message. To read the receive message from the message buffer surely, check
the overwriting to the message by the ROVRx bit of receive overrun register (ROVRR) before and after
the message reading. For details, refer to section "15.3.16 Reception Overrun Register (ROVRR)" and
"15.5.3 Procedures for Transmitting and Receiving".
Operation for suppressing transmission request
Don't set the transmission prohibition (BVALR:BVALx=0) by the BVALx bit of a message buffer valid
register, to cancel the transmission request. Set the TCANx bit of receive cancel register (TCANR) to
"1", to cancel the transmission request.
497
CHAPTER 15 CAN CONTROLLER
Operation for composing transmission message
For composing a transmission message, it is necessary to disable the message buffer by BVAL bit to
change contents of ID and IDE registers. Set the BVALx bit to invalid (BVALR:BVALx=0) after
checking that it is checked that the TREQx bit of transmission request register (TREQR) is "0" or the
TCx bit of transmission complete register (TCR) is "1".
498
CHAPTER 15 CAN CONTROLLER
15.7
Program Example of CAN Controller
This section shows the program example of CAN controller.
■ Program Example of CAN Transmission and Reception
● Processing specifications
• Set message buffer 5 of CAN to data frame transmit mode and message buffer 0 to data frame receive
mode.
• Setting of frame format:
Standard frame format
• Setting of ID:
message buffer 0 ID = 1, message buffer 5 ID = 5
• Baud rate:
100 kbps (machine clock = 16 MHz)
• Acceptance mask selection: Setting full-bit comparison
• After entering the bus mode (HALT = 0), data A0A0His transmitted.
• A transmission request is made within the transmission complete interrupt routine (TREQx=1) to
transmit the same data (When TREQx is set to start sending, the transmission complete interrupt bit is
cleared).
• The reception complete interrupt bit is cleared within the reception interrupt routine.
499
CHAPTER 15 CAN CONTROLLER
● Coding example
:
:
:
;//Setting of data format (CAN initialization)
MOVW BTR,#05CC7H
; Setting baud rate 100 kbps
MOVW IDER, #0000H
; (Machine clock = 16 MHz)
; Setting of frame format
; (0: Standard, 1:Expanded)
MOVW IDR51,#0A000H
; Setting of data frame 5 ID (ID = 5)
MOVW IDR01,#2000H
; Setting of data frame 0 ID (ID = 1)
MOVW AMSR,#0000H
; Acceptance mask select register
; (full-bit comparison)
MOVW BVALR,#021H
; Message buffers 5 and 0 enabled
;//Transmit setting
MOVW DLCR5,#02H
; Setting of transmission data length
; (00H: 0-byte length, 08H: 8-byte length)
MOVW RFWTR,#0000H
; Remote frame receive wait register
MOVW TRTRR,#0000H
; Transmission RTR register (0: Data frame
; transmission, 1: Remote frame transmission)
MOVW TIER,#0020H
; Transmission complete interrupt enable register
;//Reception setting
MOVW RIER,#0001H
; Reception complete interrupt enable register
;//Bus operation start
MOV CSR0,#80H
; Control status register (HALT=0)
sthlt
BBS CSR0:0,sthlt
; Wait until HALT=0
;//Transmission data set
MOVW DTR5,#0A0A0H
; Write A0A0H to data register of message buffer 5.
MOVW TREQR,#0020H
; Transmission request register
; (1: Transmission start, 0: Transmission stop)
:
:
:
;//Reception complete interrupt
CANRX
MOVW RCR,#0000H
; Reception complete register
RETI
;//Transmission complete interrupt
CANTX
MOVW TREQR,#0020H
; Transmission request register
; (1: Transmission start, 0: Transmission stop)
RETI
500
CHAPTER 16
8/16 ADDRESS MATCH
DETECTION FUNCTION
This chapter explains the address match detection
function and its operation.
16.1 Overview of Address Match Detection Function
16.2 Block Diagram of Address Match Detection Function
16.3 Configuration of Address Match Detection Function
16.4 Explanation of Operation of Address Match Detection Function
16.5 Program Example of Address Match Detection Function
501
CHAPTER 16 8/16 ADDRESS MATCH DETECTION FUNCTION
16.1
Overview of Address Match Detection Function
If the address of the instruction to be processed next to the instruction currently
processed by the program matches the address set in the detect address setting
registers, the address match detection function forcibly replaces the next instruction to
be processed by the program with the INT9 instruction to branch to the interrupt
processing program. Since the address match detection function can use the INT9
interrupt for instruction processing, the program can be corrected by patch processing.
■ Overview of Address Match Detection Function
• The address of the instruction to be processed next to the instruction currently processed by the program
is always held in the address latch through the internal bus. The address match detection function always
compares the value of the address held in the address latch with that of the address set in the detect
address setting registers. When these compared values match, the next instruction to be processed by the
CPU is forcibly replaced by the INT9 instruction, and the interrupt processing program is executed.
• There are two detect address setting registers (PADR0 and PADR1), each of which has an interrupt
enable bit. The generation of an interrupt due to a match between the address held in the address latch
and the address set in the detect address setting registers can be enabled and disabled for each register.
502
CHAPTER 16 8/16 ADDRESS MATCH DETECTION FUNCTION
16.2
Block Diagram of Address Match Detection Function
The address match detection module consists of the following blocks:
• Address latch
• Address detection control register (PACSR)
• Detect address setting registers
■ Block Diagram of Address Match Detection Function
Figure 16.2-1 shows the block diagram of the address match detection function.
Figure 16.2-1 Block Diagram of the Address Match Detection Function
PADR0 (24bit)
Detect address setting register 0
PADR1 (24bit)
Comparator
Internal data bus
Address latch
INT9 instruction
(INT9 interrupt
generation)
Detect address setting register 1
PACSR
Reserved Reserved Reserved Reserved AD1E Reserved AD0E Reserved
Address detection control register (PACSR)
Reserved: Always set to "0"
● Address latch
The address latch retains the value of the address output to the internal data bus.
● Address detection control register (PACSR)
The address detection control register enables or disables output of an interrupt at an address match.
● Detect address setting registers (PADR0, PADR1)
The detect address setting registers set the address that is compared with the value of the address latch.
503
CHAPTER 16 8/16 ADDRESS MATCH DETECTION FUNCTION
16.3
Configuration of Address Match Detection Function
This section details the registers used by the address match detection function.
■ List of Registers and Reset Values of Address Match Detection Function
Figure 16.3-1 List of Registers and Reset Values of Address Match Detection Function
bit
Address detection control register (PACSR)
bit
Detect address setting register 0 (PADR0):
High
bit
Detect address setting register 0 (PADR0):
Middle
bit
Detect address setting register 0 (PADR0):
Low
bit
Detect address setting register 1 (PADR1):
High
bit
Detect address setting register 1 (PADR1):
Middle
bit
Detect address setting register 1 (PADR1):
Low
X: Undefined
504
7
0
7
6
0
6
5
0
5
4
0
4
3
0
3
2
0
2
1
0
1
0
0
0
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
CHAPTER 16 8/16 ADDRESS MATCH DETECTION FUNCTION
16.3.1
Address Detection Control Register (PACSR)
The address detection control register (PACSR) enables or disables output of an
interrupt at an address match. When an address match is detected if output of an
interrupt at an address match is enabled, the INT9 interrupt is output.
■ Address Detection Control Register (PACSR)
Figure 16.3-2 Address Detection Control Register (PACSR)
Address:
00009EH
7
6
5
4
3
2
1
0
Reset value
00000000
B
R/W R/W R/W R/W R/W R/W R/W R/W
bit 0
Reserved bit
Reserved
0
Always set to "0"
bit 1
Address match detection enable bit 0
AD0E
0
Disables address match detection in PADR0
1
Enables address match detection in PADR0
bit 2
Reserved bit
Reserved
0
Always set to "0"
bit 3
Address match detection enable bit 1
AD1E
0
Disables address match detection in PADR1
1
Enables address match detection in PADR1
bit 4
Reserved bit
Reserved
0
Always set to "0"
bit 5
Reserved bit
Reserved
0
Always set to "0"
bit 6
Reserved bit
Reserved
0
Always set to "0"
bit 7
Reserved bit
Reserved
R/W : Read/Write
: Reset value
0
Always set to "0"
505
CHAPTER 16 8/16 ADDRESS MATCH DETECTION FUNCTION
Table 16.3-1 Functions of Address Detection Control Register (PACSR)
Bit Name
bit 7 to
bit 4
506
Function
Reserved: reserved bit
Always set to "0".
bit 3
AD1E:
Address match
detection enable bit 1
The address match detection operation with the detect address setting
register 1 (PADR1) is enabled or disabled.
When set to "0": Disables the address match detection operation.
When set to "1": Enables the address match detection operation.
When the value of detect address setting registers 1 (PADR1) matches
with the value of address latch at enabling the address match detection
operation (AD1E = 1), the INT9 instruction is immediately executed.
bit 2
Reserved: reserved bit
Always set to "0".
bit 1
AD0E:
Address match
detection enable bit 0
The address match detection operation with the detect address setting
register 0 (PADR0) is enabled or disabled.
When set to "0": Disables the address match detection operation.
When set to "1": Enables the address match detection operation.
When the value of detect address setting register 0 (PADR0) matches
with the value of address latch at enabling the address match detect
operation (AD0E = 1), the INT9 instruction is immediately executed.
bit 0
Reserved: reserved bit
Always set to "0".
CHAPTER 16 8/16 ADDRESS MATCH DETECTION FUNCTION
16.3.2
Detect Address Setting Registers (PADR0 and PADR1)
The value of an address to be detected is set in the detect address setting registers.
When the address of the instruction processed by the program matches the address set
in the detect address setting registers, the next instruction is forcibly replaced by the
INT9 instruction, and the interrupt processing program is executed.
■ Detect Address Setting Registers (PADR0 and PADR1)
Figure 16.3-3 Detect Address Setting Registers (PADR0 and PADR1)
PADR0, PADR1:
High
001FF0H, 001FF3H
PADR0, PADR1:
Middle
001FF1H, 001FF4H
PADR0, PADR1:
Low
001FF2H, 001FF5H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reset value
D23
D22
D21
D20
D19
D18
D17
D16
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Reset value
D15
D14
D13
D12
D11
D10
D9
D8
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reset value
D7
D6
D5
D4
D3
D2
D1
D0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Read/Write
X: Undefined
507
CHAPTER 16 8/16 ADDRESS MATCH DETECTION FUNCTION
■ Functions of Detect Address Setting Registers
• There are two detect address setting registers (PADR0 and PADR1) that consist of three bytes, a high
byte (bank), middle byte, and low byte, totaling 24 bits.
Table 16.3-2 Address Setting of Detect Address Setting Registers
Register Name
Interrupt Output Enable
Address Setting
High
Detect address setting
register 0 (PADR0)
Detect address setting
register 1 (PADR1)
PACSR: AD0E
PACSR: AD1E
Set the upper 8 bits of detect address 0 (bank).
Middle
Set the middle 8 bits of detect address 0.
Low
Set the lower 8 bits of detect address 0.
High
Set the upper 8 bits of detect address 1 (bank).
Middle
Set the middle 8 bits of detect address 1.
Low
Set the lower 8 bits of detect address 1.
• In the detect address setting registers (PADR0 and PADR1), starting address (first byte) of instruction to
be replaced by INT9 instruction should be set.
Figure 16.3-4 Setting of Starting Address of Instruction Code to be Replaced by INT9
Set to detect address (High : FFH, Middle : 00H, Low : 1FH)
Address
Instruction code
FF001CH:
FF001FH:
FF0022H:
A8 00 00
4A 00 00
4A 80 08
Mnemonic
MOVW
MOVW
MOVW
RW0, #0000
A, #0000
A,#0880
Notes:
• When an address of other than the first byte is set to the detect address setting register (PADR0
and PADR1), the instruction code is not replaced by INT9 instruction and a program of an
interrupt processing is not be performed. When the address is set to the second byte or
subsequent, the address set by the instruction code is replaced by "01" (INT9 instruction code)
and, which may cause malfunction.
• The detect address setting registers (PADR0 and PADR1) should be set after disabling the
address match detection (PACSR: AD0E = 0 or AD1E = 0) of corresponding address match
control registers. If the detect address setting registers are changed without disabling the address
match detection, the address match detection function will work immediately after an address
match occurs during writing address, which may cause malfunction.
• The address match detection function can be used only for addresses of the internal ROM area. If
addresses of the external memory area are set, the address match detection function will not work
and the INT9 instruction will not be executed.
508
CHAPTER 16 8/16 ADDRESS MATCH DETECTION FUNCTION
16.4
Explanation of Operation of Address Match Detection
Function
If the addresses of the instructions executed in the program match those set in the
detection address setting registers (PADR0 and PADR1), the address match detection
function will replace the first instruction code with the INT9 instruction (01H) to branch
to the interrupt processing program.
■ Operation of Address Match Detection Function
Figure 16.4-1 shows the operation of the address match detection function when the detect addresses are set
and an address match is detected.
Figure 16.4-1 Operation of Address Match Detection Function
Program execution
The instruction address to be
executed by program matches
detect address setting register 0
Address
Instruction code
FF001CH:
FF001FH:
FF0022H:
A8 00 00
4A 00 00
4A 80 08
Mnemonic
MOVW
MOVW
MOVW
RW0, #0000
A, #0000
A, #0880
Replaced by INT9 instruction (01H)
■ Setting Detect Address
1. Disable the detection address setting register 0 (PADR0) where the detect address is set for address
match detection (PACSR: AD0E = 0).
2. Set the detect address in the detection address setting register 0 (PADR0). Set "FFH" at the higher bits of
the detection address setting register 0 (PADR0), "00H" at the middle bits, and "1FH" at the lower bits.
3. Enable the detect address setting register 0 (PADR0) where the detect address is set for address match
detection (PACSR: AD0E = 1).
■ Program Execution
1. If the address of the instruction to be executed in the program matches the set detect address, the first
instruction code at the matched address is replaced by the INT9 instruction code (01H).
2. INT9 instruction is executed. INT9 interrupt is generated and then interrupt processing program is
executed.
509
CHAPTER 16 8/16 ADDRESS MATCH DETECTION FUNCTION
16.4.1
Example of using Address Match Detection Function
This section gives an example of patch processing for program correction using the
address match detection function.
■ System Configuration and E2PROM Memory Map
● System configuration
Figure 16.4-2 gives an example of the system configuration using the address match detection function.
Figure 16.4-2 Example of System Configuration using Address Match Detection Function
Serial E2PROM
Interface
MCU
F2MC 16LX
E2PROM
Storing patch program
Pull up resistor
SIN
Connector (UART)
Storing patch program from the outside
510
CHAPTER 16 8/16 ADDRESS MATCH DETECTION FUNCTION
■ E2PROM Memory Map
Figure 16.4-3 shows the allocation of the patch program and data at storing the patch program in E2PROM.
Figure 16.4-3 Allocation of E2PROM Patch Program and Data
E2PROM
Address
PADR0
PADR1
0000H
Patch program byte count
0001H
Detect address 0 (Low)
0002H
Detect address 0 (Middle)
0003H
Detect address 0 (High)
0004H
Patch program byte count
0005H
Detect address 1 (Low)
0006H
Detect address 1 (Middle)
0007H
Detect address 1 (High)
0010H
Patch program 0
(main body)
0020H
Patch program 1
(main body)
For patch program 0
For patch program 1
● Patch program byte count
The total byte count of the patch program (main body) is stored. If the byte count is "00H", it indicates that
no patch program is provided.
● Detect address (24 bits)
The address where the instruction code is replaced by the INT9 instruction code due to program error is
stored. This address is set in the detection address setting registers (PADR0 and PADR1).
● Patch program (main body)
The program executed by the INT9 interrupt processing when the program address matches the detect
address is stored. Patch program 0 is allocated from any predetermined address. Patch program 1 is
allocated from the address indicating <starting address of patch program 0 + total byte count of patch
program 0>.
511
CHAPTER 16 8/16 ADDRESS MATCH DETECTION FUNCTION
■ Setting and Operating State
● Initialization
E2PROM data are all cleared to "00H".
● Occurrence of program error
• By using the connector (UART), information about the patch program is transmitted to the MCU
(F2MC-16LX) from the outside according to the allocation of the E2PROM patch program and data.
• The MCU (F2MC-16LX) stores the information received from outside in the E2PROM.
● Reset sequence
• After reset, the MCU (F2MC-16LX) reads the byte count of the E2PROM patch program to check the
presence or absence of the correction program.
• If the byte count of the patch program is not "00H", the higher, middle and lower bits at detect addresses
0 and 1 are read and set in the detection address setting registers 0 and 1 (PADR0 and PADR1). The
patch program (main body) is read according to the byte count of the patch program and written to
RAM in the MCU (F2MC-16LX).
• The patch program (main body) is allocated to the address where the patch program is executed in the
INT9 interrupt processing by the address match detection function.
• Address match detection is enabled (PACSR: AD0E = 1, AD1E = 1)
● INT9 Interrupt processing
• Interrupt processing is performed by the INT9 instruction. The MB90385 series has no interrupt request
flag by address match detection. Therefore, if the stack information in the program counter is discarded,
the detect address cannot be checked. When checking the detect address, check the value of program
counter stacked in the interrupt processing routine.
• After the patch program is executed, the normal program is branched.
512
CHAPTER 16 8/16 ADDRESS MATCH DETECTION FUNCTION
■ Operation of Address Match Detection Function at Storing Patch Program in
E2PROM
Figure 16.4-4 shows the operation of the address match detection function at storing the patch
program in E2PROM.
Figure 16.4-4 Operation of Address Match Detection Function at Storing Patch Program in
E2PROM
000000 H
(3)
Patch program
RAM
Detection address setting register
E2PROM
(1)
Detection address setting
(reset sequence)
Serial E2PROM
interface
. Patch program byte count
. Address for address detection
. Patch program
ROM
(2)
(4)
Program error
FFFFFFH
(1) Execution of detection address setting of reset sequence and normal program
(2) Branch to patch program which expanded in RAM with INT9 interrupt processing by address match detection
(3) Patch program execution by branching of INT9 processing
(4) Execution of normal program which branches from patch program
513
CHAPTER 16 8/16 ADDRESS MATCH DETECTION FUNCTION
■ Flow of Patch Processing
Figure 16.4-5 shows the flow of patch processing using the address match detection function.
Figure 16.4-5 Flow of Patch Processing
E2PROM
MB90387(s)
000000H
I/O area
000100H
Register/RAM area
000400H
Patch program
000480H
RAM area
RAM
Stack area
0000 H
Patch program byte count : 80H
0001 H
Detect address (Low) : 00H
0002 H
Detect address (Middle) : 80H
0003 H
Detect address (High) : FFH
0010 H
Patch program
000900H
Detection address setting register
0090 H
FFFFH
FF0000H
FF8000H
ROM
Program error
FF8050H
FFFFFF H
YES
Reset
INT9
Read the 00H
of E2PROM
Branch to patch program
JMP 000400H
Execution of patch program
000400H to 000480H
E2PROM : 0000H
=0
NO
End of patch program
JMP FF8050H
Read detect address
E2PROM : 0001H to 0003H
↓
MCU : Set to PADR0
Read patch program
E2PROM : 0010H to 008FH
↓
MCU : 000400H to 00047FH
Enable address match detection
(PACSR : AD0E = 1)
Execution of normal
program
NO
514
Program address
= PADR0
YES
INT9
CHAPTER 16 8/16 ADDRESS MATCH DETECTION FUNCTION
16.5
Program Example of Address Match Detection Function
This section gives a program example for the address match detection function.
■ Program Example for Address Match Detection Function
● Processing specifications
If the address of the instruction to be executed by the program matches the address set in the detection
address setting register (PADR0), the INT9 instruction is executed.
● Coding example
PACSR
EQU 00009EH
; Address detection control register
PADRL
EQU 001FF0H
; Detection address setting register 0 (Low)
PADRM
EQU 001FF1H
; Detection address setting register 0 (Middle)
PADRH
EQU 001FF2H
; Detection address setting register 0 (High)
;
;-----Main program--------------------------------------------------------------CODE
CSEG
START:
; Stack pointer (SP), etc.,
; already reset
MOV PADRL,#00H
; Set address detection register 0 (Low)
MOV PADRM,#00H
; Set address detection register 0 (Middle)
MOV PADRH,#00H
; Set address detection register 0 (High)
;
MOV I:PACSR,#00000010B ; Enable address match
:
processing by user
:
LOOP:
:
processing by user
:
BAR LOOP
;-----Interrupt program---------------------------------------------------------WARI:
:
processing by user
:
RETI
; Return from interrupt processing
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG 00FFDCH
DSL WARI
ORG 00FFDCH
; Set reset vector
DSL START
DB
00H
; Set to single-chip mode
VECT
ENDS
END START
515
CHAPTER 16 8/16 ADDRESS MATCH DETECTION FUNCTION
516
CHAPTER 17
ROM MIRRORING FUNCTION
SELECT MODULE
This chapter describes the functions and operations of
the ROM mirroring function select module.
17.1 Overview of ROM Mirroring Function Select Module
17.2 ROM Mirroring Function Select Register (ROMM)
517
CHAPTER 17 ROM MIRRORING FUNCTION SELECT MODULE
17.1
Overview of ROM Mirroring Function Select Module
The ROM mirroring function select module provides a setting so that ROM data in the
FF bank can be read by access to the 00 bank.
■ Block Diagram of ROM Mirroring Function Select Module
Figure 17.1-1 Block Diagram of ROM Mirroring Function Select Module
ROM mirroring function select register (ROMM)
Reserved Reserved Reserved Reserved Reserved Reserved Reserved MI
Address
Internal data bus
Address area
00 bank
FF bank
Data
ROM
■ Access to FF Bank by ROM Mirroring Function
Figure 17.1-2 shows the location in memory when ROM mirroring function allows access to the 00 bank to
read ROM data in the FF bank.
Figure 17.1-2 Access to FF Bank by ROM Mirroring Function
004000 H
00 bank
ROM mirror area
00FFFFH
FC0000H
FEFFFF H
FF0000 H
FF4000 H
FFFFFFH
518
MB90V495G
FF bank
(ROM mirror-target area)
MB90F387/S
MB90387/S
CHAPTER 17 ROM MIRRORING FUNCTION SELECT MODULE
■ Memory Space when ROM Mirroring Function Enabled/Disabled
Figure 17.1-3 shows the availability of access to memory space when the ROM mirroring function is
enabled or disabled.
Figure 17.1-3 Memory Space when ROM Mirroring Function Enabled/Disabled (in Single Chip Mode)
000000H
I/O area
I/O area
RAM area
RAM area
Extend I/O area
Extend I/O area
0000C0H
000100H
Address 1
003900H
004000H
ROM area
010000H
FE0000H
ROM area*
ROM area*
ROM area
ROM area
FF0000H
FFFFFFH
When ROM mirroring
function enabled
When ROM mirroring
function disabled
Product type MB90V495G MB90F387/S MB90387/S
Address 1
000900H
001900H
000900H
: Internal access memory
: Access disabled
: When the area from "FE0000H" to "FEFFFFH" of MB90387/S or MB90F387/S
is read out, the area "FF0000H" to "FFFFFFH" can be read.
■ List of Registers and Reset Values of ROM Mirroring Function Select Module
Figure 17.1-4 List of Registers and Reset Values of ROM Mirroring Function Select Module
bit
ROM mirroring function select register
(ROMM)
15
14
13
12
11
10
9
8
X
X
X
X
X
X
X
1
X: Undefined
519
CHAPTER 17 ROM MIRRORING FUNCTION SELECT MODULE
17.2
ROM Mirroring Function Select Register (ROMM)
The ROM mirroring function select register (ROMM) enables or disables the ROM
mirroring function. When the ROM mirroring function is enabled, ROM data in the FF
bank can be read by access to the 00 bank.
■ ROM Mirroring Function Select Register (ROMM)
Figure 17.2-1 ROM Mirroring Function Select Register (ROMM)
Address:
00006FH
15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
⎯
⎯
⎯
W
W
X
⎯
:
:
:
:
Reset value
XXXXXXX1B
bit 8
Write only
Undefined
Unused
Reset value
MI
0
1
ROM mirroring function select bit
ROM mirroring function disabled
ROM mirroring function enabled
Table 17.2-1 Functions of ROM Mirroring Function Select Register (ROMM)
Bit Name
bit 15 to bit 9
bit 8
Function
Unused bits
Read: Value undefined
Be sure to set these bits to "0".
MI:
ROM mirroring function
select bit
This bit enables or disables the ROM mirroring function.
When set to "0": Disables ROM mirroring function
When set to "1": Enables ROM mirroring function
When the ROM mirroring function is enabled (MI = 1), data at ROM
addresses "FF4000H" to "FFFFFFH" can be read by accessing addresses
"004000H" to "00FFFFH"
Note:
While the ROM area at addresses "004000H" to "00FFFFH" is being used, access to the ROM
mirroring function select register (ROMM) is prohibited.
520
CHAPTER 18
512 KBIT FLASH MEMORY
This chapter describes the function and operation of
512 Kbit flash memory.
18.1 Overview of 512 Kbit Flash Memory
18.2 Registers and Sector Configuration of Flash Memory
18.3 Flash Memory Control Status Register (FMCS)
18.4 How to Start Automatic Algorithm of Flash Memory
18.5 Check the Execution State of Automatic Algorithm
18.6 Details of Programming/Erasing Flash Memory
18.7 Program Example of 512 Kbit Flash Memory
521
CHAPTER 18 512 KBIT FLASH MEMORY
18.1
Overview of 512 Kbit Flash Memory
There are three ways of programming and erasing flash memory as follows:
• Programming and erasing using parallel writer
• Programming and erasing using serial writer
• Programming and erasing by executing program
This chapter describes the above "Programming and Erasing by Executing Program".
■ Overview of 512 Kbit Flash Memory
512 Kbit flash memory is placed in the FFH banks on the CPU memory map. The function of the flash
memory interface circuit provides read access and program access from the CPU to flash memory.
Programming and erasing flash memory are enabled by an instruction from the CPU via the flash memory
interface circuit. This allows reprogramming in the mounted state under CPU control and improvement of
programming data efficiency.
■ Features of 512 Kbit Flash Memory
• 128 Kwords × 8 bits/64 Kwords × 16 bits (16 K + 8 K + 8 K + 32 K) sector configuration
• Uses automatic program algorithm (Embedded AlgorithmTM: the same manner as MBM29LV200)
• Erase pause/restart function
• Detects completion of writing/erasing using data polling or toggle bit functions
• Detects completion of writing/erasing by CPU interrupts
• Sector erase function (any combination of sectors)
• Programming/erase count 10,000 (min.)
• Flash read cycle time (min.): 2 machine cycles
• Sector protection function
• Temporary sector protection cancel function
• Extend sector protection function
Embedded AlgorithmTM is a registered trademark of Advanced Micro Devices, Inc.
Note:
The function for reading the manufacture code and device code is unprovided.
These codes cannot be accessed by any command.
■ Programming and Erasing Flash Memory
• Programming and erasing flash memory cannot be performed at one time.
• Programming or erasing flash memory can be performed by copying the program in flash memory to
RAM and executing the program copied in RAM.
522
CHAPTER 18 512 KBIT FLASH MEMORY
18.2
Registers and Sector Configuration of Flash Memory
This section explains the registers and the sector configuration of flash memory.
■ List of Registers and Reset Values of Flash Memory
Figure 18.2-1 List of Registers and Reset Values of Flash Memory
bit
Flash memory control status
register (FMCS)
7
6
5
4
3
2
1
0
0
0
0
X
0
0
0
0
X: Undefined
■ Sector Configuration of 512 Kbit Flash Memory
Figure 18.2-2 shows the sector configuration of 512 Kbit flash memory. The upper and lower addresses of
each sector are given in the figure.
● Sector configuration
For access from the CPU, the FF bank register has SA0 to SA3.
Figure 18.2-2 Sector Configuration of 512 Kbit Flash Memory
Flash memory
CPU address
Writer address*
FF0000H
70000H
FF7FFF H
77FFFH
FF8000H
78000H
FF9FFF H
79FFFH
FFA000H
7A000H
FFBFFF H
7BFFF H
FFC000 H
7C000H
FFFFFF H
7FFFFH
SA0 (32 Kbytes)
SA1 (8 Kbytes)
SA2 (8 Kbytes)
SA3 (16 Kbytes)
*: The writer address is equivalent to the CPU address when data is
programmed to flash memory by a parallel writer. This address is
where programming and erasing are performed by a generalpurpose writer.
523
CHAPTER 18 512 KBIT FLASH MEMORY
18.3
Flash Memory Control Status Register (FMCS)
The flash memory control status register (FMCS) functions are shown in Figure 18.3-1.
■ Flash Memory Control Status Register (FMCS)
Figure 18.3-1 Flash Memory Control Status Register (FMCS)
Address:
0000AEH
7
6
5
4
3
2
1
0
R
W
W
W
W
Reset value
000X0000B
R/W R/W R/W
bit 0
Reserved bit
Reserved
0
Always set to "0"
bit 1
Reserved bit
Reserved
0
Always set to "0"
bit 2
Reserved bit
Reserved
0
Always set to "0"
bit 3
Reserved bit
Reserved
0
Always set to "0"
bit 4
Flash memory programming/erasing status bit
RDY
0
Programming/erasing (next data programming/erasing disabled)
1
Programming/erasing terminated (next data programming/erasing enabled)
bit 5
WE
0
1
Flash memory programming/erasing enable bit
Programming/erasing flash memory area disabled
Programming/erasing flash memory area enabled
bit 6
RDYINT
0
1
Flash memory operation flag bit
Read
Programming/erasing
Write
This RDYINT bit cleared
Programming/erasing terminated No effect
bit 7
R/W
R
W
X
524
:
:
:
:
:
Read/Write
Read only
Write only
Undefined
Reset value
INTE Flash memory programming/erasing interrupt enable bit
0
Interrupt disabled at end of programming/erasing
1
Interrupt enabled at end of programming/erasing
CHAPTER 18 512 KBIT FLASH MEMORY
Table 18.3-1 Functions of Flash Memory Control Status Register (FMCS)
Bit Name
Function
bit 7
INTE:
Flash memory
programming/erasing
interrupt enable bit
This bit enables or disables an interrupt as programming/erasing flash
memory is terminated.
When set to "1":If the flash memory operation flag bit is set to "0" (FMCS:
RDYINT = 1), an interrupt is generated.
bit 6
RDYINT:
Flash memory operation
flag bit
This bit shows the operating state of flash memory.
If programming/erasing flash memory is terminated, the RDYINT bit is set to
"1" in timing of termination of the automatic flash memory algorithm.
• If the RDYINT bit is set to "1" when an interrupt as programming/erasing
flash memory is terminated is enabled (FMCS: INTE = 1), an interrupt is
generated.
• If the RDYINT bit is "0", programming/erasing flash memory is disabled.
When set to "0": Cleared.
When set to "1": No effect.
If the read-modify-write (RMW) instructions are used, "1" is always read.
bit 5
WE:
Flash memory
programming/erasing
enable bit
This bit enables or disables the programming/erasing of flash memory area.
The WE bit should be set before starting the command to program/erase flash
memory.
When set to "0":No program/erase signal is generated even if the command
to program/erase the FF bank is input.
When set to "1":Programming/erasing flash memory is enabled after
inputting program/erase command to the FF bank.
• When not performing programming/erasing, the WE bit should be set to
"0" so as not to accidentally program or erase flash memory.
bit 4
RDY:
Flash memory
programming/erasing
status bit
This bit shows the programming/erasing status of flash memory.
• If the RDY bit is "0", programming/erasing flash memory is disabled.
• The read/reset command and sector erasing pause command can be
accepted even if the RDY bit is "0". The RDY bit is set to "0" when
programming/erasing is completed.
Reserved: Reserved bits
Always set these bits to "0".
bit 3 to bit 0
525
CHAPTER 18 512 KBIT FLASH MEMORY
Note:
The flash memory operation flag bit (RDYINT) and flash memory programming/erasing status bit
(RDY) do not change simultaneously. A program should be created so that either RDYINT bit or
RDY bit can identify the termination of programming/erasing.
Automatic algorithm
end timing
RDYINT bit
RDY bit
1 Machine cycle
526
CHAPTER 18 512 KBIT FLASH MEMORY
18.4
How to Start Automatic Algorithm of Flash Memory
There are four commands for starting the automatic algorithm of flash memory: read/
reset, write, chip erase, sector erase. The sector erase command controls suspension
and resumption of sector erase.
■ Command Sequence Table
Table 18.4-1 lists the commands used in programming/erasing flash memory.
All data is written to command registers by byte access but should be written by word access in the normal
mode. Upper data bytes are ignored.
Table 18.4-1 Command Sequence Table
Write Cycle of Write Cycle of Write Cycle of Write Cycle of Write Cycle of Write Cycle of
Command Bus
Write
First Bus
Second Bus
Third Bus
Fourth Bus
Fifth Bus
Sixth Bus
Sequence
Access Address Data Address Data Address Data Address Data Address Data Address Data
Read/
FFXXXX XXF0
1
Reset*
Read/
FFAAAA XXAA
4
Reset*
Write
FFAAAA XXAA
4
Program
(even) (word)
Chip
FFAAAA XXAA
6
Erase
Sector
FFAAAA XXAA
6
Erase
(even)
Sector Erase Suspend Input of address"FFXXXX"Data (xxB0H) suspends sector erasing.
Sector Erase Resume
Auto
Select
3
Input address"FFXXXX"Data (xx30H) suspends and resumes sector erasing.
FFAAAA XXAA
*: Two kinds of read/reset commands can reset flash memory to the read mode.
Notes:
• Addresses in the table are the values in the CPU memory map. All addresses and data are
hexadecimal values, where "x" is any value.
• RA: Read address
• PA: Program address. Only even addresses can be specified.
• SA: Sector address (See "18.2 Registers and Sector Configuration of Flash Memory")
• RD: Read data
• PD: Program data. Only word data can be specified.
527
CHAPTER 18 512 KBIT FLASH MEMORY
Auto Select in Table 18.4-2 is the command to check the state of sector protection. The addresses must be
set as indicated below together with the command in Table 18.4-2.
Table 18.4-2 Address Setting for Auto Select
Sector protection
AQ13 to AQ15
AQ7
AQ2
AQ1
AQ0
DQ7 to DQ0
Sector address
L
H
L
L
CODE *
*: The output at the protected sector address is "01H".
The output at the unprotected sector address is "00H".
528
CHAPTER 18 512 KBIT FLASH MEMORY
18.5
Check the Execution State of Automatic Algorithm
Since the programming/erasing flow is controlled by the automatic algorithm, hardware
sequence flag can check the internal operating state of flash memory.
■ Hardware Sequence Flags
● Overview of hardware sequence flag
The hardware sequence flag consists of the following 5-bit outputs:
• Data polling flag (DQ7)
• Toggle bit flag (DQ6)
• Timing limit over flag (DQ5)
• Sector erasing timer flag (DQ3)
• Toggle bit 2 flag (DQ2)
Hardware sequence flags can be used to check whether programming, chip and sector erasing, and erase
code writing are enabled.
The hardware sequence flags can be referred by setting command sequences and performing read access to
the address of a target sector in flash memory. Table 18.5-1 gives the bit allocation of the hardware
sequence flags.
Table 18.5-1 Bit Allocation of Hardware Sequence Flags
Bit No.
Hardware sequence flag
7
6
5
4
3
2
1
0
DQ7
DQ6
DQ5
−
DQ3
DQ2
−
−
• To identify whether automatic programming/chip and sector erasing is in execution or terminated, check
the hardware sequence flag or the flash memory programming/erasing status bit in the flash memory
control status register (FMCS: RDY). Programming/erasing is terminated, returning to the read/reset
state.
• To create a programming/erasing program, use the DQ7, DQ6, DQ5, DQ3 and DQ2 flags to check that
automatic programming/erasing is terminated and read data.
• The hardware sequence flags can also be used to check whether the second and later sector erase code
writing is enabled.
529
CHAPTER 18 512 KBIT FLASH MEMORY
● Explanation of hardware sequence flag
Table 18.5-2 lists the functions of the hardware sequence flag.
Table 18.5-2 List of Hardware Sequence Flag Functions
State
State change in
normal
operation
Abnormal
operation
DQ7
DQ6
DQ5
DQ3
DQ2
Programming --> Completed
(when program address
specified)
DQ7 -->
DATA:7
Toggle -->
DATA:6
0 -->
DATA:5
0 -->
DATA:3
1 -->
DATA:2
Chip and sector erasing
--> Completed
0 --> 1
Toggle -->
Stop
0 --> 1
1
Toggle -->
Stop
Sector erasing wait
--> Started
0
Toggle
0
0 --> 1
Toggle
Erasing --> Sector erasing
suspended
(Sector being erased)
0 --> 1
Toggle --> 1
0
1 --> 0
Toggle
Sector erasing suspended -->
Resumed
(Sector being erased)
1 --> 0
1 --> Toggle
0
0 --> 1
Toggle
Sector erasing being
suspended
(Sector not being erased)
DATA:7
DATA:6
DATA:5
DATA:3
DATA:2
Programming
DQ7
Toggle
1
0
1
Chip and sector erasing
0
Toggle
1
1
*
*: If the DQ5 flag is "1" (timing limit over), the DQ2 flag performs the toggle operation for continuous reading from the
programming/erasing sector but does not perform the toggle operation for reading from other sectors.
530
CHAPTER 18 512 KBIT FLASH MEMORY
18.5.1
Data Polling Flag (DQ7)
The data polling flag (DQ7) is mainly used to notify that the automatic algorithm is
executing or has been completed using the data polling function.
■ Data Polling Flag (DQ7)
Table 18.5-3 and Table 18.5-4 give the state transition of the data polling flag.
Table 18.5-3 State Transition of Data Polling Flag (State Change at Normal Operation)
Operating State
Programming -->
Completed
Chip and
Sector Erasing
--> Completed
DQ7
DQ7 --> DATA:7
0 --> 1
Wait for Sector
Erasing -->
Started
Sector Erasing
--> Erasing
Suspended
(Sector being
Erased)
Sector Erasing
Suspended -->
Resume
(Sector being
Erased)
Sector Erasing
being
Suspended
(Sector not
being Erased)
0
0 --> 1
1 --> 0
DATA:7
Table 18.5-4 State Transition of Data Polling Flag (State Change at Abnormal Operation)
Operating
State
DQ7
Programming
Chip and
Sector Erasing
DQ7
0
● At programming
• Read access during execution of the auto-programming algorithm causes flash memory to output the
reversed data of bit 7 last written.
• Read access at the end of the auto-programming algorithm causes flash memory to output the value of
bit 7 at the address to which read access was performed.
● At chip/sector erasing
During executing chip and sector erasing algorithms, when read access is made to the currently being
erasing sector, bit 7 of flash memory outputs 0. When chip erasing/sector erasing is terminated, bit 7 of
flash memory outputs 1.
531
CHAPTER 18 512 KBIT FLASH MEMORY
● At sector erasing suspension
• Read access during sector erasing suspension causes flash memory to output 1 if the address specified
by the address signal belongs to the sector being erased. Flash memory outputs bit 7 (DATA: 7) of the
read value at the address specified by the signal address if the address specified by the address signal
does not belong to the sector being erased.
• Referring this flag together with the toggle bit flag (DQ6) permits a decision on whether flash memory
is in the erase suspended state and which sector is being erased.
Note:
Read access to the specified address while the automatic algorithm starts is ignored. Data reading
is enabled after "1" is set to the data polling flag (DQ7). Data reading after the end of the automatic
algorithm should be performed following read access after completion of data polling has been
checked.
532
CHAPTER 18 512 KBIT FLASH MEMORY
18.5.2
Toggle Bit Flag (DQ6)
The toggle bit flag (DQ6) is a hardware sequence flag used to notify that the automatic
algorithm is being executed or in the end state using the toggle bit function.
■ Toggle Bit Flag (DQ6)
Table 18.5-5 and Table 18.5-6 give the state transition of the toggle bit flag.
Table 18.5-5 State Transition of Toggle Bit Flag (State Change at Normal Operation)
Operating State
Programming -->
Completed
Chip and
Sector Erasing
--> Erasing
Completed
DQ6
Toggle --> DATA:6
Toggle --> Stop
Wait for Sector
Erasing -->
Erasing
Started
Sector Erasing
--> Erasing
Suspended
(Sector being
Erased)
Sector Erasing
Suspended -->
Resume
(Sector being
Erased)
Sector Erasing
Suspended
(Sector not
being Erased)
Toggle
Toggle --> 1
1 --> Toggle
DATA:6
Table 18.5-6 State Transition of Toggle Bit Flag (State Change at Abnormal Operation)
Operating
State
DQ6
Programming
Chip and
Sector Erasing
Toggle
Toggle
● At programming and chip/sector erasing
• If a continuous read access is made during the execution of the automatic algorithm for programming
and chip erasing/sector erasing, flash memory toggle-outputs 1 and 0 alternately every reading.
• If a continuous read access is made after the completion of the automatic algorithm for programming
and chip erasing/sector erasing, flash memory outputs bit 6 (DATA: 6) for the read value of the read
address every reading.
● At sector erasing suspension
If a read access is made in the sector erasing suspension state, flash memory outputs 1 when the read
address is the sector being erased and bit 6 (DATA: 6) for the read value of the read address when the read
address is not the sector being erased.
Reference:
If the sector for programming is reprogram-protected, the toggle bit flag (DQ6) produces a toggle
output for approximately 2 µs, and then terminates it without reprogramming data.
If all sectors for erasing are reprogram-protected, the toggle bit flag (DQ6) produces a toggle output
for approximately 100 µs, and then returns to the read/reset state without reprogramming data.
533
CHAPTER 18 512 KBIT FLASH MEMORY
18.5.3
Timing Limit Over Flag (DQ5)
The timing limit over flag (DQ5) is a hardware sequence flag that notifies flash memory
that the execution of the automatic algorithm has exceeded a prescribed time (the time
required for programming/erasing).
■ Timing Limit Over Flag (DQ5)
Table 18.5-7 and Table 18.5-8 give the state transition of the timing limit over flag.
Table 18.5-7 State Transition of Timing Limit Over Flag (State Change at Normal Operation)
Operating State
Programming -->
Completed
Chip and
Sector Erasing
--> Completed
DQ5
0 --> DATA:5
0 --> 1
Wait for Sector
Erasing -->
Started
Sector Erasing
--> Erasing
Suspended
(Sector being
Erased)
Sector Erasing
Suspended -->
Resume
(Sector being
Erased)
Sector Erasing
being
Suspended
(Sector not
being Erased)
0
0
0
DATA:5
Table 18.5-8 State Transition of Timing Limit Over Flag (State Change at Abnormal Operation)
Operating
State
DQ5
Programming
Chip and
Sector Erasing
1
1
● At programming and chip erasing/sector erasing
• If a read access made after starting the automatic algorithm for programming or chip erasing/sector
erasing is within a prescribed time (the time required for programming/erasing), the timing limit over
flag (DQ5) outputs 0. If it exceeds the prescribed time, the timing limit over flag (DQ5) outputs 1.
• The timing limit over flag (DQ5) can be used to identify the success or failure of programming/erasing,
regardless of whether the automatic algorithm is in progress or terminated. If the automatic algorithm
by the data polling or the toggle bit function is in execution when the timing limit over flag (DQ5)
outputs 1, programming can be identified as a failure.
• For example, when "1" is set to the flash memory address with 1 set the flash memory, programming
fails. In this case, the flash memory will be locked and the automatic algorithm will not complete.
Therefore, no valid data is output from the data polling flag (DQ7). Also, the toggle bit flag (DQ6) does
not stop the toggle operation and exceeds the time limit, causing the timing limit over flag (DQ5) to
output 1. This state means that the flash memory is not being used correctly; it does not mean that the
flash memory is faulty. When this state occurs, execute the reset command.
534
CHAPTER 18 512 KBIT FLASH MEMORY
18.5.4
Sector Erase Timer Flag (DQ3)
The sector erase timer flag (DQ3) is a hardware sequence flag used to notify during the
period of waiting for sector erasing after the sector erase command has started.
■ Sector Erase Timer Flag (DQ3)
Table 18.5-9 and Table 18.5-10 give the state transition of the sector erase timer flag.
Table 18.5-9 State Transition of Sector Erase Timer Flag (State Change at Normal Operation)
Operating State
Programming -->
Completed
Chip and
Sector Erasing
--> Completed
DQ3
0 --> DATA:3
1
Wait for Sector
Erasing -->
Started
Sector Erasing
--> Erasing
Suspended
(Sector being
Erased)
Sector Erasing
Suspended -->
Resume
(Sector being
Erased)
Sector Erasing
being
Suspended
(Sector not
being Erased)
0 --> 1
1 --> 0
0 --> 1
DATA:3
Table 18.5-10 State Transition of Sector Erase Timer Flag (State Change at Abnormal Operation)
Operating
State
DQ3
Programming
Chip and
Sector Erasing
0
1
● At sector erasing
• If a read access made after starting the sector erase command is within a sector erasing wait period, the
sector erasing timer flag (DQ3) outputs 0. If it exceeds the period, the sector erasing timer flag (DQ3)
outputs 1.
• If the sector erasing timer flag (DQ3) is "1", indicating that the automatic algorithm for sector erasing by
the data polling or toggle bit function is in progress (DQ = 0; DQ6 produces a toggle output), sector
erasing is performed. If any command other than the sector erasing suspension is set, it is ignored until
sector erasing is terminated.
• If the sector erasing timer flag (DQ3) is "0", flash memory can accept the sector erase command. To
program the sector erase command, check that the sector erasing timer flag (DQ3) is "0". If the flag is
"1", flash memory may not accept the sector erase command of suspending.
● At sector erasing suspension
Read access during sector erasing suspension causes flash memory to output 1, if the read address is the
sector being erased. Flash memory outputs bit 3 (DATA: 3) for the read value of the read address when
the read address is not the sector being erased.
535
CHAPTER 18 512 KBIT FLASH MEMORY
18.5.5
Toggle Bit 2 Flag (DQ2)
The toggle bit 2 flag (DQ2) is a hardware sequence flag that notifies flash memory that
sector erasing is being suspended using the toggle bit function.
■ Toggle Bit Flag (DQ2)
Table 18.5-11 and Table 18.5-12 give the state transition of the toggle bit flag.
Table 18.5-11 State Transition of Toggle Bit Flag (State Change at Normal Operation)
Operating State
Programming -->
Completed
Chip and
Sector Erasing
--> Completed
DQ2
1 --> DATA:2
Toggle --> Stop
Wait for Sector
Erasing
--> Started
Sector Erasing
--> Erasing
Suspended
(Sector being
Erased)
Sector Erasing
Suspended -->
Resume Sector
being Erased)
Sector Erasing
being
Suspended
(Sector not
being Erased)
Toggle
Toggle
Toggle
DATA:2
Table 18.5-12 State Transition of Toggle Bit Flag (State Change at Abnormal Operation)
Operating
State
DQ2
Programming
1
Chip and
Sector
Erasing
*
*: If the DQ5 flag is "1" (timing limit over), the DQ2 flag performs the toggle operation
for continuous reading from the programming/erasing sector but does not perform
the toggle operation for reading from other sectors.
● At sector erasing
• If a continuous read access is made during the execution of the automatic algorithm for chip erasing/
sector erasing, flash memory toggle-outputs 1 and 0 alternately every reading.
• If a continuous read access is made after the completion of the algorithm for chip erasing/sector erasing,
flash memory outputs bit 2 (DATA: 2) for the read value of the read address every reading.
536
CHAPTER 18 512 KBIT FLASH MEMORY
● At sector erasing suspension
• If a read access is made in the sector erasing suspension state, flash memory outputs 1 and 0 alternately
when the read address is the sector being erased and bit 2 (DATA: 2) for the read value of the read
address when the read address is not the sector being erased.
• If programming is performed in the sector erasing suspension state, flash memory outputs 1 when a
continuous read access is started with the sector that is not in the erasing suspension state.
• The toggle bit 2 flag (DQ2) is used together with the toggle bit flag (DQ6) to detect that sector erasing is
suspended (the DQ2 flag performs the toggle operation but the DQ6 flag does not).
• If a read access from the sector being erased is made, the toggle bit 2 flag (DQ2) performs the toggle
operation, so it can also be used to detect the sector being erased.
Reference:
If all sectors for erasing are reprogram-protected, the toggle bit flag (DQ2) produces a toggle output
for approximately 100 µs, and then returns to the read/reset state without reprogramming data.
537
CHAPTER 18 512 KBIT FLASH MEMORY
18.6
Details of Programming/Erasing Flash Memory
This section explains the procedure for inputting commands starting the automatic
algorithm, and for read/reset of flash memory, programming, chip erasing, sector
erasing, sector erasing suspension and sector erasing resumption.
■ Detailed Explanation of Programming and Erasing Flash Memory
Automatic algorithm can be started by programming the command sequence of read/reset, programming,
chip erasing, sector erasing, sector erasing suspension and erasing resumption from CPU to flash memory.
Programming flash memory from the CPU should always be performed continuously. The termination of
the automatic algorithm can be checked by the data polling function. After normal termination, it returns to
the read/reset state.
Each operation is explained in the following order.
• Read/reset state
• Data programming
• All data erasing (chip all erase)
• Any data erasing (sector erase)
• Sector erasing suspension
• Sector erasing resumption
538
CHAPTER 18 512 KBIT FLASH MEMORY
18.6.1
Read/Reset State in Flash Memory
This section explains the procedure for inputting the read/reset command to place flash
memory in the read/reset state.
■ Read/Reset State in Flash Memory
• Flash memory can be placed in the read/reset state by continuously transmitting the read/reset command
in the command sequence table from CPU to flash memory.
• There are two kinds of read/reset commands: one is executed at one time bus operation, and the other is
executed at three times bus operations; the command sequence of both is essentially the same.
• Since the read/reset state is the initial state for flash memory, flash memory always enters this state after
power-on and at the normal termination of command. The read/reset state is also described as the wait
state for command input.
• In the read/reset state, a read access to flash memory enables data to be read. As is the case with mask
ROM, a program access from the CPU can be made. A read access to flash memory does not require
the read/reset command. If the command is not terminated normally, use the read/reset command to
initialize the automatic algorithm.
539
CHAPTER 18 512 KBIT FLASH MEMORY
18.6.2
Data Programming to Flash Memory
This section explains the procedure for inputting the program command to program
data to flash memory.
■ Data Programming to Flash Memory
• In order to start the data programming automatic algorithm, continuously transmit the program
command in the command sequence table from CPU to flash memory.
• At completion of data programming to a target address in the fourth cycle, the automatic algorithm starts
automatic programming.
● How to specify address
• The only even addresses can be specified for the programming address specified by programming data
cycle. Specifying odd addresses prevents correct writing. Writing to even addresses must be performed
in word data units.
• Programming is possible in any address order or even beyond sector boundaries. However, execution of
one programming command, permits programming of only one word for data.
● Notes on data programming
• Data 0 cannot be returned to data 1 by programming. When data 0 is programmed to data 1, the data
polling algorithm (DQ7) or toggling (DQ6) is not terminated and the flash memory is considered faulty;
the timing limit over flag (DQ5) is determined as an error.
• When data is read in the read/reset state, the bit data remains 0. To return the bit data to "1" from "0",
erase flash memory data.
• All commands are ignored during automatic programming. If a hardware reset occurs during
programming, data being programmed to addresses are not assured.
■ Data Programming Procedure
• Figure 18.6-1 gives an example of the procedure for programming data into flash memory. The
hardware sequence flags can be used to check the operating state of the automatic algorithm in flash
memory. The data polling flag (DQ7) is used for checking the completion of programming to flash
memory in this example.
• Flag check data should be read from the address where data was last written.
• Because the data polling flag (DQ7) and the timing limit over flag (DQ5) change at the same time, the
data polling flag (DQ7) must be checked even when the timing limit over flag (DQ5) is "1".
• Similarly, since the toggle bit flag (DQ6) stops toggling at the same time the timing limit over flag
(DQ5) changes to "1", toggle bit flag (DQ6) must be checked.
540
CHAPTER 18 512 KBIT FLASH MEMORY
Figure 18.6-1 Example of Procedure of Data Programming to Flash Memory
Start
FMCS : WE (bit 5)
Programming enabled
Program command sequence
(1) FFAAAA ← XXAA
(2) FF5554 ← XX55
(3) FFAAAA ← XXA0
(4) Program address ← Program data
Internal address read
Data polling
(DQ7)
Next address
Data
Data
0
Timing limit
(DQ5)
1
Internal address read
Data
Data polling
(DQ7)
Data
Programming error
Last address
NO
YES
FMCS : WE (bit 5)
Programming enabled
Completed
Check by hardware
sequence flag
541
CHAPTER 18 512 KBIT FLASH MEMORY
18.6.3
Data Erase from Flash Memory (Chip Erase)
This section explains the procedure for inputting the chip erase command to erase all
data from flash memory.
■ All Data Erase from Flash Memory (Chip Erase)
• All data can be erased from flash memory by continuously transmitting the chip erase command in the
command sequence table from CPU to flash memory.
• The chip erase command is executed in six bus operations. Chip erasing is started at completion of the
sixth programming cycle.
• Before chip erasing, the user need not perform programming to flash memory. During execution of the
automatic erasing algorithm, flash memory automatically programs 0 before erasing all cells.
542
CHAPTER 18 512 KBIT FLASH MEMORY
18.6.4
Erasing Any Data in Flash Memory (Sector Erasing)
This section explains the procedure for inputting the sector erase command to erase
any data in flash memory. Sector-by-sector erasing is enabled and multiple sectors can
be specified at a time.
■ Erasing Any Data in Flash Memory (Sector Erasing)
Any sector in flash memory can be erased by continuously transmitting the sector erase command in the
command sequence table from CPU to flash memory.
● How to specify sector
• The sector erase command is executed in six bus operations. By setting the address on the sixth cycle in
the even address in the target sector and programming the sector erase code (30H) to data, a 50 μs sector
erasing wait is started
• When erasing more than one sector, the sector erase code (30H) is programmed to the sector address to
be erased, following the above.
● Notes on specifying multiple sectors
• Sector erasing is started after a 50 μs period waiting for sector erasing is completed after the last sector
erase code has been programmed.
• That is, when erasing more than one sector simultaneously, the address of erase sector and the sector
erase code must be input within 50 μs. If the sector erase code is input 50 μs or later, it cannot be
accepted.
• Whether continuous programming of the sector erase code is enabled can be checked by the sector erase
timer flag (DQ3).
• In this case, the address from which the sector erase timer is flag (DQ3) read should correspond to the
sector to be erased.
■ Erasing Procedure for Flash Memory Sectors
• The state of the automatic algorithm in the flash memory can be determined using the hardware
sequence flag. Figure 18.6-2 gives an example of the flash memory sector erase procedure. In this
example, the toggle bit flag (DQ6) is used to check that erase ends.
• DQ6 terminates toggling concurrently with the change of the timing limit over flag (DQ5) to "1", so the
DQ6 must be checked even when DQ5 is "1".
• Similarly, the data polling flag (DQ7) changes concurrently with the transition of the DQ5, so DQ7
must be checked.
543
CHAPTER 18 512 KBIT FLASH MEMORY
Figure 18.6-2 Example of Sector Erasing Procedure
Start
FMCS : WE (bit 5)
Erasing enabled
Erase command sequence
(1) FFAAAA ← XXAA
(2) FF5554 ← XX55
(3) FFAAAA ← XX80
(4) FFAAAA ← XXAA
(5) FF5554 ← XX55
(6) Code input to erase sector (30H)
YES
Is any other
erase sector?
NO
Internal address read 1
Internal address read 2
Next sector
NO
YES
Sector Erase
Completed?
Toggle bit (DQ6)
Data 1 = Data 2
YES
NO
0
Timing limit
(DQ5)
1
Internal address read
Internal address read
NO
Toggle bit (DQ6)
Data 1 = Data 2
YES
Erasing error
Last sector
YES
FMCS : WE (bit 5)
Erasing enabled
Check by hardware
sequence flag
544
Completed
NO
CHAPTER 18 512 KBIT FLASH MEMORY
18.6.5
Sector Erase Suspension in Flash Memory
This section explains the procedure for inputting the sector erase suspend command to
suspend sector erasing. Data can be read from the sector not being erased.
■ Sector Erase Suspension in Flash Memory
• To cause flash memory sector erasing to suspend, transmit the sector erasing suspend command in the
command sequence table from CPU to flash memory.
• The sector erasing suspend command suspends the sector erase currently being performed, enabling data
read from a sector that is currently not being erased. Only read can be performed when this command is
suspended; programming cannot be performed.
• This command is only enabled during the sector erasing period including the erasing wait time; it is
ignored during the chip erasing period or during programming.
• The sector erasing suspend command is executed when the sector erasing suspend code (B0H) is
programmed. Arbitrary address in flash memory should be set for address. If the sector erasing suspend
command is executed during sector erasing pause, the command input again is ignored.
• When the sector erasing suspend command is input during the sector erasing wait period, the sector
erase wait state ends immediately, the erasing is interrupted, and the erase stop state occurs.
• When the erase suspend command is input during the sector erasing after the sector erase wait period,
the erase suspend state occurs after 20 μs max. The sector erase suspend command is performed after
20μs following the issuance of the sector erase command or sector erase resume command.
545
CHAPTER 18 512 KBIT FLASH MEMORY
18.6.6
Sector Erase Resumption in Flash Memory
This section explains the procedure for inputting the sector erase resume command to
resume erasing of the suspended flash memory sector.
■ Erase Resumption in Flash Memory
• To re-start sector erasing, transmit the sector erase resume command in the command sequence table
from CPU to flash memory.
• The sector erase resume command resumes sector erasing suspended by the sector erase suspend
command. This command is executed by writing the erase resume code (30H). In this case, any address
in the flash memory area is specified.
• Inputting the sector erase resume command during sector erasing is ignored.
546
CHAPTER 18 512 KBIT FLASH MEMORY
18.7
Program Example of 512 Kbit Flash Memory
A program example of the 512 Kbit flash memory is given below.
■ Program Example of 512 Kbit Flash Memory
NAME
FLASHWE
TITLE
FLASHWE
;-------------------------------------------------------------------------------; 512 Kbit FLASH Sample Program
; 1: Transfer program in FLASH (address FFBC00 H,
;
sector SA2) to RAM (address 000700H).
; 2: Execute program on RAM.
; 3: Program PDR1 value to FLASH (address FF0000H, sector SA0).
; 4: Read programmed value (address FF0000H, sector SA0) and output to PDR2.
; 5: Erase programmed sector (SA0).
; 6: Output check that data is erased.
; Conditions
;
- Count of bytes transferred to RAM: 100H (256 bytes)
;
- Completion of programming and erasing checked by:
;
Timing limit over flag (DQ5)
;
Toggle bit flag (DQ6)
;
RDY (FMCS)
;
- Action taken at error
;
Output H to P00 to P07.
;
Issue reset command.
;-------------------------------------------------------------------------------;
RESOUS IOSEG ABS=00
; Definition of "RESOUS" I/O segment
ORG
0000H
PDR0
RB
1
PDR1
RB
1
PDR2
RB
1
PDR3
RB
1
ORG
0010H
DDR0
RB
1
DDR1
RB
1
DDR2
RB
1
DDR3
RB
1
ORG
00A1H
CKSCR
RB
1
ORG
00AEH
FMCS
RB
1
ORG
006FH
ROMM
RB
1
RESOUS ENDS
;
547
CHAPTER 18 512 KBIT FLASH MEMORY
SSTA
STA_T
SSTA
;
DATA
SSEG
RW
RW
ENDS
0127H
1
DSEG ABS=0FFH
; FLASH command address
ORG
5554H
COMADR2 ORG
1
ORG
0AAAAH
COMADR1 ORG
1
DATA
ENDS
;-------------------------------------------------------------------------------; Main program (SA1)
;-------------------------------------------------------------------------------CODE
CSEG
START:
;-----------------------------------------------------------------------; Initialize
;-----------------------------------------------------------------------MOV
CKSCR,#0BAH
; Set to 3-multiplying count
MOV
RP,#0
MOV
A,#!STA_T
MOV
SSB,A
MOVW A,#STA_T
MOVW SP, A
MOV
ROMM,#00H
; Mirror OFF
MOV
PDRO,#00H
; For error check
MOV
DDR0,#0FFH
MOV
PDR1,#00H
; Data input port
MOV
DDR1,#00H
MOV
PDR2,#00H
; Data output port
MOV
DDR2,#0FFH
;-----------------------------------------------------------------------; Transfer FLASH programming/erasing program (FFBC00H) to RAM
; (address 700H)
;-----------------------------------------------------------------------MOVW A,#0700H
; Transfer destination RAM area
MOVW A,#0BC00H
; Transfer source address
; (position where program exist)
MOVW RW0,#100H
; Count of bytes to be transferred
MOVS ADB,PCB
; Transfer 100H from FFBC00H to 000700H
CALLP 000700H
; Jump to address where transferred program exists
OUT
END
CODE
548
;-----------------------------------------------------------------------; Data output
;-----------------------------------------------------------------------MOV
A,#0FFH
MOV
ADB,A
MOVW RW2,#0000H
MOVW A,@RW2+00
MOV
PDR2,A
JMP
*
ENDS
CHAPTER 18 512 KBIT FLASH MEMORY
;-------------------------------------------------------------------------------Flash programming/erasing program (SA2)
;-------------------------------------------------------------------------------RAMPRG CSEG ABS=0FFH
ORG
0BC00H
;-----------------------------------------------------------------------; Initialize
;-----------------------------------------------------------------------MOVW RW0,#0500H
; RW0: RAM space for storage of input data
; 00:0500 to
MOVW RW2,#0000H
; RW2: Flash memory programming address
; FD:0000 to
MOV
A,#00H
; DTB change
MOV
DTB,A
; Specify bank for @RW0
MOV
A,#0FFH
; ADB change 1
MOV
ADB,A
; Specify bank for program mode specifying address
MOV
PDR3,#00H
; Initialize switch
MOV
DDR3,#00H
;
WAIT1
BBC
PDR3:0,WAIT1
; PDR3: 0 with High level, start programming
;
;-------------------------------------------------------------------------------; Program (SA0)
;-------------------------------------------------------------------------------MOV
A,PDR1
MOVW @RW0+00,A
; Save PDR1 data in RAM.
MOV
FMCS,#20H
; Set program mode.
MOVW ADB:COMADR1, #00AAH
; Flash program command 1
MOVW ADB:COMADR2, #0055H
; Flash program command 2
MOVW ADB:COMADR1, #00A0H
; Flash program command 3
;
MOVW A, @RW0+00
; Program input data (RW0) to flash memory (RW2).
;
MOVW @RW2+00, A
WRITE
; Waiting time check
;-----------------------------------------------------------------------;ERROR occurs when the time limit over check flag is set and toggling.
;-----------------------------------------------------------------------MOVW A,@RW2+00
AND
A,#20H
; DQ5 time limit check
BZ
NTOW
; Time limit over
MOVW A,@RW2+00
; AH
MOVW A,@RW2+00
; AL
XORW A
; XOR of AH and AL (1 if value is invalid)
AND
A,#40H
; Is DQ6 toggle bit?
BNZ
ERROR
; If no, go to ERROR.
;-----------------------------------------------------------------------;Programming end check (FMCS-RDY)
;-----------------------------------------------------------------------NTOW
MOVW A,FMCS
AND
A,#10H
; Extract RDY bit (bit 4) of FMCS.
BZ
WRITE
; Is programming ended?
MOV
FMCS,#00H
; Cancel program mode.
549
CHAPTER 18 512 KBIT FLASH MEMORY
;-----------------------------------------------------------------------;Program data output
;-----------------------------------------------------------------------MOVW RW2,#0000H
; Output program data
MOVW A, @RW2+00
MOV
PDR2,A
;
WAIT2
BBC
PDR3:1,WAIT2
; PDR3:1 With "H", start sector erasing.
;
;-------------------------------------------------------------------------------; Sector erasing (SA0)
;-------------------------------------------------------------------------------MOV
@RW2+00,#0000H
; Initialize address
MOV
FMCS,#20H
; Set erase mode
MOVW ADB:COMADR1,#00AAH ; Flash command 1
MOVW ADB:COMADR2,#0055H ; Flash command 2
MOVW ADB:COMADR1,#0080H ; Flash command 3
MOVW ADB:COMADR1,#00AAH ; Flash command 4
MOVW ADB:COMADR2,#0055H ; Flash command 5
MOV
@RW2+00,#0030H
; Issue erase command to sector to be erased 6.
ELS
; Waiting time check
;-----------------------------------------------------------------------;ERROR occurs when time limit over check flag is set and toggling is underway.
;-------------------------------------------------------------------------------MOVW A,@RW2+00
AND
A,#20H
; DQ5 time limit check
BZ
NOTE
; Time limit over
MOVW A,@RW2+00
; During AH programming, "H/L" is output
MOVW A,@RW2+00
; alternately every time AL is read from DQ6
XORW A
; XOR of AH and AL (1 if DQ6 value invalid,
; indicating programming underway)
AND
A, #40H
; Is DQ6 toggle bit "H"?
BNZ
ERROR
; If "H", go to ERROR
;-----------------------------------------------------------------------;Erasing end check (FMCS-RDY)
;-----------------------------------------------------------------------NTOE
MOVW A,FMCS
;
AND
A,#10H
; Extract RDY bit (bit 4) of FMCS
BZ
ELS
; Is erasing ended?
MOV
FMCS,#00H
; Cancel FLASH erase mode
RETP
; Return to main program
;-------------------------------------------------------------------------------;Error
;-------------------------------------------------------------------------------ERROR
MOV
ADB:COMADR1,#0F0H ; Reset command (read enabled)
MOV
FMCS,#00H
; Cancel FLASH mode
MOV
PDR0,#0FFH
; Check error processing
RETP
; Return to main program
RAMPRG ENDS
;------------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG
0FFDCH
DSL
START
DB
00H
VECT
ENDS
;
ENDS START
550
CHAPTER 19
FLASH SERIAL
PROGRAMMING
CONNECTION
This chapter describes an example of serial
programming connection using the flash microcontroller
programmer made by Yokogawa Digital Computer
Corporation.
19.1 Basic Configuration of Serial Programming Connection for
F2MC-16LX MB90F387/S
19.2 Connection Example in Single-chip Mode (User Power Supply)
19.3 Connection Example in Single-chip Mode (Writer Power Supply)
19.4 Example of Minimum Connection to Flash Microcontroller
Programmer (User Power Supply)
19.5 Example of Minimum Connection to Flash Microcontroller
Programmer (Writer Power Supply)
551
CHAPTER 19 FLASH SERIAL PROGRAMMING CONNECTION
19.1
Basic Configuration of Serial Programming Connection for
F2MC-16LX MB90F387/S
The MB90F387/S supports the serial on-board programming of flash ROM (Fujitsu
standard). The specification for serial on-board programming are explained below.
■ Basic Configuration of Serial Programming Connection for MB90F387/S
The flash microcontroller programmer made by Yokogawa Digital Computer Corporation is used for
Fujitsu standard serial on-board programming. Either of the program that operates on the single chip mode
or the internal ROM external bus mode can be written.
Figure 19.1-1 Basic Configuration of Serial Programming Connection
Host interface cable (AZ221)
General-purpose common cable
(AZ210)
RS232C
Flash
microcontroller
programmer
+
memory card
Clock synchronous serial MB90F387(S)
user system
Stand-alone operation enable
Note:
Inquire of Yokogawa Digital Computer Corporation for details about the functions and operations of
the AF220/AF210/AF120/AF110 flash microcontroller programmer, general-purpose common cable
for connection (AZ210), and connectors
Table 19.1-1 Pins Used for Fujitsu Standard Serial On-board Programming (1/2)
Pin
MD2, MD1,
MD0
X0, X1
552
Function
Supplementary Information
Mode pins
Writing 1 to MD2, MD1 and 0 to MD0 sets the flash serial program mode.
Oscillation pins
In the flash serial program mode, the internal operating clock of the CPU has
a frequency one time that of the PLL clock, so the internal operating clock
frequency is the same as the oscillation clock frequency. Since the
oscillation clock frequency serves as an internal operation clock, the
oscillator used for serial programming have frequencies from 1 MHz to 16
MHz.
CHAPTER 19 FLASH SERIAL PROGRAMMING CONNECTION
Table 19.1-1 Pins Used for Fujitsu Standard Serial On-board Programming (2/2)
Pin
Function
Supplementary Information
P30, P31
Programming program
start pins
SIN1
Serial data input pin
SOT1
Serial data output pin
SCK1
Serial clock input pin
C
C pin
This pin is a capacitance pin for stabilizing voltage. Connect the ceramic
capacitor approx. 0.1 μF externally.
VCC
Power supply voltage pin
Program voltage (5 V±10%)
VSS
GND pin
GND pin is common to the ground of the flash microcontroller programmer.
Input a "L" level to P30 and a "H" level to P31.
UART is used in clock synchronous mode.
Note:
Even if the P30, SIN1, SOT1, and SCK1 pins are used for the user system, the controller shown in
the figure below is required. The TICS signal of the flash microcontroller programmer can be used to
disconnect the user circuit during serial programming.
See the following serial programming connection examples given in Sections "19.2 Connection
Example in Single-chip Mode (User Power Supply)" to "19.5 Example of Minimum Connection to
Flash Microcontroller Programmer (Writer Power Supply)".
• Connection example in single-chip mode (user power supply)
• Connection example in single-chip mode (writer power supply)
• Example of minimum connection with flash microcontroller programmer (user power supply)
• Example of minimum connection with flash microcontroller programmer (writer power supply)
Figure 19.1-2 Control circuit
AF220/AF210/AF120/AF110
programming control pin
MB90F387(S)
programming control pin
AF220/AF210/AF120/AF110
/TICS pin
User circuit
553
CHAPTER 19 FLASH SERIAL PROGRAMMING CONNECTION
■ Oscillation Clock Frequency and Serial Clock Input Frequency
The inputable serial clock frequency for the MB90F387/S can be determined by the following expression.
Therefore, change the serial clock input frequency according to the setting of the programmer of the flash
microcontroller on the basis of the oscillation clock frequency.
Inputable serial clock frequency = 0.125 × oscillation clock frequency
Table 19.1-2 Maximum Serial Clock Frequency
Oscillation
Clock
Frequency
Maximum serial clock
frequency that can be
input for the
microcomputer
Maximum serial clock
frequency that can be set
with AF220/AF210/
AF120/AF110
Maximum serial clock
frequency that can be set
with AF200
4 MHz
500 kHz
500 kHz
500 kHz
8 MHz
1 MHz
850 kHz
500 kHz
16 MHz
2 MHz
1.25 MHz
500 kHz
■ Flash Microcontroller Programmer System Configuration
(Made by Yokogawa Digital Computer Corporation)
Table 19.1-3 Flash Microcontroller Programmer System Configuration (Made by Yokogawa Digital
Computer Corporation)
Model
Function
AF220/AC4P
Model with internal Ethernet interface/
100 V to 220 V power adapter
AF210/AC4P
Standard model/
100 V to 220 V power adapter
AF120/AC4P
Single key internal Ethernet interface model/
100 V to 220 V power adapter
AF110/AC4P
Single key model/
100 V to 220 V power adapter
Unit
AZ221
PC/AT RS232C cable for writer
AZ210
Standard target probe (a) length: 1 m
FF201
Control module for Fujitsu F2MC-16LX flash microcontroller
/P2
2MB PC Card (Option) FLASH memory corresponding Max. 128 KB
/P4
4MB PC Card (Option) FLASH memory corresponding Max. 512 KB
Note:
The AF200 flash microcontroller programmer is an end product but is made available using the
control module FF201. Examples of serial programming connections can correspond to those in the
next section.
554
CHAPTER 19 FLASH SERIAL PROGRAMMING CONNECTION
19.2
Connection Example in Single-chip Mode
(User Power Supply)
When "1" is input to the mode pin MD2 of the user system placed in single-chip mode
and 0 to the mode pin MD0 from the TAUX and TMODE pins of the AF220/AF210/AF120/
AF110, the system enters the flash memory serial programming mode. A connection
example using the user power supply is given below.
■ Connection Example in Single-chip Mode (User Power Supply Used)
Figure 19.2-1 Example of Serial Programming Connection for MB90F387/S (User Power Supply Used)
AF220/AF210/AF120/AF110
flash microcontroller
programmer
User system
Connector
DX10-28S
TAUX3
MB90F387/S
(19)
MD2
MD1
TMODE
(12)
MD0
X0
1MHz to 16MHz
X1
TAUX
(23)
/TICS
(10)
P30
User circuit
/TRES
RST
(5)
User circuit
P31
C
TTXD
TRXD
TCK
(13)
(27)
(6)
SIN1
SOT1
SCK1
TVcc
(2)
Vcc
GND
(7, 8,
14, 15,
21, 22,
1, 28)
User power supply
Vss
14 pin
Pins 3, 4, 9, 11, 16, 17, 18, 20, 24, 25 and 26 are OPEN
DX10-28S: Right-angle type
1 pin
DX10-28S
28 pin
15 pin
Connector (made by Hirose Electric Co., Ltd.) pin assignment
555
CHAPTER 19 FLASH SERIAL PROGRAMMING CONNECTION
Notes:
• Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the controller shown in
Figure 19.2-2 is required in the same as P30. The /TICS signal of the flash microcontroller
programmer can be used to disconnect the user circuit during serial programming.
• Connect the AF220/AF210/AF120/AF110 while the user power is off.
Figure 19.2-2 Control circuit
AF220/AF210/AF120/AF110
programming control pin
MB90F387/S
programming control pin
AF220/AF210/AF120/AF110
/TICS pin
User circuit
556
CHAPTER 19 FLASH SERIAL PROGRAMMING CONNECTION
19.3
Connection Example in Single-chip Mode
(Writer Power Supply)
When "1" is input to the mode pin MD2 of the user system placed in single-chip mode
and 0 to the mode pin MD0 from the TAUX and TMODE pins of the AF220/AF210/AF210/
AF120/AF110, the system enters the flash memory serial programming mode.
A connection example using the writer power supply is given below.
■ Connection Example in Single-chip Mode
(Power Supplied from Flash Microcontroller Programmer)
Figure 19.3-1 Example of Serial Programming Connection for MB90F387/S
(Power Supplied from Flash Microcontroller Programmer)
AF220/AF210/AF120/AF110
flash microcontroller
programmer
Usersystem
Connector
DX10-28S
TAUX3
MB90F387/S
MD2
(19)
MD1
TMODE
MD0
X0
(12)
1MHz to 16MHz
X1
TAUX
(23)
/TICS
(10)
P30
User circuit
/TRES
RST
(5)
User circuit
TTXD
TRXD
TCK
TVcc
Vcc
TVPP1
GND
SIN1
SOT1
SCK1
(13)
(27)
(6)
(2)
(3)
(16)
Vcc
(7, 8,
14, 15,
21, 22,
1, 28)
User power supply
14 pin
Pins 4, 9, 11, 17, 18, 20, 24, 25 and 26 are OPEN
DX10-28S: Right-angle type
P31
C
Vss
1 pin
DX10-28S
28 pin
15 pin
Connector (made by Hirose Electric Co., Ltd.) pin assignment
557
CHAPTER 19 FLASH SERIAL PROGRAMMING CONNECTION
Notes:
• Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the controller shown in
Figure 19.3-2 is required in the same as P30 (Figure 19.3-2). The /TICS signal of the flash
microcontroller programmer can be used to disconnect the user circuit during serial programming
• Connect the AF220/AF210/AF120/AF110 while the user power is off.
• When supplying programming power from AF220/AF210/AF120/AF110, do not short-circuit the
programming power and user power.
Figure 19.3-2 Control circuit
AF220/AF210/AF120/AF110
programming control pin
MB90F387/S
programming control pin
AF220/AF210/AF120/AF110
/TICS pin
User circuit
558
CHAPTER 19 FLASH SERIAL PROGRAMMING CONNECTION
19.4
Example of Minimum Connection to Flash Microcontroller
Programmer (User Power Supply)
When each pin is set as shown below at programming to flash memory, there is no
need for connections between MD2, MD0, P30 and the flash microcontroller
programmer.
■ Example of Minimum Connection to Flash Microcontroller Programmer
(User Power Supply Used)
Figure 19.4-1 Example of Minimum Connection to the Flash Microcontroller Programmer
(User Power Supply Used)
AF220/AF210/AF120/AF110
flash microcontroller
programmer
User system
1 for serial programming
10 kΩ
MB90F387/S
MD2
1 for serial programming
10 kΩ
10 kΩ
MD1
10 kΩ
10 kΩ
MD0
0 for serial programming
10 kΩ
X0
1MHz to 16MHz
X1
10 kΩ
P30
0 for serial programming
User circuit
1 for serial programming
10 kΩ
P31
User circuit
C
Connector
DX10-28S
0.1 μF
10 kΩ
/TRES
(5)
RST
TTXD
(13)
SIN1
TRXD
(27)
SOT1
TCK
(6)
SCK1
TVcc
(2)
GND
(7, 8,
14, 15,
21, 22,
1,28)
Vcc
User power supply
Vss
14 pin
Pins 3, 4, 9, 10, 11, 12, 16, 17, 18, 19, 20, 23, 24, 25
and 26 are OPEN
DX10-28S: Right-angle type
1 pin
DX10-28S
28 pin
15 pin
Connector (made by Hirose Electric Co., Ltd.) pin assignment
559
CHAPTER 19 FLASH SERIAL PROGRAMMING CONNECTION
Notes:
• Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the controller shown in
Figure 19.4-2 is required. The /TICS signal of the flash microcontroller programmer can be used
to disconnect the user circuit during serial programming.
• Connect the AF220/AF210/AF120/AF110 while the user power is off.
Figure 19.4-2 Control circuit
AF220/AF210/AF120/AF110
programming control pin
MB90F387/S
programming control pin
AF220/AF210/AF120/AF110
/TICS pin
User circuit
560
CHAPTER 19 FLASH SERIAL PROGRAMMING CONNECTION
19.5
Example of Minimum Connection to Flash Microcontroller
Programmer (Writer Power Supply)
When each pin is set as shown below at programming to flash memory, there is no
need for connections between MD2, MD0, P30 and the flash microcontroller
programmer.
■ Example of Minimum Connection to Flash Microcontroller Programmer
(Power Supplied from Flash Microcontroller Programmer)
Figure 19.5-1 Example of Minimum Connection to the Flash Microcontroller Programmer
(Power Supplied from Flash Microcontroller Programmer)
AF220/AF210/AF120/AF110
flash microcontroller
programmer
User system
1 for serial programming
10 kΩ
MB90F387/S
MD2
1 for serial programming
10 kΩ
10 kΩ
MD1
10 kΩ
10 kΩ
MD0
0 for serial programming
10 kΩ
X0
1MHz to 16MHz
X1
10 kΩ
P30
0 for serial programming
User circuit
1 for serial programming
10 kΩ
P31
User circuit
C
Connector
DX10-28S
0.1 μF
10 kΩ
/TRES
(5)
RST
TTXD
(13)
SIN1
TRXD
(27)
SOT1
TCK
(6)
(2)
(3)
(16)
SCK1
TVcc
GND
Vcc
(7, 8,
14, 15,
21,22,
1, 28)
Vss
14 pin
Pins 4, 9, 10, 11, 12, 17, 18, 19, 20, 23, 24, 25
and 26 are OPEN
DX10-28S: Right-angle type
1 pin
DX10-28S
28 pin
15 pin
Connector (made by Hirose Electric Co., Ltd.) pin assignment
561
CHAPTER 19 FLASH SERIAL PROGRAMMING CONNECTION
Notes:
• Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the controller shown in
Figure 19.5-2 is required. The /TICS signal of the flash microcontroller programmer can be used
to disconnect the user circuit during serial programming.
• Connect the AF220/AF210/AF120/AF110 while the user power is off.
• When supplying programming power from AF220/AF210/AF120/AF110, do not short-circuit the
programming power and user power.
Figure 19.5-2 Control circuit
AF220/AF210/AF120/AF110
programming control pin
MB90F387/S
programming control pin
10 kΩ
AF220/AF210/AF120/AF110
/TICS pin
User
562
APPENDIX
The appendices provide the I/O map and outline of
instructions.
APPENDIX A Instructions
APPENDIX B Register Index
APPENDIX C Pin Function Index
APPENDIX D Interrupt Vector Index
563
APPENDIX
APPENDIX A Instructions
APPENDIX A describes the instructions used by the F2MC-16LX.
A.1 Instruction Types
A.2 Addressing
A.3 Direct Addressing
A.4 Indirect Addressing
A.5 Execution Cycle Count
A.6 Effective address field
A.7 How to Read the Instruction List
A.8 F2MC-16LX Instruction List
A.9 Instruction Map
Code: CM44-00202-1E
564
APPENDIX A Instructions
A.1
Instruction Types
The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an
effective address field of each instruction or using the instruction code itself.
■ Instruction Types
The F2MC-16LX supports the following 351 types of instructions:
•
41 transfer instructions (byte)
•
38 transfer instructions (word or long word)
•
42 addition/subtraction instructions (byte, word, or long word)
•
12 increment/decrement instructions (byte, word, or long word)
•
11 comparison instructions (byte, word, or long word)
•
11 unsigned multiplication/division instructions (word or long word)
•
11 signed multiplication/division instructions (word or long word)
•
39 logic instructions (byte or word)
•
6 logic instructions (long word)
•
6 sign inversion instructions (byte or word)
•
1 normalization instruction (long word)
•
18 shift instructions (byte, word, or long word)
•
50 branch instructions
•
6 accumulator operation instructions (byte or word)
•
28 other control instructions (byte, word, or long word)
•
21 bit operation instructions
•
10 string instructions
565
APPENDIX
A.2
Addressing
With the F2MC-16LX, the address format is determined by the instruction effective
address field or the instruction code itself (implied). When the address format is
determined by the instruction code itself, specify an address in accordance with the
instruction code used. Some instructions permit the user to select several types of
addressing.
■ Addressing
The F2MC-16LX supports the following 23 types of addressing:
566
•
Immediate (#imm)
•
Register direct
•
Direct branch address (addr16)
•
Physical direct branch address (addr24)
•
I/O direct (io)
•
Abbreviated direct address (dir)
•
Direct address (addr16)
•
I/O direct bit address (io:bp)
•
Abbreviated direct bit address (dir:bp)
•
Direct bit address (addr16:bp)
•
Vector address (#vct)
•
Register indirect (@RWj j = 0 to 3)
•
Register indirect with post increment (@RWj+ j = 0 to 3)
•
Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
•
Long register indirect with displacement (@RLi + disp8 i = 0 to 3)
•
Program counter indirect with displacement (@PC + disp16)
•
Register indirect with base index (@RW0 + RW7, @RW1 + RW7)
•
Program counter relative branch address (rel)
•
Register list (rlst)
•
Accumulator indirect (@A)
•
Accumulator indirect branch address (@A)
•
Indirectly-specified branch address (@ear)
•
Indirectly-specified branch address (@eam)
APPENDIX A Instructions
■ Effective Address Field
Table A.2-1 lists the address formats specified by the effective address field.
Table A.2-1 Effective Address Field
Code
Representation
00
R0
RW0
RL0
01
R1
RW1
(RL0)
02
R2
RW2
RL1
03
R3
RW3
(RL1)
04
R4
RW4
RL2
05
R5
RW5
(RL2)
06
R6
RW6
RL3
07
R7
RW7
(RL3)
08
@RW0
09
@RW1
Address format
Default bank
Register direct: Individual parts correspond to the
byte, word, and long word types in order from the
left.
None
DTB
DTB
Register indirect
0A
@RW2
ADB
0B
@RW3
SPB
0C
@RW0+
DTB
0D
@RW1+
DTB
Register indirect with post increment
0E
@RW2+
ADB
0F
@RW3+
SPB
10
@RW0+disp8
DTB
11
@RW1+disp8
DTB
Register indirect with 8-bit displacement
12
@RW2+disp8
ADB
13
@RW3+disp8
SPB
14
@RW4+disp8
DTB
15
@RW5+disp8
DTB
Register indirect with 8-bit displacement
16
@RW6+disp8
ADB
17
@RW7+disp8
SPB
18
@RW0+disp16
DTB
19
@RW1+disp16
DTB
Register indirect with 16-bit displacement
1A
@RW2+disp16
ADB
1B
@RW3+disp16
SPB
1C
@RW0+RW7
Register indirect with index
DTB
1D
@RW1+RW7
Register indirect with index
DTB
1E
@PC+disp16
PC indirect with 16-bit displacement
PCB
1F
addr16
Direct address
DTB
567
APPENDIX
A.3
Direct Addressing
An operand value, register, or address is specified explicitly in direct addressing mode.
■ Direct Addressing
● Immediate addressing (#imm)
Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32).
Figure A.3-1 Example of Immediate Addressing (#imm)
MOVW A, #01212H (This instruction stores the operand value in A.)
Before execution
A 2233
4455
After execution
A 4455
1 2 1 2 (Some instructions transfer AL to AH.)
● Register direct addressing
Specify a register explicitly as an operand. Table A.3-1 lists the registers that can be specified. Figure A.3-2
shows an example of register direct addressing.
Table A.3-1 Direct Addressing Registers
General-purpose register
Special-purpose register
Byte
R0, R1, R2, R3, R4, R5, R6, R7
Word
RW0, RW1, RW2, RW3, RW4, RW5, RW6,
RW7
Long word
RL0, RL1, RL2, RL3
Accumulator
A, AL
Pointer
SP *
Bank
PCB, DTB, USB, SSB, ADB
Page
DPR
Control
PS, CCR, RP, ILM
*: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on
the value of the S flag bit in the condition code register (CCR). For branch instructions, the program
counter (PC) is not specified in an instruction operand but is specified implicitly.
568
APPENDIX A Instructions
Figure A.3-2 Example of Register Direct Addressing
MOV R0, A (This instruction transfers the eight low-order bits of A to the generalpurpose register R0.)
Before execution
A 0716
2534
Memory space
R0
After execution
A 0716
2564
??
Memory space
R0
34
● Direct branch addressing (addr16)
Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which
indicates the branch destination in the logical address space. Direct branch addressing is used for an
unconditional branch, subroutine call, or software interrupt instruction. Bit23 to bit16 of the address are
specified by the program counter bank register (PCB).
Figure A.3-3 Example of Direct Branch Addressing (addr16)
JMP 3B20H (This instruction causes an unconditional branch by direct branch
addressing in a bank.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
62
4F3C21H
20
4F3C22H
3B
JMP 3B20H
569
APPENDIX
● Physical direct branch addressing (addr24)
Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical
direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction.
Figure A.3-4 Example of Direct Branch Addressing (addr24)
JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit
addressing.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 3 3
Memory space
333B20H
Next instruction
4F3C20H
63
4F3C21H
20
4F3C22H
3B
4F3C23H
33
JMPP 333B20H
● I/O direct addressing (io)
Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the
physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB)
and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an
instruction using I/O direct addressing.
Figure A.3-5 Example of I/O Direct Addressing (io)
MOVW A, i : 0C0H (This instruction reads data by I/O direct addressing and stores it
in A.)
Before execution
After execution
570
A 0716
2534
A 2534 FFEE
Memory space
0000C0H
EE
0000C1H
FF
APPENDIX A Instructions
● Abbreviated direct addressing (dir)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB).
Figure A.3-6 Example of Abbreviated Direct Addressing (dir)
MOV S : 20H, A (This instruction writes the contents of the eight low-order bits of A in
abbreviated direct addressing mode.)
Before execution
A 4455
DPR 6 6
After execution
A 4455
DPR 6 6
1212
DTB 7 7
Memory space
776620H
1212
DTB 7 7
??
Memory space
776620H
12
● Direct addressing (addr16)
Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are
specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for
this mode of addressing.
Figure A.3-7 Example of Direct Addressing (addr16)
MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.)
Before execution
After execution
A 2020
A AABB
AABB
0123
DTB 5 5
Memory space
553B21H
01
553B20H
23
DTB 5 5
571
APPENDIX
● I/O direct bit addressing (io:bp)
Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp",
where the larger number indicates the most significant bit (MSB) and the lower number indicates the least
significant bit (LSB).
Figure A.3-8 Example of I/O Direct Bit Addressing (io:bp)
SETB i : 0C1H : 0 (This instruction sets bits by I/O direct bit addressing.)
Memory space
Before execution
0000C1H
00
Memory space
After execution
0000C1H
01
● Abbreviated direct bit addressing (dir:bp)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure A.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp)
SETB S : 10H : 0 (This instruction sets bits by abbreviated direct bit addressing.)
Memory space
Before execution
DTB 5 5
DPR 6 6
556610H
00
Memory space
After execution
DTB 5 5
DPR 6 6
556610H
01
● Direct bit addressing (addr16:bp)
Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure A.3-10 Example of Direct Bit Addressing (addr16:bp)
SETB 2222H : 0 (This instruction sets bits by direct bit addressing.)
Memory space
Before execution
DTB 5 5
552222H
00
Memory space
After execution
572
DTB 5 5
552222H
01
APPENDIX A Instructions
● Vector Addressing (#vct)
Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector
numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction.
Figure A.3-11 Example of Vector Addressing (#vct)
CALLV #15 (This instruction causes a branch to the address indicated by the interrupt
vector specified in an operand.)
Before execution
PC 0 0 0 0
Memory space
PCB F F
After execution
FFC000H
EF
FFFFE0H
00
FFFFE1H
D0
CALLV #15
PC D 0 0 0
PCB F F
Table A.3-2 CALLV Vector List
Instruction
Vector address L
Vector address H
CALLV #0
XXFFFEH
XXFFFFH
CALLV #1
XXFFFCH
XXFFFDH
CALLV #2
XXFFFAH
XXFFFBH
CALLV #3
XXFFF8H
XXFFF9H
CALLV #4
XXFFF6H
XXFFF7H
CALLV #5
XXFFF4H
XXFFF5H
CALLV #6
XXFFF2H
XXFFF3H
CALLV #7
XXFFF0H
XXFFF1H
CALLV #8
XXFFEEH
XXFFEFH
CALLV #9
XXFFECH
XXFFEDH
CALLV #10
XXFFEAH
XXFFEBH
CALLV #11
XXFFE8H
XXFFE9H
CALLV #12
XXFFE6H
XXFFE7H
CALLV #13
XXFFE4H
XXFFE5H
CALLV #14
XXFFE2H
XXFFE3H
CALLV #15
XXFFE0H
XXFFE1H
Note: A PCB register value is set in XX.
Note:
When the program counter bank register (PCB) is FFH, the vector area overlaps the vector area of
INT #vct8 (#0 to #7). Use vector addressing carefully (see Table A.3-2).
573
APPENDIX
A.4
Indirect Addressing
In indirect addressing mode, an address is specified indirectly by the address data of an
operand.
■ Indirect Addressing
● Register indirect addressing (@RWj j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to
23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register
(SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when
RW2 is used.
Figure A.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3)
MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores
it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 0 F
DTB 7 8
● Register indirect addressing with post increment (@RWj+ j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. After operand
operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word).
Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system
stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank
register (ADB) when RW2 is used.
If the post increment results in the address of the register that specifies the increment, the incremented
value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to
writing by an instruction and, therefore, the register that would be incremented becomes write data.
574
APPENDIX A Instructions
Figure A.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3)
MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post
increment and stores it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 1 1
DTB 7 8
● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
Memory is accessed using the address obtained by adding an offset to the contents of general-purpose
register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric
values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or
RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is
used, or additional data bank register (ADB) when RW2 or RW6 is used.
Figure A.4-3 Example of Register Indirect Addressing with Offset
(@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+10H)
RW1 D 3 0 F
After execution
DTB 7 8
Memory space
78D31FH
EE
78D320H
FF
A 2534 FFEE
RW1 D 3 0 F
DTB 7 8
575
APPENDIX
● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the
contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value.
Figure A.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3)
MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+25H)
RL2 F 3 8 2
After execution
4B02
Memory space
824B27H
EE
824B28H
FF
A 2534 FFEE
RL2 F 3 8 2
4B02
● Program counter indirect addressing with offset (@PC + disp16)
Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one
word long. Address bits 16 to 23 are specified by the program counter bank register (PCB). Note that the
operand address of each of the following instructions is not deemed to be (next instruction address +
disp16):
•
DBNZ eam, rel
•
DWBNZ eam, rel
•
CBNE eam, #imm8, rel
•
CWBNE eam, #imm16, rel
•
MOV eam, #imm8
•
MOVW eam, #imm16
Figure A.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16)
MOVW A, @PC+20H (This instruction reads data by program counter indirect
addressing with an offset and stores it in A.)
Before execution
A 0716
2534
Memory space
PCB C 5 PC 4 5 5 6
After execution
A 2534
FFEE
PCB C 5 PC 4 5 5 A
576
+4
C54556H
73
C54557H
9E
C54558H
20
C54559H
00
C5455AH
.
.
.
+20H
C5457AH
EE
C5457BH
FF
MOVW
A, @PC+20H
APPENDIX A Instructions
● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7)
Memory is accessed using the address determined by adding RW0 or RW1 to the contents of generalpurpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB).
Figure A.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7)
MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with
a base index and stores it in A.)
Before execution
A 0716
RW1 D 3 0 F
WR7 0 1 0 1
After execution
A 2534
RW1 D 3 0 F
2534
+
DTB 7 8
Memory space
78D410H
EE
78D411H
FF
FFEE
DTB 7 8
WR7 0 1 0 1
577
APPENDIX
● Program counter relative branch addressing (rel)
The address of the branch destination is a value determined by adding an 8-bit offset to the program
counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is
not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte
bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to
23 are indicated by the program counter bank register (PCB).
Figure A.4-7 Example of Program Counter Relative Branch Addressing (rel)
BRA 10H (This instruction causes an unconditional relative branch.)
Before execution
After execution
PC 3 C 2 0
PC 3 C 3 2
PCB 4 F
PCB 4 F
Memory space
4F3C32H
Next instruction
4F3C21H
10
4F3C20H
60
BRA 10H
● Register list (rlst)
Specify a register to be pushed onto or popped from a stack.
Figure A.4-8 Configuration of the Register List
MSB
LSB
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
A register is selected when the corresponding bit is 1 and deselected when the bit is 0.
578
APPENDIX A Instructions
Figure A.4-9 Example of Register List (rlist)
POPW, RW0, RW4 (This instruction transfers memory data indicated by the SP to
multiple word registers indicated by the register list.)
SP
34FA
SP
34FE
RW0
×× ××
RW0
02 01
RW1
×× ××
RW1
×× ××
RW2
×× ××
RW2
×× ××
RW3
×× ××
RW3
×× ××
RW4
×× ××
RW4
04 03
RW5
×× ××
RW5
×× ××
RW6
×× ××
RW6
×× ××
RW7
×× ××
RW7
×× ××
Memory space
SP
Memory space
01
34FAH
01
34FAH
02
34FBH
02
34FBH
03
34FCH
03
34FCH
04
34FDH
04
34FDH
34FEH
SP
Before execution
34FEH
After execution
● Accumulator indirect addressing (@A)
Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the
accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB).
Figure A.4-10 Example of Accumulator Indirect Addressing (@A)
MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.)
Before execution
A
0716
2534
DTB B B
After execution
A
0716
Memory space
BB2534H
EE
BB2535H
FF
FFEE
DTB B B
579
APPENDIX
● Accumulator indirect branch addressing (@A)
The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the
accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are
specified by the program counter bank register (PCB). For the Jump Context (JCTX) instruction, however,
address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for
unconditional branch instructions.
Figure A.4-11 Example of Accumulator Indirect Branch Addressing (@A)
JMP @A (This instruction causes an unconditional branch by accumulator indirect
branch addressing.)
Before execution
PC 3 C 2 0
A 6677
After execution
PC 3 B 2 0
A 6677
PCB 4 F
3B20
Memory space
4F3B20H
Next instruction
4F3C20H
61
JMP @A
PCB 4 F
3B20
● Indirect specification branch addressing (@ear)
The address of the branch destination is the word data at the address indicated by ear.
Figure A.4-12 Example of Indirect Specification Branch Addressing (@ear)
JMP @@RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
After execution
580
PC 3 C 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
PC 3 B 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
Memory space
217F48H
20
217F49H
3B
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
08
JMP @@RW0
APPENDIX A Instructions
● Indirect specification branch addressing (@eam)
The address of the branch destination is the word data at the address indicated by eam.
Figure A.4-13 Example of Indirect Specification Branch Addressing (@eam)
JMP @RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
PC 3 C 2 0
PCB 4 F
RW0 3 B 2 0
After execution
PC 3 B 2 0
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
00
JMP @RW0
RW0 3 B 2 0
581
APPENDIX
A.5
Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is
obtained by adding the number of cycles required for each instruction, "correction
value" determined by the condition, and the number of cycles for instruction fetch.
■ Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is obtained by adding the
number of cycles required for each instruction, "correction value" determined by the condition, and the
number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal
ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments.
Therefore, intervening in data access increases the execution cycle count.
Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the
program fetches every byte of an instruction being executed. Therefore, intervening in data access increases
the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register,
internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the
cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register.
Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add
the "access count x cycle count for the halt" as a correction value to the normal execution count.
582
APPENDIX A Instructions
■ Calculating the Execution Cycle Count
Table A.5-1 lists execution cycle counts and Table A.5-2 and Table A.5-3 summarize correction value data.
Table A.5-1 Execution Cycle Counts in Each Addressing Mode
(a) *
Code
Operand
00
|
07
Ri
Rwi
RLi
08
|
0B
Execution cycle count in
each addressing mode
Register access count in
each addressing mode
See the instruction list.
See the instruction list.
@RWj
2
1
0C
|
0F
@RWj+
4
2
10
|
17
@RWi+disp8
2
1
18
|
1B
@RWi+disp16
2
1
1C
1D
1E
1F
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
4
4
2
1
2
2
0
0
*: (a) is used for ~ (cycle count) and B (correction value) in "A.8 F2MC-16LX Instruction List".
583
APPENDIX
Table A.5-2 Cycle Count Correction Values for Counting Execution Cycles
(b) byte *
Operand
(c) word *
(d) long *
Cycle
count
Access
count
Cycle
count
Access
count
Cycle
count
Access
count
Internal register
+0
1
+0
1
+0
2
Internal memory
Even address
+0
1
+0
1
+0
2
Internal memory
Odd address
+0
1
+2
2
+4
4
External data bus
16-bit even address
+1
1
+1
1
+2
2
External data bus
16-bit odd address
+1
1
+4
2
+8
4
External data bus
8-bits
+1
1
+4
2
+8
4
*: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in "A.8 F2MC-16LX
Instruction List".
Note:
When an external data bus is used, the cycle counts during which an instruction is made to wait by
ready input or automatic ready must also be added.
Table A.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
-
+2
External data bus 16-bits
-
+3
External data bus 8-bits
+3
-
Notes:
• When an external data bus is used, the cycle counts during which an instruction is made to wait
by ready input or automatic ready must also be added.
• Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the
correction values to calculate the worst case.
584
APPENDIX A Instructions
A.6
Effective address field
Table A.6-1 shows the effective address field.
■ Effective Address Field
Table A.6-1 Effective Address Field
Code
Representation
00
01
02
03
04
05
06
07
08
09
0A
R0
R1
R2
R3
R4
R5
R6
R7
@RW0
@RW1
@RW2
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
0B
0C
0D
0E
0F
10
11
12
13
14
15
@RW3
@RW0+
@RW1+
@RW2+
@RW3+
@RW0+disp8
@RW1+disp8
@RW2+disp8
@RW3+disp8
@RW4+disp8
@RW5+disp8
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Address format
Byte count of
extended
address part *
Register direct: Individual parts correspond to
the byte, word, and long word types in order
from the left.
-
Register indirect
0
Register indirect with post increment
0
Register indirect with 8-bit displacement
1
16
@RW6+disp8
17
@RW7+disp8
18
@RW0+disp16
19
@RW1+disp16
Register indirect with 16-bit displacement
2
1A
@RW2+disp16
1B
@RW3+disp16
1C
@RW0+RW7
Register indirect with index
0
1D
@RW1+RW7
Register indirect with index
0
1E
@PC+disp16
PC indirect with 16-bit displacement
2
1F
addr16
Direct address
2
*1: Each byte count of the extended address part applies to + in the # (byte count) column in "A.8 F2MC-16LX
Instruction List".
585
APPENDIX
A.7
How to Read the Instruction List
Table A.7-1 describes the items used in "A.8 F2MC-16LX Instruction List", and Table
A.7-2 describes the symbols used in the same list.
■ Description of Instruction Presentation Items and Symbols
Table A.7-1 Description of Items in the Instruction List (1/2)
Item
Mnemonic
Uppercase, symbol: Represented as is in the assembler.
Lowercase: Rewritten in the assembler.
Number of following lowercase: Indicates bit length in the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
See Table A.2-1 for the alphabetical letters in items.
RG
B
Operation
586
Description
Indicates the number of times a register access is performed during instruction
execution.
The number is used to calculate the correction value for CPU intermittent
operation.
Indicates the correction value used to calculate the actual number of cycles during
instruction execution.
The actual number of cycles during instruction execution can be determined by
adding the value in the ~ column to this value.
Indicates the instruction operation.
LH
Indicates the special operation for bit15 to bit08 of the accumulator.
Z: Transfers 0.
X: Transfers after sign extension.
-: No transfer
AH
Indicates the special operation for the 16 high-order bits of the accumulator.
*: Transfers from AL to AH.
-: No transfer
Z: Transfers 00 to AH.
X: Transfers 00H or FFH to AH after AL sign extension.
APPENDIX A Instructions
Table A.7-1 Description of Items in the Instruction List (1/2)
Item
Description
I
Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N
(negative), Z (zero), V (overflow), C (carry).
*: Changes upon instruction execution.
-: No change
S: Set upon instruction execution.
R: Reset upon instruction execution.
S
T
N
Z
V
C
RMW
Indicates whether the instruction is a Read Modify Write instruction (reading data
from memory by the I instruction and writing the result to memory).
*: Read Modify Write instruction
-: Not Read Modify Write instruction
Note:
Cannot be used for an address that has different meanings between read and
write operations.
Table A.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
A
Explanation
The bit length used varies depending on the 32-bit accumulator instruction.
Byte: Low-order 8 bits of byte AL
Word: 16 bits of word AL
Long word: 32 bits of AL and AH
AH
16 high-order bits of A
AL
16 low-order bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
program counter bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
587
APPENDIX
Table A.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
Ri
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
Direct addressing
addr24
Physical direct addressing
ad24 0-15
Bit0 to bit15 of addr24
ad24 16-23
Bit16 to bit23 of addr24
io
I/O area (000000H to 0000FFH)
#imm4
4-bit immediate data
#imm8
8-bit immediate data
#imm16
16-bit immediate data
#imm32
32-bit immediate data
ext (imm8)
16-bit data obtained by sign extension of 8-bit immediate data
disp8
8-bit displacement
disp16
16-bit displacement
bp
588
Explanation
Bit offset
vct4
Vector number (0 to 15)
vct8
Vector number (0 to 255)
( )b
Bit address
rel
PC relative branch
ear
Effective addressing (code 00 to 07)
eam
Effective addressing (code 08 to 1F)
rlst
Register list
APPENDIX A Instructions
A.8
F2MC-16LX Instruction List
Table A.8-1 to Table A.8-18 list the instructions used by the F2MC-16LX.
■ F2MC-16LX Instruction List
Table A.8-1 41 Transfer Instructions (Byte)
Mnemonic
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
XCH
XCH
XCH
XCH
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RLi+disp8
A,#imm4
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
Ri,A
ear,A
eam,A
io,A
@RLi+disp8,A
Ri,ear
Ri,eam
ear,Ri
eam,Ri
Ri,#imm8
io,#imm8
dir,#imm8
ear,#imm8
eam,#imm8
@AL,AH
A,ear
A,eam
Ri,ear
Ri,eam
#
~
RG
B
2
3
1
2
2+
2
2
2
3
1
2
3
2
2
2+
2
2
2
2
3
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
2
2+
2
2+
3
4
2
2
3 + (a)
3
2
3
10
1
3
4
2
2
3 + (a)
3
2
3
5
10
3
4
2
2
3 + (a)
3
10
3
4 + (a)
4
5 + (a)
2
5
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
0
0
1
1
0
0
0
0
2
0
0
0
1
1
0
0
0
0
1
2
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
2
0
4
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
0
2 × (b)
0
2 × (b)
Operation
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi)+disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
Z
Z
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
Note:
See Table A.5-1 and Table A.5-2 for information on (a) and (b) in the table.
589
APPENDIX
Table A.8-2 38 Transfer Instructions (Word, Long Word)
Mnemonic
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW
XCHW
XCHW
MOVL
MOVL
MOVL
MOVL
MOVL
A,dir
A,addr16
A,SP
A,RWi
A,ear
A,eam
A,io
A,@A
A,#imm16
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
SP,A
RWi,A
ear,A
eam,A
io,A
@RWi+disp8,A
@RLi+disp8,A
RWi,ear
RWi,eam
ear,RWi
eam,RWi
RWi,#imm16
io,#imm16
ear,#imm16
eam,#imm16
@AL,AH
A,ear
A,eam
RWi, ear
RWi, eam
A,ear
A,eam
A,#imm32
ear,A
eam,A
#
~
RG
B
2
3
1
1
2
2+
2
2
3
2
3
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
2
2
2+
2
2+
2
2+
5
2
2+
3
4
1
2
2
3 + (a)
3
3
2
5
10
3
4
1
2
2
3 + (a)
3
5
10
3
4 + (a)
4
5 + (a)
2
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
4
5 + (a)
3
4
5 + (a)
0
0
0
1
1
0
0
0
0
1
2
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
0
2
0
4
2
2
0
0
2
0
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
0
(c)
0
(c)
0
(c)
0
(c)
(c)
0
2 × (c)
0
2 × (c)
0
(d)
0
0
(d)
Operation
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi)+disp8)
word (A) ← ((RLi)+disp8)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
word ((RWi)+disp8) ← (A)
word ((RLi)+disp8) ← (A)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
word (ear) ← imm16
word (eam) ← imm16
word ((A)) ← (AH)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
long (ear) ← (A)
long(eam) ← (A)
LH
AH
I
S
T
N
Z
V
C
RMW
-
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
Note:
See Table A.5-1 and Table A.5-2 for information on (a), (c), and (d) in the table.
590
APPENDIX A Instructions
Table A.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
ADDW
ADDW
ADDW
ADDW
ADDW
ADDW
ADDCW
ADDCW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBCW
SUBCW
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A,ear
A,eam
A,#imm32
A,ear
A,eam
A,#imm32
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
2+
5
2
2+
5
2
3
4+(a)
2
3
5+(a)
3
4+(a)
2
3
4+(a)
2
3
5+(a)
3
4+(a)
6
7+(a)
4
6
7+(a)
4
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
2
0
0
2
0
0
0
0
(c)
0
0
2 × (c)
0
(c)
0
0
(c)
0
0
2 × (c)
0
(c)
0
(d)
0
0
(d)
0
Operation
byte (A) ← (A) + imm8
byte (A) ← (A) + (dir)
byte (A) ← (A) + (ear)
byte (A) ← (A) + (eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear)+ (C)
byte (A) ← (A) + (eam)+ (C)
byte (A) ← (AH) + (AL) + (C)
(decimal)
byte (A) ← (A) - imm8
byte (A) ← (A) - (dir)
byte (A) ← (A) - (ear)
byte (A) ← (A) - (eam)
byte (ear) ← (ear) - (A)
byte (eam) ← (eam) - (A)
byte (A) ← (AH) - (AL) - (C)
byte (A) ← (A) - (ear) - (C)
byte (A) ← (A) - (eam) - (C)
byte (A) ← (AH) - (AL) - (C)
(decimal)
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) - (AL)
word (A) ← (A) - (ear)
word (A) ← (A) - (eam)
word (A) ← (A) - imm16
word (ear) ← (ear) - (A)
word (eam) ← (eam) - (A)
word (A) ← (A) - (ear) - (C)
word (A) ← (A) - (eam) - (C)
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
long (A) ← (A) - (ear)
long (A) ← (A) - (eam)
long (A) ← (A) - imm32
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (d) in the table.
591
APPENDIX
Table A.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
INC
ear
2
3
2
0
INC
eam
2+
5+(a)
0
2 × (b)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
byte (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
byte (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DEC
ear
2
3
2
0
byte (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
DEC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
INCW
ear
2
3
2
0
word (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
INCW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DECW
ear
2
3
2
0
DECW
eam
2+
5+(a)
0
2 × (c)
INCL
ear
2
7
4
0
INCL
eam
2+
9+(a)
0
2 × (d)
DECL
ear
2
7
4
0
DECL
eam
2+
9+(a)
0
2 × (d)
word (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
word (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (d) in the table.
Table A.8-5 11 Compare Instructions (Byte, Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
CMP
Mnemonic
A
1
1
0
0
byte (AH) - (AL)
Operation
-
-
-
-
-
*
*
*
*
-
CMP
A,ear
2
2
1
0
byte (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMP
A,eam
2+
3+(a)
0
(b)
byte (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMP
A,#imm8
2
2
0
0
byte (A) - imm8
-
-
-
-
-
*
*
*
*
-
CMPW
A
1
1
0
0
word (AH) - (AL)
-
-
-
-
-
*
*
*
*
-
CMPW
A,ear
2
2
1
0
word (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPW
A,eam
2+
3+(a)
0
(c)
word (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPW
A,#imm16
3
2
0
0
word (A) - imm16
-
-
-
-
-
*
*
*
*
-
CMPL
A,ear
2
6
2
0
long (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPL
A,eam
2+
7+(a)
0
(d)
long (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPL
A,#imm32
5
3
0
0
long (A) - imm32
-
-
-
-
-
*
*
*
*
-
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (d) in the table.
592
APPENDIX A Instructions
Table A.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIVU
A
1
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
-
-
-
-
-
-
-
*
*
-
DIVU
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
-
-
-
-
-
-
-
*
*
-
DIVU
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MULU
A
1
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
MULU
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A
1
*11
0
0
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
MULUW
A,ear
2
*12
1
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,eam
2+
*13
0
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
*1: 3: Division by 0 7: Overflow 15: Normal
*2: 4: Division by 0 8: Overflow 16: Normal
*3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal
*4: 4: Division by 0 7: Overflow 22: Normal
*5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal
*6: (b): Division by 0 or overflow 2 × (b): Normal
*7: (c): Division by 0 or overflow 2 × (c): Normal
*8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0.
*9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0.
*10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0.
*11: 3: Word (AH) is 0. 11: Word (AH) is not 0.
*12: 4: Word (ear) is 0. 12: Word (ear) is not 0.
*13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0.
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (c) in the table.
593
APPENDIX
Table A.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIV
A
2
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
Z
-
-
-
-
-
-
*
*
-
DIV
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
Z
-
-
-
-
-
-
*
*
-
DIV
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
Z
-
-
-
-
-
-
*
*
-
DIVW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MUL
A
2
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,eam
2+
*10
0
(b)
MULW
A
2
*11
0
0
MULW
A,ear
2
*12
1
MULW
A,eam
2+
*13
0
*1:
*2:
*3:
*4:
3: Division by 0, 8 or 18: Overflow, 18: Normal
4: Division by 0, 11 or 22: Overflow, 23: Normal
5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal
When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal
When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal
*5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal
When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal
*6: (b): Division by 0 or overflow, 2 × (b): Normal
*7: (c): Division by 0 or overflow, 2 × (c): Normal
*8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative
*9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative
*10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative
*11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative
*12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative
*13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative
Notes:
• The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a
pre-operation count or a post-operation count depending on the detection timing.
• When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed.
• See Table A.5-1 and Table A.5-2 for information on (a) to (c) in the table.
594
APPENDIX A Instructions
Table A.8-8 39 Logic 1 Instructions (Byte, Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
AND
A,#imm8
2
2
0
0
byte (A) ← (A) and imm8
-
-
-
-
-
*
*
R
-
AND
A,ear
2
3
1
0
byte (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
AND
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
byte (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
byte (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
AND
ear,A
2
3
2
0
AND
eam,A
2+
5+(a)
0
2 × (b)
OR
A,#imm8
2
2
0
0
byte (A) ← (A) or imm8
-
-
-
-
-
*
*
R
-
-
OR
A,ear
2
3
1
0
byte (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
OR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
OR
ear,A
2
3
2
0
byte (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
OR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XOR
A,#imm8
2
2
0
0
byte (A) ← (A) xor imm8
-
-
-
-
-
*
*
R
-
-
XOR
A,ear
2
3
1
0
byte (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XOR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XOR
ear,A
2
3
2
0
byte (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XOR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOT
A
1
2
0
0
byte (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOT
ear
2
3
2
0
byte (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOT
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
ANDW
A
1
2
0
0
word (A) ← (AH) and (A)
-
-
-
-
-
*
*
R
-
-
ANDW
A,#imm16
3
2
0
0
word (A) ← (A) and imm16
-
-
-
-
-
*
*
R
-
-
ANDW
A,ear
2
3
1
0
word (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
word (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
word (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
0
word (A) ← (AH) or (A)
-
-
-
-
-
*
*
R
-
-
0
word (A) ← (A) or imm16
-
-
-
-
-
*
*
R
-
-
1
0
word (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
4+(a)
0
(c)
word (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
2
3
2
0
word (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XORW
A
1
2
0
0
word (A) ← (AH) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
A,#imm16
3
2
0
0
word (A) ← (A) xor imm16
-
-
-
-
-
*
*
R
-
-
XORW
A,ear
2
3
1
0
word (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
ear,A
2
3
2
0
ANDW
eam,A
2+
5+(a)
0
2 × (c)
ORW
A
1
2
0
ORW
A,#imm16
3
2
0
ORW
A,ear
2
3
ORW
A,eam
2+
ORW
ear,A
ORW
XORW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
XORW
ear,A
2
3
2
0
word (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOTW
A
1
2
0
0
word (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOTW
ear
2
3
2
0
word (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOTW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (c) in the table.
595
APPENDIX
Table A.8-9 6 Logic 2 Instructions (Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
ANDL
A,ear
2
6
2
0
long (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
ORL
A,ear
2
6
2
0
long (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
ORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
XORL
A,ear
2
6
2
0
long (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
Note:
See Table A.5-1 and Table A.5-2 for information on (a) and (d) in the table.
Table A.8-10 6 Sign Inversion Instructions (Byte, Word)
Mnemonic
NEG
A
#
~
RG
B
1
2
0
0
byte (A) ← 0 - (A)
byte (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
byte (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
word (A) ← 0 - (A)
-
-
-
-
-
*
*
*
*
-
NEG
ear
2
3
2
0
NEG
eam
2+
5+(a)
0
2 × (b)
NEGW
A
1
2
0
0
NEGW
ear
2
3
2
0
NEGW
eam
2+
5+(a)
0
2 × (c)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
X
-
-
-
-
*
*
*
*
-
word (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
word (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (c) in the table.
Table A.8-11 1 Normalization Instruction (Long Word)
Mnemonic
NRML
A,R0
#
~
RG
B
2
*1
1
0
Operation
long (A) ← Shift left to the position where '1' is set
for the first time.
byte (R0) ← Shift count at that time
*1: 4 when all accumulators have a value of 0; otherwise, 6+(R0)
596
LH
AH
I
S
T
N
Z
V
C
RMW
-
-
-
-
-
-
*
-
-
-
APPENDIX A Instructions
Table A.8-12 18 Shift Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
RORC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
ear
2
3
2
0
byte (ear) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
*
ROLC
ear
2
3
2
0
byte (ear) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
*
ASR
A,R0
2
*1
1
0
byte (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSR
A,R0
2
*1
1
0
byte (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSL
A,R0
2
*1
1
0
byte (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRW
A
1
2
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSRW
A/SHRW A
1
2
0
0
word (A) ← Logical right shift (A, 1 bit)
-
-
-
-
*
R
*
-
*
-
LSLW
A/SHLW A
1
2
0
0
word (A) ← Logical left shift (A, 1 bit)
-
-
-
-
-
*
*
-
*
-
ASRW
A,R0
2
*1
1
0
word (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRW
A,R0
2
*1
1
0
word (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLW
A,R0
2
*1
1
0
word (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRL
A,R0
2
*2
1
0
long (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRL
A,R0
2
*2
1
0
long (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLL
A,R0
2
*2
1
0
long (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
*1: 6 when R0 is 0; otherwise, 5 + (R0)
*2: 6 when R0 is 0; otherwise, 6 + (R0)
Note:
See Table A.5-1 and Table A.5-2 for information on (a) and (b) in the table.
597
APPENDIX
Table A.8-13 31 Branch 1 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
BZ/BEQ
rel
2
*1
0
0
Branch on (Z) = 1
-
-
-
-
-
-
-
-
-
-
BNZ/
BNE
rel
2
*1
0
0
Branch on (Z) = 0
-
-
-
-
-
-
-
-
-
-
BC/BLO
rel
2
*1
0
0
Branch on (C) = 1
-
-
-
-
-
-
-
-
-
-
BNC/
BHS
rel
2
*1
0
0
Branch on (C) = 0
-
-
-
-
-
-
-
-
-
-
BN
rel
2
*1
0
0
Branch on (N) = 1
-
-
-
-
-
-
-
-
-
-
BP
rel
2
*1
0
0
Branch on (N) = 0
-
-
-
-
-
-
-
-
-
-
BV
rel
2
*1
0
0
Branch on (V) = 1
-
-
-
-
-
-
-
-
-
-
BNV
rel
2
*1
0
0
Branch on (V) = 0
-
-
-
-
-
-
-
-
-
-
BT
rel
2
*1
0
0
Branch on (T) = 1
-
-
-
-
-
-
-
-
-
-
BNT
rel
2
*1
0
0
Branch on (T) = 0
-
-
-
-
-
-
-
-
-
-
BLT
rel
2
*1
0
0
Branch on (V) xor (N) = 1
-
-
-
-
-
-
-
-
-
-
BGE
rel
2
*1
0
0
Branch on (V) xor (N) = 0
-
-
-
-
-
-
-
-
-
-
BLE
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BGT
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BLS
rel
2
*1
0
0
Branch on (C) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BHI
rel
2
*1
0
0
Branch on (C) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BRA
rel
2
*1
0
0
Unconditional branch
-
-
-
-
-
-
-
-
-
-
JMP
@A
1
2
0
0
word (PC) ← (A)
-
-
-
-
-
-
-
-
-
-
JMP
addr16
3
3
0
0
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
JMP
@ear
2
3
1
0
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
JMP
@eam
2+
4+(a)
0
(c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
JMPP
@ear *3
2
5
2
0
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
JMPP
@eam *3
2+
6+(a)
0
(d)
JMPP
addr24
4
4
0
0
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
CALL
@ear *4
2
6
1
(c)
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
CALL
@eam *4
2+
7+(a)
0
2 × (c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
CALL
addr16 *5
3
6
0
(c)
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
CALLV
#vct4 *5
1
7
0
2 × (c)
Vector call instruction
-
-
-
-
-
-
-
-
-
-
CALLP
@ear *6
2
10
2
2 × (c)
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
CALLP
@eam *6
2+
11+(a)
0
*2
CALLP
addr24 *7
4
10
0
2 × (c)
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
*1: 4 when a branch is made; otherwise, 3
*2: 3 × (c) + (b)
*3: Read (word) of branch destination address
*4: W: Save to stack (word) R: Read (word) of branch destination address
*5: Save to stack (word)
*6: W: Save to stack (long word), R: Read (long word) of branch destination address
*7: Save to stack (long word)
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (d) in the table.
598
APPENDIX A Instructions
Table A.8-14 19 Branch 2 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S T N Z V C
RMW
CBNE
A,#imm8,rel
3
*1
0
0
Branch on byte (A) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
A,#imm16,rel
4
*1
0
0
Branch on word (A) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CBNE
ear,#imm8,rel
4
*2
1
0
Branch on byte (ear) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CBNE
eam,#imm8,rel *9
4+
*3
0
(b)
Branch on byte (eam) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
ear,#imm16,rel
5
*4
1
0
Branch on word (ear) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CWBNE
eam,#imm16,rel*9
5+
*3
0
(c)
Branch on word (eam) not equal to imm16
-
-
-
-
-
*
*
*
*
-
DBNZ
ear,rel
3
*5
2
0
byte (ear) ← (ear) - 1, Branch on (ear) not equal to 0
-
-
-
-
-
*
*
*
-
*
DBNZ
eam,rel
3+
*6
2
DWBNZ
ear,rel
3
*5
2
DWBNZ
eam,rel
3+
*6
2
2 × (b) byte (eam) ← (eam) - 1, Branch on (eam) not equal to 0
-
-
-
-
-
*
*
*
-
-
-
-
-
-
*
*
*
-
-
2 × (c) word (eam) ← (eam) - 1, Branch on (eam) not equal to 0
-
-
-
-
-
*
*
*
-
*
0
word (ear) ← (ear) - 1, Branch on (ear) not equal to 0
INT
#vct8
2
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT
addr16
3
16
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INTP
addr24
4
17
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
1
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT9
RETI
LINK
#imm8
UNLINK
1
*8
0
*7
Return from interrupt
-
-
*
*
*
*
*
*
*
-
2
6
0
(c)
Saves the old frame pointer in the stack upon entering the
function, then sets the new frame pointer and reserves the
local pointer area.
-
-
-
-
-
-
-
-
-
-
1
5
0
(c)
Recovers the old frame pointer from the stack upon exiting
the function.
-
-
-
-
-
-
-
-
-
-
RET
*10
1
4
0
(c)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
RETP
*11
1
6
0
(d)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
*1: 5 when a branch is made; otherwise, 4
*2: 13 when a branch is made; otherwise, 12
*3: 7+(a) when a branch is made; otherwise, 6+(a)
*4: 8 when a branch is made; otherwise, 7
*5: 7 when a branch is made; otherwise, 6
*6: 8+(a) when a branch is made; otherwise, 7+(a)
*7: 3 × (b) + 2 × (c) when jumping to the next interruption request; 6 × (c) when returning from the current interruption
*8: 15 when jumping to the next interruption request; 17 when returning from the current interruption
*9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction.
*10: Return from stack (word)
*11: Return from stack (long word)
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (d) in the table.
599
APPENDIX
Table A.8-15 28 Other Control Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
PUSHW
A
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (A)
-
-
-
-
-
-
-
-
-
-
PUSHW
AH
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (AH)
-
-
-
-
-
-
-
-
-
-
PUSHW
PS
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (PS)
-
-
-
-
-
-
-
-
-
-
PUSHW
rlst
2
*3
*5
*4
(SP) ← (SP) - 2n, ((SP)) ← (rlst)
-
-
-
-
-
-
-
-
-
-
POPW
A
1
3
0
(c)
word (A) ← ((SP)), (SP) ← (SP) + 2
-
*
-
-
-
-
-
-
-
-
POPW
AH
1
3
0
(c)
word (AH) ← ((SP)), (SP) ← (SP) + 2
-
-
-
-
-
-
-
-
-
-
POPW
PS
1
4
0
(c)
word (PS) ← ((SP)), (SP) ← (SP) + 2
-
-
*
*
*
*
*
*
*
-
POPW
rlst
2
*2
*5
*4
(rlst) ← ((SP)), (SP) ← (SP) + 2n
-
-
-
-
-
-
-
-
-
-
JCTX
@A
1
14
0
6 × (c)
Context switch instruction
-
-
*
*
*
*
*
*
*
-
AND
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) and imm8
-
-
*
*
*
*
*
*
*
-
OR
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) or imm8
-
-
*
*
*
*
*
*
*
-
MOV
RP,#imm8
2
2
0
0
byte (RP) ← imm8
-
-
-
-
-
-
-
-
-
-
MOV
ILM,#imm8
2
2
0
0
byte (ILM) ← imm8
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,ear
2
3
1
0
word (RWi) ← ear
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,eam
2+
2+(a)
1
0
word (RWi) ← eam
-
-
-
-
-
-
-
-
-
-
MOVEA
A,ear
2
1
0
0
word (A) ← ear
-
*
-
-
-
-
-
-
-
-
MOVEA
A,eam
2+
1+(a)
0
0
word (A) ← eam
-
*
-
-
-
-
-
-
-
-
ADDSP
#imm8
2
3
0
0
word (SP) ← (SP) + ext(imm8)
-
-
-
-
-
-
-
-
-
-
ADDSP
#imm16
3
3
0
0
word (SP) ← (SP) + imm16
-
-
-
-
-
-
-
-
-
-
MOV
A,brg1
2
*1
0
0
byte (A) ← (brg1)
Z
*
-
-
-
*
*
-
-
-
MOV
brg2,A
-
2
1
0
0
byte (brg2) ← (A)
-
-
-
-
-
*
*
-
-
NOP
1
1
0
0
No operation
-
-
-
-
-
-
-
-
-
-
ADB
1
1
0
0
Prefix code for AD space access
-
-
-
-
-
-
-
-
-
-
DTB
1
1
0
0
Prefix code for DT space access
-
-
-
-
-
-
-
-
-
-
PCB
1
1
0
0
Prefix code for PC space access
-
-
-
-
-
-
-
-
-
-
SPB
1
1
0
0
Prefix code for SP space access
-
-
-
-
-
-
-
-
-
-
NCC
1
1
0
0
Prefix code for flag no-change
-
-
-
-
-
-
-
-
-
-
CMR
1
1
0
0
Prefix code for common register bank
-
-
-
-
-
-
-
-
-
-
*1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2
*2: 7 + 3 × (POP count) + 2 × (POP last register number), 7 when RLST = 0 (no transfer register)
*3: 29 + 3 × (PUSH count) - 3 × (PUSH last register number), 8 when RLST = 0 (no transfer register)
*4: (POP count) × (c) or (PUSH count) × (c)
*5: (POP count) or (PUSH count)
Note:
See Table A.5-1 and Table A.5-2 for information on (a) and (c) in the table.
600
APPENDIX A Instructions
Table A.8-16 21 Bit Operand Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
MOVB
A,dir:bp
3
5
0
(b)
byte (A) ← (dir:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,addr16:bp
4
5
0
(b)
byte (A) ← (addr16:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,io:bp
3
4
0
(b)
byte (A) ← (io:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
dir:bp,A
3
7
0
2 × (b)
bit (dir:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
addr16:bp,A
4
7
0
2 × (b)
bit (addr16:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
io:bp,A
3
6
0
2 × (b)
bit (io:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
*
SETB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 1
-
-
-
-
-
-
-
-
-
SETB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
*
CLRB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 0
-
-
-
-
-
-
-
-
-
CLRB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
CLRB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
BBC
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
io:bp,rel
4
*2
0
(b)
Branch on (io:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBS
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
io:bp,rel
4
*2
0
(b)
Branch on (io:bp) b = 1
-
-
-
-
-
-
*
-
-
-
SBBS
addr16:bp,rel
5
*3
0
2 × (b)
Branch on (addr16:bp) b = 1,
bit (addr16:bp) b ← 1
-
-
-
-
-
-
*
-
-
*
WBTS
io:bp
3
*4
0
*5
Waits until (io:bp) b = 1
-
-
-
-
-
-
-
-
-
-
WBTC
io:bp
3
*4
0
*5
Waits until (io:bp) b = 0
-
-
-
-
-
-
-
-
-
-
RMW
*1: 8 when a branch is made; otherwise, 7
*2: 7 when a branch is made; otherwise, 6
*3: 10 when the condition is met; otherwise, 9
*4: Undefined count
*5: Until the condition is met
Note:
See Table A.5-1 and Table A.5-2 for information on (b) in the table.
Table A.8-17 6 Accumulator Operation Instructions (Byte, Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
SWAP
Mnemonic
1
3
0
0
byte (A)0-7 ↔ (A)8-15
Operation
-
-
-
-
-
-
-
-
-
-
SWAPW
1
2
0
0
word (AH) ↔ (AL)
-
*
-
-
-
-
-
-
-
-
EXT
1
1
0
0
Byte sign extension
X
-
-
-
-
*
*
-
-
-
EXTW
1
2
0
0
Word sign extension
-
X
-
-
-
*
*
-
-
-
ZEXT
1
1
0
0
Byte zero extension
Z
-
-
-
-
R
*
-
-
-
ZEXTW
1
1
0
0
Word zero extension
-
Z
-
-
-
R
*
-
-
-
601
APPENDIX
Table A.8-18 10 String Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
MOVS / MOVSI
2
*2
*5
*3
byte transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
MOVSD
2
*2
*5
*3
byte transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCEQ / SCEQI
2
*1
*8
*4
byte search @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCEQD
2
*1
*8
*4
byte search @AH- ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
FILS / FILSI
2
6m+6
*8
*3
byte fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
MOVSW / MOVSWI
2
*2
*5
*6
word transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
-
MOVSWD
2
*2
*5
*6
word transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCWEQ / SCWEQI
2
*1
*8
*7
word search @AH+ - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCWEQD
2
*1
*8
*7
word search @AH- - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
FILSW / FILSWI
2
6m+6
*8
*6
word fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
*1: 5 when RW0 is 0, 4 + 7 × (RW0) when the counter expires, or 7n + 5 when a match occurs
*2: 5 when RW0 is 0; otherwise, 4 + 8 × (RW0)
*3: (b) × (RW0) + (b) × (RW0) When the source and destination access different areas, calculate the (b) item individually.
*4: (b) × n
*5: 2 × (b) × (RW0)
*6: (c) × (RW0) + (c) × (RW0) When the source and destination access different areas, calculate the (c) item individually.
*7: (c) × n
*8: (b) × (RW0)
Note:
m: RW0 value (counter value), n: Loop count
See Table A.5-1 and Table A.5-2 for information on (b) and (c) in the table.
602
APPENDIX A Instructions
A.9
Instruction Map
Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction
map consists of multiple pages. Table A.9-2 to Table A.9-21 summarize the F2MC-16LX
instruction map.
■ Structure of Instruction Map
Figure A.9-1 Structure of Instruction Map
Basic page map
Bit operation
instructions
Character string
operation
instructions
2-byte
instructions
: Byte 1
ea instructions × 9 : Byte 2
An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An
instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it
references byte 1, and can check the following one byte by referencing the map for byte 2. Figure A.9-2
shows the correspondence between an actual instruction code and instruction map.
603
APPENDIX
Figure A.9-2 Correspondence between Actual Instruction Code and Instruction Map
Some instructions do
not contain byte 2.
Instruction
code
Length varies
depending on the
instruction.
Byte 1
Byte 2
Operand
Operand
...
[Basic page map]
XY
+Z
[Extended page map]*
UV
+W
*: The extended page map is a generic name of maps for bit operation instructions, character
string operation instructions, 2-byte instructions, and ea instructions. Actually, there are
multiple extended page maps for each type of instructions.
An example of an instruction code is shown in Table A.9-1.
Table A.9-1 Example of an Instruction Code
Byte 1
(from basic page map)
Byte 2
(from extended page map)
NOP
00 +0=00
-
AND A, #8
30 +4=34
-
MOV A, ADB
60 +F=6F
00 +0=00
@RW2+d8, #8, rel
70 +0=70
F0 +2=F2
Instruction
604
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
A
ZEXT
SWAP
ADDSP
DTB
ADB
SPB
#8
A, #8
dir, A
A, dir
io, A
A, io
JMP
BRA
60
MULU
DIVU
ea
@A instruction 2
A
MOVW
MOVX
RET
SP, A A, addr16
A0
B0
C0
ea
instruction 8
D0
E0
rel
rel
LSRW
ASRW
LSLW
SWAPW
ZEXTW
XORW
ORW
ANDW
ORW
PUSHW
POPW
A, #16
AH
AH
MOVW
ea, RWi
Bit operation MOV
A instruction
ea, Ri
MOVW
RWi, ea
PUSHW
POPW
2-byte
XCHW
A
rlst
rlst instruction
RWi, ea
Character
XORW
PUSHW
POPW
XCH
operation
A
A, #16
PS
PS string
Ri, ea
instruction
A
ANDW
PUSHW
POPW
A
A, #16
A
CMPW
MOVL
MOVW
RETI
A, #16
A, #32 addr16, A
ADDSP
MULUW
NOTW
A
#16
A
A
A
EXTW
A
BHI
BLS
BGT
BLE
rel
rel
rel
rel
rel
BGE
CMPL
CMPW
A, #32
NEGW
A
rel
rel
rel
rel
rel
rel
BLT
BT
BNV
BV
BP
BN
BNC/BHS
rel
BC/BLO
BNZ/BNE
rel
BZ/BEQ
MOV
MOV
CBNE A, CWBNE A, MOVW
MOVW
INTP
MOV
RP, #8
ILM, #8
#8, rel
#16, rel
A, #16 A,addr16
addr24
Ri, ea
#4
F0
rel
ADDW
MOVW
MOVW
INT
ea
MOVW
MOVW
MOVW
MOV A,
MOVW
A, #16
A, dir
A, io
#vct8 instruction 9
A, RWi
RWi, A RWi, #16 @RWi+d8 @RWi+d8, A
NOT
ea
instruction 7
MOVX
MOVX
CALLP
ea
A, dir
A, io
addr24 instruction 6
MOVW
MOVW
RETP
A, #8
A, SP
io, #16
A, #8
90
BNT
SUBL
SUBW
A, #32
A
A
A
XOR
OR
OR
CCR, #8
80
ea
MOV
MOV
MOV
MOV
MOVX A, MOV
CALL
rel instruction 1
A, Ri
Ri, A
Ri, #8
A, Ri @RWi+d8
A, #4
70
MOV
JMP
ea
A, addr16
addr16 instruction 3
MOV
MOV
50
MOVX
MOV
JMPP
ea
A, #8
A, #8 addr16, A
addr24 instruction 4
MOV
MOV
MOV
40
SUBW
MOVW
MOVW
INT
MOVEA
A
A, #16
dir, A
io, A
addr16
RWi, ea
UNLINK
A
CMP
A
A, #8
A, #8
SUBC
SUB
ADD
30
AND
AND
MOV
MOV
CALL
ea
CCR, #8
A, #8
dir, #8
io, #8
addr16 instruction 5
CMP
A
A, dir
A, dir
ADDC
SUB
ADD
20
LINK
ADDL
ADDW
#imm8
A, #32
EXT
@A
PCB
A
JCTX
SUBDC
ADDDC
NEG
NCC
INT9
A
CMR
10
NOP
00
APPENDIX A Instructions
Table A.9-2 Basic Page Map
605
606
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
10
MOVB
io:bp, A
20
30
CLRB
io:bp
40
50
SETB
io:bp
60
70
BBC
io;bp, rel
80
90
BBS
io:bp, rel
A0
B0
MOVB
MOVB A, MOVB
MOVB
CLRB
CLRB
SETB
SETB
BBC
BBC
BBS
BBS
A, dir:bp addr16:bp
dir:bp, A addr16:bp,A
dir:bp addr16:bp
dir:bp addr16:bp dir:bp, rel addr16:bp,rel dir:bp, rel addr16:bp,rel
MOVB
A, io:bp
00
WBTS
io:bp
C0
D0
WBTC
io:bp
E0
SBBS
addr16:bp
F0
APPENDIX
Table A.9-3 Bit Operation Instruction Map (First Byte = 6CH)
MOVSI
MOVSD
PCB, PCB
PCB, DTB
PCB, ADB
PCB, SPB
DTB, PCB
DTB, DTB
DTB, ADB
DTB, SPB
ADB, PCB
ADB, DTB
ADB, ADB
ADB, SPB
SPB, PCB
SPB, DTB
SPB, ADB
SPB, SPB
+1
+2
+3
+4
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
10
+0
00
MOVSWI
20
MOVSWD
30
40
50
60
70
90
A0
B0
C0
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SCEQI
SCEQD
SCWEQI SCWEQD FILSI
PCB
PCB
PCB
PCB
PCB
80
D0
FILSI
SPB
ADB
DTB
PCB
E0
F0
APPENDIX A Instructions
Table A.9-4 Character String Operation Instruction Map (First Byte = 6EH)
607
608
LSLW
LSLL
LSL
MOVW
MOVW
A, R0
A, R0
A, R0 @RL2+d8, A A, @RL2+d8
MOVW
MOVW
NRML
A, @A @AL, AH
A, R0
ASRW
ASRL
ASR
MOVW
MOVW
A, R0
A, R0
A, R0 @RL3+d8, A A, @RL3+d8
LSRW
LSRL
LSR
A, R0
A, R0
A, R0
+D
+E
+F
MOVW
MOVW
@RL1+d8, A A, @RL1+d8
MOVW
MOVW
@RL0+d8, A A, @RL0+d8
+C
+B
+A
+9
+8
A
MOV
MOV
MOVX
MOV
MOV
A, PCB
A, @A A, @RL3+d8 @RL3+d8, A A, @RL3+d8
+6
ROLC
MOV
MOV
A, @A @AL, AH
+5
A
MOV
MOV
MOVX
MOV
MOV
A, DPR
DPR, A A, @RL2+d8 @RL2+d8, A A, @RL2+d8
+4
ROLC
MOV
MOV
A, USB
USB, A
+3
+7
MOV
MOV
MOVX
MOV
MOV
A, SSB
SSB, A A, @RL1+d8 @RL1+d8, A A, @RL1+d8
+2
40
MOV
MOV
A, ADB
ADB, A
30
+1
20
MOV
MOV
MOVX
MOV
MOV
A, DTB
DTB, A A, @RL0+d8 @RL0+d8, A A, @RL0+d8
10
+0
00
50
DIVU
MULW
MUL
60
A
A
A
70
80
90
A0
B0
C0
D0
E0
F0
APPENDIX
Table A.9-5 2-byte Instruction Map (First Byte = 6FH)
50
90
B0
D0
@RW1, @RW1+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
@RW2, @RW2+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
@RW3, @RW3+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
SUBL
SUBL A,
A, RL2 @RW5+d8
SUBL
SUBL A,
A, RL3 @RW6+d8
SUBL
SUBL A,
A, RL3 @RW7+d8
ADDL
ADDL A,
A, RL2 @RW5+d8
ADDL
ADDL A,
A, RL3 @RW6+d8
ADDL
ADDL A,
A, RL3 @RW7+d8
ADDL
ADDL A, SUBL
SUBL A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ADDL
ADDL A, SUBL
SUBL A, Use
@RW0+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW0+RW7
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
#16, rel A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
,#8, rel
ADDL
ADDL A, SUBL
SUBL A, Use
@RW1+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW1+RW7
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
#16, rel A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
,#8, rel
ADDL
ADDL A,
A,@RW2+ @PC+d16
ADDL
ADDL A, SUBL
SUBL A, Use
A,@RW3+
addr16 A,@RW3+
addr16 prohibited
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
SUBL
SUBL A,
A,@RW2+ @PC+d16
@RW0, @RW0+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
SUBL
SUBL A,
A, RL2 @RW4+d8
Use
prohibited
ANDL
ANDL A,
A,@RW2+ @PC+d16
ANDL
ANDL A,
A, RL3 @RW7+d8
ANDL
ANDL A,
A, RL3 @RW6+d8
ANDL
ANDL A,
A, RL2 @RW5+d8
ANDL
ANDL A,
A, RL2 @RW4+d8
ORL
ORL A,
A,@RW2+ @PC+d16
ORL
ORL A,
A, RL3 @RW7+d8
ORL
ORL A,
A, RL3 @RW6+d8
ORL
ORL A,
A, RL2 @RW5+d8
ORL
ORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A,@RW2+ @PC+d16
XORL
XORL A,
A, RL3 @RW7+d8
XORL
XORL A,
A, RL3 @RW6+d8
XORL
XORL A,
A, RL2 @RW5+d8
XORL
XORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A, RL1 @RW3+d8
addr16,
,#8, rel
Use
@PC+d16,
prohibited
,#8, rel
@RW3, @RW3+d16
#8, rel
,#8, rel
@RW2, @RW2+d16
#8, rel
,#8, rel
@RW1, @RW1+d16
#8, rel
,#8, rel
@RW0, @RW0+d16
#8, rel
,#8, rel
R7, @RW7+d8,
#8, rel
#8, rel
R6, @RW6+d8,
#8, rel
#8, rel
R5, @RW5+d8,
#8, rel
#8, rel
R4, @RW4+d8,
#8, rel
#8, rel
R3, @RW3+d8,
#8, rel
#8, rel
addr16, CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
#16, rel A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 prohibited
@PC+d16, CMPL
CMPL A,
#16, rel A,@RW2+ @PC+d16
RW7, @RW7+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW7+d8
RW6, @RW6+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW6+d8
RW5, @RW5+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW5+d8
RW4, @RW4+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW4+d8
ORL
ORL A,
A, RL1 @RW3+d8
R2, @RW2+d8,
#8, rel
#8, rel
R1, @RW1+d8,
#8, rel
#8, rel
ADDL
ADDL A,
A, RL2 @RW4+d8
ANDL
ANDL A,
A, RL1 @RW3+d8
XORL
XORL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW1+d8
+4
RW3, @RW3+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW3+d8
ORL
ORL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW1+d8
SUBL
SUBL A,
A, RL1 @RW3+d8
ANDL
ANDL A,
A, RL1 @RW2+d8
ANDL
ANDL A,
A, RL0 @RW1+d8
ADDL
ADDL A,
A, RL1 @RW3+d8
RW2, @RW2+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW2+d8
RW1, @RW1+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW1+d8
+3
CBNE ↓
F0
R0, @RW0+d8,
#8, rel
#8, rel
CBNE ↓
E0
SUBL
SUBL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW0+d8
C0
ADDL
ADDL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW0+d8
A0
+2
ANDL
ANDL A,
A, RL0 @RW0+d8
80
SUBL
SUBL A,
A, RL0 @RW1+d8
70
ADDL
ADDL A,
A, RL0 @RW1+d8
60
RW0, @RW0+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW0+d8
CWBNE ↓ CWBNE ↓
40
+1
30
+0
20
SUBL
SUBL A,
A, RL0 @RW0+d8
10
ADDL
ADDL A,
A, RL0 @RW0+d8
00
APPENDIX A Instructions
Table A.9-6 ea Instruction 1 (First Byte = 70H)
609
610
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW7+d8
@RL3 @@RW7+d8
RL3 @RW7+d8
RL3 @RW7+d8
A, RL3 @RW7+d8
RL3, A @RW7+d8,A
R7, #8 @RW7+d8,#8
A, RW7 @RW7+d8
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #8 @RW0+d16,#8
A,@RW0 @RW0+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1,A @RW1+d16,A @RW1, #8 @RW1+d16,#8
A,@RW1 @RW1+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2,A @RW2+d16,A @RW2, #8 @RW2+d16,#8
A,@RW2 @RW2+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3,A @RW3+d16,A @RW3, #8 @RW3+d16,#8
A,@RW3 @RW3+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+,A @RW0+RW7,A @RW0+, #8 @RW0+RW7,#8 A,@RW0+ @RW0+RW7
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+,A @RW1+RW7,A @RW1+, #8 @RW1+RW7,#8 A,@RW1+ @RW1+RW7
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+,A @PC+d16, A @RW2+, #8 @PC+d16, #8 A,@RW2+ @PC+d16
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+,A
addr16, A @RW3+, #8
addr16, #8 A,@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW6+d8
@RL3 @@RW6+d8
RL3 @RW6+d8
RL3 @RW6+d8
A, RL3 @RW6+d8
RL3, A @RW6+d8,A
R6, #8 @RW6+d8,#8
A, RW6 @RW6+d8
D0
+6
C0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW5+d8
@RL2 @@RW5+d8
RL2 @RW5+d8
RL2 @RW5+d8
A, RL2 @RW5+d8
RL2, A @RW5+d8,A
R5, #8 @RW5+d8,#8
A, RW5 @RW5+d8
B0
+5
A0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW4+d8
@RL2 @@RW4+d8
RL2 @RW4+d8
RL2 @RW4+d8
A, RL2 @RW4+d8
RL2, A @RW4+d8,A
R4, #8 @RW4+d8,#8
A, RW4 @RW4+d8
90
+4
80
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW3+d8
@RL1 @@RW3+d8
RL1 @RW3+d8
RL1 @RW3+d8
A, RL1 @RW3+d8
RL1, A @RW3+d8,A
R3, #8 @RW3+d8,#8
A, RW3 @RW3+d8
70
+3
60
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW2+d8
@RL1 @@RW2+d8
RL1 @RW2+d8
RL1 @RW2+d8
A, RL1 @RW2+d8
RL1, A @RW2+d8,A
R2, #8 @RW2+d8,#8
A, RW2 @RW2+d8
50
+2
40
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW1+d8
@RL0 @@RW1+d8
RL0 @RW1+d8
RL0 @RW1+d8
A, RL0 @RW1+d8
RL0, A @RW1+d8,A
R1, #8 @RW1+d8,#8
A, RW1 @RW1+d8
30
+1
20
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW0+d8
@RL0 @@RW0+d8
RL0 @RW0+d8
RL0 @RW0+d8
A, RL0 @RW0+d8
RL0, A @RW0+d8,A
R0, #8 @RW0+d8,#8
A, RW0 @RW0+d8
10
+0
00
APPENDIX
Table A.9-7 ea Instruction 2 (First Byte = 71H)
D0
E0
F0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A A,@RW3+
addr16 A,@RW3+
addr16
+D
+E
+F
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R7 @RW7+d8
A, R7 @RW7+d8
R7, A @RW7+d8,A
A, R7 @RW7+d8
A, R7 @RW7+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R6 @RW6+d8
A, R6 @RW6+d8
R6, A @RW6+d8,A
A, R6 @RW6+d8
A, R6 @RW6+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R5 @RW5+d8
A, R5 @RW5+d8
R5, A @RW5+d8,A
A, R5 @RW5+d8
A, R5 @RW5+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R4 @RW4+d8
A, R4 @RW4+d8
R4, A @RW4+d8,A
A, R4 @RW4+d8
A, R4 @RW4+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R3 @RW3+d8
A, R3 @RW3+d8
R3, A @RW3+d8,A
A, R3 @RW3+d8
A, R3 @RW3+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R2 @RW2+d8
A, R2 @RW2+d8
R2, A @RW2+d8,A
A, R2 @RW2+d8
A, R2 @RW2+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R1 @RW1+d8
A, R1 @RW1+d8
R1, A @RW1+d8,A
A, R1 @RW1+d8
A, R1 @RW1+d8
+C
INC
DEC
R7 @RW7+d8
C0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ROLC
RORC
RORC
INC
R7 @RW7+d8
R7 @RW7+d8
ROLC
INC
DEC
R6 @RW6+d8
B0
+B
ROLC
RORC
RORC
INC
R6 @RW6+d8
R6 @RW6+d8
ROLC
INC
DEC
R5 @RW5+d8
A0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ROLC
RORC
RORC
INC
R5 @RW5+d8
R5 @RW5+d8
ROLC
INC
DEC
R4 @RW4+d8
90
+A
ROLC
RORC
RORC
INC
R4 @RW4+d8
R4 @RW4+d8
ROLC
INC
DEC
R3 @RW3+d8
INC
DEC
R2 @RW2+d8
INC
DEC
R1 @RW1+d8
80
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R0 @RW0+d8
A, R0 @RW0+d8
R0, A @RW0+d8,A
A, R0 @RW0+d8
A, R0 @RW0+d8
70
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ROLC
RORC
RORC
INC
R3 @RW3+d8
R3 @RW3+d8
ROLC
60
INC
DEC
R0 @RW0+d8
50
+9
ROLC
RORC
RORC
INC
R2 @RW2+d8
R2 @RW2+d8
ROLC
40
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0, A @RW0+d16,A
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ROLC
RORC
RORC
INC
R1 @RW1+d8
R1 @RW1+d8
ROLC
30
ROLC
RORC
RORC
INC
R0 @RW0+d8
R0 @RW0+d8
20
ROLC
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX A Instructions
Table A.9-8 ea Instruction 3 (First Byte = 72H)
611
612
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16 @RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, #16 @RW3+d16,#16 A,@RW3 @RW3+d16
+B
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A @RW3+, #16
addr16, #16 A,@RW3+
addr16
INCW @
+F
INCW
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16 @RW2+ @@PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A @RW2+, #16 @PC+d16, #16 A,@RW2+ @PC+d16
CALL @
+E
CALL
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, #16 @RW1+RW7,#16 A,@RW1+ @RW1+RW7
XCHW
XCHW A,
A, RW7 @RW7+d8
XCHW
XCHW A,
A, RW6 @RW6+d8
XCHW
XCHW A,
A, RW5 @RW5+d8
+D @@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7
INCW @
MOVW
MOVW
RW7, #16 @RW7+d8,#16
MOVW
MOVW
RW6, #16 @RW6+d8,#16
MOVW
MOVW
RW5, #16 @RW5+d8,#16
XCHW
XCHW A,
A, RW4 @RW4+d8
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, #16 @RW0+RW7,#16 A,@RW0+ @RW0+RW7
INCW
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW7 @RW7+d8
RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, A @RW7+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW6 @RW6+d8
RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, A @RW6+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW5 @RW5+d8
RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, A @RW5+d8,A
MOVW
MOVW
RW4, #16 @RW4+d8,#16
+C @@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7
JMP @
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16 @RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, #16 @RW2+d16,#16 A,@RW2 @RW2+d16
+A
JMP
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16 @RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, #16 @RW1+d16,#16 A,@RW1 @RW1+d16
+9
CALL @
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16 @RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #16 @RW0+d16,#16 A,@RW0 @RW0+d16
+8
CALL
CALL
CALL
RW7 @@RW7+d8
JMP
JMP
@RW7 @@RW7+d8
+7
JMP @
CALL
CALL
RW6 @@RW6+d8
JMP
JMP
@RW6 @@RW6+d8
+6
JMP
CALL
CALL
RW5 @@RW5+d8
JMP
JMP
@RW5 @@RW5+d8
+5
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW4 @RW4+d8
RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, A @RW4+d8,A
XCHW
XCHW A,
A, RW3 @RW3+d8
XCHW
XCHW A,
A, RW2 @RW2+d8
XCHW
XCHW A,
A, RW1 @RW1+d8
CALL
CALL
RW4 @@RW4+d8
MOVW
MOVW
RW3, #16 @RW3+d8,#16
MOVW
MOVW
RW2, #16 @RW2+d8,#16
MOVW
MOVW
RW1, #16 @RW1+d8,#16
JMP
JMP
@RW4 @@RW4+d8
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW3 @RW3+d8
RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, A @RW3+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW2 @RW2+d8
RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, A @RW2+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW1 @RW1+d8
RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, A @RW1+d8,A
+4
F0
XCHW
XCHW A,
A, RW0 @RW0+d8
E0
CALL
CALL
RW3 @@RW3+d8
D0
MOVW
MOVW
RW0, #16 @RW0+d8,#16
C0
JMP
JMP
@RW3 @@RW3+d8
B0
+3
A0
CALL
CALL
RW2 @@RW2+d8
90
JMP
JMP
@RW2 @@RW2+d8
80
+2
70
CALL
CALL
RW1 @@RW1+d8
60
JMP
JMP
@RW1 @@RW1+d8
50
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW0 @RW0+d8
RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, A @RW0+d8,A
40
+1
30
CALL
CALL
RW0 @@RW0+d8
20
JMP
JMP
@RW0 @@RW0+d8
10
+0
00
APPENDIX
Table A.9-9 ea Instruction 4 (First Byte = 73H)
ADD
A, SUB
SUB
SUB
ADDC
A, ADDC
A,
ADDC
ADDC A,
A, CMP
CMP
CMP
CMP
A,
A,
A, AND
AND
AND
AND
AND
AND
A,
A,
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r PC+d16, r
+F A,@RW3+
ADD
ADD
SUB
SUB
ADDC
ADDC
CMP
CMP
AND
AND
OR
OR
XOR
XOR
DBNZ
DBNZ
A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+
A, addr16 A,@RW3+ A, addr16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ADD
SUB
CMP
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW1+ @RW1+RW7 @RW1+, r W1+RW7, r
A,
CMP
OR
OR
A,
A,@RW1+ @RW1+RW7
ADD
ADD
ADDC A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ADDC
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW0+ @RW0+RW7 @RW0+, r W0+RW7, r
A,
OR
OR
A,
A,@RW0+ @RW0+RW7
SUB
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
SUB
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW3 @RW3+d16 @RW3, r W3+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
A,
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW2 @RW2+d16 @RW2, r W2+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW1 @RW1+d16 @RW1, r W1+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW0 @RW0+d16 @RW0, r W0+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
R7, r RW7+d8, r
ADD
F0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
R6, r RW6+d8, r
E0
ADD
D0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
R5, r RW5+d8, r
C0
ADD
B0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
R4, r RW4+d8, r
A0
ADD
90
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
R3, r RW3+d8, r
80
ADD
70
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
R2, r RW2+d8, r
60
ADD
50
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
R1, r RW1+d8, r
40
ADD
30
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
R0, r RW0+d8, r
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX A Instructions
Table A.9-10 ea Instruction 5 (First Byte = 74H)
613
614
NOT
NOT
R2 @RW2+d8
SUB
SUB
SUB
SUB
ADD
SUB
SUB
@RW1+RW7,A @RW1+, A @RW1+RW7,A
ADD @R
@RW0+RW7,A @RW0+, A @RW0+RW7,A
ADD @R
+F
ADD
ADD
@RW3+, A addr16, A
SUB
SUB
@RW3+, A addr16, A
+E @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
ADD
+D @RW1+, A
ADD
+C @RW0+, A
ADD
NOT
NOT
@RW1+ @RW1+RW7
NOT
NOT
@RW0+ @RW0+RW7
SUBC
SUBC A, NEG
NEG A,
AND
AND
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
OR
OR
@RW3+, A addr16, A
XOR
XOR
@RW3+, A addr16, A
NOT
NOT
@RW3+
addr16
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
NOT
NOT
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+ @PC+d16
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A
NOT
NOT
@RW3 @RW3+d16
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
+B
XOR
NOT
NOT
R7, A @RW7+d8, A
R7 @RW7+d8
XOR
NOT
NOT
R6, A @RW6+d8, A
R6 @RW6+d8
XOR
NOT
NOT
R5, A @RW5+d8, A
R5 @RW5+d8
XOR
NOT
NOT
R4, A @RW4+d8, A
R4 @RW4+d8
XOR
NOT
NOT
R3, A @RW3+d8, A
R3 @RW3+d8
XOR
R2, A @RW2+d8,A
XOR
NOT
NOT
R1, A @RW1+d8, A
R1 @RW1+d8
NOT
NOT
@RW2 @RW2+d16
XOR
F0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
NEG A,
AND
AND
OR
OR
R7 @RW7+d8
R7, A @RW7+d8, A
R7, A @RW7+d8, A
XOR
XOR
XOR
XOR
XOR
XOR
E0
XOR
NOT
NOT
R0, A @RW0+d8, A
R0 @RW0+d8
D0
+A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R7, A @RW7+d8, A
R7, A @RW7+d8, A
A, R7 @RW7+d8
ADD
NEG A,
AND
AND
OR
OR
R6 @RW6+d8
R6, A @RW6+d8, A
R6, A @RW6+d8, A
NEG A,
AND
AND
OR
OR
R5 @RW5+d8
R5, A @RW5+d8, A
R5, A @RW5+d8, A
NEG A,
AND
AND
OR
OR
R4 @RW4+d8
R4, A @RW4+d8, A
R4, A @RW4+d8, A
NEG A,
AND
AND
OR
OR
R3 @RW3+d8
R3, A @RW3+d8, A
R3, A @RW3+d8, A
NEG A,
AND
AND
OR
OR
R2 @RW2+d8
R2, A @RW2+d8,A
R2, A @RW2+d8,A
NEG A,
AND
AND
OR
OR
R1 @RW1+d8
R1, A @RW1+d8, A
R1, A @RW1+d8, A
XOR
C0
NOT
NOT
@RW1 @RW1+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R6, A @RW6+d8, A
R6, A @RW6+d8, A
A, R6 @RW6+d8
ADD
B0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R5, A @RW5+d8, A
R5, A @RW5+d8, A
A, R5 @RW5+d8
ADD
A0
+9
ADD
SUB
SUB
SUBC
SUBC A, NEG
R4, A @RW4+d8, A
R4, A @RW4+d8, A
A, R4 @RW4+d8
ADD
90
NOT
NOT
@RW0 @RW0+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R3, A @RW3+d8, A
R3, A @RW3+d8, A
A, R3 @RW3+d8
ADD
80
NEG A,
AND
AND
OR
OR
R0 @RW0+d8
R0, A @RW0+d8, A
R0, A @RW0+d8, A
70
ADD
ADD
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R2, A @RW2+d8,A
R2, A @RW2+d8,A
A, R2 @RW2+d8
60
ADD
50
ADD
SUB
SUB
SUBC
SUBC A, NEG
R1, A @RW1+d8, A
R1, A @RW1+d8, A
A, R1 @RW1+d8
40
ADD
30
ADD
SUB
SUB
SUBC
SUBC A, NEG
R0, A @RW0+d8, A
R0, A @RW0+d8, A
A, R0 @RW0+d8
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX
Table A.9-11 ea Instruction 6 (First Byte = 75H)
ADDW A, SUBW
ADDW
ADDCW
CMPW
ADDCW A, CMPW
ADDCW A,
ANDW
CMPW A, ANDW
CMPW A,
ORW
ORW
ANDW A, ORW
ANDW A,
ANDW A,
ORW
ORW
ORW
A,
A,
A, XORW
XORW A, DWBNZ
DWBNZ
+F A,@RW3+
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
addr 16 A,@RW3+ addr 16
A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr16 A,@RW3+
addr 16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r @PC+d16,r
SUBW A, ADDCW
SUBW A,
ANDW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW1+ @RW1+RW7 @RW1+, r @RW1+RW7,r
SUBW
ADDW A,
ADDW
CMPW A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
CMPW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW0+ @RW0+RW7 @RW0+, r @RW0+RW7,r
ADDCW A,
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ADDCW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW3 @RW3+d16 @RW3, r @RW3+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
SUBW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW2 @RW2+d16 @RW2, r @RW2+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
SUBW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW1 @RW1+d16 @RW1, r @RW1+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADDW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW0 @RW0+d16 @RW0, r @RW0+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
ADDW
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, r @RW7+d8,r
F0
+7
E0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, r @RW6+d8,r
D0
+6
C0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, r @RW5+d8,r
B0
+5
A0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, r @RW4+d8,r
90
+4
80
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, r @RW3+d8,r
70
+3
60
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, r @RW2+d8,r
50
+2
40
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, r @RW1+d8,r
30
+1
20
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, r @RW0+d8,r
10
+0
00
APPENDIX A Instructions
Table A.9-12 ea Instruction 7 (First Byte = 76H)
615
616
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
@RW3 @RW3+d16
SUBW
SUBW
@RW3+, A addr16, A
ADDW
ADDW
@RW3+, A addr16, A
+F
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
ORW
ORW
@RW3+, A addr16, A
XORW
XORW
@RW3+, A addr16, A
NOTW
NOTW
@RW3+
addr16
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
@RW2+ @PC+d16
SUBW
SUBW
@RW2+, A @PC+d16,A
ADDW
ADDW
@RW2+, A @PC+d16,A
+E
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+ @RW1+RW7
SUBCW
+D
SUBW
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+ @RW0+RW7
SUBW
SUBCW
+C
ADDW
ADDW
SUBW
SUBCW A,
+B @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
SUBW
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
@RW2 @RW2+d16
ADDW
ADDW
SUBW
+A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
SUBW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
@RW1 @RW1+d16
ADDW
ADDW
SUBCW A,
+9 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
@RW0 @RW0+d16
SUBW
NOTW
NOTW
RW7 @RW7+d8
NOTW
NOTW
RW6 @RW6+d8
NOTW
NOTW
RW5 @RW5+d8
+8 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
SUBW
XORW
XORW
RW7, A @RW7+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
A, RW7 @RW7+d8
RW7 @RW7+d8
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
+7
ADDW
XORW
XORW
RW6, A @RW6+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
A, RW6 @RW6+d8
RW6 @RW6+d8
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
+6
ADDW
XORW
XORW
RW5, A @RW5+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
A, RW5 @RW5+d8
RW5 @RW5+d8
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
+5
NOTW
NOTW
RW4 @RW4+d8
XORW
XORW
RW4, A @RW4+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
A, RW4 @RW4+d8
RW4 @RW4+d8
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
+4
F0
NOTW
NOTW
RW0 @RW0+d8
E0
NOTW
NOTW
RW3 @RW3+d8
D0
XORW
XORW
RW3, A @RW3+d8, A
C0
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
A, RW3 @RW3+d8
RW3 @RW3+d8
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
B0
+3
A0
NOTW
NOTW
RW2 @RW2+d8
90
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
A, RW2 @RW2+d8
RW2 @RW2+d8
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
80
+2
70
NOTW
NOTW
RW1 @RW1+d8
60
XORW
XORW
RW1, A @RW1+d8, A
50
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
A, RW1 @RW1+d8
RW1 @RW1+d8
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
40
+1
30
XORW
XORW
RW0, A @RW0+d8, A
20
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
A, RW0 @RW0+d8
RW0 @RW0+d8
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
10
+0
00
APPENDIX
Table A.9-13 ea Instruction 8 (First Byte = 77H)
DIV
DIV
A, DIVW
DIVW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
DIV
DIV
A, DIVW
DIVW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW MULUW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MULU
MULU A, MULUW MULUW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MULU
MULU A, MULUW MULUW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
+9
+A
+B
+C
+D
+E
+F A, @RW3+
MULU
DIV
DIV
A, DIVW
DIVW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
addr16 A,@RW3+ addr16
A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
A, DIVW
DIVW A,
addr16 A,@RW3+
addr16
DIV
DIV
A, DIVW
DIVW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
F0
+7
E0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
D0
+6
C0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
B0
+5
A0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
90
+4
80
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
70
+3
60
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
50
+2
40
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
30
+1
20
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
10
+0
00
APPENDIX A Instructions
Table A.9-14 ea Instruction 9 (First Byte = 78H)
617
618
MOVEA
MOVEA RW1
RW1,RW4 ,@RW4+d8
MOVEA
MOVEA RW1
RW1,RW5 ,@RW5+d8
MOVEA
MOVEA RW1
RW1,RW6 ,@RW6+d8
MOVEA
MOVEA RW1
RW1,RW7 ,@RW7+d8
MOVEA
MOVEA RW1
RW1,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,@RW1 ,@RW1+d16
MOVEA
MOVEA RW1
RW1,@RW2 ,@RW2+d16
MOVEA
MOVEA RW1
RW1,@RW3 ,@RW3+d16
MOVEA
MOVEA RW0
RW0,RW4 ,@RW4+d8
MOVEA
MOVEA RW0
RW0,RW5 ,@RW5+d8
MOVEA
MOVEA RW0
RW0,RW6 ,@RW6+d8
MOVEA
MOVEA RW0
RW0,RW7 ,@RW7+d8
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
+4
+5
+6
+7
50
70
90
B0
C0
D0
F0
MOVEA
MOVEA RW3
RW3,@RW2+ ,@PC+d16
MOVEA
MOVEA RW4
RW4,@RW2+ ,@PC+d16
MOVEA
MOVEA RW7
RW7,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
RW6,@RW3+ RW6, addr16 [email protected]+ RW7, addr16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2+ ,@PC+d16
RW6,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
RW0,@RW3+ RW0, addr16 RW1,@RW3+ RW1, addr16 RW2,@RW3+ RW2, addr16 RW3,@RW3+ RW3, addr16 RW4,@RW3+ RW4, addr16 RW5,@RW3+ RW5, addr16
MOVEA
MOVEA RW2
RW2,@RW2+ ,@PC+d16
+F
MOVEA
MOVEA RW1
RW1,@RW2+ ,@PC+d16
MOVEA
MOVEA RW0
RW0,@RW2+ ,@PC+d16
MOVEA RW1
+E
MOVEA
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW5,@RW1+ ,@RW1+RW7 RW6,@RW1+ ,@RW1+RW7 RW7,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW7
RW7,@RW3 ,@RW3+d16
MOVEA
MOVEA RW7
RW7,@RW2 ,@RW2+d16
MOVEA
MOVEA RW7
RW7,@RW1 ,@RW1+d16
MOVEA
MOVEA RW7
RW7,@RW0 ,@RW0+d16
MOVEA
MOVEA RW7
RW7,RW7 ,@RW7+d8
MOVEA
MOVEA RW7
RW7,RW6 ,@RW6+d8
MOVEA
MOVEA RW7
RW7,RW5 ,@RW5+d8
MOVEA
MOVEA RW7
RW7,RW4 ,@RW4+d8
MOVEA
MOVEA RW7
RW7,RW3 ,@RW3+d8
MOVEA
MOVEA RW7
RW7,RW2 ,@RW2+d8
MOVEA
MOVEA RW7
RW7,RW1 ,@RW1+d8
MOVEA
MOVEA RW7
RW7,RW0 ,@RW0+d8
E0
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4
RW2,@RW1+ ,@RW1+RW7 RW3,@RW1+ ,@RW1+RW7 RW4,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW3 ,@RW3+d16 RW6,@RW3 ,@RW3+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2 ,@RW2+d16 RW6,@RW2 ,@RW2+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW1 ,@RW1+d16 RW6,@RW1 ,@RW1+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW0 ,@RW0+d16 RW6,@RW0 ,@RW0+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW7 ,@RW7+d8
RW6,RW7 ,@RW7+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW6 ,@RW6+d8
RW6,RW6 ,@RW6+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW5 ,@RW5+d8
RW6,RW5 ,@RW5+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW4 ,@RW4+d8
RW6,RW4 ,@RW4+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW3 ,@RW3+d8
RW6,RW3 ,@RW3+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW2 ,@RW2+d8
RW6,RW2 ,@RW2+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW1 ,@RW1+d8
RW6,RW1 ,@RW1+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW0 ,@RW0+d8
RW6,RW0 ,@RW0+d8
A0
+D RW0,@RW1+ ,@RW1+RW7 RW1,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW4
RW4,@RW3 ,@RW3+d16
MOVEA
MOVEA RW4
RW4,@RW2 ,@RW2+d16
MOVEA
MOVEA RW4
RW4,@RW1 ,@RW1+d16
MOVEA
MOVEA RW4
RW4,@RW0 ,@RW0+d16
MOVEA
MOVEA RW4
RW4,RW7 ,@RW7+d8
MOVEA
MOVEA RW4
RW4,RW6 ,@RW6+d8
MOVEA
MOVEA RW4
RW4,RW5 ,@RW5+d8
MOVEA
MOVEA RW4
RW4,RW4 ,@RW4+d8
MOVEA
MOVEA RW4
RW4,RW3 ,@RW3+d8
MOVEA
MOVEA RW4
RW4,RW2 ,@RW2+d8
MOVEA
MOVEA RW4
RW4,RW1 ,@RW1+d8
MOVEA
MOVEA RW4
RW4,RW0 ,@RW0+d8
80
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW5,@RW0+ ,@RW0+RW7 RW6,@RW0+ ,@RW0+RW7 RW7,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW3
RW3,@RW3 ,@RW3+d16
MOVEA
MOVEA RW3
RW3,@RW2 ,@RW2+d16
MOVEA
MOVEA RW3
RW3,@RW1 ,@RW1+d16
MOVEA
MOVEA RW3
RW3,@RW0 ,@RW0+d16
MOVEA
MOVEA RW3
RW3,RW7 ,@RW7+d8
MOVEA
MOVEA RW3
RW3,RW6 ,@RW6+d8
MOVEA
MOVEA RW3
RW3,RW5 ,@RW5+d8
MOVEA
MOVEA RW3
RW3,RW4 ,@RW4+d8
MOVEA
MOVEA RW3
RW3,RW3 ,@RW3+d8
MOVEA
MOVEA RW3
RW3,RW2 ,@RW2+d8
MOVEA
MOVEA RW3
RW3,RW1 ,@RW1+d8
MOVEA
MOVEA RW3
RW3,RW0 ,@RW0+d8
60
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4
RW2,@RW0+ ,@RW0+RW7 RW3,@RW0+ ,@RW0+RW7 RW4,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW2
RW2,@RW3 ,@RW3+d16
MOVEA
MOVEA RW2
RW2,@RW2 ,@RW2+d16
MOVEA
MOVEA RW2
RW2,@RW1 ,@RW1+d16
MOVEA
MOVEA RW2
RW2,@RW0 ,@RW0+d16
MOVEA
MOVEA RW2
RW2,RW7 ,@RW7+d8
MOVEA
MOVEA RW2
RW2,RW6 ,@RW6+d8
MOVEA
MOVEA RW2
RW2,RW5 ,@RW5+d8
MOVEA
MOVEA RW2
RW2,RW4 ,@RW4+d8
MOVEA
MOVEA RW2
RW2,RW3 ,@RW3+d8
MOVEA
MOVEA RW2
RW2,RW2 ,@RW2+d8
MOVEA
MOVEA RW2
RW2,RW1 ,@RW1+d8
MOVEA
MOVEA RW2
RW2,RW0 ,@RW0+d8
40
+C RW0,@RW0+ ,@RW0+RW7 RW1,@RW0+ ,@RW0+RW7
+B RW0,@RW3 ,@RW3+d16
+A RW0,@RW2 ,@RW2+d16
+9 RW0,@RW1 ,@RW1+d16
MOVEA RW1
MOVEA
MOVEA RW1
RW1,RW3 ,@RW3+d8
MOVEA
MOVEA RW0
RW0,RW3 ,@RW3+d8
+3
MOVEA
MOVEA
MOVEA RW1
RW1,RW2 ,@RW2+d8
MOVEA
MOVEA RW0
RW0,RW2 ,@RW2+d8
+2
+8 RW0,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,RW1 ,@RW1+d8
MOVEA
MOVEA RW0
RW0,RW1 ,@RW1+d8
+1
30
MOVEA
MOVEA RW1
RW1,RW0 ,@RW0+d8
20
MOVEA
MOVEA RW0
RW0,RW0 ,@RW0+d8
10
+0
00
APPENDIX
Table A.9-15 MOVEA RWi, ea Instruction (First Byte = 79H)
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW2 @RW2+d16 R1,@RW2 @RW2+d16 R2,@RW2 @RW2+d16 R3,@RW2 @RW2+d16 R4,@RW2 @RW2+d16 R5,@RW2 @RW2+d16 R6,@RW2 @RW2+d16 R7,@RW2 @RW2+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW3+
addr16 @RW3+
addr16
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16
@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX A Instructions
Table A.9-16 MOV Ri, ea Instruction (First Byte = 7AH)
619
620
MOVW
MOVW RW5,
RW5,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW1 @RW1+d16 RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16 RW3,@RW1 @RW1+d16 RW4,@RW1 @RW1+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW2 @RW2+d16 RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16 RW3,@RW2 @RW2+d16 RW4,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW3 @RW3+d16 RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16 RW3,@RW3 @RW3+d16 RW4,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4, MOVW
MOVW RW5, MOVW
MOVW RW6, MOVW
MOVW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, @RW2+ @PC+d16
RW2, @RW2+ @PC+d16
RW3, @RW2+ @PC+d16
RW4, @RW2+ @PC+d16
MOVW
MOVW
RW1, @RW3+ RW1, addr16
MOVW
RW0, @RW1+
MOVW
MOVW
RW0, @RW2+ @PC+d16
MOVW
MOVW
RW0, @RW3+ RW0, addr16
+9
+A
+B
+C
+D
+E
+F
MOVW
MOVW
RW2, @RW3+ RW2, addr16
MOVW
MOVW
RW3, @RW3+ RW3, addr16
MOVW
MOVW
RW5, @RW3+ RW5, addr16
MOVW
MOVW
RW5, @RW2+ @PC+d16
MOVW
MOVW
RW6, @RW3+ RW6, addr16
MOVW
MOVW RW6,
RW6, @RW2+ @PC+d16
MOVW
MOVW
RW7, @RW3+ RW7, addr16
MOVW
MOVW RW7,
RW7, @RW2+ @PC+d16
MOVW RW7,
@RW1+RW7
MOVW
MOVW RW7,
RW7,@RW3 @RW3+d16
MOVW
MOVW RW7,
RW7,@RW2 @RW2+d16
MOVW
MOVW RW7,
RW7,@RW1 @RW1+d16
MOVW
MOVW RW7,
RW7,@RW0 @RW0+d16
MOVW
MOVW RW7,
RW7, RW7 @RW7+d8
MOVW
MOVW RW7,
RW7, RW6 @RW6+d8
MOVW
MOVW RW7,
RW7, RW5 @RW5+d8
MOVW
MOVW RW7,
RW7, RW4 @RW4+d8
MOVW RW6, MOVW
@RW1+RW7 RW7, @RW1+
MOVW
MOVW RW6,
RW6,@RW3 @RW3+d16
MOVW
MOVW RW6,
RW6,@RW2 @RW2+d16
MOVW
MOVW RW6,
RW6,@RW1 @RW1+d16
MOVW
MOVW RW6,
RW6,@RW0 @RW0+d16
MOVW
MOVW RW6,
RW6, RW7 @RW7+d8
MOVW
MOVW RW6,
RW6, RW6 @RW6+d8
MOVW
MOVW RW6,
RW6, RW5 @RW5+d8
MOVW
MOVW RW6,
RW6, RW4 @RW4+d8
MOVW
MOVW
@RW1+RW7 RW6, @RW1+
MOVW
MOVW RW5,
RW5, RW6 @RW6+d8
MOVW
MOVW RW5,
RW5, RW5 @RW5+d8
MOVW RW4, MOVW
@RW1+RW7 RW5, @RW1+
MOVW
MOVW
RW4, @RW3+ RW4, addr16
MOVW RW3, MOVW
@RW1+RW7 RW4, @RW1+
MOVW
MOVW RW5,
RW5,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW0 @RW0+d16 RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16 RW3,@RW0 @RW0+d16 RW4,@RW0 @RW0+d16
+8
MOVW RW2, MOVW
@RW1+RW7 RW3, @RW1+
MOVW
MOVW RW5,
RW5,@RW1 @RW1+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
MOVW
MOVW
RW0, RW7 @RW7+d8
+7
MOVW RW1, MOVW
@RW1+RW7 RW2, @RW1+
MOVW
MOVW RW5,
RW5,@RW0 @RW0+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
MOVW
MOVW
RW0, RW6 @RW6+d8
+6
MOVW
MOVW
@RW1+RW7 RW1, @RW1+
MOVW
MOVW RW5,
RW5, RW7 @RW7+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
MOVW
MOVW
RW0, RW5 @RW5+d8
+5
MOVW
MOVW RW5,
RW5, RW4 @RW4+d8
MOVW
MOVW RW7,
RW7, RW3 @RW3+d8
MOVW
MOVW RW7,
RW7, RW2 @RW2+d8
MOVW
MOVW RW7,
RW7, RW1 @RW1+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
MOVW
MOVW RW6,
RW6, RW3 @RW3+d8
MOVW
MOVW RW6,
RW6, RW2 @RW2+d8
MOVW
MOVW RW6,
RW6, RW1 @RW1+d8
MOVW
MOVW
RW0, RW4 @RW4+d8
MOVW
MOVW RW5,
RW5, RW3 @RW3+d8
MOVW
MOVW RW5,
RW5, RW2 @RW2+d8
MOVW
MOVW RW5,
RW5, RW1 @RW1+d8
+4
F0
MOVW
MOVW RW7,
RW7, RW0 @RW0+d8
E0
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
D0
MOVW
MOVW RW6,
RW6, RW0 @RW0+d8
C0
MOVW
MOVW
RW0, RW3 @RW3+d8
B0
MOVW
MOVW RW5,
RW5, RW0 @RW0+d8
A0
+3
90
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
80
MOVW
MOVW
RW0, RW2 @RW2+d8
70
+2
60
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
50
MOVW
MOVW
RW0, RW1 @RW1+d8
40
+1
30
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
20
MOVW
MOVW
RW0, RW0 @RW0+d8
10
+0
00
APPENDIX
Table A.9-17 MOVW RWi, ea Instruction (First Byte = 7BH)
+F
+E
+D
+C
+B
+A
+9
+8
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R1 addr16, R1
MOV
MOV
@RW3+, R0 addr16, R0
MOV
MOV
MOV
@RW2+, R1 @PC+d16, R1
@RW2+, R0 @PC+d16, R0
MOV
MOV
MOV
MOV
MOV
@RW0+, R1 @RW0+RW7, R1
MOV
@RW3, R1 @RW3+d16, R1
MOV
@RW2, R1 @RW2+d16, R1
MOV
@RW1, R1 @RW1+d16, R1
MOV
@RW1+, R1 @RW1+RW7, R1
MOV
MOV
@RW0, R1 @RW0+d16, R1
MOV
@RW1+, R0 @RW1+RW7, R0
MOV
@RW0+, R0 @RW0+RW7, R0
MOV
@RW3, R0 @RW3+d16, R0
MOV
@RW2, R0 @RW2+d16, R0
MOV
@RW1, R0 @RW1+d16, R0
MOV
@RW0, R0 @RW0+d16, R0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R2 addr16, R2
MOV
@RW2+, R2 @PC+d16, R2
MOV
@RW1+, R2 @RW1+RW7, R2
MOV
@RW0+, R2 @RW0+RW7, R2
MOV
@RW3, R2 @RW3+d16, R2
MOV
@RW2, R2 @RW2+d16, R2
MOV
@RW1, R2 @RW1+d16, R2
MOV
@RW0, R2 @RW0+d16, R2
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R3 addr16, R3
MOV
@RW2+, R3 @PC+d16, R3
MOV
@RW1+, R3 @RW1+RW7, R3
MOV
@RW0+, R3 @RW0+RW7, R3
MOV
@RW3, R3 @RW3+d16, R3
MOV
@RW2, R3 @RW2+d16, R3
MOV
@RW1, R3 @RW1+d16, R3
MOV
@RW0, R3 @RW0+d16, R3
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R4 addr16, R4
MOV
@RW2+, R4 @PC+d16, R4
MOV
@RW1+, R4 @RW1+RW7, R4
MOV
@RW0+, R4 @RW0+RW7, R4
MOV
@RW3, R4 @RW3+d16, R4
MOV
@RW2, R4 @RW2+d16, R4
MOV
@RW1, R4 @RW1+d16, R4
MOV
@RW0, R4 @RW0+d16, R4
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R5 addr16, R5
MOV
@RW2+, R5 @PC+d16, R5
MOV
@RW1+, R5 @RW1+RW7, R5
MOV
@RW0+, R5 @RW0+RW7, R5
MOV
@RW3, R5 @RW3+d16, R5
MOV
@RW2, R5 @RW2+d16, R5
MOV
@RW1, R5 @RW1+d16, R5
MOV
@RW0, R5 @RW0+d16, R5
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R6 addr16, R6
MOV
@RW2+, R6 @PC+d16, R6
MOV
@RW1+, R6 @RW1+RW7, R6
MOV
@RW0+, R6 @RW0+RW7, R6
MOV
@RW3, R6 @RW3+d16, R6
MOV
@RW2, R6 @RW2+d16, R6
MOV
@RW1, R6 @RW1+d16, R6
MOV
@RW0, R6 @RW0+d16,
R6
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R7 addr16, R7
MOV
@RW2+, R7 @PC+d16, R7
MOV
@RW1+, R7 @RW1+RW7, R7
MOV
@RW0+, R7 @RW0+RW7, R7
MOV
@RW3, R7 @RW3+d16, R7
MOV
@RW2, R7 @RW2+d16, R7
MOV
@RW1, R7 @RW1+d16, R7
MOV
@RW0, R7 @RW0+d16, R7
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R7, R0 @RW7+d8, R0
R7, R1 @RW7+d8, R1
R7, R2 @RW7+d8, R2
R7, R3 @RW7+d8, R3
R7, R4 @RW7+d8, R4
R7, R5 @RW7+d8, R5
R7, R6 @RW7+d8, R6
R7, R7 @RW7+d8, R7
F0
+7
E0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R6, R0 @RW6+d8, R0
R6, R1 @RW6+d8, R1
R6, R2 @RW6+d8, R2
R6, R3 @RW6+d8, R3
R6, R4 @RW6+d8, R4
R6, R5 @RW6+d8, R5
R6, R6 @RW6+d8, R6
R6, R7 @RW6+d8, R7
D0
+6
C0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R5, R0 @RW5+d8, R0
R5, R1 @RW5+d8, R1
R5, R2 @RW5+d8, R2
R5, R3 @RW5+d8, R3
R5, R4 @RW5+d8, R4
R5, R5 @RW5+d8, R5
R5, R6 @RW5+d8, R6
R5, R7 @RW5+d8, R7
B0
+5
A0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R4, R0 @RW4+d8, R0
R4, R1 @RW4+d8, R1
R4, R2 @RW4+d8, R2
R4, R3 @RW4+d8, R3
R4, R4 @RW4+d8, R4
R4, R5 @RW4+d8, R5
R4, R6 @RW4+d8, R6
R4, R7 @RW4+d8, R7
90
+4
80
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R3, R0 @RW3+d8, R0
R3, R1 @RW3+d8, R1
R3, R2 @RW3+d8, R2
R3, R3 @RW3+d8, R3
R3, R4 @RW3+d8, R4
R3, R5 @RW3+d8, R5
R3, R6 @RW3+d8, R6
R3, R7 @RW3+d8, R7
70
+3
60
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R2, R0 @RW2+d8, R0
R2, R1 @RW2+d8, R1
R2, R2 @RW2+d8, R2
R2, R3 @RW2+d8, R3
R2, R4 @RW2+d8, R4
R2, R5 @RW2+d8, R5
R2, R6 @RW2+d8, R6
R2, R7 @RW2+d8, R7
50
+2
40
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R1, R0 @RW1+d8, R0
R1, R1 @RW1+d8, R1
R1, R2 @RW1+d8, R2
R1, R3 @RW1+d8, R3
R1, R4 @RW1+d8, R4
R1, R5 @RW1+d8, R5
R1, R6 @RW1+d8, R6
R1, R7 @RW1+d8, R7
30
+1
20
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R0, R0 @RW0+d8, R0
R0, R1 @RW0+d8, R1
R0, R2 @RW0+d8, R2
R0, R3 @RW0+d8, R3
R0, R4 @RW0+d8, R4
R0, R5 @RW0+d8, R5
R0, R6 @RW0+d8, R6
R0, R7 @RW0+d8, R7
10
+0
00
APPENDIX A Instructions
Table A.9-18 MOV ea, Ri Instruction (First Byte = 7CH)
621
622
MOVW
[email protected]
@RW2, RW1 +d16, RW1
MOVW
[email protected]
@RW3, RW1 +d16, RW1
MOVW
[email protected]
@RW0+, RW1 +RW7,RW1
MOVW
[email protected]
@RW1+,RW1 +RW7,RW1
MOVW
[email protected]
@RW2+,RW1 +d16, RW1
MOVW
MOVW
@RW3+,RW1 addr16, RW1
MOVW
[email protected]
@RW2, RW0 +d16, RW0
MOVW
[email protected]
@RW3, RW0 +d16, RW0
MOVW
[email protected]
@RW0+,RW0 +RW7,RW0
MOVW
[email protected]
@RW1+,RW0 +RW7,RW0
MOVW
[email protected]
@RW2+,RW0 +d16, RW0
MOVW
MOVW
@RW3+,RW0 addr16, RW0
+B
+C
+D
+E
+F
MOVW
MOVW
@RW3+,RW2 addr16, RW2
MOVW
[email protected]
@RW2+,RW2 +d16, RW2
MOVW
[email protected]
@RW1+,RW2 +RW7,RW2
MOVW
[email protected]
@RW0+,RW2 +RW7,RW2
MOVW
[email protected]
@RW3, RW2 +d16, RW2
MOVW
[email protected]
@RW2, RW2 +d16, RW2
MOVW
MOVW
@RW3+,RW3 addr16, RW3
MOVW
[email protected]
@RW2+,RW3 +d16, RW3
MOVW
[email protected]
@RW1+,RW3 -+RW7,RW3
MOVW
[email protected]
@RW0+,RW3 +RW7,RW3
MOVW
[email protected]
@RW3, RW3 +d16, RW3
MOVW
[email protected]
@RW2, RW3 +d16, RW3
MOVW
[email protected]
@RW1, RW3 +d16, RW3
MOVW
MOVW
@RW3+,RW4 addr16, RW4
MOVW
[email protected]
@RW2+,RW4 +d16, RW4
MOVW
[email protected]
@RW1+,RW4 +RW7,RW4
MOVW
[email protected]
@RW0+,RW4 +RW7,RW4
MOVW
[email protected]
@RW3, RW4 +d16, RW4
MOVW
[email protected]
@RW2, RW4 +d16, RW4
MOVW
[email protected]
@RW1, RW4 +d16, RW4
MOVW
MOVW
@RW3+,RW5 addr16, RW5
MOVW
[email protected]
@RW2+,RW5 +d16, RW5
MOVW
[email protected]
@RW1+,RW5 +RW7,RW5
MOVW
[email protected]
@RW0+,RW5 +RW7,RW5
MOVW
[email protected]
@RW3, RW5 +d16, RW5
MOVW
[email protected]
@RW2, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW5 +d16, RW5
MOVW
MOVW
@RW3+,RW6 addr16, RW6
MOVW
MOVW @PC
@RW2+,RW6 +d16, RW6
MOVW
[email protected]
@RW1+,RW6 +RW7,RW6
MOVW
[email protected]
@RW0+,RW6 +RW7,RW6
MOVW
[email protected]
@RW3, RW6 +d16, RW6
MOVW
[email protected]
@RW2, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW6 +d16, RW6
MOVW
MOVW
@RW3+,RW7 addr16, RW7
MOVW
[email protected]
@RW2+,RW7 +d16, RW7
MOVW
[email protected]
@RW1+,RW7 +RW7,RW7
MOVW
[email protected]
@RW0+,RW7 +RW7,RW7
MOVW
[email protected]
@RW3, RW7 +d16, RW7
MOVW
[email protected]
@RW2, RW7 +d16, RW7
MOVW
[email protected]
@RW1, RW7 +d16, RW7
MOVW
[email protected]
@RW0, RW7 +d16, RW7
+A
MOVW
[email protected]
@RW1, RW2 +d16, RW2
MOVW
[email protected]
@RW0, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW1 +d16, RW1
MOVW
[email protected]
@RW0, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW0 +d16, RW0
MOVW
[email protected]
@RW0, RW4 +d16, RW4
+9
MOVW
[email protected]
@RW0, RW3 +d16, RW3
MOVW
[email protected]
@RW0, RW1 +d16, RW1
MOVW
[email protected]
@RW0, RW0 +d16, RW0
+8
MOVW
[email protected]
@RW0, RW2 +d16, RW2
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW7, RW0 @RW7+d8, RW0
RW7, RW1 @RW7+d8, RW1 RW7, RW2 @RW7+d8, RW2 RW7, RW3 @RW7+d8, RW3 RW7, RW4 @RW7+d8, RW4 RW7, RW5 @RW7+d8, RW5 RW7, RW6 @RW7+d8, RW6 RW7, RW7 @RW7+d8, RW7
F0
+7
E0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW6, RW0 @RW6+d8, RW0
RW6, RW1 @RW6+d8, RW1 RW6, RW2 @RW6+d8, RW2 RW6, RW3 @RW6+d8, RW3 RW6, RW4 @RW6+d8, RW4 RW6, RW5 @RW6+d8, RW5 RW6, RW6 @RW6+d8, RW6 RW6, RW7 @RW6+d8, RW7
D0
+6
C0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW5, RW0 @RW5+d8, RW0
RW5, RW1 @RW5+d8, RW1 RW5, RW2 @RW5+d8, RW2 RW5, RW3 @RW5+d8, RW3 RW5, RW4 @RW5+d8, RW4 RW5, RW5 @RW5+d8, RW5 RW5, RW6 @RW5+d8, RW6 RW5, RW7 @RW5+d8, RW7
B0
+5
A0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW4, RW0 @RW4+d8, RW0
RW4, RW1 @RW4+d8, RW1 RW4, RW2 @RW4+d8, RW2 RW4, RW3 @RW4+d8, RW3 RW4, RW4 @RW4+d8, RW4 RW4, RW5 @RW4+d8, RW5 RW4, RW6 @RW4+d8, RW6 RW4, RW7 @RW4+d8, RW7
90
+4
80
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW3, RW0 @RW3+d8, RW0
RW3, RW1 @RW3+d8, RW1 RW3, RW2 @RW3+d8, RW2 RW3, RW3 @RW3+d8, RW3 RW3, RW4 @RW3+d8, RW4 RW3, RW5 @RW3+d8, RW5 RW3, RW6 @RW3+d8, RW6 RW3, RW7 @RW3+d8, RW7
70
+3
60
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW2, RW0 @RW2+d8, RW0
RW2, RW1 @RW2+d8, RW1 RW2, RW2 @RW2+d8, RW2 RW2, RW3 @RW2+d8, RW3 RW2, RW4 @RW2+d8, RW4 RW2, RW5 @RW2+d8, RW5 RW2, RW6 @RW2+d8, RW6 RW2, RW7 @RW2+d8, RW7
50
+2
40
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW1, RW0 @RW1+d8, RW0
RW1, RW1 @RW1+d8, RW1 RW1, RW2 @RW1+d8, RW2 RW1, RW3 @RW1+d8, RW3 RW1, RW4 @RW1+d8, RW4 RW1, RW5 @RW1+d8, RW5 RW1, RW6 @RW1+d8, RW6 RW1, RW7 @RW1+d8, RW7
30
+1
20
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW0, RW0 @RW0+d8, RW0
RW0, RW1 @RW0+d8, RW1 RW0, RW2 @RW0+d8, RW2 RW0, RW3 @RW0+d8, RW3 RW0, RW4 @RW0+d8, RW4 RW0, RW5 @RW0+d8, RW5 RW0, RW6 @RW0+d8, RW6 RW0, RW7 @RW0+d8, RW7
10
+0
00
APPENDIX
Table A.9-19 MOVW ea, Rwi Instruction (First Byte = 7DH)
XCH
XCH
XCH
XCH
R1,
XCH
XCH R1,
R1,@RW2 W2+d16, A
XCH
XCH
R2,
XCH
XCH R2,
R2,@RW2 W2+d16, A
XCH
XCH
R3,
XCH
XCH R3,
R3,@RW2 W2+d16, A
XCH
XCH
R4,
XCH
XCH R4,
R4,@RW2 W2+d16, A
XCH
XCH
R5,
XCH
XCH R5,
R5,@RW2 W2+d16, A
XCH
XCH
R6,
XCH
XCH R6,
R6,@RW2 W2+d16, A
XCH
XCH
R7,
XCH
XCH R7,
R7,@RW2 W2+d16, A
XCH
XCH
XCH
XCH
XCH
R1, XCH
XCH
R2, XCH
XCH
R3, XCH
XCH
R4, XCH
XCH
R5, XCH
XCH
R6, XCH
XCH
R7,
+F R0,@RW3+ R0, addr16
XCH
XCH
R1,@RW3+ R1, addr16
XCH
XCH
R2,@RW3+ R2, addr16
XCH
XCH
R3,@RW3+ R3, addr16
XCH
XCH
R4,@RW3+ R4, addr16
XCH
XCH
R5,@RW3+ R5, addr16
XCH
XCH
R6,@RW3+ R6, addr16
XCH
XCH
R7,@RW3+ R7, addr16
+E R0,@RW2+ @PC+d16 R1,@RW2+ @PC+d16 R2,@RW2+ @PC+d16 R3,@RW2+ @PC+d16 R4,@RW2+ @PC+d16 R5,@RW2+ @PC+d16 R6,@RW2+ @PC+d16 R7,@RW2+ @PC+d16
R0, XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW1+RW7 R1,@RW1+ @RW1+RW7 R2,@RW1+ @RW1+RW7 R3,@RW1+ @RW1+RW7 R4,@RW1+ @RW1+RW7 R5,@RW1+ @RW1+RW7 R6,@RW1+ @RW1+RW7 R7,@RW1+ @RW1+RW7
+D R0,@RW1+
XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW0+RW7 R1,@RW0+ @RW0+RW7 R2,@RW0+ @RW0+RW7 R3,@RW0+ @RW0+RW7 R4,@RW0+ @RW0+RW7 R5,@RW0+ @RW0+RW7 R6,@RW0+ @RW0+RW7 R7,@RW0+ @RW0+RW7
XCH
+C R0,@RW0+
+B R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
R0,
+A R0,@RW2 W2+d16, A
R0,
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
+9
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
+8
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
F0
+7
E0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX A Instructions
Table A.9-20 XCH Ri, ea Instruction (First Byte = 7EH)
623
624
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2+ @PC+d16
RW1,@RW2+ @PC+d16
RW2,@RW2+ @PC+d16
RW3,@RW2+ @PC+d16
RW4,@RW2+ @PC+d16
RW5,@RW2+ @PC+d16
RW6,@RW2+ @PC+d16
RW7,@RW2+ @PC+d16
XCHW
XCHW
RW0,@RW3+ RW0, addr16
+E
+F
XCHW
XCHW
RW7,@RW3+ RW7, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW1+ @RW1+RW7 RW1,@RW1+ @RW1+RW7 RW2,@RW1+ @RW1+RW7 RW3,@RW1+ @RW1+RW7 RW4,@RW1+ @RW1+RW7 RW5,@RW1+ @RW1+RW7 RW6,@RW1+ @RW1+RW7 RW7,@RW1+ @RW1+RW7
+D
XCHW
XCHW
RW6,@RW3+ RW6, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
+C
XCHW
XCHW
RW5,@RW3+ RW5, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW3 @RW3+d16
RW1,@RW3 @RW3+d16
RW2,@RW3 @RW3+d16
RW3,@RW3 @RW3+d16
RW4,@RW3 @RW3+d16
RW5,@RW3 @RW3+d16
RW6,@RW3 @RW3+d16
RW7,@RW3 @RW3+d16
+B
XCHW
XCHW
RW4,@RW3+ RW4, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2 @RW2+d16
RW1,@RW2 @RW2+d16
RW2,@RW2 @RW2+d16
RW3,@RW2 @RW2+d16
RW4,@RW2 @RW2+d16
RW5,@RW2 @RW2+d16
RW6,@RW2 @RW2+d16
RW7,@RW2 @RW2+d16
+A
XCHW
XCHW
RW3,@RW3+ RW3, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW1 @RW1+d16
RW1,@RW1 @RW1+d16
RW2,@RW1 @RW1+d16
RW3,@RW1 @RW1+d16
RW4,@RW1 @RW1+d16
RW5,@RW1 @RW1+d16
RW6,@RW1 @RW1+d16
RW7,@RW1 @RW1+d16
+9
XCHW
XCHW
RW2,@RW3+ RW2, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW0 @RW0+d16
RW1,@RW0 @RW0+d16
RW2,@RW0 @RW0+d16
RW3,@RW0 @RW0+d16
RW4,@RW0 @RW0+d16
RW5,@RW0 @RW0+d16
RW6,@RW0 @RW0+d16
RW7,@RW0 @RW0+d16
+8
XCHW
XCHW
RW1,@RW3+ RW1, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW7 @RW7+d8
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
RW5, RW7 @RW7+d8
RW6, RW7 @RW7+d8
RW7, RW7 @RW7+d8
F0
+7
E0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW6 @RW6+d8
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
RW5, RW6 @RW6+d8
RW6, RW6 @RW6+d8
RW7, RW6 @RW6+d8
D0
+6
C0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW5 @RW5+d8
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
RW5, RW5 @RW5+d8
RW6, RW5 @RW5+d8
RW7, RW5 @RW5+d8
B0
+5
A0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW4 @RW4+d8
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
RW5, RW4 @RW4+d8
RW6, RW4 @RW4+d8
RW7, RW4 @RW4+d8
90
+4
80
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW3 @RW3+d8
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
RW5, RW3 @RW3+d8
RW6, RW3 @RW3+d8
RW7, RW3 @RW3+d8
70
+3
60
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW2 @RW2+d8
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
RW5, RW2 @RW2+d8
RW6, RW2 @RW2+d8
RW7, RW2 @RW2+d8
50
+2
40
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW1 @RW1+d8
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
RW5, RW1 @RW1+d8
RW6, RW1 @RW1+d8
RW7, RW1 @RW1+d8
30
+1
20
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW0 @RW0+d8
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
RW5, RW0 @RW0+d8
RW6, RW0 @RW0+d8
RW7, RW0 @RW0+d8
10
+0
00
APPENDIX
Table A.9-21 XCHW RWi, ea Instruction (First Byte = 7FH)
APPENDIX B Register Index
APPENDIX B Register Index
■ Register Index
Table B-1 Register Index (1/9)
Address
Abbreviation of
Register Name
Register Name
Reset Value
Resource Name
Page
Number
(Reserved area) *
000000H
000001H
PDR1
Port 1 data register
XXXXXXXXB
Port 1
163
000002H
PDR2
Port 2 data register
XXXXXXXXB
Port 2
168
000003H
PDR3
Port 3 data register
XXXXXXXXB
Port 3
173
000004H
PDR4
Port 4 data register
XXXXXXXXB
Port 4
178
000005H
PDR5
Port5 data register
XXXXXXXXB
Port 5
183
000006H
to
000010H
(Reserved area) *
000011H
DDR1
Port 1 direction register
00000000B
Port 1
163
000012H
DDR2
Port 2 direction register
00000000B
Port 2
168
000013H
DDR3
Port 3 direction register
000X0000B
Port 3
173
000014H
DDR4
Port 4 direction register
XXX00000B
Port 4
178
000015H
DDR5
Port 5 direction register
00000000B
Port 5
183
8/10-bit
A/D converter
358
000016H
to
00001AH
00001BH
(Reserved area) *
ADER
Analog input enable register
00001CH
to
000025H
11111111B
(Reserved area) *
000026H
SMR1
Serial mode register 1
00000000B
383
000027H
SCR1
Serial control register 1
00000100B
381
000028H
SIDR1/SODR1
Serial input data register 1/
serial output data register 1
000029H
SSR1
Serial status register 1
UART1
387
00001000B
385
(Reserved area) *
00002AH
00002BH
XXXXXXXXB
CDCR1
Communication prescaler control
register 1
0XXX0000B
UART1
389
625
APPENDIX
Table B-1 Register Index (2/9)
Address
Abbreviation of
Register Name
Register Name
00002CH
to
00002FH
Reset Value
ENIR
DTP/external interrupt enable
register
00000000B
000031H
EIRR
DTP/external interrupt factor
register
XXXXXXXXB
ELVR
Detection level setting register
000033H
000034H
000035H
000036H
000037H
ADCS
ADCR
000038H
to
00003FH
A/D control status register
328
00000000B
331
00000000B
352
XXXXXXXXB
8/10-bit
A/D converter
00101XXXB
350
357
355
(Reserved area) *
PPGC0
PPG0 operation mode control
register
0X000XX1B
000041H
PPGC1
PPG1 operation mode control
register
0X000001B
000042H
PPG01
PPG0/1 count clock select register
000000XXB
294
8/16-bit PPG
PPG timer 0/1
296
298
(Reserved area) *
000043H
000044H
PPGC2
PPG2 operation mode control
register
0X000XX1B
000045H
PPGC3
PPG3 operation mode control
register
0X000001B
000046H
PPG23
PPG2/3 count clock select register
000000XXB
626
DTP/external
interrupt
332
00000000B
A/D data register
329
00000000B
000040H
000047H
to
00004FH
Page
Number
(Reserved area) *
000030H
000032H
Resource Name
(Reserved area) *
294
8/16-bit
PPG timer 2/3
296
298
APPENDIX B Register Index
Table B-1 Register Index (3/9)
Address
000050H
Abbreviation of
Register Name
Register Name
Reset Value
IPCP0
Input capture data register 0
IPCP1
Input capture data register 1
000054H
ICS01
000055H
ICS23
Input capture control status
register
TCDT
Timer counter data register
TCCS
Timer counter control status
register
000051H
000052H
000053H
000056H
000057H
000058H
00005BH
00005CH
00005DH
IPCP2
IPCP3
00005EH
to
000065H
000066H
000067H
000068H
000069H
Input capture data register 3
XXXXXXXXB
231
XXXXXXXXB
00000000B
00000000B
16-bit
I/O timers
00000000B
228
227
00000000B
00000000B
225
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
231
16-bit
I/O timers
231
XXXXXXXXB
00000000B
Timer control status register
TMCSR1
XXXX0000B
00000000B
XXXX0000B
16-bit reload timer
0
16-bit reload timer
1
251
249
251
249
(Reserved area) *
ROMM
ROM mirroring function select
register
XXXXXXX1B
ROM mirroring
function select
module
520
CAN controller
444
CAN controller
448
(Reserved area) *
BVALR
Message buffer valid register
00000000B
(Reserved area) *
000081H
000082H
Input capture data register 2
TMCSR0
000070H
to
00007FH
000080H
231
XXXXXXXXB
(Reserved area) *
00006AH
to
00006EH
00006FH
XXXXXXXXB
Page
Number
(Reserved area) *
000059H
00005AH
Resource Name
TREQR
Transmission request register
00000000B
627
APPENDIX
Table B-1 Register Index (4/9)
Address
Abbreviation of
Register Name
Register Name
TCANR
Transmission cancel register
TCR
Transmission complete register
RCR
Reception complete register
RRTRR
CAN controller
456
CAN controller
460
CAN controller
462
CAN controller
464
CAN controller
466
00000000B
Address match
detecting function
505
XXXXXXX0B
Delayed interrupt
generation module
319
00000000B
00000000B
(Reserved area) *
ROVRR
00000000B
Reception overrun register
(Reserved area) *
00008DH
00008EH
454
00000000B
Reception RTR register
00008BH
00008CH
CAN controller
(Reserved area) *
000089H
00008AH
00000000B
(Reserved area) *
000087H
000088H
Page
Number
(Reserved area) *
000085H
000086H
Resource Name
(Reserved area) *
000083H
000084H
Reset Value
RIER
Reception complete interrupt
enable register
00008FH
to
00009DH
00000000B
(Reserved area) *
00009EH
PACSR
Address detection control register
00009FH
DIRR
Delayed interrupt request
generate/cancel register
0000A0H
LPMCR
Low-power consumption mode
control register
00011000B
Low-power
consumption mode
129
0000A1H
CKSCR
Clock select register
11111100B
Clock
114
0000A2H
to
0000A7H
(Reserved area) *
0000A8H
WDTC
Watchdog timer control register
XXXXX111B
Watchdog timer
208
0000A9H
TBTC
Timebase timer control register
1XX00100B
Timebase timer
193
0000AAH
WTC
Watch timer control register
1X001000B
Watch timer
277
512-Kbit flash
memory
524
0000ABH
to
0000ADH
0000AEH
0000AFH
628
(Reserved area) *
FMCS
Flash memory control status
register
000X0000B
(Reserved area) *
APPENDIX B Register Index
Table B-1 Register Index (5/9)
Address
Abbreviation of
Register Name
0000B0H
ICR00
Interrupt control register 00
00000111B
0000B1H
ICR01
Interrupt control register 01
00000111B
0000B2H
ICR02
Interrupt control register 02
00000111B
0000B3H
ICR03
Interrupt control register 03
00000111B
0000B4H
ICR04
Interrupt control register 04
00000111B
0000B5H
ICR05
Interrupt control register 05
00000111B
0000B6H
ICR06
Interrupt control register 06
00000111B
0000B7H
ICR07
Interrupt control register 07
00000111B
0000B8H
ICR08
Interrupt control register 08
00000111B
0000B9H
ICR09
Interrupt control register 09
00000111B
0000BAH
ICR10
Interrupt control register 10
00000111B
0000BBH
ICR11
Interrupt control register 11
00000111B
0000BCH
ICR12
Interrupt control register 12
00000111B
0000BDH
ICR13
Interrupt control register 13
00000111B
0000BEH
ICR14
Interrupt control register 14
00000111B
0000BFH
ICR15
Interrupt control register 15
00000111B
Register Name
0000C0H
to
0000FFH
Reset Value
Detect address setting register 0
(Low)
XXXXXXXXB
Detect address setting register 0
(Middle)
XXXXXXXXB
001FF2H
Detect address setting register 0
(High)
XXXXXXXXB
001FF3H
Detect address setting register 1
(Low)
XXXXXXXXB
Detect address setting register 1
(Middle)
XXXXXXXXB
Detect address setting register 1
(High)
XXXXXXXXB
001FF4H
PADR0
PADR1
001FF5H
003900H
003901H
Page
Number
Interrupt controller
66
(Reserved area) *
001FF0H
001FF1H
Resource Name
TMR0/TMRLR0
16-bit timer register 0/
16-bit reload register 0
XXXXXXXXB
XXXXXXXXB
507
Address match
detecting function
507
16-bit reload timer
0
253/254
629
APPENDIX
Table B-1 Register Index (6/9)
Address
003902H
003903H
Abbreviation of
Register Name
TMR1/TMRLR1
Register Name
16-bit timer register 1/
16-bit reload register 1
003904H
to
00390FH
Reset Value
Resource Name
Page
Number
XXXXXXXXB
16-bit reload timer
1
253/254
XXXXXXXXB
(Reserved area) *
003910H
PRLL0
PPG0 reload register L
XXXXXXXXB
300
003911H
PRLH0
PPG0 reload register H
XXXXXXXXB
300
003912H
PRLL1
PPG1 reload register L
XXXXXXXXB
300
003913H
PRLH1
PPG1 reload register H
XXXXXXXXB
003914H
PRLL2
PPG2 reload register L
XXXXXXXXB
003915H
PRLH2
PPG2 reload register H
XXXXXXXXB
300
003916H
PRLL3
PPG3 reload register L
XXXXXXXXB
300
003917H
PRLH3
PPG3 reload register H
XXXXXXXXB
300
003918H
to
00392FH
(Reserved area) *
003930H
to
003BFFH
(Reserved area) *
003C00H
to
003C0FH
RAM (general-purpose RAM)
003C10H
to
003C13H
IDR0
003C14H
to
003C17H
IDR1
300
8/16-bit PPG timer
300
ID register 0
XXXXXXXXB
to
XXXXXXXXB
473
ID register 1
XXXXXXXXB
to
XXXXXXXXB
473
003C18H
to
003C1BH
IDR2
ID register 2
XXXXXXXXB
to
XXXXXXXXB
003C1CH
to
003C1FH
IDR3
ID register 3
XXXXXXXXB
to
XXXXXXXXB
473
ID register 4
XXXXXXXXB
to
XXXXXXXXB
473
003C20H
to
003C23H
630
IDR4
CAN controller
473
APPENDIX B Register Index
Table B-1 Register Index (7/9)
Address
Abbreviation of
Register Name
003C24H
to
003C27H
IDR5
003C28H
to
003C2BH
IDR6
Register Name
Reset Value
Resource Name
Page
Number
ID register 5
XXXXXXXXB
to
XXXXXXXXB
473
ID register 6
XXXXXXXXB
to
XXXXXXXXB
473
473
003C2CH
to
003C2FH
IDR7
ID register 7
XXXXXXXXB
to
XXXXXXXXB
003C30H
003C31H
DLCR0
DLC register 0
XXXXXXXXB
XXXXXXXXB
476
003C32H
003C33H
DLCR1
DLC register 1
XXXXXXXXB
XXXXXXXXB
476
003C34H
003C35H
DLCR2
DLC register 2
XXXXXXXXB
XXXXXXXXB
476
003C36H
003C37H
DLCR3
DLC register 3
XXXXXXXXB
XXXXXXXXB
476
003C38H
003C39H
DLCR4
DLC register 4
XXXXXXXXB
XXXXXXXXB
003C3AH
003C3BH
DLCR5
DLC register 5
XXXXXXXXB
XXXXXXXXB
476
003C3CH
003C3DH
DLCR6
DLC register 6
XXXXXXXXB
XXXXXXXXB
476
003C3EH
003C3FH
DLCR7
DLC register 7
XXXXXXXXB
XXXXXXXXB
476
003C40H
to
003C47H
DTR0
Data register 0
XXXXXXXXB
to
XXXXXXXXB
477
477
CAN controller
476
003C48H
to
003C4FH
DTR1
Data register 1
XXXXXXXXB
to
XXXXXXXXB
003C50H
to
003C57H
DTR2
Data register 2
XXXXXXXXB
to
XXXXXXXXB
477
Data register 3
XXXXXXXXB
to
XXXXXXXXB
477
003C58H
to
003C5FH
DTR3
631
APPENDIX
Table B-1 Register Index (8/9)
Address
Abbreviation of
Register Name
003C60H
to
003C67H
DTR4
003C68H
to
003C6FH
DTR5
Register Name
Reset Value
Data register 4
477
Data register 5
XXXXXXXXB
to
XXXXXXXXB
477
DTR6
Data register 6
XXXXXXXXB
to
XXXXXXXXB
003C78H
to
003C7FH
DTR7
Data register 7
XXXXXXXXB
to
XXXXXXXXB
003C80H
to
003CFFH
CSR
003D02H
LEIR
0XXXX001B
00XXX000B
Control status register
Last event indicate register
RTEC
Receive/transmit error counter
00000000B
00000000B
003D06H
003D07H
BTR
Bit timing register
11111111B
X1111111B
003D08H
IDER
IDE register
003D09H
431/433
CAN controller
436
438
CAN controller
XXXXXXXXB
440
446
(Reserved area) *
TRTRR
00000000B
Transmission RTR register
CAN controller
450
CAN controller
452
CAN controller
458
CAN controller
468
(Reserved area) *
003D0BH
RFWTR
Remote frame receiving wait
register
XXXXXXXXB
(Reserved area) *
003D0DH
TIER
Transmission complete interrupt
enable register
00000000B
(Reserved area) *
003D0FH
632
477
000XX000B
003D04H
003D05H
003D10H
003D11H
477
(Reserved area) *
003D03H
003D0EH
CAN controller
(Reserved area) *
003D00H
003D01H
003D0CH
Page
Number
XXXXXXXXB
to
XXXXXXXXB
003C70H
to
003C77H
003D0AH
Resource Name
AMSR
Acceptance mask select register
XXXXXXXXB
to
XXXXXXXXB
APPENDIX B Register Index
Table B-1 Register Index (9/9)
Address
Abbreviation of
Register Name
Register Name
003D12H
003D13H
003D14H
to
003D17H
003D18H
to
003D1BH
Reset Value
Resource Name
Page
Number
(Reserved area) *
AMR0
AMR1
Acceptance mask register 0
XXXXXXXXB
to
XXXXXXXXB
Acceptance mask register 1
XXXXXXXXB
to
XXXXXXXXB
003D1CH
to
003DFFH
(Reserved area) *
003E00H
to
003EFFH
(Reserved area) *
003FF0H
to
003FFFH
(Reserved area) *
470
CAN controller
470
Explanation of reset value
0: The reset value of this bit is "0".
1: The reset value of this bit is "1".
X: The reset value of this bit is unfixed.
* : Do not write the data to "(Reserved area)". If the data is read from "(Reserved area)", it is undefined values.
633
APPENDIX
APPENDIX C Pin Function Index
■ Pin Function Index
Table C-1 Pin Function Index (1/2)
Pin
Number
Pin Name
Circuit
Type
Function
M26
Page
Number for
Block
Diagram
1
AVCC
−
VCC input pin for A/D converter
346
345
2
AVR
−
Vref + input pin for A/D converter
346
345
General-purpose I/O ports
181
182
Analog input pins for A/D converter
346
345
General-purpose I/O port
171
172
External trigger input pin for A/D converter
348
345
General-purpose I/O port
166
167
Event input pin for reload timer 0
246
244
General-purpose I/O port
166
167
Event output pin for reload timer 0
246
244
General-purpose I/O port
166
167
Event input pin for reload timer 1
246
244
General-purpose I/O ports
166
167
Event output pin for reload timer 1
246
244
General-purpose I/O ports
166
167
External interrupt input pins
327
325
3 to 10
11
12
13
14
15
16 to 19
P50 to P57
AN0 to AN7
P37
ADTG
P20
TIN0
P21
TOT0
P22
TIN1
P23
TOT1
P24 to P27
INT4 to INT7
E
D
D
D
D
D
D
20
MD2
F
Operation mode select input pin
150
−
21
MD1
C
Operation mode select input pin
150
−
22
MD0
C
Operation mode select input pin
150
−
23
RST
B
External reset input pin
99
103
24
VCC
Power (5 V) input pin
−
−
25
VSS
−
Power (0 V) input pin
−
−
26
C
−
Power stabilization capacitance pin
−
−
27
X0
A
High-speed oscillation pin
109
112
28
X1
A
High-speed oscillation pin
109
112
General-purpose I/O ports
161
162
Trigger input pins for input capture channels 0
to 3
222
220
General-purpose I/O ports
161
162
Output pins for PPG timers 01 and 23
292
288/290
P10 to P13
29 to 32
33 to 36
634
Page
Number for
Function
Explanation
IN0 to IN3
P14 to P17
PPG0 to PPG3
D
D
APPENDIX C Pin Function Index
Table C-1 Pin Function Index (2/2)
Pin
Number
Pin Name
Circuit
Type
Page
Number for
Function
Explanation
Page
Number for
Block
Diagram
General-purpose I/O port
176
177
Serial data input pin for UART1
379
376
General-purpose I/O port
176
177
Serial clock input/output pin for UART1
379
376
General-purpose I/O port
176
177
Serial data output pin for UART1
379
376
General-purpose I/O port
176
177
Transmit output pin for CAN controller
427
423
General-purpose I/O port
176
177
Receive input pin for CAN controller
427
423
General-purpose I/O port
171
172
Low-speed oscillation pin
108
111
General-purpose I/O port
171
172
Low-speed oscillation pin
108
111
General-purpose I/O port
171
172
VSS input pin for A/D converter
346
345
Function
M26
37
38
39
40
41
42 to 45
46
47
48
P40
SIN1
P41
SCK1
P42
SOT1
P43
TX
P44
RX
P30 to P33
X0A*
P35*
X1A*
P36*
AVSS
D
D
D
D
D
D
A
A
−
*:MB90387, MB90F387: X1A, X0A
MB90387S, MB90F387S: P36, P35
635
APPENDIX
APPENDIX D Interrupt Vector Index
■ Interrupt Vector Index
Table D-1 Interrupt Vector Index (1/2)
Interrupt Control
Interrupt
Number
ICR
Address
Low
Middle
High
Page
Number
#08
Reset
−
−
FFFFDCH
FFFFDDH
FFFFDEH
99
#09
INT9 instruction
−
−
FFFFD8H
FFFFD9H
FFFFDAH
502
#10
Exception processing
−
−
FFFFD4H
FFFFD5H
FFFFD6H
91
#11
CAN controller receive
completion
FFFFD0H
FFFFD1H
FFFFD2H
#12
CAN controller receive
completion/
node status transition
FFFFCCH
FFFFCDH
FFFFCEH
478
#13
Reserved
FFFFC8H
FFFFC9H
FFFFCAH
−
FFFFC4H
FFFFC5H
FFFFC6H
−
FFFFC0H
FFFFC1H
FFFFC2H
62
FFFFBCH
FFFFBDH
FFFFBEH
195
FFFFB8H
FFFFB9H
FFFFBAH
255
FFFFB4H
FFFFB5H
FFFFB6H
360
FFFFB0H
FFFFB1H
FFFFB2H
232
ICR00
ICR01
#14
Reserved
#15
CAN wake-up
ICR02
#16
Timebase timer
#17
16-bit reload timer 0
ICR03
#18
8/10-bit A/D converter
#19
16-bit free-run timer
overflow
ICR04
478
0000B0H
0000B1H
0000B2H
0000B3H
0000B4H
#20
Reserved
FFFFACH
FFFFADH
FFFFAEH
−
#21
Reserved
FFFFA8H
FFFFA9H
FFFFAAH
−
#22
PPG timer channel 0/1
underflow
FFFFA4H
FFFFA5H
FFFFA6H
301
#23
Input capture 0 fetched
FFFFA0H
FFFFA1H
FFFFA2H
232
#24
External interrupt 4 (INT4)/
external interrupt 5 (INT5)
FFFF9CH
FFFF9DH
FFFF9EH
324
#25
Input capture 1 fetched
FFFF98H
FFFF99H
FFFF9AH
232
#26
PPG timer channel 2/3
underflow
FFFF94H
FFFF95H
FFFF96H
301
#27
External interrupt 6 (INT6)/
external interrupt 7 (INT7)
FFFF90H
FFFF91H
FFFF92H
324
FFFF8CH
FFFF8DH
FFFF8EH
279
#28
636
Address in Vector Table
Interrupt Factor
Watch timer
ICR05
ICR06
ICR07
ICR08
0000B5H
0000B6H
0000B7H
0000B8H
APPENDIX D Interrupt Vector Index
Table D-1 Interrupt Vector Index (2/2)
Interrupt
Number
Interrupt Control
Address in Vector Table
Interrupt Factor
ICR
#29
Reserved
#30
Input capture 2 fetched
Input capture 3 fetched
#31
Reserved
ICR09
ICR10
#32
Reserved
#33
Reserved
ICR11
#34
Reserved
#35
Reserved
ICR12
#36
16-bit reload timer 1
#37
UART1 receive
ICR13
#38
UART1 transmit
#39
Reserved
ICR14
#40
Reserved
#41
Flash memory
#42
Delayed interrupt generation
module
ICR15
Address
0000B9H
0000BAH
0000BBH
0000BCH
0000BDH
0000BEH
0000BFH
Page
Number
Low
Middle
High
FFFF88H
FFFF89H
FFFF8AH
−
FFFF84H
FFFF85H
FFFF86H
232
FFFF80H
FFFF81H
FFFF82H
−
FFFF7CH
FFFF7DH
FFFF7EH
−
FFFF78H
FFFF79H
FFFF7AH
−
FFFF74H
FFFF75H
FFFF76H
−
FFFF70H
FFFF71H
FFFF72H
−
FFFF6CH
FFFF6DH
FFFF6EH
255
FFFF68H
FFFF69H
FFFF6AH
391
FFFF64H
FFFF65H
FFFF66H
391
FFFF60H
FFFF61H
FFFF62H
−
FFFF5CH
FFFF5DH
FFFF5EH
−
FFFF58H
FFFF59H
FFFF5AH
522
FFFF54H
FFFF55H
FFFF56H
316
637
APPENDIX
638
INDEX
The index follows on the next page.
This is listed in alphabetic order.
639
INDEX
Index
Numerics
16-bit Free-run Timer
Block Diagram of 16-bit Free-run Timer ........... 218
Operation of 16-bit Free-run Timer ................... 233
Operation Timing of 16-bit Free-run Timer........ 234
Setting of 16-bit Free-run Timer ....................... 233
16-bit Input/Output Timer
16-bit Input/Output Timer Interrupts and EI2OS
Function ............................................ 232
Block Diagram of 16-bit Input/Output Timer
......................................................... 217
Block Diagram of Pins for 16-bit Input/Output Timer
......................................................... 222
Configuration of 16-bit Input/Output Timer
......................................................... 216
Correspondence between 16-bit Input/Output Timer
Interrupt and EI2OS............................ 232
Functions of 16-bit Input/Output Timer ............. 216
Generation of Interrupt Request from 16-bit Input/
Output Timer ..................................... 224
Interrupt Control Bits and Interrupt Factors of 16-bit
Input/Output Timer............................. 232
List of Registers and Reset Values of 16-bit Input/
Output Timer ..................................... 223
Pins of 16-bit Input/Output Timer ..................... 222
Precautions when 16-bit Input/Output Timer
......................................................... 238
16-bit PPG Output Operation Mode
Setting for 16-bit PPG Output Operation Mode
......................................................... 306
16-bit Reload Registers
16-bit Reload Registers (TMRLR0,TMRLR1)
......................................................... 254
16-bit Reload Timer
Baud Rate by Internal Timer
(16-bit Reload Timer Output) .............. 401
Block Diagram for Pins of 16-bit Reload Timer
......................................................... 246
Block Diagram of 16-bit Reload Timer.............. 244
Correspondence between 16-bit Reload Timer
Interrupt and EI2OS............................ 255
2
EI OS Function of 16-bit Reload Timer............. 255
Generation of Interrupt Request from 16-bit Reload
Timer ................................................ 248
Interrupts of 16-bit Reload Timer...................... 255
List of Registers and Reset Values of 16-bit Reload
Timer ................................................ 247
Operation Modes of 16-bit Reload Timer........... 242
Pins of 16-bit Reload Timer ............................. 246
640
Precautions when Using 16-bit Reload Timer
.........................................................266
Setting of 16-bit Reload Timer ..........................256
16-bit Timer Register
16-bit Timer Registers (TMR0,TMR1) ..............253
Operating State of 16-bit Timer Register ............257
Operation as 16-bit Timer Register Underflows
.................................................259, 264
24-bit Operand
Linear Addressing by Specifying 24-bit Operand
...........................................................28
2-channel Independent Operation Mode
Setting for 8-bit PPG Output 2-channel Independent
Operation Mode..................................304
32-bit Register
Addressing by Indirect-specifying 32-bit Register
...........................................................28
512 Kbit Flash Memory
Features of 512 Kbit Flash Memory...................522
Overview of 512 Kbit Flash Memory.................522
Program Example of 512 Kbit Flash Memory
.........................................................547
Sector Configuration of 512 Kbit Flash Memory
.........................................................523
8+8-bit PPG Output Operation Mode
Setting for 8+8-bit PPG Output Operation Mode
.........................................................309
8-/10-bit A/D Converter
8-/10-bit A/D Converter Interrupt and EI2OS
.........................................................360
A/D-converted Data Protection Function in 8-/10-bit
A/D Converter ....................................369
Block Diagram of 8-/10-bit A/D Converter.........345
Conversion Modes of 8-/10-bit A/D Converter
.........................................................344
EI2OS Function of 8-/10-bit A/D Converter........360
Function of 8-/10-bit A/D Converter ..................344
Generation of Interrupt from 8-/10-bit A/D Converter
.........................................................349
List of Registers and Reset Values of 8-/10-bit A/D
Converter ...........................................349
Pins of 8-/10-bit A/D Converter ........................348
Precautions when Using 8-/10-bit A/D Converter
.........................................................371
8-/16-bit PPG Timer
8-/16-bit PPG Timer Interrupt and EI2OS Function
.........................................................302
Block Diagram of 8-/16-bit PPG Timer 0 ...........288
Block Diagram of 8-/16-bit PPG Timer 1 ...........290
INDEX
Block Diagram of 8-/16-bit PPG Timer Pins
..........................................................292
Correspondence between 8-/16-bit PPG Timer
Interrupt and EI2OS.............................301
Functions of 8-/16-bit PPG Timer......................284
Generation of Interrupt Request from 8-/16-bit PPG
Timer.................................................293
Interrupts of 8-/16-bit PPG Timer ......................301
List of Registers and Reset Values of 8-/16-bit PPG
Timer.................................................293
Operation Modes of 8-/16-bit PPG Timer ...........284
Operation of 8-/16-bit PPG Timer......................303
Pins of 8-/16-bit PPG Timer..............................292
Precautions when Using 8-/16-bit PPG Timer
..........................................................312
8-bit PPG Output
Setting for 8-bit PPG Output 2-channel Independent
Operation Mode ..................................304
A
A
Accumulator (A) ............................................... 36
A/D Control Status Register
A/D Control Status Register (High) (ADCS: H)
......................................................... 350
A/D Control Status Register (Low) (ADCS: L)
......................................................... 352
A/D Converter
8-/10-bit A/D Converter Interrupt and EI2OS
......................................................... 360
A/D-converted Data Protection Function in 8-/10-bit
A/D Converter.................................... 369
Block Diagram of 8-/10-bit A/D Converter ........ 345
Conversion Modes of 8-/10-bit A/D Converter
......................................................... 344
EI2OS Function of 8-/10-bit A/D Converter ....... 360
Function of 8-/10-bit A/D Converter.................. 344
Generation of Interrupt from 8-/10-bit A/D Converter
......................................................... 349
Interrupt of A/D Converter ............................... 360
List of Registers and Reset Values of 8-/10-bit A/D
Converter........................................... 349
Pins of 8-/10-bit A/D Converter ........................ 348
Precautions when Using 8-/10-bit A/D Converter
......................................................... 371
A/D Data Register
A/D Data Register (High) (ADCR: H) ............... 355
A/D Data Register (Low) (ADCR: L) ................ 357
A/D-converted Data
A/D-converted Data Protection Function in 8-/10-bit
A/D Converter.................................... 369
Acceptance Mask Register
Acceptance Mask Register (AMR) .................... 470
Acceptance Mask Select Register
Acceptance Mask Select Register (AMSR) ........ 468
Access Space
Bank Registers and Access Space........................ 29
Accumulator
Accumulator (A) ............................................... 36
ADB
Additional Bank Register (ADB) ........................ 49
Bank Select Prefix (PCB,DTB,ADB,SPB) ........... 53
ADCR
A/D Data Register (High) (ADCR: H) ............... 355
A/D Data Register (Low) (ADCR: L) ................ 357
ADCS
A/D Control Status Register (High) (ADCS: H)
......................................................... 350
A/D Control Status Register (Low) (ADCS: L)
......................................................... 352
Continuous Conversion Mode
(ADCS: MD1,MD0= 10B ) ................. 361
641
INDEX
Pause-conversion Mode (ADCS: MD1,MD0= 11B )
......................................................... 361
Single Conversion Mode
(ADCS: MD1,MD0= 00B or 01B ) ...... 361
Additional Bank Register
Additional Bank Register (ADB) ........................ 49
Address Detection Control Register
Address Detection Control Register (PACSR)
......................................................... 505
Address Match Detection Function
Block Diagram of Address Match Detection Function
......................................................... 503
List of Registers and Reset Values of Address Match
Detection Function ............................. 504
Operation of Address Match Detection Function
......................................................... 509
Operation of Address Match Detection Function at
Storing Patch Program in E2PROM
......................................................... 513
Overview of Address Match Detection Function
......................................................... 502
Program Example for Address Match Detection
Function ............................................ 515
Addressing
Addressing ..................................................... 566
Addressing by Indirect-specifying 32-bit Register
........................................................... 28
Bank Addressing and Default Space.................... 30
Direct Addressing............................................ 568
Indirect Addressing ......................................... 574
Linear Addressing and Bank Addressing ............. 27
ADER
Analog Input Enable Register (ADER) .............. 358
All Data Erase
All Data Erase from Flash Memory (Chip Erase)
......................................................... 542
AMR
Acceptance Mask Register (AMR).................... 470
AMSR
Acceptance Mask Select Register (AMSR) ........ 468
Analog Input Enable Register
Analog Input Enable Register (ADER) .............. 358
Array
Array of Prefix Codes ........................................ 58
Asynchronous Mode
Operation in Asynchronous Mode..................... 406
B
Bank
Access to FF Bank by ROM Mirroring Function
......................................................... 518
Register Bank ................................................... 51
Setting of Each Bank and Data Access ................ 49
642
Bank Addressing
Bank Addressing and Default Space ....................30
Linear Addressing and Bank Addressing ..............27
Bank Registers
Bank Registers and Access Space ........................29
Bank Select Prefix
Bank Select Prefix (PCB,DTB,ADB,SPB) ...........53
BAP
Buffer Address Pointer (BAP).............................86
Basic Configuration
Basic Configuration of Serial Programming
Connection for MB90F387/S ...............552
Baud Rate
Baud Rate by Dedicated Baud Rate Generator
.........................................................398
Baud Rate by External Clock ............................403
Baud Rate by Internal Timer
(16-bit Reload Timer Output)...............401
Select of UART1 Baud Rate .............................396
Bidirectional Communication
Bidirectional Communication Function ..............413
Bit Timing
Calculation of Bit Timing .................................442
Bit Timing Register
Bit Timing Register (BTR) ...............................440
Bit Timing Segment
Definition of Bit Timing Segment .....................441
Block Diagram
Block Diagram for Pins of 16-bit Reload Timer
.........................................................246
Block Diagram for Pins of CAN Controller ........427
Block Diagram of 16-bit Free-run Timer ............218
Block Diagram of 16-bit Input/Output Timer
.........................................................217
Block Diagram of 16-bit Reload Timer ..............244
Block Diagram of 8-/10-bit A/D Converter.........345
Block Diagram of 8-/16-bit PPG Timer 0 ...........288
Block Diagram of 8-/16-bit PPG Timer 1 ...........290
Block Diagram of 8-/16-bit PPG Timer Pins.......292
Block Diagram of Address Match Detection Function
.........................................................503
Block Diagram of CAN Controller ....................423
Block Diagram of Clock Generation Section
.........................................................112
Block Diagram of Delayed Interrupt Generation
Module ..............................................317
Block Diagram of DTP/External Interrupt ..........325
Block Diagram of External Reset Pin.................103
Block Diagram of Input Capture........................220
Block Diagram of Low-power Consumption Circuit
.........................................................127
Block Diagram of MB90385 Series .......................8
Block Diagram of Pins .....................................327
Block Diagram of Pins for 16-bit Input/Output Timer
.........................................................222
INDEX
Block Diagram of Pins of Port 2
(General-purpose I/O Port)...................167
Block Diagram of Pins of Port 3 ........................172
Block Diagram of Pins of Port 4 ........................177
Block Diagram of Pins of Port 5 ........................182
Block Diagram of Pins of UART1 .....................379
Block Diagram of Port 1 Pins (in Single Chip Mode)
..........................................................162
Block Diagram of ROM Mirroring Function Select
Module ..............................................518
Block Diagram of Timebase Timer ....................190
Block Diagram of UART1 ................................376
Block Diagram of Watch Timer.........................274
Block Diagram of Watchdog Timer ...................205
Details of Pins in Block Diagram...............218, 221
BTR
Bit Timing Register (BTR) ...............................440
Buffer Address Pointer
Buffer Address Pointer (BAP) .............................86
Bus Mode
Bus Mode........................................................154
BVAL
Caution for Disabling Message Buffers by BVAL bits
..........................................................497
BVALR
Message Buffer Valid Register (BVALR) ..........444
C
Calculating
Calculating the Execution Cycle Count ..............583
CAN
Program Example of CAN Transmission and
Reception ...........................................499
CAN Controller
Block Diagram for Pins of CAN Controller ........427
Block Diagram of CAN Controller ....................423
CAN Controller Registers .................................428
Explanation of Operation of CAN Controller
..........................................................480
Generation of Interrupt Request by CAN Controller
..........................................................430
Interrupts of CAN Controller ............................478
Overview of CAN Controller ............................422
Pins of CAN Controller ....................................427
Registers and Vector Tables Related to Interrupt of
CAN Controller ..................................479
CCR
Configuration of Condition Code Register (CCR)
............................................................43
CDCR
Communication Prescaler Control Register 1
(CDCR1)............................................389
Channels
Channels and PPG Pins of PPG Timers ..............287
Chip Erase
All Data Erase from Flash Memory (Chip Erase)
......................................................... 542
Circuit
Block Diagram of Low-power Consumption Circuit
......................................................... 127
CKSCR
Configuration of Clock Select Register (CKSCR)
......................................................... 115
Clock
Baud Rate by External Clock ............................ 403
Block Diagram of Clock Generation Section
......................................................... 112
Clock.............................................................. 109
Clock Supply Map ........................................... 110
Connection of Oscillator and External Clock
......................................................... 123
Machine Clock ................................................ 119
Oscillation Clock Frequency and Serial Clock Input
Frequency .......................................... 554
Register in Clock Generation Section and List of Reset
Values ............................................... 114
Setting Operation Clock of Watchdog Timer
......................................................... 281
Supply of Operation Clock ............................... 199
Clock Generation
Block Diagram of Clock Generation Section
......................................................... 112
Register in Clock Generation Section and List of Reset
Values ............................................... 114
Clock Mode
Clock Mode ............................................ 118, 125
Transition of Clock Mode......................... 118, 147
Clock Select Register
Configuration of Clock Select Register (CKSCR)
......................................................... 115
Clock Supply
Clock Supply .................................................. 189
Cycle of Clock Supply ..................................... 273
Clock Synchronous Mode
Operation in Clock Synchronous Mode
(Operation Mode 2) ............................ 410
CMR
Common Register Bank Prefix (CMR) ................ 55
Command Sequence
Command Sequence Table ............................... 527
Common Register Bank Prefix
Common Register Bank Prefix (CMR) ................ 55
Communication
Bidirectional Communication Function.............. 413
Master/Slave Type Communication Function
......................................................... 415
Communication Prescaler Control Register
Communication Prescaler Control Register 1
(CDCR1) ........................................... 389
643
INDEX
Condition Code Register
Configuration of Condition Code Register (CCR)
........................................................... 43
Connection
Example of Minimum Connection to Flash
Microcontroller Programmer
(Power Supplied from Flash Microcontroller
Programmer)...................................... 561
Example of Minimum Connection to Flash
Microcontroller Programmer
(User Power Supply Used) .................. 559
Connection Example
Connection Example in Single-chip Mode
(Power Supplied from Flash Microcontroller
Programmer)...................................... 557
Connection Example in Single-chip Mode
(User Power Supply Used) .................. 555
Consumption
Block Diagram of Low-power Consumption Circuit
......................................................... 127
CPU Operation Modes and Current Consumption
......................................................... 124
Continuous Conversion Mode
Continuous Conversion Mode
(ADCS: MD1,MD0= 10B ) ................. 361
Operation of Continuous Conversion Mode
......................................................... 364
Setting of Continuous Conversion Mode ........... 364
Control Status Register
Control Status Register (High) (CSR: H) ........... 431
Control Status Register (Low) (CSR: L) ............ 433
Conversion
Conversion Using EI2OS ................................. 368
Conversion Mode
Continuous Conversion Mode
(ADCS: MD1,MD0= 10B ) ................. 361
Conversion Modes of 8-/10-bit A/D Converter
......................................................... 344
Operation of Continuous Conversion Mode ....... 364
Operation of Single Conversion Mode............... 362
Setting of Continuous Conversion Mode ........... 364
Setting of Single Conversion Mode................... 362
Single Conversion Mode
(ADCS: MD1,MD0= 00B or 01B ) ...... 361
Count Clock Select Register
PPG0/1 Count Clock Select Register (PPG01)
......................................................... 298
CPU
CPU and Resources for MB90385 Series............... 6
CPU Intermittent Operation Mode
CPU Intermittent Operation Mode .................... 125
Operation in CPU Intermittent Operation Mode
......................................................... 133
644
CPU Operation Modes
CPU Operation Modes and Current Consumption
.........................................................124
CSR
Control Status Register (High) (CSR: H)............431
Control Status Register (Low) (CSR: L).............433
Current Consumption
CPU Operation Modes and Current Consumption
.........................................................124
Cycle
Cycle of Clock Supply......................................273
Processing of Program for Measuring Cycle Using
Input Capture......................................239
D
Data Access
Setting of Each Bank and Data Access .................49
Data Bank Register
Data Bank Register (DTB)..................................49
Data Counter
Data Counter (DCT)...........................................84
Data Polling Flag
Data Polling Flag (DQ7)...................................531
Data Programming
Data Programming Procedure ...........................540
Data Programming to Flash Memory .................540
Data Register
Data Register (DTR) ........................................477
DCT
Data Counter (DCT)...........................................84
Dedicated Baud Rate Generator
Baud Rate by Dedicated Baud Rate Generator
.........................................................398
Dedicated Registers
Configuration of Dedicated Registers...................33
Dedicated Registers and General-purpose Register
...........................................................35
Default Space
Bank Addressing and Default Space ....................30
Delayed Interrupt Generation Module
Block Diagram of Delayed Interrupt Generation
Module ..............................................317
Explanation of Operation of Delayed Interrupt
Generation Module .............................320
List of Registers and Reset Values in Delayed
Interrupt Generation Module ................318
Overview of Delayed Interrupt Generation Module
.........................................................316
Precautions when Using Delayed Interrupt Generation
Module ..............................................321
Program Example of Delayed Interrupt Generation
Module ..............................................322
INDEX
Delayed Interrupt Request Generate/Cancel Register
Delayed Interrupt Request Generate/Cancel Register
(DIRR)...............................................319
Description
Description of Instruction Presentation Items and
Symbols .............................................586
Descriptor
Configuration of EI2OS Descriptor (ISD) .............82
Detect Address
Setting Detect Address .....................................509
Detect Address Setting Registers
Detect Address Setting Registers
(PADR0 and PADR1) .........................507
Functions of Detect Address Setting Registers
..........................................................508
Detection Level Setting Register
Detection Level Setting Register (ELVR) (High)
..........................................................331
Detection Level Setting Register (ELVR) (Low)
..........................................................332
Direct Addressing
Direct Addressing ............................................568
Direct Page Register
Direct Page Register (DPR) ................................48
DIRR
Delayed Interrupt Request Generate/Cancel Register
(DIRR)...............................................319
Disabling Message Buffers
Caution for Disabling Message Buffers by BVAL bits
..........................................................497
DLC Register
DLC Register (DLCR)......................................476
DLCR
DLC Register (DLCR)......................................476
DPR
Direct Page Register (DPR) ................................48
DQ2
Toggle Bit Flag (DQ2) .....................................536
DQ3
Sector Erase Timer Flag (DQ3) .........................535
DQ5
Timing Limit Over Flag (DQ5) .........................534
DQ6
Toggle Bit Flag (DQ6) .....................................533
DQ7
Data Polling Flag (DQ7)...................................531
DTB
Bank Select Prefix (PCB,DTB,ADB,SPB)............53
Data Bank Register (DTB) ..................................49
DTP Function
DTP Function ..................................................337
Program Example of DTP Function ...................341
DTP/External Interrupt
Block Diagram of DTP/External Interrupt.......... 325
DTP/External Interrupt Operation ..................... 334
List of Registers and Reset Values in DTP/External
Interrupt............................................. 327
Pins of DTP/External Interrupt.......................... 327
Precautions when Using DTP/External Interrupt
......................................................... 338
Program Example of DTP/External Interrupt Function
......................................................... 340
Setting of DTP/External Interrupt...................... 333
DTP/External Interrupt Enable Register
DTP/External Interrupt Enable Register (ENIR)
......................................................... 329
DTP/External Interrupt Factor Register
DTP/External Interrupt Factor Register (EIRR)
......................................................... 328
DTP/External Interrupt Function
DTP/External Interrupt Function ....................... 324
DTR
Data Register (DTR) ........................................ 477
E
E2PROM
E2PROM Memory Map ................................... 511
Operation of Address Match Detection Function at
Storing Patch Program in E2PROM ...... 513
System Configuration and E2PROM Memory Map
......................................................... 510
Effective Address Field
Effective Address Field ............................ 567, 585
EI2OS
16-bit Input/Output Timer Interrupts and EI2OS
Function ............................................ 232
8-/10-bit A/D Converter Interrupt and EI2OS
......................................................... 360
8-/16-bit PPG Timer Interrupt and EI2OS Function
......................................................... 302
Conversion Using EI2OS.................................. 368
Correspondence between 16-bit Input/Output Timer
Interrupt and EI2OS ............................ 232
Correspondence between 16-bit Reload Timer
Interrupt and EI2OS ............................ 255
Correspondence between 8-/16-bit PPG Timer
Interrupt and EI2OS ............................ 301
Correspondence between Timebase Timer Interrupt
and EI2OS.......................................... 195
2
EI OS............................................................... 80
EI2OS Function of 16-bit Reload Timer............. 255
EI2OS Function of 8-/10-bit A/D Converter ....... 360
EI2OS Function of UART1............................... 392
EI2OS Processing Time (time for one transfer) ..... 89
Interrupt Related to UART1 and EI2OS ............. 392
Operation of EI2OS...................................... 81, 87
Procedure for Use of EI2OS................................ 88
645
INDEX
Program Example of EI2OS ............................... 97
Watch Timer Interrupt and EI2OS Function ....... 279
EI2OS Descriptor
Configuration of EI2OS Descriptor (ISD) ............ 82
2
EI OS Status Register
EI2OS Status Register (ISCS) ............................. 85
EIRR
DTP/External Interrupt Factor Register (EIRR)
......................................................... 328
ELVR
Detection Level Setting Register (ELVR) (High)
......................................................... 331
Detection Level Setting Register (ELVR) (Low)
......................................................... 332
ENIR
DTP/External Interrupt Enable Register (ENIR)
......................................................... 329
Erase
All Data Erase from Flash Memory (Chip Erase)
......................................................... 542
Sector Erase Suspension in Flash Memory......... 545
Erase Resumption
Erase Resumption in Flash Memory.................. 546
Erasing
Detailed Explanation of Programming and Erasing
Flash Memory.................................... 538
Erasing Any Data in Flash Memory (Sector Erasing)
......................................................... 543
Programming and Erasing Flash Memory .......... 522
Erasing Procedure
Erasing Procedure for Flash Memory Sectors
......................................................... 543
Error
Node Status Transition due to Error Occurrence
......................................................... 439
Event Count Mode
Event Count Mode .......................................... 242
Operation in Event Count Mode ....................... 265
Program Example in Event Count Mode............ 269
Setting of Event Count Mode ........................... 263
Exception Processing
Exception Processing......................................... 91
Execution Cycle Count
Calculating the Execution Cycle Count ............. 583
Execution Cycle Count .................................... 582
Extended I/O
Extended I/O Area............................................. 23
External Clock
Baud Rate by External Clock............................ 403
Connection of Oscillator and External Clock
......................................................... 123
External Interrupt
External Interrupt Function .............................. 336
646
External Reset
Block Diagram of External Reset Pin.................103
F
F2MC-16LX Instruction List
F2MC-16LX Instruction List.............................589
Factor
Correspondence of Reset Factor Bit and Reset Factor
.........................................................107
Notes on Reset Factor Bit .................................107
Fetch
Mode Fetch .....................................................105
FF Bank
Access to FF Bank by ROM Mirroring Function
.........................................................518
Flag
Hardware Sequence Flags .................................529
Flag Change Inhibit Prefix
Flag Change Inhibit Prefix (NCC) .......................56
Flag Set
Generation of Receive Interrupt and Timing of Flag
Set .....................................................393
Generation of Transmit Interrupt and Timing of Flag
Set .....................................................395
Flash Memory
All Data Erase from Flash Memory (Chip Erase)
.........................................................542
Data Programming to Flash Memory .................540
Detailed Explanation of Programming and Erasing
Flash Memory ....................................538
Erase Resumption in Flash Memory ..................546
Erasing Any Data in Flash Memory (Sector Erasing)
.........................................................543
Erasing Procedure for Flash Memory Sectors
.........................................................543
Features of 512 Kbit Flash Memory...................522
List of Registers and Reset Values of Flash Memory
.........................................................523
Overview of 512 Kbit Flash Memory.................522
Program Example of 512 Kbit Flash Memory
.........................................................547
Programming and Erasing Flash Memory...........522
Read/Reset State in Flash Memory ....................539
Sector Configuration of 512 Kbit Flash Memory
.........................................................523
Sector Erase Suspension in Flash Memory .........545
Flash Memory Control Status Register
Flash Memory Control Status Register (FMCS)
.........................................................524
Flash Microcontroller Programmer
Connection Example in Single-chip Mode
(Power Supplied from Flash Microcontroller
Programmer) ......................................557
INDEX
Example of Minimum Connection to Flash
Microcontroller Programmer
(Power Supplied from Flash Microcontroller
Programmer) ......................................561
Example of Minimum Connection to Flash
Microcontroller Programmer
(User Power Supply Used) ...................559
Flash Microcontroller Programmer System
Flash Microcontroller Programmer System
Configuration (Made by Yokogawa Digital
Computer Corporation)........................554
FMCS
Flash Memory Control Status Register (FMCS)
..........................................................524
FPT-48P-M26
Package Dimension of FPT-48P-M26 ..................10
Pin Assignment (FPT-48P-M26) ...........................9
Free-run Timer
Block Diagram of 16-bit Free-run Timer ............218
Operation of 16-bit Free-run Timer....................233
Operation Timing of 16-bit Free-run Timer ........234
Setting of 16-bit Free-run Timer ........................233
Frequency
Oscillation Clock Frequency and Serial Clock Input
Frequency ..........................................554
G
General-purpose I/O Port
Block Diagram of Pins of Port 2
(General-purpose I/O Port)...................167
Operation of Port 2 (General-purpose I/O Port)
..........................................................169
Operation of Port 3 (General-purpose I/O Port)
..........................................................174
General-purpose Register
Configuration of General-purpose Register...........50
Dedicated Registers and General-purpose Register
............................................................35
General-purpose Register Area and Register Bank
Pointer .................................................45
Generator
Baud Rate by Dedicated Baud Rate Generator
..........................................................398
H
Handling Devices
Precautions when Handling Devices ....................18
Hardware Interrupt
Hardware Interrupt.............................................71
Hardware Interrupt Inhibition..............................72
Mechanism of Hardware Interrupt .......................72
Operation of Hardware Interrupt..........................75
Procedure for Use of Hardware Interrupt ..............76
Return from Hardware Interrupt ..........................74
Start of Hardware Interrupt ................................. 74
Hardware Sequence Flags
Hardware Sequence Flags................................. 529
I
I/O
I/O Area ........................................................... 23
I/O Address Pointer
I/O Address Pointer (IOA).................................. 84
I/O Circuit
I/O Circuit ........................................................ 14
I/O Port
Block Diagram of Pins of Port 2
(General-purpose I/O Port) ................. 167
I/O Port Function............................................. 158
Operation of Port 2 (General-purpose I/O Port)
......................................................... 169
Operation of Port 3 (General-purpose I/O Port)
......................................................... 174
Registers of I/O Ports ....................................... 160
ICR
Bit Configuration of Interrupt Control Register (ICR)
........................................................... 68
Interrupt Control Register (ICR00 to ICR15)........ 66
ICS
Input Capture Control Status Registers
(ICS01 and ICS23) ............................. 228
ID Register
ID Register (IDR) ............................................ 473
IDE Register
IDE Register (IDER)........................................ 446
IDER
IDE Register (IDER)........................................ 446
IDR
ID Register (IDR) ............................................ 473
ILM
Interrupt Level Mask Register (ILM)................... 46
Image Access
Image Access to Internal ROM ........................... 25
Independent Operation Mode
Setting for 8-bit PPG Output 2-channel Independent
Operation Mode.................................. 304
Index
Interrupt Vector Index...................................... 636
Pin Function Index........................................... 634
Register Index ................................................. 625
Indirect Addressing
Indirect Addressing.......................................... 574
Indirect-specifying
Addressing by Indirect-specifying 32-bit Register
........................................................... 28
Input Capture
Block Diagram of Input Capture ....................... 220
647
INDEX
Operation of Input Capture............................... 236
Operation Timing of Input Capture ................... 237
Processing of Program for Measuring Cycle Using
Input Capture ..................................... 239
Setting of Input Capture ................................... 235
Input Capture Control Status Registers
Input Capture Control Status Registers
(ICS01 and ICS23) ............................. 228
Input Capture Data Registers
Input Capture Data Registers 0 to 3 (IPCP0 to IPCP3)
......................................................... 231
Operation of Input Capture Data Registers 0 to 3
(IPCP0 to IPCP3) ............................... 231
Input/Output Pins
State of Input/Output Pins (Single-chip Mode)
......................................................... 145
Input/Output Timer
16-bit Input/Output Timer Interrupts and EI2OS
Function ............................................ 232
Block Diagram of 16-bit Input/Output Timer
......................................................... 217
Block Diagram of Pins for 16-bit Input/Output Timer
......................................................... 222
Configuration of 16-bit Input/Output Timer ....... 216
Correspondence between 16-bit Input/Output Timer
Interrupt and EI2OS............................ 232
Functions of 16-bit Input/Output Timer ............. 216
Generation of Interrupt Request from 16-bit Input/
Output Timer ..................................... 224
Interrupt Control Bits and Interrupt Factors of 16-bit
Input/Output Timer............................. 232
List of Registers and Reset Values of 16-bit Input/
Output Timer ..................................... 223
Pins of 16-bit Input/Output Timer ..................... 222
Precautions when 16-bit Input/Output Timer
......................................................... 238
Instruction
Description of Instruction Presentation Items and
Symbols ............................................ 586
F2MC-16LX Instruction List........................... 589
Instruction Types............................................. 565
Prefix Code and Interrupt Inhibit Instruction ........ 57
Structure of Instruction Map............................. 603
Instruction Presentation Items and Symbols
Description of Instruction Presentation Items and
Symbols ............................................ 586
Internal Clock Mode
Internal Clock Mode........................................ 242
Operation in Internal Clock Mode..................... 259
Program Example in Internal Clock Mode ......... 267
Setting of Internal Clock Mode......................... 258
Internal ROM
Image Access to Internal ROM ........................... 25
648
Internal Timer
Baud Rate by Internal Timer (16-bit Reload Timer
Output) ..............................................401
Interrupt
16-bit Input/Output Timer Interrupts and EI2OS
Function.............................................232
8-/10-bit A/D Converter Interrupt and EI2OS
.........................................................360
8-/16-bit PPG Timer Interrupt and EI2OS Function
.........................................................302
Block Diagram of DTP/External Interrupt ..........325
Cancellation of Standby Mode by Interrupt
.........................................................146
Correspondence between 16-bit Input/Output Timer
Interrupt and EI2OS ............................232
Correspondence between 16-bit Reload Timer
Interrupt and EI2OS ............................255
Correspondence between 8-/16-bit PPG Timer
Interrupt and EI2OS ............................301
Correspondence between Timebase Timer Interrupt
and EI2OS ..........................................195
Details of Pins and Interrupt Numbers................326
DTP/External Interrupt Function .......................324
DTP/External Interrupt Operation......................334
External Interrupt Function ...............................336
Generation of Interrupt from 8-/10-bit A/D Converter
.........................................................349
Generation of Receive Interrupt and Timing of Flag
Set .....................................................393
Generation of Transmit Interrupt and Timing of Flag
Set .....................................................395
Hardware Interrupt.............................................71
Hardware Interrupt Inhibition..............................72
Interrupt Control Bits and Interrupt Factors of 16-bit
Input/Output Timer .............................232
Interrupt Number .............................................317
Interrupt of A/D Converter................................360
Interrupt of UART1 .........................................391
Interrupt Operation.............................................60
Interrupt Related to UART1 and EI2OS .............392
Interrupts of 16-bit Reload Timer ......................255
Interrupts of 8-/16-bit PPG Timer ......................301
Interrupts of CAN Controller ............................478
List of Registers and Reset Values in DTP/External
Interrupt .............................................327
Mechanism of Hardware Interrupt .......................72
Multiple Interrupts .............................................77
Operation of Hardware Interrupt..........................75
Pins of DTP/External Interrupt ..........................327
Precautions when Using DTP/External Interrupt
.........................................................338
Procedure for Use of Hardware Interrupt..............76
Program Example of DTP/External Interrupt Function
.........................................................340
Registers and Vector Tables Related to Interrupt of
CAN Controller ..................................479
Return from Hardware Interrupt ..........................74
INDEX
Setting of DTP/External Interrupt ......................333
Start and Operation of Software Interrupt .............79
Start of Hardware Interrupt .................................74
Timebase Timer Interrupt .................................195
Type and Function of Interrupt ............................59
Watch Timer Interrupt ......................................279
Watch Timer Interrupt and EI2OS Function ........279
Interrupt Control Register
Bit Configuration of Interrupt Control Register (ICR)
............................................................68
Function of Interrupt Control Register..................69
Interrupt Control Register (ICR00 to ICR15) ........66
Interrupt Control Register List.............................64
Interrupt Factor,Interrupt Vector,and Interrupt
Control Register....................................62
Interrupt Factor
Interrupt Control Bits and Interrupt Factors of 16-bit
Input/Output Timer .............................232
Interrupt Factor,Interrupt Vector,and Interrupt
Control Register....................................62
Interrupt Inhibit Instruction
Prefix Code and Interrupt Inhibit Instruction.........57
Interrupt Level Mask Register
Interrupt Level Mask Register (ILM) ...................46
Interrupt Number
Interrupt Number .............................................317
Interrupt Processing
Program Example of Interrupt Processing.............95
Stack Operation at Return from Interrupt Processing
............................................................94
Stack Operation at Starting Interrupt Processing
............................................................94
Time Required to Start Interrupt Processing .........92
Interrupt Request
Generation of Interrupt Request by CAN Controller
..........................................................430
Generation of Interrupt Request from 16-bit Input/
Output Timer ......................................224
Generation of Interrupt Request from 16-bit Reload
Timer.................................................248
Generation of Interrupt Request from 8-/16-bit PPG
Timer.................................................293
Generation of Interrupt Request from Timebase Timer
..........................................................192
Generation of Interrupt Request from Watch Timer
..........................................................276
Interrupt Request Generation by UART1............380
Interrupt Vector
Interrupt Factor,Interrupt Vector,and Interrupt
Control Register....................................62
Interrupt Vector .................................................61
Interrupt Vector Index
Interrupt Vector Index ......................................636
Interval Timer
Functions of Interval Timer...............................188
Interval Timer Function.................... 196, 272, 280
IOA
I/O Address Pointer (IOA).................................. 84
IPCP
Input Capture Data Registers 0 to 3 (IPCP0 to IPCP3)
......................................................... 231
Operation of Input Capture Data Registers 0 to 3
(IPCP0 to IPCP3) ............................... 231
ISCS
EI2OS Status Register (ISCS) ............................. 85
ISD
Configuration of EI2OS Descriptor (ISD)............. 82
L
Last Event Indicate Register
Last Event Indicate Register (LEIR) .................. 436
LEIR
Last Event Indicate Register (LEIR) .................. 436
Linear Addressing
Linear Addressing and Bank Addressing.............. 27
Linear Addressing by Specifying 24-bit Operand
........................................................... 28
Lineup
Product Lineup for MB90385 Series...................... 5
List
List of Registers and Reset Values of 16-bit Reload
Timer ................................................ 247
Low-power Consumption
Block Diagram of Low-power Consumption Circuit
......................................................... 127
Low-power Consumption Mode Control Register
Low-power Consumption Mode Control Register
(LPMCR)........................................... 130
Low-power Consumption Mode Control Register and
Reset Values ...................................... 129
Notes on Accessing the Low-power Consumption
Mode Control Register (LPMCR) to Enter
the Standby Mode............................... 148
LPMCR
Low-power Consumption Mode Control Register
(LPMCR)........................................... 130
Notes on Accessing the Low-power Consumption
Mode Control Register (LPMCR) to Enter
the Standby Mode............................... 148
M
Machine Clock
Machine Clock ................................................ 119
Master/Slave Type Communication
Master/Slave Type Communication Function
......................................................... 415
MB90385 Series
Block Diagram of MB90385 Series ....................... 8
649
INDEX
CPU and Resources for MB90385 Series............... 6
Features of MB90385 Series................................. 2
Memory Map for MB90385 Series...................... 24
Product Lineup for MB90385 Series ..................... 5
MB90F387/S
Basic Configuration of Serial Programming
Connection for MB90F387/S............... 552
MD
Continuous Conversion Mode
(ADCS: MD1,MD0= 10B ) ................. 361
Pause-conversion Mode (ADCS: MD1,MD0= 11B )
......................................................... 361
Setting of Mode Pins (MD2 to MD0) ................ 150
Single Conversion Mode
(ADCS: MD1,MD0= 00B or 01B ) ...... 361
Memory Access Mode
Selection of Memory Access Mode ................... 155
Memory Map
E2PROM Memory Map ................................... 511
Memory Map .................................................... 26
Memory Map for MB90385 Series...................... 24
System Configuration and E2PROM Memory Map
......................................................... 510
Memory Space
Memory Space .................................................. 22
Memory Space when ROM Mirroring Function
Enabled/Disabled ............................... 519
Message Buffer
Caution for Disabling Message Buffers by BVAL bits
......................................................... 497
Message Buffers.............................................. 472
Procedure for Receiving Message Buffer (x)
......................................................... 492
Procedure for Transmitting Message Buffer (x)
......................................................... 489
Setting Configuration of Multiple Message Buffer
......................................................... 495
Message Buffer Valid Register
Message Buffer Valid Register (BVALR).......... 444
Minimum Connection
Example of Minimum Connection to Flash
Microcontroller Programmer
(Power Supplied from Flash Microcontroller
Programmer)...................................... 561
Example of Minimum Connection to Flash
Microcontroller Programmer
(User Power Supply Used) .................. 559
Mode
Block Diagram of Port 1 Pins (in Single Chip Mode)
......................................................... 162
Bus Mode ....................................................... 154
Cancellation of Standby Mode by Interrupt
......................................................... 146
Classification of Modes ................................... 149
Clock Mode ............................................ 118, 125
650
Connection Example in Single-chip Mode
(Power Supplied from Flash Microcontroller
Programmer) ......................................557
Connection Example in Single-chip Mode
(User Power Supply Used)...................555
Continuous Conversion Mode
(ADCS: MD1,MD0= 10B )..................361
Conversion Modes of 8-/10-bit A/D Converter
.........................................................344
CPU Intermittent Operation Mode .....................125
CPU Operation Modes and Current Consumption
.........................................................124
Event Count Mode ...........................................242
Function of Registers for Port 1 (in Single Chip Mode)
.........................................................163
Internal Clock Mode ........................................242
Mode Pin ........................................................105
Note on Cancelling Standby Mode ....................146
Notes on Accessing the Low-power Consumption
Mode Control Register (LPMCR) to Enter
the Standby Mode ...............................148
Notes on the Transition to Standby Mode ...........146
Operating State in Each Standby Mode ..............134
Operation in Asynchronous Mode .....................406
Operation in Clock Synchronous Mode
(Operation Mode 2).............................410
Operation in CPU Intermittent Operation Mode
.........................................................133
Operation in Event Count Mode ........................265
Operation in Internal Clock Mode .....................259
Operation Mode...............................................149
Operation Modes of 16-bit Reload Timer ...........242
Operation Modes of 8-/16-bit PPG Timer...........284
Operation of Continuous Conversion Mode ........364
Operation of Pause-conversion Mode.................366
Operation of Port 1 (in Single Chip Mode) .........164
Operation of Single Conversion Mode ...............362
Oscillation Stabilization Wait Time in Standby Mode
.........................................................104
Pause-conversion Mode (ADCS: MD1,MD0= 11B )
.........................................................361
Program Example in Event Count Mode ............269
Program Example in Internal Clock Mode..........267
Registers for Port 1 (in Single Chip Mode) .........162
Return from Sleep Mode...................................136
Return from Stop Mode ....................................142
Return from Timebase Timer Mode ...................140
Return from Watch Mode .................................138
Selection of Memory Access Mode ...................155
Setting for 16-bit PPG Output Operation Mode
.........................................................306
Setting for 8+8-bit PPG Output Operation Mode
.........................................................309
Setting for 8-bit PPG Output 2-channel Independent
Operation Mode..................................304
Setting of Continuous Conversion Mode ............364
Setting of Event Count Mode ............................263
INDEX
Setting of Internal Clock Mode..........................258
Setting of Pause-conversion Mode .....................366
Setting of Single Conversion Mode....................362
Single Conversion Mode
(ADCS: MD1,MD0= 00B or 01B ) .......361
Standby Mode .................................................125
State of Input/Output Pins (Single-chip Mode)
..........................................................145
Stop Mode.......................................................141
Transition of Clock Mode .........................118, 147
Transition to Sleep Mode..................................135
Transition to Standby Mode ..............................146
Transition to Timebase Timer Mode ..................139
Transition to Watch Mode ................................137
Mode Data
Mode Data ......................................................152
Setting Mode Data ...........................................153
State of Pins after Mode Data Read....................108
Mode Fetch
Mode Fetch .....................................................105
Mode Pins
Setting Mode Pins ............................................151
Setting of Mode Pins (MD2 to MD0) .................150
Multi-byte Data
Access to Multi-byte Data...................................32
Storage of Multi-byte Data in Stack .....................32
Store of Multi-byte Data in RAM ........................31
Multi-byte Length
Storage of Multi-byte Length Operand .................31
Multiple Interrupts
Multiple Interrupts .............................................77
Multiple Message Buffer
Setting Configuration of Multiple Message Buffer
..........................................................495
Multiplication Rate
Selection of PLL Clock Multiplication Rate
..........................................................119
N
NCC
Flag Change Inhibit Prefix (NCC) .......................56
Node Status Transition
Node Status Transition due to Error Occurrence
..........................................................439
O
Operand
Linear Addressing by Specifying 24-bit Operand
............................................................28
Storage of Multi-byte Length Operand .................31
Operating State
Setting and Operating State ...............................512
Operation Clock
Supply of Operation Clock................................199
Operation Mode
CPU Intermittent Operation Mode..................... 125
CPU Operation Modes and Current Consumption
......................................................... 124
Operation in CPU Intermittent Operation Mode
......................................................... 133
Operation Mode .............................................. 149
Operation Modes of 16-bit Reload Timer ........... 242
Setting for 8-bit PPG Output 2-channel Independent
Operation Mode.................................. 304
Operation Mode Control Register
PPG0 Operation Mode Control Register (PPGC0)
......................................................... 294
PPG1 Operation Mode Control Register (PPGC1)
......................................................... 296
Oscillation Clock Frequency
Oscillation Clock Frequency and Serial Clock Input
Frequency .......................................... 554
Oscillation Stab