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The following document contains information on Cypress products.
CM44-10123-2E
FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
2
F MC-16LX
16-BIT MICROCONTROLLER
MB90435 Series
HARDWARE MANUAL
2
F MC-16LX
16-BIT MICROCONTROLLER
MB90435 Series
HARDWARE MANUAL
The information for microcontroller supports is shown in the following homepage.
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page
"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU MICROELECTRONICS LIMITED
PREFACE
■ Objectives and Intended Reader
Thank you for your continued use of Fujitsu semiconductor products.
The MB90435 series has been developed as a general-purpose version of the F2MC-16LX
series, which is an original 16-bit single-chip microcontroller compatible with Application Specific
ICs (ASICs).
This manual describes the functions and operation of the MB90435 series for designers who will
use the MB90435 series to design products. Read this manual before starting to design
products.
■ Trademark
F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
Other system and product names in this manual are trademarks of respective companies or
organizations.
The symbols TM and ® are sometimes omitted in this manual.
■ Structure of This Manual
This manual has 24 chapters and an appendix:
CHAPTER 1 "OVERVIEW"
This chapter explains the features and basic specifications of the M90540/545 series
products.
CHAPTER 2 "CPU"
This chapter explains the CPU.
CHAPTER 3 "INTERRUPTS"
This chapter explains the interrupt functions and operations.
CHAPTER 4 "CLOCK AND RESET"
This chapter explains the functions and operations of clocks and resets.
CHAPTER 5 "LOW-POWER CONTROL CIRCUIT"
This chapter explains the functions and operation of the low-power control circuit.
CHAPTER 6 "LOW-POWER CONSUMPTION MODES"
This chapter explains the functions and operation of the low-power consumption modes.
CHAPTER 7 "MEMORY ACCESS MODES"
This chapter explains the functions and operations of the memory access modes.
CHAPTER 8 "I/O PORTS"
This chapter explains the functions and operations of the I/O ports.
CHAPTER 9 "TIMEBASE TIMER"
This chapter explains the functions and operations of the timebase timer.
i
CHAPTER 10 "WATCH-DOG TIMER"
This chapter explains the functions and operations of the watch-dog timer.
CHAPTER 11 "WATCH TIMER"
This chapter explains the functions and operations of the watch timer.
CHAPTER 12 "16-BIT I/O TIMER"
This chapter explains the functions and operations of the 16-bit I/O timer.
CHAPTER 13 "16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)"
This chapter explains the functions and operations of the 16-bit reload timer (with the event
count function).
CHAPTER 14 "8/16-BIT PPG"
This chapter explains the functions and operation of the 8/16-bit PPG.
CHAPTER 15 "DELAYED INTERRUPTS"
This chapter explains the functions and operations of the delayed interrupt.
CHAPTER 16 "DTP/EXTERNAL INTERRUPTS"
This chapter explains the functions and operations of the DTP/external interrupts.
CHAPTER 17 "A/D CONVERTER"
This chapter explains the functions and operations of the A/D converter.
CHAPTER 18 "UART0"
This chapter explains the UART0 functions and operations.
CHAPTER 19 "UART1 (SCI)"
This chapter explains the UART1 (SCI) functions and operation.
CHAPTER 20 "SERIAL I/O"
This chapter explains the functions and operations of the serial I/O.
CHAPTER 21 "ADDRESS MATCH DETECTION FUNCTION"
This chapter explains the address match detection function and operation.
CHAPTER 22 "ROM MIRRORING FUNCTION SELECTION MODULE"
This chapter explains the ROM mirroring function selection module.
CHAPTER 23 "1M/2M-BIT FLASH MEMORY"
This chapter explains the functions and operation of the 1M/2M-bit flash memory.
CHAPTER 24 "EXAMPLES OF MB90F438L(S)/F439(S) SERIAL PROGRAMMING
CONNECTION"
This chapter provides examples of serial programming connection with the AF220/AF210/
AF120/AF110 flash microcomputer programmer manufactured by Yokogawa Digital
Computer Corporation.
Appendix
The appendix provides I/O maps and outlines instructions.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©2002-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
OVERVIEW ................................................................................................... 1
Product Overview .................................................................................................................................. 2
Features ................................................................................................................................................ 3
Block Diagram ....................................................................................................................................... 5
Package Dimensions ............................................................................................................................. 6
Pin Assignment ...................................................................................................................................... 8
Pin Functions ....................................................................................................................................... 10
I/O Circuits ........................................................................................................................................... 15
Handling the Device ............................................................................................................................. 18
CHAPTER 2
CPU ............................................................................................................. 21
2.1 Outline of CPU ..................................................................................................................................... 22
2.2 Memory Space ..................................................................................................................................... 23
2.3 Memory Space Map ............................................................................................................................. 24
2.4 Linear Addressing ................................................................................................................................ 25
2.5 Bank Addressing Types ....................................................................................................................... 26
2.6 Multi-byte Data in Memory Space ........................................................................................................ 28
2.7 Registers .............................................................................................................................................. 29
2.7.1 Accumulator (A) .............................................................................................................................. 31
2.7.2 User Stack Pointer (USP) and System Stack Pointer (SSP) .......................................................... 33
2.7.3 Processor Status (PS) .................................................................................................................... 34
2.7.4 Program Counter (PC) .................................................................................................................... 37
2.8 Register Bank ...................................................................................................................................... 38
2.9 Prefix Codes ........................................................................................................................................ 40
2.10 Interrupt Disable Instructions ............................................................................................................... 42
2.11 Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions .............................................................. 43
CHAPTER 3
INTERRUPTS .............................................................................................. 45
3.1 Outline of Interrupts ............................................................................................................................. 46
3.2 Interrupt Sources ................................................................................................................................. 47
3.3 Interrupt Vector .................................................................................................................................... 49
3.4 Hardware Interrupts ............................................................................................................................. 51
3.4.1 Hardware Interrupt Operation ......................................................................................................... 53
3.4.2 Flow of Hardware Interrupt Operation ............................................................................................ 56
3.5 Software Interrupts .............................................................................................................................. 57
3.6 Extended Intelligent I/O Service (EI2OS) ............................................................................................. 59
3.6.1 Interrupt Control Register (ICR) ...................................................................................................... 61
3.6.2 Extended Intelligent I/O Service Descriptor (ISD) .......................................................................... 64
3.6.3 Operation of Extended Intelligent I/O Service (EI2OS) ................................................................... 67
3.6.4 Execution Time of the Extended Intelligent I/O Service (EI2OS) .................................................... 69
3.7 Exception Due to Execution of an Undefined Instruction ..................................................................... 71
CHAPTER 4
4.1
CLOCK AND RESET .................................................................................. 73
Clock Generator ................................................................................................................................... 74
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4.2
4.3
Reset Cause Occurrence .................................................................................................................... 75
Reset Causes ..................................................................................................................................... 80
CHAPTER 5
LOW-POWER CONTROL CIRCUIT ........................................................... 83
5.1 Outline of Low-Power Control Circuit ..................................................................................................
5.2 Block Diagram of Low-Power Control Circuit ......................................................................................
5.3 Low-Power Control Circuit Registers ..................................................................................................
5.3.1 Low-Power Mode Control Register (LPMCR) ................................................................................
5.3.2 Clock Selection Register (CKSCR) ................................................................................................
5.4 Status Transition for Clock Selection ..................................................................................................
CHAPTER 6
84
86
87
88
91
94
LOW-POWER CONSUMPTION MODES ................................................... 97
6.1 Low-Power Consumption Modes ........................................................................................................ 98
6.1.1 Sleep Mode .................................................................................................................................. 102
6.1.2 Pseudo Watch Mode ................................................................................................................... 103
6.1.3 Watch Mode ................................................................................................................................. 104
6.1.4 Stop mode .................................................................................................................................. 105
6.1.5 Hardware Standby Mode ............................................................................................................. 107
6.1.6 Intermittent CPU Operation ......................................................................................................... 108
6.2 Status Transitions in Low-Power Consumption Mode ...................................................................... 109
6.3 Status Transition Diagram for Low-Power Consumption Mode ........................................................ 114
CHAPTER 7
MEMORY ACCESS MODES .................................................................... 123
7.1 Outline of Memory Access Modes ....................................................................................................
7.1.1 Mode Pins ....................................................................................................................................
7.1.2 Mode Data ...................................................................................................................................
7.1.3 Memory Space in Each Bus Mode ..............................................................................................
7.2 External Memory Access (Bus Pin Control Circuit) ...........................................................................
7.2.1 External Memory Access (External Bus Pin Control Circuit) Registers .......................................
7.2.2 Automatic Ready Function Selection Register (ARSR) ...............................................................
7.2.3 External Address Output Control Register (HACR) .....................................................................
7.2.4 Bus Control Signal Selection Register (ECSR) ............................................................................
7.3 External Memory Access Control Signal Operation ..........................................................................
7.3.1 Ready Function ............................................................................................................................
7.3.2 Hold Function ...............................................................................................................................
CHAPTER 8
I/O PORTS ................................................................................................ 143
8.1 I/O Ports ............................................................................................................................................
8.2 I/O Port Registers .............................................................................................................................
8.2.1 Port Data Register (PDR) ............................................................................................................
8.2.2 Port Direction Register (DDR) ......................................................................................................
8.2.3 Pull-up Control Register (PUCR) .................................................................................................
8.2.4 Analog Input Enable Register (ADER) ........................................................................................
CHAPTER 9
9.1
9.2
9.3
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124
125
126
127
129
130
131
133
134
137
139
141
144
145
146
147
148
150
TIMEBASE TIMER .................................................................................... 151
Outline of Timebase Timer ................................................................................................................ 152
Timebase Timer Control Register (TBTC) ........................................................................................ 154
Operations of Timebase Timer ......................................................................................................... 156
CHAPTER 10 WATCH-DOG TIMER ................................................................................ 157
10.1 Outline of Watch-dog Timer ............................................................................................................... 158
10.2 Watch-dog Timer Control Register (WDTC) ...................................................................................... 160
10.3 Watch-dog Timer Operation .............................................................................................................. 162
CHAPTER 11 WATCH TIMER ......................................................................................... 163
11.1 Outline of Watch Timer ...................................................................................................................... 164
11.2 Watch Timer Control Register (WTC) ................................................................................................ 166
11.3 Watch Timer Operation ...................................................................................................................... 168
CHAPTER 12 16-BIT I/O TIMER ...................................................................................... 169
12.1 Outline of 16-Bit I/O Timer ................................................................................................................. 170
12.2 16-bit I/O Timer Registers .................................................................................................................. 172
12.3 16-bit Free-running Timer .................................................................................................................. 173
12.3.1 16-bit Free-running Timer Registers ............................................................................................. 174
12.3.2 Timer Counter Control Status Register ........................................................................................ 175
12.3.3 16-bit Free-running Timer Operation ............................................................................................ 177
12.4 Output Compare ................................................................................................................................ 179
12.4.1 Output Compare Register ............................................................................................................. 180
12.4.2 Control Status Register of Output Compare ................................................................................. 181
12.4.3 16-bit Output Compare Operation ................................................................................................ 184
12.5 Input Capture ..................................................................................................................................... 187
12.5.1 Input Capture Register Details ..................................................................................................... 188
12.5.2 16-bit Input Capture Operation ..................................................................................................... 190
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) ................ 193
13.1 Outline of 16-Bit Reload Timer (with Event Count Function) ............................................................. 194
13.2 16-Bit Reload Timer (with Event Count Function) ............................................................................. 196
13.2.1 Timer Control Status Register (TMCSR) ...................................................................................... 197
13.2.2 Register Layout of 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR) ...................... 200
13.3 Internal Clock and External Clock Operations of 16-bit Reload Timer .............................................. 201
13.4 Underflow Operation of 16-bit Reload Timer ..................................................................................... 203
13.5 Output Pin Functions of 16-bit Reload Timer ..................................................................................... 204
13.6 Counter Operation State .................................................................................................................... 205
CHAPTER 14 8/16-BIT PPG ............................................................................................ 207
14.1 Outline of 8/16-bit PPG ...................................................................................................................... 208
14.2 Block Diagram of 8/16-bit PPG .......................................................................................................... 209
14.3 8/16-bit PPG Registers ...................................................................................................................... 211
14.3.1 PPG0 Operation Mode Control Register (PPGC0) ....................................................................... 212
14.3.2 PPG1 Operation Mode Control Register (PPGC1) ....................................................................... 214
14.3.3 PPG0, 1 Clock Selection Register (PPG0/1) ................................................................................ 217
14.3.4 Reload Register (PRLL/PRLH) ..................................................................................................... 219
14.4 Operations of 8/16-bit PPG ................................................................................................................ 220
14.5 Selecting a Count Clock for 8/16-bit PPG .......................................................................................... 222
14.6 Controlling Pin Output of 8/16-bit PPG Pulses .................................................................................. 223
14.7 8/16-bit PPG Interrupts ...................................................................................................................... 224
14.8 Initial Values of 8/16-bit PPG Hardware ............................................................................................ 225
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CHAPTER 15 DELAYED INTERRUPT ............................................................................ 227
15.1 Outline of Delayed Interrupt Module ................................................................................................. 228
15.2 Delayed Interrupt Register ................................................................................................................ 229
15.3 Delayed Interrupt Operation .............................................................................................................. 230
CHAPTER 16 DTP/EXTERNAL INTERRUPTS ............................................................... 231
16.1
16.2
16.3
16.4
16.5
Outline of DTP/External Interrupts ....................................................................................................
DTP/External Interrupt Registers ......................................................................................................
Operations of DTP/External Interrupts ..............................................................................................
Switching between External Interrupt and DTP Requests ................................................................
Notes on Using DTP/External Interrupts ...........................................................................................
232
234
236
238
239
CHAPTER 17 A/D CONVERTER ..................................................................................... 241
17.1 Features of A/D Converter ................................................................................................................
17.2 Block Diagram of A/D Converter .......................................................................................................
17.3 A/D Converter Registers ...................................................................................................................
17.3.1 Control Status Registers (ADCS0) ...............................................................................................
17.3.2 Control Status Register (ADCS1) ................................................................................................
17.3.3 Data Registers (ADCR1 and ADCR0) .........................................................................................
17.4 Operations of A/D Converter .............................................................................................................
17.5 Conversion Using EI2OS ..................................................................................................................
17.5.1 Starting EI2OS in Single Mode ...................................................................................................
17.5.2 Starting EI2OS in Continuous Mode ............................................................................................
17.5.3 Starting EI2OS in Stop Mode .......................................................................................................
17.6 Conversion Data Protection ..............................................................................................................
242
244
245
246
249
252
254
256
257
259
261
263
CHAPTER 18 UART0 ...................................................................................................... 265
18.1 Feature of UART0 .............................................................................................................................
18.2 UART0 Block Diagram ......................................................................................................................
18.3 UART0 Registers ..............................................................................................................................
18.3.1 Serial Mode Control Register 0 (UMC0) ......................................................................................
18.3.2 Status Register 0 (USR0) ............................................................................................................
18.3.3 Input Data Register 0 (UIDR0) and Output Data Register 0 (UODR0) ........................................
18.3.4 Rate and Data Register 0 (URD0) ...............................................................................................
18.4 UART0 Operation .............................................................................................................................
18.5 Baud Rate .........................................................................................................................................
18.6 Internal and External Clock ...............................................................................................................
18.7 Transfer Data Format ........................................................................................................................
18.8 Parity Bit ............................................................................................................................................
18.9 Interrupt Generation and Flag Set Timings .......................................................................................
18.9.1 Flag Set Timings for a Receive Operation (in Mode 0, 1, or 3) ....................................................
18.9.2 Flag Set Timings for a Receive Operation (in Mode 2) ................................................................
18.9.3 Flag Set Timings for a Transmit Operation ..................................................................................
18.9.4 Status Flag During Transmit and Receive Operation ..................................................................
18.10 UART0 Application Example .............................................................................................................
266
267
268
269
271
273
274
276
277
280
281
282
283
284
285
286
287
288
CHAPTER 19 UART1 (SCI) ............................................................................................. 291
19.1 Features of UART1 ........................................................................................................................... 292
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19.2 UART1 Block Diagram ....................................................................................................................... 293
19.3 UART1 Registers ............................................................................................................................... 294
19.3.1 Serial Mode Register 1 (SMR1) .................................................................................................... 295
19.3.2 Serial Control Register 1 (SCR1) ................................................................................................. 297
19.3.3 Serial Input Data Register 1 (SIDR1) / Serial Output Data Register 1 (SODR1) .......................... 299
19.3.4 Serial Status Register 1 (SSR1) ................................................................................................... 300
19.3.5 UART1 Prescaler Control Register (U1CDCR) ............................................................................ 302
19.4 UART1 Operating Modes and Clock Selection .................................................................................. 303
19.4.1 Asynchronous (Start-Stop Synchronized) Mode .......................................................................... 307
19.4.2 CLK Synchronous Mode ............................................................................................................... 308
19.5 UART1 Flags and Interrupt Sources .................................................................................................. 310
19.6 UART1 Interrupts and Flag Set Timing .............................................................................................. 311
19.7 Negative Clock Operation .................................................................................................................. 314
19.8 UART1 Sample Applications and Precautionary Information ............................................................ 315
CHAPTER 20 SERIAL I/O ................................................................................................ 317
20.1 Outline of Serial I/O ........................................................................................................................... 318
20.2 Serial I/O Registers ............................................................................................................................ 319
20.2.1 Serial Mode Control Status Register (SMCS) .............................................................................. 320
20.2.2 Serial Shift Data Register (SDR) .................................................................................................. 325
20.2.3 Serial I/O Prescaler (SCDCR) ...................................................................................................... 326
20.3 Serial I/O Operation ........................................................................................................................... 327
20.3.1 Shift Clock .................................................................................................................................... 328
20.3.2 Serial I/O Operation ...................................................................................................................... 329
20.3.3 Shift Operation Start/Stop Timing ................................................................................................. 331
20.3.4 Interrupt Function of the Serial I/O Interface ................................................................................ 334
20.4 Negative Clock Operation .................................................................................................................. 335
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION .......................................... 337
21.1
21.2
21.3
21.4
Overview of the Address Match Detection Function .......................................................................... 338
Registers of the Address Match Detection Function .......................................................................... 339
Operation of the Address Match Detection Function ......................................................................... 341
Example of the Address Match Detection Function ........................................................................... 342
CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE ........................... 345
22.1 Outline of ROM Mirroring Function Selection Module ....................................................................... 346
22.2 ROM Mirroring Function Selection Register (ROMM) ....................................................................... 347
CHAPTER 23 1M/2M-BIT FLASH MEMORY ................................................................... 349
23.1 Outline of 1M/2M-bit Flash Memory ................................................................................................... 350
23.2 Sector Configuration of the Flash Memory ........................................................................................ 351
23.3 Write/Erase Modes ............................................................................................................................ 352
23.4 Flash Memory Control Status Register (FMCS) ................................................................................ 354
23.5 Starting the Flash Memory Automatic Algorithm ............................................................................... 356
23.6 Confirming the Automatic Algorithm Execution State ........................................................................ 358
23.6.1 Data Polling Flag (DQ7) ............................................................................................................... 360
23.6.2 Toggle Bit Flag (DQ6) ................................................................................................................... 362
23.6.3 Timing Limit Exceeded Flag (DQ5) .............................................................................................. 363
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23.6.4 Sector Erase Timer Flag (DQ3) ...................................................................................................
23.6.5 Toggle Bit 2 Flag (DQ2) ...............................................................................................................
23.7 Detailed Explanation of Writing to and Erasing Flash Memory .........................................................
23.7.1 Setting The Read/Reset State .....................................................................................................
23.7.2 Writing Data .................................................................................................................................
23.7.3 Erasing All Data (Erasing Chips) .................................................................................................
23.7.4 Erasing Optional Data (Erasing Sectors) .....................................................................................
23.7.5 Suspending Sector Erase ............................................................................................................
23.7.6 Restarting Sector Erase ...............................................................................................................
23.8 Notes on using 1M/2M-bit Flash Memory .........................................................................................
23.9 Flash Security Feature ......................................................................................................................
23.10 Example of Programming 1M/2M-bit Flash Memory .........................................................................
CHAPTER 24 EXAMPLES OF MB90F438L(S)/F439(S) SERIAL PROGRAMMING
CONNECTION
24.1
24.2
24.3
24.4
Basic Configuration of MB90F438L(S)/F439(S) Serial Programming Connection ...........................
Example of Serial Programming Connection (User Power Supply Used) ........................................
Example of Serial Programming Connection (Power Supplied from the Programmer) ....................
Example of Minimum Connection to the Flash Microcomputer Programmer
(User Power Supply Used)
24.5 Example of Minimum Connection to the Flash Microcomputer Programmer
(Power Supplied from the Programmer)
364
366
368
369
370
372
373
375
376
377
379
380
385
386
390
392
394
396
APPENDIX .......................................................................................................................... 399
APPENDIX A I/O Maps ...............................................................................................................................
APPENDIX B Instructions ...........................................................................................................................
B.1 Instruction Types ............................................................................................................................
B.2 Addressing .....................................................................................................................................
B.3 Direct Addressing ...........................................................................................................................
B.4 Indirect Addressing .........................................................................................................................
B.5 Execution Cycle Count ...................................................................................................................
B.6 Effective Address Field ...................................................................................................................
B.7 How to Read the Instruction List ....................................................................................................
B.8 F2MC-16LX Instruction List ............................................................................................................
B.9 Instruction Map ...............................................................................................................................
400
408
409
410
412
418
426
429
430
433
447
INDEX ...................................................................................................................................469
x
Main changes in this edition
Page
408 to 468
Changes (For details, refer to main body.)
Changed the entire part of "APPENDIX B Instructions"
The vertical lines marked in the left side of the page show the changes.
xi
xii
CHAPTER 1
OVERVIEW
This chapter explains the features and basic specifications of the MB90435 series
products.
1.1 "Product Overview"
1.2 "Features"
1.3 "Block Diagram"
1.4 "Package Dimensions"
1.5 "Pin Assignment"
1.6 "Pin Functions"
1.7 "Input/Output Circuits"
1.8 "Handling the Device"
1
CHAPTER 1 OVERVIEW
1.1
Product Overview
The following table provides a quick outlook of the MB90435 Series
■ Overview of MB90435 series products
Table 1.1-1 Overview
Features
MB90V540G
MB90F438L(S)/F439(S)
MB90437L(S)*1/438L(S)/439(S)
F2MC-16LX CPU
CPU
System clock
On-chip PLL clock multiplier (x1, x2, x3, x4, 1/2 when PLL stop)
Minimum instruction execution time: 62.5 ns (4 MHz osc. PLL x4)
ROM capacity
External
Flash memory
MB90F438L(S): 128 Kbytes
MB90F439(S): 256 Kbytes
MB90437L(S)*1: 64 Kbytes
MB90438L(S): 128 Kbytes
MB90439(S): 256 Kbytes
RAM capacity
8 Kbytes
MB90F438L(S): 4K bytes
MB90F439(S): 6K bytes
MB90437L(S)*1: 2 Kbytes
MB90438L(S): 4 Kbytes
MB90439(S): 6 Kbytes
MB90F438L/F439:
Two clocks system
MB90F438LS/F439S:
One clock system
MB90437L*1/438L/439:
Two clocks system
MB90437LS*1/438LS/439S:
One clock system
Clocks
Package
Emulatorspecific power
supply *2
Two clocks/One clock
system
PGA-256
QFP100, LQFP100
None
-
*1: Under development
*2: It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.
Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details.
2
1.2 Features
1.2
Features
Table 1.2-1 "MB90435 Series Features" lists the features of the MB90435 series.
■ Features
Table 1.2-1 MB90435 Series Features
Function
Feature
UART0
Full duplex double buffer
Supports asynchronous/synchronous (with start/stop bit) transfer
Baud rate: 4808/5208/9615/10417/19230/38460/62500/500000bps
(asynchronous)
500K/1M/2Mbps (synchronous) at System clock = 16MHz
UART1
(SCI)
Full duplex double buffer
Asynchronous (start-stop synchronized) and CLK-synchronous
communication
Baud rate: 1202/2404/4808/9615/192301/31250/38460/62500bps
(asynchronous)
62.5K/125K/250K/500K/1Mbps (synchronous) at 6,8,10,12,16 MHz
Serial IO
Transfer can be started from MSB or LSB
Supports internal clock synchronized transfer and external clock
synchronized transfer
Supports positive-edge and negative-edge clock synchronization
Baud rate: 31.25K/62.5K/125K/500K/1M/2M bps at System clock =
16MHz
A/D
Converter
10-bit or 8-bit resolution
8 input channels
Conversion time: 26.3μs (per one channel)
16-bit Reload
Timer
(2 channels)
Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = System
clock frequency)
Supports External Event Count function
16-bit
I/O Timer
Signals an interrupt when overflow
Supports Timer Clear when a match with Output Compare
(Channel 0)
Operation clock freq.: fsys/22, fsys/24, fsys/26, fsys/28(fsys =
System clock freq.)
16-bit
Output Compare
(4 channels)
Signals an interrupt when a match with 16-bit IO Timer
Four 16-bit compare registers
A pair of compare registers can be used to generate an output
signal
16-bit
Input Capture
(8 channels)
Rising edge, falling edge or rising & falling edge sensitive
Four 16-bit Capture registers
Signals an interrupt upon external event
3
CHAPTER 1 OVERVIEW
Table 1.2-1 MB90435 Series Features (Continued)
Function
Feature
8/16-bit
Programmable
Pulse Generator
(4 channels)
Supports 8-bit and 16-bit operation modes
Eight 8-bit reload counters
Eight 8-bit reload registers for L pulse width
Eight 8-bit reload registers for H pulse width
A pair of 8-bit reload counters can be configured as one 16-bit
reload counter or as 8-bit prescaler plus 8-bit reload counter
4 output pins
Operation clock freq.: fsys, fsys/21, fsys/22, fsys/23, fsys/24 or
[email protected]=4MHz
(fsys = System clock frequency, fosc = Oscillation clock frequency)
External Interrupt
Can be programmed edge sensitive or level sensitive
External bus
interface
External access using the selectable 8-bit or 16-bit bus is enabled
(external bus mode).
IO Ports
Virtually all external pins can be used as general purpose IO
All push-pull outputs and schmitt trigger inputs
Bit-wise programmable as input/output or peripheral signal
32 kHz subclock
Subclock for low-power operation
Flash Memory
Supports automatic programming, Embedded AlgorithmTM *1
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles: 10,000 times
Data retention time: 10 years
Boot block configuration
Erase can be performed on each block
Block protection by externally programmed voltage
*1: Embeded Algorithm is a trade mark of Advanced Micro Devices Inc.
4
1.3 Block Diagram
1.3
Block Diagram
Figure 1.3-1 "Block Diagram" shows a block diagram of the MB90435 series.
■ Block Diagram
Figure 1.3-1 Block Diagram
X0, X1
X0A, X1A
RST
HST
Clock
Controller
16LX
CPU
IO Timer
RAM
2K/4K/6K
Input
Capture
8ch
IN6/OUT2, IN7/OUT3
ROM
64K/128K/256K
SOT0
SCK0
SIN0
UART0
Prescaler
Output
Compare
4ch
Internal data bus
Prescaler
8/16-bit
PPG
4ch
16-bit Reload
Timer 2ch
SOT1
SCK1
SIN1
UART1
(SCI)
Serial I/O
OUT0, OUT1
PPG0 to PPG3
TIN0, INT1
TOT0, TOT1
AD00 to AD15
A16 to A23
Prescaler
SCK2
SOT2
SIN2
IN0 to IN5
External
bus
interface
ALE
RD
WRL/WR
WRH
HRQ
HAK
RDY
AVCC
AVSS
AN0 to AN7
AVRH
AVRL
ADTG
CLK
10-bit
ADC 8ch
External
Interrupt
8 ch
INT0 to INT7
5
CHAPTER 1 OVERVIEW
1.4
Package Dimensions
Figure 1.4-1 "FPT-100P-M06 Package Dimensions" shows the package dimensions of
the FPT-100P-M06. Figure 1.4-2 "FPT-100P-M05 Package Dimensions" shows the
package dimensions of the FPT-100P-M05
Note that the dimensions show below are reference dimensions.
For formal dimensions of each package, contact us.
■ FPT-100P-M06 Package Dimensions
Figure 1.4-1 FPT-100P-M06 Package Dimensions
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note: Pins width and pins thickness include plating thickness.
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
"A"
C
6
0.25(.010)
+0.35
3.00 −0.20
+.014
.118 −.008
(Mounting height)
0~8°
31
2001 FUJITSU LIMITED F100008S-c-4-4
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches).
1.4 Package Dimensions
■ FPT-100P-M05 Package Dimensions
Figure 1.4-2 FPT-100P-M05 Package Dimensions
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width
package length
14.0
14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.65g
(FPT-100P-M05)
100-pin plastic LQFP
(FPT-100P-M05)
Pins width and pins thickness include plating thickness.
16.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
100
26
"A"
1
25
0.50(.020)
C
+.008
1.50
.059
(Mounting height)
INDEX
2000 FUJITSU LIMITED F100007S-3c-5
0.20±0.05
(.008±.002)
0.08(.003)
M
0.145±0.055
(.0057±.0022)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
7
CHAPTER 1 OVERVIEW
1.5
Pin Assignment
Figure 1.5-1 "Pin Assignment of FPT-100P-M06"shows the pin assignments of the FPT100P-M06. Figure 1.5-2 "Pin Assignment of FPT-100P-M05"shows the pin assignments
of the FPT-100P-M05.
■ Pin Assignment
Figure 1.5-1 Pin Assignment of FPT-100P-M06
MB90435 series
8
1.5 Pin Assignment
100 P21/A17
99 P20/A16
98 P17/AD15
97 P16/AD14
96 P15/AD13
95 P14/AD12
94 P13/AD11
93 P12/AD10
92 P11/AD09
91 P10/AD08
90 P07/AD07
89 P06/AD06
88 P05/AD05
87 P04/AD04
86 P03/AD03
85 P02/AD02
84 P01/AD01
83 P00/AD00
82 VCC
81 X1
80 X0
79 VSS
78 X0A
77 X1A
76 PA0
Figure 1.5-2 Pin Assignment of FPT-100P-M05
LQFP-100
MB90435 series
(TOP VIEW)
FPT-100P-M05
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RST
P97
P96
P95
P94
P93/INT3
P92/INT2
P91/INT1
P90/INT0
P87/TOT1
P86/TIN1
P85/OUT1
P84/OUT0
P83/PPG3
P82/PPG2
P81/PPG1
P80/PPG0
P77/OUT3/IN7
P76/OUT2/IN6
P75/IN5
P74/IN4
P73/IN3
P72/IN2
P71/IN1
P70/IN0
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P50/SIN2
P51/INT4
P52/INT5
P53/INT6
P54/INT7
P55/ADTG
AVCC
AVRH
AVRL
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
VSS
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P56/TIN0
P57/TOT0
MD0
MD1
MD2
HST
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
P30/ALE
P31/RD
VSS
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SOT0
P41/SCK0
P42/SIN0
P43/SIN1
P44/SCK1
VCC
P45/SOT1
P46/SOT2
P47/SCK2
C
9
CHAPTER 1 OVERVIEW
1.6
Pin Functions
Table 1.6-1 "Pin Functions" lists pin names, circuit types, and pin functions.
■ Pin Functions
Table 1.6-1 Pin Functions
Pin No.
Pin name
LQFP
QFP
80, 81
82, 83
78
80
Circuit
type
X0, X1
X0A
Pins for high-speed oscillation
A
(oscillation)
Pin for low-speed oscillation. Pull-down the pin externally for
one clock system parts.
77
79
75
77
RST
B
External reset request input pin
50
52
HST
C
Hardware standby input pin
Pin for low-speed oscillation. Leave the pin open for one clock
system parts.
X1A
General-purpose I/O ports with programmable pull-up function.
These functions can be used in single-chip mode.
P00 to P07
83 to 90
85 to 92
I
I/O pins for lower 8 bits of external address/data bus. These
functions can be used when the external bus is enabled.
AD00 to AD07
General-purpose I/O ports with programmable pull-up function.
These functions can be used in single-chip mode.
P10 to P17
91 to 98
93 to 100
I
I/O pins for upper 8 bits of external address/data bus. These
functions can be used when the external bus is enabled.
P08 to AD15
General-purpose I/O ports with programmable pull-up function.
These functions can be used in single-chip mode.
P20 to P27
99 to 6
1 to 8
I
I/O pins for A16 to A23 of external address bus. These
functions can be used when the external bus is enabled.
A16 to A23
General-purpose I/O port with programmable pull-up function.
This function can be used in single-chip mode.
P30
7
8
9
I
ALE
Output pin that enables address latch. This function can be
used when the external bus is enabled.
P31
General-purpose I/O port with programmable pull-up function.
This function can be used in single-chip mode.
10
I
RD
10
Function
Read strobe output pin for data bus. This function can be used
when the external bus is enabled.
1.6 Pin Functions
Table 1.6-1 Pin Functions (Continued)
Pin No.
Pin name
LQFP
QFP
Circuit
type
General-purpose I/O port with programmable pull-up function.
This function can be used in single-chip mode or when WR/WRL
pin output is disabled.
P32
10
12
WRL
I
WR
13
I
WRH
P34
12
13
14
15
16
14
I
Write strobe output pin for upper 8 bits of data bus. This
function can be used when the external pin is enabled, 16-bit
mode for external bus is selected, or the WRH pin output is
enabled.
General-purpose I/O port with programmable pull-up function.
This function can be used in single-chip mode or when the hold
function is disabled.
HRQ
Hold request input pin. This function can be used when both the
external bus and hold function are enabled.
P35
General-purpose I/O port with programmable pull-up function.
This function can be used in single-chip mode or when the hold
function is disabled.
15
I
HAK
Hold acknowledge output pin. This function can be used when
both the external bus and hold function are enabled.
P36
General-purpose I/O port with programmable pull-up function.
This function can be used in single-chip mode or when the
external ready function is disabled.
16
I
RDY
Ready input signal. This function can be used when both the
external bus and external ready function are enabled.
P37
General-purpose I/O port with programmable pull-up function.
This function can be used in single-chip mode or when the hold
function is disabled.
17
H
CLK
Clock output pin. This function can be used when both the
external bus and clock output are enabled.
P40
General-purpose I/O port. This function can be used when
UART0 disables serial data output.
18
G
UART0 serial data output pin. This function can be used when
UART0 enables serial data output.
SOT0
General-purpose I/O port. This function can be used when
UART0 disables clock output.
P41
17
Write strobe output pin for data bus. This function can be used
when both the external bus and WR/WRL pin are enabled.
WRL is used for strobe write for the lower 8 bits of the data bus
in 16-bit access mode. WR is used for strobe write for 8 bits of
the data bus in 8-bit access mode.
General-purpose I/O port with programmable pull-up function.
This function can be used in single-chip mode and 8-bit mode
for the external bus or when WRH pin output is enabled.
P33
11
Function
19
G
SCK0
UART0 clock I/O pin. This function can be used when UART0
enables clock output.
11
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Functions (Continued)
Pin No.
Pin name
LQFP
QFP
18
20
Circuit
type
P42
19
20
General-purpose I/O port. This function can always be used.
G
SIN0
UART0 serial data input pin. Set the corresponding DDR
register to input if this function is used.
P43
General-purpose I/O port. This function can always be used.
21
G
SIN1
UART1 serial data input pin. Set the corresponding DDR
register to input if this function is used.
P44
General-purpose I/O port. This function can be used when
UART1 disables clock output.
22
G
UART1 clock pulse I/O pin. This pin can be used when UART1
enables clock output.
SCK1
General-purpose I/O port. This function can be used when
UART1 disables serial data output.
P45
22
24
G
UART1 serial data output pin. This function can be used when
UART1 enables serial data output.
SOT1
General-purpose I/O port. This function can be used when
serial I/O disables serial data output.
P46
23
25
G
Serial data output pin for I/O serial data. This function can be
used when serial I/O enables serial data output.
SOT2
General-purpose I/O port. This function can be used when
serial I/O disables clock output.
P47
24
26
G
Clock pulse I/O pin of serial I/O. This function can be used
when serial I/O enables clock output.
SCK2
P50
26
28
General-purpose I/O port. This function can always be used.
D
SIN2
29 to 32
D
External interrupt request input pins for INT4 and INT7. Set the
corresponding DDR register to input if this function is used.
INT4 to INT 7
P55
31
36 to 39
33
General-purpose I/O port. This function can always be used.
D
ADTG
Trigger input pin for A/D converter. Set the corresponding DDR
register to input if this function is used.
P60 to P63
General-purpose I/O ports. These functions can be used when
ports are specified in the register that enables analog input.
38 to 41
E
AN0 to AN3
12
Serial data input pin for serial I/O. Set the corresponding DDR
register to input if this function is used.
General-purpose I/O ports. These functions can always be
used.
P51 to P54
27 to 30
Function
Analog input pins for A/D converter. These functions can be
used when AD is specified in the register that enables analog
input.
1.6 Pin Functions
Table 1.6-1 Pin Functions (Continued)
Pin No.
Pin name
LQFP
QFP
Circuit
type
General-purpose I/O ports. These functions can be used when
ports are specified in the register that enables analog input.
P64 to P67
41 to 44
45
46
43 to 46
E
AN4 to AN7
Analog input pins for A/D converter. These functions can be
used when AD is specified in the register that enables analog
input.
P56
General-purpose I/O port. This function can always be used.
47
D
TIN0
Event input pin for reload timer 0. Set the corresponding DDR
register to input if this function is used.
P57
General-purpose I/O port. This function can be used when
reload timer 0 disables output.
48
D
Output pin for reload timer 0. This function can be used when
reload timer 0 enables output.
TOT0
General-purpose I/O ports. These functions can always be
used.
P70 to P75
51 to 56
57 to 58
59 to 62
53 to 58
59 to 60
D
IN0 to IN5
Data sample input pins from which ICU0 to ICU5 capture data is
input. Set the corresponding DDR register to input if this
function is used.
P76 to P77
General-purpose I/O ports. These functions can be used when
the OCU disables waveform output.
OUT2 to
OUT3
Waveform output pins from which OCU2 and OCU3 comparison
data is output. These functions can be used when the OCU
enables waveform output.
D
IN6 to IN7
Data sample input pins from which ICU6 and ICU7 capture data
is input. Set the corresponding DDR register to input and
disable the OCU waveform output if this function is used.
P80 to P83
General-purpose I/O ports. These functions can be used when
PPG disables waveform output.
61 to 64
D
PPG0 to
PPG3
PPG output pins. These functions can be used when PPG
enables waveform output.
General-purpose I/O ports. These functions can be used when
the OCU disables waveform output.
P84 to P85
63 to 64
65 to 66
D
OUT0 to
OUT1
P86
65
66
Function
67
Waveform output pins from which OCU0 and OCU1 comparison
data is output. These functions can be used when OCU enables
waveform output.
General-purpose I/O port. This function can always be used.
D
TIN1
Event input pin for reload timer 1. Set the corresponding DDR
register to input if this function is used.
P87
General-purpose I/O port. This function can be used when
reload timer 0 disables output.
68
D
TOT1
Output pin for reload timer 1. This function can be used when
reload timer 1 enables output.
13
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Functions (Continued)
Pin No.
Pin name
LQFP
QFP
Circuit
type
General-purpose I/O ports. These functions can always be
used.
P90 to P93
67 to 70
69 to 72
D
External interrupt request input pins for INT0 to INT3. Set the
corresponding DDR register to input if this function is used.
INT0 to INT3
14
Function
71
73
P94
D
General-purpose I/O port.
72
74
P95
D
General-purpose I/O port.
73
75
P96
D
General-purpose I/O port.
74
76
P97
D
General-purpose I/O port.
76
78
PA0
D
General-purpose I/O port.
32
34
AVCC
Power
supply
Power supply input pin for A/D converter. See Section 1.8
35
37
AVSS
Power
supply
Dedicated ground pin for A/D converter
33
35
AVRH
Power
supply
Reference voltage input pin for A/D converter. See Section 1.8
34
36
AVRL
Power
supply
Reference low-voltage input pin for A/D converter
47
48
49
50
MD0
MD1
C
Operating-mode-dedicated input pins. Connect these pins
directly to VCC or VSS.
49
51
MD2
F
Operating-mode-dedicated input pin. Connect this pin directly to
VCC or VSS.
25
27
C
-
Power capacitor pin. Connect this pin externally to a 0.1 μF
ceramic capacitor.
21, 82
23, 84
VCC
Power
supply
Power (5.0V) input pin for digital circuit
9, 40
79
11, 42
81
VSS
Power
supply
Ground power (0.0V) pins for digital circuit
"Handling the Device".
"Handling the Device".
1.7 I/O Circuits
1.7
I/O Circuits
Table 1.7-1 "I/O Circuits" shows input/output circuits.
■ I/O Circuits
Table 1.7-1 I/O Circuits
Circuit type
Diagram
Remarks
A
X1, X1A
•
Oscillation feedback resistor:
Approx. 1 MΩ (High-speed
oscillation)
Approx. 10 MΩ (Low-speed
oscillation)
•
•
Hysteresis input
Pull-up resistor: Approx. 50 kΩ
•
Hysteresis input
Oscillation feedback resistor
X0, X0A
Standby control signal
B
R (pull-up)
R
HYS
R
HYS
C
15
CHAPTER 1 OVERVIEW
Table 1.7-1 I/O Circuits (Continued)
Circuit type
Diagram
Remarks
D
•
•
CMOS output
Hysteresis input
•
•
•
CMOS output
Hysteresis input
Analog input
•
•
Hysteresis input
Pull-down resistor:
Approx. 50 kΩ (except flash device
product)
•
•
•
CMOS output
Hysteresis input
TTL input (for flash device product in
flash write mode only)
P-ch
N-ch
R
HYS
E
Vcc
P-ch
N-ch
P-ch
Analog input
N-ch
HYS
R
F
R
HYS
R (pull-down)
G
Vcc
P-ch
N-ch
HYS
R
TTL
R
16
1.7 I/O Circuits
Table 1.7-1 I/O Circuits (Continued)
Circuit type
Diagram
Remarks
H
CNTL
Vcc
Vcc
P-ch
•
•
•
CMOS output
Hysteresis input
Programmable pull-up resistor:
Approx. 50 kΩ
•
•
•
CMOS output
Hysteresis input
TTL input (for flash device product in
flash write mode only)
Programmable pull-up resistor:
Approx. 50 kΩ
N-ch
HYS
R
I
Vcc
CNTL
Vcc
P-ch
•
N-ch
HYS
R
TTL
R
17
CHAPTER 1 OVERVIEW
1.8
Handling the Device
When handling devices, be careful about the following:
• Preventing latch-up
• Treatment of unused pins
• Using external clock
• Power supply pins (VCC/VSS)
•
•
•
•
•
•
•
•
•
•
•
Pull-up/down resistors
Crystal Oscillator Circuit
Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Connection of Unused Pins of A/D Converter
N.C. Pin
Notes on Energization
Use of the subclock
Initialization
Directions of "DIV A, Ri" and "DIVW A, RWi" instructions
Using REALOS
Notes on during operation of PLL clock mode
■ Handling the Device
❍ Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions:
•
A voltage higher than Vcc or lower than Vss is applied to an input or output pin.
•
A voltage higher than the rated voltage is applied between VCC and VSS.
•
The AVcc power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the
device.
For the same reason, also be careful not let the analog power-supply voltage (AVCC, AVRH)
exceed the digital power-supply voltage.
❍ Treatment of unused pins
Unused input pins left open may cause abnormal operation, or latch-up leading to permanent
damage. Unused input pins should be pulled down through at least 2KΩ resistance.
Unused input/output pins may be left open in output state, but if such pins are in input state they
should be handled in the same way as input pins.
18
1.8 Handling the Device
❍ Using external clock
To use external clock, drive X0 pin only and leave X1 pin.
Below is a diagram of how to use external clock.
Figure 1.8-1 Example of Using External Clock
MB90435 series
X0
Open
X1
❍ Power supply pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected
in the device to avoid abnormal operations including latch-up. However connect the pins to
external power and ground line to lower the electro-magnetic emission level, to prevent
abnormal operation of signals caused by the rise in the ground level, and to conform to the total
current rating.
Make sure to connect VCC and VSS pins via the lowest impedance to power lines.
It is recommended to provide a bypass capacitor of around 0.1 μF between VCC and VSS pins
near the device.
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90435
Series
Vcc
Vss
Vss
Vcc
❍ Pull-up/down resistors
The MB90435 series does not support internal pull-up/down resistors (except Port0 - Port3:pullup resistors). Use external components where needed.
19
CHAPTER 1 OVERVIEW
❍ Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to
provide bypass capacitors via the shortest distances from X0, X1 pins, crystal oscillator (or
ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation
circuits do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins
with a ground area for stabilizing the operation.
❍ Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs
(AN0 to AN7) after turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this
case, make sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and
digital power supplies simultaneously is acceptable).
❍ Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.
❍ N.C. Pin
The N.C. (internally connected) pin must be opened for use.
❍ Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during
energization at 50 μs or more (0.2 V to 2.7 V).
❍ Use of the subclock
Use the one clock system parts when the subclock is not used. In that case, pull-down the pin
X0A and leave the pin X1A open. When using the one clock system parts, a 32 kHz oscillator
has to be connected to the X0A and X1A pins.
❍ Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To
initialize these registers, please turn on the power again.
❍ Directions of "DIV A, Ri" and "DIVW A, RWi" instructions
In the Signed multiplication and division instructions ("DIV A, Ri" and "DIVW A, RWi"), the value
of the corresponding bank register (DTB, ADB, USB, SSB) is set in "00h".
If the values of the corresponding bank registers (DTB,ADB,USB,SSB) are set to other than
"00H", the remainder by the execution result of the instruction is not stored in the register of the
instruction operand.
❍ Using REALOS
The use of EI2OS is not possible with the REALOS real time operating system.
❍ Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the selfoscillating circuit even when there is no external oscillator or external clock input is stopped.
Performance of this operation, however, cannot be guaranteed.
20
CHAPTER 2
CPU
This chapter explains the CPU.
2.1 "Outline of CPU"
2.2 "Memory Space"
2.3 "Memory Space Map"
2.4 "Linear Addressing"
2.5 "Bank Addressing Types"
2.6 "Multi-byte Data in Memory Space"
2.7 "Registers"
2.8 "Register Bank"
2.9 "Prefix Codes"
2.10 "Interrupt Disable Instructions"
2.11 "Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions"
21
CHAPTER 2 CPU
2.1
Outline of CPU
The F2MC-16LX CPU core is a 16-bit CPU designed for applications that require highspeed real-time processing, such as home-use or vehicle-mounted electronic
appliances. The F2MC-16LX instruction set is designed for controller applications, and
is capable of high-speed, highly efficient control processing.
■ Outline of CPU
In addition to 16-bit data, the F2MC-16LX CPU core can process 32-bit data by using an internal
32-bit accumulator (32-bit data can be processed by some instructions). Memory space of up to
16 megabytes (expandable) can be accessed by either the linear or bank method. The
instruction set, based on the F2MC-8 A-T architecture, has been made richer by adding
instructions that are compatible with high-level languages, expanding addressing modes,
improving the multiplication and division instructions, and enhancing bit processing.
The features of the F2MC-16LX CPU are explained below.
❍ Minimum instruction execution time: 62.5 ns (at 4-MHz oscillation, 4 times clock
multiplication)
❍ Maximum memory space: 16 Mbytes, accessed in linear or bank mode
❍ Instruction set optimized for controller applications
•
Rich data types: Bit, byte, word, long word
•
Extended addressing modes: 23 types
•
High-precision operation (32-bit length) based on 32-bit accumulator
❍ Powerful interrupt functions
Eight priority levels (programmable)
❍ CPU-independent automatic transfer
Up to 16 channels of the extended intelligent I/O service
❍ Instruction set compatible with high-level language (C)/multitasking
System stack pointer/instruction set symmetry/barrel-shift instructions
❍ Improved execution speed: 4-byte queue
22
2.2 Memory Space
2.2
Memory Space
An F2MC-16LX CPU has a 16-megabyte memory space. All data items, programs, and
input-outputs managed by F2MC-16LX CPU are located in this 16-megabyte memory
space. The CPU can access resources by indicating their addresses using a 24-bit
address bus.
■ Outline of CPU Memory Space
Figure 2.2-1 "Sample Relationship between F2MC-16LX System and Memory Map" shows a
sample relationship between the F2MC-16LX system and memory map.
Figure 2.2-1 Sample Relationship between F2MC-16LX System and Memory Map
FFFFFF H
Program
FF8000H
Data
810000H
Interrupt
800000H
F2MC-16LX
CPU
Program area
Data area
Peripheral
circuits
[Device]
Generalpurpose ports
0000C0H
0000B0 H
000020H
Interrupt controller
Peripheral circuits
General-purpose ports
000000H
■ Address Generation Types
The F2MC-16LX has the following two addressing:
❍ Linear addressing
An entire 24-bit address is specified by an instruction.
❍ Bank addressing
The eight high-order bits of an address are specified by an appropriate bank register, and the
remaining 16 low-order bits are specified by an instruction.
23
CHAPTER 2 CPU
2.3
Memory Space Map
The memory space of the MB90435 Series is shown in Figure 2.3-1 "Memory Space
Map".
■ Memory Space Map
The high-order portion of bank 00 gives the image of the FF bank ROM to make the small
model of the C compiler effective. Since the low-order 16 bits are the same, the table in ROM
can be referenced without using the far specification in the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.
The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank
00.
The image between FF4000H and FFFFFFH is visible in bank 00, while the image between
FF0000H and FF3FFFH is visible only in bank FF.
Figure 2.3-1 Memory Space Map
MB90437L(S) *1
MB90V540G
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
ROM (FF bank)
FF0000H
ROM (FF bank)
ROM (FE bank)
FF0000H
FEFFFFH
FE0000H
ROM (FD bank)
External access
memory
ROM (FF bank)
ROM (FE bank)
External access
memory
ROM (FC bank)
MB90F439(S)/439(S)
FFFFFFH
FFFFFFH
FFFFFFH
FFFFFFH
MB90F438L(S)/438L(S)
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
004000H
003FFFH
ROM (Image of
FF bank)
00FFFFH
004000H
003FFFH
0020FFH
001FF5H
001FF0H
External access
memory
003900H
002000H
External access
memory
004000H
003FFFH
ROM (Image of
FF bank)
0008FFH
000100H
External access memory
002000H
Peripheral
*1: Under development
Peripheral
004000H
003FFFH
ROM (FD bank)
ROM (FC bank)
External access
memory
Peripheral
002100H
External access
memory
0018FFH
RAM 6K
000100H
000100H
External access memory
External access memory
0000BFH
000000H
ROM (Image of
FF bank)
003900H
RAM 4K
External access memory
0000BFH
000000H
00FFFFH
Peripheral
003900H
0010FFH
RAM 2K
000100H
24
00FFFFH
ROM correction
RAM 8K
0000BFH
000000H
ROM (Image of
FF bank)
Peripheral
Peripheral
003900H
ROM (FE bank)
External access
memory
External access
memory
00FFFFH
ROM (FF bank)
Peripheral
0000BFH
000000H
Peripheral
2.4 Linear Addressing
2.4
Linear Addressing
There are two types of linear addressing:
• 24-bit operand specification: Directly specifies a 24-bit address using operands.
• 32-bit register indirect specification: Indirectly specifies the 24 low-order bits of a
32-bit general-purpose register value as the address.
■ 24-bit Operand Specification
Figure 2.4-1 "Example of Linear Method (24-bit Register Operand Specification)" shows an
example of 24-bit operand specification. Figure 2.4-2 "Example of Linear Method (32-bit
Register Indirect Specification") shows an example of 32-bit register indirect specification.
Figure 2.4-1 Example of Linear Method (24-bit Register Operand Specification)
JMPP 123456 H
Old program counter
+ program bank
17
17452D H
452D
JMPP 123456 H
123456 H
New program counter
+ program bank
12
Next instruction
3456
■ 32-bit Register Indirect Specification
Figure 2.4-2 Example of Linear Method (32-bit Register Indirect Specification)
MOV A, @RL1+7
Old AL
090700 H
XXXX
3A
+7
RL1
240906F9
(The high-order eight bits are ignored.)
New AL
003A
25
CHAPTER 2 CPU
2.5
Bank Addressing Types
In the bank method, the 16-Mbyte space is divided into 256 64-Kbyte banks. The
following five bank registers are used to specify the banks corresponding to each
space:
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional bank register (ADB)
■ Bank Addressing Types
❍ Program bank register (PCB)
The 64-Kbyte bank specified by the PCB is called a program (PC) space. The PC space
contains instruction codes, vector tables, and immediate value data, for example.
❍ Data bank register (DTB)
The 64-Kbyte bank specified by the DTB is called a data (DT) space. The DT space contains
readable/writable data, and control/data registers for internal and external resources.
❍ User stack bank register (USB)/system stack bank register (SSB)
The 64-Kbyte bank specified by the USP or SSP is called a stack (SP) space. The SP space is
accessed when a stack access occurs during a push/pop instruction or interrupt register saving.
The S flag in the condition code register determines the stack space to be accessed.
❍ Additional bank register (ADB)
The 64-Kbyte bank specified by the ADB is called an additional (AD) space. The AD space, for
example, contains data that cannot fit into the DT space.
Table 2.5-1 "Default Space" lists the default spaces used in each addressing mode, which are
pre-determined to improve instruction coding efficiency. To use a non-default space for an
addressing mode, specify a prefix code corresponding to a bank before the instruction. This
enables access to the bank space corresponding to the specified prefix code.
After reset, the DTB, USB, SSB, and ADB are initialized to 00H. The PCB is initialized to a value
specified by the reset vector. After reset, the DT, SP, and AD spaces are allocated in bank 00H
(000000H to 00FFFFH), and the PC space is allocated in the bank specified by the reset vector.
26
2.5 Bank Addressing Types
Table 2.5-1 Default Space
Default space
Program space
Addressing mode
PC indirect, program access, branch
Data space
Addressing mode using @RW0, @RW1, @RW4, or @RW5, @A, addr16,
and dir
Stack space
Addressing mode using PUSHW, POPW, @RW3, or @RW7
Additional space
Addressing mode using @RW2 or @RW6
Figure 2.5-1 "Physical Addresses of Each Space" is an example of a memory space divided into
register banks.
Figure 2.5-1 Physical Addresses of Each Space
FFFFFF H
Program space
FF0000 H
FF H
:
PCB (Program bank register)
B3 H
: ADB (Additional bank register)
92 H
: USB (User stack bank register)
68 H
: DTB (Data bank register)
4B H
: SSB (System stack bank register)
B3FFFF H
Additional space
Physical address
B30000 H
92FFFF H
User stack space
920000 H
68FFFF H
680000 H
Data space
4BFFFF H
System stack space
4B0000 H
000000 H
27
CHAPTER 2 CPU
2.6
Multi-byte Data in Memory Space
Data is written to memory from the low-order addresses. Therefore, for a 32-bit data
item, the low-order 16 bits are transferred before the high-order 16 bits.
If a reset signal is input immediately after the low-order bits are written, the high-order
bits might not be written.
■ Multi-byte Data Allocation in Memory Space
Figure 2.6-1 "Sample Allocation of Multi-byte Data in Memory" is a diagram of multi-byte data
configuration in memory. The low-order eight bits of a data item are stored at address n, then
address n+1, address n+2, address n+3, etc.
Figure 2.6-1 Sample Allocation of Multi-byte Data in Memory
MSB
H
LSB
01010101
11001100
11111111
00010100
01010101
11001100
11111111
Address n
00010100
L
■ Accessing Multi-byte Data
Fundamentally, accesses are made within a bank. For an instruction accessing a multi-byte
data item, address FFFFH is followed by address 0000H of the same bank. Figure 2.6-2
"Execution of MOVW A, 080FFFFH" is an example of an instruction accessing multi-byte data.
Figure 2.6-2 Execution of MOVW A, 080FFFFH
H
80FFFF H
AL before execution
??
AL after execution
23 H
??
01H
·
·
·
23 H
800000 H
L
28
01H
2.7 Registers
2.7
Registers
The F2MC-16LX registers are largely classified into two types: special registers in the
CPU and general-purpose registers in memory. The special registers are dedicated
internal hardware of the CPU, and they have specific use defined by the CPU
architecture. The general-purpose registers share the CPU address space with RAM.
The general-purpose registers are the same as the special registers in that they can be
accessed without using an address. The applications of the general-purpose registers
can be specified by the user however, as is ordinary memory space.
■ Special Registers
The F2MC-16LX CPU core has the following 13 special registers:
•
Accumulator (A=AH:AL): Two 16-bit accumulators (Can be used as a single 32-bit
accumulator.)
•
User stack pointer (USP): 16-bit pointer indicating the user stack area
•
System stack pointer (SSP): 16-bit pointer indicating the system stack area
•
Processor status (PS): 16-bit register indicating the system status
•
Program counter (PC): 16-bit register holding the address of the program
•
Program bank register (PCB): 8-bit register indicating the PC space
•
Data bank register (DTB): 8-bit register indicating the DT space
•
User stack bank register (USB): 8-bit register indicating the user stack space
•
System stack bank register (SSB): 8-bit register indicating the system stack space
•
Additional bank register (ADB): 8-bit register indicating the AD space
•
Direct page register (DPR): 8-bit register indicating a direct page
Figure 2.7-1 "Special Registers" is a diagram of the special registers.
29
CHAPTER 2 CPU
Figure 2.7-1 Special Registers
AH
AL
Accumulator
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
DPR
Direct page register
PCB
Program bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8 bit
16 bit
32 bit
■ General-purpose Registers
The F2MC-16LX general-purpose registers are located from addresses 000180H to 00037FH
(maximum configuration) of main storage. The register bank pointer (RP) indicates which of the
above addresses are currently being used as a register bank. Each bank has the following three
types of registers. These registers are mutually dependent as described in Figure 2.7-2
"General-purpose Registers".
•
R0 to R7: 8-bit general-purpose register
•
RW0 to RW7: 16-bit general-purpose register
•
RL0 to RL3: 32-bit general-purpose register
Figure 2.7-2 General-purpose Registers
MSB
LSB
16 bit
000180 H + RP × 10H
RW0
Low-order
RL0
First address of
general-purpose register
RW1
RW2
RL1
RW3
R1
R0
RW4
R3
R2
RW5
R5
R4
RW6
R7
R6
RW7
RL2
RL3
High-order
The relationship between the high-order and low-order bytes of a byte or word register is
expressed as follows:
RW (i + 4) = R (i x 2 + 1) x 256 + R (i x 2) [i=0 to 3]
The relationship between the high-order and low-order bytes of Rli and RW can be expressed
as follows:
RL (i) = RW (i x 2 + 1) x 65536+RW (i x 2) [i=0 to 3]
30
2.7 Registers
2.7.1
Accumulator (A)
The accumulator (A) register consists of two 16-bit arithmetic operation registers (AH
and AL), and is used as a temporary storage for operation results and transfer data.
■ Accumulator (A)
In 32-bit data processing, AH and AL are used together. Only AL is used for word processing in
16-bit data processing mode or for byte processing in 8-bit data processing mode (see Figure
2.7-3 "32-bit Data Transfer" and Figure 2.7-4 "AL-AH Transfer") . The data in the A register can
be operated upon with data in memory or with registers (Ri, RWi, or RLi). As with the F2MC-8L,
when a word or shorter data item is transferred to AL, the previous data item in AL is
automatically transferred to AH (data save function). The data save function and the operations
between AL and AH help to improve processing efficiency.
When a byte or shorter data item is transferred to AL, the data is sign-extended or zeroextended and stored as a 16-bit data item in AL. The data in AL can be handled either as word
or byte long.
When a byte-processing arithmetic operation instruction is executed on AL, the high-order eight
bits of AL before operation are ignored. The high-order eight bits of the operation result all
become zeroes.
The A register is not initialized by a reset. The A register holds an undefined value immediately
after a reset.
Figure 2.7-3 32-bit Data Transfer
MO VL A,@R W1+6
(Instruction that performs a long-word-length read using the result of
RW1 + an 8-bit offset as the address and stores the read value in the A register)
MSB
Old A
XXXX H
XXXX H
DTB
New A
8F74 H
AH
2B52 H
A6 H
Memory space
A61540 H
8F H
74 H
A6153E H
2B H
52 H
15 H
38 H
LSB
+6
RW1
AL
31
CHAPTER 2 CPU
Figure 2.7-4 AL-AH Transfer
MO VW A,@R W1+6
(Instruction that performs a word-length read using the result of RW1 + an
8-bit offset as the address and stores the read value in the A register)
MSB
Old A
XXXX H
1234 H
DTB
New A
32
1234 H
1234 H
A6 H
LSB
Memory space
A61540 H
8F H
74 H
A6153E H
2B H
52 H
15 H
38 H
+6
RW1
2.7 Registers
2.7.2
User Stack Pointer (USP) and System Stack Pointer (SSP)
USP and SSP are 16-bit registers that indicate the memory addresses for saving and
restoring data when a push/pop instruction or subroutine is executed.
■ User Stack Pointer (USP) and System Stack Pointer (SSP)
USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring
data in the event of a push/pop instruction or subroutine execution. The USP and SSP registers
are used by stack instructions. The USP register is enabled when the S flag in the processor
status register is '0,' and the SSP register is enabled when the S flag is '1' (see Figure 2.7-5
"Stack Manipulation Instruction and Stack Pointer"). Since the S flag is set when an interrupt is
accepted, register values are always saved in the memory area indicated by SSP during
interrupt processing. SSP is used for stack processing in an interrupt routine, while USP is used
for stack processing outside an interrupt routine. If the stack space is not divided, use only the
SSP.
During stack processing, the high-order eight bits of an address are indicated by SSB (for SSP)
or USB (for USP). USP and SSP are not initialized by a reset. Instead, they hold undefined
values.
Figure 2.7-5 Stack Manipulation Instruction and Stack Pointer
Example 1 PUSHW A when the S flag is '0'
Before execution
AL
S flag
After execution
AL
MSB
C6F326 H
LSB
A624 H
USB
C6 H
USP
F328 H
0
SSB
56 H
SSP
1234 H
A624 H
USB
C6 H
USP
F326 H
0
SSB
56 H
SSP
1234 H
C6F326 H
A6 H
24 H
A624 H
USB
C6 H
USP
F328 H
561232 H
XX
XX
1
SSB
56 H
SSP
1234 H
A624 H
USB
C6 H
USP
F328 H
561232 H
A6 H
24 H
1
SSB
56 H
SSP
1232 H
XX
XX
User stack is used because
the S flag is '0.'
Example 2 PUSHW A when the S flag is '1'
Before execution
AL
After execution
AL
System stack is used because
the S flag is '1.'
Note:
Specify an even-numbered address in the stack pointer whenever possible.
33
CHAPTER 2 CPU
2.7.3
Processor Status (PS)
The PS register consists of the bits controlling the CPU Operation and the bits
indicating the CPU status.
■ Processor Status (PS)
As shown in Figure 2.7-6 "Processor Status (PS) Structure", the high-order byte of the PS
register consists of a register bank pointer (RP) and an interrupt level mask register (ILM). The
RP indicates the start address of a register bank. The low-order byte of the PS register is a
condition code register (CCR), containing the flags to be set or reset depending on the results of
instruction execution or interruptoccurrences.
Figure 2.7-6 Processor Status (PS) Structure
15
13 12
0
8 7
PS
ILM
RP
Initial value
000
00000
CCR
-01XXXXX
X:Undefined
■ Condition Code Register (CCR)
Figure 2.7-7 "Condition Code Register (CCR) Configuration" is a diagram of condition code
register configuration.
Figure 2.7-7 Condition Code Register (CCR) Configuration
Initial value
7
6
5
4
3
2
1
0
-
I
S
T
N
Z
V
C
: CCR
-
0
1
X
X
X
X
X
X: Undefined
❍ I: Interrupt enable flag:
Interrupts other than software interrupts are enabled when the I flag is 1 and are masked when
the I flag is 0. The I flag is cleared by a reset.
❍ S: Stack flag:
When the S flag is 0, USP is enabled as the stack manipulation pointer.
When the S flag is 1, SSP is enabled as the stack manipulation pointer.
The S flag is set by an interrupt reception or a reset.
❍ T: Sticky bit flag:
1 is set in the T flag when there is at least one '1' in the data shifted out from the carry after
execution of a logical right/arithmetic right shift instruction. Otherwise, 0 is set in the T flag. In
addition, '0' is set in the T flag when the shift amount is zero.
❍ N: Negative flag:
The N flag is set when the MSB of the operation result is '1,' and is otherwise cleared.
34
2.7 Registers
❍ Z: Zero flag:
The Z flag is set when the operation result is all zeroes, and is otherwise cleared.
❍ V: Overflow flag:
The V flag is set when an overflow of a signed value occurs as a result of operation execution
and is otherwise cleared.
❍ C: Carry flag:
The C flag is set when a carry-up or carry-down from the MSB occurs as a result of operation
execution, and is otherwise cleared.
■ Register Bank Pointer (RP)
The RP register indicates the relationship between the general-purpose registers of the F2MC16LX and the internal RAM addresses. Specifically, the RP register indicates the first memory
address of the currently used register bank in the following conversion expression: [00180H +
(RP) x 10H] (see Figure 2.7-8 "Register Bank Pointer (RP)"). The RP register consists of five
bits, and can take a value between 00H and 1FH. Register banks can be allocated at addresses
from 000180H to 00037H in memory.
Even within that range, however, the register banks cannot be used as general-purpose
registers if the banks are not in internal RAM. The RP register is initialized to all zeroes by a
reset. An instruction may transfer an eight-bit immediate value to the RP register; however, only
the low-order five bits of that data are used.
Figure 2.7-8 Register Bank Pointer (RP)
Initial value
B4
B3
B2
B1
0
0
0
0
B0
: RP
0
■ Interrupt Level Mask Register (ILM)
The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt
request is accepted only when the level of the interrupt is higher than that indicated by these
three bits. Level 0 is the highest priority interrupt, and level 7 is the lowest priority interrupt (see
Table 2.7-1 "Levels Indicated by the Interrupt Level Mask (ILM) Register"). Therefore, for an
interrupt to be accepted, its level value must be smaller than the current ILM value. When an
interrupt is accepted, the level value of that interrupt is set in ILM. Thus, an interrupt of the same
or lower level cannot be accepted subsequently. ILM is initialized to all zeroes by a reset. An
instruction may transfer an eight-bit immediate value to the ILM register, but only the low-order
three bits of that data are used.
Figure 2.7-9 Interrupt Level Register (ILM)
ILM2
Initial value
0
ILM1
0
ILM0
: ILM
0
35
CHAPTER 2 CPU
Table 2.7-1 Levels Indicated by the Interrupt Level Mask (ILM) Register
36
ILM2
ILM1
ILM0
Level value
Acceptable interrupt level
0
0
0
0
Interrupt disabled
0
0
1
1
0 only
0
1
0
2
Level value smaller than 1
0
1
1
3
Level value smaller than 2
1
0
0
4
Level value smaller than 3
1
0
1
5
Level value smaller than 4
1
1
0
6
Level value smaller than 5
1
1
1
7
Level value smaller than 6
2.7 Registers
2.7.4
Program Counter (PC)
The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory
address of an instruction code to be executed by the CPU. The high-order eight bits of
the address are indicated by the PCB. The PC register is updated by a conditional
branch instruction, subroutine call instruction, interrupt, or reset.
The PC register can also be used as a base pointer for operand access.
■ Program Counter (PC)
Figure 2.7-10 "Program Counter" shows the program counter.
Figure 2.7-10 Program Counter
PCB
FE H
PC
ABCD H
Next instruction to be executed
FEABCD H
37
CHAPTER 2 CPU
2.8
Register Bank
A register bank consists of eight words. The register bank can be used as the
following general-purpose registers for arithmetic operations: byte registers R0 to R7,
word registers RW0 to RW7, and long word registers RL0 to RL3. In addition, the
register bank can be used as instruction pointers.
■ Register Bank
Table 2.8-1 "Register Functions" lists the functions of the registers. Table 2.8-2 "Relationship
between Registers" indicates the relationship between the registers.
In the same manner as for an ordinary RAM area, the register bank values are not initialized by
a reset. The status before a reset is maintained. When the power is turned on, however, the
register bank will have an undefined value.
Table 2.8-1 Register Functions
R0 to R7
RW0 to RW7
RL0 to RL3
Used as operands of instructions.
Note: R0 is also used as a counter for barrel shift or normalization
instructions.
Used as pointers.
Used as operands of instructions.
Note: RW0 is used as a counter for string instructions.
Used as long pointers.
Used as operands of instructions.
Table 2.8-2 Relationship between Registers
RW0
RL0
RW1
RW2
RL1
RW3
R0
RW4
R1
RL2
R2
RW5
R3
R4
RW6
R5
RL3
R6
RW7
R7
38
2.8 Register Bank
❍ Direct page register (DPR) <Initial value: 01H>
DPR specifies addr8 to addr15 of the instruction operands in direct addressing mode as shown
in Figure 2.8-1 "Generating a Physical address in Direct Addressing Mode". DPR is eight bits
long, and is initialized to 01H by a reset. DPR can be read or written to by an instruction.
Figure 2.8-1 Generating a Physical address in Direct Addressing Mode
DTB register
DPR register
Direct address during instruction
αααααααα
ββββββββ
γγγγγγγγ
MSB
24-bit physical
address
LSB
ααααααααββββββββγγγγγγγγ
❍ Program counter bank register (PCB) <Initial value: Value in reset vector>
❍ Data bank register(DTB) <Initial value: 00H>
❍ User stack bank register(USB) <Initial value: 00H>
❍ System stack bank register(SSB) <Initial value: 00H>
❍ Additional data bank register(ADB) <Initial value: 00H>
Each bank register indicates the memory bank where the PC, DT, SP (user), SP (system), or
AD space is allocated. All bank registers are one byte long. PCB is initialized to 00H by a reset.
Bank registers other than PCB can be read or written to. PCB can be read but cannot be written
to.
PCB is updated when the JMPP, CALLP, RETP, RETI, or RETF instruction branching to the
entire 16-Mbyte space is executed or when an interrupt occurs. For operation of each register,
see Section 2.2 "Memory space".
39
CHAPTER 2 CPU
2.9
Prefix Codes
Placing a prefix code before an instruction partially changes the operation of the
instruction. Three types of prefix codes can be used: bank select prefix, common
register bank prefix, and flag change disable prefix.
■ Bank Select Prefix
The memory space used for accessing data is determined for each addressing mode.
When a bank select prefix is placed before an instruction, the memory space used for accessing
data by that instruction can be selected regardless of the addressing mode.
Table 2.9-1 "Bank Select Prefix" lists the bank select prefixes and the corresponding memory
spaces.
Table 2.9-1 Bank Select Prefix
Bank select prefix
Space selected
PCB
PC space
DTB
Data space
ADB
AD space
SPB
Either the SSP or USP space is used according to the stack flag
value.
Use the following instructions with care:
❍ String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW)
The bank register specified by an operand is used regardless of the prefix.
❍ Stack manipulation instructions (PUSHW, POPW)
SSB or USB is used according to the S flag regardless of the prefix.
❍ I/O access instructions
MOV A, io / MOV io, A /MOVX A, io / MOVW A, io /MOVW io, A / MOV io, #imm8
MOV io, #imm16 / MOVB A, io:bp / MOB io:bp, A /SETB io:bp / CLRB io:bp
BBC io:bp, rel / BBS io:bp, rel WBTC, WBTS
The IO space of the bank is used regardless of the prefix.
❍ Flag change instructions (AND CCR,#imm8, OR CCR,#imm8)
The instruction is executed normally, but the prefix affects the next instruction.
❍ POPW PS
SSB or USB is used according to the S flag regardless of the prefix. The prefix affects the next
instruction.
40
2.9 Prefix Codes
❍ MOV ILM,#imm8
The instruction is executed normally, but the prefix affects the next instruction.
❍ RETI
SSB is used regardless of the prefix.
■ Common Register Bank Prefix (CMR)
To simplify data exchange between multiple tasks, the same register bank must be accessed
relatively easily regardless of the RP value. When CMR is placed before an instruction that
accesses a register bank, that instruction accesses the common bank (the register bank
selected when RP=0) at addresses from 000180H to 00018FH regardless of the current RP
value. When using the common register bank prefix (CMR), use the following instructions
carefully:
❍ String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW)
If an interrupt request occurs during execution of a string instruction with a prefix code, the
prefix code becomes invalid when the string instruction is resumed after the interrupt is
processed. Thus, the string instruction is executed falsely after the interrupt is processed. Do
not prefix any of the above string instructions with CMR.
❍ Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS)
The instruction is executed normally, but the prefix affects the next instruction.
❍ MOV ILM,#imm8
The instruction is executed normally, but the prefix affects the next instruction.
■ Flag Change Disable Prefix (NCC)
To disable flag changes, use the flag change disable prefix code (NCC). Placing NCC before an
instruction disables flag changes associated with that instruction. When using the flag change
disable prefix (NCC), use the following instructions carefully:
❍ String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW)
If an interrupt request occurs during execution of a string instruction with a prefix code, the
prefix code becomes invalid when the string instruction is resumed after the interrupt is
processed. Thus, the string instruction is executed incorrectly after the interrupt is processed.
Do not prefix any of the above string instructions with NCC.
❍ Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS)
The instruction is executed normally, but the prefix affects the next instruction.
❍ Interrupt instructions (INT #vct8, INT9, INT addr16, INTP addr24, RETI)
CCR changes according to the instruction specifications regardless of the prefix.
❍ JCTX @A
CCR changes according to the instruction specifications regardless of the prefix.
❍ MOV ILM,#imm8
The instruction is executed normally, but the prefix affects the next instruction.
41
CHAPTER 2 CPU
2.10 Interrupt Disable Instructions
Interrupt requests are not sampled for the following ten instructions:
- MOV ILM,#imm8
- PCB
- SPB
- OR
CCR,#imm8
- AND CCR,#imm8
- ADB
- CMR
- POPW PS
- NCC
- DTB
■ Interrupt Disable Instructions
If a valid interrupt request occurs during execution of any of the above instructions, the interrupt
can be processed only when an instruction other than the above is executed. For details, see
Figure 2.10-1 "Interrupt Disable Instruction".
Figure 2.10-1 Interrupt Disable Instruction
Interrupt disable instruction
••••••••
(a)
•••
(a) Ordinary
instruction
Interrupt request
Interrupt acceptance
■ Restrictions on Interrupt Disable Instructions and Prefix Instructions
When a prefix code is placed before an interrupt disable instruction, the prefix code affects the
first instruction after the code other than the interrupt disable instruction.
Figure 2.10-2 Interrupt Disable Instructions and Prefix Codes
Interrupt disable instruction
MOV A, FF H
NCC
••••
MOV ILM,#imm8
ADD A,01
CCR:XXX10XX
H
CCR:XXX10XX
CCR does not change with NCC.
■ Consecutive Prefix Codes
When competitive prefix codes are placed consecutively, the latter becomes valid.
In the figure below, competitive prefix codes are PCB, ADB, DTB, and SPB.
Figure 2.10-3 Consecutive Prefix Codes
Prefix code
•••••
ADB
DTB
PCB
A D D A , 0 1H
••••
PCB is valid as the prefix code
42
2.11 Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions
2.11 Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions
Set the value of the corresponding bank register to "00H" when using "DIV A, Ri" and
"DIVW A, RWi" instructions.
■ Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions
Table 2.11-1 Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions
Instruction
DIV A, R0
Name of the bank
register affected
when executing the
instructions shown
in the table
DTB
Address at which the remainder is stored
(DTB: Higher 8-bit) + (0180H + RP x 10H + 8H : Lower 16-bit)
DIV A, R1
(DTB: Higher 8-bit) + (0180H + RP x 10H + 9H : Lower 16-bit)
DIV A, R4
(DTB: Higher 8-bit) + (0180H + RP x 10H + CH : Lower 16-bit)
DIV A, R5
(DTB: Higher 8-bit) + (0180H + RP x 10H + DH : Lower 16-bit)
DIVW A, RW0
(DTB: Higher 8-bit) + (0180H + RP x 10H + 0H : Lower 16-bit)
DIVW A, RW1
(DTB: Higher 8-bit) + (0180H + RP x 10H + 2H : Lower 16-bit)
DIVW A, RW4
(DTB: Higher 8-bit) + (0180H + RP x 10H + 8H : Lower 16-bit)
DIVW A, RW5
(DTB: Higher 8-bit) + (0180H + RP x 10H + AH : Lower 16-bit)
DIV A, R2
ADB
(ADB: Higher 8-bit) + (0180H + RP x 10H + AH : Lower 16-bit)
DIV A, R6
(ADB: Higher 8-bit) + (0180H + RP x 10H + EH : Lower 16-bit)
DIVW A, RW2
(ADB: Higher 8-bit) + (0180H + RP x 10H + 4H : Lower 16-bit)
DIVW A, RW6
(ADB: Higher 8-bit) + (0180H + RP x 10H +EH : Lower 16-bit)
DIV A, R3
DIV A, R7
USB
SSB *1
(USB *2: Higher 8-bit) + (0180H + RP x 10H + BH : Lower 16-bit)
(USB *2: Higher 8-bit) + (0180H + RP x 10H + FH : Lower 16-bit)
DIVW A, RW3
(USB *2: Higher 8-bit) + (0180H + RP x 10H + 6H : Lower 16-bit)
DIVW A, RW7
(USB *2: Higher 8-bit) + (0180H + RP x 10H + EH : Lower 16-bit)
*1: Depending on the S bit of the CCR register
*2: When the S bit of the CCR register is "0"
If the value of corresponding bank registers (DTB, ADB, USB, SSB) is set to "00H", the
remainder of division results are stored in the register of the instruction operand. If the value is
set to a value other than "00H", the higher 8-bit address is specified by the bank register
corresponding to the register of the instruction operand. The lower 16-bit address then
becomes the same address as that of the register of the instruction operand at which the
remainder is stored.
43
CHAPTER 2 CPU
[Example]
If "DIV A, R0" instruction is executed in the case of DTB=053H/RP=003H, the address of R0
is as follows: 0180H+RP (003H) x 10H+08H (address equivalent to R0) = 0001B8H
The bank register to be specified by "DIV A, R0" is DTB, so the address to which bankspecified 053H is added, that is 05301B8H, is the address at which the remainder of a result
is stored.
For an explanation of the bank register, Ri register, and RWi register, see Section 2.7
"Registers".
■ Evasion of notes
In order to evade notes of the "DIV A, Ri" and "DIVW A, RWi" instructions during program
development, the compiler modifies the program so that the respective instructions are not
generated. The assembler then replaces these instructions by functions equivalent to the
instruction strings.
Use the following compiler and assembler.
•
Compiler: Version V02L06 of cc907 or later, and version V30L02 of fcc907s or later
•
Assembler:
Version V03L04 of asm907a or later, and version V30L04 (Rev.30004) of
fasm907s or later
44
CHAPTER 3
INTERRUPTS
This chapter explains the interrupt functions and operations.
3.1 "Outline of Interrupts"
3.2 "Interrupt Sources"
3.3 "Interrupt Vector"
3.4 "Hardware Interrupts"
3.5 "Software Interrupts"
3.6 "Extended Intelligent I/O Service (EI2OS)"
3.7 "Exception Due to Execution of an Undefined Instruction
45
CHAPTER 3 INTERRUPTS
3.1
Outline of Interrupts
The F2MC-16LX has interrupt functions that, when an event occurs, terminate the
processing being currently executed and transfer control to a separately defined
program.
■ Outline of Interrupts
There are four types of interrupt functions:
•
Hardware interrupt: Interrupt processing due to an internal resource event
•
Software interrupt: Interrupt processing due to an instruction causing a software event
•
Extended intelligent I/O service (EI2OS): Transfer processing due to an internal resource
event
•
Exception: Termination due to an operation exception
This section explains these four types
46
3.2 Interrupt Sources
3.2
Interrupt Sources
Table 3.2-1 "Interrupt Sources, Interrupt Vectors, and Interrupt Control Registers" lists
the interrupt sources, interrupt vectors, and interrupt control registers in the MB90435
series.
■ Interrupt Sources
Table 3.2-1 Interrupt Sources, Interrupt Vectors, and Interrupt Control Registers
Interrupt source
EI2OS clear
Interrupt vector
Interrupt control register
Number
Address
Number
Address
Reset
X
#08
FFFFDCH
-
-
INT9 instruction
X
#09
FFFFD8H
-
-
Exception
X
#10
FFFFD4H
-
-
Reserved
X
#11
FFFFD0H
ICR00
0000B0H
Reserved
X
#12
FFFFCCH
Reserved
X
#13
FFFFC8H
ICR01
0000B1H
Reserved
X
#14
FFFFC4H
External interrupt INT0/INT1
O
#15
FFFFC0H
ICR02
0000B2H
Timebase timer
X
#16
FFFFBCH
16-bit reload timer 0
O
#17
FFFFB8H
ICR03
0000B3H
A/D converter
O
#18
FFFFB4H
Input/output timer
X
#19
FFFFB0H
ICR04
0000B4H
External interrupt INT2/INT3
O
#20
FFFFACH
Serial I/O
O
#21
FFFFA8H
ICR05
0000B5H
PPG 0/1
X
#22
FFFFA4H
Input capture 0
O
#23
FFFFA0H
ICR06
0000B6H
External interrupt INT4/INT5
O
#24
FFFF9CH
Input capture 1
O
#25
FFFF98H
ICR07
0000B7H
PPG 2/3
X
#26
FFFF94H
External interrupt INT6/INT7
O
#27
FFFF90H
ICR08
0000B8H
Monitoring timer
X
#28
FFFF8CH
PPG 4/5
X
#29
FFFF88H
ICR09
0000B9H
Input capture 2/3
O
#30
FFFF84H
47
CHAPTER 3 INTERRUPTS
Table 3.2-1 Interrupt Sources, Interrupt Vectors, and Interrupt Control Registers (Continued)
Interrupt source
EI2OS clear
Interrupt vector
Number
Address
Number
Address
ICR10
0000BAH
ICR11
0000BBH
ICR12
0000BCH
ICR13
0000BDH
ICR14
0000BEH
ICR15
0000BFH
PPG 6/7
X
#31
FFFF80H
Output compare 0
O
#32
FFFF7CH
Output compare 1
O
#33
FFFF78H
Input capture 4/5
O
#34
FFFF74H
Output compare 2/3-input
capture 6/7
O
#35
FFFF70H
16-bit reload timer 1
O
#36
FFFF6CH
#37
FFFF68H
#38
FFFF64H
#39
FFFF60H
UART 0 receive
UART 0 transmit
O
UART 1 receive
Interrupt control register
UART 1 transmit
O
#40
FFFF5CH
Flash memory
X
#41
FFFF58H
Delayed interrupt
X
#42
FFFF54HH
: An EI2OS interrupt clear signal clears the interrupt request flag. A stop request is issued.
O : An EI2OS interrupt clear signal clears the interrupt request flag.
X : An EI2OS interrupt clear signal does not clear the interrupt request flag.
Note:
In a peripheral module in which two interrupt sources are assigned to the same interrupt
number, an EI2OS interrupt clear signal clears both interrupt request flags.
At EI2OS termination, an EI2OS clear signal is issued to all interrupt flags assigned to the
same interrupt number. If an interrupt flag starts EI2OS and another interrupt flag is set by a
hardware event, the flag is cleared by the EI2OS clear signal issued by the first event and
the latter event is lost. Do not use EI2OS for this interrupt number.
When EI2OS is enabled, one of two interrupt signals in the same interrupt control register
(ICR) is issued to start EI2OS. Although an individual EI2OS descriptor should be provided
for each interrupt source, the two interrupt sources actually share the same EI2OS
descriptor. While one interrupt source is using EI2OS, therefore, the other interrupt source
must be disabled.
48
3.3 Interrupt Vector
3.3
Interrupt Vector
Table 3.3-1 "Interrupt Vector" lists MB90435 series interrupt vectors.
■ Interrupt Vector
Table 3.3-1 Interrupt Vector
Software
interrupt
instruction
Vector
address L
Vector
address M
Vector
address H
Mode
register
Interrupt
No.
INT 0
FFFFFCH
FFFFFDH
FFFFFEH
Not used
#0
:
:
:
:
:
:
INT 7
FFFFE0H
FFFFE1H
FFFFE2H
Not used
#7
None
INT 8
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDFH
#8
(RESET vector)
INT 9
FFFFD8H
FFFFD9H
FFFFDAH
Not used
#9
ROM correction
INT 10
FFFFD4H
FFFFD5H
FFFFD6H
Not used
#10
<Exception>
INT 11
FFFFD0H
FFFFD1H
FFFFD2H
Not used
#11
None
INT 12
FFFFCCH
FFFFCDH
FFFFCEH
Not used
#12
None
INT 13
FFFFC8H
FFFFC9H
FFFFCAH
Not used
#13
None
INT 14
FFFFC4H
FFFFC5H
FFFFC6H
Not used
#14
None
INT 15
FFFFC0H
FFFFC1H
FFFFC2H
Not used
#15
External interrupt INT0/
INT1
INT 16
FFFFBCH
FFFFBDH
FFFFBEH
Not used
#16
Timebase timer
INT 17
FFFFB8H
FFFFB9H
FFFFBAH
Not used
#17
16-bit reload timer 0
INT 18
FFFFB4H
FFFFB5H
FFFFB6H
Not used
#18
A/D converter
INT 19
FFFFB0H
FFFFB1H
FFFFB2H
Not used
#19
I/O timer
INT 20
FFFFACH
FFFFADH
FFFFAEH
Not used
#20
External interrupt INT2/
INT3
INT 21
FFFFA8H
FFFFA9H
FFFFAAH
Not used
#21
Serial I/O
INT 22
FFFFA4H
FFFFA5H
FFFFA6H
Not used
#22
PPG 0/1
INT 23
FFFFA0H
FFFFA1H
FFFFA2H
Not used
#23
Input capture 0
INT 24
FFFF9CH
FFFF9DH
FFFF9EH
Not used
#24
External interrupt INT4/
INT5
INT 25
FFFF98H
FFFF99H
FFFF9AH
Not used
#25
Input capture 1
INT 26
FFFF94H
FFFF95H
FFFF96H
Not used
#26
PPG 2/3
Hardware interrupt
None
:
49
CHAPTER 3 INTERRUPTS
Table 3.3-1 Interrupt Vector (Continued)
Software
interrupt
instruction
Vector
address L
Vector
address M
Vector
address H
Mode
register
Interrupt
No.
INT 27
FFFF90H
FFFF91H
FFFF92H
Not used
#27
External interrupt INT6/
INT7
INT 28
FFFF8CH
FFFF8DH
FFFF8EH
Not used
#28
Monitoring timer
INT 29
FFFF88H
FFFF89H
FFFF8AH
Not used
#29
PPG 4/5
INT 30
FFFF84H
FFFF85H
FFFF86H
Not used
#30
Input capture 2/3
INT 31
FFFF80H
FFFF81H
FFFF82H
Not used
#31
PPG 6/7
INT 32
FFFF7CH
FFFF7DH
FFFF7EH
Not used
#32
Output compare 0
INT 33
FFFF78H
FFFF79H
FFFF7AH
Not used
#33
Output compare 1
INT 34
FFFF74H
FFFF75H
FFFF76H
Not used
#34
Input capture 4/5
INT 35
FFFF70H
FFFF71H
FFFF72H
Not used
#35
Output compare 2/3
Input capture 6/7
INT 36
FFFF6CH
FFFF6DH
FFFF6EH
Not used
#35
16-bit reload timer 1
INT 37
FFFF68HH
FFFF69H
FFFF6AH
Not used
#36
UART 0 receive
INT 38
FFFF64H
FFFF65H
FFFF66H
Not used
#37
UART 0 transmit
INT 39
FFFF60H
FFFF61H
FFFF62H
Not used
#38
UART 1 receive
INT 40
FFFF5CH
FFFF5DH
FFFF5EH
Not used
#39
UART 1 transmit
INT 41
FFFF58H
FFFF59H
FFFF5AH
Not used
#40
Flash memory
INT 42
FFFF54H
FFFF55H
FFFF56H
Not used
#41
Delayed interrupt
INT 43
FFFF50H
FFFF51H
FFFF52H
Not used
#42
None
:
:
:
:
:
:
INT 254
FFFC04H
FFFC05H
FFFC06H
Not used
#254
None
INT 255
FFFC00H
FFFC01H
FFFC02H
Not used
#255
None
50
Hardware interrupt
:
3.4 Hardware Interrupts
3.4
Hardware Interrupts
In response to an interrupt request signal from an internal resource, the CPU pauses
current program execution and transfers control to the interrupt processing program
defined by the user. This function is called the hardware interrupt function.
■ Hardware Interrupts
A hardware interrupt occurs when the relevant conditions are satisfied as a result of two
operations: comparison between the interrupt request level and the value in the interrupt level
mask register (ILM) of PS in the CPU, and hardware reference to the I flag value of PS.
The CPU performs the following processing when a hardware interrupt occurs:
•
Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to
the system stack.
•
Sets ILM in the PS register. The currently requested interrupt level is automatically set.
•
Fetches the corresponding interrupt vector value and branches to the processing indicated
by that value.
■ Structure of Hardware Interrupt
Hardware interrupts are handled by the following three sections:
❍ Internal resources
Interrupt enable and request bits: Used to control interrupt requests from resources.
❍ Interrupt controller
ICR: Assigns interrupt levels and determines the priority levels of simultaneously requested
interrupts.
❍ CPU
I and ILM: Used to compare the requested and current interrupt levels and to identify the
interrupt enable status.
Microcode: Interrupt processing step
The status of these sections are indicated by the resource control registers for internal
resources, the ICR for the interrupt controller, and the CCR value for the CPU. To use a
hardware interrupt, set the three sections beforehand by using software.
The interrupt vector table referenced during interrupt processing is assigned to addresses
FFFC00H to FFFFFFH in memory. These addresses are shared with software interrupts.
■ Hardware Interrupt Request during Writing to the Input-Output Area
When data is being written to the input-output area, hardware interrupt requests are not
accepted. This prevents the CPU from making operational mistakes, which could be caused if
an interrupt request were generated while data was being rewritten to the interrupt control
registers for each source.
51
CHAPTER 3 INTERRUPTS
■ Multiple Interrupts
The F2MC-16LX CPU supports multiple interrupts. If an interrupt of a higher level occurs while
another interrupt is being processed, control is transferred to the higher-level interrupt after the
current instruction completes execution. After the higher-level interrupt terminates, the CPU
returns to processing of the previous interrupt. If an interrupt of the same or lower level occurs
while another interrupt is being processed, the new interrupt request is kept pending until
termination of the current interrupt processing unless the ILM value or I flag is changed by an
instruction. The extended intelligent I/O service cannot be used for the activation of multiple
interrupts. During processing of the extended intelligent I/O service, all other interrupt requests
or extended intelligent I/O service requests are kept pending.
■ Register Saving onto the Stack
Figure 3.4-1 "Registers Saved on the Stack" shows the order of the registers saved in the stack.
Figure 3.4-1 Registers Saved on the Stack
Word (16 bits)
MSB
LSB
H
SSP
(SSP value before interrupt)
AH
AL
DPR
ADB
DTB
PCB
PC
PS
L
52
SSP
(SSP value after interrupt)
3.4 Hardware Interrupts
3.4.1
Hardware Interrupt Operation
An internal resource that has the hardware interrupt request function has an interrupt
request flag and interrupt enable flag. The interrupt request flag indicates whether an
interrupt request exists, and the interrupt enable flag indicates whether the relevant
internal resource requests an interrupt to the CPU. The interrupt request flag is set
when an event occurs that is unique to the internal resource. When the interrupt
enable flag indicates "enable", the resource issues an interrupt request to the interrupt
controller.
■ Hardware Interrupt Operation
When two or more interrupt requests are received at the same time, the interrupt controller
compares the interrupt levels (IL) in ICR, selects the request at the highest level (the smallest IL
value), then reports that request to the CPU. If multiple requests are at the same level, the
interrupt controller selects the request with the lowest interrupt number. The relationship
between the interrupt requests and ICRs is determined by the hardware.
The CPU compares the received interrupt level and the ILM in the PS register. If the interrupt
level is smaller than the ILM value and the I bit of the PS register is set to 1, the CPU activates
the interrupt processing microcode after the currently executing instruction is completed. The
CPU references the ISE bit of the ICR of the interrupt controller at the beginning of the interrupt
processing microcode, checks that the ISE bit is 0 (interrupt), and activates the interrupt
processing body.
The interrupt processing body saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the
memory area indicated by SSB and SSP, fetches three bytes of interrupt vector and loads them
onto PC and PCB, updates the ILM of PS to a level value of the received interrupt, sets the S
flag, then performs branch processing. As a result, the interrupt processing program defined by
the user is executed next.
Figure 3.4-2 "Occurrence and Release of Hardware Interrupt" illustrates the flow from the
occurrence of a hardware interrupt until there is no interrupt request in the interrupt processing
program.
53
CHAPTER 3 INTERRUPTS
Figure 3.4-2 Occurrence and Release of Hardware Interrupt
PS
Microcode
IR
I
ILM
Check
Comparator
PS
I
ILM
IR
: Processor status
: Interrupt enable flag in CCR
: Interrupt level in PS
: Instruction register
Peripheral
··
··
·
Enable FF
Cause FF
AND
Interrupt level IL
F 2 M C - 1 6 LX · C P U
Level comparator
Internal data bus
Register file
Interrupt
controller
Peripheral
Operations (1) to (7) in Figure 3.4-2 "Occurrence and Release of Hardware Interrupt" are
explained below.
1. An interrupt cause occurs in a peripheral.
2. The interrupt enable bit in the peripheral is referenced. If interrupts are enabled, the
peripheral issues an interrupt request to the interrupt controller.
3. Upon reception of the interrupt request, the interrupt controller determines the priority levels
of simultaneously requested interrupts. Then, the interrupt controller transfers the interrupt
level of the corresponding interrupt to the CPU.
4. The CPU compares the interrupt level requested by the interrupt controller with the ILM bit of
the processor status register.
5. If the comparison shows that the requested level is higher than the current interrupt
processing level, the I flag value of the same processor status register is checked.
6. If the check in step 5. shows that the I flag indicates interrupt enable status, the requested
level is written to the ILM bit. Interrupt processing is performed as soon as the currently
executing instruction is completed, then control is transferred to the interrupt processing
routine.
7. When the interrupt cause of step 1. is cleared by software in the user interrupt processing
routine, the interrupt request is completed.
The time required for the CPU to execute the interrupt processing in steps 6. and 7. is shown
below.
Interrupt start: 24 + 6 x (Table 3.4-1 "Compensation Values for Interrupt Processing Cycle
Count "machine cycles)
Interrupt return: 15 + 6 x (Table 3.4-1 "Compensation Values for Interrupt Processing Cycle
Count " machine cycles) RETI instruction
54
3.4 Hardware Interrupts
Table 3.4-1 Compensation Values for Interrupt Processing Cycle Count
Address indicated by the stack pointer
Cycle count compensation value
External area, 8-bit data bus
+4
External area, even-numbered address
+1
External area, odd-numbered address
+4
Internal area, even-numbered address
0
Internal area, odd-numbered address
+2
55
CHAPTER 3 INTERRUPTS
3.4.2
Flow of Hardware Interrupt Operation
Figure 3.4-3 "Flow of Hardware Interrupt Operation" shows the flow of hardware
interrupt operation.
■ Flow of Hardware Interrupt Operation
Figure 3.4-3 Flow of Hardware Interrupt Operation
I
ILM
IF
IE
ISE
IL
S
I&IF&IE=1
AND
ILM IL
:
:
:
:
:
:
:
Interrupt enable flag in CCR
Interrupt level mask register in PS
Interrupt request for internal resource
Interrupt enable flag for internal resource
EI2OS enable flag
Interrupt request level for internal resource
Flag in CCR
YES
NO
NO
Fetch the next instruction
and decode
Save PS, PC, PCB, DTB,
ADB, DPR, and A to the
SSP stack, then set ILM = IL
INT instruction?
Execute an ordinary instruction
Repetition of
string type instruction
completed?
YES
Update PC
56
Extended intelligent I/O
service processing
YES
NO
NO
YES
ISE = 1
Save PS, PC, PCB, DTB, ADB,
DPR, and A to the SSP stack,
then set I = 0 and ILM = IL
1
S
(fetch interrupt vector)
3.5 Software Interrupts
3.5
Software Interrupts
The software interrupt function returns control from the program being executed by
the CPU to the user-defined interrupt processing program in response to execution of
a special instruction.
■ Software Interrupts
A software interrupt is always activated when the software interrupt instruction is executed.
The CPU performs the following processing when a software interrupt occurs:
•
Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to
the system stack.
•
Sets I in the PS register. Interrupts are automatically disabled.
•
Fetches the corresponding interrupt vector value, then branches to the processing indicated
by that value.
A software interrupt request issued by the INT instruction has no interrupt request or enable
flag. A software interrupt request is always issued by executing the INT instruction.
The INT instruction does not have an interrupt level. Therefore, the INT instruction does not
update ILM. The INT instruction clears the I flag to suspend subsequent interrupt requests.
■ Structure of Software Interrupts
Software interrupts are handled within the CPU:
CPU.....Microcode: Interrupt processing step
As shown in Table 3.3-1 "Interrupt Vector", software interrupts share the same interrupt vector
area with hardware interrupts. For example, interrupt request number INT 15 is used for
external interrupt #0 (hardware interrupt) as well as for INT #15 (software interrupt). Therefore,
external interrupts #0 and INT #15 call the same interrupt processing routine.
■ Software Interrupt Operation
When the CPU fetches and executes the software interrupt instruction, the software interrupt
processing microcode is activated. The software interrupt processing microcode saves 12 bytes
(PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP. The
microcode then fetches three bytes of interrupt vector and loads them onto PC and PCB, resets
the I flag, and sets the S flag. Then, the microcode performs branch processing. As a result, the
interrupt processing program defined by the user application program is executed next.
Figure 3.5-1 "Occurrence and Release of Software Interrupt" illustrates the flow from the
occurrence of a software interrupt until there is no interrupt request in the interrupt processing
program.
57
CHAPTER 3 INTERRUPTS
Figure 3.5-1 Occurrence and Release of Software Interrupt
➀
PS
Internal data bus
Register file
➁
Microcode
F 2 M C - 1 6 LX • C P U
I
S
B unit
IR
Queue
Fetch
PS
I
ILM
IR
B unit
: Processor status
: Interrupt enable flag in CCR
: IInterrupt level in PS
: Instruction register
: Bus interface unit
Save
Instruction bus
RAM
Figure 3.5-1 "Occurrence and Release of Software Interrupt" illustrates the flow from the
occurrence of a software interrupt until there is no interrupt request in the interrupt processing
program.
1. The software interrupt instruction is executed.
2. Special CPU registers in the register file are saved according to the microcode
corresponding to the software interrupt instruction.
3. The interrupt processing is completed with the RETI instruction in the user interrupt
processing routine.
■ Note on Software Interrupt
When the program bank register (PCB) is FFH, the CALLV instruction vector area overlaps the
table of the INT #vct8 instruction. When designing software, ensure that the CALLV instruction
does not use the same address as that of the #vct8 instruction.
58
3.6 Extended Intelligent I/O Service (EI2OS)
3.6
Extended Intelligent I/O Service (EI2OS)
The EI2OS function automatically transfers data between input and output and
memory. An interrupt processing program was conventionally used for such
processing, but EI2OS enables data transfer to be performed like DMA (direct memory
access).
Note:
The use of EI2OS is not possible with the REALOS real time operating system.
■ Extended Intelligent I/O Service (EI2OS)
The extended intelligent I/O service (EI2OS) has the following advantages over the conventional
interrupt processing method:
•
The program size can be small because it is not necessary to write a transfer program.
•
No internal register is used for transfer, eliminating the need for register saving and
increasing the transfer speed.
•
Transfer can be terminated from I/O, preventing unnecessary data from being transferred.
•
Incrementing, decrementing, or no update can be selected for the buffer address.
•
Incrementing, decrementing, or no update can be selected for the I/O register address (if the
buffer address is updated).
At the end of EI2OS, processing automatically branches to an interrupt processing routine after
the end condition is set. Thus, the user can identify the end condition.
Figure 3.6-1 "Outline of Extended Intelligent I/O Service" provides an overview of EI2OS.
59
CHAPTER 3 INTERRUPTS
Figure 3.6-1 Outline of Extended Intelligent I/O Service
Memory space
by IOA
I/O register
I/O register
Peripheral
CPU
Interrupt request
ISD
by ICS
Interrupt control register
Interrupt controller
by BAP
Buffer
by
DCT
I/O requests transfer.
The interrupt controller selects the
descriptor.
The transfer source and destination
are read from the descriptor.
Data is transferred between I/O and
memory.
The interrupt source is automatically cleared.
Note:
The area that can be specified by IOA is between 000000H and 00FFFFH.
The area that can be specified by BAP is between 000000H and FFFFFFH.
The maximum transfer count that can be specified by DTC is 65,536.
■ Structure
EI2OS is handled by the following four sections:
Internal resources
Interrupt enable and request bits: Used to control interrupt requests from resources.
Interrupt controller
ICR: Assigns interrupt levels, determines the priority levels of simultaneously requested
interrupts, and selects the EI2OS operation.
CPU
I and ILM: Used to compare the requested and current interrupt levels and to identify the
interrupt enable status
Microcode: EI2OS processing step
RAM
Descriptor: Describes the EI2OS transfer information.
60
3.6 Extended Intelligent I/O Service (EI2OS)
3.6.1
Interrupt Control Register (ICR)
The interrupt control register, located in the interrupt controller, handles the interrupts
corresponding to all I/Os that have an interrupt function. The interrupt control register
has the following three functions:
• Setting an interrupt level for each related peripheral
• Selecting whether to use an ordinary interrupt or extended intelligent I/O service for
a related peripheral
• Selecting the extended intelligent I/O service channel
Do not access an interrupt control register with a read-modify-write instruction, since
an erroneous operation will result.
■ Interrupt Control Register (ICR)
Figure 3.6-2 "Interrupt Control Register (ICR)" shows the bit configuration of the interrupt control
register.
Figure 3.6-2 Interrupt Control Register (ICR)
Interrupt control register (ICR)
15/7
Address B0H to BFH
Read/write
Initial value
14/6
13/5
12/4
11/3
10/2
9/1
8/0
ICS3 ICS2 ICS1 ICS0 ISE
IL2
IL1
IL0
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(1)
(W)
(1)
(W)
(1)
15/7
14/6
13/5
12/4
11/3
10/2
9/1
8/0
S1
S0
ISE
IL2
IL1
IL0
(R)
(0)
(R)
(1)
(R)
(1)
(R)
(1)
Address B0H to BFH
Read/write
(-)
(-)
Initial value
(-)
(-)
(R)
(0)
(R)
(0)
Bit No.
During writing
Bit No.
During reading
Note:
ICS3 to ICS0 are valid only when EI2OS is activated. Set ISE to 1 to activate EI2OS and to 0
not to activate it. When EI2OS is not to be activated, any value can be set in ICS3 to ICS0.
For ICS3 and ICS2, 1 is always read.
ICS1 and ICS0 can only be written to. S1 and S0 can only be read.
[Bits 15 to 12 and 7 to 4]: ICS3 to ICS0
The ICS3 to ICS0 bits specify the EI2OS channel.
They are write-only bits. The values set for these bits determine the extended intelligent I/O
service descriptor addresses in memory. The ICS bits are initialized by a reset.
Table 3.6-1 "ICS Bits, Channel Numbers, and Descriptor Addresses" lists
correspondence between ICS bits, channel numbers, and descriptor addresses.
the
61
CHAPTER 3 INTERRUPTS
Table 3.6-1 ICS Bits, Channel Numbers, and Descriptor Addresses
ICS3
ICS2
ICS1
ICS0
Selected channel
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
[Bits 13 and 12 and bits 5 and 4]: S0 and S1
The S0 and S1 bits indicate the EI2OS termination status.
They are read-only bits. When the values in these bits are checked at EI2OS termination, a
termination condition can be identified. These bits are initialized to 00 by a reset.
Table 3.6-2 "S Bits and Termination Conditions" shows the relationship between the S bits
and termination conditions.
Table 3.6-2 S Bits and Termination Conditions
62
S1
S0
Termination condition
0
0
EI2OS running or not activated
0
1
Stopped status due to count termination
1
0
Reserved
1
1
Stopped status due to a request from the internal resource
3.6 Extended Intelligent I/O Service (EI2OS)
[Bits 11 and 3]: ISE
The ISE bit enables EI2OS. This bit can be read and written to.
If this bit is 1 when an interrupt request is generated, EI2OS is activated. If this bit is 0 when
an interrupt request is generated, the interrupt sequence is activated. When the EI2OS
termination condition is met (when the S1 and S0 bits are not 00), the ISE bit is cleared to 0.
If the corresponding peripheral function does not have the EI2OS function, the ISE bit must
be set to 0 by software. The ISE bit is initialized to 0 by a reset.
[Bits 10 to 8 and bits 2 to 0]: IL0, IL1, and IL2
The IL0, IL1, and IL2 bits set the interrupt level.
These bits specify the interrupt level of the corresponding internal resources. These bits can
be read and written to. These bits are initialized to level 7 (no interrupt) by a reset. Table
3.6-3 "Interrupt Level Setting Bits and Interrupt Levels" shows the relationship between the
interrupt level setting bits and interrupt levels.
Table 3.6-3 Interrupt Level Setting Bits and Interrupt Levels
ILM2
ILM1
ILM0
Interrupt level
0
0
0
0 (highest interrupt)
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6 (lowest interrupt)
1
1
1
7 (no interrupt)
63
CHAPTER 3 INTERRUPTS
3.6.2
Extended Intelligent I/O Service Descriptor (ISD)
The extended intelligent I/O service descriptor exists between 000100H and 00017FH in
internal RAM, and consists of the following items:
• Data transfer control data
• Status data
• Buffer address pointer
■ Extended Intelligent I/O Service Descriptor (ISD)
Figure 3.6-3 "Extended Intelligent I/O Service Descriptor Configuration" shows the configuration
of the extended intelligent I/O service descriptor.
Figure 3.6-3 Extended Intelligent I/O Service Descriptor Configuration
H
High-order 8 bits of data counter (DCTH)
Low-order 8 bits of data counter (DCTL)
High-order 8 bits of I/O address pointer (IOAH)
Low-order 8 bits of I/O address pointer (IOAL)
EI 2OS status (ISCS)
High-order 8 bits of buffer address pointer (BAPH)
000100 H + 8 × ICS
Medium-order 8 bits of buffer address pointer (BAPM)
ISD start address
Low-order 8 bits of buffer address pointer (BAPL)
L
■ Data Counter (DCT)
This is a 16-bit register that works as a counter corresponding to the number of data items
transferred. This counter is decremented by one before data transfer. EI2OS is terminated when
this counter reaches 0. Figure 3.6-4 "Data Counter Configuration" is a diagram of the data
counter configuration.
Figure 3.6-4 Data Counter Configuration
Data counter (upper)
15
B15
Initial value
Data counter (lower)
Initial value
(X)
7
14
B14
(X)
6
13
B13
(X)
5
12
B12
(X)
4
11
B11
(X)
3
10
B10
(X)
2
9
8
Bit No.
B09
B08
DCTH
(X)
1
(X)
0
B07
B06
B05
B04
B03
B02
B01
B00
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Bit No.
DCTL
■ I/O Register Address Pointer (IOA)
This is a 16-bit register that indicates the low-order address (A15 to A0) of the buffer and I/O
register used for data transfer. The high-order address (A23 to A16) are all zeroes, and any I/O
between addresses 000000H and 00FFFFH can be specified. Figure 3.6-5 "I/O Register
Address Pointer Configuration" is a diagram of the IOA configuration.
64
3.6 Extended Intelligent I/O Service (EI2OS)
Figure 3.6-5 I/O Register Address Pointer Configuration
15
14
13
12
11
10
9
8
Bit No.
A15
A14
A13
A12
A11
A10
A09
A08
IOAH
Initial value
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
I/O address pointer (lower)
7
6
5
4
3
2
1
0
A07
A06
A05
A04
A03
A02
A01
A00
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
I/O address pointer (upper)
Initial value
Bit No.
IOAL
EI2OS status register (ISCS)
The EI2OS status register (ISCS) is eight bits, and indicates the update direction (increment/
decrement), transfer data format (byte/word), and transfer direction of the buffer address
pointer and I/O register address pointer. This register also indicates whether the buffer
address pointer or I/O register address pointer is updated or fixed. Figure 3.6-6 "ISCS
Configuration" shows the ISCS configuration.
Figure 3.6-6 ISCS Configuration
7
6
5
Reserved Reserved Reserved
Initial value
(X)
(X)
(X)
4
3
2
1
0
IF
BW
BF
DIR
SE
(X)
(X)
(X)
(X)
Bit No.
ISCS
(Undefined when reset)
(X)
* Always write 0 to bits 7 to 5 of ISCS.
[Bit 4]: IF
The IF bit specifies whether the I/O register address pointer is updated or fixed.
Table 3.6-4 I/O Register Address Pointer Update/Fixed Selection Bit (IF)
IF
Function
0
After data transfer, the I/O register address pointer is updated.
1
After data transfer, the I/O register address pointer is not updated.
[Bit 3]: BW
The BW bit specifies the transfer data length.
Table 3.6-5
BW
Function
0
Byte
1
Word
[Bit 2]: BF
The BF bit specifies whether the buffer address pointer is updated or fixed.
65
CHAPTER 3 INTERRUPTS
Table 3.6-6 Buffer Address Pointer Update/Fixed Selection Bit (BF)
BF
Function
0
After data transfer, the buffer address pointer is updated.
1
After data transfer, the buffer address pointer is not updated.
Note:
Only the lower 16 bits of the buffer address pointer are updated. Only incrementing is
allowed.
[Bit 1]: DIR
The DIR bit specifies the data transfer direction.
Table 3.6-7 Data Transfer Direction Specification Bit (DIR)
DIR
Setting
0
I/O -> buffer
1
Buffer -> I/O
[Bit 0]: SE
The SE bit controls the termination of the extended intelligent I/O service based on resource
requests.
Table 3.6-8 EI2OS Termination Control Bit
SE
Setting
0
Not terminated by a resource request.
1
Terminated by a resource request.
■ Buffer Address Pointer (BAP)
This 24-bit register holds the address used for the next EI2OS transfer. BAP exists for each
EI2OS channel. Therefore, each EI2OS channel can be used for transfer with anywhere in the
16-Mbyte space.
Note:
If the BF bit of ISCS is set to "0" (update enabled), only the low-order 16 bits of BAP changes
and BAPH does not change.
66
3.6 Extended Intelligent I/O Service (EI2OS)
3.6.3
Operation of Extended Intelligent I/O Service (EI2OS)
Figure 3.6-7 "Operation Flow of the Extended Intelligent I/O Service (EI2OS)" shows the
operation flow of the extended intelligent I/O service (EI2OS). Figure 3.6-8 "Procedure
for Using the Extended Intelligent I/O Service (EI2OS)" shows the procedure for using
the extended intelligent I/O service (EI2OS).
■ Operation Flow of the Extended Intelligent I/O Service (EI2OS)
Figure 3.6-7 Operation Flow of the Extended Intelligent I/O Service (EI2OS)
Interrupt request
generated
by internal resource
ISE
1
NO
YES
Read ISD/ISCS
Termination
request from
resource?
Interrupt sequence
YES
SE
NO
DIR
1
NO
BF
0
NO
0
Data indicated by BAP
(Data transfer)
Memory indicated by BAP
YES
DCT
00
NO
Set S1 and S0 to 00
Update value
by BW
Update IOA
Update value
by BW
Update BAP
YES
NO
Decrement DCT
-1
YES
EI2 OS termination processing
Set S1 and S0 to 01
Clear interrupt request
from internal resource
Return to CPU operation
2
YES
YES
Data indicated by IOA
(Data transfer)
Memory indicated by BAP
IF
1
NO
ISD : IEI OS descriptor
ISCS : EI2OS status register
IF
: IOA update/fixed selection bit in the
EI2OS status register (ISCS)
BW : Transfer data length specification
bit in the EI2OS status register (ISCS)
BF
: BAP update/fixed selection bit in the
EI2OS status register (ISCS)
DIR : Data transfer direction specification
bit in the EI2OS status register (ISCS)
SE
: EI2OS termination control bit in the
EI2OS status register (ISCS)
Set S1 and S0 to 11
Clear ISE to 0
Interrupt sequence
DCT
IOA
BAP
ISE
S1,S0
: Data counter
: I/O register address pointer
: Buffer address pointer
: EI2OS enable bit in the interrupt control register (ICR)
: EI2OS status in the interrupt control register (ICR)
67
CHAPTER 3 INTERRUPTS
Figure 3.6-8 Procedure for Using the Extended Intelligent I/O Service (EI2OS)
Software processing
Hardware processing
Start
Initialization
Set the system stack area
Set the EI2OS descriptor
Initialize the internal resource
Set the interrupt
control register (ICR)
Set the internal resource
to start operation. Set the
interrupt enable bit (ICR)
Set the ILM and I in the PS
S1, S0
Execute the user program
(Interrupt request)and
ISE
"00"
1
Transfer data
Decide whether to end counting or to NO
branch to an interrupt by termination
request from resource
(Branch to interrupt vector)
Set the extended
intelligent I/O service
again (switch channels)
Process data in the buffer
RETI
ISE: EI2OS enable bit in the interrupt control register (ICR)
S1, S0: EI2OS status of the interrupt control register (ICR)
68
S1, S0
S1, S0
YES
"01"or
"11"
3.6 Extended Intelligent I/O Service (EI2OS)
3.6.4
Execution Time of the Extended Intelligent I/O Service
(EI2OS)
The time required for executing the extended intelligent I/O service (EI2OS) changes in
the following cases:
• When data transfer continues (when the stop condition is not satisfied)
• When a stop request is issued from a resource
• When the counting is completed
■ Execution Time of the Extended Intelligent I/O Service (EI2OS)
❍ When data transfer continues (when the stop condition is not satisfied)
(Table 3.6-9 "Execution Time When the Extended EI2OS Continues" + Table 3.6-10 "Data
Transfer Compensation Values for Extended EI2OS Execution Time") machine cycles
Table 3.6-9 Execution Time When the Extended EI2OS Continues
ISCS SE bit
Set to 0
I/O address pointer
Buffer address pointer
Set to 1
Fixed
Updated
Fixed
Updated
Fixed
32
34
33
35
Updated
34
36
35
37
❍ When a stop request is issued from a resource
(36 + 6 x Table 3.4-1 "Compensation Values for Interrupt Processing Cycle Count") machine
cycles
❍ When the counting is completed
(Table 3.6-9 "Execution Time When the Extended EI2OS Continues" + Table 3.6-10 "Data
Transfer Compensation Values for Extended EI2OS Execution Time" + (21 + 6 x Table 3.4-1
"Compensation Values for Interrupt Processing Cycle Count")) machine cycles
69
CHAPTER 3 INTERRUPTS
Table 3.6-10 Data Transfer Compensation Values for Extended EI2OS Execution Time
I/O address pointer
Buffer
address
pointer
B:
8:
E:
O:
70
Internal access
External access
B/E
O
B/E
8/O
Internal
access
B/E
0
+2
+1
+4
O
+2
+4
+3
+6
External
access
B/E
+1
+3
+2
+5
8/O
+4
+6
+5
+8
Byte data transfer
8-bit external bus word transfer
Even address word transfer
Odd address word transfer
3.7 Exception Due to Execution of an Undefined Instruction
3.7
Exception Due to Execution of an Undefined Instruction
In the F2MC-16LX, an exception occurs when an undefined instruction is executed and
exception processing is performed.
Exception processing is fundamentally the same as interrupt processing. When an
exception is detected between instructions, exception processing is performed
separately from ordinary processing. In general, exception processing is performed as
the result of an unexpected operation. It is recommended that exception processing
be used only for debugging or for activating emergency recovery software.
■ Exception Due to Execution of an Undefined Instruction
The F2MC-16LX handles all codes that are not defined in the instruction map as undefined
instructions. When an undefined instruction is executed, processing equivalent to the INT 10
software interrupt instruction is performed.
Specifically, the AL, AH, DPR, DTB, ADB, PCB, PC, and PS values are saved onto the system
stack, and processing branches to the routine indicated by the interrupt number 10 vector. In
addition, the I flag is cleared and the S flag is set. The PC value saved on the stack is the
address at which the undefined instruction is stored. Although processing can be restored with
the RETI instruction, this is pointless because the same exception occurs again.
71
CHAPTER 3 INTERRUPTS
72
CHAPTER 4
CLOCK AND RESET
This chapter explains the functions and operations of clocks and resets.
4.1 "Clock Generator"
4.2 "Reset Cause Occurrence"
4.3 "Reset Causes"
73
CHAPTER 4 CLOCK AND RESET
4.1
Clock Generator
The clock generator controls internal clock operation, including such functions as
sleep, timer, stop, and PLL multiplication. This internal clock is called the machine
clock, and one cycle of the machine clock is called a machine cycle. A clock based on
the source oscillation is called the main clock, and a clock based on the internal VCO
oscillation is called the PLL clock.
■ Notes on Clock Generator
When the operating voltage is 5 V, the OSC source oscillation can be between 3 MHz and 5
MHz. When an external clock source is used, its frequency can be between 3 MHz and 16MHz.
The highest operating frequency for the CPU and peripheral resource circuits is 16 MHz,
however. Normal operation is not guaranteed if a multiplication factor resulting in a higher
frequency than 16 MHz is specified. For example, if the external clock frequency is 16 MHz,
only 1 can be specified as the multiplication factor.
The lowest operating frequency of the VCO oscillation is 4 MHz, and an oscillation below 4 MHz
must not be specified.
Figure 4.1-1 Clock Generator Circuit Block Diagram
S Q
Reset
Interrupt
HST
Transition to
stop mode
S Q
R
Machine clock
Transition to
timer or
R
sleep mode
S Q
Selecting the machine clock
1
R
Selecting the oscillation
stabilization wait time
2
3
4
PLL multiplication
Time base timer
1/2
X0
1/2048
1/4
1/4
1/8
XL
Selecting the watch-dog
timer interval
Watch-dog
timer
Watch-dog reset
74
4.2 Reset Cause Occurrence
4.2
Reset Cause Occurrence
When a reset cause occurs, F2MC-16LX terminates the currently executing processing
and waits for reset release.
■ Reset Cause Occurrence
A reset is caused by the following factors:
•
Power-on reset
•
Hardware standby release
•
Watch-dog timer overflow
•
External reset request via RST pin
•
Reset request by software
Upon exit from the stop mode or after a power-on reset, the oscillation stabilization interval is
inserted before operation is restarted.
If a reset cause is generated, the F2MC-16LX immediately stops the current operation being
executed and enters reset release standby mode.
The machine clock and watch-dog function are initialized based on the reset causes.
The content of the watch-dog timer control register will change according to the reset cause.
Thus, the cause of the previous reset can be known.
Note:
In a mode other than stop mode, external reset input is internally sampled by the clock
circuit. When external clock signal supply is used, reset signal input is not received.
If an external bus is being used, the address generated by the device is undefined when a
reset cause occurs. The signals to be used for external bus access, including RD and WR,
become inactive.
75
CHAPTER 4 CLOCK AND RESET
■ Operation after Reset Release
When a reset cause is removed, the F2MC-16LX immediately outputs the address in which the
reset vector is stored, then fetches the reset vector and mode data. The reset vector and mode
data are assigned to the four bytes between FFFFDCH and FFFFDFH. After reset is released,
the reset vector and mode data are transferred to the registers by the hardware as described in
Figure 4.2-1 "Source and Destination of Reset Vector and Mode Data".
Use the mode pin to specify whether to read the reset vector and mode data from internal ROM
or from external memory. When the mode pin is set to external vector mode, the F2MC-16LX
reads the reset vector and mode data from external memory. When using the F2MC-16LX in
single chip mode or internal ROM external bus mode, Fujitsu recommends specifying internal
vector mode.
The bus mode after the reset vector and mode data are read is specified by the mode data.
Figure 4.2-1 Source and Destination of Reset Vector and Mode Data
F2MC-16LX CPU
Mode
Memory space
Register
FFFFDFH
Mode data
FFFFDEH
Reset vector bits 23 to 16
FFFFDD H
Reset vector bits 15 to 8
FFFFDCH
Reset vector bits 7 to 0
Micro ROM
Reset sequence
PCB
PC
Note:
The mode register in the above diagram is not defined immediately after a reset. Store
mode data in the memory space so that the value is written to this area.
76
4.2 Reset Cause Occurrence
■ Registers not Initialized by Reset Input
This microcontroller contains registers initialized only by a power-on reset.
Table 4.2-1 "Registers not Initialized by Reset Input" lists registers not initialized by each reset
cause.
Table 4.2-1 Registers not Initialized by Reset Input
CKSCR
WTC
LPMCR
Type of reset
WS1
WS0
MCS
CS1
CS0
WDCS
CG1
CG0
Software reset
(Only RST is used.)
X
X
X
X
X
X
X
X
Watchdog reset
X
X
O
X
X
X
O
O
Power-on reset
O
O
O
O
O
O
O
O
Main
mode
X
X
O
X
X
X
O
O
Sub
mode
O
O
O
O
O
O
O
O
Hardware standby
WS1 and WS0: Set the oscillation stabilization time for the main clock.
MCS: Specifies the machine clock (0 = PLL clock or 1 = main clock).
CS1 and CS0: Set the multiplication factor for the PLL clock.
WDCS: Specifies the input clock source for the watchdog timer (0 = watch timer or 1 = timebase timer).
O: Initialized
X: Not initialized
In particular, handle the MCS bit carefully because it sets the machine clock. For example, if
power-on does not satisfy the power-on reset specification, no power-on reset occurs. For this
reason, the internal operating frequency may become outside the valid operation range,
because MCS is not initialized, and the microcontroller may not operate normally.
If the CPU crashes for some reason and MCS, CS1, or CS0 is rewritten, the internal operating
frequency may also become outside the valid operation range. The microcontroller may not be
able to recover normally from this status by RST input only (however, if the internal watchdog
state occurs, MCS is initialized and the microcontroller operates normally).
When either of the above cases occurs, use of HST plus RST (connecting HST and RST with a
jumper) is recommended.
Table 4.2-2 "Registers not Initialized by Reset Input" lists registers that are not initialized by
reset input using HST plus RST. Note that the operation status after the reset is released differs
depending on the reset input type, HST plus RST reset input, or only RST input, as listed in
Table 4.2-2 "Registers not Initialized by Reset Input".
77
CHAPTER 4 CLOCK AND RESET
Table 4.2-2 Registers not Initialized by Reset Input
CKSCR
WTC
LPMCR
Type of reset
WS1
WS0
WDCS
CS1
CS0
WDCS
CG1
CG0
Main
mode
X
X
X
X
X
X
O
O
Sub
mode (*1)
O
O
O
O
O
O
O
O
HST + RST
Y: Initialized
N: Not initialized
*1: Including the sub mode transition period.
78
4.2 Reset Cause Occurrence
Figure 4.2-2 Operation Transition by Reset Input
[Operation Transition by Reset Input]
Reset input
(RST, HST+RST)
A. Oscillation status
Oscillating
Status
Main
Oscillating
Sub
Oscillating
Only RST
used
(HST ="H")
Main
HST + RST
used
Oscillating
Stopped
Waiting for main
clock oscillation
stabilization
Main clock operation enabled
Waiting for subclock
oscillation stabilization
Sub
Subclock operation
enabled
B. Execution timing (L: Stop, H: Start)
Only RST used (HST ="H")
HST plus RST used
Main clock mode
Oscillation stabilization
time set before reset input
2 main clock cycles when
subclock mode requested
Line disabling period set
by SCS bits
Subclock mode
216 cycles of subclock oscillation (32 kHz) (about 2 s)
Power-on reset
Vcc (power supply)
Oscillating
Power-on
reset
Main
Sub
Status
Oscillating
Stopped
Waiting for main
clock oscillation
stabilization
Main clock operation enabled
Waiting for subclock
oscillation stabilization
Subclock operation
enabled
Oscillation stabilization time
of 218main clock cycles
Main mode
Sub mode
2 main clock cycles when
subclock mode requested
Write disabling period set
by SCS bits
216 cycles of subclock oscillation (32 kHz) (about 2 s)
79
CHAPTER 4 CLOCK AND RESET
4.3
Reset Causes
Table 4.3-1 "Reset Causes" lists the five reset causes. The machine clock and watchdog function are initialized differently for each reset cause.
The reset cause register indicates the reset cause.
■ Reset Causes
Table 4.3-1 Reset Causes
Machine clock
Reset
At sub-clock
At PLL clock
Watch-dog
timer
Cause
Oscillation
stabilization
wait
Power-on
When the power is
turned on
Main clock *
Main clock *
Stop
Yes
Hardware
standby
"L" level input to HST pin
Main clock *
Main clock *
Stop
Yes
Watch-dog
timer
Watch-dog timer
overflow
Main clock *
Main clock *
Stop
Yes
External pin
"L" level input to RST pin
PLL clock
Previous status
maintained
No
Software
0 written to the RST bit in
the LPMCR register
PLL clock
Previous status
maintained
No
Main clock * or
PLL clock
Main clock * or
PLL clock
*: fOSC/2 (fOSC: the source oscillation)
Notes:
In stop mode, input of the external pin reset signal allows an oscillation stabilization wait time to be set.
The oscillation stabilization time for a power-on reset and hardware standby is fixed to 218 cycles of source oscillation.
For other types of reset, the oscillation stabilization wait time is determined by WS1 and WS0 of the clock selection
register.
Each reset cause has a corresponding flip-flop. The contents of the flip-flop can be obtained by
reading the watch-dog timer control register. If the reset cause must be identified after the reset
is released, be sure that the value read from the watch-dog timer control register is processed
by software and processing branches to an appropriate application program.
80
4.3 Reset Causes
Figure 4.3-1 Reset Cause bit Block Diagram
HST pin
RST pin
RST=L
HST=L
Without periodic clear
Power on
RST bit set
Power-on
detection circuit
S
R
F/F
Hardware standby
release detection
circuit
S
R
S
F/F
External reset
request detection
circuit
R
F/F
S
Watch-dog timer
reset detection circuit
R
F/F
S
R
F/F
LPMCR. RST bit
write detection circuit
WTC register
Delay
circuit
WTC register read
Internal data bus
When there are multiple reset causes, the corresponding reset cause bits in the watch-dog timer
control register are set. Therefore, if an external reset request and a watch-dog reset occur at
the same time, both the ERST and WRST bits are set to 1.
A power-on reset is an exception; while the PONR bit is 1, the values of other bits do not
indicate the correct reset causes. Therefore, design software so that the other reset cause bit
values are ignored while the PONR bit is set to 1.
Table 4.3-2 Reset Cause Bits
Reset cause
PONR
STBR
WRST
ERST
SRST
Power-on
1
-
-
-
-
Hardware standby
*
1
*
*
*
Watch-dog timer
*
*
1
*
*
External pin
*
*
*
1
*
RST bit
*
*
*
*
1
(An asterisk (*) in the table means that the previous value is maintained.)
The reset cause bits are only cleared by reading the watch-dog timer control register. The reset
cause bit that corresponds to the reset cause that has already been generated remains 1 even if
another reset cause is generated.
See Chapter 9 "TIMEBASE TIMER", Chapter 10 "WATCH-DOG TIMER" and Chapter 11
"WATCH TIMER" for details about the configuration and reset cause bits of the watch-dog timer
control register.
81
CHAPTER 4 CLOCK AND RESET
82
CHAPTER 5
LOW-POWER CONTROL CIRCUIT
This chapter explains the functions and operation of the low-power control circuit.
5.1 "Outline of Low-Power Control Circuit"
5.2 "Block Diagram of Low-Power Control Circuit"
5.3 "Low-Power Control Circuit Registers"
5.4 "Status Transition for Clock Selection"
83
CHAPTER 5 LOW-POWER CONTROL CIRCUIT
5.1
Outline of Low-Power Control Circuit
The low-power control circuit is mainly used in low-power consumption mode. The
intermittent CPU operation function and oscillation stabilization wait time can be set
by setting register bits.
In the overall block diagram, the low-power control circuit is a part of the clock control
circuit (see Section 1.3 "Block Diagram").
■ Operation Modes of Low-power Control Circuit
The MB90435 series supports the following operation modes: PLL clock mode, PLL sleep
mode, PLL watch mode, pseudo watch mode, main clock mode, main sleep mode, main watch
mode, main stop mode, subclock mode, subclock sleep mode, subclock watch mode, subclock
stop mode, and hardware standby mode. Operation modes other than PLL clock mode are
classified as low-power modes.
■ Intermittent CPU Operation Function
The intermittent CPU operation function pauses the clock supplied to the CPU for a certain
period to delay the activation of the internal bus cycle when an internal register, internal memory
(ROM, RAM, I/O, or resource memory), or external bus is accessed. The CPU execution speed
is decreased while a high-speed clock is supplied to internal resources, enabling processing
with less power consumed. The CG1 and CG0 bits of the low-power consumption mode control
register (LPMCP) are used to select the cycle count for pausing the clock to be supplied to the
CPU.
The external bus operation is performed by using the same clock signal as that used for
peripheral resources.
The instruction execution time using the intermittent CPU operation function can be obtained by
adding a compensation value to the ordinary execution time. The compensation value is
obtained by multiplying the number of accesses to a register, internal memory, or internal
resource by the cycle count for pausing.
■ Main Clock Oscillation Stabilization Wait Time
The WS1 and WS0 bits of the clock selection register (CKSCR) are used to select the main
clock oscillation stabilization wait time when stop mode is released. Select the oscillation
stabilization wait time according to the type and characteristics of the oscillation circuit and
oscillation device to be connected to X0 and X1 pins.
Reset signals other than power-on reset and hardware standby do not initialize these bits. After
power-on reset or hardware standby release is generated, these bits are initialized to 11. In that
case, the main clock oscillation stabilization wait time is about 218 counts of the source
oscillation.
84
5.1 Outline of Low-Power Control Circuit
■ Switching between Machine Clocks
❍ Switching between main clock and PLL clock
Data is written to the MCS bit of the clock selection register (CKSCR) to switch between the
main clock and PLL clock.
When the MCS bit is changed from 1 to 0, the PLL clock takes over from the main clock after
the PLL clock oscillation stabilization wait time (212 machine clock cycles).
When the MCS bit is changed from 0 to 1, the main clock takes over from the PLL clock the next
time the edges of the PLL clock and main clock signals match (after 1 to 8 PLL clock cycles).
Writing to the MCS bit does not immediately change the machine clock. To manipulate a
resource that depends on the machine clock, always reference the MCM bit beforehand to
check that the machine clock has been switched.
❍ Switching between main clock and subclock
In the two clocks system parts, data is written to the SCS bit of the clock selection register
(CKSCR) to switch between the main clock and subclock.
If the SCS bit is changed from 1 to 0, the operation is switched from the main clock to subclock
when the next edge of the subclock signal is detected.
If the SCS bit is changed from 0 to 1, the operation is switched from the subclock to the main
clock after the main clock oscillation stabilization wait time.
Writing to the SCS bit does not immediately change the machine clock.
Manipulate a resource after the machine clock operation is checked.
However, subclock can not be used in the one clock system parts.
Note:
When subclock mode is returned to main clock mode using an external reset pin (RST pin),
input level "L" for at least 2 machine cycles of the subclock.
❍ Initializing the machine clock
The MCS bit and SCS bit are not initialized by a reset using an external pin or RST bit. These
bits are initialized to 1 by any other reset.
Note:
When tune on the power or hardware standby mode or stop mode is released, the subclock
oscillation stabilization time (about 2 seconds) is generated. In the meantime, when
switching from the main clock mode to the subclock mode, the oscillation stabilization time is
generated.
In attempting to switch the clock mode, do not attempt to switch to another clock mode or
low-power consumption mode until the first switching is completed. The MCM and SCM bits
of the clock selection register (CKSCR) indicate that switching is completed.
■ PLL Clock Multiplication Function
The CS1 and CS0 bits are used to set the multiplication factor of the PLL clock to 2, 4, 6, and 8.
This clock is divided by two and used as a machine clock signal.
85
CHAPTER 5 LOW-POWER CONTROL CIRCUIT
5.2
Block Diagram of Low-Power Control Circuit
This section contains a block diagram of the low-power control circuit.
■ Block Diagram of Low-Power Control Circuit
Figure 5.2-1 Block Diagram of Low-Power Control Circuit and Clock Generator
CKSCR
SCM
SCS
Subclock
switch control
Dividing by 4
1/4
1/2
CKSCR
MCM
MCS
PLL multiplication
circuit
1
2
3 4
Dividing by 2
CPU
clock generation
CKSCR
CS1
CS0
LPMCR
CG1
Internal data bus
CG0
1/2 1/4
CPU
CPU clock selector
STP
TMD
Main clock
(OSC oscillation)
CPU clock
0/9/17/33
intermittent cycle selection
Intermittent
CPU operation function
Cycle count
selection circuit
Peripheral
clock generation
LPMCR
SLP
Subclock
(OSC oscillation)
SCM
Peripheral clock
SLEEP
Standby control
circuit
Main clock OSC stop
MSTP
Subclock OSC stop
HST STOP
RST Release activation
HST pin
Interrupt request or RST
CKSCR
WS1
WS0
Oscillation
stabilization
wait time
selector
1/2
210
Clock input
213
215
Timebase timer
217 *1
212 214 216 219
LPMCR
SPL
SSR
LPMCR
RST
Pin high-impedance control circuit
Pin HI-Z
Self-refresh control circuit
Self refresh
Internal reset
generation circuit
RST pin
Internal RST
To watch-dog timer
WDGRST
*1: 218 at power-on
86
5.3 Low-Power Control Circuit Registers
5.3
Low-Power Control Circuit Registers
A low-power control circuit has the following two registers:
• Low-power mode control register
• Clock selection register
■ Low-Power Mode Control Register
Figure 5.3-1 Low-Power Control Circuit Registers
Low-Power Mode Control Register
7
Read/write
Initial value
Address:0000A1H
Read/write
Initial value
5
STP SLP
Address: 0000A0H
Clock selection register
6
(W)
(0)
15
14
4
SPL
3
12
(W)
(1)
11
SCM MCM WS1 WS0 SCS
(R)
(1)
(R)
(1)
1
0
RST TMD CG1 CG0
(W) (R/W) (W)
(0)
(0)
(1)
13
2
SSR
Bit No.
LPMCR
(R/W) (R/W) (R/W)
(0)
(0)
(0)
10
9
MCS CS1
8
CS0
Bit No.
CKSCR
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(1)
(1)
(1)
(1)
(0)
(0)
87
CHAPTER 5 LOW-POWER CONTROL CIRCUIT
5.3.1
Low-Power Mode Control Register (LPMCR)
This section explains the configuration and bit functions of the low-power mode
control register (LPMCR).
■ Low-Power Mode Control Register (LPMCR)
Figure 5.3-2 Low-Power Mode control Register (LPMCR)
Low Power Module Control Register (LPMCR)
Address
0000A0H
Read/write
Initial value
7
6
5
4
STP
SLP
SPL
(W)
(0)
(W) (R/W) (W)
(0)
(0)
(1)
3
2
1
0
RST TMD CG1 CG0 Reserved
(W)
(1)
Bit No.
LPMCR
(R/W) (R/W) (-)
(0)
(0)
(0)
[bit 7] STP
Writing 1 to this bit starts pseudo watch mode (CKSCR. MCS=0 and SCS=1) or stop mode
(CKSCR. MCS=1 or SCS=0). Writing 0 performs no operation. This bit is cleared to 0 by a
reset, watch mode release, or stop mode release. This is a write-only bit. The value read
from this bit is always 0.
[bit 6] SLP
Writing 1 to this bit starts sleep mode. Writing 0 performs no operation. This bit is cleared to
0 by a reset, sleep mode release, or stop mode release.
Writing 1 to the STP and SLP bits simultaneously starts watch mode or pseudo watch mode.
This is a write-only bit. The value read from this bit is always 0.
[bit 5] SPL
When 0 is written to this bit, the external pin level in timer, pseudo timer, or stop mode is
maintained. When 1 is written to this bit, the external pin in timer, pseudo timer, or stop
mode is set to high impedance. This bit is cleared to 0 by a reset.
[bit 4] RST
Writing "0" to this bit generates internal reset signals for three machine cycles. Writing "1"
performs no operation. "1" is always read from this bit.
[Bit 3] TMD
Two clocks system:
Writing 0 to this bit starts watch mode. Writing 1 performs no operation. This bit is cleared
to 1 by a reset, watch mode release, or stop mode release. This is a write-only bit. The
value read from this bit is always 1.
One clock system:
Always write "1".
88
5.3 Low-Power Control Circuit Registers
[bits 2 and 1] CG1 and CG0
These bits are used to set the clock pause cycle count during intermittent CPU operation.
These bits are initialized to "00" upon a reset by power-on, hardware standby, or watch-dog.
These bits are not initialized by any other type of reset.
Table 5.3-1 lists the CG bit setting.
Table 5.3-1 CG bit setting.
CG1
CG0
CPU clock pause cycle count
0
0
0 cycle (CPU clock = Resource clock)
0
1
9 cycles (CPU clock: Resource clock = 1:3 to 4 approx.)
1
0
17 cycles (CPU clock: Resource clock = 1:5 to 6 approx.)
1
1
33 cycles (CPU clock: Resource clock = 1:9 to 10 approx.)
[Bit 0] Reserved
This is a reserved bit. Always write "0".
89
CHAPTER 5 LOW-POWER CONTROL CIRCUIT
■ Access to the Low-Power Mode Control Register
To use word length to write data to the low-power mode control register, be sure that even
addresses are used. Writing with odd addresses to switch to low-power consumption mode
may cause a malfunction.
Writing data to the low-power mode control register starts low-power consumption mode
(including stop mode and sleep mode). Use the instructions listed in Table 5.3-2 "Instructions to
Be Used for Switching to Low-Power Consumption Mode" for this purpose. Using other
instructions to start low-power consumption mode may cause a malfunction. Any instruction
can be used to control functions other than switching to low-power consumption mode from the
low-power mode control register.
To use word length to write data to the low-power mode control register, be sure that even
addresses are used. Writing with odd addresses to start low-power consumption mode may
cause a malfunction.
Table 5.3-2 Instructions to Be Used for Switching to Low-Power Consumption Mode
90
MOV io,#imm8
MOV dir,#imm8
MOV eam,#imm8
MOV eam,#immRi
MOV io,A
MOV dir,A
MOV addr16,A
MOV eam,A
MOV RLi+dip8,A
MOVP addr24,A
MOVW io,#imm16
MOVW dir,#imm16
MOVW eam,#imm16
MOVW eam,RWi
MOVW io,A
MOVW dir,A
MOVW addr16,A
MOVW eam,RWi
MOVW RLi+dip8,A
MOPW addr24,A
SETB io:bp
SETB dir:bp
SETB addr16:bp
5.3 Low-Power Control Circuit Registers
5.3.2
Clock Selection Register (CKSCR)
This section explains the configuration and bit functions of the clock selection register
(CKSCR).
■ Clock Selection Register (CKSCR)
Figure 5.3-3 Clock Selection Register (CKSCR)
Clock Selection Register
15
Address
0000A1H
Read/write
Initial value
14
13
12
11
SCM MCM WS1 WS0 SCS
(R)
(1)
(R)
(1)
10
9
MCS CS1
8
Bit No.
CS0
CKSCR
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(1)
(1)
(1)
(1)
(0)
(0)
[Bit 15] SCM
Two clocks system:
This bit indicates whether the main clock or subclock is selected as the machine clock.
When this bit is set to 0, the subclock is selected. When this bit is set to 1, the main clock is
selected. When SCS=1 and SCM=0, the system is waiting for main clock oscillation to
stabilize.
One clock system:
The read value is always "1".
[bit 14] MCM
This bit indicates whether the main clock or PLL clock is selected as the machine clock. "0"
indicates that the PLL clock is selected, and "1" indicates that the main clock is selected.
When MCS=0 and MCM=1, the system is waiting for the PLL clock oscillation to stabilize.
The PLL clock oscillation stabilization wait time is fixed to 213 main clock cycles.
91
CHAPTER 5 LOW-POWER CONTROL CIRCUIT
[bits 13 and 12] WS1 and WS0
The WS1 and WS0 bits are used to specify the oscillation stabilization wait time when stop
mode is released. Specify the oscillation stabilization time according to the type and
characteristics of the oscillation circuits and oscillation devices connected to the X0 and X1
pins.
These bits are not initialized by a reset except a power-on reset and hardware standby
release. Therefore, at power-on, the oscillation stabilization wait time is about 218 counts of
source oscillation. These bits can be read and written.
Table 5.3-3 "WS Bit Setting" lists the WS bit setting.
Table 5.3-3 WS Bit Setting
WS1
WS0
Oscillation stabilization wait time (at 4 MHz source oscillation)
0
0
Approx. 256μs (210 counts of source oscillation)
0
1
Approx. 2.05 ms (213 counts of source oscillation)
1
0
Approx. 8.19 ms (215 counts of source oscillation)
1
1
Approx. 32.77 ms (217 counts of source oscillation)
Approx. 65.54 ms (218 counts of source oscillation) at power-on reset
and hardware standby only
[Bit 11] SCS
Two clocks system:
This bit is used to select the main clock or subclock as the machine clock. Writing 0 selects
the subclock. Writing 1 selects the main clock. When this bit is updated from 0 to 1, the
oscillation stabilization wait time for oscillation clock is generated and the timebase timer is
cleared automatically. When the subclock is selected, the operation clock is generated by
dividing the subclock by fore (the operation clock is 8 kHz at a source oscillation of 32 kHz).
This bit is initialized to 1 by a power-on, hardware standby, watch-dog, external, or software
reset.
One clock system:
Always write "1".
[bit 10] MCS
This bit is used to select the main clock or PLL clock as the machine clock. Writing "0"
selects the PLL clock and writing "1" selects the main clock. When this bit is updated from
"1" to "0", the PLL clock oscillation stabilization wait period is created by automatically
clearing the timebase timer. The oscillation stabilization wait time for the PLL clock is fixed to
213 main clock cycles.
When the main clock is selected, the operation clock is generated by dividing the main clock
by two. (The operation clock is 2 MHz at 4 MHz source oscillation.)
When the MCS bit is updated from 0 to 1, the main clock takes over from the PLL clock
when the edges of the main clock and PLL clock match (after about 1 to 8 PLL clock cycles).
Writing to the MCS bit does not immediately change the machine clock. To use a resource
that depends on the machine clock, always reference the MCM bit beforehand to check
whether the machine clock has been changed.
92
5.3 Low-Power Control Circuit Registers
Note:
The MCS bit is initialized to 1 by a power-on, hardware standby, or watch-dog reset instead
of a reset using an external pin or RST bit.
[bits 9 and 8] CS1 and CS0
These bits determine the multiplication factor of the PLL clock. These bits are initialized to
00 by a reset due to power-on and hardware standby.
When the MCS bit is 0, write is disabled. Write 1 to the MCS bit (main clock mode), then
update the CS bits. These bits can be read and written to.
Table 5.3-4 "CS Bit Setting" lists the settings of the CS bits.
Table 5.3-4 CS Bit Setting
CS1
CS0
Machine clock (at 4 MHz source oscillation)
0
0
4 MHz (Operation frequency = OSC oscillation frequency)
0
1
8 MHz (Operation frequency = OSC oscillation frequency *2)
1
0
12 MHz (Operation frequency = OSC oscillation frequency *3)
1
1
16 MHz (Operation frequency = OSC oscillation frequency *4)
Note:
When the operating voltage is 5 V, the OSC source oscillation can be between 3 MHz and 5
MHz. When an external clock source is used, its frequency can be between 3 MHz and
16MHz. Since the highest operating frequency for the CPU and peripheral resource circuits
is 16 MHz, however, normal operation is not guaranteed if a multiplication factor resulting in
a higher frequency than 16 MHz is specified. For example, if the external clock frequency is
16 MHz, only 1 can be specified as the multiplication factor.
The lowest operating frequency of the VCO oscillation is 4 MHz, and an oscillation below 4
MHz must not be specified.
93
CHAPTER 5 LOW-POWER CONTROL CIRCUIT
5.4
Status Transition for Clock Selection
This section explains the status transitions for clock selection.
■ Status Transition for Clock Selection
Figure 5.4-1 Status transition diagram 1 for clock selection (Two clocks system parts No.1)
Power on
Main
SCS=1, MCS=1
SCM=1, MCM=1
CS1/0=xx
Subclock
PLLx
SCS=1, MCS=0
SCM=0, MCM=1
CS1/0=xx
subclock
Main
SCS=0, MCS=x
SCM=1
SCM=1
PLLx
Main
SCS=1, MCS=0
SCM=1, MCM=1
CS1/0=xx
main
PLL1
SCS=0 or MCS=1
SCM=1, MCM=0
CS1/0=00
PLL1 multiplication
SCS=1, MCS=0
SCM=1, MCM=0
CS1/0=00
PLL2
main
SCS=0 or MCS=1
SCM=1, MCM=0
CS1/0=01
PLL2 multiplication
SCS=1, MCS=0
SCM=1, MCM=0
CS1/0=01
PLL3
main
SCS=0 or MCS=1
SCM=1, MCM=0
CS1/0=10
PLL3 multiplication
SCS=1, MCS=0
SCM=1, MCM=0
CS1/0=10
PLL4
main
SCS=0 or MCS=1
SCM=1, MCM=0
CS1/0=11
PLL4 multiplication
SCS=1, MCS=0
SCM=1, MCM=0
CS1/0=11
MCS bit clear and SCS bit set
PLL clock oscillation stabilization wait termination and CS1/0=00
PLL clock oscillation stabilization wait termination and CS1/0=01
PLL clock oscillation stabilization wait termination and CS1/0=10
PLL clock oscillation stabilization wait termination and CS1/0=11
MCS bit set or SCS bit clear
Synchronization timing between PLL clock and main clock and SCS=1
Synchronization timing between PLL clock and main clock and SCS=0
Main clock oscillation stabilization wait termination and MCS=0
94
5.4 Status Transition for Clock Selection
Figure 5.4-2 Status Transition Diagram 2 for Clock Selection (Two clocks system parts No.2)
Power on
Main
SCS=1, MCS=1
SCM=1
MCM=1
subclock
PLLx
SCS=0, MCS=x
SCM=1, MCM=0
CS1/0=xx
subclock
Main
SCS=0
SCM=1
MCM=1
subclock
SCS=1
SCM=0
MCM=1
Main
subclock
SCS=0
SCM=0
MCM=1
Main
PLLx
SCS=1, MCS=0
SCM=1, MCM=1
CS1/0=xx
SCS bit clear
Subclock edge detection timing
SCS bit set
Main clock oscillation stabilization wait termination and MCS=1
Synchronization timing between PLL clock and main clock and SCS=0
Main clock oscillation stabilization wait termination and MCS=0
95
CHAPTER 5 LOW-POWER CONTROL CIRCUIT
Figure 5.4-3 Clock Selection Status Transition 3 (one-way item)
Power-on
Main clock
SCS = 1, MCS = 1
SCM = 1, MCM = 1
CS1/0 = xxB
Main clock
PLLx
SCS = 1, MCS = 0
SCM = 1, MCM = 1
CS1/0 = xxB
PLL multiplication
Main clock
factor: 1
SCS = 1, MCS = 1
SCM = 1, MCM = 0
CS1/0 = 00'B
PLL multiplication factor: 1
SCS = 1, MCS = 0
SCM = 1, MCM = 0
CS1/0 = 00'B
PLL multiplication
Main clock
factor: 2
SCS = 1, MCS = 1
SCM = 1, MCM = 0
CS1/0 = 01'B
PLL multiplication factor: 2
SCS = 1, MCS = 0
SCM = 1, MCM = 0
CS1/0 = 01'B
PLL multiplication
Main clock
factor: 3
SCS = 1, MCS = 1
SCM = 1, MCM = 0
CS1/0 = 10'B
PLL multiplication factor: 3
SCS = 1, MCS = 0
SCM = 1, MCM = 0
CS1/0 = 10'B
PLL multiplication
Main clock
factor: 4
SCS = 1, MCS = 1
SCM = 1, MCM = 0
CS1/0 = 11'B
PLL multiplication factor: 4
SCS = 1, MCS = 0
SCM = 1, MCM = 0
CS1/0 = 11'B
The MCS bit is cleared and the SCS bit is set.
The PLL clock oscillation stabilization time has passed and CS1 and CS0 are 00B.
The PLL clock oscillation stabilization time has passed and CS1 and CS0 are 01B.
The PLL clock oscillation stabilization time has passed and CS1 and CS0 are 10B.
The PLL clock oscillation stabilization time has passed and CS1 and CS0 are 10B.
The MCS bit is set.
The PLL clock is synchronized with the main clock and the SCS bit is 1.
Note:
In attempting to switch the clock mode, do not attempt to switch to another clock mode or
low-power consumption mode until the first switching is completed. The MCM bit of the clock
selection register (CKSCR) indicates that switching is completed.
96
CHAPTER 6
LOW-POWER CONSUMPTION MODES
This chapter explains the functions and operation of the low-power consumption
modes.
6.1 "Outline of Low-Power Control Circuit"
6.2 "Status Transitions in Low-Power Consumption Mode"
6.3 "Status Transition Diagram for Low-Power Consumption Mode"
97
CHAPTER 6 LOW-POWER CONSUMPTION MODES
6.1
Low-Power Consumption Modes
The MB90435 series supports the following operation modes:
• PLL clock mode
• PLL sleep mode
• PLL watch mode
• Pseudo watch mode
• Main clock mode
• Main sleep mode
• Main watch mode
• Main stop mode
• Subclock mode
• Subclock sleep mode
• Subclock watch mode
• Subclock stop mode
• Hardware standby mode
Modes other than PLL clock mode are classified as low-power consumption modes.
■ Low-Power Consumption Modes
❍ Main clock mode and main sleep mode
In main clock mode or main sleep mode, the main clock (main OSC oscillation clock) and the
subclock (subclock OSC oscillation clock) are used for operation.
The operation clock is generated by dividing the main clock signal by two, and the subclock
signal (subclock OSC oscillation clock) is used as the timer clock signal while the PLL clock
(VCO oscillation clock) is stopped.
❍ Subclock mode and subclock sleep mode
In subclock mode or subclock sleep mode, only the subclock is used for operation. The
operation clock is generated by the subclock signal by fore, and the main clock and PLL clock
are stopped.
❍ PLL sleep mode and main sleep mode
In PLL sleep mode or main sleep mode, only the CPU operation clock is stopped. Clocks other
than the CPU clock are used for operation.
❍ Pseudo watch mode
In pseudo watch mode, only the watch timer and timebase timer are used for operation.
98
6.1 Low-Power Consumption Modes
❍ PLL watch mode, Main watch mode, and subclock watch mode
In PLL watch mode, main watch mode, or subclock watch mode, only the watch timer is used
for operation. Only the subclock signal is used for operation and the main clock and PLL clock
are stopped. PLL watch mode, main watch mode, and subclock watch mode are different in
that the operation modes at return by interrupts are PLL clock mode, main clock mode, and
subclock mode. The operation in the watch modes is the same.
❍ Main stop mode, subclock stop mode, and hardware standby mode
In main stop mode, subclock stop mode, or hardware standby mode, oscillation is stopped and
data can be held at the lowest power consumption level. Main stop mode and subclock stop
mode are different in that the operation mode at return by interrupts is main clock mode and
subclock mode. Operation in the stop modes is the same.
❍ Intermittent CPU operation function
The intermittent CPU operation function causes intermittent operation of the clock supplied to
the CPU when an internal register, internal memory, internal resource, or external bus is
accessed. The CPU execution speed is decreased while a high-speed clock is supplied to
internal resources, enabling processing with little power consumed.
The CS1 and CS0 bits are used to set the multiplication factor of the PLL clock. The
multiplication factor is obtained by multiplying the clock signal by 2, 4, 6, or 8. This clock signal
is divided by two and used as a machine clock signal.
Note:
In attempting to switch the clock mode, do not attempt to switch to another clock mode or
low-power consumption mode until the first switching is completed. The MCM and SCM bits
of the clock selection register (CKSCR) indicate that switching is completed.
99
CHAPTER 6 LOW-POWER CONSUMPTION MODES
■ Operation Status of Low-Power Consumption Mode
Table 6.1-1 "Operation Status in Low-Power Consumption Mode (Two clocks system parts)"
and Table 6.1-2 "Operation Status in Low-Power Consumption Mode (One clock system parts)
lists the chip operation status in each operation mode.
Table 6.1-1 Operation Status in Low-Power Consumption Mode (Two clocks system parts)
Transition
condition
Subclock
oscillation
Main
oscillation
Machine
clock
CPU
Peripheral
Pin
Subclock
SCS=0
MCS=x
Operating
Stopped
Operating
Operating
Operating
Operating
External
reset
Interrupt
Subclock
sleep
SCS=0
MCS=x
SLP=1
Operating
Stopped
Operating
Stopped
Operating
Operating
External
reset
Interrupt
Main
sleep
SCS=1
MCS=1
SLP=1
Operating
Operating
Operating
Stopped
Operating
Operating
External
reset
Interrupt
PLL
sleep
SCS=1
MCS=0
SLP=1
Operating
Operating
Operating
Stopped
Operating
Operating
External
reset
Interrupt
Pseudo
timer
(SPL=0)
SCS=1
MCS=0
STP=1
Operating
Operating
Stopped
Stopped
Stopped
Previous
status
held
External
reset
Interrupt *1
Pseudo
timer
(SPL=1)
SCS=1
MCS=0
STP=1
Operating
Operating
Stopped
Stopped
Stopped
HI-Z
External
reset
Interrupt *1
Timer
(SPL=0)
SCS=x
MCS=x
TMD=0
Operating
Stopped
Stopped
Stopped
Stopped
Previous
status
held
External
reset
Interrupt *2
Timer
(SPL=1)
SCS=x
MCS=x
TMD=0
Operating
Stopped
Stopped
Stopped
Stopped
HI-Z
External
reset
Interrupt *2
Stop
(SPL=0)
MCS=1
or SCS=0
STP=1
Stopped
Stopped
Stopped
Stopped
Stopped
Previous
status
held
External
reset
Interrupt *3
Stop
(SPL=1)
MCS=1
or SCS=0
STP=1
Stopped
Stopped
Stopped
Stopped
Stopped
HI-Z
External
reset
Interrupt *3
Hardware
standby
HST=L
Stopped
Stopped
Stopped
Stopped
Stopped
HI-Z
HST=H
Status
*1: Watch prescaler, timebase timer, and external interrupt
*2: Watch prescaler and external interrupt
*3: External interrupt
100
Release
method
6.1 Low-Power Consumption Modes
Table 6.1-2 Operation Status in Low-Power Consumption Mode (One clock system parts)
Transition
condition
Subclock
oscillation
Main clock
oscillation
Machine
clock
CPU
Peripherals
Pins
Release
method
Main sleep
SCS=1
MCS=1
SLP=1
-
Operating
Operating
Stopped
Operating
Operating
External
reset
interrupt
POLL sleep
SCS=1
MCS=0
SLP=1
-
Operating
Operating
Stopped
Operating
Operating
External
reset
interrupt
Pseudo
watch
(SPL=0)
SCS=1
MCS=0
STP=1
-
Operating
Stopped
Stopped
Stopped
Retained
External
reset
interrupt *4
Pseudo
watch
(SPL=1)
SCS=1
MCS=0
STP=1
-
Operating
Stopped
Stopped
Stopped
Hi-z
External
reset
interrupt *4
Stop
(SPL=0)
SCS=1
MCS=1
STP=1
-
Stopped
Stopped
Stopped
Stopped
Retained
External
reset
interrupt *5
Stop
(SPL=1)
SCS=1
MCS=1
STP=1
-
Stopped
Stopped
Stopped
Stopped
Hi-z
External
reset
interrupt *5
Hardware
standby
HST=L
-
Stopped
Stopped
Stopped
Stopped
Hi-z
HST=H
*4: Timebase timer and external interrupt
*5: External interrupt
101
CHAPTER 6 LOW-POWER CONSUMPTION MODES
6.1.1
Sleep Mode
In sleep mode, only the clock supplied to the CPU is stopped. As a result, the CPU
terminates while peripheral circuits keep operating.
However, the watch mode cannot be used in the one clock system parts.
■ Transition to Sleep Mode
Writing 1 to the SLP bit, 1 to the TMD bit, and 0 to the STP bit of low-power consumption mode
control register (LPMCR) starts transition to sleep mode.
If an interrupt request has been issued when "1" is written to the SLP bit, the standby control
circuit does not enter sleep mode. Therefore, the CPU executes the next instruction if the
interrupt cannot be accepted, or immediately branches to the interrupt processing routine if the
interrupt can be accepted.
In sleep mode, the values of special registers such as the accumulator and the internal RAM are
maintained.
■ Releasing Sleep Mode
The standby control circuit releases sleep mode in the event of a reset input or an interrupt. If
sleep mode is released by a reset, the reset status takes effect after sleep mode is released.
If a peripheral circuit or similar issues an interrupt request of a higher interrupt level than 7 in
sleep mode, the standby control circuit releases sleep mode. After sleep mode is released,
processing is handled as normal interrupt processing. The CPU executes the instruction that is
not in the standby write pending state, then executes interrupt processing when the interrupt
can be accepted according to the I flag in the condition code register (CCR), interrupt level
mask register (ILM), and interrupt control register (ICR). If the interrupt cannot be accepted,
processing continues with the instruction following the instruction that was placed in sleep
mode.
Note:
When subclock sleep mode is returned to main clock mode using an external reset pin (RST
pin), input level "L" for at least 2 machine cycles of the subclock.
102
6.1 Low-Power Consumption Modes
6.1.2
Pseudo Watch Mode
Pseudo watch mode stops operations other than source oscillation (main and
subclock), the watch timer, and the timebase timer.
■ Transition to Pseudo Watch Mode
Writing 1 to the SCS bit and 0 to the MCS bit of the clock selection register (CKSCR) and 1 to
the TMD bit and 1 to the STP bit of low-power consumption mode control register (LPMCR)
starts transition to pseudo watch mode.
The SPL bit of the low-power mode control register (LPMCR) can be used to control whether
the I/O pin is maintained at the immediately preceding status or at high impedance in pseudo
watch mode.
If an interrupt request has been issued when 1 is written to the STP bit, the standby control
circuit does not enter pseudo watch mode.
In pseudo watch mode, the values of special registers such as the accumulator and the internal
RAM register are maintained.
■ Releasing Pseudo Watch Mode
The standby control circuit releases pseudo watch mode when a reset signal is input or an
interrupt request is issued. If pseudo watch mode is released by a reset cause, the reset status
takes effect after pseudo watch mode is released.
To return from pseudo watch mode, the standby control circuit initially releases pseudo watch
mode, then enters the PLL clock oscillation stabilization wait state. When the release of pseudo
watch mode starts by an interrupt request, the reset sequence is performed using the main
clock.
If a peripheral resource circuit issues an interrupt request of a higher interrupt level than 7, the
standby control circuit releases pseudo watch mode. After pseudo watch mode is released,
processing is handled as normal interrupt processing. The CPU executes the instruction that
both is not in the write pending state and follows the standby write instruction, then executes
interrupt processing when the interrupt can be accepted according to the I flag in the condition
code register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR). If
the interrupt cannot be accepted, processing continues with the instruction following the
instruction that was executed before transition to pseudo watch mode.
Notes: [only for MB90437L(S)/438L(S)]
•
When pseudo watch mode is returned to main clock mode using an external reset pin (RST
pin), input level "L" for at least 100 μs.
•
When pseudo watch mode is returned by an interrupt, the interrupt processing is performed
after the maximum 80 μs after the interrupt request is accepted.
103
CHAPTER 6 LOW-POWER CONSUMPTION MODES
6.1.3
Watch Mode
Watch mode stops operations other than subclock source oscillation and the watch
timer.
However, the watch mode cannot be used in the one clock system parts.
■ Transition to Watch Mode
Writing 0 to the TMD bit of the clock selection register (CKSCR) starts transition to watch mode.
The SPL bit of the low-power mode control register (LPMCR) can be used to control whether
the I/O pin is maintained at the immediately preceding status or at high impedance in pseudo
watch mode.
If an interrupt request has been issued when 1 is written to the TMD bit, the standby control
circuit does not enter watch mode.
In watch mode, the values of special registers such as the accumulator and the internal RAM
register are maintained.
■ Releasing Watch Mode
The standby control circuit releases watch mode when a reset signal is input or an interrupt
request is issued. If watch mode is released by a reset cause, the reset status takes effect after
watch mode is released.
To return from subclock watch mode, the standby control circuit initially releases watch mode,
then immediately enters subclock state. When the release of subclock watch mode is a reset
cause, the reset sequence is performed using the subclock signal.
To return from main watch mode or PLL watch mode, the standby control circuit initially
releases watch mode, then enters the main clock oscillation stabilization wait state. When the
release of watch mode is a reset cause, the reset sequence is performed using the subclock
signal.
If a peripheral resource circuit issues an interrupt request of a higher interrupt level than 7, the
standby control circuit releases watch mode. After pseudo watch mode is released, processing
is handled as normal interrupt processing. The CPU executes the instruction that both is not in
the write pending state and follows the standby write instruction, then executes interrupt
processing when the interrupt can be accepted according to the I flag in the condition code
register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR). If the
interrupt cannot be accepted, processing continues with the instruction following the instruction
that was executed before transition to pseudo watch mode.
Note:
When watch mode is returned to main clock mode using an external reset pin (RST pin),
input level "L" for at least 2 machine cycles of the subclock.
104
6.1 Low-Power Consumption Modes
6.1.4
Stop mode
Stop mode stops source oscillation (main and subclock). Data can be maintained at
the lowest power consumption level.
■ Transition to Stop Mode
Writing 0 to the SCS bit or 1 to the MCS bit of the clock control register and 1 to the STP bit of
the low-power mode control register (LPMCR) causes the standby control circuit to enter stop
mode.
The SPL bit of the low-power mode control register (LPMCR) can be used to control whether
the I/O pin is maintained at the immediately preceding status or at high impedance.
If an interrupt request has been issued when 1 is written to the STP bit, the standby control
circuit does not enter stop mode.
In stop mode, the values of special registers such as the accumulator and the internal RAM
register are maintained.
■ Releasing Stop Mode
The standby control circuit releases stop mode when a reset signal is input or an interrupt is
generated. If stop mode is released by a reset cause, the reset status takes effect after stop
mode is released.
To return from subclock watch mode, the standby control circuit initially enters subclock
oscillation stabilization wait mode, then releases stop mode. When the release of stop mode is
a reset cause, the reset sequence is performed after the subclock oscillation stabilization wait
time elapses.
To return from main stop mode, the standby control circuit initially enters main clock oscillation
stabilization wait mode, then releases stop mode. When the release of stop mode is a reset
cause, the reset sequence is performed after the main clock oscillation stabilization wait time
elapses.
If a peripheral circuit or other resource issues an interrupt request of a higher interrupt level than
7 in stop mode, the standby control circuit releases stop mode. After subclock stop mode is
released, the subclock oscillation stabilization wait time applies and processing is handled as
normal interrupt processing. The CPU executes the instruction that both is not in the write
pending state and follows the standby write instruction, then executes interrupt processing when
the interrupt can be accepted according to the I flag in the condition code register (CCR),
interrupt level mask register (ILM), and interrupt control register (ICR). If the interrupt cannot be
accepted, processing continues with the instruction following the instruction that was executed
before transition to stop mode.
After main stop mode is released, the oscillation stabilization wait time specified in WS1 and
WS0 bits of the clock selection register (CKSCR) elapses and processing is then handled as
normal interrupt processing. The CPU executes the instruction that both is not in the write
pending state and follows the standby write instruction, then branches to interrupt processing
when the interrupt can be accepted according to the I flag in the condition code register (CCR),
interrupt level mask register (ILM), and interrupt control register (ICR). If the interrupt cannot be
accepted, processing continues with the instruction following the instruction that was executed
before transition to stop mode.
105
CHAPTER 6 LOW-POWER CONSUMPTION MODES
Note:
When stop mode is returned to main clock mode using an external reset pin (RST pin), input
level "L" for at least the oscillation time of the oscillator (*1) + 4 machine cycles.
*1: The oscillation time of the oscillator is the time required to reach 90% of amplitude. It
takes several to dozens of ms for crystal oscillators, hundreds of μs to several ms for
FAR/ceramic oscillators, and 0 ms for external clocks.
106
6.1 Low-Power Consumption Modes
6.1.5
Hardware Standby Mode
In the hardware standby mode, oscillation is stopped and all I/O pins are set to high
impedance while the HST pin is at "L" level, regardless of other statuses (including
reset).
■ Transition to Hardware Standby Mode
The standby control circuit can be set in hardware standby mode from any status by setting the
HST pin at "L" level. In hardware standby mode, oscillation is stopped and all I/O pins are set to
high impedance while the HST pin is at "L" level, regardless of other status including reset.
In hardware standby mode, the internal RAM contents are maintained but the special registers
such as the accumulator are initialized.
■ Releasing Hardware Standby Mode
Hardware standby mode can be released only by the HST pin. When the HST pin is set at "H"
level, the standby control circuit releases hardware standby mode, enables the internal reset
signal, and enters oscillation stabilization wait status. After the oscillation stabilization wait
period, the standby control circuit releases the internal reset, and consequently the CPU starts
execution from the reset sequence.
The oscillation stabilization wait time for hardware standby mode is fixed to 218 cycles of the
source oscillation.
107
CHAPTER 6 LOW-POWER CONSUMPTION MODES
6.1.6
Intermittent CPU Operation
The intermittent CPU operation function delays the activity of the internal bus cycle to
stop the clock supplied to the CPU when a register, internal memory (ROM, RAM, I/O or
resource), or the external bus is accessed. While a high-speed clock is supplied to
internal resources, the CPU execution speed is decreased, thus enabling processing
with little power consumed. The CG1 and CG0 bits are used to specify the cycle count
for clock stop.
External bus operation is performed using the same clock as that for the resource.
■ Intermittent CPU Operation
The instruction execution time using the intermittent CPU operation function can be obtained by
adding a compensation value to the ordinary execution time. The compensation value is
obtained by multiplying the number of accesses to a register, internal memory, internal
resource, or external bus by the cycle count for pausing.
108
6.2 Status Transitions in Low-Power Consumption Mode
6.2
Status Transitions in Low-Power Consumption Mode
In low-power consumption mode, the transition to each status is based on the
condition set in the clock selection register or low-power mode control register.
■ Transition Conditions in Low-Power Consumption Mode
The meanings of symbols used in the table and figure are explained below:
•
MCS: MCS bit (clock selection register) (PLL clock mode selected when MSC=0)
•
SCS: SCS bit (clock selection register) (subclock mode selected when SCS=0)
•
STP: STP bit (low-power mode control register) (stop mode selected when STP=1)
•
SLP: SLP bit (low-power mode control register) (sleep mode selected when SLP=1)
•
TMD: TMD bit (low-power mode control register) (watch mode selected when TMD=0)
•
MCM: MCM bit (clock selection register) (PLL clock used when MCM=0)
•
SCM: SCM bit (clock selection register) (subclock used when SCM=0)
•
SCD: Subclock oscillation stop (subclock oscillation stopped when SCD=1)
•
MCD: Main clock oscillation stop (main clock oscillation stopped when MCD=1)
•
PCD: PLL clock oscillation stop (PLL clock oscillation stopped when PCD=1)
Table 6.2-1 Transition Conditions of the Two Clocks System Parts
Status before transition
Transition condition
Status after transition
Power-on
01 Main oscillation stabilization wait
termination
Main mode
Main oscillation stabilization
05 Main oscillation stabilization wait
termination
Main mode
Main mode
06 SCS=0 write
MS transition mode
07 SCS=1, MCS=0 write
MP transition mode
31 TMD=1, STP=0, SLP=1 write
Main sleep mode
32 TMD=0 write
Main timer transition mode
33 TMD=1, STP=1 write
Main stop
21 SCS=0 write
PS transition mode
20 SCS=1, MCS1 write
PM transition mode
59 TMD=1, STP=0, SLP=1 write
PLL sleep mode
58 TMD=0 write
PLL timer transition P
57 TMD=1, STP=1 write
Pseudo timer transition mode
PLL mode
109
CHAPTER 6 LOW-POWER CONSUMPTION MODES
Table 6.2-1 Transition Conditions of the Two Clocks System Parts (Continued)
Status before transition
Subclock mode
PM transition mode
SM transition mode
MP transition mode
110
Transition condition
Status after transition
10 SCS=1, MCS1 write
SM transition mode
12 SCS=1, MCS=0 write
SP transition mode
11 Reset activation
Main oscillation stabilization
42 TMD=1, STP=0, SLP=1 write
Subclock sleep mode
43 TMD=0 write
Subclock watch mode
44 TMD=1, STP=1 write
Subclock stop mode
13 PLL -> main switch wait termination
Main mode
38 TMD=1, STP=0, SLP=1 write
PM transition sleep mode
39 TMD=0 write and PLL -> main switch wait
termination
Main timer transition mode
40 TMD=1, STP =1 write and PLL -> main
switch wait termination
Main stop mode
02 Main oscillation stabilization time wait
termination
Main mode
03 Reset activation or interrupt
Main oscillation stabilization
04 SCS=0 write
Subclock mode
27 TMD=1, STP=0, SLP=1 write
SM transition sleep mode
28 TMD=0 write and main oscillation
stabilization wait termination
Main watch mode
29 TMD=1, STP=1 write and main oscillation
stabilization wait termination
Main stop mode
16 PLL oscillation stabilization wait
termination
PLL mode
14 SCS=1, MCS=1 write
Main mode
15 SCS=0 write
MS transition mode
68 TMD=1, STP=0, SLP=1 write
MP transition sleep mode
70 TMD=0 write
PLL timer transition mode
69 TMD=1, STP=1 write
Pseudo watch mode
6.2 Status Transitions in Low-Power Consumption Mode
Table 6.2-1 Transition Conditions of the Two Clocks System Parts (Continued)
Status before transition
SP transition mode
Transition condition
Status after transition
17 Main oscillation stabilization wait
termination
MP transition mode
18 MCS=1 write
SM transition mode
19 Reset activation
Main oscillation stabilization
75 TMD=1, STP=0, SLP=1 write
SP transition sleep mode
76 TMD=0 write
PLL watch mode
78 TMD=1, STP=1 write and main oscillation
stabilization wait termination
Pseudo watch mode
09 Main -> subclock switch wait termination
Subclock mode
08 Reset activation
Main mode
51 TMD=1, STP=0, SLP=1 write
MS transition sleep mode
52 TMD=0 write and main -> subclock switch
wait termination
Subclock watch mode
53 TMD=1, STP=1 write and main ->
subclock switch wait termination
Subclock stop mode
23 PLL -> main clock switch wait termination
MS transition mode
22 SCS=1 write
PM transition mode
56 TMD=1, STP=0, SLP=1 write
PS transition sleep mode
Main sleep
26 Interrupt or reset activation
Main mode
SM transition sleep
24 Main oscillation stabilization wait
termination
Main sleep
25 Interrupt or reset activation
SM transition mode
34 PLL -> main clock switch wait termination
Main sleep mode
35 Interrupt or reset activation
PM transition mode
PLL sleep mode
63 Interrupt or reset activation
PLL mode
MP transition sleep
66 PLL oscillation stabilization wait
termination
PLL sleep mode
67 Interrupt or reset activation
MP transition mode
73 Main oscillation stabilization wait
termination
MP transition sleep
74 Interrupt or reset activation
SP transition mode
Subclock sleep
46 Interrupt or reset activation
Subclock mode
MS transition sleep
49 Main -> subclock switch wait termination
Subclock sleep mode
50 Interrupt or reset activation
MS transition mode
MS transition mode
PS transition mode
PM transition sleep
SP transition sleep
111
CHAPTER 6 LOW-POWER CONSUMPTION MODES
Table 6.2-1 Transition Conditions of the Two Clocks System Parts (Continued)
Status before transition
PS transition sleep
Transition condition
Status after transition
54 PLL -> main clock switch wait termination
MS transition sleep mode
55 Interrupt or reset activation
PS transition mode
Main timer
30 Interrupt or reset activation
SM transition mode
Main timer transition
36 Main -> subclock switch wait termination
Main timer
37 Interrupt or reset activation
Main mode
PLL timer
77 Interrupt or reset activation
SP transition mode
PLL timer transition M
72 Main -> subclock switch wait termination
PLL timer
71 Interrupt or reset activation
MP transition mode
65 PLL -> main clock switch wait termination
PLL time transition M
64 Interrupt or reset activation
PLL mode
Subclock timer
47 Interrupt or reset activation
Subclock mode
Main stop
41 Interrupt or reset activation
Main oscillation stabilization
Pseudo timer
62 Interrupt or reset activation
MP transition mode
Pseudo timer transition
61 PLL -> main clock switch wait termination
Pseudo watch mode
60 Interrupt or reset activation
PLL mode
48 Interrupt
Subclock oscillation stabilization
79 Reset activation
Main oscillation stabilization
45 Subclock oscillation stabilization
termination
Subclock mode
80 Reset activation
Main oscillation stabilization
PLL timer transition P
Subclock stop
Subclock oscillation
stabilization
Note:
•
When stop mode is returned to main clock mode using an external reset pin (RST pin), input
level "L" for at least the oscillation time of the oscillator (*1) + 4 machine cycles.
*1: The oscillation time of the oscillator is the time required to reach 90% of amplitude. It
takes several to dozens of ms for crystal oscillators, hundreds of μs to several ms for
FAR/ceramic oscillators, and 0 ms for external clocks.
•
112
When subclock mode, sleep mode or watch mode is returned to main clock mode using an
external reset pin (RST pin), input level "L" for at least 2 machine cycles of the subclock.
6.2 Status Transitions in Low-Power Consumption Mode
Table 6.2-2 Transition Conditions of the One Clock System Parts
Status before
transition
Transition condition
Status after transition
Power-on
01
Main oscillation stabilization time end
Main mode
Main oscillation
stabilization
05
Main oscillation stabilization time end
Main mode
07
SCS=1, MCS=0 write
MP transition mode
31
TMD=1, STP=0, SLP=1 write
Main sleep
33
TMD=1, STP=1 write
Main stop
20
SCS=1, MCS=1 write
PM transition mode
59
TMD=1, STP=0, SLP=1 write
PLL sleep
57
TMD=1, STP=1 write
Pseudo watch transition
13
PLL/main switching timing wait end
Main mode
38
TMD=1, STP=0, SLP=1 write
PM transition sleep
40
TMD=1, STP=1 write & PLL to main switching
timing wait end
Main stop
16
PLL oscillation stabilization wait time end
PLL mode
14
SCS=1, MCS=1 write
Main mode
68
TMD=1, STP=0, SLP=1 write
MP transition sleep
69
TMD=1, STP=1 write
Pseudo watch mode
Main sleep
26
Interrupt or reset activation
Main mode
PM transition sleep
34
PLL/main switching timing wait end
Main sleep
35
Interrupt or reset activation
PM transition mode
PLL sleep
63
Interrupt or reset activation
PLL mode
MP transition sleep
66
PLL oscillation stabilization wait time end
PLL sleep
67
Interrupt or reset activation
MP transition mode
Main stop
41
Interrupt or reset activation
Main oscillation
stabilization
Pseudo watch
62
Interrupt or reset activation
MP transition mode
Pseudo watch transition
61
PLL/main switching timing wait end
Pseudo watch mode
60
Interrupt or reset activation
PLL mode
Main mode
PLL mode
PM transition mode
MP transition mode
Note:
When stop mode is returned to main clock mode using an external reset pin (RST pin), input
level "L" for at least the oscillation time of the oscillator (*1) + 4 machine cycles.
*1: The oscillation time of the oscillator is the time required to reach 90% of amplitude. It
takes several to dozens of ms for crystal oscillators, hundreds of μs to several ms for
FAR/ceramic oscillators, and 0 ms for external clocks.
113
CHAPTER 6 LOW-POWER CONSUMPTION MODES
6.3
Status Transition Diagram for Low-Power Consumption
Mode
Figure 6.3-1 "Status Transition Diagram A for Low-Power Consumption Mode (Two
Clocks System Parts)" to Figure 6.3-7 "Status Transition Diagram for Low-Power
Consumption Mode (One Clock System Parts) 3" are status transition diagrams.
For simplification, the status transition diagrams show events that occur
simultaneously as stepwise transitions. In actuality, status transition take place
instantaneously.
■ Status Transition Diagram for Low-Power Consumption Mode (Two Clocks System Parts)
For simplification, the status transition diagram shows events that occur simultaneously as
stepwise transitions. In actuality, however, status transitions take place instantaneously.
In the status transition diagram, if MSC=1 and SLP=1 are set simultaneously in PLL clock
mode, a transition to PM transition mode is followed by a transition to PM transition sleep. In
actuality, however, a transition from PLL clock mode to PM transition sleep takes place
instantaneously. If reset is activated in subclock sleep mode, a transition to subclock mode is
followed by a transition to a main oscillation stabilization period. In actuality, however, a
transition from subclock sleep mode to a main oscillation stabilization period takes place.
Note:
•
When stop mode is returned to main clock mode using an external reset pin (RST pin), input
level "L" for at least the oscillation time of the oscillator (*1) + 4 machine cycles.
*1: The oscillation time of the oscillator is the time required to reach 90% of amplitude. It
takes several to dozens of ms for crystal oscillators, hundreds of μs to several ms for
FAR/ceramic oscillators, and 0 ms for external clocks.
•
114
When subclock mode, sleep mode or watch mode is returned to main clock mode using an
external reset pin (RST pin), input level "L" for at least 2 machine cycles of the subclock.
6.3 Status Transition Diagram for Low-Power Consumption Mode
Figure 6.3-1 Status Transition Diagram A for Low-Power Consumption Mode (Two Clocks System Parts)
Power-on reset
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=1
SCM=1,MCM=1,
SCD=0, MCD=0,
PCD=1
SM transition mode
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=1
SCM=0,MCM=1,
SCD=0, MCD=0,
PCD=1
Main oscillation
stabilization period
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=1
SCM=1,MCM=1,
SCD=0, MCD=0,
PCD=1
03
04
02
01
05
10
11
Main mode
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=1
SCM=1,MCM=1,
SCD=0, MCD=0,
PCD=1
06
MS transition mode
SCS=0, MCS=x,
STP=0, SLP=0,
TMD=1
08
SCM=1,MCM=1,
SCD=0, MCD=0,
PCD=1
Subclock mode
SCS=0, MCS=x,
STP=0, SLP=0,
TMD=1
SCM=0,MCM=1,
SCD=0, MCD=1,
PCD=1
09
07
12
18
13
PM transition mode
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=1
SCM=1,MCM=0,
SCD=0, MCD=0,
PCD=1
19
15
14
MP transition mode
SCS=1, MCS=0,
STP=0, SLP=0,
TMD=1
SCM=1,MCM=1,
SCD=0, MCD=0,
PCD=0
17
SP transition mode
SCS=1, MCS=0,
STP=0, SLP=0,
TMD=1
SCM=0,MCM=1,
SCD=0, MCD=0,
PCD=1
16
23
20
PLL mode
SCS=1, MCS=0,
STP=0, SLP=0,
TMD=1
SCM=1,MCM=0,
SCD=0, MCD=0,
PCD=0
22
21
PS transition mode
SCS=0, MCS=x,
STP=0, SLP=0,
TMD=1
SCM=1,MCM=0,
SCD=0, MCD=0,
PCD=0
115
CHAPTER 6 LOW-POWER CONSUMPTION MODES
Figure 6.3-2 Status Transition Diagram B for Low-Power Consumption Mode (Two Clocks System Parts)
SM transition sleep
SCS=1, MCS=1,
STP=0, SLP=1,
TMD=1
SCM=0, MCM=1,
SCD=0, MCD=0,
PCD=1
Main sleep
SCS=1, MCS=1,
STP=0, SLP=1,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=1
24
26
25
27
31
SM transition mode
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=1
SCM=0, MCM=1,
SCD=0, MCD=0,
PCD=1
28
30
Main timer
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=0
SCM=0, MCM=1,
SCD=0, MCD=1,
PCD=1
Main mode
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=1
32
29
03
33
37
34
36
PM transition sleep
SCS=1, MCS=1,
STP=0, SLP=1,
TMD=1
SCM=1, MCM=0,
SCD=0, MCD=0,
PCD=0
05
Main oscillation
stabilization time
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=1
Main timer transition
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=0
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=1
35
38
39
PM transition mode
SCS=1, MCS=1,
STP=0, SLP=0,
TMD=1
SCM=1, MCM=0,
SCD=0, MCD=0,
PCD=0
116
40
Main stop
SCS=1,
STP=1,
TMD=1
SCM=1,
SCD=1,
PCD=1
MCS=1,
SLP=0,
MCM=1,
MCD=1,
41
6.3 Status Transition Diagram for Low-Power Consumption Mode
Figure 6.3-3 Status Transition Diagram C for Low-Power Consumption Mode (Two Clocks System Parts)
Subclock mode
SCS=0, MCS=x,
STP=0, SLP=0,
TMD=1
SCM=0, MCM=1,
SCD=0, MCD=1,
PCD=1
42
45
44
Subclock oscillation
stabilization time
SCS=0, MCS=x,
STP=0, SLP=0,
TMD=1
SCM=0, MCM=1,
SCD=0, MCD=1,
PCD=1
Main oscillation
stabilization time
SCS=1, MCS=x,
STP=0, SLP=0,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=1
80
43
46
48
Subclock sleep
SCS=0, MCS=x,
STP=0, SLP=1,
TMD=1
SCM=0, MCM=1,
SCD=0, MCD=1,
PCD=1
47
49
Subclock timer
SCS=0, MCS=x,
STP=0, SLP=0,
TMD=0
SCM=0, MCM=1,
SCD=0, MCD=1,
PCD=1
79
Subclock stop
SCS=0, MCS=x,
STP=1, SLP=0,
TMD=1
SCM=0, MCM=1,
SCD=1, MCD=1,
PCD=1
52
53
MS transition sleep
SCS=0, MCS=x,
STP=0, SLP=1,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=1
51
50
MS transition mode
SCS=0, MCS=x,
STP=0, SLP=0,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=1
23
54
PM transition sleep
SCS=1, MCS=x,
STP=0, SLP=1,
TMD=1
SCM=1, MCM=0,
SCD=0, MCD=0,
PCD=0
56
55
PM transition mode
SCS=0, MCS=x,
STP=0, SLP=0,
TMD=1
SCM=1, MCM=0,
SCD=0, MCD=0,
PCD=0
117
CHAPTER 6 LOW-POWER CONSUMPTION MODES
Figure 6.3-4 Status Transition Diagram D for Low-Power Consumption Mode (Two Clocks System Parts)
PLL mode
SCS=1, MCS=0,
STP=0, SLP=0,
TMD=1
SCM=1, MCM=0,
SCD=0, MCD=0,
PCD=0
57
58
60 Pseudo timer transition
SCS=1, MCS=0,
61
STP=1, SLP=0,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=0
62
Pseudo timer mode
SCS=1, MCS=0,
STP=1, SLP=0,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=1
59
63
PLL sleep
SCS=1, MCS=0,
STP=0, SLP=1,
TMD=1
SCM=1, MCM=0,
SCD=0, MCD=0,
PCD=1
64
PLL timer transition P
SCS=1, MCS=0,
STP=0, SLP=0,
TMD=0
SCM=1, MCM=0,
SCD=0, MCD=0
PCD=0
65
16
66
MP transition sleep
SCS=1, MCS=0,
STP=0, SLP=1,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=0
69
68
67
MP transition mode
SCS=1, MCS=0,
STP=0, SLP=0,
TMD=1
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=0
70
71 PLL timer transition M
SCS=1, MCS=0,
STP=0, SLP=0,
TMD=0
SCM=1, MCM=1,
SCD=0, MCD=0,
PCD=1
78
73
SP transition sleep
SCS=1, MCS=0,
STP=0, SLP=1,
TMD=1
SCM=0, MCM=1,
SCD=0, MCD=0,
PCD=1
17
75
74
SP transition mode
SCS=1, MCS=0,
STP=0, SLP=0,
TMD=1
SCM=0, MCM=1,
SCD=0, MCD=0,
PCD=1
72
77
76
PLL timer
SCS=1, MCS=0,
STP=0, SLP=0,
TMD=0
SCM=0, MCM=1,
SCD=0, MCD=1,
PCD=1
Note:
In attempting to switch the clock mode, do not attempt to switch to another clock mode or
low-power consumption mode until the first switching is completed. The MCM and SCM bits
of the clock selection register (CKSCR) indicate that switching is completed.
118
6.3 Status Transition Diagram for Low-Power Consumption Mode
■ Status Transition Diagram for Low-Power Consumption Mode (One Clock System Parts)
Figure 6.3-5 Status Transition Diagram for Low-Power Consumption Mode (One Clock System Parts) 1
Power-on reset
SCS=1,MCS=1
STP=0,SLP=0
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=1
Main oscillation
stabilization time
SCS=1,MCS=1
STP=0,SLP=0
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=1
05
01
Main mode
SCS=1,MCS=1
STP=0,SLP=0
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=1
07
13
PM transition mode
SCS=1,MCS=1
STP=0,SLP=0
TMD=1
SCM=1,MCM=0
SCD=0,MCD=0
PCD=0
14
MP transition mode
SCS=1,MCS=0
STP=0,SLP=0
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=0
16
20
PLL mode
SCS=1,MCS=0
STP=0,SLP=0
TMD=1
SCM=1,MCM=0
SCD=0,MCD=0
PCD=0
119
CHAPTER 6 LOW-POWER CONSUMPTION MODES
Figure 6.3-6 Status Transition Diagram for Low-Power Consumption Mode (One Clock System Parts) 2
Main sleep
SCS=1,MCS=1
STP=0,SLP=1
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=1
26
31
Main mode
SCS=1,MCS=1
STP=0,SLP=0
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=1
33
34
05
PM transition sleep
SCS=1,MCS=1
STP=0,SLP=1
TMD=1
SCM=1,MCM=0
SCD=0,MCD=0
PCD=0
Main oscillation
stabilization time
SCS=1,MCS=1
STP=0,SLP=0
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=1
35
38
PM transition mode
SCS=1,MCS=1
STP=0,SLP=0
TMD=1
SCM=1,MCM=0
SCD=0,MCD=0
PCD=0
120
40
Main stop
SCS=1,MCS=1
STP=1,SLP=0
TMD=1
SCM=1,MCM=1
SCD=1,MCD=1
PCD=1
41
6.3 Status Transition Diagram for Low-Power Consumption Mode
Figure 6.3-7 Status Transition Diagram for Low-Power Consumption Mode (One Clock System Parts) 3
PLL mode
SCS=1,MCS=0
STP=0,SLP=0
TMD=1
SCM=1,MCM=0
SCD=0,MCD=0
PCD=0
57
60 Pseudo watch
transition
SCS=1,MCS=0
STP=1,SLP=0
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=1
61
62
Pseudo watch mode
SCS=1,MCS=0
STP=1,SLP=0
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=1
59
63
PLL sleep
SCS=1,MCS=0
STP=0,SLP=1
TMD=1
SCM=1,MCM=0
SCD=0,MCD=0
PCD=0
16
69
66
MS transition sleep
SCS=1,MCS=0
STP=0,SLP=1
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
67
PCD=0
68
MP transition mode
SCS=1,MCS=0
STP=0,SLP=0
TMD=1
SCM=1,MCM=1
SCD=0,MCD=0
PCD=0
Note:
In attempting to switch the clock mode, do not attempt to switch to another clock mode or
low-power consumption mode until the first switching is completed. The MCM bit of the clock
selection register (CKSCR) indicates that switching is completed.
121
CHAPTER 6 LOW-POWER CONSUMPTION MODES
122
CHAPTER 7
MEMORY ACCESS MODES
This chapter explains the functions and operations of the memory access modes.
7.1 "Outline of Memory Access Modes"
7.2 "External Memory Access (Bus Pin Control Circuit)
7.3 "External Memory Access Control Signal Operation
123
CHAPTER 7 MEMORY ACCESS MODES
7.1
Outline of Memory Access Modes
In the F2MC-16LX, various modes are provided for access methods and access areas.
■ Memory Access Modes
Table 7.1-1 Mode Pins and Modes
Operation mode
Bus mode
Access mode
Single chip
-
Internal ROM, external bus
8 bits
RUN
16 bits
External ROM, external bus
8 bits
16 bits
Flash programming
-
-
Test functions
-
-
❍ Operation mode
Operation mode means the mode for controlling the device operation status. The operation
mode is specified by the MDx mode setting pin and the Mx bit in mode data. By selecting an
operation mode, ordinary operation can be activated and flash memory can be written.
❍ Bus mode
Bus mode means the mode for controlling the internal ROM operation and external access
function. The bus mode is specified by the MDx mode setting pin and the Mx bit in mode data.
The MDx mode setting pin specifies the bus mode for reading the reset vector and mode data,
and the Mx bit in mode data specifies the bus mode for normal operation.
❍ Access mode
Access mode means the mode for controlling the external data bus width. The access mode is
specified by the MDx mode setting pin and the S0 bit in mode data. By selecting an access
mode, an 8- or 16-bit external data bus is specified.
124
7.1 Outline of Memory Access Modes
7.1.1
Mode Pins
Table 7.1-2 "Mode Pins and Modes" lists the operations that can be specified by
combining the three external pins MD2 to MD0.
■ Mode pins
Table 7.1-2 Mode Pins and Modes
Mode pin setting
Mode name
Reset
vector
access area
External
data bus
width
Remarks
MD2
MD1
MD0
0
0
0
External vector mode 0
External
8 bits
0
0
1
External vector mode 1
External
16 bits
Reset vector, 16-bit
bus width access
0
1
0
Reserved
Internal
(Mode data)
Reset sequence and
later segments are
controlled based on
mode data.
0
1
1
Internal vector mode
1
0
0
1
0
1
1
1
0
Flash memory serial
programming (*1)
-
-
1
1
1
Flash memory
-
-
Reserved
Mode when parallel
writer is used
*1: Data cannot be written only by setting the flash serial programming mode by mode pins.
Other must be set. For detail, see CHAPTER 24 "EXAMPLES OF MB90F438L(S)/F439(S) SERIAL
PROGRAMMING CONNECTION".
125
CHAPTER 7 MEMORY ACCESS MODES
7.1.2
Mode Data
Mode data is stored at FFFFDFH of main memory and used for controlling the CPU
operation. This data is fetched during a reset sequence and stored in the mode
register inside the device. The mode register value can be changed only by a reset
sequence.
The setting of this register is valid after the reset sequence.
Always set the reserved bits to "0".
■ Mode Data
Figure 7.1-1 Mode Data Configuration
Mode data address
address FFFFDFH
7
6
5
M1
M0
4
3
Reserved Reserved
S0
2
1
0
Bit No.
Reserved Reserved Reserved
[Bits 7 and 6] M1, M0 (bus mode setting bits)
The M1 and M0 bits are used to specify the operation mode after the reset sequence is
completed. Table 7.1-3 "M1 and M0 (Bus Mode Setting Bit) Functions" shows the
relationship between the M1 and M0 bits and the functions.
Table 7.1-3 M1 and M0 (Bus Mode Setting Bit) Functions
M1
M0
Function
0
0
Single-chip mode
0
1
Internal ROM, external bus mode
1
0
External ROM, external bus mode
1
1
Setting prohibited
Remarks
[Bit 3] S0 (mode setting bit)
The S0 bit is used to specify the bus mode or access mode after the reset sequence is
completed. Table 7.1-4 "S0 (Mode Setting Bit) Functions" shows the relationship between
the S0 bit and the functions.
Table 7.1-4 S0 (Mode Setting Bit) Functions
S0
126
Function
0
External 8-bit data bus mode
1
External 16-bit data bus mode
Remarks
7.1 Outline of Memory Access Modes
7.1.3
Memory Space in Each Bus Mode
Figure 7.1-2 "Relationship between Access Areas and Physical Addresses for Each
Bus Mode" shows the correspondence between the access areas and physical
addresses for each bus mode.
■ Memory Space in Each Bus Mode
Figure 7.1-2 Relationship between Access Areas and Physical Addresses for Each Bus Mode
FFFFFFH
ROM area
ROM area
ROM area
(FF bank image)
ROM area
(FF bank image)
I/O
I/O
I/O
RAM
RAM
RAM
Address #1
010000H
004000H
003900H
Address #2
Address #3
: Internal
: External
000100H
0000C0H
I/O
I/O
Single chip
Internal ROM, external bus
000000H
Model
I/O
: No access
External ROM, external bus
Address #1
Address #2
Address #3
MB90437L(S) *1
FF0000H
002000H
000900H
MB90F438L(S)/438L(S)
FE0000H
002000H
001100H
MB90F439(S)/439(S)
FC0000H
002100H
001900H
(FC0000H)
002100H
002100H
MB90V540G
*1: Under development
127
CHAPTER 7 MEMORY ACCESS MODES
■ Recommended Setting
Table 7.1-5 "Example of Recommended Settings for Mode Pins and Mode Data" lists an
example of recommended settings for mode pins and mode data.
Table 7.1-5 Example of Recommended Settings for Mode Pins and Mode Data
Sample setting
MD1
MD1
MD0
M1
M0
S0
Single chip
0
1
1
0
0
x
Internal ROM and external bus mode, 16-bit bus
0
1
1
0
1
1
Internal ROM and external bus mode, 8-bit bus
0
1
1
0
1
0
External ROM and external bus mode, 16-bit bus,
vector 16 bus width
0
0
1
1
0
1
External ROM and external bus mode, 8-bit bus
0
0
0
1
0
0
External pins have signal functions that depend on each mode.
Table 7.1-6 External Pin Functions for Each Mode
Function
Pin name
External bus expansion
Single chip
8 bits
P07 to 00
16 bits
AD07 to 00
P17 to 10
A15 to 08
Flash
programming
D07 to 00
AD15 to 08
A15 to 08
P27 to 20
A23 to 16*
A07 to 00
P30
ALE
A16
P31
RD
CEX
P32
P33
Port
WR *
WRL *
OEX
Port
WRH *
PGMX
P34
HRQ*
P35
HAK *
P36
RDY*
P37
CLK*
Unused
Note:
The upper address output pins and the WRL/WR, WRH, HRQ, HAK, RDY, and CLK pins can be used as
ports through function selection. See Section 7.2 "External Memory Access (Bus Pin Control Circuit)" for
details.
128
7.2 External Memory Access (Bus Pin Control Circuit)
7.2
External Memory Access (Bus Pin Control Circuit)
The external bus pin control circuit controls the external bus pins for external
expansion of the CPU address and data buses.
■ External Memory Access (Bus Pin Control Circuit)
The following address, data, and control signals are used to access external memory and
peripherals of the device:
•
CLK (P37): Machine cycle clock (KBP) output pin
•
RDY (P36): External ready input pin
•
WRH (P33): Write signal for upper 8 bits of data bus
•
WRL/WR (P32): Write signal for lower 8 bits of data bus in 16-bit access mode, for 8-bit
access mode
•
RD (P31): Read signal
•
ALE (P30): Address latch enable signal
The external bus pin control circuit is used to control the external bus pins to enable external
expansion of the CPU address and data buses.
■ Block Diagram of External Memory Access
Figure 7.2-1 External Bus Controller
P0
P0 data
P1
P2
P3
P3
P0
P0 direction
RB
Data control
Address control
Access control
Access control
129
CHAPTER 7 MEMORY ACCESS MODES
7.2.1
External Memory Access (External Bus Pin Control
Circuit) Registers
External memory access (external bus pin control circuit) uses the following three
types of registers:
• Automatic ready function selection register
• External address output control register
• Bus control signal selection register
■ External Memory Access Registers
Figure 7.2-2 External memory access (external bus pin control circuit) registers
Automatic ready function selection register
15
Address:0000A5H
Read/write
Initial value
14
13
12
11
10
IOR1 IOR0 HMR1 HMR0
(W)
(0)
(W)
(0)
(W)
(1)
(W)
(1)
7
6
5
E23
E22
E21
9
8
LMR1 LMR0
(-)
(-)
(-)
(-)
(W)
(0)
(W)
(0)
4
3
2
1
0
E20
E19
E18
E17
E16
Bit No.
ARSR
External address output control register
Address:0000A6H
Read/write
Initial value
(W)
(0)
Bus control signal selection register
15
130
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
14
13
12
11
10
9
8
Address:0000A7H
CKE
RYE
HDE
Read/write
Initial value
(W)
(0)
(W)
(0)
(W)
(0)
IOBS HMBS WRE LMBS
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
Bit No.
HACR
Bit No.
ECSR
(-)
(-)
7.2 External Memory Access (Bus Pin Control Circuit)
7.2.2
Automatic Ready Function Selection Register (ARSR)
The automatic ready function selection register (ARSR) is used to set the automatic
wait time for memory access for each area during external access.
■ Automatic Ready Function Selection Register (ARSR)
Figure 7.2-3 Automatic Ready Function Selection Register Configuration
Automatic ready function selection register
15
Address:0000A5H
Read/write
Initial value
14
13
12
11
10
IOR1 IOR0 HMR1 HMR0
(W)
(0)
(W)
(0)
(W)
(1)
(W)
(1)
9
8
LMR1 LMR0
(-)
(-)
(-)
(-)
(W)
(0)
Bit No.
ARSR
(W)
(0)
[Bits 15 and 14] IOR1, IOR0
The IOR1 and IOR0 bits are used to specify the automatic wait function for external access
to the area from 0000C0H to 0000FFH. Table 7.2-1 "IOR1 and IOR0 (Automatic Wait
Function Specification Bit) Functions" lists the settings that can be specified by combining
the IOR1 and IOR0 bits.
Table 7.2-1 IOR1 and IOR0 (Automatic Wait Function Specification Bit) Functions
IOR1
IOR0
Function
0
0
Automatic wait disabled [initial value]
0
1
Automatic wait of 1 cycle is inserted for external access
1
0
Automatic wait of 2 cycles is inserted for external access
1
1
Automatic wait of 3 cycles is inserted for external access
[Bits 13 and 12] HMR1, HMR0
The HMR1 and HMR0 bits are used to specify the automatic wait function for external
access to the area from 800000H to FFFFFFH. Table 7.2-2 "HMR1 and HMR0 (Automatic
Wait Function Specification Bit) Functions" lists the settings that can be specified by
combining the HMR1 and HMR0 bits.
Table 7.2-2 HMR1 and HMR0 (Automatic Wait Function Specification Bit) Functions
HMR1
HMR0
Function
0
0
Automatic wait disabled
0
1
Automatic wait of 1 cycle is inserted for external access
1
0
Automatic wait of 2 cycles is inserted for external access
1
1
Automatic wait of 3 cycles is inserted for external access
[initial value]
131
CHAPTER 7 MEMORY ACCESS MODES
[Bits 9 and 8] LMR1, LMR0
The LMR1 and LMR0 bits are used to specify the automatic wait function for external access
to the areas between 002000H and 7FFFFFH. Table 7.2-3 "LMR1 and LMR0 (Automatic Wait
Function Specification Bit) Functions" lists the settings that can be specified by combining
the LMR1 and LMR0 bits.
Table 7.2-3 LMR1 and LMR0 (Automatic Wait Function Specification Bit) Functions
132
LMR1
LMR0
Function
0
0
Automatic wait disabled [initial value]
0
1
Automatic wait of 1 cycle is inserted for external access
1
0
Automatic wait of 2 cycles is inserted for external access
1
1
Automatic wait of 3 cycles is inserted for external access
7.2 External Memory Access (Bus Pin Control Circuit)
7.2.3
External Address Output Control Register (HACR)
The external address output control register (HACR) controls the external output of
addresses (A19 to A16). The bits correspond to addresses A19 to A16, which control
address output pins, as shown in Figure 7.2-4 "External Address Output Control
Address Configuration".
■ External Address Output Control Register (HACR)
Figure 7.2-4 External Address Output Control Address Configuration
External address output control register
7
6
5
4
3
2
1
0
Address:0000A6H
E23
E22
E21
E20
E19
E18
E17
E16
Read/write
Initial value
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
Bit No.
HACR
The HACR register controls output of addresses (A23 to A16) to the external circuit. The
address output pin is controlled as follows with the eight bits that correspond to address bits
A32 to A16.
The HACR register cannot be accessed when the device is in single-chip mode, since all pins
function as I/O ports whatever the value of this register.
All bits of this register are write-only bits, and the value read from the bits is 1.
Table 7.2-4 External Address Output Control Register (E16 to E32 bits) Functions
0
The corresponding pin is used for address output (AXX) [initial value].
1
The corresponding pin is used as an I/O port (PXX).
133
CHAPTER 7 MEMORY ACCESS MODES
7.2.4
Bus Control Signal Selection Register (ECSR)
The bus control signal selection register sets the bus operation control function in
external bus mode. This register cannot be accessed when the device is in single-chip
mode, since all pins function as I/O ports whatever the value of this register. All bits of
the bus control signal selection register are write-only bits, and the value from the bits
is 1.
■ Bus Control Signal Selection Register (ECSR)
Figure 7.2-5 Bus Control Signal Selection Register Configuration
Bus control signal selection register
15
14
Address:0000A7H
CKE
RYE
Read/write
Initial value
(W)
(0)
(W)
(0)
13
12
11
10
9
8
HDE IOBS HMBS WRE LMBS
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
Bit No.
ECSR
(-)
(-)
[Bit 15] CKE
The CKE bit controls output of the external clock signal pin (CLK), as shown in Table 7.2-5
"CKE (External Clock (CLK) Output Control Bit) Functions".
Table 7.2-5 CKE (External Clock (CLK) Output Control Bit) Functions
0
I/O port (P37) operation (clock output disabled) [initial value]
1
Clock signal (CLK) output enabled
[Bit 14] RYE
The RYE bit controls input of the external ready (RDY) signal pin, as shown in Table 7.2-6
"RYE (External Ready (RDY) Input Control Bit) Functions".
Table 7.2-6 RYE (External Ready (RDY) Input Control Bit) Functions
0
I/O port (P36) operation (external RDY input disabled) [initial value]
1
External ready (RDY) input enabled
[Bit 13] HDE
The HDE bit specifies that input-output of hold signals is enabled. The hold request input
signal (HRQ) and hold acknowledge output signal (HAK) are controlled according to the
setting of the HDE bit, as shown in Table 7.2-7 "HDE (Hold Signal Input-Output Enable
Specification Bit) Functions".
Table 7.2-7 HDE (Hold Signal Input-Output Enable Specification Bit) Functions
134
0
I/O port (P35, P34) operation (hold function input-output disabled) [initial value]
1
Hold request (HRQ) input/hold acknowledge (HAK) output enabled
7.2 External Memory Access (Bus Pin Control Circuit)
[Bit 12] IOBS
The IOBS bit is used to specify the bus width for external access to the area from 0000C0H
to 0000FFH in external 16-bit data bus mode Control is based on the setting of this bit, as
shown in Table 7.2-8 "IOBS (Bus Width Specification Bit)".
Table 7.2-8 IOBS (Bus Width Specification Bit)
0
16-bit bus width access [initial value]
1
8-bit bus width access
[Bit 11] HMBS
The HMBS bit is used to specify the bus width for external access to the area from 800000H
to FFFFFFH in external 16-bit data bus mode. Control is based on the setting of this bit, as
shown in Table 7.2-9 "HMBS (Bus Width Specification Bit".
Table 7.2-9 HMBS (Bus Width Specification Bit)
0
16-bit bus width access [initial value]
1
8-bit bus width access
[Bit 10] WRE
The WRE bit controls output of external write signals (both WRH and WRL pins in external
16-bit data bus mode and WR pin in external 8-bit data bus mode), as shown in Table 7.2-10
"WRE (External Write Signal Output Control Bit) Functions".
In external 8-bit data bus mode, P33 functions as the I/O port regardless of the setting value
of this bit.
Table 7.2-10 WRE (External Write Signal Output Control Bit) Functions
0
I/O port (P33, P32) operation (write signal output disabled) [initial value]
1
Write strobe signal (WRH/WRL or WR only) output enabled
135
CHAPTER 7 MEMORY ACCESS MODES
[Bit 9] LMBS
The LMBS bit is used to specify the bus width for external access to the area from 002000H
to 7FFFFFH in external 16-bit data bus mode. Control is based on the setting of this bit, as
shown in Table 7.2-11 "LMBS (Bus Width Specification Bit)".
Table 7.2-11 LMBS (Bus Width Specification Bit)
0
16-bit bus width access [initial value]
1
8-bit bus width access
Notes:
136
•
To use the WRE bit to enable the WR, WRH, and WRL functions in external 16-bit data bus
mode, place P33 and P32 in input mode (set bits 3 and 2 of the DDR3 register to 0).
•
To use the WRE bit to enable the WR function in external 8-bit data bus mode, place P32 in
input mode (set bit 2 of the DDR3 register to 0).
•
If the RYE and HDE bits are used to enable the RDY and HRQ signals, the I/O port function
of the port is also enabled. Be sure to write 0 (input mode) to the DDR3 register that
corresponds to the port.
7.3 External Memory Access Control Signal Operation
7.3
External Memory Access Control Signal Operation
If the ready function is not used, external memory is accessed in three cycles. The 8bit bus width access function is used to read and write the 8-bit width peripheral chip
when the 8- and 16-bit width peripheral chips are connected together to the external
bus.
■ External Memory Access Control Signal
The HMBS, LMBS, and IOBS bits are used to specify whether 16-bit bus width access or 8-bit
bus width access is to be used in external 16-bit data bus mode.
Actually, bus operation may not be performed by providing only address output and assert
output of the ALE signal without asserting RD, WR, WRL, and WRH. Be sure that access to a
peripheral chip using only the ALE signal is not executed.
Figure 7.3-1 Access Timing Chart for External 8-bit data bus mode)
Read
Read
Write
P37/CLK
P33/WRH
(Port data)
P32/WRL/WR
P31/RD
P30/ALE
P27 to 20/A23 to 16
Read address
Write address
Read address
P17 to 10/A15 to 08
Read address
Write address
Read address
P07 to 00/AD07 to 00
Read
address
Write
address
Read address
Read data
Write data
137
CHAPTER 7 MEMORY ACCESS MODES
Figure 7.3-2 Access Timing Chart for External 16-bit data bus mode
(At 16-bit bus width access, 8-bit bus width access)
8-bit bus width byte read
Even address byte read
8-bit bus width byte write
Even address byte write
P37/CLK
P33/WRH
P32/WRL/WR
P31/RD
P30/ALE
P27 to 20/A23 to 16
P17 to 10/AD15 to 08
Read address
P07 to 00/AD07 to 00
Read address
Read address
Write address
Read address
Invalid
(Undefined)
Write address
Read address
Write address
Write data
Read data
Odd address byte read
Read address
Odd address byte write
P37/CLK
P33/WRH
P32/WRL/WR
P31/RD
P30/ALE
P27 to 20/A23 to 16
Write address
Read address
P17 to 10/AD15 to 08
Read address
P07 to 00/AD07 to 00
Read address
Read address
Read address
Write address
Invalid
Read address
Write data
Read data
Even address word read
(Undefined)
Write address
Even address word write
P37/CLK
P33/WRH
P32/WRL/WR
P31/RD
P30/ALE
P27 to 20/A23 to16
Write address
Read address
Read address
P17 to 10/AD15 to 08
Read address
Write address
Read address
P07 to 00/AD07 to 00
Read address
Write address
Read address
Read data
Write data
Note:
Set the external circuit so that data is always read in word mode.
The setting of P36/RDY pin or the automatic ready function selection register (ARSR) enables access to
low-speed memory and peripheral circuits.
138
7.3 External Memory Access Control Signal Operation
7.3.1
Ready Function
The setting of P36/RDY pin or the automatic ready function selection register (ARSR)
enables access to the low-speed memory and peripheral circuits.
If the RYE bit of the bus control signal selection register (EPCR) is set to 1, the wait
cycle is entered to enable extension of the access cycle while the L level is input to
P36/RDY signal during access to the external circuit.
■ Ready Function
Figure 7.3-3 Timing Chart for Ready Function
Even address word read
Even address word write
P37/CLK
P33/WRH
P32/WRL/WR
P31/RD
P30/ALE
P27 to 20/A23 to 16
Read address
Write address
P17 to 10/AD15 to 08
Read address
Write address
P07 to 00/AD07 to 00
Read address
Write address
P36/RDY
RDY pin fetch
Even address word write
Read data
Write data
Even address word read
P37/CLK
P33/WRH
P32/WRL/WR
P31/RD
P30/ALE
P27 to 20/A23 to 16
Read address
Write address
P17 to 10/AD15 to 08
Write address
Read address
P07 to 00/AD07 to 00
Write address
Read address
Write data
Cycle extended by auto ready
139
CHAPTER 7 MEMORY ACCESS MODES
The MB90435 series has two types of auto ready functions for external memory access. The
auto ready function can automatically insert 1 to 3 wait cycles to extend the access cycle
without an external circuit for access to the external areas at lower addresses 002000H to
7FFFFFH and at upper addresses 800000H to FFFFFFH. This function is activated according to
the setting of the LMR1 and LMR0 bits (external areas at lower addresses) of ARSR and the
HMR1 and HMR0 bits (external area at upper addresses) of ARSR.
The MB90435 series also has an auto ready function for I/O that is independent of the auto
ready function for memory. When the IOR1 and IOR0 bits of the ARSR register are set to 0, 1
to 3 wait cycles can be automatically inserted to extend the access cycle without an external
circuit for access to the external area from addresses 0000C0H to 0000FFH.
If the RYE bit of the EPCR is set to 1 and the L level is continues to be input to P36/RDY pin
after the wait cycle using the auto ready function for external memory and for external I/O is
completed, the wait cycle continues.
140
7.3 External Memory Access Control Signal Operation
7.3.2
Hold Function
If the HDE bit in the bus control signal selection register (EPCR) is set to 1, the
external bus hold function specified by the P34/HRQ and P35/HAK pins is enabled.
■ Hold Function
If the high level is applied to the P34/HRQ pin, the hold state is set up at termination of a CPU
instruction (for a string instruction, at termination of 1-element data processing). The P35/HAK
pin outputs the low level to place the following pins in a high-impedance state:
•
Address output: P27/A23 to P20/A16
•
Address/data I/O: P17/D15 to P00/D00
•
Bus control signal: P30/ALE, P31/RD, P32/WRL/WR, P33/WRH
Thus, an external bus can be used from a device external circuit. When the low level is input to
the P34/HRQ pin, the P35/HAK pin outputs the high-level, thereby restoring the external pin
state and restarting the CPU operation. In the stop status, hold request input is not accepted.
Figure 7.3-4 "Hold Timing (in an External Bus 16-Bit Mode)" shows the hold timing (in an
external 16-bit bus mode).
Figure 7.3-4 Hold Timing (in an External Bus 16-Bit Mode)
Read cycle
Hold cycle
Write cycle
P37/CLK
P34/HRQ
P35/HAK
P33/WRH
P32/WRL/WR
P31/RD
P30/ALE
P27 to 20/A23 to 16
(Address)
(Address)
P17 to 10/AD15 to 08
(Address)
P07 to 00/AD07 to 00
(Address)
Read data
Write data
141
CHAPTER 7 MEMORY ACCESS MODES
142
CHAPTER 8
I/O PORTS
This chapter explains the functions and operations of the I/O ports.
8.1 "I/O Port"
8.2 "I/O Port Registers"
143
CHAPTER 8 I/O PORTS
8.1
I/O Ports
Each pin of the ports can be specified as input or output using the port direction
register (DDR) if the corresponding peripheral does not use the pin.
■ Outline of I/O ports
When a pin is specified as input, the logic level at the pin is read. When a pin is specified as
output, the data register value is read. The above also applies to a read operation for the readmodify-write instructions.
However, When a pin is used as an output for another peripheral, the logic level at the pin is
read regardless of the value of the data register.
It is generally recommended that the read-modify-write instructions not be used for setting the
data register before a port is set for output and the output of the peripheral resource is switched
off. The reason is that a read-modify-write instruction in this case reads the logic level at the
port instead of the register value.
Figure 8.1-1 "I/O Port Block Diagram" is a block diagram of the I/O ports.
Figure 8.1-1 I/O Port Block Diagram
Internal data bus
Data register read
Data register
Data register write
Direction register
Direction register write
Direction register read
144
Pin
8.2 I/O Port Registers
8.2
I/O Port Registers
Figure 8.2-1 "I/O Port Registers" shows the bit configuration of the I/O port registers.
■ I/O Port Registers
Figure 8.2-1 I/O Port Registers
Bit No.
15/7
14/6
13/5
12/4
11/3
10/2
9/1
8/0
Address
000000H
P07
P06
P05
P04
P03
P02
P01
P00
Port 0 data register (PDR0)
Address
000001H
P17
P16
P15
P14
P13
P12
P11
P10
Port 1 data register (PDR1)
Address
000002H
P27
P26
P25
P24
P23
P22
P21
P20
Port 2 data register (PDR2)
Address
000003H
P37
P36
P35
P34
P33
P32
P31
P30
Port 3 data register (PDR3)
Address
000004H
P47
P46
P45
P44
P43
P42
P41
P40
Port 4 data register (PDR4)
Address
000005H
P57
P56
P55
P54
P53
P52
P51
P50
Port 5 data register (PDR5)
Address
000006H
P67
P66
P65
P64
P63
P62
P61
P60
Port 6 data register (PDR6)
Address
000007H
P77
P76
P75
P74
P73
P72
P71
P70
Port 7 data register (PDR7)
Address
000008H
P87
P86
P85
P84
P83
P82
P81
P80
Port 8 data register (PDR8)
Address
000009H
P97
P96
P95
P94
P93
P92
P91
P90
Port 9 data register (PDR9)
Address
00000AH
PA0
Port A data register (PDRA)
Bit No.
15/7
14/6
13/5
12/4
11/3
10/2
9/1
8/0
Address
000010H
D07
D06
D05
D04
D03
D02
D01
D00
Port 0 direction register (DDR0)
Address
000011H
D17
D16
D15
D14
D13
D12
D11
D10
Port 1 direction register (DDR1)
Address
000012H
D27
D26
D25
D24
D23
D22
D21
D20
Port 2 direction register (DDR2)
Address
000013H
D37
D36
D35
D34
D33
D32
D31
D30
Port 3 direction register (DDR3)
Address
000014H
D47
D46
D45
D44
D43
D42
D41
D40
Port 4 direction register (DDR4)
Address
000015H
D57
D56
D55
D54
D53
D52
D51
D50
Port 5 direction register (DDR5)
Address
000016H
D67
D66
D65
D64
D63
D62
D61
D60
Port 6 direction register (DDR6)
Address
000017H
D77
D76
D75
D74
D73
D72
D71
D70
Port 7 direction register (DDR7)
Address
000018H
D87
D86
D85
D84
D83
D82
D81
D80
Port 8 direction register (DDR8)
Address
000019H
D97
D96
D95
D94
D93
D92
D91
D90
Port 9 direction register (DDR9)
Address
00001AH
DA0
Port A direction register (DDRA)
Bit No.
15/7
14/6
13/5
12/4
11/3
10/2
9/1
8/0
Address
00001CH PU07 PU06 PU05 PU04 PU03 PU02 PU01 PU00
Port 0 pull-up control register (PUCR0)
Address
00001DH PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10
Port 1 pull-up control register (PUCR1)
Address
00001EH
PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20
Port 2 pull-up control register (PUCR2)
00001FH
PU37 PU36 PU35 PU34 PU33 PU32 PU31 PU30
Port 3 pull-up control register (PUCR3)
Address
Bit No.
Address
15
14
13
12
11
10
9
8
00001BH ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
Port 6 analog input enable register (ADER)
145
CHAPTER 8 I/O PORTS
8.2.1
Port Data Register (PDR)
Figure 8.2-2 "Port Data Registers (PDR)" shows the detailed bit configuration of the
port data register (PDR).
■ Port data Register (PDR)
Figure 8.2-2 Port Data Registers (PDR)
Bit No.
PDR0
Address : 000000H
Bit No.
PDR1
Address : 000001H
Bit No.
PDR2
Address : 000002H
Bit No.
PDR3
Address : 000003H
Bit No.
PDR4
Address : 000004H
Bit No.
PDR5
Address : 000005H
Bit No.
PDR6
Address : 000006H
Bit No.
PDR7
Address : 000007H
Bit No.
PDR8
Address : 000008H
Bit No.
PDR9
Address : 000009H
Bit No.
PDRA
Address : 00000AH
7
6
5
4
3
2
1
0
Initial value
Access
P07
P06
P05
P04
P03
P02
P01
P00
Undefined
R/W
*
15
14
13
12
11
10
9
8
P17
P16
P15
P14
P13
P12
P11
P10
Undefined
R/W
*
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
Undefined
R/W
*
15
14
13
12
11
10
9
8
P37
P36
P35
P34
P33
P32
P31
P30
Undefined
R/W
*
7
6
5
4
3
2
1
0
P47
P46
P45
P44
P43
P42
P41
P40
Undefined
R/W
*
15
14
13
12
11
10
9
8
P57
P56
P55
P54
P53
P52
P51
P50
Undefined
R/W
*
7
6
5
4
3
2
1
0
P67
P66
P65
P64
P63
P62
P61
P60
Undefined
R/W
*
15
14
13
12
11
10
9
8
P77
P76
P75
P74
P73
P72
P71
P70
Undefined
R/W
*
7
6
5
4
3
2
1
0
P87
P86
P85
P84
P83
P82
P81
P80
Undefined
R/W
*
15
14
13
12
11
10
9
8
P97
P96
P95
P94
P93
P92
P91
P90
Undefined
R/W
*
7
6
5
4
3
2
1
0
Undefined
R/W
*
PA0
*: Note the following differences between R/W for the I/O ports and R/W for memory:
- Input mode
Read: The level at the corresponding pin is read.
Write: Data is written to an output latch.
- Output mode
Read: The pin output value is read.
Write: Data is written to an output latch and output to the corresponding pin.
146
8.2 I/O Port Registers
8.2.2
Port Direction Register (DDR)
Figure 8.2-3 "Port Direction Registers (DDR)" shows the bit configuration of the port
direction register (DDR).
■ Port Direction Register (DDR)
Figure 8.2-3 Port Direction Registers (DDR)
Bit No.
DDR0
Address : 000010H
Bit No.
DDR1
Address : 000011H
Bit No.
7
6
5
4
3
2
1
D07
D06
D05
D04
D03
D02
D01
15
14
13
12
11
10
D17
D16
D15
D14
D13
D12
7
6
5
4
3
2
DDR2
Address : 000012H
D27
D26
D25
D24
D23
D22
Bit No.
DDR3
Address : 000013H
15
14
13
12
11
10
D37
D36
D35
D34
D33
D32
Bit No.
DDR4
Address : 000014H
Bit No.
DDR5
Address : 000015H
Bit No.
DDR6
Address : 000016H
Bit No.
DDR7
Address : 000017H
Bit No.
DDR8
Address : 000018H
Bit No.
DDR9
Address : 000019H
Bit No.
DDRA
Address : 00001AH
7
6
5
4
3
2
D47
D46
D45
D44
D43
D42
15
14
13
12
11
10
D57
D56
D55
D54
D53
D52
7
6
5
4
3
2
D67
D66
D65
D64
D63
D62
15
14
13
12
11
10
D77
D76
D75
D74
D73
D72
7
6
5
4
3
2
D87
D86
D85
D84
D83
D82
15
14
13
12
11
10
D97
D96
D95
D94
D93
D92
7
6
5
4
3
2
9
D11
1
D21
9
D31
1
D41
9
D51
1
D61
9
D71
1
D81
9
D91
1
0
D00
Initial value
Access
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
- - - - - - - 0B
R/W
8
D10
0
D20
8
D30
0
D40
8
D50
0
D60
8
D70
0
D80
8
D90
0
DA0
When a pin functions as a port, the corresponding pin is controlled as follows:
0: Input mode
1: Output mode
The bits are set to 0 by a reset.
147
CHAPTER 8 I/O PORTS
8.2.3
Pull-up Control Register (PUCR)
Figure 8.2-4 "Bit Configuration of Pull-up Control Register (PUCR)" shows the bit
configuration of the pull-up control register (PUCR), and Figure 8.2-5 "lock Diagram of
Pull-up Control Register (PUCR)" is the block diagram.
■ Pull-up Control Register (PUCR)
Figure 8.2-4 Bit Configuration of Pull-up Control Register (PUCR)
Pull-up control register
7
5
4
3
2
1
0
Address : 00001CH
PU07 PU06 PU05 PU04 PU03 PU02 PU01 PU00
Read/write
Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
15
14
13
12
11
10
9
8
Address : 00001DH
PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10
Read/write
Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
7
6
5
4
3
2
1
0
Address : 00001EH
PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20
Read/write
Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
15
148
6
14
13
12
11
10
9
8
Address : 00001FH
PU37 PU36 PU35 PU34 PU33 PU32 PU31 PU30
Read/write
Initial value
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Bit No.
PUCR0
Bit No.
PUCR1
Bit No.
PUCR2
Bit No.
PUCR3
8.2 I/O Port Registers
■ Block Diagram of Pull-up Control Register (PUCR)
Figure 8.2-5 Block Diagram of Pull-up Control Register (PUCR)
Pull-up resistor (about 50KΩ)
Data register
Port input-output
Direction register
Resistor register
Internal data bus
Note:
In input mode, the pull-up resistor is controlled.
0: No pull-up resistor in input mode
1: Pull-up resistor in input mode
In output mode, this register has no meaning (no pull-up resistor).
The direction register (DDR) determines the input-output mode.
In hardware standby mode and stop mode (SPL=1), the state with no pull-up resistor is
entered (high impedance).
If the port is used as an external bus, this function is disabled and data is not written to the
register.
149
CHAPTER 8 I/O PORTS
8.2.4
Analog Input Enable Register (ADER)
Figure 8.2-6 "Bit Configuration of Analog Input Enable Register (ADER)" shows the bit
configuration of the analog input enable register (ADER).
■ Analog Input Enable Register (ADER)
Figure 8.2-6 Bit Configuration of Analog Input Enable Register (ADER)
Analog Input Enable Register
15
Address : 00001BH
Read/write
Initial value
14
13
12
11
10
9
8
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
Bit No.
ADER
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
The analog input enable register (ADER) controls the pins of port 6 as follows:
•
0: Port input mode
•
1: Analog input mode
If an external pin is used as analog input of the A/D converter, set the corresponding bit to 1.
150
CHAPTER 9
TIMEBASE TIMER
This chapter explains the functions and operations of the timebase timer.
9.1 "Outline of Timebase Timer"
9.2 "Timebase Timer Control Register (TBTC)"
9.3 "Operations of Timebase Timer"
151
CHAPTER 9 TIMEBASE TIMER
9.1
Outline of Timebase Timer
The timebase timer consists of an 18-bit timer and a circuit that controls an interval
interrupt. The timebase timer uses the main clock signal regardless of the MSC and
SCS bits of the clock selection register (CKSCR).
■ Timebase Timer Registers
Figure 9.1-1 Timebase Timer Registers
Time base timer control register
15
Address : 0000A9H
Read/write
Initial value
152
14
13
Reserved
(R/W)
(1)
(-)
(-)
(-)
(-)
12
11
10
9
8
Bit No.
TBIE
TBOF
TBR
TBC1
TBC0
TBTC
(R/W)
(0)
(R/W)
(0)
(R/W)
(R/W)
(0)
(R/W)
(0)
(1)
9.1 Outline of Timebase Timer
■ Block Diagram of Timebase Timer
Figure 9.1-2 Block Diagram of Timebase Timer
Main clock
TBTC
TBC1
Selector
TBC0
Clock input
212
214
216
Timebase timer
219
212 214 216 219
TBTRES
TBR
TBIE
AND
Q
TBOF
S
R
Time base
interrupt
WDTC
WT1
Selector
WT0
2-bit counter
OF
CLR
Watch-dog reset
generation circuit
CLR
Internal data bus
WTE
WDGRST
To internal reset
generation circuit
WTC
WDCS
AND
SCE
Q
SCM
Power-on reset*
Subclock stop
S
R
210
WTC2
WTC1
WTC0
WTOF
214
215
Watch timer
WTR
WTIE
213
Selector
WTRES
AND
Q
S
R
Clock input
Subclock/4
Timer
interrupt
WDTC
PONR
From power-on generation
STBR
From hardware standby
control circuit
WRST
ERST
RST pin
SRST
From RST bit of
LPMCR register
153
CHAPTER 9 TIMEBASE TIMER
9.2
Timebase Timer Control Register (TBTC)
The timebase timer control register (TBTC) controls the operation of the timebase
timer and the interval interrupt time.
■ Timebase Timer Control Register (TBTC)
Figure 9.2-1 Timebase Timer Control Register (TBTC)
Time base timer control register
15
Address : 0000A9H
Read/write
Initial value
14
13
Reserved
(R/W)
(1)
(-)
(-)
(-)
(-)
12
11
10
9
8
Bit No.
TBIE
TBOF
TBR
TBC1
TBC0
TBTC
(R/W)
(0)
(R/W)
(0)
(R/W)
(R/W)
(0)
(R/W)
(0)
(1)
[Bit 15] Reserved bit
Ensure that "1" is always written to this bit.
[Bits 14 and 13] Unused bits
Bits 14 and 13 are unused.
[bit 12] TBIE
This bit is used to enable interval interrupts based on the timebase timer. Writing "1" to this
bit enables interrupts, and writing "0" disables interrupts. This bit is initialized to "0" upon a
reset. This bit is readable and writable.
[bit 11] TBOF
This is an interrupt request flag for the timebase timer. While the TBIE bit is "1", an interrupt
request is issued when "1" is written to TBOF. This bit is set to "1" for each interval specified
with the TBC1 and TBC0 bits.
This bit is cleared by writing "0", transition to stop or hardware standby mode, or a reset.
Writing "1" has no effect.
"1" is always read by a read-modify-write instruction.
[bit 10] TBR
This bit clears all bits of the timebase timer counter to "0".
Writing "0" clears the timebase counter.
Writing "1" has no effect.
"1" is always read from this bit.
154
9.2 Timebase Timer Control Register (TBTC)
[bits 9 and 8] TBC1 and TBC0
These bits are used to set the timebase timer interval. These bits are initialized to 00 by a
reset. These bits can be read and written to.
Table 9.2-1 "Settings for Timebase Timer Interval" lists the settings for the timebase timer
interval.
Table 9.2-1 Settings for Timebase Timer Interval
TBC1
TBC0
Interval at 4 MHz source oscillation
0
0
1.024 ms
0
1
4.096 ms
1
0
16.384 ms
1
1
131.072 ms
155
CHAPTER 9 TIMEBASE TIMER
9.3
Operations of Timebase Timer
The timebase timer functions as a watch-dog timer clock source, timer for waiting for
main clock and PLL clock oscillation to stabilize, and interval timer for generating
interrupts at specified intervals.
■ Timebase Timer
The timebase timer consists of an 18-bit counter that counts the pulses of the oscillation clock
used to generate the machine clock. While the oscillation clock is input, the timebase timer
keeps counting.
The timebase timer is cleared by a power-on reset, transition to stop or hardware standby
mode, or transition from the main clock to the PLL clock by writing data to the MCS bit of the
clock selection register (CKSCR). The timebase timer is also cleared by transition from the
main clock to the subclock by writing data to the SCS bit of the clock selection register (CKSCR)
or writing 0 to the TBR bit of the timebase timer control register (TBTC).
The watch-dog counter and interval interrupt function using output from the timebase timer are
affected by clearing the timebase counter.
■ Interval Interrupt Function of Timebase Timer
Interrupts are generated at specified intervals according to the carry signals of the timebase
counter. The TBOF flag is set at the intervals specified with the TBC1 and TBC0 bits of the
timebase timer control register (TBTC). This flag is set by using as a reference the last time that
the timebase timer was cleared.
On transition from main clock mode to PLL clock mode, the timebase timer is cleared because
the timebase timer is used as a timer that waits for PLL clock oscillation to stabilize.
On transition from oscillation clock mode to subclock mode, the timebase timer is cleared
because the timebase timer is used as a timer that waits for oscillation of the oscillation clock to
stabilize.
On transition to stop mode and hardware standby mode, the TBOF flag is immediately cleared
when mode transition is complete because the timebase timer is used as a timer that waits until
oscillation to stabilize upon recovery.
156
CHAPTER 10
WATCH-DOG TIMER
This chapter explains the functions and operations of the watch-dog timer.
10.1 "Outline of Watch-dog Timer"
10.2 "Watch-dog Timer Control Register (WDTC)"
10.3 "Watch-dog Timer Operation"
157
CHAPTER 10 WATCH-DOG TIMER
10.1 Outline of Watch-dog Timer
The watch-dog timer consists of a 2-bit watch-dog counter that uses the carry signal of
the 18-bit timebase timer or 15-bit watch timer as a clock source, control register, and
watch-dog reset controller.
■ Watch-dog Timer Register
Figure 10.1-1 Watch-dog Timer Register
Watch-dog timer control register
7
Address : 0000A8H
Read/write
Initial value
158
6
5
4
3
2
PONR STBR WRST ERST SRST WTE
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(W)
(1)
1
0
Bit No.
WT1
WT0
WDTC
(W)
(1)
(W)
(1)
10.1 Outline of Watch-dog Timer
■ Watch-dog Timer Block Diagram
Figure 10.1-2 Block Diagram of Watch-dog Timer
Main clock
TBTC
TBC1
Selector
TBC0
212
Clock input
214
Timebase timer
216
219
212 214 216 219
TBTRES
TBR
TBIE
AND
Q
TBOF
S
R
Internal data bus
Time base
interrupt
WDTC
WT1
Selector
WT0
2-bit counter
OF
CLR
Watch-dog reset
generation circuit
CLR
WTE
WDGRST
To internal reset
generation circuit
WTC
WDCS
AND
SCE
Q
SCM
Power-on reset*
Subclock stop
S
R
210
WTC2
WTC1
WTC0
WTOF
214
215
Selector
Watch timer
WTR
WTIE
213
WTRES
AND
Q
S
R
Clock input
Subclock/4
Timer
interrupt
WDTC
PONR
From power-on generation
STBR
From hardware standby
control circuit
WRST
ERST
RST pin
SRST
From RST bit of
LPMCR register
159
CHAPTER 10 WATCH-DOG TIMER
10.2 Watch-dog Timer Control Register (WDTC)
The watch-dog timer control register (WDTC) consists of the bits that control the
watch-dog timer and bits that identify reset causes.
■ Watch-dog Timer Control Register (WDTC)
Figure 10.2-1 Watch-dog Timer Control Register (WDTC)
Watch-dog timer control register
7
Address : 0000A8H
Read/write
6
5
4
3
2
PONR STBR WRST ERST SRST WTE
Initial value
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(W)
(1)
1
0
Bit No.
WT1
WT0
WDTC
(W)
(1)
(W)
(1)
[bits 7 to 3] PONR, STBR, WRST, ERST, and SRST
These flags indicate the reset causes. The flags are set upon a reset as described in Table
10.2-1 "Reset Cause Bits and Reset Causes".
All bits are cleared to "0" after the WDTC register is read. These bits are read-only bits. At
power-on, the values of reset cause bits other than PONR bit are not defined. When the
PONR bit is 1, ensure that the values of the bits other than PONR bit are ignored.
Table 10.2-1 Reset Cause Bits and Reset Causes
Reset cause
PONR
STBR
WRST
ERST
SRST
Power-on
1
-
-
-
-
Hardware standby
*
1
*
*
*
Watch-dog timer
*
*
1
*
*
External pin
*
*
*
1
*
RST bit
*
*
*
*
1
(*: The previous value is maintained.)
[bit 2] WTE
While the watch-dog timer is stopped, writing 0 to this bit activates the watch-dog timer.
Subsequently, writing 0 clears the watch-dog timer counter. Writing 1 has no effect.
The watch-dog timer is stopped by power-on, hardware standby, or reset by watch-dog
timer. "1" is always read from this bit.
160
10.2 Watch-dog Timer Control Register (WDTC)
[bits 1 and 0] WT1 and WT0
These bits are used to select the watch-dog timer interval.
Only the data items written during watch-dog timer activation are valid. Data items that are
written at any other time are ignored. In the two clocks system parts, the clock signal input
to the watch-dog timer is selected according to the values of the WDCS bit of the watch timer
control register (WTC). Table 10.2-2 "Access to WT1 and WT0 (Read-only)" lists the setting
for the interval.
Table 10.2-2 Access to WT1 and WT0 (Read-only)
Interval (match clock: 4 MHz)
WDCS
WT1
WT0
Minimum
Maximum
1
0
0
About 3.58ms
About 4.61ms
1
0
1
About 14.33ms
About 18.43ms
1
1
0
About 57.23ms
About 73.73ms
1
1
1
About 458.75ms
About 589.82ms
0 *1
0
0
About 0.457s
About 0.576s
0 *1
0
1
About 3.584s
About 4.608s
0 *1
1
0
About 7.167s
About 9.216s
0 *1
1
1
About 14.336s
About 18.432s
*1: Only the two clocks system parts.
Note:
The maximum interval assumes that the timebase counter is not reset during
watch-dog operation.
161
CHAPTER 10 WATCH-DOG TIMER
10.3 Watch-dog Timer Operation
The watch-dog timer function enables detection of program surge. If 0 is not written to
the WTE bit of the watch-dog timer within the specified time due to a program surge,
the watch-dog timer issues a watch-dog reset request.
■ Activating the Watch-dog Timer
The watch-dog timer is activated by writing 0 to the WTE bit of the watch-dog timer control
register (WDTC) while the watch-dog timer is stopped. At the same time, the WT1 and WT0
bits are used to set the watch-dog timer interval. Only the interval setting specified during
activation is valid.
■ Resetting the Watch-dog Timer
When the watch-dog timer is activated, the 2-bit watch-dog counter must be program-cleared.
Specifically, 0 must be periodically written to the WTE bit of the watch-dog timer control register
(WDTC). The watch-dog timer consists of a 2-bit counter that uses the carry signals of the
timebase timer as a clock source. When the timebase timer is cleared, the watch-dog reset
interval may exceed the setting.
Figure 10.3-1 "Watch-dog Timer Operation" is a diagram of the watch-dog timer operation.
Figure 10.3-1 Watch-dog Timer Operation
Time base
Watch-dog
00
01
10
00
01
10
11
00
WTE write
Watch-dog activation
Watch-dog clear
Watch-dog reset occurs
■ Stopping the Watch-dog Counter
Once activated, the watch-dog timer is initialized and stopped only by power-on, hardware
standby, or reset by watch-dog. Reset by an external pin or software merely clears the watchdog counter without stopping the watch-dog function.
■ Clearing the Watch-dog Counter
The watch-dog counter is cleared by writing 0 to the WTE bit of the watch-dog timer control
register (WDTC), occurrence of a reset, or transition to sleep mode, stop mode, or hold
acknowledge signal.
162
CHAPTER 11
WATCH TIMER
This chapter explains the functions and operations of the watch timer.
Note:
The watch timer can not be used in the one clock system parts.
11.1 "Outline of Watch Timer"
11.2 "Watch Timer Control Register (WTC)"
11.3 "Watch Timer Operation"
163
CHAPTER 11 WATCH TIMER
11.1 Outline of Watch Timer
The watch timer consists of a 15-bit timer and a circuit that controls an interval
interrupt. The watch timer uses subclock signals regardless of the MCS bit and SCS
bit of the clock selection register (CKSCR).
■ Watch Timer Register
Figure 11.1-1 Watch Timer Control Register (WTC)
Watch timer control register
7
5
4
3
2
1
0
WDCS SCE
WTIE WTOF WTR WTC2 WTC1 WTC0
Read/write
(R/W)
(R)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(1)
(X)
Address: 0000AAH
164
6
(0)
(0)
(0)
(0)
(0)
(0)
Bit No.
WTC
11.1 Outline of Watch Timer
■ Block Diagram of Watch Timer
Figure 11.1-2 Block Diagram of Watch Timer
Main clock
TBTC
TBC1
Selector
TBC0
212
214
216
219
TBTRES
Clock input
Timebase timer
212
214
216
219
TBR
TBIE
AND
Q
S
R
TBOF
Time base
interrupt
WDTC
OF
Selector
WT0
Internal data bus
Watch-dog reset
generation circuit
2-bit counter
WT1
CLR
CLR
WDGRST
To internal reset
generation circuit
WTE
WTC
WDCS
AND
SCE
Q
SCM
Power-on reset*
Subclock stop
S
R
210
WTC2
WTC1
WTC0
Selector
WTR
WTIE
WTOF
Q
S
R
214
215
Watch timer
WTRES
AND
213
Clock input
Subclock/4
Timer
interrupt
WDTC
PONR
From power-on generation
STBR
From hardware standby
control circuit
WRST
ERST
RST pin
SRST
From RST bit of
LPMCR register
165
CHAPTER 11 WATCH TIMER
11.2 Watch Timer Control Register (WTC)
The watch timer control register (WTC) controls the operation of the watch timer and
the interval interrupt time.
■ Watch Timer Control Register (WTC)
Figure 11.2-1 Watch Timer Control Register (WTC)
Watch timer control register
7
6
5
4
3
2
1
0
WDCS SCE
WTIE WTOF WTR WTC2 WTC1 WTC0
Read/write
(R/W)
(R)
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(1)
(X)
Address: 0000AAH
(0)
(0)
(0)
(0)
(0)
Bit No.
WTC
(0)
[Bit 7] WDCS
The WDCS bit is used to specify whether the clock signal of the watch timer or timebase
timer is used as the input clock of the watch-dog timer when the main clock or PLL clock is
selected as the machine clock. When WDCS=0, the clock signal of the watch timer can be
selected. When WDCS=1, the clock signal of the timebase timer can be selected. When 1
is set in WDCS, the function that selects the main clock or PLL clock uses the timebase
timer output. Functions that include the subclock use output from the watch timer.
This bit is initialized to 1 by a power-on reset.
Note:
If WDCS is set to 1, the watch-dog timer counter may be incremented because the timebase
timer output and watch timer output are asynchronous. If WDCS is set to 1, the watch-dog
timer must be cleared before and after the clock mode is changed.
[Bit 6] SCE
The SCE bit indicates that the subclock oscillation stabilization wait time has elapsed. When
this bit is 0, the oscillation stabilization is currently in progress. The oscillation stabilization
time is fixed at 214 cycles (subclock). This bit is initialized to 0 by a power-on reset and stop.
[Bit 5] WTIE
The WTIE bit enables an interval interrupt by the watch timer. When this bit is 1, the
interrupt is enabled. When this bit is 0, the interrupt is disabled. This bit is initialized to 0 by
a reset. This bit can be read and written to.
[Bit 4] WTOF
The WTOF bit is the watch timer interrupt flag. When the WTIE bit is 1 and WTOF is set to
1, an interrupt request is issued. This bit is set to 1 at each interval specified by the WTC1
and WTC0 bits. This bit is cleared by writing 0, transition to stop mode or hardware standby
mode, or a reset. Writing 1 has no effect.
During read operation using a read-modify-write instruction, 1 is always read from this bit.
166
11.2 Watch Timer Control Register (WTC)
[Bit 3] WTR
The WTR bit clears all bits of the watch timer counter to 0. Writing 0 to this bit clears the
timer counter. Writing 1 has no effect. The value read from this bit is always 1.
[Bits 2, 1, and 0] WTC2, WTC1, WTC0
The WTC2, WTC1, and WTC0 bits set the watch timer interval. Table 11.2-1 "Settings for
the Watch Timer Interval" lists the settings for the interval. These bits are initialized to 000
by a reset. These bits can be read and written to.
When data is written to these bits, bit 4 (WTOF) should be cleared.
Table 11.2-1 Settings for the Watch Timer Interval
WTC2
WTC1
WTC0
Interval (subclock: 32kHz)
0
0
0
62.5 ms
0
0
1
125 ms
0
1
0
250 ms
0
1
1
500 ms
1
0
0
1.000 s
1
0
1
2.000 s
1
1
0
4.000 s
1
1
1
-
167
CHAPTER 11 WATCH TIMER
11.3 Watch Timer Operation
The watch timer functions as a watch-dog counter clock source, timer for waiting for
the subclock oscillation to stabilize, and interval timer for generating interrupts at
specified intervals.
■ Watch Timer
The watch timer consists of a 15-bit counter that counts oscillation inputs generated by the
subclock. While the subclock is input, the watch timer keeps counting. The watch timer is
cleared by a power-on reset or writing 0 to the WTR bit of the watch timer control register
(WTC).
The watch-dog counter and an interval interrupt using the watch timer output are affected by
clearing of the timer counter.
■ Interval Interrupt Function of Watch Timer
The interval interrupt function generates interrupts at specified intervals according to the carry
signals of the timer counter. The WTOF flag is set at the intervals specified by the WTC1 and
WTC0 bits of the watch timer control register (WTC). This flag is set by using as a reference the
last time that the watch timer was cleared.
On transition to stop or hardware standby mode, the watch timer is used as a timer for subclock
oscillation to stabilize upon recovery, and the WTOF flag is immediately cleared upon mode
transition.
168
CHAPTER 12
16-BIT I/O TIMER
This chapter explains the functions and operations of the 16-bit I/O timer.
12.1 "Outline of 16-Bit I/O Timer"
12.2 "16-Bit I/O Timer Registers"
12.3 "16-bit Free-running Timer"
12.4 "Output Compare"
12.5 "Input Capture"
169
CHAPTER 12 16-BIT I/O TIMER
12.1 Outline of 16-Bit I/O Timer
MB90435 series products contain one 16-bit free-running timer module, two output
compare modules, and four input capture modules, and support eight input channels
and four output channels. The following sections only describes the 16-bit freerunning timer, Output Compare 0/1 and Input Capture 0/1.
The remaining modules have the identical functions and the register addresses should
be found in the I/O map.
■ 16-bit Free-running Timer
The 16-bit free-run timer consists of a 16-bit up counter, control register, and prescaler. The
values output from this timer counter are used as the base timer for input capture and output
compare.
•
Four counter clocks are available.
•
Internal clock: φ/4, φ/16, φ/64, φ/256
•
An interrupt can be generated upon a counter overflow or a match with compare register 0.
•
The counter value can be initialized to "0000H" upon a reset, software clear, or match with
compare register 0.
■ Output Compare (2 Channels per One Module)
The output compare module consists of two 16-bit compare registers, compare output latch, and
control register.
When the 16-bit free-running timer value matches the compare register value, the output level is
reversed and an interrupt is issued.
❍ The two compare registers can be used independently.
Output pins and interrupt flags corresponding to compare registers
❍ Output pins can be controlled based on pairs of the two compare registers.
Output pins can be reversed by using the two compare registers.
❍ Initial values for output pins can be set.
❍ Interrupts can be generated upon a compare match.
170
12.1 Outline of 16-Bit I/O Timer
■ Input Capture (2 Channels per one Module)
The input capture module consists of two 16-bit capture registers and control registers
corresponding to two independent external input pins. The 16-bit free-running timer value can
be stored in the capture register and an interrupt is issued simultaneously upon detection of an
edge of a signal input from an external input pin.
❍ The detection edge of an external input signal can be specified.
Rising, falling, or both edges
❍ Two input channels can operate independently.
❍ An interrupt can be issued upon a valid edge of an external input signal.
The intelligent I/O service can be activated upon an input capture interrupt.
■ Block Diagram of 16-bit I/O Timer
Figure 12.1-1 "Block Diagram of 16-bit I/O Timer" shows a block diagram of the 16-bit I/O timer.
Figure 12.1-1 Block Diagram of 16-bit I/O Timer
Control logic
To each block
Interrupt
16-bit free-run timer
16-bit timer
Internal data bus
Clear
Output compare 0
Compare register 0
T
Q
OUT0
T
Q
OUT1
Edge selection
IN0
Edge selection
IN1
Output compare 1
Compare register 1
Input capture 0
Capture register 0
Input capture 1
Capture register 1
171
CHAPTER 12 16-BIT I/O TIMER
12.2 16-bit I/O Timer Registers
The 16-bit I/O timer has the following three registers:
• 16-bit free-running timer register
• 16-bit output compare register
• 16-bit input capture register
■ 16-bit I/O Timer Registers
Figure 12.2-1 16-bit I/O Timer Registers
16-bit free-running timer register
15
0
TCDT
Address : 00006CH
7
Timer counter data registers
0
Address : 00006EH
Timer counter control
status register
TCCS
16-bit output compare register
15
0
Address : 003928H
00392AH
OCCP0/1
Compare registers 0 and 1
0
15
Address : 000058H
OCS1
Compare control status
registers 0 and 1
OCS0
16-bit input capture register
0
15
Address : 003920H
003922H
Input capture data
registers 0 and 1
IPCP0/1
7
Address : 00004CH
172
0
ICS0/1
Input capture control status
registers 0 and 1
12.3 16-bit Free-running Timer
12.3 16-bit Free-running Timer
The 16-bit free-running timer consists of a 16-bit up counter and a control status
register. The count values are used as the base timer for the output compares and
input captures.
• Four counter clock frequencies are available.
• An interrupt can be generated upon a counter value overflow.
• The counter value can be initialized upon a match with compare register 0,
depending on the mode.
■ 16-bit Free-running Timer Block Diagram
Figure 12.3-1 16-bit Free-running Timer Block Diagram
Internal data bus
Interrupt request
IVF
IVFE
STOP MODE CLR
CLK1
Machine clock
φ
Divider
CLK0
(TCCS)
Comparator 0
16-bit free-running time
Clock
Count value output
T15
to
T00
173
CHAPTER 12 16-BIT I/O TIMER
12.3.1 16-bit Free-running Timer Registers
The data register can read the count value of the 16-bit free-running timer. The counter
value is cleared to "0000" upon a reset. The timer value can be set by writing a value to
this register. However, ensure that the value is written while the operation is stopped
(STOP=1).
The data register must be accessed by the word access instructions.
■ Timer Counter Data Register (TCDT)
Figure 12.3-2 Timer Counter Data Register (TCDT)
Timer counter data register (TCDT)
Address : 00006DH
Read/write
Initial value
Read/write
Initial value
14
13
12
11
10
9
8
T15
T14
T13
T12
T11
T10
T09
T08
Bit No.
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
bit
Address : 00006CH
15
7
6
5
4
3
2
1
0
T07
T06
T05
T04
T03
T02
T01
T00
Bit No.
TCDT
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
The 16-bit free-running timer is initialized upon the following factors:
174
•
Reset
•
Clear bit (CLR) of control status register
•
A match between compare register 0 and the timer counter value (Setting the mode is
required).
12.3 16-bit Free-running Timer
12.3.2 Timer Counter Control Status Register
The timer counter control status register sets the operation mode of the 16-bit freerunning timer, starts and stops the 16-bit free-running timer, and controls interrupts.
■ Timer Counter Control Status Register
Figure 12.3-3 Timer Counter Control Status Register
Timer Counter Control Status Register (TCCS)
7
6
5
4
3
2
1
Reserved
IVF
IVFE
STOP
MODE
CLR
CLK1
CLK0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Address : 00006EH
0
Bit No.
TCCS
[bit 7] Reserved bit
Always write "0" to this bit.
[bit 6] IVF
This bit is an interrupt request flag of the 16-bit free-running timer.
If the 16-bit free-running timer overflows, or if the counter is cleared by a match with
compare register 0, "1" is set to this bit.
An interrupt is issued if the interrupt request enable bit (bit 5: IVFE) is set.
This bit is cleared by writing "0". Writing "1" has no effect.
"1" is always read by a read-modify-write instruction.
0
No interrupt request (initial value)
1
Interrupt request
[bit 5] IVFE
IVFE is an interrupt enable bit of the 16-bit free-run timer. While this bit is "1", an interrupt is
issued if "1" is set to the interrupt flag (bit 5: IVF).
0
Interrupt disabled (initial value)
1
Interrupt enabled
175
CHAPTER 12 16-BIT I/O TIMER
[bit 4] STOP
The STOP bit is used to stop the 16-bit free-running timer.
Writing "1" to this bit stops the timer. Writing "0" starts the timer.
0
Counter enabled (operation) (initial value)
1
Counter disabled (stop)
Note:
The output compare operation stops when the 16-bit free-running timer stops.
[bit 3] MODE
The MODE bit is used to set the reset condition of the 16-bit free-running timer.
When "0" is set, the counter value can be initialized by RESET or a clear bit (bit 2: CLR).
When "1" is set, the counter value can be initialized by a match with compare register 0 in
addition to RESET and a clear bit (bit 2: CLR).
0
Initialization by reset or clear bit (initial value)
1
Initialization by reset, clear bit, or compare register 0
Note:
The clear bit and a match with the compare register initialize the timer when the timer value
changes.
[bit 2] CLR
The CLR bit initializes the operating 16-bit free-running timer value to "0000".
When "1" is set, the counter value is initialized to "0000". Writing "0" has no effect. "0" is
always read from this bit. The counter value is initialized when the count value changes.
0
No effect (initial value)
1
The counter value is initialized to "0000".
Note:
To initialize the counter value while the timer is stopped, write "0000" to the data register.
[bits 1 and 0] CLK1 and CLK0
CLK1 and CLK0 are used to select the count clock for the 16-bit free-run timer. The clock is
updated immediately after a value is written to these bits. Therefore, ensure that the output
compare and input capture operations are stopped before a value is written to these bits.
CLK1
CLK0
Count clock
φ=16 MHz
φ=8 MHz
φ=4 MHz
φ=2 MHz
0
0
φ/4
0.25 μs
0.5 μs
1 μs
2 μs
0
1
φ/16
1 μs
2 μs
4 μs
8 μs
1
0
φ/64
4 μs
8 μs
16 μs
32 μs
1
1
φ/256
16 μs
32 μs
64 μs
128 μs
φ = Machine clock
176
12.3 16-bit Free-running Timer
12.3.3 16-bit Free-running Timer Operation
The 16-bit free-running timer starts counting from counter value "0000" after the reset
is released. The counter value is used as the reference time for the 16-bit output
compare and 16-bit input capture operations.
■ 16-bit Free-running Timer Operation
The counter value is cleared in the following conditions:
•
When an overflow occurs.
•
When a match with the output compare register 0 occurs. (This depends on the mode.)
•
When "1" is written to the CLR bit of the TCCS register during operation.
•
When "0000" is written to the TCDT register during stop.
•
Reset
An interrupt can be generated when an overflow occurs or when the counter is cleared by a
match with the compare register 0. (Compare match interrupts can be used only in an
appropriate mode.)
Figure 12.3-4 Clearing the Counter by an Overflow
Counter value
Overflow
FFFF H
BFFF H
7FFF H
3FFF H
Time
0000 H
Reset
Interrupt
Figure 12.3-5 Clearing the Counter upon a Match with Output Compare Register 0
Counter value
FFFF H
BFFF H
Match
Match
7FFF H
3FFF H
Time
0000 H
Reset
Compare
register value
Interrupt
BFFFH
177
CHAPTER 12 16-BIT I/O TIMER
■ 16-bit Free-running Timer Timing
As shown in Figure 12.3-6 "16-bit free-running timer count timing", the 16-bit free-running timer
is incremented based on the input clock (internal or external clock). When an external clock is
selected, the 16-bit free-running timer is incremented at the rising edge.
Figure 12.3-6 16-bit free-running timer count timing
Machine clock φ
External clock
input
Count clock
N
Counter value
N+1
As shown in Figure 12.3-7 "16-bit free-running timer clear timing (match with the compare
register 0)", the counter can be cleared by a reset, software clear, or match with compare
register 0. For a reset or software clear, the counter is immediately cleared. For a match with
compare register 0, the counter is cleared synchronously with the count timing.
Figure 12.3-7 16-bit free-running timer clear timing (match with the compare register 0)
Machine clock φ
N
Compare
register value
Compare match
Counter value
178
N
0000
12.4 Output Compare
12.4 Output Compare
The output compare module consists of two 16-bit compare registers, two compare
output pins, and control register. If the value written to the compare register of this
module matches the 16-bit free-running timer value, the output level of the pin can be
reversed and an interrupt can be issued.
■ Output Compare
•
Two compare registers exist that can be used independently. Depending on the setting, the
two compare registers can be used to control pin outputs.
•
The initial value for the pin output can be specified.
•
An interrupt can be issued upon a match as a result of comparison.
■ Output Compare Block Diagram
Figure 12.4-1 Output Compare Block Diagram
16-bit timer counter value (T15 to T00)
T
Compare control
Q
OTE0
OUT0
OTE1
OUT1
Internal data bus
Compare register 0
16-bit timer counter value (T15 to T00)
CMOD
T
Compare control
Q
Compare register 1
ICP1 ICP0 ICE1 ICE0
Controller
Control blocks
Compare 1
interrupt
Compare 0
interrupt
179
CHAPTER 12 16-BIT I/O TIMER
12.4.1 Output Compare Register
These 16-bit compare registers are compared with the 16-bit free-running timer. Since
the initial register values are undefined, set appropriate value before enabling the
operation. These registers must be accessed by the word access instructions. When
the value of the register matches that of the 16-bit free-running timer, a compare signal
is generated and the output compare interrupt flag is set. If output is enabled, the
output level corresponding to the compare register is reversed.
■ Output Compare Register
Figure 12.4-2 Output Compare Register
Compare register (OCCP0 and OCCP1)
15
14
13
12
11
10
9
8
Address : 003929H
C15 C14 C13 C12 C11 C10 C09 C08
00392BH
Read/write
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X)
(X)
(X)
(X)
(X)
(X)
Initial value
(X)
Address : 003928H
00392AH
Read/write
Initial value
180
Bit No.
7
6
5
4
3
2
1
0
C07
C06
C05
C04
C03
C02
C01
C00
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X)
(X)
(X)
(X)
(X)
(X)
(X)
Bit No.
OCCP0,1
12.4 Output Compare
12.4.2 Control Status Register of Output Compare
The control status register sets the operation mode of output compare, starts and
stops output compare, controls interrupts, and sets the external output pins.
■ Control Status Register of Output Compare
Figure 12.4-3 Control Status Register
Compare control status register (0/1)
15
14
13
Address : 000059H
Read/write
Initial value
Address : 000058H
Read/write
Initial value
(-)
(-)
11
10
9
8
CMOD
OTE1
OTE0
OTD1
OTD0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(-)
(-)
(-)
(-)
Bit No.
12
7
6
5
4
ICP1
ICP0
ICE1
ICE0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
3
(-)
(-)
2
(-)
(-)
1
0
Bit No.
CST1
CST0
OCS0/1
(R/W)
(0)
(R/W)
(0)
[bits 15, 14, and 13] Unused bits
[bit 12] CMOD
CMOD is used to switch the pin output level reverse mode upon a match while pin output is
enabled (OTE1=1 or OTE0=1).
•
•
When CMOD=0 (initial value), the output level of the pin corresponding to the compare
register is reversed.
•
OUT0: The level is reversed upon a match with compare register 0.
•
OUT1: The level is reversed upon a match with compare register 1.
When CMOD=1, the output level is reversed for the compare register 0 in the same manner
as for CMOD=0. The output level of the pin corresponding to compare register 1 (OUT1),
however, is reversed upon a match with compare register 0 or 1. If compare registers 0 and
1 have the same value, the same operation as with a single compare register is performed.
•
OUT0: The level is reversed upon a match with compare register 0.
•
OUT1: The level is reversed upon a match with compare register 0 or 1.
[bits 11 and 10] OTE1 and OTE0
These bits are used to enable the output compare output pins. The initial value for these bits
is "0".
0
General-purpose port (initial value)
1
Output compare pin output
Note:
OTE1: Corresponds to output compare 1 (OUT1).
OTE0: Corresponds to output compare 0 (OUT0).
181
CHAPTER 12 16-BIT I/O TIMER
[bits 9 and 8] OTD1 and OTD0
These bits are used to change the pin output level when the output compare pin output is
enabled. The initial value of the compare pin output is "0". Ensure that the compare
operation is stopped before a value is written. When read, these bits indicate the output
compare pin output value.
0
Sets "0" for the compare pin output. (initial value)
1
Sets "1" for the compare pin output.
Note:
OTD1: Corresponds to output compare 1.
OTD0: Corresponds to output compare 0.
[bits 7 and 6] ICP1 and ICP0
These bits are used as output compare interrupt flags. "1" is set to these bits when the
compare register value matches the 16-bit free-run timer value. While the interrupt request
bits (ICE1 and ICE0) are enabled, an output compare interrupt occurs when the ICP1 and
ICP0 bits are set. These bits are cleared by writing "0".
Writing "1" has no effect. "1" is always read by a read-modify-write instruction.
0
No compare match (initial value)
1
Compare match
Note:
ICP1: Corresponds to output compare 1.
ICP0: Corresponds to output compare 0.
[bits 5 and 4] ICE1 and ICE0
These bits are used as output compare interrupt enable flags. While the "1" is written to
these bits, an output compare interrupt occurs when an interrupt flag (ICP1 or ICP0) is set.
0
Output compare interrupt disabled (initial value)
1
Output compare interrupt enabled
Note:
ICE1: Corresponds to output compare 1.
ICE0: Corresponds to output compare 0.
[bits 3 and 2] Unused bits
[bits 1 and 0] CST1 and CST0
These bits are used to enable the comparison with 16-bit free-run timer.
0
Compare operation disabled (initial value)
1
Compare operation enabled
Ensure that a value is written to the compare register before the compare operation is
enabled.
182
12.4 Output Compare
Note:
CST1: Corresponds to output compare 1.
CST0: Corresponds to output compare 0.
Since output compare is synchronized with the 16-bit free-running timer clock, stopping the
16-bit free-running timer stops compare operation.
183
CHAPTER 12 16-BIT I/O TIMER
12.4.3 16-bit Output Compare Operation
In the 16-bit output compare operation, an interrupt request flag can be set and the
output level can be reversed when the specified compare register value matches the
16-bit free-run timer value.
■ Sample of Output Waveform when Compare Registers 0 and 1 are Used (The Initial Output Value is 0.)
Figure 12.4-4 Sample of Output Waveform when Compare Registers 0 and 1 are Used
Counter value
FFFFH
BFFF H
7FFFH
3FFFH
Time
0000H
Reset
Compare register
0 value
Compare register
1 value
OUT0
BFFFH
7FFFH
OUT1
Compare 0
interrupt
Compare 1
interrupt
The output level can be changed using two compare registers (when CMOD=1).
184
12.4 Output Compare
■ Sample of a Output Waveform with Two Compare Registers (The Initial Output Value is 0.)
Figure 12.4-5 Sample of a Output Waveform with Two Compare Registers (The Initial Output Value is 0.)
Counter value
FFFFH
BFFF H
7FFFH
3FFFH
0000H
Time
Reset
BFFFH
Compare register
0 value
Compare register
1 value
OUT0
7FFFH
Corresponds to compare 0
Corresponds to
compare 0 and 1
OUT1
Compare 0
interrupt
Compare 1
interrupt
■ Output Compare Timing
In output compare operation, a compare match signal is generated when the free-running timer
value matches the specified compare register value. The output value can be reversed and an
interrupt can be issued. The output reverse timing upon a compare match is synchronized with
the counter count timing.
When the compare register is updated, comparison with the counter value is not performed.
As shown in Figure 12.4-6 "Compare operation upon update of compare register", when the
compare register is updated, comparison with the counter value is not performed.
Figure 12.4-6 Compare operation upon update of compare register
N
Counter value
N+1
N+2
N+3
No match signal is generated.
Compare register
0 value
Compare register
0 write
M
Compare register
1 value
Compare register
1 write
M
N+1
N+3
Compare 0 stop
Compare 1 stop
Figure 12.4-7 "Interrupt timing" shows the output compare interrupt timing, and Figure 12.4-8
"Output pin change timing" shows the output compare output pin change timing.
185
CHAPTER 12 16-BIT I/O TIMER
Figure 12.4-7 Interrupt timing
Machine clock φ
N
Counter value
N+1
N
Compare register
value
Compare match
Interrupt
Figure 12.4-8 Output pin change timing
Counter value
Compare register
value
Compare match
signal
Pin output
186
N
N+1
N
N
N+1
12.5 Input Capture
12.5 Input Capture
Input capture detects a rising or falling edge or both edges of an external input signal
and stores a 16-bit free-running timer value at that time in a register. In addition, input
capture can generate an interrupt upon detection of an edge. Input capture consists
of an input capture data register and a control register.
■ Input Capture
Each input capture has a corresponding external input pin.
❍ The valid edge of an external input can be selected from the following three types:
Rising edge
Falling edge
Both edges
❍ An interrupt can be generated upon detection of a valid edge of an external input.
■ Input Capture Block Diagram
Figure 12.5-1 Input Capture Block Diagram
Internal data bus
IN0
Edge detection
Capture data register 0
EG11 EG10 EG01 EG00
16-bit timer counter value (T15 to T00)
Edge detection
Capture data register 1
ICP1
ICP0
ICE1
IN1
ICE0
Interrupt
Interrupt
187
CHAPTER 12 16-BIT I/O TIMER
12.5.1 Input Capture Register Details
Input capture has the two registers listed. These registers store a value from the 16-bit
timer when a valid edge of the corresponding external pin input waveform is detected.
(The registers must be accessed in word mode. No values can be written to the
registers.)
■ Input Capture Data Register
Figure 12.5-2 Input Capture Data Register
Input capture data register 0/1
15
Address : 003919H
00391BH
Read/write
bit
Initial value
13
12
11
10
9
8
Bit No.
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08
Initial value
Address : 003918H
00391AH
Read/write
14
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
7
6
5
4
3
2
1
0
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Bit No.
IPCP0/1
■ Control Status Register
Figure 12.5-3 Input Capture Control Status Register
Input capture control status register 0/1
7
Address : 00004CH
Read/write
Initial value
6
5
4
3
2
1
0
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
Bit No.
ICS0/1
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
[bits 7 and 6] ICP1 and ICP0
These bits are used as input capture interrupt flags. "1" is set to this bit upon detection of a
valid edge of an external input pin. While the interrupt enable bits (ICE0 and ICE1) are set,
an interrupt can be generated upon detection of a valid edge.
These bits are cleared by writing "0". Writing "1" has no effect. "1" is always read by a readmodify-write instruction.
0
No valid edge detection (initial value)
1
Valid edge detection
Note:
ICP0: Corresponds to input capture 0.
ICP1: Corresponds to input capture 1.
188
12.5 Input Capture
[bits 5 and 4] ICE1 and ICE0
These bits are used to enable input capture interrupts. While these bits are "1", an input
capture interrupt is generated when the interrupt flag (ICP0 or ICP1) is set.
0
Interrupt disabled (initial value)
1
Interrupt enabled
Note:
ICE0: Corresponds to input capture 0.
ICE1: Corresponds to input capture 1.
[bits 3, 2, 1, and 0] EG11, EG10, EG01, and EG00
These bits are used to specify the valid edge polarity of the external inputs. These bits are
also used to enable input capture operation.
EG11
EG01
EG10
EG00
0
0
No edge detection (stop) (initial value)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edge detection
Edge detection polarity
Note:
EG01 and EG00: Correspond to input capture 0.
EG11 and EG10: Correspond to input capture 1.
189
CHAPTER 12 16-BIT I/O TIMER
12.5.2 16-bit Input Capture Operation
In 16-bit input capture operation, an interrupt can be generated upon detection of at
the specified edge, fetching the 16-bit free-run timer value and writing it to the capture
register.
■ Sample of Input Capture Fetch Timing
•
Capture 0: Rising edge
•
Capture 1: Falling edge
•
Capture example: Both edges
Figure 12.5-4 Sample of Input Capture Fetch Timing
Counter value
FFFF H
BFFF H
7FFF H
3FFF H
0000 H
Time
Reset
IN0
IN1
IN example
Capture 0
Capture 1
Capture
example
Capture 0
interrupt
Capture 1
interrupt
Capture
interrupt
190
Undefined
3FFFH
Undefined
Undefined
7FFFH
BFFFH
3FFFH
12.5 Input Capture
■ Input Capture Input Timing
Figure 12.5-5 Capture timing for input signals
Machine clock
φ
Counter value
Input capture
input
N
N+1
Valid edge
Capture signal
Capture register
N+1
Interrupt
191
CHAPTER 12 16-BIT I/O TIMER
192
CHAPTER 13
16-BIT RELOAD TIMER (WITH EVENT
COUNT FUNCTION)
This chapter explains the functions and operations of the 16-bit reload timer (with the
event count function).
13.1 "Outline of 16-bit Reload Timer (with Event Count Function)"
13.2 "16-bit Reload Timer (with Event Count Function)"
13.3 "Internal Clock and External Clock Operations of 16-bit Reload Timer"
13.4 "Underflow Operation of 16-bit Reload Timer"
13.5 "Output Pin Functions of 16-bit Reload Timer"
13.6 "Counter Operation State"
193
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.1 Outline of 16-Bit Reload Timer (with Event Count Function)
The 16-bit reload timer consists of a 16-bit down-counter, a 16-bit reload register, one
input pin (TIN) and one output pin (TOUT), and a control register. The input clock can
be selected from one external clock and three types of internal clock.
■ Outline of 16-bit Reload Timer (with Event Count Function)
The output pin (TOUT) outputs a toggle output waveform in reload mode and outputs a square
waveform indicating counting in one-shot mode. The input pin (TIN) is used for event input in
event count mode, and can be used for trigger input or gate input in internal clock mode.
MB90435 series products have two 16-bit reload timers.
■ Intelligent I/O Service (EI2OS) Function and Interrupts
The timer includes a circuit that supports EI2OS. The timer can activate EI2OS when an
underflow occurs. EI2OS can be used with both timers on this product.
194
13.1 Outline of 16-Bit Reload Timer (with Event Count Function)
■ Block Diagram of 16-bit Reload Timer
Figure 13.1-1 "Block Diagram of 16-bit Reload Timer" shows a block diagram of the 16-bit
reload timer.
Figure 13.1-1 Block Diagram of 16-bit Reload Timer
16
16-bit reload register
8
Reload
Internal data bus
RELD
16-bit down-counter
OUTE
UF
16
OUTL
2
INTE
OUT
CTL.
GATE
UF
IRQ
CSL1
Clock selector
CNTE
CSL0
TRG
Clear
EI 2 OSCLR
Re-trigger
2
IN CTL
Port (TIN)
EXCK
φ
φ
φ
21
23
25
Output enable
3
Prescaler
clear
Port (TOUT)
MOD2
MOD1
Machine clock
MOD0
UART baud rate (ch0)
A/DC (ch1)
3
195
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.2 16-Bit Reload Timer (with Event Count Function)
The 16-bit reload timer has the following two types of registers:
• Timer control register (TMCSR)
• 16-bit timer register (TMR)/16-bit reload register (TMRLR)
■ 16-bit Reload Timer Register
Figure 13.2-1 16-bit Reload Timer Register
Timer control status register (upper)
Address: ch0 000051H
ch1 000055H
⎫
⎬
⎭
Read/write
Initial value
15
13
12
11
10
—
—
—
CSL1
CSL0
MOD2
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(—)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
6
5
4
3
MOD0
OUTE
OUTL
RELD
INTE
UF
Read/write
Initial value
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
16-bit timer register (upper)/
16-bit reload register (upper)
Address: ch0 000053H
ch1 000057H
15
13
12
11
Bit No.
(R/W)
(0)
1
0
CNTE
(R/W)
(0)
10
Bit No.
TMCSR
TRG
(R/W)
(0)
9
8
Bit No.
⎫
⎬
⎭
Read/write
Initial value
16-bit timer register (lower)/
16-bit reload register (lower)
Address: ch0 000052H
ch1
ch1 000056
00003EHH
14
8
MOD1
2
⎫
⎬
⎭
Address: ch0 000050H
ch1 000054H
9
—
Timer control status register (lower)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
7
6
5
4
3
2
1
0
⎫
⎬
⎭
Read/write
Initial value
196
14
Bit No.
TMR/
TMRLR
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
13.2 16-Bit Reload Timer (with Event Count Function)
13.2.1 Timer Control Status Register (TMCSR)
Controls the operation mode and interrupts for the 16-bit timer. Only modify bits other
than UF, CNTE, and TRG when CNTE = "0".
■ Timer Control Status Register (TMCSR)
Figure 13.2-2 Timer Control Status Register (TMCSR)
Timer control status register (upper)
Address: ch0 000051H
ch1 000055
00003DHH
ch1
⎫
⎬
⎭
Read/write
Initial value
15
14
13
12
11
10
8
—
—
—
—
CSL1
CSL0
MOD2
MOD1
(—)
(—)
(—)
(—)
(R/W)
(R/W)
(R/W)
(R/W)
(—)
(—)
(—)
(—)
(0)
(0)
(0)
(0)
Timer control status register (lower)
7
6
5
4
3
2
⎫
⎬
⎭
MOD0
OUTE
OUTL
RELD
INTE
UF
Read/write
Initial value
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Address: ch0 000050H
ch1 000054
00003CHH
ch1
9
1
CNTE
(R/W)
(0)
Bit No.
0
TRG
Bit No.
TMCSR
(R/W)
(0)
[Bits 11, 10] CSL1, CSL0 (Clock select 1, 0)
The count clock select bits. Table 13.2-1 "Clock Sources for CSL Bit Settings" lists the
selected clock sources.
Table 13.2-1 Clock Sources for CSL Bit Settings
CSL1
CSL0
Clock Source (Machine cycle φ = 16 MHz)
0
0
φ/21 (0.125 μs)
0
1
φ/23 (0.5 μs)
1
0
φ/25 (2.0 μs)
1
1
External event count mode
197
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
[Bits 9, 8, 7] MOD2, MOD1, MOD0
These bits set the operation mode and I/O pin functions.
The MOD2 bit selects the I/O functions. When MOD2 = "0", the input pin functions as a
trigger input. In this case, the reload register contents is loaded to the counter when an
active edge is input to the input pin and count operation proceeds. When MOD2 = "1", the
timer operates in gate counter mode and the input pin functions as a gate input. In this
mode, the counter only counts while an active level is input to the input pin.
The MOD1 and 0 bits set the pin functions for each mode. Table 13.2-2 "MOD2, 1, 0 Bit
Settings (1)" and Table 13.2-3 "MOD2, 1, 0 Bit Settings (2)" list the MOD2, 1, 0 bit settings.
Table 13.2-2 MOD2, 1, 0 Bit Settings (1)
MOD2
MOD1
MOD0
Input Pin Function
Active Edge or Level
0
0
0
Trigger disabled
-
0
0
1
Trigger input
Rising edge
0
1
0
Falling edge
0
1
1
Both edges
1
×
0
1
×
1
Gate input
"L" level
"H" level
Internal clock mode (CSL0, 1 = "00", "01", or "10")
Table 13.2-3 MOD2, 1, 0 Bit Settings (2)
MOD2
MOD1
MOD0
Input Pin Function
Active Edge or Level
0
0
-
-
0
1
Trigger input
Rising edge
1
0
Falling edge
1
1
Both edges
×
•
Event counter mode (CSL0,1 = "11")
•
Bits marked as × in the table can be set to any value.
[Bit 6] OUTE
Output enable bit. The TOUT pin functions as a general-purpose port when this bit is "0" and
as the timer output pin when this bit is "1". In reload mode, the output waveform toggles. In
one-shot mode, TOUT outputs a square waveform that indicates that counting is in progress.
198
13.2 16-Bit Reload Timer (with Event Count Function)
[Bit 5] OUTL
This bit sets the output level for the TOUT pin.
Table 13.2-4 OUTE, RELD, and OUTL Settings
OUTE
RELD
OUTL
Output Waveform
0
×
×
General-purpose port
1
0
0
Output an "H" level square waveform during counting.
1
0
1
Output an "L" level square waveform during counting.
1
1
0
Toggle output. Starts with "L" level output.
1
1
1
Toggle output. Starts with "H" level output.
[Bit 4] RELD (Reload)
This bit enables reload operations. When RELD is "1", the timer operates in reload mode. In
this mode, the timer loads the reload register contents into the counter and continues
counting whenever an underflow occurs (when the counter value changes from 0000H to
FFFFH). When RELD is "0", the timer operates in one-shot mode. In this mode, the count
operation stops when an underflow occurs due to the counter value changing from 0000H to
FFFFH.
[Bit 3] INTE (Interrupt enable)
Timer interrupt request enable bit. When INTE is "1", an interrupt request is generated when
the UF bit changes to "1". When INTE is "0", no interrupt request is generated, even when
the UF bit changes to "1".
[Bit 2] UF (Underflow)
Timer interrupt request flag. UF is set to "1" when an underflow occurs (when the counter
value changes from 0000H to FFFFH). Cleared by writing "0" or by the intelligent I/O service.
Writing "1" to this bit has no meaning. Read as "1" by read-modify-write instructions.
[Bit 1] CNTE (Count enable)
Timer count enable bit. Writing "1" to CNTE sets the timer to wait for a trigger. Writing "0"
stops count operation.
[Bit 0] TRG (Trigger)
Software trigger bit. Writing "1" to TRG applies a software trigger, causing the timer to load
the reload register contents to the counter and start counting. Writing "0" has no meaning.
Reading always returns "0". Applying a trigger using this register is only valid when CNTE =
"1". Writing "1" has no effect if CNTE = "0".
199
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.2.2 Register Layout of 16-bit Timer Register (TMR)/16-bit
Reload Register (TMRLR)
TMR contents (for reading)
Reading this register reads the count value of the 16-bit timer. The initial value is
undefined. Always read this register using the word access instructions.
TMRLR contents (for writing)
The 16-bit reload register holds the initial count value. The initial value is undefined.
Always write to this register using the word access instructions.
■ 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR)
Figure 13.2-3 16-bit Timer Register (TMR)/16-bit Reload Register (TMRLR)
16-bit timer register (upper)/
16-bit reload register (upper)
Address: ch0 000053H
ch1 000057
00003FHH
ch1
15
Address: ch0 000052H
ch1 000056
00003EHH
ch1
(R/W)
(X)
12
11
10
9
Bit No.
8
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
6
5
4
3
2
1
⎫
⎬
⎭
Read/write
Initial value
200
13
⎫
⎬
⎭
Read/write
Initial value
16-bit timer register (lower)/
16-bit reload register (lower)
14
0
Bit No.
TMR/
TMRLR
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
13.3 Internal Clock and External Clock Operations of 16-bit Reload Timer
13.3 Internal Clock and External Clock Operations of 16-bit
Reload Timer
The machine clock divided by 21, 23, or 25 can be selected as the clock sources for
operating the timer from an internal divide clock. The external input pin can be
selected as either a trigger input or gate input by a register setting.
If an external clock is selected, the TIN pin functions as an external event input pin to
count the number of valid edges set in the register.
■ Internal Clock Operation of 16-bit Reload Timer
Writing "1" to both the CNTE and TRG bits in the control register enables and starts counting at
one time. Using the TRG bit as a trigger input is always available when the timer is enabled
(CNTE = "1"), regardless of the operation mode.
Figure 13.3-1 "Activation and Operation of 16-bit Reload Timer Counter" shows counter
activation and counter operation. A time period T (T: machine cycle) is required from the counter
start trigger being input until the reload register data is loaded into counter.
Figure 13.3-1 Activation and Operation of 16-bit Reload Timer Counter
Count clock
Counter
Reload data
-1
-1
-1
Data load
CNTE (bit)
TRG (bit)
T
201
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
■ Input Pin Functions of 16-bit Reload Timer (in Internal Clock Mode)
The TIN pin can be used as either a trigger input or a gate input when an internal clock is
selected as the clock source. When used as a trigger input, input of an active edge causes the
timer to load the reload register contents to the counter and then start count operation after
clearing the internal prescaler. Input a pulse width of at least 2T (T is the machine cycle) to TIN
pin.
Figure 13.3-2 "Trigger Input Operation of 16-bit Reload Timer" shows the operation of trigger
input.
Figure 13.3-2 Trigger Input Operation of 16-bit Reload Timer
Count clock
Rising edge detected
TIN pin
Prescaler clear
Counter
0000H
Reload data
-1
-1
-1
Load
2T2.5T
When used as a gate input, the counter only counts while the active level specified by the
MOD0 bit of the control register is input to the TIN pin. In this case, the count clock continues to
operate unless stopped. The software trigger can be used in gate mode, regardless of the gate
level. Input a pulse width of at least 2T (T is the machine cycle) to the TIN pin. Figure 13.3-3
"Gate Input Operation of 16-bit Reload Timer" shows the operation of gate input.
Figure 13.3-3 Gate Input Operation of 16-bit Reload Timer
Count clock
When MOD0 = "1" (Count when "H" is input)
TIN pin
-1
Counter
-1
-1
■ External Event Counter
The TIN pin functions as an external event input pin when an external clock is selected. The
counter counts on the active edge specified in the register. Input a pulse width of at least 4T (T
is the machine cycle) to the TIN pin.
202
13.4 Underflow Operation of 16-bit Reload Timer
13.4 Underflow Operation of 16-bit Reload Timer
An underflow is defined for this timer as the time when the counter value changes
from 0000H to FFFFH. Therefore, an underflow occurs after (reload register setting + 1)
counts.
■ Underflow Operation of 16-bit Reload Timer
If the RELD bit in the control register is "1" when the underflow occurs, the contents of the
reload register is loaded into the counter and counting continues. When RELD is "0", counting
stops with the counter at FFFFH.
The UF bit in the control register is set when the underflow occurs. If the INTE bit is "1" at this
time, an interrupt request is generated.
Figure 13.4-1 "Underflow Operation of 16-bit Reload Timer [RELD=1]" and Figure 13.4-2
"Underflow Operation of 16-bit Reload Timer [RELD=0]" show the operation when an underflow
occurs.
Figure 13.4-1 Underflow Operation of 16-bit Reload Timer [RELD=1]
Count clock
Counter
0000H
Reload data
-1
-1
-1
Data load
Underflow set
Figure 13.4-2 Underflow Operation of 16-bit Reload Timer [RELD=0]
Count clock
Counter
0000H
FFFFH
Underflow set
203
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
13.5 Output Pin Functions of 16-bit Reload Timer
In reload mode, the TOUT pin performs toggle output (inverts at each underflow). In
one-shot mode, the TOUT pin functions as a pulse output that outputs a particular
level while the count is in progress.
■ Output Pin Functions of 16-bit Reload Timer
The OUTL bit of the control register sets the output polarity. When OUTL = "0", the initial value
for toggle output is "0" and the one-shot pulse output is "1" while the count is in progress. The
output waveforms are opposite when OUTL = "1".
Figure 13.5-1 "Output Pin Function of 16-bit Reload Timer (RELD=1, OUTL=0)"
and Figure 13.5-2 "Output Pin Function of 16-bit Reload Timer (RELD=0, OUTL=0)" show the
output pin functions.
Figure 13.5-1 Output Pin Function of 16-bit Reload Timer (RELD=1, OUTL=0)
Count start
Underflow
Level is opposite
when OUTL = "1".
TOUT
General-purpose port
CNTE
Trigger
Figure 13.5-2 Output Pin Function of 16-bit Reload Timer (RELD=0, OUTL=0)
Underflow
TOUT
Level is opposite
when OUTL = "1".
General-purpose port
CNTE
Trigger
Waiting for a trigger
[RELD=0, OUTL=0]
204
13.6 Counter Operation State
13.6 Counter Operation State
The counter state is determined by the CNTE bit in the control register and the internal
WAIT signal. Available states are: CNTE = "0" and WAIT = "1" (STOP state), CNTE = "1"
and WAIT = "1" (WAIT state for trigger), and CNTE = "1" and WAIT = "0" (RUN state).
■ Counter Operation State
Figure 13.6-1 "Counter State Transitions" shows the transitions between each state.
Figure 13.6-1 Counter State Transitions
Reset
State transitions by hardware
STOP
CNTE=0, WAIT=1
State transitions by register access
TOUT pin: Input disabled
TOUT pin: General-purpose port
Counter: Retains the value while
counting stopped.
Value undefined after reset.
CNTE='0'
CNTE='0'
CNTE='1'
TRG='1'
CNTE='1'
TRG='0'
WAIT
RUN
CNTE=1, WAIT=1
CNTE=1, WAIT=0
TIN pin: Only trigger input enabled
TIN pin: Functions as TIN pin
TOUT pin: Initial value output
TOUT pin: Functions as TOUT pin
Counter: Retains the value while
counting stopped.
Value undefined after reset until
load.
Counter: Running
RELD·UF
TRG='1'
TRG='1'
RELD·UF
LOAD
CNTE=1, WAIT= 0
Load complete
Load contents of the reload
register to the counter.
205
CHAPTER 13 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
206
CHAPTER 14
8/16-BIT PPG
This chapter explains the functions and operation of the 8/16-bit PPG.
14.1 "Outline of 8/16-bit PPG"
14.2 "Block Diagram of 8/16-bit PPG"
14.3 "8/16-bit PPG Registers"
14.4 "Operations of 8/16-bit PPG"
14.5 "Selecting a Count Clock for 8/16-bit PPG"
14.6 "Controlling Pin Output of 8/16-bit PPG Pulses"
14.7 "8/16-bit PPG Interrupts"
14.8 "Initial Values of 8/16-bit PPG Hardware"
207
CHAPTER 14 8/16-BIT PPG
14.1 Outline of 8/16-bit PPG
The 8/16-bit PPG consists of two eight-bit down counters, four eight-bit reload
registers, one 16-bit control register, two external pulse output signals, and two
interrupt outputs. The following functions are implemented:
■ Function of 8/16-bit PPG
❍ 8-bit PPG output, 2-channel independent operation mode:
Two independent channels of PPG output operation are implemented.
❍ 16-bit PPG output operation mode:
One channel of 16-bit PPG output operation is implemented.
❍ 8+8-bit PPG output operation mode:
8-bit PPG output operation is implemented at specifies intervals, using channel 0 output as
channel 1 clock input.
❍ PPG output operation:
Pulse waves are output at specified intervals and duty ratio. With an external circuit, this module
can be used as a D/A converter.
The MB90435 series contains four PPG’s. The following sections only describe the functionality
of the PPG0/1. The remaining PPG’s have the identical function and the register address
should be found in the APPENDIX A "I/O maps". The channel 0 PPG output signal is not
connected to any external pin.
208
14.2 Block Diagram of 8/16-bit PPG
14.2 Block Diagram of 8/16-bit PPG
Figure 14.2-1 "8-bit PPG ch0 Block Diagram" shows a block diagram of the 8/16-bit
PPG (ch0). Figure 14.2-2 "8-bit PPG ch1 Block Diagram" shows a block diagram of the
8/16-bit PPG (ch1).
■ Block Diagram of 8/16-bit PPG
Figure 14.2-1 8-bit PPG ch0 Block Diagram
PPG00 output enable
PPG00
Peripheral clock 16-division
Peripheral clock 8-division
Peripheral clock 4-division
Peripheral clock 2-division
Peripheral clock
In MB90435 series, this signal is not
connected to any external pin.
PPG0
Output latch
Invert
Clear
PEN0
Count clock
selection
Time base counter output
512-division of main clock
L/H selection
S
RQ
PCNT
(down counter)
In MB90435 series, this IRQ signal
merged with the Channel 1 IRQ signal
by OR logic.
IRQ
Reload
ch1-borrow
L/H selector
PRLL0
PRLBH0
PIE0
PRLH0
PUF0
L data bus
H data bus
PPGC0
(Operation mode control)
209
CHAPTER 14 8/16-BIT PPG
Figure 14.2-2 8-bit PPG ch1 Block Diagram
PPG10 output enable
PPG10
Peripheral clock 16-division
Peripheral clock 8-division
Peripheral clock 4-division
Peripheral clock 2-division
Peripheral clock
In MB90435 series this pin is connected to
the "PPG0" external pin.
PPG1
Output latch
Invert
Count clock
selection
Clear
PEN1
In MB90435 series, this IRQ signal
merged with the Channel 0 IRQ signal
by OR logic.
ch0 borrow
Time base counter output
512-division of main clock
L/H selection
S
RQ
PCNT
(down counter)
IRQ
Reload
L/H selector
PRLL1
PRLBH1
PIE
PRLH1
PUF
L data bus
H data bus
PPGC1
(Operation mode control)
Figure 14.2-3 Relationship between PPG Modules and External pins
PPG 0/1
PPG0
PPG 2/3
PPG1
PPG 4/5
PPG2
PPG 6/7
PPG3
External pin
210
14.3 8/16-bit PPG Registers
14.3 8/16-bit PPG Registers
The 8/16-bit PPG has the following five types of registers:
• PPG0 operation mode control register
• PPG1 operation mode control register
• PPG0 and PPG1 clock selection register
• Reload register H
• Reload register L
■ 8/16-bit PPG Registers
Figure 14.3-1 8/16 bit PPG Registers
PPG0 operation mode control register
7
Address: ch0 000038H
6
5
PEN0
4
PE00
3
PIE0
2
1
0
Bit No.
Reserved
PUF0
PPGC0
Read/write
Initial value
(R/W)
(0)
PPG1 operation mode control register
15
Address: ch0 000039H
PEN1
Read/write
Initial value
PPG0/1 clock selection register
(-)
(-)
14
(R/W) (R/W) (R/W)
(0)
(0)
(0)
(-)
(-)
(-)
(-)
(W)
(1)
Bit No.
13
12
11
10
9
8
PE10
PIE1
PUF1
MD1
MD0
Reserved
PPGC1
(R/W)
(0)
(-)
(-)
7
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
6
5
4
3
2
(W)
(1)
1
0
Bit No.
Address: ch0, 1 003AH
PCS2
Read/write
Initial value
PCS1 PCS0 PCM2 PCM1 PCM0
PPG0/1
(R/W)
(0)
(R/W)
(0)
1 5
(R/W) (R/W)
(0)
(0)
14
13
(-)
(-)
(R/W) (R/W)
(0)
(0)
12
11
(-)
(-)
10
9
8
Reload register H
Address: ch0 003901H
ch1 003903H
Read/write
Initial value
PRLH0/1
(R/W) (R/W) (R/W) (R/W) (R/W)
(X) (X)
(X)
(X)
(X)
7
6
5
4
(R/W) (R/W)
(X)
(X)
3
2
(R/W)
(X)
1
Reload register L
Address: ch0 003900H
ch1 003902H
Read/write
Initial value
Bit No.
0
Bit No.
PRLL0/1
(R/W) (R/W)
(X) (X)
(R/W) (R/W) (R/W)
(X)
(X)
(X)
(R/W) (R/W)
(X)
(X)
(R/W)
(X)
211
CHAPTER 14 8/16-BIT PPG
14.3.1 PPG0 Operation Mode Control Register (PPGC0)
The operation mode control register (PPGC0) is a 5-bit control register that selects the
operation mode of the block, controls pin outputs, selects a count clock, and controls
triggers.
■ PPG0 Operation Mode Control Register (PPGC0)
Figure 14.3-2 PPG0 Operation Mode Control Register (PPGC0)
PPG0 operation mode control register
7
Address: ch0, 000038H
PEN0
Read/write
Initial value
(R/W)
(0)
6
(-)
(-)
5
4
3
2
1
PE00
PIE0
PUF0
-
-
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(-)
(-)
(-)
(-)
[bit 7] PEN0 (PPG enable): Operation enable bit
This bit enables PPG count operation.
PEN0
Operation
0
Stop ("L" level output maintained)
1
PPG operation enabled
Setting this bit to "1" enables the counter operation.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit 5] PE00 (PPG output enable 00): PPG00 pin output enable bit
This bit controls the PPG00 pulse output external pin as described below.
PE00
Operation
0
General-purpose port pin (pulse output disabled)
1
PPG00 = pulse output pin (pulse output enabled)
This bit is initialized to "0" upon a reset. This bit is readable and writable.
For the MB90435 series, this bit should always be set to "0".
212
0
Reserved
(W)
(1)
Bit No.
PPGC0
14.3 8/16-bit PPG Registers
[bit 4] PIE0 (PPG interrupt enable): PPG interrupt enable bit
This bit controls PPG interrupt as described below.
PIE0
Operation
0
Interrupt disabled
1
Interrupt enabled
While this bit is "1", an interrupt request is issued as soon as PUF0 is set to "1". No interrupt
request is issued while this bit is set to "0".
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit 3] PUF0 (PPG underflow flag): PPG counter underflow bit
This bit indicates the PPG counter underflow as described below.
PUF0
Operation
0
PPG counter underflow is not detected.
1
PPG counter underflow is detected.
In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" when
an underflow occurs as a result of the ch0 counter value becoming from 00H to FFH. In 16-bit
PPG mode, this bit is set to "1" when an underflow occurs as a result of the Channel 0 and 1
counter value becoming from 0000H to FFFFH. To set this bit to "0", write "0". Writing "1" to
this bit has not effect. Upon a read operation during a read-modify-write instruction, "1" is
read.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit 0]
This is a reserved bit. When setting PPGC0, always set this bit to "1".
The value read from this bit is always "1".
213
CHAPTER 14 8/16-BIT PPG
14.3.2 PPG1 Operation Mode Control Register (PPGC1)
The PPG1 operation mode control register (PPGC1) is a 7-bit control register that
selects the operation mode of the block, controls pin outputs, selects a count clock,
and controls triggers.
■ PPG1 Operation Mode Control Register (PPGC1)
Figure 14.3-3 PPG1 Operation Mode Control Register (PPGC1)
PPG1 operation mode control register
1 5
Address: ch1 000039H
PEN1
Read/write
Initial value
(R/W)
(0)
1 4
(-)
(-)
1 3
1 2
PE10
PIE1
(R/W)
(0)
(R/W)
(0)
1 1
1 0
9
PUF1
MD1
MD0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
8
Reserved
(W)
(1)
[bit 15] PEN1 (PPG enable): Operation enable bit
This bit enables the counter operation of the PPG.
PEN1
Operation
0
Stop ("L" level output maintained)
1
PPG operation enabled
Setting this bit to "1" enables the counter operation.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit 13] PE10 (PPG output enable 10): PPG10 pin output enable bit
This bit controls the PPG10 pulse output external pin as described below.
PE10
Operation
0
General-purpose port pin (pulse output disabled)
1
PPG10 = pulse output pin (pulse output enabled)
This bit is initialized to "0" upon a reset. This bit is readable and writable.
For the MB90435 series, the pulse signal is output to the "PPG0" external pin.
214
Bit No.
PPGC1
14.3 8/16-bit PPG Registers
[bit 12] PIE1 (PPG interrupt enable): PPG interrupt enable bit
This bit controls PPG interrupt as described below.
PIE1
Operation
0
Interrupt disabled
1
Interrupt enabled
While this bit is "1", an interrupt request is issued as soon as PUF1 is set to "1". No interrupt
request is issued while this bit is set to "0".
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit 11] PUF1 (PPG underflow flag): PPG counter underflow bit
This bit indicates the PPG counter underflow as described below.
PUF1
Operation
0
PPG counter underflow is not detected.
1
PPG counter underflow is detected.
In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" when
an underflow occurs as a result of the Channel 1 counter value becoming from 00H to FFH.
In 16-bit PPG mode, this bit is set to "1" when an underflow occurs as a result of the Channel
0 and 1 counter value becoming from 0000H to FFFFH. To set this bit to "0", write "0". Writing
"1" to this bit has not effect. Upon a read operation during a read-modify-write instruction, "1"
is read.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit 10, 9] MD1, 0 (PPG count mode): Operation mode selection bit
These bits selects the PPG timer operation mode as described below.
MD1
MD0
Operation mode
0
0
8-bit PPG 2ch independent mode
0
1
8-bit prescaler + 8-bit PPG 1ch mode
1
0
Reserved (setting prohibited)
1
1
16-bit PPG 1ch mode
These bits are initialized to "00" upon a reset. These bits are readable and writable.
Note:
Do not set "10" in these bits.
To write "01" to these bits, ensure that "01" is not written to the PEN0 bit of PPGC0 or PEN1
bit of PPGC1. Write "11" or "00" in both the PEN0 and PEN1 bits simultaneously.
To write "11" to these bits, update PPGC0 and PPGC1 by word transfer and write "11" or
"00" to both the PEN0 and PEN1 bits simultaneously.
215
CHAPTER 14 8/16-BIT PPG
[bit 8] This is a reserved bit.
When setting PPGC1, always write "1" to this bit.
The value read from this bit is always "1".
216
14.3 8/16-bit PPG Registers
14.3.3 PPG0, 1 Clock Selection Register (PPG0/1)
The PPG0/1 clock selection register (PPG0/1) is an 8-bit control register that controls
the PPG operation clock.
■ PPG0, 1 Clock Selection Register (PPG0/1)
Figure 14.3-4 PPG0, 1 Clock Selection Register (PPG0/1)
PPG0, 1 Clock Selection register
Address: ch0, 1 003AH
Read/write
Initial value
7
6
5
4
PCS2
PCS1
PCS0
PCM2
PCM1
PCM0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
3
2
1
0
Bit No.
PPG01
(-)
(-)
(-)
(-)
[bits 7 to 5] PCS2 to 0 (PPG count select): Count clock selection bit
These bits select the operation clock for the down counter of Channel 1 as described below.
PCS2
PCS1
PCS0
Operation mode
0
0
0
Peripheral clock (62.5 ns machine clock, 16 MHz)
0
0
1
Peripheral clock/2 (125 ns machine clock, 16 MHz)
0
1
0
Peripheral clock/4 (250 ns machine clock, 16 MHz)
0
1
1
Peripheral clock/8 (500 ns machine clock, 16 MHz)
1
0
0
Peripheral clock/16 (1 μs machine clock, 16 MHz)
1
0
1
Clock input from the timebase timer (128 μs, 4 MHz source
oscillation)
These bits are initialized to "000" upon a reset. These bits are readable and writable.
Note:
In 8-bit prescaler + 8-bit PPG mode or in 16-bit PPG mode, ch1 PPG operates in response
to a counter clock from ch0. Therefore, the setting in these bits has no effect.
217
CHAPTER 14 8/16-BIT PPG
[bits 4 to 2] PCM2 to 0 (PPG count mode): Count clock selection bit
These bits select the operation clock for the down counter of Channel 0 as described below.
PCM2
PCM1
PCM0
Operation mode
0
0
0
Peripheral clock (62.5 ns machine clock, 16 MHz)
0
0
1
Peripheral clock/2 (125 ns machine clock, 16 MHz)
0
1
0
Peripheral clock/4 (250 ns machine clock, 16 MHz)
0
1
1
Peripheral clock/8 (500 ns machine clock, 16 MHz)
1
0
0
Peripheral clock/16 (1 μs machine clock, 16 MHz)
1
0
1
Clock input from the timebase timer (128 μs, 4 MHz
source oscillation)
These bits are initialized to "000" upon a reset. These bits are readable and writable.
218
14.3 8/16-bit PPG Registers
14.3.4 Reload Register (PRLL/PRLH)
The reload registers (PRLL and PRLH) are 8-bit registers that store reload values for
the PCNT down counters. The PRLL and PRLH registers are readable and writable.
■ Reload Register (PRLL/PRLH)
Figure 14.3-5 Reload Register (PRLL/PRLH)
15
14
13
12
11
10
9
8
Reload register H
Address: ch0 003901H
ch1 003903H
Read/write
Initial value
Bit No.
PRLH0/1
(R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
7
6
5
4
(R/W) (R/W)
(X)
(X)
3
2
(R/W)
(X)
1
Reload register L
Address: ch0 003900H
ch1 003902H
0
Bit No.
PRLL0/1
(R/W) (R/W)
(X) (X)
(R/W) (R/W) (R/W)
(X)
(X)
(X)
(R/W) (R/W)
(X)
(X)
Register name
(R/W)
(X)
Function
PRLL
Holds the L side reload value.
PRLH
Holds the H side reload value.
Note:
In 8-bit prescaler + 8-bit PPG mode, different values in PRLL and PRLH of Channel 0 may
cause the PPG waveform of ch1 to vary in each cycle. Write the same value to PRLL and
PRLH of ch0.
219
CHAPTER 14 8/16-BIT PPG
14.4 Operations of 8/16-bit PPG
One 8/16-bit PPG consists of two channels of 8-bit PPG units. These two channels can
be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG
mode, and single-channel 16-bit PPG mode.
■ Operations of 8/16-bit PPG
Each of the 8-bit PPG units has two eight-bit reload registers. One reload register is for the L
pulse width (PRLL) and the other is for the H pulse width (PRLH). The values stored in these
registers are reloaded into the 8-bit down counter (PCNT), from the PRLL and PRLH in turn.
The pin output value is inverted upon a reload caused by counter borrow. This operation results
in the pulses of the specified L pulse width and H pulse width.
Table 14.4-1 "Reload Operation and Pulse Output" lists the relationship between the reload
operation and pulse outputs.
Table 14.4-1 Reload Operation and Pulse Output
Reload operation
Pin output change
PRLH --> PCNT
PPG0/1 [0 --> 1]
Rise
PRLL --> PCNT
PPP0/1 [1 --> 0]
Fall
When "1" is set in bit 4 (PIE0) of PPGC0 or in bit 12 (PIE1) of PPGC1, an interrupt request is
output upon a borrow from 00H to FFH (from 0000H to FFFFH in 16-bit PPG mode) of each
counter.
■ Operation Modes of 8/16-bit PPG
This block can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit
PPG mode, and single-channel 16-bit PPG mode.
❍ Independent two-channel mode
The two channels of 8-bit PPG units operate independently. The PPG00 pin is connected to the
ch0 PPG output, while the PPG10 pin is connected to the ch1 PPG output.
❍ 8-bit prescaler + 8-bit PPG mode
ch0 is used as an 8-bit prescaler while the count in ch1 is based on borrow outputs from ch0.
Thus, 8-bit PPG waveforms can be output with arbitrary length of cycle time. The PPG00 pin is
connected to the ch0 prescaler output, while the PPG10 pin is connected to the ch1 PPG
output.
220
14.4 Operations of 8/16-bit PPG
❍ 16-bit PPG 1ch mode
ch0 and ch1 are connected and used as a single 16-bit PPG. The PPG00 and PPG10 pins are
connected to the 16-bit PPG output.
For the MB90435 series, the output signal from the Channel 0 PPG is not connected to any
external pin.
■ 8/16-bit PPG Output Operation
The 8/16-bit channel 0 PPG is activated by setting bit 7 (PEN0) of the PPGC0 (PWM operation
mode control) register to "1". The 8/16-bit channel 1 PPG is activated by setting bit 15 (PEN1)
of the PPGC1 register to "1". After operation is started, counting is stopped by writing "0" to bit
7 (PEN0) of PPGC0 or bit 15 (PEN1) of PPGC1. After counting is stopped, the pulse output is
maintained at the L level. In the MB90435 series, the output signal from the channel 0 PPG is
not connected to any external pin.
In 8-bit prescaler + 8-bit PPG mode, do not set ch1 to be in operation while ch0 operation is
stopped.
In 16-bit PPG mode, ensure that bit 7 (PEN0) of PPGC0 register and bit 15 (PEN1) of PPGC1
register are started or stopped simultaneously. The figure below is a diagram of PPG output
operation. During PPG operation, a pulse wave is continuously output at a frequency and duty
ratio (the ratio of the H-level period of the pulse wave to the L-level period). PPG continues
operation until stop is specified explicitly.
Figure 14.4-1 PPG Output Operation, Output Waveform
PEN
Starts operation based on PEN (from Lside).
Output pin
PPG
T
(L+1)
T
(Start)
(H+1)
L : PRLL value
H : PRLH value
T : Input from peripheral clock (
or timer base counter (depending on the
clock selection by PPGC)
■ Relationship Between 8/16-bit PPG Reload Value and Pulse Width
The width of the output pulse is determined by adding 1 to the reload register value and
multiplying it by the count clock cycle. Note that when the reload register value is 00H during 8bit PPG operation or 0000H during 16-bit PPG operation, the pulse width is equivalent to one
count clock cycle. In addition, note that when the reload register value is FFH during 8-PPG
operation, the pulse width is equivalent to 256 count clock cycles. When the reload register
value is FFFFH during 16-bit PPG operation, the pulse width is equivalent to 65536 count clock
cycles. The following is an example of calculating the pulse width:
P1=T
Ph=T
(L+1)
(H+1)
L : PRLL value
H : PRLH value
T : Input clock cycle
Ph: High pulse width
Pl : Low pulse width
221
CHAPTER 14 8/16-BIT PPG
14.5 Selecting a Count Clock for 8/16-bit PPG
The count clock used for the operation is supplied from the peripheral clock or the
timebase timer. The count clock can be selected from six choices.
■ Selecting a Count Clock for 8/16-bit PPG
Select ch0 clock at bit 4 to 2 (PCM2 to 0) of the PPG01 register, and ch1 clock at bit 7 to 5
(PCS2 to 0) of the PPG01 register.
The clock is selected from a peripheral clock 1/16 to 1 times higher than a machine clock or an
input clock from the timebase timer.
In 8-bit prescaler + 8-bit PPG mode or 16-bit PPG mode, however, the setting in the PCS2 to 0
has no effect.
When the timebase timer input is used, the first count cycle after a trigger or a stop may be
shifted. The cycle may also be shifted if the timebase counter is cleared during operation of this
module.
In 8-bit prescaler + 8-bit PPG mode, if ch1 is activated while ch0 is in operation and ch1 is
stopped, the first count cycle may be shifted.
222
14.6 Controlling Pin Output of 8/16-bit PPG Pulses
14.6 Controlling Pin Output of 8/16-bit PPG Pulses
The pulses generated by this module can be output from external pins PPG00 and
PPG10.
■ Controlling Pin Output of 8/16-bit PPG Pulses
To output the pulses from an external pin, write "1" to the bit corresponding to each pin. When
"0" is written to these bits (default), the pulses are not output from the corresponding external
pins; the pins work as general-purpose ports.
In 16-bit PPG mode, the same waveform is output from PPG00 and PPG10. Thus, the same
output can be obtained by enabling both external pin.
In 8-bit prescaler + 8-bit PPG mode, the 8-bit prescaler toggle output waveform is output from
PPG00, while the 8-bit PPG waveform is output from PPG10. Figure 14.6-1 "8+8 PPG Output
Operation Waveform" is a diagram of output waveforms in this mode.
For the MB90435 series, the output signal from the Channel 0 PPG is not connected to any
external pin.
Figure 14.6-1 8+8 PPG Output Operation Waveform
Ph0
Pl0
PPG0
PPG1
Ph1
Pl0 = T
Pl1
(L0+1)
Ph0 = T
(L0+1)
Pl1 = T
(L0+1)
(Ll+1)
Ph1 = T
(L0+1)
(Hl+1)
L0 :ch0 PRLL value and ch0 PRLH value
L1 :ch1 PRLL value
H1 :ch1 PRLH value
T : Input clock cycle
Ph0 :PPG00 high pulse width
Pl0 :PPG00 low pulse width
Ph1 :PPG10 high pulse width
Pl1 :PPG10 low pulse width
Note:
Set the same value in ch0 PRLL and ch0 PRLH.
223
CHAPTER 14 8/16-BIT PPG
14.7 8/16-bit PPG Interrupts
For the 8/16-bit PPG, an interrupt becomes active when the reload value counts out
and a borrow occurs.
■ 8/16-bit PPG Interrupts
In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, an interrupt is requested by a
borrow in each counter. In 16-bit PPG mode, PUF0 and PUF1 are simultaneously set by a
borrow in the 16-bit counter. Therefore, enable only PIE0 or PIE1 to unify the interrupt causes.
In addition, simultaneously clear the interrupt flags for PUF0 and PUF1.
224
14.8 Initial Values of 8/16-bit PPG Hardware
14.8 Initial Values of 8/16-bit PPG Hardware
The hardware components of this block are initialized to the following values when
reset:
■ Initial Values of 8/16-bit PPG Hardware
❍ <Registers>
•
PPGC0 --> 0X000001B
•
PPGC1 --> 00000001B
•
PPG10 --> XXXXXX00B
❍ <Pulse outputs>
•
PPG00 --> "L"
•
PPG10 --> "L"
•
PE00
-->
PPG00 output disabled
•
PE10
-->
PPG10 output disabled
❍ <Interrupt requests>
•
IRQ0 --> "L"
•
IRQ1 --> "L"
Hardware components other than the above are not initialized.
Note:
Write timing for 8/16-bit PPG reload registers (PRLL and PRLH)
In a mode other than 16-bit PPG mode, it is recommended to use a word transfer instruction
to write data in reload registers PRLL and PRLH. If two byte transfer instructions are used to
write a data item to these registers, a pulse of unexpected cycle time may be output
depending on the timing.
Figure 14.8-1 Write Timing for 8/16-bit PPG Reload Registers (PRLL and PRLH)
PPG0
B
A
B
C
A
B
C
C
D
D
c
Assume that PRLL is updated from A to C before point 1 in the time chart above, and PRLH is
updated from B to D after point 1. Since the PRL values at point 1 are PRLL = C and PRLH = B,
a pulse of L side count value C and H side count value B is output only once.
Similarly, to write data in PRL of ch0 and ch1 in 16-bit PPG mode, use a long word transfer
instruction, or use word transfer instructions in the order of ch0 and then ch1. In this mode, the
data is only temporarily written to ch0 PRL. Then, the data is actually written into ch0 PRL when
the ch1 PRL is written to.
225
CHAPTER 14 8/16-BIT PPG
As shown in Figure 14.8-2 "PRL Write Operation Block Diagram" in a mode other than 16-bit
PPG mode, channel 0 PRL and channel 1 PRL can be written independently.
Figure 14.8-2 PRL Write Operation Block Diagram
ch0 PRL write data
ch1 PRL write data
Transferred in synchronization
with ch1 write in 16-bit
Temporary latch
PPG mode
ch0 write in a mode other
than 16-bit PPG mode
ch1 write
ch0 PRL
226
ch1 PRL
CHAPTER 15
DELAYED INTERRUPT
This chapter explains the functions and operations of the delayed interrupt.
15.1 "Outline of Delayed Interrupt Module"
15.2 "Delayed Interrupt Register"
15.3 "Delayed Interrupt Operation"
227
CHAPTER 15 DELAYED INTERRUPT
15.1 Outline of Delayed Interrupt Module
The delayed interrupt source module is used to generate interrupts for switching
tasks. Using this module, interrupt requests to the F2MC-16LX CPU can be issued and
canceled by software.
■ Block Diagram of Delayed Interrupt
Figure 15.1-1 "Block Diagram" is a block diagram of the delayed interrupt source module.
Internal data bus
Figure 15.1-1 Block Diagram
Delayed interrupt cause issuance/cancellation decoder
Cause latch
■ Notes on Operation
This lock is set by writing "1" to the corresponding bit of DIRR, and is cleared by writing "0" to
the same bit. Therefore, interrupt processing is reactivated immediately after control returns
from interrupt processing, unless the software is designed so that the cause of the interrupt is
cleared within the interrupt processing routine.
228
15.2 Delayed Interrupt Register
15.2 Delayed Interrupt Register
DIRR controls issuance and cancellation of delayed interrupt requests. Writing "1" to
this register issues a delayed interrupt request, and writing "0" cancels the delayed
interrupt request. Upon a reset, the request is canceled.
■ Delayed Interrupt Cause Issuance/Cancellation Register (DIRR)
In DIRR, either "0" or "1" can be written to the reserved bit area. However, it is recommended
that a set bit or clear bit instruction be used to access this register for future expansions.
Figure 15.2-1 Delayed Interrupt Cause Issuance/Cancellation Register (DIRR)
Delayed Interrupt Cause Issuance/Cancellation Register
15
14
13
12
11
10
9
Address : 00009FH
8
Bit No.
R0
DIRR
Read/write
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(R/W)
Initial value
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(0)
229
CHAPTER 15 DELAYED INTERRUPT
15.3 Delayed Interrupt Operation
When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in
the delayed interrupt source module is set and an interrupt request is issued to the
interrupt controller.
■ Delayed Interrupt Occurrence
When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the
delayed interrupt source module is set and an interrupt request is issued to the interrupt
controller. If this interrupt has the highest priority or if there is no other interrupt request, the
interrupt controller issues an interrupt request to the F2MC-16LX CPU. The F2MC-16LX CPU
compares the ILM bit of its internal CCR register and the interrupt request, and starts the
hardware interrupt processing microprogram as soon as the current instruction is completed if
the interrupt level of the request is higher than that of the ILM bit. The interrupt processing
routine for this interrupt is thus executed.
Figure 15.3-1 Delayed Interrupt Issuance
Delayed interrupt source module
Interrupt controller
WRITE
F 2 MC-16LX CPU
Other requests
ICR yy
IL
CMP
CMP
DIRR
ICR xx
ILM
NTA
Writing "0" to the relevant DIRR bit in the interrupt processing routine clears the cause of this
interrupt and switches between tasks.
230
CHAPTER 16
DTP/EXTERNAL INTERRUPTS
This chapter explains the functions and operations of the DTP/external interrupts.
16.1 "Outline of DTP/External Interrupts"
16.2 "DTP/External Interrupt Registers"
16.3 "Operations of DTP/External Interrupts"
16.4 "Switching Between External Interrupt and DTP Requests"
16.5 "Notes on Using DTP/External Interrupts"
231
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.1 Outline of DTP/External Interrupts
The data transfer peripheral (DTP) is located between an external peripheral and the
F2MC-16LX CPU. The DTP receives a DMA request or interrupt request from the
external peripheral, transfers the request to the F2MC-16LX CPU to activate the
intelligent I/O service or interrupt processing.
■ Outline of DTP/External Interrupts
For the intelligent I/O service, "H" and "L" request levels are available. For an external interrupt
request, four request levels are available: "H", "L", rising edge, and falling edge.
■ Block Diagram of DTP/External Interrupts
Figure 16.1-1 Block Diagram of DTP/External Interrupts
Internal data bus
8
8
8
16
232
Interrupt/DTP enable register
Gate
Cause F/F
Edge detection circuit
Interrupt/DTP cause register
Request level setting register
8
Request input
16.1 Outline of DTP/External Interrupts
■ DTP/External Interrupts Registers
Interrupt/DTP enable register
Address : 000030H
Read/write
Initial value
7
6
5
4
3
2
1
0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(R/W)
(0)
Interrupt/DTP cause register
15
Address : 000031H
Read/write
Initial value
ER7
Request level setting register
15
Address : 000033H
Read/write
Initial value
Address : 000032H
Read/write
Initial value
13
12
11
10
9
ER6
ER5
ER4
ER3
ER2
ER1
(R/W)
(X)
(R/W) (R/W)
(X)
(X)
LB7
14
13
12
LA7
LB6
LA6
11
LB5
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
7
6
5
4
3
LB3
LA3
LB2
LA2
LB1
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
8
ER0
10
9
8
LA5
LB4
LA4
(R/W)
(0)
2
LA1
(R/W)
(0)
ENIR
(R/W) (R/W)
(0)
(0)
14
(R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
Bit No.
Bit No.
EIRR
Bit No.
ELVR
(R/W) (R/W)
(0)
(0)
1
LB0
0
LA0
Bit No.
ELVR
(R/W) (R/W)
(0)
(0)
233
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.2 DTP/External Interrupt Registers
The DTP/external interrupts has the following three types of registers:
• Interrupt/DTP enable register (ENIR: Interrupt request enable register)
• Interrupt/DTP flag (EIRR: External interrupt request register)
• Request level setting register (ELVR: External level register)
■ Interrupt/DTP Enable Register (ENIR: Interrupt request enable register)
Figure 16.2-1 Interrupt/DTP Enable Register (ENIR)
Interrupt/DTP enable register
Address : 000030H
Read/write
Initial value
7
6
5
4
3
2
1
0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(R/W)
(0)
Bit No.
ENIR
(R/W) (R/W)
(0)
(0)
ENIR enables the function to issue a request to the interrupt controller using a device pin as an
external interrupt/DTP request input. A pin corresponding to a "1" bit of this register is used as
an external interrupt/DTP request input. A pin corresponding to a "0" bit holds the external
interrupt/DTP request input cause, but does not issue a request to the interrupt controller.
■ Interrupt/DTP Cause Register (EIRR: External interrupt request register)
Figure 16.2-2 Interrupt/DTP Cause Register (EIRR)
Interrupt/DTP cause register
15
Address : 000031H
Read/write
Initial value
ER7
14
13
12
11
10
ER6
ER5
ER4
ER3
ER2
(R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
(R/W)
(X)
9
ER1
8
ER0
Bit No.
EIRR
(R/W) (R/W)
(X)
(X)
The EIRR indicates the presence of external interrupt/DTP requests at the pins corresponding
to the "1" bits of this register. Writing "0" to a bit of this register clears the corresponding request
flag. Writing "1" has no effect. "1" is always read from this register by a read-modify-write
instruction.
Note:
If more than one external interrupt request output is enabled (EN7 to EN0 of ENIR are set to
1), clear to 0 only the bit for which the CPU accepted an interrupt (any of bits ER7 to ER0
that are set to 1). Do not clear the other bits without a valid reason.
234
16.2 DTP/External Interrupt Registers
■ Request Level Setting Register (ELVR: External level register)
Figure 16.2-3 Request Level Setting Register (ELVR)
Request level setting register
Address : 000033 H
Read/write
Initial value
Address : 000032 H
Read/write
Initial value
15
14
13
12
11
10
9
8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(R/W)
(0)
Bit No.
(R/W) (R/W)
(0)
(0)
7
6
5
4
3
2
1
0
Bit No.
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
ELVR
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(R/W)
(0)
(R/W) (R/W)
(0)
(0)
ELVR defines the request event at the external pin. Each pin is assigned two bits as described
in Table 16.2-1 "Interrupt Request Detection Factor for LBx and LAx Pins". If a request is
detected by the input level, the interrupt flag is set as long as the input is at the specified level
even after the flag is reset by software.
Table 16.2-1 Interrupt Request Detection Factor for LBx and LAx Pins
LBx
LAx
0
0
1
1
0
1
0
1
Interrupt request detection factor
L level pin input
H level pin input
Rising edge pin input
Falling edge pin input
235
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.3 Operations of DTP/External Interrupts
When the interrupt flag is set, this block signals an interrupt to the interrupt controller.
The interrupt controller judges the priority levels of the simultaneous interrupts, and
issues an interrupt request to the F2MC-16LX CPU if the interrupt from this block has
the highest priority. The F2MC-16LX CPU compares the ILM bits of its internal CCR
register and the interrupt request. If the interrupt level of the request is higher than
that indicated by the ILM bits, the F2MC-16LX CPU activates the hardware interrupt
processing microprogram as soon as the currently executing instruction is terminated.
■ External Interrupt Operation
In the hardware interrupt processing microprogram, the CPU reads the ISE bit information from
the interrupt controller, identifies that the request is for interrupt processing based on that
information, and branches to the interrupt processing microprogram. The interrupt processing
microprogram reads the interrupt vector area and issues an interrupt acknowledgment signal for
the interrupt controller. Then, the microprogram transfers the jump destination address of the
macro instruction generated from the vector to the program counter, and executes the user
interrupt processing program.
Figure 16.3-1 External Interrupt
DTP/External interrupt
Interrupt controller
F2MC-16LX CPU
ICRyy
IL
Other request
ELVR
EIRR
ENIR
Cause
236
CMP
ICRxx
CMP
ILM
NTA
16.3 Operations of DTP/External Interrupts
■ DTP operation
To activate the intelligent I/O service, the user program initially sets the address of a register,
assigned between 000000H and 0000FFH, in the I/O address pointer of the intelligent I/O
service descriptor. Then, the user program sets the start address of the memory buffer in the
buffer address pointer.
The DTP operation sequence is almost the same as for external interrupts. The operation is
identical until the CPU activates the hardware interrupt processing microprogram. Then, for the
DTP, control is transferred to the intelligent I/O service processing microprogram, since the ISE
bit read by the CPU within the hardware interrupt processing microprogram indicates the DTP.
Once the intelligent I/O service is activated, a read or write signal is sent to the addresses
external peripheral, and data is transferred between the peripheral and the chip. The external
peripheral must cancel the interrupt request to this chip within three machine cycles after the
transfer is made. When the transfer is completed, the descriptor is updated, and the interrupt
controller generates a signal that clears the transfer cause. Upon receiving the signal to clear
the transfer cause, this resource clears the flip-flop holding the cause and prepares for the next
request from the pin. For details of the intelligent I/O service processing, refer to the MB90500
Programming Manual.
Figure 16.3-2 Timing to Cancel the External Interrupt at the End of DTP Operation
Edge request or H level request
Interrupt cause
Internal operation
* When data is transferred from the I/O register to memory
in the intelligent I/O service
Selecting and
reading
descriptor
Read address
Address bus pin
Data bus pin
Write address
Read data
Read signal
Write data
➀
Write signal
➁
Cancel within three machine cycles.
Data, address
bus
Internal bus
Register
External peripheral
Figure 16.3-3 Sample Interface to the External Peripheral
➀
INT
IRQ
DTP
Cancel within three machine
cycles after transfer.
➁
CORE
MEMORY
MB90435
237
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.4 Switching between External Interrupt and DTP Requests
To switch between external interrupt and DTP requests, use the ISE bit in the ICR
register corresponding to this block, which is in the interrupt controller. Each pin is
individually assigned ICR. Thus, a pin is used for a DTP request if "1" is written to the
ISE bit of the corresponding ICR, and is used for an external interrupt request if "0" is
written to the bit.
■ Switching Between External Interrupt and DTP Requests
Figure 16.4-1 Switching Between External Interrupt and DTP Requests
Interrupt controller
0
ICR xx
ICR yy
1
F 2 MC-16 LX CPU
Pin
DTP/
External interrupt
DTP
External interrupt
238
16.5 Notes on Using DTP/External Interrupts
16.5 Notes on Using DTP/External Interrupts
Note carefully the following items when using DTP/external interrupts:
• Conditions on the externally connected peripheral when DTP is used
• Recovery from standby
• External interrupt/DTP operation procedure
• External interrupt request level
■ Notes on Using DTP/External Interrupts
❍ Conditions on the externally connected peripheral when DTP is used
DTP supports only external peripherals that automatically clear a request once a transfer is
completed. The system must be designed so that a transfer request is canceled within three
machine cycles (provisional) after transfer operation starts. Otherwise, this resource assumes
that a transfer request is issued.
❍ External interrupt/DTP operation procedure
To set registers in the external interrupt/DTP, follow the steps below:
1. Disable the bits corresponding to the enable register.
2. Set the bits corresponding to the request level setting register.
3. Clear the bits corresponding to the cause register.
4. Enable the bits corresponding to the enable register.
(Steps 3. and 4. can be simultaneously performed by word specification.)
To set a register in this resource, ensure that the enable register is disabled. Before enabling
the enable register, ensure that the cause register is cleared. Clearing the cause register
prevents a false interrupt cause from being determined while registers are set or interrupts are
enabled.
239
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
❍ External interrupt request level
To detect an edge for an edge request level, the pulse width must be at least three machine
cycles.
As shown in Figure 16.5-1 "Clearing the Cause Hold Circuit Upon Level Set", when the request
input level is related to the level setting, a request that is input from an external device to the
interrupt controller is kept active even if the request is later canceled because a cause hold
circuit has been installed. To cancel the request to the interrupt controller, the cause hold circuit
must be cleared as shown in Figure 16.5-2 "Interrupt Cause and Interrupt Request to the
Interrupt Controller While Interrupts are Enabled".
Figure 16.5-1 Clearing the Cause Hold Circuit Upon Level Set
Interrupt cause
Level detection
Cause F/F (cause hold circuit)
Enable gate
To interrupt
controller
The cause is kept held unless cleared.
Figure 16.5-2 Interrupt Cause and Interrupt Request to the Interrupt Controller While Interrupts are
Enabled
Interrupt cause
H level
Interrupt request to
the interrupt controller
Set inactive when the cause F/F is cleared.
240
CHAPTER 17
A/D CONVERTER
This chapter explains the functions and operations of the A/D converter.
17.1 "Features of A/D Converter"
17.2 "Block Diagram of A/D Converter"
17.3 "A/D Converter Registers"
17.4 "Operations of A/D Converter"
17.5 "Conversion Using EI2OS"
17.6 "Conversion Data Protection"
241
CHAPTER 17 A/D CONVERTER
17.1 Features of A/D Converter
The A/D converter converts analog input voltages into digital values. The A/D
converter has the following features:
■ Features of A/D converter
❍ Conversion time:
26.3 μs min. per channel (at 16 MHz machine clock)
❍ RC sequential compare conversion with sample and hold circuit
❍ 10-bit or 8-bit resolution
❍ Analog input selected from eight channels by programming
Single conversion mode: One channel is selected for conversion.
Scan conversion mode: Voltages in multiple consecutive channels are converted. Up to eight
channels can be programmed.
Continuous conversion mode: Voltages at the specified channel are converted repeatedly.
Stop conversion mode: Voltages at the one channel is converted, then the system pauses and
stands by for the next activation. (The conversion start points can be synchronized.)
❍ Interrupt request
At the end of A/D conversion, a relevant interrupt request can be issued to the CPU. This
interrupt can be used to activate the EI2OS, which automatically transfers A/D conversion result
to memory. This feature is suitable for continuous processing.
❍ Selectable activation cause
The activation can be done by software, external trigger (falling edge), or timer (rising edge).
242
17.1 Features of A/D Converter
■ Analog Input Enable Register
Always write "1" to the ADER bit corresponding to a pin used as analog input.
Figure 17.1-1 Analog Input Enable Register
Analog Input Enable Register
15
14
13
12
11
Address: 00001BH
ADE7
ADE6
ADE5
ADE4
ADE3
Read/write
Initial value
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
9
8
Bit No.
ADE2
ADE1
ADE0
ADER
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
10
Port 6 pins are controlled as described below.
0: Port input/output mode
1: Analog input mode
"1" is set upon a reset.
■ Input Impedance
The sampling circuit of the A/D Converter can be represented with the equivalent circuit shown
below.
Analog input
ADC
30p F max.
Driving impedance to an analog input should be lower than 15.5 KΩ when the sampling time is
set to 4μs (ST=0 and ST0=0 at 16MHz machine clock). Otherwise the conversion accuracy will
be worsened. If this is the case, set the sampling time longer (ST1=1 and ST0=1) or add
external capacitor in order to compensate the driving impedance.
243
CHAPTER 17 A/D CONVERTER
17.2 Block Diagram of A/D Converter
Figure 17.2-1 "Block Diagram of A/D Converter" shows a block diagram of the A/D
converter.
■ Block Diagram of A/D Converter
Figure 17.2-1 Block Diagram of A/D Converter
AVCC
AVRH/L
AVSS
D/A converter
Sequential compare register
Comparator
Decoder
Sample and hold circuit
Data register
ADCR0/1
A/D control register 0
A/D control register 1
ADCS0/1
Activation by external trigger
ADTG pin
Activation by timer
Operation clock
16-bit Reload Timer 1
Prescaler
244
Internal data bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Input circuit
MPX
17.3 A/D Converter Registers
17.3 A/D Converter Registers
The A/D converter has the following two types of registers:
• Control status resister
• Data register
■ A/D Converter Registers
The A/D converter has the following registers:
Figure 17.3-1 A/D Converter Register Configuration
15
8
7
0
ADCS1
ADCS0
ADCR1
ADCR0
8SSR
bit
8 bit
Figure 17.3-2 A/D Converter Registers
A/D control status register (upper)
15
14
Address : 000035H
BUSY
INT
Read/write
(R/W)
Initial value
(0)
13
12
11
10
9
8
INTE PAUS STS1
STS0
STRT Reserved
(R/W) (R/W) (R/W) (R/W)
(R/W)
(R/W) (R/W)
(0)
A/D control status register (lower)
7
6
(0)
(0)
(0)
(0)
(0)
(0)
5
4
3
2
1
0
Address : 000034H
MD1
MD0
ANS2 ANS1 ANS0
ANE2
ANE1 ANE0
Read/write
Initial value
(R/W)
(R/W) (R/W) (R/W) (R/W)
(R/W)
(R/W) (R/W)
Bit No.
ADCS1
Bit No.
ADCS0
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
15
14
13
12
11
10
9
8
Bit No.
Address : 000037H
SI0
ST1
ST0
CT1
CT0
D9
D8
ADCR1
Read/write
(W)
(W)
(W)
(W)
(W)
(-)
(R)
(R)
Initial value
(0)
(0)
(0)
(0)
(1)
(-)
(X)
(X)
7
6
5
4
3
2
1
0
Bit No.
Address : 000036H
D7
D6
D5
D4
D3
D2
D1
D0
ADCR0
Read/write
Initial value
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(R)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Data register (upper)
Data register (lower)
245
CHAPTER 17 A/D CONVERTER
17.3.1 Control Status Registers (ADCS0)
The control status register (ADCS0) controls the A/D converter and indicates the
status. Do not rewrite ADCS0 during A/D conversion.
■ Control Status Registers (ADCS0)
Figure 17.3-3 Control Status Register (ADCS0)
A/D control status register (lower)
7
6
5
4
3
2
1
0
Bit No.
Address: 000034 H
MD1
MD0
ANS2
ANS1
ANS0
ANE2
ANE1
ANE0
ADCS0
Read/write
Initial value
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
[bits 7 and 6] MD1 and MD0 (A/D converter mode set):
Use the MD1 and MD0 bits to set the operation mode.
MD1
MD0
Operation mode
0
0
Single mode. Reactivation during operation is allowed.
0
1
Single mode. Reactivation during operation is not allowed.
1
0
Continuous mode. Reactivation during operation is not allowed.
1
1
Stop mode. Reactivation during operation is not allowed.
❍ Single mode:
A/D conversion is continuously performed from the channel specified with ANS2 to ANS0 to the
channel specified with ANE2 to ANE0. The conversion stops once it has been done for all these
channels.
❍ Continuous mode:
A/D conversion is repeatedly performed from the channel specified with ANS2 to ANS0 to the
channel specified with ANE2 to ANE0.
246
17.3 A/D Converter Registers
❍ Stop mode:
A/D conversion is performed from the channel specified with ANS2 to ANS0 to the channel
specified with ANE2 to ANE0, pausing for each channel. The A/D conversion is resumed upon
an activation.
Upon a reset, these bits are initialized to "00".
Note:
When activated in the continuous or stop mode, A/D conversion continues until it is stopped
by the BUSY bit.
The conversion is stopped by writing "0" to the BUSY bit.
Reactivation disabled in single mode, continuous mode, and stop mode applies to all kinds
of activation by software, an external trigger, and a timer.
[bits 5, 4, and 3] ANS2, ANS1, and ANS0 (Analog start channel set):
Use these bits to specify the start channel for A/D conversion.
When the A/D converter is activated, A/D conversion starts from the channel selected with
these bits.
ANS2
ANS1
ANS0
Start channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
Note:
* Read
During A/D conversion, the current conversion channel is read from these bits. If the system
is stopped in the stop mode, the last conversion channel is read.
* Upon a reset, these bits are initialized to "000".
247
CHAPTER 17 A/D CONVERTER
[bits 2, 1, and 0] ANE2, ANE1, and ANE0 (Analog end channel set):
Use these bits to set the A/D conversion end channel.
ANE2
ANE1
ANE0
End channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
Note:
When the same channel is written to ANE2 to ANE0 and ANS2 to ANS0, conversion is
performed for one channel only (single conversion).
In the continuous or stop mode, operation returns to the start channel specified in ANS2 to
ANS0 after the conversion is completed for the channel specified in ANE2 to ANE0.
If the ANS value is greater than the ANE value, conversion starts from the ANS channel.
Then, once conversion is complete up to channel 7, operation returns to channel 0 and
conversion is performed up to the ANE channel.
Upon a reset, these bits are initialized to "000".
Example: ANS=6, ANE=3, single mode
Conversion is performed in the following sequence: CH6, CH7, CH0, CH1, CH2, CH3
248
17.3 A/D Converter Registers
17.3.2 Control Status Register (ADCS1)
The control status register (ADCS1) controls the A/D converter and indicates the
status.
■ A/D Control Status Register (ADCS1)
Figure 17.3-4 A/D Control Status Register (ADCS1)
A/D control status register (upper)
15
14
13
12
11
10
9
8
Address: 000035 H
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
Reserved
Read/write
Initial value
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Bit No.
ADCS1
[bit 15] BUSY (busy flag and stop):
- Read
This bit indicates the A/D converter operation.
This bit is set when A/D conversion starts and is cleared when the conversion ends.
- Write
Writing "0" to this bit during A/D conversion forces the conversion to terminate.
The above feature is used for forced stop in continuous or stop mode.
"1" cannot be written to the BUSY bit. With a read-modify-write (RMW) instruction, "1" is
read from this bit. In single mode, this bit is cleared at the end of A/D conversion.
In continuous or stop mode, this bit is not cleared until conversion is stopped by writing "0".
This bit is initialized to "0" upon a reset.
Do not perform a forced stop and activation by software simultaneously (BUSY = 0, STRT =
1).
[bit 14] INT (Interrupt):
This bit is set when conversion data is written to ADCR.
An interrupt request is issued if this bit is set while bit 5 (INTE) is "1". In addition, the EI2OS
is activated if it is enabled. Writing "1" has no effect.
This bit is cleared by writing "0" or by the EI2OS interrupt clear signal.
Note: To clear this bit by writing "0", ensure that A/D conversion is not in progress.
This bit initialized to "0" upon a reset.
249
CHAPTER 17 A/D CONVERTER
[bit 13] INTE (Interrupt enable):
This bit is used to enable or disable interrupts at the end of conversion.
- 0: Interrupts are disabled.
- 1: Interrupts are enabled.
Set this bit when using the EI2OS. The EI2OS is activated when an interrupt request is
issued.
Upon a reset, this bit is initialized to "0".
[bit 12] PAUS (A/D conversion pause):
This bit is set when the A/D conversion is paused.
Only one register is available for storing the A/D conversion result. Therefore, unless the
conversion results are transferred by the EI2OS, the result data would be continuously
updated and destroyed in continuous conversion.
To prevent the above condition, the system is designed so that a data register value must be
transferred by the EI2OS before the next conversion data is saved. A/D conversion pauses
during that period. A/D conversion is resumed at the end of transfer by the EI2OS.
This register is valid only when the EI2OS is used.
Note:
For the conversion data protection function, see Section 17.4 "Operations of A/D Converter".
Upon a reset, this bit is initialized to "0".
[bits 11 and 10] STS1 and STS0 (Start source select):
Upon a reset, these bits are initialized to "00".
These bits are used to select the A/D conversion activation source.
STS1
STS0
Function
0
0
Activation by software
0
1
Activation by external pin trigger and software
1
0
Activation by timer and software
1
1
Activation by external pin trigger, timer, and software
In a mode allowing two or more activation factors, A/D conversion is activated by the source
that occurs first.
The activation source setting changes as soon as it is updated. Thus, take care when
updating it during A/D conversion.
Note:
The external pin trigger is detected by the falling edge. If this bit is updated to external trigger
activation while the external trigger input level is "L", A/D may be activated at once.
When timer is selected, the 16-bit Reload Timer 1 is selected.
250
17.3 A/D Converter Registers
[bit 9] STRT (Start):
A/D conversion is activated when "1" is written to this bit.
To reactivate A/D conversion, write "1" to this bit again.
Upon a reset, this bit is initialized to "0".
In the stop mode, a reactivation during the operation is not supported. Check the BUSY bit
before writing "1".
Do not perform a forced stop and activation by software simultaneously. (BUSY=0, STRT=1)
[bit 8] Reserved bit
Always write "0" to this bit.
251
CHAPTER 17 A/D CONVERTER
17.3.3 Data Registers (ADCR1 and ADCR0)
These registers are used to store the digital values produced as a result of the
conversion. ADCR1 stores the most significant two bits of the conversion result, while
ADCR0 stores the lower eight bits. These register values are updated each time
conversion is completed. Usually, the final conversion value is stored in these bits.
■ Data Registers (ADCR1 and ADCR0)
Figure 17.3-5 Data Registers (ADCR1 and ADCR0)
Data register (lower)
7
6
5
4
3
2
1
0
Bit No.
Address : 000036 H
D7
D6
D5
D4
D3
D2
D1
D0
ADCR0
Read/write
Initial value
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
15
14
13
12
11
10
9
8
Bit No.
SI0
ST1
ST0
CT1
CT0
D9
D8
ADCR1
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(1)
(R)
(X)
(R)
(X)
Data register (upper)
Address : 000037 H
Read/write
Initial value
(-)
(-)
"0" is always read from the bits 10 to 15 of ADCR1.
The conversion data protection function is available. See Section 17.4 "Operations of A/D
Converter" for details. Ensure that no data is written to these registers during A/D conversion.
[bits 15] S10
This bit specifies the resolution of the conversion. When it is set to "0", the 10-bit A/D
conversion is performed. Otherwise the 8-bit A/D conversion is performed and the result is
stored in the D7 to D0.
Reading this bit always returns "0".
252
17.3 A/D Converter Registers
[bits 14 and 13] ST1 and ST0 (Sampling time):
ST1
ST0
Function
0
0
64 machine cycles (4μs at 16MHz)
0
1
Reserved
1
0
Reserved
1
1
4096 machine cycles (256μs at 16MHz)
These bits determines the duration of the voltage sampling time at the input.
Reading these bits always returns "00".
[bits 12 and 11] CT1 and CT0 (Compare time):
CT1
CT0
Function
0
0
176 machine cycles (22μs at 8MHz)
0
1
352 machine cycles (22μs at 16MHz)
1
0
Reserved
1
1
Reserved
These bits determines the duration of the compare operation time.
Do not set to "00" unless the machine clock is 8MHz. Otherwise the conversion accuracy is
not guaranteed.
Reading these bits always returns "00".
253
CHAPTER 17 A/D CONVERTER
17.4 Operations of A/D Converter
The A/D converter operates employs the sequential compare technique, and has a 10bit resolution.
Since the A/D converter has only one register (16 bits) for storing the conversion
result, the conversion data registers (ADCR0 and ADCR1) are updated each time
conversion is completed. Thus, the A/D converter alone must not be used for the
continuous conversion. Use the Extended intelligent I/O service (EI2OS) function to
transfer converted data to memory while conversion is in progress.
The operation modes are explained below.
■ Single Mode
In this mode, the converter sequentially converts the analog inputs specified with the ANS and
ANE bits. The converter stops operation after the conversion is completed for the end channel
specified with the ANE bits. If the start and end channels are the same (ANS = ANE),
conversion is performed only for one channel.
Example:
ANS = 0 0 0, ANE = 0 1 1
Start -> AN0 -> AN1 -> AN2 -> AN3 -> End
ANS = 0 1 0, ANE = 0 1 0
Start -> AN2 -> End
■ Continuous Mode
In this mode, the converter sequentially converts the analog inputs specified with the ANS and
ANE bits. After the conversion is completed for the end channel specified with the ANE bits,
conversion is repeated from the analog inputs of the ANS. If the start and end channels are the
same (ANS = ANE), conversion for one channel is repeated.
Example:
ANS = 0 0 0, ANE = 0 1 1
Start -> AN0 -> AN1 -> AN2 -> AN3 -> AN0 -> Repeat
ANS = 0 1 0, ANE = 0 1 0
Start -> AN2 -> AN2 -> AN2 -> Repeat
In continuous mode, conversion is repeated until "0" is written to the BUSY bit. (Writing "0" to
the BUSY bit forces the operation to end.) If the operation is terminated forcibly, conversion
stops before conversion is completed. (Upon a forced stop, the conversion register stores the
last data that has been converted completely.)
254
17.4 Operations of A/D Converter
■ Stop Mode
In this mode, the converter sequentially converts the analog inputs specified with the ANS and
ANE bits, pausing each time conversion for one channel is completed. To release pausing,
activate the converter again.
After the conversion is completed for the end channel specified with the ANE bits, conversion is
repeated from the analog inputs of the ANS. If the start and end channels are the same (ANS =
ANE), conversion is performed only for one channel.
Example:
ANS = 0 0 0, ANE = 0 1 1
Start -> AN0 -> End -> Restart -> AN1 -> End -> Restart -> AN2 -> End ->
-> Restart -> AN3 -> End -> Restart --->AN0
Repeat
ANS = 0 1 0, ANE = 0 1 0
Start -> AN2 -> End -> Restart -> AN2 -> End -> Restart -> AN2 Repeat
Only the activation sources specified with STS1 and STS0 are used.
Using this mode, start of conversion can be synchronized with the activation source.
255
CHAPTER 17 A/D CONVERTER
17.5 Conversion Using EI2OS
Figure 17.5-1 "A/D conversion processing flow from the start to converted data
transfer (in continuous mode)" shows the processing flow from the start of A/D
conversion to the transfer of converted data (in continuous mode).
■ Conversion Using EI2OS
Figure 17.5-1 A/D conversion processing flow from the start to converted data transfer (in continuous
mode)
Starting A/D conversion
Sample and hold
Starting EI2OS
Conversion
Transferring data
Interrupt processing
End of conversion
Issuing interrupt
The portion indicated by the star (
256
Clearing interrupt
) is determined according to the EI2 OS setting.
17.5 Conversion Using EI2OS
17.5.1 Starting EI2OS in Single Mode
Follow the steps below to start the EI2OS in single mode.
• To terminate conversion after analog inputs AN1 to AN3 are converted
• To transfer conversion data sequentially to addresses 200H to 205H
• To start conversion by software
• To use the highest interrupt level
■ Starting EI2OS in Single Mode
Table 17.5-1 Example of Starting EI2OS in Single Mode
Settings
EI2OS setting
Sample program
Function
MOV ICR3, #08H
Specifies the highest interrupt level, EI2OS
activation upon an interrupt, and the descriptor
address.
MOV BAPL, #00H
Specifies the transfer destination address of
converted data.
MOV BAPM, #02H
MOV BAPH, #00H
MOV ISCS, #18H
Specifies word data transfer. The transfer
destination address is incremented after
transfer. Data is transferred from I/O to memory.
Transfer is not terminated in response to a
request from a resource.
MOV I / OA, #36H
A/D converter
setting
Interrupt
sequence
MOV DCT, #03H
EI2OS transfer is performed three times. This
count is the same as the conversion count.
MOV ADCS0 #0BH
Specifies single mode, start channel AN1, and
end channel AN3.
MOV ADCS1 #A2H
Specifies activation by software and start of A/D
conversion.
RET
Specifies return from an interrupt.
ICR3: Interrupt control register
BAPL: Buffer address pointer, low-order
BAPM: Buffer address pointer, medium-order
BAPH: Buffer address pointer, high-order
ISCS: EI2OS status register
I/OA: I/O address counter
DCT: Data counter
257
CHAPTER 17 A/D CONVERTER
Figure 17.5-2 Example of Starting EI2OS in Single Mode
Activation
AN1
Interrupt
EI2 OS transfer
AN2
Interrupt
EI 2OS transfer
AN3
Interrupt
EI 2OS transfer
End
Interrupt sequenc
Parallel processing
258
17.5 Conversion Using EI2OS
17.5.2 Starting EI2OS in Continuous Mode
Follow the steps below to start the EI2OS in continuous mode.
• To convert analog inputs AN3 to AN5 and obtain two conversion data items for each
channel
• To transfer conversion data sequentially to addresses 600H to 60BH
• To start conversion by external edge input
• To use the highest interrupt level
■ Starting EI2OS in Continuous Mode
Table 17.5-2 Example of Starting EI2OS in Continuous Mode
Settings
EI2OS setting
Sample program
Function
MOV ICR3, #08H
Specifies the highest interrupt level, EI2OS
activation upon an interrupt, and the
descriptor address.
MOV BAPL, #00H
Specifies the transfer destination address of
converted data.
MOV BAPM, #06H
MOV BAPH, #00H
A/D converter setting
Interrupt sequence
MOV ISCS, #18H
Specifies word data transfer. The transfer
destination address is incremented after
transfer. Data is transferred from I/O to
memory. Transfer is not terminated in
response to a request from a resource.
MOV I / OA, #36H
Transfer source address
MOV DCT, #06H
EI2OS transfer is performed six times. Data is
transferred for three channels x 2.
MOV ADCS0 #9DH
Specifies continuous mode, start channel
AN3, and end channel AN5.
MOV ADCS1 #A4H
Specifies activation by external edge and
start of A/D conversion.
MOV ADCS1 #00H
Specifies return from an interrupt.
RET
ICR3: Interrupt control register
BAPL: Buffer address pointer, low-order
BAPM: Buffer address pointer, medium-order
BAPH: Buffer address pointer, high-order
ISCS: EI2OS status register
I/OA: I/O address counter
DCT: Data counter
259
CHAPTER 17 A/D CONVERTER
Figure 17.5-3 Example of Starting EI2OS in Continuous Mode
Activation
AN3
Interrupt
EI 2 OS transfer
AN4
Interrupt
EI 2 OS transfer
AN5
Interrupt
EI 2 OS transfer
After six transfers
Interrupt sequenc
End
260
17.5 Conversion Using EI2OS
17.5.3 Starting EI2OS in Stop Mode
Follow the steps below to start the EI2OS in stop mode.
• To convert analog input AN3 12 times at fixed intervals
• To transfer conversion data sequentially to addresses 600H to 617H
• To start conversion by external edge input
• To use the highest interrupt level
■ Starting EI2OS in Stop Mode
Table 17.5-3 Example of Starting EI2OS in Stop Mode
Settings
EI2OS setting
Sample program
Function
MOV ICR3, #08H
Specifies the highest interrupt level, EI2OS
activation upon an interrupt, and the
descriptor address.
MOV BAPL, #00H
Specifies the transfer destination address of
converted data.
MOV BAPM, #06H
MOV BAPH, #00H
A/D converter setting
Interrupt sequence for
terminating
EI2OS
MOV ISCS, #18H
Specifies word data transfer. The transfer
destination address is incremented after
transfer. Data is transferred from I/O to
memory. Transfer is not terminated in
response to a request from a resource.
MOV I / OA, #36H
Transfer source address
MOV DCT, #0CH
EI2OS transfer is performed 12 times.
MOV ADCS0 #DBH
Specifies stop mode, start channel AN3, and
end channel AN3 (one-channel conversion).
MOV ADCS1 #A4H
Specifies activation by external edge and
start of A/D conversion.
MOV ADCS1 #00H
Specifies return from an interrupt.
RET
ICR3: Interrupt control register
BAPL: Buffer address pointer, low-order
BAPM: Buffer address pointer, medium-order
BAPH: Buffer address pointer, high-order
ISCS: EI2OS status register
I/OA: I/O address counter
DCT: Data counter
261
CHAPTER 17 A/D CONVERTER
Figure 17.5-4 Example of Starting EI2OS in Stop Mode
Activation
AN3 → Interrupt → EI2OS transfer
After 12 transfers
Stop
Activation by external edge
Interrupt sequenc
End
262
17.6 Conversion Data Protection
17.6 Conversion Data Protection
The A/D converter has a conversion data protection function that enables continuous
conversion and preservation of multiple data items using EI2OS.
One conversion data register is provided, and its value is updated after conversion.
When continuous A/D conversion is performed, conversion data is stored upon
completion of each conversion and the previous data is lost. To prevent this situation,
the A/D converter pauses without storing conversion data in the register if the
previous data has not been transferred to memory by EI2OS, even though conversion
has been completed.
■ Conversion Data Protection
The pause is released after data is transferred to memory by EI2OS.
If the previous data has been transferred to memory, the A/D converter continues operation
without pausing.
Note:
This function is related to the INT and INTE bits of ADCS1.
The data protection function operates only when interrupts are enabled (INTE=1).
If interrupts are disabled (INTE=0), this function is disabled. Continuous A/D conversion
results in loss of previous data, since the converted data items are saved to the register one
after another.
If EI2OS is not used while interrupts are enabled (INTE=1), the INT bit is not cleared. Thus,
the data protection function works and the A/D converter pauses. In this case, clearing the
INT bit in the interrupt sequence releases the pause.
If the A/D converter is pausing during EI2OS operation, disabling interrupts may restart the
A/D converter. In this case, the value in the conversion data register may be changed
without being transferred.
Restarting the A/D converter while it is pausing destroys the standby data.
263
CHAPTER 17 A/D CONVERTER
■ Flow of Data Protection Function (When EI2OS is Used)
Figure 17.6-1 Flow of Data Protection Function (When EI2OS Is Used)
Setting EI 2OS
Starting continuous A/D conversion
Ending first conversion
Saving the result in the data register
Starting EI2 OS
Ending second conversion
End EI 2 OS?
NO
Pausing A/D conversion
YES
YES
Saving the result in the data register
End EI2OS?
*
NO
Starting EI 2OS
Ending third conversion
Continued
Starting EI 2 OS
Ending the last conversion
Interrupt routine
End
Stooping A/D conversion
*: If the converter is restarted when it is pausing, standby conversion data is lost.
■ Notes on using the conversion data protection function
To start the A/D converter upon an external trigger or internal timer, A/D activation factor bits
STS1 and STS0 of the ADCS2 register are used. Ensure that the input values of the external
trigger or internal timer are inactive. If the values are active, A/D conversion may start
immediately.
When setting STS1 and STS0, ensure that "1" (input) is specified for ADTG and "0" (output) is
specified for the internal timer (timer 2).
264
CHAPTER 18
UART0
This chapter explains the UART0 functions and operations.
18.1 "Feature of UART0"
18.2 "UART0 Block Diagram"
18.3 "UART0 Registers"
18.4 "UART0 Operation"
18.5 "Baud Rate"
18.6 "Internal and External Clock"
18.7 "Transfer Data Format"
18.8 "Parity Bit"
18.9 "Interrupt Generation and Flag Set Timings"
18.10 "UART0 Application Example"
265
CHAPTER 18 UART0
18.1 Feature of UART0
UART0 is a serial I/O port for asynchronous (start-stop) or CLK synchronous
communication with external devices.
■ Feature of UART0
UART0 has the following features.
266
•
Full duplex double buffer
•
Supports CLK synchronous and CLK asynchronous start-stop data transfer.
•
Multiprocessor mode support (mode 2)
•
Internally dedicated baud rate generator (12 types)
•
Supports flexible baud rate setting using an external clock input or internal timer.
•
Variable data length (7 to 9 bits, [no parity]; 6 to 8 bits [with parity]).
•
Error detect function (framing, overrun, and parity)
•
Interrupt function (receive and transmit interrupts) Error detect function (framing, overrun,
and parity)
•
NRZ type transfer format
18.2 UART0 Block Diagram
18.2 UART0 Block Diagram
Figure 18.2-1 "Overall Block Diagram" shows a block diagram of the UART0.
■ UART0 Block Diagram
Figure 18.2-1 Overall Block Diagram
Control signal
Receive interrupt
(to CPU)
Dedicated baud rate clock
SCK0
Transmit clock
16-bit reload timer 0
Clock select
circuit
Transmit interrupt
(to CPU)
Receive clock
SCK0
SIN0
Receive control circuit
Transmit control circuit
Start bit detect
circuit
Transmit start circuit
Receive bit counter
Transmit bit counter
Receive parity
counter
Transmit parity
counter
SOT0
Receive status
evaluation circuit
Transmit shifter
Receive shifter
Receive
complete
Transmit start
UIDR0
UODR0
Receive error
indication signal
for EI2OS (to CPU)
Internal data bus
UMC0
register
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
USR0
register
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
URD0
register
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
Control signal
267
CHAPTER 18 UART0
18.3 UART0 Registers
The UART0 has the following four registers:
• Serial mode control register
• Status register
• Input data register/output data register
• Rate and data register
■ UART0 Registers
Figure 18.3-1 UART0 Register
Serial mode control register 0
7
PEN
Address: 000020H
Address: 000021H
Read/write
Initial value
268
MC1
MC0
(R/W)
(0)
(R/W)
(0)
3
SMDE
(R/W)
(0)
2
1
0
RFC
SCKE
SOE
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(W)
(1)
13
12
11
10
9
8
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
(R)
(R)
(0)
(0)
(R)
(0)
(R)
(1)
(R/W)
(0)
(R/W)
(0)
(R)
(0)
(R)
(0)
Read/write
Initial value
Read/write
Initial value
4
14
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
14
13
12
11
10
9
8
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
UMC0
USR0
6
(R/W)
(0)
Bit No.
Bit No.
7
Address: 000022H
Address: 000023 H
5
15
Input data register 0/
Output data register 0
Rate and data register 0
SBL
(R/W)
(0)
Read/write
Initial value
Status register 0
6
(R/W)
(X)
Bit No.
UIDR0 (read)
UODR0 (write)
Bit No.
URD0
18.3 UART0 Registers
18.3.1 Serial Mode Control Register 0 (UMC0)
UMC0 specifies the operation mode of UART0. Set the operation mode while operation
is halted. However, the RFC bit can be accessed during operation.
■ Serial Mode Control Register 0 (UMC0)
Figure 18.3-2 Serial Mode Control Register 0 (UMC0)
Serial mode control register 0
7
6
5
4
3
2
1
0
Bit No.
Address: 000020 H
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
UMC0
Read/write
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(0)
(0)
(1)
(0)
(0)
[Bit 7] PEN (Parity enable)
Specifies whether to add (for transmit) or detect (for receive) a parity bit in serial data I/O.
Set to "0" in mode 2.
0: Do not use parity
1: Use parity
[Bit 6] SBL (Stop bit length)
Specifies the number of stop bits for transmit data. For receive data, the first stop bit only is
recognized and any second stop bit is ignored.
0: 1 bit length
1: 2 bits length
[Bits 5, 4] MC1, MC0 (Mode control)
These bits control the length of the transferred data. Table 18.3-1 "UART0 Operation
Modes" lists the four transfer modes (data lengths) selectable by these bits.
Table 18.3-1 UART0 Operation Modes
Mode
MC1
MC0
Data Length*1
0
0
0
7 (6)
1
0
1
8 (7)
2*2
1
0
8+1
3
1
1
9 (8)
*1: The figures enclosed in parentheses indicate the data length with parity.
*2: Mode 2 is used when a number of slave CPUs are connected to a single host CPU.
As the receive parity check function cannot be used, set PEN in the UMC0 register to "0"
(see Section 18.4 "UART0 Operation" for details). The transmit data length is 9 bits and
no parity bit can be added.
269
CHAPTER 18 UART0
[Bit 3] SMDE (Synchro mode enable)
This bit selects the transfer method.
0:Start-stop CLK synchronous transfer (clocked synchronous transfer using start and stop
bits.)
1:Start-stop CLK asynchronous transfer
[Bit 2] RFC (Receiver flag clear)
Writing "0" to this bit clears the RDRF, ORFE, and PE flags in the USR0 register. Writing "1"
has no effect. Reading always returns "1".
Note:
When receive interrupts are enabled during UART0 operation, only write "0" to RFC when
either RDRF, ORFE, or PE is "1".
[Bit 1] SCKE (SCLK enable)
Writing "1" to this bit in CLK synchronous mode switches the port pin to the UART0 serial
clock output pin and outputs the synchronizing clock. Set to 0 in CLK asynchronous mode or
external clock mode.
0: The pin functions as a general purpose I/O port and does not output the serial clock. The
pin functions as the external clock input pin when the port is set to input mode (DDR=0)
and RC3 to 0 are set to "1111".
1: The pin functions as the UART0 serial clock output pin.
[Bit 0] SOE (Serial Output Enable)
Writing 1 to this bit switches the port pin to the UART0 serial data output pin, enabling serial
output.
0: The pin functions as a port pin and does not output serial data.
1: The pin functions as the UART0 serial data output pin (SOT).
270
18.3 UART0 Registers
18.3.2 Status Register 0 (USR0)
USR0 indicates the current state of the UART0 port.
■ Status Register 0 (USR0)
Figure 18.3-3 Status Register 0 (USR0)
Status register 0
Address: 000021H
Read/write
Initial value
15
14
13
12
11
10
9
8
Bit No.
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
USR0
(R)
(R)
(0)
(0)
(R)
(0)
(R)
(1)
(R/W)
(0)
(R/W)
(0)
(R)
(0)
(R)
(0)
[Bit 15] RDRF (Receiver data register full)
This flag indicates the state of the UIDR0 (input data register). The flag is set when the
receive data is loaded into UIDR0. Reading UIDR0 or writing "0" to RFC in the UMC0
register clears the flag. If RIE is active, a receive interrupt request is generated when RDRF
is set.
0: No data in UIDR0
1: Data present in UIDR0
[Bit 14] ORFE (Over-run/framing error)
The flag is set when an overrun or framing error occurs in receiving. Writing "0" to RFC in the
UMC0 register clears the flag. When this flag is set, the data in UIDR0 is invalid and the load
from the receive shifter to UIDR0 is not performed. If RIE is active, a receive interrupt
request is generated when ORFE is set.
0: No error
1: Error
Table 18.3-2 "UIDR0 State after Receive Completion" lists the UIDR0 states after receive
completion by RDRF or ORFE.
Table 18.3-2 UIDR0 State after Receive Completion
RDRF
ORFE
UIDR0 Data State
0
0
Empty
0
1
Framing error
1
0
Valid data
1
1
Overrun error
The data in UIDR0 is invalid if an overrun or framing error has occurred. Next data can be
received after clearing the flag(s).
271
CHAPTER 18 UART0
[Bit 13] PE (Parity error)
The flag is set when a receive parity error occurs. Writing "0" to RFC in the UMC0 register
clears the flag. When this flag is set, the data in UIDR0 is invalid and the load from the
receive shifter to UIDR0 is not performed. If RIE is active, a receive interrupt request is
generated when PE is set.
0: No parity error
1: Parity error
[Bit 12] TDRE (Transmitter data register empty)
This flag indicates the state of the UODR0 (output data register). Writing transmit data to the
UODR0 register clears the flag. The flag is set when the data is loaded to the transmit shifter
and the transmission is started. If TIE is active, a transmit interrupt request is generated
when TDRE is set.
0: Data present in UODR0
1: No data in UODR0
[Bit 11] RIE (Receiver interrupt enable)
Enables receive interrupt requests.
0: Disable interrupts.
1: Enable interrupts.
[Bit 10] TIE (Transmitter interrupt enable)
Enables transmit interrupt requests. A transmit interrupt is generated immediately if transmit
interrupts are enabled when TDRE is "1".
0: Disable interrupts.
1: Enable interrupts.
[Bit 9] RBF (Receiver busy flag)
This flag indicates that UART0 is receiving input data. The flag is set when the start bit is
detected and cleared when the stop bit is detected.
0: Receiver idle
1: Receiver busy
[Bit 8] TBF (Transmitter busy flag)
This flag indicates that UART0 is transmitting input data. The flag is set when transmit data
is written to the UODR0 register and cleared when transmission completes.
0: Transmitter idle
1: Transmitter busy
272
18.3 UART0 Registers
18.3.3 Input Data Register 0 (UIDR0) and Output Data Register 0
(UODR0)
UIDR0 (input data register 0) is the serial data input register. UODR0 (output data
register 0) is the serial data output register.
The most significant two bits (D7 and D6) are ignored if the data length is 6 bits and
the most significant bit (D7) is ignored if the data length is 7 bits. Write to UODR0 only
when TDRE = "1" in the USR0 register. Read UIDR0 only when RDRF = "1" in the USR0
register.
■ Input Data Register 0 (UIDR0) and Output Data Register 0 (UODR0)
Figure 18.3-4 Input Data Register 0 (UIDR0) and Output Register 0 (UODR0)
Serial input data register 0
Serial output data register 0
Address: 000022 H
Read/write
Initial value
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Bit No.
UIDR0 (read)
UODR0 (write)
273
CHAPTER 18 UART0
18.3.4 Rate and Data Register 0 (URD0)
URD0 selects the data transfer speed (baud rate) for UART0. The register also holds
the most significant bit (bit 8) of the data when the transmit data length is 9 bits. Set
the baud rate and parity when UART0 is halted.
■ Rate and Data Register 0 (URD0)
Figure 18.3-5 Rate and Data Register 0 (URD0)
Rate and data register 0
Address: 000023H
Read/write
Initial value
15
14
13
12
11
10
9
8
Bit No.
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
URD0
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(X)
[Bits 15, 10] BCH, BCH0 (Baud rate clock change)
Specifies the machine cycles for the baud rate clock (see Section 18.4 "UART0 Operation"
for details).
Table 18.3-3 Clock Input Selection
BCH
BCH0
Divider ratio
Setting Example for Each Machine Cycle
0
0
-
- Prohibited setting -
0
1
Divide by 4
For a 16 MHz machine cycle: 16/4 = 4 MHz
1
0
Divide by 3
For a 12 MHz machine cycle: 12/3 = 4 MHz
1
1
Divide by 5
For a 10 MHz machine cycle: 10/5 = 2 MHz
Note:
Do not set BCH and BCH0 to "00".
[Bits 14 to 11] RC3, RC2, RC1, RC0 (Rate control)
Selects the clock input for the UART0 port (see Section 18.4 "UART0 Operation" for details).
Table 18.3-4 Clock Input Selection
RC3 to RC0
"0000" to "1011"
Clock Input
Dedicated baud rate generator
"1101"
16-bit Reload Timer 0
"1111"
External clock
Note:
Do not set the rate control bits to "1100" "1110".
274
18.3 UART0 Registers
[Bit 9] P
Sets even or odd parity when parity is active (PEN = "1").
0: Even parity
1: Odd parity
[Bit 8] D8
Holds the bit 8 of the transfer data in mode 2 or 3 (9-bit data length) and no parity. Treated
as bit 8 of the UIDR0 register for reading. Treated as bit 8 of the UODR0 register for writing.
The bit has no meaning in the other modes. Write to D8 only when TDRE = "1" in the USR0
register.
275
CHAPTER 18 UART0
18.4 UART0 Operation
Table 18.4-1 "UART0 Operating Modes" lists the operating modes for UART0. Set the
UMC0 register to switch between modes.
■ UART0 Operation Modes
Table 18.4-1 UART0 Operating Modes
Mode
Parity
Data Length
On
6
Off
7
On
7
Off
8
Off
8+1
On
8
Off
9
Clock Mode
Length of Stop Bits*
0
1
2
CLK asynchronous or CLK
synchronous
1 bit or 2 bits
3
*: The number of stop bits can only be set for transmission. The number of receive stop bits is always set to
one. Do not set modes other than those listed above. UART0 does not operate if an invalid mode is set.
Note:
UART0 uses start-stop clock synchronous transfer. Therefore, a start and stop bit are added
to the data even in clock synchronous transfer.
276
18.5 Baud Rate
18.5 Baud Rate
When the dedicated baud rate generator is used, the following two types of baud rates
are available:
• CLK synchronous baud rate
• CLK asynchronous baud rate
■ CLK Synchronous Baud Rate
The five URD0 register bits: BCH, BCH0 and RC3, RC2, RC1 select the baud rate for CLK
synchronous transfer.
First select the machine clock divider ratio using BCH and BCH0.
BCH BCH0
0
1
⇒ Divide by 4
[For example, at 16 MHz: 16/4 = 4 MHz]
1
0
⇒ Divide by 3
[For example, at 12 MHz: 12/3 = 4 MHz]
1
1
⇒ Divide by 5
[For example, at 10 MHz: 10/5 = 2 MHz]
Then, set the division ratio for the clock selected above in RC3, RC2, and RC1. The following
three settings are available for CLK synchronous transfer. Other settings are prohibited.
RC3 RC2 RC1
0
1
0
⇒ Divide by 2
[For example, at 4 MHz: 4/2 = 2.0 M (bps)]
0
1
1
⇒ Divide by 4
[For example, at 4 MHz: 4/4 = 1.0 M (bps)]
1
0
0
⇒ Divide by 8
[For example, at 4 MHz: 4/8 = 0.5 M (bps)]
(At 2 MHz, the speed becomes half the above examples.)
■ CLK Asynchronous Baud Rate
The six URD0 register bits: BCH, BCH0 and RC3, RC2, RC1, RC0 select the baud rate for CLK
asynchronous transfer.
First select the machine clock divider ratio using BCH and BCH0.
BCH BCH0
0
1
⇒ Divide by 4
[For example, at 16 MHz: 16/4 = 4 MHz]
1
0
⇒ Divide by 3
[For example, at 12 MHz: 12/3 = 4 MHz]
1
1
⇒ Divide by 5
[For example, at 10 MHz: 10/5 = 2 MHz]
Then, set the asynchronous transfer clock division ratio for the clock selected above in RC3,
RC2, RC1, and RC0. The following settings are available.
277
CHAPTER 18 UART0
0
0
0
⇒ Divide by 8 × 1
0
1
0
⇒ Divide by 8 × 2
0
1
1
⇒ Divide by 8 × 4
1
0
0
⇒ Divide by 8 × 8
0
0
1
⇒ Not divided
1
0
1
⇒ Divide by 8
⎧
⎪
⎪
⎨
⎪
⎩
⎧
⎪
⎨
⎪
⎪
⎩
RC0
×
×
⎧
⎪
⎨ 0 ⇒ Divide by 12
⎪ 1 ⇒ Divide by 13
⎪
⎩
⎧
⎪
⎪
⎨
⎪
⎩
RC3 RC2 RC1
0
⇒ Prohibited setting
1
⇒ Divide by 8
The above 12 baud rates can be selected. The following formula shows how to calculate the
CLK synchronous baud rate.
Baud rate =
φ/4
2m-1
[bps] (machine cycle = 16 MHz)
Baud rate =
φ/3
2m-1
[bps] (machine cycle = 12 MHz)
Baud rate =
φ/5
2m-1
[bps] (machine cycle = 10 MHz)
where φ is a machine cycle and m is in decimal notation for RC3 to 1.
Note:
The above formula for m=0 or m=1 cannot be calculated.
Data transfer is possible if the CLK asynchronous baud rate is in the range -1% to +1%. The
baud rate is the CLK synchronous baud rate divided by 8 x 13, 8 x 12, or 8.
Table 18.5-1 "Baud Rate" shows examples for 16 MHz, 12 MHz, and 10 MHz machine
cycles. However, do not use the settings marked as "-" in the table.
278
18.5 Baud Rate
Table 18.5-1 Baud Rate
CLK asynchronous (μs/Baud)
CLK synchronous (μs/Baud)
RC
3
RC
2
RC
1
RC
0
BCH/0=01
BCH/0=10
BCH/0=11
CLK
asynchronous
divider ratio
0
0
0
0
-
-
48/ 20833
8 x 12
-
-
-
0
0
0
1
26/ 38460
26/ 38460
52/ 19230
8 x 13
-
-
-
0
0
1
0
-
-
-
8
-
-
-
0
0
1
1
2/500000
2/500000
4/250000
8
-
-
-
0
1
0
0
48/ 20833
48/ 20833
96/10417
8 x 12
-
-
-
0
1
0
1
52/ 19230
52/ 19230
104/ 9615
8 x 13
0.5 / 2M
0.5 / 2M
1 / 1M
0
1
1
0
96/10417
96/10417
192/ 5208
8 x 12
-
-
-
0
1
1
1
104/ 9615
104/ 9615
208/ 4808
8 x 13
1 / 1M
1 / 1M
2 / 500K
1
0
0
0
192/ 5208
192/ 5208
-
8 x 12
-
-
-
1
0
0
1
208/ 4808
208/ 4808
416/ 2404
8 x 13
2 / 500K
2 / 500K
4 / 250K
1
0
1
0
-
-
-
8
-
-
-
1
0
1
1
16/ 62500
16/ 62500
32/ 31250
8
-
-
-
16 MHz
12 MHz
10 MHz
16 MHz
12 MHz
10 MHz
BCH/0=01
BCH/0=10
BCH/0=11
279
CHAPTER 18 UART0
18.6 Internal and External Clock
Setting RC3 to 0 to "1101" selects the clock signal from the 16-bit Reload Timer.
Setting RC3 to 0 to "1111" selects the external clock.
■ Internal and External Clock
The CLK asynchronous baud rate is the CLK synchronous baud rate divided by 8. Also, data
transfer is possible if the CLK asynchronous baud rate is in the range -1% to +1% of the
selected baud rate. Table 18.6-1 "Baud Rate and Reload Value" lists the baud rates when the
internal timer is selected as the clock. The values in this table are calculated for a machine cycle
of 7.3728 MHz. However, do not use the settings marked as "-" in the table.
Baud rate=
φ/X
8 × 2 (n+1)
[bps]
⎛ φ: Machine cycle
⎜
⎜ X: Divider ratio for the count clock source for
⎜
the internal timer
⎜
⎝ n: Reload value (decimal)
⎞
⎟
⎟
⎟
⎟
⎠
Table 18.6-1 Baud Rate and Reload Value
Reload Value
Baud Rate
X = 21
(divide machine cycle by 2)
X = 23
(divide machine cycle by 8)
76800
2
-
38400
5
-
19200
11
2
9600
23
5
4800
47
11
2400
95
23
1200
191
47
600
383
95
300
767
191
The values in the table are the reload values (decimal) for reload count operation of the 16-bit
Reload Timer.
280
18.7 Transfer Data Format
18.7 Transfer Data Format
UART0 only handles NRZ (non-return-to-zero) type data. Figure 18.7-1 "Transfer Data
Format" shows the relationship between the transmit/receive clock and the data for
CLK synchronous mode.
■ Transfer Data Format
Figure 18.7-1 Transfer Data Format
SCK0
SIN0, SOT0
0
Start
1
LSB
0
1
1
0
0
1
0
MSB
1
1
⎫
Stop
Depends
D8 Stop ⎬ on the mode.
⎭
The transferred data is 01001101B (mode 1) or 101001101B (mode 3).
As shown in Figure 18.7-1 "Transfer Data Format", the transfer data always starts with the start
bit (L level data), the specified number of data bits are transmitted with the LSB first, then
transmission ends with the stop bit ("H" level data). Always input a clock if external clock
operation is selected. When an internal clock (the dedicated baud rate generator or 16-bit
Reload Timer) is selected, the clock is output continuously. When using CLK synchronous
transfer, do not start data transfer until the selected baud rate clock has stabilized (for two baud
rate clock cycles).
When using CLK asynchronous transfer, set the SCKE bit in the UMC0 register to "0" to disable
clock output. The transfer data format of SIN0 and SOUT0 is the same as shown in Figure 18.71 "Transfer Data Format".
281
CHAPTER 18 UART0
18.8 Parity Bit
The P bit in the URD0 register specifies whether to use even or odd parity when parity
is enabled. The PEN bit in the UMC0 register enables parity.
■ Parity Bit
Inputting the data shown in Figure 18.8-1 "Serial Data with Parity Enabled" to SIN0 when even
parity is set causes a receive parity error. Figure 18.8-1 "Serial Data with Parity Enabled" also
shows the data transmitted when sending 001101B with even parity and odd parity.
Figure 18.8-1 Serial Data with Parity Enabled
SIN0
(Receive parity error occurs P = 0)
0
Start
1
LSB
0
1
1
0
0
MSB
0
1
Stop
(Parity)
SOT0
(Even parity transmission P = 0)
0
Start
1
LSB
0
1
1
0
0
MSB
1
1
Stop
(Parity)
SOT0
(Odd parity transmission P = 1)
0
Start
1
LSB
0
1
1
0
0
MSB
0
(Parity)
282
1
Stop
18.9 Interrupt Generation and Flag Set Timings
18.9 Interrupt Generation and Flag Set Timings
UART0 has two interrupt causes and six flags. The two interrupt causes are the
receive and transmit interrupts. The six flags are RDRF, ORFE, PE, TDRE, RBF, and
TBF. For reception, the RDRF, ORFE, and PE flags request an interrupt. For
transmission, the TDRE flag requests an interrupt.
■ Set Timings of the Six Flags
❍ RDRF flag
The RDRF flag is set when receive data is loaded into the UIDR0 register. The flag is cleared
by writing "0" to RFC in the UMC0 register or by reading the UIDR0 register.
❍ ORFE flag
The ORFE flag is an overrun or framing error flag. The flag is set when a receive error occurs
and is cleared by writing "0" to RFC in the UMC0 register.
❍ PE flag
The PE flag is a reception parity error flag. The flag is set when a receive parity error occurs
and is cleared by writing "0" to RFC in the UMC0 register. Note that the parity detect function is
not available in mode 2.
❍ TDRE flag
The TDRE flag is set when the UODR0 register becomes empty and is available for writing. The
flag is cleared by writing to the UODR0 register. The above four flags (RDRF, ORFE, PE, and
TDRE) trigger transmit or receive interrupts.
❍ RBF and TBF flags
The RBF and TBF flags indicate that reception or transmission is in progress. The RBF flag
becomes active during reception, and the TBF flag becomes active during transmission.
283
CHAPTER 18 UART0
18.9.1 Flag Set Timings for a Receive Operation (in Mode 0, 1, or
3)
The RDRF, ORFE, and PE flags are set and an interrupt request to the CPU generated
when the final stop bit is detected indicating the end of reception transfer. The data in
UIDR0 is invalid when either the ORFE or PE bit is active.
■ Flag set Timings for a Receive Operation (in Mode 0, 1, or 3)
Figure 18.9-1 "RDRF Set Timing (Mode 0, 1, or 3)", Figure 18.9-2 "ORFE Set Timing (Mode 0,
1, or 3)", and Figure 18.9-3 "PE Set Timing (Mode 0, 1, or 3)" show the set timings of the RDRF,
ORFE, and PE flags respectively.
Figure 18.9-1 RDRF Set Timing (Mode 0, 1, or 3)
Data
Stop
(Stop)
RDRF
Receive interrupt
Figure 18.9-2 ORFE Set Timing (Mode 0, 1, or 3)
Data
Stop
Data
RDRF = 1
RDRF = 0
ORFE
ORFE
Receive interrupt
Stop
Receive interrupt
(Overrun error)
(Framing error)
Figure 18.9-3 PE Set Timing (Mode 0, 1, or 3)
Data
PE
Receive interrupt
284
Stop
(Stop)
18.9 Interrupt Generation and Flag Set Timings
18.9.2 Flag Set Timings for a Receive Operation (in Mode 2)
The RDRF flag is set when the final stop bit is detected and reception transfer ends
with the last data bit (D8) having the value "1".
The ORFE flag is set when the final stop bit is detected, irrespective of the value of the
last data bit (D8). The data in UIDR0 is invalid when the ORFE bit is active.
The interrupt request to the CPU is generated when either of the flags are set (see
Section 18.10 "UART0 Application Example" for details on using mode 2).
■ Flag Set Timings for a Receive Operation (in Mode 2)
Figure 18.9-4 RDRF Set Timing (Mode 2)
Data
D6
D7
D8
Stop
(Stop)
RDRF
Receive interrupt
Figure 18.9-5 ORFE Set Timing (Mode 2)
Data
D7
D8
Stop
Data
RDRF = 1
RDRF = 0
ORFE
ORFE
Receive interrupt
D7
D8
Stop
Receive interrupt
(Overrun error)
(Framing error)
285
CHAPTER 18 UART0
18.9.3 Flag Set Timings for a Transmit Operation
TDRE is set and an interrupt request to the CPU is generated when the data written in
UODR0 register is transferred to the internal shift register and the next data can be
written to UODR0.
■ Flag Set Timings for a Transmit Operation
Figure 18.9-6 TDRE Set Timing (Mode 0)
UODR0 write
TDRE
Interrupt request to the CPU
Transmit interrupt
SOT0 output
ST D0 D1
ST: Start bit
286
D2 D3 D4
D5 D6 D7
D0 to D7: Data bits
SP
SP ST D0 D1
SP: Stop bit
D2 D3
18.9 Interrupt Generation and Flag Set Timings
18.9.4 Status Flag During Transmit and Receive Operation
RBF is set when the start bit is detected and cleared when a stop bit is detected. The
receive data in UIDR0 at the RBF clear timing is not yet valid. The data in UIDR0
becomes valid at the RDRF set timing.
■ Status Flag during Transmit and Receive Operation
Figure 18.9-7 "RBF Set Timing (Mode 0)" shows the relationship between the RBF and receive
interrupt flag timing.
Figure 18.9-7 RBF Set Timing (Mode 0)
SIN0 input
ST D0 D1
D2 D3 D4
D5 D6 D7
SP
RBF
RDRF, PE, ORFE
Writing the transmission data to UODR0 sets TBF. TBF is cleared when transmission
completes.
Figure 18.9-8 TBF Set Timing (Mode 0)
UODR write
SOT0 output
ST D0 D1
D2 D3 D4
D5 D6 D7
SP
SP
TBF
Note:
Receive operation starts after releasing a reset unless the SIN0 input pin is fixed at "1".
Therefore, before setting the mode, write "0" to RFC in the UMC0 register to clear any
receive flags that have been set.
Set the communication mode when the RBF and TBF flags in the USR0 register are "0". The
data transmitted and received during mode setting cannot be guaranteed.
■ EI2OS (Extended intelligent I/O service)
See Section 3.6 "Extended Intelligent I/O Service (EI2OS)" for details about the extended
intelligent I/O service (EI2OS).
287
CHAPTER 18 UART0
18.10 UART0 Application Example
Mode 2 is used when a number of slave CPUs are connected to a host CPU (see Figure
18.10-1 "Example System Configuration Using Mode 2".)
■ Application Example of UART0
As shown in Figure 18.10-1 "Example System Configuration Using Mode 2", communication
starts with the host CPU transmitting address data. The ninth bit (D8) of the address data is set
to "1". The address selects the slave CPU with which communication will be established. The
selected slave CPU communicates with the host CPU using a protocol determined by the user.
In normal data, D8 is set to "0". Unselected slave CPUs wait in standby until the next
communication session starts.
Figure 18.10-2 "Communication Flowchart for Mode 2
Operation" shows a flowchart of operation in this mode.
Because the parity check function is not available in this mode, set the PEN bit in the UMC0
register to "0".
Figure 18.10-1 Example System Configuration Using Mode 2
SOT0
SIN0
Host CPU
288
SOT0 SIN0
SOT0 SIN0
Slave CPU #0
Slave CPU #1
18.10 UART0 Application Example
Figure 18.10-2 Communication Flowchart for Mode 2 Operation
(Host CPU)
(Slave CPU)
Start
Start
Set the transfer mode to 3
Set the transfer mode to 2
Set the slave CPU selection
in D0 to D7. Set D8 to "1".
Transfer the byte.
Receive a byte
No
Selected?
Set D8 to "0" and perform
communications
End
Yes
Set the transfer mode to 3
and enable SOT0 output
Perform communications
with the master CPU
Use the status flag to
confirm transfer completion,
then set the transfer mode to
2 and disable SOT0 output
289
CHAPTER 18 UART0
290
CHAPTER 19
UART1 (SCI)
This chapter explains the UART1 (SCI) functions and operation.
19.1 "Features of UART1"
19.2 "UART1 Block Diagram"
19.3 "UART1 Registers"
19.4 "UART1 Operating Modes and Clock Selection"
19.5 "UART1 Flags and Interrupt Sources"
19.6 "UART1 Interrupts and Flag Set Timing"
19.7 "Negative Clock Operation"
19.8 "UART1 Sample Applications and Precautionary Information"
291
CHAPTER 19 UART1 (SCI)
19.1 Features of UART1
The UART1 is a serial I/O port used for asynchronous (start-stop synchronized)
communication as well as for CLK-synchronized communication.
■ Features of UART1
UART provides the following features.
•
Full-duplex double buffer
•
Asynchronous (start-stop synchronized) and CLK-synchronous communication capability
•
Multi-processor mode support
•
On-chip dedicated baud rate generator
At internal machine clock speeds of 6, 8, 10, 12, 16MHz.
292
•
Asynchronous: 9615/31250/4808/2404/1202 bps
•
CLK synchronous: 1M/500K/250K/125K/62.5 Kbps
•
Automatic baud rate setting from external clock input or internal timer
•
Error detection function (parity, framing, overrun)
•
Transfer communication in NRZ transfer format
•
Intelligent I/O service support
19.2 UART1 Block Diagram
19.2 UART1 Block Diagram
Figure 19.2-1 "UART1 Block Diagram" shows the UART1 block diagram.
■ UART1 Block Diagram
Figure 19.2-1 UART1 Block Diagram
Control signals
Receive interrupt
(to CPU)
Dedicated baud
rate generator
16-bit reload timer 0
SCK1
Transmit clock
Clock
selector
circuit
Transmit
interrupt
(to CPU)
Receive clock
External clock
SIN1
Receive control circuit
Transmit control circuit
Start bit detect circuit
Transmit start circuit
Receive bit counter
Transmit bit counter
Receive parity counter
Transmit parity counter
SOT1
Receive status decision circuit
Receive shifter
Transmit shifter
Receive
complete
Transmit
Start
SIDR1
SODR1
2OS
receive error
I
indication signal (to CPU)
Internal data bus
SMR1
register
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
SCR1
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR1
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
Control bus
293
CHAPTER 19 UART1 (SCI)
19.3 UART1 Registers
Figure 19.3-1 "UART1 Register Configuration" lists the UART1 registers.
■ UART1 Registers
Figure 19.3-1 UART1 Register Configuration
15
8
7
0
SCR1
SMR1
(R/W)
SSR1
SIDR1(R)/SODR1(W)
(R/W)
–
U1CDCR
8bit
8bit
(R/W)
Figure 19.3-2 UART1 Registers
Serial mode register 1
Address: 000024H
7
MD1
6
MD0
5
CS2
4
CS1
3
CS0
Reseved
2
1
SCKE
0
SOE
Read/write
Initial value
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Address: 000025H
15
PEN
14
P
13
SBL
12
CL
11
A/D
10
REC
9
RXE
8
TXE
Read/write
Initial value
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(W)
(1)
(R/W)
(0)
(R/W)
(0)
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
PE
14
ORE
13
FRE
12
RDRF
11
TDRE
10
–
9
RIE
8
TIE
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(1)
(-)
(-)
(R/W)
(0)
(R/W)
(0)
7
MD
6
–
5
–
4
–
3
DIV3
2
DIV2
1
DIV1
0
DIV0
(R/W)
(0)
(-)
(-)
(-)
(-)
(-)
(-)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
Bit No.
SMR1
Serial control register
Bit No.
SCR1
Serial input data register
Serial output data register
Address: 000026H
Read/write
Initial value
Bit No.
SIDR1(Read)
SODR1(Write)
Serial status register
Address: 000027H
Read/write
Initial value
Bit No.
SSR1
Prescaler control register
Address: 000028H
Read/write
Initial value
294
Bit No.
U1CDCR
19.3 UART1 Registers
19.3.1 Serial Mode Register 1 (SMR1)
The serial mode register 1 (SMR1) sets the operating mode of the UART1. Operating
mode settings should be entered when the unit is not in operation. Do not write to this
register during operation.
■ Serial Mode Register 1 (SMR1)
The SMR1 register has the following bit configuration.
Figure 19.3-3 Serial Mode Register 1(SMR1)
Serial Mode Register 1
Address: 000024H
Read/write
Initial value
7
MD1
6
MD0
(R/W) (R/W)
(0)
5
CS2
4
CS1
3
CS0
Reseved
1
SCKE
0
SOE
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
2
Bit No.
SMR1
[bit 7, 6] MD1, MD0 (MoDe select)
These bits select the UART1 operation mode, according to the settings listed in Table 19.3-1
"Operating Mode Selections".
Table 19.3-1 Operating Mode Selections
Mode
MD1
MD0
Operating mode
0
0
0
Asynchronous (start-stop synchronized) normal mode
1
0
1
Asynchronous (start-stop synchronized) multiprocessor mode
2
1
0
CLK synchronous mode
−
1
1
Prohibited
Note:
Mode 1, CLK-asynchronous multi-processor mode, is used when one host CPU is connected
to multiple slave CPUs. This UART1 resource is not able to determine the data format of
incoming data, and therefore in multi-processor mode supports only the master processor.
Also, in this configuration the receive parity check function cannot be used, and therefore the
PEN bit in the UMC1 register should be set to "0".
295
CHAPTER 19 UART1 (SCI)
[bit 5 to bit 3] CS2, CS1, CS0 (Clock Select)
These bits select the baud rate clock source. The baud rate is determined at the same time
as selection of the baud rate generator. Table 19.3-2 "Clock Input Selection Settings" shows
the clock input selection settings.
Table 19.3-2 Clock Input Selection Settings
CS2 to CS0
Clock input
000B to 100B
Dedicated baud rate generator
101B
Reserved
110B
Internal timer*
111B
External clock
*1: When the internal timer is selected, the MB90435 series selects 16-bit reload timer 0
output.
[bit 2] Reserved
Always write "0" to this bit.
[bit 1] SCKE (SCLK Enable)
For communication in CLK synchronous mode (mode 2), this bit determines whether the
SCK1 pin is used as a clock input pin or a clock output pin.
In CLK asynchronous modes or external clock mode, this bit should be set to "0".
0: SCK1 pin functions as clock input pin
1: SCK1 pin functions as clock output pin
Note:
When the pin functions as a clock input, an external clock source must be selected.
[bit0] SOE (Serial Output Enable)
This bit determines whether external pins that also can be used as general purpose I/O port
pins will function as serial output pins (SOT1) or as I/O port pins.
0: General purpose I/O port pin function
1: Serial data output pin (SOT1) function
296
19.3 UART1 Registers
19.3.2 Serial Control Register 1 (SCR1)
The serial control register (SCR1) register controls the transfer protocol used for serial
transmission.
■ Serial Control Register 1 (SCR1)
The SCR1 register has the following bit configuration.
Figure 19.3-4 Serial Control Register (SCR1)
Serial Control Register
Address: 000025H
15
PEN
14
P
13
SBL
12
CL
11
A/D
10
REC
9
RXE
8
TXE
Read/write
Initial value
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(W)
(1)
(R/W)
(0)
(R/W)
(0)
Bit No.
SCR1
[bit 15] PEN (Parity Enable)
This bit determines whether parity bits are attached to data in serial transmission.
0: No parity
1: Parity
Note:
Parity bit attachment is available only in asynchronous (start-stop synchronized)
communications in normal mode (mode 0). In multi-processor mode (mode 1) and all CLKsynchronous communication (mode 2), no parity bits may be attached.
[bit 14] P (Parity)
This bit selects even or odd parity for data communications in which a parity bit is used.
0: Even parity
1: Odd parity
[bit 13] SBL (Stop Bit Length)
This bit sets the length of the stop bit that marks the frame end in asynchronous (start-stop
synchronized) communication.
0: 1 stop bit
1: 2 stop bits
[bit 12] CL (Character Length)
This bit sets the data length of one frame.
0: 7-bit data
1: 8-bit data
Note:
7-bit data handling is available only in asynchronous (start-stop synchronized)
communications in normal mode (mode 0). In multi-processor mode (mode 1) and all CLKsynchronous communication (mode 2), 8-bit data should be used.
297
CHAPTER 19 UART1 (SCI)
[bit 11] A/D (Address/Data)
This bit determines the data format of transmit frames in asynchronous (start-stop
synchronized) communication in multi-processor mode (mode 1).
0: Data frame
1: Address frame
[bit 10] REC (Receiver Error Clear)
This bit clears the error flags (PE, ORE, FRE) in the SSR1 register.
A write value of "1" is not valid, and the read value is "1" at all times.
[bit 9] RXE (Receiver Enable)
This bit controls UART1 receiver operations.
0: Receiver operation prohibited
1: Receiver operation enabled
Note:
If receiver operation is prohibited while reception is in progress (while data is present in the
receive shift register), the receiver will not stop operating until reception of the current frame
is completed, and the data has been stored in the receive data buffer SIDR1 register.
[bit 8] TXE (Transmit Enable)
This bit controls UART1 transmit operation.
0: Transmit operation prohibited
1: Transmit operation enabled
Note:
If transmit operation is prohibited while transmission is in progress (while data is being output
from the transmit register), the transmitter will not stop operating until there is no more data
remaining in the transmit data buffer SODR1 register.
298
19.3 UART1 Registers
19.3.3 Serial Input Data Register 1 (SIDR1) / Serial Output Data
Register 1 (SODR1)
These registers function as receive and transmit data buffer registers.
■ Serial Input Data Register 1 (SIDR1) / Serial Output Data Register 1 (SODR1)
The SIDR1 and SODR1 registers have the following bit configuration.
Figure 19.3-5 Serial Input Data Register 1 (SIDR1)/Serial Output Data Register 1 (SODR1)
Serial input data register
Serial output data register
Address: 000026H
Read/write
Initial value
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
(R/W)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(R/W)
(X)
(X)
(R/W)
(X)
(X)
Bit No.
SIDR1 (read)
SODR1 (write)
The serial input data register 1 (SIDR1) functions as a data buffer register for receiving serial
data.
The serial output data register 1 (SODR1) functions as a data buffer register for
transmitting serial data. When using 7-bit data length, the top bit (D7) contains invalid data. Be
sure the DTRE bit in the SSR1 register is set to "1" before writing to the SODR1 register.
Note:
Writing to these addresses refers to writing to the SODR1 register, and reading refers to
reading from the SIDR1 register.
299
CHAPTER 19 UART1 (SCI)
19.3.4 Serial Status Register 1 (SSR1)
The serial status register (SSR1) is composed of flags that indicate the operating
status of the UART1.
■ Serial Status Register 1 (SSR1)
The SSR1 register has the following bit configuration.
Figure 19.3-6 Serial Status Register 1 (SSR1)
Serial Status Register
Address: 000027H
15
PE
14
ORE
13
FRE
12
RDRF
11
TDRE
10
–
9
RIE
8
TIE
Read/write
Initial value
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(1)
(-)
(-)
(R/W)
(0)
(R/W)
(0)
Bit No.
SSR1
[bit 15] PE (Parity Error)
This interrupt request flag is set when a parity error occurs during receive. Once set, this
flag is cleared by writing "0" to the REC bit (bit 10) in the SCR1 register.
When this bit is set, data in the SIDR1 register is invalid.
0: No parity error
1: Parity error occurred
[bit 14] ORE (Over Run Error)
This interrupt request flag is set when an overrun error occurs during receive. Once set, this
flag is cleared by writing ‘0" to the REC bit (bit 10) in the SCR1 register.
When this bit is set, data in the SIDR1 register is invalid.
0: No overrun error
1: Overrun error occurred
[bit 13] FRE (Framing Error)
This interrupt request flag is set when a framing error occurs during receive. Once set, this
flag is cleared by writing ‘0" to the REC bit (bit 10) in the SCR1 register.
When this bit is set, data in the SIDR1 register is invalid.
0: No framing error
1: Framing error occurred
[bit 12] RDRF (Receiver Data Register Full)
This interrupt request flag is set to indicate that data is present in the SIDR1 register.
This flag is set when receive data is loaded into the SIDR1 register, and is automatically
cleared when the data is read from the SIDR1 register.
0: No receive data
1: Receive data present
300
19.3 UART1 Registers
[bit 11] TDRE (Transmit Data Register Empty)
This interrupt request flag is set to indicate that outgoing data can be written to the SODR1
register.
This flag is cleared when outgoing data is written to the SODR1 register. It is then reset
when the written data starts loading into the transmit shifter to indicate that the next data can
be written to the SODR1 register.
0: Prohibits writing of send data
1: Enables writing of send data
[bit 9] RIE (Receiver Interrupt Enable)
This bit controls receiver interrupts.
0: Interrupt prohibited
1: Interrupt enabled
Note:
Receiver interrupt sources include PE, ORE and FRE errors, as well as normal receive as
indicated by the RDRF flag.
[bit 8] TIE (Transmit Interrupt Enable)
This bit controls transmit interrupts.
0: Interrupt prohibited
1: Interrupt enabled
Note:
Transmit interrupt sources include transmission requests indicated by the TDRE flag.
301
CHAPTER 19 UART1 (SCI)
19.3.5 UART1 Prescaler Control Register (U1CDCR)
The prescaler control register (U1CDCR) controls the machine clock frequency divider.
The UART1 operating clock signal can be generated by dividing the machine clock
signal pulse. The prescaler is designed to enable constant baud rates from a variety of
machine clock speeds.
The output from the prescaler is used by the I/O expanded serial interface.
■ UART1 Prescaler Control Register (U1CDCR)
The U1CDCR register has the following bit configuration.
Prescaler control register
15
MD
14
–
13
–
12
–
11
DIV3
10
DIV2
9
DIV1
8
DIV0
(R/W)
(0)
(-)
(-)
(-)
(-)
(-)
(-)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
Address: 000028H
Read/write
Initial value
Bit No.
U1CDCR
[bit 7] MD (Machine clock divide MoDe select)
This bit enables the prescaler operation.
0: Prescaler stopped
1: Prescaler operating
[bit 3, 2, 1, 0] DIV3-0 (DIVide 3-0)
These bits determine the division of the machine clock frequency as shown in Table 19.3-3
"Machine Clock Division Ratios".
Table 19.3-3 Machine Clock Division Ratios
DIV3
DIV2
DIV1
DIV0
Division ratio *1
1
1
1
0
Divide by 2
1
1
0
1
Divide by 3
1
1
0
0
Divide by 4
1
0
1
1
Divide by 5
1
0
1
0
Divide by 6
1
0
0
1
Divide by 7
1
0
0
0
Divide by 8
Note:
After changing the division ratio, allow an interval of two cycles for the clock frequency to
stabilize before starting communication.
302
19.4 UART1 Operating Modes and Clock Selection
19.4 UART1 Operating Modes and Clock Selection
The UART1 has two types of operating mode, asynchronous mode and CLKsynchronous mode. Changes of mode are controlled by settings in the SMR1 register
and SCR1 register.
■ UART1 Operating Modes
Table 19.4-1 "UART1 Operating Modes" shows the UART1 operating modes.
Table 19.4-1 UART1 Operating Modes
Mode
Parity bit
Data
length
0
Y/N
7
Y/N
8
1
N
8+1
2
N
8
Operating mode
Stop bit length
Asynchronous (startstop synchronized)
normal mode
1-bit or 2-bit
Asynchronous (startstop synchronized)
multi-processor mode
CLK synchronous mode
N
Note:
In asynchronous (start-stop synchronized) normal mode, stop bit length can be set for
outgoing transmission only. For receive, the setting is always 1-bit. The unit does not operate
in modes other than those shown, and only these settings should be used.
303
CHAPTER 19 UART1 (SCI)
■ UART1 Clock Selection
❍ Dedicated baud rate generator
When the dedicated baud rate generator is selected, the baud rate settings listed in Table 19.42 "Baud Rates (Asynchronous communication)" and Table 19.4-3 "Baud Rates (CLKsynchronized communication)" are available. Also, prescaler settings are shown in Table 19.4-4
"Prescaler Settings".
φ in the tables indicates the machine clock.
Table 19.4-2 Baud Rates (Asynchronous communication)
CS2
CS1
CS0
φ/div=2MHz
φ/div=4MHz
φ/div=8MHz
Calculation formula
0
0
0
9615
19230
38460
(φ/div) / (8×13×2)
0
0
1
4808
9615
19230
(φ/div) / (8× 3×22)
0
1
0
2404
4808
9615
(φ/div) / (8×13×23)
0
1
1
1202
2404
4808
((φ/div) / (8×13×24)
1
0
0
31250
62500
-
(φ/div) / 26
Table 19.4-3 Baud Rates (CLK-synchronized communication)
304
CS2
CS1
CS0
φ/div=2MHz
φ/div=4MHz
φ/div=8MHz
Calculation formula
0
0
0
1 MHz
-
-
(φ/div) / 2
0
0
1
500 kHz
1 MHz
-
(φ/div) / 22
0
1
0
250 kHz
500 kHz
1 MHz
(φ/div) / 23
0
1
1
125 kHz
250 kHz
500 kHz
(φ/div) / 24
1
0
0
62.5 kHz
125 kHz
250 kHz
(φ/div) / 25
19.4 UART1 Operating Modes and Clock Selection
Table 19.4-4 Prescaler Settings
Recommended machine
clock speed (φ)
div
DIV3
DIV2
DIV1
DIV0
4 MHz
4
1
1
0
0
6 MHz
6
1
0
1
0
8 MHz
8
1
0
0
0
6 MHz
3
1
1
0
1
8 MHz
4
1
1
0
0
10 MHz
5
1
0
1
1
12 MHz
6
1
0
1
0
14 MHz
7
1
0
0
1
16 MHz
8
1
0
0
0
8 MHz
2
1
1
1
0
12 MHz
3
1
1
0
1
16 MHz
4
1
1
0
0
16 MHz
2
1
1
1
0
φ/div
1 MHz
2 MHz
4 MHz
8 MHz
❍ Internal timer
When bits CS2-0 are set to "110", the internal timer signal is selected, and the 16-bit (timer0)
operates in reload mode. In this case, baud rates are determined as follows.
Asynchronous (start-stop synchronized): (φ / N) / (16 × 2 × (n + 1))
CLK synchronous: (φ / N) / ( 2 × (n + 1))
N: timer count clock source
n: timer reload value
Table 19.4-5 "Baud Rates and Reload Values" shows the relation between baud rates and
reload values (decimal values) at a machine cycle speed of 7.3728MHz.
305
CHAPTER 19 UART1 (SCI)
Table 19.4-5 Baud Rates and Reload Values
Reload value
Baud rate
N=21
(machine cycle division by 2)
N=23
(machine cycle division by 8)
38400
2
−
19200
5
−
9600
11
2
4800
23
5
2400
47
11
1200
95
23
600
191
47
300
383
95
When selecting the internal timer (16-bit timer0) as the baud rate clock source, note that the 16bit timer0 output signal TOUT0 is already connected to the MB90435 controller internally.
Therefore, it is not necessary to make an external connection from the 16-bit timer0 external
output pins TOUT0 to the UART1 external clock input pin SCK1. Also, this means that unless
used in some other fashion, the timer pins are available for use as I/O port pins.
❍ External clock
When bits CS2-0 are set to "111" the external clock source is selected and baud rates are
determined by the following formula, in which f represents the external clock frequency.
Asynchronous (start-stop synchronized) mode: f/16
CLK synchronous: f
Note that f has a maximum value of 2 MHz.
306
19.4 UART1 Operating Modes and Clock Selection
19.4.1 Asynchronous (Start-Stop Synchronized) Mode
The UART1 handles only data in NRZ (non-return to zero) format.
■ Asynchronous (Start-Stop Synchronized) Mode Data Transfer Format
Figure 19.4-1 "Asynchronous (Start-Stop Synchronized) Mode Data Transfer Format (Mode 0,
1)" shows ttransfer data format.
Figure 19.4-1 Asynchronous (Start-Stop Synchronized) Mode Data Transfer Format (Mode 0, 1)
SIN1,SOT1
0
1
0
Start LSB
1
1
0
0
1
0
1
1
MSB Stop........(Mode 0)
A/D Stop........(Mode 1)
Transferred data `01001101B'
As shown in Figure 19.4-1 "Asynchronous (Start-Stop Synchronized) Mode Data Transfer
Format (Mode 0, 1)", transfer data must begin with a start bit ("L" level data value), followed by
LSB-first data of the designated bit-length, and ending with a stop bit ("H" level data value).
When an external clock signal is selected, the clock should be input at all times.
In normal mode (mode 0), data length may be set to 7 bits or 8 bits, however in multi-processor
mode (mode 1) the data length must be 8 bits. Also, no parity bit may be attached in multiprocessor mode. Instead, an A/D bit must be attached.
■ Asynchronous (Start-Stop Synchronized) Mode Receive Operation
Whenever the RXE bit (bit 9) in the SCR1 register is set to "1", UART1 is receiving.
Appearance of a start bit on the receive line allows one frame of data to be received in the data
format determined by the SCR1 register. After the frame is received, error flags are set if the
corresponding errors have occurred, and then the RDRF flag (SST register bit 12) is set. If the
RIE bit (bit 9) in the SSR1 register is set to "1", a receive interrupt is sent to the CPU. The CPU
checks each flag in the SSR1 register and reads the SIDR1 register to see if the data has been
received correctly. If any errors have occurred, take the required action.
The RDRF flag is cleared when the SIDR1 register is read.
■ Asynchronous (Start-Stop Synchronized) Mode Transmit Operation
Whenever the TDRE flag (bit 11) in the SSR1 register is set to "1" the UART1 is writing outgoing
data to the SODR1 register. If the TXE bit (bit 8) is set to "1" transmit operation is in progress.
As soon as data in the SODR1 register starts to be transferred to the transmit shift register for
transmission, the TDRE flag is reset. This enables the next unit of outgoing data to be placed in
the SODR1 register. At this time if the TIE bit (bit 8) in the SSR1 register is set to "1" a
transmission interrupt is sent to the CPU, causing outgoing data to be placed into the SODR1
register.
The TDRE flag is momentarily cleared each time data is placed into the SODR1 register.
307
CHAPTER 19 UART1 (SCI)
19.4.2 CLK Synchronous Mode
The UART1 handles only data in NRZ (non-return to zero) format.
■ CLK Synchronous Mode Data Transfer Format
Figure 19.4-2 "CLK Synchronous Mode Data Transfer Format (Mode 2)" shows the relation
between the transmit and receive clock and data in CLK synchronous mode.
Figure 19.4-2 CLK Synchronous Mode Data Transfer Format (Mode 2)
SODRwrite
Mark
SCLK
RXE,TXE
SIN1,SOT1
1
0
1
1
0
LSB
0
1
0
MSB...................(Mode 2)
Transferred data `01001101B'
When an internal clock signal source (dedicated baud rate generator or internal timer) is
selected, a receive clock signal is automatically generated each time data is transmitted.
When an external clock source is selected it is necessary to provide an accurate 1-byte clock
signal after data is confirmed present in the transmit data buffer register SODR1 (indicated by
the TDRE flag = "0"). Note also that the signal must return to mark level before and after
transmit operation.
Data length is 8-bit only, and no parity bit may be attached. Also, there is no start/stop bit so that
no error detection is enabled except for overrun errors.
■ Control Register Settings for CLK Synchronous Mode
When using CLK synchronous mode, the following settings are made to each of the control
registers.
❍ SMR1 register
MD1, MD0: 10
CS2, CS1, CS0: Indicate clock input
SCKE: 1 for dedicated baud rate generator or internal timer, 0 for external clock
SOE: 1 to send, 0 to receive only
308
19.4 UART1 Operating Modes and Clock Selection
❍ SCR1 register
PEN: 0
P, SBL, A/D: These bits have no significance
CL: 1
REC: 0 (to initialize)
RXE, TXE: At least one must be "1"
❍ SSR1 Register
RIE: 1 if interrupts are used, 0 if interrupts are not used
TIE: 0
■ Start of Communication in CLK Synchronous Mode
Communication starts by writing to the SODR1 register. Even if data is to be only received (not
sent), it is first necessary to write dummy data to the SODR1 register.
■ End of Communication in CLK Synchronous Mode
The end of communication can be verified by the change of the RDRF flag in the SSR1 register
to "1". To determine whether the communication was performed normally, read the ORE bit in
the SSR1 register.
309
CHAPTER 19 UART1 (SCI)
19.5 UART1 Flags and Interrupt Sources
The UART1 has five flags, PE, ORE, FRE, RDRF and TDRE, and two interrupt sources,
one for transmit and one for receive.
■ UART1 Flags
The five flags are the PE, ORE, FRE, RDRF and TDRE flags. The first three are set when
transmit errors occur, the PE flag for a parity error, the ORE flag for an overrun error, and the
FRE flag for a framing error, and are released by writing "0" to the REC bit in the SCR1 register.
The RDRF flag is set when receive data is loaded into the SIDR1 register, and cleared when the
data is read out of the SIDR1 register. Note however that there is no parity detect function in
mode 1, and no parity detect function or framing error detect function in mode 2. The TDRE flag
is set when the SODR1 register is empty and ready for data write access, and is cleared when
data is written to the SODR1 register.
■ UART1 Interrupt Sources
The UART1 has two interrupt sources, one for receive and one for transmit. During receive,
interrupt requests are initiated by setting the PE, ORE, FRE or RDRF flags. During transmit,
interrupt requests are initiated by setting the TDRE flag.
Interrupt flag set timing in each operating mode is described in section 19.6 "UART1 Interrupts
and Flag Set Timing".
310
19.6 UART1 Interrupts and Flag Set Timing
19.6 UART1 Interrupts and Flag Set Timing
This section describes the timing of interrupts and flag setting in each UART1
operating mode.
■ UART1 Interrupts and Flag Set Timing
❍ Mode 0 Receive
The PE, ORE, FRE and RDRF flags are set and the interrupt request signal is sent to the CPU
following the end of a receive transfer, when the final stop bit is detected. If any one of the PE,
ORE or FRE flags is active, the data in the SIDR1 register will be invalid.
Figure 19.6-1 "PE, ORE, FRE, RDRF Flag Set Timing (Mode 0)" shows the timing of the PE,
ORE, FRE, and RDRF flags (mode 0).
Figure 19.6-1 PE, ORE, FRE, RDRF Flag Set Timing (Mode 0)
Data
D6
D7
Stop
PE,ORE,FRE
RDRF
Receiving interrupt
❍ Mode 1 Receive
The ORE, FRE and RDRF flags are set and the interrupt request signal is sent to the CPU after
the end of a receive transfer, when the final stop bit is detected. Also, if the receive data length
is 8 bits, the 9th bit indicating address/data will be invalid. If either the ORE or FRE flags is
active, the data in the SIDR1 register will be invalid.
Figure 19.6-2 "ORE, FRE, RDRF Flag Set Timing (Mode 1)" shows the timing of the ORE, FRE,
and RDRF flags (mode 1).
Figure 19.6-2 ORE, FRE, RDRF Flag Set Timing (Mode 1)
Data
D7
Address/data
Stop
ORE,FRE
RDRF
Receiving interrupt
311
CHAPTER 19 UART1 (SCI)
❍ Mode 2 Receive
The ORE and RDRF flags are set and the interrupt request signal is sent to the CPU after the
end of a receive transfer, when the final data (D7) is detected. If the ORE flag is active, the data
in the SIDR1 register will be invalid.
Figure 19.6-3 "ORE, RDRF Flag Set Timing (Mode 2)" shows the timing of the ORE and RDRF
flags (mode 2).
Figure 19.6-3 ORE, RDRF Flag Set Timing (Mode 2)
Data
D5
D6
D7
ORE
RDRF
Receiving interrupt
❍ Mode 0, Mode 1, and Mode 2 Transmit
The TDRE flag is cleared when data is written to the SODR1 register. The TDRE flag is set (and
an interrupt request sent to the CPU) as soon as the data in the SODR1 register is transferred
to the internal shift register, to ready the SODR1 register for the next data write cycle. During a
transmit operation, if "0" is written to the TXE bit in the SCR1 register (including the RXE bit in
mode 2), the TDRE bit in the SSR1 register will be set to "1" and the UART1 transmit operation
will be disabled as soon as the transmit shifter stops. The data written to the SODR1 register
will be sent, however, between the writing of "0" to the TXE bit in the SCR1 register (including
the RXE bit in mode 2), and the end of the transmit operation. Figure 19.6-4 "TDRE Flag Set
Timing (Mode 0, 1) " shows the timing of the TDRE flag (mode 0, 1), and Figure 19.6-5 "TDRE
Flag Set Timing (Mode 2)" shows the timing of the TDRE flag (mode 2).
Figure 19.6-4 TDRE Flag Set Timing (Mode 0, 1)
SODR write
TDRE
Interrupt request to CPU
SOT1 interrupt
SOT1 output
312
ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3
A/D
ST: Start bit D0 to D7: Data bits SP: Stop bit A/D: Address/data multiplexer
19.6 UART1 Interrupts and Flag Set Timing
Figure 19.6-5 TDRE Flag Set Timing (Mode 2)
SODR write
TDRE
Interrupt request to CPU
SOT1 interrupt
SOT1 output
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
DO to D7: Data bits
313
CHAPTER 19 UART1 (SCI)
19.7 Negative Clock Operation
The MB90435 series supports the negative clock operation of UART1. In this
operation, an inverter can invert the shift clock signal. The definition for the shift clock
signal in an active section in UART1 is inverted from the logic L level to the logic H
level, from the negative edge to the positive edge, or vice versa. This is the same for
serial clock input and output. Thus, the edge selector register is prepared.
■ Negative Clock Operation
Figure 19.7-1 Serial Edge Select Register (SES1)
Serial edge selected after operation
7
6
5
4
Address:000029H
Read/Write
Initial value
314
2
1
0
NEG
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(0)
Table 19.7-1 Setting the NEG Bit
NEG
3
Operation
0
Normal operation [default]
1
The shift clock signal is inverted
Bit No.
SES1
19.8 UART1 Sample Applications and Precautionary Information
19.8 UART1 Sample Applications and Precautionary Information
This section presents a sample system configuration and communication flow chart as
a sample application of the UART1 used in Mode 1.
■ UART1 Sample Application (System Configuration in Mode 1)
Mode 1 is used when one host CPU is connected to multiple slave CPU's (see Figure 19.8-1
"Sample System Configuration in Mode 1"). This UART1 resource supports only communication
interface with the host-side unit.
Figure 19.8-1 Sample System Configuration in Mode 1
S0
S1
Host CPU
S0
S1
Slave CPU #0
S0
S1
Slave CPU #1
■ UART1 Communication Flow Chart
Transmission begins with the transfer of address data by the host CPU. Address data is data
handled while the A/D bit in the SCR1 register is set to "1" and is used to select the slave CPU
that is to receive the transmission, and to enable communication with the host CPU. In normal
data, the A/D bit in the SCR1 register is set to "0". Figure 19.8-2 "Communications Flowchart
Using Mode 1" illustrates the flow of this process.
No parity check function is available in mode 2, so that the PEN bit in the SCR1 register should
be set to "0".
315
CHAPTER 19 UART1 (SCI)
Figure 19.8-2 Communications Flowchart Using Mode 1
(Host CPU)
START
Set transfer mode to 1
Set D0 to D7 to data selecting slave
CPU, set A/D to `1' and transfer 1 byte
Set A/D to `0'
Enable the receiving operation
Communicate with the slave CPU
No
Communication
ended?
Yes
Communicate with
other slave CPU?
No
Yes
Disable receiving operation
END
■ Extended Intelligent I/O Service (EI2OS)
For information about EI2OS, see section 3.6 "Extended Intelligent I/O Service (EI2OS)".
■ Precautions for UART1 Use
Always make communications mode settings when the UART1 is not operating. Transmit and
receive data values are not assured during mode setting.
316
CHAPTER 20
SERIAL I/O
This chapter explains the functions and operations of the serial I/O.
20.1 "Outline of Serial I/O"
20.2 "Serial I/O Registers"
20.3 "Serial I/O Operation"
20.4 "Negative Clock Operation"
317
CHAPTER 20 SERIAL I/O
20.1 Outline of Serial I/O
The serial I/O interface operates in two modes:
• Internal shift clock mode: Data is transferred in synchronization with the internal
clock.
• External shift clock mode: Data is transferred in synchronization with the clock
supplied via the external pin (SCK2). By manipulating the general-purpose port
sharing the external pin (SCK2), data can also be transferred by a CPU instruction in
this mode.
■ Serial I/O Block Diagram
This block is a serial I/O interface that allows data transfer using clock synchronization. The
interface consists of a single eight-bit channel. Data can be transferred from the LSB or MSB.
Figure 20.1-1 Extended Serial I/O Interface Block Diagram
Internal data bus
(MSB first) D7 to D0
D7 to D0 (LSB first)
Transfer direction selection
SIN2
Read
SDR (Serial data register)
Write
SOT2
SCK2
Control circuit
Shift clock counter
Internal clock
(Prescaler)
2
1
0
SMD2 SMD1 SMD0
SIE
SIR
BUSY STOP STRT MODE BDS
Interrupt
request
Internal data bus
318
SOE
SCOE
20.2 Serial I/O Registers
20.2 Serial I/O Registers
The serial I/O has the following two registers:
• Serial mode control status register (SMCS)
• Serial data register (SDR)
■ Serial I/O Resisters
Figure 20.2-1 Serial I/O Registers
Serial Mode Control Status Register
15
Address : 00002DH
Read/write
Initial value
13
SMD2 SMD1 SMD0
12
11
10
SIE
SIR
BUSY
STOP STRT
(R)
(0)
(R/W) (R/W)
(0)
(1)
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
7
Address : 00002CH
Read/write
Initial value
14
6
5
4
3
2
9
8
Bit No.
SMCS
1
0
Bit No.
SCOE
SMCS
MODE
BDS
SOE
(R/W) (R/W)
(0)
(0)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(R/W)
(0)
(R/W)
(0)
7
6
5
4
3
2
1
0
Bit No.
D7
D6
D5
D4
D3
D2
D1
D0
SDR
Serial data register
Address : 00002E H
Read/write
Initial value
Serial I/O prescaler
Address : 00002B H
Read/write
Initial value
(R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
15
MI
14
13
12
11
DIV3
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(-)
(-)
(-)
(1)
(R/W)
(X)
(R/W) (R/W)
(X)
(X)
10
9
8
Bit No.
DIV2
DIV1
DIV0
SCDCR
(R/W)
(1)
(R/W) (R/W)
(1)
(1)
319
CHAPTER 20 SERIAL I/O
20.2.1 Serial Mode Control Status Register (SMCS)
The serial mode control status register (SMCS) controls the serial I/O transfer mode.
■ Serial Mode Control Status Register (SMCS)
Figure 20.2-2 Serial Mode Control Status Register (SMCS)
Serial Mode Control Status Register
15
Address: 00002DH
Read/write
Initial value
14
13
SMD2 SMD1 SMD0
SIE
11
SIR
10
6
5
4
8
STOP STRT
(R)
(0)
(R/W) (R/W)
(1)
(0)
*1
3
MODE
Address: 00002CH
9
BUSY
(R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
7
Read/write
Initial value
12
2
BDS
(-)
(-)
(-)
(-)
(R/W) (R/W)
(-)
(-)
(-)
(-)
(0)
(0)
*1: Only '0' can be written.
*2: Only '1' can be written. '0' is always read.
Bit No.
1
*2
0
Bit No.
SOE
SCOE
SMCS
(R/W) (R/W)
(0)
(0)
[bit 3] Serial mode selection bit (MODE)
The serial mode selection bit is used to select the conditions to start the transfer operation
from the stop state. This bit must not be updated during operation.
Table 20.2-1 Setting the Serial Mode Selection Bit
MODE
Operation
0
Transfer starts when STRT=1. [Default]
1
Transfer starts when the serial data register is read or written to.
This bit is initialized to a "0" upon a reset, and can be read or written to. To activate the
intelligent I/O service, ensure that "1" is written to this bit.
320
20.2 Serial I/O Registers
[bit 2] Bit direction select bit (BDS)
When serial data is input or output, this bit determines from which bit data is to be
transferred first, the least significant bit (LSB first) or the most significant bit (MSB first), as
shown in Table 20.2-2 "Setting the Transfer Direction Selection Bit".
Table 20.2-2 Setting the Transfer Direction Selection Bit
BDS
Operation
0
LSB first [default]
1
MSB first
Note:
Specify the bit ordering before any data is written to SDR.
[bit 1] Serial output enable bit (SOE: Serial out enable)
This bit controls the output from the serial I/O output external pins (SOT2) as shown in Table
20.2-3 "Setting the Serial Output Enable Bit".
Table 20.2-3 Setting the Serial Output Enable Bit
SOE
Operation
0
General-purpose port pin [default]
1
Serial data output
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit 0] Shift clock output enable bit (SCOE: SCK2 output enable)
This bit controls the output from the shift clock I/O output external pins (SCK2) as shown in
Table 20.2-4 "Setting the Shift Clock Output Enable Bit".
Table 20.2-4 Setting the Shift Clock Output Enable Bit
SCOE
Operation
0
General-purpose port pin, transfer for each instruction [default]
1
Shift clock output pin
Ensure that "0" is written to this bit when data is transferred for each instruction in external
shift clock mode.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
321
CHAPTER 20 SERIAL I/O
[Bits 15, 14, and 13] Shift clock selection bits (SMD2, SMD1, SMD0: Serial shift clock
mode)
These bits are used to select the serial shift clock mode, as shown in Table 20.2-5 "Setting
the Serial Shift Clock Mode".
Table 20.2-5 Setting the Serial Shift Clock Mode
SMD2
SMD1
SMD0
φ/div=4 MHz
φ/div=2 MHz
φ/div=1 MHz
0
0
0
2 MHz
1 MHz
500 kHz
0
0
1
1 MHz
500 kHz
250 kHz
0
1
0
250 kHz
125 kHz
62.5 kHz
0
1
1
125 kHz
62.5 kHz
31.25 kHz
1
0
0
62.5 kHz
31.25 kHz
15.625 kHz
1
0
1
External shift clock mode
1
1
0
Reserved
1
1
1
Reserved
div
M1
DIV3
DIV2
DIV1
DIV0
Recommended
machine cycle
3
1
1
1
0
1
6 MHz
4
1
1
1
0
0
8 MHz
5
1
1
0
1
1
10 MHz
6
1
1
0
1
0
12 MHz
7
1
1
0
0
1
14 MHz
8
1
1
0
0
0
16 MHz
Setting of the Serial I/O prescaler (SCDCR)
* For details, see 20.2.3 "Serial I/O Prescaler (SCDCR)".
These bits are initialized to "000" upon a reset. These bits must not be updated during data
transfer.
Five types of internal shift clock and an external shift clock are available. Do not set 110 or
111 in SMD2, SMD1, and SMD0 as these values are reserved.
When external shift clock mode is selected, changing the output levels of the generalpurpose I/O devices sharing the shift clock input will also enable bit shifting.
322
20.2 Serial I/O Registers
[bit 12] Serial I/O interrupt enable bit (SIE: Serial I/O interrupt enable)
This bit controls the serial I/O interrupt request as shown in Table 20.2-6 "Setting the
Interrupt Request Enable Bit".
Table 20.2-6 Setting the Interrupt Request Enable Bit
SEE
Operation
0
Serial I/O interrupt disabled [initial value]
1
Serial I/O interrupt enabled
This bit is initialized to "0" upon a reset. This bit is readable and writable.
[bit 11] Serial I/O interrupt request bit (SIR: Serial I/O interrupt request)
When serial data transfer is completed, "1" is set to this bit. If this bit is set while interrupts
are enabled (SIE=1), an interrupt request is issued to the CPU. The clear condition varies
with the MODE bit.
When "0" is written to the MODE bit, the SIR bit is cleared by writing "0". When "1" is written
to the MODE bit, the SIR bit is cleared by reading or writing to SDR. When the system is
reset or "1" is written to the STOP bit, the SIR bit is cleared regardless of the MODE bit
value.
Writing "1" to the SIR bit has no effect. "1" is always read by a read operation of a readmodify-write instruction.
[bit 10] Transfer status bit (BUSY)
The transfer status bit indicates whether serial transfer is being executed.
323
CHAPTER 20 SERIAL I/O
Table 20.2-7 Setting the Transfer Status Bit
BUSY
Operating
0
Stopped, or standing by for serial data register R/W [default]
1
Serial transfer
This bit is initialized to "0" upon a reset. This is a read-only bit.
[bit 9] Stop bit (STOP)
The stop bit forcibly terminates serial transfer. When "1" is written to this bit, the transfer is
stopped.
Table 20.2-8 Setting the Stop Bit
STOP
Operating
0
Normal operation
1
Transfer stop by STOP=1 [initial value]
This bit is initialized to "1" upon a reset. This bit is readable and writable.
[bit 8] Start bit (STRT: Start)
The start bit activates serial transfer. Writing "1" to this bit starts the data transfer when the
MODE bit is set to 0. When the MODE bit is set to 1 and the STRT bit is set to 1, writing the
data into serial data register starts the transfer.
Writing "1" is ignored while the system is performing serial transfer or standing by for a serial
shift register read or write. Writing "0" has no effect. "0" is always read.
324
20.2 Serial I/O Registers
20.2.2 Serial Shift Data Register (SDR)
This serial data register stores the serial I/O transfer data. During transfer, the SDR
must not be read or written to.
■ Serial Shift Data Register (SDR)
Figure 20.2-3 Serial Shift Data Register (SDR)
Serial Data Register
Address : 00002EH
Read/write
Initial value
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W) (R/W) (R/W) (R/W) (R/W)
(X)
(X)
(X)
(X)
(X)
(R/W)
(X)
Bit No.
SDR
(R/W) (R/W)
(X)
(X)
325
CHAPTER 20 SERIAL I/O
20.2.3 Serial I/O Prescaler (SCDCR)
The Serial I/O Prescaler provides the shift clock for the Serial I/O.
The operation clock for the Serial I/O is obtained by dividing the machine clock. The
Serial I/O is designed so that a constant baud rate can be obtained for a variety of
machine clocks by the user of the communication prescaler. The SCDCR register
controls the machine clock division.
■ Serial I/O Prescaler (SCDCR)
Figure 20.2-4 Serial I/O Prescaler (SCDCR)
Serial I/O Prescaler
15
Address: 00002B H
Read/write
Initial value
14
13
12
11
10
9
8
MI
DIV3
DIV2
DIV1
DIV0
(R/W)
(0)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
Bit No.
SCDCR
[bit 15] MD (Machine clock divide mode select):
This bit is used to control the operation of the communication prescaler.
0: The Serial I/O Prescaler is disabled.
1: The Serial I/O Prescaler is enabled.
[bits 11, 10, 9, and 8] DIV3 to DIV0 (Divide 3 to 0):
These bits are used to determine the machine clock division ratio.
Table 20.2-9 Machine Clock Division Ratio
DIV3 to 0
Division ratio
1101B
3
1100B
4
1011B
5
1010B
6
1001B
7
1000B
8
Note:
When the division ratio is changed, allow two cycles for the clock to stabilize before starting
communication.
326
20.3 Serial I/O Operation
20.3 Serial I/O Operation
The serial I/O consists of the serial mode control status register (SMCS) and shift
register (SDR), and is used for input and output of 8-bit serial data.
■ Serial I/O Operation
The bits in the shift register are serially output via the serial output pin (SOT2 pin) at the falling
edge of the serial shift clock (external clock or internal clock). The bits are serially input to the
shift register (SDR) via the serial input pin (SIN2 pin) at the rising edge of the serial shift clock.
The shift direction (transfer from MSB or LSB) is specified by the direction specification bit
(BDS) of the serial mode control status register (SMCS).
At the end of serial data transfer, this block is stopped or stands by for a read or write of the
data register according to the MODE bit of the serial mode control status register (SMCS). To
start transfer from the stop or standby state, follow the procedure below.
❍ To resume operation from the stop state, write '0' to the STOP bit and '1' to the STRT bit.
(The STOP and STRT bits can be set simultaneously.)
❍ To resume operation from the serial shift data register R/W standby state, read or write to
the data register.
327
CHAPTER 20 SERIAL I/O
20.3.1 Shift Clock
There are two modes of shift clock: internal or external shift clock. These two modes
are selected by setting the SMCS. To switch the modes, ensure that serial I/O transfer
is stopped. To check whether the serial I/O transfer is stopped, read the BUSY bit.
■ Internal Shift Clock Mode
In internal clock mode, the internal clock determines operation, and shift clocks with a duty ratio
of 50% can be output from the SCK2 pin. One bit of data is transferred for each clock. The
transfer speed (baud rate) is shown below:
Baud rate =
φ / div
A
A is a frequency-division ratio and is 21, 22, 24, 25, or 26 indicated by the SMCS SMD bits.
Table 20.3-1 Formulas for Calculating Baud Rate in Internal Shift Clock Mode
SMD2
SMD1
SMD0
φ/div=4MHz
φ/div=2MHz
φ/div=1MHz
Formula
0
0
0
2 MHz
1 MHz
500 kHz
(φ/div)/21
0
0
1
1 MHz
500 kHz
250 kHz
(φ/div)/22
0
1
0
250 kHz
125 kHz
62.5 Hz
(φ/div)/24
0
1
1
125 kHz
62.5 kHz
31.25 kHz
(φ/div)/25
1
0
0
62.5 kHz
31.2 kHz
15.625 kHz
(φ/div)/26
See Table 19.4-4 "Prescaler settings", for the div values.
■ External Shift Clock Mode
In external shift clock mode, the data transfer is based on the external clock supplied via the
SCK2 pin. Data is transferred at one bit per clock.
The transfer speed can be between DC and 1/(8 machine cycles). For example, the transfer
speed can be up to 2 MHz when 1 machine cycle is equal to 62.5 ns.
A data bit can also be transferred by software, which is enabled as described below.
Select external shift clock mode, and write "0" to the SCOE bit of SMCS. Then, write "1" to the
direction register for the port sharing the SCK2 pin, and place the port in output mode. Then,
when "1" and "0" are written to the data register (PDR) of the port, the port value output via the
SCK2 pin is fetched as the external clock and transfer starts. Ensure that the shift clock starts
from "H".
Note:
The SMCS or SDR must not be written to during serial I/O operation.
328
20.3 Serial I/O Operation
20.3.2 Serial I/O Operation
There are four serial I/O operation statuses:
• STOP
• Halt
• SDR R/W standby
• Transfer
■ Serial I/O Operation
❍ STOP
The STOP state is initiated upon RESET or when "1" is written to the STOP bit of SMCS. The
shift counter is initialized, and "0" is written to SIR.
To resume operation from the STOP state, write "0" to STOP and "1" to STRT. (These two bits
can be written to simultaneously.) Since the STOP bit overrides the STRT bit, transfer cannot be
started by writing "1" to STRT while "1" is written to STOP.
❍ Halt
When transfer is completed while the MODE bit is "0", "0" is set to BUSY and "1" is set to SIR of
the SMCS, the counter is initialized, and the system stops. To resume operation from the stop
state, write "1" to STRT.
❍ Serial data register R/W standby
When transfer is completed while the MODE bit is "1", "0" is set to BUSY and "1" is set to SIR of
the SMCS, and the system enters the serial data register R/W standby state. If the interrupt
enable flag is set, an interrupt signal is output from this block.
To resume operation from R/W standby state, read or write to the serial data register. This sets
the BUSY bit to "1" and starts data transfer.
❍ Transfer
"1" is set to the BUSY bit and serial transfer is being performed. According to the MODE bit, the
halt state or R/W standby state comes next.
Figure 20.3-1 "Extended I/O Serial Interface Operation Transitions" is diagrams of the operation
transitions.
329
CHAPTER 20 SERIAL I/O
Figure 20.3-1 Extended I/O Serial Interface Operation Transitions
STOP
STRT=0, BUSY=0
MODE=0
STRT=0, BUSY=0
STOP=1
MODE=0
&
STOP=0
&
END
STOP=0
&
STRT=1
Reset
STOP=0 & STRT=0
End of transfer
STOP=1
STOP=0
&
STRT=1
Transfer
STOP=1
Serial data register R/W standby
MODE=1 & END & STOP=0
STRT=1, BUSY=1
STRT=1, BUSY=0
MODE=1
SDR R/W & MODE=1
Serial data
Figure 20.3-2 Serial Data Register Read/write
Data bus
Data bus
Read
Write
Interrupt output
SOT2
SIN2
Extended I/O
serial interface
Read
Write
d
CPU
c
Interrupt input
Data bus Interrupt controller
1. If "1" is written to MODE, transfer ends according to the shift clock counter. The read/write
standby state starts when "1" is written to SIR. If "1" is written to the SIE bit, an interrupt
signal is generated. No interrupt signal is generated when SIE is inactive or transfer has
been terminated by writing "1" to STOP.
2. Reading or writing to the serial data register clears the interrupt request and starts serial
transfer.
330
20.3 Serial I/O Operation
20.3.3 Shift Operation Start/Stop Timing
To start the shift operation, set the STOP bit to "0" and the STRT bit to "1" in SMCS.
The system may stop the shift operation at the end of transfer or when "1" is set in the
STOP bit.
• Stop by STOP=1 -> The system stops with SIR=0 regardless of the MODE bit.
• Stop by end of transfer -> The system stops with SIR=1 regardless of the MODE
bit.
Regardless of the MODE bit, the BUSY bit becomes "1" during serial transfer and
becomes "0" during stop or R/W standby state. To check the transfer status, read this
bit.
■ Shift Operation Start/Stop Timing
❍ Internal shift clock mode (LSB first)
Figure 20.3-3 Shift Operation Start/Stop Timing (Internal Clock)
'1' output
SCK2
(Transfer start)
STRT
(Transfer end)
If MODE=0
BUSY
SOT2
DO0
DO7 (Data maintained)
❍ External shift clock mode (LSB first)
Figure 20.3-4 Shift Operation Start/Stop Timing (External Clock)
SCK2
(Transfer start)
STRT
(Transfer end)
If MODE=0
BUSY
SOT2
DO0
DO7 (Data maintained)
331
CHAPTER 20 SERIAL I/O
❍ External shift clock mode with instruction shift (LSB first)
Figure 20.3-5 Shift Operation Start/Stop Timing (External Shift Clock Mode with Instruction Shift)
SCK2='0' in PDR
SCK2
STRT
SCK2='0' in PDR
SCK2='1' in PDR (Transfer end)
If MODE=0
BUSY
DO7 (Data maintained)
DO6
SOT2
Note:
For an instruction shift, "H" is output when "1" is written to the bit corresponding to SCK2 of
PDR, and "L" is output when "0" is written. (When SCOE=0 in external shift clock mode)
❍ Stop by STOP=1 (LSB first, internal clock)
Figure 20.3-6 Stop Timing when "1" is Written to the STOP Bit
'1' output
SCK2
(Transfer start)
(Transfer stop)
If MODE=0
STRT
BUSY
STOP
DO3
SOT2
DO4
DO5 (Data maintained)
Note:
DO7 to DO0 indicate output data.
During serial data transfer, data is output from the serial output pin (SOT2) at the falling edge of
the shift clock, and input from the serial input pin (SIN2) at the rising edge.
332
20.3 Serial I/O Operation
Figure 20.3-7 Serial Data I/O Shift Timing 1
❍ LSB first (When the BDS bit is '0')
SCK2
SIN2 Input
SIN2
D10
D11
D12
D13
SOT2 Output
D14
D15
D16
D17
SOT2
DO0
DO1
DO2
DO4
DO5
DO6
DO7
D13
D12
D11
D10
DO3
DO2
DO1
DO0
DO3
Figure 20.3-8 Serial Data I/O Shift Timing 2
❍ MSB first (When the BDS bit is '1')
SCK2
SIN2
SIN2 Input
D17
D16
D15
D14
SOT2 Output
SOT2
DO7
DO6
DO5
DO4
333
CHAPTER 20 SERIAL I/O
20.3.4 Interrupt Function of the Serial I/O Interface
This block can issue an interrupt request to the CPU. At the end of data transfer, the
SIR bit is set as an interrupt flag. When "1" is written to the interrupt enable bit (SIE
bit) of SMCS, an interrupt request is issued to the CPU.
■ Interrupt Function of the Serial I/O Interface
Figure 20.3-9 Interrupt Signal Output Timing of the Extended Serial I/O Interface
SCK2
(Transfer end)
BUSY
SIE=1
SIR
SDR RD/WR
SOT2
334
DO6
DO7 (Data is maintained.)
* When MODE=1
20.4 Negative Clock Operation
20.4 Negative Clock Operation
The MB90435 series supports the negative clock operation of the Serial I/O. In this
operation, the shift clock signal is simply negated by a inverter. Therefore the
definition of the shift clock signal in the preceding sections of the Serial I/O is inverted
from the logic low level to logic high level, from the negative edge to the positive edge
and vise-versa. This is the same for both the serial clock input and output. The edge
select register is installed for this purpose.
■ Negative Clock Operation
Figure 20.4-1 Serial Edge Select Register (SES2)
7
6
5
4
3
2
1
Address : 00002FH
Read/write
Initial value
(R/W) (R/W) (R/W)
(-)
(-)
(-)
(R/W) (R/W)
(-)
(-)
(R/W)
(-)
0
Bit No.
NEG
SES2
(R/W) (R/W)
(-)
(0)
Table 20.4-1 Setting the NEG Bit
NEG
Operation
0
Normal operation [default]
1
The shift clock signal is inverted
335
CHAPTER 20 SERIAL I/O
336
CHAPTER 21
ADDRESS MATCH DETECTION FUNCTION
This chapter explains the address match detection function and operation.
21.1 "Overview of the Address Match Detection Function"
21.2 "Registers of the Address Match Detection Function"
21.3 "Operation of the Address Match Detection Function"
21.4 "Example of the Address Match Detection Function"
337
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION
21.1 Overview of the Address Match Detection Function
When an address matches the value set in the address detection register, the
instruction code to be read by the CPU is replaced with the INT9 instruction code
(01H). Consequently, the CPU executes the INT9 instruction when executing a
specified instruction. The address match detection function can be achieved using the
INT9 interrupt routine for processing.
There are two address detection registers, each with an interrupt permission bit.
When an address matches the value set in the address detection register and the
interrupt permission bit is 1, the instruction code to be read by the CPU is replaced
with the INT9 instruction code.
■ Block Diagram of the Address Match Detection Function
Address latch
Address detection
register
Permission bit
F2MC-16LX bus
338
Comparison
Figure 21.1-1 Block Diagram of the Address Match Detection Function
INT9
instruction
F2MC-16LX
CPU core
21.2 Registers of the Address Match Detection Function
21.2 Registers of the Address Match Detection Function
The two types of registers for the address match detection function are as follows:
• Program address detection registers (PADR0 and PADR1)
• Program address detection control status register (PACSR)
■ Program Address Detection Registers (PADR0 and PADR1)
The program address detection registers 0 and 1 (PADR0 and PADR1) compare the address
with the value written in each register. If they match when the interrupt permission bit
corresponding to ADCSR is 1, the CPU is requested to issue the INT9 instruction.
When the corresponding interrupt bit is 0, nothing occurs.
Figure 21.2-1 Program Address Detection Registers (PADR0 and PADR1)
Program address detection registers
byte
byte
byte
Access
Initial value
PADR0 1FF2H/1FF1H/1FF0H
R/W
Not defined
PADR1 1FF5H/1FF4H/1FF3H
R/W
Not defined
Table 21.2-1 "Correspondence between PADR0 and PADR1 Registers and PACSR" lists the
correspondence between the program address detection registers (PADR0 and PADR1) and
PACSR.
Table 21.2-1 Correspondence between PADR0 and PADR1 Registers and PACSR
Address detection register
Interrupt permission bit
PADR0
AD0E
PADR1
AD1E
■ Program Address Detection Control Status Register (PACSR)
The program address detection control status register (PACSR) controls the operation of the
address detection function.
Figure 21.2-2 Program Address Detection Control Status Register (PACSR)
Program address detection
control status register
Address: 009EH
Read/write
Initial value
7
6
5
4
Reserved Reserved Reserved Reserved
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
3
2
0
AD0E
Reserved
(R/W) (R/W) (R/W)
(0)
(0)
(0)
(R/W)
(0)
AD1E
Reserved
1
Bit No.
PACSR
[Bits 7 to 4] Reserved bits
Bits 7 to 4 are reserved. Set these bits to 0 before setting PACSR.
[Bit 3] AD1E (Address detect register 1 enable)
The AD1E bit is the operation permission bit of ASIE ADR1.
When this bit is 1, the address is compared with the PADR1 register. If they match, the INT9
instruction is issued.
339
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION
[Bit 2] Reserved bit
Bit 2 is reserved. Set this bit to 0 before setting PACSR.
[Bit 1] AD0E (Address Detect register 0 Enable)
The AD0E bit is the operation permission bit of ADR0.
When this bit is 1, the address is compared with the PADR0 register. If they match, the INT9
instruction is issued.
[Bit 0] Reserved bit
Bit 0 is reserved. Set this bit to 0 before setting PACSR.
340
21.3 Operation of the Address Match Detection Function
21.3 Operation of the Address Match Detection Function
If the program counter specifies the same address as the address match detection
register, the INT9 instruction is executed. The address match detection function can
be achieved by processing the INT9 instruction routine.
■ Operation of the Address Match Detection Function
There are two address detection registers with a compare enable bit. When the value set in the
address detection register and the value of the program counter match and the compare enable
bit is set to 1, the CPU executes the INT9 instruction.
Note:
If the value of the address detection register and the value of the program counter match, the
contents of internal data bus is changed to 01H. Consequently, the INT9 instruction is
executed. Before changing the contents of the address detection register, always set the
compare enable bit to 0. While the compare enable bit is set to 1, changing the contents of
the address detection register may result in a malfunction.
341
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION
21.4 Example of the Address Match Detection Function
Figure 21.4-1 "System Configuration Example of the Address Match Detection
Function" shows a system configuration example of the address match detection
function. Table 21.4-1 "E2PROM Memory Map" lists the E2PROM memory map.
■ System Configuration Example of the Address Match Detection Function
Figure 21.4-1 System Configuration Example of the Address Match Detection Function
E2PROM
MCU
F2MC16LX
SIN
Pull-up resister
Connector (UART)
Table 21.4-1 E2PROM Memory Map
Address
0000H
Number of bytes of patch program No.0 (If 0, no
program error exists.)
0001H
Program address No.0 bits 7 to 0
0002H
Program address No.0 bits 15 to 8
0003H
Program address No.0 bits 24 to 16
0004H
Number of bytes of patch program No.1 (If 0, no
program error exists.)
0005H
Program address No.1 bits 7 to 0
0006H
Program address No.1 bits 15 to 8
0007H
Program address No.1 bits 24 to 16
0010H or higher
❍ Initial status
E2PROM is set to all 0s.
342
Description
Main body of patch program No. 0
21.4 Example of the Address Match Detection Function
❍ When a program error occurs:
The main body of the patch program and program address are transferred to the MCU through
the connector (UART). The MCU writes the information to E2PROM.
❍ Reset sequence
The MCU reads the value of E2PROM after reset. If the number of bytes of the patch program
is not 0, the main body of the patch program is read from E2PROM and written to RAM. The
MCU then uses either PADR0 or PADR1 to set the patch address and sets the compare enable
bit. If the relocatable patch program is required, the first address of the patched program can be
written to the RAM area. In this case, the INT9 routine accesses this user-defined RAM area
and jumps to the patched program.
❍ INT9 interrupt
The interrupt routine can know the address where the interrupt occurs by checking the value of
the stack program counter. The information that has been placed on the stack during the
interrupt is discarded.
■ Example of program patch processing
Figure 21.4-2 Example of program patch processing
FFFFFFH
Abnormal program
PC = address in error
ROM
External E2PROM
Register set for
program patch
Number of program bytes
Address where the interrupt occurs
Corrected program
Data transfer using UART
Corrected program
RAM
000000H
343
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION
Figure 21.4-3 Flow of program patch processing
Reset
Reads 00H of E2PROM
INT9
YES
0000H(E2PROM)=0
To patch program
JMP 000400H
NO
Read address
0001H to 0003H (E2PROM)
MOV
PADR0 (MCU)
Execute patch program
000400H to 000480H
Read patch program
0010H to 0090H (E2PROM)
MOV
000400H to 000480H (MCU)
Terminate patch program
JMP FF0050H
Enable compare
MOV PACSR, #02H
Execute normal program
NO
PC=PADR0
YES
INT9
FFFFFFH
FF0050H
Abnormal program
ROM
EEPROM
FF0000H
FFFFH
FE0000H
0090H
Patch program
0010H
001100H
Stack area
0003H
0002H
0001H
0000H
344
Program address
low-order:
Program address
middle-order:
Program address
high-order:
Number of bytes of
the patch program:
RAM area
00
00
000480H
Patch program
RAM
000400H
RAM and register area
FF
000100H
I/O area
80
000000H
CHAPTER 22
ROM MIRRORING FUNCTION SELECTION
MODULE
This chapter explains the ROM mirroring function selection module.
22.1 "Outline of ROM Mirroring Function Selection Module"
22.2 "ROM Mirroring Function Selection Register (ROMM)"
345
CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE
22.1 Outline of ROM Mirroring Function Selection Module
The ROM Mirroring function selection module switches whether to mirror the image of
the FF bank of the ROM to the 00 bank.
■ Block Diagram of ROM Mirroring Function Selection Module
Figure 22.1-1 Block Diagram of ROM Mirroring Function Selection Module
Internal data bus
ROM Mirrroring Function Selection Register
Address Area
Address
FF bank
00 bank
Data
ROM
346
22.2 ROM Mirroring Function Selection Register (ROMM)
22.2 ROM Mirroring Function Selection Register (ROMM)
Do not access the ROM mirroring function selection register (ROMM) when addresses
004000H to 00FFFFH are being accessed.
■ ROM Mirroring Function Selection Register (ROMM)
Figure 22.2-1 ROM Mirroring Function Selection Register (ROMM)
ROM Mirroring Function Selection Module
Address : 0006FH
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
MI
(–)
(–)
(W)
(–)
(1)
Read/write
(–)
(–)
(–)
(–)
(–)
Initial value
(–)
(–)
(–)
(–)
(–)
(–)
Bit No.
ROMM
[bit 8]: MI
The image of the ROM data in the FF bank can also be found in the 00 bank when "1" is
written to this bit. However, this memory mapping will not be done when this bit is written to
"0". This bit is write only.
Note:
Only FF4000H to FFFFFFH is mirrored to 004000H to 00FFFFH when ROM mirroring function
is activated. Therefore, addresses FF0000H to FF3FFFH will not be mirrored to 00 bank.
347
CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE
348
CHAPTER 23
1M/2M-BIT FLASH MEMORY
This chapter explains the functions and operation of the 1M/2M-bit flash memory. The
following three methods are available for writing data to and erasing data from the
flash memory:
• Parallel programmer
• Serial programmer
• Executing programs to write/erase data
This chapter explains "Executing programs to write/erase data".
23.1 "Outline of 1M/2M-bit Flash Memory"
23.2 "Sector Configuration of the Flash Memory"
23.3 "Write/Erase Modes"
23.4 "Flash Memory Control Status Register (FMCS)"
23.5 "Starting the Flash Memory Automatic Algorithm"
23.6 "Confirming the Automatic Algorithm Execution State"
23.7 "Detailed Explanation of Writing to Erasing Flash Memory"
23.8 "Notes on using 1M/2M-bit Flash Memory"
23.9 "Flash Security Feature"
23.10 "Example of Programming 1M/2M-bit Flash Memory"
349
CHAPTER 23 1M/2M-BIT FLASH MEMORY
23.1 Outline of 1M/2M-bit Flash Memory
The 1M/2M-bit flash memory is mapped to the FEH/FCH to FFH bank in the CPU
memory map. The functions of the flash memory interface circuit enable read-access
and program-access from the CPU in the same way as mask ROM. Instructions from
the CPU can be used via the flash memory interface circuit to write data to and erase
data from the flash memory. Internal CPU control therefore enables rewriting of the
flash memory while it is mounted. As a result, improvements in programs and data
can be performed efficiently.
■ 1M/2M-bit Flash Memory Features
•
Use of automatic program algorithm (Embedded Algorithm: Equivalent to MBM29LV200)
•
Erase pause/restart functions provided
•
Detection of completion of writing/erasing using data polling or toggle bit functions
•
Detection of completion of writing/erasing using CPU interrupts
•
Sector erase function (any combination of sectors)
•
Minimum of 10,000 write/erase operations
Embedded Algorithm is a trademark of Advanced Micro Device, Inc.
Note:
The manufacturer code and device code do not have the reading function. These codes
cannot be accessed by the command.
■ Writing to/Erasing Flash Memory
The flash memory cannot be written to and read at the same time. That is, when data is written
to or erased data from the flash memory, the program in the flash memory must first be copied
to RAM. The entire process is then executed in RAM so that data is simply written to the flash
memory. This eliminates the need for the program to access the flash memory from the flash
memory itself.
■ Flash Memory Register
Figure 23.1-1 Flash Memory Control Status Register (FMCS)
7
6
5
4
3
2
1
0
Address: 0000AEH
INTE
RDYINT
WE
RDY
Reserved
LPM1
Reserved
LPM0
Read/write
⇒
(R/W)
(R/W)
(R/W)
(R)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
⇒
(0)
(0)
(0)
(X)
(0)
(0)
(0)
(0)
350
⇐ Bit No.
FMCS
23.2 Sector Configuration of the Flash Memory
23.2 Sector Configuration of the Flash Memory
Figure 23.2-1 "Sector Configuration of the 1M/2M-bit Flash Memory" shows the sector
configuration of the flash memory.
■ Sector Configuration of the 1M/2M-bit Flash Memory
Figure 23.2-1 "Sector Configuration of the 1M/2M-bit Flash Memory" shows the sector
configuration of the 1M/2M-bit flash memory. The addresses in the figure indicate the highorder and low-order addresses of each sector.
Figure 23.2-1 Sector Configuration of the 1M/2M-bit Flash Memory
Flash memory
SA4 (16K bytes)
SA3 (8K bytes)
CPU address
Programmer address*
FFFFFFH
7FFFFH
FFBFFFH
7BFFFH
FF9FFFH
79FFFH
FF7FFFH
77FFFH
FEFFFFH
6FFFFH
Flash memory
SA6 (16K bytes)
SA2 (8K bytes)
SA5 (8K bytes)
SA4 (8K bytes)
SA3 (32K bytes)
SA1 (32K bytes)
CPU address
Programmer address*
FFFFFFH
7FFFFH
FFBFFFH
7BFFFH
FF9FFFH
79FFFH
FF7FFFH
77FFFH
FEFFFFH
6FFFFH
FDFFFFH
5FFFFH
FCFFFFH
4FFFFH
FC0000 H
40000 H
SA2 (64K bytes)
SA0 (64K bytes)
FE0000 H
60000 H
SA1(64K bytes)
SA0 (64K bytes)
*: The programmer address is equivalent to the CPU address when data is written to the flash
memory using a parallel programmer. When a general programmer is used for writing/
erasing, this address is used for writing/erasing.
351
CHAPTER 23 1M/2M-BIT FLASH MEMORY
23.3 Write/Erase Modes
The flash memory can be accessed in two different ways: Flash memory mode and
alternative mode. Flash memory mode enables data to be directly written to or erased
from the external pins. Alternative mode enables data to be written to or erased from
the CPU via the internal bus. Use the mode external pins to select the mode.
■ Flash Memory Mode
The CPU stops when the mode pins are set to 111 while the reset signal is asserted. The flash
memory interface circuit is connected directly to ports 0, 2, 3, and 4, enabling direct control from
the external pins. This mode makes the MCU seem like a standard flash memory to the
external pins, and write/erase can be performed using a flash memory programmer.
In flash memory mode, all operations supported by the flash memory automatic algorithm can
be used.
■ Alternative Mode
The flash memory is located in the FE/FC to FF banks in the CPU memory space, and like
ordinary mask ROM, can be read-accessed and program-accessed from the CPU via the flash
memory interface circuit.
Since writing/erasing the flash memory is performed by instructions from the CPU via the flash
memory interface circuit, this mode allows rewriting even when the MCU is soldered on the
target board.
Sector protect operations cannot be performed in these modes.
■ Flash Memory Control Signals
Table 23.3-1 "Flash Memory Control Signals" lists the flash memory control signals in flash
memory mode.
There is almost a one-to-one correspondence between the flash memory control signals and the
external pins of the MBM29LV200. The VID (12 V) pins required by the sector protect
operations are MD0, MD1, and MD2 instead of A9, RESET, and OE for the MBM29LV200.
In flash memory mode, the external data bus signal width is limited to 8 bits, enabling only onebyte access. The DQ15 to DQ8 pins are not supported. The BYTE pin should always be set to
0.
352
23.3 Write/Erase Modes
Table 23.3-1 Flash Memory Control Signals
MB90F438L(S)/F439(S)
MBM29LV200
Pin number
Normal function
Flash memory mode
1 to 8
P20 to P27
AQ0 to AQ7
A-1, A0 to A6
9
P30
AQ16
A15
10
P31
CE
CE
12
P32
OE
OE
13
P33
WE
WE
14
P34
AQ17
A16
16
P36
BYTE
BYTE
17
P37
RY/BY
RY/BY
18 to 22
P40 to P44
AQ8 to AQ12
A7 to A11
24 to 26
P45 to P47
AQ13 to AQ15
A12 to A14
49
MD0
MDO
A9 (VID)
50
MD1
MD1
RESET (VID)
51
MD2
MD2
OE (VID)
85 to 92
P00 to P07
DQ0 to DQ7
DQ0 to DQ7
77
RST
RESET
RESET
Not supported
DQ8 to DQ15
353
CHAPTER 23 1M/2M-BIT FLASH MEMORY
23.4 Flash Memory Control Status Register (FMCS)
The flash memory control status register (FMCS), together with the flash memory
interface circuit, is used to write data to and erase data from the flash memory.
■ Flash Memory Control Status Register (FMCS)
Figure 23.4-1 Flash Memory Control Status Register (FMCS)
Flash Memory Control Status Register (FMCS)
7
6
5
4
3
2
1
0
Address: 0000AEH
INTE
RDYINT
WE
RDY
Reserved
LPM1
Reserved
LPM0
Read/write
(R/W)
(R/W)
(R/W)
(R)
(R/W)
(R/W)
(R/W)
(R/W)
Initial value
(0)
(0)
(0)
(X)
(0)
(0)
(0)
(0)
Bit No.
FMCS
[Bit 7] INTE (interrupt enable)
This bit generates an interrupt to the CPU when flash memory write/erase terminates.
An interrupt to the CPU is generated when the INTE and RDYINT bits are 1. No interrupt is
generated when the INTE bit is 0.
•
0: Disables interrupts when write/erase terminates.
•
1: Enables interrupts when write/erase terminates.
[Bit 6] RDYINT (ready interrupt)
This bit indicates the operating state of the flash memory.
This bit is set to 1 when flash memory write/erase terminates. Data cannot be written to or
erased from the flash memory while this bit is 0 after a flash memory write/erase. Flash
memory write/erase is enabled when write/erase terminates and this bit is set to 1.
Writing 0 clears this bit to 0. Writing 1 is ignored. This bit is set to 1 at the termination timing
of the flash memory automatic algorithm (see Section 23.5 "Starting the Flash Memory
Automatic Algorithm"). When the read-modify-write (RMW) instruction is used, 1 is always
read.
•
0: Write/erase is being executed.
•
1: Write/erase has terminated (interrupt request generated).
[Bit 5] WE (write enable)
This bit enables writing to the flash memory area.
When this bit is 1, writing after the command sequence (see Section 23.5 "Starting the Flash
Memory Automatic Algorithm") is issued to the FE/FC to FF bank writes to the flash memory
area. When this bit is 0, the write/erase signal is not generated. This bit is used when the
flash memory Write/Erase command is started.
If write/erase is not performed, it is recommended that this bit be set to 0 to prevent data
from being mistakenly written to the flash memory.
354
•
0: Disables flash memory write/erase.
•
1: Enables flash memory write/erase.
23.4 Flash Memory Control Status Register (FMCS)
[Bit 4] RDY (ready)
This bit enables flash memory write/erase.
Flash memory write/erase is disabled while this bit is 0. However, Suspend commands,
such as the Read/Reset command and Sector Erase Suspend command, can be accepted
even if this bit is 0.
•
0: Write/erase is being executed (next data write/erase disabled).
•
1: Write/erase has terminated (next data write/erase enabled).
[Bit 3] Reserved bits
These bits are reserved for testing. During regular use, they should always be set to 0.
[Bit 1] Free bit
During regular use, this bit should always be set to 0.
[Bits 2 and 0] LPM1 and LPM0 (low-power mode)
These bits control the current consumed by the flash memory when the flash memory is
accessed. Since the access time to the flash memory from the CPU is largely dependent on
this setting, select a setting value based on the operating frequency of the CPU.
•
01: Low-power consumption mode (Operates at an internal operating frequency up to 4
MHz.)
•
10: Low-power consumption mode (Operates at an internal operating frequency up to 8
MHz.)
•
11: Low-power consumption mode (Operates at an internal operating frequency up to 10
MHz.)
•
00: Regular power consumption mode (Operates at an internal operating frequency up to 16
MHz.)
Note:
The RDYINT and RDY bits cannot be changed at the same time. Create a program so that
decisions are made using one or the other of these bits.
Figure 23.4-2 RDYINT and RDY Bit Change Timing
Automatic algorithm
Termination timing
RDYINT bit
RDY bit
1 machine cycle
355
CHAPTER 23 1M/2M-BIT FLASH MEMORY
23.5 Starting the Flash Memory Automatic Algorithm
Four types of commands are available for starting the flash memory automatic
algorithm: Read/Reset, Write, and Chip Erase. Control of suspend and restart is
enabled for sector erase.
■ Command Sequence Table
Table 23.5-1 "Command Sequence Table" lists the commands used for flash memory write/
erase. All of the data written to the command register is in bytes, but use word access to write.
The data of the high-order bytes at this time is ignored.
Table 23.5-1 Command Sequence Table
Command
sequence
Bus
write
access
1st bus write cycle
2nd bus write
cycle
3rd bus write
cycle
4th bus write
cycle
5th bus write
cycle
6th bus write
cycle
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Read/Reset
(*1)
1
FxXXXX
XXF0
-
-
-
-
-
-
-
-
-
-
Read/Reset
(*1)
4
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XXF0
RA
RD
-
-
-
-
Write
program
4
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XXA0
PA
(even)
PD
(word)
-
-
-
-
Chip Erase
6
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX80
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX10
Sector Erase
6
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX80
FxAAAA
XXAA
Fx5554
XX55
SA
(even)
XX30
Sector Erase Suspend
Sector Erase Restart
Auto-select
3
FxAAA
Entering address FxXXXX data (xxB0H) suspends erasing during sector erase.
Entering address FxXXXX data (xx30H) restarts erasing after erasing is suspended during sector erase.
XXAAA
Fx5554
XX55
FxAAAA
XX90
-
-
-
-
-
-
Note:
•
The addresses Fx in the table mean FF and FE for 1M-bit flash memory, FF, FE, FD and FC
for 2M-bit flash memory. Use these addresses as the access target bank values for
operations.
•
The addresses in the table are the values in the CPU memory map. All addresses and data
are represented using hexadecimal notation. However, the letter X is an optional value.
•
RA: Read address
•
PA: Write address. Only even addresses can be specified.
•
SA: Sector address. See Section 23.2 "Sector Configuration of the Flash Memory".
•
RD: Read data
•
PD: Write data. Only word data can be specified.
*1: Both of the two types of Read/Reset commands can reset the flash memory to read mode.
356
23.5 Starting the Flash Memory Automatic Algorithm
The Auto-select command shown in Table 23.5-1 "Command Sequence Table" is used to know
the state of sector protection. When using the Auto-select command, set the address as
follows.
Table 23.5-2 Address Setting at Auto-select
Sector protection
AQ13 to AQ16
AQ7
AQ2
AQ1
AQ0
DQ7 to DQ0
Sector Address
L
H
L
L
CODE*
*: When the sector address is protected, the output is "01H".
When the sector address is not protected, the output is "00H".
357
CHAPTER 23 1M/2M-BIT FLASH MEMORY
23.6 Confirming the Automatic Algorithm Execution State
Because the write/erase flow of the flash memory is controlled using the automatic
algorithm, the flash memory has hardware for posting its internal operating state and
completion of operation. This automatic algorithm enables confirmation of the
operating state of the built-in flash memory using the following hardware sequences.
■ Hardware Sequence Flags
The hardware sequence flags are configured from the four-bit output of DQ7, DQ6, DQ5, DQ3
and DQ2. The functions of these bits are those of the data polling flag (DQ7), toggle bit flag
(DQ6), timing limit exceeded flag (DQ5), sector erase timer flag (DQ3) and toggle bit 2 flag
(DQ2). The hardware sequence flags can therefore be used to confirm that writing or chip
sector erase has been completed or that erase code write is valid.
The hardware sequence flags can be accessed by read-accessing the addresses of the target
sectors in the flash memory after setting of the command sequence (see Table 23.5-1
"Command Sequence Table" in Section 23.5 "Starting the Flash Memory Automatic Algorithm".
Table 23.6-1 "Bit Assignments of Hardware Sequence Flags" lists the bit assignments of the
hardware sequence flags.
Table 23.6-1 Bit Assignments of Hardware Sequence Flags
Bit No.
Hardware sequence flag
7
6
5
4
3
2
1
0
DQ7
DQ6
DQ5
-
DQ3
DQ2
-
-
To determine whether automatic writing or chip sector erase is being executed, the hardware
sequence flags can be checked or the status can be determined from the RDY bit of the flash
memory control register (FMCS) that indicates whether writing has been completed. After
writing/erasing has terminated, the state returns to the read/reset state. When creating a
program, use one of the flags to confirm that automatic writing/erasing has terminated. Then,
perform the next processing operation, such as data read. In addition, the hardware sequence
flags can be used to confirm whether the second or subsequent sector erase code write is valid.
The following sections describe each hardware sequence flag separately. Table 23.6-2
"Hardware Sequence Flag Functions" lists the functions of the hardware sequence flags.
358
23.6 Confirming the Automatic Algorithm Execution State
Table 23.6-2 Hardware Sequence Flag Functions
State
State
change for
normal
operation
Abnormal
operation
Write --> Write completed (write
address specified)
Chip/sector erase --> Erase
completed
DQ7
DQ7 -->
DATA:7
DQ6
Toggle -->
DATA:6
DQ5
DQ3
DQ2
0 -->
DATA:5
0 -->
DATA:3
1 -->
DATA:2
0 --> 1
Toggle -->
Stop
0 --> 1
1
Toggle -->
Stop
Sector erase wait --> Erase started
0
Toggle
0
0 --> 1
Toggle
Erase --> Sector erase suspended
(sector being erased)
0 --> 1
Toggle -->
1
0
1 --> 0
Toggle
Sector erase suspend --> Erase
restarted (sector being erased)
1 --> 0
1 -->
Toggle
0
0 --> 1
Toggle
Sector erase suspended (sector not
being erased)
DATA:7
DATA:6
DATA:5
DATA:3
DATA:2
DQ7
Toggle
1
0
1
0
Toggle
1
1
*1
Write
Chip/sector erase
*1: If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2 to
toggle. DQ2 does not toggle when the successive reads are executed from other sectors.
359
CHAPTER 23 1M/2M-BIT FLASH MEMORY
23.6.1 Data Polling Flag (DQ7)
The data polling flag (DQ7) uses the data polling function to post that the automatic
algorithm is being executed or has terminated
■ Data Polling Flag (DQ7)
Table 23.6-3 "Data Polling Flag State Transitions (State Change for Normal Operation)" and
Table 23.6-4 "Data Polling Flag State Transitions (State Change for Abnormal Operation)" list
the state transitions of the data polling flag.
Table 23.6-3 Data Polling Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
DQ7
DQ7 -->
DATA:7
Chip/sector
erase -->
Completed
Sector
erase wait
--> Started
Sector erase
--> Erase
suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
0 --> 1
0
0 --> 1
1 --> 0
DATA:7
Table 23.6-4 Data Polling Flag State Transitions (State Change for Abnormal Operation)
Operating
state
Write
Chip/sector
erase
DQ7
DQ7
0
❍ Write
Read-access during execution of the automatic write algorithm causes the flash memory to
output the opposite data of bit 7 last written, regardless of the value at the address specified by
the address signal. Read-access at the end of the automatic write algorithm causes the flash
memory to output bit 7 of the read value of the address specified by the address signal.
❍ Chip/sector erase
For a sector erase, read-access during execution of the chip erase/sector erase algorithm
causes the flash memory to output 0 from the sector currently being erased. For a chip erase,
read-access causes the flash memory to output 0 regardless of the value at the address
specified by the address signal. Read-access at the end of the automatic write algorithm
causes the flash memory to output 1 in the same way.
❍ Sector erase suspend
Read-access during a sector erase suspend causes the flash memory to output 1 if the address
specified by the address signal belongs to the sector being erased. The flash memory outputs
bit 7 (DATA: 7) of the read value at the address specified by the address signal if the address
specified by the address signal does not belong to the sector being erased. Referencing this
flag together with the toggle bit flag (DQ6) enables a decision to be made on whether the flash
memory is in the erase suspended state and which sector is being erased.
360
23.6 Confirming the Automatic Algorithm Execution State
Note:
When the automatic algorithm is being started, read-access to the specified address is
ignored. Since termination of the data polling flag (DQ7) can be accepted for a data read
and other bits output, data read after the automatic algorithm has terminated should be
performed after read-access has confirmed that data polling has terminated.
361
CHAPTER 23 1M/2M-BIT FLASH MEMORY
23.6.2 Toggle Bit Flag (DQ6)
Like the data polling flag (DQ7), the toggle bit flag (DQ6) uses the toggle bit function to
post that the automatic algorithm is being executed or has terminated.
■ Toggle Bit Flag (DQ6)
Table 23.6-5 "Toggle Bit Flag State Transitions (State Change for Normal Operation)" and Table
23.6-6 "Toggle Bit Flag State Transitions (State Change for Abnormal Operation)" list the state
transitions of the toggle bit flag.
Table 23.6-5 Toggle Bit Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
Chip/sector
erase -->
Completed
DQ6
Toggle -->
DATA:6
Toggle -->
Stop
Sector
erase wait
--> Started
Sector erase
--> Erase
suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
Toggle
Toggle --> 1
1 --> Toggle
DATA:6
Table 23.6-6 Toggle Bit Flag State Transitions (State Change for Abnormal Operation)
Operating
state
Write
Chip/sector
erase
DQ6
Toggle
Toggle
❍ Write/chip sector erase
Continuous read-access during execution of the automatic write algorithm and chip/sector erase
algorithm causes the flash memory to toggle the 1 or 0 state for every read cycle, regardless of
the value at the address specified by the address signal. Continuous read-access at the end of
the automatic write algorithm and chip/sector erase algorithm causes the flash memory to stop
toggling bit 6 and output bit 6 (DATA: 6) of the read value of the address specified by the
address signal.
❍ Sector erase suspend
Read-access during a sector erase suspend causes the flash memory to output 1 if the address
specified by the address signal belongs to the sector being erased. The flash memory outputs
bit 6 (DATA: 6) of the read value at the address specified by the address signal if the address
specified by the address signal does not belong to the sector being erased.
Note:
For a write, if the sector where data is to be written is rewrite-protected, the toggle bit
terminates the toggle operation after approximately 2μs without any data being rewritten.
For an erase, if all of the selected sectors are write-protected, the toggle bit performs
toggling for approximately 100μs and then returns to the read/reset state without any data
being rewritten.
362
23.6 Confirming the Automatic Algorithm Execution State
23.6.3 Timing Limit Exceeded Flag (DQ5)
The timing limit exceeded flag (DQ5) is used to post that execution of the automatic
algorithm has exceeded the time (internal pulse count) prescribed in the flash memory.
■ Timing Limit Exceeded Flag (DQ5)
Table 23.6-7 "Timing Limit Exceeded Flag State Transitions (State Change for Normal
Operation") and Table 23.6-8 "Timing Limit Exceeded Bit Flag State Transitions (State Change
for Abnormal Operation)" list the state transitions of the timing limit exceeded flag.
Table 23.6-7 Timing Limit Exceeded Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
DQ5
0 -->
DATA:5
Chip/sector
erase -->
Completed
Sector
erase wait
--> Started
Sector erase
--> Erase
suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
0 --> 1
0
0
0
DATA:5
Table 23.6-8 Timing Limit Exceeded Bit Flag State Transitions (State Change for
Abnormal Operation)
Operating
state
Write
Chip/sector
erase
DQ5
1
1
❍ Write/chip sector erase
Read-access after write or chip/sector erase automatic algorithm activation causes the flash
memory to output 0 if the time is within the prescribed time (time required for write/erase) or to
output 1 if the prescribed time has been exceeded. Because this is done regardless of whether
the automatic algorithm is being executed or has terminated, it is possible to determine whether
write/erase was successful or unsuccessful. That is, when this flag outputs 1, writing can be
determined to have been unsuccessful if the automatic algorithm is still being executed by the
data polling function or toggle bit function.
For example, writing 1 to a flash memory address where 0 has been written will cause the fail
state to occur. In this case, the flash memory will lock and execution of the automatic algorithm
will not terminate. As a result, valid data will not be output from the data polling flag (DQ7). In
addition, the toggle bit flag (DQ6) will exceed the time limit without stopping the toggle operation
and the timing limit exceeded flag (DQ5) will output 1. Note that this state indicates that the
flash memory is not faulty, but has been used correctly. When this state occurs, execute the
Reset command.
363
CHAPTER 23 1M/2M-BIT FLASH MEMORY
23.6.4 Sector Erase Timer Flag (DQ3)
The sector erase timer flag (DQ3) is used to post whether the automatic algorithm is
being executed during the sector erase wait period after the Sector Erase command
has been started.
■ Sector Erase Timer Flag (DQ3)
Table 23.6-9 "Sector Erase Timer Flag State Transitions (State Change for Normal Operation)"
and Table 23.6-10 "Sector Erase Timer Flag State Transitions (State Change for Abnormal
Operation)" list the state transitions of the sector erase timer flag.
Table 23.6-9 Sector Erase Timer Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
DQ3
0 -->
DATA:3
Chip/sector
erase -->
Completed
Sector
erase wait
--> Started
Sector erase
--> Erase
suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
1
0 --> 1
1 --> 0
0 --> 1
DATA:3
Table 23.6-10 Sector Erase Timer Flag State Transitions (State Change for Abnormal
Operation)
Operating
state
Write
Chip/sector
erase
DQ3
0
1
❍ Sector erase
Read-access after the Sector Erase command has been started causes the flash memory to
output 0 if the automatic algorithm is being executed during the sector erase wait period,
regardless of the value at the address specified by the address signal of the sector that issued
the command. The flash memory outputs 1 if the sector erase wait period has been exceeded.
If the data polling function or toggle bit function indicates that the erase algorithm is being
executed, internally controlled erase has already started if this flag is 1. Continuous write of the
sector erase codes or commands other than the Sector Erase Suspend command will be
ignored until erase is terminated.
If this flag is 0, the flash memory will accept write of additional sector erase codes. To confirm
this, it is recommended that the state of this flag be checked before continuing to write sector
erase codes. If this flag is 1 after the second state check, it is possible that additional sector
erase codes may not be accepted.
364
23.6 Confirming the Automatic Algorithm Execution State
❍ Sector erase
Read-access during execution of sector erase suspend causes the flash memory to output 1 if
the address specified by the address signal belongs to the sector being erased. The flash
memory outputs bit 3 (DATA: 3) of the read value of the address specified by the address
signal if the address specified by the address signal does not belong to the sector being erased.
365
CHAPTER 23 1M/2M-BIT FLASH MEMORY
23.6.5 Toggle Bit 2 Flag (DQ2)
The toggle bit 2 flag (DQ2) is a flag that uses the toggle bit function to indicate that the
sector is in the erase-suspended state.
■ Toggle Bit 2 Flag (DQ2)
Table 23.6-11 "Toggle Bit 2 Flag State Transitions (State Change for Normal Operation)" and
Table 23.6-12 "Toggle Bit 2 Flag State Transitions (State Change for Abnormal Operation)" list
the state transitions of the toggle bit flag.
Table 23.6-11 Toggle Bit 2 Flag State Transitions (State Change for Normal Operation)
Operating
state
Write -->
Completed
Chip/sector
erase -->
Completed
DQ2
1 -->
DATA:2
Toggle -->
Stop
Sector
erase wait
--> Started
Sector erase
--> Erase
suspend
(sector being
erased)
Sector erase
suspend -->
Restarted
(sector being
erased)
Sector erase
suspended
(sector not
being erased)
Toggle
Toggle
Toggle
DATA:2
Table 23.6-12 Toggle Bit 2 Flag State Transitions (State Change for Abnormal Operation)
Operating
state
Write
Chip/sector
erase
DQ2
1
*1
*1: If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2
to toggle. DQ2 does not toggle when the successive reads are executed from other sectors.
❍ During a sector erase operation
If successive reads are executed during the execution of the chip sector erase algorithm, a flash
memory toggles to output "1" and "0" to addresses alternately at every read access regardless
of the location indicated by the addresses. If successive reads are executed after the chip
sector erase algorithm is completed, the flash memory stops the toggle operation of the bit 2
and outputs the read value of the bit 2 (DATA: 2) to the location indicated by the address.
366
23.6 Confirming the Automatic Algorithm Execution State
❍ While a sector erase operation is suspended
If successive reads are executed while a sector erase operation is suspended, and if the
address indicates the sector to be erased, the flash memory toggles to alternately output "1"
and "0". If the address indicates the sector is not to be erased, the flash memory outputs the
read value of the bit 2 (DATA: 2) to the location indicated by the address.
In the erase-suspend-program mode, successive reads from the non-erase suspended sector
causes the flash memory to output "1".
Both DQ2 and DQ6 are used for detecting an erase-suspended sector (DQ2 toggles, but DQ6
does not).
DQ2 is also used for detecting an erasing sector. While erasing a sector, if a read access is
executed from the erasing sector, DQ2 toggles.
Reference:
If all sectors selected for erasing are write-protected, the toggle bit 2 toggles for about 100μs,
and then returns to the read/reset mode without writing the data.
367
CHAPTER 23 1M/2M-BIT FLASH MEMORY
23.7 Detailed Explanation of Writing to and Erasing Flash
Memory
This section describes each operation procedure of flash memory Read/Reset, Write,
Chip Erase, Sector Erase, Sector Erase Suspend, and Sector Erase Restart when a
command that starts the automatic algorithm is issued.
■ Detailed Explanation of Flash Memory Write/Erase
The flash memory executes the automatic algorithm by issuing a command sequence (see
Table 23.5-1 "Command Sequence Table" in Section 23.5 "Starting the Flash Memory
Automatic Algorithm") for a write cycle to the bus to perform Read/Reset, Write, Chip Erase,
Sector Erase, Sector Erase Suspend, or Sector Erase Restart operations. Each bus write cycle
must be performed continuously. In addition, whether the automatic algorithm has terminated
can be determined using the data polling or other function. At normal termination, the flash
memory is returned to the read/reset state.
Each operation of the flash memory is described in the following order:
368
•
Setting the read/reset state
•
Writing data
•
Erasing all data (erasing chips)
•
Erasing optional data (erasing sectors)
•
Suspending sector erase
•
Restarting sector erase
23.7 Detailed Explanation of Writing to and Erasing Flash Memory
23.7.1 Setting The Read/Reset State
This section describes the procedure for issuing the Read/Reset command to set the
flash memory to the read/reset state.
■ Setting the Flash Memory to the Read/Reset State
The flash memory can be set to the read/reset state by sending the Read/Reset command in
the command sequence table (see Table 23.5-1 "Command Sequence Table" in Section 23.5
"Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash
memory.
The Read/Reset command has two types of command sequences that execute the first and
third bus operations. However, there are no essential differences between these command
sequences.
The read/reset state is the initial state of the flash memory. When the power is turned on and
when a command terminates normally, the flash memory is set to the read/reset state. In the
read/reset state, other commands wait for input.
In the read/reset state, data is read by regular read-access. As with the mask ROM, program
access from the CPU is enabled. The Read/Reset command is not required to read data by a
regular read. The Read/Reset command is mainly used to initialize the automatic algorithm in
such cases as when a command does not terminate normally.
369
CHAPTER 23 1M/2M-BIT FLASH MEMORY
23.7.2 Writing Data
This section describes the procedure for issuing the Write command to write data to
the flash memory.
■ Writing Data to the Flash Memory
The data write automatic algorithm of the flash memory can be started by sending the Write
command in the command sequence table (see Table 23.5-1 "Command Sequence Table" in
Section 23.5 "Starting the Flash Memory Automatic Algorithm") continuously to the target sector
in the flash memory. When data write to the target address is completed in the fourth cycle, the
automatic algorithm and automatic write are started.
❍ Specifying addresses
Only even addresses can be specified as the write addresses specified in a write data cycle.
Odd addresses cannot be written correctly. That is, writing to even addresses must be done in
units of word data.
Writing can be done in any order of addresses or even if the sector boundary is exceeded.
However, the Write command writes only data of one word for each execution.
❍ Notes on writing data
Writing cannot return data 0 to data 1. When data 1 is written to data 0, the data polling
algorithm (DQ7) or toggle operation (DQ6) does not terminate and the flash memory elements
are determined to be faulty. If the time prescribed for writing is thus exceeded, the timing limit
exceeded flag (DQ5) is determined to be an error. Otherwise, the data is viewed as if dummy
data 1 had been written. However, when data is read in the read/reset state, the data remains
0. Data 0 can be set to data 1 only by erase operations.
All commands are ignored during execution of the automatic write algorithm. If a hardware
reset is started during writing, the data of the written addresses will be unpredictable.
■ Writing to the Flash Memory
Figure 23.7-1 "Example of the Flash Memory Write Procedure" is an example of the procedure
for writing to the flash memory. The hardware sequence flags (see Section 23.6 "Confirming
the Automatic Algorithm Execution State") can be used to determine the state of the automatic
algorithm in the flash memory. Here, the data polling flag (DQ7) is used to confirm that writing
has terminated.
The data read to check the flag is read from the address written to last.
The data polling flag (DQ7) changes at the same time that the timing limit exceeded flag (DQ5)
changes. For example, even if the timing limit exceeded flag (DQ5) is 1, the data polling flag bit
(DQ7) must be rechecked.
Also for the toggle bit flag (DQ6), the toggle operation stops at the same time that the timing
limit exceeded flag bit (DQ5) changes to 1. The toggle bit flag (DQ6) must therefore be
rechecked.
370
23.7 Detailed Explanation of Writing to and Erasing Flash Memory
Figure 23.7-1 Example of the Flash Memory Write Procedure
Start writing
FMCS: WE (bit 5)
Enable flash memory write
Write command sequence
(1) FxAAAA <-- XXAA
(2) Fx5554 <-- XX55
(3) FxAAAA <-- XXA0
(4) Write address <-- Write data
Read internal address
Data polling (DQ7)
Next address
Data
Data
0
Timing limit (DQ5)
1
Read internal address
Data
Data polling (DQ7)
Data
Write error
Final address
FMCS: WE (bit 5)
Disable flash memory write
Complete writing
Confirm with the hardware
sequence flags.
371
CHAPTER 23 1M/2M-BIT FLASH MEMORY
23.7.3 Erasing All Data (Erasing Chips)
This section describes the procedure for issuing the Chip Erase command to erase all
data in the flash memory.
■ Erasing all Data in the Flash Memory (Erasing Chips)
All data can be erased from the flash memory by sending the Chip Erase command in the
command sequence table (see Table 23.5-1 "Command Sequence Table" in Section 23.5
"Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash
memory.
The Chip Erase command is executed in six bus operations. When writing of the sixth cycle is
completed, the chip erase operation is started. For chip erase, the user need not write to the
flash memory before erasing. During execution of the automatic erase algorithm, the flash
memory writes 0 for verification before all of the cells are erased automatically.
372
23.7 Detailed Explanation of Writing to and Erasing Flash Memory
23.7.4 Erasing Optional Data (Erasing Sectors)
This section describes the procedure for issuing the Sector Erase command to erase
optional data (erase sector) in the flash memory. Individual sectors can be erased.
Multiple sectors can also be specified at one time.
■ Erasing Optional Data (Erasing Sectors) in the Flash Memory
Optional sectors in the flash memory can be erased by sending the Sector Erase command in
the command sequence table (see Table 23.5-1 "Command Sequence Table" in Section 23.5
"Starting the Flash Memory Automatic Algorithm") continuously to the target sector in the flash
memory.
❍ Specifying sectors
The Sector Erase command is executed in six bus operations. Sector erase wait of 50μs is
started by writing the sector erase code (30h) to an accessible even-numbered address in the
target sector in the sixth cycle. To erase multiple sectors, write the erase code (30h) to the
addresses in the target sectors after the above processing operation.
❍ Notes on specifying multiple sectors
Erase is started when the sector erase wait period of 50μs terminates after the final sector erase
code has been written. That is, to erase multiple sectors at one time, an erase code (sixth cycle
of the command sequence) must be written within 50μs of writing of the address of a sector and
the address of the next sector must be written within 50μs of writing of the previous erase code.
Otherwise, the address and erase code may not be accepted. The sector erase timer
(hardware sequence flag DQ3) can be used to check whether writing of the subsequent sector
erase code is valid. At this time, specify so that the address used for reading the sector erase
timer indicates the sector to be erased.
■ Erasing Sectors in the Flash Memory
The hardware sequence flags (see Section 23.6 "Confirming the Automatic Algorithm Execution
State") can be used to determine the state of the automatic algorithm in the flash memory.
Figure 23.7-2 "Example of the Flash Memory Sector Erase Procedure" is an example of the
procedure for erasing sectors in the flash memory. Here, the toggle bit flag (DQ6) is used to
confirm that erasing has terminated.
The data that is read to check the flag is read from the sector to be erased.
The toggle bit flag (DQ6) stops the toggle operation at the same time that the timing limit
exceeded flag (DQ5) is changed to 1. For example, even if the timing limit exceeded flag (DQ5)
is 1, the toggle bit flag (DQ6) must be rechecked.
The data polling flag (DQ7) also changes at the same time that the timing limit exceeded flag bit
(DQ5) changes. As a result, the data polling flag (DQ7) must be rechecked.
373
CHAPTER 23 1M/2M-BIT FLASH MEMORY
Figure 23.7-2 Example of the Flash Memory Sector Erase Procedure
Start erasing
FMCS: WE (bit 5)
Enable flash memory erase
Erase command sequence
(1) FxAAAA <-- XXAA
(2) Fx5554 <-- XX55
(3) FxAAAA <-- XX80
(4) Fx5554 <-- XX55
(5) Sector address <-Erase code (30H)
1
Sector erase timer (DQ3)
Read internal address
0
(6) Sector address <-Erase code (30H)
Y
Another erase sector
N
Read internal address 1
Next sector
Read internal address 2
Toggle bit (DQ6)
data 1(DQ6) = data 2(DQ6)
Y
N
0
Timing limit (DQ5)
1
Read internal address 1
Read internal address 2
N
Toggle bit (DQ6)
data 1(DQ6) = data 2(DQ6)
Y
Erase error
Final sector
N
Y
FMCS: WE (bit 5)
Disable flash memory erase
Confirm with the hardware
sequence flags.
Complete erasing
374
23.7 Detailed Explanation of Writing to and Erasing Flash Memory
23.7.5 Suspending Sector Erase
This section describes the procedure for issuing the Sector Erase Suspend command
to suspend erasing of flash memory sectors. Data can be read from sectors that are
not being erased.
■ Suspending Erasing of Flash Memory Sectors
Erasing of flash memory sectors can be suspended by sending the Sector Erase Suspend
command in the command sequence table (see Table 23.5-1 "Command Sequence Table" in
Section 23.5 "Starting the Flash Memory Automatic Algorithm") continuously to the target sector
in the flash memory.
The Sector Erase Suspend command suspends the sector erase operation being executed and
enables data to be read from sectors that are not being erased. In this state, only reading is
enabled; data cannot be written. This command is valid only during sector erase operations that
include the erase wait time. The command will be ignored during chip erase or write operations.
This command is implemented by writing the erase suspend code (B0h). At this time, specify
an optional address in the flash memory for the address. An Erase Suspend command issued
again during erasing of sectors will be ignored.
Entering the Sector Erase Suspend command during the sector erase wait period will
immediately terminate sector erase wait, cancel the erase operation, and set the erase stop
state. Entering the Erase Suspend command during the erase operation after the sector erase
wait period has terminated will set the erase suspend state after a maximum period of 15μs has
elapsed.
375
CHAPTER 23 1M/2M-BIT FLASH MEMORY
23.7.6 Restarting Sector Erase
This section describes the procedure for issuing the Sector Erase Restart command to
restart suspended erasing of flash memory sectors.
■ Restarting Erasing of Flash Memory Sectors
Suspended erasing of flash memory sectors can be restarted by sending the Sector Erase
Restart command in the command sequence table (see Table 23.5-1 "Command Sequence
Table" in Section 23.5 "Starting the Flash Memory Automatic Algorithm") continuously to the
target sector in the flash memory.
The Sector Erase Restart command is used to restart erasing of sectors from the sector erase
suspend state set using the Sector Erase Suspend command. The Sector Erase Restart
command is implemented by writing the erase restart code (30h). At this time, specify an
optional address in the flash memory area for the address.
If a Sector Erase Restart command is issued during sector erase, the command will be ignored.
376
23.8 Notes on using 1M/2M-bit Flash Memory
23.8 Notes on using 1M/2M-bit Flash Memory
This section contains notes on using 1M/2M-bit flash memory.
■ Notes on using flash memory
❍ Input of a hardware reset (RST)
To input a hardware reset when the automatic algorithm has not been started and reading is in
progress, a minimum low-level width of 500 ns must be maintained. In this case, a maximum of
500 ns is required until data can be read from the flash memory after a hardware reset has been
activated.
Similarly, to input a hardware reset when the automatic algorithm has been activated and writing
or erasing is in progress, a minimum low-level width of 50 ns must be maintained. In this case,
20 μs are required until data can be read after the operation for initializing the flash memory has
terminated.
A hardware reset during writing the data being written to be undefined. A hardware reset during
erasing may make the sector being erased unusable.
❍ Canceling of a software reset, watchdog timer reset, and hardware standby
When the flash memory is being written to or erased with CPU access and if reset conditions
occur while the automatic algorithm is active, the CPU may run out of control. This occurs
because these reset conditions cause the automatic algorithm to continue without initializing the
flash memory unit, possibly preventing the flash memory unit from entering the read state when
the CPU starts the sequence after the reset has been deasserted. These reset conditions must
be disabled during writing to or erasing of the flash memory.
❍ Program access to flash memory
When the automatic algorithm is operating, read access to the flash memory is disabled. With
the memory access mode of the CPU set to internal ROM mode, writing or erasing must be
started after the program area is switched to another area such as RAM. In this case, when
sectors (SA4/SA6) containing interrupt vectors are erased, writing or erasing interrupt
processing cannot be executed. For the same reason, all interrupt sources other than the flash
memory are disabled while the automatic algorithm is operating.
Also, while the automatic algorithm is being executed, all interrupt sources except flash memory
are disabled.
❍ Hold function
When the CPU accepts a hold request, the Write signal WE of the flash memory unit may be
skewed, causing erroneous writing or erasing due to an erroneous write. When the acceptance
of a hold request is enabled (HDE bit of EPCR set to 1), ensure that the WE bit of the control
status register (FMCS) is 0.
❍ Extended intelligent I/O service (EI2OS)
Because write and erase interrupts issued to the CPU from the flash memory interface circuit
cannot be accepted by the EI2OS, they should not be used.
377
CHAPTER 23 1M/2M-BIT FLASH MEMORY
❍ Applying VID
Applying VID required for the sector protect operation should always be started and terminated
when the supply voltage is on.
378
23.9 Flash Security Feature
23.9 Flash Security Feature
The Flash security Controller provides possibilities to protect the content of the flash
memory from being read from external pins.
■ Flash Security Feature
One predefined address of the flash memory is assigned to the Flash Security Controller (1M-bit
flash memory: FE0001, 2M-bit flash memory: FC0001). If the protection code of "01H" is written
is this address, access to the flash memory is restricted. Once the flash memory is protected,
performing the chip erase operation only can unlock the function otherwise read/write access to
the flash memory from any external pins is not generally possible.
This function is suitable for applications requiring security of self-containing and data stored in
the flash memory. If the target application requires any part of program to locate outside the
microcontroller, the Flash Security Controller can not offer the intended features. For this
reason, the External Vector Fetch mode should not be used when the protection code is set.
In order to re-program the once protected flash memory, the chip erase operation should be
performed.
379
CHAPTER 23 1M/2M-BIT FLASH MEMORY
23.10 Example of Programming 1M/2M-bit Flash Memory
This section presents a programming example of 1M/2M-bit flash memory.
■ Programming example of 1M/2M-bit flash memory
NAME
FLASHWE
TITLE FLASHWE
;------------------------------------------------------------------------------;1M/2M-bit-FLASH sample program
;
;1: Transmits the program (address: FFC000H, sector: SA4/SA6) from FLASH to RAM
;
(address: 000700H).
;2: Executes the program on RAM.
;3: Writes the PDR1 value to FLASH (address: FE0000H, sector: SA0/SA2).
;4: Reads the written value (address: FD0000H, sector: SA0/SA2) and outputs it to PDR2.
;5: Erases the written sector (SA0/SA2).
;6: Checks and outputs erase data.
;Conditions
; - Number of bytes transmitted to RAM: 100H (256B)
; - Write/erase termination judgment
;
Judgment according to DQ5 (timing limit excess flag)
;
Judgment according to DQ6 (toggle bit flag)
;
Judgment according to RDY (FMCS)
; - Error handling
;
Hi output to P00 to P07
;
Reset command issuance
;------------------------------------------------------------------;
RESOUS IOSEG
ABS=00
;"RESOUS" I/O segment definition
ORG
0000H
PDR0
RB
1
PDR1
RB
1
PDR2
RB
1
PDR3
RB
1
ORG
0010H
DDR0
RB
1
DDR1
RB
1
DDR2
RB
1
DDR3
RB
1
ORG
00A1H
CKSCR
RB
1
ORG
00AEH
FMCS
RB
1
ORG
006FH
ROMM
RB
1
RESOUS ENDS
;
SSTA
SSEG
RW
0127H
STA_T
RW
1
SSTA
ENDS
;
DATA
DSEG
ABS=0FFH
;FLASH command address
ORG
5554H
COMADR2 RW
1
ORG
0AAAAH
COMADR1 RW
1
DATA
ENDS
380
23.10 Example of Programming 1M/2M-bit Flash Memory
;/////////////////////////////////////////////////////////////
;Main program (SAI)
;/////////////////////////////////////////////////////////////
CODE
CSEG
START:
;/////////////////////////////////////////////////////
; Initialization
;/////////////////////////////////////////////////////
MOV
CKSCR,#0BAH
;3-multiple setting
MOV
RP,#0
MOV
A,#!STA_T
MOV
SSB,A
MOVW
A,#STA_T
MOVW
SP,A
MOV
ROMM,#00H
;Mirror OFF
MOV
PDR0,#00H
;For error check
MOV
DDR0,#0FFH
MOV
PDR1,#00H
;Port for data input
MOV
DDR1,#00H
MOV
PDR2,#00H
;Port for data output
MOV
DDR2,#0FFH
;
//////////////////////////////////////////////////////////////
;
Transfer of "FLASH write erase program (FFC000H)" to RAM (700H address)
;
//////////////////////////////////////////////////////////////
MOVW
A,#0700H
;Transfer destination RAM area
MOVW
A,#0C000H
;Transfer source address (program position)
MOVW
RW0,#100H
;Number of bytes to be transferred
MOVS
ADB,PCB
;Transfer of 100H from FFBC00H to 00700H
CALLP
000700H
;Jump to the address containing the transferred
;
program
;
/////////////////////////////////////////////////////
;
Data output
;
/////////////////////////////////////////////////////
OUT
MOV
A,#0FEH
MOV
ADB,A
MOVW
RW2,#0000H
MOVW
A,@RW2+00
MOV
PDR2,A
END
JMP
*
CODE
ENDS
;////////////////////////////////////////////////////////////
;FLASH write erase program (SA4/SA6)
;////////////////////////////////////////////////////////////
RAMPRG CSEG
ABS=0FFH
ORG
0C000H
;
////////////////////////////////////////////
Initialization
;
////////////////////////////////////////////
MOVW
RW0,#0500H
;RW0:RAM space for input data acquisition 00:0500 to
MOVW
RW2,#0000H
;RW2:Flash memory write address
FD:0000 to
MOV
A,#00H
;DTB modification
MOV
DTB,A
;Bank specification for @RW0
MOV
A,#0FDH
;ADB modification 1
MOV
ADB,A
;Bank specification for write mode specification
;
address
MOV
PDR3,#00H
;Switch initialization
MOV
DDR3,#00H
;
WAIT1
BBC
PDR3:0,WAIT1
;PDR3: 0(write start at high level)
;
;////////////////////////////////////////////////
;Write (SA0/SA2)
;////////////////////////////////////////////////
MOV
A,PDR1
MOVW
@RW0+00,A
;PDR1 data allocation to RAM
MOV
FMCS,#20H
;Write mode setting
MOVW
ADB:COMADR1,#00AAH
;Flash write command 1
MOVW
ADB:COMADR2,#0055H
;Flash write command 2
381
CHAPTER 23 1M/2M-BIT FLASH MEMORY
MOVW
ADB:COMADR1,#00A0H
;Flash write command 3
;
WRITE
;
;
;
;
;
;
;
;
NTOW
;
;
;
MOVW
A,@RW0+00
;Input data (RW0) write to flash memory (RW2)
MOVW
@RW2+00,A
;Wait time check
///////////////////////////////////////////////////////////////////
ERROR when the time limit excess check flag is set and toggle operation is
in progress
///////////////////////////////////////////////////////////////////
MOVW
A,@RW2+00
AND
A,#20H
;DQ5 time limit check
BZ
NTOW
;Time limit over
MOVW
A,@RW2+00
;AH
MOVW
A,@RW2+00
;AL
XORW
A
;XOR of AH and AL (1 when the values differ)
AND
A,#40H
;Is the DQ6 toggle bit different?
BNZ
ERROR
;To ERROR when the DQ6 toggle bit is different
///////////////////////////////////////
Write termination check (FMCS-RDY)
///////////////////////////////////////
///////////////////////////////////////
MOVW
A,FMCS
AND
A,#10H
;Extraction of FMCS RDY bit (bit 4)
BZ
WRITE
;End of write?
MOV
FMCS,#00H
;Write mode release
/////////////////////////////////////////////////////
Write data output
/////////////////////////////////////////////////////
MOVW
RW2,#0000H
;Write data output
MOVW
A,@RW2+00
MOV
PDR2,A
;
WAIT2
BBC
PDR3:1,WAIT2
;PDR3: 1(sector erase start at high level)
;
;/////////////////////////////////////////////
;Sector erase (SA0/SA2)
;/////////////////////////////////////////////
MOV
@RW2+00,#0000H
;Address initialization
MOV
FMCS,#20H
;Erase mode setting
MOVW
ADB:COMADR1,#00AAH
;Flash erase command 1
MOVW
ADB:COMADR2,#0055H
;Flash erase command 2
MOVW
ADB:COMADR1,#0080H
;Flash erase command 3
MOVW
ADB:COMADR1,#00AAH
;Flash erase command 4
MOVW
ADB:COMADR2,#0055H
;Flash erase command 5
MOV
@RW2+00,#0030H
;Issuance of erase command 6 to the sector
to be erased
ELS
;Wait time check
;
///////////////////////////////////////////////////////////////////
;
ERROR when the time limit excess check flag is set and toggle operation is
;
in progress
;
///////////////////////////////////////////////////////////////////
MOVW
A,@RW2+00
AND
A,#20H
;DQ5 time limit check
BZ
NTOE
;Time limit over
MOVW
A,@RW2+00
;AH High and Low are alternately output from
MOVW
A,@RW2+00
;AL DQ6 per read during write operation.
XORW
A
;XOR of AH and AL (If the DQ6 value differs,
;
write operation is in progress (1)).
AND
A,#40H
;Is the DQ6 toggle bit High?
BNZ
ERROR
;ERROR when the DQ6 toggle bit is High
;
///////////////////////////////////////
;
Erase termination check (FMCS-RDY)
;
///////////////////////////////////////
NTOE
MOVW
A,FMCS
;
AND
A,#10H
;Extraction of FMCS RDY bit (bit 4)
BZ
ELS
;End of sector erase?
MOV
FMCS,#00H
;FLASH erase mode release
RETP
;Return to the main program
382
23.10 Example of Programming 1M/2M-bit Flash Memory
;//////////////////////////////////////////////
;Error
;//////////////////////////////////////////////
ERROR
MOV
ADB:COMADR1,#0F0H
;Reset command (read is enabled)
MOV
FMCS,#00H
;FLASH mode release
MOV
PDR0,#0FFH
;Error handling check
RETP
;Return to the main program
RAMPRG ENDS
;/////////////////////////////////////////////
VECT
CSEG
ABS=0FFH
ORG
0FFDCH
DSL
START
DB
00H
VECT
ENDS
;
END
START
383
CHAPTER 23 1M/2M-BIT FLASH MEMORY
384
CHAPTER 24
EXAMPLES OF MB90F438L(S)/F439(S)
SERIAL PROGRAMMING CONNECTION
This chapter provides examples of serial programming connection with the AF220/
AF210/AF120/AF110 flash microcomputer programmer manufactured by Yokogawa
Digital Computer Corporation.
24.1 "Basic Configuration of MB90F438L(S)/F439(S) Serial Programming
Connection"
24.2 "Example of Serial Programming Connection (User Power Supply Used)"
24.3 "Example of Serial Programming Connection (Power Supplied from the
Programmer)"
24.4 "Example of Minimum Connection to the Flash Microcomputer
Programmer (User Power Supply Used)"
24.5 "Example of Minimum Connection to the Flash Microcomputer
Programmer (Power Supplied from the Programmer)"
385
CHAPTER 24 EXAMPLES OF MB90F438L(S)/F439(S) SERIAL PROGRAMMING CONNECTION
24.1 Basic Configuration of MB90F438L(S)/F439(S) Serial
Programming Connection
The MB90F438L(S)/F439(S) supports flash ROM serial on-board programming (Fujitsu
standard). This section describes the specifications.
■ Basic Configuration of MB90F438L(S)/F439(S) Serial Programming Connection
The AF220/AF210/AF120/AF110 flash microcomputer programmer manufactured by Yokogawa
Digital Computer Corporation is used for Fujitsu standard serial on-board programming. Figure
24.1-1 "Basic Configuration of MB90F438L(S)/F439(S) Serial Programming Connection" shows
the basic configuration of the MB90F438L(S)/F439(S) serial programming connection.
Figure 24.1-1 Basic Configuration of MB90F438L(S)/F439(S) Serial Programming Connection
Host interface cable
RS232C
General-purpose
common cable (AZ210)
AF220/AF210/
AF120/AF110
flash
microcomputer
programmer
+
memory card
CLK synchronous
serial
MB90F438L(S)/F439(S)
user system
Stand-alone operation enabled
Note:
Ask Yokogawa Digital Computer Corporation for information about the functions and
operations of the AF220/AF210/AF120/AF110 flash microcomputer programmer, generalpurpose common cable (AZ210) for connection, and connectors.
386
24.1 Basic Configuration of MB90F438L(S)/F439(S) Serial Programming Connection
Table 24.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming
Pin
Function
Additional information
MD2, MD1
MD0
Mode pins
Controls programming mode from the flash microcomputer
programmer.
X0, X1
Oscillation pins
In programming mode, the CPU internal operation clock signal is
one multiple of the PLL clock signal frequency. Therefore,
because the oscillation clock frequency becomes the internal
operation clock signal.
P00, P01
Programming activation pins
-
RST
Reset pin
-
SIN1
Serial data input pin
SOT1
Serial data output pin
SCK1
Serial clock input pin
C
C pin
This external capacitor pin is used to stabilize the power supply.
Connect a ceramic capacitor of approximately 0.1μF to the
outside.
VCC
Power voltage supply pin
If the programming voltage (5 V 10%) is supplied from the user
system, the flash microcomputer programmer need not be
connected. Connect so that the power supply of the user side is
not short-circuited.
VSS
GND pin
Common to the ground of the flash microcomputer programmer.
HST
Hardware standby pin
Input high level during serial programming mode.
The UART1 is used in CLK synchronous mode.
Even if the P00, SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit
shown in the figure below is required. (The /TICS signal of the flash microcomputer
programmer can be used to disconnect the user circuit during serial programming).
Figure 24.1-2 Control Circuit
AF220/AF210/AF120/AF110
write control pin
MB90F438L(S)/F439(S)
write control pin
10K
AF220/AF210/AF120/AF110/
TICS pin
User
Sections 24.2 "Example of Serial Programming Connection (User Power Supply Used)" to 24.5
"Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied
from the Programmer)" present examples the following four types of serial programming
connection. See each Section as required.
•
Serial programming connection in MB90F438L(S)/F439(S) internal vector mode (user power
supply used)
•
Serial programming connection in MB90F438L(S)/F439(S) internal vector mode (power
supplied from the Programmer)
•
Example of minimum connection to the flash microcomputer programmer (user power supply
used)
•
Example of minimum connection to the flash microcomputer programmer (power supplied
from the Programmer)
387
CHAPTER 24 EXAMPLES OF MB90F438L(S)/F439(S) SERIAL PROGRAMMING CONNECTION
Table 24.1-2 Flash Microcomputer Programmer System Configuration (Manufactured by
Yokogawa Digital Computer Corporation)
Model
Mainframe
Function
AF220/AC4P
Model with Ethernet interface built in / 100 to 220 V power
adaptor
AF210/AC4P
Standard model / 100V to 220 V power adaptor
AF120/AC4P
Single-key Ethernet interface model / 100V to 220 V power
adaptor
AF110/AC4P
Single-key model/100V to 220 V power adaptor
AZ221
PC/AT RS232C cable only for Programmer
AZ210
Standard target probe (a), length: 1 m
FF201
Fujitsu F2MC-16LX flash microcomputer control model
AZ290
Remote controller
/P2
2 MB PC card (option) for flash memory sizes of up to 128 KB
/P4
4 MB PC card (option) for flash memory sizes of up to 512 KB
Inquiries: Yokogawa Digital Computer Corporation
Telephone number: (81)-42-333-6224
Note:
The AF200 flash microcomputer programmer, which is not supported now, can be used by
using control module FF201. For the serial programming connection information, see the
following section, "Oscillation Clock Frequency and Serial Clock Input Frequency".
388
24.1 Basic Configuration of MB90F438L(S)/F439(S) Serial Programming Connection
■ Oscillation Clock Frequency and Serial Clock Input Frequency
The formula shown below can be used to calculate the maximum serial clock frequency that can
be input to the MB90F438L(S)/F439(S).
Maximum serial clock frequency that can be input = 0.125 x oscillation clock frequency
Consequently, change the serial clock input frequency by setting the serial clock frequency of
the flash microcomputer programmer according to the current oscillation clock frequency.
Table 24.1-3 Examples of the Maximum Serial Clock Frequency That Can Be Input
Oscillation or
External clock
frequency
Maximum serial clock
frequency that can be
input for the
microcomputer
Maximum serial clock
frequency that can be
set with AF220/AF210/
AF120/AF110
Maximum serial clock
frequency that can be
set with AF200
4 MHz
500 kHz
500 kHz
500 kHz
8 MHz *1
1 MHz
850 kHz
500 kHz
16 MHz *1
2 MHz
1.25 MHz
500 kHz
*1: External clock only
389
CHAPTER 24 EXAMPLES OF MB90F438L(S)/F439(S) SERIAL PROGRAMMING CONNECTION
24.2 Example of Serial Programming Connection
(User Power Supply Used)
Figure 24.2-1 "Example of Serial Programming Connection for MB90F438L(S)/F439(S)
Single-chip Modes (User Power Supply Used)"shows an example of serial
programming connection when the microcomputer power voltage is supplied from the
user power supply. The values 1 and 0 are input to mode pins MD2 and MD0 from
TAUX3 and TMODE of the AF220/AF210/AF120/AF110 programmer.
Serial reprogramming mode: MD2, MD1, MD0 = 110
■ Example of Serial Programming Connection (User Power Supply Used)
Figure 24.2-1 Example of Serial Programming Connection for MB90F438L(S)/F439(S) Single-chip Modes
(User Power Supply Used)
AF220/AF210/AF120/AF110
flash microcomputer
programmer
TAUX3
User system
MB90F438L(S)/F439(S)
Connector
DX10-28S
(19)
MD2
MD1
TMODE
MD0
X0
(12)
X1
TAUX
(23)
TICS
(10)
P00
User
User
TRES
HST
RST
(5)
P01
C
User
TTXD
TRXD
TCK
(13)
(27)
(6)
TVcc
(2)
GND
(7,8,
14,15,
21, 22
1, 28)
SIN1
SOT1
SCK1
Vcc
User power
supply
Vss
Pin 14
Pins 3, 4, 9, 11, 16, 17, 18, 20,
24, 25, and 26 are open.
DX10-28S: Right-angle type
390
Pin 1
DX10-28S
Pin 28
Pin 15
Connector (Hirose Electronics Ltd.)
pin arrangement
24.2 Example of Serial Programming Connection (User Power Supply Used)
•
Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit
shown in the figure below is required in the same way that it is for P00. (The /TICS signal of
the flash microcomputer programmer can be used to disconnect the user circuit during serial
programming.)
AF220/AF210/AF120/AF110
write control pin
MB90F438L(S)/F439(S)
write control pin
10K
AF220/AF210/
AF120/AF110/TICS pin
User
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
391
CHAPTER 24 EXAMPLES OF MB90F438L(S)/F439(S) SERIAL PROGRAMMING CONNECTION
24.3 Example of Serial Programming Connection
(Power Supplied from the Programmer)
Figure 24.3-1 "Example of Serial Programming Connection for MB90F438L(S)/F439(S)
Single-chip Modes (Power Supplied from the Programmer) "shows an example of serial
programming connection when the microcomputer power voltage is supplied from the
programmer. The values 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and
TMODE of the AF220/AF210/AF120/AF110 programmer.
Serial reprogramming mode: MD2, MD1, MD0 = 110
■ Example of Serial Programming Connection (Power Supplied from the Programmer)
Figure 24.3-1 Example of Serial Programming Connection for MB90F438L(S)/F439(S) Single-chip Modes
(Power Supplied from the Programmer)
AF220/AF210/AF120/AF110
flash microcomputer
programmer
TAUX3
User system
MB90F438L(S)/F439(S)
Connector
DX10-28S
(19)
MD2
MD1
TMODE
MD0
X0
(12)
X1
TAUX
(23)
TICS
(10)
P00
User
User
TRES
HST
(5)
RST
P01
C
User
TTXD
TRXD
TCK
TVcc
Vcc
TVPP1
GND
(13)
(27)
(6)
(2)
(3)
(16)
SIN1
SOT1
SCK1
Vcc
(7, 8,
14,15,
21, 22
1, 28)
Pins 4, 9, 11, 17, 18, 20,
24, 25, and 26 are open.
Vss
Pin 14
Pin 1
Pin 28
Pin 15
DX10-28S
DX10-28S: Right-angle type
Connector (Hirose Electronics Ltd.)
pin arrangement
392
24.3 Example of Serial Programming Connection (Power Supplied from the Programmer)
•
Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit
shown in the figure below is required in the same way that it is for P00. (The /TICS signal of
the flash microcomputer programmer can be used to disconnect the user circuit during serial
programming.)
AF220/AF210/AF120/AF110
write control pin
MB90F438L(S)/F439(S)
write control pin
10K
AF220/AF210/
AF120/AF110/TICS pin
User
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
•
When the programming power is supplied from the AF220/AF210/AF120/AF110, be careful
not to short-circuit the user power supply.
393
CHAPTER 24 EXAMPLES OF MB90F438L(S)/F439(S) SERIAL PROGRAMMING CONNECTION
24.4 Example of Minimum Connection to the Flash
Microcomputer Programmer (User Power Supply Used)
Figure 24.4-1 "Example of Minimum Connection to the Flash Microcomputer
Programmer (User Power Supply Used)" is an example of the minimum connection to
the flash microcomputer programmer when the user power supply is used.
Serial reprogramming mode: MD2, MD1, MD0 = 110
■ Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used)
For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcomputer
programmer need not be connected if the pins are set as described below.
Figure 24.4-1 Example of Minimum Connection to the MB90F438L(S)/F439(S) Flash Microcomputer
Programmer (User Power Supply Used)
AF220/AF210/AF120/AF110 User system
flash microcomputer
1 for serial
reprogramming
programmer
MB90F438L(S)/F439(S)
MD2
1 for serial
reprogramming
MD1
MD0
0 for serial
reprogramming
X0
X1
P00
0 for serial
reprogramming
User circuit
P01
1 for serial reprogramming
User
circuit
Connector
DX10-28S
TRES
TTXD
TRXD
TCK
TVcc
(5)
(13)
(27)
(6)
(2)
GND
(7,8,
14,15,
21,22,
1,28)
RST
SIN1
SOT1
SCK1
Vcc
User power supply
Pins 3, 4, 9, 10, 11, 12, 16, 17, 18, 19,
20, 23, 24, 25, and 26 are open.
DX10-28S: Right-angle type
HST
C
Vss
Pin 14
Pin 1
Pin 28
Pin 15
DX10-28S
Connector (Hirose Electronics Ltd.)
pin arrangement
394
24.4 Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used)
•
Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit
shown in the figure below is required. (The /TICS signal of the flash microcomputer
programmer can be used to disconnect the user circuit during serial programming.)
AF220/AF210/AF120/AF110
write control pin
MB90F438L(S)/F439(S)
write control pin
10K
AF220/AF210/
AF120/AF110/TICS pin
User
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
395
CHAPTER 24 EXAMPLES OF MB90F438L(S)/F439(S) SERIAL PROGRAMMING CONNECTION
24.5 Example of Minimum Connection to the Flash
Microcomputer Programmer (Power Supplied from the
Programmer)
Figure 24.5-1 "Example of Minimum Connection to the Flash Microcomputer
Programmer (Power Supplied from the Programmer)" is an example of the minimum
connection to the flash microcomputer programmer when power is supplied from the
programmer.
Serial reprogramming mode: MD2, MD1, MD0 = 110
■ Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the
Programmer)
For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcomputer
programmer need not be connected if the pins are set as described below.
Figure 24.5-1 Example of Minimum Connection to the MB90F438L(S)/F439(S) Flash Microcomputer
Programmer (Power Supplied from the Programmer)
AF220/AF210/AF120/AF110 User system
flash microcomputer
1 for serial
programmer
reprogramming
MB90F438L(S)/F439(S)
MD2
1 for serial
reprogramming
MD1
MD0
0 for serial
reprogramming
X0
X1
P00
0 for serial
reprogramming
User circuit
P01
1 for serial reprogramming
User
circuit
Connector
DX10-28S
TRES
TTXD
TRXD
TCK
TVcc
Vu
TVPP1
GND
HST
C
(5)
(13)
(27)
(6)
(2)
(3)
(16)
RST
SIN1
SOT1
SCK1
(7,8,
14,15,
21,22,
1,28)
Vss
Pins 4, 9, 10, 11, 12, 17, 18, 19,
20, 23, 24, 25, and 26 are open.
DX10-28S: Right-angle type
Vcc
Pin 14
Pin 1
Pin 28
Pin 15
DX10-28S
Connector (Hirose Electronics Ltd.)
pin arrangement
396
24.5 Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Programmer)
•
Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit
shown in the figure below is required. (The /TICS signal of the flash microcomputer
programmer can be used to disconnect the user circuit during serial programming.)
AF220/AF210/AF120/AF110
write control pin
MB90F438L(S)/F439(S)
write control pin
10K
AF220/AF210/
AF120/AF110/TICS pin
User
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
•
When the programming power is supplied from the AF220/AF210/AF120/AF110, be careful
not to short-circuit the user power supply.
397
CHAPTER 24 EXAMPLES OF MB90F438L(S)/F439(S) SERIAL PROGRAMMING CONNECTION
398
APPENDIX
The appendix provides I/O maps and outlines instructions.
APPENDIX A "I/O Maps"
APPENDIX B "Instructions"
399
APPENDIX A I/O Maps
APPENDIX A I/O Maps
Table A-1 "I/O Map" lists addresses to be assigned to the registers in the peripheral
blocks.
■ I/O Maps
Table A-1 I/O Map
Address
Register
Abbrevia
-tion
Access
Resource
Initial value
000000H
Port 0 data register
PDR0
R/W
Port 0
XXXXXXXXB
000001H
Port 1 data register
PDR1
R/W
Port 1
XXXXXXXXB
000002H
Port 2 data register
PDR2
R/W
Port 2
XXXXXXXXB
000003H
Port 3 data register
PDR3
R/W
Port 3
XXXXXXXXB
000004H
Port 4 data register
PDR4
R/W
Port 4
XXXXXXXXB
000005H
Port 5 data register
PDR5
R/W
Port 5
XXXXXXXXB
000006H
Port 6 data register
PDR6
R/W
Port 6
XXXXXXXXB
000007H
Port 7 data register
PDR7
R/W
Port 7
XXXXXXXXB
000008H
Port 8 data register
PDR8
R/W
Port 8
XXXXXXXXB
000009H
Port 9 data register
PDR9
R/W
Port 9
XXXXXXXXB
00000AH
Port A data register
PDRA
R/W
Port A
-------XB
00000BH to
00000FH
Reserved
000010H
Port 0 direction register
DDR0
R/W
Port 0
00000000B
000011H
Port 1 direction register
DDR1
R/W
Port 1
00000000B
000012H
Port 2 direction register
DDR2
R/W
Port 2
00000000B
000013H
Port 3 direction register
DDR3
R/W
Port 3
00000000B
000014H
Port 4 direction register
DDR4
R/W
Port 4
00000000B
000015H
Port 5 direction register
DDR5
R/W
Port 5
00000000B
000016H
Port 6 direction register
DDR6
R/W
Port 6
00000000B
000017H
Port 7 direction register
DDR7
R/W
Port 7
00000000B
000018H
Port 8 direction register
DDR8
R/W
Port 8
00000000B
000019H
Port 9 direction register
DDR9
R/W
Port 9
--000000B
00001AH
Port A direction register
DDRA
R/W
Port A
-------0B
400
APPENDIX A I/O Maps
Table A-1 I/O Map (Continued)
Address
Register
Abbrevia
-tion
Access
Resource
Initial value
00001BH
Analog input enable register
ADER
R/W
Port 6, A/D
11111111B
00001CH
Port 0 pull-up control register
PUCR0
R/W
Port 0
00000000B
00001DH
Port 1 pull-up control register
PUCR1
R/W
Port 1
00000000B
00001EH
Port 2 pull-up control register
PUCR2
R/W
Port 2
00000000B
00001FH
Port 3 pull-up control register
PUCR3
R/W
Port 3
00000000B
000020H
Serial mode control register 0
UMC0
R/W
00000100B
000021H
Serial status register 0
USR0
R/W
00010000B
000022H
Serial input data register 0/serial
output data register 0
UIDR0/
UODR0
R/W
XXXXXXXXB
000023H
Rate and data register
URD0
R/W
0000000XB
000024H
Serial mode register 1
SMR1
R/W
00000000B
000025H
Serial control register 1
SCR1
R/W
00000100B
000026H
Serial input data register 1/serial
output data register 1
SIDR1/
SODR1
R/W
000027H
Serial status register
SSR1
R/W
00001-00B
000028H
UART1 prescaler control register
U1CDCR
R/W
0---1111B
000029H
Serial edge select register 1
SES1
R/W
------0B
00002AH
00002BH
00002CH
UART0
UART1
XXXXXXXXB
Use prohibited
Serial I/O prescaler
Serial mode control register
SCDCR
R/W
SMCS
R/W
Serial I/O
0---1111B
----0000B
00002DH
00000010B
00002EH
Serial data register
SDR
R/W
XXXXXXXXB
00002FH
Serial edge select register 2
SES2
R/W
-------0B
000030H
External Interrupt enable register
ENIR
R/W
00000000B
000031H
External Interrupt request register
EIRR
R/W
External interrupt level register
ELVR
R/W
000032H
DTP/external
interrupt
000033H
XXXXXXXXB
00000000B
00000000B
000034H
A/D control status register 0
ADCS0
R/W
00000000B
000035H
A/D control status register 1
ADCS1
R/W
000036H
A/D data register 0
ADCR0
R
XXXXXXXXB
000037H
A/D data register 1
ADCR1
R/W
00001-XXB
A/D converter
00000000B
401
APPENDIX A I/O Maps
Table A-1 I/O Map (Continued)
Address
Register
Abbrevia
-tion
Access
000038H
PPG0 operation mode control
register
PPGC0
R/W
000039H
PPG1 operation mode control
register
PPGC1
R/W
00003AH
PPG0/1 clock selection register
PPG01
R/W
00003BH
Resource
Initial value
0-000--1B
16-bit PPG
timer 0/1
0-000001B
000000--B
Reserved
00003CH
PPG2 operation mode control
register
PPGC2
R/W
00003DH
PPG3 operation mode control
register
PPGC3
R/W
00003EH
PPG2/3 clock selection register
PPG23
R/W
00003FH
0-000--1B
16-bit PPG
timer 2/3
0-000001B
000000--B
Use prohibited
000040H
PPG4 operation mode control
register
PPGC4
R/W
000041H
PPG5 operation mode control
register
PPGC5
R/W
000042H
PPG4/5 clock selection register
PPG45
R/W
000043H
0-000--1B
16-bit PPG
timer 4/5
0-000001B
000000--B
Use prohibited
000044H
PPG6 operation mode control
register
PPGC6
R/W
000045H
PPG7 operation mode control
register
PPGC7
R/W
000046H
PPG6/7 clock selection register
PPG67
R/W
000047H to
00004BH
0-000--1B
16-bit PPG
timer 6/7
0-000001B
000000--B
Use prohibited
00004CH
Input capture control status
register 0/1
ICS01
R/W
Input capture
0/1
00000000B
00004DH
Input capture control status
register 2/3
ICS23
R/W
Input capture
2/3
00000000B
00004EH
Input capture control status
register 4/5
ICS45
R/W
Input capture
4/5
00000000B
00004FH
Input capture control status
register 6/7
ICS67
R/W
Input capture
6/7
00000000B
TMCSR0
R/W
000050H
Timer control status register 0
000051H
000052H
000053H
402
Timer register 0/timer reload
register 0
TMR0/
TMRLR0
00000000B
16-bit reload
timer 0
R/W
----0000B
XXXXXXXXB
XXXXXXXXB
APPENDIX A I/O Maps
Table A-1 I/O Map (Continued)
Address
000054H
Register
Timer control status register 1
Abbrevia
-tion
Access
TMCSR1
R/W
000055H
000056H
000057H
Timer register 1/timer reload
register 1
TMR1/
TMRLR1
000058H
Output compare control register 0
000059H
Output compare control register 1
OCS1
00005AH
Output compare control register 2
OCS2
00005BH
Output compare control register 3
00006CH
R/W
OCS0
R/W
XXXXXXXXB
OCS3
Output
compare 0/1
0000--00B
Output
compare 2/3
0000--00B
---00000B
---00000B
Use prohibited
Timer counter data register
TCDT
00000000B
R/W
I/O timer
00006EH
Timer counter control status
register
00006FH
ROM mirror function selection
register
TCCS
ROMM
R/W
R/W
Address
match
detection
function
00000000B
Delayed
interrupt
generation
module
-------0B
000080H to
00008FH
Reserved
000090H to
00009DH
Use prohibited
PACSR
00000000B
-------1B
R/W
Reserved
Program address detection control
status register
00000000B
ROM mirror
function
selection
module
000070H to
00007FH
00009FH
Delayed interrupt/release register
DIRR
R/W
0000A0H
Low-power mode control register
LPMCR
R/W
0000A1H
Clock selection register
CKSCR
R/W
0000A2H to
0000A4H
----0000B
XXXXXXXXB
00006DH
00009EH
Initial value
00000000B
16-bit reload
timer 1
R/W
00005CH to
00006BH
Resource
Low-power
control circuit
00011000B
11111100B
Use prohibited
403
APPENDIX A I/O Maps
Table A-1 I/O Map (Continued)
Address
Register
Abbrevia
-tion
0000A5H
Automatic ready function selection
register
ARSR
0000A6H
External address output control
register
HACR
0000A7H
Bus control signal selection
register
ECSR
0000A8H
Watch-dog timer control register
WDTC
R/W
Watch-dog
timer
XXXXX111B
0000A9H
Time base timer control register
TBTC
R/W
Time base
timer
1--00100B
0000AAH
Watch timer control register
WTC
R/W
Watch timer
1X000000B
Flash memory
000X0000B
0000ABH to
0000ADH
0000AEH
Access
Resource
Initial value
0011--00B
W
External
memory
access
00000000B
0000000-B
Use prohibited
Flash memory control status
register (flash only, otherwise
reserved)
0000AFH
FMCS
R/W
Use prohibited
0000B0H
Interrupt control register 00
ICR00
R/W
00000111B
0000B1H
Interrupt control register 01
ICR01
R/W
00000111B
0000B2H
Interrupt control register 02
ICR02
R/W
00000111B
0000B3H
Interrupt control register 03
ICR03
R/W
00000111B
0000B4H
Interrupt control register 04
ICR04
R/W
00000111B
0000B5H
Interrupt control register 05
ICR05
R/W
00000111B
0000B6H
Interrupt control register 06
ICR06
R/W
00000111B
0000B7H
Interrupt control register 07
ICR07
R/W
0000B8H
Interrupt control register 08
ICR08
R/W
0000B9H
Interrupt control register 09
ICR09
R/W
00000111B
0000BAH
Interrupt control register 10
ICR10
R/W
00000111B
0000BBH
Interrupt control register 11
ICR11
R/W
00000111B
0000BCH
Interrupt control register 12
ICR12
R/W
00000111B
0000BDH
Interrupt control register 13
ICR13
R/W
00000111B
0000BEH
Interrupt control register 14
ICR14
R/W
00000111B
0000BFH
Interrupt control register 15
ICR15
R/W
00000111B
0000C0H to
0000FFH
404
External area
Interrupt
controller
00000111B
00000111B
APPENDIX A I/O Maps
Table A-1 I/O Map (Continued)
Address
Register
Abbrevia
-tion
001FF0H
001FF1H
Resource
R/W
Program address detection
register 0
PADR0
001FF2H
R/W
Program address detection
register 1
PADR1
001FF5H
Initial value
XXXXXXXXB
R/W
R/W
001FF3H
001FF4H
Access
XXXXXXXXB
Address
match
detection
function
XXXXXXXXB
XXXXXXXXB
R/W
XXXXXXXXB
R/W
XXXXXXXXB
•
In the Initial value column, "0" indicates that the initial value is 0, "1" indicates that the initial value is 1, X
indicates that the initial value is undefined, and "-" indicates that the initial value is undefined (no value).
Note:
For bits to which values can be written, the values initialized by a reset are those written in the Initial value
column. These values are not read values.
The LPMCR/CKSCR/WDTC bits are not always be initialized by a reset. Whether they are initialized
depends on the reset type. The values initialized by a reset are listed in the Initial value column for these
registers.
• Free-running timer 2 is used for compare registers 0 to 3, and free-running timer 1 is used for 4 to 7. Freerunning timer 1 is also used for the input capture.
Table A-1 I/O Map (Continued)
Address
Register
Abbrevia
-tion
Access
Resource
Initial value
3900H
Reload register L
PRLL0
R/W
XXXXXXXXB
3901H
Reload register H
PRLH0
R/W
3902H
Reload register L
PRLL1
R/W
3903H
Reload register H
PRLH1
R/W
XXXXXXXXB
3904H
Reload register L
PRLL2
R/W
XXXXXXXXB
3905H
Reload register H
PRLH2
R/W
3906H
Reload register L
PRLL3
R/W
3907H
Reload register H
PRLH3
R/W
XXXXXXXXB
3908H
Reload register L
PRLL4
R/W
XXXXXXXXB
3909H
Reload register H
PRLH4
R/W
390AH
Reload register L
PRLL5
R/W
390BH
Reload register H
PRLH5
R/W
XXXXXXXXB
390CH
Reload register L
PRLL6
R/W
XXXXXXXXB
390DH
Reload register H
PRLH6
R/W
390EH
Reload register L
PRLL7
R/W
390FH
Reload register H
PRLH7
R/W
16-bit PPG
timer 0/1
16-bit PPG
timer 2/3
16-bit PPG
timer 4/5
16-bit PPG
timer 6/7
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
405
APPENDIX A I/O Maps
Table A-1 I/O Map (Continued)
Address
Register
3910H to
3917H
Abbrevia
-tion
Access
Initial value
Reserved
3918H
Input capture register 0
IPCP0
R
3919H
Input capture register 0
IPCP0
R
391AH
Input capture register 1
IPCP1
R
391BH
Input capture register 1
IPCP1
R
XXXXXXXXB
391CH
Input capture register 2
IPCP2
R
XXXXXXXXB
391DH
Input capture register 2
IPCP2
R
391EH
Input capture register 3
IPCP3
R
391FH
Input capture register 3
IPCP3
R
XXXXXXXXB
3920H
Input capture register 4
IPCP4
R
XXXXXXXXB
3921H
Input capture register 4
IPCP4
R
3922H
Input capture register 5
IPCP5
R
3923H
Input capture register 5
IPCP5
R
XXXXXXXXB
3924H
Input capture register 6
IPCP6
R
XXXXXXXXB
3925H
Input capture register 6
IPCP6
R
3926H
Input capture register 7
IPCP7
R
3927H
Input capture register 7
IPCP7
R
XXXXXXXXB
3928H
Output compare register 0
OCCP0
R/W
XXXXXXXXB
3929H
Output compare register 0
OCCP0
R/W
392AH
Output compare register 1
OCCP1
R/W
392BH
Output compare register 1
OCCP1
R/W
XXXXXXXXB
392CH
Output compare register 2
OCCP2
R/W
XXXXXXXXB
392DH
Output compare register 2
OCCP2
R/W
392EH
Output compare register 3
OCCP3
R/W
392FH
Output compare register 3
OCCP3
R/W
3930H to
39FFH
Reserved
3A00H to
3AFFH
Reserved
3B00H to
3BFFH
Reserved
406
Resource
XXXXXXXXB
Input capture
0/1
Input capture
2/3
Input capture
4/5
Input capture
6/7
Output
compare 0/1
Output
compare 2/3
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
APPENDIX A I/O Maps
Table A-1 I/O Map (Continued)
Address
Register
Abbrevia
-tion
Access
3C00H to
3CFFH
Reserved
3D00H to
3DFFH
Reserved
3E00H to
3FFFH
Reserved
Resource
Initial value
•
Explanation of write and read
R/W: Both read and write enabled
R: Only read enabled
W: Only write enabled
• Explanation of initial values
0: The initial value of this bit is 0.
1: The initial value of this bit is 1.
X: The initial value of this bit is undefined.
-: This bit is not used, and the initial value is undefined.
Note:
Do not access the reserved area in I/O map for a write. If the reserved area is read, the value is undefined.
407
APPENDIX B Instructions
APPENDIX B Instructions
APPENDIX B describes the instructions used by the F2MC-16LX.
B.1 Instruction Types
B.2 Addressing
B.3 Direct Addressing
B.4 Indirect Addressing
B.5 Execution Cycle Count
B.6 Effective address field
B.7 How to Read the Instruction List
B.8 F2MC-16LX Instruction List
B.9 Instruction Map
Code: CM44-00202-1E
408
APPENDIX B Instructions
B.1
Instruction Types
The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an
effective address field of each instruction or using the instruction code itself.
■
Instruction Types
The F2MC-16LX supports the following 351 types of instructions:
•
41 transfer instructions (byte)
•
38 transfer instructions (word or long word)
•
42 addition/subtraction instructions (byte, word, or long word)
•
12 increment/decrement instructions (byte, word, or long word)
•
11 comparison instructions (byte, word, or long word)
•
11 unsigned multiplication/division instructions (word or long word)
•
11 signed multiplication/division instructions (word or long word)
•
39 logic instructions (byte or word)
•
6 logic instructions (long word)
•
6 sign inversion instructions (byte or word)
•
1 normalization instruction (long word)
•
18 shift instructions (byte, word, or long word)
•
50 branch instructions
•
6 accumulator operation instructions (byte or word)
•
28 other control instructions (byte, word, or long word)
•
21 bit operation instructions
•
10 string instructions
409
APPENDIX B Instructions
B.2
Addressing
With the F2MC-16LX, the address format is determined by the instruction effective
address field or the instruction code itself (implied). When the address format is
determined by the instruction code itself, specify an address in accordance with the
instruction code used. Some instructions permit the user to select several types of
addressing.
■
Addressing
The F2MC-16LX supports the following 23 types of addressing:
410
•
Immediate (#imm)
•
Register direct
•
Direct branch address (addr16)
•
Physical direct branch address (addr24)
•
I/O direct (io)
•
Abbreviated direct address (dir)
•
Direct address (addr16)
•
I/O direct bit address (io:bp)
•
Abbreviated direct bit address (dir:bp)
•
Direct bit address (addr16:bp)
•
Vector address (#vct)
•
Register indirect (@RWj j = 0 to 3)
•
Register indirect with post increment (@RWj+ j = 0 to 3)
•
Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
•
Long register indirect with displacement (@RLi + disp8 i = 0 to 3)
•
Program counter indirect with displacement (@PC + disp16)
•
Register indirect with base index (@RW0 + RW7, @RW1 + RW7)
•
Program counter relative branch address (rel)
•
Register list (rlst)
•
Accumulator indirect (@A)
•
Accumulator indirect branch address (@A)
•
Indirectly-specified branch address (@ear)
•
Indirectly-specified branch address (@eam)
APPENDIX B Instructions
■
Effective Address Field
Table B.2-1 lists the address formats specified by the effective address field.
Table B.2-1 Effective Address Field
Code
Representation
00
R0
RW0
RL0
01
R1
RW1
(RL0)
02
R2
RW2
RL1
03
R3
RW3
(RL1)
04
R4
RW4
RL2
05
R5
RW5
(RL2)
06
R6
RW6
RL3
07
R7
RW7
(RL3)
08
@RW0
09
@RW1
Address format
Default bank
Register direct: Individual parts correspond to the
byte, word, and long word types in order from the
left.
None
DTB
DTB
Register indirect
0A
@RW2
ADB
0B
@RW3
SPB
0C
@RW0+
DTB
0D
@RW1+
DTB
Register indirect with post increment
0E
@RW2+
ADB
0F
@RW3+
SPB
10
@RW0+disp8
DTB
11
@RW1+disp8
DTB
Register indirect with 8-bit displacement
12
@RW2+disp8
ADB
13
@RW3+disp8
SPB
14
@RW4+disp8
DTB
15
@RW5+disp8
DTB
Register indirect with 8-bit displacement
16
@RW6+disp8
ADB
17
@RW7+disp8
SPB
18
@RW0+disp16
DTB
19
@RW1+disp16
DTB
Register indirect with 16-bit displacement
1A
@RW2+disp16
ADB
1B
@RW3+disp16
SPB
1C
@RW0+RW7
Register indirect with index
DTB
1D
@RW1+RW7
Register indirect with index
DTB
1E
@PC+disp16
PC indirect with 16-bit displacement
PCB
1F
addr16
Direct address
DTB
411
APPENDIX B Instructions
B.3
Direct Addressing
An operand value, register, or address is specified explicitly in direct addressing mode.
■
Direct Addressing
● Immediate addressing (#imm)
Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32).
Figure B.3-1 Example of Immediate Addressing (#imm)
MOVW A, #01212H (This instruction stores the operand value in A.)
Before execution
A 2233
4455
After execution
A 4455
1 2 1 2 (Some instructions transfer AL to AH.)
● Register direct addressing
Specify a register explicitly as an operand. Table B.3-1 lists the registers that can be specified. Figure B.3-2
shows an example of register direct addressing.
Table B.3-1 Direct Addressing Registers
General-purpose register
Special-purpose register
Byte
R0, R1, R2, R3, R4, R5, R6, R7
Word
RW0, RW1, RW2, RW3, RW4, RW5, RW6,
RW7
Long word
RL0, RL1, RL2, RL3
Accumulator
A, AL
Pointer
SP *
Bank
PCB, DTB, USB, SSB, ADB
Page
DPR
Control
PS, CCR, RP, ILM
*: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on
the value of the S flag bit in the condition code register (CCR). For branch instructions, the program
counter (PC) is not specified in an instruction operand but is specified implicitly.
412
APPENDIX B Instructions
Figure B.3-2 Example of Register Direct Addressing
MOV R0, A (This instruction transfers the eight low-order bits of A to the generalpurpose register R0.)
Before execution
A 0716
2534
Memory space
R0
After execution
A 0716
2564
??
Memory space
R0
34
● Direct branch addressing (addr16)
Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which
indicates the branch destination in the logical address space. Direct branch addressing is used for an
unconditional branch, subroutine call, or software interrupt instruction. Bit23 to bit16 of the address are
specified by the program counter bank register (PCB).
Figure B.3-3 Example of Direct Branch Addressing (addr16)
JMP 3B20H (This instruction causes an unconditional branch by direct branch
addressing in a bank.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
62
4F3C21H
20
4F3C22H
3B
JMP 3B20H
413
APPENDIX B Instructions
● Physical direct branch addressing (addr24)
Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical
direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction.
Figure B.3-4 Example of Direct Branch Addressing (addr24)
JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit
addressing.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 3 3
Memory space
333B20H
Next instruction
4F3C20H
63
4F3C21H
20
4F3C22H
3B
4F3C23H
33
JMPP 333B20H
● I/O direct addressing (io)
Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the
physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB)
and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an
instruction using I/O direct addressing.
Figure B.3-5 Example of I/O Direct Addressing (io)
MOVW A, i : 0C0H (This instruction reads data by I/O direct addressing and stores it
in A.)
Before execution
After execution
414
A 0716
2534
A 2534 FFEE
Memory space
0000C0H
EE
0000C1H
FF
APPENDIX B Instructions
● Abbreviated direct addressing (dir)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB).
Figure B.3-6 Example of Abbreviated Direct Addressing (dir)
MOV S : 20H, A (This instruction writes the contents of the eight low-order bits of A in
abbreviated direct addressing mode.)
Before execution
A 4455
DPR 6 6
After execution
A 4455
DPR 6 6
1212
DTB 7 7
Memory space
776620H
1212
DTB 7 7
??
Memory space
776620H
12
● Direct addressing (addr16)
Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are
specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for
this mode of addressing.
Figure B.3-7 Example of Direct Addressing (addr16)
MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.)
Before execution
After execution
A 2020
A AABB
AABB
0123
DTB 5 5
Memory space
553B21H
01
553B20H
23
DTB 5 5
415
APPENDIX B Instructions
● I/O direct bit addressing (io:bp)
Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp",
where the larger number indicates the most significant bit (MSB) and the lower number indicates the least
significant bit (LSB).
Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp)
SETB i : 0C1H : 0 (This instruction sets bits by I/O direct bit addressing.)
Memory space
Before execution
0000C1H
00
Memory space
After execution
0000C1H
01
● Abbreviated direct bit addressing (dir:bp)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure B.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp)
SETB S : 10H : 0 (This instruction sets bits by abbreviated direct bit addressing.)
Memory space
Before execution
DTB 5 5
DPR 6 6
556610H
00
Memory space
After execution
DTB 5 5
DPR 6 6
556610H
01
● Direct bit addressing (addr16:bp)
Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure B.3-10 Example of Direct Bit Addressing (addr16:bp)
SETB 2222H : 0 (This instruction sets bits by direct bit addressing.)
Memory space
Before execution
DTB 5 5
552222H
00
Memory space
After execution
416
DTB 5 5
552222H
01
APPENDIX B Instructions
● Vector Addressing (#vct)
Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector
numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction.
Figure B.3-11 Example of Vector Addressing (#vct)
CALLV #15 (This instruction causes a branch to the address indicated by the interrupt
vector specified in an operand.)
Before execution
PC 0 0 0 0
Memory space
PCB F F
After execution
FFC000H
EF
FFFFE0H
00
FFFFE1H
D0
CALLV #15
PC D 0 0 0
PCB F F
Table B.3-2 CALLV Vector List
Instruction
Vector address L
Vector address H
CALLV #0
XXFFFEH
XXFFFFH
CALLV #1
XXFFFCH
XXFFFDH
CALLV #2
XXFFFAH
XXFFFBH
CALLV #3
XXFFF8H
XXFFF9H
CALLV #4
XXFFF6H
XXFFF7H
CALLV #5
XXFFF4H
XXFFF5H
CALLV #6
XXFFF2H
XXFFF3H
CALLV #7
XXFFF0H
XXFFF1H
CALLV #8
XXFFEEH
XXFFEFH
CALLV #9
XXFFECH
XXFFEDH
CALLV #10
XXFFEAH
XXFFEBH
CALLV #11
XXFFE8H
XXFFE9H
CALLV #12
XXFFE6H
XXFFE7H
CALLV #13
XXFFE4H
XXFFE5H
CALLV #14
XXFFE2H
XXFFE3H
CALLV #15
XXFFE0H
XXFFE1H
Note: A PCB register value is set in XX.
Note:
When the program counter bank register (PCB) is FFH, the vector area overlaps the vector area of
INT #vct8 (#0 to #7). Use vector addressing carefully (see Table B.3-2).
417
APPENDIX B Instructions
B.4
Indirect Addressing
In indirect addressing mode, an address is specified indirectly by the address data of an
operand.
■
Indirect Addressing
● Register indirect addressing (@RWj j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to
23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register
(SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when
RW2 is used.
Figure B.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3)
MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores
it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 0 F
DTB 7 8
● Register indirect addressing with post increment (@RWj+ j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. After operand
operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word).
Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system
stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank
register (ADB) when RW2 is used.
If the post increment results in the address of the register that specifies the increment, the incremented
value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to
writing by an instruction and, therefore, the register that would be incremented becomes write data.
418
APPENDIX B Instructions
Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3)
MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post
increment and stores it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 1 1
DTB 7 8
● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
Memory is accessed using the address obtained by adding an offset to the contents of general-purpose
register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric
values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or
RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is
used, or additional data bank register (ADB) when RW2 or RW6 is used.
Figure B.4-3 Example of Register Indirect Addressing with Offset
(@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+10H)
RW1 D 3 0 F
After execution
DTB 7 8
Memory space
78D31FH
EE
78D320H
FF
A 2534 FFEE
RW1 D 3 0 F
DTB 7 8
419
APPENDIX B Instructions
● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the
contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value.
Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3)
MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+25H)
RL2 F 3 8 2
After execution
4B02
Memory space
824B27H
EE
824B28H
FF
A 2534 FFEE
RL2 F 3 8 2
4B02
● Program counter indirect addressing with offset (@PC + disp16)
Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one
word long. Address bits 16 to 23 are specified by the program counter bank register (PCB). Note that the
operand address of each of the following instructions is not deemed to be (next instruction address +
disp16):
•
DBNZ eam, rel
•
DWBNZ eam, rel
•
CBNE eam, #imm8, rel
•
CWBNE eam, #imm16, rel
•
MOV eam, #imm8
•
MOVW eam, #imm16
Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16)
MOVW A, @PC+20H (This instruction reads data by program counter indirect
addressing with an offset and stores it in A.)
Before execution
A 0716
2534
Memory space
PCB C 5 PC 4 5 5 6
After execution
A 2534
FFEE
PCB C 5 PC 4 5 5 A
420
+4
C54556H
73
C54557H
9E
C54558H
20
C54559H
00
C5455AH
.
.
.
+20H
C5457AH
EE
C5457BH
FF
MOVW
A, @PC+20H
APPENDIX B Instructions
● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7)
Memory is accessed using the address determined by adding RW0 or RW1 to the contents of generalpurpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB).
Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7)
MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with
a base index and stores it in A.)
Before execution
A 0716
RW1 D 3 0 F
WR7 0 1 0 1
After execution
A 2534
RW1 D 3 0 F
2534
+
DTB 7 8
Memory space
78D410H
EE
78D411H
FF
FFEE
DTB 7 8
WR7 0 1 0 1
421
APPENDIX B Instructions
● Program counter relative branch addressing (rel)
The address of the branch destination is a value determined by adding an 8-bit offset to the program
counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is
not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte
bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to
23 are indicated by the program counter bank register (PCB).
Figure B.4-7 Example of Program Counter Relative Branch Addressing (rel)
BRA 10H (This instruction causes an unconditional relative branch.)
Before execution
After execution
PC 3 C 2 0
PC 3 C 3 2
PCB 4 F
PCB 4 F
Memory space
4F3C32H
Next instruction
4F3C21H
10
4F3C20H
60
BRA 10H
● Register list (rlst)
Specify a register to be pushed onto or popped from a stack.
Figure B.4-8 Configuration of the Register List
MSB
LSB
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
A register is selected when the corresponding bit is 1 and deselected when the bit is 0.
422
APPENDIX B Instructions
Figure B.4-9 Example of Register List (rlist)
POPW, RW0, RW4 (This instruction transfers memory data indicated by the SP to
multiple word registers indicated by the register list.)
SP
34FA
SP
34FE
RW0
×× ××
RW0
02 01
RW1
×× ××
RW1
×× ××
RW2
×× ××
RW2
×× ××
RW3
×× ××
RW3
×× ××
RW4
×× ××
RW4
04 03
RW5
×× ××
RW5
×× ××
RW6
×× ××
RW6
×× ××
RW7
×× ××
RW7
×× ××
Memory space
SP
Memory space
01
34FAH
01
34FAH
02
34FBH
02
34FBH
03
34FCH
03
34FCH
04
34FDH
04
34FDH
34FEH
SP
Before execution
34FEH
After execution
● Accumulator indirect addressing (@A)
Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the
accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB).
Figure B.4-10 Example of Accumulator Indirect Addressing (@A)
MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.)
Before execution
A
0716
2534
DTB B B
After execution
A
0716
Memory space
BB2534H
EE
BB2535H
FF
FFEE
DTB B B
423
APPENDIX B Instructions
● Accumulator indirect branch addressing (@A)
The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the
accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are
specified by the program counter bank register (PCB). For the Jump Context (JCTX) instruction, however,
address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for
unconditional branch instructions.
Figure B.4-11 Example of Accumulator Indirect Branch Addressing (@A)
JMP @A (This instruction causes an unconditional branch by accumulator indirect
branch addressing.)
Before execution
PC 3 C 2 0
A 6677
After execution
PC 3 B 2 0
A 6677
PCB 4 F
3B20
Memory space
4F3B20H
Next instruction
4F3C20H
61
JMP @A
PCB 4 F
3B20
● Indirect specification branch addressing (@ear)
The address of the branch destination is the word data at the address indicated by ear.
Figure B.4-12 Example of Indirect Specification Branch Addressing (@ear)
JMP @@RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
After execution
PC 3 C 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
PC 3 B 2 0
RW0 7 F 4 8
424
PCB 4 F
DTB 2 1
Memory space
217F48H
20
217F49H
3B
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
08
JMP @@RW0
APPENDIX B Instructions
● Indirect specification branch addressing (@eam)
The address of the branch destination is the word data at the address indicated by eam.
Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam)
JMP @RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
PC 3 C 2 0
PCB 4 F
RW0 3 B 2 0
After execution
PC 3 B 2 0
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
00
JMP @RW0
RW0 3 B 2 0
425
APPENDIX B Instructions
B.5
Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is
obtained by adding the number of cycles required for each instruction, "correction
value" determined by the condition, and the number of cycles for instruction fetch.
■
Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is obtained by adding the
number of cycles required for each instruction, "correction value" determined by the condition, and the
number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal
ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments.
Therefore, intervening in data access increases the execution cycle count.
Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the
program fetches every byte of an instruction being executed. Therefore, intervening in data access increases
the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register,
internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the
cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register.
Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add
the "access count x cycle count for the halt" as a correction value to the normal execution count.
426
APPENDIX B Instructions
■
Calculating the Execution Cycle Count
Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data.
Table B.5-1 Execution Cycle Counts in Each Addressing Mode
(a) *
Code
Operand
00
|
07
Ri
Rwi
RLi
08
|
0B
Execution cycle count in
each addressing mode
Register access count in
each addressing mode
See the instruction list.
See the instruction list.
@RWj
2
1
0C
|
0F
@RWj+
4
2
10
|
17
@RWi+disp8
2
1
18
|
1B
@RWi+disp16
2
1
1C
1D
1E
1F
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
4
4
2
1
2
2
0
0
*: (a) is used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List".
427
APPENDIX B Instructions
Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles
(b) byte *
Operand
(c) word *
(d) long *
Cycle
count
Access
count
Cycle
count
Access
count
Cycle
count
Access
count
Internal register
+0
1
+0
1
+0
2
Internal memory
Even address
+0
1
+0
1
+0
2
Internal memory
Odd address
+0
1
+2
2
+4
4
External data bus
16-bit even address
+1
1
+1
1
+2
2
External data bus
16-bit odd address
+1
1
+4
2
+8
4
External data bus
8-bits
+1
1
+4
2
+8
4
*: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction
List".
Note:
When an external data bus is used, the cycle counts during which an instruction is made to wait by
ready input or automatic ready must also be added.
Table B.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
-
+2
External data bus 16-bits
-
+3
External data bus 8-bits
+3
-
Notes:
• When an external data bus is used, the cycle counts during which an instruction is made to wait
by ready input or automatic ready must also be added.
• Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the
correction values to calculate the worst case.
428
APPENDIX B Instructions
B.6
Effective address field
Table B.6-1 shows the effective address field.
■
Effective Address Field
Table B.6-1 Effective Address Field
Code
Representation
Address format
Byte count of
extended
address part *
Register direct: Individual parts correspond to
the byte, word, and long word types in order
from the left.
-
Register indirect
0
Register indirect with post increment
0
Register indirect with 8-bit displacement
1
Register indirect with 16-bit displacement
2
00
01
R0
R1
RW0
RW1
RL0
(RL0)
02
03
R2
R3
RW2
RW3
RL1
(RL1)
04
05
R4
R5
RW4
RW5
RL2
(RL2)
06
07
R6
R7
RW6
RW7
RL3
(RL3)
08
09
@RW0
@RW1
0A
0B
@RW2
@RW3
0C
0D
@RW0+
@RW1+
0E
0F
@RW2+
@RW3+
10
11
@RW0+disp8
@RW1+disp8
12
13
@RW2+disp8
@RW3+disp8
14
15
@RW4+disp8
@RW5+disp8
16
17
@RW6+disp8
@RW7+disp8
18
19
@RW0+disp16
@RW1+disp16
1A
1B
@RW2+disp16
@RW3+disp16
1C
1D
@RW0+RW7
@RW1+RW7
Register indirect with index
Register indirect with index
0
0
1E
1F
@PC+disp16
addr16
PC indirect with 16-bit displacement
Direct address
2
2
*1: Each byte count of the extended address part applies to + in the # (byte count) column in "B.8 F2MC-16LX
Instruction List".
429
APPENDIX B Instructions
B.7
How to Read the Instruction List
Table B.7-1 describes the items used in "B.8 F2MC-16LX Instruction List", and Table
B.7-2 describes the symbols used in the same list.
■
Description of Instruction Presentation Items and Symbols
Table B.7-1 Description of Items in the Instruction List (1/2)
Item
Mnemonic
Uppercase, symbol: Represented as is in the assembler.
Lowercase: Rewritten in the assembler.
Number of following lowercase: Indicates bit length in the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
See Table B.2-1 for the alphabetical letters in items.
RG
B
Operation
Indicates the number of times a register access is performed during instruction
execution.
The number is used to calculate the correction value for CPU intermittent
operation.
Indicates the correction value used to calculate the actual number of cycles during
instruction execution.
The actual number of cycles during instruction execution can be determined by
adding the value in the ~ column to this value.
Indicates the instruction operation.
LH
Indicates the special operation for bit15 to bit08 of the accumulator.
Z: Transfers 0.
X: Transfers after sign extension.
-: No transfer
AH
Indicates the special operation for the 16 high-order bits of the accumulator.
*: Transfers from AL to AH.
-: No transfer
Z: Transfers 00 to AH.
X: Transfers 00H or FFH to AH after AL sign extension.
I
S
T
N
Z
V
C
430
Description
Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N
(negative), Z (zero), V (overflow), C (carry).
*: Changes upon instruction execution.
-: No change
S: Set upon instruction execution.
R: Reset upon instruction execution.
APPENDIX B Instructions
Table B.7-1 Description of Items in the Instruction List (1/2)
Item
Description
RMW
Indicates whether the instruction is a Read Modify Write instruction (reading data
from memory by the I instruction and writing the result to memory).
*: Read Modify Write instruction
-: Not Read Modify Write instruction
Note:
Cannot be used for an address that has different meanings between read and
write operations.
Table B.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
A
Explanation
The bit length used varies depending on the 32-bit accumulator instruction.
Byte: Low-order 8 bits of byte AL
Word: 16 bits of word AL
Long word: 32 bits of AL and AH
AH
16 high-order bits of A
AL
16 low-order bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
program counter bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
Ri
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
Direct addressing
addr24
Physical direct addressing
ad24 0-15
Bit0 to bit15 of addr24
431
APPENDIX B Instructions
Table B.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
ad24 16-23
io
Bit16 to bit23 of addr24
I/O area (000000H to 0000FFH)
#imm4
4-bit immediate data
#imm8
8-bit immediate data
#imm16
16-bit immediate data
#imm32
32-bit immediate data
ext (imm8)
16-bit data obtained by sign extension of 8-bit immediate data
disp8
8-bit displacement
disp16
16-bit displacement
bp
432
Explanation
Bit offset
vct4
Vector number (0 to 15)
vct8
Vector number (0 to 255)
( )b
Bit address
rel
PC relative branch
ear
Effective addressing (code 00 to 07)
eam
Effective addressing (code 08 to 1F)
rlst
Register list
APPENDIX B Instructions
B.8
F2MC-16LX Instruction List
Table B.8-1 to Table B.8-18 list the instructions used by the F2MC-16LX.
■
F2MC-16LX Instruction List
Table B.8-1 41 Transfer Instructions (Byte)
Mnemonic
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
XCH
XCH
XCH
XCH
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RLi+disp8
A,#imm4
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
Ri,A
ear,A
eam,A
io,A
@RLi+disp8,A
Ri,ear
Ri,eam
ear,Ri
eam,Ri
Ri,#imm8
io,#imm8
dir,#imm8
ear,#imm8
eam,#imm8
@AL,AH
A,ear
A,eam
Ri,ear
Ri,eam
#
~
RG
B
2
3
1
2
2+
2
2
2
3
1
2
3
2
2
2+
2
2
2
2
3
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
2
2+
2
2+
3
4
2
2
3 + (a)
3
2
3
10
1
3
4
2
2
3 + (a)
3
2
3
5
10
3
4
2
2
3 + (a)
3
10
3
4 + (a)
4
5 + (a)
2
5
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
0
0
1
1
0
0
0
0
2
0
0
0
1
1
0
0
0
0
1
2
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
2
0
4
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
0
2 × (b)
0
2 × (b)
Operation
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi)+disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
Z
Z
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table.
433
APPENDIX B Instructions
Table B.8-2 38 Transfer Instructions (Word, Long Word)
Mnemonic
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW
XCHW
XCHW
MOVL
MOVL
MOVL
MOVL
MOVL
A,dir
A,addr16
A,SP
A,RWi
A,ear
A,eam
A,io
A,@A
A,#imm16
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
SP,A
RWi,A
ear,A
eam,A
io,A
@RWi+disp8,A
@RLi+disp8,A
RWi,ear
RWi,eam
ear,RWi
eam,RWi
RWi,#imm16
io,#imm16
ear,#imm16
eam,#imm16
@AL,AH
A,ear
A,eam
RWi, ear
RWi, eam
A,ear
A,eam
A,#imm32
ear,A
eam,A
#
~
RG
B
2
3
1
1
2
2+
2
2
3
2
3
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
2
2
2+
2
2+
2
2+
5
2
2+
3
4
1
2
2
3 + (a)
3
3
2
5
10
3
4
1
2
2
3 + (a)
3
5
10
3
4 + (a)
4
5 + (a)
2
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
4
5 + (a)
3
4
5 + (a)
0
0
0
1
1
0
0
0
0
1
2
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
0
2
0
4
2
2
0
0
2
0
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
0
(c)
0
(c)
0
(c)
0
(c)
(c)
0
2 × (c)
0
2 × (c)
0
(d)
0
0
(d)
Operation
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi)+disp8)
word (A) ← ((RLi)+disp8)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
word ((RWi)+disp8) ← (A)
word ((RLi)+disp8) ← (A)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
word (ear) ← imm16
word (eam) ← imm16
word ((A)) ← (AH)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
long (ear) ← (A)
long(eam) ← (A)
LH
AH
I
S
T
N
Z
V
C
RMW
-
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a), (c), and (d) in the table.
434
APPENDIX B Instructions
Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
ADDW
ADDW
ADDW
ADDW
ADDW
ADDW
ADDCW
ADDCW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBCW
SUBCW
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A,ear
A,eam
A,#imm32
A,ear
A,eam
A,#imm32
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
2+
5
2
2+
5
2
3
4+(a)
2
3
5+(a)
3
4+(a)
2
3
4+(a)
2
3
5+(a)
3
4+(a)
6
7+(a)
4
6
7+(a)
4
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
2
0
0
2
0
0
0
0
(c)
0
0
2 × (c)
0
(c)
0
0
(c)
0
0
2 × (c)
0
(c)
0
(d)
0
0
(d)
0
Operation
byte (A) ← (A) + imm8
byte (A) ← (A) + (dir)
byte (A) ← (A) + (ear)
byte (A) ← (A) + (eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear)+ (C)
byte (A) ← (A) + (eam)+ (C)
byte (A) ← (AH) + (AL) + (C)
(decimal)
byte (A) ← (A) - imm8
byte (A) ← (A) - (dir)
byte (A) ← (A) - (ear)
byte (A) ← (A) - (eam)
byte (ear) ← (ear) - (A)
byte (eam) ← (eam) - (A)
byte (A) ← (AH) - (AL) - (C)
byte (A) ← (A) - (ear) - (C)
byte (A) ← (A) - (eam) - (C)
byte (A) ← (AH) - (AL) - (C)
(decimal)
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) - (AL)
word (A) ← (A) - (ear)
word (A) ← (A) - (eam)
word (A) ← (A) - imm16
word (ear) ← (ear) - (A)
word (eam) ← (eam) - (A)
word (A) ← (A) - (ear) - (C)
word (A) ← (A) - (eam) - (C)
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
long (A) ← (A) - (ear)
long (A) ← (A) - (eam)
long (A) ← (A) - imm32
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
435
APPENDIX B Instructions
Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word)
#
~
RG
B
INC
Mnemonic
ear
2
3
2
0
INC
eam
2+
5+(a)
0
2 × (b)
DEC
ear
2
3
2
0
DEC
eam
2+
5+(a)
0
2 × (b)
INCW
ear
2
3
2
0
INCW
eam
2+
5+(a)
0
2 × (c)
DECW
ear
2
3
2
0
DECW
eam
2+
5+(a)
0
2 × (c)
INCL
ear
2
7
4
0
INCL
eam
2+
9+(a)
0
2 × (d)
DECL
ear
2
7
4
0
DECL
eam
2+
9+(a)
0
2 × (d)
LH
AH
I
S
T
N
Z
V
C
byte (ear) ← (ear) + 1
Operation
-
-
-
-
-
*
*
*
-
RMW
-
byte (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
byte (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
byte (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
word (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
word (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
word (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
word (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
I
S
T
N
Z
V
C
RMW
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
Table B.8-5 11 Compare Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
CMP
A
1
1
0
0
byte (AH) - (AL)
-
-
-
-
-
*
*
*
*
-
CMP
A,ear
2
2
1
0
byte (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMP
A,eam
2+
3+(a)
0
(b)
byte (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMP
A,#imm8
2
2
0
0
byte (A) - imm8
-
-
-
-
-
*
*
*
*
-
CMPW
A
1
1
0
0
word (AH) - (AL)
-
-
-
-
-
*
*
*
*
-
CMPW
A,ear
2
2
1
0
word (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPW
A,eam
2+
3+(a)
0
(c)
word (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPW
A,#imm16
3
2
0
0
word (A) - imm16
-
-
-
-
-
*
*
*
*
-
CMPL
A,ear
2
6
2
0
long (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPL
A,eam
2+
7+(a)
0
(d)
long (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPL
A,#imm32
5
3
0
0
long (A) - imm32
-
-
-
-
-
*
*
*
*
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
436
APPENDIX B Instructions
Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
DIVU
Mnemonic
A
1
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
Operation
-
-
-
-
-
-
-
*
*
-
DIVU
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
-
-
-
-
-
-
-
*
*
-
DIVU
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MULU
A
1
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A
1
*11
0
0
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,ear
2
*12
1
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,eam
2+
*13
0
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
*1: 3: Division by 0 7: Overflow 15: Normal
*2: 4: Division by 0 8: Overflow 16: Normal
*3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal
*4: 4: Division by 0 7: Overflow 22: Normal
*5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal
*6: (b): Division by 0 or overflow 2 × (b): Normal
*7: (c): Division by 0 or overflow 2 × (c): Normal
*8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0.
*9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0.
*10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0.
*11: 3: Word (AH) is 0. 11: Word (AH) is not 0.
*12: 4: Word (ear) is 0. 12: Word (ear) is not 0.
*13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0.
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
437
APPENDIX B Instructions
Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
DIV
Mnemonic
A
2
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
Operation
Z
-
-
-
-
-
-
*
*
-
DIV
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
Z
-
-
-
-
-
-
*
*
-
DIV
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
Z
-
-
-
-
-
-
*
*
-
DIVW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MUL
A
2
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
MULW
A
2
*11
0
0
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULW
A,ear
2
*12
1
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULW
A,eam
2+
*13
0
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
*1:
*2:
*3:
*4:
3: Division by 0, 8 or 18: Overflow, 18: Normal
4: Division by 0, 11 or 22: Overflow, 23: Normal
5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal
When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal
When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal
*5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal
When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal
*6: (b): Division by 0 or overflow, 2 × (b): Normal
*7: (c): Division by 0 or overflow, 2 × (c): Normal
*8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative
*9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative
*10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative
*11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative
*12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative
*13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative
Notes:
• The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a
pre-operation count or a post-operation count depending on the detection timing.
• When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed.
• See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
438
APPENDIX B Instructions
Table B.8-8 39 Logic 1 Instructions (Byte, Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
AND
A,#imm8
2
2
0
0
byte (A) ← (A) and imm8
-
-
-
-
-
*
*
R
-
RMW
-
AND
A,ear
2
3
1
0
byte (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
AND
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
AND
ear,A
2
3
2
0
byte (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
AND
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
OR
A,#imm8
2
2
0
0
byte (A) ← (A) or imm8
-
-
-
-
-
*
*
R
-
-
OR
A,ear
2
3
1
0
byte (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
OR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
OR
ear,A
2
3
2
0
byte (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
OR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XOR
A,#imm8
2
2
0
0
byte (A) ← (A) xor imm8
-
-
-
-
-
*
*
R
-
-
XOR
A,ear
2
3
1
0
byte (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XOR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XOR
ear,A
2
3
2
0
byte (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XOR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOT
A
1
2
0
0
byte (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOT
ear
2
3
2
0
byte (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOT
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
ANDW
A
1
2
0
0
word (A) ← (AH) and (A)
-
-
-
-
-
*
*
R
-
-
ANDW
A,#imm16
3
2
0
0
word (A) ← (A) and imm16
-
-
-
-
-
*
*
R
-
-
ANDW
A,ear
2
3
1
0
word (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
ANDW
ear,A
2
3
2
0
word (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
ANDW
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
ORW
A
1
2
0
0
word (A) ← (AH) or (A)
-
-
-
-
-
*
*
R
-
-
ORW
A,#imm16
3
2
0
0
word (A) ← (A) or imm16
-
-
-
-
-
*
*
R
-
-
ORW
A,ear
2
3
1
0
word (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
ORW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
ORW
ear,A
2
3
2
0
word (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
ORW
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XORW
A
1
2
0
0
word (A) ← (AH) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
A,#imm16
3
2
0
0
word (A) ← (A) xor imm16
-
-
-
-
-
*
*
R
-
-
XORW
A,ear
2
3
1
0
word (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XORW
ear,A
2
3
2
0
word (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOTW
A
1
2
0
0
word (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOTW
ear
2
3
2
0
word (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOTW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
439
APPENDIX B Instructions
Table B.8-9 6 Logic 2 Instructions (Long Word)
Mnemonic
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
ANDL
A,ear
2
6
2
0
long (A) ← (A) and (ear)
Operation
-
-
-
-
-
*
*
R
-
-
ANDL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
ORL
A,ear
2
6
2
0
long (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
ORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
XORL
A,ear
2
6
2
0
long (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (d) in the table.
Table B.8-10 6 Sign Inversion Instructions (Byte, Word)
Mnemonic
NEG
A
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
1
2
0
0
byte (A) ← 0 - (A)
X
-
-
-
-
*
*
*
*
-
byte (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
byte (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
word (A) ← 0 - (A)
-
-
-
-
-
*
*
*
*
-
word (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
word (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
NEG
ear
2
3
2
0
NEG
eam
2+
5+(a)
0
2 × (b)
NEGW
A
1
2
0
0
NEGW
ear
2
3
2
0
NEGW
eam
2+
5+(a)
0
2 × (c)
Operation
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
Table B.8-11 1 Normalization Instruction (Long Word)
Mnemonic
NRML
A,R0
#
~
RG
B
2
*1
1
0
Operation
long (A) ← Shift left to the position where '1' is set
for the first time.
byte (R0) ← Shift count at that time
*1: 4 when all accumulators have a value of 0; otherwise, 6+(R0)
440
LH
AH
I
S
T
N
Z
V
C
RMW
-
-
-
-
-
-
*
-
-
-
APPENDIX B Instructions
Table B.8-12 18 Shift Instructions (Byte, Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RORC
Mnemonic
A
2
2
0
0
byte (A) ← Right rotation with carry
Operation
-
-
-
-
-
*
*
-
*
RMW
-
ROLC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
ear
2
3
2
0
byte (ear) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
*
ROLC
ear
2
3
2
0
byte (ear) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
*
ASR
A,R0
2
*1
1
0
byte (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSR
A,R0
2
*1
1
0
byte (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSL
A,R0
2
*1
1
0
byte (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRW
A
1
2
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSRW
A/SHRW A
1
2
0
0
word (A) ← Logical right shift (A, 1 bit)
-
-
-
-
*
R
*
-
*
-
LSLW
A/SHLW A
1
2
0
0
word (A) ← Logical left shift (A, 1 bit)
-
-
-
-
-
*
*
-
*
-
ASRW
A,R0
2
*1
1
0
word (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRW
A,R0
2
*1
1
0
word (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLW
A,R0
2
*1
1
0
word (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRL
A,R0
2
*2
1
0
long (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRL
A,R0
2
*2
1
0
long (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLL
A,R0
2
*2
1
0
long (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
*1: 6 when R0 is 0; otherwise, 5 + (R0)
*2: 6 when R0 is 0; otherwise, 6 + (R0)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table.
441
APPENDIX B Instructions
Table B.8-13 31 Branch 1 Instructions
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
BZ/BEQ
Mnemonic
rel
2
*1
0
0
Branch on (Z) = 1
Operation
-
-
-
-
-
-
-
-
-
-
BNZ/
BNE
rel
2
*1
0
0
Branch on (Z) = 0
-
-
-
-
-
-
-
-
-
-
BC/BLO rel
2
*1
0
0
Branch on (C) = 1
-
-
-
-
-
-
-
-
-
-
BNC/
BHS
rel
2
*1
0
0
Branch on (C) = 0
-
-
-
-
-
-
-
-
-
-
BN
rel
2
*1
0
0
Branch on (N) = 1
-
-
-
-
-
-
-
-
-
-
BP
rel
2
*1
0
0
Branch on (N) = 0
-
-
-
-
-
-
-
-
-
-
BV
rel
2
*1
0
0
Branch on (V) = 1
-
-
-
-
-
-
-
-
-
-
BNV
rel
2
*1
0
0
Branch on (V) = 0
-
-
-
-
-
-
-
-
-
-
BT
rel
2
*1
0
0
Branch on (T) = 1
-
-
-
-
-
-
-
-
-
-
BNT
rel
2
*1
0
0
Branch on (T) = 0
-
-
-
-
-
-
-
-
-
-
BLT
rel
2
*1
0
0
Branch on (V) xor (N) = 1
-
-
-
-
-
-
-
-
-
-
BGE
rel
2
*1
0
0
Branch on (V) xor (N) = 0
-
-
-
-
-
-
-
-
-
-
BLE
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BGT
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BLS
rel
2
*1
0
0
Branch on (C) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BHI
rel
2
*1
0
0
Branch on (C) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BRA
rel
2
*1
0
0
Unconditional branch
-
-
-
-
-
-
-
-
-
-
JMP
@A
1
2
0
0
word (PC) ← (A)
-
-
-
-
-
-
-
-
-
-
JMP
addr16
3
3
0
0
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
JMP
@ear
2
3
1
0
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
JMP
@eam
2+
4+(a)
0
(c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
JMPP
@ear *3
2
5
2
0
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
JMPP
@eam *3
2+
6+(a)
0
(d)
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
JMPP
addr24
4
4
0
0
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
CALL
@ear *4
2
6
1
(c)
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
CALL
@eam *4
2+
7+(a)
0
2 × (c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
CALL
addr16 *5
3
6
0
(c)
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
CALLV
#vct4 *5
1
7
0
2 × (c)
Vector call instruction
-
-
-
-
-
-
-
-
-
-
CALLP
@ear *6
2
10
2
2 × (c)
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
CALLP
@eam *6
2+
11+(a)
0
*2
CALLP
addr24 *7
4
10
0
2 × (c)
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
*1: 4 when a branch is made; otherwise, 3
*2: 3 × (c) + (b)
*3: Read (word) of branch destination address
*4: W: Save to stack (word) R: Read (word) of branch destination address
*5: Save to stack (word)
*6: W: Save to stack (long word), R: Read (long word) of branch destination address
*7: Save to stack (long word)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
442
APPENDIX B Instructions
Table B.8-14 19 Branch 2 Instructions
Mnemonic
#
~
RG
B
LH
AH
I
S T N Z V C
CBNE
A,#imm8,rel
3
*1
0
0
Branch on byte (A) not equal to imm8
Operation
-
-
-
-
-
*
*
*
*
CWBNE
A,#imm16,rel
4
*1
0
0
Branch on word (A) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CBNE
ear,#imm8,rel
4
*2
1
0
Branch on byte (ear) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CBNE
eam,#imm8,rel *9
4+
*3
0
(b)
Branch on byte (eam) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
ear,#imm16,rel
5
*4
1
0
Branch on word (ear) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CWBNE
eam,#imm16,rel*9
5+
*3
0
(c)
Branch on word (eam) not equal to imm16
-
-
-
-
-
*
*
*
*
-
DBNZ
ear,rel
3
*5
2
0
byte (ear) ← (ear) - 1, Branch on (ear) not equal to 0
-
-
-
-
-
*
*
*
-
-
DBNZ
eam,rel
3+
*6
2
-
-
-
-
-
*
*
*
-
*
2 × (b) byte (eam) ← (eam) - 1, Branch on (eam) not equal to 0
word (ear) ← (ear) - 1, Branch on (ear) not equal to 0
-
DWBNZ
ear,rel
3
*5
2
-
-
-
-
-
*
*
*
-
-
DWBNZ
eam,rel
3+
*6
2
2 × (c) word (eam) ← (eam) - 1, Branch on (eam) not equal to 0
-
-
-
-
-
*
*
*
-
*
INT
#vct8
2
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT
addr16
3
16
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INTP
addr24
4
17
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT9
1
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
RETI
1
*8
0
*7
Return from interrupt
-
-
*
*
*
*
*
*
*
-
2
6
0
(c)
Saves the old frame pointer in the stack upon entering the
function, then sets the new frame pointer and reserves the
local pointer area.
-
-
-
-
-
-
-
-
-
-
1
5
0
(c)
Recovers the old frame pointer from the stack upon exiting
the function.
-
-
-
-
-
-
-
-
-
-
LINK
#imm8
UNLINK
0
RMW
RET
*10
1
4
0
(c)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
RETP
*11
1
6
0
(d)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
*1: 5 when a branch is made; otherwise, 4
*2: 13 when a branch is made; otherwise, 12
*3: 7+(a) when a branch is made; otherwise, 6+(a)
*4: 8 when a branch is made; otherwise, 7
*5: 7 when a branch is made; otherwise, 6
*6: 8+(a) when a branch is made; otherwise, 7+(a)
*7: 3 × (b) + 2 × (c) when jumping to the next interruption request; 6 × (c) when returning from the current interruption
*8: 15 when jumping to the next interruption request; 17 when returning from the current interruption
*9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction.
*10: Return from stack (word)
*11: Return from stack (long word)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
443
APPENDIX B Instructions
Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
PUSHW
Mnemonic
A
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (A)
Operation
-
-
-
-
-
-
-
-
-
-
PUSHW
AH
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (AH)
-
-
-
-
-
-
-
-
-
-
PUSHW
PS
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (PS)
-
-
-
-
-
-
-
-
-
-
PUSHW
rlst
2
*3
*5
*4
(SP) ← (SP) - 2n, ((SP)) ← (rlst)
-
-
-
-
-
-
-
-
-
-
POPW
A
1
3
0
(c)
word (A) ← ((SP)), (SP) ← (SP) + 2
-
*
-
-
-
-
-
-
-
-
POPW
AH
1
3
0
(c)
word (AH) ← ((SP)), (SP) ← (SP) + 2
-
-
-
-
-
-
-
-
-
-
POPW
PS
1
4
0
(c)
word (PS) ← ((SP)), (SP) ← (SP) + 2
-
-
*
*
*
*
*
*
*
-
POPW
rlst
2
*2
*5
*4
(rlst) ← ((SP)), (SP) ← (SP) + 2n
-
-
-
-
-
-
-
-
-
-
JCTX
@A
1
14
0
6 × (c)
Context switch instruction
-
-
*
*
*
*
*
*
*
-
AND
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) and imm8
-
-
*
*
*
*
*
*
*
-
OR
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) or imm8
-
-
*
*
*
*
*
*
*
-
MOV
RP,#imm8
2
2
0
0
byte (RP) ← imm8
-
-
-
-
-
-
-
-
-
-
MOV
ILM,#imm8
2
2
0
0
byte (ILM) ← imm8
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,ear
2
3
1
0
word (RWi) ← ear
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,eam
2+
2+(a)
1
0
word (RWi) ← eam
-
-
-
-
-
-
-
-
-
-
MOVEA
A,ear
2
1
0
0
word (A) ← ear
-
*
-
-
-
-
-
-
-
-
MOVEA
A,eam
2+
1+(a)
0
0
word (A) ← eam
-
*
-
-
-
-
-
-
-
-
ADDSP
#imm8
2
3
0
0
word (SP) ← (SP) + ext(imm8)
-
-
-
-
-
-
-
-
-
-
ADDSP
#imm16
3
3
0
0
word (SP) ← (SP) + imm16
-
-
-
-
-
-
-
-
-
-
MOV
A,brg1
2
*1
0
0
byte (A) ← (brg1)
Z
*
-
-
-
*
*
-
-
-
MOV
brg2,A
2
1
0
0
byte (brg2) ← (A)
-
-
-
-
-
*
*
-
-
-
NOP
1
1
0
0
No operation
-
-
-
-
-
-
-
-
-
-
ADB
1
1
0
0
Prefix code for AD space access
-
-
-
-
-
-
-
-
-
-
DTB
1
1
0
0
Prefix code for DT space access
-
-
-
-
-
-
-
-
-
-
PCB
1
1
0
0
Prefix code for PC space access
-
-
-
-
-
-
-
-
-
-
SPB
1
1
0
0
Prefix code for SP space access
-
-
-
-
-
-
-
-
-
-
NCC
1
1
0
0
Prefix code for flag no-change
-
-
-
-
-
-
-
-
-
-
CMR
1
1
0
0
Prefix code for common register bank
-
-
-
-
-
-
-
-
-
-
*1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2
*2: 7 + 3 × (POP count) + 2 × (POP last register number), 7 when RLST = 0 (no transfer register)
*3: 29 + 3 × (PUSH count) - 3 × (PUSH last register number), 8 when RLST = 0 (no transfer register)
*4: (POP count) × (c) or (PUSH count) × (c)
*5: (POP count) or (PUSH count)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (c) in the table.
444
APPENDIX B Instructions
Table B.8-16 21 Bit Operand Instructions
Mnemonic
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
MOVB
A,dir:bp
3
5
0
(b)
byte (A) ← (dir:bp)b
Operation
Z
*
-
-
-
*
*
-
-
-
MOVB
A,addr16:bp
4
5
0
(b)
byte (A) ← (addr16:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,io:bp
3
4
0
(b)
byte (A) ← (io:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
dir:bp,A
3
7
0
2 × (b)
bit (dir:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
addr16:bp,A
4
7
0
2 × (b)
bit (addr16:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
io:bp,A
3
6
0
2 × (b)
bit (io:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
SETB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
CLRB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
CLRB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
CLRB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
BBC
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
io:bp,rel
4
*2
0
(b)
Branch on (io:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBS
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
io:bp,rel
4
*2
0
(b)
Branch on (io:bp) b = 1
-
-
-
-
-
-
*
-
-
-
SBBS
addr16:bp,rel
5
*3
0
2 × (b)
Branch on (addr16:bp) b = 1,
bit (addr16:bp) b ← 1
-
-
-
-
-
-
*
-
-
*
WBTS
io:bp
3
*4
0
*5
Waits until (io:bp) b = 1
-
-
-
-
-
-
-
-
-
-
WBTC
io:bp
3
*4
0
*5
Waits until (io:bp) b = 0
-
-
-
-
-
-
-
-
-
-
AH
I
S
T
N
Z
V
C
RMW
-
*1: 8 when a branch is made; otherwise, 7
*2: 7 when a branch is made; otherwise, 6
*3: 10 when the condition is met; otherwise, 9
*4: Undefined count
*5: Until the condition is met
Note:
See Table B.5-1 and Table B.5-2 for information on (b) in the table.
Table B.8-17 6 Accumulator Operation Instructions (Byte, Word)
Mnemonic
#
~
RG
B
Operation
LH
SWAP
1
3
0
0
byte (A)0-7 ↔ (A)8-15
-
-
-
-
-
-
-
-
-
SWAPW
1
2
0
0
word (AH) ↔ (AL)
-
*
-
-
-
-
-
-
-
-
EXT
1
1
0
0
Byte sign extension
X
-
-
-
-
*
*
-
-
-
EXTW
1
2
0
0
Word sign extension
-
X
-
-
-
*
*
-
-
-
ZEXT
1
1
0
0
Byte zero extension
Z
-
-
-
-
R
*
-
-
-
ZEXTW
1
1
0
0
Word zero extension
-
Z
-
-
-
R
*
-
-
-
445
APPENDIX B Instructions
Table B.8-18 10 String Instructions
#
~
RG
B
MOVS / MOVSI
Mnemonic
2
*2
*5
*3
byte transfer @AH+ ← @AL+, counter = RW0
Operation
LH
AH
-
-
I
S
T
N
Z
V
C
RMW
-
-
-
-
-
-
-
-
MOVSD
2
*2
*5
*3
byte transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCEQ / SCEQI
2
*1
*8
*4
byte search @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCEQD
2
*1
*8
*4
byte search @AH- ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
FILS / FILSI
2
6m+6
*8
*3
byte fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
MOVSW / MOVSWI
2
*2
*5
*6
word transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
-
MOVSWD
2
*2
*5
*6
word transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCWEQ / SCWEQI
2
*1
*8
*7
word search @AH+ - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCWEQD
2
*1
*8
*7
word search @AH- - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
FILSW / FILSWI
2
6m+6
*8
*6
word fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
*1: 5 when RW0 is 0, 4 + 7 × (RW0) when the counter expires, or 7n + 5 when a match occurs
*2: 5 when RW0 is 0; otherwise, 4 + 8 × (RW0)
*3: (b) × (RW0) + (b) × (RW0) When the source and destination access different areas, calculate the (b) item individually.
*4: (b) × n
*5: 2 × (b) × (RW0)
*6: (c) × (RW0) + (c) × (RW0) When the source and destination access different areas, calculate the (c) item individually.
*7: (c) × n
*8: (b) × (RW0)
Note:
m: RW0 value (counter value), n: Loop count
See Table B.5-1 and Table B.5-2 for information on (b) and (c) in the table.
446
APPENDIX B Instructions
B.9
Instruction Map
Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction
map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F2MC-16LX
instruction map.
■
Structure of Instruction Map
Figure B.9-1 Structure of Instruction Map
Basic page map
Bit operation
instructions
Character string
operation
instructions
2-byte
instructions
: Byte 1
ea instructions × 9 : Byte 2
An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An
instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it
references byte 1, and can check the following one byte by referencing the map for byte 2. Figure B.9-2
shows the correspondence between an actual instruction code and instruction map.
447
APPENDIX B Instructions
Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map
Some instructions do
not contain byte 2.
Instruction
code
Length varies
depending on the
instruction.
Byte 1
Byte 2
Operand
Operand
...
[Basic page map]
XY
+Z
[Extended page map]*
UV
+W
*: The extended page map is a generic name of maps for bit operation instructions, character
string operation instructions, 2-byte instructions, and ea instructions. Actually, there are
multiple extended page maps for each type of instructions.
An example of an instruction code is shown in Table B.9-1.
Table B.9-1 Example of an Instruction Code
Byte 1
(from basic page map)
Byte 2
(from extended page map)
NOP
00 +0=00
-
AND A, #8
30 +4=34
-
MOV A, ADB
60 +F=6F
00 +0=00
@RW2+d8, #8, rel
70 +0=70
F0 +2=F2
Instruction
448
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
A
SWAP
ADDSP
ADB
SPB
#8
CMP
A, #8
MOV
MOV
io, A
A, io
JMP
BRA
60
MULU
DIVU
ea
@A instruction 2
A
MOVW
MOVX
RET
SP, A A, addr16
MOVW
MOVW
RETP
A, SP
io, #16
ea
instruction 8
ea
instruction 7
MOVX
MOVX
CALLP
ea
A, #8
A, dir
A, io
addr24 instruction 6
A, #8
A0
B0
C0
E0
rel
rel
LSRW
ASRW
LSLW
A
A
A
XORW
ORW
ANDW
MOVW
ea, RWi
Bit operation MOV
A instruction
ea, Ri
ORW
PUSHW
POPW
A, #16
AH
AH
ANDW
PUSHW
POPW
A, #16
A
MOVW
RWi, ea
A
PUSHW
POPW
2-byte
XCHW
rlst
rlst instruction
RWi, ea
Character
XORW
PUSHW
POPW
XCH
operation
A
A, #16
PS
PS string
Ri, ea
instruction
A
A
ADDSP
MULUW
NOTW
#16
A
SWAPW
ZEXTW
EXTW
CMPW
MOVL
MOVW
RETI
A
A, #16
A, #32 addr16, A
BHI
BLS
BGT
BLE
rel
rel
rel
rel
rel
rel
CMPL
CMPW
A
A, #32
BGE
rel
rel
rel
rel
rel
NEGW
BNT
BT
BNV
BV
BP
BN
BNC/BHS
rel
BC/BLO
BNZ/BNE
rel
BZ/BEQ
BLT
#4
F0
MOV
MOV
CBNE A, CWBNE A, MOVW
MOVW
INTP
MOV
RP, #8
ILM, #8
#8, rel
#16, rel
A, #16 A,addr16
addr24
Ri, ea
A
D0
rel
SUBL
SUBW
A, #32
NOT
XOR
90
ADDW
MOVW
MOVW
INT
ea
MOVW
MOVW
MOVW
MOV A,
MOVW
A
A, #16
A, dir
A, io
#vct8 instruction 9
A, RWi
RWi, A RWi, #16 @RWi+d8 @RWi+d8, A
A
A
OR
OR
CCR, #8
80
ea
MOV
MOV
MOV
MOV
MOVX A, MOV
CALL
rel instruction 1
A, Ri
Ri, A
Ri, #8
A, Ri @RWi+d8
A, #4
70
MOV
JMP
ea
A, #8 A, addr16
addr16 instruction 3
dir, A
A, dir
50
MOVX
MOV
JMPP
ea
A, #8 addr16, A
addr24 instruction 4
MOV
MOV
MOV
40
SUBW
MOVW
MOVW
INT
MOVEA
A, #16
dir, A
io, A
addr16
RWi, ea
UNLINK
A
A
A, #8
A, #8
SUBC
SUB
ADD
30
AND
AND
MOV
MOV
CALL
ea
CCR, #8
A, #8
dir, #8
io, #8
addr16 instruction 5
CMP
A
A, dir
A, dir
ADDC
SUB
ADD
20
LINK
ADDL
ADDW
#imm8
A, #32
ZEXT
DTB
@A
EXT
JCTX
PCB
A
SUBDC
ADDDC
NEG
NCC
INT9
A
CMR
10
NOP
00
APPENDIX B Instructions
Table B.9-2 Basic Page Map
449
450
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
10
MOVB
io:bp, A
20
30
CLRB
io:bp
40
50
SETB
io:bp
60
70
BBC
io;bp, rel
80
90
BBS
io:bp, rel
A0
B0
MOVB
MOVB A, MOVB
MOVB
CLRB
CLRB
SETB
SETB
BBC
BBC
BBS
BBS
A, dir:bp addr16:bp
dir:bp, A addr16:bp,A
dir:bp addr16:bp
dir:bp addr16:bp dir:bp, rel addr16:bp,rel dir:bp, rel addr16:bp,rel
MOVB
A, io:bp
00
WBTS
io:bp
C0
D0
WBTC
io:bp
E0
SBBS
addr16:bp
F0
APPENDIX B Instructions
Table B.9-3 Bit Operation Instruction Map (First Byte = 6CH)
MOVSI
MOVSD
PCB, PCB
PCB, DTB
PCB, ADB
PCB, SPB
DTB, PCB
DTB, DTB
DTB, ADB
DTB, SPB
ADB, PCB
ADB, DTB
ADB, ADB
ADB, SPB
SPB, PCB
SPB, DTB
SPB, ADB
SPB, SPB
+1
+2
+3
+4
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
10
+0
00
MOVSWI
20
MOVSWD
30
40
50
60
70
90
A0
B0
C0
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SCEQI
SCEQD
SCWEQI SCWEQD FILSI
PCB
PCB
PCB
PCB
PCB
80
D0
FILSI
SPB
ADB
DTB
PCB
E0
F0
APPENDIX B Instructions
Table B.9-4 Character String Operation Instruction Map (First Byte = 6EH)
451
452
LSLW
LSLL
LSL
MOVW
MOVW
A, R0
A, R0
A, R0 @RL2+d8, A A, @RL2+d8
MOVW
MOVW
NRML
A, @A @AL, AH
A, R0
ASRW
ASRL
ASR
MOVW
MOVW
A, R0
A, R0
A, R0 @RL3+d8, A A, @RL3+d8
LSRW
LSRL
LSR
A, R0
A, R0
A, R0
+D
+E
+F
MOVW
MOVW
@RL1+d8, A A, @RL1+d8
MOVW
MOVW
@RL0+d8, A A, @RL0+d8
+C
+B
+A
+9
+8
A
MOV
MOV
MOVX
MOV
MOV
A, PCB
A, @A A, @RL3+d8 @RL3+d8, A A, @RL3+d8
+6
ROLC
MOV
MOV
A, @A @AL, AH
+5
A
MOV
MOV
MOVX
MOV
MOV
A, DPR
DPR, A A, @RL2+d8 @RL2+d8, A A, @RL2+d8
+4
ROLC
MOV
MOV
A, USB
USB, A
+3
+7
MOV
MOV
MOVX
MOV
MOV
A, SSB
SSB, A A, @RL1+d8 @RL1+d8, A A, @RL1+d8
+2
40
MOV
MOV
A, ADB
ADB, A
30
+1
20
MOV
MOV
MOVX
MOV
MOV
A, DTB
DTB, A A, @RL0+d8 @RL0+d8, A A, @RL0+d8
10
+0
00
50
DIVU
MULW
MUL
60
A
A
A
70
80
90
A0
B0
C0
D0
E0
F0
APPENDIX B Instructions
Table B.9-5 2-byte Instruction Map (First Byte = 6FH)
50
90
B0
D0
@RW1, @RW1+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
@RW2, @RW2+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
@RW3, @RW3+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
SUBL
SUBL A,
A, RL2 @RW5+d8
SUBL
SUBL A,
A, RL3 @RW6+d8
SUBL
SUBL A,
A, RL3 @RW7+d8
ADDL
ADDL A,
A, RL2 @RW5+d8
ADDL
ADDL A,
A, RL3 @RW6+d8
ADDL
ADDL A,
A, RL3 @RW7+d8
ADDL
ADDL A, SUBL
SUBL A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ADDL
ADDL A, SUBL
SUBL A, Use
@RW0+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW0+RW7
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
#16, rel A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
,#8, rel
ADDL
ADDL A, SUBL
SUBL A, Use
@RW1+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW1+RW7
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
#16, rel A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
,#8, rel
ADDL
ADDL A,
A,@RW2+ @PC+d16
ADDL
ADDL A, SUBL
SUBL A, Use
A,@RW3+
addr16 A,@RW3+
addr16 prohibited
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
SUBL
SUBL A,
A,@RW2+ @PC+d16
@RW0, @RW0+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
SUBL
SUBL A,
A, RL2 @RW4+d8
Use
prohibited
ANDL
ANDL A,
A,@RW2+ @PC+d16
ANDL
ANDL A,
A, RL3 @RW7+d8
ANDL
ANDL A,
A, RL3 @RW6+d8
ANDL
ANDL A,
A, RL2 @RW5+d8
ANDL
ANDL A,
A, RL2 @RW4+d8
ORL
ORL A,
A,@RW2+ @PC+d16
ORL
ORL A,
A, RL3 @RW7+d8
ORL
ORL A,
A, RL3 @RW6+d8
ORL
ORL A,
A, RL2 @RW5+d8
ORL
ORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A,@RW2+ @PC+d16
XORL
XORL A,
A, RL3 @RW7+d8
XORL
XORL A,
A, RL3 @RW6+d8
XORL
XORL A,
A, RL2 @RW5+d8
XORL
XORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A, RL1 @RW3+d8
addr16,
,#8, rel
Use
@PC+d16,
prohibited
,#8, rel
@RW3, @RW3+d16
#8, rel
,#8, rel
@RW2, @RW2+d16
#8, rel
,#8, rel
@RW1, @RW1+d16
#8, rel
,#8, rel
@RW0, @RW0+d16
#8, rel
,#8, rel
R7, @RW7+d8,
#8, rel
#8, rel
R6, @RW6+d8,
#8, rel
#8, rel
R5, @RW5+d8,
#8, rel
#8, rel
R4, @RW4+d8,
#8, rel
#8, rel
R3, @RW3+d8,
#8, rel
#8, rel
addr16, CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
#16, rel A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 prohibited
@PC+d16, CMPL
CMPL A,
#16, rel A,@RW2+ @PC+d16
RW7, @RW7+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW7+d8
RW6, @RW6+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW6+d8
RW5, @RW5+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW5+d8
RW4, @RW4+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW4+d8
ORL
ORL A,
A, RL1 @RW3+d8
R2, @RW2+d8,
#8, rel
#8, rel
R1, @RW1+d8,
#8, rel
#8, rel
ADDL
ADDL A,
A, RL2 @RW4+d8
ANDL
ANDL A,
A, RL1 @RW3+d8
XORL
XORL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW1+d8
+4
RW3, @RW3+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW3+d8
ORL
ORL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW1+d8
SUBL
SUBL A,
A, RL1 @RW3+d8
ANDL
ANDL A,
A, RL1 @RW2+d8
ANDL
ANDL A,
A, RL0 @RW1+d8
ADDL
ADDL A,
A, RL1 @RW3+d8
RW2, @RW2+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW2+d8
RW1, @RW1+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW1+d8
+3
CBNE ↓
F0
R0, @RW0+d8,
#8, rel
#8, rel
CBNE ↓
E0
SUBL
SUBL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW0+d8
C0
ADDL
ADDL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW0+d8
A0
+2
ANDL
ANDL A,
A, RL0 @RW0+d8
80
SUBL
SUBL A,
A, RL0 @RW1+d8
70
ADDL
ADDL A,
A, RL0 @RW1+d8
60
RW0, @RW0+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW0+d8
CWBNE ↓ CWBNE ↓
40
+1
30
+0
20
SUBL
SUBL A,
A, RL0 @RW0+d8
10
ADDL
ADDL A,
A, RL0 @RW0+d8
00
APPENDIX B Instructions
Table B.9-6 ea Instruction 1 (First Byte = 70H)
453
454
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW7+d8
@RL3 @@RW7+d8
RL3 @RW7+d8
RL3 @RW7+d8
A, RL3 @RW7+d8
RL3, A @RW7+d8,A
R7, #8 @RW7+d8,#8
A, RW7 @RW7+d8
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #8 @RW0+d16,#8
A,@RW0 @RW0+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1,A @RW1+d16,A @RW1, #8 @RW1+d16,#8
A,@RW1 @RW1+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2,A @RW2+d16,A @RW2, #8 @RW2+d16,#8
A,@RW2 @RW2+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3,A @RW3+d16,A @RW3, #8 @RW3+d16,#8
A,@RW3 @RW3+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+,A @RW0+RW7,A @RW0+, #8 @RW0+RW7,#8 A,@RW0+ @RW0+RW7
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+,A @RW1+RW7,A @RW1+, #8 @RW1+RW7,#8 A,@RW1+ @RW1+RW7
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+,A @PC+d16, A @RW2+, #8 @PC+d16, #8 A,@RW2+ @PC+d16
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+,A
addr16, A @RW3+, #8
addr16, #8 A,@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW6+d8
@RL3 @@RW6+d8
RL3 @RW6+d8
RL3 @RW6+d8
A, RL3 @RW6+d8
RL3, A @RW6+d8,A
R6, #8 @RW6+d8,#8
A, RW6 @RW6+d8
D0
+6
C0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW5+d8
@RL2 @@RW5+d8
RL2 @RW5+d8
RL2 @RW5+d8
A, RL2 @RW5+d8
RL2, A @RW5+d8,A
R5, #8 @RW5+d8,#8
A, RW5 @RW5+d8
B0
+5
A0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW4+d8
@RL2 @@RW4+d8
RL2 @RW4+d8
RL2 @RW4+d8
A, RL2 @RW4+d8
RL2, A @RW4+d8,A
R4, #8 @RW4+d8,#8
A, RW4 @RW4+d8
90
+4
80
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW3+d8
@RL1 @@RW3+d8
RL1 @RW3+d8
RL1 @RW3+d8
A, RL1 @RW3+d8
RL1, A @RW3+d8,A
R3, #8 @RW3+d8,#8
A, RW3 @RW3+d8
70
+3
60
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW2+d8
@RL1 @@RW2+d8
RL1 @RW2+d8
RL1 @RW2+d8
A, RL1 @RW2+d8
RL1, A @RW2+d8,A
R2, #8 @RW2+d8,#8
A, RW2 @RW2+d8
50
+2
40
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW1+d8
@RL0 @@RW1+d8
RL0 @RW1+d8
RL0 @RW1+d8
A, RL0 @RW1+d8
RL0, A @RW1+d8,A
R1, #8 @RW1+d8,#8
A, RW1 @RW1+d8
30
+1
20
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW0+d8
@RL0 @@RW0+d8
RL0 @RW0+d8
RL0 @RW0+d8
A, RL0 @RW0+d8
RL0, A @RW0+d8,A
R0, #8 @RW0+d8,#8
A, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-7 ea Instruction 2 (First Byte = 71H)
D0
E0
F0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A A,@RW3+
addr16 A,@RW3+
addr16
+D
+E
+F
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R7 @RW7+d8
A, R7 @RW7+d8
R7, A @RW7+d8,A
A, R7 @RW7+d8
A, R7 @RW7+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R6 @RW6+d8
A, R6 @RW6+d8
R6, A @RW6+d8,A
A, R6 @RW6+d8
A, R6 @RW6+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R5 @RW5+d8
A, R5 @RW5+d8
R5, A @RW5+d8,A
A, R5 @RW5+d8
A, R5 @RW5+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R4 @RW4+d8
A, R4 @RW4+d8
R4, A @RW4+d8,A
A, R4 @RW4+d8
A, R4 @RW4+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R3 @RW3+d8
A, R3 @RW3+d8
R3, A @RW3+d8,A
A, R3 @RW3+d8
A, R3 @RW3+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R2 @RW2+d8
A, R2 @RW2+d8
R2, A @RW2+d8,A
A, R2 @RW2+d8
A, R2 @RW2+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R1 @RW1+d8
A, R1 @RW1+d8
R1, A @RW1+d8,A
A, R1 @RW1+d8
A, R1 @RW1+d8
+C
INC
DEC
R7 @RW7+d8
C0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ROLC
RORC
RORC
INC
R7 @RW7+d8
R7 @RW7+d8
ROLC
INC
DEC
R6 @RW6+d8
B0
+B
ROLC
RORC
RORC
INC
R6 @RW6+d8
R6 @RW6+d8
ROLC
INC
DEC
R5 @RW5+d8
A0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ROLC
RORC
RORC
INC
R5 @RW5+d8
R5 @RW5+d8
ROLC
INC
DEC
R4 @RW4+d8
90
+A
ROLC
RORC
RORC
INC
R4 @RW4+d8
R4 @RW4+d8
ROLC
INC
DEC
R3 @RW3+d8
INC
DEC
R2 @RW2+d8
INC
DEC
R1 @RW1+d8
80
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R0 @RW0+d8
A, R0 @RW0+d8
R0, A @RW0+d8,A
A, R0 @RW0+d8
A, R0 @RW0+d8
70
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ROLC
RORC
RORC
INC
R3 @RW3+d8
R3 @RW3+d8
ROLC
60
INC
DEC
R0 @RW0+d8
50
+9
ROLC
RORC
RORC
INC
R2 @RW2+d8
R2 @RW2+d8
ROLC
40
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0, A @RW0+d16,A
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ROLC
RORC
RORC
INC
R1 @RW1+d8
R1 @RW1+d8
ROLC
30
ROLC
RORC
RORC
INC
R0 @RW0+d8
R0 @RW0+d8
20
ROLC
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX B Instructions
Table B.9-8 ea Instruction 3 (First Byte = 72H)
455
456
CALL
CALL
RW5 @@RW5+d8
CALL
CALL
RW6 @@RW6+d8
CALL
CALL
RW7 @@RW7+d8
JMP
JMP
@RW5 @@RW5+d8
JMP
JMP
@RW6 @@RW6+d8
JMP
JMP
@RW7 @@RW7+d8
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16 @RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #16 @RW0+d16,#16 A,@RW0 @RW0+d16
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16 @RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, #16 @RW1+d16,#16 A,@RW1 @RW1+d16
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16 @RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, #16 @RW2+d16,#16 A,@RW2 @RW2+d16
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16 @RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, #16 @RW3+d16,#16 A,@RW3 @RW3+d16
JMP
JMP @
CALL
CALL @
INCW
INCW @
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, #16 @RW0+RW7,#16 A,@RW0+ @RW0+RW7
JMP
JMP @
CALL
CALL @
INCW
INCW @
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, #16 @RW1+RW7,#16 A,@RW1+ @RW1+RW7
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16 @RW2+ @@PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A @RW2+, #16 @PC+d16, #16 A,@RW2+ @PC+d16
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A @RW3+, #16
addr16, #16 A,@RW3+
addr16
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW7 @RW7+d8
RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, A @RW7+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW6 @RW6+d8
RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, A @RW6+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW5 @RW5+d8
RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, A @RW5+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW4 @RW4+d8
RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, A @RW4+d8,A
MOVW
MOVW
RW7, #16 @RW7+d8,#16
MOVW
MOVW
RW6, #16 @RW6+d8,#16
MOVW
MOVW
RW5, #16 @RW5+d8,#16
MOVW
MOVW
RW4, #16 @RW4+d8,#16
XCHW
XCHW A,
A, RW7 @RW7+d8
XCHW
XCHW A,
A, RW6 @RW6+d8
XCHW
XCHW A,
A, RW5 @RW5+d8
XCHW
XCHW A,
A, RW4 @RW4+d8
XCHW
XCHW A,
A, RW3 @RW3+d8
XCHW
XCHW A,
A, RW2 @RW2+d8
XCHW
XCHW A,
A, RW1 @RW1+d8
CALL
CALL
RW4 @@RW4+d8
MOVW
MOVW
RW3, #16 @RW3+d8,#16
MOVW
MOVW
RW2, #16 @RW2+d8,#16
MOVW
MOVW
RW1, #16 @RW1+d8,#16
JMP
JMP
@RW4 @@RW4+d8
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW3 @RW3+d8
RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, A @RW3+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW2 @RW2+d8
RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, A @RW2+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW1 @RW1+d8
RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, A @RW1+d8,A
+4
F0
XCHW
XCHW A,
A, RW0 @RW0+d8
E0
CALL
CALL
RW3 @@RW3+d8
D0
MOVW
MOVW
RW0, #16 @RW0+d8,#16
C0
JMP
JMP
@RW3 @@RW3+d8
B0
+3
A0
CALL
CALL
RW2 @@RW2+d8
90
JMP
JMP
@RW2 @@RW2+d8
80
+2
70
CALL
CALL
RW1 @@RW1+d8
60
JMP
JMP
@RW1 @@RW1+d8
50
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW0 @RW0+d8
RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, A @RW0+d8,A
40
+1
30
CALL
CALL
RW0 @@RW0+d8
20
JMP
JMP
@RW0 @@RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-9 ea Instruction 4 (First Byte = 73H)
ADD
A, SUB
SUB
SUB
ADDC
A, ADDC
A,
ADDC
ADDC A,
A, CMP
CMP
CMP
CMP
A,
A,
A, AND
AND
AND
AND
AND
AND
A,
A,
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r PC+d16, r
+F A,@RW3+
ADD
ADD
SUB
SUB
ADDC
ADDC
CMP
CMP
AND
AND
OR
OR
XOR
XOR
DBNZ
DBNZ
A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+
A, addr16 A,@RW3+ A, addr16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ADD
SUB
CMP
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW1+ @RW1+RW7 @RW1+, r W1+RW7, r
A,
CMP
OR
OR
A,
A,@RW1+ @RW1+RW7
ADD
ADD
ADDC A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ADDC
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW0+ @RW0+RW7 @RW0+, r W0+RW7, r
A,
OR
OR
A,
A,@RW0+ @RW0+RW7
SUB
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
SUB
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW3 @RW3+d16 @RW3, r W3+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
A,
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW2 @RW2+d16 @RW2, r W2+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW1 @RW1+d16 @RW1, r W1+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW0 @RW0+d16 @RW0, r W0+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
R7, r RW7+d8, r
ADD
F0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
R6, r RW6+d8, r
E0
ADD
D0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
R5, r RW5+d8, r
C0
ADD
B0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
R4, r RW4+d8, r
A0
ADD
90
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
R3, r RW3+d8, r
80
ADD
70
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
R2, r RW2+d8, r
60
ADD
50
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
R1, r RW1+d8, r
40
ADD
30
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
R0, r RW0+d8, r
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX B Instructions
Table B.9-10 ea Instruction 5 (First Byte = 74H)
457
458
NOT
NOT
R2 @RW2+d8
SUB
SUB
SUB
SUB
SUB
SUB
@RW2+, A @PC+d16,A
SUB
SUB
@RW3+, A addr16, A
ADD
ADD
@RW2+, A @PC+d16,A
ADD
ADD
@RW3+, A addr16, A
+F
@RW1+RW7,A @RW1+, A @RW1+RW7,A
ADD @R
@RW0+RW7,A @RW0+, A @RW0+RW7,A
ADD @R
+E
+D @RW1+, A
ADD
+C @RW0+, A
ADD
NOT
NOT
@RW1+ @RW1+RW7
NOT
NOT
@RW0+ @RW0+RW7
SUBC
SUBC A, NEG
NEG A,
AND
AND
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
OR
OR
@RW3+, A addr16, A
XOR
XOR
@RW3+, A addr16, A
NOT
NOT
@RW3+
addr16
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
NOT
NOT
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+ @PC+d16
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A
NOT
NOT
@RW3 @RW3+d16
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
+B
XOR
NOT
NOT
R7, A @RW7+d8, A
R7 @RW7+d8
XOR
NOT
NOT
R6, A @RW6+d8, A
R6 @RW6+d8
XOR
NOT
NOT
R5, A @RW5+d8, A
R5 @RW5+d8
XOR
NOT
NOT
R4, A @RW4+d8, A
R4 @RW4+d8
XOR
NOT
NOT
R3, A @RW3+d8, A
R3 @RW3+d8
XOR
R2, A @RW2+d8,A
XOR
NOT
NOT
R1, A @RW1+d8, A
R1 @RW1+d8
NOT
NOT
@RW2 @RW2+d16
XOR
F0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
NEG A,
AND
AND
OR
OR
R7 @RW7+d8
R7, A @RW7+d8, A
R7, A @RW7+d8, A
XOR
XOR
XOR
XOR
XOR
XOR
E0
XOR
NOT
NOT
R0, A @RW0+d8, A
R0 @RW0+d8
D0
+A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R7, A @RW7+d8, A
R7, A @RW7+d8, A
A, R7 @RW7+d8
ADD
NEG A,
AND
AND
OR
OR
R6 @RW6+d8
R6, A @RW6+d8, A
R6, A @RW6+d8, A
NEG A,
AND
AND
OR
OR
R5 @RW5+d8
R5, A @RW5+d8, A
R5, A @RW5+d8, A
NEG A,
AND
AND
OR
OR
R4 @RW4+d8
R4, A @RW4+d8, A
R4, A @RW4+d8, A
NEG A,
AND
AND
OR
OR
R3 @RW3+d8
R3, A @RW3+d8, A
R3, A @RW3+d8, A
NEG A,
AND
AND
OR
OR
R2 @RW2+d8
R2, A @RW2+d8,A
R2, A @RW2+d8,A
NEG A,
AND
AND
OR
OR
R1 @RW1+d8
R1, A @RW1+d8, A
R1, A @RW1+d8, A
XOR
C0
NOT
NOT
@RW1 @RW1+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R6, A @RW6+d8, A
R6, A @RW6+d8, A
A, R6 @RW6+d8
ADD
B0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R5, A @RW5+d8, A
R5, A @RW5+d8, A
A, R5 @RW5+d8
ADD
A0
+9
ADD
SUB
SUB
SUBC
SUBC A, NEG
R4, A @RW4+d8, A
R4, A @RW4+d8, A
A, R4 @RW4+d8
ADD
90
NOT
NOT
@RW0 @RW0+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R3, A @RW3+d8, A
R3, A @RW3+d8, A
A, R3 @RW3+d8
ADD
80
NEG A,
AND
AND
OR
OR
R0 @RW0+d8
R0, A @RW0+d8, A
R0, A @RW0+d8, A
70
ADD
ADD
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R2, A @RW2+d8,A
R2, A @RW2+d8,A
A, R2 @RW2+d8
60
ADD
50
ADD
SUB
SUB
SUBC
SUBC A, NEG
R1, A @RW1+d8, A
R1, A @RW1+d8, A
A, R1 @RW1+d8
40
ADD
30
ADD
SUB
SUB
SUBC
SUBC A, NEG
R0, A @RW0+d8, A
R0, A @RW0+d8, A
A, R0 @RW0+d8
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX B Instructions
Table B.9-11 ea Instruction 6 (First Byte = 75H)
ADDW A, SUBW
ADDW
ADDCW
CMPW
ADDCW A, CMPW
ADDCW A,
ANDW
CMPW A, ANDW
CMPW A,
ORW
ORW
ANDW A, ORW
ANDW A,
ANDW A,
ORW
ORW
ORW
A,
A,
A, XORW
XORW A, DWBNZ
DWBNZ
+F A,@RW3+
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
addr 16 A,@RW3+ addr 16
A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr16 A,@RW3+
addr 16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r @PC+d16,r
SUBW A, ADDCW
SUBW A,
ANDW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW1+ @RW1+RW7 @RW1+, r @RW1+RW7,r
SUBW
ADDW A,
ADDW
CMPW A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
CMPW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW0+ @RW0+RW7 @RW0+, r @RW0+RW7,r
ADDCW A,
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ADDCW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW3 @RW3+d16 @RW3, r @RW3+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
SUBW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW2 @RW2+d16 @RW2, r @RW2+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
SUBW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW1 @RW1+d16 @RW1, r @RW1+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADDW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW0 @RW0+d16 @RW0, r @RW0+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
ADDW
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, r @RW7+d8,r
F0
+7
E0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, r @RW6+d8,r
D0
+6
C0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, r @RW5+d8,r
B0
+5
A0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, r @RW4+d8,r
90
+4
80
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, r @RW3+d8,r
70
+3
60
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, r @RW2+d8,r
50
+2
40
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, r @RW1+d8,r
30
+1
20
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, r @RW0+d8,r
10
+0
00
APPENDIX B Instructions
Table B.9-12 ea Instruction 7 (First Byte = 76H)
459
460
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
@RW3 @RW3+d16
SUBW
SUBW
@RW3+, A addr16, A
ADDW
ADDW
@RW3+, A addr16, A
+F
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
ORW
ORW
@RW3+, A addr16, A
XORW
XORW
@RW3+, A addr16, A
NOTW
NOTW
@RW3+
addr16
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
@RW2+ @PC+d16
SUBW
SUBW
@RW2+, A @PC+d16,A
ADDW
ADDW
@RW2+, A @PC+d16,A
+E
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7
@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+ @RW1+RW7
SUBCW
+D
SUBW
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7
@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+ @RW0+RW7
SUBW
SUBCW
+C
ADDW
ADDW
SUBW
SUBCW A,
+B @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
SUBW
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
@RW2 @RW2+d16
ADDW
ADDW
SUBW
+A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
SUBW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
@RW1 @RW1+d16
ADDW
ADDW
SUBCW A,
+9 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
@RW0 @RW0+d16
SUBW
NOTW
NOTW
RW7 @RW7+d8
NOTW
NOTW
RW6 @RW6+d8
NOTW
NOTW
RW5 @RW5+d8
+8 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
SUBW
XORW
XORW
RW7, A @RW7+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
A, RW7 @RW7+d8
RW7 @RW7+d8
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
+7
ADDW
XORW
XORW
RW6, A @RW6+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
A, RW6 @RW6+d8
RW6 @RW6+d8
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
+6
ADDW
XORW
XORW
RW5, A @RW5+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
A, RW5 @RW5+d8
RW5 @RW5+d8
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
+5
NOTW
NOTW
RW4 @RW4+d8
XORW
XORW
RW4, A @RW4+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
A, RW4 @RW4+d8
RW4 @RW4+d8
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
+4
F0
NOTW
NOTW
RW0 @RW0+d8
E0
NOTW
NOTW
RW3 @RW3+d8
D0
XORW
XORW
RW3, A @RW3+d8, A
C0
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
A, RW3 @RW3+d8
RW3 @RW3+d8
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
B0
+3
A0
NOTW
NOTW
RW2 @RW2+d8
90
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
A, RW2 @RW2+d8
RW2 @RW2+d8
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
80
+2
70
NOTW
NOTW
RW1 @RW1+d8
60
XORW
XORW
RW1, A @RW1+d8, A
50
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
A, RW1 @RW1+d8
RW1 @RW1+d8
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
40
+1
30
XORW
XORW
RW0, A @RW0+d8, A
20
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
A, RW0 @RW0+d8
RW0 @RW0+d8
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
10
+0
00
APPENDIX B Instructions
Table B.9-13 ea Instruction 8 (First Byte = 77H)
DIV
DIV
A, DIVW
DIVW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
DIV
DIV
A, DIVW
DIVW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MUL
MUL A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MUL
MUL A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MUL
MUL A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW MULUW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MULU
MULU A, MULUW MULUW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MULU
MULU A, MULUW MULUW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
+9
+A
+B
+C
+D
+E
+F A, @RW3+
MULU
DIV
DIV
A, DIVW
DIVW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MUL
MUL A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
addr16 A,@RW3+ addr16
A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
A, DIVW
DIVW A,
addr16 A,@RW3+
addr16
DIV
DIV
A, DIVW
DIVW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
F0
+7
E0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
D0
+6
C0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
B0
+5
A0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
90
+4
80
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
70
+3
60
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
50
+2
40
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
30
+1
20
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-14 ea Instruction 9 (First Byte = 78H)
461
462
MOVEA
MOVEA RW1
RW1,RW4 ,@RW4+d8
MOVEA
MOVEA RW1
RW1,RW5 ,@RW5+d8
MOVEA
MOVEA RW1
RW1,RW6 ,@RW6+d8
MOVEA
MOVEA RW1
RW1,RW7 ,@RW7+d8
MOVEA
MOVEA RW1
RW1,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,@RW1 ,@RW1+d16
MOVEA
MOVEA RW1
RW1,@RW2 ,@RW2+d16
MOVEA
MOVEA RW1
RW1,@RW3 ,@RW3+d16
MOVEA
MOVEA RW0
RW0,RW4 ,@RW4+d8
MOVEA
MOVEA RW0
RW0,RW5 ,@RW5+d8
MOVEA
MOVEA RW0
RW0,RW6 ,@RW6+d8
MOVEA
MOVEA RW0
RW0,RW7 ,@RW7+d8
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
+4
+5
+6
+7
50
70
90
B0
C0
D0
F0
MOVEA
MOVEA RW3
RW3,@RW2+ ,@PC+d16
MOVEA
MOVEA RW4
RW4,@RW2+ ,@PC+d16
MOVEA
MOVEA RW7
RW7,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
RW6,@RW3+ RW6, addr16 [email protected]+ RW7, addr16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2+ ,@PC+d16
RW6,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
RW0,@RW3+ RW0, addr16 RW1,@RW3+ RW1, addr16 RW2,@RW3+ RW2, addr16 RW3,@RW3+ RW3, addr16 RW4,@RW3+ RW4, addr16 RW5,@RW3+ RW5, addr16
MOVEA
MOVEA RW2
RW2,@RW2+ ,@PC+d16
+F
MOVEA
MOVEA RW1
RW1,@RW2+ ,@PC+d16
MOVEA
MOVEA RW0
RW0,@RW2+ ,@PC+d16
MOVEA RW1
+E
MOVEA
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW5,@RW1+ ,@RW1+RW7 RW6,@RW1+ ,@RW1+RW7 RW7,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW7
RW7,@RW3 ,@RW3+d16
MOVEA
MOVEA RW7
RW7,@RW2 ,@RW2+d16
MOVEA
MOVEA RW7
RW7,@RW1 ,@RW1+d16
MOVEA
MOVEA RW7
RW7,@RW0 ,@RW0+d16
MOVEA
MOVEA RW7
RW7,RW7 ,@RW7+d8
MOVEA
MOVEA RW7
RW7,RW6 ,@RW6+d8
MOVEA
MOVEA RW7
RW7,RW5 ,@RW5+d8
MOVEA
MOVEA RW7
RW7,RW4 ,@RW4+d8
MOVEA
MOVEA RW7
RW7,RW3 ,@RW3+d8
MOVEA
MOVEA RW7
RW7,RW2 ,@RW2+d8
MOVEA
MOVEA RW7
RW7,RW1 ,@RW1+d8
MOVEA
MOVEA RW7
RW7,RW0 ,@RW0+d8
E0
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4
RW2,@RW1+ ,@RW1+RW7 RW3,@RW1+ ,@RW1+RW7 RW4,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW3 ,@RW3+d16 RW6,@RW3 ,@RW3+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2 ,@RW2+d16 RW6,@RW2 ,@RW2+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW1 ,@RW1+d16 RW6,@RW1 ,@RW1+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW0 ,@RW0+d16 RW6,@RW0 ,@RW0+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW7 ,@RW7+d8
RW6,RW7 ,@RW7+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW6 ,@RW6+d8
RW6,RW6 ,@RW6+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW5 ,@RW5+d8
RW6,RW5 ,@RW5+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW4 ,@RW4+d8
RW6,RW4 ,@RW4+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW3 ,@RW3+d8
RW6,RW3 ,@RW3+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW2 ,@RW2+d8
RW6,RW2 ,@RW2+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW1 ,@RW1+d8
RW6,RW1 ,@RW1+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW0 ,@RW0+d8
RW6,RW0 ,@RW0+d8
A0
+D RW0,@RW1+ ,@RW1+RW7 RW1,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW4
RW4,@RW3 ,@RW3+d16
MOVEA
MOVEA RW4
RW4,@RW2 ,@RW2+d16
MOVEA
MOVEA RW4
RW4,@RW1 ,@RW1+d16
MOVEA
MOVEA RW4
RW4,@RW0 ,@RW0+d16
MOVEA
MOVEA RW4
RW4,RW7 ,@RW7+d8
MOVEA
MOVEA RW4
RW4,RW6 ,@RW6+d8
MOVEA
MOVEA RW4
RW4,RW5 ,@RW5+d8
MOVEA
MOVEA RW4
RW4,RW4 ,@RW4+d8
MOVEA
MOVEA RW4
RW4,RW3 ,@RW3+d8
MOVEA
MOVEA RW4
RW4,RW2 ,@RW2+d8
MOVEA
MOVEA RW4
RW4,RW1 ,@RW1+d8
MOVEA
MOVEA RW4
RW4,RW0 ,@RW0+d8
80
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW5,@RW0+ ,@RW0+RW7 RW6,@RW0+ ,@RW0+RW7 RW7,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW3
RW3,@RW3 ,@RW3+d16
MOVEA
MOVEA RW3
RW3,@RW2 ,@RW2+d16
MOVEA
MOVEA RW3
RW3,@RW1 ,@RW1+d16
MOVEA
MOVEA RW3
RW3,@RW0 ,@RW0+d16
MOVEA
MOVEA RW3
RW3,RW7 ,@RW7+d8
MOVEA
MOVEA RW3
RW3,RW6 ,@RW6+d8
MOVEA
MOVEA RW3
RW3,RW5 ,@RW5+d8
MOVEA
MOVEA RW3
RW3,RW4 ,@RW4+d8
MOVEA
MOVEA RW3
RW3,RW3 ,@RW3+d8
MOVEA
MOVEA RW3
RW3,RW2 ,@RW2+d8
MOVEA
MOVEA RW3
RW3,RW1 ,@RW1+d8
MOVEA
MOVEA RW3
RW3,RW0 ,@RW0+d8
60
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4
RW2,@RW0+ ,@RW0+RW7 RW3,@RW0+ ,@RW0+RW7 RW4,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW2
RW2,@RW3 ,@RW3+d16
MOVEA
MOVEA RW2
RW2,@RW2 ,@RW2+d16
MOVEA
MOVEA RW2
RW2,@RW1 ,@RW1+d16
MOVEA
MOVEA RW2
RW2,@RW0 ,@RW0+d16
MOVEA
MOVEA RW2
RW2,RW7 ,@RW7+d8
MOVEA
MOVEA RW2
RW2,RW6 ,@RW6+d8
MOVEA
MOVEA RW2
RW2,RW5 ,@RW5+d8
MOVEA
MOVEA RW2
RW2,RW4 ,@RW4+d8
MOVEA
MOVEA RW2
RW2,RW3 ,@RW3+d8
MOVEA
MOVEA RW2
RW2,RW2 ,@RW2+d8
MOVEA
MOVEA RW2
RW2,RW1 ,@RW1+d8
MOVEA
MOVEA RW2
RW2,RW0 ,@RW0+d8
40
+C RW0,@RW0+ ,@RW0+RW7 RW1,@RW0+ ,@RW0+RW7
+B RW0,@RW3 ,@RW3+d16
+A RW0,@RW2 ,@RW2+d16
+9 RW0,@RW1 ,@RW1+d16
MOVEA RW1
MOVEA
MOVEA RW1
RW1,RW3 ,@RW3+d8
MOVEA
MOVEA RW0
RW0,RW3 ,@RW3+d8
+3
MOVEA
MOVEA
MOVEA RW1
RW1,RW2 ,@RW2+d8
MOVEA
MOVEA RW0
RW0,RW2 ,@RW2+d8
+2
+8 RW0,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,RW1 ,@RW1+d8
MOVEA
MOVEA RW0
RW0,RW1 ,@RW1+d8
+1
30
MOVEA
MOVEA RW1
RW1,RW0 ,@RW0+d8
20
MOVEA
MOVEA RW0
RW0,RW0 ,@RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-15 MOVEA RWi, ea Instruction (First Byte = 79H)
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW2 @RW2+d16 R1,@RW2 @RW2+d16 R2,@RW2 @RW2+d16 R3,@RW2 @RW2+d16 R4,@RW2 @RW2+d16 R5,@RW2 @RW2+d16 R6,@RW2 @RW2+d16 R7,@RW2 @RW2+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW3+
addr16 @RW3+
addr16
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16
@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-16 MOV Ri, ea Instruction (First Byte = 7AH)
463
464
MOVW
MOVW RW5,
RW5,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW1 @RW1+d16 RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16 RW3,@RW1 @RW1+d16 RW4,@RW1 @RW1+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW2 @RW2+d16 RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16 RW3,@RW2 @RW2+d16 RW4,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW3 @RW3+d16 RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16 RW3,@RW3 @RW3+d16 RW4,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4, MOVW
MOVW RW5, MOVW
MOVW RW6, MOVW
MOVW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, @RW2+ @PC+d16
RW2, @RW2+ @PC+d16
RW3, @RW2+ @PC+d16
RW4, @RW2+ @PC+d16
MOVW
MOVW
RW1, @RW3+ RW1, addr16
MOVW
RW0, @RW1+
MOVW
MOVW
RW0, @RW2+ @PC+d16
MOVW
MOVW
RW0, @RW3+ RW0, addr16
+9
+A
+B
+C
+D
+E
+F
MOVW
MOVW
RW2, @RW3+ RW2, addr16
MOVW
MOVW
RW3, @RW3+ RW3, addr16
MOVW
MOVW
RW5, @RW3+ RW5, addr16
MOVW
MOVW
RW5, @RW2+ @PC+d16
MOVW
MOVW
RW6, @RW3+ RW6, addr16
MOVW
MOVW RW6,
RW6, @RW2+ @PC+d16
MOVW
MOVW
RW7, @RW3+ RW7, addr16
MOVW
MOVW RW7,
RW7, @RW2+ @PC+d16
MOVW RW7,
@RW1+RW7
MOVW
MOVW RW7,
RW7,@RW3 @RW3+d16
MOVW
MOVW RW7,
RW7,@RW2 @RW2+d16
MOVW
MOVW RW7,
RW7,@RW1 @RW1+d16
MOVW
MOVW RW7,
RW7,@RW0 @RW0+d16
MOVW
MOVW RW7,
RW7, RW7 @RW7+d8
MOVW
MOVW RW7,
RW7, RW6 @RW6+d8
MOVW
MOVW RW7,
RW7, RW5 @RW5+d8
MOVW
MOVW RW7,
RW7, RW4 @RW4+d8
MOVW RW6, MOVW
@RW1+RW7 RW7, @RW1+
MOVW
MOVW RW6,
RW6,@RW3 @RW3+d16
MOVW
MOVW RW6,
RW6,@RW2 @RW2+d16
MOVW
MOVW RW6,
RW6,@RW1 @RW1+d16
MOVW
MOVW RW6,
RW6,@RW0 @RW0+d16
MOVW
MOVW RW6,
RW6, RW7 @RW7+d8
MOVW
MOVW RW6,
RW6, RW6 @RW6+d8
MOVW
MOVW RW6,
RW6, RW5 @RW5+d8
MOVW
MOVW RW6,
RW6, RW4 @RW4+d8
MOVW
MOVW
@RW1+RW7 RW6, @RW1+
MOVW
MOVW RW5,
RW5, RW6 @RW6+d8
MOVW
MOVW RW5,
RW5, RW5 @RW5+d8
MOVW RW4, MOVW
@RW1+RW7 RW5, @RW1+
MOVW
MOVW
RW4, @RW3+ RW4, addr16
MOVW RW3, MOVW
@RW1+RW7 RW4, @RW1+
MOVW
MOVW RW5,
RW5,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW0 @RW0+d16 RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16 RW3,@RW0 @RW0+d16 RW4,@RW0 @RW0+d16
+8
MOVW RW2, MOVW
@RW1+RW7 RW3, @RW1+
MOVW
MOVW RW5,
RW5,@RW1 @RW1+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
MOVW
MOVW
RW0, RW7 @RW7+d8
+7
MOVW RW1, MOVW
@RW1+RW7 RW2, @RW1+
MOVW
MOVW RW5,
RW5,@RW0 @RW0+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
MOVW
MOVW
RW0, RW6 @RW6+d8
+6
MOVW
MOVW
@RW1+RW7 RW1, @RW1+
MOVW
MOVW RW5,
RW5, RW7 @RW7+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
MOVW
MOVW
RW0, RW5 @RW5+d8
+5
MOVW
MOVW RW5,
RW5, RW4 @RW4+d8
MOVW
MOVW RW7,
RW7, RW3 @RW3+d8
MOVW
MOVW RW7,
RW7, RW2 @RW2+d8
MOVW
MOVW RW7,
RW7, RW1 @RW1+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
MOVW
MOVW RW6,
RW6, RW3 @RW3+d8
MOVW
MOVW RW6,
RW6, RW2 @RW2+d8
MOVW
MOVW RW6,
RW6, RW1 @RW1+d8
MOVW
MOVW
RW0, RW4 @RW4+d8
MOVW
MOVW RW5,
RW5, RW3 @RW3+d8
MOVW
MOVW RW5,
RW5, RW2 @RW2+d8
MOVW
MOVW RW5,
RW5, RW1 @RW1+d8
+4
F0
MOVW
MOVW RW7,
RW7, RW0 @RW0+d8
E0
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
D0
MOVW
MOVW RW6,
RW6, RW0 @RW0+d8
C0
MOVW
MOVW
RW0, RW3 @RW3+d8
B0
MOVW
MOVW RW5,
RW5, RW0 @RW0+d8
A0
+3
90
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
80
MOVW
MOVW
RW0, RW2 @RW2+d8
70
+2
60
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
50
MOVW
MOVW
RW0, RW1 @RW1+d8
40
+1
30
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
20
MOVW
MOVW
RW0, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-17 MOVW RWi, ea Instruction (First Byte = 7BH)
+F
+E
+D
+C
+B
+A
+9
+8
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R1 addr16, R1
MOV
MOV
@RW3+, R0 addr16, R0
MOV
MOV
MOV
@RW2+, R1 @PC+d16, R1
@RW2+, R0 @PC+d16, R0
MOV
MOV
MOV
MOV
MOV
@RW0+, R1 @RW0+RW7, R1
MOV
@RW3, R1 @RW3+d16, R1
MOV
@RW2, R1 @RW2+d16, R1
MOV
@RW1, R1 @RW1+d16, R1
MOV
@RW1+, R1 @RW1+RW7, R1
MOV
MOV
@RW0, R1 @RW0+d16, R1
MOV
@RW1+, R0 @RW1+RW7, R0
MOV
@RW0+, R0 @RW0+RW7, R0
MOV
@RW3, R0 @RW3+d16, R0
MOV
@RW2, R0 @RW2+d16, R0
MOV
@RW1, R0 @RW1+d16, R0
MOV
@RW0, R0 @RW0+d16, R0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R2 addr16, R2
MOV
@RW2+, R2 @PC+d16, R2
MOV
@RW1+, R2 @RW1+RW7, R2
MOV
@RW0+, R2 @RW0+RW7, R2
MOV
@RW3, R2 @RW3+d16, R2
MOV
@RW2, R2 @RW2+d16, R2
MOV
@RW1, R2 @RW1+d16, R2
MOV
@RW0, R2 @RW0+d16, R2
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R3 addr16, R3
MOV
@RW2+, R3 @PC+d16, R3
MOV
@RW1+, R3 @RW1+RW7, R3
MOV
@RW0+, R3 @RW0+RW7, R3
MOV
@RW3, R3 @RW3+d16, R3
MOV
@RW2, R3 @RW2+d16, R3
MOV
@RW1, R3 @RW1+d16, R3
MOV
@RW0, R3 @RW0+d16, R3
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R4 addr16, R4
MOV
@RW2+, R4 @PC+d16, R4
MOV
@RW1+, R4 @RW1+RW7, R4
MOV
@RW0+, R4 @RW0+RW7, R4
MOV
@RW3, R4 @RW3+d16, R4
MOV
@RW2, R4 @RW2+d16, R4
MOV
@RW1, R4 @RW1+d16, R4
MOV
@RW0, R4 @RW0+d16, R4
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R5 addr16, R5
MOV
@RW2+, R5 @PC+d16, R5
MOV
@RW1+, R5 @RW1+RW7, R5
MOV
@RW0+, R5 @RW0+RW7, R5
MOV
@RW3, R5 @RW3+d16, R5
MOV
@RW2, R5 @RW2+d16, R5
MOV
@RW1, R5 @RW1+d16, R5
MOV
@RW0, R5 @RW0+d16, R5
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R6 addr16, R6
MOV
@RW2+, R6 @PC+d16, R6
MOV
@RW1+, R6 @RW1+RW7, R6
MOV
@RW0+, R6 @RW0+RW7, R6
MOV
@RW3, R6 @RW3+d16, R6
MOV
@RW2, R6 @RW2+d16, R6
MOV
@RW1, R6 @RW1+d16, R6
MOV
@RW0, R6 @RW0+d16,
R6
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R7 addr16, R7
MOV
@RW2+, R7 @PC+d16, R7
MOV
@RW1+, R7 @RW1+RW7, R7
MOV
@RW0+, R7 @RW0+RW7, R7
MOV
@RW3, R7 @RW3+d16, R7
MOV
@RW2, R7 @RW2+d16, R7
MOV
@RW1, R7 @RW1+d16, R7
MOV
@RW0, R7 @RW0+d16, R7
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R7, R0 @RW7+d8, R0
R7, R1 @RW7+d8, R1
R7, R2 @RW7+d8, R2
R7, R3 @RW7+d8, R3
R7, R4 @RW7+d8, R4
R7, R5 @RW7+d8, R5
R7, R6 @RW7+d8, R6
R7, R7 @RW7+d8, R7
F0
+7
E0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R6, R0 @RW6+d8, R0
R6, R1 @RW6+d8, R1
R6, R2 @RW6+d8, R2
R6, R3 @RW6+d8, R3
R6, R4 @RW6+d8, R4
R6, R5 @RW6+d8, R5
R6, R6 @RW6+d8, R6
R6, R7 @RW6+d8, R7
D0
+6
C0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R5, R0 @RW5+d8, R0
R5, R1 @RW5+d8, R1
R5, R2 @RW5+d8, R2
R5, R3 @RW5+d8, R3
R5, R4 @RW5+d8, R4
R5, R5 @RW5+d8, R5
R5, R6 @RW5+d8, R6
R5, R7 @RW5+d8, R7
B0
+5
A0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R4, R0 @RW4+d8, R0
R4, R1 @RW4+d8, R1
R4, R2 @RW4+d8, R2
R4, R3 @RW4+d8, R3
R4, R4 @RW4+d8, R4
R4, R5 @RW4+d8, R5
R4, R6 @RW4+d8, R6
R4, R7 @RW4+d8, R7
90
+4
80
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R3, R0 @RW3+d8, R0
R3, R1 @RW3+d8, R1
R3, R2 @RW3+d8, R2
R3, R3 @RW3+d8, R3
R3, R4 @RW3+d8, R4
R3, R5 @RW3+d8, R5
R3, R6 @RW3+d8, R6
R3, R7 @RW3+d8, R7
70
+3
60
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R2, R0 @RW2+d8, R0
R2, R1 @RW2+d8, R1
R2, R2 @RW2+d8, R2
R2, R3 @RW2+d8, R3
R2, R4 @RW2+d8, R4
R2, R5 @RW2+d8, R5
R2, R6 @RW2+d8, R6
R2, R7 @RW2+d8, R7
50
+2
40
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R1, R0 @RW1+d8, R0
R1, R1 @RW1+d8, R1
R1, R2 @RW1+d8, R2
R1, R3 @RW1+d8, R3
R1, R4 @RW1+d8, R4
R1, R5 @RW1+d8, R5
R1, R6 @RW1+d8, R6
R1, R7 @RW1+d8, R7
30
+1
20
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R0, R0 @RW0+d8, R0
R0, R1 @RW0+d8, R1
R0, R2 @RW0+d8, R2
R0, R3 @RW0+d8, R3
R0, R4 @RW0+d8, R4
R0, R5 @RW0+d8, R5
R0, R6 @RW0+d8, R6
R0, R7 @RW0+d8, R7
10
+0
00
APPENDIX B Instructions
Table B.9-18 MOV ea, Ri Instruction (First Byte = 7CH)
465
466
MOVW
[email protected]
@RW2, RW1 +d16, RW1
MOVW
[email protected]
@RW3, RW1 +d16, RW1
MOVW
[email protected]
@RW0+, RW1 +RW7,RW1
MOVW
[email protected]
@RW1+,RW1 +RW7,RW1
MOVW
[email protected]
@RW2+,RW1 +d16, RW1
MOVW
MOVW
@RW3+,RW1 addr16, RW1
MOVW
[email protected]
@RW2, RW0 +d16, RW0
MOVW
[email protected]
@RW3, RW0 +d16, RW0
MOVW
[email protected]
@RW0+,RW0 +RW7,RW0
MOVW
[email protected]
@RW1+,RW0 +RW7,RW0
MOVW
[email protected]
@RW2+,RW0 +d16, RW0
MOVW
MOVW
@RW3+,RW0 addr16, RW0
+B
+C
+D
+E
+F
MOVW
MOVW
@RW3+,RW2 addr16, RW2
MOVW
[email protected]
@RW2+,RW2 +d16, RW2
MOVW
[email protected]
@RW1+,RW2 +RW7,RW2
MOVW
[email protected]
@RW0+,RW2 +RW7,RW2
MOVW
[email protected]
@RW3, RW2 +d16, RW2
MOVW
[email protected]
@RW2, RW2 +d16, RW2
MOVW
MOVW
@RW3+,RW3 addr16, RW3
MOVW
[email protected]
@RW2+,RW3 +d16, RW3
MOVW
[email protected]
@RW1+,RW3 -+RW7,RW3
MOVW
[email protected]
@RW0+,RW3 +RW7,RW3
MOVW
[email protected]
@RW3, RW3 +d16, RW3
MOVW
[email protected]
@RW2, RW3 +d16, RW3
MOVW
[email protected]
@RW1, RW3 +d16, RW3
MOVW
MOVW
@RW3+,RW4 addr16, RW4
MOVW
[email protected]
@RW2+,RW4 +d16, RW4
MOVW
[email protected]
@RW1+,RW4 +RW7,RW4
MOVW
[email protected]
@RW0+,RW4 +RW7,RW4
MOVW
[email protected]
@RW3, RW4 +d16, RW4
MOVW
[email protected]
@RW2, RW4 +d16, RW4
MOVW
[email protected]
@RW1, RW4 +d16, RW4
MOVW
MOVW
@RW3+,RW5 addr16, RW5
MOVW
[email protected]
@RW2+,RW5 +d16, RW5
MOVW
[email protected]
@RW1+,RW5 +RW7,RW5
MOVW
[email protected]
@RW0+,RW5 +RW7,RW5
MOVW
[email protected]
@RW3, RW5 +d16, RW5
MOVW
[email protected]
@RW2, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW5 +d16, RW5
MOVW
MOVW
@RW3+,RW6 addr16, RW6
MOVW
MOVW @PC
@RW2+,RW6 +d16, RW6
MOVW
[email protected]
@RW1+,RW6 +RW7,RW6
MOVW
[email protected]
@RW0+,RW6 +RW7,RW6
MOVW
[email protected]
@RW3, RW6 +d16, RW6
MOVW
[email protected]
@RW2, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW6 +d16, RW6
MOVW
MOVW
@RW3+,RW7 addr16, RW7
MOVW
[email protected]
@RW2+,RW7 +d16, RW7
MOVW
[email protected]
@RW1+,RW7 +RW7,RW7
MOVW
[email protected]
@RW0+,RW7 +RW7,RW7
MOVW
[email protected]
@RW3, RW7 +d16, RW7
MOVW
[email protected]
@RW2, RW7 +d16, RW7
MOVW
[email protected]
@RW1, RW7 +d16, RW7
MOVW
[email protected]
@RW0, RW7 +d16, RW7
+A
MOVW
[email protected]
@RW1, RW2 +d16, RW2
MOVW
[email protected]
@RW0, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW1 +d16, RW1
MOVW
[email protected]
@RW0, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW0 +d16, RW0
MOVW
[email protected]
@RW0, RW4 +d16, RW4
+9
MOVW
[email protected]
@RW0, RW3 +d16, RW3
MOVW
[email protected]
@RW0, RW1 +d16, RW1
MOVW
[email protected]
@RW0, RW0 +d16, RW0
+8
MOVW
[email protected]
@RW0, RW2 +d16, RW2
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW7, RW0 @RW7+d8, RW0
RW7, RW1 @RW7+d8, RW1 RW7, RW2 @RW7+d8, RW2 RW7, RW3 @RW7+d8, RW3 RW7, RW4 @RW7+d8, RW4 RW7, RW5 @RW7+d8, RW5 RW7, RW6 @RW7+d8, RW6 RW7, RW7 @RW7+d8, RW7
F0
+7
E0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW6, RW0 @RW6+d8, RW0
RW6, RW1 @RW6+d8, RW1 RW6, RW2 @RW6+d8, RW2 RW6, RW3 @RW6+d8, RW3 RW6, RW4 @RW6+d8, RW4 RW6, RW5 @RW6+d8, RW5 RW6, RW6 @RW6+d8, RW6 RW6, RW7 @RW6+d8, RW7
D0
+6
C0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW5, RW0 @RW5+d8, RW0
RW5, RW1 @RW5+d8, RW1 RW5, RW2 @RW5+d8, RW2 RW5, RW3 @RW5+d8, RW3 RW5, RW4 @RW5+d8, RW4 RW5, RW5 @RW5+d8, RW5 RW5, RW6 @RW5+d8, RW6 RW5, RW7 @RW5+d8, RW7
B0
+5
A0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW4, RW0 @RW4+d8, RW0
RW4, RW1 @RW4+d8, RW1 RW4, RW2 @RW4+d8, RW2 RW4, RW3 @RW4+d8, RW3 RW4, RW4 @RW4+d8, RW4 RW4, RW5 @RW4+d8, RW5 RW4, RW6 @RW4+d8, RW6 RW4, RW7 @RW4+d8, RW7
90
+4
80
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW3, RW0 @RW3+d8, RW0
RW3, RW1 @RW3+d8, RW1 RW3, RW2 @RW3+d8, RW2 RW3, RW3 @RW3+d8, RW3 RW3, RW4 @RW3+d8, RW4 RW3, RW5 @RW3+d8, RW5 RW3, RW6 @RW3+d8, RW6 RW3, RW7 @RW3+d8, RW7
70
+3
60
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW2, RW0 @RW2+d8, RW0
RW2, RW1 @RW2+d8, RW1 RW2, RW2 @RW2+d8, RW2 RW2, RW3 @RW2+d8, RW3 RW2, RW4 @RW2+d8, RW4 RW2, RW5 @RW2+d8, RW5 RW2, RW6 @RW2+d8, RW6 RW2, RW7 @RW2+d8, RW7
50
+2
40
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW1, RW0 @RW1+d8, RW0
RW1, RW1 @RW1+d8, RW1 RW1, RW2 @RW1+d8, RW2 RW1, RW3 @RW1+d8, RW3 RW1, RW4 @RW1+d8, RW4 RW1, RW5 @RW1+d8, RW5 RW1, RW6 @RW1+d8, RW6 RW1, RW7 @RW1+d8, RW7
30
+1
20
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW0, RW0 @RW0+d8, RW0
RW0, RW1 @RW0+d8, RW1 RW0, RW2 @RW0+d8, RW2 RW0, RW3 @RW0+d8, RW3 RW0, RW4 @RW0+d8, RW4 RW0, RW5 @RW0+d8, RW5 RW0, RW6 @RW0+d8, RW6 RW0, RW7 @RW0+d8, RW7
10
+0
00
APPENDIX B Instructions
Table B.9-19 MOVW ea, Rwi Instruction (First Byte = 7DH)
XCH
XCH
XCH
XCH
R1,
XCH
XCH R1,
R1,@RW2 W2+d16, A
XCH
XCH
R2,
XCH
XCH R2,
R2,@RW2 W2+d16, A
XCH
XCH
R3,
XCH
XCH R3,
R3,@RW2 W2+d16, A
XCH
XCH
R4,
XCH
XCH R4,
R4,@RW2 W2+d16, A
XCH
XCH
R5,
XCH
XCH R5,
R5,@RW2 W2+d16, A
XCH
XCH
R6,
XCH
XCH R6,
R6,@RW2 W2+d16, A
XCH
XCH
R7,
XCH
XCH R7,
R7,@RW2 W2+d16, A
XCH
XCH
XCH
XCH
XCH
R1, XCH
XCH
R2, XCH
XCH
R3, XCH
XCH
R4, XCH
XCH
R5, XCH
XCH
R6, XCH
XCH
R7,
+F R0,@RW3+ R0, addr16
XCH
XCH
R1,@RW3+ R1, addr16
XCH
XCH
R2,@RW3+ R2, addr16
XCH
XCH
R3,@RW3+ R3, addr16
XCH
XCH
R4,@RW3+ R4, addr16
XCH
XCH
R5,@RW3+ R5, addr16
XCH
XCH
R6,@RW3+ R6, addr16
XCH
XCH
R7,@RW3+ R7, addr16
+E R0,@RW2+ @PC+d16 R1,@RW2+ @PC+d16 R2,@RW2+ @PC+d16 R3,@RW2+ @PC+d16 R4,@RW2+ @PC+d16 R5,@RW2+ @PC+d16 R6,@RW2+ @PC+d16 R7,@RW2+ @PC+d16
R0, XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW1+RW7 R1,@RW1+ @RW1+RW7 R2,@RW1+ @RW1+RW7 R3,@RW1+ @RW1+RW7 R4,@RW1+ @RW1+RW7 R5,@RW1+ @RW1+RW7 R6,@RW1+ @RW1+RW7 R7,@RW1+ @RW1+RW7
+D R0,@RW1+
XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW0+RW7 R1,@RW0+ @RW0+RW7 R2,@RW0+ @RW0+RW7 R3,@RW0+ @RW0+RW7 R4,@RW0+ @RW0+RW7 R5,@RW0+ @RW0+RW7 R6,@RW0+ @RW0+RW7 R7,@RW0+ @RW0+RW7
XCH
+C R0,@RW0+
+B R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
R0,
+A R0,@RW2 W2+d16, A
R0,
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
+9
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
+8
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
F0
+7
E0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH)
467
468
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2+ @PC+d16
RW1,@RW2+ @PC+d16
RW2,@RW2+ @PC+d16
RW3,@RW2+ @PC+d16
RW4,@RW2+ @PC+d16
RW5,@RW2+ @PC+d16
RW6,@RW2+ @PC+d16
RW7,@RW2+ @PC+d16
XCHW
XCHW
RW0,@RW3+ RW0, addr16
+E
+F
XCHW
XCHW
RW7,@RW3+ RW7, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW1+ @RW1+RW7 RW1,@RW1+ @RW1+RW7 RW2,@RW1+ @RW1+RW7 RW3,@RW1+ @RW1+RW7 RW4,@RW1+ @RW1+RW7 RW5,@RW1+ @RW1+RW7 RW6,@RW1+ @RW1+RW7 RW7,@RW1+ @RW1+RW7
+D
XCHW
XCHW
RW6,@RW3+ RW6, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
+C
XCHW
XCHW
RW5,@RW3+ RW5, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW3 @RW3+d16
RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16
RW3,@RW3 @RW3+d16
RW4,@RW3 @RW3+d16
RW5,@RW3 @RW3+d16
RW6,@RW3 @RW3+d16
RW7,@RW3 @RW3+d16
+B
XCHW
XCHW
RW4,@RW3+ RW4, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2 @RW2+d16
RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16
RW3,@RW2 @RW2+d16
RW4,@RW2 @RW2+d16
RW5,@RW2 @RW2+d16
RW6,@RW2 @RW2+d16
RW7,@RW2 @RW2+d16
+A
XCHW
XCHW
RW3,@RW3+ RW3, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW1 @RW1+d16
RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16
RW3,@RW1 @RW1+d16
RW4,@RW1 @RW1+d16
RW5,@RW1 @RW1+d16
RW6,@RW1 @RW1+d16
RW7,@RW1 @RW1+d16
+9
XCHW
XCHW
RW2,@RW3+ RW2, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW0 @RW0+d16
RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16
RW3,@RW0 @RW0+d16
RW4,@RW0 @RW0+d16
RW5,@RW0 @RW0+d16
RW6,@RW0 @RW0+d16
RW7,@RW0 @RW0+d16
+8
XCHW
XCHW
RW1,@RW3+ RW1, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW7 @RW7+d8
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
RW5, RW7 @RW7+d8
RW6, RW7 @RW7+d8
RW7, RW7 @RW7+d8
F0
+7
E0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW6 @RW6+d8
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
RW5, RW6 @RW6+d8
RW6, RW6 @RW6+d8
RW7, RW6 @RW6+d8
D0
+6
C0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW5 @RW5+d8
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
RW5, RW5 @RW5+d8
RW6, RW5 @RW5+d8
RW7, RW5 @RW5+d8
B0
+5
A0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW4 @RW4+d8
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
RW5, RW4 @RW4+d8
RW6, RW4 @RW4+d8
RW7, RW4 @RW4+d8
90
+4
80
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW3 @RW3+d8
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
RW5, RW3 @RW3+d8
RW6, RW3 @RW3+d8
RW7, RW3 @RW3+d8
70
+3
60
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW2 @RW2+d8
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
RW5, RW2 @RW2+d8
RW6, RW2 @RW2+d8
RW7, RW2 @RW2+d8
50
+2
40
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW1 @RW1+d8
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
RW5, RW1 @RW1+d8
RW6, RW1 @RW1+d8
RW7, RW1 @RW1+d8
30
+1
20
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW0 @RW0+d8
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
RW5, RW0 @RW0+d8
RW6, RW0 @RW0+d8
RW7, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-21 XCHW RWi, ea Instruction (First Byte = 7FH)
INDEX
INDEX
The index follows on the next page.
This is listed in alphabetic order.
469
INDEX
Index
Numerics
16-bit free-running timer ....................................... 170
16-bit free-running timer block diagram................ 173
16-bit free-running timer operation ....................... 177
16-bit free-running timer timing ............................ 178
16-bit I/O timer register ........................................ 172
16-bit I/O timer, block diagram of .........................171
16-bit reload timer (in internal clock mode), input pin
function of .................................................. 202
16-bit reload timer (with event count function), outline
of ................................................................194
16-bit reload timer register ................................... 196
16-bit reload timer, block diagram of.................... 195
16-bit reload timer, internal clock operation of ..... 201
16-bit reload timer, output pin function of............. 204
16-bit reload timer, underflow operation of........... 203
16-bit timer register (TMR)/16-bit reload register
(TMRLR) .................................................... 200
1M/2M-bit flash memory feature........................... 350
1M/2M-bit flash memory, sector configuration of . 351
24-bit operand specification ................................... 25
32-bit register indirect specification ........................ 25
8/16-bit PPG hardware, initial value of ................. 225
8/16-bit PPG output operation.............................. 221
8/16-bit PPG Pulses, controlling pin output of......223
8/16-bit PPG register............................................211
8/16-bit PPG, function of ......................................208
8/16-bit PPG, operation modes of ........................ 220
8/16-bit PPG, operation of.................................... 220
8/16-bit PPG, selecting count clock for ................ 222
A
A/D Control Status Register (ADCS1).................. 249
A/D converter register .......................................... 245
A/D converter, block diagram of........................... 244
A/D converter, features of .................................... 242
accumulator (A) ...................................................... 31
address generation type......................................... 23
address match detection function, block diagram of
................................................................... 338
address match detection function, operation of ... 341
address match detection function, system
configuration example of ............................ 342
Addressing .......................................................... 410
alternative mode...................................................352
470
analog input enable register................................. 243
analog input enable register (ADER) ................... 150
application example of UART0 ............................ 288
asynchronous (start-stop synchronized) mode data
transfer format ........................................... 307
asynchronous (start-stop synchronized) mode
receive operation ....................................... 307
asynchronous (start-stop synchronized) mode
transmit operation ...................................... 307
automatic ready function selection register (ARSR)
................................................................... 131
B
bank addressing type............................................. 26
bank select prefix ................................................... 40
block diagram........................................................... 5
block diagram of 8/16-bit PPG ............................. 209
buffer address pointer (BAP) ................................. 66
bus control signal selection register (ECSR) ....... 134
C
Calculating the Execution Cycle Count ............... 427
CLK asynchronous baud rate .............................. 277
CLK synchronous baud rate ................................ 277
CLK synchronous mod, control register setting for
................................................................... 308
CLK synchronous mode data transfer format ...... 308
CLK synchronous mode, end of communication in
................................................................... 309
CLK synchronous mode, start of communication in
................................................................... 309
clock generator, note on ........................................ 74
clock selection register (CKSCR)........................... 91
command sequence table.................................... 356
common register bank prefix (CMR) ...................... 41
compare registers 0 and 1 being used, output
waveform sample when ............................. 184
compare registers, output waveform sample with two
................................................................... 185
condition code register (CCR)................................ 34
continuous mode.................................................. 254
continuous mode, starting EI2OS in .................... 259
control status register........................................... 188
control status register (ADCS0) ........................... 246
conversion data protection................................... 263
INDEX
counter operation state ........................................ 205
CPU memory space, outline of .............................. 23
CPU, outline of....................................................... 22
D
data counter (DCT) ................................................ 64
data polling flag (DQ7) ......................................... 360
data registers (ADCR1 and ADCR0) ................... 252
delayed interrupt cause issuance/cancellation
register (DIRR)........................................... 229
delayed interrupt occurrence ............................... 230
delayed interrupt, block diagram of...................... 228
Description of Instruction Presentation Items and
Symbols .................................................... 430
Direct Addressing ................................................ 412
DIV A, Ri and DIVW A, RWi instruction, note on using
..................................................................... 43
DTP operation...................................................... 237
DTP request, switching between external interrupt
and............................................................. 238
DTP/External interrup, block diagram of .............. 232
DTP/External interrup, outline of.......................... 232
DTP/External interrupt register ............................ 233
DTP/external interrupt, note on using .................. 239
E
Effective Address Field ............................... 411, 429
EI2OS (extended intelligent I/O service) .............. 287
EI2OS, conversion using ..................................... 256
erasing chip.......................................................... 372
erasing flash memory........................................... 350
erasing sector ...................................................... 373
erasing sector in flash memory ............................ 373
exception due to execution of an undefined
instruction .................................................... 71
Execution Cycle Count ........................................ 426
extended intelligent I/O service (EI2OS) ........ 59, 316
extended intelligent I/O service (EI2OS), execution
time of the .................................................... 69
extended intelligent I/O service (EI2OS), operation
flow of .......................................................... 67
extended intelligent I/O service descriptor (ISD).... 64
extended serial I/O interface, interrupt function of
................................................................... 334
external address output control register (HACR) . 133
external clock ....................................................... 280
external event counter ......................................... 202
external interrupt operation .................................. 236
external interrupt request ..................................... 238
external interrupt request register ........................ 234
external level register ...........................................235
external memory access (bus pin control circuit) .129
external memory access control signal ................137
external memory access register..........................130
external memory access, block diagram of ..........129
external shift clock mode ......................................328
F
F2MC-16LX Instruction List .................................433
feature ......................................................................3
flag change disable prefix (NCC)............................41
flag set timing .......................................................311
flag set timing for a transmit operation .................286
flag set timings for a receive operation (in Mode 0, 1,
or 3) ............................................................284
flag set timings for a receive operation (in Mode 2)
...................................................................285
flash memory control signal..................................352
flash memory control status register (FMCS) .......354
flash memory mode ..............................................352
flash memory register ...........................................350
flash memory write/erase, detailed explanation of
...................................................................368
flash memory, writing data to................................370
flash memory, writing to........................................370
flash microcomputer programmer (power supplied
from programmer), example of minimum
connection to ..............................................396
flash microcomputer programmer (user power supply
used), example of minimum connection to
...................................................................394
flash security feature ............................................379
flow of data protection function (when EI2OS is use)
...................................................................264
FPT-100P-M05 package dimension .........................7
FPT-100P-M06 package dimension .........................6
G
general-purpose register ........................................30
H
handling the device.................................................18
hardware interrupt ..................................................51
hardware interrupt operation ..................................53
hardware interrupt operation, flow of ......................56
hardware interrupt request during writing to the inputoutput area ...................................................51
hardware interrupt, structure of ..............................51
hardware sequence flag .......................................358
hardware standby mode, releasing ......................107
471
INDEX
hardware standby mode, transition to .................. 107
hold function .........................................................141
I
i/o circuit ................................................................. 15
I/O map ................................................................400
I/O port register .................................................... 145
I/O ports, outline of............................................... 144
I/O register address pointer (IOA) .......................... 64
Indirect Addressing ............................................. 418
input capture ........................................................ 187
input capture (2 channel per one module) ........... 171
input capture block diagram ................................. 187
input capture data register ................................... 188
input capture fetch timing, sample of ...................190
input capture input timing ..................................... 191
input data register 0 (UIDR0) ............................... 273
input impedance ...................................................243
Instruction Types ................................................. 409
intelligent I/O service (EI2OS) function and interrupt
................................................................... 194
intermittent CPU operation ................................... 108
intermittent CPU operation function ....................... 84
internal and external clock ................................... 280
internal shift clock mode....................................... 328
interrupt control register (ICR)................................ 61
interrupt disable instruction .................................... 42
interrupt level mask register (ILM).......................... 35
interrupt request enable register .......................... 234
interrupt source ...................................................... 47
interrupt vector ....................................................... 49
interrupt, 8/16-bit PPG ......................................... 224
interrupt, intelligent I/O service (EI2OS) function and
................................................................... 194
interrupt, outline of ................................................. 46
interrupt/DTP cause register ................................ 234
interrupt/DTP enable register ............................... 234
L
low-power consumption mode................................ 98
low-power consumption mode, operation status of
................................................................... 100
low-power control circuit, block diagram of ............ 86
low-power control circuit, operation modes of ........ 84
low-power mode control register ............................ 87
low-power mode control register (LPMCR) ............ 88
low-power mode control register, access to ........... 90
472
M
main clock oscillation stabilization wait time .......... 84
MB90435 series product, overview of...................... 2
MB90F438L(S)/F439(S) serial programming
connection, basic configuration of ............. 386
memory access mode.......................................... 124
memory space in each bus mode ........................ 127
memory space map ............................................... 24
mode data ............................................................ 126
mode pin .............................................................. 125
multi-byte data allocation in memory space........... 28
multi-byte data, accessing ..................................... 28
multiple interrupt .................................................... 52
N
negative clock operation ...................................... 335
notes on using the conversion data protection
function ...................................................... 264
notes, evasion of.................................................... 44
O
operation after reset release .................................. 76
operation, note on ................................................ 228
oscillation clock frequency and serial clock input
frequency ................................................... 389
Outline of Interrupts ............................................... 46
output compare .................................................... 179
output compare (2 channel per one module) ....... 170
output compare block diagram............................. 179
output compare register ....................................... 180
output compare timing ......................................... 185
output compare, control status register of............ 181
output data register 0 (UODR0) ........................... 273
P
parity bit ............................................................... 282
pin assignment......................................................... 8
pin function............................................................. 10
PLL clock multiplication function ............................ 85
port data register (PDR)....................................... 146
port direction register (DDR) ................................ 147
PPG0 operation mode control register (PPGC0) . 212
PPG0, 1 clock selection register (PPG0/1) .......... 217
PPG1 operation mode control register (PPGC1) . 214
precautions for UART1 use.................................. 316
prefix code ............................................................. 42
prefix code, consecutive ........................................ 42
processor status (PS) ............................................ 34
INDEX
program address detection control status register
(PACSR) .................................................... 339
program address detection register (PADR0 and
PADR1)...................................................... 339
program counter (PC) ............................................ 37
program patch processing, example of................ 343
programming example of 1M/2M-bit flash memory
................................................................... 380
pseudo watch mode, releasing ............................ 103
pseudo watch mode, transition to ........................ 103
PT-100P-M06 Package Dimensions.................... 6, 7
pull-up control register (PUCR) ............................ 148
pull-up control register (PUCR), block diagram of
................................................................... 149
R
rate and data register 0 (URD0)........................... 274
read state, setting flash memory to...................... 369
ready function ...................................................... 139
receive operation ................................................. 287
recommended set ................................................ 128
register bank .......................................................... 38
register bank pointer (RP)...................................... 35
register saving onto stack ...................................... 52
releasing sleep mode........................................... 102
reload register (PRLL/PRLH) ............................... 219
reload value and pulse width, relationship between
8/16-bit PPG .............................................. 221
request level setting register ................................ 235
reset cause ............................................................ 80
reset cause occurrence.......................................... 75
reset input, register not initialized by...................... 77
reset state, setting flash memory to ..................... 369
restrictions on interrupt disable instruction and prefix
instruction .................................................... 42
ROM mirroring ÇÜunction selection module, block
diagram of.................................................. 346
ROM mirroring function selection register (ROMM)
................................................................... 347
S
sector erase timer flag (DQ3)............................... 364
sector, restarting erasing of flash memory........... 376
sector, suspending erasing of flash memory ....... 375
serial control register 1 (SCR1)............................ 297
serial I/O block diagram ....................................... 318
serial I/O operation....................................... 327, 329
serial I/O prescaler (SCDCR)............................... 326
serial I/O resister.................................................. 319
serial input data register 1 (SIDR1)/serial output data
register 1 (SODR1).....................................299
serial mode control register 0 (UMC)....................269
serial mode control status register (SMCS)..........320
serial mode register 1 (SMR1)..............................295
serial output data register 1 (SODR1) ..................299
serial programming connection (power supplied from
programmer), example of ...........................392
serial programming connection (user power supply
used), example of.......................................390
serial shift data register (SDR) .............................325
serial statu register 1 (SSR1) ...............................300
set timing of six flags ............................................283
shift operation Start/Stop timing ...........................331
single mode ..........................................................254
single mode, starting EI2OS in .............................257
sleep mode, transition to ......................................102
software interrupt....................................................57
software interrupt operation....................................57
software interrupt, note on......................................58
software interrupt, structure of................................57
special register .......................................................29
start-stop synchronized mode data transfer format
...................................................................307
start-stop synchronized mode receive operation..307
start-stop synchronized mode transmit operation.307
status flag during transmit and receive operation.287
status register0 (USR0) ........................................271
status transition diagram for low-power consumption
mode (one clock system parts) ..................119
status transition diagram for low-power consumption
mode (two clocks system parts) .................114
status transition for clock selection.........................94
stop mode.............................................................255
stop mode, releasing ............................................105
stop mode, starting EI2OS in................................261
stop mode, transition to ........................................105
structure..................................................................60
Structure of Instruction Map ................................447
switching between machine clock ..........................85
system configuration in mode 1............................315
T
timebase timer ......................................................156
timebase timer control register (TBTC) ................154
timebase timer register .........................................152
timebase timer, Block Diagram of.........................153
timer control register (TMSCR).............................197
timer counter control status register .....................175
473
INDEX
timer counter data register (TCDT) ...................... 174
timing limit exceeded flag (DQ5) .......................... 363
toggle bit 2 flag (DQ2) .......................................... 366
toggle bit flag (DQ6) ............................................. 362
transfer data format.............................................. 281
transition conditions in low-power consumption mode
................................................................... 109
UART1 prescaler control register (U1CDCR) ...... 302
UART1 register .................................................... 294
UART1 sample application (system configuration in
mode 1)...................................................... 315
UART1, features of .............................................. 292
user power supply........................................ 390, 394
user stack pointer (USP) and system stack pointer
(SSP) ........................................................... 33
U
UART block diagram ............................................267
UART0 operation mode ....................................... 276
UART0 register .................................................... 268
UART0, feature of ................................................ 266
UART1 block diagram .......................................... 293
UART1 clock selection ......................................... 304
UART1 communication flow chart ........................ 315
UART1 flag........................................................... 310
UART1 interrupt and flag set timing ..................... 311
UART1 interrupt source ....................................... 310
UART1 operating mode ....................................... 303
474
W
watch mode, releasing ......................................... 104
watch mode, transition to ..................................... 104
watch timer........................................................... 168
watch timer register.............................................. 164
watch timer, interval interrupt function of ............. 168
watch-dog timer control register (WDTC) ............ 160
watch-dog timer control register (WTC) ............... 166
watch-dog timer register ...................................... 158
watch-dog timer, activating .................................. 162
watch-dog timer, resetting.................................... 162
writing to flash memory ........................................ 350
CM44-10123-2E
FUJITSU MICROELECTRONICS • CONTROLLER MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90435 Series
HARDWARE MANUAL
July 2008 the second edition
Published
FUJITSU MICROELECTRONICS LIMITED
Edited
Strategic Business Development Dept.