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FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
CM44-10127-3E
F2MC-16LX
16-BIT MICROCONTROLLER
MB90895 Series
HARDWARE MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90895 Series
HARDWARE MANUAL
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU MICROELECTRONICS LIMITED
PREFACE
■ Purpose of this document and intended reader
We sincerely thank you for your continued use of Fujitsu semiconductor products.
The MB90895 series are proprietary 16-bit single-chip microcontrollers which can be incorporated
into ASICs (application specific ICs) and were developed as general-purpose products in the
F2MC-16LX family.
This manual describes the functions and operation of the MB90895 series and is intended for
engineers who intend to use MB90895 series microcontrollers to develop actual products. Please
read through this manual.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ Trademark
The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
■ Organization of this document
This manual contains the following 21 chapters and an appendix.
CHAPTER 1 Overview
This chapter describes the features and basic specifications of MB90895 series.
CHAPTER 2 Handling Devices
This chapter describes points to note when using the MB90895 series.
CHAPTER 3 CPU
This chapter explains the function and operation of the CPU.
CHAPTER 4 I/O PORT
This chapter describes the function and operation of the I/O port.
CHAPTER 5 Timebase Timer
This chapter describes the function and operation of the I/O port.
CHAPTER 6 Watchdog Timer
This chapter explains the functions and operation of the watchdog timer.
CHAPTER 7 16-bit I/O Timer
This chapter describes the function and operation of the 16-bit I/O timer.
CHAPTER 8 16-bit Reload Timer
This chapter describes the function and operation of the 16-bit reload timer.
CHAPTER 9 Watch Timer
This chapter explains the functions and operation of the watch timer.
CHAPTER 10 8-/16-bit PPG Timer
This section describes the functions and operations of the 8-/16-bit PPG timer.
CHAPTER 11 Delayed Interrupt Generation Module
This section describes the functions and operations of the delayed interrupt generation module.
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CHAPTER 12 DTP/External Interrupt Circuit
This section describes the functions and operations of the DTP/external interrupt.
CHAPTER 13 8-/10-bit A/D Converter
This section describes the functions and operations of the 8-/10-bit A/D converter.
CHAPTER 14 UART0
This section describes the functions and operations of the UART0.
CHAPTER 15 UART1
This section describes the functions and operations of the UART1.
CHAPTER 16 CAN Controller
This section describes the functions and operations of the CAN controller.
CHAPTER 17 Address Match Detecting Function
This section describes the functions and operations of the address match detecting function.
CHAPTER 18 ROM Mirror Function Selection Module
This section describes the functions and operations of the ROM mirror function selection
module
CHAPTER 19 512 KBIT FLASH MEMORY
This section describes the functions and operations of the 512 Kbit flash memory.
CHAPTER 20 Dual Operation Flash
This section describes the functions and operations of the dual operation flash.
CHAPTER 21 FLASH SERIAL PROGRAMMING CONNECTION EXAMPLE
This section describes the functions and operations of the flash serial programming
connection example.
APPENDIX
The appendixes include an I/O map, pin function index, interrupt vector index.
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©2003-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
CHAPTER 2
2.1
HANDLING DEVICES ................................................................................ 15
Precautions when Handling Devices ................................................................................................ 16
CHAPTER 3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
OVERVIEW ................................................................................................... 1
Features of the MB90895 series ......................................................................................................... 2
Product Lineup for MB90895 Series ................................................................................................... 4
Block Diagram of MB90895 Series ..................................................................................................... 7
Pin Assignment ................................................................................................................................... 8
Package Dimensions .......................................................................................................................... 9
Pin Description .................................................................................................................................. 10
I/O Circuit .......................................................................................................................................... 13
CPU ............................................................................................................ 19
Memory Space ..................................................................................................................................
Mapping of and Access to Memory Space ..................................................................................
Memory Map ................................................................................................................................
Addressing ...................................................................................................................................
Linear Addressing ........................................................................................................................
Bank Addressing .........................................................................................................................
Allocation of Multi-byte Data in Memory ......................................................................................
Dedicated Registers .........................................................................................................................
Dedicated Registers and General-purpose Register ...................................................................
Accumulator (A) ...........................................................................................................................
Stack Pointer (USP, SSP) ...........................................................................................................
Processor status (PS) ..................................................................................................................
Program counter (PC) .................................................................................................................
Direct page register (DPR) ..........................................................................................................
Bank Register (PCB, DTB, USB, SSB, and ADB) .......................................................................
General-purpose Register ................................................................................................................
Prefix Code .......................................................................................................................................
Bank select prefix (PCB, DTB, ADB, and SPB) ...........................................................................
Common register bank prefix (CMR) ...........................................................................................
Flag change inhibit prefix (NCC) .................................................................................................
Restrictions on Prefix Code .........................................................................................................
Interrupt ............................................................................................................................................
Interrupt Factor and Interrupt Vector ...........................................................................................
Interrupt Control Registers and Peripherals ................................................................................
Interrupt Control Register (ICR00 to ICR15) ...............................................................................
Function of Interrupt Control Register .........................................................................................
Hardware Interrupt .......................................................................................................................
Operation of Hardware Interrupt ..................................................................................................
Procedure for Use of Hardware Interrupt ....................................................................................
Multiple interrupts ........................................................................................................................
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24
25
26
27
29
31
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34
37
40
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53
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59
62
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69
72
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75
3.5.9
Software interrupt ........................................................................................................................ 77
3.5.10 Interrupts by extended intelligent I/O service (EI2OS) ................................................................. 78
3.5.11 EI2OS descriptor (ISD) ................................................................................................................ 80
3.5.12 Each Register of EI2OS Descriptor (ISD) .................................................................................... 82
3.5.13 Operation of EI2OS ...................................................................................................................... 85
3.5.14 Procedure for Use of EI2OS ........................................................................................................ 86
3.5.15 EI2OS Processing Time ............................................................................................................... 87
3.5.16 Exception Processing Interrupt .................................................................................................... 89
3.5.17 Time Required to Start Interrupt Processing ............................................................................... 90
3.5.18 Stack Operation for Interrupt Processing .................................................................................... 92
3.5.19 Program Example of Interrupt Processing ................................................................................... 93
3.6
Reset ................................................................................................................................................ 96
3.6.1
Reset Factors and Oscillation Stabilization Wait Times .............................................................. 98
3.6.2
External Reset Pin ..................................................................................................................... 100
3.6.3
Reset Operation ........................................................................................................................ 101
3.6.4
Reset Factor Bit ......................................................................................................................... 103
3.6.5
State of Each Pin at Reset ........................................................................................................ 106
3.7
Clock ............................................................................................................................................... 107
3.7.1
Block Diagram of Clock Generation Section ............................................................................. 110
3.7.2
Register in Clock Generation Section ........................................................................................ 112
3.7.3
Clock select register (CKSCR) .................................................................................................. 113
3.7.4
PLL/subclock control register (PSCCR) .................................................................................... 116
3.7.5
Clock Mode ................................................................................................................................ 118
3.7.6
Oscillation Stabilization Wait Time ............................................................................................ 122
3.7.7
Connection of Oscillator and External Clock ............................................................................. 123
3.8
Low-power Consumption Mode ...................................................................................................... 124
3.8.1
Block Diagram of Low-power Consumption Circuit ................................................................... 127
3.8.2
Registers for Setting Low-power Consumption Modes ............................................................. 129
3.8.3
Low-power consumption mode control register (LPMCR) ......................................................... 130
3.8.4
CPU Intermittent operation mode .............................................................................................. 133
3.8.5
Standby Mode ........................................................................................................................... 134
3.8.6
State Transition in Standby Mode ............................................................................................. 146
3.8.7
Pin State in Standby Mode, at Reset ......................................................................................... 147
3.8.8
Precautions when Using Low-power Consumption Mode ......................................................... 148
3.9
CPU Mode ...................................................................................................................................... 152
3.9.1
Mode Pins (MD2 to MD0) .......................................................................................................... 153
3.9.2
Mode Data ................................................................................................................................. 155
3.9.3
Memory Access Mode ............................................................................................................... 157
3.9.4
Operations for Selecting Memory Access Mode ....................................................................... 158
CHAPTER 4
4.1
4.2
4.3
4.3.1
4.3.2
4.4
I/O PORT .................................................................................................. 159
Overview of I/O Ports ......................................................................................................................
Registers of I/O Port and Assignment of Pins Serving as External Bus .........................................
Port 1 ..............................................................................................................................................
Registers for Port 1 (PDR1, DDR1) ...........................................................................................
Operation of Port 1 ....................................................................................................................
Port2 ...............................................................................................................................................
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161
162
164
165
167
4.4.1
4.4.2
4.5
4.5.1
4.5.2
4.6
4.6.1
4.6.2
4.7
4.7.1
4.7.2
4.8
Registers for Port 2 (PDR2, DDR2) ...........................................................................................
Operation of Port 2 ....................................................................................................................
Port 3 ..............................................................................................................................................
Registers for Port 3 (PDR3, DDR3) ...........................................................................................
Operation of Port 3 ....................................................................................................................
Port 4 ..............................................................................................................................................
Registers for Port 4 (PDR4, DDR4) ...........................................................................................
Operation of Port 4 ....................................................................................................................
Port 5 ..............................................................................................................................................
Registers for Port 5 (PDR5, DDR5, ADER) ...............................................................................
Operation of Port 5 ....................................................................................................................
Port input level select register .........................................................................................................
CHAPTER 5
5.1
5.2
5.3
5.3.1
5.4
5.5
5.6
5.7
6.1
6.2
6.3
6.3.1
6.4
6.5
6.6
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196
197
199
200
204
205
WATCHDOG TIMER ................................................................................ 207
Overview of Watchdog Timer .........................................................................................................
Configuration of Watchdog Timer ...................................................................................................
Watchdog Timer Registers .............................................................................................................
Watchdog timer control register (WDTC) ..................................................................................
Explanation of Operations of Watchdog Timer Functions ..............................................................
Precautions when Using Watchdog Timer ......................................................................................
Program Examples of Watchdog Timer ..........................................................................................
CHAPTER 7
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.4
7.5
7.6
7.7
7.8
TIMEBASE TIMER ................................................................................... 191
Overview of Timebase Timer ..........................................................................................................
Block Diagram of Timebase Timer .................................................................................................
Configuration of Timebase Timer ...................................................................................................
Timebase timer control register (TBTC) ....................................................................................
Interrupt of Timebase Timer ...........................................................................................................
Explanation of Operations of Timebase Timer Functions ...............................................................
Precautions when Using Timebase Timer ......................................................................................
Program Example of Timebase Timer ............................................................................................
CHAPTER 6
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171
173
175
176
178
180
181
183
186
188
190
208
209
211
212
214
217
218
16-bit I/O TIMER ...................................................................................... 219
Overview of 16-bit Input/Output Timer ............................................................................................
Block Diagram of 16-bit Input/Output Timer ...................................................................................
Block Diagram of 16-bit Free-run Timer ....................................................................................
Block Diagram of Input Capture ................................................................................................
Configuration of 16-bit Input/Output Timer .....................................................................................
Timer counter control status register (TCCS) ............................................................................
Timer counter data register (TCDT) ..........................................................................................
Input capture control status registers (ICS01, ICS23) ...............................................................
Input capture data registers (IPCP0 to IPCP3) ..........................................................................
Interrupts of 16-bit Input/Output Timer ............................................................................................
Explanation of Operation of 16-bit Free-run Timer .........................................................................
Explanation of Operation of Input Capture .....................................................................................
Precautions when Using 16-bit Input/Output Timer ........................................................................
Program Example of 16-bit Input/Output Timer ..............................................................................
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221
222
224
226
229
231
233
235
236
237
239
242
243
CHAPTER 8
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.4
8.5
8.5.1
8.5.2
8.6
8.7
Overview of 16-bit Reload Timer ....................................................................................................
Block Diagram of 16-bit Reload Timer ............................................................................................
Configuration of 16-bit Reload Timer ..............................................................................................
Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H) ...........................................
Timer Control Status Registers (Low) (TMCSR0: L, TMCSR1: L) .............................................
16-bit Timer Registers (TMR0, TMR1) ......................................................................................
16-bit Reload Registers (TMRLR0, TMRLR1) ...........................................................................
Interrupts of 16-bit Reload Timer ....................................................................................................
Explanation of Operation of 16-bit Reload Timer ............................................................................
Operation in Internal Clock Mode ..............................................................................................
Operation in Event Count Mode ................................................................................................
Precautions when Using 16-bit Reload Timer ................................................................................
Program Example of 16-bit Reload Timer ......................................................................................
CHAPTER 9
9.1
9.2
9.3
9.3.1
9.4
9.5
9.6
16-bit RELOAD TIMER ............................................................................ 245
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249
252
255
257
259
260
261
262
264
269
272
273
WATCH TIMER ........................................................................................ 277
Overview of Watch Timer ...............................................................................................................
Block Diagram of Watch Timer .......................................................................................................
Configuration of Watch Timer .........................................................................................................
Watch timer control register (WTC) ...........................................................................................
Watch Timer Interrupt .....................................................................................................................
Explanation of Operation of Watch Timer .......................................................................................
Program Example of Watch Timer ..................................................................................................
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282
283
285
286
288
CHAPTER 10 8/16-bit PPG TIMER ................................................................................. 289
10.1 Overview of 8-/16-bit PPG Timer ....................................................................................................
10.2 Block Diagram of 8-/16-bit PPG Timer ...........................................................................................
10.2.1 Block Diagram for 8-/16-bit PPG Timer 0 ..................................................................................
10.2.2 Block Diagram of 8-/16-bit PPG Timer 1 ...................................................................................
10.3 Configuration of 8-/16-bit PPG Timer .............................................................................................
10.3.1 PPG0 Operation Mode Control Register (PPGC0) ....................................................................
10.3.2 PPG1 Operation Mode Control Register (PPGC1) ....................................................................
10.3.3 PPG0/1 count clock select register (PPG01) .............................................................................
10.3.4 PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1) ..........................................................
10.4 Interrupts of 8-/16-bit PPG Timer ....................................................................................................
10.5 Explanation of Operation of 8-/16-bit PPG Timer ...........................................................................
10.5.1 8-bit PPG output 2-channel independent operation mode ........................................................
10.5.2 16-bit PPG output mode ............................................................................................................
10.5.3 8 + 8-bit PPG output mode ........................................................................................................
10.6 Precautions when Using 8-/16-bit PPG Timer ................................................................................
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299
301
303
305
307
308
310
311
313
316
319
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE .................................. 321
11.1 Overview of Delayed Interrupt Generation Module .........................................................................
11.2 Block Diagram of Delayed Interrupt Generation Module ................................................................
11.3 Configuration of Delayed Interrupt Generation Module ..................................................................
11.3.1 Delayed interrupt request generate/cancel register (DIRR) ......................................................
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323
324
325
11.4
11.5
11.6
Explanation of Operation of Delayed Interrupt Generation Module ................................................ 326
Precautions when Using Delayed Interrupt Generation Module ..................................................... 327
Program Example of Delayed Interrupt Generation Module ........................................................... 328
CHAPTER 12 DTP/EXTERNAL INTERRUPT ................................................................. 329
12.1 Overview of DTP/External Interrupt ................................................................................................
12.2 Block Diagram of DTP/External Interrupt ........................................................................................
12.3 Configuration of DTP/External Interrupt ..........................................................................................
12.3.1 DTP/external interrupt factor register (EIRR) ............................................................................
12.3.2 DTP/external interrupt enable register (ENIR) ...........................................................................
12.3.3 Detection Level Setting Register (ELVR) (High) ........................................................................
12.3.4 Detection Level Setting Register (ELVR) (Low) ........................................................................
12.4 Explanation of Operation of DTP/External Interrupt .......................................................................
12.4.1 External Interrupt Function ........................................................................................................
12.4.2 DTP Function .............................................................................................................................
12.5 Precautions when Using DTP/External Interrupt ............................................................................
12.6 Program Example of DTP/External Interrupt Function ...................................................................
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338
341
342
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345
CHAPTER 13 8/10-bit A/D CONVERTER ....................................................................... 349
13.1 Overview of 8-/10-bit A/D Converter ...............................................................................................
13.2 Block Diagram of 8-/10-bit A/D Converter ......................................................................................
13.3 Configuration of 8-/10-bit A/D Converter ........................................................................................
13.3.1 A/D Control Status Register (High) (ADCS: H) ..........................................................................
13.3.2 A/D Control Status Register (Low) (ADCS: L) ...........................................................................
13.3.3 A/D Data Register (High) (ADCR: H) .........................................................................................
13.3.4 A/D Data Register (Low) (ADCR: L) ..........................................................................................
13.3.5 Analog input enable register (ADER) ........................................................................................
13.4 Interrupt of 8-/10-bit A/D Converter ................................................................................................
13.5 Explanation of Operation of 8-/10-bit A/D Converter ......................................................................
13.5.1 Single-shot conversion mode ....................................................................................................
13.5.2 Continuous conversion mode ....................................................................................................
13.5.3 Pause-conversion mode ............................................................................................................
13.5.4 Conversion Using EI2OS Function ............................................................................................
13.5.5 A/D-converted Data Protection Function ...................................................................................
13.6 Precautions when Using 8-/10-bit A/D Converter ...........................................................................
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362
364
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368
369
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373
375
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379
CHAPTER 14 UART0 ...................................................................................................... 381
14.1 Overview of UART0 ........................................................................................................................
14.2 Block Diagram of UART0 ................................................................................................................
14.3 Configuration of UART0 ..................................................................................................................
14.3.1 Serial control register 0 (SCR0) .................................................................................................
14.3.2 Serial mode register 0 (SMR0) ..................................................................................................
14.3.3 Serial status register 0 (SSR0) ..................................................................................................
14.3.4 Serial Input Data Register 0 (SIDR0) and Serial Output Data Register 0 (SODR0) ..................
14.3.5 Communication Prescaler Control Register 0 (CDCR0) ............................................................
14.3.6 Serial edge select register 0 (SES0) .........................................................................................
14.4 Interrupt of UART0 ..........................................................................................................................
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384
387
389
391
393
395
397
399
400
14.4.1 Generation of Receive Interrupt and Timing of Flag Set ...........................................................
14.4.2 Generation of Transmit Interrupt and Timing of Flag Set ..........................................................
14.5 UART0 baud rate ............................................................................................................................
14.5.1 Baud rate by dedicated baud rate generator .............................................................................
14.5.2 Baud Rate by Internal Timer (16-bit Reload Timer) ...................................................................
14.5.3 Baud rate by external clock .......................................................................................................
14.6 Explanation of Operation of UART0 ...............................................................................................
14.6.1 Operation in asynchronous mode (operation mode 0 or 1) .......................................................
14.6.2 Operation at clock synchronous mode (operating mode 2) .......................................................
14.6.3 Bidirectional Communication Function (Operation Modes 0 and 2) ..........................................
14.6.4 Master/slave type communication function (multi processor mode) ..........................................
14.7 Precautions when using UART0 .....................................................................................................
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428
CHAPTER 15 UART1 ...................................................................................................... 429
15.1 Overview of UART1 ........................................................................................................................
15.2 Block Diagram of UART1 ................................................................................................................
15.3 Configuration of UART1 ..................................................................................................................
15.3.1 Serial control register 1 (SCR1) .................................................................................................
15.3.2 Serial mode register 1 (SMR1) ..................................................................................................
15.3.3 Serial status register 1 (SSR1) ..................................................................................................
15.3.4 Serial Input Data Register 1 (SIDR1) and Serial Output Data Register 1 (SODR1) ..................
15.3.5 Communication Prescaler Control Register 1 (CDCR1) ............................................................
15.4 Interrupt of UART1 ..........................................................................................................................
15.4.1 Generation of Receive Interrupt and Timing of Flag Set ...........................................................
15.4.2 Generation of Transmit Interrupt and Timing of Flag Set ..........................................................
15.5 UART1 Baud Rate ..........................................................................................................................
15.5.1 Baud rate by dedicated baud rate generator .............................................................................
15.5.2 Baud Rate by Internal Timer (16-bit Reload Timer) ...................................................................
15.5.3 Baud rate by external clock .......................................................................................................
15.6 Explanation of Operation of UART1 ...............................................................................................
15.6.1 Operation in Asynchronous Mode (Operation Mode 0 or 1) ......................................................
15.6.2 Operation in Clock Synchronous Mode (Operation Mode 2) .....................................................
15.6.3 Bidirectional Communication Function (Operation Modes 0 and 2) ..........................................
15.6.4 Master/Slave Type Communication Function (Multiprocessor Mode) .......................................
15.7 Precautions when Using UART1 ....................................................................................................
15.8 Program Example for UART1 .........................................................................................................
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460
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463
467
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471
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475
CHAPTER 16 CAN CONTROLLER ................................................................................ 477
16.1 Overview of CAN Controller ............................................................................................................
16.2 Block Diagram of CAN Controller ...................................................................................................
16.3 Configuration of CAN Controller .....................................................................................................
16.3.1 Control Status Register (High) (CSR: H) ...................................................................................
16.3.2 Control Status Register (Low) (CSR: L) ....................................................................................
16.3.3 Last event indication register (LEIR) .........................................................................................
16.3.4 Receive/Transmit Error Counter (RTEC) ...................................................................................
16.3.5 Bit timing register (BTR) ............................................................................................................
16.3.6 Message buffer validating register (BVALR) .............................................................................
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479
482
486
488
491
493
495
499
16.3.7 IDE register (IDER) ....................................................................................................................
16.3.8 Transmit request register (TREQR) ...........................................................................................
16.3.9 Transmit RTR register (TRTRR) ................................................................................................
16.3.10 Remote frame receive waiting register (RFWTR) ......................................................................
16.3.11 Transmission cancel register (TCANR) .....................................................................................
16.3.12 Transmit complete register (TCR) .............................................................................................
16.3.13 Transmit complete interrupt enable register (TIER) ..................................................................
16.3.14 Receive complete register (RCR) ..............................................................................................
16.3.15 Receive RTR register (RRTRR) ................................................................................................
16.3.16 Receive overrun register (ROVRR) ...........................................................................................
16.3.17 Receive complete interrupt enable register (RIER) ...................................................................
16.3.18 Acceptance mask select register (AMSR) .................................................................................
16.3.19 Acceptance Mask Select Register (AMR) .................................................................................
16.3.20 Message Buffers ........................................................................................................................
16.3.21 ID Register (IDRx, x = 7 to 0) ....................................................................................................
16.3.22 DLC Register (DLCR) ................................................................................................................
16.3.23 Data Register (DTR) ..................................................................................................................
16.4 Interrupts of CAN Controller ...........................................................................................................
16.5 Explanation of Operation of CAN Controller ...................................................................................
16.5.1 Transmission .............................................................................................................................
16.5.2 Reception ..................................................................................................................................
16.5.3 Procedures for Transmitting and Receiving ..............................................................................
16.5.4 Setting Multiple Message Reception .........................................................................................
16.6 Precautions when Using CAN Controller ........................................................................................
16.7 Program Example of CAN Controller ..............................................................................................
501
503
505
507
509
511
513
515
517
519
521
523
525
527
528
531
532
533
535
536
539
543
550
552
553
CHAPTER 17 ADDRESS MATCH DETECTING FUNCTION ......................................... 555
17.1 Overview of Address Match Detection Function .............................................................................
17.2 Block Diagram of Address Match Detection Function ....................................................................
17.3 Configuration of Address Match Detection Function ......................................................................
17.3.1 Address detection control register (PACSR) .............................................................................
17.3.2 Detect address setting registers (PADR0, PADR1) ...................................................................
17.4 Explanation of Operation of Address Match Detection Function ....................................................
17.4.1 Example of using Address Match Detection Function ...............................................................
17.5 Program Example of Address Match Detection Function ...............................................................
556
557
558
559
561
563
564
569
CHAPTER 18 ROM MIRRORING FUNCTION SELECTION MODULE .......................... 571
18.1
18.2
Overview of ROM Mirroring Function Selection Module ................................................................. 572
ROM Mirroring Function Selection Register (ROMM) .................................................................... 574
CHAPTER 19 512 KBIT FLASH MEMORY .................................................................... 575
19.1
19.2
19.3
19.4
19.5
19.6
Overview of 512 Kbit Flash Memory ...............................................................................................
Registers and Sector/Bank Configuration of Flash Memory ...........................................................
Flash Memory Control Status Register (FMCS) .............................................................................
Flash Memory Write Control Register (FWR0/1) ............................................................................
How to Start Automatic Algorithm of Flash Memory .......................................................................
Reset Vector Addresses in Flash Memory .....................................................................................
xi
576
577
579
582
587
589
19.7 Check the Execution State of Automatic Algorithm ........................................................................
19.7.1 Data Polling Flag (DQ7) ............................................................................................................
19.7.2 Toggle Bit Flag (DQ6) ................................................................................................................
19.7.3 Timing Limit Over Flag (DQ5) ....................................................................................................
19.7.4 Sector Erase Timer Flag (DQ3) .................................................................................................
19.7.5
Toggle Bit 2 Flag (DQ2) ............................................................................................................
19.8 Details of Programming/Erasing Flash Memory .............................................................................
19.8.1 Read/Reset State in Flash Memory ...........................................................................................
19.8.2 Data programming to flash memory ..........................................................................................
19.8.3 Data Erase from Flash Memory (Chip Erase) ...........................................................................
19.8.4
Erasing Any Data in Flash Memory (Sector Erasing) ...............................................................
19.8.5 Sector Erase Suspension ..........................................................................................................
19.8.6 Sector Erase Resumption ..........................................................................................................
590
592
594
595
596
597
599
600
601
603
604
606
607
CHAPTER 20 DUAL OPERATION FLASH ..................................................................... 609
20.1
20.2
20.3
Overview of Dual Operation Flash .................................................................................................. 610
Register for Dual Operation Flash .................................................................................................. 611
Operation of Dual Operation Flash ................................................................................................. 613
CHAPTER 21 CONNECTION EXAMPLE of FLASH SERIAL PROGRAMMING ........... 615
21.1
21.2
21.3
21.4
21.5
Basic Configuration of Serial Programming Connection for F2MC-16LX MB90F897/S .................
Connection Example for Single-chip Mode (User Power Supply) ..................................................
Connection Example for Single-chip Mode (Writer Power Supply) ................................................
Flash Microcontroller Programmer and Example of Minimum Connection (User Power Supply)
.........................................................................................................................................................
Flash Microcontroller Programmer and Example of Minimum Connection (Writer Power Supply)
.........................................................................................................................................................
616
619
621
623
625
APPENDIX ......................................................................................................................... 627
APPENDIX A Instructions ...........................................................................................................................
A.1 Instruction Types ............................................................................................................................
A.2 Addressing .....................................................................................................................................
A.3 Direct Addressing ...........................................................................................................................
A.4 Indirect Addressing ........................................................................................................................
A.5 Execution Cycle Count ...................................................................................................................
A.6 Effective address field ....................................................................................................................
A.7 How to Read the Instruction List ....................................................................................................
A.8 F2MC-16LX Instruction List ............................................................................................................
A.9 Instruction Map ...............................................................................................................................
APPENDIX B Register Index ......................................................................................................................
APPENDIX C Pin Function Index ...............................................................................................................
APPENDIX D Interrupt Vector Index ..........................................................................................................
xii
628
629
630
632
638
646
649
650
653
667
689
699
701
Main changes in this edition
Page
Changes (For details, refer to main body.)
5
CHAPTER 1 OVERVIEW
1.2 Product Lineup for
MB90895 Series
Changed Table 1.2-2 CPU and peripheral functions of MB90895 series
8/16-bit PPG timer.
(PPG operable with 8 bits × 4 channels or 16 bits × 1 channel →
PPG operable with 8 bits × 4 channels or 16 bits × 2 channels)
16
CHAPTER 2 HANDLING
DEVICES
2.1 Precautions when Handling Devices
Changed ● Handling un-used pins.
(unused input pins → unused I/O pins)
17
Changed ● Crystal oscillator circuit.
Added "• Please ask the crystal maker to evaluate the oscillational
characteristics of the crystal and this device."
Changed ● Procedure of A/D converter/analog input power-on.
(Deleted (The analog power and digital power can be simultaneously
turned on or off with no problem.).)
24
CHAPTER 3 CPU
3.1.2 Memory Map
Changed Figure 3.1-3 Memory Map of MB90895 Series.
83
CHAPTER 3 CPU
3.5.12 Each Register of EI2OS
Descriptor (ISD)
Changed bit4 of Figure 3.5-13 Configuration of EI2OS Status Register
(ISCS).
114
CHAPTER 3 CPU
3.7.3 Clock select register
(CKSCR)
Changed Table 3.7-1 Functions of clock select register (CKSCR).
146
CHAPTER 3 CPU
3.8.6 State Transition in
Standby Mode
Changed Figure 3.8-8 State Transition Diagram.
147
CHAPTER 3 CPU
3.8.7 Pin State in Standby
Mode, at Reset
Changed *2 of Table 3.8-6 State of Input/Output Pins (Single-chip Mode).
"In the input cut off state, the input is masked and "L" level is transmitted
internally. Output Hi-Z means that the driving of pin driving transistors is
disabled to place the pins in a high impedance state."
155
CHAPTER 3 CPU
3.9.2 Mode Data
Changed Figure 3.9-2 Mode Data.
230
Table 7.3-2 Functions of
Timer Counter Control Status
Register (TCCS)
Changed bit3 of Table 7.3-2 Functions of Timer Counter Control Status
Register (TCCS).
Added Note.
273
CHAPTER 8 16-bit RELOAD
TIMER
8.7 Program Example of 16-bit
Reload Timer
Changed ● Coding example.
(MOVW I:TMRLR0,#30D4H ;Setting of data in 25ms timer →
MOVW I:TMRLR0,#30D3H ;Setting of data in 25ms timer
318
CHAPTER 10 8/16-bit PPG
TIMER
10.5.3 8 + 8-bit PPG output
mode
Changed ● Operation in 8+8-bit PPG output operation mode.
(Output Waveform in 8+8-bit PPG Output Operation Mode →
Operation in 8+8-bit PPG output operation mode)
Changed Table 3.9-3 function of mode register.
xiii
Page
Changes (For details, refer to main body.)
334
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.3.1 DTP/external interrupt
factor register (EIRR)
Changed Table 12.3-2 Function of DTP/External Interrupt Factor Register
(EIRR).
335
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.3.2 DTP/external interrupt
enable register (ENIR)
Changed Table 12.3-3 Functions of DTP/External Interrupt Enable
Register (ENIR).
338
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.4 Explanation of Operation
of DTP/External Interrupt
Changed ● Setting procedure.
357,
358
CHAPTER 13 8/10-bit A/D
CONVERTER
13.3.1 A/D Control Status
Register (High) (ADCS: H)
Changed Table 13.3-2 Function of Each Bit of A/D Control Status Register
(High) (ADCS: H).
361
CHAPTER 13 8/10-bit A/D
CONVERTER
13.3.2 A/D Control Status
Register (Low) (ADCS: L)
Changed Table 13.3-3 Function of Each Bit of A/D Control Status Register
(Low) (ADCS: L).
392
CHAPTER 14 UART0
14.3.2 Serial mode register 0
(SMR0)
Changed Table 14.3-3 Functions of Serial Mode Register 0 (SMR0).
Added Note.
398
CHAPTER 14 UART0
14.3.5 Communication Prescaler Control Register 0
(CDCR0)
Changed ■ Communication Prescaler Control Register 0 (CDCR0).
Added Note.
428
CHAPTER 14 UART0
14.7 Precautions when using
UART0
Added ● Setting clock in clock synchronous mode.
440
CHAPTER 15 UART1
15.3.2 Serial mode register 1
(SMR1)
Changed bit3 to bit5 of Table 15.3-3 Functions of Serial Mode Register 1
(SMR1).
Added Note.
447
CHAPTER 15 UART1
15.3.5 Communication Prescaler Control Register 1
(CDCR1)
Changed ■ Communication Prescaler Control Register 1 (CDCR1) .
Added Note.
474
CHAPTER 15 UART1
15.7 Precautions when Using
UART1
Added ● Setting clock in clock synchronous mode.
490
CHAPTER 16 CAN CONTROLLER
16.3.2 Control Status Register
(Low) (CSR: L)
Changed bit0 of Table 16.3-3 Functions of Control Status Register (Low)
(CSR:L).
(for (i=0; (i<= 500) || (IO_CANCT0.CSR.bit.HALT= 0):i++); →
for (i=0; (i<= 500) && (IO_CANCT0.CSR.bit.HALT= 0):i++);)
xiv
Page
Changes (For details, refer to main body.)
606
CHAPTER 19 512 KBIT
FLASH MEMORY
19.8.5 Sector Erase Suspension
Changed ■ Note
(20ms → 20μs)
617
CHAPTER 21 CONNECTION EXAMPLE of FLASH
SERIAL PROGRAMMING
21.1 Basic Configuration of
Serial Programming Connection for F2MC-16LX
MB90F897/S
Changed the additional Information of the VCC pin of Table 21.1-1
in Used for Fujitsu Standard Serial On-board Programming.
634
A.3 Direct Addressing
● I/O direct addressing (io)
Changed Figure A.3-5.
(MOVW A, i : 0C0H → MOVW A, I:0C0H)
Added the note to Figure A.3-5.
635
A.3 Direct Addressing
● Abbreviated direct addressing (dir)
Added the note to Figure A.3-6.
636
A.3 Direct Addressing
● I/O direct bit addressing
(io:bp)
Changed Figure A.3-8.
(SETB i : 0C1H : 0 → SETB I:0C1H:0)
A.3 Direct Addressing
● Abbreviated direct bit
addressing (dir:bp)
Added the note to Figure A.3-9.
642
A.4 Indirect Addressing
● Program counter relative
branch addressing (rel)
Changed Figure A.4-7.
(BRA 10H → BRA 3C32H)
643
A.4 Indirect Addressing
● Register list (rlst)
Changed Figure A.4-9.
(POPW, RW0, RW4 → POPW RW0, RW4)
668
A.9 Instruction Map
■ Structure of Instruction Map
Changed column: instruction in Table A.9-1.
(@RW2+d8, #8, rel → CBNE @RW2+d8, #8, rel)
Added the note to Figure A.3-8.
xv
Page
669
Changes (For details, refer to main body.)
A.9 Instruction Map
Changed the operand at row: +0, column: E0 in Table A.9-2.
(#4 → #vct4)
Changed the mnemonic at row: +0, column: D0 in Table A.9-2.
(MOV → MOVN)
Changed the mnemonic at row: +0, column: B0 in Table A.9-2.
(MOV → MOVX)
Changed the mnemonic at row: +8, column: B0 in Table A.9-2.
(MOV → MOVW)
671
Changed the mnemonic at row: +0, column: E0 in Table A.9-4.
(FILSI → FILSWI)
672
Changed Table A.9-5.
(· Moved "MUL A" and "MULW A" instruction from column:60 to column:70.
· Changed mnemonic and moved the Instruction from column:60, row:+A
to column:70, row:+A.
(DIVU → DIV)
)
673
676
A.9 Instruction Map
Changed the operand at row: +E and +F, column: F0 in Table A.9-6.
(,#8, rel → #8, rel)
Changed the operand at row: +8 to +E, column: 50 in Table A.9-9.
(@@ → @)
Changed the operand at row: +0 to +7, column: 20 in Table A.9-9.
(RWi → @RWi)
677
Changed the operand at column: E0 and F0 in Table A.9-10.
(,r → ,rel)
678
Changed the operand at column: 70 in Table A.9-11.
(NEG A, → NEG)
679
Changed the operand at column: E0 and F0 in Table A.9-12.
(,r → ,rel)
The vertical lines marked in the left side of the page show the changes.
xvi
CHAPTER 1
OVERVIEW
This chapter describes the features and basic
specifications of MB90895 series.
1.1 Features of the MB90895 series
1.2 Product Lineup for MB90895 Series
1.3 Block Diagram of MB90895 Series
1.4 Pin Assignment
1.5 Package Dimensions
1.6 Pin Description
1.7 I/O Circuit
1
CHAPTER 1 OVERVIEW
1.1
Features of the MB90895 series
MB90895 series devices are 16-bit micro general-purpose controllers designed for
applications which need high-speed real-time processing. The devices of this series are
high-performance 16-bit CPU micro controllers employing of the dual operation flash
memory and CAN controller on LQFP-48 small package.
The instruction system is based on the architecture of the F2MC family and provides
additional high-level language instructions, extended addressing modes, enhanced
multiply/divide instructions, and enriched bit processing instructions. A 32-bit
accumulator enables long-word data (32 bits) processing.
■ Features of the MB90895 series
● Clock
• Built-in PLL clock multiplying circuit
• Machine clock (PLL clock) selectable from 1/2 frequency of oscillation clock or 1 to 4 multiples of
oscillation clock (4 MHz to 16 MHz when oscillation clock is 4 MHz)
• Sub clock operation (8.192 kHz) (MB90F897)
• Minimum instruction execution time: 62.5 ns (4-MHz oscillation clock, 4-multiplied PLL clock)
● 16-MB CPU memory space
• Internal 24-bit addressing
● Instruction system optimized for controllers
• Various data types (bit, byte, word, long word)
• 23 types of addressing modes
• Enhanced signed instructions of multiplication/division and RETI
• High-accuracy operations enhanced by 32-bit accumulator
● Instruction system for high-level language (C language)/multitask
• System stack pointer
• Enhanced pointer indirect instructions
• Barrel shift instructions
● Higher execution speed
• 4-byte instruction queue
● Powerful interrupt function
• Powerful interrupt function with 8 levels and 34 factors
● CPU-independent automatic data transfer function
• Extended intelligent I/O service (EI2OS): Maximum 16 channels
2
CHAPTER 1 OVERVIEW
● Low-power consumption (standby) mode
• Sleep mode (stops CPU clock)
• Timebase timer mode (operates only oscillation clock and sub clock, timebase timer and watch timer)
• Watch mode (operates only sub clock and watch timer)
• Stop mode (stops oscillation clock and sub clock)
• CPU Intermittent operation mode
● Process
• CMOS Technology
● I/O port
• General-purpose I/O ports (CMOS output): 34 ports (for MB90F897) (included 4 output ports for high
current) note: 36 ports (for MB90F897S) on condition of unusing sub-clock.
● Timers
• Timebase timer, watch timer, watchdog timer: 1 channel
• 8/16-bit PPG timer: 8 bits x 4 channels or 16 bits x 2 channels
• 16-bit reload timer: 2 channels
• 16-bit I/O timer
- 16-bit free-run timer: 1 channel
- 16-bit input capture (ICU): 4 channels
By detecting the edge of the pin input, the count value of the 16-bit free-run timer is latched to generate an
interrupt request.
● CAN Controller: 1 channel
• Conforms to CAN Specification Ver.2.0A and Ver.2.0B.
• Built-in 8 message buffers
• Transfer rate: 10 Kbps to 1 Mbps (at 16-MHz machine clock frequency)
• CAN wake-up
● UART0(SCI),UART1(SCI): 2 channel
• Full-duplex double buffer
• Clock asynchronous or clock synchronous serial transfer
● DTP/external interrupt: 4 channels, CAN wake-up: 1channel
• External input to start EI2OS and external interrupt generation module
● Delayed interrupt generation module
• Generates interrupt request for task switching
● 8-/10-bit A/D converter: 8 channels
• The resolution can be switched between 8 and 10 bits.
• Start by external trigger input
• Conversion time: 6.125μs (including sampling time at 16-MHz machine clock frequency)
● Program patch function
• Detects address match for two address pointers
3
CHAPTER 1 OVERVIEW
1.2
Product Lineup for MB90895 Series
MB90895 series is available in two types. This section provides the product lineup, CPU,
and peripherals.
■ Product Lineup for MB90895 Series
Table 1.2-1 Product Lineup for MB90895 Series
MB90V495G
MB90F897/S
Evaluation product
Flash ROM
ROM Size
−
64 KB
RAM Size
6 KB
2 KB
Classification
Clock
Dual-line model
Process
Package
CMOS
PGA256
LQFP-48 (with 0.50-mm pin pitch)
Operating supply voltage
4.5V to 5.5V
3.5V to 5.5V
Power supply for emulator*
Not provided
−
*:
4
MB90F897:Dual-line model
MB90F897S:Single-line model
Setting of DIP Switch (S2) when using emulation pod (MB2145-507). For details, refer to the MB2145-507
Hardware Manual (Section 2.7 Emulator-specific Power Supply).
CHAPTER 1 OVERVIEW
■ CPU and peripheral functions of MB90895 series
Table 1.2-2 CPU and peripheral functions of MB90895 series (1/2)
MB90V495G
CPU function
MB90F897/S
Number of basic instructions: 351 instructions
Instruction bit length: 8 bits, 16 bits
Instruction length: 1 byte to 7 bytes
Data bit length: 1 bit, 8 bits, 16 bits
Minimum instruction execution time: 62.5 ns (at a machine clock frequency of 16 MHz)
Interrupt operating time: Min 1.5 ms (at 16-MHz machine clock frequency)
Low-power consumption (standby) mode
Sleep mode/Watch mode/Timebase timer mode/Stop mode/CPU intermittent mode
I/O port
General-purpose I/O ports (CMOS output): 34 (36 *)
They include four pins serving as high-current output ports (P14 to P17).
Timebase timer
18-bit free-run counter
Interrupt cycle: 1.024ms,4.096ms,16.834ms,131.072ms
(Assuming an oscillation clock frequency of 4 MHz)
Watchdog timer
Reset generation cycle:3.58ms,14.33ms,57.23ms,458.75ms
(Assuming an oscillation clock frequency of 4 MHz)
16-bit I/O
timer
16-bit free-run timer
Channel count: 1
interrupt by overflow generation
Input capture
Channel count: 4
Free-run timer value held at pin input timing (rising edge, falling edge, both edges)
16-bit reload timer 1
Channel count: 2
16-bit reload timer operation
Count Clock Cycle: 0.25μs,0.5μs,2.0μs
(Assuming a machine clock frequency of 16 MHz)
External event countable
Watch timer
15-bit free-run counter
Interrupt cycle: 31.25ms,62.5ms,12ms,250ms,500ms,1.0s,2.0s
(Assuming a subclock frequency of 8.192 kHz)
8/16-bit PPG timer
Channel count: 2 (operable with 8 bits x 4 channels)
PPG operable with 8 bits x 4 channels or 16 bits x 2 channels
Pulse waveform output at arbitrary cycle and duty
Count clock: 62.5 ns to 1 μs
(Assuming a machine clock frequency of 16 MHz)
Delayed interrupt generation module
Interrupt generation module for task switching
Used for Real-time OS
DTP/external interrupt
Input count: 4
Capable of starting at the rising or falling edge or High or Low level input and of using
external interrupts and Extended Intelligent I/O Service (EI2OS)
5
CHAPTER 1 OVERVIEW
Table 1.2-2 CPU and peripheral functions of MB90895 series (2/2)
MB90V495G
8/10-bit A/D converter
Channel count: 8
Resolution: 10 or 8 bits
Conversion time: 6.125 μs (including sampling time at 16-MHz machine clock frequency)
Two or more continuous channels can be converted sequentially (up to 8 channels)
Single conversion mode: Selected channel converted once only
Continuous conversion mode: Selected channel converted continuously
Stop conversion mode: Selected channel converted and temporary stopped alternately
UART0 (SCI)
Channel count: 1
Clock synchronous transfer: 62.5 K bps to 2 M bps
Clock asynchronous transfer: 1,202 bps to 62,500 K bps
Two-way serial communication function, master/slave-connected communication
UART1 (SCI)
Channel count: 1
Clock synchronous transfer: 62.5 K bps to 2 M bps
Clock asynchronous transfer: 9,615 bps to 500 K bps
Two-way serial communication function, master/slave-connected communication
CAN
Conforms to CAN Specification Ver.2.0A and Ver.2.0B
Transmit/receive message buffer: 8
Transfer bit rate: 10 K bps to 1 M bps (at 16-MHz machine clock)
CAN wake-up
*: MB90F897S
6
MB90F897/S
CHAPTER 1 OVERVIEW
1.3
Block Diagram of MB90895 Series
Block diagram of MB90895 series is shown in the figure below.
■ Block Diagram of MB90895 Series
Figure 1.3-1 Block Diagram of MB90895 Series
X0,X1
RST
X0A,X1A
Clock controller
CPU
F2MC-16LX core
Watch timer
16-bit
free-run timer
Timebase timer
Input capture
(4ch)
IN0 to IN3
RAM
Prescaler
SOT1
SCK1
SIN1
UART1
Internal data bus
FLASH
16-bit PPG timer
(2ch)
CAN
DTP/external
interrupt
PPG0 to PPG3
RX
TX
INT4 to INT7
Prescaler
SOT0
SCK0
SIN0
UART0
16-bit reload timer
(2ch)
TIN0,TIN1
TOT0,TOT1
AVcc
AVss
AN0 to AN7
AVR
8/10-bit
A/D converter
(8ch)
ADTG
7
CHAPTER 1 OVERVIEW
1.4
Pin Assignment
Pin assignment of MB90895 series is shown in the figure below.
■ Pin Assignment (FPT-48P-M26)
48
47
46
45
44
43
42
41
40
39
38
37
AV SS
X1A/ P36*
X0A/ P35*
P33
P32/SIN0
P31/SCK0
P30/SOT0
P44/ RX
P43/ TX
P42/ SOT1
P41/ SCK1
P40/ SIN1
Figure 1.4-1 Pin Assignment (FPT-48P-M26)
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
P21/ TOT0
P22/ TIN1
P23/ TOT1
P24/ INT4
P25/ INT5
P26/ INT6
P27/ INT7
MD2
MD1
MD0
RST
V CC
13
14
15
16
17
18
19
20
21
22
23
24
AV CC
AVR
P50/ AN0
P51/ AN1
P52/ AN2
P53/ AN3
P54/ AN4
P55/ AN5
P56/ AN6
P57/ AN7
P37/ ADTG
P20/ TINO
*: MB90F897:X1A, X0A
MB90F897S:P36, P35
8
36
35
34
33
32
31
30
29
28
27
26
25
P17/ PPG3
P16/ PPG2
P15/ PPG1
P14/ PPG0
P13/ IN3
P12/ IN2
P11/ IN1
P10/ IN0
X1
X0
C
V SS
CHAPTER 1 OVERVIEW
1.5
Package Dimensions
MB90895 series is available in one type of package.
The package dimensions below are for reference only. Contact Fujitsu for the correct
package dimensions.
■ Package Dimension of FPT-48P-M26
48-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
7 × 7 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.17 g
Code
(Reference)
P-LFQFP48-7×7-0.50
(FPT-48P-M26)
48-pin plastic LQFP
(FPT-48P-M26)
Note 1) * : These dimensions include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00±0.20(.354±.008)SQ
+0.40
+.016
* 7.00 –0.10 .276 –.004 SQ
36
0.145±0.055
(.006±.002)
25
37
24
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
48
13
"A"
0˚~8˚
LEAD No.
0.50(.020)
1
(Mounting height)
.059 –.004
INDEX
0.10±0.10
(.004±.004)
(Stand off)
12
0.20±0.05
(.008±.002)
0.08(.003)
0.25(.010)
M
0.60±0.15
(.024±.006)
©2003-2008
FUJITSU
LIMITED F48040S-c-2-3
C
2003 FUJITSU
LIMITEDMICROELECTRONICS
F48040S-c-2-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
9
CHAPTER 1 OVERVIEW
1.6
Pin Description
This section describes the I/O pins and their functions of MB90895 series.
■ Pin Description
Table 1.6-1 Pin Description (1/3)
Pin
Number
Pin Name
Circuit
Type
Functional description
M26
1
AVCC
−
VCC power input pin for A/D converter
2
AVR
−
Power (Vref+) input pin for A/D converter. The power supply should not be input VCC
exceeding
P50 to P57
3 to 10
General-purpose I/O port
E
AN0 to AN7
P37
11
General-purpose I/O port
D
ADTG
External trigger input pin for A/D converter. This pin should be set to input port.
P20
12
General-purpose I/O port
D
TIN0
Event input pin for reload timer 0. This pin should be set to input port.
P21
General-purpose I/O port
13
D
TOT0
P22
14
Event output pin for reload timer 0. This pin is enabled only when the output setting is
enabled.
General-purpose I/O port
D
TIN1
Event input pin for reload timer 1. This pin should be set to input port.
P23
15
General-purpose I/O port
D
TOT1
P24 to P27
16 to 19
Event output pin for reload timer 1. This pin is enabled only when the output setting is
enabled.
General-purpose I/O port
D
INT4 to INT7
10
Analog input pin for A/D converter. These pins work when the analog input is set to
enable.
External interrupt input pins. This pin should be set to input port.
20
MD2
F
Input pin for selecting operation mode Connect directly to VSS.
21
MD1
C
Input pin for selecting operation mode Connect directly to VCC.
22
MD0
C
Input pin for selecting operation mode Connect directly to VCC.
23
RST
B
Input pin for external reset
24
VCC
−
Power (5 V) input pin.
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Description (2/3)
Pin
Number
Pin Name
Circuit
Type
Functional description
M26
25
VSS
−
Power (0 V) input pin
26
C
−
Capacity pin for stabilizing power supply. This pin should be connected to a ceramic
capacitor of approx. 0.1μF.
27
X0
A
High-speed oscillation pin
28
X1
A
High-speed oscillation pin
P10 to P13
29 to 32
General-purpose I/O port
D
IN0 to IN3
Trigger input pins for input capture channels 0 to 3. This pin should be set to input port.
P14 to P17
General-purpose I/O port High current output port.
33 to 36
G
PPG0 to PPG3
P40
37
General-purpose I/O port
D
SIN1
Serial data input pin for UART1. This pin should be set to input port.
P41
General-purpose I/O port
38
D
SCK1
Serial clock I/O pin for UART1. This pin functions only when the serial clock I/O setting
of the UART1 is enabled.
P42
General-purpose I/O port
39
D
SOT1
P43
40
Serial data output pin for UART1.
This pin functions only when the serial data output setting of the UART1 is enabled.
General-purpose I/O port
D
TX
CAN transmission output pin. This pin is enabled only when the output setting is enabled.
P44
41
General-purpose I/O port
D
RX
CAN reception input pin. This pin should be set to input port.
P30
General-purpose I/O port
42
D
SOT0
P31
43
P32
44
UART0 serial data output pin This pin is enabled only when UART0 serial output setting
is enabled.
General-purpose I/O port
D
SCK0
UART0 serial clock output pin This pin functions only when the serial clock I/O setting of
the UART1 is enabled.
General-purpose I/O port
D
SIN0
45
Output pins for PPG timers 01 and 23. These pins are enabled when the output setting is
enabled.
UART0 serial data input pin This pin should be set to input port.
P33
D
General-purpose I/O port
X0A*
A
Low-speed oscillation pin.
P35*
D
General-purpose I/O port
46
11
CHAPTER 1 OVERVIEW
Table 1.6-1 Pin Description (3/3)
Pin
Number
Pin Name
Circuit
Type
Functional description
M26
X1A*
A
Low-speed oscillation pin.
P36*
D
General-purpose I/O port
AVSS
−
VSS power input pin for A/D converter
47
48
*: MB90F897:X1A,X0A
MB90F897S:P36,P35
12
CHAPTER 1 OVERVIEW
1.7
I/O Circuit
I/O circuit of MB90895 series is shown in the figure below.
■ I/O Circuit
Table 1.7-1 I/O Circuit (1/2)
Classifi
cation
Circuit
Remarks
A
•
X1
Clock input
•
X1A
X0
X0A
Approximately 1MΩ high speed oscillation feedback
resistor.
Oscillation feedback resistor for low speed approximately
10MΩ
Standby control signal
B
Vcc
•
•
Hysteresis input with pull-up resistor
pull-up resistor: about 50kΩ
•
Hysteresis input
•
•
•
•
CMOS hysteresis input
CMOS-level output
Standby control provided
Automotive Input
R
R
Hysteresis input
C
R
Hysteresis input
D
Vcc
P-ch
Digital output
N-ch
Digital output
R
Vss
CMOS hysteresis input
Standby control
R
automotive input
13
CHAPTER 1 OVERVIEW
Table 1.7-1 I/O Circuit (2/2)
Classifi
cation
Circuit
Remarks
E
Vcc
P-ch
N-ch
R
Digital output
•
•
•
•
•
CMOS hysteresis input
CMOS-level output
Also used as analog input pin
Standby control provided
Automotive Input
•
•
•
Hysteresis input with pull-down resistor
pull-down resistor: about 50 kΩ
There is no pull-down resistor in FLASH product
•
•
•
•
CMOS hysteresis input
CMOS-level output (for high current output)
Standby control provided
Automotive Input
•
•
•
•
•
CMOS hysteresis input
CMOS-level output
Standby control provided
CMOS input
Automotive Input
Digital output
Vss
CMOS hysteresis input
Standby control
R
automotive input
Analog input
F
R
Hysteresis input
R
Vss
G
Vcc
P-ch
N-ch
R
High current output
High current output
Vss
CMOS hysteresis input
Standby control
R
H
automotive input
Vcc
P-ch
N-ch
R
Digital output
Digital output
Vss
CMOS hysteresis input
R
Automotive input
R
CMOS input
Standby control
14
CHAPTER 2
HANDLING DEVICES
This chapter describes the precautions when handling
the general-purpose one chip micro-controller.
2.1 Precautions when Handling Devices
15
CHAPTER 2 HANDLING DEVICES
2.1
Precautions when Handling Devices
This section describes the precautions against the power supply voltage of the device
and processing of pin.
■ Precautions when Handling Devices
● Voltage not exceeding maximum ratings (preventing latch-up)
• For a CMOS IC, latch-up may occur when a voltage higher than VCC or a voltage lower than VSS is
input to the I/O pin other than medium-/high-voltage withstand I/O pins, or when a voltage that exceeds
the rated voltage is impressed between VCC and VSS
• Latch-up may cause a sudden increase in supply current, resulting in thermal damage to the device.
Therefore, the maximum voltage ratings must not be exceeded.
• When turning the analog power supply on and off, the analog supply voltage (AVCC and AVR) and the
analog input voltage should not exceed the digital supply voltage (VCC).
● Handling un-used pins
If unused input pins remain open, a malfunction or latch-up may cause permanent damage, so take
countermeasures such as pull-up or pull-down using a 2 kΩ or larger resistor. Leave unused I/O pins open
in the output state or, if left in the input state, treat them in the same manner as for input pins in use.
● Precautions when using external clock
When an external clock is used, drive only the X0 pin and open the X1 pin. Figure 2.1-1shows an use
example of external clock.
Figure 2.1-1 Example of Using External Clock
X0
Open
X1
MB90895 Series
● Precautions when not using sub clock
If an oscillator is not connected to the X0A and X1A pins, connect the X0A pin to Pull-down resistor and
leave the X1A pin open.
● Precautions during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit
even when there is no external oscillator or external clock input is stopped. Performance of this operation,
however, cannot be guaranteed.
16
CHAPTER 2 HANDLING DEVICES
● Power pins
• When the device is provided with multiple VCC pins and VSS pins, the pins designed to have equal
potential are internally connected to them to prevent malfunctions such as latch-up. However, be sure to
connect all of the potentially equal pins to the power supply and ground outside the device to reduce
unwanted radiation, prevent the strobe signal from malfunctioning due to a rise of ground level, and to
follow the standards of total output current.
• The power pins should be connected to VCC and VSS of MB90895 series device at the lowest possible
impedance from the current supply source.
• It is best to connect an approximately 0.1μF capacitor between VCC and VSS as a bypass capacitor near
the pins of the MB90895 series device.
● Crystal oscillator circuit
• Noise near the X0 and X1 pins may cause MB90895 series to malfunction. When designing a PC board
using the device, place the X0 and X1 pins, the crystal (or ceramic) oscillator, and the bypass capacitor
leading to the ground as close to one another as possible and prevent the wiring patterns for the X0 and
X1 pins from crossing.
• For stable operation, the PC board is recommended to have the artwork with the X0 and X1 pins
enclosed by a ground line.
• Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
● Procedure of A/D converter/analog input power-on
• Always apply power to the A/D converter power and the analog input (AN0 to AN7 pins) after or
concurrently with the digital power (VCC)-on.
• Always turn off the A/D converter power and the analog input before or concurrently with the digital
power-down.
• Note that AVR should not exceed AVCC at turn on or off.
● Handling pins when not using A/D converter
When not using the A/D converter, the pins should be connected so that AVCC = AVR = VCC and AVSS =
VSS.
● Precautions at power on
To prevent a malfunction of the internal step-down circuit, the voltage rise time at power-on should be
50μs or more (between 0.2 V and 2.7 V).
● Stabilization of supply voltage
A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC
supply voltage operating range. Therefore, the VCC supply voltage should be stabilized.
For stabilization reference, the supply voltage should be controlled so that VCC ripple variations (peak-topeak values) at commercial frequencies (50 to 60 Hz) fall below 10% of the standard VCC supply voltage
and the transient regulation does not exceed 0.1 V/ms.
17
CHAPTER 2 HANDLING DEVICES
18
CHAPTER 3
CPU
This chapter explains the CPU functions of the MB90895
series.
3.1 Memory Space
3.2 Dedicated Registers
3.3 General-purpose Register
3.4 Prefix Code
3.5 Interrupt
3.6 Reset
3.7 Clock
3.8 Low-power Consumption Mode
3.9 CPU Mode
19
CHAPTER 3 CPU
3.1
Memory Space
The memory space of the F2MC-16LX is 16 MB and is allocated to I/O, programs, and
data. Part of the memory space is used for specific uses such as the expansion
intelligent I/O service (EI2OS) descriptors, the general-purpose registers, and the vector
tables.
■ Memory Space
I/O, programs and data are all allocated somewhere in the 16-MB memory space of the F2MC-16LX CPU.
And the CPU can indicate their addresses in the 24-bit address bus to access each resource.
Figure 3.1-1 shows an example of the relationships between the F2MC-16LX and the memory map.
Figure 3.1-1 Example of Relationships between F2MC-16LX System and Memory Map
F2MC-16LX device
Generalpurpose ports
Peripheral
circuit
F2MC-16LX
CPU
Internal data bus
Interrupt
EI2OS
Data
000000H
000020H
0000B0H
0000C0H
000100H
I/O port control
register area
Peripheral function
control register area
Interrupt control
register area
EI2OS
descriptor area
000180H
000380H
000900H
003900H
004000H
General-purpose
register
*1
RAM area
Data area
Peripheral function
control register area
Expanded I/O area
ROM area
(Image of FF Bank)
010000H
FE0000H
FF0000H
I/O area
*2
ROM area
(Same data as FF Bank)
Program area
Program
FFFC00H
ROM area
Vector table area
FFFE00H
FFFFFFH
*1: The capacity of the internal RAM depends on the product.
*2: The capacity of the internal ROM depends on the product.
20
hardwired reset
vectors
CHAPTER 3 CPU
■ ROM Area
● Vector table area (address: FFFC00H to FFFFFFH)
• The vector table is provided for reset and interrupts.
• This area is allocated at the top of the ROM area. And The starting address of the corresponding
processing routine is set to the address of each vector table as data.
● Program area (address: to FFFBFFH)
• ROM is contained as the internal program area.
• The capacity of the internal ROM depends on the product.
■ RAM Area
● Data area (address: 000100H to 000900H)
• Static RAM is contained as the internal data area.
• The capacity of the internal RAM depends on the product.
● General-purpose register area (address: 000180H to 00037FH)
• Auxiliary registers for operations or transfer of the 8-bit, 16-bit, or 32-bit data are allocated in this area.
• This area is allocated to part of the RAM area, and can also be used as ordinary RAM.
• When this area is used as general-purpose registers, they can be accessed quickly using a short
instruction through general-purpose register addressing.
● Expanded intelligent I/O service (EI2OS) descriptor area (address: 000100H to 00017FH)
• This area holds the transfer mode, I/O address, transfer count, and buffer address.
• This area is allocated to part of the RAM area, and can also be used as ordinary RAM.
■ I/O Area
● Interrupt control register area (address: 0000B0H to 0000BFH)
The interrupt control registers (ICR00 to ICR15) correspond to all resources with an interrupt function, and
control the setting of interrupt level and EI2OS.
● Resource control register area (address: 000020H to 0000AFH)
This area controls the resource function and data I/O.
● I/O port control register area (address: 000000H to 00001FH)
This area controls the I/O ports and data I/O.
■ Extended I/O Area
● Peripheral function control register area (address: 003900H to 003FFFH)
This area controls the resource function and data I/O.
21
CHAPTER 3 CPU
3.1.1
Mapping of and Access to Memory Space
In MB90895 series, the single-chip mode can be set as a memory access modes.
■ Memory Map for MB90895 Series
In MB90895 series, the internal address bus is output up to a width of 24 bits and the external address bus
is output up to a width of 24 bits; the external access memory can access up to the 16-MB memory space.
Figure 3.1-2 shows the memory map when the ROM mirroring function is enabled and disabled.
Figure 3.1-2 Memory Map for MB90895 Series
When ROM mirroring
function is enabled
000000H
0000C0H
000100H
Address #1
When ROM mirroring
function is disabled
Peripheral
Peripheral
RAM area
RAM area
Register
Register
Expanded I/O area
Expanded I/O area
003900H
004000H
ROM area
(Image of FF Bank)
010000H
FE0000H
*
*
ROM area
FF0000H
FFE000H
FFFFFFH
ROM area
Products
ROM area
Hardwired
reset vectors
ROM area
Address #1
MB90V495G
MB90F897/S
: internal access memory
: Access prohibited
*: In MB90F897/S, When the area of FE0000H to FEFFFFH is read, data of
FF0000H to FFFFFFH can be read.
22
CHAPTER 3 CPU
■ Image Access to Internal ROM
In the F2MC-16LX family, with the internal ROM in operation, ROM data in the FF bank can be seen as an
image in the top 00 bank. This function is called ROM mirroring and enables effective use of a small C
compiler.
In the F2MC-16LX family, the lower 16-bit addresses of the FF bank are the same as the lower 16-bit
addresses of the 00 bank, so the table in ROM can be referenced without specifying far with a pointer.
For example, if "00C000 H" is accessed, data in ROM at "FFC000 H" is actually accessed. However, the
ROM area in the FF bank exceeds 48 KB and all areas cannot be seen as images in the 00 bank. Therefore,
ROM data from "FF4000H" to "FFFFFFH" is see as an image from "004000H" to "00FFFFH" so the ROM
data table should be stored in the area from "FF4000H" to "FFFFFH".
Note:
To disable the ROM mirroring function (ROMM: MI = 0), see 18.1 "Overview of ROM
Mirroring Function Select Module".
23
CHAPTER 3 CPU
3.1.2
Memory Map
MB90895 series memory map is shown for each device.
■ Memory Map
Figure 3.1-3 shows the memory map for MB90895 series.
Figure 3.1-3 Memory Map of MB90895 Series
MB90F897/S
000100H
000900H
003900H
004000H
MB90V495G
Single chip
Single chip
Internal ROM
external bus
External ROM
external bus
I/O
I/O
I/O
I/O
RAM
general-purpose
port
RAM
general-purpose
port
RAM
general-purpose
port
Extended I/O area
Extended I/O area
Extended I/O area
000100H
RAM
general-purpose
port
001900H
002000H
003800H
003900H
004000H
Extended I/O area
ROM area*2
(Image in the
FF Bank)
2
ROM area*2
ROM area*
(Image in the
FF Bank)
(Image in the
FF Bank)
ROM*1
ROM*1
010000H
010000H
FE0000H
ROM*3
FF0000H
FC0000H
ROM
FFE000H
FFFFFFH
Hardwired reset vectors
FFFFFFH
: Internal access memory
: External access memory
: Access prohibited
*1: MB90V495G does not have bulit-in ROM. However, only the operating of dedicated
development tools can operate same as the bult-in ROM product.
*2: FF4000H to FFFFFH address can be seen as an image in the 00 bank in MB90F897/S and
MB90V495G.
*3: In MB90F897/S, when FE Bank is read, FF Bank can be read.
24
CHAPTER 3 CPU
3.1.3
Addressing
Linear and bank types are available for addressing.
The F2MC-16LX family basically uses bank addressing.
• Linear type: direct-addressing all 24 bits by instruction
• Bank type: addressing higher 8 bits by bank registers suitable for the use, and lower
16 bits by instruction
■ Linear Addressing and Bank Addressing
The linear addressing is to access the 16-MB memory space by direct-addressing. The bank addressing is to
access the 16-MB memory space which divided into 256 64-KB banks, by specifying banks and addresses
in banks.
Figure 3.1-4 shows overview of memory management in linear and bank type.
Figure 3.1-4 Memory Management in Linear and Bank Types
Linear types
000000H
bank types
000000H
00FFFFH
010000H
01FFFFH
020000H
02FFFFH
123456H
123456H
FFFFFFH
FD0000H
FDFFFFH
FE0000H
FEFFFFH
FF0000H
FFFFFFH
All is divided by an instruction
00 Bank
64KByte
01 Bank
02 Bank
12 Bank
FD Bank
FE Bank
FF Bank
Divided by an instruction
divided by using the bank register
25
CHAPTER 3 CPU
3.1.4
Linear Addressing
The linear addressing has the following two types:
• Direct-addressing 24 bits by instruction
• Using lower 24 bits of 32-bit general-purpose register for address
■ Linear Addressing by Specifying 24-bit Operand
Figure 3.1-5 Example of 24-bit Physical Direct Addressing in Linear Type
JMPP 123456H
Old program bank
+Program counter
10
452D
10452DH
New program bank
+Program counter
12
3456
123456H
JMPP 123456H
Next instruction
■ Addressing by Indirect-specifying 32-bit Register
Figure 3.1-6 Example of indirect-specifying 32-bit General-purpose Register in Linear Type
MOV A,@RL1+7
Old accumulator
XXXX
(Upper 8-bit is ignored)
RL1
FFFF06F9H
+7
New accumulator
003A
RL1: 32-bit general-purpose register (long word)
26
FF0700H
3AH
CHAPTER 3 CPU
3.1.5
Bank Addressing
The bank addressing is a type of addressing each of 254 64-KB banks into which the 16MB memory space is divided, using the bank register, and the lower 16 bits by an
instruction.
The following five types of bank registers are available for different purposes.
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional bank register (ADB)
■ Bank Registers and Access Space
Table 3.1-1shows the access space for each bank register and the major use of it.
Table 3.1-1 Access Space for Each Bank Register and Major Use of Access Space
Bank Register Name
Access Space
Major Use
Reset
Value
Program bank register (PCB)
Program (PC) space
Stores instruction code, vector tables, immediate data.
FFH
Data bank register (DTB)
Data (DT) space
Stores data that can be read/written and can access
resource control registers and data registers.
00H
User stack bank register (USB)
System stack bank register (SSB)*
Stack (SP) space
Additional bank register (ADB)
Additional (AD) space
These are used for the stack accessing such as the
PUSH/POP instruction and the register saving at an
interrupt. When the stack flag (CCR: S) is "1", SSB is
used. When the stack flag is "0", USB is used.*
00H
Stores data that cannot be stored in data (DT) space.
00H
00H
*: SSB is always used for the stack at an interrupt.
27
CHAPTER 3 CPU
Figure 3.1-7 shows the relationships between the memory space divided into banks and each register.
Figure 3.1-7 Example of Bank Addressing
000000H
070000H
System stack space
07FFFFH
07H : SSB (System stack bank register)
0B0000H
Physical address
Data space
0BH : DTB (Data bank register)
0BFFFFH
0D0000H
User stack space
0DH : USB (User stack bank register)
Additional space
0FH : ADB (Additional bank register)
Program space
FFH : PCB (Program bank register)
0DFFFFH
0F0000H
0FFFFFH
FF0000H
FFFFFFH
Note:
For details, see 3.2 "Dedicated Registers".
■ Bank Addressing and Default Space
To improve the instruction code efficiency, the default space shown in Table 3.1-2 is determined for each
instruction in each addressing type. To use any bank space other than the default space, specify the prefix
code for that bank space before the instruction, which makes the arbitrary bank space corresponding to the
prefix code accessible.
Table 3.1-2 Addressing and Default Spaces
Default Spaces
Note:
28
Addressing
Program space
PC indirect addressing, program-access addressing, branch instruction
addressing
Data space
Addressing with @RW0, @RW1, @RW4, @RW5, @A, addr16, and dir
Stack space
Addressing with PUSHW, POPW, @RW3, and @RW7PUSHW, POPW,
@RW3, @RW7
Additional space
Addressing with @RW2 and @[email protected], @RW6
For details on the prefix codes, see 3.4 "Prefix Codes".
CHAPTER 3 CPU
3.1.6
Allocation of Multi-byte Data in Memory
Multi-byte data is written to memory in sequence starting from the low addresses. For
32- bit length data, the lower 16 bits are written first, and then the higher 16 bits are
written.
If a reset signal is output immediately after the lower 16 bits is written, the higher data
may not be written.
■ Store of Multi-byte Data in RAM
Figure 3.1-8 shows the order in which multi-byte data is stored. Lower 8 bits are allocated to n address, and
in order of n+1, n+2 n+3 and.
Figure 3.1-8 Store of Multi-byte Data in RAM
Lower address
n address
00010100B
n+1
11111111B
n+2
n+3
11001100B
01010101B
MSB
Upper address
LSB
01010101B 11001100B 11111111B 00010100B
MSB: Most significant bit
LSB : Least significant bit
■ Storage of Multi-byte Length Operand
Figure 3.1-9 shows the configuration of a multi-byte length operand in memory.
Figure 3.1-9 Storage of Multi-byte Operand
JMPP 123456H
Lower address
n address
n+1
n+2
n+3
JMPP 1 2 3 4 5 6H
63H
56H
34H
12H
Upper address
29
CHAPTER 3 CPU
■ Storage of Multi-byte Data in Stack
Figure 3.1-10 shows the order in which multi-byte data is stored in the stack.
Figure 3.1-10 Storage of Multi-byte Data in Stack
PUSHW RW1,RW3
Lower address
PUSHW
RW1,
RW3
(35A4H) (6DF0H)
SP
A4H
35H
F0H
6DH
After execution
Upper address
RW1: 35A4H
RW3: 6DF0H
■ Access to Multi-byte Data
All accesses are basically made inside the bank. Consequently, for an instruction that accesses multi-byte
data, the address after the "FFFFH" address is the "0000H" address of the same bank.
Figure 3.1-11 shows an example of access instruction for multi-byte data on the bank boundary.
Figure 3.1-11 Access to Multi-byte Data on Bank Boundary
Lower address
AL before execution
800000H
??
??
23H
MOVW A, 080FFFFH
80FFFFH
Upper address
30
01H
AL after execution
23H
01H
CHAPTER 3 CPU
3.2
Dedicated Registers
The CPU has the following dedicated registers.
• Accumulator
• User stack pointer
• System stack pointer
• Processor status
• Program counter
• Direct page register
• Bank registers (program bank register, data bank register, user stack bank register,
system stack bank register, additional data bank register)
■ Configuration of Dedicated Registers
Figure 3.2-1 Configuration of Dedicated Registers
AH
AL
: Accumulator (A)
They are two 16-bit registers for calculation.
Consecutively used the registers can be used as 32-bit register.
USP
: User stack pointer (USP)
It is a 16-bit pointer for user stack address.
SSP
: System stack pointer (SSP)
It is a 16-bit pointer for system stack address.
PS
: Processor status (PS)
It is a 16-bit register for system status.
PC
: Program counter (PC)
It is a 16-bit register for stored position of current instruction.
DPR
: Direct page register (DPR)
It sets bit 8 to bit 15 in address 24-bit, when executing the instruction
by abbreviated direct addressing. It is a 8-bit register.
PCB
: Program bank register (PCB)
It is a 8-bit register for program space.
DTB
: Data bank register (DTB)
It is a 8-bit register for data space.
USB
: User stack bank register (USB)
It is a 8-bit register for user stack bank space.
SSB
: System stack bank register (SSB)
It is a 8-bit register for system stack bank space.
ADB
8 bits
: Additional data bank register (ADB)
It is a 8-bit register for additional space.
16 bits
32 bits
31
CHAPTER 3 CPU
Table 3.2-1 Reset Values of Dedicated Registers
Dedicated Registers
Reset Value
Accumulator (A)
Undefined
User stack pointer (USP)
Undefined
System stack pointer (SSP)
Undefined
Processor status (PS)
bit15 bit13 bit12
PS
Program counter (PC)
Direct page register (DPR)
Program bank register (PCB)
bit8 bit7
RP
ILM
0 0 0 0 0 0 0 0
Value of reset vector (data at FFFFDCH and FFFFDH)
01H
Value of reset vector (data at FFFFDEH)
Data bank register (DTB)
00H
User stack bank register (USB)
00H
System stack bank register (SSB)
00H
Additional data bank register (ADB)
00H
Note:
32
-
bit0
CCR
0 1 x x x x x
The above reset values are the reset values for the device. The reset values for the
ICE (such as emulator) are different from those of the device.
CHAPTER 3 CPU
3.2.1
Dedicated Registers and General-purpose Register
The F2MC-16LX family has two types of registers: dedicated registers in the CPU and
general-purpose register in the internal RAM.
■ Dedicated Registers and General-purpose Register
The dedicated registers are limited to the use in the hardware architecture of the CPU.
The general-purpose registers are in the internal RAM in the CPU address space. As with the dedicated
registers, these registers can be used for addressing and the use of these registers is not limited.
Figure 3.2-2 shows the allocation of the dedicated registers and the general-purpose registers.
Figure 3.2-2 Dedicated Registers and General-purpose Register
CPU
Dedicated register
Internal RAM
Accumulator
General-purpose
register
User stack pointer
Processor status
Program counter
Direct page register
Internal bus
System stack pointer
Program bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register
33
CHAPTER 3 CPU
3.2.2
Accumulator (A)
The accumulator (A) consists of two 16-bit length operation registers (AH and AL) used
for temporary storage of the operation result or data.
The accumulator can be used as a 32-, 16-, or 8-bit register to perform various
operations between the AH and AL registers and memory or other registers.
■ Accumulator (A)
● Data transfer to accumulator
The accumulator can process 32-bit data (long word), 16-bit data (word), and 8-bit data (byte).
• When processing 32-bit data, the AH register and the AL register are concatenated and used.
• When processing 16- or 8-bit data, only the AL register is used.
Data retention function
When data of word length or less is transferred to the AL register, data stored in the AL register is
transferred automatically to the AH register.
Code-extended function and zero-extended function
When transferring data of byte length or less to the AL register, the data is code-extended (MOVX
instruction) or zero-extended (MOV instruction) to be the 16-bit length and stored in the AL register. Data
in the AL register can also be treated in word and byte lengths.
Figure 3.2-3 shows data transfer to the accumulator and a concrete example.
Figure 3.2-3 Data transfer to accumulator
32-bit
AH
AL
32-bit data transfer
Data transfer Data transfer
AH
16-bit data transfer
AL
Data saving
Data transfer
AH
8-bit data transfer
AL
Data saving
Data transfer
00H or FFH *
(* : 0 extension or sign extension)
34
CHAPTER 3 CPU
● Byte processing arithmetic operation of accumulator
When the arithmetic operation instruction for byte processing is executed for the AL register, the higher 8
bits of the AL register in pre-operation are ignored, and the higher 8 bits of the operation result become all
"0".
● Reset value of accumulator
The reset value is undefined.
Figure 3.2-4 Example of 8-bit Data Transfer to Accumulator (A) (Data Saving)
(Instruction of storing 3000H address data in registers)
MOVW A,3000H
MSB
Before
execution
AH
AL
XXXXH
2456H
2456H
77H
88H
LSB
B53000H
B5H
DTB
After
execution
B53001H
Memory space
X: Undefined
MSB: Most significant bit
LSB: Least significant bit
DTB: Data bank register
7788H
Figure 3.2-5 Example of 8-bit Data Transfer to Accumulator (A) (Data Saving, Zero-extended)
(Instruction that extends 3000H address data and stores in registers)
MOV A,3000H
MSB
Before
execution
AH
AL
XXXXH
2456H
DTB
After
execution
2456H
0088H
B53001H
Memory space
77H
88H
LSB
B53000H
B5H
X : Undefined
MSB: Most significant bit
LSB: Least significant bit
DTB: Data bank register
35
CHAPTER 3 CPU
Figure 3.2-6 Example of 16-bit Data Transfer to Accumulator (A) (Data Saving)
MOVW A,@RW1+6
AH
Before
execution
XXXXH
(Instruction of following execution;
- Reading by the result(RW1 contents + 8-bit length offset) as address
- Storing the data contents in register A)
1234H
DTB
After
execution
1234H
MSB
AL
A6H
Memory space
RW1
15H
38H
A6153FH
A61541H
2BH
8FH
52H
74H
LSB
+6
2B52H
A6153EH
A61540H
X: Undefined
MSB: Most significant bit
LSB: Least significant bit
DTB: Data bank register
Figure 3.2-7 Example of 32-bit Data Transfer to Accumulator (A) (Register Indirect)
MOVL A,@RW1+6
Before
execution
AH
XXXXH
(Instruction of following execution;
- Reading long word by the result(RW1 contents + 8-bit length offset) as address
- Storing the data contents in register A)
AL
XXXXH
DTB
After
execution
8F74H
MSB
2B52H
A6H
Memory space
RW1
15H
38H
A6153FH
A61541H
2BH
8FH
52H
74H
+6
X: Undefined
MSB: Most significant bit
LSB: Least significant bit
DTB: Data bank register
36
LSB
A6153EH
A61540H
CHAPTER 3 CPU
3.2.3
Stack Pointer (USP, SSP)
The stack pointers include a user stack pointer (USP) and a system stack pointer (SSP).
Both these pointers indicate the address where saved data and return data are stored
when the PUSH instruction, the POP instruction, and the subroutine are executed.
• The higher 8 bits of the stack address are set by the user stack bank register (USB) or
the system stack bank register (SSB).
• When the stack flag (PS: CCR: S) is "0", the USP and USB register are enabled. When
the stack flag is "1", the SSP and SSB register are enabled.
■ Stack Selection
For the F2MC-16LX family, two types of stack pointer can be used: system stack, and user stack.
The addresses of the stack pointers are set by the stack flag of the condition code register (CCR: S) as
shown in Table 3.2-2.
Table 3.2-2 Stack Address Specification
Stack Address
S Flag
Higher 8 Bits
Lower 16 Bits
0
User stack bank register (USB)
User stack pointer (USP)
1*
System stack bank register (SSB)
System stack pointer (SSP)
*:Reset value
Since the stack flag (CCR: S) is set to "1" by a reset, the system stack pointer is used after reset.
Ordinarily, the system stack pointer is used in processing the stack at the interrupt routine, and the user
stack pointer is used in processing the stack at other than an interrupt routine. When it is not necessary to
divide the stack space, use only the system stack pointer.
Note:
When an interrupt is accepted, the stack flag (CCR: S) is set and the system stack
pointer is always used.
37
CHAPTER 3 CPU
Figure 3.2-8 shows an example of the stack operation using the system stack.
Figure 3.2-8 Stack Operation Instructions and Stack Pointers
PUSHW A when S flag is "0"
Before
execution
After
execution
MSB
AL A624H
USB C6H
USP F328H
0
SSB 56H
SSP 1234H
AL A624H
USB C6H
USP F326H
S flag
SSB 56H
SSP 1234H
S flag
0
C6F327H
LSB
XXH
XXH
C6F326H
Because S flug = "0",
use the user stack pointer.
C6F327H
A6H
24H
C6F326H
PUSHW A when S flag is "1"
MSB
Before
execution
After
execution
AL A624H
USB C6H
USP F328H
S flag
1
SSB 56H
SSP 1234H
AL A624H
USB C6H
USP F328H
S flag
SSB 56H
SSP 1232H
1
LSB
561233H
XXH
XXH
561232H
561233H
A6H
24H
561232H
Because S flug = "1",
use the system stack pointer.
X: Undefined
MSB: Most significant bit
LSB: Least significant bit
Notes:
• Use even addresses for setting value to the stack pointer. Setting an odd address
divides the word access into two accesses, decreasing the efficiency.
• The reset values of the USP and SSP registers are undefined.
■ System stack pointer (SSP)
When using the system stack pointer (SSP), the stack flag (CCR: S) is set to "1". The higher 8 bits of the
address used in processing the stack are set by the system stack bank register (SSB).
■ User stack pointer (USP)
When using the user stack pointer (USP), the stack flag (CCR: S) is set to"0". The higher 8 bits of the
address used in processing the stack are set by the user stack bank register (USB).
38
CHAPTER 3 CPU
■ Stack Area
● Securing stack area
The stack area is used to save and return the program counter (PC) at execution of the interrupt processing,
subroutine call instruction (CALL) and vector call instruction (CALLV). It is also used to save and return
temporary registers using the PUSHW and POP
The stack area is secured with the data area in RAM.
The stack area is as shown below:
Figure 3.2-9 Stack Area
000000H
I/O area
0000C0H
000100H
000180H
General purpose
register
bank area
Stack area
000380H
Internal RAM area
000900H
FF0000H
*
ROM area
Vector table
(reset, interrupt
vector call instruction)
FFFC00H
FFFFFFH
*: The capacity of the internal ROM depends on the product.
Notes:
• As a general rule, even addresses should be set in the stack pointers (SSP and
USP).
• The system stack area, user stack area, and data area should not overlap.
● System stack area and user stack area
The system stack area is used for interrupt processing. When an interrupt occurs, even though the user stack
area is being used, it is forced to be switched to the system stack area. Therefore, in systems mainly using
the user stack area also, the system stack area must be set correctly.
In particular, only the system stack area should be used unless it is necessary to divide the stack space.
39
CHAPTER 3 CPU
3.2.4
Processor status (PS)
The processor status (PS) consists of the bits controlling CPU and various bits
indicating the CPU status. The processor status (PS) consists of the following three
registers.
• Interrupt level mask register (ILM)
• Register bank pointer (RP)
• Condition code register (CCR)
■ Configuration of Processor Status (PS)
The processor status (PS) consists of bits controlling CPU and various bits indicating the CPU status.
Figure 3.2-10 shows the configuration of the processor status (PS).
Figure 3.2-10 Processor status (PS)
RP
ILM
bit15 14 13 12 11 10
PS
CCR
9
8
ILM2ILM1ILM0 B4 B3 B2 B1 B0
Reset value 0
0
0
0
0
0
0
0
7
6
5
4
3
-
I
-
0
2
1 bit0
S
T
1
X
N
Z
V
C
X
X
X
X
- : Unused
X : Undefined
● Interrupt level mask register (ILM)
This register indicates the level of the interrupt that the CPU is currently accepting. The value of this
register is compared to the value of the interrupt level setting bits of the interrupt control register (ICR: IL0
to IL2) corresponding to the interrupt request of each resource.
● Register bank pointer (RP)
This register set the memory block (register bank) to be used for the general-purpose registers allocated in
the internal RAM.
General-purpose registers can be set for up to 32 banks. The general-purpose register banks to be used are
set by setting 0 to 31 in the register bank pointer (RP).
● Condition code register (CCR)
This register consists of various flags that are set ("1") or cleared ("0") by instruction execution result or
acceptance of an interrupt.
40
CHAPTER 3 CPU
3.2.4.1
Condition Code Register (PS: CCR)
The condition code register (CCR) is an 8-bit register consisting of bits indicating the
result of instruction execution, and the bits enabling or disabling the interrupt request.
■ Configuration of Condition Code Register (CCR)
Figure 3.2-11 shows the configuration of the CCR register.
Figure 3.2-11 Configuration of Condition Code Register (CCR)
RP
ILM
bit15 14 13 12 11 10
PS
ILM2 ILM1 ILM0
0
0
- : Unused
X : Undefined
0
CCR
9
8
B4 B3 B2 B1 B0
0
0
0
0
0
7
6
5
4
3
2
1 bit0 CCR reset value
-
I
S
T
N
Z
V
C
-
0
1
X
X
X
X
X
-01XXXXXB
Interrupt enable flag
Stack flag
Sticky bit flag
Negative flag
0 flag
Overflow flag
Carry flag
● Interrupt enable flag (I)
All interrupts except software interrupts are enabled when the interrupt enable flag (CCR: I) is set to "1",
and are disabled when the interrupt enable flag is set to "0". This flag is cleared to "0" by a reset.
● Stack flag (S)
This flag sets the pointer for stack processing.
When the stack flag (CCR: S) is "0", the user stack pointer (USP) is enabled. When the stack flag (CCR: S)
is "1", the system stack pointer (SSP) is enabled. If an interrupt is accepted or a reset occurs, the flag is set
to "1".
● Sticky-bit flag (T)
This flag is set to "1" if any of the items of data shifted out by a carry is "1" when the logic right-shift
instruction or arithmetic right-shift instruction is executed. If all the shifted-out data is "0" or the shift
amount is "0", this flag is set to "0".
● Negative flag (N)
If the most significant bit (MSB) of the operation result is "1", this flag is set to "1". If the MSB is "0", the
flag is cleared to "0".
● Zero flag (Z)
If all the bits of the operation result are "0", this flag is set to "1". If any 1 bit is "1", the flag is cleared to
41
CHAPTER 3 CPU
"0".
● Overflow flag (V)
If an overflow occurs as a signed numeric value at the execution of operation, this flag is set to "1". If no
overflow occurs, the flag is cleared to "0".
● Carry flag (C)
If a carry from the MSB or to the least significant bit (LSB) occurs at the execution of operation, this flag is
set to "1". If no carry occurs, this flag is cleared to "0".
Note:
42
For the state of the condition code register (CCR) during instruction execution, refer
to the Programming Manual.
CHAPTER 3 CPU
3.2.4.2
Register Bank Pointer (PS: RP)
The register bank pointer (RP) is a 5-bit register that indicates the starting address of
the currently used general-purpose register bank.
■ Register bank pointer (RP)
Figure 3.2-12 shows the configuration of the register bank pointer (RP).
Figure 3.2-12 Configuration of Register Bank Pointer (RP)
RP
ILM
bit15 14 13 12 11 10
PS
ILM2 ILM1 ILM0
CCR
9
8
B4 B3 B2 B1 B0
7
6
5
4
3
2
1 bit0
-
I
S
T
N
Z
V
C
RP reset value
00000B
■ General-purpose Register Area and Register Bank Pointer
The register bank pointer (RP) indicates the allocation of general-purpose registers used in the internal
RAM. The relationship between the values of PR and the actual addresses should conform to the
conversion rule shown in Figure 3.2-13.
Figure 3.2-13 Physical Address Conversion Rules in General-purpose Register Area
Conversion expression [000180H + (RP ) x 10H]
When RP=10H
000180H
000280H
000370H
Register bank 0
Register bank 16
Register bank 31
• The register bank pointer (RP) can take the values from "00H to 1FH" so that the starting address of the
register bank can be set within the range of "000180H to 00037FH".
• The assembler instruction can use the 8-bit immediate value transfer instruction that is transferred to the
register bank pointer (RP), but only the lower 5 bits of that data is actually used.
• The reset value of the register bank pointer (RP) is set to "00H" after a reset.
43
CHAPTER 3 CPU
3.2.4.3
Interrupt Level Mask Register (PS: ILM)
The interrupt level mask register (ILM) is a 3-bit register indicating the interrupt level
accepted by the CPU.
■ Interrupt level mask register (ILM)
Figure 3.2-14 shows the configuration of the interrupt level mask register (ILM).
Figure 3.2-14 Configuration of Interrupt Level Mask Register (ILM)
RP
ILM
bit15 14 13 12 11 10
PS
ILM2 ILM1 ILM0
CCR
9
8
B4 B3 B2 B1 B0
7
6
5
4
3
2
1 bit0
-
I
S
T
N
Z
V
ILM reset value
C
000B
The interrupt level mask register (ILM) indicates the level of an interrupt that the CPU is accepting for
comparison with the values of the interrupt level setting bits (ICR: IL2 to IL0) set according to interrupt
requests from each resource. The CPU performs interrupt processing only when an interrupt with a lower
value (interrupt level) than that indicated by the interrupt level mask register (ILM) is requested with an
interrupt enabled (CCR: I = 1).
• When an interrupt is accepted, its interrupt level value is set in the interrupt level mask register (ILM).
Thereafter, an interrupt with a level value lower than the set level value is not accepted.
• At a reset, the interrupt level mask register (ILM) is always set to "0" to enter the interrupt-disabled
(highest interrupt level) state.
• The assembler instruction can use the 8-bit immediate value transfer instruction that is transferred to the
interrupt level mask register (ILM), but only the lower 3 bits of that data is actually used.
Table 3.2-3 Interrupt Level Mask Register (ILM) and Interrupt Level (High/Low)
Note:
44
ILM2
ILM1
ILM0
Interrupt
Level
Interrupt Level (High/Low)
0
0
0
0
high (interrupt prohibited)
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
↓
1
1
1
7
low
For details of interrupt, see "3.5 Interrupt".
↑
CHAPTER 3 CPU
3.2.5
Program counter (PC)
The program counter (PC) is a 16-bit counter indicating the lower 16 bits of the address
for the next instruction code to be executed by the CPU.
■ Program counter (PC)
The program bank register (PCB) indicates the higher 8 bits of addresses where the next instruction code to
be executed by the CPU is stored; the program counter (PC) indicates the lower 16 bits. As shown in Figure
3.2-15, the actual addresses are combined into 24 bits.
The program counter (PC) is updated by the execution of the conditional branch instruction, the subroutine
call instruction, by an interrupt or reset, etc.
The program counter (PC) can also be used as the base pointer when reading the operand.
Figure 3.2-15 Program counter (PC)
Upper 8-bit
PCB FEH
Lower 16-bit
PC ABCDH
FEABCDH Instruction executed next
Note:
Neither the program counter (PC) nor the program bank register (PCB) can be
rewritten directly by a program (such as MOV PC and #FF).
45
CHAPTER 3 CPU
3.2.6
Direct page register (DPR)
The direct page register (DPR) sets bit 8 to bit 15 (addr 15 to addr 8) for the 8 bits of the
low address directly specified using the operand when executing the instruction by the
abbreviated direct addressing.
■ Direct page register (DPR)
The direct page register (DPR) sets bit 8 to bit 15 (addr 15 to addr 8) for the 8 bits of the low address
directly specified using the operand when executing the instruction by the abbreviated direct addressing.
The direct page register (DPR) is 8 bits long and is set to "01H" at a reset. It is a read and write register.
Figure 3.2-16 Generation of Physical Address in Direct Page Register (DPR)
DTB register
DPR register
Direct addres during instruction
AAAAAAAA
BBBBBBBB
CCCCCCCC
MSB
LSB
24bit
Physical address
AAAAAAAA
BBBBBBBB
CCCCCCCC
bit24
bit16 bit15
bit8 bit7
bit0
MSB: Most significant bit
LSB : Least significant bit
Figure 3.2-17 shows the setting of direct page register (DPR) and an example of data access.
Figure 3.2-17 Setting of Direct Page Register (DPR) and Data Access Example
MOV S:56H, #5AH
Result of executing instruction
Upper 8bit Lower 8bit
DTB register
12H
DPR resister
34H
MSB: Most significant bit
LSB : Least significant bit
46
123454H
123455H
123457H
5AH
123459H
123456H
123458H
MSB
LSB
CHAPTER 3 CPU
3.2.7
Bank Register (PCB, DTB, USB, SSB, and ADB)
The bank register sets the MSB 8 bit of the 24-bit address using bank addressing The
following five registers are included.
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional bank register (ADB)
Each of the above registers indicate the memory bank to which the program, data, user
stack, system stack, or additional is allocated.
■ Program bank register (PCB)
The program bank register (PCB) sets the program (PC) space.
This register is rewritten at execution of the JMPP, CALLP, RETP, or RETI instructions that branches to
the entire 16-MB space, at executing a software interrupt instruction, or at a hardware interrupt or
exception interrupt.
■ Data bank register (DTB)
The data bank register (DTB) sets the data (DT) space.
■ User Stack Bank Register (USB) and System Stack Bank Register (SSB)
The user stack bank register (USB) and system stack bank register (SSB) set the stack (SP) space. The bank
register that is used is determined by the value of the stack flag (CCR: S).
■ Additional bank register (ADB)
The additional bank register (ADB) sets the additional (AD) space.
■ Setting of Each Bank and Data Access
Each bank register is 8 bits long. At a reset, the program bank register (PCB) is set to "FFH" and other bank
registers are set to "00H".
The program bank register (PCB) is a read-only register. Other bank registers are read and write registers.
Note:
For the operation of each bank register, see 3.1" Memory Space".
47
CHAPTER 3 CPU
3.3
General-purpose Register
The general-purpose register is a memory block allocated to addresses "000180H" to
"00037FH" in the internal RAM in 1 bank units of 16 bits x 8.
• General-purpose 8-bit register (byte registers R0 to R7)
• 16-bit register (word registers RW0 to RW7)
• 32-bit register (long-word registers RL0 to RL7)
■ Configuration of General-purpose Register
General-purpose registers are provided as 32 banks in the internal RAM from "000180H" to "00037FH".
The banks that are used are set by the register bank pointer (RP). The current banks are indicated by
reading the register bank pointer (RP).
The register bank pointer (RP) determines the starting address of each bank as the following expression.
Starting address of general-purpose register = 000180H + RP x 10H
Figure 3.3-1 shows the allocation and configuration of the general-purpose register banks in memory space.
Figure 3.3-1 Allocation and Configuration of General-Purpose Register Banks in Memory Space
Internal RAM
02C0H
RW0
Byte
address
02C1H
02C2H
RW1
02C3H
02C4H
RW2
02C5H
02C6H
02C7H
02C8H
RW3
R1
R0
02CAH
R2
R3
02C9H RW4
02CBH RW5
02CCH
R4
R5
02CDH RW6
02CEH
R6
R7
02CFH RW7
Byte
address
000180H Register bank 0
000190H
Register bank 1
0001A0H
0001B0H Register bank 2
0002B0H Register bank 19
0002C0H
Register bank 20
0002D0H
0002E0H Register bank 21
RP
14H
LSB
000360H
Register bank 30
000370H
Register bank 31
000380H
Note:
48
16bit
RL0
RL1
RL2
RL3
MSB
Conversion expression [000180H + RP x 10H]
R0 to R7: Byte register
RW0 to RW7: Word register
RL0 to RL3: Long word register
MSB: Most significant bit
LSB: Least significant bit
The register bank pointer (RP) is initialized to "00000B" by a reset.
CHAPTER 3 CPU
■ Register Bank
The register bank can be used as a general-purpose register (byte registers R0 to R7, word registers RW0 to
RW7, and long-word registers RL0 to RL3) to perform various operations or to serve as a pointer. The
long- word register can also be used as a linear addressing to directly access the entire memory space.
In the same way as ordinary RAM, the value in the general-purpose register is unchanged by a reset,
meaning that the state before the reset is held. However, at power-on, the value is undefined.
Table 3.3-1 shows the typical functions of the general- purpose register.
Table 3.3-1 Typical Functions of the General-purpose Register
Register Name
Function
R0 to R7
Used as operands for various instructions
Note:
R0 can also be used as the barrel shift counter or the normalized instruction counter.
RW0 to RW7
Used as addressing
Used as operands for various instructions
Note:
RW0 can also be used as the string instruction counter.
RL0 to RL3
Used as linear addressing
Used as operands for various instructions
49
CHAPTER 3 CPU
3.4
Prefix Code
When prefix code is inserted by an instruction, the operation of the instruction can be
changed partially. The prefix code has the following three types:
• Bank select prefix (PCB, DTB, ADB, and SPB)
• Common register bank prefix (CMR)
• Flag change inhibit prefix (NCC)
■ Prefix Code
● Bank select prefix (PCB, DTB, ADB, and SPB)
When the bank select prefix (PCB, DTB, ADB, SPB) codes precede an instruction, any memory space to
be accessed by the instruction can be selected, regardless of the addressing types.
● Common register bank prefix (CMR)
When the common register bank prefix (CMR) code precedes an instruction for accessing a generalpurpose register, the general-purpose register to be accessed by the instruction can be changed to a common
bank (register bank selected when the register bank pointer (RP) is 0) at 000180H to 00018FH, regardless of
the current value of the register bank pointer (RP).
● Flag change inhibit prefix (NCC)
When the flag change inhibit (NCC) code precedes an instruction for changing various flags of the
condition code register (CCR), a flag change with instruction execution can be inhibited.
50
CHAPTER 3 CPU
3.4.1
Bank select prefix (PCB, DTB, ADB, and SPB)
When the bank select prefix codes precede an instruction, any memory space accessed
by the instruction can be set, regardless of the addressing modes.
■ Bank select prefix (PCB, DTB, ADB, and SPB)
Memory space used at data access is predetermined for each addressing mode. However, when the bank
select prefix codes precede an instruction statement, any memory space accessed by the instruction
statement can be set, regardless of addressing method. Table 3.4-1 shows the bank select prefix code and
the memory space to be selected.
Table 3.4-1 Bank Select Prefix
Bank Select Prefix
Selected Space
PCB
Program space
DTB
Data space
ADB
Additional space
SPB
When the stack flag (CCR: S) is "0", user stack space is selected. When the stack flag is "1", system stack space
is selected.
The use of the bank select prefix (PCB, DTB, ADB, SPB) codes causes some instructions to perform
exceptional operations as explained below.
Table 3.4-2 shows the instructions not affected by the bank select prefix code, and Table 3.4-2 shows the
instructions requiring precaution
Table 3.4-2 Instructions Unaffected by Bank Select Prefix
Instruction Types
Instruction
Effect of bank select prefix code
String instruction
MOVS
SCEQ
FILS
MOVSW
SCWEQ
FILSW
The bank register specified for the operand is used irrespective
of the presence or absence of the bank select prefix code.
Stack instruction
PUSHW
POPW
Irrespective of the presence or absence of the bank select prefix
code, the user stack bank (USB) is used when the S flag is "0";
and the system stack bank (SSB) is used when the S flag is "1"
I/O Access
instruction
MOV A,io
MOVW A,io
MOV io,A
MOV io,#imm8
MOVB A,io:bp
SETB io:bp
BBC io:bp,rel
WBTC io,bp
MOVX A,io
The I/O space ("000000H" to "0000FFH") is accessed
irrespective of the presence or absence of the bank select prefix
code.
Interrupt return
instruction
RETI
MOVW io,A
MOVW io,#imm16
MOVB io:bp,A
CLRB io:bp
BBS io:bp,rel
WBTS io:bp
The system stack bank (SSB) is used irrespective of the
presence or absence of the bank select prefix code.
51
CHAPTER 3 CPU
Table 3.4-3 Instructions Requiring Precaution When Using Bank Select Prefix
Instruction Types
Instruction
Description
Flag change instruction
AND CCR,#imm8
OR CCR,#imm8
The bank select prefix code affects up to the next instruction.
ILM setting instruction
MOV ILM,#imm8
The bank select prefix code affects up to the next instruction.
PS Return instruction
POPW PS
Do not add the bank select prefix code to the PS return instruction.
52
CHAPTER 3 CPU
3.4.2
Common register bank prefix (CMR)
When the common register bank prefix (CMR) code precedes an instruction for
accessing a general-purpose register, the general-purpose register to be accessed by
the instruction can be changed to a common bank (register bank selected when the
register bank pointer (RP) is 0) at 000180H to 00018FH, regardless of the current value of
the register bank pointer (RP).
■ Common Register Bank Prefix (CMR)
The F2MC-16LX family provides common banks at "000180H" to "00018FH" as register banks that can be
commonly accessed by each task, regardless of the values of the register bank pointer (RP). Using the
common banks facilitates data exchange between two or more tasks.
Using the common banks facilitates data exchange between two or more tasks.
When the common register bank prefix (CMR) code precedes an instruction for accessing a generalpurpose register, the general-purpose register to be accessed by the instruction can be changed to a common
bank (register bank selected when the register bank pointer (RP) is 0) at 000180H to 00018FH, regardless of
the current value of the register bank pointer (RP).
Table 3.4-4 shows the instructions requiring care when using the common register bank prefix.
Table 3.4-4 Instructions Requiring Precaution When Using Bank Select Prefix (CMR)
Instruction Types
Instruction
MOVSW
SCWEQ
FILSW
Description
String instruction
MOVS
SCEQ
FILS
Do not add the CMR code to string instructions.
Flag change instruction
AND CCR,#imm8
OR CCR,#imm8
The common register bank prefix code affects up to the next instruction.
PS Return instruction
POPW PS
The common register bank prefix code affects up to the next instruction.
ILM setting instruction
MOV ILM,#imm8
The common register bank prefix code affects up to the next instruction.
53
CHAPTER 3 CPU
3.4.3
Flag change inhibit prefix (NCC)
When the flag change inhibit prefix (NCC) code precedes an instruction for changing
various flags of the condition code register (CCR), a flag change caused by instruction
execution can be inhibited.
■ Flag change inhibit prefix (NCC)
The flag change inhibit prefix (NCC) code is used to inhibit an unnecessary flag change.
When the flag change inhibit prefix (NCC) code precedes an instruction for changing various flags of the
condition code register (CCR), a flag change caused by instruction execution can be inhibited.
• Sticky-bit flag (CCR: T)
• Negative flag (CCR: N)
• Zero flag (CCR: Z)
• Overflow flag (CCR: V)
• Carry flag (CCR: C)
Table 3.4-5 shows the instructions requiring precaution when using the flag change inhibit prefix.
Table 3.4-5 Instructions Requiring Precaution When Using Flag Change Inhibit Prefix (NCC)
Instruction Types
Instruction
String instruction
MOVS
SCEQ
FILS
Flag change instruction
AND CCR,#imm8
OR CCR,#imm8
The CCR changes by execution of an instruction, regardless of the
presence or absence of the NCC code.
The flag change inhibit prefix code affects the next instruction.
PS Return instruction
POPW PS
The CCR changes by execution of an instruction, regardless of the
presence or absence of the NCC code.
The flag change inhibit prefix code affects the next instruction.
ILM setting instruction
MOV ILM,#imm8
The flag change inhibit prefix code affects up to the next instruction.
Interrupt instruction
Interrupt return instruction
INT #vct8
INT addr16
RETI
The CCR changes by execution of an instruction, regardless of the
presence or absence of the NCC code.
Context switch instruction
JCTX @A
54
MOVSW
SCWEQ
FILSW
Description
INT9
INTP addr24
Do not the add the NCC code to the string instruction.
The CCR changes by execution of an instruction, regardless of the
presence or absence of the NCC code.
CHAPTER 3 CPU
3.4.4
Restrictions on Prefix Code
The use of the prefix codes is restricted as follows:
• No interrupt request is accepted during execution of a prefix code and interrupt
inhibit instruction.
• When a prefix code precedes an interrupt inhibit instruction, The effect of the prefix
code is delayed.
• When conflicting prefix codes are used in succession, the last prefix code is enabled.
■ Prefix Code and Interrupt Inhibit Instruction
The interrupt inhibit instruction and prefix code are restricted as shown below.
Table 3.4-6 Prefix Code and Interrupt Inhibit Instruction
Prefix Code
PCB
DTB
ADB
SPB
CMR
NCC
Instruction that does not
accept interrupt request
Interrupt/Hold Inhibit Instruction (instruction
that delays effect of prefix code)
MOV
OR
AND
POPW
ILM,#imm8
CCR,#imm8
CCR,#imm8
PS
● Interrupt Inhibition
Even if generated, an interrupt request is not accepted during execution of a prefix code and interrupt
inhibit instruction. The interrupt is processed when any other instruction is executed after execution of a
prefix code or interrupt inhibit instruction.
Figure 3.4-1 Interrupt Inhibition
Interrupt inhibit instruction
(a)
The generation of interrupt request
Interrupt requests (a) Normal instruction
55
CHAPTER 3 CPU
● Delay of the effect of the prefix code
When a prefix code precedes an interrupt inhibit instruction, it affects the next instruction after the interrupt
inhibit instruction.
Figure 3.4-2 Interrupt Inhibit Instruction and Prefix Code
Interrupt inhibit instruction
MOV A,FFH
NCC
MOV ILM,#imm8
ADD A,01H
CCR: XXX10XXB
CCR: XXX10XXB
CCR remains unchanged by NCC.
■ Array of Prefix Codes
For a succession of conflicting prefix codes (PCB, ADB, DTB, SPB) the last one is enabled.
Figure 3.4-3 Array of Prefix Codes
Prefix code
ADB
DTB
PCB
ADD A,01H
Prefix code enables PCB.
56
CHAPTER 3 CPU
3.5
Interrupt
The F2MC-16LX family has four interrupt functions for suspending the current
processing to pass control to a separately defined program when a specific event
occurs.
• Hardware Interrupt
• Software interrupt
• Interrupts by extended intelligent I/O service (EI2OS)
• Exception processing
■ Type and Function of Interrupt
● Hardware Interrupt
This transits control to the interrupt processing program defined by the user in response to the interrupt
request from resources.
● Software interrupt
This transfers control to the interrupt processing program defined by user by executing an instruction (such
as INT instruction) dedicated to the software interrupt.
● Interrupts by extended intelligent I/O service (EI2OS)
The extended intelligent I/O service (EI2OS) provides automatic data transfer between resources and
memory. Data can be transferred just by creating the startup-setting program and end program of the
EI2OS. At completion of data transfer, the interrupt processing program is executed automatically.
An interrupt generated by the EI2OS is a type of the above hardware interrupt.
● Exception processing
If an exception (execution of an undefined instruction) is detected among instructions, ordinary processing
is suspended to perform exception processing. This is equivalent to the above software interrupt instruction
"INT10".
57
CHAPTER 3 CPU
■ Interrupt Operation
Figure 3.5-1 shows interrupt start and return processing.
Figure 3.5-1 General Flow of Interrupt Operation
START
Main program
Valid interrupt ?
YES
Interrupt start/return processing
During execution of
string instruction*
NO
YES
Starting the EI2OS ?
Fetch of next
instruction and decode
EI2OS
NO
YES
INTinstruction ?
NO
EI2OS processing
Software
interrupt/
Exception
processing
dedicated registers are
saved in the system stack
Hardware
interrupt
disabling the interrupt
recieving hardware (I=0)
YES
Dedicated registers are
saved in the system stack
CPU interrupt processing
level (ILM) updating
YES
RETI instruction ?
NO
Normal instruction
execution
NO
Interrupt return
processing
Dedicated register returns
from system stack, and
returns to the execution
befor calling interrupt process.
Reading interrupt vector,
updating PC and PCB,
and branch to the
interrupt processing
Repeat of
string instruction
transmitting ?
YES
PC updating and pointer
transfering to next instruction
*: During executing instruction of string type, they are determinated step by step.
58
completes
the specified number ?
or request of finish from
peripheral
function ?
NO
CHAPTER 3 CPU
3.5.1
Interrupt Factor and Interrupt Vector
The F2MC-16LX family has vector tables corresponding to 256 types of interrupt factor.
■ Interrupt Vector
The interrupt vector tables referenced at interrupt processing are allocated to the most significant addresses
("FFFC00H" to "FFFFFFH") of the memory area. The interrupt vectors share the same area with the EI2OS,
exception processing, and hardware and software interrupts.
• Interrupts (INT0 to INT255) are used as software interrupts.
• At hardware interrupts, the interrupt vectors and interrupt control register (ICR) are fixed for each
resource.
Figure 3.5-1 shows the interrupt number and allocation of interrupt vector.
Table 3.5-1 List of Interrupt Vectors
Software Interrupt
Instruction
Vector
address L
Vector
Address M
Vector
address H
Mode Data
Interrupt
number.
Hardware Interrupt
INT0
FFFFFCH
FFFFFDH
FFFFFEH
Unused
#0
None
:
:
:
:
:
:
:
INT7
FFFFE0H
FFFFE1H
FFFFE2H
Unused
#7
None
INT8
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDFH
#8
(RESET vector)
INT9
FFFFD8H
FFFFD9H
FFFFDAH
Unused
#9
None
INT10
FFFFD4H
FFFFD5H
FFFFD6H
Unused
#10
<Exception processing>
INT11
FFFFD0H
FFFFD1H
FFFFD2H
Unused
#11
Resource interrupt #0
INT12
FFFFCCH
FFFFCDH
FFFFCEH
Unused
#12
Resource interrupt #1
INT13
FFFFC8H
FFFFC9H
FFFFCAH
Unused
#13
Resource interrupt #2
INT14
FFFFC4H
FFFFC5H
FFFFC6H
Unused
#14
Resource interrupt #3
:
:
:
:
:
:
:
INT254
FFFC04H
FFFC05H
FFFC06H
Unused
#254
None
INT255
FFFC00H
FFFC01H
FFFC02H
Unused
#255
None
Reference:
It is recommended to set the unused interrupt vectors to the addresses for exception
processing.
59
CHAPTER 3 CPU
■ Interrupt Factor, Interrupt Vector, and Interrupt Control Register
Table 3.5-2 shows the relationships between the interrupt factor except software interrupt, and interrupt
vector and interrupt control register.
Table 3.5-2 Interrupt Factor, Interrupt Vector, and Interrupt Control Register
Interrupt Factor
EI2OSCorresponded
Interrupt Vector
Number
Interrupt Control Register
Address
ICR
Address
*4
High
Reset
#08
08H
FFFFDCH
−
−
INT9 instruction
#09
09H
FFFFD8H
−
−
Exception processing
#10
0AH
FFFFD4H
−
−
CAN controller receive completion (RX)
#11
0BH
FFFFD0H
#12
0CH
FFFFCCH
ICR00
0000B0H(*1)
#13
0DH
FFFFC8H
Reserved
#14
0EH
FFFFC4H
ICR01
0000B1H
CAN wake-up
#15
0FH
FFFFC0H
Timebase timer
#16
10H
FFFFBCH
ICR02
0000B2H(*3)
16-bit reload timer 0
#17
11H
FFFFB8H
8/10-bit A/D converter
#18
12H
FFFFB4H
ICR03
0000B3H(*1)
16-bit free-run timer overflow
#19
13H
FFFFB0H
Reserved
#20
14H
FFFFACH
ICR04
0000B4H
Reserved
#21
15H
FFFFA8H
PPG timer channel 0/1 underflow
#22
16H
FFFFA4H
ICR05
0000B5H
Input capture 0 fetched
ICR06
0000B6H(*1)
ICR07
0000B7H(*2)
ICR08
0000B8H(*1)
ICR09
0000B9H
ICR10
0000BAH
ICR11
0000BBH
ICR12
0000BCH
ICR13
0000BDH(*1)
ICR14
0000BEH
ICR15
0000BFH(*1)
CAN controller transmitting complete (TX) /
Node Status transition (NS)
Reserved
#23
17H
FFFFA0H
External interrupt (INT4/INT5)
#24
18H
FFFF9CH
Input capture 1 fetched
#25
19H
FFFF98H
PPG timer channel 2/3 underflow
#26
1AH
FFFF94H
External interrupt (INT6/INT7)
#27
1BH
FFFF90H
Watch timer
#28
1CH
FFFF8CH
Reserved
#29
1DH
FFFF88H
#30
1EH
FFFF84H
#31
1FH
FFFF80H
Reserved
#32
20H
FFFF7CH
Reserved
#33
21H
FFFF78H
Reserved
#34
22H
FFFF74H
Reserved
#35
23H
FFFF70H
16-bit reload timer 1
#36
24H
FFFF6CH
UART1 Reception
#37
25H
FFFF68H
UART1 Transmission
#38
26H
FFFF64H
Input capture 2 fetched
Input capture 3 fetched
Reserved
UART0 Reception
#39
27H
FFFF60H
UART0 Transmission
#40
28H
FFFF5CH
Flash memory
#41
29H
FFFF58H
Delayed interrupt generation module
60
#42
2AH
Priority
FFFF54H
↑
↓
low
CHAPTER 3 CPU
:Available
:Not available
:Interrupt factor corresponds to EI2OS and has EI2OS stop function
: Interrupt factor can be used when not using interrupt sources sharing ICR register
*1:
• The interrupt level for resources sharing an ICR register become the same.
• When two resources share an ICR register, only one can use the EI2OS.
• When two resources share an ICR register and one specifies the EI2OS, the remaining resource cannot use the
interrupt.
*2:Only input capture unit 1 supports EI2OS. As the PPG timer does not support EI2OS, the PPG timer should be
disabled for interrupts when input capture unit 1 uses EI2OS.
*3:Only CAN wake-up supports EI2OS. As the timebase timer does not support EI2OS, the timebase timer should be
disabled for interrupts when CAN wake-up uses EI2OS.
*4:The priority is given when plural interrupts with the same level are generated simultaneously.
61
CHAPTER 3 CPU
3.5.2
Interrupt Control Registers and Peripherals
The interrupt control registers (ICR00 to ICR15) are allocated in he interrupt controller,
and correspond to all peripherals with interrupt functions. The registers control the
interrupt and extended intelligent I/O service (EI2OS).
■ Interrupt Control Register List
Table 3.5-3 lists the peripherals corresponding to the interrupt control registers.
Table 3.5-3 Interrupt Control Register List
Address
62
Register
Abbreviation
Corresponding Peripheral
0000B0H
Interrupt control register 00
ICR00
CAN controller
0000B1H
Interrupt control register 01
ICR01
Reserved
0000B2H
Interrupt control register 02
ICR02
CAN wake-up
Timebase timer
0000B3H
Interrupt control register 03
ICR03
16-bit reload timer 0
A/D converter
0000B4H
Interrupt control register 04
ICR04
16-bit free-run timer overflow
0000B5H
Interrupt control register 05
ICR05
PPG0/1
0000B6H
Interrupt control register 06
ICR06
Input capture 0
External interrupt INT4/INT5
0000B7H
Interrupt control register 07
ICR07
Input capture 1
PPG2/3
0000B8H
Interrupt control register 08
ICR08
External interrupt INT6/INT7
Watch timer
0000B9H
Interrupt control register 09
ICR09
Input capture 2/3
0000BAH
Interrupt control register 10
ICR10
Reserved
0000BBH
Interrupt control register 11
ICR11
Reserved
0000BCH
Interrupt control register 12
ICR12
16-bit reload timer 1
0000BDH
Interrupt control register 13
ICR13
UART1
0000BEH
Interrupt control register 14
ICR14
UART0
0000BFH
Interrupt control register 15
ICR15
Flash memory
Delayed interrupt
CHAPTER 3 CPU
Each interrupt control register (ICR) has the following four functions.
Some functions of the interrupt control register (ICR) are different at write and read.
• Setting of interrupt level of corresponding peripheral
• Selection of whether to perform normal interrupt or EI2OS for corresponding peripheral
• Selection of channel of EI2OS
• Display of end state of EI2OS
Note:
Do not access the interrupt control register (ICR) using the read modify write
instruction because it causes a malfunction.
63
CHAPTER 3 CPU
3.5.3
Interrupt Control Register (ICR00 to ICR15)
The functions of the interrupt control registers are shown below.
■ Interrupt Control Register (ICR00 to ICR15)
Some functions differ depending on whether data is written to or read from the interrupt control registers.
Figure 3.5-2 Interrupt Control Register (ICR00 to ICR15) at Write
At writing
7
6
5
4
3
2
1
0
Reset value
00000111B
W
W
W
W R/W R/W R/W R/W
bit2
IL2
0
0
0
0
1
1
1
1
bit1
IL1
0
0
1
1
0
0
1
1
bit0
IL0
0
1
0
1
0
1
0
1
Interupt level setting bit
Interrupt level 0 (highest)
Interrupt level 7 (without interruption)
bit3
ISE
0
1
When an interrupt occurs, start normal interrupt process
When an interrupt occurs, start El2OS
bit7
bit6
El2OS enable bit
bit5
bit4
ICS3 ICS2 ICS1 ICS0
R/W : Read/write
W
: Write only
: Reset value
64
El2OS chanel select bit
Chanel
Descriptor address
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
000100H
000108H
000110H
000118H
000120H
000128H
000130H
000138H
000140H
000148H
000150H
000158H
000160H
000168H
000170H
000178H
CHAPTER 3 CPU
Figure 3.5-3 Interrupt Control Register (ICR00 to ICR15) at Read
At read
7
6
5
4
-
-
R
R
3
2
1
0
Reset value
XX000111B
R/W: Read/Write
W: Write only
- : Unused
X: Undefined
: Reset value
R/W R/W R/W R/W
bit0
IL0
0
1
0
1
0
1
0
1
bit2
IL2
0
0
0
0
1
1
1
1
bit1
IL1
0
0
1
1
0
0
1
1
bit3
ISE
0
1
When an interrupt occurs, start normal interrupt process
When an interrupt occurs, start El2OS
bit5
bit4
S1
0
0
1
1
S0
0
1
0
1
Interupt level setting bit
Interrupt level 0 (highest)
Interrupt level 7 (without interruption)
El2OS enable bit
El2OS status bit
When EI2OS in operation or not started
Stop state by end of counting
Reserved
Stop state by request from resource
65
CHAPTER 3 CPU
3.5.4
Function of Interrupt Control Register
The interrupt control registers (ICR00 to ICR15) consist of the following bits with four
functions.
• Interrupt level setting bits (IL2 to IL0)
• EI2OS enable bit (ISE)
• EI2OS channel select bits (ICS3 to ICS0)
• EI2OS status bits (S1 and S0)
■ Bit Configuration of Interrupt Control Register (ICR)
The bit configuration of the interrupt control registers (ICR) is show below.
Figure 3.5-4 Configuration of Interrupt Control Register (ICR)
Configuration of interrupt control register (ICR) at writing
bit7 6
5
4
3
2
1
bit0
IL2
IL1
IL0
W
W
W
W
3
2
1
bit0
ICS3 ICS2 ICS1 ICS0 ISE
W
W
W
W
Configuration of interrupt control register (ICR) at reading
bit7 6
5
4
-
-
S1
S0
ISE
IL2
IL1
IL0
-
-
R
R
R
R
R
R
Reset value
00000111B
Reset value
XX000111B
R : Read only
W : Write only
- : Unused
References:
66
• The setting of the channel select bits (ICR: ICS3 to ICS0) is enabled only when
starting the EI2OS. When starting the EI2OS, set the EI2OS enable bit (ICR: ISE)
to "1". When not starting the EI2OS, set the bit to "0".
• The channel select bits (ICR: ICS3 to ICS0) are enabled only at write, and the
EI2OS status bits (ICR: S1, S0) are enabled only at read.
CHAPTER 3 CPU
■ Function of Interrupt Control Register
● Interrupt level setting bits (IL2 to IL0)
Sets corresponding peripheral Functions of Interrupt Control Register. At reset, the bits are set to level 7
(IL2 to IL0 =111B: no interrupt).
Table 3.5-4 shows the relationship between the interrupt level setting bits and interrupt levels.
Table 3.5-4 Relationship between Interrupt Level Setting Bits and Interrupt Levels
IL2
IL1
IL0
Interrupt Level
0
0
0
0(maximum interrupt)
0
0
1
↑
0
1
0
0
1
1
1
0
0
1
0
1
↓
1
1
0
6 (lowest interrupt)
1
1
1
7 (No interrupt)
● Extended Intelligent I/O Service (EI2OS) enable bit (ISE)
When an interrupt occurs with the ISE bit set to "1", the EI2OS is started. When an interrupt occurs with the
ISE bit set to "0", ordinary interrupt processing is started. If the EI2OS end condition is satisfied (when the
status bits S1 and S0 are not "00B"), the ISE bit is cleared. When the corresponding resources have no
EI2OS function, this bit must be set to "0" by the program. At reset, the ISE bit is set to "0".
● EI2OS channel select bits (ICS3 to ICS0)
These bits select EI2OS channels. The EI2OS descriptor addresses are set according to the setting values of
the ICS3 to ICS0 bits. At reset, the ICS3 to ICS0 are set to" 0000B".
Table 3.5-5 shows the correspondence between the EI2OS channel select bits and descriptor addresses.
Table 3.5-5 Correspondence between EI2OS Channel Select Bits and Descriptor
Addresses (1/2)
ICS3
ICS2
ICS1
ICS0
Channel to be Selected
Descriptor Address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
67
CHAPTER 3 CPU
Table 3.5-5 Correspondence between EI2OS Channel Select Bits and Descriptor
Addresses (2/2)
ICS3
ICS2
ICS1
ICS0
Channel to be Selected
Descriptor Address
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
● EI2OS status bits (S1 and S0)
When the S1 and S0 bits are read at the termination of the EI2OS, the operating and end states can be
checked. At reset, the bit is set to "00B".
Table 3.5-6 shows the relationship between the EI2OS status bits (ICR: S1, S0) and the EI2OS status.
Table 3.5-6 Relationships Between EI2OS Status Bits and EI2OS Status
68
S1
S0
0
0
When E2 OS in operation or not started
0
1
Stop state due to end of counting
1
0
Reserved
1
1
Stop state due to request from peripheral
EI2OS Status
CHAPTER 3 CPU
3.5.5
Hardware Interrupt
The hardware interrupt responds to the interrupt request from a resource, suspends the
current-executing program and transfers control to the interrupt processing program
defined by user.
The hardware interrupt corresponds to the EI2OS.
■ Hardware Interrupt
● Function of hardware interrupt
When a hardware interrupt occurs, the interrupt level (IR: IL) of the interrupt request from a peripheral
resource is compared with the interrupt level mask register (PS: ILM) and the state of the interrupt enable
flag (CCR: I) is referenced to determine whether can be accepted.
When the hardware interrupt is accepted, registers in the CPU are automatically saved in the system stack.
The interrupt level of the accepted interrupt is stored in the interrupt level mask register (ILM), then
branches to the corresponding interrupt vector.
● Multiple interrupts
Multiple hardware interrupts can be started.
● EI2OS
When the EI2OS function ends, normal interrupt processing is performed. Two or more instances of EI2OS
are not started at once. During EI2OS processing, other interrupt requests and EI2OS requests are all put on
hold.
● External interrupt
The external interrupt (wake-up interrupt included) is accepted as a hardware interrupt via the peripheral
(interrupt request detector).
● Interrupt Vector
The interrupt vector tables referenced during interrupt processing are allocated to "FFFC00H" to
"FFFFFFH" in the memory and shared with software interrupts.
69
CHAPTER 3 CPU
■ Mechanism of Hardware Interrupt
The mechanism related to hardware interrupts consists of the four sections.
When starting the hardware interrupt, these four sections must be set by the program.
Table 3.5-7 Mechanism Related to Hardware Interrupt
Mechanism Related to Hardware
Interrupt
Function
Peripheral
Interrupt enable bit, interrupt request bit
Controls interrupt request from peripheral
Interrupt controller
Interrupt control register (ICR)
Sets interrupt level and controls EI2OS
Interrupt enable flag (I)
Identifies interrupt enable state
Interrupt level mask register (ILM)
Compares requested interrupt level and current interrupt level
Microcode
Executes interrupt routine
Interrupt vector table
Stores branch destination address at interrupt processing
CPU
"FFFC00H" to "FFFFFFH"
in memory
■ Hardware Interrupt Inhibition
No hardware interrupt requests are inhibited under following conditions.
● Hardware interrupt inhibition during write to resource control register in I/O area
No hardware interrupt requests are accepted during write to resource control register. This prevents the
CPU from malfunctioning with respect to interrupt requests generated during rewrite related to interrupt
control registers of each resource.
Figure 3.5-5 shows the hardware interrupt operation during write to the resource control register.
Figure 3.5-5 Hardware Interrupt Request During Write to the Resource Control Register
Write instruction of peripheral function control register
MOV A,#08
MOV io,A
MOV A,2000H
interrupt
Not transition to
request generateat hardware
this point
interrupt processing
70
Interrupt processing
Transition to hardware
interrupt processing
CHAPTER 3 CPU
● Hardware interrupt inhibition by interrupt inhibit instruction
Table 3.5-8 shows the hardware interrupt inhibit instructions.
If a hardware interrupt occurs during execution of a hardware interrupt inhibit instruction, the interrupt is
processed after execution of the hardware interrupt inhibit instruction and other instructions.
Table 3.5-8 Hardware Interrupt Inhibit Instructions
Prefix Code
Instruction that does not
accept interrupt request
PCB
DTB
ADB
SPB
CMR
NCC
Interrupt Inhibit Instruction
MOV ILM,#imm8
OR CCR,#imm8
AND CCR,#imm8
POPW PS
● Hardware interrupt inhibition during execution of software interrupt
When a software interrupt is started, the interrupt enable flag (CCR: I) is cleared to 0 and the interrupt is
disabled.
71
CHAPTER 3 CPU
3.5.6
Operation of Hardware Interrupt
The operation from the generation of hardware interrupt request to the completion of
interrupt processing is explained below.
■ Start of Hardware Interrupt
● Operation of peripheral (generation of interrupt request)
The peripherals with a hardware interrupt request function have an interrupt request flag indicating the
generation of an interrupt request, as well as an interrupt enable flag selecting between enabling and
disabling an interrupt request. The interrupt request flag is set when events inherent to peripherals occur.
When the interrupt enable flag is set to enabled, an interrupt request is generated to the interrupt controller.
● Operation of interrupt controller (control of interrupt request)
The interrupt controller compares the interrupt level (ICR: IL2 to IL0) of simultaneously generated
interrupt requests, selects the request with the highest level (with the smallest IL setting value), and posts it
to the CPU. If there are two or more interrupt requests with the same level, the interrupt request with the
smallest interrupt number is given priority.
● Operation of CPU (interrupt request acceptance and interrupt processing)
The CPU compares the received interrupt level (ICR: IL2 to IL0) with the value of the interrupt level mask
register (ILM) and generates an interrupt processing microcode after end of the current instruction
execution if the interrupt level (IL) is smaller than the value of the interrupt level mask register (ILM) and
an interrupt is enabled (CCR: I = 1).
When the EI2OS enable bit (ICR: ISE) is set to "0", ordinary interrupt processing is performed. If the bit is
set to "1", the EI2OS starts.
At interrupt processing, the values of the dedicated registers (A, DPR, ADB, DTB, PCB, PC and PS) are
saved in the system stack (system stack space indicated by SSB and SSP) first.
Next, the address of the vector table corresponding to the generated interrupt is loaded to the program
counter (PCB, PC), the interrupt level mask register (ILM) is updated, and the stack flag (CCR: S) is set to
"1".
■ Return from Hardware Interrupt
When the interrupt processing program clears, the interrupt request flag in the resource that causes the
interrupt to execute the RETI instruction, the values of the dedicated registers saved in the system stack are
returned to each register and returns to process execution before the interrupt processing.
The interrupt request output to the interrupt controller by the resource is cleared by clearing the interrupt
request flag.
72
CHAPTER 3 CPU
■ Operation of Hardware Interrupt
Figure 3.5-6 shows the operation from the generation of hardware interrupt to the completion of interrupt
processing.
Figure 3.5-6 Operation of Hardware Interrupt
Internal bus
PS
PS,PC
(7)
I
ILM
IR
Micro code
F2MC-16LXCPU
(6)
Check
Comparator
(5)
(4)
(3)
Other peripheral function
Peripheral function of
interrupt request generate
Enable FF
(8)
AND
Factor FF
Level
comparator
Interrupt
level IL
(2)
(1)
Interrupt controller
RAM
IL : Interupt level setting bit of interupt control register (ICR)
PS : Processor status
I
: Interrupt enable flag
ILM : Interrupt level mask register
IR : Instruction register
FF : Flip flop
(1) The peripheral generates an interrupt request.
(2) When the interrupt enable bit in the peripheral is set to enabled, the peripheral generates an interrupt
request to the interrupt controller.
(3) The interrupt controller that received the interrupt request determines the priority of interrupts
simultaneously requested and posts the interrupt level (IL) corresponding to the appropriate interrupt
request to the CPU.
(4) The CPU compares the interrupt level (IL) requested from the interrupt controller with the value of the
interrupt level mask register (ILM).
(5) If the interrupt request is preferred to the interrupt mask register (ILM), the interrupt enable flag (CCR:
I) is checked.
(6) When an interrupt is enabled by the interrupt enable flag (CCR: I = 1), the requested interrupt level (IL)
is set to the interrupt level mask register (ILM) after completion of the current instruction execution.
(7) The values of the dedicated registers are saved, and processing transfers to interrupt processing.
(8) The program clears the interrupt request generated from the peripheral and executes the interrupt return
instruction (RETI) to terminate interrupt processing.
73
CHAPTER 3 CPU
3.5.7
Procedure for Use of Hardware Interrupt
The settings of the system stack area, resources, interrupt control registers (ICR) are
required for using the hardware interrupt.
■ Procedure for Use of Hardware Interrupt
Figure 3.5-7 shows an example of the procedure for use of the hardware interrupt.
Figure 3.5-7 Procedure for Use of Hardware Interrupt
Start
(1)
Setting the system stack area
(2)
Setting the peripheral function interrupt
Interrupt processing program
(3)
ICR setting in interrupt
controller
(4)
Setting starting operation
of perpheral function
Setting enable interrupt
enable bit
(5)
Stack processing
branch to interrupt vector
(7)
Processing
by hardware
Setting ILM, I in PS
(7)
Processing of interrupt for
peripheral function
(execution of interrupt
processing)
(8)
Clear of interrupt request
(10)
Interrupt return instruction (RETI)
Main program
(6)
Interrupt request generate
Main program
(1) Set the system stack area.
(2) Set an interrupt of the peripheral with the interrupt request function.
(3) Set the interrupt control register (ICR) in the interrupt controller.
(4) Set the resource to start operation and the interrupt enable bit to enabled.
(5) Set the interrupt level mask register (ILM) and the interrupt enable flag (CCR: I) ready to accept an
interrupt (CCR: I = 1).
(6) An interrupt generated from the resource generates a hardware interrupt request.
(7) The interrupt controller saves data in the dedicated registers, and processing transits to interrupt
processing.
(8) Execute the program for interrupt generation at interrupt processing.
(9) Clear the interrupt request from the peripheral.
(10)Execute the interrupt return instruction (RETI) to return to the program executed before transition to
interrupt processing.
74
CHAPTER 3 CPU
3.5.8
Multiple interrupts
Multiple hardware interrupts can be generated by setting different interrupt levels in the
interrupt level setting bits of the interrupt control register (ICR: ILO to IL2) in response
to multiple interrupt requests from the resource. However, multiple EI2OS cannot be
started.
■ Multiple interrupts
● Multiple Interrupts
If an interrupt request with a higher priority than the interrupt level of the current interrupt processing is
generated during interrupt processing, the current interrupt processing is suspended to accept the generated
higher-level interrupt request. When the higher-level interrupt processing is terminated, the suspended
interrupt processing is resumed.
The interrupt level (IL) can be set to "0" to "7". The interrupt request set to level 7 is never accepted.
If an interrupt request with a priority equal to or lower than the interrupt level of the current-executing
interrupt is generated during interrupt processing, unless the setting of the interrupt enable flag (CCR: I) or
the interrupt level mask register (ILM)
Starting of multiple interrupts generated during interrupt processing can be disabled temporarily by setting
the interrupt enable flag (CCR: I) to disabled (CCR: I= 0) or the interrupt level mask register (ILM) to
disabled (ILM = 000).
Note:
Multiple EI2OS cannot be started. During EI2OS processing, other interrupt requests
and other EI2OS requests are all put on hold.
75
CHAPTER 3 CPU
● Example of multiple interrupts
As an example of multiple interrupt processing, assuming that a timer interrupt is preferred to an A/D
converter interrupt, set the interrupt level of the A/D converter to 2 and the interrupt level of the timer to 1.
Figure 3.5-8 shows the processing of the timer interrupt generated during processing of the A/D converter
interrupt.
Figure 3.5-8 Example of multiple interrupts
Main program
(ILM=111B)
A/D interrupt processing (ILM=010B)
Interrupt level 2
Timer interrupt processing (ILM=001B)
(IL=010B)
Setting interrupt (1)
Interrupt level 1
(IL=001B)
(3) Timer interrupt generate
(2)
A/D interrupt
(4) Timer interrupt
generate
Suspend
processing
Restart
Main processing (8)
restart
(6) A/D interrupt processing
(5) Timer interrupt
return
(7) A/D interrupt return
• When processing of the A/D converter interrupt is started, the interrupt level mask register (ILM) is set
automatically to the value (2 in example) of the interrupt level (ICR: IL2 to IL0) of the A/D converter.
When an interrupt request with an interrupt level of 1 or 0 is generated under this condition, processing
the generated interrupt is preferred.
• When the interrupt return instruction (RETI) is executed after the completion of interrupt processing, the
values of the dedicated registers (A, DPR, ADB, DTB, PCB, PC, PS) saved in the system stack are
returned to each register and the interrupt level mask register (ILM)
76
CHAPTER 3 CPU
3.5.9
Software interrupt
The software interrupt is a function for transiting control from the current-executing
program to the interrupt processing program defined by user by execution of a software
interrupt instruction (INT instruction). The software interrupt is held during execution of
a software interrupt.
■ Start and operation of software interrupt
● Start of Software Interrupt
A software interrupt is started by executing the INT instruction. It does not have an interrupt request flag or
an interrupt enable flag. An interrupt request is generated immediately after the INT instruction is executed.
● Hardware interrupt inhibition
Interrupts by the INT instruction have no interrupt level and the interrupt level mask register (ILM) is not
updated. During execution of the INT instruction, the interrupt enable flag (CCR: I) is set to "0" and a
hardware interrupt is masked.
When enabling a hardware interrupt during software interrupt processing, set the interrupt enable flag
(CCR: I) to "1" during software interrupt processing.
● Operation of software interrupt
When the INT instruction is executed, the software interrupt processing microcode in the CPU is started.
The software interrupt processing microcode saves the values of the dedicated registers in the system stack;
branching to the address of the corresponding interrupt vector table after a hardware interrupt is masked
(CCR: I = 0).
■ Return from Software Interrupt
When the interrupt return instruction (RETI) is executed in the interrupt processing program, the values of
the dedicated registers saved in the system stack are returned to each register and the operation is returned
to the processing performed before branching to interrupt processing.
Note:
When the program bank register (PCB) is "FFH", the vector area for the CALLV
instruction overlaps the table for the INT #vct8 instruction. A CALLV and INT #vct8
instructions can not use the same address in creating a program.
77
CHAPTER 3 CPU
3.5.10
Interrupts by extended intelligent I/O service (EI2OS)
EI2OS is a function to automatically transfer data between the peripherals (I/O) and
memory. It generates the hardware interrupt at termination of data transfer.
■ EI2OS
The EI2OS provides automatic data transfer between the I/O area and memory. When data transfer is
terminated, the termination factor (end condition) is set, branching automatically to the interrupt processing
routine. Data can be transferred just by creating a setup program for starting the EI2OS and an end
program.
● Advantages of EI2OS
Compared to data transfer using the interrupt-processing routine, EI2OS has the following advantages.
• Since the creation of transfer program is not required, the program size can be reduced.
• The transfer count can be set to prevent transfer of unnecessary data.
• Whether to update the buffer address pointer can be specified.
• Whether to update the I/O address pointer can be specified.
● Interrupt by EI2OS termination
At completion of data transfer by the EI2OS, the end condition is set in the EI2OS status bits (ICR: S1, S0),
and then the processing automatically transits to interrupt processing.
The EI2OS termination factor can be determined by checking the EI2OS status bits (ICR: S1, S0) using the
interrupt processing program.
● Interrupt control register (ICR)
This register is within the interrupt controller, and displays the states at starting, setting channel, and
terminating the EI2OS.
● EI2OS descriptor (ISD)
The EI2OS descriptor (ISD), which is allocated between "000100H" and "00017FH" in internal RAM, is 8byte data that is used to set the transfer mode, addresses, transfer count and buffer addresses. It has 16
channels, and a channel number is allocated to each of these channels by the interrupt control register
(ICR).
Note:
78
The CPU stops while the EI2OS is in operation.
CHAPTER 3 CPU
■ Operation of EI2OS
Figure 3.5-9 shows the operation of the EI2OS.
Figure 3.5-9 Operation of EI2OS
Memory space
By IOA
I/O area
00 Bank area
(5)
CPU
Interrupt request
(2)
(3)
(1)
By ICS
ISD
Interrupt control register (ICR)
(3)
Interrupt controller
By BAP
(4)
Buffer
Count by DCT
ISD : EI2OS Descriptor
IOA : I/O address pointer
BAP : Buffer address pointer
ICS : EI2OS chanel selct bit of Interrupt control register (ICR)
DCT : Data counter
(1) An interrupt request is generated and the EI2OS is started.
(2) The interrupt controller selects the EI2OS descriptor.
(3) The transfer-source and transfer-destination address pointers are read from the EI2OS descriptor.
(4) Data is transferred according to the transfer-source and transfer-destination address pointers.
(5) An interrupt factor is cleared automatically.
79
CHAPTER 3 CPU
3.5.11
EI2OS descriptor (ISD)
The EI2OS descriptor (ISD) is allocated to the addresses "000100H" to "00017FH" in the
internal RAM, and consists of 8 bytes x 16 channels.
■ Configuration of EI2OS Descriptor (ISD)
ISD consists of 8 bytes x 16 channels, and each ISD is composed as shown in Figure 3.5-10. Table 3.5-9
shows the correspondence between the channel number and ISD address.
Figure 3.5-10 Configuration of EI2OS Descriptor (ISD)
MSB
LSB
Data counter upper 8bit (DCTH)
H
Data counter lower 8bit (DCTL)
I/O address pointer upper 8bit (IOAH)
I/O address pointer lower 8bit (IOAL)
EI2OS status register (ISCS)
Buffer address pointer upper 8bit (BAPH)
Buffer address pointer middle 8bit (BAPM)
ISD head address
(000100H + 8 × ICS)
Buffer address pointer lower 8bit (BAPL)
ICS: EI2OS channel select bit (ICR: ICS3 to ICS0)
Table 3.5-9 EI2OS Descriptor (ISD) Area (1/2)
80
Channel
(ICR: ICS3 to ICS0)
Descriptor header Address
0
000100H
1
000108H
2
000110H
3
000118H
4
000120H
5
000128H
6
000130H
7
000138H
8
000140H
L
CHAPTER 3 CPU
Table 3.5-9 EI2OS Descriptor (ISD) Area (2/2)
Channel
(ICR: ICS3 to ICS0)
Descriptor header Address
9
000148H
10
000150H
11
000158H
12
000160H
13
000168H
14
000170H
15
000178H
81
CHAPTER 3 CPU
3.5.12
Each Register of EI2OS Descriptor (ISD)
The EI2OS descriptor (ISD) consists of the following registers.
• Data counter (DCT)
• I/O address pointer (IOA)
• EI2OS status register (ISCS)
• Buffer address pointer (BAP)
The reset value of each register is undefined and a reset should be performed carefully.
■ Data counter (DCT)
The data counter (DCT) is a 16-bit register, and corresponds to the transfer data count. It decrements by
one each time data is transferred. When the data counter (DCT) reaches 0, the EI2OS is terminated and then
the processing transits to interrupt processing.
Figure 3.5-11 shows the configuration of the data counter (DCT).
Figure 3.5-11 Configuration of Data Counter (DCT)
DCTL
DCTH
bit15 14 13 12 11
10
9 bit8 bit7
6
5
4
3
2
1
bit0
DCT B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00
Reset value
XXXXXXXX XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/W R/W R/W
R/W : Read/Write
X : Undefined
■ I/O address pointer (IOA)
The I/O address pointer (IOA) is a 16-bit register that sets the low addresses (A15 to A0) of the 00 bank
area where data is transferred to or from the buffer. The high addresses (A23 to A16) are set all to "0" and
the area between "000000H" and "00FFFFH" can be addressed.
Figure 3.5-12 shows the configuration of I/O address pointer (IOA).
Figure 3.5-12 Configuration of I/O Address Pointer (IOA)
IOAL
IOAH
bit15 14 13 12 11
10
9 bit8 bit7
6
5
4
3
2
1
bit0
IOA A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/W R/W R/W
R/W: Read/Write
X : Undefined
82
Reset value
XXXXXXXX XXXXXXXXB
CHAPTER 3 CPU
■ EI2OS Status Register (ISCS)
The EI2OS status register (ISCS) is an 8-bit register that sets the method to update the buffer address
pointer and I/O address pointer, transfer data format (byte/word), and transfer direction.
Figure 3.5-13 shows the bit configuration of the EI2OS status register (ISCS).
Figure 3.5-13 Configuration of EI2OS Status Register (ISCS)
7
6
5
4
3
2
1
0
Reset value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit0
SE
0
1
El2OS terminate control bit
Not termination by the termination request from a peripheral resource
Termination by the termination request from a peripheral resource
bit1
DIR
0
1
buffer address pointer
I/O address pointer
Buffer address pointer I/O address pointer
bit2
BF
0
1
Buffer address pointer is updated after data transfer.*1
Buffer address pointer is not updated after data transfer.
bit3
BW
0
1
Byte
Word
bit4
IF
0
1
I/O address pointer is updated after data transfer.*2
I/O address pointer is not updated after data transfer.
bit7
bit6
Data transfer direction specification bit
BAP updating/fixed select bit
Transfer data length specification bit
IOA updating/fixed select bit
bit5
Reserved Reserved Reserved
0
0
0
Reserved bit
Always write to this bit "0".
R/W: Read/Write
X: Undefined
*1: The buffer address pointer changes only in the lower 16 bits and enables in increment only.
*2: I/O address pointer enables in increment only.
83
CHAPTER 3 CPU
■ Buffer address pointer (BAP)
The buffer address pointer (BAP) is a 24-bit register and sets the 16-MB addresses where data is transferred
to or from I/O area. When the BAP updating/fixing select bit of the EI2OS status register (ISCS: BF) is set
to updated (ISCS: BF=0), the buffer address pointer (BAP) changes only in the lower 16 bits (BAPH,
BAPL) and does not change in the higher 8 bits (BAPH). Figure 3.5-14 shows the configuration of the
buffer address pointer (BAP).
Figure 3.5-14 Configuration of Buffer Address Pointer (BAP)
bit23
BAP
bit16 bit15
BAPH
R/W
bit8 bit7
bit0
BAPM
BAPL
R/W
R/W
Reset value
XXXXXXH
R/W: Read/Write
X : Undefined
References:
84
• The area that can be set by the I/O address pointer (IOA) is "000000H" to
"00FFFFH".
• The area that can be set by the buffer address pointer (BAP) is "000000H" to
"FFFFFFH".
• The maximum transfer count that can be set by the data counter (DCT) is 65,536.
CHAPTER 3 CPU
3.5.13
Operation of EI2OS
The flowchart of operation of the EI2OS using the microcode in the CPU is shown
below:
■ Operation of EI2OS
Figure 3.5-15 Flowchart of Operation of EI2OS
Interrupt request generate
from peripheral resource
ISD : EI2OS descriptor
ISCS : EI2OS status register
IF
: IOA update/fixed select bit
BW : Transfer data length specification bit
BF
: BAP update/fixed select bit
DIR : Data transfer direction specification bit
SE
: EI2OS terminate control bit
DCT : Data counter
IOA : I/O address pointer
BAP : Buffer address pointer
ISE : EI2OS enable bit (ICR)
S1,S0 : EI2OS status (ICR)
NO
ISE=1
YES
Interrupt processing
ISD/ISCS rread
Termination by the
termination request from
a peripheral resource ?
YES
NO
NO
YES
DIR=1?
NO
Address setting for IOA
(Data transfer)
Address setting for BAP
Address setting for BAP
(Data transfer)
Address setting for IOA
YES
IF=0?
NO
Updating value
is by BW
IOA updating
YES
BF=0?
NO
YES
SE=1?
Updating value
is by BW
DCT decrement
DCT="00H"?
NO
Set "00B" to S1, S0
BAP updating
(-1)
YES
EI2OS terminate processing
Set "01B" to S1, S0
Set "11B" to S1, S0
Clear of peripheral
resourceinterruptewquest
Clear ISE to "0"
CPU operation return
Interrupt processing
85
CHAPTER 3 CPU
3.5.14
Procedure for Use of EI2OS
The procedure for using the EI2OS is shown below:
■ Procedure for Use of EI2OS
Figure 3.5-16 Procedure for Use of EI2OS
Processing by software
Processing by hardware
Start
Initialization
Setting of system stack area
Setting of EI2OS Descriptor
Setting of peripheral resource
interruption
Setting of interrupt
control register(ICR)
Setting the start
operation of resource
and interrupt enable bit
Setting ILM, I in PS
S1, S0=00B
(Interrupt request) and (ISE=1)
Execution of user program
Data transfer
Transfer termination of specified
number or Identification of transfer
to interrupt by termination
request from peripheral resources
(transfer to interrupt processing)
Resetting of
intelligent I/O Service
(Switching channels)
Data processing during buffer
RETI
ISE
: Enable bit EI2OS (ICR)
S1, S0 : EI2OS status (ICR)
86
YES
S1, S0=01B or
S1, S0=11B
NO
CHAPTER 3 CPU
3.5.15
EI2OS Processing Time
The time required for EI2OS processing depends on the following factors:
• Setting of EI2OS status register (ISCS)
• Data length of transfer data
Some interrupt handling time is required at the transition to hardware interrupt
processing after completion of data transfer.
■ EI2OS Processing Time (time for one transfer)
● For continuous data transfer (DCT ≠ 0, ISCS: SE=0)
The EI2OS processing time at continuing data transfer is determined by the setting of the EI2OS status
register (ISCS) as shown in Table 3.5-10.
Table 3.5-10 Extended Intelligent I/O Service Execution Time
Setting of the EI2OS termination control bit
(SE)
Termination by the termination
request from a peripheral resource
Setting of the IOA updating/fixing select bit
(IF)
Setting of BAP address updating/
fixing select bit (BF)
The termination request from the
peripheral resource is ignored.
fixed
Update
fixed
Update
fixed
32
34
33
35
Update
34
36
35
37
Unit: One machine cycle is equal to one clock cycle of the machine clock (φ).
In addition, compensation is required depending on the conditions at executing EI2OS as shown in Table
3.5-11.
Table 3.5-11 Compensation Value for Data Transfer at EI2OS Processing Time
Internal Access
I/O Register Address Pointer
Buffer address pointer
B/even
Odd
B/even
0
+2
Odd
+2
+4
Internal Access
B: Byte data transfer
Even: Word transfer at even address
Odd: Word transfer at odd address
87
CHAPTER 3 CPU
● At end of data counter (DCT) (DCT ≠ 0, ISCS: SE=0)
At completion of data transfer by the EI2OS, since the hardware interrupt is started, the interrupt handling
time is added. The EI2OS processing time at the end of counting is calculated by the following expression.
El2OS Processing Time after count finish
=El2OS Processing Time at continuing data transfer + (21 + 6 × Z)
Machine clock
Interrupt handling time
(Z: compensation value of interrupt handling time)
The interrupt handling time depends on the address set by the stack pointer. Table 3.5-12 shows the
compensation value (Z) of the interrupt handling time.
Table 3.5-12 Compensation Value (Z) of Interrupt Handling Time
Address Set by Stack Pointer
Compensation Value (Z)
For internal area (even address)
0
For internal area (odd address)
+2
● At termination by termination request from peripheral (DCT ≠ 0, ISCS=1)
If data transfer by the EI2OS is terminated during its processing by the termination request from a resource
(ICR: S1, S0 = "11B"), processing transits to interrupt processing. The EI2OS processing time at a
termination request from a resource is calculated as follows:
El2OS Processing Time at halting =36 + 6 × Z
Machine cycle
(Z: compensation value of interrupt handling time)
Reference:
88
One machine cycle is equal to one clock cycle of the machine clock (φ).
CHAPTER 3 CPU
3.5.16
Exception Processing Interrupt
The F2MC-16LX family performs exception processing when an undefined instruction is
executed.
Exception is basically the same as interrupt. When an exception is detected between
instructions, normal processing is suspended to perform exception processing.
Exception processing is performed when an unexpected operation is performed, and
should be used only for starting recovery software at debugging or in an emergency.
■ Exception processing
● Operation of exception processing
The F2MC-16LX family treats all instruction codes not defined in the instruction map as undefined
instructions. If an undefined instruction is executed, the processing equal to the software interrupt
instruction "INT # 10" is performed.
At exception processing, the following processing is performed before the transition to interrupt
processing:
• The values of dedicated registers (A, DPR, ADB, DTB, PCB, PC, PS) are saved to the system stack
• The interrupt enable flag (CCR: I) cleared to "0" and interrupts disabled
• The stack flag (CCR: S) set to "1"
The value of the program counter (PC) saved in the stack is a value of the address where undefined
instructions are stored. For instruction codes of 2 bytes or more, the value of the program counter (PC) is a
value of the address where instruction codes that can be identified as undefined are stored. When the type
of exception factor must be determined at exception processing, use the saved program counter (PC).
● Return from exception processing
When the program counter (PC) indicates an undefined instruction, the interrupt return instruction (RETI)
from exception processing is executed to return to exception processing. Some measures such as
performing a software reset should be taken when returning from exception processing.
89
CHAPTER 3 CPU
3.5.17
Time Required to Start Interrupt Processing
The time for terminating the currently executing instruction plus the interrupt handling
time is required from generation of the hardware interrupt request to execution of the
interrupt-processing.
■ Time Required to Start Interrupt Processing
The interrupt request sampling wait time and the interrupt handling time (time required for preparation for
interrupt processing) are required from generation of the interrupt request and acceptance of interrupt, to
execution of the interrupt processing. Figure 3.5-17 shows the interrupt processing time.
Figure 3.5-17 Interrupt Processing Time
Operation of CPU
Interrupt waiting time
Normal onsstruction execution
Interrupt request
sampling waiting time
Interrupt handling
Interrupt processing
Interrupt handling time
(θ machinecycle)*
Interrupt request generate
: Instruction last cycle, sampling interrupt request here
* : One machine cycle is equal to one clock cycle of the machine clockO Service (φ).
● Interrupt request sampling wait time
It indicates a time from the generation of the interrupt request to the termination of the currently executing
instruction.
Whether the interrupt request is generated or not is determined by sampling the interrupt request in the last
cycle of each instruction. The CPU cannot recognize the interrupt request during execution of each
instruction, as a result wait time occurs.
Reference:
The interrupt request sampling wait time is longest when the interrupt request is
generated immediately after starting execution of the POPW, RW0,... RW7
instructions with the longest execution cycle (45 machine cycles).
● Interrupt handling time (θ machine cycles)
The CPU requires an interrupt handling time of θ machine cycles to save the dedicated registers to the
system stack and fetch the interrupt vector table address after accepting the interrupt request. The interrupt
handling time (θ) is obtained using the following equations.
θ = 24 + 6 x Z machine cycles (Z: compensation value of interrupt handling time)
The interrupt handling time depends on the address set by the stack pointer. Table 3.5-13 shows the
compensation value (Z) of the interrupt handling time.
90
CHAPTER 3 CPU
Table 3.5-13 Compensation Value (Z) of Interrupt Handling Time
Address Set by Stack Pointer
Reference:
Compensation
Value (Z)
For internal area (even address)
0
For internal area (odd address)
+2
One machine cycle is equal to one clock cycle of the machine clock (φ).
91
CHAPTER 3 CPU
3.5.18
Stack Operation for Interrupt Processing
When an interrupt request is accepted, the values of dedicated registers are
automatically saved to the system stack before transition to interrupt processing. At
completion of interrupt processing, the values of the dedicated registers are
automatically returned from the system stack.
■ Stack Operation at Starting Interrupt Processing
When an interrupt is accepted, the CPU automatically saves the values of the current-dedicated registers in
the system stack in the following order.
• Accumulator (AH, AL)
• Direct page register (DPR)
• Additional data bank register (ADB)
• Data bank register (DTB)
• Program bank register (PCB)
• Program counter (PC)
• Processor status (PS)
Figure 3.5-18 shows the stack operation at starting interrupt processing.
Figure 3.5-18 Stack Operation at Starting Interrupt Processing
Immediatelypreceding interrupt
SSB
00H
SSP
08FEH
A
0000H
AH
Address
08F2H
08FEH
AL
DPR 01H
ADB 00H
DTB
PCB FFH
PC
PS
00H
803FH
20E0H
Immediately-after
interrupt
Memory
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
XXH
08FEH
08FFH
Lower
SSB
00H
SSP
08F2H
A
0000H
AH
08F2H
08FEH
AL
DPR 01H
ADB 00H
00H
PCB FFH
DTB
PC
803FH
SP
PS
Byte
Address
20E0H
Upper
Memory
E0H
20H
3FH
80H
FFH
00H
00H
01H
FEH
08H
00H
00H
08FEH
08FFH
SP after
updating
PS
PC
PCB
DTB
ADB
DPR
AL
AH
SP
Byte
■ Stack Operation at Return from Interrupt Processing
When the interrupt return instruction (RETI) is executed after completion of interrupt processing, the
values of the dedicated registers (PS, PC, PCB, DTB, ADB, DPR, AL, AH) are returned to each register
from the system stack, and the dedicated registers return to the condition before interrupt started.
92
CHAPTER 3 CPU
3.5.19
Program Example of Interrupt Processing
This section gives a program example of interrupt processing.
■ Program Example of Interrupt Processing
● Processing specification
This is an example of interrupt program using external interrupt 4 (INT4).
● Coding example
DDR2
EQU 000012H
;Port 2 direction register
ENIR
EQU 030H
;Interrupt/DTP enable register
EIRR
EQU 031H
;Interrupt/DTP flag
ELVR
EQU 032H
;Request level setting register
ICR00
EQU 0B0H
;Interrupt control register
STACK
SSEG
;Stack
RW
100
STACK_T RW
1
STACK
ENDS
;----------Main program----------------------------------CODE
CSEG
;
START:
MOV RP,#0
;Using the head bank as general
purpose register
MOV ILM,#07H
;Setting ILM in PS to level 7
MOV A,#!STACK_T
;Setting of system stack
MOV SSB,A
MOVW A,#STACK_T
;Setting of stack pointer,
LOOP
MOVW SP,A
;in this case,S flag=1,so set to SSP
MOV
OR
DDR2,#00000000B
CCR,#40H
;Setting P24/INT4 pin to input
;I flag of CCR in PS set to interrupt enabled
MOV
MOV
MOV
MOV
:
NOP
NOP
NOP
NOP
BRA
I:ICR00,#00H
I:ELVR,#00010000B
I:EIRR,#00H
I:ENIR,#10H
;Interrupt level 0 (strongest)
;Regard INT4 as H level request
;Clear interrupt factor of INT4
;Input enable of INT4
;Dummy roop
LOOP
;Jump without condition
93
CHAPTER 3 CPU
;----------Interupt program------------------------------------ED_INT1:
MOV I:EIRR,#00H
;Prohibition of new INT4 reception
NOP
NOP
NOP
NOP
NOP
NOP
RETI
;Recover from interrupt
CODE
ENDS
;----------Vector setting---------------------------------------VECT
CSEG ABS=0FFH
ORG 0FFD0H
;Setting vector to interrupt #11(0BH)
DSL ED_INT1
ORG 0FFDCH
;Setteing of reset vector
DSL START
DB
00H
;Setting to single chip mode
VECT
ENDS
END START
■ Extended Intelligent I/O Service (EI2OS) program
● Processing specification
• EI2OS is started upon detection of the High level of the signal input to the INT4 pin.
• When the High level is input to the INT4 pin, EI2OS is started and the data at port 2 is transferred to
memory address "3000H".
• The transfer data size is 100 bytes. After 100 bytes are transferred, an interrupt is generated upon
completion of transfer by EI2OS.
● Coding example
DDR2
ENIR
EIRR
ELVR
ICR00
BAPL
BAPM
BAPH
ISCS
IOAL
IOAH
DCTL
DCTH
ER0
STACK
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
000012H
000030H
000031H
000032H
0000B0H
000100H
000101H
000102H
000103H
000104H
000105H
000106H
000107H
EIRR:0
SSEG
RW
100
STACK_T RW
1
STACK
ENDS
94
;Port 2 direction register
;Interrupt/DTP enable register
;Interrupt/DTP factor register
;Request level setting register
;Interrupt control register
;Buffer address pointer lower
;Buffer address pointer middle
;Buffer address pointer upper
;EI2OS status
;I/O address pointer lower
;I/O address pointer upper
;Data counter lower
;Data counter upper
;Definition of external interrupt
request flag bit
;Stack
CHAPTER 3 CPU
;----------Main program----------------------------------CODE
CSEG
START:
AND CCR,#0BFH
;I flag of CCR in PS cleared to interrupt disabled
MOV
MOV
MOV
MOVW
MOVW
RP,#00
A,#!STACK_T
SSB,A
A,#STACK_T
SP,A
;Setting register bank pointer
;Setting system stack
MOV
MOV
I:DDR2,#00000000B
BAPL,#00H
;Setting P24/INT4 pin to input
;Setting buffer address
;(003000H)
MOV
MOV
MOV
BAPM,#30H
BAPH,#00H
ISCS,#00010001B
MOV
IOAL,#00H
MOV
MOV
MOV
MOV
IOAH,#00H
DCTL,#64H
;Setting transmission byte number(100 bytes)
DCTH,#00H
I:ICR00,#00001000B ;EI2OS channel 0,EI2OS enable,
;Interrupt level 0(strongest)
I:ELVR,#00010000B ;Regard INT4 as "H" level request
I:EIRR,#00H
;Clear interrupt factor of INT4
I:ENIR,#10H
;Interrupt enable of INT4
ILM,#07H
;Setting ILM in PS to level 7
CCR,#40H
;I flag of CCR in PS set to interrupt enabled
MOV
MOV
MOV
MOV
OR
;Setting system stack pointer
;in this case,S flag=1,so set to SSP
;Without I/O address renewal,byte transmission,
;With buffer address renewal
;Data transferred from I/O to buffer,
;and termination by resource
;Setting transmission source address
;(port 2: 000002H)
:
LOOP:
BRA LOOP
;No limit roop
;----------Interrupt program------------------------------------WARI
CLRB ER0
;Clear interrupt/DTPrequest flag
:
User processing
;Check finish factor of EI2OS,
:
;Processing of data in buffer,
;Re-setting of EI2OS, etc.
RETI
CODE
ENDS
----------Vector setting----------------------------------------VECT
CSEG ABS=0FFH
ORG
0FFD0H
;Setting vector to interrupt #11(0BH)
DSL
WARI
ORG
0FFDCH
;Reset vector setting
DSL
START
DB
00H
;Setting to single chip mode
VECT
ENDS
END
START
95
CHAPTER 3 CPU
3.6
Reset
When a reset trigger even occurs, the CPU immediately suspends the current process
and starts the reset operation. The reset factors are as follows:
• Power on reset
• Watchdog timer overflow
• Generation of software reset request
• Generation of external reset request (RST pin)
■ Reset Factor
Table 3.6-1 Reset Factor
Reset
Factor
Machine
clock
Watchdog timer
Oscillation Stabilization
Waiting
Power on reset
At power on
MCLK
Stops
Yes
Watchdog timer
reset
Watchdog timer overflow
MCLK
Stops
None
Software reset
"0" is written to the RST bit
MCLK
Stops
None
External reset
Input "L" level to RST pin
MCLK
Stops
None
MCLK: Main clock
● Power on reset
• The power on reset occurs at power on.
• The reset operation is executed after the oscillation stabilization wait time of 218/HCLK has elapsed.
● Watchdog timer reset
• Unless the watchdog timer is periodically cleared at the interval time to be repeatedly counted after
starting, an overflow occurs, causing a reset.
• The oscillation stabilization wait time is not generated by a watchdog timer reset.
Note:
For details on the watchdog timer, see "CHAPTER 6 WATCHDOG TIMER".
● Software reset
• The software reset occurs when "0" is written to the internal reset signal generation bit (LPMCR: RST)
in the low-power consumption mode control register.
• The oscillation stabilization wait time is not generated by a software reset.
96
CHAPTER 3 CPU
● External reset
• The external reset occurs when a Low level is input to the external reset pin (RST pin). The time for
inputting Low level from the RST pin requires at least 16 machine cycles (main clock).
• An external reset does not require the oscillation stabilization wait time.
Notes:
•
If an external reset request is generated from the RST pin during writing by a
transfer instruction (such as MOV), the reset cancel wait state is set after
completion of the transfer instruction, so writing is terminated normally. For a string
instruction (such as MOVS), the reset cancel wait state may be set before
completion of transfer by a specified counter value.
• To return from stop mode, subclock mode, subsleep mode, or watch mode to main
clock mode using the external reset pin (RST pin), input the Low level for at least
"oscillator's oscillation time* + 100 μs + 16 machine cycles (main clock)".
*: The oscillation time for the oscillator is the period of time taken until its amplitude
reaches 90%. It takes several to dozens of ms for crystal oscillators, hundreds of
μs to several ms for ceramic oscillators, and 0 ms for external clocks.
97
CHAPTER 3 CPU
3.6.1
Reset Factors and Oscillation Stabilization Wait Times
The oscillation stabilization wait state after reset varies depending on the reset factors.
■ Reset Factors and Oscillation Stabilization Wait Times
Table 3.6-2 Reset Factors and Oscillation Stabilization Wait Times
Oscillation Stabilization Wait Time
Parenthesized values are examples calculated at an oscillation clock frequency of 4 MHz.
Reset Factor
Power on reset
216/HCLK*
watchdog reset
None
Software reset
None
External reset
None
HCLK: Oscillation clock frequency
*: MB90V495G requires 218/HCLK.
Figure 3.6-1 MB90895 series oscillation stabilization wait time at generating power-on reset
VCC
CLK
CPU operation
215/HCLK
Oscillation
time of oscillator
216/HCLK
Wait time for stabilizing oscillation
HCLK: Oscillation clock frequency
98
CHAPTER 3 CPU
Table 3.6-3 Oscillation stabilization wait time setting by clock select register (CKSCR)
Clock select bit
Oscillation Stabilization Wait Time
Parenthesized values are examples calculated
at an oscillation clock frequency of 4 MHz.
WS1
WS0
0
0
210/HCLK (256μs)
0
1
213/HCLK (approx.2.048ms)
1
0
214/HCLK (approx.4.1ms)*1
1
1
215/HCLK (approx.8.19ms)*1,*2
HCLK: Oscillation clock frequency
*1: MB90V495G requires 215/HCLK when WS1/0 = "10" and 217/HCLK when WS1/0 = "11".
*2: The oscillation stabilization wait time taken when the power supply is turned on is fixed at 216/HCLK (about
16.38 ms). However, MB90V495G is fixed at 218/HCLK (approximately 65.54ms).
Note:
Ceramic or crystal oscillators require an oscillation stabilization wait time of several
milliseconds to some tens of milliseconds to stabilize oscillation. Set the oscillation
stabilization wait time required for the oscillator to be used.
Reference:
For clock, see "3.7 Clock".
99
CHAPTER 3 CPU
3.6.2
External Reset Pin
The external reset pin (RST pin) is a reset input pin. Input of an external Low level
generates a reset factor. MB90895 series starts the reset operation in synchronization
between the CPU and clock.
■ Block Diagram of External Reset Pin
Figure 3.6-2 Block Diagram of External Reset Pin
RST
P-ch
Pin
N-ch
CPU operating clock (PLL multiplier circuit,
2-frequency division of HCLK)
Synchronization
of circuit
HCLK: Oscillation colck
Notes:
100
Internal reset siganal
Input buffer
• To prevent memory from being broken due to a reset during writing to memory, a
Low level is input to the RST pin in a machine cycle in which memory is not
broken.
• The CPU operation clock is required to initialize internal circuits. During operation
using an external clock, in particular, the reset signal and CPU operation clock
signal must be input.
CHAPTER 3 CPU
3.6.3
Reset Operation
During reset operation, the mode for reading mode data and reset vectors is set
according to the settings of the mode pins (MD0 to MD2) and a mode fetch is executed.
When the oscillation clock is returned from stop states (power on, stop mode) by a
reset, a mode fetch is executed after the elapse of the main clock oscillation
stabilization wait time.
■ Flowchart of Reset Operation
Figure 3.6-3 shows the flowchart of reset operation.
Figure 3.6-3 Flowchart of Reset Operation
Power-on-reset
Software reset
External reset (RST pin)
Watchdog timer reset
Reset operation
Oscillation stabilization waiting time
Reset cancel
Mode data fetched
Bus mode pin setting
Reset sequence
Reset vector fetched
Normal operation
(RUN state)
Execution of processing from
address that reset vector shows
■ Oscillation Stabilization Wait Time in Standby Mode
When a reset occurs during operation in a stop mode or sub clock mode in which the oscillation clock is
stopped, and oscillation stabilization wait time of 215/HCLK (approximately 8.19 ms when the oscillation
clock operates at 4 MHz) is generated. MB90V495G requires an oscillation stabilization wait time of
217/HCLK (about 32.77 ms).
Reference:
For standby mode operation, see 3.8 "Low-power Consumption Mode".
■ Mode Pin
The MD0 to MD2 mode pins are external pins. They are used to set the mode for reading data and reset
vectors.
Reference:
For details on the mode pins (MD0 to MD2), see 3.9.3" Memory Access Mode".
101
CHAPTER 3 CPU
■ Mode Fetch
At transition to the reset operation, the CPU automatically transfers mode data and reset vectors by
hardware to the appropriate register in the CPU core. The mode data and reset vector are allocated to four
bytes of addresses "FFFFDCH" to "FFFFDFH". After a reset trigger event occurs (or after the lapse of
oscillation stabilization wait time if generated), the CPU immediately outputs the addresses of the mode
data and reset vectors to the bus to input the mode data and reset vectors. This operation is called "mode
fetch". At completion of mode fetch, the CPU starts processing from the address indicated by the reset
vector.
Figure 3.6-4 Transfer of Mode Data and Reset Vectors
F2MC-16LX CPU core
Memory space
PC
FFFFDCH
Reset vector : bit 7 to 0
FFFFDDH
Reset vector : bit 15 to 8
FFFFDEH
FFFFDFH
PCB
Reset vector : bit 23 to 16
CPU mode data
Reset sequence
Micro ROM
Mode register
Note:
The mode for reading mode data and reset vectors from internal ROM is set
according to the settings of the mode pins (MD0 to MD2). To use the mode pins in
single-chip mode, set them to the internal vector mode.
● Mode Data
The mode data is used to set a memory access mode or a memory access area. It is allocated to address
"FFFFDFH". During the reset operation, this data is read automatically by a mode fetch and stored in the
mode register.
● Reset vectors
The reset vectors are the start addresses of execution after completion of the reset operation. They are
allocated to addresses "FFFFDCH" to "FFFFDEH". During the reset operation, these vectors are read
automatically by a mode fetch and transferred to the program counter.
Note:
102
This is hard wird reset vector on MB90F897/S.
See "19.6 Check the Execution State of Automatic Algorithm".
CHAPTER 3 CPU
3.6.4
Reset Factor Bit
To check reset factors, read the value of the watchdog timer control register (WDTC).
■ Reset Factor Bit
Each reset factor provides a flip-flop circuit corresponding to each factor. The state of the flip-flop circuit
can be checked by reading the value of the watchdog timer control register (WDTC). If it is necessary to
identify reset factors after completion of the reset operation, read the value of the watchdog timer control
register (WDTC) by software to branch to the appropriate program.
Figure 3.6-5 Block Diagram of Reset Factor Bits
RST pin
Power on
Power on
generate
detection circuit
Watchdog timer
control register
(WDTC)
Without clear
during interval time
RST=L
External reset
request
detection circuit
Watchdog taimer
reset generate
detection circuit
RST bit set
LPMCR register
RST bit program
detection circuit
Clear
S
R
S
F/F
Q
R
S
F/F
Q
R
S
F/F
Q
R
F/F
Q
Delay
circuit
Watchdog timer
control register
(WDTC) read
F2MC-16LX internal bus
S : Set
R : Reset
Q : Out put
F/F : Flip Flop
103
CHAPTER 3 CPU
■ Correspondence of Reset Factor Bit and Reset Factor
Figure 3.6-6 shows the configuration of the reset factor bits in the watchdog timer control register (WDTC:
PONR, WRST, ERST, SRST).
Figure 3.6-6 Configuration of Reset Factor Bit
Watchdog timer control
register (WDTC)
bit7
bit6
PONR
-
R
-
bit5
bit4
bit3
bit2
bit1
bit0
Reset value
WRST ERST SRST WTE WT1 WT0
R
R
R
W
W
XXXXX111B
W
R : Read only
W : Write only
X : Indefined
Table 3.6-4 Correspondence of Reset Factor Bit and Reset Factor
Reset Factor
PONR
WRST
ERST
SRST
Generating power-on reset
1
X
X
X
Reset by watchdog timer
*
1
*
*
Input of external reset signal to RST pin
*
*
1
*
Software reset bit
*
*
*
1
*: The previous state is held.
X: Undefined
104
CHAPTER 3 CPU
■ Notes on Reset Factor Bit
● Power on reset
When a power on reset is executed, the PONR bit is set to "1" after completion of the reset operation. Any
reset factor bit other than the PONR bit is undefined. When the PONR bit is "1" after completion of the
reset operation, ignore the value of any bit other than the PONR bit.
● At two or more reset factors
The reset factor bit is set to "1" according to each reset factor even when two or more reset factors are
generated. For example, if the watchdog timer overflows and an external reset request is generated from the
RST pin at the same time, both WRST and ERST bits are set to "1" after completion of the reset operation.
● Clearing of reset factor bit
Once set, the reset factor bit is not cleared even if any reset factor other than the set factor is generated. The
reset factor bit is cleared after the completion of reading the watchdog timer control register (WDTC).
Reference:
For details on the watchdog timer, see "CHAPTER 6 WATCHDOG TIMER".
105
CHAPTER 3 CPU
3.6.5
State of Each Pin at Reset
This section explains the state of each pin at reset.
■ State of Pins at Reset
The state of the pins during reset operation is determined by the settings of the mode pins (MD2 to MD0).
● When internal vector mode set:
• If the internal vector mode is set, all I/O pins enter the high-impedance state and mode data is read to
internal ROM.
■ State of Pins after Mode Data Read
• The I/O pins are all set to the high-impedance state, and the mode data read destination is the internal
ROM.
Note:
106
Be careful not to let those devices malfunction which are connected to pins that enter
the high impedance state when a reset trigger event occurs.
CHAPTER 3 CPU
3.7
Clock
The clock generation section controls the internal clock that is an operating clock for
the CPU or resources. The clock generated by the clock generation section is called a
machine clock and one cycle of the machine clock is a machine cycle. The clock to be
supplied from a high-speed oscillator is called an oscillation clock and the 2- frequency
division of the oscillation clock is called a main clock. The 4-frequency division of a
clock to be supplied from a low-speed oscillator is called a sub clock and the clock to
be supplied from the PLL oscillator circuit is called a PLL clock.
■ Clock
The clock generation section has oscillators and generates an oscillation clock by connecting an oscillator
to oscillation pins. External clocks that are input to the oscillation pins can be used as oscillation clocks.
The PLL clock multiplying circuit can be used to generate four clocks for multiplying the oscillation clock.
The clock generation section controls the oscillation stabilization wait time, PLL clock multiplying circuit,
and selects internal clock by the clock selector.
● Oscillation clock (HCLK)
This clock is generated by connecting an oscillator or inputting an external clock to the high-speed
oscillation pins (X0 and X1).
● Main clock (MCLK)
This clock is 2-frequency division of oscillation clock. It is an input clock to the timebase timer and clock
selector.
● Sub clock (SCLK)
This clock has a 4-frequency division of the clock generated by connecting an oscillator or inputting an
external clock to the low-speed oscillation pins (X0A and X1A). It can also be used as an operating clock
for the watch timer or as a low-speed machine clock.
● PLL clock (PCLK)
This clock is multiplied by the PLL clock multiplying circuit (PLL oscillator). It can be selected from four
types of clock according to the setting of the multiplication rate select bits (CKSCR: CS1, CS0).
107
CHAPTER 3 CPU
● Machine clock
This clock is an operating clock for the CPU and the resources. One cycle of the machine clock is a
machine cycle (1/φ). One clock can be selected from the main clock sub clock, and four types of PLL
clock.
Notes:
• When the operating voltage is 5V, the oscillation clock can oscillate at 3 to 16 MHz. The
maximum operating frequency of the CPU and peripheral resources is 16 MHz. If a
multiplier that exceeds the maximum operating frequency is set, the device does not
operate normally. When the oscillation clock frequency is 16 MHz, therefore, the PLL clock
multiplier can be set only to 1. The PLL oscillator oscillates in the range of 3 to 16 MHz,
which varies depending on the operating voltage and multiplier.
• There is no sub-clock in MB90F897S.
108
CHAPTER 3 CPU
■ Clock Supply Map
Machine clocks generated by the clock generation section are supplied as operating clocks of the CPU and
peripherals. The operation of the CPU and peripheral peripherals is affected by switching between the main
clock and subclock or PLL clock (clock mode) or by switching the PLL clock multiplier. The clockdivided output of the timebase timer is supplied to some peripherals, and the operating clock can be
selected for each peripheral.
Figure 3.7-1 shows the clock supply map.
Figure 3.7-1 Clock Supply Map
Peripheral functions
4
4
Watch timer
8/16 bit
PPG timer 0,1
Time base timer
8/16 bit
PPG timer 2,3
Clock generator
X0A
Pin
X1A
Pin
X1
Pin
PPG0,1
Pin
PPG2,3
Pin
TIN0
Pin
Sub clock
generator
1 2 3 4
16 bit
reload timer 0
PLL multiplying circuit
X0
Pin
Watchdog timer
SCLK PCLK
Oscillation
2-frequency
clock
Clock selector
division
generator HCLK
MCLK
TOT0
Pin
2/4-frequency
division
φ
Communication prescaler 1
UART1
SCK1
Pin
SOT1
Pin
SIN1
Pin
CPU Intermittent
operation
TIN1
Pin
CPU
16-bit
reload timer 1
TOT1
Pin
ADTG
Pin
8/10-bit
A/D converter
IN0,1,2,3
Pin
Input capture
unit
16-bit
free-run-timer
CAN controller
HCLK: Oscillation clock
PCLK: PLL clock
SCLK: Sub clock
φ : Machine clock
3
RX
Pin
TX
Pin
Oscillation
stabilization waiting time
109
CHAPTER 3 CPU
3.7.1
Block Diagram of Clock Generation Section
The clock generation section consists of the following five blocks:
• Oscillation clock generator/sub clock generator
• PLL multiplying circuit
• Clock selector
• Clock select register (CKSCR)
• Oscillation stabilization wait time selector
■ Block Diagram of Clock Generation Section
Figure 3.7-2 shows the block diagram of the clock generation section. It also includes the standby
controller and timebase timer circuit.
Figure 3.7-2 Block Diagram of Clock Generation Section
Standby control cicuit
Low-power Consumption mode control register (LPMCR)
CPUintermittent
operation cycle
selector
Re-
STP SLP SPL RST TMD CG1 CG0 served
2
CPU clock
control circuit
CPU
operation
clock
Peripheral clock
control circuit
Peripheral
function
operation clock
Clock mode
Sleep signal
Stop signal
S
Q
S
R
Reset
Interrupt
Q
Machine
clock
R
S
S
Q
Q
R
R
Operation clock
selector
Oscillation
stabilization
wait time selector
2
2
PLL multiplying
circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock select register (CKSCR)
X0 Pin
X1 Pin
Oscillation
clock
Oscillation clock
generator (HCLK)
X0A Pin
2frequency
division
4frequency
division
2frequency
division
Sub clock
2frequency
division
2frequency
division
2frequency
division
To watchdog timer
1024-frequency
division
Watch timer
Sub clock generator
110
1024frequency
division
Main
clock Timebase timer
4-frequency
division
X1A Pin
S : Set
R : Reset
Q : Output
2frequency
division
8frequency
division
2frequency
division
2frequency
division
2frequency
division
CHAPTER 3 CPU
● Oscillation clock generator
This generator generates an oscillation clock (HCLK) by connecting an oscillator or inputting an external
clock to the high-speed oscillation pins.
● Sub clock generator
This generator generates a sub clock (SCLK) by connecting an oscillator or inputting an external clock to
the low-speed oscillation pins (X0A, X1A).
● PLL multiplying circuit
This circuit multiplies the oscillation clock and supplies it as a PLL clock (PCLK) to the clock selector.
● Clock selector
This selector selects the clock that is supplied to the CPU or resources from the main clock, sub clock, and
four types of PLL clock.
● Clock select register (CKSCR)
This register is used to select between the oscillation clock and PLL clock, between the main clock and
subclock, the oscillation stabilization wait time, and the PLL clock multiplier.
● Oscillation stabilization wait time selector
This selector selects the oscillation stabilization wait time of the oscillation clock.These bits are used to
select one from four timebase timer outputs.
Note:
There is no sub-clock in MB90F897S.
111
CHAPTER 3 CPU
3.7.2
Register in Clock Generation Section
This section explains the register in the clock generation section.
■ Register in Clock Generation Section and List of Reset Values
Figure 3.7-3 Clock Select Register and List of Reset Values
bit
Clock select register (CKSCR)
112
15
14
13
12
11
10
9
8
1
1
1
1
1
1
0
0
CHAPTER 3 CPU
3.7.3
Clock select register (CKSCR)
The clock select register (CKSCR) is used to switch the clock mode between main
clock, subclock, and PLL clock and to select the oscillation stabilization wait time and
the PLL clock multiplier.
■ Clock select register (CKSCR)
Figure 3.7-4 Clock select register (CKSCR)
15
14
13
12
11
10
9
8
Reset value
11111100B
R
R
R/W R/W R/W R/W R/W R/W
PSCCR: bit9
bit8
Multiplying select bit
CS2 CS1 CS0
Parenthesized values are examples calculated at an
oscillation clock frequency of 4 MHz.
0
0
0
1 × HCLK (4MHz)
0
0
1
2 × HCLK (8MHz)
0
1
0
3 × HCLK (12MHz)
0
1
1
4 × HCLK (16MHz)
1
0
0
2 × HCLK (8MHz)
1
0
1
4 × HCLK (16MHz)
1
1
0
Unavailable
1
1
1
Unavailable
bit10
MCS
PLL clock select bit
0
Select PLL clock
1
Select main clock
bit11
SCS
0
Sub clock select bit
Select sub clock
Select main clock
1
bit13 bit12
Oscillation stabilization wait time select bit
WS1 WS0
Parenthesized values are examples calculated at an
oscillation clock frequency of 4 MHz.
0
0
210/HCLK (approx.256 μs)
0
1
1
0
213/HCLK (approx.2.05ms)
214/HCLK (approx.4.1ms)*
1
1
bit14
MCM
PLL clock operation bit
0
Operating in PLL clock
1
Operating in main clock or sub clock
bit15
SCM
HCLK : Oscillation clock
R/W : Read/Write
R
: Read only
: Reset value
215/HCLK (approx.8.19ms, other than power-on reset)*
216/HCLK (approx.16.38ms, power-on reset only)*
0
Sub clock operation bit
Operating in sub clock
1
Operating in main clock or PLL clock
*: When WS1/0="10" 215/HCLK (appox.8.19ms) in MB90V495G
WS1/0="11" 217/HCLK (appox.32.77ms, other than power-on reset)
218/HCLK (appox.65.54ms, power-on reset only)
113
CHAPTER 3 CPU
Table 3.7-1 Functions of clock select register (CKSCR) (1/2)
bit name
Function
bit15
SCM:
sub clock operating
flag bit
The bit indicates the main clock or sub clock currently selected as the machine clock.
• When the subclock flag bit (CKSCR: SCM) is "0" and the subclock select bit (CKSCR: SCS) is
"1", it indicates that the machine clock is currently switching from subclock to main clock.When
the subclock flag bit (CKSCR: SCM) is "1" and the subclock select bit (CKSCR: SCS) is "0", it
indicates that the machine clock is currently switching from main clock to subclock.
• Write is no effect on operation.
bit14
MCM:
PLL clock operation
flag bit
The bit indicates the main clock or PLL clock currently selected as the machine clock.
• When the PLL clock flag bit (CKSCR: MCM) is "1" and the PLL clock select bit (CKSCR:
MCS) is "0", it indicates that the oscillation stabilization wait time of the PLL clock is currently
being taken.
• Write is no effect on operation.
bit13,
bit12
WS1, WS0:
oscillation stabilization
wait time select bit
These bits are used to select an oscillation stabilization wait time required for the oscillation clock
when the stop mode is canceled, when transition occurs from subclock mode to main clock mode, or
when transition occurs from subclock mode to PLL clock
• These bits are used to select one from four timebase timer outputs.
Any reset causes the bit to return to the reset value.
Note:
Set the oscillation stabilization wait time to an appropriate value depending on the oscillator
used.See 1.6.1 Reset Factors and Oscillation Stabilization Wait Times.
The oscillation stabilization wait time taken when the clock mode is switched from main clock
to PLL clock is fixed at 214/HCLK (about 4.1 ms during operation at an oscillation clock
frequency of 4 MHz).When the CPU switches from subclock mode to PLL clock mode or when
it returns from PLL stop mode to PLL clock mode, the oscillation stabilization wait time follows
the values specified in these bits.
The PLL clock requires an oscillation stabilization wait time of at least 214/HCLK. For
switching from subclock mode to PLL clock mode, therefore, set these bits to 10B or 11B.
bit11
SCS:
sub clock selection bit
This bit indicates the main clock or sub clock to be selected as the machine clock.
• When the machine clock is switched from the main clock to the subclock (CKSCR: SCS = 1 →
0), the main clock mode changes to the subclock mode in synchronization with the subclock
(about 130 μs).
• When the machine clock is switched from the subclock to the main clock (CKSCR: SCS = 0 →
1), the clock mode changes from subclock mode to main clock mode after the main clock
oscillation stabilization wait time is generated.Timebase timer is cleared automatically.
Any reset causes the bit to return to the reset value.
Notes:
1) When both of the MCS and SCS bits contain 0, the SCS bit supersedes the MCS bit, thereby
setting the subclock mode.
2) If both the subclock select bit (CKSCR: MCS) and PLL clock select bit (CKSCR: SCS)
contain 0, the subclock is preferred.
3) When switching from the main clock to subclock (CKSCR: SCS = 1 → 0), use the timebase
timer interrupt enable bit (TBTC: TBIE) or interrupt level mask register (ILM: ILM2 to 0) to
disable timebase timer interrupts before writing 0 to the subclock select bit.
4) The sub clock oscillation stabilization wait time (approximately 2 s) is generated at power on
or at cancellation of the stop mode.If the clock mode is switched from main clock mode to
subclock mode, therefore, the oscillation stabilization wait time is generated.
5) There is no sub-clock in MB90F897S.Set the reset value.
114
CHAPTER 3 CPU
Table 3.7-1 Functions of clock select register (CKSCR) (2/2)
bit name
Function
bit10
MCS:
PLL clock select bit
This bit indicates the main clock or PLL clock to be selected as the machine clock.
When the machine clock is switched from the main clock to the PLL clock (CKSCR: MCS = 1 → 0),
the clock mode changes from main clock mode to PLL clock mode after the PLL clock oscillation
stabilization wait time is generated.The timebase timer is cleared automatically.The oscillation
stabilization wait time taken when the clock mode is switched from main clock to PLL clock is fixed
at 214/HCLK (about 4.1 ms during operation at an oscillation clock frequency of 4 MHz).The
oscillation stabilization wait time taken when the machine clock is switched from subclock mode to
PLL clock mode follows the values specified in the oscillation stabilization wait time select bits
(CKSCR: WS1, WS0).
Any reset causes the bit to return to the reset value.
Notes:
1) When both of the MCS and SCS bits contain 0, the SCS bit supersedes the MCS bit, thereby
setting the subclock mode.
2) When switching from the main clock to PLL clock (CKSCR: MCS = 1 → 0), use the
timebase timer interrupt enable bit (TBTC: TBIE) or interrupt level mask register (ILM:
ILM2 to 0) to disable timebase timer interrupts before writing 0 to the PLL clock select bit.
bit9,
bit8
CS1, CS0:
the multiplication rate
select bits
The PLL clock multiplier is selected from among seven options depending on the combination of
PSCCR: CS2 and CKSCR: CS1/CS0.
Any reset causes the bit to return to the reset value.
Note:
When the PLL clock is selected (CKSCR: MCS = 0), writing is inhibited.To change the
multiplier, write 1 to the PLL clock select bit (CKSCR: MCS), update the multiplier select bits
(CKSCR: CS1, CS0), then set the PLL clock select bit (CKSCR: MCS) back to 0.
115
CHAPTER 3 CPU
3.7.4
PLL/subclock control register (PSCCR)
The PLL/subclock control register (PSCCR) is used to switch the subclock frequency
divide ratio (selecting division by 2 or 4) and to set the PLL clock multiplier (division by
1, 2, 3 or 4).
■ PLL/subclock control register (PSCCR)
Figure 3.7-5 PLL/subclock control register (PSCCR)
15
14
13
12
11
Address:003FH
-
-
-
-
Reserved
Read/Write
(-)
(-)
(-)
(-)
(W)
(W)
(W)
(W)
Initial value
(X)
(X)
(X)
(X)
(0)
(0)
(0)
(0)
bit
10
9
8
SCDS Reserved CS2
The register is used to set the subclock frequency divide ratio and to set the PLL clock multiplier.
The PLL clock multiplier can be set to "1", "2", "3, or "4" depending on the combination of the clock select
register (CKSCR: CS0/CS1) and this register (PSCCR: CS2).
This register must always be set in main clock mode.
Table 3.7-2 Functions of PLL/subclock control register (PSCCR)
bit name
116
Function
bit15
to
bit12
Unused bits
Write: No effect on operation
Read: Read value undefined
bit11
Reserved
Be sure to set this bit to "0".
bit10
SCDS
4-frequency division (8 kHz)
2-frequency division1:(16 kHz)
bit9
Reserved
Be sure to set this bit to "0".
bit8
CS2
Multiplication by 1, 2, 3, or 4 can be set.
Multiplication by 2 or 4 can be set.
CHAPTER 3 CPU
Table 3.7-3 PLL multiplier setting in PSCCR:CS2 and CKSCR:CS1/CS0
(Calculated assuming a frequency of 4 MHz)
Note:
CS2
CS1
CS0
Function
0
0
0
1×HCLK (4 MHz)
0
0
1
2×HCLK (8 MHz)
0
1
0
3×HCLK (12 MHz)
0
1
1
4×HCLK (16 MHz)
1
0
0
2×HCLK(8 MHz)
1
0
1
4×HCLK(16 MHz)
1
1
0
Unavailable
1
1
1
Unavailable
This feature is not provided for the MB90V495G.This register therefore returns "1"
whenever read.
117
CHAPTER 3 CPU
3.7.5
Clock Mode
Clock modes have a main clock mode, sub clock mode, and PLL clock mode.
■ Clock Mode
● Main clock mode
In the main clock mode, a clock with 2-frequency division of the clock generated by connecting an
oscillator or inputting an external clock to the high-speed oscillation pins (X0, X1) is used as the operating
clock for the CPU or peripherals.
● Sub clock mode
In the sub clock mode, a clock with 4-frequency division of the clock generated by connecting an oscillator
or inputting an external clock to the low-speed oscillation pins (X0A, X1A) is used as the operating clock
for the CPU or peripherals.
● PLL clock mode
In the PLL clock mode, the oscillation clock multiplied by the PLL clock multiplying circuit (PLL
oscillator circuit) is used as the operating clock for the CPU or peripherals.The PLL clock multiplication
rate can be set using the clock select register (CKSCR: CS1, CS0).
Note:
There is no sub-clock in MB90F897S.
■ Transition of Clock Mode
In clock modes, the setting of the PLL clock select bit (CKSCR: MCS) and sub clock select bit (CKSCR:
SCS) transits to the main clock mode, sub clock mode or PLL clock mode.
● Transition from main clock mode to PLL clock mode
If the PLL clock select bit (CKSCR: MCS) is rewritten from "1" to "0", the main clock switches to the PLL
clock after the PLL oscillation stabilization wait time (214/HCLK) has elapsed.
● Transition from PLL clock mode to main clock mode
If the PLL clock select bit (CKSCR: MCS) is updated from "0" to "1", the PLL clock switches to the main
clock when the edge of the PLL clock signal matches the edge of the main clock signal (after 1 to 8 PLL
clock cycles).
● Transition from main clock mode to sub clock mode
If the sub clock select bit (CKSCR: SCS) is rewritten from "1" to "0", the main clock switches to the sub
clock synchronizing the sub clock(approx.130μs).
118
CHAPTER 3 CPU
● Transition from sub clock mode to main clock mode
When the sub clock select bit (CKSCR: SCS) is rewritten from "0" to "1", the sub clock switches to the
main clock after the main clock oscillation stabilization wait time has elapsed.
Notes:
• For switching from subclock mode to main clock mode using the external reset pin
(RST pin), input the Low level for at least oscillator’s oscillation time* + 100 μs +
16 machine cycles (main clock).
*:The oscillation time for the oscillator is the period of time taken until its amplitude
reaches 90%.
It takes several to dozens of ms for crystal oscillators, hundreds of μs to several
ms for ceramic oscillators, and 0 ms for external clocks.
• There is no sub-clock in MB90F897S.
● Transition from PLL clock mode to sub clock mode
When the sub clock select bit (CKSCR: SCS) is rewritten from "1" to "0", the PLL clock switches to the
sub clock.
● Transition from sub clock mode to PLL clock mode
When the sub clock select bit (CKSCR: SCS) is rewritten from "0" to "1", the sub clock switches to the
PLL clock after the main clock oscillation stabilization wait time has elapsed.
■ Selection of PLL Clock Multiplication Rate
The PLL clock multiplication rate can be set from x1 to x4 by writing values of 00B to 11B to the
multiplication rate select bits (CKSCR: CS1, CS0).
■ Machine clock
The PLL clock, main clock, and sub clock output from the PLL multiplying circuit are used as machine
clocks. These machine are clocks supplied to the CPU or peripherals.Any of the main clock, PLL clock,
and sub clock can be selected by writing to the sub clock select bit (CKSCR: SCS) and the PLL clock
select bit (CKSCR: MCS).
Notes:
• The machine clock is not switched immediately even when the PLL clock select bit
(CKSCR: MCS) and subclock select bit (CKSCR: SCS) are updated. Before
running a peripheral resource that depends on the machine clock, switch the
machine clock to a desired clock, then reference the value of the PLL clock flag bit
(CKSCR: MCM) or subclock flag bit (CKSCR: SCM) to check that the machine
clock has been switched to the selected clock.
• When the PLL clock select bit (CKSCR: MCS) is "0" (PLL clock mode) and the
subclock select bit (CKSCR: SCS) is "0" (subclock mode), the SCS bit supersedes
the MCS bit, causing a transition to the subclock mode.
• While the clock mode is being switched, do not switch the CPU to any other clock
mode or to low power consumption mode until the current process of mode
switching is completed.Check the MCM and SCM bits in the clock select register
(CKSCR) to make sure that the transition to the new clock mode has been
completed. If the mode is switched to another clock mode or low power
consumption mode before completion of switching, the mode may not be
switched.
• There is no sub-clock in MB90F897S.
119
CHAPTER 3 CPU
Figure 3.7-6 shows the transition of a clock mode.
Figure 3.7-6 Clock Mode Transition
Main
MCS=1
MCM=1
SCS=1
SCM=1
CS1,CS0=xx
Main → Sub
MCS=1
MCM=1
SCS=0
(10)
SCM=1
CS1,CS0=xx
(8)
Sub
MCS=1
MCM=1
(16) SCS=0
(10) SCM=0
CS1,CS0=xx
(1)
(6)
Main → PLLx
MCS=0
MCM=1
SCS=1
SCM=1
CS1,CS0=xx
120
(9)
(11) Sub → Main
MCS=1
MCM=1
SCS=1
SCM=0
(2)
CS1,CS0=xx
(8)
(3)
(4)
(5)
(8)
(12) Sub → PLL
(13) MCS=0
MCM=1
(14) SCS=1
(15) SCM=0
CS1,CS0=xx
PLL1 → Main
MCS=1
(7) MCM=0
SCS=1
SCM=1
CS1,CS0=00
PLL1 mutiplier
MCS=0
MCM=0
(6) SCS=1
(8)
SCM=1
CS1,CS0=00
PLL1 → Sub
MCS=1
(17)
MCM=0
SCS=0
SCM=1
CS1,CS0=00
PLL2 → Main
MCS=1
(7) MCM=0
SCS=1
SCM=1
CS1,CS0=01
PLL2 mutiplier
MCS=0
MCM=0
(6) SCS=1
(8)
SCM=1
CS1,CS0=01
PLL2 → Sub
MCS=1
(17)
MCM=0
SCS=0
SCM=1
CS1,CS0=01
PLL3 → Main
MCS=1
(7) MCM=0
SCS=1
SCM=1
CS1,CS0=10
PLL3 mutiplier
MCS=0
MCM=0
(6) SCS=1
(8)
SCM=1
CS1,CS0=10
PLL3 → Sub
MCS=1
(17)
MCM=0
SCS=0
SCM=1
CS1,CS0=10
PLL4 → Main
MCS=1
(7) MCM=0
SCS=1
SCM=1
CS1,CS0=11
PLL4 mutiplier
MCS=0
MCM=0
(6) SCS=1
(8)
SCM=1
CS1,CS0=11
PLL4 → Sub
MCS=1
MCM=0
(17)
SCS=0
SCM=1
CS1,CS0=11
CHAPTER 3 CPU
(1) MCS bit "0" write
(2) Termination of PLL clock oscillation stabilization wait time & CS1,CS0=00
(3) Termination of PLL clock oscillation stabilization wait time & CS1,CS0=01
(4) Termination of PLL clock oscillation stabilization wait time & CS1,CS0=10
(5) Termination of PLL clock oscillation stabilization wait time & CS1,CS0=11
(6) MCS bit "1" write (include hardwarestandby and watchdogreset)
(7) Synchronous timin of PLL clock and main clock
(8) SCS bit "0" write
(9) Terminate of sub clock oscillration stabilization wait time (214/SCLK)
(10) SCS bit "1" write
(11) Termination of main clock oscillation stabilization wait time
(12) Termination of main clock oscillation stabilization wait time & CS1,CS0=00
(13) Termination of main clock oscillation stabilization wait time & CS1,CS0=01
(14) Termination of main clock oscillation stabilization wait time & CS1,CS0=10
(15) Termination of main clock oscillation stabilization wait time & CS1,CS0=11
(16) SCS bit "1" write, MCS bit"0" wreit
(17) Synchronous timing of PLL clock and ub ckock
MCS
MCM
SCS
SCM
CS1,CS0
Notes:
: PLL clock selector bit of Clock selecter register (CKSCR)
: PLL clock indicate bit of Clock selecter register (CKSCR)
: Sub clock selector bit of Clock selecter register (CKSCR)
: Sub clock indicate bit of Clock selecter register (CKSCR)
: Multiprecation selecter bit of Clock selecter register (CKSCR)
• The reset value of the machine clock is in the main clock mode (MCS = 1, SCS = 1)
• When SCS and MCS are both "0", SCS is preferred, and the sub clock is selected.
• For switching from subclock mode to PLL clock mode, set the oscillation
stabilization wait time select bits (WS1, WS0) in the CKSCR register to "10B" or
"11B".
• There is no sub-clock in MB90F897S.
121
CHAPTER 3 CPU
3.7.6
Oscillation Stabilization Wait Time
At power on or return from the stop mode when the oscillation clock is stopped, a time
until the oscillation clock stabilizes (oscillation stabilization wait time) is required after
starting an oscillation.The oscillation stabilization wait time is also required for
switching the clock mode from main clock mode to PLL clock or subclock mode and
from subclock mode to main clock or PLL clock mode.
■ Operation During Oscillation Stabilization Wait Time
Ceramic and crystal oscillators require some tens of milliseconds to reach a stable oscillation frequency
after starting oscillation.Therefore when, immediately after an oscillation starts, once the CPU operation is
disabled and then an oscillation stabilizes after the elapse of oscillation stabilization wait time, the machine
clock is supplied to the CPU.
The oscillation stabilization wait time varies with the type of oscillator (ceramic, crystal, etc.).It is
necessary to select a oscillation stabilization wait time appropriate to an oscillator to be used.The
oscillation stabilization wait time can be selected using the clock select register (CKSCR).
When the clock mode changes from main clock mode to PLL clock or subclock mode or from subclock
mode to main clock or PLL clock mode, the CPU runs to the previous clock during the oscillation
stabilization wait time. When the oscillation stabilization wait time has elapsed, the CPU changes to the
specified clock mode.
Figure 3.7-7 shows the oscillating operation immediately after it starts.
Figure 3.7-7 Operation after Oscillation Stabilization Wait Time
The oscillation time
for the oscillator
Oscillation
stabilization time
X1
Oscillating start
Note:
122
Oscillating stabilization
There is no sub-clock in MB90F897S.
Start the normal operation or
change to PLL clock/subclock
CHAPTER 3 CPU
3.7.7
Connection of Oscillator and External Clock
MB90895 series has a system clock generator and generates an internal clock by
connecting an oscillator to the oscillation pins. External clocks that are input to the
oscillation pins can be used as oscillation clocks.
■ Connection of Oscillator and External Clock
● Example of connection of crystal oscillator or ceramic oscillator
Figure 3.7-8 Example of connection of crystal oscillator or ceramic oscillator
X0
X1
C1
C2
MB90895 series
X0A
X1A
C3
C4
● Example of connection of external clock
Figure 3.7-9 Example of connection of external clock
X0
Open
X1
MB90895 series
X0A
Open
Note:
X1A
There is no sub-clock in MB90F897S.
123
CHAPTER 3 CPU
3.8
Low-power Consumption Mode
The CPU operation modes are classified as follows according to the selection of the
operation clock and the oscillation control of a clock. All the operation modes except
the PLL clock mode are low-power consumption modes.
• Clock modes (main clock, PLL clock and sub clock modes)
• CPU intermittent operation modes (main clock, PLL clock, and sub clock modes)
• Standby modes (sleep, stop, watch, and timebase timer modes)
■ CPU Operation Modes and Current Consumption
Figure 3.8-1 shows the relationships between the CPU operation mode and current consumption.
Figure 3.8-1 CPU Operation Modes and Current Consumption CPU
Consumption current
High
CPU
operating mode
PLL clock mode
4 multiplier clock
3 multiplier clock
2 multiplier clock
1 multiplier clock
PLL clockintermittent
operating mode
4 multiplier clock
3 multiplier clock
2 multiplier clock
1 multiplier clock
Main clock mode (21/HCLK)
Main clock intermittent operating mode
Subclock mode (SCLK)
Subclock intermittent operating mode
Standby mode
Sleep mode
Watch mode
Time base timer mode
Stop mode
Low
Low power consumption mode
This figure shows the image of operating mode and has some difference from actual consumption current.
124
CHAPTER 3 CPU
■ Clock Mode
● PLL clock mode
In PLL clock mode, the CPU and peripherals operate on a PLL multiplying clock of oscillation clock
(HCLK).
● Main clock mode
In main clock mode, the CPU and peripherals operate on a clock with 2-frequency division of oscillation
clock (HCLK). In this mode, the PLL multiplying circuit stops.
● Sub clock mode
In sub clock mode, the CPU and peripherals operate on a sub clock (SCLK).In this mode, the main clock
and PLL multiplying circuit stop.The sub clock oscillation stabilization wait time (approximately 2 s) is
generated at power on or at cancellation of the stop mode.If the clock mode is switched from main clock
mode to subclock mode, therefore, the oscillation stabilization wait time is generated.
Note:
Note:
There is no sub-clock in MB90F897S.
For the clock mode, see 3.7 "Clocks".
■ CPU Intermittent operation mode
In CPU intermittent operation mode, the CPU performs the intermittent operation with the high-speed clock
supplied to the peripherals to reduce the power consumption.In this mode, the intermittent clock is input to
only the CPU at accessing registers, internal memory, resources, or at the external access.
■ Standby Mode
The standby mode causes the standby control circuit to stop the supply of an operation clock to the CPU or
peripherals or to stop the oscillation clock (HCLK) in order to reduce power consumption.
● Sleep mode
The sleep mode stops supply of an operation clock to the CPU during operation in each clock mode.The
CPU stops and the peripherals operate in the clock mode before the transition to the sleep mode.The sleep
mode is divided into the main sleep mode, PLL sleep mode, and sub-sleep mode according to the clock
mode before the transition to the sleep mode.
● Watch mode
The watch mode operates only the sub clock (SCLK) and watch timer.The main clock and PLL clock
stop.All peripherals except the watch timer stop.
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CHAPTER 3 CPU
● Timebase timer mode
The timebase timer mode operates only the oscillation clock (HCLK), sub clock (SCLK), timebase timer,
and watch timer.Resources other than the timebase timer and watch timer stop.
● Stop mode
The stop mode stops the oscillation clock (HCLK) and sub clock (SCLK) during operation in each clock
mode.It enables data to be retained with the least power consumption.
Notes:
126
• While the clock mode is being switched, do not switch the CPU to any other clock
mode or to low power consumption mode until the current process of mode
switching is completed.Check the MCM and SCM bits in the clock select register
(CKSCR) to make sure that the transition to the new clock mode has been
completed. If the mode is switched to another clock mode or low power
consumption mode before completion of switching, the mode may not be
switched.
• There is no sub-clock in MB90F897S.
CHAPTER 3 CPU
3.8.1
Block Diagram of Low-power Consumption Circuit
This section shows block diagram of low-power consumption circuit.
■ Block Diagram of Low-power Consumption Circuit
Figure 3.8-2 Block Diagram of Low-power Consumption Circuit
Low power consumption mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0
Reserved
RST Pin
Pin High-Z
control circuit
Pin Hi-z control
Internal reset
generator
Internal reset
CPU intermittent
operation cycle selector
Select the intermittent cycle
CPU clock
control circuit
Clock, sleep and stop signal
Standby control
circuit
Reset (cancellation)
2
CPU operating
clock
Clock and stop signal
Interrupt (cancellation)
Peripheral clock
control circuit
Resources
operating clock
Cancellation of subclock oscillration stabilization time
Clock
generator
Cancellation of main clock oscillration stabilization time
Operating clock
selector
Machine clock
Oscillation
stabilization
selector
2
2
PLL multiplier
circuit
X0 Pin
X1 Pin
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock select register (CKSCR)
2-divided
Oscillation
clock (HCLK)
Main
clock
1024
-divided
2
-divided
4
-divided
2
-divided
Timebase timer
4-divided
1024
-divided
2
-divided
2
-divided
2
-divided
To watchdog timer
Oscillation clock
Sub clock
generator
(SCLK)
X0A Pin
2
-divided
8
-divided
2
-divided
2
-divided
Clock timer
X1A Pin
Sub clock generator
127
CHAPTER 3 CPU
● CPU intermittent operation selector
This selector selects the halt cycle count of the CPU clock in the CPU intermittent operation mode.
● Standby controller
The CPU clock controller and resource clock controller switch between the CPU operating clock and
resource operating clock to enter and cancel the standby mode.
● CPU clock controller
This controller supplies an operating clock to the CPU.
● Pin high-impedance controller
This controller causes the input/output pins to become high impedance in the watch mode, timebase timer
mode, and stop mode.
● Internal reset generator
This generator generates the internal reset signal.
● Low-power consumption mode control register (LPMCR)
This register transits a clock mode to, and cancels the standby mode, and sets the CPU intermittent
operation mode.
Note:
128
There is no sub-clock in MB90F897S.
CHAPTER 3 CPU
3.8.2
Registers for Setting Low-power Consumption Modes
This section explains the registers to be used to set lower-power consumption modes.
■ Low-power Consumption Mode Control Register and Reset Values
Figure 3.8-3 Low-power Consumption Mode Control Register and Reset Values
bit
Low power consumption control register
(LPMCR)
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0
129
CHAPTER 3 CPU
3.8.3
Low-power consumption mode control register (LPMCR)
The low-power consumption mode control register (LPMCR) transits an operation mode
to, and cancels the low-power consumption modes, generates an internal reset signal,
and sets the halt cycle count in the CPU intermittent operation mode.
■ Low-power consumption mode control register (LPMCR)
Figure 3.8-4 Low-power consumption mode control register (LPMCR)
7
6
5
4
3
W
W
R/W
W
W
2
1
0
Reset value
00011000B
R/W R/W R/W
bit0
Reserved bit
Reserved
0
Be sure to set this bit to 0.
bit2 bit1
CG1 CG0
CPU suspendedcycle number select bit
0
0
0 cycle (CPU clock = peripheral clock)
0
1
8 cycle (CPU clock: peripheral clock = 1: approx.3 to 4)
1
0
16 cycle (CPU clock: peripheral clock = 1: approx.5 to 6)
1
1
32 cycle (CPU clock: peripheral clock = 1: approx.9 to 10)
bit3
TMD
0
1
bit4
RST
0
1
bit5
SPL
0
1
Clock mode bit
Transfer to clock mode or timebase timer mode
No effect
Internal reset signal generation bit
Generate the internal reset of 3-machine cycle
No effect
Pin state specification bit
Hold I/O pin state
High-Z
Only in timebase timer, clock and stop mode
bit6
SLP
0
1
Sleep mode bit
No effect
Change to sleep mode
bit7
STP
R/W : Read/Write
: Write only
W
: Reset value
130
Stop mode bit
0
No effect
1
Change to stop mode
CHAPTER 3 CPU
Table 3.8-1 Functions of low-power consumption mode control register (LPMCR)
bit name
Function
bit7
STP:
stop mode bit
Transiting to the stop mode.
When the bit is set to "0": No effect.
When the bit is set to "1": The CPU enters the stop mode.
Read: "1" is always read.
• The bit is initialized to "0" when a reset or external interrupt occurs.
bit6
SLP:
sleep mode bit
Shift to sleep mode
When the bit is set to "0": No effect.
When the bit is set to "1": The CPU enters the sleep mode.
• The bit is initialized to "0" when a reset or external interrupt occurs.
• When the STP and SLP bits are set to "1" at the same time, the STP bit supersedes the SLP bit,
causing a transition to stop mode.
bit5
SPL:
setting pin state bit
The bit is used to set the state of input/output pins after transition to the stop mode, watch mode,
or timebase timer mode.
When the bit is set to "0": The current level of input/output pins is held.
When the bit is set to "1": The I/O pins enter a high impedance state.
• The bit is initialized to "0" at a reset.
bit4
RST:
Internal reset signal
generation bit
generating software reset
When the bit is set to "0": An internal reset signal for three machine cycles is generated.
When the bit is set to "1": No effect.
Read: "1" is always read.
bit3
TMD:
watch mode bit
Shift to watch mode or timebase timer mode
When the bit is set to "0": The CPU enters the watch mode.
When the bit is set to "1": No effect.
The bit is set to "1" when a reset or interrupt occurs.
Read: "1" is always read.
bit2,
bit1
CG1, CG0:
CPU halt cycle count
select bits
These bits are used to set the halt cycle count of the CPU clock in the CPU intermittent operation
mode.
• Any reset causes the bit to return to the reset value.
bit0
Reserved: reserved bit
Always set this bit to "0".
131
CHAPTER 3 CPU
Notes:
• To set the low power consumption mode control register (LPMCR) to enter a low power
consumption mode, use the instructions listed in Table 3.8-2.
• The low-power consumption mode transition instruction in Table 3.8-2 must always be
followed by an array of instructions highlighted by a line below.
MOV
LPMCR,#H'XX ; The low-power consumption mode transition instruction
in Table 3.8-2
NOP
NOP
JMP
$+3
; jump to next instruction
MOV
A,#H'10
; any instruction
The devices does not guarantee its operation after returning from the lowpower consumption mode if you place an array of instructions other than the
one enclosed in the dine.
• To access the low-power consumption mode control register (LPMCR) with C
language, refer to "■ Notes on Accessing the Low-Power Consumption Made
Control Register (LPMCR) to Enter the Standby Mode" in the section 3.8.8
"Precautions when Using Low-Power Consumption Mode".
• When writing in words in a low power consumption mode, write data to even
addresses.Writing to an odd address may cause a malfunction.
• To set that pin to high impedance which serves as a peripheral resource or as
a port in stop mode, watch mode, or timebase timer mode, disable the output
of the peripheral resource, then set the STP bit of the low power consumption
mode control register (LPMCR) to "1" or set the TMD bit to "0".
This applies to the following pins: P21/TOT0, P23/TOT1
• There is no sub-clock in MB90F897S.
Table 3.8-2 Instructions at Transition to Low-power Consumption Mode
MOV io,#imm8
MOV dir,#imm8
MOV eam,#imm8
MOV eam,Ri
MOV io,A
MOV dir,A
MOV addr16,A
MOV eam,A
MOVW io,#imm16
MOVW dir,#imm16
MOVW eam,#imm16
MOVW eam,RWi
MOVW io,A
MOVW dir,A
MOVW addr16,A
MOVW eam,A
SETB io:bp
SETB dir:bp
SETB addr16:bp
CLRB io:bp
CLRB dir:bp
CLRB addr16:bp
MOV @RLi+disp8,A
MOVW @RLi+disp8,A
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CHAPTER 3 CPU
3.8.4
CPU Intermittent operation mode
The CPU intermittent operation mode causes the CPU to operate intermittently with an
operating clock supplied to the CPU or resources to reduce power consumption.
■ Operation in CPU Intermittent Operation Mode CPU
The CPU intermittent operation mode halts the clock supplied to the CPU at every instruction execution
when the CPU accesses registers, internal memory, I/O, or resources delaying to start the internal
bus.Decreasing the CPU processing speed while supplying a high-speed clock to resources reduces the
power consumption.
• The count of machine cycles in which clock supply to the CPU halts is set by the CG1 and CG0 bits in
the low-power consumption mode control register (LPMCR).
• The instruction execution time in the CPU intermittent operation mode is determined by adding the
normal execution time to the compensation value obtained by multiplying count of accesses to registers,
internal memory, and resources by halt cycle count.
Figure 3.8-1 shows the clock operation in the CPU intermittent operation mode.
Figure 3.8-5 Clock Operation in CPU Intermittent Operation Mode
Peripheral clock
CPU clock
Suspended cycle
1-instruction
execution
cycle
Internal bus starts
133
CHAPTER 3 CPU
3.8.5
Standby Mode
The standby mode causes the standby control circuit to either stop supplying an
operation clock to the CPU and resources, or to stop the oscillation clock (HCLK) to
reduce power consumption.
■ the operating state in each standby mode
Table 3.8-3 shows the operating state in each standby mode.
Table 3.8-3 the operating state in each standby mode
Mode Name
Sleep
mode
timebase
timer
mode
Sub
clock
(SCLK)
Machine
clock
CPU
Resource
pin
external reset or
interrupt
Sub-sleep
mode
MCS=X
SCS=0
SLP=1
external reset or
interrupt
PLL sleep
mode
MCS=0
SCS=1
SLP=1
external reset or
interrupt
SPL=0
MCS=X
SCS=1
TMD=0
*1
MCS=X
SCS=1
TMD=0
*1
MCS=X
SCS=0
TMD=0
*2
MCS=X
SCS=0
TMD=0
*2
SPL=0
SPL=0
STP=1
SPL=1
STP=1
external reset or
interrupt*4
Hi-Z
*3
external reset or
interrupt*4
external reset or
interrupt*5
Hi-Z
*3
external reset or
interrupt*5
external reset or
interrupt*6
Hi-Z
*3
134
Setting disabled
MCS=1
SCS=1
SLP=1
SPL=1
stop
mode
Oscillation
clock
(HCLK)
Main sleep
mode
SPL=1
watch
mode
Transition
conditions
external reset or
interrupt*6
CHAPTER 3 CPU
: operation,
: stop,
: held in the state before transiting, Hi-Z: High impedance
*1: The timebase timer and watch timer operate.*2: The watch timer operates.
*3: The DTP/external interrupt input pin operates.
*4: Watch timer, timebase timer, and external interrupts
*5: Watch timer and external interrupts
*6: External interrupt INT6/INT7
MCS: PLL clock select bit in clock select register (CKSCR)
SCS: subclock select bit in the clock select register (CKSCR)
SPL: setting pin state bit of low-power consumption mode control register (LPMCR)
SLP: sleep mode bit of low-power consumption mode control register (LPMCR)
STP: stop mode bit of low-power consumption mode control register (LPMCR)
TMD: clock mode bit of low-power consumption mode control register (LPMCR)
Note:
There is no sub-clock in MB90F897S.
135
CHAPTER 3 CPU
3.8.5.1
Sleep Mode
The sleep mode stops the operating clock to the CPU during an operation in each clock
mode.The CPU stops and the resources continue to operate.
■ Transition to Sleep Mode
When the mode transits to the sleep mode by setting the low-power consumption mode control register
(LPMCR: SLP = 1, STP = 0), the mode transits to the sleep mode according to the settings of the MCS and
SCS bits in the clock select register (CKSCR).
Table 3.8-4 shows the settings of the MCS and SCS bits in the clock select register (CKSCR) and the sleep
modes.
Table 3.8-4 Clock select register (CKSCR) settings and sleep modes
Clock select register (CKSCR)
Sleep Mode to be transited
MCS
SCS
1
1
Main sleep mode
0
1
PLL sleep mode
1
0
0
0
Sub-sleep mode
Notes:
• If both the STP and SLP bits in the low-power consumption mode control register
(LPMCR) are set to "1" simultaneously, the STP bit is preferred and the mode
transits to the stop mode.When the SLP and TMD bits are set to "1" and "0",
respectively, at the same time, the TMD bit supersedes the SLP bit, causing a
transition to the timebase timer mode or watch mode.
• There is no sub-clock in MB90F897S.
● Data retention function
In the sleep mode, data in the dedicated registers such as accumulators and internal RAM are held.
● Operation when interrupt request generated
If an interrupt request is generated when the SLP bit in the low-power consumption mode control register
(LPMCR) is set to "1", the mode does not transit to the sleep mode.If the CPU is not ready to accept any
interrupt request, the instruction next to the currently executing instruction is executed.If the CPU is ready
to accept any interrupt request, an interrupt operation immediately branches to the interrupt processing
routine.
● Pin state
In the sleep mode, pins other than those used for bus input/output or bus control are held in the state before
transiting to the sleep mode.
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CHAPTER 3 CPU
■ Return from Sleep Mode
The sleep mode is cancelled by a reset factor or when an interrupt is generated.
● Return by reset factor
When the sleep mode is cancelled by a reset factor, the mode transits to the main clock mode after the sleep
mode is cancelled, transiting to the reset sequence.
Notes:
• For returning from subsleep mode to main clock mode using the external reset
pin (RST pin), input the Low level for at least oscillator’s oscillation time* + 100 μs
+ 16 machine cycles (main clock).
*: The oscillation time for the oscillator is the period of time taken until its
amplitude reaches 90%.
It takes several to dozens of ms for crystal oscillators, hundreds of μs to
several ms for ceramic oscillators, and 0 ms for external clocks.
• There is no sub-clock in MB90F897S.
● Return by interrupt
When a higher interrupt request than the interrupt level (IL) of 7 is generated from the resources in the
sleep mode, the sleep mode is cancelled.After the sleep mode is cancelled, as with normal interrupt
processing, the generated interrupt request is identified according to the settings of the I flag in the
condition code register (CCR), the interrupt level mask register (ILM), and the interrupt control register
(ICR).
• When the CPU is not ready to accept any interrupt request, the next instruction to the currently
executing instruction is executed.
• When the CPU is ready to accept any interrupt request, it branches immediately to the interrupt
processing routine.
Figure 3.8-6 shows the cancellation of sleep mode by an interrupt.
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CHAPTER 3 CPU
Figure 3.8-6 Cancellation of Sleep Mode by Interrupt
Set to interrupt flag of resources
INT generate (IL<7)
NO
No cancellation of sleep
No cancellation of sleep
YES
Cancellation of sleep
I=0
YES
Execute the next instruction
NO
ILM<IL
YES
NO
Execution of interrupt
process
Note:
138
When handling an interrupt, the CPU usually services the interrupt after executing
the instruction that follows the one specifying the sleep mode.
CHAPTER 3 CPU
3.8.5.2
Watch Mode
The watch mode operates only the sub clock (SCLK) and the watch timer.-The main
clock and PLL clock stop.
■ Transition to Watch Mode
In the sub clock mode, when 0 is written to the TMD bit in the LPMCR register according to the settings of
the low-power consumption mode control register (LPMCR), the mode transits to the watch mode.
● Data retention function
In the watch mode, data in the dedicated registers such as an accumulator and internal RAM are held.
● Operation when interrupt request generated
When interrupt request generated with the TMD bit of the low-power consumption mode control register
(LPMCR) set to "0" the mode does not transit to the watch mode.If the CPU is not ready to accept any
interrupt request, the instruction next to the currently executing instruction is executed.If the CPU is ready
to accept any interrupt request, an interrupt operation immediately branches to the interrupt processing
routine.
● Pin state
In the watch mode, the input/output pins can be set to the high-impedance state or held in the state before
transiting to the watch mode according to the setting of the SPL bit in the low-power consumption mode
control register (LPMCR).
Notes:
• To set that pin to high impedance which serves either for a peripheral resource or
as a port in watch mode, disable the output of the peripheral resource, then set
the TMD bit to "0".Listed below are applicable ports.
This applies to the following pins:P14/PPG0, P15/PPG1, P16/PPG2, P17/PPG3,
P21/TOT0, P23/TOT1
• There is no sub-clock in MB90F897S.
139
CHAPTER 3 CPU
■ Return from Watch Mode
The watch mode is cancelled by a reset factor or when an interrupt is generated.
● Return by reset factor
When the watch mode is cancelled by a reset factor, the mode transits to the main clock mode after the
watch mode is cancelled, transiting to the reset sequence.
Notes:
• To return from watch mode to main clock mode using the external reset pin (RST
pin), input the Low level for at least oscillator’s oscillation time* + 100 μs + 16
machine cycles (main clock).
*: The oscillation time for the oscillator is the period of time taken until its
amplitude reaches 90%.It takes several to dozens of ms for crystal oscillators,
hundreds of μs to several ms for ceramic oscillators, and 0 ms for external
clocks.
• There is no sub-clock in MB90F897S.
● Return by interrupt
When an interrupt request higher than the interrupt level (IL) of 7 is generated from the watch timer and
external interrupt in the watch mode, the watch mode is cancelled. After the watch mode is cancelled, as
with normal interrupt processing, the generated interrupt request is identified according to the settings of
the I flag in the condition code register (CCR), the interrupt level mask register (ILM), and the interrupt
control register (ICR). In the sub-timer mode, no oscillation stabilization wait time is generated and the
interrupt request is identified immediately after return from the watch mode.
• When the CPU is not ready to accept any interrupt request, the next instruction to the currently
executing instruction is executed.
• When the CPU is ready to accept any interrupt request, it branches immediately to the interrupt
processing routine.
Notes:
• When handling an interrupt, the CPU usually services the interrupt after
executing the instruction that follows the one specifying the watch mode.
• There is no sub-clock in MB90F897S.
140
CHAPTER 3 CPU
3.8.5.3
Timebase Timer Mode
The timebase timer mode operates only the oscillation clock (HCLK), sub clock (SCLK),
timebase timer, and watch timer. Peripherals other than the timebase timer and watch
timer stop.
■ Timebase Timer Mode
The mode transits to the timebase timer mode when 0 is written to the TMD bit of the low-power
consumption mode control register (LPMCR) during operation in the PLL clock mode or the main clock
mode (CKSCR: SCM = 1).
● Data retention function
In the timebase timer mode, data in the dedicated registers such as an accumulator and internal RAM are
held.
● Operation when interrupt request generated
When an interrupt request is generated with the TMD bit of the low-power consumption mode control
register (LPMCR) set to "0", the mode does not transit to the timebase timer mode.If the CPU is not ready
to accept any interrupt request, the instruction next to the currently executing instruction is executed.If the
CPU is ready to accept any interrupt request, an interrupt operation immediately branches to the interrupt
processing routine.
● Pin state
In the timebase timer mode, the input/output pins can be set to the high-impedance state or held in the state
before transiting to the timebase timer mode according to the setting of the SPL bit in the low-power
consumption mode control register (LPMCR).
Note:
To set that pin to high impedance which serves either for a peripheral resource or as
a port in timebase timer mode, disable the output of the peripheral resource, then set
the TMD bit to "0".Listed below are applicable ports.This applies to the following pins:
P14/PPG0, P15/PPG1, P16/PPG2, P17/PPG3, P21/TOT0, P23/TOT1
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CHAPTER 3 CPU
■ Return from Timebase Timer Mode
The timebase timer mode is cancelled by a reset factor or when an interrupt is generated.
● Return by reset factor
When the timebase timer mode is cancelled by a reset factor, the mode transits to the main clock mode after
the timebase timer mode is cancelled, transiting to the reset sequence.
Note:
To return from timebase timer mode to main clock mode using the external reset pin (RST pin), input the
Low level for at least 100 μs.
● Return by interrupt
When an interrupt request higher than interrupt level (IL) 7 is generated from the watch timer, timebase
timer, and external interrupt in the timebase timer mode, the timebase timer mode is cancelled.After the
timebase timer mode is cancelled, as with normal interrupt processing, the generated interrupt request is
identified according to the settings of the I flag in the condition code register (CCR), the interrupt level
mask register (ILM), and the interrupt control register (ICR).
• When the CPU is not ready to accept any interrupt request, the nest instruction to the currently
executing instruction is executed.
• When the CPU is ready to accept any interrupt request, it branches immediately to the interrupt
processing routine.
• The following two timebase timer modes are available:
- Main clock ←→ timebase timer mode
- PLL clock ←→
Notes:
timebase timer mode
• When handling an interrupt, the CPU usually services the interrupt after
executing the instruction that follows the one specifying the timebase timer mode.
• When the CPU returns from the timebase timer mode in response to an interrupt,
the CPU services the interrupt a maximum of 80 μs after accepting the interrupt
request.
142
CHAPTER 3 CPU
3.8.5.4
Stop Mode
The stop mode stops the oscillation clock (HCLK) and sub clock (SCLK) during
operation in each clock mode.It enables data to be retained with the least power
consumption.
■ Stop Mode
When 1 is written to the STP bit of the low-power consumption mode control register (LPMCR) during
operation in the PLL clock mode, the mode transits to the stop mode according to the settings of the MCS
bit and SCS bit in the clock select register (CKSCR).
Table 3.8-5 shows the settings of the MCS and SCS bits in the clock select register (CKSCR) and the stop
modes.
Table 3.8-5 Clock select register (CKSCR) settings and stop modes
Clock select register (CKSCR)
Stop Mode to be Transited
MCS
SCS
1
1
Main stop mode
0
1
PLL stop mode
1
0
0
0
Sub-stop mode
Notes:
• If both the STP and SLP bits in the low-power consumption mode control register
(LPMCR) are set to "1" simultaneously, the STP bit is preferred and the mode
transits to the stop mode.
• There is no sub-clock in MB90F897S.
● Data retention function
In the stop mode, data in the dedicated registers such as accumulators and internal RAM are held.
● Operation when interrupt request generated
When an interrupt request is generated with the STP bit in the low-power consumption mode control
register (LPMCR) set to "1", the mode does not transit to the stop mode.If the CPU is not ready to accept
any interrupt request, the next instruction to the currently executing instruction is executed.If the CPU is
ready to accept any interrupt request, an interrupt operation immediately branches to the interrupt
processing routine.
● Pin state
In the stop mode, the input/output pins can be set to the high-impedance state or held in the state before
transiting to the stop mode according to the setting of the SPL bit in the low-power consumption mode
control register (LPMCR).
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CHAPTER 3 CPU
Note:
To set that pin to high impedance which serves either as a peripheral resource or as
a port in stop mode, disable the output of the peripheral resource, then set the STP
bit of to "1".Listed below are applicable ports.
This applies to the following pins: P14/PPG0, P15/PPG1, P16/PPG2, P17/PPG3,
P21/TOT0, P23/TOT1
■ Return from Stop Mode
The stop mode is cancelled by a reset factor or when an interrupt is generated.At return from the stop mode,
the oscillation clock (HCLK) stops and the sub clock (SCLK), so the stop mode is cancelled after the elapse
of the main clock oscillation stabilization wait time or the sub clock oscillation stabilization wait time.
● Return by reset factor
When the stop mode is cancelled by a reset factor, the main clock oscillation stabilization wait time is
generated.After the termination of the main clock oscillation stabilization wait time, the stop mode is
cancelled, transiting to the reset sequence.
Figure 3.8-7 shows the return from the sub-stop mode by an external reset.
Figure 3.8-7 Return from the Sub-stop Mode by an External Reset
RST pin
Stop mode
Main clock
Oscillation stabilization wait
During oscillation
Subclock
Oscillation stabilization wait
During oscillation
Oscillation
stabilization wait
PLL clock
CPU operation clock
CPU clock
Subclock
During stop
Reset sequence
Main clock
During oscillation
PLL clock
Normal process
Cancellation of stop mode
Cancellation of reset
Notes:
• To return from stop mode to main clock mode using the external reset pin (RST
pin), input the Low level for at least oscillator’s oscillation time* + 100 μs + 16
machine cycles (main clock).
*: The oscillation time for the oscillator is the period of time taken until its
amplitude reaches 90%.
It takes several to dozens of ms for crystal oscillators, hundreds of μs to
several ms for ceramic oscillators, and 0 ms for external clocks.
• There is no sub-clock in MB90F897S.
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CHAPTER 3 CPU
● Return by interrupt
When an interrupt request higher than the interrupt level (IL) of 7 is generated from external interrupt in the
stop mode, the stop mode is cancelled.In the stop mode, the main clock oscillation stabilization wait time or
the sub clock oscillation stabilization wait time is generated after the stop mode is cancelled. After the stop
mode is cancelled, as with normal interrupt processing, the generated interrupt request is identified
according to the settings of the I flag in the condition code register (CCR), the interrupt level mask register
(ILM), and the interrupt control register (ICR).
• When the CPU is not ready to accept any interrupt request, the instruction next to the currently
executing instruction is executed.
• When the CPU is ready to accept any interrupt request, it branches immediately to the interrupt
processing routine.
Note:
When handling an interrupt, the CPU usually services the interrupt after executing
the instruction that follows the one specifying the stop mode.
In PLL stop mode, the main clock and PLL multiplier circuit remain stopped. When
the CPU returns from PLL stop mode, therefore, it is necessary to allow for the main
clock oscillation stabilization wait time and PLL clock oscillation stabilization wait
time to be held. In this case, the oscillation stabilization wait times for the main clock
and PLL clock are counted simultaneously according to the value specified in the
oscillation stabilization wait time select bits (CKSCR: WS1, WS0) in the clock select
register. The CKSCR: WS1/WS0 bits must therefore be set to a value according to
the main clock or PLL clock oscillation stabilization wait time, whichever is longer.
The PLL clock requires an oscillation stabilization wait time of at least 214/HCLK. Set
the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock
selection register to "10B" or "11B".
145
CHAPTER 3 CPU
3.8.6
State Transition in Standby Mode
The operating state and state transition in the clock mode and standby mode in
MB90895 series are shown in the diagram.
■ State Transition Diagram
Figure 3.8-8 State Transition Diagram
Power-on
External reset, Watchdog timer reset, Software reset
Power-on reset
Reset
SCS=0
SCS=1
Terminate of oscillation
stabilization wait
Main clock mode
MCS=0
SCS=0
PLL clock mode
MCS=1
SLP=1
Interrupt
Main sleep mode
TMD=0
Interrupt
Main
timebase timer
mode
STP=1
Main stop mode
Interrupt
Terminate of oscillation
stabilization wait
Main clock
oscillation stabilization
wait
Notes:
SCS=1
SLP=1
SLP=1
Interrupt
PLL sleep mode
TMD=0
STP=1
PLL stop mode
Interrupt
Terminate of oscillation
stabilization wait
PLL clock
oscillation stabilization
wait
Interrupt
Subsleep mode
Interrupt
PLL timebase timer
mode
TMD=0
Interrupt
Clock mode
STP =1
Substop mode
Interrupt
Terminate of oscillation
stabilization wait
Subclock
oscillation stabilization
wait
• While the clock mode is being switched, do not switch the CPU to any other clock
mode or to low power consumption mode until the current process of mode
switching is completed.Check the MCM and SCM bits in the clock select register
(CKSCR) to make sure that the transition to the new clock mode has been
completed. If the mode is switched to another clock mode or low power
consumption mode before completion of switching, the mode may not be
switched.
• There is no sub-clock in MB90F897S.
146
Subclock mode
CHAPTER 3 CPU
3.8.7
Pin State in Standby Mode, at Reset
The state of input/output pins in the standby mode and at reset is shown in each access
mode.
■ State of Input/Output Pins (Single-chip Mode)
Table 3.8-6 State of Input/Output Pins (Single-chip Mode)
At stop/clock/timebase timer
Pin Name
At sleep
At a reset
SPL=0
SPL=1
P17 to P10
P27 to P20
P37 to P35, P33 to P30
P44 to P40
Immediatelypreceding state
held*1
Input cut off/
immediatelypreceding state
held*1
Input cut off/
output Hi-Z*2
Input disabled/output
Hi-Z
P57 to P50
*1: Indicates that either the output pins output their state as it is immediately before entering each standby mode or the
input pins are input-disabled. Output of the output state as it is means that when the resource with an output is in
operation, the state of pins is output according to the state of the resource and, when the state of output pins is output,
it is held.Input disabled means that no pin value can be accepted internally because the internal circuit is off while the
operation of the input gates of pins is enabled.
*2: In the input cut off state, the input is masked and "L" level is transmitted internally. Output Hi-Z means that the
driving of pin driving transistors is disabled to place the pins in a high impedance state.
Note:
To set that pin to high impedance which serves either for a peripheral resource or as
a port in stop mode, watch mode, or timebase timer mode, disable the output of the
peripheral resource, then set the STP bit to "1" or set the TMD bit to "0".Listed below
are applicable ports.
This applies to the following pins: P14/PPG0, P15/PPG1, P16/PPG2, P17/PPG3,
P21/TOT0, P23/TOT1
147
CHAPTER 3 CPU
3.8.8
Precautions when Using Low-power Consumption Mode
This section explains the precautions when using the low-power consumption modes.
■ Transition to Standby Mode
When an interrupt request is generated from the resource to the CPU, the mode does not transit to each
standby mode even after setting the STP and SLP bits in the low-power consumption mode control register
(LPMCR) to 1 and the TMD bit to 0 (and also even after interrupt processing).
If the CPU is servicing an interrupt, the interrupt-service-time interrupt request flag is cleared and the CPU
can enter the standby mode unless any other interrupt request has been generated.
■ Cancellation of Standby Mode by Interrupt
When an interrupt request higher than the interrupt level (IL) of 7 is generated from the resource and
external interrupt during operation in the sleep mode, watch mode, timebase timer mode, or stop mode, the
standby mode is cancelled.The standby mode is cancelled by an interrupt regardless of whether the CPU
accept interrupts or not.
Notes:
• To prevent the CPU from causing a branch to interrupt servicing immediately
after returning from standby mode, take measures, such as disabling interrupts
before setting the standby mode.
• There is no sub-clock in MB90F897S.
■ Notes on the Transition to Standby Mode
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode,
watch mode, or timebase timer mode, use the following procedure:
1. Disable the output of peripheral functions.
2. Set the SPL bit to "1", STP bit to "1", or TMD bit to "0" in the low-power mode control register
(LPMCR).
Note:
There is no sub-clock in MB90F897S.
■ Note on Canceling Standby Mode
The standby mode can be cancelled by an input according to the settings of an input factor of an external
interrupt.The input factor can be selected from High level, Low level, rising edge, and falling edge.
■ Oscillation Stabilization Wait Time
● Oscillation stabilization wait time of main clock
In the sub clock mode, watch mode, or stop mode, the oscillation of the main clock stops and the oscillation
stabilization wait time of the main clock is required.The oscillation stabilization wait time of the main clock
is set by the WS1 and WS0 bits in the clock select register (CKSCR).
148
CHAPTER 3 CPU
● Oscillation stabilization wait time of sub clock
In the sub-stop mode, the oscillation of the sub clock stops and the oscillation stabilization wait time of the
sub clock is required.The oscillation stabilization wait time of the sub clock is fixed at 214/SCLK (SCLK:
sub clock).
● Oscillation stabilization wait time of PLL clock
In main clock mode, the PLL multiplier circuit remains stopped. When the CPU enters the PLL clock
mode, therefore, it is necessary to allow for the PLL clock oscillation stabilization wait time.The CPU runs
in main clock mode till the PLL clock oscillation stabilization wait time has elapsed.The PLL clock
oscillation stabilization wait time taken when the clock mode is switched from main clock to PLL clock is
fixed at 214/HCLK (HCLK: oscillation clock).
In subclock mode, the main clock and PLL multiplier circuit remain stopped. When the CPU enters the
PLL clock mode, therefore, it is necessary to allow for the main clock oscillation stabilization wait time and
PLL clock oscillation stabilization wait time. In this case, the oscillation stabilization wait times for the
main clock and PLL clock are counted simultaneously according to the value specified in the oscillation
stabilization wait time select bits (CKSCR: WS1, WS0) in the clock select register. The CKSCR: WS1/
WS0 bits must therefore be set to a value according to the main clock or PLL clock oscillation stabilization
wait time, whichever is longer. The PLL clock requires an oscillation stabilization wait time of at least 214/
HCLK. For switching to PLL clock mode, therefore, set the CKSCR: WS1 and WS0 bits to "10B" or "11B".
In PLL stop mode, the main clock and PLL multiplier circuit remain stopped. When the CPU returns from
PLL stop mode, therefore, it is necessary to allow for the main clock oscillation stabilization wait time and
PLL clock oscillation stabilization wait time. In this case, the oscillation stabilization wait times for the
main clock and PLL clock are counted simultaneously according to the value specified in the oscillation
stabilization wait time select bits (CKSCR: WS1, WS0) in the clock select register. The CKSCR: WS1/
WS0 bits must therefore be set to a value according to the main clock or PLL clock oscillation stabilization
wait time, whichever is longer. The PLL clock requires an oscillation stabilization wait time of at least 214/
HCLK. Set the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection
register to "10B" or "11B".
■ Transition of Clock Mode
While the clock mode is being switched, do not switch the CPU to low power consumption mode or to any
other clock mode until the current process of mode switching is completed.Check the MCM and SCM bits
in the clock select register (CKSCR) to make sure that the transition to the new clock mode has been
completed. If the mode is switched to another clock mode or low power consumption mode before
completion of switching, the mode may not be switched.
Note:
There is no sub-clock in MB90F897S.
149
CHAPTER 3 CPU
■ Notes on Accessing the Low-Power Consumption Made Control Register (LPMCR) to Enter the Standby
Mode
● To access the low-power consumption mode control register (LPMCR) with assembler language
• To set the low power consumption mode control register (LPMCR) to enter the standby mode, use the
instruction listed in Table 3.8-2.
• The standby mode transition instruction in Table 3.8-2 must always be followed by an array of
instructions highlighted by a line below.
MOV LPMCR,#H’xx
; The low-power consumption mode transition instruction in Table 3.8-2
NOP
NOP
JMP $+3
; Jump to the next instruction
MOV A,#H’10
; Arbitrary instruction
The devices does not guarantee its operation after returning from the standby mode if you place an array of
instructions other than the one enclosed in the line,
● To access the low-power consumption mode (LPMCR) with C language
To enter the standby mode using the low power consumption mode control register (LPMCR), use one of
the following methods (1) to (3) to access the register:
(1) Specify the standby mode transition instruction as a function and insert two __wait_nop() built-in
functions after that instruction.If any interrupt other than the interrupt to return from the standby mode
can occur within the function, optimize the function during compilation to suppress the LINK and
UNLINK instructions from occurring.
Example: Watch mode or timebase timer mode transition function
void enter_watch(){
IO_LPMCR.byte = 0x10; /* Set LPMCR TMD bit to 0 */
__wait_nop();
__wait_nop();
}
(2) Define the standby mode transition instruction using __asm statements and insert two NOP and JMP
instructions after that instruction.
Example: Transition to sleep mode
__asm("
__asm("
__asm("
__asm("
150
MOVI;_IO_LPMCR,#H’58); /* Set LPMCR SLP bit to 1 */
NOP");
NOP");
JMP $+3");
/* Jump to the next instruction */
CHAPTER 3 CPU
(3) Define the standby mode transition instruction between #pragma asm and #pragma endasm and insert
two NOP and JMP instructions after that instruction.
Example: Transition to stop mode
#progrma asm
MOVI;_IO_LPMCR,#H’58); /* Set LPMCR SLP bit to 1 */
NOP
NOP
JMP $+3"
/* Jump to the next instruction */
#progrma endasm
151
CHAPTER 3 CPU
3.9
CPU Mode
The F2MC-16XL family can set the CPU operation and the access method and area by
switching the operation mode and access mode.
■ Classification of Modes
Table 3.9-1shows the classification of operation modes and memory access modes for the F2MC-16XL
family.Each mode is set by mode pins (MD2 to MD0) in reset and mode- fetched mode data.
Table 3.9-1 Classification of Modes
Operating mode
Memory Access Mode
Bus Modes
RUN modes
Single-chip mode
(Internal-ROM internal-bus mode)
Flash serial programming mode
−
Flash memory mode
−
■ Operating mode
The operation modes control the operating state of the device and are set by the mode pins (MD2 to MD0).
● RUN modes
The RUN mode is the normal CPU operation mode.It provides various low-power consumption modes,
such as the main clock mode, PLL clock mode, and sub clock mode.
Reference:
For details on the low power consumption modes, see 3.8 "Low-power Consumption
Mode".
● Flash serial programming mode and flash memory mode
Some products in MB90895 series have user-programmable flash memory.
The flash serial programming mode is that for serially programming data to flash memory.
152
CHAPTER 3 CPU
3.9.1
Mode Pins (MD2 to MD0)
The mode pins are three external pins of MD2 to MD0, and enable a combination of
these pins to set, the following:
• Operation modes (RUN mode, flash serial programming mode, flash memory mode)
• Reading reset vectors and mode data
■ Setting of Mode Pins (MD2 to MD0)
Table 3.9-2 shows the settings of the mode pins.
Table 3.9-2 Setting of Mode Pins
Mode Pin*
Mode Name
MD2
MD1
MD0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
Flash serial programming mode
1
1
1
Flash memory mode
Setting disabled
Internal vector mode
Setting disabled
*:Set MD2 to MD0: 0 = V SS or 1 = V CC.
● Internal vector mode
Reset vectors are read from internal ROM.
● Flash serial programming mode
Flash serial programming cannot be performed just by the settings of the mode pins.
Reference:
For details on flash serial programming, see "CHAPTER 20 DUAL OPERATION
FLASH".
● Flash memory mode
This mode is set when using a parallel writer.
■ Setting of Mode Pins
Set the mode pins as shown in Figure 3.9-1.
153
CHAPTER 3 CPU
Figure 3.9-1 Flow of Mode Pin Setting
Setting the pin mode
Flash memory
programing
NO
YES
Flash programing
mode
Internal vector
mode
MD2 MD1 MD0 MD2 MD1 MD0
"1" "1" "1"
"0" "1" "1"
MD2 to MD0: Set to 0=Vss, 1=Vcc. And also, do not set to other than above description.
154
CHAPTER 3 CPU
3.9.2
Mode Data
Mode data is used to set the memory access mode.It is automatically read to the CPU
by mode fetch.
■ Mode Data
The values of the mode register can be changed only in the reset sequence.The changed mode register
values are enabled after the reset sequence.
Figure 3.9-2 Mode Data
7
6
5
4
3
2
1
0
R/W R/W R/W R/W R/W R/W R/W R/W
bit0 bit1 bit2 bit3 bit4 bit5
Reserved bit
Reserved
0
R/W : Read/Write
X
: Undefined
: Reset value
Be sure to set this bit to 0.
bit7
bit6
M1
0
0
1
1
M0
0
1
0
1
Bus mode setting bit
Single chip mode
Setting prohibited
Table 3.9-3 function of mode register
bit name
Function
bit7,
bit6
M1, M0:
Bus modes setting bit
Always set this bit to "00B".
bit5
to
bit0
Reserved: reserved bit
Be sure to write "0".
155
CHAPTER 3 CPU
■ Setting Mode Data
Set the mode data as shown in Figure 3.9-3.
Figure 3.9-3 Flow of Mode Data Setting
Setting of mode data
Single chip
mode
Single chip
mode
Mode data 00H
Do not set mode data other than above value.
156
CHAPTER 3 CPU
3.9.3
Memory Access Mode
There are two modes in the memory access mode: bus mode and external access
mode.
• Bus mode: Sets access area (internal)
■ Bus Modes
Figure 3.9-4 shows the memory map in the mode.
Figure 3.9-4 Memory map in the mode
When ROM mirror is enabled
000000H
Peripheral
0000C0H
000100H
RAM area
Register
Address #1
003900H
Extended I/O area
004000H
ROM area
(imge of
FF Bank)
010000H
FE0000H
ROM area
*
FF0000H
ROM area
FFFE00H
FFFFFFH
Hardwired reset vectors
: Internal access memory
: Access prohibited
*: In MB90F897/S, if read the FE0000H to FEFFFFH area,
can be read the data of FF0000H to FFFFFFH.
Reference:
For details on access areas, see 3.1 "Memory Space".
● Single-chip mode (internal-ROM internal-access)
• Only internal ROM and internal RAM are used and no external access occurs.
• Ports 1 to 3 can be used as general-purpose I/O ports.
157
CHAPTER 3 CPU
3.9.4
Operations for Selecting Memory Access Mode
This section explains selection of the memory access mode in the reset sequence.
■ Operations for Selecting Memory Access Mode
After reset is cancelled, the CPU selects the memory access mode according to the procedure shown in
Figure 3.9-5 by referencing the settings of the mode pins and mode data.
Figure 3.9-5 Operations for Selecting Memory Access Mode
Generate the reset factor
Setting of mode pin
(MD2,1,0)?
Check the mode pin
Internal data read to
internal ROM.
All I/O pins are
High-Z.
Reset factor cancellation wait
(external reset or
oscillation stabilization time)
During reset
operation?
NO
Mode fetched
Fetch the mode data and reset
vectors from internal ROM
(M1,M0=00B)
M1 and M0 bit
of mode data
Check the mode data
Setting the single
chip mode
158
YES
CHAPTER 4
I/O PORT
This chapter describes the function and operation of the
I/O port.
4.1 Overview of I/O Ports
4.2 Registers of I/O Port and Assignment of Pins Serving as External
Bus
4.3 Port 1
4.4 Port2
4.5 Port 3
4.6 Port 4
4.7 Port 5
4.8 Port input level select register
159
CHAPTER 4 I/O PORT
4.1
Overview of I/O Ports
I/O ports can be used as general-purpose I/O ports (parallel I/O ports). In MB90895
series, there are five ports (34 pins).
Each port pin also serves as a peripheral I/O pins.
■ I/O Port Function
The I/O ports enable the port data register (PDR) to output data to the I/O pins from the CPU and fetch
signals input to the I/O pins.These also enable the port direction register (DDR) to set a direction for the I/
O pins by bit.
The following shows the function of each port, and the peripherals that it also serves as:
• Port 1: Serves as both general-purpose I/O port and PPG timer output, or input capture input
• Port 2: Serves as both general-purpose I/O port and reload timer I/O, or external interrupt input
• Port 3: Serves as both general-purpose I/O port or A/D converter start trigger pin
• Port 4: Serves as both general-purpose I/O port and UART1 I/O or CAN controller transmit/receive pin
• Port 5: Serves as both general-purpose I/O port and analog input pin
Table 4.1-1 List of Each Port Functions
Port Name
port 1
port 2
port 3
Pin Name
Input Type
P10/IN0 to
P13/IN3
Output Type
CMOS
P14/PPG0 to
P17/PPG3
P20/TIN0 to
P27/INT7
P30/SOT0 to
P33, P35/X0A
to P37/ADTG
CMOS high
current
Port 5
Resource
General-purpose
I/O ports
Analog/CMOS
(hysteresis)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
P17
P16
P15
P14
P13
P12
P11
P10
PPG3
PPG2
PPG1
PPG0
IN3
IN2
IN1
IN0
P27
P26
P25
P24
P23
P22
P21
P20
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
−
P33
P32
P31
P30
P37
P36*2/X1A P35*2/X0A
ADTG
−
−
−
−
SIN0
SCK0
SOT0
General-purpose
I/O ports
−
−
−
P44
P43
P42
P41
P40
Resource
Resource
P40/SIN1 to
P44/RX
P50/AN0 to
P57/AN7
Resource
General-purpose
I/O ports
CMOS
(hysteresis)
/Automotive
/CMOS*1
CMOS
Port 4
Function
General-purpose
I/O ports
−
−
−
RX
TX
SOT1
SCK1
SIN1
General-purpose
I/O ports
P57
P56
P55
P54
P53
P52
P51
P50
Analog input pin
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
*1:Only P32/SIN, P40/SIN1
*2:If the low-speed oscillation pin is selected (for MB90F897), P35 and P36 pins cannot be used.
Note:
160
When using these ports as general-purpose ports, always set each bit of the analog
input enable register (ADER) corresponding to each pin of the ports to "0".ADER bit
is "1" at a reset.
CHAPTER 4 I/O PORT
4.2
Registers of I/O Port and Assignment of Pins Serving as
External Bus
The registers related to I/O port setting are listed as follows.
■ Registers of I/O Ports
Table 4.2-1 shows the register list of each port.
Table 4.2-1 Registers of Each Port
Register Name
Read/Write
Address
Reset Value
Port 1 data register (PDR1)
R/W
000001H
XXXXXXXXB
Port 2 data register (PDR2)
R/W
000002H
XXXXXXXXB
Port 3 data register (PDR3)
R/W
000003H
XXXXXXXXB
Port 4 data register (PDR4)
R/W
000004H
XXXXXXXXB
Port 5 data register (PDR5)
R/W
000005H
XXXXXXXXB
Port 1 direction register (DDR1)
R/W
000011H
00000000B
Port 2 direction register (DDR2)
R/W
000012H
00000000B
Port 3 direction register (DDR3)
R/W
000013H
000X0000B
Port 4 direction register (DDR4)
R/W
000014H
XXX00000B
Port 5 direction register (DDR5)
R/W
000015H
00000000B
Analog input enable register (ADER)
R/W
00001BH
11111111B
R/W: Read/Write
X: Undefined
161
CHAPTER 4 I/O PORT
4.3
Port 1
Port 1 is a general-purpose I/O port that also serves as a peripheral resource I/O pin.
When the single-chip mode is set, use port 1 by switching between the resource pin and
the general-purpose I/O port.
The configuration, pin assignment, block diagram of the pins, and registers for port 1
are shown below.
■ Configuration of Port 1
Port 1 consists of the following three elements:
• General-purpose I/O port, resource I/O pin (P10/IN0 to P17/PPG3)
• Port 1 data register (PDR1)
• Port 1 direction register (DDR1)
■ Pin Assignment of Port 1
• When the single-chip mode is set, use the port by switching between the peripheral pin and the generalpurpose I/O port.
• Since the port serves as a resource pin, it cannot be used as a general-purpose I/O port when used as a
peripheral.
• When using port 1 as the input pin of the peripheral, set the pin corresponding to the resource in the
DDR1 as an input port.
• When using the port as the output of the resource, set the output of the corresponding resource to
enabled.Port 1 functions as the output pin of the resource regardless of the settings of the DDR1.
Table 4.3-1 shows pin assignment of port 1.
Table 4.3-1 Pin Assignment of Port 1
I/O Type
Port
Name
Pin Name
Port Function
Input
P10/IN0
P10
IN0
P11/IN1
P11
IN1
P12/IN2
P12
IN2
P13/IN3
P13
P14/PPG0
P14
P15/PPG1
P15
PPG1
P16/PPG2
P16
PPG2
P17/PPG3
P17
PPG3
port 1
Reference:
162
Resource
Generalpurpose I/O
input capture
input
Output
Circuit
Type
CMOS
D
CMOS
high current
G
CMOS
(hysteresis)
CMOS/
Automotive
IN3
PPG0
PPG timer
output
For the circuit type, see "Section 1.7 I/O Circuit".
CHAPTER 4 I/O PORT
■ Block Diagram of Port-1 Pins (in Single Chip Mode)
Figure 4.3-1 Block Diagram of Pins of Port 1
Resource input
Resource output
Port data register (PDR)
Resource output
acceptance
Internal data bus
PDR read
P-ch
Output latch
PDR write
Pin
Port direction register (DDR)
N-ch
Direction latch
DDR write
Standby control (SPL=1)
DDR read
Standby control : Control of stop mode (SPL=1), timebase timer mode (SPL=1) and clock mode (SPL=1)
■ Block Diagram of Port 1 Pins
• Registers for Port 1 (in Single Chip Mode)
• The bits composing each register correspond to the pins of port 1 one-to-one.
Table 4.3-2 shows the correspondence between the registers and pins of port 1.
Table 4.3-2 The correspondence between the registers and pins of port 1
Port Name
Bits of Related Registers and Corresponding Pins
PDR1, DDR1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P17
P16
P15
P14
P13
P12
P11
P10
port 1
163
CHAPTER 4 I/O PORT
4.3.1
Registers for Port 1 (PDR1, DDR1)
The registers for port 1 are explained.
■ Function of Registers for Port 1 (in Single Chip Mode)
● Port 1 data register (PDR1)
• Port 1 data register indicates the state of the pins.
● Port 1 direction register (DDR1)
• The port 1 direction register sets the input/output directions.
• When the bit corresponding to the pin is set to "1", port 1 functions as an output port. When the bit is set
to "0", port "1" functions as an input port.
Table 4.3-3 shows function of the registers for port 1.
Table 4.3-3 Functions of the Registers for Port 1
Register
Name
Data
At Read
The pin state is
Low level.
"0" is set for the output
latch, and when the pin is
an output port pin, the Low
level is output to the pin.
1
The pin state is
High level.
"1" is set for the output
latch, and when the pin is
an output port pin, the High
level is output to the pin.
0
The direction
latch is "0".
The output buffer is set to
"OFF", and the pin
becomes an input port pin.
The direction
latch is "1".
The output buffer is set to
"ON", and the pin becomes
an output port pin
0
Port 1 data
register
(PDR1)
Port 1
direction
register
(DDR1)
At Write
1
Read/
Write
Register
Address
Reset Value
R/W
000001H
XXXXXXXXB
R/W
000011H
00000000B
R/W: Read/Write
X: Undefined
References:
164
• When using port 1 as the input pin of the resource, clear the bit in the DDR1
corresponding to the input pin of the resource to 0 and set the input pin as an input
port.
• When using port 1 as the output pin of the resource, set the output of the
corresponding resource to enabled.Port 1 functions as the output pin of the
resource regardless of the settings of the DDR1.
CHAPTER 4 I/O PORT
4.3.2
Operation of Port 1
The operation of port 1 is explained.
■ Operation of Port 1 (in Single Chip Mode)
● Operation of output port
• When the bit in the port 1 direction register (DDR1) corresponding to the output pin is set to "1", port 0
functions as an output port.
• When the output buffer is turned "ON" and output data is written to the port 1 data register (PDR1), the
data is retained in the output latch and output from the pin.
• When the PDR1 is read, the state of the output latch in the PDR1 is read.
Note:
If read modify write instructions (such as the bit set instruction) are used to read the
PDR, the pin set as an output port by the DDR outputs the desired data. To switch a
pin from input port to output port, write output data to the port data register and use
the port direction register to set the pin as an output port.
● Operation of input port
• If the bit in the DDR corresponding to the input pin is set to "0", port 1 functions as an input port.
• The output buffer is turned "OFF" and the pin enters the high impedance state.
• When data is written to the PDR1, it is retained in the output latch in the PDR1 but not output to the pin.
• When the PDR1 is read, the level value (Low or High) of the pin is read.
● Operation of resource output
• When using the port as the output pin of the resource, set the resource output to enabled.
• Since the resource output is preferred enabled, the resource output functions regardless of the settings of
the DDR1.
• When the pin state is read with the resource output set to enabled, the output state of the resource is
read.
● Operation of resource input
• The state of the pin that serves as the resource input is input to the resource.
• When using port 1 as the input pin of the resource, clear the bit in the DDR1 corresponding to the input
pin of the resource to 0 and set the input pin as an input port.
● Operation at reset
• When the CPU is reset, the value of the DDR1 is cleared to "0".Consequently, all output buffers are set
to "OFF" (the pin becomes an input port pin), and the pin enters the high-impedance state.
• The PDR1 is not initialized by reset. Therefore, when using port 1 as an output port, it is necessary to set
output data in the PDR1, and then set the bit in the DDR1 corresponding to the output pin to 1, and then,
to output.
165
CHAPTER 4 I/O PORT
● Operation in stop mode, timebase timer mode or watch mode
• When the pin state specification bit of the low power consumption mode control register (LPMCR:
SPL) is "1", at a transition to the stop mode, timebase timer mode or watch mode, the pin enters the
high- impedance state. The output buffer is set forcibly to "OFF" irrespective of the value of the DDR1.
Table 4.3-4 shows state of port 1 pins.
Table 4.3-4 State of Port 1 Pins
Pin Name
Normal
Operation
Sleep mode
Stop Mode,
Timebase Timer Mode or Watch Mode
SPL=0
P10/IN0 to
P17/PPG3
Generalpurpose I/O
ports
Generalpurpose I/O
ports
General-purpose I/O
ports
SPL=1
Input cut off, and
output becomes Hi-Z
(Pull-up resistor
disconnected)
SPL: Pin state specification bit of low power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
Note:
166
To set that pin to high impedance which serves either as a peripheral resource or as
a port in stop mode, watch mode, or timebase timer mode, disable the output of the
peripheral resource, then set the STP bit to "1" or set the TMD bit to "0".Listed below
are applicable ports.
This applies to the following pins: P14/PPG0, P15/PPG1, P16/PPG2, P17/PPG3
CHAPTER 4 I/O PORT
4.4
Port2
Port 2 is a general-purpose I/O port that also serves as a peripheral resource I/O pin.
Use port 2 by switching between the resource pin and the general-purpose I/O port.
The configuration, pin assignment, block diagram of the pins, and registers for port 2
are shown below.
■ Configuration of Port 2
Port 2 consists of the following four elements:
• General-purpose I/O port, resource I/O pin (P20/TIN0 to P27/INT7)
• Port 2 data register (PDR2)
• Port 2 direction register (DDR2)
• High address control register (HACR)
■ Pin Assignment of Port 2
• The pin is used either a resource pin or a general-purpose I/O pin
• Since the port serves as resource pin, when used as a resource pin the port cannot be used as generalpurpose I/O port.
• When using port 2 as the input pin of the resource, set the pin corresponding to the resource in the
DDR2 as an input port.
• When using the port as the output of the resource, set the output of the corresponding resource to
enabled.Port 2 functions as the output pin of the resource regardless of the settings of the DDR2.
167
CHAPTER 4 I/O PORT
Table 4.4-1 shows pin assignment of port 2.
Table 4.4-1 Pin Assignment of Port 2
Port
Name
Pin
Name
I/O Type
Port Function
P20/
TIN0
P20
TIN0
16-bit reload
timer 0 input
P21/
TOT0
P21
TOT0
16-pit reload
timer 0 output
P22/
TIN1
P22
TIN1
16-bit reload
timer 1 input
P23/
TOT1
P23
TOT1
16-bit reload
timer 1 output
Generalpurpose I/O
port 2
Reference:
168
Resource
P24/
INT4
P24
INT4
P25/
INT5
P25
INT5
P26/
INT6
P26
INT6
P27/
INT7
P27
INT7
External
interrupt input
For the circuit type, see Section "1.7 I/O Circuit".
Input
Output
CMOS
CMOS
(hysteresis)/
Automotive
CMOS
Circuit
Type
D
CHAPTER 4 I/O PORT
■ Block Diagram of Pins of Port 2 (General-purpose I/O Port)
Figure 4.4-1 Block Diagram of Pins of Port 2
Resource input
Resource output
Port data register (PDR)
Resource output
acceptance
Internal data bus
PDR read
P-ch
Output latch
PDR write
Pin
Port direction register (DDR)
N-ch
Direction latch
DDR write
Standby control (SPL=1)
DDR read
Standby control : Control of stop mode (SPL=1), timebase timer mode (SPL=1) and clock mode (SPL=1)
■ Registers for Port 2
• The registers for port 2 are PDR2 and DDR2.
• The bits composing each register correspond to the pins of port 2 one-to-one.
Table 4.4-2 shows the correspondence between the registers and pins of port 2
Table 4.4-2 The correspondence between the registers and pins of port 2.
Port Name
Bits of Related Registers and Corresponding Pins
PDR2, DDR2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P27
P26
P25
P24
P23
P22
P21
P20
port 2
169
CHAPTER 4 I/O PORT
4.4.1
Registers for Port 2 (PDR2, DDR2)
The registers for port 2 are explained.
■ Function of Registers for Port 2
● Port 2 data register (PDR2)
Port 2 data register indicates the input/output state of the pins.
● Port 2 direction register (DDR2)
• The port 2 direction register sets the input/output directions.
• When the bit corresponding to the pin is set to "1", port 1 functions as an output port. When the bit is set
to "0", port 1 functions as an input port.
Table 4.4-3 shows functions of the registers for port 2.
Table 4.4-3 Functions of the Registers for Port 2
Register
Name
Data
At Read
The pin state is
Low level.
"0" is set for the output
latch, and when the pin is an
output port pin, the Low
level is output to the pin.
1
The pin state is
High level.
"1" is set for the output
latch, and when the pin is an
output port pin, the High
level is output to the pin.
0
The direction
latch is "0".
The output buffer is set to
"OFF", and the pin becomes
an input port pin.
The direction
latch is "1".
The output buffer is set to
"ON", and the pin becomes
an output port pin
0
Port 2 data
register
(PDR2)
Port 2
direction
register
(DDR2)
At Write
1
Read/
Write
Register
Address
Reset Value
R/W
000002H
XXXXXXXXB
R/W
000012H
00000000B
R/W: Read/Write
X: Undefined
References:
170
• When using port 2 as the input pin of the resource, set the pin corresponding to
the resource in the DDR2 as an input port.
• When using the port as the output of the resource, set the output of the
corresponding resource to enabled.Port 2 functions as the output pin of the
resource regardless of the settings of the DDR2.
CHAPTER 4 I/O PORT
4.4.2
Operation of Port 2
The operation of port 2 is explained.
■ Operation of Port 2 (General-purpose I/O Port)
● Operation of output port
• When the bit in the port 2 direction register (DDR2) corresponding to the output pin is set to "1", port 2
functions as an output port.
• When the output buffer is turned "ON" and output data is written to the port 2 data register (PDR2), the
data is retained in the output latch and output from the pin.
• When the PDR2 is read, the state of the output latch in the PDR2 is read.
Note:
If read modify write instructions (such as the bit set instruction) are used to read the
PDR, the pin set as an output port by the DDR outputs the desired data. To switch a
pin from input port to output port, write output data to the port data register and use
the port direction register to set the pin as an output port.
● Operation of input port
• If the bit in the DDR2 corresponding to the input pin is set to "0", port 2 functions as an input port.
• The output buffer is turned "OFF" and the pin enters the high impedance state.
• When data is written to the PDR2, it is retained in the output latch in the PDR2 but not output to the pin.
• When the PDR2 is read, the level value (Low or High) of the pin is read.
● Operation of resource output
• When using the port as the output pin of the resource, set the resource output to enabled.
• Since the resource output is preferred enabled, the resource output functions regardless of the settings of
the DDR2.
• When the pin state is read with the resource output set to enabled, the output state of the resource is
read.
● Operation of resource input
• The state of the pin that serves as the resource input is input to the resource.
• When using port 2 as the input pin of the resource, set the pin corresponding to the resource in the
DDR2 as an input port.
171
CHAPTER 4 I/O PORT
● Operation at reset
• When the CPU is reset, the value of the DDR2 is initialized to "0".Consequently, all output buffers are
set to "OFF" (the pin becomes an input port pin), and the pin enters the high-impedance state.
• The PDR2 is not initialized by reset. Therefore, when using port 2 as an output port, it is necessary to set
output data in the PDR2, and then set the bit in the DDR2 corresponding to the output pin to 1, and then,
to output.
● Operation in stop mode, timebase timer mode or watch mode
• When the pin state specification bit of the low power consumption mode control register (LPMCR:
SPL) is "1", at a transition to the stop mode, timebase timer mode or watch mode, the pin enters the
high- impedance state.Because the output buffer is set forcibly to "OFF" irrespective of the value of the
DDR2.
Table 4.4-4 shows the state of the port 2 pins.
Table 4.4-4 The state of the port 2 pins
Pin Name
Normal
Operation
Sleep mode
Stop Mode,
Timebase Timer Mode or Watch Mode
SPL=0
P20/TIN0 to
P27/INT7
Generalpurpose I/O
ports
Generalpurpose I/O
ports
General-purpose I/O
ports
SPL=1
Input cut off, and
output becomes Hi-Z
SPL: Pin state specification bit of low power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
Note:
172
To set that pin to high impedance which serves either for a peripheral resource or as
a port in stop mode, watch mode, or timebase timer mode, disable the output of the
peripheral resource, then set the STP bit to 1 or set the TMD bit to 0. Listed below
are applicable ports.
This applies to the following pins: P21/TOT0, P23/TOT1
CHAPTER 4 I/O PORT
4.5
Port 3
Port 3 is a general-purpose I/O port that serves as the resource I/O pin. Use port 3 by
switching between the resource pin and the general-purpose I/O port.
The configuration, pin assignment, block diagram of the pins, and registers for port 3
are shown below.
■ Configuration of Port 3
Port 3 consists of the following three elements:
• General-purpose I/O port, resource I/O pin (P30 to P33, P35*/X0A, P36*/X1A, P37/AD)
• Port 3 data register (PDR3)
• Port 3 direction register (DDR3)
■ Pin Assignment of Port 3
• The pin is used either a resource pin or a general-purpose I/O pin.
• Since the port serves as a resource pin, it cannot be used as a general-purpose I/O port when used as a
resource.
• When using port 4 as the input pin of the resource, set the pin corresponding to the resource in the
DDR4 as an input port.
Table 4.5-1 shows pin assignment of port 3.
Table 4.5-1 Pin Assignment of Port 3
Port
Name
port 3
Pin
Name
I/O Type
Port Function
Resource
Input
P30/
SOT0
P30
SOT0
UART0 serial clock
output
P31/
SCK0
P31
SCK0
UART0 serial clock
I/O
P32/
SIN0
P32
SIN0
UART0 serial data
input
P33
P33
P35/X0A
P35*
P36/X1A
P36*
P37/
ADTG
P37
Generalpurpose
I/O
−
−
−
−
−
ADTG
−
Output
Circu
it
Type
CMOS
CMOS (hysteresis)/
Automotive
CMOS
D
CMOS
CMOS (hysteresis)/
Automotive/CMOS
CMOS
H
D
CMOS
CMOS (hysteresis)/
Automotive
External trigger input
for A/D converter
D/A
CMOS
D/A
D
*:If the low-speed oscillation pin is selected (for MB90F897), P35 and P36 pins cannot be used.
Reference:
For the circuit type, see Section "1.7 I/O Circuit".
173
CHAPTER 4 I/O PORT
■ Block Diagram of Pins of Port 3 (General-purpose I/O Port)
Figure 4.5-1 Block Diagram of Pins of Port 3
Resource input
Resource output
Internal data bus
Port data register (PDR)
Resource output
acceptance
PDR read
P-ch
Output latch
PDR write
Pin
Port direction register (DDR)
N-ch
Direction latch
DDR write
Standby control (SPL=1)
DDR read
Standby control : Control of stop mode (SPL=1), timebase timer mode (SPL=1) and clock mode (SPL=1)
■ Registers for Port 3
• The registers for port 3 are PDR3 and DDR3.
• The bits composing each register correspond to the pins of port 3 one-to-one.
Table 4.5-2 shows the correspondence between registers and pins for port 3.
Table 4.5-2 Correspondence between Registers and Pins for Port 3
Port Name
Bits of Related Registers and Corresponding Pins
PDR3, DDR3
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P37
P36*
P35*
−
P33
P32
P31
P30
port 3
*:MB90F897 has neither P35 nor P36.
174
CHAPTER 4 I/O PORT
4.5.1
Registers for Port 3 (PDR3, DDR3)
The registers for port 3 are explained.
■ Function of Registers for Port 3
● Port 3 data register (PDR3)
• Port 3 data register indicates the state of the pins.
● Port 3 direction register (DDR3)
• The port 3 direction register sets the input/output directions.
• When the bit corresponding to the pin is set to "1", port 1 functions as an output port. When the bit is set
to "0", port 1 functions as an input port.
Table 4.5-3 shows function of the registers for port 3.
Table 4.5-3 Functions of the Registers for Port 3
Register
Name
Data
At Read
The pin state is
Low level.
"0" is set for the output
latch, and when the pin is an
output port pin, the Low
level is output to the pin.
1
The pin state is
High level.
"1" is set for the output
latch, and when the pin is an
output port pin, the High
level is output to the pin.
0
The direction
latch is "0".
The output buffer is set to
"OFF", and the pin becomes
an input port pin.
The direction
latch is "1".
The output buffer is set to
"ON", and the pin becomes
an output port pin
0
Port 3 data
register
(PDR3)
Port 3
direction
register
(DDR3)
At Write
1
Read/
Write
Register
Address
Reset Value
R/W
000003H
XXXXXXXXB
R/W
000013H
000X0000B
R/W: Read/Write
X: Undefined
References:
• When using port 3 as the input pin of the resource, clear the bit in the DDR3
corresponding to the input pin of the resource to 0 and set the input pin as an input
port.
• When using the port as the output of the resource, set the output of the
corresponding resource to enabled. Port 3 functions as the output pin of the
resource regardless of the settings of the DDR3.
175
CHAPTER 4 I/O PORT
4.5.2
Operation of Port 3
The operation of port 3 is explained.
■ Operation of Port 3 (General-purpose I/O Port)
● Operation of output port
• When the bit in the port 3 direction register (DDR3) corresponding to the output pin is set to "1", port 3
functions as an output port.
• When the output buffer is turned "ON" and output data is written to the port 3 data register (PDR3), the
data is retained in the output latch and output from the pin.
• When the PDR3 is read, the state of the output latch in the PDR3 is read.
Note:
If read modify write instructions (such as the bit set instruction) are used to read the
PDR, the pin set as an output port by the DDR outputs the desired data. To switch a
pin from input port to output port, write output data to the port data register and use
the port direction register to set the pin as an output port.
● Operation of input port
• If the bit in the DDR3 corresponding to the input pin is set to "0", port 3 functions as an input port.
• The output buffer is turned "OFF" and the pin enters the high impedance state.
• When data is written to the PDR3, it is retained in the output latch in the PDR3 but not output to the pin.
• When the PDR3 is read, the level value (Low or High) of the pin is read.
● Operation of resource input
• The state of the pin that serves as a resource is input to the resource.
• When using port 3 as the input pin of the resource, clear the bit in the DDR3 corresponding to the input
pin of the resource to "0" and set the input pin as an input port.
● Operation at reset
• When the CPU is reset, the value of the DDR3 is cleared to 0.Consequently, all output buffers are set to
"OFF" (the pin becomes an input port pin), and the pin enters the high-impedance state.
• The PDR3 is not initialized by reset. Therefore, when using port 3 as an output port, it is necessary to set
output data in the PDR3, and then set the bit in the DDR3 corresponding to the output pin to "1" and to
output.
● Operation in stop mode, timebase timer mode or watch mode
• When the pin state specification bit of the low power consumption mode control register (LPMCR:
SPL) is "1", at a transition to the stop mode, timebase timer mode or watch mode, the pin enters the
high- impedance state.The output buffer is set forcibly to "OFF" irrespective of the value of the DDR3
register.
176
CHAPTER 4 I/O PORT
Table 4.5-4 shows the state of the port 3 pins.
Table 4.5-4 The state of the port 3 pins
Pin Name
Normal
Operation
Sleep mode
Stop Mode,
Timebase Timer Mode or Watch Mode
SPL=0
P30 to P33,
P35/X0A to
P37/ADTG
Generalpurpose I/O
ports
Generalpurpose I/O
ports
General-purpose I/O
ports
SPL=1
Input cut off, and
output becomes Hi-Z
SPL: Pin state specification bit of low power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
177
CHAPTER 4 I/O PORT
4.6
Port 4
Port 4 is a general-purpose I/O port that also serves as a peripheral resource I/O pin.
Use port 4 by switching between the resource pin and the general-purpose I/O port.
The configuration, pin assignment, block diagram of the pins, and registers for port 4
are shown below.
■ Configuration of Port 4
Port 4 consists of the following three elements:
• General-purpose I/O port, resource I/O pin (P40/SIN1 to P44/RX)
• Port 4 data register (PDR4)
• Port 4 direction register (DDR4)
■ Pin Assignment of Port 4
• The pin is used either a resource pin or a general-purpose I/O pin
• Since the port serves as a resource pin, it cannot be used as a general-purpose I/O port when used as a
resource.
• When using port 4 as the input pin of the resource, set the pin corresponding to the resource in the
DDR4 as an input port.
• When using the port as the output of the resource, set the output of the corresponding resource to
enabled.Port 4 functions as the output pin of the resource regardless of the settings of the DDR4.
Table 4.6-1 shows pin assignment of port 4.
Table 4.6-1 Pin Assignment of Port 4
Port Name
Port 4
Reference:
178
Pin
Name
I/O Type
Port Function
Resource
P40/
SIN1
P40
SIN1
UART1 serial data
input
P41/
SCK1
P41
SCK1
UART1 serial clock
I/O
P42/
SOT1
P42
SOT1
UART1 serial data
output
Generalpurpose I/O
P43/TX
P43
TX
CAN controller
send output
P44/RX
P44
RX
CAN controller
receive input
For the circuit type, see Section "1.7 I/O Circuit".
Circuit
Type
Input
Output
CMOS
CMOS (hysteresis)/
Automotive/CMOS
CMOS
H
CMOS
CMOS (hysteresis)/
Automotive
CMOS
D
CHAPTER 4 I/O PORT
■ Block Diagram of Pins of Port 4
Figure 4.6-1 Block Diagram of Pins of Port 4
Resource input
Resource output
Port data register (PDR)
Resource output
acceptance
Internal data bus
PDR read
P-ch
Output latch
PDR write
Pin
Port direction register (DDR)
N-ch
Direction latch
DDR write
Standby control (SPL=1)
DDR read
Standby control : Control of stop mode (SPL=1), timebase timer mode (SPL=1) and clock mode (SPL=1)
■ Registers for Port 4
• The registers for port 4 are PDR4 and DDR4.
• The bits composing each register correspond to the pins of port 4 one-to-one.
Table 4.6-2 shows correspondence between registers and pin for port 4.
Table 4.6-2 Correspondence between Registers and Pins for Port 4
Port Name
Bits of Related Registers and Corresponding Pins
PDR4, DDR4
−
−
−
bit4
bit3
bit2
bit1
bit0
Corresponding pin
−
−
−
P44
P43
P42
P41
P40
Port 4
179
CHAPTER 4 I/O PORT
4.6.1
Registers for Port 4 (PDR4, DDR4)
The registers for port 4 are explained.
■ Function of Registers for Port 4
● Port 4 data register (PDR4)
• Port 4 data register indicates the state of the pins.
● Port 4 direction register (DDR4)
• The port 4 direction register sets the input/output directions.
• When the bit corresponding to the pin is set to "1", port 1 functions as an output port. When the bit is set
to "0", port 1 functions as an input port.
Table 4.6-3 shows functions of the registers for port 4.
Table 4.6-3 Functions of the Registers for Port 4
Register
Name
Data
At Read
The pin state is
Low level.
"0" is set for the output
latch, and when the pin is an
output port pin, the Low
level is output to the pin.
1
The pin state is
High level.
"1" is set for the output
latch, and when the pin is an
output port pin, the High
level is output to the pin.
0
The direction
latch is" 0".
The output buffer is set to
"OFF", and the pin becomes
an input port pin.
The direction
latch is "1".
The output buffer is set to
"ON", and the pin becomes
an output port pin
0
Port 4 data
register
(PDR4)
Port 4
direction
register
(DDR4)
At Write
1
Read/
Write
Register
Address
Reset Value
R/W
000004H
XXXXXXXXB
R/W
000014H
XXX00000B
R/W: Read/Write
X: Undefined
References:
180
• When using port 4 as the input pin of the resource, set the pin corresponding to
the resource in the DDR4 as an input port.
• When using port 1 as the output pin of the resource, set the output of the
corresponding resource to enabled.Port 4 functions as the output pin of the
resource regardless of the settings of the DDR4.
CHAPTER 4 I/O PORT
4.6.2
Operation of Port 4
The operation of port 4 is explained.
■ Operation of Port 4
● Operation of output port
• When the bit in the port 4 direction register (DDR4) corresponding to the output pin is set to "1", port 4
functions as an output port.
• When the output buffer is turned "ON" and output data is written to the port 4 data register (PDR4), the
data is retained in the output latch and output from the pin.
• When the port 4 data register (PDR4) is read, the state of the output latch in the port 4 data register
(PDR4) is read.
Note:
If read modify write instructions (such as the bit set instruction) are used to read the
PDR, the pin set as an output port by the DDR outputs the desired data. To switch a
pin from input port to output port, write output data to the port data register and use
the port direction register to set the pin as an output port.
● Operation of input port
• If the bit in the DDR4 corresponding to the input pin is set to "0", port 4 functions as an output port.
• The output buffer is turned "OFF" and the pin enters the high impedance state.
• When data is written to the PDR4, it is retained in the output latch in the PDR4 but not output to the pin.
• When the PDR4 is read, the level value (Low or High) of the pin is read.
● Operation of resource output
• When using the port as the output pin of the resource, set the resource output to enabled.
• Since the resource output is preferred enabled, the resource output functions regardless of the settings of
the DDR4.
• When the pin state is read with the resource output set to enabled, the output state of the resource is
read.
● Operation of resource input
• The state of the pin that serves as the resource input is input to the resource.
• When using port 4 as the input pin of the resource, clear the bit in the DDR4 corresponding to the input
pin of the resource to 0 and set the input pin as an input port.
● Operation at reset
• When the CPU is reset, the value of the DDR4 is initialized to "0".Consequently, all output buffers are
set to "OFF" (the pin becomes an input port pin), and the pin enters the high-impedance state.
• The PDR4 is not initialized by reset. Therefore, when using port 4 as an output port, it is necessary to set
output data in the PDR4, and then set the bit in the DDR4 corresponding to the output pin to ""1 and to
output.
181
CHAPTER 4 I/O PORT
● Operation in stop mode, timebase timer mode or watch mode
If the pin state specify bit (SPL) of the low-power consumption mode control register (LPMCR) is set to
"1" when the CPU operation mode switches to stop mode, timebase timer mode or watch mode, the pin
enters the high-impedance state.In this case, the output buffer is forcibly set to off regardless of the values
of the Port 4 direction register (DDR4).
Table 4.6-4 shows the state of the port-4 pins.
Table 4.6-4 The state of the port 4 pins
Pin Name
Normal
Operation
Sleep mode
Stop Mode,
Timebase Timer Mode or Watch Mode
SPL=0
P40/SIN1 to
P44/RX
Generalpurpose I/O
ports
Generalpurpose I/O
ports
General-purpose I/O
ports
SPL=1
Input cut off, and
output becomes Hi-Z
(Pull-up resistor
disconnected)
SPL: Pin state specification bit of low power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
182
CHAPTER 4 I/O PORT
4.7
Port 5
Port 5 is a general-purpose I/O port that also serves as an analog input pin. Use port 5
by switching between the analog input pin and the general-purpose I/O port.
The configuration, pin assignment, block diagram of the pins, and registers for port 5
are shown below.
■ Configuration of Port 5
Port 5 consists of the following four elements:
• General-purpose I/O port, analog input pins (P50/AN0 to P57AN7)
• Port 5 data register (PDR5)
• Port 5 direction register (DDR5)
• Analog input enable register (ADER)
■ Pins Assignment of Port 5
• The pin is used either as an analog input pin or a general-purpose I/O pin.
• Since port 5 serves as an analog input pin, it cannot be used as a general-purpose I/O port when used as
an analog input pin.
• When using port 5 as an analog input pin, set the pin corresponding to the analog input in the DDR5 as
an input port.
• When using port 5 as a general-purpose I/O port, do not input any analog signal.
183
CHAPTER 4 I/O PORT
Table 4.7-1 shows pins assignment of port 5.
Table 4.7-1 Pins Assignment of Port 5
Port Name
Pin
Name
I/O Type
Port Function
P50/AN0
P50
AN0
Analog input
channel 0
P51/AN1
P51
AN1
Analog input
channel 1
P52/AN2
P52
AN2
Analog input
channel 2
P53/AN3
P53
AN3
Analog input
channel 3
Generalpurpose I/O
Port 5
Reference:
184
Resource
P54/AN4
P54
AN4
Analog input
channel 4
P55/AN5
P55
AN5
Analog input
channel 5
P56/AN6
P56
AN6
Analog input
channel 6
P57/AN7
P57
AN7
Analog input
channel 7
For the circuit type, see Section "1.7 I/O Circuit".
Input
Output
CMOS
(hysteresis)/analog
input/Automotive
CMOS
Circuit
Type
E
CHAPTER 4 I/O PORT
■ Block Diagram of Pins of Port 5
Figure 4.7-1 Block Diagram of Pins of Port 5
Analog input
ADER
PDR (Port data register)
Internal data bus
PDR read
Output latch
P-ch
PDR write
Pin
DDR (Port direction register)
Direction latch
N-ch
DDR write
Standby control (SPL=1)
DDR read
Standby control : Control of stop mode (SPL=1), timebase timer mode (SPL=1) and clock mode (SPL=1)
■ Registers for Port 5
• The registers for port 5 are PDR5, DDR5, and ADER.
• The ADER sets input of an analog signal to the analog input pin to enabled or disabled.
• The bits composing each register correspond to the pins of port 5 one-to-one.
Table 4.7-2 shows correspondence between registers and pins for port 5.
Table 4.7-2 Correspondence between Registers and Pins for Port 5
Port Name
Bits of Related Registers and Corresponding Pins
PDR5 to DDR5
Port 5
ADER
Corresponding pin
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
P57
P56
P55
P54
P53
P52
P51
P50
185
CHAPTER 4 I/O PORT
4.7.1
Registers for Port 5 (PDR5, DDR5, ADER)
The registers for port 5 are explained.
■ Function of Registers for Port 5
● Port 5 data register (PDR5)
• Port 5 data register indicates the state of the pins.
● Port 5 direction register (DDR5)
• The port 5 direction register sets the input/output directions.
• When the bit corresponding to the pin is set to "1", port 1 functions as an output port. When the bit is set
to "0", port 1 functions as an input port.
● Analog input enable register (ADER)
• The analog input enable register (ADER) sets the general-purpose I/O ports and analog input pin in unit
of ports.
• When the ADE bit corresponding to the analog input pin is set to "1", port 5 functions as an analog input
pin. When the bit is set to "0", port 5 functions as a general-purpose I/O port.
Table 4.7-3 shows functions of the registers for port 5.
Note:
186
When a middle-level signal is input with port 5 set as an input port, input leakage
current flows. Therefore, when inputting an analog signal, set the corresponding ADE
bit in the ADER to analog input enabled.
CHAPTER 4 I/O PORT
Table 4.7-3 Functions of the Registers for Port 5
Register
Name
Data
At Read
At Write
The pin state is
Low level.
"0" is set for the output
latch, and when the pin is
an output port pin, the Low
level is output to the pin.
1
The pin state is
High level.
"1" is set for the output
latch, and when the pin is
an output port pin, the High
level is output to the pin.
Port 5
direction
register
(DDR5)
0
The direction
latch is "0".
The output buffer is set to
"OFF", and the pin
becomes an input port pin.
1
The direction
latch is "1".
The output buffer is set to
"ON", and the pin becomes
an output port pin
Analog input
enable register
(ADER)
0
General-purpose I/O ports
1
Analog input mode
0
Port 5 data
register
(PDR5)
Read/
Write
Register
Address
Reset Value
R/W
000005H
XXXXXXXXB
R/W
000015H
00000000B
R/W
00001BH
11111111B
R/W: Read/Write
X: Undefined
References:
• When using port 5 as an analog input pin, set the pin corresponding to the analog
input in the DDR5 as an input port.
• When using port 5 as the input pin of the resource, clear the bit in the DDR5
corresponding to the input pin of the resource to "0" and set the input pin as an
input port.
187
CHAPTER 4 I/O PORT
4.7.2
Operation of Port 5
The operation of port 5 is explained.
■ Operation of Port 5
● Operation of output port
• When the bit in the port 5 direction register (DDR5) corresponding to the output pin is set to "1", port 5
functions as an output port.
• When the output buffer is turned "ON2 and output data is written to the port 5 data register (PDR5), the
data is retained in the output latch and output from the pin.
• When the port 5 data register (PDR5) is read, the state of the output latch in the PDR5 is read.
Note:
If read modify write instructions (such as the bit set instruction) are used to read the
PDR, the pin set as an output port by the DDR outputs the desired data. To switch a
pin from input port to output port, write output data to the port data register and use
the port direction register to set the pin as an output port.
● Operation of input port
• If the bit in the DDR5 corresponding to the input pin is set to "0", port 5 functions as an input port.
• The output buffer is turned "OFF" and the pin enters the high impedance state.
• When data is written to the port 5 data register (PDR5), it is retained in the output latch in the PDR5 but
not output to the pin.
• When the PDR5 is read, the level value (Low or High) of the pin is read.
● Operation of analog input
• When using port 5 as an analog input pin, set the bit in the ADER corresponding to the analog input pin
to "1".Port 5 is disabled to operate as a general-purpose I/O port, and functions as an analog input pin.
• When the PDR5 is read with the bit set to analog input enabled, the read value is "0".
188
CHAPTER 4 I/O PORT
● Operation at reset
• When the CPU is reset, the value of the DDR5 is initialized to "0".Consequently, all output buffers are
set to "OFF" (the pin becomes an input port pin), and the pin enters the high-impedance state.
• The PDR5 is not initialized by reset. Therefore, when using port 5 as an output port, it is necessary to set
output data in the PDR5, and then set the bit in the DDR5 corresponding to the output pin to "1" and to
output.
● Operation in stop mode, timebase timer mode or watch mode
• When the pin state specification bit of the low power consumption mode control register (LPMCR:
SPL) is "1", at a transition to the stop mode, timebase timer mode or watch mode, the pin enters the
high- impedance state. The output buffer is set forcibly to "OFF" irrespective of the value of the DDR5.
Table 4.7-4 shows the state of the port 5 pins.
Table 4.7-4 The state of the port 5 pins
Pin Name
Normal
Operation
Sleep
mode
Stop Mode,
Timebase Timer Mode or Watch Mode]
SPL=0
P50/AN0,
P57/AN7
Generalpurpose I/O
ports
Generalpurpose I/O
ports
General-purpose I/O
ports
SPL=1
Input cut off, and output
becomes Hi-Z
SPL: Pin state specification bit of low power consumption mode control register (LPMCR: SPL)
Hi-Z: High impedance
189
CHAPTER 4 I/O PORT
4.8
Port input level select register
The port input level select register is used to set the input signal to CMOS hysteresis
input, Automotive input, or to CMOS input.
■ Port input level select register (PILR)
bit
PILR:00A2H
Read/Write
Initial value
7
6
ILS1 ILS0
5
4
3
2
1
0
IL5
IL4
IL3
IL2
IL1
-
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(-)
(-)
The CMOS hysteresis and Automotive input levels are set in units of ports.For P32/SIN0 and P40/SIN1,
CMOS setting is possible as well.
Table 4.8-1 shows functions of input level select register.
Table 4.8-1 Functions of port input level select register
bit
bit name
Applicable ports
Function
7
ILS1*2
P40/SIN1
0:Conform to the IL3 setting.
1:CMOS level
6
ILS0*2
P32/SIN0
0:Conform to the IL3 setting.
1:CMOS level
5
IL5
P50 to P57
0:CMOS hysteresis level
1:Automotive level
4
IL4
P40 to P44
0:CMOS hysteresis level
1:Automotive level
3
IL3
P30 to P33
P35, P36*1, P37*1
2
IL2
P20 to P27
0:CMOS hysteresis level
1:Automotive level1
1
IL1
P00 to P17
0:CMOS hysteresis level
1:Automotive level
0
Unused bit
-
0:CMOS hysteresis level
1:CMOS Automotive level
Write: No effect on operation
Read: Read value undefined
*1:Only MB90F897S
*2:P32/SIN0 and P40/SIN1 serve for CMOS input independently of IL3/IL4 when ILS0/ILS1 is
"1".When ILS0/ILS1 is "0", the input level set by IL3/IL4 is selected.
Note:
190
This feature is not provided for the MB90V495G.This register therefore returns "1"
whenever read.
CHAPTER 5
TIMEBASE TIMER
This chapter describes the function and operation of the
timebase timer.
5.1 Overview of Timebase Timer
5.2 Block Diagram of Timebase Timer
5.3 Configuration of Timebase Timer
5.4 Interrupt of Timebase Timer
5.5 Explanation of Operations of Timebase Timer Functions
5.6 Precautions when Using Timebase Timer
5.7 Program Example of Timebase Timer
191
CHAPTER 5 TIMEBASE TIMER
5.1
Overview of Timebase Timer
The timebase timer is an 18-bit free-run counter (timebase timer counter) that
increments in synchronization with the main clock (half frequency of main oscillation
clock).
• Four interval times can be selected and an interrupt request can be generated for
each interval time.
• An operation clock is supplied to the oscillation stabilization wait time timer and
other peripherals.
■ Interval Timer Function
• When the timebase timer counter reaches the interval time set by the interval time select bits (TBTC:
TBC1, TBC0), an overflow occurs (TBTC: TBOF = 1) and an interrupt request is generated.
• When an interrupt is enabled when an overflow occurs (TBTC: TBIE = 1), an overflow occurs (TBTC:
TBOF = 1) and an interrupt is generated.
• The timebase timer has four interval times that can be selected.Table 5.1-1 shows the interval times of
the timebase timer.
Table 5.1-1 Interval Times of Timebase Timer
Count Clock
Interval Time
212/HCLK (approx. 1.0 ms)
2/HCLK (0.5 μs)
214/HCLK (approx. 4.1 ms)
216/HCLK (approx. 16.4 ms)
219/HCLK (approx. 131.1 ms)
HCLK: Oscillation clock
The parenthesized values are provided at 4-MHz oscillation clock.
192
CHAPTER 5 TIMEBASE TIMER
■ Clock Supply
• The timebase timer supplies an operation clock to the resources such as an oscillation stabilization wait
time timer, PPG timer, and watchdog timer. Table 5.1-2 shows the clock cycles supplied from the
timebase timer.
Table 5.1-2 Clock Cycles Supplied from Timebase Timer
Where to Supply Clock
Clock Cycle
210/HCLK (approx. 256 μs)
213/HCLK (approx. 2.0 ms)
Oscillation Stabilization Wait Time*
215/HCLK (approx. 8.2 ms)
217/HCLK (approx. 32.8 ms)
212/HCLK (approx. 1.0 ms)
214/HCLK (approx. 4.1 ms)
Watchdog timer
216/HCLK (approx. 16.4 ms)
219/HCLK (approx. 131.1 ms)
PPG timer
29/HCLK (approx. 128 μs)
HCLK: Oscillation clock
The parenthesized values are provided at 4-MHz oscillation clock.
*:As the oscillation cycle is unstable immediately after oscillation starts, standard oscillation
stabilization wait time values are given as a guide.
193
CHAPTER 5 TIMEBASE TIMER
5.2
Block Diagram of Timebase Timer
The timebase timer consists of the following blocks:
• Timebase timer counter
• Counter clear circuit
• Interval timer selector
• Timebase timer control register (TBTC)
■ Block Diagram of Timebase Timer
Figure 5.2-1 Block Diagram of Timebase Timer
To watchdog
timer
To PPG timer
Timebase timer counter
21/HCLK
× 21 × 22 × 23
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
OF
OF
OF
OF
Power-on reset
Stop mode
CKSCR: MCS=1 → 0*1
CKSCR: SCS=0 → 1*2
To clock control part
oscillation stabilization
waiting time selector
Counter clear
circuit
Interval
timer selector
TBOF clear
Timebase timer control register
(TBTC)
Reserved
-
TBOF set
-
TBIE TBOF TBR TBC1 TBC0
Timebase timer interrupt signal
OF
: Over flow
HCLK : Oscillation clock
*1
: For switching machine clock from mainclock to PLL clock
*2
: For switching machine clock from sub clock to main clock
The actual interrupt request number of the timebase timer is as follows:
Interrupt request number: #16 (10 H)
194
CHAPTER 5 TIMEBASE TIMER
● Timebase timer counter
The timebase timer counter is an 18-bit up counter that uses a clock with a half frequency of the oscillation
clock (HCLK) as a count clock.
● Counter clear circuit
The counter clear circuit clears the value of the timebase timer counter by the following factors:
• Timebase timer counter clear bit in the timebase timer control register (TBTC: TBR = 0)
• Power on reset
• Transition to main stop mode or PLL stop mode (CKSCR: SCS = 1, LPMCR: STP = 1)
• Switching the clock mode (from main clock mode to PLL clock mode, from subclock mode to PLL
clock mode, or from subclock mode to main clock mode)
● Interval timer selector
The time interval selector selects the output of the timebase timer counter from four types.When
incrementing causes the selected interval time bit to overflow, an interrupt request is generated.
● Timebase timer control register (TBTC)
The timebase timer control register (TBTC) selects the interval time, clears the timebase timer counter,
enables or disables interrupts, and checks and clears the state of an interrupt request.
195
CHAPTER 5 TIMEBASE TIMER
5.3
Configuration of Timebase Timer
This section explains the registers and interrupt factors of the timebase timer.
■ List of Registers and Reset Values of Timebase Timer
Figure 5.3-1 List of Registers and Reset Values of Timebase Timer
bit
Timebase timer control register
(TBTC)
15
14
13
12
11
10
9
8
1
×
×
0
0
1
0
0
× : Undefined
■ Generation of Interrupt Request from Timebase Timer
When the selected timebase timer counter bit reaches the interval time, the overflow interrupt request flag
bit in the timebase timer control register (TBTC: TBOF) is set to "1".If the overflow interrupt request flag
bit is set (TBTC: TBOF = 1) when the interrupt is enabled (TBTC: TBIE = 1), the timebase timer generates
an interrupt request.
196
CHAPTER 5 TIMEBASE TIMER
5.3.1
Timebase timer control register (TBTC)
The timebase timer control register (TBTC) provides the following settings:
• Selecting the interval time of the timebase timer
• Clearing the count value of the timebase timer
• Enabling or disabling the interrupt request when an overflow occurs
• Checking and clearing the state of the interrupt request flag when an overflow occurs
■ Timebase timer control register (TBTC)
Figure 5.3-2 Timebase timer control register (TBTC)
15
14
13
R/W
-
-
12
11
10
9
8
Reset value
1XX00100B
R/W R/W W R/W R/W
bit9 bit8
TBC1 TBC0
Interval time select bit
0
0
212/HCLK (approx. 1.0ms)
0
1
214/HCLK (approx. 4.1ms)
1
0
216/HCLK (approx. 16.4ms)
1
1
219/HCLK (approx. 131.1ms)
HCLK: Oscillation clock
The parenthesized values are provided when the oscillation clock
operates at 4 MHz.
bit10
TBR
0
1
Timebase timer counter clear bit
Write
Read
Clear timebase timer counter.
Clear TBOF bit.
No effect.
1 is always read.
bit11
TBOF
0
1
bit12
TBIE
0
1
Over flow interrupt request flag bit
Write
Read
Without over flow of
Being clear.
selected count bit
No effect
With over flow of
selected count bit
Over flow interrupt enable bit
Disabling of over flow interrupt request
Enabling of over flow interrupt request
bit15
Reserved bit
Reserved
R/W : Read/write
W : Write only
X
: Undefined
: Reset value
: Unused
1
1 is always set.
197
CHAPTER 5 TIMEBASE TIMER
Table 5.3-1 Functions of Timebase Timer Control Register (TBTC)
bit name
198
Function
bit15
Reserved: reserved bit
Always set this bit to "1".
bit14,
bit13
Unused bits
Read: The value is undefined.
Write: No effect
bit12
TBIE:
Overflow interrupt
enable bit
This bit enables or disables an interrupt when the interval time
bit in the timebase timer counter overflows.
When set to "0": No interrupt request is generated at an
overflow (TBOF = 1).
When set to "1": An interrupt request is generated at an
overflow (TBOF = 1).
bit11
TBOF:
Overflow interrupt
request flag bit
This bit indicates an overflow (carrying) in the time interval bit
in the timebase timer counter.
When an overflow (carrying) occurs with interrupts enabled
(TBIE = 1), an interrupt request is generated.
When set to "0": The bit is cleared.
When set to "1": Disabled.The state remains unchanged.
Read by read modify write instructions: "1" read
Note:
1)To clear the TBOF bit, disable interrupts (TBIE = 0) or
mask interrupts using the interrupt mask register (ILM) in
the processor status.
2)The TBOF bit is cleared at a write of "0", transition to
main stop mode or to PLL stop mode, transition from
subclock mode to main clock mode or to PLL mode,
transition from main clock mode to PLL clock mode, at a
write of "0" to the timebase timer counter clear bit (TBR),
or at a reset.
bit10
TBR:
Timebase timer counter
clear bit
This bit clears all the bits in the timebase timer counter.
When set to "0": All the bits in the timebase timer counter are
cleared to "0".The TBOF bit is also cleared.
When set to "1": Disabled.The state remains unchanged.
Read: "1" is always read.
bit9,
bit8
TBC1, TBC0:
Interval time select bits
These bits set the cycle of the interval timer in the timebase
timer counter.
• The interval time of the timebase timer is set according to the
setting of the TBC1 and TBC0 bits.
• One of four time intervals can be selected.
CHAPTER 5 TIMEBASE TIMER
5.4
Interrupt of Timebase Timer
The timebase timer generates an interrupt request (interval timer function) when the
interval time bit in the timebase timer counter corresponding to the interval time set by
the timebase timer control register carries (overflows).
■ Interrupt of Timebase Timer
• The timebase timer continues incrementing for as long as the main clock (with a half frequency of the
oscillation clock) is input.
• When the interval time set by the interval time select bits in the timebase timer control register (TBTC:
TBC1, TBC0) is reached, the interval time select bit corresponding to the interval time selected in the
timebase timer counter overflows.
• When the interval time select bit overflows, the overflow interrupt request flag bit in the timebase timer
control register (TBTC: TBOF) is set to "1".
• When the overflow interrupt request flag bit in the timebase timer control register is set (TBTC: TBOF
= 1) with an interrupt enabled (TBTC: TBIE = 1), an interrupt request is generated.
• When the selected interval time is reached, the overflow interrupt request flag bit in the timebase timer
control register (TBTC: TBOF) is set regardless of whether an interrupt is enabled or disabled (TBTC:
TBIE)
• To clear the overflow interrupt request flag bit (TBTC: TBOF), disable a timebase timer interrupt at
interrupt processing or mask a timebase timer interrupt by using the ILM bit in the processor status (PS)
to write "0" to the TBOF bit.
Note:
An interrupt request is issued immediately if you enable interrupts (TBTC: TBIE = 1)
with the overflow interrupt request flag bit set (TBTC: TBOF = 1) in the timebase
timer control register.
■ Correspondence between Timebase Timer Interrupt and EI2OS
• The timebase timer does not correspond to EI2OS.
• For details of the interrupt number, interrupt control register, and interrupt vector address, see Section
"3.5 Interrupt".
199
CHAPTER 5 TIMEBASE TIMER
5.5
Explanation of Operations of Timebase Timer Functions
The timebase timer operates as an interval timer or an oscillation stabilization wait time
timer. It also supplies a clock to peripherals.
■ Interval Timer Function
Interrupt generation at every interval time enables the timebase timer to be used as an interval timer.
Operating the timebase timer as an interval timer requires the settings shown in Figure 5.5-1.
● Setting of timebase timer
Figure 5.5-1 Setting of timebase timer
Timebase timer control register
(TBTC)
- : Unused bit
: Used bit
0 : Set to "0".
1 : Set to "1".
bit15
14
13
12
11
10
Reserved
-
-
TBIE
TBOF
TBR
0
0
1
9
bit8
TBC1 TBC0
● Operations of the Interval Timer Functions
The timebase timer can be used as an interval timer by generating an interrupt at every set interval time.
• The timebase timer continues incrementing in synchronization with the main clock (a half frequency of
the oscillation clock) while the oscillation clock is active.
• When the timebase timer counter reaches the interval time set by the interval time select bits in the
timebase timer control register (TBTC: TBC1, TBC0), it causes an overflow (carrying) and the overflow
interrupt request flag bit (TBTC: TBOF) is set to "1".
• When the overflow interrupt request flag bit is set (TBTC: TBOF = 1) with interrupts enabled (TBTC:
TBIE = 1), an interrupt request is generated.
Note:
200
The interval time may be longer than the one set by clearing the timebase timer
counter.
CHAPTER 5 TIMEBASE TIMER
● Example of operation of timebase timer
Figure 5.5-2 gives an example of the operation that the timebase timer performs under the following
conditions:
• A power-on reset occurs.
• The mode transits to the sleep mode during the operation of the interval timer.
• The mode transits to the stop mode during the operation of the interval timer.
• A request to clear the timebase timer counter is issued.
At transition to the stop mode, the timebase timer counter is cleared to stop counting.At return from the
stop mode, the timebase timer counts the oscillation stabilization wait time of the main clock.
Figure 5.5-2 Example of operation of timebase timer
Counter value
Clear by transfering to
stop mode
3FFFFH
Oscillation stabilization
waiting over flow
00000H
Start CPU
operation
Power-on reset
Interval cycle
(TBTC : TBC1 : TBC0=11B)
Counter clear
(TBTC : TBR=0)
Clear by interrupt process
TBOF bit
TBIE bit
Sleep
SLP bit
(LPMCR register)
Cancellation of sleep at interval
interrupt of timebase timer
Stop
STP bit
(LPMCR register)
When set the interval time select bit (TBTC : TBC1, TBC0) to "11B" (219/HCLK)
: Oscillation stabilization waiting time
HCLK: Oscillation clock
201
CHAPTER 5 TIMEBASE TIMER
■ Operation as Oscillation Stabilization Wait Time Timer
The timebase timer can be used as the oscillation stabilization wait timer for the main clock and PLL clock.
• The oscillation stabilization wait time is the time elapsed from when the timebase timer counter
increments from "0" until the set oscillation stabilization wait time select bit overflows (carrying).
Table 5.5-1 shows clearing conditions and oscillation stabilization wait time of timebase timer
Table 5.5-1 Clearing Conditions and Oscillation Stabilization Wait Time of Timebase Timer (1/2)
Operation
Counter
Clear
TBOF
Clear
Oscillation Stabilization Wait
Time
Writing "0" to timebase timer
counter clear bit (TBTC: T BR)
Reset
Power on reset
Transition to main clock mode after
oscillation stabilization wait time of
main clock completed
watchdog reset
×
None
External reset
×
None
Software reset
×
None
Switching Clock Mode
Main clock → PLL clock
(CKSCR: MCS=1 → 0)
Main clock → sub clock
(CKSCR: SCS=1 → 0)
Transition to PLL clock mode after
oscillation stabilization wait time of
PLL clock completed
×
×
Transition to sub clock mode after
oscillation stabilization wait time of
sub clock completed
Sub clock → main clock
(CKSCR: SCS=0 → 1)
Transition to main clock mode after
oscillation stabilization wait time of
main clock completed
Sub clock → PLL clock
(CKSCR: MCS=0, SCS=0 → 1)
Transition to PLL clock mode after
oscillation stabilization wait time of
main clock completed
PLL clock → main clock
(CKSCR: MCS=0 → 1)
×
×
None
PLL clock → sub clock
(CKSCR: MCS=0, SCS=1 → 0)
×
×
None
Cancellation of stop modes
Cancellation of main stop mode
Cancellation of sub-stop mode
202
Transition to main clock mode after
oscillation stabilization wait time of
main clock completed
×
×
Transition to sub clock mode after
oscillation stabilization wait time of
sub clock completed
CHAPTER 5 TIMEBASE TIMER
Table 5.5-1 Clearing Conditions and Oscillation Stabilization Wait Time of Timebase Timer (2/2)
Operation
Counter
Clear
TBOF
Clear
Cancellation of PLL stop mode
Oscillation Stabilization Wait
Time
Transition to PLL clock mode after
oscillation stabilization wait time of
main clock completed
Cancellation of timer mode
×
×
None
Return to main clock mode
×
×
None
Return to sub clock mode
×
×
None
Return to PLL clock mode
×
×
None
Cancellation of main sleep mode
×
×
None
Cancellation of sub-sleep mode
×
×
None
Cancellation of PLL sleep mode
×
×
None
Cancellation of sub-timer mode
Cancellation of timebase timer modes
Cancellation of sleep modes
■ Supply of Operation Clock
The timebase timer supplies an operation clock to the PPG timers (PPG01, PPG23) and the watchdog
timer.
Note:
Clearing the timebase timer counter may affect the operation of the resources such
as the watchdog timer and PPG timers using the output of the timebase timer.
References:
• For details on the PPG timer, see "CHAPTER 10 8/16-bit PPG timer".
• For details on the watchdog timer, see "CHAPTER 6 WATCHDOG TIMER".
203
CHAPTER 5 TIMEBASE TIMER
5.6
Precautions when Using Timebase Timer
Precautions when using the timebase timer are shown below.
■ Precautions when Using Timebase Timer
● Clearing interrupt request
To clear the overflow interrupt request flag bit in the timebase timer control register (TBTC: TBOF = 0),
disable interrupts (TBTC: TBIE = 0) or mask the timebase timer interrupt by using the interrupt level mask
register in the processor status.
● Clearing timebase timer counter
Clearing the timebase timer counter affects the following operations:
• When the timebase timer is used as the interval timer (interval interrupt).
• When the watchdog timer is used.
• When the clock supplied from the timebase timer is used as the operation clock of the PPG timer.
● Using timebase timer as oscillation stabilization wait time timer
• After power on or in the main stop mode, PLL stop mode, and sub clock mode, the oscillation clock
stops.Therefore, when oscillation starts, the timebase timer requires the oscillation stabilization wait
time of the main clock. An appropriate oscillation stabilization wait time must be selected according to
the types of oscillators connected to high-speed oscillation input pins.
Reference:
For details on the oscillation stabilization wait time, see "3.7.6 Oscillation Stabilization
Wait Time".
● Resources to which timebase timer supplies clock
• At transition to operation modes (PLL stop mode, sub clock mode, and main stop mode) in which the
oscillation clock stops, the timebase timer counter is cleared and the timebase timer stops.
• When the timebase timer counter is cleared, an after-clearing interval time is needed. It may cause the
clock supplied from the timebase timer to have a short High level or a 1/2 cycle longer Low level.
• The watchdog timer performs normal counting because the watchdog timer counter and timebase timer
counter are cleared simultaneously.
204
CHAPTER 5 TIMEBASE TIMER
5.7
Program Example of Timebase Timer
Programming examples for the timebase timer are shown below.
■ Program Example of Timebase Timer
● Processing specification
The 212/HCLK (HCLK: oscillation clock) interval interrupt is generated repeatedly.In this case, the interval
time is approximately 1.0 ms (at 4-MHz operation).
● Coding example
ICR02
EQU
0000B2H
;Time base timer interrupt control register
TBTC
EQU
0000A9H
;Time base timer control register
TBOF
EQU
TBTC:3
;Interrupt rquest flag bit
TBIE
EQU
TBTC:2
;Interrupt enable bit
;-------Main program--------------------------------------CODE
CSEG
START:
;Stack pointer(SP),already initialized
AND
MOV
MOV
CCR,#0BFH
;Interrupt disable
I:ICR02 #00H
;Interrupt level 0(highest)
I:TBTC,#10000000B
;Upper 3 bis are fixed
;TBOF clear,
;Counter clear interval time
;212/HCLK selection
SETB
I:TBIE
;Interrupt enable
MOV
ILM,#07H
;Setting ILM in PS to level 7
OR
CCR,#40H
;Interrupt enable
LOOP:
MOV
A,#00H
;No limit roop
MOV
A,#01H
BRA
LOOP
;-------Interrupt program-----------------------------------WARI:
CLRB
I:TBIE
;Clear interrupt enable bit
CLRB
I:TBOF
;Clear interrupt request flag
.
User processing
.
SETB
I:TBIE
;Interrupt enable
RETI
;Recovery from interrupt processing
CODE
ENDS
;-------Vector setting---------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFBCH
;Vector setting to interrupt number #16(10H)
DSL
WARI
ORG
0FFDCH
;Reset bector setting
DSL
START
DB
00H
;Setting to single chip mode
VECT
ENDS
END
START
205
CHAPTER 5 TIMEBASE TIMER
206
CHAPTER 6
WATCHDOG TIMER
This chapter describes the function and operation of the
watchdog timer.
6.1 Overview of Watchdog Timer
6.2 Configuration of Watchdog Timer
6.3 Watchdog Timer Registers
6.4 Explanation of Operations of Watchdog Timer Functions
6.5 Precautions when Using Watchdog Timer
6.6 Program Examples of Watchdog Timer
207
CHAPTER 6 WATCHDOG TIMER
6.1
Overview of Watchdog Timer
The watchdog timer is a 2-bit counter that uses the timebase timer or watch timer as a
count clock.If the counter is not cleared within a set interval time, the CPU is reset.
■ Functions of Watchdog Timer
• The watchdog timer is a timer counter that is used to prevent program malfunction.When the watchdog
timer is started, the watchdog timer counter must continue to be cleared within a set interval time.If the
set time interval is reached without clearing the watchdog timer counter, the CPU is reset. This is called
watchdog timer
• The interval time of the watchdog timer depends on the clock cycle input as a count clock and a
watchdog reset occurs between the minimum and maximum times.
• The clock source output destination is set by the watchdog clock select bit in the watch timer control
register (WTC: WDCS).
• The interval time of the watchdog timer is set by the timebase timer output select bit/watch timer output
select bit in the watchdog timer control register (WDTC: WT1, WT0).
Table 6.1-1 lists the interval times of the watchdog timer.
Table 6.1-1 Interval Time of Watchdog Timer
Min.
Max.
Clock Cycle
Min.
Max.
Clock Cycle
Approx. 3.58
ms
Approx. 4.61
ms
214 ± 211/
HCLK
Approx.
0.457 s
Approx.
0.576 s
212 ± 29/
SCLK
Approx.
14.33 ms
Approx. 18.3
ms
216 ± 213/
HCLK
Approx.
3.584 s
Approx.
4.608 s
215 ± 212/
SCLK
Approx.
57.23 ms
Approx.
73.73 ms
218 ± 215/
HCLK
Approx.
7.168 s
Approx.
9.216 s
216 ± 213/
SCLK
Approx.
458.75 ms
Approx.
589.82 ms
221 ± 218/
HCLK
Approx.
14.336 s
Approx.
18.432 s
217 ± 214/
SCLK
HCLK: Oscillation clock (4 MHz), SLCK: Sub clock (8.192 kHz)
Notes:
208
• When the timebase timer output (carry signal) is used as a count clock to the
watchdog timer, clearing the timebase timer may extend the time for a watchdog
reset to occur.
• When the subclock is used as the machine cock, be sure to set the watchdog
timer clock source select bit (WDCS) in the watch timer control register (WTC) to
"0" to select the watch timer output.
CHAPTER 6 WATCHDOG TIMER
6.2
Configuration of Watchdog Timer
The watchdog timer consists of the following blocks:
• Count clock selector
• Watchdog timer counter (2-bit counter)
• Watchdog reset generator
• Counter clear control circuit
• Watchdog timer control register (WDTC)
■ Block Diagram of Watchdog Timer
Figure 6.2-1 Block Diagram of Watchdog Timer
Watchdog timer control register (WDTC)
PONR
-
Clock timer control register (WTC)
WRST ERST SRST WTE WT1
Watchdog timer
WT0
WDCS
2
Start up
Generation of reset
Shift to sleep mode
Shift to timebase
timer mode
Shift to clock mode
Shift to stop mode
Counter clear
control circuit
Count clock
selector
2-bit
counter
Watchdog reset
generation
circuit
To internal reset
generation circuit
Clear
4
4
(Timebase timer counter)
Main clock
(2 division of HCLK)
× 21 × 22
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
(Clock counter)
Sub clock
SCLK
× 21 × 22
× 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215
HCLK : Oscillation clock
SCLK : Sub clock
209
CHAPTER 6 WATCHDOG TIMER
● Count clock selector
The count clock selector selects the timebase timer output or watch timer output as a count clock input to
the watchdog timer.Each timer output has four time intervals that can be set.
● Watchdog timer counter (2-bit counter)
The watchdog timer counter is a 2-bit counter that uses the timebase timer output or watch timer output as a
count clock.The clock source output destination is set by the watchdog clock select bit in the watch timer
control register (WTC: WDCS).
● Watchdog reset generator
The watchdog reset generation circuit generates a reset signal when the watchdog timer overflows.
● Counter clear circuit
The counter clear controller clears the watchdog timer counter.
● Watchdog timer control register (WDTC)
The watchdog timer control register starts and clears the watchdog timer, sets the interval time, and holds
reset factors.
210
CHAPTER 6 WATCHDOG TIMER
6.3
Watchdog Timer Registers
This section explains the registers used for setting the watchdog timer.
■ List of Registers and Reset Values of Watchdog Timer
Figure 6.3-1 List of Registers and Reset Values of Watchdog Timer
bit
Watchdog timer control register
(WDTC)
7
6
5
4
3
2
1
0
×
×
×
×
×
1
1
1
× : Undefined
211
CHAPTER 6 WATCHDOG TIMER
6.3.1
Watchdog timer control register (WDTC)
The watchdog timer control register starts and clears the watchdog timer, sets the
interval time, and holds reset factors.
■ Watchdog timer control register (WDTC)
Figure 6.3-2 Watchdog timer control register (WDTC)
7
6
5
4
3
2
1
0
R
-
R
R
R
W
W
W
Reset value
XXXXX111B
bit1
bit0
Interval time select bit (timebase timer output select)
WT1 WT0
Interval time
Min
Max
Clock cycle
0
0 approx. 3.58ms approx. 4.61ms
214 ± 211/HCLK
0
1 approx. 14.33ms approx. 18.3ms
216 ± 213/HCLK
1
0 approx. 57.23ms approx. 73.73ms
218 ± 215/HCLK
1
1 approx. 458.75ms approx. 589.82ms 221 ± 218/HCLK
HCLK: Oscillation clock
The parenthesized values are interval time when the oscillation
clock operates at HCLK 4 MHz.
bit1
bit0
Interval time select bit (clock timer outpu select)
WT1 WT0
Interval time
Min
Max
Clock cycle
0
0
approx. 0.457s
approx. 0.576s
212 ± 29/SCLK
0
1
215 ± 212/SCLK
approx. 3.584s
approx. 4.608s
1
0
216 ± 213/SCLK
approx. 7.168s
approx. 9.216s
1
1
217 ± 214/SCLK
approx. 14.336s
approx. 18.432s
SCLK: Sub clock
The parenthesized values are interval time when the oscillation
clock operates at SCLK 8.192 kHz.
bit2
Watchdog timer control bit
WTE
0
1
bit7
First programming after reset:
Twice or more programming after reset :
Start up the watchdog timer
Clear the watchdog timer
No effect
bit5 bit4 bit3
Reset factor bit
Reset factor
PONR WRST ERST SRST
R
W
*
X
212
: Read only
: Write only
: The previous state is held.
: Undefined
1
*
*
*
X
1
*
*
X
*
1
*
X
*
*
1
Watchdog reset
External reset (Low level input to RST pin)
Software reset (write "1" to RST bit)
CHAPTER 6 WATCHDOG TIMER
Table 6.3-1 Functions of the Watching Timer Control Register (WDTC)
bit name
Function
bit7,
bit5
to
bit3
PONR, WRST, ERST,
SRST:
Reset Factor bits
These bits indicate reset factors.
• When a reset occurs, the bit corresponding to the reset factor
is set to "1".After a reset, the reset factor can be checked by
reading the watchdog timer control register (WDTC).
• These bits are cleared after the watchdog timer control
register (WDTC) is read.
Note:
No bit value other than the PONR bit after power-on reset is
assured.If the PONR bit is set at read, other bit values should
be ignored.
bit6
Unused bit
Read: The value is undefined.
Write: No effect
bit2
WTE:
Watchdog timer control
bit
This bit starts or clears the watchdog timer.
When set to "0" (first time after reset):
The watchdog timer is started.
When set to "0" (second or subsequent):
The watchdog timer is cleared.
bit1,
bit0
WT1, WT0:
Interval time select bits
These bits set the interval time of the watchdog timer.
'The time interval when the watch timer is used as the clock source
to the watchdog timer (watchdog clock select bit WDCS = 0) is
different from when the main clock mode or the PLL clock
mode is selected as the clock mode and the WDCS bit in the
watch timer control register (WTC) is set to "1" as shown in
Figure 6.3-2 according to the settings of the WTC register.
• Settings of the WTC register.
• Write data after the watchdog timer is started is ignored.
• These are write-only bits.
213
CHAPTER 6 WATCHDOG TIMER
6.4
Explanation of Operations of Watchdog Timer Functions
After starting, when the watchdog timer reaches the set interval time without the
counter being cleared, a watchdog reset occurs.
■ Operations of Watchdog Timer
The operation of the watchdog timer requires the settings shown in Figure 6.4-1.
Figure 6.4-1 Setting of Watchdog Time
Watchdog timer control register
(WDTC)
bit7
6
PONR
-
5
4
3
2
WRST ERST SRST WTE
1
bit0
WT1 WT0
0
bit7
Clock timer control register
(WTC)
6
5
4
3
2
1
bit0
WDCS SCE WTIE WTOF WTR WTC2 WTC1WTC0
: Used bit
0 : Set to "0".
● Selecting clock input source
• The timebase timer or watch timer can be selected as the clock input source to the watchdog timer.When
the watchdog clock select bit (WTC: WDCS) is set to "1", the timebase timer is selected. When the bit is
set to "0", the watch timer is selected.After a reset, the bit returns to "1".
• During operation in the sub clock mode, set the WDCS bit to 0 to select the watch timer.
● Setting interval time
• Set the interval time select bits (WDTS: WT1, WT0) to select the interval time for the watchdog timer.
• Set the interval time concurrently when starting the watchdog timer.Writing to the bit is ignored after
the watchdog timer is started.
● Activating watchdog timer
• When "0" is written to the watchdog timer control bit (WDTC: WTE) after a reset, the watchdog timer
is started and starts incrementing.
214
CHAPTER 6 WATCHDOG TIMER
● Clearing watchdog timer
• When "0" is written once again to the watchdog timer control bit (WDTC: WTE) within the interval
time after starting the watchdog timer, the watchdog timer is cleared. If the watchdog timer is not
cleared within the interval time, it overflows and the CPU is reset.
• A reset, or transitions to the standby modes (sleep mode, stop mode, watch mode, timebase timer mode)
clear the watchdog timer.
• During operation in the timebase timer mode or watch mode, the watchdog timer counter is cleared.
However, the watchdog timer remains in the activation state.
• Figure 6.4-2 shows relationship between clear timing and interval time of watch dog timer. The interval
time varies with the timing of clearing the watchdog timer.
215
CHAPTER 6 WATCHDOG TIMER
● Checking reset factors
• The reset factor bits in the watchdog timer control register (WDTC: PONR, WRST, ERST, SRST) can
be read after a reset to check the reset factors.
Note:
For details on the reset source bit, see "Section 3.6 Reset".
Figure 6.4-2 Relationship between Clear Timing and Interval Time of Watchdog Timer
[Watchdog timer block diagram]
2-bit counter
Clock
selector
a
2-division
circuit
b
2-division
circuit
c
Reset circuit
d
Reset
signal
Count enable and clear
WTE bit
Count enable
output circuit
[Minimum interval time] When clear WTE bit immediately before rising of counter clock.
Count start
Counter clear
Count clock a
2-division's value b
2-division's value c
Count enable
Reset signal d
7 × (Count clock cycle/2)
WTE bit clear
Watchdog reset generation
[Minimum interval time] When clear WTE bit immediately after rising of counter clock.
Count start
Counter clear
Count clock a
2-division's value b
2-division's value c
Count enable
Reset signal
9 × (Count clock cycle/2)
WTE bit clear
216
Watchdog reset generation
CHAPTER 6 WATCHDOG TIMER
6.5
Precautions when Using Watchdog Timer
Take the following precautions when using the watchdog timer.
■ Precautions when Using Watchdog Timer
● Stopping watchdog timer
• The watchdog timer is stopped by all the reset sources.
● Interval time
• The interval time uses the carry signal of the time-base timer or watch timer as a count clock. If the
time-base timer or watch timer is cleared, the interval time of the watchdog timer may become long.
Note that the timebase timer is cleared when "0" is written to the timebase timer counter clear bit (TBR)
in the timebase timer control register (TBTC) and when the clock mode changes from the main clock to
PLL clock, from the subclock to main clock, or from the subclock to PLL clock.
• Set the interval time concurrently when starting the watchdog timer. Setting the time interval except
starting the watchdog timer is ignored.
● Precautions when creating program
• When clearing the watchdog timer repeatedly in the main loop, set a shorter processing time for the
main loop, including interrupt processing, than the interval time of watchdog timer.
217
CHAPTER 6 WATCHDOG TIMER
6.6
Program Examples of Watchdog Timer
Program example of watchdog timer is given below:
■ Program Examples of Watchdog Timer
● Processing specification
• The watchdog timer is cleared each time in the loop of the main program.
• The main program must be executed once within the minimum interval time of the watchdog timer.
● Coding example
WTE
EQU
WDTC:2
;Watchdog control bit
;
;---------Main program------------------------------------CODE
CSEG
START:
;Stack pointer(SP),already initialized
MOV
I:WDTC,#00000011B
;Start up of watchdog timer
;Select interval time 221+218 cycle
LOOP:
CLRB I:WTE
;Clear watchdog timer
.
User processing
.
BRA
LOOP
;---------Vector setting-----------------------------------------VECT
CSEG ABS=0FFH
ORG
00FFDCH
;Reset vector setting
DSL
START
DB
00H
;Setting to single chip mode
VECT
ENDS
END
START
218
CHAPTER 7
16-bit I/O TIMER
This chapter explains the function and operation of the
16- bit input/output timer.
7.1 Overview of 16-bit Input/Output Timer
7.2 Block Diagram of 16-bit Input/Output Timer
7.3 Configuration of 16-bit Input/Output Timer
7.4 Interrupts of 16-bit Input/Output Timer
7.5 Explanation of Operation of 16-bit Free-run Timer
7.6 Explanation of Operation of Input Capture
7.7 Precautions when Using 16-bit Input/Output Timer
7.8 Program Example of 16-bit Input/Output Timer
219
CHAPTER 7 16-bit I/O TIMER
7.1
Overview of 16-bit Input/Output Timer
The 16-bit input/output timer is a combined module that consists of a 16-bit free-run
timer (x 1 unit) and an input capture (x 2 units/4 input pins).The clock cycle of an input
signal and a pulse width can be measured based on the 16-bit input/output timer.
■ Configuration of 16-bit Input/Output Timer
The 16-bit input/output timer consists of the following modules:
• 16-bit free-run timer (× 1 unit)
• Input capture (× 2 units with 2 input pins each)
■ Functions of 16-bit Input/Output Timer
● Functions of 16-bit free-run timer
The 16-bit free-run timer consists of a 16-bit up counter, a timer counter control status register, and a
prescaler.The 16-bit up counter increments in synchronization with the division ratio of the machine clock.
• Count clock is selected from four machine clock division ratios.Count Clock: φ, φ/2, φ/4, φ/8, φ/16,
φ/32, φ/64, φ/128
• An overflow in the count value generates an interrupt.
• Interrupt generation starts the extended intelligent I/O service (EI2OS).
• Either a reset or software reset by the timer count clear bit TCCS: CLR) clears the count value of the 16bit free-run timer to "0000H".
• The count value of the 16-bit free-run timer is output to the input capture and can be used as the base
time for capture operation.
● Functions of input capture
When the input capture detects the edge of the external signal input to the input pins, it stores the count
value of the 16-bit free-run timer in the input capture data registers. The input capture consists of the input
capture data registers corresponding to four input pins, an input capture control status register, and an edge
detection circuit.
• The detected edge can be selected from among the rising edge, falling edge, and both edges.
• Detecting the edge of the input signal generates an interrupt request to the CPU.
• Interrupt generation starts the extended intelligent I/O service (EI2OS).
• The input capture unit has four sets of input pins and input capture data registers which can be used to
measure up to four events.
220
CHAPTER 7 16-bit I/O TIMER
7.2
Block Diagram of 16-bit Input/Output Timer
The 16-bit input/output timer consists of the following modules:
• 16-bit free-run timer
• Input capture
■ Block Diagram of 16-bit Input/Output Timer
Figure 7.2-1 Block Diagram of 16-bit Input/Output Timer
Internal data bus
Input
capture
Dedicated bus
16-bit
free run
timer
● 16-bit free-run timer
The count value of the 16-bit free-run timer can be use as the base time for the input capture.
● Input capture
The input capture detects the rising edge, falling edge, or both edges of the external signal input to the input
pins to retain the count value of the 16-bit free-run timer.Detecting the edge of the input signal generates an
interrupt.
221
CHAPTER 7 16-bit I/O TIMER
7.2.1
Block Diagram of 16-bit Free-run Timer
The 16-bit free-run timer consists of the following blocks:
• Prescaler
• Timer counter data register (TCDT)
• Timer counter control status register (TCCS)
■ Block Diagram of 16-bit Free-run Timer
Figure 7.2-2 Block Diagram of 16-bit Free-run Timer
Timer counter data register
(TCDT)
Output count value
to input capture
16-bit free-run timer
φ
CLK
STOP
CLR
Internal data bus
OF
Prescaler
3
Timer counter control
status register
(TCCS)
IVF
IVFE STOP
Reserved
CLR CLK2 CLK1 CLK0
φ : Machine clock
OF : Over flow
Free-run timer
interrupt request
■ Details of Pins in Block Diagram
The 16-bit I/O timer contains one 16-bit free-run timer.
The interrupt request number of the 16-big free-run timer is as follows:
Interrupt request number: 19 (13 H)
● Prescaler
The prescaler divides the frequency of the machine clock to supply a count clock to the 16-bit up counter.
Any of four machine clock division ratios are selected by setting the timer counter control status register
(TCCS).
● Timer counter data register (TCDT)
The timer counter data register (TCDT) is a 16-bit up counter.At read, the current count value of the 16-bit
free-run timer can be read.Writing while the counter is stopped enables any count value to be set.
222
CHAPTER 7 16-bit I/O TIMER
● Timer counter control status register (TCCS)
The timer counter control status register (TCCS) selects the division ratio of the machine clock, clears the
count value by software, enables or disables the count operation, checks and clears the overflow generation
flag, and enables or disables interrupt.
223
CHAPTER 7 16-bit I/O TIMER
7.2.2
Block Diagram of Input Capture
The input capture consist of the following blocks:
• Input capture data registers (IPCP0 to IPCP3)
• Input capture control status registers (ICS01, ICS23)
• Edge detection circuit
■ Block Diagram of Input Capture
Figure 7.2-3 Block Diagram of Input Capture
16-bit free-run timer
Edge detection circuit
IN3
Input capture data register 3 (IPCP3)
Pin
IN2
Input capture data register 2 (IPCP2)
Pin
2
2
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
Input capture
instruction request
Input capture control
status register
(ICS01)
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
2
2
IN1
Input capture data register 1 (IPCP1)
Pin
IN0
Input capture data register 0 (IPCP0)
Pin
Edge detection circuit
224
Internal data bus
Input capture control
status register
(ICS23)
CHAPTER 7 16-bit I/O TIMER
■ Details of Pins in Block Diagram
The 16-bit input/output timer has four input capture input pins.
The actual pin names and interrupt request numbers used in the input capture unit are shown in Table 7.2-1.
Table 7.2-1 Pins and Interrupt Request Numbers of 16-bit Input/Output Timer
Input Pin
Actual Pin Name
Interrupt Request Number
IN0
P10/IN0
#23(17H)
IN1
P11/IN1
#25(19H)
IN2
P12/IN2
IN3
P13/IN3
#30(1EH)
● Input capture data registers (IPCP0 to IPCP3)
The counter value of the 16-bit free-run timer actually read when the edge of the external signal input to the
input pins (IN0 to IN3) is detected is stored in the input capture data registers (IPC0 to IPC3)
corresponding to the input pins (IN0 to IN3).
● Input capture control status registers (ICS01, ICS23)
The input capture control status registers start and stop the capture operation of each input capture, check
and clear the valid edge detection flag when the edge is detected, and enable or disable an interrupt. The
ICS01 register sets the input capture corresponding to the input pins IN0 and IN1, and the ICS23 register
sets the input capture corresponding to the input pins IN2 and IN3.
● Edge detection circuit
The edge detection circuit detects the edge of the external signal input to the input pins.The detected edge
can be selected from among the rising edge, falling edge, and both edges.
225
CHAPTER 7 16-bit I/O TIMER
7.3
Configuration of 16-bit Input/Output Timer
This section explains the pins, registers, and interrupt factors of the 16-bit input/output
timer.
■ Pins of 16-bit Input/Output Timer
The pins of the 16-bit input/output timer serve as general-purpose I/O ports. Table 7.3-1 shows the pin
functions and the pin settings required to use the 16-bit input/output timer.
Table 7.3-1 Pins of 16-bit Input/Output Timer
Pin
Name
Pin Setting Required for Use of 16bit Input/Output Timer
Pin Function
IN0
General-purpose I/O port, capture input
Set as input port in port direction
register (DDR).
IN1
General-purpose I/O port, capture input
Set as input port in port direction
register (DDR).
IN2
General-purpose I/O port, capture input
Set as input port in port direction
register (DDR).
IN3
General-purpose I/O port, capture input
Set as input port in port direction
register (DDR).
■ Block Diagram of Pins for 16-bit Input/Output Timer
Reference:
226
For the block diagram of the pins, see "CHAPTER 4 I/O PORT".
CHAPTER 7 16-bit I/O TIMER
■ List of Registers and Reset Values of 16-bit Input/Output Timer
Figure 7.3-1 List of Registers and Reset Values of 16-bit Input/Output Timer
bit
Timer counter control status register
(TCCS)
bit
Timer counter data register upper
(TCDT: H)
bit
Timer counter data register lower
(TCDT: L)
bit
Input capture control status
register(ICS01)
bit
Input capture data register 0
upper (IPCP0: H)
bit
Input capture data register 0
lower (IPCP0: L)
bit
Input capture data register 1
upper (IPCP1: H)
bit
Input capture data register 1
lower (IPCP1: L)
bit
Input capture control status
register (ICS23)
bit
Input capture data register 2
upper (IPCP2: H)
bit
Input capture data register 2
lower (IPCP2: L)
bit
Input capture data register 3
upper (IPCP3: H)
bit
Input capture data register 3
lower (IPCP3: L)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
× : Undefined
227
CHAPTER 7 16-bit I/O TIMER
■ Generation of Interrupt Request from 16-bit Input/Output Timer
The 16-bit input/output timer can generate an interrupt request as a result of the following factors:
● Overflow in 16-bit free-run timer
In the 16-bit input/output timer, when the 16-bit free-run timer overflows, the overflow generation flag bit
in the timer counter control status register (TCCS: IVF) is set to "1".When an overflow interrupt is enabled
(TCCS: IVFE = 1), an interrupt request is generated.
● Edge detection by capture function
The counter value of the 16-bit free-run timer actually read when the edge of the external signal input to the
input pins (IN0 to IN3) is detected is stored in the input capture data registers (IPC0 to IPC3)
corresponding to the input pins (IN0 to IN3). When the input capture interrupt corresponding to the channel
generating an interrupt request is enabled (ICS: ICE), an interrupt request is generated.
228
CHAPTER 7 16-bit I/O TIMER
7.3.1
Timer counter control status register (TCCS)
The timer counter control status register (TCCS) selects the count clock and conditions
for clearing the counter, clears the counter, enables or disables the count operation or
interrupt, and checks the interrupt request flag.
■ Timer counter control status register (TCCS)
Figure 7.3-2 Timer counter control status register (TCCS)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit2
bit1
bit0
CLK2 CLK1 CLK0
Count clock setting bit
Count clock
φ =16MHz φ =8MHz φ =4MHz φ =1MHz
0
0
0
φ
0
0
1
φ /2
0.125 μs 0.25 μs
0
1
0
φ /4
0.25 μs
0
1
1
φ /8
1
0
0
1
0
1
1
62.5ns
0.125 μs 0.25 μs
1 μs
0.5 μs
2 μs
0.5 μs
1 μs
4 μs
0.5 μs
1 μs
2 μs
8 μs
φ /16
1 μs
2 μs
4 μs
16 μs
1
φ /32
2 μs
4 μs
8 μs
32 μs
1
0
φ /64
4 μs
8 μs
16 μs
64 μs
1
1
φ /128
8 μs
16 μs
32 μs
128 μs
φ : Machine clock
bit3
Timer count clear bit
CLR
0
No effection
1
Initialize counter to "0000H".
bit4
Reserved bit
Reserved
0
Be sure to set to "0".
bit5
Timer count operating bit
STOP
0
1
Count operating enabled
Count operating disabled (stop)
bit6
Over flow interrupt enable bit
IVFE
0
Over flow interrupt disabled
1
Over flow interrupt enabled
bit7
IVF
R/W : Read/Write
: Reset value
0
1
Over flow generating flag bit
Read
Without over flow
With orver flow
Write
Clear
No effection
229
CHAPTER 7 16-bit I/O TIMER
Table 7.3-2 Functions of Timer Counter Control Status Register (TCCS)
bit name
230
Function]
bit7
IVF:
Overflow generation flag
bit
This bit indicates that the 16-bit free-run timer has overflowed.
• This bit is set to "1" either when the 16-bit free-run timer
causes an overflow or when mode setting causes a compare
match with compare register 0 to clear the counter.
• When an overflow occurs with an overflow interrupt enabled
(IVFE = 1), an interrupt request is generated.
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
When EI2OS started: Bit cleared
Read by read modify write instructions: "1" is always read.
bit6
IVFE:
Overflow interrupt
enable bit
This bit enables or disables an interrupt request generated when
the 16-bit free- run timer overflows.
When set to "0": No interrupt request generated at overflow
(IVF = 1)
When set to "1": Generates interrupt request at overflow
(IVF = 1)
bit5
STOP:
Timer count bit
This bit enables or disables (stops) the count operation of the 16bit free-run timer.
When set to "0": Enables count operation.
The 16-bit timer counter data register
(TCDT) starts incrementing in
synchronization with the count clock selected
by the count clock select bits
(CLK1 and CLK0).
When set to "1": Stops count operation
bit4
Reserved: reserved bit
Always set this bit to "0".
bit3
CLR:
Timer count clear bit
This bit clears the count value of the 16-bit free-run timer.
When set to "1": Clears timer counter data register (TCDT) to
"0000H"
When the bit is set to "0": No effect.
Read: "0" is always read.
• When the count value changes, the CLR bit is cleared.
• When clearing the count value while stopping the count
operation, write "0000H" to the timer counter data register
(TCDT).
Note:
If "1" is written to this bit first and then "0" is written before
the next count clock, the counter value is not initialized.
bit0
bit1
bit2
CLK2, CLK1, CLK0:
Count clock selection
bits
These bits set the count clock to the 16-bit free-run time.
Notes:
• Set the count clock after stopping the count operation
(STOP = 1).
• When rewriting the count clock, write "1" to the timer
counter clear bit (CLR) and clear the count value.
CHAPTER 7 16-bit I/O TIMER
7.3.2
Timer counter data register (TCDT)
The timer counter data register (TCDT) is a 16-bit up counter.At read the register value
being counted is read.At write while the counter is stopped, any count value can be set.
■ Timer counter data register (TCDT)
Figure 7.3-3 Timer counter data register (TCDT)
bit15 bit14 bit13 bit12 bit11 bit10 bit9
Timer counter data
register (TCDT): upper
Timer counter data
register (TCDT): lower
T15
T14
T13
T12 T11
T10
bit8
T9
Reset value
T8
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reset value
T7
T6
T5
T4
T3
T2
T1
T0
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Read /Write
■ Count Operation of Timer Counter Data Register (TCDT)
• When the timer counter data register (TCDT) is read during the count operation, the count value of the
16-bit free-run timer is read.
• When the count value of the timer counter data register (TCDT) increments from "FFFFH" to "0000H",
an overflow occurs and the overflow generation flag bit (TCCS: IVF) is also set to "1".
• When an overflow occurs (TCCS: IVF = 1) with an overflow interrupt enabled (TCCS: IVFE = 1), an
overflow interrupt request is generated.
• The count value of the timer counter data register (TCDT) is retained while the count operation is
stopped.
• When stopping the count operation of the timer counter data register (TCDT), write 1 to the timer count
operation bit (TCCS: STOP).
• When the count operation stops (TCCS: STOP = 1), the counter of the timer counter data register
(TCDT) can be set to any value.
231
CHAPTER 7 16-bit I/O TIMER
● Factors clearing timer counter data register (TCDT)
The timer counter data register (TCDT) is cleared to 0000 H by the following factors: Of the following
events, the overflow clears the register in synchronization with the count clock and each of the other events
clears the register on occurrence of that event.
• Reset
• Writing "1" to the timer count clear bit (TCCS: CLR) (possible even during count operation)
• Writing "0000H" to timer counter data register (TCDT) while count operation stopped
• Overflow in 16-bit free-run timer
Note:
232
Always use a word instruction (MOVW) to set the timer counter data register (TCDT).
CHAPTER 7 16-bit I/O TIMER
7.3.3
Input capture control status registers (ICS01, ICS23)
The input capture control status registers sets the operation of input captures.The
ICS01 register sets the operation of input captures 0 and 1 and the ICS23 sets the
operation of input captures 2 and 3.The input capture control status registers provides
the following settings:
• Selecting the edge to be detected
• Enabling or disabling an interrupt when the edge is detected
• Checking and clearing the valid edge detection flag when the edge is detected
■ Input capture control status registers (ICS01, ICS23)
Figure 7.3-4 Input capture control status registers (ICS01, ICS23)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit1 bit0
EG01 EG00
Input capture 0 (2) edge select bit
0
0
Without edge detection
0
1
Detect rising edge
1
0
Detect falling edge
1
1
Detect both edge
bit3 bit2
EG11 EG10
Operating enable
Operating disable
Input capture 1 (3) edge select bit
0
0
Without edge detection
0
1
Detect rising edge
1
0
Detect falling edge
1
1
Detect both edge
Operating enable
Operating disable
bit4
Input capture 0 (2) interrupt enable bit
ICE0
0
Input capture 0 (2) interrupt disable
1
Input capture 0 (2) interrupt enable
bit5
Input capture 1 (3) interrupt enable bit
ICE1
0
Input capture 1 (3) interrupt disable
1
Input capture 1 (3) interrupt enable
bit6
ICP0
0
1
Input capture 0 (2) enable available edge detection flag bit
Read
Input capture 0 (2)
without available edge detection
Input capture 0 (2)
With available edge detection
Write
Clear of ICP0 bit
No effenct
bit7
ICP1
Input capture 1 (3) enable available edge detection flag bit
0
Read
Input capture 1 (3)
without available edge detection
1
Input capture 1 (3)
R/W : Read/Write
With available edge detection
: Reset value
Numbers in ( ) show channel numbers in ICS23.
Write
Clear of ICP1 bit
No effenct
233
CHAPTER 7 16-bit I/O TIMER
Table 7.3-3 Functions of Input Capture Control Status Register (ICS01)
bit name
234
Function
bit7
ICP1:
Input capture 1 valid
edge detection flag bit
This bit indicates the edge detection by input capture 1.
• When the valid edge selected by the input capture 1 edge
select bits (EG11, EG10) is detected, the ICP1 bit is set to
"1".
• When the valid edge is detected by input capture 1 (ICP1 =
1) when an interrupt due to the edge detection by input
capture 1 is enabled (ICE1 = 1), an interrupt is generated.
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
When EI2OS started: Bit cleared
Read by read modify write instructions: "1" is always read.
bit6
ICP0:
Input capture 0 valid
edge detection flag bit
This bit indicates the edge detection by input capture 0.
• When the valid edge selected by the input capture 0 edge
select bits (EG01, EG00) is detected, the ICP0 bit is set to "1".
• When the valid edge is detected by input capture 0 (ICP0 = 1)
when an interrupt due to the edge detection by input capture
0 is enabled (ICE0 = 1), an interrupt is generated.
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
When EI2OS started: Bit cleared
Read by read modify write instructions: "1" is always read.
bit5
ICE1:
Input capture 1 interrupt
enable bit
This bit enables or disables an interrupt when the edge is
detected by input capture 1.
When set to "0": No interrupt is generated even when the edge
is detected by input capture 1.
When set to "1": An interrupt is generated when the edge is
detected by input capture 1.
bit4
ICE0:
Input capture 0 interrupt
enable bit
This bit enables or disables an interrupt when the edge is
detected by input capture 0.
When set to "0": No interrupt is generated even when the valid
edge is detected by input capture 0.
When set to "1": An interrupt is generated when the valid edge
is detected by input capture 0.
bit3
bit2
EG11, EG10:
Input capture 1 edge
select bits
These bits enable or disable the operation of input capture 1.The
edge detected by input capture 1 is selected when the operation
of input capture 1 is enabled.
EG01, EG00=00B: The operation of input capture 1 is disabled
and no edge is detected.
EG01, EG00=00B: The operation of input capture 1 is enabled
and the edge is detected.
bit1
bit0
EG01, EG00:
Input capture 0 edge
select bits
These bits enable or disable the operation of input capture 0.The
edge detected by input capture 0 is selected when the operation
of input capture 0 is enabled.
EG01, EG00 =00B: The operation of input capture 0 is disabled
and no edge is detected.
EG01, EG00=00B: The operation of input capture 0 is enabled
and the edge is detected.
CHAPTER 7 16-bit I/O TIMER
7.3.4
Input capture data registers (IPCP0 to IPCP3)
The input capture data registers 0 to 3 (IPCP0 to IPCP3) store the counter value of the
16-bit free-run timer read in the timing with the edge detection by the input capture.The
counter value of the 16-bit free-run timer is stored in the input capture data registers
(IPCP0 to IPCP3) corresponding to the input pins (IN0 to IN3) to which an external signal
is input.
■ Input capture data registers (IPCP0 to IPCP3)
Figure 7.3-5 Input capture data registers (IPCP0 to IPCP3)
bit15 bit14 bit13 bit12 bit11 bit10 bit9
Input capture data
register (IPCP) : upper
R
X
Reset value
CP15 CP14 CP13 CP12 CP11 CP10 CP9 CP8
R
R
bit7
Input capture data
register (IPCP) :lower
bit8
R
R
bit2
R
XXXXXXXXB
R
bit3
R
Reset value
R
bit4
R
CP7 CP6 CP5 CP4 CP3 CP2 CP1 CP0
R
bit5
R
bit0
R
bit6
R
XXXXXXXXB
R
bit1
R
R
: Read only
: Undefined
■ Operation of Input Capture Data Registers 0 to 3 (IPCP0 to IPCP3)
• At the same time that the edges of signals input from the input pins (IN0 to IN3) of the 16-bit input/
output timer are detected, the counter value of the 16-bit free-run timer is stored in the input capture data
registers 0 to 3 (IPCP0 to IPCP3) corresponding to the input pins (INO to IN3).
Note:
Always use a word instruction (MOVW) to read the input capture data registers 0 to 3
(IPCP0 to IPCP3).
235
CHAPTER 7 16-bit I/O TIMER
7.4
Interrupts of 16-bit Input/Output Timer
The interrupt factors of the 16-bit input/output timer include an overflow in the 16-bit
free-run timer and edge detection by the input capture.Interrupt generation starts EI2OS.
■ Interrupt Control Bits and Interrupt Factors of 16-bit Input/Output Timer
Table 7.4-1 shows interrupt control bits and interrupt factors of 16-bit input/output timer.
Table 7.4-1 Interrupt Control Bits and Interrupt Factors of 16-bit Input/Output Timer
Interrupt
Name
Overflow interrupt
Input Capture Interrupt
Interrupt
Factor
Overflow in counter
value of 16-bit freerun timer
Valid edge input to input pins (IN0 to IN3) of input capture
IN0
IN1
IN2
IN3
Interrupt
request flag
bit
TCCS: IVF
ICS01:ICP0
ICS01:ICP1
ICS23:ICP0
ICS23:ICP1
Interrupt
enable bit
TCCS: IVFE
ICS01:ICE0
ICS01:ICE1
ICS23:ICE0
ICS23:ICf
● 16-bit free-run timer interrupt
• When the count value of the timer counter data register (TCDT) increments from "FFFFH" to "0000H",
an overflow occurs and the overflow generation flag bit (TCCS: IVF) is also set to "1".
• When an overflow occurs (TCCS: IVF = 1) with an overflow interrupt enabled (TCCS: IVFE = 1), an
overflow interrupt request is generated.
● Input Capture Interrupt
• When the valid edge selected by the input capture edge select bit (ICS: EG) is detected, the input
capture interrupt request flag bits (ICS01, ICS23: ICP1, ICP0) corresponding to the input pins (IN0 to
IN3) are set to "1".
• When the valid edge is detected by the input captures corresponding to the input pins (IN0 to IN3) with
the input capture interrupts corresponding to the input pins (IN0 to IN3) enabled, an input capture
interrupt is generated.
■ Correspondence between 16-bit Input/Output Timer Interrupt and EI2OS
For details of the interrupt number, interrupt control register, and interrupt vector address, see 3.5 Interrupt.
■ 16-bit Input/Output Timer Interrupt and EI2OS function
The 16-bit I/O timer corresponds to the EI2OS function. Generation of an enabled interrupt factor starts the
EI2OS.However, it is necessary to disable generation of interrupt requests by peripherals sharing the
interrupt control register.
236
CHAPTER 7 16-bit I/O TIMER
7.5
Explanation of Operation of 16-bit Free-run Timer
After a reset, the 16-bit free-run timer starts incrementing from "0000H".When the
counter value is incremented from "FFFFH" to "0000H", an overflow occurs.
■ Setting of 16-bit Free-run Timer
Operation of the 16-bit free-run timer requires the setting shown in Figure 7.5-1
Figure 7.5-1 Setting of 16-bit Free-run Timer
bit15 14
13
12
11
10
9
bit8 bit7
5
4
3
2
1
bit0
Re- CLR CLK2 CLK1 CLK0
IVF IVFE STOP served
TCCS
0
TCDT
6
0
0
Counter value of 16-bit free-run timer
: Using bit
0
: Setting to "0"
Reserved : Be sure to set to "0".
■ Operation of 16-bit Free-run Timer
• After a reset, the 16-bit free-run timer starts incrementing from "0000H" in synchronization with the
count clock selected by the count clock select bits (TCCS: CLK2, CLK1, CLK0).
• When the counter value of the timer counter data register (TCDT) is incremented from "FFFFH"to
"0000H", an overflow occurs.When an overflow occurs, the overflow generation flag bit (TCCS: IVF) is
set to "1" and the 16-bit free-run timer starts incrementing again from "0000H".
• When an overflow occurs (TCCS: IVF = 1) with an overflow interrupt enabled (TCCS: IVFE = 1), an
overflow interrupt request is generated.
• When stopping the count operation of the timer counter data register (TCDT), write "1" to the timer
count operation bit (TCCS: STOP).
• Set the counter value in the timer counter data register (TCDT) after stopping the count operation of the
16-bit free-run timer.After completing setting of the count value, enable the count operation of the 16bit free-run timer (TCCS: STOP = 0).
237
CHAPTER 7 16-bit I/O TIMER
■ Operation Timing of 16-bit Free-run Timer
Figure 7.5-2 shows counter clearing at an overflow.
Figure 7.5-2 Counter Clearing at an Overflow
Counter value
Over flow
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Reset
Over flow interrupt
238
Time
CHAPTER 7 16-bit I/O TIMER
7.6
Explanation of Operation of Input Capture
When the input capture detects the edge of the external signal input to the input pins, it
stores the count value of the 16-bit free-run timer in the input capture data registers.
■ Setting of Input Capture
Operation of the input capture requires the setting shown in Figure 7.6-1
Figure 7.6-1 Setting of Input Capture
bit15 14
13
12
11
10
9
bit8 bit7
6
5
4
3
2
1
bit0
ICP1ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
ICS
IPCP
DDR port
direction register
Hold counter value of 16-bit free-run timer
Setting the corresponding bit using pin
as capture input pin to "0"
: Using bit
239
CHAPTER 7 16-bit I/O TIMER
■ Operation of Input Capture
• When the valid edges of the external signals input to the input pins (IN0 to IN3) are detected, the input
capture valid edge detection flag bit (ICS: ICP) corresponding to the input pin is set to "1".At the same
time, the count value of the 16-bit free-run timer is stored in the input capture data registers (IPCP)
corresponding to the input pins (IN0 to IN3).
• The edge to be detected can be selected from the rising edge, falling edge and both edges by setting the
input capture edge select bit in the input capture control status register (ICS: EG).]
• When the effective edge is detected by the input captures corresponding to the input pins (IN0 to IN3)
when the input captures corresponding to the input pins (IN0 to IN3) are enabled for interrupts, an input
capture interrupt is generated.
• The input capture valid edge detection flag bit (ICS: ICP) is set when the valid edge is detected,
regardless of the interrupt enable settings (ICS01, ICS23: ICE1, ICE0).
• Table 7.6-1 shows correspondence between input pins and input captures.
Table 7.6-1 Correspondence between Input Pins and Input Captures
240
Input Pin
Interrupt Request Flag
Bit of Input Capture
Interrupt Output
Enable Bit of Input
Capture
Input Capture Data
Register
IN0
ICS01: ICP0
ICS01: ICE0
IPCP0
IN1
ICS01: ICP1
ICS01: ICE1
IPCP1
IN2
ICS23: ICP0
ICS23: ICE0
IPCP2
IN3
ICS23: ICP1
ICS23: ICE1
IPCP3
CHAPTER 7 16-bit I/O TIMER
■ Operation Timing of Input Capture
Figure 7.6-2 shows the timing of reading the counter value of the 16-bit free-run timer.
Figure 7.6-2 Timing of Reading Counter Value of Input Capture
φ
Counter value
N
N+1
Input capture
input
Available edge
Capture signal
Input capture
data register (IPCP)
N+1
Input capture
interrupt
φ : Machine clock
Capturing counter value
Figure 7.6-3 shows the timing of the capture operation depending on the edge type.
Figure 7.6-3 Timing of Capture Operation Depending on Edge Type
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
IN0 (rising edge)
IN1 (falling edge)
IN2 (both edge)
Input capture
data register 0 (IPCP0)
Undefined
input capture
data register 1 (IPCP1)
Undefined
Input capture
data register 2 (IPCP2)
Undefined
3FFFH
7FFFH
BFFFH
3FFFH
Input capture 0
Interrupt
Input capture 1
Interrupt
Input capture 2
Interrupt
241
CHAPTER 7 16-bit I/O TIMER
7.7
Precautions when Using 16-bit Input/Output Timer
This section explains the precautions when using the 16-bit input/output timer.
■ Precautions when Using 16-bit Input/Output Timer
● Precautions when setting 16-bit free-run timer
• Do not change the count clock select bits (TCCS: CLK2, CLK1, CLK0) during the count operation
(TCCS: STOP = 0).
• The counter value of the 16-bit free-run timer is cleared to "0000H" by reset.The 16-bit free-run timer
can be set by writing any count value to the timer counter data register (TCDT) while the count
operation is stopped (TCCS: STOP = 1).
• Always use a word instruction (MOVW) to set the timer counter data register (TCDT).
● Precautions on interrupts
• When an overflow interrupt or an input capture interrupt is enabled, clear only the set bit of the overflow
generation flag bit or the input capture valid edge detection flag bit.When clearing the flag bit for an
event that caused an interrupt to be accepted, for example, avoid unconditional clearing of the interrupt
request flag bits for other interrupt trigger events because another input capture interrupt may have been
generated.
• If the interrupt request flag bits in the 16-bit input/output timer (TCCS: IVF, ICS01, ICS23: ICP1, ICP0)
are set to "1" and interrupts corresponding to the set interrupt request flag bits are enabled (TCCS: IVFE = 1,
ICS01, ICS23: ICE1 = 1, ICE0 = 1), it is impossible to return from interrupt processing. Always clear
the interrupt request flag bits.When using the EI2OS, the set interrupt request flag bits are cleared
automatically when the EI2OS is started.
242
CHAPTER 7 16-bit I/O TIMER
7.8
Program Example of 16-bit Input/Output Timer
This section gives a program example of the 16-bit input/output timer.
■ Processing of Program for Measuring Cycle Using Input Capture
• The cycle of a signal input to the IN0 pin is measured.
• The 16-bit free-run timer and input capture 0 are used.
• The rising edge is selected as the edge to be detected.
• The machine clock (φ) is 16 MHz and the count clock is φ/4 (0.25 μs).
• The overflow interrupt and input capture interrupt of input capture 0 are used.
• The overflow interrupt of the 16-bit free-run timer is counted beforehand and used for the cycle
calculation.
• The cycle can be determined from the following equation:
Cycle = (overflow count x "10000H" + nth IPCP0 value - (n-1)th IPCP0 value) x count clock cycle
= (overflow count x 10000H + nth IPCP0 value - (n-1)th IPCP0 value) x 0.25 μs
● Coding example
DDR1
TCCS
EQU
EQU
000011H
000058H
TCDT
ICS01
EQU
EQU
000056H
000054H
IPCP0
IVFE
ICP0
EQU
EQU
EQU
000050H
TCCS:5
ICS01:6
ICR04
EQU
0000B4H
ICR06
EQU
0000B6H
;Port direction register
;Timer counter control
;Status register
;Timer counter data register
;Input capture control
;Status register 01
;Input capture data register 0
;Over flow interrupt enable bit
;Input capture 0 interrupt request
;Flag bit
;Interrupt cotrol register
16-bit free-run timer
;Interrupt control register
16-bit inpu capture
DATA
DSEG ABS=00H
ORG
0100H
OV_CNT RW
1
;Over flow counter
DATA
ENDS
;---------Main program------------------------------------CODE
CSEG ABS=0FFH
START:
;Stack pointer (SP),
;already initialized
:
243
CHAPTER 7 16-bit I/O TIMER
AND
MOV
MOV
MOV
MOV
MOV
MOV
CCR,#0BFH
I:ICR04,#00H
I:ICR06,#00H
I:DDR1,#00000000B
I:TCCS,#00110100B
;Interrupt disable
;Interrupt level 0 (strongest)
;Interrupt level 0 (strongest)
;Setting pin to input
;Count enable,counter clear,
;Over flow,interrupt enable,
;Count clock φ/4 selection
I:ICS01,#00010001B ;IN0 pin selection,
;IPCP0 rising edge
;Without IPCP1 edge detection,
;Clear each interrupt request flag
;Input capture interrupt request enable
ILM,#07
;Setting interrupt mask level,
Interrupt enable
CCR,#40H
;Interrupt enanle
OR
:
;---------Interrupt program------------------------------------WARI1 CLRB I:ICP0
;Input capture 0 interrupt request
;Flag clear
:
User processing (processing of cycle calculate)
:
MOV
A,0
;Over flow for next cycle measuring
;Clear counter
MOV
D:OV_CNT,A
RETI
;Recover from interrupt
WARI2 CLRB I:IVFE
;Clear over flow interrupt request flag
INC
D:OV_CNT
;Over flow counter incremented by one
RETI
CODE
ENDS
;--------Vector setting----------------------------------------VECT
CSEG ABS=0FFH
ORG
0FFA0
;Setting vector to interrupt number #23 (17H)
DSL
WARI1
;Input capture 0 interrupt
ORG
0FFB0
;Setting vector to interrupt number #19 (13H)
DSL
WARI2
;Over flow interrupt
ORG
0FFDCH
;Reset vector setting
DSL
START
DB
00H
;Setting to single chip mode
VECT
ENDS
END START
244
CHAPTER 8
16-bit RELOAD TIMER
This chapter explains the functions and the operations
of 16-bit reload timer.
8.1 Overview of 16-bit Reload Timer
8.2 Block Diagram of 16-bit Reload Timer
8.3 Configuration of 16-bit Reload Timer
8.4 Interrupts of 16-bit Reload Timer
8.5 Explanation of Operation of 16-bit Reload Timer
8.6 Precautions when Using 16-bit Reload Timer
8.7 Program Example of 16-bit Reload Timer
245
CHAPTER 8 16-bit RELOAD TIMER
8.1
Overview of 16-bit Reload Timer
The 16-bit reload timer has the following functions:
• The count clock can be selected from three internal clocks and external event clocks.
• A software trigger or external trigger can be selected as the start trigger.
• If the 16-bit timer register (TMR) underflows, an interrupt can be generated to the
CPU.The 16-bit reload timer can be used as an interval timer by using an interrupt.
• If the TMR underflows, either the one-shot mode for stopping the TMR count
operation, or the reload mode for reloading the value of the 16-bit reload register
(TMRLR) to the TMR to continue the TMR count operation can be selected.
• The hardware interrupt corresponds to the EI2OS.
• MB90895 series has two channels of 16-bit reload timers.
■ Operation Modes of 16-bit Reload Timer
Table 8.1-1 indicates the operation modes of the 16-bit reload timer.
Table 8.1-1 Operation Modes of 16-bit Reload Timer
Count Clock
Start Trigger
Operation Performed upon
Underflow
Internal clock mode
Software trigger
External trigger
One-shot mode
Reload mode
Event count mode
Software trigger
One-shot mode
Reload mode
■ Internal clock mode
• When the count clock select bits in the timer control status register (TMCSR: CSL1, CSL0) are set to
"00B", "01B" or "10B", the 16-bit reload timer is set in the internal clock mode.
• In the internal clock mode, the 16-bit reload timer decrements in synchronization with the internal clock.
• The count clock select bits in the timer control status register (TMCSR: CSL1, CSL0) can be used to
select three count clock cycles.
• The start trigger sets the edge detection for a software trigger or an external trigger.
246
CHAPTER 8 16-bit RELOAD TIMER
■ Event count mode
• When the count clock select bits in the timer control status register (TMCSR: CSL1, CSL0) are set to
"11B", the 16-bit reload timer is set to the event count mode.
• In the event count mode, the 16-bit reload timer decrements in synchronization with the edge detection
of the external event clock input to the TIN pin.
• A software trigger is selected as the start trigger.
• The 16-bit reload timer can be used as an interval timer by using a fixed cycle of the external clock.
247
CHAPTER 8 16-bit RELOAD TIMER
■ Operation at Underflow
When the start trigger is input, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit
timer register, starting decrementing in synchronization with the count clock.When the 16-bit timer register
(TMR) is decremented from "0000H" to "FFFFH", an underflow occurs.
• When an underflow occurs with an underflow interrupt enabled (TMCSR: INTE = 1), an underflow
interrupt is generated.
• The TMRLR operation when an underflow occurs is set by the reload select bit in the timer control
status register (TMCSR: RELD).
(One-shot mode (TMCSR: RELD = 0))
When an underflow occurs, the TMR count operation is stopped.When the next start trigger is input, the
value set in the TMRLR is reloaded in the TMR, starting the TMR count operation.
• In the one-shot mode, during the TMR count operation, a High-level or Low-level rectangular wave is
output from the TOT pin.
• The pin output level select bit in the timer control status register (TMCSR: OUTL) can be set to select
the level (High or Low) of the rectangular wave.
(Reload mode (TMCSR: RELD = 1))
When an underflow occurs, the value set in the TMRLR is reloaded to the TMR, continuing the TMR count
operation.
• In the reload mode, a toggle wave inverting the output level of the TOT pin is output each time an
underflow occurs during the TMR count operation.
• The pin output level select bit in the timer control status register (TMCSR: OUTL) can be set to select
the level (High or Low) of a toggle wave.
• The 16-bit reload timer can be used as an interval timer by using an underflow interrupt.
Table 8.1-2 Interval Time of 16-bit Reload Timer
Count Clock
Internal clock mode
Event count mode
Count Clock Cycle
Interval Time
21T (0.125μs)
0.125μs to 8.192ms
23T (0.5μs)
0.5μs to 32.768ms
25T (2.0μs)
2.0μs to 131.1ms
23T or more
0.5μs or more
T: Machine cycle
The values in Interval time and the parenthesized values are provided when the machine clock operates
at 16 MHz.
Reference:
248
The 16-bit reload timer 1 can be used as the clock input source of the UART1 and
the start trigger of the A/D converter.
CHAPTER 8 16-bit RELOAD TIMER
8.2
Block Diagram of 16-bit Reload Timer
The 16-bit reload timers 0 and 1 composed of the following seven blocks:
• Count clock generator
• Reload controller
• Output controller
• Operation controller
• 16-bit timer register (TMR)
• 16-bit reload register (TMRLR)
• Timer control status register (TMCSR)
■ Block Diagram of 16-bit Reload Timer
Figure 8.2-1 Block Diagram of 16-bit Reload Timer
Internal data bus
TMRLR
16-bit reload register
Reload signal
Reload
control circuit
TMR
16-bit timer register UF
CLK
Count clock generating circuit
Machine
clock
φ
Prescaler 3
Gate
input
Valid
clock
judge
circuit
Wait signal
Output control
circuit
Output to
internal
peripheral
function
Output signal
generating circuit
Pin
Clear
Input
control
circuit
Pin
TIN
Internal
clock
Clock
selector
External
clock
3
CLK
2
Functional selection
-
-
-
TOT
EN
Select
signal
Operating
control circuit
- CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG
Timer control status register (TMCSR)
Interrupt request
output
249
CHAPTER 8 16-bit RELOAD TIMER
● Details of Pins in Block Diagram
There are two channels for 16-bit reload timer.
The actual pin names, outputs to resources, and interrupt request numbers for each channel are as follows:
16-bit reload timer 0:
TIN pin: P20/TIN0
TOT pin: P21/TOT0
Interrupt request number: #17 (11H)
16-bit reload timer 1:
TIN pin: P22/TIN1
TOT pin: P23/TOT1
Output to resources: Clock input source of UART1 and start trigger of A/D converter
Interrupt request number: #36 (24H)
● Count clock generator
The count clock generator generates a count clock supplied to the 16-bit timer register (TMR) on the basis
of the machine clock or external event clock.
● Reload controller
When the 16-bit reload timer starts operation or the TMR underflows, the reload controller reloads the
value set in the 16-bit reload register (TMRLR) to the TMR.
● Output controller
The output controller inverts and enables or disables the output of the TOT pin at underflow.
● Operation controller
The operation controller starts or stops the 16-bit reload timer.
● 16-bit timer register (TMR)
The 16-bit timer register (TMR) is a 16-bit down counter.At read, the value being counted is read.
● 16-bit reload register (TMRLR)
The 16-bit reload register (TMRLR) sets the interval time of the 16-bit reload timer.When the 16-bit reload
timer starts operation or the TMR underflows, the reload controller reloads the value set in the 16-bit reload
register (TMRLR) to the TMR.
250
CHAPTER 8 16-bit RELOAD TIMER
● Timer control status register (TMCSR)
The timer control status register (TMCSR) selects the operation mode, sets the operation conditions, selects
the start trigger, performs a start using the software trigger, selects the reload operation mode, enables or
disables an interrupt request, sets TOT pin output level, and sets TOT output pin.
251
CHAPTER 8 16-bit RELOAD TIMER
8.3
Configuration of 16-bit Reload Timer
This section explains the pins, registers, and interrupt factors of the 16-bit reload timer.
■ Pins of 16-bit Reload Timer
The pins of the 16-bit reload timer serve as general-purpose I/O ports.Table 8.3-1 shows the pin functions
and the pin settings required to use the 16-bit reload timer.
Table 8.3-1 Pins of 16-bit Reload Timer
Pin Function
Pin Setting Required for Use in 16-bit
Reload Timer
TIN0
General-purpose I/O port,
16-bit reload timer input
Set as input port in port direction register
(DDR).
TOT0
General-purpose I/O port,
16-bit reload timer output
Set timer output enable.
(TMCSR0: OUTE=1)
TIN1
General-purpose I/O port,
16-bit reload timer input
Set as input port in port direction register
(DDR).
TOT1
General-purpose I/O port,
16-bit reload timer output
Set timer output enable.
(TMCSR1: OUTE=1)
Pin Name
■ Block Diagram for Pins of 16-bit Reload Timer
Note:
252
For the block diagram of the pins, see "CHAPTER 4 I/O PORT".
CHAPTER 8 16-bit RELOAD TIMER
■ List of Registers and Reset Values of 16-bit Reload Timer
● Registers of 16-bit reload timer 0
Figure 8.3-1 List of Registers and Reset Values of 16-bit Reload Timer 0
bit
Timer control status register
upper (TMCSR0)
bit
Timer control status register
lower (TMCSR0)
bit
16-bit timer register upper
(TMR0)
bit
16 timer register lower
(TMR0)
bit
16-bit reload register upper
(TMRLR0)
bit
16-bit reload register lower
(TMRLR0)
15
14
13
12
11
10
9
8
×
×
×
×
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
× : Undefined
● Registers of 16-bit reload timer 1
Figure 8.3-2 List of Registers and Reset Values of 16-bit Reload Timer
bit
Timer control status register
upper (TMCSR1)
bit
Timer control status register
lower (TMCSR1)
bit
16-bit timer register upper
(TMR1)
bit
16-bit timer register lower
(TMR1)
bit
16-bit reload register upper
(TMRLR1)
bit
16-bit reload register lower
(TMRLR1)
15
14
13
12
11
10
9
8
×
×
×
×
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
× : Undefined
253
CHAPTER 8 16-bit RELOAD TIMER
■ Generation of Interrupt Request from 16-bit Reload Timer
When the 16-bit reload timer is started and the count value of the 16-bit timer register is decremented from
"0000H" to "FFFFH", an underflow occurs.When an underflow occurs, the UF bit in the timer control status
register is set to "1" (TMCSR: UF). If an underflow interrupt is enabled (TMCSR: INTE = 1), an interrupt
request is generated.
254
CHAPTER 8 16-bit RELOAD TIMER
8.3.1
Timer Control Status Registers (High) (TMCSR0: H,
TMCSR1: H)
The timer control status registers (High) (TMCSR0: H, TMCSR1: H) set the operation
mode and count clock.
This section also explains the bit 7 in the timer control status registers (Low) (TMCSR0:
L, TMCSR1: L).
■ Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H)
Figure 8.3-3 Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H)
15
14
13
12
-
-
-
-
11
10
9
8
7
Reset value
XXXX00000B
R/W R/W R/W R/W R/W
bit9
bit8
bit7
MOD2 MOD1 MOD0
0
0
0
0
1
1
0
0
1
1
×
×
0
1
0
1
0
1
bit9
bit8
bit7
MOD2 MOD1 MOD0
×
×
×
×
0
0
1
1
0
1
0
1
Operating mode select bit (internal clock mode)
(CSL1,0=00B, 01B, 10B)
Valid edge, level
Input pin function
Torigger disabled
Torigger input
Gate input
Rising edge
Falling edge
Both edge
"L" level
"H" level
Operating mode select bit (Event count mode)
(CSL1,0=11B)
Valid edge
Input pin function
Torigger input
Rising edge
Falling edge
Both edge
bit11 bit10
CSL1 CSL0
R/W
X
-
: Read/Write
: Undefined
: Unused
: Reset value
Count clock select bit
Count clock cycle
Count clock
21T
Internal clock mode
23T
25T
Event count mode
External event clock
0
0
0
1
1
0
1
1
T : Machine cycle
255
CHAPTER 8 16-bit RELOAD TIMER
Table 8.3-2 Functions of Timer Control Status Registers (High) (TMCSR0: H, TMCSR1: H)
bit name
bit15
to
bit12
Unused bits
Read: The value is undefined.
Write: No effect
bit11,
bit10
CSL1, CSL0:
Count clock selection
bits
These bits select the count clock of the 16-bit reload timer.
When set to anything other than "11B":
The edge of the external event clock is counted (internal
count mode)
When set to "11B": The edge of the external event clock is
counted (event count mode)
MOD2, MOD1, MOD0:
Operation mode select
bits
These bits set the operation conditions of the 16-bit reload timer.
(Internal clock mode)
The MOD2 bit is used to select the function of the input pin.
When MOD2 bit set to "0":
The input pin functions as a trigger input.
The MOD1 and MOD0 bits are used to select the edge to be
detected.When the edge is detected, the value set in the 16-bit
reload register (TMRLR) is reloaded in the 16-bit timer
register (TMR), starting the count operation of the TMR.
When MOD2 set to "1":
The input pin functions as a gate input.
The MOD1 bit is not used.The MOD0 bit is used to select the
signal level (High or Low) to be detected.The count operation
of the 16-bit timer register (TMR) is performed only when the
signal level is input.
(Event count mode)
The MOD2 bit is not used.An external event clock is input from
the input pin.The MOD1 and MOD0 bits are used to select the
edge to be detected.
bit9
to
bit7
256
Function
CHAPTER 8 16-bit RELOAD TIMER
8.3.2
Timer Control Status Registers (Low) (TMCSR0: L,
TMCSR1: L)
The timer control status registers (Low) (TMCSR0: L, TMCSR1: L) enables or disables
the timer operation, checks the generation of a software trigger or an underflow,
enables or disables an underflow interrupt, selects the reload mode, and sets the output
of the TOT pin.
■ Timer Control Status Registers (Low) (TMCSR0: L, TMCSR1: L)
Figure 8.3-4 Timer Control Status Registers (Low) (TMCSR0: L, TMCSR1: L)
7
6
5
4
3
2
1
0
Reset value
*
00000000B
R/W R/W R/W R/W R/W R/W R/W
bit0
TRG
0
1
bit1
CNTE
0
1
Software trigger bit
No effect
After reload, starting-up count operation
Timer operation enable bit
Timer operation disabled
Timer operation enabled (waiting start-up trigger)
bit2
UF
0
1
Under flow generating flag bit
Write
Read
Without under flow
With under flow
Clear UF bit
No effect
bit3
INTE
0
1
Under flow interrupt enable bit
Under flow interrupt disabled
Under flow interrupt enabled
bit4
RELD
0
1
One-shot mode
Reload mode
Reload select bit
bit5
TOT pin output level select bit
OUTL
0
1
One-shot mode
(RELD=0)
High rectangular wave output
during counting
Low rectangular wave output
during counting
Reloaad mode
(RELD=1)
Low toggle output at starting
reload timer
High toggle output at starting
reload timer
bit6
OUTE
0
R/W
*
Pin function
TOT pin output enable bit
Register and pin support for channel
TMCSR0
TMCSR1
General purpose I/O port
General purpose I/O port General purpose I/O port
: Read/Write
1
TOT output
TOT0
: Reset value
: Refer to "8.3.1 Timer Control Status Registers High" about MOD0 (bit 7).
TOT1
257
CHAPTER 8 16-bit RELOAD TIMER
Table 8.3-3 Timer Control Status Registers (Low) (TMCSR0: L, TMCSR1: L)
bit name
258
Function
bit6
OUTE:
TOT Output enable bit
This bit sets the function of the TOT pin of the 16-bit reload
timer.
When set to "0": Functions as general-purpose I/O port
When set to "1": Functions TOT as pin of 16-bit reload timer
bit5
OUTL:
TOT Pin output level
select bit
This bit sets the output level of the output pin of the 16-bit
reload timer.
<One-shot mode (RELD = 0)>
When set to "0": Outputs High-level rectangular wave during
TMR count operation
When set to "1": Outputs Low-level rectangular wave during
TMR count operation
<Reload mode (RELD = 1)>
When set to "0": Outputs Low-level toggle wave when reload
timer started
When set to "1": Outputs High-level toggle wave when 16-bit
reload timer started
bit4
RELD:
Reload select bit
This bit sets the reload operation at underflow.
When set to "1": At underflow, reloads value set in TMRLR to
TMR, continuing count operation (reload
mode)
When set to "0": At underflow, stops count operation (one-shot
mode)
bi3
INTE:
Underflow interrupt
enable bit
This bit enables or disables an under flow interrupt.
When an underflow occurs (TMCSR: UF = 1) with an
underflow interrupt enabled (TMCSR: INTE = 1), an interrupt
request is generated.
bit2
UF:
Underflow generation
flag bit
This bit indicates that the TMR underflows.
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
Read by read modify write instructions: "1" read
bit1
CNTE:
Timer operation enable
bit
This bit enables or disables the operation of the 16-bit reload
timer.
When set to "1": 16-bit reload timer enters start trigger wait
state.When the start trigger is input, the timer
register restarts count operation.
When set to "0": Stops count operation
bit0
TRG:
Software trigger bit
This bit starts the 16-bit reload timer by software.
The software trigger function works only when the timer
operation is enabled (CNTE = 1).
When set to "0": Disabled.The state remains unchanged.
When set to "1": Reloads value set in 16-bit reload register
(TMRLR) to 16-bit timer register (TMR),
starting TMR count operation "1".
Read: "0" is always read.
CHAPTER 8 16-bit RELOAD TIMER
8.3.3
16-bit Timer Registers (TMR0, TMR1)
The 16-bit timer registers (TMR0, TMR1) are 16-bit down counters.At read, the value
being counted is read.
■ 16-bit Timer Registers (TMR0, TMR1)
Figure 8.3-5 16-bit Timer Registers (TMR0, TMR1)
15
TMR0
TMR1
14
D15 D14
R
TMR0
TMR1
R
X
: Read only
: Undefined
13
12
D13
D12 D11 D10
R
R
11
R
10
R
9
8
D9
D8
R
R
R
Reset value
XXXXXXXXB
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R
R
R
R
R
R
R
R
Reset value
XXXXXXXXB
When the timer operation is enabled (TMCSR: CNTE = 1) and the start trigger is input, the value set in the
16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR), starting the TMR count
operation.
When the timer operation is disabled (TMCSR: CNTE = 0), the TMR value is retained.
When the TMR value is counted down from "0000H" to "FFFFH" during the TMR count operation, an
underflow occurs.
(Reload mode)
When the TMR underflows, the value set in the TMRLR is reloaded to the TMR, starting the TMR count
operation.
(One-shot mode)
When the TMR underflows, the TMR count operation is stopped, entering the start trigger input wait
state.The TMR value is retained to "FFFFH".
Notes:
• The TMR can be read during the TMR count operation. However, always use the
word instruction (MOVW).
• The TMR and the TMRLR are assigned to the same address.At write, the set
value can be written to the TMRLR without affecting the TMR.At read, the TMR
value being counted can be read.
259
CHAPTER 8 16-bit RELOAD TIMER
8.3.4
16-bit Reload Registers (TMRLR0, TMRLR1)
The 16-bit reload registers (TMRLR0, TMRLR1) set the value to be reloaded to the 16-bit
timer register (TMR).When the start trigger is input, the value set in the 16-bit reload
registers (TMRLR0, TMRLR1) is reloaded to the TMR, starting the TMR count operation.
■ 16-bit Reload Registers (TMRLR0, TMRLR1)
Figure 8.3-6 16-bit Reload Registers (TMRLR0, TMRLR1)
15
TMRLR0
TMRLR1
14
D15 D14
W
TMRLR0
TMRLR1
W
X
: Write only
: Undefined
13
12
D13
D12 D11 D10
W
W
11
W
10
W
W
9
8
D9
D8
W
W
Reset value
XXXXXXXXB
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
W
W
W
W
W
W
W
W
Reset value
XXXXXXXXB
Set the 16-bit reload registers (TMRLR0, TMRLR1) after disabling the timer operation (TMCSR: CNTE =
0).After completing setting of the 16-bit reload registers (TMRLR0, TMRLR1), enable the timer operation
(TMCSR: CNTE = 1).
When the start trigger is input, the value set in the TMRLR is reloaded to the TMR, starting the TMR count
operation.
Notes:
260
• Perform a write to the TMRLR after disabling the operation of the 16-bit reload
timer (TMCSR: CNTE = 0).Always use the word instruction (MOVW).
• The TMRLR and the TMR are assigned to the same address.At write, the set
value can be written to the TMRLR without affecting the TMR.At read, the TMR
value being counted is read.
• Instructions, such as the INC/DEC instruction, which provide the read modify write
(RMW) operation cannot be used.
CHAPTER 8 16-bit RELOAD TIMER
8.4
Interrupts of 16-bit Reload Timer
The 16-bit reload timer generates an interrupt request when the 16-bit timer register
(TMR) underflows.
■ Interrupts of 16-bit Reload Timer
When the value of the TMR is decremented from "0000H" to "FFFFH" during the TMR count operation, an
underflow occurs.When an underflow occurs, the underflow generation flag bit in the timer control status
register (TMCSR: UF) is set to "1".If an underflow interrupt is enabled (TMCSR: INTE = 1), an interrupt
request is generated.
Table 8.4-1 Interrupt Control Bits and Interrupt Factors of 16-bit Reload Timer
16-bit reload timer 0
16-bit reload timer 1
Interrupt request flag bit
TMCSR0: UF
TMCSR1: UF
Interrupt request flag bit
TMCSR0: INTE
TMCSR1: INTE
Interrupt Factor
Underflow in TMR0
Underflow in TMR1
■ Correspondence between 16-bit Reload Timer Interrupt and EI2OS
Note:
For details of the interrupt number, interrupt control register, and interrupt vector
address, see "Section 3.5 Interrupt".
■ EI2OS Function of 16-bit Reload Timer
The 16-bit reload timer corresponds to the EI2OS function. An underflow in the TMR starts the EI2OS.
Note however, that EI2OS can be used only when any other peripheral resources sharing the interrupt
control register (ICR) is not using interrupts.When using the EI2OS in the 16-bit reload timers 0 and 1, it is
necessary to disable generation of interrupt requests by resources sharing the interrupt control register
(ICR) with the 16-bit reload timers 0 and 1.
261
CHAPTER 8 16-bit RELOAD TIMER
8.5
Explanation of Operation of 16-bit Reload Timer
This section explains the setting of the 16-bit reload timer and the operation state of the
counter.
■ Setting of 16-bit Reload Timer
● Setting of internal clock mode
Counting the internal clock requires the setting shown in Figure 8.5-1.
Figure 8.5-1 Setting of internal clock mode
bit15 14
TMCSR
-
-
13
12
-
-
11
10
9
8
7
6
5
4
3
2
1
bit0
CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG
1
Other than "11B"
Setting reload value to 16-bit timer register
TMRLR
: Using bit
1 : Setting to "1"
● Setting of Event Counter Mode
Inputting an external event to operate the 16-bit reload timer requires the setting shown in Figure 8.5-2.
Figure 8.5-2 Setting of Event Count Mode
bit15 14
TMCSR
-
-
13
12
-
-
11
9
8
7
6
5
4
3
2
1
1
1
Setting reload value to 16-bit timer register
Set the bit of DDR(port direction register) corresponding to the pin to be used as TIN pin to "0".
: Using bit
1 : Setting to "1"
262
bit0
CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG
1
TMRLR
10
CHAPTER 8 16-bit RELOAD TIMER
■ Operating State of 16-bit Timer Register
The operating state of the 16-bit timer register is determined by the timer operation enable bit in the timer
control status register (TMCSR: CNTE) and the WAIT signal.The operating states include the stop state,
start trigger input wait state (WAIT state), and RUN state.
Figure 8.5-3 shows the state transition diagram for the 16-bit timer registers.
Figure 8.5-3 State Transition Diagram
STOP state CNTE=0, WAIT=1
TIN pin : Input disabled
TOT pin : General purpose I/O port
Reset
16-bit timer register : Hold the value at stop
Immediatelp after a reset,
the value is undefined.
CNTE=0
CNTE=0
CNTE=1
TRG=0
CNTE=1
TRG=1
WAIT state CNTE=1, WAIT=1
TIN pin : Valid for trigger input only
RUN state
TOT pin : Output value of 16-bit
reload register
16-bit timer register : Hold value at stop
A time until loading, the value is undefined.
TRG=1
(software trigger)
External trigger from TIN
WAIT
TRG
CNTE
UF
RELD
CNTE=1, WAIT=0
TIN pin : Function as input pin of
16-bit reload timer
UF=1 &
RELD=0
(one-shot mode)
LOAD
TOT pin : Function as output pin of
16-bit reload timer
UF=1 & 16-bit timer register : Operation
RELD=1
(reload mode)
TRG=1
CNTE=1, WAIT=0
Load the contents of 16-bit reload
register to 16-bit timer register
(software trigger)
Finish loading
: State transmission by hardware
: State transmission by register access
: WAIT signal (internal signal)
: Software trigger bit (TMCSR)
: Timer operating enable bit (TMCSR)
: Under flow generating flag bit (TMCSR)
: Reload select bit (TMCSR)
263
CHAPTER 8 16-bit RELOAD TIMER
8.5.1
Operation in Internal Clock Mode
In the internal clock mode, three operation modes can be selected by setting the
operation mode select bits in the timer control status register (TMCSR: MOD2 to
MOD0).When the operation mode and reload mode are set, a rectangular wave or a
toggle wave is output from the TOT pin.
■ Setting of internal clock mode
• By setting the count clock select bits (CSL1, CSL0) in the timer control status register to "00B", "01B",
"10B", the 16-bit reload timer (TMRLR) is set to the internal clock mode.
• In the internal clock mode, the 16-bit timer register (TMR) decrements in synchronization with the
internal clock.
• In the internal clock mode, three count clock cycles can be selected by setting the count clock select bits
in the timer control status register (TMCSR: CSL1, CSL0).
[Setting a reload value to TMR]
After the 16-bit reload timer is started, the value set in the TMRLR is reloaded to the TMR.
1. Disables the timer operation (TMCSR: CNTE = 0).
2. Sets a reload value to the TMR in the TMRLR.
3. Enables the timer operation (TMCSR: CNTE = 1).
Note:
264
It takes 1 machine cycle (time) to load the value set in the TMRLR to the TMR after
the start trigger is input.
CHAPTER 8 16-bit RELOAD TIMER
■ Operation as 16-bit Timer Register Underflows
When the value of the 16-bit timer register (TMR) is decremented from "0000H" to "FFFFH" during the
TMR count operation, an underflow occurs.
• When an underflow occurs, the underflow generation flag bit in the timer control status register
(TMCSR: UF) is set to "1".
• When an underflow occurs, the underflow generation flag bit in the timer control status register
(TMCSR: UF) is set to "1".
• The reload operation when an underflow occurs is set by the reload select bit in the timer control status
register (TMCSR: RELD).
[One-shot mode (TMCSR: RELD = 0)]
When an underflow occurs, the count operation of the TMR is stopped, entering the start trigger input wait
state.When the next start trigger is input, the TMR count operation is restarted.
In the one-shot mode, a rectangular wave is output from the TOT pin during the TMR count operation.The
pin output level select bit in the timer control status register (TMCSR: OUTL) can be set to select the level
(High or Low) of a rectangular wave.
[Reload mode (TMCSR: RELD = 1)]
When an underflow occurs, the value set in the 16-bit reload timer register (TMRLR) is reloaded to the
TMR, continuing the TMR count operation.
In the reload mode, a toggle wave inverting the output level of the TOT pin is output each time an
underflow occurs during the TMR count operation.The pin output level select bit in the timer control status
register (TMCSR: OUTL) can be set to select the level (High or Low) of a toggle wave as the 16-bit reload
timer is started.
■ Operation in Internal Clock Mode
In the internal clock mode, the operation mode select bits in the timer control status register (TMCSR:
MOD2 to MOD0) can be used to select the operation mode.Disable the timer operation by setting the timer
operation enable bit in the timer control status register (TMCSR: CNTE).
[Software trigger mode (MOD2 to MOD0 =000B)]
If the software trigger mode is set, start the 16-bit reload timer by setting the software trigger bit in the
timer control status register (TMCSR: TRG) to 1.When the 16-bit reload timer is started, the value set in
the TMRLR is reloaded to the TMR, starting the TMR count operation.
Note:
When both the timer operation enable bit in the timer control status register (TMCSR:
CNTE) and the software trigger bit in the timer control status register (TMCSR: TRG)
are set to "1", the 16-bit reload timer and the count operation of the TMR are started
265
CHAPTER 8 16-bit RELOAD TIMER
Figure 8.5-4 Count Operation in Software Trigger Mode (One-shot Mode)
Count clock
Reload
data
Counter
-1
Reload
data
0000H FFFFH
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
T*
TOT pin
Activating trigger input waite
T : Machine cycle
* : It takes 1T time from trigger input to loading data of reload register.
Figure 8.5-5 Count Operation in Software Trigger Mode (Reload Mode)
Count clock
Reload
data
Counter
-1
0000H Reload
data
-1
0000H Reload
data
-1
Data load signal
UF bit
CNTE bit
TRG bit
T*
TOT pin
T : Machine cycle
* : It takes 1T time from trigger input to loading data of reload register.
266
0000H Reload
data
-1
CHAPTER 8 16-bit RELOAD TIMER
[External trigger mode (MOD2 to MOD0 = 001B, 010B, 011B)]
When the external trigger mode is set, the 16-bit reload timer is started by inputting the external valid edge
to the TIN pin.When the 16-bit reload timer is started, the value set in the TMRLR is reloaded to the TMR,
starting the TMR count operation.
• By setting the operation mode select bits in the timer control status register (TMCSR: MOD2 to
MOD0), the detected edge can be selected from the rising edge, falling edge, and both edges.
Note:
The trigger pulse width of the edge to be input to the TIN pin should be 2 machine
cycles (time) or more.
Figure 8.5-6 Count Operation in External Trigger Mode (One-shot Mode)
Count clock
Reload
data
Counter
-1
Reload
data
0000H FFFFH
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TIN bit
2T to 2.5T *
TOT pin
Activating trigger input wait
T : Machine cycle
* : It takes from 2T to 2.5T time from trigger input to loading data of reload register.
Figure 8.5-7 Count Operation in External Trigger Mode (Reload Mode)
Count clock
Reload
data
Counter
-1
0000H Reload
data
-1
0000H Reload
data
-1
0000H Reload
data
-1
Data load signal
UF bit
CNTE bit
TIN bit
2T to 2.5T *
TOT pin
T : Machine cycle
* : It takes from 2T to 2.5T time from trigger input to loading data of reload register.
267
CHAPTER 8 16-bit RELOAD TIMER
[External gate input mode (MOD2 to MOD0 = 1x0B, 1x1B)]
When the external gate input mode is set, start the 16-bit reload timer by setting the software trigger bit in
the timer control status register (TMCSR: TRG) to "1".When the 16-bit reload timer is started, the value set
in the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR).
• After the 16-bit reload timer is started, the count operation of the TMR is performed while the set gate
input level is input to the TIN pin.
• The gate input level (High or Low) can be selected by setting the operation mode select bits in the timer
control status register (TMCSR: MOD2 to MOD0).
Figure 8.5-8 Count Operation in External Gate Input Mode (One-shot Mode)
Count clock
Reload data
Counter
-1
-1
0000H
FFFFH
Reload
data
-1
-1
Data load signal
UF bit
CNTE bit
TRG bit
T*
T*
TIN pin
TOT pin
Activating trigger input wait
T : Machine cycle
* : It takes 1T time from trigger input to loading data of reload register.
Figure 8.5-9 Count Operation in External Gate Input Mode (Reload Mode)
Count clock
Counter
Reload data
-1
-1
-1
0000H Reload
data
-1
-1
Data load signal
UF bit
CNTE bit
TRG bit
T*
TIN pin
TOT pin
T : Machine cycle
* : It takes 1T time from trigger input to loading data of reload register.
268
CHAPTER 8 16-bit RELOAD TIMER
8.5.2
Operation in Event Count Mode
In the event count mode, after the 16-bit reload timer is started, the edge of the signal
input to the TIN pin is detected to perform the count operation of the 16-bit timer
register (TMR).When the operation mode and reload mode are set, a rectangular wave
or a toggle wave is output from the TOT pin.
■ Setting of Event Count Mode
• The 16-bit reload timer (TMRLR) is placed in the event count mode by setting the count clock select
bits in the timer control status register (TMCSR: CSL1, CSL0) to "11B".
• In the event count mode, the TMR decrements in synchronization with the edge detection of the external
event clock input to the TIN pin.
[Setting reset value of counter]
After the 16-bit reload timer is started, the value set in the TMRLR is reloaded to the TMR.
1. Disables the operation of the 16-bit reload timer (TMCSR: CNTE = 0).
2. Sets a reload value to the TMR in the TMRLR.
3. Enables the operation of the 16-bit reload timer (TMCSR: CNTE = 1).
Note:
It takes 1 machine cycle (time) to load the value set in the TMRLR to the TMR after
the start trigger is input.
269
CHAPTER 8 16-bit RELOAD TIMER
■ Operation as 16-bit Timer Register Underflows
When the value of the 16-bit timer register (TMR) is decremented from "0000H" to "FFFFH" during the
TMR count operation, an underflow occurs.
• When an underflow occurs, the underflow generation flag bit in the timer control status register
(TMCSR: UF) is set to "1".
• When an underflow occurs, the underflow generation flag bit in the timer control status register
(TMCSR: UF) is set to "1".
• The reload operation when an underflow occurs is set by the reload select bit in the timer control status
register (TMCSR: RELD).
[One-shot mode (TMCSR: RELD = 0)]
When an underflow occurs, the count operation of the TMR is stopped, entering the start trigger input wait
state.When the next start trigger is input, the TMR count operation is restarted.
In the one-shot mode, a rectangular wave is output from the TOT pin during the TMR count operation.The
pin output level select bit in the timer control status register (TMCSR: OUTL) can be set to select the level
(High or Low) of a rectangular wave.
[Reload mode (TMCSR: RELD = 1)]
When an underflow occurs, the value set in the 16-bit reload timer register (TMRLR) is reloaded to the
TMR, continuing the TMR count operation.
In the reload mode, a toggle wave inverting the output level of the TOT pin is output each time an
underflow occurs during the TMR count operation.The pin output level select bit in the timer control status
register (TMCSR: OUTL) can be set to select the level (High or Low) of a toggle wave as the 16-bit reload
timer is started.
270
CHAPTER 8 16-bit RELOAD TIMER
■ Operation in Event Count Mode
The operation of the 16-bit reload timer is enabled by setting the timer operation enable bit in the timer
control status register (TMCSR: CNTE) to "1".When the software trigger bit in the timer control status
register (TMCSR: TRG) is set to "1", the 16-bit reload timer is started.When the 16-bit reload timer is
started, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR),
starting the TMR count operation.After the 16-bit reload timer is started, the edge of the external event
clock input to the TIN pin is detected to perform the TMR count operation.
• By setting the operation mode select bits in the timer control status register (TMCSR: MOD2 to
MOD0), the detected edge can be selected from the rising edge, falling edge, and both edges.
Note:
The level width of the external event clock signal input to the TIN pin should be at
least 4 T (T: machine cycle).
Figure 8.5-10 Count Operation in Event Count Mode (One-shot Mode)
TIN pin
Reload
data
Counter
-1
Reload
data
0000H FFFFH
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
T*
TOT pin
Activating trigger input wait
T : Machine cycle
* : It takes 1T time from trigger input to loading data of reload register.
Figure 8.5-11 Count Operation in Event Count Mode (Reload Mode)
TIN pin
Reload
data
Counter
-1
0000H Reload
data
-1
0000H Reload
data
-1
0000H Reload
data
-1
Data load signal
UF bit
CNTE bit
TRG bit
T*
TOT pin
T : Machine cycle
* : It takes 1T time from trigger input to loading data of reload register.
271
CHAPTER 8 16-bit RELOAD TIMER
8.6
Precautions when Using 16-bit Reload Timer
This section explains the precautions when using the 16-bit reload timer.
■ Precautions when Using 16-bit Reload Timer
● Precautions when using programs to set timebase timer
• Set the 16-bit reload register (TMRLR) after disabling the timer operation (TMCSR: CNTE = 0)
• The 16-bit timer register (TMR) can be read during the TMR count operation. However, always use the
word instruction (MOVW).
• Change the CSL1 and CSL0 bits in the TMCSR after disabling the timer operation (TMCSR: CNTE =
0)
● Precautions on interrupt
• When the UF bit in the TMCSR is set to "1" and the underflow interrupt output is enabled (TMCSR:
INTE = 1), it is impossible to return from interrupt processing.However, when the EI2OS is used, the
UF bit is cleared automatically.
• When using the EI2OS in the 16-bit reload timer, it is necessary to disable generation of interrupt
requests by resources that share the interrupt control register (ICR) with the 16-bit reload timer.
272
CHAPTER 8 16-bit RELOAD TIMER
8.7
Program Example of 16-bit Reload Timer
This section gives a program example of the 16-bit reload timer operated in the internal
clock mode and the event count mode are given below:
■ Program Example in Internal Clock Mode
● Processing specification
• The 25-ms interval timer interrupt is generated by the 16-bit reload timer 0.
• The repeated interrupts are generated in the reload mode.
• The timer is started using the software trigger instead of the external trigger input.
• EI2OS is not used.
• The machine clock is 16 MHz; the count clock is 2 μs.
● Coding example
ICR03
EQU
0000B3H
;For 16-bit reload timer
;Interrupt control register
TMCSR0 EQU 000066H
;Timer control status register
TMR0
EQU 003900H
;16-bit timer register
TMRLR0 EQU 003900H
;16-bit reload register
UF0
EQU TMCSR0:2
;Interrupt request flag bit
CNTE0 EQU TMCSR0:1
;Counter operation enable bit
TRG0
EQU TMCSR0:0
;Software trigger bit
;--------Main program-----------------------------------CODE
CSEG
;
:
;Stack pointer (sp),already initialized
AND
MOV
CLRB
MOVW
MOVW
CCR,#0BFH
;Interrupt disabled
I:ICR03,#00H
;Interrupt level 0 (storongest)
I:CNTE0
;Temporary stop of counter
I:TMRLR0,#30D3H ;Setting of data in 25ms timer
I:TMCSR0,#0000100000011011B
;Interval timer operation, clock 2ms
;External triger disabled,
External output disabled,
;Reload mode selection, interrupt enabled
;Clear interrupt flag, count start
ILM,#07H
;Setting ILM in PS to level7
CCR,#40H
;Interrupt enaled
MOV
OR
LOOP:
.
User processing
.
BRA LOOP
;
273
CHAPTER 8 16-bit RELOAD TIMER
;---------Interrupt program----------------------------------WARI:
CLR I:UF0
;Clear interrupt request flag
.
.
User processing
.
.
RETI
;Recovery from interrupt
CODE
ENDS
;---------Vector setting---------------------------------------VECT
CSEG ABS=0FFH
ORG 00FFB8H
;Setting vector to interrupt #17(11H)
DSL WARI
ORG 00FFDCH
;Reset vector setting
DSL START
DB
00H
;Setting to single chip mode
VECT
ENDS
END START
■ Program Example in Event Counter Mode
● Processing specification
• An interrupt is generated when rising edges of the pulse input to the external event input pin are counted
10000 times by the 16-bit reload timer/counter.
• Operation is performed in the one-shot mode.
• The rising edge is selected for the external trigger input.
• EI2OS is not used.
● Coding example
ICR03
EQU
;For 16-bit reload timer
;Interrupt control register
TMCSR0 EQU 000066H
;Timer control status register
TMR0
EQU 003900H
;16-bit timer register
TMRLR0 EQU 003900H
;16-bit reload register
DDR2
EQU 000012H
;Port data register
UF0
EQU TMCSR0:2
;Interrupt request flag bit
CNTE0 EQU TMCSR0:1
;Counter operating enable bit
TRG0
EQU TMCSR0:0
;Software trigger bit
;---------Main program----------------------------------CODE
CSEG
;
:
;Stack pointer (sp),already initialized
AND
MOV
274
0000B3H
CCR,#0BFH
I:ICR03,#00H
;Interrupt disabled
;Interrupt level 0 (strongesut)
CHAPTER 8 16-bit RELOAD TIMER
MOV
CLRB
MOVW
MOVW
MOV
OR
I:DDR2,00H
;Setting P20/TIN0 pin to input
I:CNTE0
;Temporary stop of counter
I:TMRLR0,#2710H;Reload value set to 10000 times
I:TMCSR0,#0000110000001011B
;Counter operating, external trigger, rising
;edge, external output disabled
;One-shot mode selection, interrupt enabled
;Clear interrupt flag, count start
ILM,#07H
;Setting ILM in PS to level 7
CCR,#40H
;Interrupt enabled
LOOP:
.
User processing
.
BRA
LOOP
;
;---------Interrupt program----------------------------------WARI:
CLR
I:UF0
;Clear interrupt request flag
.
.
User processing
.
.
RETI
;Recovery from interrupt
CODE ENDS
;---------Vector setting---------------------------------------VECT CSEG ABS=0FFH
ORG
00FFB8H
;Setting vector to interrupt #17(11H)
DSL
WARI
ORG
00FFDCH
;Reset vector setting
DSL
START
DB
00H
;Setting to single chip mode
VECT ENDS
END
START
275
CHAPTER 8 16-bit RELOAD TIMER
276
CHAPTER 9
WATCH TIMER
This section describes the functions and operations of
the watch timer.
9.1 Overview of Watch Timer
9.2 Block Diagram of Watch Timer
9.3 Configuration of Watch Timer
9.4 Watch Timer Interrupt
9.5 Explanation of Operation of Watch Timer
9.6 Program Example of Watch Timer
277
CHAPTER 9 WATCH TIMER
9.1
Overview of Watch Timer
The watch timer is a 15-bit free-run counter that increments in synchronization with the
sub clock.
• Seven interval times can be selected and an interrupt request can be generated for
each interval time.
• An operation clock can be supplied to the oscillation stabilization wait time timer of
the sub clock and the watchdog timer.
• The sub clock is always used as a count clock regardless of the settings of the clock
select register (CKSCR).
■ Interval Timer Function
• 'When the watch timer reaches the interval time set by the interval time select bits (WTC: WTC2 to
WTC0), the bit corresponding to the interval time of the watch timer counter overflows carries and the
overflow flag bit is set (WTC: WTOF = 1).
• When the overflow flag bit is set (WTC: WTOF = 1) with interrupt enabled when an overflow occurs
(WTC: WTIE = 1), an interrupt request is generated.
• The interval time of the watch timer can be selected from seven types. The interval time of the watch
timer can be selected from seven types shown in Table 9.1-1.
Table 9.1-1 Interval Times of Watch Timer
Sub clock Cycle
Interval Time
28/SCLK (31.25ms)
29/SCLK (62.5ms)
210/SCLK (125ms)
211/SCLK (250ms)
1/SCLK (122μs)
212/SCLK (500ms)
213/SCLK (1.0s)
214/SCLK (2.0s)
215/SCLK (4.0s)
SCLK: Sub clock frequency
The parenthesized values are provided when the sub clock operates at 8.192 kHz.
278
CHAPTER 9 WATCH TIMER
■ Cycle of Clock Supply
The watch timer supplies an operation clock to the oscillation stabilization wait time timer of the sub clock
and the watchdog timer.Table 9.1-2 shows the cycles of clocks supplied from the watch timer.
Table 9.1-2 Cycle of Clock Supply from Watch Timer
Receiver of clock supply
Timer for oscillation stabilization wait time of
sub clock
Clock Cycle
214/SCLK (2.000s)
210/SCLK (125ms)
213/SCLK (1.000s)
Watchdog timer
214/SCLK (2.000s)
215/SCLK (4.000s)
SCLK: Sub clock frequency
The parenthesized values are provided when the sub clock operates at 8.192 kHz.
279
CHAPTER 9 WATCH TIMER
9.2
Block Diagram of Watch Timer
The watch timer consists of the following blocks:
• Watch timer counter
• Counter clear circuit
• Interval timer selector
• Watch timer control register (WTC)
■ Block Diagram of Watch Timer
Figure 9.2-1 Block Diagram of Watch Timer
To watchdog timer
Watch timer counter
SCLK
× 21 × 22 × 23 × 24 × 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215
OF OF OF
OF
Power-on reset
Hardware standby transmission
Stop mode transmission
OF
OF
OF
OF
Counter
clear
circuit
To subclock
oscillation stabilization
waiting time
Interval timer
selector
Watch timer interrupt
OF
: Over flow
SCLK : Subclock
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
Wa tch timer control regis ter (WTC)
The actual interrupt request number of the watch timer is as follows:
Interrupt request number: #28 (1CH)
● Watch timer counter
The watch timer counter is a 15-bit up counter that uses the sub clock (SCLK) as a count clock.
● Counter clear circuit
The counter-clear circuit clears the watch timer counter.
280
CHAPTER 9 WATCH TIMER
● Interval timer selector
The interval timer selector sets the overflow flag bit when the watch timer counter reaches the interval time
set in the watch timer control register (WTC).
● Watch timer control register (WTC)
The watch timer control register (WTC) selects the interval time, clears the watch timer counter, enables or
disables an interrupt, checks the overflow state, and clears the overflow flag bit.
281
CHAPTER 9 WATCH TIMER
9.3
Configuration of Watch Timer
This section explains the registers and interrupt factors of the watch timer.
■ List of Registers and Reset Values of Watch Timer
Figure 9.3-1 List of Registers and Reset Values of Watch Timer
bit
Watch timer control register (WTC)
7
6
5
4
3
2
1
0
1
×
0
0
0
0
0
0
× : Undefined
■ Generation of Interrupt Request from Watch Timer
• When the interval time set by the interval time select bits (WTC: WTC2 to WTC0) is reached, the
overflow flag bit (WTC: WTOF) is set to "1".
• When the overflow flag bit is set (WTC: WTOF = 1) and with interrupt enabled when the watch timer
counter overflows (carries) (WTC: WTIE = 1), an interrupt request is generated.
282
CHAPTER 9 WATCH TIMER
9.3.1
Watch timer control register (WTC)
This section explains the functions of the watch timer control register (WTC).
■ Watch timer control register (WTC)
Figure 9.3-2 Watch timer control register (WTC)
7
6
5
4
3
2
1
0
Reset value
1X001000B
R/W
R
R/W R/W R/W R/W R/W R/W
bit2 bit1 bit0
WTC2 WTC1 WTC0
Interval time select bit
0
0
0
28/SCLK (31.25ms)
0
0
1
29/SCLK (62.5ms)
0
1
0
210/SCLK (125ms)
0
1
1
211/SCLK (250ms)
1
0
0
212/SCLK (500ms)
1
0
1
213/SCLK (1.0s)
1
1
0
214/SCLK (2.0s)
1
1
1
215/SCLK (4.0s)
bit3
WTR
0
1
Watch timer clear bit
Read
Write
"1" is always read.
Clear watch timer counter
No effection
bit4
WTOF
over flow flag bit
Read
Write
0
Without over flow of corresponding
bit within setting interval time
Clear WTOF bit
1
With over flow of corresponding bit
within setting interval time
No effection
bit5
Over flow interrupt enable bit
WTIE
Interrupt request disabled
0
Interrupt request enabled
1
bit6
SCE
0
1
Oscillation stabilization waiting time finish bit
Oscillation stabilization waiting state
Oscillation stabilization waiting time finish
bit7
WDCS
Watchdog clock select bit
(Input clock of watchdog timer)
R/W : Read/Write
Main of PLL clock mode
R
: Read only
0
Watch timer
X
: Undefined
Time base timer
1
SCLK : Subclock
: Reset value
The values in "()" are the calculated example at subclock = 8.192 kHz.
Sub clock mode
Set "0".
283
CHAPTER 9 WATCH TIMER
Table 9.3-1 Functions of Watch Timer Control Register (WTC)
bit name
284
Function
bit7
WDCS:
Watchdog clock select
bit
This bit selects the operation clock of the watchdog timer.
<Main clock mode or PLL clock mode>
When set to "0": Selects output of watch timer as operation
clock of watchdog timer.
When set to "1": Selects output of timebase timer as operation
clock of watchdog timer.
<Sub clock mode>
Always set this bit to "0" to select the output of the watch timer.
Note:
The watch timer and the timebase timer operate
asynchronously. When the WDCS bit is changed from "0" to
"1", the watchdog timer may run fast.The watchdog timer
must be cleared before and after changing the WDCS bit.
bit6
SCE:
Oscillation stabilization
wait time end bit
This bit indicates that the oscillation stabilization wait time of
the sub clock ends.
When cleared to "0": Sub clock in oscillation stabilization wait
state.
When set to "1": Sub clock oscillation stabilization wait time
ends.
• The oscillation stabilization wait time of the sub clock is
fixed at 214/SCLK (SCLK: sub clock frequency).
bit5
WTIE:
Overflow interrupt
enable bit
This bit enables or disables generation of an interrupt request
when the watch timer counter overflows (carries).
When set to "0": Interrupt request not generated even at
overflow (WTOF = 1).
When set to "1": Interrupt request generated at overflow
(WTOF = 1).
bit4
WTOF:
Overflow flag bit
This bit is set to "1" when the counter value of the watch timer
reaches the value set by the interval time select bit.
When an overflow occurs (WTOF = 1) with interrupt request
enabled (WTIE = 1), an interrupt request is generated.
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
• The overflow flag bit is set to "1" when the bit of the watch
timer counter corresponding to the interval time set by the
interval time select bits (WTC2 to WTC0) overflows.
bit3
WTR:
Watch timer clear bit
This bit clears the watch timer counter.
When set to "0": Clears watch timer counter to "0000H".
When the bit is set to "1": No effect.
Read: "1" is always read.
bit2
to
bit0
WTC2, WTC1, WTC0:
Interval time select bits
These bits set the interval time of the watch timer.
• When the interval time set by the WTC2 to WTC0 bits is
reached, the corresponding bit of the watch timer counter
overflows (carries) and the overflow flag bit is set (WTC:
WTOF = 1).
• To set the WTC2 to WTC0 bits, set the WTOF bit to "0".
CHAPTER 9 WATCH TIMER
9.4
Watch Timer Interrupt
When the interval time is reached with the watch timer interrupt enabled, the overflow
flag bit is set to "1" and an interrupt request is generated.
■ Watch Timer Interrupt
Table 9.4-1 shows the interrupt control bits and interrupt factors of the watch timer.
Table 9.4-1 Interrupt Control Bits of Watch Timer
Watch timer
Interrupt Factor
Interval time of watch timer counter
Interrupt request flag bit
WTC:WTOF (overflow flag bit)
Interrupt factor enable bit
WTC: WTIE
• When the value set by the interval time select bits (WTC2 to WTC0) in the watch timer control register
(WTC) is reached, the overflow flag bit in the WTC register is set to "1" (WTC: WTOF = 1).
• When the overflow flag bit is set (WTC: WTOF = 1) with the watch timer interrupt enabled (WTC:
WTIE = 1), an interrupt request is generated.
• At interrupt processing, set the WTOF bit to "0" and cancel the interrupt request.
■ Watch Timer Interrupt and EI2OS Function
• The watch timer does not correspond to the EI2OS function.
• For details of the interrupt number, interrupt control register, and interrupt vector address, see "3.5
Interrupt".
285
CHAPTER 9 WATCH TIMER
9.5
Explanation of Operation of Watch Timer
The watch timer operates as an interval timer or an oscillation stabilization wait time
timer of the sub clock.It also supplies an operation clock to the watchdog timer.
■ Watch timer counter
The watch timer counter continues incrementing in synchronization with the sub clock (SCLK) while the
sub clock (SCLK) is operating.
● Clearing watch timer counter
The watch timer counter is cleared to "0000H" when:
• Power on reset
• The mode transits to the stop mode.
• The watch timer clear bit (WTR) in the watch timer control register (WTC) is set to "0".
Note:
When the watch timer counter is cleared, the interrupts of the watchdog timer and
interval timer that use the output of the watch timer counter are affected.
Before clearing the watch timer by setting the watch timer clear bit (WTR) in the
watch timer control register (WTC), set the overflow interrupt enable bit (WTIE) in the
WTC register to disable the watch timer for interrupts.Before enabling interrupts, set
the WTC overflow flag bit (WTOF) to clear the interrupt request.
■ Interval Timer Function
The watch timer can be used as an interval timer by generating an interrupt at each interval time.
● Settings when using watch timer as interval timer
Operating the watch timer as an interval timer requires the settings shown in Figure 9.5-1.
Figure 9.5-1 Setting of Watch Timer
bit7
WTC
: Used bit
× : Unused bit
6
5
4
3
2
1
bit0
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
×
×
• When the value set by the interval time select bits (WTC1, WTC0) in the watch timer control register
(WTC) is reached, the overflow flag bit in the WTC register is set to "1" (WTC: WTOF = 1).
• When the overflow flag bit is set (WTC: WTOF = 1) with the overflow interrupt of the watch timer
counter enabled (WTC: WTIE = 1), an interrupt request is generated.
286
CHAPTER 9 WATCH TIMER
• The overflow flag bit (WTC: WTOF) is set when the interval time is reached at the starting point of the
timing at which the watch timer is finally cleared.
● Clearing overflow flag bit (WTC: WTOF)
When the mode is switched to the stop mode, the watch timer is used as an oscillation stabilization wait
time timer of sub clock. The WTOF bit is cleared concurrently with mode switching.
■ Setting Operation Clock of Watchdog Timer
The watchdog clock select bit (WDCS) in the watch timer control register (WTC) can be used to set the
clock input source of the watchdog timer.
When using the sub clock as the machine clock, always set the WDCS bit to "0" and select the output of the
watch timer.
■ Oscillation Stabilization Wait Time Timer of Sub clock
When the watch timer returns from the power-on reset and the stop mode, it functions as an oscillation
stabilization wait time timer of sub clock.
• The sub clock oscillation stabilization wait time is fixed at 214/SCLK (SCLK: sub clock frequency).
287
CHAPTER 9 WATCH TIMER
9.6
Program Example of Watch Timer
This section gives a program example of the watch timer.
■ Program Example of Watch Timer
● Processing specification
An interval interrupt at 213/SCLK (SCLK: sub clock) is generated repeatedly.The internal time is
approximately 1.0s (when sub clock operates at 8.192 kHz).
● Coding example
ICR07 EQU
0000B7H
;Interrupt control register
WTC
EQU
0000AAH
;Watch timer control register
WTOF
EQU
WTC:4
;Over flow flag bit
;
;---------Main program------------------------------------CODE
CSEG
START:
;
;Stack pointer (SP),already initialized
AND
MOV
MOV
CCR,#0BFH
I:ICR07,#00H
I:WTC,#10100101B
MOV
OR
ILM,#07H
CCR,#40H
;Interrupt disabled
;Interrupt level 0 (storngest)
;Interrupt enabled,
;Clear over flow flag
;Clear watch timer caunter,
;213/SCLK (approx.1.0s)
;Setting ILM in PS to level 7
;Interrupt enabled
LOOP:
.
User processing
.
BRA
LOOP
;---------Interrupt program-------------------------------------WARI:
CLRB I:WTOF
;Clear over flow flag
.
User processing
.
RETI
;Recovery from interrupt processing
CODE
ENDS
;---------Vector setting-----------------------------------------VECT
CSEG ABS=0FFH
ORG
00FF8CH
;Setting vector to interrupt number #28 (1CH)
DSL
WARI
ORG
00FFDCH
;Reset vector setting
DSL
START
DB
00H
;Setting to single chip mode
VECT
ENDS
END
START
288
CHAPTER 10
8/16-bit PPG TIMER
This section describes the functions and operations of
the 8-/16-bit PPG timer.
10.1 Overview of 8-/16-bit PPG Timer
10.2 Block Diagram of 8-/16-bit PPG Timer
10.3 Configuration of 8-/16-bit PPG Timer
10.4 Interrupts of 8-/16-bit PPG Timer
10.5 Explanation of Operation of 8-/16-bit PPG Timer
10.6 Precautions when Using 8-/16-bit PPG Timer
289
CHAPTER 10 8/16-bit PPG TIMER
10.1
Overview of 8-/16-bit PPG Timer
The 8-/16-bit PPG timer is a reload timer module with two channels (PPG0 and PPG1)
that outputs a pulse in any cycle and at any duty ratio.A combination of two channels
provides:
• 8-bit PPG output 2-channel independent operation mode
• 16-bit PPG output mode
• 8 + 8-bit PPG output mode
The MB90895 series has two 8-/16-bit PPG timers.This section explains the functions of
PPG0/1. PPG2/3 has the same functions as PPG0/1.
■ Functions of 8-/16-bit PPG Timer
The 8-/16-bit PPG timer consists of four eight-bit reload registers (PRLH0/PRLL0, PRLH1/PRLL1) and
two PPG down counters (PCNT0, PCNT1).
• Individual setting of High and Low widths in output pulse enables an output pulse of any cycle and duty
ratio.
• The count clock can be selected from six internal clocks.
• The 8-/16-bit PPG timer can be used as an interval timer by generating an interrupt request at each
interval time.
• An external circuit enables the 8-/16-bit PPG timer to be used as a D/A converter.
290
CHAPTER 10 8/16-bit PPG TIMER
■ Operation Modes of 8-/16-bit PPG Timer
● 8-bit PPG output 2-channel independent operation mode
The 8-bit PPG output 2-channel independent operation mode causes the 2-channel modules (PPG0 and
PPG1) to each operate as independent 8-bit PPG timers.
Table 10.1-1 shows the interval times in the 8-bit PPG output 2-channel independent operation mode.
Table 10.1-1 Interval Times in 8-bit PPG Output 2-channel Independent Operation Mode
PPG, CPPG1
Count Clock Cycle
Interval Time
Output Pulse Time
1/φ (62.5ns)
1/φ to 28/φ
2/ to 29/φ
2/φ (125ns)
2/φ to 29/φ
22/ to 210/φ
22/φ (250ns)
22/φ to 210/φ
23/φ to 211/φ
23/φ (500ns)
23/φ to 211/φ
24/φ to 212/φ
24/φ (1μs)
24/φ to 212/φ
25/φ to 213/φ
29/HCLK (128μs)
29/HCLK to 217/HCLK
210/HCLK to 218/HCLK
HCLK: Oscillation clock
φ: Machine clock
The parenthesized values are provided when the oscillation clock operates at 4 MHz and the machine
clock operates at 16 MHz.
● 16-bit PPG output mode
The 16-bit PPG output mode concatenates the 2-channel modules (PPG0 and PPG1) to operate as a 16-bit
1-channel PPG timer.
Table 10.1-2 Interval Times in 8+8-bit PPG Output Operation Mode shows the interval times in this mode.
Table 10.1-2 Interval Times in 16-bit PPG Output Operation Mode
Count Clock Cycle
Interval Time
Output Pulse Time
1/φ (62.5ns)
1/φ to 216/φ
2/φ to 217/φ
2/φ (125ns)
2/φ to 217/φ
22/φ to 218/φ
22/φ (250ns)
22/φ to 218/φ
23/φ to 219/φ
23/φ (500ns)
23/φ to 219/φ
24/φ to 220/φ
24/φ (1μs)
24/φ to 220/φ
25/φ to 221/φ
29/HCLK (128μs)
29/HCLK to 225/HCLK
210/HCLK to 226/HCLK
HCLK: Oscillation clock
φ: Machine clock
The parenthesized values are provided when the oscillation clock operates at 4 MHz and the machine
clock operates at 16 MHz.
291
CHAPTER 10 8/16-bit PPG TIMER
● 8 + 8-bit PPG output mode
The 8 + 8-bit PPG output mode causes the PPG0 of the 2-channel modules (PPG0 and PPG1) to operate as
an 8-bit prescaler and the underflow output of the PPG0 to operate as the count clock of the PPG1.
Table 10.1-3 Interval Times in 8+8-bit PPG Output Operation Mode shows the interval times in this mode.
Table 10.1-3 Interval Times in 8+8-bit PPG Output Operation Mode
PPG0
Count Clock
Cycle
PPG1
Interval Time
Output Pulse
Time
Interval Time
Output Pulse
Time
1/φ (62.5ns)
1/φ to 28/φ
2/φ to 29/φ
1/φ to 216/φ
2/φ to 217/φ
2/φ (125ns)
2/φ to 29/φ
22/φ to 210/φ
2/φ to 217/φ
22/φ to 218/φ
22/φ (250ns)
22/φ to 210/φ
23/φ to 211/φ
22/φ to 218/φ
23/φ to 219/φ
23/φ (500ns)
23/φ to 211/φ
24/φ to 212/φ
23/φ to 219/φ
24/φ to 220/φ
24/φ (1μs)
24/φ to 212/φ
25/φ to 213/φ
24/φ to 220/φ
25/φ to 221/φ
29/HCLK
(128μs)
29/HCLK to
217/HCLK
210/HCLK to
218/HCLK
29/HCLK to
225/HCLK
210/HCLK to
226/HCLK
Oscillation clock
φ: Machine clock
The parenthesized values are provided when the oscillation clock operates at 4 MHz and the machine
clock operates at 16 MHz.
292
CHAPTER 10 8/16-bit PPG TIMER
10.2
Block Diagram of 8-/16-bit PPG Timer
The MB90895 series contains two 8-/16-bit PPG timers (each with two channels).
One 8-/16-bit PPG timer consists of two channels of 8-bit PPG timers.
This section shows the block diagrams for the 8-/16-bit PPG timer 0 and 8-/16-bit PPG
timer 1.The PPG2 has the same function as the PPG0, and PPG3 has the same function
as PPG1.
■ Channels and PPG Pins of PPG Timers
Figure 10.2-2 shows the relationship between the channels and the PPG pins of the 8-/16-bit PPG timers in
the MB90895 series.
Figure 10.2-1 Channels and PPG Pins of PPG Timers
PPG0/1
Pin
PPG0 output pin
Pin
PPG1 output pin
PPG2/3
Pin
PPG2 output pin
Pin
PPG3 output pin
293
CHAPTER 10 8/16-bit PPG TIMER
10.2.1
Block Diagram for 8-/16-bit PPG Timer 0
The 8-/16-bit PPG timer 0 consists of the following blocks.
■ Block Diagram for 8-/16-bit PPG Timer 0
Figure 10.2-2 Block Diagram for 8-/16-bit PPG Timer 0
"H" level side data bus
"L" level side data bus
PPG0 reload
register
PRLH0
("H" level side)
PPG0 operating mode control register
(PPGC0)
PRLL0
("L" level side)
PEN0
-
PE0 PIE0 PUF0
PPG0 temporary
buffer 0 (PRLBH0)
-
-
Interrupt
request
output*
R
S
Q
2
Select signal
Reload register
L/H selector
Count starting
value
Reserved
Reload
Clear
Pulse selector
PPG0 down counter
(PCNT0)
Operating mode
control signal
PPG1 under flow
PPG0 under flow
(to PPG1)
Under flow
CLK
Inversion
PPG0
output latch
Pin
PPG0
PPG output control circuit
Time base timer output
(512/HCLK)
Peripheral clock (1/φ)
Peripheral clock (2/φ)
Peripheral clock (4/φ)
Peripheral clock (8/φ)
Peripheral clock (16/φ)
Count
clock
selector
3
Select signal
Reserved
HCLK
φ
*
294
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
: Unused
PPG0/1 count clock select register (PPG01)
: Reserved bit
: Oscillation clock frequency
: Machine clock frequency
: The interrupt output of 8-/16-bit PPG timer 0 is combined to one interrupt by
OR circuit with the interrupt request output of PPG timer 1.
-
CHAPTER 10 8/16-bit PPG TIMER
● Details of Pins in Block Diagram
Table 10.2-1 lists the actual pin names and interrupt request numbers of the 8-/16-bit PPG timer.
Table 10.2-1 Pins and Interrupt Request Numbers in Block Diagram
Channel
Output Pin
PPG0
P14/PPG0
PPG1
P15/PPG1
PPG2
P16/PPG2
PPG3
P17/PPG3
Interrupt Request Number
#22 (16H)
#26 (1AH)
● PPG operation mode control register 0 (PPGC0)
This register enables or disables operation of the 8-/16-bit PPG timer 0, the pin output, and an underflow
interrupt.It also indicates the occurrence of an underflow.
● PPG0/1 count clock select register (PPG01)
This register sets the count clock of the 8-/16-bit PPG timer 0.
● PPG0 reload registers (PRLH0 and PRLL0)
These registers set the High width or Low width of the output pulse. The values set in these registers are
reloaded to the PPG0 down counter (PCNT0) when the 8-/16-bit PPG timer 0 is started.
● PPG0 down counter (PCNT0)
This counter is an 8-bit down counter that alternately reloads the values set in the PPG0 reload registers
(PRLH0 and PRLL0) and counts down. The pin output is inverted when underflow occurs.This counter is
concatenated for use as a single-channel 16-bit PPG down counter.
● PPG0 temporary buffer (PRLBH0)
This buffer prevents deviation of the output pulse width caused at writing to the PPG reload registers
(PRLH0 and PRLL0).This buffer stores the PRLH0 value temporarily and enables it in synchronization
with the timing of writing to the PRLL0.
● Reload register L/H selector
This selector detects the current pin output level to select which register value, Low reload register
(PRLL0) or High reload register (PRLH0), should be reloaded to the PPG0 down counter.
● Count clock selector
This selector selects the count clock to be input to the PPG0 down counter from five frequency-divided
clocks of the machine clock or the frequency-divided clocks of the timebase timer.
● PPG output control circuit
This circuit inverts the pin output level and the output when an underflow occurs.
295
CHAPTER 10 8/16-bit PPG TIMER
10.2.2
Block Diagram of 8-/16-bit PPG Timer 1
The 8-/16-bit PPG timer 1 consists of the following blocks.
■ Block Diagram of 8-/16-bit PPG Timer 1
Figure 10.2-3 Block Diagram of 8-/16-bit PPG Timer 1
"H" side data bus
"L" side data bus
PPG1 operating mode control register
(PPGC1)
PPG1 reload
register
PRLH1
("H" side)
PRLL1
("L" side)
PEN1
-
PE1 PIE1 PUF1 MD1 MD0
Operating
mode control signal
S
Reload selector
L/H selector
Q
Select signal
Reload
Clear
Under
PPG1 down counter flow
(PCNT1)
PPG1 under flow
(to PPG0)
Interrupt
request
output*
R
PPG1 temporary
buffer (PRLBH1)
Count starting
value
Reserved
2
Inversion
PPG1
output latch
Pin
PPG1
CLK
PPG output control circuit
MD0
PPG0 under flow
Time base timer output
(from PPG0)
(512/HCLK)
Peripheral clock (1/φ)
Peripheral clock (2/φ)
Peripheral clock (4/φ)
Peripheral clock (8/φ)
Peripheral clock (16/φ)
Count
clock
selector
Reserved
HCLK
φ
*
296
3
Select signal
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
: Unused
PPG0/1 count clock select register (PPG01)
: Reserved bit
: Oscillation clock frequency
: Machine clock frequency
: The interrupt output of 8-/16-bit PPG timer 1 is combined to one interrupt by
OR circuit with the interrupt request output of PPG timer 0.
-
CHAPTER 10 8/16-bit PPG TIMER
● Details of pins in block diagram
Table 10.2-2 lists the actual pin names and interrupt request numbers of the 8-/16-bit PPG timer.
Table 10.2-2 Pins and Interrupt Request Numbers in Block Diagram
Channel
Output Pin
PPG0
P14/PPG0
PPG1
P15/PPG1
PPG2
P16/PPG2
PPG3
P17/PPG3
Interrupt Request Number
#22 (16H)
#26 (1AH)
● PPG operation mode control register 1 (PPGC1)
These bits set the operation mode of the 8-/16-bit PPG timer.This register sets the operation mode of the 8-/
16-bit PPG timer, enables or disables the operation of the 8-/16-bit PPG timer 1, the pin output and an
underflow interrupt, and also indicates the generation of an underflow. It also indicates the occurrence of an
underflow.
● PPG0/1 count clock select register (PPG01)
This register sets the count clock of the 8-/16-bit PPG timer 0.
● PPG1 reload registers (PRLH1 and PRLL1)
These registers set the High width or Low width of the output pulse.The values set in these registers are
reloaded to the PPG1 down counter (PCNT1) when the 8-/16-bit PPG timer 1 is started.
● PPG1 down counter (PCNT1)
This counter is an 8-bit down counter that alternately reloads the values set in the PPG1 reload registers
(PRLH1 and PRLL1) and counts down. The pin output is inverted when underflow occurs.This counter is
concatenated for use as a single-channel 16-bit PPG down counter.
● PPG1 temporary buffer (PRLBH1)
This buffer prevents deviation of the output pulse width caused at writing to the PPG reload registers
(PRLH1 and PRLL1).It stores the PRLH1 value temporarily and enables it in synchronization with the
timing of writing to the PRLL1.
● Reload register L/H selector
This selector detects the current pin output level to select which register value, Low reload register
(PRLL1) or High reload register (PRLH1), should be reloaded to the PPG1 down counter.
● Count clock selector
This selector selects the count clock to be input to the PPG1 down counter from five frequency-divided
clocks of the machine clock or the frequency-divided clocks of the timebase timer.
297
CHAPTER 10 8/16-bit PPG TIMER
● PPG output control circuit
This circuit inverts the pin output level and the output when an underflow occurs.
298
CHAPTER 10 8/16-bit PPG TIMER
10.3
Configuration of 8-/16-bit PPG Timer
This section explains the pins, registers and interrupt factors of the 8-/16-bit PPG timer.
■ Pins of 8-/16-bit PPG Timer
The pins of the 8-/16-bit PPG timer serve as general-purpose I/O ports. Table 10.3-1 indicates the pin
functions and pin settings required to use the 8-/16-bit PPG timer.
Table 10.3-1 Pins of 8-/16-bit PPG Timer
Channel
Pin Name
Pin Function
Pin Setting Required for Use of 8-/
16-bit PPG Timer
PPG0
PPG0 output pin
General-purpose I/O
ports/
PPG0 output pin
Set PPG0 pin output to enabled
(PPGC0: PE0=1)
PPG1
PPG1 output pin
General-purpose I/O
ports/
PPG1 output pin
Set PPG1 pin output to enabled
(PPGC1: PE1=1)
PPG2
PPG2 output pin
General-purpose I/O
ports/
PPG2 output pin
Set PPG2 pin output to enabled
(PPGC2: PE0=1)
PPG3
PPG3 output pin
General-purpose I/O
ports/
PPG3 output pin
Set PPG3 pin output to enabled
(PPGC3: PE1=1)
■ Block Diagram of 8-/16-bit PPG Timer Pins
Reference:
For the block diagram of the pins, see "CHAPTER 4 I/O PORT".
299
CHAPTER 10 8/16-bit PPG TIMER
■ List of Registers and Reset Values of 8-/16-bit PPG Timer
Figure 10.3-1 List of Registers and Reset Values of 8-/16-bit PPG Timer
bit
PPG0 operating mode control register
: H (PPGC1)
bit
PPG0 operating mode control register
: L (PPGC0)
bit
PPG0/1 count clock select register
(PPG01)
bit
PPG0 reload register : H (PRLH0)
bit
PPG0 reload register : L (PRLL0)
bit
PPG1 reload register : H (PRLH1)
bit
PPG1 reload register : L (PRLL1)
15
14
13
12
11
10
9
8
0
-
0
0
0
0
0
1
7
6
5
4
3
2
1
0
0
-
0
0
0
-
-
1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
×
×
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
× : Undefined
■ Generation of Interrupt Request from 8-/16-bit PPG Timer
In the 8-/16-bit PPG timer, the underflow generation flag bits in the PPG operation mode control registers
(PPGC0: PUF0, PPGC1: PUF1) are set to "1" when an underflow occurs.If the underflow interrupts of
channels causing an underflow are enabled (PPGC0: PIF0, PPGC1: PIF1), an underflow interrupt request is
generated to the interrupt controller.
300
CHAPTER 10 8/16-bit PPG TIMER
10.3.1
PPG0 Operation Mode Control Register (PPGC0)
The PPG0 operation mode control register (PPGC0) provides the following settings:
• Enabling or disabling operation of 8-/16-bit PPG timer
• Pin function switching (Enabling or disabling pulse output)
• Enabling or disabling underflow interrupt
• Setting underflow interrupt request flag
■ PPG0 Operation Mode Control Register (PPGC0)
Figure 10.3-2 PPG0 Operation Mode Control Register (PPGC0)
7
6
5
4
3
2
1
0
Reset value
0X000XX1B
R/W
-
R/W R/W R/W
-
-
W
bit0
Reserved
1
Reserved bit
Be sure to set to "1".
bit3
PUF0
0
1
Under flow generating flag bit
Read
Without under flow
With under flow
Write
Clear PUF0 bit
No effection
bit4
PIE0
Under flow interrupt enable bit
0
Interrupt request disabled
Interrupt request enabled
1
bit5
PE0
0
1
R/W : Read/Write
W
: Write only
X
: Undefined
: Unused
: Reset value
PPG0 pin output enable bit
General purpose I/O port (pulse output disabled)
PPG0 output (pulse output enabled)
bit7
PEN0
PPG0 operating enable bit
Count operating disabled (holding "L" level output)
0
Count operating inabled
1
301
CHAPTER 10 8/16-bit PPG TIMER
Table 10.3-2 Functions of PPG0 Operation Mode Control Register (PPGC0)
bit name
302
Function
bit7
PEN0:
PPG0 operation enable
bit
This bit enables or disables the count operation of the 8-/16-bit
PPG timer 0.
When set to "0": Count operation disabled.
When set to "1": Count operation enabled.
• When the count operation is disabled (PEN0 = 0), the output
is held at a Low level.
bit6
Unused bits
Read: The value is undefined.
Write: No effect.
bit5
PE0:
PPG0 pin output enable
bit
This bit switches the PPG0 pin function to enable or disable the
pulse output.
When set to "0": Functions as general-purpose I/O port.
The pulse output is disabled.
When set to "1": PPG0 pin functions as PPG0 output pin.
The pulse output is enabled.
bit4
PIE0:
Underflow interrupt
enable bit
This bit enables or disables an interrupt.
When set to "0": No interrupt request generated even at
underflow (PUF0 = 1).
When set to "1": Interrupt request generated at underflow
(PUF0 = 1).
bit3
PUF0:
Underflow generation
flag bit
8-bit PPG output 2-channel independent operation mode,
8+8-bit PPG output operation mode:
When the value of the PPG0 down counter is
decremented from "00H" to "FFH", an underflow occurs
(PUF0 = 1).
16-bit PPG output operation mode:
When the values of the PPG0 and PPG1 down counters
are decremented from "0000H" to "FFFFH", an
underflow occurs (PUF0 = 1).
• When an underflow occurs (PUF0 = 1) with an underflow
interrupt enabled (PIE0 = 1), an interrupt request is
generated.
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
Read by read modify write instructions: "1" read.
bit2,
bit1
Unused bits
Read: The value is undefined.
Write: No effect.
bit0
Reserved: reserved bit
Always set this bit to "1".
CHAPTER 10 8/16-bit PPG TIMER
10.3.2
PPG1 Operation Mode Control Register (PPGC1)
The PPG1 operation mode control register (PPGC1) provides the following settings:
• Enabling or disabling operation of 8-/16-bit PPG timer
• Pin function switching (Enabling or disabling pulse output)
• Enabling or disabling underflow interrupt
• Setting underflow interrupt request flag
• Enabling or disabling operation of 8-/16-bit PPG timer
■ PPG1 Operation Mode Control Register (PPGC1)
Figure 10.3-3 PPG1 Operation Mode Control Register (PPGC1)
15
14
13
12
11
10
9
8
Reset value
0X000001B
R/W
-
R/W R/W R/W R/W R/W
W
bit8
Reserved
1
Reserved bit
Be sure to set to "1".
bit10 bit9
MD1 MD0
0
0
0
1
1
0
1
1
8-bit PPG output 2ch independent operating mode
8+8-bit PPG output operating mode
Setting disabled
16-bit PPG output operating mode
Operating mode select bit
bit11
PUF1
0
1
Under flow generating flag bit
Read
Without under flow
With under flow
Write
Clear PUF1 bit
No effection
bit12
PIE1
Under flow interrupt enable bit
0
Under flow interrupt request disabled
1
Under flow interrupt request enabled
bit13
PE1
PPG1 pin output enable bit
0
General purpose I/O port (pulse output disabled)
1
PPG1 output (pulse output enabled)
R/W : Read/Write
W
: Write only
X
: Undefined
: Unused
: Reset value
bit15
PEN1
PPG1 operating enabled
Count operating disabled (holding "L" level output)
0
Count operating enabled
1
303
CHAPTER 10 8/16-bit PPG TIMER
Table 10.3-3 Functions of PPG1 Operation Mode Control Register (PPGC1)
bit name
304
Function
bit15
PEN1:
PPG1 operation enable
bit
This bit enables or disables the count operation of the 8-/16-bit
PPG timer 1.
When set to "0": Count operation disabled
When set to "1": Count operation enabled
• When the count operation is disabled (PEN1 = 0), the output
is held at a Low level.
bit14
Unused bits
Read: The value is undefined.
Write: No effect.
bit13
PE1:
PPG1 Pin output enable
bit
This bit switches the PPG1 pin function to enable or disable the
pulse output.
When set to "0": Functions as general-purpose I/O port
The pulse output is disabled.
When set to "1": PPG0 pin functions as PPG0 output pin.
The pulse output is enabled.
bit12
PIE1:
Underflow interrupt
enable bit
This bit enables or disables an interrupt.
When set to "0": No interrupt request is generated even at
underflow (PUF1 = 1)
When set to "1": Interrupt request is generated at underflow
(PUF1 = 1)
bit11
PUF1:
Underflow generation
flag bit
8-bit PPG output 2-channel independent operation mode,
8+8-bit PPG output operation mode:
When the value of the PPG1 down counter is
decremented from "00H" to "FFH", an underflow occurs
(PUF1 = 1).
16-bit PPG output operation mode:
When the values of the PPG0 and PPG1 down counters
are decremented from "0000H" to "FFFFH", an underflow
occurs (PUF1 = 1).
• When an underflow occurs (PUF1 = 1) with an underflow
interrupt enabled (PIE1 = 1), an interrupt request is generated.
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
Read by read modify write instructions: "1" read
bit10,
bit9
MD1, MD0:
Operation mode select
bits
These bits set the operation mode of the 8-/16-bit PPG timer.
(Any mode other than 8-bit PPG output 2-channel
independent operation mode)
• Use a word instruction to set the PPG operation enable bits
(PEN0 and PEN1) at one time.
• Do not set operation of only one of the two channels
(PEN1 = 0/PEN0 = 1 or PEN1 = 1/PEN0 = 0).
Note:
Do not set the MD1 and MD0 bits to "10B".
bit8
Reserved: reserved bit
Always set this bit to "1".
CHAPTER 10 8/16-bit PPG TIMER
10.3.3
PPG0/1 count clock select register (PPG01)
The PPG0/1 count clock select register (PPG01) selects the count clock of the 8-/16-bit
PPG timer.
■ PPG0/1 count clock select register (PPG01)
Figure 10.3-4 PPG0/1 count clock select register (PPG01)
7
6
5
4
3
2
1
0
Reset value
000000XXB
R/W R/W R/W R/W R/W R/W
-
bit4 bit3 bit2
PCM2 PCM1 PCM0
PPG0 counter clock select bit
0
0
0
1/φ (62.5ns)
0
0
1
2/φ (125ns)
0
1
0
22/φ (250ns)
0
1
1
23/φ (500ns)
1
0
0
24/φ (1 μs)
1
0
1
Setting disabled
1
1
0
Setting disabled
1
1
1
29/HCLK (128 μs)
R/W
X
-
bit7 bit6 bit5
PCS2 PCS1 PCS0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
0
1
1
1
0
1
1
1
1
: Read/Write
: Undefined
: Unused
: Reset value
HCLK : Oscillation clock
: Machine clock frequency
φ
HCLK=4MHz in ( ), value of operating at φ =16MHz
PPG1 counter clock select bit
1/φ (62.5ns)
2/φ (125ns)
22/φ (250ns)
23/φ (500ns)
24/φ (1 μs)
Setting disabled
Setting disabled
29/HCLK (128 μs)
305
CHAPTER 10 8/16-bit PPG TIMER
Table 10.3-4 Functions of PPG0/1 Count Clock Select Register (PPG01)
bit name
306
Function
bit7
to
bit5
PCS2 to PCS0:
PPG1 count clock select
bits
These bits set the count clock of the 8-/16-bit PPG timer 1.
• The count clock can be selected from five frequency-divided
clocks of the machine clock and the frequency-divided clocks
of the timebase timer.
• The settings of the PPG1 count clock select bits (PCS2 to
PCS0) are enabled only in the 8-bit PPG output 2-channel
independent mode (PPGC1: MD1, MD0 =00B).
bit4
to
bit2
PCM2 to PCM0:
PPG0 count clock select
bit
These bits set the count clock of the 8-/16-bit PPG timer 0.
• The count clock can be selected from five frequency-divided
clocks of the machine clock and the frequency-divided clocks
of the timebase timer.
bit1,
bit0
Undefined
Read: The value is undefined.
Write: No effect
CHAPTER 10 8/16-bit PPG TIMER
10.3.4
PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1)
The value (reload value) from which the PPG down counter starts counting is set in the
PPG reload registers.They are an 8-bit register at both Low level and at High level.
■ PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1)
Figure 10.3-5 PPG Reload Registers (PRLL0/PRLH0, PRLL1/PRLH1)
PRLH0/PRLH1
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
D15 D14
D8
D13
D12 D11 D10
D9
Reset value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reset value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
PRLL0/PRLL1
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Read/Write
X : Undefined
Table 10.3-5 indicates the functions of the PPG reload registers.
Table 10.3-5 Functions of PPG Reload Registers
Function
Notes:
8-/16-bit PPG Timer 0
8-/16-bit PPG Timer 1
Retains reload value on Lowlevel side
PRLL0
PRLL1
Retains reload value on Highlevel side
PRLH0
PRLH1
• In the 16-bit PPG output operation mode (PPGC1: MD1, MD0 = 11B), use a longword instruction to set the PPG reload registers or the word instruction to set the
PPG0 and PPG1 in this order.
• In the 8 + 8-bit PPG output operation mode (PPGC1: MD1, MD0 =01B), set the
same value in both the Low-level and High-level PPG reload registers (PRTLL0/
PRLH0) of the 8-/16-bit PPG timer 0.
Setting a different value in the Low-level and High-level PPG reload registers may
cause the 8-/16-bit PPG timer 1 to have different PPG output waveforms at each
clock cycle.
307
CHAPTER 10 8/16-bit PPG TIMER
10.4
Interrupts of 8-/16-bit PPG Timer
The 8-/16-bit PPG timer can generate an interrupt request when the PPG down counter
underflows.It corresponds to the EI2OS.
■ Interrupts of 8-/16-bit PPG Timer
Table 10.4-1 shows the interrupt control bits and interrupt factor of the 8-/16-bit PPG timer.
Table 10.4-1 The interrupt control bits of the 8-/16-bit PPG timer
PPG0
PPG1
Interrupt request flag bit
PPGC0: PUF0
PPGC1: PUF1
Interrupt request flag bit
PPGC0: PIE0
PPGC1: PIE1
Interrupt Factor
Underflow in PPG0 down
counter
Underflow in PPG1 down
counter
[8-bit PPG output 2-channel independent operation mode or 8 + 8-bit PPG output operation mode]
• In the 8-bit PPG output 2-channel independent operation mode or the 8 + 8-bit PPG output operation
mode, the PPG0 and PPG1 timers can generate an interrupt independently.
• When the value of the PPG0 or PPG1 down counter is decremented from "00H" to "FFH", an underflow
occurs.When an underflow occurs, the underflow generation flag bit in the channel causing an
underflow is set (PPGC0: PUF0 = 1 or PPGC1: PUF1 = 1).
• If an interrupt request from the channel that causes an underflow is enabled (PPGC0: PIE0 = 1 or
PPGC1: PIE1 = 1), an interrupt request is generated.
[16-bit PPG output operation mode]
• In the 16-bit PPG output operation mode, when the values of the PPG0 and PPG1 down counters are
decremented from "0000H" to "FFFFH", an underflow occurs.When an underflow occurs, the underflow
generation flag bits in the two channels are set at one time (PPGC0: PUF0 = 1 and PPGC1: PUF1 = 1).
• When an underflow occurs with either of the two channel of the interrupt requests enabled (PPGC0:
PIE1 = 0, PPGC1: PIE1 = 1 or PPGC0: PIE1 = 1, PPGC1: PIE1 = 0), an interrupt request is generated.
• To prevent duplication of interrupt requests, disable either of the two channel of the underflow interrupt
enable bits (PPGC0: PIE1 = 0, PPGC1: PIE1 = 1 or PPGC0: PIE1 = 1, PPGC1: PIE1 = 0).
• When the two channels of the underflow generation flag bits are set (PPGC0: PUF0 = 1 and PPGC1:
PUF1 = 1), clear the two channels at the same time.
308
CHAPTER 10 8/16-bit PPG TIMER
■ 8-/16-bit PPG Timer Interrupt and EI2OS
For details of the interrupt number, interrupt control register, and interrupt vector address, see 3.5 Interrupt.
■ 8-/16-bit PPG Timer Interrupt and EI2OS Function
The 8-/16-bit PPG timer corresponds to the EI2OS function. Generation of an enabled interrupt factor starts
the EI2OS.However, it is necessary to disable generation of interrupt requests by resources sharing the
interrupt control register (ICR) with the 8-/16-bit PPG timer.
309
CHAPTER 10 8/16-bit PPG TIMER
10.5
Explanation of Operation of 8-/16-bit PPG Timer
The 8-/16-bit PPG timer outputs a pulse width at any cycle and at any duty ratio
continuously.
■ Operation of 8-/16-bit PPG Timer
● Output operation of 8-/16-bit PPG timer
• The 8-/16-bit PPG timer has two (Low-level and High-level) 8-bit reload registers (PRLL0/PRLH0 and
PRLL1/PRLH1) for each channel.
• The values set in the 8-bit reload registers (PRLL0/PRLH0 and PRLL1/PRLH1) are reloaded alternately
to the PPG down counters (PCNT0 and PCNT1).
• After reloading the values in the PPG down counters, decrementing is performed in synchronization
with the count clocks set by the PPG count clock select bits (PPG01: PCM2 to PCM0 and PCS1 and
PCS0).
• If the values set in the reload registers are reloaded to the PPG down counters when an underflow
occurs, the pin output is inverted.
Figure 10.5-1 shows the output waveform of the 8-/16-bit PPG timer.
Figure 10.5-1 Output Waveform of 8-/16-bit PPG Timer
Operating start
Operating stop
PPG operating enable bit
(PEN)
PPG output pin
T × (L+1)
T × (H+1)
L : Value of PPG reload register (PRLL)
H : Value of PPG reload register (PRLH)
T : Count clock cycle
● Operation Modes of 8-/16-bit PPG Timer
As long as the operation of the 8-/16-bit PPG timer is enabled (PPGC0: PEN0 = 1, PPGC1: PEN1 = 1), a
pulse waveform is output continuously from the PPG output pin.A pulse width of any cycle and duty ratio
can be set.
The pulse output of the 8-/16-bit PPG timer is not stopped until operation of the 8-/16-bit PPG timer is
stopped (PPGC0: PEN0 = 0, PPGC1: PEN1 = 0).
• 8-bit PPG output 2-channel independent operation mode
• 16-bit PPG output mode
• 8 + 8-bit PPG output mode
310
CHAPTER 10 8/16-bit PPG TIMER
10.5.1
8-bit PPG output 2-channel independent operation mode
In the 8-bit PPG output 2-channel independent operation mode, the 8-/16-bit PPG timer
is set as an 8-bit PPG timer with two independent channels.PPG output operation and
interrupt request generation can be performed independently for each channel.
■ Setting for 8-bit PPG Output 2-channel Independent Operation Mode
Operating the 8-/16-bit PPG timer in the 8-bit PPG output 2-channel independent operation mode requires
the setting shown in Figure 10.5-2.
Figure 10.5-2 Setting for 8-bit PPG Output 2-channel Independent Operation Mode
bit15 14
PPGC1/PPGC0 PEN1
1
-
13
12
11
PE1 PIE1 PUF1
10
9
bit8 bit7
ReMD1 MD0 served
0
0
1
PEN0
6
-
5
4
3
PE0 PIE0 PUF0
2
1
bit0
-
-
Reserved
1
1
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
-
-
PPG01
(Reserved area)
PRLH0/PRLL0
Settting reload value of PPG0 "H" level side
Settting reload value of PPG0 "L" level side
PRLH1/PRLL1
Settting reload value of PPG1 "H" level side
Settting reload value of PPG1 "L" level side
: Used bit
- : Unused bit
1 : Setting "1"
0 : Setting "0"
Note:
Use the word instruction to set both High-level and Low-level PPG reload registers
(PRLL0/PRLH0 and PRLL1/PRLH1) at the same time.
● Operation in 8-bit PPG output 2-channel independent operation mode
• The 8-bit PPG timer with two channels performs an independent PPG operation.
• When the pin output is enabled (PPGC0: PE0 = 1, PPGC1: PE1 = 1), the PPG0 pulse wave is output
from the PPG0 pin and the PPG1 pulse wave is output from the PPG1 pin.
• When a reload value is set in the PPG reload register (PRLL0/PRLH0, PRLL1/PRLH1) and PPG timer
operation is enabled (PPGC0:PEN0=1, PPGC1:PEN1=1), the PPG down counter starts count operation
in the channel that enables operation.
• To stop the count operation of the PPG down counter, disable the operation of the PPG timer of the
channel to be stopped (PPGC0: PEN0 = 0, PPGC1: PEN1 = 0).The count operation of the PPG down
counter is stopped and the output of the PPG output pin is held at a Low level.
• When the PPG down counter of each channel underflows, the reload values set in the PPG reload
registers (PRLL0/PRLH0 and PRLL1/PRLH1) are reloaded to the PPG down counter that underflows.
311
CHAPTER 10 8/16-bit PPG TIMER
• When an underflow occurs, the underflow generation flag bit in the channel that causes an underflow is
set (PPGC0: PUF0 = 1, PPGC1: PUF1 = 1).If an interrupt request is enabled at the channel that causes
an underflow (PPGC0: PIE0 = 1, PPGC1: PIE1 = 1), the interrupt request is generated.
● Output waveform in 8-bit PPG output 2-channel independent operation mode
• The High and Low pulse widths to be output are determined by adding 1 to the value in the PPG reload
register and multiplying it by the count clock cycle.For example, if the value in the PPG reload register
is 00 H, the pulse width has one count clock cycle, and if the value is FF H, the pulse width has 256
count clock cycles.
The equations for calculating the pulse width are shown below:
PL=T × (L+1)
PH=T × (H+1)
PL: Low width of output pulse
PH: High width of output pulse
L: Values of 8 bits in PPG reload register (PRLL0 or PRLL1)
H: Values of 8 bits in PPG reload register (PRLH0 or PRLH1)
T: Count clock cycle
Figure 10.5-3 shows the output waveform in the 8-bit PPG output 2-channel independent operation mode.
Figure 10.5-3 Output waveform in 8-bit PPG output 2-channel independent operation mode
Operating start
Operating stop
PPG operating enable bit
(PEN)
PPG output pin
T × (L+1)
L : Value of PPG reload register (PRLL)
H : Value of PPG reload register (PRLH)
T : Count clock cycle
312
T × (H+1)
CHAPTER 10 8/16-bit PPG TIMER
10.5.2
16-bit PPG output mode
In the 16-bit PPG output operation mode, the 8-/16-bit PPG timer is set as a 16-bit PPG
timer with one channel.
■ Setting for 16-bit PPG Output Operation Mode
Operating the 8-/16-bit PPG timer in the 8+8-bit PPG output operation mode requires the setting shown in
Figure 10.5-4.
Figure 10.5-4 Setting for 16-bit PPG Output Operation Mode
bit15 14
PPGC1/PPGC0 PEN1
1
-
13
12
11
10
9
PE1 PIE1 PUF1 MD1 MD0
1
1
bit8 bit7
Reserved
PEN0
1
1
(Reserved area)
PPG01
-
5
4
3
PE0 PIE0 PUF0
2
1
bit0
-
-
Reserved
1
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
×
×
-
-
×
PRLH0/PRLL0
Settting reload value lower 8 bits of PPG0
"H" level side
Settting reload value lower 8 bits of PPG0
"L" level side
PRLH1/PRLL1
Settting reload value upper 8 bis of PPG1
"H" level side
Settting reload value upper 8 bits of PPG1 .
"L" level side
×
1
0
Note:
6
: Used bit
: Unused bit
: Undefined bit
: Setting "1"
: Setting "0"
Use a long-word instruction to set the values in the PPG reload registers or a word
instruction to set the PPG0 and PPG1 (PRLL0 → PRLL1 or PRLH0 → PRLH1) in
this order.
313
CHAPTER 10 8/16-bit PPG TIMER
● Operation in 16-bit PPG output operation mode
• When either PPG0 pin output or PPG1 pin output is enabled (PPGC0: PE0 = 1, PPGC1: PE1 = 1), the
same pulse wave is output from both the PPG0 and PPG1 pins.
• When a reload value is set in the PPG reload register (PRLL0/PRLH0, PRLL1/PRLH1) and a PPG timer
operation is also enabled (PPGC0:PEN0=1 and PPGC1:PEN1=1), the PPG down counter starts count
operation as a 16 - bit down counter (PCNT0 + PCNT1).
• To stop the count operation of the PPG down counters, disable the operation of the PPG timers of both
channels (PPGC0: PEN0 = 0 and PPGC1: PEN1 = 0).The count operation of the PPG down counter is
stopped and the output of the PPG output pin is held at a Low level.
• If the PPG1 down counter underflows, the reload values set in the PPG0 and PPG1 reload registers
(PRLL0/PRLH0 and PRLL1/PRLH1) are reloaded simultaneously to the PPG down counters (PCNT0 +
PCNT1).
• When an underflow occurs, the underflow generation flag bits in both channels are set simultaneously
(PPGC0: PUF0 = 1, PPGC1: PUF1 = 1). If an interrupt request is enabled at either channel (PPGC0:
PIE0 = 1, PPGC1: PIE1 = 1), an interrupt request is generated.
Notes:
314
• In the 16-bit PPG output operation mode, the underflow generation flag bits in the
two channels are set simultaneously when an underflow occurs (PPGC0: PUF0 =
1 and PPGC1: PUF1 = 1).To prevent duplication of interrupt requests, disable
either of the underflow interrupt enable bits in the two channels (PPGC0: PIE0 =
0, PPGC1: PIE1 = 1 or PPGC0: PIE0 = 1, PPGC1: PIE1 = 0).
• If the underflow generation flag bits in the two channels are set (PPGC0: PUF0 =
0 and PPGC1: PUF1 = 0), clear the two channels at the same time.
CHAPTER 10 8/16-bit PPG TIMER
● Output waveform in 16-bit PPG output operation mode
• The High and Low pulse widths to be output are determined by adding 1 to the value in the PPG reload
register and multiplying it by the count clock cycle.For example, if the value in the PPG reload register
is "0000H", the pulse width has one count clock cycle, and if the value is "FFFFH", the pulse width has
65,536 count clock cycles.
The equations for calculating the pulse width are shown below:
PL=T × (L+1)
PH=T × (H+1)
PL: Low width of output pulse
PH: High width of output pulse
L: Values of 16 bits in PPG reload register (PRLL0 + PRLL1)
H: Values of 16 bits in PPG reload register (PRLH0 + PRLH1)
T: Count clock cycle
Figure 10.5-5 shows the output waveform in the 8+8-bit PPG output operation mode.
Figure 10.5-5 Output waveform in 16-bit PPG output operation mode
Operating start
Operating stop
PPG operating enable bit
(PEN)
PPG output pin
T × (L+1)
T × (H+1)
L : 16-bit value of PPG reload register (PRLL1+PRLL0)
H : 16-bit value of PPG reload register (PRLH1+PRLH0)
T : Count clock cycle
315
CHAPTER 10 8/16-bit PPG TIMER
10.5.3
8 + 8-bit PPG output mode
The PPG0 operates as an 8-bit prescaler and the PPG1 operates using the PPG output
of the PPG0 as a clock source.
■ Setting for 8+8-bit PPG Output Operation Mode
Operating the 8-/16-bit PPG timer in the 8+8-bit PPG output operation mode requires the setting shown in
Figure 10.5-6.
Figure 10.5-6 Setting for 8+8-bit PPG Output Operation Mode
bit15 14
PPGC1/PPGC0 PEN1
1
-
13
12
11
10
9
PE1 PIE1 PUF1 MD1 MD0
0
1
bit8 bit7
Reserved
PEN0
1
1
(Reserved area)
PPG01
4
3
2
1
bit0
-
-
Reserved
1
×
-
-
×
PRLH0/PRLL0
Settting reload value of PPG0 "H" level side
Settting reload value of PPG0 "L" level side
PRLH1/PRLL1
Settting reload value of PPG1 "H" level side
Settting reload value of PPG1 "L" level side
×
1
0
316
-
5
PE0 PIE0 PUF0
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
×
Note:
6
: Used bit
: Unused bit
: Undefined bit
: Setting "1"
: Setting "0"
Use the word instruction to set both High-level and Low-level PPG reload registers
(PRLL0/PRLH0 and PRLL1/PRLH1) at the same time.
CHAPTER 10 8/16-bit PPG TIMER
● Operation in 8+8-bit PPG output operation mode
• The PPG0 operates as the prescaler of the PPG timer and the PPG1 operates using the PPG0 output as a
clock source.
• When the pin output is enabled (PPGC0: PE0 = 1, PPGC1: PE1 = 1), the PPG0 pulse wave is output
from the PPG0 pin and the PPG1 pulse wave is output from the PPG1 pin.
• When the reload value is set in the PPG reload registers (PRLL0/PRLH0, PRLL1/PRLH1) to enable
operation of the PPG timer (PPGC0: PEN0 = 1 and PPGC1: PEN1 = 1), the PPG down counter starts
counting.
• To stop the count operation of the PPG down counters, disable the operation of the PPG timers of both
channels (PPGC0: PEN0 = 0 and PPGC1: PEN1 = 0).The count operation of the PPG down counter is
stopped and the output of the PPG output pin is held at a Low level.
• When the PPG down counter of each channel underflows, the reload values set in the PPG reload
registers (PRLL0/PRLH0 and PRLL1/PRLH1) are reloaded to the PPG down counter that underflows.
• When an underflow occurs, the underflow generation flag bit in the channel that causes an underflow is
set (PPGC0: PUF0 = 1, PPGC1: PUF1 = 1).If an interrupt request is enabled at the channel that causes
an underflow (PPGC0: PIE0 = 1, PPGC1: PIE1 = 1), the interrupt request is generated.
Notes:
• Do not operate PPG1 (PPGC1: PEN1 = 1) when PPG0 is stopped (PPGC0: PEN0 = 0).
• It is recommended to set the same value in both Low-level and High-level PPG
reload registers (PRLL0/PRLH0, PRLL1/PRLH1).
317
CHAPTER 10 8/16-bit PPG TIMER
● Operation in 8+8-bit PPG output operation mode
• The High and Low pulse widths to be output are determined by adding 1 to the value in the PPG reload
register and multiplying it by the count clock cycle.
The equations for calculating the pulse width are shown below:
PL=T × (L0+1) × (L1+1)
PH=T × (H0+1) × (H1+1)
PL: Low width of output pulse of PPG1 pin
PH: High width of output pulse of PPG1 pin
L0: Values of 8 bits in PPG reload register (PRLL0)
H0: Values of 8 bits in PPG reload register (PRLH0)
L1: Values of 8 bits in PPG reload register (PRLL1)
H1: Values of 8 bits in PPG reload register (PRLH1)
T: Count clock cycle
Figure 10.5-7 shows the output waveform in the 8+8-bit PPG output operation mode.
Figure 10.5-7 Output Waveform in 8+8-bit PPG Output Operation Mode
Operating start
Operating stop
PPG operating enable bit
(PEN0, PEN1)
T × (L0+1)
T × (H0+1)
PPG0 output pin
PPG1 output pin
T × (L0+1) × (L1+1)
L0 : 8-bit value of PPG reload register (PRLL0)
H0 : 8-bit value of PPG reload register (PRLH0)
H1 : 8-bit value of PPG reload register (PRLL1)
L1 : 8-bit value of PPG reload register (PRLH1)
T : Count clock cycle
318
T × (H0+1) × (H1+1)
CHAPTER 10 8/16-bit PPG TIMER
10.6
Precautions when Using 8-/16-bit PPG Timer
Precautions when Using 8-/16-bit PPG Timer
■ Precautions when Using 8-/16-bit PPG Timer
● Effect on 8-/16-bit PPG timer when using timebase timer output
• If the output signal of the timebase timer is used as the input signal for the count clock of the 8-/16-bit
PPG timer (PPG01: PCM2 to PCM0 =111B, PCS2 to PCS0 =111B), deviation may occur in the first
count cycle in which the PPG timer is started
• When the timebase timer counter is cleared during the count operation of the PPG down counter,
deviation may occur in the count cycle.
● Setting of PPG reload registers when using 8-bit PPG timer
• The Low-level and High-level pulse widths are determined at the timing of reloading the values in the
Low-level PPG reload registers (PRLL0, PRLL1) to the PPG down counter.
• If the 8-bit PPG timer is used in the 8-bit PPG output 2-channel independent operation mode or the 8 +
8-bit PPG output operation mode, use a word instruction to set both High-level and Low-level PPG
reload registers (PRLL0/PRLH0, PRLL1/PRLH1) at the same
Using a byte instruction may cause an unexpected pulse to be generated.
[Example of rewriting PPG reload registers using byte instruction]
If you update the value in the High-level PPG reload register (PRLH) after updating the value in the Lowlevel PPG reload register (PRLL) using a byte instruction immediately before the signal level of the PPG
pin changes from High to Low, a Low-level pulse width is generated after updating and a High-level pulse
width is generated before updating only once.
Figure 10.6-1 shows the waveform as the values in the PPG reload registers are rewritten using the byte
instruction.
Figure 10.6-1 Waveform when Values in PPG Reload Registers Rewritten Using Byte Instruction
PRLL
A
PRLH
B
C
D
A+B
A+B
B+C
C+D
C+D Timing to
renew reload
value
C+D
PPG pin
A
<1>
<2>
B
A
B
C
B
C
D
C
D
<1> <2>
: To renew the value of PPG reload register (PRLL) (A → C)
: To renew the value of PPG reload register (PRLH) (B → D)
319
CHAPTER 10 8/16-bit PPG TIMER
● Setting of PPG reload registers when using 16-bit PPG timer
• Use a long-word instruction to set the PPG reload registers (PRLL0/PRLH0, PRLL1/PRLH1) or a word
instruction to set the word instruction to set the PPG0 and PPG1 (PRLL0 → PRLL1 or PRLH0 →
PRLH1) in this order.
[Reload timing in 16-bit PPG output operation mode]
In the 16-bit PPG output operation mode, the reload values written to the PPG0 reload registers (PRLL0/
PRLH0) are written temporarily to the temporary latch, written to the PPG1 reload registers (PRLL1/
PRLH1), and then transferred to the PPG0 reload register (PPLL0, PRLH0). Therefore, when setting the
reload value in the PPG1 reload registers (PRLL1/PRLH1), it is necessary to set the reload value in the
PPG0 reload registers (PRLL0/PRLH0) simultaneously or set the reload value in the PPG0 reload registers
(PRLL0/PRLH0) before setting PPG1 reload value.
Figure 10.6-2 shows the reload timing in the 16-bit PPG output operation mode.
Figure 10.6-2 Reload Timing in 16-bit PPG Output Operation Mode
Reload value
of PPG0
Only 16-bit PPG output operating mode
Writing to PPG0
other than 16-bit PPG
output operating mode
PPG reload register
(PRLL0, PRLH0)
320
Temporary latch
Reload value
of PPG1
Write to
PPG1
Synchronize with writing
to PPG1 and transmit
PPG reload register
(PRLL1, PRLH1)
CHAPTER 11
DELAYED INTERRUPT
GENERATION MODULE
This chapter explains the functions and operations of
the delayed interrupt generation module.
11.1 Overview of Delayed Interrupt Generation Module
11.2 Block Diagram of Delayed Interrupt Generation Module
11.3 Configuration of Delayed Interrupt Generation Module
11.4 Explanation of Operation of Delayed Interrupt Generation Module
11.5 Precautions when Using Delayed Interrupt Generation Module
11.6 Program Example of Delayed Interrupt Generation Module
321
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.1
Overview of Delayed Interrupt Generation Module
The delayed interrupt generation module generates the interrupt for task switching.
The hardware interrupt request can be generated/cancelled by software.
■ Overview of Delayed Interrupt Generation Module
By using the delayed interrupt generation module, a hardware interrupt request can be generated or
cancelled by software.
Table 11.1-1 Overview of Delayed Interrupt Generation Module
Function and Control
322
Interrupt Factor
An interrupt request is generated by setting the R0 bit in the delayed interrupt
request generate/cancel register to 1 (DIRR: R0 = 1).
An interrupt request is cancelled by setting the R0 bit in the delayed interrupt
request generate/cancel register to 0 (DIRR: R0 = 0).
Interrupt Number
#42 (2AH)
Interrupt Control
An interrupt is not enabled by the DIRR register.
Interrupt flag
The interrupt flag is held in the R0 bit in the DIRR register.
EI2OS
The DIRR register does not correspond to the EI2OS.
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.2
Block Diagram of Delayed Interrupt Generation Module
The delayed interrupt generation module consists of the following blocks:
• Interrupt request latch
• Delayed interrupt request generate/cancel register (DIRR)
■ Block Diagram of Delayed Interrupt Generation Module
Figure 11.2-1 Block Diagram of Delayed Interrupt Generation Module
Internal data bus
-
-
-
-
-
-
-
R0
Delay interrupt request generation/
release register (DIRR)
S Interrupt
request
R Latch
Interrupt
request
signal
- : Unused
● Interrupt request latch
This latch keeps the settings (delayed interrupt request generation or cancellation) of the delayed interrupt
request generate/cancel register (DIRR).
● Delayed interrupt request generate/cancel register (DIRR)
This bit generates or cancels a delayed interrupt request.
■ Interrupt Number
The interrupt number used in the delayed interrupt generation module is as follows:
Interrupt number #42 (2A H)
323
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.3
Configuration of Delayed Interrupt Generation Module
This section lists registers and reset values in the delayed interrupt generation module.
■ List of Registers and Reset Values
Figure 11.3-1 List of Registers and Reset Values in Delayed Interrupt Generation Module
bit
Delay interrupt request generation/
release register (DIRR)
× : Undefined
324
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
0
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.3.1
Delayed interrupt request generate/cancel register
(DIRR)
The delayed interrupt request generate/cancel register (DIRR) generates or cancels a
delayed interrupt request.
■ Delayed interrupt request generate/cancel register (DIRR)
Figure 11.3-2 Delayed interrupt request generate/cancel register (DIRR)
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
R/W
Reset value
XXXXXXX0B
bit8
: Unused
R/W : Read/Write
: Reset value
-
R0
0
1
Delay interrupt request generating bit
Release of delay interrupt request
Generation of delay interrupt request
Table 11.3-1 Functions of Delayed Interrupt Request Generate/Cancel Register (DIRR)
bit name
Function
bit15
to
bit9
Undefined
Read: The value is undefined.
Write: No effect
bit8
R0:
Delayed interrupt request
generate bit
This bit generates or cancels a delayed interrupt request.
When set to "0": Cancels delayed interrupt request
When set to "1": Generates delayed interrupt request
325
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.4
Explanation of Operation of Delayed Interrupt Generation
Module
The delayed interrupt generation module has a function for generating or canceling an
interrupt request by software.
■ Explanation of Operation of Delayed Interrupt Generation Module
Using the delayed interrupt generation module requires the setting shown in Figure 11.4-1.
Figure 11.4-1 Setting for Delayed Interrupt Generation Module
bit15 14
DIRR
-
13
12
11
10
-
-
-
-
-
9 bit8
-
R0
: Used bit
- : Unused bit
When the R0 bit in the delayed interrupt request generate/cancel register (DIRR) is set to "1" (DIRR: R0 =
1), an interrupt request is generated.
● Operation of delayed interrupt generation module
• When the R0 bit in the delayed interrupt request generate/cancel register (DIRR) is set to "1", the
interrupt request latch is set to "1" and an interrupt request is generated to the interrupt controller.
• An interrupt request is generated to the CPU when the interrupt controller prioritizes the interrupt
request over other requests.
• When the level of an interrupt request (ICR: IL) is higher to that of the interrupt level mask bit (ILM) in
the processor status (PS), the CPU delays interrupt processing until completion of execution of the
current instruction.
• At interrupt processing, the user program sets the R0 bit to 0 to cancel the interrupt request and performs
task switching.
Figure 11.4-2 Operation of Delayed Interrupt Generation Module
Delay interrupt generating module
Other
request
DIRR
Interrupt controller
ICR YY
CPU
IL
CMP
CMP
ICR XX
326
ILM
Interrupt
processing
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.5
Precautions when Using Delayed Interrupt Generation
Module
This section explains the precautions when using the delayed interrupt generation
module.
■ Precautions when Using Delayed Interrupt Generation Module
• The interrupt processing is restarted at return from interrupt processing without setting the R0 bit in the
delayed interrupt request generate/cancel register (DIRR) to "0" within the interrupt processing routine.
• Unlike software interrupts, interrupts in the delayed interrupt generation module are delayed.
327
CHAPTER 11 DELAYED INTERRUPT GENERATION MODULE
11.6
Program Example of Delayed Interrupt Generation Module
This section gives a program example of the delayed interrupt generation module.
■ Program Example of Delayed Interrupt Generation Module
● Processing specification
The main program writes "1" to the R0 bit in the delayed interrupt request generate/cancel register (DIRR)
to generate a delayed interrupt request and performs task switching.
● Coding example
ICR15
DIRR
EQU
EQU
0000BFH
00009FH
;Interrupt control register
;Delay interrupt factor generating/
Release register
DIRR_R0 EQU
DIRR:0
;Delay interrupt request generating bit
;---------Main program-----------------------------------CODE
CSEG
START:
;Stack pointer (SP),already initialized
AND
CCR,#0BFH
;Interrupt disabled
MOV
I:ICR15,#00H
;Interrupt level 0 (storng)
MOV
ILM,#07H
;Setting ILM in PS to levle 7
OR
CCR,#40H
;Interrupt enabled
SETB
I:DIRR_R0
;Delay interrupt request generating
LOOP
MOV
A,#00H
;No limit roop
MOV
A,#01H
BRA
LOOP
;---------Interrupt program-------------------------------------WARI:
CLRB
I:DIRR_R0
;Clear interrupt request flag
:
;
User processing
;
:
RETI
;Recovery from interrput
CODE
ENDS
;---------Vector setting----------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FF54H
;Setting vector to interrupt #42 (2AH)
DSL
WARI
ORG
0FFDCH
;Reset vector setting
DSL
START
DB
00H
;Setting to single chip mode
VECT
ENDS
END
START
328
CHAPTER 12
DTP/EXTERNAL INTERRUPT
This chapter explains the functions and operations of
DTP/external interrupt.
12.1 Overview of DTP/External Interrupt
12.2 Block Diagram of DTP/External Interrupt
12.3 Configuration of DTP/External Interrupt
12.4 Explanation of Operation of DTP/External Interrupt
12.5 Precautions when Using DTP/External Interrupt
12.6 Program Example of DTP/External Interrupt Function
329
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.1
Overview of DTP/External Interrupt
The DTP/external interrupt sends interrupt requests from external peripheral devices or
data transfer requests to the CPU to generate an external interrupt request, or starts the
(EI2OS).RX input of CAN controller can be used as external interrupt input.
■ DTP/External Interrupt Function
The interrupt request input from an external peripheral device to the external interrupt input pins (INT7 to
INT4) or RX pin is generated in the same way as interrupts by peripheral resources. It generates an external
interrupt or starts Extended Intelligent I/O service (EI2OS).
If the (EI2OS) is disabled in the interrupt control register (ICR: ISE = 0), the external interrupt function is
enabled, branching to interrupt processing.
If the EI2OS is enabled (ICR: ISE = 1), the DTP function is enabled and automatic data transfer is
performed, branching to interrupt processing after the completion of data transfer for the specified number
of times.
Table 12.1-1 shows overview DTP/external interrupt.
Table 12.1-1 Overview of DTP/External Interrupt
External interrupt
Input Pin
DTP Function
5 pins (RX, INT4 to INT7)
The interrupt factor is set in unit of pins using the detection level setting registers.
330
Interrupt Factor
Input of High level, Low level, rising
edge, or falling edge
Interrupt
Number
#15 (0FH), #24 (18H), #27 (1BH)
Interrupt
Control
The interrupt request output is enabled/disabled using the DTP/external interrupt
enable register (ENIR).
Interrupt flag
The interrupt factor is held using the DTP/external interrupt factor register (EIRR)
Processing
selection
The EI2OS is disabled.
(ICR: ISE=0)
The EI2OS is enabled.
(ICR: ISE=1)
Processing
contents
A branch is caused to the external
interrupt processing routine.
EI2OS performs auto data transfer and
completes the specified number of timer
for data transfers, causing a branch to
the interrupt processing.
Input of High level or Low level
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.2
Block Diagram of DTP/External Interrupt
The block diagram of the DTP/external interrupt is shown below.
■ Block Diagram of DTP/External Interrupt
Figure 12.2-1 Block Diagram of DTP/External Interrupt
Detection level setting register (ELVR)
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4
Pin
ReReReReReReserved served served served served served
LB0 LA0
Level edge
selector
INT7
Pin
Level edge
selector
Internal data bus
INT6
Pin
Level edge
selector
INT5
Pin
Level edge
selector
Pin
INT4
Level edge
selector
RX
DTP/external interrupt input
detection circuit
Re-
Re-
Re-
ER7 ER6 ER5 ER4 served served served ER0
Interrupt request
signal
DTP/external interrupt
factor register (EIRR)
Interrupt
request
signal
Re-
Re-
Re-
EN7 EN6 EN5 EN4 served served served EN0
DTP/external interrupt
enable register (ENIR)
331
CHAPTER 12 DTP/EXTERNAL INTERRUPT
● DTP/external interrupt input detector
This circuit detects interrupt requests or data transfer requests generated from external peripheral devices.
The interrupt request flag bit corresponding to the pin whose level or edge set by the detection level setting
register (ELVR) is detected is set to "1" (EIRR: ER).
● Detection level setting register (ELVR)
This register sets the level or edge of input signals from external peripheral devices that cause DTP/external
interrupt factors.
● DTP/external interrupt factor register (EIRR)
This register holds DTP/external interrupt factors.
If an enable signal is input to the DTP/external interrupt pin, the corresponding DTP/external interrupt
request flag bit is set to "1".
● DTP/external interrupt enable register (ENIR)
This register enables or disables DTP/external interrupt requests from external peripheral devices.
■ Details of Pins and Interrupt Numbers
Table 12.2-1 shows the pins and interrupt numbers used in the DTP/external interrupt.
Table 12.2-1 Pins and Interrupt Numbers Used by DTP/External Interrupt
Pin
Channel
Interrupt Number
P44/RX
RX
#15 (0FH)
P24/INT4
4
P25/INT5
5
P26/INT6
6
P27/INT7
7
#24 (18H)
#27 (1BH)
332
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.3
Configuration of DTP/External Interrupt
This section lists and details the pins, interrupt factors, and registers in the DTP/
external interrupt.
■ Pins of DTP/External Interrupt
The pins used by the DTP/external interrupt serve as general-purpose I/0 ports.
Table 12.3-1 lists the pin functions and the pin setting required for use in the DTP/external interrupt
Table 12.3-1 Pins of DTP/External Interrupt
Pin Name
P44/RX
Pin Function
Pin Settings Required for Use in DTP/
External Interrupt
General-purpose I/O port,
CAN reception input
P24/INT4
P25/INT5
P26/INT6
General-purpose I/O ports, DTP
external interrupt inputs
Set as input port in port direction register
(DDR).
P27/INT7
■ Block Diagram of Pins
Note:
For the block diagram of the pins, see "CHAPTER 4 I/O PORT".
■ List of Registers and Reset Values in DTP/External Interrupt
Figure 12.3-1 List of Registers and Reset Values in DTP/External Interrupt
bit
DTP/external interrupt factor register
(EIRR)
bit
DTP/external interrupt enable register
(ENIR)
bit
Detection level setting register
: upper (ELVR)
bit
Detection level setting register
: lower (ELVR)
× : Undefined
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
333
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.3.1
DTP/external interrupt factor register (EIRR)
This register holds DTP/external interrupt factors.
When a valid signal is input to the DTP/external interrupt pin or RX pin, the
corresponding interrupt request flag bit is set to "1".
■ DTP/external interrupt factor register (EIRR)
Figure 12.3-2 DTP/external interrupt factor register (EIRR)
15
14
13
12
11
10
9
8
-
-
-
R/W
Reset value
XXXXXXXXB
R/W R/W R/W R/W
bit15 to bit12,bit8
ER7 to ER4,ER0
R/W : Read/Write
X : Undefined
: Unused
0
1
DTP/external interrupt request flag bit
Read
Without DTP/external interrupt
With DTP/external interrupt
Write
Clear ER bit
No effection
Table 12.3-2 Function of DTP/External Interrupt Factor Register (EIRR)
bit name
Function
bit15
to
bit12,
bit8
ER7 to ER4, ER0:
DTP/External interrupt
request flag bits
These bits are set to "1" when the edges or level signals set by the detection condition select bits
(ELVR: LB, LA) in the detection level setting register are input to the DTP/external interrupt pin
or RX pin.
When set to "1": When the DTP/external interrupt request enable bit (ENIR: EN) is set to "1",
an interrupt request is generated to the corresponding DTP/external interrupt
channel.
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
Note:
• The bit returns "1" when read by a read modify write instruction.
• If more than one DTP/external interrupt request is enabled (ENIR: EN = 1), clear only the
bit in the channel that accepts an interrupt (EIRR: ER = 0).No other bits must be cleared
unconditionally.
• The value of the DTP/external interrupt request flag bit (EIRR:ER) is valid only when the
corresponding DTP/external interrupt request enable bit (ENIR:EN) is set to "1". When no
DTP/external interrupt is enabled (ENIR:EN=0), the DTP/external interrupt request flag
bit may be set regardless of whether a DTP/external interrupt factor is present.
• Clear the corresponding DTP/external interrupt request flag bit (EIRR:ER) immediately
before enabling a DTP/external interrupt (ENIR:EN=1).
Reference:
When the (EI2OS) is started, the interrupt request flag bit is automatically cleared after the
completion of data transfer (EIRR: ER = 0)
bit11
to
bit9
Unused bits
Read: The value is undefined.
Write: No effect
334
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.3.2
DTP/external interrupt enable register (ENIR)
The DTP/external interrupt enable register (ENIR) enables/disables the DTP/external
interrupt request for external interrupt pins (INT7 to INT4) and the RX pin respectively.
■ DTP/external interrupt enable register (ENIR)
Figure 12.3-3 DTP/external interrupt enable register (ENIR)
7
6
5
4
3
2
1
0
Reset value
ReReReserved served served
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit3 to bit1
Reserved
bit7 to bit4,bit0
EN7 to EN4,EN0
R/W : Read/Write
: Reset value
Reserved bit
Be sure to set to "0".
0
DTP/external interrupt request enable bit
DTP/external interrupt diszbled
DTP/external interrupt enabled
0
1
Table 12.3-3 Functions of DTP/External Interrupt Enable Register (ENIR)
bit name
bit7
to
bit4,
bit0
Function
EN7 to EN4, EN0:
DTP/external interrupt
request enable bits
This register enables or disables DTP/external interrupt requests via the DTP/
external interrupt pin or RX pin.
When the DTP/external interrupt request flag bit (EIRR: ER) is set to "1" with the
DTP/external interrupt request enable bit (ENIR: EN) containing "1", an interrupt
request is generated to the corresponding DTP/external interrupt pin or RX pin.
Note:
Clear the corresponding DTP/external interrupt request flag bit (EIRR:ER)
immediately before enabling a DTP/external interrupt (ENIR:EN=1).
Reference:
The state of the DTP/external interrupt pin or RX pin can be read directly using
the port data register irrespective of the setting of the DTP/external interrupt
request enable bit.
Table 12.3-4 Correspondence between DTP/External Interrupt Pins, DTP/External Interrupt
Request Flag Bits, and DTP/External Interrupt Request Enable Bits
DTP/External Interrupt Pins
DTP/External interrupt
request flag bits
DTP/external interrupt
request enable bits
RX
ER0
EN0
INT4
ER4
EN4
INT5
ER5
EN5
INT6
ER6
EN6
INT7
ER7
EN7
335
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.3.3
Detection Level Setting Register (ELVR) (High)
The detection level setting register (High) sets the levels or edges of input signals that
cause interrupt factors in INT7 to INT4 of the DTP/external interrupt pins.
■ Detection Level Setting Register (ELVR) (High)
Figure 12.3-4 Detection Level Setting Register (ELVR) (High)
15
14
13
12
11
10
9
8
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit15 to bit8
LB7, LA7
LB6, LA6
LB5, LA5
LB4, LA4
0
0
0
1
1
0
1
1
R/W : Read/Write
: Reset value
Detection condition select bit
"L" level detection
"H" level detection
Rising edge detection
Falling edge detection
Table 12.3-5 Functions of Detection Level Setting Register (ELVR) (High)
bit name
bit15
to
bit8
Function
LB7, LA7 to LB4, LA4:
Detection condition
select bits
These bits set the levels or edges of input signals from external peripheral devices
that cause interrupt factors in the DTP/external interrupt pins.
• Two levels or two edges are selectable for external interrupts, and two levels are
selectable for the EI2OS.
Reference:
When the set detection signal is input to the DTP/external interrupt pins, the
DTP/external interrupt request flag bits are set to "1" even if DTP/external
interrupt requests are disabled (ENIR: EN = 0).
Table 12.3-6 Correspondence between Detection Level Setting Register (ELVR) (High) and
Channels
336
DTP/External Interrupt Pins
bit name
INT4
LB4, LA4
INT5
LB5, LA5
INT6
LB6, LA6
INT7
LB7, LA7
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.3.4
Detection Level Setting Register (ELVR) (Low)
The detection level setting register (ELVR) (Low) sets the levels or edges of input
signals that cause interrupt factors in the RX pin.
■ Detection Level Setting Register (ELVR) (Low)
Figure 12.3-5 Detection Level Setting Register (ELVR) (Low)
7
6
5
4
3
2
1
0
Reset value
Re- Re- Re- Re- Re- Reserved served served served served served
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit1 bit0
LB0, LA0
0
0
1
1
0
1
0
1
Detection condition select bit
"L" level detection
"H" level detection
Rising edge detection
Falling edge detection
bit7 to bit2
Reserved bit
Reserved
R/W : Read/Write
: Reset value
0
Be sure to set to "0".
Table 12.3-7 Functions of Detection Level Setting Register (ELVR) (Low)
bit name
bit1,
bit0
Function
LB0, LA0:
Detection condition
select bits
These bits set the levels or edges of input signals from external peripheral devices
that cause interrupt factors in the RX pin.
• Two levels or two edges are selectable for external interrupts, and two levels are
selectable for the EI2OS.
Reference:
When the set detection signal is input to the RX pin, the DTP/external interrupt
request flag bits are set to "1" even if DTP/external interrupt requests are
disabled (ENIR: EN = 0).
Table 12.3-8 Correspondence between Detection Level Setting Register (ELVR) (Low) and
Channels
DTP/External Interrupt Pins
bit name
RX
LB0 to LA0
337
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.4
Explanation of Operation of DTP/External Interrupt
The DTP/external interrupt circuit has an external interrupt function and a DTP
function.The setting and operation of each function is explained.
■ Setting of DTP/External Interrupt Circuit
Using the DTP/external interrupt requires, the setting shown in Figure 12.4-1.
Figure 12.4-1 Setting of DTP/External Interrupt Circuit
bit15 14 13 12
ICR interrupt
ICS3 ICS2 ICS1 ICS0
control register
External interrupt
DTP
EIRR/ENIR
ELVR
11
10
9 bit8 bit7 6
5
4
3
2
1 bit0
ISE IL2 IL1 IL0 ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0
0
1
-
-
-
-
0
1
Re-
Re-
Re-
0
0
0
ER7 ER6 ER5 ER4 -
-
- ER0 EN7 EN6 EN5 EN4 served served served EN0
-
-
-
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4
ReReReReReReserved served served served served served
0
0
0
0
0
LB0 LA0
0
DDR port direction
register
DTP/Setting "0" to corresponding bit to used pin as external
- : Unused bit
interrupt input
: Used bit
; Setting "1" to corresponding bit to used pin
0 : Setting "0"
1 : Setting "1"
● Setting procedure
To use the DTP/external interrupt, set each register by using the following procedure:
1. Set the general-purpose I/O port served dual use as the pin for the external interrupt input to input port.
2. Set the interrupt request enable bit corresponding to the DTP/external interrupt channel to be used to "0"
(ENIR: EN).
3. Use the detection condition select bit corresponding to the DTP/external interrupt pin or RX pin to be
used to set the edge or level to be detected.
4. Set the interrupt request flag bit corresponding to the DTP/external interrupt channel to be used to "0"
(EIRR: ER).
5. Set the interrupt request enable bit corresponding to the DTP/external interrupt channel to be used to "1"
(ENIR: EN).
• When setting the registers for the DTP/external interrupt, the external interrupt request must be disabled
in advance (ENIR: EN0 = 0).
• When enabling the DTP/external interrupt request (ENIR: EN = 1), the corresponding DTP/external
interrupt request flag bit must be cleared in advance (EIRR: ER = 0).These actions prevent the mistaken
interrupt request from occurring when setting the register.
338
CHAPTER 12 DTP/EXTERNAL INTERRUPT
● Selecting of DTP or external interrupt function
Whether the DTP function or the external interrupt function is executed depends on the setting of the
EI2OS enable bit in the corresponding interrupt control register (ICR: ISE).
If the ISE bit is set to "1", the EI2OS is enabled and the DTP function is executed.
If the ISE bit is set to "0", the EI2OS is disabled and the external interrupt function is executed.
Notes:
• All interrupt requests assigned to one interrupt control register have the same
interrupt level (IL2 to IL0).
• If two or more interrupt requests are assigned to one interrupt control register and
EI2OS is used for any of them, other interrupt requests cannot be used.
■ DTP/External Interrupt Operation
The control bits and the interrupt factors for the DTP/external interrupt are shown in Table 12.4-1.
Table 12.4-1 Control Bits and Interrupt Factors for DTP/External Interrupt
DTP/external interrupt
Interrupt request flag bit
EIRR: ER7 to ER4, ER0
Interrupt request flag bit
ENIR: EN7 to EN4, EN0
Interrupt Factor
Input of valid edge/level to INT7 to INT4, RX pins
If the interrupt request signal from the DTP/external interrupt is output to the interrupt controller and the
EI2OS enable bit in the interrupt control register (ICR: ISE) is set to "0", the interrupt processing is
executed. When this bit is set to "1", the EI2OS is executed.
339
CHAPTER 12 DTP/EXTERNAL INTERRUPT
Figure 12.4-2 shows operation of DTP/external interrupt.
Figure 12.4-2 Operation of DTP/External Interrupt
DTP/external interrupt circuit
Other request
ELVR
CPU
Interrupt controller
ICR YY
EIRR
IL
CMP
CMP
ICR XX
ENIR
ILM
Interrupt
processing
Factor
EI2OS start-up
DTP/external interrupt
request generating
Memory
Peripheral data
trnsmission
Descriptor renewal
Interrupt controller
reception judge
Descriptor
data counter
CPU interrupt
reception judge
=0
Interrupt processing
0
Re-setting or stop
Interrupt processing
micro program
start-up
ICR : ISE
Recovery from
DTP processing
1
0
Start-up external interrupt
Processing and clear
interrupt flag
Recovery from external interrupt
340
Recovery from
EI2OS processing
(DTP processing)
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.4.1
External Interrupt Function
The DTP/external interrupt has an external interrupt function for generating an interrupt
request by detecting the signal (edge or level) in the DTP/external interrupt pin or RX
pin.
■ External Interrupt Function
• When the signal (edge or level) set in the detection level setting register is detected in the DTP/external
interrupt pin or RX pin, the interrupt request flag bit (EIRR: ER) in the DTP/external interrupt request
register is set to "1".
• If the interrupt request enable bit in the DTP/external interrupt enable register is enabled (ENIR: EN =
1) and the interrupt request flag bit set to "1", the interrupt is implemented to the interrupt controller.
• An interrupt request is generated when the interrupt controller prefers the interrupt request to other
requests.
• If the level of an interrupt request (ICR: IL) is higher than that of the interrupt level mask bit (TLM) in
the processor status (PS) and the interrupt enable bit is enabled (PS: CCR: I = 1), the CPU performs
interrupt processing after completion of the current instruction execution and branches to interrupt
processing.
• At interrupt processing, set the corresponding DTP/external interrupt request flag bit to "0" and clear the
DTP/external interrupt request.
Notes:
• When the DTP/external interrupt start factor is generated, the DTP/external
interrupt request flag bit (EIRR: ER) is set to "1", regardless of the setting of the
DTP/external interrupt request enable bit (ENIR: EN).
• When the interrupt processing is started, clear the DTP/external interrupt request
flag bit that caused the interrupt. Control cannot be returned from the interrupt
while the DTP/external interrupt request flag bit is set to "1".When clearing, do not
clear any flag bit other than the accepted DTP/external interrupt factor.
341
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.4.2
DTP Function
The DTP/external interrupt has the DTP function that detects the signal from an external
peripheral device through the DTP/external interrupt pin or RX pin to start Extended
Intelligent I/O Service (EI2OS).
■ DTP Function
The DTP function detects the signal level set by the detection level setting register of the DTP/external
interrupt function to start the EI2OS.
• When the EI2OS operation is already enabled (ICR: ISE = 1) at the point when the interrupt request is
accepted by the CPU, the DTP function starts the EI2OS and starts data transfer.
• Upon completion of transfer of one data item, the descriptor is updated and the DTP/external interrupt
request flag bit is cleared to prepare for the next request from the DTP/external interrupt pin and RX
pin.
• When the EI2OS completes transfer of all the data, control branches to the interrupt processing.
Figure 12.4-3 Example of Interface with External Peripheral Device
"H" level request (ELVR: LB4, LA4=01B)
Input to INT4 pin
(DTP factor)
CPU internal
operation
Descriptor
select and read
Peripheral
equipment
of external
connection
Data
transmisson
request
Descriptor
renewal
Internal data bus
Read/Write
operation*2
DTP factor*1
INT DTP/extenal Interrupt
interrupt
request
circuit
CPU
(EI2OS)
*1: This must be cancelled within three machine clooks after the start of data transfer.
*2: When EI2OS in "peripheral function
internal memory transfer".
342
Internal
memory
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.5
Precautions when Using DTP/External Interrupt
This section explains the precautions when using the DTP/external interrupt.
■ Precautions when Using DTP/External Interrupt Circuit
● Condition of external-connected peripheral device when DTP function is used
• When using the DTP function, the peripheral device must automatically clear a data transfer request
when data transfer is performed.
• Inactivate the transfer request signal within three machine clocks after starting data transfer.If the
transfer request signal remains active, the DTP/external interrupt regards the transfer request signal as a
generation of next transfer request.
● External interrupt input polarity
• When the edge detection is set in the detection level setting register, the pulse width for edge detection
must be at least three machine clocks.
• When a level causing an interrupt factor is input with level detection set in the detection level setting
register, the DTP/external interrupt request flag bit (EIRR: ER) in the DTP/external interrupt factor
register is set to "1" and the factor is held as shown in Figure 12.5-1.
With the factor held in the DTP/external interrupt request flag bit (EIRR: ER), the request to the interrupt
controller remains active if the interrupt request is enabled (ENIR: EN = 1) even after the DTP/external
interrupt factor is cancelled.To cancel the request to the interrupt controller, clear the DTP/external
interrupt request flag bit (EIRR: ER) as shown in Figure 12.5-2.
Figure 12.5-1 Clearing Factor Hold Circuit when Level Set
DTP/external
interrupt factor
DTP/interrupt input
detection circuit
DTP/external
interrupt request
flag bit (EIRR: ER)
Enable gate
To interrupt
controller
(interrupt request)
Hold the factor untill clearing
343
CHAPTER 12 DTP/EXTERNAL INTERRUPT
Figure 12.5-2 DTP/External Interrupt Factor and Interrupt Request Generated when Interrupt Request
Enabled
DTP/externalinterrupt factor
(ehen "H" level detection)
Terminated interrupt factor
Interrupt request to
interrupt controller
Being inactive by clearing the DTP/external interrupt request flag bit (EIRR: ER)
● Precautions on interrupts
• When the DTP/external interrupt is used as the external interrupt function, no return from interrupt
processing can be made with the DTP/external interrupt request flag bit set to "1" (EIRR: ER) and the
DTP/external interrupt request set to enabled (ENIR: EN = 1). Always set the DTP/external interrupt
request flag bit to "0" (EIRR: ER) at interrupt processing.
• When the level detection is set in the detection level setting register and the level that becomes the
interrupt factor remains input, the external interrupt request flag bit is reset immediately even when
cleared (EIRR: ER = 0).Disable the DTP/external interrupt request output as needed (ENIR: EN = 0), or
cancel the interrupt factor itself.
344
CHAPTER 12 DTP/EXTERNAL INTERRUPT
12.6
Program Example of DTP/External Interrupt Function
This section gives a program example of the DTP/external interrupt function.
■ Program Example of DTP/External Interrupt Function
● Processing specification
An external interrupt is generated by detecting the rising edge of the pulse input to the INT4 pin.
● Coding example
ICR06 EQU
0000B6H
;DTP/external interrupt control register
DDR2
EQU
000012H
;Port 2 direction register
ENIR
EQU
000030H
;DTP/external interrupt enable register
EIRR
EQU
000031H
;DTP/external interrupt factor register
ELVRL EQU
000032H
;Detection level setting register: L
ELVRH EQU
000033H
;Detection level setting register: H
ER0
EQU
EIRR:0
;INT4 interrupt request flag bit
EN0
EQU
ENIR:0
;INT4 interrupt request flag bit
;
;---------Main program------------------------------------CODE
CSEG
START:
;Stack pointer (SP),already initialized
MOV
I:DDR2,#00000000B ;Setting DDR2 to input port
AND
CCR,#0BFH
;Interrupt disabled
MOV
I:ICR06,#00H
;Interrupt level 0 (highest)
CLRB I:EN4
;Disable INT4 at ENIR
MOV
I:ELVRL,#00000010B ;INT4 is rising edge selection
CLRB I:ER4
;Interrupt request flag of INT4 in EIRR
;Clear
SETB I:EN4
;Interrupt request enabled of INT4 in ENIR
MOV
ILM,#07H
;Setting ILM in PS to level 7
OR
CCR,#40H
;Interrupts enabled
LOOP:
.
User processing
.
BRA
LOOP
;---------Interrupt program------------------------------------WARI:
CLRB
I:ER4
;Clear interrupt request flag
.
User processing
.
RETI
;Recovery from interrupt processing
CODE
ENDS
;---------Vector setting----------------------------------------VECT
CSEG ABS=0FFH
ORG
00FFC0H
;Setting vector to interrupt number #15(0FH)
DSL
WARI
ORG
00FFDCH
;Reset vector setting
DSL
START
DB
00H
;Set to single chip mode
VECT
ENDS
END
START
345
CHAPTER 12 DTP/EXTERNAL INTERRUPT
■ Programming sample of DTP Function
● Processing specification
• Channel 0 of Extended Intelligent I/O Service (EI2OS) is started upon detection of the High level of the
signal input to the INT4 pin.
• RAM data is output to port 0 by DTP processing (EI2OS).
● Coding example
ICR06 EQU
0000B6H
;DTP/external interrupt control register
DDR1
EQU
000011H
;Port 1 direction register
DDR5
EQU
000015H
;Port 5 direction register
ENIR
EQU
000030H
;DTP/external interrupt enable register
EIRR
EQU
000031H
;DTP/external interrupt factor register
ELVRL EQU
000032H
;Detection level setting: L
ELVRH EQU
000033H
;Detection level setting: H
ER4
EQU
EIRR:0
;INT4 interrupt request enable bit
EN4
EQU
ENIR:0
;INT4 interrput request enable bit
;
BAPL
EQU
000100H
;Buffer addresuu pointer loewr
BAPM
EQU
000101H
;Buffer addresuu pointer middle
BAPH
EQU
000102H
;Buffer addresuu pointer upper
ISCS
EQU
000103H
;EI2OS stasu register
IOAL
EQU
000104H
;I/O address register lower
IOAH
EQU
000105H
;I/O address register upper
DCTL
EQU
000106H
;Data counter lower
DCTH
EQU
000107H
;Data counter upper
;
;---------Main ptrogram------------------------------------CODE
CSEG
START:
;Stack pointer (SP),already initialized
MOV
I:DDR1,#11111111B ;Setting output port in DDR1
MOV
I:DDR5,#00000000B ;Setting input port in DDR5
AND
CCR,#0BFH
;Interrupt disabled
MOV
I:ICR06,#08H
;Interrupt level 0 (strongest) EI2OS
;Channel 0
;
;Data bank register (DTB) = 00H
;
MOV
BAPL,#00H
;Address for storing output data set
MOV
BAPM,#06H
;(600H to 60AH used)
MOV
BAPH,#00H
MOV
ISCS,#12H
;Byte transmission, buffer address + 1,
;Fix I/O address,
;Transmission from memory to I/O
MOV
IOAL,#00H
;Port 1 set as
MOV
IOAH,#00H
;transfer destination address pointer
MOV
DCTL,#0AH
;Transfer count set to 10
MOV
DCTH,#00H
;
CLRB I:EN4
;Disable INT4 in ENIR
MOV
I:ELVRL,#00010000B ;INT4 sets "H" level detection.
CLRB I:ER4
;Interrupt request flag of INT4 in EIRR
;Clear
SETB I:EN4
;Interrupt request enable of INT4 in ENIR
MOV
ILM,#07H
;Setting ILM in PS to level 7
OR
CCR,#40H
;Interrupt enable
346
CHAPTER 12 DTP/EXTERNAL INTERRUPT
LOOP:
.
User processing
.
BRA
LOOP
;---------Interrupt program------------------------------------WARI:
CLRB
I:ER4
;Clear INT4 interrupt request flag
.
User processing
.
RETI
;Recovery from interrupt processing
CODE
ENDS
;---------Vector setting-----------------------------------------VECT
CSEG ABS=0FFH
ORG
00FF9CH
;Setting vector to interrupt number #24(18H)
DSL
WARI
ORG
00FFDCH
;Reset vector setting
DSL
START
DB
00H
;Setting to single chip mode
VECT ENDS
END
START
347
CHAPTER 12 DTP/EXTERNAL INTERRUPT
348
CHAPTER 13
8/10-bit A/D CONVERTER
This chapter explains the functions and operation of 8-/
10-bit A/D converter.
13.1 Overview of 8-/10-bit A/D Converter
13.2 Block Diagram of 8-/10-bit A/D Converter
13.3 Configuration of 8-/10-bit A/D Converter
13.4 Interrupt of 8-/10-bit A/D Converter
13.5 Explanation of Operation of 8-/10-bit A/D Converter
13.6 Precautions when Using 8-/10-bit A/D Converter
349
CHAPTER 13 8/10-bit A/D CONVERTER
13.1
Overview of 8-/10-bit A/D Converter
The 8-/10-bit A/D converter converts the analog input voltage to a 8- or 10-bit digital
value by using the RC sequential-comparison converter system.
• An input signal can be selected from the input signals of the analog input pins for 8
channels.
• The start trigger can be selected from a software trigger, internal timer output, and an
external trigger.
■ Function of 8-/10-bit A/D Converter
The 8-/10-bit A/D converter converts the analog voltage (input voltage) input to the analog input pin into
an 8- or 10-bit digital value (A/D conversion).
The 8-/10-bit A/D converter has the following functions:
• A/D conversion time is a minimum of 6.12 μs* per channel including sampling time.
• Sampling time is a minimum of 2.0 μs* per channel.
• RC sequential-comparison converter system with sample & hold circuit
• Setting of 8-bit or 10-bit resolution enabled
• Analog input pin can be used up to 8 channels.
• Generates interrupt request by storing A/D conversion results in A/D data register
• Starts EI2OS if interrupt request generated. Use of the EI2OS prevents data loss even at continuous
conversion.
• Selects start trigger from software trigger, internal timer output, and external trigger (falling edge)
*:When the machine clock operates at 16 MHz
■ Conversion Modes of 8-/10-bit A/D Converter
There are conversion modes of 8-/10-bit A/D converter as shown below:
Table 13.1-1 Conversion Modes of 8-/10-bit A/D Converter
Conversion Mode
350
Description
Single-shot
conversion mode
A/D conversion is performed sequentially from the start channel to the end
channel.When A/D conversion for the end channel is terminated, it stops.
Continuous
conversion mode
A/D conversion is performed sequentially from the start channel to the end
channel.When A/D conversion for the end channel is terminated, it is continued
after returning to the start channel.
Pause-conversion
mode
A/D conversion is performed sequentially from the start channel to the end
channel.When A/D conversion for the end channel is terminated, A/D
conversion and pause are repeated after returning to the start channel.
CHAPTER 13 8/10-bit A/D CONVERTER
13.2
Block Diagram of 8-/10-bit A/D Converter
The 8-/10-bit A/D converter consists of following blocks.
■ Block Diagram of 8-/10-bit A/D Converter
Figure 13.2-1 Block Diagram of 8-/10-bit A/D Converter
A/D control
Interrupt requext output
status
register
(ADCS)
BUSY INT INTE PAUS STS1 STS0 STRT Re- MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
served
2
2
Start-up
selector
Decoder
Internal data bus
ADTG
TO
6
φ
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Sample &
hold circuit
Comparator
Control circuit
Analog
channel
selector
AVR
AVcc
AVss
D/A converter
2
2
A/D data
register
(ADCR) S10 ST1 ST0 CT1 CT0
-
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
: Internal timer output
TO
: Unused
Reserved : Be sure to set to "0".
: Machine clock
φ
351
CHAPTER 13 8/10-bit A/D CONVERTER
● Details of pins in block diagram
Table 13.2-1 shows the actual pin names and interrupt request numbers of the 8-/10-bit A/D converter
Table 13.2-1 Pins and Interrupt Request Numbers in Block Diagram
Pin Name/Interrupt Request Number in Block
Diagram
Actual Pin Name/Interrupt Request
Number
ADTG
Trigger input pin
P37/ADTG
TO
Internal timer output
TO (16-bit reload timer, 16-bit free-run
timer)
AN0
Analog input pin ch 0
P50/AN0
AN1
Analog input pin ch 1
P51/AN1
AN2
Analog input pin ch 2
P52/AN2
AN3
Analog input pin ch 3
P53/AN3
AN4
Analog input pin ch 4
P54/AN4
AN5
Analog input pin ch 5
P55/AN5
AN6
Analog input pin ch 6
P56/AN6
AN7
Analog input pin ch 7
P57/AN7
AVR
Vref+ Input pin
AVR
AVCC
V CC Input pin
AVCC
AVSS
V SS Input pin
AVSS
Interrupt request
output
#18 (12H)
● A/D control status registers (ADCS)
This register starts the A/D conversion function by software, selects the start trigger for the A/D conversion
function, selects the conversion mode, enables or disables an interrupt request, checks and clears the
interrupt request flag, temporarily stops A/D conversion and checks the state during conversion, and sets
the start and end channels for A/D conversion.
● A/D data registers (ADCR)
This register stores the A/D conversion results.And it selects the comparison time, sampling time, and
resolution of A/D conversion.
● Start selector
This selector selects the trigger to start A/D conversion.An internal timer output or external pin input can
be set as the start trigger.
352
CHAPTER 13 8/10-bit A/D CONVERTER
● Decoder
This decoder sets the A/D conversion start channel select bits and the A/D conversion end channel select
bits in the A/D control status register (ADCS: ANS2 to ANS0 and ANE2 to ANE0) to select the analog
input pin to be used for A/D conversion.
● Analog channel selector
This selector selects the pin to be used for A/D conversion from the 8-channel analog input pins by
receiving a signal from the decoder.
● Sample & hold circuit
This circuit holds the input voltage selected by the analog channel selector. By holding the input voltage
immediately after A/D conversion is started, A/D conversion is performed without being affected by the
fluctuation of the input voltage during A/D conversion.
● D/A converter
This converter generates the reference voltage which is compared with the input voltage held in the sample
& hold circuit.
● Comparator
This comparator compares the D/A converter output voltage with input voltage held in the sample & hold
circuit to determine the mount of voltage.
● Control circuit
This circuit determines the A/D conversion value by receiving the signal indicating the amount of voltage
determined by the comparator.When the A/D conversion results are determined, the result data is stored in
the A/D data register.If an interrupt request is enabled, an interrupt is generated.
353
CHAPTER 13 8/10-bit A/D CONVERTER
13.3
Configuration of 8-/10-bit A/D Converter
This section explains the pins, registers, and interrupt factors of the A/D converter.
■ Pins of 8-/10-bit A/D Converter
The pins of the 8-/10-bit A/D converter serve as general-purpose I/O ports.Listed below are the pin
functions and the settings required for use of the 8-/10-bit A/D converter.
Table 13.3-1 Pins of 8-/10-bit A/D Converter
Function Used
Trigger input
Reference:
354
Pin Name
ADTG
Channel 0
AN0
Channel 1
AN1
Channel 2
AN2
Channel 3
AN3
Channel 4
AN4
Channel 5
AN5
Channel 6
AN6
Channel 7
AN7
Pin Function
General-purpose I/O
port,
external trigger input
General-purpose I/O
ports, analog inputs
Setting Required for Use of 8-/10-bit
A/D Converter
Set as input port in port direction register
(DDR).
Set as input port in port direction register
(DDR).
Input of analog signal enabled
(ADER: ADE7 to ADE0 = 11111111 B)
For the block diagram of the pins, see "CHAPTER 4 I/O PORT".
CHAPTER 13 8/10-bit A/D CONVERTER
■ List of Registers and Reset Values of 8-/10-bit A/D Converter
Figure 13.3-1 List of Registers and Reset Values of 8-/10-bit A/D Converter
bit
A/D control status register upper
(ADCS: H)
bit
A/D control status register lower
(ADCS: L)
bit
A/D data register upper (ADCR: H)
bit
A/D data register lower (ADCR: L)
bit
Analog input enable register (ADER)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
1
0
1
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
× : Undefined
■ Generation of Interrupt from 8-/10-bit A/D Converter
In the 8-/10-bit A/D converter, when the A/D conversion results are stored in the A/D data register
(ADCR), the interrupt request flag bit in the A/D control status register (ADCS: INT) is set to "1".When an
interrupt request is enabled (ADCS: INTE = 1), an interrupt is generated.
355
CHAPTER 13 8/10-bit A/D CONVERTER
13.3.1
A/D Control Status Register (High) (ADCS: H)
The A/D control status register (High) (ADCS: H) provides the following settings:
• Starting A/D conversion function by software
• Selecting start trigger for A/D conversion
• Storing A/D conversion results in A/D data register to enable or disable interrupt
request
• Storing A/D conversion results in A/D data register to check and clear interrupt
request flag
• Pausing A/D conversion and checking state during conversion
■ A/D Control Status Register (High) (ADCS: H)
Figure 13.3-2 A/D Control Status Register (High) (ADCS: H)
15
14
13
12
11
10
9
8
Reset value
00000000B
R/W R/W R/W R/W R/W R/W
W R/W
bit8
Reserved
0
Reserved bit
Be sure to set to "0".
bit9
STRT
A/D conversion software start-up bit
0
A/D conversion function doesn't start-up.
1
A/D conversion function start-up.
bit11 bit10
A/D conversion start-up trigger select bit
STS1 STS0
0
0 Software stra-up
0
1 Software stra-up or external trigger start-up
1
0 Software stra-up or internal timer start-up
1
1 Software stra-up, external trigger or internal timer start-up
bit12
PAUS
Temporary stop flag bit
(Valid only when EI2OS is used)
0
A/D conversion operation doesn't stop temporarily.
1
A/D conversion operation stops temporarily.
bit13
INTE
0
1
Interrupt request enable bit
Interrupt request disabled
Interrupt request enabled
bit14
INT
Interrupt request flag bit
0
Read
Not finish A/D conversion
Write
Clear to "0"
1
Finish A/D conversion
No effection
bit15
BUSY
0
R/W
356
: Read Write
: Reset value
1
A/D conversion operating flag bit
Read
Finish A/D conversion
(no starting-up state)
In operating of A/D conversion
Write
Terminates A/D conversion
forcibly
No effection
CHAPTER 13 8/10-bit A/D CONVERTER
Table 13.3-2 Function of Each Bit of A/D Control Status Register (High) (ADCS: H) (1/2)
bit name
Function
bit15
BUSY:
A/D conversion-on flag
bit
This bit forcibly terminates the 8-/10-bit A/D converter.When read,
this bit indicates whether the 8-/10-bit A/D converter is operating or
stopped.
When set to "0": Forcibly terminates 8-/10-bit A/D converter
When the bit is set to "1": No effect.
Read: "1" is read when the 8-/10-bit A/D converter is operating and
"0" is read when the 8-/10-bit A/D converter is stopped.
Note:
Do not perform forcible termination (BUSY = 0) and software
start (STRT = 1) of the 8-/10-bit A/D converter simultaneously.
bit14
INT:
Interrupt request flag bit
This bit indicates that an interrupt request is generated.
• When A/D conversion is terminated and its results are stored in
the A/D data register (ADCR), the INT bit is set to "1".
• When the interrupt request flag bit is set (INT = 1) with an
interrupt request enabled (INTE = 1), an interrupt request is
generated.
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
When EI2OS function started: Cleared
Note:
To clear the INT bit, write "0" when the 8-/10-bit A/D converter
is stopped.
bit13
INTE:
Interrupt request flag bit
This bit enables or disables output of an interrupt request.
• When the interrupt request flag bit is set with an interrupt
request enabled (INTE = 1), an interrupt request is generated.
Note:
Always set this bit to 1 when the EI2OS function is used.
bit12
PAUS:
Pause flag bit
This bit indicates the A/D conversion operating state when the
STS1, STS0:
A/D conversion start
trigger select bits
These bits select the trigger to start the 8-/10-bit A/D converter.
If two or more start triggers are set (except STS1, STS0=00B),
the 8-/10-bit A/D converter is started by the first-generated start
trigger.
Note:
Start trigger setting should be changed when the operation of
resource generating a start trigger is stopped.
bit11,
bit10
EI2OS function is used.
• The PAUS bit is enabled only when the EI2OS function is used.
• A/D conversion pauses while the A/D conversion results are
transferred from the A/D data register (ADCR) to
memory.When A/D conversion pauses, the PAUS bit is set to
"1".
• After transfer of the A/D conversion results to memory,
the 8-/10-bit A/D converter automatically resumes A/D
conversion.When A/D conversion is started, the PAUS bit is
cleared to "0".
357
CHAPTER 13 8/10-bit A/D CONVERTER
Table 13.3-2 Function of Each Bit of A/D Control Status Register (High) (ADCS: H) (2/2)
bit name
358
Function
bit9
STRT:
A/D conversion software
start bit
This bits starts the 8-/10-bit A/D converter by software.
When set to "1": Starts 8-/10-bit A/D converter
• If A/D conversion pauses in the pause-conversion mode, it is
resumed by writing "1" to the STRT bit.
When set to "0":
Disabled.The state remains unchanged.
Read: The bit returns "1" when byte/word instructions.
The bit returns "0" when read-modify-write instructions.
Note:
Do not perform forcible termination (BUSY = 0) and software
start (STRT = 1) of the 8-/10-bit A/D converter simultaneously.
bit8
Reserved: reserved bit
Always set this bit to "0".
CHAPTER 13 8/10-bit A/D CONVERTER
13.3.2
A/D Control Status Register (Low) (ADCS: L)
The A/D control status register (Low) (ADCS: L) provides the following settings:
• Selecting A/D conversion mode
• Selecting start channel and end channel of A/D conversion
■ A/D Control Status Register (Low) (ADCS: L)
Figure 13.3-3 A/D Control Status Register (Low) (ADCS: L)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit2 bit1 bit0
ANE2 ANE1 ANE0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
0
1
1
1
0
1
1
1
1
bit5
bit4
A/D conversion finish channel select bit
AN0 pin
AN1 pin
AN2 pin
AN3 pin
AN4 pin
AN5 pin
AN6 pin
AN7 pin
bit3
A/D conversion start channel select bit
ANS2 ANS1 ANS0
0
0
0
0
1
1
1
1
R/W : Read/Write
: Reset value
0
0
1
1
0
0
1
1
bit7 bit6
MD1 MD0
0
0
1
0
0
1
1
1
0
1
0
1
0
1
0
1
No start-up
state
AN0 pin
AN1 pin
AN2 pin
AN3 pin
AN4 pin
AN5 pin
AN6 pin
AN7 pin
Read in
cenversion
Channel
number in
conversion
Read during
a pause in stop
conversion mode
Channel number
just previously
converted
A/D conversion mode selection bit
Single conversion mode 1 (enable to restart-up during operation)
Single conversion mode 2 (disable to restart-up during operation)
Sequential conversion mode (disable to restart-up during operation)
Stop conversion mode (disable to restart-up during operation)
359
CHAPTER 13 8/10-bit A/D CONVERTER
Table 13.3-3 Function of Each Bit of A/D Control Status Register (Low) (ADCS: L) (1/2)
bit name
bit7,
bit6
360
MD1, MD0:
A/D conversion
mode select bits
Function
These bits set the A/D conversion mode.
Single-shot conversion mode 1:
• The analog inputs from the start channel (ADCS: ANS2 to ANS0) to the end channel (ADCS: ANE2
to ANE0) are A/D-converted continuously.
• The A/D conversion pauses after A/D conversion for the end channel.
• This mode can be restarted during A/D conversion.
Single-shot conversion mode 2:
• The analog inputs from the start channel (ADCS: ANS2 to ANS0) to the end channel (ADCS: ANE2
to ANE0) are A/D-converted continuously.
• The A/D conversion pauses after A/D conversion for the end channel.
• This mode cannot be restarted during A/D conversion.
Continuous conversion mode:
• The analog inputs from the start channel (ADCS: ANS2 to ANS0) to the end channel (ADCS: ANE2
to ANE0) are A/D-converted continuously.
• When A/D conversion for the end channel is terminated, it is continued after returning to the analog
input for the start channel.
• To terminate A/D conversion forcibly, write "0" to the A/D conversion-on flag bit in the A/D control
status register (ADCS: BUSY).
• This mode cannot be restarted during A/D conversion.
Pause conversion mode:
• A/D conversion for the start channel (ADCS: ANS2 to ANS0) starts.The A/D conversion pauses at
termination of A/D conversion for a channel.When the start trigger is input while A/D conversion
pauses, A/D conversion for the next channel is started.
• The A/D conversion pauses at the termination of A/D conversion for the end channel.When the start
trigger is input while A/D conversion pauses, A/D conversion is continued after returning to the analog
input for the start channel.
• To terminate A/D conversion forcibly, write "0" to the A/D conversion-on flag bit in the A/D control
status register (ADCS: BUSY).
• This mode cannot be restarted during A/D conversion.
Note:
When the conversion mode is set to not restartable (except MD1, MD0=00B), it cannot be restarted
with any start triggers (software trigger, internal timer, and external trigger) during A/D conversion.
CHAPTER 13 8/10-bit A/D CONVERTER
Table 13.3-3 Function of Each Bit of A/D Control Status Register (Low) (ADCS: L) (2/2)
bit name
Function
bit5
to
bit3
ANS2 to ANS0:
A/D conversion
start channel select
bits
These bits set the channel at which A/D conversion start.At read, the channel number under A/D
conversion or A/D-converted immediately before A/D conversion pauses can be checked.
And before A/D conversion starts, the previous conversion channel will be read even if these bits have
already been set to the new value. These bits are initialized to "000B" at reset.
Start channel < end channel: A/D conversion starts at channel set by A/D conversion start channel
select bits (ANS2 to ANS0) and terminates channel set by A/D
conversion end channel select bits (ANE2 to ANE0).
Start channel = end channel: A/D conversion is performed only for one channel set by A/D conversion
(= end) channel select bits (ANS2 to ANS0 = ANE2 to ANE0).
Start channel > end channel: A/D conversion is performed from channel set by A/D conversion start
channel select bits (ANS2 to ANS0) to AN7, and from AN0 to channel
set by A/D conversion end channel select bits (ANE2 to ANE0).
Continuous conversion mode and pause-conversion mode:
When A/D conversion terminated at the channel set by the A/D conversion end channel select
bits (ANE2 to ANE0), it returns to the channel set by the A/D conversion start channel select
bits (ANS2 to ANS0).
Read (During A/D conversion): The channel numbers (7 to 0) under A/D conversion are read.
Read (During a pause in pause conversion mode): At read during a pause, the channel number A/Dconverted immediately before a pause is read.
Note:
• Do not set the A/D conversion start channel bits (ANS2 to ANS0) during A/D conversion.
• Do not use a read-modify-write instruction to set the bits in this register after setting the start
channel for the A/D conversion start channel bits (ANS2, ANS1 and ANS0).
• Reading ANS2, ANS1 and ANS0 returns the previous conversion channel until A/D conversion
starts. Therefore, if the bits in this register are set by using a read-modify-write instruction after
the start channel is set in ANS2, ANS1 and ANS0, the value contained in ANS2, ANS1 and ANS0
may be rewritten.
bit2
to
bit0
ANE2 to ANE0:
A/D conversion end
channel select bits
These bits set the channel at which A/D conversion terminated.
Start channel < end channel: A/D conversion starts at channel set by A/D conversion start channel
select bits (ANS2 to ANS0) and terminates channel set by A/D
conversion end channel select bits (ANE2 to ANE0).
Start channel = end channel: A/D conversion is performed only for one channel set by A/D converter
end (= start) channel select bits (ANE2 to ANE0 = ANS2 to ANS0).
Start channel > end channel: A/D conversion is performed from channel set by A/D conversion start
channel select bits (ANS2 to ANS0) to AN7, and from AN0 to channel
set by A/D conversion end channel select bits (ANE2 to ANE0).
A/D conversion is performed up to the specified channel.
Continuous conversion mode and pause-conversion mode:
When A/D conversion terminated at the channel set by the A/D conversion end channel select bits
(ANE2 to ANE0), it returns to the channel set by the A/D conversion start channel select bits (ANS2
to ANS0).
Note:
Do not set the A/D conversion end channel select bits (ANE2 to ANE0) during A/D conversion.
361
CHAPTER 13 8/10-bit A/D CONVERTER
13.3.3
A/D Data Register (High) (ADCR: H)
The higher five bits in the A/D data register (ADCR: H) select the compare time,
sampling time and resolution of A/D conversion.
Bits 9 and 8 in the A/D data register (ADCR) are explained in Section 13.3-4 A/D Data
Register (Low) (ADCR: L).
■ A/D Data Register (High) (ADCR: H)
Figure 13.3-4 A/D Data Register (High) (ADCR: H)
15
W
14
W
13
W
12
W
11
W
10
-
9
8
*3
*3
R
R
Reset value
00101XXXB
bit12 bit11
CT1 CT0
0
0
1
0
0
1
1
1
Compare time select bit
44/φ (5.5 μs)*1
66/φ (4.12 μs)*2
88/φ (5.5 μs)*2
176/φ (11.0 μs)*2
bit14 bit13
ST1 ST0
0
0
1
1
R
W
X
φ
362
: Read only
: Write only
: Undefined
: Unused
: Machine clock
: Reset value
bit15
S10
0
1
0
1
0
1
Sampling time select bit
20/φ (2.5 μs)*1
32/φ (2.0 μs)*2
48/φ (3.0 μs)*2
128/φ (8.0 μs)*2
Resolution select bit
10 bits (D9 to D0)
8 bits (D7 to D0)
*1: The parenthesized values are provided when the machine clock
operates at 8-MHz
*2: The parenthesized values are provided when the machine clock
operates at 16-MHz
*3: Bit8 and bit9 are described in "A/D data register lower (ADCR: L)".
CHAPTER 13 8/10-bit A/D CONVERTER
Table 13.3-4 Functions of A/D Data Register (High) (ADCR: H)
bit name
Function
bit15
S10:
Resolution select bit
This bit selects the A/D conversion resolution.
When set to "0": Sets A/D conversion resolution in 10 bits
from A/D conversion data bits D9 to D0.
When set to "1": Sets A/D conversion resolution in 8 bits from
A/D conversion data bits D7 to D0.
Note:
Change the S10 bit in the pausing state before starting A/D
conversion.Changing the S10 bit after A/D conversion starts
disables the A/D conversion results stored in the A/D
conversion data bits (D9 to D0).
bit14,
bit13
ST1, ST0:
Sampling time select bits
These bits set the A/D conversion sampling time.
• These bits set the time required from when A/D conversion
starts until the input analog voltage is sampled and held by
the sample & hold circuit.
Note:
The setting of ST1 and ST0 =00B is based on operation at 8
MHz.Setting based on operation at 16 MHz does not assure
normal operation.When these bits are read,
"00B" is read.
bit12
bit11
CT1, CT0:
Compare time select bits
These bits set the A/D conversion compare time.
• These bits set the time required from when analog input is
A/D-converted until it is stored in the data bits (D9 to D0).
Note:
The setting of CT1 and CT0 =00B is based on operation at 8
MHz.Setting based on operation at 16 MHz does not assure
normal operation.When read, these bits return "00B".
363
CHAPTER 13 8/10-bit A/D CONVERTER
13.3.4
A/D Data Register (Low) (ADCR: L)
The A/D data register (Low) (ADCR: L) stores the A/D conversion results.
Bits 8 and 9 in the A/D data register (ADCR) in this section.
■ A/D Data Register (Low) (ADCR: L)
Figure 13.3-5 A/D Data Register (Low) (ADCR: L)
bit9
8
7
6
5
4
3
2
1
0
Reset value
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R
R
R
R
R
R
R
R
R
R
R : Read only
X : Undefined
Table 13.3-5 Functions of A/D Data Register (Low) (ADCR: L)
bit name
bit9
to
bit0
364
D9 to D0:
A/D conversion data bits
Function
These bits store the A/D conversion results.
When resolution set in 10 bits (S10 = 0):
Conversion data is stored in the 10 bits from D9 to D0.
When resolution set in 8 bits: Conversion data is stored in the
8 bits from D7 to D0.
Note:
Use a word instruction (MOVW) to read the A/D conversion
results stored in the A/D conversion data bits (D9 to D0).
CHAPTER 13 8/10-bit A/D CONVERTER
13.3.5
Analog input enable register (ADER)
The analog input enable register (ADER) enables or disables the analog input pins to be
used in the 8-/10-bit A/D converter.
■ Analog input enable register (ADER)
Figure 13.3-6 Analog input enable register (ADER)
7
6
5
4
3
2
1
0
Reset value
11111111B
R/W R/W R/W R/W R/W R/W R/W R/W
bit0
Analog input enable bit 0 (AN0)
ANE0
Analog input disabled
0
Analog inpug enabled
1
bit1
Analog input enable bit 1 (AN1)
ANE1
Analog input disabled
0
1
Analog inpug enabled
bit2
Analog input enable bit 2 (AN2)
ANE2
Analog input disabled
0
1
Analog inpug enabled
bit3
ANE3
Analog input enable bit 3 (AN3)
Analog input disabled
0
1
Analog inpug enabled
bit4
Analog input enable bit 4 (AN4)
ANE4
Analog input disabled
0
1
Analog inpug enabled
bit5
Analog input enable bit 5 (AN5)
ANE5
Analog input disabled
0
1
Analog inpug enabled
bit6
Analog input enable bit 6 (AN6)
ANE6
Analog input disabled
0
1
Analog inpug enabled
R/W
: Read/Write
: Reset value
bit7
Analog input enable bit 7 (AN7)
ANE7
Analog input disabled
0
1
Analog inpug enabled
365
CHAPTER 13 8/10-bit A/D CONVERTER
Table 13.3-6 Functions of Analog Input Enable Register (ADER)
bit name
bit7
to
bit0
Notes:
366
ADE7 to ADE0:
Analog input enable bits
Function
These bits enable or disable the analog input of the pin to be
used for A/D conversion.
When set to "0": Disables analog input
When set to "1": Enables analog input
• The analog input pins serve as a general-purpose I/O port of the port 5.To use the
pin as an analog input pin, set the port-5 direction register (DDR5) and analog
input enable register (ADER) to switch it to an analog input pin.
• When using the pin as an analog input pin, write 0 to the bit in the port 5 direction
register (DDR5) corresponding to the pin to be used and turn off the output
transistor.Also write "1" to the bit in the analog input enable register (ADER)
corresponding to the pin to be used and set the pin to analog input.
CHAPTER 13 8/10-bit A/D CONVERTER
13.4
Interrupt of 8-/10-bit A/D Converter
When A/D conversion is terminated and its results are stored in the A/D data register
(ADCR), the 8-/10-bit A/D converter generates an interrupt request.The EI2OS function
can be used.
■ Interrupt of A/D Converter
When A/D conversion of the analog input voltage is terminated and its results are stored in the A/D data
register (ADCR), the interrupt request flag bit in the A/D control status register (ADCS: INT) is set to
"1".When the interrupt request flag bit is set to "0" (ADCS: INT = 1) with an interrupt request output
enabled (ADCS: INTE = 1), an interrupt request is generated.
■ 8-/10-bit A/D Converter Interrupt and EI2OS
Reference:
For details of the interrupt number, interrupt control register, and interrupt vector
address, see 3.5 Interrupt.
■ EI2OS Function of 8-/10-bit A/D Converter
In the 8-/10-bit A/D converter, the EI2OS function can be used to transfer the A/D conversion results from
the A/D data register (ADCR) to memory.If the EI2OS function is used, the A/D-converted data protection
function is activated to cause A/D conversion to pause during memory transfer.The A/D-converted data
protection function is activated to prevent data loss as A/D conversion is performed continuously.
367
CHAPTER 13 8/10-bit A/D CONVERTER
13.5
Explanation of Operation of 8-/10-bit A/D Converter
The 8-/10-bit A/D converter has the following A/D conversion modes.Set each mode
according to the setting of the A/D conversion mode select bits in the A/D control status
register (ADCS: MD1, MD0).
• Single conversion mode (restartable/not-restartable during A/D conversion)
• Continuous conversion mode (not-restartable during A/D conversion)
• Pause conversion mode (not-restartable during A/D conversion)
■ Single-shot Conversion Mode (ADCS: MD1, MD0 =00B or 01B)
• When the start trigger is input, the analog inputs from the start channel (ADCS: ANS2 to ANS0) to the
end channel (ADCS: ANE2 to ANE0) are A/D-converted continuously.
• The A/D conversion pauses after A/D conversion for the end channel.
• To terminate A/D conversion forcibly, write "0" to the A/D conversion-on flag bit in the A/D control
status register (ADCS: BUSY).
• When the A/D conversion mode select bits (MD1, MD0) are set to "00B", this mode can be restarted
during A/D conversion.If the bits are set to "01B", this mode cannot be restarted during A/D conversion.
■ Continuous Conversion Mode (ADCS: MD1, MD0 =10B)
• When the start trigger is input, the analog inputs from the start channel (ADCS: ANS2 to ANS0) to the
end channel (ADCS: ANE2 to ANE0) are A/D-converted continuously.
• When A/D conversion for the end channel is terminated, it is continued after returning to the analog
input for the start channel.
• To terminate A/D conversion forcibly, write "0" to the A/D conversion-on flag bit in the A/D control
status register (ADCS: BUSY).
• This mode cannot be restarted during A/D conversion.
■ Pause-conversion Mode (ADCS: MD1, MD0 =11B)
• When the start trigger is input, A/D conversion starts for the start channel (ADCS: ANS2 to ANS0).The
A/D conversion pauses at termination of A/D conversion for a channel.When the start trigger is input
while A/D conversion pauses, A/D conversion for the next channel is started.
• The A/D conversion pauses at the termination of A/D conversion for the end channel.When the start
trigger is input while A/D conversion pauses, A/D conversion is continued after returning to the analog
input for the start channel.
• To terminate A/D conversion forcibly, write "0" to the A/D conversion-on flag bit in the A/D control
status register (ADCS: BUSY).
• This mode cannot be restarted during A/D conversion.
368
CHAPTER 13 8/10-bit A/D CONVERTER
13.5.1
Single-shot conversion mode
In the single conversion mode, A/D conversion is performed sequentially from the start
channel to the end channel.The A/D conversion pauses after A/D conversion for the end
channel.
■ Setting of Single-shot Conversion Mode
Operating the 8-/10-bit A/D converter in the single conversion mode requires the setting shown in Figure
13.5-1.
Figure 13.5-1 Setting of Single-shot Conversion Mode
bit15 14 13 12 11 10
ADCS
BUSY INT INTE PAUS STS1 STS0
9 bit8 bit7 6
0
ADCR
5
4
3
2
1 bit0
ReSTRT served
MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
S10 ST1 ST0 CT1 CT0 -
0
D9 to D0 (hold the conversion result)
ADER
- : Unused
: Used bit
: Setting "1" to corresponding bit using as analog input pin
0 : Setting "0"
■ Operation of Single-shot Conversion Mode
• When the start trigger is input, A/D conversion starts from the channel set by the A/D conversion start
channel select bits (ANS2 to ANS0) and is performed continuously up to the channel set by the A/D
conversion end channel select bits (ANE2 to ANE0).
• The A/D conversion stops at the termination of the A/D conversion for the channel set by the A/D
conversion end channel select bits (ANE2 to ANE0).
• To terminate A/D conversion forcibly, write "0" to the A/D conversion-on flag bit in the A/D control
status register (ADCS: BUSY).
• When the A/D conversion mode select bits (MD1, MD0) are set to "00B", this mode can be restarted
during A/D conversion. If the bits are set to "01B", this mode cannot be restarted during A/D
conversion.
[When start and end channels are the same]
• If the start and end channels have the same channel number (ADCS: ANS2 to ANS0 = ADCS: ANE2 to
ANE0), only one A/D conversion for one channel set as the start channel (= end channel) is performed
and terminated.
369
CHAPTER 13 8/10-bit A/D CONVERTER
[Conversion order in single-shot conversion mode]
Table 13.5-1 gives an example of the conversion order in the single-shot conversion mode.
Table 13.5-1 Conversion Order in Single-shot Conversion Mode
Start Channel
370
End Channel
Conversion Order in Single-shot Conversion Mode
AN0 pin
(ADCS: ANS=000B)
AN3 pin
(ADCS: ANE=011B)
AN0 → AN1 → AN2 → AN3 → End
AN6 pin
(ADCS: ANS=110B)
AN2 pin
(ADCS: ANE=010B)
AN6 → AN7 → AN0 → AN1 → AN2 → End
AN3 pin
(ADCS: ANS=011B)
AN3 pin
(ADCS: ANE=011B)
AN3 → End
CHAPTER 13 8/10-bit A/D CONVERTER
13.5.2
Continuous conversion mode
In the continuous conversion mode, A/D conversion is performed sequentially from the
start channel to the end channel.When A/D conversion for the end channel is
terminated, it is continued after returning to the start channel.
■ Setting of Continuous Conversion mode
Operating the 8-/10-bit A/D converter in the continuous conversion mode requires the setting shown in
Figure 13.5-2.
Figure 13.5-2 Setting of Continuous Conversion mode
bit15 14 13 12 11 10
ADCS
BUSY NT INTE PAUS STS1 STS0
9 bit8 bit7 6
0
ADCR
5
4
3
2
1 bit0
ReSTRT served
MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
S10 ST1 ST0 CT1 CT0 -
1
0
D9 to D0 (hold the conversion result)
ADER
-
1
0
: Unused
: Used bit
: Setting "1" to corresponding bit using as analog input pin
: Setting "1"
: Setting "0"
■ Operation of Continuous Conversion Mode
• When the start trigger is input, A/D conversion starts from the channel set by the A/D conversion start
channel select bits (ANS2 to ANS0) and is performed continuously up to the channel set by the A/D
conversion end channel select bits (ANE2 to ANE0).
• When A/D conversion for the channel set by the A/D conversion end channel select bits (ANE2 to
ANE0) is terminated, it is continued after returning to the channel set by the A/D conversion start
channel select bits (ANS2 to ANS0).
• To terminate A/D conversion forcibly, write "0" to the A/D conversion-on flag bit in the A/D control
status register (ADCS: BUSY).
• This mode cannot be restarted during A/D conversion.
[When start and end channels are the same]
• If the start and end channels have the same channel number (ADCS: ANS2 to ANS0 = ADCS: ANE2 to
ANE0), A/D conversion for one channel set as the start channel (= end channel) is repeated.
371
CHAPTER 13 8/10-bit A/D CONVERTER
[Conversion order in continuous conversion mode]
Table 13.5-2 gives an example of the conversion order in the continuous conversion mode.
Table 13.5-2 Conversion Order in Continuous Conversion Mode
Start Channel
372
End Channel
Conversion Order in Continuous Conversion Mode
AN0 pin
(ADCS: ANS=000B)
AN3 pin
(ADCS: ANE=011B)
AN0 → AN1 → AN2 → AN3 → AN0 → Repeat
AN6 pin
(ADCS: ANS=110B)
AN2 pin
(ADCS: ANE=010B)
AN6 → AN7 → AN0 → AN1 → AN2 → AN6 →
Repeat
AN3 pin
(ADCS: ANS=011B)
AN3 pin
(ADCS: ANE=011B)
AN3 → AN3 → Repeat
CHAPTER 13 8/10-bit A/D CONVERTER
13.5.3
Pause-conversion mode
In the pause-conversion mode, A/D conversion starts and pauses repeatedly for each
channel.When the start trigger is input after the A/D conversion pauses at the
termination of the A/D conversion for the end channel, A/D conversion is continued
after returning to the start channel.
■ Setting of Pause-conversion Mode
Operating the 8-/10-bit A/D converter in the pause-conversion mode requires the setting shown in Figure
13.5-3.
Figure 13.5-3 Setting of Pause-conversion Mode
bit15 14 13 12 11 10
ADCS
BUSY NT INTE PAUS STS1 STS0
9 bit8 bit7 6
0
ADCR
S10 ST1 ST0 CT1 CT0 -
5
4
3
2
1 bit0
ReSTRT served MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
1
1
D9 to D0 (hold the conversion result)
ADER
-
: Unused
: Used bit
: Setting "1" to corresponding bit using as analog input pin
1 : Setting "1"
0 : Setting "0"
■ Operation of Pause-conversion Mode
• When the start trigger is input, A/D conversion starts at the channel set by the A/D conversion start
channel select bits (ANS2 to ANS0).The A/D conversion pauses at the termination of the A/D
conversion for one channel.When the start trigger is input while A/D conversion pauses, A/D
conversion for the next channel is performed.
• The A/D conversion pauses at the termination of the A/D conversion for the channel set by the A/D
conversion end channel select bits (ANE2 to ANE0). When the start trigger is input while A/D
conversion pauses, A/D conversion is continued after returning to the channel set by the A/D conversion
start channel select bits (ANS2 to ANS0).
• To restart this mode while A/D conversion pauses, input the start trigger set by the A/D start trigger
select bits in the A/D control status register (ADCS: STS1, STS0).
• To terminate A/D conversion forcibly, write "0" to the A/D conversion-on flag bit in the A/D control
status register (ADCS: BUSY).
• This mode cannot be restarted during A/D conversion.
373
CHAPTER 13 8/10-bit A/D CONVERTER
[When start and end channels are the same]
• If the start and end channels have the same channel number (ADCS: ANS2 to ANS0 = ADCS: ANE2 to
ANE0), A/D conversion for one channel set as the start channel (= end channel), and pause are repeated.
[Conversion order in pause-conversion mode]
Table 13.5-3 gives an example of the conversion order in the pause-conversion mode.
Table 13.5-3 Conversion Order in Pause-conversion Mode
Start Channel
374
End Channel
Conversion Order in Single-shot Conversion Mode
AN0 pin
(ADCS: ANS=000B)
AN3 pin
(ADCS: ANE=011B)
AN0 → Stop, Start → AN1 → Stop, Start → AN2 →
Stop, Start → AN3 → Stop, Start → AN0 →
Repeat
AN6 pin
(ADCS: ANS=110B)
AN2 pin
(ADCS: ANE=010B)
AN6 → Stop, Start → AN7→ Stop, Start → AN0 →
Stop, Start → AN1 → Stop, Start → AN2 →
Stop, Start → AN6 → Repeat
AN3 pin
(ADCS: ANS=011B)
AN3 pin
(ADCS: ANE=011B)
AN3 → Stop, Start → AN3 → Stop, Start → Repeat
CHAPTER 13 8/10-bit A/D CONVERTER
13.5.4
Conversion Using EI2OS Function
The 8-/10-bit A/D converter can transfer the A/D conversion result to memory by using
the EI2OS function.
■ Conversion Using EI2OS
The use of the EI2OS enables the A/D-converted data protection function to transfer multiple data to
memory without the loss of converted data even if A/D conversion is performed continuously.
The conversion flow when the EI2OS is used is shown in Figure 13.5-4.
Figure 13.5-4 Flow of Conversion when Using EI2OS
A/D converter start-up
Sample & hold
A/D conversion start
A/D conversion finish
Interrupt generating
EI2OS start-up
Conversion result transmission
Specified count *
completed
NO
Interrupt clear
YES
Interrupt processing
*: The specitied count depends on the setting of the EI2OS
375
CHAPTER 13 8/10-bit A/D CONVERTER
13.5.5
A/D-converted Data Protection Function
A/D conversion with the output an interrupt request enabled activates the A/D
conversion data protection function.
■ A/D-converted Data Protection Function in 8-/10-bit A/D Converter
The 8-/10-bit A/D converter has only one A/D data register (ADCR) for holding A/D-converted data.
When the results of A/D conversion are determined upon completion, data in the A/D data register is
updated.Therefore, the A/D conversion results may be lost if the A/D conversion results already stored are
not read before data in the A/D data register is rewritten.The A/D-converted data protection function in the
8-/10-bit A/D converter is activated to prevent data loss. This function automatically causes A/D
conversion to pause when an interrupt request is generated (ADCS: INT = 1) with an interrupt request
enable
● A/D-converted data protection function when EI2OS not used
• When the A/D conversion results are stored in the A/D data register (ADCR) after the analog input is A/
D-converted, the interrupt request flag bit in the A/D control status register (ADCS: INT) is set to "1".
• A/D conversion pauses for data protection while the interrupt request flag bit in the A/D control status
register (ADCS: INT) is set.
• When the INT bit is set with an interrupt request from the A/D control status register enabled (ADCS:
INTE = 1), an interrupt request is generated.When the INT bit is cleared by the generated interrupt
processing, the pause of A/D conversion is cancelled.
● A/D-converted data protection function when EI2OS used
• A/D conversion pauses for data protection while the EI2OS function is used to transfer the A/D
conversion results to memory from the A/D data register after A/D conversion.When A/D conversion
pauses, the pause flag bit in the A/D control status register (ADCS: PAUS) is set to "1".
• When the transfer of the A/D conversion results to memory by the EI2OS function is terminated, the
pause of A/D conversion is cancelled and the pause flag bit (ADCS: PAUS) is cleared to "0". If A/D
conversion is performed continuously, it is restarted.
376
CHAPTER 13 8/10-bit A/D CONVERTER
● Processing flow of A/D conversion data protection function when EI2OS used
Figure 13.5-5 shows the processing flow of the A/D conversion data protection function when the EI2OS is
used.
Figure 13.5-5 Processing flow of A/D conversion data protection function when EI2OS used
EI2OS setting
A/D sequential conversion
start-up
One time conversion finish
Store in A/D data register
EI2OS start-up
Two time conversion finish
EI2OS finish
NO
A/D temporal stop
YES
Store in A/D data register
Third conversion
EI2OS start-up
Continued
All conversion finish
EI2OS start-up
Interrupt processing
A/D conversion stop
Finish
Note : The operation flow of when the A/D converter is stopped is omitted.
377
CHAPTER 13 8/10-bit A/D CONVERTER
Notes:
378
• The A/D conversion data protection function is activated only when an interrupt
request is enabled.Set the interrupt request enable bit in the A/D control status
register (ADCS: INTE) to "1".
• When the EI2OS function is used to transfer the A/D conversion results to
memory, do not disable output of an interrupt request.If output of an interrupt
request is disabled during a pause of A/D conversion (ADCS: INTE = 0), A/D
conversion may be restarted to rewrite data being transferred.
• When the EI2OS function is used to transfer the A/D conversion results to
memory, do not restart.Restarting during a pause of A/D conversion may cause
loss of the A/D conversion results.
CHAPTER 13 8/10-bit A/D CONVERTER
13.6
Precautions when Using 8-/10-bit A/D Converter
Precautions when using the 8-/10-bit A/D converter are given below:
■ Precautions when Using 8-/10-bit A/D Converter
● Analog input pin
• The analog input pins serve as a general-purpose I/O port of the port 5.To use the pin as an analog input
pin, set the port-5 direction register (DDR5) and analog input enable register (ADER) to switch it to an
analog input pin.
• When using the pin as an analog input pin, write "0" to the bit in the port 5 direction register (DDR5)
corresponding to the pin to be used and turn off the output transistor. Also write "1" to the bit in the
ADER corresponding to the pin to be used and set the pin to analog input enable.
• When an intermediate-level signal is input with the pin set as a general-purpose I/O port, the input
leakage current flows in the gate. When using the pin as an analog input pin, always set the pin to
analog input enable.
● Precaution when starting by internal timer or external trigger
• The input value at which the 8-/10-bit A/D converter is started by the internal timer output or external
trigger should be set to inactive (High for external trigger).Holding the input value for the start trigger
active may cause the 8-/10-bit A/D converter to start concurrently with the setting of the A/D start
trigger select bits in the A/D control status register (ADCS: STS1, STS0).
● Procedure of 8-/10-bit A/D converter and analog input power-on
• Always apply a power to the A/D converter power and the analog input (AN0 to AN7 pins) after or
concurrently with the digital power (VCC)-on.
• Always turn off the A/D converter power and the analog input before or concurrently with the digital
power-down.Note that AVR should not exceed AVCC at power on or power down.
● Power supply voltage of 8-/10-bit A/D converter
• To prevent latch up, note that the 8-/10-bit A/D converter power (AVCC) should not exceed the digital
power (VCC) voltage.
379
CHAPTER 13 8/10-bit A/D CONVERTER
380
CHAPTER 14
UART0
This chapter explains the functions and operation of the
UART0.
14.1 Overview of UART0
14.2 Block Diagram of UART0
14.3 Configuration of UART0
14.4 Interrupt of UART0
14.5 UART0 baud rate
14.6 Explanation of Operation of UART0
14.7 Precautions when using UART0
381
CHAPTER 14 UART0
14.1
Overview of UART0
The UART0 is a general-purpose serial-data communication interface for synchronous
or asynchronous communication with external devices.
• Incorporates a bidirectional communication function (clock synchronous and
asynchronous modes)
• The master/slave communication function (multiprocessor mode) is incorporated.
• Capable of generating an interrupt request upon transmission, reception, or detection
of a reception error.
• Supports expansion intelligent I/O service (EI2OS)
■ Functions of UART0
● Functions of UART0
The UART0 is a general-purpose serial data communication interface to exchange serial data with external
devices. Its functions are listed in Table 14.1-1.
Table 14.1-1 Function of UART0
Function
Data buffer
Transfer mode
Baud rate
• Special-purpose baud-rate generator, selectable 10 types
• Any baud rate can be set by external clock.
• A clock supplied from the internal clock (16-bit reload timer
0) can be used.
• 7 bits (for asynchronous normal mode only)
• 8 bits
Signal type
NRZ (Non Return to Zero) type
interrupt request
Master/slave type communication
function (multi processor mode)
382
• Synchronous to clock (without start bit/stop bit and parity
bit)
• Asynchronous (start-stop synchronization to clock)
Data length
Detection of receive error
Note:
Full-duplicate double-buffer
• Framing error
• Overrun error
• Parity error (Not supported in operation mode 1)
• Detection of receive error
• Transmission interrupt (Transmission)
• Both the transmission and reception support EI2OS.
This function enables communications between 1 (only use
master) and n (slave) (This function is used only as the master
side)
At clock synchronous transfer, data is transferred alone with neither start nor stop bit
added.
CHAPTER 14 UART0
Table 14.1-2 Operation Mode of UART0
Data length
Operating mode
With Parity
0
Normal mode
1
Multiprocessor
mode
2
Clock
synchronous
mode
No Parity
7 bits or 8 bits
Synchronous
type
Length of Stop
Bit
Asynchronous
1 bit or 2 bits*2
8+1*1
-
Asynchronous
8
-
Clock
synchronous
None
-:Setting disabled
*1:"+1" is the address/data select bit (SCR: A/D) used for controlling communications.
*2: During reception, only one bit can be detected as the stop bit.
383
CHAPTER 14 UART0
14.2
Block Diagram of UART0
The UART0 consists of the following block.
■ Block Diagram of UART0
Figure 14.2-1 Block Diagram of UART0
Control bus
Dedicated
baud rate
generator
Reception
interrupt
request output
Transmission
clock
16-bit
reload timer
Clock
selector Reception
clock
Pin
SCK
Reception
control
cirsuit
Transmission
control
circuit
Start bit
detection circuit
Transmission
start circuit
Reception bit
counter
Transmission
bit counter
Reception parity
counter
Transmission
parity counter
Transmission
interrupt
request output
Pin
SOT
Shift register
for transmission
Shift register
for reception
Pin
SIN
Reception state
judge circuit
Serial input
data register
Reception
complete
Serial outpu
data register
Transmission
start
Reception error
generating signal
for EI2OS (to CPU)
Internal data bus
Serial
edge
select
register
NEG
384
Communi
-cation
prescaler
control
register
Serial
mode
DIV3
DIV2 register
DIV1
DIV0
MD
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
Serial
control
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
Serial
status
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
CHAPTER 14 UART0
● Details of Pins in Block Diagram
The actual pin names and interrupt request numbers used in the UART0 are as follows:
SCK pin: P31/SCK0/RD
TX pin: P43/TX: P30/SOT0/ALE
SIN pin: P32/SIN0/WRL
Transmit interrupt number: #39 (27H)
Receive interrupt number: #40 (28H)
● Clock selector
The clock selector selects the transmission/reception clock from among the dedicated baud rate generator,
external input clock, and internal clock (clock supplied from 16-bit reload timer 0).
● Reception control circuit
The receive controller is composed of receive bit counter, start bit detector and receive parity counter.The
receive bit counter counts received data and outputs a receive interrupt request when the reception of one
frame of data is completed.
The start bit detection circuit detects a start bit in a serial input signal and writes the received data to the
serial input data register while shifting bit by bit according to the transfer rate.The receive parity counter
calculates parity in received data.
● Transmission control circuit
The transmit controller is composed of the transmit bit counter, transmit start circuit, and transmit parity
counter.The transmit bit counter counts the data to transmit and outputs a transmission interrupt request
when the transmission of one frame of data is completed.The transmit start circuit starts transmission when
serial output data register (SODR) is written to.The transmit parity counter generates the parity bit of the
data transferred when parity is provided.
● Receive shift register
The receive shift register captures the receive data input from the SIN pin while shifting bit by bit and,
upon completion of reception, transfers the received data to the serial input data register.
● Transmit shift register
Data written to the serial output data register is transferred to the transmit shift register to output the data to
the SOT pin while shifting bit by bit.
● Serial mode register 0 (SMR0)
The serial mode register (SMR0) is used to select the operation mode, select the clock input source (baud
rate), and to enable or disable serial data and clock pin outputs.
● Serial control register (SCR)
The register is used to select whether to use parity, select the type of parity, set the stop bit length and data
length, select the frame data format in operation mode 1, clear the error flag, and to enable/disable
385
CHAPTER 14 UART0
transmission and reception.
● Serial status register (SSR)
The status register checks the transmission/reception status and error status and enables/disables
transmission/reception interrupt requests.
● Serial input data register
The register retains the receive data.The serial input is converted and then stored in this register.
● Serial output data register 0 (SODR0)
The register sets the transmit data.Data written to this register is serial-converted and then output.
● Communication Prescaler Control Register (CDCR0)
The control register sets the baud rate of the baud rate generator.It sets the start/stop of the communication
prescaler and the division rate of machine clock.
● Serial edge select register (SES0)
The register is an inverter that inverts a clock signal.The register inverts the shift clock signal from Low
level to High level or from High level to Low level.
386
CHAPTER 14 UART0
14.3
Configuration of UART0
The UART0 pins, interrupt factors, register list and details are shown.
■ Pins of UART0
The pins used in the UART0 serve also as general-purpose I/O ports.
Table 14.3-1 indicates the pin functions and the setting necessary for use in the UART0.
Table 14.3-1 Pins of UART0
Pin Name
Pin Function
SOT0
General-purpose I/O port,
Address latch enable output/
serial data output
SCK0
General-purpose I/O port,
read strobe output/
serial clock output input
SIN0
General-purpose I/O port,
Write strobe output pin for lower 8
bits in data bus/
serial data input
Setting Necessary for Use in UART0
Set to output enable.
(SMR0: SOE=1)
In clock input, set pin as input port in port
direction register (DDR).
In clock output, set to output enable.
(SMR0: SCKE=1)
Set as input port in port direction register
(DDR).
■ Block Diagram of Pins of UART0
Reference:
For the block diagram of the pins, see "CHAPTER 4 I/O PORT".
387
CHAPTER 14 UART0
■ List of Registers in UART0
Figure 14.3-1 List of Registers and Reset Values in UART0
bit
Serial control register (SCR0)
bit
Serial mode register (SMR0)
bit
Serial status register (SSR0)
bit
Serial input data register (SIDR0)
/serial output data register (SODR0)
15
14
13
12
11
10
9
8
0
0
0
0
0
1
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
1
×
0
0
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
Note : Function as SIDR0 when reading, function as SODR0 when writing
bit
Serial edge select register (SES0)
bit
Communication prescaler control
register (CDCR0)
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
0
7
6
5
4
3
2
1
0
0
×
×
×
1
1
1
1
× : Undefined
■ Interrupt Request Generation by UART0
● Reception Interrupt
• When received data is loaded into the serial input data register (SIDR0), the receive data load flag bit
(SSR0: RDRF) in the serial status register is set to "1".When reception interrupts have been enabled
(SSR0: RIE = 1), a reception interrupt request is generated.
• When either a framing error, overrun error, or parity error occurs, the framing error flag bit (SSR0:
FRE), the overrun error flag bit (SSR0: ORE), or parity error flag bit (SSR0: PE) in the serial status
register are set to "1" according to the error occurred. When reception interrupts have been enabled
(SSR0: RIE = 1), a reception interrupt request is generated.
● Transmission Interrupt
The transmit data empty flag bit (SSR0: TDRE) in the serial status register is set to "1" when data to
transmit is transferred from the serial output data register (SODR0) to the transmission shift
register.Interrupt requests are generated while transmission interrupts are enabled (SSR0: TIE = 1).
388
CHAPTER 14 UART0
14.3.1
Serial control register 0 (SCR0)
Serial control register 0 (SCR0) is used to set the parity bit, select the stop bit length
and data length, select the frame data format in operation mode 1, clear the reception
error flag, and to enable/disable transmission and reception.
■ Serial control register (SCR0)
Figure 14.3-2 Serial control register (SCR0)
15
14
13
12
11
10
9
8
Reset value
00000100B
R/W R/W R/W R/W R/W
W
R/W R/W
bit8
TXE
0
1
bit9
RXE
0
1
bit10
REC
0
1
bit11
A/D
0
1
bit12
CL
0
1
bit13
SBL
0
1
Transmission operating enable bit
Transmission operating disabled
Transmission operating enabled
Reception operating enable bit
Reception operating disabled
Reception operating enabled
Reception error flag clear bit
Clear FRE, ORE and PE flag
No effection
Address/data select bit
Data frame
Address frame
Data length select bit
7 bits
8 bits
Stop bit length select bit
1 bit length
2 bit length
bit14
P
0
1
R/W : Read/Write
W
: Write only
: Reset value
bit15
PEN
0
1
Parity select bit
Only valid with parity (PEN=1)
Even parity
Odd parity
Parity append enable bit
Without parity
With parity
389
CHAPTER 14 UART0
Table 14.3-2 Functions of Serial Control Register 0 (SCR0)
bit name
Function
bit15
PEN:
Parity addition enable bit
Specify whether to add (at sending) and detect (at receiving) a parity bit.
Note:
In operation modes 1 and 2, no parity bit can be added. Always set this bit to
"0".
bit14
P:
Parity select bit
Select either odd or even parity when the use of the parity bit has been selected
(SCR0: PEN = 1).
bit13
SBL:
Stop-bit length select bit
Set the length of the stop bits (transmit data’s frame end mark) in operation modes 0
and 1 (asynchronous).
Note:
At receiving, only the first bit of the stop bit is always detected.
bit12
CL:
Data-length select bit
Specify the length of send and receive data.
Note:
A data length of seven bits can be selected only in operation mode 0.In operation
modes 1 and 2, be sure to set a data length of 8 bits.
bit11
A/D:
Address/data select bit
In operation mode 1, set the data format of frames to be transmitted/received.
When the bit is set to "0": The frame format is set to data frame.
When the bit is set to "1": The frame format is set to address data frame.
bit10
REC:
Receive error flag clear
bit
Clear the reception error flags (SSR0: FRE, ORE, PE) in the serial status register to
"0".
When the bit is set to "0": The FRE, ORE, and PE flags are cleared.
When the bit is set to "1": No effect.
Read: "1" is always read.
Note:
If reception interrupts have been enabled (SSR0: RIE = 1), set the REC bit to "0"
only when any of the FRE, ORE, and PE flags contains "1".
bit9
RXE:
reception enable bit
The bit enables or disables the UART0 for reception.
When the bit is set to "0": Reception is disabled.
When the bit is set to "1": Reception is enabled.
Note:
When reception is disabled, the device stops reception after storing the currently
received data to the serial input data register.
bit8
TXE:
transmit enable bit
The bit enables or disables the UART0 for transmission.
When the bit is set to "0": Transmission is disabled.
When the bit is set to "1": Transmission is enabled.
Note:
When transmission is disabled, the device stops transmitting after transmitting
the current data from the serial output data register.
Before setting the bit to "0", write data to the serial output data register
(SODR0) and wait for a time of at least one sixteenth of the baud rate in the
asynchronous mode or for a time at least equal to the baud rate in the
synchronous mode.
390
CHAPTER 14 UART0
14.3.2
Serial mode register 0 (SMR0)
Serial mode register 0 (SMR0) is used to select the operation mode, select the baud rate
clock, and to disable/enable the output of serial data and clock signal to pins.
■ Serial mode register 0 (SMR0)
Figure 14.3-3 Serial mode register 0 (SMR0)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit0
Serial data output enable bit (SOT0 pin)
SOE
General purpose I/O port
0
Output of UART0 serial data
1
bit1
SCKE
Serial clock I/O enable bit (SCK0 pin)
Clock I/O pin of general purpose I/O port or UART0
0
1
Serial clock I/O pin of UART0
bit2
Reserved bit
Reserved
0
Be sure to set to "0"
bit5 bit4 bit3
CS2 CS1 CS0
Clock input cource select bit
"000B" to "100B" Baud rate by dedicated baud rate generater
Setting disabled
"101B"
Baud rate internal timer
"110B"
(16-bit reload timer 0)
"111B"
bit7
bit6
MD1 MD0
R/W : Read/Write
: Reset value
Baud rate by external clock
Operating mode select bit
Mode No.
Operating mode
0
0
0
Asynchronous normal mode
0
1
1
Asynchronous multiprocessor mode
1
0
2
Clock synchronous mode
1
1
-
Setting disabled
391
CHAPTER 14 UART0
Table 14.3-3 Functions of Serial Mode Register 0 (SMR0)
bit name
Function
bit7,
bit6
MD1, MD0:
Operation mode select
bits
Select the UART0 operation mode.
Note:
In operation mode 1, the device can be used only as the master for master/slave
communication.1)In operation mode 1, the address/data bit as bit 9 cannot be
received, so the device cannot be used as the slave.
In operation mode 1, set the parity addition enable bit to no parity
(SCR0: PEN = 0) as the parity check function cannot be used.2).
bit5
to
bit3
CS2 to CS0:
Clock input source select
bits
Set the clock input source for the baud rate.
• Select the external clock (SCK1 pin), internal timer (16-bit reload timer), or
dedicated baud rate generator as the clock input source.
• Set the baud rate when selecting the baud rate generator.
Note:
If the dedicated baud rate generator is used at synchronous transfer, the
following settings are the prohibitions.
1) CS2 to CS0=000B
2) CS2 to CS0=001B and DIV3 to DIV0=0000B
bit2
Reserved: reserved bit
Always set this bit to "0".
bit1
SCKE:
Serial clock I/O enable
bit
The serial clock input/output is switched.
When the bit is set to "0": The pin is set as a general-purpose I/O port or serial
clock input pin.
When the bit is set to "1": The pin is set as a serial clock output pin.
Note:
When using the SCK1 pin as the serial clock input, set the pin to the input port
using the port direction register (DDR1). Also, use the clock input source select
bit to select the external clock (SMR0: CS2 to CS0 =111B).
When using the pin as the serial clock output, set the clock input source select
bits to anything other than the external clock (SMR0: CS2 to CS0 = other than
"111B").
bit0
SOE:
Serial-data output enable
bit
Enable or disable output of serial data.
When the bit is set to "0": The pin is set as a general-purpose I/O port.
When the bit is set to "1": The pin is set as a serial data output pin.
392
CHAPTER 14 UART0
14.3.3
Serial status register 0 (SSR0)
Serial status register 0 (SSR0) is used to check the reception/transmission status and
error status and to enable/disable interrupts.
■ Serial status register (SSR0)
Figure 14.3-4 Serial status register (SSR0)
15
14
13
12
11
10
R
R
R
R
R
-
9
8
Reset value
00001X00B
R/W R/W
bit8
TIE
0
1
bit9
RIE
0
1
bit11
TDRE
0
1
bit12
RDRF
0
1
R/W : Read/Write
R
: Read only
X
: Undefined
: Unused
-
Transmission interrupt enable bit
Transmission interrupt disabled
Transmission interrupt enabled
Reception interrupt enable bit
Reception interrupt disabled
Reception interrupt enabled
Transmission data writing flag bit
With transmission data (writing of transmission data disabled)
Without transmission data (writing of transmission data enabled)
Reception data load flag bit
Without reception data
With reception data
bit13
FRE
0
1
Framing error flag bit
Without framing error
bit14
ORE
0
1
Over run error flag bit
Without over run error
bit15
PE
0
1
Parity error flag bit
Without parity error
With framing error
With over run error
With parity error
: Reset value
393
CHAPTER 14 UART0
Table 14.3-4 Function of Serial Status Register 0 (SSR0)
bit name
Function
bit15
PE:
parity error flag bit
Detect an overrun error in receiving.
• This bit is set to "1" when a parity error occurs.
• The flag is cleared by writing "0" to the reception error flag clear bit (SCR0:
REC).
• When reception interrupts have been enabled (SSR0: RIE = 1), a reception
interrupt request is generated if a parity error occurs.
• When the parity error flag bit is set (SSR0: PE = 1), data in serial input data
register 0 is made invalid.
bit14
ORE:
Overrun error flag bit
Detect an overrun error in receiving.
• This bit is set to "1" when an overrun error occurs.
• The flag is cleared by writing "0" to the reception error flag clear bit (SCR0:
REC).
• When reception interrupts have been enabled (SSR0: RIE = 1), a reception
interrupt request is generated if an overrun error occurs.
• When the overrun error flag bit is set (SSR0: ORE = 1), data in serial input data
register 0 is made invalid.
bit13
FRE:
flaming error flag bit
Detect a framing error in receive data.
• This bit is set to "1" when a framing error occurs.
• The flag is cleared by writing "0" to the reception error flag clear bit (SCR0:
REC).
• When reception interrupts have been enabled (SSR0: RIE = 1), a reception
interrupt request is generated if a framing error occurs.
• When the framing error flag bit is set (SSR0: FRE = 1), data in serial input data
register 0 is made invalid.
bit12
RDRF:
Receive data load flag bit
Show the status of the serial input data register 0.
• When received data is loaded to serial input data register 0 (SSR0), the receive
data load flag bit (SSR0: RDRF) is set to "1".
• The bit is cleared to 0 when data is read from serial input register 0 (SIDR0).
• When reception interrupts have been enabled (SSR0: RIE = 1), a reception
interrupt request is generated if received data is loaded into the serial input data
register (SIDR0).
bit11
TDRE:
Transmit data write flag
bit
Show the status of the serial output data register 0.
• The flag is cleared to "0" when transmit data is written to serial output data
register 0 (SODR0).
• This bit is set to "1" when data is loaded to the send shift register and
transmission starts.
• A transmission interrupt request is generated when the transmit data written to
serial output data register 0 (SODR0) is transferred to the transmission shift
register with transmission interrupts enabled (SSR0: TIE = 1).
bit10
Unused bits
Read: The value is undefined.
Write: No effect
bit9
RIE:
Interrupt enable bit
Enable or disable receive data.
When the bit is set to "1": A reception interrupt request is generated either when
received data is loaded to serial input data register 0
(SSR0: RDRF = 1) or when a reception error occurs
(SSR0: PE = 1, DRE = 1, or FRE = 1).
bit8
TIE:
Transmission interrupt
enable bit
Enable or disable send interrupt.
When the bit is set to "1": A transmission interrupt request is generated when the
data written to serial output data register 0 is
transmitted to the send shift register (SSR0:TDRE=1).
394
CHAPTER 14 UART0
14.3.4
Serial Input Data Register 0 (SIDR0) and Serial Output
Data Register 0 (SODR0)
The serial input data register and serial output data register are allocated to the same
address.The register functions as the serial data input register at a read; the register
functions as the serial data output register at a write.
■ Serial input data register 0 (SIDR0)
Figure 14.3-5 Serial input data register 0 (SIDR0)
R : Read only
X : Undefined
bit7
6
5
4
3
2
1
bit0
Reset value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R
R
R
R
R
R
R
R
SIDR0 is a data buffer register for receiving serial data.
• The serial data signal sent to the serial input pin (SIN0) is converted by the shift register and stored in
serial input data register 0 (SIDR0).
• When the data length is 7 bits, the upper one bit (SIDR1: D7) becomes invalid.
• When received data is stored in serial input data register 0 (SIDR0), the receive data load flag bit (SSR0:
RDRF) is set to "1".When reception interrupts have been enabled (SSR0: RIE = 1), a reception interrupt
request is generated.
• Serial input data register 0 (SIDR0) should be read with the receive data load flag bit (SSR0: RDRF)
containing "1".When serial input data register 0 (SIDR0) is read, the receive data load flag (SSR0:
RDRF) is automatically cleared to "0".
• When a reception error occurs (SSR0: PE, ORE, or FRE =1), received data in serial input data register 0
(SIDR0) is made invalid.
395
CHAPTER 14 UART0
■ Serial output data register 0 (SODR0)
Figure 14.3-6 Serial output data register 0 (SODR0)
W : Write only
X : Undefined
7
6
5
4
3
2
1
bit0
Reset value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
W
W
W
W
W
W
W
W
The serial output data register 0 (SODR0) is a data buffer register for transmitting serial data.
• When data to transmit is written to serial output data register 0 (SODR0) with transmission enabled
(SCR0: TXE = 1), the transmit data is transferred to the transmission shift register, converted to serial
data, then output from the serial data output pin (SOT0 pin).
• When the data length is seven bits, the data in upper one bit (D7) is invalid.
• The transmit data write flag (SSR0: TDRE) is cleared to 0 when data to transmit is written to serial
output data register 0 (SODR0).
• The transmit data write flag is set to "1" at completion of data transfer to the transmit shift register.
• The next data to transmit can be written when the transmit data write flag (SSR0: TDRE) contains
"1".Transmission interrupts occur while enabled (SSR0: TIE = 1).The succeeding transmit bit data
should be written with the transmit data write flag (SODR: TDRE) containing "1".
Note:
396
The serial output data register is a write-only register and the serial input data
register is a read-only register.Since the same address is allocated to the two
registers, the values written and read are different.Instructions, such as the INC/DEC
instruction, which provide the read modify write (RMW) operation cannot be used.
CHAPTER 14 UART0
14.3.5
Communication Prescaler Control Register 0 (CDCR0)
The communication prescaler control register 0 (CDCR0) is used to set the baud rate of
the dedicated baud rate generator for the UART0.
• Starts/stop the communication prescaler
• Sets the division ratio for machine clock
■ Communication Prescaler Control Register 0 (CDCR0)
Figure 14.3-7 Communication Prescaler Control Register
7
6
5
4
R/W
-
-
-
3
2
1
0
Reset value
0XXX1111B
R/W R/W R/W R/W
bit3 bit2 bit1 bit0
DIV3 DIV2 DIV1 DIV0 Communication prescaler dividing ratio (div) bit
1
1
1
1
Setting disabled
1
1
1
0
Dividing by 2
1
1
0
1
Dividing by 3
1
1
0
0
Dividing by 4
1
0
1
1
Dividing by 5
1
0
1
0
Dividing by 6
1
0
0
1
Dividing by 7
1
0
0
0
Dividing by 8
bit7
MD
R/W
X
-
: Read/Write
: Undefined
: Unused
: Reset value
Communication prescaler control bit
0
Communication prescaler operating stop
1
Communication prescaler operating enabled
397
CHAPTER 14 UART0
Table 14.3-5 Functions of Communication Prescaler Control Register
bit name
Function
bit7
MD:
Communication
prescaler control bit
The bit enables or disables the communication prescaler.
When the bit is set to "0": Operation stops.
When the bit is set to "1": Operation starts.
bit6
to
bit4
Unused bits
Read: The value is undefined.
Write: No effect
bit3
to
bit0
DIV3 to DIV0:
Communication
prescaler division ratio
bits
• These bits set the machine clock division ratio.
Note:
When changing the division ratio, the time of at least two cycles of the division
clock should be allowed before the next communication is started in order to
stabilize the clock frequency.
Note:
398
If the dedicated baud rate generator is used at synchronous transfer, the following
settings are the prohibitions.
1) CS2 to CS0=000B
2) CS2 to CS0=001B and DIV3 to DIV0=0000B
CHAPTER 14 UART0
14.3.6
Serial edge select register 0 (SES0)
Serial edge select register 0 (SES0) inverts the clock signal of the UART0 using an
inverter.The register logically inverts the shift clock signal input to the UART0 from Low
level to High level and from falling edge to rising edge, or from High level to Low level
and from rising edge to falling edge.The inversion acts on the serial clock output, too.
■ serial edge select register 0 (SES0)
Figure 14.3-8 serial edge select register 0 (SES0)
15
14
13
12
11
10
9
8
Reset value
XXXXXXX0B
-
-
-
R/W
-
-
: Unused
: Read/Write
: Reset value
-
-
-
R/W
bit8
NT
0
1
Clock inversion bit
Normal
Convert shift clock signal
Table 14.3-6 Functions of serial edge select register 0 (SES0)
bit name
Function
bit15
to
bit9
Unused bits
Read: The value is undefined.
Write: No effect
bit8
NT:
Clock reverse bit
The bit inverts the clock signal input to the UART0.
• Signals are inverted from Low level to High level or from High level to Low
level.
• The inversion acts on the serial clock output, too.
399
CHAPTER 14 UART0
14.4
Interrupt of UART0
The UART0 has reception and transmission interrupts and can generate interrupt
requests in the following events.
• Receive data is loaded to the serial input data register 0 (SIDR0).
• A receive error (parity error, overrun error, framing error) occurs.
• When data to transmit is transferred from serial output data register 0 (SODR0) to the
transmission shift register.
These are ready for expanded intelligent I/O service (EI2OS).
■ Interrupt of UART0
The UART0 interrupt control bits and interrupt factors are shown in Table 14.4-1.
Table 14.4-1 UART0 Interrupt Control Bit and Interrupt Factor
Transmission/
Reception
Interrupt
request
flag bit
Operating
mode
0
1
Receive data loaded
into serial input data
register 0 (SIDR0)
Overrun error
SSR0:ORE
SSR0:FRE
SSR0:PE
Transmission
: using bit
×: Unused bit
400
SSR0:
TDRE
Interrupt factor
enable bit
2
SSR0:
RDRF
Reception
Interrupt Factor
×
×
Framing error
×
generating parity
error
Serial output data
register 0 (SODR)
is empty.
Clear of the
Interruptrequest Flag
Reading receive
data
SSR0: RIE
SSR0: TIE
Writing "0" to
the reception
error flag clear
bit (SSR0: REC)
Writing transmit
data
CHAPTER 14 UART0
● Reception Interrupt
When a receive interrupt is enabled (SSR0: RIE = 1), a receive interrupt request is issued at completion of
data receiving (SSR0: RDRF = 1) or when any one of the overrun error (SSR0: ORE = 1), framing error
(SSR0: FRE = 1), and parity error (SSR0: PE = 1) occurs.
When serial input data register 0 (SIDR0) is read, the receive data load flag (SSR0: RDRF) is automatically
cleared to 0.Each reception error flag (SSR0: PE, ORE, FRE) is cleared to "0" when "0" is written to the
reception error flag clear bit (SCR0: REC).
Note:
If a reception error (parity error, overrun error, or framing error) occurs, correct the
error as necessary, and then write "0" to the reception error flag clear bit (SCR0:
REC) to clear each reception error flag.
● Transmission Interrupt
The transmit data write flag bit (SSR0: TDRE) is set to "1" when data to transmit is transferred from serial
output data register 0 (SODR0) to the transmission shift register.
If the transmission interrupt enable bit (SSR0: TIE) contains 1, a transmission interrupt request is
generated.
■ Interrupt Related to UART0 and EI2OS
Note:
For details of the interrupt number, interrupt control register, and interrupt vector
address, see "3.5 Interrupt".
■ EI2OS Function of UART0
The UART0 supports EI2OS.Consequently, EI2OS can be started separately for receive interrupts and
transmit interrupts.
● At reception:
MB90895 series cannot use interrupt vectors as it contains no I2C interface.
● At transmission:
Since the interrupt control register (ICR14) is shared with the UART0 for reception interrupts, EI2OS can
be started only when no interrupt is used for transmission by the UART0.
401
CHAPTER 14 UART0
14.4.1
Generation of Receive Interrupt and Timing of Flag Set
Interrupts during reception are one generated upon completion of reception
(SSR:RDRF) and one generated upon occurrence of a reception error (SSR:PE, ORE,
FRE).
■ Generation of Receive Interrupt and Timing of Flag Set
● Receive data load flag and each receive error flag sets
When data is received, it is stored in serial input data register 0 (SIDR0) upon detection of the stop bit (in
operation mode 0 or 1) or of the data’s last bit (SIDR0: D7) (in operation mode 2).When a reception error
occurs, the corresponding error flag (SSR0:PE, ORE, or FRE) is set and the receive data load flag (SSR0:
RDRF) is set as well.In each operation mode, the received data in the serial input data register 0 (SIDR0) is
invalid if either error flag is set.
Operation mode 0 (Asynchronous normal mode)
The receive data load flag bit (SSR0: RDRF) is set upon detection of the stop bit.When a reception occurs,
the error flag (SSR0: ORE) is set.
Operating mode 1 (asynchronous multiprocessor mode)
The receive data load flag bit (SSR0: RDRF) is set when the stop bit is detected.When a reception occurs,
the error flag (SSR0: ORE) is set.But parity errors cannot be detected.
Operating mode 2 (clock synchronous mode)
The receive data load flag bit (SSR0: RDRF) is set to "1" upon detection of the last bit (SIDR0: D7) of the
received data.When a reception occurs, the error flag (SSR0: ORE) is set.Neither a parity error (SSR0: PE)
nor a framing error (SSR0: FRE) can be detected.
402
CHAPTER 14 UART0
Reception and timing of flag set are shown in Figure 14.4-1.
Figure 14.4-1 Reception and Timing of Flag Set
Reception data
(operating mode 0)
ST
D0
D1
D5
D6
D7
SP
Reception data
(operating mode 1)
ST
D0
D1
D6
D7
A/D
SP
D0
D1
D4
D5
D6
D7
Reception data
(operating mode 2)
SSR0 : PE, ORE, FRE *
SSR0 : RDRF
Reception interrupt generating
* : PE flag is disabled to detect in mode 1.
PE and FRE flag are disabled to detect in mode 2.
ST : Start bit
SP : Stop bit
A/D : Address/data select bit in operating mode 2.
● Timing of receive interrupt request generation
With a receive interrupt enabled (SSR0: RIE = 1), when a receive interrupt request is issued when any one
of the receive data load flag (SSR0: RDRF), parity error flag (SSR0: PE), and overrun error flag (SSR0:
ORE) and framing error flag (SSR0: FRE) is set, reception interrupt is requested.
403
CHAPTER 14 UART0
14.4.2
Generation of Transmit Interrupt and Timing of Flag Set
An interrupt during transmission is generated when serial output data register 0
(SODR0) becomes empty, or ready to accommodate the next data to transmit.
■ Generation of Transmit Interrupt and Timing of Flag Set
● Set and clear of transmit data empty flag bit
The transmit data write flag bit (SSR0: TDRE) is set when the transmit data written to serial output data
register 0 (SODR0) is transferred to the transmission shift register, making it ready to write the next data to
transmit.The transmit data write flag bit (SSR0: TDRE) is cleared to "0" when the next data to transmit is
written to serial output data register 0 (SODR0).
Transmission and timing of flag set are shown in Figure 14.4-2.
Figure 14.4-2 Transmission and Timing of Flag Set
[Operating mode 0, 1]
Transmission interrupt generating
Transmission interrupt generating
SODR0 writing
SSR0: TDRE
SOT0 output
SP SP ST D0 D1 D2 D3
ST D0 D1 D2 D3 D4 D5 D6 D7 A/D
[Operating mode 2]
Transmission interrupt generating
Transmission interrupt generating
SODR0 writing
SSR0: TDRE
SOT0 output
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
ST
: Start bit
D0 to D7 : Data bit
SP
: Stop bit
A/D
: Address/data select bit
404
CHAPTER 14 UART0
● Timing of transmit interrupt request
A transmission interrupt request is generated when the transmit data write flag bit (SSR0: TDRE) is set
with transmission interrupts enabled (SSR0: TIE = 1).
Note:
If the transmission in progress is disabled (SCR0: TXE = 1, and reception is also
disabled with RXE = 0 in operation mode 1), the transmit data write flag bit is set
(SSR0: TDRF = 1), the transmission shift register stops shifting, then the UART0 is
disabled. That transmit data is transmitted which is already written to serial output
data register 0 (SODR0) before transmission stops (SODR).
405
CHAPTER 14 UART0
14.5
UART0 baud rate
The UART0 transmission/reception clock is selected from among the following options:
• Dedicated baud rate generator
• Internal clock (16-bit reload timer output)
• External clock (clock input to SCK pin)
■ Select of UART0 Baud Rate
The UART0 baud rate select circuit comprises as shown in Figure 14.5-1.The clock input source can be
selected from among the following three types:
● Baud rate by dedicated baud rate generator
• To use the dedicated baud rate generator incorporated in the UART0 as a clock input source, set the CS2
to CS0 bits in the serial mode register to "000B" to "100B" depending on the baud rate used.The baud
rate can be selected from six types.
● Baud rate by internal timer
• To use the internal clock signal supplied from 16-bit reload timer 0 as the clock input, set the CS2 to
CS0 bits in the serial mode register to "110B".
• The baud rate is the value resulting from dividing the frequency of the clock signal supplied from 16-bit
reload timer 0 by 2 in the clock synchronous mode or the value resulting from dividing the frequency of
the supplied clock signal by 32 in the clock asynchronous mode.
• Any baud rate can be selected according to the setting values of the 16-bit reload timer.
● Baud rate by external clock
• To use the external clock signal input via the clock input pin (SCK0) of the UART0 as the clock input,
set the CS2 to CS0 bits in the serial mode register to "111B".
• The baud rate is the value equal to the frequency of the external clock signal supplied in the clock
synchronous mode or the value resulting from dividing the frequency of the input clock signal by 16 in
the clock asynchronous mode.
• Any baud rate can be used if the external clock frequency is 2 MHz or less.
406
CHAPTER 14 UART0
Figure 14.5-1 UART0 Baud Rate Selector
SMR0: CS2 to CS0
(Clock input source select bit)
Clock selector
CS2 to CS0 =000B to 100B
[Dedicated baud rate generator]
φ /3, φ /4,
φ /5, φ /6,
φ /8
φ
Communication prescaler
(CDCR0: MD0, DIV3 to DIV0)
[Internal timer]
TMCSR0: CSL1, CSL0
Clock selector
φ
Division circuit
[Clock sync]
Select from 1/2, 1/4,
1/8, 1/16, or 1/32
[Asynchronous]
Select internal fixed
division ratio
CS2 to CS0 =110B
Down
counter
UF
1/2 [Clock sync]
1/32 [Asynchronous]
Baud rate
φ /21 φ /23 φ /25
prescaler
16-bit reload timer 0
CS2 to CS0 =111B
[External clock]
SCK0
Pin
φ : Machine clock
UF : Under flow
1/1 [Clock sync]
1/16 [Asynchronous]
SMR0: MD1, MD0
(operating select mode)
407
CHAPTER 14 UART0
14.5.1
Baud rate by dedicated baud rate generator
The baud rate that can be set when the output clock of the dedicated baud rate
generator is selected as the transfer clock of the UART0 is shown.
■ Baud rate by dedicated baud rate generator
The baud rate based on the dedicated baud rate generator is set by setting the clock input source select bits
(SMR0: CS2 to CS0) to "000B" to "100B".
When generating a transmission/reception clock signal using the dedicated baud rate generator, the
machine clock frequency is divided by the communication prescaler and then the divide ratio for the clock
input source selected by the clock selector is selected to determine the baud rate.
The division ratio at which the machine clock frequency is divided by the communication prescaler is the
same for the clock synchronous and asynchronous modes. The division ratio at which the baud rate is
determined is different for the clock synchronous and asynchronous modes.
Figure 14.5-2 shows the baud rate selector based on the dedicated baud rate generator.
Figure 14.5-2 Baud Rate Selector Based on Dedicated Baud Rate Generator
SMR0 : CS2 to CS0
(Clock input source select bit)
Clock selector
φ
φ/3, φ/4,
φ/5, φ/6,
φ/8
Communication prescaler
(CDCR0 : MD0, DIV3 to DIV0)
φ : Machine clock frequency
Division circuit
[Clock sync]
Select from 1/2,1/4,
1/8,1/16 or 1/32
[Asynchronous]
Select internal fixed
division ratio
Baud rate
SMR0 : MD1, MD0
(Operating mode select bit)
● Calculation expression for baud rate
Baud rate in asynchronous mode = φ × div × (division ratio of transfer clock in asynchronous mode)
Baud rate in clock synchronous mode = φ × div × (division ratio of transfer clock in clock synchronous mode)
φ:Machine clock
div: Division ratio based on communication prescaler
408
CHAPTER 14 UART0
● Division ratio based on communication prescaler (common between asynchronous and clock
synchronous modes)
The frequency divide ratio of the machine clock is set by the divide ratio select bits (CDCR0: DIV3 to
DIV0) in the communication prescaler control register.
Table 14.5-1 Division Ratio Based on Communication Prescaler
Machine
clockφ(MHz)
Divide
ratio
div
Communication Prescaler Control
Register
(CDCR0)
DIV3
DIV2
DIV1
DIV0
4
4
1
1
0
0
6
6
1
0
1
0
8
8
1
0
0
0
6
3
1
1
0
1
8
4
1
1
0
0
10
5
1
0
1
1
12
6
1
0
1
0
14
7
1
0
0
1
16
8
1
0
0
0
8
2
1
1
1
0
12
3
1
1
0
1
16
4
1
1
0
0
16
2
1
1
1
0
Division result
φ/div
(MHz)
1
2
4
8
div: Division ratio based on communication prescaler
● Baud Rate (Asynchronous Mode)
The baud rate in asynchronous/clock-synchronous mode is generated by dividing the output clock
frequency of the communication prescaler by 2, 4, 8, 16, or 32.The divide ratio is set by the clock input
source select bits (SMR0: CS2 to CS0).
Table 14.5-2 Baud Rate (Asynchronous Mode)
Baud rate selection bit
Baud Rate (bps)
Calculation
CS2
CS1
CS0
φ/div=2MHz
φ/div=4MHz
φ/div=8MHz
0
0
0
9,615
19,230
38,460
(φ / div) / (8 × 13 × 2)
0
0
1
4,808
9,615
19,230
(φ / div) / (8 × 13 × 22)
0
1
0
2,404
4,808
9,615
(φ / div) / (8 × 13 × 23)
0
1
1
1,202
2,404
4,808
(φ / div) / (8 × 13 × 24)
1
0
0
31,250
62,500
-
(φ / div) /26
φ:Machine clock
div: Division ratio based on communication prescaler
409
CHAPTER 14 UART0
● Baud Rate (Clock Synchronous)
Table 14.5-3 Baud Rate (Clock Synchronous)
Baud rate selection bit
Baud Rate (bps)
CS1
CS0
φ/div=2MHz
φ/div=4MHz
φ/div=8MHz
0
0
0
1M
2M
Reserved
(φ / div) / 2
0
0
1
500K
1M
2M
(φ / div) / 22
0
1
0
250K
500K
1M
(φ / div) / 23
0
1
1
125K
250K
500K
(φ / div) / 24
1
0
0
62.5K
125K
250K
(φ / div) /25
φ:Machine clock
div: Division ratio based on communication prescaler
410
Calculation
CS2
CHAPTER 14 UART0
14.5.2
Baud Rate by Internal Timer (16-bit Reload Timer)
The setting when selecting the internal clock supplied from the 16-bit reload timer 1 as
the clock input source of the UART0 and the baud rate calculation are shown below.
■ Baud Rate by Internal Timer (16-bit Reload Timer Output)
The baud rate based on the internal timer (16-bit reload timer 0 output) is set by setting the clock input
source select bits (SMR0: CS2 to CS0) to "110B".Any baud rate can be set by selecting the division ratio of
the count clock and the reload value of the 16-bit reload timer.
Figure 14.5-3 shows the baud rate selector based on the internal timer.
• If the internal timer (16-bit reload timer) is selected as a clock input source (SMR0: CS2 to CS0), the 16-bit
reload timer output pin (TOT) is connected internally and does not need to be connected externally to the
external clock input pin (SCK0).
• The 16-bit reload timer output pin (TOT) can be used as a general-purpose I/O port when it is not being
used in other way.
Figure 14.5-3 Baud Rate Selector by Internal Timer (16-bit Reload Timer Output)
SMR0: CS2 to CS0 =110B
(Clock input source select bit)
Clock selector
16-vit reload timer 0 output
(Specifying frequency count clock
dividing ratio and reload value)
1/2 [Clock sync]
1/32 [Asynchronous]
Baud rate
SMR0: MD1, MD0
(Operating mode select bit)
411
CHAPTER 14 UART0
● Calculation expression for baud rate
φ
bps
Asynchronous baud rate =
X (n + 1) × 2 × 16
φ
Clock synchronous baud rate =
bps
X (n + 1) × 2
φ: Machine clock
X: Count clock frequency divide ratio for 16-bit reload timer (2, 8, 32)
n: 16-bit reload register setting value (0 to 65,535) for 16-bit reload timer (0 to 65,535)
● Example of setting baud rates and reload register setting values (machine clock frequency: 7.3728
MHz)
Table 14.5-4 Baud Rate and Reload Value
Reload Value
Baud Rate
(bps)
Clock Asynchronous (start-stop
synchronization)
X = 21 (machine
cycle 2-divided)
X = 23
Machine clock:
8-frequency
division
X = 21 (machine
cycle 2-divided)
X = 23 (machine
cycle 8-divided)
38,400
2
−
47
11
19,200
5
−
95
23
9,600
11
2
191
47
4,800
23
5
383
95
2,400
47
11
767
191
1,200
95
23
1,535
383
600
191
47
3,071
767
300
383
95
6,143
1,535
X: Count clock frequency divide ratio for 16-bit reload timer
−: Setting disabled
412
Clock synchronous
CHAPTER 14 UART0
14.5.3
Baud rate by external clock
This section explains the setting when selecting the external clock as the transmit/
receive clock of the UART0.
■ Baud rate by external clock
The following settings are required for selecting a baud rate depending on the external clock input:
• Set the clock input source select bits (SMR0: CS2 to CS0) in the serial mode register to "111B".
• Set the SCK0 pin as the input port in the port direction register (DDR).
• To set the SCK0 pin as an external clock input pin, set the serial clock I/O enable bit (SMR0: SCKE) to
"0".
• Set the baud rate on the basis of the external clock input from the SCK0 pin.To change the baud rate, the
external input clock cycle must be changed as the internal frequency divide ratio is fixed.
Figure 14.5-4 Baud Rate Selector by External Clock
SMR0: CS2 to CS0 =111B
(Clock input source select bit)
Clock selector
SCK0
1/1 [Clock sync]
1/16 [Asynchronous]
Pin
Baud rate
SMR0: MD1, MD0
(Operating mode select bit)
● Calculation expression for baud rate
Asynchronous baud rate = f/16 bps
Clock synchronous baud rate = f bps
External clock frequency (2 MHz max.)
413
CHAPTER 14 UART0
14.6
Explanation of Operation of UART0
The UART0 has the bidirectional serial communication function (operation modes 0 and
2) and master/slave-connection communication function (operation mode 1).
■ Operation of LIN-UART
● Operating mode
The UART0 has three types of operation modes, they can set the inter-CPU connection mode or data
communication mode.
Table 14.6-1 shows operation mode of UART0.
Table 14.6-1 Operation Mode of UART0
Data length
Operating mode
No Parity
0
Normal mode
With Parity
Synchrono
us type
Length of Stop
Bit
Asynchrono
us
7 bits or 8 bits
1 bit or 2 bits*2
1
Multiprocessor
mode
2
Clock
synchronous
mode
8+1
8
*1
−
Asynchrono
us
−
Clock
synchronous
None
−:Setting disabled
*1:"+1" is the address/data select bit (A/D) used for communication control.
*2:During reception, only one bit is detected as the stop bit.
Note:
414
In UART0 operation mode 1, the device can be used only as the master in the
master/slave configuration.
CHAPTER 14 UART0
● Inter-CPU connection method
Either 1-to-1 connection or master/slave type connection can be selected for the inter-CPU controller.In
both cases, the data length, parity, synchronous or asynchronous mode, etc., must be the same for all
CPUs.The operation modes are selected as follows.
• For one-to-one connection, the same operation mode (either operation mode 0 or 2) must be adopted for
the two CPUs.For asynchronous transfer, set operation mode 0 (SMR0: MD1, MD0 =00B). For clocksynchronous transfer, set operation mode 2 (SMR0: MD1, MD0 =10B).
• For master/slave connection, set operation mode 1 (SMR0: MD1, MD0 =01B).When operation mode 1
is set, use the device as the master.For this connection, select no parity and a data length of 8 bits.
● Synchronous type
For the operation modes, either the asynchronous mode (start-stop synchronization) or the clocksynchronous mode can be selected.
● Signal type
The UART0 can only handle the NRZ (Non Return to Zero) data format.
● Start of transmission/reception
• Transmission starts when the transmission enable bit (SCR0: TXE) in the serial control register is set to
"1".
• Reception starts when the reception enable bit of the serial control register (SCR0: RXE) is set to "1".
● Stop of transmission/reception
• Transmission starts when the transmission enable bit (SCR0: TXE) in the serial control register is set to
"0".
• Reception starts when the reception enable bit (SCR0: RXE) in the serial control register is set to "0".
● Stop during transmission/reception
• When the reception in process is disabled (SCR0: RXE = 0) (during data input to the reception shift
register), the device stops reception after receiving the current frame of data completely and storing the
received data to serial input data register 0 (SIDR0).
• When transmission is disabled during transmission (during data output from the transmission shift
register) (SCR1 register bit 8: TXE = 0), transmission stops after transmission of one frame to the
transmission shift register from the serial output data register 1
415
CHAPTER 14 UART0
14.6.1
Operation in asynchronous mode
(operation mode 0 or 1)
When the UART0 is used in operation mode 0 (normal mode) or operation mode 1
(multiprocessor mode), the asynchronous transfer mode is selected.
■ Operation in Asynchronous Mode
● Format of transmit/receive data
Transmission and reception always begin with the start bit (Low level); transmission and reception are
performed at the specified data bit length on an LSB-first basis and end with the stop bit (High level).
• For use in operation mode 0, select a data length of seven or eight bits.You can select whether to use the
parity bit.
• In operation mode 1, the data length is fixed at 8 bits.There is no parity bit.The address/data bit (SMR0:
A/D) is added as bit 9.
Figure 14.6-1 shows the transmit/receive data format in the asynchronous mode.
Figure 14.6-1 Format of Transmit/Receive Data (Operation Mode 0 or 1)
[Operating mode 0]
ST
D0
D1
D2
D3
D4
D5
D7
D8
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
D8
SP
ST
D0
D1
D2
D3
D4
D5
D7
D8
P
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
D8
P
SP
ST
D0
D1
D2
D3
D4
D5
D7
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
SP
ST
D0
D1
D2
D3
D4
D5
D7
P
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
P
SP
Without P
Data 8bit
With P
Without P
Data 7bit
With P
[Operating mode 1]
ST
D0
D1
D2
D3
D4
D5
D7
D8
A/D
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
D8
A/D
SP
Data 8bit
ST
SP
P
A/D
416
: Start bit
: Stop bit
: Parity bit
: Address/data bit
CHAPTER 14 UART0
● Transmission
• Data to transmit is written to serial output data register 0 (SODR0) with the transmit data write flag bit
(SSR0: TDRE) containing "1".
• Transmission starts when the transmission enable bit (SCR0:TXE) in the serial control register is set to
"1"with the data to transmit written.
• The transmit data write flag bit (SSR0: TDRE) is temporarily cleared to "0" when data to transmit is
written to the serial output data register.
• The transmit data write flag bit (SSR0: TDRE) is set back to "1" when data to transmit is transferred
from serial output data register 0 (SODR0) to the transmission shift register.
• If the transmission interrupt enable bit (SSR0: TIE) contains "1", a transmission interrupt request is
generated when the transmit data write flag bit (SSR0: TDRE) is set to "1".During interrupt processing,
the next data to transmit can be written to serial output data register 0 (SODR0).
● Reception
• Reception is always performed while it is enabled (SCR0: RXE = 1).
• Upon detection of the start bit in received data, the UART0 uses serial input data register 0 (SIDR0) to
receive one frame of data according to the data format set in serial control register 0 (SCR0).
• Upon completion of receiving one frame of data, the receive data load flag bit (SSR0: RDRF) is set to "1".
• To read received data, check the state of the error flag in the serial status register (SSR0) after receiving
one frame of data and, if the data has been received normally, read the received data from serial input
data register 0 (SSR0).When a reception error occurs, perform error handling.
• When received data is read, the receive data load flag bit (SSR0: RDRF) is cleared to "0".
● Start bit detection method
To detect the start bit, make the following settings:
• Immediately before the communication period, be sure to set the communication line to "H" (add the mark
level).
• Enable reception (RXE="H") while the communication line remains at the mark level (H).
• Do not enable reception (RXE = "H") except during the communication period (excluding the mark level)
• After detection of the stop bit (after the RDRF flag is set to "1"), disable reception (RXE = "L") while
the communication line remains at the mark level (H).
417
CHAPTER 14 UART0
Figure 14.6-2 example of normal operating
Communication period
Non communication period
Marc level
Start bit
SIN
ST
Non communication period
Stop bit
Data
D0
D1
D2
D3
D4
D5
D6
D7
SP
(01010101B transmission)
RXE
Reception clock
Sampling clock
Reception clock(8-pulse)
Recognition of maicrocontroller side
(01010101B reception)
ST
Sampling clock is built from 1/16 divided of the reception clock.
D0
D1
D2
D3
D4
D5
D6
D7
SP
Keep in mind that the microcontroller cannot recognize input data (SIN) correctly if reception is enabled at
the following timing.
• Example of operation when reception is enabled (RXE = "H") while the communication line remains at
"L" level
Figure 14.6-3 example of abnormal operation
Communication period
Non communication period
Mark level
SIN
(01010101B transmission)
RXE
Start bit
Non communication period
Stop bit
Data
ST
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
SP
SP
Reception clock
Sampling clock
Recognition of microcontrol side
(10101010B reception)
ST recognition
PE,ORE,FRE
Reception error generating
● Stop Bit
During transmission, one bit or two bits can be selected.However, the receive side always detects only the
first bit.
● Error detection
• In operation mode 0, parity, overrun, and frame errors can be detected.
• In operation mode 1, overrun and frame errors can be detected.But parity errors cannot be detected.
418
CHAPTER 14 UART0
● Parity bit
The addition of a parity bit can be set only in operation mode 0.The parity addition enable bit (SCR0: PEN)
and parity select bit (SCR0:P) can be used to select whether to use parity and to set the even or odd parity,
respectively.
In operation modes 1 and 2, no parity bit can be added.
The transmit/receive data when the parity bit enabled are shown in Figure 14.6-4.
Figure 14.6-4 Transmit/Receive Data when Parity Bit Enabled
Reception
SIN0
ST
1
Transmission
SOT0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
SP
Transmission in
even parity
(SCR0: PEN = 1, P = 0)
SP
Transmission in
odd parity
(SCR0: PEN = 1, P = 1)
0
ST
1
Parity error generated
by reception in even parity
(SCR0: PEN = 1, P = 0)
1
ST
1
Transmission
SOT0
0
SP
1
Data
Parity
ST : Start bit
SP : Stop bit
Note: Parity bit is not set in operating mode 1 or mode 2.
419
CHAPTER 14 UART0
14.6.2
Operation at clock synchronous mode
(operating mode 2)
When the UART0 is used in operation mode 2, the transfer mode is clock synchronous.
■ Operation in Clock Synchronous Mode
● Format of transmit/receive data
In clock synchronous mode, 8-bit data is transmitted and received on an LSB-first basis.The start and stop
bits are not added to the transmit/receive data.
Figure 14.6-5 shows the data format for the clock synchronous mode.
Figure 14.6-5 Format of Transmit/Receive Data (Operation Mode 2)
Transmission by output of serial clock
Mark level
SCK0 output
SOT0
(LSB)
1
0
1
1
0
0
1
0
(MSB)
Transmission data
Transmission data writing
TXE
Reception by input of serial clock
Mark level
SCK0 input
SIN0
(LSB)
1
0
1
1
0
0
Reception data
RXE
Reception data reading
420
1
0
(MSB)
CHAPTER 14 UART0
● Clock Supply
In the clock synchronous mode, count of clocks equal to the transmit and receive bits count must be
supplied.
• When data is transmitted with the internal clock (dedicated baud rate generator or internal timer)
selected (SMR0: CS2 to CS0 = "000B" to "100B" or "110B"), the synchronous clock signal for data
reception is generated automatically.
• When an external clock is been selected (SMR0: CS2 to CS0 = "111B"), the clock signal for exact one
byte must be supplied from the external clock after it is ensured that data to be transmitted is present
(SSR0: TDRE = 0) in the serial output data register 0 (SODR0) of the UART0. Also, before and after
transmitting, always return to the mark level (High level).
● Error detection
Only overrun errors can be detected.Parity and framing errors cannot be detected.
● Setting of register
Table 14.6-2 shows the setting of the control register in transmitting serial data from the transmitting end to
the receiving end using the clock synchronous mode (operation mode 2).
Table 14.6-2 Setting of Control Register
Setting
Register Name
bit name
Transmit End (output serial clock)
Serial mode
register 0
(SMR0)
Serial control
register (SCR)
MD1,MD0
Set clock synchronous mode (MD1, MD0 =10 B).
CS2,CS1,
CS0
Set clock input source.
• Dedicated baud rate generator (CS2 to
CS0 =000B to 100B)
• Internal timer (CS2 to CS0 =110B)
Set clock input source.
• External clock (CS2 to CS0=111B)
SCKE
Set serial clock output (SCKE = 1).
Set serial clock input (SCKE = 0).
SOE
Set serial data output pin (SOE = 1).
Set general-purpose I/O port (SOE = 0).
PEN
Do not add parity bit (PEN = 0).
CL
8-bit data length (CL = 1)
REC
Serial status
register (SSR)
Receive End (input serial clock)
Initialize error flag (REC = 0).
TXE
Enable transmitting (TXE = 1).
Disable transmitting (TXE = 0).
RXE
Disable receiving (RXE = 0).
Enable receiving (RXE = 1).
TIE
Enable transmitting (TIE = 1)
Disable transmitting (TIE = 0)
RIE
Disable receiving (RIE = 0).
Enable receiving (RIE = 1).
● Starting communications
Communication is started when transmit data is written to serial output data register 0 (SODR0).When
starting communication even for reception only, it is always necessary to write dummy transmit data to
serial output data register 0 (SODR0).
421
CHAPTER 14 UART0
● Terminating communications
Upon completion of transmitting/receiving one frame of data, the receive data load flag bit (SSR0: RDRF)
is set to "1".When data is received, check the overrun error flag bit (SSR0: ORE) to ensure that the
communication has performed normally.
422
CHAPTER 14 UART0
14.6.3
Bidirectional Communication Function (Operation
Modes 0 and 2)
In operation modes 0 and 2, serial bidirectional communication can be performed in a
one-to-one connection.Operation modes 0 and 2 use asynchronous and clocksynchronous transfers, respectively.
■ Bidirectional Communication Function
The UART0 requires the settings shown in Figure 14.6-6 to operate in operation mode 0 or 2.
Figure 14.6-6 Settings to use the UART0 in operation mode 0 or 2
bit15 14
13
12
11
10
9 bit8 bit7 6
5
4
PEN P SBL CL AD REC RXE TXE MD1 MD0 CS2 CS1
SCR0, SMR0
Operating mode 0
Operating mode 2
SSR0,
SIDR0/SODR0
Operating mode 0
Operating mode 2
0
×
×
1
×
×
PE ORE FRE RDRFTDRE ×
0
1
0
0
RIE TIE
3
2
1 bit0
ReCS0 served
SCKE SOE
0
0
0
0
Setting transmission data (Write)
/hold reception data (Read)
×
DDR port direction register
- : Unused bit
: Used bit
× : Unused bit
1 : Setting "1"
0 : Setting "0"
Setting "0" corresponding bit
to pin as using SIN0 input pin,
SCK0 input pin
● Inter-CPU connection
To connect two CPUs.
Figure 14.6-7 Example of Bidirectional Communication Connect for UART0
SOT0
SOT0
SIN0
SCK0
CPU-1
SIN0
Output
Input
SCK0
CPU-2
423
CHAPTER 14 UART0
● Communication procedure
Communications start at any timing from the transmitting end when transmit data is provided.On the
transmission side, load transmit data into the serial output data register (SODR0) and set the transmission
enable bit (SCR0: TXE) in the serial control register to 1 to start transmission.
Figure 14.6-8 gives an example of transferring receive data to the transmitting end to inform the
transmitting end of normal reception.
Figure 14.6-8 Flowchart for Bidirectional Communication
(Transmission side)
(Reception side)
Start
Start
Operating mode setting
(one of 0,1,2)
(synchronized with tranmission side)
Setting 1-byte data to
SODR0 and communication
Operating mode setting
Data transmission
NO
NO
With reception
data
With reception
data
YES
Reception data reading
and processing
YES
Reception data reading
and processing
424
Data transmission
1-byte data transmission
CHAPTER 14 UART0
14.6.4
Master/slave type communication function (multi
processor mode)
Operation mode 1 allows communication between multiple CPUs connected in a
master/slave configuration.Note, however, that the function is available only to the
master side.
■ Master/Slave Mode Communication Function
The UART0 requires the settings shown in Figure 14.6-9 to operate in operation mode 1.
Figure 14.6-9 Setting about UART0 operating mode 1
bit15 14
13
12
11
10
9 bit8 bit7 6
5
4
3
2
1 bit0
Re- SCKE SOE
PEN P SBL CL AD REC RXE TXE MD1 MD0 CS2 CS1 CS0 served
SCR0, SMR0
0
SSR0,
SIDR0/SODR0
×
1
0
PE ORE FRE RDRFTDRE -
0
RIE TIE
0
1
0
Setting transmission data (Write)
/hold reception data (Read)
×
DDR port direction register
- : Undefined bit
: Used bit
× : Unused bit
1 : Setting "1"
0 : Setting "0"
Setting "0" corresponding bit
used as SIN0 input pin, SCK0
input pin
● Inter-CPU connection
One master CPU and two or more slave CPUs are connected to a pair of common communication lines to
make up the master/slave communication system.The UART0 can be used only as the master CPU.
Figure 14.6-10 Example of Master/Slave Mode Communication Connect for UART0
SOT
SIN
Master CPU
SOT
SIN
Slave CPU #0
SOT
SIN
Slave CPU #1
425
CHAPTER 14 UART0
● Function selection
At master/slave type communication, select the operation mode and data transfer type.
Since the parity check function cannot be used in operation mode 1, set the parity enable bit (SCR0: PEN)
to 0.
Table 14.6-3 Select of Master/Slave Communication Function
Operating mode
Master
CPU
Address
transmit/
receive
Data
transmit/
receive
426
Operation
mode 1
Slave
CPU
−
Data
A/D=1
+
8-bit address
A/D=0
+
8-bit data
Parity
Synchro
nous
type
Stop Bit
Not
provided
Asynchro
nous
1 bit or 2
bits
CHAPTER 14 UART0
● Communication procedure
Communication is started by the master CPU by transmitting address data.
The address data is data with the A/D bit set to "1". The address data bit (SCR0: A/D) is added to select the
slave CPU that the master CPU communicates with.When the program identifies address data and finds a
match with the allocated address, each slave CPU starts communications with the master CPU.
Figure 14.6-11 shows the flowchart for master/slave communications.
Figure 14.6-11 Flowchart for Master/Slave Communications
(Master CPU)
Start
Setting operating mode
to 1
Setting SIN pin to serial
data input
Setting 1-byte data
selecting slave CPU to
D0 to D7 (address data)
and transmitting (A/D=1)
Setting "0" in A/D
Reception operation
enabled
Communicate with slave
CPU
Communication
finish?
NO
YES
Communicate
with other slave
CPU
NO
YES
Reception operating
disabled
End
427
CHAPTER 14 UART0
14.7
Precautions when using UART0
Use of the UART0 requires the following precautions.
■ Precautions when using UART0
● Enabling sending and receiving
The UART0 has the transmission enable bit (SCR0: TXE) and reception enable bit (SCR0: RXE) provided
for transmission and reception.
• In the initial state after a reset, transmission and reception are both disabled (SCR0: TXE = 0, RXE = 0).
Transmission and reception must therefore be enabled in advance.
• The device can stop transmission and reception by disabling them (SCR0: TXE = 0, RXE = 0).
● Setting operation mode
Set the operation mode after disabling transmission and reception (SCR0: TXE = 0, RXE = 0).When the
operation mode is changed during transmission or reception, the transmitted/received data is not
guaranteed.
● About clock synchronous mode
UART0 operation mode 2 is set as the clock synchronous mode.Transmit/receive data is associated with no
start and stop bits.
● Timing of enabling send interrupt
Since the transmit data write enable flag bit (SSR0: TDRE) is set to a reset value of "1" (no transmit data,
transmit data write enabled), a transmission interrupt request is generated the moment transmission
interrupts are enabled (SSR0: TIE = 1).Be sure to prepare data to transmit before enabling transmission
(SSR0: TIE = 1).
● Setting clock in clock synchronous mode
If the dedicated baud rate generator is used at synchronous transfer, the following settings are the
prohibitions.
1) CS2 to CS0=000B
2) CS2 to CS0=001B and DIV3 to DIV0=0000B
428
CHAPTER 15
UART1
This chapter explains the functions and operation of the
UART.
15.1 Overview of UART1
15.2 Block Diagram of UART1
15.3 Configuration of UART1
15.4 Interrupt of UART1
15.5 UART1 Baud Rate
15.6 Explanation of Operation of UART1
15.7 Precautions when Using UART1
15.8 Program Example for UART1
429
CHAPTER 15 UART1
15.1
Overview of UART1
The UART1 is a general-purpose serial-data communication interface for synchronous
or asynchronous communication with external devices.
• Incorporates a bidirectional communication function (clock synchronous and
asynchronous modes)
• Incorporates a master/slave type communication function (in multiprocessor mode:
only master)
• Can generate an interrupt request at transmit completion and receive completion, and
at detection of a receive error.
• Supports expansion intelligent I/O service (EI2OS)
■ Functions of UART1
● Functions of UART1
The UART1 is a general-purpose serial-data communication interface, which transmits/receives serial data
with external devices. And UART1 has functions listed in Table 15.1-1 .
Table 15.1-1 Function of UART1
Function
Data buffer
Transfer mode
Baud rate
• Dedicated baud-rate generator (The baud rate can be selected from among
eight types.)
• Any baud rate can be set by external clock.
• A clock supplied from the internal clock (16-bit reload timer 0) can be
used.
• 7 bits (for asynchronous normal mode only)]
• 8 bits
Signal type
NRZ (Non Return to Zero) type]
Interrupt request
Master/slave type communication
function (multiprocessor mode)
430
• Synchronous to clock (without start bit/stop bit and parity bit)
• Asynchronous (start-stop synchronization to clock)
Data length
Detection of receive error
Note:
Full-duplicate double-buffer
• Framing error
• Overrun error
• Parity error (not supported for operation mode 1)
• Detection of receive error
• Transmission interrupt (Transmission)
• Both the transmission and reception support EI2OS.
This function enables communications between 1 (only use master) and n
(slave) (This function is used only as the master side)
At the clock synchronous transfer, the UART only transfers data, not affixing the start
and stop bits.
CHAPTER 15 UART1
Table 15.1-2 Operation Mode of UART1
Data length
Operating mode
With Parity
0
Asynchronous mode (Normal
mode)
1
Multiprocessor mode
2
Synchronous mode
No Parity
7 bits or 8 bits
Synchronous
type
Length of Stop
Bit
Asynchronous
1 bit or 2 bits*2
*1
8+1
-
Asynchronous
8
-
Synchronous
None
-: Setting disabled
*1: "+1" is the address/data select bit (bit 11 of SCR1 register: A/D) used for controlling communications.
*2: During reception, only one bit can be detected as the stop bit.
431
CHAPTER 15 UART1
15.2
Block Diagram of UART1
The UART1 consists of the following block.
■ Block Diagram of UART1
Figure 15.2-1 Block Diagram of UART1
Control bus
Dedicated baud
rate generator
16-bit
reload timer
Reception
interrupt
request output
Transmission
clock
Clock
selector Reception
clock
Pin
SCK1
Transmission
control
circuit
Reception
control
circuit
Start bit
detection circuit
Transmission
start circuit
Reception bit
counter
Transmission
bit counter
Reception parity
counter
Transmission
parity counter
Transmission
interrupt
request output
Pin
SOT1
Shift register
for transmission
Shift register
for reception
Pin
SIN1
Reception state
judge circuit
Serial input
data register 1
Reception
finish
Serial output
data register 1
Transmission start
Reception error
generating signal
for EI2OS (to CPU)
Internal data bus
Communication
prescaler
control
register
432
MD
DIV2
DIV1
DIV0
Serial
mode
register
1
MD1
MD0
CS2
CS1
CS0
RST
SCKE
SOE
Serial
control
register
1
PEN
P
SBL
CL
A/D
REC
RXE
TXE
Serial
status
register
1
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
CHAPTER 15 UART1
● Details of Pins in Block Diagram
The actual pin names and interrupt request numbers used in the UART1 are as follows:
SIN1 pin: P40/SIN1
SCK1 pin: P41/SCK1
SOT1 pin: P42/SOT1
Transmit interrupt number 1: #38 (26H)
Receive interrupt number 1: #37 (25H)
● Clock selector
The clock selector selects the transmit/receive clock from the dedicated baud rate generator, external input
clock, and internal clock (clock supplied from 16-bit reload timer).
● Reception control circuit
The receive controller is composed of receive bit counter, start bit detector and receive parity counter.The
receive bit counter counts the receive data, and outputs a receive interrupt request when reception of one
piece of data is completed.
The start bit detector detects the start bit from the serial input signal and writes the received data to the
serial input data register, on a bit-by-bit shift basis in accordance with the transfer rate.The receive parity
counter detects a parity bit in received data.
● Transmission control circuit
The transmit controller is composed of the transmit bit counter, transmit start circuit, and transmit parity
counter.The transmit bit counter counts the transmit data, and outputs a transmit interrupt request when
transmission of one piece of data is completed according to the set data length.The transmit start circuit
starts transmission when serial output data register (SODR1) is written.The transmit parity counter
generates the parity bit of the data transferred when parity is provided.
● Receive shift register
The receive shift register writes the receive data input from the SIN pin while shifting bit-by-bit, and when
the data reception is completed, it transfers the receive data to the serial input data register (SIDR1).
● Transmit shift register
Data written to SODR1 is transferred to the transmit shift register itself, and then the data is output to the
SOT pin while shifting bit-by-bit.
433
CHAPTER 15 UART1
● Serial mode register 1 (SMR1)
This register:
Selects operation mode
Selects clock input source (baud rate)
Sets dedicated baud rate generator
Selects clock speed (clock division value) when using dedicated baud rate generator
Enables or disables output of serial data and clock pins
Initialize UART
● Serial control register 1 (SCR1)
This register:
Sets availability of parity
Selects type of parity
Sets stop bit length
Sets data length
Selects frame data format in operation mode 1 (asynchronous multiprocessor mode)
Clears error flag
Enables or disables transmitting
Enables or disables receiving
● Serial status register 1 (SSR1)
The status register checks the transmission/reception state and error state and sets enabling/disabling of the
transmit/receive interrupt request.
● Serial input data register 1 (SIDR1)
The serial input data register retains the receive data.The serial input is converted and then stored in this
register.
● Serial output data register 1 (SODR1)
The serial output data register sets the transmit data.Data written to this register is serial-converted and then
output.
● Communication prescaler control register (CDCR)
The control register sets the baud rate of the baud rate generator.It sets the start/stop of the communication
prescaler and the division rate of the machine clock.
434
CHAPTER 15 UART1
15.3
Configuration of UART1
The UART1 pins, interrupt factors, register list and details are shown.
■ UART1 Pin
The pins used in the UART1 serve as general-purpose I/O port.
Table 15.3-1 indicates the pin functions and the setting necessary for use in the UART1.
Table 15.3-1 UART1 Pin
Pin Name
Pin Function
SOT1
General-purpose I/O port,
serial data output
SCK1
General-purpose I/O port,
serial clock output input
SIN1
General-purpose I/O port,
serial data input
Setting Necessary for Use in UART
Set to output enable.
(SMR1 register bit 0: SOE=1)
In clock input, set pin as input port in port direction
register (DDR).
In clock output, set to output enable.
(SMR register bit 1: SCKE=1)
Set as input port in port direction register (DDR).
■ Block Diagram of Pins of UART1
Reference:
See "CHAPTER 4 I/O PORT" for the block diagram of pins.
435
CHAPTER 15 UART1
■ List of Registers in UART1
Figure 15.3-1 List of Registers and Reset Values in UART1
bit
Serial control register 1 (SCR1)
bit
Serial mode register 1 (SMR1)
bit
Serial status register 1 (SSR1)
bit
Serial input data register 1 (SIDR1)
/serial output data register 1 (SODR1)
15
14
13
12
11
10
9
8
0
0
0
0
0
1
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
1
0
0
0
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
Note : Function as SIDR1 when reading, function as SODR1 when writing.
bit
Communication prescaler control
register 1 (CDCR1)
15
14
13
12
11
10
9
8
0
×
×
×
0
0
0
0
× : Undefined
■ Interrupt Request Generation by UART1
● Reception Interrupt
• When receive data is loaded to the serial input data register (SIDR1), the receive data load flag bit (bit
12: RDRF) in the serial status register (SSR1) is set to "1". When a receive interrupt is enabled (bit 9:
RIE = 1), a receive interrupt request is generated to the interrupt controller.
• When either a framing error, overrun error, or parity error occurs, the framing error flag bit (bit 13:
FRE), the overrun error flag bit (bit 14: ORE), or parity error flag bit (bit 15: PE) in the serial status
register (SSR1) are set to "1" according to the error occurred. When a receive interrupt is enabled (bit 9:
RIE = 1), a receive interrupt request is generated to the interrupt controller.
● Transmission Interrupt
When transmit data is transferred from the serial output data register (SODR1) to the transmit shift register,
the transmit data empty flag bit (bit 11: TDRE) in the serial status register (SSR1) is set to "1".If a transmit
interrupt is enabled (bit 8: TIE = 1), a transmit interrupt is requested.
436
CHAPTER 15 UART1
15.3.1
Serial control register 1 (SCR1)
The serial control register 1 (SCR1) performs the following: setting parity bit, selecting
stop bit length and data length, selecting frame data format in operation mode 1,
clearing receive error flag, and enabling/disabling of transmitting/receiving.
■ Serial control register 1 (SCR1)
Figure 15.3-2 Serial control register 1 (SCR1)
15
14
13
12
11
10
9
8
Reset value
00000100B
R/W R/W R/W R/W R/W
W
R/W R/W
bit8
TXE
0
1
bit9
RXE
0
1
bit10
REC
0
1
bit11
A/D
0
1
bit12
CL
0
1
bit13
SBL
0
1
Transmission enable bit
Transmission disabled
Transmission enabled
Reception enable bit
Reception disabled
Reception enabled
Reception error flag clear bit
Clear PE, ORE and FRE bit
No effection
Address/data select bit
Data frame
Address frame
Data length select bit
7 bits
8 bits
Stop bit length select bit
1 bit length
2 bits length
bit14
P
0
1
R/W
W
: Read/write
: Write only
: Reset value
bit15
PEN
0
1
Parity select bit
Valid only with parity (PEN = 1)
Even parity
Odd parity
Parity additional enable bit
Without parity
With parity
437
CHAPTER 15 UART1
Table 15.3-2 Functions of Serial Control Register 1 (SCR1)
bit name
438
Function
bit15
PEN:
Parity addition
enable bit
Specify whether to add (at sending) and detect (at receiving) a parity bit.
Note:
A parity bit is not added in operation modes 1 and 2 (Multiprocessor
mode, Synchronous mode).Be sure to set this bit to "0".
bit14
P:
Parity select bit
Select either odd or even parity when "with parity" (PEN = 1) is set.
bit13
SBL:
Stop-bit length select
bit
Set the length of the stop bit (frame end mark of send data) in operation
modes 0 and 1 (multiprocessor mode, synchronous mode).
Note:
At receiving, only the first bit of the stop bit is always detected.
bit12
CL:
Data-length select bit
Specify the length of send and receive data.
Note:
A data length of "7 bits" can be selected only in operation mode 0
(asynchronous normal mode).In operation modes 1 and 2
(asynchronous multiprocessor mode, Clock synchronous mode), be
sure to set a data length of "8 bits".
bit11
A/D:
Address/data select
bit
In operation mode 1 (asynchronous multiprocessor mode), set the data
format of the frame to be transmitted/received.
When bit set to "0": Data frame set
When bit set to "1": Address data frame set
bit10
REC:
Receive error flag
clear bit
Clear the receive error flags (bit 15 to 13: PE, ORE and FRE) of the serial
status register (SSR1) to "0".
When set to "0": Clears PE, ORE and FRE flags
When set to "1": No effect
When read: "1" always read
Note:
When a receive interrupt is "enabled" (bit 9: RIE = 1), set the bit10:
REC bit to "0" only when any one of the PE, ORE and FRE flags is set
to "1".
bit9
RXE:
Receive enable bit
Enable or disable the UART1 for receiving.
When set to "0": Reception disabled
When set to "1": Reception enabled
Note:
When receiving is "disabled" during receiving, receiving stops after the
data being received is stored in the serial input data register.
bit8
TXE:
Transmit enable bit
Enable or disable the UART1 for sending.
When set to "0": Transmission disabled
When set to "1": Transmission enabled
Note:
When transmitting is disabled during transmitting, transmitting stops
after the data in the serial input data register being transmitted is
completed in the serial input data register.
To set this bit to "0", after writing data to SODR1, wait for a time of
1/16th of the baud rate in the asynchronous mode and for a time equal
to or more than the baud rate in the synchronous mode.
CHAPTER 15 UART1
15.3.2
Serial mode register 1 (SMR1)
The serial mode register 1 (SMR1) performs selecting operation mode, selecting baud
rate clock, and disabling/enabling of output of serial data and clock to pin.
■ Serial mode register 1 (SMR1)
Figure 15.3-3 Serial mode register 1 (SMR1)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit0
Serial data output enable bit (SOT1 pin)
SOE
General purpose I/O port
0
Serial data output of UART1
1
bit1
SCKE
0
1
Serial clock I/O enable bit (SCK1 pin)
Clock input pin of general purpose I/O port or UART
Serial clock output pin of UART1
bit2
RST UART initialization bit
0
No effection
1
Initialization of all register in UART1
bit5 bit4 bit3
CS2 CS1 CS0
Clock input source select bit
"000B" to "101B" Baud rate by dedicated baud rate generator
Baud rate by internal timer
"110B"
(16-bit reload timer 1)
"111B"
bit7
bit6
MD1 MD0
R/W
: Read/Write
: Reset value
Baud rate by external clock
Oerating mode select bit
Mode No.
Operating mode
0
0
0
Asynchronous mode (normal mode)
0
1
1
Multi processor mode
1
0
2
Synchronous mode
1
1
-
Setting disabled
439
CHAPTER 15 UART1
Table 15.3-3 Functions of Serial Mode Register 1 (SMR1)
bit name
Note:
440
Function
bit7
bit6
MD0, MD1 :
Operation mode select
bits
Select the UART1 operation mode.
Notes:
(1)In operation mode 1 (asynchronous multiprocessor mode),
only the master can be used for master/slave
communication.In operation mode 1, the address/data bit
on bit 9 cannot be received, so the slave cannot be used.
(2)In operation mode 1 (asynchronous multiprocessor mode),
the parity check function cannot be used, set the parity
addition enable bit to "no parity" (SCR1 register bit 15:
PEN = 0).
bit5
to
bit3
CS0 to : CS2
Clock input source
select bits
Set the clock input source for the baud rate.
• Select the external clock (SCK1 pin), internal timer (16-bit
reload timer), or dedicated baud rate generator as the clock
input source.
• Set the baud rate when selecting the dedicated baud rate
generator.
Note:
If the dedicated baud rate generator is used at synchronous
transfer, the following settings are the prohibitions.
1) CS2 to CS0=000B
2) CS2 to CS0=001B and DIV3 to DIV0=0000B
bit2
UART Reset bit
RST:UART
This bit resets all registers in the UART1.
When set to "0": No effect on operation
When set to "1": Resets all registers in UART1
bit1
SCKE:
Serial clock I/O enable
bit
Switch between input and output of the serial clock.
When set to "0": "General-purpose I/O port" or "serial clock
input pin" set
When set to "1": "Serial clock output pin" set
Notes:
(1)When using the SCK1 pin as the serial clock input, set the
pin to the input port using the port direction register
(DDR).Also select the external clock (bit 5 to 3: CS2 to
CS0 = 111B) using the clock input source select bit.
(2)When using the SCK pin as the serial clock output, set the
clock input source select bit to anything other than the
external clock (bit 5 to 3: CS2 to CS0 = anything other
than 111B).
bit0
SOE:
Serial-data output
enable bit
Enable or disable output of serial data.
When set to "0": "General-purpose I/O port" set
When set to "1": "Serial data output pin" set
When "0" is written to the RST bit of Serial Mode Register, the interruption UART
should be prohibited.To prohibit the interruption, take one of the following
procedures:
• Interrupt disabling method
• (1)Before writing "0" to the RST bit, clear I flag to prohibit all interrupt factors.
(2)Before writing "0" to the RST bit, prohibit the UART interruption with the ILM
register.
(3)When "0" is written to the RST bit, writing should be performed at the UART
interruption level or the level with higher priority than the UART interruption.
CHAPTER 15 UART1
15.3.3
Serial status register 1 (SSR1)
The serial status register 1 (SSR1) checks the transmission/reception status and error
status and enables/disables interrupts.
■ Serial status register 1 (SSR1)
Figure 15.3-4 Serial status register 1 (SSR1)
15
14
13
12
11
R
R
R
R
R
10
9
8
Reset value
00001000B
R/W R/W R/W
bit8
TIE
0
1
Transmission interrupt generating enable bit
Transmission interrupt generating disabled
Transmission interrupt generating enabled
bit9
RIE
0
1
Reception interrupt generating disabled
Reception interrupt generating enabled
bit10
BDS
0
1
Reception interrupt generating enable bit
Transmission direction select bit
LSB first (transmission from lowest bit)
MSB first (transmission from uppermost bit)
bit11
Transmission data writing flag bit
TDRE
0
With transmission data (transmission data writing disabled)
1
Without transmission data (transmission data writing enabled)
bit12
RDRF
0
1
R/W
R
: Reaad/Write
: Read only
Reception data load flag bit
Without reception data
With reception data
bit13
FRE
0
1
Framing error flag bit
Without framing error
With framing error
bit14
ORE
0
1
Overrun error flag bit
Without overrun eeror
With overrun error
bit15
PE
0
1
Parity error flag bit
Without parity error
With parity error
: Reset value
441
CHAPTER 15 UART1
Table 15.3-4 Functions of Serial Status Register 1 (SSR1) (1/2)
bit name
442
Function
bit15
PE:
parity error flag bit
Detect an overrun error in receiving.
• This bit is set to "1" when a parity error occurs.
• This bit is cleared when "0" is written to the receive error flag
clear bit (SCR1 register bit 10: REC).
• When a receive interrupt is enabled (bit 9: RIE = 1), a receive
interrupt request is issued when a parity error occurs.
• When the parity error flag bit is set (bit 15: PE = 1), data in
the serial input data register 1 (SIDR1) is invalid.
bit14
ORE:
Overrun error flag bit
Detect an overrun error in receiving.
• This bit is set to "1" when an overrun error occurs.
• This bit is cleared when "0" is written to the receive error flag
clear bit (SCR1 register bit 10: REC).
• When a receive interrupt is enabled (bit 9: RIE = 1), a receive
interrupt request is issued when an overrun error occurs.
• When the overrun error flag bit is set (bit 14: ORE = 1), data
in the serial input data register (SIDR1) is invalid.
bit13
FRE:
flaming error flag bit
Detect a framing error in receive data.
• This bit is set to "1" when a framing error occurs.
• This bit is cleared when 0 is written to the receive error flag
clear bit (SCR1 register bit 10: REC).
• When a receive interrupt is enabled (bit 9: RIE = 1), a receive
interrupt request is issued when a framing error occurs.
• When the framing error flag bit is set (bit 13: FRE = 1), data
in the serial input data register 1 (SIDR1) is invalid.
bit12
RDRF:
Receive data load flag bit
Show the status of the serial input data register 1 (SIDR1).
• This bit is set to "1" when receive data is loaded to the serial
input register 1 (SIDR1).
• This bit is cleared to "0" when data is read from the SIDR1.
• When a receive interrupt is enabled (bit 9: RIE = 1), a receive
interrupt request is issued when receive data is loaded to the
serial input data register 1 (SIDR1).
bit11
TDRE:
Transmit data write flag
bit
Show the status of the serial output data register 1.
• This bit is cleared to "0" when send data is written to the
serial output register 1(SODR1).
• This bit is set to "1" when data is loaded to the send shift
register and transmission starts.
• When a transmission interrupt is enabled (bit 8: TIE = 1), a
transmit interrupt request is issued when data written to the
serial output data register 1(SODR1) is transmitted to the
transmit shift register (bit 11: TDRE=1).
CHAPTER 15 UART1
Table 15.3-4 Functions of Serial Status Register 1 (SSR1) (2/2)
bit name
Function
bit10
BDS:
Transfer direction select
bit
This bit sets the direction of serial data transfer.
When set to "0": Transfers data from least significant bit (LSB
first)
When set to "1": Transfers data from most significant bit
(MSB first)
Note:
At reading and writing data from and to the serial data
register, data is written to the serial output data register
(SODR1) and then the transfer direction select bit (BDS) is
rewritten to switch between the upper bits and the lower bits
of data. In this case the written data becomes invalid.
bit9
RIE:
Receive interrupt request
enable bit
Enable or disable receive data.
When set to "1": A receive interrupt request is issued when
receive data is loaded to the serial input data
register 1 (SIDR1) (bit 12: RDRF = 1) or
when a receive error occurs (bit 15: PE = 1,
bit 14: ORE = 1, or bit 13: FRE = 1).
bit8
TIE:
Transmit interrupt
request enable bit
Enable or disable send interrupt.
When set to "1": A receive interrupt request is issued when
data written to the serial output data register
1 (SODR1) is sent to the transmit shift register (bit 11: TDRE = 1).
443
CHAPTER 15 UART1
15.3.4
Serial Input Data Register 1 (SIDR1) and Serial Output
Data Register 1 (SODR1)
The serial input data register and serial output data register are allocated to the same
address.At read, the register functions as SIDR1. At write, the register functions as
SODR.
■ Serial input data register 1 (SIDR1)
Figure 15.3-5 Serial input data register 1 (SIDR1)
bit7
6
5
4
3
2
1
bit0
Reset value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R
R
R
R
R
R
R
R
R : Read only
X : Undefined
SIDR1 is a data buffer register for receiving serial data.
• The serial data signal transmitted to the serial input pin (SIN1) is converted by the shift register and
stored in SIDR1.
• When the data length is 7 bits, the upper one bit (SIDR1: D7) becomes invalid.
• When receive data is stored in the serial input data register 1 (SIDR1), the receive data load flag bit
(SSR1 register bit 12: RDRF) is set to "1".When a receive interrupt is enabled (SSR1 register bit 9: RIE = 1),
a receive interrupt request is issued.
• Read SIDR1 when the receive data load flag bit (SSR1 register bit 12: RDRF) is set to "1".The receive
data load flag bit (SSR1 register bit 12: RDRF) is cleared to 0 automatically when SIDR1 is read.
• When a receive error occurs (any one of SSR1 register bit 15, 14, 13: PE, ORE and FRE is "1"), the
receive data in SIDR1 becomes invalid.
444
CHAPTER 15 UART1
■ Serial output data register 1 (SODR1)
Figure 15.3-6 Serial output data register 1 (SODR1)
7
6
5
4
3
2
1
bit0
Reset value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
W
W
W
W
W
W
W
W
W: Write only
X : Undefined
The serial output data register 1 (SODR1) is a data buffer register for transmitting serial data.
• When data to transmit is written to serial output data register 1 (SODR1) with transmission enabled (bit
8 of SCR1 register: TXE = 1), the transmit data is transferred to the transmission shift register,
converted to serial data, then output from the serial data output pin (SOT1 pin).
• When the data length is 7 bits, the upper one bit (SODR1 register bit 7: D7) becomes invalid.
• The transmit data write flag (SSR1 register bit 11: TDRE) is cleared to "0" when send data is written to
SODR1.
• The transmit data write flag is set to "1" at completion of data transfer to the transmit shift register.
• When the transmit data write flag (SSR1 register bit 11: TDRE) is "1", the transmit data can be
written.When a transmit interrupt is enabled (SSR1 register bit 8: TIE=1), a transmit interrupt
occurs.The transmit bit data should be written with the transmit data write flag (SCR1 register bit 11:
TDRE) at "1".
Note:
Serial output data register is a write-only register and serial input data register is a
read-only register.Since the same address is allocated to the two registers, the
values written and read are different.Therefore, do not use instructions that perform
read-modify-write (RMW) operation such as INC and DEC instructions.
445
CHAPTER 15 UART1
15.3.5
Communication Prescaler Control Register 1 (CDCR1)
The communication prescaler control register 1 (CDCR1) is used to set the baud rate of
the dedicated baud rate generator for the UART1.
• Starts/stop the communication prescaler
• Sets the division ratio for machine clock
■ Communication Prescaler Control Register 1 (CDCR1)
Figure 15.3-7 Communication Prescaler Control Register 1 (CDCR1)
15
14
13
12
11
10
9
8
Reset value
0XXX0000B
R/W
-
-
-
R/W R/W R/W R/W
bit10 bit9 bit8
DIV2 DIV1 DIV0 Communication prescaler division ratio (div) bit
0
0
0
Divided by 1
0
0
1
Divided by 2
0
1
0
Divided by 3
0
1
1
Divided by 4
1
0
0
Divided by 5
1
0
1
Divided by 6
1
1
0
Divided by 7
1
1
1
Divided by 8
bit11
Reserved
0
bit15
MD
R/W : Read/Write
X
: Undefined
: Unused
: Reset value
446
0
1
Reserved bit
Be sure to set to "0".
Communication prescaler control bit
Communication prescaler operating stop
Communication prescaler operating enabled
CHAPTER 15 UART1
Table 15.3-5 Functions of Communication Prescaler Control Register 1 (CDCR1)
bit name
Note:
Function
bit15
MD:
Communication
prescaler control bit
This bit enables or disables the communication prescaler.
When set to "0": Stops communication prescaler
When set to "1": Operates communication prescaler
bit14
to
bit12
Unused bits
Read: The value is undefined.
Write: No effect
bit11
Reserved: reserved bit
Be sure to set this bit to "0".
bit10
to
bit8
DIV0 to DIV2:
Communication
prescaler division ratio
bits
• These bits set the machine clock division ratio.
Note:
When changing the division ratio, the time of at least two
clock cycles of the division clock should be allowed before
the next communication is started in order to stabilize the
clock frequency.
If the dedicated baud rate generator is used at synchronous transfer, the following
settings are the prohibitions.
1) CS2 to CS0=000B
2) CS2 to CS0=001B and DIV3 to DIV0=0000B
447
CHAPTER 15 UART1
15.4
Interrupt of UART1
The UART1 has a receive and a transmit interrupts, and the following factors can issue
interrupt requests.
• Receive data is loaded to the serial input data register 1 (SIDR1).
• A receive error (parity error, overrun error, framing error) occurs.
• When send data transferred from the output data register 1 (SODR1) to transmit shift
register
Also, each of these interrupt factors supports the expansion intelligent I/O service
(EI2OS).
■ Interrupt of UART1
The UART1 interrupt control bits and interrupt factors are shown in Table 15.4-1 .
Table 15.4-1 UART1 Interrupt Control Bit and Interrupt Factor
Transmission/
Reception
Interrupt
request
flag bit
SSR1:
RDRF
Reception
: Used bit
: Unused bit
448
0
1
Interrupt Factor
Receive data loaded
into serial input data
register 1 (SIDR1)
Overrun error
SSR1:
FRE
Framing error
SSR1:
TDRE
Interrupt factor
enable bit
2
SSR1:
ORE
SSR1:PE
Transmission
Operating
mode
Reading receive
data
SSR1: RIE
generating parity
error
Transfer of transmit
data completed
from serial output
data register
(SODR1)
Clear of the
Interruptrequest Flag
SSR1: TIE
Writing 0 to
receive error flag
clear bit (SCR1
register bit 10:
REC)
Writing transmit
data
CHAPTER 15 UART1
● Reception Interrupt
When a receive interrupt is enabled (SSR1 register bit 9: RIE = 1), a receive interrupt request is issued at
completion of data receiving (SSR1 register bit 12: RDRF = 1) or when any one of the overrun error (SSR1
register bit 14: ORE = 1), framing error (SSR 1 register bit 13: FRE = 1), and parity error (SSR 1 register
bit 15: PE = 1) occurs.
The receive data load flag (SSR1 register bit 12: RDRF) is cleared to 0 automatically when the serial input
data register 1 (SIDR1) is read.Each receive error flag (SSR1 register bit 15, 14, 13: PE, ORE, FRE) is
cleared to "0" when "0" is written to the receive error flag clear bit (SCR1 register bit 10: REC).
Note:
If a receive error (parity error, overrun error, framing error) occurs, correct the error
as necessary, and then write "0" to the receive error flag clear bit (SCR1 register bit
10: REC) to clear each receive error flag.
● Transmission Interrupt
When send data is transmitted from the serial output data register 1 (SODR1) to the transmit shift register,
the transmit data write flag bit (SSR1 register bit 11: TDRE) is set to "1".
When a transmit interrupt is enabled (SSR1 register bit 8: TIE = 1), a send interrupt request is issued.
■ Interrupt Related to UART1 and EI2OS
Reference:
For details of the interrupt number, interrupt control register, and interrupt vector
address, see "3.5 Interrupt".
■ EI2OS Function of UART1
The UART1 supports EI2OS.Consequently, EI2OS can be started separately for receive interrupts and
transmit interrupts.
● At reception:
EI2OS can be used regardless of the states of other resources.
● At transmission:
Since the interrupt control registers (ICR13, 14) are shared with receive interrupts of UART1, EI2OS can
be started only when UART1 transmit interrupts are not used.
449
CHAPTER 15 UART1
15.4.1
Generation of Receive Interrupt and Timing of Flag Set
Interrupts at receiving include the receive completion (SSR1 register bit 12: RDRF), and
the receive error (SSR1 register bit 15, 14, 13: PE, ORE, FRE).
■ Generation of Receive Interrupt and Timing of Flag Set
● Receive data load flag and each receive error flag sets
When data is received, it is stored in the serial input data register (SIDR) when the stop bit is detected (in
operation modes 0 and 1: Asynchronous normal mode, Asynchronous multiprocessor mode) or when the
last bit of receive data (SIDR1 register bit 7: D7) is detected (in operation mode 2: Clock synchronous
normal mode). When a receive error occurs, the error flags (SSR1 register bit 15, 14, 13: PE, ORE, FRE)
and receive data load flag (SSR1 register bit 12: RDRF) are set. When a reception error occurs, the
corresponding error flag (bit 15, 14, 13 of SSR1 register: PE, ORE, or FRE) is set and the receive data load
flag (bit 12 of SSR1 register: RDRF) is set as well. In each operation mode, the received data in the serial
input data register 0 (SIDR1) is invalid if either error flag is set. If any of the flags is set to the each
operation mode, the serial input data registers 1 (SIDR1) that have received are invalid.
Operation mode 0 (Asynchronous normal mode)
The receive data load flag bit (SSR1 register bit 12: RDRF) is set when the stop bit is detected.The error
flags (SSR1 register bit 15, 14, 13: PE, ORE, FRE) are set when a receive error occurs.
Operation mode 1 (Asynchronous multiprocessor mode)
The receive data load flag bit (SSR1 register bit 12: RDRF) is set to "1" when the stop bit is detected.The
error flags (SSR1 register bit 14, 13: ORE, FRE) are set when a receive error occurs.A parity error (SSR1
register bit 15: PE) cannot be detected.
Operation mode 2 (Clock synchronous mode)
The receive data load flag bit (SSR1 register bit 12: RDRF) is set to "1" when the last bit of receive data
(SIDR1 register bit 7: D7) is detected.The error flags (SSR1 register bit 14: ORE) are set when a receive
error occurs.A parity error (SSR1 register bit 15: PE) and framing error (SSR1 register bit 13: FRE) cannot
be detected.
Reception and timing of flag set are shown in Figure 15.4-1 .
450
CHAPTER 15 UART1
Figure 15.4-1 Reception and Timing of Flag Set
Reception data
(operating mode 0)
ST
D0
D1
D5
D6
D7
SP
Reception data
(operating mode 1)
ST
D0
D1
D6
D7
A/D
SP
D0
D1
D4
D5
D6
D7
Reception data
(operating mode 2)
SSR1 : PE, ORE, FRE *
SSR1 : RDRF
Reception interrupt generating
*
: PE flag is not detected in operating mode 1.
PE and FRE flag are detected in operating mode 2.
ST : Start bit
SP : Stop bit
A/D : Address of operating mode 2/ Data select bit
● Timing of receive interrupt request generation
With a receive interrupt enabled (SSR1 register bit 9: RIE = 1), when a receive interrupt request is issued
when any one of the receive data load flag (SSR1 register bit 12: RDRF), parity error flag (SSR1 register
bit 15: PE), and overrun error flag (SSR1 register bit 14: ORE) and framing error flag (SSR1 register bit
13: FRE) is set, reception interrupt is requested to interrupt controller.
451
CHAPTER 15 UART1
15.4.2
Generation of Transmit Interrupt and Timing of Flag Set
The transmit interrupt is generated when the serial output data register (SODR1) is
empty, and is in a state where the next transmitted data can be written.
■ Generation of Transmit Interrupt and Timing of Flag Set
● Set and clear of transmit data empty flag bit
The send data write flag bit (SSR1 register bit 11: TDRE) is set when the send data written to the serial
output data register 1 (SODR1) is loaded to the send shift register and the next data is ready for writing.The
send data write flag bit (SSR1 register bit 11: TDRE) is cleared to "0" when the next send data is written to
the serial output data register 1 (SODR1).
Transmission and timing of flag set are shown in Figure 15.4-2 .
Figure 15.4-2 Transmission and Timing of Flag Set
[Operating mode 1, 2]
Transmission interrupt request
Transmission interrupt generating
SODR1 writing
SSR1: TDRE
SOT1 output
[Operating mode 2]
SP SP ST D0 D1 D2 D3
ST D0 D1 D2 D3 D4 D5 D6 D7 A/D
Transmission interrupt generating
Transmission interrupt generating
SODR1 writing
SSR1: TDRE
SOT1 output
ST
D0 to D7
SP
A/D
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
: Start bit
: Data bit
: Stop bit
: Address/DAta select bit
● Timing of transmit interrupt request
When a transmit interrupt is enabled (SSR1 register bit 8: TIE = 1), a send interrupt request is issued to
interrupt controller when the transmit data load flag bit (SSR1 register bit 11: TDRE) is set.
Note:
452
When sending is disabled during sending (SCR1 register bit 8: TXE=0: and also in
operation mode 1 (asynchronous multiprocessor mode), receiving disabled (also
including bit 9: RXE)), the send data write flag bit is set (SSR1 register bit 11:
TDRF=1) and UART 1 communications are disabled after the shift operation of the
send shift register stops.
The transmit data written to the serial output data register 1 (SODR1) before the
transmission stops is sent.
CHAPTER 15 UART1
15.5
UART1 Baud Rate
One of the following can be selected as the UART1 transmit/receive clock.
• Dedicated baud rate generator
• Internal clock (16-bit reload timer output)
• External clock (clock input to SCK1 pin)
■ Select of UART1 Baud Rate
The UART1 baud rate select circuit comprises as shown in Figure 15.5-1 .The clock input source can be
selected from among the following three types:
● Baud rate by dedicated baud rate generator
• When using the dedicated baud rate generator incorporated into UART1 as a clock input source, set the
CS2 to CS0 bits in the serial mode register (SMR1) to "000B" to "101B" according to the baud rate.The
baud rate can be selected from six types.
● Baud rate by internal timer
• When using the internal clock supplied from the 16-bit reload timer as a clock input source, set the CS2
to CS0 bits in SMR1 bit 5 to 3 to "110B".
• The baud rate is the value at which the frequency of the clock supplied from the 16-bit reload timer as it
is in the clock synchronous mode, and the value at which the frequency of the supplied clock is divided
by 16 in the clock asynchronous mode.
• Any baud rate can be selected according to the setting values of the 16-bit reload timer.
● Baud rate by external clock
• When using the external clock supplied from the clock input pin (SCK1) in the UART1 as the clock
input source, set the CS2 to CS0 bits in SMR1 bit 5 to 3 to "111B".
• The baud rate is the value at which the external clock is supplied in the clock synchronous mode and the
value at which the frequency of the input clock is divided by 16 in the clock asynchronous mode.
453
CHAPTER 15 UART1
Figure 15.5-1 UART Baud Rate Selector
SMR1: CS2 to CS0
(Clock input source select bit)
Clock selector
CS2 to CS0 =000B to 101B
[Dedicated baud rate generator]
φ
φ/1, φ/2, φ/3, φ/4,
φ/5, φ/6, φ/7, φ/8
Communication prescaler
(CDCR1: MD0, DIV2 to DIV0)
[Internal timer]
TMCSR1: CSL1, CSL0
Clock selector
φ
Down
counter
Division circuit
[Clock synchronous]
Select any of 1/1, 1/2,
1/4, 1/8, 1/16, 1/32
[Asynchronous]
Select internal fixed
dividing ratio
CS2 to CS0 = 110B
UF
1/1 [Clock synchronous]
1/16 [Asynchronous]
φ/21 φ/23 φ/25
prescaler
16-bit reload timer 1
CS2 to CS0 = 111B
[External clock]
SCK1
Pin
φ : Machine clock
UF : Under flow
454
1/1 [Clock synchronous]
1/16 [Asynchronous]
SMR1: MD1, MD0
(Operating mode select bit)
Baud rate
CHAPTER 15 UART1
15.5.1
Baud rate by dedicated baud rate generator
The baud rate that can be set when the output clock of the dedicated baud rate
generator is selected as the transfer clock of the UART1 is shown.
■ Baud rate by dedicated baud rate generator
The baud rate based on the dedicated baud rate generator is set by setting the clock input source select bits
in the serial mode register (SMR1 register bit 5 to 3: CS2 to CS0) to "000B" to "101B".
When generating a transmit/receive clock using the dedicated baud rate generator, the division ratio for the
clock input source selected by the clock selector is selected to determine the baud rate after the machine
clock frequency is divided by the communications prescaler.
The division ratio at which the machine clock frequency is divided by the communication prescaler is the
same for the clock in synchronous and asynchronous modes. The division ratio at which the baud rate is
determined is different for the clock in synchronous and asynchronous mode.
Figure 15.5-2 shows the baud rate selector based on the dedicated baud rate generator.
Figure 15.5-2 Baud Rate Selector Based on Dedicated Baud Rate Generator
SMR1: CS2 to CS0
(Clock input source select bit)
Clock selector
φ
φ/1, φ/2, φ/3, φ/4,
φ/5, φ/6, φ/7, φ/8
Communication prescaler
(CDCR1: MD0, DIV2 to DIV0)
Division circtuit
[Clock synchronous]
Select any of 1/1,1/2,1/4,
1/8,1/16,1/32
[Asynchronous]
Select internal fixed
dividing ratio
Baud rate
SMR1: MD1, MD0
(Opearating mode select bit)
φ : Machine clock
● Calculation expression for baud rate
Baud rate in asynchronous mode = φ x div x (division ratio of transfer clock in asynchronous mode)
Baud rate in clock synchronous mode = φ x div x (division ratio of transfer clock in clock synchronous
mode)
φ:Machine clock frequency
div: Division ratio based on communication prescaler
455
CHAPTER 15 UART1
● Division ratio based on communication prescaler (common between asynchronous and clock
synchronous modes)
The division ratio of the machine clock is set by the division ratio select bits in the communication
prescaler control register (CDCR1 register bit 10 to 8: DIV2 to DIV0).
Table 15.5-1 Division Ratio Based on Communication Prescaler
MD
DIV2
DIV1
DIV0
0
-
-
-
Stops
1
0
0
0
1-frequency division
1
0
0
1
2-frequency division
1
0
1
0
3-frequency division
1
0
1
1
4-frequency division
1
1
0
0
5-frequency division
1
1
0
1
6-frequency division
1
1
1
0
7-frequency division
1
1
1
1
8-frequency division
div*
* div: Division ratio based on communication prescaler
● Baud Rate (Asynchronous Mode)
The baud rate in the asynchronous mode is generated using output clock of the communication prescaler.
The division ratio is set by the clock input source select bits (SMR1 register bit 5 to 3: CS2 to CS0).
Table 15.5-2 Baud Rate (Asynchronous Mode)
CS2
CS1
CS0
Asynchronous Mode (Start/Stop
Synchronous)
Calculation
0
0
0
76,923bps
(φ/ div) / (8 × 13 × 2)
0
0
1
38,461bps
(φ / div) / (8 × 13 × 4)
0
1
0
19,230bps
(φ/ div) /(8 × 13 × 8)
0
1
1
9,615bps
(φ/ div) / (8 × 13 × 16)
1
0
0
500kbps
(φ / div) / (8 × 2 × 2)
1
0
1
250kbps
(φ / div) / (8 × 2 × 4)
φ:Machine clock frequency
div:Division ratio based on communication prescaler
456
CHAPTER 15 UART1
● Baud rate (clock mode)
The baud rate in the synchronous mode is generated by dividing the output clock of the communication
prescaler by 1, 2, 4, 8, 16 and 32.The division ratio is set by the clock input source select bits (SMR1
register bit 5 to 3: CS2 to CS0).
Table 15.5-3 Baud Rate (Clock Synchronous)
CS2
CS1
CS0
CLK Synchronous
Calculation
0
0
0
2Mbps
(φ/ div) / 1
0
0
1
1Mbps
(φ / div) / 2
0
1
0
500kbps
(φ/ div) / 4
0
1
1
250kbps
(φ/ div) / 8
1
0
0
125kbps
(φ/ div) /16
1
0
1
62.5kbps
(φ/ div) /32
φ:Machine clock frequency
div: Division ratio based on communication prescaler
457
CHAPTER 15 UART1
15.5.2
Baud Rate by Internal Timer (16-bit Reload Timer)
The setting when selecting the internal clock supplied from the 16-bit reload timer 1 as
the clock input source of the UART1 and the baud rate calculation are shown below.
■ Baud Rate by Internal Timer (16-bit Reload Timer Output)
The baud rate based on the internal timer (16-bit reload timer output) is set by setting the clock input source
select bits (SMR1 register bit 5 to 3: CS2 to CS0) to "110B".Any baud rate can be set by selecting the
division ratio of the count clock and the reload value of the 16-bit reload timer.
Figure 15.5-3 shows the baud rate selector based on the internal timer.
• If the internal timer (16-bit reload timer) is selected as a clock input source (SMR1 register bit 5 to 3: CS2
to CS0), the 16-bit reload timer output pin (TOT) is connected internally and does not need to be
connected externally to the external clock input pin (SCK).
• The 16-bit reload timer output pin (TOT) can be used as a general-purpose I/O port unless otherwise
used.
Figure 15.5-3 Baud Rate Selector by Internal Timer (16-bit Reload Timer Output)
SMR1: CS2 to CS0 = 110B
(Clock input source select bit)
Clock selector
16-bit reload timer output
(Specifying frequency by
count clock dividing ratio
and reload value)
1/1 [Clock synchronous]
1/16 [Asynchronous]
Baud rate
SMR1: MD1, MD0
(Operating mode select bit)
● Calculation expression for baud rate
Asynchronous baud rate =
Clock synchronous baud rate =
φ/N
bps
16 × 2 × (n+1)
φ/N
bps
2 × (n+1)
φ:Machine clock frequency
N: division ratio based on communication prescaler for 16-bit reload timer (21, 23, 25)
n: reload value for 16-bit reload timer (0 to 65,535)
458
CHAPTER 15 UART1
● Example of setting baud rates and reload register setting values (machine clock frequency: 7.3728
MHz)
Table 15.5-4 Baud Rate and Reload Value
Reload Value
Baud Rate
(bps)
Clock Asynchronous (start-stop
synchronization)
Clock synchronous
N = 21 (machine
cycle divided by 2)
N = 23 (machine
cycle divided by 8)
N = 21 (machine
cycle divided by 2)
N = 23 (machine
cycle divided by 8)
38,400
2
-
47
11
19,200
5
-
95
23
9,600
11
2
191
47
4,800
23
5
383
95
2,400
47
11
767
191
1,200
95
23
1,535
383
600
191
47
3,071
767
300
383
95
6,143
1,535
N: Division ratio based on communication prescaler for 16-bit reload timer
- : Setting disabled
459
CHAPTER 15 UART1
15.5.3
Baud rate by external clock
This section explains the setting when selecting the external clock as the transmit/
receive clock of the UART1.
■ Baud rate by external clock
To select a baud rate by the external clock input, the following settings are essential:
• Set the CS2 to CS0 bits in the serial mode register (SMR1 register bit 5 to 3: CS2 to CS0) to "111B".
• Set the SCK1 pin as the input port in the port direction register (DDR).
• Set the serial dock I/O enable bit (SMR1 register bit 1: SCKE) to "0".
• Set the baud rate on the basis of the external clock input from the SCK1 pin.Since the internal division
ratio is fixed, the cycle of the external input clock must be changed when changing the baud rate.
Figure 15.5-4 Baud Rate Selector by External Clock
SMR1: CS2 to CS0 = 111B
(Clock input source select bit)
Clock selector
SCK1
Pin
1/1 [Clock synchronous]
1/16 [Asynchronous]
SMR1: MD1, MD0
(Operating mode select bit)
● Calculation expression for baud rate
Asynchronous baud rate = f/16 bps
Clock synchronous baud rate = φ bps
φ:External clock frequency (2 MHz max.)
460
Baud rate
CHAPTER 15 UART1
15.6
Explanation of Operation of UART1
The UART1 has master/slave type connection communication function (operation mode
1: asynchronous multiprocessor mode) in addition to bidirectional serial
communication functions (operation modes 0 and 2: asynchronous normal mode and
clock synchronous mode)
■ Operation of UART1
● Operating mode
The UART1 has three types of operation modes, they can set the inter-CPU connection mode or data
communication mode.
Table 15.6-1 shows operation mode of UART1.
Table 15.6-1 Operation Mode of UART1
Data length
Operating mode
No Parity
0
Normal
mode
1
Multiprocessor
mode
2
Clock
synchronous
mode
With Parity
7 bits or 8 bits
Synchronous
type
Length of Stop
Bit
Asynchronous
1 bit or 2 bits*2
8+1*1
-
Asynchronous
8
-
Clock
synchronous
None
-: Setting disabled
*1:"+1" is the address/data select bit (SCR1 register bit 11: A/D) used for controlling communications.
*2:During reception, only one bit can be detected as the stop bit.
Note:
The UART1 operation mode 1 (asynchronous multiprocessor mode) is only used as
the master in the master/slave type connection.
● Inter-CPU connection method
Either a 1-to-1 connection or a master/slave type connection can be selected for the inter-CPU controller.In
both cases, the data length, parity, synchronous or asynchronous mode, etc., must be the same for all
CPUs.The operation modes are selected as follows.
• For one-to-one connection, the same operation mode (either operation mode 0 as normal mode or operation
mode 2 as clock synchronous mode) must be adopted for the two CPUs. For the asynchronous mode, select
operation mode 1: asynchronous multiprocessor mode (SMR1 register bit 7, 6: MD1, MD0 = 00B): for the
synchronous mode select operation mode 2: clock synchronous mode (SMR1 register bit 7, 6: MD1,
MD0 =10B).
• For the master/slave type connection, operation mode 1: asynchronous multiprocessor mode (SMR1
register bit 7, 6: MD1, MD0 = 01B is set. For the master/slave type connection, operation mode 1:
461
CHAPTER 15 UART1
asynchronous multiprocessor mode (SMR1 register bit 7, 6: MD1, MD0 = 01B is set. Select operation
mode 1 (asynchronous multiprocessor mode) and use it as the master. For this connection, select no
parity 8-bit data length.
● Synchronous type
For the operation modes, either the asynchronous mode (start-stop synchronization) or the clocksynchronous mode can be selected.
● Signal type
The UART1 can only handle the NRZ (Non Return to Zero) data format.
● Start of transmission/reception
• Transmission starts when the transmission enable bit of the serial control register (SCR1 register bit 8:
TXE) is set to "1".
• Reception starts when the reception enable bit of the serial control register (SCR1 register bit 9: RXE) is
set to "1".
● Stop of transmission/reception
• Transmission stops when the transmission enable bit of the serial control register (SCR1 register bit 8:
TXE) is set to "0".
• Reception stops when the reception enable bit of the serial control register (SCR1 register bit 9: RXE) is
set to "0".
● Stop during transmission/reception
• When reception is disabled during receiving (during data input to reception shift register) (SCR1
register bit 9: RXE = 0), reception stops after reception of the frame being received is completed and the
receive data is stored to the serial input data register 1 (SIDR1).
• When transmission is disabled during transmission (during data output from the transmission shift
register) (SCR1 register bit 8: TXE = 0), transmission stops after transmission of one frame to the
transmission shift register from the serial output data register 1 (SODR1).
462
CHAPTER 15 UART1
15.6.1
Operation in Asynchronous Mode
(Operation Mode 0 or 1)
When the UART1 is used in operation mode 0 (asynchronous normal mode) or
operation mode 1 (asynchronous multiprocessor mode), the asynchronous transfer
mode is selected.
■ Operation in Asynchronous Mode
● Format of transmit/receive data
Transmission and reception always start with the start bit (Low level); transmission and reception are
performed at the specified data bit length on LSB first basis and end with the stop bit (High level).
• In operation mode 0 (Asynchronous normal mode), the data length can be set to 7 or 8 bits.Use of the
parity bit can be specified.
• In operation mode 1 (Asynchronous multiprocessor mode), the data length is fixed to 8 bits.The address/
data bit (SCR1 register bit 11: A/D) is added to bit 9.
Figure 15.6-1 shows the transmit/receive data format in the asynchronous mode.
Figure 15.6-1 Format of Transmit/Receive Data (Operation Mode 0 or 1)
[Operating mode 0]
ST
D0
D1
D2
D3
D4
D5
D7
D8
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
D8
SP
ST
D0
D1
D2
D3
D4
D5
D7
D8
P
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
D8
P
SP
ST
D0
D1
D2
D3
D4
D5
D7
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
SP
ST
D0
D1
D2
D3
D4
D5
D7
P
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
P
SP
Without P
Data 8bit
With P
Without P
Data 7bit
With P
[Operating mode 1]
ST
D0
D1
D2
D3
D4
D5
D7
D8
A/D
SP SP
ST
D0
D1
D2
D3
D4
D5
D7
D8
A/D
SP
Data 8bit
ST : Start bit
SP : Stop bit
P : Parity bit
A/D : Address/Data bit
463
CHAPTER 15 UART1
● Transmission
• Transmit data is written to the serial output data register 1 (SODR1) with the transmit data write flag bit
(SSR1 register bit 11: TDRE) set to "1".
• Transmission starts when transmit data is written and the transmit enable bit of the serial control register
(SCR1 register bit 8: TXE) is set to "1".
• The transmit data write flag bit (SSR1 register bit 11: TDRE) is cleared to 0 temporarily when transmit
data is written to SODR1.
• The transmit data write flag bit (SSR1 register bit 11: TDRE) is set to "1" again once the transmit data is
written to the send shift register from the serial output data register 0 (SODR1).
• When the transmit interrupt enable bit (SSR1 register bit 8: TIE) is set to "1", a send interrupt request is
issued once the send data write flag bit (SSR1 register bit 11: TDRE) is set to "1".The succeeding send
data can be written to the serial output data register 1 (SODR1) at interrupt processing.
● Reception
• When reception is enabled (SCR1 register bit 9: RXE = 1), receiving is always performed.
• When the start bit of receive data is detected, the serial input data register 1 (SIDR1) receives one frame of
data and stores data to the serial input data register 1 (SIDR1) according to the data format specified in the
serial control register 1 (SCR1).
• At completion of receiving one frame of data, the receive data load flag bit (SSR1 register bit 12: RDRF)
is set to "1".
• When the status of the error flag of the serial status register 1 (SSR1) is checked to find normal
reception at the completion of one frame of data, read the receive data.When a receive error occurs,
perform error processing.
• The receive data load flag bit (SSR1 register bit 12: RDRF) is cleared to 0 when receive data is read.
● Start bit detection method
To detect the start bit, make the following settings:
• Immediately before the communication period, be sure to set the communication line to "H" (add the
mark level).
• Enable reception (RXE="H") while the communication line remains at the mark level (H).
• Do not enable reception (RXE = "H") except during the communication period (excluding the mark level)
• After detection of the stop bit (after the RDRF flag is set to "1"), disable reception (RXE = "L") while
the communication line remains at the mark level (H).
464
CHAPTER 15 UART1
Figure 15.6-2 example of normal operating
Communication period
Non communication period
Marc level
Start bit
SIN
Non communication period
Stop bit
Data
ST
D0
D1
D2
D3
D4
D5
D6
D7
SP
(01010101B transmission)
RXE
Reception clock
Sampling clock
Reception clock(8-pulse)
Recognition of maicrocontroller side
(01010101B reception)
ST
Sampling clock is built from 1/16 divided of the reception clock.
D0
D1
D2
D3
D4
D5
D6
D7
SP
Keep in mind that the microcontroller cannot recognize input data (SIN) correctly if reception is enabled at
the following timing.
• Example of operation when reception is enabled (RXE = H) while the communication line remains at L
level
Figure 15.6-3 example of abnormal operation
Communication period
Non communication period
Mark level
SIN
(01010101B transmission)
RXE
Start bit
Non communication period
Stop bit
Data
ST
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
SP
SP
Reception clock
Sampling clock
Recognition of microcontrol side
(10101010B reception)
ST recognition
PE,ORE,FRE
Reception error generating
● Stop Bit
During transmission, one bit or two bits can be selected.However, the receive side always detects only the
first bit.
● Error detection
• In operation mode 0 (asynchronous normal mode), parity, overrun, and frame errors can be detected.
• In operation mode 1 (asynchronous multiprocessor mode), overrun and frame errors can be detected.But
parity errors cannot be detected.
● Parity bit
A parity bit can be set only in operation mode 0 (asynchronous normal mode).The parity addition enable bit
(SCR1 register bit 15: PEN) is used to specify whether there is parity or not, and the parity select bit (SCR1
register bit 14: P) is used to select odd or even parity.
There is no parity bit in operation modes 1 (asynchronous multiprocessor mode).
465
CHAPTER 15 UART1
The transmit/receive data when the parity bit enabled are shown in Figure 15.6-4 .
Figure 15.6-4 Transmit/Receive Data when Parity Bit Enabled
Reception
SIN1
ST
SP
1
Transmission
SOT1
1
1
0
0
0
1
0
1
1
0
0
1
0
0
1
1
0
0
Data
ST : Start bit
SP : Stop bit
<Note> Parity bit is not set in operating mode 1.
1
0
SP
Transmission in even parity
(SCR1: PEN = 1, P = 0)
SP
Transmission in odd parity
(SCR1: PEN = 1, P = 1)
0
ST
1
466
1
ST
1
Transmission
SOT1
0
Parity error generated
with reception in even parity
(SCR1: PEN = 1, P = 0)
1
Parity
CHAPTER 15 UART1
15.6.2
Operation in Clock Synchronous Mode
(Operation Mode 2)
When the UART1 is used in operation mode 2, the transfer mode is clock synchronous.
■ Operation in Clock Synchronous Mode
● Format of transmit/receive data
In the synchronous mode, 8-bit data is transmitted/received on LSB-first.The start and stop bits are not
added to the transmit/receive data.
Figure 15.6-5 shows the data format for the clock synchronous mode.
Figure 15.6-5 Format of Transmit/Receive Data (Operation Mode 2)
Transmission by serial clock output
Mark level
SCK1 output
SOT1
(LSB)
1
0
1
1
0
0
1
0
(MSB)
Transmission data
Transmission data
writing
TXE
Reception by serial clock input
Mark level
SCK1 input
SIN1
(LSB)
1
0
1
1
0
0
1
0
(MSB)
Reception data
RXE
Reception data
reading
● Clock Supply
In the clock synchronous mode, count of clocks equal to the transmit and receive bits count must be
supplied.
• When the internal clock (dedicated baud rate generator or internal timer) has already selected (SMR1
register bit 5 to 3: CS2 to CS0 =000B to 101B or 110B) and data is transmitted, the synchronous clock
for data reception is generated automatically.
• When the external clock has already selected (SMR1 register bit 5 to 3: CS2 to CS0 =111B), the clock
for exact one byte must be supplied from outside after ensuring that data is present (SSR1 register bit
467
CHAPTER 15 UART1
11: TDRE = 0) in the serial output data register (SODR1). Also, before and after transmitting, always
return to the mark level (High level).
● Error detection
Only overrun errors can be detected.Parity and framing errors cannot be detected.
● Setting of register
Table 15.6-2 shows the setting of the control register in transmitting serial data from the transmitting end
to the receiving end using the clock synchronous mode (operation mode 2).
Table 15.6-2 Setting of Control Register
Setting
Register Name
bit name
Transmit End (output serial clock)
Serial mode register 1
(SMR1)
Serial control register
1 (SCR1)
MD1,
MD0
Set clock synchronous mode (MD1, MD0 = 10B).
CS2, CS1,
CS0
Set clock input source.
• Dedicated baud rate generator
(CS2 to CS0 =000B to 100B)
• Internal timer (CS2 to CS0 = 110B)
Set clock input source.
• External clock
(CS2 to CS0 = 111B)
SCKE
Set serial clock output (SCKE = 1).
Set serial clock input (SCKE = 0).
SOE
Set serial data output pin (SOE = 1).
Set general-purpose I/O port
(SOE = 0).
PEN
Do not add parity bit (PEN = 0).
CL
8-bit data length (CL = 1)
REC
Serial status register 1
(SSR1)
Receive End (input serial clock)
Initialize error flag (REC = 0).
TXE
Enable transmitting (TXE = 1).
Disable transmitting (TXE = 0).
RXE
Disable receiving (RXE = 0).
Enable receiving (RXE = 1).
TIE
Enable transmitting (TIE = 1)
Disable transmitting (TIE = 0)
RIE
Disable receiving (RIE = 0).
Enable receiving (RIE = 1).
● Starting communications
When send data is written to the serial output data register 1 (SODR1), communication starts. When
starting communication only in receiving, it is always necessary to write dummy send data to the serial
output data register 1 (SODR1).
● Terminating communications
Upon completion of transmission/reception of one frame of data, the receive data load flag bit (bit 12 in the
SSR1 register: RDRF) is set to "1". When data is received, check the overrun error flag bit (SSR1 register
bit 14: ORE) to ensure that the communication has performed normally.
468
CHAPTER 15 UART1
15.6.3
Bidirectional Communication Function (Operation
Modes 0 and 2)
In operation modes 0 and 2 (asynchronous normal mode, clock synchronous mode),
normal serial bidirectional communications using 1-to-1 connection can be
performed.For operation mode 0 (asynchronous normal mode), the asynchronous mode
is used; for operation mode 2 (clock synchronous mode), the clock synchronous mode
is used.
■ Bidirectional Communication Function
To operate the UART1 in the operation mode 0, 2 (asynchronous normal mode, clock synchronous mode),
shown in Figure 15.6-6 is required.
Figure 15.6-6 Setting of Operation Modes 0, 2 (Asynchronous Normal Mode and Clock Synchronous
Mode) for UART1
bit15 14
SCR1, SMR1
Operating mode 0
Operating mode 2
SSR1,
SIDR1/SODR1
Operating mode 0
Operating mode 2
13
12
11
10
9 bit8 bit7 6
5
4
PEN P SBL CL AD REC RXE TXE MD1 MD0 CS2 CS1
0
×
×
1
×
×
PE ORE FRE RDRFTDRE ×
0
1
0
0
RIE TIE
0
0
3
2
1 bit0
ReCS0 served SCKE SOE
0
0
Setting transmission data (write)
/holding reception data (read)
×
DDR port direction register
- : Unudefined bit
: Used bit
× : Unused bit
1 : Setting to "1"
0 : Setting to "0"
Setting "0" to corresponding bit
using as SIN1 input pin and SCK1
input pin
● Inter-CPU connect
Connect the two CPUs.
469
CHAPTER 15 UART1
Figure 15.6-7 Example of Bidirectional Communication Connect for UART
SOT
SOT
SIN
SCK
SIN
Output
Input
CPU-1
SCK
CPU-2
● Communication procedure
Communications start at any timing from the transmitting end when transmit data is provided.At the
transmitting end, set transmit data in the serial output data register (SODR1) and set the transmitting enable
bit in the serial control register (SCR1 register bit 8: TXE) to 1 to start transmitting.
Figure 15.6-8 gives an example of transferring receive data to the transmitting end to inform the
transmitting end of normal reception.
Figure 15.6-8 Flowchart for Bidirectional Communication
(Transmission side)
(Reception side)
Start
Start
Opearating mode setting
(either 0 or 2)
(synchronized with transmission side)
Setting 1 byte data to SODR
and communicating
Operating mode setting
Data
transmission
NO
With reception data
YES
NO
With reception data
YES
Reading reception data
and processing
470
Reading reception data
and processing
Data
transmission
Transmission of 1byte data
CHAPTER 15 UART1
15.6.4
Master/Slave Type Communication Function
(Multiprocessor Mode)
Operation mode 1 (asynchronous multiprocessor mode) enables communications by
the master/slave connection of more than one CPU.Only the master CPU functions.
■ Master/Slave Mode Communication Function
To operate the UART1 in operation mode 1 (asynchronous multiprocessor mode), the setting shown in
Figure 15.6-9 is required.
Figure 15.6-9 Setting of Operation Mode 1 (Asynchronous Multiprocessor Mode) for UART1
bit15 14
SCR1, SMR1
12
11
10
9 bit8 bit7 6
5
4
PEN P SBL CL AD REC RXE TXE MD1 MD0 CS2 CS1
0
SSR1,
SIDR1/SODR1
13
×
1
PE ORE FRE RDRFTDRE
0
0
1
3
2
1 bit0
ReCS0 served
SCKE SOE
0
0
transmission data (write)
- RIE TIE Setting
/holding reception data (read)
×
DDR port direction register
- : Undefined bit
: Useing bit
× : Unused bit
1 : Setting to "1"
0 : Setting to "0"
Setting "0" to corresponding bit
using as SIN1 input pin and SCK1
input pin
● Inter-CPU connection
One master CPU and two or more slave CPUs are connected to a pair of common communication lines to
make up the master/slave communication system.The UART1 can be used only as the master CPU.
471
CHAPTER 15 UART1
Figure 15.6-10 Example of Master/Slave Mode Communication Connect for UART1
SOT1
SIN1
Master CPU
SOT
SIN
SOT
Slave CPU #0
SIN
Slave CPU #1
● Function selection
At master/slave type communication, select the operation mode and data transfer type.
Since the parity check function cannot be used in operation mode 1 (asynchronous multiprocessor mode),
set the parity add enable bit (SCR1 register bit 15: PEN) to 0.
Table 15.6-3 Selection of Master/Slave Communication Function
Operating mode
Master
CPU
Address
transmit/
receive
Data
transmit/
receive
472
Operation
mode 1
Slave
CPU
Data
Parity
Synchro
nous
type
Stop Bit
None
Asynchro
nous
1 bit or 2
bits
A/D=1
+
8-bit address
A/D=0
+
8-bit data
CHAPTER 15 UART1
● Communication procedure
Communications start when the master CPU transmits address data.
The address data is data with the A/D bit set to "1". The address/data select bit (SCR1 register bit 11: A/D)
is added to select the slave CPU that the master CPU communicates with.When the program identifies
address data and finds a match with the allocated address, each slave CPU starts communications with the
master CPU.
Figure 15.6-11 shows the flowchart for master/slave communications.
Figure 15.6-11 Flowchart for Master/Slave Communications
(Master CPU)
Start
Select operating mode 1
(Asynchronous
multiprocessor mode)
Slave to D0 to D7
Setting 1 byte data
selecting CPU (address
data) and transmission
(A/D=1)
Setting "0" to A/D
Reception operating
enable
Communicating with
slave CPU
Communication finish?
NO
YES
Communicating
with otehr slave
CPU
NO
YES
Reception operating
disabled
End
473
CHAPTER 15 UART1
15.7
Precautions when Using UART1
Use of the UART1 requires the following precautions.
■ Precautions when Using UART1
● Enabling sending and receiving
The send enable bit (SCR1 register bit 8: TXE) and receive enable bit (SCR1 register bit 9: RXE) are
provided for sending and receiving.
• In the initial state after reset, both sending and receiving are disabled (SCR1 register bit 8: TXE = 0, bit
9: RXE = 0). Therefore, it is necessary to enable sending and receiving.
• Sending and receiving are disabled to stop (SCR1 register bit 8: TXE = 0, bit 9: RXE = 0).
● Setting operation mode
Set the operation mode after disabling sending and receiving (SCR1 register bit 8: TXE = 0, bit 9: RXE =
0). When the operation mode is changed during transmission or reception, the transmitted/received data is
not guaranteed.
● Clock synchronous mode
Operation mode 2 (clock synchronous mode) is set as the clock synchronous mode.Send and receive data
do not have start and stop bits.
● Timing of enabling send interrupt
The reset value after reset of the send data write flag bit (SSR1 register bit 11: TDRE) is set at "1" (no send
data, send data write enabled). Therefore, the send interrupt is enabled (SSR1 register bit 8: TIE = 1) and a
send interrupt request is issued. Always prepare send data and enable a send interrupt (SSR1 register bit 8:
TIE = 1).
● Setting clock in clock synchronous mode
If the dedicated baud rate generator is used at synchronous transfer, the following settings are the
prohibitions.
1) CS2 to CS0=000B
2) CS2 to CS0=001B and DIV3 to DIV0=0000B
474
CHAPTER 15 UART1
15.8
Program Example for UART1
This section gives a program example for the UART1.
■ Program Example for UART1
● Processing contents
The bidirectional communication function (normal mode) of the UART1 is used to perform serial
transmission/reception.
• Set operation mode 0, asynchronous mode (normal), 8-bit data length, 2-bit stop bit length, and no
parity.
• Use the P40/SIN1 and PS/SOT1 pins for communications.
• Use the dedicated baud rate generator to set the baud rate to approximately 9600 bps.
• Transmit the character 13H from the SOT1 pin and receive it at an interrupt.
• Assume the machine clock (φ) 16 MHz.
● Coding example
ICR13 EQU
; UART transminssion/reception
interrupt control register
DDR1 EQU
000011H
; Port1 data direction register
CDCR1 EQU
00001BH
; Communication prescaler register 1
SMR1 EQU
000024H
; Mode control register 1
SCR1 EQU
000025H
; Control register 1
SIDR1 EQU
000026H
; Input data register 1
SODR1 EQU
000026H
; Output data register 1
SSR1 EQU
000027H
; State register 1
REC
EQU
SCR1:2
; Reception error flag clear bit
; -------Main program-----------------------------------------CODE CSEG ABS = 0FFH
START:
;
:
; Assume stack pointer (SP) already reset
AND
MOV
MOV
MOV
MOV
MOV
0000BDH
CCR,#0BFH
I:ICR13,#00H
I:DDR1,#00000000B
I:CDCR1,#080H
I:SMR1,#00010001B
; Disable interrupt
; Interrupt level 0 (highest priority)
; Setting SIN1 pin as input pin
; Enable communication prescaler
; Operating mode 0 (asynchronous)
; Using dedicated baud rate generator (9615 bps)
; Disabled clock pulse output and
enable data output
I:SCR1,#00010011B ; Without N parity. 2 stop bit
; Clear 8 data bit and reception error flag
; Enable transmission/reception operating
475
CHAPTER 15 UART1
MOV
I:SSR1,#00000010B ; Disable transmission interrupt and
enable reception interrupt
MOV
I:SODR1,#13H
; Write transmission data
MOV
ILM,#07H
; Setting ILM in PS to level 7
OR
CCR,#40H
; Enable interrupt
LOOP: MOV
A,#00H
; No limit roop
MOV
A,#01H
BRA
LOOP
; ------Interrupt program-------------------------------------------WARI:
MOV
A,SIDR1
; Read reception data
CLRB I:REC
; Clear reception interrupt requestflag
;
:
;
User processing
;
:
RETI
; Recavery from interrupt
CODE ENDS
; -------Vector setting---------------------------------------------VECT CSEG ABS=0FFH
ORG
0FF68H
; Setting vector of interrupt #37 (25H)
DSL
WARI
ORG
0FFDCH
; Setting reset vector
DSL
START
DB
00H
; Setting single chip mode
VECT ENDS
476
CHAPTER 16
CAN CONTROLLER
This chapter explains the functions and operations of
the CAN controller.
16.1 Overview of CAN Controller
16.2 Block Diagram of CAN Controller
16.3 Configuration of CAN Controller
16.4 Interrupts of CAN Controller
16.5 Explanation of Operation of CAN Controller
16.6 Precautions when Using CAN Controller
16.7 Program Example of CAN Controller
477
CHAPTER 16 CAN CONTROLLER
16.1
Overview of CAN Controller
The CAN (controller area network) is a serial communication protocol conformed to
CAN Ver.2.0A and Ver.2.0B.Transmitting and receiving can be performed in the
standard frame format and the extended frame format.
■ Features of CAN controller
• The CAN controller format conforms to CAN Ver.2.0A and Ver.2.0B.
• Transmitting and receiving can be performed in the standard frame format and the extended frame
format.
• Data frames can be transmitted automatically by remote frames receiving.
• The baud rate ranges from 10 KBps to 1 Mbps (at 16-MHz machine clock frequency).
• The CAN controller equips eight transmit/receive message buffers.
• The standard frame format provides transmitting and receiving with 11-bit ID and the extended frame
format 29-bit ID.
• Message data can be set from 0 byte to 8 bytes.
• Message buffer configuration can be performed at a multilevel.
• The CAN controller contains two acceptance mask registers, each of which can set a mask
independently for a receive message ID.
• The two acceptance mask registers allow reception in the standard frame and extended frame formats.
• Four masks can be set at all bit comparison and masking, and partially at acceptance mask registers 0
and 1.
478
CHAPTER 16 CAN CONTROLLER
16.2
Block Diagram of CAN Controller
The CAN controller consists of two types of registers; one controls the CAN controller
and the other controls each message buffer.
■ Block Diagram of CAN Controller
Figure 16.2-1 Block Diagram of CAN Controller
2
Operating clock (TQ)
F MC-16LX bus
CPU operating
clock
PSC
TS1
TS2
RSJ
TOE
TS
RS
CSR HALT
NIE
NT
NS1,0
Prescaler
(divided by 1 to 64)
Sing segment
Time segment 1
Time segment 2
Bit timing generating circuit
BTR
Error
control
circuit
RTEC
BVALR
TREQR
Bus state
judge
circuit
Node status
transfer interrupt
signal
Node status
transfer interrupt
generating circuit
Transmission
buffer clear Transmission buffer Transmission
determine circuit buffer
Transmission/
reception sequencer
Error frame
generating circuit
Acceptance
Data
counter filter control circuit
Over load frame
generating circuit
Transmission
Reception ID selection
DLC
DLC
Transmission buffer
Bit error, stuff error,
CRC error, frame error,
ACK error
TCANR
Idle, interrupt,
suspend,
transmission,
reception,
error, over load
Arbitration lost
Output
driver
Pin TX
Input
latch
Pin RX
TRTRR
Transmission shift
register
RFWTR
TCR
TIER
RCR
Set and clear of transmission buffer
Transmission completion
Transmission
interrupt generating circuit competion
interrupt signal
Setting of reception buffer
Reception
completion
interrupt circuit
Reception complemet
interrupt generating
circuit
RIER
RRTRR
Set and clear of reception buffer
ROVRR
ID select
Setting of
reception buffer
CRC
generating
Transmission
circuit
DLC
CRC error
0
1
AMR0
Reception shift
register
AMR1
Reception buffer
determine circuit
Reception buffer
RAM address
generating circuit
Stuff error
Destuffing/
stuffing error check
Bit error
Acceptance
filter
ACK
generating
circuit
Reception CRC generating circuit/
DLC
error check
Arbitration lost
AMSR
IDR0 to 7
DLCR0 to 7
DTR0 to 7
RAM
Stuffing
Arbitration
check
Bit error
check
ACK error
Acknowledge
error check
Form error
Form error
check
Reception buffer, transmissio buffer, reception DLC, transmission DLC, ID selection
IDER
LEIR
The pin names in the block diagram are as follows:
TX pin: P43/TX
RX pin: P44/RX
479
CHAPTER 16 CAN CONTROLLER
● Bit timing register (BTR)
This register sets the division ratio at which CAN bit timing is generated.
● Control status register (CSR)
This register controls the operation of the CAN controller.It indicates the state of transmitting/receiving and
the CAN bus, controls interrupts, and controls the bus halt and indicates its state.
● Receive/transmit error counter register (RTEC)
This register indicates the number of times transmit and receive errors have occurred.It counts up when an
error occurs in transmitting and receiving messages and counts down when transmitting and receiving are
performed normally.
● Message buffer validating register (BVALR)
This register enables or disables a specified message buffer.It also indicates the enabled/disabled status.
● IDE register (IDER)
This register sets the frame format of each message buffer.It sets the standard frame format or extended
frame format.
● Transmit request register (TREQR)
This register sets a transmit request to each message buffer.
● Transmit cancel register (TCANR)
This register cancels transmit requests held in each buffer message.
● Transmit RTR register (TRTRR)
This register selects a frame format transmitted to each message buffer.It selects the data frame or remote
frame.
● Remote frame receive waiting register (RFWTR)
This register sets the condition for transmitting start when a transmit request of the data frame is set.
● Transmit complete register (TCR)
Sets the bit which is corresponds to the number of the message buffer that completes message transmitting.
● Transmit complete interrupt enable register (TIER)
This register controls the generation of an interrupt request when each message buffer completes
transmitting.When an interrupt is enabled, an interrupt request is generated when transmitting is completed.
● Receive complete register (RCR)
This register sets the bit corresponding to the number of the message buffer that completes receiving
message.
● Receive complete interrupt enable register (RIER)
This register controls output of an interrupt request when each message buffer completes receiving.If
output of an interrupt request is enabled, an interrupt request is output at completion of receiving.
480
CHAPTER 16 CAN CONTROLLER
● Receive RTR register (RRTRR)
When a remote frame is stored in a message buffer, the bit corresponding to the number of the message
buffer is set.
● Receive overrun register (ROVRR)
This register sets the bit corresponding to the number of the buffer that overruns when the message is
received.
● Acceptance mask select register (AMSR)
This register sets the method for masking the receive message for each message buffer.
● Acceptance mask registers (AMR0 and AMR1)
These registers set a mask with the ID for filtering the message to be received.
● Last event indication register (LEIR)
This register indicates the operating state that last occurred.It indicates that either node status transition,
transmitting completion, or receiving completion occurred.
● Prescaler
The prescaler generates a bit timing clock at a frequency of 1/1 to 1/64 of the system clock.
It sets the operation clock (TQ).
● Bit timing generator
This generator detects a bit timing clock signal to generate a sync segment and time segments 1 and 2.
● Node status transition interrupt generator
This generates a node status transition interrupt signal when the node status transits.
● Bus state identification circuit
This circuit identifies the CAN bus state from the bus halt bit (CSR: HALT) and the signal from the error
frame generator.
● Acceptance filter
This filter compares the receive message ID with the acceptance code to select the message to be received.
● Transmit message buffers/receive message buffers
There are 8 message buffers to store the message to be transmitted and received.They store the message to
be transmitted and received.
● CRC generator/ACK generator
This circuit generates a CRC field or an ACK field when a data frame or remote frame is transmitted.
481
CHAPTER 16 CAN CONTROLLER
16.3
Configuration of CAN Controller
This section explains the pins and, related registers, interrupt factors of the CAN
controller.
■ Pins of CAN Controller
Table 16.3-1 CAN controller pin
Pin name
Function
Pin setting during used by CAN
TX
Transmitting output pin
General purpose I/O port
Set transmitting output pin
(If TOE bit of CSR register = 1)
RX
Receiving input pin
General purpose I/O port
Set receiving input pin
(If bit4 of DDR4 register = 0)
■ Block Diagram for Pins of CAN Controller
Reference:
482
For details of pin block diagram, see "CHAPTER 4 I/O PORT".
CHAPTER 16 CAN CONTROLLER
■ CAN Controller Registers
Figure 16.3-1, Figure 16.3-2 and Figure 16.3-3 list the registers of the CAN controller.
Figure 16.3-1 Registers of CAN Controller (Control Registers)
CAN controller control register
bit15
bit8 bit7
bit0
Reset value
Reserved area *
BVALR (Message buffer valid register)
00000000B
Reserved area *
TREQR (Transmission request register)
00000000B
Reserved area *
TCANR (Transmission cancel register)
00000000B
Reserved area *
TCR (Transmission completion register)
00000000B
Reserved area *
RCR (Reception completion register)
00000000B
Reserved area *
RRTRR (Reception RTR register)
00000000B
Reserved area *
ROVRR (Reception overrun register)
00000000B
Reserved area *
RIER (Reception completion interrupt enable register)
00000000B
bit15
bit8 bit7
bit0
CSR (Control status register)
Reserved area *
Reset value
00XXX000B
0XXXX001B
000XX000B
LEIR (Last event display register)
RTEC (Transmission/reception error counter)
00000000B
00000000B
BTR (Bit timing register)
X1111111B
11111111B
Reserved area *
IDER (IDE register)
Reserved area *
TRTRR (Transmission RTR register)
Reserved area *
RFWTR (Remode frame reception waiting register)
Reserved area *
TIER (transmission completion interrupt enable register)
AMSR (Acceptance mask select register)
XXXXXXXXB
00000000B
XXXXXXXXB
00000000B
XXXXXXXXB
XXXXXXXXB
AMR0 (Acceptance mask select register 0)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
AMR1 (Acceptance mask select register 1)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Reserved area *
* : Resarved area is address for using in system, so it must not use.
483
CHAPTER 16 CAN CONTROLLER
Figure 16.3-2 Registers of CAN Controller (ID Register and DLC Register)
Message buffer (ID register)
bit15
bit8
bit7
bit0
XXXXXXXXB XXXXXXXXB
to
XXXXXXXXB XXXXXXXXB
RAM (general purpose RAM) (16byte)
IDR0 (ID register 0)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IDR1 (ID register 1)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IDR2 (ID register 2)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IDR3 (ID register 3)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IDR4 (ID register 4)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IDR5 (ID register 5)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IDR6 (ID register 6)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IDR7 (ID register 7)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Message buffer (DLC register)
bit15
bit8
bit7
bit0
Reset value
Reserved area *
DLC0 (DLC register 0)
XXXXXXXXB
Reserved area *
DLC1 (DLC register 1)
XXXXXXXXB
Reserved area *
DLC2 (DLC register 2)
XXXXXXXXB
Reserved area *
DLC3 (DLC register 3)
XXXXXXXXB
Reserved area *
DLC4 (DLC register 4)
XXXXXXXXB
Reserved area *
DLC5 (DLC register 5)
XXXXXXXXB
Reserved area *
DLC6 (DLC register 6)
XXXXXXXXB
Reserved area *
DLC7 (DLC register 7)
XXXXXXXXB
* : Resarved area is address for using in system, so it must not use.
484
Reset value
CHAPTER 16 CAN CONTROLLER
Figure 16.3-3 Registers of CAN Controller (DTR Register)
Message buffer (DTR register)
bit15
bit8 bit7
DTR0 (Data register 0) (8byte)
bit0
Reset value
XXXXXXXXB XXXXXXXXB
to
XXXXXXXXB XXXXXXXXB
DTR1 (Data register 1) (8byte)
XXXXXXXXB XXXXXXXXB
to
XXXXXXXXB XXXXXXXXB
DTR2 (Data register 2) (8byte)
XXXXXXXXB XXXXXXXXB
to
XXXXXXXXB XXXXXXXXB
DTR3 (Data register 3) (8byte)
XXXXXXXXB XXXXXXXXB
to
XXXXXXXXB XXXXXXXXB
DTR4 (Data register 4) (8byte)
XXXXXXXXB XXXXXXXXB
to
XXXXXXXXB XXXXXXXXB
DTR5 (Data register 5) (8byte)
XXXXXXXXB XXXXXXXXB
to
XXXXXXXXB XXXXXXXXB
DTR6 (Data register 6) (8byte)
XXXXXXXXB XXXXXXXXB
to
XXXXXXXXB XXXXXXXXB
DTR7 (Data register 7) (8byte)
XXXXXXXXB XXXXXXXXB
to
XXXXXXXXB XXXXXXXXB
Reserved area* (128byte)
*: Resarved area is address for using in system, so it must not use.
■ Generation of Interrupt Request by CAN Controller
The CAN controller has three types of interrupts: transmit complete interrupt, receive complete interrupt,
and node status interrupt. The CAN controller generates each interrupt request as follows:
• When a transmit complete interrupt is enabled for the message buffer (x) (TIRE: TIEx = 1), the TCx bit
in the transmit complete register is set to "1" and a transmit complete interrupt request is generated after
a completion of message transmitting.
• When a receive complete interrupt is enabled for the message buffer (x) (RIRE: RIEx = 1), the RCx bit
in the receive complete register is set to "1" and a receive complete interrupt request is generated after a
completion of message receiving.
• When a node status transition interrupt is enabled (CSR: NIE = 1), the NT bit in the CAN status register
is set to "1" and a node status transition interrupt request is generated after the node status transits.
485
CHAPTER 16 CAN CONTROLLER
16.3.1
Control Status Register (High) (CSR: H)
The control status register (CSR) controls operation of the CAN controller.The control
status register (High) (CSR: H) transmits and receives the message and indicates the
node status.
■ Control Status Register (High) (CSR: H)
Figure 16.3-4 Control Status Register (High) (CSR: H)
15
14
13
12
11
10
9
8
Reset value
00XXX000B
R
R
-
-
-
R/W
R
R
bit9 bit8
Node status bit
NS1 NS0
0
0
Error active
0
1
Warning (error active)
Error passive
1
0
Bus off
1
1
bit10
NT
Node status transfer flag
0
Without transfer of node status
1
With transfer of node status
bit14
RS
Reception status bit
0
Not receiving message
1
In receiving message
R/W : Read/Write
R : Read only
X
: Undefined
: Unused
: Reset value
Note:
486
bit15
TS
Transmission status bit
0
Not transmitting message
1
In transmitting message
It is prohibited to execute a bit operation (read-modify-write) instruction on the lower
8 bits of control status register (CSR).
Only in the case of HALT bits unchanged, use any bits operation instructions without
problems (initialization of the macro instructions e.t.c).
CHAPTER 16 CAN CONTROLLER
Table 16.3-2 Functions of Control Status Register (High) (CSR: H)
bit name
bit15
Function
TS:
Transmit status bit
This bit indicates whether the message is being transmitted.
Message being transmitted: Bit set to "1"
Error frame or overload frame being transmitted:
Bit set to "0"
bit14
RS:
Receive status bit
This bit indicates whether the message is being received.
Message being received: Bit set to "1"
• For example, if the message is on the bus, even during
message transmitting, this bit is set to "1".Regardless of
whether the receive message passes the acceptance filter.
Error frame or overload frame on bus: Bit set to "0"
• When the RS bit is "0", the bus halt state (HALT = 1), bus
intermission state and bus idle state are also included.
bit13
to
bit11
Unused bits
Read: The value is undefined.
Write: No effect.
bit10
NT:
Node status transition
flag bit
This bit indicates that the node status transits.
When node status transits: Bit set to "1"
1)Error active ("00B") → Warning ("01B")
2)Warning ("01B") → Error Passive ("10B")
3)Error Passive ("10B") → Bus off ("11B")
4)Bus off ("11B") → Error active ("00B")
(The parenthesized values are those for the NS1 and NS2 bits.)
When set to "0": The bit is cleared.
When set to "1": Disables bit setting.
Read using read modify write instructions: "1" always read.
bit9,
bit8
NS1, NS0:
Node status bits
The combination of the NS1 and NS0 bits indicates the current
node status.
"00B": Error active
"01B": Warning (error active)
"10B": Error passive
"11B": Bus off
Note:
Warning is included in error active in the CAN
specifications as a node status.
487
CHAPTER 16 CAN CONTROLLER
16.3.2
Control Status Register (Low) (CSR: L)
The control status register (CSR) controls operation of the CAN controller.The control
status register (Low) (CSR: L) enables and disables transmit interrupt and node status
transition interrupt and, controls bus halt and indicates the node status.
■ Control Status Register (Low) (CSR: L)
Figure 16.3-5 Control Status Register (Low) (CSR: L)
7
6
5
4
3
2
1
0
Reset value
0XXXX001B
R/W
-
-
-
-
R/W
W R/W
bit0
HALT
Bus halt bit
at reading
at writing
0
On bus operation
Canceling bus halt
1
Halting bus
Set bus halting
bit1
Reserved
Reserved bit
0
Be sure to set this bit to 0.
bit2
NIE
0
1
Node status transition interrupt output enable bit
Node status transition interrupt is prohibited
Node status transition interrupt is enabled
bit7
R/W
W
X
-
: Read/Write
: Write only
: Undefined
: Unused
TOE
0
1
Transmit output enable bit
Can be used as general-purpose I/O ports.
Can be used as transmit pin (TX)
:Reset value
Note:
488
It is prohibited to execute a bit operation (read-modify-write) instruction on the lower
8 bits of control status register (CSR).
Only in the case of HALT bits unchanged, use any bits operation instructions without
problems (initialization of the macro instructions, etc.).
CHAPTER 16 CAN CONTROLLER
Table 16.3-3 Functions of Control Status Register (Low) (CSR: L) (1/2)
bit name
Function
bit7
TOE:
Transmit
output
enable bit
This bit switches between general-purpose I/O port and transmit pin TX.
When set to "0": Functions as general-purpose I/O port
When set to "1": Functions as transmit pin (TX)
bit6
to
bit3
Unused bits
Read: The value is undefined.
Write: No effect
bit2
NIE:
Node status
transition
interrupt
output
enable bit
This bit controls generation of a node status transition interrupt when the node status transits (CSR: NT = 1).
When set to "0": Disables interrupt generation
When set to "1": Enables interrupt generation
bit1
Reserved:
reserved bit
Be sure to set this bit to "0".
Read: "0" is always read.
489
CHAPTER 16 CAN CONTROLLER
Table 16.3-3 Functions of Control Status Register (Low) (CSR: L) (2/2)
bit name
bit0
HALT:
Bus halt bit
Function
This bit controls the bus halt.The halt state of the bus can be checked by reading the HALT bit.
At reading
"0": on bus operation
"1": halting bus operation
At writing
"0": cancels bus halt
"1":set bus halt
Note: When write 0 to this bit during the node status is Bus Off, ensure that 1 is written to this bit.
Reference programming example:
switch (IO_CANCT0.CSR.bit.NS)
{
case 0:/* error active */
break;
case 1:/* warning */
break;
case 2:/* error passive */
break;
default:/* bus off */
for (i=0; (i<= 500) && (IO_CANCT0.CSR.bit.HALT= 0):i++);
IO_CANCT0.CSR.word = 0x0084; /* halt = 0 */
}
*: The variable i is used for fail safe.
[Conditions for halting bus]
• Hardware reset
• Node status transition to bus off
• Writing "1" to HALT bit
[Operation when bus halted]
Message being transmitted: Bus halted after completion of transmitting
Message being receiving: Bus halted immediately
Storing in message buffer: Bus halted after completion of storing
Note:
• To check whether the bus is halted, read the value of the HALT bit.
• Before switching to the low power consumption mode, write "1" to the HALT bit and then read the HALT bit
to check that the bus is completely halted (CSR: HALT = 1).
[Conditions for canceling bus halt]
• The state in which the bus is halted by a hardware reset or by writing "1" to the HALT bit is cancelled after 0
is written to the HALT bit and an 11-bit High level (receive) is input continuously to the receive input pin
(RX).
• The state in the bus off is cancelled after "0" is written to the HALT bit and an 11-bit High level (receive) is
input continuously 128 times to the receive input pin (RX).
• The values of the transmit and receive error counters are both returned to "0" and the node status transits to
error active.
Note: When write 0 to this bit during the node status is Bus Off, ensure that 1 is written to this bit.
[State in which bus halted]
• Transmitting and receiving are not performed.
• A High level (receive) is output to the transmit output pin (TX).
• Other registers or error counters are not updated.
Note:
• Set the bit timing register (BTR) after halting the bus.
490
CHAPTER 16 CAN CONTROLLER
16.3.3
Last event indication register (LEIR)
This register indicates the state of the last event (LEIR).
■ Last event indication register (LEIR)
Figure 16.3-6 Last event indication register (LEIR)
bit7
6
5
4
3
2
1
0
Reset value
000XX000B
R/W R/W R/W
-
-
R/W R/W R/W
bit2
MBP2
0
0
0
0
1
1
1
1
bit1
MBP1
0
0
1
1
0
0
1
1
bit0
MBP0
0
1
0
1
0
1
0
1
Message buffer pointer bit
Message buffer 0
Message buffer 1
Message buffer 2
Message buffer 3
Message buffer 4
Message buffer 5
Message buffer 6
message buffer 7
bit5
RCE
0
1
Last event=Reception complete bit
No receiving completed
Receiving completed
bit6
TCE
0
1
Last event=transmission complete bit
No transmitting completed
Transmitting completed
bit7
R/W : Read / Write
X
: Undefined
- : Unused
: Reset value
Note:
NTE
0
1
Last event=node status transition bit
No node ststus transition
Node ststus transition
If the condition is one of following on the last event, the other bit set 0.
- Last event = node status transmission bit (NTE)
- Last event = transmitting completed bit (TCE)
- Last event = receiving completed bit (RCE)
491
CHAPTER 16 CAN CONTROLLER
Table 16.3-4 Function of the last event display register (LEIR)
Bit name
bit7
NTE:
last event node status
transmitting bit
Function
This bit indicates that the last event refers to the node status transition.
Last event referring to node status transition: Sets bit to 1 when NTx bit in
control status register set (CSR: NTx = 1)
- The NTE bit is set to "1" at the same time that the TCx in the
transmission complete register (TCR) is set.
- Nothing is related to the setting of the NIE bit in the control status
register (CSR).
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
Read using read modify write instructions: "1" always read.
bit6
TCE:
last event transmitting completed bit
This bit indicates that the transmitting the last event is completed.
Transmitting of last event completed: Sets bit to "1" when TCx bit in
transmission complete register set (TCR: TCx = 1)
- Nothing is related to the setting of the reception complete interrupt
enable register (TIER).
- The number (x) of the message buffer that completes receiving the
message is indicated as the last event in the MBP2 to MBP0 bits.
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
Read using read modify write instructions: "1" always read.
bit5
RCE:
last event receiving
completed bit
This bit indicates that receiving the last event is completed.
Receiving of last event completed: Sets bit to "1" when RCx bit in reception
complete register set (RCR: RCx = 1)
- Nothing is related to the setting of the reception complete interrupt
enable register (RIER).
- The number (x) of the message buffer that completes receiving the
message is indicated as the last event in the MBP2 to MBP0 bits.
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
Read using read modify write instructions: "1" always read.
Note:
492
bit4,
bit3
undefined bit
At a read: The value is undefined.
At a write: No effect.
bit2
to
bit0
MBP2 to 0:
message buffer
pointer bit
These bits indicate the number (x) of the message buffer where the last event
occurs which is corresponding to each message buffer pointer bit.
Receiving completed: Indicates number (x) of message buffer that completes
receiving message
Transmitting completed: Indicates number (x) of message buffer that completes
transmitting message
Node status transition: The values of the MBP2 to MBP0 bits are invalid.
When set to "0": The bit is cleared.
When the bit is set to "1": No effect.
Read using read modify write instructions: "1" always read.
When the last event indicate register (LEIR) is accessed in interrupt processing of
the CAN controller, the event causing the interrupt does not always match the event
indicated by the last event indicate register (LEIR). Other event may occur before the
last event indicate register (LEIR) is accessed in interrupt processing after an
interrupt request is generated.
CHAPTER 16 CAN CONTROLLER
16.3.4
Receive/Transmit Error Counter (RTEC)
The receive/transmit error counter (RTEC) indicates the number of times an error
occurs at transmitting and receiving the message.It counts up when transmit or receive
errors occurs and counts down when transmitting and receiving are performed
normally.
■ Receive/Transmit Error Counter (RTEC)
Figure 16.3-7 Receive/transmit error counter
bit15
14
13
12
11
10
9
8
TEC7
TEC6
TEC5
TEC4
TEC3
TEC2
TEC1
TEC0
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
REC7
REC6
REC5
REC4
REC3
REC2
REC1
REC0
R
R
R
R
R
R
R
R
Reset value
00000000B
Reset value
00000000B
R : Read only
Table 16.3-5 Functions of Receive/Transmit Error Counter (RTEC)
bit name
Function
bit15
to
bit8
TEC7 to 0:
Transmit error counter
bits
Transmit error counter value = 96:
Node status transits to warning (CSR: NS1, NS0 = 01B)
Transmit error counter value = 128:
Node status transits to error passive (CSR: NS1, NS0 = 10B)
Transmit error counter value = 256:
Stops counting up. The node status transits to bus off
(CSR: NS1, NS0 = 11B).
bit7
to
bit0
REC7 to 0:
Receive error counter
bits
Reception error counter value = 96 or more:
The node status changes to warning (CSR: NS1, NS0 =01B).
Reception error counter value = 128 or more:
The node status changes to error passive
(CSR: NS1, NS0 = 10B).
Reception error counter value = 256 or more:
Stops incrementing.The node status remains with error
passive (CSR: NS1, NS0=10B).
493
CHAPTER 16 CAN CONTROLLER
■ Node Status Transition due to Error Occurrence
In the CAN controller, the node status transits according to the error count of the receive/transmit error
counter (RTEC).Figure 16.3-8 shows the node status transition.
Figure 16.3-8 Node Status Transition
Hardware reset
When transfering, need to release of bus
operation stop
Error active
REC ≥ 96
or TEC ≥ 96
REC < 96
and TEC < 96
REC : Reception error counter
TEC : Transmission error counter
After 0 was written to the HALT bit of the
control status register (CSR),
continuous 11-bit High levels (recessive) are
input 128 times to the receive input pin (RX)
to transit.
Warning
(error active)
REC ≥ 128
or TEC ≥ 128
REC < 128
and TEC < 128
Error passive
TEC ≥ 256
Bus off
(HALT=1)
Table 16.3-6 Node Status
Node Status
Error active
State of CAN Bus
Normal state
Warning
A bus fault occurs
Error passive
Bus off
494
Communications are disabled.The CAN controller is completely
isolated from the CAN bus.
(To return to the normal state, perform the steps in the above figure.)
CHAPTER 16 CAN CONTROLLER
16.3.5
Bit timing register (BTR)
The bit timing register (BTR) sets the prescaler and bit timing.Set this after halting the
bus (CSR: HALT = 1).
■ Bit timing register (BTR)
Figure 16.3-9 Bit timing register (BTR)
bit15
14
13
12
11
10
9
8
TS2.2
TS2.1
TS2.0
TS1.3
TS1.2
TS1.1
TS1.0
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
RSJ1
RSJ0
PSC5
PSC4
PSC3
PSC2
PSC1
PSC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
X1111111B
Reset value
11111111B
R/W : Read/Write
X
: Undefined
: Unused
-
Table 16.3-7 Function of bit timing register (BTR)
Bit name
Function
bit14
to
bit12
TS2.2 to 2.0:
time segment 2 setting
bits 2 to 0
These bits set the time of time segment 2 (TSEG2).
Time segment 2 is equivalent to phase buffer segment 2
(PHASE_SEG2) based on CAN specifications.
bit11
to
bit8
TS1.3 to 1.0:
time segment 1 setting
bits 3 to 0
These bits set the time of time segment 1 (TSEG1).
Time segment 1 is equivalent to propagation segment
(PROP_EG) and phase buffer segment 1 (PHASE_SEG1)
based on CAN specifications.
bit7,
bit6
RSJ1 to 0:
resynchronous jump
width setting bits 1, 0
These bits set the resynchronous jump width (RSJW).
bit5
to
bit0
PSC5 to 0:
prescaler setting bit 5
to 0
These bits divide the frequency of the system clock to
determine the time quantum (TQ) of the CAN controller.
Note:
Set the bit timing register (BTR) after halting the bus (CSR: HALT = 1). After setting the bit timing
register (BTR), write 0 to the HALT bit in the control status register to cancel the bus halt.
495
CHAPTER 16 CAN CONTROLLER
■ Definition of Bit Timing Segment
Bit timing is set in the bit timing register (BTR).Figure 16.3-10 and Figure 16.3-11 show the segments of
the nominal bit time (one bit of time within message) and bit timing register (BTR).
● Bit time segments of general CAN specifications
Figure 16.3-10 Bit Time Segments of CAN Specifications
nominal bit time
SYNC_SEG
(sync segment)
PROP_SEG
(propagetion segment)
PHASE_SEG1
(phase segment 1)
PHASE_SEG2
(phase segment 2)
samplingpoint
• SYNC_SEG (sync segment): Synchronization is performed to shorten or prolong the bit time.
• PROP_SEG (propagation segment): The physical delay among networks is adjusted.
• PHASE_SEG (phase segment): The phase shift due to oscillation errors is adjusted.
● Bit time segments of Fujitsu CAN controller
The propagation segment (PROP_SEG) and phase segment 1 (PHASE_SEG1) are used as a single segment
of time segment 1 (TSEG1).The phase segment 2 (PHASE_SEG2) is used as the time segment 2 (TSEG2).
Figure 16.3-11 Bit Time Segments of CAN Controller
nominal bit time
SYNC_SEG
(sync segment)
TSEG1
(time segment 1)
TSEG2
(time segment 2)
samplingpoint
• TSEG1 = PROP_SEG + PHASE_SEG1
• TSEG2 = PHASE_SEG2
496
CHAPTER 16 CAN CONTROLLER
■ Calculation of Bit Timing
Figure 16.3-12 and Figure 16.3-13 show the calculation example of bit timing, respectively, assuming input
clock (CLK), time quantum (TQ), bit time (BT), synchronous segment (SYNC_SEG), time segment 1, 2
(TSEG1, TSEG2), re-synchronous jump width (RSJW), frequency divided (PSC).
Figure 16.3-12 Calculation of Bit Timing
• TQ = (PSC + 1) × CLK
• BT = SYNC_SEG + TSEG1 + TSEG2
= (1 + (TS1 + 1) + (TS2 + 1) ) × TQ
= (3 + TS1 + TS2) × TQ
• RSJW = (RSJ + 1) × TQ
For each segment, the following conditions shoud be met.
• When PSC is 1 to 63 (2 to 64-devided clock)
TSEG1 ≥ 2TQ
TSEG1 ≥ RSJW
TSEG2 ≥ 2TQ
TSEG2 ≥ RSJW
• When PSC is 0 (1-devided clock)
TSEG1 ≥ 5TQ
TSEG2 ≥ 2TQ
TSEG2 ≥ RSJW
497
CHAPTER 16 CAN CONTROLLER
Figure 16.3-13 Calculation Example of Bit Timing
Example : When 1TQ is 1/20 bit timing at 100Kbps (1/100kbps/20)
Condition : (resynchronous jump width is 4TQ, delay time is 50μs)
(1) Calculations of time quantum (TQ) [TQ = (PSC + 1) × CLK]
(Unit: μs)
Division of input clock (PSC+1)
10 11 12 13 14 15
9
8
7
6
5
4
1
3
2
0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75
0.13 0.25 0.38 0.5 0.63 0.75 0.88 1 1.13 1.25 1.38 1.5 1.63 1.75 1.88
0.06 0.13 0.19 0.25 0.31 0.38 0.44 0.5 0.56 0.63 0.69 0.75 0.81 0.88 0.94
Machine clock (CLK)
4MHz (0.25 μs)
8MHz (0.125 μs)
16MHz (0.0625 μs)
(4) Condition of bit timing (BT) [BT ≥ 8TQ]
MAchine clock (CLK)
4MHz (0.25 μs)
8MHz (0.125 μs)
16MHz (0.0625 μs)
2
1
0.5
4
2
1
(Unit: μs)
6
3
1.5
8
4
2
10
5
2.5
14
7
3.5
12
6
3
8TQ
16 18
9
8
4.5
4
20
10
5
22
11
5.5
24
12
6
26
13
6.5
28
14
7
30
15
7.5
(3) Setting of resynchronous jump width (when resynchronous jump width is 4TQ)
RSJ+1 (Division of TQ)
RSJW = (RSJ + 1) × TQ
1
0.5
2
1
3
1.5
4 (Unit: TQ)
2 (Unit: us)
1
1
0.5
2
2
1
3
3
1.5
4
4
2
(5) Condition of TSEG2
RSJW = (RSJ + 1) × TQ
TSEG2 ≥ RSJW
TSEG2 ≥ RSJW
(Unit: TQ)
(Unit: TQ)
(Unit: us)
(6) Condition of TSEG1
TSEG1 ≥ Delay time + RSJW (Assuming that delaytime is 50ns) × 2 + 4TQ ≥ 5TQ
TSEG1
5 (Unit: TQ)
(2) Calculation of bit time (BT) based or the above setting and condition
BT = SYNC_SEG + TSEG1 + TSEG2
= (1 + (TS1 + 1)+ (TS2+1)) × TQ
= (3 + TS1 + TS2) × TQ
Calculating of sample point
SYNC_SEG + (TSEG1 + 1) TSEG2 + 1
(1)
(2)
(3)
(4)
(5)
16
15
14
13
12
4
5
6
7
8
SYNC_SEG TSEG 1 + 1 TSEG2 + 1
Sample point
498
Sample
point
80%
75%
70%
65%
60%
TSEG1 + 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Unit: kbps)
1
667
500
400
333
286
250
222
200
182
167
154
143
133
125
118
111
2
500
400
333
286
250
222
200
182
167
154
143
133
125
118
111
105
3
400
333
286
250
222
200
182
167
154
143
133
125
118
111
105
100
TSEG2 + 1
6
5
4
333 286 250
286 250 222
250 222 200
222 200 182
200 182 167
182 167 154
167 154 143
154 143 133
143 133 125
133 125 118
125 118 111
118 111 105
111 105 100
105 100 95.2
100 95.2 90.9
95.2 90.9 87
(1) (2) (3) (4) (5)
7
222
200
182
167
154
143
133
125
118
111
105
100
95.2
90.9
87
83.3
8
200
182
167
154
143
133
125
118
111
105
100
95.2
90.9
87
83.3
80
CHAPTER 16 CAN CONTROLLER
16.3.6
Message buffer validating register (BVALR)
The message buffer valid register (BVALR) enables or disables the message buffers
and indicates their status.
■ Message buffer validating register (BVALR)
Figure 16.3-14 Message buffer validating register (BVALR)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit0
BVAL0
0
1
bit1
BVAL1
0
1
bit2
BVAL2
0
1
bit3
BVAL3
0
1
bit4
BVAL4
0
1
bit5
BVAL5
0
1
bit6
BVAL6
0
1
bit7
BVAL7
R/W : Read / Write
: Reset value
0
1
Message buffer enable bit 0
message buffer 0 disabled
message buffer 0 enable
Message buffer enable bit 1
message buffer 1 disabled
message buffer 1 enable
Message buffer enable bit 2
message buffer 2 disabled
message buffer 2 enable
Message buffer enable bit 3
message buffer 3 disabled
message buffer 3 enable
Message buffer enable bit 4
message buffer 4 disabled
message buffer 4 enable
Message buffer enable bit 5
message buffer 5 disabled
message buffer 5 enable
Message buffer enable bit 6
message buffer 6 disabled
message buffer 6 enable
Message buffer enable bit 7
message buffer 7 disabled
message buffer 7 enable
499
CHAPTER 16 CAN CONTROLLER
Table 16.3-8 Functions of Message Buffer Enable Register
Bit name
bit7
to
bit0
BVAL7 to 0:
Message buffer enable
bits 7 to 0
Function
These bits enable or disable transmitting and receiving of the
message to and from the message buffer (x).
When set to "0": No message can be transmitted and received
to and from the message buffer (x).
When set to "1": A message can be transmitted and received to
and from the message buffer (x).
When Message buffer set disabled (BVALx = 0)
During transmitting: Transmitting and receiving are disabled
after message transmitting is completed
or a transmit error is terminated.
During receiving: Transmitting and receiving are disabled
immediately. When the received message is
stored in the message buffer, transmitting
and receiving are disabled after the message
is stored.
Note:
The read modify write instructions are disabled until the
BVALx bit is actually set to "0" after "0" is written to the bit.
500
CHAPTER 16 CAN CONTROLLER
16.3.7
IDE register (IDER)
The IDE register (IDER) sets the frame format of the message buffer used during
transmitting and receiving.Transmitting and receiving are enabled in the standard frame
format (ID11 bits) and the extended frame format (ID29 bits).
■ IDE register (IDER)
Figure 16.3-15 IDE register (IDER)
7
6
5
4
3
2
1
0
Reset value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit0
IDE0
0
1
bit1
IDE1
0
1
bit2
IDE2
0
1
bit3
IDE3
0
1
bit4
IDE4
0
1
bit5
IDE5
0
1
bit6
IDE6
0
1
bit7
IDE7
X
: Undefined
R/W : Read/Write
0
1
ID Format select bit 0 (message buffer 0)
Standard format (ID11bit) are used
Extended format (ID29bit) are used
ID Format select bit 1 (message buffer 1)
Standard format (ID11bit) are used
Extended format (ID29bit) are used
ID Format select bit 2 (message buffer 2)
Standard format (ID11bit) are used
Extended format (ID29bit) are used
ID Format select bit 3 (message buffer 3)
Standard format (ID11bit) are used
Extended format (ID29bit) are used
ID Format select bit 4 (message buffer 4)
Standard format (ID11bit) are used
Extended format (ID29bit) are used
ID Format select bit 5 (message buffer 5)
Standard format (ID11bit) are used
Extended format (ID29bit) are used
ID Format select bit 6 (message buffer 6)
Standard format (ID11bit) are used
Extended format (ID29bit) are used
ID Format select bit 7 (message buffer 7)
Standard format (ID11bit) are used
Extended format (ID29bit) are used
501
CHAPTER 16 CAN CONTROLLER
Table 16.3-9 Functions of IDE Register (IDER)
Bit name
bit7
to
bit0
502
IDE7 to 0:
ID Format select bits 7
to 0
Function
Set the frame format used in the message buffer (x).
When set to "0": Uses message buffer (x) in standard format
(ID11 bits)
When set to "1": Uses message buffer (x) in extended format
(ID29 bits)
Note:
The IDE register (IDER) should be set after having the
message buffer (x) disabled (BVALR: BVALx = 0). Setting
the IDE register (IDER) with the message buffer (x) being
enabled may store message unnecessary received.
CHAPTER 16 CAN CONTROLLER
16.3.8
Transmit request register (TREQR)
The transmission request register (TREQR) sets a transmit request for each message
buffer and indicates its status.
■ Transmit request register (TREQR)
Figure 16.3-16 Transmit request register (TREQR)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit0
Transmission request bit 0 (message buffer 0)
TREQ0
Not request transmission (When reception no request transmission)
0
Transmit repuest (When reception transmit request)
1
bit1
TREQ1
0
1
bit2
TREQ2
0
1
bit3
TREQ3
0
1
Transmission request bit 1 (message buffer 1)
Not request transmission (When reception no request transmission)
Transmit repuest (When reception transmit request)
Transmission request bit 2 (message buffer 2)
Not request transmission (When reception no request transmission)
Transmit repuest (When reception transmit request)
Transmission request bit 3 (message buffer 3)
Not request transmission (When reception no request transmission)
Transmit repuest (When reception transmit request)
bit4
Transmission request bit 4 (message buffer 4)
TREQ4
Not request transmission (When reception no request transmission)
0
1
Transmit repuest (When reception transmit request)
bit5
TREQ5
0
1
Transmission request bit 5 (message buffer 5)
Not request transmission (When reception no request transmission)
Transmit repuest (When reception transmit request)
bit6
Transmission request bit 6 (message buffer 6)
TREQ6
Not request transmission (When reception no request transmission)
0
1
Transmit repuest (When reception transmit request)
R/W : Read/Write
: Reset value
bit7
Transmission request bit 7 (message buffer 7)
TREQ7
Not request transmission (When reception no request transmission)
0
1
Transmit repuest (When reception transmit request)
503
CHAPTER 16 CAN CONTROLLER
Table 16.3-10 Functions of Transmission Request Register (TREQR)
Bit name
bit7
to
bit0
TREQ7 to 0:
Transmission request
bits 7 to 0
Function
These bits starts transmitting for the message buffer (x).
When set to "0": No effect on operation
When set to "1": Starts transmitting for message buffer (x)
- If more than one transmit complete bit is set (TREQx =
1), transmitting is started with the lower number of the
message buffer (x) that accepts the transmit request.
- These bits remain "1" during the transmit being
requested. These bits are cleared to "0" when
transmitting is completed or the transfer request is
cancelled.
- Clearing a transmit request when transmitting is
completed (TREQx = 0) overrides setting of the transmit
request bit when "0" is written (TREQx = 1) if both
occur at the same time.
Read using read modify write instructions: "1" always read
Setting of remote frame receive wait bit (RFWTR: RFWTx)
RFWTx bit = 0: Starts transmitting immediately. Even if
RRTRx bit in receive RTR register = 1.
RFWTx bit = 1: Starts transmitting after remote frame received.
504
CHAPTER 16 CAN CONTROLLER
16.3.9
Transmit RTR register (TRTRR)
This register sets the frame format of transmit message for the message buffers.
■ Transmit RTR register (TRTRR)
Figure 16.3-17 Transmit RTR register (TRTRR)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit0
TRTR0
0
1
Remote frame setting bit 0
(message buffer 0)
Transmit a data frame
Transmit a remote frame
bit1
TRTR1
Remote frame setting bit 1
(message buffer 1)
0
Transmit a data frame
1
Transmit a remote frame
bit2
TRTR2
Remote frame setting bit 2
(message buffer 2)
0
Transmit a data frame
1
Transmit a remote frame
bit3
TRTR3
Remote frame setting bit 3
(message buffer 3)
0
Transmit a data frame
1
Transmit a remote frame
bit4
TRTR4
Remote frame setting bit 4
(message buffer 4)
0
Transmit a data frame
1
Transmit a remote frame
bit5
TRTR5
0
1
Remote frame setting bit 5
(message buffer 5)
Transmit a data frame
Transmit a remote frame
bit6
TRTR6
0
1
Remote frame setting bit 6
(message buffer 6)
Transmit a data frame
Transmit a remote frame
bit7
TRTR7
R/W : Read/Write
: Reset value
0
1
Remote frame setting bit 7
(message buffer 7)
Transmit a data frame
Transmit a remote frame
505
CHAPTER 16 CAN CONTROLLER
• When "0" is written to each bit in the transmit RTR register (TRTRR), the data frame format is set.
When "1" is written to each bit, the remote frame format is set.
Table 16.3-11 Functions of Transmission RTR Register (TRTRR)
Bit name
bit7
to
bit0
506
TRTR7 to 0:
Remote frame setting
bits 7 to 0
Function
These bits set the transfer format of the message buffer (x) for
transmitting or receiving.
When set to "0": Sets data frame format
When set to "1": Sets remote frame format
CHAPTER 16 CAN CONTROLLER
16.3.10
Remote frame receive waiting register (RFWTR)
Remote frame receiving wait register (RFWTR) sets whether a remote frame receiving
wait occurs or not, when transmission request of data frame is set.
■ Remote frame receive waiting register (RFWTR)
Figure 16.3-18 Remote frame receive waiting register (RFWTR)
7
6
5
4
3
2
1
0
Reset value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
bit0
RFWT0
Remote frame receiving wait bit 0
(message buffer 0)
0
transmission immediately
1
Transmitting after remote frame received
bit1
RFWT1
0
1
Remote frame receiving wait bit 1
(message buffer 1)
transmission immediately
Transmitting after remote frame received
bit2
RFWT2
Remote frame receiving wait bit 2
(message buffer 2)
0
transmission immediately
1
Transmitting after remote frame received
bit3
RFWT3
Remote frame receiving wait bit 3
(message buffer 3)
0
transmission immediately
1
Transmitting after remote frame received
bit4
RFWT4
0
1
Remote frame receiving wait bit 4
(message buffer 4)
transmission immediately
Transmitting after remote frame received
bit5
RFWT5
0
1
bit6
RFWT6
0
1
Remote frame receiving wait bit 5
(message buffer 5)
transmission immediately
Transmitting after remote frame received
Remote frame receiving wait bit 6
(message buffer 6)
transmission immediately
Transmitting after remote frame received
bit7
RFWT7
R/W : Read/Write
0
1
Remote frame receiving wait bit 7
(message buffer 7)
transmission immediately
Transmitting after remote frame received
507
CHAPTER 16 CAN CONTROLLER
Table 16.3-12 Functions of Remote Frame Receiving Wait Register (RFWTR)
Bit name
bit7
to
bit0
RFWT7 to 0:
Remote frame receive
bits 7 to 0
Function
These bits set whether to wait for reception of a remote frame
for the message buffer (x) for which a request to transmit a data
frame is set.
When set to "0": Starts transmitting immediately for message
buffer (x) for which a request to transmit data
frame set
- Transmitting is started immediately even if the receive
RTR register is already set in the message buffer (x)
(RRTRR: RRTRx = 1).
When set to "1": Starts transmitting after remote frame is
received in message buffer (x) in which a
request to transmit a data frame
Note:
When transmitting a remote frame, do not write 1 to the
RFWTx bit.
Reference:
508
• For details on the transmission request register (TREQR), see "16.3.8
Transmission Request Register (TREQR)".
• For details on the transmission RTR register (TRTRR), see "16.3.9 Transmission
RTR Register (TRTRR)".
• For details on the receive RTR register (RRTRR), see "16.3.15 Reception RTR
Register (RRTRR)".
CHAPTER 16 CAN CONTROLLER
16.3.11
Transmission cancel register (TCANR)
The transmission cancel register (TCANR) sets cancellation of a transmission request
for the message buffer in the transmit wait state.
■ Transmit cancel register (TCANR)
Figure 16.3-19 Transmit cancel register (TCANR)
7
6
5
4
3
2
1
0
W
W
W
W
W
W
W
W
Reset value
00000000B
bit0
TCAN0
0
1
Transmission on cancel bit 0
No effect on operation
Cancel transmission request for message buffer 0
bit1
Transmission on cancel bit 1
TCAN1
No effect on operation
0
1
Cancel transmission request for message buffer 1
bit2
TCAN2
0
1
bit3
TCAN3
0
1
Transmission on cancel bit 2
No effect on operation
Cancel transmission request for message buffer 2
Transmission on cancel bit 3
No effect on operation
Cancel transmission request for message buffer 3
bit4
Transmission on cancel bit 4
TCAN4
No effect on operation
0
1
Cancel transmission request for message buffer 4
bit5
Transmission on cancel bit 5
TCAN5
No effect on operation
0
1
Cancel transmission request for message buffer 5
bit6
TCAN6
0
1
bit7
TCAN7
W
: Write only
:Reset value
0
1
Transmission on cancel bit 6
No effect on operation
Cancel transmission request for message buffer 6
Transmission on cancel bit 7
No effect on operation
Cancel transmission request for message buffer 7
509
CHAPTER 16 CAN CONTROLLER
Table 16.3-13 Functions of Transmission Cancel Register (TCANR)
Bit name
bit7
to
bit0
510
TCAN7 to 0:
Transmission on cancel
bits 7 to 0
Function
These bits cancel a transmission request for the message buffer
(x) in the transmit wait state.
When set to "0": No effect on operation
When set to "1": Cancels transmission request for message
buffer (x)
• When a transmission request is cancelled by setting 1 to the
TCANx bit, the TREQx bit corresponding to the message
buffer (x) is cleared (TREQx = 0) for which transmission
request is cancelled.
Read: "0" is always read.
Note:
The transmission cancel register (TCANR) is a write-only
register.
CHAPTER 16 CAN CONTROLLER
16.3.12
Transmit complete register (TCR)
The transmission complete register (TCR) indicates whether a data transmission from
the message buffer completes.When an output of interrupt is enabled at completing
transmitting, an interrupt request is output when transmission is completed.
■ Transmit complete register (TCR)
Figure 16.3-20 Transmit complete register (TCR)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit0
TC0
0
1
bit1
TC1
0
1
bit2
TC2
0
1
bit3
TC3
0
1
bit4
TC4
0
1
bit5
TC5
0
1
bit6
TC6
0
1
R/W : Read/Write
: Reset value
bit7
TC7
0
1
Transmission complete bit 0 (message buffer 0)
Not Transmitting complete / Not transmission
Transmitting complete
Transmission complete bit 1 (message buffer 1)
Not Transmitting complete / Not transmission
Transmitting complete
Transmission complete bit 2 (message buffer 2)
Not Transmitting complete / Not transmission
Transmitting complete
Transmission complete bit 3 (message buffer 3)
Not Transmitting complete / Not transmission
Transmitting complete
Transmission complete bit 4 (message buffer 4)
Not Transmitting complete / Not transmission
Transmitting complete
Transmission complete bit 5 (message buffer 5)
Not Transmitting complete / Not transmission
Transmitting complete
Transmission complete bit 6 (message buffer 6)
Not Transmitting complete / Not transmission
Transmitting complete
Transmission complete bit 7 (message buffer 7)
Not Transmitting complete / Not transmission
Transmitting complete
511
CHAPTER 16 CAN CONTROLLER
Table 16.3-14 Functions of Transmission Complete Register (TCR)
Bit name
bit7
to
bit0
TC7 to 0:
Transmission complete
bits 7 to 0
Function
These bits indicate whether the message buffer (x) completes
transmitting message.
When message transmitting completed: "1" is set to the TCx bit
corresponding to the message buffer (x) that completes
transmitting.
When set to "0": Clears bits if transmitting already completed
When set to "1": No effect
Read using read modify write instructions: "1" always read
• Setting the TCx bit when transmitting is completed
(TCx = 1) overrides clearing of the TCx bit when 0 is
written (TCx = 0) if both occur at the same time.
• When the TREQx bit in the transmit request register
(TREQR) is set (TREQR: TREQx = 1), the TCx bit is
cleared (TCx = 0).
Generation of transmission complete interrupt
• If the transmit complete interrupt enable register (TIER) is
set (TIER: TIEx = 1), a transmit complete interrupt is
generated when transmitting is completed (TCR: TCx = 1).
512
CHAPTER 16 CAN CONTROLLER
16.3.13
Transmit complete interrupt enable register (TIER)
The transmission complete interrupt enable register (TIER) enables or disables a
transmit complete interrupt for each message buffer.
■ Transmit complete interrupt enable register (TIER)
Figure 16.3-21 Transmit complete interrupt enable register (TIER)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit0
TIE0
0
1
Transmission interrupt enable bit 0
(message buffer 0)
Transmission complete interrupt disabled
Transmission complete interrupt enable
bit1
TIE1
0
1
Transmission interrupt enable bit 1
(message buffer 1)
Transmission complete interrupt disabled
Transmission complete interrupt enable
bit2
TIE2
0
1
Transmission interrupt enable bit 2
(message buffer 2)
Transmission complete interrupt disabled
Transmission complete interrupt enable
bit3
TIE3
0
1
Transmission interrupt enable bit 3
(message buffer 3)
Transmission complete interrupt disabled
Transmission complete interrupt enable
bit4
TIE4
0
1
Transmission interrupt enable bit 4
(message buffer 4)
Transmission complete interrupt disabled
Transmission complete interrupt enable
bit5
TIE5
0
1
Transmission interrupt enable bit 5
(message buffer 5)
Transmission complete interrupt disabled
Transmission complete interrupt enable
bit6
TIE6
0
1
Transmission interrupt enable bit 6
(message buffer 6)
Transmission complete interrupt disabled
Transmission complete interrupt enable
bit7
TIE7
R/W : Read/Write
: Reset value
0
1
Transmission interrupt enable bit 7
(message buffer 7)
Transmission complete interrupt disabled
Transmission complete interrupt enable
513
CHAPTER 16 CAN CONTROLLER
Table 16.3-15 Functions of Transmission Complete Interrupt Enable Register (TIER)
Bit name
bit7
to
bit0
514
TIE7 to 0:
Transmission complete
interrupt enable bits 7 to
0
Function
These bits enable or disable a transmission complete interrupt
for the message buffer (x).
When set to "0": Disables transmit complete interrupt for
message buffer (x)
When set to "1": Enables transmit complete interrupt for
message buffer (x)
CHAPTER 16 CAN CONTROLLER
16.3.14
Receive complete register (RCR)
The reception complete register (RCR) indicates whether the reception of data to the
message buffer (x) completes. When an interrupt is enabled at completion of receiving,
an interrupt request is generated.
■ Receive complete register (RCR)
Figure 16.3-22 Receive complete register (RCR)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit0
RC0
0
1
bit1
RC1
0
1
bit2
RC2
0
1
bit3
RC3
0
1
bit4
RC4
0
1
bit5
RC5
0
1
bit6
RC6
0
1
R/W : Read/Write
: Reset value
bit7
RC7
0
1
Reception complete bits0 (message buffer 0)
Not reception complete / Not receiving
Reception complete
Reception complete bits1 (message buffer 1)
Not reception complete / Not receiving
Reception complete
Reception complete bits2 (message buffer 2)
Not reception complete / Not receiving
Reception complete
Reception complete bits3 (message buffer 3)
Not reception complete / Not receiving
Reception complete
Reception complete bits4 (message buffer 4)
Not reception complete / Not receiving
Reception complete
Reception complete bits5 (message buffer 5)
Not reception complete / Not receiving
Reception complete
Reception complete bits6 (message buffer 6)
Not reception complete / Not receiving
Reception complete
Reception complete bits6 (message buffer 6)
Not reception complete / Not receiving
Reception complete
515
CHAPTER 16 CAN CONTROLLER
Table 16.3-16 Functions of Reception Complete Register (RCR)
Bit name
bit7
to
bit0
RC7 to0:
Reception complete bit 7
to 0
Function
These bits indicate whether the message buffer (x) completes
message transmitting.
When message receiving completed: "1" is set to the RCx bit
corresponding to the message buffer (x) that completes
receiving.
When set to "0": Clears bits when receiving already completed
When set to "1": No effect
Read using read modify write instructions: "1" always read
• Setting the RCx bit when receiving is completed (TCx = 1)
overrides clearing of the RCx bit when 0 is written (RCx = 0)
if both occur at the same time.
[Generation of reception complete interrupt]
• If the transmit complete enable register is set (RIER: RIEx = 1),
a reception complete interrupt is generated when receiving is
completed.
Note:
To clear the reception complete register (RCR), read the
received message after the completion of receiving and write 0.
516
CHAPTER 16 CAN CONTROLLER
16.3.15
Receive RTR register (RRTRR)
The reception RTR register (RRTRR) indicates that the remote frame is stored in the
message buffer.
■ Receive RTR register (RRTRR)
Figure 16.3-23 Receive RTR register (RRTRR)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit0
RRTR0
0
1
Remot frame receive bits0
(message buffers 0)
Not remote frame received
Remote frame received
bit1
RRTR1
0
1
Remot frame receive bits1
(message buffers 1)
Not remote frame received
Remote frame received
bit2
RRTR2
0
1
Remot frame receive bits2
(message buffers 2)
Not remote frame received
Remote frame received
bit3
RRTR3
0
1
Remot frame receive bits3
(message buffers 3)
Not remote frame received
Remote frame received
bit4
RRTR4
0
1
Remot frame receive bits4
(message buffers 4)
Not remote frame received
Remote frame received
bit5
RRTR5
Remot frame receive bits5
(message buffers 5)
0
Not remote frame received
1
Remote frame received
bit6
RRTR6
0
1
Remot frame receive bits6
(message buffers 6)
Not remote frame received
Remote frame received
bit7
RRTR7
R/W : Read/Write
: Reset value
Remot frame receive bits6
(message buffers 6)
0
Not remote frame received
1
Remote frame received
517
CHAPTER 16 CAN CONTROLLER
Table 16.3-17 Functions of Reception RTR Register (RRTRR)
Bit name
bit7
to
bit0
518
RRTR7 to 0:
Remote frame receive
bits 7 to 0
Function
These bits indicate that the message buffer (x) receives a remote
frame.
When remote frame is received:
"1" is set to the RRTRx bit corresponding to the message
buffer (x) that receives a remote frame.
When set to "0": Clears bits when receiving already completed
When set to "1": No effect
• Setting the RRTRx bit when a remote frame is received
(RRTRx = 1) overrides clearing of the RRTRx bit when 0 is
written (RRTRx = 0) if both occur at the same time.
• The RRTRx bit corresponding to the message buffer (x) that
receives a data frame is cleared (RRTRx = 0).
• If message transmitting is completed (TCR: TCx = 1), the
RRTRx bit corresponding to the message buffer (x) that
transmits the message is cleared (RRTRx = 0).
Read using read modify write instructions: "1" always read
CHAPTER 16 CAN CONTROLLER
16.3.16
Receive overrun register (ROVRR)
The reception overrun register (ROVRR) indicates that an overrun occurs (the
corresponding message buffer is in the receive complete state) at storing the received
message in the message buffer.
■ Receive overrun register (ROVRR)
Figure 16.3-24 Receive overrun register (ROVRR)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit0
ROVR0
0
1
bit1
ROVR1
0
1
bit2
ROVR2
0
1
bit3
ROVR3
0
1
bit4
ROVR4
0
1
bit5
ROVR5
0
1
bit6
ROVR6
0
1
bit7
ROVR7
R/W : Read/Write
: Reset value
0
1
Receive overrun bit 0 (Message buffer 0)
Not overrun error occurs
Overrun error occurs
Receive overrun bit 1(messag buffer1)
Not overrun error occurs
Overrun error occurs
Receive overrun bit 2 (messag buffer2)
Not overrun error occurs
Overrun error occurs
Receiv overrun bit 3 (messag buffer 3)
Not overrun error occurs
Overrun error occurs
Receiv overrun bit 4 (messag buffer 4)
Not overrun error occurs
Overrun error occurs
Receiv overrun bit 5 (messag buffer 5)
Not overrun error occrs
Overrun error occurs
Receiv overrun bit 6 (messag buffer 6)
Not overrun error occrs
Overrun error occrs
Receiv overrun bit 7 (messag buffer 7)
Not overrun error occrs
Overrun error occrs
519
CHAPTER 16 CAN CONTROLLER
Table 16.3-18 Functions of Reception Overrun Register (ROVRR)
Bit name
bit7
to
bit0
520
ROVR7 to 0:
Reception overrun bit 7
to 0
Function
These bits indicate that an overrun occurs at storing the received
message in the message buffer that had completed receiving.
At overrun: "1" is set to the ROVRx bit corresponding to the
message buffer (x) where an overrun occurs.
When set to "0": Cleared when 0 is set to after reception
overrun occurred.
When set to "1": No effect
Read using read modify write instructions: "1" always read
• Setting the ROVRx bit when an overrun occurs (ROVRx =
1) overrides clearing of the ROVRx bit when 0 is written
(ROVRx = 0) if both occur at the same time.
CHAPTER 16 CAN CONTROLLER
16.3.17
Receive complete interrupt enable register (RIER)
The reception complete interrupt enable register (RIER) enables or disables a reception
complete interrupt for each message buffer.
■ Receive complete interrupt enable register (RIER)
Figure 16.3-25 Receive complete interrupt enable register (RIER)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit0
RIE0
0
1
bit1
RIE1
0
1
bit2
RIE2
0
1
bit3
RIE3
0
1
bit4
RIE4
0
1
bit5
RIE5
0
1
bit6
RIE6
0
1
bit7
RIE7
R/W
: Read/Write
: Reset value
0
1
Reception interrupt enable bit 0 (Message buffer 0)
Disable reception compiete interrupt
Enables reception complete interrupt
Reception interrupt enable bit 1 (Message buffer 1)
Disable reception complete interrupt
Enables reception complete interrupt
Reception interrupt enable bit 2 (Message buffer 2)
Disable reception complete interrupt
Enables reception complete interrupt
Reception interrupt enable bit 3 (Message buffer 3)
Disable reception complete interrupt
Enables reception complete interrupt
Reception interrupt enable bit 4 (Message buffer 4)
Disable reception complete interrupt
Enables reception complete interrupt
Reception interrupt enable bit 5 (Message buffer 5)
Disable reception complete interrupt
Enables reception complete interrupt
Reception interrupt enable bit 6 (Message buffer 6)
Disable reception complete interrupt
Enables reception complete interrupt
Reception interrupt enable bit 7 (Message buffer 7)
Disable reception complete interrupt
Enables reception complete interrupt
521
CHAPTER 16 CAN CONTROLLER
Table 16.3-19 Functions of Reception Complete Interrupt Enable Register (RIER)
Bit name
bit7
to
bit0
522
RIE7 to 0:
Reception complete
interrupt enable bits 7 to 0
Function
These bits enable or disable a reception complete interrupt for
the message buffer (x).
When set to "0": Disables reception complete interrupt for
message buffer (x)
When set to "1": Enables reception complete interrupt for
message buffer (x)
CHAPTER 16 CAN CONTROLLER
16.3.18
Acceptance mask select register (AMSR)
The acceptance mask select register (AMSR) selects the mask (acceptance mask)
format for comparison between the identifier (ID) of the received message and the
message buffer.
■ Acceptance mask select register (AMSR)
Figure 16.3-26 Acceptance mask select register (AMSR)
bit15
14
13
12
11
10
9
8
AMS7.1 AMS7.0 AMS6.1 AMS6.0 AMS5.1 AMS5.0 AMS4.1 AMS4.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
AMS3.1 AMS3.0 AMS2.1 AMS2.0 AMS1.1 AMS1.0 AMS0.1 AMS0.0
R/W
R/W
AMSx.1
0
0
1
1
R/W
AMSx.0
0
1
0
1
R/W
R/W
R/W
R/W
Reset value
XXXXXXXXB
Reset value
XXXXXXXXB
R/W
Acceptance mask select bits (x=7 to 0)
Full-bit comparison is performed.
Full-bit masking is performed.
Uses Acceptance mask Register 0 (AMR0)
Uses Acceptance mask Register 1 (AMR1)
Message buffer (x) number x(7 to 0).
X
: Undefined
R/W : Read/Write
523
CHAPTER 16 CAN CONTROLLER
Table 16.3-20 Functions of Acceptance Mask Select Register (AMSR)
Bit name
bit15
:
:
:
:
bit0
524
Acceptance mask select
bits 7.0 to 0.0, 7.1 to 0.0
ASM7.0 to 0.0, 7.1 to
0.1:
Function
These bits select the mask (acceptance mask) format for
comparison between the received message ID and message
buffer ID (IDR) for the message buffer (x). No comparison with
masked bits is made.
Full-bit comparison: All bits are compared in collating the
setting values of the ID register (IDR)
with the received message ID.
Full-bit masking: All bits for the setting values of the ID
register (IDR) and the received message ID
are masked.
Using acceptance mask register 0 (or 1): The acceptance mask
register 0 or 1 (AMR0 or AMR1) is used as an acceptance mask
filter.At collating the setting values of the ID register (IDR) with the
received message ID, only the bits set to "0" and corresponding to
the AMx bit in the acceptance mask register are compared and
the bits set to "1" and corresponding to the AMx bit are masked.
• If the AMSx.1 and AMSx.0 bits are set to "10 B" or "11 B",
always set the acceptance mask register (AMR0 or AMR1)
to be used, too.
Note:
• The acceptance mask select register (AMSR) should be set
after disabling the message buffer (x) to be set (BVALR:
BVALx = 0). Setting the acceptance mask select register
(AMSR) with the message buffer (x) enabled may store a
message unnecessary received.
CHAPTER 16 CAN CONTROLLER
16.3.19
Acceptance Mask Select Register (AMR)
The CAN controller contains two acceptance mask registers (AMR0 and AMR1), each of
which can be used in the standard frame format (ID11 bits, AM28 to AM18) and the
extended frame format (ID29 bits, AM28 to AM0).
■ Acceptance Mask Select Register (AMSR)
Figure 16.3-27 Acceptance Mask Select Register (AMSR)
BYTE0
BYTE1
BYTE2
BYTE3
R/W
X
-
bit7
6
5
4
3
2
1
0
AM28
AM27
AM26
AM25
AM24
AM23
AM22
AM21
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit15
14
13
12
11
10
9
8
AM20
AM19
AM18
AM17
AM16
AM15
AM14
AM13
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
6
5
4
3
2
1
0
AM12
AM11
AM10
AM9
AM8
AM7
AM6
AM5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
AM4
AM3
AM2
AM1
AM0
R/W
R/W
R/W
R/W
R/W
Reset value
XXXXXXXXB
Reset value
XXXXXXXXB
Reset value
XXXXXXXXB
Rsest value
XXXXXXXXB
-
-
-
: Read/Write
: Undefined
: Unused
: Standard frame format uses in bit
525
CHAPTER 16 CAN CONTROLLER
Table 16.3-21 Functions of Acceptance Mask Register (AMR)
Bit name
Note:
526
bit15:
:
:
bit11
AM4 to AM0:
Acceptance mask bit 4 to
0 (BYTE3)
bit15
:
:
:
bit8
AM20 to AM13:
Acceptance mask bit 20
to 13 (BYTE1)
bit7
:
:
:
bit0
AM12 to AM5:
Acceptance mask bit 12
to 5 (BYTE2)
bit7
:
:
:
bit0
AM28 to AM20:
Acceptance mask bit 28
to 21 (BYTE0)
Function
These bits set whether to compare or mask each bit at collating
the acceptance code set in the ID register (IDR: IDx) with the
received message ID.
• If the AMSx.1 or AMSx.0 bits of acceptance mask select
registers are set to "10B" or "11B", always set the acceptance
mask register (AMR0 or AMR1) to be used, too.
Standard frame format (IDER: IDEx = 0): 11 bits from AM28 to
AM18 are used.
Extended frame format (IDER: IDEx = 1):
29 bits from AM28 to AM0 are used.
When AMx bit set to "0" (compare):
The bits corresponding to the AMx bit set to "0" are
compared at collating the acceptance code set in the ID
register (IDR: IDx) with the received message ID.
When AMx bit set to "1" (mask):
The bits corresponding to the AMx bit set to "1" are
masked at collating the acceptance code set in the ID
register (IDR: IDx) with the received message ID.
Note:
• The acceptance mask select register (AMSR) should be set
after disabling the message buffer (x) to be set (BVALR:
BVALx = 0). Setting the acceptance mask select register
(AMSR) with the message buffer (x) enabled may store a
message unnecessary received.
To invalidate the message buffer (BVALR: BVAL = 0) with the CAN controller
participating in CAN communication (the read value of the CSR: HALT bit is 0 and
the CAN controller participating in CAN bus communication is ready to receive and
transmit messages), follow the cautions in Section 16.6 "Precautions when Using
CAN Controller".
CHAPTER 16 CAN CONTROLLER
16.3.20
Message Buffers
The message buffers consist of ID register, DLC register, and data register and are used
for transmission/reception of messages.
■ Message Buffers
• There are 8 message buffers.
• One message buffer x (x = 0 to 7) consists of the ID register (IDRx), DLC register (DLCRx), and data
register (DTRx).
• The message buffer (x) is used to transmit and receive messages.
• Higher priority is given to smaller number message buffer.
- At transmission, if a transmit request is generated to more than one message buffer, transmission is
started with the message buffer with the smallest number.
- At receiving, if the received message ID passes the acceptance filter (which compares received
message ID with message buffer ID after acceptance masking) set in more than one message buffer,
the received message is stored in the message buffer with the smallest number.
• If the same acceptance filter is set in more than one message buffer, it can be used as multiple message
buffers.This provides sufficient time to perform receiving.
Notes:
• Write by words to the message buffer area and general-purpose RAM area. At
writing by bytes, undefined data is written to the upper bytes when writing to the
lower bytes is performed. Writing to the upper bytes is ignored.
• The message buffer (x) area disabled by the message buffer enable register
(BVALR: BVALx = 0) can be used as a general-purpose RAM area. However, during transmitting or receiving, it may take up to 64 machine cycles to access the
message buffer area and general - purpose RAM area.
Reference:
• For details on transmission, see "16.5.1 Transmission".
• For details on reception, see "16.5.2 Reception".
• See "16.5.4 Setting Multiple Message Receiving" for details of the configuration of
the multiple message buffer.
527
CHAPTER 16 CAN CONTROLLER
16.3.21
ID Register (IDRx, x = 7 to 0)
The ID register (IDR) sets the ID of the message buffer used for transmitting and
receiving.In the standard frame format 11 bits from ID28 to ID18 are used, and in the
extended frame format 29 bits from ID28 to ID0 are used.
■ ID Register (IDR)
Figure 16.3-28 ID Register (IDR)
BYTE0
BYTE1
BYTE2
BYTE3
bit7
6
5
4
3
2
1
0
ID28
ID27
ID26
ID25
ID24
ID23
ID22
ID21
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
ID20
ID19
ID18
ID17
ID16
ID15
ID14
ID13
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
ID12
ID11
ID10
ID9
ID8
ID7
ID6
ID5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit15
14
13
12
11
10
9
8
ID4
ID3
ID2
ID1
ID0
R/W
R/W
R/W
R/W
R/W
R/W : Read/Write
X
: Undefined
: Unused
: Standard frame format uses in bit
528
Reset value
XXXXXXXXB
Reset value
XXXXXXXXB
Rsest value
XXXXXXXXB
Reset value
XXXXXXXXB
-
-
-
CHAPTER 16 CAN CONTROLLER
Table 16.3-22 Functions of ID Register (IDR)
Bit name
bit15
:
:
:
bit11
ID4 to 0:
ID bit 4 to 0 (BYTE3)
bit15
:
:
:
bit8
ID20 to 13:
ID bit 20 to 13 (BYTE1)
bit7
:
:
:
bit0
ID12 to 5:
ID bit 28 to 21 (BYTE2)
bit7
:
:
:
bit0
ID28 to 21:
ID bit 28 to 21(BYTE0)
Function
These bits set the acceptance code or transmit message ID to be
collated with the received message ID.
Standard frame format (IDER: IDEx = 0):
11 bits from ID28 to ID18 are used.
• The old messages left in the receive shift register are stored
in ID17 to ID0. This will not affect the operation.
• All received message IDs are stored even if specific bits are
masked.
Extended frame format (IDER: IDEx = 1):
29 bits from ID28 to ID0 are used.
Note:
• When using the standard frame format (IDER: IDEx = 0),
the bits from ID28 to ID22 cannot be all set to "1".
• When setting the ID register (IDR), perform writing by
words. Writing by bytes is disabled.
529
CHAPTER 16 CAN CONTROLLER
● Setting example of ID register (IDR)
Table 16.3-23 gives a setting example of the ID register (IDR) in the standard and extended frame formats.
Table 16.3-23 Example of ID Setting in Standard and Extended Frame Formats
Standard frame format
ID (Hex) BYTE0
1
00
2
00
3
00
4
00
5
00
6
00
7
00
8
01
9
01
A
01
BYTE1
20
40
60
80
A0
C0
E0
00
20
40
30
31
32
1E
1F
20
03
03
04
C0
E0
00
30
31
32
1E
1F
20
00
00
00
100
101
64
65
0C
0C
80
A0
100
101
64
65
200
C8
19
00
200
2043
2044
2045
2046
2047
7FB
7FC
7FD
7FE
7FF
FF
FF
FF
FF
FF
60
80
A0
C0
E0
ID (Dec)
1
2
3
4
5
6
7
8
9
10
530
Extended frame format
ID (Hex) BYTE0 BYTE1
00
00
1
00
00
2
00
00
3
00
00
4
00
00
5
00
00
6
00
00
7
00
00
8
00
00
9
00
00
A
BYTE2
00
00
00
00
00
00
00
00
00
00
BYTE3
08
10
18
20
28
30
38
40
48
50
00
00
00
00
00
01
F0
F8
00
00
00
00
00
03
03
20
28
C8
00
00
06
40
2043
2044
2045
2046
2047
7FB
7FC
7FD
7FE
7FF
00
00
00
00
00
00
00
00
00
00
3F
3F
3F
3F
3F
D8
E0
E8
F0
F8
8190
8191
8192
1FFE
1FFF
2000
00
00
00
00
00
01
FF
FF
00
F0
F8
00
536870905
536870906
536870907
536870908
536870909
536870910
536870911
1FFFFFF9
1FFFFFFA
1FFFFFFB
1FFFFFFC
1FFFFFFD
1FFFFFFE
1FFFFFFF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
FC
FD
FD
FE
FE
FF
FF
80
00
80
00
80
00
80
ID (Dec)
1
2
3
4
5
6
7
8
9
10
CHAPTER 16 CAN CONTROLLER
16.3.22
DLC Register (DLCR)
DLC register (DLCR) for message buffer. The DLC register (DLCR) sets the data length
of the message to be transmitted or received.
■ DLC Register (DLCR)
Figure 16.3-29 DLC Register (DLCR)
bit7
-
bit6
-
bit5
-
bit4
-
bit3
bit2
bit1
bit0
DLC3
DLC2
DLC1
DLC0
R/W
R/W
R/W
R/W
Reset value
XXXXXXXXB
R/W : Read/Write
X
: Undefined
: Unused
Table 16.3-24 Functions of DLC Register (DLCR)
Bit name
bit3
to
bit0
DLC3 to 0:
Data length setting bits
Function
These bits set the data length (byte count) of the message to be
transmitted or received.
When data frame transmitted:
The data length (byte count) of the transmit message is set.
When remote frame transmitted:
The data length (byte count) of the request message is set.
When data frame received:
The data length (byte count) of the received message is
stored.
When remote frame received:
The data length (byte count) of the request message is
stored.
Note:
• The data length should be set within the range of 0 to 8 bytes.
• When setting the DLC register (DLCR), write by words.
Writing by bytes is disabled.
531
CHAPTER 16 CAN CONTROLLER
16.3.23
Data Register (DTR)
Data register (DTR) for message buffer. The data register (DTR) sets the messages at
transmitting or receiving a data frame.The data length can be set from 0 to 8 bytes.
■ Data Register (DTR)
Figure 16.3-30 Data Register (DTR)
BYTE0
BYTE7
bit7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit15
14
13
12
11
10
9
8
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
XXXXXXXXB
Reset value
XXXXXXXXB
X
:Undefined
R/W :Read/Write
Table 16.3-25 Functions of Data Register (DTR)
Bit name
bit15
:
:
:
bit0
532
D7 to 0 (BYTE7 to 0) :
Data bit 7 to 0
Function
•
The data register (DTRx) is used only for transmitting or
receiving a data frame.
• The transmit message is set up to 8 bytes. The received message is stored on an MSB-first basis starting with the small
message buffer number (BYTE0 to BYTE7).
• The received message is stored. The received message is
stored on an MSB-first basis starting with the small message
buffer number (BYTE0 to BYTE7).
• If the received message is less than 8 bytes, undefined data is
stored in the rest of the bytes of the data register (DTRx).
However this does not affect the operation.
Note:
When setting the data register (DTR), write by words.
Writing by bytes is disabled.
CHAPTER 16 CAN CONTROLLER
16.4
Interrupts of CAN Controller
The CAN controller has a transmit complete interrupt, receive complete interrupt and
node state transition interrupt, and can generate interrupts when;
• The transmission complete bit (TCR: TCx) is set.
• The reception complete bit (RCR: RCx) is set.
• The node status transition flag (CSR: NT) is set.
■ Interrupts of CAN Controller
Table 16.4-1 shows the interrupt control bits and interrupt factors of the CAN controller.
Table 16.4-1 Interrupt Control Bits and Interrupt Factors of CAN Controller
Transmission/
Reception
Interrupt flag bit
Interrupt
factor
Interrupt enable bit
Clear of the interrupt-request flag
Transmission
Transmission
complete bit TCR:
TCx=1
Message
transmitting
complete
Transmission complete
interrupt enable bit
TIER: TIEx=1
Transmission request bit
Set TREQR: TREQx=1
Writing 0 to transmission complete bit (TCR:
TCx)
Reception
Reception
complete bitRCR:
RCx=1
Message
receiving
complete
Reception complete
interrupt enable bit
RIER: RIEx=1
Writing 0 to reception complete bit (RCR: RCx)
Transmission
Node status
transition flag bit
CSR: NT=1
Node status
transition
Node status transition
interrupt enable bit
CSR: NIE=1
Writing 0 to node status transition flag (CSR: NT)
● Transmission complete interrupt
When message transmission is completed, 1 is set to the TCx bit in the transmission complete register
(TCR).When a transmission complete interrupt is enabled (TIER: TIEx = 1) and when TCx = 1, a
transmission complete interrupt is generated.When a transmission request to the message buffer is set
(TREQR: TREQx = 1), the TCx bit in the transmission complete register (TCR) is automatically cleared to
"0".When "0" is written to the TCx bit in the transmission complete register (TCR) after the completion of
message transmitting (TCR: TCx = 1), the TCx bit is cleared.
● Reception complete interrupt
When message reception is completed, "1" is set to the RCx bit in the receive complete register
(RCR).When a reception complete interrupt is enabled (RIER: RIEx = 1) and when RCx = 1, a reception
complete interrupt is generated.When "0" is written to the RCx bit in the reception complete register (RCR)
after the completion of message receiving (RCR: RCx = 1), the RCx bit is cleared.
533
CHAPTER 16 CAN CONTROLLER
● Node status transition interrupt
When the node status of the CAN controller changes, "1" is set to the NT bit in the control status register
(CSR).If a node status transition interrupt is enabled (CSR: NIE = 1) when NT = 1, a node status transition
interrupt is generated.When "0" is written to the NT bit in the control status register, the NT bit is cleared.
■ Registers and Vector Tables Related to Interrupt of CAN Controller
Reference:
534
For details on interrupts, see "3.5 Interrupt".
CHAPTER 16 CAN CONTROLLER
16.5
Explanation of Operation of CAN Controller
This section explains the procedures for transmitting and receiving messages and the
setting of bit timing, frame format, ID and acceptance filter.
■ Explanation of Operation of CAN Controller
The following sections provide more details of the operation of CAN controller.
• Transmission of messages (See "Section 16.5.1 Transmission")
• Reception of messages (See "Section 16.5.2 Reception")
• Procedures for transmission/reception of messages (See "Section 16.5.3 Procedures for Transmitting and
Receiving")
• Reception of multiple messages (See "Section 16.5.4 Setting Multiple Message Receiving")
535
CHAPTER 16 CAN CONTROLLER
16.5.1
Transmission
Figure 16.5-1 shows a transmission flowchart.
■ Transmission procedure
Figure 16.5-1 Transmission Flowchart
Set transmission request register
(TREQR:TREQx=1)
Clear transmission completio register
(TCR:TCx=0)
NO:0
Set transmission request?
(TREQR:TREQx)
YES:1
NO:0
Remote frame reception waiting?
(RFWTR:RFWTx)
YES:1
NO:0
Remote frame reception?
(RRTRR:RRTRx)
YES:1
If there remains message buffer meeting
transmission conditions, the lowest-numbered
message buffer is selected.
NO
Bus idle state?
YES
TRTRx=0
TRTRx=1
How is fram setting?
(TRTRR:TRTRx)
Transmit data frame
Tranmit remote frame
Transmission seccessed?
NO
YES
Cancel transmission?
(TCANR:TCANx)
Transmission request register is cleared (TREQR:TREQx=0)
Reception RTR register is cleared (RRTRR:RRTRx=0)
Transmission complete register is set (TCR:TCx=1)
NO:0
YES:1
Clear transmission request register
(TREQR:TREQx=0)
Transmission complete interrupt enabled ?
YES:1
(TIER:TIEx=1)
NO:0
Transmission complete interrupt
request is output
Transmission operating finish
536
CHAPTER 16 CAN CONTROLLER
● Starting transmission
Setting of transmission request
To start transmitting, set the TREQx bit in the transmission request register to "1" which corresponding
to the message buffer (x) that transmits the message.When the TREQx bit is set, the transmission
complete register is cleared (TCR: TCx = 0).
Presence or absence of remote frame receive wait
If the RFWTx bit in the remote frame receive wait register is set, transmitting is started after a remote
frame is received (RRTRR: RRTRx = 1).If the remote frame receive wait register does not wait for
receiving of a remote frame (RFWTR: RFWTx = 0), transmitting is started immediately after the
transmission request bit is set (TREQR: TREQx = 1).
● Transmission operation
Transmission request set in more than one message buffer
When a transmission request is set in more than one message buffer (TREQR: TREQx = 1),
transmitting is performed starting with the small-numbered message buffer (x = 7 to 0).
Transmitting to CAN bus
Transmitting message to the CAN bus from the transmit output pin (TX) is started when the CAN bus is
idle.
Arbitration
Arbitration is performed when the CAN controller causes contention for a message buffer with another
transmitting CAN controller on the CAN bus.If arbitration fails or an error occurs during transmitting,
retransmitting is performed automatically until it succeeds after waiting until the bus goes idle again.
Selection of frame format
When "0" is set to the TRTRx bit in the transmit RTR register, a data frame is transmitted.When "1" is
set to the bit, a remote frame is transmitted.
● Canceling transmit request
Cancellation by transmission cancel register (TCANR)
During message transmission, the transmission request set in the message buffer that is not transmitted
(held) can be cancelled by setting "1" in the transmission cancel register (TCANR).
When the transmission request is completely cancelled (TCANR: TCANx = 1), the transmission request
register is cleared (TREQx = 1).
Cancellation by receiving message
The message buffer can receive the message even during requesting a transmission. However, the
transmission request is cancelled under the following conditions:
Request to transmit data frame:
When a data frame is received, the transmission request is cancelled.When a remote frame is received,
the transmission request is not cancelled.
Request to transmit remote frame:
The transmission request is cancelled even if either a data frame or remote frame is received.
537
CHAPTER 16 CAN CONTROLLER
● Completing transmission
Success of transmission
When transmission is terminated normally, the TCx bit in the transmission complete register is set.The
transmission request register and receive RTR register (TREQR: TREQx = 0, RRTRR: RRTRx = 0) are
cleared.
Generation of transmission interrupt
When the TIEx bit in the transmission complete interrupt enable register is set, an interrupt request is
generated when transmitting is completed (TCR: TCx = 1).
538
CHAPTER 16 CAN CONTROLLER
16.5.2
Reception
Figure 16.5-2 shows a reception flowchart.
■ Reception procedure
Figure 16.5-2 Reception Flowchart
Detecting start of frame (SOF) in
data frame or remote frame
With message buffer (X) through
acceptance filt?
NO
YES
Reception successed?
NO
YES
Determining message buffer (X)
storing receives message
Storing received message in
message buffer (X)
Reception complete register
set ? (RCR:RCx)
Received overrun generating
(ROVRR:ROVRx=1)
NO:0
Data frame
YES:1
Receiveing message ?
Remote frame
Setting received RTR register
(RRTRR:RRTRx=1)
Clear received RTR register
(RRTRR:RRTRx=0)
TRTRx=1
Transmission request of remote
frame ? (TRTRR:TRTRx)
Clear transmission request
register (TREQR:TREQx=0)
TRTRx=0
Setting reception completion
register (RCR:RCx=1)
Reception complete interrupt
enabled ? (RIER:RIEx=1)
YES:1
When reception completion,
output interrupt request
NO:0
Reception operating finish
539
CHAPTER 16 CAN CONTROLLER
● Starting reception
Reception is started when the start-of-frame (SOF) of a data frame or remote frame is detected on the CAN
bus.
● Acceptance filter
The received message in the standard frame format is compared with the message buffer (x) set in the
standard frame format (IDER: IDEx = 0).The received message in the extended frame format is compared
with the message buffer (x) set in the extended frame format (IDER: IDEx = 1).
Passing through the acceptance filter
If all bits set to compare in the acceptance mask are matched after "comparison" between the received
message ID and acceptance code (IDR: IDx), the received message passes the acceptance filter in the
message buffer (x).
● Storing received message
If message reception is successful, the received message is stored in the message buffer (x) that has the ID
that had passed the acceptance filter.
Data frame received
The received message is stored in the ID register (IDR) and DLC register (DLCR), data register
(DTR).If the received message is less than 8 bytes, undefined data is stored in the rest of the bytes in the
data register (DTR).
Remote frame received
The received message is stored in the ID register (IDR) and DLC register (DLCR).The data register
(DTR) remains unchanged.
More than one message buffer
If there is more than one message buffer with the ID that had passed the acceptance filter, the message
buffer (x) where the received message is stored is determined under the following conditions:
• Higher priority is given to the message buffer with a smaller number (x = 0 to 7).The priority of
message buffer 0 is the highest and 7 is the lowest.
• The received message is stored in preference to the message buffer that has not been completed
receiving (RCR: RCx = 0).
• If the bit in the acceptance mask select register is set to "full-bit comparison" (AMSx.1, AMSx.0 = 00B),
the received message is stored in the corresponding message buffer (x), regardless of the setting value of
the reception complete register (RCR: RCx).
• If there is more than one message buffer that has not been completed receiving, or if there is more than
one message buffer with the AMSx.1 and AMSx.0 bits in the acceptance mask select register set to "00 B"
(full-bit comparison), the received message is stored in the message buffer with the smallest number (x).
• If there is no message buffer that satisfies the above conditions, the received message is stored in the
message buffer with the lowest number (x).
540
CHAPTER 16 CAN CONTROLLER
• The message buffers should be arranged in order of ascending number (x) as follows;
- Smallest number (x): Acceptance mask set to full-bit comparison
- Middle number (x): Acceptance mask registers 0 and 1 used
- Largest number (x): Acceptance mask set to "full-bit masking"
● setting acceptance mask select register
Table 16.5-1 Setting acceptance mask select register
AMSx.1
AMSx.0
Acceptance mask (x=7 to 0)
0
0
Full-bit comparison is performed.
0
1
Full-bit masking is performed.
1
0
Using acceptance mask register 0 (AMR0)
1
1
Using acceptance mask register 1 (AMR1)
Figure 16.5-3 Flowchart of Determining Message Buffer that Stores Received Message
Start
Message is not received (RCR : RCx=0),
or any message buffer set to "full-bit comparison"
(AMSR : AMSx.1=0, AMSx.0=0)?
NO
YES
Select the smallest-numbered message
buffer (X) from message buffers
corresponding to the above.
Select one of the smallest
message buffer number (X)
Finish
541
CHAPTER 16 CAN CONTROLLER
● Reception overrun
When another received message is stored in the message buffer that has completed receiving (RCR: RCx =
1), a reception overrun occurs.When a reception overrun occurs, "1" is set to the ROVRx bit in the
reception overrun register corresponding to the number of the message buffer (x) where the reception
overrun occurs.
● Processing for reception of data frame and remote frame
Processing for reception of data frame
• The reception RTR register is cleared (RRTRR: RRTRx = 0).
• The transmission request register is cleared (TREQR: TREQx = 0) immediately before the received
message is stored.A transmission request to the message buffer (x) that does not perform transmitting is
cancelled.
Note:
Either the request to transmit a data frame or a remote frame is cancelled.
Processing for reception of remote frame
• The reception RTR register is set (RRTRR: RRTRx = 1).
• If the transmission RTR register is set (TRTRR: TRTRx = 1), the transmission request register is cleared
(TREQx = 0).The request to transmit a remote frame to the message buffer (x) that does not perform
transmitting is cancelled.
Note:
The request to transmit a data frame is not cancelled.
For details about how to cancel a transmit request, see Canceling transmit request.
● Completing receiving
When the received message is stored, the reception complete register is set.If the reception complete
interrupt enable register is set (RIER: RIEx = 1), an interrupt is generated when receiving is completed
(RCR: RCx = 1).
Note:
542
The CAN controller cannot receive any message transmitted by itself.
CHAPTER 16 CAN CONTROLLER
16.5.3
Procedures for Transmitting and Receiving
The section explains the procedure for transmission/reception of message.
■ Presetting
● Setting of bit timing
• Set the bit timing register (BTR) after halting the bus operation (CSR: HALT = 1).
● Setting of frame format
• Set the frame format used in the message buffer (x).When using the standard frame format, set the IDEx
bit in the IDE register (IDER) to "0". When using the extended frame format, set the IDEx bit to "1".
● Setting of ID
• Set the ID of the message buffer (x) to the ID28 to ID0 bits in the ID register (IDR).In the standard
frame format, it does not have to set the ID17 to ID0 bits.The ID of the message buffer (x) is used as the
transmit message ID at transmitting and as the acceptance code at receiving.
• Set the ID after disabling the message buffer (x) (BVALR: BVALx = 0).Setting the ID with the message
buffer (x) enabled may store a message unnecessary received.
● Setting of acceptance filter
• The acceptance filter used in the message buffer (x) is set by a combination of the acceptance code and
acceptance mask.Set the acceptance filter after disabling the message buffer (x) (BVALR: BVALx =
0).Setting the ID with the message buffer (x) enabled may store a message unnecessary received.
• The acceptance filter used for each message buffer (x) is selected by the acceptance mask select register
(AMSR).When using the acceptance mask registers (AMR0 and AMR1), set the acceptance mask
register (AMR0.1), too.
• Set the acceptance mask so that a transmission request will not be cancelled by storing an unnecessary
received message.
543
CHAPTER 16 CAN CONTROLLER
■ Procedure for Transmitting message Buffer (x)
Figure 16.5-4 shows a procedure for the transmit setting.
Figure 16.5-4 Flowchart of Procedure for Transmit Setting
START
Setting of bit timing
Setting of frame for mat
Setting of ID
Setting of acceptance filter
Bit timing register (BTR)
IDE register (IDER)
ID register (IDR)
Acceptance mask select register (AMSR)
Acceptance mask registers (AMR0,1)
Message buffer filter used selected
Message buffer validating register (BVALR)
Setting transmission complete interrupt
Transmit complete interrupt enable register (TIER)
Data frame
Remote frame
Selection of frame type
Setting offrame type
Transmit RTR register (TRTRx=0)
Setting of frame type
Transmit RTR register (TRTRx=1)
Setting transmit data length
Setting request data length
DLC register (DLCR)
DLC register (DLCR)
data register in transmission data stored
Data register (DTR)
Remote frame receive
wait
YES
NO
Remote frame receive wait
RFWTx=0
Remote frame receive wait
RFWTx=1
Canceling bus halt HALT=1
Transmission message
Setting the request to transmit a data frame
Transmitting a data frame (TREQR)
Remote frame receiving wait
Communication error
Success of transmitting?
TCx
NO : 0
Transmit cancel?
NO
YES
YES : 1
Transmission request cancel
Transmit cancel register (TCANR)
TREQx
0
1
TCx
0
Transmission complete
END
544
Transmission cancel
1
CHAPTER 16 CAN CONTROLLER
● Procedure for Transmitting message Buffer (x)
After completion of presetting, set the message buffer (x) enabled (BVALR: BVALx =1) by message
buffer enable register.
● Setting transmit data length code
• Set the transmit data length code (byte count) to the DLC3 to DLC0 bits in the DLC register (DLCR).
• When transmitting a data frame (TRTRR: TRTRx = 0), set the data length of the transmit message.
• When transmitting a remote frame (TRTRR: TRTRx = 1), set the data length (byte count) of the
message to be requested.
Note:
Setting other than 0000B to 1000B (0 to 8 bytes) is prohibited.
● Setting transmit data (only for transmission of data frame)
When transmitting a data frame (TRTRR: TRTRx = 0), set the data of byte count to be transmitted in the
data register (DTR).
Note:
Rewrite transmit data after setting the TREQx bit in the transmit request register to 0.
There is no need to set the bit disabled in the message buffer enable register
(BVALR: BVALx = 0). When the bit is set to disabled, no remote frame can be
received.
● Transmit RTR register (TRTRR)]
• When transmitting a data frame, set the TRTRx bit in the transmission RTR register to "0".
• When transmitting a remote frame, set the TRTRx bit in the transmission RTR register to "1".
● Setting conditions for starting transmitting (only in transmitting data frame)
• When setting the request to transmit a data frame (TREQR: TREQx = 1 and TRTRR: TRTRx = 0) and
starting transmission immediately, set the RFWTx bit in the remote frame wait register to "0".
• When setting the request to transmit a data frame (TREQR: TREQx = 1 and TRTRR: TRTRx = 0) and
starting transmission after waiting until a remote frame is received (RRTRR: RRTRx = 1), set the
RFWTx bit in the remote frame wait register to "1".
Note:
When the RFWTx bit in the remote frame wait register is set to "1", no remote frame
can be transmitted.
● Setting transmission complete interrupt
• When enabling an interrupt when transmission is completed (TCR: TCx = 1), set the TIEx bit in the
transmit complete enable register to "1".
• When disabling an interrupt when transmission is completed (TCR: TCx = 1), set the TIEx bit in the
transmission complete enable register to "0".
● Canceling bus halt
After the completion of setting bit timing and transmission, write "0" to the HALT bit in the control status
register (CSR: HALT) to cancel the bus halt.
545
CHAPTER 16 CAN CONTROLLER
● Setting of transmission request
To set a transmission request, set the TREQx bit in the transmission request register to "1".
● Canceling transmission request
• To cancel the transmission request held in the message buffer (x), write "1" to the TCANx bit in the
transmission cancel register.
• When the TREQx bit is "0", transmission cancel is terminated or transmission is completed.After that,
check the TCx bit in the transmission complete register (TCR). If the TCx bit is "0", transmission cancel
is terminated and if the TCx bit is "1", transmission is completed.
● Processing when transmission completed
• When transmission is successful, "1" is set to the TCx bit in the transmit complete register (TCR).
• When a transmission complete interrupt is enabled (TIER: TIEx = 1), an interrupt is generated.
• After checking the completion of transmission, write "0" to the TCx bit in the transmission complete
register (TCR) to clear the transmission complete register (TCR).When the transmission complete
register (TCR) is cleared, the transmission complete interrupt is cancelled.
• When the message is received or stored, the held transmission requests are cancelled as follows:
- When a data frame is received, the request to transmit a data frame is cancelled.
- When a data frame is received, the request to transmit a remote frame is cancelled.
- When a remote frame is received, the request to transmit a remote frame is cancelled.
When a remote frame is received or stored, the request to transmit a data frame is not cancelled but the data
in the ID register and DLC register are rewritten to the data of the received remote frame.Therefore, the
data in the ID register and DLC register for the data frame to be transmitted are replaced by data in the
received remote frame.
546
CHAPTER 16 CAN CONTROLLER
■ Procedure for Receiving Message Buffer (x)
Figure 16.5-5 shows the procedure for the receiving setting.
Figure 16.5-5 Flowchart of Procedure for Receive Setting
START
Setting of bit timing
Setting of frame for mat
Setting of ID
Setting of acceptance filter
Bit timing register (BTR)
IDE register (IDER)
ID register (IDR)
Acceptance mask select register (AMSR)
Acceptance mask registers (AMR0,1)
Using Message Buffre select
Message buffer validating register (BVALR)
Setting reception complete interrupt
Receive complete interrupt enable register (RIER)
Canceling bus halt HALT=1
NO
If received message
RCx=1 ?
YES
Receive bytes count read
Reception overrun bits cleared
ROVRx=0
Processing message stored
(processing receiving completed interrupt)
Received message is read
Receive overrun?
ROVRx=0 ?
NO
YES
Reception complete bits cleared
RCx=0
END
● Procedure for Receiving Message Buffer (x)
After presetting, perform the following setting:
● Setting reception complete interrupt
• To generate a reception complete interrupt, set the RIEx bit in the reception complete interrupt enable
register (RIER) to "1".
• To disable a reception complete interrupt (RCR: RCx = 1), set the RIEx bit to "0".
547
CHAPTER 16 CAN CONTROLLER
● Starting receiving
To start receiving after the completion of setting, set the BVALx bit in the message buffer enable register
(BVALR) to "1" and enable the message buffer (x).
● Canceling bus halt
After the completion of setting bit timing and transmission, write "0" to the HALT bit in the control status
register (CSR: HALT) to cancel the bus halt.
● Processing when receiving completed
• If reception is successful after passing through the acceptance filter, the received message is stored in
the message buffer (x), "1" is set to the RCx of the reception complete register (RCR). For data frame
reception, RRTRx bit of the remote request receive register (RRTRR) is cleared to "0".For remote frame
reception, "1" is set to the RRTRx bit.
• If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is "1"), an
interrupt is generated.
• Process the received message after checking the completion of receiving (RCR: RCx = 1).
• Check the ROVRx bit in the receive overrun register (ROVRR) after the completion of processing the
received message.
- If the ROVRx bit is set to "0", the received message is enabled.When "0" is written to the RCx bit (a
reception complete interrupt is also cancelled), receiving is terminated.
- If the ROVRx bit is set to "1", a receive overrun occurs and the new message may overwrite the
received message.When a receive overrun occurs, write "0" to the ROVRx bit and then process the
received message again.
Above shows example of interrupt processing in the reception completion.
548
CHAPTER 16 CAN CONTROLLER
Figure 16.5-6 Example of Reception Interrupt Processing
RCx=1 at interrupt generation
Received message is
read
A:=ROVRx
ROVRx:=0
A=0?
NO
YES
RCx: 0
END
549
CHAPTER 16 CAN CONTROLLER
16.5.4
Setting Multiple Message Reception
• When there is insufficient time to receive messages such as frequently received
messages or messages with different IDs, more than one message buffer can be
combined to a multiple message buffer to give the CPU sufficient time to process
received messages.
• To configure multiple message buffers, perform the same setting of acceptance filter
of the message buffers to be combined.
■ Setting Configuration of Multiple Message Buffer
When four messages in the standard frame format are received with doing the acceptance filter of message
buffers 5, 6 and 7 on the same settings, the multiple message buffer operates as shown in the figure.
Note:
550
When the acceptance mask select register is set to full - bit comparison (AMSR:
AMSx.1, AMSx.0 = 00B), do not set the same acceptance code. When the register is
set to full-bit comparison, the messages are always stored in the message buffer with
the smaller number, so the message buffers cannot be formed into a multiple message buffer.
CHAPTER 16 CAN CONTROLLER
Figure 16.5-7 Example of Operation of Multiple Message Buffer
Initialization
AMSR
AMS7
10
AMS6
10
AMS5
10
Acceptance
Maskregister choice
AMR0
AM28 to AM18
0000 1111 111
Message Buffers5
ID28 to ID18
0101 0000 000
IDE
0
Message Buffers6
0101 0000 000
0
Message Buffers7
0101 0000 000
IDER
IDE7 IDE6 IDE5
0
0
0
RCR
RC7
0
RC6
0
RC5
0
0
ROVR7
0
0
ROVRR
0
6
5
mask
Message receiving → Message Buffers 5 memory
ID28 to ID18
0101 1111 000
IDE
0
Message Buffers5
0101 1111 000
0
RCR
0
0
1
Message Buffers6
0101 0000 000
0
ROVRR
0
0
0
Message Buffers7
0101 0000 000
0
Reception message
Message receiving → Message Buffers 6 memory
ID28 to ID18
0101 1111 001
IDE
0
Message Buffers5
0101 1111 000
0
RCR
0
1
1
Message Buffers6
0101 1111 001
0
ROVRR
0
0
0
Message Buffers7
0101 0000 000
0
RCR
1
1
1
ROVRR
0
0
0
Reception message
Message receiving → Message Buffers 7 memory
Reception message
Message Buffers5
ID28 to ID18
0101 1111 010
IDE
0
0101 1111 000
0
Message Buffers6
0101 1111 001
0
Message Buffers7
0101 1111 010
0
Message receiving → Receive overrun (ROVR5 = 1)occurs,Message buffer 5 memory
ID28 to ID18
0101 1111 011
IDE
0
Message Buffers5
0101 1111 011
0
RCR
1
1
1
Message Buffers6
0101 1111 001
0
ROVRR
0
0
1
Message Buffers7
0101 1111 010
0
Reception message
551
CHAPTER 16 CAN CONTROLLER
16.6
Precautions when Using CAN Controller
Use of the CAN Controller requires the following cautions.
■ Caution for disabling message buffers by BVAL bits
The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set disabled
while CAN Controller is participating in CAN communication (the read value of the CSR: HALT bit is 0
and CAN Controller is ready to transmit messages). This section shows the work around of this
malfunction.
● Condition
When following two conditions occur at the same time, the CAN Controller will not perform to transmit
messages normally.
• CAN Controller is participating in the CAN communication. (i.e. The read value of the CSR: HALT bit
is 0 and CAN Controller is ready to transmit messages)
• Message buffers are read when BVAL bits disable the message buffers.
● Work around
Operation for suppressing transmission request
Do not use BVAL bit for suppressing transmission request, use TCAN bit instead of it.
Operation for composing transmission message
For composing a transmission message, it is necessary to disable the message buffer by BVAL bit to
change contents of ID and IDE registers. In this case, BVAL bit should reset (BVAL=0) after checking
if TREQ bit is 0 or after completion of the previous message transmission (TC=1).
In case a buffer needs to be disabled, ensure that no transmission request is pending (if it was requested
before)! Therefore, do not reset BVALx-Bit before testing, if a transmission is ongoing:
a) Cancel the transmission request (TCANx=1;), if necessary
b) Wait for the transmission completion (while (TREQx==1);) by polling or interrupt.
Only after that the transmission buffer can be disabled (BVALx=0;).
Note:
552
Note for case a), if transmission of that buffer has already started, canceling the
request is ignored and disabling the buffer is delayed until the end of the transmission.
CHAPTER 16 CAN CONTROLLER
16.7
Program Example of CAN Controller
This section shows the program example of CAN controller.
■ Program Example of CAN Transmission and Reception
● Processing specification
• Set buffer 5 of CAN to data frame transmit mode and buffer 0 to data frame receive mode.
• Setting of frame format: Standard frame format
• Setting of ID: Buffer 0 ID = 1, Buffer 5 ID = 5
• Baud rate: 100 Kbps (machine clock = 16 MHz)
• Acceptance mask selection: full-bit comparison
• After entering the bus mode (HALT = 0), data A0A0H is transmitted.
• A transmission request (TREQx=1) is made within the transmission complete interrupt routine to
transmit the same data.(When TREQx is set to start sending, the transmission complete interrupt bit is
cleared)
• The reception interrupt bit is cleared within the reception interrupt routine.
553
CHAPTER 16 CAN CONTROLLER
● Coding example
;//Data format ste (CAN resets)
MOVW BTR,#05CC7H
;Baud Rate set100Kbps
; (Machine clock=16MHz)
MOVW IDER,#0000H
;Setting of frame for mat
; (0:standard,1:extended)
MOVW IDR51,#0A000H ;Data frame 5 ID set (ID=5)
MOVW IDR01,#2000H ;Data frame 0 ID set (ID=1)
MOVW AMSR,#0000H ;Acceptance mask select register
; (Full-bit comparison)
MOVW BVALR,#21H
;Message Buffers 5,0 enable
;//Transmission set
MOVW DLCR5,#02H
;Transefer data Length set (00H:0 byte length,
;08H:8 byte length)
MOVW RFWTR,#0000H ; Remote frame receiv waiting register
MOVW TRTRR,#0000H ; Transmission RTR register (0: Transmitting a data frame
;,1: Transmitting a remote frame)
MOVW TIER,#0020H
; Transmit complete interrupt enable register
;// Receive Setting
MOVW RIER,#0001H
;Receive complete interrupt enable register
;//Bus opening
MOV CSR0,#80H
;Control status register (HALT=0)
sthlt BBS CSR0:0,sthlt
;HALT=0 wait
;//Transmit data set
MOVW DTR5,#0A0A0H ;Message buffer 5 data register
;A0A0H write
MOVW TREQR,#0020H ;Transmit request register (1:Starting transmitting,
;0:Stop transmitting)
;// Reception complete interrupt
CANRX
MOVW RCR,#0000H
RETI
;Receive complete register
;// Transmission complete interrupt
CANTX
MOVW TREQR,#0020H ;Transmit request register (1:Starting transmitting,
;0:Stop transmitting)
RETI
554
CHAPTER 17
ADDRESS MATCH
DETECTING FUNCTION
This chapter explains the address match detection
functions and its operation.
17.1 Overview of Address Match Detection Function
17.2 Block Diagram of Address Match Detection Function
17.3 Configuration of Address Match Detection Function
17.4 Explanation of Operation of Address Match Detection Function
17.5 Program Example of Address Match Detection Function
555
CHAPTER 17 ADDRESS MATCH DETECTING FUNCTION
17.1
Overview of Address Match Detection Function
If the address of the instruction to be processed next after the instruction currently
being processed by the program matches the address set in the detect address setting
registers, the address match detection function forcibly replaces the next instruction to
be INT9 instruction, and branches to interrupt processing program. Since the address
match detection function can use the INT9 interrupt for instruction processing, the
program can be corrected by patch processing.
■ Overview of Address Match Detection Function
• The address of the instruction to be processed next after the instruction currently processed by the
program is always held in the address latch through the internal bus.The address match detection
function always compares the value of the address held in the address latch with that of the address set
in the detect address setting registers. When these compared values match, the next instruction to be
processed by the CPU is forcibly replaced by the INT9 instruction, and the interrupt processing program
is executed.
• There are two detect address setting registers (PADR0 and PADR1), each of which has an interrupt
enable bit.The generation of an interrupt due to a match between the address held in the address latch
and the address set in the detect address setting registers can be enabled and disabled for each register.
556
CHAPTER 17 ADDRESS MATCH DETECTING FUNCTION
17.2
Block Diagram of Address Match Detection Function
The address match detection module consists of the following blocks:
• Address latch
• Address detection control register (PACSR)
• Detect address setting registers
■ Block Diagram of Address Match Detection Function
Figure 17.2-1 shows the block diagram of the address match detection function.
Figure 17.2-1 Block Diagram of Address Match Detection Function
Address latch
Detect address setting registers 0
PADR1 (24bit)
Comparator
Internal data bus.
PADR0 (24bit)
INT9 instruction
(INT9 interrupt generated)
Detect address setting registers 1
PACSR
Reserved Reserved Reserved Reserved AD1E Reserved AD0E Reserved
Address detection controlregister(PACSR)
Reserved : Always set this bit to 0.
● Address latch
The address latch stores the value of the address output to the internal data bus.
● Address detection control register (PACSR)
The address detection control register enables or disables output of an interrupt at an address match.
● Detect address setting registers (PADR0, PADR1)
The detect address setting registers set the address that is compared with the value of the address latch.
557
CHAPTER 17 ADDRESS MATCH DETECTING FUNCTION
17.3
Configuration of Address Match Detection Function
This section details the registers used by the address match detection function.
■ List of Registers and Reset Values of Address Match Detection Function
Figure 17.3-1 List of Registers and Reset Values of Address Match Detection Function
bit
Address detection control registes (PACSR)
bit
Detect address setting registers 0 (PADR0)
: High
bit
Detect address setting registers 0 (PADR0)
: Middle
bit
Detect address setting registers 0 (PADR0)
: Low
bit
Detect address setting registers 1 (PADR1)
: High
bit
Detect address setting registers 1 (PADR1)
:Middle
bit
Detect address setting registers 1 (PADR1)
:Low
× : Undefined
558
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
×
7
6
5
4
3
2
1
0
×
×
×
×
×
×
×
×
CHAPTER 17 ADDRESS MATCH DETECTING FUNCTION
17.3.1
Address detection control register (PACSR)
The address detection control register (PACSR) enables or disables output of an
interrupt at an address match.When an address match is detected when output of an
interrupt at an address match is enabled, the INT9 interrupt is generated.
■ Address detection control register (PACSR)
Figure 17.3-2 Address detection control register (PACSR)
7
6
5
4
3
2
1
0
Reset value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
bit0
Reserved
0
Reserved bit
Always set this bit to 0.
bit1
AD0E
0
1
Address match detection enable bit 0
Disables the address match PADR0
Enables the address match PADR0
bit2
Reserved bit
Reserved
Always set this bit to 0.
0
bit3
AD1E
0
1
Address match detection enable bit 1
Disables the address match PADR1
Enables the address match PADR1
bit4
Reserved
Reserved bit
0
Always set this bit to 0.
bit5
Reserved bit
Reserved
0
Always set this bit to 0.
bit6
Reserved bit
Reserved
0
Always set this bit to 0.
R/W : Read / Write
: Reset value
bit7
Reserved bit
Reserved
0
Always set this bit to 0.
559
CHAPTER 17 ADDRESS MATCH DETECTING FUNCTION
Table 17.3-1 Functions of Address Detection Control Register (PACSR)
bit name
560
Function
bit7
to
bit4
Reserved: reserved bit
Always set this bit to "0".
bit3
AD1E:
Address match detection
enable bit 1
The address match detection operation with the detect address
setting register 1 (PADR1) is enabled or disabled.
When set to "0": Disables the address match detection
operation.
When set to "1": Enables the address match detection
operation.
• When the value of detect address setting registers 1 (PADR1)
matches with the value of address latch at enabling the
address match detection operation (AD0E = 1), the INT9
instruction is immediately executed.
bit2
Reserved: reserved bit
Always set this bit to "0".
bit1
AD0E:
Address match detection
enable bit 0
The address match detection operation with the detect address
setting register 0 (PADR0) is enabled or disabled.
When set to "0": Disables the address match detection
operation.
When set to "1": Enables the address match detection
operation.
• When the value of detect address setting register 0 (PADR0)
matches with the value of address latch at enabling the
address match detect operation (AD0E = 1), the INT9
instruction is immediately executed.
bit0
Reserved: reserved bit
Always set this bit to "0".
CHAPTER 17 ADDRESS MATCH DETECTING FUNCTION
17.3.2
Detect address setting registers (PADR0, PADR1)
The value of an address to be detected is set in the detect address setting
registers.When the address of the instruction processed by the program matches the
address set in the detect address setting registers, the next instruction is forcibly
replaced by the INT9 instruction, and the interrupt processing program is executed.
■ Detect address setting registers (PADR0, PADR1)
Figure 17.3-3 Detect address setting registers (PADR0, PADR1)
bit7
PADR0, PADR1 : High
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reset value
D23 D22
D21
D20 D19 D18
D17
D16
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
PADR0, PADR1 : Middle
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
D15 D14
D8
D13
D12 D11 D10
D9
Reset value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
PADR0, PADR1 : Low
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reset value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Read/Write
X
: Undefined
561
CHAPTER 17 ADDRESS MATCH DETECTING FUNCTION
■ Functions of Detect Address Setting Registers
• There are two detect address setting registers (PADR0 and PADR1) that consist of a high byte (bank),
middle byte, and low byte, totaling 24 bits.
Table 17.3-2 Address Setting of Detect Address Setting Registers
Register Name
Interrupt
Output Enable
Address Setting
High
Detect address setting
register 0 (PADR0)
Detect address setting
register 1 (PADR1)
PACSR: AD0E
PACSR: AD1E
Set the upper 8 bits of detect address 0 (bank).
Middle
Set the middle 8 bits of detect address 0.
Low
Set the lower 8 bits of detect address 0.
High
Set the upper 8 bits of detect address 1 (bank).
Middle
Set the middle 8 bits of detect address 1.
Low
Set the lower 8 bits of detect address 1.
• In the detect address setting registers (PADR0 and PADR1), starting address (first byte) of instruction to
be replaced by INT9 instruction should be set.
Figure 17.3-4 Setting of Starting Address of Instruction Code to be Replaced by INT9
Setting Detect Address(High : FFH, Middle : 00H, Low : 1FH)
Address Instruction Code
FF001C:
FF001F:
FF0022:
Notes:
562
A8 00 00
4A 00 00
4A 80 08
Mnemonic
MOVW
MOVW
MOVW
RW0,#0000
A,#0000
A,#0880
• When an address of other than the first byte is set to the detect address setting
register (PADR0 and PADR1), the instruction code is not replaced by INT9
instruction and a program of an interrupt processing is not be performed.When the
address is set to the second byte or subsequent, the address set by the instruction
code is replaced by "01" (INT9 instruction code) and, which may cause
malfunction.
• The detect address setting registers (PADR0 and PADR1) should be set after
disabling the address match detection (PACSR: AD0E = 0 or AD1E = 0) of
corresponding address match control registers.If the detect address setting
registers are changed without disabling the address match detection, the address
match detection function will work immediately after an address match occurs
during writing address, which may cause malfunction.
• The address match detection function can be used only for addresses of the
internal ROM area.If addresses of the external memory area are set, the address
match detection function will not work and the INT9 instruction will not be
executed.
CHAPTER 17 ADDRESS MATCH DETECTING FUNCTION
17.4
Explanation of Operation of Address Match Detection
Function
If the addresses of the instructions executed in the program match those set in the
detection address setting registers (PADR0 and PADR1), the address match detection
function will replace the first instruction with the INT9 instruction ("01H") and branch to
interrupt processing program.
■ Operation of Address Match Detection Function
Figure 17.4-1 shows the operation of the address match detection function when the detect addresses are set
and an address match is detected.
Figure 17.4-1 Operation of Address Match Detection Function
Program Execution
Address Instruction code
Instruction address
executed in program
matches with detection
address setting register 0.
FF001C:
FF001F:
FF0022:
A8 00 00
4A 00 00
4A 80 08
Mnemonic
MOVW
MOVW
MOVW
RW0,#0000
A,#0000
A,#0880
Replaced by INT9(01H)
■ Setting Detect Address
1)Disable the detection address setting register 0 (PADR0) where the detect address is set for address
match detection (PACSR: AD0E = 0).
2)Set the detect address in the detection address setting register 0 (PADR0).Set "FFH" at the higher bits of
the detection address setting register 0 (PADR0), "00H" at the middle bits, and "1FH" at the lower bits.
3)Enable the detect address setting register 0 (PADR0) where the detect address is set for address match
detection (PACSR: AD0E = 1).
■ Program Execution
4)If the address of the instruction to be executed in the program matches the set detect address, the first
instruction code at the matched address is replaced by the INT9 instruction code ("01H").
5)INT9 instruction is executed.INT9 interrupt is generated and then interrupt processing program is
executed.
563
CHAPTER 17 ADDRESS MATCH DETECTING FUNCTION
17.4.1
Example of using Address Match Detection Function
This section gives an example of patch processing for program correction using the
address match detection function.
■ System Configuration and E2PROM Memory Map
● System configuration
Figure 17.4-2 gives an example of the system configuration using the address match detection function.
Figure 17.4-2 Example of System Configuration using Address Match Detection Function
Serial E2PROM
interface
MCU
F2MC-16LX
E2PROM
Function patch program
Pull up resistor
SIN
connector (UART)
External patch program reception
564
CHAPTER 17 ADDRESS MATCH DETECTING FUNCTION
■ E2PROM Memory Map
Figure 17.4-3 shows the allocation of the patch program and data at storing the patch program in E2PROM.
Figure 17.4-3 Allocation of E2PROM Patch Program and Data
E2PROM
Address
PADR0
PADR1
0000H
Patch program byte count
0001H
Detect address0 (Low)
0002H
Detect address0 (Middle)
0003H
Detect address0 (High)
0004H
Patch program byte count
0005H
Detect address1 (Low)
0006H
Detect address1 (middle)
0007H
Detect address1 (High)
0010H
Patch program0
(main body)
0020H
Patch program1
(main body)
Patch program0
Patch program1
● Patch program byte count
The total byte count of the patch program (main body) is stored.If the byte count is "00H", it indicates that
no patch program is provided.
● Detect address (24 bits)
The address where the instruction code is replaced by the INT9 instruction code due to program error is
stored.This address is set in the detection address setting registers (PADR0 and PADR1).
● Patch program (main body)
The program executed by the INT9 interrupt processing when the program address matches the detect
address is stored.Patch program 0 is allocated from any predetermined address.Patch program 1 is allocated
from the address indicating <starting address of patch program 0 + total byte count of patch program 0>.
565
CHAPTER 17 ADDRESS MATCH DETECTING FUNCTION
■ Setting and Operating State
● Initialization
• E2PROM data are all cleared to "00H".
● Occurrence of program error
• By using the connector (UART), information about the patch program is transmitted to the MCU
(F2MC-16LX) from the outside according to the allocation of the E2PROM patch program and data.
• The MCU (F2MC-16LX) stores the information received from outside in the E2PROM.
● Reset sequence
• After reset, the MCU (F2MC-16LX) reads the byte count of the E2PROM patch program to check the
presence or absence of the correction program.
• If the byte count of the patch program is not "00H", the higher, middle and lower bits at detect addresses
0 and 1 are read and set in the detection address setting registers 0 and 1 (PADR0 and PADR1).The
patch program (main body) is read according to the byte count of the patch program and written to
RAM in the MCU (F2MC-16LX).
• The patch program (main body) is allocated to the address where the patch program is executed in the
INT9 interrupt processing by the address match detection function.
• Address match detection is enabled (PACSR: AD0E = 1, AD1E = 1)
● INT9 Interrupt processing
• Interrupt processing is performed by the INT9 instruction.MB90895 series has no interrupt request flag
by address match detection.Therefore, if the stack information in the program counter is discarded, the
detect address cannot be checked.When checking the detect address, check the value of program counter
stacked in the interrupt processing routine.
• The patch program is executed, branching to the normal program.
566
CHAPTER 17 ADDRESS MATCH DETECTING FUNCTION
■ Operation of Address Match Detection Function at Storing Patch Program in E2PROM
Figure 17.4-4 shows the operation of the address match detection function at storing the patch program in
E2PROM.
Figure 17.4-4 Operation of Address Match Detection Function at Storing Patch Program in E2PROM
000000H
(3)
Patch program
RAM
Detect address setting registers
E2PROM
(1)
Setting Detect Address
(Reset sequence)
Serial E2PROM
Interface
• Pach program byte count
• Address detection address
• Patch program
ROM
(2)
(4)
Program error
FFFFFFH
(1) Execution of detection address setting of reset sequence and normal program
(2) Branch to patch program which expanded in RAM with INT9 interrupt processing by
address match detection
(3) Patch program execution by branching of INT9 processing
(4) Execution of normal program which branches from patch program
567
CHAPTER 17 ADDRESS MATCH DETECTING FUNCTION
■ Flow of Patch Processing
Figure 17.4-5 shows the flow of patch processing using the address match detection function.
Figure 17.4-5 Flow of Patch Processing
E2PROM
0000H
Patch program byte count :80H
0001H
Detect address(Low)
0002H
Detect address(Middle) :80H
0003H
Detect address(High)
0010H
Patch program
0090H
FFFFH
YES
Reset
INT9
E2PROM: 00H
read in
Patch program branching
JMP 000400H
Patch program execution
000400H to 000480H
E2PROM: 0000H
=0
NO
Patch program end
JMP FF8050H
Detect address read in
E2PROM: 0001H to 0003H
↓
MCU: PADR0 Setting
Patch program read in
E2PROM: 0010H to 008FH
↓
MCU: 000400H to 00047FH
Enables the address
match detection
(PACSR: AD0E =1)
Usual program
execution
NO
568
program address
=PADR0
YES
INT9
:00H
:FFH
CHAPTER 17 ADDRESS MATCH DETECTING FUNCTION
17.5
Program Example of Address Match Detection Function
This section gives a program example for the address match detection function.
■ Program Example of Address Match Detection Function
● Processing specification
If the address of the instruction to be executed by the program matches the address set in the detection
address setting register (PADR0), the INT9 instruction is executed.
● Coding example
PACSR EQU 00009EH
;Address detection control register
PADRL EQU 001FF0H
;Detect address setting registers 0 Low
PADRM EQU 001FF1H
;Detect address setting registers 0 Middle
PADRH EQU 001FF2H
;Detect address setting registers 0 High
;
;---------Main Program------------------------------------CODE CSEG
START:
;Stack pointer (SP), already initialized
MOV PADRL,#00H
MOV PADRM,#00H
MOV PADRH,#00H
;Detect address setting registers 0 Low
;Detect address setting registers 0 Middle
;Detect address setting registers 0 High
;
MOV I:PACSR,#00000010B ;Enables the address match
•
User processing
•
LOOP:
•
User processing
•
BRA LOOP
;---------Interrupt program------------------------------------WARI:
•
User procseeing
•
RETI
;Return from interrupt processing
CODE ENDS
;---------Vector Setting-----------------------------------------VECT CSEG ABS=0FFH
ORG 00FFDCH
DSL WARI
ORG 00FFDCH
;Reset vector Setting
DSL START
DB 00H
;Single-chip mode Setting
VECT ENDS
END START
569
CHAPTER 17 ADDRESS MATCH DETECTING FUNCTION
570
CHAPTER 18
ROM MIRRORING FUNCTION
SELECTION MODULE
This chapter describes the functions and operations of
the ROM mirroring function select module.
18.1 Overview of ROM Mirroring Function Selection Module
18.2 ROM Mirroring Function Selection Register (ROMM)
571
CHAPTER 18 ROM MIRRORING FUNCTION SELECTION MODULE
18.1
Overview of ROM Mirroring Function Selection Module
The ROM mirroring function select module provides a setting so that ROM data in the
FF bank can be read by access to the 00 bank.
■ Block Diagram of ROM Mirroring Function Select Module
Figure 18.1-1 Block Diagram of ROM Mirroring Function Select Module
ROM Mirroring Function Select register (ROMM)
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
MI
Address
Internal Data Bus
Address Area
00 Bank
FF Bank
Data
ROM
■ Access to FF Bank by ROM Mirroring Function
Figure 18.1-2 shows the location in memory when ROM mirroring function allows access to the 00 bank to
read ROM data in the FF bank.
Figure 18.1-2 Access to FF Bank by ROM Mirroring Function
004000H
00 bank
ROM mirroring area
00FFFFH
FC0000H
FEFFFFH
FF0000H
FF4000H
FFFFFFH
572
MB90V495G
FF bank
(ROM mirroring
applicable Area)
MB90F897/S
CHAPTER 18 ROM MIRRORING FUNCTION SELECTION MODULE
■ Memory Space when ROM Mirroring Function Enabled/Disabled
Figure 18.1-3 shows the availability of access to memory space when the ROM mirroring function is
enabled or disabled
Figure 18.1-3 Memory Space when ROM Mirroring Function Enabled/Disabled (in Single Chip Mode)
When ROM mirroring
function is enabled
000000H
0000C0H
000100H
Address #1
When ROM mirroring
function is disabled
Peripheral
Peripheral
RAM area
RAM area
Register
Register
Expanded I/O area
Expanded I/O area
003900H
004000H
ROM area
(Image of FF Bank)
010000H
FE0000H
*
*
ROM area
FF0000H
ROM area
FFE000H
FFFFFFH
Products
ROM area
Hardwired
reset vectors
ROM area
Address #1
MB90V495G
MB90F897/S
: internal access memory
: Access prohibited
*: In MB90F897/S, When the area of FE0000H to FEFFFFH is read, data of
FF0000H to FFFFFFH can be read.
■ List of Registers and Reset Values of ROM Mirroring Function Select Module
Figure 18.1-4 List of Registers and Reset Values of ROM Mirroring Function Select Module
bit
ROM mirroring function select register (ROMM)
15
14
13
12
11
10
9
8
×
×
×
×
×
×
×
1
× : Undefined
573
CHAPTER 18 ROM MIRRORING FUNCTION SELECTION MODULE
18.2
ROM Mirroring Function Selection Register (ROMM)
The ROM mirroring function select register (ROMM) enables or disables the ROM
mirroring function.When the ROM mirroring function is enabled, ROM data in the FF
bank can be read by access to the 00 bank.
■ ROM Mirroring Function Select Register (ROMM)
Figure 18.2-1 ROM Mirroring Function Select Register (ROMM)
15
14
13
12
11
10
9
8
Reset Value
XXXXXXX1B
-
-
-
-
-
-
-
W
bit8
W
X
-
: Write Only
: Undefined
: Unused
: Reset Value
MI
0
1
ROM mirroring function select bit
Disables ROM mirroring function
Enables ROM mirroring function
Table 18.2-1 Functions of ROM Mirroring Function Select Register (ROMM)
bit name
Note:
574
Function
bit15
to
bit9
Reserved
Read: The value is undefined.
Be sure to set this bit to "0".
bit8
MI:
ROM mirroring function
select bit
This bit enables or disables the ROM mirroring function.
When set to "0": Disables ROM mirroring function
When set to "1": Enables ROM mirroring function
• When the ROM mirroring function is enabled (MI = 1), data
at ROM addresses "FF4000H" to "FFFFFFH" can be read by
accessing addresses "004000H" to "00FFFFH".
While the ROM area at addresses "004000H" to "00FFFFH" is being used, access to
the ROM mirroring function select register (ROMM) is prohibited.
CHAPTER 19
512 KBIT FLASH MEMORY
This chapter describes the function and operation of the
512 Kbit flash memory.
19.1 Overview of 512 Kbit Flash Memory
19.2 Registers and Sector/Bank Configuration of Flash Memory
19.3 Flash Memory Control Status Register (FMCS)
19.4 Flash Memory Write Control Register (FWR0/1)
19.5 How to Start Automatic Algorithm of Flash Memory
19.6 Reset Vector Addresses in Flash Memory
19.7 Check the Execution State of Automatic Algorithm
19.8 Details of Programming/Erasing Flash Memory
575
CHAPTER 19 512 KBIT FLASH MEMORY
19.1
Overview of 512 Kbit Flash Memory
There are three ways of programming and erasing flash memory as follows:
1. Programming and erasing using parallel writer
2. Programming and erasing using serial writer
3. Programming and erasing by executing program
This chapter describes the above "3. Programming and Erasing by Executing Program".
■ Overview of 512 Kbit Flash Memory
512 Kbit flash memory is placed in the FFHbanks on the CPU memory map. The function of the flash
memory I/F circuit is to provide read access and program access from the CPU to flash memory.
Programming and erasing flash memory are enabled by an instruction from the CPU via the flash memory
I/F circuit. This allows efficient reprogramming and programming data in the mounted state under CPU
control.
Data can be reprogrammed not only by program execution in RAM but also by program execution in flash
memory because of dual operation. In addition, an erase/write and reading of the different banks (the upper
and lower banks) can be executed concurrently.
■ Features of 512 Kbit Flash Memory
• 64 Kword x 8 bits/32 Kword x 16 bits (4 K x 4 + 16 K + 8 K x 2 + 4 K x 4) sector configuration
• An erase/program and a read can be executed concurrently in two banks configuration
• Uses automatic program algorithm (Embedded AlgorithmTM)
• Erase pause/restart function
• Detects completion of writing/erasing using data polling or toggle bit functions
• Detects completion of writing/erasing by CPU interrupts
• Erase function by sector (any combination of sectors)
• Programming/erase available 10,000 (min.)
• Flash read cycle time (min.): 2 machine cycles
Embedded AlgorithmTM is a registered trademark of Advanced Micro Devices, Inc.
Note:
The function of the manufacture code and device code to be read is not provided.
These codes cannot be accessed by any command.
■ Programming and Erasing Flash Memory
• Programming and erasing flash memory in the same bank cannot be performed at the same time.
• Data can be programmed into and erased from flash memory by executing either the program residing in
the flash memory or the one copied to RAM from the flash memory.
576
CHAPTER 19 512 KBIT FLASH MEMORY
19.2
Registers and Sector/Bank Configuration of Flash Memory
This section explains the registers and the sector/bank configuration of flash memory.
■ List of Registers and Reset Values of Flash Memory
Figure 19.2-1 List of Registers and Reset Values of Flash Memory
bit
Flash memory control status
register (FMCS)
bit
Flash memory write control
register (FWR0)
bit
Flash memory write control
register (FWR1)
7
6
5
4
3
2
1
0
0
0
0
´
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
´: Undefined
■ Sector and Bank Configuration of 512 Kbit Flash Memory
Figure 19.2-2 shows the sector configuration of 512 Kbit flash memory. The upper and lower addresses of
each sector are given in the figure.
● Sector configuration
For access from the CPU, the FF bank register has SA0 to SA9.
● Bank configuration
The flash memory consists of two banks: upper one ranging from SA4 and SA9 and lower one from SA0
and SA3.
577
CHAPTER 19 512 KBIT FLASH MEMORY
Figure 19.2-2 Sector Configuration of 512 Kbit Flash Memory
Flash memory
CPU address
Writer address*
FF0000H
70000H
FF0FFFH
70FFFH
FF1000H
71000H
FF1FFFH
71FFFH
FF2000H
72000H
FF2FFFH
72FFFH
FF3000H
73000H
FF3FFFH
73FFFH
FF4000H
74000H
FF7FFFH
77FFFH
FF8000H
78000H
FF8FFFH
78FFFH
FFC000H
7C000H
FFCFFFH
7CFFFH
FFD000H
7D000H
FFDFFFH
7DFFFH
FFE000H
7E000H
FFEFFFH
7EFFFH
FFF000H
7F000H
FFFFFFH
7FFFFH
SA0 (4 Kbytes)
SA1 (4 Kbytes)
SA2 (4 Kbytes)
SA3 (4 Kbytes)
SA4 (16 Kbytes)
SA5 (16 Kbytes)
SA6 (4 Kbytes)
SA7 (4 Kbytes)
SA8 (4 Kbytes)
SA9 (4 Kbytes)
*: The writer address is equivalent to the CPU address when data is
programmed to flash memory by a parallel writer. This address is
where programming and erasing are performed by a
general-purpose writer.
578
CHAPTER 19 512 KBIT FLASH MEMORY
19.3
Flash Memory Control Status Register (FMCS)
The flash memory control status register (FMCS) functions are shown in Figure 19.3-1
"Functions of Flash Memory Control Status Register (FMCS)".
■ Flash Memory Control Status Register (FMCS)
Figure 19.3-1 Flash Memory Control Status Register (FMCS)
7
6
5
4
3
2
1
0
R
W
W
W
W
Reset value
000X0000B
R/W R/W R/W
bit 0
Reserved bit
Reserved
0
Always set to "0"
bit 1
Reserved bit
Reserved
0
Always set to "0"
bit 2
Reserved bit
Reserved
0
Always set to "0"
bit 3
Reserved bit
Reserved
0
Always set to "0"
bit 4
Flash memory programming/erasing status bit
RDY
0
Programming/erasing (next data programming/erasing disabled)
1
Programming/erasing terminated (next data programming/erasing enabled)
bit 5
WE
0
1
Flash memory programming/erasing enable bit
Programming/erasing flash memory area disabled
Programming/erasing flash memory area enabled
bit 6
RDYINT
0
1
Flash memory operation flag bit
Read
Programming/erasing
Write
This RDYIN bit cleared
Programming/erasing terminated No effect
bit 7
R/W
R
W
X
:
:
:
:
:
Read/Write
Read only
Write only
Undefined
Reset value
INTE Flash memory programming/erasing interrupt enable bit
0
Interrupt disabled at end of programming/erasing
1
Interrupt enabled at end of programming/erasing
579
CHAPTER 19 512 KBIT FLASH MEMORY
Table 19.3-1 Functions of Flash Memory Control Status Register (FMCS)
Bit Name
bit 7
INTE:
Flash memory
programming/erasing
interrupt enable bit
This bit enables or disables an interrupt as programming/erasing flash
memory is terminated.
When set to "1": If the flash memory operation flag bit is set to "1"
(FMCS: RDYINT = 1), an interrupt is requested.
bit 6
RDYINT:
Flash memory
operation flag bit
This bit shows the operating state of flash memory.
If programming/erasing flash memory is terminated, the RDYINT bit
is set to "1" in timing of termination of the automatic flash memory
algorithm.
• When interrupt for flash memory program/erase termination is
enabled (FMCS: INTE = 1), If RDYINT bit is set to "1" an
interrupt request is generated.
• If the RDYINT bit is "0", programming/erasing flash memory is
disabled.
When set to "0": Cleared.
When set to "1": Unaffected.
If the read-modify-write (RMW) instructions are used, "1" is always
read.
bit 5
WE:
Flash memory
programming/erasing
enable bit
This bit enables or disables the programming/erasing of flash
memory.
The WE bit should be set before starting the command to program/
erase flash memory.
When set to "0": No program/erase signal is generated even if the
command to program/erase the FF bank is input.
When set to "1": Programming/erasing flash memory is enabled
after inputting program/erase command to the FF
bank.
• When not performing programming/erasing, the WE bit should be
set to "0" so as not to accidentally program or erase flash memory.
• To program data into the flash memory, after setting FMCS:WE
to "1" to write-enable the flash memory and set the flash memory
write control register (FWR0/1). When FMCS:WE contains "0"
for write protection, programming into the flash memory is not
performed even with the flash memory write control register
(FWR0/1) write-enabling the flash memory.
bit 4
RDY:
Flash memory
programming/erasing
status bit
This bit shows the programming/erasing status of flash memory.
• If the RDY bit is 0, programming/erasing flash memory is
disabled.
• The read/reset command and the sector erasing pause command
can be accepted even if the RDY bit is 0. The RDY bit is set to "1"
when programming/erasing is completed.
Reserved: Reserved
bits
Always set these bits to 0.
bit 3 to bit 0
580
Function
CHAPTER 19 512 KBIT FLASH MEMORY
Note:
The flash memory operation flag bit (RDYINT) and flash memory programming/
erasing status bit (RDY) do not change simultaneously. A program should be created
so as to identify the termination of programming/erasing using either the RDYINT bit
or RDY bit.
Automatic algorithm
end timing
RDYINT bit
RDY bit
1 Machine cycle
581
CHAPTER 19 512 KBIT FLASH MEMORY
19.4
Flash Memory Write Control Register (FWR0/1)
The flash memory write control register (FWR0/1) is a register in the flash memory
interface, used to set the accidental write preventive function for the flash memory.
■ Flash memory write control register (FWR0/1)
The flash memory write control register (FWR0/1) contains the write-enable/protect bits for individual
sectors (SA0 to SA9). The reset value of the bits is "0" to disable writing to the sectors. Writing "1" to one
of the bits enabled to write the corresponding sector. Writing "0" to it prevents an accidental write from
being executed to the sector. Once you have written "0" to the bit, therefore, you cannot write to the sector
even though you write "1" to the bit. When you write to the sector again, you have to reset the bit.
Figure 19.4-1 Flash Memory Write Control Register (FWR0/1)
FWR0
[390AH]
FWR1
[390BH]
bit
7
5
4
3
2
1
0
SA7E SA6E SA5E SA4E SA3E SA2E SA1E SA0E
bit
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
15
14
13
12
11
10
9
8
-
-
-
-
-
-
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
R/W : Read/write enabled
0
: Write protected [Reset value]
582
6
SA9E SA8E
( 0)
R/W
(0)
R/W
CHAPTER 19 512 KBIT FLASH MEMORY
Figure 19.4-2 Flash Memory Write-Protect, Write-Enable, Accidental-Write-Preventive Status Example in
the Flash Memory Write Control Register (FWR0/1)
Initialize
Register
write
Register
write
Initialize
RST
Write
protected
Write
enabled
accidentalwriteprevent
Write
protected
SA0E
Write
protected
accidental-write-prevent
Write
protected
Write
protected
accidental-write-prevent
Write
protected
Write
protected
Write enabled
Write
protected
SA1E
SA2E
SA3E
Write-protected: 0 status. "0" has not been written to the flash memory write control register (FWR0/1),
where you can write "1" to the register bit for each sector to write-enable the sector.
(after reset state)
Write-enabled: 1 status. Data can be written to the corresponding sector.
Accidental write preventive: 0 status. "0" has been written to the flash memory write control register
(FWR0/1), where the corresponding sector cannot be write-enabled ("1")
even though "1" is written to the register bit.
583
CHAPTER 19 512 KBIT FLASH MEMORY
Table 19.4-1 Functions of Flash Memory Write Control Register (FWR0/1)
Bit Name
bit 15 to
bit 10
bit 9to bit 0
Function
Reserved: Reserved bits
Always set these bits to 0.
SA9E to SA0E:
These bits are used to set the accidental write preventive function
for the individual sectors of the flash memory. Writing "1" to each
of the bits write-enables the corresponding sector. Writing "0" to
the bit activates the accidental write preventive function for the
sector.
Resetting the bit initializes it to "0" (write-protecting the sector).
Accidental write preventive function setting bits and flash memory
sectors
Accidental write
preventive function
setting bits
Bit
9
8
7
6
5
4
3
2
1
0
Bit name
SA9E
SA8E
SA7E
SA6E
SA5E
SA4E
SA3E
SA2E
SA1E
SA0E
Flash memory sector
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
Write-protected: 0 status. "0" has not been written to the flash
memory write control register (FWR0/1), where
you can write "1" to the register bit for each
sector to write-enable the sector (after reset state).
Write-enabled: 1 status. Data can be written to the corresponding
sector.
Accidental write preventive: 0 status. "0" has been written to the
flash memory write control register
(FWR0/1), where the corresponding
sector cannot be write-enabled ("1")
even though "1" is written to the
register bit.
584
CHAPTER 19 512 KBIT FLASH MEMORY
■ Flash Memory Write Control Register (FWR0/1) Setting Flow
Set the FMCS:WE bit, then set the bits for sectors to write to and the bits for sectors to be prevented from
an accidental write in the flash memory write control register (FWR0/1) to "1" and "0", respectively. Note
that writes must be performed in words and bit manipulation instructions must not be used for setting.
Figure 19.4-3 Sample Procedure for Flash Memory Write-Enable/Protect Setting and Writing
Start
FMCS: WE (bit5)
Programming enabled
FFWR0/1
Accidental write preventive function setting
(Accidental write preventive sector: 0,
writing sector
:1 )
Program command sequence
(1)FFUAAA
XXAA
(2)FFU554
XX55
(3)FFUAAA
XXA0
(4)Program address
Program data
Next address
Internal address read
Data polling
(DQ7)
Data
Data
0
Timing limit
(DQ5)
1
Internal address read
Data
Data polling
(DQ7)
Data
Programming error
Last address
NO
YES
FMCS: WE (bit5)
Programming enabled
Completed
585
CHAPTER 19 512 KBIT FLASH MEMORY
■ Setting of FMCS:WE
When writing the flash memory, after setting the FMCS:WE bit to "1" in order to be write-enabled, then set
the flash memory write control register (FWR0/1). In case of FMCS:WE is "0", writing is disabled even if
the flash memory write control register (FWR0/1) is write-enabled.
586
CHAPTER 19 512 KBIT FLASH MEMORY
19.5
How to Start Automatic Algorithm of Flash Memory
There are four commands for starting the automatic algorithm of flash memory: read/
reset, write, chip erase, sector erase. The sector erase command controls suspension
and resumption.
■ Command Sequence Table
Table 19.5-1 lists the commands to be used to program or erase the flash memory. You can write to the
command register both in bytes and in words. The upper byte written by word access is ignored.
Table 19.5-1 Command Sequence Table
Write Cycle of
Command Bus
Write
First Bus
Sequence
Access Address Data
Read/
FFXXXXH XXF0H
1
Reset*
Read/
4
FFUAAAH XXAAH
Reset*
Write
4
FFUAAAH XXAAH
program
Chip
6
FFXAAAH XXAAH
erace
Sector
6
FFUAAAH XXAAH
erase
Write Cycle of Write Cycle of Write Cycle of Write Cycle of Write Cycle of
Second Bus
Third Bus
Fourth Bus
Fifth Bus
Sixth Bus
Address Data Address Data Address Data Address Data Address Data
-
-
-
-
-
-
FFU554H XX55H FFUAAAH XXF0H
RA
RD
-
-
-
-
FFU554H XX55H FFUAAAH XXA0H
PA
PD
-
-
-
-
-
-
-
-
FFX554H XX55H FFXAAAH XX80H FFXAAAH XXAAH FFX554H XX55H FFXAAAH XX10H
FFU554H XX55H FFUAAAH XX80H FFUAAAH XXAAH FFU554H XX55H
SA
Sector erase suspend
Input address"FFXXXXH" Data (xxB0H) suspends sector erasing.
Sector erase resume
Input address"FFXXXXH" Data (xx30H) suspends and resume sector erasing.
XX30H
RA: Read address
PA: Write address
SA: Sector address (Specify an arbitrary address in sector)
RD: Read data
PD: Write data
U: The upper 4 bit same as RA, PA, SA
*: Both 2 types of read/reset command can reset flash memory to read mode.
Notes:
• Addresses in the table are the values in the CPU memory map. All addresses and data are
hexadecimal values, where "x" is any value.
• The address representations "U" in the table are not arbitrary; the four address bits (bits 15
to 12) must have the same value as RA, PA, and SA.
Example:
When RA = FFC48EH -> U = C
When SA = FF3000H -> U = 3
When PA = FF1024H -> U = 1
• The chip erase command is accepted only when all sectors have been write-enabled. The
chip erase command is ignored when any of the sector write-enable/protect bits in the flash
memory write control register (FWR0/1) contains "0" (write-protected or accidental write
prevented status).
587
CHAPTER 19 512 KBIT FLASH MEMORY
■ Notes on Command Issuance
Pay attention to the following points when issuing commands in the command sequence table:
• Write-enable each required sector before issuing the first command.
• The upper address "U" bits (bits 15 to 12) used when commands are issued must have the same value as
RA, PA, and SA, from the first command on.
If these instructions are not followed, commands are not recognized normally, requiring that the command
sequencer in the flash memory be initialized by a reset.
588
CHAPTER 19 512 KBIT FLASH MEMORY
19.6
Reset Vector Addresses in Flash Memory
The MB90F897 uses hardwired reset vectors.
In CPU mode, any read access to addresses FFFFDCH to FFFFDFH returns a hardwarefixed value. In flash memory mode, by contrast, these addresses are accessible.
Writing to these addresses is therefore meaningless. When programming the flash
memory by CPU access, in particular, do not read these addresses by software polling.
In that case, fixed reset vector values are read in place of flash memory status flag
values.
■ Hardwired Reset Vector Addresses
Table 19.6-1 lists reset vectors and mode data fixed values.
Table 19.6-1 Reset Vectors and Mode Data Fixed Values
Reset Vector
Mode Data
Note:
Address
Data (Fixed Value)
FFFFDCH
00H
FFFFDDH
E0H
FFFFDEH
FFH
FFFFDFH
00H
Reset vectors and mode data have values indicated as above, so values of them in the program
written to flash memory have no effect on operation. However, when using the same program in
mask ROM, it is possible to operate differently, therefore, be sure to write the same data to flash
memory.
589
CHAPTER 19 512 KBIT FLASH MEMORY
19.7
Check the Execution State of Automatic Algorithm
Since the programming/erasing flow is controlled by the automatic algorithm, hardware
sequence flag can check the internal operating state inside of flash memory.
■ Hardware Sequence Flags
● Overview of hardware sequence flag
The hardware sequence flag consists of the following 5-bit outputs:
• Data polling flag (DQ7)
• Toggle bit flag (DQ6)
• Timing limit over flag (DQ5)
• Sector erasing timer flag (DQ3)
• Toggle bit 2 flag (DQ2)
These flags can be used to check completion of programming, chip and sector erasing, and whether erase
code writing are enabled.
The hardware sequence flags can be referred by setting command sequences and performing read access to
the address of a target sector in flash memory. The hardware sequence flag should be output from the bank
of only command published side. Table 19.7-1 gives the bit allocation of the hardware sequence flags.
Table 19.7-1 Bit Allocation of Hardware Sequence Flags
Bit No.
Hardware sequence flag
7
6
5
4
3
2
1
0
DQ7
DQ6
DQ5
−
DQ3
DQ2
−
−
• To identify whether automatic programming/chip and sector erasing is in execution or terminated, check
the hardware sequence flag or the flash memory programming/erasing status bit (FMCS: RDY) in the
flash memory control status register. Programming/erasing is terminated, returning to the read/reset
state.
• To create a programming/erasing program, use the DQ7, DQ6, DQ5, DQ3 and DQ2 flags to check that
automatic programming/erasing is terminated and read data.
• The hardware sequence flags can also be used to check whether the second and later sector erase code
writing is enabled.
590
CHAPTER 19 512 KBIT FLASH MEMORY
● Explanation of hardware sequence flag
Table 19.7-2 lists the functions of the hardware sequence flag.
Table 19.7-2 List of Hardware Sequence Flag Functions
State
State change in
normal
operation
DQ7
DQ6
DQ5
DQ3
DQ2
DQ7 →
DADATA:7
Toggle →
DATA:6
0→
DATA:5
0→
DATA:3
1→
DATA:2
0→ 1
Toggle →
Stop
0→ 1
1
Toggle →
Stop
0
Toggle
0
0→ 1
Toggle
Erasing → Sector erasing
suspended
(Sector being erased)
0→ 1
Toggle → 1
0
1→ 0
Toggle
Sector erasing suspended →
Resumed
(Sector being erased)
1→ 0
1 → Toggle
0
0→ 1
Toggle
Sector erasing being
suspended
(Sector not being erased)
DATA:7
DATA:6
DATA:5
DATA:3
DATA:2
DQ7
Toggle
1
0
1
0
Toggle
1
1
*
Programming → Completed
(when program address
specified)
Chip and sector erasing →
Completed
Sector erasing wait →
Started
Abnormal
operation
Programming
Chip and sector erasing
*: If the DQ5 flag is 1 (timing limit over), the DQ2 flag performs the toggle operation for continuous reading from the
programming/erasing sector but does not perform the toggle operation for reading from other sectors.
591
CHAPTER 19 512 KBIT FLASH MEMORY
19.7.1
Data Polling Flag (DQ7)
The data polling flag (DQ7) is a hardware sequence flag which mainly used to notify that
the automatic algorithm is executing or has been completed using the data polling
function.
■ Data Polling Flag (DQ7)
Table 19.7-3 and Table 19.7-4 give the state transition of the data polling flag.
Table 19.7-3 State Transition of Data Polling Flag (State Change at Normal Operation)
Operating State
Programming →
Completed
Chip and
Sector Erasing
→ Completed
DQ7
DQ7 → DATA:7
0 → 1
Wait for Sector
Erasing →
Started
Sector Erasing
→ Erasing
Suspended
(Sector being
Erased)
Sector Erasing
Suspended →
Resume
(Sector being
Erased)
Sector Erasing
being
Suspended
(Sector not
being Erased)
0
0 → 1
1 → 0
DATA:7
Table 19.7-4 State Transition of Data Polling (State Change at Abnormal Operation)
Operating
State
DQ7
Programming
Chip and
Sector Erasing
DQ7
0
● At programming
• Read access during execution of the auto-programming algorithm causes flash memory to output the
reversed data of bit 7 last written.
• Read access at the end of the auto-programming algorithm causes flash memory to output the read value
of bit 7 at the address to which read access was performed.
● At chip/sector erasing
• During executing chip and sector erasing algorithms, when read access is made to the currently being
erasing sector, bit 7 of flash memory outputs 0. When chip erasing/sector erasing is terminated, bit 7 of
flash memory outputs 1.
● At sector erasing suspension
• Read access during sector erasing suspension causes flash memory to output 1 if the address specified
by the address signal belongs to the sector being erased. Flash memory outputs bit 7 (DATA: 7) of the
read value at the address specified by the signal address if the address specified by the address signal
does not belong to the sector being erased.
• Referring this flag together with the toggle bit flag (DQ6) permits a decision on whether flash memory
is in the erase suspended state and which sector is being erased.
592
CHAPTER 19 512 KBIT FLASH MEMORY
Note:
Read access to the specified address while the automatic algorithm starts is ignored. Data
reading can be enabled after "1" is set to data polling flag (DQ7). Data reading after the end of
the automatic algorithm should be performed following read access after completion of data
polling has been checked.
593
CHAPTER 19 512 KBIT FLASH MEMORY
19.7.2
Toggle Bit Flag (DQ6)
The toggle bit flag is a hardware sequence flag used to notify that the automatic
algorithm is being executed or in the end state using the toggle bit function.
■ Toggle Bit Flag (DQ6)
Table 19.7-5 and Table 19.7-6 give the state transition of the toggle bit flag.
Table 19.7-5 State Transition of Toggle Bit Flag (State Change at Normal Operation)
Operating State
Programming
→ Completed
Chip and
Sector Erasing
→ Erasing
Completed
DQ6
Toggle →
DATA:6
Toggle → Stop
Sector Erasing
Wait for Sector → Erasing
Erasing →
Suspended
Erasing Started (Sector being
Erased)
Toggle
Toggle → 1
Sector Erasing
Suspended →
Resume
(Sector being
Erased)
Sector Erasing
Suspended
(Sector not
being Erased)
1 → Toggle
DATA:6
Table 19.7-6 State Transition of Toggle Bit Flag (State Change at Abnormal Operation)
Operating
State
DQ6
Programming
Chip and
Sector Erasing
Toggle
Toggle
● At programming and chip/sector erasing
• If a continuous read access is made during the execution of the automatic algorithm for programming
and chip erasing/sector erasing, flash memory toggle-outputs 1 and 0 alternately every reading.
• If a continuous read access is made after the completion of the automatic algorithm for programming
and chip erasing/sector erasing, flash memory outputs bit 6 (DATA: 6) for the read value of the read
address every reading.
● At sector erasing suspension
If a read access is made in the sector erasing suspension state, flash memory outputs 1 when the read
address is the sector being erased and bit 6 (DATA: 6) for the read value of the read address when the read
address is not the sector being erased.
594
CHAPTER 19 512 KBIT FLASH MEMORY
19.7.3
Timing Limit Over Flag (DQ5)
The timing limit over flag (DQ5) is a hardware sequence flag that notifies flash memory
that the execution of the automatic algorithm has exceeded a prescribed time (the time
required for programming/erasing).
■ Timing Limit Over Flag (DQ5)
Table 19.7-7 and Table 19.7-8 give the state transition of the timing limit over flag.
Table 19.7-7 State Transition of Timing Limit Over Flag (State Change at Normal Operation)
Operating State
Programming
→ Completed
Chip and
Sector Erasing
→ Completed
DQ5
0 → DATA:5
0→1
Wait for Sector
Erasing →
Started
Sector Erasing
→ Erasing
Suspended
(Sector being
Erased)
Sector Erasing
Suspended →
Resume
(Sector being
Erased)
Sector Erasing
being
Suspended
(Sector not
being Erased)
0
0
0
DATA:5
Table 19.7-8 State Transition of Timing Limit Over Flag (State Change at Abnormal Operation
Operating
State
DQ5
Programming
Chip and
Sector Erasing
1
1
● At programming and chip/sector erasing
• If a read access is made after starting the automatic algorithm for programming or chip /sector erasing
and it is within a prescribed time (the time required for programming/erasing), the timing limit over flag
(DQ5) outputs 0. If it exceeds the prescribed time, the timing limit over flag (DQ5) outputs 1.
• The timing limit over flag (DQ5) can be used to identify the success or failure of programming/erasing,
regardless of whether the automatic algorithm is in progress or terminated. If the automatic algorithm by
the data polling or the toggle bit function is in execution when the timing limit over flag (DQ5) outputs
1, programming can be identified as a failure.
• For example, when 1 is set to the flash memory address with 1 set the flash memory, programming fails.
In this case, the flash memory will be locked and the automatic algorithm will not complete. Therefore,
no valid data is output from the data polling flag (DQ7). Also, the toggle bit flag (DQ6) does not stop
the toggle operation and exceeds the time limit, causing the timing limit over flag (DQ5) to output 1.
This state means that the flash memory is not being used correctly; it does not mean that the flash
memory is faulty. When this state occurs, execute the reset command.
595
CHAPTER 19 512 KBIT FLASH MEMORY
19.7.4
Sector Erase Timer Flag (DQ3)
The sector erase timer flag is used to notify during the period of waiting for sector
erasing after the sector erase command has started.
■ Sector Erase Timer Flag (DQ3)
Table 19.7-9 and Table 19.7-10 give the state transition of the sector erase timer flag.
Table 19.7-9 State Transition of Sector Erase Timer Flag (State Change at Normal Operation)
Operating State
Programming
→ Completed
Chip and
Sector Erasing
→ Completed
DQ3
0 → DATA3
1
Wait for Sector
Erasing →
Started
Sector Erasing
→ Erasing
Suspended
(Sector being
Erased)
Sector Erasing
Suspended →
Resume
(Sector being
Erased)
Sector Erasing
being
Suspended
(Sector not
being Erased)
0 → 1
1 → 0
0→1
DATA:3
Table 19.7-10 State Transition of Sector Erase Timer Flag (State Change at Abnormal Operation)
Operating
State
DQ3
Programming
Chip and
Sector Erasing
0
1
● At sector erasing
• If a read access is made after starting the sector erase command and it is within a sector erasing wait
period, the sector erasing timer flag (DQ3) outputs 0. If it exceeds the period, the sector erasing timer
flag (DQ3) outputs 1.
• If the sector erasing timer flag (DQ3) is 1, indicating that the automatic algorithm for sector erasing by
the data polling or toggle bit function is in progress (DQ7 = 0; DQ6 produces a toggle output), sector
erasing is performed. If any command other than the sector erasing suspension is set, it is ignored until
sector erasing is terminated.
• If the sector erasing timer flag (DQ3) is 0, flash memory can accept the sector erase command. To
program the sector erase command, check that the sector erasing timer flag (DQ3) is 0. If the flag is 1,
flash memory may not accept the sector erase command of suspending.
● At sector erasing suspension
• Read access during sector erasing suspension causes flash memory to output 1, if the read address is in
the sector being erased. Flash memory outputs bit 3 (DATA: 3) for the read value of the read address
when the read address is not the sector being erased.
596
CHAPTER 19 512 KBIT FLASH MEMORY
19.7.5
Toggle Bit 2 Flag (DQ2)
The toggle bit 2 flag (DQ2) is a hardware sequence flag that notifies flash memory that
sector erasing is being suspended using the toggle bit function.
■ Toggle Bit Flag (DQ2)
Table 19.7-11 and Table 19.7-12 give the state transition of the toggle bit flag.
Table 19.7-11 State Transition of Toggle Bit Flag (State Change at Normal Operation)
Operating State
Programming
→ Completed
Chip and
Sector Erasing
→ Completed
DQ2
1 → DATA:2
Toggle → Stop
Wait for Sector
→ Started
Sector Erasing
→ Erasing
Suspended
(Sector being
Erased)
Sector Erasing
Suspended →
Resume Sector
being Erased)
Sector Erasing
being
Suspended
(Sector not
being Erased)
Toggle
Toggle
Toggle
DATA:2
Table 19.7-12 State Transition of Toggle Bit Flag (State Change at Abnormal Operation)
Operating State
DQ2
Programming
Chip and Sector Erasing
1
*
*: If the DQ5 flag is 1 (timing limit over), the DQ2 flag performs the toggle operation for continuous reading from the
programming/erasing sector but does not perform the toggle operation for reading from other sectors.
● At sector erasing
• If a continuous read access is made during the execution of the automatic algorithm for chip /sector
erasing, flash memory toggle-outputs 1 and 0 alternately every reading.
• If a continuous read access is made after the completion of the algorithm for chip/sector erasing, flash
memory outputs bit 2 (DATA: 2) of the read address every reading.
597
CHAPTER 19 512 KBIT FLASH MEMORY
● At sector erasing suspension
• If a continuous read access is made in the state of the sector erasing suspension, flash memory outputs 1
and 0 alternately when the read address is the sector being erased and bit 2 (DATA: 2) for the read value
of the read address when the read address is not the sector being erased.
• If programming is performed in the state of the sector erasing suspension, flash memory outputs 1 when
a continuous read access is started with the sector that is not in the state of the sector erasing suspension.
• The toggle bit 2 flag (DQ2) is used together with the toggle bit flag (DQ6) to detect that sector erasing is
suspended (the DQ2 flag performs the toggle operation but the DQ6 flag does not).
• If a read access to the sector being erased is made, the toggle bit 2 flag (DQ2) performs the toggle
operation, so it can also be used to detect the sector being erased.
598
CHAPTER 19 512 KBIT FLASH MEMORY
19.8
Details of Programming/Erasing Flash Memory
This section explains the procedure for inputting commands starting the automatic
algorithm, and for read/reset of flash memory, programming, chip erasing, sector
erasing, sector erasing suspension and sector erasing resumption.
■ Detailed Explanation of Programming and Erasing Flash Memory
The automatic algorithm can be started by programming the command sequence of read/reset,
programming, chip erasing, sector erasing, sector erasing suspension and erasing resumption from CPU to
flash memory. Programming flash memory from the CPU should always be performed continuously. The
termination of the automatic algorithm can be checked by the data polling function. After normal
termination, it returns to the read/reset state.
Each operation is explained in the following order.
• Read/reset state
• Data programming
• All data erasing (chip all erase)
• Any data erasing (sector erase)
• Sector erasing suspension
• Sector erasing resumption
599
CHAPTER 19 512 KBIT FLASH MEMORY
19.8.1
Read/Reset State in Flash Memory
This section explains the procedure for inputting the read/reset command to place flash
memory in the read/reset state.
■ Read/Reset State in Flash Memory
• Flash memory can be placed in the read/reset state by transmitting the read/reset command in the
command sequence table from CPU to flash memory.
• There are two kinds of read/reset commands: one is executed at one time bus operation, and the other is
executed at three times bus operation; the command sequence of both is essentially the same.
• Since the read/reset state is the initial state for flash memory, flash memory always enters this state after
power-on and at the normal termination of command. The read/reset state is also described as the wait
state for command input.
• In the read/reset state, a read access to flash memory enables data to be read. As is the case with mask
ROM, a program access from the CPU can be made.
• A read access to flash memory does not require the read/reset command. If the command is not
terminated normally, use the read/reset command to initialize the automatic algorithm.
600
CHAPTER 19 512 KBIT FLASH MEMORY
19.8.2
Data programming to flash memory
This section explains the procedure for inputting the program command to program
data to flash memory.
■ Data Programming to Flash Memory
• In order to start the data programming automatic algorithm, continuously transmit the program
command in the command sequence table from CPU to flash memory.
• At completion of data programming to a target address in the fourth cycle, the automatic algorithm starts
automatic programming.
● How to specify address
• Only even addresses can be specified for the programming address specified by programming data
cycle. Specifying odd addresses prevents correct writing. Writing to even addresses must be performed
in word data units.
• Programming is possible in any address order or even beyond sector boundaries. However, execution of
one programming command permits programming of data for only one word.
● Notes on data programming
• The bit data 0 cannot be returned to the bit data 1 by programming. When the bit data 0 is programmed
to data 1, the data polling algorithm (DQ7) or toggling (DQ6) is not terminated and the flash memory is
considered faulty; the timing limit over flag (DQ5) is determined as an error.
• When data is read in the read/reset state, the bit data remains 0. To return the bit data to 1 from 0, erase
flash memory data.
• All commands are ignored during automatic programming.
• If a hardware reset occurs during programming, data being programmed to addresses is not assured.
Please re-try from chip delete or sector erase.
■ Data Programming Procedure
• Figure 19.8-1 gives an example of the procedure for programming data into flash memory. The
hardware sequence flags can be used to check the operating state of the automatic algorithm in flash
memory. The data polling flag (DQ7) is used for checking the completion of programming to flash
memory in this example.
• Flag check data should be read from the address where data was last written.
• Because the data polling flag (DQ7) and the timing limit over flag (DQ5) change at the same time, the
data polling flag (DQ7) must be checked even when the timing limit over flag (DQ5) is 1.
• Similarly, since the toggle bit flag (DQ6) stops toggling at the same time the timing limit over flag
(DQ5) changes to 1, the toggle bit flag (DQ6) must be checked.
601
CHAPTER 19 512 KBIT FLASH MEMORY
Figure 19.8-1 Example of Data Programming Procedure
Start
FMCS: WE (bit5)
Programming enabled
FFWR0/1
Accidental write preventive function setting
(Accidental write preventive sector: 0,
writing sector
:1 )
Program command sequence
(1)FFUAAA
XXAA
(2)FFU554
XX55
(3)FFUAAA
XXA0
(4)Program address
Program data
Next address
Internal address read
Data polling
(DQ7)
Data
Data
0
Timing limit
(DQ5)
1
Internal address read
Data
Data polling
(DQ7)
Data
Programming error
Last address
YES
FMCS: WE (bit5)
Programming enabled
Completed
602
NO
CHAPTER 19 512 KBIT FLASH MEMORY
19.8.3
Data Erase from Flash Memory (Chip Erase)
This section explains the procedure for inputting the chip erase command to erase all
data from flash memory.
■ All Data Erase from Flash Memory (Chip Erase)
• All data can be erased from flash memory by continuously transmitting the chip erase command in the
command sequence table from CPU to flash memory.
• The chip erase command is executed in six bus operations. Chip erasing is started at completion of the
sixth programming cycle.
• Before chip erasing, the user need not perform programming to flash memory. During execution of the
automatic erasing algorithm, flash memory automatically programs 0 before erasing all cells.
■ Notes on Chip Erasure
• The chip erase command is accepted only when all sectors have been write-enabled. The chip erase
command is ignored when any of the sector write-enable/protect bits in the flash memory write control
register (FWR0/1) contains "0" (write-protected or accidental write prevented status).
• If the hardware reset is generated during erase operation, the data of flash memory is not guaranteed.
603
CHAPTER 19 512 KBIT FLASH MEMORY
19.8.4
Erasing Any Data in Flash Memory (Sector Erasing)
This section explains the procedure for inputting the sector erase command to erase
any data in flash memory. Sector-by-sector erasing is enabled and multiple sectors can
be specified at the same time.
■ Erasing Any Data in Flash Memory (Sector Erasing)
Any sector in flash memory can be erased by continuously transmitting the sector erase command in the
command sequence table from CPU to flash memory.
● How to specify sector
• The sector erase command is executed in six bus operations. By setting the address on the sixth cycle on
the even address in the target sector and programming the sector erase code (30H) to data, a 50 μs sector
erasing wait is started
• When erasing more than one sector, the sector erase code (30H) is programmed to the sector address to
be erased, following the above.
● Notes on specifying multiple sectors
• Sector erasing is started after a 50 μs period waiting for sector erasing is completed after the last sector
erase code has been programmed.
•
That is, when erasing more than one sector simultaneously, the address of erase sector address and the
sector code must be input within 50 μs. If the sector erase code is input 50 μs or later, it cannot be
accepted.
• Whether continuous programming of the sector erase code is enabled can be checked by the sector erase
timer flag (DQ3).
• In this case, the address from which the sector erase timer flag (DQ3) is read should correspond to the
sector to be erased.
■ Erasing Procedure for Flash Memory Sectors
• The state of the automatic algorithm in the flash memory can be determined using the hardware
sequence flag. Figure 19.7-2 "Example of Sector Erasing Procedure" gives an example of the flash
memory sector erase procedure. In this example, the toggle bit flag (DQ6) is used to check that erase
ends.
• DQ6 terminates toggling concurrently with the change of the timing limit over flag (DQ5) to 1, so the
DQ6 must be checked even when DQ5 is 1.
• Similarly, the data polling flag (DQ7) changes concurrently with the transition of the DQ5, so DQ7
must be checked.
■ Note on Sector Erasing
• If the hardware reset is generated during erase operation, the data of flash memory is not guaranteed.
Please re-try sector erase.
604
CHAPTER 19 512 KBIT FLASH MEMORY
Figure 19.8-2 Example of Sector Erasing Procedure
Start
FMCS: WE (bit5)
Programming enabled
FFWR0/1
Accidental write preventive function setting
(Accidental write preventive sector: 0,
writing sector
:1 )
Erase command sequence
(1) FFAAAA XXAA
(2) FF5554
XX55
(3) FFAAAA XX80
(4) FFAAAA XXAA
(5) FF5554
XX55
1
Sector erase timer
(DQ3)
0
(6) Code input to erase sector (30H)
Internal address read
YES
Is any other
erase sector?
NO
Internal address read 1
Internal address read 2
Toggle bit (DQ6)
Data 1 = Data 2
Next sector
YES
NO
0
Timing limit
(DQ5)
1
Internal address read
Internal address read
NO
Toggle bit (DQ6)
Data 1 = Data 2
YES
Erasing error
Last sector
NO
YES
FMCS : WE (bit 5)
Programming enabled
Completed
605
CHAPTER 19 512 KBIT FLASH MEMORY
19.8.5
Sector Erase Suspension
This section explains the procedure for inputting the sector erase suspend command to
suspend sector erasing. Data can be read from the sector not being erased.
■ Sector Erase Suspension
• To cause flash memory sector erasing to suspend, transmit the sector erasing suspend command in the
command sequence table from CPU to flash memory.
• The sector erasing suspend command suspends the sector erase currently being performed, enabling data
read from a sector that is currently not being erased.
• This command is only enabled during the sector erasing period including the erasing wait time; it is
ignored during the chip erasing period or during programming.
• The sector erasing suspend command is executed when the sector erasing suspend code (B0H) is
programmed. Arbitrary address in flash memory should be set for address. If the sector erasing suspend
command is executed during sector erasing pause, the successive command input is ignored.
• When the sector erasing suspend command is input during the sector erasing wait period, the sector
erase wait state ends immediately, the erasing is interrupted, and the erase stop state occurs.
• When the erase suspend command is input during the sector erasing after the sector erase wait period,
the erase suspend state occurs after a maximum of 20 μs.
■ Note
Please issue after 20μs or more after the sector deletion command is issued or issue it after 20μs or more
after the sector deletion restart command is issued when you issue the temporary stop command. However,
please stop the issue frequency several times.
606
CHAPTER 19 512 KBIT FLASH MEMORY
19.8.6
Sector Erase Resumption
This section explains the procedure for inputting the sector erase resume command to
resume erasing of the suspended flash memory sector.
■ Erase Resumption
• Suspended sector erasing can be resumed by transmitting the sector erase resume command in the
command sequence table from CPU to flash memory.
• The sector erase resume command resumes sector erasing suspended by the sector erase suspend
command. This command is executed by writing the erase resume code (30H). In this case, even address
in the specified sector for erase area is specified.
• Inputting the sector erase resume command during sector erasing is ignored.
607
CHAPTER 19 512 KBIT FLASH MEMORY
608
CHAPTER 20
DUAL OPERATION FLASH
This chapter describes the functions and operation of
Dual Operation Flash.
20.1 Overview of Dual Operation Flash
20.2 Register for Dual Operation Flash
20.3 Operation of Dual Operation Flash
609
CHAPTER 20 DUAL OPERATION FLASH
20.1
Overview of Dual Operation Flash
Dual Operation Flash consists of the upper bank (4K x 4) and lower bank (16K x 2 + 4K x
4), allowing concurrent execution of an erase/program and a read in the two banks,
which is not allowed in conventional flash products.
This feature enables program execution in the flash memory and programming control
using interrupts. It also eliminates the need for a conventional process to download a
program to RAM for execution to program data into the flash memory, resulting in
reduced download time and no need to consider power shutdown for RAM data
maintenance.
Also, the minimum sectors are as compact as four kilobytes that can be handled easily
as program/data areas.
■ Features of Dual Operation Flash
• Two-bank configuration, enabling simultaneous execution of an erase/program and reading
• Minimum sectors in four kilobytes to be handled easily as program/data areas
In the Dual Operation Flash, the following combination is possible.
Upper bank
Lower bank
Read
Read
Write/Sector eras
Write/Sector erase
Read
Chip erase
Note: When one bank is in state of write/sector erase, the other bank cannot use it.
610
CHAPTER 20 DUAL OPERATION FLASH
20.2
Register for Dual Operation Flash
The following register is used for operation of Dual Operation Flash:
• Sector switching register (SSR0)
■ Sector switching register (SSR0)
Figure 20.2-1 shows the configuration of the sector switching register (SSR0).
Please use byte access for write/read to the sector switching register.
Figure 20.2-1 The configuration of the sector switching register (SSR0)
SSR0
[390CH]
bit
7
6
Reserved Reserved
(0)
R/W
(0)
R/W
5
4
3
2
1
0
-
-
-
-
-
SEN0
(X)
(X)
(X)
(X)
(X)
(0)
R/W
R/W : Read/Write enabled
Table 20.2-1 the function of the sector switching register (SSR0)
Bit name
Function
bit7, bit6
Reserved: Reserved bit
Be sure to set to "0".
bit5 to
bit1
Undefined bit
At a read: The value is undefined.
At a write: The operation is not affected.
bit0
SEN0:
The SEN0 bit switches access from the CPU for reprogramming
the upper bank from SA9 containing the interrupt vector to SA3 in
the lower bank.
SEN0
0
1
Function
Interrupt vector to SA9 (Initial value)
Interrupt vector to SA3
611
CHAPTER 20 DUAL OPERATION FLASH
■ SEN0 bit access sector map
Figure 20.2-2 shows the access sector map based on the SEN0 setting.
Figure 20.2-2 The access sector map based on the SEN0 setting
CPU address
FF0000H
FF0FFFH
FF1000H
FF1FFFH
FF2000H
FF2FFFH
FF3000H
FF3FFFH
FF4000H
SA0:4K
SA0:4K
SA1:4K
SA1:4K
SA2:4K
SA2:4K
SA3:4K
SA9:4K
SA4:16K
SA4:16K
SA5:16K
SA5:16K
SA6:4K
SA6:4K
SA7:4K
SA7:4K
SA8:4K
SA8:4K
SA9:4K
SA3:4K
SEN0="0"
SEN0="1"
FF7FFFH
FF8000H
FFBFFFH
FFC000H
FFCFFFH
FFD000H
FFDFFFH
FFE000H
Interrupt
Vector
612
FFEFFFH
FFF000H
FFFFFFH
Hard Wired
Reset Vector
(FFE000H)
Interrupt
Vector
CHAPTER 20 DUAL OPERATION FLASH
20.3
Operation of Dual Operation Flash
Described below is the operation of Dual Operation Flash.
Pay particular attention to the following points when using Dual Operation Flash:
• Interrupt occurring when the upper bank is reprogrammed
• Sector switching register (SSR0) setting procedure
■ Interrupt occurring when the upper bank is reprogrammed
Dual Operation Flash consists of two banks and, like conventional flash memory products, it cannot
execute an erase/program and a read simultaneously in the same bank.
Since SA9 contains an interrupt vector, the interrupt vector from the CPU cannot be read normally when an
interrupt occurs at write access to the upper bank. To reprogram the upper bank, SSR0:SEN0 must be set to
"1". When an interrupt occurs, therefore, SA3 is accessed to read the interrupt vector data. The same data as
SA3 and SA9 must be before setting the sector switching register (SSR0).
■ Sector switching register (SSR0) setting procedure
Figure20.3-1 illustrates the procedure of setting the sector switching register (SSR0).
The SEN0 bit must be set to "1" before reprogramming of data in the upper bank. Note also that it is not
allowed to make any change to the setting of the sector switching register (SSR0) during write access to the
flash memory. Be sure to set the sector switching register (SSR0) before or after reprogramming the flash
memory.
During setting this register, the interrupt enable is set prohibit. After setting SEN0 bit, the interrupt will be
set enable.
Figure20.3-1 The procedure of setting the sector switching register (SSR0)
Start of
FLASH data reprogramming
Start of
FLASH data writing
Copy SA9 data to SA3
SSR0: SEN0 setting ("1")
Start of
FLASH data writing
End of
FLASH data reprogramming
End of
FLASH data reprogramming
SSR0: SEN0 setting ("0")
613
CHAPTER 20 DUAL OPERATION FLASH
■ Operation during Write/Erase
• If the interrupt is generated during write/erase to flash memory, the write/erase operation to flash
memory is prohibited in interrupt routine.
If there are two or more write/erase routines, the next write/erase routine should be execution after the
an write/erase routine step-by-step.
• During write/erase operation to flash memory, the state transferring from write/erase mode (main clock
mode, PLL clock mode, sub clock mode) is prohibited.
The state transfers after write/erase operation.
614
CHAPTER 21
CONNECTION EXAMPLE of
FLASH SERIAL
PROGRAMMING
This chapter provides an example of serial programming
connection using a flash microcontroller programmer
manufactured by Yokogawa Digital Computer
Corporation.
21.1 Basic Configuration of Serial Programming Connection for F2MC16LX MB90F897/S
21.2 Connection Example for Single-chip Mode (User Power Supply)
21.3 Connection Example for Single-chip Mode (Writer Power Supply)
21.4 Flash Microcontroller Programmer and Example of Minimum
Connection (User Power Supply)
21.5 Flash Microcontroller Programmer and Example of Minimum
Connection (Writer Power Supply)
615
CHAPTER 21 CONNECTION EXAMPLE of FLASH SERIAL PROGRAMMING
21.1
Basic Configuration of Serial Programming Connection for
F2MC-16LX MB90F897/S
MB90F897/S supports the Fujitsu standard serial on-board programming for the flash
ROM. Specifications for the on-board programming are explained as follows.
■ Basic Configuration of Serial Programming Connection for F2MC-16LX MB90F897/S
The flash microcontroller programmer manufactured by Yokogawa Digital Computer Corporation is used
for the Fujitsu standard serial on-board programming.
Figure 21.1-1 Basic Configuration of Serial Programming Connection
Host interface (AZ221)
Standard Target Probe (AZ210)
RS232C
flash microcontroller clock synchronous serial
MB90F897(S)
programmer
user's systemr
+
memory card
It is stand-alone and operable
Note:
For information about the functions and operating method of the flash microcontroller
programmers (AF220/AF210/AF120/AF110) and the general-purpose common cable for
connection (AZ210), contact Yokogawa Digital Computer Corporation.
Table 21.1-1 ins Used for Fujitsu Standard Serial On-board Programming (1 / 2)
Pin
MD2, MD1,
MD0
616
Function
Additional Information
Mode pins
Flash serial programming mode is selected when
MD2=1, MD1=1, and MD0=0.
X0, X1
Oscillator pins
In flash serial programming mode, the internal CPU
operating clock is equivalent to the PLL clock multiplied
by 1. As the oscillation clock frequency is used as the
internal operating clock, the oscillator used for serial
programming operates between 1 MHz and 16 MHz.
P30, P31
Writing program start pins
Input the "L" level to P 30 and the "H" level to P31.
RST
Reset pin
-
Table 21.1-1 ins Used for Fujitsu Standard Serial On-board Programming (2 / 2)
Pin
Note:
Function
Additional Information
SIN1
Serial data input pin
SOT1
Serial data output pin
SCK1
Serial clock input pin
C
C pin
Capacitance pin for stabilizing the power supply.
Connect a ceramic capacitor of about 0.1μF externally.
VCC
Power supply voltage supply
pin
Programming voltage (5V±10%)
VSS
GND pin
Use the same GND as for the flash microcontroller
programmer.
UART is used in clock synchronous mode.
The control circuit shown in Figure 21.1-2is required for using P30, SIN1, SOT1, and SCK1 also
in the user system. During serial programming, the user circuit can be separated by the TICS
signal from the flash microcontroller programmer.
Use the following serial programming connection examples shown in sections 21.2 to 21.5 as
reference.
• Connection Example for Single-chip Mode (User Power Supply)
• Connection Example for Single-chip Mode (Writer Power Supply)
• Flash Microcontroller Programmer and Example of Minimum Connection (User Power
Supply)
• Flash Microcontroller Programmer and Example of Minimum Connection (Writer Power
Supply)
Figure 21.1-2 Control Circuit
AF220/AF210/AF120/AF110
write control pin
MB90F897/S
write control pin
10KΩ
AF220/AF210/AF120/AF110
/TICS pin
user
617
CHAPTER 21 CONNECTION EXAMPLE of FLASH SERIAL PROGRAMMING
■ Oscillation Clock Frequency and Serial Clock Input Frequency
The serial clock frequency that can be input for MB90F897/S can be calculated using the following
formula. Modify the serial clock input frequency by setting the flash microcontroller programmer,
according to the oscillation clock frequency used.
Serial clock frequency that can be input = 0.125 × Oscillation clock frequency
Table 21.1-2 Maximum Serial Clock Frequency
Oscillation
clock
frequency
Maximum serial clock
frequency that can be
input to microcontroller
Maximum serial clock
frequency of AF220/AF210/
AF120/AF110 that can be set
Maximum serial clock
frequency of AF200 that
can be set
4MHz
500kHz
500kHz
500kHz
8MHz
1MHz
850kHz
500kHz
16MHz
2MHz
1.25MHz
500kHz
■ System Configuration of Flash Microcontroller Programmer (Manufactured by
Yokogawa Digital Computer Corporation)
Table 21.1-3 System Configuration of Flash Microcontroller Programmer (Manufactured by
Yokogawa Digital Computer Corporation)
Model
AF220/AC4P
Model with internal Ethernet interface: 100V-220V power adapter
AF210/AC4P
Standard model: 100V-220V power adapter
AF120/AC4P
Single-key model with internal Ethernet interface: 100V-220V power
adapter
AF110/AC4P
Single-key model: 100V-220V power adapter
Unit
Note:
618
Function
AZ221
RS232C cable for PC/AT used exclusively for the writer
AZ210
Standard target probe (a) length: 1m
FF201
Control module for Fujitsu F2MC-16LX flash microcontroller
/P2
2MB PC Card (optional): Flash memory capacity of up to 128 KB supported
/P4
4MB PC Card (optional): Flash memory capacity of up to 512 KB supported
The AF200 flash microcontroller programmer is an EOL product but is made available using the
control module FF201. Serial programming connection can also be supported following the
connection example in the next section.
21.2
Connection Example for Single-chip Mode
(User Power Supply)
Flash serial programming mode is selected when mode pins MD2 and MD0 of the user
system set to single-chip mode are set (MD2=1, MD0=0) by the TAUX and TMODE pins
of AF220/AF210/AF210/AF120/AF110. The following figure shows an example of the
connection when the user power supply is used.
■ Connection Example for Single-chip Mode (User Power Supply Used)
Figure 21.2-1 Example of Serial Programming Connection for MB90F897/S (User Power Supply Used)
AF220/AF210/AF120/AF110
Flash microcontroller
Programmer
User's system
Connector
DX10-28S
TAUX3
MB90F897/S
(19)
MD2
10KΩ
10KΩ
MD1
10KΩ
TMODE
(12)
MD0
X0
1MHz to 16MHz
X1
TAUX
(23)
/TICS
(10)
P30
10KΩ
user
10KΩ
10KΩ
/TRES
RST
(5)
user
10KΩ
P31
C
0.1μF
(13)
(27)
(6)
SIN1
SOT1
SCK1
TVcc
(2)
Vcc
GND
(7,8,
14,15,
21,22,
1,28)
TTXD
TRXD
TCK
User Power Supply
Vss
14pin
3,4,9,11,16,17,18,20,24,25,26pin is OPEN
DX10-28S : Write angle type
1pin
DX10-28S
28pin
15pin
Connector (Hirose Electronics) to pin assignment
619
CHAPTER 21 CONNECTION EXAMPLE of FLASH SERIAL PROGRAMMING
Notes:
• The same circuit as the controller circuit connected to P30 (Figure 21.2-2) is required when
using the SIN1, SOT1 and SCK1 pins also in the user system. During serial programming, the
user circuit can be separated by the TICS signal from the flash microcontroller programmer.
• Connect to AF220/AF210/AF120/AF110 when the user power supply is turned off.
Figure 21.2-2 Control Circuit
AF220/AF210/AF120/AF110
programming control pin
MB90F897/S
programming control pin
10KΩ
AF220/AF210/AF120/AF110
/TICS pin
user
620
21.3
Connection Example for Single-chip Mode
(Writer Power Supply)
Flash serial programming mode is selected when mode pins MD2 and MD0 of the user
system set to single-chip mode are set (MD2=1, MD0=0) by the TAUX and TMODE pins
of AF220/AF210/AF210/AF120/AF110. The following figure shows an example of the
connection when the writer power supply is used.
■ Connection Example for Single-chip Mode (Power Supplied from Flash Microcontroller
Programmer)
Figure 21.3-1 Example of Serial Programming Connection for MB90F897/S
(Power Supplied from Flash Microcontroller Programmer)
AF220/AF210/AF120/AF110
Flash microcontroller
Programmer
User's system
Connector
DX10-28S
TAUX3
MB90F897/S
MD2
(19)
10KΩ
10KΩ
MD1
10KΩ
TMODE
MD0
X0
(12)
1MHz to 16MHz
X1
TAUX
(23)
/TICS
(10)
P30
10KΩ
user
10KΩ
10KΩ
/TRES
RST
(5)
user
10KΩ
P31
C
0.1μF
TTXD
TRXD
TCK
TVcc
Vcc
TVPP1
GND
SIN1
SOT1
SCK1
(13)
(27)
(6)
(2)
(3)
(16)
Vcc
(7,8,
14,15,
21,22,
1,28)
User power supply
Vss
14pin
4,9,11,17,18,20,24,25,26pin is OPEN
DX10-28S : Write angle type
1pin
DX10-28S
28pin
15pin
Connector (Hirose Electronics) to pin assignment
621
CHAPTER 21 CONNECTION EXAMPLE of FLASH SERIAL PROGRAMMING
Notes:
• The same circuit as the controller circuit connected to P30 (Figure 21.3-2) is required when
using the SIN1, SOT1 and SCK1 pins also in the user system. During serial programming, the
user circuit can be separated by the TICS signal from the flash microcontroller programmer.
• Connect to AF220/AF210/AF120/AF110 when the user power supply is turned off.
• When supplying the programming power from AF220/AF210/AF120/AF110, avoid a short
circuit with the user power supply.
Figure 21.3-2 Control Circuit
AF220/AF210/AF120/AF110
Write control pin
MB90F897/S
Write control pin
10KΩ
AF220/AF210/AF120/AF110
/TICS pin
user
622
21.4
Flash Microcontroller Programmer and Example of
Minimum Connection (User Power Supply)
MD2, MD0 and P30 do not need to be connected to the flash microcontroller
programmer, when each pin is set as shown in Figure 21.4-1 during serial programming.
■ Flash Microcontroller Programmer and Example of Minimum Connection
(User Power Supply Used)
Figure 21.4-1 Flash Microcontroller Programmer and Example of Minimum Connection
(User Power Supply Used)
AF220/AF210/AF120/AF110
Flash microcontroller
Programmer
User's system
serial programming"1"
10KΩ
MB90F897/S
MD2
serial programming"1"
10KΩ
10KΩ
MD1
10KΩ
10KΩ
serial programming"0"
10KΩ
MD0
X0
1MHz to 16MHz
X1
10KΩ
serial programming"0"
P30
10KΩ
user control
P31
serial programming"1"
user control
C
connector
DX10-28S
0.1μF
10KΩ
/TRES
(5)
RST
TTXD
(13)
SIN1
TRXD
(27)
SOT1
TCK
(6)
SCK1
TVcc
(2)
GND
(7,8,
14,15,
21,22,
1,28)
Vcc
User power supply
Vss
14pin
3,4,9,10,11,12,16,17,18,19,20,23,24,25,26
pin is OPEN
DX10-28S : Write angle type
1pin
DX10-28S
28pin
15pin
Connector (Hirose Electronics) to pin assignment
623
CHAPTER 21 CONNECTION EXAMPLE of FLASH SERIAL PROGRAMMING
Notes:
• The control circuit illustrated in Figure 21.4-2 is required when using the SIN1, SOT1 and
SCK1 pins also in the user system. During serial programming, the user circuit can be
separated by the TICS signal from the flash microcontroller programmer.
• Connect to AF220/AF210/AF120/AF110 when the user power supply is turned off.
Figure 21.4-2 Control Circuit
AF220/AF210/AF120/AF110
write control pin
MB90F897/S
write control pin
10KΩ
AF220/AF210/AF120/AF110
/TICS pin
user
624
21.5
Flash Microcontroller Programmer and Example of
Minimum Connection (Writer Power Supply)
MD2, MD0 and P30 do not need to be connected to the flash microcontroller
programmer, when each pin is set as shown in Figure 21.5-1 during serial programming.
■ Example of Minimum Connection (Power Supplied from Flash Microcontroller
Programmer)
Figure 21.5-1 Example of Minimum Connection (Power Supplied from Flash Microcontroller Programmer)
AF220/AF210/AF120/AF110
Flash microcotroller
Programmer
User's system
serial programming"1"
MB90F897/S
10KΩ
MD2
serial programming"1"
10KΩ
10KΩ
10KΩ
10KΩ
MD1
MD0
10KΩ
serial programming"0"
X0
1MHz to 16MHz
X1
10KΩ
serial programming"0"
P30
10KΩ
user control
serial programming"1"
P31
user control
C
connector
DX10-28S
0.1μF
10KΩ
/TRES
(5)
RST
TTXD
(13)
SIN1
TRXD
(27)
SOT1
TCK
(6)
(2)
(3)
(16)
SCK1
TVcc
GND
Vcc
(7,8,
14,15,
21,22,
1,28)
Vss
14pin
4,9,10,11,12,17,18,19,20,23,24,25,26
pin is OPEN
DX10-28S : Write angle type
1pin
DX10-28S
28pin
15pin
Connector (Hirose Electronics) to pin assignment
625
CHAPTER 21 CONNECTION EXAMPLE of FLASH SERIAL PROGRAMMING
Notes:
• The control circuit illustrated in Figure 21.5-2 is required when using the SIN1, SOT1 and
SCK1 pins also in the user system. During serial programming, the user circuit can be
separated by the TICS signal from the flash microcontroller programmer.
• Connect to AF220/AF210/AF120/AF110 when the user power supply is turned off.
• When supplying the programming power from AF220/AF210/AF120/AF110, avoid a short
circuit with the user power supply.
Figure 21.5-2 Control Circuit
AF220/AF210/AF120/AF110
write control pin
MB90F897/S
writ control pin
10KΩ
AF220/AF210/AF120/AF110
/TICS pin
user
626
APPENDIX
The appendices provide the I/O map and outline of
instructions.
APPENDIX A Instructions
APPENDIX B Register Index
APPENDIX C Pin Function Index
APPENDIX D Interrupt Vector Index
627
APPENDIX
APPENDIX A Instructions
APPENDIX A describes the instructions used by the F2MC-16LX.
A.1 Instruction Types
A.2 Addressing
A.3 Direct Addressing
A.4 Indirect Addressing
A.5 Execution Cycle Count
A.6 Effective address field
A.7 How to Read the Instruction List
A.8 F2MC-16LX Instruction List
A.9 Instruction Map
Code: CM44-00202-3E
628
APPENDIX A Instructions
A.1
Instruction Types
The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an
effective address field of each instruction or using the instruction code itself.
■ Instruction Types
The F2MC-16LX supports the following 351 types of instructions:
•
41 transfer instructions (byte)
•
38 transfer instructions (word or long word)
•
42 addition/subtraction instructions (byte, word, or long word)
•
12 increment/decrement instructions (byte, word, or long word)
•
11 comparison instructions (byte, word, or long word)
•
11 unsigned multiplication/division instructions (word or long word)
•
11 signed multiplication/division instructions (word or long word)
•
39 logic instructions (byte or word)
•
6 logic instructions (long word)
•
6 sign inversion instructions (byte or word)
•
1 normalization instruction (long word)
•
18 shift instructions (byte, word, or long word)
•
50 branch instructions
•
6 accumulator operation instructions (byte or word)
•
28 other control instructions (byte, word, or long word)
•
21 bit operation instructions
•
10 string instructions
629
APPENDIX
A.2
Addressing
With the F2MC-16LX, the address format is determined by the instruction effective
address field or the instruction code itself (implied). When the address format is
determined by the instruction code itself, specify an address in accordance with the
instruction code used. Some instructions permit the user to select several types of
addressing.
■ Addressing
The F2MC-16LX supports the following 23 types of addressing:
630
•
Immediate (#imm)
•
Register direct
•
Direct branch address (addr16)
•
Physical direct branch address (addr24)
•
I/O direct (io)
•
Abbreviated direct address (dir)
•
Direct address (addr16)
•
I/O direct bit address (io:bp)
•
Abbreviated direct bit address (dir:bp)
•
Direct bit address (addr16:bp)
•
Vector address (#vct)
•
Register indirect (@RWj j = 0 to 3)
•
Register indirect with post increment (@RWj+ j = 0 to 3)
•
Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
•
Long register indirect with displacement (@RLi + disp8 i = 0 to 3)
•
Program counter indirect with displacement (@PC + disp16)
•
Register indirect with base index (@RW0 + RW7, @RW1 + RW7)
•
Program counter relative branch address (rel)
•
Register list (rlst)
•
Accumulator indirect (@A)
•
Accumulator indirect branch address (@A)
•
Indirectly-specified branch address (@ear)
•
Indirectly-specified branch address (@eam)
APPENDIX A Instructions
■ Effective Address Field
Table A.2-1 lists the address formats specified by the effective address field.
Table A.2-1 Effective Address Field
Code
Representation
00
R0
RW0
RL0
01
R1
RW1
(RL0)
02
R2
RW2
RL1
03
R3
RW3
(RL1)
04
R4
RW4
RL2
05
R5
RW5
(RL2)
06
R6
RW6
RL3
07
R7
RW7
(RL3)
08
@RW0
09
@RW1
Address format
Default bank
Register direct: Individual parts correspond to the
byte, word, and long word types in order from the
left.
None
DTB
DTB
Register indirect
0A
@RW2
ADB
0B
@RW3
SPB
0C
@RW0+
DTB
0D
@RW1+
DTB
Register indirect with post increment
0E
@RW2+
ADB
0F
@RW3+
SPB
10
@RW0+disp8
DTB
11
@RW1+disp8
DTB
Register indirect with 8-bit displacement
12
@RW2+disp8
ADB
13
@RW3+disp8
SPB
14
@RW4+disp8
DTB
15
@RW5+disp8
DTB
Register indirect with 8-bit displacement
16
@RW6+disp8
ADB
17
@RW7+disp8
SPB
18
@RW0+disp16
DTB
19
@RW1+disp16
DTB
Register indirect with 16-bit displacement
1A
@RW2+disp16
ADB
1B
@RW3+disp16
SPB
1C
@RW0+RW7
Register indirect with index
DTB
1D
@RW1+RW7
Register indirect with index
DTB
1E
@PC+disp16
PC indirect with 16-bit displacement
PCB
1F
addr16
Direct address
DTB
631
APPENDIX
A.3
Direct Addressing
An operand value, register, or address is specified explicitly in direct addressing mode.
■ Direct Addressing
● Immediate addressing (#imm)
Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32).
Figure A.3-1 Example of Immediate Addressing (#imm)
MOVW A, #01212H (This instruction stores the operand value in A.)
Before execution
A 2233
4455
After execution
A 4455
1 2 1 2 (Some instructions transfer AL to AH.)
● Register direct addressing
Specify a register explicitly as an operand. Table A.3-1 lists the registers that can be specified. Figure A.3-2
shows an example of register direct addressing.
Table A.3-1 Direct Addressing Registers
General-purpose register
Special-purpose register
Byte
R0, R1, R2, R3, R4, R5, R6, R7
Word
RW0, RW1, RW2, RW3, RW4, RW5, RW6,
RW7
Long word
RL0, RL1, RL2, RL3
Accumulator
A, AL
Pointer
SP *
Bank
PCB, DTB, USB, SSB, ADB
Page
DPR
Control
PS, CCR, RP, ILM
*: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on
the value of the S flag bit in the condition code register (CCR). For branch instructions, the program
counter (PC) is not specified in an instruction operand but is specified implicitly.
632
APPENDIX A Instructions
Figure A.3-2 Example of Register Direct Addressing
MOV R0, A (This instruction transfers the eight low-order bits of A to the generalpurpose register R0.)
Before execution
A 0716
2534
Memory space
R0
After execution
A 0716
2564
??
Memory space
R0
34
● Direct branch addressing (addr16)
Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which
indicates the branch destination in the logical address space. Direct branch addressing is used for an
unconditional branch, subroutine call, or software interrupt instruction. Bit23 to bit16 of the address are
specified by the program counter bank register (PCB).
Figure A.3-3 Example of Direct Branch Addressing (addr16)
JMP 3B20H (This instruction causes an unconditional branch by direct branch
addressing in a bank.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
62
4F3C21H
20
4F3C22H
3B
JMP 3B20H
633
APPENDIX
● Physical direct branch addressing (addr24)
Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical
direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction.
Figure A.3-4 Example of Direct Branch Addressing (addr24)
JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit
addressing.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 3 3
Memory space
333B20H
Next instruction
4F3C20H
63
4F3C21H
20
4F3C22H
3B
4F3C23H
33
JMPP 333B20H
● I/O direct addressing (io)
Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the
physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB)
and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an
instruction using I/O direct addressing.
Figure A.3-5 Example of I/O Direct Addressing (io)
MOVW A, I:0C0H (This instruction reads data by I/O direct addressing and stores it in A.)
Before execution
After execution
A 0716
2534
Memory space
0000C0H
EE
0000C1H
FF
A 2534 FFEE
Note : "I:" is Addressing Specifier that shows the I/O Direct Addressing.
634
APPENDIX A Instructions
● Abbreviated direct addressing (dir)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB).
Figure A.3-6 Example of Abbreviated Direct Addressing (dir)
MOV S:20H, A (This instruction writes the contents of the eight low-order bits of A in
abbreviated direct addressing mode.)
Before execution
A 4455
DPR 6 6
After execution
A 4455
DPR 6 6
1212
DTB 7 7
Memory space
776620H
1212
DTB 7 7
??
Memory space
776620H
12
Note : "S:" is Addressing Specifier that shows the Abbreviated Direct Addressing.
● Direct addressing (addr16)
Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are
specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for
this mode of addressing.
Figure A.3-7 Example of Direct Addressing (addr16)
MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.)
Before execution
After execution
A 2020
A AABB
AABB
0123
DTB 5 5
Memory space
553B21H
01
553B20H
23
DTB 5 5
635
APPENDIX
● I/O direct bit addressing (io:bp)
Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp",
where the larger number indicates the most significant bit (MSB) and the lower number indicates the least
significant bit (LSB).
Figure A.3-8 Example of I/O Direct Bit Addressing (io:bp)
SETB I:0C1H:0 (This instruction sets bits by I/O direct bit addressing.)
Memory space
Before execution
0000C1H
00
Memory space
After execution
0000C1H
01
Note : "I:" is Addressing Specifier that shows the I/O Direct Addressing.
● Abbreviated direct bit addressing (dir:bp)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure A.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp)
SETB S:10H:0 (This instruction sets bits by abbreviated direct bit addressing.)
Memory space
Before execution
DTB 5 5
DPR 6 6
556610H
00
Memory space
After execution
DTB 5 5
DPR 6 6
01
556610H
Note : "S:" is Addressing Specifier that shows the Abbreviated Direct Addressing.
● Direct bit addressing (addr16:bp)
Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure A.3-10 Example of Direct Bit Addressing (addr16:bp)
SETB 2222H : 0 (This instruction sets bits by direct bit addressing.)
Memory space
Before execution
DTB 5 5
552222H
00
Memory space
After execution
636
DTB 5 5
552222H
01
APPENDIX A Instructions
● Vector Addressing (#vct)
Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector
numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction.
Figure A.3-11 Example of Vector Addressing (#vct)
CALLV #15 (This instruction causes a branch to the address indicated by the interrupt
vector specified in an operand.)
Before execution
PC 0 0 0 0
Memory space
PCB F F
After execution
FFC000H
EF
FFFFE0H
00
FFFFE1H
D0
CALLV #15
PC D 0 0 0
PCB F F
Table A.3-2 CALLV Vector List
Instruction
Vector address L
Vector address H
CALLV #0
XXFFFEH
XXFFFFH
CALLV #1
XXFFFCH
XXFFFDH
CALLV #2
XXFFFAH
XXFFFBH
CALLV #3
XXFFF8H
XXFFF9H
CALLV #4
XXFFF6H
XXFFF7H
CALLV #5
XXFFF4H
XXFFF5H
CALLV #6
XXFFF2H
XXFFF3H
CALLV #7
XXFFF0H
XXFFF1H
CALLV #8
XXFFEEH
XXFFEFH
CALLV #9
XXFFECH
XXFFEDH
CALLV #10
XXFFEAH
XXFFEBH
CALLV #11
XXFFE8H
XXFFE9H
CALLV #12
XXFFE6H
XXFFE7H
CALLV #13
XXFFE4H
XXFFE5H
CALLV #14
XXFFE2H
XXFFE3H
CALLV #15
XXFFE0H
XXFFE1H
Note: A PCB register value is set in XX.
Note:
When the program counter bank register (PCB) is FFH, the vector area overlaps the vector area of
INT #vct8 (#0 to #7). Use vector addressing carefully (see Table A.3-2).
637
APPENDIX
A.4
Indirect Addressing
In indirect addressing mode, an address is specified indirectly by the address data of
an operand.
■ Indirect Addressing
● Register indirect addressing (@RWj j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to
23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register
(SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when
RW2 is used.
Figure A.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3)
MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores
it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 0 F
DTB 7 8
● Register indirect addressing with post increment (@RWj+ j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. After operand
operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word).
Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system
stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank
register (ADB) when RW2 is used.
If the post increment results in the address of the register that specifies the increment, the incremented
value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to
writing by an instruction and, therefore, the register that would be incremented becomes write data.
638
APPENDIX A Instructions
Figure A.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3)
MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post
increment and stores it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 1 1
DTB 7 8
● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
Memory is accessed using the address obtained by adding an offset to the contents of general-purpose
register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric
values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or
RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is
used, or additional data bank register (ADB) when RW2 or RW6 is used.
Figure A.4-3 Example of Register Indirect Addressing with Offset
(@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+10H)
RW1 D 3 0 F
After execution
DTB 7 8
Memory space
78D31FH
EE
78D320H
FF
A 2534 FFEE
RW1 D 3 0 F
DTB 7 8
639
APPENDIX
● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the
contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value.
Figure A.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3)
MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+25H)
RL2 F 3 8 2
After execution
4B02
Memory space
824B27H
EE
824B28H
FF
A 2534 FFEE
RL2 F 3 8 2
4B02
● Program counter indirect addressing with offset (@PC + disp16)
Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one
word long. Address bits 16 to 23 are specified by the program counter bank register (PCB). Note that the
operand address of each of the following instructions is not deemed to be (next instruction address +
disp16):
•
DBNZ eam, rel
•
DWBNZ eam, rel
•
CBNE eam, #imm8, rel
•
CWBNE eam, #imm16, rel
•
MOV eam, #imm8
•
MOVW eam, #imm16
Figure A.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16)
MOVW A, @PC+20H (This instruction reads data by program counter indirect
addressing with an offset and stores it in A.)
Before execution
A 0716
2534
Memory space
PCB C 5 PC 4 5 5 6
After execution
A 2534
FFEE
PCB C 5 PC 4 5 5 A
640
+4
C54556H
73
C54557H
9E
C54558H
20
C54559H
00
C5455AH
.
.
.
+20H
C5457AH
EE
C5457BH
FF
MOVW
A, @PC+20H
APPENDIX A Instructions
● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7)
Memory is accessed using the address determined by adding RW0 or RW1 to the contents of generalpurpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB).
Figure A.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7)
MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with
a base index and stores it in A.)
Before execution
A 0716
RW1 D 3 0 F
WR7 0 1 0 1
After execution
A 2534
RW1 D 3 0 F
2534
+
DTB 7 8
Memory space
78D410H
EE
78D411H
FF
FFEE
DTB 7 8
WR7 0 1 0 1
641
APPENDIX
● Program counter relative branch addressing (rel)
The address of the branch destination is a value determined by adding an 8-bit offset to the program
counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is
not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte
bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to
23 are indicated by the program counter bank register (PCB).
Figure A.4-7 Example of Program Counter Relative Branch Addressing (rel)
BRA 3C32H (This instruction causes an unconditional relative branch.)
Before execution
After execution
PC 3 C 2 0
PC 3 C 3 2
PCB 4 F
PCB 4 F
Memory space
4F3C32H
Next instruction
4F3C21H
10
4F3C20H
60
BRA 3C32H
● Register list (rlst)
Specify a register to be pushed onto or popped from a stack.
Figure A.4-8 Configuration of the Register List
MSB
LSB
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
A register is selected when the corresponding bit is 1 and deselected when the bit is 0.
642
APPENDIX A Instructions
Figure A.4-9 Example of Register List (rlst)
POPW RW0, RW4 (This instruction transfers memory data indicated by the SP to
multiple word registers indicated by the register list.)
SP
34FA
SP
34FE
RW0
×× ××
RW0
02 01
RW1
×× ××
RW1
×× ××
RW2
×× ××
RW2
×× ××
RW3
×× ××
RW3
×× ××
RW4
×× ××
RW4
04 03
RW5
×× ××
RW5
×× ××
RW6
×× ××
RW6
×× ××
RW7
×× ××
RW7
×× ××
Memory space
SP
Memory space
01
34FAH
01
34FAH
02
34FBH
02
34FBH
03
34FCH
03
34FCH
04
34FDH
04
34FDH
34FEH
SP
Before execution
34FEH
After execution
● Accumulator indirect addressing (@A)
Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the
accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB).
Figure A.4-10 Example of Accumulator Indirect Addressing (@A)
MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.)
Before execution
A
0716
2534
DTB B B
After execution
A
0716
Memory space
BB2534H
EE
BB2535H
FF
FFEE
DTB B B
643
APPENDIX
● Accumulator indirect branch addressing (@A)
The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the
accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are
specified by the program counter bank register (PCB). For the Jump Context (JCTX) instruction, however,
address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for
unconditional branch instructions.
Figure A.4-11 Example of Accumulator Indirect Branch Addressing (@A)
JMP @A (This instruction causes an unconditional branch by accumulator indirect
branch addressing.)
Before execution
PC 3 C 2 0
A 6677
After execution
PC 3 B 2 0
A 6677
PCB 4 F
3B20
Memory space
4F3B20H
Next instruction
4F3C20H
61
JMP @A
PCB 4 F
3B20
● Indirect specification branch addressing (@ear)
The address of the branch destination is the word data at the address indicated by ear.
Figure A.4-12 Example of Indirect Specification Branch Addressing (@ear)
JMP @@RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
After execution
644
PC 3 C 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
PC 3 B 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
Memory space
217F48H
20
217F49H
3B
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
08
JMP @@RW0
APPENDIX A Instructions
● Indirect specification branch addressing (@eam)
The address of the branch destination is the word data at the address indicated by eam.
Figure A.4-13 Example of Indirect Specification Branch Addressing (@eam)
JMP @RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
PC 3 C 2 0
PCB 4 F
RW0 3 B 2 0
After execution
PC 3 B 2 0
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
00
JMP @RW0
RW0 3 B 2 0
645
APPENDIX
A.5
Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is
obtained by adding the number of cycles required for each instruction, "correction
value" determined by the condition, and the number of cycles for instruction fetch.
■ Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is obtained by adding the
number of cycles required for each instruction, "correction value" determined by the condition, and the
number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal
ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments.
Therefore, intervening in data access increases the execution cycle count.
Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the
program fetches every byte of an instruction being executed. Therefore, intervening in data access increases
the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register,
internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the
cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register.
Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add
the "access count x cycle count for the halt" as a correction value to the normal execution count.
646
APPENDIX A Instructions
■ Calculating the Execution Cycle Count
Table A.5-1 lists execution cycle counts and Table A.5-2 and Table A.5-3 summarize correction value data.
Table A.5-1 Execution Cycle Counts in Each Addressing Mode
(a) *
Code
Operand
00
|
07
Ri
Rwi
RLi
08
|
0B
Execution cycle count in
each addressing mode
Register access count in
each addressing mode
See the instruction list.
See the instruction list.
@RWj
2
1
0C
|
0F
@RWj+
4
2
10
|
17
@RWi+disp8
2
1
18
|
1B
@RWi+disp16
2
1
1C
1D
1E
1F
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
4
4
2
1
2
2
0
0
*: (a) is used for ~ (cycle count) and B (correction value) in "A.8 F2MC-16LX Instruction List".
647
APPENDIX
Table A.5-2 Cycle Count Correction Values for Counting Execution Cycles
(b) byte *
Operand
(c) word *
(d) long *
Cycle
count
Access
count
Cycle
count
Access
count
Cycle
count
Access
count
Internal register
+0
1
+0
1
+0
2
Internal memory
Even address
+0
1
+0
1
+0
2
Internal memory
Odd address
+0
1
+2
2
+4
4
External data bus
16-bit even address
+1
1
+1
1
+2
2
External data bus
16-bit odd address
+1
1
+4
2
+8
4
External data bus
8-bits
+1
1
+4
2
+8
4
*: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in "A.8 F2MC-16LX
Instruction List".
Note:
When an external data bus is used, the cycle counts during which an instruction is made to wait by
ready input or automatic ready must also be added.
Table A.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
-
+2
External data bus 16-bits
-
+3
External data bus 8-bits
+3
-
Notes:
• When an external data bus is used, the cycle counts during which an instruction is made to wait
by ready input or automatic ready must also be added.
• Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the
correction values to calculate the worst case.
648
APPENDIX A Instructions
A.6
Effective address field
Table A.6-1 shows the effective address field.
■ Effective Address Field
Table A.6-1 Effective Address Field
Code
Representation
00
01
02
03
04
05
06
07
08
09
0A
R0
R1
R2
R3
R4
R5
R6
R7
@RW0
@RW1
@RW2
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
0B
0C
0D
0E
0F
10
11
12
13
14
15
@RW3
@RW0+
@RW1+
@RW2+
@RW3+
@RW0+disp8
@RW1+disp8
@RW2+disp8
@RW3+disp8
@RW4+disp8
@RW5+disp8
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Address format
Byte count of
extended
address part *
Register direct: Individual parts correspond to
the byte, word, and long word types in order
from the left.
-
Register indirect
0
Register indirect with post increment
0
Register indirect with 8-bit displacement
1
16
@RW6+disp8
17
@RW7+disp8
18
@RW0+disp16
19
@RW1+disp16
Register indirect with 16-bit displacement
2
1A
@RW2+disp16
1B
@RW3+disp16
1C
@RW0+RW7
Register indirect with index
0
1D
@RW1+RW7
Register indirect with index
0
1E
@PC+disp16
PC indirect with 16-bit displacement
2
1F
addr16
Direct address
2
*1: Each byte count of the extended address part applies to + in the # (byte count) column in "A.8 F2MC-16LX
Instruction List".
649
APPENDIX
A.7
How to Read the Instruction List
Table A.7-1 describes the items used in "A.8 F2MC-16LX Instruction List", and Table
A.7-2 describes the symbols used in the same list.
■ Description of Instruction Presentation Items and Symbols
Table A.7-1 Description of Items in the Instruction List (1/2)
Item
Mnemonic
Uppercase, symbol: Represented as is in the assembler.
Lowercase: Rewritten in the assembler.
Number of following lowercase: Indicates bit length in the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
See Table A.2-1 for the alphabetical letters in items.
RG
B
Operation
650
Description
Indicates the number of times a register access is performed during instruction
execution.
The number is used to calculate the correction value for CPU intermittent
operation.
Indicates the correction value used to calculate the actual number of cycles during
instruction execution.
The actual number of cycles during instruction execution can be determined by
adding the value in the ~ column to this value.
Indicates the instruction operation.
LH
Indicates the special operation for bit15 to bit08 of the accumulator.
Z: Transfers 0.
X: Transfers after sign extension.
-: No transfer
AH
Indicates the special operation for the 16 high-order bits of the accumulator.
*: Transfers from AL to AH.
-: No transfer
Z: Transfers 00 to AH.
X: Transfers 00H or FFH to AH after AL sign extension.
APPENDIX A Instructions
Table A.7-1 Description of Items in the Instruction List (1/2)
Item
Description
I
Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N
(negative), Z (zero), V (overflow), C (carry).
*: Changes upon instruction execution.
-: No change
S: Set upon instruction execution.
R: Reset upon instruction execution.
S
T
N
Z
V
C
RMW
Indicates whether the instruction is a Read Modify Write instruction (reading data
from memory by the I instruction and writing the result to memory).
*: Read Modify Write instruction
-: Not Read Modify Write instruction
Note:
Cannot be used for an address that has different meanings between read and
write operations.
Table A.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
A
Explanation
The bit length used varies depending on the 32-bit accumulator instruction.
Byte: Low-order 8 bits of byte AL
Word: 16 bits of word AL
Long word: 32 bits of AL and AH
AH
16 high-order bits of A
AL
16 low-order bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
program counter bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
651
APPENDIX
Table A.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
Ri
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
Direct addressing
addr24
Physical direct addressing
ad24 0-15
Bit0 to bit15 of addr24
ad24 16-23
Bit16 to bit23 of addr24
io
I/O area (000000H to 0000FFH)
#imm4
4-bit immediate data
#imm8
8-bit immediate data
#imm16
16-bit immediate data
#imm32
32-bit immediate data
ext (imm8)
16-bit data obtained by sign extension of 8-bit immediate data
disp8
8-bit displacement
disp16
16-bit displacement
bp
652
Explanation
Bit offset
vct4
Vector number (0 to 15)
vct8
Vector number (0 to 255)
( )b
Bit address
rel
PC relative branch
ear
Effective addressing (code 00H to 07H)
eam
Effective addressing (code 08H to 1FH)
rlst
Register list
APPENDIX A Instructions
A.8
F2MC-16LX Instruction List
Table A.8-1 to Table A.8-18 list the instructions used by the F2MC-16LX.
■ F2MC-16LX Instruction List
Table A.8-1 41 Transfer Instructions (Byte)
Mnemonic
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
XCH
XCH
XCH
XCH
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RLi+disp8
A,#imm4
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
Ri,A
ear,A
eam,A
io,A
@RLi+disp8,A
Ri,ear
Ri,eam
ear,Ri
eam,Ri
Ri,#imm8
io,#imm8
dir,#imm8
ear,#imm8
eam,#imm8
@AL,AH
A,ear
A,eam
Ri,ear
Ri,eam
#
~
RG
B
2
3
1
2
2+
2
2
2
3
1
2
3
2
2
2+
2
2
2
2
3
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
2
2+
2
2+
3
4
2
2
3 + (a)
3
2
3
10
1
3
4
2
2
3 + (a)
3
2
3
5
10
3
4
2
2
3 + (a)
3
10
3
4 + (a)
4
5 + (a)
2
5
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
0
0
1
1
0
0
0
0
2
0
0
0
1
1
0
0
0
0
1
2
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
2
0
4
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
0
2 × (b)
0
2 × (b)
Operation
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi)+disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
Z
Z
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
Note:
See Table A.5-1 and Table A.5-2 for information on (a) and (b) in the table.
653
APPENDIX
Table A.8-2 38 Transfer Instructions (Word, Long Word)
Mnemonic
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW
XCHW
XCHW
MOVL
MOVL
MOVL
MOVL
MOVL
A,dir
A,addr16
A,SP
A,RWi
A,ear
A,eam
A,io
A,@A
A,#imm16
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
SP,A
RWi,A
ear,A
eam,A
io,A
@RWi+disp8,A
@RLi+disp8,A
RWi,ear
RWi,eam
ear,RWi
eam,RWi
RWi,#imm16
io,#imm16
ear,#imm16
eam,#imm16
@AL,AH
A,ear
A,eam
RWi, ear
RWi, eam
A,ear
A,eam
A,#imm32
ear,A
eam,A
#
~
RG
B
2
3
1
1
2
2+
2
2
3
2
3
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
2
2
2+
2
2+
2
2+
5
2
2+
3
4
1
2
2
3 + (a)
3
3
2
5
10
3
4
1
2
2
3 + (a)
3
5
10
3
4 + (a)
4
5 + (a)
2
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
4
5 + (a)
3
4
5 + (a)
0
0
0
1
1
0
0
0
0
1
2
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
0
2
0
4
2
2
0
0
2
0
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
0
(c)
0
(c)
0
(c)
0
(c)
(c)
0
2 × (c)
0
2 × (c)
0
(d)
0
0
(d)
Operation
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi)+disp8)
word (A) ← ((RLi)+disp8)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
word ((RWi)+disp8) ← (A)
word ((RLi)+disp8) ← (A)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
word (ear) ← imm16
word (eam) ← imm16
word ((A)) ← (AH)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
long (ear) ← (A)
long(eam) ← (A)
LH
AH
I
S
T
N
Z
V
C
RMW
-
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
Note:
See Table A.5-1 and Table A.5-2 for information on (a), (c), and (d) in the table.
654
APPENDIX A Instructions
Table A.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
ADDW
ADDW
ADDW
ADDW
ADDW
ADDW
ADDCW
ADDCW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBCW
SUBCW
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A,ear
A,eam
A,#imm32
A,ear
A,eam
A,#imm32
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
2+
5
2
2+
5
2
3
4+(a)
2
3
5+(a)
3
4+(a)
2
3
4+(a)
2
3
5+(a)
3
4+(a)
6
7+(a)
4
6
7+(a)
4
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
2
0
0
2
0
0
0
0
(c)
0
0
2 × (c)
0
(c)
0
0
(c)
0
0
2 × (c)
0
(c)
0
(d)
0
0
(d)
0
Operation
byte (A) ← (A) + imm8
byte (A) ← (A) + (dir)
byte (A) ← (A) + (ear)
byte (A) ← (A) + (eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear)+ (C)
byte (A) ← (A) + (eam)+ (C)
byte (A) ← (AH) + (AL) + (C)
(decimal)
byte (A) ← (A) - imm8
byte (A) ← (A) - (dir)
byte (A) ← (A) - (ear)
byte (A) ← (A) - (eam)
byte (ear) ← (ear) - (A)
byte (eam) ← (eam) - (A)
byte (A) ← (AH) - (AL) - (C)
byte (A) ← (A) - (ear) - (C)
byte (A) ← (A) - (eam) - (C)
byte (A) ← (AH) - (AL) - (C)
(decimal)
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) - (AL)
word (A) ← (A) - (ear)
word (A) ← (A) - (eam)
word (A) ← (A) - imm16
word (ear) ← (ear) - (A)
word (eam) ← (eam) - (A)
word (A) ← (A) - (ear) - (C)
word (A) ← (A) - (eam) - (C)
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
long (A) ← (A) - (ear)
long (A) ← (A) - (eam)
long (A) ← (A) - imm32
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (d) in the table.
655
APPENDIX
Table A.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
INC
ear
2
3
2
0
INC
eam
2+
5+(a)
0
2 × (b)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
byte (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
byte (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DEC
ear
2
3
2
0
byte (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
DEC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
INCW
ear
2
3
2
0
word (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
INCW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DECW
ear
2
3
2
0
DECW
eam
2+
5+(a)
0
2 × (c)
INCL
ear
2
7
4
0
INCL
eam
2+
9+(a)
0
2 × (d)
DECL
ear
2
7
4
0
DECL
eam
2+
9+(a)
0
2 × (d)
word (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
word (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (d) in the table.
Table A.8-5 11 Compare Instructions (Byte, Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
CMP
Mnemonic
A
1
1
0
0
byte (AH) - (AL)
Operation
-
-
-
-
-
*
*
*
*
-
CMP
A,ear
2
2
1
0
byte (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMP
A,eam
2+
3+(a)
0
(b)
byte (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMP
A,#imm8
2
2
0
0
byte (A) - imm8
-
-
-
-
-
*
*
*
*
-
CMPW
A
1
1
0
0
word (AH) - (AL)
-
-
-
-
-
*
*
*
*
-
CMPW
A,ear
2
2
1
0
word (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPW
A,eam
2+
3+(a)
0
(c)
word (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPW
A,#imm16
3
2
0
0
word (A) - imm16
-
-
-
-
-
*
*
*
*
-
CMPL
A,ear
2
6
2
0
long (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPL
A,eam
2+
7+(a)
0
(d)
long (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPL
A,#imm32
5
3
0
0
long (A) - imm32
-
-
-
-
-
*
*
*
*
-
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (d) in the table.
656
APPENDIX A Instructions
Table A.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIVU
A
1
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
-
-
-
-
-
-
-
*
*
-
DIVU
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
-
-
-
-
-
-
-
*
*
-
DIVU
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MULU
A
1
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
MULU
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A
1
*11
0
0
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
MULUW
A,ear
2
*12
1
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,eam
2+
*13
0
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
*1: 3: Division by 0 7: Overflow 15: Normal
*2: 4: Division by 0 8: Overflow 16: Normal
*3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal
*4: 4: Division by 0 7: Overflow 22: Normal
*5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal
*6: (b): Division by 0 or overflow 2 × (b): Normal
*7: (c): Division by 0 or overflow 2 × (c): Normal
*8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0.
*9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0.
*10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0.
*11: 3: Word (AH) is 0. 11: Word (AH) is not 0.
*12: 4: Word (ear) is 0. 12: Word (ear) is not 0.
*13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0.
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (c) in the table.
657
APPENDIX
Table A.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIV
A
2
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
Z
-
-
-
-
-
-
*
*
-
DIV
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
Z
-
-
-
-
-
-
*
*
-
DIV
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
Z
-
-
-
-
-
-
*
*
-
DIVW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MUL
A
2
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,eam
2+
*10
0
(b)
MULW
A
2
*11
0
0
MULW
A,ear
2
*12
1
MULW
A,eam
2+
*13
0
*1:
*2:
*3:
*4:
3: Division by 0, 8 or 18: Overflow, 18: Normal
4: Division by 0, 11 or 22: Overflow, 23: Normal
5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal
When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal
When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal
*5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal
When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal
*6: (b): Division by 0 or overflow, 2 × (b): Normal
*7: (c): Division by 0 or overflow, 2 × (c): Normal
*8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative
*9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative
*10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative
*11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative
*12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative
*13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative
Notes:
• The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a
pre-operation count or a post-operation count depending on the detection timing.
• When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed.
• See Table A.5-1 and Table A.5-2 for information on (a) to (c) in the table.
658
APPENDIX A Instructions
Table A.8-8 39 Logic 1 Instructions (Byte, Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
AND
A,#imm8
2
2
0
0
byte (A) ← (A) and imm8
-
-
-
-
-
*
*
R
-
AND
A,ear
2
3
1
0
byte (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
AND
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
byte (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
byte (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
AND
ear,A
2
3
2
0
AND
eam,A
2+
5+(a)
0
2 × (b)
OR
A,#imm8
2
2
0
0
byte (A) ← (A) or imm8
-
-
-
-
-
*
*
R
-
-
OR
A,ear
2
3
1
0
byte (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
OR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
OR
ear,A
2
3
2
0
byte (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
OR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XOR
A,#imm8
2
2
0
0
byte (A) ← (A) xor imm8
-
-
-
-
-
*
*
R
-
-
XOR
A,ear
2
3
1
0
byte (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XOR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XOR
ear,A
2
3
2
0
byte (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XOR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOT
A
1
2
0
0
byte (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOT
ear
2
3
2
0
byte (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOT
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
ANDW
A
1
2
0
0
word (A) ← (AH) and (A)
-
-
-
-
-
*
*
R
-
-
ANDW
A,#imm16
3
2
0
0
word (A) ← (A) and imm16
-
-
-
-
-
*
*
R
-
-
ANDW
A,ear
2
3
1
0
word (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
word (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
word (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
0
word (A) ← (AH) or (A)
-
-
-
-
-
*
*
R
-
-
0
word (A) ← (A) or imm16
-
-
-
-
-
*
*
R
-
-
1
0
word (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
4+(a)
0
(c)
word (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
2
3
2
0
word (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XORW
A
1
2
0
0
word (A) ← (AH) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
A,#imm16
3
2
0
0
word (A) ← (A) xor imm16
-
-
-
-
-
*
*
R
-
-
XORW
A,ear
2
3
1
0
word (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
ear,A
2
3
2
0
ANDW
eam,A
2+
5+(a)
0
2 × (c)
ORW
A
1
2
0
ORW
A,#imm16
3
2
0
ORW
A,ear
2
3
ORW
A,eam
2+
ORW
ear,A
ORW
XORW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
XORW
ear,A
2
3
2
0
word (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOTW
A
1
2
0
0
word (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOTW
ear
2
3
2
0
word (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOTW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (c) in the table.
659
APPENDIX
Table A.8-9 6 Logic 2 Instructions (Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
ANDL
A,ear
2
6
2
0
long (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
ORL
A,ear
2
6
2
0
long (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
ORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
XORL
A,ear
2
6
2
0
long (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
Note:
See Table A.5-1 and Table A.5-2 for information on (a) and (d) in the table.
Table A.8-10 6 Sign Inversion Instructions (Byte, Word)
Mnemonic
NEG
A
#
~
RG
B
1
2
0
0
byte (A) ← 0 - (A)
byte (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
byte (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
word (A) ← 0 - (A)
-
-
-
-
-
*
*
*
*
-
NEG
ear
2
3
2
0
NEG
eam
2+
5+(a)
0
2 × (b)
NEGW
A
1
2
0
0
NEGW
ear
2
3
2
0
NEGW
eam
2+
5+(a)
0
2 × (c)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
X
-
-
-
-
*
*
*
*
-
word (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
word (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (c) in the table.
Table A.8-11 1 Normalization Instruction (Long Word)
Mnemonic
NRML
A,R0
#
~
RG
B
2
*1
1
0
Operation
long (A) ← Shift left to the position where '1' is set
for the first time.
byte (R0) ← Shift count at that time
*1: 4 when all accumulators have a value of 0; otherwise, 6+(R0)
660
LH
AH
I
S
T
N
Z
V
C
RMW
-
-
-
-
-
-
*
-
-
-
APPENDIX A Instructions
Table A.8-12 18 Shift Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
RORC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
ear
2
3
2
0
byte (ear) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
*
ROLC
ear
2
3
2
0
byte (ear) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
*
ASR
A,R0
2
*1
1
0
byte (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSR
A,R0
2
*1
1
0
byte (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSL
A,R0
2
*1
1
0
byte (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRW
A
1
2
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSRW
A/SHRW A
1
2
0
0
word (A) ← Logical right shift (A, 1 bit)
-
-
-
-
*
R
*
-
*
-
LSLW
A/SHLW A
1
2
0
0
word (A) ← Logical left shift (A, 1 bit)
-
-
-
-
-
*
*
-
*
-
ASRW
A,R0
2
*1
1
0
word (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRW
A,R0
2
*1
1
0
word (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLW
A,R0
2
*1
1
0
word (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRL
A,R0
2
*2
1
0
long (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRL
A,R0
2
*2
1
0
long (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLL
A,R0
2
*2
1
0
long (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
*1: 6 when R0 is 0; otherwise, 5 + (R0)
*2: 6 when R0 is 0; otherwise, 6 + (R0)
Note:
See Table A.5-1 and Table A.5-2 for information on (a) and (b) in the table.
661
APPENDIX
Table A.8-13 31 Branch 1 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
BZ/BEQ
rel
2
*1
0
0
Branch on (Z) = 1
-
-
-
-
-
-
-
-
-
-
BNZ/
BNE
rel
2
*1
0
0
Branch on (Z) = 0
-
-
-
-
-
-
-
-
-
-
BC/BLO
rel
2
*1
0
0
Branch on (C) = 1
-
-
-
-
-
-
-
-
-
-
BNC/
BHS
rel
2
*1
0
0
Branch on (C) = 0
-
-
-
-
-
-
-
-
-
-
BN
rel
2
*1
0
0
Branch on (N) = 1
-
-
-
-
-
-
-
-
-
-
BP
rel
2
*1
0
0
Branch on (N) = 0
-
-
-
-
-
-
-
-
-
-
BV
rel
2
*1
0
0
Branch on (V) = 1
-
-
-
-
-
-
-
-
-
-
BNV
rel
2
*1
0
0
Branch on (V) = 0
-
-
-
-
-
-
-
-
-
-
BT
rel
2
*1
0
0
Branch on (T) = 1
-
-
-
-
-
-
-
-
-
-
BNT
rel
2
*1
0
0
Branch on (T) = 0
-
-
-
-
-
-
-
-
-
-
BLT
rel
2
*1
0
0
Branch on (V) xor (N) = 1
-
-
-
-
-
-
-
-
-
-
BGE
rel
2
*1
0
0
Branch on (V) xor (N) = 0
-
-
-
-
-
-
-
-
-
-
BLE
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BGT
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BLS
rel
2
*1
0
0
Branch on (C) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BHI
rel
2
*1
0
0
Branch on (C) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BRA
rel
2
*1
0
0
Unconditional branch
-
-
-
-
-
-
-
-
-
-
JMP
@A
1
2
0
0
word (PC) ← (A)
-
-
-
-
-
-
-
-
-
-
JMP
addr16
3
3
0
0
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
JMP
@ear
2
3
1
0
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
JMP
@eam
2+
4+(a)
0
(c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
JMPP
@ear *3
2
5
2
0
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
JMPP
@eam *3
2+
6+(a)
0
(d)
JMPP
addr24
4
4
0
0
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
CALL
@ear *4
2
6
1
(c)
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
CALL
@eam *4
2+
7+(a)
0
2 × (c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
CALL
addr16 *5
3
6
0
(c)
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
CALLV
#vct4 *5
1
7
0
2 × (c)
Vector call instruction
-
-
-
-
-
-
-
-
-
-
CALLP
@ear *6
2
10
2
2 × (c)
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
CALLP
@eam *6
2+
11+(a)
0
*2
CALLP
addr24 *7
4
10
0
2 × (c)
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
*1: 4 when a branch is made; otherwise, 3
*2: 3 × (c) + (b)
*3: Read (word) of branch destination address
*4: W: Save to stack (word) R: Read (word) of branch destination address
*5: Save to stack (word)
*6: W: Save to stack (long word), R: Read (long word) of branch destination address
*7: Save to stack (long word)
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (d) in the table.
662
APPENDIX A Instructions
Table A.8-14 19 Branch 2 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S T N Z V C
RMW
CBNE
A,#imm8,rel
3
*1
0
0
Branch on byte (A) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
A,#imm16,rel
4
*1
0
0
Branch on word (A) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CBNE
ear,#imm8,rel
4
*2
1
0
Branch on byte (ear) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CBNE
eam,#imm8,rel *9
4+
*3
0
(b)
Branch on byte (eam) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
ear,#imm16,rel
5
*4
1
0
Branch on word (ear) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CWBNE
eam,#imm16,rel*9
5+
*3
0
(c)
Branch on word (eam) not equal to imm16
-
-
-
-
-
*
*
*
*
-
DBNZ
ear,rel
3
*5
2
0
byte (ear) ← (ear) - 1, Branch on (ear) not equal to 0
-
-
-
-
-
*
*
*
-
*
DBNZ
eam,rel
3+
*6
2
DWBNZ
ear,rel
3
*5
2
DWBNZ
eam,rel
3+
*6
2
2 × (b) byte (eam) ← (eam) - 1, Branch on (eam) not equal to 0
-
-
-
-
-
*
*
*
-
-
-
-
-
-
*
*
*
-
-
2 × (c) word (eam) ← (eam) - 1, Branch on (eam) not equal to 0
-
-
-
-
-
*
*
*
-
*
0
word (ear) ← (ear) - 1, Branch on (ear) not equal to 0
INT
#vct8
2
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT
addr16
3
16
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INTP
addr24
4
17
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
1
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT9
RETI
LINK
#imm8
UNLINK
1
*8
0
*7
Return from interrupt
-
-
*
*
*
*
*
*
*
-
2
6
0
(c)
Saves the old frame pointer in the stack upon entering the
function, then sets the new frame pointer and reserves the
local pointer area.
-
-
-
-
-
-
-
-
-
-
1
5
0
(c)
Recovers the old frame pointer from the stack upon exiting
the function.
-
-
-
-
-
-
-
-
-
-
RET
*10
1
4
0
(c)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
RETP
*11
1
6
0
(d)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
*1: 5 when a branch is made; otherwise, 4
*2: 13 when a branch is made; otherwise, 12
*3: 7+(a) when a branch is made; otherwise, 6+(a)
*4: 8 when a branch is made; otherwise, 7
*5: 7 when a branch is made; otherwise, 6
*6: 8+(a) when a branch is made; otherwise, 7+(a)
*7: 3 × (b) + 2 × (c) when jumping to the next interruption request; 6 × (c) when returning from the current interruption
*8: 15 when jumping to the next interruption request; 17 when returning from the current interruption
*9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction.
*10: Return from stack (word)
*11: Return from stack (long word)
Note:
See Table A.5-1 and Table A.5-2 for information on (a) to (d) in the table.
663
APPENDIX
Table A.8-15 28 Other Control Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
PUSHW
A
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (A)
-
-
-
-
-
-
-
-
-
-
PUSHW
AH
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (AH)
-
-
-
-
-
-
-
-
-
-
PUSHW
PS
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (PS)
-
-
-
-
-
-
-
-
-
-
PUSHW
rlst
2
*3
*5
*4
(SP) ← (SP) - 2n, ((SP)) ← (rlst)
-
-
-
-
-
-
-
-
-
-
POPW
A
1
3
0
(c)
word (A) ← ((SP)), (SP) ← (SP) + 2
-
*
-
-
-
-
-
-
-
-
POPW
AH
1
3
0
(c)
word (AH) ← ((SP)), (SP) ← (SP) + 2
-
-
-
-
-
-
-
-
-
-
POPW
PS
1
4
0
(c)
word (PS) ← ((SP)), (SP) ← (SP) + 2
-
-
*
*
*
*
*
*
*
-
POPW
rlst
2
*2
*5
*4
(rlst) ← ((SP)), (SP) ← (SP) + 2n
-
-
-
-
-
-
-
-
-
-
JCTX
@A
1
14
0
6 × (c)
Context switch instruction
-
-
*
*
*
*
*
*
*
-
AND
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) and imm8
-
-
*
*
*
*
*
*
*
-
OR
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) or imm8
-
-
*
*
*
*
*
*
*
-
MOV
RP,#imm8
2
2
0
0
byte (RP) ← imm8
-
-
-
-
-
-
-
-
-
-
MOV
ILM,#imm8
2
2
0
0
byte (ILM) ← imm8
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,ear
2
3
1
0
word (RWi) ← ear
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,eam
2+
2+(a)
1
0
word (RWi) ← eam
-
-
-
-
-
-
-
-
-
-
MOVEA
A,ear
2
1
0
0
word (A) ← ear
-
*
-
-
-
-
-
-
-
-
MOVEA
A,eam
2+
1+(a)
0
0
word (A) ← eam
-
*
-
-
-
-
-
-
-
-
ADDSP
#imm8
2
3
0
0
word (SP) ← (SP) + ext(imm8)
-
-
-
-
-
-
-
-
-
-
ADDSP
#imm16
3
3
0
0
word (SP) ← (SP) + imm16
-
-
-
-
-
-
-
-
-
-
MOV
A,brg1
2
*1
0
0
byte (A) ← (brg1)
Z
*
-
-
-
*
*
-
-
-
MOV
brg2,A
-
2
1
0
0
byte (brg2) ← (A)
-
-
-
-
-
*
*
-
-
NOP
1
1
0
0
No operation
-
-
-
-
-
-
-
-
-
-
ADB
1
1
0
0
Prefix code for AD space access
-
-
-
-
-
-
-
-
-
-
DTB
1
1
0
0
Prefix code for DT space access
-
-
-
-
-
-
-
-
-
-
PCB
1
1
0
0
Prefix code for PC space access
-
-
-
-
-
-
-
-
-
-
SPB
1
1
0
0
Prefix code for SP space access
-
-
-
-
-
-
-
-
-
-
NCC
1
1
0
0
Prefix code for flag no-change
-
-
-
-
-
-
-
-
-
-
CMR
1
1
0
0
Prefix code for common register bank
-
-
-
-
-
-
-
-
-
-
*1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2
*2: 7 + 3 × (POP count) + 2 × (POP last register number), 7 when RLST = 0 (no transfer register)
*3: 29 + 3 × (PUSH count) - 3 × (PUSH last register number), 8 when RLST = 0 (no transfer register)
*4: (POP count) × (c) or (PUSH count) × (c)
*5: (POP count) or (PUSH count)
Note:
See Table A.5-1 and Table A.5-2 for information on (a) and (c) in the table.
664
APPENDIX A Instructions
Table A.8-16 21 Bit Operand Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
MOVB
A,dir:bp
3
5
0
(b)
byte (A) ← (dir:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,addr16:bp
4
5
0
(b)
byte (A) ← (addr16:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,io:bp
3
4
0
(b)
byte (A) ← (io:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
dir:bp,A
3
7
0
2 × (b)
bit (dir:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
addr16:bp,A
4
7
0
2 × (b)
bit (addr16:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
io:bp,A
3
6
0
2 × (b)
bit (io:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
SETB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
*
CLRB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 0
-
-
-
-
-
-
-
-
-
CLRB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
CLRB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
BBC
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
io:bp,rel
4
*2
0
(b)
Branch on (io:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBS
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
io:bp,rel
4
*2
0
(b)
SBBS
addr16:bp,rel
5
*3
0
2 × (b)
Branch on (io:bp) b = 1
-
-
-
-
-
-
*
-
-
-
Branch on (addr16:bp) b = 1,
bit (addr16:bp) b ← 1
-
-
-
-
-
-
*
-
-
*
WBTS
io:bp
3
*4
0
WBTC
io:bp
3
*4
0
*5
Waits until (io:bp) b = 1
-
-
-
-
-
-
-
-
-
-
*5
Waits until (io:bp) b = 0
-
-
-
-
-
-
-
-
-
-
RMW
*1: 8 when a branch is made; otherwise, 7
*2: 7 when a branch is made; otherwise, 6
*3: 10 when the condition is met; otherwise, 9
*4: Undefined count
*5: Until the condition is met
Note:
See Table A.5-1 and Table A.5-2 for information on (b) in the table.
Table A.8-17 6 Accumulator Operation Instructions (Byte, Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
SWAP
Mnemonic
1
3
0
0
byte (A)0-7 ↔ (A)8-15
Operation
-
-
-
-
-
-
-
-
-
-
SWAPW
1
2
0
0
word (AH) ↔ (AL)
-
*
-
-
-
-
-
-
-
-
EXT
1
1
0
0
Byte sign extension
X
-
-
-
-
*
*
-
-
-
EXTW
1
2
0
0
Word sign extension
-
X
-
-
-
*
*
-
-
-
ZEXT
1
1
0
0
Byte zero extension
Z
-
-
-
-
R
*
-
-
-
ZEXTW
1
1
0
0
Word zero extension
-
Z
-
-
-
R
*
-
-
-
665
APPENDIX
Table A.8-18 10 String Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
MOVS / MOVSI
2
*2
*5
*3
byte transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
MOVSD
2
*2
*5
*3
byte transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCEQ / SCEQI
2
*1
*8
*4
byte search @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCEQD
2
*1
*8
*4
byte search @AH- ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
FILS / FILSI
2
6m+6
*8
*3
byte fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
MOVSW / MOVSWI
2
*2
*5
*6
word transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
-
MOVSWD
2
*2
*5
*6
word transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCWEQ / SCWEQI
2
*1
*8
*7
word search @AH+ - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCWEQD
2
*1
*8
*7
word search @AH- - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
FILSW / FILSWI
2
6m+6
*8
*6
word fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
*1: 5 when RW0 is 0, 4 + 7 × (RW0) when the counter expires, or 7n + 5 when a match occurs
*2: 5 when RW0 is 0; otherwise, 4 + 8 × (RW0)
*3: (b) × (RW0) + (b) × (RW0) When the source and destination access different areas, calculate the (b) item individually.
*4: (b) × n
*5: 2 × (b) × (RW0)
*6: (c) × (RW0) + (c) × (RW0) When the source and destination access different areas, calculate the (c) item individually.
*7: (c) × n
*8: (b) × (RW0)
Note:
m: RW0 value (counter value), n: Loop count
See Table A.5-1 and Table A.5-2 for information on (b) and (c) in the table.
666
APPENDIX A Instructions
A.9
Instruction Map
Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction
map consists of multiple pages. Table A.9-2 to Table A.9-21 summarize the F2MC-16LX
instruction map.
■ Structure of Instruction Map
Figure A.9-1 Structure of Instruction Map
Basic page map
Bit operation
instructions
Character string
operation
instructions
2-byte
instructions
: Byte 1
ea instructions × 9 : Byte 2
An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An
instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it
references byte 1, and can check the following one byte by referencing the map for byte 2. Figure A.9-2
shows the correspondence between an actual instruction code and instruction map.
667
APPENDIX
Figure A.9-2 Correspondence between Actual Instruction Code and Instruction Map
Some instructions do
not contain byte 2.
Instruction
code
Length varies
depending on the
instruction.
Byte 1
Byte 2
Operand
Operand
...
[Basic page map]
XY
+Z
[Extended page map]*
UV
+W
*: The extended page map is a generic name of maps for bit operation instructions, character
string operation instructions, 2-byte instructions, and ea instructions. Actually, there are
multiple extended page maps for each type of instructions.
An example of an instruction code is shown in Table A.9-1.
Table A.9-1 Example of an Instruction Code
Byte 1
(from basic page map)
Byte 2
(from extended page map)
NOP
00 +0=00
-
AND A, #8
30 +4=34
-
MOV A, ADB
60 +F=6F
00 +0=00
CBNE @RW2+d8, #8, rel
70 +0=70
F0 +2=F2
Instruction
668
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
A
ZEXT
SWAP
ADDSP
DTB
ADB
SPB
#8
A, #8
dir, A
A, dir
io, A
A, io
JMP
BRA
60
MULU
DIVU
ea
@A instruction 2
A
MOVW
MOVX
RET
SP, A A, addr16
A0
B0
C0
ea
instruction 8
D0
E0
F0
rel
LSRW
ASRW
LSLW
SWAPW
ZEXTW
XORW
ORW
ANDW
ORW
PUSHW
POPW
A, #16
AH
AH
MOVW
ea, RWi
Bit operation MOV
A instruction
ea, Ri
MOVW
RWi, ea
PUSHW
POPW
2-byte
XCHW
A
rlst
rlst instruction
RWi, ea
Character
XORW
PUSHW
POPW
XCH
operation
A
A, #16
PS
PS string
Ri, ea
instruction
A
ANDW
PUSHW
POPW
A
A, #16
A
CMPW
MOVL
MOVW
RETI
A, #16
A, #32 addr16, A
ADDSP
MULUW
NOTW
A
#16
A
A
A
EXTW
A
BHI
BLS
BGT
BLE
rel
rel
rel
rel
rel
BGE
CMPL
CMPW
A, #32
NEGW
A
rel
BLT
rel
rel
rel
rel
rel
MOV
MOV
CBNE A, CWBNE A, MOVW
MOVW
INTP
MOV
RP, #8
ILM, #8
#8, rel
#16, rel
A, #16 A,addr16
addr24
Ri, ea
BT
BNV
BV
BP
BN
BNC/BHS
rel
BC/BLO
BNZ/BNE
rel
rel
ADDW
MOVW
MOVW
INT
ea
MOVW
MOVW
MOVW
MOVW A, MOVW
A, #16
A, dir
A, io
#vct8 instruction 9
A, RWi
RWi, A RWi, #16 @RWi+d8 @RWi+d8, A
NOT
ea
instruction 7
MOVX
MOVX
CALLP
ea
A, dir
A, io
addr24 instruction 6
MOVW
MOVW
RETP
A, #8
A, SP
io, #16
A, #8
90
BNT
SUBL
SUBW
A, #32
A
A
A
XOR
OR
OR
CCR, #8
80
ea
MOV
MOV
MOV
MOVX
MOVX A, MOVN
CALL
BZ/BEQ
rel instruction 1
A, Ri
Ri, A
Ri, #8
A, Ri @RWi+d8
A, #4
#vct4
rel
70
MOV
JMP
ea
A, addr16
addr16 instruction 3
MOV
MOV
50
MOVX
MOV
JMPP
ea
A, #8
A, #8 addr16, A
addr24 instruction 4
MOV
MOV
MOV
40
SUBW
MOVW
MOVW
INT
MOVEA
A
A, #16
dir, A
io, A
addr16
RWi, ea
UNLINK
A
CMP
A
A, #8
A, #8
SUBC
SUB
ADD
30
AND
AND
MOV
MOV
CALL
ea
CCR, #8
A, #8
dir, #8
io, #8
addr16 instruction 5
CMP
A
A, dir
A, dir
ADDC
SUB
ADD
20
LINK
ADDL
ADDW
#imm8
A, #32
EXT
@A
PCB
A
JCTX
SUBDC
ADDDC
NEG
NCC
INT9
A
CMR
10
NOP
00
APPENDIX A Instructions
Table A.9-2 Basic Page Map
669
670
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
10
MOVB
io:bp, A
20
30
CLRB
io:bp
40
50
SETB
io:bp
60
70
BBC
io;bp, rel
80
90
BBS
io:bp, rel
A0
B0
MOVB
MOVB A, MOVB
MOVB
CLRB
CLRB
SETB
SETB
BBC
BBC
BBS
BBS
A, dir:bp addr16:bp
dir:bp, A addr16:bp,A
dir:bp addr16:bp
dir:bp addr16:bp dir:bp, rel addr16:bp,rel dir:bp, rel addr16:bp,rel
MOVB
A, io:bp
00
WBTS
io:bp
C0
D0
WBTC
io:bp
E0
SBBS
addr16:bp
F0
APPENDIX
Table A.9-3 Bit Operation Instruction Map (First Byte = 6CH)
MOVSI
MOVSD
PCB, PCB
PCB, DTB
PCB, ADB
PCB, SPB
DTB, PCB
DTB, DTB
DTB, ADB
DTB, SPB
ADB, PCB
ADB, DTB
ADB, ADB
ADB, SPB
SPB, PCB
SPB, DTB
SPB, ADB
SPB, SPB
+1
+2
+3
+4
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
10
+0
00
MOVSWI
20
MOVSWD
30
40
50
60
70
90
A0
B0
C0
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SCEQI
SCEQD
SCWEQI SCWEQD FILSI
PCB
PCB
PCB
PCB
PCB
80
D0
SPB
ADB
DTB
FILSWI
PCB
E0
F0
APPENDIX A Instructions
Table A.9-4 Character String Operation Instruction Map (First Byte = 6EH)
671
672
LSLW
LSLL
LSL
MOVW
MOVW
A, R0
A, R0
A, R0 @RL2+d8, A A, @RL2+d8
MOVW
MOVW
NRML
A, @A @AL, AH
A, R0
ASRW
ASRL
ASR
MOVW
MOVW
A, R0
A, R0
A, R0 @RL3+d8, A A, @RL3+d8
LSRW
LSRL
LSR
A, R0
A, R0
A, R0
+D
+E
+F
MOVW
MOVW
@RL1+d8, A A, @RL1+d8
MOVW
MOVW
@RL0+d8, A A, @RL0+d8
+C
+B
+A
+9
+8
A
MOV
MOV
MOVX
MOV
MOV
A, PCB
A, @A A, @RL3+d8 @RL3+d8, A A, @RL3+d8
+6
ROLC
MOV
MOV
A, @A @AL, AH
+5
A
MOV
MOV
MOVX
MOV
MOV
A, DPR
DPR, A A, @RL2+d8 @RL2+d8, A A, @RL2+d8
+4
ROLC
MOV
MOV
A, USB
USB, A
+3
+7
MOV
MOV
MOVX
MOV
MOV
A, SSB
SSB, A A, @RL1+d8 @RL1+d8, A A, @RL1+d8
+2
40
MOV
MOV
A, ADB
ADB, A
30
+1
20
MOV
MOV
MOVX
MOV
MOV
A, DTB
DTB, A A, @RL0+d8 @RL0+d8, A A, @RL0+d8
10
+0
00
50
60
DIV
MULW
MUL
70
A
A
A
80
90
A0
B0
C0
D0
E0
F0
APPENDIX
Table A.9-5 2-byte Instruction Map (First Byte = 6FH)
50
90
B0
D0
@RW1, @RW1+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
@RW2, @RW2+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
@RW3, @RW3+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
SUBL
SUBL A,
A, RL2 @RW5+d8
SUBL
SUBL A,
A, RL3 @RW6+d8
SUBL
SUBL A,
A, RL3 @RW7+d8
ADDL
ADDL A,
A, RL2 @RW5+d8
ADDL
ADDL A,
A, RL3 @RW6+d8
ADDL
ADDL A,
A, RL3 @RW7+d8
ADDL
ADDL A, SUBL
SUBL A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ADDL
ADDL A, SUBL
SUBL A, Use
@RW0+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW0+RW7,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
#16, rel A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
#8, rel
ADDL
ADDL A, SUBL
SUBL A, Use
@RW1+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW1+RW7,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
#16, rel A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
#8, rel
ADDL
ADDL A,
A,@RW2+ @PC+d16
ADDL
ADDL A, SUBL
SUBL A, Use
A,@RW3+
addr16 A,@RW3+
addr16 prohibited
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
SUBL
SUBL A,
A,@RW2+ @PC+d16
@RW0, @RW0+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
SUBL
SUBL A,
A, RL2 @RW4+d8
Use
prohibited
ANDL
ANDL A,
A,@RW2+ @PC+d16
ANDL
ANDL A,
A, RL3 @RW7+d8
ANDL
ANDL A,
A, RL3 @RW6+d8
ANDL
ANDL A,
A, RL2 @RW5+d8
ANDL
ANDL A,
A, RL2 @RW4+d8
ORL
ORL A,
A,@RW2+ @PC+d16
ORL
ORL A,
A, RL3 @RW7+d8
ORL
ORL A,
A, RL3 @RW6+d8
ORL
ORL A,
A, RL2 @RW5+d8
ORL
ORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A,@RW2+ @PC+d16
XORL
XORL A,
A, RL3 @RW7+d8
XORL
XORL A,
A, RL3 @RW6+d8
XORL
XORL A,
A, RL2 @RW5+d8
XORL
XORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A, RL1 @RW3+d8
addr16,
#8, rel
Use
@PC+d16,
prohibited
#8, rel
@RW3, @RW3+d16,
#8, rel
#8, rel
@RW2, @RW2+d16,
#8, rel
#8, rel
@RW1, @RW1+d16,
#8, rel
#8, rel
@RW0, @RW0+d16,
#8, rel
#8, rel
R7, @RW7+d8,
#8, rel
#8, rel
R6, @RW6+d8,
#8, rel
#8, rel
R5, @RW5+d8,
#8, rel
#8, rel
R4, @RW4+d8,
#8, rel
#8, rel
R3, @RW3+d8,
#8, rel
#8, rel
addr16, CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
#16, rel A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 prohibited
@PC+d16, CMPL
CMPL A,
#16, rel A,@RW2+ @PC+d16
RW7, @RW7+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW7+d8
RW6, @RW6+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW6+d8
RW5, @RW5+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW5+d8
RW4, @RW4+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW4+d8
ORL
ORL A,
A, RL1 @RW3+d8
R2, @RW2+d8,
#8, rel
#8, rel
R1, @RW1+d8,
#8, rel
#8, rel
ADDL
ADDL A,
A, RL2 @RW4+d8
ANDL
ANDL A,
A, RL1 @RW3+d8
XORL
XORL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW1+d8
+4
RW3, @RW3+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW3+d8
ORL
ORL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW1+d8
SUBL
SUBL A,
A, RL1 @RW3+d8
ANDL
ANDL A,
A, RL1 @RW2+d8
ANDL
ANDL A,
A, RL0 @RW1+d8
ADDL
ADDL A,
A, RL1 @RW3+d8
RW2, @RW2+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW2+d8
RW1, @RW1+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW1+d8
+3
CBNE ↓
F0
R0, @RW0+d8,
#8, rel
#8, rel
CBNE ↓
E0
SUBL
SUBL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW0+d8
C0
ADDL
ADDL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW0+d8
A0
+2
ANDL
ANDL A,
A, RL0 @RW0+d8
80
SUBL
SUBL A,
A, RL0 @RW1+d8
70
ADDL
ADDL A,
A, RL0 @RW1+d8
60
RW0, @RW0+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW0+d8
CWBNE ↓ CWBNE ↓
40
+1
30
+0
20
SUBL
SUBL A,
A, RL0 @RW0+d8
10
ADDL
ADDL A,
A, RL0 @RW0+d8
00
APPENDIX A Instructions
Table A.9-6 ea Instruction 1 (First Byte = 70H)
673
674
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW7+d8
@RL3 @@RW7+d8
RL3 @RW7+d8
RL3 @RW7+d8
A, RL3 @RW7+d8
RL3, A @RW7+d8,A
R7, #8 @RW7+d8,#8
A, RW7 @RW7+d8
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #8 @RW0+d16,#8
A,@RW0 @RW0+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1,A @RW1+d16,A @RW1, #8 @RW1+d16,#8
A,@RW1 @RW1+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2,A @RW2+d16,A @RW2, #8 @RW2+d16,#8
A,@RW2 @RW2+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3,A @RW3+d16,A @RW3, #8 @RW3+d16,#8
A,@RW3 @RW3+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+,A @RW0+RW7,A @RW0+, #8 @RW0+RW7,#8 A,@RW0+ @RW0+RW7
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+,A @RW1+RW7,A @RW1+, #8 @RW1+RW7,#8 A,@RW1+ @RW1+RW7
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+,A @PC+d16, A @RW2+, #8 @PC+d16, #8 A,@RW2+ @PC+d16
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+,A
addr16, A @RW3+, #8
addr16, #8 A,@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW6+d8
@RL3 @@RW6+d8
RL3 @RW6+d8
RL3 @RW6+d8
A, RL3 @RW6+d8
RL3, A @RW6+d8,A
R6, #8 @RW6+d8,#8
A, RW6 @RW6+d8
D0
+6
C0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW5+d8
@RL2 @@RW5+d8
RL2 @RW5+d8
RL2 @RW5+d8
A, RL2 @RW5+d8
RL2, A @RW5+d8,A
R5, #8 @RW5+d8,#8
A, RW5 @RW5+d8
B0
+5
A0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW4+d8
@RL2 @@RW4+d8
RL2 @RW4+d8
RL2 @RW4+d8
A, RL2 @RW4+d8
RL2, A @RW4+d8,A
R4, #8 @RW4+d8,#8
A, RW4 @RW4+d8
90
+4
80
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW3+d8
@RL1 @@RW3+d8
RL1 @RW3+d8
RL1 @RW3+d8
A, RL1 @RW3+d8
RL1, A @RW3+d8,A
R3, #8 @RW3+d8,#8
A, RW3 @RW3+d8
70
+3
60
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW2+d8
@RL1 @@RW2+d8
RL1 @RW2+d8
RL1 @RW2+d8
A, RL1 @RW2+d8
RL1, A @RW2+d8,A
R2, #8 @RW2+d8,#8
A, RW2 @RW2+d8
50
+2
40
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW1+d8
@RL0 @@RW1+d8
RL0 @RW1+d8
RL0 @RW1+d8
A, RL0 @RW1+d8
RL0, A @RW1+d8,A
R1, #8 @RW1+d8,#8
A, RW1 @RW1+d8
30
+1
20
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW0+d8
@RL0 @@RW0+d8
RL0 @RW0+d8
RL0 @RW0+d8
A, RL0 @RW0+d8
RL0, A @RW0+d8,A
R0, #8 @RW0+d8,#8
A, RW0 @RW0+d8
10
+0
00
APPENDIX
Table A.9-7 ea Instruction 2 (First Byte = 71H)
D0
E0
F0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A A,@RW3+
addr16 A,@RW3+
addr16
+D
+E
+F
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R7 @RW7+d8
A, R7 @RW7+d8
R7, A @RW7+d8,A
A, R7 @RW7+d8
A, R7 @RW7+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R6 @RW6+d8
A, R6 @RW6+d8
R6, A @RW6+d8,A
A, R6 @RW6+d8
A, R6 @RW6+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R5 @RW5+d8
A, R5 @RW5+d8
R5, A @RW5+d8,A
A, R5 @RW5+d8
A, R5 @RW5+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R4 @RW4+d8
A, R4 @RW4+d8
R4, A @RW4+d8,A
A, R4 @RW4+d8
A, R4 @RW4+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R3 @RW3+d8
A, R3 @RW3+d8
R3, A @RW3+d8,A
A, R3 @RW3+d8
A, R3 @RW3+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R2 @RW2+d8
A, R2 @RW2+d8
R2, A @RW2+d8,A
A, R2 @RW2+d8
A, R2 @RW2+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R1 @RW1+d8
A, R1 @RW1+d8
R1, A @RW1+d8,A
A, R1 @RW1+d8
A, R1 @RW1+d8
+C
INC
DEC
R7 @RW7+d8
C0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ROLC
RORC
RORC
INC
R7 @RW7+d8
R7 @RW7+d8
ROLC
INC
DEC
R6 @RW6+d8
B0
+B
ROLC
RORC
RORC
INC
R6 @RW6+d8
R6 @RW6+d8
ROLC
INC
DEC
R5 @RW5+d8
A0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ROLC
RORC
RORC
INC
R5 @RW5+d8
R5 @RW5+d8
ROLC
INC
DEC
R4 @RW4+d8
90
+A
ROLC
RORC
RORC
INC
R4 @RW4+d8
R4 @RW4+d8
ROLC
INC
DEC
R3 @RW3+d8
INC
DEC
R2 @RW2+d8
INC
DEC
R1 @RW1+d8
80
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R0 @RW0+d8
A, R0 @RW0+d8
R0, A @RW0+d8,A
A, R0 @RW0+d8
A, R0 @RW0+d8
70
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ROLC
RORC
RORC
INC
R3 @RW3+d8
R3 @RW3+d8
ROLC
60
INC
DEC
R0 @RW0+d8
50
+9
ROLC
RORC
RORC
INC
R2 @RW2+d8
R2 @RW2+d8
ROLC
40
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0, A @RW0+d16,A
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ROLC
RORC
RORC
INC
R1 @RW1+d8
R1 @RW1+d8
ROLC
30
ROLC
RORC
RORC
INC
R0 @RW0+d8
R0 @RW0+d8
20
ROLC
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX A Instructions
Table A.9-8 ea Instruction 3 (First Byte = 72H)
675
676
JMP
JMP @
CALL
CALL @
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16 @RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, #16 @RW3+d16,#16 A,@RW3 @RW3+d16
+B
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A @RW2+, #16 @PC+d16, #16 A,@RW2+ @PC+d16
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A @RW3+, #16
addr16, #16 A,@RW3+
addr16
INCW
+F
INCW
JMP
JMP
CALL
CALL
INCW
INCW
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16 @RW2+ @PC+d16
CALL @
+E
CALL
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, #16 @RW1+RW7,#16 A,@RW1+ @RW1+RW7
XCHW
XCHW A,
A, RW7 @RW7+d8
XCHW
XCHW A,
A, RW6 @RW6+d8
XCHW
XCHW A,
A, RW5 @RW5+d8
+D @@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7
INCW
MOVW
MOVW
RW7, #16 @RW7+d8,#16
MOVW
MOVW
RW6, #16 @RW6+d8,#16
MOVW
MOVW
RW5, #16 @RW5+d8,#16
XCHW
XCHW A,
A, RW4 @RW4+d8
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, #16 @RW0+RW7,#16 A,@RW0+ @RW0+RW7
INCW
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW7 @RW7+d8
RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, A @RW7+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW6 @RW6+d8
RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, A @RW6+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW5 @RW5+d8
RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, A @RW5+d8,A
MOVW
MOVW
RW4, #16 @RW4+d8,#16
+C @@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7
JMP @
JMP
JMP @
CALL
CALL @
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16 @RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, #16 @RW2+d16,#16 A,@RW2 @RW2+d16
+A
JMP
JMP
JMP @
CALL
CALL @
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16 @RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, #16 @RW1+d16,#16 A,@RW1 @RW1+d16
+9
CALL @
JMP
JMP @
CALL
CALL @
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16 @RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #16 @RW0+d16,#16 A,@RW0 @RW0+d16
+8
CALL
CALL
CALL
@RW7 @@RW7+d8
JMP
JMP
@RW7 @@RW7+d8
+7
JMP @
CALL
CALL
@RW6 @@RW6+d8
JMP
JMP
@RW6 @@RW6+d8
+6
JMP
CALL
CALL
@RW5 @@RW5+d8
JMP
JMP
@RW5 @@RW5+d8
+5
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW4 @RW4+d8
RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, A @RW4+d8,A
XCHW
XCHW A,
A, RW3 @RW3+d8
XCHW
XCHW A,
A, RW2 @RW2+d8
XCHW
XCHW A,
A, RW1 @RW1+d8
CALL
CALL
@RW4 @@RW4+d8
MOVW
MOVW
RW3, #16 @RW3+d8,#16
MOVW
MOVW
RW2, #16 @RW2+d8,#16
MOVW
MOVW
RW1, #16 @RW1+d8,#16
JMP
JMP
@RW4 @@RW4+d8
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW3 @RW3+d8
RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, A @RW3+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW2 @RW2+d8
RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, A @RW2+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW1 @RW1+d8
RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, A @RW1+d8,A
+4
F0
XCHW
XCHW A,
A, RW0 @RW0+d8
E0
CALL
CALL
@RW3 @@RW3+d8
D0
MOVW
MOVW
RW0, #16 @RW0+d8,#16
C0
JMP
JMP
@RW3 @@RW3+d8
B0
+3
A0
CALL
CALL
@RW2 @@RW2+d8
90
JMP
JMP
@RW2 @@RW2+d8
80
+2
70
CALL
CALL
@RW1 @@RW1+d8
60
JMP
JMP
@RW1 @@RW1+d8
50
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW0 @RW0+d8
RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, A @RW0+d8,A
40
+1
30
CALL
CALL
@RW0 @@RW0+d8
20
JMP
JMP
@RW0 @@RW0+d8
10
+0
00
APPENDIX
Table A.9-9 ea Instruction 4 (First Byte = 73H)
ADD
A, SUB
SUB
SUB
ADDC
A, ADDC
A,
ADDC
ADDC A,
A, CMP
CMP
CMP
CMP
A,
A,
A, AND
AND
AND
AND
AND
AND
A,
A,
DBNZ @PC
A, OR
OR
A, XOR
XOR
A, DBNZ
+d16, rel
A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, rel
+F A,@RW3+
ADD
ADD
SUB
SUB
ADDC
ADDC
CMP
CMP
AND
AND
OR
OR
XOR
XOR
DBNZ
DBNZ
A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+
A, addr16 A,@RW3+ A, addr16 @RW3+, rel addr16, rel
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ADD
SUB
CMP
DBNZ @RW1
XOR
XOR A,
DBNZ
+RW7, rel
A,@RW1+ @RW1+RW7 @RW1+, rel
A,
CMP
OR
OR
A,
A,@RW1+ @RW1+RW7
ADD
ADD
ADDC A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ADDC
XOR
XOR A,
DBNZ
DBNZ @RW0
+RW7, rel
A,@RW0+ @RW0+RW7 @RW0+, rel
A,
OR
OR
A,
A,@RW0+ @RW0+RW7
SUB
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
SUB
DBNZ @RW3
XOR
XOR
A, DBNZ
@RW3, rel
+d16, rel
A,@RW3 @RW3+d16
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
A,
DBNZ @RW2
XOR
XOR
A, DBNZ
@RW2, rel
+d16, rel
A,@RW2 @RW2+d16
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
ADD
DBNZ @RW1
XOR
XOR
A, DBNZ
@RW1, rel
+d16, rel
A,@RW1 @RW1+d16
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADD
DBNZ @RW0
XOR
XOR
A, DBNZ
@RW0, rel
+d16, rel
A,@RW0 @RW0+d16
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @RW7
+d8, rel
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
R7, rel
ADD
F0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @RW6
+d8, rel
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
R6, rel
E0
ADD
D0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @RW5
+d8, rel
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
R5, rel
C0
ADD
B0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @RW4
+d8, rel
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
R4, rel
A0
ADD
90
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @RW3
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
R3, rel +d8, rel
80
ADD
70
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @RW2
+d8, rel
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
R2, rel
60
ADD
50
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @RW1
+d8, rel
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
R1, rel
40
ADD
30
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @RW0
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
R0, rel +d8, rel
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX A Instructions
Table A.9-10 ea Instruction 5 (First Byte = 74H)
677
678
NOT
NOT
R2 @RW2+d8
SUB
SUB
SUB
SUB
ADD
SUB
SUB
@RW1+RW7,A @RW1+, A @RW1+RW7,A
ADD @R
@RW0+RW7,A @RW0+, A @RW0+RW7,A
ADD @R
+F
ADD
ADD
@RW3+, A addr16, A
SUB
SUB
@RW3+, A addr16, A
+E @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
ADD
+D @RW1+, A
ADD
+C @RW0+, A
ADD
NOT
NOT
@RW1+ @RW1+RW7
NOT
NOT
@RW0+ @RW0+RW7
SUBC
SUBC A, NEG
NEG
AND
AND
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
OR
OR
@RW3+, A addr16, A
XOR
XOR
@RW3+, A addr16, A
NOT
NOT
@RW3+
addr16
SUBC
SUBC A, NEG
NEG
AND
AND
OR
OR
XOR
XOR
NOT
NOT
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+ @PC+d16
SUBC
SUBC A,
NEG
NEG
AND
AND
OR
OR
XOR
XOR
A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A
SUBC
SUBC A,
NEG
NEG
AND
AND
OR
OR
XOR
XOR
A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A
NOT
NOT
@RW3 @RW3+d16
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG
AND
AND
OR
OR
XOR
XOR
@RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
+B
XOR
NOT
NOT
R7, A @RW7+d8, A
R7 @RW7+d8
XOR
NOT
NOT
R6, A @RW6+d8, A
R6 @RW6+d8
XOR
NOT
NOT
R5, A @RW5+d8, A
R5 @RW5+d8
XOR
NOT
NOT
R4, A @RW4+d8, A
R4 @RW4+d8
XOR
NOT
NOT
R3, A @RW3+d8, A
R3 @RW3+d8
XOR
R2, A @RW2+d8,A
XOR
NOT
NOT
R1, A @RW1+d8, A
R1 @RW1+d8
NOT
NOT
@RW2 @RW2+d16
XOR
F0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG
AND
AND
OR
OR
XOR
XOR
@RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
NEG
AND
AND
OR
OR
R7 @RW7+d8
R7, A @RW7+d8, A
R7, A @RW7+d8, A
XOR
XOR
XOR
XOR
XOR
XOR
E0
XOR
NOT
NOT
R0, A @RW0+d8, A
R0 @RW0+d8
D0
+A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R7, A @RW7+d8, A
R7, A @RW7+d8, A
A, R7 @RW7+d8
ADD
NEG
AND
AND
OR
OR
R6 @RW6+d8
R6, A @RW6+d8, A
R6, A @RW6+d8, A
NEG
AND
AND
OR
OR
R5 @RW5+d8
R5, A @RW5+d8, A
R5, A @RW5+d8, A
NEG
AND
AND
OR
OR
R4 @RW4+d8
R4, A @RW4+d8, A
R4, A @RW4+d8, A
NEG
AND
AND
OR
OR
R3 @RW3+d8
R3, A @RW3+d8, A
R3, A @RW3+d8, A
NEG
AND
AND
OR
OR
R2 @RW2+d8
R2, A @RW2+d8,A
R2, A @RW2+d8,A
NEG
AND
AND
OR
OR
R1 @RW1+d8
R1, A @RW1+d8, A
R1, A @RW1+d8, A
XOR
C0
NOT
NOT
@RW1 @RW1+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R6, A @RW6+d8, A
R6, A @RW6+d8, A
A, R6 @RW6+d8
ADD
B0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG
AND
AND
OR
OR
XOR
XOR
@RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R5, A @RW5+d8, A
R5, A @RW5+d8, A
A, R5 @RW5+d8
ADD
A0
+9
ADD
SUB
SUB
SUBC
SUBC A, NEG
R4, A @RW4+d8, A
R4, A @RW4+d8, A
A, R4 @RW4+d8
ADD
90
NOT
NOT
@RW0 @RW0+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R3, A @RW3+d8, A
R3, A @RW3+d8, A
A, R3 @RW3+d8
ADD
80
NEG
AND
AND
OR
OR
R0 @RW0+d8
R0, A @RW0+d8, A
R0, A @RW0+d8, A
70
ADD
ADD
SUB
SUB
SUBC
SUBC A, NEG
NEG
AND
AND
OR
OR
XOR
XOR
@RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R2, A @RW2+d8,A
R2, A @RW2+d8,A
A, R2 @RW2+d8
60
ADD
50
ADD
SUB
SUB
SUBC
SUBC A, NEG
R1, A @RW1+d8, A
R1, A @RW1+d8, A
A, R1 @RW1+d8
40
ADD
30
ADD
SUB
SUB
SUBC
SUBC A, NEG
R0, A @RW0+d8, A
R0, A @RW0+d8, A
A, R0 @RW0+d8
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX
Table A.9-11 ea Instruction 6 (First Byte = 75H)
ADDW A, SUBW
ADDW
ADDCW
CMPW
ADDCW A, CMPW
ADDCW A,
ANDW
CMPW A, ANDW
CMPW A,
ORW
ORW
ANDW A, ORW
ANDW A,
ANDW A,
ORW
ORW
ORW
A,
A,
A, XORW
DWBNZ @PC
XORW A, DWBNZ
@RW2+, rel
+d16,rel
+F A,@RW3+
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 @RW3+, rel addr16, rel
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16, A,@RW2+ @PC+d16
SUBW A, ADDCW
SUBW A,
ANDW
XORW
XORW A,
DWBNZ
DWBNZ @RW1
+RW7,rel
A,@RW1+ @RW1+RW7 @RW1+, rel
SUBW
ADDW A,
ADDW
CMPW A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
CMPW
XORW
XORW A,
DWBNZ
DWBNZ @RW0
+RW7,rel
A,@RW0+ @RW0+RW7 @RW0+, rel
ADDCW A,
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ADDCW
XORW
XORW A, DWBNZ
DWBNZ @RW3
+d16,rel
A,@RW3 @RW3+d16 @RW3, rel
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
SUBW A,
XORW
XORW A, DWBNZ
DWBNZ @RW2
+d16,rel
A,@RW2 @RW2+d16 @RW2, rel
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
SUBW
XORW
XORW A, DWBNZ
DWBNZ @RW1
+d16,rel
A,@RW1 @RW1+d16 @RW1, rel
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADDW A,
XORW
XORW A, DWBNZ
DWBNZ @RW0
+d16,rel
A,@RW0 @RW0+d16 @RW0, rel
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
ADDW
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ @RW7
+d8,rel
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, rel
F0
+7
E0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ @RW6
+d8,rel
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, rel
D0
+6
C0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ @RW5
+d8,rel
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, rel
B0
+5
A0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ @RW4
+d8,rel
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, rel
90
+4
80
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ @RW3
+d8,rel
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, rel
70
+3
60
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ @RW2
+d8,rel
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, rel
50
+2
40
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ @RW1
+d8,rel
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, rel
30
+1
20
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ @RW0
+d8,rel
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, rel
10
+0
00
APPENDIX A Instructions
Table A.9-12 ea Instruction 7 (First Byte = 76H)
679
680
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
@RW3 @RW3+d16
SUBW
SUBW
@RW3+, A addr16, A
ADDW
ADDW
@RW3+, A addr16, A
+F
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
ORW
ORW
@RW3+, A addr16, A
XORW
XORW
@RW3+, A addr16, A
NOTW
NOTW
@RW3+
addr16
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
@RW2+ @PC+d16
SUBW
SUBW
@RW2+, A @PC+d16,A
ADDW
ADDW
@RW2+, A @PC+d16,A
+E
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+ @RW1+RW7
SUBCW
+D
SUBW
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+ @RW0+RW7
SUBW
SUBCW
+C
ADDW
ADDW
SUBW
SUBCW A,
+B @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
SUBW
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
@RW2 @RW2+d16
ADDW
ADDW
SUBW
+A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
SUBW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
@RW1 @RW1+d16
ADDW
ADDW
SUBCW A,
+9 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
@RW0 @RW0+d16
SUBW
NOTW
NOTW
RW7 @RW7+d8
NOTW
NOTW
RW6 @RW6+d8
NOTW
NOTW
RW5 @RW5+d8
+8 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
SUBW
XORW
XORW
RW7, A @RW7+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
A, RW7 @RW7+d8
RW7 @RW7+d8
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
+7
ADDW
XORW
XORW
RW6, A @RW6+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
A, RW6 @RW6+d8
RW6 @RW6+d8
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
+6
ADDW
XORW
XORW
RW5, A @RW5+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
A, RW5 @RW5+d8
RW5 @RW5+d8
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
+5
NOTW
NOTW
RW4 @RW4+d8
XORW
XORW
RW4, A @RW4+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
A, RW4 @RW4+d8
RW4 @RW4+d8
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
+4
F0
NOTW
NOTW
RW0 @RW0+d8
E0
NOTW
NOTW
RW3 @RW3+d8
D0
XORW
XORW
RW3, A @RW3+d8, A
C0
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
A, RW3 @RW3+d8
RW3 @RW3+d8
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
B0
+3
A0
NOTW
NOTW
RW2 @RW2+d8
90
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
A, RW2 @RW2+d8
RW2 @RW2+d8
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
80
+2
70
NOTW
NOTW
RW1 @RW1+d8
60
XORW
XORW
RW1, A @RW1+d8, A
50
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
A, RW1 @RW1+d8
RW1 @RW1+d8
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
40
+1
30
XORW
XORW
RW0, A @RW0+d8, A
20
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
A, RW0 @RW0+d8
RW0 @RW0+d8
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
10
+0
00
APPENDIX
Table A.9-13 ea Instruction 8 (First Byte = 77H)
DIV
DIV
A, DIVW
DIVW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
DIV
DIV
A, DIVW
DIVW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW MULUW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MULU
MULU A, MULUW MULUW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MULU
MULU A, MULUW MULUW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
+9
+A
+B
+C
+D
+E
+F A, @RW3+
MULU
DIV
DIV
A, DIVW
DIVW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
addr16 A,@RW3+ addr16
A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
A, DIVW
DIVW A,
addr16 A,@RW3+
addr16
DIV
DIV
A, DIVW
DIVW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
F0
+7
E0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
D0
+6
C0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
B0
+5
A0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
90
+4
80
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
70
+3
60
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
50
+2
40
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
30
+1
20
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
10
+0
00
APPENDIX A Instructions
Table A.9-14 ea Instruction 9 (First Byte = 78H)
681
682
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW1,@RW0 @RW0+d16
RW2,@RW0 @RW0+d16
RW3,@RW0 @RW0+d16
RW4,@RW0 @RW0+d16
RW5,@RW0 @RW0+d16
RW6,@RW0 @RW0+d16
RW7,@RW0
@RW0+d16
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW1,@RW1 @RW1+d16
RW2,@RW1 @RW1+d16
RW3,@RW1 @RW1+d16
RW4,@RW1 @RW1+d16
RW5,@RW1 @RW1+d16
RW6,@RW1 @RW1+d16
RW7,@RW1
@RW1+d16
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW1,@RW2 @RW2+d16
RW2,@RW2 @RW2+d16
RW3,@RW2 @RW2+d16
RW4,@RW2 @RW2+d16
RW5,@RW2 @RW2+d16
RW6,@RW2 @RW2+d16
RW7,@RW2
@RW2+d16
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW1,@RW3 @RW3+d16
RW2,@RW3 @RW3+d16
RW3,@RW3 @RW3+d16
RW4,@RW3 @RW3+d16
RW5,@RW3 @RW3+d16
RW6,@RW3 @RW3+d16
RW7,@RW3
@RW3+d16
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW1,@RW1+ @RW1+RW7 RW2,@RW1+ @RW1+RW7 RW3,@RW1+ @RW1+RW7 RW4,@RW1+ @RW1+RW7 RW5,@RW1+ @RW1+RW7 RW6,@RW1+ @RW1+RW7 RW7,@RW1+ @RW1+RW7
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
RW0,@RW3+ RW0, addr16 RW1,@RW3+ RW1, addr16 RW2,@RW3+ RW2, addr16 RW3,@RW3+ RW3, addr16 RW4,@RW3+ RW4, addr16 RW5,@RW3+ RW5, addr16
+F
MOVEA
MOVEA
MOVEA
MOVEA
RW6,@RW3+ RW6, addr16 [email protected]+ RW7, addr16
MOVEA
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW0,@RW2+ @PC+d16
RW1,@RW2+ @PC+d16
RW2,@RW2+ @PC+d16
RW3,@RW2+ @PC+d16
RW4,@RW2+ @PC+d16
RW5,@RW2+ @PC+d16
RW6,@RW2+ @PC+d16
RW7,@RW2+
@PC+d16
+E
+D RW0,@RW1+ @RW1+RW7
+C RW0,@RW0+ @RW0+RW7
+B RW0,@RW3 @RW3+d16
+A RW0,@RW2 @RW2+d16
+9 RW0,@RW1 @RW1+d16
+8 RW0,@RW0 @RW0+d16
MOVEA
MOVEA
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW0,RW7 @RW7+d8
RW1,RW7 @RW7+d8
RW2,RW7 @RW7+d8
RW3,RW7 @RW7+d8
RW4,RW7 @RW7+d8
RW5,RW7 @RW7+d8
RW6,RW7 @RW7+d8
RW7,RW7
@RW7+d8
F0
+7
E0
MOVEA
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW0,RW6 @RW6+d8
RW1,RW6 @RW6+d8
RW2,RW6 @RW6+d8
RW3,RW6 @RW6+d8
RW4,RW6 @RW6+d8
RW5,RW6 @RW6+d8
RW6,RW6 @RW6+d8
RW7,RW6
@RW6+d8
D0
+6
C0
MOVEA
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW0,RW5 @RW5+d8
RW1,RW5 @RW5+d8
RW2,RW5 @RW5+d8
RW3,RW5 @RW5+d8
RW4,RW5 @RW5+d8
RW5,RW5 @RW5+d8
RW6,RW5 @RW5+d8
RW7,RW5
@RW5+d8
B0
+5
A0
MOVEA
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW0,RW4 @RW4+d8
RW1,RW4 @RW4+d8
RW2,RW4 @RW4+d8
RW3,RW4 @RW4+d8
RW4,RW4 @RW4+d8
RW5,RW4 @RW4+d8
RW6,RW4 @RW4+d8
RW7,RW4
@RW4+d8
90
+4
80
MOVEA
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW0,RW3 @RW3+d8
RW1,RW3 @RW3+d8
RW2,RW3 @RW3+d8
RW3,RW3 @RW3+d8
RW4,RW3 @RW3+d8
RW5,RW3 @RW3+d8
RW6,RW3 @RW3+d8
RW7,RW3
@RW3+d8
70
+3
60
MOVEA
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW0,RW2 @RW2+d8
RW1,RW2 @RW2+d8
RW2,RW2 @RW2+d8
RW3,RW2 @RW2+d8
RW4,RW2 @RW2+d8
RW5,RW2 @RW2+d8
RW6,RW2 @RW2+d8
RW7,RW2
@RW2+d8
50
+2
40
MOVEA
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW0,RW1 @RW1+d8
RW1,RW1 @RW1+d8
RW2,RW1 @RW1+d8
RW3,RW1 @RW1+d8
RW4,RW1 @RW1+d8
RW5,RW1 @RW1+d8
RW6,RW1 @RW1+d8
RW7,RW1
@RW1+d8
30
+1
20
MOVEA
MOVEA RW0, MOVEA
MOVEA RW1, MOVEA
MOVEA RW2, MOVEA
MOVEA RW3, MOVEA
MOVEA RW4, MOVEA
MOVEA RW5, MOVEA
MOVEA RW6, MOVEA
MOVEA RW7,
RW0,RW0 @RW0+d8
RW1,RW0 @RW0+d8
RW2,RW0 @RW0+d8
RW3,RW0 @RW0+d8
RW4,RW0 @RW0+d8
RW5,RW0 @RW0+d8
RW6,RW0 @RW0+d8
RW7,RW0
@RW0+d8
10
+0
00
APPENDIX
Table A.9-15 MOVEA RWi, ea Instruction (First Byte = 79H)
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW2 @RW2+d16 R1,@RW2 @RW2+d16 R2,@RW2 @RW2+d16 R3,@RW2 @RW2+d16 R4,@RW2 @RW2+d16 R5,@RW2 @RW2+d16 R6,@RW2 @RW2+d16 R7,@RW2 @RW2+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW3+
addr16 @RW3+
addr16
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16
@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX A Instructions
Table A.9-16 MOV Ri, ea Instruction (First Byte = 7AH)
683
684
MOVW
MOVW RW5,
RW5,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW1 @RW1+d16 RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16 RW3,@RW1 @RW1+d16 RW4,@RW1 @RW1+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW2 @RW2+d16 RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16 RW3,@RW2 @RW2+d16 RW4,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW3 @RW3+d16 RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16 RW3,@RW3 @RW3+d16 RW4,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4, MOVW
MOVW RW5, MOVW
MOVW RW6, MOVW
MOVW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, @RW2+ @PC+d16
RW2, @RW2+ @PC+d16
RW3, @RW2+ @PC+d16
RW4, @RW2+ @PC+d16
MOVW
MOVW
RW1, @RW3+ RW1, addr16
MOVW
RW0, @RW1+
MOVW
MOVW
RW0, @RW2+ @PC+d16
MOVW
MOVW
RW0, @RW3+ RW0, addr16
+9
+A
+B
+C
+D
+E
+F
MOVW
MOVW
RW2, @RW3+ RW2, addr16
MOVW
MOVW
RW3, @RW3+ RW3, addr16
MOVW
MOVW
RW5, @RW3+ RW5, addr16
MOVW
MOVW
RW5, @RW2+ @PC+d16
MOVW
MOVW
RW6, @RW3+ RW6, addr16
MOVW
MOVW RW6,
RW6, @RW2+ @PC+d16
MOVW
MOVW
RW7, @RW3+ RW7, addr16
MOVW
MOVW RW7,
RW7, @RW2+ @PC+d16
MOVW RW7,
@RW1+RW7
MOVW
MOVW RW7,
RW7,@RW3 @RW3+d16
MOVW
MOVW RW7,
RW7,@RW2 @RW2+d16
MOVW
MOVW RW7,
RW7,@RW1 @RW1+d16
MOVW
MOVW RW7,
RW7,@RW0 @RW0+d16
MOVW
MOVW RW7,
RW7, RW7 @RW7+d8
MOVW
MOVW RW7,
RW7, RW6 @RW6+d8
MOVW
MOVW RW7,
RW7, RW5 @RW5+d8
MOVW
MOVW RW7,
RW7, RW4 @RW4+d8
MOVW RW6, MOVW
@RW1+RW7 RW7, @RW1+
MOVW
MOVW RW6,
RW6,@RW3 @RW3+d16
MOVW
MOVW RW6,
RW6,@RW2 @RW2+d16
MOVW
MOVW RW6,
RW6,@RW1 @RW1+d16
MOVW
MOVW RW6,
RW6,@RW0 @RW0+d16
MOVW
MOVW RW6,
RW6, RW7 @RW7+d8
MOVW
MOVW RW6,
RW6, RW6 @RW6+d8
MOVW
MOVW RW6,
RW6, RW5 @RW5+d8
MOVW
MOVW RW6,
RW6, RW4 @RW4+d8
MOVW
MOVW
@RW1+RW7 RW6, @RW1+
MOVW
MOVW RW5,
RW5, RW6 @RW6+d8
MOVW
MOVW RW5,
RW5, RW5 @RW5+d8
MOVW RW4, MOVW
@RW1+RW7 RW5, @RW1+
MOVW
MOVW
RW4, @RW3+ RW4, addr16
MOVW RW3, MOVW
@RW1+RW7 RW4, @RW1+
MOVW
MOVW RW5,
RW5,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW0 @RW0+d16 RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16 RW3,@RW0 @RW0+d16 RW4,@RW0 @RW0+d16
+8
MOVW RW2, MOVW
@RW1+RW7 RW3, @RW1+
MOVW
MOVW RW5,
RW5,@RW1 @RW1+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
MOVW
MOVW
RW0, RW7 @RW7+d8
+7
MOVW RW1, MOVW
@RW1+RW7 RW2, @RW1+
MOVW
MOVW RW5,
RW5,@RW0 @RW0+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
MOVW
MOVW
RW0, RW6 @RW6+d8
+6
MOVW
MOVW
@RW1+RW7 RW1, @RW1+
MOVW
MOVW RW5,
RW5, RW7 @RW7+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
MOVW
MOVW
RW0, RW5 @RW5+d8
+5
MOVW
MOVW RW5,
RW5, RW4 @RW4+d8
MOVW
MOVW RW7,
RW7, RW3 @RW3+d8
MOVW
MOVW RW7,
RW7, RW2 @RW2+d8
MOVW
MOVW RW7,
RW7, RW1 @RW1+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
MOVW
MOVW RW6,
RW6, RW3 @RW3+d8
MOVW
MOVW RW6,
RW6, RW2 @RW2+d8
MOVW
MOVW RW6,
RW6, RW1 @RW1+d8
MOVW
MOVW
RW0, RW4 @RW4+d8
MOVW
MOVW RW5,
RW5, RW3 @RW3+d8
MOVW
MOVW RW5,
RW5, RW2 @RW2+d8
MOVW
MOVW RW5,
RW5, RW1 @RW1+d8
+4
F0
MOVW
MOVW RW7,
RW7, RW0 @RW0+d8
E0
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
D0
MOVW
MOVW RW6,
RW6, RW0 @RW0+d8
C0
MOVW
MOVW
RW0, RW3 @RW3+d8
B0
MOVW
MOVW RW5,
RW5, RW0 @RW0+d8
A0
+3
90
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
80
MOVW
MOVW
RW0, RW2 @RW2+d8
70
+2
60
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
50
MOVW
MOVW
RW0, RW1 @RW1+d8
40
+1
30
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
20
MOVW
MOVW
RW0, RW0 @RW0+d8
10
+0
00
APPENDIX
Table A.9-17 MOVW RWi, ea Instruction (First Byte = 7BH)
+F
+E
+D
+C
+B
+A
+9
+8
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R1 addr16, R1
MOV
MOV
@RW3+, R0 addr16, R0
MOV
MOV
MOV
@RW2+, R1 @PC+d16, R1
@RW2+, R0 @PC+d16, R0
MOV
MOV
MOV
MOV
MOV
@RW0+, R1 @RW0+RW7, R1
MOV
@RW3, R1 @RW3+d16, R1
MOV
@RW2, R1 @RW2+d16, R1
MOV
@RW1, R1 @RW1+d16, R1
MOV
@RW1+, R1 @RW1+RW7, R1
MOV
MOV
@RW0, R1 @RW0+d16, R1
MOV
@RW1+, R0 @RW1+RW7, R0
MOV
@RW0+, R0 @RW0+RW7, R0
MOV
@RW3, R0 @RW3+d16, R0
MOV
@RW2, R0 @RW2+d16, R0
MOV
@RW1, R0 @RW1+d16, R0
MOV
@RW0, R0 @RW0+d16, R0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R2 addr16, R2
MOV
@RW2+, R2 @PC+d16, R2
MOV
@RW1+, R2 @RW1+RW7, R2
MOV
@RW0+, R2 @RW0+RW7, R2
MOV
@RW3, R2 @RW3+d16, R2
MOV
@RW2, R2 @RW2+d16, R2
MOV
@RW1, R2 @RW1+d16, R2
MOV
@RW0, R2 @RW0+d16, R2
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R3 addr16, R3
MOV
@RW2+, R3 @PC+d16, R3
MOV
@RW1+, R3 @RW1+RW7, R3
MOV
@RW0+, R3 @RW0+RW7, R3
MOV
@RW3, R3 @RW3+d16, R3
MOV
@RW2, R3 @RW2+d16, R3
MOV
@RW1, R3 @RW1+d16, R3
MOV
@RW0, R3 @RW0+d16, R3
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R4 addr16, R4
MOV
@RW2+, R4 @PC+d16, R4
MOV
@RW1+, R4 @RW1+RW7, R4
MOV
@RW0+, R4 @RW0+RW7, R4
MOV
@RW3, R4 @RW3+d16, R4
MOV
@RW2, R4 @RW2+d16, R4
MOV
@RW1, R4 @RW1+d16, R4
MOV
@RW0, R4 @RW0+d16, R4
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R5 addr16, R5
MOV
@RW2+, R5 @PC+d16, R5
MOV
@RW1+, R5 @RW1+RW7, R5
MOV
@RW0+, R5 @RW0+RW7, R5
MOV
@RW3, R5 @RW3+d16, R5
MOV
@RW2, R5 @RW2+d16, R5
MOV
@RW1, R5 @RW1+d16, R5
MOV
@RW0, R5 @RW0+d16, R5
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R6 addr16, R6
MOV
@RW2+, R6 @PC+d16, R6
MOV
@RW1+, R6 @RW1+RW7, R6
MOV
@RW0+, R6 @RW0+RW7, R6
MOV
@RW3, R6 @RW3+d16, R6
MOV
@RW2, R6 @RW2+d16, R6
MOV
@RW1, R6 @RW1+d16, R6
MOV
@RW0, R6 @RW0+d16,
R6
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R7 addr16, R7
MOV
@RW2+, R7 @PC+d16, R7
MOV
@RW1+, R7 @RW1+RW7, R7
MOV
@RW0+, R7 @RW0+RW7, R7
MOV
@RW3, R7 @RW3+d16, R7
MOV
@RW2, R7 @RW2+d16, R7
MOV
@RW1, R7 @RW1+d16, R7
MOV
@RW0, R7 @RW0+d16, R7
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R7, R0 @RW7+d8, R0
R7, R1 @RW7+d8, R1
R7, R2 @RW7+d8, R2
R7, R3 @RW7+d8, R3
R7, R4 @RW7+d8, R4
R7, R5 @RW7+d8, R5
R7, R6 @RW7+d8, R6
R7, R7 @RW7+d8, R7
F0
+7
E0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R6, R0 @RW6+d8, R0
R6, R1 @RW6+d8, R1
R6, R2 @RW6+d8, R2
R6, R3 @RW6+d8, R3
R6, R4 @RW6+d8, R4
R6, R5 @RW6+d8, R5
R6, R6 @RW6+d8, R6
R6, R7 @RW6+d8, R7
D0
+6
C0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R5, R0 @RW5+d8, R0
R5, R1 @RW5+d8, R1
R5, R2 @RW5+d8, R2
R5, R3 @RW5+d8, R3
R5, R4 @RW5+d8, R4
R5, R5 @RW5+d8, R5
R5, R6 @RW5+d8, R6
R5, R7 @RW5+d8, R7
B0
+5
A0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R4, R0 @RW4+d8, R0
R4, R1 @RW4+d8, R1
R4, R2 @RW4+d8, R2
R4, R3 @RW4+d8, R3
R4, R4 @RW4+d8, R4
R4, R5 @RW4+d8, R5
R4, R6 @RW4+d8, R6
R4, R7 @RW4+d8, R7
90
+4
80
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R3, R0 @RW3+d8, R0
R3, R1 @RW3+d8, R1
R3, R2 @RW3+d8, R2
R3, R3 @RW3+d8, R3
R3, R4 @RW3+d8, R4
R3, R5 @RW3+d8, R5
R3, R6 @RW3+d8, R6
R3, R7 @RW3+d8, R7
70
+3
60
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R2, R0 @RW2+d8, R0
R2, R1 @RW2+d8, R1
R2, R2 @RW2+d8, R2
R2, R3 @RW2+d8, R3
R2, R4 @RW2+d8, R4
R2, R5 @RW2+d8, R5
R2, R6 @RW2+d8, R6
R2, R7 @RW2+d8, R7
50
+2
40
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R1, R0 @RW1+d8, R0
R1, R1 @RW1+d8, R1
R1, R2 @RW1+d8, R2
R1, R3 @RW1+d8, R3
R1, R4 @RW1+d8, R4
R1, R5 @RW1+d8, R5
R1, R6 @RW1+d8, R6
R1, R7 @RW1+d8, R7
30
+1
20
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R0, R0 @RW0+d8, R0
R0, R1 @RW0+d8, R1
R0, R2 @RW0+d8, R2
R0, R3 @RW0+d8, R3
R0, R4 @RW0+d8, R4
R0, R5 @RW0+d8, R5
R0, R6 @RW0+d8, R6
R0, R7 @RW0+d8, R7
10
+0
00
APPENDIX A Instructions
Table A.9-18 MOV ea, Ri Instruction (First Byte = 7CH)
685
686
MOVW
[email protected]
@RW2, RW1 +d16, RW1
MOVW
[email protected]
@RW3, RW1 +d16, RW1
MOVW
[email protected]
@RW0+, RW1 +RW7,RW1
MOVW
[email protected]
@RW1+,RW1 +RW7,RW1
MOVW
[email protected]
@RW2+,RW1 +d16, RW1
MOVW
MOVW
@RW3+,RW1 addr16, RW1
MOVW
[email protected]
@RW2, RW0 +d16, RW0
MOVW
[email protected]
@RW3, RW0 +d16, RW0
MOVW
[email protected]
@RW0+,RW0 +RW7,RW0
MOVW
[email protected]
@RW1+,RW0 +RW7,RW0
MOVW
[email protected]
@RW2+,RW0 +d16, RW0
MOVW
MOVW
@RW3+,RW0 addr16, RW0
+B
+C
+D
+E
+F
MOVW
MOVW
@RW3+,RW2 addr16, RW2
MOVW
[email protected]
@RW2+,RW2 +d16, RW2
MOVW
[email protected]
@RW1+,RW2 +RW7,RW2
MOVW
[email protected]
@RW0+,RW2 +RW7,RW2
MOVW
[email protected]
@RW3, RW2 +d16, RW2
MOVW
[email protected]
@RW2, RW2 +d16, RW2
MOVW
MOVW
@RW3+,RW3 addr16, RW3
MOVW
[email protected]
@RW2+,RW3 +d16, RW3
MOVW
[email protected]
@RW1+,RW3 -+RW7,RW3
MOVW
[email protected]
@RW0+,RW3 +RW7,RW3
MOVW
[email protected]
@RW3, RW3 +d16, RW3
MOVW
[email protected]
@RW2, RW3 +d16, RW3
MOVW
[email protected]
@RW1, RW3 +d16, RW3
MOVW
MOVW
@RW3+,RW4 addr16, RW4
MOVW
[email protected]
@RW2+,RW4 +d16, RW4
MOVW
[email protected]
@RW1+,RW4 +RW7,RW4
MOVW
[email protected]
@RW0+,RW4 +RW7,RW4
MOVW
[email protected]
@RW3, RW4 +d16, RW4
MOVW
[email protected]
@RW2, RW4 +d16, RW4
MOVW
[email protected]
@RW1, RW4 +d16, RW4
MOVW
MOVW
@RW3+,RW5 addr16, RW5
MOVW
[email protected]
@RW2+,RW5 +d16, RW5
MOVW
[email protected]
@RW1+,RW5 +RW7,RW5
MOVW
[email protected]
@RW0+,RW5 +RW7,RW5
MOVW
[email protected]
@RW3, RW5 +d16, RW5
MOVW
[email protected]
@RW2, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW5 +d16, RW5
MOVW
MOVW
@RW3+,RW6 addr16, RW6
MOVW
MOVW @PC
@RW2+,RW6 +d16, RW6
MOVW
[email protected]
@RW1+,RW6 +RW7,RW6
MOVW
[email protected]
@RW0+,RW6 +RW7,RW6
MOVW
[email protected]
@RW3, RW6 +d16, RW6
MOVW
[email protected]
@RW2, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW6 +d16, RW6
MOVW
MOVW
@RW3+,RW7 addr16, RW7
MOVW
[email protected]
@RW2+,RW7 +d16, RW7
MOVW
[email protected]
@RW1+,RW7 +RW7,RW7
MOVW
[email protected]
@RW0+,RW7 +RW7,RW7
MOVW
[email protected]
@RW3, RW7 +d16, RW7
MOVW
[email protected]
@RW2, RW7 +d16, RW7
MOVW
[email protected]
@RW1, RW7 +d16, RW7
MOVW
[email protected]
@RW0, RW7 +d16, RW7
+A
MOVW
[email protected]
@RW1, RW2 +d16, RW2
MOVW
[email protected]
@RW0, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW1 +d16, RW1
MOVW
[email protected]
@RW0, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW0 +d16, RW0
MOVW
[email protected]
@RW0, RW4 +d16, RW4
+9
MOVW
[email protected]
@RW0, RW3 +d16, RW3
MOVW
[email protected]
@RW0, RW1 +d16, RW1
MOVW
[email protected]
@RW0, RW0 +d16, RW0
+8
MOVW
[email protected]
@RW0, RW2 +d16, RW2
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW7, RW0 @RW7+d8, RW0
RW7, RW1 @RW7+d8, RW1 RW7, RW2 @RW7+d8, RW2 RW7, RW3 @RW7+d8, RW3 RW7, RW4 @RW7+d8, RW4 RW7, RW5 @RW7+d8, RW5 RW7, RW6 @RW7+d8, RW6 RW7, RW7 @RW7+d8, RW7
F0
+7
E0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW6, RW0 @RW6+d8, RW0
RW6, RW1 @RW6+d8, RW1 RW6, RW2 @RW6+d8, RW2 RW6, RW3 @RW6+d8, RW3 RW6, RW4 @RW6+d8, RW4 RW6, RW5 @RW6+d8, RW5 RW6, RW6 @RW6+d8, RW6 RW6, RW7 @RW6+d8, RW7
D0
+6
C0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW5, RW0 @RW5+d8, RW0
RW5, RW1 @RW5+d8, RW1 RW5, RW2 @RW5+d8, RW2 RW5, RW3 @RW5+d8, RW3 RW5, RW4 @RW5+d8, RW4 RW5, RW5 @RW5+d8, RW5 RW5, RW6 @RW5+d8, RW6 RW5, RW7 @RW5+d8, RW7
B0
+5
A0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW4, RW0 @RW4+d8, RW0
RW4, RW1 @RW4+d8, RW1 RW4, RW2 @RW4+d8, RW2 RW4, RW3 @RW4+d8, RW3 RW4, RW4 @RW4+d8, RW4 RW4, RW5 @RW4+d8, RW5 RW4, RW6 @RW4+d8, RW6 RW4, RW7 @RW4+d8, RW7
90
+4
80
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW3, RW0 @RW3+d8, RW0
RW3, RW1 @RW3+d8, RW1 RW3, RW2 @RW3+d8, RW2 RW3, RW3 @RW3+d8, RW3 RW3, RW4 @RW3+d8, RW4 RW3, RW5 @RW3+d8, RW5 RW3, RW6 @RW3+d8, RW6 RW3, RW7 @RW3+d8, RW7
70
+3
60
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW2, RW0 @RW2+d8, RW0
RW2, RW1 @RW2+d8, RW1 RW2, RW2 @RW2+d8, RW2 RW2, RW3 @RW2+d8, RW3 RW2, RW4 @RW2+d8, RW4 RW2, RW5 @RW2+d8, RW5 RW2, RW6 @RW2+d8, RW6 RW2, RW7 @RW2+d8, RW7
50
+2
40
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW1, RW0 @RW1+d8, RW0
RW1, RW1 @RW1+d8, RW1 RW1, RW2 @RW1+d8, RW2 RW1, RW3 @RW1+d8, RW3 RW1, RW4 @RW1+d8, RW4 RW1, RW5 @RW1+d8, RW5 RW1, RW6 @RW1+d8, RW6 RW1, RW7 @RW1+d8, RW7
30
+1
20
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW0, RW0 @RW0+d8, RW0
RW0, RW1 @RW0+d8, RW1 RW0, RW2 @RW0+d8, RW2 RW0, RW3 @RW0+d8, RW3 RW0, RW4 @RW0+d8, RW4 RW0, RW5 @RW0+d8, RW5 RW0, RW6 @RW0+d8, RW6 RW0, RW7 @RW0+d8, RW7
10
+0
00
APPENDIX
Table A.9-19 MOVW ea, Rwi Instruction (First Byte = 7DH)
XCH
XCH
XCH
XCH
R1,
XCH
XCH
R2,
XCH
XCH
R3,
XCH
XCH
R4,
XCH
XCH
R5,
XCH
XCH
R6,
XCH
XCH
R7,
XCH
XCH
R1,
XCH
XCH
R2,
XCH
XCH
R3,
XCH
XCH
R4,
XCH
XCH
R5,
XCH
XCH
R6,
XCH
XCH
R7,
XCH
XCH
XCH
XCH
XCH
R1, XCH
XCH
R2, XCH
XCH
R3, XCH
XCH
R4, XCH
XCH
R5, XCH
XCH
R6, XCH
XCH
R7,
+F R0,@RW3+ R0, addr16
XCH
XCH
R1,@RW3+ R1, addr16
XCH
XCH
R2,@RW3+ R2, addr16
XCH
XCH
R3,@RW3+ R3, addr16
XCH
XCH
R4,@RW3+ R4, addr16
XCH
XCH
R5,@RW3+ R5, addr16
XCH
XCH
R6,@RW3+ R6, addr16
XCH
XCH
R7,@RW3+ R7, addr16
+E R0,@RW2+ @PC+d16 R1,@RW2+ @PC+d16 R2,@RW2+ @PC+d16 R3,@RW2+ @PC+d16 R4,@RW2+ @PC+d16 R5,@RW2+ @PC+d16 R6,@RW2+ @PC+d16 R7,@RW2+ @PC+d16
R0, XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW1+RW7 R1,@RW1+ @RW1+RW7 R2,@RW1+ @RW1+RW7 R3,@RW1+ @RW1+RW7 R4,@RW1+ @RW1+RW7 R5,@RW1+ @RW1+RW7 R6,@RW1+ @RW1+RW7 R7,@RW1+ @RW1+RW7
+D R0,@RW1+
XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW0+RW7 R1,@RW0+ @RW0+RW7 R2,@RW0+ @RW0+RW7 R3,@RW0+ @RW0+RW7 R4,@RW0+ @RW0+RW7 R5,@RW0+ @RW0+RW7 R6,@RW0+ @RW0+RW7 R7,@RW0+ @RW0+RW7
XCH
+C R0,@RW0+
+B R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3