The following document contains information on Cypress products. FUJITSU MICROELECTRONICS CONTROLLER MANUAL CM44-10129-6E F2MC-16LX 16-bit Microcontroller MB90330A Series HARDWARE MANUAL F2MC-16LX 16-bit Microcontroller MB90330A Series HARDWARE MANUAL For the information for microcontroller supports, see the following web site. This web site includes the "Customer Design Review Supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ FUJITSU MICROELECTRONICS LIMITED PREFACE ■ Purpose of this document and intended reader We sincerely thank you for your continued use of Fujitsu semiconductor products. MB90330A series is a 16-bit microcontroller designed for applications such as personal computer peripheral device requiring USB communication. The USB function is not only function operation of 12M bps but also simple HOST operation. MB90330A series has functions which are suitable for controlling personal computer peripheral devices such as display and audio and mobile devices supporting the USB communication. This manual describes the functions and operations of the MB90330A Series for engineers who develop products using the MB90330A Series. Please read through this manual. For more information on various instructions, refer to "Instruction Manual". Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller. ■ Trademarks The company names and brand names herein are the trademarks or registered trademarks of their respective owners. ■ Sample program We provide sample programs free of charge to operate peripheral functions of the F2MC-16LX family. The programs can be used to check the operational specification and usage of our microcontroller device. MPU/MCU Support Information http://edevice.fujitsu.com/micom/en-support/ Note: The sample programs are subject to change without notice. The software is designed to show the standard operation and usage of the product, therefore, it must be used after full evaluation before using it on your system. Moreover, we assume no liability for any damage resulting from or caused by the use of the programs. ■ Organization of this document This manual contains the following 27 chapters and appendix. Chapter 1 OVERVIEW This chapter describes basics to give the understanding of the MB90330A series as a whole such as the features, block diagrams, and overviews of the functions. Chapter 2 CPU This chapter describes the basic knowledge on architecture, specifications, instructions, and others to provide better understanding of the CPU core functions of the MB90330A Series. i Chapter 3 INTERRUPT This chapter describes the overview of interruptions, interrupt vector and interrupt cause, register configuration/function, and interrupt processing operations. Chapter 4 Reset This chapter describes the overview of reset, reset cause and oscillation stabilization wait time, and reset operation. Chapter 5 Clock This chapter describes the overview of the clock, register configuration/function, clock mode, and oscillation stability wait time. Chapter 6 Low-Power Consumption Mode This chapter describes the overview of the low-power consumption mode, register configuration/ function, and operation of the low-power consumption mode. Chapter 7 Mode setting This chapter describes the overview of mode settings, mode pin, mode data, and operation in each mode of mode setting. Chapter 8 I/O port This chapter describes the overview of the I/O port and the register configuration/function used in the I/ O port. Chapter 9 Time-base timer This chapter describes the overview of the time-base time, register configuration/function, interrupt, and operation of the time-base timer. Chapter 10 Watchdog timer This chapter describes the overview of the watchdog timer, register configuration/function, and operation of the watchdog timer. Chapter 11 Watch timer This chapter describes a overview of the watch timer, functions and configurations of its registers, and its operation. Chapter 12 16-bit I/O timer This chapter describes a overview of the 16-bit I/O timer, the functions and configurations of its registers, and its operation. Chapter 13 USB function This chapter describes the overview, block diagram, register, and operation of the USB function. Chapter 14 USB HOST This chapter describes the features of the USB HOST, difference from the USB HOST, block diagrams, registers and operations of USB HOST, and each token flowchart of USB HOST. Chapter 15 PWC timer This chapter describes an overview of PWC timer, the configuration and function of register, and the PWC timer operation and precaution. Chapter 16 16-bit reload timer This chapter describes an overview of 16-bit reload timer, the configuration and functions of register and the 16-bit reload timer operation. ii Chapter 17 8/16-bit PPG timer This chapter describes an overview of 8/16-bit PPG timer, the configuration and functions of register, and the 8/16-bit PPG timer operation. Chapter 18 DTP/External interrupt This chapter describes an overview of DTP/external interrupt, the configuration and functions of register, and the DTP/external interrupt operation. Chapter 19 8/10-bit A/D converter This chapter describes the overview of the 8/10-bit A/D converter, the configuration/functions of the register, and the operation of the 8/10-bit A/D converter. Chapter 20 Extended I/O serial interface This chapter describes an overview of the extended I/O serial interface, the configuration and function of registers, and operations of extended I/O serial interface. Chapter 21 UART This chapter describes the overview of the UART, the configuration/functions of the register, the operation of the UART, the usage note of the UART, and the example of UART program. Chapter 22 I2C interface This chapter gives an overview of I2C interface, the configuration and functions of registers, and operations of I2C interface. Chapter 23 ROM mirror function selection module This chapter describes the functions of the ROM mirror function selection module and the configuration/function of the register. Chapter 24 Address match detection function This chapter explains the address match detection function and its operation. Chapter 25 FLASH MEMORY This chapter describes the functions and operation of 3M/4M-bit flash memory, and the method for writing/deleting data to the flash memory. Chapter 26 Example of connecting serial writing (FLASH MICROCONTROLLER PROGRAMMER MODE by YOKOGAWA DIGITAL COMPUTER CORPORATION) This chapter describes the serial on-board writing of the flash ROM (Fujitsu standard). Chapter 27 SERIAL PROGRAMMING CONNECTION (FUJITSU MICROELECTRONICSSERIAL PROGRAMMER) This chapter explains the basic configuration for serial write to flash memory by using the Fujitsu Microelectronics Serial Programmer. APPENDIX Appendix includes detailed information on I/O map, interrupt vector, and instruction list, which are not mentioned in this manual and information that is needed for programming. iii • • • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Copyright ©2005-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved. iv CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 CHAPTER 2 2.1 2.2 2.3 2.4 2.5 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 2.7 2.8 2.9 CPU ............................................................................................................ 23 Overview of the CPU ........................................................................................................................ Memory Space .................................................................................................................................. Linear Addressing ............................................................................................................................. Bank Addressing ............................................................................................................................... Multibyte Data in Memory Space ...................................................................................................... Registers ........................................................................................................................................... Accumulator (A) ........................................................................................................................... User Stack Pointer (USP) and System Stack Pointer (SSP) ....................................................... Processor Status (PS) ................................................................................................................. Program Counter (PC) ................................................................................................................. Bank Registers (PCB, DTB, USB, SSB, ADB) ............................................................................ Direct Page Register (DPR) ........................................................................................................ Register Bank ................................................................................................................................... Prefix Codes ..................................................................................................................................... Interrupt Disable Instructions ............................................................................................................ CHAPTER 3 3.1 3.2 3.3 3.3.1 3.3.2 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.5 3.6 3.6.1 3.6.2 3.6.3 OVERVIEW ................................................................................................... 1 Feature of MB90330A Series ............................................................................................................. 2 Block Diagram .................................................................................................................................... 7 Package Dimension ............................................................................................................................ 8 Pin Assignment ................................................................................................................................. 10 Pin Function ...................................................................................................................................... 11 I/O Circuit Types ............................................................................................................................... 17 Precautions when Using Devices ..................................................................................................... 20 24 25 28 29 31 32 35 36 37 40 41 42 43 44 47 INTERRUPT ............................................................................................... 49 Outline of Interrupt ............................................................................................................................ Interrupt Cause and Interrupt Vector ................................................................................................ Interrupt Control Register and Peripheral Function .......................................................................... Interrupt Control Registers (ICR00 to ICR15) .............................................................................. Interrupt Control Register Functions ............................................................................................ Hardware Interrupt ............................................................................................................................ Operation of Hardware Interrupt .................................................................................................. Operation Flow of Hardware Interrupt ......................................................................................... Procedure for Using a Hardware Interrupt ................................................................................... Multiple Interrupts ........................................................................................................................ Hardware Interrupt Processing Time ........................................................................................... Software Interrupt ............................................................................................................................. Interrupts by Extended Intelligent I/O Service (EI2OS) ..................................................................... Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) .......................................................... Each Register of Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) .............................. Operation of Extended Intelligent I/O Service (EI2OS) ................................................................ v 50 53 56 58 60 63 66 68 69 70 72 74 76 78 80 83 3.6.4 Procedure for use of Extended Intelligent I/O Service (EI2OS) ................................................... 84 3.6.5 Extended Intelligent I/O Service (EI2OS) Processing Time ......................................................... 85 3.7 Exception Processing Interrupt ......................................................................................................... 88 3.8 Interruption by μDMAC ..................................................................................................................... 89 3.8.1 μDMAC Function ......................................................................................................................... 90 3.8.2 Register of μDMAC ...................................................................................................................... 91 3.8.2.1 DMA Descriptor Channel Specification Register (DCSR) ........................................................ 92 3.8.2.2 DMA Status Register (DSRH/DSRL) ........................................................................................ 94 3.8.2.3 DMA Stop Status Register (DSSR) .......................................................................................... 95 3.8.2.4 DMA Permission Register (DERH/DERL) ................................................................................ 96 3.8.3 DMA Descriptor Window Register (DDWR) ................................................................................. 97 3.8.3.1 DMA Data Counter (DDCTH/DDCTL) ...................................................................................... 98 3.8.3.2 DMA I/O Register Address Pointer (DIOAH/DIOAL) ................................................................ 99 3.8.3.3 DMA Control Register (DMACS) ............................................................................................ 100 3.8.3.4 DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL) ........................................................ 102 3.8.4 Explanation of Operation of μDMAC ......................................................................................... 103 3.9 Exceptions ...................................................................................................................................... 105 3.10 Stack Operation of Interrupt Processing ......................................................................................... 106 3.11 Program Example of Interrupt Processing ...................................................................................... 108 3.12 Delayed Interrupt Generation Module ............................................................................................. 112 3.12.1 Operation of Delayed Interrupt Generation Module ................................................................... 113 CHAPTER 4 4.1 4.2 4.3 4.4 4.5 4.6 Outline of Reset .............................................................................................................................. Reset Factors and Oscillation Stabilization Wait Times ................................................................. External Reset Pin .......................................................................................................................... Reset Operation .............................................................................................................................. Reset Factor Bit .............................................................................................................................. State of Each Pin at Reset .............................................................................................................. CHAPTER 5 5.1 5.2 5.3 5.4 5.5 5.6 116 118 120 121 123 125 CLOCK ..................................................................................................... 127 Outline of Clock .............................................................................................................................. Block Diagram of Clock Generation Section ................................................................................... Clock Select Register (CKSCR) ..................................................................................................... Clock Mode ..................................................................................................................................... Oscillation Stabilization Wait Time .................................................................................................. Connection of Oscillator and External Clock .................................................................................. CHAPTER 6 6.1 6.2 6.3 6.4 6.5 6.5.1 6.5.2 6.5.3 RESET ...................................................................................................... 115 128 131 134 137 140 141 LOW-POWER CONSUMPTION MODE ................................................... 143 Outline of Low-Power Consumption Mode ..................................................................................... Block Diagram of Low-power Consumption Control Circuit ............................................................ Low-power Consumption Mode Control Register (LPMCR) ........................................................... CPU Intermittent Operation Mode .................................................................................................. Standby Mode ................................................................................................................................. Sleep Mode ............................................................................................................................... Time-base Timer Mode ............................................................................................................. Watch Mode .............................................................................................................................. vi 144 147 149 152 153 154 156 158 6.5.4 Stop Mode ................................................................................................................................. 6.6 State Transition Diagram ................................................................................................................ 6.7 State of the Pin during Standby Mode, Hold, and Reset ................................................................ 6.8 Precautions when Using Low-power Consumption Mode .............................................................. CHAPTER 7 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.5 7.5.1 7.5.2 7.5.3 MODE SETTING ....................................................................................... 177 Mode Setting ................................................................................................................................... Mode Pins (MD2 to MD0) ............................................................................................................... Mode Data ...................................................................................................................................... External Memory Access ................................................................................................................ Automatic Ready Function Selection Register (ARSR) ............................................................. External Address Output Control Register (HACR) ................................................................... Bus Control Signal Selection Register (EPCR) ......................................................................... Operation in Each Mode of Mode Setting ....................................................................................... External Memory Access Control Signal ................................................................................... Ready Function ......................................................................................................................... Holding Function ........................................................................................................................ CHAPTER 8 9.1 9.2 9.3 9.4 9.5 9.6 9.7 178 179 180 184 186 187 188 190 191 194 197 I/O PORT .................................................................................................. 199 8.1 Functions of I/O Ports ..................................................................................................................... 8.2 I/O Port Register ............................................................................................................................. 8.2.1 Port Data Register (PDR0 to PDRB) ......................................................................................... 8.2.2 Port Direction Register (DDR0 to DDRB) .................................................................................. 8.2.3 Other Registers ......................................................................................................................... CHAPTER 9 160 162 164 174 200 201 202 203 204 TIME-BASE TIMER .................................................................................. 207 Overview of Time-base Timer ......................................................................................................... Configuration of Time-base Timer .................................................................................................. Time-base Timer Control Register (TBTC) ..................................................................................... Interrupt of Time-base Timer .......................................................................................................... Operations of Time-base Timer ...................................................................................................... Precautions when Using Time-base Timer ..................................................................................... Program Example of Time-base Timer ........................................................................................... 208 210 212 214 215 217 219 CHAPTER 10 WATCHDOG TIMER ................................................................................ 221 10.1 10.2 10.3 10.4 10.5 10.6 Overview of Watchdog Timer ......................................................................................................... Watchdog Timer Control Register (WDTC) .................................................................................... Configuration of Watchdog Timer ................................................................................................... Operations of Watchdog Timer ....................................................................................................... Precautions when Using Watchdog Timer ...................................................................................... Program Examples of Watchdog Timer .......................................................................................... 222 224 226 228 230 231 CHAPTER 11 WATCH TIMER ........................................................................................ 233 11.1 11.2 11.3 11.4 Overview of Watch Timer ............................................................................................................... Configuration of Watch Timer ......................................................................................................... Watch Timer Control Register (WTC) ............................................................................................. Operation of Watch Timer ............................................................................................................... vii 234 235 236 238 CHAPTER 12 16-BIT I/O TIMER ..................................................................................... 239 12.1 Overview of 16-bit I/O Timer ........................................................................................................... 12.2 Register of 16-bit I/O Timer ............................................................................................................ 12.2.1 16-bit Free-run Timer ................................................................................................................. 12.2.2 Output Compare ........................................................................................................................ 12.2.3 Input Capture ............................................................................................................................. 12.3 Operation of 16-bit I/O Timer .......................................................................................................... 12.3.1 Operation of 16-bit Free-run Timer ............................................................................................ 12.3.2 Operation of 16-bit Output Compare ......................................................................................... 12.3.3 Operation of 16-bit Input Capture .............................................................................................. 12.3.4 Timing of 16-bit Free-run Timer ................................................................................................. 12.3.5 Output Compare Timing ............................................................................................................ 12.3.6 Input Timing of Input Capture .................................................................................................... 240 242 243 249 254 257 258 260 262 263 264 265 CHAPTER 13 USB FUNCTION ....................................................................................... 267 13.1 Overview of USB Function .............................................................................................................. 13.2 Block Diagram of USB Function ..................................................................................................... 13.3 Registers of USB Function ............................................................................................................. 13.3.1 UDC Control Register (UDCC) .................................................................................................. 13.3.2 EP0 Control Register (EP0C) .................................................................................................... 13.3.3 EP1 to EP5 Control Register (EP1C to EP5C) .......................................................................... 13.3.4 Time Stamp Register (TMSP) ................................................................................................... 13.3.5 UDC Status Register (UDCS) .................................................................................................... 13.3.6 UDC Interruption Enable Register (UDCIE) .............................................................................. 13.3.7 EP0I Status Register (EP0IS) .................................................................................................... 13.3.8 EP0O Status Register (EP0OS) ................................................................................................ 13.3.9 EP1 to EP5 Status Register (EP1S to EP5S) ............................................................................ 13.3.10 EP0 to EP5 Data Register (EP0DT to EP5DT) ......................................................................... 13.4 Operation Explanation of USB Function ......................................................................................... 13.4.1 Detecting Connection and Disconnection .................................................................................. 13.4.2 Each Register Operation when Command Responds ............................................................... 13.4.3 STALL Response and Release ................................................................................................. 13.4.4 Suspend Function ...................................................................................................................... 13.4.5 Wake-up Function ..................................................................................................................... 13.4.6 DMA Transfer Function ............................................................................................................. 13.4.7 NULL Transfer Function ............................................................................................................ 268 269 270 273 276 278 282 283 286 288 290 293 297 298 301 303 305 309 310 311 315 CHAPTER 14 USB HOST ............................................................................................... 317 14.1 Feature of USB HOST .................................................................................................................... 14.2 Restriction on USB HOST .............................................................................................................. 14.3 Block Diagram of USB HOST ......................................................................................................... 14.4 Register of USB HOST ................................................................................................................... 14.4.1 Host Control Register 0,1(HCNT0/HCNT1) ............................................................................... 14.4.2 Host Interruption Register (HIRQ) ............................................................................................. 14.4.3 Host Error Status Register (HERR) ........................................................................................... 14.4.4 Host State Status Register (HSTATE) ....................................................................................... 14.4.5 SOF Interruption FRAME Comparison Register (HFCOMP) ..................................................... viii 318 319 320 321 324 328 331 334 337 14.4.6 Retry Timer Setting Register (HRTIMER) ................................................................................. 14.4.7 Host Address Register (HADR) ................................................................................................. 14.4.8 EOF Setting Register (HEOF) ................................................................................................... 14.4.9 FRAME Setting Register (HFRAME) ......................................................................................... 14.4.10 Host Token Endpoint Register (HTOKEN) ................................................................................ 14.5 Operation of USB HOST ................................................................................................................. 14.5.1 Connection of Device ................................................................................................................ 14.5.2 Reset of USB Bus ...................................................................................................................... 14.5.3 Token Packet ............................................................................................................................. 14.5.4 Data Packet ............................................................................................................................... 14.5.5 Handshake Packet .................................................................................................................... 14.5.6 Retry Function ........................................................................................................................... 14.5.7 SOF Interrupt ............................................................................................................................. 14.5.8 Error Status ............................................................................................................................... 14.5.9 Packet End ................................................................................................................................ 14.5.10 Suspend Resume ...................................................................................................................... 14.5.11 Cutting of Device ....................................................................................................................... 14.6 Each Token Flow Chart of USB HOST ........................................................................................... 338 339 340 341 342 344 345 347 348 350 351 352 353 355 356 357 360 361 CHAPTER 15 PWC TIMER ............................................................................................. 363 15.1 Overview of PWC Timer ................................................................................................................. 15.2 Register of PWC Timer ................................................................................................................... 15.2.1 PWC Control Status Register (PWCSR) ................................................................................... 15.2.2 PWC Data Buffer Register (PWCR) .......................................................................................... 15.2.3 PWC Ratio of Dividing Frequency Control Register (DIVR) ...................................................... 15.3 Movement of PWC Timer ............................................................................................................... 15.3.1 Operation of PWM Timer Functions .......................................................................................... 15.3.2 Operation of Pulse Width Measurement Function ..................................................................... 15.3.3 Count Clock Selection and Operation Mode selection .............................................................. 15.3.4 Startup and Stop of Timer/Pulse Width Measurement .............................................................. 15.3.5 Operation of Timer Mode ........................................................................................................... 15.3.6 Operation of Pulse Width Measurement Mode .......................................................................... 15.4 Precautions when Using PWC Timer ............................................................................................. 364 366 367 372 373 374 375 376 377 379 381 384 389 CHAPTER 16 16-BIT RELOAD TIMER ........................................................................... 391 16.1 Overview of 16-bit Reload Timer .................................................................................................... 392 16.1.1 Function of 16-bit Reload Timer ................................................................................................ 393 16.1.2 Block Diagram of 16-bit Reload Timer ....................................................................................... 395 16.2 Registers of 16-bit Reload Timer .................................................................................................... 396 16.2.1 Timer Control Status Register 0 to 2 (TMCSR0 to TMCSR2) ................................................... 397 16.2.2 16-bit Timer Register 0 to 2 (TMR0 to TMR2)/16-bit Reload Register 0 to 2 (TMRLR0 to TMRLR2) .................................................................................................................................................... 401 16.3 Movement of 16-bit Reload Timer .................................................................................................. 403 16.3.1 State Transition of Counter Operation ....................................................................................... 404 16.3.2 Operation of Internal Clock Mode (Reload Mode) ..................................................................... 405 16.3.3 Operation of Internal Clock Mode (Single Shot Mode) .............................................................. 407 16.3.4 Event Count Mode ..................................................................................................................... 409 ix CHAPTER 17 8/16-BIT PPG TIMER ............................................................................... 411 17.1 Overview of 8/16-bit PPG Timer ..................................................................................................... 17.1.1 Block Diagram of 8/16-bit PPG Timer ....................................................................................... 17.2 Registers of 8/16-bit PPG Timer ..................................................................................................... 17.2.1 PPG0/PPG2/PPG4 Operation Mode Control Register (PPGC0/PPGC2/PPGC4) .................... 17.2.2 PPG1/PPG3/PPG5 Operation Mode Control Register (PPGC1/PPGC3/PPGC5) .................... 17.2.3 PPG0 to PPG5 Output Control Register (PPG01/PPG23/PPG45) ........................................... 17.2.4 PPG Reload Registers (PRLL0 to PRLL5, PRLH0 to PRLH5) .................................................. 17.3 Operation of 8/16-bit PPG Timer .................................................................................................... 412 413 415 416 418 421 423 424 CHAPTER 18 DTP/EXTERNAL INTERRUPT ................................................................. 429 18.1 18.2 18.3 18.4 Overview of DTP/External Interrupt ................................................................................................ Register of DTP/External Interrupt .................................................................................................. Operation of DTP/External Interrupt ............................................................................................... Precaution of Using DTP/External Interrupt .................................................................................... 430 431 434 436 CHAPTER 19 8/10-BIT A/D CONVERTER ..................................................................... 439 19.1 Overview of 8/10-bit A/D Converter ................................................................................................ 440 19.2 Configuration of 8/10-bit A/D Converter .......................................................................................... 441 19.3 Register of 8/10-bit A/D Converter .................................................................................................. 443 19.3.1 A/D Control Status Register (High) (ADCS1) ............................................................................ 444 19.3.2 A/D Control Status Register (Low) (ADCS0) ............................................................................. 446 19.3.3 A/D Conversion Channel Set Register (ADMR) ........................................................................ 448 19.3.4 A/D Data Register (ADCR1/ADCR0) ......................................................................................... 450 19.4 Explanation of Operation of 8/10-bit A/D Converter ....................................................................... 452 19.4.1 Conversion Operation Using μDMAC or EI2OS ........................................................................ 455 19.4.2 A/D-converted Data Protection Function ................................................................................... 456 19.5 Precautions when Using 8/10-bit A/D Converter ............................................................................ 458 19.6 Example of program-1 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Single Mode) ......................................................................................................................................................... 459 19.7 Example of Program-2 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Continuous Mode) .............................................................................................................................................. 462 19.8 Example of Program-3 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Stop Mode) ......................................................................................................................................................... 465 CHAPTER 20 EXTENDED I/O SERIAL INTERFACE ..................................................... 469 20.1 Outline of Extended I/O Serial Interface ......................................................................................... 20.2 Register in Extended I/O Serial Interface ....................................................................................... 20.2.1 Serial Mode Control Status Register (SMCS) ........................................................................... 20.2.2 Serial Data Register (SDR) ....................................................................................................... 20.2.3 Communication Prescaler Control Register (SDCR) ................................................................. 20.3 Operation of Extended I/O Serial Interface ..................................................................................... 20.3.1 Shift Clock Mode ....................................................................................................................... 20.3.2 Operation State of Serial I/O ..................................................................................................... 20.3.3 Start/stop Timing of Shift Operation and Timing of I/O .............................................................. 20.3.4 Interrupt Function ...................................................................................................................... x 470 471 472 476 477 478 479 480 482 484 CHAPTER 21 UART ........................................................................................................ 485 21.1 Overview of UART .......................................................................................................................... 486 21.2 UART Block Diagram ...................................................................................................................... 488 21.3 UART Pins ...................................................................................................................................... 491 21.4 Register of UART ............................................................................................................................ 492 21.4.1 Serial Control Register 0 to 3 (SCR0 to SCR3) ......................................................................... 493 21.4.2 Serial Mode Register 0 to 3 (SMR0 to SMR3) ........................................................................... 495 21.4.3 Serial Status Register 0 to 3 (SSR0 to SSR3) ........................................................................... 497 21.4.4 Serial Input Data Register 0 to 3 (SIDR0 to SIDR3) and Serial Output Data Register 0 to 3 (SODR0 to SODR3) .................................................................................................................. 500 21.4.5 UART Prescaler Control Register 0 to 3 (UTCR0 to UTCR3) and UART Prescaler Reload Register 0 to 3 (UTRLR0 to UTRLR3) ..................................................................................................... 502 21.5 UART Interrupt ................................................................................................................................ 504 21.5.1 Receive Interrupt Generation and Flag Set Timing ................................................................... 506 21.5.2 Transmit Interrupt Generation and Flag Set Timing .................................................................. 508 21.6 UART Baud Rate ............................................................................................................................ 510 21.6.1 Baud Rate of the UART Internal Clock Using the Dedicated Baud Rate Generator ................. 511 21.6.2 Baud Rate of the External Clock Using the Dedicated Baud Rate Generator ........................... 512 21.6.3 Baud Rate of the External Clock (One-to-one Mode) ................................................................ 513 21.7 Explanation of Operation of UART ................................................................................................. 514 21.7.1 Operation in Asynchronous Mode (Operation Mode 0 or Operation Mode 1) ........................... 516 21.7.2 Operation in Synchronous Mode (Operation Mode 2) ............................................................... 519 21.7.3 Bi-directional Communication Function (Normal Mode) ............................................................ 522 21.7.4 Master/Slave Mode Communication Function (Multi-processor Mode) ..................................... 524 21.8 Notes on Using UART .................................................................................................................... 527 21.9 Example of UART Programming .................................................................................................... 528 CHAPTER 22 I2C INTERFACE ....................................................................................... 531 22.1 I2C Interface Outline ....................................................................................................................... 22.2 I2C Interface Register ..................................................................................................................... 22.2.1 I2C Bus Status Register 0 to 2 (IBSR0 to IBSR2) ..................................................................... 22.2.2 I2C Bus Control Register 0 to 2 (IBCR0 to IBCR2) .................................................................... 22.2.3 I2C Bus Clock Control Register 0 to 2 (ICCR0 to ICCR2) ......................................................... 22.2.4 I2C Bus Address Register 0 to 2 (IADR0 to IADR2) .................................................................. 22.2.5 I2C Bus Data Register 0 to 2 (IDAR0 to IDAR2) ........................................................................ 22.3 I2C Interface Operation ................................................................................................................... 22.3.1 Transfer Flow of I2C Interface ................................................................................................... 22.3.2 Mode Flow of I2C Interface ........................................................................................................ 22.3.3 Operation Flow of I2C Interface ................................................................................................. 532 534 535 537 542 544 545 546 548 550 551 CHAPTER 23 ROM MIRROR FUNCTION SELECTION MODULE ................................ 553 23.1 23.2 Overview of ROM Mirror Function Select Module .......................................................................... 554 ROM Mirror Function Select Register (ROMM) .............................................................................. 555 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION ......................................... 557 24.1 24.2 Overview of Address Match Detection Function ............................................................................. 558 Block Diagram of Address Match Detection Function .................................................................... 559 xi 24.3 Configuration of Address Match Detection Function ...................................................................... 24.3.1 Address Detection Control Register (PACSR) .......................................................................... 24.3.2 Detect Address Setting Registers (PADR0, PADR1) ................................................................ 24.4 Explanation of Operation of Address Match Detection Function .................................................... 24.4.1 Example of Using Address Match Detection Function .............................................................. 24.5 Program Example of Address Match Detection Function ............................................................... 560 561 563 565 566 571 CHAPTER 25 FLASH MEMORY ..................................................................................... 573 25.1 Overview of Flash Memory ............................................................................................................. 25.2 Sector Configuration of Flash Memory ........................................................................................... 25.3 Flash Memory Control Status Register (FMCS) ............................................................................. 25.4 Automatic Algorithm Initiation Method of Flash Memory ................................................................ 25.5 Check the Execution State of Automatic Algorithm ........................................................................ 25.5.1 Data Polling Flag (DQ7) ............................................................................................................ 25.5.2 Toggle Bit Flag (DQ6) ................................................................................................................ 25.5.3 Timing Limit Over Flag (DQ5) .................................................................................................... 25.5.4 Sector Erasing Timer Flag (DQ3) .............................................................................................. 25.6 Write/Erase of Flash memory ......................................................................................................... 25.6.1 Read/Reset State in Flash Memory ........................................................................................... 25.6.2 Writing Data to Flash Memory ................................................................................................... 25.6.3 Erasing All Data from Flash Memory (Chip Erase) .................................................................... 25.6.4 Erasing Any Data in Flash Memory (Sector Erasing) ................................................................ 25.6.5 Flash Memory Sector Erase Suspension .................................................................................. 25.6.6 Flash Memory Sector Erase Resumption .................................................................................. 574 575 577 579 580 582 584 585 586 587 588 589 591 592 594 595 CHAPTER 26 EXAMPLE of CONNECTING SERIAL WRITING (FLASH MICROCONTROLLER PROGRAMMER MODE by YOKOGAWA DIGITAL COMPUTER CORPORATION) ................................................. 597 26.1 Basic Configuration ......................................................................................................................... 598 26.2 Oscillation Clock Frequency and Serial Clock Input Frequency ..................................................... 600 26.3 Flash Microcontroller Programmer System Configuration .............................................................. 601 26.4 Example of Connecting Serial Writing ............................................................................................ 602 26.4.1 Example Connection in Single-chip Mode (when Using User Power) ....................................... 603 26.4.2 Example of Minimum Connection to Flash Microcontroller Programmer (when Using User Power) .................................................................................................................................................... 605 CHAPTER 27 SERIAL PROGRAMMING CONNECTION (FUJITSU MICROELECTRONICS SERIAL PROGRAMMER) ................ 607 27.1 Fujitsu Microelectronics Serial Programmer ................................................................................... 608 27.1.1 Pins Used .................................................................................................................................. 612 APPENDIX ......................................................................................................................... 613 APPENDIX A Memory Map ........................................................................................................................ APPENDIX B Instructions ........................................................................................................................... B.1 Instruction Types ............................................................................................................................ B.2 Addressing ..................................................................................................................................... B.3 Direct Addressing ........................................................................................................................... xii 614 630 631 632 634 B.4 Indirect Addressing ........................................................................................................................ B.5 Execution Cycle Count ................................................................................................................... B.6 Effective address field .................................................................................................................... B.7 How to Read the Instruction List .................................................................................................... B.8 F2MC-16LX Instruction List ............................................................................................................ B.9 Instruction Map ............................................................................................................................... APPENDIX B 640 648 651 652 655 669 690 INDEX................................................................................................................................... 691 xiii xiv Main changes in this edition Page - Changes (For details, refer to main body.) - Changed USB. USB Mini-Host → USB HOST 2, 5 CHAPTER 1 OVERVIEW 1.1 Feature of MB90330A Series Corrected the minimum instruction execution time. 41.6 ns → 41.7 ns 22 CHAPTER 1 OVERVIEW 1.7 Precautions when Using Devices Added "● Serial communication". 24 CHAPTER 2 CPU 2.1 Overview of the CPU ■ Overview of the CPU Corrected the "● Minimum execution time". • 41.7 ns / 6 MHz original oscillation four-time multiplication (at 24 MHz/3.3 V ± 0.3 V internal operation) • PLL clock multiplication method → • 41.7 ns (at machine clock 24MHz) • The frequency of the machine clock varies depending on the model. Changed the "● CPU-independent automatic transfer function". • Extended intelligent I/O service function from maximum 16 channels • μDMAC from maximum 16 channels → • Up to 16 channels of the extended intelligent I/O service (EI2OS) • Up to 16 channels of the DMA transfer (μDMAC) • The DMA transfer (μDMAC) might not be built-in by the series.) 39 41 CHAPTER 2 CPU 2.6 Registers Corrected "Acceptable interrupt level" in Table 2.6-1. Corrected title and content of section 2.6.5. 44 CHAPTER 2 CPU 2.8 Prefix Codes Corrected "Bank select prefix" of PC space in Table 2.8-1. PCC → PCB 91 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC ■ μDMAC Register List Changed the Figure 3.8-1 μDMA Register List. bit8 to bit15 → STP15 to STP8 bit0 to bit7 → STP7 to STP0 95 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC ■ DMA Stop Status Register (DSSR) Changed the Notes. Bit8 to Bit15 → STP15 to STP8 Bit0 to Bit7 → STP7 to STP0 203 CHAPTER 8 I/O PORT 8.2.2 Port Direction Register (DDR0 to DDRB) Corrected the explanation of "● When each terminal functions as a port". 319 CHAPTER 14 USB HOST 14.2 Restriction on USB HOST Changed the description. Diversity with USB HOST → Restriction on USB HOST xv Page 421 422 580 581 Changes (For details, refer to main body.) CHAPTER 17 8/16-BIT PPG TIMER 17.2 Registers of 8/16-bit PPG Timer ■ PPG0 to PPG5 Output Control Register (PPG01/PPG23/ PPG45) Corrected the operation mode column in the table "[bit 7 to bit 5] PCS2 to PCS0: ppg Count Select (count clock selection)". 41.6 ns → 41.7 ns CHAPTER 25 FLASH MEMORY 25.5 Check the Execution State of Automatic Algorithm Deleted "Toggle Bit 2 Flag (DQ2)". 586 Corrected the operation mode column in the table "[bit 4 to bit 2] PCM2 to PCM0:ppg Count Mode (count clock selection)". 41.6 ns → 41.7 ns Deleted "Toggle Bit 2 Flag (DQ2)" in Table 25.5-2. Deleted "*" sentence under Table 25.5-2. Deleted "25.5.5 Toggle Bit 2 Flag (DQ2)". 593 CHAPTER 25 FLASH MEMORY 25.6.4 Erasing Any Data in Flash Memory (Sector Erasing) Corrected flowchart of figure 25.6-2. 636 B.3 Direct Addressing ● I/O direct addressing (io) Changed Figure B.3-5. (MOVW A, i : 0C0H → MOVW A, I:0C0H) Added the note to Figure B.3-5. 637 B.3 Direct Addressing ● Abbreviated direct addressing (dir) Added the note to Figure B.3-6. 638 B.3 Direct Addressing ● I/O direct bit addressing (io:bp) Changed Figure B.3-8. (SETB i : 0C1H : 0 → SETB I:0C1H:0) B.3 Direct Addressing ● Abbreviated direct bit addressing (dir:bp) Added the note to Figure B.3-9. 644 B.4 Indirect Addressing ● Program counter relative branch addressing (rel) Changed Figure B.4-7. (BRA 10H → BRA 3C32H) 645 B.4 Indirect Addressing ● Register list (rlst) Changed Figure B.4-9. (POPW, RW0, RW4 → POPW RW0, RW4) Added the note to Figure B.3-8. xvi Page 670 671 Changes (For details, refer to main body.) B.9 Instruction Map ■ Structure of Instruction Map Changed column: instruction in Table B.9-1. (@RW2+d8, #8, rel → CBNE @RW2+d8, #8, rel) Changed the operand at row: +0, column: E0 in Table B.9-2. (#4 → #vct4) Changed the mnemonic at row: +0, column: D0 in Table B.9-2. (MOV → MOVN) Changed the mnemonic at row: +0, column: B0 in Table B.9-2. (MOV → MOVX) Changed the mnemonic at row: +8, column: B0 in Table B.9-2. (MOV → MOVW) 673 Changed the mnemonic at row: +0, column: E0 in Table B.9-4. (FILSI → FILSWI) 674 Changed Table B.9-5. (· Moved "MUL A" and "MULW A" instruction from column:60 to column:70. · Changed mnemonic and moved the Instruction from column:60, row:+A to column:70, row:+A. (DIVU → DIV)) 675 Changed the operand at row: +E and +F, column: F0 in Table B.9-6. (,#8, rel → #8, rel) 678 Changed the operand at row: +8 to +E, column: 50 in Table B.9-9. (@@ → @) Changed the operand at row: +0 to +7, column: 20 in Table B.9-9. (RWi → @RWi) 679 Changed the operand at column: E0 and F0 in Table B.9-10. (,r → ,rel) 680 Changed the operand at column: 70 in Table B.9-11. (NEG A, → NEG) 681 Changed the operand at column: E0 and F0 in Table B.9-12. (,r → ,rel) 689 Changed Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH). (Column "A" → Column "A0", Changed row "+A" ( W2+d16,A → @RW2+d16 )) The vertical lines marked in the left side of the page show the changes. xvii xviii CHAPTER 1 OVERVIEW This chapter describes basics to give the understanding of the MB90330A series as a whole such as the features, block diagrams, and overviews of the functions. 1.1 Feature of MB90330A Series 1.2 Block Diagram 1.3 Package Dimension 1.4 Pin Assignment 1.5 Pin Function 1.6 I/O Circuit Types 1.7 Precautions when Using Devices CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 1 CHAPTER 1 OVERVIEW 1.1 Feature of MB90330A Series 1.1 MB90330A Series Feature of MB90330A Series The MB90330A series are 16-bit microcontrollers designed for applications, such as personal computer peripheral devices, that require USB communications. The USB function enables not only 12-Mbps function operations but also simplified host operations. It is equipped with functions that are suitable for personal computer peripheral devices such as displays and audio devices, and control of mobile devices that support USB communications. ■ Feature of MB90330A Series In the MB90330A series, there are the following features. ● Built-in PLL clock multiplying circuit • When the original oscillation is 6 MHz. Operating clock (PLL clock) of 3-24 MHz can be selected from: divided-by-two of the original oscillation or 1-, 2-, or 4-times multiplication of the original oscillation. A clock for USB is 48 MHz. • Minimum instruction execution time of 41.7 ns (at oscillation of 6 MHz, four multiplied PLL clock, operation at Vcc of 3.3 V) ● Maximum memory space: 16 Mbytes ● Instruction system optimized to control usage • Data type which can be handled: bit/byte/word/long word • Standard addressing mode: 23 types • High-precision operation enhanced by the employed 32-bit accumulator • Signed multiplication and division, and enhanced RETI instructions ● Instruction system that supports high-level language (C language) multitasking • Adoption of system stack point • Instruction set symmetry and barrel shift instructions ● For no multi-bus/multi-bus ● Higher execution speed: 4-byte queue ● Powerful interrupt function (priority is programmable and can be set to eight levels): 8 external interrupts ● Data transfer function • μDMAC: maximum 16 channels • Extended intelligent I/O service function: maximum 16 channels 2 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 1 OVERVIEW 1.1 Feature of MB90330A Series MB90330A Series ● Capacity of built-in ROM and ROM type • Mask ROM:256 Kbytes, 384 Kbytes • Flash ROM:384 Kbytes ● Built-in RAM • Mass production products:16 Kbytes, 24 Kbytes • Flash products:24 Kbytes, 30 Kbytes • Evaluation chip: 28 Kbytes ● Process: CMOS technology ● Low-power consumption (standby) mode • Sleep mode (mode by which the CPU operation clock is stopped) • Stop mode (mode by which original oscillation is stopped) • CPU intermittent operation mode ● Package • LQFP-120 (FPT-120P-M24:0.4 mm pin pitch) • LQFP-120 (FPT-120P-M21:0.5 mm pin pitch) ● Operation guaranteed temperature: - 40 °C to +85 °C (0 °C to +70 °C when USB is in use) ● General-purpose: maximum 94 ports General-purpose I/O (CMOS):56 ports General-purpose I/O ports (input pull-up resistor settable): 16 ports General-purpose I/O ports (output open drain/5 V tolerant I/O ports): 22 ports ● Timer: Time-base timer/watchdog timer/clock timer: One channel ● 16-bit I/O timer • 16-bit free-run timer: 1 channel • Input capture (ICU): 4 channels • Output compare (OCU): 4 channels ● 8/16-bit PPG timer: 8 bits x 16 channels or 16 bits x 3 channels ● 16-bit reload timer: 3 channels ● 16 bit PWC timer: 1channel ● UART:4 channels CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 3 CHAPTER 1 OVERVIEW 1.1 Feature of MB90330A Series MB90330A Series ● Extended I/O serial interface: 1 channel ● I2C interface: 3 channels ● 8/10-bit A/D converter (RC sequential comparator type):16 channels ● DTP/external interrupt: 8 channels ● USB • USB function (Correspond to USB Full Speed):1 channel • USB HOST:1 channel 4 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 1 OVERVIEW 1.1 Feature of MB90330A Series MB90330A Series ■ Product Lineup Table 1.1-1 MB90330A Series Product Lineup List (1 / 2) Product name MB90V330A * MB90F334A MB90F335A MB90333A Evaluation product Flash memory product Flash memory product MASK ROM products ROM size None 384 Kbytes 512Kbytes 256 Kbytes RAM size 28 Kbytes 24 Kbytes 30 Kbytes 16 Kbytes Power supply for emulator Provided - - - Classification CPU function Number of basic instructions: Instruction bit length: Minimum instruction execution time: Addressing type: Maximum size of memory space: Port Input/output port (CMOS) : 94 16 bit Input/Output Timers 351 8 bits, 16 bits 41.7 ns/24 MHz 23 types 16 Mbytes 16-bit free-run timer Channel count: 1 Overflow interrupt Output Comparison (OCU) Channel count: 4 Pin input factor: matching signal of the compare register Input Capture (ICU) Channel count: 4 Rewriting a register upon a pin input (rising edge, falling edge, or both edges) 8/16-bit PPG timer Number of channels: 8 bits x 6 channels, 16 bits x 3 channels with mode switching function PPG operations of byte or 16 bits Pulse waveform output at arbitrary cycle and duty 16-bit reload timer Channel count: 3 16-bit reload timer operation With Event Counter 16-bit PWC timer Channel count: 1 Timer function (selects one clock for a counter from three internal clocks) Pulse width measurement function (selects one clock for a counter from three internal clocks) UART Channel count: 4 Clock synchronous/asynchronous selectable Dedicated baud rate generator Clock synchronizer LSB and MSB can be switched. I/O Extended serial interface Channel count: 1 Clock synchronous transfer LSB first/MSB first I2C bus communication Channel count: 3 Serial I/O by which Inter IC BUS is supported 8/10-bit A/D converter 10-bit resolution analog input 16 channels CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 5 CHAPTER 1 OVERVIEW 1.1 Feature of MB90330A Series MB90330A Series Table 1.1-1 MB90330A Series Product Lineup List (2 / 2) Product name MB90V330A * MB90F334A MB90F335A MB90333A DTP/external interrupt Input count: 8 Interrupt factor: rising edge/falling edge/"L" level/"H" level selectable USB USB Function (Corresponding to USB Full Speed) Supports Full speed Endpoint are specifiable up to six. Transfer type: Control, Interrupt, Bulk, or Isochronous transfer possible Dual port RAM (The FIFO mode is supported). USB HOST Functions μDMAC Corresponded External bus interface It is (multi/no multi correspondence). The others 22 I/O pins with 5 V tolerant (including pins also used for I2C) Package PGA299 Operating voltage LQFP120 3.3 V ± 0.3 V *: It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details. Note: Writing to the Flash, be sure to perform VCC=3.13 V to 3.60 V more than. 6 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 1 OVERVIEW 1.2 Block Diagram MB90330A Series 1.2 Block Diagram Figure 1.2-1 shows the block diagram of a MB90330A series. ■ Block Diagram of the MB90330A Series Figure 1.2-1 Block Diagram of the MB90330A Series X0,X1 X0A,X1A RST Clock control circuit CPU 2 F MC-16LX core Port 6 RAM(28Kbyte)* ROM(384Kbyte)* 16-bit PWC timer Interrupt controller Extended I/O serial interface Port B PB6/PPG5 PB5/PPG4 PB4 PB3/SDA2 PB2/SCL2 PB1/SDA1 PB0/SCL1 P67/INT7/SDA0 P66/INT6/SCL0 P65/INT5/PWC P64/INT4/SCK P63/INT3/SOT P62/INT2/SIN P61/INT1 P60/INT0 External interrupt (ch.0 to 7) 8/16-bit PPG timer (ch.2) 2 I C interface (ch.0) I2C interface (ch.1,2) P57/CLK P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE Port 5 Port A 16-bit output compare (ch.0,1,2,3) 16-bit free-run timer Port 4 P47/A15/SCK1 P46/A14/SOT1 P45/A13/SIN1 P44/A12/SCK0 P43/A11/SOT0 P42/A10/SIN0 P41/A09/TOT0 P40/A08/TIN0 UART(ch.0,1) 16-bit reload timer (ch.0) 2 P96/ADTG/FRCK P95/SCK3 P94/SOT3 P93/SIN3 P92/SCK2 P91/SOT2 P90/SIN2 16-bit input capture (ch.0,1,2,3) F MC-16LX BUS PA7/OUT3 PA6/OUT2 PA5/OUT1 PA4/OUT0 PA3/IN3 PA2/IN2 PA1/IN1 PA0/IN0 P37/A07 P36/A06 P35/A05 P34/A04 P33/A03/TOT2 P32/A02/TIN2 P31/A01/TOT1 P30/A00/TIN1 Port 3 UART(ch.2,3) 16-bit reload timer (ch.1,2) Port 9 P87 to P80/ AN15 to AN8 AVcc, AVss AVRH P77 to P70/ AN7 to AN0 DVP DVM HVP HVM HCON UTEST Port 8 A/D converter (16ch) P27/A23/PPG3 P26/A22/PPG2 P25/A21/PPG1 P24/A20/PPG0 P23/A19 P22/A18 P21/A17 P20/A16 P17 to P10/ AD15 to AD08/ D15 to D08 Port 2 8/16-bit PPG (ch.0,1) Port 7 USB HOST Port 1 USB function P07 to P00/ AD07 to AD00/ D07 to D00 Port 0 Other pins External bus interface Vss Vcc MD0 MD1 MD2 *: Maximum value Note: In Figure 1.2-1, I/O ports share pins with each of built-in functional blocks. Any port used for built-in module pin cannot be used as an I/O port. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 7 CHAPTER 1 OVERVIEW 1.3 Package Dimension 1.3 MB90330A Series Package Dimension MB90330A series is available in two types of package. ■ Package Dimension (LQFP-120) Figure 1.3-1 Package Dimension of LQFP-120 Type 120-pin plastic LQFP Lead pitch 0.40 mm Package width × package length 14.0 mm × 14.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Code (Reference) P-LFQFP120-14×14-0.40 (FPT-120P-M24) 120-pin plastic LQFP (FPT-120P-M24) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 16.00±0.20(.630±.008)SQ * 14.00±0.10(.551±.004)SQ 90 61 91 60 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 (Mounting height) .059 –.004 INDEX 120 31 "A" 0~8˚ LEAD No. 1 0.40(.016) 30 0.16±0.05 (.006±.002) 0.07(.003) M 0.145±0.055 (.006±.002) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) ©2006-2008 FUJITSU MICROELECTRONICS LIMITED F120036S-c-1-2 C 2006 FUJITSU LIMITED F120036S-c-1-1 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 8 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 1 OVERVIEW 1.3 Package Dimension MB90330A Series ■Package Dimension (LQFP-120) Figure 1.3-2 Package Dimension of LQFP-120 Type 120-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 16.0 × 16.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.88 g Code (Reference) P-LFQFP120-16×16-0.50 (FPT-120P-M21) 120-pin plastic LQFP (FPT-120P-M21) Note 1) * : These dimensions do not include resin protrusion. Resin protrusion is +0.25(.010) MAX(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 18.00±0.20(.709±.008)SQ +0.40 * 16.00 –0.10 .630 +.016 –.004 SQ 90 61 60 91 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 (Mounting height) .059 –.004 INDEX 0~8˚ 120 LEAD No. "A" 31 1 30 0.50(.020) 0.22±0.05 (.009±.002) 0.08(.003) M ©2002-2008 FUJITSU MICROELECTRONICS LIMITED F120033S-c-4-5 C 2002 FUJITSU LIMITED F120033S-c-4-4 0.145 .006 +0.05 –0.03 +.002 –.001 0.60±0.15 (.024±.006) 0.10±0.05 (.004±.002) (Stand off) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values. Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 9 CHAPTER 1 OVERVIEW 1.4 Pin Assignment 1.4 MB90330A Series Pin Assignment Figure 1.4-1 shows the pin assignments of a MB90330A series. ■ Pin Assignment (LQFP-120) Figure 1.4-1 Pin Assignments of the MB90330A Series (LQFP-120) P56/RDY P57/CLK P00/AD00/D00 P01/AD01/D01 P02/AD02/D02 P03/AD03/D03 P04/AD04/D04 P05/AD05/D05 P06/AD06/D06 P07/AD07/D07 P10/AD08/D08 P11/AD09/D09 P12/AD10/D10 P13/AD11/D11 Vcc Vss X1 X0 P14/AD12/D12 P15/AD13/D13 P16/AD14/D14 P17/AD15/D15 P20/A16 P21/A17 P22/A18 P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 P30/A00/TIN1 P31/A01/TOT1 P32/A02/TIN2 P33/A03/TOT2 P34/A04 P35/A05 P36/A06 P37/A07 P40/A08/TIN0 P41/A09/TOT0 P42/A10/SIN0 P43/A11/SOT0 X0A X1A Vcc Vss P44/A12/SCK0 P45/A13/SIN1 P46/A14/SOT1 P47/A15/SCK1 P60/INT0 P61/INT1 P62/INT2/SIN P63/INT3/SOT P64/INT4/SCK P65/INT5/PWC P66/INT6/SCL0 P67/INT7/SDA0 P90/SIN2 P91/SOT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MB90330A series TOP VIEW 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RST MD0 MD1 MD2 P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE HCON Vcc HVP HVM Vss Vcc DVP DVM Vss UTEST PB6/PPG5 PB5/PPG4 PB4 PB3/SDA2 PB2/SCL2 PB1/SDA1 PB0/SCL1 PA7/OUT3 PA6/OUT2 PA5/OUT1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 PA4/OUT0 PA3/IN3 PA2/IN2 PA1/IN1 PA0/IN0 P87/AN15 P86/AN14 P85/AN13 P84/AN12 P83/AN11 P82/AN10 P81/AN9 P80/AN8 Vss P77/AN7 P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 AVss AVRH AVcc P96/ADTG/FRCK P95/SCK3 P94/SOT3 P93/SIN3 P92/SCK2 10 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 1 OVERVIEW 1.5 Pin Function MB90330A Series 1.5 Pin Function Table 1.5-1 describes the MB90330A series pin functions. ■ Pin Function Table 1.5-1 Pin Function (1 / 6) Pin No. Pin Name Circuit Type 107 X1 A It is oscillation pin. 108 X0 A It is oscillation pin. 13 X0A A It is 32 kHz oscillation pin. 14 X1A A It is 32 kHz oscillation pin. 90 RST F It is reset input. It is General-purpose I/O port. You can set a pull-up resistor ON (RD00 to RD07= 1) with the pull-up resistor setting register (RDR0) (When the power output is set, it is invalid). P00 to P07 93 to 100 101 to 104 109 to 112 AD00 to AD07 Functional description H Functions as an I/O pin for the low-order external address/data bus in multiplex mode. D00 to D07 Functions as an I/O pin for the low-order external data bus in non-multiplex mode. P10 to P13 It is General-purpose I/O port. You can set a pull-up resistor ON (RD10 to RD13= 1) with the pull-up resistor setting register (RDR1) (When the power output is set, it is invalid). AD08 to AD11 H Functions as an I/O pin for the high-order external address/data bus in multiplex mode. D08 to D11 Functions as an I/O pin for the high-order external data bus in non-multiplex mode. P14 to P17 It is General-purpose I/O port. You can set a pull-up resistor ON (RD14 to RD17= 1) with the pull-up resistor setting register (RDR1) (When the power output is set, it is invalid) AD12 to AD15 D12 to D15 CM44-10129-6E H Functions as an I/O pin for the high-order external address/data bus in multiplex mode. Functions as an I/O pin for the high-order external data bus in non-multiplex mode. FUJITSU MICROELECTRONICS LIMITED 11 CHAPTER 1 OVERVIEW 1.5 Pin Function MB90330A Series Table 1.5-1 Pin Function (2 / 6) Pin No. Pin Name Circuit Type It is General-purpose I/O port. Functions as the general-purpose input/output port in the external bus mode if the bit corresponding to external address output control register (HACR) is set to "1". P20 to P23 113 to 116 117 to 120 A16 to A19 D Functions as the upper output pin of an address (A16 to A19) in the nonmultiplex mode if the bit corresponding to external address output control register (HACR) is set to "0". P24 to P27 It is General-purpose I/O port. Functions as the general-purpose input/output port in the external bus mode if the bit corresponding to external address output control register (HACR) is set to "1". A20 to A23 Functions as the upper output pin of an address (A20 to A23) in the multiplex mode if the bit corresponding to external address output control register (HACR) is set to "0". D Functions as the upper output pin of an address (A20 to A23) in the nonmultiplex mode if the bit corresponding to external address output control register (HACR) is set to "0". PPG0 to PPG3 Function as ch.0 to ch.3 output pins for the PPG timer. P30 A00 It is General-purpose I/O port. D TIN1 A01 It is General-purpose I/O port. D TOT1 A02 It is General-purpose I/O port. D TIN2 A03 It is General-purpose I/O port. D TOT2 It is General-purpose I/O port. D A04 to A07 12 Functions as the external address pin in non-multi-bus mode. Functions as an output pin for 16-bit reload timer ch.2. P34 to P37 5 to 8 Functions as the external address pin in non-multi-bus mode. Functions as an event input pin for 16-bit reload timer ch.2. P33 4 Functions as the external address pin in non-multi-bus mode. Functions as an output pin for 16-bit reload timer ch.1. P32 3 Functions as the external address pin in non-multi-bus mode. Functions as an event input pin for 16-bit reload timer ch.1. P31 2 Functions as the upper output pin of an address (A16 to A19) in the multiplex mode if the bit corresponding to external address output control register (HACR) is set to "0". A16 to A19 A20 to A23 1 Functional description Functions as the external address pin in non-multi-bus mode. FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 1 OVERVIEW 1.5 Pin Function MB90330A Series Table 1.5-1 Pin Function (3 / 6) Pin No. Pin Name Circuit Type P40 9 A08 It is General-purpose I/O port. G TIN0 A09 It is General-purpose I/O port. G TOT0 12 A10 It is General-purpose I/O port. G Functions as a data input pin for UART ch.0. P43 It is General-purpose I/O port. A11 G A12 It is General-purpose I/O port. G SCK0 19 It is General-purpose I/O port. G Functions as the external address pin in non-multi-bus mode. SIN1 Functions as a data input pin for UART ch.1. P46 It is General-purpose I/O port. A14 G SOT1 A15 It is General-purpose I/O port. G SCK1 Functions as the external address pin in non-multi-bus mode. Functions as a clock I/O pin for UART ch.1. P50 81 Functions as the external address pin in non-multi-bus mode. Functions as a data output pin for UART ch.1. P47 20 Functions as the external address pin in non-multi-bus mode. Functions as a clock I/O pin for UART ch.0. P45 A13 Functions as the external address pin in non-multi-bus mode. Functions as a data output pin for UART ch.0. P44 18 Functions as the external address pin in non-multi-bus mode. SIN0 SOT0 17 Functions as the external address pin in non-multi-bus mode. Functions as an output pin for 16-bit reload timer ch.0. P42 11 Functions as the external address pin in non-multi-bus mode. Functions as an event input pin for 16-bit reload timer ch.0. P41 10 Functional description It is General-purpose I/O port. L ALE Functions as the address latch enable signal (ALE) pin in external bus mode. P51 82 It is General-purpose I/O port. L RD Functions as the read strobe output (RDX) pin in external bus mode. P52 It is General-purpose I/O port. 83 L WRL CM44-10129-6E Functions as the data write strobe output (WRLX) pin on the lower side in external bus mode. Functions as a general-purpose I/O port when the WRE bit in the EPCR register is "0". FUJITSU MICROELECTRONICS LIMITED 13 CHAPTER 1 OVERVIEW 1.5 Pin Function MB90330A Series Table 1.5-1 Pin Function (4 / 6) Pin No. Pin Name Circuit Type P53 84 It is General-purpose I/O port. L WRH P54 85 It is General-purpose I/O port. L Functions as the hold request input (HRQ) pin in external bus mode. Functions as a general-purpose I/O port when the HDE bit in the EPCR register is "0". P55 It is General-purpose I/O port. L HAK P56 91 It is General-purpose I/O port. L Functions as the external ready input (RDY) pin in external bus mode. Functions as a general-purpose I/O port when the RYE bit in the EPCR register is "0". P57 It is General-purpose I/O port. L CLK P60, P61 21, 22 It is General-purpose I/O port (Withstand voltage of 5 V). Function as input pins for external interrupt ch.0, ch.1. P62 26 INT2 It is General-purpose I/O port (Withstand voltage of 5 V). C Function as input pins for external interrupt ch.2. SIN It is extended serial I/O data output pin. P63 It is General-purpose I/O port (Withstand voltage of 5 V). INT3 C Function as input pins for external interrupt ch.3. SOT It is simple serial I/O data output pin. P64 It is General-purpose I/O port (Withstand voltage of 5 V). INT4 C Function as input pins for external interrupt ch.4. SCK It is extended serial I/O clock input/output pin. P65 It is General-purpose I/O port (Withstand voltage of 5 V). INT5 PWC 14 Functions as the machine cycle clock output (CLK) pin in external bus mode. Functions as a general-purpose I/O port when the CKE bit in the EPCR register is "0". C INT0, INT1 25 Functions as the hold acknowledge output (HAKX) pin in external bus mode. Functions as a general-purpose I/O port when the HDE bit in the EPCR register is "0". RDY 92 24 Functions as the data write strobe output (WRHX) pin on the higher side in 16bit external bus mode. Functions as a general-purpose I/O port when the WRE bit in the EPCR register is "0". HRQ 86 23 Functional description C Function as input pins for external interrupt ch.5. Functions as the PWC input pin. FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 1 OVERVIEW 1.5 Pin Function MB90330A Series Table 1.5-1 Pin Function (5 / 6) Pin No. Pin Name Circuit Type P66 27 INT6 It is General-purpose I/O port (Withstand voltage of 5 V). C P67 INT7 It is General-purpose I/O port (Withstand voltage of 5 V). C P70 to P77 It is General-purpose I/O port. I AN0 to AN7 Function as input pins for analog ch.0 to ch.7. P80 to P87 48 to 55 It is General-purpose I/O port. I AN8 to AN15 Function as input pins for analog ch.8 to ch.15. P90 29 It is General-purpose I/O port. D SIN2 Functions as a data input pin for UART ch.2. P91 30 It is General-purpose I/O port. D SOT2 Functions as a data output pin for UART ch.2. P92 31 It is General-purpose I/O port. D SCK2 Functions as a clock I/O pin for UART ch.2. P93 32 It is General-purpose I/O port. D SIN3 Functions as a data input pin for UART ch.3. P94 33 It is General-purpose I/O port. D SOT3 Functions as a data output pin for UART ch.3. P95 34 It is General-purpose I/O port. D SCK3 Functions as a clock I/O pin for UART ch.3. P96 35 Function as input pins for external interrupt ch.7. Functions as the data I/O pin for the I2C interface ch.0. Set port output to Hi-Z during I2C interface operations. SDA0 39 to 46 Function as input pins for external interrupt ch.6. Functions as the clock I/O pin for the I2C interface ch.0. Set port output to Hi-Z during I2C interface operations. SCL0 28 Functional description ADTG It is General-purpose I/O port (Withstand voltage of 5 V). C FRCK Functions as the external clock input pin when the free-run timer is being used. PA0 to PA3 56 to 59 Functions as the external trigger input pin when the A/D converter is being used. It is General-purpose I/O port (Withstand voltage of 5 V). C IN0 to IN3 Captures as trigger input for ch.0 to ch.3 of the input capture. PA4 to PA7 60 to 63 It is General-purpose I/O port (Withstand voltage of 5 V). C OUT0 to OUT3 CM44-10129-6E Functions as the event output pins for ch.0 to ch.3 of the output compare. FUJITSU MICROELECTRONICS LIMITED 15 CHAPTER 1 OVERVIEW 1.5 Pin Function MB90330A Series Table 1.5-1 Pin Function (6 / 6) Pin No. Pin Name Circuit Type PB0 64 It is General-purpose I/O port (Withstand voltage of 5 V). C SCL1 PB1 65 C PB2 C PB3 PB4 C Functions as the data I/O pin for the I2C interface ch.2. Set port output to Hi-Z during I2C interface operations. C It is General-purpose I/O port (Withstand voltage of 5 V). PB5 69 Functions as the clock I/O pin for the I2C interface ch.2. Set port output to Hi-Z during I2C interface operations. It is General-purpose I/O port (Withstand voltage of 5 V). SDA2 68 Functions as the data I/O pin for the I2C interface ch.1. Set port output to Hi-Z during I2C interface operations. It is General-purpose I/O port (Withstand voltage of 5 V). SCL2 67 Functions as the clock I/O pin for the I2C interface ch.1. Set port output to Hi-Z during I2C interface operations. It is General-purpose I/O port (Withstand voltage of 5 V). SDA1 66 Functional description It is General-purpose I/O port. D PPG4 Function as ch.4 output pins for the PPG timer. PB6 70 It is General-purpose I/O port. D PPG5 Function as ch.5 output pins for the PPG timer. 71 UTEST C It is USB test pin. Requires a pull-down connection in normal use. 73 DVM K It is USB Function D- pin. 74 DVP K It is USB Function D + pin. 77 HVM K It is USB HOST D- pin. 78 HVP K It is USB HOST D + pin. 80 HCON E It is external pull-up resistor pin. 36 AVcc - It is A/D converter power supply pin. 37 AVRH J It is A/D converter external reference power supply pin. 38 AVss - It is A/D converter power supply pin. 87 to 89 MD2 to MD0 B It is Operation mode select input pin. 15, 75, 79, 105 Vcc - It is power supply pin. 16, 47, 72, 76, 106 Vss - It is power supply pin (GND). 16 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 1 OVERVIEW 1.6 I/O Circuit Types MB90330A Series 1.6 I/O Circuit Types Table 1.6-1 shows I/O circuit types for pins of a MB90330A series. ■ I/O Circuit Types Table 1.6-1 I/O Circuit Types (1 / 3) Classification Circuit Remarks A X1,X1A Clock Input P-ch N-ch • Oscillation return resistance: X1, X0 approximately 1 MΩ X1A,X0A 10 MΩ • With standby control X0,X0A Standby control signal B CMOS hysteresis input CMOS hysteresis input C • CMOS hysteresis input • N-ch open drain output N-ch N-ch open drain output CMOS hysteresis input Standby control signal D • CMOS output • CMOS hysteresis input • With standby control P-ch N-ch CMOS hysteresis input Standby control signal E CM44-10129-6E CMOS output P-ch Pout N-ch Nout FUJITSU MICROELECTRONICS LIMITED 17 CHAPTER 1 OVERVIEW 1.6 I/O Circuit Types MB90330A Series Table 1.6-1 I/O Circuit Types (2 / 3) Classification Circuit Remarks F • CMOS hysteresis input with pull-up • Resistance: Approximately 50 kΩ R CMOS hysteresis input G P-ch Open drain control signal N-ch • • • • CMOS output CMOS hysteresis input With open drain control With standby control • • • • • CMOS output CMOS input With input pull-up resistor control Resistance: Approximately 50 kΩ With standby control • • • • CMOS output CMOS hysteresis input With standby control Analog input CMOS hysteresis input Standby control signal H Control signal P-ch N-ch CMOS input Standby control signal I P-ch N-ch Analog input CMOS hysteresis input Standby control signal J A/D converter voltage input pin P-ch N-ch 18 Analog input FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 1 OVERVIEW 1.6 I/O Circuit Types MB90330A Series Table 1.6-1 I/O Circuit Types (3 / 3) Classification Circuit Remarks K D+ Input USB I/O pins D- Input D+ D- Differential input Full D+ Output Full D- Output Low D+ Output Low D- Output direction speed L P-ch Pout N-ch Nout • CMOS output • CMOS input (With input interception function at standby) CMOS input Standby control signal CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 19 CHAPTER 1 OVERVIEW 1.7 Precautions when Using Devices 1.7 MB90330A Series Precautions when Using Devices This section describes the precautions when using devices. ■ Precautions when Using Devices ● Preventing Latch-up, Turning on Power Supply Latch-up may occur on CMOS IC under the following conditions: • If a voltage higher than VCC or lower than VSS is applied to input and output pins, • If a voltage higher than the rated voltage is applied between VCC pin to VSS pin, • If the AVCC power supply is turned on before the VCC voltage. Ensure that you apply a voltage to the analog power supply at the same time as VCC or after you turn on the digital power supply (when you perform power-off, turn off the analog power supply first or at the same time as VCC and the digital power supply). When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When using CMOS IC, take great care to prevent the occurrence of latch-up. ● Treatment of Unused Pins Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 kΩ. Any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. If there is unused output pin, make it to open. ● Treatment of Power Supply Pins on Models with A/D Converters Even when the A/D converters are not in use, be sure to make the necessary connections AVCC = AVRH = VCC and AVSS = VSS. ● Treatment of Power Supply Pins (VCC/VSS) In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 μF between VCC and VSS near this device. 20 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 1 OVERVIEW 1.7 Precautions when Using Devices MB90330A Series ● About Crystal oscillator circuit Noise near the X0/X1 pins and X0A/X1A pins may cause the device to malfunction. Design the printed circuit board so that X0/X1 pins and X0A/X1A pins, the crystal oscillator (or the ceramic oscillator) and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the X0/X1 pins and X0A/X1A pins surrounded by ground plane because stable operation can be expected with such a layout. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. ● Note on using external clock If you are using the external clock, you must connect external pins as shown in the Figure 1.7-1. Figure 1.7-1 illustrates an external clock usage. (under f=7 MHz) Figure 1.7-1 Method for Using External Clock X0 OPEN X1 ● Stabilization of Supply Voltage A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage operating range. For stabilization reference, the supply voltage should be stabilized so that VCC ripple variations (peak-to-peak value) at commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard VCC supply voltage and the transient regulation does not exceed 0.1 V/ms at temporary changes such as power supply switching. ● Crystal oscillator circuit of low voltage use If you are using the device with voltages of 2.0 V or less, the external crystal oscillator may not oscillate at power-on. Therefore, It will recommend the use of the external clock. ● When the dual-supply is used as a single-supply device. If you are using only a single-system of the MB90330A series that come in the dual-system product, use it with X0A=VSS: X1A=OPEN. ● Writing to flash memory For serial writing to flash memory, always make sure that the operating voltage VCC is between 3.13 V and 3.6 V. For normal writing to flash memory, always make sure that the operating voltage VCC is between 3.0 V and 3.6 V. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 21 CHAPTER 1 OVERVIEW 1.7 Precautions when Using Devices MB90330A Series Ensure that you must write to Flash at the operation voltage VCC of 3.0 V to 3.60 V. ● Caution on Operations during PLL Clock Mode On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs. ● Serial communication There is a possibility to receive wrong data due to noise or other causes on the serial communication. Therefore, design a printed circuit board so as to avoid noise. Consider receiving of wrong data when designing the system. For example, apply a checksum to detect an error. If an error is detected, retransmit the data. 22 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 2 CPU This chapter explains the setting and operation of the CPU. 2.1 Overview of the CPU 2.2 Memory Space 2.3 Linear Addressing 2.4 Bank Addressing 2.5 Multibyte Data in Memory Space 2.6 Registers 2.7 Register Bank 2.8 Prefix Codes 2.9 Interrupt Disable Instructions Code: CM44-00101-2E Page: 24, 24 CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 23 CHAPTER 2 CPU 2.1 Overview of the CPU 2.1 MB90330A Series Overview of the CPU The F2MC-16LX CPU core is a 16-bit CPU designed for applications that require highspeed real-time processing, such as consumer or vehicle-mounted equipments. The F2MC-16LX instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing. ■ Overview of the CPU In addition to 16-bit data, the F2MC-16LX CPU core can process 32-bit data using an internal 32-bit accumulator. Up to 16Mbytes of memory space (expandable) can be used, which can be accessed by either the linear pointer or bank method. The instruction set, based on the F2MC-8L A-T architecture, has been reinforced by adding instructions compatible with high-level languages, expanding addressing modes, reinforcing multiplication and division instructions, and enhancing bit processing. The features of the F2MC-16LX CPU are explained below: ● Minimum execution time • 41.7 ns (at machine clock 24MHz) • The frequency of the machine clock varies depending on the model. ● Maximum memory space 16Mbytes, accessed in linear or bank method ● Instruction set optimized for controller applications • Rich data types: Bit, byte, word, long word • Extended addressing modes: 23 types • Reinforced high-precision operation (32-bit length) with 32-bit accumulator ● Powerful interrupt function 8 priority levels (programmable) ● CPU-independent automatic transfer function • Up to 16 channels of the extended intelligent I/O service (EI2OS) • Up to 16 channels of the DMA transfer (μDMAC) • The DMA transfer (μDMAC) might not be built-in by the series. ● Instruction set for high-level language (C language)/multitask System stack pointer/instruction set symmetry/barrel-shift instructions ● Higher execution speed 4-byte queue 24 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 2 CPU 2.2 Memory Space MB90330A Series 2.2 Memory Space F2MC-16LX CPU has the memory space of 16Mbytes. ■ Overview of CPU Memory Space An F2MC-16LX CPU has 16Mbytes of memory space where all data program I/Os managed by the F2MC16LX CPU are located. The CPU accesses the resources by indicating their addresses using a 24-bit address bus. Figure 2.2-1 shows a sample relationship between the F2MC-16LX system and memory map. Figure 2.2-1 Sample Relationship between F2MC-16LX System and Memory Map F2MC-16LX device FFFFFFH FFFC00H Programs Vector table area ROM area Program area FF0000H*1 100000H External area*3 010000H ROM area (FF bank image) 008000H 2 F MC-16LX CPU Internal Data Bus Peripheral circuits I/O area 007900H 001900H*2 Data EI2OS 000380H 000180H 000100H Data area General-purpose registers RAM area 2 EI OS descriptor area External area*3 Peripheral circuits Interrupts 0000F0H 0000C0H 0000B0H Peripheral circuits General-purpose ports 000020H 000000H Peripheral function control register area Interrupt control register area Peripheral function control register area I/O port control register area I/O area *1: The size of the built-in ROM varies depending on the model. *2: The size of the built-in RAM varies depending on the model. *3: Access is not possible in single chip mode. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 25 CHAPTER 2 CPU 2.2 Memory Space MB90330A Series ■ ROM Area ● Vector table area (address: FFFC00H to FFFFFFH) • This area is used as a vector table for the reset, interrupt, and CALLV vectors. • This area is allocated at the highest addresses of the ROM area. The start address of the corresponding processing routine is set as data in each vector table address. ● Program area (address: Up to FFFBFFH) • ROM is built in as an internal program area. • The size of internal ROM varies depending on the model. ■ RAM Area ● Data area (address: 000100H to 0018FFH (for 6Kbytes)) • The static RAM is built in as an internal data area. • The size of internal RAM varies depending on the model. ● General-purpose register area (address: 000180H to 00037FH) • Auxiliary registers, used for 8-bit, 16-bit, and 32-bit arithmetic operations and transfer, are allocated in this area. • Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM. • When this area is used as a general-purpose register, general-purpose register addressing enables high speed access with short instructions. ● Extended intelligent I/O service (El2OS) descriptor area (address: 0000100H to 00017FH) • This area retains the transfer modes, I/O addresses, transfer count, and buffer addresses. • Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM. ■ I/O Area ● Interrupt control register area (address: 0000B0H to 0000BFH) The interrupt control registers (ICR00 to ICR15) support all peripheral functions that have an interrupt function, and perform the interrupt levels setting and the control of the extended intelligent I/O service (EI2OS). ● Peripheral function control register area (address: 000020H to 0000AFH, 0000C0H to 0000EFH, and 007900H to 007FFFH) This register controls the peripheral functions and inputs/outputs of data. ● I/O port control register area (address: 000000H to 00001FH) This register controls I/O ports, and inputs/outputs of data. 26 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 2 CPU 2.2 Memory Space MB90330A Series ■ Address Generation Methods The F2MC-16LX has the following two addressing methods: ● Linear addressing An 24-bit address is specified by an instruction. ● Bank addressing Upper 8-bit of an address are specified by an appropriate bank register, and the remaining lower 16-bit of an address are specified by an instruction. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 27 CHAPTER 2 CPU 2.3 Linear Addressing 2.3 MB90330A Series Linear Addressing There are two types of linear addressing: • 24-bit operand specification: Directly specifies a 24-bit address using operands. • 32-bit register indirect specification: Uses the lower 24-bit of a 32-bit general-purpose register contents as the address. ■ 24-bit Operand Specification Figure 2.3-1 and Figure 2.3-2 show examples of 24-bit operand specification and 32-bit register indirect specification, respectively. Figure 2.3-1 Example of Linear Method (24-bit Operand Specification) JMPP 123456H 17452DH Old program counter 17 program bank 452D JMPP 123456H 123456H Next instruction New program counter 12 program bank 3456 Figure 2.3-2 Example of Linear Method (32-bit Register Indirect Specification) MOV A,@RL1+7 Old AL 090700H XXXX 3AH 7 RL1 240906F9H (The upper 8-bit are ignored) New 28 AL 003A FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 2 CPU 2.4 Bank Addressing MB90330A Series 2.4 Bank Addressing In the bank method, the 16 M byte space is divided into 256 of 64 K byte banks. The following five bank registers are used to specify the banks corresponding to each space: • Program counter bank register (PCB) • Data bank register (DTB) • User stack bank register (USB) • System stack bank register (SSB) • Additional data bank register (ADB) ■ Bank Addressing ● Program counter bank register (PCB) The 64Kbyte bank specified by the program counter bank register (PCB) is called a program (PC) space. The PC space typically contains instruction codes, vector tables, and immediate data. ● Data bank register (DTB) The 64Kbyte bank specified by the data bank register (DTB) is called a data (DT) space. The DT space typically contains readable/ writable data, and control/data registers for internal and external resources. ● User stack bank register (USB) and System stack bank register (SSB) The 64Kbyte bank specified by the user stack bank register (USB) or system stack bank register (SSB) is called a stack (SP) space. The SP space is accessed when a stack access occurs during a push/pop instruction or interrupt register saving. The S flag in the condition code register determines which stack space is to be accessed. ● Additional data bank register (ADB) The 64Kbyte bank specified by the Additional data bank register (ADB) is called an additional (AD) space. The AD space typically contains data that cannot fit into the DT space. Table 2.4-1 lists the default spaces used in each addressing mode, which are pre-determined to improve instruction coding efficiency. To use a non-default space for an addressing mode, specify a prefix code corresponding to a bank before the instruction. This enables access to the bank space corresponding to the specified prefix code. By resetting, the DTB, USB, SSB, and ADB are initialized to 00H. The PCB is initialized to a value specified by the reset vector. After reset, the DT, SP, and AD spaces are allocated in bank 00H (000000H to 00FFFFH), and the PC space is allocated in the bank specified by the reset vector. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 29 CHAPTER 2 CPU 2.4 Bank Addressing MB90330A Series Table 2.4-1 Default Space Default space Addressing Program space PC indirect, program access, branch Data space @A, addr16, dir, and addressing using @RW0, @RW1, @RW4, or @RW5 Stack space Addressing using PUSHW, POPW, @RW3, or @RW7 Additional space Addressing using @RW2 or @RW6 The example of the physical address of the memory space divided into the register bank is shown in Figure 2.4-1. Figure 2.4-1 The Example of Physical Addresses of Each Space FFFFFFH Program space FF0000H FFH : PCB (Program counter bank register) B3H : ADB (Additional data bank register) 92H : USB (User stack bank register) B3FFFFH Additional space Physical address B30000H 92FFFFH User stack space 920000H 68FFFFH Data space 680000H 68H : DTB (Data bank register) 4BFFFFH System stack space 4B0000H 4BH : SSB (System stack bank register) 000000H 30 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 2 CPU 2.5 Multibyte Data in Memory Space MB90330A Series 2.5 Multibyte Data in Memory Space Multibyte data is allocated from the low-order addresses to the high-order addresses in the memory space in the order from the byte in LSB to the byte in MSB. ■ Multibyte Data Allocation in Memory Space Data is written to memory from the low-order addresses. Therefore, for a 32-bit data item, the lower 16 bits are transferred before the upper 16 bits. If a reset signal is input immediately after the lower bits are written, the upper bits might not be written. Figure 2.5-1 shows a sample allocation of multibyte data in memory. The lower 8 bits of a data item are stored at address n, then address n+1, address n+2, address n+3, etc. Figure 2.5-1 Sample Allocation of Multibyte Data in Memory MSB "H" LSB 01010101B 11001100B 11111111B 00010100B 01010101B 11001100B 11111111B n location 00010100B "L" ■ Accessing Multibyte Data Basically, all accesses are made within a bank. For an instruction accessing a multibyte data item, the next address of FFFFH location is 0000H location of the same bank. Figure 2.5-2 shows an example of an instruction accessing multibyte data. Figure 2.5-2 Execution of MOVW A, FFFFH "H" AL before execution 80FFFFH ?? ?? 23H 01H 01H · · · 800000H 23H AL after execution "L" CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 31 CHAPTER 2 CPU 2.6 Registers 2.6 MB90330A Series Registers The F2MC-16LX registers are largely classified into two types: dedicated registers and general-purpose registers. The dedicated registers exist as dedicated internal hardware of the CPU, and they have specific use defined by the CPU architecture. The applications of the general-purpose registers can be specified by the user, as is ordinary memory space. Sharing the CPU address space with RAM, the generalpurpose registers are the same as the dedicated registers in that they can be accessed without using an address. ■ Dedicated Registers The F2MC-16LX CPU core has the following 11 dedicated registers: • Accumulator (A=AH: AL) : 2 × 16-bit accumulators (Can be used as a single 32-bit accumulator.) • User stack pointer (USP) : 16-bit pointer indicating the user stack area • System stack pointer (SSP) : 16-bit pointer indicating the system stack area • Processor status (PS) : 16-bit register indicating the system status • Program counter (PC) : 16-bit register containing the address where the program is stored • Program counter bank register (PCB) : 8-bit register indicating the PC space • Data bank register (DTB) : 8-bit register indicating the DT space • User stack bank register (USB) : 8-bit register indicating the user stack space • System stack bank register (SSB) : 8-bit register indicating the system stack space • Additional data bank register (ADB) : 8-bit register indicating the AD space • Direct page register (DPR) : 8-bit register indicating a direct page Figure 2.6-1 shows the configuration of the dedicated registers. 32 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 2 CPU 2.6 Registers MB90330A Series Figure 2.6-1 Dedicated Resisters AH AL Accumulator USP User stack pointer SSP System stack pointer PS Processor status PC Program counter DPR Direct page register PCB Program counter bank register DTB Data bank register USB User bank register SSB System stack bank register ADB Additional data bank register 8 bits 16 bits 32 bits CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 33 CHAPTER 2 CPU 2.6 Registers MB90330A Series ■ General-purpose Registers As described in Figure 2.6-2, the F2MC-16LX general-purpose registers are located from 000180H to 00037FH (maximum configuration) of main storage. The register bank pointer (RP) indicates which of the above addresses is currently being used as a register bank. Each bank has the following three types of registers. These registers are mutually dependent and have a relationship as shown below: • R0 to R7 : 8-bit general-purpose registers • RW0 to RW7 : 16-bit general-purpose registers • RL0 to RL3 : 32-bit general-purpose registers Figure 2.6-2 General-purpose Registers MSB LSB 16 bits 000180H RP × 10 H RW0 Lower RL0 Starting address of general-purpose register RW1 RW2 RL1 RW3 R1 R0 RW4 R3 R2 RW5 R5 R4 RW6 R7 R6 RW7 RL2 RL3 Upper The relationship between the upper/lower bytes of a byte or word register is expressed as follows: RW(i+4)=R(i × 2+1) × 256 + R(i × 2) [i=0 to 3] The relationship between the upper/lower bytes of RLi and RW is expressed as follows: RL(i)=RW(i × 2+1) × 65536 + RW(i × 2) [i=0 to 3] 34 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 2 CPU 2.6 Registers MB90330A Series 2.6.1 Accumulator (A) The accumulator (A) register consists of 2 × 16-bit arithmetic operation registers (AH and AL), and is used as a temporary register for operation results and transfer data. ■ Accumulator (A) During 32-bit data processing, AH and AL are used together (see Figure 2.6-3). Only AL is used for word processing in 16-bit data processing mode or for byte processing in 8-bit data processing mode (see Figure 2.6-4). The data stored in the accumulator (A) register can be operated upon with the data in memory or registers (Ri, RWi, and RLi). In the same manner as with the F2MC-8L, when a word or shorter data item is transferred to AL, the previous data item in AL is automatically sent to AH (data preservation function). The data preservation function and operation between AL and AH help improve processing efficiency. When a byte or shorter data item is transferred to AL, the data is sign-extended or zero-extended and stored as a 16-bit data item in AL. The data in AL can be handled either as word or byte long. When a byteprocessing arithmetic operation instruction is executed on AL, the upper 8 bits of AL before operation are ignored. The upper 8 bits of the operation result all become "0". The A register is not initialized by a reset and holds an undefined value right after the reset. Figure 2.6-3 An Example of 32-bit Data Transfer MOVL A,@RW1+6 A before execution XXXXH MSB XXXXH 8F74H 8FH 74H A6153EH 2BH 52H 15H 38H +6 2B52H AH A61540H A6H DTB A after execution LSB RW1 AL Figure 2.6-4 An Example of AL to AH Transfer MSB MOVW A,@RW1+6 A before execution XXXXH 1234H DTB A6H LSB A61540H 8FH 74H A6153EH 2BH 52H 15H 38H +6 A after execution CM44-10129-6E 1234H 2B52H RW1 FUJITSU MICROELECTRONICS LIMITED 35 CHAPTER 2 CPU 2.6 Registers 2.6.2 MB90330A Series User Stack Pointer (USP) and System Stack Pointer (SSP) User stack pointer (USP) and system stack pointer (SSP) are 16-bit registers that indicate the memory addresses for saving/restoring data when a push/pop instruction or subroutine is executed. ■ User Stack Pointer (USP) and System Stack Pointer (SSP) User stack pointer (USP) and system stack pointer (SSP) registers are used by the stack instructions. However, the USP register is enabled when the S flag in the processor status register is "0", and the SSP register is enabled when the S flag is "1" (see Figure 2.6-5). Since the S flag is set when an interrupt is accepted, register values are always saved in the memory area indicated by SSP during interrupt processing. SSP is used for stack processing in an interrupt routine, while USP is used for stack processing other than in an interrupt routine. If you do not need to divide the stack space, use only the SSP. During stack processing, the upper 8 bits of an address are indicated by SSB (for SSP) or USB (for USP). USP and SSP are not initialized by a reset. Instead, they hold undefined values. Figure 2.6-5 Stack Manipulation Instruction and Stack Pointer Example of PUSHW A when the S flag is "0" Before execution AL S flag After execution AL S flag MSB LSB A624 H USB C6H USP F328H 0 SSB 56H SSP 1234H A624 H USB C6H USP F326H 0 SSB 56H SSP 1234H C6F326H A6H 24H 561232H XX XX 561232H A6H 24H C6F326H XX XX System stack is used because the S flag is "0". Example of PUSHW A when the S flag is "1" AL S flag AL S flag A624 H USB C6H USP F328H 1 SSB 56H SSP 1234H A624 H USB C6H USP F328H 1 SSB 56H SSP 1232H System stack is used because the S flag is "1". Note: When you specify a value to be set in the stack pointer, use an even-numbered address whenever possible. 36 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 2 CPU 2.6 Registers MB90330A Series 2.6.3 Processor Status (PS) The processor status (PS) register consists of the bits controlling the CPU operation and the bits indicating the CPU status. ■ Processor Status (PS) As shown in Figure 2.6-6, the upper bytes of the PS register consist of the register bank pointers (RP) and the interrupt level mask register (ILM) that indicate the starting address of a register bank. The lower bytes of the PS register consist of the condition code register (CCR), containing the flags to be set or reset depending on the results of instruction execution or interrupt occurrences. Figure 2.6-6 Processor Status (PS) Structure bit 15 13 PS 12 8 ILM 7 0 RP CCR ■ Condition Code Register (CCR) Figure 2.6-7 shows the structure of the condition code register. Figure 2.6-7 Structure of Condition Code Register (CCR) bit Initial value 7 6 5 4 3 2 1 0 - I S T N Z V C - 0 1 * * * * * : CCR * : Undefined value ● Interrupt enable flag (I) Interrupts other than software interrupts are enabled when the I flag is "1," and are disabled when the I flag is "0". The I flag is cleared to "0" by a reset. ● Stack flag (S) When the S flag is "0", USP is enabled as the stack manipulation pointer. When the S flag is "1", SSP is enabled as the stack manipulation pointer. The S flag is set to "1" by an interrupt reception or a reset. ● Sticky bit flag (T) "1" is set in the T flag when there is one or more "1" in the data shifted out from the carry after execution of a logical right/arithmetic right shift instruction. Otherwise, "0" is set in the T flag. ● Negative flag (N) The "1" is set in the N flag when the MSB of the operation result is "1". Otherwise, N flag is cleared to "0". CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 37 CHAPTER 2 CPU 2.6 Registers MB90330A Series ● Zero flag (Z) The Z flag is set to "1" when the operation result is all "0". Otherwise, Z flag is cleared to "0". ● Overflow flag (V) The V flag is set when an overflow of a signed value occurs as a result of operation execution. In other cases, V flag is cleared to "0". ● Carry flag (C) The C flag is set when a carry-up or carry-down from the MSB occurs as a result of operation execution. In other cases, C flag is cleared to "0". ■ Register Bank Pointer (RP) As shown in Figure 2.6-8, the register bank pointer (RP) register indicates the relationship between the general-purpose registers of the F2MC-16LX and the internal RAM addresses where the general-purpose registers exist. Specifically, the RP register indicates the starting memory address of the currently used register bank in the following conversion expression: [00180H + (RP) × 10H]. The RP register that consists of five bits can take a value between "00H" and "1FH" and allocate the register banks at addresses from 000180H to 00037FH in the memory. Even within that range, however, the register banks cannot be used as general-purpose registers if the banks are not in internal RAM. All RP registers are initialized to "0" by a reset. An instruction may transfer an 8-bit immediate value to the RP register but, only the lower 5 bits of that data are used. Figure 2.6-8 Register Bank Pointer (RP) Initial value B4 B3 B2 B1 B0 0 0 0 0 0 : RP ■ Interrupt Level Mask Register (ILM) As described in Figure 2.6-9, the interrupt level mask register (ILM) consists of 3 bits, indicating the CPU interrupt masking level. Only an interrupt request of which interrupt level is higher than that indicated by these 3 bits will be accepted. Level 0 is the highest priority interrupt, and level 7 is the lowest priority interrupt (see Table 2.6-1). Therefore, for an interrupt to be accepted, its level value must be smaller than the current ILM value. When an interrupt is accepted, the level value of that interrupt is set in ILM. Thus, a subsequent interrupt of the same or lower level cannot be accepted. All ILMs are initialized to "0" by a reset. An instruction may transfer an 8-bit immediate value to the ILM register, but only the lower 3 bits of that data are used. Figure 2.6-9 Interrupt Level Mask Register (ILM) Initial value 38 ILM2 ILM1 ILM0 0 0 0 : ILM FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 2 CPU 2.6 Registers MB90330A Series Table 2.6-1 Levels Indicated by the Interrupt Level Mask Register (ILM) ILM2 ILM1 ILM0 Level value 0 0 0 0 Interrupts disabled 0 0 1 1 Level value less than 1 (0 only) 0 1 0 2 Level value less than 2 (0 and 1) 0 1 1 3 Level value less than 3 (0, 1 and 2) 1 0 0 4 Level value less than 4 (0, 1, 2 and 3) 1 0 1 5 Level value less than 5 (0, 1, 2, 3 and 4) 1 1 0 6 Level value less than 6 (0, 1, 2, 3, 4 and 5) 1 1 1 7 Level value less than 7 (0, 1, 2, 3, 4, 5 and 6) CM44-10129-6E Acceptable interrupt level FUJITSU MICROELECTRONICS LIMITED 39 CHAPTER 2 CPU 2.6 Registers 2.6.4 MB90330A Series Program Counter (PC) Program counter (PC) shows lower 16-bit of the memory address of the instruction code that CPU should execute. ■ Program Counter (PC) The program counter (PC) register is a 16-bit counter that indicates the lower 16 bits of the memory address of an instruction code to be executed by the CPU. The upper 8 bits of the address are indicated by the PCB. The PC register is updated by a conditional branch instruction, subroutine call instruction, interrupt, or reset. The PC register can also be used as a base pointer for operand access. Figure 2.6-10 shows the program counter. Figure 2.6-10 Program Counter PCB FEH PC ABCDH Next instruction to be executed FEABCDH 40 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 2 CPU 2.6 Registers MB90330A Series 2.6.5 Bank Registers (PCB, DTB, USB, SSB, ADB) The bank register shows the memory bank where the program space, the data space, the user stack space, the system stack space, and the Additional space are arranged. ■ Bank Registers (PCB, DTB, USB, SSB, ADB) The bank registers includes the following five registers. • Program Count Bank Register (PCB) <Initial Value: Value in Reset Vector> • Data bank register (DTB) < Initial value: 00H > • User stack bank register (USB) < Initial value: 00H > • System stack bank register (SSB) < Initial value: 00H > • Additional data bank register (ADB) < Initial value: 00H > Each bank register indicates memory banks to which PC, DT, SP (user), SP (system), and AD space are allocated. All bank registers has a length of 1 byte. They are initialized to "00H" by a reset. Bank registers other than PCB can be read. PCB can be read, but writing to PCB is not permitted. PCB is updated either when the JMPP, CALLP, RETP, RETI, or RETF instruction that branches is executed, and it may then branch to an entire 16-M bytes space. PCB is also updated when an interrupt occurs. For information on the operation of each register, see Section "2.2 Memory Space". CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 41 CHAPTER 2 CPU 2.6 Registers 2.6.6 MB90330A Series Direct Page Register (DPR) This section explains the direct page register (DPR) functions. ■ Direct Page Register (DPR) <Initial Value: 01H> The direct page register (DPR) specifies, as shown in Figure 2.6-11, addresses 8 to 15 of an instruction operand in the direct addressing mode. DPR has a length of 8 bits, and is initialized to "01H" by a reset. It also allows reading and writing by instructions. Figure 2.6-11 illustrates the generation of a physical address in the direct addressing mode. Figure 2.6-11 Generating a Physical Address in Direct Addressing Mode DTB register DPR register MSB Direct address in instruction LSB 24-bit physical address 42 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 2 CPU 2.7 Register Bank MB90330A Series 2.7 Register Bank A register bank that consists of 8 words can be used as the general-purpose registers for the arithmetic operations or as the pointers for the instructions, such as byte registers (R0 to R7), word registers (RW0 to RW7), and long word registers (RL0 to RL3). In addition, RL0 to RL3 can also be used as the linear pointers to access directly to the entire space in the memory space. ■ Register Bank Table 2.7-1 lists the register functions. Table 2.7-2 shows the relationship between each register. In the same manner as for an ordinary RAM area, the register bank values are not initialized by a reset. The status before a reset is maintained. When the power is turned-on, however, the register bank will have an undefined value. Table 2.7-1 Register Functions Used as operands of instructions. Note: R0 is also used as a counter for barrel shift or normalization instruction R0 to R7 RW0 to RW7 Used as pointers and operands of instructions. Note: RW0 is used as a counter for string instructions. RL0 to RL3 Used as long pointers and operands of instructions. Table 2.7-2 Relationship between Registers Address Byte register 000180H + RP × 10H + 0 Long word register RW0 000180H + RP × 10H + 1 RL0 000180H + RP × 10H + 2 RW1 000180H + RP × 10H + 3 000180H + RP × 10H + 4 RW2 000180H + RP × 10H + 5 RL1 000180H + RP × 10H + 6 RW3 000180H + RP × 10H + 7 000180H + RP × 10H + 8 R0 000180H + RP × 10H + 9 R1 000180H + RP × 10H + 10 R2 000180H + RP × 10H + 11 R3 000180H + RP × 10H + 12 R4 000180H + RP × 10H + 13 R5 000180H + RP × 10H + 14 R6 000180H + RP × 10H + 15 R7 CM44-10129-6E Word register RW4 RL2 RW5 RW6 RL3 RW7 FUJITSU MICROELECTRONICS LIMITED 43 CHAPTER 2 CPU 2.8 Prefix Codes 2.8 MB90330A Series Prefix Codes Placing a prefix code before an instruction can partially change the operation of the instruction. 3 types of prefix codes can be used: bank select prefix, common register bank prefix, and flag change disable prefix. ■ Bank Select Prefix The memory space used for accessing data depends on each addressing mode. When a bank select prefix is placed before an instruction, the memory space used for accessing data by that instruction can be selected regardless of the addressing mode. Table 2.8-1 shows the bank select prefixes and selected memory spaces. Table 2.8-1 Bank Select Prefix Bank select prefix Selected space PCB PC space DTB Data space ADB AD space SPB Either the SSP or USP space is used according to the stack flag value. Use the following instructions with care: ● String instructions (MOVS / MOVSW / SCEQ / SCWEQ / FILS / FILSW) The bank register specified by an operand is used regardless of the prefix. ● Stack manipulation instructions (PUSHW / POPW) SSB or USB is used according to the S flag regardless of the prefix. ● I/O access instructions MOV A,io MOV io,#imm8 CLRB io:bp MOV io,A MOVW io,#imm16 BBC io:bp,rel MOVX A,io MOVB A,io:bp BBS io:bp,rel MOVW A,io MOVB io:bp,A WBTC MOVW io,A SETB io:bp WBTS The I/O space of the bank is used regardless of the prefix. ● Flag change instructions (AND CCR,#imm8 / OR CCR,#imm8) The instruction is executed normally, but the prefix affects the next instruction. 44 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 2 CPU 2.8 Prefix Codes MB90330A Series ● POPW PS Either SSB or USB is used according to the S flag regardless of the prefix. The prefix affects the next instruction. ● MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. ● RETI SSB is used regardless of the prefix. ■ Common Register Bank Prefix (CMR) To simplify data exchange between multiple tasks, the same register bank must be accessed regardless of the RP value. When the common register bank prefix (CMR) is placed before an instruction that accesses the register bank, that instruction accesses the common bank (the register bank selected when RP=0) at addresses from 000180H to 00018FH regardless of the current RP value. Use the following instructions with care: ● String instructions (MOVS / MOVSW / SCEQ / SCWEQ / FILS / FILSW) If an interrupt request occurs during execution of a string instruction with a prefix code, the string instruction is executed falsely because the prefix becomes invalid for the string instruction after the interrupt is returned. Do not attach CMR prefix to any of the above string instructions. ● Flag change instructions (AND CCR,#imm8 / OR CCR,#imm8 / POPW PS) The instruction is executed normally, but the prefix affects the next instruction. ● MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. ■ Flag Change Disable Prefix (NCC) To disable a flag change, use the flag change disable prefix code (NCC). Placing NCC before an instruction that disables an unwanted flag change can disable flag changes associated with that instruction. Use the following instructions with care: ● String instructions (MOVS / MOVSW / SCEQ / SCWEQ / FILS / FILSW) If an interrupt request occurs during execution of a string instruction with a prefix code, the string instruction is executed falsely because the prefix becomes invalid for the string instruction after the interrupt is returned. Do not attach NCC prefix to any of the above string instructions. ● Flag change instructions (AND CCR,#imm8 / OR CCR,#imm8 / POPW PS) The instruction is executed normally, but the prefix affects the next instruction. ● Interrupt instructions (INT #vct8 / INT9 / INT addr16 / INTP addr24 / RETI) CCR changes according to the instruction specifications regardless of the prefix. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 45 CHAPTER 2 CPU 2.8 Prefix Codes MB90330A Series ● JCTX @A CCR changes according to the instruction specifications regardless of the prefix. ● MOV ILM,imm8 The instruction is executed normally, but the prefix affects the next instruction. 46 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 2 CPU 2.9 Interrupt Disable Instructions MB90330A Series 2.9 Interrupt Disable Instructions Interrupt requests are not accepted about following 10 instructions: MOV ILM, #imm8 AND CCR, #imm8 PCB ADB SPB CMR OR CCR, #imm8 POPW PS NCC DTB ■ Interrupt Disable Instructions As shown in Figure 2.9-1, if a valid hardware interrupt request occurs during execution of any of the above instructions, the interrupt can be processed only when an instruction other than the above is executed. Figure 2.9-1 Interrupt Disable Instructions Interrupt disable instructions •••••••• ••• (a) (a) : Ordinary instruction Interrupt request generated Interrupt accepted ■ Restrictions on Interrupt Disable Instructions and Prefix Instructions As shown in Figure 2.9-2, when a prefix code is placed before an interrupt disable instruction, the prefix code affects the first instruction after the code other than the interrupt disable instruction. Figure 2.9-2 Interrupt Disable Instructions and Prefix Codes Interrupt disable instructions MOV A, FFH NCC •••• MOV ILM,#imm8 ADD A,01H CCR:XXX10XXB CCR:XXX10XXB CCR does not change with NCC. ■ Consecutive Prefix Codes As shown in Figure 2.9-3, when competitive prefix codes are placed consecutively, the latter one becomes valid. Competitive prefix codes are PCB, ADB, DTB, and SPB. Figure 2.9-3 Consecutive Prefix Codes Prefix codes ••••• ADB DTB PCB ADD A,01H ••••• PCB becomes valid as the prefix code CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 47 CHAPTER 2 CPU 2.9 Interrupt Disable Instructions 48 MB90330A Series FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT This chapter describes the interruption, extended intelligent I/O service (EI2OS), and direct memory access controller (μDMAC) of MB90330A Series. 3.1 Outline of Interrupt 3.2 Interrupt Cause and Interrupt Vector 3.3 Interrupt Control Register and Peripheral Function 3.4 Hardware Interrupt 3.5 Software Interrupt 3.6 Interrupts by Extended Intelligent I/O Service (EI2OS) 3.7 Exception Processing Interrupt 3.8 Interruption by μDMAC 3.9 Exceptions 3.10 Stack Operation of Interrupt Processing 3.11 Program Example of Interrupt Processing 3.12 Delayed Interrupt Generation Module CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 49 CHAPTER 3 INTERRUPT 3.1 Outline of Interrupt 3.1 MB90330A Series Outline of Interrupt F2MC-16LX has the following five interrupt functions, which suspend the current process when an event occurs and transfer control to a separately defined program. • Hardware Interrupt • Software interrupt • Interrupts by extended intelligent I/O service (EI2OS) • Interruption by μDMAC • Exception processing ■ Type and Function of Interrupt ● Hardware Interrupt Transfers control to the user-defined interrupt handling program in response to an interrupt request from a peripheral function. Figure 3.1-1 Overview of Hardware Interrupts PS Register file I ILM Microcode Check AND Cause FF Interrupt level IL Peripheral Enable FF 50 Comparator PS : Processor status I : Interrupt enable flag ILM : Interrupt level mask register IR : Instruction register F2MC-16LX CPU Level comparator F2MC-16LX bus IR Interrupt controller FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.1 Outline of Interrupt MB90330A Series ● Software interrupt Transfers control to the user-defined interrupt handing program by executing the instruction dedicated to software interrupt (for example, INT instruction). Figure 3.1-2 Overview of Software Interrupts PS Register file I F2MC-16LX bus IR S PS I S ILM IR B unit B unit Microcode Queue F2MC-16LX CPU ILM Fetch : Processor status : Interrupt enable flag : Stack flag : Interrupt level mask register : Instruction register : Bus interface unit Save Instruction bus RAM ● Interrupts by extended intelligent I/O service (EI2OS) EI2OS is involved in automatic data transfer between peripheral functions and memory. EI2OS is capable of performing data transfer like DMA (direct memory access) although it was previously performed by the interrupt handling program. Once the data transfer process has been performed the specified number of times, EI2OS automatically executes the interrupt handling program. Interruption by EI2OS is a type of hardware interrupt. Figure 3.1-3 Overview of the Extended Intelligent I/O Service (EI2OS) Memory space by IOA I/O register I/O register Peripheral Interrupt request CPU by ICS ISD Interrupt control register Interrupt controller by BAP Buffer CM44-10129-6E by DCT I/O requests transfer The interrupt controller selects the descriptor. The transfer source and destination are read from the descriptor. Data is transferred between I/O and memory. FUJITSU MICROELECTRONICS LIMITED 51 CHAPTER 3 INTERRUPT 3.1 Outline of Interrupt MB90330A Series ● Interruption by μDMAC μDMAC is involved in automatic data transfer between peripheral functions and memory. EI2OS performs data transfer by DMA transfer although it was previously performed by the interrupt handling program. Once the data transfer process has been performed the specified number of times, μDMAC automatically executes the interrupt handling program. Interruption by μDMAC is a type of hardware interrupt. Figure 3.1-4 Overview of the Direct Memory access (DMA) Memory space IOA I/O register I/O register (4) (a) RAM for descriptor Peripheral function (I/O) (1) (2) (3) DMA controller (2) DMA descriptor (4) (b) BAP Buffer CPU Interrupt controller DCT IOA: I/O address pointer BAP: Buffer address pointer DER: DMA enable register DCT: Data counter (1) The peripheral resource (I/O) requests DMA transfer. (2) When the corresponding bit of DMA enable register (DER) is "1", DMAC reads from the descriptor the transfer data such as the transfer source address, transfer destination address, and transfer count of specified channels. (3) DMA data transfer is started between I/O and memory. (4) After one item (either Byte data or Word data) transferred. (a) Transfer has not been completed (DCT does not reached to 0): μDMAC requests to clear the DMA transfer request to the peripheral resouece. (b) At transfer end (DCT reached to 0): After completion of DMA transfer, the flag indicating completion of transfer is set in the DMA status register, outputting an interrupt request to the interrupt controller. Note: Write access to the internal registers DCSR, DSRH, DSRL, DSSR, DERH, and DERL is prohibited during DMA transfer. ● Exception processing Exception processing, basically the same as interrupt, is executed when an exception item (execution of an undefined instruction) is detected at an instruction-to-instruction boundary; the normal process is suspended for this purpose. Equivalent to software interrupt instruction "INT10". 52 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.2 Interrupt Cause and Interrupt Vector MB90330A Series 3.2 Interrupt Cause and Interrupt Vector F2MC-16LX has functions that are associated with 256 types of interrupt causes, and 256 interrupt vector tables are assigned to the most significant address area of memory. This interruption vector is shared by all the interruptions. All of interrupt INT0 to INT255 are available for software interrupt, although some interrupt vectors are shared with hardware interrupt or exception processing interrupt. Furthermore, for hardware interrupt, the fixed interrupt vectors and interrupt control registers (ICR) are used for each of the peripheral functions. ■ Interrupt Vector The interrupt vector table referenced during interrupt processing is assigned to the most significant of memory address area (FFFC00H to FFFFFFH). Furthermore, the interrupt vectors share the same area with EI2OS, μDMAC, hardware interrupt, software interrupts, and exception processing. Table 3.2-1 shows the allocation of the interrupt numbers and interrupt vectors. Table 3.2-1 Interrupt Vector List Software interrupt instruction Vector address L Vector address M Vector address H Mode data Interrupt number Hardware interrupt INT0 FFFFFCH FFFFFDH FFFFFEH Unused #0 None : : : : : : : INT7 FFFFE0H FFFFE1H FFFFE2H Unused #7 None INT8 FFFFDCH FFFFDDH FFFFDEH FFFFDFH #8 (RESET vector) INT9 FFFFD8H FFFFD9H FFFFDAH Unused #9 None INT10 FFFFD4H FFFFD5H FFFFD6H Unused #10 <Exception processing> INT11 FFFFD0H FFFFD1H FFFFD2H Unused #11 Hardware Interrupt #0 INT12 FFFFCCH FFFFCDH FFFFCEH Unused #12 Hardware Interrupt #1 INT13 FFFFC8H FFFFC9H FFFFCAH Unused #13 Hardware Interrupt #2 INT14 FFFFC4H FFFFC5H FFFFC6H Unused #14 Hardware Interrupt #3 : : : : : : : INT254 FFFC04H FFFC05H FFFC06H Unused #254 None INT255 FFFC00H FFFC01H FFFC02H Unused #255 None Reference: It is recommended that the unused interrupt vectors are set in the exception processing addresses, etc. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 53 CHAPTER 3 INTERRUPT 3.2 Interrupt Cause and Interrupt Vector MB90330A Series ■ Interrupt Factors, Interrupt Vectors, and Interrupt Control Registers Table 3.2-2 shows the relationship between the causes of interrupts except software interrupt, and the interrupt vectors and control registers. Table 3.2-2 Interrupt Factors, Interrupt Vectors, and Interrupt Control Registers Interrupt cause EI2OScorresponded μDMACcorresponded Interrupt vector Interrupt control registers *2 Number Address ICR Address 08H FFFFDCH - - Reset #08 INT9 instruction #09 09H FFFFD8H - - Exception processing #10 0AH FFFFD4H - - USB function 1 0,1 #11 0BH FFFFD0H USB function 2 2 to 6 *3 #12 0CH FFFFCCH USB function 3 #13 0DH FFFFC8H USB function 4 #14 0EH FFFFC4H USB HOST 1 #15 0FH FFFFC0H USB HOST 2 #16 10H FFFFBCH #17 11H FFFFB8H #18 12H FFFFB4H #19 13H FFFFB0H #20 14H FFFFACH #21 15H FFFFA8H #22 16H FFFFA4H #23 17H FFFFA0H #24 18H FFFF9CH #25 19H FFFF98H #26 1AH FFFF94H #27 1BH FFFF90H 2 I C ch.0 DTP/ External interruption ch.0/ch.1 ❍ 2 I C ch.1 DTP/ External interruption ch.2/ch.3 ❍ I2C ch.2 DTP/ External interruption ch.4/ch.5 ❍ PWC/reload timer ch.0 Δ DTP/ External interruption ch.6/ch.7 Δ Input capture ch.0./ch.1 Δ Reload timer ch.1 Δ Input capture ch.2/ch.3 Δ Reload timer ch.2 Δ #28 1CH FFFF8CH Output compare ch.0/ch.1 ❍ #29 1DH FFFF88H #30 1EH FFFF84H #31 1FH FFFF80H 14 7 8 PPG ch.0/ch.1 Output compare ch.2/ch.3 ❍ PPG ch.2/ch.3 UART transmission end ch.2/ch.3 ❍ #32 20H FFFF7CH #33 21H FFFF78H #34 22H FFFF74H 10 #35 23H FFFF70H 11 PPG ch.4/ch.5 UART1 reception ch.2/ch.3 A/D conversion and free-run timer Δ 15 #36 24H FFFF6CH UART1 transmission ch.0/ch.1 ❍ 13 #37 25H FFFF68H Extended serial I/O 9 #38 26H FFFF64H UART1 reception ch.0/ch.1 12 #39 27H FFFF60H Time-base timer/Watch timer #40 28H FFFF5CH Writing and Erasing Flash Memory #41 29H FFFF58H Delay interruption generation module #42 2AH FFFF54H 54 Priority FUJITSU MICROELECTRONICS LIMITED High ICR00 0000B0 *1 H ICR01 0000B1 *1 H ICR02 0000B2 *1 H ICR03 0000B3 *1 H ICR04 0000B4 *1 H ICR05 0000B5 *1 H ICR06 0000B6 *1 H ICR07 0000B7 *1 H ICR08 0000B8 *1 H ICR09 0000B9 *1 H ICR10 0000BA *1 H ICR11 0000BB *1 H ICR12 0000BC *1 H ICR13 0000BD *1 H ICR14 0000BE *1 H ICR15 0000BF *1 H Low CM44-10129-6E CHAPTER 3 INTERRUPT 3.2 Interrupt Cause and Interrupt Vector MB90330A Series : Available. With EI2OS stop function. (The interrupt request flag is cleared by the interrupt clear signal. With a stop request.) ❍: Available. (The interrupt request flag is cleared by the interrupt clear signal.) Δ: Available when not using the interrupt factor shared with ICR : Not available *1: The interrupt levels for the peripheral functions sharing the ICRs are identical. *2: The priority is given when interrupts with the same level are generated simultaneously. *3: Ch.2 and ch.3 can use even when USB HOST is operated. Notes: • If use of EI2OS is permitted when a same interrupt control register (ICR) has two interrupt causes, EI2OS is activated when either of interrupt causes is detected. Any interrupt which is due to a non-activation cause is masked during activation of EI2OS. It is therefore recommended that either of the interrupt requests be masked while EI2OS is in use. • In a resource for which two interrupt causes exist in a same interrupt control register (ICR), the interrupt flag is cleared by the EI2OS interrupt clear signal. • If two interrupt causes were found at a single interrupt number, both the interrupt request flags in the resource are cleared by the μDMAC interrupt clear signal. Thus, if the μDMAC function is used for one of the two causes, the other interrupt function will not be available. Set the interrupt request permission bit to "0" in the appropriate resource, and take measures by software polling processing. ■ Type and Function of USB interrupt USB interrupt factor USB function 1 USB function 2 USB function 3 USB function 4 USB HOST 1 USB HOST 2 Details End point0-IN End Point0-OUT End Point1-5* SUSP SOF BRST WKUP CONF SPK DIRQ CNNIRQ URIRQ RWKIRQ SOFIRQ CMPIRQ *: End Point 1, 2 can use even when USB HOST is operated. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 55 CHAPTER 3 INTERRUPT 3.3 Interrupt Control Register and Peripheral Function 3.3 MB90330A Series Interrupt Control Register and Peripheral Function Interrupt control registers (ICR00 to ICR15) located in the interrupt controller, are associated with all the peripheral functions which have the interrupt function. This register controls the interrupt and the extended intelligent I/O service (EI2OS). ■ Interrupt Control Register List Table 3.3-1 shows the list of the peripheral functions associated with the interrupt control registers. Table 3.3-1 Interrupt Control Register List Address Registers Abbreviation 0000B0H Interrupt control registers 00 ICR00 USB function 1 and USB function 2 0000B1H Interrupt control registers 01 ICR01 USB function 3 and USB function 4 0000B2H Interrupt control registers 02 ICR02 USB HOST 1 and USB HOST 2 0000B3H Interrupt control registers 03 ICR03 I2C ch.0, DTP External interruption ch.0/ch.1 0000B4H Interrupt control registers 04 ICR04 I2C ch.1, DTP External interruption ch.2/ch.3 0000B5H Interrupt control registers 05 ICR05 I2C ch.2, DTP External interruption ch.4/ch.5 0000B6H Interrupt control registers 06 ICR06 PWC, reload timer ch.0, DTP external interruption ch.6/ch.7 0000B7H Interrupt control registers 07 ICR07 Input capture ch.0/ch.1 and reload timer ch.1 0000B8H Interrupt control registers 08 ICR08 Input capture ch.2/ch.3, and reload timer ch.2 0000B9H Interrupt control registers 09 ICR09 Output compare ch.0/ch.1, PPG ch.0/ch.1 0000BAH Interrupt control registers 10 ICR10 Output compare ch.2/ch.3, PPG ch.2/ch.3 0000BBH Interrupt control registers 11 ICR11 UART Transmission ch.2/ch.3, PPG ch.4/ch.5 0000BCH Interrupt control registers 12 ICR12 UART reception ch.2/ch.3, AD conversion, and free-run timer 0000BDH Interrupt control registers 13 ICR13 UART transmission ch.0/ch.1 and extended serial I/O 0000BEH Interrupt control registers 14 ICR14 UART reception ch.0/ch.1, timer base timer, and watch timer 0000BFH Interrupt control registers 15 ICR15 Flash writing and delay interruption generation module 56 Corresponding peripheral function FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.3 Interrupt Control Register and Peripheral Function MB90330A Series ■ Interrupt Control Register Functions Each of the interrupt control register (ICR) has the following four functions. • Setting of interrupt level for peripheral function • Selection of whether to perform normal interrupt or external intelligent for corresponding peripheral function (EI2OS) • Select the channel of Extended Intelligent I/O service (EI2OS) • Display of extended intelligent I/O service (EI2OS) status For the interrupt control registers (ICRs), some functions are different between write and read. Details are shown in Figure 3.1-1 and Figure 3.1-2 in Section "3.3.1 Interrupt Control Registers (ICR00 to ICR15)". Note: Do not use any read modify write instruction to access the interrupt control register (ICR). An attempt of this may cause a malfunction. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 57 CHAPTER 3 INTERRUPT 3.3 Interrupt Control Register and Peripheral Function 3.3.1 MB90330A Series Interrupt Control Registers (ICR00 to ICR15) Interrupt control registers (ICR00 to ICR15) associated with all the peripheral functions provided with the interrupt function, controls the handling which takes place when an interrupt request is generated. Some functions of the registers are different between write and read. ■ Interrupt Control Registers (ICR00 to ICR15) Figure 3.3-1 Interrupt Control Register (ICR00 to ICR15) at Writing At write Address MSB LSB 0000B0H to ICS3 ICS2 ICS1 ICS0 0000BFH ISE IL2 IL1 IL2 0 IL0 Initial value 00000111B Interrupt level set bit Interrupt level 0 (Highest) IL1 IL0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Interrupt level 7 (No interrupt) ISE EI2OS enable bit 0 Activate interrupt sequence during generation of an interrupt. 1 Activate EI2OS during generation of an interrupt. ICS3 ICS2 ICS1ICS0 MSB : The most significant bit LSB : The least significant bit : Initial value 58 EI2OS channel select bit Channel Descriptor address 0 0 0 0 0 0 0 1 0 000100H 1 0 0 1 0 2 000108H 000110H 0 0 1 1 3 000118H 0 1 0 0 4 000120H 0 1 0 1 5 000128H 0 1 1 0 6 000130H 0 1 1 1 7 000138H 1 0 0 0 8 000140H 1 0 0 1 9 000148H 1 0 1 0 10 000150H 1 0 1 1 11 000158H 1 1 0 0 12 1 1 0 1 13 000160H 000168H 1 1 1 0 14 000170H 1 1 1 1 15 000178H FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.3 Interrupt Control Register and Peripheral Function MB90330A Series Figure 3.3-2 Interrupt Control Register (ICR00 to ICR15) at Read At read Address MSB 0000B0 H to 0000BF H LSB S1 S0 ISE IL2 IL1 IL2 IL1 IL0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 : Undefined : Initial value CM44-10129-6E - - 000111B Interrupt level set bit Interrupt level 0 (Highest) Interrupt level 7 (No interrupt) EI2OS enable bit ISE 0 Activate interrupt sequence during generation of an interrupt. 1 Activate EI2OS during generation of an interrupt. S1 MSB : The most significant bit LSB : The least significant bit IL0 Initial value EI2OS status S0 2 0 0 EI OS operation in progress or EI2OS not activated 0 1 Stop status by count end 1 0 Reserved 1 1 Stop status by request from peripheral function FUJITSU MICROELECTRONICS LIMITED 59 CHAPTER 3 INTERRUPT 3.3 Interrupt Control Register and Peripheral Function 3.3.2 MB90330A Series Interrupt Control Register Functions Each of the interrupt control register (ICR00 to ICR15) consists of the following bits, which have four functions. • Interrupt level set bit (IL2 to IL0) • EI2OS enable bit (ISE) • EI2OS channel select bits (ICS3 to ICS0) • EI2OS status bit (S1, S0) ■ Configuration of Interrupt Control Register (ICR) Figure 3.3-3 shows the bit configuration of the interrupt control register (ICR). Figure 3.3-3 Configuration of Interrupt Control Register (ICR) Writing to Interrupt control register (ICR) Address 0000B0H to 0000BFH MSB LSB ICS3 ICS2 ICS1 ICS0 ISE Reading to Interrupt control register (ICR) MSB Address 0000B0H S0 S1 to IL2 IL1 IL0 LSB ISE IL2 IL1 IL0 0000BFH Initial value 00000111B Initial value --000111B MSB : The most significant bit LSB : The least significant bit : Undefined References: • ICS3 to ICS0 bit are enabled only when starting the extended intelligent I/O service (EI2OS). If EI2OS is to be activated, set the ISE bit to "1". Otherwise, set it to "0". When you do not start EI2OS, you can not set ICS3 to ICS0. • ICS1 and ICS0 are enabled only for write. S1 and S0 are enabled only for read. Note: Reading the upper rank two-bit is an irregular value. 60 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.3 Interrupt Control Register and Peripheral Function MB90330A Series ■ Interrupt Control Register Functions ● Interrupt level set bit (IL2 to IL0) Specifies the interrupt level for the associated peripheral function. Initialized to level 7 (no interrupts) by reset. Table 3.3-2 shows the relationship between the interrupt level set bits and each interrupt level. Table 3.3-2 Correspondence between Interrupt Level Set Bits and Interrupt Levels IL2 IL1 IL0 Interrupt level 0 0 0 0 (highest interrupt) 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 6 (lowest interrupt) 1 1 1 7 (No interrupt) ● EI2OS enable bit (ISE) If the ISE bit is "1" during generation of an interrupt request, EI2OS is activated; if it is "0", the interrupt sequence will be activated. Furthermore, when the end condition of EI2OS is satisfied, (both the S1 and S0 bits are other than "00B"), the ISE bit is cleared. If the associated peripheral function does not have the EI2OS function, the ISE bit must have been set to "0" by software. The ISE bit is initialized to "0" by reset by "0000B". ● EI2OS channel select bits (ICS3 to ICS0) Specifies the channel of EI2OS with a write only bit. The address of the EI2OS descriptor is determined by the value set here. The ICS bit is initialized to "0000B" by reset by. Table 3.3-3 shows the correspondence between the EI2OS channel select bits and descriptor addresses. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 61 CHAPTER 3 INTERRUPT 3.3 Interrupt Control Register and Peripheral Function MB90330A Series Table 3.3-3 Correspondence between EI2OS Channel Select Bits and Descriptor Addresses ICS3 ICS2 ICS1 ICS0 Channel to be selected Descriptor address 0 0 0 0 0 000100H 0 0 0 1 1 000108H 0 0 1 0 2 000110H 0 0 1 1 3 000118H 0 1 0 0 4 000120H 0 1 0 1 5 000128H 0 1 1 0 6 000130H 0 1 1 1 7 000138H 1 0 0 0 8 000140H 1 0 0 1 9 000148H 1 0 1 0 10 000150H 1 0 1 1 11 000158H 1 1 0 0 12 000160H 1 1 0 1 13 000168H 1 1 1 0 14 000170H 1 1 1 1 15 000178H ● EI2OS status bits (S1 and S0) It is a bit only for reading. By examining the value at the end of EI2OS operation, the operating state and/or termination status can be determined. The bit is initialized to "00B" at a reset. Table 3.3-4 shows the relationships between the S0/S1 bit and the EI2OS status. Table 3.3-4 Relation between EI2OS Status Bits and EI2OS Status 62 EI2OS status S1 S0 0 0 When EI2OS in operation or not started. 0 1 Stop state by end of counting 1 0 Reserved 1 1 Stop state by request from peripheral function FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90330A Series 3.4 Hardware Interrupt Hardware interrupt suspends the active program execution by the CPU in response to an interrupt request signal generated by a peripheral function, resulting in transfer of control to the user-defined interrupt handling program. Extended intelligent I/O service (EI2OS), μDMAC, external interrupts, and other similar processes are also executed as a type of hardware interrupt. ■ Function of Hardware Interrupt ● Function of hardware interrupt Hardware interrupt makes comparison between the interrupt level of the interrupt request signal which a peripheral function outputs and the interrupt level mask register (ILM) in the CPU's processor status (PS). This interrupt also refers the contents of the I flag in PS, by hardware, to determine whether the interrupt is acceptable. Once the hardware interrupt is accepted, the contents of the registers and their related data in the CPU are automatically saved in the system stack. The level of the currently requested interrupt is stored in the ILM. Then, control branches to the associated interrupt vector. ● Multiple interrupts Multiple hardware interrupts can be activated. ● EI2OS At the completion of transfer, a hardware interrupt is activated although EI2OS is an automatic transfer function between EI2OS/memory and I/O. Further, EI2OS cannot be activated in a multiple manner. While an EI2OS process is in progress, all the other interrupt requests and μDMAC requests remain pending. ● μDMAC At the completion of transfer, a hardware interrupt is activated although μDMAC is an automatic transfer function between memory and I/O. Further, μDMAC cannot be activated in a multiple manner. While an μDMAC process is in progress, all the other interrupt requests and EI2OS requests remain pending. ● External interrupt The external interrupt (including a wake-up interrupt) is accepted as a hardware interrupt through the peripheral function (its interrupt request detector circuit). ● Interrupt vector The interrupt vector table, referred during execution of the interrupt process, is assigned to the "FFFC00H" to "FFFFFFH" memory for shared with software interrupt. For allocations of interrupt numbers and interrupt vectors, see Section "3.2 Interrupt Cause and Interrupt Vector". CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 63 CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90330A Series ■ Construction of Hardware Interrupt As shown in Table 3.4-1, there are four features related to hardware interrupt. These four must be programmed when hardware interrupt is used. Table 3.4-1 Mechanism Related to Hardware Interrupt Mechanism related to hardware interrupt Functions Peripheral function Interrupt enable bits, interrupt request bits Controls interrupt request from peripheral function Interrupt controller Interrupt control registers (ICR) Setting interrupt levels Interrupt enable flag (I) Identification of interrupt enable state Interrupt level mask register (ILM) Compares request interrupt level and current interrupt level Microcode Execution of interruption handling routine Interrupt vector table Stores the branch destination address at interrupt processing CPU FFFC00H to FFFFFFH in memory ■ Hardware Interrupt Suppression For hardware interrupt, acceptance of the interrupt request is suppressed in the following conditions: ● Suppressing a hardware interrupt which is generated during write to a peripheral function control register area While data is being written to a peripheral function control register area, no hardware interrupt request is accepted. The purpose of this is to prevent the CPU from causing a malfunction due to some interruptrelated problem in response to an interrupt request which is generated while the interrupt control register relation for each resource is being rewritten. The peripheral function control register area is the area assigned to the control and data registers of the peripheral function control registers. Note that they are not the "000000H" to "0000FFH" I/O addressing area. Figure 3.4-1 shows the hardware interrupt operation which takes place during write to the peripheral function control register area. Figure 3.4-1 Hardware Interrupt Request during Write to the Peripheral Function Control Register Area Instruction of writing to peripheral function control register area MOV A.#08 MOV io,A generating interrupt request here 64 MOV A,2000H not branch to interrupt FUJITSU MICROELECTRONICS LIMITED Interrupt processing branch to interrupt CM44-10129-6E CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90330A Series ● Hardware interrupt suppression of interrupt suppression instruction Table 3.4-2 shows the hardware interrupt suppression instruction. If the hardware interrupt request is generated during execution of hardware interrupt suppression instruction, an interrupt is processed after execution of hardware interrupt suppression instruction and then other instruction. Table 3.4-2 Hardware Interrupt Suppression Instruction Prefix code The instructions which do not accept the interrupt and hold requests. PCB DTB ADB SPB CMR NCC Interruption/holding control instruction (The command that delays the effect of prefix code) MOV ILM,#imm8 OR CCR,#imm8 AND CCR,#imm8 POPW PS ● Suppressing a hardware interrupt during execution of a software interrupt When a software interrupt is activated, no other interrupt requests are acceptable to clear the I flag to "0". CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 65 CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt 3.4.1 MB90330A Series Operation of Hardware Interrupt The following describes the operation sequence from generation of a hardware interrupt request to completion of interrupt handling. ■ Start of Hardware Interrupt ● Operation of peripheral function (generation of interrupt request) Any peripheral function provided with the hardware interrupt request function has "interrupt request flag" and "interrupt enable flag". The interrupt request flag indicates whether an interrupt request has been generated or not. The interrupt enable flag indicates whether an interrupt request is enabled or disabled. The interrupt request flag is set by occurrence of an specific event to the peripheral function. It causes an interrupt request to the interrupt controller when the interrupt enable flag indicates "enable". ● Operation of Interrupt controller (Control of interrupt request) The interrupt controller makes a comparison between interrupt levels (ILs) of the simultaneously received interrupt requests. It adopts the highest-level request, (the request with the smallest IL value), and notifies it to the CPU. If two or more requests at the same level are found, the highest priority is given to the request with the smallest interrupt number. ● CPU operation (Interrupt request acceptance and interrupt processing) The CPU compares the received interrupt level (IL2 to IL0 of ICR) with the contents of the interrupt level mask (ILM) register. If IL < ILM and the interrupt has been enabled (CCR I = 1), the currently active instruction terminates, the interrupt handling microcode is then activated to execute the interrupt handling. First, the interrupt handling saves the contents of the dedicated registers (12 bytes of A, DPR, ADB, DTB, PCB, PC, and PS) in the system stack (system stack space indicated by SSB and SSP). Next, the interrupt handling loads to the program counters (PCB and PC) of the interrupt vector, and updates the ILM. It also sets the stack flag (S) (setting CCR:S = 1 to enable the system stack). ■ Return from Hardware Interrupt When the interrupt request flag of the peripheral function causing the interrupt is cleared, and the RETI instruction is executed in the interrupt handling program, the 12-byte data saved in the system stack returns to the dedicated registers. Control then returns to the process which was being executed before the interrupt branch. By clearing the interrupt request flag, the interrupt request which the peripheral function has output to the interrupt controller is canceled automatically. 66 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90330A Series ■ Operation of Hardware Interrupt Figure 3.4-2 shows the operation sequence from generation of a hardware interrupt to completion of interrupt handling. Figure 3.4-2 Operation of Hardware Interrupt Internal bus PS PS, PC (7) ILM IR Microcode Check (6) F2MC-16LX I CPU Comparator (5) (4) Other peripheral function (3) Peripheral function generated Interrupt request Level comparator Enable FF AND Factor FF (8) Interrupt level IL (2) (1) Interrupt controller RAM IL : Interrupt level set bit of Interrupt control register (ICR) PS : Processor status I : Interrupt enable flag ILM: Interrupt level mask register IR : Instruction register FF : flip - flop (1) An interrupt cause occurs in a peripheral function. (2) The peripheral function interrupt enable bit is referred. If it indicates "enable", an interrupt request is output from the periphery to the interrupt controller. (3) After receiving the interrupt request, the interrupt controller determines the priorities of the simultaneously received interrupt requests. Then, the controller sends the ILs associated with the interrupt requests to the CPU. (4) The CPU compares the interrupt level requested from the interrupt controller with the interrupt level mask register (ILM). (5) If the comparison reveals that the priority is higher than the current interrupt handling level, the contents of the I flag of the condition code register (CCR) will be checked. (6) If the check in Item (5) reveals that the I flag indicates "enable", that is, I = 1, control waits for completion of the currently active instruction. The requested IL is set in the ILM on completion. (7) The contents of the register are saved before control branches to the interrupt handling routine. (8) The software in the interrupt handling routine clears the interrupt cause generated at 1 and executes the RETI instruction to complete the interrupt handling. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 67 CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt 3.4.2 MB90330A Series Operation Flow of Hardware Interrupt When the peripheral function generates an interrupt request, the interrupt controller notifies the CPU of the interrupt level. If the CPU is ready to accept the interrupt, it suspends the currently active instruction; the CPU then executes the interrupt handling routine or activates Extended Intelligent I/O service (EI2OS) μDMAC. Furthermore, if a software interrupt is generated by the INT instruction, the interrupt handling routine is executed independently of the CPU state. At this time, the hardware interrupt is prohibited. ■ Operation Flow of Hardware Interrupt Figure 3.4-3 shows the handling flow which takes place during interrupt operation. Figure 3.4-3 Handling Flow in the Interrupt Operation START NO ENx = 1 YES YES I & IF & IE = 1 AND ILM > IL Has the specified number of times been completed? Or did a peripheral function issue a complete request? YES NO ISE = 1 YES YES NO Fetch and decode next instruction INT instruction NO Saving PS, PC, PCB, DTB, DPR and A into the stack of SSP, and setting ILM=IL Expanded intelligent I/O service processing (EI2OS processing) NO Execute normal instruction NO Saving PS, PC, PCB, DTB, DPR and A into the stack of SSP, and setting ILM=IL Completion of string instruction repetition YES S Update PC I : Interrupt enable flag of Condition code register (CCR) IF : Interrupt request flag of peripheral function 1 Fetch interrupt vector S : Stack flag of Condition code register (CCR) ENx : DMA activation request flag of DMA enable register IE : Interrupt enable flag of peripheral function ILM : CPU register level ISE : EI2OS enable flag of Interrupt control register (ICR) IL : Interrupt level set bit of Interrupt control register (ICR) 68 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90330A Series 3.4.3 Procedure for Using a Hardware Interrupt Use of hardware interrupt requires the system stack area, peripheral functions, and interrupt control registers (ICR) to be set up. ■ Procedure for Using a Hardware Interrupt Figure 3.4-4 shows an example of the procedure for using a hardware interrupt. Figure 3.4-4 Example of Procedure for Using a Hardware Interrupt START (1) Setting System stack area (2) Initialize peripheral function (3) Setting ICR in interrupt controller Interrupt processing program Branch to Stack processing interrupt vector (8) Execution for peripheral interrupt (execute interrupt routine) (9) Clearing interrupt factor (10) Interrupt return instruction (RETI) (7) Set the interrupt enable bit of operation (4) starting setting for peripheral function = enable. (5) Processing by Hardware Setting ILM, I in PS Main program (6) Interrupt request generation Main program (1) The system stack area is set. (2) Initialize the setting of a peripheral function which can generate an interrupt request. (3) Set the interrupt control register (ICR) in the interrupt controller. (4) Make the peripheral function ready to start, and set the interrupt enable bit to "enable". (5) Sets the interrupt level mask register (ILM) and interrupt enable flag (I) to accept interrupts. (6) Generation of an interrupt in the peripheral function generates a hardware interrupt request. (7) The contents of the registers are saved by the interrupt handling hardware, and control branches to the interrupt handling program. (8) The interrupt handling program handles to the peripheral function in response to generation of the interrupt. (9) Clear the interrupt request from the peripheral function. (10)Execute the interrupt return instruction to return control to the program before branching. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 69 CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt 3.4.4 MB90330A Series Multiple Interrupts Multiple hardware interrupts can be implemented. To do so, set different interrupt levels for interrupt level set bits (IL0 to IL2) of the ICR in response to two or more interrupt requests from a peripheral function. However, multiple EI2OS and multiple μDMAC cannot be started. ■ Multiple Interrupts If an interrupt request with a higher interrupt level is generated during execution of the interrupt handling routine, this higher interrupt level request is accepted with the current interrupt handling suspended. After completion of the higher interrupt level, control returns to the handling of the suspended interrupt. The interrupt level can be set to "0" to "7". If it is set to "7", the CPU will accept no interrupt request. If a new interrupt at the same or a lower level is generated during execution of the current interrupt handling, the new one remains pending until the current one is completed, unless the I flag changes the ILM. Activation of the multiple interrupt function during the interrupt is temporarily disabled by setting the I flag in the condition code register (CCR) to "disable" (CCR:I = 0), or setting the interrupt level mask register (ILM) to "disable" (ILM = 000B) in the interrupt handling routine. Note: However, multiple EI2OS and multiple μDMAC cannot be started. If an extended intelligent I/O service (EI2OS) or μDMAC process is in progress, all the other interrupt requests and all the EI2OS and μDMAC requests remain pending. 70 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90330A Series ■ Example of Multiple Interrupts Aa an example of multiple interrupt processing, set the A/D converter interrupt level to 2 and the timer interrupt level to "1", considering a case when timer interrupts are to be given higher priority than A/D converter interrupts. At this time, the handling is executed as shown in Figure 3.4-5 if a time interrupt is generated during the A/D converter interrupt handling. Figure 3.4-5 Example of Multiple Interrupts Main program A/D interrupt processing Timer interrupt processing Interrupt level 2 Interrupt level 1 (ILM=010B) (ILM=001B) Initialize (1) peripheral (3) Timer interrupt generation Timer interrupt A/D interrupt (2) (4) processing generation Suspend Restart Main processing restart (8) (6) A/D interrupt processing (5) Timer interrupt return (7) A/D interrupt return ● A/D Interruption generation At the start of the A/D converter interrupt handling, the ILM is automatically set to the same value as the A/D converter interrupt level (IL2 to IL0 in ICR). If a Level 1 or 0 interrupt request is generated, the interrupt handling makes it a higher priority in execution. ● End of interrupt processing When the interrupt processing has completed and the return instruction (RETI) is executed, the values of the dedicated registers (A, DPR, ADB, DTB, PCB, PC, PS) saved in the stack are returned and the interrupt level mask register (ILM) has the values before the interrupt. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 71 CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt 3.4.5 MB90330A Series Hardware Interrupt Processing Time Before the interrupt handling routine can be executed after a hardware interrupt request is generated, the time to complete of the currently active instruction and the interrupt handling time are required. ■ Hardware Interrupt Processing Time Before the interrupt handling routine can be executed after an interrupt request is generated and the interrupt is accepted, the waiting time for the interrupt request sample and the interrupt handling time (required for preparation for interrupt handling) are required. Figure 3.4-6 shows the interrupt handling time. Figure 3.4-6 Interrupt Processing Time Normal instruction execute Interrupt handling Interrupt processing routine Operation of CPU Interrupt wait time Interrupt request sampling wait time Interrupt handling time (φ machine cycle)* Interrupt request generation * : The last cycle, Sampling interrupt request here : 1 machine cycle is appropriate 1 clock cycle of machine clock (φ). ● Interrupt request sampling wait time The wait time for an interrupt request sample refers to the time from generation of an interrupt request to the completion of the currently active instruction. Whether or not an interrupt request is present is determined by interrupt request sampling in the final cycle of each instruction. Because the CPU cannot recognize the interrupt request for the above reason, the wait time is produced. The wait time for an interrupt request sample reaches the maximum if an interrupt request is generated immediately after the start of the PCPW, PW0,..., RW7 instructions with the longest cycle of execution (45 machine cycle). 72 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt MB90330A Series ● Interrupt handling time (θ machine cycle) The CPU must save the dedicated registers in the system stack, fetch the interrupt vectors, and execute other processes by acceptance of the interrupt request. To do so, it requires the interrupt handling time with the θ machine cycles. The interrupt handling time can be calculated by the expression shown below. • When an interrupt is activated: θ = 24 + 6 × Z machine cycles • When an interrupt is returned: θ = 11 + 6 × Z machine cycles (RETI instructions) The interrupt handling time depends on the address to which the stack pointer points. Table 3.4-3 shows the compensation values (Z) of the interrupt handling time. One machine cycle is equal to one clock cycle of the machine clock (φ). Table 3.4-3 Compensation Value of Interrupt Handling Time (Z) CM44-10129-6E Address which stack pointer indicates Compensation value (Z) For the external 8-bit +4 For the external even address +1 For the external odd address +4 For internal even address 0 For internal odd address +2 FUJITSU MICROELECTRONICS LIMITED 73 CHAPTER 3 INTERRUPT 3.5 Software Interrupt 3.5 MB90330A Series Software Interrupt The software interrupt function transfers control from the currently active program by the CPU to the user-defined interrupt handling program in response to execution of the software interrupt instruction (INT instruction). The hardware interrupt stops during execution of a software interrupt. ■ Start of Software Interrupt ● Start of software interrupt A software interrupt is started by using the INT instruction. The software interrupt request has neither the interrupt request flag nor enable flag, execution of the INT instruction always generates a software interrupt request. ● Hardware interrupt inhibition Because the INT instruction has no interrupt level, the interrupt level mask register (ILM) is not updated. During the execution of an INT instruction, "0" is set in the I flag of the condition code register (CCR) to mask hardware interrupts. To enable hardware interrupts also during software interrupt handling, set the I flag to "1" in the software interrupt handling routine. ● Operation of software interrupt Once the CPU fetches and executes the INT instruction, the software interrupt handling microcode is activated. With this microcode, the registers and their related data in the CPU are automatically saved in the system stack. After hardware interrupts are masked (CCR:I = 0), control branches to the associated interrupt vector. For allocations of interrupt numbers and interrupt vectors, see Section "3.2 Interrupt Cause and Interrupt Vector". ■ Return from Software Interrupt When the return interrupt (RETI instruction) instruction is executed in the interrupt handling program, the 12-byte data saved in the system stack returns to the dedicated registers. Control then returns to the process which was being executed before the interrupt branch. 74 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.5 Software Interrupt MB90330A Series ■ Operation of Software Interrupt Figure 3.5-1 shows the operation sequence from generation of a software interrupt to completion of interrupt handling. Figure 3.5-1 Operation of Software Interrupt Internal bus PS, PC (2) Microcode (1) PS I S IR Queue Fetch RAM PS : Processor status I : Interrupt enable flag S : Stack flag IR : Instruction register (1) Software interrupt instruction is executed. (2) The required processes are performed; for example, the contents of the dedicated registers are saved according to the microcode associated with the software interrupt instruction. The branching process is then executed. (3) The RETI instruction in the user-defined interrupt handling routine terminates the interrupt handling. ■ Precautions on Software Interrupt If the program counter bank register (PCB) is "FFH", the vector area for the CALLV instruction overlaps with the table for the INT#vct8 instruction. When creating the software, pay attention to overlap of the CALLV instruction and INT#vct8 instruction addresses. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 75 CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI2OS) 3.6 MB90330A Series Interrupts by Extended Intelligent I/O Service (EI2OS) The extended intelligent I/O service (EI2OS) executes automatic data transfer between the peripheral function (I/O) and memory. A hardware interrupt is generated at the end of the data transfer. ■ Extended Intelligent I/O Service (EI2OS) The extended intelligent I/O service is a kind of hardware interrupts. EI2OS executes automatic data transfer between the peripheral function (I/O) and memory. EI2OS executes data exchange with the peripheral function (I/O), previously executed by the interrupt handling program, like direct memory access (DMA), at the end of transfer, and sets the end condition before control automatically branches to the interrupt handling routine. The user has to write the program only about the start and end of EI2OS without having to code the data transfer program between them. ● Advantages of extended intelligent I/O service (EI2OS) Compared with data transfer by the interrupt handling routine, EI2OS provides the user with the following advantages: • Because no data transfer program needs to be coded, the program size can shrink. • Because the transfer can be stopped depending the state of the peripheral function (I/O), no unnecessary data needs to be transferred. • Enables the user to select whether the buffer address is incremented or not updated. • Enables the user to select whether the I/O register address is incremented or not updated. ● Interrupt by extended intelligent I/O service (EI2OS) termination After completion of data transfer by EI2OS, this sets the end condition in the S1 and S0 bits of the interrupt control register (ICR) before automatic branch to the interrupt handling routine. The cause for a stop of EI2OS can be determined by checking the EI2OS status (S1 and S0 of ICR) with the interrupt handling program. The interrupt numbers, interrupt vectors, etc. are fixed for individual peripheral functions. For details, see Section "3.2 Interrupt Cause and Interrupt Vector". ● Interrupt control registers (ICR) Located in the interrupt controller. Activates EI2OS, specifies the channel, and displays the at end state of EI2OS. ● Extended intelligent I/O service (EI2OS) descriptor (ISD) Located in the 000100H to 00017FH area in RAM. Contains a set of 8-byte data used to store the transfer mode, I/O address and transfer count, and buffer address. Repeated for 16 channels. Specifies the channel with the interrupt control register (ICR). Note: The CPU program execution stops while the extended intelligent I/O service (EI2OS). 76 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI2OS) MB90330A Series ■ Operation of Extended Intelligent I/O Service (EI2OS) Figure 3.6-1 shows the operation of the EI2OS. Figure 3.6-1 Operation of Extended Intelligent I/O Service (EI2OS) Memory space by IOA I/O register I/O register Peripheral function (I/O) (5) CPU Interrupt request (3) ISD by ICS (2) (3) (1) Interrupt control register (ICR) Interrupt controller by BAP (4) ISD IOA BAP ICS DCT Buffer by DCT : EI2OS descriptor : I/O address pointer : Buffer address pointer : EI2OS channel select bit for Interrupt control register (ICR) : Data counter (1) I/O demands forwarding. (2) The interrupt controller selects the descriptor. (3) Reads the transfer-source or transfer-destination from the descriptor. (4) Forwarding between I/O and the memory is executed. (5) The interruption factor is automatically clear. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 77 CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI2OS) 3.6.1 MB90330A Series Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) Extended intelligent I/O service (EI2OS) descriptor (ISD) is existed to the addresses 000100H to 00017FH in the internal RAM and consists of 8 bytes × 16 channels. ■ Configuration of Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) Configuration of ISD consists of 8 bytes × 16 channels, and each ISD has the configuration shown in Figure 3.6-2. The correspondence between the channel numbers and ISD addresses is as listed in Table 3.6-1. Figure 3.6-2 Configuration of EI2OS Descriptor (ISD) MSB Data counter upper 8bit (DCTH) LSB H Data counter lower 8bit (DCTL) I/O Register address pointer upper 8bit (IOAH) I/O Register address pointer lower 8bit (IOAL) EI2OS status register (ISCS) Buffer address pointer upper 8bit (BAPH) Buffer address pointer middle 8bit (BAPM) ISD start address (000100H + 8 x ICS) 78 Buffer address pointer lower 8bit (BAPL) FUJITSU MICROELECTRONICS LIMITED L CM44-10129-6E CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI2OS) MB90330A Series Table 3.6-1 Correspondence between Channel Numbers and Descriptor Addresses CM44-10129-6E Channel Descriptor address 0 000100H 1 000108H 2 000110H 3 000118H 4 000120H 5 000128H 6 000130H 7 000138H 8 000140H 9 000148H 10 000150H 11 000158H 12 000160H 13 000168H 14 000170H 15 000178H FUJITSU MICROELECTRONICS LIMITED 79 CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI2OS) 3.6.2 MB90330A Series Each Register of Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) The extended intelligent I/O service (EI2OS) descriptor (ISD) consists of the following registers. • Data counter (DCT) • I/O register address pointer (IOA) • EI2OS status register (ISCS) • Buffer address pointer (BAP) Note that resetting each register causes its initial value to be undefined. ■ Data Counter (DCT) Data counter (DCT), a 16-bit length register, indicates the corresponding to the transfer data count. After each of data has been transferred, the counter is decremented by 1 (reduced value). EI2OS ends when this counter reaches "0". Figure 3.6-3 shows the DCT configuration. Figure 3.6-3 Configuration of Data Counter (DCT) DCTH DCTL bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value DCT B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 XXXXXXXXXXXXXXXXB R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W R/WR/WR/WR/W R/W : Readable/Writable X : Undefined ■ I/O Register Address Pointer (IOA) I/O register address pointer (IOA), a 16-bit length register, contains those low address (A15 to A00) of the I/O register which are used for data transfer to or from the buffer. The upper address (A23 to A16) containing all "0" data, can specify any I/O from 000000H to 00FFFFH. Figure 3.6-4 shows the IOA configuration. Figure 3.6-4 Configuration of I/O Register Address Pointer (IOA) IOAH IOAL bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value IOA A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 XXXXXXXXXXXXXXXXB R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W R/W : Readable/Writable X : Undefined 80 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI2OS) MB90330A Series ■ Extended Intelligent I/O Service (EI2OS) Status Register (ISCS) The extended intelligent I/O service status register (ISCS) updates or fixes the buffer address and I/O register address pointers by the 8-bit length register. It also indicates the transfer data format (byte or word) and the direction of transfer. Figure 3.6-5 shows the configuration of the ISCS. Figure 3.6-5 Configuration of EI2OS Status Register (ISCS) bit7 bit6 bit5 Reserved Reserved Reserved bit4 bit3 bit2 bit1 bit0 IF BW BF DIR SE Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W SE EI2OS end control bit 0 It is completed by request from peripheral function. 1 It is not completed by request from peripheral function. Data transfer direction specification bit DIR 0 I/O register address pointer Buffer address pointer 1 Buffer address pointer I/O register address pointer BF BAP update/fix selection bit 0 Buffer address pointer is updated after transfer data. *1 1 Buffer address pointer is not updated after transfer data. BW Transfer data length specification bit 0 Byte 1 Word IF IOA update/fix selection bit 0 I/O register address pointer is updated after transfer data. *2 1 I/O register address pointer is not updated after transfer data. Reserved Reserved bit. Always set this bit to "0". R/W : Readable/Writable X : Undefined *1 : Buffer address pointer is changed only lower 16-bit and enabled only increment. *2 : Address pointer is enabled only increment. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 81 CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI2OS) MB90330A Series ■ Buffer address Pointer (BAP) The buffer address pointer (BAP), a 24-bit register, contains the address used for the next attempt of transfer by EI2OS. The BAP is provided independently for the EI2OS channels to enable the EI2OS channels to transfer data between any address of 16 Mbytes and I/O. If the BF bit (BAP update/fix selection bit of EI2OS status register) of the EI2OS status register (ISCS) is set to "updated", only the low order 16bit (BAPM, BAPL) will change in the BAP. The higher 8-bit (BAPH) will be unchanged in this case. Figure 3.6-6 shows the BAP configuration. Figure 3.6-6 Configuration of Buffer address Pointer (BAP) bit23 BAP bit8 bit7 bit16 bit15 bit0 BAPH BAPM BAPL (R/W) (R/W) (R/W) Initial value XXXXXXXXXXXXXXXXXXXXXXXXB R/W : Readable/Writable X : Undefined Note: In the I/O address pointer (IOA), the 000000H to 00FFFFH area is available for specification. In the buffer address pointer (BAP), the 000000H to FFFFFFH area is available for specification. The maximum transfer count which may be specified in the data counter (DCT) is 65536 (64 Kbytes). 82 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI2OS) MB90330A Series 3.6.3 Operation of Extended Intelligent I/O Service (EI2OS) If the peripheral function has generated an interrupt request and activation of EI2OS has been set in the associated interrupt control register (ICR), the CPU will execute data transfer using EI2OS. Once data transfer has been executed the specified number of times, the hardware interrupt handling is executed automatically. ■ Operation of Extended Intelligent I/O Service (EI2OS) Figure 3.6-7 shows the EI2OS operation flow chart by the microcode of the internal CPU. Figure 3.6-7 Flow Chart of Operation of Extended Intelligent I/O Service (EI2OS) Generation of interrupt request from peripheral function NO ISE=1 YES Interrupt sequence ISD/ISCS read End request from peripheral function YES YES SE=1 NO NO YES DIR=1 NO Data indicated by IOA (Data transfer) Memo indicated by BAP Data indicated by BAP (Data transfer) Memo indicated by IOA YES IF=0 NO BF=0 DCT=00 NO IOA update Update value by BW BAP update YES NO DCT decrement Update value by BW (-1) YES EI2OS end processing Set "00" to S1,S0 Clearing peripheral function interrupt request CPU operation return ISD : EI2OS descriptor ISCS : EI2OS status register (ISCS) IF : IOA update/fix selection bit of EI2OS status register (ISCS) BW : Transfer data length specification bit of EI2OS status register (ISCS) BF : BAP update/fix selection bit of EI2OS status register (ISCS) DIR : Transfer data direction specification bit of EI2OS status register (ISCS) SE : EI2OS end control bit of EI2OS status register (ISCS) CM44-10129-6E Set "01" to S1,S0 Set "11" to S1,S0 Clearing ISE to "0" Interrupt sequence DCT : Data counter IOA : I/O register address pointer BAP : Buffer address pointer ISE : EI2OS enable bit of Interrupt control register (ICR) S1,S0 : EI2OS status bit of Interrupt control register (ICR) FUJITSU MICROELECTRONICS LIMITED 83 CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI2OS) 3.6.4 MB90330A Series Procedure for use of Extended Intelligent I/O Service (EI2OS) To use extended intelligent I/O service (EI2OS), the system stack area, EI2OS descriptor, peripheral function, interrupt control register (ICR), and other requirements must be set up. ■ Procedure for Use of Extended Intelligent I/O Service (EI2OS) Figure 3.6-8 shows the EI2OS software and the process by hardware. Figure 3.6-8 Procedure for Use of Extended Intelligent I/O Service (EI2OS) Processing by Software Processing by Hardware START Initialization Setting System stack area Setting EI2OS descriptor Initializing Peripheral function Setting Interrupt control register (ICR) Setting Operation start set interrupt enable bit of internal resource Setting ILM, I in PS S1,S0=00 User program execution (Interrupt request)and (ISE=1) Data transfer Decide whether to end counting or to NO branch to an interrupt by termination request from resource YES (Branch to Interrupt vector) Resetting expanded intelligent I/O service (Changing channel etc.) S1,S0=01 or S1,S0=11 Data processing during buffer RETI ISE : EI2OS enable bit of Interrupt control register (ICR) S1,S0 : EI2OS status of Interrupt control register (ICR) 84 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI2OS) MB90330A Series 3.6.5 Extended Intelligent I/O Service (EI2OS) Processing Time The time required for extended intelligent I/O service (EI2OS) processing depends on the following factors: • • • • • Setting of EI2OS status register (ISCS) Address (area) indicating I/O register address pointer (IOA) Address (area) indicating buffer address pointer (BAP) Width of external data bus when external is accessed Data length of transfer data Because a hardware interrupt is activated at the end of data transfer by EI2OS, the interrupt handling time will be added. ■ Extended Intelligent I/O Service (EI2OS) Processing Time (Time for One Transfer) ● For continued data transfer For continued data transfer, the EI2OS processing time varies with the setting in the EI2OS status register (ISCS), as listed in Table 3.6-2. Table 3.6-2 Extended Intelligent I/O Service Execution Time Setting of the EI2OS termination control bit (SE) Setting of the IOA updating/fixing select bit (IF) BAP address update/fixation Setting of selection bits (BF) Terminated by an end request from periphery Termination request from the surrounding is disregarded. Fixed Update Fixed Update Fixed 32 34 33 35 Update 34 36 35 37 Unit: One machine cycle is equal to one clock cycle of the machine clock (φ). CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 85 CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI2OS) MB90330A Series Further, correction may be required, depending on the condition for executing EI2OS, as shown in Table 3.6-3. Table 3.6-3 Compensation Value for Data Transfer at EI2OS Processing Time Internal Access External access I/O register address pointer B/Even Odd B/Even 8/Odd B/Even 0 +2 +1 +4 Odd +2 +4 +3 +6 B/Even +1 +3 +2 +5 8/Odd +4 +6 +5 +8 Internal Access Buffer address pointer External access B: 8: Even: Odd: Byte data transfer External bus width 8-bit/word transfer Word transfer at even address Word transfer at odd address ● At completion of counting by data counter (DCT) (for final data transfer) Because a hardware interrupt is activated at the end of data transfer by EI2OS, the interrupt handling time is added. The EI2OS processing time at the end of counting is calculated by the following expression. EI2OS processing time when count ends = EI2OS processing time in data transfer + (21 + 6 × Z) machine cycles ↑ Interrupt handling time The interrupt handling time depends on the address to which the stack pointer points. Table 3.6-4 shows the compensation values (Z) of the interrupt handling time. Table 3.6-4 Compensation Value of Interrupt Handling Time (Z) 86 Address which stack pointer indicates Compensation Value (Z) At the external 8 bits +4 At the external even number address +1 At the external odd number address +4 At the internal even number address 0 At the internal odd number address +2 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E MB90330A Series CHAPTER 3 INTERRUPT 3.6 Interrupts by Extended Intelligent I/O Service (EI2OS) ● At the end caused by an end request from the peripheral function (I/O) If data transfer by EI2OS is aborted due to an end request from the peripheral function (I/O) (ICR S1, ICR S0 = 11), the hardware interrupt is activated without performing data transfer. The EI2OS processing time is calculated using the expression below. Z in the expression represents the interrupt handling time compensation value (see Table 3.6-4). EI2OS processing time for aborted = 36 + 6 × Z machine cycles Reference: One machine cycle is equal to one clock cycle of the machine clock (φ). CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 87 CHAPTER 3 INTERRUPT 3.7 Exception Processing Interrupt 3.7 MB90330A Series Exception Processing Interrupt F2MC-16LX executes exception handling by executing undefined instructions. Exception handling, basically the same as interrupt, is executed when an exception item is detected during a period between instructions, the normal process is suspended for this purpose. In general, exception handling takes place as a result of unpredicted operation; it is recommended that it be used only for debugging or for activating the recovery software in the event of an emergency. ■ Exception Processing Interrupt ● Operation of exception processing F2MC-16LX regards as an undefined instruction any code not defined in the instruction map. When executing an undefined instruction, F2MC-16LX performs a process equivalent to software interrupt instruction "INT#10". Before control branches to the interrupt routine, the exception handling performs the following processes: 1) Saving the registers of A, DPR, ADB, DTB, PCB, PC, and PS in the system stack. 2) Clearing the I flag of the condition code register (CCR) to "0" to mask the hardware interrupt. 3) Setting the S flag of the condition code register (CCR) to "1" to enable the system stack. The program counter (PC) value saved in the system stack indicates the address storing the undefined instruction. For any instruction code of 2 or more bytes, the PC value indicates the address which stores the code by which the instruction has been identified as an undefined one. The PC value is useful to determine the type of the exception cause in the exception handling routine. ● Return from exception processing After returning from the exception handling according to the RETI instruction, control starts the exception handling again because the PC points to an undefined instruction. Some measurement such as performing a software reset should be taken. 88 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90330A Series 3.8 Interruption by μDMAC μDMAC is a simplified DMA with the same function as EI2OS. 3.8.1 μDMAC Function 3.8.2 Register of μDMAC 3.8.2.1 DMA Descriptor Channel Specification Register (DCSR) 3.8.2.2 DMA Status Register (DSRH/DSRL) 3.8.2.3 DMA Stop Status Register (DSSR) 3.8.2.4 DMA Permission Register (DERH/DERL) 3.8.3 DMA Descriptor Window Register (DDWR) 3.8.3.1 DMA Data Counter (DDCTH/DDCTL) 3.8.3.2 DMA I/O Register Address Pointer (DIOAH/DIOAL) 3.8.3.3 DMA Control Register (DMACS) 3.8.3.4 DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL) 3.8.4 Explanation of Operation of μDMAC CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 89 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC 3.8.1 MB90330A Series μDMAC Function μDMAC is simple DMA with the function equal with EI2OS. ■ μDMAC Function μDMAC has the following functions. • Performs automatic data transfer between the peripheral resource (I/O) and memory. • The program execution of CPU stops in the DMA startup. • The DMA transfer channel is 16 channels (The smaller the channel number, the higher the priority of DMA transfer). • Can select either "incremented" or "not incremented" for the source or destination address. • DMA transfer may be activated, depending on the interrupt cause by a peripheral resource (I/O). • DMA transfer can be controlled with (a) DMA permission register (DERH/DERL), (b) DMA stop status register (DSSR), (c) DMA status register (DSRH/DSRL), (d) DMA descriptor channel specification register (DCSR), and (e) descriptor (DMACS). • A STOP request is available for stopping DMA transfer from the resource. • After completion of DMA transfer, the flag is set in the appropriate bit of the DMA status register (DSRH/DSRL), resulting in output of an interrupt to the interrupt controller. 90 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90330A Series 3.8.2 Register of μDMAC μDMAC has four registers: DCSR, DSR, DSSR, and DER. The DMA descriptor used to set up DMA transfer is described in Section "3.8.3 DMA Descriptor Window Register (DDWR)". ■ μDMAC Register List Figure 3.8-1 μDMA Register List DMA descriptor channel specification register (DCSR) 14 13 12 11 10 bit 15 00009BH STP Reserved Reserved Reserved R/W R/W R/W R/W DMA status register (DSRH/DSRL) 14 13 12 bit 15 9 DCSR3 DCSR2 DCSR1 DCSR0 R/W R/W R/W 11 10 9 00009DH DTE15 DTE14 DTE13 DTE12 DTE11 DTE10 DTE9 bit 00009CH 8 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 DTE7 DTE6 DTE5 DTE4 DTE3 DTE2 DTE1 R/W R/W R/W R/W R/W R/W R/W 3 2 DCSR R/W Initial value 00000000B 8 DTE8 DSRH R/W Initial value 00000000B 0 DTE0 DSRL R/W Initial value 00000000B DMA stop status register (DSSR) bit 0000A4H bit 7 6 5 4 1 0 STP15 STP14 STP13 STP12 STP11 STP10 STP9 STP8 R/W 7 0000A4H STP7 R/W 6 R/W 5 R/W 4 STP6 STP5 STP4 DSSR R/W 3 R/W 2 R/W 1 R/W Initial value 00000000B 0 STP3 STP2 STP1 STP0 DSSR R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B When the STP bit of DCSR is "0", DSSR uses STP15 to STP8. When the STP bit of DCSR is "1", DSSR uses STP7 to STP0. DMA permission register (DERH/DERL) bit 0000ADH bit 0000ACH 15 14 EN15 EN14 R/W 7 R/W 6 EN7 R/W 13 12 11 10 9 8 EN12 EN11 EN10 EN9 EN8 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W Initial value 00000000B 0 EN6 EN5 EN4 EN3 EN2 EN1 EN0 R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B EN13 DERH DERL R/W : Readable/Writable CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 91 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90330A Series DMA Descriptor Channel Specification Register (DCSR) 3.8.2.1 DMA descriptor channel specification register (DCSR) switches the descriptor of each channel. The descriptor is set after the channel is specified by this register. ■ DMA Descriptor Channel Specification Register (DCSR) Figure 3.8-2 DMA Descriptor Channel Specification Register bit 00009BH 15 STP R/W 14 13 12 Reserved Reserved Reserved R/W R/W R/W 11 10 9 8 DCSR3 DCSR2 DCSR1 DCSR0 R/W R/W R/W R/W DCSR Initial value 00000000B R/W : Readable/Writable [bit 11 to bit 8] DCSRx: Specifies the DMA descriptor channel. Table 3.8-1 Relation between DCSR and Selector Channel 92 DCSR3 to DCSR0 Selection channel Resource interrupt request 0000B 0 USB function 1 (End Point 0-IN) 0001B 1 USB function 1 (End Point 0-OUT) 0010B 2 USB function 2 (End Point 1)* 0011B 3 USB function 2 (End Point 2)* 0100B 4 USB function 2 (End Point 3) 0101B 5 USB function 2 (End Point 4) 0110B 6 USB function 2 (End Point 5) 0111B 7 Input capture 0,1 1000B 8 Input capture 2,3 1001B 9 I/O extended serial 1010B 10 UART2/3, Reception 1011B 11 UART2/3, Transmission 1100B 12 UART0/1, Reception 1101B 13 UART0/1, Transmission 1110B 14 PWC, reload timer 0 1111B 15 A/D converter, conversion end, and free run timer FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90330A Series One descriptor channel of the 16 channels is selected by setting the DCSR. For details, see Section "3.8.3 DMA Descriptor Window Register (DDWR)". *: This function can use even when USB HOST is operated. [bit 15] STP:STP control bit STP bit Function 0 [Initial value] STP8 to STP15 is selected as DSSR. 1 STP0 to STP7 is selected as DSSR. [bit 14 to bit 12] Reserved: (reserved bits) These bits are a reserved bit. These bits are always "0" at the beginning of reading. Please write "0". Note: Do not use any read modify write (RMW) instruction to access the DCSR register. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 93 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC 3.8.2.2 MB90330A Series DMA Status Register (DSRH/DSRL) DMA status register (DSRH/DSRL) indicates that the DMA transfer ended. When "1" is set to this register, the interrupt is generated at the same time. ■ Bit Configuration of DMA Status Register (DSRH/DSRL) Figure 3.8-3 Bit Configuration of DMA Status Register (DSRH/DSRL) bit 15 14 13 12 11 10 9 00009DH DTE15 DTE14 DTE13 DTE12 DTE11 DTE10 DTE9 bit 00009CH 8 DTE8 R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 DTE7 DTE6 DTE5 DTE4 DTE3 DTE2 DTE1 DTE0 R/W R/W R/W R/W R/W R/W R/W R/W DSRH Initial value 00000000B DSRL Initial value 00000000B R/W : Readable/Writable [bit 15 to bit 0] DTEx: DMA Status DTEx bit 0 [Initial value] 1 Function The DMA transfer has not ended. Please write "0" when DTEx is "0". Indicates that DMA transfer was completed and an interrupt request is being executing. The DMA transfer due to the STOP request except last transfer does not set 1 to this bit. When DTEx is "1", writing "0" clears it to "0" and writing "1" holds the previous data. Note: To write data to the DSRH/DSRL, use a read-modify-write (RMW) instruction. 94 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90330A Series 3.8.2.3 DMA Stop Status Register (DSSR) DMA stop status register (DSSR) indicates that the DMA transfer stopped due to the STOP request. The meaning of the bit in this register is different depending on the STP bit of the DMA descriptor channel specification register (DCSR). ■ DMA Stop Status Register (DSSR) Figure 3.8-4 Bit Configuration of DMA Stop Status Register (DSSR) DCSR:STP bit = 0 7 6 bit 5 4 3 2 1 0000A4H STP15 STP14 STP13 STP12 STP11 STP10 STP9 R/W R/W DCSR:STP bit = 1 6 bit 7 0000A4H STP7 R/W R/W R/W 5 4 R/W 0 STP8 R/W R/W 3 2 1 0 DSSR R/W Initial value 00000000B STP6 STP5 STP4 STP3 STP2 STP1 STP0 R/W R/W R/W R/W R/W R/W Initial value 00000000B R/W DSSR R/W : Readable/Writable [bit15 to bit 0] STPx: DMA stop status STPx bit Function During DMA transfer, no STOP request is accepted from the resource. Please write "0" at STPx=0. 0 [Initial value] During DMA transfer, indicates that DMA transfer stopped in response to a STOP request from the resource. However, "1" is not set to STPx bit even though the STOP request is accepted at last transfer. If the SE bit of DMA control register is "1" and a STOP request is received by the associated channel, the corresponding bit of the DMA permission register is cleared to "0". When STPx = 1, writing "0" clears it to "0" and writing "1" holds the previous data. 1 The following two channels correspond to the STOP demand. Channel Corresponding STPx bit Resource ch.10 STP10 UART2/3, Reception ch.12 STP12 UART0/1, Reception Bits other than STP10 and STP12 do not have the meaning. Notes: • • DSSR is controlled by most significant bit (STP) of DCSR. If STP is "0", STP15 to STP8 will be selected as being used for the DSSR. If it is "1", STP7 toSTP0 will be used for the DSSR. Because the initial value of STP is "0", STP15 to STP8 is initially selected. To write data to the DSSR, use a read modify write (RMW) instruction. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 95 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90330A Series DMA Permission Register (DERH/DERL) 3.8.2.4 DMA permission register (DERH/DERL) enables the DMA transfer. When "1" is set to this register, the interrupt request, which is the DMA transfer request, generates to the corresponding channel, and starts the DMA transfer. ■ DMA Permission Register (DERH/DERL) Figure 3.8-5 Bit Configuration of DMA Permission Register (DERH/DERL) bit 15 14 0000ADH EN15 EN14 bit R/W 7 R/W 6 0000ACH EN7 R/W 13 12 11 10 9 EN12 EN11 EN10 EN9 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 EN6 EN5 EN4 EN3 EN2 EN1 EN0 R/W R/W R/W R/W R/W R/W R/W EN13 8 EN8 DERH Initial value 00000000B DERL Initial value 00000000B R/W : Readable/Writable [bit15 to bit0] ENx: DMA permission ENx bit 0 [Initial value] 1 Function This bit does not execute the DMA transfer. The interrupt request from the resource is handled as a DMA activation request, and the interrupt request is output to the interrupt controller at the end of DMA transfer. When the number of DMA transfer bytes reaches 0, or a STOP request from the resource stops DMA transfer, this is cleared to "0". Notes: 96 • To write data to the DERH/DERL, use a read modify write (RMW) instruction. • Before changing the mode to the standby mode (sleep mode, stop mode, watch mode, and timebase timer mode) or the CPU intermittent operation mode (main clock intermittent operation mode, PLL clock intermittent mode, and sub clock intermittent mode), the DMA permission register (DERH/DERL) must be set to "0". FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90330A Series 3.8.3 DMA Descriptor Window Register (DDWR) The DMA descriptor, consisting of 8 bytes × 16 channels, is used to set up DMA transfer. One of the 16 channels is specified, and mapped to the DMA descriptor window register (DDWR) for being accessible. The address of DDWR is 007920H to 007927H. ■ Configuration of DMA Descriptor Window Register (DDWR) The DMA descriptor consists of 8 bytes × 16 channels. The configuration of each channel is shown in Figure 3.8-6. The descriptor of the channel selected by the DMA descriptor channel specification register (DCSR) or interrupt request channel number is mapped to the DMA descriptor window register (DDWR). See Table 3.8-1 for the relationship between the DMA descriptor channel specification register (DCSR) and the selected channel. Figure 3.8-6 Configuration of DMA Descriptor Window Register (DDWR) Address 007927H DMA Data counter upper 8-bit (DDCTH) 007926H DMA Data counter lower 8-bit (DDCTL) 007925H DMA I/O register address pointer upper 8-bit (DIOAH) 007924H DMA I/O register address pointer lower 8-bit (DIOAL) 007923H DMA Control register (DMACS) 007922H DMA Buffer address pointer upper 8-bit (DBAPH) 007921H DMA Buffer address pointer middle 8-bit (DBAPM) 007920H DMA Buffer address pointer lower 8-bit (DBAPL) ■ Each Register of DMA Descriptor Each register configuring the DMA descriptor is described in the following pages. The initial value of each register is made undefined when a reset is generated. Thus, make sure that the initialization has finished before ENx is set to "1". Note: If the DCSR is used to switch the channel descriptor, access to DDWR is inhibited during the two subsequent machine cycles. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 97 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC 3.8.3.1 MB90330A Series DMA Data Counter (DDCTH/DDCTL) DMA data counter (DDCTH/DDCTL) sets the data transfer. When DDCTH/DDCTL is 0, the DMA transfer ends. ■ DMA Data Counter (DDCTH/DDCTL) DMA data counter (DDCTH/DDCTL), a 16-bit length register, indicates the counter associated with transferred number. After each data has been transferred, the counter is always decremented by 1 regardless of transferred data (word or byte). The DMA transfer ends when this counter reaches 0. Figure 3.8-7 shows the DDCT configuration. If the DDCT is set to "0", the maximum data transfer count (65536) is set. Figure 3.8-7 Bit Configuration of DMA Data Counter (DDCTH/DDCTL) 007927H/007926H DDCTH DDCTL bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value DDCTH/ B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 XXXXXXXXXXXXXXXXB DDCTL R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: Readable/Writable X: Undefined ■ About the Set Value of DMA Data Counter (DDCTH/DDCTL) Table 3.8-2 shows the relationship between the number of transferred bytes and the DDCTH/DDCTL. Table 3.8-2 Set Value of DMA Data Counter (DDCTH/DDCTL) DMACS DDCT BW bit BYTEL bit 0 - N 1 0 N/2 1 1 (N+1)/2 N: Number of transfer bytes 98 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90330A Series 3.8.3.2 DMA I/O Register Address Pointer (DIOAH/DIOAL) DMA I/O register address pointer (DIOAH/DIOAL) sets the I/O address pointer. The upper address (A23 to A16) is fixed at "00H". ■ DMA I/O Register Address Pointer (DIOAH/DIOAL) The DMA I/O register address pointer (DIOAH/DIOAL), a 16-bit length register, indicates the 16 low order bits (A15 to A00) of the DMA I/O register address. The upper-level address (A23 to A16), containing all "0" data, can specify any I/O address space from 000000H to 00FFFFH. If the IF bit (DIOA update/fix selection bit) of the DMA control register (DMACS) is set to "updated", the DIOA will be incremented by 1 during byte transfer or by 2 during word transfer. If this bit is set to "not updated", the DIOA will be fixed. Figure 3.8-8 shows the DIOA configuration. Figure 3.8-8 Bit Configuration of DMA I/O address Register Pointer (DIOAH/DIOAL) 007925H/007924H DIOAH DIOAL bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value DIOAH/ A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 XXXXXXXXXXXXXXXXB DIOAL R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: Readable/Writable X : Undefined CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 99 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC 3.8.3.3 MB90330A Series DMA Control Register (DMACS) DMA control register (DMACS) controls the DMA transfer. The following can be controlled by the DMACS. • Direction control (IOA → BAP and BAP→ IOA) • Transfer bit length (Byte and word) • Address update (provided or not provided) • Transfer interval • Odd-numbered byte control at word transfer ■ DMA Control Register (DMACS) The DMA control register (DMACS), an 8 bit length specifies update/fix, the transfer data format (byte or word), the direction of transfer, and byte transfer, and issues a wait instruction of DMA buffer address pointer and DMA I/O register address pointer. Figure 3.8-9 shows the DMACS configuration. Figure 3.8-9 Bit Configuration of DMA Control Register (DMACS) Address bit7 bit6 bit5 007923H RDY2 RDY1 BYTEL R/W R/W R/W bit4 bit3 bit2 bit1 bit0 Initial value IF BW BF DIR SE XXXXXXXXB R/W R/W R/W R/W R/W SE DMA transfer end control bit 0 It is not completed by request from peripheral function. 1 It is completed by request from peripheral function. DIR Data transfer direction specification bit 0 DMA I/O register address pointer 1 DMA Buffer address pointer BF DMA Buffer address pointer DMA I/O register address pointer BAP update/fix selection bit 0 After data transfer, the buffer address pointer is updated. 1 After data transfer, the buffer address pointer is not updated. Transfer data length specification bit BW 0 Byte 1 Word IF IOA update/fix selection bit 0 After data transfer, the I/O register address pointer is updated. 1 After data transfer, the I/O register address pointer is not updated. BYTEL Byte transfer specification bit (only enabled for word transfer) 0 Even number of Bytes 1 Odd number of Bytes RDY2 RDY1 0 R/W: Readable/Writable X : Undefined 100 0 Wait instruction bits (see Figure 3.8-10) No wait is inserted between transfers. 0 1 A 1-cycle wait is inserted between transfers. 1 0 A 2-cycle wait is inserted between transfers. 1 1 A 3-cycle wait is inserted between transfers. FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90330A Series Figure 3.8-10 Wait Specification Bit Explanation source destination wait source destination Length of wait part in transfer such as above figure is defined by RDY2 and RDY1. Note: If writing transmission data to UART by using μDMAC, not setting RDY2 and RDY1 bit of DMACS register in (0, 0). CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 101 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90330A Series DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL) 3.8.3.4 DMA buffer address pointer (DBAPH/DBAPM/DBAPL) sets the buffer address pointer. The DBAPH/DBAPM/DBAPL can be set A23 to A00. ■ DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL) The DMA buffer address pointer (DBAPH/DBAPM/DBAPL), a 24-bit register, contains the address used for DMA transfer. DBAP are provided independently for the DMA channels to enable the DMA channels to transfer data between any address of 16 Mbytes and I/O. If the BF bit (DBAP update/fix selection bit) of the DMA control register (DMACS) is set to "updated", the 16 lower order bits (DBAPM, DBAPL) of the DBAP will be incremented by 1 during byte transfer or by 2 during word transfer. The 8 high order bits (DBAPH) will be unchanged in this case Figure 3.8-11 shows the DBAP configuration. Figure 3.8-11 Bit Configuration of DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL) 007922H/007921H/007920H DBAPH/ DBAPM/ DBAPL bit23 bit16 bit15 bit8 bit7 bit0 DBAPH DBAPM DBAPL R/W R/W R/W Initial value XXXXXXXXXXXXXXXXXXXXXXXXB R/W : Readable/Writable X : Undefined Notes: 102 • In the DMA I/O register address pointer (DIOAH/DIOAL), the 000000H to 00FFFFH area is available for specification. • In the DMA buffer address pointer (DBAPH/DBAPM/DBAPL), the 000000H to FFFFFFH area is available for specification. • μDMAC internal register DCSR, DSRH, DSRL, DSSR, DERH, or DERL, or an address of DMA descriptor window register (DDWR) may not be specified in the DIOA or DBAP. FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90330A Series 3.8.4 Explanation of Operation of μDMAC This section describes the μDMAC operation. ■ Operation of μDMAC Figure 3.8-12 shows the DMA operation. Data transfer using μDMAC performs the following steps in order: 1. The peripheral resource (I/O) makes a request for DMA transfer. 2. If the DMA permission register (DERH/DERL) is "1", μDMAC reads transfer-related data, such as the source and destination addresses for the specified channel and the transfer count, from the descriptor. 3. The DMA data transfer is begun between I/O and the memory. 4. After executing forwarding one byte or 1word. (a) If transfer is not yet completed, that is, the DMA data counter (DDCT) does not contain 0 yet, A request to clear the DMA transfer request is issued to the peripheral resource. (b) When forwarding ends (DMA data counter DDCT=0) After completion of DMA transfer, the transfer end flag is set. Note: When writing to the internal register DSRH, DSRL, DSSR, DERH, and DERL, be sure to use the read modify write (RMW) instruction. Figure 3.8-12 Operation of μDMAC Memory space DIOA Peripheral function I/O register I/O register RAM for descriptor (I/O) (4) (a) (3) (1) DMA controller (2) DMA descriptor (4) (b) Buffer DDCT Interrupt DBAP CPU DIOA : DMA I/O address pointer DBAP : DMA buffer address pointer CM44-10129-6E (2) controller DER : DMA enable register DDCT : DMA data counter FUJITSU MICROELECTRONICS LIMITED 103 CHAPTER 3 INTERRUPT 3.8 Interruption by μDMAC MB90330A Series ■ Use Procedure of μDMAC Figure 3.8-13 shows the procedure for using μDMAC. Figure 3.8-13 Use Procedure of μDMAC Hardware processing Software processing (Interrupt generation) START NO ENx=1 of appropriate ch Setting System stack area YES Setting Interrupt control register YES Initialization Initializing peripheral function STOP request and SE=1 NO DMA transfer (DBAP) (DIOA) NO BF = 0 NO IF = 0 YES YES NO BW = 1 BW = 1 YES Execute User program NO BYTEL = 0 YES NO YES NO BYTEL = 0 NO YES DCT = 0 DCT = 0 YES YES BAP = BAP+2 NO BAP = BAP+1 STPx = 1 IOA = IOA+2 DCT = 0 IOA = IOA+1 NO YES DTEx = 1 (Jump to Interrupt routine) Interrupt processing ENx = 0 NO Generating other interrupt YES Generating interrupt YES NO End of processing ENx : DMA enable register appropriate bit DTEx : DMA status register appropriate bit STPx : DMA stop status register appropriate bit : Output interrupt request to interrupt controller 104 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.9 Exceptions MB90330A Series 3.9 Exceptions The F2MC-16LX performs exception processing when the following event occurs. ■ Execution of an Undefined Instruction Exception processing is fundamentally the same as interrupt processing. When an exception is detected between instructions, exception processing is performed separately from ordinary processing. In general, exception processing is performed as a result of an unexpected operation. Fujitsu recommends using exception processing only for debugging or for activating emergency recovery software. ■ Exception due to Execution of an Undefined Instruction The F2MC-16LX handles all codes that are not defined in the instruction map as undefined instructions. When an undefined instruction is executed, processing equivalent to the INT 10 software interrupt instruction is performed. Specifically, the AL, AH, DPR, DTB, ADB, PCB, PC, and PS values are saved into the system stack, and processing branches to the routine indicated by the interrupt number 10 vector. In the undefined instruction is stored. Processing can be restored by the RETI instruction, but is of no use, however, because the same exception occurs again. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 105 CHAPTER 3 INTERRUPT 3.10 Stack Operation of Interrupt Processing 3.10 MB90330A Series Stack Operation of Interrupt Processing Once an interrupt is accepted, the contents of the dedicated registers are automatically saved in the system stack before control branches to the interrupt handling. Return from the stack at the end of the interrupt handling also takes place automatically. ■ Stack Operation at the Start of Interrupt Processing Once the interrupt is accepted, the CPU automatically saves the contents of the current dedicated registers and their related data in the system stack in the order below: 1. Accumulator (A) 2. Direct page register (DPR) 3. Additional data bank register (ADB) 4. Data bank register (DTB) 5. Program counter bank register (PCB) 6. Program counter (PC) 7. Processor status (PS) Figure 3.10-1 shows the stack operation at the start of interrupt handling. Figure 3.10-1 Stack Operation at Start of Interrupt Processing Address Previously interrupt SSB Memory Immediately interrupt Address SSB 08FFH 00H SSP 08FEH A 0000H 08FFH 00H SP 08FEH XX H H AH XX H AL XX H 08F2H A 0000H 08FEH 08H AH AL FEH 00H 00H 01H XX H DPR 01H ADB 00H DTB 00H PCB FFH XX H DPR 01H ADB 00H DTB 00H PCB FFH 00H 00H XX H XX H XX H PC 803FH PS 20E0H XX H FFH L 80H PC 803FH PS 20E0H 3FH 20H XX H 08F2H XX H SP 08FEH SSP XX H 08FEH Memory Byte 08F2H E0H AH AL DPR ADB DTB PCB PC PS SP after updated Byte ■ Stack Operation when Interrupt Processing Returns When the interrupt return instruction (RETI) is executed at the end of interrupt process, the values of PS, PC, PCB, DTB, ADB, DPR, and A return from the stack in the reverse order for the start of interrupt handling. The dedicated registers are restored to the initial state preceding the start of interrupt. 106 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.10 Stack Operation of Interrupt Processing MB90330A Series ■ Stack Area ● Securing stack area The stack area is used to save or return the program counter (PC) used to execute the subroutine call (CALL) or vector call (CALLV) instruction as well as execute the interrupt handling. This area is also used, by the PUSHW or POPW instruction, to save or return the contents of temporary registers and their related data. The stack area is located in RAM together with the data area. Figure 3.10-2 shows the stack area. Figure 3.10-2 Stack Area Vector table (Reset, Interrupt vector call instruction) FFFFFFH FFFC00H ROM area FC0000H*1 0040FFH*2 Internal RAM area Stack area 000380H 000180H Generalpurpose register bank area 000100H 0000FBH 000000H Internal I/O area *1: Built-in ROM capacity is difference depending on products. *2: Built-in RAM capacity is difference depending on products. Notes: • As a general rule, even addresses should be set in the stack pointers (SSP and USP). • The system stack area, user stack area, and data area should not overlap. ● System stack area and user stack area The system stack area is used for interrupt processing. Even if the user stack area is being used, generation of an interrupt causes forcible switching to the system stack. For this reason, the system stack area must have been set up properly even in a system where the user stack area is primarily used. In particular, only the system stack area should be used unless it is necessary to divide the stack space. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 107 CHAPTER 3 INTERRUPT 3.11 Program Example of Interrupt Processing 3.11 MB90330A Series Program Example of Interrupt Processing An example of interrupt processing program is shown below. ■ Program Example of Interrupt Processing ● Processing specification An example interruption program that uses external interruption 0 (INT0). ● Coding example DDR6 EQU 000016H ; Port 6 direction register ENIR EQU 00003CH ; Interruption/DTP permission register. EIRR EQU 00003DH ; Interruption/DTP factor register ELVR EQU 00003EH ; Request level setting register ICR03 EQU 0000B3H ; Interrupt control register 03 STACK SSEG RW 100 STACK_T RW STACK ENDS ; Stack 1 ;----------Main Program-----------------------------------------------------------CODE CSEG ; START: MOV RP, #0 ; Header bank used for general-purpose registers MOV ILM, #07H ; Sets ILM in PS to level 7 MOV A, #!STACK_T ; Sets system stack MOV SSB, A MOVW A, #STACK_T ; Setting of stack pointer, in this case, MOVW SP, A ; S flag = 1, so set to SSP MOV DDR6,#00000000B ; Sets the P60/INT0 pin for input OR CCR, #40H ; Sets I flag of CCR in PS to enable interrupts. MOV I:ICR03, #00H ; It is assumed interrupt levels 0(Max) MOV I:ELVR, #00000001B ; Make INT0 "H" level request MOV I:EIRR, #00H ; Clears interrupt cause for INT0. MOV I:ENIR, #01H ; INT0 input permitted : LOOP: NOP ; Dummy loop NOP NOP 108 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.11 Program Example of Interrupt Processing MB90330A Series NOP BRA LOOP ; Unconditional jump ;----------Interrupt Program-----------------------------------------------------------ED_INT1: MOV I:EIRR, #00H ; New acceptance of INT0 prohibited NOP NOP NOP NOP NOP NOP RETI CODE ; Returns from interrupt. ENDS ;----------Vector Settings-----------------------------------------------------------------VECT VECT CSEG ABS=0FFH ORG 0FFB4H DSL ED_INT1 ORG 0FFDCH DSL START DB 00H ; The vector is set in interruption #18(12H) ; Reset vector setting ; Single-chip mode setting ENDS END START ● Processing specification for program example of extended intelligent I/O service (EI2OS) 1. The extended intelligent I/O service (EI2OS) is started upon detection of the "H" level signal which inputs to the INT0 pin. 2. When "H" level is input to INT0 pin, EI2OS is started, which transfers data at port 0 to memory address "3000H". 3. The number of transfer data bytes is 100. After the 100 bytes have been transferred, an interrupt is generated because of completion of EI2OS data transfer. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 109 CHAPTER 3 INTERRUPT 3.11 Program Example of Interrupt Processing MB90330A Series ● Coding example DDR6 EQU 000016H ; Port 6 direction register ENIR EQU 00003CH ; Interruption/DTP permission register EIRR EQU 00003DH ; Interruption/DTP factor register ELVR EQU 00003EH ; A register to specify the required level ICR03 EQU 0000B3H ; Interrupt control registers 03 BAPL EQU 000100H ; Buffer address pointer lower BAPM EQU 000101H ; Buffer address pointer middle BAPH EQU 000102H ; Buffer address pointer upper ISCS EQU 000103H ; EI2OS Status IOAL EQU 000104H ; Lower I/O address pointer IOAH EQU 000105H ; Higher I/O address pointer DCTL EQU 000106H ; Data counter lower DCTH EQU 000107H ; Data counter upper ER0 EQU EIRR:0 ; Defines external interrupt request flag bit. STACK SSEG RW 100 STACK_T RW STACK ENDS ; Stack 1 ;----------Main Program-----------------------------------------------------------CODE CSEG START: AND CCR,#0BFH ; Clears the I flag of CCR in PS to disable interrupts. MOV RP,#00 ; Sets register bank pointer. MOV A,#!STACK_T ; Sets system stack MOV SSB,A MOVW A,#STACK_T ; Setting of stack pointer, in this case, MOVW SP,A ; S flag = 1, so set to SSP MOV I:DDR6,#00000000B ; Sets the P60/INT0 pin for input. MOV BAPL,#00H ; Sets buffer address (003000H) MOV BAPM,#30H MOV BAPH,#00H MOV ISCS,#00010001B ; No I/O address update, byte transfer Buffer address updated ; The peripheral function terminates I/O to buffer transfer. Yes 110 MOV IOAL,#00H MOV IOAH,#00H ; Sets transfer source address (port 0: 000000H) FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.11 Program Example of Interrupt Processing MB90330A Series MOV DCTL,#64H ; Sets transfer byte count (100 bytes) MOV DCTH,#00H MOV I:ICR00,#00001000B ; EI2OS channel 0, EI2OS enable, interrupt level 0 (highest) MOV I:ELVR,#00000001B ; Make INT0 "H" level request MOV I:EIRR,#00H ; Clears interrupt cause for INT0. MOV I:ENIR,#01H ; Enables INT0 interrupt. MOV ILM,#07H ; Sets ILM in PS to level 7 OR CCR,#40H ; Sets I flag of CCR in PS to enable interrupts. LOOP ; Infinite loop : LOOP: BRA ;----------Interrupt Program-----------------------------------------------------------WARI CLRB ER0 ; Interrupt/DTP request flag clear : user processing ; confirmation of the cause of the EI2OS completion : ; Processes data in buffer, resetting EI2OS etc. RETI CODE ENDS ;----------Vector Settings------------------------------------------------------------------VECT VECT CSEG ABS=0FFH ORG 0FFB4H DSL WARI ORG 0FFDCH DSL START DB 00H ; Reset vector setting ; Single-chip mode setting ENDS END CM44-10129-6E ; The vector is set in interruption #18(12H). START FUJITSU MICROELECTRONICS LIMITED 111 CHAPTER 3 INTERRUPT 3.12 Delayed Interrupt Generation Module 3.12 MB90330A Series Delayed Interrupt Generation Module The delayed interrupt generation module is used to generate a task switching interrupt. Use of this module enables F2MC-16LX CPU to generate or cancel an interrupt request. ■ Block Diagram of Delayed Interrupt Generation Module Figure 3.12-1 shows the block diagram of the delayed interrupt generation module. Figure 3.12-1 Block Diagram of Delayed Interrupt Generation Module F2MC-16LX bus delayed interrupt request generation/ clear decoder Factor latch ■ List of Register of Delay Interruption Generation Module The register configuration of the delayed interrupt generation module {delayed interrupt cause generation/ clear register (delayed interrupt request register (DIRR))} is shown in the following figure. Figure 3.12-2 Delayed Interrupt Cause Generation/clear Register (DIRR) bit 15 14 13 12 11 10 9 8 R0 00009FH Initial value -------0B R/W R/W : Readable/Writable Delay interruption factor generation/release register (DIRR) controls the delay factor generation and release. Writing "1" to this register generates a delayed interrupt request. Writing "0" to it resets the request. A reset causes the state cause to remain cleared. Either "0" or "1" may be written to the reserved bit area. However, it is recommended that the set or clear bit instruction for accessing this register be used, taking the future extension into account. 112 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 3 INTERRUPT 3.12 Delayed Interrupt Generation Module MB90330A Series 3.12.1 Operation of Delayed Interrupt Generation Module When the CPU writes "1" to the appropriate bit of the DIRR by software, the request latch in the delay interrupt generation module is set, resulting in generation of the interrupt request to the interrupt controller. ■ Operation of Delayed Interrupt Generation Module When the CPU writes "1" to the appropriate bit of the DIRR by software, the request latch in the delay interrupt generation module is set, resulting in generation of the interrupt request to the interrupt controller. If all the other interrupt requests have a lower priority than that of this one, or no other requests have been generated, the interrupt controller generates the interrupt to F2MC-16LX CPU. When F2MC-16LX CPU compares the ILM bit in the internal CCR register with interrupt request, if the request level is higher than the ILM bit, a hardware interrupt processing microprogram is activated as soon as the current execution instruction is completed. As a result, the interrupt routine is executed for this interrupt. The interrupt cause is cleared by writing 0 to the appropriate bit of the DIRR in the interrupt handling routine. This also causes task switching. Figure 3.12-3 shows the above operation flow. Figure 3.12-3 Operation of Delayed Interrupt Generation Module Delayed interrupt generation module Interrupt controller F2MC-16LX bus Other request IL ICRYY DIRR CMP ICRXX CMP ILM INTA ■ Notes on Use of Delay Interruption Generation Module (Delay Interruption Request Latch) This latch is set by writing "1" to the appropriate bit of the DIRR, and cleared by writing "0" to this bit. Note that for this reason, the interrupt handling may be reactivated immediately when control returns from the interrupt cause handling, unless the software has been designed to clear the cause in the interrupt handling routine. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 113 CHAPTER 3 INTERRUPT 3.12 Delayed Interrupt Generation Module 114 FUJITSU MICROELECTRONICS LIMITED MB90330A Series CM44-10129-6E CHAPTER 4 RESET This chapter explains reset of the MB90330A series. 4.1 Outline of Reset 4.2 Reset Factors and Oscillation Stabilization Wait Times 4.3 External Reset Pin 4.4 Reset Operation 4.5 Reset Factor Bit 4.6 State of Each Pin at Reset CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 115 CHAPTER 4 RESET 4.1 Outline of Reset 4.1 MB90330A Series Outline of Reset When the reset cause is generated, the CPU suspends the currently executed process immediately before entering the wait state for release of the reset. After the reset is cleared, processing starts from the address indicated in the reset vector. There are the following four kinds of factors of resets. • Generation power on reset • Watchdog timer overflow • Generation of external reset request from RST pin • Generation of software reset request ■ Reset Factor Table 4.1-1 shows the causes of reset. Table 4.1-1 Reset Factor Reset Generation factor Machine clock Watchdog timers Oscillation stability waiting Power on At power on Main clock (MCLK) Stops Yes Watchdog timer Watchdog timer overflow Main clock (MCLK) Stops None External pin Input "L" level to RST pin Main clock (MCLK) Stops None Software A "0" is written to the RST bit of low-power consumption mode control register (LPMCR) Main clock (MCLK) Stops None Main clock: Oscillation clock frequency divided by 2 ● Power on reset Power on reset is reset generated at power on. For an evaluation or flash product, the oscillation stabilization wait time is 218/HCLK (approx. 43.70 ms at an oscillation clock of 6 MHz). For a MASK product, this wait time is 217/HCLK (approx. 21.85 ms at an oscillation clock of 6 MHz). Reset operation starts after elapsing the oscillation stabilization wait time. ● Watchdog reset Watchdog reset generates a reset in response to an overflow of the watchdog timer after start of the watchdog timer. This overflow occurs when a "0" is not written in the watchdog control bit (WTE) of the watchdog timer control register (WDTC) within the predetermined time. The oscillation stabilization wait time can be selected using the clock select register (CKSCR). 116 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 4 RESET 4.1 Outline of Reset MB90330A Series ● External reset An external reset is generated by inputting the "L" level signal to external reset pin (RST). The input time of the "L" level signal to the (RST) pin must be continued for 16 machine cycles (16/φ) or more. The external reset, that is, the RST pin input reset does not produce the oscillation stabilization wait time. Reference: Only when a reset request via the RST pin is generated, a reset cause generated in write operation (An example of such write operation is the MOV instruction which is issued during execution of a transfer instruction.) causes a wait state for release of the reset after completion of the instruction. Thus, the write process terminates normally even if a reset signal is input during write operation. However, if a string instruction such as MOVS is used, transfer of all the data will not be guaranteed. This is because the instruction accepts a reset before the transfer data for the specified counter value is completed. A reset is accepted also if extension of the bus cycle via the RDY pin continues for 16 machine cycles or more during access to the external bus. ● Software reset Software reset causes an internal reset by writing "0" to the internal reset signal generation bit (RST) of the low-power consumption mode control register (LPMCR). Software reset does not cause the oscillation stabilization wait time. Reference: Clock definition HCLK: Oscillation clock, which is provided via the high speed oscillation pin. MCLK: Main clock (HCLK frequency divided by 4) SCLK: Sub clock (a clock which is frequency divided by 4 on the clock provided via the low speed oscillation pin) φ: Machine clock (CPU operation clock) 1/φ: machine cycle (CPU operating clock cycle) Refer to the Section "5.1 Outline of Clock" for details of the machine clocks. Note: A reset generated in stop or sub clock mode produces an 217/HCLK oscillation stabilization wait time (approximately 21.85 ms at the oscillation clock is 6 MHz). Refer to the Section "5.4 Clock Mode" for details of the clock mode. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 117 CHAPTER 4 RESET 4.2 Reset Factors and Oscillation Stabilization Wait Times 4.2 MB90330A Series Reset Factors and Oscillation Stabilization Wait Times There are four kinds of reset factors of MB90330A series. The oscillation stabilization wait time varies with the reset cause. ■ Reset Factors and Oscillation Stabilization Wait Times Table 4.2-1 shows the relationship between the reset causes and the oscillation stabilization wait time. Table 4.2-1 Reset Factors and Oscillation Stabilization Wait Times Reset factor Oscillation stabilization wait time Each value in parentheses ( ) represents the period for the oscillation clock at 6 MHz. Power on reset Evaluation products/flash products: 218/HCLK (about 43.70 ms). MASK product: 217/HCLK (about 21.85 ms). Watchdog timer None: However, WS1 and WS0 bit are initialized by "11B". External reset from RST pin None: However, WS1 and WS0 bit are initialized by "11B". Software reset None: However, WS1 and WS0 bit are initialized by "11B". HCLK: Oscillation clock WS1, WS0: Bits used to select the oscillation stabilization wait time of the clock selection register (CKSCR). Figure 4.2-1 shows the oscillation stabilization wait times for the evaluation/flash and MASK products during power on reset time. 118 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 4 RESET 4.2 Reset Factors and Oscillation Stabilization Wait Times MB90330A Series Figure 4.2-1 Oscillation Stabilization Wait Times for the Evaluation/flash and MASK Products during Power on Reset Time Evaluation/Flash Products VCC 217/HCLK 217/HCLK CLK CPU operation Down-conversion Oscillation Stabilizing Stabilizing Wait Time Wait Time MASK Products VCC 217/HCLK CLK CPU operation Oscillation Stabilizing Wait Time HCLK : Oscillation clock Note: For ceramic or quartz oscillators, typically the oscillation stabilization wait time of several to some tens of milliseconds is required until the oscillation is stabilized at the natural oscillation. after it begins. For this reason, set the wait time value meeting the oscillator used. For details, see Section "5.5 Oscillation Stabilization Wait Time". ■ Oscillation Stabilization Waiting Reset State The reset operation in response to a reset which occurs during power on reset or in stop or sub clock mode begins after passing the oscillation stabilization wait time produced by the time-base timer expires. The reset operation is performed after the external reset is released. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 119 CHAPTER 4 RESET 4.3 External Reset Pin 4.3 MB90330A Series External Reset Pin The external reset pin (RST pin), dedicated to reset input pin, generates an internal reset in response to input of the "L" level signal. MB90330A series are reset in synch with the CPU operating clock, except for external pin in asynchronous (generated through ports and so on), which change to the reset state. ■ Block Diagram of External Reset Pin Figure 4.3-1 shows the block diagram of the generation of the internal reset. Figure 4.3-1 Block Diagram of Internal Reset Generation CPU operation clock (PLL frequency multiplication circuit, divided-by-two of HCLK) RST CPU P-ch Synchronous circuit Pin N-ch Input buffer HCLK : Oscillation clock Peripheral function I/O port etc. Note: To protect the memory from destruction by a reset during write operation, the RST pin input is accepted with a cycle which does not cause the memory to be destroyed. Also, the clock is required to initialize the internal circuits. In particular, when using an external clock, the clock must be input during input of the reset. 120 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 4 RESET 4.4 Reset Operation MB90330A Series 4.4 Reset Operation Once the reset is released, the object from which to read the mode data and reset vector is selected by setting the mode pin, before the mode fetch is performed. This fetch determines the CPU operation mode and the execution activation address succeeding the reset operation. At power on or when recovering from stop mode via a reset, the mode fetch is performed after the oscillation stabilization delay time elapses. ■ Overview of Reset Operation Figure 4.4-1 shows the reset operation flow. Figure 4.4-1 Reset Operation Flow Power on reset Stop mode Sub clock mode During reset External reset Software reset Watchdog timer reset Oscillation stabilizing wait reset state Mode fetch (Reset operation) Fetch Mode data Pin state and function change of external bus mode relation Fetch Reset vector Normal operation (RUN state) Capture the instruction code from the address specified by reset vector and execute the instruction ■ Mode Pin The mode pins (MD2 to MD0) specify the way to fetch the reset vector and mode data. This fetch is performed according to the reset sequence. See Section "7.2 Mode Pins (MD2 to MD0)" for details of the mode pins. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 121 CHAPTER 4 RESET 4.4 Reset Operation MB90330A Series ■ Mode Fetch Once the reset is released, the CPU transfers the reset vector and mode data into the appropriate register in the CPU core. The reset vector and mode data are assigned to the four bytes of FFFFDCH to FFFFDFH. When the reset is released, the CPU immediately outputs these addresses to the bus before fetching the reset vector and mode data. The CPU starts the mode fetch process at the address pointed to by the reset vector. Figure 4.4-2 shows how the reset vector and mode data are transferred. Figure 4.4-2 Reset Vector and Mode Data Transfers F2MC-16LX CPU core Memory space FFFFDFH Mode data FFFFDEH Reset vector bit 23 to 16 FFFFDDH Reset vector bit 15 to 8 FFFFDCH Reset vector bit 7 to 0 Mode register Micro ROM Reset sequence PCB PC Reference: The object from which to read the reset vector and mode data (either internal ROM or external memory) can be specified using the mode pins. It is recommended that the internal vector mode be specified using the mode pins in single chip mode or internal ROM external bus mode. This is because specifying the external vector mode with the mode pins causes an attempt to read the reset vector and mode data from the external memory, instead of the internal memory. ● Mode data (address: FFFFDFH) The contents of the mode register can be modified only by reset operation. The mode register settings will take effect after reset operation. Refer to the Section "7.3 Mode Data" for details of the mode data. ● Reset vector (address FFFFDCH to FFFFDEH) Write the execution start address after the completion of the reset operation. Execution begins from the address of this content. 122 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 4 RESET 4.5 Reset Factor Bit MB90330A Series 4.5 Reset Factor Bit A reset factor can be identified by reading the watchdog timer control register (WDTC). ■ Reset Factor Bit There are the flip-flop registers associated with respective reset causes, as shown in Figure 4.5-1. The contents of the flip-flops are obtained by reading the watchdog timer control register (WDTC). If the reset cause needs to be identified after the reset has been released, the values read from the WDTC register should be processed by software before control branches to the program. Figure 4.5-1 Block Diagram of Reset Factor Bit RST Pin Power on Power on generation detection circuit RST=L External reset request detection circuit Watchdog timer control register (WDTC) S R S F/F Q R Without routine clear Watchdog timer reset generation detection circuit S F/F R S F/F Q Q RST bit set LPMCR, RST bit write detection circuit R F/F Delayed circuit Q Watchdog timer control register (WDTC) read F2MC-16LX internal bus S: set R: reset Q: output F/F: flip-flop CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 123 CHAPTER 4 RESET 4.5 Reset Factor Bit MB90330A Series ■ Correspondence of Reset Factor Bit and Reset Factor Figure 4.5-2 shows the configuration of the reset cause bits of the watchdog timer control register (WDTC). Contents of reset cause bits and associated reset causes are shown in the Table 4.5-1. For details, see the Section "10.2 Watchdog Timer Control Register (WDTC)". Figure 4.5-2 Configuration of Reset Factor Bits (Watchdog Timer Control Register) Watchdog Timer Control Register (WDTC) bit 7 6 5 15 - 8 0000A8H (TBTC) PONR X R Reserved X - 4 3 2 1 0 WRST ERST SRST WTE WT1 WT0 X R X R X R 1 W 1 W 1 W Initial value R/W R: Read only W: Write only X: Undefined Table 4.5-1 Correspondence of Reset Factor Bit and Reset Factor Reset Factor PONR WRST ERST SRST Generating power-on reset 1 X X X Generating watchdog timer overflow * 1 * * Generating External reset request from RST pin * * 1 * Generation of software reset request * * * 1 *: Previous state held X: Undefined ■ Notes on Reset Factor Bit ● At two or more reset factors If more than one reset cause is generated, the corresponding each reset cause bits of the WDTC register will be set to "1". For example, if an external reset request via the RST pin and an overflow are generated simultaneously, ERST and WRST of reset cause bits are set to "1". ● At power on reset When a power on reset is generated, the PONR of reset cause bit is set to "1" and all the other reset cause bits are made undefined. For this reason, the software must be designed so that all the reset cause bits other than PONR will be ignored if PONR is "1". ● Clearing of reset factor bit Each of the reset cause bits is cleared only when the values are read from the WDTC register. Once a reset cause is generated, the bit corresponding to it is not cleared even when the reset is generated (a setting of "1" is retained). Note: If power is turned on when a power on reset has not been generated, the WDTC register values may be unprotected. 124 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 4 RESET 4.6 State of Each Pin at Reset MB90330A Series 4.6 State of Each Pin at Reset This section explains the state of each pin at reset. ■ Pin Status during Reset The state of each pin during reset is determined by the settings of the mode pins (MD2 to MD0). ● When internal vector mode has been set: (MD2 to MD0=011B) All I/O, or resource, pins are placed at high impedance. The internal ROM is defined as the object form which to read the mode data. See the Section "6.7 State of the Pin during Standby Mode, Hold, and Reset" for details of the state of each pin during reset." ■ State of Pins after Mode Data Read The pin state succeeding read of the mode data is determined by the mode data (M1, M0). ● When single chip is selected a mode (M1,M0=00B) All I/O, or resource, pins are placed at high impedance. The internal ROM is defined as the object form which to read the mode data. Note: For any pin to which place at high impedance when a reset cause is generated, give consideration so that the equipment connected to the pin will not malfunction. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 125 CHAPTER 4 RESET 4.6 State of Each Pin at Reset 126 MB90330A Series FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 5 CLOCK This chapter explains the clock of the MB90330A series. 5.1 Outline of Clock 5.2 Block Diagram of Clock Generation Section 5.3 Clock Select Register (CKSCR) 5.4 Clock Mode 5.5 Oscillation Stabilization Wait Time 5.6 Connection of Oscillator and External Clock CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 127 CHAPTER 5 CLOCK 5.1 Outline of Clock 5.1 MB90330A Series Outline of Clock The clock generation section controls operation of the internal clock which is the operation clock for the CPU and peripheral functions. In this document, the clocks are called as follows according to clock type. • Machine clock: Internal clock. • Main clock: Oscillation clock frequency divided by 2. • Oscillation clock: Clock provided via a high-speed oscillation pin. • PLL clock: Clock generated by internal PLL oscillation. • Sub clock: A clock frequency divided by 4 on the clock provided via the low speed oscillation pin. ■ Overview of Clock The clock generation section, containing an oscillator circuit, can generate the oscillation and sub clocks by being connected with an external oscillator. Clock generated externally can be input and used as the oscillation clock. The generator, also containing a PLL clock frequency multiplication circuit, can generate three frequency multiplication clocks of the oscillation clock. The clock generation section controls the oscillation stabilization wait time, controls the PLL clock multiplication and controls the internal clock operation by clock switching with the clock selector. ● Oscillation clock (HCLK) This clock is generated by connecting an oscillator or inputting an external clock to the high-speed oscillation pins. ● Sub clock (SCLK) It is a clock which operates the watch timer. Moreover, it is available as a low-speed machine clock. A clock frequency divided by 4 on the clock which is generated by connecting an oscillator or inputting an external clock to the low-speed oscillation pin. ● Main clock (MCLK) It is an oscillation clock frequency divided by 2 and an input clock to the time-base timer and clock selector. ● PLL clock (PCLK) An oscillation clock which is obtained by frequency multiplication through the internal PLL clock frequency multiplication circuit (PLL oscillator circuit). Three kinds of clocks can be selected. ● Machine clock (φ) Operation clock for CPU and peripheral functions. One cycle of this clock is used as machine cycle (1/φ). A desired clock can be selected from among the main clock, that is, an oscillation clock frequency divided by 2, the sub clock, and the three frequency multiplication clocks. 128 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 5 CLOCK 5.1 Outline of Clock MB90330A Series Notes: • As for the oscillation clock, 1 MHz to 7 MHz can oscillate. The maximum operating frequency is 24 MHz for the CPU and peripheral functions. When multiplier exceeding the maximum operating frequency is specified, the device does not operate correctly. If the source oscillation at a frequency of 6 MHz, only 4-time frequency multiplication can be specified. • To use the USB HOST or USB function, the PLL clock mode must have been set. ■ Clock Supply Map Machine clocks generated by the clock generation section are supplied as operating clocks of the CPU and peripheral function. For this reason, operation of the peripheral functions is influenced by switching clock mode between the main and PLL clock or switching the PLL clock frequency multiplication rate. The frequency divided output from the time-base timer is provided to some peripheral functions, thereby enabling each periphery to select its operating clock. Figure 5.1-1 contains the map showing how the clocks are provided. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 129 CHAPTER 5 CLOCK 5.1 Outline of Clock MB90330A Series Figure 5.1-1 Clock Supply Map 4 Peripheral function Watchdog timer 4 Clock generation unit 16 - bit PPG timer 0/1/2/3/4/5 Pin PPG0 to PPG5 16 - bit PWC timer Pin PWC Pin SCK Pin SIN Pin SOT Pin SCK0 to SCK3 Pin SIN0 to SIN3 Pin SOT0 to SOT3 Pin TIN0 to TIN2 Pin TOT0 to TOT2 External interrupt Pin INT0 to INT7 16 - bit output compare 0/1/2/3 Pin OUT0 to OUT3 16 - bit free - run timer Pin FRCK 16 - bit input capture 0/1/2/3 Pin IN0 to IN3 Pin AN0 to 15 Pin ADTG Pin DVP Pin DVM Pin HCON Pin UTEST Pin HVP Pin HVM Pin SCL0 to SCL2 Pin SDA0 to SDA2 Watch timer X0A Pin X1A Pin Time-base timer Sub clock generation circuit X0 Pin X1 Pin 1 4 division System clock generation HCLK circuit 2 8 - bit expanded serial I/O 4 PLL frequency multiplication circuit PCLK SCLK UART0/1/2/3 Clock selector 2 division MCLK 16 - bit reload timer 0/1/2 CPU HCLK : Oscillation clock MCLK : Main clock SCLK : Sub clock PCLK : PLL clock : Machine clock 8/10 - bit A/D converter USB function USB HOST I2C interface 3 130 Oscillation stabilization wait time FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 5 CLOCK 5.2 Block Diagram of Clock Generation Section MB90330A Series 5.2 Block Diagram of Clock Generation Section The clock generation section consists of the following six blocks: • System clock generation circuit • Sub clock generation circuit • PLL multiplying circuit • Clock selector • Clock select register (CKSCR) • Oscillation stabilization wait time selector ■ Block Diagram of Clock Generation Section Figure 5.2-1 shows the block diagram of the clock generation section. Figure 5.2-1 contains the standby control and time-base timer circuits. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 131 CHAPTER 5 CLOCK 5.2 Block Diagram of Clock Generation Section MB90330A Series Figure 5.2-1 Block Diagram of Clock Generation Section Low power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 Reserved Pin high impedance control circuit Pin Hi-Z control Internal reset Internal reset generation circuit Intermittent cycle selection RST Pin CPU intermittent operation sector CPU clock control circuit Reset (Cancellation) Watch, Stop, Sleep signal Standby control circuit 2 CPU clock Watch, Stop signal Interrupt (Cancellation) Oscillation stable wait cancellation Clock generation unit Peripheral clock control circuit Sub clock oscillation stabilization wait cancellation Main clock oscillation stabilization wait cancellation Operation clock selector Machine clock Oscillation stable wait time selector 2 2 PLL frequency multiplication circuit SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock selection register (CKSCR) 2 -division X0 Pin X1 Pin Oscillation clock (HCLK) Oscillation clock generation circuit 4 512 -division -division Main clock Time-base timer 2 -division 2 -division 4 -division 1024 -division 2 -division 2 -division 4 -division to Watchdog timer Sub clock (SCLK) X0A Pin 2 -division 8 -division 2 -division 2 -division Watch timer X1A Pin System clock generation circuit ● System clock generation circuit Generates an oscillation clock (HCLK) using the oscillator connected to the high-speed oscillation pin. It is also possible to input an external clock. ● Sub clock generator circuit Generates the sub clock (SCLK) using the oscillator connected to the low-speed oscillation pin. It is also possible to input an external clock. 132 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 5 CLOCK 5.2 Block Diagram of Clock Generation Section MB90330A Series ● PLL multiplying circuit The oscillation clock is multiplied by PLL oscillation and supplied to the CPU clock selector. ● Clock selector From the main and sub clocks, and the three PLL clocks, this selects the clock to be supplied to the CPU and periphery clock control circuits. ● Clock select register (CKSCR) Switches between the oscillation and PLL clocks, selects the oscillation stabilization wait time, and selects the PLL clock multiplier. ● Oscillation stabilization wait time selector A circuit which selects the oscillation stabilization wait time for the oscillation clock succeeding release of the stop mode or a watchdog reset. Four time-base timer outputs are selected. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 133 CHAPTER 5 CLOCK 5.3 Clock Select Register (CKSCR) 5.3 MB90330A Series Clock Select Register (CKSCR) The clock select register (CKSCR) switches the clock mode between the main, sub, and PLL clocks, and selects the oscillation stabilization wait time and the PLL clock frequency multiplier. ■ Configuration of Clock Select Register (CKSCR) Figure 5.3-1 shows the clock selection register (CKSCR) configuration. Table 5.3-1 summarizes the functions of the clock selection register bits. Figure 5.3-1 Configuration of Clock Select Register (CKSCR) Address bit15 bit14 bit13 bit12 bit11 bit10 bit 9 0000A1H SCM MCM WS1 R R WS0 SCS MCS CS1 bit 8 bit 7 CS0 bit 0 Initial value (LPMCR) 11111100B R/W R/W R/W R/W R/W R/W CS1 CS0 Multiplication factor selection bit Each value in parentheses ( ) represents the period at 6MHz. 0 0 1 0 1 0 1×HCLK ( 6MHz) 1 1 Disable to setting Machine clock selection bit MCS 0 1 PLL clock selection Main clock selection Sub clock selection bit SCS 0 1 2×HCLK (12MHz) 4×HCLK (24MHz) Sub clock selection Main clock selection WS1 WS0 Oscillation stabilization wait time selection bit Each value in parentheses ( ) represents the period at 6MHz. 0 0 1 0 1 0 210/HCLK ( Approx. 170.7 μs ) 1 1 217/HCLK ( Approx. 21.84 ms )* 213/HCLK ( Approx. 1.36 ms ) 215/HCLK ( Approx. 5.46 ms ) *:216/HCLK (approx. 10.92 ms) at pwer-on reset Machine clock display bit MCM 0 1 SCM R/W R : Readable/Writable : Read only 0 1 During operating at PLL clock During operating at Main clock Sub clock display bit Sub clock selection Main clock selection Initial value 134 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 5 CLOCK 5.3 Clock Select Register (CKSCR) MB90330A Series Note: The machine clock selection bit (MCS) is initialized by reset to main clock selection. Table 5.3-1 Functions of Clock Select Register (CKSCR) Bits (1 / 2) Bit name Functions bit 15 SCM: Sub clock display bit • Bit indicating the main clock or sub clock, whichever selected as the machine clock. • A "0" in this bit indicates that the sub clock has been selected. A "1" in the bit indicates that the main or PLL clock has been selected. • If SCS = 1 and SCM = 0, now is the main clock oscillation stabilization wait time. bit 14 MCM: PLL clock display bit • Bit indicating the main or PLL clock, whichever selected as the machine clock. • A "0" in this bit indicates that the PLL clock has been selected. A "1" in the bit indicates that the main or sub clock has been selected. • If the PLL clock selection bit (MCS) = 0 and MCM = 1, now is the PLL clock oscillation stabilization wait time. WS1, WS0: Oscillation stabilization wait time selection bits • These bits are used to select an oscillation stabilization wait time required for the oscillation clock when the stop mode is canceled, when transition occurs from sub clock mode to main clock mode, or when transition occurs from sub clock mode to PLL clock. • Initialized to "11B" by every reset cause. Note: The oscillation stabilization wait time must be set to a suitable value for the oscillator to use. See Section "4.2 Reset Factors and Oscillation Stabilization Wait Times". Please set the setting of "00B" only at the main clock mode. Reference: The oscillation stabilization wait time for PLL clock is fixed to 214/HCLK. SCS: Sub clock selection bit • Bit for specifying main or sub clock as the machine clock. • A "0" in this bit selects the sub clock. A "1" in the bit selects the main clock. • If "1" is written to this bit when it is "0", the main clock oscillation stabilization wait time is produced, thereby clearing the time-base timer automatically. • When the sub clock is selected, it is used as the operating clock. (If the low-speed oscillation is 32 kHz, the machine clock is 8 kHz.) • When both SCS and MCS are "0", SCS has priority and sub clock is selected. • Initialized to "1" by every reset cause. MCS: PLL clock selection bit • Bit for selecting main or PLL clock as the machine clock. • A "0" in this bit selects the PLL clock. A "1" in the bit selects the main clock. • If "0" is written to this bit when it is "1", the PLL clock oscillation stabilization wait time is produced, thereby clearing the time-base timer automatically. Also, the interrupt request flag bit (TBOF) of the time-base timer control register (TBTC) is cleared. • The PLL clock oscillation stabilization wait time is fixed to 214/HCLK. (If the oscillation clock is 6 MHz, the oscillation stabilization wait time will be approximately 2.73 ms.) • If the main clock is selected, the operating clock frequency will be the oscillation clock frequency-divided by 2. (If the oscillation clock is 6 MHz, the operating clock will be 3 MHz.) • Initialized to "1" by every reset cause. Note: To write "0" if when MCS bit is "1", make sure that the time-base timer interrupt have been masked using the TBTC register interrupt request enable bit (TBIE) or interrupt level mask register (ILM). bit 13, bit 12 bit 11 bit 10 CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 135 CHAPTER 5 CLOCK 5.3 Clock Select Register (CKSCR) MB90330A Series Table 5.3-1 Functions of Clock Select Register (CKSCR) Bits (2 / 2) Bit name bit 9, bit 8 CS1, CS0: Multiplier selection bit Functions • Bit for selecting the multiply factor for PLL clock. • The multiplier can be selected from among three options. • Initialized to "00B" by every reset cause. Note: When the MCS or MCM is "0", writing to these bits is not allowed. Rewrite the CS1 and CS0 bits after setting the MCS bit to "1" once. "11B" is a set interdiction. HCLK: Oscillation clock 136 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 5 CLOCK 5.4 Clock Mode MB90330A Series 5.4 Clock Mode The clock modes are the main clock mode, PLL clock mode and sub clock mode. ■ Main Clock Mode, PLL Clock Mode, Sub Clock Mode ● Main clock mode The main clock mode stops the PLL clock by using an oscillation clock frequency divided by 2 as the operating clock of the CPU and peripheral resources. ● PLL clock mode The PLL clock mode uses the PLL clock as operation clock for the CPU and peripheral functions. The PLL clock frequency multiplier factor can be selected using the clock selection register (CKSCR). Note: To use the USB HOST or USB function, the PLL clock mode must have been set. ● Sub clock mode The sub clock mode stops the main and PLL clocks by using the sub clock as the operating clock of the CPU and peripheral resources. ■ Transition of Clock Mode Writing the PLL clock selection bit (MCS) or sub clock selection bit (SCS) of the CKSCR changes the clock mode to main, PLL, or sub. ● Transition from main clock mode to PLL clock mode If the CKSCR of MCS bit is rewritten from "1" to "0" while in the main clock mode, the mode will change from main to PLL after the PLL clock oscillation stabilization wait time (214/HCLK). ● Transition from PLL clock mode to main clock mode If the CKSCR of MCS bit is rewritten from "0" to "1" while in the PLL clock mode, the mode will change from PLL to main when the PLL and main clock edges will match (after 1 to 8 PLL clocks). ● Transition from main clock mode to sub clock mode If the CKSCR of SCS bit is rewritten from "1" to "0" while in the main clock mode, the mode will change from main to sub. ● Transition from sub clock mode to main clock mode If the CKSCR of SCS bit is rewritten from "0" to "1" while in the sub clock mode, the mode will change from sub to main after the main clock oscillation stabilization wait time. The oscillation stabilization wait time can be selected using the oscillation stabilization wait time selection bits (WS1, WS0) of the CKSCR. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 137 CHAPTER 5 CLOCK 5.4 Clock Mode MB90330A Series ● Transition from PLL clock mode to sub clock mode If the sub clock selection bit (SCS) of the clock selection register (CKSCR) is rewritten from "1" to "0" while in the PLL clock mode, the mode changes from PLL clock to sub clock. ● Transition from sub clock mode to PLL clock mode If the SCS bit of the CKSCR is rewritten from "0" to "1" while in the sub clock mode, the mode changes from sub clock to PLL clock after the main clock oscillation stabilization wait time. The oscillation stabilization wait time can be selected using the oscillation stabilization wait time selection bits (WS1, WS0) of the CKSCR. Note: Even if the PLL clock selection (MCS) or SCS bit of the CKSCR is rewritten, the machine clock is not switched immediately. If a resource which depends on the machine clock needs to be operated, refer the PLL clock indicator bit (MCM) and sub clock indicator bit (SCM) of the CKSCR to check that the machine clock has been switched, before beginning the operation. If both the SCS and MCS bits are "0", the higher priority is given to SCS and the sub clock mode is entered. If the clock mode is switched, the mode must not be switched to another clock mode or the lowpower consumption mode until completion of the switching. Completion of the switching can be checked by referring the MCM and SCM bits of the CKSCR. ■ Selection of PLL Clock Multiplication Rate One of the three PLL clock frequency multiplier from 1 to 4 times can be selected by writing "00B" to "10B" to the CS1 and CS0 bits of the CKSCR. "11B" is a set interdiction. ■ Machine Clock The PLL clock, main clock, and sub clock output from the PLL multiplying circuit are used as machine clocks. These machine are clocks supplied to the CPU or peripheral function. One of the main, PLL, and sub clock modes can be selected by writing the CKSCR of MCS and SCS bit. Figure 5.4-1 shows the transition chart of the machine clock selection. 138 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 5 CLOCK 5.4 Clock Mode MB90330A Series Figure 5.4-1 State Transition Diagram of Machine Clock Selection (7) Main MCS=1 MCM=1 SCS=1 (1) SCM=1 CS1, CS0= xx (6) (5) Main PLLx MCS= 0 MCM=1 SCS=1 SCM=1 CS1, CS0= xx PLL1 Main MCS=1 MCM= 0 SCS=1 SCM=1 (6) CS1, CS0= 00 PLL2 Main MCS=1 MCM= 0 SCS=1 SCM=1 (6) CS1, CS0= 01 PLL4 Main MCS=1 MCM= 0 SCS=1 SCM=1 (6) CS1, CS0= 10 Main Sub MCS=1 MCM=1 SCS= 0 SCM=1 (9) (8) Sub MCS=1 MCM=1 (14) SCS= 0 (9) SCM= 0 CS1, CS0= xx CS1, CS0= xx Main MCS=1 (10) MCM=1 SCS=1 SCM=1 (2) CS1, CS0= xx (3) (4) (7) (7) (11) (12) (13) Sub PLLx MCS= 0 MCM=1 SCS= 1 SCM= 0 CS1, CS0= xx PLL1 multiplication MCS= 0 MCM= 0 (5) SCS=1 (7) SCM=1 CS1, CS0= 00 PLL2 multiplication MCS= 0 MCM= 0 (5) SCS=1 SCM=1 (7) CS1, CS0= 01 PLL4 multiplication MCS= 0 MCM= 0 (5) SCS=1 (7) SCM=1 CS1, CS0= 10 (15) PLL1 Sub MCS=1 MCM= 0 SCS= 0 SCM=1 (15) CS1, CS0= 00 PLL2 Sub MCS=1 MCM= 0 SCS= 0 SCM=1 (15) CS1, CS0= 01 Sub PLL4 MCS=1 MCM= 0 SCS= 0 SCM=1 (15) CS1, CS0= 10 (1) MCS bit "0" write (2) PLL clock oscillation stabilization wait end & CS1, CS0=00 (3) PLL clock oscillation stabilization wait end & CS1, CS0=01 (4) PLL clock oscillation stabilization wait end & CS1, CS0=10 (5) MCS bit "1" write (within Watchdog reset) (6) Synchronous timing of PLL clock and Main clock (7) SCS bit "0" write (8) Sub clock oscillation stabilization wait end (max. 215/SCLK) (9) SCS bit "1" write (10) Main clock oscillation stabilization wait end (11) Main clock oscillation stabilization wait end & CS1, CS0=00 (12) Main clock oscillation stabilization wait end & CS1, CS0=01 (13) Main clock oscillation stabilization wait end & CS1, CS0=10 (14)SCS bit "1" write, MCS bit "0" write (15)Synchronous timing of PLL clock and Sub clock MCS : PLL clock selection bit of Clock selection register (CKSCR) MCM : PLL clock display bit of Clock selection register (CKSCR) SCS : Sub clock selection bit of Clock selection register (CKSCR) SCM : Sub clock display bit of Clock selection register (CKSCR) CS1, CS0 : Multiplication factor selection bit of Clock selection register (CKSCR) Note: The initial value for machine clock is the main clock (MCS = 1, SCS = 1). If both the SCS and MCS bits are "0", the higher priority is given to SCS and the sub clock mode is entered. When the mode needs to be switched from sub to PLL, the oscillation stabilization wait time selection bits (WS1, WS0) of CKSCR must be set to "01B", "10B", or "11B". CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 139 CHAPTER 5 CLOCK 5.5 Oscillation Stabilization Wait Time 5.5 MB90330A Series Oscillation Stabilization Wait Time When power is turned on, the stop mode is quit, or the clock mode changes from the sub to main or PLL clock, the oscillation stabilization wait time is required after the oscillation begins. This is because the oscillation of the oscillation clock remains in stopped state. Also when the clock mode changes from main to PLL, the oscillation stabilization wait time is required after the PLL oscillation begins. ■ Oscillation Stabilization Wait Time In general, ceramic and crystal oscillators require several milliseconds to some tens of milliseconds until the they provide stable oscillation at their natural frequency (oscillation frequency). Accordingly, CPU operation is disabled immediately after the oscillation starts and the clock supply to the CPU is enabled until the oscillation stabilization wait time has elapsed. This gives the oscillation time to stabilize. It is necessary to select a oscillation stabilization wait time appropriate to an oscillator to be used because the oscillation stabilization time depends on the type of oscillator (crystal, ceramic, etc.). The oscillation stabilization wait time can be selected by setting in the clock selection register (CKSCR). When changing the clock mode from main to PLL, the CPU operates with the main clock during the PLL oscillation stabilizing wait time before the mode actually changes to PLL. Figure 5.5-1 shows the operation immediately after starting the oscillation. Figure 5.5-1 Operation Immediately after the Start of Oscillation Oscillation time of oscillator Oscillation stabilization Starting normal operation or switching to PLL clock wait time X1 Oscillation start 140 Oscillation stabilization FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 5 CLOCK 5.6 Connection of Oscillator and External Clock MB90330A Series 5.6 Connection of Oscillator and External Clock MB90330A series, containing a system clock generator circuit, generates the clock with the oscillator connected externally. It is also possible to input an externally generated clock. ■ Connection of Oscillator and External Clock ● Example of connection of crystal oscillator or ceramic oscillator Connect the crystal or ceramic oscillator as shown in Figure 5.6-1. Figure 5.6-1 Example of Connection of Crystal Oscillator or Ceramic Oscillator MB90330A series X0 (X0A) X1 (X1A) ● Example of connection of external clock As shown in Figure 5.6-2, connect the external clock to the X0 pin and open the X1 pin. Figure 5.6-2 Example of Connection of External Clock MB90330A series X0 (X0A) X1 (X1A) Open CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 141 CHAPTER 5 CLOCK 5.6 Connection of Oscillator and External Clock 142 FUJITSU MICROELECTRONICS LIMITED MB90330A Series CM44-10129-6E CHAPTER 6 LOW-POWER CONSUMPTION MODE This chapter describes the low-power consumption mode of the MB90330A series. 6.1 Outline of Low-Power Consumption Mode 6.2 Block Diagram of Low-power Consumption Control Circuit 6.3 Low-power Consumption Mode Control Register (LPMCR) 6.4 CPU Intermittent Operation Mode 6.5 Standby Mode 6.6 State Transition Diagram 6.7 State of the Pin during Standby Mode, Hold, and Reset 6.8 Precautions when Using Low-power Consumption Mode CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 143 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.1 Outline of Low-Power Consumption Mode 6.1 MB90330A Series Outline of Low-Power Consumption Mode The MB90330A series have the following CPU operation modes by selecting the operation clock and operating the control of the clock. • Clock mode (PLL clock mode, main clock mode, and sub clock mode) • CPU Intermittent operation mode (PLL clock intermittent operation mode, main clock intermittent operation mode, and sub clock intermittent operation mode) • Standby mode (sleep mode, time-base timer mode, and stop, watch mode) ■ CPU Operation Modes and Current Consumption Figure 6.1-1 shows the relationships between the CPU operation modes and current consumption. Figure 6.1-1 CPU Operation Modes and Current Consumption Current consumption Several dozen mA CPU Operation mode PLL clock mode Clock multiplied by four Clock multiplied by two Clock multiplied by one Clock multiplied by four PLL clock intermittent operation mode Clock multiplied by two Clock multiplied by one Main clock mode (1/2 HCLK) Main clock intermittent operation mode Sub clock mode Sub clock intermittent operation mode Several mA Standby mode Sleep mode Time-base timer mode Watch mode Several μA Stop mode Low-power consumption mode Note: This diagram shows an image of each mode, so its values may differ from actual current consumption. 144 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.1 Outline of Low-Power Consumption Mode MB90330A Series ■ Clock Mode ● PLL clock mode In PLL clock mode, the CPU and peripheral function operate on a PLL multiplying clock of oscillation clock (HCLK). Note: When using USB HOST and the USB function, you need to set to the PLL clock mode. ● Main clock mode In main clock mode, the CPU and peripheral function operate on a clock with 2-frequency division of oscillation clock (HCLK). In this mode, the PLL multiplying circuit stops. ● Sub clock mode In sub clock mode, the CPU and peripheral function operate on a sub clock (SCLK). In this mode, the main clock and PLL multiplying circuit stop. Reference: For the clock mode, see Section "5.4 Clock Mode". ■ CPU Intermittent Operation Mode The CPU intermittent mode operates the CPU intermittently and lowers the power consumption while supplying the high-speed clock to the peripheral functions. The CPU intermittent operation mode is a mode for supplying intermittent clock only to the CPU when it makes access to the registers, internal memory, peripheral functions, or external devices. ■ Standby Mode Standby mode reduces the power consumption by the low-power consumption control circuit which stops clock supply to the CPU (sleep mode), stops clock supply to the CPU and peripheral functions (time-base timer mode), or stops the oscillation clock (stop mode). ● PLL sleep mode The PLL sleep mode terminates the CPU operation clock in the PLL clock mode and operates components except for CPU under the PLL clock. ● Main sleep mode The main sleep mode terminates the CPU operation clock in the main clock mode and operates components except for the CPU under the main clock. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 145 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.1 Outline of Low-Power Consumption Mode MB90330A Series ● Sub sleep mode The sub sleep mode terminates the CPU operation clock in the sub clock mode and operates components except for the CPU under the sub clock. ● Time-base timer mode The time-base timer mode terminates all the operations other than the oscillation clock, the time-base timer, and the clock timer, terminating all the functions other than the time-base timer and the watch timer. ● Watch mode It is a mode by which only the clock timer is operated. Only the sub clock operates and the main clock and PLL multiplication circuit stops. ● Stop mode Stop mode is mode for stopping original oscillation and all functions are stopped. Note: In the stop mode, data is kept at the lowest power consumption since the oscillation clock is terminated. When you change the clock mode, be sure not to shift to other clock modes or the low-power consumption mode until you complete the clock mode change. Completion of the switching can be checked by referring the MCM and SCM bits of the CKSCR. The mode transits to the standby mode is also inhibited during the USB is transferred. 146 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.2 Block Diagram of Low-power Consumption Control Circuit MB90330A Series 6.2 Block Diagram of Low-power Consumption Control Circuit The low-power consumption control circuit is composed of the following seven blocks. • CPU intermittent operation selector • Standby controller circuit • CPU clock controller circuit • Peripheral clock controller circuit • Pin high-impedance controller circuit • Internal reset generator circuit • Low-power consumption mode control register (LPMCR) ■ Block Diagram of Low-power Consumption Control Circuit Figure 6.2-1 shows the block diagram of the low-power consumption control circuit. Figure 6.2-1 Block Diagram of Low-power Consumption Control Circuit Low power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 Reserved Pin high impedance control circuit Pin Hi-Z control Internal reset Internal reset generation circuit Intermittent cycle selection RST Pin CPU intermittent operation sector CPU clock control circuit Reset (Cancellation) Watch, Stop, Sleep signal Standby control circuit 2 CPU clock Watch, Stop signal Interrupt (Cancellation) Oscillation stable wait cancellation Clock generation unit Peripheral clock control circuit Sub clock oscillation stabilization wait cancellation Main clock oscillation stabilization wait cancellation Operation clock selector Machine clock Oscillation stable wait time selector 2 2 PLL frequency multiplication circuit SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock selection register (CKSCR) 2 -division X0 Pin X1 Pin Oscillation clock (HCLK) Oscillation clock generation circuit 2 -division 2 -division 1024 -division 2 -division 2 -division 2 -division 4 -division to Watchdog timer Sub clock (SCLK) 4 -division X0A Pin 4 512 -division -division Main clock Time-base timer 8 -division 2 -division 2 -division Watch timer X1A Pin System clock generation circuit CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 147 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.2 Block Diagram of Low-power Consumption Control Circuit MB90330A Series ● CPU intermittent operation selector The CPU intermittent operation sector selects the number of the suspended clocks in the CPU intermittent operation mode. ● Standby controller circuit The standby controller circuit controls the CPU clock control circuit and the peripheral clock control circuit, and then performs the transition to the low-power consumption mode or cancellation. ● CPU clock controller circuit The CPU clock controller circuit controls the clock supplied to CPU. ● Peripheral clock controller circuit The peripheral clock controller circuit controls the clock supplied to the peripheral functions. ● Pin high-impedance controller circuit The pin high-impedance controller circuit makes the external pin to the high-impedance while the mode is in the time-base timer mode and the stop mode. For the pin to which pull-up option is selected, you need to cut the pull-up resistance during the stop mode. ● Internal reset generator circuit This circuit generates internal reset signals. ● Low-power consumption mode control register (LPMCR) The low-power consumption mode control register (LPMCR) shifts to/cancels the standby mode or sets the CPU intermittent operation function. 148 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.3 Low-power Consumption Mode Control Register (LPMCR) MB90330A Series 6.3 Low-power Consumption Mode Control Register (LPMCR) The low-power consumption mode control register (LPMCR) performs transition to/ cancellation of the low-power consumption mode or sets the number of the CPU clock suspend cycles in the CPU intermittent operation mode. ■ Low-power Consumption Mode Control Register (LPMCR) Figure 6.3-1 shows the configuration of the low-power consumption mode control register (LPMCR). Figure 6.3-1 Configuration of Low-power Consumption Mode Control Register (LPMCR) Address bit15 0000A0H bit7 (CKSCR) bit3 bit2 bit1 bit0 Initial value STP SLP SPL RST TMD CG1 CG0 RESV 00011000B W bit6 bit5 W R/W bit4 W W 0 CG1 CG0 R/W Count bit for CPU clock temporary halt cycle 0 0 0 cycles (CPU clock = Resource clock) 0 1 1 0 8 cycles (CPU clock: Resource clock = 1:3 to 4 approx.) 1 1 32 cycles (CPU clock: Resource clock = 1:9 to 10 approx.) TMD 16 cycles (CPU clock: Resource clock = 1:5 to 6 approx.) Time-base timer mode bit 0 Switches to the time-base timer mode or watch mode 1 No change, no effect on operation RST Internal reset signal generation bit 0 Generates an internal reset signal of three machine cycles 1 No change, no effect on operation SPL Watch and pin state setting bit (for time-base timer mode and stop mode) 0 Previous pin state retained 1 High impedance SLP Sleep mode bit 0 No change, no effect on operation 1 Switches to sleep mode STP CM44-10129-6E R/W Reserved Always write "0" to this bit RESV R/W : Read/write W : Write-only : Initial value R/W Stop mode bit 0 No change, no effect on operation 1 Switches to stop mode FUJITSU MICROELECTRONICS LIMITED 149 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.3 Low-power Consumption Mode Control Register (LPMCR) MB90330A Series Table 6.3-1 Function Description of Each Bit of Low-power Consumption Mode Control Register (LPMCR) Bit name Functions STP: Stop mode bit • This bit indicates the transition to the stop mode. • Writing "1" to this bit changes the stop mode. • Writing "0" to this bit has no influence on operation. • Cleared to "0" by generation of a reset or interrupt request. • The bit always returns "0" when read. bit 6 SLP: Sleep mode bit • This bit indicates the transition to the sleep mode. • Writing "1" to this bit changes the sleep mode. Writing "0" to this bit has no influence on operation. • Cleared to "0" by generation of a reset or interrupt request. • The bit always returns "0" when read. bit 5 SPL: Pin state specification bit (At the stop mode of the watch and the time-base timer) • Valid only while in the watch mode, time-base timer, or stop mode. • A "0" in this bit causes the clock to remain at the level of the external pin. • An external pin is made high impedance in case of "1". • The bit is initialized to "0" at a reset. bit 4 RST: Internal reset signal generation bit • Writing "0" to this generator generates the internal reset signal three machine cycle. • Writing "1" to this bit has no influence on operation. • The bit always returns "1" when read. bit 3 TMD: Clock, time-base timer mode bit • This bit indicates the transition to the watch and time-base timer mode. • Writing "0" to this bit while in main or PLL clock mode changes the time-base timer mode. • Writing "0" to this bit while in sub clock mode changes the watch mode. • Initialized to "1" by generation of a reset or interrupt request. • The bit always returns "1" when read. bit 2, bit 1 CG1,CG0: Temporary CPU clock stop Cycle count selection bit • Bit used for setting the number of suspension cycles of the CPU clock for CPU intermittent operation function. • Stops the CPU clock supply for the specified number of cycles each time the instruction is executed once. • Selectable from four types of clocks counts. • The bit is initialized to "00B" at a reset. bit 0 Reserved: Reserved bit bit 7 150 Be sure to set this bit to "0". FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.3 Low-power Consumption Mode Control Register (LPMCR) MB90330A Series ■ Access to Low-power Consumption Mode Control Register Transition to the low-power consumption modes (stop mode, sleep mode, time-base timer mode, and watch mode) by writing to the low-power consumption mode control register is made, in this case, be sure to use the instructions in Table 6.3-2. The low-power consumption mode transition instruction in Table 6.3-2 must always be followed by an array of instructions highlighted by a line below. MOV LPMCR, #H'XX ; the low-power consumption mode transition instruction in Table 6.3-2 NOP NOP JMP $+3 MOV A,#H'10 ; jump to next instruction ; any instruction The devices does not guarantee its operation after returning from the low-power consumption mode if you place an array of instructions other than the one enclosed in the line. To access the low-power consumption mode control register (LPMCR) with C language, refer to "■ Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to Enter the Standby Mode" in the Section "6.8 Precautions when Using Low-power Consumption Mode". To write word length data into the low-power consumption mode control register (LPMCR), use even addresses. Transition to the low-power consumption mode is made by writing at odd addresses may cause an erroneous operations. When you control other functions than the functions listed in Figure 6.3-1, you may use any instruction. Table 6.3-2 List of Instructions Used for Transition to Low-power Consumption Mode MOV io,#imm8 MOV io,A MOV @RLi+disp8,A MOVW io,#imm16 MOVW io,A MOVW @RLi+disp8,A SETB io:bp CLRB io:bp MOV dir,#imm8 MOV dir,A MOV eam,#imm8 MOV addr16,A MOV eam,Ri MOV eam,A MOVW dir,#imm16 MOVW dir,A MOVW eam,#imm16 MOVW addr16,A MOVW eam,RWi MOVW eam,A SETB dir:bp CLRB dir:bp SETB addr16:bp CLRB addr16:bp ■ Priority Level of STP, SLP, and TMD Bit When the stop mode, sleep mode, and watch mode • time-base timer mode requests are performed at the same time, requests are processed according to the following order. Stop mode request > watch mode • time-base timer mode request > sleep mode request CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 151 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.4 CPU Intermittent Operation Mode 6.4 MB90330A Series CPU Intermittent Operation Mode The CPU intermittent operation mode is a mode for reducing the power consumption by intermittently operating the CPU while operating the external bus and peripheral functions at high speed. ■ CPU Intermittent Operation Mode The CPU intermittent operation mode is a mode for stopping the clock supplied to the CPU for a predetermined period of time for each instruction execution to delay the internal bus cycle start when accessing the registers, internal memory (ROM, RAM), I/O, peripheral functions, or external bus. If the CPU operation speed is decreased while supplying a high-speed peripheral clock to the peripheral functions, processing at low-power consumption becomes available. • Selection of the number of the suspend cycles of the clock supplied to CPU is made in the CPU clock suspend cycle number selection bit (CG1 and CG0) of the low-power consumption mode control register (LPMCR). • The external bus operation itself uses the same clock as the peripheral functions. • The instruction execution time in CPU intermittent operation mode can be calculated by adding to the ordinary execution time the compensation value obtained by multiplying the instruction execution count for accessing the registers, internal memory, internal peripheral function, and external bus by the number of suspension cycles. Figure 6.4-1 shows the operation clock for CPU intermittent operation mode. Figure 6.4-1 Clock for the CPU Intermittent Operation Mode Peripheral clock CPU clock Suspended cycle 1 instruction execution cycle Internal bus activation 152 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90330A Series 6.5 Standby Mode Standby modes are: sleep (PLL sleep, main sleep, sub sleep), watch, time-base timer, and stop mode. ■ Operation Status in Standby Mode Table 6.5-1 shows the operation state in the standby mode. Table 6.5-1 Operation Status in Standby Mode Standby Mode Transition Condition PLL sleep mode SCS=1 MCS=0 SLP=1 Main sleep mode SCS=1 MCS=1 SLP=1 Sub sleep mode SCS=0 SLP=1 Main Clock Sub Clock Machine Clock CPU Peripheral Pin Operation Operation Release Method Operation Sleep mode Time-base timer mode Time-base (SPL=0) timer Time-base timer mode mode (SPL=1) Watch mode Watch mode (SPL=0) Operation Stops Operation SCS=1 TMD=0 Hold Operation Stops SCS=1 TMD=0 Hi-Z SCS=0 TMD=0 Reset or interrupt Hold Stops Watch mode (SPL=1) Stops *1 Stops *2 SCS=0 TMD=0 Hi-Z Stops Stop mode (SPL=0) STP=1 Stop mode (SPL=1) STP=1 Stop mode *1: *2: SPL: SLP: STP: TMD: MCS: SCS: Hi-Z: RST: Hold Stops Stops Hi-Z The time-base timer and the clock timer work. The watch timer operates. Pin state specification bit of low-power consumption mode control register (LPMCR) Sleep mode bit of low-power consumption mode control register (LPMCR) Stop mode bit of low-power consumption mode control register (LPMCR) Watch and time-base timer mode bit of low-power consumption mode control register (LPMCR) Machine clock selection bit of clock selection register (CKSCR) Machine clock selection bit (sub) of clock selection register (CKSCR) High impedance External reset pin CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 153 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode 6.5.1 MB90330A Series Sleep Mode Sleep mode is mode for stopping the CPU operation clock and the operation other than CPU continues. When you instruct the transition to the sleep mode with the low-power consumption mode control register (LPMCR), the transition to the PLL sleep mode is made if the PLL clock mode is set, the transition to the main sleep mode is made if the main clock mode is set, and the transition to the sub sleep mode is made if the sub clock mode is set. ■ Transition to Sleep Mode If you write "1" to the sleep mode bit (SLP), "1" to the watch/time-base timer mode bit (TMD), and "0" to the stop mode bit (STP) of the low-power consumption mode control register (LPMCR), the transition to the sleep mode is made. In this case, the transition to the PLL sleep mode is made if the clock selection register (CKSCR) is in the state of PLL clock selection bit (MCS)=0 and sub clock selection bit (SCS)=1, transition to the main sleep mode is made if MCS=1 and SCS=1, and transition to the sub sleep mode is made if SCS=0. Note: If you write "1" to the SLP bit and the STP bit of the LPMCR register at the same time, the STP bit is prioritized and the transition to the stop mode is made. If you write "1" to the SLP bit and "0" to the TMD bit in the low-power consumption mode control register, the TMD bit is prioritized and the transition to the time-base timer mode or the watch mode is made. ● Data retention function In the sleep mode, the contents of the dedicated registers such as accumulators and the internal RAM are held unchanged. ● Holding function In the sleep mode, the external bus hold function operates and the state becomes the hold status upon a hold request. ● Operation during an interrupt request Writing "1" to the SLP bit in the LPMCR register does not make the transition to the sleep mode if there is an interrupt request. Therefore, the CPU executes the next instruction when it is in a state accepting no interrupts and branches immediately to the interrupt processing routine when it is in a state accepting interrupts. ● Pin state In the sleep mode, the preceding state is retained except for the pins used as the bus input/output or the bus control. 154 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90330A Series ■ Cancellation of Sleep Modes The low-power consumption control circuit clears sleep mode by reset input or interrupt generation. ● Return by reset Initialization to the main clock mode is made by reset. ● Return by interrupt If there is an interrupt request higher than level 7 from the peripheral circuit and others in the sleep mode, the sleep mode is canceled. After clearing sleep mode, the action is the same as for ordinary interrupt processing. When an interrupt is acceptable by settings in the I flag of the condition code register (CCR), the interrupt level mask register (ILM), and the interrupt control register (ICR), the CPU performs interrupt processing. When an interrupt is not acceptable, processing from the instruction succeeding the one which has specified sleep mode continues. Figure 6.5-1 shows clearing sleep mode by interrupt generation. Figure 6.5-1 Cancellation of Sleep Mode of Interrupt Generation Interrupt enable flag setting of Peripheral function INT generation (IL<7) No Sleep cancellation NO No Sleep cancellation YES YES I=0 Next instruction execution Sleep cancellation NO YES ILM<IL Next instruction execution NO Interrupt execution Note: When handling an interrupt, the CPU usually services the interrupt after executing the instruction that follows the one specifying the sleep mode. However, if the transition to the sleep mode and the receipt of the external bus hold request occur at the same time, the transition to the interruption procedure before executing the next instruction will be made. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 155 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode 6.5.2 MB90330A Series Time-base Timer Mode The time-base timer mode terminates the original oscillation and all the operations other than the time-base timer and the watch timer, resulting in termination of all the functions other than the time-base timer and the watch timer. ■ Transition to Time-base Timer Mode In the PLL clock mode or the main clock mode (the sub clock display bit (SCM)=1 of the clock selection register (CKSCR)), writing "0" to the watch/time-base timer mode bit (TMD) of the low-power consumption mode control register (LPMCR) makes the transition to the time-base timer mode. ● Data retention function In the time-base timer mode, the contents of dedicated registers such as accumulators and the internal RAM are held unchanged. ● Holding function In the time-base timer mode, the external bus hold function is terminated, thereby neglecting a hold request even a request is input. If a hold request is input during the transition to the time-base timer mode, the condition of bus high-impedance is maintained and the HAK signal may not become "L". ● Operation during an interrupt request Writing "0" to the TMD bit of the low-power consumption mode control register (LPMCR) does not make the transition to the time-base timer mode if there is an interrupt request. ● Pin state You can set whether the external pin in the time-base timer mode should be retained in the preceding state or becomes to the high impedance state by controlling the pin state specification bit (SPL) in the LPMCR register. 156 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90330A Series ■ Cancellation of Time-base Timer Modes The low-power consumption circuit cancels the time-base timer mode by generating a reset input or an interrupt request. ● Return by external reset The external reset initializes the mode to the main clock mode. ● Return by interrupt If there is an interrupt request higher than level 7 from peripheral circuit and others in the time-base timer mode (except for IL2, IL1, IL0 of the interrupt control register (ICR) = 111B), the low-power consumption control circuit cancels the time-base timer mode. After cancellation of time-base timer modes, the action is the same as for ordinary interrupt processing. When an interrupt is acceptable according to the setting of the I flag of the condition code register (CCR), the interrupt level mask register (ILM), and the interrupt control register (ICR), interrupt processing is performed. When an interrupt is not acceptable, processing from the instruction succeeding the one before entering time-base timer mode continues. Note: When handling an interrupt, the CPU usually services the interrupt after executing the instruction that follows the one specifying the time-base timer mode. When transition to time-base timer mode and acceptance of an external bus hold request have occurred at the same time, interrupt processing may transit before executing the next instruction. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 157 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode 6.5.3 MB90330A Series Watch Mode The watch mode terminates all the operations other than the sub clock and the watch timer, where almost all the functions of the chip are terminated. ■ Transition to Watch Mode In the sub clock mode (the sub clock display bit of the clock selection register (CKSCR) (SCS)=0), when you write "0" into the watch/time-base timer mode bit (TMD) of the low-power consumption mode control register (LPMCR the transition to the watch mode). ● Data retention function In the watch mode, contents of the dedicated registers such as accumulators and the internal RAM are held unchanged. ● Holding function During the watch mode, the external bus hold function halts, thereby neglecting a hold request if a hold request is input. If a hold request is input during the transition to the watch mode, the condition of bus highimpedance is maintained and the HAK signal may not become "L". ● Operation during an interrupt request When "0" is set to the TMD bit of the LPMCR register, transition to the watch mode is not made if there is an interrupt request. ● Pin state setting You can set whether the external pin in the watch mode should be retained in the preceding state or become to the high impedance state by controlling the pin state specification bit (SPL) in the LPMCR register. ■ Cancellation of Watch Mode The low-power consumption circuit cancels the watch mode by generating a reset input or an interrupt request. ● Return by Reset When clearing watch mode by a reset cause, transition occurs to oscillation stabilization wait reset state after clearing watch mode. The reset sequence is executed after the oscillation stabilization wait time. ● Return by interrupt If there is an interrupt request higher than level 7 from peripheral circuits and others in the watch mode (except for IL2, IL1, IL0 of the interrupt control register (ICR) = 111B), the low-power consumption control circuit cancels the watch mode and immediately changes to the sub clock mode. After transiting to sub clock mode, the action is the same as for ordinary interrupt processing. When an interrupt is acceptable by settings in the I flag of the condition code register (CCR), the interrupt level mask register (ILM), and the interrupt control register (ICR), interrupt processing is carried out. When an interrupt is not acceptable, processing from the instruction succeeding the one caused to enter clock mode continues. 158 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90330A Series Note: When handling an interrupt, the CPU usually services the interrupt after executing the instruction that follows the one specifying the watch mode. However, if the transition to the watch mode and the receipt of the external bus hold request occur at the same time, transition to interruption procedure may be made before execution of the next instruction. Figure 6.5-2 shows the cancellation operation of the watch mode. Figure 6.5-2 Cancellation of Watch Mode (External Reset) RST Pin Watch mode Main clock Sub clock suspension oscillation PLL clock oscillation Oscillation stabilizing wait suspension oscillation CPU clock suspension CPU operation suspension Main clock Processing Reset sequence Reset cancellation Watch mode cancellation CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 159 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode 6.5.4 MB90330A Series Stop Mode Stop mode is mode for stopping original oscillation and all functions are stopped. That means, data can be held with the lowest power consumption. ■ Transition to Stop Mode If you write "1" into the stop mode bit (STP) of the low-power consumption mode control register (LPMCR), the transition to the stop mode is made. ● Data retention function In the stop mode, the contents of the dedicated registers such as accumulators and the internal RAM are held unchanged. ● Holding function In the stop mode, the external bus hold function is terminated, thereby neglecting a hold request even a request is input. If you input a hold request while transiting to the stop mode, the HAK signal may not get to "L" with the bus being high impedance. ● Operation during an interrupt request When you write "1" into the SLP bit of the LPMCR register, the transition to the stop mode is not made if there is an interrupt request. ● Pin state setting You may determine by the pin state specification bit (SPL) of the LPMCR register whether the external pin in the stop mode should be retained in the preceding state or be shifted into the high impedance state. ■ Cancellation of Stop Modes The low-power consumption control circuit clears stop mode when reset input or interrupt occurs. As oscillation of the operation clock is stopped when returning from stop mode, the low-power consumption control circuit first transits to the oscillation stabilization wait state and then clears stop mode. ● Return by Reset When clearing stop mode by a reset cause, transition occurs to oscillation stabilization wait reset state after clearing stop mode. The reset sequence is executed after the oscillation stabilization wait time. ● Return by interrupt If there is an interrupt request higher than level 7 from the peripheral circuit and others in the stop mode (except for IL2, IL1, IL0 of the interrupt control register (ICR) = 111B), the low-power consumption control circuit cancels the stop mode. After canceling the stop mode, a normal interrupt procedure is executed when elapsing the main clock oscillation stable wait time specified by the oscillation stable wait time selection bit (WS1, WS0) of the clock selection register (CKSCR). When an interrupt is acceptable by settings in the I flag of the condition code register (CCR), the interrupt level mask register (ILM), and the interrupt control register (ICR), interrupt processing is carried out. When an interrupt is not acceptable, processing from the instruction succeeding the one caused to enter stop mode continues. 160 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode MB90330A Series Notes: • When handling an interrupt, the CPU usually services the interrupt after executing the instruction that follows the one specifying the stop mode. When transition to stop mode and acceptance of an external bus hold request have occurred at the same time, interrupt processing may transit before executing the next instruction. • In PLL stop mode, the main clock and PLL multiplier circuit remain stopped. When the CPU returns from PLL stop mode, therefore, it is necessary to allow for the main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time. In this case, the oscillation stabilization wait time concurrently counts the main clock oscillation stabilization wait time and the PLL clock oscillation stabilization wait time, according to the value specified in the oscillation stabilization wait time selection bit (CKSCR; WS1, WS0) of the clock selection register, thus the CKSCR; WS1, WS0 bit must be set in accordance with the longer oscillation stabilization wait time. However, as the PLL clock stabilization wait time requires at least 214/HCLK, be sure to set the CKSCR; WS1, WS0 bit to "10B" or "11B". Figure 6.5-3 shows the cancellation operation of the stop mode. Figure 6.5-3 Cancellation of Stop Mode (External Reset) RST Pin Stop mode Main clock Oscillation stabilizing wait oscillation Sub clock CPU clock CPU operation oscillation PLL clock suspension Main clock suspension Processing Reset sequence Reset cancellation Stop mode cancellation CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 161 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.6 State Transition Diagram 6.6 MB90330A Series State Transition Diagram The transition of the operation state and the transition conditions of MB90330A series are shown. ■ State Transition Diagram Figure 6.6-1 shows the transition of the operation state and the transition conditions of MB90330A series. Figure 6.6-1 State Transition and Transition Conditions External reset, Watchdog timer reset, Software reset Power on Reset Power on reset SCS=0 Oscillation stabilization wait end SCS=1 MCS=0 Main clock mode MCS=1 SLP=1 SCS=0 PLL clock mode Interruption PLL sleep mode TMD=0 Main time-base timer mode STP=1 Interruption TMD=0 Interruption Oscillation stabilization wait end Main clock oscillation stablization wait Interruption Sub sleep mode TMD=0 PLL time-base timer mode STP=1 Main stop mode SLP=1 Interruption Main sleep mode TMD=0 SCS=1 SLP=1 Interruption Sub clock mode Watch mode STP=1 PLL stop mode * Interruption Interruption Oscillation stabilization wait end PLL clock oscillation stabilization wait Sub stop mode Interruption Oscillation stabilization wait end Sub clock oscillation stabilization wait * : Interrupt from USB bus at interrupt + USB function 162 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.6 State Transition Diagram MB90330A Series ■ Operation Status in Low-power Consumption Mode Table 6.6-1 lists the operation states in low-power consumption mode. Table 6.6-1 Operation States in Low-power Consumption Mode Operating State Main Clock Sub Clock PLL Clock PLL PLL sleep CPU Operation Operation Operation Operation Peripheral Operation Clock Time-base Timers Operation Operation PLL time-base timer PLL stop PLL oscillation stabilization waiting Stops Stops Stops Operation Operation Operation Main Main sleep Operation Operation Operation Main time-base timer Main stop Main oscillation stabilization waiting Stops Stops Stops Operation Operation Sub Operation Stops Sub-stop Reset CM44-10129-6E Stops Stops Sub oscillation stabilization waiting Power on reset Stops Operation Sub sleep Clock Stops Stops Stops Operation Stops Operation Stops Operation Operation Operation Stops Stops Operation Operation Operation Operation Stops Stops Operation Operation Clock Source PLL Clock Main Clock Operation Stops Sub Clock Operation Main Clock Stops Operation Stops Operation Stops Stops FUJITSU MICROELECTRONICS LIMITED Operation 163 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.7 State of the Pin during Standby Mode, Hold, and Reset MB90330A Series State of the Pin during Standby Mode, Hold, and Reset 6.7 The state of the pin at the time of the stand by mode, the hold, or the reset is shown for each memory access code. ■ Pin State in Single-chip Mode Table 6.7-1 shows the state of the pin in the single-chip mode. Table 6.7-1 Pin State in Single-chip Mode In stop mode Pin Name At sleep At holding SPL=0 SPL=1 Input cutoff/ The state immediately before hold Input cutoff/ output Hi-Z At a reset P07 to P00 P17 to P10 P27 to P20 P37 to P30 P47 to P40 P57 to P50 The state immediately before hold*2 P77 to P70 *3 *2,*3 This state does not exist. Impossible to input/ output Hi-Z P87 to P80 P96 to P90 PA7 to PA0 PB6 to PB0 P67 to P60 Possible to input*1 Possible to input*1 Impossible to input USB port input USB port input *4 Hi-Z DVP DVM HVP *5 HVM UTEST Pull-down connect Pull-down connect Pull-down connect HCON The state immediately before hold Hold state preserved "H" output *1: Same as the other ports if this is being used for the output state. "Input enabled" means that the input function is currently enabled; Pull-up/Pull-down or an input from the external is required. *2: Outputs the initial output preceding this mode. Alternatively, this means "Input disabled" if the signal is input. "Input disabled" means that the contents of a pin are not accepted internally, because the internal circuit is not in operation although operation of the input gate nearest to the pin is currently enabled. 164 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.7 State of the Pin during Standby Mode, Hold, and Reset MB90330A Series *3: In the input shutoff state, the input is masked and the "L" level is passed to the internal. *4: When operation stops due to a cause in the USB, the signal is input via the USB port. When it stops due to another cause, the preceding state remains unchanged. *5: There is no influence in the pin USB operation. Note: The mode transits to the standby mode is also inhibited during the USB is transferred. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 165 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.7 State of the Pin during Standby Mode, Hold, and Reset MB90330A Series ■ Pin State in External Bus 16-bit Data Bus and Multiplex 16-bit External Bus Mode Table 6.7-2 shows the state of the pins of the external bus 16-bit data bus mode and the multiplex 16-bit external bus mode. Table 6.7-2 Pin State in External Bus 16-bit Data Bus and Multiplex 16-bit External Bus Mode In stop mode Pin Name At sleep At holding SPL=0 P07 to P00 (AD07 to AD00) P17 to P10 (AD15 to AD08) P27 to P20 (A23 to A16) P57(CLK) P56(RDY) P55(HAK) Impossible to Input cutoff/ input/ output Hi-Z output Hi-Z Impossible to input/ Impossible to input/ output Hi-Z output Hi-Z Output state *1,*4 Output state *1,*4 Impossible to input/ Output state*1 output Hi-Z *4 Impossible to input/ possible to output*2,*4 Impossible to input/ output state *1,*4 Impossible to input/ Impossible to input/ possible to possible to output*2 output*2,*4 Input cutoff/ The state immediately before hold *5,*6 Impossible to input The state immediately before hold*5 P54(HRQ) P53(WRH) At a reset SPL=1 *4 "L" output Input cutoff/ output Hi-Z *6 Impossible to input/ output Hi-Z "1" input "H" output *4 "H" output *4 Impossible to input/ output Hi-Z *4 "H" output P51(RD) "H" output "H" output P50(ALE) "L" output "L" output Impossible to input/ output Hi-Z Possible to output *2 The state immediately before hold*5 Input cutoff/ The state immediately before hold*5 Hold state preserved*5 P52(WRL) P37 to P30 P47 to P40 P77 to P70 P87 to P80 P96 to P90 Impossible to input/ output Hi-Z PA7 to PA0 PB6 to PB0 P67 to P60 Possible to input*3 Possible to input *3 Possible to input *3 Impossible to input DVP DVM HVP USB port input USB port input *7 Hi-Z *8 HVM UTEST Pull-down connect Pull-down connect Pull-down connect HCON Hold state preserved "H" output Hold state preserved *1: "Output status" means that although the pin driving transistor is left drive enabled, fixed value "H" or "L" is output, because operation of the internal circuit remains in stopped state. If the internal peripheral circuit is in operation and the output function is in use, the output varies except when a reset is generated. There is no output change in reset. 166 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.7 State of the Pin during Standby Mode, Hold, and Reset MB90330A Series *2: "Output enabled" means that the contents of operation appear via the pin because the pin driving transistor is in driven state and operation of the internal circuit remains enabled. *3: Same as the other ports if this is being used for the output state. "Input enabled" means that the input function is currently enabled; Pull-up/Pull-down or an input from the external is required. *4: If this is being used as an output port, it holds the preceding value. *5: Outputs the initial output preceding this mode. Alternatively, this means "input disabled" if the signal is input. "Input disabled" means that the contents of a pin are not accepted internally, because the internal circuit is not in operation although operation of the input gate nearest to the pin is currently enabled. *6: In the input shutoff state, the input is masked and the "L" level is passed to the internal. *7: When operation stops due to a cause in the USB, the signal is input via the USB port. When it stops due to another cause, the preceding state remains unchanged. *8: There is no influence in the pin USB operation. Note: The mode transits to the standby mode is also inhibited during the USB is transferred. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 167 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.7 State of the Pin during Standby Mode, Hold, and Reset MB90330A Series ■ Pin State in External Bus 8-bit Data Bus and Multiplex 8-bit External Bus Mode Table 6.7-3 shows the state of the pins of the external bus 8-bit data bus mode and the multiplex 8-bit external bus mode. Table 6.7-3 Pin Signal State in External Bus 8-bit Data Bus and Multiplex 8-bit External Bus Mode Pin Name P07 to P00 (AD07 to AD00) P17 to P10 (A15 to A08) P27 to P20 (A23 to A16) P57(CLK) In stop mode At sleep SPL=0 Output state *1 Impossible to input/ Impossible to input/ possible to output output state Output state *1 Impossible to input/ output Hi-Z *4 Impossible to input/ Impossible to input/ possible to output possible to output *2,*4 *2,*4 Output state *1,*4 Output state *1,*4 *1,*4 Input cutoff/ The state immediately before hold*5 Input cutoff/ output Hi-Z *6 Hold state preserved*5 P53(WRH) P52(WRL) P51(RD) P50(ALE) P37 to P30 P47 to P40 P77 to P70 P87 to P80 P96 to P90 PA7 to PA0 PB6 to PB0 P67 to P60 DVP DVM HVP HVM UTEST HCON *2 Impossible to input*4 P56(RDY) P55(HAK) P54(HRQ) At a reset Impossible to input/ Impossible to input/ output Hi-Z output Hi-Z Impossible to input/ Input cutoff/ output Hi-Z output Hi-Z Output state *1 At holding SPL=1 "H" output*5 "H" output*5 "H" output "H" output "L" output "L" output Hold state preserved*5 Input cutoff/ The state immediately before hold*5 Possible to input*3 Possible to input*3 USB port input USB port input *7 "L" output Impossible to input/ "1" input output Hi-Z The state immediately before hold*5 Impossible to input/ output Hi-Z *4 "H" output Impossible to input/ output Hi-Z "L" output Impossible to input/ The state output Hi-Z immediately before *5 hold Possible to input*3 Impossible to input Hi-Z *8 Pull-down connect Pull-down connect The state immediately before Hold state preserved hold Pull-down connect "H" output *1: "Output status" means that although the pin driving transistor is left drive enabled, fixed value "H" or "L" is output, because operation of the internal circuit remains in stopped state. If the internal peripheral circuit is in operation and the output function is in use, the output varies except when a reset is generated. There is no output change in reset. 168 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.7 State of the Pin during Standby Mode, Hold, and Reset MB90330A Series *2: "Output enabled" means that the contents of operation appear via the pin because the pin driving transistor is in driven state and operation of the internal circuit remains enabled. *3: Same as the other ports if this is being used for the output state. "Input enabled" means that the input function is currently enabled; Pull-up/Pull-down or an input from the external is required. *4: If this is being used as an output port, it holds the preceding value. *5: Outputs the initial output preceding this mode. Alternatively, this means "Input disabled" if the signal is input. "Input disabled" means that the contents of a pin are not accepted internally, because the internal circuit is not in operation although operation of the input gate nearest to the pin is currently enabled. *6: In the input shutoff state, the input is masked and the "L" level is passed to the internal. *7: When operation stops due to a cause in the USB, the signal is input via the USB port. When it stops due to another cause, the preceding state remains unchanged. *8: There is no influence in the pin USB operation. Note: The mode transits to the standby mode is also inhibited during the USB is transferred. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 169 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.7 State of the Pin during Standby Mode, Hold, and Reset MB90330A Series ■ Pin State in External Bus 16-bit Data Bus and Non-multiplex 16-bit External Bus Mode Table 6.7-4 shows the state of the pins of the external bus 16-bit data bus mode and the non-multiplex 16bit external bus mode. Table 6.7-4 Pin State in External Bus 16-bit Data Bus and Non-multiplex 16-bit External Bus Mode Pin Name P07 to P00 (D07 to D00) P17 to P10 (D15 to D08) P37 to P30 (A07 to A00) P47 to P40 (A15 to A08) P27 to P20 (A23 to A16) P57(CLK) P56(RDY) P55(HAK) P54(HRQ) P53(WRH) P52(WRL) P51(RD) P50(ALE) P77 to P70 P87 to P80 P96 to P90 PA7 to PA0 PB6 to PB0 P67 to P60 DVP DVM HVP HVM UTEST HCON In stop mode At sleep SPL=0 Possible to input/ output Hi-Z At holding SPL=1 At a reset Impossible to input/ output Hi-Z Input cutoff/ output Hi-Z Impossible to input/ output Hi-Z Output state*1 Output state*1 Output state*1 Output state *1,*4 Output state *1,*4 Impossible to input/ Impossible to input/ possible to possible to output*1,*4 output*2,*4 The state immediately before hold*5 "H" output*5 Input cutoff/ The state immediately before hold*5 Input cutoff/ output Hi-Z Impossible to input/ output Hi-Z *4 Impossible to input/ possible to output*2,*4 Impossible to input Impossible to input/ possible to output*2 *4 *6 "L" output Impossible to input/ output Hi-Z "1" input "H" output*5 Impossible to input/ output Hi-Z *4 "H" output Impossible to input/ output Hi-Z Possible to output*2 "H" output "H" output "L" output "L" output The state immediately before hold*5 Input cutoff/ The state immediately before hold*5 Possible to input*3 Possible to input*3 The state immediately before hold*5 Possible to input*3 Impossible to input/ output Hi-Z Impossible to input Hi-Z *7 USB port input USB port input Pull-down connect The state immediately before hold Pull-down connect Pull-down connect Hold state preserved "H" output *8 *1: "Output status" means that although the pin driving transistor is left drive enabled, fixed value "H" or "L" is output, because operation of the internal circuit remains in stopped state. If the internal peripheral circuit is in operation and the output function is in use, the output varies except when a reset is generated. There is no output change in reset. *2: "Output enabled" means that the contents of operation appear via the pin because the pin driving transistor is in driven state and operation of the internal circuit remains enabled. 170 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.7 State of the Pin during Standby Mode, Hold, and Reset MB90330A Series *3: Same as the other ports if this is being used for the output state. "Input enabled" means that the input function is currently enabled; Pull-up/Pull-down or an input from the external is required. *4: If this is being used as an output port, it holds the preceding value. *5: Outputs the initial output preceding this mode. Alternatively, this means "Input disabled" if the signal is input. "Input disabled" means that the contents of a pin are not accepted internally, because the internal circuit is not in operation although operation of the input gate nearest to the pin is currently enabled. *6: In the input shutoff state, the input is masked and the "L" level is passed to the internal. *7: When operation stops due to a cause in the USB, the signal is input via the USB port. When it stops due to another cause, the preceding state remains unchanged. *8: There is no influence in the pin USB operation. Note: The mode transits to the standby mode is also inhibited during the USB is transferred. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 171 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.7 State of the Pin during Standby Mode, Hold, and Reset MB90330A Series ■ Pin State in External Bus 8-bit Data Bus and Non-multiplex 8-bit External Bus Mode Table 6.7-5 shows the state of the pins of the external bus 8-bit data bus mode and the non-multiplex 8-bit external bus mode. Table 6.7-5 Pin State in External Bus 8-bit Data Bus and Non-multiplex 8-bit External Bus Mode Pin Name P07 to P00 (D07 to D00) P37 to P30 (A07 to A00) P47 to P40 (A15 to A08) P27 to P20 (A23 to A16) P57(CLK) In stop mode At sleep SPL=0 Output state *1 Output state Impossible to input/ output Hi-Z *1 Output state *1 Output state *1,*4 Impossible to input/ output Hi-Z *4 Impossible to input/ Impossible to input/ possible to output possible to output *2 *2,*4 Output state *1,*4 Impossible to input/ Impossible to input/ possible to output possible to output *1,*4 Impossible to input/ P56(RDY) P53(WRH) P52(WRL) P51(RD) P50(ALE) P17 to P10 P77 to P70 P87 to P80 P96 to P90 PA7 to PA0 PB6 to PB0 P67 to P60 DVP DVM HVP HVM UTEST HCON At a reset Impossible to input/ output Hi-Z Impossible to input/ Input cutoff/ output Hi-Z output Hi-Z *2,*4 P55(HAK) P54(HRQ) At holding SPL=1 *4 Input cutoff/ The state "L" output The state Impossible to input/ immediately before immediately before Input cutoff/*6 output Hi-Z *5 output Hi-Z "1" input hold hold *5 Hold state preserved*5 Impossible to input/ "H" output *4 "H" output *4 output Hi-Z *4 "H" output "H" output "H" output Impossible to input/ output Hi-Z "L" output "L" output Possible to output*2 Input cutoff/ The state immediately before The state immediately before hold *5 hold *5 Possible to input*3 Possible to input*3 USB port input USB port input *7 Hold state preserved*5 Possible to input*3 Impossible to input/ output Hi-Z Impossible to input Hi-Z *8 Pull-down connect Pull-down connect The state immediately before Hold state preserved hold Pull-down connect "H" output *1: "Output status" means that although the pin driving transistor is left drive enabled, fixed value "H" or "L" is output, because operation of the internal circuit remains in stopped state. If the internal peripheral circuit is in operation and the output function is in use, the output varies except when a reset is generated. There is no output change in reset. 172 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.7 State of the Pin during Standby Mode, Hold, and Reset MB90330A Series *2: "Output enabled" means that the contents of operation appear via the pin because the pin driving transistor is in driven state and operation of the internal circuit remains enabled. *3: Same as the other ports if this is being used for the output state. "Input enabled" means that the input function is currently enabled; Pull-up/Pull-down or an input from the external is required. *4: If this is being used as an output port, it holds the preceding value. *5: Outputs the initial output preceding this mode. Alternatively, this means "input disabled" if the signal is input. "Input disabled" means that the contents of a pin are not accepted internally, because the internal circuit is not in operation although operation of the input gate nearest to the pin is currently enabled. *6: In the input shutoff state, the input is masked and the "L" level is passed to the internal. *7: When operation stops due to a cause in the USB, the signal is input via the USB port. When it stops due to another cause, the preceding state remains unchanged. *8: There is no influence in the pin USB operation. Note: The mode transits to the standby mode is also inhibited during the USB is transferred. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 173 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.8 Precautions when Using Low-power Consumption Mode 6.8 MB90330A Series Precautions when Using Low-power Consumption Mode Special attention for the following is needed when using the low-power consumption mode. • Transition to standby mode and interrupt • Cancellation of standby mode by interrupt • Oscillation stabilization wait time • Switching clock mode • Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to Enter the Standby Mode ■ Transition to Standby Mode and Interrupt When there is the generation of an interrupt request to the CPU from the peripheral functions, the transition to each standby mode is not made (the transition to the standby mode is not made even after the interrupt processing) because even if you set "1" to the stop mode bit (STP) and the sleep mode bit (SLP) of the lowpower consumption mode control register (LPMCR), or "0" to the watch/time-base timer mode bit (TMD), it is ignored. In this case, if the interrupt level is higher than 7, whether or not the interrupt request is accepted by the CPU is not related to this operation. Even when the CPU is currently performing interrupt processing, the device can go to the standby mode if no other interrupt request is present with the interrupt request flag bit cleared. ■ Cancellation of Standby Mode by Interrupt When an interrupt request with an interrupt level higher than 7 has been generated from a peripheral circuit, etc. in sleep, time-base timer, or stop mode, standby mode is cleared. Whether or not the interrupt request is accepted by the CPU is not related to this operation. After the standby mode is canceled by the interruption, the operation is branched off to the interrupt processing routine, if the priority of the interruption level set bit (IL2, IL1, IL0 bits of ICR register) to the interrupt request is over the interrupt level mask register (ILM), and the interrupt is permitted by the I flag of the condition cord register (CCR) (I=1). When an interrupt is not acceptable, processing from the instruction succeeding the one which has specified standby mode continues. When performing interrupt processing, interrupt processing normally transits after executing the instruction succeeding the one specifying standby mode. Depending on the conditions for transiting to standby mode, interrupt processing may starts before executing the next instruction. Note: To prohibit a branch to the interrupt processing routine immediately after return, interrupts must be prohibited before standby mode is set. 174 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.8 Precautions when Using Low-power Consumption Mode MB90330A Series ■ Oscillation Stabilization Wait Time ● Oscillation Stabilization Wait Time of oscillation clock Because the oscillator for original oscillation is stopped in stop mode, the oscillation stabilization wait time must be required. For the oscillation stabilization wait time, you take the time selected in the oscillation stabilization wait time selection bit (WA1, WA0) of the clock selection register (CKSCR). Note: Be sure to set "00B" for the oscillation stabilization wait time selection bit (WS1, WS0) of the CKSCR register ONLY at the time of the main clock. ● Oscillation stabilization wait time of PLL clock When the transition is made from a state where the CPU is operated by the main clock and the PLL clock halts, to a mode where CPU and the peripherals are operated by the PLL clock, transition to the PLL clock oscillation stabilization wait state is made and it is operated by the main clock during the oscillation stabilization wait state. The PLL clock oscillation stabilization wait time is fixed to 214/HCLK (HCLK: oscillation clock). In sub clock mode, the main clock and PLL multiplication circuit stop. When changing to PLL clock mode, it is necessary to reserve the main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time. The oscillation stabilization wait times for main clock and PLL clock are counted simultaneously according to the value specified in the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the longer of the main clock and PLL clock oscillation stabilization wait times. The PLL clock oscillation stabilization wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register to "10B" or "11B". In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL stop mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time. The oscillation stabilization wait times for main clock and PLL clock are counted simultaneously according to the value specified in the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the longer of the main clock and PLL clock oscillation stabilization wait time. The PLL clock oscillation stabilization wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register to "10B" or "11B". ■ Switching Clock Mode When switching of the clock mode is made, be sure not to change to other clock modes or the low-power consumption mode until the completion of the switching. Completion of the switching can be checked by referencing the MCM and SCM bits of the CKSCR. If the mode is switched to another clock mode or lowpower-consumption mode before completion of switching, the mode may not be switched. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 175 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.8 Precautions when Using Low-power Consumption Mode MB90330A Series ■ Notes on Accessing the Low-Power Consumption Mode Control Register (LPMCR) to Enter the Standby Mode ● To access the low-power consumption mode control register (LPMCR) with assembler language • To set the low-power consumption mode control register (LPMCR) to enter the standby mode, use the instruction listed in Table 6.3-2. • The low-power consumption mode transition instruction in Table 6.3-2 must always be followed by an array of instructions highlighted by a line below. MOV LPMCR,#H'XX NOP NOP JMP $+3 MOV A,#H'10 ; the low-power consumption mode transition instruction in Table 6.3-2 ; jump to next instruction ; any instruction The devices does not guarantee its operation after returning from the low-power consumption mode if you place an array of instructions other than the one enclosed in the line. ● To access the low-power consumption mode (LPMCR) with C language To enter the standby mode using the low-power consumption mode control register (LPMCR), use one of the following methods (1) to (3) to access the register: (1) Specify the standby mode transition instruction as a function and insert two _wait_nop() built-in functions after that instruction. If any interrupt other than the interrupt to return from the standby mode can occur within the function, optimize the function during compilation to suppress the LINK and UNLINK instructions from occurring. Example: Watch mode or time-base timer mode transition function Void enter_watch(){ IO_LPMCR_byte = 0x10 /* Set LPMCR TMD bit to 0 */ _wait_nop(); _wait_nop(); } (2) Define the standby mode transition instruction using _asm statements and insert two NOP and JMP instructions after that instruction. Example: Transition to sleep mode _asm(" MOV I: _IO_LPMCR,#H'58"); /* Set LPMCR SLP bit to 1 */ _asm(" NOP"); _asm(" NOP"); _asm(" JMP $+3"); /* Jump to next instruction */ (3) Define the standby mode transition instruction between #pragma asm and #pragma endasm and insert two NOP and JMP instructions after that instruction. Example: Transition to stop mode #pragma asm MOV I: _IO_LPMCR,#H'98 NOP NOP JMP $+3 #pragma endasm 176 /* Set LPMCR STP bit to 1 */ /* Jump to next instruction */ FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 7 MODE SETTING This chapter describes the mode setting and the external memory access. 7.1 Mode Setting 7.2 Mode Pins (MD2 to MD0) 7.3 Mode Data 7.4 External Memory Access 7.5 Operation in Each Mode of Mode Setting CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 177 CHAPTER 7 MODE SETTING 7.1 Mode Setting 7.1 MB90330A Series Mode Setting F2MC-16LX has respective modes in the access method, access area, and test. Respective mode is set according to the mode pin at the time of reset and the modefetched mode data. ■ Mode Setting F2MC-16LX has respective modes in the access method, the access area, and the test, and Figure 7.1-1 shows the classification. Figure 7.1-1 Classification of Mode Operation mode Bus mode Single chip mode Internal ROM external bus mode External ROM external bus mode RUN operation Flash write mode Various test function mode Access mode External bus data bus length 8/16-bit Address data bus Non-multiplex mode Multiplex mode ■ Operating Mode The operation mode controls the operation state of the device and is specified by the mode setting pin (MDx) and the contents of the Mx bit in the mode data. Selecting the operation mode, you may perform the normal operation/the start of the internal test program/the start of the special test function. ■ Bus Modes The bus mode controls the internal ROM operation and the external access function operation, and is specified by the mode setting pin (MDx) and the contents of the Mx bit in the mode data. The mode setting pin (MDx) specifies the bus mode to read the reset vector and the mode data. The Mx bit in the mode data specifies the bus mode at the normal operation. ■ Access Mode The access mode controls the external data bus width and is specified by the mode setting pin (MDx) and the Sx bit in the mode data. Selecting the access mode specifies either the 8-bit length or the 16-bit length for the external data bus. Also, this mode specifies either the non-multiplex mode or the multiplex mode for the address data bus. 178 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 7 MODE SETTING 7.2 Mode Pins (MD2 to MD0) MB90330A Series 7.2 Mode Pins (MD2 to MD0) The mode pin is the three external pins (MD2 to MD0) and specifies the load methods for the reset vector and the mode data. ■ Setting of Mode Pins (MD2 to MD0) With the mode pin (MD2 to MD0), you may select either the external data bus or the internal data bus for the reset vector read and select the bus width while selecting the external data bus. For the internal Flash ROM products, the mode pin also specifies the Flash ROM write mode to write the internal ROM program and so forth. Table 7.2-1 shows the content of the mode pin setting. Table 7.2-1 Content of Setting of Mode Pins P61 P60 MD2 MD1 MD0 Mode Name Reset vectors access area External Data Bus width Remark - - 0 0 0 External vector mode 0 External Multiplex mode Reset vector bus width access - - 0 0 1 External vector mode 1 External Multiplex mode Reset vector bus width access - - 0 1 0 External vector mode 2 External Non-multiplex mode Reset vector bus width access - - 0 1 1 External vector mode Internal Mode Data Operation after reset sequence is controlled with mode data - - 1 0 0 - - 1 0 1 1 0 1 1 0 - - 1 1 1 Setting disabled Flash serial writing Flash writer write mode - - - Note: Set MD2 to MD0:0=VSS or 1=VCC. For the external vector mode 2, the data bus width also has the initial value of 8-bit. When setting 16-bit as the data bus width, specify the mode data for the nonmultiplex external data bus 16-bit mode, and then the LMBS areas are set to the 16-bit size access. To set the HMBS area for the 16-bit size access change the EPCR:HMBS bit setting. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 179 CHAPTER 7 MODE SETTING 7.3 Mode Data 7.3 MB90330A Series Mode Data The mode data is located on the memory of the FFFFDFH address and specifies the operation after the reset sequence. The mode data is automatically taken into the CPU by a mode fetch. ■ Mode Data While executing the reset sequence, the mode data in the FFFFDFH address is captured into the mode register in the CPU core. CPU sets the memory access mode by this mode data. The values of the mode register can be changed only in the reset sequence. The setting of the mode data is enabled after the reset sequence. Figure 7.3-1 shows the configuration of the mode data. Figure 7.3-1 Bit Configuration of Mode Data bit Mode data 7 6 M1 M0 5 0 Bus setting bit 4 S1 3 2 1 0 S0 0 0 0 Various mode Function extended bit setting bit (Reserved area) ■ Set Bit of Various Modes (S1, S0) The S1and S0 bits specify the bus mode and access mode after the reset sequence. Table 7.3-1 shows the content of the S1, S0 bit setting. Table 7.3-1 Content of S1 and S0 Bit Setting S1 S0 Functions 0 0 External data bus 8-bit mode 0 1 External data bus 16-bit mode 1 0 External data bus 8-bit mode 1 External data bus 16-bit mode Address data bus multiplex Address data bus non-multiplex 1 180 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 7 MODE SETTING 7.3 Mode Data MB90330A Series ■ Set Bit of Bus Mode (M1, M0) The M1and M0 bits specify the operation mode after the reset sequence. Table 7.3-2 shows the content of the M1, M0 bit setting. Table 7.3-2 Content of M1 and M0 Bit Setting M1 M0 Function 0 0 Single-chip mode 0 1 Internal ROM external bus modes 1 0 External ROM external bus modes 1 1 (Setting prohibited) ■ Relation between Access Area and Physical Address Figure 7.3-2 shows the relation between the access area and the physical address. Figure 7.3-2 Relation between Access Area and Physical Address Single chip Internal ROM external bus External ROM bus (with ROM mirrorring function) (with ROM mirrorring function) FFFFFFH ROM area ROM area Image of FF bank in ROM area Image of FF bank in ROM area Extended I/O area Extended I/O area RAM Register RAM Register Address#1 00FFFFH Address#2 007900H Extended I/O area Address#3 RAM Register 000100H 0000FBH Peripheral Peripheral Peripheral 000000H : Internal : External : No access Note: The "address #X" is determined by each family. Please refer to "Appendix A memory map" for details. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 181 CHAPTER 7 MODE SETTING 7.3 Mode Data MB90330A Series ■ Relation between Mode Pin and Mode Data (Recommended Example) Table 7.3-3 shows the relation between the mode pin and the mode data. Table 7.3-3 Relation between Mode Pin and Mode Data Mode MD2 MD1 MD0 M1 M0 S1 S0 Single Chip 0 1 1 0 0 X X Internal ROM external bus mode 8 bits (Address data multiplex) 0 1 1 0 1 0 0 Internal ROM external bus Mode 16 bits (Address data multiplex) 0 1 1 0 1 0 1 Internal ROM external bus Mode 8 bits (Address data non-multiplex) 0 1 1 0 1 1 0 Internal ROM external bus Mode 16 bits (Address data non-multiplex) 0 1 1 0 1 1 1 External ROM external bus mode 16 bits bus vector 16 bits width (Address data multiplex) 0 0 1 1 0 0 1 External ROM external bus mode 8 bits (Address data bus multiplex) 0 0 0 1 0 0 0 External ROM external bus mode 8 bits (Address data bus non-multiplex) 0 1 0 1 0 1 0 Note: The maximum accessible capacity is 64 Kbytes when you control the output of the upper addresses A23 to A16. 182 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 7 MODE SETTING 7.3 Mode Data MB90330A Series ■ Operation of External Pin in Each Mode Table 7.3-4 shows the operation relation of each external pin in the non-multiplex mode and the multiplex mode. Table 7.3-4 Operation Relation of External Pin in Each Mode Functions Non- multiplex mode Multiplex mode External Address control External Address control Permission (Address) Prohibit (port) External bus expansion External bus expansion 8 bits 16 bits P07 to P00/ D07 to D00/ AD07 to AD00 P17 to P10/ D15 to D08/ AD15 to AD08 8 bits 16 bits Permission (Address) External bus expansion External bus expansion 8 bits 16 bits D07 to D00 Port D15 to D08 Prohibit (port) 8 bits AD07 to AD00 Port D15 to D08 A15 to A08 P27 to P20 A23 to A16 Port P37 to P30 A07 to A00 A07 to A00 P47 to P40 A15 to A08 A15 to A08 AD15 to AD08 A15 to A08 A23 to A16 Port ALE ALE RD RD RD P52/WRL WRL WRL Port WRH Port WRH AD15 to AD08 Port ALE P53/WRH 16 bits Port WRH Port P54/HRQ HRQ HRQ P55/HAK HAK HAK P56/RDY RDY RDY P57/CLK CLK CLK WRH Notes: • The single chip mode is all available as the port. • The upper addresses, (WRL), (WRH), (HAK), HRQ, RDY, and CLK are used as a port according to the function selection. • While using the multiplex, you can use the upper addresses A23 to A20 as a port or PPG3 to PPG0. • While using the non-multiplex, you may not use the reload time ch.0/ch.1/ch.2, UART ch.0/ch.1. It works as an address. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 183 CHAPTER 7 MODE SETTING 7.4 External Memory Access 7.4 MB90330A Series External Memory Access The block diagram of the external memory access, the configuration/function of the register, and the operation of the external memory access are described. ■ I/O Signal Pin of External Memory Access F2MC-16LX provides the following address/data/control signal to access the external memory/peripheral. • CLK(P57): Machine cycle clock (KBP) is output. • RDY(P56): It is an external ready input pin. • (HAK)(P55): It is a hold acknowledge output pin. • HRQ(P54): It is a holding request input pin. • (WRH)(P53): It is a writing signal of a data bus upper byte. • (WRL)(P52): It is a data bus lower 8 bit write signal. • (RD)(P51): It is a reading signal. • ALE(P50): It is an address latch permission signal (enabled in the multiplex mode). ■ Block Diagram Figure 7.4-1 shows the block diagram of the external bus pin control circuit. Figure 7.4-1 Block Diagram of External Bus Pin Control Circuit P0 Internal address bus P1 P2 P3 P4 P5 P0 data P5 P0 P0 direction Internal data bus Data control Address control Access control 184 Access control FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 7 MODE SETTING 7.4 External Memory Access MB90330A Series ■ Register List Figure 7.4-2 shows the list of the registers of the external bus pin control circuit. Figure 7.4-2 List of the Registers of External Bus Pin Control Circuit bit 0000A5H 15 12 (W) (1) 7 6 E23 10 9 8 LMR1 LMR0 (W) (1) (-) (-) (-) (-) (W) (0) (W) (0) 5 4 3 2 1 0 E22 E21 E20 E19 E18 E17 E16 (W) (*) (W) (*) (W) (*) (W) (*) (W) (*) (W) (*) (W) (*) 15 14 13 12 CKE RYE HDE Reserved (W) (1) (W) (0) (W) (0) (W) (0) bit 11 HMR1 HMR0 (W) (0) (W) (*) 0000A7H 13 (W) (0) bit 0000A6H 14 Reserved Reserved 11 10 9 8 HMBS WRE LMBS (W) (*) (W) (1) (W) (0) (-) (-) Automatic Ready Function Selection Register (ARSR) Read/write Initial value External Address Output Control Register (HACR) Read/write Initial value Bus Control Signal Selection Register (EPCR) Read/write Initial value W: Write only CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 185 CHAPTER 7 MODE SETTING 7.4 External Memory Access 7.4.1 MB90330A Series Automatic Ready Function Selection Register (ARSR) The configuration and functions of the automatic ready function selection register (ARSR) are described. ■ Automatic Ready Function Selection Register (ARSR) Figure 7.4-3 shows the bit configuration of the automatic ready function selection register (ARSR). Figure 7.4-3 Bit Configuration of automatic Ready Function Selection Register (ARSR) 15 bit 0000A5H 14 Reserved Reserved (W) (0) 13 12 11 10 (W) (0) (W) (1) (W) (1) 9 8 LMR1 LMR0 HMR1 HMR0 (-) (-) (-) (-) (W) (0) (W) (0) Automatic Ready Function Selection Register (ARSR) Read/write Initial value W: Write only Function of each bit for the automatic ready function selection register (ARSR) shows as follows. [bit 15, bit 14] Reserved It is Reserved bit. Please write "00B". [bit 13, bit 12] HMR1, HMR0 The automatic wait function is selected when executing the external access to the area 800000H to FFFFFFH. A set content is a table below. HMR1 HMR0 Setting 0 0 Automatic wait interdiction 0 1 At the external access, an automatic wait of 1 machine cycle 1 0 At the external access, an automatic wait of 2 machine cycle 1 1 At the external access, an automatic wait of 3 machine cycles [Initial value] [bit 11, bit 10] Undefined bit Nothing is affected when it is written. [bit 9, bit 8] LMR1, LMR0 The automatic wait function is selected when executing the external access to the area 007100H to 7FFFFFH (however, the extended I/O area 007900H to 007FFFH is disable). A set content is a table below. 186 LMR1 LMR0 Setting 0 0 Automatic wait interdiction [Initial value] 0 1 At the external access, an automatic wait of 1 machine cycle 1 0 At the external access, an automatic wait of 2 machine cycle 1 1 At the external access, an automatic wait of 3 machine cycle FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 7 MODE SETTING 7.4 External Memory Access MB90330A Series 7.4.2 External Address Output Control Register (HACR) The configuration and functions of the external address output control register are described. ■ External Address Output Control Register (HACR) Figure 7.4-4 shows the bit configuration of the external address output control register. Figure 7.4-4 Bit Configuration of External Address Output Control Register (HACR) 7 6 5 4 3 2 1 0 E23 E22 E21 E20 E19 E18 E17 E16 (W) (*) (W) (*) (W) (*) (W) (*) (W) (*) (W) (*) bit 0000A6H (W) (*) (W) (*) External Address Output Control Register (HACR) Read/write Initial value W: Write only The external address output control register controls the output of the address (A23 to A16) to the outside. Each bit corresponds to the addresses A23 to A16 respectively, and controls each address output pin as shown in the following table. 0 The corresponding pin is address output (AXX). [Initial value] 1 The corresponding pin is I/O port (PXX). The HACR register is not accessible when the device is in the single chip mode. In that case, all the ports function as the I/O ports regardless of the value of the HACR register. All the bits of the HACR register are write-only and the read-out value is "1". Furthermore, when expecting an output of an address by selecting the address output, be sure to use DDR with "0". The initial value is "1" only when starting in the internal vector mode. Otherwise, it is "0". Note: When using PPG, be sure to set to "1" (I/O port setting). CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 187 CHAPTER 7 MODE SETTING 7.4 External Memory Access 7.4.3 MB90330A Series Bus Control Signal Selection Register (EPCR) The configuration and functions of the bus control signal selection register are described. ■ Bus Control Signal Selection Register (EPCR) The bus control signal selection register sets the control functions of the bus operation in the external bus mode. Figure 7.4-5 shows the bit configuration of the bus control signal selection register. Figure 7.4-5 Bit Configuration of Bus Control Signal Selection Register (EPCR) 15 14 13 12 CKE RYE HDE Reserved (W) (1) (W) (0) (W) (0) (W) (0) bit 0000A7H 11 10 9 8 HMBS WRE LMBS (W) (*) (W) (1) (W) (0) (-) (-) Bus Control Signal Selection Register (EPCR) Read/write Initial value W: Write only The EPCR register is not accessible when the device is in the single chip mode. In the single chip mode, all pins function as the I/O ports regardless of the register value. All the bits of the EPCR register are writeonly and the read-out value is "1". The functions of each bit of the bus control signal selection register are described below. [bit 15] CKE The output of external clock (CLK) is controlled. 0 I/O port (P57) operation (clock interdiction) 1 Clock signal (CLK) output permission [Initial value] [bit 14] RYE The input of external ready (RDY) is controlled. 0 I/O port (P56) operation (external RDY input prohibited) [Initial value] 1 External ready (RDY) input permission [bit 13] HDE This is the bit that specifies the I/O permission of hold related pin. The setting controls the hold request input (HRQ) and the hold acknowledge output (HAK). 0 I/O port (P55, P54) operation (hold function input/output prohibited) [Initial value] 1 Hold Request (HRQ) Input/Hold acknowledge (HAK) output permission [bit 12] Reserved Reserved bit. Please write "0". 188 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 7 MODE SETTING 7.4 External Memory Access MB90330A Series [bit 11] HMBS Specify the bus size when accessing the external bus to the area 800000H to FFFFFFH in the external data bus 16-bit mode. 0 Bus size access of 16 bits (Initial Value in the external vector mode 1) 1 Bus size access of 8 bits (Initial Value in the external vector mode 0.2) [bit 10] WRE Control the output of the external write signal (WRH/WRL) pins in the external data bus 16-bit mode, and (WRL) pin in the external data bus 8-bit mode). 0 I/O Port (P53, P52) operation (Write signal output permission) 1 Write strobe signal (WRH/WRL or WRL only) output permission. [Initial value] [bit 9] LMBS Specify the bus size when accessing the external bus to the area 007100H to 7FFFFFH (however, the extended I/O area 007900H to 007FFFH is disable) in the external data bus 16-bit mode. 0 16-bit bus size access [Initial value] 1 8-bit bus size access Note: In the external data bus 16-bit mode, when you permit the WRH/WRL) function by the WRE bit, be sure to place P53/P52 in the input mode (set the bit 3 and 2 of DDR5 to "0"). In addition, the I/O function of the port is enabled even when the RDY and HRQ inputs by RYE and HDE bits are permitted. Therefore, be sure to set to "0" (input mode) for the bit corresponding to the port in DDR5. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 189 CHAPTER 7 MODE SETTING 7.5 Operation in Each Mode of Mode Setting 7.5 MB90330A Series Operation in Each Mode of Mode Setting Operation in each mode of mode setting is described in the timing chart. ■ Mode Type Operations of the following items are described for each function. • External memory access control signal - External data bus 8-bit mode (non-multiplex mode) - External data bus 8-bit mode (multiplex mode) - External data bus 16-bit mode (non-multiplex mode) - External data bus 16-bit mode (multiplex mode) • Ready Function - Non-multiplex mode - Multiplex mode • Holding function - Non-multiplex mode - Multiplex mode 190 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 7 MODE SETTING 7.5 Operation in Each Mode of Mode Setting MB90330A Series 7.5.1 External Memory Access Control Signal The access to the external memory is performed at 3 cycles unless the ready function is not used. ■ External Memory Access Control Signal Figure 7.5-1 to Figure 7.5-4 show the timing charts of the external access in each mode. The 8-bit bus width access in the external data bus 16-bit mode reads or writes the 8-bit width peripheral chip when you connect to the external bus by mixing the 8-bit width peripheral chip and the 16-bit width peripheral chip. Be sure to connect the 8-bit width peripheral chip to the lower 8-bit of data because the 8-bit bus width access is executed by the lower 8-bit of the data bus. Whether performing the 16-bit bus width access or the 8-bit bus width access in the external data bus 16-bit mode is determined by the specification of the HMBS/ LMBS bit of EPCR. Furthermore, in the multiplex mode, any actual bus operation may not be performed by executing only the address output and the assert output of ALE and not asserting RD/WRL/WRH. Note: Be sure not to execute the access to the peripheral chip only by using the ALE signal. ● External data bus 8-bit mode (non-multiplex mode) Figure 7.5-1 Timing Chart of External Memory Access (External Data Bus 8-bit/non-multiplex Mode) Read Write Read P57/CLK P53/WRH (Port data) P52/WRL P51/RD P50/ALE A23 to A16 Read address A15 to A08 Read address Write address Read address Read address Write address Read address A07 to A00 D15 to D08/ AD15 to AD08 D07 to D00/ AD07 to AD00 CM44-10129-6E Write address Read address (Port data) Read data Write data FUJITSU MICROELECTRONICS LIMITED 191 CHAPTER 7 MODE SETTING 7.5 Operation in Each Mode of Mode Setting MB90330A Series ● External Data Bus 8-Bit Mode (External Data Bus 8-Bit/Multiplex Mode) Figure 7.5-2 Timing Chart of External Memory Access (Multiple Mode) Read Write Read P57/CLK P53/WRH (Port data) P52/WRL P51/RD P50/ALE A23 to A16 Read address A15 to A08 (Port data) A07 to A00 (Port data) D15 to D08/ AD15 to AD08 D07 to D00/ AD07 to AD00 Read address Write address Read address Write address Read address Write address Read address Read data Read address Write data ● External Data Bus 16-bit Mode (External Data Bus 16-bit/Non-Multiplex Mode) Figure 7.5-3 Timing Chart of External Memory Access (External Data Bus 16-bit/non-multiplex Mode) Even address word read Odd address word write P57/CLK P53/WRH P52/WRL P51/RD P50/ALE A23 to A16 Read address Write address Read address A15 to A08 Read address Write address Read address A07 to A00 Read address Write address Read address D15 to D08/ AD15 to AD08 D07 to D00/ AD07 to AD00 Read data 192 Write data FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 7 MODE SETTING 7.5 Operation in Each Mode of Mode Setting MB90330A Series ■ External 16-bit Bus Mode (External Data Bus 16-bit/Multiplex Mode) Figure 7.5-4 Timing Chart of External Memory Access (External Data Bus 16-bit/multiplex Mode) Read Write Read P57/CLK P53/WRH P52/WRL P51/RD P50/ALE A23 to A16 Read address A15 to A08 (Port data) A07 to A00 (Port data) D15 to D08/ AD15 to AD08 D07 to D00/ AD07 to AD00 Write address Read address Read address Write address Read data CM44-10129-6E Read address Write address Read address Read address Write data FUJITSU MICROELECTRONICS LIMITED 193 CHAPTER 7 MODE SETTING 7.5 Operation in Each Mode of Mode Setting 7.5.2 MB90330A Series Ready Function The setting of the P56/RDY pin or the automatic ready function selection register (ARSR) enables the access to the low-speed memory and the peripheral circuits. When the RYE bit in the bus control signal selection register (EPCR) is set to "1", the condition is in the wait cycle while the period "L" level is being input to the P56/RDY pin at the time of accessing to the external area, and then it is possible to extend the access cycle. ■ Ready Function The F2MC-16LX has two built-in auto-ready functions for the external memory. The auto-ready function inserts the wait cycle of 1 to 3 cycles without the external circuit and extends the access cycle, when an access to the lower address external area located between the addresses 007100H to 7FFFFFH (however, the extend I/O area 007900H to 007FFFH is disable) is generated, and when an access to the upper address external area located between the addresses 800000H to FFFFFFH is generated. The auto-ready function is activated by the setting of the LMR1/LMR0 bit (lower address external area) in the ARSR and the HMR1/ HMR0 bit (upper address external area) in the ARSR. In the auto-ready functions for the external memory or the external I/O, when the RYE bit in the EPCR is set to "1", the wait cycle is maintained if the "L" level is input into the P56/RDY pin after the wait cycle ends by the above auto-ready function. The timing charts of the ready functions in the non-multiplex mode and the multiplex mode are illustrated below. In both modes, the above chart does not set the ready function; the following chart sets this function. Note: When inputting from the RDY pin, note that the device may run away if the AC standard is not satisfied. 194 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 7 MODE SETTING 7.5 Operation in Each Mode of Mode Setting MB90330A Series ● Non-multiplex mode Figure 7.5-5 Timing Chart of Ready Function (Non-multiplex Mode) Even address word read Odd address word write P57/CLK P53/WRH P52/WRL P51/RD P50/ALE A23 to A16 Read address Write address A15 to A08 Read address Write address A07 to A00 Read address Write address D15 to D08/ AD15 to AD08 D07 to D00/ AD07 to AD00 P56/RDY Read data RDY pin fetching Even address word read Write data Odd address word write P57/CLK P53/WRH P52/WRL P51/RD P50/ALE A23 to A16 Read address Write address A15 to A08 Read address Write address A07 to A00 Read address Write address D15 to D08/ AD15 to AD08 D07 to D00/ AD07 to AD00 Write data CM44-10129-6E Cycle lengthened by auto ready FUJITSU MICROELECTRONICS LIMITED 195 CHAPTER 7 MODE SETTING 7.5 Operation in Each Mode of Mode Setting MB90330A Series ● Multiplex mode Figure 7.5-6 Timing Chart of Ready Function (Multiplex Mode) Even address word read Odd address word write P57/CLK P53/WRH P52/WRL P51/RD P50/ALE A23 to A16 Write address Read address A15 to A08 (Port data) A07 to A00 (Port data) D15 to D08/ AD15 to AD08 Read address Write address D07 to D00/ AD07 to AD00 Read address Write address P56/RDY RDY pin fetching Read data Even address word read Write data Odd address word write P57/CLK P53/WRH P52/WRL P51/RD P50/ALE A23 to A16 A15 to A08 (Port data) A07 to A00 (Port data) D15 to D08/ AD15 to AD08 Write address Read address D07 to D00/ AD07 to AD00 Write address Read address Write data 196 Write address Read address Cycle length end by auto ready FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 7 MODE SETTING 7.5 Operation in Each Mode of Mode Setting MB90330A Series 7.5.3 Holding Function The operation of the hold function is described in the timing chart. ■ Operation of Holding Function If the HDE bit in the EPCR is set to "1", the hold function of the external bus by both the P54/HRQ and the P55/HAK pins are enabled. When the "H" level is input to the P54/HRQ pin, the pin enters in the hold state when CPU's instruction ends (for the string instruction, when 1 element data procedure ends), and outputs the "L" level from the P55/HAK and the following pin enters into the high-impedance state. ● Non-multiplex mode • Address output: A23 to A00 • Data I/O: D15/AD15 to D00/AD00 • Bus control signal: P51/RD,P52/WRL,P53/WRH ● Multiplex mode • Address output: A23 to A16 • Data I/O: D15/AD15 to D00/AD00 • Bus control signal: P51/RD,P52/WRL,P53/WRH Thus, the device external circuit enables the use of the external bus. If the "L" level is input to the P54/ HRQ pin, the p55/HAK pin becomes the "H" level output and the external pin state is restored, and then the CPU restarts the operation. In the state of STOP, the holding demand is not accepted. ■ Non-multiplex Mode Figure 7.5-7 shows the timing chart of the hold function of the non-multiplex mode in the external data bus 16-bit mode. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 197 CHAPTER 7 MODE SETTING 7.5 Operation in Each Mode of Mode Setting MB90330A Series Figure 7.5-7 Timing Chart of Holding Function (Non-multiplex Mode) Read cycle Hold cycle Write cycle P57/CLK P54/HRQ P55/HAK P53/WRH P52/WRL P51/RD P50/ALE A23 to A16 (Address) (Address) A15 to A08 (Address) (Address) A07 to A00 (Address) (Address) D15 to D08/ AD15 to AD08 D07 to D00/ AD07 to AD00 Read data Write data ■ Multiple Mode Figure 7.5-8 shows the timing chart of the hold function of the multiplex mode in the external data bus 16bit mode. Figure 7.5-8 Timing Chart of Holding Function (Multiplex Mode) Read cycle Hold cycle Write cycle P57/CLK P54/HRQ P55/HAK P53/WRH P52/WRL P51/RD P50/ALE A23 to A16 (Address) A15 to A08 (Port data) A07 to A00 (Port data) (Address) D15 to D08/ AD15 to AD08 (Address) D07 to D00/ AD07 to AD00 (Address) Read data Write data Note: When "H" level is inputted to the P54/HRQ pin, it is retained until P55 pin becomes "L" level. 198 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 8 I/O PORT This chapter describes the configuration and functions of the register used in the I/O port. 8.1 Functions of I/O Ports 8.2 I/O Port Register CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 199 CHAPTER 8 I/O PORT 8.1 Functions of I/O Ports 8.1 MB90330A Series Functions of I/O Ports The overview of functions of the I/O ports is shown. ■ Functions of I/O Ports The I/O port outputs data from the CPU to the I/O pin and loads the signal input in the I/O pin in the CPU by using the port data register (PDR). In addition, the port can randomly set the direction of the input/ output of the I/O pin in bit unit by the port direction register (DDR). The MB90330A Series has 72 input/output pins and 22 open drain output pins. P07 to P00, 17 to P10, P27 to P20, P37 to P30, P47 to P40, P57 to P50, P77 to P70, P87 to P80, P95 to P90, PB6, and PB5 are I/O ports; P67 to P60, P96, and PA7 to PA0, PB4 to PB0 are open drain pins. 200 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 8 I/O PORT 8.2 I/O Port Register MB90330A Series 8.2 I/O Port Register The configuration and functions of the register used in the I/O port are described. ■ I/O Port Registers There are the following registers in I/O port. • Port data register (PDR0 to PDRB) • Port direction register (DDR0 to DDRB) • Input resistance register (RDR0,RDR1) • Output terminal register (ODR4) • Analog input enable register (ADER0,ADER1) CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 201 CHAPTER 8 I/O PORT 8.2 I/O Port Register 8.2.1 MB90330A Series Port Data Register (PDR0 to PDRB) The configuration and functions of the port data register (PDR0 to PDRB) are described. ■ Port Data Register (PDR0 to PDRB) Figure 8.2-1 shows the list of the port data register (PDR0 to PDRB). Figure 8.2-1 List of Port Data Register (PDR0 to PDRB) PDR0 bit Address : 000000H PDR1 bit Address : 000001H 7 P07 15 P17 7 P27 15 P37 7 P47 15 P57 7 P67 15 P77 7 P87 15 bit PDR2 Address : 000002H bit PDR3 Address : 000003H bit PDR4 Address : 000004H bit PDR5 Address : 000005H bit PDR6 Address : 000006H bit PDR7 Address : 000007H bit PDR8 Address : 000008H bit PDR9 Address : 000009H bit 7 PDRA Address : 00000AH PA7 bit 7 PDRB Address : 00000CH 6 5 4 3 2 1 0 P06 P05 P04 P03 P02 P01 P00 14 13 12 11 10 9 8 P16 P15 P14 P13 P12 P11 P10 6 5 4 3 2 1 0 P26 P25 P24 P23 P22 P21 P20 14 13 12 11 10 9 8 P36 P35 P34 P33 P32 P31 P30 6 5 4 3 2 1 0 P46 P45 P44 P43 P42 P41 P40 14 13 12 11 10 9 8 P56 P55 P54 P53 P52 P51 P50 6 5 4 3 2 1 0 P66 P65 P64 P63 P62 P61 P60 14 13 12 11 10 9 8 P76 P75 P74 P73 P72 P71 P70 6 5 4 3 2 1 0 P86 P85 P84 P83 P82 P81 P80 14 13 12 11 10 9 8 P96 P95 P94 P93 P92 P91 P90 6 5 4 3 2 1 0 PA6 PA5 PA4 PA3 PA2 PA1 PA0 6 5 4 3 2 1 0 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Initial value XXXXXXXXB Access XXXXXXXXB R/W * XXXXXXXXB R/W * XXXXXXXXB R/W * XXXXXXXXB R/W * XXXXXXXXB R/W * XXXXXXXXB R/W * XXXXXXXXB R/W * XXXXXXXXB R/W * -XXXXXXXB R/W * XXXXXXXXB R/W * -XXXXXXXB R/W * R/W * *: The R/W access to the input/output port operates slightly different from the R/W access to the memory. Please note that the following operations are done. • Input mode - When reading: Read the level of the corresponding pin. - When writing: Write into the latch for the input/output. • Output mode - When reading: Read the value of the data register latch. - When writing: Output into the corresponding pin. 202 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 8 I/O PORT 8.2 I/O Port Register MB90330A Series 8.2.2 Port Direction Register (DDR0 to DDRB) The configuration and functions of the port direction register are described. ■ Port Direction Register (DDR0 to DDRB) Figure 8.2-2 shows the list of the port direction register (DDR0 to DDRB). Figure 8.2-2 List of Port Direction Register (DDR0 to DDRB) 6 D06 bit 14 DDR1 Address : 000011H D16 bit 6 DDR2 Address : 000012H D26 bit 14 DDR3 Address : 000013H D36 bit 6 DDR4 Address : 000014H D46 bit 14 DDR5 Address : 000015H D56 6 bit DDR6 Address : 000016H D66 bit 14 DDR7 Address : 000017H D76 6 bit DDR8 Address : 000018H D86 bit 14 DDR9 Address : 000019H D96 6 bit 7 DDRA Address : 00001AH DA7 DA6 bit 15 14 DDRB Address : 00000DH DB6 DDR0 bit Address : 000010H 7 D07 15 D17 7 D27 15 D37 7 D47 15 D57 7 D67 15 D77 7 D87 15 5 D05 13 D15 5 D25 13 D35 5 D45 13 D55 5 D65 13 D75 5 D85 13 D95 5 DA5 13 DB5 4 D04 12 D14 4 D24 12 D34 4 D44 12 D54 4 D64 12 D74 4 D84 12 D94 4 DA4 12 DB4 3 D03 11 D13 3 D23 11 D33 3 D43 11 D53 3 D63 11 D73 3 D83 11 D93 3 DA3 11 DB3 2 D02 10 D12 2 D22 10 D32 2 D42 10 D52 2 D62 10 D72 2 D82 10 D92 2 DA2 10 DB2 1 D01 9 D11 1 D21 9 D31 1 D41 9 D51 1 D61 9 D71 1 D81 9 D91 1 DA1 9 DB1 0 D00 8 D10 0 D20 8 D30 0 D40 8 D50 0 D60 8 D70 0 D80 8 D90 0 DA0 8 DB0 Initial value 00000000B Access 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W -0000000B R/W 00000000B R/W -0000000B R/W R/W ● When each terminal functions as a port When each terminal functions as a port, controls the corresponding each terminal as follows. • 0: Input mode. • 1: Output mode Reset sets to "0". Note: When accessing the DDR0 to DDRB registers by using the instruction of the read modify write system (instructions such as bit set) is made, the bit targeted by an instruction becomes the defined value, while the content of the output register set with the other bit changes to the input value to the pin. Therefore, be sure to write an expected value into PDR firstly, and then set DDR, and finally change to the output when changing the input pin to the output pin is made. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 203 CHAPTER 8 I/O PORT 8.2 I/O Port Register 8.2.3 MB90330A Series Other Registers The configuration and functions of the register other than the port data register (PDR0 to PDRB) and the port direction register (DDR0 to DDRB) are described. ■ Port 0, 1 Pull-up Resistance Register (RDR0, RDR1) Figure 8.2-3 shows the bit configuration of the pull-up resistance register (RDR0, RDR1). Figure 8.2-3 Bit Configuration of Pull-up Resistance Register (RDR0,RDR1) RDR0 bit 7 6 5 4 3 2 1 0 Address : 00001CH RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 RDR1 bit 15 14 13 12 11 10 9 Initial value 00000000B Access 00000000B R/W R/W 8 Address : 00001DH RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10 The pull-up resistance register (RDR0, RDR1) determines whether the pull-up resistor is enabled or not in the input mode. • 0: There is not a pull-up resistor none at input mode • 1: There is a pull-up resistor at the input mode. The RDR0 and RDR1 registers do not have any function in the output mode (no pull-up resistor). The input/output register is decided by the setting of the direction register (DDR). There is no pull-up resistor at the time of stop (SPL=1) (high impedance). This function is disable for the external bus. Be sure not to write into the RDR0 and RDR1 registers. ■ Port 4 Output Terminal Register (ODR4) Figure 8.2-4 shows the bit configuration of the output pin register (ODR4). Figure 8.2-4 Bit Configuration of Output Terminal Register (ODR4) ODR4 bit 15 14 13 12 11 10 9 8 Address : 00001BH OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 Initial value 00000000B Access R/W The output terminal register (ODR4) executes open drain control in the output mode. • 0: Entering in the standard output port in the output mode • 1: Entering in the open drain output port in the output mode The output terminal register (ODR4) does not have it function in the input mode (Output of Hi-Z). The input/output mode is decided by the setting of the direction register (DDR). This function is disable for the external bus. Do not write to the output terminal register (ODR4). 204 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 8 I/O PORT 8.2 I/O Port Register MB90330A Series ■ Analog Input Enable Register (ADER0, ADER1) Figure 8.2-5 shows the bit configuration of the analog input permission registers (ADER0, ADER1). Figure 8.2-5 Bit Configuration of analog Input Enable Register (ADER0, ADER1) ADER0 bit 7 6 5 4 3 2 1 0 Address : 00001EH ADE07 ADE06 ADE05 ADE04 ADE03 ADE02 ADE01 ADE00 bit Address : 00001FH ADER1 15 14 13 12 11 10 9 Initial value 11111111B Access 11111111B R/W R/W 8 ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE09 ADE08 The analog input enable registers (ADER0, ADER1) control each pin of port 7, 8 as follows; • 0: Entering in the port I/O mode • 1: Entering in the analog input mode. This bit becomes 0 after a reset. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 205 CHAPTER 8 I/O PORT 8.2 I/O Port Register 206 MB90330A Series FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 9 TIME-BASE TIMER This chapter describes the function and operation of the time-base timer. 9.1 Overview of Time-base Timer 9.2 Configuration of Time-base Timer 9.3 Time-base Timer Control Register (TBTC) 9.4 Interrupt of Time-base Timer 9.5 Operations of Time-base Timer 9.6 Precautions when Using Time-base Timer 9.7 Program Example of Time-base Timer CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 207 CHAPTER 9 TIME-BASE TIMER 9.1 Overview of Time-base Timer 9.1 MB90330A Series Overview of Time-base Timer The time-base timer has an interval timer function that enables a selection of four interval times using 18-bit free-run counter (time-base counter) count-up with synchronizing to the internal count clock (2 division of original oscillation). Furthermore, the function of timer output of oscillation stabilization wait time or function supplying operation clocks for watchdog timer are provided. ■ Interval Timer Function The interval timer function generates interrupt requests at regular intervals. • An overflow of the bit for the interval timer in the time-base counter generates an interrupt request. • You can select one of four bits (interval time) for the interval timer. Table 9.1-1 shows the interval time of the time-base timer. Table 9.1-1 Interval Time of Time-base Timer Internal count clock cycle Time of interval 212/HCLK (Approx. 0.68 ms) 2/HCLK(0.33 μs) 214/HCLK (Approx. 2.7 ms) 216/HCLK (Approx. 10.9 ms) 219/HCLK (Approx. 87.4 ms) HCLK: Oscillation clock The value in parentheses is applicable when the oscillation clock operates at 6 MHz. 208 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 9 TIME-BASE TIMER 9.1 Overview of Time-base Timer MB90330A Series ■ Function of Clock Supply The clock supply function supplies the operating clock to the timer for oscillation stabilization wait time and some peripheral functions. Table 9.1-2 shows the clock cycle supplied from the time-base timer to each peripheral. Table 9.1-2 Clock Cycles Supplied from Time-base Timer Where to Supply Clock Clock Cycle 213/HCLK (Approx. 1.4 ms) Oscillation Stabilization Wait Time Remark Oscillation Stabilization Wait Time for ceramic oscillator 215/HCLK (Approx. 5.5 ms) Oscillation Stabilization Wait Time for crystal oscillator 217/HCLK (Approx. 21.8 ms) 212/HCLK (Approx. 0.68 ms) 214/HCLK (Approx. 2.7 ms) Watchdog timer Watchdog timer count up clock 216/HCLK (Approx. 10.9 ms) 219/HCLK (Approx. 87.4 ms) HCLK: Oscillation clock The value in parentheses is applicable when the oscillation clock operates at 6 MHz. Reference: Because oscillation cycles is unstabled after oscillation starts, the oscillation stabilization wait time is listed for reference. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 209 CHAPTER 9 TIME-BASE TIMER 9.2 Configuration of Time-base Timer 9.2 MB90330A Series Configuration of Time-base Timer The time-base timer consists of the following four blocks. • Time-base timer counter • Counter clear circuit • Interval timer selector • Time-base timer control register (TBTC) ■ Block Diagram of Time-base Timer Figure 9.2-1 shows the block diagram of the time-base timer. Figure 9.2-1 Block Diagram of Time-base Timer to Watchdog timer to PPG timer Time-base timer counter 2 division of HCLK × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 × 2 1 × 2 2 × 23 OF OF Power-on reset Stop mode start CKSCR : MCS = 1 CKSCR : SCS = 0 Counter clear circuit 0 *1 1 *2 OF OF to Oscillation stabilization wait time selector in Clock control unit Interval timer selector TBOF set TBOF clear Time-base timer control register(TBTC) Reserved TBIE TBOF TBR TBC1 TBC0 Time-base timer interrupt signal OF HCLK *1 *2 Undefined Overflow Oscillation clock Switch Machine clock to PLL clock from Main clock or Sub clock Switch Machine clock to PLL clock from Sub clock ● Time-base timer counter This is an 18-bit up-counter whose count clock is two-division clock of oscillation clock (HCLK). 210 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 9 TIME-BASE TIMER 9.2 Configuration of Time-base Timer MB90330A Series ● Counter clear circuit This circuit clears the counter by writing "0" to time-base timer initialization bit (TBR) of time-base timer control register (TBTC), power-on reset, transition to the stop mode, switching to PLL clock mode from the main clock mode or sub clock, or switching to the main clock mode from sub clock. ● Interval timer selector This selects the output of the time-base timer counter from one of four types. The overflow of selected bit will be the interrupt cause. ● Time-base timer control register (TBTC) Interval time selection, counter clearance, and interrupt request control and status check are executed. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 211 CHAPTER 9 TIME-BASE TIMER 9.3 Time-base Timer Control Register (TBTC) 9.3 MB90330A Series Time-base Timer Control Register (TBTC) The time-base timer control register (TBTC) executes interval time selection, time-base timer counter clearance, and interrupt control and status check. ■ Time-base Timer Control Register (TBTC) Figure 9.3-1 Time-base Timer Control Register (TBTC) Address 0000A9H bit15 bit14 bit13 bit12 bit11 bit10 bit8 bit7 bit9 R/W R/W R/W R/W W 0 Initial value 1--00100B R/W TBC1 TBC0 0 0 bit0 (WDTC) TBIE TBOF TBR TBC1 TBC0 Reserved 0 0 Interval time selection bit 212/HCLK (Approx. 0.68 ms) 214/HCLK (Approx. 2.7 ms) 216/HCLK (Approx. 10.9 ms) 0 219/HCLK (Approx. 87.4 ms) 1 1 The value in parentheses is applicable when the oscillation clock operates at 6 MHz. Time-base timer initialization bit TBR Read Write Clear Time-base timer counter, TBOF bit. 0 1 Always "1" is read. No change, no others are affected Interrupt request flag bit TBOF Read Write 0 No overflow of specification bit Clear this bit. 1 Overflow of specification bit No change, no others are affected TBIE Interrupt request enable bit 0 Interrupt request output disabled 1 Interrupt request output enables Reseved Reseved bit Always write this bit to "1". R/W W HCLK 212 : Readable/Writable : Write only : Undefined : Oscillation clock : Initial value FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 9 TIME-BASE TIMER 9.3 Time-base Timer Control Register (TBTC) MB90330A Series Table 9.3-1 Time-base Timer Control Register (TBTC) Bit name Functions bit 15 Reserved: Reserved bit Note: Be sure to write "1". bit 14, bit 13 Unused bits • The value at the time of reading is irregular. • No effect on writing. bit 12 TBIE: Interrupt request enable bit • This bit permits or prohibits an interrupt request output to the CPU. • If the TBIE bit and interrupt request flag bit (TBOF) is set to "1", an interrupt request is output. bit 11 TBOF: Interrupt request flag bit • An overflow of time-base timer counter specification bit sets the status to "1". • If the TBOF bit and interrupt request permission bit (TBIE) is set to "1", an interrupt request is output. Setting to "0" executes clearance during writing and no changes are made at "1", making no influences on others. Note: • When clearing the TBOF bit, set to the condition that prohibits time-base timer interrupt with the interrupt request permission bit (TBIE) or by specifying interrupt level mask register (ILM) in processor status (PS). • The status is cleared to "0" by "0" writing, transition to the stop mode, transition from the sub clock mode to main clock mode, transition from the main clock mode to the PLL clock mode, "0" writing to time-base timer initialization bit (TBR), or resetting. bit 10 TBR: Time-base timer initialization bit • This bit clears the time-base timer counter. • Writing "0" clears the counter, immediately after that, clears the TBOF bit. No changes are made at "1", making no influences on others. Reference: Always read value is "1". bit 9, bit 8 TBC1, TBC0: Interval time select bits • These bits specify a cycle for the interval timer. • The bit for the interval timer of time-base timer counter is specified. • One of four interval time can be selected. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 213 CHAPTER 9 TIME-BASE TIMER 9.4 Interrupt of Time-base Timer 9.4 MB90330A Series Interrupt of Time-base Timer The time-base timer can generate an interrupt request by the overflow of the specified bit of the time-base timer counter (interval timer function). ■ Interrupt of Time-base Timer After the time-base counter undergoes count-up with the internal count clock and the bit for the selected interval timer overflows, the interrupt request flag bit (TBOF) of time-base timer control register (TBTC) is set to "1". In this case, an interrupt request to CPU is generated if interrupt request is permitted by setting the interrupt request permission bit (TBIE) is set to "1". Clear the interrupt request by writing "0" to the TBOF bit in the interrupt processing routine. The TBOF bit is set when the specified bit overflows regardless of the value of interrupt request permission bit (TBIE). Note: When clearing the interrupt request flag bit (TBOF) in the time-base timer control register (TBTC), perform while the time-base timer interrupt is prohibited by the setting of the interrupt level mask register (IML) of the interrupt request permission bit (TBIE) or the processor status (PS). References: • When the TBOF bit is "1", an interrupt request is immediately generated upon the transition of the TBIE bit from prohibition to permission ("0" to "1"). • EI2OS and μDMAC cannot be used. ■ Interrupt of Time-base Timer and EI2OS, μDMAC Table 9.4-1 shows the time-base timer interrupt and EI2OS, μDMAC. Table 9.4-1 Interrupt of Time-base Timer and EI2OS, μDMAC Interrupt number Interrupt level setting register Address in Vector Table Register Name Address Low High Bank ICR14 0000BEH FFFF5CH FFFF5DH FFFF5EH #40 EI2OS μDMAC : Not available Note: ICR14 can be used for three interrupts, time-base timer interrupt, watch timer interrupt, and UART reception end ch.0/1 interrupt, but the interrupt level is the same. 214 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 9 TIME-BASE TIMER 9.5 Operations of Time-base Timer MB90330A Series 9.5 Operations of Time-base Timer The time-base timer has functions of interval timer and clock supply to peripheral functions. ■ Operation of Interval Timer Function (Time-base Timer) Interval timer function generates interrupt requests at regular intervals. In order to function as an interval timer, setup in Figure 9.5-1 is needed. Figure 9.5-1 Setting of Time-base Timer bit15 Address 0000A9H TBTC Reserved 1 bit14 bit13 bit12 TBIE bit11 bit10 TBOF TBR 0 bit9 bit8 TBC1 TBC0 bit7 bit0 (WDTC) 0 : Used bit : Unused bit 0 : Set to "0". 1 : Set to "1". • The time-base timer counter continues count-up synchronizing to the internal count clock (two division of oscillation clock) as long as the clock oscillate. • Count-up from "0" is made when the counter is cleared; the interrupt request flag bit (TBOF) is set to "1" when the bit for the interval timer overflows. In this case, interrupts are generated at selected intervals based on the cleared if the interrupt request output is permitted (TBIE = 1). • The interval time may be longer than the set period by the clearance operation of the time-base timer. ■ Oscillation Stabilization Wait Time Function The time-base timer can also be used for the oscillation clock or timer for PLL clock oscillation stabilization wait time. The oscillation stabilization wait time is the duration elapsed by counting up from "0" (count clear) to the moment at which the bit for oscillation stabilization wait time overflows. When the mode recovers from the time-base timer mode to the PLL clock mode or main clock mode, the oscillation stabilization wait time is the duration from the middle of counting because the time-base timer counter has not cleared. Table 9.5-1 shows the clearance operation of the time-base timer counter and oscillation stabilization wait time. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 215 CHAPTER 9 TIME-BASE TIMER 9.5 Operations of Time-base Timer MB90330A Series Table 9.5-1 Time-base Timer Counter Clearance Operation and Oscillation Stabilization Wait Time Operation Counter Clear TBOF Writing "0" to time-base timer initialization bit (TBR) of time-base timer control register (TBTC) ❍ ❍ Power-on reset ❍ ❍ Oscillation Stabilization Wait Time ❍ Watchdog reset Release of main stop mode ❍ ❍ Release of PLL stop mode ❍ ❍ Release of Sub-stop mode Main clock oscillation stabilization wait time Sub clock oscillation stabilization wait time Transition from main clock mode to PLL clock mode (MCS=1 → 0) ❍ ❍ PLL clock oscillation stabilization wait time Transition from sub clock mode to main clock mode (MCS=1 → 1) ❍ ❍ Main clock oscillation stabilization wait time Release of time-base timer mode Release of sleep mode ❍: Yes : None ■ Function of Clock Supply The time-base timer supplies clock to the watchdog timer. The clearance of time-base counter effects the operation of watchdog timer. 216 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 9 TIME-BASE TIMER 9.6 Precautions when Using Time-base Timer MB90330A Series 9.6 Precautions when Using Time-base Timer Cautions about influences on peripheral functions due to interrupt request and timebase timer clearances. ■ Precautions when Using Time-base Timer ● Clearing Interrupt request When clearing the interrupt request flag bit (TBOF) in the time-base timer control register (TBTC), perform while the time-base timer interrupt is masked by the setting of the interrupt level mask register (IML) of the interrupt request permission bit (TBIE) or the processor status (PS). ● Effect from time-base timer clear By clearing the time-base timer counter, the following operations are affected. • When using the interval timer function (interval interrupt) in the time-base timer • When using the watchdog timer ● Using time-base timer as oscillation stabilization wait time After power on, since the oscillation clock halts in the main stop mode, oscillation stabilization wait time of the oscillation clock will be needed using the operation clock supplied from the time-base timer after the oscillator starts operating. Selection of suitable oscillation stabilization wait time is necessary depending on the types of resonators connected to the high-speed oscillation pin. For details, see Section "5.5 Oscillation Stabilization Wait Time". ● Notes on peripheral functions the time-base timer supplies to the clock The mode that stops the main clock clears the counter, and then the time-base timer stops operation. The clock supplied from the time-base timer may shorten the "H" level or lengthen the "L" level for up to 1/2 cycle because the clock is supplied from the initial state when the counter of the time-base timer is cleared. The clock for the watchdog timer is also supplied from the initial status, however, the watchdog timer operates in the normal cycles because the counter of the watchdog timer is cleared at the same time. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 217 CHAPTER 9 TIME-BASE TIMER 9.6 Precautions when Using Time-base Timer MB90330A Series ■ Operations of Time-base Timer Operations in the following situations are shown in Figure 9.6-1. • At a power-on reset occurs. • At a transition to sleep mode during the operation of interval timer function • At a transition to stop mode. • At a counter clear request occurs. The transition to the stop mode clears the time-base timer, terminating operations. Upon the recovery from the stop mode, oscillation stabilization wait time is counted with the time-base timer. Figure 9.6-1 Operations of Time-base Timer Counter value 3FFFFH Clear by transition to the stop mode Oscillation stabilization wait overflow 00000H CPU operation start Power-on reset (Option) Interval cycle (TBTC : TBC1, TBC0=11B) Counter clear (TBTC : TBR=0) Clear by interrupt routine TBOF bit TBIE bit Sleep SLP bit (LPMCR register) Interval interrupt sleep cancellation Stop STP bit (LPMCR register) Stop cancellation by External interrupt When setting "11B" to interval time selection bit (TBTC: TBC1, TBC0) of time-base timer control register (219/HCLK) : Oscillation stabilization wait time HCLK : Oscillation clock 218 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 9 TIME-BASE TIMER 9.7 Program Example of Time-base Timer MB90330A Series 9.7 Program Example of Time-base Timer Programming examples for the time-base timer are shown below. ■ Program Example of Time-base Timer ● Processing specification Interval interruptions of 212/HCLK (oscillation clock) are repeatedly generated. In this case, the interval time is about 0.68 ms (at 6-MHz operation). ● Coding example ICR14 EQU 0000BEH ; Interrupt control register for time-base timer TBTC EQU 0000A9H ; Time-base timer control register TBOF EQU TBTC:3 ; Interrupt request flag bit ;----------Main Program---------------------------------------------------CODE CSEG START: ; : ; Initialize such as a stack pointer (SP) AND CCR, #0BFH ; Disables the interrupt MOV I:ICR14, #00H ; Interrupt level 0 (highest) MOV I:TBTC, #10010000B ; Upper 3 bits fixed ; Interrupt enabled, TBOF Clear ; Counter Clear ; Interval Time Selection 212/HCLK selection LOOP: MOV ILM, #07H ; Sets ILM in PS to level 7 OR CCR, #40H ; Interruption permission MOV A,#00H ; infinite loop MOV A,#01H BRA LOOP ;----------Interrupt Program---------------------------------------------------WARI: CLR bit BOF ; : ; User processing ; : RETI CODE ; The interrupt request flag is clear ; Returns from interrupt ENDS ;----------Vector Settings---------------------------------------------------------VECT CM44-10129-6E CSEG ABS=0FFH FUJITSU MICROELECTRONICS LIMITED 219 CHAPTER 9 TIME-BASE TIMER 9.7 Program Example of Time-base Timer VECT ORG 0FF6CH DSL WARI ORG 0FFDCH DSL START DB 00H ; The interruption vector is set ; Reset vector setting ; Single-chip mode ENDS END 220 MB90330A Series START FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 10 WATCHDOG TIMER This chapter describes the function and operation of the watchdog timer. 10.1 Overview of Watchdog Timer 10.2 Watchdog Timer Control Register (WDTC) 10.3 Configuration of Watchdog Timer 10.4 Operations of Watchdog Timer 10.5 Precautions when Using Watchdog Timer 10.6 Program Examples of Watchdog Timer CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 221 CHAPTER 10 WATCHDOG TIMER 10.1 Overview of Watchdog Timer 10.1 MB90330A Series Overview of Watchdog Timer The watchdog timer is a 2-bit counter operating with an output of the time-base timer or clock timer as the count clock and resets the CPU when the counter is not cleared for a preset period of time. ■ Functions of Watchdog Timer The watchdog timer is a counter for preventing programs from hanging up. The timer must be cleared at specified intervals after being activated. If the watchdog timer is not cleared within a certain time due to an infinite loop of the program, etc., a watchdog reset is generated to the CPU. The interval time of the watchdog timer can be set by the watchdog timer control register (WDTC), as shown in Table 10.1-1. When the watchdog timer is not cleared, a watchdog reset occurs following the time between the minimum time interval and the maximum time interval. The counter must be cleared within the time of the minimum time interval. Table 10.1-1 Interval Time of Watchdog Timer WT1 WT0 WDCS & SCM Interval Time Clock cycle number Min. * Max. * 0 0 1 Approx. 2.39 ms Approx. 3.07 ms (214 ± 211)/HCLK 0 1 1 Approx. 9.56 ms Approx. 12.29 ms (216 ± 213)/HCLK 1 0 1 Approx. 38.23 ms Approx. 49.15 ms (218 ± 215)/HCLK 1 1 1 Approx. 305.83 ms Approx. 393.22 ms (221 ± 218)/HCLK 0 0 0 Approx. 0.448 s Approx. 0.576 s (212 ± 29)/SCLK 0 1 0 Approx. 3.584 s Approx. 4.608 s (215 ± 212)/SCLK 1 0 0 Approx. 7.168 s Approx. 9.216 s (216 ± 213)/SCLK 1 1 0 Approx. 14.336 s Approx. 18.432 s (217 ± 214)/SCLK *: Value for when operating at oscillator clock (HCLK) of 6 MHz, sub clock (SCLK) of 32 kHz divided by 4 (= 8 kHz). The maximum and minimum watchdog timer interval time and the number of oscillation clock cycles are determined by the timing of clear operation. The interval time will be 3.5 to 4.5 times of the count clock (supplied clock of time-base timer) cycle. For the watchdog timer interval time, see Section "10.4 Operations of Watchdog Timer". Note: The watchdog counter is a 2-bit counter that counts carry-up signals from the time-base timer. Therefore, when the time-base timer is cleared, the time period until the occurrence of a watchdog timer reset may be longer than the preset period of time. 222 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E MB90330A Series CHAPTER 10 WATCHDOG TIMER 10.1 Overview of Watchdog Timer Reference: When the watchdog timer is activated, it is initialized and set to the stopped state by a reset upon power-on or by a reset by the watchdog. Also, the watchdog counter is cleared by writing to the reset by the external pin, the software reset, and the watchdog control bit (WTE) of the watchdog timer control register and by changing to sleep, stop, and watch mode, but the watchdog timer is still activated. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 223 CHAPTER 10 WATCHDOG TIMER 10.2 Watchdog Timer Control Register (WDTC) 10.2 MB90330A Series Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) displays the activation, clearance, and reset factor of the watchdog timer. ■ Watchdog Timer Control Register (WDTC) Figure 10.2-1 shows the watchdog timer control register (WDTC). Table 10.2-1 describes the function of each bit of the WDTC register. Figure 10.2-1 Watchdog Timer Control Register (WDTC) Address bit15 bit7 bit8 (TBTC) 0000A8H bit6 PONR R WT1 WT0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 bit5 bit3 bit4 bit2 WRST ERST SRST WTE R R R W bit1 bit0 Initial value WT1 WT0 X-XXX111B W W Interval time select bit (HCLK: 6MHz, SCLK: operating at 32 kHz) Interval time Number of oscillation WDCS & SCM clock cycles Minimum Maximum Approx. 2.39ms Approx. 3.07ms 1 (214 ± 211)/HCLK cycles Approx. 9.56ms Approx. 12.29ms 1 (216 ± 213)/HCLK cycles 1 Approx. 38.23ms Approx. 49.15ms (218 ± 215)/HCLK cycles 1 Approx. 305.83ms Approx. 393.22ms (221 ± 218)/HCLK cycles Approx. 0.448s Approx. 0.576s 0 (212 ± 29)/SCLK cycles Approx. 3.584s (215 ± 212)/SCLK cycles Approx. 4.608s 0 Approx. 7.168s Approx. 9.216s 0 (216 ± 213)/SCLK cycles 0 Approx. 14.336s (217 ± 214)/SCLK cycles Approx. 18.432s HCLK: Oscillation clock SCLK: Sub clock Watchdog control bit Starts the watchdog timer (at first write event after reset) Clears the watchdog timer (at second write event after reset) No operation WTE 0 1 Reset cause bits PONR WRST W R X * ERST SRST Reset cause 1 X X X Power on Read only * 1 * * Watchdog timer Write only * * 1 * External pin (RST ="L" input) * * * 1 RST bit (software reset) Undefined Not used The previous state is held. Default value The interval time will be 3.5 to 4.5 times of the count clock (output value from the time-base timer) cycle. For details, see Section "10.4 Operations of Watchdog Timer". 224 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 10 WATCHDOG TIMER 10.2 Watchdog Timer Control Register (WDTC) MB90330A Series Table 10.2-1 Function of Each Bit of Watchdog Timer Control Register (WDTC) Bit name Functions bit 7, bit 5 to bit 3 PONR WRST ERST SRST Reset factor bit bit 6 Reserved Reserved bit bit 2 WTE bit 1, bit 0 WT1 WT0 CM44-10129-6E • Read-only bits that indicate reset factors. When a reset factor occurs, the relevant bit is set to "1". • The PONR, WRST, ERST and SRST bits are all cleared to "0" after the WDTC register is read. • The contents of the bits other than the PONR bit are not assured at power-on. Therefore, when the PONR bit is "1", ignore the contents of the bits other than the PONR bit. • The reading value is irregular. • Writing does not have the influence in the operation. Watchdog control bit • Writing "0", activates the watchdog timer (at the first write after reset) or clears the 2-bit counter (at the second write after reset). • There is no influence in the operation in writing "1". Interval time select bit • This is a bit to select the interval time of the watchdog timer. • The interval timer when the sub clock mode is selected as the clock mode (the sub clock display bit (SCM) of clock select register (CKSCR) sets to "0") or when the watch timer is used as the clock source of watchdog timer (watchdog timer clock source select bit (WDCS) sets to "0") is different from when the main clock mode or PLL clock mode is selected as the clock mode and the WDCS bit of the WTC is set to "1" as shown in Figure 10.2-1 according to the setting of the watch timer control register (WTC). • The data at the activation of the watchdog timer is valid. Data written after the activation of the watchdog timer is ignored. • The WT1 and WT0 bit are only for writing. FUJITSU MICROELECTRONICS LIMITED 225 CHAPTER 10 WATCHDOG TIMER 10.3 Configuration of Watchdog Timer 10.3 MB90330A Series Configuration of Watchdog Timer The watchdog timer consists of following five blocks. • Count clock selector • Watchdog counter (two bits counter) • Watchdog reset generator circuit • Counter clear control circuit • Watchdog timer control register (WDTC) ■ Block Diagram of Watchdog Timer Figure 10.3-1 shows a watchdog timer block diagram. Figure 10.3-1 Block Diagram of Watchdog Timer Watchdog timer control register (WDTC) PONR WRST ERST SRST WTE Reset Generation Watch mode start Watchdog timer Time-base timer mode start Sleep mode start Hold state start Counter μDMAC state* clear control circuit Stop mode start WT1 WT0 WDCS bit of Watch timer control register (WTC) SCM bit of Clock selection register (CKSCR) 2 CLR and Activation CLR OverWatchdog flow Watchdog reset generation counter circuit Counter clock selector to Internal reset generation circuit CLR 4 4 Clear (Time-base timer counter) 2 divided of HCLK 21 22 28 29 210 211 212 213 214 215 216 217 218 HCLK 21 22 28 29 210 211 212 213 214 215 216 217 218 HCLK: Oscillation clock SCLK: Sub clock *: Hold state means a state at the HRQ (Hold Request) input in the external bus operation mode and at the tool hold input (for MB90V330A only). ● Count clock selector Circuit that selects the count clock of the watchdog timer from four types of time-base timer output and four types of watch timer output. This determines the watchdog reset generation time. ● Watchdog counter (two bits counter) 2-bit up-counter that uses time-base timer output as the count clock. ● Watchdog reset generator circuit Generates a reset signal by an overflow of the watchdog counter. 226 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 10 WATCHDOG TIMER 10.3 Configuration of Watchdog Timer MB90330A Series ● Counter clear control circuit Clears the watchdog counter and controls operation/stop of the counter. Table 10.3-1 Watchdog Timer Clearing Conditions Operation mode Reset WDTC register WTE=0 Stop mode Sleep mode Time-base timer mode Watch mode Hold μDMAC Clear In transition In writing In transition In transition In transition In transition In transition In starting Operating (Starts counting after clearing) Operating (Starts counting after clearing) Operating (Starts counting after clearing) Stopped (Keeps cleared) Stopped (Keeps cleared) Watchdog timer state in modes Disabled - Stopped (Keeps cleared) Watchdog reset in modes Not occur - Not occur Occur Occur Occur Not occur Not occur Operating Operating (Restarts counting after clearing) Operating (Continues counting) Operating (Continues counting) Operating (Continues counting) Operating (Restarts counting after clearing) Operating (Restarts counting after clearing) Watchdog timer state after canceling and returning modes Disabled ● Watchdog timer control register (WDTC) Activates/clears the watchdog timer and holds the reset occurrence factor. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 227 CHAPTER 10 WATCHDOG TIMER 10.4 Operations of Watchdog Timer 10.4 MB90330A Series Operations of Watchdog Timer The watchdog timer generates a watchdog reset upon an overflow of the watchdog counter. ■ Operations of Watchdog Timer Figure 10.4-1 shows the setting required to operate the watchdog timer. Figure 10.4-1 Setting of Watchdog Timer bit15 Address 0000A8H WDTC bit8 bit7 (TBTC) PONR bit6 bit5 bit4 bit3 WRST ERST SRST bit2 bit1 bit0 WT1 WT0 WTE 0 0 Used bit Unused bit Set to "0". ● Activating watchdog timer • The watchdog timer is activated at the first write of "0" to the watchdog control bit (WTE) of the watchdog timer control register (WDTC) after reset. In this case, specify the interval time at the same time by the interval time selection bits (WT1, WT) of the WDTC register. • Once the watchdog time is activated, it cannot stop until power-on or a watchdog reset occurs. ● Clearing watchdog timer • The 2-bit counter of the watchdog timer is cleared by the second write of "0" to the WTE bit. If the counter is not cleared within the interval time, the counter overflows and the watchdog is reset. • The watchdog counter is cleared when a reset operation occurs or when a change to sleep mode, stop mode or time-base timer mode is made. • When a change to time-base timer mode or watch mode is made, the watchdog counter is once cleared. However, be careful that the watchdog counter does not stop after being cleared. • When watch mode is used (sub clock), do not use the watchdog timer. ● Interval Time of Watchdog Timer Figure 10.4-2 shows the relationship between watchdog timer clear timing and interval time. The interval time varies depending on the timing of clearing the watchdog timer and takes 3.5 to 4.5 times of the count clock cycle. ● Checking reset factors By checking the reset factor bit (PONR, WRST, ERST, SRST) of the WDTC register after reset, the factor of the reset can be identified. 228 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 10 WATCHDOG TIMER 10.4 Operations of Watchdog Timer MB90330A Series Figure 10.4-2 Relationship between Clear Timing and Interval Time of Watchdog Timer [Block diagram of Watchdog timer] 2-bit counter Clock selector a 2 divided circuit b 2 divided circuit c Reset circuit d Reset signal Count enable and clear Count enable output circuit WTE bit [Minimum interval time] When clear WTE bit immediately before rising of count clock Count start Counter clear Count clock a 2 divided value b 2 divided value c Count enable Reset signal d 7 (Count clock cycle/2) WTE bit clear Watchdog reset generation [Maximum interval time] When clear WTE bit immediately after rising of count clock Counter clear Count start Count clock a 2 divided value b 2 divided value c Count enable Reset signal d WTE bit clear CM44-10129-6E 7 (Count clock cycle/2) Watchdog reset generation FUJITSU MICROELECTRONICS LIMITED 229 CHAPTER 10 WATCHDOG TIMER 10.5 Precautions when Using Watchdog Timer 10.5 MB90330A Series Precautions when Using Watchdog Timer This section explains precautions when using watchdog timer. ■ Precautions when Using Watchdog Timer ● Stopping watchdog timer Once the watchdog time is activated, it cannot stop until power-on or a watchdog-external reset occurs. ● Interval Time Because the interval time uses carry-up signals from the time-base timer, as the count clock, clearing the time-base timer may make the interval time of the watch dog timer longer than the preset period of time. ● Selecting Interval Time The interval time can be set when activating the watchdog timer. Data written after the activation of the watchdog timer is ignored. ● Precautions when creating program When creating a program that clears the watchdog timer repeatedly in the main loop, the main loop processing time including the interrupt processing must not exceed the minimum interval time of the watchdog timer. 230 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 10 WATCHDOG TIMER 10.6 Program Examples of Watchdog Timer MB90330A Series 10.6 Program Examples of Watchdog Timer Program example of watchdog timer is given below. ■ Program Examples of Watchdog Timer ● Processing specification • The watchdog timer is cleared each time in loop of the main program. • The processing of the main loop must go round within the minimum interval time. ● Coding example WDTC EQU 0000A8H ; Watchdog timer control register WTE EQU WDTC:2 ; Watchdog timer control bit ;----------Main program--------------------------------------------------CODE CSEG START: ; : ; Initialize such as a stack pointer (SP). WDG_START: MOV WDTC, #00000011B ; Activating watchdog timer ; 221 ± 218 cycles in time of the interval are selected. ;----------Main loop------------------------------------------------------MAIN: CLRB ; : ; User processing ; : JMP I:WTE ; Clearing watchdog timer It is regularly clearness of two bits. MAIN ; Interval Time of Watchdog Timer ; Loop in the shortest possible time CODE ENDS ;----------Vector Settings--------------------------------------------------------VECT VECT CSEG ABS=0FFH ORG 0FFDCH DSL START DB 00H ; Single-chip mode setting ENDS END CM44-10129-6E ; Reset vector setting START FUJITSU MICROELECTRONICS LIMITED 231 CHAPTER 10 WATCHDOG TIMER 10.6 Program Examples of Watchdog Timer 232 FUJITSU MICROELECTRONICS LIMITED MB90330A Series CM44-10129-6E CHAPTER 11 WATCH TIMER This chapter describes a overview of the watch timer, functions and configurations of its registers, and its operation. 11.1 Overview of Watch Timer 11.2 Configuration of Watch Timer 11.3 Watch Timer Control Register (WTC) 11.4 Operation of Watch Timer CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 233 CHAPTER 11 WATCH TIMER 11.1 Overview of Watch Timer 11.1 MB90330A Series Overview of Watch Timer The watch timer is a 15-bit timer using the sub clock. It can generate interval interrupts. The watch timer can also be used as the clock source of the watchdog timer by setting so. ■ Functions of Watch Timer The watch timer consists of a 15-bit timer and a circuit that controls interval interrupt. The watch timer uses the sub clock, regardless of the values of the PLL clock selection bit (MCS) and sub clock selection bit (SCS) of the clock selection register (CKSCR). The interval time of the watch timer are shown in Table 11.1-1. Table 11.1-1 Interval Times of Watch Timer WTC2 WTC1 WTC0 Interval Time* 0 0 0 31.25 ms 0 0 1 62.5 ms 0 1 0 125 ms 0 1 1 250 ms 1 0 0 500 ms 1 0 1 1.000 s 1 1 0 2.000 s 1 1 1 Setting disabled *: Four dividing of sub clock 32 kHz (=8 kHz) 234 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 11 WATCH TIMER 11.2 Configuration of Watch Timer MB90330A Series 11.2 Configuration of Watch Timer The watch timer is composed of the following four blocks. • Interval selector • Watch Counter • Watch timer interruption generation circuit • Watch timer control register (WTC) ■ Block Diagram of Watch Timer Figure 11.2-1 shows the watch timer block diagram. Figure 11.2-1 Block Diagram of Watch Timer Watch timer control register (WTC) WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 Clear Watch Counter Sub clock 210 213 214 215 28 29 210 211 212 213 214 Interval selector Interrupt generation circuit Watch timer interrupt to Watchdog timer ● Clock Counter A 15-bit up-counter using the sub clock as the clock source. ● Interval selector A selector that selects one from seven types of interval of the watch timer interrupt. ● Interrupt generation circuit Generates an interval interrupt of the watch timer. ● Watch timer control register (WTC) It specifies the operation of the watch timer, the control of the watch timer interrupt, and the clock source of the watchdog timer. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 235 CHAPTER 11 WATCH TIMER 11.3 Watch Timer Control Register (WTC) 11.3 MB90330A Series Watch Timer Control Register (WTC) Watch timer control register (WTC) controls the operation of watch timer. It also controls the interval interrupt time. ■ Configuration of Watch Timer Control Register (WTC) Figure 11.3-1 shows the watch timer control register (WTC) configuration. Table 11.3-1 summarizes the functions of each bit functions of watch timer control register (WTC). Figure 11.3-1 Configuration of Watch Timer Control Register (WTC) Address bit15 0000AAH bit8 bit7 bit6 WDCS SCE R/W R bit5 bit4 bit3 bit2 bit1 WTIE WTOF WTR WTC2 WTC1 WTC0 R/W R/W R/W R/W WTC2 WTC1 WTC0 R/W 10001000B R/W 0 0 0 31.5 ms 0 0 1 62.5 ms 0 1 0 125 ms 0 1 1 1 0 0 250 ms 500 ms 1 1 0 1 1 0 1 1 1 1000 s 2000 s Setting disabled Watch counter clear bit 0 Clear all bits of counter in Watch timer to "0" 1 No effect WTOF Watch timer interrupt request flag bit 0 No interrupt request generation 1 Interrupt request generation WTIE Watch timer interval interrupt enable bit 0 Interrupt disabled 1 Interrupt enabled SCE 0 1 WDCS R : Write only Initial value Watch timer interval selection bit Interval time (Sub clock: 32kHz) WTR R/W : Readable/Writable bit0 Sub clock oscillation stabilization wait time end bit Oscillation stabilization wait period Oscillation stabilization wait period termination Watchdog timer clock source selection bit 0 Select clock of Watch timer 1 Select clock of Time-base timer : Initial value 236 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E MB90330A Series CHAPTER 11 WATCH TIMER 11.3 Watch Timer Control Register (WTC) Table 11.3-1 Each Bit Functions of Watch Timer Control Register (WTC) Bit name Functions bit 7 WDCS: Watchdog timer clock source selection bit • This bit selects the clock source of the watchdog timer. • Watch timer clock is selected if this bit is "0", and otherwise time-base timer clock is selected if this bit is "1". • Initialized to "1" by a reset. bit 6 SCE: Sub clock oscillation stabilization wait time end bit • It is a bit that indicates the oscillation stabilization wait time for the sub clock ends. • When this bit is "0", it indicates that the oscillation stabilization wait time is elapsing. • The oscillation stabilization wait time for the sub clock is fixed to 214 sub clock cycles. • Initialized to "0" upon power-on reset and upon stop. bit 5 WTIE: Watch timer interval interrupt enable bit • This bit enables an interval interrupt by the watch timer. • Interrupt is enabled if this bit is "1", and otherwise it is disabled if this bit is "1". • Initialized to "0" by a reset. bit 4 WTOF: Watch timer interrupt request flag bit • This bit indicates that an interrupt request of the watch timer has occurred. • When the WTIE bit is 1 and this bit is set to "1", an interrupt request is generated. • It is set to "1" at every interval set with the WTC2 to WTC0 bits. • It is cleared with "0" by writing "0" into it, shifting to stop mode, and reset operation. • Writing "1" does not have the meaning. bit 3 WTR: Watch counter clear bit • This bit clears all bits of the watch timer counter. • The watch timer counter is cleared to "0" by writing "0". • Writing "1" does not have the meaning. • The bit always returns "1" when read. bit 2 to bit 0 WTC2,WTC1,WTC0: Watch timer interval selection bit • It is a bit by which the interval of the watch timer is set. • Initialized to "000B" by reset. • To change the WTC2, WTC1, and WTC0 bits, clear the WTOF bit at the same time. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 237 CHAPTER 11 WATCH TIMER 11.4 Operation of Watch Timer 11.4 MB90330A Series Operation of Watch Timer The watch timer functions as s clock source for the watchdog timer, a timer for sub clock oscillation stabilization delay time and an interval timer that generates an interrupt at regular intervals. ■ Watch Counter The watch counter is a 15-bit counter that counts sub clock and continues counting while sub clock is input. ● Clearing Watch Counter The watch counter is cleared upon a power-on reset, change to stop mode and writing "0" to the watch counter clear bit (WTR) of the watch timer control register (WTC). Notes: • The watchdog timer and interval interrupts that use the output of the watch timer effect on the operation by clearing the watch counter. • To clear the watch timer by writing "0" to the WTR bit in the watch timer control register (WTC), set the WTIE bit to "0" and set the watch timer to interrupt inhibited state. Before permitting an interrupt, clear the interrupt request issued by writing "0" to the WTOF flag. ■ Interruption Function of Interval of Watch Timer A carry-up signal from the watch counter causes an interrupt at regular intervals. ● Specification of Interval Time The (WTC2, WTC1 and WTC0) bits of the WTC register specifies interval time. ● Generation of Watch timer interrupt The watch timer interrupt request flag bit (WTOF) is set for each interval time set by the WTC2, WTC1 and WTC0 bits. In this case, if interrupt is enabled by setting "1" in the watch timer interval interrupt enable bit (WTIE), a watch timer interrupt is generated. The WTOF bit is set, based on the time the watch timer was cleared last. Because, in stop mode, the watch timer functions as a timer for sub clock oscillation stabilization delay time, the WTOF bit is cleared immediately when mode is changed to stop mode. ■ Specification Function of Clock Source of Watchdog Timer The clock source of the watchdog timer can be specified by the watchdog timer clock source selection bit (WDCS) of the WTC register. However, when clock mode is sub clock mode, the counter value of the watch timer is used, regardless of the value of the WDCS bit. ■ Sub Clock Oscillation Stabilization Delay Time Function When recovering from power-on reset or stop mode, the watch timer functions as a timer for sub clock oscillation stabilization delay time. The sub clock oscillation stabilization delay time is fixed to 214 sub clock cycles. 238 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 12 16-BIT I/O TIMER This chapter describes a overview of the 16-bit I/O timer, the functions and configurations of its registers, and its operation. 12.1 Overview of 16-bit I/O Timer 12.2 Register of 16-bit I/O Timer 12.3 Operation of 16-bit I/O Timer CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 239 CHAPTER 12 16-BIT I/O TIMER 12.1 Overview of 16-bit I/O Timer 12.1 MB90330A Series Overview of 16-bit I/O Timer The 16-bit I/O timer consists of one 16-bit free-run timer, and four output compare and four input capture modules. This function enables four independent waveforms to be output based on the 16-bit free-run timer, and input pulse widths and external clock cycle to be measured. ■ Configuration Function of 16-bit I/O Timer The functions of a 16-bit free-run timer, output compare, and input captures that make up the 16-bit I/O timer are as follows: ● 16-bit free-run timer (x1) The 16-bit free-run timer consists of a 16-bit up counter, control register, and prescaler. A value output from the timer counter is used as a basic time by the input capture and output compare. Clock for the counter operation can be selected from eight types (φ: Machine clock). • Eight types of internal clocks (φ,φ/2,φ/4,φ/8,φ/16,φ/32,φ/64,φ/128) • Either the internal or external clock (FRCK) for the basic machine clock can be selected. An interrupt can be generated through the overflow of the counter value and comparing match with the compare clear register (Mode setting is required for comparing match). The count value can be initialized to "0000H" with reset, software clear, and compare match operations with compare clear register. ● Output compare (x4) The output compare consists of four 16-bit compare registers, compare output latch, and control registers. It can reverse the output level and at the same time generate an interrupt when the 16-bit free-run timer value matches that of the compare registers. • Four compare registers are operated independently of each other. There are an output pin and interrupt flag that correspond to each compare register. • The output pin can be controlled by pairing two compare registers. • The initial value of the output pin can be set. • An interrupt can be generated by a comparing match. ● Input capture (x4) The input capture consists of four independent external input pins and associated capture and control registers. It can detect an arbitrary edge of the signal input from external input pin to generate an interrupt while holding the 16-bit free-run timer value in the capture register. • The edge of an external input signal is optional. The external input signal edge can be selected from a rising edge, falling edge, or both edges. • Four input capture can operate independently. Interrupts can be generated through valid edges of external input signals. The input capture can activate μDMAC via interrupt. 240 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 12 16-BIT I/O TIMER 12.1 Overview of 16-bit I/O Timer MB90330A Series ■ Block Diagram Figure 12.1-1 shows the 16-bit I/O timer block diagram. Figure 12.1-1 Block Diagram of 16-bit I/O Timer Control logic Interrupt to each blocks 16-bit free-run timer Compare clear register Clear 16-bit free-run timer 16-bit timer Output compare 0 TQ OUT0 TQ OUT1 Compare register 2 TQ OUT2 Output compare 3 Compare register 3 TQ OUT3 F2MC-16LX Bus Compare register 0 Output compare 1 Compare register 1 Output compare 2 Input capture 0 CM44-10129-6E Capture register 0 Edge selection IN0 Input capture 1 Capture register 1 Edge selection IN1 Input capture 2 Capture register 2 Edge selection IN2 Input capture 3 Capture register 3 Edge selection IN3 FUJITSU MICROELECTRONICS LIMITED 241 CHAPTER 12 16-BIT I/O TIMER 12.2 Register of 16-bit I/O Timer 12.2 MB90330A Series Register of 16-bit I/O Timer Registers for the 16-bit I/O timer are classified into the following general categories: • 16-bit free-run timer • 16-bit output compare • 16 bit input capture The configuration and functions of register are described. ■ Register Configuration of 16-bit I/O Timer The register configuration of the 16-bit I/O timer is shown in the following. ● 16-bit free-run timer Figure 12.2-1 16-bit Free-run Timer Configuration 0 bit 15 00008BH,00008AH CPCLR 000087H,000086H TCDT Timer counter data register 000089H,000088H TCCS Timer control status register Compare clear register ● 16-bit Output compare Figure 12.2-2 16-bit Output Compare Configuration 0 bit 15 007919H,007918H 00791BH,00791AH 00791DH,00791CH 00791FH,00791EH 000055H,000054H 000057H,000056H OCCP0 OCCP1 OCCP2 OCCP3 OCS1 OCS3 Output compare register OCS0 OCS2 Output compare control register ● 16 bit input capture Figure 12.2-3 16 Bit Input Capture Configuration 0 bit 15 007911H,007910H 007913H,007912H 007915H,007914H 007917H,007916H 000053H,000052H 242 IPCP0 IPCP1 IPCP2 IPCP3 ICS23 Input capture data register ICS01 Input capture control status register FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 12 16-BIT I/O TIMER 12.2 Register of 16-bit I/O Timer MB90330A Series 12.2.1 16-bit Free-run Timer The 16-bit free-run timer consists of a 16-bit up-down counter and control status register. A value of the timer counter is used as a basic time of the input capture and output compare (base timer). • Clock for the counter operation can be selected from eight types. • The counter overflow interruption can be generated. • Setting the mode enables initialization of the counter through match operation with the value of the compare clear register in the output compare. ■ Register List of 16-bit Free-run Timer Figure 12.2-4 lists the 16-bit free-run timer registers. Figure 12.2-4 Register List of 16-bit Free-run Timer bit 15 CL15 00008BH R/W 7 bit 00008AH CL07 R/W bit 15 000087H T15 R/W 14 CL14 R/W 6 CL06 R/W 14 T14 R/W 13 CL13 R/W 5 CL05 R/W 13 T13 R/W 7 000086H T07 R/W bit 15 000089H ECKE R/W bit 7 000088H IVF R/W 6 T06 R/W 14 5 T05 R/W 13 bit 12 CL12 R/W 4 CL04 R/W 12 T12 R/W 11 CL11 R/W 3 CL03 R/W 11 T11 R/W 10 CL10 R/W 2 CL02 R/W 10 T10 R/W 9 CL09 R/W 1 CL01 R/W 9 T09 R/W 8 CPCLR CL08 Compare clear register upper R/W Initial value XXXXXXXXB 0 CPCLR CL00 Compare clear register lower R/W Initial value XXXXXXXXB TCDT 8 Timer counter data register upper T08 R/W Initial value 00000000B 4 T04 R/W 12 MSI2 R/W R/W R/W 6 5 4 IVFE STOP MODE R/W R/W R/W 3 T03 R/W 11 MSI1 R/W 3 CLR R/W 2 T02 R/W 10 MSI0 R/W 2 CLK2 R/W 1 T01 R/W 9 ICLR R/W 1 CLK1 R/W 0 T00 R/W 8 ICRE R/W 0 CLK0 R/W TCDT Timer counter data register lower Initial value 00000000B TCCS Timer control status register upper Initial value 0XX00000B TCCS Timer control status register lower Initial value 00000000B R/W :Readable/Writable CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 243 CHAPTER 12 16-BIT I/O TIMER 12.2 Register of 16-bit I/O Timer MB90330A Series ■ Block Diagram of 16-bit Free-run Timer Figure 12.2-5 shows the 16-bit free-run timer block diagram. Figure 12.2-5 Block Diagram of 16-bit Free-run Timer φ Interrupt request #36 F2MC-16LX Bus Comparator IVFE STOP MODE CLR CLK2 CLK1 IVF CLK0 Clock 16-bit free-run timer Count value output T15 to T00 16-bit compare clear register Compare circuit MSI 2 to MSI 0 ICLR ICRE Interrupt request #36 ■ Compare Clear Register (CPCLR) Figure 12.2-6 shows the bit configuration of the compare clear register (CPCLR). Figure 12.2-6 Bit Configuration of Compare Clear Register (CPCLR) 15 00008BH CL15 R/W 7 bit 00008AH CL07 R/W bit 14 CL14 R/W 6 CL06 R/W 13 CL13 R/W 5 CL05 R/W 12 CL12 R/W 4 CL04 R/W 11 CL11 R/W 3 CL03 R/W 10 CL10 R/W 2 CL02 R/W 9 CL09 R/W 1 CL01 R/W 8 CPCLR CL08 Compare clear register upper R/W Initial value XXXXXXXXB 0 CPCLR CL00 Compare clear register lower R/W Initial value XXXXXXXXB R/W :Readable/Writable The compare clear register (CPCLR) is a 16-bit length compare register that is compared with the 16-bit free-run timer. Since the CPCLR register has an indefinite, initial value, you must set the value before enabling the operation. Moreover, please access the CPCLR register the word. When the MODE bit of the timer control status register (TCCS) is set to "1", 16-bit free-run timer value is cleared to "0000H" at matching between the register value and 16-bit free-run timer value. And when the register value is matched with 16-bit free-run timer value, 16-bit free-run timer value is initialized to "0000H", and the compare clear interrupt flag is set. When the interrupt is enabled on the compare clear interrupt flag = 1, the interrupt request is generated to CPU. 244 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 12 16-BIT I/O TIMER 12.2 Register of 16-bit I/O Timer MB90330A Series ■ Timer Counter Data Register (TCDT) Figure 12.2-7 shows the bit configuration of the timer counter data register (TCDT). Figure 12.2-7 Bit Configuration of Timer Counter Data Register (TCDT) bit 000087H bit 000086H 15 14 T15 T14 R/W R/W 13 T13 R/W 12 11 T12 T11 R/W R/W 10 9 8 T10 T09 T08 R/W R/W R/W TCDT 7 6 T07 T06 R/W R/W 5 T05 R/W 4 3 T04 T03 R/W R/W 2 1 0 T02 T01 T00 R/W R/W R/W TCDT Timer counter data register upper Initial value 00000000B Timer counter data register lower Initial value 00000000B R/W :Readable/Writable The timer counter data register (TCDT) is a register that can read a count value of the 16-bit free-run timer. A reset operation clears the count value with "0000H". A timer value can be set by writing the value into the TCDT register, but ensure to perform at the stop state (STOP=1) before doing so. Please access the TCDC register the word. The 16-bit free-run timer is initialized with the following causes: • Initialization by Reset • Initialization by clear bit (CLR) of control status • Initialization by match operation between the compare clear register and the timer counter value (setting the mode is required) ■ Timer Control Status Register (TCCS) Figure 12.2-8 shows the bit configuration of the timer control status register (TCCS). Figure 12.2-8 Bit Configuration of Timer Control Status Register (TCCS) 15 14 13 12 MSI2 000089H ECKE R/W R/W R/W R/W bit 7 6 5 4 000088H IVF IVFE STOP MODE R/W R/W R/W R/W bit 11 MSI1 R/W 3 CLR R/W 10 9 8 TCCS MSI0 ICLR ICRE Timer control status register upper R/W R/W R/W Initial value 0XX00000B 2 1 0 TCCS CLK2 CLK1 CLK0 Timer control status register lower R/W R/W R/W Initial value 00000000B R/W :Readable/Writable The function of each bit in the timer control status register (TCCS) is described in the following. [bit 15] ECKE (External clock input enable bit) This bit enables selection of the count clock source of the 16-bit free-run timer from the internal or external source. Since the clock is changed immediately after writing into the ECKE bit, you must change it when the output compare and input capture are in stopping state. 0 The internal clock source is selected 1 The clock is input from external pin (FRCK). [Initial value] [bit 14, bit 13] Undefined bit The reading value is irregular. No effect on writing. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 245 CHAPTER 12 16-BIT I/O TIMER 12.2 Register of 16-bit I/O Timer MB90330A Series [bit 12 to bit 10] MSI2,MSI1,MSI0 (Interrupt mask selection bit) Bit to set the number of times the compare clear interrupt be masked. It consists of a 3-bit reload counter and the count value is reloaded every time the counter value is "000B". In addition, when writing into the MSI2, MSI1, and MSI0 registers, the count value is also loaded. The number of masks is the number of settings. (Example: Set "010B" if masked twice, interrupted at the third time) However, setting "000B" cannot mask interrupt causes. [bit 9] ICLR (Compare clear interrupt flag bit) It is the interrupt request flag of compare clear. When the compare clear register value matches with the 16-bit free-run timer value by compare operation, this bit is set to "1". When the interrupt request enable bit (ICRE of bit 8) is set, an interrupt is generated. The ICLR bit is cleared by writing "0". Writing "1" does not have the meaning. By the read-modify-write instruction, this bit is always read "1". 0 No Interrupt request 1 Interrupt request [Initial value] [bit 8] ICRE (Compare clear interrupt request enable bit) It is the interrupt enable bits of compare clear. When the bit is "1" and the interrupt flag (ICLR of bit 9) is set to "1", an interrupt is generated. 0 Interrupt disabled 1 Interruption permission [Initial value] [bit 7] IVF (Time overflow generation flag bit) It is the interrupt request flag of 16-bit free-run timer. If the 16-bit free-run timer overflows, or the counter is cleared when it matches the compare clear register through compare operation as a result the mode setting, the IVF bit is set to "1". When the interrupt request enable bit (IVFE of bit 5) is set, an interrupt is generated. Writing "0" into it clears it. Writing "1" does not have the meaning. The read-modify-write instructions always read "1" from this bit. 0 No Interrupt request [Initial value] 1 Interrupt request [bit 6] IVFE (Time overflow interrupt enable bit) It is Interrupt enable bit of 16-bit free-run timer. When the bit is "1" and the write flag (IVF of bit 5) is set to "1", an interrupt is generated. 246 0 Interrupt disabled 1 Interruption permission FUJITSU MICROELECTRONICS LIMITED [Initial value] CM44-10129-6E CHAPTER 12 16-BIT I/O TIMER 12.2 Register of 16-bit I/O Timer MB90330A Series [bit 5] STOP (Timer operation stop bit) It is bit for stopping count of 16-bit free-run timer. Writing "1" into this bit stops counting the 16-bit free-run timer and writing "0" starts counting it. 0 Count permission (operation) 1 Count disabled (Stop) [Initial value] Note that the output compare operation will stop when the 16-bit free-run timer stops counting. [bit 4] MODE (Clear condition selection bit) This bit specifies the initialization conditions of the 16-bit free-run timer. If this bit is "0", the value of the count can be initialized with reset operation and clear bit ((CLR) of bit 2). If this bit is "1", the value of the count can be initialized with reset operation and clear bit ((CLR) of bit 2), and through matching the value of the compare clear register. 0 Initialization by reset and clear bit 1 Initialization by a reset, clear bit or the compare clear register. [Initial value] Further, note that the value of the counter is initialized on the point of change in the count value. [bit 3] CLR (Timer clear bit) This bit initializes the value of the 16-bit free-run timer to "0000H" while it is operating. Writing "1" into the bit initializes the value of the counter to "0000H". Writing "0" into the bit has no meaning. This bit is always "0" at the beginning of reading. The value of the counter is initialized on the point of change in the counter value. 0 No meaning. 1 The counter value is initialized to "0000H" [Initial value] Note that you must write "0000H" into the data register if you want to initialize the counter value while the timer is stopped. Note: If "0" is written to this bit after writing "1" and until next count clock, counter value is not initialized. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 247 CHAPTER 12 16-BIT I/O TIMER 12.2 Register of 16-bit I/O Timer MB90330A Series [bit 2 to bit 0] CLK2,CLK1,CLK0 (Count clock cycle selection bit) Select count clock of 16-bit free-run timer. Since the clock is changed immediately after writing into the CLK2, CLK1, and CLK0 bits you must change it when the output compare and input capture are in stopping state. 248 CLK2 CLK1 CLK0 Count Clock φ=24 MHz φ=12 MHz φ=6 MHz φ=3 MHz 0 0 0 φ 41.7 ns 83.3 ns 0.17 μs 0.33 μs 0 0 1 φ/2 83.3 ns 0.17 μs 0.33 μs 0.67 μs 0 1 0 φ/4 0.17 μs 0.33 μs 0.67 μs 1.33 μs 0 1 1 φ/8 0.33 μs 0.67 μs 1.33 μs 2.67 μs 1 0 0 φ/16 0.67 μs 1.33 μs 2.67 μs 5.33 μs 1 0 1 φ/32 1.33 μs 2.67 μs 5.33 μs 10.7 μs 1 1 0 φ/64 2.67 μs 5.33 μs 10.7 μs 21.3 μs 1 1 1 φ/128 5.33 μs 10.7 μs 21.3 μs 42.7 μs FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 12 16-BIT I/O TIMER 12.2 Register of 16-bit I/O Timer MB90330A Series 12.2.2 Output Compare The output compare consists of 16-bit compare registers, compare output pin part, and a control register. It can reverse the output level for the pin and, at the same time, generate an interrupt when the 16-bit free-run timer value matches a value set in the 16bit compare registers. • It has a total of four compare registers that can operate independently. In addition, the output can be set to be controlled by using two compare registers. • Interrupt can be set through compare-match operation. ■ List of Output Compare Registers Figure 12.2-9 lists the output compare registers. Figure 12.2-9 List of Output Compare Registers bit ch.0:007919H ch.1:00791BH ch.2:00791DH ch.3:00791FH bit ch.0:007918H ch.1:00791AH ch.2:00791CH ch.3:00791EH bit ch.1:000055H ch.3:000057H bit ch.0:000054H ch.2:000056H 14 C14 13 C13 12 C12 11 C11 10 C10 9 C09 8 C08 OCCP0 to OCCP3 Output compare register upper R/W R/W R/W R/W R/W R/W R/W R/W Initial value XXXXXXXXB 7 6 C07 C06 R/W R/W 5 4 3 C05 C04 C03 R/W R/W R/W 2 C02 R/W 1 C01 R/W 0 C00 R/W OCCP0 to OCCP3 Output compare register lower 15 C15 15 14 13 - - - 12 11 10 9 8 CMOD OTE1 OTE0 OTD1 OTD0 R/W R/W R/W R/W R/W 7 6 5 4 ICP1 ICP0 ICE1 ICE0 R/W R/W R/W R/W 3 2 - - Initial value XXXXXXXXB OCS1/OCS3 Output compare control register upper Initial value ---00000B OCS0/OCS2 1 0 Output compare CST1 CST0 control register lower R/W R/W Initial value 0000--00B R/W :Readable/Writable Note: If you rewrite compare registers, you must rewrite them in a compare interrupt routine or in the state of disabled compare operation to ensure that compare-match operation and write operation never occur at the same time. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 249 CHAPTER 12 16-BIT I/O TIMER 12.2 Register of 16-bit I/O Timer MB90330A Series ■ Block Diagram of Output Compare Figure 12.2-10 shows the output compare block diagram. Figure 12.2-10 Block Diagram of Output Compare F2MC-16LX Bus Compare control TQ OTE0 OUT0,OUT2 Compare register 0,2 CMOD 16-bit timer counter value (T15 to T00) OTE1 TQ Compare control OUT1,OUT3 Compare register 1,3 ICP1 ICP0 ICE1 ICE0 Control unit Compare 1, 3 interrupt #29,#31 Each control blocks Compare 0, 2 interrupt #29,#31 ■ Output Compare Registers (OCCP0 to OCCP3) Figure 12.2-11 shows the bit configurations of the output compare registers (OCCP0 to OCCP3). Figure 12.2-11 Bit Configurations of Output Compare Registers (OCCP0 to OCCP3) bit ch.0:007919H ch.1:00791BH ch.2:00791DH ch.3:00791FH bit ch.0:007918H ch.1:00791AH ch.2:00791CH ch.3:00791EH 14 C14 13 C13 12 C12 11 C11 10 C10 9 C09 8 C08 OCCP0 to OCCP3 Output compare register upper R/W R/W R/W R/W R/W R/W R/W R/W Initial value XXXXXXXXB 7 6 C07 C06 R/W R/W 5 4 3 C05 C04 C03 R/W R/W R/W 2 C02 R/W 1 C01 R/W 0 C00 R/W OCCP0 to OCCP3 Output compare register lower 15 C15 Initial value XXXXXXXXB R/W :Readable/Writable The output compare registers (OCCP0 to OCCP3) are 16-bit length compare registers any of which is compared with the 16-bit free-run timer. Since the registers have indefinite, initial values, set the initial values before enabling them. Please access the OCCP0 to OCCP3 register the word. When the values of the OCCP0 to OCCP3 registers match that of the 16-bit free-run timer, the compare signal is generated and the output compare interrupt flag is set. In addition, if output is enabled, the output level corresponding to each of the compare registers is reversed. 250 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 12 16-BIT I/O TIMER 12.2 Register of 16-bit I/O Timer MB90330A Series ■ Output Compare Control Registers (OCS0 to OCS3) Figure 12.2-12 shows the bit configurations of the output compare control registers (OCS0 to OCS3). Figure 12.2-12 Bit Configurations of Output Compare Control Registers (OCS0 to OCS3) bit ch.1:000055H ch.3:000057H bit ch.0:000054H ch.2:000056H 15 14 13 - - - 12 11 10 9 8 CMOD OTE1 OTE0 OTD1 OTD0 R/W R/W R/W R/W R/W 7 6 5 4 ICP1 ICP0 ICE1 ICE0 R/W R/W R/W R/W 3 2 - - OCS1/OCS3 Output compare control register upper Initial value ---00000B OCS0/OCS2 1 0 Output compare CST1 CST0 control register lower R/W R/W Initial value 0000--00B R/W :Readable/Writable The function of each bit in the output compare control registers (OCS0 to OCS3) is described in the following. [bit 15 to bit 13] Undefined bit The reading value is irregular. No effect on writing. [bit 12] CMOD (Output level inverse mode bit) If pin output is enabled (OTE1=1 or OTE0=1), pin output level inverse operation mode is switched when there is a comparing match. • When CMOD=0 (initial value), the pin output level that correspond to the compare register is reversed. - OUT0/OUT2: Reverses the level at a match with the compare register 0/2. - OUT1/OUT3: Reverses the level at a match with the compare register 1/3. • When CMOD=1, compare register 0/2 reverses the output level the same way as when CMOD=0, and the output level of the pin (OUT1/OUT3) that corresponds to compare register 1/3 is reversed when there are comparing matches with both compare register 0/2 and compare register 1/3. If compare register 0/2 and compare register 1/3 have the same value, the operation would be the same as if they were one compare register. - OUT0/OUT2: Reverses the level at a match with the compare register 0/2. - OUT1/OUT3: Reverses the level at a match with the compare register 1/3 or 0/2. [bit 11, bit 10] OTE1,OTE0 (Output enable bit) Bit to enable the pin output of the output compare. The initial value is "0". 0 It operates as a general-purpose port. [Initial value] 1 Becomes the output compare pin output. • OTE1: Corresponding to output compare 1/3 • OTE0: Corresponding to output compare 0/2 CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 251 CHAPTER 12 16-BIT I/O TIMER 12.2 Register of 16-bit I/O Timer MB90330A Series [bit 9, bit 8] OTD1,OTD0 (Output level bit) It is used when you want to change the pin output level if the pin output of the output compare is enabled. The initial value of the compare pin output is "0". To perform a write operation, first, stop the compare operation. When you perform a read operation, the output value of the output compare pin is read out. 0 Sets the compare pin output to "0". [Initial value] 1 Sets the compare pin output to "1". • OTD1: Corresponding to output compare 1/3 • OTD0: Corresponding to output compare 0/2 [bit 7, bit 6] ICP1,ICP0 (Compare match interrupt flag bit) It is output compare interrupt flag.When the values of the compare registers match that of the 16-bit free-run timer, it is set to "1". If the interrupt request bits (ICE1 and ICE0) are enabled, an output compare interrupt is generated when ICP1 and ICP0 bits are set. It is cleared by writing "0" and writing "1" has no meaning. In the read modify system, "1" is read. 0 No Compare match[Initial value] 1 Compare match • ICP1: Corresponding to output compare 1/3 • ICP0: Corresponding to output compare 0/2 [bit 5, bit 4] ICE1,ICE0 (Compare match interrupt enable bit) It is the interrupt enable bit for the output compare. If the ICE1 and ICE0 bits are "1", an output compare interrupt is generated when the interrupt flags (ICP1 and ICP0) are set. 0 Output compare interruption interdiction [Initial value] 1 Output compare interruption permission. • ICE1: Corresponding to output compare 1/3 • ICE0: Corresponding to output compare 0/2 [bit 3, bit 2] Undefined bit The reading value is irregular. No effect on writing. [bit 1, bit 0] CST1,CST0 (Compare operation enable bit) These bits permit a matching operation with the 16-bit free-run timer. 0 Compare operation disabled [Initial value] 1 Compare Operation enabled • CST1: Corresponding to output compare 1/3 • CST0: Corresponding to output compare 0/2 Set the compare register values before enabling a compare operation. 252 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 12 16-BIT I/O TIMER 12.2 Register of 16-bit I/O Timer MB90330A Series Note: Since the output compare is synchronous with the clock of the 16-bit free-run timer, stopping the timer means the stop of the compare operation. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 253 CHAPTER 12 16-BIT I/O TIMER 12.2 Register of 16-bit I/O Timer 12.2.3 MB90330A Series Input Capture This module has a function that detects a rising edge, falling edge, or both edges of externally input signal and holds a value of the 16-bit free-run timer in a register at the time of detection. It can also generate an interrupt when detecting an edge. ■ Input Capture The input capture consist of input capture and control registers. Each input capture has its corresponding external input pin. • The valid edge of the external input can be selected from three types: Rising edge/falling edge/both edges. • It can generate an interrupt when it detects the valid edge of the external input. ■ Block Diagram of Input Capture Figure 12.2-13 shows the input capture block diagram. Figure 12.2-13 Block Diagram of Input Capture Interrupt #25 F2MC-16LX Bus ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 Input capture data register 0 Edge detection IN0 Input capture data register 1 Edge detection IN1 Input capture data register 2 Edge detection IN2 Input capture data register 3 Edge detection IN3 16-bit timer counter value (T15 to T00) ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 Interrupt #27 254 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 12 16-BIT I/O TIMER 12.2 Register of 16-bit I/O Timer MB90330A Series ■ List of Register of Input Capture Figure 12.2-14 lists input capture registers. Figure 12.2-14 List of Register of Input Capture ch.0:007911H ch.1:007913H ch.2:007915H ch.3:007917H ch.0:007910H ch.1:007912H ch.2:007914H ch.3:007916H 000053H bit 15 14 13 12 11 10 9 8 CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 R bit bit R R R R R R R IPCP0 to IPCP3 Input capture data register upper Initial value XXXXXXXXB 7 6 5 4 3 2 1 0 IPCP0 to IPCP3 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 Input capture data register lower Initial value XXXXXXXXB R R R R R R R R ICS23 15 14 13 12 11 10 9 8 Input capture ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 control status register 23 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B ICS01 000052H bit 7 6 5 4 3 2 1 0 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 R/W R/W R/W R/W R/W R/W R/W R/W Input capture control status register 01 Initial value 00000000B R/W :Readable/Writable Read Only R: ■ Input Capture Data Registers (IPCP0 to IPCP3) Figure 12.2-15 shows the bit configurations of the input capture data registers (IPCP0 to IPCP3). Figure 12.2-15 Bit Configurations of Input Capture Data Register (IPCP0 to IPCP3) ch.0:007911H ch.1:007913H ch.2:007915H ch.3:007917H bit 15 14 13 12 11 10 9 8 CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 R R R R R R R R IPCP0 to IPCP3 Input capture data register upper Initial value XXXXXXXXB bit 7 6 5 4 3 2 1 0 IPCP0 to IPCP3 ch.0:007910H CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 Input capture data register lower ch.1:007912H Initial value XXXXXXXXB R R R R R R R R ch.2:007914H ch.3:007916H R :Read Only The input capture data registers (IPCP0 to IPCP3) are registers that hold a value of the 16-bit free-run timer when the valid edges of waveforms input from their corresponding external pins are detected. Please access the IPCP0 to IPCP3 register the word. The IPCP0 to IPCP3 registers are not permitted to write. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 255 CHAPTER 12 16-BIT I/O TIMER 12.2 Register of 16-bit I/O Timer MB90330A Series ■ Control Status Registers (ICS01, ICS23) Figure 12.2-16 shows the bit configurations of the control status registers (ICS01 and ICS23). Figure 12.2-16 The Configuration of Input Capture Control Status Register (ICS01,ICS23) 000053H bit ICS23 15 14 13 12 11 10 9 8 Input capture ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 control status register 23 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B ICS01 000052H bit 7 6 5 4 3 2 1 0 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 R/W R/W R/W R/W R/W R/W R/W R/W Input capture control status register 01 Initial value 00000000B R/W :Readable/Writable The function of each bit in the input capture control status registers (ICS01, ICS23) is described in the following. [bit 15, bit 14, bit 7, bit 6] ICP3,ICP2,ICP1,ICP0 (Valid edge detection flag bit) It is input capture interrupt flag. The input capture sets the ICP3 to ICP0 bits to "1" when it detects valid edges of external input pins. It can generate an interrupt by detecting a valid edge when any of the interrupt enable bits (ICE3, ICE2, ICE1, and ICE0) is set. Writing "0" into it clears it. Writing "1" does not have the meaning. The read-modify-write instructions always read "1" from this bit. 0 There is no effective edge detection 1 There is effective edge detection. [Initial value] ICPn: a number denoted by n corresponds to the channel number of the input capture. [bit 13, bit 12, bit 5, bit 4] ICE3,ICE2,ICE1,ICE0 (Capture interrupt enable bit) It is input capture interrupt enable bit. An input capture interrupt is generated when any of ICE3 to ICE0 bits is "1" and its corresponding interrupt flag (ICP3 to ICP0) is also set. 0 Interrupt disabled [Initial value] 1 Interruption permission ICEn: a number denoted by n corresponds to the channel number of the input capture. [bit 11 to bit 8, bit 3 to bit 0] EG31,EG30,EG21,EG20,EG11,EG10,EG01,EG00 (Edge selection bit) It specifies the polarity of a valid edge of the external input. The input capture operation permission is used combinedly. EGn1 EGn0 Edge detection polarity 0 0 No edge detection (stopped state) 0 1 Rising edge detection 1 0 Falling edge detection 1 1 Both edges detection [Initial value] EGn1/EGn0: a number denoted by n corresponds to the channel number of the input capture. 256 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 12 16-BIT I/O TIMER 12.3 Operation of 16-bit I/O Timer MB90330A Series 12.3 Operation of 16-bit I/O Timer The operation and timing of the 16-bit I/O timer are described. ■ Operation and Timing of 16-bit I/O Timer The following items related to the operation and timing of the 16-bit I/O timer are described. • Operation of 16-bit free-run timer • Operation of 16-bit output compare • Operation of 16-bit input capture • Timing of 16-bit free-run timer - Count timing - Clear timing • Output compare timing - Timing of compare operation - Interrupt timing - Changing timing of the output pin • Input timing of input capture Capture timing to input signal CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 257 CHAPTER 12 16-BIT I/O TIMER 12.3 Operation of 16-bit I/O Timer 12.3.1 MB90330A Series Operation of 16-bit Free-run Timer The operation and timing of the 16-bit free-run timer are described. ■ Operation of 16-bit Free-run Timer The 16-bit free-run timer starts counting at the counter value of "0000H" when a reset has been released. This counter value is a reference time for the 16-bit output compare and 16-bit input capture. The count value is cleared by the following condition. • When an overflow occurs • When there is a comparing match with the value of compare clear register (setting mode is required). • When "1" is written into the CLR bit in the TCCS register while it is operating. • When you write "0000H" in the TCDC register while operating. • At a reset An interrupt is raised when an overflow occurs, or there is a comparing match with the value of compare clear register and the counter value of 16-bit free-run timer (the compare-match interrupt requires mode setting). Figure 12.3-1 shows the timing chart for clearing the counter due to overflow, and Figure 12.3-2 shows the timing chart for clearing the counter due to compare-match operation. Figure 12.3-1 Timing Chart of Counter Clear by Overflow Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset Interrupt 258 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 12 16-BIT I/O TIMER 12.3 Operation of 16-bit I/O Timer MB90330A Series Figure 12.3-2 Timing Chart of Counter Clear by Comparison Result Agreement Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset Compare register value BFFFH Interrupt CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 259 CHAPTER 12 16-BIT I/O TIMER 12.3 Operation of 16-bit I/O Timer 12.3.2 MB90330A Series Operation of 16-bit Output Compare The 16-bit output compare compares the value of the 16-bit free-run timer with that set in one of the compare registers, sets the interrupt request flag and, at the same time, reverses the output level when a match is detected. ■ Example of Output Waveform Examples of the output waveform are illustrated in the following. ● Example of the output waveform when using compare register 0 and 1: Figure 12.3-3 shows an example of the output waveform when the output initial value is "0". Figure 12.3-3 Example of Output Waveform when Using Compare Register 0 and 1 (for Output Initial Value=0, CMOD=0) Compare value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset Compare register 0 value Compare register 1 value BFFFH 7FFFH OUT0 Corresponding to compare 0 OUT1 Corresponding to compare 1 Compare 0 interrupt Compare 1 interrupt The output level can be changed by using two pairs of compare registers. (At CMOD=1) 260 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 12 16-BIT I/O TIMER 12.3 Operation of 16-bit I/O Timer MB90330A Series ● Example of the output waveform by two pairs of compare registers Figure 12.3-4 shows an example of the output waveform when the output initial value is "0". Figure 12.3-4 Example of Output Waveform by Two Pairs of Compare Registers (for Output Initial Value=0, CMOD=1) Compare value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset Compare register 0 value Compare register 1 value BFFFH 7FFFH OUT0 Corresponding to compare 0 Corresponding to compare 1 OUT1 Compare 0 interrupt Compare 1 interrupt Note: To rewriting the compare register, within the compare interrupt routine or compare operation is disabled. Be sure not to occur simultaneously a compare match and writing the compare register. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 261 CHAPTER 12 16-BIT I/O TIMER 12.3 Operation of 16-bit I/O Timer 12.3.3 MB90330A Series Operation of 16-bit Input Capture The 16-bit input capture can capture the value of the 16-bit free-run timer into the capture register and generate an interrupt when it detects a predefined valid edge. ■ Example of Taking Timing of Input Capture Figure 12.3-5 shows the input capture capturing timing example. Figure 12.3-5 Example of Taking Timing of Input Capture Compare value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset IN0 IN1 IN example Capture 0 Indeterminate Capture 1 Indeterminate Capture example Indeterminate 3FFFH 7FFFH BFFFH 7FFFH Capture 0 interrupt Capture 1 interrupt Capture example interrupt 262 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 12 16-BIT I/O TIMER 12.3 Operation of 16-bit I/O Timer MB90330A Series 12.3.4 Timing of 16-bit Free-run Timer The 16-bit free-run timer is counted up by the input clock (internal or external clock). When an external clock is selected, this timer is counted up at a rising edge. ■ Count Timing of Free-run Timer Figure 12.3-6 shows the count timing for the free-run timer. Figure 12.3-6 Count Timing of Free-run Timer φ External clock input Count clock Counter value N N+1 The counter can be cleared by a reset operation, software, and match operation with compare clear register. Clearing the counter with a reset operation and software is performed as a clear is generated. Clearing the counter with a match with compare clear register is performed in sync with the count timing. ■ Free-run Timer Clear Timing (for a Match with Compare Clear Register) Figure 12.3-7 shows the free-run timer clear timing for a match with compare clear register. Figure 12.3-7 Free-run Timer Clear Timing (for a Match with Compare Clear Register) φ Compare clear register value N Compare match Counter value CM44-10129-6E N FUJITSU MICROELECTRONICS LIMITED 0000H 263 CHAPTER 12 16-BIT I/O TIMER 12.3 Operation of 16-bit I/O Timer 12.3.5 MB90330A Series Output Compare Timing The output compare indicates that a compare match signal that is generated when the free-run timer match the value set in the compare registers can reverse the output value and raise an interrupt. The output inverse timing when a comparing match is detected is in sync with the counter timing. ■ Interrupt Timing Figure 12.3-8 shows the output compare interrupt timing. Figure 12.3-8 Output Compare Interrupt Timing φ Counter value N Compare register value N N+1 Compare match Compare match ■ Change Timing for Output Pin Figure 12.3-9 shows the change timing for the output pin of the output compare. Figure 12.3-9 Change Timing for Output Pin of Output Compare Counter value Compare register value N N+1 N N+1 N Compare match signal Output pin Note: If you rewrite compare registers, you must rewrite them in a compare interrupt routine or in the state of disabled compare operation to ensure that compare-match operation and write operation never occur at the same time. 264 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 12 16-BIT I/O TIMER 12.3 Operation of 16-bit I/O Timer MB90330A Series 12.3.6 Input Timing of Input Capture Capture timing to input signal of input capture is described. ■ Capture Timing to Input Signal Figure 12.3-10 shows the capture timing to the input signal of the input capture. Figure 12.3-10 Capture Timing to Input Signal of Input Capture φ Counter value Input capture input N N+1 valid edge Capture signal Capture register N+1 Interrupt CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 265 CHAPTER 12 16-BIT I/O TIMER 12.3 Operation of 16-bit I/O Timer 266 MB90330A Series FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION This chapter describes the functions and overview of the USB Function. 13.1 Overview of USB Function 13.2 Block Diagram of USB Function 13.3 Registers of USB Function 13.4 Operation Explanation of USB Function Code: CM44-00104-1E CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 267 CHAPTER 13 USB FUNCTION 13.1 Overview of USB Function 13.1 MB90330A Series Overview of USB Function The USB Function is an interface that supports the USB (Universal Serial Bus) communication protocol. It operates supporting the transfer speed of FULL (12 Mbps) and has the following characteristics. ■ Features of USB Function • FULL speed (12 Mbps) is supported. (Correspond to USB Full Speed) • The device status is auto-answer. • Bit string, bit stuffing, and automatic generation and check of CRC5 and CRC16 • Toggle check by data synchronization bit • Automatic response to all standard commands except Get/SetDescriptor and SynchFrame commands (these three commands can be processed the same way as the class vendor commands.) • The class vendor commands can be received as data and responded via firmware. • Support up to six EndPoints (EndPoint0 is fixed to control transfer.) • 2 built-in transfer data buffers for each EndPoint (each of two built-in buffers dedicated to IN and OUT, respectively, for EndPoint0) • Support automatic transfer mode for transfer data via DMA (except buffers for EndPoint0) 268 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.2 Block Diagram of USB Function MB90330A Series 13.2 Block Diagram of USB Function Figure 13.2-1 shows the USB Function block diagram. ■ Block Diagram of USB Function Figure 13.2-1 Block Diagram of USB Function EndPoint0 In buffer Internal data bus EndPoint0 Out buffer EndPoint1 buffer Interrupt #11,12 EndPoint2 buffer UDC interface CLK(48MHz) UDC EndPoint3 buffer EndPoint4 buffer Pin DVM DRV USB DVP EndPoint5 buffer SUSP SPT CPU interface UDCC register UDCS register Timestamp Interrupt #13 Interrupt #14 CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 269 CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function 13.3 MB90330A Series Registers of USB Function The configuration and functions of registers used in the USB Function are described. ■ Register List of USB Function Figure 13.3-1 Register List of USB Function bit 15 8 7 UDCC (R/W) EP0C (R/W) EP1C (R/W) EP2C (R/W) EP3C (R/W) EP4C (R/W) EP5C (R/W) TMSP (R) UDCIE 8 bits 270 0 UDCS (R/W) EP0IS (R/W) EP0OS (R/W) EP1S (R/W) EP2S (R/W) EP3S (R/W) EP4S (R/W) EP5S (R/W) EP0DT (R/W) EP1DT (R/W) EP2DT (R/W) EP3DT (R/W) EP4DT (R/W) EP5DT (R/W) 8 bits FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series Figure 13.3-2 Registers of USB Function bit Address:0000D0H 7 6 5 4 RST RESUM HCON USTP 3 2 Reserved Reserved 1 0 RFBK PWC UDC control register (UDCC) bit 15 14 13 12 11 10 9 8 Address:0000D1H Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved bit 7 Address:0000D2H Reserved 6 5 4 bit Address:0000D3H 15 14 13 12 - - - - bit Address:0000D4H 7 6 5 4 bit Address:0000D5H 15 3 2 1 0 10 9 8 STAL Reserved PKS0 11 EP0 control register (EP0C) Reserved Reserved 3 2 1 0 12 11 10 9 8 DIR DMAE NULE STAL PKS1 4 3 2 1 0 PKS1 14 EPEN TYPE bit 7 Address:0000D6H Reserved 6 bit Address:0000D7H 14 15 EPEN 13 TYPE 6 bit Address:0000D9H 14 5 EP2 control register (EP2C) 12 11 10 9 8 DIR DMAE NULE STAL Reserved 4 3 2 1 0 PKS3 EPEN 13 TYPE bit 7 Address:0000DAH Reserved 6 bit Address:0000DBH 14 15 5 EP1 control register (EP1C) PKS2 bit 7 Address:0000D8H Reserved 15 13 5 EP3 control register (EP3C) 12 11 10 9 8 DIR DMAE NULE STAL Reserved 4 3 2 1 0 PKS4 EPEN 13 11 10 9 8 DIR DMAE NULE STAL Reserved bit 7 Address:0000DCH Reserved 6 5 4 3 2 1 0 bit Address:0000DDH 14 13 12 11 10 9 8 DIR DMAE NULE STAL Reserved 4 3 2 1 0 11 10 9 8 15 TYPE EP4 control register (EP4C) 12 PKS5 EPEN TYPE 6 5 EP5 control register (EP5C) bit Address:0000DEH 7 bit Address:0000DFH 15 - - - - - bit Address:0000E0H 7 6 5 4 3 2 1 0 - - SUSP SOF BRST WKUP SETP CONF bit 15 14 13 12 11 10 9 8 SUSPIE SOFIE BRSTIE WKUPIE CONFN CONFIE 0 TMSP 14 Address:0000E1H Reserved Reserved 13 12 Time stamp register (TMSP) TMSP bit Address:0000E2H 7 6 5 4 3 2 1 - - - - - - - - bit Address:0000E3H 15 14 13 12 11 10 9 8 BFINI DRQIIE - - - DRQI - - 7 6 5 4 3 2 1 0 bit Address:0000E4H Reserved bit Address:0000E5H UDC status register (UDCS) UDC interruption permission register (UDCIE) EP0I status register (EP0IS) EP0O status register (EP0OS) SIZE 15 14 13 12 11 10 9 8 BFINI DRQOIE SPKIE - - DRQO SPK Reserved (Continued) CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 271 CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series (Continued) 7 6 5 4 Address:0000E6H bit Address:0000E7H bit 3 bit bit Address:0000EBH bit 15 14 13 12 11 10 9 8 DRQIE SPKIE Reserved BUSY DRQ SPK SIZE 7 6 5 4 3 2 1 0 SIZE Address:0000EDH bit 15 14 13 12 11 10 9 8 DRQIE SPKIE Reserved BUSY DRQ SPK Reserved 7 6 5 4 3 2 1 0 SIZE Address:0000EFH bit 14 13 12 11 10 9 8 BFINI DRQIE SPKIE Reserved BUSY DRQ SPK Reserved 7 6 5 4 3 2 1 0 SIZE 14 13 12 11 10 9 8 BFINI DRQIE SPKIE Reserved BUSY DRQ SPK Reserved 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 BFINI DRQIE SPKIE Reserved BUSY DRQ SPK Reserved 7 6 5 4 3 2 1 0 SIZE 15 14 13 12 7 6 5 4 15 14 13 12 7 6 5 4 15 14 13 12 7 6 5 4 15 14 13 12 7 6 5 4 15 14 13 12 bit 272 0 EP 1 data register (EP1DT) 11 10 9 8 3 2 1 0 EP 2 data register (EP2DT) 11 10 9 8 3 2 1 0 EP 3 data register (EP3DT) 11 10 9 8 3 2 1 0 EP 4 data register (EP4DT) 11 10 9 8 3 2 1 0 BFDT 7 6 5 4 Address:0000FAH Address:0000FBH 1 BFDT Address:0000F9H bit 2 BFDT Address:0000F8H bit 3 BFDT Address:0000F7H bit 8 BFDT Address:0000F6H bit 9 BFDT Address:0000F5H bit 10 BFDT Address:0000F4H bit 11 BFDT Address:0000F3H bit EP0 data register (EP0DT) BFDT Address:0000F2H bit EP5 status register (EP5S) BFDT Address:0000F1H bit EP4 status register (EP4S) 15 Address:0000F0H bit EP3 status register (EP3S) 15 Address:0000EEH Reserved bit EP2 status register (EP2S) BFINI Address:0000ECH Reserved bit 0 BFINI Address:0000EAH Reserved bit 1 EP1 status register (EP1S) Address:0000E8H Reserved Address:0000E9H 2 SIZE EP 5 data register (EP5DT) BFDT 15 14 13 12 11 10 9 8 BFDT FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series 13.3.1 UDC Control Register (UDCC) UDC control register (UDCC) controls the UDC core circuit. ■ UDC Control Register (UDCC) Figure 13.3-3 shows the bit configuration of the UDC control register (UDCC). Figure 13.3-3 UDC Control Register (UDCC) Address bit 0000D0H Address bit 0000D1H 7 6 5 4 3 2 1 0 RST RESUM HCON USTP Reserved Reserved RFBK PWC 1 0 1 0 0 0 0 0 R/W R/W R/W R/W - - R/W R/W 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 0 0 0 0 0 0 ← Initial value - - - - - - - - ← Access UDC control register ← Initial value ← Access R/W : Readable/Writable Note: The UDC control register (UDCC) should be set when bit7:RST=1 and not be rewritten when USB is in operating. However, bit 6 of RESUM and bit 4 of USTP are exclusive. RESUM of bit6 should be set or reset in suspend status of USB only by the remote wake-up enable status due to the following commands. Set USTP of bit4 to "1" before entering the stop mode state. To deselect the stop mode, set the order of SUSP in the UDCS and USTP in the UDCC to "0". The following describes the function of each bit in the UDC control register (UDCC). [bit15 to bit8] Reserved bits These bits are reserved bits. Please write "0". The bit always reads "0". [bit7] RST: Function reset bit Apply an individual reset that is equivalent to the system reset to the chip to the USB Function. Apply a reset to the USB Function with the RST bit when connecting a cable to the HOST PC. Since the RST bit has the initial value of "1" and the USB Function is in reset status, release the Function by writing "0" to the bit. CM44-10129-6E RST Operating mode 0 Reset of USB Function release 1 Reset USB Function FUJITSU MICROELECTRONICS LIMITED 273 CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series Note: The RST bit initializes the corresponding bits of the timestamp register, UDC status register, and interrupt enable register at once. In addition, since it sets EP0I, EP0O, and BFINIs of EP1 to EP5 status registers at the same time after initialization, clear the RST bit (which does not clear the BFINI bits), and clear the BFINI of an endpoint to be used in this sequence. [bit6] RESUM: Resume setting bit When it is in remote Wake-up enabled status (or DEVICE_REMOTE_WAKEUP bit is set with the SET_FEATURE command by the host) and in suspend status, the resume operation is started by writing "1" to the RESUM bit. Clear the resume direction by writing "0" to the RESUM bit that was set to "1". RESUM Operating mode 0 USB resume start dictating bit release 1 USB resume start dictate [bit5] HCON: Host connection bit Control a switch between an external pull-up resistor and the USB data line and allows the USB Function to recognize connections to HOST PC or HUB. HCON Operating mode 0 HOST PC or HUB and connection 1 HOST PC or HUB and state of cutting Note: Even if the external pull-up resistor is HOST at the state of ON or the connection is recognized from the HUB, the bus reset and the command of the USB bus ignores when the HCON bit is set to "1". [bit4] USTP:USB operation clock stop bit Stop the clock of the USB operation part by setting the USTP bit. Setting the USTP bit can reduce power consumption when keeping the USB out of service. 274 USTP Operating mode 0 Normal mode 1 Clock stop of USB operation part FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series Note: If the USTP bit is not used in the stop mode, wait for 3 cycles or 43 cycles to elapse in FULL speed or in LOW speed (that is supported only in HOST mode) so that you can ensure that the reset operation will function when you have set RST=1. You may clear the USTP bit and the RST bit at once. [bit3, bit2] Reserved bits It is reserved bit. Please write "0". The bit always reads "0". [bit1] RFBK: Data toggle mode selection bit (rate feedback mode) It is a bit that selects data toggle mode for USB Interrupt transfer. RFBK Operating mode 0 Selection of alternation data toggle mode It toggles a data PID when a transfer has been successfully completed. 1 Selection of data toggle mode It is a toggle the data PID in unconditional. The data toggle mode selection can be used for rate feedback information in ISO transfer. [bit0] PWC: Power supply control bit It specifies the operating power supply mode (self power or bus power) for the USB Function. (The setting of the PWC bit is reflected in the standard command GetStatus.) CM44-10129-6E PWC Operating mode 0 Bus power 1 Self power FUJITSU MICROELECTRONICS LIMITED 275 CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function 13.3.2 MB90330A Series EP0 Control Register (EP0C) EP0 control register (EP0C) controls concerning end point 0. ■ EP0 Control Register (EP0C) Figure 13.3-4 shows the bit configuration of the EP0 control register (EP0C). Figure 13.3-4 EP0 Control Register (EP0C) Address bit 0000D2H Address 0000D3H 7 6 5 4 3 Reserved bit 2 1 0 PKS0 EP0 control register ← Initial value 0 1 0 0 0 0 0 0 - R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 - - - - Reserved Reserved STAL Reserved X X X X 0 0 0 0 ← Initial value - - - - - - R/W - ← Access ← Access R/W : Readable/Writable Note: Ensure that you must set the EP0 control register (EP0C), except bit9 STAL, when both bit7 RST of the UDC control register (UDCC) and bit15 BFINI of the EP0I/EP0O status register (EP0IS/EP0OS) are "1" and must not rewrite it while the USB is operating. The following describes the function of each bit in the EP0 control register (EP0C). [bit15 to bit12] Undefined bits Writing has no effect on the operation. Reading is undefined. [bit11, bit10] Reserved bits It is reserved bit. Please write "00B". These bits always reads "00B" when read. [bit9] STAL:STALL EndPoint0 set bit Setting the STAL bit can put EndPoint0 in STALL status (STALL response). STAL 276 Operating mode 0 Release of state of STALL 1 Set of state of STALL (STALL response) FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series Note: The STALL response is continued to the host while the STAL bit is set. The USB Function returns from STALL status when it receives a normal SETUP packet after the STAL bit is deselected. [bit8, bit7] Reserved bits It is reserved bit. Please write "00B". These bits always reads "00B" when read. [bit6 to bit0] PKS0:Packet size end point 0 set bits It specifies the maximum number of transfer bytes per packet. The maximum number of transfer bytes per packet that EndPoint0 can specify is 64 bytes, which is a setting common to IN and OUT. <Example> "08H" → 8 Byte, "40H" → 64 Byte (maximum specified value) Note: Setting a value not less than the maximum number of transfer bytes (40H) and "00H" is forbidden. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 277 CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series EP1 to EP5 Control Register (EP1C to EP5C) 13.3.3 EP1 to EP5 control register (EP1C to EP5C) controls concerning end point 1 to end point 5. ■ EP1 to EP5 Control Register (EP1C to EP5C) Figure 13.3-5 shows the bit configuration of the EP1 to EP5 control register (EP1C to EP5C). Figure 13.3-5 EP1 to EP5 Control Register (EP1C to EP5C) Address bit 7 6 5 4 EP1C 0000D4H Address bit EP2C 0000D6H EP3C 0000D8H EP4C 0000DAH EP5C 0000DCH Address bit EP1C 0000D5H Address bit EP2C 0000D7H EP3C 0000D9H EP4C 0000DBH EP5C 0000DDH 3 2 1 0 PKS1 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Reserved ← Initial value ← Access PKS5 to PKS2 0 1 0 0 0 0 0 0 - R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 DIR DMAE NULE STAL PKS1 EPEN TYPE 0 1 1 0 0 0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 DIR DMAE NULE STAL Reserved EPEN TYPE ← Initial value ← Access ← Initial value ← Access 0 1 1 0 0 0 0 0 ← Initial value R/W R/W R/W R/W R/W R/W R/W - ← Access R/W : Readable/Writable Note: Ensure that you must set the EP1 to EP5 control registers (EP1C to EP5C), except DMAE, NULE, and STAL, when both bit7 RST of the UDC control register (UDCC) and bit15 BFINI of the EP0 to EP5 status registers (EP1S to EP5S) are "1" and must not rewrite them while the USB is operating. The following describes the function of each bit in the EP1 to EP5 control register (EP1C to EP5C). [bit15] EPEN: End Point 1 to End Point 5 permission bit The end point is made effective. Setting the EPEN bit allows it to be configures by the host as an end point for use in the USB Function. TYPE, DIR, and PKS of the EP1 to EP5 control registers become valid for configuration information. 278 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series EPEN Operating mode 0 End Point is invalid. 1 End Point is assumed to be effective. [bit14, bit13] TYPE: End point forwarding type selection bits The forwarding type supported by the end point is specified. TYPE Operating mode 00 Specification prohibited 01 Isochronous transfer 10 Bulk transfer 11 Interrupt transfer Note: In Isochronous transfer of USB 2.0, the following item was added to the specification. Initial setting: Alternate value 0 and Maximum number of packets 0. For USB function of this series, if the Alternate value is set to the number other than 0, STALL response is given to Host automatically and the Alternate value cannot be changed. Therefore, maximum number of packets cannot be set by changing the Alternate value. [bit12] DIR: End point forwarding direction selection bit It specifies a transfer direction that the end point supports. DIR Function operating mode HOST operating mode (for EP1 and EP2 only) 0 OUT end point IN end point 1 IN end point OUT end point [bit11] DMAE: DMA automatic transfer enable bit It is a mode setting that uses DMA for read and write operations to transmit and receive buffers for transfer data and automatically transfers transmit and receive data in sync with IN and OUT data requests from the HOST until data whose pieces are as many as the number of transfer data set in DMA is transferred. DMAE Operating mode 0 Release of the automatic buffer TRANSFER mode 1 Set of the automatic buffer TRANSFER mode Note: Access to transmit and receive buffers by CPU is forbidden while the DMAE bit is set. Set the number of DMA transfer data to a multiple of the value of the PKS set in direction the EP1 to EP5 control registers (EP1C to EP5C) when transferring data to OUT. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 279 CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series [bit10] NULE: NULL automatic transfer enable bit This bit sets up a mode where the last packet transfer will be detected and 0-byte data transfer will be automatically sent when IN- direction data transfer request arrives if the automatic buffer transfer mode is set (DMAE=1). NULE Operating mode 0 Release of the NULL automatic TRANSFER mode 1 Set of the NULL automatic TRANSFER mode Note: Setting the NULE bit has no effect on communications when transferring data to OUT direction or the automatic buffer transfer mode is not set. [bit9] STAL:STALL set bit Setting the STAL bit can put EndPoint in STALL status (STALL response). STAL Operating mode 0 Release of state of STALL 1 Set of state of STALL (STALL response) Note: STALL keeps responding for HOST while setting the STAL bit. The USB Function can return from STALL status with the ClearFutcher command from the host after the STAL bit was deselected. EP2 to EP5: [bit8, bit7] Reserved bits These bits are reserved bit. Please write "00B". These bits always read "00B". EP1:[bit8 to bit0] PKS: Packet size set bits EP2 to EP5:[bit6 to bit0] PKS: Packet size set bits The number of maximum forwarding by one packet is specified. The following lists a maximum number of transfer packets that can be specified in each of EndPoint1 to EndPoint5. 280 EndPoint Max. number of transfer Range which can be set 1 256 bytes (The odd can be set). 001H to 100H 2 to 5 64 bytes (The odd can be set). 01H to 40H FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series Note: Setting any number not less than a maximum number of transfer (100H or 40H) and "00H" are prohibited. Please write "00" in bit8, bit7 about EndPoint2 to EndPoint5. In addition, when using the automatic buffer transfer mode (DMAE=1), setting bit0 to bit2 in the corresponding EndPoint is forbidden. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 281 CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function 13.3.4 MB90330A Series Time Stamp Register (TMSP) The time stamp register (TMSP) displays a frame number when an SOF packet is received. ■ Time Stamp Register (TMSP) Figure 13.3-6 shows the bit configuration of the timestamp register (TMSP). Figure 13.3-6 Time Stamp Register (TMSP) Address bit 7 6 5 4 0000DEH Address bit 0000DFH 3 2 1 0 TMSP Time stamp register 0 0 0 0 0 0 0 0 ← Initial value 0 0 0 0 0 0 0 0 ← RST Reset R R R R R R R R ← Access 15 14 13 12 11 10 9 8 - - - - - X X X X X 0 0 0 ← Initial value X X X X X 0 0 0 ← RST Reset - - - - - R R R ← Access TMSP R : Read only The functions of each bit of the time stamp register (TMSP) are described below. [bit15 to bit11] Undefined bits Writing has no effect on the operation. Reading is undefined. [bit10 to bit0] TMSP: Time stamp bits Frame number by the reception of the SOF packet is shown. When the SOF packet is received, frame number is updated. 282 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series 13.3.5 UDC Status Register (UDCS) The UDC status register (UDCS) is a register that indicates the status of a bus on USB communications and a particular command received. Each bit in the register except SETP indicates an interrupt factor and raises an interrupt to CPU if its corresponding interrupt enable bit is specified and valid. ■ UDC Status Register (UDCS) Figure 13.3-7 shows the bit configurations of the UDC status register (UDCS). Figure 13.3-7 UDC Status Register (UDCS) Address bit 0000E0H 7 6 5 4 3 2 1 0 - - SUSP SOF BRST WKUP SETP CONF X X 0 0 0 0 0 0 ← Initial value X X 0 0 0 0 0 0 ← RST Reset - - R/W R/W R/W R/W R/W R/W UDC status register ← Access R/W : Readable/Writable The function of each bit in the UDC status register (UDCS) is described in the following. [bit7, bit6] Undefined bits Writing has no effect on the operation. Reading is undefined. [bit5] SUSP: Suspend detection bit It displays the fact that the USB Function shifts to suspend status. The SUSP bit is an interrupt factor and writing "1" is ignored. Please clear by writing "0". "1" is read at the read modification write. SUSP Operating mode 0 Suspend undetection and interruption clear factor 1 Suspend detection [bit4] SOF:SOF reception detection bit It indicates that an SOF packet has been received, and the value of the time stamp register is updated. The SOF bit is an interrupt factor and writing "1" is ignored. Please clear by writing "0". "1" is read at the read modification write. SOF CM44-10129-6E Operating mode 0 SOF unreception and interruption clear factor 1 The SOF packet is received. FUJITSU MICROELECTRONICS LIMITED 283 CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series [bit3] BRST: Bus reset detection bit The detection of USB bus reset is displayed. The BRST bit is an interrupt factor and writing "1" is ignored. Please clear by writing "0". "1" is read at the read modification write. BRST Operating mode 0 USB bus reset undetected and interrupt factors clear 1 USB bus reset is detected. Note: Set registers again by initializing the USB Function with RST in the UDCC register when the BRST bit is detected. [bit2] WKUP: Wake-Up detection bit It displays the fact that the USB Function has returned from suspend status. What causes the USB Function to return from suspend status are a remote wake-up by setting the RESUM bit and a wake-up from the host request, and the WKUP bit is automatically set only by a return request from the host. The WKUP bit is an interrupt factor and writing "1" is ignored. Please clear by writing "0". "1" is read at the read modification write. WKUP Operating mode 0 HOST factor RESUME undetected and interrupt factors clear 1 HOST factor RESUME is detected. Note: Even if a wake up is caused by a host request, the WKUP bit is not set when the RESUM bit in the UDCC register is set. [bit1] SETP:SETUP stage detection bit It indicates that received data belongs to the Setup stage of USB control transfer. "1" Writing is disregarded. Please clear by writing "0". "1" is read at the read modification write. SETP Operating mode 0 SETUP unreception and clear factor 1 Control forwarding SETUP stage is received. Note: It is not set when automatically responding to any standard command. The SETP bit is not an interruption factor. 284 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series [bit0] CONF: Configuration detection bit It displays the fact that the USB Function has been configured. The CONF bit is set when a SetConfig, a USB command, has been successfully received. The CONF bit is an interrupt factor and writing "1" is ignored. Please clear by writing "0". "1" is read at the read modification write. CONF CM44-10129-6E Operating mode 0 SetConfig undetection and interruption clear factor 1 SetConfig is detected. FUJITSU MICROELECTRONICS LIMITED 285 CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series UDC Interruption Enable Register (UDCIE) 13.3.6 The UDC interrupt enable register (UDCIE) is a register that allows each interrupt factor in the UDC status register to be raised as an interrupt bit wisely except CONFN. ■ UDC Interruption Enable Register (UDCIE) Figure 13.3-8 shows the bit configuration of the UDC interrupt enable register (UDCIE). Figure 13.3-8 UDC Interrupt Enable Register (UDCIE) Address 0000E1H bit 15 14 13 12 11 10 9 8 Reserved Reserved SUSPIE SOFIE BRSTIE WKUPIE CONFN CONFIE UDC interrupt enable register 0 0 0 0 0 0 0 0 ← Initial value 0 0 0 0 0 0 0 0 ← RST Reset - - R/W R/W R/W R/W R R/W ← Access R/W : Readable/Writable R: Read Only The function of each bit in the UDC interrupt enable register (UDCIE) is described in the following. [bit15, bit14] Reserved bits It is reserved bit. Please write "00B". These bits always read "00B". [bit13] SUSPIE: Suspend interrupt enable bit It allows an interrupt due to the interrupt factor for the UDC status register "SUSP" to be generated. SUSPIE Operating mode 0 Interrupt disabled by SUSP factor 1 Interruption permission by SUSP factor [bit12] SOFIE: SOF reception interruption permission bit It allows an interrupt due to the interrupt factor for the UDC status register "SOF" to be generated. 286 SOFIE Operating mode 0 Interrupt disabled by SOF factor 1 Interruption permission by SOF factor FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series [bit11] BRSTIE: Bus reset interruption permission bit It allows an interrupt due to the interrupt factor for the UDC status register "BRST" to be generated. BRSTIE Operating mode 0 Interrupt disabled by BRST factor 1 Interruption permission by BRST factor [bit10] WKUPIE: Wake-Up interruption permission bit It allows an interrupt due to the interrupt factor for the UDC status register "WKUP" to be generated. WKUPIE Operating mode 0 Interrupt disabled by WKUP factor 1 Interruption permission by WKUP factor [bit9] CONFN: Configuration number display bit It displays a configuration number. It is updated when setting the interrupt cause for the UDC status register "CONF". CONFN Operating mode 0 CONFIG Number 0 1 CONFIG Number 1 [bit8] CONFIE: Configuration interrupt enable bit It allows an interrupt due to the interrupt factor for the UDC status register "CONF" to be generated. CM44-10129-6E CONFIE Operating mode 0 Interrupt disabled by CONF factor 1 Interruption permission by CONF factor FUJITSU MICROELECTRONICS LIMITED 287 CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function 13.3.7 MB90330A Series EP0I Status Register (EP0IS) The EP0I status register (EP0IS) displays status related to transfer toward In for EndPoint0. ■ EP0I Status Register (EP0IS) Figure 13.3-9 shows the bit configuration of the EP0I Status Register (EP0IS). Figure 13.3-9 EP0I Status Register (EP0IS) Address bit 0000E2H Address 0000E3H bit 7 6 5 4 3 2 1 0 - - - - - - - - EP0I status register X X X X X X X X ← Initial value X X X X X X X X ← BFINI Reset - - - - - - - - ← Access 15 14 13 12 11 10 9 8 BFINI DRQIIE - - - DRQI - - 1 0 X X X 1 X X ← Initial value 1 Irrelevance X X X 1 X X ← BFINI Reset R/W R/W - - - R/W - - ← Access R/W : Readable/Writable The function of each bit in the EP0I status register (EP0IS) is described in the following. [bit15] BFINI: Transmission buffer initialization bit The forwarding data transmission buffer is initialized. The BFINI bit is automatically set by setting the RST bit in the UDC control register (UDCC). Consequently, when the reset operation has been performed with the RST bit, clear the RST bit before clearing the BFINI bit. BFINI Operating mode 0 Cancelling Initialization 1 Initialization of transmission buffer Note: The initialization of the BFINI bit initializes a buffer and the DRQI bit. You must initialize the buffer when you have set the STAL bit if necessary after you ensure that the DRQI or DRQO bit is set and there is no access from the HOST. 288 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series [bit14] DRQIIE: Transmit data interrupt enable bits It allows an interrupt due to the interrupt factor for the EP0I status register "DRQI" to be generated. DRQIIE Operating mode 0 Interrupt disabled by DRQI factor 1 Interruption permission by DRQI factor [bit13 to bit11] Undefined bits Writing has no effect on the operation. Reading is undefined. [bit10] DRQI: Transmission data interrupt request bit It indicates that IN packet has been successfully transferred from the EP0 host, data has been read from the transmission buffer, and the next transmit data can be written into the buffer. The DRQI bit is a interrupt factor and writing "1" is ignored. Please clear by writing "0". "1" is read at the read modification write. DRQI Operating mode 0 Clearing interrupt cause 1 Writing transmit data enable state Note: After the data write of the transmission buffer is processed, the DRQI must be cleared. Also, when the DRQI is not set, writing "0" is prohibited. When the DRQI is set to "1", writing data to the transmission buffer is enabled. Furthermore, it indicates the data is set to the transmission buffer at the time of clearing. Therefore, when IN packet request is performed with DRQI set "1", the NAK is responded to the HOST automatically. [bit9 to bit0] Undefined bits Writing has no effect on the operation. Reading is undefined. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 289 CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function 13.3.8 MB90330A Series EP0O Status Register (EP0OS) The EP0O status register (EP0OS) displays status related to transfer toward out for EndPoint0. ■ EP0O Status Register (EP0OS) Figure 13.3-10 shows the bit configuration of the EP0O Status Register (EP0OS). Figure 13.3-10 EP0O Status Register (EP0OS) Address bit 0000E4H Address 0000E5H 7 6 5 4 Reserved bit 3 2 1 0 SIZE EP0O status register 0 X X X X X X X ← Initial value 0 X X X X X X X ← BFINI Reset - R R R R R R R ← Access 15 14 13 12 11 10 9 8 BFINI DRQOIE SPKIE - - DRQO SPK Reserved 1 0 0 X X 0 0 0 ← Initial value X X 0 0 0 ← BFINI Reset - - R/W R/W - ← Access 1 Irrelevance Irrelevance R/W R/W R/W R/W : Readable/Writable R: Read Only The function of each bit in the EP0O status register (EP0OS) is described in the following. [bit15] BFINI: Reception buffer initialization bit The forwarding data reception buffer is initialized. The BFINI bit is automatically set by setting the RST bit in the UDC control register (UDCC). Consequently, when the reset operation has been performed with the RST bit, clear the RST bit before clearing the BFINI bit. BFINI Operating mode 0 Cancelling Initialization 1 Initialization of reception buffer Note: The initialization of the BFINI bit initializes a DRQO and the SPK bit. You must initialize the buffer when you have set the STAL bit if necessary after you ensure that the DRQI or DRQO bit is set and there is no access from the HOST. 290 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series [bit14] DRQOIE: Received data interruption permission bit It allows an interrupt due to the interrupt factor for the EP0O status register "DRQO" to be generated. DRQOIE Operating mode 0 Interrupt disabled by DRQO factor 1 Interruption permission by DRQO factor [bit13] SPKIE: Short packet interruption permission bit It allows an interrupt due to the interrupt factor for the EP0O status register "SPK" to be generated. SPKIE Operating mode 0 Interrupt disabled by SPK factor 1 Interruption permission by SPK factor [bit12, bit11] Undefined bits These bits are undefined at read. No effect on writing. [bit10] DRQO: Received data interrupt request bit It indicates that OUT packet has been successfully transferred from the EP0 host, data has been written into the receive buffer, and the receive data can be read from the buffer. The DRQO bit is an interrupt factor and writing "1" is ignored. Please clear by writing "0". "1" is read at the read modification write. DRQO Operating mode 0 Clearing interrupt cause 1 Reading receive data enable state Note: After the data read of reception buffer is processed, the DRQO must be cleared. Also, writing "0" when the DRQO is not set is disabled. When the DRQO is set to "1", the reception buffer is not updated. The buffer is enabled to update when it is cleared. When the OUT packet request is executed with DRQO set "1", the NAK is responded to the HOST automatically. [bit9] SPK: Short packet interrupt request bit It indicates that the number of pieces of transfer data that has been successfully received from the host is less than a maximum number of packets set in PKS in the EP0 control register (EP0C) (including 0 byte). The SPK bit is a interrupt factor and writing "1" is ignored. Please clear by writing "0". "1" is read at the read modification write. CM44-10129-6E SPK Operating mode 0 Maximum number of transfer packets received 1 Data less than the maximum number of transfer packets received FUJITSU MICROELECTRONICS LIMITED 291 CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series [bit8, bit7] Reserved bits These bits are reserved bits. Writing has no effect on the operation. Reading is undefined. [bit6 to bit0] SIZE: Packet size display bit When OUT packets have been transferred from EP0, the number of data bytes that has been written into the receive buffer is displayed. The SIZE bit is updated to a valid value when the interrupt factor for DRQO in the EP0O status register (EP0OS) has been set. <Example> 8 bytes → "08H", 64 bytes → "40H" (maximum value) 292 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series 13.3.9 EP1 to EP5 Status Register (EP1S to EP5S) The EP1 to EP5 status registers (EP1S to EP5S) displays status related to EndPoint1 to EndPoint5. ■ EP1 to EP5 Status Register (EP1S to EP5S) Figure 13.3-11 shows the bit configurations of the EP1 to EP5 status registers (EP1S to EP5S). Figure 13.3-11 EP1 to EP5 Status Register (EP1S to EP5S) Address bit 7 6 5 4 EP1S 0000E6H Address bit 1 0 X X X X X X X X ← Initial value X X X X X X X X ← BFINI Reset R R R R R R R R ← Access 7 6 5 4 3 2 1 0 Reserved bit EP1S 0000E7H bit EP2S 0000E9H EP3S 0000EBH EP4S 0000EDH EP5S 0000EFH SIZE 0 X X X X X X X ← Initial value 0 X X X X X X X ← BFINI Reset - R R R R R R R ← Access 15 14 13 12 11 10 9 8 BFINI DRQIE SPKIE Reserved BUSY DRQ SPK SIZE 1 0 0 - 0 0 0 X ← Initial value - Irrelevance 0 0 X ← BFINI Reset ← Access 1 Address 2 SIZE EP2S 0000E8H EP3S 0000EAH EP4S 0000ECH EP5S 0000EEH Address 3 Irrelevance Irrelevance R/W R/W R/W - R R/W R/W R 15 14 13 12 11 10 9 8 BFINI DRQIE SPKIE Reserved BUSY DRQ SPK Reserved 1 0 0 - 0 0 0 0 ← Initial value - Irrelevance 0 0 0 ← BFINI Reset - R R/W R/W - ← Access 1 R/W Irrelevance Irrelevance R/W R/W R/W : Readable/Writable R: Read Only The function of each bit in the EP1 to EP5 status register (EP1S to EP5S) is described in the following. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 293 CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series [bit15] BFINI: Transmission/receive buffer initialization bit The transmission and reception buffer of the forwarding data is initialized. The BFINI bit is automatically set by setting the RST bit in the UDC control register (UDCC). Consequently, when the reset operation has been performed with the RST bit, clear the RST bit before clearing the BFINI bit. BFINI Operating mode 0 Cancelling Initialization 1 Initialization of transmitting and receiving buffer Note: The transmission/receive buffer for EP1 to EP5 has a configuration of double buffers and initialization by the BFINI bit initializes the double buffers at once and also initializes the DRQ and SPK bits. You must initialize the buffers when you have set the STAL bit after you ensure that the DRQ bit is set and the BUSY bit shows no access from the HOST. [bit14] DRQIE: Packet forwarding interruption permission bit It allows an interrupt due to the interrupt factor for the EP1 to EP5 status register "DRQ" to be generated. DRQIE Operating mode 0 Interrupt disabled by DRQ factor 1 Interruption permission by DRQ factor Note: If you use the automatic buffer transfer mode (DMAE=1), you must enable the settings of DMA and transfer before enabling the DRQIE bit. [bit13] SPKIE: Short packet interruption permission bit It allows an interrupt due to the interrupt factor for the EP1 to EP5 status register "SPK" to be generated. SPKIE Operating mode 0 Interrupt disabled by SPK factor 1 Interruption permission by SPK factor [bit12] Reserved bit This bit is reserved bit. Writing has no effect on the operation. Reading is undefined. 294 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series [bit11] BUSY: Busy flag bit It indicates that writing into the transmission/receive buffer or accessing it for read from the HOST is under way. The BUSY bit is set by the automatic operation, and reset. BUSY Operating mode 0 There is no access by HOST. 1 During writing/reading from HOST Note: It indicates that the HOST is accessing a buffer that is different from either of the double buffer accessed from CPU or DMA when the DRQ bit is set and the BUSY bit is set. Normally, you do not need to control via the BUSY bit, but if you initialize the buffer with BFINI set, you must initialize the buffer by setting the STAL bit after you ensure that the DRQ bit is set and the BUSY bit shows no access from the HOST. [bit10] DRQ: Packet forwarding interrupt request bit It indicates that the packet transfer for EP1 to EP5 has been successfully completed and data processing is needed. The DRQ bit is a interrupt factor and writing "1" is ignored. Please clear by writing "0". "1" is read at the read modification write. DRQ Operating mode 0 Clearing Interrupt cause 1 The packet forwarding ends normally. Note: When the automatic buffer transfer mode (DMAE=1) is not used after the data read or write of transmission and reception buffers is processed, "0" must be write to DRQ bit. When the DRQ bit is cleared, access buffer is switched. When the transfer direction is set to IN direction if the DRQ bit is "1" and the buffer is cleared without writing data, 0-byte data is set to it. In the initial setting, when the DIR of the EP1 to EP5 control register (EP1C to EP5C) is set to "1", the DRQ bit of the corresponding end point is set at the same time. Furthermore, writing 0 is prohibited when the DRQ bit is not set. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 295 CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series [bit9] SPK: Short packet interrupt request bit It indicates that the number of pieces of transfer data that has been successfully received from the host is less than a maximum number of packets set the PKS in the EP1 to EP5 control register (EP1C to EP5C) (including 0 packet). The SPK bit is a interrupt factor and writing "1" is ignored. Please clear by writing "0". "1" is read at the read modification write. SPK Operating mode 0 Max. number of transfer packets received 1 Data less than the Max. number of transfer packets received Note: The SPK bit is not set when data toward IN is transferred. EP2 to EP5:[bit8, bit7] Reserved bits In EP2 to EP5, these bits are reserved bits. "0" is read out from the bit. No effect on writing. EP1:[bit8 to bit0] PKS: Packet size display bits EP2 to EP5:[bit6 to bit0] PKS: Packet size display bits It displays the number of data bytes that have been written into the receive buffer when OUT packet transfer for EP1 to EP5 has been completed. The SIZE bit is updated to a valid value when the interrupt factor for DRQ in the EP1 to EP5 status register (EP1S to EP5S) has been set. The following lists each maximum number of transfer data for EndPoint1 to 5. EndPoint Max. number of transfer Range of display 1 256 Bytes 000H to 100H 2 to 5 64 Bytes 00H to 40H Note: Since the SIZE bit is set to the number of pieces of data that are written into the buffer from the HOST for the OUT direction transfer, any value read from the SIZE bit when IN direction is under way has no meaning. 296 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.3 Registers of USB Function MB90330A Series 13.3.10 EP0 to EP5 Data Register (EP0DT to EP5DT) The EP0 to EP5 data registers (EP0DT to EP5DT) are access registers used to read or write into the transmission/receive buffer for transfer data related to EndPoint0 to EndPoint5. ■ EP0 to EP5 Data Register (EP0DT to EP5DT) Figure 13.3-12 shows the bit configurations of the EP0 to EP5 data registers (EP0DT to EP5DT). Figure 13.3-12 EP0 to EP5 Data Register (EP0DT to EP5DT) Address bit 7 6 5 4 3 2 1 0 BFDT EP0DT 0000F0H EP1DT 0000F2H EP2DT 0000F4H EP3DT 0000F6H EP4DT 0000F8H EP5DT 0000FAH Address bit EP0DT 0000F1H EP1DT 0000F3H EP2DT 0000F5H EP3DT 0000F7H EP4DT 0000F9H EP5DT 0000FBH X X X X X X X X R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 ← Initial value ← Access BFDT X X X X X X X X R/W R/W R/W R/W R/W R/W R/W R/W ← Initial value ← Access R/W : Readable/Writable The following describes the function of each bit in the EP0 to EP5 data registers (EP0DT to EP5DT). [bit15 to bit0] BFDT: EndPoint transmission/receive buffer data bits It is a data read and data write register for the transmission/receive buffer for each EndPoint. Access to the BFDT register via DMA transfer is supported on a word access only. If you transfer the odd number of pieces of data through DMA transfer, you can do so by setting a byte transfer for the last data transfer. If you perform word transfer via CPU access, the last transfer must be byte transfer the same way as in DMA transfer. Note: CPU access to the EP0DT to EP5DT registers are possible both on a per-byte basis and on a perword basis, and if you byte access any of the registers, first, access bit7 to bit0, then access bit15 to bit8, and subsequently access the high-order and low-order alternately. Accessing the EP0DT to EP5DT registers via bit instruction is prohibited. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 297 CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function 13.4 MB90330A Series Operation Explanation of USB Function The USB Function conforms to the USB (Universal Serial Bus) communication protocol and supports basic protocol operations (handshake) by hardware. Consequently, only processing communication data can provide the USB communication. ■ Operation of USB Function The USB Function performs two-way packet transfer with a host controller that supports the USB protocol. A host PC and its devices are connected and configured through enumeration. Then, communications based on various types of transfers using device drivers are performed. This section describes the operation of the USB communications between a host PC and its devices by using enumeration as an example. It illustrates the operations of registers and USB packets to understand the overview of USB communication processing. ● Enumeration process It is the first process that establishes the connection between a host PC and its device before the USB can operate. The host PC examines which devices are connected to the USB bus by using USB control transfer (USB transfer type). This uses EP0 (EndPoint0) out of six endpoints (as defined in the USB specifications) (USB Specification). When EP1 to EP5 are used, the following must be received on the USB bus. 1. USB bus reset 2. Address set by SET_Address 3. Configuration set by SET_Config 298 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function MB90330A Series Figure 13.4-1 Connection Example of USB Cable Pin Direction Overview of operation USB bus connection detection Host Device Operation is not started until the host detects pull-up on the USB bus. Acquiring descriptor information Host Device Data of descriptor is returned to the host. Setting device address Host Device Any address is divided from the host. Acquiring descriptor information (device) Host Device Data of descriptor is returned to the host. Acquiring descriptor information (configuration) Host Device Data of descriptor is returned to the host. Setting configuration Host Device Configuration number is divided from the host. ● Detecting a connection The device notifies the host PC. The host monitors the two signals (D+ and D-) on the USB bus and detects a device connection if either signal goes to the "H" level. For the detailed procedure in the case of a self-powered device, see "13.4.1 Detecting Connection and Disconnection". In the case of a bus-powered device, perform the operation described in "● Example Register Initialization and Operation Startup Procedure". ● Example Register Initialization and Operation Startup Procedure The following is an example of how to initialize the registers and start operation. 1. Set EP0 in the EP0C register (packet size, etc.) 2. Set the EPEN, DIR, and TYPE settings for each EP in the EP1C to EP5C registers. 3. Clear the RST bit in the UDCC register 4. Clear BFINI in the EP0IS, EP0OS, and EP1S to EP5S registers 5. Clear the HCON bit in the UDCC register ● USB bus reset A bus reset is applied from the host PC to the device and the USB device core is initialized. A device must perform processing in the following steps. (The first bus reset after USB has been connected does not need any processing.) 1. Initializes the USB Function with RST in the UDCC register. 2. Set transmission/receive buffers and related control registers again it will use. 3. Return firmware control to the state prior to enumeration. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 299 CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function MB90330A Series ● Getting descriptor The device receives a request from the host PC and sends data to the host. In more detail, communications are performed in the following three stages: Figure 13.4-2 Communication Stage Setup stage → data stage → status stage The setup stage ensures that the device receives normal packets from the host PC and identify the command by decoding it. In addition, the next data stage prepares information on a descriptor to be sent back in a transmission buffer. The data stage simply confirms that normal data is sent from the host PC. The status stage performs end processing when the host PC sends a packet without data. 300 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function MB90330A Series 13.4.1 Detecting Connection and Disconnection This section describes how to detect connection to and disconnection from the USB host. ■ Example USB System Connection Connection to and disconnection from the USB host can be detected by connecting an external interrupt pin to the VBUS pin on the USB connector and connecting a pull-down resistor. Figure 13.4-3 shows an example connection for the D+, D-, and VBUS pins on the USB connector. Figure 13.4-3 Example USB System Connection USB device B connector This device USB host VBUS(5V) VBUS External interrupt (3.3V) D+ 1.5kΩ 27Ω D+ USB USB HCON I/O I/O 27Ω D- D- ● Detecting connection Figure 13.4-4 Operation When Detecting a Connection Connection to HOST VBUS Enable external interrupts ENx Change in interrupt level ERx {LBx,LAx} {0,1} {0,0} HCON Enable connection Time for VBUS to stabilize The device uses the following sequence to detect a connection with the host PC. 1. Set the external interrupt connected to the VBUS to detect "H" level inputs and enable the interrupt. 2. Detection of an "H" level on the external interrupt pin indicates a connection to a USB host. When this occurs, wait for the VBUS to stabilize. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 301 CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function MB90330A Series 3. Temporarily disable the external interrupt. Change the interrupt setting to detect "L" level inputs to the external interrupt pin, and then clear and re-enable the external interrupt. 4. Perform initialization (complete initialization including the USB Function Register). See "Example Register Initialization and Operation Startup Procedure". 5. Clear the HCON bit in the UDCC register and connect the D+ pull-up resistor. (Clear the HCON bit even if not performing control of the pull-up resistor.) Note: You do not need to allow for the above VBUS stabilization time in your program if using an external noise filter on the external interrupt pin. ● Detecting disconnection Figure 13.4-5 Operation When Detecting Disconnection VBUS Disconnect from host ENx Change in source level ERx {LBx,LAx} {0,0} {0,1} On recovery from stop mode SUSP USTP HCON VBUS stabilization time or oscillation stabilization time Set disconnection The device uses the following sequence to detect a disconnection from the host PC. 1. Detection of an "L" level on the external interrupt pin connected to VBUS indicates disconnection from the USB host. 2. On recovery from stop mode: After waiting for the oscillation stabilization time, clear SUSP in the UDCS register followed by USTP in the UDCC register. When not recovering from stop mode: Wait for the VBUS stabilization time. 3. Temporarily disable the external interrupt. Change the interrupt setting to detect "H" level inputs to the external interrupt pin, and then clear and re-enable the external interrupt. 4. Set the HCON bit in the UDCC register and disconnect the D+ pull-up resistor. (Set the HCON bit even if not performing control of the pull-up resistor.) Note: You do not need to allow for the above VBUS stabilization time in your program if using an external noise filter on the external interrupt pin. 302 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function MB90330A Series 13.4.2 Each Register Operation when Command Responds This section describes basic operations and control of registers and then how to process USB packets (architecture). Firmware tasks triggered via CPU interrupt are processed for each handshake operation. This is equivalent to processing each packet on a per-stage basis. ■ Each Register Operation when Read Command Responds For GetDescripter, SynchFrame, and the class vender command Figure 13.4-6 Each Register Operation when Read Command Responds Setup stage Host PC Device Data stage SET DATA UP 0 Device Host PC ACK IN DATA0 DATA 0 write ACK Status stage IN DATA1 write ACK DATA 1 OUT DATA 1 ACK DRQIIE Command read DRQI DRQOIE Soft clear Soft clear DRQO DATA1 read SETP Setup processing Next processing for data stage Command completed processing ● Set-up processing When the setup stage is received, DRQO is set. If the DRQO is set, CPU interrupt is raised and the SETP flag is confirmed. It reads as many commands as necessary in the receive buffer if the DRQO is set (which does not mean all eight bytes need to be read), decode the commands, performs setting tasks, and returns to a point where a process was interrupted after it clears the SETP flag and DRQO interrupt cause. ● Data stage processing If the data stage indicates IN direction as a result of a decoded command, it enables the DRQIIE (as the interrupt cause DRQI has the initial value of "1", it only sets an interrupt to be enabled), and transfers transmission data to the transmission buffer triggered by an CPU interrupt. When transfer has been completed, it clears the interrupt cause DRQI before returning to the interrupted point. The DRQI is set when the data packet toward IN has been completed. The CPU interrupt is entered when the DRQI is set, the transfer data is transferred to the transmission buffer to prepare for the next data packet. When transfer has been completed. it clears the interrupt cause DRQI before returning to the interrupted point. Note: This USB function is not compatible with the newly added commands for USB 2.0; for GetDescripter command, respond with the USB 1.1. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 303 CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function MB90330A Series ● Command completion processing The DRQI is set when the status stage toward OUT has been completed. It enters a CPU interrupt process when the DRQO is set, confirms that the number of received data is 0, and clears the interrupt cause DRQO and returns to the interrupted point to prepare for the next setup stage. ■ Each Register Operation when Write Command Responds For GetDescripter and the class vender command Figure 13.4-7 Each Register Operation when Write Command Responds Setup stage Host PC Device SETUP DATA0 Data stage OUT DATA0 OUT DATA1 ACK ACK Device Host PC Status stage IN ACK ACK DATA1 DRQIIE Soft clear DRQI Command read DRQOIE DATA0 read DATA1 Soft clear Soft clear read DRQO SETP Setup processing Next processing for data stage Command completed processing ● Set-up processing When the setup stage is received, DRQO is set. If the DRQO is set, CPU interrupt is raised and the SETP flag is confirmed. It reads as many commands as necessary in the receive buffer if the DRQO is set (which does not mean all eight bytes need to be read), decode the commands, performs setting tasks. It clears the DRQI (the interrupt cause DRQI due to the initial value of "1") without writing data to the transmission buffer to prepare for a 0-byte response in the status stage, and sets the DRQIIE to confirm the successful completion of the status stage. It also clears the SETP flag and the DRQO interrupt cause before returning from the interrupt to the interrupted point. ● Data stage processing The DRQO is set when the data stage toward OUT has been completed. It enters a CPU interrupt process when the DRQO is set, and first, confirms SIZE of the EP0 status register, and then activates DMA as many times as required for the received number of pieces of data or reads data from the receive buffer via CPU read. Then, it clears the DRQO interrupt cause before returning from the interrupt to the interrupted point. ● Command completion processing The DRQI is set when the status stage toward IN has been completed. It enters a CPU interrupt process when the DRQI is set, and can confirm that the status stage has been successfully completed. Then, it clears the DRQIIE interrupt enable before returning to the interrupted point. 304 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function MB90330A Series 13.4.3 STALL Response and Release For Endpoint0 and For Endpoints 1 to 5, this section explains STALL response and release procedures. ■ STALL response and release procedures for Endpoint0 STALL response and release procedures for Endpoint0 are executed with STAL bit of EP0 Control Register (EP0C). • Set timing of STAL bit For STALL response, interprets the command at detecting SETP bit of "1" (DRQO bit = 1 for interrupt) that indicates the set-up stage of control transfer. (See Figure 13.4-8.) After setting STAL bit, clear interrupt cause (DRQO bit). Figure 13.4-8 Figure 31.4-7 STAL Bit Set Timing Idle time Data stage Set-up stage Token packet Data packet Handshake packet Token packet Data packet Handshake packet DRQO bit SETP bit STAL bit CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 305 CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function MB90330A Series • STAL Bit Clear Timing For STALL release, clears STAL bit at detecting SETP bit of "1" (DRQO bit = 1 for interrupt) that indicates the set-up stage of control transfer, and sets STAL bit if the STALL response is required. (See Figure 13.4-9.) Figure 13.4-9 STAL Bit Clear Timing Idle time Data stage Set-up stage Token packet Data packet Handshake packet Token packet Data packet Handshake packet DRQO bit SETP bit STAL bit clear timing STAL bit Within idle time and 2.75 μs For STALL response release (STAL bit clear), clear STAL bit the period between the time when SETP bit of "1" (DRQO bit= 1 for interrupt) is detected and the time when the data packet transmission/ reception of the next data stage is started. The period between the time when DRQO becomes "1" and the time when STAL bit is cleared is as follows: (Transfer speed: at Full speed of 12Mbps) When STAL bit is not cleared in the following period, execute STAL response with the handshake of data stage. The period between the time when DRQO bit of "1" is detected and the time when STAL bit is cleared: within idle time + 2.75 μs * When idle time is the shortest period of 2-bit transfer time, the above period is within about 2.9 μs. If the STAL bit clear cannot executed within the above period, take an appropriate countermeasures such as lengthening of the idle time with a driver of USB host. ■ STALL response /release of Endpoints 1 to 5 STALL response /release of Endpoints 1 to 5 are controlled with Control registers of EP1 to EP5 and internal condition bit • To execute STAL response with software The procedures to execute STAL response with software are shown in Figure 13.4-10. To execute STAL response, set STAL bit of the relevant endpoint with software. In this time, the internal condition bit does not change. Furthermore, when a host generates a transaction to the endpoint where STAL bit is set, hardware would automatically set the internal condition bit of the relevant endpoint and gives STALL response to the host. Once the internal condition bit is set, the internal condition bit has been set and continues STAL response until Clear Feature command is issued from the host despite of the clearing of STAL bit. As long as the STAL bit is set, STAL bit response continues even if the internal condition bit is cleared with Clear Feature command because the internal condition bit is set every time a transaction to the relevant endpoint occurs. Therefore, to release the STAL response, be sure to clear STAL bit and the internal condition bit with the Clear Feature command. 306 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function MB90330A Series Figure 13.4-10 Case where STALL response is executed with software processing Host or hub Function EPn (End Point n) of Function Macro Internal STAL bit Condition bit 0 Internal Condition bit 0 Software 0 STAL bit Sets STAL bit to "1". 1 IN/OUT token Data (at OUT) STAL handshake Internal Condition bit STAL bit 1 1 When STAL bit is "1", if a transaction occurs, the internal condition bit is set to "1". IN/OUT token Data (at OUT) Transaction to EPn When the internal condition bit is "1", STALL response to a transaction continues. STAL handshake Internal Condition bit IN/OUT token Data (at OUT) STAL handshake 1 STAL bit 0 Clear STAL bit to "0" When the internal condition bit is "1", STALL response to a transaction continues Although STAL bit is "0", it does not affect the internal condition bit. Setup token Clear Feature command to EP0 (EPn is specified.) Data ACK handshake When EPn is specified with Clear Feature command, the internal condition bit is cleared to "0". Internal Condition bit 0 CM44-10129-6E STAL bit 0 FUJITSU MICROELECTRONICS LIMITED 307 CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function MB90330A Series • To automatically execute STALL response with hardware. The procedures to execute STAL response with hardware are shown in Figure 13.4-11. When STALL response is set with Set Feature command, the hardware would automatically set the internal condition bit of the relevant endpoint and gives the STALL response regardless of the STAL bit. Once the internal condition bit is set, the internal condition bit has been held until Clear Feature command is issued from the host to clear the internal condition bit regardless of STAL bit. After the relevant bit is cleared with Clear Feature command, STAL bit is referenced. Therefore, to clear STAL response, be sure to clear the internal condition bit with Clear Feature command. Figure 13.4-11 Case where STALL response is executed with hardware automatically Host or hub Function EPn (End Point n) of Function Macro Internal STAL bit Condition bit 0 Software 0 Setup token Set Feature command to EP0 (EPn is specified.) Data (at OUT) ACK handshake When EPn is specified with Set Feature command, the internal condition bit is set to "1". Internal Condition bit 1 STAL bit 0 IN/OUT token Data (at OUT) Transaction to EPn STALL handshake When the internal condition bit is "1", STALL response to a transaction continues. Although STAL bit is "0", it does not affect the internal condition bit. Setup token Clear Feature command to EP0 (EPn is specified.) 308 Data ACK handshake Internal Condition bit STAL bit 0 0 When EPn is specified with Set Feature command, the internal condition bit is cleared to "0". FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function MB90330A Series 13.4.4 Suspend Function A USB device must have a configuration of bus power supply where power consumption is 500μA or less in suspend status. The section covers a USB device from its transmitting to suspend status to its entering STOP mode. ■ Suspend Processing When the USB device core detects suspend status, SUSP of the UDCS register is set to be enabled. The following shows an example of suspend operation: Figure 13.4-12 Suspend Operation Host PC Device 1ms SOF 1ms SOF 3ms SOF Suspend state Remote wake-up support 2ms SUSP STP SUSP flag Soft clear ● Suspend processing The USB Function determines that it detects suspend status when there is no operation for not less than 3 ms on the USB bus, and the SUSP interrupt cause in the UDCS register is set. If a USB device supports remote wake-up, the USB Function waits another 2 ms (which blocks remote wake-up during this time period), and set the device to stop mode. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 309 CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function 13.4.5 MB90330A Series Wake-up Function To shift a USB device from suspend status to wake-up status, the USB protocol provides the following two ways: • Remote wake-up from device • Wake-up from host PC The above is explained. ■ Remote Wake-up Figure 13.4-13 Remote Wake-up Operation Suspend state Host PC Device Device Host PC 20ms 1ms 1ms RESUME SOF SOF RESUME Oscillation stabilization time 10ms RESUM STP INT pin RESUM Soft set, clear External interrupt A device must perform processing in the following steps: 1. Recover the device from stop mode through external interrupt. 2. RESUM of the UDCC register is set. 3. RESUM of the UDCC register is cleared. ■ Wake-up from Host Figure 13.4-14 Wake-up Operation from Host Suspend state not less than 20ms Host PC Device RESUME Oscillation stabilization time WKUP 1ms 1ms SOF SOF WKUP flag Soft clear STP For the devices, the following processing is required: 1. Set oscillation stabilizing time to be not more than 10 ms. 2. Enter an interrupt due to the WKUP factor and clear WKUP of UDCS that is the interrupt cause and return from the interrupt. 310 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function MB90330A Series 13.4.6 DMA Transfer Function It is possible to transfer data between transmission/receive buffer and internal RAM that the USB Function communicates. You can select the following two modes in DMA transfer: one is packet transfer mode where data is transferred based on the number of pieces of transfer set on a per-packet basis and another is data number automatic transfer mode where all data is transferred based on the number of pieces of data specified once. Each DMA transfer mode is explained. ■ Packet Transfer Mode • The packet transfer mode performs transfer by setting the number of pieces of transfer per packet in DMA and clearing the interrupt cause when transfer has been completed. The transfer mode can access any buffer in each endpoint. • Timing by which the buffer is accessed in OUT direction and IN direction is shown as follows. • OUT direction (host PC → device) forwarding Figure 13.4-15 OUT Packet Forwarding OUT packet Host PC Device Device Host PC DMAE OUT OUT packet OUT DATA0 DATA1 ACK ACK DRQ flag* CPU clear DRQ flag* CPU clear DRQIE DRQ SIZE DER(ENx) DMA receive buffer read (DATA0) DMA receive buffer read (DATA1) In OUT- direction transfer, a USB device must perform processes in the follows steps: 1. It confirms the number of pieces of transfer data when the DRQ flag is set and the interrupt process is entered. 2. It sets the number of pieces of transfer data in the data counter register DDCT of DMA, enables DMA with the DER register, and start transfer. 3. Once transfer has been completed, it clears the corresponding DRQ flag in the EP1S to EP5S registers and the corresponding interrupt factor flag in the DSR register of μDMAC and returns from the interrupt process. *: EP1 to EP5 consists of the double buffers, it can be cleared only when one buffer that is not being accessed is empty and data is read from another buffer being accessed and cannot be cleared even though "0" is written to it if one buffer that is not being accessed has data left to be read (Dotted line status). It continuously enters the DRQ interrupt process. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 311 CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function MB90330A Series ● IN direction (host PC → device) forwarding Figure 13.4-16 IN Packet Forwarding IN packet IN packet Host PC Device Device DRQ flag* Host PC CPU clear DMAE DRQIE IN ACK DATA0 IN DRQ flag* CPU clear ACK DATA1 DRQ DER(Enx) DMA sending buffer write (DATA0) DMA sending buffer write (DATA1) In IN- direction transfer, a USB device must perform processes in the follows steps: 1. When the DRQ flag is set and enters the interrupt process, it sets the number of pieces of data to be transferred in an IN packet in the data counter register DDCT of DMA, enables DMA with the DER register, and start transfer. 2. Once DMA transfer has been completed, it clears the corresponding DRQ flag in the EP1S to EP5S registers and the corresponding interrupt factor flag in the DSR register of μDMAC and returns from the interrupt process. *: EP1 to EP5 consists of the double buffers, it can be cleared only when one buffer that is not being accessed has already data written into it and data is written into another buffer that is being accessed and cannot be cleared even though "0" is written to it when one buffer that is not being accessed is empty (Dotted line status). It continuously enters the DRQ interrupt process. 312 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function MB90330A Series ■ Data Number Automatic Transfer Mode It sets the total number of pieces of data to be transferred in DMA and sets the transfer enable bit in advance. When DMAE is enabled and the DRQ is set after transfer from the HOST has been completed, the interrupt cause is automatically cleared when data whose number of pieces is equal to the PKS in the EP1 to EP5 control registers (EPxC) has been transferred (Whether the DRQ flag is actually cleared depends on the fact that both buffers in a double buffer are empty or full). Subsequently, when transfer from the HOST has been completed, repeat the similar process until data equivalent to the number of pieces of transfer data predefined in DMA. has been transferred. Meanwhile, any intervention from CPU is not required, and transfer will be completed with only one setting, which is the automatic transfer mode. If the device performs the next transfer, it sets μDMAC again and enables DMA when a CPU interrupt is raised when the last data has been transferred, and returns from the CPU interrupt. Since the data number automatic transfer mode is used for DMAE=1, only buffer access to endpoint 1 to endpoint5 is enabled. Timing by which the buffer is accessed in OUT direction and IN direction is shown as follows. Figure 13.4-17 OUT Direction (Host PC → Device) Forwarding OUT packet Host PC Device Device Host PC OUT Last OUT packet OUT DATA1 DATA0 ACK DRQ flag* Automatic clear DRQ flag* ACK Automatic clear DMAE DRQIE DATA0 DRQ SIZE DATA1 DER(Enx) Read PKS part of DMA receive buffer Read the rest of DMA receive buffer In both OUT- direction and IN- direction transfer, a USB device must perform processes in the following steps: 1. It sets the total number of pieces of data to be transferred in the data counter register DDCT in DMA and enables DMA with the DER register. 2. DMAE and DRQIE, are permitting set. 3. Once transfer has been completed, it sets μDMAC again with an interrupt due to the corresponding interrupt factor in the DSR register of μDMAC and clear the flag if necessary, and returns from the interrupt process. *: It consists the double buffers of EP1 to EP5. It should be cleared only (auto-reset) when one buffer that is not being accessed is empty and data is read from another buffer being accessed (Automatic clear) and cannot be cleared if one buffer that is not being accessed has data left to be read. It continuously enters the DRQ interrupt process. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 313 CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function MB90330A Series Figure 13.4-18 IN Direction (Device → Host PC) Forwarding Last data Data Host PC Device Device Host PC ACK IN DRQ flag * Automatic clear DATA0 ACK IN DRQ flag* Automatic clear DATA1 DMAE DRQIE DRQ DATA0 DATA1 DER(Enx) Write PKS part of DMA sending buffer Write the rest of DMA sending buffer In both OUT- direction and IN- direction transfer, a USB device must perform processes in the following steps: 1. It sets the total number of pieces of data to be transferred in the data counter register DDCT in DMA and enables DMA with the DER register. 2. DMAE and DRQIE, are permitting set. 3. Once transfer has been completed, it sets μDMAC again with an interrupt due to the corresponding interrupt factor in the DSR register of μDMAC and clear the flag if necessary, and returns from the interrupt process. *: EP1 to EP5 consists of the double buffers, it can be cleared only when one buffer that is not being accessed has already data written into it and data is written into another buffer that is being accessed and cannot be cleared when one buffer that is not being accessed is empty. It continuously enters the DRQ interrupt process. 314 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function MB90330A Series 13.4.7 NULL Transfer Function If data sent from the USB Function is the last packet and a maximum number of packets, it is possible to automatically transfer 0-byte data in the next packet transfer. The NULL transfer function requires that DMAE is enabled and is a function that is only valid for IN transfer. ■ NULL Transfer Mode ● This is the mode where if the automatic buffer transfer mode is set (DMAE=1) and IN-direction data transfer request arrives, and a maximum number of packets are written via DMA and the last data write decrements the number of DMA count data to "0", it automatically sets 0-byte data transfer and will send 0-byte data for the next IN-direction data transfer request when the last IN-direction data transfer request from the HOST has been received. The DRQ interrupt flag is not set until 0-byte data is read from the HOST after the last data was written into a buffer via DMA. Timing by which the buffer is accessed is shown as follows. ● Only IN direction (device → host PC) forwarding Figure 13.4-19 NULL Data Transfer Operation Data before last Host PC Device DRQ flag Device Automatic Host PC clear IN Last data ACK IN DATA0 0 byte data ACK DATA1 IN ACK DATA0 DMAE DRQIE DRQ Last data DATA1 NULE DER(ENx) DMA sending buffer MAX packet write Interrupt factor is not set. For the devices, the following processing is required: DMAE, DRQIE, and NULE are permitting set. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 315 CHAPTER 13 USB FUNCTION 13.4 Operation Explanation of USB Function 316 FUJITSU MICROELECTRONICS LIMITED MB90330A Series CM44-10129-6E CHAPTER 14 USB HOST This chapter describes the functions and operation of USB HOST. 14.1 Feature of USB HOST 14.2 Restriction on USB HOST 14.3 Block Diagram of USB HOST 14.4 Register of USB HOST 14.5 Operation of USB HOST 14.6 Each Token Flow Chart of USB HOST Code: CM44-00102-1E CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 317 CHAPTER 14 USB HOST 14.1 Feature of USB HOST 14.1 MB90330A Series Feature of USB HOST USB HOST provides minimum host operations required and is a function that enables data to be transferred to and from Device without PC intervention. ■ Feature of USB HOST USB HOST has not only original function as the USB host but also the USB function by switching operation mode. USB HOST has the following features. • Automatic detection of Low Speed/Full Speed forwarding • Low Speed/Full Speed forwarding support • Automatic detection of connection and cutting device • Reset sending function support to USB bus • Support of IN/OUT/SETUP/SOF token • Automatic transmission of handshake packet for IN token (excluding STALL) • Handshake packet automatic detection at OUT token • Supports a maximum packet length of 256 bytes. • Various error (CRC error/toggle error/time-out) supports • Wake Up function support 318 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.2 Restriction on USB HOST MB90330A Series 14.2 Restriction on USB HOST This section indicates Restriction on USB HOST. ■ Restriction on USB HOST HOST ❍* Support Hub Transfer Transfer speed Bulk transfer ❍ Control transfer ❍ Interrupt transfer ❍ Isochronous transfer × Low Speed ❍ Full Speed ❍ PRE packet support × SOF packet support ❍ Error CRC error ❍ Toggle error ❍ Time-out ❍ Max. packet < Receive Data ❍ Detection of connection and cutting of device ❍ Transfer speed detection ❍ ❍: Supported : Not supported * : Only Full Speed corresponds, and HUB is a support up to one step. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 319 CHAPTER 14 USB HOST 14.3 Block Diagram of USB HOST 14.3 MB90330A Series Block Diagram of USB HOST Figure 14.3-1 shows the block diagram of USB HOST. ■ UART Block Diagram of USB HOST Figure 14.3-1 Block Diagram of USB HOST RX Selector Receive control unit Buffer HRX CPU I/F UDC I/F TX TXENL Transmit control unit HTX USB bus reset control unit Explanation of block CPUI/F Buffer CPUI/F USB bus reset control part RX control part TX control part: Host TX control part: TX RX TXENL HTX HRX HTXENL 320 Host receive control unit HTXENL : Interface circuit block with CPU : Buffer and buffer control circuit block : Interface circuit block with CPU : USB bus reset and connection control block : Receive data serial to parallel conversion circuit and RX control circuit block : Transmission data parallel to serial conversion circuit and TX control circuit block for the USB Function : Transmission data parallel to serial conversion circuit and TX control circuit block for HOST : Transmission data signal of function : Received data signal of function : Function transmission and receive direction signal : HOST transmit data signal : HOST receive data signal : HOST transmission and receive direction signal FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.4 Register of USB HOST MB90330A Series 14.4 Register of USB HOST In USB HOST, there are the following ten types of registers: • Host control register 0,1(HCNT0/HCNT1) • Host interruption register (HIRQ) • Host error status register (HERR) • Host state status register (HSTATE) • SOF interruption FRAME comparison register (HFCOMP) • Retry timer setting register (HRTIMER) • HOST address register (HADR) • EOF setting register (HEOF) • FRAME setting register (HFRAME) • Host token end point register (HTOKEN) ■ Register of USB HOST • Host control register 0 bit 7 6 5 4 3 2 1 0 RWKIRE URIRE CMPIRE CNNIRE DIRE SOFIRE URST HOST (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved SOFSTEP CANCEL RETRY (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (1) 7 6 5 4 3 2 1 0 Address: 0000C2H TCAN Reserved RWKIRQ URIRQ CMPIRQ CNNIRQ DIRQ SOFIRQ Read/Write → (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value → (0) (0) (0) (0) (0) (0) (0) (0) 15 14 13 12 11 10 9 8 LSTSOF RERR TOUT CRC TGERR STUFF HS (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (11B) Address: 0000C0H Read/Write → Initial value → HCNT0 • Host control register 1 bit 15 Address: 0000C1H Reserved Read/Write → Initial value → HCNT1 • Host interruption register bit HIRQ • Host error status register bit Address: 0000C3H Read/Write → Initial value → HERR (Continued) CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 321 CHAPTER 14 USB HOST 14.4 Register of USB HOST MB90330A Series (Continued) • Host state status register bit 7 5 4 3 2 1 0 Reserved ALIVE CLKSEL SOFBUSY SUSP TMODE CSTAT → (-) (R/W) (R/W) (R/W) (R/W) (R) (R) Initial value → (x) (0) (1) (0) (0) (1) (0) 11 10 9 8 Address: 0000C4H Read/Write 6 HSTATE • SOF interruption FRAME comparison register bit 15 14 13 12 Address: 0000C5H Read/Write FRAMECOMP → HFCOMP (R/W) Initial value → (00000000B) • Retry timer setting register bit 7 6 5 4 Address: 0000C6H Read/Write → bit 1 0 HRTIMER (R/W) (00000000B) 15 14 13 12 Address: 0000C7H 11 10 9 8 RTIMER1 → HRTIMER (R/W) Initial value → bit 2 RTIMER0 Initial value → Read/Write 3 (00000000B) 7(23) 6(22) 5(21) Address: 0000C8H 4(20) 3(19) 2(18) 1(17) 0(16) Reserved RTIMER2 → (-) (R/W) Initial value → (x) (00B) Read/Write HRTIMER • Host address register bit 15 14 13 12 Address: 0000C9H Reserved 11 10 8 Address → (-) (R/W) Initial value → (x) (0000000B) Read/Write 9 HADR • EOF setting Register bit 7 6 5 4 3 Address:0000CAH EOF0 → (R/W) Read/Write Initial value → bit Address:0000CBH 2 0 HEOF (00000000B) 15 14 13 12 11 10 Reserved EOF1 → (-) (R/W) Initial value → (x) (000000B) Read/Write 1 9 8 HEOF (Continued) 322 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.4 Register of USB HOST MB90330A Series (Continued) • FRAME setting Register bit 7 6 5 4 Address:0000CCH Read/Write 2 1 HFRAME (R/W) Initial value → (00000000B) 15 14 Address:0000CDH 13 12 11 10 9 Reserved FRAME1 → (-) (R/W) Initial value → (x) (000B) Read/Write 0 FRAME0 → bit 3 8 HFRAME • Host token end point register bit 7 6 5 4 3 2 1 Address:0000CEH TGGL TKNEN ENDPT → (R/W) (R/W) (R/W) (0) (000B) (0000B) Read/Write Initial value → CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 0 HTOKEN 323 CHAPTER 14 USB HOST 14.4 Register of USB HOST 14.4.1 MB90330A Series Host Control Register 0,1(HCNT0/HCNT1) Host control registers 0,1(HCNT0/HCNT1) specify the USB operation mode and the settings of an interrupt. ■ Host Control Register 0, 1(HCNT0/HCNT1) Figure 14.4-1 Bit Configuration of Host Control Register 0, 1 (HCNT0/HCNT1) Host control register 0 bit 7 6 5 4 3 2 1 0 RWKIRE URIRE CMPIRE CNNIRE DIRE SOFIRE URST HOST (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value → (0) (0) (0) (0) (0) (0) (0) (0) Reset On/Off at UDCC RST bit → ( ) ( ) ( ) ( ) ( ) ( ) (❍) ( ) 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved SOFSTEP CANCEL RETRY (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value → (0) (0) (0) (0) (0) (0) (0) (1) Reset On/Off at UDCC RST bit → ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) Address: 0000C0H Read/Write → HCNT0 Host control register 1 bit Address: 0000C1H Reserved Read/Write → HCNT1 [bit 15 to bit 11] Reserved It is reserved bit. Be sure to set this bit to "0". [bit 10] SOFSTEP: SOF interrupt condition selection It sets whether an interrupt due to SOF is generated every time SOF is executed. The interrupt is enabled when the SOFIRE bit in host control register 0 (HCNT0) is "1". When it is "0", the interrupt is generated via the setting of the SOF interrupt FRAME comparison register (HFCOMP), and when it is "1", the interrupt is unconditionally generated every time SOF is executed. However, the interruption is not generated at the first SOF token. It is not initialized with the RST bit in the UDC control register (UDCC). SOFSTEP 324 Operation mode 0 Interrupt is generated due to the setting of HFCOMP. 1 Interruption generation FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.4 Register of USB HOST MB90330A Series [bit 9] CANCEL: Token cancellation permission This bit sets whether a token is to be cancelled when the token (which is issued in an EOF area) has never been executed and is in waiting status if the SOFIRQ bit in the host interrupt register (HIRQ) is "1". It is not initialized with the RST bit in the UDC control register (UDCC). CANCEL Operation mode 0 Token continuance 1 Token discontinuance [bit 8] RETRY: Retry permission This bit sets whether a retry is attempted when a NAK and CRC errors happen. It is not initialized with the RST bit in the UDC control register (UDCC). RETRY Operation mode 0 No retry 1 Retry [bit 7] RWKIRE: Reactivation interrupt request permission It is a bit to set whether an interrupt is to be generated when the HOST function can be operational after resume operation has been completed. In host mode, to enter suspend status, write "1" to the SUSP bit in the host state status register. Only the host mode is effective. It is not initialized with the RST bit in the UDC control register (UDCC). RWKIRE Operation mode 0 Reactivation interrupt disable 1 Reactivation interrupt enable [bit 6] URIRE: USB bus reset interrupt request enable This bit sets whether an interrupt is to be generated when reset operation to the USB bus has been completed. Only the host mode is effective. It is not initialized with the RST bit in the UDC control register (UDCC). URIRE CM44-10129-6E Operation mode 0 Interrupt disabled after USB bus is reset 1 Interruption enable after USB bus is reset FUJITSU MICROELECTRONICS LIMITED 325 CHAPTER 14 USB HOST 14.4 Register of USB HOST MB90330A Series [bit 5] CMPIRE: Completion interrupt request enable It sets whether an interrupt is generated when a token has been completed. Only the host mode is effective. It is not initialized with the RST bit in the UDC control register (UDCC). CMPIRE Operation mode 0 Completion interrupt disabled 1 Completion interrupt enabled [bit 4] CNNIRE: Connection interrupt request enable It is a bit used to set whether an interrupt is generated when a connection is made to a device. Only the host mode is effective. It is not initialized with the RST bit in the UDC control register (UDCC). CNNIRE Operation mode 0 Interrupt disabled when device is connected 1 Interruption enable when device is connected [bit 3] DIRE: Disconnection interrupt request enable It is a bit used to set whether an interrupt is generated when a disconnection is made to a device. Only the host mode is effective. It is not initialized with the RST bit in the UDC control register (UDCC). DIRE Operation mode 0 Interrupt disabled when device is cut 1 Interruption enable when device is cut [bit 2] SOFIRE:SOF interrupt request enable It is a bit used to set whether an interrupt is generated when sending an SOF. Only the host mode is effective. It is not initialized with the RST bit in the UDC control register (UDCC). SOFIRE 326 Operation mode 0 Interrupt disabled when SOF is transmitted 1 Interrupt enabled when SOF is transmitted FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.4 Register of USB HOST MB90330A Series [bit 1] URST: USB bus reset It is set to USB bus whether reset is generated. It indicates "1" while the USB bus is being reset and turns "0" when it has been completed. It is forbidden to set it to "1" when the SUSP bit in the host state status register (HSTATE) is "1" or while a token is being executed. It is also forbidden to update the host control registers (HCNT0, HCNT1) while it is set to "1". Only the host mode is effective. To update them, you must set the RST bit in the UDC control register (UDCC) to "0". URST Operation mode 0 USB bus state maintenance 1 USB bus reset [bit 0] HOST: Host mode The LSI is set whether it is a function or HOST. Since it is not initialized due to the RST bit in the UDC control register (UDCC), change it when the RST bit is "1". And, if you change the mode from function mode to host mode, make a disconnection to the HOST PC or HUB by setting the HCON bit in the UDC control register (UDCC) to "1". If you change the mode from host mode to function mode, ensure that the SOFBUSY bit in the host status register (HSTATE) is set to "0" and the TKNEN bit in the host token endpoint register (HTOKEN) is 000B. HOST CM44-10129-6E Operation mode 0 Function mode 1 Host mode FUJITSU MICROELECTRONICS LIMITED 327 CHAPTER 14 USB HOST 14.4 Register of USB HOST 14.4.2 MB90330A Series Host Interruption Register (HIRQ) The host interrupt register (HIRQ) indicates for the interrupt request flag for USB HOST. It can allow an interrupt to be generated by setting the interrupt enable bit in the host control registers (HCNT0/HCNT1) except the TCAN bit. ■ Host Interruption Register (HIRQ) Figure 14.4-2 Bit Configuration of Host Interruption Register (HIRQ) Host interruption register bit 7 6 5 4 3 2 1 0 Address: 0000C2H TCAN Reserved RWKIRQ URIRQ CMPIRQ CNNIRQ DIRQ SOFIRQ → (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) (❍) (❍) (❍) (❍) (❍) ( ) ( ) (❍) Read/Write Initial value → Reset On/Off at UDCC RST bit → HIRQ [bit 7] TCAN: Token cancellation flag When the SOFIRQ bit in the host interrupt register (HIRQ) becomes "1", it indicates that a token is cancelled without being executed once. Any interrupt is not raised because the register is combined with interrupt due to SOF. To set it to "0", write "0" to it. To update them, you must set the RST bit in the UDC control register (UDCC) to "0". TCAN Operation mode 0 There is no token discontinuance. 1 There is token discontinuance. [bit 6] Reserved It is reserved bit. Be sure to set this bit to "0". [bit 5] RWKIRQ: Reactivation interrupt request It indicates that resume operation has been completed. When it becomes "1", it gets back to "0" by writing "0" to it. When you write "1" to it, the current state will be preserved. If the RWKIRE bit in the host control register 0 (HCNT0) is "1", an interrupt is generated when it is "1". The interrupt signal is cleared when it is cleared with "0". To update them, you must set the RST bit in the UDC control register (UDCC) to "0". RWKIRQ 328 Operation mode 0 There is no interrupt request by reactivation. 1 There is an interrupt request by reactivation. FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.4 Register of USB HOST MB90330A Series [bit 4] URIRQ: USB bus interrupt request It is shown that reset in USB bus ended. When it becomes "1", it gets back to "0" by writing "0" to it. When you write "1" to it, the current state will be preserved. If the URIRE bit in the host control register 0 (HCNT0) is "1", an interrupt is generated when it is "1". The interrupt signal is cleared when it is cleared with "0". To update them, you must set the RST bit in the UDC control register (UDCC) to "0". URIRQ Operation mode 0 There is no interrupt request by USB bus reset. 1 There is an interrupt request by USB bus reset. [bit 3] CMPIRQ: Completion interrupt request It is shown to have completed the token. It is not set to "1" when the TCAN bit in the host interrupt register (HIRQ) is "1". When it becomes "1", it gets back to "0" by writing "0" to it. When you write "1" to it, the current state will be preserved. If the CMPIRE bit in the host control register 0 (HCNT0) is "1", an interrupt is generated when it is "1". The interrupt signal is cleared when it is cleared with "0". To update them, you must set the RST bit in the UDC control register (UDCC) to "0". CMPIRQ Operation mode 0 There is no interrupt request by token completion. 1 There is an interrupt request by the token completion. [bit 2] CNNIRQ: Connected interrupt request It is shown to have detected the connection of the device. When it becomes "1", it gets back to "0" by writing "0" to it. When you write "1" to it, the current state will be preserved. If the CNNIRE bit in the host control register 0 (HCNT0) is "1", an interrupt is generated when it is "1". The interrupt signal is cleared when it is cleared with "0". It is not initialized with the RST bit in the UDC control register (UDCC). CNNIRQ CM44-10129-6E Operation mode 0 Interrupt request none by device connection detection. 1 Indicates interrupt request due to device connection detected. FUJITSU MICROELECTRONICS LIMITED 329 CHAPTER 14 USB HOST 14.4 Register of USB HOST MB90330A Series [bit 1] DIRQ: Cutting interrupt request It is shown to have detected cutting the device. When it becomes "1", it gets back to "0" by writing "0" to it. When you write "1" to it, the current state will be preserved. If the DIRE bit in the host control register 0 (HCNT0) is "1", an interrupt is generated when it is "1". The interrupt signal is cleared when it is cleared with "0". It is not initialized with the RST bit in the UDC control register (UDCC). DIRQ Operation mode 0 There is no interrupt request by device cutting detection. 1 There is interrupt request by device cutting detection. [bit 0] SOFIRQ: SOF interruption requests Whether the SOF token was begun is shown. When it becomes "1", it gets back to "0" by writing "0" to it. When you write "1" to it, the current state will be preserved. If the SOFIRE bit in the host control register 0 (HCNT0) is "1", an interrupt is generated when it is "1". The interrupt signal is cleared when it is cleared with "0". To update them, you must set the RST bit in the UDC control register (UDCC) to "0". SOFIRQ 330 Operation mode 0 There is no interrupt request by SOF token beginning. 1 There is an interrupt request by the SOF token beginning. FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.4 Register of USB HOST MB90330A Series 14.4.3 Host Error Status Register (HERR) The host error status register (HERR) is a register that indicates whether an error occurs or not when sending or receiving data in host mode. ■ Host Error Status Register (HERR) Figure 14.4-3 Bit Configuration of Host Error Status Register (HERR) Host error status register bit Address: 0000C3H Read/Write → Initial value → Reset On/Off at UDCC RST bit → 15 14 13 12 11 10 9 8 LSTSOF RERR TOUT CRC TGERR STUFF HS (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (11B) (❍) (❍) (❍) (❍) (❍) (❍) (❍) HERR [bit 15] LSTSOF:SOF execution error It indicates that an SOF token could not be executed because another token was running when you tried to execute it in host mode. Please do "0" in the writing to clear "1". To update them, you must set the RST bit in the UDC control register (UDCC) to "0". LSTSOF Operation mode 0 SOF execution 1 SOF execution error [bit 14] RERR: Receive error It indicates whether data more than a maximum number of packets set was received in host mode. When the reception error occurs, TOUT is set in "1". Please do "0" in the writing to clear "1". To update them, you must set the RST bit in the UDC control register (UDCC) to "0". RERR CM44-10129-6E Operation mode 0 No receive error 1 The maximum packet reception error FUJITSU MICROELECTRONICS LIMITED 331 CHAPTER 14 USB HOST 14.4 Register of USB HOST MB90330A Series [bit 13] TOUT: Time-out It indicates whether time-out was generated. If "1" is cleared, write "0" to this bit. The bit is updated after the RST bit of the UDC control register (UDCC) is set to "0". TOUT Operation mode 0 There is no time-out. 1 There is a time-out. [bit 12] CRC:CRC error It is shown whether the CRC error occurred at the host mode. When the CRC error occurs, TOUT is set in "1". Please do "0" in the writing to clear "1". To update them, you must set the RST bit in the UDC control register (UDCC) to "0". CRC Operation mode 0 There is no CRC error. 1 There is a CRC error. [bit 11] TGERR: Toggle error In indicates whether an toggle error occurs in host mode. Please do "0" in the writing to clear "1". To update them, you must set the RST bit in the UDC control register (UDCC) to "0". TGERR Operation mode 0 There is no toggle error. 1 There is a toggle error. [bit 10] STUFF: Stuffing error It indicates whether a stuffing error happens in host mode. TOUT is also set to "1" when a stuffing error occurs. Please do "0" in the writing to clear "1". To update it, you must set the RST bit in the UDC control register (UDCC) to "0". 332 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.4 Register of USB HOST MB90330A Series [bit 9, bit 8] HS: Handshake status It indicates the status of handshake operations between transmission and reception in host mode. It indicates NULL when handshake operation is not performed due to any reasons such as an error and the SOF token is completed. It is updated when transmission or reception has been completed. To update them, you must set the RST bit in the UDC control register (UDCC) to "0". Table 14.4-1 Handshake HS Handshake CM44-10129-6E bit9 bit8 0 0 ACK 0 1 NAK 1 0 STALL 1 1 NULL FUJITSU MICROELECTRONICS LIMITED 333 CHAPTER 14 USB HOST 14.4 Register of USB HOST 14.4.4 MB90330A Series Host State Status Register (HSTATE) The host state status register (HSTATE) is a register that indicates the status of the USB circuit such as connections to devices and transfer mode. Note that the CLKSEL bit is also enabled in the function mode. ■ Host State Status Register (HSTATE) Figure 14.4-4 Bit Configuration of Host State Status Register (HSTATE) Host state status register bit 7 Address: 0000C4H Reserved 6 5 4 3 2 1 0 Reserved ALIVE CLKSEL SOFBUSY SUSP TMODE CSTAT → (-) (-) (R/W) (R/W) (R/W) (R/W) (R) (R) Initial value → (x) (x) (0) (1) (0) (0) (1) (0) Reset On/Off at UDCC RST bit → (-) (-) ( ) ( ) (❍) (❍) ( ) Read/Write HSTATE ( ) [bit 7, bit 6] Reserved It is reserved bits. The reading is undefined. The writing does not influence the operation. [bit 5] ALIVE: Keep-Alive function setting It is a bit that sets the Keep-Alive function in Low Speed. If you set it to "1" when the CLKSEL bit in the host state status register (HSTATE) is "0", SE0 is will be output instead of an SOF. If it is enabled when the CLKSEL bit in the host state status register (HSTATE) is "0", and the CLKSEL becomes "1", an SOF will be output regardless of the setting of the ALIVE bit. ALIVE Operation mode 0 SOF 1 SE0 output (Keep-Alive) [bit 4] CLKSEL: Clock selection The operation clock of USB is selected. You must set it to "1" for Full Speed, and to "0" for Low Speed. You must switch clock when the RST bit in the UDC control register (UDCC) is "1" and both the function mode and host mode are enabled. "0" setting at the function mode is a interdiction. CLKSEL 334 Operation mode 0 Clock for Low Speed 1 Clock for Full Speed FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.4 Register of USB HOST MB90330A Series [bit 3] SOFBUSY:SOF timer operation It indicates whether the SOF timer is operating in host mode. Sending SOF stops when "0" is done in the writing. To update them, you must set the RST bit in the UDC control register (UDCC) to "0". SOFBUSY Operation mode 0 SOF timer is stop. 1 SOF timer is working. [bit 2] SUSP: Suspend It is a bit used to set suspend status in host mode. Writing "1" to the bit enables suspend status. When you write "0" to the bit that holds "1" or the USB bus changes to k-state status, the suspend status is deselected, the RWKIRQ bit in the host interrupt register (HIRQ) is "1". When connection or disconnection is detected if the SUSP bit is "1", you must write "0" to the bit. Then, when disconnection or connection is detected and the SUSP bit is cleared, the RWKIRQ bit in the host interrupt register (HIRQ) is set to "1" twice, and overwrite the RWKIRQ bit with "1" when it is set to "1". It is forbidden to set the bit to "1" while the USB is operating (such as resetting the USB bus or sending/receiving data). In host mode, it is forbidden to stop the USB clock even in suspend status. To update it, you must set the RST bit in the UDC control register (UDCC) to "0" and are prohibited to set it to "1" in function mode. In addition, if it is "1" when you change the mode from host mode to function mode, you must get out of suspend status by writing "0" into it before changing the mode. Table 14.4-2 Suspend Setting SUSP Operation "1" Write Suspend They are "0" writing at "1" state. Resume The others State maintenance [bit 1] TMODE: Transfer mode The transfer mode at the host mode is shown. Write "1" for the write operation. It is not initialized with the RST bit in the UDC control register (UDCC). Please use the CPU clock at 24 MHz. TMODE CM44-10129-6E Operation mode 0 Low Speed 1 Full Speed FUJITSU MICROELECTRONICS LIMITED 335 CHAPTER 14 USB HOST 14.4 Register of USB HOST MB90330A Series [bit 0] CSTAT: Connected state It is whether the device is connected is shown. The pin for HOST becomes an object. It is not initialized with the RST bit in the UDC control register (UDCC). CSTAT 336 Operation mode 0 Device cut off 1 Device connect FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.4 Register of USB HOST MB90330A Series 14.4.5 SOF Interruption FRAME Comparison Register (HFCOMP) The SOF interrupt FRAME comparison register (HFCOMP) is a register used to set data that is compared with the lower 8 bits of FRAME Number for SOF token. If the lower 8 bits of FRAME Number is compared with the HFCOMP register and a match is detected with the SOFIRE bit in host control register 0 (HCNT0) set to "1", an interrupt will be generated by setting the SOFIRQ bit in the host interrupt register (HIRQ) to "1" when starting SOF transmission. ■ SOF Interruption FRAME Comparison Register (HFCOMP) Figure 14.4-5 Bit Configuration of SOF Interruption FRAME Comparison Register (HFCOMP) SOF interruption FRAME comparison register bit 15 14 13 Address: 0000C5H 12 11 10 FRAMECOMP Read/Write → (R/W) Initial value → (00000000B) Reset On/Off at UDCC RST bit → 9 8 HFCOMP ( ) [bit 15 to bit 8] FRAMECOMP It sets data that is to be compared with the lower 8 bits of Frame Number. It is not initialized with the RST bit in the UDC control register (UDCC). To update them, you must set the RST bit in the UDC control register (UDCC) to "0". CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 337 CHAPTER 14 USB HOST 14.4 Register of USB HOST 14.4.6 MB90330A Series Retry Timer Setting Register (HRTIMER) The retry timer setting register (HRTIMER) is a register used to set a retry time period for a token. ■ Retry Timer Setting Register (HRTIMER) Figure 14.4-6 Bit Configuration of Retry Timer Setting Register (HRTIMER) Retry timer setting register bit 7 6 5 4 Address: 0000C6H Read/Write 3 HRTIMER (00000000B) Reset On/Off at UDCC RST bit → ( ) 15 14 13 12 Address: 0000C7H 11 10 9 8 RTIMER1 → HRTIMER (R/W) Initial value → (00000000B) Reset On/Off at UDCC RST bit → bit 0 (R/W) Initial value → Read/Write 1 RTIMER0 → bit 2 ( ) 7(23) 6(22) Address: 0000C8H 5(21) 4(20) 3(19) 2(18) 1(17) 0(16) Reserved RTIMER2 → (-) (R/W) Initial value → (x) (00B) Reset On/Off at UDCC RST bit → (-) ( ) Read/Write HRTIMER [bit 23 to bit 18] Reserved These are reserved bits. The reading is undefined. The writing does not influence the operation. [bit 17 to bit 0] HRTIMER0, HRTIMER1, HRTIMER2 These bits set a time to retry a token. When the RETRY bit of the host control register (HCNT1) is "1", a retry timer is activated after the token is started, and the timer is decremented by "1" due to 1-bit transfer clock (12 MHz at Full Speed). When the retry timer becomes "0", token retry dose not execute. When the token retry occurs in an EOF area, the retry timer stops until the SOF is completed. The timer value that was stopped is decremented by 1 after the SOF is executed. It is not initialized with the RST bit in the UDC control register (UDCC). To update them, you must set the RST bit in the UDC control register (UDCC) to "0". 338 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.4 Register of USB HOST MB90330A Series 14.4.7 Host Address Register (HADR) The host address register (HADR) is a register used for an address field when a token is sent. ■ Host Address Register (HADR) Figure 14.4-7 Bit Configuration of Host address Register (HADR) Host address register bit 15 14 13 Address: 0000C9H Reserved 12 11 Address → (-) (R/W) Initial value → (x) (0000000B) Reset On/Off at UDCC RST bit → (-) ( ) Read/Write 10 9 8 HADR [bit 15] Reserved It is reserved bit. The reading is undefined. The writing does not influence the operation. [bit 14 to bit 8] Address: Address The address of the token is set. It is not initialized with the RST bit in the UDC control register (UDCC). To update them, you must set the RST bit in the UDC control register (UDCC) to "0". CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 339 CHAPTER 14 USB HOST 14.4 Register of USB HOST 14.4.8 MB90330A Series EOF Setting Register (HEOF) The EOF setting register (HEOF) is a register that sets a time period for which a token is inhibited before the execution of the SOF token. If the data of the SOF timer turns out to be lower than data in the HEOF register as a result of comparing both, and any of an IN token, OUT token, and SETUP token execution requests is made, it will be run after the SOF token is executed. This prevents an SOF token generated by hardware and other tokens from being simultaneously executed. The unit of time for the HEOF register is one-bit transfer time. ■ EOF Setting Register (HEOF) Figure 14.4-8 Bit Configuration of EOF Setting Register (HEOF) EOF setting register bit 7 6 5 4 3 Address: 0000CAH EOF0 → (R/W) Read/Write Initial value → Address: 0000CBH 0 HEOF ( ) 15 14 13 12 11 10 Reserved EOF1 → (-) (R/W) Initial value → (x) (000000B) Reset On/Off at UDCC RST bit → (-) ( ) Read/Write 1 (00000000B) Reset On/Off at UDCC RST bit → bit 2 9 8 HEOF [bit 15, bit 14] Reserved These are reserved bits. The reading is undefined. The writing does not influence the operation. [bit 13 to bit 0] EOF1,EOF0:EOF Set a time period during which the execution of a token is inhibited before the execution of SOF. Set a margin that is longer than one packet length. The unit is one bit forwarding time. It is not initialized with the RST bit in the UDC control register (UDCC). To update them, you must set the RST bit in the UDC control register (UDCC) to "0". For the MAXPKT=64 byte and Full Speed of set example (Token_length + packet_length + header + CRC)×7/6 + Turn_around_time =(34bit + 546bit)×7/6 + 36bit = 712.7bits As the above is true, specify 2C9H. 340 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.4 Register of USB HOST MB90330A Series 14.4.9 FRAME Setting Register (HFRAME) The FRAME setting register (HFRAME) is a register that sets a FRAME Number in handling SOF tokens. When you set the TKNEN bits of the host token endpoint register (HTOKEN) to SOF activation, the SOF timer starts and, afterwards, an SOF is automatically sent out every 1 ms. The FRAME setting register is automatically incremented by 1 every time an SOF is completed. ■ FRAME Setting Register (HFRAME) Figure 14.4-9 Bit Configuration of FRAME Setting Register (HFRAME) FRAME setting register bit 7 6 5 4 Address: 0000CCH Read/Write 1 HFRAME (00000000B) (❍) Reset On/Off at UDCC RST bit → 15 14 13 12 11 10 9 Reserved FRAME1 → (-) (R/W) Initial value → (x) (000B) Reset On/Off at UDCC RST bit → (-) (❍) Read/Write 0 (R/W) Initial value → Address: 0000CDH 2 FRAME0 → bit 3 8 HFRAME [bit 15 to bit 11] Reserved These are reserved bits. The reading is undefined. The writing does not influence the operation. [bit 10 to bit 0] FRAME1, FRAME0 Frame Number is set. Before setting the TKNEN bits of the host token endpoint register (HTOKEN) to SOF, set Frame Number. Furthermore, when the SOFBUSY bit of the host status register (HSTATE) is "1" and an SOF token is being executed, write operation is inhibited. To update them, you must set the RST bit in the UDC control register (UDCC) to "0". CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 341 CHAPTER 14 USB HOST 14.4 Register of USB HOST 14.4.10 MB90330A Series Host Token Endpoint Register (HTOKEN) The host token endpoint register (HTOKEN) is a register that sets a toggle, endpoint, and token. ■ Host Token Endpoint Register (HTOKEN) Figure 14.4-10 Bit Configuration of Host Token Endpoint Register (HTOKEN) Host token end point register bit 7 6 5 4 3 2 1 Address: 0000CEH TGGL TKNEN ENDPT → (R/W) (R/W) (R/W) (0) (000B) (0000B) (❍) (❍) (❍) Read/Write Initial value → Reset On/Off at UDCC RST bit → 0 HTOKEN [bit 7] TGGL: Toggle This bit sets toggle data. At transmission, the toggle data is sent according to the bit. At reception, the received toggle data is compared to the toggle data which the bit shows and use at the error detection. The bit is updated after the RST bit of the UDC control register (UDCC) is set to "0" and the TKNEN bit to 000B. TGGL Operation Mode 0 Data 0 1 Data 1 [bit 6 to bit 4] TKNEN: Token permission These bits send a token corresponding to the setting. After the operation is completed TKNEN = 000B, the CMPIRQ bit of the host interrupt register (HIRQ) is set to "1". At that time, if the CMPIRE bit of the host control register 0 (HCNT0) is "1", an interrupt generates. The TGGL and ENDPT bits are ignored during the SOF token. To write to the TKNEN bits, you must set the RST bit in the UDC control register (UDCC) to "0" and turn the mode to host mode. In addition, if you issue a token again because an interrupt due to a token is generated, you must wait three cycles or longer in terms of USB transfer clock (12 MHz for Full Speed and 1.5 MHz for Low Speed) before writing to the TKNEN bits. Note that writing to the TKNEN bits will not run a token in disconnection status (HSTATE CSTAT= 0). 342 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.4 Register of USB HOST MB90330A Series Table 14.4-3 Token Setting bit6 bit5 bit4 Operation 0 0 0 No send out 0 0 1 SETUP is sent 0 1 0 IN is sent. 0 1 1 OUT is sent. 1 0 0 SOF is sent. 1 0 1 Reserved (Set prohibition) 1 1 0 Reserved (Set prohibition) 1 1 1 Reserved (Set prohibition) Note: The PRE packet is not supported. When the SOFBUSY bit in the host state status register (HSTATE) is "1", setting TKNEN = 100B respectively, is forbidden. [bit 3 to bit 0] ENDPT: end point The transmitted and received endpoint to the device is set. To update them, you must set the RST bit in the UDC control register (UDCC) to "0". CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 343 CHAPTER 14 USB HOST 14.5 Operation of USB HOST 14.5 MB90330A Series Operation of USB HOST The operation of USB HOST is explained. ■ Operation of USB HOST ● Connection of device The software detects that the external USB device was connected. ● Reset of USB bus USB bus is reset. ● Token packet Three kinds of tokens can be selected at the host mode. ● Data packet The data packet is transmitted and received. ● Handshake packet It informs send/receive partners of status via handshake packet. ● Retry function When an error etc. occur at the packet termination, the retry operation is continued. ● SOF INTERRUPT The interruption is generated. ● Error status Various errors are displayed. ● Packet end When the packet ends, the interruption is generated. ● Suspend-resume It puts the USB circuit in suspend-resume status. ● Cutting of device The detection of the status of HOST pins determines the disconnection. 344 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.5 Operation of USB HOST MB90330A Series 14.5.1 Connection of Device The method for detecting the connection of the external USB device by software is described. ■ Setting of HOST Function To make it operate as a host of the USB device, set the HOST bit of the host control register 0 (HCNT0) to "1". ■ Disconnection Status, Connection Status of the External USB Device When the external USB device is disconnected, both HOST pins, D + and D-, are "L" by the pull-down resistor. Then, the CSTAT bit in the host state status register (HSTATE) is "0", and the TMODE bit is indefinite. The CSTAT bit of the host state status register (HSTATE) becomes "1" when the external USB device is connected. ■ Connected Detection of External USB Device To detect the connection of the external USB device, set the CNNIRE bit of the host control register 0 (HCNT0) to "1". The CNNIRQ bit of the host interrupt register (HIRQ) becomes "1", and a device connection interrupt is generated. To clear this interrupt, write "0" to the CNNIRQ bit of the host interrupt register (HIRQ). To detect the connection of the external USB device not through interrupt but through polling, create a program so that it ensures that the CNNIRE bit of the host control register 0 (HCNT0) is set to "0" and the CNNIRQ bit of the host interrupt register (HIRQ) is "1". ■ Acquiring Transfer Speed of Destination USB Device and Selecting Clock To acquire the transfer speed of a destination USB after detecting the connection, make reference to the value of the TMODE of the host state status register (HSTATE). The relation between the transfer speed and the TMODE bit of the host state status register (HSTATE) is as follows: • When a destination device is a Full Speed-enabled device → TMODE= 1 • When a destination device is a Low Speed-enabled device → TMODE= 0 After the transfer speed of the external USB device is acquired, when the RST bit of the UDC control register (UDCC) is "1", update the CLKSEL bit of the host state status register (HSTATE) based on the acquired transfer speed. The relation between the TMODE and CLKSEL bits of the host status register (HSTATE) is as follows: • TMODE = 1 → "1" is set to CLKSEL bit. • TMODE = 0 → "0" is set to CLKSEL bit. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 345 CHAPTER 14 USB HOST 14.5 Operation of USB HOST MB90330A Series Figure 14.5-1 Connecting Detection Timing Example of Speed Device (HCNT0 Bit 0 = 0) Device connection Pin D+ for HOST Pin D- for HOST 2.5μs CSTAT bit of HSTATE TMODE bit of HSTATE Indeterminate CNNIRQ bit of HIRQ "0" HOST bit of HCNT Note: The CSTAT bit of the host state status register (HSTATE) becomes "1" in 2.5 μs after the connection of the external USB device. The TMODE and CSTAT bits of the host state status register (HSTATE) are updated regardless of the setting of the HOST bit in the host control register 0 (HCNT0). 346 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.5 Operation of USB HOST MB90330A Series 14.5.2 Reset of USB Bus When you set the URST bit of the host control register 0 (HCNT0) to "1" in the host mode, it sends out SE0 for not less than 10 ms and resets the USB bus. When the USB bus has been reset, it sets back the URST bit of the host control register to "0" and generates an interrupt and the URIRQ bit of the host interrupt register (HIRQ) is set to "1" when the URIRE bit of the host control register 0 (HCNT0) is "1." If you clear the interrupt, write "0" to the URIRQ bit of the host interrupt register (HIRQ). ■ Notes before and after Reset of USB Bus Please note the following points about reset of USB bus. 1. Before the USB bus is reset, confirm that the device is connected to and the CSTAT bit of the host state status register (HSTATE) is set to "1". 2. When you reset the USB bus, the CSTAT bit of the host state status register (HSTATE) turns to "0" and the USB device is put into disconnection status. Then, the DIRQ bit of the host interrupt control register (HIRQ) does not become "1". 3. After the USB bus is reset, you must update the CLKSEL bit of the host state status register (HSTATE) to match the TMODE bit of the same register if you compare them and they do not match. Before you update the CLKSEL bit, ensure that the RST bit of the UDC control register (UDCC) is "1". Figure 14.5-2 Reset Timing Example to Device Pin D + for HOST Pin D - for HOST URST bit of HCNT CSTAT bit of HSTATE URIRQ bit of HIRQ (HCNT URIRE=1) Write "1" to URST bit of HCNT CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 347 CHAPTER 14 USB HOST 14.5 Operation of USB HOST 14.5.3 MB90330A Series Token Packet If you execute any of an IN token, OUT token, and SETUP token in the host mode, a token packet is started when you set necessary data in the host token register (HTOKEN) after you set the PKS bit of the EP1 control register (EP1C) or EP2 control register (EP2C) based on the host address register (HADR) and the DIR bit in EP1C. In handling an SOF token, you must set necessary data in the host token register (HTOKEN) after configuring the FRAME setting register (HFRAME) and EOF setting register (HEOF). If registers (HADR, EP1C, EP2C, HFRAME, and HEOF) have not been changed, setting them is not required. ■ Setting of Token Packet For the IN token, OUT token, and SETUP token, set the destination address to the host address register (HADR), and set the maximum bytes of one packet to the PKS bit of the EP1 control register (EP1C) or the EP2 control register based on the token to be executed and the DIR bit of the EP1 control register. If the DIR bit of the EP1 control register (EP1C) is "1", the buffer for endpoint 1 is used as an OUTdirection buffer and the one for endpoint 2 is used as an IN- direction buffer. Then, set the DIR bit of the EP2 control register (EP2C) to "0". If the DIR bit of the EP1 control register (EP1C) is "0", the buffer for endpoint 1 is used as an IN- direction buffer and the one for endpoint 2 is used as an OUT- direction buffer. Then, set the DIR bit of the EP2 control register (EP2C) to "1". If you want to use the buffer for endpoint 1, you must ensure that the DRQ bit of EP1 status register (EP1S) is set to "0" and if you want to use the buffer for endpoint 2, you must ensure that the DRQ bit of EP2 status register (EP2S) is set to "1," before setting the target endpoint, token, and toggle data in the host token endpoint register (HTOKEN). The USB circuit sends out a token packet in the order of a Sync, token, address, endpoint, CRC5, and EOP based on the specified token (a Sync, CRC5, and EOP are automatically sent). After one packet is ended, the CMPIRQ bit of the host interrupt register (HIRQ) becomes "1", and the TKNEN bit of the host token endpoint register (HTOKEN) is set to 000B (See Section "14.5.7 SOF Interrupt"). At that time, if the CMPIRE bit of the host control register 0 (HCNT0) is "1", an interrupt occurs. To clear the interrupt, write "0" to the CMPIRQ bit of the host interrupt register (HIRQ). Figure 14.5-3 Example of Register Setting until Execution of IN/OUT/SETUP Token Write to HADR (when a change is required) Write to EP1C or EP2C (when a change is required) Write to HTOKEN Register write signal Confirm the status of the buffer for endpoint 1/endpoint 2 In the case of an SOF token, when you set an EOF time and FRAME number in the EOF setting register (HEOF) and FRAME setting register (HFRAME), and write the code of the SOF token to the TKNEN bits of the host token endpoint register (HTOKEN), a Sync, SOF token, FRAME number, CRC5, and EOP will be sent out and the SOFBUSY bit of the host state status register (HSTATE) is set to "1" and HFRAME is 348 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.5 Operation of USB HOST MB90330A Series incremented by 1. In this case, the CMPIRQ of the host interrupt register (HIRQ) is also set to "1", and the TKNEN bit of the host token endpoint register (HTOKEN) is cleared to 000B. When the CMPIRE bit of host control register (HCNTO) is "1", an interrupt occurs. Then, when the SOF that generates automatically is used, the interrupt by the CMPIRQ does not occur. To clear the interrupt of the token completion, write "0" to the CMPIRQ of the HIRQ. SOF is automatically sent out every 1 ms while the SOFBUSY bit of the host state status register (HSTATE) is "1". The conditions (SOF stop conditions) that make the SOFBUSY bit of the host state status register (HSTATE) "0" are as follows: "0" write to SOFBUSY bit of host state register (HSTATE) Reset ("1" write to URST bit of HCNT) in USB bus "1" write to SUSP bit of host state status register (HSTATE) Cutting of the device (For "0" the CSTAT bit of HSTATE). To switch from host mode to function mode, first, ensure that the SOFBUSY bit of the host state status register (HSTATE) is "0" after writing "0" to it. If you want to set back the SOFBUSY bit of the host state status register (HSTATE) to "1" again, you need to run an SOF token once again. To prevent the simultaneous executions of an SOF token and other tokens, the EOF setting register is used to run a token you have set after making it wait for the end of SOF execution if you write to the TKNEN bits of the host token endpoint register (HTOKEN) in a time period from the EOF setting time to SOF start time. The unit of time for the EOF setting register is one-bit time. For example, when setting 10H to the EOF setting register, the following time is required: 16×1/12 MHz = 13333.3 ns in Full speed mode and 16×1/1.5 MHz = 10666.6 ns in Low speed mode. If the EOF set time is shorter than one packet time, the SOF execution max overlap other token execution. In this case, the LSTOF bit of host error status register (HERR) is set to "1", the SOF is not executed. When the LSTOF bit of the host error status register (HERR) is set to "1", you must increase data of the EOF setting register. (See Section "14.4.8 EOF Setting Register (HEOF)") Figure 14.5-4 SOF Timing SOF start SOF start EOF set time EOF set time 1ms EOF >1 packet time CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 349 CHAPTER 14 USB HOST 14.5 Operation of USB HOST 14.5.4 MB90330A Series Data Packet If a data packet is transmitted after a token packet has been sent, toggle data will be transmitted based on the TGGL bit of the host token endpoint register (HTOKEN), and the buffer data for endpoint 1 or endpoint 2 according to the DIR bit of the EP1 control register (EP1C), CRC16 data, and EOP is sent. In the case of receiving a data packet, the TGGL bit of the host token endpoint register (HTOKEN) and received toggle data are compared, and, if they match, the received data is written to the buffer for endpoint 1 or endpoint 2 based on the DIR bit of the EP1 control register (EP1C) and the CRC16 is checked for an error. ■ Data Packet After sending a token packet, the data packet is executed in the following procedure: ● At Transmission • Automatic sending of Sync • DATA0 is transmitted when the TGGL bit of the host token endpoint register (HTOKEN) is "0" and DATA1 is transmitted when the TGGL bit is "1". • The buffer for endpoint 1 is selected when the DIR bit of the EP1 control register (EP1C) is "1" and otherwise the one for endpoint 2 is selected when the DIR bit is "0" and all transmit data is sent. • The CRC16-bit is sent. • The EOP 2-bit is sent. • The J State 1-bit is sent. ● At Reception • Reception of Sync • The toggle data is received, and is compared with the TGGL bit of the host token endpoint register (HTOKEN). • If they match as a result of the comparison, the buffer for endpoint 2 is selected when the DIR bit of the EP1 control register (EP1C) is "1" and the one for endpoint 0 is selected when the DIR bit is "0" and the received data is written into it. • When the EOF is received, the CRC16 bit is inspected. You must set inversion data, respectively, in the DIR bits of the EP1 control register (EP1C) and EP2 control register (EP2C) when the HOST bit of the host control register 0 (HCNT0) is "1". For example, when the DIR bit of the EP1 control register (EP1C) is "0", the DIR bit of the EP2 control register (EP2C) is set to "1". 350 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.5 Operation of USB HOST MB90330A Series 14.5.5 Handshake Packet Transmission/reception partner must be informed of your own status via handshake packet. ■ Handshake Packet The reception side transmits one of ACK, NAK, and STALL when it determines through handshake packet whether it can receive data properly or the endpoint supports it. Then, when the USB circuit receives a handshake packet, the received handshake packet is set to the HS bit of the host error status register (HERR). When the handshake packet is transmitted, the transmitted handshake packet is set to the HS bit of the host error status register (HERR). CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 351 CHAPTER 14 USB HOST 14.5 Operation of USB HOST 14.5.6 MB90330A Series Retry Function At the termination of the packet, when NAK or an error such as CRC error occurs, and the RETRY bit of the host control register 1 (HCNT1) is "1", it continues to retry during a time period set in the retry timer register (HRTIMER). ■ Retry Function If an error except STALL and disconnected device happens, it retries to process the token when the RETRY bit of the host control register 1 (HCNT1). The end condition of retry "0" setting of RETRY bit of host control register 1(HCNT1) • Detecting 0 in the retry timer • Occurrence of an interrupt due to SOF (SOFIRE= 1 of HCNT0 and SOFIRQ= 1 of HIRQ) • Detection of ACK • Detection of cutting device The retry timer is activated when the process of a token is started, counts down with one-bit transfer clock, and stops counting when a retry happens in an EOF area. The retry timer restarts at the value when the timer stopped if the SOFIRQ bit of HIRQ was "0". The SOF token was completed, and when the timer counts down to "0" and a packet ends, any retry request it receives is cancelled and the packet will be terminated. Figure 14.5-5 Retry Timer Operation (SOFIRQ of HIRQ = 0) Token beginning EOF SOF retry Token execution Timer countdown Timer stop Timer restart Retry generation When the retry operation is completed, end information on the completed packet is set in related registers. 352 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.5 Operation of USB HOST MB90330A Series 14.5.7 SOF Interrupt Once you have set the SOFIRE bit of the host control register 0 (HCNT0) to "1", it sets the SOFIRQ bit of the host interrupt register (HIRQ) to "1" and will generate an interrupt when starting an SOF with the SOFSTEP bit of the host control register 1 (HCNT1) and the SOF interrupt FRAME comparison register (HFCOMP). The SOF execution with the host token endpoint register (HTOKEN) does not set the SOFIRQ bit of the host interrupt register (HIRQ) to "1". ■ SOF Interrupt Once you have set the SOFIRE bit in host control register 0 (HCNT0) to "1", an interrupt is generated when sending an SOF, and the SOFIRQ bit in the host interrupt register (HIRQ) is set to "1". You can select one of an SOF interrupt conditions: One is generation of an SOF interrupt every time an SOF is sent out with the setting of the SOFSTEP bit of the host control register 1 (HCNT1) and another generation is due to the Frame number in the lower 8 bits indicated by the SOF interrupt FRAME comparison register (HFCOMP). Figure 14.5-6 SOF Interrupt For " 1 " the SOFSTEP bit of host control register 1(HCNT1) following SOF transmission The SOF transmission SOFIRQ bit of HIRQ Soft clear Soft clear For " 0 " the SOFSTEP bit of host control register 1(HCNT1) following SOF transmission The SOF transmission HFRAME HFCOMP 010 H 011H 011H SOFIRQ bit of HIRQ HFRAME lower 8 bit and HFCOMP is corresponding. If you set the CANCEL bit of the host control register 1 (HCNT1) to "1" and set a token other than an SOF token in the host token endpoint register (HTOKEN) in the EOF area, and the SOFIRQ bit of the host interrupt register (HIRQ) is set to "1" in the next SOF, the token is not executed and the TKNEN bits of the HTOKEN are set to 000B. Then, the CMPIRQ bit of the host interrupt register (HIRQ) does not become "1". Canceling the token can be known by the TCAN bit of the HIRQ when the SOFIRQ bit becomes "1". If you execute the token again, write "0" to the TCAN bit of the HIRQ, and write the token to be executed to the TKNEN bit of HTOKEN. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 353 CHAPTER 14 USB HOST 14.5 Operation of USB HOST MB90330A Series If you set the CANCEL bit of host control register 1 (HCNT1) to "0", the token set in the host token endpoint register (HTOKEN) is executed after the SOF is sent. Figure 14.5-7 Example of Token Cancel Operation when CANCEL Bit of HCNT1 is "1". IN TOKEN write EOF area SOF execution SOFIRQ bit of HIRQ TKNEN bit of HTOKEN 000B 010B 000B CMPIRQ bit of HIRQ "0" Figure 14.5-8 Example of Token Cancel Operation when CANCEL Bit of HCNT1 is "0". IN TOKEN write EOF area SOF execution IN TOKEN execution SOFIRQ bit of HIRQ TKNEN bit of HTOKEN 000B 010B 000B CMPIRQ bit of HIRQ 354 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.5 Operation of USB HOST MB90330A Series 14.5.8 Error Status USB HOST supports various error information. ■ Error Status ● Stuffing error If continuous 6 bits happen to be "1", one bit of "0" should be inserted in somewhere in the sequence, but the STUFF bit of the host error status register (HERR) is set to "1" as a stuffing error if continuous 7 bits of "1" are detected. Please do "0" to the STUFF bit in the writing to clear this. If the next token is executed without clearing the STUFF bit, it is updated at the termination of the next token. ● Toggle error When receiving an IN token, the TGERR bit in the host error register (HERR) is set to "1" if the toggle data for the data packet and the TGGL bit of the host token endpoint register (HTOKEN) are compared and a match is not detected. To clear the TGERR bit, write "0" to it of the host error register (HERR). If the next token is executed without clearing the TGERR bit, it is updated at the termination of the next token. ● CRC error When receiving an IN token, data in the received data packet and CRC are calculated with the CRC polynomial G(X)=X16+X15+X2+1, and if the remainder is not 800DH, then a CRC error is assumed to happen and the CRC bit of the host error register (HERR) is set to "1". To clear the CRC bit, write "0" to it of the host error register (HERR). If the next token is executed without clearing the CRC bit, it is updated at the termination of the next token. ● Time-out error The TOUT bit of the host error status register (HERR) is set to "1" if a data packet or handshake is not received in a given time, SE0 is detected in received data, or a stuffing error is detected. To clear the TOUT bit, write "0" to it of the host error register (HERR). If the next token is executed without clearing the TOUT bit, it is updated at the termination of the next token. ● Receive error If EP1 or EP2 is used as the reception buffer, the PKS bit of the EP1 control register (EP1C) or EP2 control register (EP2C), respectively. If the received data is greater than that of the received packet size, the RERR bit of the host error status register (HERR) is set to "1". To clear the RERR bit, write "0" to it of the host error register (HERR). If the next token is executed without clearing the RERR bit, it is updated at the termination of the next token. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 355 CHAPTER 14 USB HOST 14.5 Operation of USB HOST 14.5.9 MB90330A Series Packet End When one packet terminates in USB HOST, if the CMPIRE bit of the host control register 0 (HCNT0) is "1", an interrupt is generated to set the CMPIRQ bit of the host interrupt register (HIRQ) to "1". ■ Packet End Timing When one packet terminates, an interrupt is generated in the following timing: When the TKNEN bits of the host token end point register (HTOKEN) are 001B, 010B or 011B (SETUP token, IN token, and OUT token) Figure 14.5-9 CMPIRQ Bit Set Timing Example 1 of HOST Interrupt Register (HIRQ) To the TKNEN bit of HTOKEN Write Token packet J-ST Sync handshake packet data packet TKN ADR ENDPT CRC5 EOP J-ST Sync TGGL DATA CRC16 CMPIRQ bit (HIRQ) EOP J-ST Sync ACK EOP J-ST J-ST : J State TKN : Token ADR : Address ENDPT : Endpoint TGGL : Toggle When the TKNEN bit of the host token end point register (HTOKEN) is 100B (SOF token) Figure 14.5-10 CMPIRQ Bit Set Timing Example 2 of HOST Interrupt Register (HIRQ) (SOF TOKEN) To the TKNEN bit of HTOKEN Write J-ST Sync TKN FRAME CRC5 EOP J-ST CMPIRQ bit (HIRQ) J-ST :J State TKN :Token FRAME :Frame Number 356 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.5 Operation of USB HOST MB90330A Series 14.5.10 Suspend Resume USB HOST supports suspend and resume operations. ■ Suspend Operation When writing "1" to the SUSP bit of the host state status register (HSTATE), • USB bus high impedance state • Stop of circuit block where clock is not necessary USB HOST follows the steps above, and puts the USB circuit in suspend status. When the USB circuit is put in suspend status, it sets the SUSP bit of the host state status register (HSTATE) to "1". It is inhibited for USB HOST to set the USB circuit to suspend status or stop clock supplied to the circuit when the USB bus is being reset or the SOFBUSY of HSTATE is "1" or data is being sent or received. ■ Resume Operation Before it can start resume operation in suspend status, one of the following conditions must be true: (1) Write "0" to the SUSP bit of the host state status register (HSTATE). (2) The pins D+ and D- for HOST are detected to be k-state. (3) The device is detected being cut. (4) The device is detected being connected. After the RWKIRQ bit of the host interrupt register (HIRQ) is set to "1", an issuance of the token is allowed. The followings show the operation timing for each condition. Figure 14.5-11 Resume Operation by Register (Full Speed Mode) (1) Write "0" to the SUSP bit of the host state status register (HSTATE) To bit2 of HCNT "0" Write Pin D+ for HOST Pin D- for HOST 20μs∗ 1.33μs∗ 1 bit time RWKIRQ bit of HIRQ (RWKIRE=1) : Power output from USB HOST : Drive by resistances of pull-up and pull-down ∗ : This value is not guaranteed. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 357 CHAPTER 14 USB HOST 14.5 Operation of USB HOST MB90330A Series Figure 14.5-12 Resume Operation by Device (Full Speed Mode) (2) The simple host pins D+ and D- are detected to be K State. Discovers that HOST pin D + and HOST pin D - become K State. Pin D+ for HOST Pin D- for HOST 20μs∗ 1.33μs∗ 1 bit time RWIRQ bit of HIRQ (RWKIRE=1) : Power output from USB HOST : Power output from device : Drive by resistances of pull-up and pull-down ∗: This value is not guaranteed. Figure 14.5-13 Resume Operation by Device Cutoff (3) The device is detected being cut. The device is detected being cut. Cutting Pin D+ for HOST Pin D- for HOST RWKIRQ bit of HIRQ (RWKIRE=1) HIRQ bit1 (DIRE=1) Interrupt occurs CSTAT bit of HSTATE 2.5μs or more : Drive by resistances of pull-up and pull-down 358 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.5 Operation of USB HOST MB90330A Series Figure 14.5-14 Resume Operation by Device Connection (4) The device is detected being connected. Connect Pin D+ for HOST Pin D- for HOST RWKIRQ bit of HIRQ (RWKIRE=1) HIRQ bit2 (DIRE=1) Interrupt occurs CSTAT bit of HSTATE 2.5μs or more : Drive by resistances of pull-up and pull-down CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 359 CHAPTER 14 USB HOST 14.5 Operation of USB HOST 14.5.11 MB90330A Series Cutting of Device Once both HOST pins D + and D- become "L", the disconnection timer starts, and sets the CSTAT bit of the host state status register (HSTATE) to "0" when both pins detect "L" for 2.5 μs or longer. ■ Cutting of Device Regardless of Host mode and function mode, when both Host pins D+ and D- detect "L" for 2.5 μs or longer, it determines that the device is cut. Therefore, the CSTAT bit of the host state status register (HSTATE) becomes "0", and the DIRQ bit of the host interrupt register (HIRQ) is set to "1". If the DIRE bit of the host control register 0(HCNT0) is "1", an interrupt generates. To clear the interrupt, write "0" to the DIRQ bit of the HIRQ. When a reset is performed on the USB bus, it determines that the device is disconnected and sets the CSTAT bit of the host state status register 0 (HSTATE) to "0", but the DIRQ bit of the host interrupt register (HIRQ) does not become "1". 360 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 14 USB HOST 14.6 Each Token Flow Chart of USB HOST MB90330A Series 14.6 Each Token Flow Chart of USB HOST The flow chart of each token of USB HOST is as follows. ■ IN, OUT, SETUP Token Figure 14.6-1 Flow Chart at IN, OUT, SETUP Token IN,OUT, SETUP TOKEN HADR change? YES NO HADR change YES IN TOKEN NO EP1 DIR=1? YES YES EP1 DIR=1? NO EP2C PKS change? YES NO NO NO EP1 PKS change? YES PKS change Buffer direction OK? NO Buffer direction change YES Buffer usable? NO YES Set Buffer usable Set toggle and Endpoint, Execute TOKEN CMPIRQ of HIRQ=1? NO YES END CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 361 CHAPTER 14 USB HOST 14.6 Each Token Flow Chart of USB HOST MB90330A Series ■ SOF Token Figure 14.6-2 Flow Chart at SOF Token SOF TOKEN HFRAME change? YES NO HEOF change? HFRAME change YES NO HEOF change TOKEN execution (Setting TGGL and ENDPT is disregarded.) CMPIRQ of HIRQ=1? NO YES END 362 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 15 PWC TIMER This chapter describes an overview of PWC timer, the configuration and function of register, and the PWC timer operation and precaution. 15.1 Overview of PWC Timer 15.2 Register of PWC Timer 15.3 Movement of PWC Timer 15.4 Precautions when Using PWC Timer CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 363 CHAPTER 15 PWC TIMER 15.1 Overview of PWC Timer 15.1 MB90330A Series Overview of PWC Timer The PWC timer is the multi-functional 16-bit up count timer that has the function to measure the pulse width of input signal. PWC: Pulse Width Count (pulse width measurement) ■ Function of PWC Timer Following functions are implemented by hardware of a single channel including a 16-bit up count timer, a register to control input pulse divider and division ratio, a measurement input pin, and a 16-bit control register: ● Timer Functions • The set interval interrupt request can be generated. • Standard internal clock can be selected from three types. ● Pulse width measurement function • The time interval between arbiter events of external pulse input is measured. • Standard internal clock can be selected from three types. • Each kind of measurement mode - "H" pulse width(↑ - ↓)/"L" pulse width(↑ - ↓) - Rising cycle(↑ - ↑)/falling cycle(↓ - ↓) - Measurement between edges(↑ or ↓ to ↓ or ↑) • The 8-bit input divider enables the division measurement by dividing the input pulses with a denominator of 22n (n = 1, 2, 3, or 4). • You can make an interrupt occur at the end of measurement. • You can select either a single measurement or continuous measurements. 364 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 15 PWC TIMER 15.1 Overview of PWC Timer MB90330A Series ■ Block Diagram of PWC Timer Figure 15.1-1 shows the PWC timer block diagram. Figure 15.1-1 Block Diagram of PWC Timer PWCR read Error detection ERR Internal clock (Machine clock/4) PWCR 16 Reload Data transmit 16 Clock Overflow 22 16-bit Up count timer Clock divider 23 F2MC-16LX Bus Timer clear Count enabled Control bit output Flag set etc. Control circuit Start edge End edge selection selection Measurement start edge Divider clear Division ON/OFF Input waveform comparator Edge detection PWC Measurement end edge Measurement end PIS0/PIS1 interrupt request Overflow interrupt request 8-bit divider ERR CKS0/CKS1 PWCSR Ratio selection 15 2 CM44-10129-6E CKS1/CKS0 DIVR FUJITSU MICROELECTRONICS LIMITED 365 CHAPTER 15 PWC TIMER 15.2 Register of PWC Timer 15.2 MB90330A Series Register of PWC Timer Configuration and function of the register used for PWC timer are described. ■ Register List of PWC Timer Figure 15.2-1 shows the PWC timer register list. Figure 15.2-1 Register List of PWC Timer bit 15 8 7 PWCSR 0 (R/W) (R/W) PWCR (R/W) DIVR bit 15 14 13 12 11 10 9 00005DH STRT STOP EDIR EDIE OVIR OVIE ERR (R/W) (R/W) (R) (R/W) (R/W) (R/W) (R) 8 Reserved (R/W) PWCSR PWC control status register Initial value 0000000XB 6 5 4 3 2 1 0 bit 7 PWCSR 00005CH CKS1 CKS0 PIS1 PIS0 S/C MOD2 MOD1 MOD0 PWC control status register (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000B bit 15 00005FH bit 00005EH bit 000060H 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D9 D8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 7 − (−) 6 − (−) 5 − (−) 4 − (−) 3 − (−) 2 − (−) 1 0 DIV1 DIV0 (R/W) (R/W) PWCR PWC data buffer register Initial value 00000000B PWCR PWC data buffer register Initial value 00000000B DIVR PWC ratio of dividing frequency control register Initial value ------00B R/W : Readable/Writable R : Read only − 366 : Undefined FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 15 PWC TIMER 15.2 Register of PWC Timer MB90330A Series 15.2.1 PWC Control Status Register (PWCSR) Configuration and function of PWC control status register (PWCSR) are described. ■ PWC Control Status Register (PWCSR) Figure 15.2-2 shows the bit configuration of PWC control status register (PWCSR). Figure 15.2-2 Bit Configuration of PWC Control Status Register (PWCSR) bit 15 14 13 12 11 10 9 00005DH STRT STOP EDIR EDIE OVIR OVIE ERR (R/W) (R/W) (R) (R/W) (R/W) (R/W) (R) 8 Reserved (R/W) PWCSR PWC control status register Initial value 0000000XB bit 7 6 5 4 3 2 1 0 PWCSR 00005CH CKS1 CKS0 PIS1 PIS0 S/C MOD2 MOD1 MOD0 PWC control status register (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000B R/W : Readable/Writable R : Read only − : Undefined The function of each bit in the PWC control status register (PWCSR) is described in the following. [bit 15, bit 14] STRT, STOP (Timer Start Bit, Timer Stop Bit) This bit controls to start, restart, and stop the 16-bit up count timer. Timer operation status is displayed when reading. The table below shows the function of STRT and STOP bit. Table 15.2-1 Functions for Write Operation (Controlling the 16-bit Up Count Timer Operation) STRT STOP Operation control functions 0 0 The influence is not in the function none/the operation. 0 1 Timer start/restart (count enabled).* 1 0 Timer operation forced stop (count disabled). * 1 1 The influence is not in the function none/the operation. *: Enable use for clear bit instruction. Table 15.2-2 Functions for Read Operation (Displaying the 16-bit Up-count Timer Operation Status) STRT STOP 0 0 Timer under suspension (unstarted or measurement completed). [initial value] 1 1 During timer count operating (during measurement). CM44-10129-6E Operation control functions FUJITSU MICROELECTRONICS LIMITED 367 CHAPTER 15 PWC TIMER 15.2 Register of PWC Timer MB90330A Series • Initialized to "0" at reset. • Read and write are enabled. However, meanings are different between when writing and reading as shown in Table 15.2-1 and Table 15.2-2. • The value read by read-modify-write instructions is always "11B" regardless of the bit value. • Note that no bit instruction can be used for reading in the operating status (reading always produces the operating status) although the bit instruction (bit clear) can be used for either STRT or STOP bit to start or stop the timer. [bit 13] EDIR (measurement end interrupt request flag) This flag indicates the measurement termination in the pulse width measurement. When the measurement termination interrupt factor is permitted (bit 12: EDIE = 1) and this bit is set, the measurement termination interrupt request occurs. EDIR Set factor Clear factor Operation mode Set when the pulse width measurement terminates (measured results are stored in PWCR). Because PWCR (measurement result) is read, it is clear. • Initialized to "0" at reset. • Only reading is allowed. • Bit values cannot be changed by writing. [bit 12] EDIE (measurement end interruption permission) Measurement termination interrupt request during the pulse width measurement is controlled as shown in the table below: EDIE Operation mode 0 Measurement end interrupt request output disabled (interrupt is not generated even if EDIR is set). [Initial value] 1 Measurement end interrupt request output enabled (interrupt is generated if EDIR is set). • Initialized to "0" at reset. • Reading or writing is allowed. [bit 11] OVIR (timer overflow interrupt request flag) This flag indicates the 16-bit up count timer overflowed from FFFFH to 0000H. When the timer overflow interrupt factor is permitted (bit 10: OVIE = 1) and this bit is set, the timer overflow interrupt request occurs. OVIR Set factor Clear factor Operation mode Set when the overflow generates (FFFFH to 0000H). It is clear because of "0" writing or μDMAC. • Initialized to "0" at reset. • Reading and writing are allowed; however, only writing "0" is effective, while writing "1" causes no changes in the bit value. • The read value is "1" in the read-modify write instructions regardless of the bit value. 368 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 15 PWC TIMER 15.2 Register of PWC Timer MB90330A Series [bit 10] OVIE (timer overflow interrupt request permission) Measurement termination interrupt request during the pulse width measurement is controlled as shown in the table below: OVIE Operation mode 0 Overflow interrupt request output disabled (interrupt is not generated even if OVIR is set). [Initial value] 1 Overflow interrupt request output enabled (interrupt is generated when OVIR is set). • Initialized to "0" at reset. • Reading and writing are allowed. [bit 9] ERR (error flag) This flag indicates the next measurement termination before reading the measured result in the PWCR in the pulse width measurement in the continuous measurement mode. In this case, the PWCR value is updated with the new measurement result and the previous measurement result is lost. The measurement is continued regardless of the bit value. ERR Operation mode Set factor Set when measurement results that are not read yet are erased due to the following results: Clear factor Because PWCR (measurement result) is read, it is clear. • Initialized to "0" at reset. • Only reading is allowed. Write operations have no effect. [bit 8] Reserved bit It is Reserved bit. Be sure to write "0". [bit 7, bit 6] CKS1 and CKS0 (clock selection) Internal count clock can be selected from three types shown in Table 15.2-3. Table 15.2-3 Count Clock of 16 Bit Up Count Timer CKS1 CKS0 Operation mode 0 0 Clock of machine clock divided by 4 (0.17 μs for 24 MHz machine clock) [Initial value] 0 1 Clock of machine clock divided by 16 (0.67 μs for 24 MHz machine clock) 1 0 Clock of machine clock divided by 32 (1.337 μs for 24 MHz machine clock) 1 1 Setting disabled (Undefined) • Initialized to 00B at reset. • Read and write are enabled. However, setting "11B" is a interdiction. Note: Rewriting after the startup is an interdiction. Always perform the write operation before start or after stop. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 369 CHAPTER 15 PWC TIMER 15.2 Register of PWC Timer MB90330A Series [bit 5, bit 4] PIS1, PIS0 (pulse width measurement input pin selection) The pulse width measurement input pin is selected. Table 15.2-4 Selection of Pulse Width Measurement Input Pin PIS1 PIS0 Operation mode 0 0 (The pin PWC is selected). [Initial value] 0 1 Setting disabled 1 0 Setting disabled 1 1 Setting disabled (Undefined) • Initialized to 00B at reset. • Read and write are enabled. However, do not set "01B", "10B", and "11B". Note: Rewriting after the startup is an interdiction. Always perform the write operation before start or after stop. [bit 3] S/C (Measurement mode (single/continuous) selection) The measurement mode is selected. Table 15.2-5 Selection of Measurement Mode of 16-bit Up-count Timer S/C Measurement mode selection At timer mode Pulse width 0 Single measurement mode [Initial value] Reload none (single shot) Stop after one measurement 1 Continuous measurement mode There is reload (reload timer). Continuous measurement: buffer register enabled • Initialized to "0" at reset. • Reading and writing are allowed. Note: Rewriting after the startup is an interdiction. Always perform the write operation before start or after stop. 370 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 15 PWC TIMER 15.2 Register of PWC Timer MB90330A Series [bit 2 to bit 0] MOD2, MOD1, MOD0 (operation mode/measurement edge selection) Operation mode and width measurement edge are selected. Table 15.2-6 Selection of Operating Mode/measurement Edge of 16-bit Up-count Timer MOD2 MOD1 MOD0 Operation mode/measurement edge selection 0 0 0 Timer mode [Initial value] 0 0 1 Timer mode (only Reload mode) 0 1 0 Pulse width measurement mode between all edges (↑ or ↓ - ↓ or ↑) 0 1 1 Divided cycle measurement mode (input divisor enabled) 1 0 0 Cycle between rising edges measurement mode (↑ - ↑) 1 0 1 "H" pulse width measurement mode (↑ - ↓) 1 1 0 "L" pulse width measurement mode (↓ - ↑) 1 1 1 Cycle between falling edges measurement mode (↓ - ↓) • Initialized to "00B" at reset. • Reading and writing are allowed. Note: Rewriting after the startup is an interdiction. Always perform the write operation before start or after stop. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 371 CHAPTER 15 PWC TIMER 15.2 Register of PWC Timer 15.2.2 MB90330A Series PWC Data Buffer Register (PWCR) Configuration and function of PWC data buffer register (PWCR) are described. ■ PWC Data Buffer Register (PWCR) Figure 15.2-3 shows the bit configuration of PWC data buffer register (PWCR). Figure 15.2-3 Bit Configuration of PWC Data Buffer Register (PWCR) bit 15 00005FH bit 00005EH 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D9 D8 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) PWCR PWC data buffer register Initial value 00000000B PWCR PWC data buffer register Initial value 00000000B R/W : Readable/Writable The function of PWC data buffer register (PWCR) varies in between the timer mode and the pulse width setting mode that are set by the PWCSR register bit 2 to "0" (MOD2 to MOD0). ● In the timer mode (read/write enabled) Becomes the reload register that holds the reload data when the reload timer operates (PWCSR bit 3: S/C = 1). It is reading/writing in this case, it is possible in both writing. Becomes a direct access to the up count timer in the one-shot timer operation mode (PWCSR bit 3: S/C = 0). Perform the write operation when the timer stops although either read or write is possible also in this case. Reading is always enabled to read the timer value in the count operation. ● In the pulse width measurement mode (read only enabled) Becomes the buffer register that holds the previous measurement result in the continuous measurement mode (PWCSR bit 3: S/C = 1). In this case, the read only is enabled and no register value will be changed even when writing. Becomes a direct access to the up count timer in the single mode (PWCSR bit 3: S/C = 0). Also in this case, the read only is enabled and no register value will be changed even when writing. Reading is anytime enabled to obtain the timer value during the count operation. When the measurement is finished, the measured value is held. Note: Please access the PWCR register by word move operation. Be initialized to "00B" when resetting. 372 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 15 PWC TIMER 15.2 Register of PWC Timer MB90330A Series 15.2.3 PWC Ratio of Dividing Frequency Control Register (DIVR) Configuration and function of PWC Ratio of dividing frequency control register (DIVR) are described. ■ PWC Ratio of Dividing Frequency Control Register (DIVR) Figure 15.2-4 shows the bit configuration of a PWC ratio of dividing frequency control register (DIVR). Figure 15.2-4 Bit Configuration of PWC Ratio of Dividing Frequency Control Register (DIVR) bit 000060H 7 − (−) 6 − (−) 5 − (−) 4 − (−) 3 − (−) 2 − (−) 1 0 DIV1 DIV0 (R/W) (R/W) DIVR PWC ratio of dividing frequency control register Initial value ------00B R/W : Readable/Writable − : Undefined [bit 7 to bit 2] Undefined bit The reading value is irregular. No effect on writing. [bit 1, bit 0] DIV1, DIV0 (division ratio selection) This register is used in the division cycle measurement mode (PWCSR bit 2.1.0: MOD2.MOD1.MOD0 = 001B) and has no meaning in the other mode else. In the division cycle measurement mode, pulses input to the measurement pin are divided by the division ratio set in the DIVR register and a single cycle width is measured after dividing. Table 15.2-7 Division Ratio Selection DIV1 DIV0 Count clock selection 0 0 4-dividing frequency [Initial value] 0 1 16-frequency division 1 0 64-frequency division 1 1 256-frequency division • Initialized to "00B" at reset. • Reading and writing are allowed. Note: Rewriting after the startup is an interdiction. Always perform the write operation before start or after stop. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 373 CHAPTER 15 PWC TIMER 15.3 Movement of PWC Timer 15.3 MB90330A Series Movement of PWC Timer The movement of the PPG timer is explained. ■ Outline of PWC Timer Operation The PWC timer, a multi-functional timer based on the 16-bit up count timer has built-in measurement input pin, 8-bit input division, etc. PWC timer has the following two main functions: • Timer Functions • Pulse width count function Either function can select three kinds of count clocks. Basic performance and operation of each function are described as follows: 374 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 15 PWC TIMER 15.3 Movement of PWC Timer MB90330A Series 15.3.1 Operation of PWM Timer Functions The up count timer enables the reload and one-shot operations. ■ Operation of PWM Timer Functions Performs the count up at every count clock after starting the timer. An interrupt request may occur when an overflow occurs in the range between 0000H and FFFFH. The following operation is executed due to the mode when an overflow occurs: • One-shot mode: Stops Counting • Reload mode: The contents of reload register is reloaded to the timer and the counting restarts. Figure 15.3-1 shows the timer function operation in the one-shot and reload modes. Figure 15.3-1 Operation of Timer Functions [One-shot mode] (A solid line shows the timer count value.) Timer count value Overflow Overflow FFFFH Write to PWCR (Restart disabled) 0000H Timer start OVIR flag set/Timer stop Timer start OVIR flag set/Timer stop Time [Reload mode] Timer count value Overflow Overflow FFFFH Overflow Overflow Overflow Reload PWCR write value Reload Reload Reload Reload Reload 0000H PWCR write Timer start * * Restart * * Reload * Timer stop Time * :OVIR flag set CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 375 CHAPTER 15 PWC TIMER 15.3 Movement of PWC Timer 15.3.2 MB90330A Series Operation of Pulse Width Measurement Function Time cycle between arbiter events of input pulse can be measured by the time. ■ Operation of Pulse Width Measurement Function The pulse width measurement function does not start the count until the set measurement start edge is input after it is started. Starts the count up after clearing the timer to be 0000H when detecting the start edge and stops the count when detecting the stop edge. The value counted in this period is registered as the pulse width. When the measurement ends, the interruption is detected. Operates as follows depending on the measurement mode after the measurement. • Single measurement mode: Suspends the operation. • Continuous measurement mode: The timer value is transferred to the buffer register and the measurement is suspended until the next start edge is input. Figure 15.3-2 and Figure 15.3-3 show the single measurement mode operation and the continuous measurement mode operation, respectively. Figure 15.3-2 Pulse Width Measurement Operation (Single Measurement Mode/ "H" Width Measurement) PWC input measured pulse (A sold line shows the timer count value.) Timer count value FFFFH Timer clear 0000H Measurement start Timer start Timer stop Time EDIR flag set (Measurement end) Figure 15.3-3 Pulse Width Measurement Operation (Continuous Measurement Mode/ "H" Width Measurement) PWC input measured pulse (A solid line shows the timer count value.) Timer count value Overflow FFFFH Transfer data to PWCR Timer clear Timer clear 0000H Measurement start Timer start Timer stop Timer start Time EDIR flag set (Measurement end) 376 EDIR flag set FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 15 PWC TIMER 15.3 Movement of PWC Timer MB90330A Series 15.3.3 Count Clock Selection and Operation Mode selection Count clock selection and operation mode selection are described. ■ Count Clock Selection Timer count clock can be selected from three types of internal clock sources by setting the RWCSR bit 7 (CKS1) and bit 6 (CKS0). Table 15.3-1 shows the count clock selection contents. Table 15.3-1 Count Clock Selection Contents PWCSR/ bit7,bit6:CKS1,CKS0 Selected internal count clock 00B 4-division of Machine clock (0.17 μs in case of machine clock of 24 MHz) [Initial value] 01B 16-division of Machine clock (0.67 μs in case of machine clock of 24 MHz) 10B 32-division of Machine clock (1.33 μs in case of machine clock of 24 MHz) • 4-division clock of machine clock is selected for the initial value after the reset. Note: Select the count clock always before starting the timer. ■ Selects Operation Mode Select each of operation and measurement modes by setting the PWCSR bit. • Operation mode selection: PWCSR bit 2, 1, 0 (MOD2, MOD1, and MOD0 bits) timer mode/pulse width measurement mode selection, measurement edge decision, etc. • Measurement mode setting: PWCSR bit 3 (S/C bit) single measurement/continuous measurement or reload/one-shot selection. Table 15.3-2 shows the setting contents of operation mode/measurement mode. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 377 CHAPTER 15 PWC TIMER 15.3 Movement of PWC Timer MB90330A Series Table 15.3-2 Setting Contents of Operation Mode/measurement Mode Content Operating mode S/C MOD2 MOD1 MOD0 Single shot timer 0 0 0 0 Reload timer 1 0 0 0 ↑ or ↓ - ↑ or ↓ Single measurement: Buffer invalidity Measurement between all Continuous measurement: Buffer effective edges 0 0 1 0 1 0 1 0 Measurement at cycle of Single measurement: Buffer invalidity dividing frequency 1-256 frequency division Continuous measurement: Buffer effective 0 0 1 1 1 0 1 1 ↑-↑ Measurement of cycle between rising Single measurement: Buffer invalidity 0 1 0 0 Continuous measurement: Buffer effective 1 1 0 0 ↑-↓ "H" pulse width measurement Single measurement: Buffer invalidity 0 1 0 1 Continuous measurement: Buffer effective 1 1 0 1 ↓-↑ "L" pulse width measurement Single measurement: Buffer invalidity 0 1 1 0 Continuous measurement: Buffer effective 1 1 1 0 ↓-↓ Measurement of cycle between falling Single measurement: Buffer invalidity 0 1 1 1 Continuous measurement: Buffer effective 1 1 1 1 Timer Pulse width measurement • One-shot timer is selected in the initial setting after the reset. Note Select the operation mode always before starting the timer. 378 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 15 PWC TIMER 15.3 Movement of PWC Timer MB90330A Series 15.3.4 Startup and Stop of Timer/Pulse Width Measurement Start/restart/stop/forced stop of each operation are performed by using the PWCSR bit 15 and PWCSR bit 14 (STRT and STOP bits). ■ Startup and Stop of Timer/Pulse Width Measurement Functions are separated so that the STRT bit starts and restarts the timer/pulse width measurement and the STOP bit forcibly stops the measurement when "0" is written in either one of bits. However, no function is effective unless the values written in both bits are exclusive each other. When writing an instruction other than bit manipulation instructions (one-byte instruction or more), the bits combination is always limited as shown in Table 15.3-3. Table 15.3-3 Function of STRT Bit and STOP Bit STRT STOP Function 0 1 Startup/reactivation of timer/pulse width measurement 1 0 Compulsion stop of timer/pulse width measurement When using a bit manipulation instruction (clear bit instruction), the hardware automatically writes it in the combination as shown in Table 15.3-3 and no care is necessary. ■ Operation after Startup Operations are as follow after starting the timer mode or the pulse width measurement mode. ● Timer mode The count operation begins at once. ● Pulse width measurement mode No count is performed until the measurement start edge is input. After the measurement start edge is detected, the 16-bit up count timer is cleared to be 0000B and the count starts. ■ Reactivation Starting (writing "0" in the STRT bit) during the operation after starting the timer/pulse width measurement mode is called as restarting. Restarting performs the following operations depending on the mode: ● Single shot timer mode There is no influence in the operation. ● Reload timer mode Reload operates, and the operation is continued. Restarting at the same timing when an overflow occurs sets the overflow flag (OVIR). CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 379 CHAPTER 15 PWC TIMER 15.3 Movement of PWC Timer MB90330A Series ● Pulse width measurement mode In the state of measurement starting edge waiting there is no influence in the operation. During the measurement, the count is stopped and the measurement start edge is again waited. In this case, if the measurement termination edge detection and the restart occur at the same time, the measurement termination flag (EDIR) is set and the result is transferred to PWCR in the continuous measurement mode. ■ Stops In the one-shot timer mode and the single measurement mode, the timer overflow or the measurement termination automatically stops the count and no intentional stop is necessary. In the other modes, however, the timer must be forcibly stopped. Similarly, if you want to stop the timer before the automatic stop, you must forcibly stop it. ■ Check Operating State When the above-mentioned STRT and STOP bits are read, they are functional as the operating state indication bits. Table 15.3-4 shows the function of operating state indication bit. Table 15.3-4 Function of Operating State Indication Bit STRT STOP Operating State 0 0 Timer stop (excluding status of waiting for measurement start edge): It is not active or shows that the measurement ended. 1 1 During timer counting or waiting for measurement start edge Note: Reading either the STRT or STOP bit provides a same value. Do not use, however, the read-modifywrite instructions (bit process instructions, etc.) to read the STRT and STOP bits because "11B" always results. 380 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 15 PWC TIMER 15.3 Movement of PWC Timer MB90330A Series 15.3.5 Operation of Timer Mode The operation of the timer mode is explained. ■ Clearing Timer The 16-bit up count timer is cleared to be 0000H in the following case: • At a reset • In the pulse width measurement mode, when the measurement start edge is detected and the count is started. ■ One-shot Operation Modes. In the one-shot operation mode, the count up is performed at every count clock after the timer started and an overflow occurrence at counting from FFFFH to 0000H automatically stops the count. When a value is set in the PWCR before starting the timer, the count is started from the value. In this case, the set value is not held and the PWCR value indicates the current count value. ■ Reload Operation Mode In the reload operation mode, the count up is performed at every count clock after the reload value in the PWCR is set in the timer after starting the timer. Overflow occurrence at counting from FFFFH to 0000H again sets the reload value in the PWCR in the timer (reload operation) to repeat the count operation. The timer does not stop until it is forcibly stopped by writing into the PWCSR STOP bit or it is reset. The value set in the PWCR before starting the timer is held as the reload value during the count operation and always set in the timer at starting/restarting and an overflow occurrence. Use a newly changed reload value to change the set value during the count operation at the next overflow occurrence or the timer restarting. ■ Timer Value and Reload Value The PWCR in the one-shot operation mode has a direct access to the up count timer. The value written in the PWCR is written in the timer as it is so that you can acquire the timer value in the count operation by reading the PWCR value during the timer operation. If you write an arbiter value in the PWCR before starting the timer, the count operation is started from this specified value. In the reload operation mode, accessing the up count timer is impossible. The PWCR functions as the reload register to hold the reload value. When the timer start, restart, or overflow occurs, the value written in the PWCR always set to the timer. When PWCR is read, the stored reload value is read. The PWCR value and the timer value are undefined when the timer is set to the one-shot operation mode after forcibly suspending the reload operation mode. Therefore, always write the value before using the timer. ■ Interrupt Generation Request In timer mode operation, interrupt request by the timer overflow can be generated. An interrupt request is generated when the overflow flag is set at an overflow occurrence caused by the count up and the overflow interrupt request is permitted. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 381 CHAPTER 15 PWC TIMER 15.3 Movement of PWC Timer MB90330A Series ■ Timer Cycle If 0000H is set to the PWCR in the one-shot operation mode and the timer is started, an overflow occurs after 65536 times counted up to stop the count. The time period from the start to the stop is calculated by the following expression: T1=(65536-n1) × t T1: Time from startup to stop (μs) n1: Timer value written in the PWCR at the start t: Count Clock cycle (μs) If 0000H is set to the PWCR in the reload operation mode and the timer is started, an overflow occurs at every 65536-time counted up. Reload cycle time is calculated by the following expression: TR=(65536-nR) × t TR: Reload cycle (overflow cycle) (μs) nR: Reload value held in the PWCR t: Count Clock cycle (μs) ■ Count Clock and Maximum Cycle Maximum cycle is provided when 0000H is set for the PWCR value in the timer mode. The count clock cycle and the maximum cycle of the timer are shown in Table 15.3-5 when the machine clock frequency (called F hereafter) is 24 MHz. Table 15.3-5 Count Clock and Cycle Count clock selection in CSK1,CSK0=00:(φ/4) in CSK1,CSK0=00:(φ/16) in CSK1,CSK0=00:(φ/32) Count Clock Cycle 0.17 μs 0.67 μs 1.33 μs Timer maximum cycle 10.92 ms 43.7 ms 87.4 ms 382 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 15 PWC TIMER 15.3 Movement of PWC Timer MB90330A Series ■ Operation Flow of Timer Figure 15.3-4 shows the timer operation flow. Figure 15.3-4 Operation Flow of Timer Count clock selection Operation/ Each Measurement settings mode selection Interrupt flag clear Interrupt enabled Set value to PWCR Restart Reload operation mode Start by STRT bit One-shot operation mode Read PWCR value to Timer Count start Count start Count up Count up Overflow generation OVIR flag set Overflow generation OVIR flag set Count stop Operation stop CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 383 CHAPTER 15 PWC TIMER 15.3 Movement of PWC Timer 15.3.6 MB90330A Series Operation of Pulse Width Measurement Mode Operation of pulse width measurement mode is described. ■ Single Measurement and Continuous Measurement Pulse width measurement modes include a mode to perform only one-time measurement and a mode to perform continuous measurements. Each mode is selected by the PWCSR S/C bits (see Section "15.3.3 Count Clock Selection and Operation Mode selection"). ● One-time measurement mode When the first measurement termination edge is input, the timer counter stops and the measurement termination flag (EDIR) in the PWCSR is set not to perform measurement anymore (however, when the restart occurs at the same time, the measurement start is waited). ● Continuous measurement mode When the measurement termination edge is input, the timer counter stops and the measurement termination flag (EDIR) in the PWCSR is set to stop the count until the measurement start edge is again input. When the measurement start edge is again input, the measurement is started after the timer is cleared to 0000H. At the measurement termination, the measured result in the timer is transferred to the PWCR. Note: Always change the measurement mode selection when the timer stops. ■ Data of Measurement Result Measured results, the timer value handling, and the PWCR function are different between the single measurement mode and the continuous measurement mode. The measurement result in both modes is as follows: ● One-time measurement mode • When the PWCR is read during the operation, the timer value in the measurement is acquired. • When the PWCR is read after the measurement termination, the measured result data is acquired. ● Continuous measurement mode • At the measurement termination, the measured result in the timer is transferred to the PWCR. • When the PWCR is read, the last measurement result is acquired and the previous measurement result is held even in the measurement operation. The timer value under the measurement cannot be read. When the next measurement is terminated before reading the measured result in the continuous measurement mode, the previous measurement result is erased by a new measurement result. In this case, the gill in PWCSR-Flag (ERR) is set. Error flag (ERR) is automatically cleared when reading the PWCR. 384 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 15 PWC TIMER 15.3 Movement of PWC Timer MB90330A Series ■ Measurement Mode and Counter Operation The measurement mode can be selected from six types depending on the place where the input pulse is measured. The cycle measurement mode is also prepared to arbitrarily divide the input pulse for highprecision measurement of higher frequency pulse width. Table 15.3-6 shows the measurement mode list. Table 15.3-6 The Measurement Mode List (1 / 2) Measurement mode MOD2 MOD1 MOD0 Measurement mode measured target (W: width of a measured pulse) W "H" pulse width measurement 1 0 1 Count start W Count stop Start Stop The width at "H" period is measured. Count (measurement) start: when detecting a rising edge Count (measurement) end: when detecting a falling edge W "L" pulse width measurement 1 1 0 Count start W Count stop Start Stop The width at "L" period is measured. Count (measurement) start: when detecting a falling edge Count (measurement) end: when detecting a rising edge W Rising Between edges Measurement at cycle 1 0 0 Count stop Start Count start 1 1 1 W Count stop Start Count start Stop Start Stop W Stop Start Stop A cycle between falling edges is measured. Count (measurement) start: when detecting a falling edge Count (measurement) end: when detecting a falling edge W Between all edges pulse width measurement W A cycle between rising edges is measured. Count (measurement) start: when detecting a rising edge Count (measurement) end: when detecting a rising edge W Falling Between edges Measurement at cycle W W W Count stop 0 1 0 Count start Start Stop Start Stop The width between the edges continuously input is measured. Count (measurement) beginning: When edge is detected Count (measurement) end: When edge is detected CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 385 CHAPTER 15 PWC TIMER 15.3 Movement of PWC Timer MB90330A Series Table 15.3-6 The Measurement Mode List (2 / 2) Measurement mode Measurement mode measured target (W: width of a measured pulse) MOD2 MOD1 MOD0 W Measurement at cycle of dividing frequency 0 1 Count start (Example of 4 division) 1 W Count stop Start W Stop For only dividing ratio selected by division setting register DIVR The input pulse is divided and the cycle is measured. Count (measurement) start: when detecting a rising edge immediately after counting starts Count (measurement) end: when one cycle ends after it is divided No timer count is performed from start of the count to input of the count start edge in any modes. The timer is cleared to 0000H after inputting the count start edge and the timer count is performed at every count clock until the count termination edge is input. When the count termination edge is input, the next operation is executed. 1. Measurement ending flag (EDIR) in PWCSR is set. 2. The timer count operation stops (excluding when it is at the same time of restarting). 3. Continuous measurement mode: The timer value (measured result) is transferred to the PWCR and the count is suspended until the next measurement start edge is input. 4. Single measurement mode: The measurement is terminated (excluding when it is at the same time of restarting). When the pulse width measurement between all edges or the division measurement is performed in the continuous measurement mode, the termination edge is the next measurement edge. ■ Minimum Input Pulse Width There are following limitations for pulses that can be input to width measurement input pins (PWC). Pulse width must be 4-machine cycle (0.17 μs for the 24-MHz machine clock) or more. ■ Calculation Method of Pulse Width/cycle Pulse width/cycle to be measured can be calculated by the following expression: TW=n × t/DIV (μs) TW: pulse width to be measured/cycle (μs) n: Measurement result data in PWCR t: Count Clock cycle (μs) DIV: Division ratio selected by the division ratio register DIVR (Frequency of dividing frequency measurement mode) 386 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 15 PWC TIMER 15.3 Movement of PWC Timer MB90330A Series ■ Range of Count at Pulse Width/cycle Measurable ranges of pulse width/cycle vary depending on the selected combination of division ratios of count clock and input divider. Table 15.3-7 shows the measurement range list of machine clock when the clock frequency (called φ hereafter) is 24 MHz. Table 15.3-7 Pulse Width Measurement Range List Divide ratio DIV1 DIV0 in CKS1,CKS0= 00(φ/4) in CKS1,CKS0= 01(φ/16) in CKS1,CKS0= 10(φ/32) None - - 0.17 μs to 10.92 ms (0.25 μs) 0.17 μs to 43.7 ms (1.6 μs) 0.17 μs to 87.4 ms (3.2 μs) 4-frequency division 0 0 0.17 μs to 2.73 ms (6.25 μs) 0.17 μs to 10.92 ms (0.4 μs) 0.17 μs to 21.85 ms (0.8 μs) 16-frequency division 0 1 0.17 μs to 683 μs (15.6 ns) 0.17 μs to 2.73 ms (1.6 μs) 0.17 μs to 5.46 ms (0.2 μs) 64-frequency division 1 0 0.17 μs to 170 μs (3.91 μs) 0.17 μs to 683 μs (25 μs) 0.17 μs to 1.36 ms (50 ns) 256-frequency division 1 1 0.17 μs to 43 μs (0.98 μs) 0.17 μs to 171 μs (6.25 μs) 0.17 μs to 341 μs (12.5 ns) Note: These values enclosed in brackets ( ) indicate the granularity per bit ■ Interrupt Request Generation Two following interrupt requests can be generated in the pulse width measurement mode: ● Interrupt request by overflow of timer When an overflow is generated by the count up during the measurement, the overflow flag is set. When the overflow interrupt request is permitted, an interrupt request occurs. ● Interrupt request by measurement termination When the measurement termination edge is detected, the measurement termination flag (EDIR) in the PWCSR is set. If the measurement termination interrupt request is permitted, the interrupt request occurs. The measurement termination flag (EDIR) is automatically cleared as soon as the measured result PWCR is read. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 387 CHAPTER 15 PWC TIMER 15.3 Movement of PWC Timer MB90330A Series ■ Operation Flow of Pulse Width Measurement Figure 15.3-5 shows the pulse width measurement operation flow. Figure 15.3-5 Operation Flow of Pulse Width Measurement Count clock selection Operation/ Each Measurement settings mode selection Interrupt flag clear Interrupt enabled Restart Start by STRT bit Continuous measurement mode Measurement start edge detection Measurement start edge detection Clear timer Clear timer Count start Count start Count up Count up Overflow generation OVIR flag set 388 Single measurement mode Overflow generation OVIR flag set Measurement edge detection EDIR flag set Measurement edge detection EDIR flag set Count stop Count stop Read Timer value to PWCR Operation stop FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 15 PWC TIMER 15.4 Precautions when Using PWC Timer MB90330A Series 15.4 Precautions when Using PWC Timer Precautions when using the PWC timer are described. ■ Precautions when Using PWC Timer ● Notes concerning rewriting register Following bits among PWCSRs are inhibited to be updated during the operation. Always update the bits before starting or after stopping the operation. • (Bit 7, bit 6) CKS1,CKS0 (clock selection) • (Bit 5, bit 4) PIS1, PIS0 (input signal selection) • (Bit 3) S/C (Measurement mode (single/continuous) selection) • (Bit 2 to bit 0) MOD2, MOD1, MOD0 (operation mode/measurement edge selection) It is inhibited to update the DIVR during the operation. Always update the bits before starting or after stopping the operation. ● Handling of measurement ending flag of timer mode Measurement termination interrupt request flag (EDIR) value in the PWCSR has no meaning in the timer mode. Therefore, always set "0" to the measurement termination interrupt request bit (EDIE) in the PWCSR, when using in the timer mode. ● Treatment of STRT and STOP bit in PWCSR Note that both bits have different meaning between when writing and reading (see Section "15.2.1 PWC Control Status Register (PWCSR)"). In addition, the read value is "11B" when using a read-modify-write instruction regardless of the bit value. Therefore, note that no bit process instruction can be used to read the operating status (reading always produces the operating status). When writing to the STRT and STOP bits to start/stop the timer, bit process instruction (bit clear instruction, etc.) can be used for the respective bits. ● Clearing Timer Since the timer is cleared by the measurement start edge in the pulse width measurement mode, the data present in the timer before starting become invalid. ● Value of PWCR and timer when mode is changed • Always write the value before using the timer because the held value in the PWCR and the timer value become undefined when they are used in the reload timer mode before forcibly stopping the timer to switch to the one-shot timer mode. • Always write the value before the use because the PWCR value becomes undefined if it is used in the one-shot timer mode. • Always reset the value to the PWCR before starting the operation when switching the pulse width measurement mode to the timer mode. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 389 CHAPTER 15 PWC TIMER 15.4 Precautions when Using PWC Timer MB90330A Series ● Minimum pulse width There are following limitations for pulses that can be input to width measurement input pins: • Minimum pulse width: 2 divisions of machine clock (0.25μs or more for 16-MHz machine clock) • Minimum input frequency: 4 divisions of machine clock (4 MHz or less for 16-MHz machine clock) When the input pulse width is smaller or the input pulse frequency is higher than the above description, the operation cannot be guaranteed. If there is a possibility of such noise in the input signal, use, for example, a filter outside of the chip to eliminate the noise before the signal is input. ● Frequency of dividing frequency measurement mode Note that the pulse width obtained from the measured result calculation is the average value because the input pulses are divided in the division cycle measurement mode among the pulse width measurement modes. ● Handling of clock select bit Do not set "11B" to (Bit 7, bit 6) CKS1, CKS0 (clock selection) in the PWCSR. ● Reactivation under operation When restarting after starting the count operation, following cases may occur depending on the timing: • When restarting at the same time of an overflow occurrence in the reload timer mode, the overflow flag (OVIR) is set. • When restarting at the same time of measurement termination edge input in the pulse width single measurement mode, the measurement start edge is waited and the measurement termination edge (EDIR) is set. • When restarting at the same time of measurement termination edge input in the pulse width single measurement mode, the measurement start edge is waited and the measurement termination edge (EDIR) is set and the current measured result is transferred to the PWCR. ● When the PWC timer is used in "the "H" pulse-width or "L" pulse-width measurement mode in the continuous measurement mode": The pulse width measurement is completed, the next pulse width measurement start is waited, the timer operation is unexpectedly continued, and the overflow flag (OVIR) of timer may be sometime set before starting the next pulse width measurement. In this case, even when no overflow occurs at the next pulse width measurement termination, the overflow flag has been set. Therefore, do not use the overflow flag when using the PWC timer in the "H" pulse width or "L" pulse width measurement mode in the continuous measurement mode. 390 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 16 16-BIT RELOAD TIMER This chapter describes an overview of 16-bit reload timer, the configuration and functions of register and the 16-bit reload timer operation. 16.1 Overview of 16-bit Reload Timer 16.2 Registers of 16-bit Reload Timer 16.3 Movement of 16-bit Reload Timer CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 391 CHAPTER 16 16-BIT RELOAD TIMER 16.1 Overview of 16-bit Reload Timer 16.1 MB90330A Series Overview of 16-bit Reload Timer The 16-bit reload timer provides two functions either one of which can be selected, the internal clock that performs the count down by synchronizing with 3-type internal clocks and the event count mode that performs the count down by detecting the arbiter edge of pulses input to the external pin. ■ Overview of 16-bit Reload Timer Underflow of the 16-bit reload timer is defined as a case when the count value becomes from 0000H to FFFFH. Therefore, when the equation (reload register setting value + 1) holds, an underflow occurs. Either mode can be selected for the count operation from the reload mode which repeats the count by reloading the count setting value at the underflow occurrence or the one-shot mode which stops the count at the underflow occurrence. The interrupt can be generated at the counter underflow occurrence so as to correspond to the DTC. 392 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 16 16-BIT RELOAD TIMER 16.1 Overview of 16-bit Reload Timer MB90330A Series 16.1.1 Function of 16-bit Reload Timer This section describes overview and Function of 16-bit reload timer. ■ Operation Modes of 16-bit Reload Timer Clock Mode Counter operation Reload mode Internal clock One-shot mode 16-bit reload timer operation Software trigger operation External trigger operation External gate input operation Reload mode Event count mode (External clock Mode) Software trigger operation One-shot mode ■ Internal Clock Mode One type can be selected for the count clock from 3 types of internal clocks. ● Software trigger operation When 1 is written to TGR bit of timer control status register (TMCSR0 to TMCSR2), counter operation is started. Trigger input using the TRG bit is valid for the external trigger input and the external gate input. ● External trigger operation When the selected edges (rising edge, falling edge, or both edges) are input to the TIN0/TIN1/TIN2 pin, the count operation is started. ● External gate input operation While the selected signal ("L" or "H") is being input to TIN0/TIN1/TIN2, the count operation is continued. ■ Event Count Mode (External Clock Mode) This function count downs at the edge when the selected edges (rising edge, falling edge, or both edges) are input to the TIN0/TIN1/TIN2 pin. External clock of a constant cycle can be also used for the interval timer. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 393 CHAPTER 16 16-BIT RELOAD TIMER 16.1 Overview of 16-bit Reload Timer MB90330A Series ■ Counter Operation Mode ● Reload mode When an underflow (0000H → FFFFH) occurs during the count down, the count setting value is reloaded to continue the count operation. Interrupt request that can be generated at the underflow occurrence can be also used as an interval timer. The toggle waveform which reverses at every underflow occurrence can be also output from the TOT0/TOT1/TOT2 pin. Count Clock Internal clock External clock Count Clock Cycle Time of interval 21/ φ (0.083 μs) 0.083 μs to 5.461 ms 23/ φ (0.33 μs) 0.33 μs to 21.845 ms 25/ φ (1.33 μs) 1.33 μs to 87.38 ms 23/ φ (0.5 μs) 0.5 μs or more φ: Machine clock values in parentheses ( ) are when machine clock is in 24 MHz operating. ● One-shot mode When an underflow (0000H → FFFFH) occurs during the count down, the count operation is stopped. The interruption can be generated by the underflow. Short waveform which indicates the count operation can be also output from the TOT0/TOT1/TOT2 pin during the count operation. 394 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 16 16-BIT RELOAD TIMER 16.1 Overview of 16-bit Reload Timer MB90330A Series 16.1.2 Block Diagram of 16-bit Reload Timer Block Diagram of 16-bit Reload Timer is shown. ■ Block Diagram of 16-bit Reload Timer Figure 16.1-1 Block Diagram of 16-bit Reload Timer Internal data bus TMRLR0 to TMRLR2 16-bit reload register Reload signal TMR0 to TMR2 Reload control circuit 16-bit timer register (down-counter) UF CLK Count clock generation circuit Machine clock frequency 3 Prescaler Gate input Circuit to determine which clock is valid Clear Wait signal CLK Output signal generation circuit Reserved Input control circuit Pin Output signal generation circuit External clock TIN0 to TIN2 Function selection Clock selector 3 Selection signal Pin EN 2 OUTL RELD TOT0 to TOT2 Operation control circuit OUTE Timer control status register (TMCSR0 to TMCSR2) CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 395 CHAPTER 16 16-BIT RELOAD TIMER 16.2 Registers of 16-bit Reload Timer 16.2 MB90330A Series Registers of 16-bit Reload Timer Configuration and functions of register used for the 16-bit reload timer are described. ■ Register List of 16-bit Reload Timer Figure 16.2-1 is shown the list of the register of 16-bit reload timer. Figure 16.2-1 List of Register of 16-bit Reload Timer bit 15 − ch.0 : 000063H ch.1 : 000067H ( − ) ch.2 : 00006BH (X) 14 13 − − (−) (X) (−) (X) 12 TMCSR0 to TMCSR2 11 10 9 8 CSL1 CSL0 MOD2 MOD1 Timer control status register (Upper) ( − ) (R/W) (R/W) (R/W) (R/W) Read/Write (0) (0) (0) (0) (X) Initial value − 6 5 4 3 2 1 0 TMCSR0 to TMCSR2 bit 7 ch.0 : 000062H MOD0 OUTE OUTL RELD INTE UF CNTE TRG Timer control status register (Lower) ch.1 : 000066H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/Write ch.2 : 00006AH (0) (0) (0) (0) (0) (0) (0) (0) Initial value bit 15 ch.0 : 000065H D15 ch.1 : 000069H (R) ch.2 : 00006DH (W) (X) bit 7 ch.0 : 000064H D07 ch.1 : 000068H (R) ch.2 : 00006CH (W) (X) 14 13 12 11 10 9 8 D14 (R) (W) (X) D13 (R) (W) (X) D12 (R) (W) (X) D11 (R) (W) (X) D10 (R) (W) (X) D09 (R) (W) (X) D08 (R) (W) (X) 6 5 4 3 2 1 0 D06 D05 D04 D03 D02 D01 D00 (R) (W) (X) (R) (W) (X) (R) (W) (X) (R) (W) (X) (R) (W) (X) (R) (W) (X) (R) (W) (X) TMR0 to TMR2/TMRLR0 to TMRLR2 16-bit timer register/ 16-bit reload register (Upper)∗ Read (TMR0 to TMR2) Write (TMRLR0 to TMRLR2) Initial value TMR0 to TMR2/TMRLR0 to TMRLR2 16-bit timer register/ 16-bit reload register (Lower)∗ Read (TMR0 to TMR2) Write (TMRLR0 to TMRLR2) Initial value ∗ : This functions as 16-bit timer register (TMR0 to TMR2) at reading, This functions as 16-bit timer register (TMRLR0 to TMRLR2) at writing. 396 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 16 16-BIT RELOAD TIMER 16.2 Registers of 16-bit Reload Timer MB90330A Series 16.2.1 Timer Control Status Register 0 to 2 (TMCSR0 to TMCSR2) Configuration and functions of timer control status registers 0 to 2 (TMCSR0 to TMCSR2) are described. ■ Timer Control Status Register 0 to 2 (TMCSR0 to TMCSR2) The timer control status registers 0 to 2 (TMCSR0 to TMCSR2) control the operation mode and interrupt of 16-bit reload timer. Bits other than UF/CNTE/TRG are modified at CNTE=0. Figure 16.2-2 shows the bit configuration of timer control status registers 0 to 2 (TMCSR0 to TMCSR2). Figure 16.2-2 Bit Configuration of Timer Control Status Registers 0 to 2 (TMCSR0 to TMCSR2) Address: bit ch.0 : 000063H ch.1 : 000067H ch.2 : 00006BH 15 (X) 14 (X) 12 13 (X) (X) 11 10 9 8 CSL1 CSL0 MOD2 MOD1 (R/W) (R/W) (R/W) (R/W) Address: 6 5 2 0 bit 7 4 3 1 ch.0 : 000062H MOD0 OUTE OUTL RELD INTE UF CNTE TRG ch.1 : 000066H ch.2 : 00006AH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) TMCSR0 to TMCSR2 (upper) Initial value XXXX0000B TMCSR0 to TMCSR2 (lower) Initial value 00000000B R/W Readable/Writable X Undefined value Undefined The functions of each bit of timer control status registers 0 to 2 (TMCSR0 to TMCSR2) are described in the following: [bit 15 to bit 12] Undefined bit The reading value is irregular. No effect on writing. [bit 11, bit 10] CSL1, CSL0 (clock selection) Clock source is selected by count clock selection. CM44-10129-6E Clock source (machine clock φ=24 MHz time) CSL1 CSL0 0 0 φ/21(0.083 μs) [Initial value] 0 1 φ/23(0.33 μs) 1 0 φ/25(1.33 μs) 1 1 Event count mode FUJITSU MICROELECTRONICS LIMITED 397 CHAPTER 16 16-BIT RELOAD TIMER 16.2 Registers of 16-bit Reload Timer MB90330A Series [bit 9 to bit 7] MOD2, MOD1, MOD0 This bit is used to set the operation mode and the I/O pin functions. The input pin functions as a trigger at MOD2=0. When the active edge is input to the input pin and the count operation proceeds, the content of the reload register is loaded to the counter. When the MOD2 value is "1", the timer operates in the gate counter mode and the input pin functions as the gate input. In this mode, the counter operates only while the active level is being input to the input pin. The internal clock mode and the event counter mode are selected from the modes shown in Table 16.2-1 and Table 16.2-2 by combining the bits from MOD2 to MOD0. Table 16.2-1 Internal Clock Mode (CSL1, CSL0 = 00, 01 or 10) MOD2 MOD1 MOD0 Input Pin function Active edge or level 0 0 0 Trigger invalidity - [Initial value] 0 0 1 0 1 0 0 1 1 1 X 0 Rising edge Trigger input Falling edge Both edges "L" level Gate input 1 X 1 "H" level Table 16.2-2 Event Counter Mode (CSL1, CSL0 = 11) MOD2 MOD1 MOD0 Input Pin function Active edge or level X 0 0 Trigger invalidity - [Initial value] X 0 1 X 1 0 X 1 1 Rising edge Trigger input Falling edge Both edges [bit 6] OUTE (power output permission) The power output permission is controlled. The TOT0 to TOT2 pin functions as the general-purpose port and the timer output pin when "0" and "1" are provided, respectively. The output waveform becomes a toggle waveform in the reload mode. In the one-shot mode, the TOT0 to TOT2 pin outputs a short-shape wave which indicates the proceeding count operation. OUTE 398 Function 0 General-purpose port [Initial value] 1 Timer output FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 16 16-BIT RELOAD TIMER 16.2 Registers of 16-bit Reload Timer MB90330A Series [bit 5] OUTL (setting of output level) This bit is used to set the TOT0 to TOT2 pin output level. OUTL and the output pin level reverses in 0/1. OUTL At One-shot mode (RELD=0) At Reload mode (RELD=1) 0 Short-shape wave during counting "H" 0 [Initial value] 1 Short-shape wave during counting "L" 1 X 1 0 X 1 1 [bit 4] RELD (reload operation permission) It is a bit by which the reload operation is permitted. When the RELD is "1", the timer operates in the reload mode operation. In this mode, the timer loads the reload register content to the counter and continues the count operation even when an underflow occurs (when the counter value changes from 0000H to FFFFH). The timer works in the single shot mode when RELD is "0". In this mode, the counter operation stops when the counter value changes from 0000H to FFFFH and the underflow occurs. RELD Function 0 One-shot mode [Initial value] 1 Reload mode [bit 3] INTE (timer interruption demand permission) This bit permits the timer interrupt request. If the INTE value is 0, no interrupt request is generated even when the UF value becomes "1". INTE Function 0 Interrupt request power output interdiction [Initial value] 1 Interrupt request output enabled [bit 2] UF (timer interruption demand flag) It is Interrupt request flag. When the underflow is generated, UF is set in "1". Cleared by writing "0" or by μDMAC. The read value is "1" when using a read-modify-write instruction. CM44-10129-6E UF At write At programming 0 Underflow none of counter [Initial value] Clearness of this bit 1 There is an underflow of the counter. There is no change (There is no influence on another). FUJITSU MICROELECTRONICS LIMITED [Initial value] 399 CHAPTER 16 16-BIT RELOAD TIMER 16.2 Registers of 16-bit Reload Timer MB90330A Series [bit 1] CNTE (timer counter permission) It is a bit by which the timer counter is permitted. CNTE Function 0 Counter stop [Initial value] 1 Counter permission (startup trigger waiting) [bit 0] TRG (Software trigger) It is Software trigger bit. When 1 is written on the TRG, the software trigger is applied so that the reload register contents of timer is loaded to the counter to start the count operation. Writing "0" has no meaning. Reading is always "0". Always enabled only when the CNTE value is 1 regardless of the operation mode. TRG 400 Function 0 There is no change (There is no influence on another). 1 Count operation start FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 16 16-BIT RELOAD TIMER 16.2 Registers of 16-bit Reload Timer MB90330A Series 16.2.2 16-bit Timer Register 0 to 2 (TMR0 to TMR2)/ 16-bit Reload Register 0 to 2 (TMRLR0 to TMRLR2) Configuration and functions of 16-bit timer registers 0 to 2 (TMR0 to TMR2)/16-bit reload registers 0 to 2 (TMRLR0 to TMRLR2) are described. ■ 16-bit Timer Register 0 to 2 (TMR0 to TMR2)/16-bit Reload Register 0 to 2 (TMRLR0 to TMRLR2) Figure 16.2-3 shows the bit configuration of 16-bit timer registers 0 to 2 (TMR0 to TMR2)/16-bit reload registers (TMRLR0 to TMRLR2). Figure 16.2-3 Bit Configuration of 16-bit Timer Registers 0 to 2 (TMR0 to TMR2)/16-bit Reload Registers 0 to 2 (TMRLR0 to TMRLR2) bit ch.0 : 000065H ch.1 : 000069H ch.2 : 00006DH 15 14 13 12 11 10 9 8 D15 (R) (W) (X) D14 (R) (W) (X) D13 (R) (W) (X) D12 (R) (W) (X) D11 (R) (W) (X) D10 (R) (W) (X) D09 (R) (W) (X) D08 (R) (W) (X) 6 5 4 3 2 1 0 D06 D05 D04 D03 D02 D01 D00 (R) (W) (X) (R) (W) (X) (R) (W) (X) (R) (W) (X) (R) (W) (X) (R) (W) (X) (R) (W) (X) bit 7 ch.0 : 000064H D07 ch.1 : 000068H (R) ch.2 : 00006CH (W) (X) TMR0 to TMR2/TMRLR0 to TMRLR2 16-bit timer register/ 16-bit reload register (Upper)∗ Read (TMR0 to TMR2) Write (TMRLR0 to TMRLR2) Initial value TMR0 to TMR2/TMRLR0 to TMRLR2 16-bit timer register/ 16-bit reload register (Lower)∗ Read (TMR0 to TMR2) Write (TMRLR0 to TMRLR2) Initial value ∗ : This functions as 16-bit timer register (TMR0 to TMR2) at reading. This functions as 16-bit timer register (TMRLR0 to TMRLR2) at writing. ■ 16-bit Timer Register 0 to 2 (TMR0 to TMR2) This register can read the counter value of 16-bit down counter. When the counter operation is permitted (CNTE = 1 for TMCSR0 to TMCSR2) and the count operation is started, the value written in the 16-bit reload register is loaded to the registers TMR0 to TMR2 and the count down is started. In the count stop status (CNTE = 0 for TMCSR0 to TMCSR2), the TMR0 to TMR2 register value is held. Note: Always use the word transfer instruction (MOVW A 003AH, etc.) when reading the TMR0 to TMR2 register that is enabled during the counter operation. The 16-bit timer register (TMR0 to TMR2) has a read-only function despite its location at the same address as the write-only 16-bit reload register (TMRLR0 to TMRLR2). Therefore, the write process does not affect the TMR0 to TMR2 value but the TMRLR0 to TMRLR2 is written. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 401 CHAPTER 16 16-BIT RELOAD TIMER 16.2 Registers of 16-bit Reload Timer MB90330A Series ■ 16-bit Reload Register 0 to 2 (TMRLR0 to TMRLR2) Set the initial counter value to the registers TMRLR0 to TMRLR2 in the status the counter operation is inhibited (CNTE = 0 for TMCSR0 to TMCSR2) regardless of the 16-bit reload timer operation. When the counter operation is permitted (CNTE = 1 for TMCSR0 to TMCSR2) and the counter is started, the count down is started from the value written in the registers TMRLR0 to TMCSR2. Values set in the registers TMRLR0 to TMCSR2 are reloaded to the counter to continue the count down at the underflow occurrence in the reload mode. In the one-shot mode, the counter stops at FFFFH when an underflow occurs. Note: Write the TMRLR0 to TMRLR2 register in the status the counter stops (CNTE = 0 for TMCSR0 to TMCSR2). In addition, always use the word transfer instruction (MOVW A 003AH, etc.) when writing. The 16-bit timer register (TMRLR0 to TMRLR2) has a write-only function despite its location at the same address as the read-only 16-bit reload register (TMR0 to TMR2). Therefore, since the read value is the TMR0 to TMR2 value, instructions such as INC, DEC, etc. cannot be used to perform the read-modify-write (RMW) operations. 402 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 16 16-BIT RELOAD TIMER 16.3 Movement of 16-bit Reload Timer MB90330A Series 16.3 Movement of 16-bit Reload Timer The 16-bit reload timer setting and the counter operation status transition are described. ■ Setting of 16-bit Reload Timer ● Setting of internal clock mode To operate it as an interval timer, the setting shown in Figure 16.3-1 is necessary. Figure 16.3-1 Setting of Internal Clock Mode TMCSR0 bit 15 − to TMCSR2 14 13 12 − − − 11 10 9 8 7 6 5 4 3 CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE 2 1 0 UF CNTE TRG 1 Other than "11" Setting initial value (Reload value) of Counter TMRLR0 to TMRLR2 Used bit Set "1". 1 ● Setting of Event Count Mode To operate it in the event counter mode, the setting shown in Figure 16.3-2 is necessary. Figure 16.3-2 Setting of Event Count Mode bit 15 − TMCSR 14 13 12 − − − 11 10 9 8 7 6 5 4 3 CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE 2 UF 1 0 CNTE TRG 1 Other than "11" Setting initial value (Reload value) of Counter TMRLR DDR3 D37 DDR4 D46 1 CM44-10129-6E D36 D46 D35 D45 D34 D44 D33 D43 D32 D42 D31 D41 D30 D40 Used bit Set "1". Set the bit corresponding to using pin to "0". FUJITSU MICROELECTRONICS LIMITED 403 CHAPTER 16 16-BIT RELOAD TIMER 16.3 Movement of 16-bit Reload Timer 16.3.1 MB90330A Series State Transition of Counter Operation The state transition of the counter operation is shown. ■ State Transition of Counter Operation Figure 16.3-3 State Transition of Counter Operation Reset STOP state CNTE = 0, WAIT = 1 TIN pin: input disabled TOT pin: general-purpose I/O port 16-bit timer register: Retained the value at stop The value which is immediately after reset is undefined. CNTE = 0 CNTE = 0 CNTE = 1/TRG = 0 WAIT state RUN state CNTE = 1, WAIT = 1 TIN pin: only trigger input TOT pin: output value of 16-bit reload register UF = 1 & RELD = 0 (One-shot mode) 16-bit timer register: Retained the value at stop the value is undefined until loading immediately after reset. TRG = 1 (Software trigger) LOAD External trigger of TIN CNTE = 1/TRG = 1 CNTE = 1, WAIT = 0 TIN pin: function as input pin of 16-bit reload timer TOT pin: function as output pin of 16-bit reload timer 16-bit timer register: Counter operation UF = 1 & RELD = 1 (Reload mode) TRG = 1 (Software trigger) CNTE = 1, WAIT = 0 Load setting value of 16-bit reload register to 16-bit timer register Load end Status transition by Hardware Status transition by Register access 404 WAIT WAIT signal (internal signal) TRG Software trigger bit (TMCSR) CNTE Timer counter enable bit (TMCSR) UF Timer interrupt request flag bit (TMCSR) RELD Reload operation enable bit (TMCSR) FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 16 16-BIT RELOAD TIMER 16.3 Movement of 16-bit Reload Timer MB90330A Series 16.3.2 Operation of Internal Clock Mode (Reload Mode) It is synchronized with the internal count clock, the 16-bit counter performs the count down, and the counter underflow generates the CPU interrupt request. Also can output toggle waveforms from the timer output pin. ■ Operation of Internal Clock Mode (Reload Mode) When the count operation is permitted (CNTE = 1 for TMCSR) and the timer is started by the software trigger bit (TRG of TMCSR) or an external trigger, the reload register (TMRLR) value is loaded to the counter and the counter operation is started. When the counter permission bit and the software trigger bit are simultaneously set to "1", the count operation starts at the same time of the counter permission. When the counter value underflows ("0000H" → "FFFFH"), the 16-bit reload register (TMRLR) value is loaded to the counter and the count operation is continued. At this moment, if the underflow interrupt request flag bit (UF) is set to "1" and the interrupt request permission bit (INTE) is set to "1", the interrupt request occurs. In addition, the toggle waveform which reverses at every underflow can be output from the TOT pin. ● Operation of Software trigger When "1" is written to TRG bit of timer control status register (TMCSR), the counter is started. Figure 16.3-4 shows the software trigger operation at reloading. Figure 16.3-4 Count Operation (Software Trigger Operation) in the Reload Mode Count clock −1 Reload data Counter Data load signal UF bit 0000H Reload data −1 0000H Reload data −1 0000H Reload data −1 CNTE bit TRG bit T* TOT pin T: Machine cycle *: It takes 1T time from trigger input to loading of reload data. ● Operation of External trigger When a valid edge (rising edge, falling edge, or both edges can be selected) is input to the TIN pin, the counter is started. Figure 16.3-5 shows the external trigger operation in the reload mode. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 405 CHAPTER 16 16-BIT RELOAD TIMER 16.3 Movement of 16-bit Reload Timer MB90330A Series Figure 16.3-5 Count Operation in the Reload Mode (external Trigger Operation) Count clock Counter Data load signal UF bit Reload data −1 0000H Reload data −1 0000H Reload data −1 0000H Reload data −1 CNTE bit TIN pin TOT pin 2T to 2.5T* T: Machine cycle *: It takes 2T to 2.5T time from trigger input to loading of reload data. Note: Input a trigger pulse of which width is 2/φ or more to the TIN pin. ● Operation of gate input When "1" is set to the count permission bit (CNTE) of timer control status register (TMCSR) and "1" is set to the software trigger bit (TRG), the count operation is started. While a valid level ("L" or "H" can be set) of gate input, which is, set in the operation mode-setting bit (MOD2, MOD1, and MOD0) is being input to the TIN pin, the count operation is performed. Figure 16.3-6 Count Operation in the Reload Mode (Soft Trigger Operation) Count clock Counter Reload data −1 −1 −1 0000H Reload data −1 −1 Data load signal UF bit CNTE bit TRG bit T* TIN pin TOT pin T: Machine cycle *: It takes 1T time from trigger input to loading of reload data. Note: Input a trigger pulse of which width is 2/φ or more to the TIN pin. 406 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 16 16-BIT RELOAD TIMER 16.3 Movement of 16-bit Reload Timer MB90330A Series 16.3.3 Operation of Internal Clock Mode (Single Shot Mode) It is synchronized with the internal count clock, the 16-bit counter performs the count down, and the counter underflow generates the CPU interrupt request. Also the TOT pin can output rectangular waveforms indicating that counting is going on. ■ Internal Clock Mode (Single Shot Mode) When the count operation is permitted (CNTE = 1 for TMCSR) and the timer is stared by the software trigger bit (TRG of TMCSR) or an external trigger, the count operation is started. When the count permission bit and the software trigger bit are simultaneously set to "1", the count is started at the same time of the count permission. When the counter value underflows ("0000H" → "FFFFH"), the counter stops in the state of "FFFFH". At this moment, if the underflow interrupt request flag bit (UF) is set to "1" and the interrupt request permission bit (INTE) is set to "1", the interrupt request occurs. In addition, the rectangular waveform indicating the count operation can be output from the TOT pin. ● Operation of Software trigger When "1" is written to TRG bit of timer control status register (TMCSR), the counter is started. Figure 16.3-7 shows the software trigger operation in the one-shot mode. Figure 16.3-7 Count Operation in One-shot Mode (Software Trigger Operation) Count clock Reload data Counter −1 0000H FFFFH Reload data −1 0000H FFFFH Data load signal UF bit CNTE bit TRG bit T* TOT pin Start trigger input wait T: Machine cycle *: It takes 1T time from trigger input to loading of reload data. ● Operation of External trigger When a valid edge (rising edge, falling edge, or both edges can be selected) is input to the TIN pin, the counter is started. Figure 16.3-8 shows the external trigger operation in the one-shot mode. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 407 CHAPTER 16 16-BIT RELOAD TIMER 16.3 Movement of 16-bit Reload Timer MB90330A Series Figure 16.3-8 Count Operation in One-shot Mode (external Trigger Operation) Count clock Reload data Counter −1 0000H FFFFH Reload data −1 0000H FFFFH Data load signal UF bit CNTE bit TIN pin 2T to 2.5T* TOT pin Start trigger input wait T: Machine cycle *: It takes 2T to 2.5T time from trigger input to loading of reload data. Note: Input a trigger pulse of which width is 2/φ or more to the TIN pin. ● Operation of gate input While the valid level ("H" level or "L" level can be selected) is being input to the TIN pin, the count operation is performed. Figure 16.3-9 shows the gate input operation in the one-shot mode. Figure 16.3-9 Count Operation in One-shot Mode (Soft Trigger Gate Input Operation) Count clock Reload data Counter −1 0000H FFFFH Reload data −1 0000H FFFFH Data load signal UF bit CNTE bit TRG bit T* TOT pin Start trigger input wait T: Machine cycle *: It takes 1T time from trigger input to loading of reload data. Note: Input a gate input of which pulse width is 2/φ or more to the TIN pin. 408 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 16 16-BIT RELOAD TIMER 16.3 Movement of 16-bit Reload Timer MB90330A Series 16.3.4 Event Count Mode When the input edge from the TIN pin is counted, the 16-bit counter is counted down and the counter underflow occurs, the CPU interrupt request is generated. In addition, the toggle waveform or the rectangular waveform can be output from the TOT pin. ■ Event Count Mode When the count operation is permitted (CNTE = 1 for TMCSR) and the counter is started (TRG = 1 for TMCSR), the 16-bit reload register (TMRLR) value is loaded to the counter. Every time when the valid edge (rising edge, falling edge, or both edge can be selected) of pulses (external count clock) input to the TIN pin is detected, the count down is performed. When the count permission bit and the software trigger bit are simultaneously set to "1", the count is started at the same time of the count permission. ● Operation of Reload mode When the counter value underflows ("0000H" → "FFFFH"), the 16-bit reload register (TMRLR) value is loaded to the counter and the count operation is continued. At this moment, if the underflow interrupt request flag bit (UF) is set to "1" and the interrupt request permission bit (INTE of TMCSR) is "1", the interrupt request is generated. In addition, the toggle waveform which reverses at every underflow can be output from the TOT pin. Figure 16.3-10 shows Count operation (event count mode) at reload mode. Figure 16.3-10 Count Operation (Event Count Mode) at Reload Mode Count clock Reload data Counter −1 0000H Reload data −1 0000H Reload data −1 0000H Reload data −1 Data load signal UF bit CNTE bit TRG bit T* TOT pin T: Machine cycle *: It takes 1T time from trigger input to loading of reload data. Note: Use the 4/φ or more "H" width and "L" width of the clock to be input to the TIN pin. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 409 CHAPTER 16 16-BIT RELOAD TIMER 16.3 Movement of 16-bit Reload Timer MB90330A Series ● Operation of One-shot mode When the counter value underflows ("0000H" → "FFFFH"), the counter stops in the state of "FFFFH". At this moment, if the underflow request flag bit (UF) is set to "1" and the interrupt request output permission bit (INTE) is "1", the interrupt request is generated. In addition, the rectangular waveform indicating the count operation can be output from the TOT pin. Figure 16.3-11 shows Counter operation (event count mode) at single shot mode. Figure 16.3-11 Counter Operation (Event Count Mode) at Single Shot Mode Count clock Reload data Counter −1 0000H FFFFH Reload data −1 0000H FFFFH Data load signal UF bit CNTE bit TRG bit T* TOT pin Start trigger input wait T: Machine cycle *: It takes 1T time from trigger input to loading of reload data. Note: Use the 4/φ or more "H" width and "L" width of the clock to be input to the TIN pin. 410 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 17 8/16-BIT PPG TIMER This chapter describes an overview of 8/16-bit PPG timer, the configuration and functions of register, and the 8/16-bit PPG timer operation. 17.1 Overview of 8/16-bit PPG Timer 17.2 Registers of 8/16-bit PPG Timer 17.3 Operation of 8/16-bit PPG Timer CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 411 CHAPTER 17 8/16-BIT PPG TIMER 17.1 Overview of 8/16-bit PPG Timer 17.1 MB90330A Series Overview of 8/16-bit PPG Timer The 8/16-bit PPG timer provides the PPG output via the pulse output according to the timer operation with the 8-bit reload timer module. It has the following as a hardware. • Six 8-bit down counters • Twelve 8-bit reload timers • Three 16-bit control registers • Six external pulse output pins • Six interrupt outputs. Further, the MB90330A series provides 6 channels as the 8-bit PPG that also operate as the 16-bit PPG (3 channels) in the combination of PPG0 + PPG1/PPG2 + PPG3/PPG4 + PPG5. ■ Overview of 8/16-bit Timer PPG Timer Overview of 8/16-bit PPG timer function is shown below. ● 8-PPG power output six channel independent operation mode Independent 6-channel PPG output operation is enabled. ● 16-bit PPG output operation mode The 3-channel and 16-bit PPG output operation is enabled. Combination of PPG0 + PPG1, PPG2 + PPG3, and PPG4 + PPG5 are used. ● 8 + 8-bit PPG output operation mode When the PPG0 (PPG2/PPG4) output is clock-input of PPG1 (PPG3/PPG5), the 8-bit PPG output in an arbiter cycle is enabled. ● PPG output operation Pulse waves in an arbiter cycle and of duty ratio are output. Reference: Only the PPG1 can be used for the interrupt trigger of A/D converter. 412 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 17 8/16-BIT PPG TIMER 17.1 Overview of 8/16-bit PPG Timer MB90330A Series 17.1.1 Block Diagram of 8/16-bit PPG Timer Block diagram of ch.0/ch.2/ch.4 and ch.1/ch.3/ch.5 of 8/16-bit PPG timer is shown. ■ Block Diagram of 8/16-bit PPG Timer Figure 17.1-1 shows the block diagram of ch.0/ch.2/ch.4. Figure 17.1-2 shows the block diagram of channels 1/3/5. Figure 17.1-1 Block Diagram of 8/16-bit PPG Timer (ch.0/ch.2/ch.4) Peripheral clock 16 division Peripheral clock 8 division Peripheral clock 4 division Peripheral clock 2 division Peripheral clock PPG0/PPG2/PPG4 Output enabled PPG0/PPG2/PPG4 PPG0/PPG2/PPG4 Output latch PEN0 S R Q IRQ PCNT (Down counter) ch.1/ch.3/ch.5 borrow L/H selector Count clock selection PUF0 Time-base counter output: divided by 512 of Main clock PIE0 L/H selection PRLL PRLBH PPGC0/PPGC2/PPGC4 (Operation mode control) PRLH “L” data bus “H” data bus CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 413 CHAPTER 17 8/16-BIT PPG TIMER 17.1 Overview of 8/16-bit PPG Timer MB90330A Series Figure 17.1-2 Block Diagram of 8/16-bit PPG Timer (ch.1/ch.3/ch.5) PPG1/PPG3/PPG5 Output enabled Peripheral clock 16 division Peripheral clock 8 division Peripheral clock 4 division Peripheral clock 2 division Peripheral clock PPG1/PPG3/PPG5 A/D converter (only PPG1) PPG1/PPG3/PPG5 Output latch PEN1 S R Q IRQ PCNT (Down counter) L/H Count clock selection PUF1 Time-base counter output: divided by 512 of Main clock PIE1 L/H selection PRLL PRLBH PPGC1/PPGC3/PPGC5 (Operation mode control) PRLH "L" data bus "H" data bus 414 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 17 8/16-BIT PPG TIMER 17.2 Registers of 8/16-bit PPG Timer MB90330A Series 17.2 Registers of 8/16-bit PPG Timer Configuration and functions of register used for the 8/16-bit PPG timer are described. ■ Register List of 8/16-bit PPG Timer Figure 17.2-1 shows the register list of 8/16-bit PPG timer. Figure 17.2-1 Register List of 8/16-bit PPG Timer ch.0 : 000046H ch.2 : 000048H ch.4 : 00004AH ch.1 : 000047H ch.3 : 000049H ch.5 : 00004BH bit 7 6 PEN0 (R/W) (0) bit 15 (X) 14 PEN1 (R/W) (0) 5 PE00 3 (R/W) (R/W) (R/W) (0) (0) (0) 13 PE10 (X) 4 2 1 PIE0 PUF0 12 11 PIE1 PUF1 0 Reserved (X) (X) (R/W) (1) 10 9 8 MD1 MD0 Reserved (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (1) PPGC0/PPGC2/PPGC4 PPG Operation mode control register Read/Write Initial value PPGC1/PPGC3/PPGC5 PPG Operation mode control register Read/Write Initial value 6 5 4 3 2 1 0 PPG01/PPG23/PPG45 ch.0, 1 : 00004CH bit 7 PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 Reserved Reserved PPG Output control register ch.2, 3 : 00004EH ch.4, 5 : 000050H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/Write (0) ch.0 : 007900H ch.1 : 007902H ch.2 : 007904H ch.3 : 007906H ch.4 : 007908H ch.5 : 00790AH ch.0 : 007901H ch.1 : 007903H ch.2 : 007905H ch.3 : 007907H ch.4 : 007909H ch.5 : 00790BH CM44-10129-6E bit (0) (0) (0) (0) (0) (X) (X) Initial value PRLL0 to PRLL5 PPG Reload register lower Read/Write Initial value 7 6 5 4 3 2 1 0 D07 D06 D05 D04 D03 D02 D01 D00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) bit 15 D15 14 13 12 11 10 9 8 D14 D13 D12 D11 D10 D09 D08 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) PRLH0 to PRLH5 PPG Reload register upper Read/Write Initial value FUJITSU MICROELECTRONICS LIMITED 415 CHAPTER 17 8/16-BIT PPG TIMER 17.2 Registers of 8/16-bit PPG Timer 17.2.1 MB90330A Series PPG0/PPG2/PPG4 Operation Mode Control Register (PPGC0/PPGC2/PPGC4) Configuration and functions of PPG0/PPG2/PPG4 operation mode control register (PPGC0/PPGC2/PPGC4) are described. ■ PPG0/2/4 Operation Mode Control Register (PPGC0/PPGC2/PPGC4) The PPG0/PPG2/PPG4 operation mode control register (PPGC0/PPGC2/PPGC4) selects the operation mode of ch.0/ch.2/ch.4, controls the pin output, selects the count clock, and controls the trigger. Figure 17.2-2 shows the bit configuration of PPG0/PPG2/v4 operation mode control registers (PPGC0/ PPGC2/PPGC4). Figure 17.2-2 Bit Configuration of PPG0/PPG2/PPG4 Operation Mode Control Registers (PPGC0/PPGC2/PPGC4) ch.0 : 000046H ch.2 : 000048H ch.4 : 00004AH bit 7 6 5 PEN0 (R/W) (0) PE00 4 3 (R/W) (R/W) (R/W) (0) (0) (0) (X) 2 1 0 PIE0 PUF0 Reserved (X) (X) (R/W) (1) PPGC0/PPGC2/PPGC4 PPG Operation mode control register Read/Write Initial value The following describes functions of each bit of PPG0/PPG2/PPG/4 operation mode control registers (PPGC0/PPGC2/PPGC4): [bit 7] PEN0: ppg Enable (operation permission) The operation start and operation mode of PPG0/PPG2/PPG4 are selected. PEN0 Operating State 0 Operation stop ("L" level output maintenance) 1 PPG Enabling Operations • With this bit is set to "1", the PPG starts counting. • This bit is initialized to "0" at reset. • Reading and writing are allowed. [bit 6] Undefined bit The read value is irregular. Nothing is affected when it is written. [bit 5] PE00: ppg output Enable 00 (PPG0/PPG2/PPG4 output pin enabled) Inhibition and permission of pulse output to the external pulse output pin PPG0/PPG2/PPG4 are controlled. PE00 Operating State 0 General-purpose port pin (pulse output interdiction). 1 PPG0/PPG2/PPG4 pulse output (pulse output permission). • This bit is initialized to "0" at reset. • Reading and writing are allowed. 416 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 17 8/16-BIT PPG TIMER 17.2 Registers of 8/16-bit PPG Timer MB90330A Series [bit 4] PIE0: ppg Interrupt Enable (interrupt to PPG0/PPG2/PPG4 enabled) PPG0/PPG2/PPG4 interrupt inhibition and permission are controlled. PIE0 Operating State 0 Disables the interrupt 1 Interruption permission • If PUF0 is changed to "1" while this bit is "1", an interrupt request is generated. If this bit is "0", no interrupts are generated. • This bit is initialized to "0" at reset. • Reading and writing are allowed. [bit 3] PUF0: ppg Underflow Flag (PPG0/PPG2/PPG4 counter underflow) Detected result of counter underflow of the PPG0/PPG2/PPG4 is shown. PUF0 Operating State 0 The PPG counter underflow is not detected. 1 The PPG counter underflow was detected. In the 8-bit PPG6 channel mode (PPG0, PPG1/PPG2, PPG3/PPG4, PPG5) and the 8-bit prescaler + 8-bit PPG mode, the counter values of ch.0, ch.2, ch.4 are set to "1" when they underflow from 00H to FFH. In the 16-bit PPG3 channel mode (PPG0, PPG1/PPG2, PPG3/PPG4, PPG5), the counter values of ch.1, ch.3, ch.5/ch.0, ch.2, ch.4 are set to "1" when they underflow from 0000H to FFFFH. Becomes "0" by written "0". "1" writing in the PUF0 bit is not significant. "1" is read with a read-modify-write instruction. • This bit is initialized to "0" at reset. • Reading and writing are allowed. [bit 2, bit 1] Undefined bit The read value is irregular. Nothing is affected when it is written. [bit 0] Reserved bit It is Reserved bit. Always set this bit to "1". CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 417 CHAPTER 17 8/16-BIT PPG TIMER 17.2 Registers of 8/16-bit PPG Timer 17.2.2 MB90330A Series PPG1/PPG3/PPG5 Operation Mode Control Register (PPGC1/PPGC3/PPGC5) Configuration and functions of PPG1/PPG3/PPG5 operation mode control register (PPGC1/PPGC3/PPGC5) are described. ■ PPG1/PPG3/PPG5 Operation Mode Control Register (PPGC1/PPGC3/PPGC5) The PPG1/PPG3/PPG5 operation mode control register (PPGC1/PPGC3/PPGC5) selects the operation mode of ch.1/ch.3/ch.5, controls the pin output, selects the count clock, and controls the trigger. Figure 17.2-3 shows the bit configuration of PPG1/PPG3/PPG5 operation mode control registers (PPGC1/ PPGC3/PPGC5). Figure 17.2-3 Bit Configuration of PPG1/PPG3/PPG5 Operation Mode Control Registers (PPGC1/PPGC3/PPGC5) ch.1 : 000047H bit 15 PEN1 ch.3 : 000049H ch.5 : 00004BH (R/W) (0) 14 13 PE10 (X) 12 11 PIE1 PUF1 10 9 8 MD1 MD0 Reserved (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (1) PPGC1/PPGC3/PPGC5 PPG Operation mode control register Read/Write Initial value The following describes functions of each bit of PPG1/PPG3/PPG5 operation mode control registers (PPGC1/PPGC3/PPGC5): [bit 15] PEN1: ppg Enable (operation permission) The operation start and operation mode of PPG1/PPG3/PPG5 are selected. PEN1 Operating State 0 Operation stop ("L" level power output maintenance) 1 PPG Enabling Operations • When this bit is set to "1", PPG count starts. • This bit is initialized to "0" at reset. • Reading and writing are allowed. [bit 14] Undefined bit The lead value is irregular. Nothing is affected when it is written. 418 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 17 8/16-BIT PPG TIMER 17.2 Registers of 8/16-bit PPG Timer MB90330A Series [bit 13] PE10: ppg output Enable10 (PPG1/PPG3/PPG5 output pin enabled) Inhibition and permission of pulse output to the external pulse output pin PPG1/PPG3/PPG5 are controlled. PE10 Operating State 0 General-purpose port pin (pulse output interdiction) 1 PPG1/PPG3/PPG5 pulse output (pulse output permission) • This bit is initialized to "0" at reset. • Reading and writing are allowed. [bit 12] PIE1: ppg Interrupt Enable (interrupt to PPG1/PPG3/PPG5 enabled) PPG1/PPG3/PPG5 interrupt inhibition and permission are controlled. PIE1 Operating State 0 Disables the interrupt. 1 Interruption permission. • If PUF1 is set to "1" when this bit is "1", an interrupt request is generated. When this bit is "0", no interrupts are generated. • This bit is initialized to "0" at reset. • Reading and writing are allowed. [bit 11] PUF1:Ppg Underflow Flag (PPG1/PPG3/PPG5 counter underflow) Detected result of counter underflow of the PPG1/PPG3/PPG5 is shown. PUF1 Operating State 0 The PPG counter underflow has not been detected. 1 The PPG counter underflow was detected. In the 8-bit PPG6 channel mode (PPG0, PPG1/PPG2, PPG3/PPG4, PPG5) and the 8-bit prescaler + 8-bit PPG mode, the counter values of ch.1, ch.3, ch.5 are set to "1" when they underflow from 00H to FFH. In the 16-bit PPG3 channel mode (PPG0, PPG1/PPG2, PPG3/PPG4, PPG5), the counter values of ch.1, ch.3, ch.5/ch.0, ch.2, ch.4 are set to "1" when they underflow from 0000H to FFFFH. Becomes "0" by written "0". "1" writing in the PUF0 bit is not significant. "1" is read with a read-modify-write instruction. • This bit is initialized to "0" at reset. • Reading and writing are allowed. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 419 CHAPTER 17 8/16-BIT PPG TIMER 17.2 Registers of 8/16-bit PPG Timer MB90330A Series [bit 10, bit 9] MD1, MD0: ppg count Mode (operation mode selection) The operation mode of the PPG timer is selected. MD1 MD0 Operating mode 0 0 Byte PPG2 channel independent mode (The case multiplied by 3 is enabled). 0 1 8-bit prescaler + 8-bit PPG 1channel. 1 0 Reserved (Setting prohibited). 1 1 16-bit PPG1 channel mode (The case multiplied by 3 is enabled). • This bit is initialized to "0" at reset. • Reading and writing are allowed. Notes: • Please set neither MD1 nor MD0 bits in "10B". • Do not set the PPGC0 PEN0 bit and the PPGC1 PEN1 bit to "01B" when setting the MD1 and MD0 bits to "01B". In addition, the PEN0 and PEN1 bits are recommended to simultaneously set to "11B" or "00B". • Set the PEN0/PEN1 to "11B" or "00B" simultaneously, when setting the MD1 and MD0 bits to "11B" by updating the PPGC0/PPGC1 via the word transfer. [bit 8] Reserved bit It is Reserved bit. Always set this bit to "1". 420 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 17 8/16-BIT PPG TIMER 17.2 Registers of 8/16-bit PPG Timer MB90330A Series 17.2.3 PPG0 to PPG5 Output Control Register (PPG01/PPG23/PPG45) Configuration and functions of PPG0 to PPG5 output control register (PPG01/PPG23/ PPG45) are described. ■ PPG0 to PPG5 Output Control Register (PPG01/PPG23/PPG45) Figure 17.2-4 shows the bit configuration of the PPG0 to PPG5 output control registers (PPG01/PPG23/ PPG45). Figure 17.2-4 PPG0 to PPG5 Output Control Register (PPG01/PPG23/PPG45) 1 bit 7 6 3 2 5 4 0 ch.0, 1 : 00004CH PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 Reserved Reserved ch.2, 3 : 00004EH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ch.4, 5 : 000050H (0) (X) (X) (0) (0) (0) (0) (0) PPG01/PPG23/PPG45 PPG Output control register Read/Write Initial value PPG0 to PPG5 output control register (PPG01/PPG23/PPG45) [bit 7 to bit 5] PCS2 to PCS0: ppg Count Select (count clock selection) Selects the operation clock of the ch.1, ch.3, and ch.5 down counters. PCS2 PCS1 PCS0 Operating mode 0 0 0 Peripheral Clock (41.7 ns machine clock 24 MHz time) in surrounding 0 0 1 Peripheral Clock /2 (83.3 ns machine clock 24 MHz time) in surrounding 0 1 0 Peripheral Clock /4 (167 ns machine clock 24 MHz time) in surrounding 0 1 1 Peripheral Clock /8 (333 ns machine clock 24 MHz time) in surrounding 1 0 0 Peripheral Clock /16 (667 ns machine clock 24 MHz time) in surrounding 1 1 1 Input clock from time-base counter (29 × 167 ns=85μs field oscillation 6 MHz time) • These bits are initialized to "000B" at reset. • Reading and writing are allowed. Note: Since the PPG of ch.1, ch.3, and ch.5 operates by receiving the count clock from the ch.0, ch.2, and ch.4 in the 8-bit prescaler + 8-bit PPG mode and the 16-bit PPG mode, the specified PCS2 to PCS0 bits become invalid. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 421 CHAPTER 17 8/16-BIT PPG TIMER 17.2 Registers of 8/16-bit PPG Timer MB90330A Series [bit 4 to bit 2] PCM2 to PCM0:ppg Count Mode (count clock selection) These bits select the down counter operation clock of ch.0, ch.2, and ch.4. PCM2 PCM1 PCM0 Operating mode 0 0 0 Peripheral Clock (41.7 ns machine clock 24 MHz time) in surrounding 0 0 1 Peripheral Clock /2 (83.3 ns machine clock 24 MHz time) in surrounding 0 1 0 Peripheral Clock /4 (167 ns machine clock 24 MHz time) in surrounding 0 1 1 Peripheral Clock /8 (333 ns machine clock 24 MHz time) in surrounding 1 0 0 Peripheral Clock /16 (667 ns machine clock 24 MHz time) in surrounding 1 1 1 Input clock from time-base counter (29 × 167 ns=85 ms field oscillation 6 MHz time) • These bits are initialized to "000B" at reset. • Reading and writing are allowed. [bit 1, bit 0] Reserved bit It is Reserved bit. Always set this bit to "00B". 422 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 17 8/16-BIT PPG TIMER 17.2 Registers of 8/16-bit PPG Timer MB90330A Series 17.2.4 PPG Reload Registers (PRLL0 to PRLL5, PRLH0 to PRLH5) Configuration and functions of PPG reload registers (PRLL0 to PRLL5, PRLH0 to PRLH5) are described. ■ PPG Reload Registers (PRLL0 to PRLL5, PRLH0 to PRLH5) Figure 17.2-5 shows the bit configuration of PPG reload registers (PRLL0 to PRLL5, PRLH0 to PRLH5). Figure 17.2-5 PPG Reload Registers ((PRLL0 to PRLL5, PRLH0 to PRLH5) ch.0 : 007900H ch.1 : 007902H 6 5 4 3 2 1 0 ch.2 : 007904H bit 7 D07 D06 D05 D04 D03 D02 D01 D00 ch.3 : 007906H ch.4 : 007908H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ch.5 : 00790AH (X) (X) (X) (X) (X) (X) (X) (X) ch.0 : 007901H 14 13 12 11 10 9 8 ch.1 : 007903H bit 15 ch.2 : 007905H D15 D14 D13 D12 D11 D10 D09 D08 ch.3 : 007907H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ch.4 : 007909H (X) (X) (X) (X) (X) (X) (X) (X) ch.5 : 00790BH PRLL0 to PRLL5 PPG Reload register lower Read/Write Initial value PRLH0 to PRLH5 PPG Reload register upper Read/Write Initial value The PPG reload registers (PRLL0 to PRLL5, PRLH0 to PRLH5) are the 8-bit registers that hold the reload values for the down counter (PCNT). Each of them has roles as shown in the following table: Register Name Function PRLL Hold the reload value of L side. PRLH Hold the reload value of H side. • Both registers can be read and written. Note: When different values are set for the PRLL and PRLH of the ch.0, ch.2, and ch.4 using the 8-bit prescaler + 8-bit PPG mode, the PPG waveforms of ch.1, ch.3, and ch.5 may be different each other according to the cycle. Therefore, the same value is recommended to set for the PRLL and PRLH of the ch.0, ch.2, and ch.4. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 423 CHAPTER 17 8/16-BIT PPG TIMER 17.3 Operation of 8/16-bit PPG Timer 17.3 MB90330A Series Operation of 8/16-bit PPG Timer The 8/16-bit PPG timer has the 6 channels (PPG0, PPG1/PPG2, PPG3/PPG4, PPG5) of 8bit length PPG unit. Each of them can operate 3-type operations in total, the 8-bit prescaler + 8-bit PPG modes and the 16-bit PPG mode by performing the direct-coupled (PPG0 + PPG1/PPG2 + PPG3/PPG4 + PPG5) operations in addition to the independent mode. ■ Outline of Operation of 8/16-bit PPG Timer Each of 8-bit length PPG units has two 8-bit-length reload registers for the "L" and "H" sides (PRLL, PRLH). Values written in the PRLL and PRLH registers are reloaded to the 8-bit down counter (PCNT) for the "L" and "H" sides alternately and down-counted at every count clock so that the output pin value is reversed when the registers are reloaded at the count borrow occurrence. This operation causes the pin output to be the "L"-width/"H"-width pulse output corresponding to the reload register value. Operation is started/restarted by the written register bit. The relation between the reload operation and the pulse output is shown in the following table. Reload operation Pin output change PRLH → PCNT PPG0/PPG1 (0 → 1) rising In addition, when the bit 4 (PIE0) in PPGC0/PPGC2/PPGC4 is "1" and the bit 2 (PIE1) in PPGC1/PPGC3/ PPGC5 is "1", the interrupt request is output at a borrow occurrence from 00H to FFH (borrow from 0000H to FFFFH in the 16-bit PPG mode) for respective counter. ■ Operating Mode The 8/16-bit PPG timer has 3-type operation modes in total, the 2-channel independent mode, the 8-bit prescaler + 8-bit PPG mode, and the 16-bit PPG mode (MB90330A series have 3 channels for each mode). The 2-channel independent mode is a mode to allow an independent 2-channel operation as the 8-bit PPG. The PPG outputs of ch.0 and ch.1 are connected to the PPG0 and PPG1 pins, respectively (PPG2 to PPG5 correspond to ch.2 to ch.5). The 8-bit prescaler + 8-bit PPG mode is the operation mode to operate the ch.0 (ch.2/ch.4) as the 8-bit prescaler and to enable the 8-bit PPG waveform output in an arbiter cycle, by counting the ch.1 (ch.3/ch.5) at a ch.0 (ch.2/ch.4) borrow output. The PPG0 (PPG2/PPG4) pin is connected to the bit prescaler output of ch.0 (ch.2/ch.4) and the PPG1 pin is connected to the PPG output of ch.1 (ch.3/ch.5). The 16-bit PPG channel mode (MB90330A series provide 3 channels) is the operation mode to allow the direct-coupling of ch.0 and ch.1 (direct-coupled ch.2, ch.3/ch.4, ch.5) to be operated as the 16-bit PPG. Both PPG0 and PPG1 16-bit PPG power outputs are both connected. 424 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 17 8/16-BIT PPG TIMER 17.3 Operation of 8/16-bit PPG Timer MB90330A Series ■ PPG Output Operation The 8/16-bit PPG timer is started to begin the count when both the bit 7 (PEN0) of PPGC0 register for 0 (ch.2/ch.4) PPG and the bit 15 (PEN1) of PPGC1 register for 1 (ch.3/ch.5) PPG are set to "1". After the operation started, when "0" is written to the bit 7 (PEN0) of PPGC0 or the bit 15 (PEN1) of PPGC1, the count operation is stopped and the pulse output is held at the "L" level thereafter. Do not set the ch.1 (ch.3/ch.5) to the operating status in the 8-bit prescaler + 8-bit PPG mode when the ch.0 (ch.2/4) is in the stop state. Control the bit 7 (PEN0) in the PPGC0 register and the bit 15 (PEN1) in the PPGC1 register to simultaneously start and stop in the 16-bit PPG mode. PPG output operation is explained as follows. When the PPG operates, the pulse wave is continuously output in an arbiter cycle and arbiter duty ratio (ratio of "H" level period and "L" level period of pulse wave). The PPG starts the pulse wave output and does not stop until the operation stop is set. Figure 17.3-1 shows the output waveform in the PPG output operation. Figure 17.3-1 Output Waveform in the PPG Output Operation PEN Operation start by PEN (from "L" side) Output pin PPG T × (L + 1) T × (H + 1) L : PRLL value H : PRLH value (START) T : Peripheral clock (by Clock select of PPGC) ■ Relation between Reload Value and Pulse Width The written value in the reload register added to "1" and multiplied by the count clock cycle produces the output pulse width. Note, therefore, that the pulse width is one count clock cycle when the reload register value is 00H during the 8-bit PPG operation or when the reload register value is 0000H during the 16-bit PPG operation. Note also that the pulse width is the 256 count clock cycles when the reload register value is FFH during the 8-bit PPG operation and the pulse width is the 65536 divisions of count clock when the reload register value is FFFFH during the 16-bit PPG operation. The equations for calculating the pulse width are shown below: PL=T × (L+1) PH=T × (H+1) PL: Width of "L" pulse PH: Width of "H" pulse T: Clock Cycle L: PRLL value H: PRLH value CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 425 CHAPTER 17 8/16-BIT PPG TIMER 17.3 Operation of 8/16-bit PPG Timer MB90330A Series ■ Count Clock Selection The count clock used for 8/16-bit PPG timer operation uses the peripheral clock and the time-base counter input to allow 6 types of count clock input selection. The bit4 to bit2 (PCM2 to PCM0) of PPG01/PPG23/PPG45 register selects the ch.0 (ch.2/ch.4) clock and the bit7 to bit5 (PCS2 to PCS0) of PPG01/PPG23/PPG45 register selects the ch.1 (ch.3/ch.5) clock. For the clock selection, 1/16 to 1 times of machine clock and the time-base counter input are selected. Notes: • The bit 14 (PCS1) value of PPGC1 register is invalid in the 8-bit prescaler + 8-bit PPG mode and 16-bit PPG mode. • When the time-base timer input is used, the trigger or the first count cycle after stopping may deviate. In addition, if the time-base counter is initialized in the 8/16-bit PPG timer operation, the cycle may deviate. • When the ch.0/ch.2/ch.4 is in the operating status, the ch.1/ch.3/ch.5 is in the stopped status, and the ch.1 (ch.3/ch.5) is started in the 8-bit prescaler + 8-bit PPG mode, the first count cycle may deviate. ■ Pin Output Control of Pulse The pulse generated by the 8/16-bit PPG timer can be output from the external pins (PPG0 to PPG5). To output pulses from the external pin, "1" is written in the bit corresponding to each pin. The PPGC0 bit 5 (PE0) and the PPGC1 bit 3 (PE1) are used for the PPG0/PPG2/PPG4 and PPG1/PPG3/PPG5 pins, respectively. When "0" is written in this pin (initial value), no pulse is output from the external pin that then functions as a general-purpose port. Since the same waveform is output from the PPG0 to PPG5 in the 16-bit PPG mode, either of external pins can be enabled to obtain the same output. The 8-bit prescaler toggle waveform and the 8-bit PPG waveform are output from the PPG0/PPG2/PPG4 and the PPG1/PPG3/PPG5, respectively, in the 8-bit prescaler + 8-bit PPG mode. The output waveform in this mode is shown in Figure 17.3-2. Figure 17.3-2 8 + 8PPG Output Operation Waveform PH0 P L0 PPG0 PPG1 PH1 PL1 The pulse width shown in Figure 17.3-2 can be calculated by the following expression. 426 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 17 8/16-BIT PPG TIMER 17.3 Operation of 8/16-bit PPG Timer MB90330A Series PL0=T × (L0+1) PH0=T × (L0+1) PL1=T × (L0+1) × (L1+1) PH1=T × (L0+1) × (H1+1) L0: Value of PRLL of ch.0 and value of PRLH of ch.1 L1: Value of PRLL of ch.1 H1: Value of PRLH of ch.1 T: input clock cycle PH0: Width of "H" pulse of PPG0 PL0: Width of "L" pulse of PPG0 PH1: Width of "H" pulse of PPG1 PL1: Width of "L" pulse of PPG1 Note: PRLL of ch.0 and PRLH of ch.1 set the same value. ■ Interrupts of 8/16-bit PPG Timer The 8/16-bit PPG timer interrupt becomes active when the reload value is counted out and a borrow occurs. In the 8-bit PPG2 channel mode or the 8-bit prescaler + 9 bit PPG mode (each of MB90330A series has 3 channels), each interrupt request is generated by each borrow. In the 16-bit PPG mode, however, the PUF0 and the PUF1 are simultaneously set by the 16-bit counter borrow. Permit, therefore, either only one of PIE0 or PIE1 to unify interrupt factors. Also clear interrupt factors for the PUF0 and the PUF1 at the same time. ■ Initial Value of Hardware Component The 8/16-bit PPG timer hardware component is initialized to the following value at the reset: <REGISTERS > PPG0 → 0X000001B PPG1 → 00000001B PPG01 → XXXXXX00B <pulse output > PPG0 → "L" PPG1 → "L" PE0 → PPG0 power output interdiction PE1 → PPG1 power output interdiction <interruption requests > IRQ0 → "L" IRQ1 → "L" Hardware components not listed above are not initialized. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 427 CHAPTER 17 8/16-BIT PPG TIMER 17.3 Operation of 8/16-bit PPG Timer MB90330A Series ■ Writing Timing to Reload Register In any modes other than the 16-bit PPG mode, the word transfer instruction is recommended to write data into the reload registers PRLL and PRLH. When the data item is written in the register by using the byte transfer instructions for two times, an unexpected pulse width output may be generated depending on the timing. Figure 17.3-3 shows the timing for writing in reload register. Figure 17.3-3 Timing Chart for Writing in Reload Register PPG0 A B A B C B C D C D [1] In Figure 17.3-3, when the PRLL is updated from A to C before the [1] timing and the PRLH value is updated from B to D after the [1] timing, the PRL values at the [1] timing are represented as PRLL = C and PRLH = B to generate pulses of the count number C for the L side and the count number B for H side only once. Similarly, in order to write data in the PRL of ch.0/ch.2/ch.4 and ch.1/ch.3/ch.5 in the 16-bit PPG mode, the long-word transfer instruction is used or the word transfer instruction is sequentially used for the PRL of the ch.0 → ch.1 (ch.2 → ch.3/ch.4 → ch.5). In this mode, the data are temporally written from the ch.0/ch.2/ch.4 to the PRL. Then, when they are written in the PRL of ch.1/ch.3/ch.5, they actually written in the PRL of ch.0. In modes other than the 16-bit PPG mode, data can be written independently to the ch.0/ch.2/ch.4 and ch.1/ ch.3/ch.5. Figure 17.3-4 shows the block diagram of writing to PRL register. Figure 17.3-4 Block Diagram of Writing to PRL Register Writing data of PRL of ch.0 Writing to ch.0 other than 16-bit PPG mode Temporary latch Writing data of PRL of ch.1 Synchronize with writing to ch.1 at 16-bit PPG mode and transfer Written data of ch.1 PRL of ch.0 428 FUJITSU MICROELECTRONICS LIMITED PRL of ch.1 CM44-10129-6E CHAPTER 18 DTP/EXTERNAL INTERRUPT This chapter describes an overview of DTP/external interrupt, the configuration and functions of register, and the DTP/external interrupt operation. 18.1 Overview of DTP/External Interrupt 18.2 Register of DTP/External Interrupt 18.3 Operation of DTP/External Interrupt 18.4 Precaution of Using DTP/External Interrupt CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 429 CHAPTER 18 DTP/EXTERNAL INTERRUPT 18.1 Overview of DTP/External Interrupt 18.1 MB90330A Series Overview of DTP/External Interrupt The DTP (Data Transfer Peripheral) is located between peripherals existing out of the device and the F2MC-16LX CPU. It is the peripheral control section that receives a DMA request or an interrupt request generated by the external peripheral, reports it to the F2MC-16LX CPU, and starts the μDMAC or the interrupt processing. ■ Overview of DTP/External Interrupt Two types, "H" and "L" can be selected as the request level for μDMAC. Four types in total, the rising edge and falling edge in addition to "H" and "L" can be selected for an external interrupt request. ■ Block Diagram of DTP/External Interrupt Figure 18.1-1 shows the block diagram of DTP/external interrupt. Figure 18.1-1 Block Diagram of DTP/External Interrupt F2MC-16LX bus 4 4 4 8 430 DTP/Interrupt enable register Gate Factor F/F Edge detection circuit 4 Request input DTP/Interrupt factor register Request level setting register FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 18 DTP/EXTERNAL INTERRUPT 18.2 Register of DTP/External Interrupt MB90330A Series 18.2 Register of DTP/External Interrupt This section describes the configuration and functions of registers used for the DTP and external interrupts. ■ Register List of DTP/External Interrupt Figure 18.2-1 shows the register list of the DTP/external interrupts. Figure 18.2-1 Register List of DTP/External Interrupt bit Address : 00003CH 7 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 bit Address : 00003DH 15 14 13 12 11 10 9 8 ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 bit Address : 00003EH 7 6 5 4 3 2 1 0 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 bit Address : 00003FH 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 DTP/Interrupt register (ENIR) DTP/Interrupt register (EIRR) Request level setting register (ELVR) Request level setting register (ELVR) ■ DTP/Interruption Permission Register (ENIR: Enable Interrupt Request Register) Figure 18.2-2 shows the bit configuration of the DTP and enable interrupt register (ENIR). Figure 18.2-2 Bit Configuration of the DTP and the Enable Interrupt Request Register (ENIR) ENIR bit Address : 00003CH 7 6 5 4 3 2 1 0 EN7 R/W EN6 R/W EN5 R/W EN4 R/W EN3 R/W EN2 R/W EN1 R/W EN0 R/W Initial value 00000000B R/W: Readable/Writable The DTP and the enable interrupt register (ENIR) determine to issue the request to the interrupt controller by using the device pin as the external interrupt and the DTP request input. The pin corresponding to the bits set to "1" in the ENIR register is used to input an external interrupt or DTP request to issue the requests to the interrupt controller. The pin corresponding to the bits set to "0" holds the external interrupt or DTP request input factor but issues no request to the interrupt controller. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 431 CHAPTER 18 DTP/EXTERNAL INTERRUPT 18.2 Register of DTP/External Interrupt MB90330A Series ■ DTP/Interruption Request Register (EIRR: External Interrupt Request Register) Figure 18.2-3 shows the bit configuration of DTP/interruption request register (EIRR). Figure 18.2-3 Bit Configuration of DTP/interruption Request Register (EIRR) bit 15 EIRR Address : 00003DH ER7 R/W R/W: Readable/Writable 14 13 12 11 10 9 8 ER6 ER5 ER4 ER3 ER2 ER1 ER0 R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B (However, the object is different between both of them.) The DTP/interruption request register (EIRR) indicates the presence of corresponding external DTP/ interruption request when reading and clears the flip-flop contents that indicates this request when writing. When "1" is read from the EIRR register it indicates the external DTP/interruption request presence in a pin corresponding to the ERx bit. In addition, when "0" is written in the EIRR register, the request flip-flop of the corresponding bit is cleared. Writing "1" causes no operation. "1" is read with a read-modify-write instruction. Notes: • The initial value is "00H" while the value is changed after the reset depending on the status of pin in the common-use with the external interrupt. • Clear only the bits that the CPU accepted the interrupt (those bits that ER7 to ER0 are set to "1") to "0" when plural external interrupt request outputs are enabled (ENIR: EN7 to EN0 = 1). No other bits must be cleared unconditionally. • The value of the DTP/external interrupt request bit (EIRR:ER) is available only when the corresponding DTP/external internal enable bit (ENIR:EN) is set to "1". When the DTP/external interrupt is not enabled (ENIR:EN = 0), the DTP/external interrupt factor may be set regardless of whether the DTP/external interrupt request exists or not. • Clear the corresponding DTP/external interrupt request bit (EIRR:ER) just before enabling the DTP/external interrupts (ENIR:EN = 1). ■ Request Level Setting Register (ELVR: External Level Register) Figure 18.2-4 shows the bit configuration of the request level setting register (ELVR). Figure 18.2-4 Request Level Setting Register (ELVR) ELVR bit Address : 00003EH 7 6 5 4 3 2 1 0 LB3 R/W LA3 R/W LB2 R/W LA2 R/W LB1 R/W LA1 R/W LB0 R/W LA0 R/W bit 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 R/W R/W: Readable/Writable R/W R/W R/W R/W R/W R/W R/W Address : 00003FH Initial value 00000000B Initial value 00000000B The request level setting register (ELVR) selects the request detection level. Two bits are allocated per pin as shown in Table 18.2-1. When the request input is in the level mode and the input is active, it is again set even if it is cleared. 432 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 18 DTP/EXTERNAL INTERRUPT 18.2 Register of DTP/External Interrupt MB90330A Series Table 18.2-1 ELVR allocation (LA0-LA7,LB0-LB7) CM44-10129-6E LBx LAx Operation 0 0 There is a demand at "L" level. 0 1 There is a demand at "H" level. 1 0 Request present at the rising edge 1 1 Request present at the falling edge FUJITSU MICROELECTRONICS LIMITED 433 CHAPTER 18 DTP/EXTERNAL INTERRUPT 18.3 Operation of DTP/External Interrupt 18.3 MB90330A Series Operation of DTP/External Interrupt This section describes the Operation of DTP/External Interrupt. ■ External Interrupt Operation If a request set by the ELVR register at the corresponding pin is input after setting an external interrupt request, this resource issues an interrupt request signal for the interrupt controller. When the interrupt from this resource had the highest priority as a result of the priority identification of the interrupts simultaneously occurred in the interrupt controller, the interrupt controller issues an interrupt request to the F2MC-16LX CPU. The F2MC-16LX CPU compares the interrupt level mask register (ILM) in the processor status (PS) with the interrupt request. When the request level is higher than the ILM bit, the hardware interrupt process microprogram is started as soon as the current instruction execution is terminated. Figure 18.3-1 shows the external interrupt operation flow. Figure 18.3-1 External Interrupt Operation External interrupt/DTP Other requests ELVR Interrupt controller IL ICRyy CMP CMP EIRR ENIR F2MC-16LX CPU ICRxx ILM INTA Factor The interrupt process microprogram reads the interrupt vector area, issues the interrupt acknowledge to the interrupt controller, transfers the macro instruction jump address generated by the vector to the program counter, and executes the user interrupt process program. ■ Operation of DTP As an initialization in the user program before starting the μDMAC, the register addresses allocated in from 000000H to 0000FFH are set to the I/O address pointer in the μDMAC descriptor and the memory buffer start address is set to the buffer address pointer. The DTP operation sequence is almost same with those of external interrupt and are quite identical until the CPU starts the hardware interrupt process microprogram. When the μDMAC is started, the read or write signal is sent to the addressed external peripheral device for the transfer operation with this chip. The external peripheral device must cancel the interrupt request to this chip within three machine cycles after the transfer operation. When the transfer is terminated, the descriptor, etc. are updated and the interrupt controller generates the signal to clear the transfer factor. When this resource receives the signal to clear the transfer factor, it clears the flip-flop that holds the factor and prepares for the next pin request. Figure 18.3-2 shows the timing to cancel the external interrupt request at the DTP operation termination. In addition, Figure 18.3-3 shows the example of interfaces with external peripheral devices. 434 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 18 DTP/EXTERNAL INTERRUPT 18.3 Operation of DTP/External Interrupt MB90330A Series Figure 18.3-2 Timing to Cancel the External Interrupt Request at the DTP Operation Termination Edge request or H level request Interrupt factor Internal operation Descriptor select/read Address bus pin Note : μDMAC I/O register At memory transfer Read address Write address Read data Data bus pin Write data Read signal Write signal Withdraw within 3-machine cycle. Data, Address, Bus Internal bus Register External peripheral device Figure 18.3-3 Example of an External Peripheral Interface INT IRQ DTP CORE MEMORY When transfer is terminated, withdraw within 3-machine cycle MB90330A CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 435 CHAPTER 18 DTP/EXTERNAL INTERRUPT 18.4 Precaution of Using DTP/External Interrupt 18.4 MB90330A Series Precaution of Using DTP/External Interrupt Notes DTP/an external interruption is used are explained. ■ Condition of Peripheral Equipment Connected Outside The external peripheral device that the DTP can support must automatically clear the request at the transfer execution. In addition, if the transfer request is not canceled within three-machine-cycle (an interim value) after the transfer operation started, this resource handles it as if the next transfer request occurs. ■ Operation Process of DTP/External Interrupt Set the registers within the DTP/external interrupt by using the following procedures: 1. Set the general purpose I/O port that is shared with the external interrupt as input port. 2. Disable the bits for the enable register. 3. The target bit for request level set register is set. 4. The target bit for the factor register is cleared. 5. Enable the bits for the enable register. Simultaneous writing is possible for 4 and 5 with the word specification. Before setting registers in this resource, the enable register must be disabled. In addition, before enabling the enable register, the factor register must be cleared. These actions prevent erroneous interrupt factor occurrence at register setting or in the interrupt enable state. ■ External Interrupt Request Level • Minimum 3 machine cycles are necessary for the pulse width to detect the edge presence when the request level is set to the edge request. • When the request input level is set to the level setting, the request to the interrupt controller remains active even if an external request is input and canceled afterward, in case of the interrupt request enable state (ENIR:EN=1). To cancel the request for the interrupt controller, the interrupt request flag bit (EIRR: ER) must be cleared. Figure 18.4-1 Clearness of Interrupt Request Flag Bit (EIRR: ER) when Level is Set Interrupt factor Level detection Interrupt request flag bit (EIRR: ER) Enable gate to Interrupt controller Continue to retain the factor as long as it is not cleared. 436 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E MB90330A Series CHAPTER 18 DTP/EXTERNAL INTERRUPT 18.4 Precaution of Using DTP/External Interrupt Figure 18.4-2 Interrupt Factor when Enabling the Interrupt and the Interrupt Request for the Interrupt Controller Interrupt factor (e.g. "H" level detection) Interrupt request to interrupt controller Cancel of interrupt request Inactive by clearing interrupt request flag bit (EIRR: ER) Note: Returning from the clock mode is impossible at the edge detection. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 437 CHAPTER 18 DTP/EXTERNAL INTERRUPT 18.4 Precaution of Using DTP/External Interrupt 438 FUJITSU MICROELECTRONICS LIMITED MB90330A Series CM44-10129-6E CHAPTER 19 8/10-BIT A/D CONVERTER This chapter explains the functions and operation of 8/10-bit A/D converter. 19.1 Overview of 8/10-bit A/D Converter 19.2 Configuration of 8/10-bit A/D Converter 19.3 Register of 8/10-bit A/D Converter 19.4 Explanation of Operation of 8/10-bit A/D Converter 19.5 Precautions when Using 8/10-bit A/D Converter 19.6 Example of program-1 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Single Mode) 19.7 Example of Program-2 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Continuous Mode) 19.8 Example of Program-3 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Stop Mode) CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 439 CHAPTER 19 8/10-BIT A/D CONVERTER 19.1 Overview of 8/10-bit A/D Converter 19.1 MB90330A Series Overview of 8/10-bit A/D Converter The 8/10-bit A/D converter has a function to convert the analog input voltage to the 8-bit or 10-bit digital value by the RC sequential comparison conversion method. The input signal can be selected from the 16-channel analog input pin. The conversion start can be selected from three types of the software, the PPG timer 1 output, and the trigger input start from external pin. ■ Function of 8/10-bit A/D Converter There is a function having following features to perform the A/D conversion of the analog voltage input from the analog input pin (input voltage) to the digital value: • The conversion time is a minimum of 7.16 μs (including the sampling time using the 24 MHz machine clock). • Sampling time is 3.33 μs or more (machine clock 6 MHz time). • The used conversion method is the RC sequential compare conversion method with sample hold circuit. • The analog input pin can be selected from the 16 channels using the program. • The interrupt request can be generated at the A/D conversion termination and the EI2OS can be also started. No data are lost in the interrupt enable status since the conversion data protection function works even in the continuous conversion. • The conversion start factor can be selected from the software, the PPG timer 1 output (rising edge), and the external trigger input (falling edge). Conversion mode has three types shown in Table 19.1-1. Table 19.1-1 Conversion Modes of 8/10-bit A/D Converter Conversion Mode Single conversion operation Scanning conversion operation Single-shot conversion mode The specified channel (one channel only) is converted for one time and terminated. Continuous plural channels (maximum 16 channels can be specified) are converted for one time and terminated. Continuous conversion mode The specified channel (one channel only) is repetitively converted. Continuous plural channels (maximum 16 channels can be specified) are repetitively converted. Pauseconversion mode The specified channel (one channel only) is converted for one time and suspended until the next start. Continuous plural channels (maximum 16 channels can be specified) are converted. However, one channel is converted and suspended until the next start. 440 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 19 8/10-BIT A/D CONVERTER 19.2 Configuration of 8/10-bit A/D Converter MB90330A Series 19.2 Configuration of 8/10-bit A/D Converter 8/10-bit A/D converter is composed of the following 9 blocks. • A/D control status register (ADCS) • A/D data register (ADCR) • A/D conversion channel set register (ADMR) • Decoder • Analog channel selector • Sample hold circuit • D/A converter • Comparator • Control circuit (Sequential comparison register) ■ Block Diagram of 8/10-bit A/D Converter Figure 19.2-1 Block Diagram of 8/10-bit A/D Converter AVcc AVRH AVss Comparator Sample & Hold circuit A/D data register Decoder P87/AN15 Control circuit 2 to D/A converter F MC-16LX Bus P70/AN0 analog channel selector MPX ADCR1, ADCR0 A/D conversion channel set register ADMR A/D Control status register upper A/D Control status register lower PPG1 output Timer start P96/ADTG/FRCK Trigger start ADCS1, ADCS0 Operation clock Prescaler CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 441 CHAPTER 19 8/10-BIT A/D CONVERTER 19.2 Configuration of 8/10-bit A/D Converter MB90330A Series ● A/D control status registers (ADCS) Displayed are the start and start trigger selection by software, the conversion mode selection, the A/D conversion channel selection, the enabled and disabled interrupt requests, the interrupt request status confirmation, the suspension status and the conversion status. ● A/D data registers (ADCR) This register stores the A/D conversion result and also has a function to select the A/D conversion resolution. ● A/D conversion channel set register (ADMR) This register selects the A/D conversion channel. ● Decoder This circuit selects the analog input pin to be used from the setting of bits from ANE0 to ANE3 and from ANS0 to ANS3 of A/D conversion channel set register (ADMR). ● Analog channel selector This circuit selects the pin to be used from the 16 analog input pins. ● Sample hold circuit This circuit holds the input voltage selected by the analog channel selector. The input voltage can be converted without affected by the input voltage fluctuation in the A/D conversion (in the comparison) by holding the sample of input voltage immediately after starting the A/D conversion. ● D/A converter The reference voltage is generated to compare the held sample of input voltage. ● Comparator This compares the input voltage for which sample hold is performed, with the output voltage of the D/A converter to determine which is the greater of the two. ● Control circuit (Sequential comparison register) The signal from the comparator (higher or lower) determines the A/D conversion value. When the A/D conversion is terminated, the conversion result is stored in the A/D data register (ADCR) and the interrupt request is generated. 442 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 19 8/10-BIT A/D CONVERTER 19.3 Register of 8/10-bit A/D Converter MB90330A Series 19.3 Register of 8/10-bit A/D Converter Register list of 8/10-bit A/D converter is shown. ■ Register List of 8/10-bit A/D Converter Figure 19.3-1 Register of 8/10-bit A/D Converter 6 bit 7 Address: 000040H MD1 MD0 5 − (R/W) (R/W) ( − ) 14 bit 15 Address: 000041H BUSY INT 4 − 3 − 2 − (−) (−) (−) 1 − 0 A/D Control status register (Lower) (ADCS0) ( − ) (R/W) Initial value 0 0 - - - - - 0B 13 12 11 10 9 INTE PAUS STS1 STS0 STRT Reserved 8 A/D Control status register (Upper) (ADCS1) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) Initial value 00000000B Reserved bit 7 Address: 000042H D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 (R) (R) (R) (R) (R) (R) (R) (R) bit 15 Address: 000043H S10 14 ST1 13 ST0 12 CT1 11 CT0 10 − 9 D9 8 D8 (R/W) (W) (W) (W) (W) (−) (R) (R) A/D Data register (Lower) (ADCR0) Initial value XXXXXXXXB A/D Data register (Upper) (ADCR1) Initial value 00101XXXB 14 13 12 11 10 9 8 bit 15 A/D Conversion Channel Set register Address: 000045H ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0 (ADMR) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000B R/W: Readable/Writable CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 443 CHAPTER 19 8/10-BIT A/D CONVERTER 19.3 Register of 8/10-bit A/D Converter 19.3.1 MB90330A Series A/D Control Status Register (High) (ADCS1) The A/D control status register "H" level (ADCS1) has functions to start the software, to select the start trigger, to enable and disable the interrupt request, and to confirm the interrupt request, suspension and conversion statuses. ■ A/D Control Status Register (High) (ADCS1) Figure 19.3-2 A/D Control Status Register (High) (ADCS1) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 000041H BUSY INT R/W R/W INTE PAUS STS1 STS0 STRT R/W R/W R/W R/W W bit 8 bit 7 Reserved bit 0 (ADCS0) Initial value 00000000B R/W Reserved bit Reserved Always write this to "0". A/D conversion start bit (only valid for Software start) STRT 0 No A/D conversion function start 1 A/D conversion function start STS1 STS0 A/D start factor selection bit 0 Software start 0 1 Trigger start or Software start 1 0 Timer start or Software start 1 Trigger star, Timer start or Software start 0 1 PAUS 0 1 INTE Suspension flag bit (only valid for using EI2OS) A/D conversion operation doesn't stop temporarily. A/D conversion operation stops temporarily. Interrupt request enable bit 0 Interrupt request output disabled 1 Interrupt request output enabled Interrupt request flag bit INT Read Write 0 Not finish A/D conversion Clear this bit. 1 Finish A/D conversion No change, no effection to others In operating bit BUSY Read R/W W 444 Write 0 Stop A/D conversion 1 In operating of A/D conversion No change, no effection to others Stop A/D conversion forcibly : Readable/Writable : Write only : Initial value FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 19 8/10-BIT A/D CONVERTER 19.3 Register of 8/10-bit A/D Converter MB90330A Series Table 19.3-1 Description and Functions of Each Bit of A/D Control Status Register (High) (ADCS1) Bit name Functions BUSY: Under the conversion bit • The operation display bit of A/D converter. • When the BUSY bit is "0" and "1" in the read process, it indicates the stopped A/D conversion and the operated A/D conversion, respectively. • When "0" is written in the BUSY bit in the write process, the A/D conversion operation is forcibly stopped. When "1" is written, the conversion is not changed and no others are affected. Note: Do not perform the forced stop and the software start (BUSY = 0, STRT = 1) at the same time. INT: Interrupt request flag bit • When the data are set to the A/D data register by the A/D conversion, the INT bit is set to "1". • When the INT bit and the interrupt request enabled bit (ADCS1: INTE) are set to "1", the interrupt request is generated. If EI2OS has been permitted, EI2OS is started. • When "0" is set in the write process, the INT bit is cleared. When "1" is set, it is not changed and no others are affected. • The INT bit is cleared by the startup of EI2OS. Note: The A/D must be stopped when writing "0" in the INT bit for clearing. INTE: Interrupt demand permission bit • This bit is used to enable and disable the interrupt output to CPU. • When the INTE bit and the interrupt request flag bit (ADCS1: INT) are set to "1", the interrupt request is generated. • Set it to "1" when using the EI2OS. PAUS: Temporary stop flag bit • It is set to "1" when the A/D conversion operation is suspended. • Since this A/D converter has only one A/D data register, when the CPU has not yet completed to read the old conversion result by using the continuous conversion mode, the old conversion data are lost by a new conversion result. Therefore, to use the continuous conversion mode, the automatic transfer of conversion result to the memory must be basically set by using the EI2OS at every conversion termination. However, such case can be assumed that the conversion data transfer is not completed before the next conversion in the multiple interrupts, etc. The PAUS bit is the function to prepare for the such case. When the PAUS bit is set to "1", the A/D conversion is stopped so that the next conversion data are not stored during the period from the conversion termination to the data register contents transfer with the EI2OS. After that, the A/ D converter automatically restarts the conversion at the transfer termination with the EI2OS. Note: Only when EI2OS is used, the PAUS bit is effective. STS1, STS0: A/D startup factor selection bits • The start factor of A/D conversion is selected. • When the start factor is in the common use, the first start factor generation starts the operation. Note: Switch the start factor when the target start factor is not present to update it during the A/D conversion operation because it is changed at the same time of updating. bit 9 STRT: Analog to digitalizing A/D converter start up bit • This bit is used to start the A/D conversion operation by the software. • When "1" is written in the STRT bit, the A/D conversion is started. • During the suspend conversion mode, the restart operation by STRT bit is not performed. Note: Forcibly stop and software start up must not be done at the same time. bit 8 Reserved: reserved bit Note: Be sure to write "0". bit 15 bit 14 bit 13 bit 12 bit 11, bit 10 CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 445 CHAPTER 19 8/10-BIT A/D CONVERTER 19.3 Register of 8/10-bit A/D Converter 19.3.2 MB90330A Series A/D Control Status Register (Low) (ADCS0) The A/D control status register low-level (ADCS0) has a function to select the conversion mode. ■ A/D Control Status Register (Low) (ADCS0) Figure 19.3-3 A/D Control Status Register (Low) (ADCS0) Address 000040H bit 15 (ADCS1) bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 MD1 MD0 Reserved R/W R/W R/W Initial value 00 - - - - - 0B Reserved bit Always set this bit to "0". Reserved MD1 MD0 R/W : Readable/Writable : Undefined : Initial value 446 0 0 0 1 1 0 1 1 A/D conversion mode selection bit Single conversion mode 1 (Enable restart during operation) Single conversion mode 2 (Disable restart during operation) Continuous conversion mode (Disable restart during operation) Stop conversion mode (Disable restart during operation) FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 19 8/10-BIT A/D CONVERTER 19.3 Register of 8/10-bit A/D Converter MB90330A Series Table 19.3-2 Description and Functions of Each Bit of A/D Control Status Register (Low) (ADCS0) Bit name bit 7, bit 6 MD1, MD0: A/D conversion mode selection bits bit 5 to bit 1 Undefined bits bit 0 Reserved bit CM44-10129-6E Functions • This bit is used to select the conversion mode during the A/D conversion operation. • Two bit values of MD1 and MD0 allow the selection of either the single conversion mode 1, the single conversion mode 2, the continuous conversion mode, or the stop conversion mode. • The meaning of each mode is as follows. Single conversion mode 1:The continuous A/D conversion from the setting channels of ANS3 to ANS0 to the setting channels of ANE3 to ANE0 is performed only once. It is possible to reactivate while operating. Single conversion mode 2:The continuous A/D conversion from the setting channels of ANS3 to ANS0 to the setting channels of ANE3 to ANE0 is performed only once. It is not possible to reactivate while operating. Continuous conversion mode:The continuous A/D conversion from the setting channels of ANS3 to ANS0 to the setting channels of ANE3 to ANE0 is repetitively performed until it is forcibly stopped with the BUSY bit. It is not possible to reactivate while operating. Stop conversion mode:The A/D conversion from the setting channels of ANS3 to ANS0 to the setting channel of ANE3 to ANE0 is repeated and suspended at every channel until it is forcibly stopped with the BUSY bit. It is not possible to reactivate while operating. The suspended conversion is restarted by the start factor occurrence selected by the STS1 and STS0 bits. Note: The disabled restart in each of the single, continuous, and stop conversion modes is applied to the external trigger and software start. The read value is irregular. Nothing is affected when it is written. Be sure to set this bit to "0". FUJITSU MICROELECTRONICS LIMITED 447 CHAPTER 19 8/10-BIT A/D CONVERTER 19.3 Register of 8/10-bit A/D Converter 19.3.3 MB90330A Series A/D Conversion Channel Set Register (ADMR) A/D conversion channel set register (ADMR) has the function to select the A/D conversion. ■ A/D Conversion Channel Set Register (ADMR) Figure 19.3-4 A/D Conversion Channel Set Register (ADMR) Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 000045H ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0 bit 9 bit 8 Initial value 00000000B (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) ANE3 ANE2 ANE1 ANE0 A/D conversion end selection bit 0 0 0 0 0 0 0 0 1 0 1 0 AN0 Pin 0 0 1 1 AN3 Pin 0 1 0 0 AN4 Pin 0 1 0 1 AN5 Pin 0 1 1 0 AN6 Pin 0 1 1 1 AN7 Pin 1 0 0 0 AN8 Pin 1 0 0 1 AN9 Pin 1 0 1 0 AN10 Pin 1 0 1 1 AN11 Pin 1 1 1 1 0 0 0 1 AN12 Pin 1 1 1 0 AN14 Pin 1 1 1 1 AN15 Pin AN1 Pin AN2 Pin AN13 Pin A/D conversion start selection bit ANS3 ANS2 ANS1 ANS0 R/W : Readable/Writable : Initial value 448 Reading stopped Read temporarily in stop In stop mode during conversion conversion mode 0 0 0 0 0 0 0 0 1 0 1 0 AN0 Pin 0 0 1 1 AN3 Pin 0 1 0 0 AN4 Pin 0 1 0 1 AN5 Pin 0 1 1 0 AN6 Pin 0 1 1 1 AN7 Pin 1 0 0 0 AN8 Pin 1 0 0 1 AN9 Pin 1 0 1 0 AN10 Pin 1 0 1 1 AN11 Pin 1 1 1 1 0 0 0 1 AN12 Pin 1 1 1 1 1 1 AN1 Pin AN2 Pin Number during conversion Number converted immediately before AN13 Pin 0 AN14 Pin 1 AN15 Pin FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E MB90330A Series CHAPTER 19 8/10-BIT A/D CONVERTER 19.3 Register of 8/10-bit A/D Converter Table 19.3-3 Description and Functions of Each Bit of A/D Conversion Channel Set Register (ADMR) Bit name bit 15 to bit 12 bit 11 to bit 8 Functions ANS3, ANS2, ANS1, ANS0: A/D conversion beginning channel selection bits • This bit set the start channel of the A/D conversion and indicates the channel numbers under A/D conversion during conversion operation. • When the A/D conversion is started, it is begun from the channels written in these bits. • Channel numbers under the conversion can be read during the A/D conversion. The channel number converted immediately before can be read during the suspension in the stop conversion mode. ANE3, ANE2, ANE1, ANE0: A/D conversion end channel selection bits • This bit sets the end channel of the A/D conversion. • A/D conversion is performed up to the specified channel. • When the same channels with ANS3 to ANS0 are set, only those channels are converted. In addition, when the continuous conversion mode or the stop conversion mode is set and the conversion is completed for the channels set by those bits, the start channel set by the ANS3 to ANS0 is resumed. Note: Do not set the A/D conversion mode selection bits (MD1 and MD0) and A/D conversion end channel selection bits (ANE3, ANE2, ANE1 and ANE0) through read-modify-write commands after the start channel is set in the A/D conversion start channel selection bits (ANS3, ANS2, ANS1 and ANS0). The ANS3, ANS2, ANS1 and ANS0 bits will read the last conversion channel until the A/D conversion operation starts. Accordingly when the MD1 and MD0 bits and the ANE3, ANE2, ANE1 and ANE0 bits are set through read-modify-write commands after the start channel is set in the ANS3, ANS2, ANS1 and ANS0 bits, the values of the ANE3, ANE2, ANE1 and ANE0 bits may be rewritten. Note: Setting that the A/D conversion end channel is smaller than the A/D conversion start channel (ANS > ANE) is disabled. Analog to digital conversion channel set register (ADMR) should be set by byte access. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 449 CHAPTER 19 8/10-BIT A/D CONVERTER 19.3 Register of 8/10-bit A/D Converter 19.3.4 MB90330A Series A/D Data Register (ADCR1/ADCR0) The A/D data register (ADCR1/ADCR0) stores the A/D conversion result and also has a function to select the A/D conversion resolution. ■ A/D Data Register (ADCR1/ADCR0) Figure 19.3-5 A/D Data Register (ADCR1/ADCR0) Address bi t15 bi t14 bi t13 bit12 bi t11 bi t10 bi t9 000043H/ S10 ST1 ST0 CT1 CT0 D9 000042H W W W W W R bi t8 bi t7 bi t6 bi t5 bi t4 bit3 bi t2 bit1 D8 D7 D6 D5 D4 D3 D2 D1 D0 00101XXX B R R R R R R R R R 450 Initial value XXXXXXXX B A/D data bit D9 to D0 Conversion data R: Read only W: Write only bit0 CT1 0 0 1 1 CT0 0 1 0 1 Compare time setting bit 44 Machine cycle (1.83ms@24MHz) 66 Machine cycle (2.75ms@24MHz) 88 Machine cycle (3.67ms@24MHz) 176 Machine cycle (7.33ms@24MHz) ST1 0 0 1 1 ST0 0 1 0 1 20 Machine cycle (3.33ms@6MHz) 32 Machine cycle (5.33ms@6MHz) 48 Machine cycle (4.0ms@12MHz) 128 Machine cycle (5.33ms@24MHz) S10 0 1 Sampling time setting bit AD data bit 10-bit conversion resolution mode (D9 to D0) 8-bit conversion resolution mode (D7 to D0) FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E MB90330A Series CHAPTER 19 8/10-BIT A/D CONVERTER 19.3 Register of 8/10-bit A/D Converter Table 19.3-4 Functional Explanation of Each Bit in the A/D Data Register (ADCR0/ADCR1) Bit name Functions S10: A/D conversion resolution selection bit • This bit is used to select the A/D conversion resolution. • When "0" and "1" are written in the S10 bit, 10-bit and 8-bit resolutions are selected, respectively. Note: The A/D data bits used are different depends on the resolution. bit 14, bit 13 ST1,ST0: Sampling time setting bit • This bit is used to select the sampling time at the A/D conversion. • When the A/D is started, the set time and the analog input are fetched into the ST1 and ST0 bits. Note: When the setting for "00" 6 MHz is provided during the 24 MHz operation, the normal analog voltage sometime cannot be fetched. bit 12, bit 11 CT1,CT0: Comparison time setting bit • This bit is used to select the comparison time at the A/D conversion. • The analog input is fetched (sampling time elapsed), the CT1 and CT0 bits are set, the conversion result data is determined, and then they are stored in the bit 9 to bit 0 of this register. Note: When the setting for "00" 6 MHz is provided during the 24 MHz operation, the normal analog conversion value sometime cannot be fetched. Undefined bit The read value is irregular. Nothing is affected when it is written. D9 to D0 • The A/D conversion result is stored and the register is updated at every conversion termination. • The final conversion value is stored usually. • The initial value of the ADCR register is irregular. Note: The conversion data protection function is provided. (Please refer to Section "19.4 Explanation of Operation of 8/10-bit A/D Converter".) Do not write data in the D9 to D0 bits during the A/D conversion. bit 15 bit 10 bit 9 to bit 0 Notes: • Rewrite the S10 bit always when the A/D operation before the conversion is stopped. When updating after the conversion, the ADCR contents become undefined. • Always use the word transfer instruction (MOVW A, 0042H, etc.) to read the ADCR register by specifying the 10 bit mode. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 451 CHAPTER 19 8/10-BIT A/D CONVERTER 19.4 Explanation of Operation of 8/10-bit A/D Converter 19.4 MB90330A Series Explanation of Operation of 8/10-bit A/D Converter Three mode types, the single conversion, continuous conversion, and stop conversion modes are available for the 8/10-bit A/D converter. The operation explanation in each mode is done. ■ Operation of Single-shot Conversion Mode In single conversion mode, it sequentially converts the analog input on the channels which have been set by the ANS bit and ANE bit, and when it reaches to the end channel set in ANE bit, it stops the A/D conversion. When the start channel and the termination channel are same (ANS = ANE), only one channel specified by the ANS bit is converted. For the operation in the single conversion mode, the setting as shown in Figure 19.4-1 is necessary. Figure 19.4-1 Setting of Single Conversion Mode bit15 bit14 bit13 bit12 bit11 bit10 ADCS BUSY INT bit9 bit8 bit7 bit6 INTE PAUS STS1 STS0 STRT Reserved MD1 bit5 bit4 bit3 bit2 bit1 MD0 bit0 Reserved 0 ADCR S10 ST1 ST0 CT1 Store conversion data CT0 ADMR ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0 ADER ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 : Used bit : Set bit corresponding to using pin to "1". 0 : Set "0" Example of Conversion Order in Single Conversion Mode. In the case of ANS = 000B and ANE = 011B: AN0 → AN1 → AN2 → AN3 → termination In the case of ANS = 011B and ANE = 011B: AN3 → termination 452 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 19 8/10-BIT A/D CONVERTER 19.4 Explanation of Operation of 8/10-bit A/D Converter MB90330A Series ■ Operation of Continuous Conversion Mode In the continuous conversion mode, the analog inputs set by the ANS and ANE bits are sequentially converted, the analog input set by the ANE bit is resumed at the end of conversion of the termination channel set by the ANS bit, and the A/D conversion operation is continued. When the start channel and the termination channel are same (ANS = ANE), the conversion of only channels specified by the ANS is repeated. For the operation in the continuous conversion mode, the setting as shown in Figure 19.4-2 is necessary. Figure 19.4-2 Setting of Continuous Conversion Mode bit15 bit14 bit13 bit12 bit11 bit10 ADCS BUSY INT S10 ADCR ADMR ST1 INTE ST0 bit9 PAUS STS1 STS0 STRT CT1 bit7 bit6 Reserved bit8 MD1 MD0 0 1 0 CT0 bit5 bit4 bit3 bit2 bit1 bit0 Reserved 0 Store conversion data ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0 ADER ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 : Used bit : Set bit corresponding to using pin to "1". 1 : Set "1" 0 : Set "0" Example of Conversion Order in Continuous Conversion Mode is shown below. In the case of ANS = 000B and ANE = 011B: AN0 → AN1 → AN2 → AN3 → AN0 → repeat In the case of ANS = 011B and ANE= 011B: AN3 → AN3 → repeat CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 453 CHAPTER 19 8/10-BIT A/D CONVERTER 19.4 Explanation of Operation of 8/10-bit A/D Converter MB90330A Series ■ Operation of Pause-conversion Mode In the stop conversion mode, the analog input set by the ANS and ANE bits is converted by being suspended for every channel, the analog input set by the ANE bit is resumed at the end of conversion of the termination channel set by the ANS bit, and the operation of A/D conversion and suspension is continued. When the start channel and the termination channel are same (ANS = ANE), the conversion of only channels specified by the ANS is repeated. When the conversion is restarted during the suspension, the start factor specified by the STS1 and STS0 bits is generated. For the operation in the stop conversion mode, the setting as shown in Figure 19.4-3 is necessary. Figure 19.4-3 Setting of Operation of Pause Conversion Mode bit15 bit14 bit13 bit12 bit11 bit10 ADCS ADCR BUSY INT S10 ST1 bit9 INTE PAUS STS1 STS0 STRT ST0 CT1 bit7 bit6 Reserved bit8 MD1 MD0 0 1 1 bit5 bit4 bit3 bit2 bit1 bit0 0 Store conversion data CT0 ADMR ANS3 ANS2 ANS1 ANS0 ANE3 ANE2 ANE1 ANE0 ADER ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 : Used bit : Set bit corresponding to using pin to "1". 1 : Set "1" 0 : Set "0" Example of Conversion Order in Pause-conversion Mode is shown below. In the case of ANS=000B, ANE=011B: AN0 → Suspension → AN1 → Suspension → AN2 → Suspension → AN0 → Repetitive In the case of ANS = 011B and ANE = 011B: AN3 → Suspension → AN3 → Suspension → Repetitive 454 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 19 8/10-BIT A/D CONVERTER 19.4 Explanation of Operation of 8/10-bit A/D Converter MB90330A Series 19.4.1 Conversion Operation Using μDMAC or EI2OS The 10-bit A/D converter allows the transfer of A/D conversion result to memory using the μDMAC or EI2OS. ■ Conversion Operation Using μDMAC or EI2OS Figure 19.4-4 shows the operation flow when using the μDMAC or EI2OS. Figure 19.4-4 Example of Operation Flow Chart when μDMAC or EI2OS is Used A/D conversion start Sample hold μDMAC or EI2OS start A/D convert start Conversion data transmission A/D conversion end Specified number of times* end? YES Interrupt processing NO Interrupt generation Interrupt clear *: Decided by the setting of μDMAC or EI2OS By using the μDMAC or EI2OS, the conversion data protection function allows the assured data transfer to the memory without losing data even in the continuous conversion. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 455 CHAPTER 19 8/10-BIT A/D CONVERTER 19.4 Explanation of Operation of 8/10-bit A/D Converter 19.4.2 MB90330A Series A/D-converted Data Protection Function When the A/D conversion is executed in the interrupt enable status, the conversion data protection function works. ■ A/D-converted Data Protection Function Since this A/D converter has only one data register to store the converted data, the A/D conversion operation rewrites the data stored in data register at the conversion termination. Therefore, when the converted data transfer to the memory is delayed, a part of previous data may be lost. To cope with this problem, when the interrupt is enabled (INTE = 1), the data protection function operates as follows: ● Data protection function when μDMAC or EI2OS is not used When the converted data is stored in the A/D data register (ADCR), the INT bit of the A/D control status register "H" level (ADCS1) is set to "1". While this INT bit is set to "1", the A/D conversion is in the temporally stopped state. When the INT bit is cleared after the A/D data register (ADCR) transferred to the memory, etc. in the interrupt routine, the stopped state is released. ● Data protection function when μDMAC or EI2OS is used When the μDMAC or EI2OS is used to specify the continuous conversion, the PAUS bit of A/D control status register "H" level (ADCS1) is set to "1" in the period from the conversion termination to the completion of converted data transfer from the data register to the memory with the μDMAC or EI2OS, the A/D conversion operation is stopped, and the next conversion data is not stored. When the data transfer to the memory is completed, the PAUS bit is cleared to "0" and the conversion operation is restarted. Figure 19.4-5 shows the flow of the data protection function when using the μDMAC or EI2OS. 456 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 19 8/10-BIT A/D CONVERTER 19.4 Explanation of Operation of 8/10-bit A/D Converter MB90330A Series Figure 19.4-5 Data Protection Function Flow when μDMAC or EI2OS is Used A/D continuous conversion start Converted for 1 time Store in A/D data register Converted for 2 times NO A/D suspend YES Store in A/D data register Converted for 3 times continue Converted for all continue Store in A/D data register Interrupt processing routine A/D initialize or stop END Note: Flow at A/D converter operation stop is omitted. Notes: • The converted data protection function operates only in the interrupt enabled (ADCS1: INTE=1) status. • When the μDMAC or EI2OS operates, the A/D conversion is suspended, and the interrupt is disabled, the A/D conversion may operate to write new data before the old data transfer. Also when the conversion is restarted during the suspension, the old data are destroyed. • When the conversion is restarted during the suspension, the waiting data are destroyed. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 457 CHAPTER 19 8/10-BIT A/D CONVERTER 19.5 Precautions when Using 8/10-bit A/D Converter 19.5 MB90330A Series Precautions when Using 8/10-bit A/D Converter Precautions when using 8/10-bit A/D converter is indicated. ■ Precautions when Using 8/10-bit A/D Converter ● Analog input pin The A/D input pin is in the common use with the input-output pins of port 7 and port 8 to be used by switching between the port 7 and port 8 direction register (DDR7 and DDR8) and the analog input enable register (ADER). Write "0" to the corresponding bits of DDR7 and DDR8 to input the port setting and set the analog input mode (ADEx = 1) to the ADER register to fix the port side input gate for pins to be used as analog input. When the intermediate level signal is input in the port input mode (ADEx = 0), the input leak current flows through the gate. ● Notes on using in Internal timer (16-bit reload timer 1) Set the input value of internal timer to the inactive side ("L" for the internal timer) when setting the STS1 and STS0 bits of A/D control status register "H" level (ADCS1) to start the A/D converter by the internal timer. When it is set to the active side, the operation may be started at the same time of writing on the ADCS1 register. Set the STS1 and STS0 in the status of the "1" input to the ADTG and the "0" output from the internal timer (PPG1). ● Turning-on sequence of power supply to A/D converter and analog inputs Apply the A/D converter power supply (AVcc and AVRH) and the analog input (AN0 to AN15) always after or simultaneously turning on the digital power supply (Vcc). In addition, turn off the A/D converter power supply and the analog input after or simultaneously turn off the digital power supply (Vcc). ● Power supply voltage of the A/D converter Keep the A/D converter power supply voltage (AVcc) not to exceed the digital power supply voltage (Vcc) to prevent the latch up. 458 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 19 8/10-BIT A/D CONVERTER 19.6 Example of program-1 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Single Mode) MB90330A Series 19.6 Example of program-1 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Single Mode) This section shows the A/D conversion program started in single mode EI2OS ■ Example of EI2OS Start Program in Single Mode ● Processing specification Conversion is performed up to analog inputs AN1 to AN3. The converted data is transferred to addresses 200H to 205H. Resolution is assumed to be ten bits. Startup is performed by software. Figure 19.6-1 shows flow of the EI2OS start program (single mode). Figure 19.6-1 Flow of the EI2OS Start Program (single Mode) Activation start AN1 Interrupt EI2OS transfer AN2 Interrupt EI2OS transfer AN3 Interrupt EI2OS transfer End Interrupt sequence Parallel process CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 459 CHAPTER 19 8/10-BIT A/D CONVERTER 19.6 Example of program-1 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Single Mode) ● Coding example MB90330A Series BAPL EQU 000100H ; Buffer address pointer lower BAPM EQU 000101H ; Buffer address pointer middle BAPH EQU 000102H ; Buffer address pointer upper ISCS EQU 000103H ; EI2OS status register IOAL EQU 000104H ; I/O address register lower IOAH EQU 000105H ; I/O address register upper DCTL EQU 000106H ; Data counter lower DCTH EQU 000107H ; Data counter upper DDR7 EQU 000017H ; Port 7 direction register ADER0 EQU 00001EH ; Analog input enable register 0 ICR12 EQU 0000BCH ; Interrupt control register for A/DC ADMR EQU 000045H ; A/D conversion channel set register ADCS0 EQU 000040H ; A/D Control status register ADCS1 EQU 000041H ; ADCR0 EQU 000042H ; A/D data register ADCR1 EQU 000043H ; ;----------Main Program-----------------------------------------------------------CODE CSEG START: ; Stack pointer (SP), etc. shall be initialized. AND CCR, #0BFH ; Disables the interrupt. MOV ICR12, #00H ; Interrupt levels (0 strength) MOV BAPL, #00H ; Setting the converted data storage address MOV BAPM, #02H ; (uses 200H to 205H) MOV BAPH, #00H ; MOV ISCS, #18H ; Transferring the word data, Transferred address + 1, ; I/O → Transfer to the memory 460 MOV IOAL, #42H ; As forwarding former address pointer MOV IOAH, #00H ; Setting analog data register address MOV DCTL, #03H ; Transferring the EI2OS for three times, Performing ; the conversion for the same number of times. MOV DDR7, #11110001B ; P71 to P73 are set to input. MOV DCTH, #00H ; MOV ADER0, #00001110B ; P71/AN1 to P73/AN3 are set in the analog input. MOV ADMR, #013H ; AN1 to AN3 CH are converted MOV ADCSL, #000H ; Single startup MOV ADCSH, #0A2H ; Starting the software, Starting the A/D conversion, ; Enabling the interrupt MOV ILM, #07H ; Sets ILM in PS to level 7 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E OR CHAPTER 19 8/10-BIT A/D CONVERTER 19.6 Example of program-1 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Single Mode) CCR, #40H ; Interruption permission MOV A,#00H MOV A,#01H BRA LOOP MB90330A Series LOOP: ; Infinite loop ;----------Interrupt Program-----------------------------------------------------------ED_INT1: MOV I:ADCS1, #00H RETI CODE ; Stopping the A/D, Disabling the interrupt and the ; flag clearance ; Returns from interrupt. ENDS ;----------Vector Settings-----------------------------------------------------------------VECT VECT CSEG ABS=0FFH ORG 0FF6CH DSL ED_INT1 ORG 0FFDCH DSL START DB 00H ; Reset vector setting ; Set Single-chip mode ENDS END CM44-10129-6E ; The vector is set in interruption #36(24H). START FUJITSU MICROELECTRONICS LIMITED 461 CHAPTER 19 8/10-BIT A/D CONVERTER 19.7 Example of Program-2 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Continuous Mode) 19.7 MB90330A Series Example of Program-2 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Continuous Mode) This section shows the A/D conversion program started the EI2OS in continuous mode. ■ Example of EI2OS Start Program in Continuous Mode ● Processing specification Convert the analog inputs AN3 to AN5 twice to acquire two converted data for each of channels. The converted data is transferred to addresses 600H to 60BH. Resolution is assumed to be ten bits. Start up is performed by 16-bit reload timer 0 Figure 19.7-1 shows flow of the EI2OS start program (continuous mode). Figure 19.7-1 Flow of the EI2OS Start Program (Continuous Mode) Activation start After 6 times transfer AN3 Interrupt EI2OS transfer AN4 Interrupt EI2OS transfer Interrupt sequence AN5 Interrupt EI 2OS transfer End 462 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E MB90330A Series CHAPTER 19 8/10-BIT A/D CONVERTER 19.7 Example of Program-2 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Continuous Mode) ● Coding example BAPL EQU 000100H ; Buffer address pointer lower BAPM EQU 000101H ; Buffer address pointer middle BAPH EQU 000102H ; Buffer address pointer upper ISCS EQU 000103H ; EI2OS status register IOAL EQU 000104H ; I/O address register lower IOAH EQU 000105H ; I/O address register upper DCTL EQU 000106H ; Data counter lower DCTH EQU 000107H ; Data counter upper DDR7 EQU 000017H ; Port 7 direction register ADER0 EQU 00001EH ; Analog input enable register 0 ICR12 EQU 0000BCH ; Interrupt control register for A/DC ADMR EQU 000045H ; A/D conversion channel set register ADCS0 EQU 000040H ; A/D Control status register ADCS1 EQU 000041H ; ADCR0 EQU 000042H ; A/D data register ADCR1 EQU 000043H ; TMCSR1L EQU 000062H ; Timer control status register 0 Low TMCSR0H EQU 000063H ; TMRLR0L EQU 000064H ; Reload Register 0 TMRLR0H EQU 000065H ; ;----------Main Program-----------------------------------------------------------CODE CSEG START: ; Stack pointer (SP), etc. shall be initialized. AND CCR,#0BFH ; Disables the interrupt. MOV ICR12, #08H ; Interrupt level 0 (the strongest), Interrupt enabled MOV BAPL, #00H ; Setting the converted data storage address MOV BAPM, #06H ; (uses 600H to 60BH) MOV BAPH, #00H ; MOV ISCS, #18H ; Transferring the word data, Transferred address +, ; I/O → Transfer to the memory CM44-10129-6E MOV IOAL, #42H ; As forwarding former address pointer MOV IOAH, #00H ; Setting analog data register address MOV DCTL, #06H ; EI2OS transfer for 6 times, Transfer for 3ch x 2 ; times MOV DCTH, #00H MOV DDR7, #00000000B ; P70 to P77 are set in the input. MOV ADER0, #00111000B ; P73/AN3 to P75/AN5are set in the analog input. MOV ADMR, #035H ; AN3 to AN5 CH are converted. FUJITSU MICROELECTRONICS LIMITED 463 CHAPTER 19 8/10-BIT A/D CONVERTER 19.7 Example of Program-2 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Continuous Mode) MOV ADCS0, #080H ; Continuous mode MOV LOOP: ADCS1, #0A8H MB90330A Series ; Starting the 16-bit timer, Starting the A/D ; conversion, Interrupting permission MOVW TMRLR0L, #0320H ; Setting the timer value 800 (320H) 66 ms MOV TMCSR0H, #00H ; Setting the clock source to 83 ns, External trigger ; Interdiction MOV TMCSR0L, #12H ; Disabling the timer output, Disabling the interrupt, ; Enabling the reload MOV TMCSR0L, #13H ; 16-bit timer startup MOV ILM, #07H ; Sets ILM in PS to level 7 OR CCR, #40H ; Interruption permission MOV A,#00H ; Infinite loop MOV A,#01H BRA LOOP ;----------Interrupt Program-----------------------------------------------------------ED_INT1: MOV I:ADCS1, #80H ; The A/D does not stop, The A/D conversion process ; program started by the EI2OS with the interrupt flag ; clearance in the stop mode is shown. ; Interdiction RETI CODE ; Returns from interrupt. ENDS ;----------Vector Setting-----------------------------------------------------------------VECT VECT CSEG ABS=0FFH ORG 0FF7CH DSL ED_INT1 ORG 0FFDCH DSL START DB 00H ; Reset vector setting ; Setting Single-chip mode ENDS END 464 ; The vector is set in interruption #36(24H). START FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 19 8/10-BIT A/D CONVERTER 19.8 Example of Program-3 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Stop Mode) MB90330A Series 19.8 Example of Program-3 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Stop Mode) This section shows the A/D conversion program started the EI2OS in stop mode. ■ Example of EI2OS Start Program in Continuous Mode ● Processing specification Analog input AN3 is converted for 12 times in a constant period. The converted data is transferred to addresses 600H to 617H. Resolution is assumed to be ten bits. Start up is performed by 16-bit reload timer 0. Figure 19.8-1 shows flow of the EI2OS start program (stop mode). Figure 19.8-1 Flow of the EI2OS Start Program (Stop Mode) Activation start AN3 Interrupt After 12 times transfer EI2OS transfer STOP Interrupt sequence External edge start End CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 465 CHAPTER 19 8/10-BIT A/D CONVERTER 19.8 Example of Program-3 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Stop Mode) ● Coding example MB90330A Series BAPL EQU 000100H ; Buffer address pointer lower BAPM EQU 000101H ; Buffer address pointer middle BAPH EQU 000102H ; Buffer address pointer upper ISCS EQU 000103H ; EI2OS status register IOAL EQU 000104H ; I/O address register lower IOAH EQU 000105H ; I/O address register upper DCTL EQU 000106H ; Data counter lower DCTH EQU 000107H ; Data counter upper DDR7 EQU 000017H ; Port 7 direction register ADER0 EQU 00001EH ; Analog input enable register 0 ICR12 EQU 0000BCH ; Interrupt control register for A/DC ADMR EQU 000045H : A/D conversion channel set register ADCS0 EQU 000040H ; A/D Control status register ADCS1 EQU 000041H ; ADCR0 EQU 000042H ; A/D data register. ADCR1 EQU 000043H ; TMCSR0L EQU 000062H ; Timer control status register 0 Low TMCSR0H EQU 000063H ; TMRLR0L EQU 000064H ; Reload Register 0 TMRLR0H EQU 000065H ; ;----------Main Program-----------------------------------------------------------CODE CSEG START: 466 ; Stack pointer (SP), etc. shall be initialized. AND CCR,#0BFH ; Disables the interrupt. MOV ICR12, #08H ; Interrupt levels (0 strength) MOV BAPL, #00H ; Setting the converted data storage address MOV BAPM, #06H ; (uses 600H to 617H). MOV BAPH, #00H ; MOV ISCS, #19H ; Transferring the word data, Transferred address +, ; I/O → Transfer to the memory, Termination at the ; resource request MOV IOAL, #42H ; As forwarding former address pointer MOV IOAH, #00H ; Setting analog data register address MOV DCTL, #0CH ; EI2OS transfer for 12 times, 3ch only MOV DCTH, #00H ; MOV DDR7, #00000000B ; P70 to P77 are set in the input MOV ADER, #00001000B ; P73/AN3 are set in the analog input MOV ADMR, #033H ; AN3 CH is converted FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E MOV CHAPTER 19 8/10-BIT A/D CONVERTER 19.8 Example of Program-3 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Stop Mode) ADCS0, #0C0H ; Stop mode MOV ADCS1, #0A8H MB90330A Series LOOP: ; Starting the 16-bit timer, Starting the A/D ; conversion, Interrupting permission MOVW TMRLR0L, #0320H ; Setting the timer value 800 (320H) 66 ms MOV TMCSR0H, #00H ; Setting the clock source to 83 ns, External trigger ; Interdiction MOV TMCSR0L, #12H ; Disabling the timer output, Disabling the interrupt, ; Enabling the reload MOV TMCSR0L, #13H ; 16-bit timer startup MOV ILM, #07H ; Sets ILM in PS to level 7 OR CCR, #40H ; Interruption permission MOV A,#00H ; Infinite loop MOV A,#01H BRA LOOP ;----------Interrupt Program-----------------------------------------------------------ED_INT1: MOV I:ADCS1, #80H ; The A/D does not stop, The A/D conversion process ; program started by the EI2OS with the interrupt flag ; clearance in the stop mode is shown. ; Interdiction RETI CODE ; Returns from interrupt. ENDS ;----------Vector Settings-----------------------------------------------------------------VECT VECT CSEG ABS=0FFH ORG 0FF6CH DSL ED_INT1 ORG 0FFDCH DSL START DB 00H ; Reset vector setting ; Setting Single-chip mode ENDS END CM44-10129-6E ; The vector is set in interruption #36(24H). START FUJITSU MICROELECTRONICS LIMITED 467 CHAPTER 19 8/10-BIT A/D CONVERTER 19.8 Example of Program-3 of 8/10-bit A/D Converter (Example of Starting the EI2OS in the Stop Mode) 468 FUJITSU MICROELECTRONICS LIMITED MB90330A Series CM44-10129-6E CHAPTER 20 EXTENDED I/O SERIAL INTERFACE This chapter describes an overview of the extended I/O serial interface, the configuration and function of registers, and operations of extended I/O serial interface. 20.1 Outline of Extended I/O Serial Interface 20.2 Register in Extended I/O Serial Interface 20.3 Operation of Extended I/O Serial Interface CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 469 CHAPTER 20 EXTENDED I/O SERIAL INTERFACE 20.1 Outline of Extended I/O Serial Interface 20.1 MB90330A Series Outline of Extended I/O Serial Interface The extended I/O serial interface is a serial I/O interface that can transfer data through the adoption of 8-bit × 1 channel configured clock synchronization scheme. LSB first/ MSB first can be selected in data transfer. ■ Outline of Extended I/O Serial Interface The following two operation modes are available for the extended I/O serial interface. • Internal shift clock mode: Transfers data in sync with the internal clock. • External shift clock mode: Transfers data in sync with the clock input through an external pin (SCK). In this mode, transfer operation performed by the CPU instruction is also available by operating the general-use port sharing an external pin (SCK). ■ Block Diagram in Extended I/O Serial Interface Figure 20.1-1 shows the block diagram of extended I/O serial interface. Figure 20.1-1 Block Diagram of Extended I/O Serial Interface Internal data bus Initial value D7 to D0 (LSB first) (MSB first) D0 to D7 Transfer direction selection SIN Read Write SDR (Serial data register) SOT SCK Control circuit Shift clock counter Internal clock 2 1 0 SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT MODE BDS SOE SCOE Interrupt request #38 SMCS Internal data bus 470 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 20 EXTENDED I/O SERIAL INTERFACE 20.2 Register in Extended I/O Serial Interface MB90330A Series 20.2 Register in Extended I/O Serial Interface The configuration and functions of registers used in the extended I/O serial interface are described. ■ List of Register in Extended I/O Serial Interface Figure 20.2-1 shows the list of register in extended I/O serial interface. Figure 20.2-1 List of Register in Extended I/O Serial Interface SMCS 13 bit 15 14 Address : 000059H SMD2 SMD1 SMD0 12 11 10 9 8 Serial mode control SIE SIR BUSY STOP STRT status register (SMCS) (R/W) (R/W) (R/W) (R/W) (R/W) (R) (R/W) (R/W) Initial value 00000010B bit SMCS Address : 000058H 7 6 5 4 3 2 1 0 Serial mode control MODE BDS SOE SCOE status register (SMCS) (R/W) (R/W) (R/W) (R/W) Initial value XXXX0000B SDR bit 7 Address : 00005AH D7 6 bit SDCR Address : 00005BH 14 5 4 3 2 1 0 Serial data register (SDR) D1 D0 D6 D5 D4 D3 D2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value XXXXXXXXB 15 MD (R/W) 13 12 11 10 9 8 DIV3 DIV2 DIV1 DIV0 Communication prescaler control register (SDCR) (R/W) (R/W) (R/W) (R/W) Initial value 0XXX0000B R/W : Readable/Writable : Undefined X : Undefined CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 471 CHAPTER 20 EXTENDED I/O SERIAL INTERFACE 20.2 Register in Extended I/O Serial Interface 20.2.1 MB90330A Series Serial Mode Control Status Register (SMCS) The configuration and functions of Serial mode control status register (SMCS) is described. ■ Serial Mode Control Status Register (SMCS) Serial mode control status register (SMCS) is a register which controls the transfer operating mode of serial I/O. Figure 20.2-2 shows the bit configuration of serial mode control status register (SMCS). Figure 20.2-2 Bit Configuration of Serial Mode Control Status Register (SMCS) SMCS 13 bit 15 14 Address : 000059H SMD2 SMD1 SMD0 11 12 10 9 8 Serial mode control SIE SIR BUSY STOP STRT status register (R/W) (R/W) (R/W) (R/W) (R/W) (R) (R/W) (R/W) Initial value 00000010B bit SMCS Address : 000058H 7 6 5 3 4 2 1 0 Serial mode control MODE BDS SOE SCOE status register (R/W) (R/W) (R/W) (R/W) Initial value XXXX0000B R/W : Readable/Writable : Undefined Function of each bit of serial mode control status register (SMCS) is described as follows: [bit 15 to bit 13] SMD2,SMD1,SMD0:Serial Shift Clock Mode (shift clock selection) The serial shift clock mode is selected. Table 20.2-1 and Table 20.2-2 show the settings of the serial shift clock mode. Table 20.2-1 Serial Shift Clock Mode Selection SMD2 SMD1 SMD0 φ=24 MHz div=8 φ=12 MHz div=4 φ=6 MHz div=6 Value of dividing frequency 0 0 0 1.5 MHz 1.5 MHz 500 kHz 2 0 0 1 750 kHz 750 kHz 250 kHz 4 0 1 0 188 kHz 188 kHz 62.5 kHz 16 0 1 1 93.4 kHz 93.4 kHz 31.2 kHz 32 1 0 0 46.9 kHz 46.9 kHz 15.6 kHz 64 1 0 1 External shift clock mode 1 1 0 Setting disabled 1 1 1 Setting disabled Initialized to "000B" by reset. Rewriting under forwarding is a interdiction. Shift clock includes five alternatives of internal shift clock and one alternative of external shift clock. The external shifts. Please set neither "110B" nor "111B" to SMD2, SMD1, and SMD0. 472 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 20 EXTENDED I/O SERIAL INTERFACE 20.2 Register in Extended I/O Serial Interface MB90330A Series Table 20.2-2 Example of Settings of the Communication Prescaler (SDCR) (Machine clock) Div Machine cycle (Recommended Setting) MD DIV3 DIV2 DIV1 DIV0 1 1 0 0 0 0 3 MHz 2 1 0 0 0 1 6 MHz 4 1 0 0 1 1 12 MHz 8 1 0 1 1 1 24 MHz Providing shift operation for each instruction is also possible by defining SCOE=0 on clock selection and operating the port sharing SCK pin. [bit 12] SIE: Serial I/0 Interrupt Enable (enabling serial I/O interrupt) Serial I/O interrupt request is controlled as shown in the table below. SIE Operation 0 Interrupt disabled [Initial value] 1 Serial I/O interrupt enabled • This bit is initialized to "0" at reset. • This bit can be read and written. [bit 11] SIR: Serial I/0 Interrupt Request (serial I/O interrupt request) On completion of the serial data transfer, this bit is set to "1". And when this bit turns to "1" on interrupt enabled (SIE= 1), an interrupt request to the CPU occurs. A clear condition is different according to the MODE bit. • When MODE bit is "0", it is cleared by writing "0" to SIR bit. • When MODE bit is "1", it is cleared by writing to or reading SDR bit. • Regardless of values of MODE bit, it is cleared by resetting or writing "1" to STOP bit. • It is not significant to write "1". • On reading read/modify/write instructions, "1" is read in all cases. [bit 10] BUSY (forwarding status display) This bit indicates whether serial transfer is running or not. BUSY Operation 0 Stop or serial data register R/W standby [Initial value] 1 State of serial transfer • This bit is initialized to "0" at reset. • This bit can only be read. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 473 CHAPTER 20 EXTENDED I/O SERIAL INTERFACE 20.2 Register in Extended I/O Serial Interface MB90330A Series [bit 9] STOP (stop bit) This bit forcibly suspends serial transfer. When this bit is "1", the state changes into HALT based on STOP=1. STOP Operation 0 Normal Operation 1 Forwarding stop [Initial value] by STOP=1 • This bit is initialized to "0" at reset. • This bit can be read and written. [bit 8] STRT: Start (start bit) It is a bit by which the serial transfer is started. Forwarding is begun by writing "1" in the stopped state. Lines specified as "1" are ignored, where serial transfer operation is on-going and the state is in serial shift register R/W WAIT. • Writing "0" is not significant. • The bit always returns "0" when read. [bit 7 to bit 4] Undefined bit The read value is irregular. Nothing is affected when it is written. [bit 3] MODE (serial mode selection) The startup condition from the stopped state is selected. However, rewriting under the operation is a interdiction. MODE Operation 0 Started when STRT = 1. [Initial value] 1 Started by reading or writing the serial data register. • This bit is initialized to "0" at reset. • This bit can be read and written. • This bit set to "1" at μDMAC start. [bit 2] BDS: Bit Direction Selection (transfer direction selection) On input and output of the serial data, Select either of the following alternatives: transfer in ascending order from the least significant bit (LSB first); transfer in descending order from the most significant bit (MSB first). BDS Operation 0 LSB first [Initial value] 1 MSB first • This bit is initialized to "0" at reset. • This bit can be read and written. 474 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 20 EXTENDED I/O SERIAL INTERFACE 20.2 Register in Extended I/O Serial Interface MB90330A Series Note: Select transfer direction before writing data to SDR. [bit 1] SOE: Serial Out Enable (serial output permission) Controls the external pin (SOT) for serial I/O. SOE Operation 0 General-purpose port [Initial value] 1 Serial data output • This bit is initialized to "0" at reset. • This bit can be read and written. [bit 0] SCOE: SCk1 Output Enable (shift clock output enable) Controls output of the input/output external pins (SCK1,SCK2) for shift clock. SCOE Operation 0 At the transfer by general-purpose port pin and instruction 1 Shift clock output pin [Initial value] Set this bit to "0", when you transfer data in external shift clock mode for each individual instruction. • Initialized to "0" at reset. • This bit can be read and written. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 475 CHAPTER 20 EXTENDED I/O SERIAL INTERFACE 20.2 Register in Extended I/O Serial Interface 20.2.2 MB90330A Series Serial Data Register (SDR) The configuration and functions of Serial data register (SDR) are described. ■ Serial Data Register (SDR) Figure 20.2-3 shows the bit configuration of the serial data register (SDR). Figure 20.2-3 Bit Configuration of Serial Data Register (SDR) bit 7 SDR Address : 00005AH D7 6 5 4 3 2 1 0 Serial data register D1 D0 D6 D5 D4 D3 D2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value XXXXXXXXB R/W : Readable/Writable X : Undefined The serial data register (SDR) is a serial data register to hold transfer data of the serial I/O. Both writing and reading to and from SDR during transfer are disabled. 476 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 20 EXTENDED I/O SERIAL INTERFACE 20.2 Register in Extended I/O Serial Interface MB90330A Series 20.2.3 Communication Prescaler Control Register (SDCR) The configuration and functions of communication prescaler control register (SDCR) are described. ■ Communication Prescaler Control Register (SDCR) Figure 20.2-4 shows the bit configuration of communication prescaler control register (SDCR). Figure 20.2-4 Communication Prescaler Control Register (SDCR) SDCR bit Address : 00005BH 15 14 MD (R/W) 13 12 11 10 9 8 DIV3 DIV2 DIV1 DIV0 Communication prescaler control register (R/W) (R/W) (R/W) (R/W) Initial value 0XXX0000B R/W : Readable/Writable : Undefined The functions of each bit of the communication prescaler control register (SDCR) are described below. [bit 15] MD: Machine clock divide moDe select Bit to enable the operation of the communication prescaler MD Operation 0 Communication Prescaler stops. 1 Communication Prescaler is operating. [bit 11 to bit 8] DIV3,DIV2,DIV1,DIV0:DIVide3 to DIVide0 These bits determine the machine clock division ratio. DIV3 to DIV0 Rate of division 0000B 1-frequency division 0001B 2-frequency division 0010B 3-frequency division 0011B 4-frequency division 0100B 5-frequency division 0101B 6-frequency division 0110B 7-frequency division 0111B 8-frequency division Note: In the case of making changes to the rate of division, allow for two divisions of intervals as the duration of stabilization of the clock before communication. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 477 CHAPTER 20 EXTENDED I/O SERIAL INTERFACE 20.3 Operation of Extended I/O Serial Interface 20.3 MB90330A Series Operation of Extended I/O Serial Interface Extended I/O interface consists of a serial mode control status register (SMCS) and a serial data register (SDR) and is used to input and output 8-bit serial data. Operation of extended I/O serial interface is described. ■ Outline of Operation of Extended I/O Serial Interface When serial data is input or output, each of input and output operations is performed as described below. ● Input of Serial data The content of the serial data register is output in a bit serial fashion to the serial output pin (SOT pin) in synchronization with the falling edge of the serial shift clock (external clock, internal clock). ● Output of Serial data Input from the serial input pin (SIN pin) into SDR (serial data register) in a bit serial fashion in synchronization with the rising edge of the serial shift clock (external clock, internal clock). The direction of shift (transfer from MSB or LSB) can be specified by the bit of direction specification (BDS) of SMCS (serial mode control status register). Once the transfer completes, the state goes into STOP or into data register R/W wait (or SDR R/W WAIT) by MODE bit of the serial mode control status register (SMCS). To change state into TRANSFER from each of the states, you should do each of the following steps. • To return from HALT, write "0" in STOP bit, and "1" in STRT bit (STOP and STRT can be set concurrently). • To return from serial data register R/W wait (SDR R/W WAIT), read or write the data register. 478 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 20 EXTENDED I/O SERIAL INTERFACE 20.3 Operation of Extended I/O Serial Interface MB90330A Series 20.3.1 Shift Clock Mode Shift clock includes two types of modes; one is Internal Shift Clock Mode, the other is External Shift Clock Mode, both of which are specified by settings of SMCS. Please switch the mode with serial I/O stopped. Reading BUSY bit allows the checking of the state of HALT. ■ Internal Shift Clock Mode Operation is driven by the internal clock, and the shift clock whose duty ratio is 50% is output from SCK pin as an output of the timing of synchronization. Data is forwarded by one bit per a clock. Transfer rate can be calculated using the following formula. transfer rate (S) = A Internal clock machine cycle (A) A indicates the rate of division represented by SMD bit of SMCS. (φ/div)/2, (φ/div)/22, (φ/div)/24, (φ/div)/25, (φ/div)/26 ■ External Shift Clock Mode In synchronization with the external shift clock input through SCK pin, 1 bit of data is transferred for each individual clock. Allowed transfer rate varies from DC to 1/(8 machine cycles). When 1 machine cycle = 62.5 ns for example, a maximum of 2 MHz is allowable. Transfer by instruction by instruction can be accomplished by setting as described below. • Select the external shift clock mode, and set SCOE bit of SMCS to "0". • Write "1" in the direction register of which the port shares SCK pin, and place the port in the output mode. Once the settings complete as indicated above, write "1" or "0" in the data register (PDR) of the port, then the value to be delivered to SCK pin is captured as the external clock and transfer operation is accomplished. Have the shift clock start at "H". Note: Writing to SMCS.SDR during serial I/O operation is disabled. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 479 CHAPTER 20 EXTENDED I/O SERIAL INTERFACE 20.3 Operation of Extended I/O Serial Interface 20.3.2 MB90330A Series Operation State of Serial I/O The states of serial I/O operation includes the following 4 types of states; STOP, HALT, R/W WAIT of SDR, and TRANSFER. ■ Operation State of Serial I/O ● STOP State On RESET or in the state of writing "1" in STOP bit of SMCS, the shift counter is initialized, resulting in SIR=0. Returning from the stop state is performed by setting STOP = 0 and STRT = 1 (both can be set at the same time). Even though STRT=1 is provided when STOP=1, transfer operation is not executed, since STOP bit is upper than STRT bit. ● HALT State When MODE bit is "0", termination of transfer provides SMCS with BUSY=0 and SIR=1, resulting in the initialization of the counter to go into HALT state. To return from the HALT state, set STRT to "1", then transfer operation restarts. ● Serial data register R/W standby When MODE bit of SMCS is "1", termination of serial transfer provides SMCS with BUSY=0 and SIR=1, resulting in the serial data register to go into R/W WAIT state. If the interrupt enable register is enabled, this block issues interrupt signals. To return from the R/W WAIT state, when the serial data register is read or written, then BUSY is set to "1", which allows to transfer operation to restart. ● Transfer State It is a state to do the serial transfer by BUSY = 1. MODE bit triggers the transition to the state of HALT and R/W WAIT respectively. Figure 20.3-1 shows the transition diagram of each state, and Figure 20.3-2 shows the conceptual diagram of read/write of the serial data register. 480 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 20 EXTENDED I/O SERIAL INTERFACE 20.3 Operation of Extended I/O Serial Interface MB90330A Series Figure 20.3-1 Transition Diagram of Operation in Extended I/O Serial Interface Reset Stop state (Transfer complete) STOP=0 & STRT=0 STOP=1 STRT=0, BUSY=0 MODE=0 STOP=0 & STRT=1 MODE=0 & STOP=0 & END STOP=1 STOP STRT=0, BUSY=0 STOP=0 & STRT=1 Transfer operation Serial data register R/wait MODE=1 & END & STOP=1 STRT=1, BUSY=1 STOP=1 STRT=1, BUSY=0 MODE=1 SDR R/W & MODE=1 Serial data Figure 20.3-2 Conceptual Diagram of Reading/writing Serial Data Register Data bus Data bus Read SIN Write Interrupt output SOT Extended I/O serial interface Read Write CPU (1) (2) Interrupt input Data bus Interrupt controller (1) When MODE=1, transfer is terminated by the shift clock counter. This allows SIR=1 to go into read/ write state. If the SIE bit is "1", the interruption signal is generated. However, when SIE is inactive, or when writing "1" in STOP causes the suspend of transfer, interrupt signals are not generated. (2) Once the serial data register is read or written, interrupt requests are cleared, and serial transfer starts. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 481 CHAPTER 20 EXTENDED I/O SERIAL INTERFACE 20.3 Operation of Extended I/O Serial Interface 20.3.3 MB90330A Series Start/stop Timing of Shift Operation and Timing of I/O Start/stop timing of shift operation and timing of I/O is described. ■ Start/stop Timing of Shift Operation and Timing of I/O • Start STOP bit of Start SMCS is set to "0", while STRT bit to "1". • Stop One halt is triggered from the termination of transfer; the other from STOP=1. - Halt from STOP=1: Halts staying with SIR=0, regardless of MODE bit. - Halt from transfer termination: Halts with SIR=1, regardless of MODE bit. Regardless of MODE bit when BUSY bit is in the state of serial transfer, it is set to "1", and when in HALT or R/W WAIT state, it is set to "0". Please read this bit to confirm forwarding. The following chart shows the operation for each mode and the timing of halt operation. DO7 to DO0 in figure shows output data. ● Internal shift clock mode (LSB first) Figure 20.3-3 Start/stop Timing of Shift Operation (Internal Clock) "1" Output SCK (Transfer start) STRT (Transfer complete) MODE=0 BUSY DO0 SOT DO7 (Data hold) ● External shift clock mode (LSB first) Figure 20.3-4 Start/stop Timing of Shift Operation (External Clock) SCK STRT (Transfer start) (Transfer complete) MODE=0 BUSY SOT DO0 DO7 (Data hold) ● For instruction shift in external shift clock mode (LSB first) In instruction shift, when "1" is written to the bit corresponding to SCK of PDR, "H" is output, and when "0" is written, "L" is output (where external shift clock mode is selected, and SCOE=0). 482 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 20 EXTENDED I/O SERIAL INTERFACE 20.3 Operation of Extended I/O Serial Interface MB90330A Series Figure 20.3-5 When Instruction Shift is Performed in the External Shift Clock Mode. SCK bit "0" of PDR SCK SCK bit "1" of PDR SCK bit "0" of PDR (Transfer end) STRT When Mode = 0 BUSY SOT DO7 (Data hold) DO6 ● Stop by STOP=1 (LSB first, At internal clock) Figure 20.3-6 Stop Timing when STOP Bit is Assumed to be "1" "1" Output SCK (Transfer complete) (Transfer start) STRT MODE=0 BUSY STOP SOT DO3 DO4 (Data hold) DO5 ■ Operation during Transfer Serial Data During transferring serial data, data from the serial output pin (SOT) is output on the falling edge of the shift clock, data of the serial input pin (SIN) is input on the rising edge. ● LSB first (when BDS bit is set to "0") Figure 20.3-7 Shift Timing of I/O (LSB First) SCK SIN DI0 DI1 SOT DO0 DO1 SIN Input DI3 DI2 DI4 SOT Output DO3 DO2 DO4 DI5 DI6 DI7 DO5 DO6 DO7 ● MSB first (when BDS bit is set to "1") Figure 20.3-8 Shift Timing of I/O (LSB First) SCK CM44-10129-6E SIN DI7 DI6 SOT DO7 DO6 SIN Input DI4 DI5 DI3 SOT Output DO4 DO5 DO3 DI2 DI1 DI0 DO2 DO1 DO0 FUJITSU MICROELECTRONICS LIMITED 483 CHAPTER 20 EXTENDED I/O SERIAL INTERFACE 20.3 Operation of Extended I/O Serial Interface 20.3.4 MB90330A Series Interrupt Function Extended I/O serial interface can generate the interrupt request to the CPU. ■ Interruption Function of Extended I/O Serial Interface Upon completion of data transfer, SIR bit indicating an interrupt flag is set, and when SIE bit of the SMCS enabling interrupts is "1", the interrupt request is output to the CPU. Figure 20.3-9 shows the output timing of interrupt signal. Figure 20.3-9 Output Timing of Interruption Signal SCK (Transfer complete) BUSY SIR MODE=1 SIE=1 RD/WR of SDR SOT 484 DO6 DO7 (Data hold) FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART This chapter explains the function and operation of the UART. 21.1 Overview of UART 21.2 UART Block Diagram 21.3 UART Pins 21.4 Register of UART 21.5 UART Interrupt 21.6 UART Baud Rate 21.7 Explanation of Operation of UART 21.8 Notes on Using UART 21.9 Example of UART Programming CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 485 CHAPTER 21 UART 21.1 Overview of UART 21.1 MB90330A Series Overview of UART UART is a general purpose serial data communication interface for synchronous or asynchronous (start-stop synchronization) communications with external devices. Not only the typical function of bi-directional communication (normal mode), but also the function of master/slave communication (multiprocessor mode: only supported master side) are supported. ■ UART Function ● UART function UART, or a general serial data communication interface that sends and receives serial data to and from other CPU and peripherals, has the functions listed in Table 21.1-1. Table 21.1-1 UART Function Functions Data buffer Transfer mode Baud rate Full-duplicate double-buffer • Clock synchronous (No start/stop bit) • Clock asynchronous (start-stop synchronization to clock) • Dedicate baud-rate generator • External clock input enabled. Data length • 8 bits or 7 bits (in the asynchronous normal mode only) • 1 to 8 bit (s) (synchronous mode only) Signal type NRZ (Non Return to Zero) type Detection of receive error Interrupt request Master/slave type communication function (multi processor mode) • Framing error • Overrun error • Parity error (Not supported in operation mode 1) • Receive interrupt (receive, detection of receive error) • Transmission interrupt (transmission complete) • Extended intelligent I/O service for both sending and receiving Support of (EI2OS) μDMA Capable of 1 (master) to n (slaves) communication (available just as master) Note: At clock synchronous transfer, data is transferred alone with neither start nor stop bit added. 486 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.1 Overview of UART MB90330A Series Table 21.1-2 UART Operation Modes Data length Operating mode Without Parity With Parity 7 bits or 8 bits Synchronous type Length of Stop Bit Asynchronous 0 Normal mode 1 Multiprocessor mode 8 bits + 1 *1 - Asynchronous 1 bit or 2 bits *2 2 Normal mode 1 to 8 bits - Synchronous None -: Unavailable *1: "+1" indicates the address/data select bit (A/D) used for communication control. *2: During reception, only one bit is detected as the stop bit. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 487 CHAPTER 21 UART 21.2 UART Block Diagram 21.2 MB90330A Series UART Block Diagram UART is composed of the following block. ■ UART Block Diagram Figure 21.2-1 UART Block Diagram Control bus Receive interrupt signal UART prescaler control register (UTCR0 to UTCR3) UART prescaler reload register (UTRLR0 to UTRLR3) Clock selector Machine clock Dedicated baud rate generator Pin Transfer clock Transmit interrupt signal Receive clock Receive control circuit Transmit control circuit Start bit detection circuit Transmit start circuit Receive bit counter Transmit bit counter Receive parity counter Transmit parity counter SCK0 to SCK3 External clock Pin SOT0 to SOT3 Receiving shift register Pin Transmit shift register SIN0 to SIN3 Receiving end SIDR0 to SIDR3 SODR0 to SODR3 Transmission end Receive state judge circuit F2MC - 16LX Bus SMR0 to SMR3 register 488 MD1 MD0 SCKL M2L2 M2L1 M2L0 SCKE SOE SCR0 to SCR3 register PEN P SBL CL AD REC RXE TXE SSR0 to SSR3 register FUJITSU MICROELECTRONICS LIMITED PE ORE FRE RDRF TDRE BDS RIE TIE CM44-10129-6E CHAPTER 21 UART 21.2 UART Block Diagram MB90330A Series ● Clock selector Dedicated baud rate generator, selecting the send and receive clock from external input clocks. ● Reception Control Circuit The reception control circuit is configured with the reception bit counter, start bit detecting circuit, and reception parity counter. The receive bit counter counts receiving data. Once this counter completes receiving a piece of data based on the specified data length, then a receiving interrupt request is generated. The start bit detection circuit is a circuit that detects the start bit from serial input signals. When detecting the start bit, this circuit writes the data in the serial input data registers 0 to 3 (SIDR0 to SIDR3) with shifting based on specified transfer rates. The receive parity counter calculates parity in received data. ● Transmission Control Circuit The transmission control circuit is configured with the transmission bit counter, transmission start circuit, and transmission parity counter. The send bit counter counts sending data. Once this counter completes sending a piece of data based on the specified data length, then a sending interrupt request is generated. The sending start circuit starts sending operation by writing to the serial output data registers 0 to 3 (SODR0 to SODR3). The transmit parity counter generates a parity bit for data to be transmitted if the data is paritychecked. ● Receive shift register This circuit captures the receiving data, shifting bit by bit, that is input from SIN0 to SIN3 pins. On completion of reception, this circuit transfers the receiving data to the serial input data registers 0 to 3 (SIDR0 to SIDR3). ● Transmit shift register The data that is written to the serial output data registers 0 to 3 (SODR0 to SODR3) is transferred to the sending shift register, which outputs it to the SOT pin with shifting bit by bit. ● Serial mode register 0 to 3 (SMR0 to SMR3) Specifies selecting operation modes, enabling/disabling output of serial data to the pin, setting to enable/ disable output of the clock to the pin, setting the arbitrary number of 1 bit to 8 bits to be transferred in the synchronous communication mode, and setting levels of serial clock output (fixed on "L", fixed on "H") when not operating. ● Serial control register 0 to 3 (SCR0 to SCR3) Specifies setting the presence or the absence of parity, selection of parity, setting stop bit length, setting data length, selecting frame data format in the mode 1, clearance of flags, and enabling/disabling of sending and receiving. ● Serial Status Register 0 to 3 (SSR0 to SSR3) Checking sending and receiving, or the states of errors, and specifies enabling/disabling sending and receiving interrupt requests. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 489 CHAPTER 21 UART 21.2 UART Block Diagram MB90330A Series ● Serial input data register 0 to 3 (SIDR0 to SIDR3) The register retains the receive data. The serial input is converted and then stored in this register. ● Serial output data register 0 to 3 (SODR0 to SODR3) The register sets the transmit data. Data written to this register is serially converted to be output. ● UART prescaler control register 0 to 3 (UTCR0 to UTCR3) Specifies start-up/halt of the communication prescaler, forced reset of UART, selecting of clock sources, and the rate of division of the machine clock. ● UART prescaler reload register 0 to 3 (UTRLR0 to UTCR3) Specifies the division rate of the machine clock. 490 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.3 UART Pins MB90330A Series 21.3 UART Pins The pin of UART is shown. ■ UART Pins The UART pins also serve as general-purpose ports. Table 21.3-1 shows the functions of pins, input-output formats, and settings in using UART, etc. Table 21.3-1 UART Pins Pin Name Pin Function P42/A10/SIN0 P45/A13/SIN1 P90/SIN2 P93/SIN3 Port 4,9 I/O / serial data input P43/A11/SOT0 P46/A14/SOT1 P91/SOT2 P94/SOT3 Port 4,9 I/O / serial data output P44/A12/SCK0 P47/A15/SCK1 P92/SCK2 P95/SCK3 I/O Type Pull-up Selection Stand-by control Setting for the use of the pin Set to the input port (DDR4: bit2=0) (DDR4: bit5=0) (DDR9: bit0=0) (DDR9: bit3=0) CMOS output/ CMOS hysteresis input Set to output enable. (SMR0 to SMR3: SOE=1) None Yes Port 4,9 I/O / serial clock input/output Set to the input port at clock input. (DDR4: bit4=0) (DDR4: bit7=0) (DDR9: bit2=0) (DDR9: bit5=0) Set to output enable at clock output. (SMR0 to SMR3: SCKE=1) CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 491 CHAPTER 21 UART 21.4 Register of UART 21.4 MB90330A Series Register of UART The list of the register of UART is shown. ■ List of UART Register Figure 21.4-1 List of UART Register Address bit8 bit7 bit15 bit0 ch.0 : 000021H, 20H ch.1 : 000027H, 26H ch.2 : 00002DH, 2CH ch.3 : 000033H, 32H SCR0 to SCR3 (Serial control register 0 to 3) SMR0 to SMR3 (Serial mode register 0 to 3) ch.0 : 000023H, 22H ch.1 : 000029H, 28H ch.2 : 00002FH, 2EH ch.3 : 000035H, 34H SSR0 to SSR3 (Serial status register 0 to 3) SIDR0 to SIDR3 · SODR0 to SODR3 (Serial input · Output data register 0 to 3) UTCR0 to UTCR3 (UART prescaler control register 0 to 3) UTRLR0 to UTRLR3 (UART prescaler reload register 0 to 3) ch.0 : 000025H, 24H ch.1 : 00002BH, 2AH ch.2 : 000031H, 30H ch.3 : 000037H, 36H Note: When you set the communication mode, do this while operation is halted. Any data sent or received while setting modes is not guaranteed. 492 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.4 Register of UART MB90330A Series 21.4.1 Serial Control Register 0 to 3 (SCR0 to SCR3) Serial control registers 0 to 3 (SCR0 to SCR3) are responsible for setting parity, selecting the stop bit length and data length, selecting the frame data format in mode 1, clearing receiving error flags, and enabling/disabling send and receive operations. ■ Serial Control Register 0 to 3 (SCR0 to SCR3) Figure 21.4-2 Serial Control Register 0 to 3 (SCR0 to SCR3) Address bit15 bit14 ch.0 : 000021H P ch.1 : 000027H PEN ch.2 : 00002DH R/W R/W ch.3 : 000033H bit9 bit8 REC RXE TXE W R/W R/W bit13 bit12 bit11 bit10 SBL CL A/D R/W R/W R/W bit7 bit0 (SMR0 to SMR3) Bit indicating that sending operation TXE 0 Sending operation disabled 1 Sending operation enabled RXE 0 1 Initial value 00000100B Bit indicating that receiving operation Receiving operation disabled Receiving operation enabled Receiving error clear bit REC 0 Clear FRE, ORE, PE flag. 1 The conversion is not changed and no others are affected A/D 0 1 Address/Data selection bit Data frame Address frame CL 0 1 SBL Data length selection bit 7 bit 8 bit Stop bit length selection bit 0 1 bit length 1 2 bit length Parity selection bit P Only enable when parity is existent (PN = 1) 0 Even parity 1 Odd parity Parity enable bit PEN R/W : Readable/Writable W: Write only : Initial value CM44-10129-6E 0 1 No Parity With Parity FUJITSU MICROELECTRONICS LIMITED 493 CHAPTER 21 UART 21.4 Register of UART MB90330A Series Table 21.4-1 Functional Description of Each Bit in Serial Control Register 0 to 3 (SCR0 to SCR3) Bit name Functions bit 15 PEN: Parity enable bit Specify whether to add (at sending) or detect (at receiving) a parity bit. Note: In operation mode1 and operation mode 2, parity bit cannot be appended. Always set this bit to "0". bit 14 P: Parity selection bit Select either odd or even parity when the use of the parity bit has been selected (SCR0 to SCR3: PEN = 1). bit 13 SBL: Stop bit length selection bit Set the length of the stop bits (transmit data’s frame end mark) in operation mode 0 and operation mode 1 (asynchronous). Note: During receiving data, only the first bit of the stop bit is detected in all cases. bit 12 CL: Data length selection bit Specify the data length of data to be transmitted and received. It is only operation mode 0 to be able to select seven bits. In operation mode 1 and operation mode 2, be sure to set a data length of 8 bits. bit 11 A/D: Address/Data selection bit • In operation mode 1, set the data format of frames to be transmitted/received. • When the bit is set to "0": The frame format is set to data frame. • When the bit is set to "1": The frame format is set to address data frame. bit 10 REC: Receive error flag clear bit • Clear the reception error flags (SSR0 to SSR3: FRE, ORE, PE) in the serial status register to "0". • When the bit is set to "0": The FRE, ORE, and PE flags are cleared. • When the bit is set to "1": No effect. • When read: "1" is always read. Note: When the receiving interrupt is set to be enabled (SSR0 to SSR3:RIE=1), REC bit may be set to "0" as long as each of FRE, ORE, PE flag is set to "1". bit 9 RXE: Reception operation enable bit • The bit enables or disables the UART for reception. • When the bit is set to "0": Reception is disabled. • When the bit is set to "1": Reception is enabled. Note: During receiving data, if the receiving operation is set to be disabled, the receiving operation is halted after in-coming data is stored in the serial input data register. bit 8 TXE: Transmission operation enable bit • The bit enables or disables the UART for transmission. • When the bit is set to "0": Transmission is disabled. • When the bit is set to "1": Transmission is enabled. Note: If transfer operation is set to be disabled during data transfer, the transfer operation is stopped on completion of data transfer of the serial output data register. 494 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.4 Register of UART MB90330A Series 21.4.2 Serial Mode Register 0 to 3 (SMR0 to SMR3) The serial mode registers 0 to 3 (SMR0 to SMR3) are responsible for selecting operation modes, setting pins related to serial data and cock to be enabled or disabled, and setting how many bit to transfer ranging from 1to 8 bits, setting the serial clock output level in the inactive operation (fixed to "L" and "H"). ■ Serial Mode Register 0 to 3 (SMR0 to SMR3) Figure 21.4-3 Serial Mode Register 0 to 3 (SMR0 to SMR3) Address ch.0 : 000020H ch.1 : 000026H ch.2 : 00002CH ch.3 : 000032H bit15 bit8 (SCR0 to SCR3) bit7 bit6 bit0 Initial value MD1 MD0 SCKL M2L2 M2L1 M2L0 SCKE SOE 00100000B R/W R/W bit5 R/W bit4 R/W bit3 R/W bit2 R/W bit1 R/W R/W Serial data output enable bit SOE 0 As general-purpose port 1 As Serial data output pin of UART Serial clock input/output enable bit SCKE 0 As general-purpose port or Clock input pin of UART0/1 1 As Clock output pin of UART M2L2 to M2L0 Synchronous mode transfer number setting bit "000B" Transfer number: 8 bit "001B" Transfer number: 1 bit "010B" Transfer number: 2 bit "011B" Transfer number: 3 bit "100B" Transfer number: 4 bit "101B" Transfer number: 5 bit "110B" Transfer number: 6 bit "111B" Transfer number: 7 bit Serial clock output level setting bit SCKL 0 Serial clock output "L" level when not operating 1 Serial clock output "H" level when not operating Operation mode selection bit MD1 MD0 R/W : Readable/Writable : Initial value CM44-10129-6E Operation mode 0 0 0 Asynchronous mode (Normal mode) 0 1 1 Asynchronous mode (multiprocessor mode) 1 0 2 Synchronous mode (Normal mode) 1 1 Setting disabled FUJITSU MICROELECTRONICS LIMITED 495 CHAPTER 21 UART 21.4 Register of UART MB90330A Series Table 21.4-2 Functional Description of Each Bit in Serial Mode Register 0 to 3 (SMR0 to SMR3) Bit name Functions bit 7, bit 6 MD1, MD0: Operating mode selection bits Set Operating mode Notes: - In operation mode 1, the device can be used only as the master for master/slave communication. In operation mode 1, the address/data bit as bit 9 cannot be received, so the device cannot be used as the slave. - In operation mode 1, set the parity addition enable bit to no parity (SCR0 to SCR3: PEN = 0) as the parity check function cannot be used. bit 5 SCKL: Serial clock output level set bit • When communication is performed in the clock synchronous mode, serial clock output level at non-operating is set. • When set to "0": Output of serial clock is "L" level. • When set to "1": Output of serial clock is "H" level. M2L2, M2L1, M2L0: Synchronous mode transfer numerical set bits • Specify the number of bits transferred in the synchronous communication mode. • It is invalid at the asynchronous communication mode. • When set to "000B": Specify as 8-bit transmission. • When set to "001B": Specify as 1-bit transmission. • When set to "010B": Specify as 2-bit transmission. • When set to "011B": Specify as 3-bit transmission. • When set to "100B": Specify as 4-bit transmission. • When set to "101B": Specify as 5-bit transmission. • When set to "110B": Specify as 6-bit transmission. • When set to "111B": Specify as 7-bit transmission. bit 1 SCKE: Serial clock input/output enable bit • Switch between input and output of the serial clock. • When the bit is set to "0":The pin is set as a general-purpose I/O port or serial clock input pin. • When the bit is set to "1":The pin is set as a serial clock output pin. Notes: - When using the SCK0 to SCK3 pin as the serial clock input (SCK=0), set the pin to the input port using the port direction register (DDR). Also, use the clock input source select bit to select the external clock (UTCR0 to UTCR3: CKS=1). - When using this as serial clock output, set the clock input source selection bit to the dedicated baud rate generator (UTCR0 to UTCR3: CKS=0). - When SCK pins (0 to 3) are set to serial clock output, they function as serial clock output pins, regardless of the settings of the generic input-output port. bit 0 SOE: Serial data output enable bit • Enable or disable output of serial data. • When the bit is set to "0": The pin is set as a general-purpose I/O port. • When the bit is set to "1": The pin is set as a serial data output pin. • When SOT pins (0 to 3) are set to serial data output, they function as serial clock output pins, regardless of the settings of the generic input-output port. bit 4 to bit 2 496 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.4 Register of UART MB90330A Series 21.4.3 Serial Status Register 0 to 3 (SSR0 to SSR3) The serial status registers 0 to 3 (SSR0 to SSR3) are responsible for checking sending and receiving and the states of errors, and setting interrupts to be enabled or disabled. ■ Serial Status Register 0 to 3 (SSR0 to SSR3) Figure 21.4-4 Serial Status Register 0 to 3 (SSR0 to SSR3) Address ch.0 : 000023H ch.1 : 000029H ch.2 : 00002FH ch.3 : 000035H bit15 bit14 PE R bit13 bit12 bit11 bit10 bit9 (SIDR0 to SIDR3, SODR0 to SODR3) RIE TIE R/W R/W R/W R R R 00001000B Transfer interrupt request enable bit 0 1 Transfer interrupt request output disabled Transfer interrupt request output enabled RIE Receive interrupt request enable bit 0 Receive interrupt request output disabled Receive interrupt request output enabled BDS Transfer direction selection bit 0 LSB first (Transfer form Least significant bit) 1 MSB first (Transfer form Most significant bit) TDRE Transfer data empty flag bit 0 With Transfer data (Transfer data writing disabled) 1 No Transfer data (Transfer data writing enabled) RDRF Receive data full flag bit 0 No Receive data 1 With Receive data FRE 0 1 ORE 0 1 PE 0 R/W : Readable/Writable R : Read only : Initial value Initial value TIE 1 CM44-10129-6E bit7 ORE FRE RDRF TDRE BDS R bit0 bit8 1 Framing error flag bit No Framing error With Framing error Over run error flag bit No Over run error With Over run error Parity error flag bit No Parity error With Parity error FUJITSU MICROELECTRONICS LIMITED 497 CHAPTER 21 UART 21.4 Register of UART MB90330A Series Table 21.4-3 Description of Each Bit of the Serial Status Registers 0 to 3 (SSR0 to SSR3) (1 / 2) Bit name bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 498 Functions PE: Parity error flag bit • Detect a parity error of receiving data. • This bit is set to "1" when a parity error occurs. • This is cleared by writing "0" in the receiving error clear bit (SCR0 to SCR3: REC). • When receiving interrupts are enabled (SSR0 to SSR3: RIE=1), a receiving interrupt request is generated if a parity error occurs • When the parity error flag bit is set (SSR0 to SSR3: PE = 1), data in serial input data register is invalid. ORE: Overrun error flag bit • Detect an overrun error in receiving. • This bit is set to "1" when an overrun error occurs. • This is cleared by writing "0" in the receiving error flag clear bit (SCR0 to SCR3: REC). • When receiving interrupts are enabled (SSR0 to SSR3: RIE=1), a receiving interrupt request is generated if a overrun error occurs. • When the overrun error flag bit is set (SSR0 to SSR3: ORE = 1), data in serial input data register is invalid. FRE: Framing error flag bit • Detect a framing error of receive data. • This bit is set to "1" when a framing error occurs. • This is cleared by writing "0" in the receiving error clear bit (SCR0 to SCR3: REC). • When receiving interrupts are enabled (SSR0 to SSR3: RIE=1), a receiving interrupt request is generated if a framing error occurs. • When the framing error flag bit is set (SSR0 to SSR3: FRE = 1), data in serial input data register is invalid. RDRF: Receive data full flag bit • Show the status of the serial input data register. • When received data is loaded to serial input data register 0 to 3 (SIDR0 to SIDR3), "1" is set. • This bit is cleared to "0" when data is read from the serial input data register 0 to 3 (SIDR0 to SIDR3). • When receiving interrupts are enabled (SSR0 to SSR3: RIE=1), a receiving interrupt request are generated if receiving data is loaded to the serial input data registers (SIDR0 to SIDR3). TDRE: Transmission data empty flag bit • Show the status of the serial output data register 0 to 3 (SODR0 to SODR3). • The bit is cleared to "0" by writing sending data to the serial output data registers 0 to 3 (SODR0 to SODR3). • This bit is set to "1" when data is loaded to the send shift register and transmission starts. • When sending interrupts are enabled (SSR0 to SSR3: TIE=1) and if the data that has written to the serial output data registers 0 to 3 (SODR0 to SODR3) is transferred to the sending shift register, then a sending interrupt request is generated. BDS: Transfer direction selection bit • This bit sets the direction of serial data transfer. • When set to "0": Serial data is transferred from the LSB bit first (LSB first). • When set to "1": Serial data is transferred from the MSB bit first (MSB first). Note: If BDS bit is rewritten after the completion of the access to the register, the rewritten data will be invalid, since in reading to the serial input data register and in writing to the serial output data register, the LSB data and the MSB data are turned upside down. FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.4 Register of UART MB90330A Series Table 21.4-3 Description of Each Bit of the Serial Status Registers 0 to 3 (SSR0 to SSR3) (2 / 2) Bit name Functions bit 9 RIE: Reception interrupt request enable bit • Enable or disable receive data. • When set to "1": If receiving data is loaded to the serial input data registers 0 to 3 (SSR0 to SSR3: RDRF=1). Or if an receiving error occurs (SSR0 to SSR3: PE=1, or ORE=1, or FRE=1), then a receiving interrupt request is generated. bit 8 TIE: Transmission interrupt request enable bit • Enable or disable send interrupt. • When set to "1": If the data written to the serial output data registers 0 to 3 is sent to the sending shift register (SSR0 to SSR3: TDRE=1), then a sending interrupt request is generated. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 499 CHAPTER 21 UART 21.4 Register of UART 21.4.4 MB90330A Series Serial Input Data Register 0 to 3 (SIDR0 to SIDR3) and Serial Output Data Register 0 to 3 (SODR0 to SODR3) Serial input data and serial output data registers are located in the same address. They function as a serial input data register in reading, while in writing as a serial output data register. ■ Serial Input Data Register 0 to 3 (SIDR0 to SIDR3) Figure 21.4-5 shows the bit configuration of the serial input data register. Figure 21.4-5 Serial Input Data Register 0 to 3 (SIDR0 to SIDR3) Address ch.0 : 000022H ch.1 : 000028H ch.2 : 00002EH ch.3 : 000034H bit1 bit0 Initial value D2 D1 D0 XXXXXXXXB R R R bit7 bit6 bit5 bit4 bit3 bit2 D7 D6 D5 D4 D3 R R R R R R : Read only X : Undefined Serial input data register 0 to 3 (SIDR0 to SIDR3) is a data buffer register for receiving serial data. • The serial data signals sent to the serial input pins (SIDR0 to SIDR3) are converted in the shift register, and stored in the serial input data registers 0 to 3 (SIDR0 to SIDR3). • When the data length is 7 bits, the upper one bit (SIDR0 to SIDR3:D7) becomes invalid. • When the receiving data is stored in the serial input data registers 0 to 3 (SIDR0 to SIDR3), the receiving data full flag bit (SSR0 to SSR3: RDRF) is set to "1". When receiving interrupts are enabled (SSR0 to SSR3: RIE=1), receiving interrupt requests are generated. • Read the serial input data registers 0 to 3 (SIDR0 to SIDR3) in the state that the receiving data full flag bit (SSR0 to SSR3: RDRF) is set to "1". When the receiving data full flag bit (SSR0 to SSR3: RDRF) reads the serial input data registers 0 to 3 (SIDR0 to SIDR3), it is automatically cleared to "0". • If any receiving error occurs (SSR0 to SSR3: PE, ORE, or FRE is "1"), the data of the serial input data registers 0 to 3 (SIDR0 to SIDR3) is invalid. 500 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.4 Register of UART MB90330A Series ■ Serial Output Data Register 0 to 3 (SODR0 to SODR3) Figure 21.4-6 shows the bit configuration of serial output data register. Figure 21.4-6 Serial Output Data Register 0 to 3 (SODR0 to SODR3) Address bit7 ch.0 : 000022H ch.1 : 000028H ch.2 : 00002EH ch.3 : 000034H bit6 bit5 bit4 bit3 D7 D6 D5 D4 D3 W W W W W bit1 bit0 Initial value D2 D1 D0 XXXXXXXXB W W W bit2 W : Write only X : Undefined The serial output data register 0 to 3 (SODR0 to SODR3) is a data buffer register for transmitting serial data. • When sending operation is allowed (SCR0 to SCR3: TXE=1), and if the sending data is written to the serial output data registers 0 to 3 (SODR0 to SODR3), the sending data is transferred to the sending shift register to be converted into the serial data and is sent out from the serial data output pins (SOT0 to SOT 3 pins). • When the data length is seven bits, the data in upper one bit (SODR0 to SODR3:D7) is invalid. • The sending data empty flag (SSR0 to SSR3: TDRE) is cleared to "0" as soon as sending data is written into the serial output data registers 0 to 3 (SODR0 to SODR3). • The sending data empty flag (SSR0 to SSR3: TDRE) is set to "1" as soon as transmission to the sending shift register completes. • If the sending data empty flag (SSR0 to SSR3: TDRE) is set to "1", the next sending data can be written in. When sending interrupts are enabled, a sending interrupt is generated. Write the subsequent sending data in the state that the sending data empty flag (SSR0 to SSR3: TDRE) is "1". Note: Serial output data registers are write-only, while serial input data registers are read-only. Both of the registers are located in the same address, so the writing values and reading values are different. Instructions, such as the INC/DEC instruction, which provide the read modify write (RMW) operation, cannot be used. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 501 CHAPTER 21 UART 21.4 Register of UART 21.4.5 MB90330A Series UART Prescaler Control Register 0 to 3 (UTCR0 to UTCR3) and UART Prescaler Reload Register 0 to 3 (UTRLR0 to UTRLR3) UART prescaler control registers 0 to 3 (UTCR0 to UTCR3) are responsible of setting start-up/halt of the prescaler, forced reset, and selecting clock sources. The UART prescaler control registers 0 to 3 (UTCR0 to UTCR3) are also responsible of setting the division rate of the machine clock by combining their lower 3 bits with UART prescaler reload registers 0 to 3 (UTCR0 to UTCR3). ■ UART Prescaler Control Register 0 to 3 (UTCR0 to UTCR3) and UART Prescaler Reload Register 0 to 3 (UTRLR0 to UTRLR3) The UART operation clock is obtained by dividing the machine clock. Is designed to obtain a certain level of baud rate for a wide variety of machine cycles using this prescaler. Figure 21.4-7 shows the configuration of UTCR0 to UTCR3. Figure 21.4-7 UART Prescaler Control Register 0 to 3 (UTCR0 to UTCR3) and UART Prescaler Reload Register 0 to 3 (UTRLR0 to UTRLR3) UART prescaler control register 0 to 3 (UTCR0 to UTCR3) bit15 bit14 Address ch.0 : 000025H ch.1 : 00002BH ch.2 : 000031H ch.3 : 000037H MD bit13 bit12 bit11 bit10 SRST CKS R/W R/W R/W bit9 bit8 Initial value Reserved D10 D9 D8 R/W R/W R/W R/W 0000-000B UART prescaler reload register 0 to 3 (UTRLR0 to UTRLR3) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value D7 D6 D5 D4 D3 D2 D1 D0 00000000B R/W R/W R/W R/W R/W R/W R/W R/W Address ch.0 : 000024H ch.1 : 00002AH ch.2 : 000030H ch.3 : 000036H R/W : Readable/Writable : Undefined [bit 15] MD: Prescaler permission bit It is an operation permission bit of the prescaler. 0: Prescaler is stop. 1: Prescaler is in operation. [bit 14] SRST: UART compulsion reset bit It is an internal reset bit for UART. Forcibly resets UART to initialize. Once initialized, turns to "0" automatically. 0:State maintenance 1: Forced reset 502 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.4 Register of UART MB90330A Series [bit 13] CKS: clock source selection bit The clock source is selected. 0: Dedicated baud rate generator 1: External clock [bit 12] Reserved: reserved bit It is Reserved bit. Be sure to set this bit to "0". [bit 11] Undefined bit This bit is undefined when it is read. Nothing is affected when it is written. [bit 10 to bit 0] D10 to D0:Fundamental period set bit <Asynchronous mode> Two cycles of the serial clock worth of a cycle is decided. UART is responsible for dividing the serial clock into 8 pieces, and baud rate is as follows. BAUD RATES= φ/4n(bps) φ:Machine clock n:D10 to D0 (fundamental period set bit) However, please set neither n=1 or 2 nor 3. <Clock synchronous mode> BAUD RATES = 2φ/n (bps) φ : Machine clock n : D10 to D0 (fundamental period set bit) However, please set n to "00B", in case of n ≥ 16 (D1, D0). Notes: • Setting "01B", "10B", and "11B" to D1 and D0 (bit 1 and 0 of UTRLR0 to UTRLR3) of the basic cycle set bit generates the serial clock whose duty ratio is different. So set D1 and D0 (bit 1 and 0 of UTRLR0 to UTRLR3) to "00B" when in the clock synchronization mode. • Please access UTCR0 to UTCR3 and UTRLR0 to UTRLR3 by word move operation. • Halt the operation of the prescaler (MD=0 and CKS=0) before you switch the clock source. • When the external selection mode is selected and if you need to modify the reload value, halt the operation of the prescaler (MD=0 and CKS=0) before you change to your reload value. • Please set neither reload value n=1, 2 nor 3. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 503 CHAPTER 21 UART 21.5 UART Interrupt 21.5 MB90330A Series UART Interrupt The UART support reception and transmission interrupts, capable of generating an interrupt request in the following conditions: • Where the receiving data is set to the serial input data registers 0 to 3 (SIDR0 to SIDR3), or an receiving error has occurred. • When data to transmit is transferred from serial output data register 0 to 3 (SODR0 to SODR3) to the transmission shift register. Also, support for each extended intelligent I/O service (EI2OS), μDMAC. ■ UART Interrupt Table 21.5-1 shows the interrupt control bit and interrupt factor of UART. Table 21.5-1 Interrupt Control Bit of UART and Interruption Factor Serial Status Register 0 to 3 (SSR0 to SSR3) Transmission/ Reception Reception Transmission Interrupt flag bit Operating mode 0 1 2 RDRF ❍ ❍ ❍ ORE ❍ ❍ ❍ FRE ❍ ❍ PE ❍ TDRE ❍ Interrupt cause Interruption permission bit Load receive data to the buffer (SIDR0 to SIDR3) Generating overrun error Generating framing error • Reading receive data • Reset RIE Generating parity error ❍ ❍ Transmission buffer (SODR0 to SODR3) is empty. Clear Interrupt flag TIE • Writing "0" to the reception error flag clear bit (SSR0 to SSR3: REC) • Reset • Writing transmit data • Reset ❍: Using bit : Unused bit ● Reception Interrupt When receiving interrupts are enabled (SSR0 to SSR3: RIE=1) and if either completion of data reception (SSR0 to SSR3: RDRF=1), an overrun error (SSR0 to SSR3: ORE=1), a framing error (SSR0 to SSR3: FRE=1), or a parity error (SSR0 to SSR3: PE=1) occurs, then an receiving interrupt request is generated. When the receiving data full flag (SSR0 to SSR3: RDRF) reads the serial input data registers 0 to 3 (SIDR0 to SIDR3: RDRF), it is automatically cleared to "0". Each reception error flag (SSR0 to SSR3: PE, ORE, FRE) is cleared to "0" when "0" is written to the reception error flag clear bit (SCR0 to SCR3: REC). In the case that any receiving error (a parity error, an overrun error, a framing error) occurs, handle such error where necessary, and then write "0" in the receiving error flag clear bit (SCR0 to SCR3: REC) to clear each of the receiving error flags. 504 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.5 UART Interrupt MB90330A Series ● Transmission Interrupt When sending data is sent from the serial output data registers 0 to 3 (SODR0 to SODR3) to the sending shift register, then the sending data empty flag bit (SSR0 to SSR3: TDRE) is set to "1". When sending interrupts are enabled (SSR0 to SSR3: TIE=1), a sending interrupt request is generated. ■ Interruption of UART, EI2OS, and μDMAC Table 21.5-2 Interruption of UART, EI2OS, and μDMAC Interrupt control register Interrupt cause Interrupt number Vector table address Register Name Address Low High Bank μDMAC Channel number 10 EI2OS UART3 Reception Interrupt #35(23H) ICR12 0000BCH FFFF70H FFFF71H FFFF72H UART3 Transmission Interrupt #33(21H) ICR11 0000BBH FFFF78H FFFF79H FFFF7AH UART2 Reception Interrupt #35(23H) ICR12 0000BCH FFFF70H FFFF71H FFFF72H UART2 Transmission Interrupt #33(21H) ICR11 0000BBH FFFF78H FFFF79H FFFF7AH UART1 Reception Interrupt #39(27H) ICR14 0000BEH FFFF60H FFFF61H FFFF62H UART1 Transmission Interrupt #37(25H) ICR13 0000BDH FFFF68H FFFF69H FFFF6AH UART0 Reception Interrupt #39(27H) ICR14 0000BEH FFFF60H FFFF61H FFFF62H UART0 Transmission Interrupt #37(25H) ICR13 0000BDH FFFF68H FFFF69H FFFF6AH ❍ 11 10 ❍ 11 12 ❍ 13 12 ❍ 13 : Available; with a function that stops EI2OS by detecting a UART receive error ❍: Available ■ UART EI2OS Function UART has the circuit of the EI2OS correspondence. This allows EI2OS to start up separately on the occasion of each of the send interrupt and the receive interrupt. ● At Transmission/Reception At the transmission / reception, EI2OS is available regardless of the states of any other peripherals. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 505 CHAPTER 21 UART 21.5 UART Interrupt 21.5.1 MB90330A Series Receive Interrupt Generation and Flag Set Timing Interrupts during reception are one generated upon completion of reception (SSR0 to SSR3: RDRF) and one generated upon occurrence of a reception error (SSR0 to SSR3: PE, ORE, FRE). ■ Receive Interrupt Generation and Flag Set Timing When data is received, it is stored in serial input data register 0 to 3 (SIDR0 to SIDR3) upon detection of the stop bit (in operation mode 0 or 1) or of the data’s last bit (SIDR0 to SIDR3: D7) (in operation mode 2). When a receiving error occurs, an error flag (SSR0 to SSR3: PE, ORE, FRE) is set, a receiving data full flag (SSR0 to SSR3: RDRF) is set. If any of the flags is set to the each operation mode, the serial input data registers 0 to 3 (SIDR0 to SIDR3) that have received are invalid. ● Operation mode 0 (Asynchronous normal mode) The receiving data full flag (SSR0 to SSR3: RDRF) is set on detection of the stop bit. When a reception occurs, the error flag (SSR0 to SSR3: PE, ORE, FRE) is set. ● Operating mode 1 (asynchronous multiprocessor mode) The receiving data full flag bit (SSR0 to SSR3: RDRF) is set when the stop bit is detected. When a reception error occurs, the error flag (SSR0 to SSR3: ORE, FRE) is set. But parity errors (SSR0 to SSR3:PE) cannot be detected. ● Operation mode 2 (clock synchronizer normal mode) When the last bit (SIDR0 to SIDR3: D7) of the receiving data is detected, the receiving data full flag bit (SSR0 to SSR3: RDRF) is set. When a reception error occurs, the error flag (SSR0 to SSR3:ORE) is set. Neither a parity error (SSR0 to SSR3:PE) nor a framing error (SSR0 to SSR3:FRE) can be detected. Figure 21.5-1 shows the timing of receiving operation and the set of flags. 506 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.5 UART Interrupt MB90330A Series Figure 21.5-1 Timing of Receiving Operation and Set of Flags Receive data (Operation mode 0) ST D0 D1 D5 D6 D7/P SP Receive data (Operation mode 1) ST D0 D1 D6 D7 AD SP D0 D1 D4 Receive data (Operation mode 2) D5 D6 D7 PE, ORE, FRE* RDEF Receive Interrupt generation * : PE flag cannot be use in mode 1. PE, FRE flag cannot be used in mode 2. ST : Start bit SP : Stop bit AD : Address of mode 1 (multiprocessor mode)/Data selection bit ● Timing of receiving interrupt generation When receiving interrupts are enabled (SSR0 to SSR3: RIE=1), any of a receiving data full flag (SSR0 to SSR3: RDRF), a parity error flag (SSR0 to SSR3: PE), an overrun error flag (SSR0 to SSR3:ORE), and a framing error flag (SSR0 to SSR3: FRE) is set to "1", then a receiving interrupt request is generated. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 507 CHAPTER 21 UART 21.5 UART Interrupt 21.5.2 MB90330A Series Transmit Interrupt Generation and Flag Set Timing An interrupt during transmission is generated when serial output data register 0 to 3 (SODR0 to SODR3) becomes empty, or ready to accommodate the next data to transmit. ■ Transmit Interrupt Generation and Flag Set Timing The sending data empty flag bit (SSR0 to SSR3: TDRE) is set to "1" in the state that the sending data that is written to the serial output data registers 0 to 3 (SODR0 to SODR3) is transferred to the sending shift register, the subsequent data goes into the readable state. When the subsequent data is written to the serial output data registers 0 to 3 (SODR0 to SODR3), the sending data empty flag bit (SSR0 to SSR3: TDRE) is cleared to "0". Figure 21.5-2 shows the timing of sending operation and the set of flags. Figure 21.5-2 Timing of Sending Operation and the Set of Flags [Operation mode 0, 1] Transfer interrupt generation Transfer interrupt generation SODR0 to SODR3 write TDRE SOT0 to SOT3 output [Operation mode 2] ST D0 D1 D2 D3 Transfer interrupt generation D4 SP D5 D6 D7 SP AD ST D0 D1 D2 D3 Transfer interrupt generation SODR0 to SODR3 write TDRE SOT0 to SOT3 output ST: D0 to D7: SP: AD: 508 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Start bit Data bit Stop bit Address/Data selection bit FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.5 UART Interrupt MB90330A Series ● Timing transmission interrupt request generation When sending interrupts are enabled (SSR0 to SSR3: TIE=1) and if the sending data empty flag bit (SSR0 to SSR3: TDRE) is set to "1", a sending interrupt request is generated. Note: If the sending operation is set to be disabled (SCR0 to SCR3: TXE=0, in the operation mode 1, also including receiving operation disabled RXE) in the middle of sending operation, the sending data empty flag bit is set (SSR0 to SSR3: TDRE=1), the shift operation of the sending shift register is halted and then UART communication operation is disabled. The send data written to the serial output data register 1 before the transmission stops 0 to 3 (SODR0 to SODR3) is sent. By default TDRE bit is "1". So, as soon as sending interrupts are enabled (TIE=1), the interrupt indicating completion of transmission is generated. TDRE bit is a read-only bit and has no other way to clear than by writing new data in the serial output data registers 0 to 3 (SODR0 to SODR3) to clear. So be careful when to enable a sending interrupt. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 509 CHAPTER 21 UART 21.6 UART Baud Rate 21.6 MB90330A Series UART Baud Rate The sending and receiving clocks of UART has the following alternatives. • Internal clock (reload counter) • External clock (reload counter) • External clock (clock input to SCK pin) ■ UART Baud Rate Selection You can select one of the following three different baud rates: ● Baud rate resulting from a dedicated baud rate generator of the internal clock. The baud rate can be selected by setting the 11-bit reload value on settings of the UART prescaler control registers 0 to 3 (UTCR0 to UTCR3), and the UART prescaler reload registers 0 to 3 (UTRLR0 to UTRLR3). The reload counter divides the machine clock by the specified value. It is used in the synchronous and asynchronous modes. ● Baud rate resulting from a dedicated baud rate generator of the external clock. The external clock is used as the clock source for the reload counter. The baud rate can be selected by setting the 11-bit reload value on settings of the UART prescaler control registers 0 to 3 (UTCR0 to UTCR3), and the UART prescaler reload registers 0 to 3 (UTRLR0 to UTRLR3). The reload counter divides the external clock frequency by the set value. It is used in the asynchronous modes. ● Baud rate of the external clock (one-to-one mode) The clock that is entered from the UART clock input pins (SCK0 to SCK3) is used as the baud rate as it is. It is used in the synchronous mode. 510 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.6 UART Baud Rate MB90330A Series 21.6.1 Baud Rate of the UART Internal Clock Using the Dedicated Baud Rate Generator Indicates baud rates possible to set when selecting a dedicated baud rate generator, as an UART transfer clock. ■ Baud Rate of the Internal Clock Using the Dedicated Baud Rate Generator Divides the machine clock by setting the 11-bit reload value at the UART prescaler control registers 0 to 3 (UTCR0 to UTCR3), and the UART prescaler reload registers 0 to 3 (UTRLR0 to UTRLR3). <Asynchronous mode> BAUD RATES= φ/4n (bps) φ: Frequency of the machine clock, n: Values of D10 to D0 (UTCR0 to UTCR3, UTRLR0 to UTRLR3) However, please set neither n=1, 2 nor 3. <Synchronous mode> BAUD RATES = 2φ/n (bps) φ : Frequency of the machine clock, n : Values of D10 to D0 (UTCR0 to UTCR3, UTRLR0 to UTRLR3) However, please set n to "00B", in case of n ≥ 16 (D1, D0). Note: Setting "01B", "10B", and "11B" to D1 and D0 (bit1 and bit0 of UTRLR0 to UTRLR3) of the basic cycle set bit generates the serial clock whose duty ratio is different. So set D1 and D0 (bit1 and bit0 of UTRLR0 to UTRLR3) to "00B" when in the clock synchronization mode. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 511 CHAPTER 21 UART 21.6 UART Baud Rate 21.6.2 MB90330A Series Baud Rate of the External Clock Using the Dedicated Baud Rate Generator Indicates baud rates possible to set when a dedicated baud rate generator of an external clock is selected, as UART transfer clock. It is used in the clock asynchronous modes. ■ Baud Rate of the External Clock Using the Dedicated Baud Rate Generator Divides the clock by setting the 11-bit reload value at the UART prescaler control registers 0 to 3 (UTCR0 to UTCR3), and the UART prescaler reload registers 0 to 3 (UTRLR0 to UTRLR3). Provided f for the frequency of the external clock, baud rates are described as follows: • UTCR0 to UTCR3: If MD is set to "1". b= f/4n (bps), f ≤ φ × n/4 f: Frequency of the external clock, b: Baud rate n: Values of D10 to D0 (UTCR0 to UTCR3, UTRLR0 to UTRLR3), However, please set neither n=1, 2 nor 3. The maximum frequency of f is 24 MHz. 512 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.6 UART Baud Rate MB90330A Series 21.6.3 Baud Rate of the External Clock (One-to-one Mode) Indicates the formula for the settings and the baud rates for selecting the external clock, as UART transfer clock. ■ Baud Rate of the External Clock (One-to-one Mode) Selecting the baud rate of external clock (one-to-one mode) requires the following three settings. Write "0" in MD bit of UART prescaler control registers 0 to 3 (UTCR0 to UTCR3), and "1" to CKS bit, and select the baud rate resulting from the external clock (one-to-one mode). Set SCK pins 0 to 3 to Enter (DDR4: bit4=0, bit7=0, DDR9: bit2=0, bit5=0). Write "0" in SCKE bit of the serial mode registers 0 to 3 (SMR0 to SMR3) to define the pin as external clock input pin. It is used in the synchronous modes. ● Calculation expression for baud rate When the baud rate resulting from the external clock (one-to-one mode) is selected (UTCR0 to UTCR3: MD=0, CKS=1), resulted baud rate is as follows (f for the frequency of the external clock). Synchronous = f' (bps) f': External clock frequency However, the maximum of f' is up to 1/8 of the machine clocks. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 513 CHAPTER 21 UART 21.7 Explanation of Operation of UART 21.7 MB90330A Series Explanation of Operation of UART UART supports the master/slave connection based communication function (operation mode 1) as well as the typical bi-directional serial communication function (operation mode 0, operation mode 2). ■ Operation of UART ● Operating mode UART has 3 types of operation modes (i.e. mode 0 to 3), which can be selected based on the appropriate connection system or data transfer system between CPUs as shown in Table 21.7-1. Table 21.7-1 UART Operation Modes Data length Operating mode Without Parity With Parity 7 bits or 8 bits Synchronous type Length of Stop Bit Asynchronous 0 Normal mode 1 Multiprocessor mode 8+1 *1 bits - Asynchronous 1 bit or 2 bits*2 2 Normal mode 8 bits - Synchronous None - : Unavailable *1: "+1" indicates the address/data select bit (AD) used for communication control. *2: Only one bit can be detected as a stop bit at reception. Note: The UART operation mode 1 is used only for the master connection on the master/slave connection. ● Inter-CPU connection method Two alternatives are provided; one-to-one connection and master/slave connection. In both cases, the data length, parity, synchronous mode, must be the same for all CPUs. The operation modes are selected as follows. One-to-one connection: 2 CPUs should adopt the same method either in the mode 0 or in the mode 2. Select the mode 0 in the asynchronous method and the mode 2 in the synchronous method. Master/slave connection: Set the operation mode 1. When selecting the operation mode 1, use this as master. For this connection, select no parity and a data length of 8 bits. 514 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.7 Explanation of Operation of UART MB90330A Series ● Synchronous type Either asynchronous method or (start-stop synchronization) clock synchronous method can be selected. ● Signal type Data in NRZ (Non Return to Zero) format is only supported. ● Start of transmission/reception When the bit indicating that sending operation is enabled (SCR0 to SCR3: TXE) is set to "1", sending operation starts. Receiving operation starts when the reception enable bit of the serial control register (SCR0 to SCR3:RXE) is set to "1". ● Stop of transmission/reception Transmission stops when the transmission enable bit (SCR0 to SCR3:TXE) in the serial control register is set to "0". Reception stops when the reception enable bit (SCR0 to SCR3:RXE) in the serial control register is set to "0". ● Stop during transmission/reception When receiving operation (SCR0 to SCR3: RXE=0) is disabled in the middle of reception (while data is being input to the receiving shift register), the receiving operation is halted after the frame that is being received has completely received and the received data has been stored into the serial input data registers 0 to 3 (SIDR0 to SIDR3). When sending operation (SCR0 to SCR3: TXE=0) is disabled in the middle of transmission (while data is being output from the sending shift register), the sending operation is halted after one frame has been completely sent. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 515 CHAPTER 21 UART 21.7 Explanation of Operation of UART 21.7.1 MB90330A Series Operation in Asynchronous Mode (Operation Mode 0 or Operation Mode 1) The UART uses asynchronous transfer when used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode). ■ Operation in Asynchronous Mode ● Format of transmit/receive data Sending and receiving always start with the start bit ("L" Level), specified data bit length is sent and received, and end with the stop bit ("H" Level). For use in operation mode 0, select a data length of seven or eight bits. You can select whether to use the parity bit. In operation mode 1, the data length is fixed at 8 bits. There is no parity bit. The address/data bit (SCR0 to SCR3:AD) is added as bit 9. Figure 21.7-1 shows the data formats for sending and receiving in the asynchronous mode. Figure 21.7-1 Data Format for Sending and Receiving (Operation Mode 0 and 1) [Operation mode 0] ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 SP ST D0 D1 D2 D3 D4 D5 D6 D7 P No P Data 8 bit SP SP with P ST D0 D1 D2 D3 D4 D5 D6 D7 P ST D0 D1 D2 D3 D4 D5 D6 SP SP SP No P ST D0 D1 D2 D3 D4 D5 D6 SP ST D0 D1 D2 D3 D4 D5 D6 P SP ST D0 D1 D2 D3 D4 D5 D6 P SP Data 7 bit SP with P [Operation mode 1] ST D0 D1 D2 D3 D4 D5 D6 D7 AD SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 AD SP SP Data 8 bit ST : Start bit SP : Stop bit P : Parity bit AD : Address/Data bit 516 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.7 Explanation of Operation of UART MB90330A Series ● Transmission Operation • Sending data is written in the serial output data registers 0 to 3 (SODR0 to SODR3) in the state of "1" being set to the sending data empty flag bit (SSR0 to SSR3: TDRE). • When the sending data is written, and the bit of the serial control register indicating that sending operation is enabled (SCR0 to SCR3: TXE) is set to "1", then sending starts. • When the sending data is written to the serial output data register, the sending data empty flag bit (SSR0 to SSR3: TDRE) is once cleared to "0". • When the sending data is transferred from the serial output data registers 0 to 3 (SODR0 to SODR3) to the sending shift register, the sending data empty flag bit (SSR0 to SSR3: TDRE) is set to "1" again. • When the sending data is transferred from the serial output data registers 0 to 3 (SODR0 to SODR3) to the sending shift register, the sending data empty flag bit (SSR0 to SSR3: TDRE) is set to "1" again. • When the bit indicating that the sending interrupts (SSR0 to SSR3: TIE) is enabled has already been set to "1", a sending interrupt request is generated if the sending data empty flag bit (SSR0 to SSR3: TDRE) is set to "1". In interrupt processing, the following data can be written to the serial output data registers 0 to 3 (SODR0 to SODR3). ● Reception Operation • Receiving operation are always performed when the receiving operations are set to be enabled (SCR0 to SCR3: RXE=1). • When the start bit of the receiving data is detected, one frame of data is received in the serial input data registers 0 to 3 (SIDR0 to SIDR3) based on the data format that is set in the serial input control register 0 to 3 (SCR0 to SCR3). • One frame of data reception is completed, the receiving data full flag bit (SSR0 to SSR3: RDRF) is set to "1". • When reading receiving data, check the state of error flags of the serial status registers 0 to 3 (SSR0 to SSR3). If receiving is successful, then read the receiving data from the serial input data register. When a reception error occurs, perform error handling. • When the receiving data has been read, the receiving data full flag bit (SSR0 to SSR3: RDRF) is cleared to "0". ● Stop Bit One bit or two bits length can be selected. However, the receive side always detects only the first bit. ● Error detection In mode 0, parity, overrun, and framing error can be detected. In the operation mode 1, overrun and framing errors can be detected. But parity errors cannot be detected. ● Parity bit The addition of a parity bit can be set only in operation mode 0. The parity addition enable bit (SCR0 to SCR3: PEN) and parity select bit (SCR0 to SCR3:P) can be used to select whether to use parity and to set the even or odd parity, respectively. In the operation mode 1 and 2, parity cannot be appended. Figure 21.7-2 shows the sending and receiving data when parity bits are valid. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 517 CHAPTER 21 UART 21.7 Explanation of Operation of UART MB90330A Series Figure 21.7-2 Sending and Receiving Data when Parity Bits are Valid ST SIN0 to SIN3 SP When receiving by even parity Parity error generation (SCR0 to SCR3 : P=0) SP Transfer even parity (SCR0 to SCR3 : P=0) SP Transfer odd parity (SCR0 to SCR3 : P=1) 1 0 1 1 0 0 0 SOT0 to SOT3 ST 1 0 1 1 0 0 1 SOT0 to SOT3 ST 1 0 1 1 0 0 0 Data parity ST : Start bit SP : Stop bit (Note) Parity cannot be used in operation mode 1, 2. 518 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.7 Explanation of Operation of UART MB90330A Series 21.7.2 Operation in Synchronous Mode (Operation Mode 2) The UART uses clock-synchronous transfer when used in operation mode 2 (normal mode). ■ Operation in Synchronous Mode (Operation Mode 2) ● Format of transmit/receive data In the synchronous mode, 1 to 8 bits of data is transferred and the stop bit is not appended. Figure 21.7-3 shows the formats of send and receive data in the clock synchronization mode. Figure 21.7-3 Format of Transmit/Receive Data (Operation Mode 2) When transfer by output serial clock Mark level SCK0 to SCK3 output SOT0 to SOT3 (LSB) 1 0 1 1 0 0 1 (MSB) Transfer data Transfer data write TXE When transfer by input serial clock Mark level SCK0 to SCK3 output SIN0 to SIN3 (LSB) 1 0 1 1 0 0 1 (MSB) Receive data Receive data write RXE ● Clock Supply In the clock synchronous mode, count of clocks equal to the transmit and receive bits count must be supplied. When the internal clock (a dedicated baud rate generator) has been selected, the synchronous clock for receiving data is automatically generated by sending data. When the external clock has been selected, exactly one byte of clock should be provided externally after making sure that the serial output data registers 0 to 3 (SODR0 to SODR3) contains sending data (SSR0 to SSR3: TDRE=0). Also, both before and after sending, ensure that the level is marked with "H". CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 519 CHAPTER 21 UART 21.7 Explanation of Operation of UART MB90330A Series ● Specification of serial clock output level at inoperative Serial clock output level (SMR: SCL) at the clock synchronous mode and inoperative can be set. Figure 21.7-4 Setting of Serial Clock Output Level at Inoperative Transfer data write Transfer/receive clock (SCKL=1) Mark level Transfer/receive clock (SCKL=0) RXE, TXE Transfer data 1 0 1 1 0 0 1 0 ● Error detection Only overrun errors can be detected. Parity and framing errors cannot be detected. ● Initialization The setting value of each control register is described when using the synchronous mode. [Serial mode register 0 to 3 (SMR0 to SMR3)] MD1, MD0 :"10B" SCKL :If the level of the serial clock output in the inactive operating state is "L", set to "1" :If the level of the serial clock output in the inactive operating state is "L", set to "0". M2L2 to M2L0 :If 8-bit transmission is specified, set to "000B". :If 7-bit transmission is specified, set to "111B". :If 6-bit transmission is specified, set to "110B". :If 5-bit transmission is specified, set to "101B". :If 4-bit transmission is specified, set to "100B". :If 3-bit transmission is specified, set to "011B". :If 2-bit transmission is specified, set to "010B". :If 1-bit transmission is specified, set to "001B". 520 SCKE : "1" for the dedicated baud rate generator, "0" for the clock output and the external clock (clock input). SOE : "1" for transmitting, "0" only in case of reception FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.7 Explanation of Operation of UART MB90330A Series [Serial control register 0 to 3 (SCR0 to SCR3)] PEN : "0" P, SBL, and AD : These bits do not have the meaning. CL : "1"(8-bit data) REC : "0" (for initialization, error flags cleared). RXE and TXE : At least, it is "1" as for either [Serial Status Register 0 to 3 (SSR0 to SSR3)] RIE : "1" to use interrupts, "0" not to use interrupts. TIE : "1" to use interrupts, "0" not to use interrupts. ● Starting communications When the sending data is written in the serial output data registers 0 to 3 (SODR0 to SODR3), communication starts. To start communication, temporal sending data must be written to the serial output data registers 0 to 3 (SODR0 to SODR3) even when only receiving operation is necessary. ● Terminating communications As soon as one frame of data is sent and received, the receiving data full flag bit (SSR0 to SSR3: RDRF) is set to "1". Having received the data, check the overrun error flag bit (SSR0 to SSR3: ORE) to ensure that the communication was successfully done. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 521 CHAPTER 21 UART 21.7 Explanation of Operation of UART 21.7.3 MB90330A Series Bi-directional Communication Function (Normal Mode) In the mode 0 and 2, typical serial bi-directional communication on the one-to-one connection is available. The communication clock mode becomes asynchronous for the operation mode 0, synchronous for the operation mode 2. ■ Bi-directional Communication Function To operate UART in the normal mode (operation mode 0, operation mode 2), the settings described in Figure 21.7-5 must be executed. Figure 21.7-5 Setting of Operation Mode 0 in UART bit15 bit14 bit13 bit12 bit11 bit10 SCR3 to SCR0, SMR3 to SMR0 PEN Mode 0 Mode 2 SSR3 to SSR0, SIDR3 to SIDR0/ SODR3 to SODR0 Mode 0 Mode 2 P SBL CL A/D bit9 bit8 REC RXE TXE 0 0 0 1 PE ORE FRE RDRF TDRE BDS : Used bit : Unused bit 1 : Set to "1" 0 : Set to "0" : Set to "0" when using input of pin bit7 TIE bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 1 RIE bit6 MD1 MD0 SCKL M2L2 M2L1 M2L0 SCKE SOE Setting transfer data (at writing)/ Holding receive data (at reading) DDR4 D47 D46 D45 D44 D43 D42 D41 D40 DDR9 D96 D95 D94 D93 D92 D91 D90 ● Inter-CPU connection As shown in Figure 21.7-6, connect 2 CPUs each other. Figure 21.7-6 Example of Bi-directional Communication Connect for UART SOT SIN SCK CPU-1 522 SOT Output Input SIN SCK CPU-2 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.7 Explanation of Operation of UART MB90330A Series ● Communication procedure Communications start at any timing from the transmitting side when transmit data is provided. On the transmission side, load transmit data into the serial output data register 0 to 3 (SODR0 to SODR3) and set the transmission enable bit (SCR0 to SCR3:TXE) in the serial control register to "1" to start transmission. Figure 21.7-7 shows the example of transferring the receiving data to the sender to indicate that the data was successfully sent. Upon the receipt of the sending data, the receiver periodically returns ANS (1 byte in this example). Figure 21.7-7 Flowchart for Bi-directional Communication (Sender) (Receiver) START START Operation mode setting (either of 0 or 2) Operaiton mode setting (tune to transfer side) Set 1 byte data to SODR and communicate. Data transfer NO Reception data is existence. YES NO Reception data is existence. Reception data read and process YES Receive data reading and processing CM44-10129-6E Data transfer 1 byte data transfer (ANS) FUJITSU MICROELECTRONICS LIMITED 523 CHAPTER 21 UART 21.7 Explanation of Operation of UART 21.7.4 MB90330A Series Master/Slave Mode Communication Function (Multi-processor Mode) Operation mode 1 allows communication between multiple CPUs connected in a master/slave configuration. However, this is available only as master. ■ Master/Slave Mode Communication Function To operate UART in the multi-processor mode (operation mode 1), the settings described in Figure 21.7-8 must be executed. Figure 21.7-8 UART Operation Mode 1 Setting bit15 bit14 bit13 bit12 bit11 bit10 SCR0 to SCR3, SMR0 to SMR3 SSR0 to SSR3, SIDR0 to SIDR3/ SODR0 to SODR3 PEN P SBL CL A/D bit9 bit8 REC RXE TXE 0 1 0 PE ORE FRE RDRF TDRE BDS : Used bit : Unused bit 1 : Set to "1" 0 : Set to "0" : Set to "0" when using input of pin bit7 0 RIE TIE bit6 bit5 bit4 bit3 bit2 bit1 bit0 MD1 MD0 SCKL M2L2 M2L1 M2L0 SCKE SOE 1 Setting transfer data (at writing)/ Holding receive data (at reading) DDR4 D47 D46 D45 D44 D43 D42 D41 D40 DDR9 D96 D95 D94 D93 D92 D91 D90 ● Inter-CPU connection One master CPU and two or more slave CPUs are connected to a pair of common communication lines to make up the master/slave communication system as shown in Figure 21.7-9. The UART1 can be used only as the master CPU. Figure 21.7-9 Connection Example for UART Master-slave Communications SOT0 to SOT3 SIN0 to SIN3 Master CPU SOT SIN Slave CPU #0 524 SOT SIN Slave CPU #1 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.7 Explanation of Operation of UART MB90330A Series ● Function Selection When it comes to master/slave communication, select the operation mode and data transfer direction, as shown in Table 21.7-2. Since the parity check function cannot be used in operation mode 1, set the parity enable bit (SCR0 to SCR3:PEN) to "0". Table 21.7-2 Select of Master/Slave Communication Function Operating mode Master CPU Slave CPU Data Parity Synchronous type Stop bit Not provided Asynchronous 1 bit or 2 bits AD= 1 + 8 bits Address Address Trans-mission/ Reception Mode 1 AD= 0 + 8 bits Data Data Trans-mission/ Reception ● Communication procedure The communication starts when the master CPU transmits the address data. The address data, having an AD bit as 1, locates the slave CPU as the destination. Each slave CPU identifies the address data based on the program, and if there is a match with the address that is already assigned, the slave CPU communicates (typical data) with the master CPU. Figure 21.7-10 shows the flowchart of the master/slave communication (multiprocessor mode). CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 525 CHAPTER 21 UART 21.7 Explanation of Operation of UART MB90330A Series Figure 21.7-10 Flowchart for Master/Slave Communications (Master CPU) START Setting operating mode to "1" Set SIN pin to Serial data input Set 1 byte data (address data) selecting the slave CPU to D0 to D7 and transfer (AD=1) Set AD to "0" Receive operation enabled Slave CPU and communication Communication end? NO YES Other slave CPU and communication NO YES Receive operation disabled END 526 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.8 Notes on Using UART MB90330A Series 21.8 Notes on Using UART Use of the UART requires the following cautions. ■ Notes on Using UART ● Enabling sending and receiving • The bits indicating that sending operation is enabled (SCR0 to SCR3: TXE) and that receiving operation is enabled (SCR0 to SCR3: RXE) is provided for sending and receiving respectively. • In the initial state after a reset, transmission and reception are both disabled (SCR0 to SCR3:TXE=0,RXE=0). Transmission and reception must therefore be enabled in advance. • The device can stop transmission and reception by disabling them (SCR0 to SCR3:TXE=0,RXE=0). ● Setting operation mode Set the operation mode after disabling transmission and reception (SCR0 to SCR3:TXE=0,RXE=0). When the operation mode is changed during transmission or reception, the transmitted/received data is not guaranteed. ● About clock synchronous mode Operation mode 2 is set as a clock synchronizer method. Transmit/receive data is associated with no start and stop bits. ● Transmission interrupt enable timing The sending data empty flag bit (SSR0 to SSR3: TDRE) is set to "1" (no sending data, enabled to write sending data) by default after resetting. So, as soon as a sending interrupt is enabled (SSR0 to SSR3: TIE=1), the sending interrupt request is generated. Be sure to prepare data to transmit before enabling transmission (SSR0 to SSR3:TIE=1). ● Receiving Multiprocessor mode In the multiprocessor mode, receiving operation based on 9-bit receipt is not allowed. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 527 CHAPTER 21 UART 21.9 Example of UART Programming 21.9 MB90330A Series Example of UART Programming This section provides program example for UART. ■ Example of UART Programming ● Processing specification Perform serial transmission/reception using the bi-directional communication function (normal mode) of the UART. Defined as: Operation mode 0, asynchronous, 8 bits of data length, 2 bits of stop bit length, without parity. Use the P42/A10/SIN0, P43/A11/SOT0 pins for communication. The baud rate is set to about 9600 bps using the dedicated baud rate generator. Send character "13H" from the SOT0 pin to receive using an interrupt. Set the machine clock (φ) to 16 MHz. ● Coding example ICR14 EQU 0000BEH ; UART send/receive interrupt control register. DDR4 EQU 000014H ; Port 4 direction register SMR0 EQU 000020H ; Serial mode register 0 SCR0 EQU 000021H ; Serial control register 0 SIDR0 EQU 000022H ; Serial input data register 0 SODR0 EQU 000022H ; Serial output data register 0 SSR0 EQU 000023H ; Serial Status Register 0 UTCR0 EQU 000025H ; UART prescaler control register 0 UTRLR0 EQU 000024H ; UART prescaler reload register 0 REC EQU SCR:2 ; Receive error flag clear bit ;----------Main Program-----------------------------------------------------------CODE CSEG ABS = 0FFH START: ; : ; Initialize such as a stack pointer (SP). ; Defined as done. AND CCR,#0BFH ; Disables the interrupt. MOV I:ICR14, #00H ; Interrupt levels 0 (strength) MOV I:DDR4, #00000000B ; Sets the SIN0 pin for input. MOV I:SMR0, #00000001B ; operation mode 0 (asynchronous) ; Disables the clock output and enables the data ; output. MOVW I:UTRL0, #81A0H ; uses Dedicated baud rate generator ; (9615bps Selection) 528 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 21 UART 21.9 Example of UART Programming MB90330A Series MOV I:SCR0, #00010011B ; Parity none and stop bit 2 bits ; Data length 8 bits and reception clear error flag ; Enables the transmission/reception operation LOOP: MOV I:SSR0, #00000010B ; sending interrupt disabled, receiving interrupt ; enabled MOV I:SODR0, #13H ; Transmission data writing MOV ILM, #07H ; Sets ILM in PS to level 7 OR CCR, #40H ; Interruption permission MOV A,#00H ; infinite loop MOV A,#01H BRA LOOP ;----------Interrupt Program-----------------------------------------------------------WARI: MOV A, SIDR0 ; Reading receive data CLRB I:REC ; The reception interrupt request flag is clear. ; : ; User processing ; : RETI CODE ; Returns from interrupt. ENDS ;----------Vector Settings-----------------------------------------------------------------VECT CM44-10129-6E CSEG ABS=0FFH ORG 0FF60H DSL WARI ORG 0FFDCH DSL START DB 00H VECT ENDS ; The vector is set in interruption #39(27H). ; Reset vector setting ; Set to Single-chip mode FUJITSU MICROELECTRONICS LIMITED 529 CHAPTER 21 UART 21.9 Example of UART Programming 530 FUJITSU MICROELECTRONICS LIMITED MB90330A Series CM44-10129-6E CHAPTER 22 I2C INTERFACE This chapter gives an overview of I2C interface, the configuration and functions of registers, and operations of I2C interface. 22.1 I2C Interface Outline 22.2 I2C Interface Register 22.3 I2C Interface Operation CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 531 CHAPTER 22 I2C INTERFACE 22.1 I2C Interface Outline 22.1 MB90330A Series I2C Interface Outline I2C interface is Serial I/O by which Inter IC BUS is supported. Operates as the master/ slave devices on I2C bus. ■ I2C Interface Function The I2C interface has the following functions: • Master/slave sending and receiving • Arbitration function • Clock synchronous function • Slave address/General call address detection function • Forwarding direction detection function • Repetitive generation and detection function of the start condition • Bus error detection function 532 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 22 I2C INTERFACE 22.1 I2C Interface Outline MB90330A Series ■ Block Diagram of I2C Interface Figure 22.1-1 shows the block diagram of I2C interface. Figure 22.1-1 Block Diagram of I2C Interface ICCR I2C enable EN Peripheral clock Clock divider 1 5 ICCR CS4 6 7 8 Clock selection 1 CS3 Clock divider 2 CS2 2 4 8 16 32 64 128 CS1 CS0 256 Synch Shift clock generation Clock selection 2 Shift clock edge change timing IBSR Bus busy BB Repeat start RSC Last Bit LRB Stop Condition detection Send/ receive TRX F2MC-16LX Bus Start Error First Byte FBT Arbitration lost detection AL IBCR SCL0 to SCL2 BER BEIE Interrupt request IRQ #17,19,21 SDA0 to SDA2 INTE INT IBCR SCC MSS ACK End Start Master Start ACK enable Stop Condition generation GC-ACK enable GCAA IDAR IBSR Slave AAS GCA Global call Slave address compare IADR CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 533 CHAPTER 22 I2C INTERFACE 22.2 I2C Interface Register 22.2 MB90330A Series I2C Interface Register The configuration and functions of registers used in the I2C interface are described. ■ Register List of I2C Interface Figure 22.2-1 Register List of I2C Interface ch.0:000070H ch.1:000076H ch.2:00007CH bit 7 6 5 4 3 2 1 IBSR0 to IBSR2 I2C Bus status register 0 BB RSC AL LRB TRX AAS GCA FBT R R R R R R R R IBCR0 to IBCR2 I2C Bus status register Initial value 00000000B Read/Write bit 15 14 13 12 11 10 9 8 ch.0:000071H GCAA INTE INT BER BEIE SCC MSS ACK ch.1:000077H ch.2:00007DH R/W R/W R/W R/W R/W R/W R/W R/W ch.0:000072H ch.1:000078H ch.2:00007EH 7 bit 6 ICCR0 to ICCR2 I2C Clock control register EN CS4 CS3 CS2 CS1 CS0 Initial value --0XXXXXB R/W R/W R/W R/W R/W R/W Read/Write 5 4 3 2 1 0 IADR0 to IADR2 I2C Bus address register Initial value -XXXXXXXB Read/Write bit 15 14 13 12 11 10 9 8 ch.0:000073H A6 A5 A4 A3 A2 A1 A0 ch.1:000079H R/W R/W R/W R/W R/W R/W R/W ch.2:00007FH ch.0:000074H ch.1:00007AH ch.2:000080H bit Initial value 00000000B Read/Write IDAR0 to IDAR2 I2C Bus data register D7 D6 D5 D4 D3 D2 D1 D0 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W Read/Write 7 6 5 4 3 2 1 0 R/W : Readable/Writable R: Read only 534 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 22 I2C INTERFACE 22.2 I2C Interface Register MB90330A Series 22.2.1 I2C Bus Status Register 0 to 2 (IBSR0 to IBSR2) The configuration and functions of I2C bus status register 0 to 2 (IBSR0 to IBSR2) are described. ■ I2C Bus Status Register 0 to 2 (IBSR0 to IBSR2) Figure 22.2-2 shows the bit configuration of I2C bus status registers 0 to 2 (IBSR0 to IBSR2). Figure 22.2-2 Bit Configuration of I2C Bus Status Register 0 to 2(IBSR0 to IBSR2) ch.0:000070H bit ch.1:000076H ch.2:00007CH 7 6 5 4 3 2 1 0 BB RSC AL LRB TRX AAS GCA FBT R R R R R R R R IBSR0 to IBSR2 I2C Bus status register Initial value 00000000B R : Read only The function of each bit of the I2C bus status registers 0 to 2 (IBSR0 to IBSR2) is described as follows: [bit 7] BB: Bus Busy It is a bit shown the state of the I2C bus. 0 Stop condition is detected. 1 Start condition is detected. (The bus is used.) [bit 6] RSC: Repeated Start Condition It is a start condition detection repeatedly bit. 0 The start condition is not repeatedly detected. 1 The start condition was detected in the bus Occupied again. Is cleared either by writing "0" in INT bit, with no addressing on the slave connection, or by detecting the start condition during the halted bus, or by detecting the stop condition. [bit 5] AL: Arbitration Lost It is an arbitration lost detection bit. 0 The arbitration lost is not detected. 1 When arbitration lost has occurred on master transmission, or when other systems are using the bus, "1" was written in MSS bit. It is cleared by writing "0" in INT bit. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 535 CHAPTER 22 I2C INTERFACE 22.2 I2C Interface Register MB90330A Series [bit 4] LRB: Last Received bit It is the acknowledgement storage bit. Stores the acknowledge from the receiver. 0 Reception is acknowledged. 1 Reception is not acknowledged. It is cleared by detecting the start condition or the stop condition. [bit 3] TRX: Transfer/Receive It is the bit indicating sending and receiving of data transfer. 0 Receiving state 1 Transmission state [bit 2] AAS: Addressed As Slave It is Addressing detection bit. 0 Addressing is not done at the slave. 1 Addressing was done at the slave. It is cleared by detecting of the start condition or stop condition. [bit 1] GCA: General Call Address It is General call address (00H) detection bit. 0 The General call address is not received at the slave. 1 The General call address was received at the slave. It is cleared by detecting of the start condition or stop condition. [bit 0] FBT: First Byte Transfer It is a first byte detection bit. 0 Received data is things except the first byte. 1 Received data is a first byte (address data). It is cleared either if "0" is written in INT bit or if no addressing is provided on the slave connection, even though detection of the start condition has set "1". 536 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 22 I2C INTERFACE 22.2 I2C Interface Register MB90330A Series 22.2.2 I2C Bus Control Register 0 to 2 (IBCR0 to IBCR2) The configuration and functions of I2C bus control register 0 to 2 (IBCR0 to IBCR2) are described. ■ I2C Bus Control Register 0 to 2 (IBCR0 to IBCR2) Figure 22.2-3 shows the bit configuration of bus control register 0 to 2(IBCR0 to IBCR2). Figure 22.2-3 Bit Configuration of I2C Bus Control Register 0 to 2 (IBCR0 to IBCR2) bit 15 ch.0:000071H ch.1:000077H ch.2:00007DH 14 13 12 11 10 9 8 BER BEIE SCC MSS ACK GCAA INTE INT R/W R/W R/W R/W R/W R/W R/W R/W IBCR0 to IBCR2 I2C Bus status register Initial value 00000000B Read/Write R/W : Readable/Writable The function of each bit of the bus control registers 0 to 2 (IBCR0 to IBCR2) is described as follows: [bit 15] BER: Bus ERror It is Bus error Interrupt request flag. Functions in writing phase differ from those as follows. (at writing) 0 Clear bus error interrupt request flag. 1 No effect on operation (at reading) 0 The bus error is not detected. 1 Illegal start and stop condition was detected during data transfer. If BER bit is set, EN bit of ICCR register is cleared, the I2C interface goes into a halted state, and data transfer is terminated. [bit 14] BEIE: Bus Error Interrupt Enable It is bus error Interrupt enable bit. 0 Bus error interrupt disabled 1 Bus error interrupt enabled The interruption is generated if the BER bit is "1" when this bit is "1". CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 537 CHAPTER 22 I2C INTERFACE 22.2 I2C Interface Register MB90330A Series [bit 13] SCC: Start Condition Continue It is a start condition generation bit. (at writing) 0 No effect on operation 1 A start condition is regenerated on master transmission. This bit is always "0" at the beginning of reading. [bit 12] MSS: Master Slave Select It is Master/slave selection bit. 0 Generates the stop condition, and goes into the slave mode after the completion of transmission. 1 Goes into the master mode, generates the start condition, and starts transferring. If the arbitration lost has occurred during the master sending, it will be cleared and will switch to the slave mode. Note: The transmission of the general call address is prohibited, because the receiving as the slave cannot be operation on the following condition. • When (1) other LSI that is a master mode without this LSI exists on the bus, and (2) this LSI transmits the general call address as master, and (3) the arbitration lost is generated since the second byte. [bit 11] ACK: ACKnowledge It is the acknowledge generation enable bit when the data is received. 0 Acknowledgement is disabled to be generated. 1 Acknowledgement is enabled to be generated. Is invalid during receiving address data in the slave. [bit 10] GCAA: General Call Address Acknowledge It is an acknowledge generating enable bit, when you receive the General call address. 0 Acknowledgement is disabled to be generated 1 Acknowledgement is enabled to be generated. [bit 9] INTE: INTerrupt Enable It is Interrupt enable bits. 0 Disables the interrupt. 1 Enables the interrupt. The interruption is generated if the INT bit is "1" when this bit is "1". 538 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 22 I2C INTERFACE 22.2 I2C Interface Register MB90330A Series [bit 8] INT: INTerrupt It is transfer stop interrupt request flag bit. (at writing) 0 Clear Transfer stop interrupt request flag. 1 No effect on operation (at reading) 0 Transfer has not been finished yet. 1 This is set when 1 byte of data including the ACK bit has already been transferred and if the following condition is applied. • It is a bus master. • It is a slave that the address is done. • The General call address was received. • The arbitration lost happened. • Other systems tried to generate a start condition while the bus was in use. The SCL line is kept at "L" level at "1". Is cleared by writing "0", releases SCL line, and sends the subsequent bite. And is reset to "0" by occurrence of the start condition or the stop condition on the master connection. Notes: When an instruction which generates a start condition is executed (the MSS bit is set to "1") at the timing shown in Figure 22.2-4 and Figure 22.2-5, arbitration lost detection (AL bit=1) prevents an interrupt (INT bit=1) from being generated. • Condition 1 in which an interrupt (INT bit=1) upon detection of "AL bit=1" does not occur. When an instruction which generates a start condition is executed (setting the MSS bit in the IBCR register to "1") with no start condition detected (BB bit=0) and with the SDA or SCL pin at the "L" level. Figure 22.2-4 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" does not Occur SCL or SDA pin at "L" level SCL pin "L" SDA pin "L" 1 I2C operation enable state (EN bit=1) Master mode setting (MSS bit=1) Arbitration lost detection (AL bit=1) CM44-10129-6E Bus busy (BB bit) 0 Interrupt (INT bit) 0 FUJITSU MICROELECTRONICS LIMITED 539 CHAPTER 22 I2C INTERFACE 22.2 I2C Interface Register MB90330A Series • Condition 2 in which an interrupt (INT bit=1) upon detection of "AL bit=1" does not occur When an instruction which generates a start condition by enabling I2C operation (EN bit=1) is executed (setting the MSS bit in the IBCR register to "1") with the I2C bus occupied by another master. This is because, as shown in Figure 22.2-5, when the other master on the I2C bus starts communication with I2C disabled (EN bit=0), the I2C bus enters the occupied state with no start condition detected (BB bit =0). Figure 22.2-5 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" does not Occur Start Condition The INT bit interrupt does not occur in the ninth clock cycle. Stop Condition SCL pin SDA pin SLAVE ADDRESS ACK DATA ACK EN bit MSS bit AL bit BB bit 0 INT bit 0 If a symptom as described above can occur, follow the procedure below for software processing. 1. Execute the instruction that generates a start condition (set the MMS bit to "1"). 2. Use, for example, the timer function to wait for the time* for three-bit data transmission at the I2C transfer frequency set in the ICCR register. Example: Time for three-bit data transmission at an I2C transfer frequency of 100 kHz {1/(100×103)}×3=30 μs 3. Check the AL and BB bits in the IBSR register and, if the AL and BB bits are "1" and "0", respectively, set the EN bit in the ICCR register to "0" to initialize I2C. When the AL and BB bits are not so, perform normal processing. A sample flow is given below. Master mode setting Set the MSS bit in the bus control register (IBCR) to 1. Wait* for the time for three-bit data transmission at the I2C transfer frequency set in the clock control register (ICCR). BB bit=0 and AL bit=1? YES NO to normal process Set the EN bit to 0 to initialize I2C 540 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 22 I2C INTERFACE 22.2 I2C Interface Register MB90330A Series *: When "arbitration lost" is detected, the MSS bit is set to "1" and then the AL bit is set to "1" without failure after the time for three-bit data transmission at the I2C transfer frequency. • Example of occurrence of an interrupt (INT bit=1) upon detection of "AL bit=1" When an instruction which generates a start condition is executed (setting the MSS bit to "1") with "bus busy" detected (BB bit=1) and arbitration is lost, the INT bit interrupt occurs upon detection of "AL bit=1". Figure 22.2-6 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" Occurs Start Condition Interrupt in the ninth clock cycle SCL pin SDA pin SLAVE ADDRESS ACK DATA EN bit MSS bit Clearing the AL bit by software AL bit BB bit Releasing the SCL by clearing the INT bit by software INT bit ■ Notes on Use of I2C Bus Control Register 0 to 2 (IBCR0 to IBCR2) The following care should be taken to conflicts among SCC bit, MSS bit, and INT bit. Writing to SCC bit, MSS bit, INT bit simultaneously causes conflicts of transferring the next bite, occurrence of the start condition, and occurrence of the stop condition. The priority in this case is as follows. ● The following byte forwarding and stop condition generation If "0" is written in INT bit and "0" in MSS bit, writing "0" in MSS bit is preferred and the stop condition occurs. ● The following byte forwarding and start condition generation If "0" is written in INT bit and "1" in SCC bit, writing "1" in SCC bit is preferred and the start condition occurs. ● Start condition generation and stop condition generation Simultaneous writing is disabled that not only "1" is written in SCC bit but also "0" is written in MSS bit. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 541 CHAPTER 22 I2C INTERFACE 22.2 I2C Interface Register 22.2.3 MB90330A Series I2C Bus Clock Control Register 0 to 2 (ICCR0 to ICCR2) The configuration and functions of I2C bus clock control register 0 to 2 (ICCR0 to ICCR2) are described. ■ I2C Bus Clock Control Register 0 to 2 (ICCR0 to ICCR2) Figure 22.2-7 shows the bit configuration of I2C bus clock control registers 0 to 2 (ICCR0 to ICCR2). Figure 22.2-7 Bit Configuration of I2C Bus Clock Control Register 0 to 2 (ICCR0 to ICCR2) ch.0:000072H ch.1:000078H ch.2:00007EH bit 7 6 5 EN 4 3 2 1 0 ICCR0 to ICCR2 CS4 CS3 CS2 CS1 CS0 I2C Clock control register R/W R/W R/W R/W R/W R/W Initial value XX0XXXXXB R/W : Readable/Writable The functions of I2C bus clock control registers 0 to 2 (ICCR0 to ICCR2) are described below. [bit 7, bit 6] undefinition bit The read value is irregular. Nothing is affected when it is written. [bit 5] EN: ENable It is an operation permission bit in the I2C interface. 0 Operation disabled 1 Operation enabled • When "0", each bit of IBSR register and IBCR register (except BER and BEIE bits) is cleared. • Is cleared when BER bit is set. Notes: • If the I2C interface operation is inhibited, transmit/receive operation is immediately stopped. • If you wish to inhibit the I2C interface operation after generating the stop condition by writing "0" to the MSS bit, confirm the stop condition is generated (BB=0 for IBSR) before inhibiting the operation (EN=0 for ICCR). 542 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 22 I2C INTERFACE 22.2 I2C Interface Register MB90330A Series [bit 4 to bit 0] CS4 to CS0:Clock Period Select 4-0 It is the bit which sets the serial clock frequency. The frequency fsck in the shift clock is set as shown in the next formula. fsck φ m n 4 φ : Machine clock Note: The cycle + 4 is minimum overhead for checking that the output level of SCL pin has changed. If delay is longer on the rising edge of SCL pin, or a slave device delays a clock, it exceeds this value. Note that the frequency of the serial clock must be set to 100 kHz or less. m and n for CS4 to CS0 is as shown in Table 22.2-1. Table 22.2-1 Setting of Serial Clock Frequency CM44-10129-6E m CS4 CS3 n CS2 CS1 CS0 5 0 0 4 0 0 0 6 0 1 8 0 0 1 7 1 0 16 0 1 0 8 1 1 32 0 1 1 64 1 0 0 128 1 0 1 256 1 1 0 512 1 1 1 FUJITSU MICROELECTRONICS LIMITED 543 CHAPTER 22 I2C INTERFACE 22.2 I2C Interface Register 22.2.4 MB90330A Series I2C Bus Address Register 0 to 2 (IADR0 to IADR2) The configuration and functions of I2C bus address register 0 to 2 (IADR0 to IADR2) are described. ■ I2C Bus Address Register 0 to 2 (IADR0 to IADR2) Figure 22.2-8 shows the bit configuration of the I2C bus address registers 0 to 2 (IADR0 to IADR2). Figure 22.2-8 I2C Bus address Register 0 to 2 (IADR0 to IADR2) ch.0:000073H bit ch.1:000079H ch.2:00007FH 15 14 A6 R/W 13 A5 12 A4 R/W R/W 11 10 9 8 A3 A2 A1 A0 R/W R/W IADR0 to IADR2 I2C Bus address register Initial value XXXXXXXXB R/W R/W R/W : Readable/Writable [bit 14 to bit 8] A6 to A0 It is a slave address bit. It is a register which specifies the slave address. In the slave, the address data is compared to the IDAR register upon reception of the address, and if they match, then it will send the acknowledge to the master. 544 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 22 I2C INTERFACE 22.2 I2C Interface Register MB90330A Series 22.2.5 I2C Bus Data Register 0 to 2 (IDAR0 to IDAR2) The configuration and functions of I2C bus data register 0 to 2 (IDAR0 to IDAR2) are described. ■ I2C Bus Data Register 0 to 2 (IDAR0 to IDAR2) Figure 22.2-9 shows the bit configuration of the I2C bus data registers 0 to 2 (IDAR0 to IDAR2). Figure 22.2-9 Bit Configuration of I2C Bus Data Register 0 to 2 (IDAR0 to IDAR2) 6 5 4 3 2 1 0 ch.0:000074H bit 7 D7 D6 D5 D4 D3 D2 D1 D0 ch.1:00007AH ch.2:000080H R/W R/W R/W R/W R/W R/W R/W R/W IDAR0 to IDAR2 I2C Bus data register Initial value XXXXXXXXB R/W : Readable/Writable [bit 7 to bit 0] D7 to D0 It is a data bit. It is the data register used for the serial transfer, and transferred from MSB. During the data receiving (TRX= 0), the data output value becomes "1". The writing side of IDAR register is double buffering. If the bus is in use (BB=1), the data to be written to is loaded to the register for serial transferring when each byte is transferred. In reading the register for serial transferring is directly read, so the receiving data is valid only when INT bit is set. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 545 CHAPTER 22 I2C INTERFACE 22.3 I2C Interface Operation 22.3 MB90330A Series I2C Interface Operation For I2C bus, 1 serial data line (SDA), 1 serial clock line (SCL), and 2 bi-directional bus lines are responsible for communication. I2C interface, which has 2 open drain inputoutput pins (SDA and SCL) to them, allows wired logic. ■ Start Condition If "1" is written to MSS bit in the state of the bus being released (BB=0 and MSS=0), I2C interface generates the start condition as soon as it changes to the master mode. In the master mode the start condition can be regenerated by writing "1" to SCC bit even though the bus is in use (BB=1). To generate start conditions, 2 methods are provided as follows. • Writing "1" to MSS bit in the state that the bus is not in use (MSS=0 * BB=0 * INT=0 * AL=0). • Writing "1" to SEC bit in the state of interrupting in bus master (MSS=1 * BB=1 * INT=1 * AL=0). When the bus (in the idle state) is used by other systems and if "1" is written to MSS bit, then AL bit is set to "1". Writing to MSS bit and SCC bit in any other state than being mentioned above is ignored. ■ Stop Condition When "0" is written to MSS bit in the state of the master mode (MSS=1), the stop condition is generated, resulting in the slave mode. The condition to generate the stop condition is as follows. Writing "0" to MSS bit in the state of interrupting in bus master (MSS=1 * BB=1 * INT=1 * AL=0). Writing "0" excluding this in the MSS bit is disregarded. ■ Addressing In the master mode, BB= 1 and TRX= 1 will be set after the start condition generation, and it outputs the IDAR register contents from the MSB. After sending the address data, receives the acknowledgement from the slave, reverses bit 0 (bit 0 of IDAR register that is already sent) of the sending data, and then stores it into TRX bit. In the slave mode, BB is set to "1" and TRX is set to "0" after the start condition is generated, and the sending data from the master is received in IDAR register. After the address data is received, IDAR register is compared with IADR register. If they matches, AAS is set to "1" and the acknowledgement is sent to the master. Then, bit 0 of the receiving data (bit 0 of IDAR register that is already received) is stored in TRX bit. ■ Arbitration If other master are sending the data simultaneously in the master sending mode, the arbitration will occur. When the sending data of its own is "1", and the data on SDA line is "L" level, it is considered that its arbitration is lost and AL is set to "1". When an attempt is made that the start condition is generated in the state the bus is in use as mentioned above, Al is also set to "1".When AL is set to "1", MSS is "0" and TRX is "0", resulting in the slave receiving mode. 546 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 22 I2C INTERFACE 22.3 I2C Interface Operation MB90330A Series ■ Acknowledge The receiver send the acknowledge to the sender. During data reception, ACK bit can specify acknowledgement is necessary or not. During the data sending, the acknowledge from the receiver is stored in the LRB bit. If the sender as slave does not receive any acknowledgement from the receiver as master, TRX becomes "0", resulting in the slave receiving mode. This allows the master to generate the stop condition when the slave releases the SCL line. ■ Bus Error If the following conditions exist, it will be considered as bus error, and the I2C interface will be in the stopped state. • Detecting of violation of the basic rules on I2C bus during data transfer (including ACK bit) • Stop condition detection at master • Detecting of violation of the basic rules on I2C bus in bus idle. ■ The Others ● Processing after arbitration lost is detected After arbitration lost occurs, must decide if it is addressed or not by software. Once arbitration lost occurs, it becomes slave from the viewpoint of hardware. After one byte of data transfer both CLK line and DATA line are pulled to "L". For this reason, if addressing is done, CLK line and DATA line should be released after slave transmission or slave reception is ready. if no addressing is done, then CLK line and DATA line should be immediately released. (Software is responsible for this all.) ● Interruption factor when arbitration lost is detected When arbitration lost is detected, causes of interrupts are not issued immediately but after one byte of data has been transferred. When arbitration lost is detected, it becomes slave from the viewpoint of hardware. Even if so, it outputs 9 clocks in all in order to issue causes of interrupts. For this reason, causes and interrupts are not immediately issued, so no processing is allowed after arbitration lost. ● Interrupt condition It is specified that I2C bus has one interrupt and causes of interrupts are issued once one byte of transfer completes or if the conditions of interrupts are satisfied. Each flag should be checked within the interrupt routine, since multiple conditions of interrupts is identified based on one interrupt. Multiple conditions of interrupts on completion of one byte transfer is as follows. • When it is a bus master • When it is a slave that the address is done • When you receive the General call address • When arbitration lost has occurred. ● Transfer rate Note that I2C bus can support up to 100 kHz of the serial clock frequency of transmission. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 547 CHAPTER 22 I2C INTERFACE 22.3 I2C Interface Operation 22.3.1 MB90330A Series Transfer Flow of I2C Interface Figure 22.3-1 shows the 1-byte transfer flow from master to slave, and Figure 22.3-2 shows the 1-byte transfer flow from slave to master. ■ Transfer Flow of I2C Interface Figure 22.3-1 1-byte Transfer Flow from the Master to Slave Master Slave Start IDAR: Writing MSS: Writing 1 Start condition BB set, TRX set BB set, TRX set Address data transfer AAS set Acknowledgement LRB reset INT set,TRX set IDAR: Writing INT : Writing 0 Interrupt INT set,TRX set ACK: Writing 1 INT: Writing 0 Data transfer Acknowledgement LRB reset INT set Interrupt MSS: Writing 0 INT reset BB reset,TRX reset Stop condition INT set IDAR: Read INT: Writing 0 BB reset,TRX reset AAS reset End 548 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 22 I2C INTERFACE 22.3 I2C Interface Operation MB90330A Series Figure 22.3-2 1-byte Transfer Flow from Slave to Master Master Slave Start IDAR: Writing MSS: Writing 1 Start condition BB set,TRX set BB set,TRX set Address data transfer AAS reset Acknowledgement LRB reset INT set,TRX reset Interrupt INT: Writing 0 INT set,TRX set IDAR: Writing INT: Writing 0 Data transfer Negative acknowledgement INT set IDAR: Read LRB set,TRX set INT set Interrupt INT: Writing 0 MSS: Writing 0 INT reset BB reset,TRX reset Stop condition BB reset,TRX reset AAS reset End CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 549 CHAPTER 22 I2C INTERFACE 22.3 I2C Interface Operation 22.3.2 MB90330A Series Mode Flow of I2C Interface Figure 22.3-3 shows the flow of mode transitions for the I2C interface. ■ Flow of I2C Interface Mode Transitions Figure 22.3-3 I2C Mode Flow Slave receive mode SCC NO YES TRX,AAS,LRB:reset FBT:set SCC&BB=1 YES RSC:set NO BB:set 8 bits received Address comparison RSC,FBT:reset Match AAS: set INT:set Acknowledgement output SCL line retained at "L" NO TRX=1 Slave receive mode YES SCC Slave send mode YES AAS,LRB,BB,RSC NO :reset INT: 0 write FBT:reset SCL line freed Send/receive YES Acknowledgement received? NO TRX:reset 550 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 22 I2C INTERFACE 22.3 I2C Interface Operation MB90330A Series Operation Flow of I2C Interface 22.3.3 Figure 22.3-4 shows the operation flow of a master send/receive program (with interrupts) for the I2C interface. Figure 22.3-5 shows the operation flow of the slave program (with interrupts) for the I2C interface. ■ Operation Flow of I2C Interface Figure 22.3-4 Operation Flow of the Master Send/Receive Program (with Interrupts) for the I2C Interface Main routine Interrupt routine Start Start Set the slave address Bus error occurred? I2C operating enabled Master receive operation? Master send YES NO Send the slave address set (Data direction bit=0) AL occurred? RETI I2C operation enabled I2C operation disabled RETI Acknowledge occurrence enabled 3 To the slave program interrupt routine NO 1 YES BBbit=1? BB bit=0 and AL bit=1? NO LOOP Is the number of remaining bytes to be received 0? NO Is the data direction bit (TRX)=1? YES Is the number of remaining bytes to be sent 0? Wait for a certain amount of time YES I2C initial setting 3 YES Was ACK returned? Generate the start condition while sending the slave address Wait for a certain amount of time LOOP Clear the bus error interrupt factor 3 NO NO Generate the start condition while sending the slave address YES Master? Receive the slave address set (Data direction bit=1) NO NO STOP condition generated 2 NO Master receive Set the number of bytes to be sent for each time that data is written YES BBbit=1? BB bit=0 and AL bit=1? 2 NO Set the number of bytes to be sent for each time that data is written YES YES 1 Is the number of remaining bytes to be received 1? 1 YES NO Decrement the number of bytes to be sent I2C operation disabled 1 NO YES NO YES YES Acknowledge occurrence enabled Acknowledge occurrence enabled Set the send data Is the first byte being received? Clear the end interrupt factor YES NO RETI Decrement the number of bytes to be received Store the receive data to the RAM Clear the end interrupt factor RETI CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 551 CHAPTER 22 I2C INTERFACE 22.3 I2C Interface Operation MB90330A Series Figure 22.3-5 Operation Flow of the Slave Program (with Interrupts) for the I2C Interface Main routine Interrupt routine Start Start Set the slave address I2C operation enabled Set slave mode LOOP Bus error occurred? YES 2 NO Is addressing completed? 1 2 Clear the transfer end interrupt source Clear the bus error interrupt factor RETI I2C operation enabled I2C initial setting NO 1 RETI YES Is the data direction bit (TRX)=1? Is the receive data an address? NO YES Is ACK returned? Yes Set the send data Clear the transfer end interrupt source NO 1 YES NO Store the data in RAM Clear the transfer end interrupt source RETI RETI 552 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 23 ROM MIRROR FUNCTION SELECTION MODULE This chapter describes the ROM mirror function selection module. 23.1 Overview of ROM Mirror Function Select Module 23.2 ROM Mirror Function Select Register (ROMM) CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 553 CHAPTER 23 ROM MIRROR FUNCTION SELECTION MODULE 23.1 Overview of ROM Mirror Function Select Module 23.1 MB90330A Series Overview of ROM Mirror Function Select Module The ROM mirror function selection module is used to select via register settings an FF bank in ROM, whose contents can be viewed via 00 bank. ■ Block Diagram of ROM Mirror Function Select Module Figure 23.1-1 shows the block diagram of ROM mirror function selection module. Figure 23.1-1 Block Diagram of ROM Mirror Function Select Module F2MC-16LX Bus ROM mirror function selection Address area FF bank 00 bank ROM ■ Register of ROM Mirror Function Selection Module Figure 23.1-2 shows the configuration of ROM mirror function select module. Figure 23.1-2 ROM Mirror Function Selection Module Configuration bit ROMM Address : 00006FH 15 14 13 12 11 10 9 8 Reserved MI R/W W initial value 11B R/W : Readable/Writable W: Write only 554 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 23 ROM MIRROR FUNCTION SELECTION MODULE 23.2 ROM Mirror Function Select Register (ROMM) MB90330A Series 23.2 ROM Mirror Function Select Register (ROMM) The configuration and functions of ROM Mirror Function Select Register (ROMM) are described. ■ ROM Mirror Function Select Register (ROMM) Figure 23.2-1 shows the bit configuration of ROM mirror function select register (ROMM). Figure 23.2-1 Bit Configuration of ROM Mirror Function Select Register (ROMM) bit 15 14 13 12 11 10 ROMM Address : 00006FH 9 8 Reserved MI R/W W initial value 11B R/W : Readable/Writable W: Write only [bit 9] Reserved bit It is Reserved bit. Please write "1". [bit 8] MI • When "1" is written, ROM data in FF bank can be also read in 00 bank. • When "0" is written, this function is not available to 00 bank. • Only writing is enabled. Notes: • Do not access to ROMM register in the middle of the operation of the address 008000H to 00FFFFH. • When ROM mirror function is activated, the addresses from FF8000H to FFFFFFH are mirrored to the addresses from 008000H to 00FFFFH of 00 bank. So ROM addresses under the address FF7FFFH are not mirrored even though ROM mirror function is set. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 555 CHAPTER 23 ROM MIRROR FUNCTION SELECTION MODULE 23.2 ROM Mirror Function Select Register (ROMM) 556 FUJITSU MICROELECTRONICS LIMITED MB90330A Series CM44-10129-6E CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION This chapter explains the address match detection function and its operation. 24.1 Overview of Address Match Detection Function 24.2 Block Diagram of Address Match Detection Function 24.3 Configuration of Address Match Detection Function 24.4 Explanation of Operation of Address Match Detection Function 24.5 Program Example of Address Match Detection Function CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 557 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.1 Overview of Address Match Detection Function 24.1 MB90330A Series Overview of Address Match Detection Function If the address of the instruction to be processed next to the instruction currently processed by the program matches the address set in the detect address setting registers, the address match detection function forcibly replaces the next instruction to be processed by the program with the INT9 instruction to branch to the interrupt processing program. Since the address match detection function can use the INT9 interrupt for instruction processing, the program can be corrected by patch processing. ■ Overview of Address Match Detection Function • The address of the instruction to be processed next to the instruction currently processed by the program is always held in the address latch through the internal data bus. The address match detection function always compares the value of the address held in the address latch with that of the address set in the detect address setting registers. When these compared values match, the next instruction to be processed by the CPU is forcibly replaced by the INT9 instruction, and the interrupt processing program is executed. • There are two detect address setting registers (PADR0 and PADR1), each of which has an interrupt enable bit. The generation of an interrupt due to a match between the address held in the address latch and the address set in the detect address setting registers can be enabled and disabled for each register. 558 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.2 Block Diagram of Address Match Detection Function MB90330A Series 24.2 Block Diagram of Address Match Detection Function The address match detection module consists of the following blocks: • Address latch • Address detection control register (PACSR) • Detect address setting registers (RADR0, RADR1) ■ Block Diagram of Address Match Detection Function Figure 24.2-1 shows the block diagram of the address match detection function. Figure 24.2-1 Block Diagram of the Address Match Detection Function Internal data bus PADR0 (24bit) Detect address setting register 0 PADR1 (24bit) Comparator Address latch INT9 instruction (INT9 interrupt generation) Detect address setting register 1 PACSR Reserved Reserved Reserved Reserved AD1E Reserved AD0E Reserved Address detection control register (PACSR) Reserved: Always set to "0" ● Address latch The address latch stores the value of the address output to the internal data bus. ● Address detection control register (PACSR) The address detection control register enables or disables output of an interrupt at an address match. ● Detect address setting registers (PADR0, PADR1) The detect address setting registers set the address that is compared with the value of the address latch. Note: The addresses of the detect address setting register are 1FF0H to 1FF5H and are included in the RAM area. Therefore, the access to the RAM area should not be performed during the use of this function. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 559 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.3 Configuration of Address Match Detection Function 24.3 MB90330A Series Configuration of Address Match Detection Function This section details the registers used by the address match detection function. ■ List of Registers and Reset Values of Address Match Detection Function Figure 24.3-1 List of Registers and Reset Values of Address Match Detection Function bit Address detection control register (PACSR) Address : 009EH Detect address setting register 0 (PADR0): High Address : 1FF2H Detect address setting register 0 (PADR0): Middle Address : 1FF1H Detect address setting register 0 (PADR0): Low Address : 1FF0H Detect address setting register 1 (PADR1): High Address : 1FF5H Detect address setting register 1 (PADR1): Middle Address : 1FF4H Detect address setting register 1 (PADR1): Low Address : 1FF3H bit bit bit bit bit bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 × × × × × × × × 15 14 13 12 11 10 9 8 × × × × × × × × 7 6 5 4 3 2 1 0 × × × × × × × × 7 6 5 4 3 2 1 0 × × × × × × × × 15 14 13 12 11 10 9 8 × × × × × × × × 7 6 5 4 3 2 1 0 × × × × × × × × × : Undefined 560 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.3 Configuration of Address Match Detection Function MB90330A Series 24.3.1 Address Detection Control Register (PACSR) The address detection control register (PACSR) enables or disables output of an interrupt at an address match. When an address match is detected when output of an interrupt at an address match is enabled, the INT9 interrupt is generated. ■ Address Detection Control Register (PACSR) Figure 24.3-2 Address Detection Control Register (PACSR) bit 7 6 5 4 3 2 1 0 Initial value Reserved Reserved Reserved Reserved AD1E Reserved AD0E Reserved 00000000B Address 009EH R/W R/W R/W R/W R/W R/W R/W R/W bit 0 Reserved bit Reserved 0 Always set to "0" bit 1 Address match detection enable bit 0 AD0E 0 Disables address match detection in PADR0 1 Enables address match detection in PADR0 bit 2 Reserved bit Reserved 0 Always set to "0" bit 3 Address match detection enable bit 1 AD1E 0 Disables address match detection in PADR1 1 Enables address match detection in PADR1 bit 4 Reserved bit Reserved 0 Always set to "0" bit 5 Reserved bit Reserved 0 Always set to "0" bit 6 Reserved bit Reserved 0 Always set to "0" bit 7 Reserved bit Reserved R/W : Readable/Writable : Initial value CM44-10129-6E 0 Always set to "0" FUJITSU MICROELECTRONICS LIMITED 561 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.3 Configuration of Address Match Detection Function MB90330A Series Table 24.3-1 Functions of Address Detection Control Register (PACSR) Bit Name bit 7 to bit 4 562 Function Always set to "0". Reserved bit bit 3 AD1E: Address match detection enable bit 1 The address match detection operation with the detect address setting register 1 (PADR1) is enabled or disabled. When set to "0": Disables the address match detection operation. When set to "1": Enables the address match detection operation. • When the value of detect address setting registers 1 (PADR1) matches with the value of address latch at enabling the address match detection operation (AD1E = 1), the INT9 instruction is immediately executed. bit 2 Reserved bit Always set to "0". bit 1 AD0E: Address match detection enable bit 0 The address match detection operation with the detect address setting register 0 (PADR0) is enabled or disabled. When set to "0": Disables the address match detection operation. When set to "1": Enables the address match detection operation. • When the value of detect address setting register 0 (PADR0) matches with the value of address latch at enabling the address match detect operation (AD0E = 1), the INT9 instruction is immediately executed. bit 0 Reserved bit Always set to "0". FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.3 Configuration of Address Match Detection Function MB90330A Series 24.3.2 Detect Address Setting Registers (PADR0, PADR1) The value of an address to be detected is set in the detect address setting registers. When the address of the instruction processed by the program matches the address set in the detect address setting registers, the next instruction is forcibly replaced by the INT9 instruction, and the interrupt processing program is executed. ■ Detect Address Setting Registers (PADR0, PADR1) Figure 24.3-3 Detect Address Setting Registers (PADR0, PADR1) PADR0, PADR1: High Address 1FF2H, 1FF5H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value D23 D22 D20 D19 D18 XXXXXXXXB D21 D17 D16 R/W R/W R/W R/W R/W R/W R/W R/W bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 PADR0, PADR1: Middle Address 1FF1H, 1FF4H D15 D14 D13 D12 D11 D10 D9 D8 Reset value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit 7 bit 6 b it 5 bit 4 bit 3 bit 2 bit 1 bit 0 PADR0, PADR1: Low Address 1FF0H, 1FF3H D7 D6 D5 D4 D3 D2 D1 D0 Reset value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W : Readable/Writable X : Undefined CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 563 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.3 Configuration of Address Match Detection Function MB90330A Series ■ Functions of Detect Address Setting Registers • There are two detect address setting registers (PADR0, PADR1) that consist of a high byte (bank), middle byte, and low byte, totaling 24 bits. Table 24.3-2 Address Setting of Detect Address Setting Registers Register Name Interrupt Output Enable Address Setting High Detect address setting register 0 (PADR0) Detect address setting register 1 (PADR1) PACSR: AD0E PACSR: AD1E Set the upper 8 bits of detect address 0 (bank). Middle Set the middle 8 bits of detect address 0. Low Set the lower 8 bits of detect address 0. High Set the upper 8 bits of detect address 1 (bank). Middle Set the middle 8 bits of detect address 1. Low Set the lower 8 bits of detect address 1. • In the detect address setting registers (PADR0, PADR1), starting address (first byte) of instruction to be replaced by INT9 instruction should be set. Figure 24.3-4 Setting of Starting Address of Instruction Code to be Replaced by INT9 Set to detect address (High : FFH, Middle : 00H, Low : 1FH) Address Instruction code FF001C : FF001F : FF0022 : A8 00 00 4A 00 00 4A 80 08 Mnemonic MOVW MOVW MOVW RW0, #0000 A, #0000 A,#0880 Notes: 564 • When an address of other than the first byte is set to the detect address setting register (PADR0, PADR1), the instruction code is not replaced by INT9 instruction and a program of an interrupt processing is not be performed. When the address is set to the second byte or subsequent, the address set by the instruction code is replaced by "01H" (INT9 instruction code) and, which may cause malfunction. • The detect address setting registers (PADR0, PADR1) should be set after disabling the address match detection (PACSR: AD0E = 0 or AD1E = 0) of corresponding address match control registers. If the detect address setting registers are changed without disabling the address match detection, the address match detection function will work immediately after an address match occurs during writing address, which may cause malfunction. • The address match detection function can be used only for addresses of the internal ROM area. If addresses of the external memory area are set, the address match detection function will not work and the INT9 instruction will not be executed. FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.4 Explanation of Operation of Address Match Detection Function MB90330A Series 24.4 Explanation of Operation of Address Match Detection Function If the addresses of the instructions executed in the program match those set in the detection address setting registers (PADR0, PADR1), the address match detection function will replace the first instruction with the INT9 instruction (01H) to branch to the interrupt processing program. ■ Operation of Address Match Detection Function Figure 24.4-1 shows the operation of the address match detection function when the detect addresses are set and an address match is detected. Figure 24.4-1 Operation of Address Match Detection Function Program execution The instruction address to be executed by program matches detect address setting register 0 Address Instruction code FF001C : FF001F : FF0022 : A8 00 00 4A 00 00 4A 80 08 Mnemonic MOVW MOVW MOVW RW0, #0000 A, #0000 A, #0880 Replaced by INT9 instruction (01H) ■ Setting Detect Address 1. Disable the detection address setting register 0 (PADR0) where the detect address is set for address match detection (PACSR: AD0E = 0). 2. Set the detect address in the detection address setting register 0 (PADR0). Set "FFH" at the higher bits of the detection address setting register 0 (PADR0), "00H" at the middle bits, and "1FH" at the lower bits. 3. Enable the detect address setting register 0 (PADR0) where the detect address is set for address match detection (PACSR: AD0E = 1). ■ Program Execution 1. If the address of the instruction to be executed in the program matches the set detect address, the first instruction code at the matched address is replaced by the INT9 instruction code (01H). 2. INT9 instruction is executed. INT9 interrupt is generated and then interrupt processing program is executed. Table 25.5-2 shows the function list of the hardware sequence flag. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 565 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.4 Explanation of Operation of Address Match Detection Function 24.4.1 MB90330A Series Example of Using Address Match Detection Function This section gives an example of patch processing for program correction using the address match detection function. ■ System Configuration and E2PROM Memory Map ● System configuration Figure 24.4-2 gives an example of the system configuration using the address match detection function. Figure 24.4-2 Example of System Configuration Using Address Match Detection Function MCU SIN0 Serial E2PROM Interface E2PROM Storing patch program MB90330A series ■ E2PROM Memory Map Figure 24.4-3 shows the allocation of the patch program and data at storing the patch program in E2PROM. 566 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.4 Explanation of Operation of Address Match Detection Function MB90330A Series Figure 24.4-3 Allocation of E2PROM Patch Program and Data E2PROM Address PADR0 PADR1 0000H Patch program byte count 0001H Detect address 0 (Low) 0002H Detect address 0 (Middle) 0003H Detect address 0 (High) 0004H Patch program byte count 0005H Detect address 1 (Low) 0006H Detect address 1 (Middle) 0007H Detect address 1 (High) For patch program 0 For patch program 1 0010H Patch program 0 (main body) 0020H Patch program 1 (main body) ● Patch program byte count The total byte count of the patch program (main body) is stored. If the byte count is "00H", it indicates that no patch program is provided. ● Detect address (24 bits) The address where the instruction code is replaced by the INT9 instruction code due to program error is stored. This address is set in the detection address setting registers (PADR0, PADR1). ● Patch program (main body) The program executed by the INT9 interrupt processing when the program address matches the detect address is stored. Patch program 0 is allocated from any predetermined address. Patch program 1 is allocated from the address indicating <starting address of patch program 0 + total byte count of patch program 0>. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 567 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.4 Explanation of Operation of Address Match Detection Function MB90330A Series ■ Setting and Operating State ● Initialization • E2PROM data are all cleared to "00H". ● Occurrence of program error • By using the connector (UART), information about the patch program is transmitted to the MCU (MB90330A series) from the outside according to the allocation of the E2PROM patch program and data. • The MCU (MB90330A series) stores the information received from outside in the E2PROM. ● Reset sequence • After reset, the MCU (MB90330A series) reads the byte count of the E2PROM patch program to check the presence or absence of the correction program. • If the byte count of the patch program is not "00H", the higher, middle and lower bits at detect addresses 0 and 1 are read and set in the detection address setting registers 0 and 1 (PADR0, PADR1). The patch program (main body) is read according to the byte count of the patch program and written to RAM in the MCU (MB90330A series). • The patch program (main body) is allocated to the address where the patch program is executed in the INT9 interrupt processing by the address match detection function. • Address match detection is enabled (PACSR: AD0E = 1, AD1E = 1) ● INT9 Interrupt processing • Interrupt processing is performed by the INT9 instruction. The MB90330A series has no interrupt request flag by address match detection. Therefore, if the stack information in the program counter is discarded, the detect address cannot be checked. When checking the detect address, check the value of program counter stacked in the interrupt processing routine. • The patch program is executed, branching to the normal program. 568 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.4 Explanation of Operation of Address Match Detection Function MB90330A Series ■ Operation of Address Match Detection Function at Storing Patch Program in E2PROM Figure 24.4-4 shows the operation of the address match detection function at storing the patch program in E2PROM. Figure 24.4-4 Operation of Address Match Detection Function at Storing Patch Program in E2PROM 000000H (3) Patch program RAM Detection address setting register (1) Detection address setting (reset sequence) Serial E2PROM interface E2PROM . Patch program byte count . Address for address detection . Patch program ROM (2) (4) Program error FFFFFFH (1) Execution of detection address setting of reset sequence and normal program (2) Branch to patch program which expanded in RAM with INT9 interrupt processing by address match detection (3) Patch program execution by branching of INT9 processing (4) Execution of normal program which branches from patch program CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 569 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.4 Explanation of Operation of Address Match Detection Function MB90330A Series ■ Flow of Patch Processing Figure 24.4-5 shows the flow of patch processing using the address match detection function. Figure 24.4-5 Flow of Patch Processing E2PROM MB90330A series I/O area 000000H 000100H Register/RAM area 000400H Patch program 000480H RAM area RAM Stack area 0000H Patch program byte count : 80H 0001H Detect address (Low) : 00H 0002H Detect address (Middle) : 80H 0003H Detect address (High) : FFH 0010H Patch program 000900H Detection address setting register 0090H FFFFH FF0000H ROM Program error FF8000H FF8050H FFFFFFH YES Reset INT9 Read the 00H of E2PROM Branch to patch program JMP 000400H Execution of patch program 000400H to 000480H E2PROM : 0000H =0 NO End of patch program JMP FF8050H Read detect address E2PROM : 0001H to 0003H ↓ MCU : Set to PADR0 Read patch program E2PROM : 0010H to 008FH ↓ MCU : 000400H to 00047FH Enable address match detection (PACSR : AD0E = 1) Execution of normal program NO 570 Program address PC= PADR0 YES INT9 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.5 Program Example of Address Match Detection Function MB90330A Series 24.5 Program Example of Address Match Detection Function This section gives a program example for the address match detection function. ■ Program Example for Address Match Detection Function ● Processing specifications If the address of the instruction to be executed by the program matches the address set in the detection address setting register (PADR0), the INT9 instruction is executed. ● Coding example PACSR EQU 00009EH ; Address detection control register PADRL EQU 001FF0H ; Detection address setting register 0 (Low) PADRM EQU 001FF1H ; Detection address setting register 0 (Middle) PADRH EQU 001FF2H ; Detection address setting register 0 (High) ; ;-----Main program--------------------------------------------------------------CODE CSEG START: ; Stack pointer (SP), etc., ; already reset MOV PADRL,#00H ; Set address detection register 0 (Low) MOV PADRM,#00H ; Set address detection register 0 (Middle) MOV PADRH,#00H ; Set address detection register 0 (High) ; MOV I:PACSR,#00000010B ; Enable address match : processing by user : LOOP: : processing by user : BAR LOOP ;-----Interrupt program---------------------------------------------------------WARI: : processing by user : CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 571 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.5 Program Example of Address Match Detection Function BETI CODE MB90330A Series ; Return from interrupt processing ENDS ;-----Vector setting------------------------------------------------------------VECT VECT CSEG ABS=0FFH ORG 00FFDCH DSL WARI ORG 00FFDCH DSL START DB 00H ; Set to single-chip mode ENDS END 572 ; Set reset vector START FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 25 FLASH MEMORY This chapter describes the functions and operations of 3M/4M-bit flash memory. There are three methods for writing and erasing date on flash memory as described in the following. • Programming and erasing by executing program • Writing by cereal writer • Flash memory writer In this chapter, we describe "Write/Erase by Program Execution". 25.1 Overview of Flash Memory 25.2 Sector Configuration of Flash Memory 25.3 Flash Memory Control Status Register (FMCS) 25.4 Automatic Algorithm Initiation Method of Flash Memory 25.5 Check the Execution State of Automatic Algorithm 25.6 Write/Erase of Flash memory Code: CM44-00105-1E CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 573 CHAPTER 25 FLASH MEMORY 25.1 Overview of Flash Memory 25.1 MB90330A Series Overview of Flash Memory The flash memory is allocated from F9 to FF banks on the CPU memory map. The flash memory can be read-accessed and program-accessed from the CPU using the function of the flash memory interface circuit. Writing/erasing on flash memory can be executed by the instructions from the CPU through the flash memory interface circuit. Additionally, rewriting can be executed in the mounted condition by the control of the built-in CPU, the effective improvement of the program and data are realized. ■ Features of Flash Memory Flash memory has the following features. • Uses automatic program algorithm (Embedded Algorithm: the same manner as MBM29LV400TC.) • Erase pause/restart function • Detection of completion of writing/erasing by data polling and toggle bit. • Detection of completion of writing/erasing by CPU interrupts. • Erase per sector enabled (random sector combination) • Programming/erase count 10000 (min.) • Sector protect function (Possibility that sets up with a recommendation parallel writer) ■ Flash Memory Size and Products Either 3M-bit or 4M-bit flash memory is mounted, depending on your model type. ● 3M-bit flash memory • Product: MB90F334A • Size: 384K Bytes / 192K words • Sector configuration: 64K × 5 + 32K + 8K × 2 + 16K ● 4M-bit flash memory • Product: MB90F335A • Size: 512K Bytes / 256K words • Sector configuration: 64K × 6 + 32K × 2 + 8K × 4 + 16K × 2 ■ Method for Writing/deleting Flash Memory Programming and erasing flash memory cannot be performed at one time. In other words, to perform writing/erasing data on flash memory, it possible to execute writing operation by copying the program on the flash memory on RAM and executing from RAM, without program-accessing from the flash memory. 574 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 25 FLASH MEMORY 25.2 Sector Configuration of Flash Memory MB90330A Series 25.2 Sector Configuration of Flash Memory Sector configuration of the flash memory is shown. ■ Sector Configuration Figure 25.2-1 and Figure 25.2-2 show the sector configuration of the 3M-bit and 4M-bit flash memory respectively. The upper and lower addresses of each sector are shown in the figure. Figure 25.2-1 Sector Configuration of 3M-bit Flash Memory Flash memory CPU address Writer address* FFFFFFH 7FFFFH FFC000H FFBFFFH 7C000H 7BFFFH FFA000H FF9FFFH 7A000H 79FFFH FF8000H FF7FFFH 78000H 77FFFH FF0000H FEFFFFH 70000H 6FFFFH FE0000H FDFFFFH 60000H 5FFFFH FD0000H FCFFFFH 50000H 4FFFFH FC0000H FBFFFFH 40000H 3FFFFH FB0000H FAFFFFH 30000H 2FFFFH FA0000H F9FFFFH 20000H 1FFFFH F90000H F8FFFFH 10000H 0FFFFH F80000H 00000H SA8 (16K bytes) SA7 ( 8K bytes) SA6 ( 8K bytes) SA5 (32K bytes) SA4 (64K bytes) SA3 (64K bytes) Using disabled SA2 (64K bytes) SA1 (64K bytes) SA0 (64K bytes) Using disabled In the case of access from CPU, SA0 is allocated on the F9 bank register, SA1 on the FA bank register, SA2 on the FB bank register, SA3 on the FD bank register, SA4 on the FE bank register, and SA5 to SA8 on the FF bank register. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 575 CHAPTER 25 FLASH MEMORY 25.2 Sector Configuration of Flash Memory MB90330A Series Figure 25.2-2 Sector Configuration of 4M-bit Flash Memory Flash memory CPU address FFFFFF H Writer address* 7FFFFH FFC000 H FFBFFFH 7C000H 7BFFFH FFA000 H FF9FFF H 7A000H 79FFF H FF8000 H FF7FFF H 78000H 77FFF H FF0000 H FEFFFFH 70000 H 6FFFF H FE0000H FDFFFFH 60000 H 5FFFF H FD0000H FCFFFFH 50000H 4FFFF H FC0000H FBFFFFH 40000H 3FFFFH FBC000 H FBBFFFH 3C000 H 3BFFFH FBA000H FB9FFF H 3A000H 39FFF H FB8000 H FB7FFF H 38000H 37FFF H FB0000H FAFFFFH 30000H 2FFFFH FA0000H F9FFFFH 20000H 1FFFFH F90000H F8FFFFH 10000H 0FFFFH F80000H 00000H SA13 (16K bytes) SA12 (8K bytes) SA11 (8K bytes) SA10 (32K bytes) SA9 (64K bytes) SA8 (64K bytes) SA7 (64K bytes) SA6 (16K bytes) SA5 (8K bytes) SA4 (8K bytes) SA3 (32K bytes) SA2 (64K bytes) SA1 (64K bytes) SA0 (64K bytes) In the case of access from CPU, SA0 is allocated on the F8 bank register, SA1 on the F9 bank register, SA2 on the FA bank register, SA3 to SA6 on the FB bank register, SA7 on the FC bank register, and SA8 on the FD bank register, SA9 on the FE bank register, SA10 to SA13 on the FF bank register. *: The writer address The writer address is the address corresponding to the CPU address when data is written on the flash memory with the parallel writer. When writing/erasing is executed using a general-purpose writer, writing/ erasing is executed in this address. 576 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 25 FLASH MEMORY 25.3 Flash Memory Control Status Register (FMCS) MB90330A Series 25.3 Flash Memory Control Status Register (FMCS) The flash memory control status register (FMCS), which is allocated in the flash memory interface circuit, is used for writing/erasing on the flash memory. ■ Flash Memory Control Status Register (FMCS) Figure 25.3-1 shows the bit configuration of the flash memory control status register (FMCS). Figure 25.3-1 Bit Configuration of Flash Memory Control Status Register (FMCS) Flash memory control status register (FMCS) bit Address: 0000AEH 7 INTE R/W 6 RDYINT R/W 5 4 WE RDY R/W R 3 2 1 0 Reserved Reserved Reserved Reserved W W W Initial value 000X0000B W R/W : Readable/Writable R: Read only W: Write only The function of each bit in the flash memory control status register (FMCS) is described in the following. [bit 7] INTE: INTerrupt Enable Finishing writing/erasing on the flash memory allows the CPU to generate an interrupt. If the INTE bit is "1" and the RDYINT bit is "1", an interrupt to the CPU is generated. If the INTE bit is "0", the interrupt is not generated. 0 Interrupt disabled in writing/erasing end 1 Interruption permission by writing/erase end [bit 6] RDYINT: ReaDY INTerrupt This is the bit representing the operation state of flash memory. Completion of writing/erasing on the flash memory allows this bit to set to "1". After writing/erasing on flash memory, it is not possible to write/erase to flash memory while the RDYINT bit is "0". After writing/erasing is completed and "1" is set, writing/erasing to flash memory is possible. Writing "0" clears to "0" and writing "1" is ignored. The completion timing of the flash memory automatic algorithm (see Section "25.4 Automatic Algorithm Initiation Method of Flash Memory") sets to "1". When the read modify write (RMW) instruction is used, "1" is always read. CM44-10129-6E 0 During writing/the deletion operation execution 1 Completion of writing/erasing operation (occurrence of interrupt requests) FUJITSU MICROELECTRONICS LIMITED 577 CHAPTER 25 FLASH MEMORY 25.3 Flash Memory Control Status Register (FMCS) MB90330A Series [bit 5] WE: Write Enable It is a write enable bit to the flash memory area. When the setting is "1", writing after issuing command sequences for F9 to FB, FD to FF banks (see Section "25.4 Automatic Algorithm Initiation Method of Flash Memory") is executed on the area in the flash memory. The signal of writing/ deletion is not generated at "0". It is used for activating the write/ erase command of flash memory. In order to avoid erroneous data writing to the flash memory, it is recommended to set "0" permanently when the writing/erasing command is not used. 0 Writing Erasing on Flash Memory disabled 1 Writing Erasing on Flash Memory enabled [bit 4] RDY: ReaDY This is the writing/erasing permission bit of flash memory. While this is "0", the writing/erasing flash memory are disabled. However, the read/reset command or sector erase suspend command is enabled in this state. 0 During writing/ deletion operation execution 1 Completion of writing/erasing operation (write/erase the next data enabled) [bit 3 to bit 0] Reserved bit These are reserved bits. Be sure to set to "0". Note: As for the FMCS register, only byte access is possible. ■ Automatic Algorithm End Timing Figure 25.3-2 shows the relation between automatic algorithm end timing and RDYINT bit and RDY bit. RDYINT and RDY bits do not change at the same time. Please make the program to judge either by one of bits. Figure 25.3-2 Relation between Automatic Algorithm End Timing and RDYINT Bit and RDY Bit Automatic algorithm End timing RDYINT bit RDY bit 1 Machine cycle 578 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 25 FLASH MEMORY 25.4 Automatic Algorithm Initiation Method of Flash Memory MB90330A Series 25.4 Automatic Algorithm Initiation Method of Flash Memory There are four types of commands to start the automatic algorithm of flash memory: read/reset, write, sector erase, and chip erase. The control of the suspend and the restart is enabled for the sector erase. ■ Command Sequence Table Table 25.4-1 lists the commands used for flash memory write/erase. All data written on the command register is in the units of byte, but be sure that the data can be written in word access. In this case, highorder byte data is ignored. Table 25.4-1 Command Sequence Table Command Sequence Bus Programming Cycle the 1th bus Programming Cycle the 2th bus Programming Cycle the 3th bus Programming Cycle Address Data Address Data Address Data the 4th bus Programming Cycle the 5th bus Programming Cycle the 6th bus Programming Cycle Address Data Address Data Address Data - - - - - - Read/ Reset * 1 FxXXXX XXF0 - - Read/ Reset * 4 FxAAAA XXAA Fx5554 XX55 FxAAAA XXF0 RA RD - - - - Programming 4 FxAAAA XXAA Fx5554 XX55 FxAAAA XXA0 PA (even) PD (word) - - - - Chip Erasing 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXAA Fx5554 XX55 FxAAAA XX10 XX55 SA (even) XX30 Sector Erasing 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXAA Fx5554 Sector Erasing being Suspended Entry of Address "FxXXXX" Data(xxB0H) temporally suspends erasing a sector in the middle of erasing the sector. Sector Erasing being restarted Entry of Address "FxXXXX" Data(xx30H) restarts erasing after the temporal suspension of erasing of the sector. Auto-Select 3 FxAAAA XXAA Fx5554 XX55 FxAAAA XX90 - - - - - - RA: Read address PA: Program address. Only even addresses can be specified. SA: See sector addresses (see Section "25.2 Sector Configuration of Flash Memory"). RD: Read data PD: Program data. Only word data can be specified. *:Two kinds of read/reset commands can reset flash memory to the read mode. Notes: • The address Fx in the table means FF, FE, FD, FB, FA, and F9. In each operation, specify this as the value of the bank to be accessed. • Addresses in the table are the values in the CPU memory map. All addresses and data are expressed as hexadecimals. However, "X" is any value. The Auto-Select in Table 25.4-1 is a command that is used to recognize the state of the sector protection. Actually, an address is needed to be set along with the above command as follows: Table 25.4-2 Address Setting at Auto-Select Sector protection AQ13 to AQ17 AQ7 AQ2 AQ1 AQ0 DQ7 to DQ0 Sector address L H L L CODE * *: "01H" for the output in protected sector addresses, "00H" for the output in non-protected sector addresses. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 579 CHAPTER 25 FLASH MEMORY 25.5 Check the Execution State of Automatic Algorithm 25.5 MB90330A Series Check the Execution State of Automatic Algorithm Because write/erase flow are performed through automatic algorithm in flash memory, the algorithm must wait signals from hardware that notify the operation conditions or operation end. This automatic algorithm can check the operation state of the internal flash memory by the following hardware sequence. ■ Hardware Sequence Flag The hardware sequence flag consists of 4-bit outputs: DQ7, DQ6, DQ5, and DQ3. Each bit has the functions of the data polling flag (DQ7), toggle bit flag (DQ6), timing limit excess flag (DQ5), and sector erase timer flag (DQ3). These flags can be used to confirm whether write/chip sector erase end and erase code write are effective or not. Reference to the hardware sequence flag, read-access to the address in the target sector in the flash memory after setting the command sequence (See Table 25.4-1). Table 25.5-1 shows the bit allocation of the hardware sequence flag. Table 25.5-1 Bit Allocation of Hardware Sequence Flag Bit No. Hardware sequence flag 7 6 5 4 3 2 1 0 DQ7 DQ6 DQ5 - DQ3 - - - To check if the automatic write/chip sector erase is operating or ended, verify the hardware sequence flag or the RDY bit of the flash memory control register (FMCS). After the write/erase commands end, it returns to the read/reset state. When actually creating a program, perform the following procedures including data read after verifying the automatic write/erase end with one of these flags. Also, you can check if the sector erase code write after the second command is enabled by using the hardware sequence flag. The next section describes each hardware sequence flag. Table 25.5-2 shows the list of the hardware sequence flag functions. 580 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 25 FLASH MEMORY 25.5 Check the Execution State of Automatic Algorithm MB90330A Series Table 25.5-2 Function List of Hardware Sequence Flag State State change in Writing operation → writing completion normal operation (when program address specified) Chip sector deletion operation Wait for Sector Erasing → deletion completion Sector erasing suspended (Sector being erased) → Resumed Sector erasing being suspended (Sector not being deleted) Programming Chip sector deletion operation CM44-10129-6E DQ6 DQ5 DQ3 DQ7 → DATA:7 Toggle → DATA:6 0→ DATA:5 0→ DATA:3 0 → erasing start Sector Erasing being Suspended (Sector being erased) Abnormal operation DQ7 →1 Toggle → Stop 1 0 →1 0 →1 0 →1 1 →0 0 → Toggle 0 →1 0 DATA:7 DATA:6 DATA:5 DATA:3 DQ7 Toggle 0 1 0 Toggle 1 1 0 Toggle 0 →1 Toggle 1 →0 1 FUJITSU MICROELECTRONICS LIMITED 581 CHAPTER 25 FLASH MEMORY 25.5 Check the Execution State of Automatic Algorithm 25.5.1 MB90330A Series Data Polling Flag (DQ7) The data polling flag (DQ7) is a hardware sequence flag that notifies the state that the automatic algorithm execution is proceeding or ended by using the data polling function. ■ State Transition of Data Polling Flag (DQ7) Table 25.5-3 and Table 25.5-4 shows the state transition of the data polling flag. Table 25.5-3 State Transition of Data Polling Flag (State Change in Normal Operation) Operation State Programming → Completion DQ7 → DATA:7 DQ7 Chip and sector erasing → Completion Sector erasing wait → start 0→1 0 Sector Erasing being Suspended → Restart Sector being erased Sector Erasing → Temporary deletion stop Sector being erased 0→1 1→0 Sector Erasing Temporary Sector not being deleted DATA:7 Table 25.5-4 State Transition of Data Polling Flag (State Change in Abnormal Operation) Operation State Programming operation Chip sector erase operation DQ7 DQ7 0 ■ At Programming Operation If you execute read-access while executing the automatic write algorithm, the flash memory outputs the inversion data of the last update of bit 7 regardless of address specifications. If you execute read-access when the automatic write algorithm ends, the flash memory outputs the bit 7 of the read value of the specified address. ■ When Chip/sector Deletion Operates If you execute read-access from the sector which is currently being erased, while executing the automatic sector-erase algorithm, the flash memory outputs "0". If you execute read-access while executing the automatic chip-erase algorithm, the flash memory outputs "0", regardless of the specified address. Once the chip/sector-erase operation ends, the flash memory outputs "1". ■ Sector Erasing being Suspended If you execute read-access when the sector erase suspends, the flash memory outputs "1" if the specified address is the erased sector, and it outputs bit 7 (DATA: 7) of the read value of the specified address if it is not the erased sector. You can determine whether the current state is the sector suspend or not and which sector is being erased by referencing with the toggle bit flag (DQ6). 582 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E MB90330A Series CHAPTER 25 FLASH MEMORY 25.5 Check the Execution State of Automatic Algorithm Note: At the start-up of the automatic algorithm, the read-access to the specified address is disregarded. As the data polling flag (DQ7) ends, other bit outputs are enabled for data read. Therefore, be sure to read data after the automatic algorithm ends, following read-access whose end of the data polling has confirmed. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 583 CHAPTER 25 FLASH MEMORY 25.5 Check the Execution State of Automatic Algorithm 25.5.2 MB90330A Series Toggle Bit Flag (DQ6) Like the data polling flag (DQ7), the toggle bit flag (DQ6) is a hardware sequence flag that indicates that the automatic algorithm execution is proceeding or ended by the toggle bit function. ■ Transition State of Toggle Bit Flag (DQ6) Table 25.5-5 and Table 25.5-6 shows the transition state of the toggle bit flag. Table 25.5-5 Transition State of Toggle Bit Flag (State Change in Normal Operation) Operation State Programming → Completion Chip and sector erasing → Sector erasing wait → start Sector Erasing → Temporary deletion stop Sector being erased Sector Erasing being Suspended → Restart Sector being erased Sector Erasing Temporary Sector not being deleted Toggle Toggle → 1 1 → Toggle DATA:6 Completion Toggle DQ6 → DATA:6 Toggle → Stop Table 25.5-6 Transition State of Toggle Bit Flag (State Change in Abnormal Operation) Operation State Programming operation Chip sector deletion operation DQ6 Toggle Toggle ■ When Writing/chip Sector is Deleted If you execute read-access sequentially while executing the automatic write algorithm and the automatic algorithm of chip/sector erase, the flash memory outputs the toggle state generating "1" and "0" alternately per read, regardless of the specified address. If you execute read-access sequentially after the automatic write algorithm and the automatic chip/sector-erase algorithm end, the flash memory stops the toggle operation of bit 6 and outputs the bit 6 (DATA: 6) of the read value of the specified address. ■ Sector Erasing being Suspended If you execute read-access when the sector erase suspends, the flash memory outputs "1" if the specified address belongs to the sector being erased. If the specified address does not belong to the sector being erased, it outputs the bit 6 (DATA: 6) of the read value of the specified address. Reference: During writing, when the sector being written is rewrite-protected, the toggle operation is terminated without rewriting the data after toggle-operating for about 2μs. During erasing, if all the selected sectors are rewrite-protected, the toggle bit performs toggleoperation for about 100 μs, and then it goes back to the read/reset state without rewriting the data. 584 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 25 FLASH MEMORY 25.5 Check the Execution State of Automatic Algorithm MB90330A Series 25.5.3 Timing Limit Over Flag (DQ5) The timing limit excess flag (DQ5) is a hardware sequence flag that indicates that the automatic algorithm execution is over the predefined time (internal pulse frequency) in the flash memory. ■ Transition State of Timing Limit Over Flag (DQ5) Table 25.5-7 and Table 25.5-8 shows the transition state of the timing limit over flag. Table 25.5-7 Transition State of Timing Limit Over Flag (State Change in Normal Operation) Operation State Programming → Completion Chip and sector erasing → Sector erasing wait → start Completion 0 → DATA:5 DQ5 0→1 0 Sector Erasing being Suspended → Restart Sector being erased Sector Erasing → Temporary deletion stop Sector being erased 0 Sector Erasing Temporary Sector not being deleted 0 DATA:5 Table 25.5-8 Transition State of Timing Limit Over Flag (State Change in Abnormal Operation) Operation State Programming operation Chip sector deletion operation DQ5 1 1 ■ When Writing/chip Sector is Deleted If you execute read-access after starting the automatic algorithms of the write or the chip erase/sector erase, the flash memory outputs "0" if it is within the predefined time (time necessary for write/erase) and "1" if it is over the predefined time. As this flag is irrelevant to the state of the automatic algorithm, you can judge whether the write/erase algorithm was successfully executed or not. In other words, the automatic algorithm is still operating by the data polling or toggle bit functions when this flag outputs "1", you can recognize that writing was failed. For example, if you write "1" into the flash memory address to which "0" is already written, the operation fails. In this case, the flash memory is locked and the automatic algorithm does not end. In rare cases, it ends normally as if "1" was written to the address. Therefore, an effective data is not output from the data polling flag (DQ7). Also, the toggle bit flag (DQ6) does not terminate the toggle operation, and the timing limit excess flag (DQ5) outputs "1" overrunning the time limit. This state means that the flash memory does not have any defect, but it was not used properly. Be sure to execute the reset command if this state appears. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 585 CHAPTER 25 FLASH MEMORY 25.5 Check the Execution State of Automatic Algorithm 25.5.4 MB90330A Series Sector Erasing Timer Flag (DQ3) The sector erase timer flag (DQ3) is a hardware sequence flag that indicates whether the status is in the sector erase wait period or not after starting the sector erase command. ■ Transition State of Sector Erasing Timer Flag (DQ3) Table 25.5-9 and Table 25.5-10 shows the transition state of the sector erasing timer flag. Table 25.5-9 Transition State of Sector Erasing Timer Flag (State Change in Normal Operation) Operation State Programming → Completion Sector erasing wait → start Chip and sector erasing → Completion DQ3 0 → DATA:3 0→1 1 Sector Erasing → Temporary deletion stop Sector being erased Sector Erasing being Suspended → Restart Sector being erased 1→0 0→1 Sector Erasing Temporary Sector not being deleted DATA:3 Table 25.5-10 Transition State of Sector Erasing Timer Flag (State Change in Abnormal Operation) Operation State Programming operation Chip sector deletion operation DQ3 0 1 ■ When Sector Deletion Operate If you execute read-access after starting the sector erase command, the flash memory outputs "0" if this access is in the sector erase wait period and "1" if this access is over the sector erase wait period, regardless of the specified address of the sector. When the erase algorithm is in execution with the data polling and toggle bit functions, the internal erasing is beginning if this flag is "1". Any subsequent commands are ignored except for the write command or erase suspend command for the sector erase code until erasing finishes. When this flag is "0", the flash memory accepts writing of an additional sector erase code. To verify that, it is recommended to check this flag state before writing of subsequent erase codes. If it is "1" at the second state checking, the additional sector erase code may not be accepted. ■ Sector Erasing being Suspended If you execute read-access when the sector erase suspends, the flash memory outputs "1" if the specified address is the erased sector, and it outputs bit 3 (DATA: 3) of the read value of the specified address if it is not the erased sector. 586 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 25 FLASH MEMORY 25.6 Write/Erase of Flash memory MB90330A Series 25.6 Write/Erase of Flash memory This section describes the procedure to issue a command to start the automatic algorithm and how to perform the operations of the read/reset, write, chip erase, sector erase, sector erase suspend, and sector erase restart. ■ Write/Erase of Flash Memory The flash memory can execute the automatic algorithm by performing the read/reset, write, chip erase, sector erase, sector erase suspend, and sector erase restart operations to write in cycle into the bus of the command sequence (See Table 25.4-1). The write cycle into each bus needs to be performed consecutively. Besides, the automatic algorithm can detect the end time with data polling function or other functions. After normal termination, it returns to the read/reset state. In the following section, the following items regarding the write/erase on the flash memory are described. • Read/reset state • Writing Data • All data erasing (chip all erase) • Any data erasing (sector erase) • Suspend Sector erasing • Restart Sector erasing CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 587 CHAPTER 25 FLASH MEMORY 25.6 Write/Erase of Flash memory 25.6.1 MB90330A Series Read/Reset State in Flash Memory This section describes the procedure to issue the read/reset commands and to set the read/reset state in flash memory. ■ Read/Reset State in Flash Memory To set the flash memory to the read/reset state, it is possible to execute by sending the read/reset command sequentially in the command sequence table (See Table 25.4-1) to the target sector in the flash memory. The read/reset command has two kinds of command sequences of the one-time bus operation and the threetimes bus operation, while in fact, there is no fundamental differences between them. The read/reset state is the initial state of the flash memory, and this system is always the read/reset state at the time of the power-on or the normal command completion. Reading/reset is an input waiting state of other commands. In the read/reset state, you can read-access normally to read data. As with mask ROM, program access from the CPU is enabled. This command is not needed to read data in the normal data read. When you need to initialize the automatic algorithm as in the case of an abnormal command completion for some causes, this command is mainly used. 588 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 25 FLASH MEMORY 25.6 Write/Erase of Flash memory MB90330A Series 25.6.2 Writing Data to Flash Memory The procedure to issue the write command and write data into the flash memory is described. ■ Writing Data to Flash Memory To start the data write automatic algorithm, you may send the write command sequentially in the command sequence table (See Table 25.4-1) to the target sector in the flash memory. When data writing to the target address ends at the forth cycle, the automatic algorithm is activated and then the automatic writing starts. ● How to specify address Only an even address is acceptable for the write address specified in the data write cycle. An odd address does not allow you to write properly. In other words, writing into an even address per word data is required. However, execution of one programming command, permits programming of only one word for data. ● Notes on data programming Data "0" cannot be returned to data "1" by writing. If you write data "1" into data "0", the data polling algorithm (DQ7) or the toggle operation (DQ5) do not finish and the flash memory device is determined to have a defect, and as a result writing exceeds the predefined time, and the timing limit excess. However, when data is read while read/reset, data is "0". You can change data from "0" to "1" only in the erase operation. All commands are disregarded while the automatic write command is being executed. Please note that if the hardware reset is started while writing, the address data currently being written is not secured. ■ Writing Procedure of Flash Memory Figure 25.6-1 shows an Procedure example for writing to flash memory. You may determine the state of the automatic algorithm in the flash memory by using the hardware sequence flag (See Section "25.5 Check the Execution State of Automatic Algorithm"). In this section data polling flag (DQ7) is used to confirm an end of writing. Flag check data should be read from the address where data was last written. As the data polling flag (DQ7) is changed along with the timing limit excess flag (DQ5), you need to recheck the data polling flag bit (DQ7) even if the timing limit excess flag (DQ5) is "1". Likewise, the toggle bit flag (DQ6) terminates the toggle operation just when the timing limit excess flag (DQ5) changes into "1", you need to recheck the toggle bit flag (DQ6). CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 589 CHAPTER 25 FLASH MEMORY 25.6 Write/Erase of Flash memory MB90330A Series Figure 25.6-1 Procedure Example for Writing to Flash Memory Writing start FMCS : WE(bit5) Flash memory writing enabled Write command sequence FxAAAAH Fx555AH FxAAAAH Write address XXAAH XX55H XXA0H Write data Internal address read Data polling (DQ7) Next address Data Data 0 Timing limit (DQ5) Internal address read Data Data polling (DQ7) Data NO Write error End address YES FMCS : WE(bit5) Flash memory writing disabled Write complete 590 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 25 FLASH MEMORY 25.6 Write/Erase of Flash memory MB90330A Series 25.6.3 Erasing All Data from Flash Memory (Chip Erase) This section describes the procedure for issuing the chip erase command and erasing all the data from flash memory. ■ Erasing All Data from Flash Memory (Chip Erase) To erase all the data from the flash memory, you can erase by sending the chip erase command in the command sequence table (See Table 25.4-1) to the target sector in the flash memory. Chip deletion command is done by six bus operations. When data writing into the target address ends at the sixth cycle, the chip erase operation is started. Before chip erasing, the user need not perform programming to flash memory. While the automatic algorithm is executed, the flash memory writes "0" to check conditions before erasing all the cells automatically. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 591 CHAPTER 25 FLASH MEMORY 25.6 Write/Erase of Flash memory 25.6.4 MB90330A Series Erasing Any Data in Flash Memory (Sector Erasing) The procedure to issue the sector erase command and erase any data in the flash memory is described. Sector-by-sector erasing is enabled and multiple sectors can be specified at a time. ■ Erasing Any Data in Flash Memory (Sector Erasing) To erase any data in the flash memory, you may send the sector erase command sequentially in the command sequence table (See Table 25.4-1) to the target sector in the flash memory. ● How to specify sector The sector erase command is executed in six bus operations. In the sixth cycle, the minimum 50 μs sector erase wait is started by writing the sector erase code (30H) into any even one address accessible in the target sector. To erase multiple sectors, write the erase code (30H) into the address in the target sector to be erased, following the above procedure. ● Notes on specifying multiple sectors Sector erasing is started after a minimum 50 μs period waiting for sector erasing is completed after the last sector erase code has been programmed. In other words, when multiple sectors are erased at the same time, the next erase sector address and the erase code (in the command sequence sixth cycle) need to be entered within 50 μs, after which they may not be accepted. You may check if writing the subsequent sector erase code is enabled or not by the sector erase timer (hardware sequence flag: DQ3). In this case, make sure that the address to read the sector erase timer indicates the sector to be erased. ■ Procedure of Sector Deletion You may determine the state of the automatic algorithm in the flash memory by using the hardware sequence flag (See Section "25.5 Check the Execution State of Automatic Algorithm"). Figure 25.6-2 shows an example of the sector erase procedure of the flash memory. In this example, the toggle bit flag (DQ6) is used to check that erase ends. Please note that data to be read for flag check is read from the sector to be erased. The toggle bit flag (DQ6) terminates the toggle operation at the moment at which the timing limit excess flag (DQ5) changes into "1", you need to recheck the toggle bit flag (DQ6) even if the timing limit excess flag (DQ5) is "1". Likewise, the data polling flag (DQ7) changes at the moment at which the timing limit excess flag (DQ5) changes into "1", you need to recheck the data polling flag (DQ7). 592 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 25 FLASH MEMORY 25.6 Write/Erase of Flash memory MB90330A Series Figure 25.6-2 Example of Sector Erasing Procedure of Flash Memory Erase start FMCS : WE(bit5) Flash memory erase enabled Erase command sequence FxAAAAH Fx5554H FxAAAAH FxAAAAH Fx5554H Input to erase sector (30H) YES XXAAH XX55H XX80H XXAAH XX55H Is there any other sector? NO Internal address read Internal address read 1 Sector erase timer (DQ3) Internal address read 2 toggle bit (DQ6) YES Data 1 (DQ6) =Data 2 (DQ6) No erasing specification occurs within 50 μs additionally. Set the flag for starting again from the remainder andsuspend the erasing. NO Timing limit (DQ5) Internal address read 1 Internal address read 2 NO Toggle bit (DQ6) Data 1 (DQ6) =Data 2 (DQ6) YES Erase error Set the flag for starting again from the remainder YES NO FMCS : WE(bit5) Flash memory erase disabled Erase complete CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 593 CHAPTER 25 FLASH MEMORY 25.6 Write/Erase of Flash memory 25.6.5 MB90330A Series Flash Memory Sector Erase Suspension This section describes the procedure to issue the sector erase suspend command and suspend the sector erase of flash memory. Data can be read from the sector not being deleted. ■ Flash Memory Sector Erase Suspension To suspend the sector erase of the flash memory, you can perform the suspension by sending the sector erase suspend command in the command sequence table (See Table 25.4-1) to the flash memory. The sector erase suspend command enables you to suspend the erase while erasing a sector and read data from the sector that is not being erased. In this state, you can only read but cannot write. This command is enabled only when a sector is being erased including the erase wait time and ignored while erasing or writing to a chip. This command can be executed by writing the erase suspend code (B0H), for which the address should indicate any address in the flash memory. The sector erase suspend command is ignored at the second time for erase suspend. If the sector erase suspend command is entered during a sector erase wait period, sector erase wait is finished immediately and erase operation is stopped, and the state enters in erase-terminated condition. During sector deletion following the waiting period for sector deletion, if a deletion suspension command is input, deletion suspension status starts after a maximum of 15 μs. The sector erase suspend command is performed after 20 μs following the issuance of the sector erase command or sector erase resume command. 594 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 25 FLASH MEMORY 25.6 Write/Erase of Flash memory MB90330A Series 25.6.6 Flash Memory Sector Erase Resumption The procedure to issue the sector erase restart command and restart the flash memory sector erase that is suspended is described. ■ Flash Memory Sector Erase Resumption To restart the suspended sector erase, you can restart by sending the sector erase restart command sequentially in the command sequence table (See Table 25.4-1) to the flash memory. The sector erase resume command resumes sector erasing suspended by the sector erase suspend command. This command can be executed by writing the erase restart code (30H), for which the address should indicate arbitrary address in the flash memory area. Further, issuing the sector erase restart command is ignored while erasing a sector. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 595 CHAPTER 25 FLASH MEMORY 25.6 Write/Erase of Flash memory 596 MB90330A Series FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 26 EXAMPLE of CONNECTING SERIAL WRITING (FLASH MICROCONTROLLER PROGRAMMER MODE by YOKOGAWA DIGITAL COMPUTER CORPORATION) This chapter describes examples of serial write connection when using flash microcontroller programmer mode by Yokogawa Digital Computer Corporation. 26.1 Basic Configuration 26.2 Oscillation Clock Frequency and Serial Clock Input Frequency 26.3 Flash Microcontroller Programmer System Configuration 26.4 Example of Connecting Serial Writing CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 597 CHAPTER 26 EXAMPLE of CONNECTING SERIAL WRITING 26.1 Basic Configuration 26.1 MB90330A Series Basic Configuration The MB90F334A and MB90F335A support the serial on-board programming of flash ROM (Fujitsu Microelectronics standard). The specification for serial on-board programming are explained below. ■ The Serial On-board Writing Basic Component The flash microcontroller programmer made by Yokogawa Digital Computer Corporation is used for Fujitsu standard serial on-board programming. It is possible to choose between the program operated in single-chip mode and the program operated in internal ROM external bus mode and to write. Figure 26.1-1 shows the basic configuration of serial write connection examples. Figure 26.1-1 Basic Configuration of Example for Serial Write Connection Host interface cable General-purpose common connecting cable Flash microcontroller CLK synchronous serial MB90F334A/ programmer MB90F335A User system Memory card Stand-alone operation enabled Note: Contact Yokogawa Digital Computer Corporation for details of the functions, operations, generalpurpose common connecting cable and applicable connectors of the flash microcontroller programmer. 598 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 26 EXAMPLE of CONNECTING SERIAL WRITING 26.1 Basic Configuration MB90330A Series ■ Pins Used for Fujitsu Standard Serial On-board Programming Table 26.1-1 shows the function of pins used for Fujitsu standard serial on-board programming. Table 26.1-1 Function of Used Pins Pin Function MD2,MD1,MD0 Mode Pin Supplementary Information Setting MD2=1, MD1=1, and MD0=0 allows the mode to be in the serial write mode. X0,X1 Oscillation pins Because the internal CPU operation clock is set to be the 1 multiplication PLL clock in the serial write mode, the internal operation clock frequency is the same as the oscillation clock frequency. When you perform the serial write, the frequency you can input into the high-speed oscillation input pin is fixed to 6 MHz. P60,P61 Writing program activating pins Input a "L" level to P60 and a "H" level to P61. RST Reset SIN0 Serial data input SOT0 Serial data output SCK0 Serial clock input - UART0 is used as CLK synchronous mode. VCC Supply voltage The write voltage (VCC=3.3 V ± 0.3 V) VSS GND GND pin is common to the ground of the flash microcontroller programmer. Figure 26.1-2 Pin Control Circuit Write control pin MB90F334A/MB90F335A Write control pin 10 kΩ TICS pin User Notes: • When the P60, P61, SIN0, SOT0, or SCK0 pin is used also in a user system, the control circuit shown in Figure 26.1-2 is required. • During serial write, the user circuit can be disconnected using the /TICS signal from the flash microcontroller programmer. Please refer to Section "26.4 Example of Connecting Serial Writing". CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 599 CHAPTER 26 EXAMPLE of CONNECTING SERIAL WRITING 26.2 Oscillation Clock Frequency and Serial Clock Input Frequency 26.2 MB90330A Series Oscillation Clock Frequency and Serial Clock Input Frequency The MB90F334A and MB90F335A serial clock frequencies that can be input are determined by the following expression: Thus, set up the flash microcontroller programmer to change the serial clock input frequency corresponding to the using oscillation clock frequency. ■ Oscillation Clock Frequency and Serial Clock Input Frequency Serial clock frequencies that can be input are determined using the expression below. Imputable serial clock frequency = 0.125 × oscillation clock frequency. Table 26.2-1 shows the serial clock frequencies that can be input. Table 26.2-1 Serial Clock Frequency that can be Input Oscillation clock frequency in 6 MHz 600 Maximum serial clock frequency that Maximum serial clock frequency that can be input to the microcontroller can be set 750 kHz FUJITSU MICROELECTRONICS LIMITED 500 kHz CM44-10129-6E CHAPTER 26 EXAMPLE of CONNECTING SERIAL WRITING 26.3 Flash Microcontroller Programmer System Configuration MB90330A Series 26.3 Flash Microcontroller Programmer System Configuration Table 26.3-1 shows the system configuration of the flash microcontroller programmer. ■ Flash Microcontroller Programmer System Table 26.3-1 System Configuration of Flash Microcontroller Programme Product name Part number Description AF420/AC4P FULL KEY model 100BASE-TX host interface AF620/AC4P FULL KEY model CAN interface 100BASE-TX host interface AF320/AC4P Single KEY model 100BASE-TX host interface AF520/AC4P Single KEY model CAN interface 100BASE-TX host interface Standard Target Probe AZ410 Standard Target Probe (a): 1 m Compact Modules FF801 Control modules for Fujitsu Microelectronics microcontroller Remote Controller AZ490 Remote Controller Flash Microcontroller Programmer Main Unit Memory card - PC Card Contact: Yokogawa Digital Computer Corporation Tel: + 81-42-333-6224 Note: Sales of the AF2xx/AF1xx series products have been terminated since March 31, 2007. The maintenance (repair) service of the products will be provided for five years from the date of the sales termination. The customer who hopes for the new or additional purchase of the product might consider the purchase of the succession product (AF400/300 and AF600/500 series) in the future. For details, contact Yokokawa Digital Computer Ltd. We will continue the support for Fujitsu microcomputer successors. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 601 CHAPTER 26 EXAMPLE of CONNECTING SERIAL WRITING 26.4 Example of Connecting Serial Writing 26.4 MB90330A Series Example of Connecting Serial Writing The examples of serial write connection is shown. ■ Example of Connecting Serial Writing Example of connecting serial writing has following two types. • Connection example in Single-chip mode (when using user power) • Example of minimum connection to flash microcontroller programmer (when using user power) 602 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 26 EXAMPLE of CONNECTING SERIAL WRITING 26.4 Example of Connecting Serial Writing MB90330A Series 26.4.1 Example Connection in Single-chip Mode (when Using User Power) In a user system, from TAUX3 and TMODE of flash microcontroller programmer, "1" for MD1 and "0" for MD0 are input to the MD2 and MD0 mode pins, which have been set to the single chip mode; this changes the mode to serial write mode. (Serial write mode:MD2, MD1, and MD0=110) ■ Connection Example in Single-chip Mode (when Using User Power) Figure 26.4-1 Example of Connection in Single Chip Mode (with User Power) User system Flash microcontroller programmer TAUX3 MB90F334A/ MB90F335A Connector DX10-28S MD2 (19) MD1 TMODE MD0 X0 (12) 6 MHz X1 TAUX (23) /TICS (10) P60 User /TRES (5) RST P61 User TTXD (13) SIN0 TRXD (27) SOT0 TCK (6) SCK0 TVCC (2) (7,8 GND VCC User power 14.15, 21.22, 1,28) VSS 14 pin 3, 4, 9, 11, 16, 17, 18, 20, 24, 25, 26 pins are OPEN DX10-28S : Right-angle type CM44-10129-6E 1 pin DX10-28S 28 pin 15 pin Connector (Hirose Electronics Ltd.) pin assignment FUJITSU MICROELECTRONICS LIMITED 603 CHAPTER 26 EXAMPLE of CONNECTING SERIAL WRITING 26.4 Example of Connecting Serial Writing MB90330A Series Notes: 604 • When the SIN0, SOT0, or SCK0 pin is used also in a user system, the control circuit shown in Figure 26.1-2 is required like P60. (During serial write, the user circuit can be disconnected using the /TICS signal from the flash microcontroller programmer.) • Connect the flash microcontroller programmer while the user power is off. FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 26 EXAMPLE of CONNECTING SERIAL WRITING 26.4 Example of Connecting Serial Writing MB90330A Series 26.4.2 Example of Minimum Connection to Flash Microcontroller Programmer (when Using User Power) During serial write, when MD2, MD0, and P60 pins are set as shown in Figure 26.4-2, it is unnecessary to connect these pins with the flash microcontroller programmer. ■ Example of Minimum Connection to Flash Microcontroller Programmer (when Using User Power) Figure 26.4-2 Example of Minimum Connection to Flash Microcontroller Programmer (when Using User Power) Flash microcontroller programmer User system MB90F334A/ MB90F335A At rewriting serial 1 MD2 MD1 At rewriting serial 1 MD0 At rewriting serial 0 X0 6 MHz X1 P60 At rewriting serial 0 User circuit P61 At rewriting serial 1 User circuit Connector DX10-28S /TRES TTXD TRXD TCK TVcc GND (5) (13) (27) (6) (2) (7, 8, 14, 15, 21, 22, 1, 28) 3, 4,9, 10, 11, 12, 16, 17, 18, 19, 20, 23, 24, 25, 16 pins are OPEN DX10-28S : Right-angle type CM44-10129-6E RST SIN0 SOT0 SCK0 Vcc User power Vss 14 pin 1 pin 28 pin 15 pin DX10-28S Pin assignment by connector (Hirose Electronics Ltd.) FUJITSU MICROELECTRONICS LIMITED 605 CHAPTER 26 EXAMPLE of CONNECTING SERIAL WRITING 26.4 Example of Connecting Serial Writing MB90330A Series Notes: 606 • When the SIN0, SOT0, or SCK0 pin is used also in a user system, the control circuit shown in Figure 26.1-2 is required. (During serial write, the user circuit can be disconnected using the /TICS signal from the flash microcontroller programmer.) • Connect the flash microcontroller programmer while the user power is off. FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 27 SERIAL PROGRAMMING CONNECTION (FUJITSU MICROELECTRONICS SERIAL PROGRAMMER) MB90F334A/335A supports serial onboard write (Fujitsu Microelectronics standard) to flash memory. This chapter explains the basic configuration for serial write to flash memory by using the Fujitsu Microelectronics Serial Programmer. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 607 CHAPTER 27 SERIAL PROGRAMMING CONNECTION 27.1 Fujitsu Microelectronics Serial Programmer 27.1 MB90330A Series Fujitsu Microelectronics Serial Programmer Fujitsu Microelectronics Serial Programmer (software) is an onboard programming tool for all Fujitsu Microelectronics-made controllers with built-in flash memory. Two types of Serial Programmer are available according to the PC interface (RS-232C or USB) used. Choose the type according to your environment. ■ Basic Configuration of FUJITSU MICROELECTRONICS MCU Programmer (Clock Asynchronous Serial Write) FUJITSU MICROELECTRONICS MCU Programmer is used when the PC and microcontroller are connected through an RS-232C cable. MCU Programmer writes data, through clock asynchronous serial communication, to built-in flash memory of a microcontroller installed in the user system. Figure 27.1-1 shows the basic configuration of FUJITSU MICROELECTRONICS MCU Programmer, and Table 27.1-1 lists the system configuration. Figure 27.1-1 Basic Configuration of FUJITSU MICROELECTRONICS MCU Programmer * User system RS-232C * RS-232C driver IC is required separately. Table 27.1-1 System Configuration of FUJITSU MICROELECTRONICS MCU Programmer Name Type FUJITSU MICROELECTRONICS MCU Programmer - Specifications Software (can be downloaded from Web (registration system))* * For registration, contact your sales representatives. 608 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 27 SERIAL PROGRAMMING CONNECTION 27.1 Fujitsu Microelectronics Serial Programmer MB90330A Series Figure 27.1-2 shows a connection example. Figure 27.1-2 Connection Example using FUJITSU MICROELECTRONICS MCU Programmer User system 4.7 kΩ 1 for serial rewriting 1 MB90F334A/335A MD2 0 Vcc 1 MD1 4.7 kΩ 1 0 for serial rewriting MD0 0 4.7 kΩ 4.7 kΩ 1 P60 0 for serial rewriting 0 4.7 kΩ 4.7 kΩ 1 0 for serial rewriting P61 0 4.7 kΩ X0 6 MHz X1 RS-232C driver RST SIN0 SOT0 RS-232C Communication with UART Vss Note: The value of the pull-up resistor is just one example. Select the optimum value for each system. Table 27.1-2 Oscillating frequency and communication baud rate available for clock asynchronous serial communication Master Oscillating Frequency Communication Baud Rate 6 MHz 19200 bps CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 609 CHAPTER 27 SERIAL PROGRAMMING CONNECTION 27.1 Fujitsu Microelectronics Serial Programmer MB90330A Series ■ Basic Configuration of FUJITSU MICROELECTRONICS USB Programmer (Clock Synchronous Serial Write) FUJITSU MICROELECTRONICS USB Programmer is used when the PC and microcontroller are connected through an adapter (MB2146-09A-E). USB Programmer writes data, through clock synchronous serial communication, to built-in flash memory of a microcontroller. Figure 27.1-3 shows the basic configuration of FUJITSU MICROELECTRONICS USB Programmer, and Table 27.1-3 lists the system configuration. Figure 27.1-3 Basic Configuration of FUJITSU MICROELECTRONICS USB Programmer CLK synchronous serial USB Adapter (MB2146-09A-E) User system Table 27.1-3 System Configuration of FUJITSU MICROELECTRONICS USB Programmer Name Type Specifications FUJITSU MICROELECTRONICS USB Programmer - Software (can be downloaded from Web (registration system))* Adapter MB2146-09A-E F2MC family BGM adapter (Accessory: USB cable) * For registration, contact your sales representatives. 610 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CHAPTER 27 SERIAL PROGRAMMING CONNECTION 27.1 Fujitsu Microelectronics Serial Programmer MB90330A Series Figure 27.1-4 shows a connection example. Figure 27.1-4 Connection example using FUJITSU MICROELECTRONICS USB Programmer 3.3 V MB90F334A/335A 3.3 V Vcc Connector of Yamaichi Electronics Ltd. FAP-10-08#4-0BS 3.3 V 4.7 kΩ P60 4.7 kΩ 1 for serial rewriting MOD2 1, 10 Connector of Yamaichi Electronics Ltd. FAP-10-08#4-0BS Index mark 9 pin 3.3 V 3.3 V MOD1 1 pin 4.7 kΩ P61 3.3 V 4.7 kΩ 10 pin 2 pin MOD0 (TOP VIEW) "L" for serial rewriting 4.7 kΩ BGM Pin name of Connector microcontroller BGM Connector Pin name of microcontroller 1 Vcc 6 SCK0 2 GND 7 SIN0 3 RSTX 8 Not connected 4 Not connected 9 GND 10 Vcc 5 SOT0 X0 6 MHz X1 3 RST 7 SIN0 5 SOT0 6 SCK0 2, 9 Vss Note: The value of the pull-up resistor is just one example. Select the optimum value for each system. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 611 CHAPTER 27 SERIAL PROGRAMMING CONNECTION 27.1 Fujitsu Microelectronics Serial Programmer 27.1.1 MB90330A Series Pins Used Table 27.1-4 Function of Used Pins Pin Function MD2,MD1,MD0 Mode Pin 612 Supplementary Information Setting MD2=1, MD1=1, and MD0=0 allows the mode to be in the serial write mode. X0,X1 Oscillation pins Because the internal CPU operation clock is set to be the 1 multiplication PLL clock in the serial write mode, the internal operation clock frequency is the same as the oscillation clock frequency. When you perform the serial write, the frequency you can input into the high-speed oscillation input pin is fixed to 6 MHz. P60,P61 Writing program activating pins For CLK synchronous serial writing, input "L" level to P60 and "H" level to P61. For CLK asynchronous serial writing, input "L" level to P60 and P61. RST Reset SIN0 Serial data input SOT0 Serial data output SCK0 Serial clock input - UART0 is used in CLK synchronous mode/CLK asynchronous mode. Note: SCK0 is not used in CLK asynchronous mode. VCC Supply voltage The write voltage (VCC=3.3 V ± 0.3 V) VSS GND GND pin is common to the ground of the flash microcontroller programmer. FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX The appendix describes the memory map and the instructions used in the F2MC-16LX. APPENDIX A Memory Map APPENDIX B Instructions CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 613 APPENDIX APPENDIX A Memory Map MB90330A Series APPENDIX A Memory Map The memory space divides into three modes. ■ Memory Map Figure A-1 Memory Map of MB90330A Series (1/3) Single chip mode (with ROM mirror function) FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (F8 bank) F80000H 00FFFFH 008000H 007FFFH ROM (image of FF bank) Peripheral area 007900H MB90F335A MB90F334A MB90V330A FFFFFFH FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H 00FFFFH 008000H 007FFFH ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (F8 bank) F80000H ROM (image of FF bank) Peripheral area 00FFFFH 008000H 007FFFH ROM (image of FF bank) Peripheral area 007900H 007900H MB90333A FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H 00FFFFH 008000H 007FFFH ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FB bank) ROM (image of FF bank) Peripheral area 007900H 007100H 006100H RAM area (28K bytes) 000100H Register 0000FBH 000100H 000000H 614 Register 000100H 004100H RAM area (16K bytes) 000100H Register 0000FBH Peripheral area Peripheral area 000000H Register 0000FBH 0000FBH Peripheral area RAM area (30K bytes) RAM area (24K bytes) 000000H FUJITSU MICROELECTRONICS LIMITED Peripheral area 000000H CM44-10129-6E APPENDIX APPENDIX A Memory Map MB90330A Series Notes: • For setting the ROM mirror function, see "23. ROM mirror function selection module". • When the ROM mirror function register has been set, the mirror image data at higher addresses (“FF8000H to FFFFFFH”) of bank FF is visible from the higher addresses (“008000H to 00FFFFH”) of bank 00. The ROM mirror function is effective for using the C compiler small model. The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be reproduced in bank 00. When the C compiler small model is used, the data table mirror image can be shown at “008000H to 00FFFFH” by storing the data table at “FF8000H to FFFFFFH”. Therefore, data tables in the ROM area can be referred without declaring the far addressing with the pointer. MB90F335A has the larger size of RAM area than MB90V330A, so that the emulation memory area needs to be set in the tools for a larger size of emulation area than 007100H. For details of setting, please refer to "Notes on Debug Environment Setting for MB90330A Series" by clicking "Application note" at the following URL. • • • • http://edevice.fujitsu.com/micom/en-support/ • Access to the emulation memory area (007100H to 0078FFH) is 3 cycles, which is greater by one cycle than access to the mounted RAM area. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 615 APPENDIX APPENDIX A Memory Map MB90330A Series Figure A-2 Memory Map of MB90330A Series (2/3) Internal ROM external bus mode (with ROM mirror function) FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (F8 bank) F80000H FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H Extenal area 00FFFFH 008000H 007FFFH ROM (image of FF bank) Peripheral area 007900H MB90F335A MB90F334A MB90V330A FFFFFFH FFFFFFH ROM (FF bank) FF0000H FEFFFFH ROM (FE bank) FE0000H FDFFFFH ROM (FD bank) *1 ROM (FB bank) ROM (FA bank) ROM (F9 bank) *1 FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH 008000H 007FFFH ROM (image of FF bank) Peripheral area ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) ROM (F8 bank) FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H 00FFFFH 008000H 007FFFH ROM (image of FF bank) Peripheral area 00FFFFH 008000H 007FFFH Extenal area Register RAM (30K bytes) 0000FBH RAM (24K bytes) 000100H Register 000000H 000100H Peripheral area 000000H Register 0000FBH 0000FBH Peripheral area ROM (FD bank) *2 ROM (FB bank) *2 Extenal area Extenal area ROM (image of FF bank) Peripheral area Extenal area 006100H 000100H ROM (FE bank) 007900H 007100H RAM (28K bytes) ROM (FF bank) Extenal area Extenal area 007900H 007900H Extenal area ROM (FE bank) F80000H Extenal area 00FFFFH ROM (FF bank) MB90333A FFFFFFH 004100H RAM (16K bytes) Register 000100H 0000FBH Peripheral area 000000H Peripheral area 000000H *1: In the area of F80000H to F8FFFFH and FC0000H to FCFFFFH at MB90F334 a value of "1" is read at read operating. *2: In the area of FA0000H to FAFFFFH and FC0000H to FCFFFFH at MB90333, a value of "1" is read at read operating. Notes: • For setting the ROM mirror function, see "23. ROM mirror function selection module" in "■ PERIPHERAL RESOURCES". • When the ROM mirror function register has been set, the mirror image data at higher addresses (“FF8000H to FFFFFFH”) of bank FF is visible from the higher addresses (“008000H to 00FFFFH”) of bank 00. The ROM mirror function is effective for using the C compiler small model. The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be reproduced in bank 00. When the C compiler small model is used, the data table mirror image can be shown at “008000H to 00FFFFH” by storing the data table at “FF8000H to FFFFFFH”. Therefore, data tables in the ROM area can be referred without declaring the far addressing with the pointer. MB90F335A has the larger size of RAM area than MB90V330A, so that the emulation memory area needs to be set in the tools for a larger size of emulation area than 007100H. For details of setting, please refer to "Notes on Debug Environment Setting for MB90330A Series" by clicking "Application note" at the following URL. http://edevice.fujitsu.com/micom/en-support/ Access to the emulation memory area (007100H to 0078FFH) is 3 cycles, which is greater by one cycle than access to the mounted RAM area. • • • • • 616 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX A Memory Map MB90330A Series Figure A-3 Memory Map of MB90330A Series (3/3) External ROM external bus mode FFFFFFH FFFFFFH FFFFFFH Extenal area 008000H 007FFFH Extenal area 007900H MB90F335A MB90F334A MB90V330A Extenal area 007900H Extenal area FFFFFFH Extenal area Extenal area Extenal area 008000H 007FFFH 008000H 007FFFH MB90333A 007900H 008000H 007FFFH Extenal area Extenal area Extenal area 007100H RAM area (28K bytes) Register 000100H 0000FBH 006100H 000100H 000100H Peripheral area 000000H Register 0000FBH 0000FBH Peripheral area 000000H RAM area (30K bytes) RAM area (24K bytes) Register Extenal area 007900H 004100H RAM area (16K bytes) 000100H Register 0000FBH Peripheral area 000000H Peripheral area 000000H Notes: • For setting the ROM mirror function, see "23. ROM mirror function selection module" in "■ PERIPHERAL RESOURCES". • When the ROM mirror function register has been set, the mirror image data at higher addresses (“FF8000H to FFFFFFH”) of bank FF is visible from the higher addresses (“008000H to 00FFFFH”) of bank 00. The ROM mirror function is effective for using the C compiler small model. The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be reproduced in bank 00. When the C compiler small model is used, the data table mirror image can be shown at “008000H to 00FFFFH” by storing the data table at “FF8000H to FFFFFFH”. Therefore, data tables in the ROM area can be referred without declaring the far addressing with the pointer. MB90F335A has the larger size of RAM area than MB90V330A, so that the emulation memory area needs to be set in the tools for a larger size of emulation area than 007100H. For details of setting, please refer to "Notes on Debug Environment Setting for MB90330A Series" by clicking "Application note" at the following URL. http://edevice.fujitsu.com/micom/en-support/ • • • • • Access to the emulation memory area (007100H to 0078FFH) is 3 cycles, which is greater by one cycle than access to the mounted RAM area. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 617 APPENDIX APPENDIX A Memory Map MB90330A Series ■ I/O Map Table A-1 lists addresses assigned to registers of each peripheral function. Table A-1 I/O Map (1 / 9) Address Registers Abbreviation Access Release Initial value 000000H Port 0 data register PDR0 R/W Port 0 XXXXXXXX 000001H Port 1 data register PDR1 R/W Port 1 XXXXXXXX 000002H Port 2 data register PDR2 R/W Port 2 XXXXXXXX 000003H Port 3 data register PDR3 R/W Port 3 XXXXXXXX 000004H Port 4 data register PDR4 R/W Port 4 XXXXXXXX 000005H Port 5 data register PDR5 R/W Port 5 XXXXXXXX 000006H Port 6 data register PDR6 R/W Port 6 XXXXXXXX 000007H Port 7 data register PDR7 R/W Port 7 XXXXXXXX 000008H Port 8 data register PDR8 R/W Port 8 XXXXXXXX 000009H Port 9 data register PDR9 R/W Port 9 -XXXXXXX 00000AH Port A data register PDRA R/W Port A XXXXXXXX 00000BH Use prohibited 00000CH Port B data register PDRB R/W Port B -XXXXXXX 00000DH Port B direction register DDRB R/W Port B -0000000 00000EH Use prohibited 00000FH 000010H Port 0 data direction register DDR0 R/W Port 0 00000000 000011H Port 1 direction register DDR1 R/W Port 1 00000000 000012H Port 2 direction register DDR2 R/W Port 2 00000000 000013H Port 3 direction register DDR3 R/W Port 3 00000000 000014H Port 4 direction register DDR4 R/W Port 4 00000000 000015H Port 5 direction register DDR5 R/W Port 5 00000000 000016H Port 6 direction register DDR6 R/W Port 6 00000000 000017H Port 7 direction register DDR7 R/W Port 7 00000000 000018H Port 8 direction register DDR8 R/W Port 8 00000000 000019H Port 9 direction register DDR9 R/W Port 9 -0000000 00001AH Port A direction register DDRA R/W Port A 00000000 00001BH Port 4 output terminal register ODR4 R/W Port 4 (OD control) 00000000 00001CH Port 0 Pull-up resistance register RDR0 R/W Port 0(PULLUP) 00000000 00001DH Port 1 Pull-up resistance register RDR1 R/W Port 1(PULLUP) 00000000 00001EH Analog input enable register 0 ADER0 R/W Port 7,A/D 11111111 00001FH Analog input enable register 1 ADER1 R/W Port 8,A/D 11111111 618 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX A Memory Map MB90330A Series Table A-1 I/O Map (2 / 9) Address Abbreviation Access 000020H Serial mode register 1 SMR0 R/W 000021H Serial control register 0 SCR0 R/W,W 000022H Registers Serial input data register 0/serial output data SIDR0/ SODR0 register 0 000023H Serial Status Register 0 R/W SSR0 R/W,R 000024H UART prescaler reload register 0 UTRLR0 R/W 000025H UART prescaler control register 0 UTCR0 R/W 000026H Serial mode register 1 SMR1 R/W 000027H Serial control register 1 SCR1 R/W,W 000028H Serial input data register 1/serial output data SIDR1/ SODR1 register 1 000029H Serial status register 1 R/W Release Initial value 00100000 00000100 UART0 XXXXXXXX 00001000 Communication Prescaler (UART0) 00000000 0000-000 00100000 00000100 UART1 XXXXXXXX SSR1 R/W,R 00002AH UART prescaler reload register 1 UTRLR1 R/W 00002BH UART prescaler control register 1 UTCR1 R/W 00002CH Serial mode register 2 SMR2 R/W 00100000 00002DH Serial control register 2 SCR2 R/W,W 00000100 00002EH Serial input data register 2/serial output data SIDR2/ SODR2 register 2 00002FH Serial Status Register 2 R/W 00001000 Communication Prescaler (UART1) UART2 00000000 0000-000 XXXXXXXX SSR2 R/W,R 000030H UART prescaler reload register 2 UTRLR2 R/W 000031H UART prescaler control register 2 UTCR2 R/W 000032H Serial mode register 3 SMR3 R/W 00100000 000033H Serial control register 3 SCR3 R/W,W 00000100 000034H Serial input data register 3/serial output data SIDR3/ SODR3 register 3 000035H Serial Status Register 3 R/W SSR3 R/W,R 000036H UART prescaler reload register 3 UTRLR3 R/W 000037H UART prescaler control register 3 UTCR3 R/W 000038H to 00003BH Communication Prescaler (UART2) UART3 00000000 0000-000 XXXXXXXX 00001000 Communication Prescaler (UART3) 00000000 0000-000 Use prohibited 00003CH DTP/interruption permission register ENIR R/W 00003DH DTP/interruption request register EIRR R/W 00003EH 00001000 Request level set register subordinate position 00003FH High rank of request level set register CM44-10129-6E ELVR R/W R/W FUJITSU MICROELECTRONICS LIMITED 00000000 DTP/external interrupt 00000000 00000000 00000000 619 APPENDIX APPENDIX A Memory Map MB90330A Series Table A-1 I/O Map (3 / 9) Address Registers Abbreviation Access 000040H A/D Control Status Register (Low) ADCS0 R/W 000041H A/D Control Status Register (High) ADCS1 R/W,W 000042H A/D Data Register (Low) ADCR0 R 000043H A/D Data Register (High) ADCR1 W,R 000044H Release Initial value 00-----0 8/10-bit A/D converter 00000000 XXXXXXXX 00101XXX Use prohibited Analog to digital conversion channel selection register ADMR R/W 8/10-bit A/D converter 00000000 000046H PPG0 operation mode control register PPGC0 R/W PPG ch.0 0X000XX1 000047H PPG1 operation mode control register PPGC1 R/W PPG ch.1 0X000001 000048H PPG2 operation mode control register PPGC2 R/W PPG ch.2 0X000XX1 000049H PPG3 operation mode control register PPGC3 R/W PPG ch.3 0X000001 00004AH PPG4 operation mode control register PPGC5 R/W PPG ch.4 0X000XX1 00004BH PPG5 operation mode control register PPGC6 R/W PPG ch.5 0X000001 00004CH PPG0,1 output control register PPG01 R/W PPG ch.0/1 000000XX R/W PPG ch.2/3 000000XX R/W PPG ch.4/5 000000XX 000045H 00004DH Use prohibited 00004EH PPG2,3 output control register 00004FH PPG23 Use prohibited 000050H PPG4,5 output control register 000051H PPG45 Use prohibited 000052H Input capture control status register 01 ICS01 R/W Input capture 0/1 00000000 000053H Input capture control status register 23 ICS23 R/W Input capture 2/3 00000000 000054H Low order of output compare control register ch.0 OCS0 R/W 000055H High order of output compare control register ch.1 OCS1 R/W 000056H Low order of output compare control register ch.2 OCS2 R/W 000057H High order of output compare control register ch.3 OCS3 R/W Serial mode control status register SMCS R/W SDR R/W SDCR R/W PWC Control Status Registers PWCSR R/W,R PWC data buffer register PWCR R/W PWC ratio of dividing frequency control register DIVR R/W 000058H 000059H 00005AH Serial data register 00005BH Communication Prescaler Control Register 00005CH 00005DH 00005EH 00005FH 000060H 620 FUJITSU MICROELECTRONICS LIMITED Output compare ch.0/1 Output compare ch.2/3 0000--00 ---00000 0000--00 ---00000 XXXX0000 I/O Extended serial 00000010 XXXXXXXX Communication Prescaler 0XXX0000 00000000 0000000X 16-bit PWC timer 00000000 00000000 ------00 CM44-10129-6E APPENDIX APPENDIX A Memory Map MB90330A Series Table A-1 I/O Map (4 / 9) Address Registers 000061H 000062H 000063H 000064H 000065H 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH 00006DH Abbreviation Access Initial value Use prohibited Timer control status register 0 Low order of 16-bit timer register 0 Low order of 16-bit reloading 0 High order of 16-bit timer register 0 TMCSR0 R/W TMR0 R TMRLR0 W 00000000 XXXX0000 16bit reload timer ch.0 XXXXXXXX XXXXXXXX TMR0 R XXXXXXXX High order of 16-bit reloading 0 TMRLR0 W XXXXXXXX Timer control status register 1 TMCSR1 R/W TMR1 R TMRLR1 W TMR1 R XXXXXXXX High order of 16-bit reloading 1 TMRLR1 W XXXXXXXX Timer control status register 2 TMCSR2 R/W TMR2 R TMRLR2 W TMR2 R XXXXXXXX TMRLR2 W XXXXXXXX Low order of 16-bit timer register 1 Low order of 16-bit reloading 1 High order of 16-bit timer register 1 Low order of 16-bit timer register 2 Low order of 16-bit reloading 2 High order of 16-bit timer register 2 High order of 16-bit reloading 2 00006EH 00000000 XXXX0000 16bit reload timer ch.1 XXXXXXXX XXXXXXXX 00000000 XXXX0000 16bit reload timer ch.2 XXXXXXXX XXXXXXXX Use prohibited 00006FH ROM Mirroring Function Select Register ROMM R/W,W 000070H I2C bus status register 0 IBSR0 R 000071H I2C bus control register 0 IBCR0 R/W 000072H Release I2C ROM mirror function ------11 00000000 00000000 I2C ICCR0 R/W 000073H I2C bus address register 0 IADR0 R/W XXXXXXXX 000074H I2C bus data register 0 IDAR0 R/W XXXXXXXX bus clock control register 0 000075H interface ch.0 XX0XXXXX Use prohibited 000076H I2C bus status register 1 IBSR1 R 00000000 000077H I2C bus control register 1 IBCR1 R/W 00000000 000078H I2C bus clock control register 1 ICCR1 R/W 000079H I2C bus address register 1 IADR1 R/W XXXXXXXX IDAR1 R/W XXXXXXXX 2 00007AH I C bus data register 1 00007BH CM44-10129-6E I2C interface ch.1 XX0XXXXX Use prohibited FUJITSU MICROELECTRONICS LIMITED 621 APPENDIX APPENDIX A Memory Map MB90330A Series Table A-1 I/O Map (5 / 9) Address Registers Abbreviation Access IBSR2 R 00000000 IBCR2 R/W 00000000 ICCR2 R/W 00007FH I C bus address register 2 IADR2 R/W XXXXXXXX 000080H I2C bus data register 2 IDAR2 R/W XXXXXXXX R/W 00000000 R/W 00000000 00007CH I2C bus status register 2 00007DH I2C bus control register 2 00007EH I2C clock control register 2 2 000081H to 000085H Release I2C interface ch.2 Initial value XX0XXXXX Use prohibited 000086H Low order of timer counter data register 000087H High order of timer counter data register 000088H Timer control status register, lower 000089H Timer control status register, higher 00008AH Low order of compare clear register TCDT TCCS R/W R/W 16-bit free-run timer 00000000 0XX00000 R/W XXXXXXXX R/W XXXXXXXX DCSR R/W 00000000 00009CH Low order of DMA status register DSRL R/W 00009DH Low order of DMA status register DSRH R/W 00009EH Program address detection control status register PACSR R/W Address compare detection 00000000 00009FH Delay interruption factor generation/release register DIRR R/W Delayed interrupt -------0 0000A0H Low-power consumption mode control register LPMCR R/W,W Low power consumption 00011000 CKSCR R/W,R Clock 11111100 μDMAC 00000000 00008BH High order of compare clear register 00008CH to 00009AH 00009BH CPCLR Use prohibited DMA descriptor channel specification register 0000A1H Clock select register 0000A2H μDMAC 00000000 00000000 Use prohibited 0000A3H 0000A4H DMA stop status register DSSR R/W 0000A5H Automatic ready function selection register ARSR W 0000A6H External address output control register HACR W 0000A7H Bus control signal selection register EPCR W 0000A8H Watchdog timer control register WDTC R,W Watchdog Timers X-XXX111 0000A9H Time-base timer control register TBTC R/W,W Time-base Timers 1--00100 0000AAH Watch timer control register WTC R/W,R Watch timer 10001000 0000ABH 622 0011--00 External pin ******** 1000*10- Use prohibited FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX A Memory Map MB90330A Series Table A-1 I/O Map (6 / 9) Address Registers Abbreviation Access 0000ACH Low order of DMA permission register DERL R/W 0000ADH High order of DMA permission register DERH R/W 0000AEH Flash memory control status register FMCS R/W,R,W 0000AFH Release μDMAC Flash memory I/F Initial value 00000000 00000000 000X0000 Use prohibited 0000B0H Interrupt control registers 00 ICR00 R/W 00000111 0000B1H Interrupt control registers 01 ICR01 R/W 00000111 0000B2H Interrupt control registers 02 ICR02 R/W 0000B3H Interrupt control registers 03 ICR03 R/W 00000111 0000B4H Interrupt control registers 04 ICR04 R/W 00000111 0000B5H Interrupt control registers 05 ICR05 R/W 00000111 0000B6H Interrupt control registers 06 ICR06 R/W 00000111 0000B7H Interrupt control registers 07 ICR07 R/W 00000111 0000B8H Interrupt control registers 08 ICR08 R/W 00000111 0000B9H Interrupt control registers 09 ICR09 R/W 00000111 0000BAH Interrupt control registers 10 ICR10 R/W 0000BBH Interrupt control registers 11 ICR11 R/W 00000111 0000BCH Interrupt control registers 12 ICR12 R/W 00000111 0000BDH Interrupt control registers 13 ICR13 R/W 00000111 0000BEH Interrupt control registers 14 ICR14 R/W 00000111 0000BFH Interrupt control registers 15 ICR15 R/W 00000111 0000C0H Host control register 0 HCNT0 R/W 00000000 0000C1H Host control register 1 HCNT1 R/W 00000001 0000C2H Host interruption register HIRQ R/W 00000000 0000C3H Host error status register HERR R/W 00000011 0000C4H Host state status register HSTATE R/W,R XX010010 HFCOMP R/W 00000000 0000C5H SOF interruption FRAME comparison register Interrupt controller Interrupt controller 0000C6H HRTIMER R/W 0000C8H HADR R/W HEOF R/W HFRAME R/W 0000CEH Host token end point register HTOKEN R/W 0000CFH Use prohibited 0000CCH 0000CDH USB HOST 00000000 XXXXXX00 0000C9H Host address register 0000CBH 00000111 00000000 0000C7H Retry timer setting register 0000CAH 00000111 EOF setting register FRAME setting register CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED X0000000 00000000 XX000000 00000000 XXXXX000 00000000 623 APPENDIX APPENDIX A Memory Map MB90330A Series Table A-1 I/O Map (7 / 9) Address Abbreviation Access UDC control register UDCC R/W EP0 control register EP0C EP1 control register EP1C EP2 control register EP2C EP3 control register EP3C EP4 control register EP4C EP5 control register EP5C Time stamp register TMSP 0000E0H UDC status register 0000E1H UDC interruption permission register 0000D0H 0000D1H 0000D2H 0000D3H 0000D4H 0000D5H 0000D6H 0000D7H 0000D8H 0000D9H 0000DAH 0000DBH 0000DCH 0000DDH 0000DEH 0000DFH 0000E2H 0000E3H 0000E4H 0000E5H 0000E6H 0000E7H 0000E8H 0000E9H 0000EAH 0000EBH 0000ECH 0000EDH 0000EEH 0000EFH 0000F0H 0000F1H 0000F2H 0000F3H 624 Registers Release Initial value 10100000 00000000 R/W 01000000 R/W XXXX0000 R/W 00000000 R/W 01100001 R/W 01000000 R/W 01100000 R/W 01000000 R/W 01100000 R/W 01000000 R/W 01100000 R/W 01000000 R/W 01100000 R 00000000 R XXXXX000 UDCS R/W XX000000 UDCIE R/W,R EP0I status register EP0IS EP0O status register EP0OS EP1 status register EP1S EP2 status register EP2S EP3 status register EP3S EP4 status register EP4S EP5 status register EP5S EP0 data register EP0DT EP1 data register EP1DT R/W USB function 00000000 XXXXXXXX R/W 10XXX1XX R/W,R 0XXXXXXX R/W 100XX000 R XXXXXXXX R/W,R 1000000X R 0XXXXXXX R/W,R 10000000 R 0XXXXXXX R/W,R 10000000 R 0XXXXXXX R/W,R 10000000 R 0XXXXXXX R/W,R 10000000 R/W XXXXXXXX R/W XXXXXXXX R/W XXXXXXXX R/W XXXXXXXX FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX A Memory Map MB90330A Series Table A-1 I/O Map (8 / 9) Address 0000F4H 0000F5H 0000F6H 0000F7H 0000F8H 0000F9H 0000FAH 0000FBH Registers Abbreviation EP2 data register EP2DT EP3 data register EP3DT EP4 data register EP4DT EP5 data register EP5DT 0000FCH to 0000FFH Use prohibited 000100H to #H RAM Area Access XXXXXXXX R/W XXXXXXXX R/W XXXXXXXX R/W R/W XXXXXXXX XXXXXXXX XXXXXXXX R/W XXXXXXXX R/W XXXXXXXX R/W XXXXXXXX R/W XXXXXXXX 001FF1H Middle order of program address detection register ch.0 001FF2H High order of program address detection register ch.0 R/W 001FF3H Low order of program address detection register ch.1 R/W 001FF4H Middle order of program address detection register ch.1 001FF5H High order of program address detection register ch.1 Address Match detection XXXXXXXX XXXXXXXX R/W XXXXXXXX R/W XXXXXXXX #H to 0078FFH Unused area 007900H Lower ch.0 of PPG reload register PRLL0 R/W 007901H Higher ch.0 of PPG reload register PRLH0 R/W 007902H Lower ch.1 of PPG reload register PRLL1 R/W 007903H Higher ch.1 of PPG reload register PRLH1 R/W 007904H Lower ch.2 of PPG reload register PRLL2 R/W 007905H Higher ch.2 of PPG reload register PRLH2 R/W 007906H Lower ch.3 of PPG reload register PRLL3 R/W 007907H Higher ch.3 of PPG reload register PRLH3 R/W 007908H Lower ch.4 of PPG reload register PRLL4 R/W 007909H Higher ch.4 of PPG reload register PRLH4 R/W 00790AH Lower ch.5 of PPG reload register PRLL5 R/W 00790BH Higher ch.5 of PPG reload register PRLH5 R/W CM44-10129-6E USB function R/W Low order of program address detection register ch.0 PADR1 Initial value R/W 001FF0H PADR0 Release FUJITSU MICROELECTRONICS LIMITED PPG ch.0 PPG ch.1 PPG ch.2 PPG ch.3 PPG ch.4 PPG ch.5 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 625 APPENDIX APPENDIX A Memory Map MB90330A Series Table A-1 I/O Map (9 / 9) Address Registers 00790CH to 00790FH Abbreviation Access Release Initial value Use prohibited 007910H Input Capture Data Register lower ch.0 007911H Input Capture Data Register upper ch.0 007912H Input Capture Data Register lower ch.1 007913H Input Capture Data Register upper ch.1 007914H Input Capture Data Register lower ch.2 007915H Input Capture Data Register upper ch.2 007916H Input Capture Data Register lower ch.3 007917H Input Capture Data Register upper ch.3 007918H Lower ch.0 of output compare register 007919H Higher ch.0 of output compare register 00791AH Lower ch.1 of output compare register 00791BH Higher ch.1 of output compare register 00791CH Lower ch.2 of output compare register 00791DH Higher ch.2 of output compare register 00791EH Lower ch.3 of output compare register 00791FH Higher ch.3 of output compare register IPCP0 IPCP1 IPCP2 IPCP3 OCCP0 OCCP1 OCCP2 OCCP3 R R R XXXXXXXX Input capture ch.0/1 XXXXXXXX XXXXXXXX R XXXXXXXX R XXXXXXXX R R Input capture ch.2/3 XXXXXXXX XXXXXXXX R XXXXXXXX R/W XXXXXXXX R/W R/W Output compare ch.0/1 XXXXXXXX XXXXXXXX R/W XXXXXXXX R/W XXXXXXXX R/W R/W Output compare ch.2/3 XXXXXXXX XXXXXXXX R/W XXXXXXXX 007920H DMA Buffer address pointer lower 8 bit DBAPL R/W XXXXXXXX 007921H DMA Buffer address pointer middle 8 bit DBAPM R/W XXXXXXXX 007922H DMA Buffer address pointer upper 8 bit DBAPH R/W XXXXXXXX 007923H DMA control register DMACS R/W XXXXXXXX μDMAC 007924H DMA I/O Register Address Pointer lower 8 bit DIOAL R/W 007925H DMA I/O Register Address Pointer upper 8 bit DIOAH R/W XXXXXXXX 007926H Lower 8 bits of DMA data counter DDCTL R/W XXXXXXXX 007927H Higher 8 bits of DMA data counter DDCTH R/W XXXXXXXX 007928H to 007FFFH Use prohibited XXXXXXXX • Explanation of reading/writing R/W: Readable and Writable R: Read only W: Write only • Explanation of initial value 0: The initial value is "0". 626 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX A Memory Map MB90330A Series 1: The initial value is "1". X: The initial value is irregular. -: It is Undefined bit. The initial value is indefinite. *: The initial value is "1" or "0". Note: You cannot use any I/O-related command to registers that are placed from 7900H to 7FFFH. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 627 APPENDIX APPENDIX A Memory Map MB90330A Series ■ Interrupt Factors, Interrupt Vectors, and Interrupt Control Registers Table A-2 lists the correspondence between interrupt factors, and interrupt vectors and interrupt control registers. Table A-2 Correspondence between Interrupt Factors, and Interrupt Vectors and Interrupt Control Registers EI2OS Clear Interrupt cause Reset INT9 instruction Exception USB function 1 USB function 2 USB function 3 USB function 4 USB HOST 1 USB HOST 2 0, 1 2 to 6 * I2C ch.0 DTP/External interrupt ch.0/ch.1 ❍ I2C ch.1 DTP/External interrupt ch.2/ch.3 ❍ I2C ch.2 DTP/External interrupt ch.4/ch.5 PWC/reload timer ch.0 DTP/External interrupt ch.6/ch.7 Input capture ch.0/ch.1 Reload timer ch.1 Input capture ch.2/ch.3 Reload timer ch.2 Output compare ch.0/ch.1 PPG ch.0/ch.1 Output comparech.2/ch.3 PPG ch.2/ch.3 ❍ Interrupt vector Address ICR Address #08 #09 #10 #11 #12 #13 #14 #15 #16 FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH - - ICR00 0000B0H ICR01 0000B1H ICR02 0000B2H #17 FFFFB8H #18 FFFFB4H ICR03 0000B3H #19 FFFFB0H #20 FFFFACH ICR04 0000B4H #21 FFFFA8H #22 #23 #24 #25 #26 #27 #28 ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH ❍ #29 #30 ❍ #31 #32 FFFF80H FFFF7CH #33 #34 #35 #36 FFFF78H FFFF74H FFFF70H FFFF6CH #37 #38 #39 #40 #41 #42 FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H 14 Δ Δ 7 Δ Δ 8 Δ ❍ 11 Δ 10 15 ❍ 13 9 12 Interrupt control register Number FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H Δ UART transmit end ch.2/ch.3 PPG ch.4/ch.5 UART receive end ch.2/ch.3 Analog to digital conversion / free-run timer UART transmit end ch.0/ch.1 Extended serial I/O UART receive end ch.0/ch.1 Time-base timer /Watch timer Flash writing/deletion Delay interrupt generation module 628 μDMAC Channel FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX A Memory Map MB90330A Series : Available. With the EI2OS stop function (the interrupt request flag is cleared with the interrupt clear signal. With a stop request.) ❍: Available (the interrupt request flag is cleared with the interrupt clear signal.) Δ: Usable at non-using interrupt source of sharing : Use disabled *: Channels 2 and 3 can use even when USB HOST is operated. Notes: • If the same interrupt control register (ICR) has two interrupt factors and the use of the EI2OS is permitted, the EI2OS is activated when either of the factors is detected. As any interrupt other than the activation factor is masked while the EI2OS is running, it is recommended that you should mask either of the interrupt requests when using the EI2OS. • The interrupt flag is cleared by the EI2OS interrupt clear signal for the resource that has two interrupt factors in the same interrupt control register (ICR). • When the same interrupt number has two interrupt factors, both interrupt request flags for a resource are cleared with the μDMAC interrupt clear signal. Therefore, when you use either of two interrupt factors for the DMAC function, another interrupt function is disabled. Set the interrupt request permission bit to "0" in the appropriate resource, and take measures by software polling. ■ Type and Function of USB Interrupt USB interrupt factor Details USB function1 End Point0-IN End Point0-OUT USB function 2 End Point1 to 5 * USB function 3 SUSP SOF BRST WKUP CONF USB function 4 SPK USB HOST 1 DIRQ CNNIRQ URIRQ RWKIRQ USB HOST 2 SOFIRQ CMPIRQ *: End Point 1 and 2 can use even when USB HOST is operated. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 629 APPENDIX APPENDIX B Instructions MB90330A Series APPENDIX B Instructions APPENDIX B describes the instructions used by the F2MC-16LX. B.1 Instruction Types B.2 Addressing B.3 Direct Addressing B.4 Indirect Addressing B.5 Execution Cycle Count B.6 Effective address field B.7 How to Read the Instruction List B.8 F2MC-16LX Instruction List B.9 Instruction Map Code: CM44-00202-3E 630 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series B.1 Instruction Types The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself. ■ Instruction Types The F2MC-16LX supports the following 351 types of instructions: • 41 transfer instructions (byte) • 38 transfer instructions (word or long word) • 42 addition/subtraction instructions (byte, word, or long word) • 12 increment/decrement instructions (byte, word, or long word) • 11 comparison instructions (byte, word, or long word) • 11 unsigned multiplication/division instructions (word or long word) • 11 signed multiplication/division instructions (word or long word) • 39 logic instructions (byte or word) • 6 logic instructions (long word) • 6 sign inversion instructions (byte or word) • 1 normalization instruction (long word) • 18 shift instructions (byte, word, or long word) • 50 branch instructions • 6 accumulator operation instructions (byte or word) • 28 other control instructions (byte, word, or long word) • 21 bit operation instructions • 10 string instructions CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 631 APPENDIX APPENDIX B Instructions B.2 MB90330A Series Addressing With the F2MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used. Some instructions permit the user to select several types of addressing. ■ Addressing The F2MC-16LX supports the following 23 types of addressing: 632 • Immediate (#imm) • Register direct • Direct branch address (addr16) • Physical direct branch address (addr24) • I/O direct (io) • Abbreviated direct address (dir) • Direct address (addr16) • I/O direct bit address (io:bp) • Abbreviated direct bit address (dir:bp) • Direct bit address (addr16:bp) • Vector address (#vct) • Register indirect (@RWj j = 0 to 3) • Register indirect with post increment (@RWj+ j = 0 to 3) • Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) • Long register indirect with displacement (@RLi + disp8 i = 0 to 3) • Program counter indirect with displacement (@PC + disp16) • Register indirect with base index (@RW0 + RW7, @RW1 + RW7) • Program counter relative branch address (rel) • Register list (rlst) • Accumulator indirect (@A) • Accumulator indirect branch address (@A) • Indirectly-specified branch address (@ear) • Indirectly-specified branch address (@eam) FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series ■ Effective Address Field Table B.2-1 lists the address formats specified by the effective address field. Table B.2-1 Effective Address Field Code Representation 00 R0 RW0 RL0 01 R1 RW1 (RL0) 02 R2 RW2 RL1 03 R3 RW3 (RL1) 04 R4 RW4 RL2 05 R5 RW5 (RL2) 06 R6 RW6 RL3 07 R7 RW7 (RL3) 08 @RW0 09 @RW1 Address format Default bank Register direct: Individual parts correspond to the byte, word, and long word types in order from the left. None DTB DTB Register indirect 0A @RW2 ADB 0B @RW3 SPB 0C @RW0+ DTB 0D @RW1+ DTB Register indirect with post increment 0E @RW2+ ADB 0F @RW3+ SPB 10 @RW0+disp8 DTB 11 @RW1+disp8 DTB Register indirect with 8-bit displacement 12 @RW2+disp8 ADB 13 @RW3+disp8 SPB 14 @RW4+disp8 DTB 15 @RW5+disp8 DTB Register indirect with 8-bit displacement 16 @RW6+disp8 ADB 17 @RW7+disp8 SPB 18 @RW0+disp16 DTB 19 @RW1+disp16 DTB Register indirect with 16-bit displacement CM44-10129-6E 1A @RW2+disp16 ADB 1B @RW3+disp16 SPB 1C @RW0+RW7 Register indirect with index DTB 1D @RW1+RW7 Register indirect with index DTB 1E @PC+disp16 PC indirect with 16-bit displacement PCB 1F addr16 Direct address DTB FUJITSU MICROELECTRONICS LIMITED 633 APPENDIX APPENDIX B Instructions B.3 MB90330A Series Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. ■ Direct Addressing ● Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of Immediate Addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.) Before execution A 2233 4455 After execution A 4455 1 2 1 2 (Some instructions transfer AL to AH.) ● Register direct addressing Specify a register explicitly as an operand. Table B.3-1 lists the registers that can be specified. Figure B.3-2 shows an example of register direct addressing. Table B.3-1 Direct Addressing Registers General-purpose register Special-purpose register Byte R0, R1, R2, R3, R4, R5, R6, R7 Word RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 Long word RL0, RL1, RL2, RL3 Accumulator A, AL Pointer SP * Bank PCB, DTB, USB, SSB, ADB Page DPR Control PS, CCR, RP, ILM *: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on the value of the S flag bit in the condition code register (CCR). For branch instructions, the program counter (PC) is not specified in an instruction operand but is specified implicitly. 634 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series Figure B.3-2 Example of Register Direct Addressing MOV R0, A (This instruction transfers the eight low-order bits of A to the generalpurpose register R0.) Before execution A 0716 2534 Memory space R0 After execution A 0716 2564 ?? Memory space R0 34 ● Direct branch addressing (addr16) Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which indicates the branch destination in the logical address space. Direct branch addressing is used for an unconditional branch, subroutine call, or software interrupt instruction. Bit23 to bit16 of the address are specified by the program counter bank register (PCB). Figure B.3-3 Example of Direct Branch Addressing (addr16) JMP 3B20H (This instruction causes an unconditional branch by direct branch addressing in a bank.) Before execution After execution CM44-10129-6E PC 3 C 2 0 PC 3 B 2 0 PCB 4 F PCB 4 F Memory space 4F3B20H Next instruction 4F3C20H 62 4F3C21H 20 4F3C22H 3B FUJITSU MICROELECTRONICS LIMITED JMP 3B20H 635 APPENDIX APPENDIX B Instructions MB90330A Series ● Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction. Figure B.3-4 Example of Direct Branch Addressing (addr24) JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit addressing.) Before execution After execution PC 3 C 2 0 PC 3 B 2 0 PCB 4 F PCB 3 3 Memory space 333B20H Next instruction 4F3C20H 63 4F3C21H 20 4F3C22H 3B 4F3C23H 33 JMPP 333B20H ● I/O direct addressing (io) Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB) and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an instruction using I/O direct addressing. Figure B.3-5 Example of I/O Direct Addressing (io) MOVW A, I:0C0H (This instruction reads data by I/O direct addressing and stores it in A.) Before execution After execution A 0716 2534 Memory space 0000C0H EE 0000C1H FF A 2534 FFEE Note : "I:" is Addressing Specifier that shows the I/O Direct Addressing. 636 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series ● Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB). Figure B.3-6 Example of Abbreviated Direct Addressing (dir) MOV S:20H, A (This instruction writes the contents of the eight low-order bits of A in abbreviated direct addressing mode.) Before execution A 4455 DPR 6 6 After execution A 4455 DPR 6 6 1212 DTB 7 7 Memory space 776620H 1212 DTB 7 7 ?? Memory space 776620H 12 Note : "S:" is Addressing Specifier that shows the Abbreviated Direct Addressing. ● Direct addressing (addr16) Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for this mode of addressing. Figure B.3-7 Example of Direct Addressing (addr16) MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.) Before execution After execution CM44-10129-6E A 2020 A AABB AABB 0123 DTB 5 5 Memory space 553B21H 01 553B20H 23 DTB 5 5 FUJITSU MICROELECTRONICS LIMITED 637 APPENDIX APPENDIX B Instructions MB90330A Series ● I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp) SETB I:0C1H:0 (This instruction sets bits by I/O direct bit addressing.) Memory space Before execution 00 0000C1H Memory space After execution 0000C1H 01 Note : "I:" is Addressing Specifier that shows the I/O Direct Addressing. ● Abbreviated direct bit addressing (dir:bp) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp) SETB S:10H:0 (This instruction sets bits by abbreviated direct bit addressing.) Memory space Before execution DTB 5 5 DPR 6 6 556610H 00 Memory space After execution DTB 5 5 DPR 6 6 01 556610H Note : "S:" is Addressing Specifier that shows the Abbreviated Direct Addressing. ● Direct bit addressing (addr16:bp) Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-10 Example of Direct Bit Addressing (addr16:bp) SETB 2222H : 0 (This instruction sets bits by direct bit addressing.) Memory space Before execution DTB 5 5 552222H 00 Memory space After execution 638 DTB 5 5 552222H FUJITSU MICROELECTRONICS LIMITED 01 CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series ● Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction. Figure B.3-11 Example of Vector Addressing (#vct) CALLV #15 (This instruction causes a branch to the address indicated by the interrupt vector specified in an operand.) Before execution PC 0 0 0 0 Memory space PCB F F After execution FFC000H EF FFFFE0H 00 FFFFE1H D0 CALLV #15 PC D 0 0 0 PCB F F Table B.3-2 CALLV Vector List Instruction Vector address L Vector address H CALLV #0 XXFFFEH XXFFFFH CALLV #1 XXFFFCH XXFFFDH CALLV #2 XXFFFAH XXFFFBH CALLV #3 XXFFF8H XXFFF9H CALLV #4 XXFFF6H XXFFF7H CALLV #5 XXFFF4H XXFFF5H CALLV #6 XXFFF2H XXFFF3H CALLV #7 XXFFF0H XXFFF1H CALLV #8 XXFFEEH XXFFEFH CALLV #9 XXFFECH XXFFEDH CALLV #10 XXFFEAH XXFFEBH CALLV #11 XXFFE8H XXFFE9H CALLV #12 XXFFE6H XXFFE7H CALLV #13 XXFFE4H XXFFE5H CALLV #14 XXFFE2H XXFFE3H CALLV #15 XXFFE0H XXFFE1H Note: A PCB register value is set in XX. Note: When the program counter bank register (PCB) is FFH, the vector area overlaps the vector area of INT #vct8 (#0 to #7). Use vector addressing carefully (see Table B.3-2). CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 639 APPENDIX APPENDIX B Instructions B.4 MB90330A Series Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. ■ Indirect Addressing ● Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used. Figure B.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3) MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores it in A.) Before execution A 0716 2534 Memory space RW1 D 3 0 F After execution DTB 7 8 78D30FH EE 78D310H FF A 2534 FFEE RW1 D 3 0 F DTB 7 8 ● Register indirect addressing with post increment (@RWj+ j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. After operand operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word). Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used. If the post increment results in the address of the register that specifies the increment, the incremented value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to writing by an instruction and, therefore, the register that would be incremented becomes write data. 640 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3) MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post increment and stores it in A.) Before execution A 0716 2534 Memory space RW1 D 3 0 F After execution DTB 7 8 78D30FH EE 78D310H FF A 2534 FFEE RW1 D 3 1 1 DTB 7 8 ● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) Memory is accessed using the address obtained by adding an offset to the contents of general-purpose register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is used, or additional data bank register (ADB) when RW2 or RW6 is used. Figure B.4-3 Example of Register Indirect Addressing with Offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with an offset and stores it in A.) Before execution A 0716 2534 (+10H) RW1 D 3 0 F After execution 78D31FH EE 78D320H FF A 2534 FFEE RW1 D 3 0 F CM44-10129-6E DTB 7 8 Memory space DTB 7 8 FUJITSU MICROELECTRONICS LIMITED 641 APPENDIX APPENDIX B Instructions MB90330A Series ● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3) Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value. Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3) MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with an offset and stores it in A.) Before execution A 0716 2534 (+25H) RL2 F 3 8 2 After execution 4B02 Memory space 824B27H EE 824B28H FF A 2534 FFEE RL2 F 3 8 2 4B02 ● Program counter indirect addressing with offset (@PC + disp16) Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one word long. Address bits 16 to 23 are specified by the program counter bank register (PCB). Note that the operand address of each of the following instructions is not deemed to be (next instruction address + disp16): • DBNZ eam, rel • DWBNZ eam, rel • CBNE eam, #imm8, rel • CWBNE eam, #imm16, rel • MOV eam, #imm8 • MOVW eam, #imm16 Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16) MOVW A, @PC+20H (This instruction reads data by program counter indirect addressing with an offset and stores it in A.) Before execution A 0716 2534 Memory space PCB C 5 PC 4 5 5 6 After execution A 2534 FFEE PCB C 5 PC 4 5 5 A 642 +4 C54556H 73 C54557H 9E C54558H 20 C54559H 00 MOVW A, @PC+20H C5455AH . . . +20H C5457AH EE C5457BH FF FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series ● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7) Memory is accessed using the address determined by adding RW0 or RW1 to the contents of generalpurpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB). Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7) MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with a base index and stores it in A.) Before execution A 0716 RW1 D 3 0 F WR7 0 1 0 1 After execution A 2534 RW1 D 3 0 F 2534 + DTB 7 8 Memory space 78D410H EE 78D411H FF FFEE DTB 7 8 WR7 0 1 0 1 CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 643 APPENDIX APPENDIX B Instructions MB90330A Series ● Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to 23 are indicated by the program counter bank register (PCB). Figure B.4-7 Example of Program Counter Relative Branch Addressing (rel) BRA 3C32H (This instruction causes an unconditional relative branch.) Before execution After execution PC 3 C 2 0 PC 3 C 3 2 PCB 4 F PCB 4 F Memory space 4F3C32H Next instruction 4F3C21H 10 4F3C20H 60 BRA 3C32H ● Register list (rlst) Specify a register to be pushed onto or popped from a stack. Figure B.4-8 Configuration of the Register List MSB LSB RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0 A register is selected when the corresponding bit is 1 and deselected when the bit is 0. 644 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series Figure B.4-9 Example of Register List (rlst) POPW RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.) SP 34FA SP 34FE RW0 ×× ×× RW0 02 01 RW1 ×× ×× RW1 ×× ×× RW2 ×× ×× RW2 ×× ×× RW3 ×× ×× RW3 ×× ×× RW4 ×× ×× RW4 04 03 RW5 ×× ×× RW5 ×× ×× RW6 ×× ×× RW6 ×× ×× RW7 ×× ×× RW7 ×× ×× Memory space SP Memory space 01 34FAH 01 34FAH 02 34FBH 02 34FBH 03 34FCH 03 34FCH 04 34FDH 04 34FDH 34FEH SP Before execution 34FEH After execution ● Accumulator indirect addressing (@A) Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB). Figure B.4-10 Example of Accumulator Indirect Addressing (@A) MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.) Before execution A 0716 2534 DTB B B After execution A 0716 Memory space BB2534H EE BB2535H FF FFEE DTB B B CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 645 APPENDIX APPENDIX B Instructions MB90330A Series ● Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program counter bank register (PCB). For the Jump Context (JCTX) instruction, however, address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for unconditional branch instructions. Figure B.4-11 Example of Accumulator Indirect Branch Addressing (@A) JMP @A (This instruction causes an unconditional branch by accumulator indirect branch addressing.) Before execution PC 3 C 2 0 A 6677 After execution PC 3 B 2 0 A 6677 PCB 4 F 3B20 Memory space 4F3B20H Next instruction 4F3C20H 61 JMP @A PCB 4 F 3B20 ● Indirect specification branch addressing (@ear) The address of the branch destination is the word data at the address indicated by ear. Figure B.4-12 Example of Indirect Specification Branch Addressing (@ear) JMP @@RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution After execution 646 PC 3 C 2 0 PCB 4 F RW0 7 F 4 8 DTB 2 1 PC 3 B 2 0 PCB 4 F RW0 7 F 4 8 DTB 2 1 Memory space 217F48H 20 217F49H 3B 4F3B20H Next instruction 4F3C20H 73 4F3C21H 08 FUJITSU MICROELECTRONICS LIMITED JMP @@RW0 CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series ● Indirect specification branch addressing (@eam) The address of the branch destination is the word data at the address indicated by eam. Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam) JMP @RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution PC 3 C 2 0 PCB 4 F RW0 3 B 2 0 After execution PC 3 B 2 0 PCB 4 F Memory space 4F3B20H Next instruction 4F3C20H 73 4F3C21H 00 JMP @RW0 RW0 3 B 2 0 CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 647 APPENDIX APPENDIX B Instructions B.5 MB90330A Series Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. ■ Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments. Therefore, intervening in data access increases the execution cycle count. Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the program fetches every byte of an instruction being executed. Therefore, intervening in data access increases the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register, internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register. Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add the "access count x cycle count for the halt" as a correction value to the normal execution count. 648 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series ■ Calculating the Execution Cycle Count Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data. Table B.5-1 Execution Cycle Counts in Each Addressing Mode (a) * Code Operand 00 | 07 Ri Rwi RLi 08 | 0B Execution cycle count in each addressing mode Register access count in each addressing mode See the instruction list. See the instruction list. @RWj 2 1 0C | 0F @RWj+ 4 2 10 | 17 @RWi+disp8 2 1 18 | 1B @RWi+disp16 2 1 1C 1D 1E 1F @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 4 4 2 1 2 2 0 0 *: (a) is used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List". CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 649 APPENDIX APPENDIX B Instructions MB90330A Series Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles (b) byte * Operand (c) word * (d) long * Cycle count Access count Cycle count Access count Cycle count Access count Internal register +0 1 +0 1 +0 2 Internal memory Even address +0 1 +0 1 +0 2 Internal memory Odd address +0 1 +2 2 +4 4 External data bus 16-bit even address +1 1 +1 1 +2 2 External data bus 16-bit odd address +1 1 +4 2 +8 4 External data bus 8-bits +1 1 +4 2 +8 4 *: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List". Note: When an external data bus is used, the cycle counts during which an instruction is made to wait by ready input or automatic ready must also be added. Table B.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles Instruction Byte boundary Word boundary Internal memory - +2 External data bus 16-bits - +3 External data bus 8-bits +3 - Notes: • When an external data bus is used, the cycle counts during which an instruction is made to wait by ready input or automatic ready must also be added. • Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the correction values to calculate the worst case. 650 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series B.6 Effective address field Table B.6-1 shows the effective address field. ■ Effective Address Field Table B.6-1 Effective Address Field Code Representation 00 01 02 03 04 05 06 07 08 09 0A R0 R1 R2 R3 R4 R5 R6 R7 @RW0 @RW1 @RW2 RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 0B 0C 0D 0E 0F 10 11 12 13 14 15 @RW3 @RW0+ @RW1+ @RW2+ @RW3+ @RW0+disp8 @RW1+disp8 @RW2+disp8 @RW3+disp8 @RW4+disp8 @RW5+disp8 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Address format Byte count of extended address part * Register direct: Individual parts correspond to the byte, word, and long word types in order from the left. - Register indirect 0 Register indirect with post increment 0 Register indirect with 8-bit displacement 1 16 @RW6+disp8 17 @RW7+disp8 18 @RW0+disp16 19 @RW1+disp16 Register indirect with 16-bit displacement 2 1A @RW2+disp16 1B @RW3+disp16 1C @RW0+RW7 Register indirect with index 0 1D @RW1+RW7 Register indirect with index 0 1E @PC+disp16 PC indirect with 16-bit displacement 2 1F addr16 Direct address 2 *1: Each byte count of the extended address part applies to + in the # (byte count) column in "B.8 F2MC-16LX Instruction List". CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 651 APPENDIX APPENDIX B Instructions B.7 MB90330A Series How to Read the Instruction List Table B.7-1 describes the items used in "B.8 F2MC-16LX Instruction List", and Table B.7-2 describes the symbols used in the same list. ■ Description of Instruction Presentation Items and Symbols Table B.7-1 Description of Items in the Instruction List (1/2) Item Mnemonic Uppercase, symbol: Represented as is in the assembler. Lowercase: Rewritten in the assembler. Number of following lowercase: Indicates bit length in the instruction. # Indicates the number of bytes. ~ Indicates the number of cycles. See Table B.2-1 for the alphabetical letters in items. RG B Operation 652 Description Indicates the number of times a register access is performed during instruction execution. The number is used to calculate the correction value for CPU intermittent operation. Indicates the correction value used to calculate the actual number of cycles during instruction execution. The actual number of cycles during instruction execution can be determined by adding the value in the ~ column to this value. Indicates the instruction operation. LH Indicates the special operation for bit15 to bit08 of the accumulator. Z: Transfers 0. X: Transfers after sign extension. -: No transfer AH Indicates the special operation for the 16 high-order bits of the accumulator. *: Transfers from AL to AH. -: No transfer Z: Transfers 00 to AH. X: Transfers 00H or FFH to AH after AL sign extension. FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series Table B.7-1 Description of Items in the Instruction List (1/2) Item Description I Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), C (carry). *: Changes upon instruction execution. -: No change S: Set upon instruction execution. R: Reset upon instruction execution. S T N Z V C RMW Indicates whether the instruction is a Read Modify Write instruction (reading data from memory by the I instruction and writing the result to memory). *: Read Modify Write instruction -: Not Read Modify Write instruction Note: Cannot be used for an address that has different meanings between read and write operations. Table B.7-2 Explanation on Symbols in the Instruction List (1/2) Symbol A CM44-10129-6E Explanation The bit length used varies depending on the 32-bit accumulator instruction. Byte: Low-order 8 bits of byte AL Word: 16 bits of word AL Long word: 32 bits of AL and AH AH 16 high-order bits of A AL 16 low-order bits of A SP Stack pointer (USP or SSP) PC Program counter PCB program counter bank register DTB Data bank register ADB Additional data bank register SSB System stack bank register USB User stack bank register SPB Current stack bank register (SSB or USB) DPR Direct page register brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB brg2 DTB, ADB, SSB, USB, DPR, SPB FUJITSU MICROELECTRONICS LIMITED 653 APPENDIX APPENDIX B Instructions MB90330A Series Table B.7-2 Explanation on Symbols in the Instruction List (1/2) Symbol Ri R0, R1, R2, R3, R4, R5, R6, R7 RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RWj RW0, RW1, RW2, RW3 RLi RL0, RL1, RL2, RL3 dir Abbreviated direct addressing addr16 Direct addressing addr24 Physical direct addressing ad24 0-15 Bit0 to bit15 of addr24 ad24 16-23 Bit16 to bit23 of addr24 io I/O area (000000H to 0000FFH) #imm4 4-bit immediate data #imm8 8-bit immediate data #imm16 16-bit immediate data #imm32 32-bit immediate data ext (imm8) 16-bit data obtained by sign extension of 8-bit immediate data disp8 8-bit displacement disp16 16-bit displacement bp 654 Explanation Bit offset vct4 Vector number (0 to 15) vct8 Vector number (0 to 255) ( )b Bit address rel PC relative branch ear Effective addressing (code 00H to 07H) eam Effective addressing (code 08H to 1FH) rlst Register list FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series B.8 F2MC-16LX Instruction List Table B.8-1 to Table B.8-18 list the instructions used by the F2MC-16LX. ■ F2MC-16LX Instruction List Table B.8-1 41 Transfer Instructions (Byte) Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV XCH XCH XCH XCH A,dir A,addr16 A,Ri A,ear A,eam A,io A,#imm8 A,@A A,@RLi+disp8 A,#imm4 A,dir A,addr16 A,Ri A,ear A,eam A,io A,#imm8 A,@A A,@RWi+disp8 A,@RLi+disp8 dir,A addr16,A Ri,A ear,A eam,A io,A @RLi+disp8,A Ri,ear Ri,eam ear,Ri eam,Ri Ri,#imm8 io,#imm8 dir,#imm8 ear,#imm8 eam,#imm8 @AL,AH A,ear A,eam Ri,ear Ri,eam # ~ RG B 2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ 3 4 2 2 3 + (a) 3 2 3 10 1 3 4 2 2 3 + (a) 3 2 3 5 10 3 4 2 2 3 + (a) 3 10 3 4 + (a) 4 5 + (a) 2 5 5 2 4 + (a) 3 4 5 + (a) 7 9 + (a) 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2 × (b) 0 2 × (b) Operation byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← imm8 byte (A) ← ((A)) byte (A) ← ((RLi)+disp8) byte (A) ← imm4 byte (A) ← (dir) byte (A) ← (addr16) byte (A) ← (Ri) byte (A) ← (ear) byte (A) ← (eam) byte (A) ← (io) byte (A) ← imm8 byte (A) ← ((A)) byte (A) ← ((RWi)+disp8) byte (A) ← ((RLi)+disp8) byte (dir) ← (A) byte (addr16) ← (A) byte (Ri) ← (A) byte (ear) ← (A) byte (eam) ← (A) byte (io) ← (A) byte ((RLi)+disp8) ← (A) byte (Ri) ← (ear) byte (Ri) ← (eam) byte (ear) ← (Ri) byte (eam) ← (Ri) byte (Ri) ← imm8 byte (io) ← imm8 byte (dir) ← imm8 byte (ear) ← imm8 byte (eam) ← imm8 byte ((A)) ← (AH) byte (A) ↔ (ear) byte (A) ↔ (eam) byte (Ri) ↔ (ear) byte (Ri) ↔ (eam) LH AH I S T N Z V C RMW Z Z Z Z Z Z Z Z Z Z X X X X X X X X X X Z Z - * * * * * * * * * * * * * * * * * * - - - - * * * * * * * * * R * * * * * * * * * * * * * * * * * * * * * * * * - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - Note: See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 655 APPENDIX APPENDIX B Instructions MB90330A Series Table B.8-2 38 Transfer Instructions (Word, Long Word) Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW XCHW XCHW XCHW XCHW MOVL MOVL MOVL MOVL MOVL A,dir A,addr16 A,SP A,RWi A,ear A,eam A,io A,@A A,#imm16 A,@RWi+disp8 A,@RLi+disp8 dir,A addr16,A SP,A RWi,A ear,A eam,A io,A @RWi+disp8,A @RLi+disp8,A RWi,ear RWi,eam ear,RWi eam,RWi RWi,#imm16 io,#imm16 ear,#imm16 eam,#imm16 @AL,AH A,ear A,eam RWi, ear RWi, eam A,ear A,eam A,#imm32 ear,A eam,A # ~ RG B 2 3 1 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 2 2+ 5 2 2+ 3 4 1 2 2 3 + (a) 3 3 2 5 10 3 4 1 2 2 3 + (a) 3 5 10 3 4 + (a) 4 5 + (a) 2 5 2 4 + (a) 3 4 5 + (a) 7 9 + (a) 4 5 + (a) 3 4 5 + (a) 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 2 0 0 2 0 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) 0 2 × (c) 0 2 × (c) 0 (d) 0 0 (d) Operation LH AH I S T N Z V C RMW - * * * * * * * * * * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - word (A) ← (dir) word (A) ← (addr16) word (A) ← (SP) word (A) ← (RWi) word (A) ← (ear) word (A) ← (eam) word (A) ← (io) word (A) ← ((A)) word (A) ← imm16 word (A) ← ((RWi)+disp8) word (A) ← ((RLi)+disp8) word (dir) ← (A) word (addr16) ← (A) word (SP) ← (A) word (RWi) ← (A) word (ear) ← (A) word (eam) ← (A) word (io) ← (A) word ((RWi)+disp8) ← (A) word ((RLi)+disp8) ← (A) word (RWi) ← (ear) word (RWi) ← (eam) word (ear) ← (RWi) word (eam) ← (RWi) word (RWi) ← imm16 word (io) ← imm16 word (ear) ← imm16 word (eam) ← imm16 word ((A)) ← (AH) word (A) ↔ (ear) word (A) ↔ (eam) word (RWi) ↔ (ear) word (RWi) ↔ (eam) long (A) ← (ear) long (A) ← (eam) long (A) ← imm32 long (ear) ← (A) long(eam) ← (A) Note: See Table B.5-1 and Table B.5-2 for information on (a), (c), and (d) in the table. 656 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word) Mnemonic # ~ RG B ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4 + (a) 3 5 + (a) 2 3 4 + (a) 3 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 × (b) 0 0 (b) 0 SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4 + (a) 3 5 + (a) 2 3 4 + (a) 3 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 × (b) 0 0 (b) 0 ADDW ADDW ADDW ADDW ADDW ADDW ADDCW ADDCW SUBW SUBW SUBW SUBW SUBW SUBW SUBCW SUBCW ADDL ADDL ADDL SUBL SUBL SUBL A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A,ear A,eam A,#imm32 A,ear A,eam A,#imm32 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 2+ 5 2 2+ 5 2 3 4+(a) 2 3 5+(a) 3 4+(a) 2 3 4+(a) 2 3 5+(a) 3 4+(a) 6 7+(a) 4 6 7+(a) 4 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0 0 0 (c) 0 0 2 × (c) 0 (c) 0 0 (c) 0 0 2 × (c) 0 (c) 0 (d) 0 0 (d) 0 Operation LH AH I S T N Z V C RMW Z Z Z Z Z Z Z Z Z - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - Z Z Z Z Z Z Z Z - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - byte (A) ← (A) + imm8 byte (A) ← (A) + (dir) byte (A) ← (A) + (ear) byte (A) ← (A) + (eam) byte (ear) ← (ear) + (A) byte (eam) ← (eam) + (A) byte (A) ← (AH) + (AL) + (C) byte (A) ← (A) + (ear)+ (C) byte (A) ← (A) + (eam)+ (C) byte (A) ← (AH) + (AL) + (C) (decimal) byte (A) ← (A) - imm8 byte (A) ← (A) - (dir) byte (A) ← (A) - (ear) byte (A) ← (A) - (eam) byte (ear) ← (ear) - (A) byte (eam) ← (eam) - (A) byte (A) ← (AH) - (AL) - (C) byte (A) ← (A) - (ear) - (C) byte (A) ← (A) - (eam) - (C) byte (A) ← (AH) - (AL) - (C) (decimal) word (A) ← (AH) + (AL) word (A) ← (A) + (ear) word (A) ← (A) + (eam) word (A) ← (A) + imm16 word (ear) ← (ear) + (A) word (eam) ← (eam) + (A) word (A) ← (A) + (ear) + (C) word (A) ← (A) + (eam) + (C) word (A) ← (AH) - (AL) word (A) ← (A) - (ear) word (A) ← (A) - (eam) word (A) ← (A) - imm16 word (ear) ← (ear) - (A) word (eam) ← (eam) - (A) word (A) ← (A) - (ear) - (C) word (A) ← (A) - (eam) - (C) long (A) ← (A) + (ear) long (A) ← (A) + (eam) long (A) ← (A) + imm32 long (A) ← (A) - (ear) long (A) ← (A) - (eam) long (A) ← (A) - imm32 Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 657 APPENDIX APPENDIX B Instructions MB90330A Series Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word) Mnemonic # ~ RG B INC ear 2 3 2 0 INC eam 2+ 5+(a) 0 2 × (b) Operation LH AH I S T N Z V C RMW byte (ear) ← (ear) + 1 - - - - - * * * - - byte (eam) ← (eam) + 1 - - - - - * * * - * DEC ear 2 3 2 0 byte (ear) ← (ear) - 1 - - - - - * * * - - DEC eam 2+ 5+(a) 0 2 × (b) byte (eam) ← (eam) - 1 - - - - - * * * - * INCW ear 2 3 2 0 word (ear) ← (ear) + 1 - - - - - * * * - - INCW eam 2+ 5+(a) 0 2 × (c) word (eam) ← (eam) + 1 - - - - - * * * - * DECW ear 2 3 2 0 DECW eam 2+ 5+(a) 0 2 × (c) INCL ear 2 7 4 0 INCL eam 2+ 9+(a) 0 2 × (d) DECL ear 2 7 4 0 DECL eam 2+ 9+(a) 0 2 × (d) word (ear) ← (ear) - 1 - - - - - * * * - - word (eam) ← (eam) - 1 - - - - - * * * - * long (ear) ← (ear) + 1 - - - - - * * * - - long (eam) ← (eam) + 1 - - - - - * * * - * long (ear) ← (ear) - 1 - - - - - * * * - - long (eam) ← (eam) - 1 - - - - - * * * - * Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. Table B.8-5 11 Compare Instructions (Byte, Word, Long Word) # ~ RG B LH AH I S T N Z V C RMW CMP Mnemonic A 1 1 0 0 byte (AH) - (AL) Operation - - - - - * * * * - CMP A,ear 2 2 1 0 byte (A) - (ear) - - - - - * * * * - CMP A,eam 2+ 3+(a) 0 (b) byte (A) - (eam) - - - - - * * * * - CMP A,#imm8 2 2 0 0 byte (A) - imm8 - - - - - * * * * - CMPW A 1 1 0 0 word (AH) - (AL) - - - - - * * * * - CMPW A,ear 2 2 1 0 word (A) - (ear) - - - - - * * * * - CMPW A,eam 2+ 3+(a) 0 (c) word (A) - (eam) - - - - - * * * * - CMPW A,#imm16 3 2 0 0 word (A) - imm16 - - - - - * * * * - CMPL A,ear 2 6 2 0 long (A) - (ear) - - - - - * * * * - CMPL A,eam 2+ 7+(a) 0 (d) long (A) - (eam) - - - - - * * * * - CMPL A,#imm32 5 3 0 0 long (A) - imm32 - - - - - * * * * - Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 658 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word) Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW DIVU A 1 *1 0 0 word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) - - - - - - - * * - DIVU A,ear 2 *2 1 0 word (A) / byte (ear) quotient → byte (A) remainder → byte (ear) - - - - - - - * * - DIVU A,eam 2+ *3 0 *6 word (A) / byte (eam) quotient → byte (A) remainder → byte (eam) - - - - - - - * * - DIVUW A,ear 2 *4 1 0 long (A) / word (ear) quotient → word (A) remainder → word (ear) - - - - - - - * * - DIVUW A,eam 2+ *5 0 *7 long (A) / word (eam) quotient → word (A) remainder → word (eam) - - - - - - - * * - MULU A 1 *8 0 0 byte (AH) * byte (AL) → word (A) - - - - - - - - - MULU A,ear 2 *9 1 0 byte (A) * byte (ear) → word (A) - - - - - - - - - - MULU A,eam 2+ *10 0 (b) byte (A) * byte (eam) → word (A) - - - - - - - - - - MULUW A 1 *11 0 0 word (AH) * word (AL) → Long (A) - - - - - - - - - MULUW A,ear 2 *12 1 0 word (A) * word (ear) → Long (A) - - - - - - - - - - MULUW A,eam 2+ *13 0 (c) word (A) * word (eam) → Long (A) - - - - - - - - - - *1: 3: Division by 0 7: Overflow 15: Normal *2: 4: Division by 0 8: Overflow 16: Normal *3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal *4: 4: Division by 0 7: Overflow 22: Normal *5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal *6: (b): Division by 0 or overflow 2 × (b): Normal *7: (c): Division by 0 or overflow 2 × (c): Normal *8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0. *9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0. *10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0. *11: 3: Word (AH) is 0. 11: Word (AH) is not 0. *12: 4: Word (ear) is 0. 12: Word (ear) is not 0. *13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0. Note: See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 659 APPENDIX APPENDIX B Instructions MB90330A Series Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word) Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW DIV A 2 *1 0 0 word (AH) / byte (AL) quotient → byte (AL) remainder → byte (AH) Z - - - - - - * * - DIV A,ear 2 *2 1 0 word (A) / byte (ear) quotient → byte (A) remainder → byte (ear) Z - - - - - - * * - DIV A,eam 2+ *3 0 *6 word (A) / byte (eam) quotient → byte (A) remainder → byte (eam) Z - - - - - - * * - DIVW A,ear 2 *4 1 0 long (A) / word (ear) quotient → word (A) remainder → word (ear) - - - - - - - * * - DIVW A,eam 2+ *5 0 *7 long (A) / word (eam) quotient → word (A) remainder → word (eam) - - - - - - - * * - MUL A 2 *8 0 0 byte (AH) * byte (AL) → word (A) - - - - - - - - - - MUL A,ear 2 *9 1 0 byte (A) * byte (ear) → word (A) - - - - - - - - - - byte (A) * byte (eam) → word (A) - - - - - - - - - - word (AH) * word (AL) → Long (A) - - - - - - - - - - 0 word (A) * word (ear) → Long (A) - - - - - - - - - - (c) word (A) * word (eam) → Long (A) - - - - - - - - - - MUL A,eam 2+ *10 0 (b) MULW A 2 *11 0 0 MULW A,ear 2 *12 1 MULW A,eam 2+ *13 0 *1: *2: *3: *4: 3: Division by 0, 8 or 18: Overflow, 18: Normal 4: Division by 0, 11 or 22: Overflow, 23: Normal 5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal *5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal *6: (b): Division by 0 or overflow, 2 × (b): Normal *7: (c): Division by 0 or overflow, 2 × (c): Normal *8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative *9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative *10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative *11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative *12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative *13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative Notes: • The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a pre-operation count or a post-operation count depending on the detection timing. • When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed. • See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table. 660 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series Table B.8-8 39 Logic 1 Instructions (Byte, Word) Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW - AND A,#imm8 2 2 0 0 byte (A) ← (A) and imm8 - - - - - * * R - AND A,ear 2 3 1 0 byte (A) ← (A) and (ear) - - - - - * * R - - AND A,eam 2+ 4+(a) 0 (b) byte (A) ← (A) and (eam) - - - - - * * R - - byte (ear) ← (ear) and (A) - - - - - * * R - - byte (eam) ← (eam) and (A) - - - - - * * R - * AND ear,A 2 3 2 0 AND eam,A 2+ 5+(a) 0 2 × (b) OR A,#imm8 2 2 0 0 byte (A) ← (A) or imm8 - - - - - * * R - - OR A,ear 2 3 1 0 byte (A) ← (A) or (ear) - - - - - * * R - - OR A,eam 2+ 4+(a) 0 (b) byte (A) ← (A) or (eam) - - - - - * * R - - OR ear,A 2 3 2 0 byte (ear) ← (ear) or (A) - - - - - * * R - - OR eam,A 2+ 5+(a) 0 2 × (b) byte (eam) ← (eam) or (A) - - - - - * * R - * XOR A,#imm8 2 2 0 0 byte (A) ← (A) xor imm8 - - - - - * * R - - XOR A,ear 2 3 1 0 byte (A) ← (A) xor (ear) - - - - - * * R - - XOR A,eam 2+ 4+(a) 0 (b) byte (A) ← (A) xor (eam) - - - - - * * R - - XOR ear,A 2 3 2 0 byte (ear) ← (ear) xor (A) - - - - - * * R - - XOR eam,A 2+ 5+(a) 0 2 × (b) byte (eam) ← (eam) xor (A) - - - - - * * R - * NOT A 1 2 0 0 byte (A) ← not (A) - - - - - * * R - - NOT ear 2 3 2 0 byte (ear) ← not (ear) - - - - - * * R - - NOT eam 2+ 5+(a) 0 2 × (b) byte (eam) ← not (eam) - - - - - * * R - * ANDW A 1 2 0 0 word (A) ← (AH) and (A) - - - - - * * R - - ANDW A,#imm16 3 2 0 0 word (A) ← (A) and imm16 - - - - - * * R - - ANDW A,ear 2 3 1 0 word (A) ← (A) and (ear) - - - - - * * R - - ANDW A,eam 2+ 4+(a) 0 (c) word (A) ← (A) and (eam) - - - - - * * R - - word (ear) ← (ear) and (A) - - - - - * * R - - word (eam) ← (eam) and (A) - - - - - * * R - * 0 word (A) ← (AH) or (A) - - - - - * * R - - 0 word (A) ← (A) or imm16 - - - - - * * R - - 1 0 word (A) ← (A) or (ear) - - - - - * * R - - 4+(a) 0 (c) word (A) ← (A) or (eam) - - - - - * * R - - 2 3 2 0 word (ear) ← (ear) or (A) - - - - - * * R - - eam,A 2+ 5+(a) 0 2 × (c) word (eam) ← (eam) or (A) - - - - - * * R - * XORW A 1 2 0 0 word (A) ← (AH) xor (A) - - - - - * * R - - XORW A,#imm16 3 2 0 0 word (A) ← (A) xor imm16 - - - - - * * R - - XORW A,ear 2 3 1 0 word (A) ← (A) xor (ear) - - - - - * * R - - ANDW ear,A 2 3 2 0 ANDW eam,A 2+ 5+(a) 0 2 × (c) ORW A 1 2 0 ORW A,#imm16 3 2 0 ORW A,ear 2 3 ORW A,eam 2+ ORW ear,A ORW XORW A,eam 2+ 4+(a) 0 (c) word (A) ← (A) xor (eam) - - - - - * * R - XORW ear,A 2 3 2 0 word (ear) ← (ear) xor (A) - - - - - * * R - - XORW eam,A 2+ 5+(a) 0 2 × (c) word (eam) ← (eam) xor (A) - - - - - * * R - * NOTW A 1 2 0 0 word (A) ← not (A) - - - - - * * R - - NOTW ear 2 3 2 0 word (ear) ← not (ear) - - - - - * * R - - NOTW eam 2+ 5+(a) 0 2 × (c) word (eam) ← not (eam) - - - - - * * R - * Note: See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 661 APPENDIX APPENDIX B Instructions MB90330A Series Table B.8-9 6 Logic 2 Instructions (Long Word) Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW ANDL A,ear 2 6 2 0 long (A) ← (A) and (ear) - - - - - * * R - - ANDL A,eam 2+ 7+(a) 0 (d) long (A) ← (A) and (eam) - - - - - * * R - - ORL A,ear 2 6 2 0 long (A) ← (A) or (ear) - - - - - * * R - - ORL A,eam 2+ 7+(a) 0 (d) long (A) ← (A) or (eam) - - - - - * * R - - XORL A,ear 2 6 2 0 long (A) ← (A) xor (ear) - - - - - * * R - - XORL A,eam 2+ 7+(a) 0 (d) long (A) ← (A) xor (eam) - - - - - * * R - - Note: See Table B.5-1 and Table B.5-2 for information on (a) and (d) in the table. Table B.8-10 6 Sign Inversion Instructions (Byte, Word) Mnemonic NEG A # ~ RG B 1 2 0 0 byte (A) ← 0 - (A) byte (ear) ← 0 - (ear) - - - - - * * * * - byte (eam) ← 0 - (eam) - - - - - * * * * * word (A) ← 0 - (A) - - - - - * * * * - NEG ear 2 3 2 0 NEG eam 2+ 5+(a) 0 2 × (b) NEGW A 1 2 0 0 NEGW ear 2 3 2 0 NEGW eam 2+ 5+(a) 0 2 × (c) Operation LH AH I S T N Z V C RMW X - - - - * * * * - word (ear) ← 0 - (ear) - - - - - * * * * - word (eam) ← 0 - (eam) - - - - - * * * * * Note: See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table. Table B.8-11 1 Normalization Instruction (Long Word) Mnemonic NRML A,R0 # ~ RG B 2 *1 1 0 Operation LH AH I S T N Z V C RMW - - - - - - * - - - long (A) ← Shift left to the position where '1' is set for the first time. byte (R0) ← Shift count at that time *1: 4 when all accumulators have a value of 0; otherwise, 6+(R0) 662 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series Table B.8-12 18 Shift Instructions (Byte, Word, Long Word) Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW RORC A 2 2 0 0 byte (A) ← Right rotation with carry - - - - - * * - * - ROLC A 2 2 0 0 byte (A) ← Right rotation with carry - - - - - * * - * - RORC ear 2 3 2 0 byte (ear) ← Right rotation with carry - - - - - * * - * - RORC eam 2+ 5+(a) 0 2 × (b) byte (eam) ← Right rotation with carry - - - - - * * - * * ROLC ear 2 3 2 0 byte (ear) ← Left rotation with carry - - - - - * * - * - ROLC eam 2+ 5+(a) 0 2 × (b) byte (eam) ← Left rotation with carry - - - - - * * - * * ASR A,R0 2 *1 1 0 byte (A) ← Arithmetic right shift (A, 1 bit) - - - - * * * - * - LSR A,R0 2 *1 1 0 byte (A) ← Logical right barrel shift (A, R0) - - - - * * * - * - LSL A,R0 2 *1 1 0 byte (A) ← Logical left barrel shift (A, R0) - - - - - * * - * - ASRW A 1 2 0 0 word (A) ← Arithmetic right shift (A, 1 bit) - - - - * * * - * - LSRW A/SHRW A 1 2 0 0 word (A) ← Logical right shift (A, 1 bit) - - - - * R * - * - LSLW A/SHLW A 1 2 0 0 word (A) ← Logical left shift (A, 1 bit) - - - - - * * - * - ASRW A,R0 2 *1 1 0 word (A) ← Arithmetic right barrel shift (A, R0) - - - - * * * - * - LSRW A,R0 2 *1 1 0 word (A) ← Logical right barrel shift (A, R0) - - - - * * * - * - LSLW A,R0 2 *1 1 0 word (A) ← Logical left barrel shift (A, R0) - - - - - * * - * - ASRL A,R0 2 *2 1 0 long (A) ← Arithmetic right barrel shift (A, R0) - - - - * * * - * - LSRL A,R0 2 *2 1 0 long (A) ← Logical right barrel shift (A, R0) - - - - * * * - * - LSLL A,R0 2 *2 1 0 long (A) ← Logical left barrel shift (A, R0) - - - - - * * - * - *1: 6 when R0 is 0; otherwise, 5 + (R0) *2: 6 when R0 is 0; otherwise, 6 + (R0) Note: See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 663 APPENDIX APPENDIX B Instructions MB90330A Series Table B.8-13 31 Branch 1 Instructions Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW BZ/BEQ rel 2 *1 0 0 Branch on (Z) = 1 - - - - - - - - - - BNZ/ BNE rel 2 *1 0 0 Branch on (Z) = 0 - - - - - - - - - - BC/BLO rel 2 *1 0 0 Branch on (C) = 1 - - - - - - - - - - BNC/ BHS rel 2 *1 0 0 Branch on (C) = 0 - - - - - - - - - - BN rel 2 *1 0 0 Branch on (N) = 1 - - - - - - - - - - BP rel 2 *1 0 0 Branch on (N) = 0 - - - - - - - - - - BV rel 2 *1 0 0 Branch on (V) = 1 - - - - - - - - - - BNV rel 2 *1 0 0 Branch on (V) = 0 - - - - - - - - - - BT rel 2 *1 0 0 Branch on (T) = 1 - - - - - - - - - - BNT rel 2 *1 0 0 Branch on (T) = 0 - - - - - - - - - - BLT rel 2 *1 0 0 Branch on (V) xor (N) = 1 - - - - - - - - - - BGE rel 2 *1 0 0 Branch on (V) xor (N) = 0 - - - - - - - - - - BLE rel 2 *1 0 0 Branch on ((V) xor (N)) or (Z) = 1 - - - - - - - - - - BGT rel 2 *1 0 0 Branch on ((V) xor (N)) or (Z) = 0 - - - - - - - - - - BLS rel 2 *1 0 0 Branch on (C) or (Z) = 1 - - - - - - - - - - BHI rel 2 *1 0 0 Branch on (C) or (Z) = 0 - - - - - - - - - - BRA rel 2 *1 0 0 Unconditional branch - - - - - - - - - - JMP @A 1 2 0 0 word (PC) ← (A) - - - - - - - - - - JMP addr16 3 3 0 0 word (PC) ← addr16 - - - - - - - - - - JMP @ear 2 3 1 0 word (PC) ← (ear) - - - - - - - - - JMP @eam 2+ 4+(a) 0 (c) word (PC) ← (eam) - - - - - - - - - - JMPP @ear *3 2 5 2 0 word (PC) ← (ear), (PCB) ← (ear+2) - - - - - - - - - - JMPP @eam *3 2+ 6+(a) 0 (d) JMPP addr24 4 4 0 0 word (PC) ← (eam), (PCB) ← (eam+2) - - - - - - - - - - word (PC) ← ad24 0-15, (PCB) ← ad24 16-23 - - - - - - - - - - CALL @ear *4 2 6 1 (c) word (PC) ← (ear) - - - - - - - - - - CALL @eam *4 2+ 7+(a) 0 2 × (c) word (PC) ← (eam) - - - - - - - - - - CALL addr16 *5 3 6 0 (c) word (PC) ← addr16 - - - - - - - - - - CALLV #vct4 *5 1 7 0 2 × (c) Vector call instruction - - - - - - - - - - CALLP @ear *6 2 10 2 2 × (c) word (PC) ← (ear), (PCB) ← (ear+2) - - - - - - - - - - CALLP @eam *6 2+ 11+(a) 0 *2 CALLP addr24 *7 4 10 0 2 × (c) word (PC) ← (eam), (PCB) ← (eam+2) - - - - - - - - - - word (PC) ← ad24 0-15, (PCB) ← ad24 16-23 - - - - - - - - - - *1: 4 when a branch is made; otherwise, 3 *2: 3 × (c) + (b) *3: Read (word) of branch destination address *4: W: Save to stack (word) R: Read (word) of branch destination address *5: Save to stack (word) *6: W: Save to stack (long word), R: Read (long word) of branch destination address *7: Save to stack (long word) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. 664 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series Table B.8-14 19 Branch 2 Instructions Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW CBNE A,#imm8,rel 3 *1 0 0 Branch on byte (A) not equal to imm8 - - - - - * * * * - CWBNE A,#imm16,rel 4 *1 0 0 Branch on word (A) not equal to imm16 - - - - - * * * * - CBNE ear,#imm8,rel 4 *2 1 0 Branch on byte (ear) not equal to imm8 - - - - - * * * * - CBNE eam,#imm8,rel *9 4+ *3 0 (b) Branch on byte (eam) not equal to imm8 - - - - - * * * * - CWBNE ear,#imm16,rel 5 *4 1 0 Branch on word (ear) not equal to imm16 - - - - - * * * * - CWBNE eam,#imm16,rel*9 5+ *3 0 (c) Branch on word (eam) not equal to imm16 - - - - - * * * * - DBNZ ear,rel 3 *5 2 0 byte (ear) ← (ear) - 1, Branch on (ear) not equal to 0 - - - - - * * * - * DBNZ eam,rel 3+ *6 2 DWBNZ ear,rel 3 *5 2 DWBNZ eam,rel 3+ *6 2 2 × (b) byte (eam) ← (eam) - 1, Branch on (eam) not equal to 0 - - - - - * * * - - - - - - * * * - - 2 × (c) word (eam) ← (eam) - 1, Branch on (eam) not equal to 0 - - - - - * * * - * 0 word (ear) ← (ear) - 1, Branch on (ear) not equal to 0 INT #vct8 2 20 0 8 × (c) Software interrupt - - R S - - - - - - INT addr16 3 16 0 6 × (c) Software interrupt - - R S - - - - - - INTP addr24 4 17 0 6 × (c) Software interrupt - - R S - - - - - - 1 20 0 8 × (c) Software interrupt - - R S - - - - - - INT9 RETI LINK #imm8 UNLINK 1 *8 0 *7 Return from interrupt - - * * * * * * * - 2 6 0 (c) Saves the old frame pointer in the stack upon entering the function, then sets the new frame pointer and reserves the local pointer area. - - - - - - - - - - 1 5 0 (c) Recovers the old frame pointer from the stack upon exiting the function. - - - - - - - - - - RET *10 1 4 0 (c) Return from subroutine - - - - - - - - - - RETP *11 1 6 0 (d) Return from subroutine - - - - - - - - - - *1: 5 when a branch is made; otherwise, 4 *2: 13 when a branch is made; otherwise, 12 *3: 7+(a) when a branch is made; otherwise, 6+(a) *4: 8 when a branch is made; otherwise, 7 *5: 7 when a branch is made; otherwise, 6 *6: 8+(a) when a branch is made; otherwise, 7+(a) *7: 3 × (b) + 2 × (c) when jumping to the next interruption request; 6 × (c) when returning from the current interruption *8: 15 when jumping to the next interruption request; 17 when returning from the current interruption *9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction. *10: Return from stack (word) *11: Return from stack (long word) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 665 APPENDIX APPENDIX B Instructions MB90330A Series Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word) Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW PUSHW A 1 4 0 (c) word (SP) ← (SP) - 2, ((SP)) ← (A) - - - - - - - - - - PUSHW AH 1 4 0 (c) word (SP) ← (SP) - 2, ((SP)) ← (AH) - - - - - - - - - - PUSHW PS 1 4 0 (c) word (SP) ← (SP) - 2, ((SP)) ← (PS) - - - - - - - - - - PUSHW rlst 2 *3 *5 *4 (SP) ← (SP) - 2n, ((SP)) ← (rlst) - - - - - - - - - - POPW A 1 3 0 (c) word (A) ← ((SP)), (SP) ← (SP) + 2 - * - - - - - - - - POPW AH 1 3 0 (c) word (AH) ← ((SP)), (SP) ← (SP) + 2 - - - - - - - - - - POPW PS 1 4 0 (c) word (PS) ← ((SP)), (SP) ← (SP) + 2 - - * * * * * * * - POPW rlst 2 *2 *5 *4 (rlst) ← ((SP)), (SP) ← (SP) + 2n - - - - - - - - - - JCTX @A 1 14 0 6 × (c) Context switch instruction - - * * * * * * * - AND CCR,#imm8 2 3 0 0 byte (CCR) ← (CCR) and imm8 - - * * * * * * * - OR CCR,#imm8 2 3 0 0 byte (CCR) ← (CCR) or imm8 - - * * * * * * * - MOV RP,#imm8 2 2 0 0 byte (RP) ← imm8 - - - - - - - - - - MOV ILM,#imm8 2 2 0 0 byte (ILM) ← imm8 - - - - - - - - - - MOVEA RWi,ear 2 3 1 0 word (RWi) ← ear - - - - - - - - - - MOVEA RWi,eam 2+ 2+(a) 1 0 word (RWi) ← eam - - - - - - - - - - MOVEA A,ear 2 1 0 0 word (A) ← ear - * - - - - - - - - MOVEA A,eam 2+ 1+(a) 0 0 word (A) ← eam - * - - - - - - - - ADDSP #imm8 2 3 0 0 word (SP) ← (SP) + ext(imm8) - - - - - - - - - - ADDSP #imm16 3 3 0 0 word (SP) ← (SP) + imm16 - - - - - - - - - - MOV A,brg1 2 *1 0 0 byte (A) ← (brg1) Z * - - - * * - - - MOV brg2,A - 2 1 0 0 byte (brg2) ← (A) - - - - - * * - - NOP 1 1 0 0 No operation - - - - - - - - - - ADB 1 1 0 0 Prefix code for AD space access - - - - - - - - - - DTB 1 1 0 0 Prefix code for DT space access - - - - - - - - - - PCB 1 1 0 0 Prefix code for PC space access - - - - - - - - - - SPB 1 1 0 0 Prefix code for SP space access - - - - - - - - - - NCC 1 1 0 0 Prefix code for flag no-change - - - - - - - - - - CMR 1 1 0 0 Prefix code for common register bank - - - - - - - - - - *1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2 *2: 7 + 3 × (POP count) + 2 × (POP last register number), 7 when RLST = 0 (no transfer register) *3: 29 + 3 × (PUSH count) - 3 × (PUSH last register number), 8 when RLST = 0 (no transfer register) *4: (POP count) × (c) or (PUSH count) × (c) *5: (POP count) or (PUSH count) Note: See Table B.5-1 and Table B.5-2 for information on (a) and (c) in the table. 666 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series Table B.8-16 21 Bit Operand Instructions Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW MOVB A,dir:bp 3 5 0 (b) byte (A) ← (dir:bp)b Z * - - - * * - - - MOVB A,addr16:bp 4 5 0 (b) byte (A) ← (addr16:bp)b Z * - - - * * - - - MOVB A,io:bp 3 4 0 (b) byte (A) ← (io:bp)b Z * - - - * * - - - MOVB dir:bp,A 3 7 0 2 × (b) bit (dir:bp)b ← (A) - - - - - * * - - * MOVB addr16:bp,A 4 7 0 2 × (b) bit (addr16:bp)b ← (A) - - - - - * * - - * MOVB io:bp,A 3 6 0 2 × (b) bit (io:bp)b ← (A) - - - - - * * - - * SETB dir:bp 3 7 0 2 × (b) bit (dir:bp)b ← 1 - - - - - - - - - * SETB addr16:bp 4 7 0 2 × (b) bit (addr16:bp)b ← 1 - - - - - - - - - * SETB io:bp 3 7 0 2 × (b) bit (io:bp)b ← 1 - - - - - - - - - * * CLRB dir:bp 3 7 0 2 × (b) bit (dir:bp)b ← 0 - - - - - - - - - CLRB addr16:bp 4 7 0 2 × (b) bit (addr16:bp)b ← 0 - - - - - - - - - * CLRB io:bp 3 7 0 2 × (b) bit (io:bp)b ← 0 - - - - - - - - - * BBC dir:bp,rel 4 *1 0 (b) Branch on (dir:bp) b = 0 - - - - - - * - - - BBC addr16:bp,rel 5 *1 0 (b) Branch on (addr16:bp) b = 0 - - - - - - * - - - BBC io:bp,rel 4 *2 0 (b) Branch on (io:bp) b = 0 - - - - - - * - - - BBS dir:bp,rel 4 *1 0 (b) Branch on (dir:bp) b = 1 - - - - - - * - - - BBS addr16:bp,rel 5 *1 0 (b) Branch on (addr16:bp) b = 1 - - - - - - * - - - BBS io:bp,rel 4 *2 0 (b) SBBS addr16:bp,rel 5 *3 0 2 × (b) Branch on (io:bp) b = 1 - - - - - - * - - - Branch on (addr16:bp) b = 1, bit (addr16:bp) b ← 1 - - - - - - * - - * WBTS io:bp 3 *4 0 WBTC io:bp 3 *4 0 *5 Waits until (io:bp) b = 1 - - - - - - - - - - *5 Waits until (io:bp) b = 0 - - - - - - - - - - RMW *1: 8 when a branch is made; otherwise, 7 *2: 7 when a branch is made; otherwise, 6 *3: 10 when the condition is met; otherwise, 9 *4: Undefined count *5: Until the condition is met Note: See Table B.5-1 and Table B.5-2 for information on (b) in the table. Table B.8-17 6 Accumulator Operation Instructions (Byte, Word) # ~ RG B LH AH I S T N Z V C SWAP Mnemonic 1 3 0 0 byte (A)0-7 ↔ (A)8-15 - - - - - - - - - - SWAPW 1 2 0 0 word (AH) ↔ (AL) - * - - - - - - - - EXT 1 1 0 0 Byte sign extension X - - - - * * - - - EXTW 1 2 0 0 Word sign extension - X - - - * * - - - ZEXT 1 1 0 0 Byte zero extension Z - - - - R * - - - ZEXTW 1 1 0 0 Word zero extension - Z - - - R * - - - CM44-10129-6E Operation FUJITSU MICROELECTRONICS LIMITED 667 APPENDIX APPENDIX B Instructions MB90330A Series Table B.8-18 10 String Instructions Mnemonic # ~ RG B Operation LH AH I S T N Z V C RMW - MOVS / MOVSI 2 *2 *5 *3 byte transfer @AH+ ← @AL+, counter = RW0 - - - - - - - - - MOVSD 2 *2 *5 *3 byte transfer @AH- ← @AL-, counter = RW0 - - - - - - - - - - SCEQ / SCEQI 2 *1 *8 *4 byte search @AH+ ← AL, counter = RW0 - - - - - * * * * - SCEQD 2 *1 *8 *4 byte search @AH- ← AL, counter = RW0 - - - - - * * * * FILS / FILSI 2 6m+6 *8 *3 byte fill @AH+ ← AL, counter = RW0 - - - - - * * - - - MOVSW / MOVSWI 2 *2 *5 *6 word transfer @AH+ ← @AL+, counter = RW0 - - - - - - - - - - MOVSWD 2 *2 *5 *6 word transfer @AH- ← @AL-, counter = RW0 - - - - - - - - - - SCWEQ / SCWEQI 2 *1 *8 *7 word search @AH+ - AL, counter = RW0 - - - - - * * * * - SCWEQD 2 *1 *8 *7 word search @AH- - AL, counter = RW0 - - - - - * * * * - FILSW / FILSWI 2 6m+6 *8 *6 word fill @AH+ ← AL, counter = RW0 - - - - - * * - - - *1: 5 when RW0 is 0, 4 + 7 × (RW0) when the counter expires, or 7n + 5 when a match occurs *2: 5 when RW0 is 0; otherwise, 4 + 8 × (RW0) *3: (b) × (RW0) + (b) × (RW0) When the source and destination access different areas, calculate the (b) item individually. *4: (b) × n *5: 2 × (b) × (RW0) *6: (c) × (RW0) + (c) × (RW0) When the source and destination access different areas, calculate the (c) item individually. *7: (c) × n *8: (b) × (RW0) Note: m: RW0 value (counter value), n: Loop count See Table B.5-1 and Table B.5-2 for information on (b) and (c) in the table. 668 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E APPENDIX APPENDIX B Instructions MB90330A Series B.9 Instruction Map Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F2MC-16LX instruction map. ■ Structure of Instruction Map Figure B.9-1 Structure of Instruction Map Basic page map Bit operation instructions Character string operation instructions 2-byte instructions : Byte 1 ea instructions × 9 : Byte 2 An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it references byte 1, and can check the following one byte by referencing the map for byte 2. Figure B.9-2 shows the correspondence between an actual instruction code and instruction map. CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED 669 APPENDIX APPENDIX B Instructions MB90330A Series Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map Some instructions do not contain byte 2. Instruction code Length varies depending on the instruction. Byte 1 Byte 2 Operand Operand ... [Basic page map] XY +Z [Extended page map]* UV +W *: The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte instructions, and ea instructions. Actually, there are multiple extended page maps for each type of instructions. An example of an instruction code is shown in Table B.9-1. Table B.9-1 Example of an Instruction Code Byte 1 (from basic page map) Byte 2 (from extended page map) NOP 00 +0=00 - AND A, #8 30 +4=34 - MOV A, ADB 60 +F=6F 00 +0=00 CBNE @RW2+d8, #8, rel 70 +0=70 F0 +2=F2 Instruction 670 FUJITSU MICROELECTRONICS LIMITED CM44-10129-6E CM44-10129-6E FUJITSU MICROELECTRONICS LIMITED +F +E +D +C +B +A +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 A ZEXT SWAP ADDSP DTB ADB SPB #8 A, #8 dir, A A, dir io, A A, io JMP BRA 60 MULU DIVU ea @A instruction 2 A MOVW MOVX RET SP, A A, addr16 A0 B0 C0 ea instruction 8 D0 E0 F0 rel LSRW ASRW LSLW SWAPW ZEXTW XORW ORW ANDW ORW PUSHW POPW A, #16 AH AH MOVW ea, RWi Bit operation MOV A instruction ea, Ri MOVW RWi, ea PUSHW POPW 2-byte XCHW A rlst rlst instruction RWi, ea Character XORW PUSHW POPW XCH operation A A, #16 PS PS string Ri, ea instruction A ANDW PUSHW POPW A A, #16 A CMPW MOVL MOVW RETI A, #16 A, #32 addr16, A ADDSP MULUW NOTW A #16 A A A EXTW A BHI BLS BGT BLE rel rel rel rel rel BGE CMPL CMPW A, #32 NEGW A rel BLT rel rel rel rel rel MOV MOV CBNE A, CWBNE A, MOVW MOVW INTP MOV RP, #8 ILM, #8 #8, rel #16, rel A, #16 A,addr16 addr24 Ri, ea BT BNV BV BP BN BNC/BHS rel BC/BLO BNZ/BNE rel rel ADDW MOVW MOVW INT ea MOVW MOVW MOVW MOVW A, MOVW A, #16 A, dir A, io #vct8 instruction 9 A, RWi RWi, A RWi, #16 @RWi+d8 @RWi+d8, A NOT ea instruction 7 MOVX MOVX CALLP ea A, dir A, io addr24 instruction 6 MOVW MOVW RETP A, #8 A, SP io, #16 A, #8 90 BNT SUBL SUBW A, #32 A A A XOR OR OR CCR, #8 80 ea MOV MOV MOV MOVX MOVX A, MOVN CALL BZ/BEQ rel instruction 1 A, Ri Ri, A Ri, #8 A, Ri @RWi+d8 A, #