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The following document contains information on Cypress products.
FUJITSU MICROELECTRONICS
CM44-10134-2E
CONTROLLER MANUAL
2
F MC-16LX
16-BIT MICROCONTROLLER
MB90945 Series
HARDWARE MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90945 Series
HARDWARE MANUAL
The information for microcontroller supports is shown in the following homepage.
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page
"Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
http://edevice.fujitsu.com/micom/en-support/
FUJITSU MICROELECTRONICS LIMITED
PREFACE
■ Objectives and intended reader
Thank you very much for your continued patronage of Fujitsu semiconductor products.
The MB90945 series has been developed as a general-purpose version of the F2MC-16LX series,
which is an original 16-bit single-chip microcontroller compatible with the Application Specific IC
(ASIC).
This manual explains the functions and operation of the MB90945 series for designers who actually
use the MB90945 series to design products. Please read this manual first.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ Trademark
Other systems and product names in this manual are trademarks of respective companies or
organizations.
The symbols ™ and ® are sometimes omitted in this manual.
■ Structure of this preliminary manual
CHAPTER 1 "OVERVIEW"
The MB90945 series is a family member of the F2MC-16LX microcontrollers.
CHAPTER 2 "CPU"
This chapter explains the CPU.
CHAPTER 3 "INTERRUPTS"
This chapter explains the functions and operations of the interrupt.
CHAPTER 4 "DELAYED INTERRUPT"
This chapter explains the functions and operations of the delayed interrupt.
CHAPTER 5 "CLOCKS"
This chapter describes the clocks used by MB90945 series microcontrollers.
CHAPTER 6 "CLOCK MODULATOR"
This chapter provides an overview of the clock modulator and its features. It describes the
register structure and operations of the clock modulator.
CHAPTER 7 "RESETS"
This chapter describes resets for the MB90945 series microcontrollers.
CHAPTER 8 "LOW-POWER CONTROL CIRCUIT"
This chapter explains the functions and operations of the low-power control circuits.
CHAPTER 9 "MEMORY ACCESS MODES"
This chapter explains the functions and operations of the memory access modes.
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CHAPTER 10 "I/O PORTS"
This chapter explains the functions and operations of the I/O ports.
CHAPTER 11 "TIMEBASE TIMER"
This chapter explains the functions and operations of the timebase timer.
CHAPTER 12 "WATCH-DOG TIMER"
This chapter explains the functions and operations of the watch-dog timer.
CHAPTER 13 "16-BIT I/O TIMER"
This chapter explains the functions and operations of the 16-bit I/O timer.
CHAPTER 14 "16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)"
This chapter explains the functions and operations of the 16-bit reload timer (with the event
count function).
CHAPTER 15 "8/16-BIT PPG"
This chapter explains the 8/16-bit PPG and its functions.
CHAPTER 16 "DTP/EXTERNAL INTERRUPTS"
This chapter explains the functions and operations of the DTP/external interrupts.
CHAPTER 17 "8/10-BIT A/D CONVERTER"
This chapter explains the functions and operations of the 8/10-bit A/D converter.
CHAPTER 18 "UART0"
This chapter explains the functions and operations of the UART0.
CHAPTER 19 "UART2/3"
This chapter explains the functions and operations of the UART2/3.
CHAPTER 20 "400 kHz I2C INTERFACE"
This section explains the functions and operation of the fast I2C interface.
CHAPTER 21 "SERIAL I/O"
This chapter explains the functions and operations of the serial I/O.
CHAPTER 22 "CAN CONTROLLER"
This chapter explains the functions and operations of the CAN controller. CAUTION: Do not use
the clock modulation and CAN at the same time on devices MB90F947, MB90F949 and
MB90V390HA. The problem is fixed on MB90F946A, MB90947A, MB90F947A, MB90F949A,
MB90V390HB.
CHAPTER 23 "ADDRESS MATCH DETECTION FUNCTION"
This chapter explains the functions and operations of the address match detection function.
CHAPTER 24 "ROM MIRRORING MODULE"
This chapter explains the ROM mirroring module.
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CHAPTER 25 "1M/2M/3M-BIT FLASH MEMORY"
This chapter explains the functions and operations of the 1M/2M/3M-bit flash memory. The
following three methods are available for writing data to and erasing data from the flash
memory:
• Parallel programmer
• Serial programmer
• Executing programs to write/erase data
This chapter explains "Executing programs to write/erase data".
CHAPTER 26
"EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING
CONNECTION"
This chapter provides examples of F2MC-16LX MB90F947 synchronous serial programming
connection.
APPENDIX
The appendixes provide I/O maps, instructions, and other information.
iii
• The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of
the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
• Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
• The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©2006-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
CHAPTER 2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.8
2.9
2.10
2.11
CPU ............................................................................................................ 23
Outline of the CPU ............................................................................................................................
Memory Space ..................................................................................................................................
Memory Space Map ..........................................................................................................................
Linear Addressing .............................................................................................................................
Bank Addressing Types ....................................................................................................................
Multi-Byte Data in Memory Space ....................................................................................................
Registers ...........................................................................................................................................
Accumulator (A) ...........................................................................................................................
User Stack Pointer (USP) and System Stack Pointer (SSP) .......................................................
Processor Status (PS) .................................................................................................................
Program Counter (PC) .................................................................................................................
Register Bank ...................................................................................................................................
Prefix Codes .....................................................................................................................................
Interrupt Disable Instructions ............................................................................................................
Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions ................................................
CHAPTER 3
3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.6
3.7
3.7.1
3.7.2
OVERVIEW ................................................................................................... 1
Product Overview ............................................................................................................................... 2
Features .............................................................................................................................................. 3
Block Diagram of MB90V390HA/HB ................................................................................................... 5
Block Diagram of MB90F946A ........................................................................................................... 6
Block Diagram of MB90F947(A)/MB90947A ...................................................................................... 7
Block Diagram of MB90F949(A) ......................................................................................................... 8
Pin Assignment ................................................................................................................................... 9
Package Dimensions ........................................................................................................................ 12
Pin Functions .................................................................................................................................... 13
Input-Output Circuits ......................................................................................................................... 17
Handling Device ................................................................................................................................ 20
24
25
28
30
31
33
34
36
37
38
41
42
44
46
47
INTERRUPTS ............................................................................................. 49
Outline of Interrupts ..........................................................................................................................
Interrupt Vector .................................................................................................................................
Interrupt Control Registers (ICR) ......................................................................................................
Interrupt Flow ....................................................................................................................................
Hardware Interrupts ..........................................................................................................................
Hardware Interrupt Operation ......................................................................................................
Occurrence and Release of Hardware Interrupt ..........................................................................
Multiple interrupts ........................................................................................................................
Software Interrupts ...........................................................................................................................
Extended Intelligent I/O Service (EI2OS) ..........................................................................................
Extended Intelligent I/O Service Descriptor (ISD) .......................................................................
EI2OS Status Register (ISCS) .....................................................................................................
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50
52
54
58
60
61
62
63
64
66
68
70
3.8
3.9
Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS) .............. 71
Exceptions ........................................................................................................................................ 74
CHAPTER 4
4.1
4.2
4.3
CHAPTER 5
5.1
5.2
5.3
5.3.1
5.3.2
5.4
5.5
5.6
RESETS .................................................................................................... 103
104
106
108
109
111
114
LOW-POWER CONTROL CIRCUIT ........................................................ 115
Overview of Low Power Consumption Mode ..................................................................................
Block Diagram of the Low-Power Consumption Control Circuit .....................................................
Low-Power Consumption Mode Control Register (LPMCR) ...........................................................
CPU Intermittent Operation Mode ..................................................................................................
Standby Mode .................................................................................................................................
Sleep Mode ...............................................................................................................................
Timebase Timer Mode ...............................................................................................................
Stop Mode .................................................................................................................................
Status Change Diagram .................................................................................................................
Usage Notes on Low-Power Consumption Mode ...........................................................................
CHAPTER 9
9.1
9.2
9.3
CLOCK MODULATOR ............................................................................... 97
Resets .............................................................................................................................................
Reset Cause and Oscillation Stabilization Wait Times ...................................................................
External Reset Pin ..........................................................................................................................
Reset Operation ..............................................................................................................................
Reset Cause Bits ............................................................................................................................
Status of Pins in a Reset ................................................................................................................
CHAPTER 8
8.1
8.2
8.3
8.4
8.5
8.5.1
8.5.2
8.5.3
8.6
8.7
80
82
84
85
88
90
93
94
Overview ........................................................................................................................................... 98
Clock Modulator Control Register (CMCR) ....................................................................................... 99
Application Note .............................................................................................................................. 101
CHAPTER 7
7.1
7.2
7.3
7.4
7.5
7.6
CLOCKS ..................................................................................................... 79
Clocks ...............................................................................................................................................
Block Diagram of the Clock Generation Block ..................................................................................
Clock Selection Registers .................................................................................................................
Clock Selection Register (CKSCR) .............................................................................................
PLL and Special Configuration Control Register (PSCCR) .........................................................
Clock Mode .......................................................................................................................................
Oscillation Stabilization Wait Time ....................................................................................................
Connection of an Oscillator or an External Clock to the Microcontroller ...........................................
CHAPTER 6
6.1
6.2
6.3
DELAYED INTERRUPT ............................................................................. 75
Outline of Delayed Interrupt Module ................................................................................................. 76
Delayed Interrupt Register ................................................................................................................ 77
Delayed Interrupt Operation ............................................................................................................. 78
116
119
121
125
126
127
129
131
134
136
MEMORY ACCESS MODES .................................................................... 139
Outline of Memory Access Modes .................................................................................................. 140
Mode Pins ....................................................................................................................................... 141
Mode Data ...................................................................................................................................... 142
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CHAPTER 10 I/O PORTS ................................................................................................ 145
10.1 I/O Ports ..........................................................................................................................................
10.2 I/O Port Registers ...........................................................................................................................
10.2.1 Port Data Register .....................................................................................................................
10.2.2 Port Direction Register ..............................................................................................................
10.2.3 Analog Input Enable Register ....................................................................................................
10.2.4 Input Level Select Register (MB90V390HA/HB only) ................................................................
146
147
148
150
151
152
CHAPTER 11 TIMEBASE TIMER ................................................................................... 155
11.1
11.2
11.3
Outline of Timebase Timer ............................................................................................................. 156
Timebase Timer Control Register ................................................................................................... 157
Operations of Timebase Timer ....................................................................................................... 159
CHAPTER 12 WATCH-DOG TIMER ............................................................................... 161
12.1
12.2
Outline of Watch-Dog Timer ........................................................................................................... 162
Watch-Dog Timer Operation ........................................................................................................... 165
CHAPTER 13 16-BIT I/O TIMER ..................................................................................... 169
13.1 Outline of 16-Bit I/O Timer ..............................................................................................................
13.2 16-Bit I/O Timer Registers ..............................................................................................................
13.3 16-Bit Free Run Timer ....................................................................................................................
13.3.1 Data Register .............................................................................................................................
13.3.2 Control Status Register .............................................................................................................
13.3.3 16-Bit Free Run Timer Operation ..............................................................................................
13.4 Output Compare .............................................................................................................................
13.4.1 Output Compare Register ..........................................................................................................
13.4.2 Control Status Register of Output Compare ..............................................................................
13.4.3 16-Bit Output Compare Operation .............................................................................................
13.5 Input Capture ..................................................................................................................................
13.5.1 Input Capture Register Details ..................................................................................................
13.5.2 16-Bit Input Capture Operation ..................................................................................................
170
172
174
175
176
179
181
182
183
187
193
194
199
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) ................ 201
14.1 Outline of 16-Bit Reload Timer (with Event Count Function) ..........................................................
14.2 16-Bit Reload Timer (with Event Count Function) ..........................................................................
14.2.1 Timer Control Status Register (TMCSR0) .................................................................................
14.2.2 Register Layout of 16-Bit Timer Register (TMR0)/16-Bit Reload Register (TMRLR0) ..............
14.3 Internal Clock and External Clock Operations of 16-Bit Reload Timer ...........................................
14.4 Underflow Operation of 16-Bit Reload Timer ..................................................................................
14.5 Output Pin Functions of 16-Bit Reload Timer .................................................................................
14.6 Counter Operation State .................................................................................................................
202
203
204
207
208
210
211
212
CHAPTER 15 8/16-BIT PPG ........................................................................................... 213
15.1 Outline of 8/16-Bit PPG ..................................................................................................................
15.2 Block Diagram of 8/16-Bit PPG ......................................................................................................
15.3 8/16-Bit PPG Registers ...................................................................................................................
15.3.1 PPG0 Operation Mode Control Register (PPGC0) ....................................................................
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214
215
219
220
15.3.2 PPG1 Operation Mode Control Register (PPGC1) ....................................................................
15.3.3 PPG0/1 Clock Select Register (PPG01) ....................................................................................
15.3.4 Reload Register (PRLL/PRLH) ..................................................................................................
15.4 Operations of 8/16-Bit PPG ............................................................................................................
15.5 Selecting a Count Clock for 8/16-Bit PPG ......................................................................................
15.6 Controlling Pin Output of 8/16-Bit PPG Pulses ...............................................................................
15.7 8/16-Bit PPG Interrupts ...................................................................................................................
15.8 Initial Values of 8/16-Bit PPG Hardware .........................................................................................
222
224
226
227
229
230
231
232
CHAPTER 16 DTP/EXTERNAL INTERRUPTS .............................................................. 235
16.1
16.2
16.3
16.4
16.5
Outline of DTP/External Interrupts ..................................................................................................
DTP/External Interrupt Registers ....................................................................................................
Operations of DTP/External Interrupts ............................................................................................
Switching between DTP and External Interrupt Requests ..............................................................
Notes on Using DTP/External Interrupts .........................................................................................
236
237
239
241
242
CHAPTER 17 8/10-BIT A/D CONVERTER ..................................................................... 245
17.1 Outline of the 8/10-Bit A/D Converter .............................................................................................
17.2 Configuration of the 8/10-Bit A/D Converter ...................................................................................
17.3 8/10-Bit A/D Converter Pins ............................................................................................................
17.4 8/10-Bit A/D Converter Registers ...................................................................................................
17.4.1 Analog Input Enable/ADC Select Register ................................................................................
17.4.2 A/D Control Status Register 1 (ADCS1) ....................................................................................
17.4.3 A/D Control Status Register 0 (ADCS0) ....................................................................................
17.4.4 A/D Data Register (ADCR0, ADCR1) ........................................................................................
17.5 8/10-Bit A/D Converter Interrupts ...................................................................................................
17.6 Operation of the 8/10-Bit A/D Converter .........................................................................................
17.6.1 Conversion Using EI2OS ...........................................................................................................
17.6.2 A/D Conversion Data Protection Function .................................................................................
17.7 Notes on the 8/10-Bit A/D Converter ..............................................................................................
17.8 Sample Program 1 for the 8/10-Bit A/D Converter (Single Conversion Mode Using EI2OS) .........
17.9 Sample Program 2 for the 8/10-Bit A/D Converter (Continuous Conversion Mode Using EI2OS)
.........................................................................................................................................................
17.10 Sample Program 3 for the 8/10-Bit A/D Converter (Stop Conversion Mode Using EI2OS) ............
246
248
250
252
253
254
256
258
260
261
263
264
266
267
270
273
CHAPTER 18 UART0 ...................................................................................................... 277
18.1 Features of UART0 .........................................................................................................................
18.2 UART0 Block Diagram ....................................................................................................................
18.3 UART0 Registers ............................................................................................................................
18.3.1 Serial Mode Control Register (UMC0) .......................................................................................
18.3.2 Status Register (USR0) .............................................................................................................
18.3.3 Input Data Register (UIDR0) and Output Data Register (UODR0) ............................................
18.3.4 Rate and Data Register (URD0) ................................................................................................
18.4 UART0 Operation ...........................................................................................................................
18.5 Baud Rate .......................................................................................................................................
18.6 Internal and External Clock .............................................................................................................
18.7 Transfer Data Format .....................................................................................................................
viii
278
279
280
281
283
285
286
288
289
292
293
18.8 Parity Bit .........................................................................................................................................
18.9 Interrupt Generation and Flag Set Timings .....................................................................................
18.9.1 Flag Set Timings for a Receive Operation (Mode 0, mode 1, or mode 3) .................................
18.9.2 Flag Set Timings for a Receive Operation (in Mode 2) .............................................................
18.9.3 Flag Set Timings for a Transmit Operation ................................................................................
18.9.4 Status Flag During Transmit and Receive Operation ................................................................
18.10 UART0 Application Example ..........................................................................................................
294
295
296
297
298
299
300
CHAPTER 19 UART2/3 ................................................................................................... 303
19.1 Overview of UART2/3 .....................................................................................................................
19.2 Configuration of UART2/3 ...............................................................................................................
19.3 UART2/3 Pins .................................................................................................................................
19.4 UART2/3 Registers .........................................................................................................................
19.4.1 Serial Control Register (SCR2/3) ..............................................................................................
19.4.2 Serial Mode Register (SMR2/3) .................................................................................................
19.4.3 Serial Status Register (SSR2/3) ................................................................................................
19.4.4 Reception and Transmission Data Register (RDR2/3 and TDR2/3) ..........................................
19.4.5 Extended Status/Control Register (ESCR2/3) ...........................................................................
19.4.6 Extended Communication Control Register (ECCR2/3) ............................................................
19.4.7 Baud Rate Generator Register 0/1 (BGR02/03 and BGR12/13) ...............................................
19.5 UART2/3 Interrupts .........................................................................................................................
19.5.1 Reception Interrupt Generation and Flag Set Timing ................................................................
19.5.2 Transmission Interrupt Generation and Flag Set Timing ...........................................................
19.6 UART2/3 Baud Rates .....................................................................................................................
19.6.1 Setting the Baud Rate ...............................................................................................................
19.6.2 Restarting the Reload Counter ..................................................................................................
19.7 Operation of UART2/3 ....................................................................................................................
19.7.1 Operation in Asynchronous Mode (Operation Mode 0 and Mode 1) .........................................
19.7.2 Operation in Synchronous Mode (Operation Mode 2) ...............................................................
19.7.3 Operation with LIN Function (Operation Mode 3) ......................................................................
19.7.4 Direct Access to Serial Pins ......................................................................................................
19.7.5 Bidirectional Communication Function (Normal Mode) .............................................................
19.7.6 Master-Slave Communication Function (Multiprocessor Mode) ................................................
19.7.7 LIN Communication Function ....................................................................................................
19.7.8 Sample Flowcharts for UART2/3 in LIN Communication (Operation Mode 3) ...........................
19.8 Notes on Using UART2/3 ...............................................................................................................
304
308
313
315
316
318
320
322
324
326
328
329
333
334
336
338
341
343
345
347
350
353
354
356
359
360
362
CHAPTER 20 400 kHz I2C INTERFACE ......................................................................... 365
20.1 I2C Interface Overview ....................................................................................................................
20.2 I2C Interface Registers ...................................................................................................................
20.2.1 Bus Status Register (IBSR) .......................................................................................................
20.2.2 Bus Control Register (IBCR) .....................................................................................................
20.2.3 Ten Bit Slave Address Register (ITBA) .....................................................................................
20.2.4 Ten Bit Address Mask Register (ITMK) .....................................................................................
20.2.5 Seven Bit Slave Address Register (ISBA) .................................................................................
20.2.6 Data Register (IDAR) .................................................................................................................
20.2.7 Clock Control Register (ICCR) ..................................................................................................
ix
366
368
370
373
377
378
380
382
383
20.3
20.4
I2C Interface Operation ................................................................................................................... 386
Programming Flow Charts .............................................................................................................. 389
CHAPTER 21 SERIAL I/O ............................................................................................... 391
21.1 Outline of Serial I/O ........................................................................................................................
21.2 Serial I/O Registers .........................................................................................................................
21.2.1 Serial Mode Control Status Register (SMCS) ...........................................................................
21.2.2 Serial Data Register (SDR) .......................................................................................................
21.3 Serial I/O Prescaler (CDCR) ...........................................................................................................
21.4 Serial I/O Operation ........................................................................................................................
21.4.1 Shift Clock .................................................................................................................................
21.4.2 Serial I/O Operation ...................................................................................................................
21.4.3 Shift Operation Start/Stop Timing ..............................................................................................
21.4.4 Interrupt Function of the Extended Serial I/O Interface .............................................................
392
393
394
398
399
400
401
402
404
407
CHAPTER 22 CAN CONTROLLER ................................................................................ 409
22.1 Features of CAN Controller ............................................................................................................
22.2 Block Diagram of CAN Controller ...................................................................................................
22.3 List of Overall Control Registers .....................................................................................................
22.4 List of Message Buffers (ID Registers) ...........................................................................................
22.5 List of Message Buffers (DLC Registers and Data Registers) ........................................................
22.6 Classifying the CAN Controller Registers .......................................................................................
22.6.1 Control Status Register (CSR) ..................................................................................................
22.6.2 Bus Operation Stop Bit (HALT = 1) ...........................................................................................
22.6.3 Last Event Indicator Register (LEIR) .........................................................................................
22.6.4 Receive and Transmit Error Counters (RTEC) ..........................................................................
22.6.5 Bit Timing Register (BTR) ..........................................................................................................
22.6.6 Message Buffer Valid Register (BVALR) ...................................................................................
22.6.7 IDE Register (IDER) ..................................................................................................................
22.6.8 Transmission Request Register (TREQR) ................................................................................
22.6.9 Transmission RTR Register (TRTRR) .......................................................................................
22.6.10 Remote Frame Receiving Wait Register (RFWTR) ...................................................................
22.6.11 Transmission Cancel Register (TCANR) ...................................................................................
22.6.12 Transmission Complete Register (TCR) ....................................................................................
22.6.13 Transmission Interrupt Enable Register (TIER) .........................................................................
22.6.14 Reception Complete Register (RCR) ........................................................................................
22.6.15 Remote Request Receiving Register (RRTRR) ........................................................................
22.6.16 Receive Overrun Register (ROVRR) .........................................................................................
22.6.17 Reception Interrupt Enable Register (RIER) .............................................................................
22.6.18 Acceptance Mask Select Register (AMSR) ...............................................................................
22.6.19 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) ..........................................................
22.6.20 Message Buffers ........................................................................................................................
22.6.21 ID Register x (x = 0 to 15) (IDRx) ..............................................................................................
22.6.22 DLC Register x (x = 0 to 15) (DLCRx) .......................................................................................
22.6.23 Data Register x (x = 0 to 15) (DTRx) .........................................................................................
22.7 Transmission of CAN Controller .....................................................................................................
22.8 Reception of CAN Controller ..........................................................................................................
x
410
411
412
414
417
420
421
426
427
429
430
432
433
434
435
436
437
438
439
440
441
442
443
444
446
448
449
451
452
454
456
22.9
22.10
22.11
22.12
22.13
22.14
22.15
Reception Flowchart of CAN Controller ..........................................................................................
How to Use the CAN Controller ......................................................................................................
Procedure for Transmission by Message Buffer (x) .......................................................................
Procedure for Reception by Message Buffer (x) .............................................................................
Setting Configuration of Multi-level Message Buffer .......................................................................
Setting the CAN Direct Mode Register ...........................................................................................
Precautions when Using CAN Controller ........................................................................................
459
460
462
464
466
468
469
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION ......................................... 471
23.1
23.2
23.3
23.4
Outline of the Address Match Detection Function ..........................................................................
Registers of the Address Match Detection Function .......................................................................
Operation of the Address Match Detection Function ......................................................................
Example of the Address Match Detection Function ........................................................................
472
473
475
476
CHAPTER 24 ROM MIRRORING MODULE ................................................................... 481
24.1
24.2
Outline of ROM Mirroring Module ................................................................................................... 482
ROM Mirroring Register (ROMM) ................................................................................................... 483
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY ............................................................ 485
25.1 Overview of 1M/2M/3M-Bit Flash Memory ......................................................................................
25.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory ..........
25.3 Write/Erase Modes .........................................................................................................................
25.4 Flash Memory Control Status Register (FMCS) .............................................................................
25.5 Starting the Flash Memory Automatic Algorithm ............................................................................
25.6 Confirming the Automatic Algorithm Execution State .....................................................................
25.6.1 Data Polling Flag (DQ7) ............................................................................................................
25.6.2 Toggle Bit Flag (DQ6) ................................................................................................................
25.6.3 Timing Limit Exceeded Flag (DQ5) ...........................................................................................
25.6.4 Sector Erase Timer Flag (DQ3) .................................................................................................
25.6.5 Toggle Bit-2 Flag (DQ2) ............................................................................................................
25.7 Detailed Explanation of Writing to and Erasing Flash Memory .......................................................
25.7.1 Setting The Read/Reset State ...................................................................................................
25.7.2 Writing Data ...............................................................................................................................
25.7.3 Erasing All Data (Erasing Chips) ...............................................................................................
25.7.4 Erasing Optional Data (Erasing Sectors) ...................................................................................
25.7.5 Suspending Sector Erase ..........................................................................................................
25.7.6 Restarting Sector Erase ............................................................................................................
25.8 Notes on Using 1M/2M/3M-Bit Flash Memory ................................................................................
25.9 Reset Vector Address in Flash Memory .........................................................................................
25.10 Example of Programming 1M/2M/3M-Bit Flash Memory ................................................................
486
487
491
493
495
497
499
501
502
503
505
507
508
509
511
512
514
515
516
518
519
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING
CONNECTION........................................................................................... 523
26.1
26.2
26.3
Basic Configuration of MB90F947 Synchronous Serial Programming Connection ........................ 524
Example of Synchronous Serial Programming Connection (User Power Supply Used) ................ 528
Example of Synchronous Serial Programming Connection (Power Supplied from the Programmer)
......................................................................................................................................................... 530
xi
26.4
26.5
Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used)
......................................................................................................................................................... 532
Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied
from the Programmer) .................................................................................................................... 534
APPENDIX ......................................................................................................................... 537
APPENDIX A I/O Maps ..............................................................................................................................
APPENDIX B Instructions ...........................................................................................................................
B.1 Instruction Types ............................................................................................................................
B.2 Addressing .....................................................................................................................................
B.3 Direct Addressing ...........................................................................................................................
B.4 Indirect Addressing ........................................................................................................................
B.5 Execution Cycle Count ...................................................................................................................
B.6 Effective Address Field ..................................................................................................................
B.7 How to Read the Instruction List ....................................................................................................
B.8 F2MC-16LX Instruction List ............................................................................................................
B.9 Instruction Map ...............................................................................................................................
APPENDIX C Timing Diagrams in Flash Memory Mode ............................................................................
APPENDIX D List of Interrupt Vectors ........................................................................................................
538
548
549
550
552
558
566
569
570
573
587
609
617
INDEX................................................................................................................................... 621
xii
Main changes in this edition
Page
548 to 608
Changes (For details, refer to main body.)
Changed the entire part of "APPENDIX B Instructions"
The vertical lines marked in the left side of the page show the changes.
xiii
xiv
CHAPTER 1
OVERVIEW
The MB90945 series is a family member of the F2MC16LX microcontrollers.
1.1 Product Overview
1.2 Features
1.3 Block Diagram of MB90V390HA/HB
1.4 Block Diagram of MB90F946A
1.5 Block Diagram of MB90F947(A)/MB90947A
1.6 Block Diagram of MB90F949(A)
1.7 Pin Assignment
1.8 Package Dimensions
1.9 Pin Functions
1.10 Input-Output Circuits
1.11 Handling Device
1
CHAPTER 1 OVERVIEW
1.1
Product Overview
Table 1.1-1 provides an overview of the MB90945 series.
■ Product Overview
Table 1.1-1 Product Overview
2
Features
MB90V390HA
MB90V390HB
MB90F946A
MB90F947(A)
MB90F949(A)
MB90947A
Product type
Evaluation sample
Flash version
ROM version
CPU
F2MC-16LX CPU
System clock
On-chip PLL clock multiplier (x1, x2, x3, x4, x6, x8, 1/2 when PLL stop)
Minimum instruction execution time: 42 ns (4 MHz osc. PLL x6)
ROM/Flash memory
External
RAM
30 Kbytes
Package
PGA-299
Boot-block
Flash memory:
384 Kbytes on MB90F946A
128 Kbytes on MB90F947(A)
256 Kbytes on MB90F949(A)
with Hard-wired reset vector
16 Kbytes on MB90F946A
6 Kbytes on MB90F947(A)
12 Kbytes on MB90F949(A)
ROM memory 128K bytes
6 Kbytes
QFP-100
CHAPTER 1 OVERVIEW
1.2
Features
Table 1.2-1 lists the features of the MB90945 series.
■ Features
Table 1.2-1 MB90945 Features (1 / 2)
Features
MB90V390HA
MB90V390HB
MB90F946A
MB90F947(A)
MB90F949(A)
MB90947A
UART
1 Channel
Full duplex double buffer
Supports asynchronous/synchronous (with start/stop bit) transfer
Baud rate: 4808/9615/10417/19230/38460/62500/500000bps (asynchronous)
500K/1M/2Mbps (synchronous) at System clock = 20MHz
UART (SCI / LIN)
2 channels
I2C (400kbit/s)
1 channel
Serial I/O
Transfer can be started from MSB or LSB
Supports internal clock synchronized transfer and external clock synchronized transfer
Supports positive-edge and negative-edge clock synchronization
Baud rate: 31.25K/62.5K/125K/500K/1Mbps at System clock = 20MHz
A/D converter
15 input channels
1 channel
2 channels: MB90F946A
1 channel
10-bit or 8-bit resolution
Conversion time: 4.9 μs (per 1 channel)
16-bit reload timer
2 channels
1 channel
Operation clock frequency: fsys/21, fsys/23, fsys/25
(fsys = System clock frequency)
Supports External Event Count function
16-bit I/O timer
(2 channels)
Signals an interrupt when overflow
Supports Timer Clear when a match with Output Compare (Channel 0)
Operation clock frequency: fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27
(fsys = System clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU 2/3/4/5
16-bit output
compare
(4 channels)
Signals an interrupt when a match with 16-bit I/O timer
Four 16-bit compare registers
A pair of compare registers can be used to generate an output signal
16-bit input capture
(6 channels)
Rising edge, falling edge or rising & falling edge sensitive
Six 16-bit Capture registers
Signals an interrupt upon external event
3
CHAPTER 1 OVERVIEW
Table 1.2-1 MB90945 Features (2 / 2)
Features
MB90V390HA
MB90V390HB
MB90F946A
MB90F947(A)
MB90F949(A)
MB90947A
8/16-bit
programmable
pulse generator
(6 channels)
Supports 8-bit and 16-bit operation modes
Twelve 8-bit reload counters
Twelve 8-bit reload registers for "L" pulse width
Twelve 8-bit reload registers for "H" pulse width
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler
plus 8-bit reload counter
Operation clock frequency: fsys, fsys/21, fsys/22, fsys/23, fsys/24 or [email protected]=5MHz
(fsys = System clock frequency fosc = Oscillation clock frequency)
CAN interface
1 channel
Conforms to CAN specification version 2.0 part A and B
Automatic re-transmission in case of error
Automatic transmission responding to remote frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering:
Full bit compare / Full bit mask / Two partial bit masks
Supports up to 1Mbps
MB90V390HA, MB90F947, MB90F949: Do not use clock modulation and CAN at the same time
Clock modulator
Frequency and phase
modulation mode
Phase modulation mode
Phase modulation mode
MB90V390HA, MB90F947, MB90F949: Do not use clock
modulation and CAN at the same time
Reduces EMI by modulating the PLL clock
External interrupt
(8 channels)
Can be programmed edge sensitive or level sensitive
I/O ports
Virtually all external pins can be used as general-purpose I/O
All push-pull outputs
Bit-wise programmable as input/output or peripheral signal
Automotive hysteresis input characteristics
Flash memory
⎯
Supports automatic programming,
Embedded AlgorithmTM *, Write/Erase/
Erase-Suspend/Resume commands
A flag indicating completion of the
algorithm
Number of erase cycles: 10,000 times
Data retention time: 20 years
Hard-wired reset vector available in order to
point to a fixed boot sector in Flash
Memory
Boot block configuration
Erase can be performed on each block
Block protection with external
programming voltage
*: Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
4
⎯
CHAPTER 1 OVERVIEW
1.3
Block Diagram of MB90V390HA/HB
Figure 1.3-1 shows a block diagram of the MB90V390HA/HB.
■ Block Diagram of MB90V390HA/HB
Figure 1.3-1 Block Diagram of MB90V390HA/HB
X0, X1
RST
Clock
Controller
with Phase
Modulator
16LX
CPU
IO Timer0
RAM
30 Kbytes
SOT0
SCK0
SIN0
Input
Capture
6ch
IN5 to IN0
Output
Compare
4ch
OUT3 to
OUT0
Prescaler
IO Timer1
FRCK1
UART0
8/16-bit
PPG
6ch
PPG15 to
PPG10
PPG05 to
PPG00
UART2/3
(LIN/SCI/
SPI)
FMC-16 Bus
Prescaler x2
SOT2, SOT3
SCK2, SCK3
SIN2, SIN3
FRCK0
CAN
External
Interrupt
RX1
TX1
INT7 to INT0
Prescaler
SOT4
SCK4
SIN4
Serial I/O
AVCC
AVSS
AN14 to AN0
AVRH
AVRL
ADTG
10-bit
A/D
Converter
15ch
I2C
16-bit Reload
Timer 2ch
SDA
SCL
TIN1, TIN0
TOT1, TOT0
5
CHAPTER 1 OVERVIEW
1.4
Block Diagram of MB90F946A
Figure 1.4-1 shows a block diagram of the MB90F946A.
■ Block Diagram of MB90F946A
Figure 1.4-1 Block Diagram of MB90F946A
X0, X1
RST
Clock
Controller
with Phase
Modulator
16LX
CPU
IO Timer0
RAM
16 Kbytes
Input
Capture
6ch
IN5 to IN0
Output
Compare
4ch
OUT3 to
OUT0
Prescaler
IO Timer1
FRCK1
UART0
8/16-bit
PPG
6ch
PPG15 to
PPG10
PPG05 to
PPG00
RAM
384 Kbytes
SOT0
SCK0
SIN0
UART2/3
(LIN/SCI/
SPI)
FMC-16 Bus
Prescaler x2
SOT2, SOT3
SCK2, SCK3
SIN2, SIN3
FRCK0
CAN
External
Interrupt
RX1
TX1
INT7 to INT0
Prescaler
6
SOT4
SCK4
SIN4
Serial I/O
AVCC
AVSS
AN14 to AN0
AVRH
AVRL
ADTG
10-bit
A/D
Converter
15ch
I2C
SDA
SCL
16-bit Reload
TIN0
TOT0
Timer 1ch
CHAPTER 1 OVERVIEW
1.5
Block Diagram of MB90F947(A)/MB90947A
Figure 1.5-1 shows a block diagram of the MB90F947(A) and MB90947A.
■ Block Diagram of MB90F947(A)/MB90947A
Figure 1.5-1 Block Diagram of MB90F947(A)/MB90947A
X0, X1
RST
Clock
Controller
with Phase
Modulator
16LX
CPU
IO Timer0
RAM
6 Kbytes
Flash/
ROM*
128 Kbytes
SOT0
SCK0
SIN0
Input
Capture
6ch
IN5 to IN0
Output
Compare
4ch
OUT3 to
OUT0
Prescaler
IO Timer1
FRCK1
UART0
8/16-bit
PPG
6ch
PPG15 to
PPG10
PPG05 to
PPG00
UART3
(LIN/SCI/
SPI)
FMC-16 Bus
Prescaler
SOT3
SCK3
SIN3
FRCK0
CAN
External
Interrupt
RX1
TX1
INT7 to INT0
Prescaler
SOT4
SCK4
SIN4
AVCC
AVSS
AN14 to AN0
AVRH
AVRL
ADTG
Serial I/O
10-bit ADC
15ch
I2C
SDA
SCL
16-bit Reload
TIN0
TOT0
Timer 1ch
*: MB90F947(A) : Flash 128 Kbytes, MB90947A: ROM 128 Kbytes
7
CHAPTER 1 OVERVIEW
1.6
Block Diagram of MB90F949(A)
Figure 1.6-1 shows a block diagram of the MB90F949(A).
■ Block Diagram of MB90F949(A)
Figure 1.6-1 Block Diagram of MB90F949(A)
X0, X1
RSTX
Clock
Controller
with Phase
Modulator
16LX
CPU
IO Timer0
RAM
12 Kbytes
Input
Capture
6ch
IN5 to IN0
Output
Compare
4ch
OUT3 to
OUT0
Prescaler
IO Timer1
FRCK1
UART0
8/16-bit
PPG
6ch
Flash
256 Kbytes
SOT0
SCK0
SIN0
UART3
(LIN/SCI/
SPI)
FMC-16 Bus
Prescaler
SOT3
SCK3
SIN3
FRCK0
CAN
External
Interrupt
PPG15 to
PPG10
PPG05 to
PPG00
RX1
TX1
INT7 to INT0
Prescaler
SOT4
SCK4
SIN4
AVCC
AVSS
AN14 to AN0
AVRH
AVRL
ADTG
8
Serial I/O
10-bit ADC
15ch
I2C
SDA
SCL
16-bit Reload
TIN0
TOT0
Timer 1ch
CHAPTER 1 OVERVIEW
1.7
Pin Assignment
This chapter shows the pin assignments for the MB90945 series.
■ Pin Assignment of MB90V390HA/HB
Figure 1.7-1 Pin Assignment of MB90V390HA/HB
MD2
MD0
MD1
RST
P55/PPG15
P56/PPG00
P57/PPG01
P90/SIN2
P93/SIN3
P95/SOT3
P94/SCK3
P91/SCK2
P92/SOT2
P96
Vcc
Vss
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
P80
P81
P00/IN0
P01/IN1
P02/IN2
P03/IN3
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P04/IN4
81
50
P97/FRCK1
P05/IN5
82
49
PB7/FRCK0
P06/OUT0
83
48
P54/PPG14
P07/OUT1
84
47
P53/PPG13
P10/OUT2
85
46
P52/PPG12
P11/OUT3
86
45
P51/PPG11
P12
87
44
Vss
P13
88
43
P67/AN7
P14/TIN0
89
42
P66/AN6
Vcc
90
41
P65/AN5
Vss
91
40
P64/AN4
X1
92
39
P63/AN3
X0
93
38
P62/AN2
P15/TOT0
94
37
P61/AN1
P16
95
36
P60/AN0
P17
96
35
AVss
P20/TX1
97
34
AVRL
P21/RX1
98
33
AVRH
P22/INT2
99
32
AVcc
P23/INT3
100
31
PB6/SOT4/AN14
QFP - 100
Package code (mold)
FPT-100P-M06
PB5/SCK4/AN13
PB4/SIN4/AN12
PB3/PPG05/AN11
PB2/PPG04/AN10
PB1/PPG03/AN9
PB0/PPG02/AN8
P50/PPG10
P47/INT1
P46/INT0
P43/SCL
P42/SDA
P41
P40
C
Vss
Vcc
P45/ADTG
P44
P37
P36/SIN0
P35/SCK0
P33/TOT1
P34/SOT0
P32/TIN1
P31
P30
P27/INT7
P26/INT6
P25/INT5
P24/INT4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(FPT-100P-M06)
As seen with QFP100 probe cable
9
CHAPTER 1 OVERVIEW
■ Pin Assignment of MB90F946A
Figure 1.7-2 Pin Assignment of MB90F946A
MD2
MD0
MD1
RST
P55/PPG15
P56/PPG00
P57/PPG01
P90/SIN2
P93/SIN3
P95/SOT3
P94/SCK3
P91/SCK2
P92/SOT2
P96
Vcc
Vss
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
P80
P81
P00/IN0
P01/IN1
P02/IN2
P03/IN3
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P04/IN4
81
50
P97/FRCK1
P05/IN5
82
49
PB7/FRCK0
P06/OUT0
83
48
P54/PPG14
P07/OUT1
84
47
P53/PPG13
P10/OUT2
85
46
P52/PPG12
P11/OUT3
86
45
P51/PPG11
P12
87
44
Vss
P13
88
43
P67/AN7
P14/TIN0
89
42
P66/AN6
Vcc
90
41
P65/AN5
Vss
91
40
P64/AN4
X1
92
39
P63/AN3
X0
93
38
P62/AN2
P15/TOT0
94
37
P61/AN1
P16
95
36
P60/AN0
P17
96
35
AVss
P20/TX1
97
34
AVRL
P21/RX1
98
33
AVRH
P22/INT2
99
32
AVcc
P23/INT3
100
31
PB6/SOT4/AN14
QFP - 100
Package code (mold)
FPT-100P-M06
(FPT-100P-M06)
10
PB5/SCK4/AN13
PB4/SIN4/AN12
PB3/PPG05/AN11
PB2/PPG04/AN10
PB1/PPG03/AN9
PB0/PPG02/AN8
P50/PPG10
P47/INT1
P46/INT0
P43/SCL
P42/SDA
P41
P40
C
Vss
Vcc
P45/ADTG
P44
P37
P36/SIN0
P35/SCK0
P33
P34/SOT0
P32
P31
P30
P27/INT7
P26/INT6
P25/INT5
P24/INT4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CHAPTER 1 OVERVIEW
■ Pin Assignment of MB90947A/MB90F947(A)/MB90F949(A)
Figure 1.7-3 Pin Assignment of MB90947A/MB90F947(A)/MB90F949(A)
MD2
MD0
MD1
RST
P55/PPG15
P56/PPG00
P57/PPG01
P90
P93/SIN3
P95/SOT3
P94/SCK3
P91
P92
P96
Vcc
Vss
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
P80
P81
P00/IN0
P01/IN1
P02/IN2
P03/IN3
(TOP VIEW)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P04/IN4
81
50
P97/FRCK1
P05/IN5
82
49
PB7/FRCK0
P06/OUT0
83
48
P54/PPG14
P07/OUT1
84
47
P53/PPG13
P10/OUT2
85
46
P52/PPG12
P11/OUT3
86
45
P51/PPG11
P12
87
44
Vss
P13
88
43
P67/AN7
P14/TIN0
89
42
P66/AN6
Vcc
90
41
P65/AN5
Vss
91
40
P64/AN4
X1
92
39
P63/AN3
X0
93
38
P62/AN2
P15/TOT0
94
37
P61/AN1
P16
95
36
P60/AN0
P17
96
35
AVss
P20/TX1
97
34
AVRL
P21/RX1
98
33
AVRH
P22/INT2
99
32
AVcc
P23/INT3
100
31
PB6/SOT4/AN14
QFP - 100
Package code (mold)
FPT-100P-M06
PB5/SCK4/AN13
PB4/SIN4/AN12
PB3/PPG05/AN11
PB2/PPG04/AN10
PB1/PPG03/AN9
PB0/PPG02/AN8
P50/PPG10
P47/INT1
P46/INT0
P43/SCL
P42/SDA
P41
P40
C
Vss
Vcc
P45/ADTG
P44
P37
P36/SIN0
P35/SCK0
P33
P34/SOT0
P32
P31
P30
P27/INT7
P26/INT6
P25/INT5
P24/INT4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
(FPT-100P-M06)
11
CHAPTER 1 OVERVIEW
1.8
Package Dimensions
Figure 1.8-1 shows the package dimensions of the MB90945 series.
Note that the dimensions shown below are reference dimensions.
For formal dimensions of each package, contact us.
■ Package Dimensions
Figure 1.8-1 Package Dimensions
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP100-14×20-0.65
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
"A"
C
12
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8˚
31
2002 FUJITSU LIMITED F100008S-c-5-5
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
CHAPTER 1 OVERVIEW
1.9
Pin Functions
Table 1.9-1 describes the pin functions of the MB90945 series.
■ Pin Functions
Table 1.9-1 Pin Description (1 / 4)
Pin no.
Pin name
Circuit type
92
X1
93
X0
54
RST
B
Reset input
P00 to P05
D
General-purpose I/O
77 to 82
A
Function
Oscillation input
IN0 to IN5
83 to 86
P06, P07
P10, P11
Inputs for the input captures 0 to 5
D
OUT0 to
OUT3
87, 88
89
P12, P13
D
General-purpose I/O
P14
D
General-purpose I/O
P15
TIN0 input for the 16-bit reload timer 0
D
TOT0
95, 96
97
General-purpose I/O
TOT0 output for the 16-bit reload timer 0
P16, P17
D
General-purpose I/O
P20
D
General-purpose I/O
TX1
98
General-purpose I/O
Outputs for the output compares
TIN0
94
Oscillation output
P21
TX output for CAN interface 1
F
RX1
General-purpose I/O
RX input for CAN interface 1
99, 100
1 to 4
P22 to P27
5 to 8
P30 to P33
D
General-purpose I/O
P34
D
General-purpose I/O
9
D
INT2 to INT7
SOT0
General-purpose I/O
External interrupt inputs for INT2 to INT7
SOT output for UART 0
13
CHAPTER 1 OVERVIEW
Table 1.9-1 Pin Description (2 / 4)
Pin no.
10
Pin name
P35
Circuit type
D
SCK0
11
P36
General-purpose I/O
SCK input/output for UART 0
D
SIN0
General-purpose I/O
SIN input for UART 0
12
P37
D
General-purpose I/O
13
P44
D
General-purpose I/O
14
P45
D
General-purpose I/O
ADTG
18, 19
20
External trigger input of the A/D converter
P40, P41
D
General-purpose I/O
P42
F
General-purpose I/O
SDA
21
P43
Serial data for I2C interface
F
SCL
22, 23
P46, P47
24
P50
D
29
30
31
PB0 to PB3
General-purpose I/O
External interrupt inputs for INT0 to INT1
D
PPG10
25 to 28
General-purpose I/O
Serial clock for I2C interface
INT0, INT1
14
Function
General-purpose I/O
Output for the programmable pulse generator
E
General-purpose I/O
PPG02 to
PPG05
Output for the programmable pulse generators
AN8 to AN11
Input for the A/D converter
PB4
E
General-purpose I/O
SIN4
SIN input for the serial I/O
AN12
Input for the A/D converter
PB5
E
General-purpose I/O
SCK4
SCK input/output for the serial I/O
AN13
Input for the A/D converter
PB6
E
General-purpose I/O
SOT4
SOT output for the serial I/O
AN14
Input for the A/D converter
CHAPTER 1 OVERVIEW
Table 1.9-1 Pin Description (3 / 4)
Pin no.
36 to 43
Pin name
P60 to P67
Circuit type
E
AN0 to AN7
45 to 48
P51 to P54
PB7
D
P97
D
P55
D
P56, P57
D
P90
D
P93
D
P95
D
P94
D
P91
D
P92
D
67 to 74
General-purpose I/O
SCK input/output for UART 2 (LIN/SCI/SPI) (only on MB90F946A
and MB90V390HA/HB)
D
SOT2
64
General-purpose I/O
SCK input/output for UART 3 (LIN/SCI/SPI)
SCK2
63
General-purpose I/O
SOT output for UART 3 (LIN/SCI/SPI)
SCK3
62
General-purpose I/O
SIN input for UART 3 (LIN/SCI/SPI)
SOT3
61
General-purpose I/O
SIN input for UART 2 (LIN/SCI/SPI) (only on MB90F946A and
MB90V390HA/HB)
SIN3
60
General-purpose I/O
Outputs for the programmable pulse generators
SIN2
59
General-purpose I/O
Outputs for the programmable pulse generator
PPG00,
PPG01
58
General-purpose I/O
FRCK1 input for the 16-bit I/O timer 1
PPG15
56, 57
General-purpose I/O
FRCK0 input for the 16-bit I/O timer 0
FRCK1
55
General-purpose I/O
Outputs for the programmable pulse generators
FRCK0
50
General-purpose I/O
Inputs for the A/D converter
PPG11 to
PPG14
49
Function
General-purpose I/O
SOT output for UART 2 (LIN/SCI/SPI) (only on MB90F946A and
MB90V390HA/HB)
P96
D
General-purpose I/O
PA0 to PA7
H
General-purpose I/O
For the EVA device, these pins are high current outputs with slewrate
control
15
CHAPTER 1 OVERVIEW
Table 1.9-1 Pin Description (4 / 4)
Pin no.
75, 76
Circuit type
Function
P80, P81
H
General-purpose I/O
For the EVA device, these pins are high current outputs with slewrate
control
32
AVCC
-
Dedicated power supply pin (5V) for the A/D converter
33
AVRH
-
Dedicated pos. reference voltage pin for the A/D converter
34
AVRL
-
Dedicated neg. reference voltage pin for the A/D converter
35
AVSS
-
Dedicated power supply pin (0V) for the A/D converter
MD1, MD0
C
These are input pins used to designate the operating mode
They should be connected directly to VCC or VSS
51
MD2
G
This is an input pin used to designate the operating mode
It should be connected directly to VCC or VSS
15
65
90
VCC
-
These are power supply (5V) input pins
For the EVA device, pin 65 is the DVCC supply pin for the high current
outputs
16
44
66
91
VSS
-
These are power supply (0V) input pins
For the EVA device, pin 66 is the DVSS supply pin for the high current
outputs
17
C
-
Power supply stabilization capacitor pin
It should be connected to a 0.1 μF or more ceramic capacitor
52, 53
16
Pin name
CHAPTER 1 OVERVIEW
1.10
Input-Output Circuits
Table 1.10-1 lists the input-output circuits.
■ Input-output Circuits
Table 1.10-1 I/O Circuit Types (1 / 3)
Type
Circuit
Remarks
A
Oscillation feedback resistor: 1 MΩ approx.
X1
Clock input
P-ch
N-ch
X0
Standby control signal
B
CMOS hysteresis input with pull-up resistor
VCC
R(pull-up)
R
CMOS HYS
C
R
CMOS HYS
• EVA device: CMOS hysteresis input
• Flash device: CMOS input
17
CHAPTER 1 OVERVIEW
Table 1.10-1 I/O Circuit Types (2 / 3)
Type
Circuit
Remarks
D
• CMOS output (4mA)
• Automotive hysteresis input
VCC
P-ch
N-ch
R
Automotive HYS
E
• CMOS output (4mA)
• Automotive hysteresis input
• Analog input
VCC
P-ch
N-ch
P-ch
Analog input
N-ch
R
Automotive HYS
18
CHAPTER 1 OVERVIEW
Table 1.10-1 I/O Circuit Types (3 / 3)
Type
Circuit
Remarks
F
• CMOS output
P21: 4mA
P42, P43: 3mA
• CMOS hysteresis input
VCC
P-ch
High current
N-ch
R
CMOS HYS
G
R
CMOS HYS
• EVA/ROM device: CMOS hysteresis input with
pull-down resistor
• Flash device:
CMOS input without
pull-down
R(pull-down)
H
VCC
P-ch
• EVA/ROM device: CMOS high current output
(30mA) with slewrate
control
• Flash device:
CMOS output (4mA)
• Automotive hysteresis input
N-ch
R
Automotive HYS
19
CHAPTER 1 OVERVIEW
1.11
Handling Device
Special care is required for the followings when handling the device:
• Preventing latch-up
• Treatment of unused pins
• Stabilization of power supply voltage
• Using external clock
• Power supply pins (VCC/VSS)
•
•
•
•
•
•
•
Pull-up/pull-down resistors
Crystal oscillator circuit
Turning-on sequence of power supply to A/D converter and analog inputs
Connection of unused pins of A/D converter if A/D converter is unused
Precautions at power on
Initialization
Note on operation during PLL clock mode
■ Handling the Device
● Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions:
• A voltage higher than VCC or lower than VSS is applied to an input or output pin
• A voltage higher than the rated voltage is applied between VCC and VSS
• The AVCC power supply is applied before the VCC voltage
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
● Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch-up and possible permanent damage of
the device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors
should be more than 2 kΩ.
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the
above described connection.
● Stabilization of power supply voltage
If the power supply voltage varies acutely even within the operation assurance range of the VCC power
supply voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized.
As stabilization guidelines, stabilize the power supply voltage so that VCC ripple fluctuations (peak to peak
value) in the commercial frequencies (50 to 60 Hz) fall within 10% of the standard VCC power supply
voltage and the transient fluctuation rate becomes 0.1V/ms or less in instantaneous function for power
supply switching.
20
CHAPTER 1 OVERVIEW
● Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
Figure 1.11-1 shows a diagram of how to use external clock.
Figure 1.11-1 Using External Clock
MB90945 series
X0
Open
X1
● Using power supply pins (VCC/VSS)
Ensure that all VCC-level power supply pins are the same potential. In addition, ensure the same for all
VSS-level power supply pins. (See Figure 1.11-2.) If there are more than one VCC or VSS system, the
device may operate incorrectly even within the guaranteed operating range.
Figure 1.11-2 Using Power Supply Pins (VCC/VSS)
Vcc
Vss
Vcc
Vss
Vss
Vcc
MB90390
MB90945
Series
series
Vcc
Vss
Vss
Vcc
21
CHAPTER 1 OVERVIEW
● Pull-up/pull-down resistors
The MB90945 series does not support internal pull-up/pull-down resistors. Use external components where
needed.
● Crystal oscillator circuit
Noises around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via
shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make
sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a
ground area for stabilizing the operation.
● Turning-on sequence of power supply to A/D converter and analog inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to
AN14) after turning-on the digital power supply (VCC).
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make
sure that the voltage not exceed AVRH or AVCC (turning-on/off the analog and digital power supplies
simultaneously is acceptable).
● Connection of unused pins of A/D converter if A/D converter is unused
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
● Precautions at power on
To prevent a malfunction of the internal step-down circuit, the voltage rise time at power-on should be 50
μs or more (between 0.2 V and 2.7 V).
● Initialization
In the device, there are internal registers which is initialized only by a power-on reset. To initialize these
registers turning-on the power again.
● Note on operation during PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit
even when there is no external oscillator or external clock input is stopped. Performance of this operation,
however, cannot be guaranteed.
22
CHAPTER 2
CPU
This chapter explains the CPU.
2.1 Outline of the CPU
2.2 Memory Space
2.3 Memory Space Map
2.4 Linear Addressing
2.5 Bank Addressing Types
2.6 Multi-Byte Data in Memory Space
2.7 Registers
2.8 Register Bank
2.9 Prefix Codes
2.10 Interrupt Disable Instructions
2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions
23
CHAPTER 2 CPU
2.1
Outline of the CPU
The F2MC-16LX CPU core is a 16-bit CPU designed for applications that require highspeed real-time processing, such as home-use or vehicle-mounted electronic
appliances. The F2MC-16LX instruction set is designed for controller applications, and
is capable of high-speed, highly efficient control processing.
■ Outline of the CPU
In addition to 16-bit data, the F2MC-16LX CPU core can process 32-bit data by using an internal 32-bit
accumulator (32-bit data can be processed with some instructions). Up to 16 Mbytes of memory space
(expandable) can be used, which can be accessed by either the linear pointer or bank method. The
instruction system, based on the F2MC-8 A-T architecture, has been reinforced by adding instructions
compatible with high-level languages, expanding addressing modes, reinforcing multiplication and division
instructions, and enhancing bit processing. The features of the F2MC-16LX CPU are explained below.
● Minimum instruction execution time: 42 ns (at 4-MHz oscillation, 6 times clock multiplication)
● Maximum memory space: 16 Mbytes, accessed in linear or bank mode
● Instruction set optimized for controller applications
• Rich data types: Bit, byte, word, long word
• Extended addressing modes: 23 types
• High-precision operation (32-bit length) based on 32-bit accumulator
● Powerful interrupt functions
Eight priority levels (programmable)
● CPU-independent automatic transfer
Up to 16 channels of the extended intelligent I/O service
● Instruction set compatible with high-level language (C)/multitasking
System stack pointer/instruction set symmetry/barrel-shift instructions
● Improved execution speed: 4-byte queue
24
CHAPTER 2 CPU
2.2
Memory Space
An F2MC-16LX CPU has a 16 Mbytes memory space. All data program input and output
managed by the F2MC-16LX CPU are located in this 16 Mbytes memory space. The CPU
accesses the resources by indicating their addresses using a 24-bit address bus.
■ Outline of CPU Memory Space
All I/O, programs and data are located in the 16 Mbytes memory space of the F2MC-16LX CPU.
The CPU is able to access each resource through an address indicated by the 24-bit address bus.
Figure 2.2-1 shows a sample relationship between the F2MC-16LX system and memory map.
Figure 2.2-1 Sample Relationship between F2MC-16LX System and Memory
F2MC-16LX device
FFFFFFH
FFFC00H
Programs
FF0000H *1
Vector table area
Program area
ROM area
100000H
External area *4
010000H
008000H / 004000H *2
F2MC-16LX
CPU
Internal Bus
020000H
External area *4
000D00H *3
Data
EI2OS
000380H
000180H
000100H
0000C0H
Interrupts
0000B0H
Peripheral circuits
000020H
General-purpose
ports
*1
*2
*3
*4
ROM mirror area
(FF bank image)
000000H
Data area
General-purpose register
EI2OS descriptor area
RAM area
External area *4
Interrupt control
register area
Peripheral function
control register area
I/O port control
register area
I/O area
The size of the internal ROM differs for each model.
The area accessible by the image differs for each model (see dedicated chapter).
The size of the internal RAM differs for each model.
Access is not possible in single-chip mode.
25
CHAPTER 2 CPU
■ ROM Area
● Vector table area (address: FFFC00H to FFFFFFH)
This area is used as a vector table for vector call instructions, interrupt vectors, and reset vectors.
This area is allocated at the highest addresses of the ROM area. The start address of the corresponding
processing routine is set as data in each vector table address.
● Program area (address: Up to FFFBFFH)
ROM is built in as an internal program area.
The size of internal ROM differs for each model.
■ RAM Area
● Data area (address: From 000100H to 0010FFH (for 4 Kbytes))
The static RAM is built in as an internal data area.
The size of internal RAM differs for each model.
● General-purpose register area (address: 000180H to 00037FH)
Auxiliary registers used for 8-bit, 16-bit, and 32-bit arithmetic operations and transfer are allocated in this
area.
Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM.
When this area is used as a general-purpose register, general-purpose register addressing enables highspeed access with short instructions.
● Extended intelligent I/O service (EI2OS) descriptor area (address: 000100H to 00017FH)
This area retains the transfer modes, I/O addresses, transfer count, and buffer addresses.
Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM.
■ I/O Area
● Interrupt control register area (address: 0000B0H to 0000BFH)
The interrupt control registers (ICR00 to ICR15) correspond to all peripheral functions that have an
interrupt function. These registers set interrupt levels and control the extended intelligent I/O service
(EI2OS).
● Peripheral function control register area (address: 000020H to 0000AFH)
This register controls the built-in peripheral functions and inputs and outputs data.
● I/O port control register area (address: 000000H to 00001FH)
This register controls I/O ports, and inputs and outputs data.
26
CHAPTER 2 CPU
■ Address Generation Types
The F2MC-16LX has the following two addressing modes:
● Linear addressing
An entire 24-bit address is specified by an instruction.
● Bank addressing
The eight high-order bits of an address are specified by an appropriate bank register, and the remaining 16
low-order bits are specified by an instruction.
27
CHAPTER 2 CPU
2.3
Memory Space Map
The memory space of the MB90945 series is shown in Figure 2.3-1.
■ Memory Space Map
The ROM data in the high-order portion of FF bank can be seen as an image in the higher 00 bank in order
to support the small model C compiler. Since the low-order 16 bits are identical, this part of the ROM data
can be referenced without using the far specification in the pointer declaration.
For example, when 00C000H is accessed, the contents of ROM at FFC000H are read. However, since the
ROM area in the FF bank exceeds 48 Kbytes (resp. 32 Kbytes for MB90V390HA/HB and MB90F946A),
its entire image cannot be mirrored in the 00 bank.
On MB90947A, MB90F947(A) and MB90F949(A), the image between FF4000H / FF8000H* and
FFFFFFH is visible in 00 bank, whereas the data between FF0000H and FF3FFFH / FF7FFFH* is only
visible in FF bank.
On MB90F946A and MB90V390HA/HB, the image between FF8000H and FFFFFFH is visible in 00 bank,
whereas the data between FF0000H and FF7FFFH is only visible in FF bank.
*: Can be selected by MS bit in ROM register (see Chapter 24.2)
28
CHAPTER 2 CPU
Figure 2.3-1 Memory Space Map
MB90947A
MB90V390HA
MB90V390HB
FFFFFFH
FF0000 H
FEFFFFH
FE0000 H
FDFFFFH
FD0000 H
FCFFFFH
FC0000 H
FBFFFFH
FB0000 H
FAFFFFH
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
800000 H
00FFFFH
008000 H
0070FF H
FFFFFFH
FF0000 H
FEFFFFH
FE0000 H
FDFFFFH
FD0000 H
ROM (FF bank)
ROM (FE bank)
FFFFFF H
FF0000 H
FEFFFFH
FE0000 H
MB90F947
MB90F949
MB90F947A
MB90F949A
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
FBFFFF H
FB0000 H
FAFFFFH
FA0000 H
F9FFFF H
F90000 H
FFFFFF H
FF0000 H
FEFFFF H
FE0000 H
FDFFFF H
FD0000 H
FCFFFF H
ROM (FC bank)
FA0000 H
F9FFFFH
F90000 H
8017FF H
MB90F946A
FC0000 H
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
ROM (F9 bank)
RAM 6 Kbytes
ROM (Image of
FF bank)
00FFFF H
008000 H
ROM (Image of
FF bank)
00FFFF H
ROM (Image of
004000 H /
FF bank)
008000 H
00FFFF H
004000 H /
008000 H
ROM (Image of
FF bank)
RAM 12 Kbytes
004100 H
0050FF H
004100 H
003FFF H
003FFF H
003500 H
0030FF H
Peripheral
003500 H
0030FF H
RAM 12 Kbytes
000100 H
0000BFH
000000 H
RAM 4 Kbytes
Peripheral
RAM 12 Kbytes
0000BF H
000000 H
003500 H
Peripheral
003500 H
Peripheral
0030FF H
0018FF H
000100 H
000100 H
Peripheral
003FFF H
003FFF H
Peripheral
0000BF H
000000 H
RAM 12 Kbytes
RAM 6 Kbytes
Peripheral
000100 H
0000BF H
000000 H
Peripheral
: No access
29
CHAPTER 2 CPU
2.4
Linear Addressing
There are two types of linear addressing:
• 24-bit operand specification: Directly specifies a 24-bit address using operands.
• 32-bit register indirect specification: Indirectly specifies the 24 low-order bits of a 32bit general-purpose register value as the
address.
■ 24-bit Operand Specification
Figure 2.4-1 shows an example of 24-bit operand specification. Figure 2.4-2 shows an example of 32-bit
register indirect specification.
Figure 2.4-1 Example of Linear Method (24-bit Operand Specification)
JMPP 123456 H
Old program counter +
program bank
17
17452D H
452D
JMPP 123456 H
123456 H
New program counter +
program bank
12
Next instruction
3456
Figure 2.4-2 Example of Linear Method (32-bit Register Indirect Specification)
MOV A, @RL1+7
Old AL
090700 H
XXXX
3A
+7
RL1
(The high-order eight bits are ignored.)
New AL
30
003A
240906F9
CHAPTER 2 CPU
2.5
Bank Addressing Types
In the bank method, the 16-Mbyte space is divided into 256 64 Kbytes banks. The
following five bank registers are used to specify the banks corresponding to each
space:
• Program counter bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional data bank register (ADB)
■ Bank Addressing Types
● Program counter bank register (PCB)
The 64 Kbytes bank specified by the PCB is called a program (PC) space. The PC space contains
instruction codes, vector tables, and immediate value data, for example.
● Data bank register (DTB)
The 64 Kbytes bank specified by the DTB is called a data (DT) space. The DT space contains readable/
writable data, and control/data registers for internal and external resources.
● User stack bank register (USB)/system stack bank register (SSB)
The 64 Kbytes bank specified by the USP or SSP is called a stack (SP) space. The SP space is accessed
when a stack access occurs during a push/pop instruction or interrupt register saving. The S flag in the
condition code register determines the stack space to be accessed.
● Additional data bank register (ADB)
The 64 Kbytes bank specified by the ADB is called an additional (AD) space. The AD space, for example,
contains data that cannot fit into the DT space.
Table 2.5-1 lists the default spaces used in each addressing mode, which are pre-determined to improve
instruction coding efficiency. To use a non-default space for an addressing mode, specify a prefix code
corresponding to a bank before the instruction. This enables access to the bank space corresponding to the
specified prefix code.
After reset, the DTB, USB, SSB, and ADB are initialized to 00H. The PCB is initialized to a value specified
by the reset vector. After reset, the DT, SP, and AD spaces are allocated in bank 00H (000000H to
00FFFFH), and the PC space is allocated in the bank specified by the reset vector.
31
CHAPTER 2 CPU
Table 2.5-1 Default Space
Default space
Program space
Addressing mode
PC indirect, program access, branch
Data space
Addressing mode using @RW0, @RW1, @RW4, or @RW5, @A, addr16, and dir
Stack space
Addressing mode using PUSHW, POPW, @RW3, or @RW7
Additional space
Addressing mode using @RW2 or @RW6
Figure 2.5-1 shows an example of a memory space divided into register banks.
Figure 2.5-1 Physical Addresses of Each Space
FFFFFF H
Program space
FF0000 H
FF H
:
PCB (Program counter bank register)
B3 H
: ADB (Additional data bank register)
92 H
: USB (User stack bank register)
68 H
: DTB (Data bank register)
4B H
: SSB (System stack bank register)
B3FFFF H
Additional space
Physical address
B30000 H
92FFFF H
User stack space
920000 H
68FFFF H
680000 H
Data space
4BFFFF H
System stack space
4B0000 H
000000 H
32
CHAPTER 2 CPU
2.6
Multi-Byte Data in Memory Space
Data is written to memory from the low-order addresses. Therefore, for a 32-bit data
item, the low-order 16 bits are transferred before the high-order 16 bits.
If a reset signal is input immediately after the low-order bits are written, the high-order
bits might not be written.
■ Multi-byte Data Allocation in Memory Space
Figure 2.6-1 shows a sample allocation of multi-byte data in memory. The low-order eight bits of a data
item are stored at address n, then address n+1, address n+2, address n+3, etc.
Figure 2.6-1 Sample Allocation of Multi-byte Data in Memory
MSB
"H"
LSB
01010101
11001100
11111111
00010100
01010101
11001100
11111111
Address n
00010100
"L"
■ Accessing Multi-byte Data
Fundamentally, accesses are made within a bank. For an instruction accessing a multi-byte data item,
address FFFFH is followed by address 0000H of the same bank. Figure 2.6-2 shows an example of an
instruction accessing multi-byte data.
Figure 2.6-2 Execution of MOVW A, 080FFFFH
"H"
80FFFF H
AL before execution
??
AL after execution
23 H
??
01H
·
·
·
23 H
800000 H
01H
"L"
33
CHAPTER 2 CPU
2.7
Registers
The F2MC-16LX registers are largely classified into two types: special registers in the
CPU and general-purpose registers in memory. The special registers are dedicated
internal hardware of the CPU, and they have specific use defined by the CPU
architecture. The general-purpose registers share the CPU address space with RAM.
The general-purpose registers are the same as the special registers in that they can be
accessed without using an address. The applications of the general-purpose registers
can be specified by the user however, as is ordinary memory space.
■ Special Registers
The F2MC-16LX CPU core has the following special registers:
• Accumulator (A=AH:AL): Two 16-bit accumulators (Can be used as a single 32-bit accumulator.)
• User stack pointer (USP): 16-bit pointer indicating the user stack area
• System stack pointer (SSP): 16-bit pointer indicating the system stack area
• Processor status (PS): 16-bit register indicating the system status
• Program counter (PC): 16-bit register holding the address of the program
• Program counter bank register (PCB): 8-bit register indicating the PC space
• Data bank register (DTB): 8-bit register indicating the DT space
• User stack bank register (USB): 8-bit register indicating the user stack space
• System stack bank register (SSB): 8-bit register indicating the system stack space
• Additional data bank register (ADB): 8-bit register indicating the AD space
• Direct page register (DPR): 8-bit register indicating a direct page
Figure 2.7-1 shows a diagram of the special registers.
Figure 2.7-1 Special Registers
AH
AL
Accumulator
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
DPR
Direct page register
PCB
Program counter bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8 bit
16 bit
32 bit
34
CHAPTER 2 CPU
■ General-purpose Registers
The F2MC-16LX general-purpose registers are located from addresses 000180H to 00037FH (maximum
configuration) of main storage. The register bank pointer (RP) indicates which of the above addresses is
currently being used as a register bank. Each bank has the following three types of registers. These registers
are mutually dependent as described in Figure 2.7-2.
• R0 to R7: 8-bit general-purpose register
• RW0 to RW7: 16-bit general-purpose register
• RL0 to RL3: 32-bit general-purpose register
Figure 2.7-2 General-purpose Registers
MSB
LSB
16 bit
000180 H + RP 10 H
RW0
Low-order
RL0
First address of
general-purpose register
RW1
RW2
RL1
RW3
R1
R0
RW4
R3
R2
RW5
R5
R4
RW6
R7
R6
RW7
RL2
RL3
High-order
The relationship between the high-order and low-order bytes of a byte or word register is expressed as
follows:
RW (i+4) = R (i×2+1) × 256+R (i×2) [i=0 to 3]
The relationship between the high-order and low-order bytes of RLi and RWi is expressed as follows:
RL (i) = RW (i×2+1) × 65536+RW (i×2) [i=0 to 3]
35
CHAPTER 2 CPU
2.7.1
Accumulator (A)
The accumulator (A) register consists of two 16-bit arithmetic operation registers (AH
and AL), and is used as a temporary storage for operation results and transfer data.
■ Accumulator (A)
The A register consists of two 16-bit arithmetic operation registers (AH and AL). The A register is used as
a temporary storage for operation results and transfer data. During 32-bit data processing, AH and AL are
used together. Only AL is used for word processing in 16-bit data processing mode or for byte processing
in 8-bit data processing mode (see Figure 2.7-3 and Figure 2.7-4). The data stored in the A register can be
operated upon with the data in memory or registers (Ri, RWi, and RLi). In the same manner as with the
F2MC-8L, when a word or shorter data item is transferred to AL, the previous data item in AL is
automatically sent to AH (data preservation function). The data preservation function and operation
between AL and AH help improve processing efficiency.
When a byte or shorter data item is transferred to AL, the data is sign-extended or zero-extended and stored
as a 16-bit data item in AL. The data in AL can be handled either as word or byte long.
When a byte-processing arithmetic operation instruction is executed on AL, the high-order eight bits of AL
before operation are ignored. The high-order eight bits of the operation result all become zeroes.
The A register is not initialized by a reset. The A register holds an undefined value immediately after a
reset.
Figure 2.7-3 32-bit Data Transfer
MO VL A,@R W1+6
Old A
XXXX H
MSB
XXXX H
A6 H
DTB
New A
8F74 H
AH
LSB
A61540 H
8F H
74 H
A6153E H
2B H
52 H
15 H
38 H
+6
2B52 H
RW1
AL
Figure 2.7-4 AL-AH Transfer
MSB
MO VW A,@R W1+6
Old A
XXXX H
1234 H
DTB
New A
36
1234 H
1234 H
A6 H
LSB
A61540 H
8F H
74 H
A6153E H
2B H
52 H
15 H
38 H
+6
RW1
CHAPTER 2 CPU
2.7.2
User Stack Pointer (USP) and System Stack Pointer
(SSP)
USP and SSP are 16-bit registers that indicate the memory addresses for saving and
restoring data when a push/pop instruction or subroutine is executed.
■ User Stack Pointer (USP) and System Stack Pointer (SSP)
USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data in the
event of a push/pop instruction or subroutine execution. The USP and SSP registers are used by stack
instructions. The USP register is enabled when the S flag in the processor status register is "0", and the SSP
register is enabled when the S flag is "1" (see Figure 2.7-5). Since the S flag is set when an interrupt is
accepted, register values are always saved in the memory area indicated by SSP during interrupt
processing. SSP is used for stack processing in an interrupt routine, while USP is used for stack processing
outside an interrupt routine. If the stack space is not divided, use only the SSP.
During stack processing, the high-order eight bits of an address are indicated by SSB (for SSP) or USB (for
USP). USP and SSP are not initialized by a reset. Instead, they hold undefined values.
Figure 2.7-5 Stack Manipulation Instruction and Stack Pointer
Example 1 PUSHW A when the S flag is "0"
Before execution
AL
S flag
After execution
AL
MSB
C6F326 H
LSB
A624 H
USB
C6 H
USP
F328 H
0
SSB
56 H
SSP
1234 H
A624 H
USB
C6 H
USP
F326 H
0
SSB
56 H
SSP
1234 H
C6F326 H
A6 H
24 H
A624 H
USB
C6 H
USP
F328 H
561232 H
XX
XX
1
SSB
56 H
SSP
1234 H
A624 H
USB
C6 H
USP
F328 H
561232 H
A6 H
24 H
1
SSB
56 H
SSP
1232 H
XX
XX
User stack is used because
the S flag is "0".
Example 2 PUSHW A when the S flag is "1"
AL
AL
System stack is used because
the S flag is "1".
Note:
Specify an even-numbered address in the stack pointer whenever possible.
37
CHAPTER 2 CPU
2.7.3
Processor Status (PS)
The PS register consists of the bits controlling the CPU Operation and the bits
indicating the CPU status.
■ Processor Status (PS)
As shown in Figure 2.7-6, the high-order byte of the PS register consists of a register bank pointer (RP) and
an interrupt level mask register (ILM). The RP indicates the start address of a register bank. The low-order
byte of the PS register is a condition code register (CCR), containing the flags to be set or reset depending
on the results of instruction execution or interrupt occurrences.
Figure 2.7-6 Processor Status (PS) Structure
bit15
PS
bit13 bit12
bit0
bit8 bit7
ILM
RP
CCR
■ Condition Code Register (CCR)
Figure 2.7-7 shows a diagram of condition code register configuration.
Figure 2.7-7 Condition Code Register (CCR) Configuration
Initial value
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
I
S
T
N
Z
V
C
-
0
1
*
*
*
*
*
: CCR
*: Undefined
● I: Interrupt enable flag:
Interrupts other than software interrupts are enabled when the I flag is "1" and are masked when the I flag is
"0". The I flag is cleared by a reset.
● S: Stack flag:
When the S flag is "0", USP is enabled as the stack manipulation pointer.
When the S flag is "1", SSP is enabled as the stack manipulation pointer.
The S flag is set by an interrupt reception or a reset.
38
CHAPTER 2 CPU
● T: Sticky bit flag:
"1" is set in the T flag when there is at least one "1" in the data shifted out from the carry after execution of
a logical right/arithmetic right shift instruction. Otherwise, "0" is set in the T flag. In addition, "0" is set in
the T flag when the shift amount is zero.
● N: Negative flag:
The "1" is set in the N flag when the MSB of the operation result is "1". In other cases, N flag is cleared.
● Z: Zero flag:
The Z flag is set when the operation result is all zeroes. In other cases, Z flag is cleared.
● V: Overflow flag:
The V flag is set when an overflow of a signed value occurs as a result of operation execution. In other
cases, V flag is cleared.
● C: Carry flag:
The C flag is set when a carry-up or carry-down from the MSB occurs as a result of operation execution. In
other cases, C flag is cleared.
■ Register Bank Pointer (RP)
The RP register indicates the relationship between the general-purpose registers of the F2MC-16LX and the
internal RAM addresses. Specifically, the RP register indicates the first memory address of the currently
used register bank in the following conversion expression: [00180H + (RP) × 10H] (see Figure 2.7-8). The
RP register consists of five bits, and can take a value between 00H and 1FH. Register banks can be allocated
at addresses from 000180H to 00037H in memory.
Even within that range, however, the register banks cannot be used as general-purpose registers if the banks
are not in internal RAM. The RP register is initialized to all zeroes by a reset. An instruction may transfer
an eight-bit immediate value to the RP register; however, only the low-order five bits of that data are used.
Figure 2.7-8 Register Bank Pointer (RP)
Initial value
B4
B3
B2
B1
0
0
0
0
B0
: RP
0
39
CHAPTER 2 CPU
■ Interrupt Level Mask Register (ILM)
The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt request is
accepted only when the interrupt level is higher than that indicated by these three bits. Level 0 is the
highest priority interrupt, and level 7 is the lowest priority interrupt (see Table 2.7-1). Therefore, for an
interrupt to be accepted, its level value must be smaller than the current ILM value. When an interrupt is
accepted, the level value of that interrupt is set in ILM. Thus, an interrupt of the same or lower level cannot
be accepted subsequently. ILM is initialized to all zeroes by a reset. An instruction may transfer an eight-bit
immediate value to the ILM register, but only the low-order three bits of that data are used.
Figure 2.7-9 Interrupt Level Register (ILM)
Initial value
ILM2
ILM1
ILM0
0
0
0
: ILM
Table 2.7-1 Levels Indicated by the Interrupt Level Mask (ILM) Register
40
ILM2
ILM1
ILM0
Level value
Acceptable interrupt level
0
0
0
0
Interrupt disabled
0
0
1
1
0 only
0
1
0
2
Level value smaller than 1
0
1
1
3
Level value smaller than 2
1
0
0
4
Level value smaller than 3
1
0
1
5
Level value smaller than 4
1
1
0
6
Level value smaller than 5
1
1
1
7
Level value smaller than 6
CHAPTER 2 CPU
2.7.4
Program Counter (PC)
The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory
address of an instruction code to be executed by the CPU. The high-order eight bits of
the address are indicated by the PCB. The PC register is updated by a conditional
branch instruction, subroutine call instruction, interrupt, or reset.
The PC register can also be used as a base pointer for operand access.
■ Program Counter (PC)
Figure 2.7-10 shows the program counter.
Figure 2.7-10 Program Counter
PCB
FE H
PC
ABCD H
Next instruction to be executed
FEABCD H
41
CHAPTER 2 CPU
2.8
Register Bank
A register bank consists of eight words. The register bank can be used as the following
general-purpose registers for arithmetic operations: byte registers R0 to R7, word
registers RW0 to RW7, and long word registers RL0 to RL3. In addition, the register
bank can be used as instruction pointers.
■ Register Bank
Table 2.8-1 lists the register functions. Table 2.8-2 indicates the relationship between the registers.
In the same manner as for an ordinary RAM area, the register bank values are not initialized by a reset. The
status before a reset is maintained. When the power is turned-on, however, the register bank will have an
undefined value.
Table 2.8-1 Register Functions
R0 to R7
Used as operands of instructions.
Note: R0 is also used as a counter for barrel shift or normalization instructions.
RW0 to RW7
Used as pointers.
Used as operands of instructions.
Note: RW0 is used as a counter for string instructions.
RL0 to RL3
Used as long pointers.
Used as operands of instructions.
Table 2.8-2 Relationship between Registers
RW0
RL0
RW1
RW2
RL1
RW3
R0
RW4
R1
RL2
R2
RW5
R3
R4
RW6
R5
RL3
R6
RW7
R7
42
CHAPTER 2 CPU
● Direct page register (DPR) <Initial value: 01H>
DPR specifies addr8 to addr15 of the instruction operands in direct addressing mode as shown in Figure
2.8-1. DPR is eight bits long, and is initialized to 01H by a reset. DPR can be read or written to by an
instruction.
Figure 2.8-1 Generating a Physical address in Direct Addressing Mode
DTB register
DPR register
Direct address during instruction
αααααααα
ββββββββ
γγγγγγγγ
LSB
MSB
24-bit physical
address
ααααααααββββββββγγγγγγγγ
● Program counter bank register (PCB) <Initial value: Value in reset vector>
● Data bank register (DTB) <Initial value: 00H>
● User stack bank register (USB) <Initial value: 00H>
● System stack bank register (SSB) <Initial value: 00H>
● Additional data bank register (ADB) <Initial value: 00H>
Each bank register indicates the memory bank where the PC, DT, SP (user), SP (system), or AD space is
allocated. All bank registers are one byte long. PCB is initialized to 00H by a reset. Bank registers other
than PCB can be read or written to. PCB can be read but cannot be written to.
PCB is updated when the JMPP, CALLP, RETP, RETIQ, or RETF instruction branching to the entire 16Mbyte space is executed or when an interrupt occurs. For operation of each register, see Section "2.2
Memory Space".
43
CHAPTER 2 CPU
2.9
Prefix Codes
Placing a prefix code before an instruction partially changes the operation of the
instruction. Three types of prefix codes can be used: bank select prefix, common
register bank prefix, and flag change disable prefix.
■ Bank Select Prefix
The memory space used for accessing data is determined for each addressing mode.
When a bank select prefix is placed before an instruction, the memory space used for accessing data by that
instruction can be selected regardless of the addressing mode.
Table 2.9-1 lists the bank select prefixes and the corresponding memory spaces.
Table 2.9-1 Bank Select Prefix
Bank select prefix
Space selected
PCB
PC space
DTB
Data space
ADB
AD space
SPB
Either the SSP or USP space is used according to the stack flag value.
Use the following instructions with care:
● String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW)
The bank register specified by an operand is used regardless of the prefix.
● Stack manipulation instructions (PUSHW, POPW)
SSB or USB is used according to the S flag regardless of the prefix.
● I/O access instructions
MOV A, io / MOV io, A /MOVX A, io / MOVW A, io /MOVW io, A / MOV io, #imm8
MOV io, #imm16 / MOVB A, io:bp / MOB io:bp, A /SETB io:bp / CLRB io:bp
BBC io:bp, rel / BBS io:bp, rel WBTC, WBTS
The I/O space of the bank is used regardless of the prefix.
● Flag change instructions (AND CCR,#imm8, OR CCR,#imm8)
The instruction is executed normally, but the prefix affects the next instruction.
● POPW PS
SSB or USB is used according to the S flag regardless of the prefix. The prefix affects the next instruction.
● MOV ILM,#imm8
The instruction is executed normally, but the prefix affects the next instruction.
44
CHAPTER 2 CPU
● RETI
SSB is used regardless of the prefix.
■ Common Register Bank Prefix (CMR)
To simplify data exchange between multiple tasks, the same register bank must be accessed relatively
easily regardless of the RP value. When CMR is placed before an instruction that accesses a register bank,
that instruction accesses the common bank (the register bank selected when RP=0) at addresses from
000180H to 00018FH regardless of the current RP value. Use the following instructions with care:
● String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW)
If an interrupt request occurs during execution of a string instruction with a prefix code, the prefix code
becomes invalid when the string instruction is resumed after the interrupt is processed. Thus, the string
instruction is executed falsely after the interrupt is processed. Do not prefix any of the above string
instructions with CMR.
● Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS)
The instruction is executed normally, but the prefix affects the next instruction.
● MOV ILM,#imm8
The instruction is executed normally, but the prefix affects the next instruction.
■ Flag Change Disable Prefix (NCC)
To disable flag changes, use the flag change disable prefix code (NCC). Placing NCC before an instruction
disables flag changes associated with that instruction. Use the following instructions with care:
● String instructions (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW)
If an interrupt request occurs during execution of a string instruction with a prefix code, the prefix code
becomes invalid when the string instruction is resumed after the interrupt is processed. Thus, the string
instruction is executed incorrectly after the interrupt is processed. Do not prefix any of the above string
instructions with NCC.
● Flag change instructions (AND CCR,#imm8, OR CCR,#imm8, POPW PS)
The instruction is executed normally, but the prefix affects the next instruction.
● Interrupt instructions (INT #vct8, INT9, INT addr16, INTP addr24, RETI)
CCR changes according to the instruction specifications regardless of the prefix.
● JCTX @A
CCR changes according to the instruction specifications regardless of the prefix.
● MOV ILM,#imm8
The instruction is executed normally, but the prefix affects the next instruction.
45
CHAPTER 2 CPU
2.10
Interrupt Disable Instructions
Interrupt requests are not sampled for the following ten instructions:
- MOV ILM,#imm8
- PCB
- SPB
- OR
CCR,#imm8
- NCC
- AND CCR,#imm8
- ADB
- CMR
- POPW PS
- DTB
■ Interrupt Disable Instructions
If a valid interrupt request occurs during execution of any of the above instructions, the interrupt can be
processed only when an instruction other than the above is executed. For details, see Figure 2.10-1.
Figure 2.10-1 Interrupt Disable Instructions
Interrupt disable instruction
••••••••
(a)
•••
(a) Ordinary
instruction
Interrupt request
Interrupt acceptance
■ Restrictions on Interrupt Disable Instructions and Prefix Instructions
When a prefix code is placed before an interrupt disable instruction, the prefix code affects the first
instruction after the code other than the interrupt disable instruction. For details, see Figure 2.10-2.
Figure 2.10-2 Interrupt Disable Instructions and Prefix Codes
Interrupt disable instruction
MOV A, FF H
NCC
••••
MOV ILM,#imm8
ADD A,01 H
CCR:XXX10XX
CCR:XXX10XX
CCR does not change with NCC.
■ Consecutive Prefix Codes
When competitive prefix codes are placed consecutively, the latter becomes valid.
In the figure below, competitive prefix codes are PCB, ADB, DTB, and SPB. For details, see Figure 2.10-3.
Figure 2.10-3 Consecutive Prefix Codes
Prefix code
•••••
ADB
DTB
PCB
ADD A,01H
••••
PCB is valid as the prefix code
46
CHAPTER 2 CPU
2.11
Precautions for Use of "DIV A, Ri" and "DIVW A, RWi"
Instructions
Set "00H" in the bank register before using the "DIV A, Ri" and "DIVW A, RWi"
instructions.
■ Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions
Table 2.11-1 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions (i = 0 to 7)
Instruction
DIV A, R0
Bank register affected
by the execution of the
instructions listed on the
left
DTB
Address that stores the remainder
(DTB: Upper 8 bits) + (0180H + RP x 10H + 8H : Lower 16 bits)
DIV A, R1
(DTB: Upper 8 bits) + (0180H + RP x 10H + 9H : Lower 16 bits)
DIV A, R4
(DTB: Upper 8 bits) + (0180H + RP x 10H + CH : Lower 16 bits)
DIV A, R5
(DTB: Upper 8 bits) + (0180H + RP x 10H + DH : Lower 16 bits)
DIVW A, RW0
(DTB: Upper 8 bits) + (0180H + RP x 10H + 0H : Lower 16 bits)
DIVW A, RW1
(DTB: Upper 8 bits) + (0180H + RP x 10H + 2H : Lower 16 bits)
DIVW A, RW4
(DTB: Upper 8 bits) + (0180H + RP x 10H + 8H : Lower 16 bits)
DIVW A, RW5
(DTB: Upper 8 bits) + (0180H + RP x 10H + AH : Lower 16 bits)
DIV A, R2
ADB
(ADB: Upper 8 bits) + (0180H + RP x 10H + AH : Lower 16 bits)
DIV A, R6
(ADB: Upper 8 bits) + (0180H + RP x 10H + EH : Lower 16 bits)
DIVW A, RW2
(ADB: Upper 8 bits) + (0180H + RP x 10H + 4H : Lower 16 bits)
DIVW A, RW6
(ADB: Upper 8 bits) + (0180H + RP x 10H + EH : Lower 16 bits)
DIV A, R3
USB
SSB *1
(USB *2: Upper 8 bits) + (0180H + RP x 10H + BH : Lower 16 bits)
DIV A, R7
(USB *2: Upper 8 bits) + (0180H + RP x 10H + FH : Lower 16 bits)
DIVW A, RW3
(USB *2: Upper 8 bits) + (0180H + RP x 10H + 6H : Lower 16 bits)
DIVW A, RW7
(USB *2: Upper 8 bits) + (0180H + RP x 10H + EH : Lower 16 bits)
*1: Depends on the S bit of the CCR register.
*2: In the event that the S bit of the CCR register is zero
If the value of the bank registers (DTB, ADB, USB, and SSB) is "00H", the remainder after division is
stored in the register of the instruction operands. Otherwise, the upper eight bits is specified by the bank
register corresponding to the register of the instruction operand, and the lower 16 bits is the same as the
address of the register of the instruction operand. The remainder is stored in the bank register specified by
the upper eight bits.
47
CHAPTER 2 CPU
Example:
If "DIV A,R0" is executed with DTB = "053H" and RP = "03H", the address of R0 is "0180H" + RP
("03H") x "10H" + "08H" (R0 corresponding address) = "0001B8H". Since the data bank register (DTB)
is specified by "DIV A,R0" as the bank register, the remainder is stored in address "05301B8H", which
was obtained by adding the bank address "053H".
Note:
For information about the bank register and Ri and RWi registers, see Section "2.7 Registers".
■ Use of the "DIV A, Ri" and "DIVW A, RWi" Instructions without Precautions
To enable users to develop programs without having to take precautions for using the "DIV A,Ri" and
"DIVW A,RWi" instructions, special compilers and assemblers are available. The special compiler does not
generate the instructions in Table 2.11-1. The special assemblers have a function that replaces the
instructions in Table 2.11-1 with equivalent instruction strings. For the MB90945 series, use the following
types of compilers and assemblers:
● Compiler
cc907 V02L06 or later, or fcc907s V30L02 or later
● Assembler
asm907a V03L04 or later, or fasm907s V30L04 (Rev. 300004) or later
48
CHAPTER 3
INTERRUPTS
This chapter explains the functions and operations of
the interrupt.
3.1 Outline of Interrupts
3.2 Interrupt Vector
3.3 Interrupt Control Registers (ICR)
3.4 Interrupt Flow
3.5 Hardware Interrupts
3.6 Software Interrupts
3.7 Extended Intelligent I/O Service (EI2OS)
3.8 Operation Flow of and Procedure for Using the Extended Intelligent
I/O Service (EI2OS)
3.9 Exceptions
49
CHAPTER 3 INTERRUPTS
3.1
Outline of Interrupts
The F2MC-16LX has interrupt functions that terminate the currently executing
processing and transfer control to another specified program when a specified event
occurs. There are four types of interrupt functions:
• Hardware interrupt: Interrupt processing due to an internal resource event
• Software interrupt: Interrupt processing due to a software event occurrence
instruction
• Extended intelligent I/O service (EI2OS): Transfer processing due to an internal
resource event
• Exception: Termination due to an operation exception
■ Hardware Interrupts
A hardware interrupt is activated by an interrupt request from an internal resource. A hardware interrupt
request occurs when both the interrupt request flag and the interrupt enable flag in an internal resource are
set. Therefore, an internal resource must have an interrupt request flag and interrupt enable flag to issue a
hardware interrupt request.
● Specifying an interrupt level
An interrupt level can be specified for the hardware interrupt. To specify an interrupt level, use
the level setting bits (IL0, IL1, and IL2) of the interrupt controller.
● Masking a hardware interrupt request
A hardware interrupt request can be masked by using the I flag of the processor status register
(PS) in the CPU and the ILM bits. When an unmasked interrupt request occurs, the CPU saves 12
bytes of data that consists of registers PS, PC, PCB, DTB, ADB, DPR, and A in the memory area
indicated by the SSB and SSP registers.
■ Software Interrupts
Interrupts requested by executing the INT instruction are software interrupts. An interrupt request by the
INT instruction does not have an interrupt request or enable flag. An interrupt request is issued always by
executing the INT instruction.
No interrupt level is assigned to the INT instruction. Therefore, ILM is not updated when the INT
instruction is used. Instead, the I flag is cleared and the continuing interrupt requests are suspended.
50
CHAPTER 3 INTERRUPTS
■ Extended Intelligent I/O Service (EI2OS)
The extended intelligent I/O service automatically transfers data between an internal resource and memory.
This processing is traditionally performed by an interrupt processing program, but the EI2OS enables data
to be transferred in a manner similar to a DMA (direct memory access) operation.
To activate the extended intelligent I/O service function from an internal resource, the interrupt control
register (ICR) of the interrupt controller must have an extended intelligent I/O service enable flag (ISE).
The extended intelligent I/O service is started when an interrupt request occurs with "1" specified in the
ISE flag. To generate a normal interrupt using a hardware interrupt request, set the ISE flag to "0".
■ Exceptions
Exception processing is basically the same as interrupt processing. When an exception is detected between
instructions, exception processing is performed. In general, exception processing occurs as a result of an
unexpected operation. Therefore, use exception processing only for debugging programs or for activating
recovery software in an emergency.
51
CHAPTER 3 INTERRUPTS
3.2
Interrupt Vector
An interrupt vector uses the same area for both hardware and software interrupts. For
example, interrupt request number INT42 is used for a delayed hardware interrupt and
for software interrupt INT #42. Therefore, the delayed interrupt and INT #42 call the
same interrupt processing routine. Interrupt vectors are allocated between addresses
FFFC00H and FFFFFFH as shown in Table 3.2-1.
■ Interrupt Vector
Table 3.2-1 Interrupt Vectors (1 / 2)
Interrupt
request
Interrupt cause
Interrupt control
register
Number
Address
Vector
address L
Vector
address H
Vector
address
bank
Mode
register
INT 0 *
-
-
-
FFFFFCH
FFFFFDH
FFFFFEH
Unused
INT 1 *
-
-
-
FFFFF8H
FFFFF9H
FFFFFAH
Unused
.
.
.
-
-
-
.
.
.
.
.
.
.
.
.
.
.
.
INT 7 *
-
-
-
FFFFE0H
FFFFE1H
FFFFE2H
Unused
INT 8
Reset
-
-
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDFH
INT 9
INT9 instruction
-
-
FFFFD8H
FFFFD9H
FFFFDAH
Unused
INT 10
Exception
-
-
FFFFD4H
FFFFD5H
FFFFD6H
Unused
INT 11
Timebase Timer
FFFFD0H
FFFFD1H
FFFFD2H
Unused
ICR00
0000B0H
FFFFCCH
FFFFCDH
FFFFCEH
Unused
FFFFC8H
FFFFC9H
FFFFCAH
Unused
FFFFC4H
FFFFC5H
FFFFC6H
Unused
FFFFC0H
FFFFC1H
FFFFC2H
Unused
FFFFBCH
FFFFBDH
FFFFBEH
Unused
FFFFB8H
FFFFB9H
FFFFBAH
Unused
FFFFB4H
FFFFB5H
FFFFB6H
Unused
FFFFB0H
FFFFB1H
FFFFB2H
Unused
FFFFACH
FFFFADH
FFFFAEH
Unused
FFFFA8H
FFFFA9H
FFFFAAH
Unused
FFFFA4H
FFFFA5H
FFFFA6H
Unused
INT 12
External Interrupt INT0 to
INT7
INT 13
ICR01
INT 14
INT 15
CAN 1 RX
ICR02
INT 16
CAN 1 TX/NS
INT 17
PPG 0/1
ICR03
INT 18
PPG 2/3
INT 19
PPG 4/5
ICR04
INT 20
PPG 6/7
INT 21
PPG 8/9
ICR05
INT 22
52
0000B1H
PPG A/B
0000B2H
0000B3H
0000B4H
0000B5H
CHAPTER 3 INTERRUPTS
Table 3.2-1 Interrupt Vectors (2 / 2)
Interrupt
request
INT 23
Interrupt cause
Number
Address
ICR06
0000B6H
16-bit Reload Timer 0
INT 24
INT 25
Interrupt control
register
Input Capture 0/1
ICR07
INT 26
Output Compare 0/1
INT 27
Input Capture 2/3
ICR08
INT 28
Output Compare 2/3
INT 29
Input Capture 4/5
ICR09
INT 30
I 2C
INT 31
A/D Converter
ICR10
INT 32
I/O Timer 0/1
INT 33
Serial I/O
ICR11
INT 34
INT 35
UART 0 TX
0000BAH
0000BBH
0000BCH
ICR13
INT 38
0000BDH
UART 3 RX
ICR14
INT 40
UART 3 TX
INT 41
Flash Memory
ICR15
INT 42
0000B9H
UART 0 RX
INT 37
INT 39
0000B8H
ICR12
INT 36
0000B7H
Delayed Interrupt
0000BEH
0000BFH
Vector
address L
Vector
address H
Vector
address
bank
Mode
register
FFFFA0H
FFFFA1H
FFFFA2H
Unused
FFFF9CH
FFFF9DH
FFFF9EH
Unused
FFFF98H
FFFF99H
FFFF9AH
Unused
FFFF94H
FFFF95H
FFFF96H
Unused
FFFF90H
FFFF91H
FFFF92H
Unused
FFFF8CH
FFFF8DH
FFFF8EH
Unused
FFFF88H
FFFF89H
FFFF8AH
Unused
FFFF84H
FFFF85H
FFFF86H
Unused
FFFF80H
FFFF81H
FFFF82H
Unused
FFFF7CH
FFFF7DH
FFFF7EH
Unused
FFFF78H
FFFF79H
FFFF7AH
Unused
FFFF74H
FFFF75H
FFFF76H
Unused
FFFF70H
FFFF71H
FFFF72H
Unused
FFFF6CH
FFFF6DH
FFFF6EH
Unused
FFFF68H
FFFF69H
FFFF6AH
Unused
FFFF64H
FFFF65H
FFFF66H
Unused
FFFF60H
FFFF61H
FFFF62H
Unused
FFFF5CH
FFFF5DH
FFFF5EH
Unused
FFFF58H
FFFF59H
FFFF5AH
Unused
FFFF54H
FFFF55H
FFFF56H
Unused
INT 43
-
-
-
FFFF50H
FFFF51H
FFFF52H
Unused
.
.
.
-
-
-
.
.
.
.
.
.
.
.
.
.
.
.
INT 254
-
-
-
FFFC04H
FFFC05H
FFFC06H
Unused
INT 255
-
-
-
FFFC00H
FFFC01H
FFFC02H
Unused
*: When PCB is FFH, the vector area for the CALLV instruction is the same as that for INT #vct8 (#0 to #7).
Care must be taken when using the vector for the CALLV instruction.
53
CHAPTER 3 INTERRUPTS
3.3
Interrupt Control Registers (ICR)
The interrupt control registers are in the interrupt controller. Each interrupt control
register has a corresponding I/O that has an interrupt function. The interrupt control
registers have the following three functions:
• Setting an interrupt level for corresponding peripherals
• Selecting whether to use an ordinary interrupt or extended intelligent I/O service for
the corresponding peripherals
• Selecting the extended intelligent I/O service channel
Do not access an interrupt control register by using a read-modify-write instruction, as
doing so causes a misoperation.
■ Interrupt Control Register (ICR)
Figure 3.3-1 shows the bit configuration of an interrupt control register.
Figure 3.3-1 Configuration of the Interrupt Control Register (ICR)
bit15/bit7 bit14/bit6 bit13/bit5 bit12/bit4 bit11/bit3
bit10/bit2
bit9/bit1
bit8/bit0
ICS1
or
S1
ICS0
or
S0
ISE
IL2
IL1
IL0
*
*
R/W
R/W
R/W
R/W
ICS3
ICS2
W
W
R/W: Readable/writable
W : Write only
*
: Always reads "1"
Initial value
00000111B
Note:
ICS3 to ICS0 are valid only when EI2OS is activated. Set "1" in ISE to activate EI2OS, and set "0" in
ISE not to activate it. When EI2OS is not to be activated, any value can be set in ICS3 to ICS0.
ICS1 and ICS0 are valid for write only. S1 and S0 are valid for read only.
54
CHAPTER 3 INTERRUPTS
[bit10 to bit8, bit2 to bit0] IL2 to IL0 (interrupt level setting bits)
These bits are readable and writable, and specify the interrupt level of the corresponding internal
resources. Upon a reset, these bits are initialized to level 7 (no interrupt). Table 3.3-1 describes the
relationship between the interrupt level setting bits and interrupt levels.
Table 3.3-1 Interrupt Level Setting Bits and Interrupt Levels
IL2
IL1
IL0
Level
0
0
0
0 (Strongest)
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6 (Weakest)
1
1
1
7 (No interrupt)
[bit11, bit3] ISE (extended intelligent I/O service enable bits)
These bits are readable and writable. In response to an interrupt request, EI2OS is activated when "1" is
set in the ISE bit and an interrupt sequence is activated when "0" is set in the ISE bit. Upon completion
of EI2OS, the ISE bit is cleared to "0". If the corresponding peripheral does not have the EI2OS
function, the ISE bit must be set to "0" on the software side.
The ISE bit is initialized to "0" by a reset.
55
CHAPTER 3 INTERRUPTS
[bit15 to bit12, bit7 to bit4] ICS 3 to ICS 0 (extended intelligent I/O service channel select bits)
These bits are write only. These bits specify the EI2OS channel. The values set in these bits determine
the intelligent I/O service descriptor addresses in memory, which is explained later. The ICS bits are
initialized by a reset.
Table 3.3-2 describes the correspondence between the ICS bits, channel numbers, and descriptor
addresses.
Table 3.3-2 ICS Bits, Channel Numbers, and Descriptor Addresses
56
ICS3
ICS2
ICS1
ICS0
Selected channel
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
CHAPTER 3 INTERRUPTS
[bit13, bit12, bit5, bit4] S0, S1 (extended intelligent I/O service status)
These bits are read only. The values set in these bits indicate the end condition of EI2OS. These bits are
initialized to "00B" by a reset.
Table 3.3-3 shows the relationship between the S bits and the end conditions.
Table 3.3-3 S Bits and End Conditions
S1
S0
End condition
0
0
EI2OS running or not activated
0
1
Termination by count
1
0
Reserved
1
1
Termination by request from resource
57
CHAPTER 3 INTERRUPTS
3.4
Interrupt Flow
Figure 3.4-1 shows the interrupt flow.
■ Interrupt Flow
Figure 3.4-1 Interrupt Flow
I
ILM
IF
IE
Flag in CCR
Level register in CPU
Internal resource interrupt request
Internal resource interrupt enable flag
ISE : EI 2 OS enable flag
IL : Internal resource interruptrequest level
S : Flag in CCR
I & IF & IE = 1
AND
ILM > IL
:
:
:
:
YES
NO
NO
YES
ISE = 1
Fetching and decoding
the next instruction
Saving PS, PC, PCB, DTB,
ADB, DPR, and A into the
stack of SSP, and setting ILM=IL
Executing the extended
intelligent I/O service
YES
INT instruction
NO
Executing an ordinary
instruction
NO
Completion of
string instruction
repetition
YES
Updating PC
58
Saving PS, PC, PCB, DTB, ADB,
DPR, and A into the stack of SSP,
and setting I=O and ILM=IL
S← 1
Fetching the interrupt vector
CHAPTER 3 INTERRUPTS
Figure 3.4-2 Register Saving during Interrupt Processing
Word (16 bits)
MSB
LSB
"H"
SSP (SSP value before interrupt)
AH
AL
DPR
ADB
DPB
PCB
PC
PS
"L"
SSP (SSP value after interrupt)
59
CHAPTER 3 INTERRUPTS
3.5
Hardware Interrupts
In response to an interrupt request signal from an internal resource, the CPU pauses
current program execution and transfers control to the interrupt processing program
defined by the user.
■ Hardware Interrupts
A hardware interrupt occurs when the relevant conditions are satisfied as a result of two operations:
Comparison between the interrupt request level and the value in the interrupt level mask register (ILM) of
PS in the CPU, and hardware reference to the I flag value of PS.
The CPU performs the following processing when a hardware interrupt occurs:
•
Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system
stack.
•
Sets ILM in the PS register. The currently requested interrupt level is automatically set.
•
Fetches the corresponding interrupt vector value and branches to the processing indicated by that value.
■ Structure of Hardware Interrupt
Hardware interrupts are handled by the following three sections:
● Internal resources
Interrupt enable and request bits: Used to control interrupt requests from resources.
● Interrupt controller
ICR: Assigns interrupt levels and determines the priority levels of simultaneously requested interrupts.
● CPU
I and ILM: Used to compare the requested and current interrupt levels and to identify the interrupt enable
status.
Microcode: Interrupt processing step
The status of these sections are indicated by the resource control registers for internal resources, the ICR
for the interrupt controller, and the CCR value for the CPU. To use a hardware interrupt, set the three
sections beforehand by using software.
The interrupt vector table referenced during interrupt processing is assigned to addresses FFFC00H to
FFFFFFH in memory. These addresses are shared with software interrupts.
60
CHAPTER 3 INTERRUPTS
3.5.1
Hardware Interrupt Operation
An internal resource with the hardware interrupt request function has an interrupt
request flag and interrupt enable flag. The interrupt request flag indicates whether an
interrupt request exists, and the interrupt enable flag indicates whether the relevant
internal resource requests an interrupt to the CPU. The interrupt request flag is set
when an event occurs that is unique to the internal resource. When the interrupt enable
flag indicates "enable", the resource issues an interrupt request to the interrupt
controller.
■ Hardware Interrupt Operation
When two or more interrupt requests are received at the same time, the interrupt controller compares the
interrupt levels (IL) in ICR, selects the request with the highest level (the smallest IL value), then reports
that request to the CPU. If multiple requests are at the same level, the interrupt controller selects the request
with the lowest interrupt number. The relationship between the interrupt requests and ICRs is determined
by the hardware.
The CPU compares the received interrupt level with the ILM in the PS register. If the interrupt level is
smaller than the ILM value and the I bit in the PS register is set to "1", the CPU activates the interrupt
processing microcode after completing the currently executing instruction. The CPU references the ISE bit
of the ICR in the interrupt controller at the beginning of the interrupt processing microcode to check that
the ISE bit is "0" (interrupt). If the ISE bit is "0", the CPU activates the interrupt processing body.
The interrupt processing body saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area
indicated by SSB and SSP, fetches three bytes of interrupt vector and loads them onto PC and PCB,
updates the ILM of PS to a level value of the received interrupt, sets the S flag, then performs branch
processing. As a result, the interrupt processing program defined by the user is executed next.
Figure 3.5-1 illustrates the flow from the occurrence of a hardware interrupt until there is no interrupt
request in the interrupt processing program.
61
CHAPTER 3 INTERRUPTS
3.5.2
Occurrence and Release of Hardware Interrupt
Figure 3.5-1 shows the processing flow from occurrence of a hardware interrupt to
release of the interrupt request in an interrupt processing program.
■ Occurrence and Release of Hardware Interrupt
Figure 3.5-1 Occurrence and Release of Hardware Interrupt
PS
IR
(6)
F2M C - 1 6 LX . C P U
Enable FF
AND
(7)
Check
Comparator
(5)
(4)
(3)
Peripheral
Cause FF
ILM
(2)
(1)
Interrupt level IL
Microcode
I
Level comparator
F2MC-16LX bus
Register file
Interrupt
controller
PS : Processor status
I
: Interrupt enable flag
ILM : Interrupt level mask register
IR : Instruction register
(1) An interrupt cause occurs in a peripheral.
(2) The interrupt enable bit in the peripheral is referenced. If an interrupt is enabled, the peripheral issues an
interrupt request to the interrupt controller.
(3) Upon reception of the interrupt request, the interrupt controller determines the priority levels of simultaneously
requested interrupts. Then, the interrupt controller transfers the interrupt level of the corresponding interrupt to
the CPU.
(4) The CPU compares the interrupt level requested by the interrupt controller with the ILM bit of the processor
status register.
(5) If the comparison shows that the requested level is higher than the current interrupt processing level, the I flag
value of the same processor status register is checked.
(6) If the check in step (5) shows that the I flag indicates interrupt enable status, the requested level is written to
the ILM bit. Interrupt processing is performed as soon as the currently executing instruction is completed, then
control is transferred to the interrupt processing routine.
(7) When the interrupt cause of step (1) is cleared by software in the user interrupt processing routine, the interrupt
request is completed.
The time required for the CPU to execute the interrupt processing in steps (6) and (7) is shown below.
Interrupt start: 24 + 6 × (Table 3.3-2 machine cycles)
Interrupt return: 15 + 6 × (Table 3.3-3 machine cycles) RETI instruction
Table 3.5-1 Compensation Values for Interrupt Processing Cycle Count
62
Address indicated by the stack pointer
Cycle count compensation value
Internal area, even-numbered address
0
Internal area, odd-numbered address
+2
CHAPTER 3 INTERRUPTS
3.5.3
Multiple interrupts
As a special case, no hardware interrupt request can be accepted while data is being
written to the I/O area. For MB90945 series, this includes the address ranges 000000H to
0000BFH, (3100H to 31FFH, 3300H to 33FFH), 3500H to 35FFH, (3700H to 37FFH), 3900H to
39FFH, (3B00H to 3BFFH, 3D00H to 3DFFH and 3F00H to 3FFFH). This is intended to
prevent the CPU from operating falsely because of an interrupt request issued while an
interrupt control register for a resource is being updated.
If an interrupt occurs during interrupt processing, a higher level interrupt is processed
first.
■ Multiple Interrupts
The F2MC-16LX CPU supports multiple interrupts. If an interrupt of a higher level occurs while another
interrupt is being processed, control is transferred to the high-level interrupt after the currently executing
instruction is completed. After processing of the high-level interrupt is completed, the original interrupt
processing is resumed. An interrupt of the same or lower level may be generated while another interrupt is
being processed. If this happens, the new interrupt request is suspended until the current interrupt
processing is completed, unless the ILM value or I flag is changed by an instruction. The extended
intelligent I/O service cannot be activated from multiple sources; while an extended intelligent I/O service
is being processed, all other interrupt requests or extended intelligent I/O service requests are suspended.
Figure 3.5-2 shows the order of the registers saved in the stack.
Figure 3.5-2 Registers Saved in Stack
Word (16 bits)
MSB
LSB
"H"
SSP (SSP value before interrupt)
AH
AL
DPR
ADB
DPB
PCB
PC
PS
SSP (SSP value after interrupt)
"L"
63
CHAPTER 3 INTERRUPTS
3.6
Software Interrupts
In response to execution of a special instruction, control is transferred from the
program currently executed by the CPU to the interrupt processing program defined by
the user. A software interrupt occurs whenever the software interrupt instruction is
executed.
■ Software Interrupts
The CPU performs the following processing when a software interrupt occurs:
•
Saves the values in the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers of the CPU to the system
stack.
•
Sets I in the PS register. Interrupts are automatically disabled.
•
Fetches the corresponding interrupt vector value, then branches to the processing indicated by that
value.
A software interrupt request issued by the INT instruction has no interrupt request or enable flag. A
software interrupt request is always issued by executing the INT instruction.
The INT instruction does not have an interrupt level. Therefore, the INT instruction does not update ILM.
The INT instruction clears the I flag to suspend subsequent interrupt requests.
■ Structure of Software Interrupts
Software interrupts are handled within the CPU:
CPU: Microcode: Interrupt processing step
■ List of Interrupt Vectors of MB90945 Series
Table D-1 lists the interrupt vectors of the MB90945 series.
As shown in Table D-1, software interrupts share the same interrupt vector area with hardware interrupts.
For example, interrupt request number INT 12 is used for external interrupt #0 to #7 of a hardware interrupt
as well as for INT #12 of a software interrupt. Therefore, external interrupt #0 and INT #12 call the same
interrupt processing routine.
■ Software Interrupt Operation
When the CPU fetches and executes the software interrupt instruction, the software interrupt processing
microcode is activated. The software interrupt processing microcode saves 12 bytes (PS, PC, PCB, DTB,
ADB, DPR, and A) to the memory area indicated by SSB and SSP. The microcode fetches three bytes of
interrupt vector and loads them onto PC and PCB, resets the I flag, and sets the S flag. Then, the microcode
performs branch processing. As a result, the interrupt processing program defined by the user application
program is executed next.
Figure 3.6-1 illustrates the flow from the occurrence of a software interrupt until there is no interrupt
request in the interrupt processing program.
64
CHAPTER 3 INTERRUPTS
F2MC-16LX bus
Figure 3.6-1 Occurrence and Release of Software Interrupt
Register
file
(2)
Microcode
(1)
PS
I
S
B unit
IR
F2M C - 1 6 LX. C P U
Queue
Fetch
Save
Instruction bus
RAM
PS : Processor status
I
: Interrupt enable flag
ILM : Interrupt level mask register
IR
: Instruction register
B unit: Bus interface unit
(1) The software interrupt instruction is executed.
(2) Special CPU registers in the register file are saved according to the microcode corresponding to the software
interrupt instruction.
(3) The interrupt processing is completed with the RETI instruction in the user interrupt processing routine.
■ Others
When the program counter bank register (PCB) is FFH, the CALLV instruction vector area overlaps the
table of the INT #vct8 instruction. When designing software, ensure that the CALLV instruction does not
use the same address as that of the #vct8 instruction.
Table D-2 shows the relationship of interrupt cause, interrupt vector, and interrupt control register in the
MB90945 series.
65
CHAPTER 3 INTERRUPTS
3.7
Extended Intelligent I/O Service (EI2OS)
The EI2OS function automatically transfers data between I/O and memory. An interrupt
processing program was conventionally used for such processing, but EI2OS enables
data transfer to be performed like DMA (direct memory access).
■ Extended Intelligent I/O Service (EI2OS)
EI2OS has the following advantages over the conventional method:
•
The program size can be reduced because it is not necessary to write a transfer programs not required.
•
High transfer speed is enabled by eliminating the need for saving register as no internal register is used
for transfer.
•
Transfer can be terminated by I/O, preventing unnecessary data from being transferred.
•
The buffer address may either be incremented or left unupdated.
•
The I/O register address may either be incremented or left unupdated.
At the end of EI2OS, processing automatically branches to an interrupt processing routine after the end
condition is set. Thus, the user can identify the end condition.
To implement EI2OS, the hardware is distributed in two blocks. Each block has the following registers and
descriptors.
•
Interrupt control register: Exists in the interrupt controller and indicates the ISD address.
•
Extended intelligent I/O service descriptor (ISD): Exists in RAM and holds the transfer mode, I/O
address, number of transfers, and buffer address.
Figure 3.7-1 outlines the extended intelligent I/O service.
66
CHAPTER 3 INTERRUPTS
Figure 3.7-1 Outline of Extended Intelligent I/O Service
Memory space
by IOA
I/O register
I/O register
Peripheral
CPU
Interrupt request (1)
(3)
(3)
ISD
by ICS
(2)
Interrupt control register
Interrupt controller
by BAP
(4)
Buffer
by
DCT
(1) I/O requests transfer.
(2) The interrupt controller selects the descriptor.
(3) The transfer source and destination are read from the descriptor.
(4) Data is transferred between I/O and memory.
Note:
The area that can be specified by IOA is between 000000H and 00FFFFH.
The area that can be specified by BAP is between 000000H and FFFFFFH.
The maximum transfer count that can be specified by DCT is 65,536.
■ Structure
EI2OS is handled by the following four sections:
• Internal resources:
Interrupt enable and request bits: Controls interrupt requests from resources.
• Interrupt controller:
ICR: Assigns interrupt levels, determines the priority levels of simultaneously requested interrupts, and
selects the EI2OS operation.
• CPU:
I and ILM: Compares the requested and current interrupt levels and identifies the interrupt enable status
Microcode: EI2OS processing step
• RAM:
Descriptor: Describes the EI2OS transfer information.
67
CHAPTER 3 INTERRUPTS
3.7.1
Extended Intelligent I/O Service Descriptor (ISD)
The extended intelligent I/O service descriptor exists between 000100H and 00017FH in
internal RAM, and consists of the following items:
• Data transfer control data
• Status data
• Buffer address pointer
■ Extended Intelligent I/O Service Descriptor (ISD)
Figure 3.7-2 shows the configuration of the extended intelligent I/O service descriptor.
Figure 3.7-2 Extended Intelligent I/O Service Descriptor Configuration
"H"
High-order 8 bits of data counter (DCTH)
Low-order 8 bits of data counter (DCTL)
High-order 8 bits of I/O address pointer (IOAH)
Low-order 8 bits of I/O address pointer (IOAL)
EI 2OS status (ISCS)
High-order 8 bits of buffer address pointer (BAPH)
000100 H + 8 × ICS
Medium-order 8 bits of buffer address pointer (BAPM)
ISD start address
Low-order 8 bits of buffer address pointer (BAPL)
"L"
■ Data Counter (DCT)
This is a 16-bit register that works as a counter corresponding to the number of data items transferred. This
counter is decremented by one before data transfer. EI2OS is terminated when this counter reaches "0".
Figure 3.7-3 shows the configuration of the data counter.
Figure 3.7-3 Configuration of the Data Counter (DCT)
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00
68
DCT
(Undefined when reset)
CHAPTER 3 INTERRUPTS
■ I/O Register address Pointer (IOA)
This is a 16-bit register that indicates the low-order address (A15 to A0) of the buffer and I/O register used
for data transfer. All of high-order addresses (A23 to A16) are "0", and any I/O between addresses 000000H
and 00FFFFH can be specified. Figure 3.7-4 shows the configuration of the IOA.
Figure 3.7-4 Configuration of the I/O Register address Pointer (IOA)
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
IOA
(Undefined when reset)
■ Buffer address Pointer (BAP)
This 24-bit register holds the address used for the next EI2OS transfer. BAP exists for each EI2OS channel.
Therefore, each EI2OS channel can be used for transfer with anywhere in the 16-Mbyte space. If the BF bit
of ISCS is set to "0" (update enabled), only the low-order 16 bits of BAP changes and BAPH does not
change.
69
CHAPTER 3 INTERRUPTS
EI2OS Status Register (ISCS)
3.7.2
This eight-bit register indicates the update direction (increment/decrement), transfer
data format (byte/word), and transfer direction of the buffer address pointer and the I/O
register address pointer. This register also indicates whether the buffer address pointer
or I/O register address pointer is updated or fixed.
■ EI2OS Status Register (ISCS)
Figure 3.7-5 shows the configuration of the ISCS configuration.
Figure 3.7-5 Configuration of the EI2OS (ISCS)
bit7
bit6
bit5
Reserved Reserved Reserved
bit4
bit3
bit2
bit1
bit0
IF
BW
BF
DIR
SE
ISCS
(Undefined when reset)
*: Always write "0" to bits 7 to 5 of ISCS.
[bit4] IF: Specify whether the I/O register address pointer is updated or fixed.
0: The I/O register address pointer is updated after data transfer.
1: The I/O register address pointer is not updated after data transfer.
Note:
Only increment is allowed.
[bit3] BW: Specify the transfer data length.
0: Byte
1: Word
[bit2] BF: Specify whether the buffer address pointer is updated or fixed.
0: The buffer address pointer is updated after data transfer.
1: The buffer address pointer is not updated after data transfer.
Note:
Only the low-order 16 bits of the buffer address are updated. Only increment is allowed.
[bit1] DIR: Specify the data transfer direction.
0: I/O → Buffer
1: Buffer → I/O
[bit0] SE: Control the termination of the extended intelligent I/O service based on resource requests.
0: The extended intelligent I/O service is not terminated by a resource request.
1: The extended intelligent I/O service is terminated by a resource request.
70
CHAPTER 3 INTERRUPTS
3.8
Operation Flow of and Procedure for Using the Extended
Intelligent I/O Service (EI2OS)
Figure 3.8-1 is a diagram of the EI2OS operation flow. Figure 3.8-2 is a diagram of the
EI2OS use procedure.
■ EI2OS Operation Flow
Figure 3.8-1 EI2OS Operation Flow
BAP : Buffer address pointer
I/OA : I/O address pointer
ISD : EI2OS descriptor
ISCS : EI2OS status
DCT : Data counterI
SE
: EI2OS enable bit
S1, S0: EI2OS end status
Interrupt request issued
from internal resource
ISE = 1
NO
Interrupt sequence
YES
Reading ISD/ISCS
End request from resource
YES
SE = 1
NO
DIR = 1
YES
NO
Data indicated by IOA
⇓ (Data transfer)
Memory indicated by BAP
IF = 0
YES
NO
BF = 0
Data indicated by BAP
⇓ (Data transfer)
Memory indicated by IOA
Update value
depends on BW.
Updating IOA
Update value
depends on BW.
Updating BAP
YES
NO
Decrementing DCT
DCT = 00
NO
YES
Setting S1 and S0 to "01"
Setting S1 and S0 to "11"
Setting S1 and S0
to "00"
Clearing resource
interrupt request
Clearing ISE to "0"
CPU operation return
Interrupt sequence
71
CHAPTER 3 INTERRUPTS
Figure 3.8-2 EI2OS Use Flow
Processing by EI2OS
Processing by CPU
EI2OS initialization
JOB execution
Normal
termination
(Interrupt request)
AND (ISE = 1)
Data transfer
Re-setting of extended intelligent
I/O service
(Switching channels)
Processing data in buffer
The extended EI2OS execution time for each flow is described below.
● When data transfer continues (when the stop condition is not satisfied)
(Table 3.8-1 + Table 3.8-2) machine cycles
● When a stop request is issued from a resource
(36 + 6 × Table 3.8-3) machine cycles
● When the counting is completed
(Table 3.8-1 + Table 3.8-2 + 21 + 6 × Table 3.8-3) machine cycles
Table 3.8-1 Execution Time when the Extended EI2OS Continues
ISCS SE bit
Set to "0"
I/O address pointer
Set to "1"
Fixed
Updated
Fixed
Updated
Fixed
32
34
33
35
Updated
34
36
35
37
Buffer address pointer
72
CHAPTER 3 INTERRUPTS
Table 3.8-2 Data Transfer Compensation Values for Extended EI2OS Execution Time
Internal access
I/O address pointer
Buffer address pointer
Internal
access
B/E
O
B/E
0
+2
O
+2
+4
B: Byte data transfer
E: Even address word transfer
O: Odd address word transfer
Table 3.8-3 Interrupt Handling Times
Address pointed to by the stack pointer
Interpolation value [cycles]
External 8-bit
+4
External even-numbered address
+1
External odd-numbered address
+4
Internal even-numbered address
0
Internal odd-numbered address
+2
73
CHAPTER 3 INTERRUPTS
3.9
Exceptions
The F2MC-16LX performs exception processing when the following events occurs:
■ Execution of an Undefined Instruction
Exception processing is fundamentally the same as interrupt processing. When an exception is detected
between instructions, exception processing is performed separately from ordinary processing. In general,
exception processing is performed as a result of an unexpected operation. Fujitsu recommends using
exception processing only for debugging or for activating emergency recovery software.
■ Exception Due to Execution of an Undefined Instruction
The F2MC-16LX handles all codes that are not defined in the instruction map as undefined instructions.
When an undefined instruction is executed, processing equivalent to the INT 10 software interrupt
instruction is performed. Specifically, the AL, AH, DPR, DTB, ADB, PCB, PC, and PS values are saved
into the system stack, and processing branches to the routine indicated by the interrupt number 10 vector. In
addition, the I flag is cleared and the S flag is set. The PC value saved in the stack is the address at which
the undefined instruction is stored. Processing can be restored by the RETI instruction, but is of no use,
however, because the same exception occurs again.
74
CHAPTER 4
DELAYED INTERRUPT
This chapter explains the functions and operations of
the delayed interrupt.
4.1 Outline of Delayed Interrupt Module
4.2 Delayed Interrupt Register
4.3 Delayed Interrupt Operation
75
CHAPTER 4 DELAYED INTERRUPT
4.1
Outline of Delayed Interrupt Module
The delayed interrupt source module is used to generate interrupts for switching tasks.
Using this module, interrupt requests to the F2MC-16LX CPU can be issued and
canceled by software.
■ Block Diagram of Delayed Interrupt
Figure 4.1-1 shows a block diagram of the delayed interrupt source module.
Figure 4.1-1 Block Diagram of Delayed Interrupt
F2MC-16 bus
Delayed interrupt cause issuance/cancellation decoder
Cause latch
■ Notes on Operation
The delayed interrupt signal is activated by writing "1" to the corresponding bit of DIRR, and is cleared by
writing "0" to the same bit. Therefore, interrupt processing is reactivated immediately after control returns
from interrupt processing, unless the software is designed so that the cause of the interrupt is cleared within
the interrupt processing routine.
76
CHAPTER 4 DELAYED INTERRUPT
4.2
Delayed Interrupt Register
DIRR controls issuance and cancellation of delayed interrupt requests. Writing "1" to
this register issues a delayed interrupt request, and writing "0" cancels the delayed
interrupt request. Upon a reset, the request is canceled.
■ Delayed Interrupt Cause Issuance/Cancellation Register (DIRR: Delayed Interrupt
Request Register)
Figure 4.2-1 Configuration of the Delayed Interrupt Cause/Cancel Register (DIRR)
R/W
X
-
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
00009F H
-
-
-
-
-
-
-
R0
XXXXXXX0B
-
-
-
-
-
-
-
R/W
:
:
:
Readable/writable
Undefined
Undefined bit
Table 4.2-1 Functional Explanation of Each Bit of the Delayed Interrupt Cause/Cancel Register (DIRR)
Bit name
Function
bit15 to bit9
Undefined bit
• When these bits are read, the values are undefined.
• Writing to these bits does not affect operation.
bit8
R0:
Delayed interrupt
request output bit
This bit sets the issuance/cancel of a delayed interrupt request.
• When this bit is "1", a delayed interrupt request is output.
• When this bit is "0", the delayed interrupt request is cleared.
• When a reset is specified, interrupt causes are canceled (cleared to "0").
77
CHAPTER 4 DELAYED INTERRUPT
4.3
Delayed Interrupt Operation
When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the
delayed interrupt source module is set and an interrupt request is issued to the
interrupt controller.
■ Delayed Interrupt Issuance
When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the delayed interrupt
source module is set and an interrupt request is issued to the interrupt controller. If this interrupt has the
highest priority or if there is no other interrupt request, the interrupt controller issues an interrupt request to
the F2MC-16LX CPU. The F2MC-16LX CPU compares the ILM bit of its internal CCR register with the
interrupt request, and starts the hardware interrupt processing microprogram as soon as the current
instruction is completed if the interrupt level of the request is higher than that of the ILM bit. The interrupt
processing routine for this interrupt is thus executed.
Figure 4.3-1 Delayed Interrupt Issuance
Delayed interrupt source module
Interrupt controller
F2MC-16LX CPU
WRITE
Other requests
ICR yy
IL
CMP
CMP
DIRR
ICR xx
ILM
INTA
78
CHAPTER 5
CLOCKS
This chapter describes the clocks used by MB90945
series microcontrollers.
5.1 Clocks
5.2 Block Diagram of the Clock Generation Block
5.3 Clock Selection Registers
5.4 Clock Mode
5.5 Oscillation Stabilization Wait Time
5.6 Connection of an Oscillator or an External Clock to the
Microcontroller
79
CHAPTER 5 CLOCKS
5.1
Clocks
The clock generation block controls the operation of the internal clock that controls
operation of the CPU and peripheral functions. This internal clock is called the machine
clock. One internal clock cycle is called one machine cycle. Other clocks include a
clock generated by source oscillation, called an oscillation clock, and a clock generated
by the internal PLL oscillation, called a PLL clock.
■ Clocks
The clock generation block contains the oscillation circuit that generates the oscillation clock. An external
oscillator is attached to this circuit. The oscillation clock can also be supplied by inputting an external clock
to the clock generation block. The clock generation block also contains the PLL clock multiplier circuit that
generates six clocks whose frequencies are multiples of the oscillation clock frequency. The clock
generation block controls the oscillation stabilization wait time and PLL clock multiplication as well as
internal clock operation by changing the clock with a clock selector.
● Oscillation clock (HCLK)
The oscillation clock is generated either from an external oscillator attached to the oscillation circuit or by
the input of an external clock.
● Main clock (MCLK)
The main clock, whose frequency is the oscillation clock frequency divided by 2, supplies the clock input
to the timebase timer and the clock selector.
● PLL clock (PCLK)
The PLL clock is obtained by multiplying the oscillation clock frequency with the internal PLL clock
multiplier circuit (PLL oscillation circuit). Selection can be made from among six different PLL clocks.
● Clock Modulator (CLOMO)
The clock modulator reduces the electromagnetic interference - EMI, by spreading the spectrum of the
clock signal over a wide range of different frequencies. The modulator works in phase modulation mode.
Please refer to "CHAPTER 6 CLOCK MODULATOR" for more detail.
● Machine clock (φ)
The machine clock controls the operation of the CPU and peripheral functions. One clock cycle is regarded
as one machine cycle (1/φ). An operating machine clock can be selected among the main clock (whose
frequency is the source clock frequency divided by 2) and the other six clocks (whose frequencies are
multiples of the source clock frequency).
Note:
Although an oscillation clock of 3 MHz to 8 MHz can be generated if the operating voltage is 5 V, the
maximum operating frequency for the CPU and peripheral functions is 24 MHz. If a frequency
multiplier rate or the peak frequency of the clock modulator exceeds the operating frequency as
specified, devices will not operate correctly.
80
CHAPTER 5 CLOCKS
■ Clock Supply Map
Since the machine clock generated in the clock generation block is supplied as the clock that controls the
operation of the CPU and peripheral functions, the operation of the CPU and the peripheral functions are
affected by switching the main clock and the PLL clock (clock mode) and by a change in the PLL clock
multiplier. Since some peripheral functions receive frequency-divided output from the timebase timer, a
peripheral unit can select the clock best suited for this operation. Figure 5.1-1 shows the clock supply map.
Figure 5.1-1 Clock Supply Map
Peripheral function
4
Watch-dog timer
8/16-bit PPG
PPG00 to PPG05
Pin
PPG10 to PPG15
Clock generation block
8/16-bit PPG
MCS
bit
Timebase timer
CAN1
1 2 3 4
6 8
16-bit reload
timer
PLL multiplier circuit
Pin
RX/TX
Pins
TIN0
Pins
TOT0
Pins
PCLK
SIN0/SIN1/SIN2(/SIN3)
Clock Selector
Pins
φc
UART0/UART3
+
Serial I/O
Clock modulator
X0
Pin
System
clock
generation
circuit
HCLK
X1
Pin
Divideby-2
...
SOT0/SOT1/SOT2(/SOT3)
Pins ...
SCK0/SCK1/SCK2(/SCK3)
Pins ...
Clock selector
MCLK
φ
AN0 to AN14
10-bit ADC
(15 ch)
Pins ...
SDA
Pin
I2C
SCL
Pin
16-bit free run timer
0/1
CPU
Output compare
(4 ch)
φ
φc
: Oscillation clock
: Main clock
: PLL clock
: Machine clock
: CAN1 clock
Pins
IN0 to IN5
16-bit input capture
(6 ch)
HCLK
MCLK
PCLK
FRCK0/FRCK1
3
Pins ...
OUT0 to OUT3
Pins ...
Oscillation
stabilization wait
control
81
CHAPTER 5 CLOCKS
5.2
Block Diagram of the Clock Generation Block
The clock generation block consists of five blocks:
• System clock generation circuit
• PLL multiplier circuit
• Clock selector
• Clock selection register (CKSCR)
• Oscillation stabilization wait time selector
■ Block Diagram of the Clock Generation Block
Figure 5.2-1 shows a block diagram of the clock generation block.
Figure 5.2-1 Block Diagram of the Clock Generation Block
Low-power consumption mode control register (LPMCR)
-
STP SLP SPL RST TMD CG1 CG0
RST
Pin
Interm.
cycle sel.
CPU inter mittent
operation
selector
Pin highimpedance
control circuit
Pin highimpedance
control
Internal reset
generation
circuit
Internal
reset
CPU clock
control
circuit
Stop and
sleep signals
Standby
control
circuit
Stop signal
Interrupt
clearing
Peripheral
clock control
circuit
2
PLL multiplier circuit
MCM WS1 WS0
-
MCS CS1 CS0
Clock selection register (CKSCR)
Main clock
Pin
HCLK
X1
Oscillation
stabilization
wait time
interval selector
2
CS2
X0
Peripheral
clock
Osc. stab. wait clear
Machine clock
Clock
selector
Bit8 of PLL and
special
configuration
control Register
(PSCCR)
CPU
clock
Pin
System clock
generation circuit
Divideby-2
Divideby-1024
Divideby-2
Divideby-4
Divideby-4
Divideby-4
Divideby-2
Timebase timer
Watch-dog timer
Note: The Clock Modulator is not shown in this diagram, please refer to
chapter 6 "CLOCK MODULATOR" for details.
82
CHAPTER 5 CLOCKS
● System clock generation circuit
The system clock generation circuit generates an oscillation clock (HCLK) from an external oscillator
attached to it. Alternatively, an external clock can be input to this circuit.
● PLL multiplier circuit
The PLL multiplier circuit multiplies the oscillation clock frequency through PLL oscillation and supplies a
clock whose frequency is a multiple of the oscillation clock frequency to the CPU clock selector.
● Clock selector
From among the main clock and six different PLL clocks, the clock selector selects the clock that is
supplied to the CPU and peripheral clock control circuits.
● Clock selection register (CKSCR)
The clock selection register switches the oscillation clock and a PLL clock and selects an oscillation
stabilization wait time and a PLL clock multiplier.
● Oscillation stabilization wait time selector
The oscillation stabilization wait time selector selects an oscillation stabilization wait time for the
oscillation clock when the stop mode is released. Selection is made from among four different timebase
timer outputs. In all other cases, an oscillation stabilization wait time is not selected.
83
CHAPTER 5 CLOCKS
5.3
Clock Selection Registers
This section lists the clock selection registers and describes the function of each
register in detail.
■ Clock Selection Registers
Figure 5.3-1 shows the clock selection register (CKSCR) and the PLL and special configuration control
register (PSCCR).
Figure 5.3-1 Clock Selection Registers
Address
0000A1H
Address
0035CFH
bit15
Reserved
84
bit13
MCM WS1
bit12 bit11
bit10
bit9
bit8
WS0
Reserved
MCS
CS1
CS0
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12 bit11
bit10
bit9
bit8
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
X
R/W
R
W
bit14
-
: Undefined value
: Undefined
: Readable/writable
: Read only
: Write only
-
-
W
W
W
CS2
W
Initial value
CKSCR
11111100B
Initial value
PSCCR
XXXX0000B
CHAPTER 5 CLOCKS
5.3.1
Clock Selection Register (CKSCR)
The clock selection register (CKSCR) is used to switch between the main clock and a
PLL clock and is also used to select an oscillation stabilization wait time and a PLL
clock multiplier.
■ Configuration of the Clock Selection Register (CKSCR)
Figure 5.3-2 shows the configuration of the clock selection register (CKSCR). Table 5.3-1 describes the
function of each bit of the clock selection register (CKSCR).
Figure 5.3-2 Configuration of the Clock Selection Register (CKSCR)
Address
0000A1H
bit15 bit14
Reserved
R/W
bit13
bit12
MCM WS1
WS0
R/W
R
R/W
bit11 bit10
bit9
bit8
Reserved
MCS
CS1
CS0
R/W
R/W
R/W
R/W
bit0 Initial value
(LPMCR)
11111100B
Multiplier selection bits
CS1 CS0
The resulting clock for 4 and 5 MHz crystal
is given in parentheses.
0
0
1 x HCLK (4MHz / 5 MHz)
0
1
2 x HCLK (8MHz / 10 MHz)
1
0
3 x HCLK (12MHz / 15 MHz)
1
1
4 x HCLK (16MHz / 20 MHz)
Machine clock selection bit
MCS
0
PLL clock selected.
1
Main clock selected.
Oscillation stabilization wait time selection bits
WS1 WS0
0
0
210/ HCLK(Approx. 256/204.8 s)
0
1
213/ HCLK (Aprox. 2.05/1.64 ms)
1
0
215/ HCLK (Aprox. 8.19/6.55 ms)
1
1
2 17/ HCLK (Aprox. 32.77/26.22 ms)*
MCM
R/W : Readable/writable
R : Read only
: Initial value
The corresponding time interval for an oscillation clock
of 4 MHz / 5 MHz is given in parentheses.
Machine clock indication bit
0
PLL clock selected.
1
Main clock selected.
*: except for MB90V390HA/HB (218/ HCLK, approx. 65.54/52.44 ms)
Note:
The machine clock selection bit is initialized to main clock selection at a reset.
85
CHAPTER 5 CLOCKS
Table 5.3-1 Clock Selection Register (CKSCR) (1 / 2)
Bit name
Function
bit15
Reserved
Note:
Always write "1" to this bit.
bit14
MCM:
Machine clock
indication bit
This bit indicates whether the main clock or a PLL clock has been selected as the machine
clock.
• When this bit is "0", a PLL clock has been selected. When it is "1", the main clock has
been selected.
• If MCS = 0 and MCM = 1, the PLL clock oscillation stabilization wait time is in effect.
bit13,
bit12
WS1, WS0:
Oscillation
stabilization wait time
selection bits
These bits select an oscillation stabilization wait time of the oscillation clock when stop
mode was released.
• These bits are initialized to "11B" by all reset causes.
Notes:
• The oscillation stabilization wait time must be set to a value appropriate for the
oscillator used. See Section "7.2 Reset Cause and Oscillation Stabilization Wait
Times". These bits can be set to "00B" and "01B"only for main clock mode.
• When PLL stop mode is returned to PLL clock mode, the oscillation stabilization
wait time requires 214/HCLK or more. When changing to PLL clock mode, these
bits must be set to "10B" or "11B".
bit11
86
Reserved
Wait time at 4 MHz source
oscillation
Wait time at 5 MHz source
oscillation
WS1
WS0
0
0
approx. 256 s (210 counts of
source oscillation)
approx. 205 s (210 counts of
source oscillation)
0
1
approx. 2.05 ms (213 counts of
source oscillation)
approx. 1.64 ms (213 counts of
source oscillation)
1
0
approx. 8.19 ms (215 counts of
source oscillation)
approx. 6.56 ms (215 counts of
source oscillation)
1
1
approx. 33.77 ms (217 counts of
source oscillation)
approx. 26.21 ms (217 counts of
source oscillation)
Note:
Always write "1" to this bit.
CHAPTER 5 CLOCKS
Table 5.3-1 Clock Selection Register (CKSCR) (2 / 2)
Bit name
Function
bit10
MCS:
Machine clock
selection bit
This bit specifies whether the main clock or a PLL clock is selected as the machine clock.
• When this bit is "0", a PLL clock is selected. When it is "1", the main clock is selected.
• If this bit has been set to "1" and "0" is written to it, the oscillation stabilization wait
time for the PLL clock starts. As a result, the timebase timer is automatically cleared,
and the TBOF bit of the timebase timer control register (TBTC) is also cleared.
• For PLL clocks, the oscillation stabilization wait time is fixed at 214/HCLK (the
oscillation stabilization wait time is approx. 4.1 ms for an oscillation clock frequency of
4 MHz).
• When the main clock has been selected, the operating clock frequency is the oscillation
clock frequency divided by 2 (that is, the operating clock is 2 MHz when the oscillation
clock frequency is 4 MHz).
• This bit is initialized to "1" by all reset causes.
Note:
When the MCS bit is "1", write "0" to it only when the timebase timer interrupt is
masked by the TBIE bit of the timebase timer control register (TBTC) or the interrupt
level register (ILM).
bit9,
bit8
CS1, CS0:
Multiplier selection
bits
•
•
•
•
These bits and CS2 bit in PSCCR register select a PLL clock multiplier.
Selection can be made from among six different multipliers.
These bits are initialized to "00B"by all reset causes.
Recommended settings of CS2, 1, 0:
CS2
CS1
CS0
PLL clock multiplier
0
0
0
x 1 For machine clock up to 20MHz*1
0
0
1
x 2 For machine clock up to 20MHz*1
0
1
0
x 3 For machine clock up to 20MHz*1
0
1
1
x 4 For machine clock up to 20MHz*1
1
0
0
x 5 For machine clock above 20MHz*1
1
0
1
x 6 For machine clock above 20MHz*1
1
1
0
x 7 For machine clock above 20MHz*1
1
1
1
x 8*2 For machine clock above 20MHz*1
*1 : Refer to the AC Characteristics Section in the Data sheet.
*2 : Not specified for all devices. Refer to the AC Characteristics Section in the
Data sheet.
Note:
When the MCS or MCM bit is "0", writing to these bits is not allowed. Write to the
CS2, CS1 and CS0 bits only after setting the MCS bit to "1" (main clock mode).
HCLK: Oscillation clock
87
CHAPTER 5 CLOCKS
5.3.2
PLL and Special Configuration Control Register (PSCCR)
The PLL and Special Configuration Control Register adds the selection of a PLL clock
multiplier.
■ Configuration of the PLL and Special Configuration Control Register (PSCCR)
Figure 5.3-3 shows the configuration of the PLL and Special Configuration Control Register (PSCCR).
Table 5.3-2 describes the function of each bit of the PLL and Special Configuration Control Register
(PSCCR).
Figure 5.3-3 Configuration of the PLL and Special Configuration Control Register (PSCCR)
bit15 bit14 bit13 bit12 bit11 bit10
Address
0035CFH
bit9
Reserved Reserved Reserved Reserved Reserved Reserved Reserved
-
-
-
-
W
W
W
bit8
CS2
PSCCR
W
CS2
0
1
Reserved
0
Reserved
0
Reserved
0
nly
W
X
-
88
: Write only
: Undefined value
: Undefined
: Initial value
Initial value
XXXX0000B
Additional multiplier selection bit
PLL clock multiplier x1, x2, x3, x4
(depending on the setting of the CS1 and
CS0 bits of CKSCR)
PLL clock multiplier x2, x4, x6, x8
(depending on the setting of the CS1 and
CS0 bits of CKSCR)
Reserved bit
Always write "0" to this bit
The value read from this bit is always "X"
Reserved bit
Always write "0" to this bit
The value read from this bit is always "X"
Reserved bit
Always write "0" to this bit
The value read from this bit is always "X"
Reserved
Reserved bits
XXXX
Always write "0" to these bits
The value read from these bits are always
"X"
CHAPTER 5 CLOCKS
Table 5.3-2 PLL and Special Configuration Control Register (PSCCR)
Bit name
Function
bit15
to
bit9
Reserved bit
These bits are reserved bits.
• Always write "0" to these bits.
• Reading these bits always returns "X".
bit8
CS2:
Additional multiplier
selection bit2
This bit and CS1 and CS0 bits of the Clock selection register (CKSCR) select a PLL clock
multiplier.
• About the relationship between setting CS2, CS1 and CS0 bits and the PLL clock
multiplier selection, please see Table 5.3-1.
• This bit is initialized to "0" by all reset causes.
• Reading this bit always returns "X".
Note:
When the MCS or MCM bit is "0", changing the setting of this bit is not allowed.
Change this bit only after setting the MCS bit to "1" and waiting for MCM = "1" (main
clock mode).
Note:
The PSCCR register is a write-only register, so the read value is different from the write value. Therefore, instructions
that perform a read-modify-write (RMW) operation, such as the INC/DEC instruction, cannot be used.
89
CHAPTER 5 CLOCKS
5.4
Clock Mode
Two clock modes are provided: main clock mode and PLL clock mode.
■ Main Clock Mode and PLL Clock Mode
● Main clock mode
In main clock mode, a clock whose frequency is the oscillation clock frequency divided by 2 is used as the
operating clock for the CPU and peripheral resources, and the PLL clocks are disabled.
● PLL clock mode
In PLL clock mode, a PLL clock is used as the operating clock for the CPU and peripheral resources. A
PLL clock multiplier is selected with the clock selection register (CKSCR: CS1 and CS0) and the PLL and
special configuration control register (PSCCR: CS2).
■ Clock Mode Transition
Transition among main clock mode, and PLL clock mode is performed by writing to the MCS bit of the
clock selection register (CKSCR).
● Transition from main clock mode to PLL clock mode
When the MCS bit of the clock selection register (CKSCR) is rewritten from "1" to "0" in main clock
mode, switching from the main clock to a PLL clock occurs after the PLL clock oscillation stabilization
wait time (214/HCLK).
● Transition from PLL clock mode to main clock mode
When the MCS bit of the clock selection register (CKSCR) is rewritten from "0" to "1" in PLL clock mode,
switching from the PLL clock to the main clock occurs when the edges of the PLL clock and the main
clock coincide (after 1 to 8 PLL clocks).
Note:
Even though the MCS bit of the clock selection register (CKSCR) is rewritten, machine clock switching
does not occur immediately. When operating a resource that depends on the machine clock, confirm
that machine clock switching has been performed by referring to the MCM bit of the clock selection
register (CKSCR) before operating the resource.
In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power
consumption mode until the first switching is completed. The MCM bit of the clock selection register
(CKSCR) indicate that switching is completed.
■ Selection of a PLL Clock Multiplier
Writing a value from "00B"to "11B"to the CS1 and CS0 bits of the clock selection register (CKSCR) and
"0" or "1" to the CS2 bit of the PLL and special configuration control register (PSCCR) selects a PLL clock
multiplier of 1 to 4, 6, or 8 (refer to Table 5.3-1 bit8/9).
90
CHAPTER 5 CLOCKS
■ Machine Clock
The machine clock may be a PLL clock output from the PLL multiplier circuit or a clock whose frequency
is the source oscillation frequency divided by 2. This machine clock is supplied to the CPU and peripheral
functions. The main clock or PLL clock can be selected by writing to the MCS bit of the clock selection
register (CKSCR).
■ Clock Modulator
For using the clock modulator please refer to "CHAPTER 6 CLOCK MODULATOR".
Figure 5.4-1 shows the status change caused by machine clock switching.
Figure 5.4-1 Status Change Diagram for Machine Clock Selection
Main
MCS = 1
MCM = 1
CS1, CS0 = xx
CS2 = x
(1)
(6)
(8)
(7)
Main
PLLx
MCS = 0
MCM = 1
CS1, CS0 = xx
CS2 = x
(7)
(7)
CS2 = 0
(6)
CS1, CS0 = 01
CS2 = 0
(6)
CS1, CS0 = 10
CS2 = 0
(7) CS1, CS0 = 01
CS2 = 1
CS1, CS0 = 11
CS2 = 0
(6) CS1, CS0 = 00
CS2 = 1
PLL4A: Multiplied
MCS = 0
MCM = 0
(6) CS1, CS0 = 01
CS2 = 1
PLL6
Main
MCS = 1
MCM = 0
(7)
CS1, CS0 = 10
CS2 = 1
PLL6: Multiplied
MCS = 0
MCM = 0
(6)
PLL8
Main
MCS = 1
MCM = 0
PLL4: Multiplied
MCS = 0
MCM = 0
(6)
PLL2A: Multiplied
MCS = 0
MCM = 0
PLL4A
Main
MCS = 1
MCM = 0
PLL3: Multiplied
MCS = 0
MCM = 0
PLL4
Main
MCS = 1
MCM = 0
CS1, CS0 = 11
CS2 = 0
(7) CS1, CS0 = 00
CS2 = 1
PLL2: Multiplied
MCS = 0
MCM = 0
PLL3
Main
MCS = 1
MCM = 0
CS1, CS0 = 10
CS2 = 0
(7)
(6) CS1, CS0 = 00
PLL2
Main
MCS = 1
MCM = 0
CS1, CS0 = 01
CS2 = 0
PLL2A
Main
MCS = 1
MCM = 0
PLL1: Multiplied
MCS = 0
MCM = 0
PLL1
Main
MCS = 1
MCM = 0
CS1, CS0 = 00
CS2 = 0
(7)
(9)
(10)
(11)
(2)
(3)
(4)
(5)
(7)
CS1, CS0 = 11
CS2 = 1
CS1, CS0 = 10
CS2 = 1
PLL8: Multiplied
MCS = 0
MCM = 0
(6)
CS1, CS0 = 11
CS2 = 1
91
CHAPTER 5 CLOCKS
(1)
Writing "0" to the MCS bit
(2)
End of PLL clock oscillation stabilization wait & CS2 = 0 & CS1,0 = 00
(3)
End of PLL clock oscillation stabilization wait & CS2 = 0 & CS1,0 = 01
(4)
End of PLL clock oscillation stabilization wait & CS2 = 0 & CS1,0 = 10
(5)
End of PLL clock oscillation stabilization wait & CS2 = 0 & CS1,0 = 11
(6)
Writing "1" to the MCS bit (including watch-dog timer reset)
(7)
Timing of synchronization between the PLL clock and the main clock
(8)
End of PLL clock oscillation stabilization wait & CS2 = 1 & CS1,0 = 00
(9)
End of PLL clock oscillation stabilization wait & CS2 = 1 & CS1,0 = 01
(10)
End of PLL clock oscillation stabilization wait & CS2 = 1 & CS1,0 = 10
(11)
End of PLL clock oscillation stabilization wait & CS2 = 1 & CS1,0 = 11
MCS
: Machine clock selection bit of the clock selection register (CKSCR)
MCM
: Machine clock indication bit of the clock selection register (CKSCR)
CS1, CS0 : Multiplier selection bits of the clock selection register (CKSCR)
CS2
: Multiplier selection bit of the PLL and special configuration control register (PSCCR)
Note:
The initial value for the machine clock setting is main clock (MCS of CKSCR = 1).
92
CHAPTER 5 CLOCKS
5.5
Oscillation Stabilization Wait Time
When the power is turned on or when stop mode is released, an oscillation stabilization
wait time is required after oscillation begins because there is no oscillation. When
switching from the main clock to a PLL clock occurs, an oscillation stabilization wait
time is also required after PLL oscillation starts.
■ Oscillation Stabilization Wait Time
Ceramic and crystal oscillators generally require several milliseconds to stabilize at their natural frequency
(oscillation frequency) when oscillation starts. For this reason, CPU operation is not allowed immediately
after oscillation starts but is allowed only after full oscillation stabilization. After the oscillation
stabilization wait time has elapsed, the clock is supplied to the CPU. Because the oscillation stabilization
time depends on the type of oscillator (crystal, ceramic, etc.), the proper oscillation stabilization wait time
for the oscillator used must be selected. An oscillation stabilization wait time is selected by setting the
clock selection register (CKSCR).
When switching from the main clock to a PLL clock occurs, the CPU continues to operate on the main
clock during the PLL oscillation stabilization wait time. After this interval, the operating clock switches to
the PLL clock.
Figure 5.5-1 shows the operation immediately after oscillation starts.
Figure 5.5-1 Operation Immediately after Oscillation Starts
Oscillator-activated
oscillation time
Oscillation stabilization wait interval
Normal operation
start or switching to
PLL clock
X1
Start of oscillation
Stable oscillation
93
CHAPTER 5 CLOCKS
5.6
Connection of an Oscillator or an External Clock to the
Microcontroller
The MB90945 series micro controller contains a system clock generation circuit.
Connecting an external oscillator to this circuit generates the system clock.
Alternatively, an externally generated clock can be input to the micro controller.
■ Connection of an Oscillator or an External Clock to the Microcontroller
● Example of connecting a crystal or a ceramic oscillator to the microcontroller
Connect a crystal or ceramic oscillator as shown in the example in Figure 5.6-1.
Figure 5.6-1 Example of Connecting a Crystal or a Ceramic Oscillator to the Microcontroller
X0
94
X1
CHAPTER 5 CLOCKS
● Example of connecting an external clock to the microcontroller
As shown in the example in Figure 5.6-2, connect an external clock to X0 pin. X1 pin must be open.
Figure 5.6-2 Example of Connecting an External Clock to the Microcontroller
MB90945 series
X0
~
X1
open
95
CHAPTER 5 CLOCKS
96
CHAPTER 6
CLOCK MODULATOR
This chapter provides an overview of the clock
modulator and its features. It describes the register
structure and operations of the clock modulator.
CAUTION: Do not use the clock modulation and CAN at
the same time on devices MB90F947, MB90F949 and
MB90V390HA. The problem is fixed on MB90F946A,
MB90947A, MB90F947A, MB90F949A and MB90V390HB.
6.1 Overview
6.2 Clock Modulator Control Register (CMCR)
6.3 Application Note
97
CHAPTER 6 CLOCK MODULATOR
6.1
Overview
This section gives an overview of the Clock modulator.
■ Overview
The clock modulator is intended for the reduction of electromagnetic interference - EMI, by spreading the
spectrum of the clock signal over a wide range of frequencies.
The modulator mode: phase modulation is supported.
The module is fed with an unmodulated reference clock with frequency F0, provided by the PLL circuit.
This reference clock is phase modulated by a triangular waveform or frequency modulated, controlled by a
random signal.
Figure 6.1-1 Frequency Spectrum of the Modulated Clock (Fundamentals Only)
modulation range
frequency
Fmin
98
F0
Fmax
CHAPTER 6 CLOCK MODULATOR
6.2
Clock Modulator Control Register (CMCR)
The control register (CMCR) enables/disables the phase modulation
■ Clock Modulator Control Register (CMCR)
Figure 6.2-1 Configuration of the Clock Modulator Control Register (CMCR)
bit7 bit6 bit5 bit4 bit3
Address
PMOD Reserved Reserved Reserved
0035C2H
R/W R/W R/W R/W
-
bit2
bit1
bit0
Reserved Reserved Reserved
R
Initial value
0001X000B
R/W R/W
Reserved
0
Reserved
Reserved
1
Reserved
0
CS2
R/W
R
X
-
: Readable / writable
: Read only
: Undefined value
: Undefined
: Initial value
0
1
Reserved bits
Always write "0" to these bits
Reserved bit
Writing this bit has no effect
Reserved bit
Always write "0" to this bit
Reserved bits
Always write "0" to these bits
Phase modulation enabled bit
Phase modulation disabled
Phase modulation enabled
99
CHAPTER 6 CLOCK MODULATOR
■ Clock Modulator Control Register Contents
Table 6.2-1 Function of Each Bit of the Clock Modulator Control Register
Bit name
Function
bit7
PMOD:
Phase modulation
enable bit
Writing "0": Phase modulation disabled (initial value).
Writing "1": Modulator enabled in phase modulation mode, MCU is running with
phase modulated clock
• To enable the modulator in phase modulation mode, PMOD must be set to "1".
For phase modulation mode, the modulator must remain in power down mode. i.e.
PDX must be set to "0".
• Before the modulator can be enabled, the PLL must deliver a stable reference clock
(PLL lock time must be elapsed - refer to the CLOCK chapter in the hardware
manual).
• The specified PLL frequency range for phase modulation mode is 15MHz to
25MHz.
• Whenever the PLL output frequency is changed or the PLL is switched off e.g. in
power down modes, the modulator must be disabled before → PMOD=0 and 4 NOP
cycles must follow the PMOD-bit access.
• After enabling the phase modulation mode, the clock switches immediately to
modulated clock without glitches in the clock signal.
Please refer to the application note for a description of the recommended startup
sequence.
• The status of the clock signal is indicated by PMOD. PMOD=1 clock is phase
modulated.
• The pulse width of the phase modulated clock signal can vary ± 1.2 ns.
E.g. at F0 = 20 MHz unmodulated input clock, T0 = 50ns.
Tmodmin = 50ns - 1.2ns = 48.8ns → Fmodmax = 1/48.8 ns = 20.49 MHz.
bit6, bit5
Reserved
Always write "0" to these bits.
bit4
Reserved
Always write "1" to this bit.
bit3
Undefined
bit2
Reserved
This bit read only and writing to this bit has no effect. Reading this bit always return
"0".
bit1, bit0
Reserved
Always write "0" to these bits.
100
-
CHAPTER 6 CLOCK MODULATOR
6.3
Application Note
Startup/stop sequence for phase modulation mode.
■ Recommended Startup Sequence for Phase Modulation Mode
start
1. Switch on PLL
2. Wait PLL lock time (refer to the MCM flag description in the CLOCK chapter of the hardware
manual).
3. Enable phase modulation mode (PMOD=1).
The clock switches immediately to modulated clock
... running...
stop
4. Disable modulator PMOD=0
5. 4 NOP cycles
6. Disable PLL, switch to power down mode, etc.
Note:
Do not enable the modulator before the PLL lock time has elapsed. Do not disable the PLL while the
modulator is running.
Caution:
Do not use the clock modulation and CAN at the same time on devices MB90F947, MB90F949 and
MB90V390HA. The problem is fixed on MB90F946A, MB90947A, MB90F947A, MB90F949A and
MB90V390HB.
101
CHAPTER 6 CLOCK MODULATOR
102
CHAPTER 7
RESETS
This chapter describes resets for the MB90945 series
microcontrollers.
7.1 Resets
7.2 Reset Cause and Oscillation Stabilization Wait Times
7.3 External Reset Pin
7.4 Reset Operation
7.5 Reset Cause Bits
7.6 Status of Pins in a Reset
103
CHAPTER 7 RESETS
7.1
Resets
If a reset is generated, the CPU immediately stops the current execution process and
waits for the reset to be cleared. The CPU then begins processing at the address
indicated by the reset vector.
The four causes of a reset are as follows:
• External reset request via the RST pin
• Software reset request
• Watch-dog timer overflow
• Power-on reset
■ Causes of a Reset
Table 7.1-1 lists the causes of a reset.
Table 7.1-1 Causes of a Reset
Type of reset
Cause
Machine clock
Watch-dog
timer
Oscillation
stabilization
wait
External pin
"L" level input to RST pin
Main clock (MCLK)
Stop
No
Software
A "0" is written to the RST bit of the
low power consumption mode control
register (LPMCR).
Main clock (MCLK)
Stop
No
Watch-dog timer
Watch-dog timer overflow
Main clock (MCLK)
Stop
No
Power-on
When the power is turned on
Main clock (MCLK)
Stop
Yes
Main clock: Oscillation clock frequency divided by 2
● External reset
An external reset is generated by the "L" level input to an external reset pin (RST pin). The minimum
required period of the "L" level is 16 machine cycles (16/φ). The oscillation stabilization wait time is not
required for external resets.
In the MB90945 series, the external reset has to be minimum 100 μs for wake-up from Main timebase timer
mode and minimum 100 μs + Oscillation time of oscillator + 16 machine cycles for wake-up from stop
mode. Refer to the AC characteristics section of the data sheet.
Reference:
If the reset cause is generated during a write operation (during the execution of a transfer instruction
such as MOV), the CPU waits for the reset to be cleared after completion of the instruction only for
reset requests via the RST pin. Therefore, the normal write operation is completed even though a reset
is input concurrently.
Note that a reset may prevent the data transfer requested by a string-processing instruction (such as
MOVS) from being completed because the reset is accepted before a specified number of bytes are
transferred.
104
CHAPTER 7 RESETS
● Software reset
A software reset is an internal reset generated by writing "0" to the RST bit of the low-power consumption
mode control register (LPMCR). The oscillation stabilization wait time is not required for a software reset.
● Watch-dog timer reset
A watch-dog timer reset is generated by a watch-dog timer overflow that occurs when "0" is written to the
WTE bit of the watch-dog timer control register (WDTC) within a given time after the watch-dog timer is
activated. The oscillation stabilization wait time can be set by the clock selection register (CKSCR).
● Power-on reset
A power-on reset is generated when the power is turned-on. In this case, the voltage step-down circuit
stabilization wait interval of 217/HCLK(EVA device) or 216/HCLK (others) is added to the oscillation
stabilization wait time oh 217/HCLK. When both of these wait times (approx. 65.54ms for EVA device or
49.15ms for others at 4 MHz source oscillation) have elapsed, the reset is executed. Refer to Figure 7.2-1.
Reference definition of clocks
HCLK: Oscillation clock
MCLK: Main clock
φ: Machine clock (CPU operating clock)
1/φ: Machine cycle (CPU operating clock period)
See "CHAPTER 5 CLOCKS", for details on machine clocks.
105
CHAPTER 7 RESETS
7.2
Reset Cause and Oscillation Stabilization Wait Times
The MB90945 series has four reset causes. The oscillation stabilization wait time for a
reset depends on the reset cause.
■ Reset Causes and Oscillation Stabilization Wait Times
Table 7.2-1 lists the reset causes and oscillation stabilization wait times.
Table 7.2-1 Reset Causes and Oscillation Stabilization Wait Times
Oscillation stabilization wait time
Reset cause
The corresponding time interval for an oscillation clock frequency of 4 MHz
is given in parentheses.
Power-on reset
217/HCLK(EVA device) or 216/HCLK (others) voltage step-down
circuit stabilization wait interval +217/HCLK oscillation
stabilization wait time =218/HCLK (approx. 65.54ms at 4MHz
oscillator for EVA device) or 3 x 216/HCLK (approx. 49.15ms at
4MHz oscillator for others)
Watch-dog timer
None
External reset via the RST
pin
None; though bits WS1 and WS0 are initialized to "11B".
Software reset
None; though bits WS1 and WS0 are initialized to "11B".
HCLK: Oscillation clock
WS1, WS0: Oscillation stabilization wait time selection bits of the clock selection register (CKSCR).
Figure 7.2-1 shows the oscillation stabilization wait times at a power-on reset.
106
CHAPTER 7 RESETS
Figure 7.2-1 Oscillation Stabilization Wait Times at a Power-on Reset
Vcc
EVA: 217/HCLK
217/HCLK
others:
216/HCLK
217/HCLK
CLK
CPU operation
Voltage step-down
circuit stabilization
wait interval
Oscillation
stabilization wait
time
HCLK: Oscillation clock
Note:
Ceramic and crystal oscillators generally require an oscillation stabilization wait time of several ms,
until stabilization at a natural frequency is attained. A proper oscillation stabilization wait time must be
set for the particular oscillator used.
See Section "5.5 Oscillation Stabilization Wait Time", for details about oscillation stabilization wait times.
■ Oscillation Stabilization Wait and Reset State
A reset operation in response to a power-on reset and other resets during stop mode are performed after the
oscillation stabilization wait time has elapsed. This time interval is generated by the timebase timer. If the
external reset has not been cleared after the interval, the reset operation is performed after the external reset
is cleared.
107
CHAPTER 7 RESETS
7.3
External Reset Pin
The external reset pin (RST pin) is an input pin used exclusively for a reset. Inputting an
"L" level signal generates an internal reset. For the MB90945 series, resets are
generated in synchronization with the CPU operating clock. However, the I/O port pins
are affected by the external reset pin (RST pin) in an asynchronous manner.
■ Block Diagrams of the External Reset Pin
● Block diagram of internal reset
Figure 7.3-1 Block Diagram of Internal Reset
CPU operating clock
(PLL multiplier circuit with an
HCLK frequency divided by 2)
RST
CPU
Pch
Synchronization
circuit
Pin
Nch
Input
buffer
Peripheral
functions
I/O port or
other pin
Note:
Inputs to the RST are accepted during cycles in which memory is not affected to prevent memory from
being destroyed by a reset during a write operation.
A clock is required to initialize the internal circuit. In particular, an operation with an external clock
requires clock input together with reset input.
108
CHAPTER 7 RESETS
7.4
Reset Operation
When a reset is cleared, the memory locations from which the mode data and the reset
vectors are read are selected according to the setting of the mode pins, and a mode
fetch is performed. Mode setting data determines the CPU operating mode and the
execution start address after a reset operation ends. For power-on or recovery from
stop mode by a reset, a mode fetch is performed when the oscillation stabilization wait
time elapses.
■ Overview of Reset Operation
Figure 7.4-1 shows the reset operation flow.
Figure 7.4-1 Reset Operation Flow
Power-on reset
stop mode
External reset
Software reset
Watch-dog timer reset
During a reset
Oscillation stabilization wait
and reset state
Fetching the mode data
Mode fetch
(Reset operation)
Normal operation
(Run state)
Pin state and function
change associated with
external bus mode
Fetching the reset vector
CPU executes an instruction,
fetching instruction codes from
the address indicated by the
reset vector.
■ Mode Pins
Setting the mode pins (MD0 to MD2) specifies how to fetch the reset vector and the mode data. Fetching
the reset vector and the mode data is performed in the reset sequence. See Section "9.2 Mode Pins", for
details on mode pins.
109
CHAPTER 7 RESETS
■ Mode Fetch
When the reset is cleared, the CPU transfers the reset vector and the mode data to the appropriate registers
in the CPU core by hardware. The reset vector and mode data are allocated to the four bytes from
"FFFFDCH" to "FFFFDFH". The CPU outputs these addresses to the bus immediately after the reset is
cleared and then fetches the reset vector and mode data. Using mode fetching, the CPU can begin
processing at the address indicated by the reset vector.
Figure 7.4-2 shows the transfer of the reset vector and mode data.
Figure 7.4-2 Transfer of Reset Vector and Mode Data
Memory space
FFFFDFH
Mode data
FFFFDEH
Bits 23 to 16 of reset vector
FFFFDDH
Bits 15 to 8 of reset vector
FFFFDCH
Bits 7 to 0 of reset vector
F2MC-16LX CPU core
Mode
register
Reset
sequence
MicroROM
PCB
PC
● Mode data (address: FFFFDFH)
Only a reset operation changes the contents of the mode register. The mode register setting is valid after a
reset operation. See Section "9.3 Mode Data", for details on mode data.
● Reset vector (address: FFFFDCH to FFFFDEH)
The execution start address after the reset operation ends is written as the reset vector. Execution starts at
the address contained in the reset vector.
● Note:
For MB90F946A, MB90F947(A) and MB90F949(A), the reset vector and the mode data have different
predetermined values by the hardwired logic.
For more information, refer to Section "25.9 Reset Vector Address in Flash Memory".
110
CHAPTER 7 RESETS
7.5
Reset Cause Bits
A reset cause can be identified by reading the watch-dog timer control register (WDTC).
■ Reset Cause Bits
As shown in Figure 7.5-1, a flip-flop is associated with each reset cause. The contents of the flip-flops are
obtained by reading the watch-dog timer control register (WDTC). If the cause of a reset must be identified
after the reset has been cleared, the value read from the WDTC should be processed by the software and a
branch made to the appropriate program.
Figure 7.5-1 Block Diagram of Reset Cause Bits
RST pin
No periodic clear
RST=L
External reset
request
detection cirtuit
Power-on
detection
circuit
Watch-dog timer
reset generation
detection cirtuit
Watch-dog timer
control register
(WDTC)
RST bit set
LPMCR, RST
bit write
detection circuit
Clear
S
R
S
Q
R
S
Q
R
Q
R
S
F/F
F/F
F/F
F/F
Delay
circuit
Q
Reading of
watch-dog timer
control register
(WDTC)
Internal data bus
S :
R :
Q :
F/F:
Set
Reset
Output
Flip Flop
111
CHAPTER 7 RESETS
■ Correspondence between Reset Cause Bits and Reset Causes
Figure 7.5-2 shows the configuration of the reset cause bits of the watch-dog timer control register
(WDTC). Table 7.5-1 maps the correspondence between the reset cause bits and reset causes. See "■
Watch-dog timer control register (WDTC)" in Section "12.1 Outline of Watch-Dog Timer", for details.
Figure 7.5-2 Configuration of the Reset Cause Bits (Watch-dog Timer Control Register)
Watch-dog timer control register (WDTC)
Address
bit15
0000A8 H
bit8 bit7
(TBTC)
bit6
PONR
-
R
-
bit5
bit4
bit3
bit2
bit1
bit0
WRST ERST SRST WTE WT1 WT0
R
R
R
W
W
Initial value
X -X X X X X B
W
R : Read only
W : Write only
X : Undefined
Table 7.5-1 Correspondence between Reset Cause Bits and Reset Causes
Reset cause
PONR
WRST
ERST
SRST
Power-on reset
1
X
X
X
Watch-dog timer overflow
*
1
*
*
External reset request via
RST pin
*
*
1
*
Software reset request
*
*
*
1
* : Previous state defined
X : Undefined
■ Notes about Reset Cause Bits
● Multiple reset causes generated at the same time
When multiple reset causes are generated at the same time, the corresponding reset cause bits of the watchdog timer control register (WDTC) are also set to "1". For example, an external reset request via the RST
pin and the watch-dog timer overflow occur at the same time, the ERST and the WRST bits are both set to
"1".
● Power-on reset
For a power-on reset, the PONR bit is set to "1" but all other reset cause bits are undefined. Because of it,
the software should be programmed so that it will ignore all reset cause bits except the PONR bit if it is "1".
112
CHAPTER 7 RESETS
● Clearing the reset cause bits
The reset cause bits are cleared only when the watch-dog timer control register (WDTC) is read. Any bit
corresponding to a reset cause that has already been generated is not cleared even though another reset is
generated (a setting of "1" is retained).
Note:
If the power is turned-on under conditions where no power-on reset occurs, the value in WDTC register
may not be guaranteed.
113
CHAPTER 7 RESETS
7.6
Status of Pins in a Reset
This section describes the status of pins when a reset occurs.
■ Status of Pins during a Reset
The status of pins during a reset depends on the settings of mode pins (MD2 to MD0).
● When internal vector mode has been set: (MD2 to MD0 = "011B")
All I/O pins (resource pins) are high impedance, and mode data is read from the internal ROM.
■ Status of Pins after Mode Data is Read
The status of pins after mode data has been read depends on the mode data (M1 and M0 = "00").
● When single-chip mode has been selected (M1, M0 = 00B)
All I/O pins (resource pins) are high impedance, and mode data is read from the internal ROM.
Note:
For those pins that change to high impedance when a reset cause is generated, confirm that devices
connected to the pins do not malfunction.
114
CHAPTER 8
LOW-POWER CONTROL
CIRCUIT
This chapter explains the functions and operations of
the low-power control circuits.
8.1 Overview of Low Power Consumption Mode
8.2 Block Diagram of the Low-Power Consumption Control Circuit
8.3 Low-Power Consumption Mode Control Register (LPMCR)
8.4 CPU Intermittent Operation Mode
8.5 Standby Mode
8.6 Status Change Diagram
8.7 Usage Notes on Low-Power Consumption Mode
115
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.1
Overview of Low Power Consumption Mode
The MB90945 series has the following CPU operating modes, any of which can be used
depending on operating clock selection and clock operation control:
• Clock mode (PLL clock mode or main clock mode)
• CPU intermittent operating mode (PLL clock intermittent operating mode or main
clock intermittent operating mode)
• Standby mode (sleep mode, timebase timer mode or stop mode)
■ CPU Operating Modes and Current Consumption
Figure 8.1-1 shows the relationship between the CPU operating modes and current consumption.
Figure 8.1-1 CPU Operating Mode and Current Consumption
Current consumption
Several tens
of mA
CPU operating
mode
Multiplied-by-eitht clock
PLL clock mode
Multiplied-by-six clock
Multiplied-by-four clock
Multiplied-by-three clock
Multiplied-by-two clock
Multiplied-by-one clock
Multiplied-by-eitht clock
PLL clock intermittent
operating mode
Multiplied-by-six clock
Multiplied-by-four clock
Multiplied-by-three clock
Multiplied-by-two clock
Multiplied-by-one clock
Main clock mode (1/2 clock mode)
Main clock intermittent operating mode
Several mA
Standby mode
Sleep mode
Timebase timer mode
Several μA
Stop mode
Low-power consumption mode
Note:
This figure is only an indication of the degree of power consumption for each mode. Actual current
consumption values may not agree with those in the figure.
116
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
■ Clock Mode
● PLL clock mode
In this mode, a PLL clock that is a multiple of the oscillation clock (HCLK) is used to operate the CPU and
peripheral functions.
● Main clock mode
In this mode, the main clock, with the oscillation clock (HCLK) frequency divided by 2 is used to operate
the CPU and peripheral functions. In the main clock mode, the PLL multiplier circuit is inactive.
Reference:
For the clock mode, see Section "5.4 Clock Mode".
■ CPU Intermittent Operating Mode
In this mode, the CPU is operated intermittently while high-speed clock pluses are supplied to peripheral
functions, thereby reducing power consumption. In this mode, intermittent clock pulses are supplied only to
the CPU while it is accessing a register, internal memory, peripheral function, or external unit.
■ Standby Mode
In this mode, the low-power consumption control circuit stops supplying the clock to the CPU (sleep mode)
or the CPU and peripheral functions (timebase timer mode) or stops the oscillation clock itself (stop mode),
thereby reducing power consumption.
● PLL sleep mode
The PLL sleep mode is activated to stop the CPU operating clock in the PLL clock mode. Components
excluding the CPU operate on the PLL clock.
● Main sleep mode
The main sleep mode is activated to stop the CPU operating clock in the main clock mode. Components
excluding the CPU operate on the main clock.
● Timebase timer mode
The timebase timer mode causes the operation of functions, excluding the oscillation clock, timebase timer,
and clock timer, to stop. All functions other than the timebase timer and clock timer are inactivated.
Please note that the status differentiates between Main timebase timer mode and PLL timebase timer mode.
The resulting state depends on the clock which is selected by the MCS-bit in CKSCR. See also Figure 8.61.
The power consumption is significantly higher in PLL timebase timer mode. Please refer to your datasheet
for specific values.
117
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
● Stop mode
The stop mode cause the oscillation to stop. All functions are inactivated.
Note:
Because the stop mode turn-off the oscillation clock, data can be retained at the lowest power
consumption.
In attempting to switch the clock mode, do not attempt to switch to another clock mode or low-power
consumption mode until the first switching is completed. The MCM bit of the clock selection register
(CKSCR) indicate that switching is completed.
118
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.2
Block Diagram of the Low-Power Consumption Control
Circuit
The low-power consumption control circuit consists of the following seven blocks:
• CPU intermittent operation selector
• Standby control circuit
• CPU clock control circuit
• Peripheral clock control circuit
• Pin high-impedance control circuit
• Internal reset generation circuit
• Low-power consumption mode control register (LPMCR)
■ Block Diagram of the Low-power Consumption Control Circuit
Figure 8.2-1 shows a block diagram of the low-power consumption control circuit.
Figure 8.2-1 Block Diagram of the Low-power Consumption Control Circuit
Low-power consumption mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0
RST
Reserved
Pin
Interm.
cycle sel.
CPU intermittent
operation
selector
Pin highimpedance
control circuit
Pin Hi-Z
control
Internal reset
generation
circuit
Internal
reset
CPU clock
control
circuit
Stop and
sleep signals
Standby
control
circuit
Stop signal
Interrupt
clearing
Peripheral
clock control
circuit
Bit8 of PLL and
special
configuration
control register
(PSCCR)
X0
Oscillation
stabilization
wait time
interval selector
2
2
PLL multiplier circuit
MCM WS1 WS0
-
MCS CS1 CS0
Clock Selection register (CKSCR)
Mainclock
Pin
HCLK
X1
Peripheral
clock
Osc. stab. wait clear
Machine clock
Clock
Selector
CS2
CPU
clock
Pin
System clock
generation circuit
Divideby-2
Divideby-1024
Divideby-2
Divideby-4
Divideby-4
Divideby-4
Divideby-2
Timebase timer
Watch-dog timer
119
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
● CPU intermittent operation selector
This selector selects the number of clock pulses to halt the CPU during the CPU intermittent operation
mode.
● Standby control circuit
The standby control circuit controls the CPU clock control and the peripheral clock control circuits and
turns the low-power consumption mode on and off.
● CPU clock control circuit
This circuit controls clocks supplied to the CPU. This circuit controls clocks supplied to peripheral
functions for the peripheral clock control circuit.
● Peripheral clock control circuit
This circuit controls clocks supplied to peripheral functions.
● Pin high-impedance control circuit
This circuit makes external pins high-impedance in the timebase timer mode and stop mode. For pins with
the pull-up option, this circuit disconnects the pull-up resistor in the stop mode.
● Internal reset generation circuit
This circuit generates an internal reset signal.
● Low-power consumption mode control register (LPMCR)
This register is used to switch to and release the standby mode and to set the CPU intermittent operation
function.
120
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.3
Low-Power Consumption Mode Control Register (LPMCR)
This register switches to or releases the low-power consumption mode. This register
also sets the number of CPU clock pulses to halt during the CPU intermittent operation
mode.
■ Low-power Consumption Mode Control Register (LPMCR)
Figure 8.3-1 shows the configuration of the low-power consumption mode control register (LPMCR).
Figure 8.3-1 Configuration of the Low-power Consumption Mode Control Register (LPMCR)
bit15
Address
0000A0H
(CKSCR)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
STP
SLP
SPL
RST
TMD
CG1
CG0 served
W
W
R/W
W
R/W
R/W
R/W
Re-
Reserved
0
00011000B
R/W
Reserved bit
Count bits for CPU clock temporary halt cycle
0
0
0 cycles (CPU clock = Resource clock)
0
1
8 cycles (CPU clock:Resource clock = 1:3 to 4 approx.)
1
0
16 cycles (CPU clock:Resource clock = 1:5 to 6 approx.)
1
1
32 cycles (CPU clock:Resource clock = 1:9 to 10 approx.)
TMD
Timebase timer mode bit
0
Switches to the timebase timer mode
1
No change, no effect on operation
RST
Internal reset signal generation bit
0
Generates an internal reset signal of three machine cycles.
1
No change, no effect on operation
Pin state setting bit
(for timebase timer mode and stop mode)
SPL
0
Retained
1
High impedance
SLP
: Readable / writable
: Write only
: Initial value
Initial value
Always write "0" to this bit
CG1 CG0
R/W
W
bit0
Sleep mode bit
0
No change, no effect on operation
1
Switches to sleep mode.
STP
Stop mode bit
0
No change, no effect on operation
1
Switches to stop mode.
121
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
Table 8.3-1 Function Description of Each Bit of the Low-power Consumption Mode Control Register
(LPMCR)
Bit name
Function
bit7
STP:
Stop mode bit
This bit indicates switching to the stop mode.
• When "1" is written to this bit, a switch to the stop mode is performed.
• Writing "0" in this bit has no effect on operation.
• This bit is cleared to "0" by a reset or when an interrupt request occurs.
• The read value of this bit is always "0".
bit6
SLP:
Sleep mode bit
This bit indicates switching to a sleep mode.
• When "1" is written to this bit, a switch to a sleep mode is performed.
• Writing "0" in this bit has no effect on operation.
• This bit is cleared to "0" by a reset or when an interrupt request occurs.
• The read value of this bit is always "0".
bit5
SPL:
Pin state setting bit
(for timebase timer
mode and stop mode)
This bit is enabled only in the timebase timer mode and stop mode.
• When this bit is "0", the level of the external pins is retained.
• When this bit is "1", the status of the external pins changes to high-impedance.
• This bit is initialized to "0" by a reset.
bit4
RST:
Internal reset signal
generation bit
• When "0" is written to this bit, an internal reset signal of three machine cycles is
generated.
• Writing "1" in this bit has no effect on operation.
• The read value of this bit is always "1".
bit3
TMD:
Timebase timer mode
bit
This bit indicates switching to the timebase timer mode.
• When "0" is written to this bit in the main clock mode or PLL clock mode, a switch to
timebase timer mode is performed.
• This bit is cleared to "1" by a reset or when an interrupt request occurs.
• The read value of this bit is always "1".
bit2,
bit1
CG1, CG0:
Count for CPU
temporary halt cycle
bit
These bits set the number of CPU clock pulses per cycle to halt the CPU for the CPU
intermittent operation function.
• The clock supplied to the CPU is stopped for the specified number of pulses after the
execution of each instruction.
• Four types of clock counts are selectable.
• These bits are initialized to 00B by a reset.
bit0
Reserved
• Always write "0" to this bit.
122
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
■ Access to the Low-power Consumption Mode Control Register
Writing in the low-power consumption mode control register executes a change in the low-power
consumption mode (including the stop mode, sleep mode, and timebase timer mode). Only the instructions
listed in Table 8.3-2 should be used for this purpose.
The low-power consumption mode transition instruction in Table 8.3-2 must always be followed by an
array of instructions highlighted by a line below.
MOV
LPMCR, #H’XX
; the low-power mode transition instruction in Table 8.3-2
JMP
$+3
; jump to next instruction
MOV
A, #H’10
; any instruction
NOP
NOP
The device does not guarantee its operation after returning from the low-power consumption mode if you
place an array of instructions other than the one enclosed in the line. To access the low-power consumption
mode control register (LPMCR) with C language, refer to "■ Notes on accessing the low-power
consumption mode control register (LPMCR) to enter the standby mode" in the section "8.7 Usage Notes
on Low-Power Consumption Mode". If other instructions are used for switching to a low-power
consumption mode, operation cannot be assured. To control functions not listed in Table 8.3-1, any
instruction can be used.
When word-length is used for writing the low-power consumption mode control register, even addresses
must be used. Using odd addresses to switch to a low-power consumption mode may result in a
malfunction.
■ Priorities of the STP, SLP, and TMD Bits
If the stop mode, sleep mode, and timebase timer mode are requested concurrently, the stop mode request,
timebase timer mode request, and sleep mode request are given priorities in this order for processing.
Note:
To set a pin to high impedance when the pin is shared by a peripheral function and a port in stop mode
or timebase timer mode, disable the output of peripheral functions, and set the STP bit of the low-power
consumption mode control register (LPMCR) to "1" or set the TMD bit to "0".
This applies to the following pins:
P06/OUT0, P07/OUT1, P10/OUT2, P11/OUT3, P15/TOT0, P20/TX1, P34/SOT0, P35/SCK0
123
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
Table 8.3-2 Instructions to be Used for Switching to a Low-power Consumption Mode
124
MOV io,#imm8
MOV dir,#imm8
MOV eam,#imm8
MOV eam,Ri
MOV io,A
MOV dir,A
MOV addr,A
MOV eam,A
MOV @RLi+disp8,A
MOVP addr24,A
MOVW io,#imm16
MOVW dir,#imm16
MOVW eam,#imm16
MOVW eam,RWi
MOVW io,A
MOVW dir,A
MOVW addr16,
MOVW eam,A
MOVW @RLi+disp8,A
MOVPW addr24,A
SETB io:bp
SETB dir:bp
SETB addr16:bp
CLRB io:bp
CLRB dir:bp
CLRB addr16:bp
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.4
CPU Intermittent Operation Mode
This mode is used for intermittent operation of the CPU while external buses and
peripheral functions continue to operate at high speeds. The purpose of this mode is to
reduce power consumption.
■ CPU Intermittent Operation Mode
This mode halts the supply of the clock pulse to the CPU for a certain period. The halt occurs after the
execution of every instruction that accesses a register, internal memory (ROM and RAM), I/O, peripheral
functions, or the external bus. Internal bus cycle activation is therefore delayed. While high-speed
peripheral clock pulses are supplied to peripheral functions, the execution speed of the CPU is reduced,
thereby enabling low-power consumption processing.
• The low-power consumption mode control register (LPMCR: CG1 and CG0) is used to select the
number of clock pulses per halt cycle of the clock supplied to the CPU.
• External bus operation uses the same clock as that used for peripheral functions.
• Instruction execution time in the CPU intermittent mode can be calculated. A correction value should be
obtained by multiplying the execution count of instructions that access a register, internal memory,
internal peripheral functions, or the external bus by the number of clock pulses per halt cycle. Add this
corrective value to the normal execution time. Figure 8.4-1 shows the operating clock pulses during the
CPU intermittent operation mode.
Figure 8.4-1 Clock Pulses during the CPU Intermittent Operation Mode
Peripheral clock
CPU clock
Halt cycle
Execution
cycle of one
instruction
Internal bus activation
125
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.5
Standby Mode
The standby mode includes the sleep (PLL sleep, main sleep), timebase timer, and stop
modes.
■ Operation Status during Standby Mode
Table 8.5-1 shows operation statuses during standby mode.
Table 8.5-1 Operation Status during Standby Mode
Condition
for switch
Main
clock
PLL sleep
mode
MCS=0
SLP=1
Active
Main sleep
mode
MCS=1
SLP=1
Timebase
timer mode
(SPL=0)
TMD=0
Standby mode
Sleep
mode
Machine
clock
CPU
Active
Timebase
timer
mode
Stop
mode
TMD=0
Stop mode
(SPL=0)
STP=1
Active
Active
Release
event
Retained
Inactive
Reset
or
Interrupt
Inactive *
Hi-Z
Inactive
Retained
Inactive
Stop mode
(SPL=1)
Pin
Active
Active
Timebase
timer mode
(SPL=1)
Peripheral
Inactive
STP=1
Hi-Z
*: The timebase timer operates.
SPL: Pin state setting bit of low-power consumption mode control register (LPMCR)
SLP: Sleep mode bit of low-power consumption mode control register (LPMCR)
STP: Stop mode bit of low-power consumption mode control register (LPMCR)
TMD: Timebase timer mode bit of low-power consumption mode control register (LPMCR)
MCS: Machine clock selection bit of clock selection register (CKSCR)
Hi-Z: High-impedance
Note:
To set a pin to high-impedance when the pin is shared by a peripheral function with a port in stop mode
or timebase timer mode, disable the output of peripheral functions, and set the STP bit of the low-power
consumption mode control register (LPMCR) to "1" or set the TMD bit to "0".
This applies to the following pins:
P06/OUT0, P07/OUT1, P10/OUT2, P11/OUT3, P15/TOT0, P20/TX1, P34/SOT0, P35/SCK0
126
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.5.1
Sleep Mode
This mode stops the CPU operating clock. Other components continue to operate.
When the low-power consumption mode control register (LPMCR) indicates a switch to
a sleep mode, a switch to the PLL sleep mode occurs if the PLL clock mode has been
set. A switch to the main sleep mode occurs if the main clock mode has been set.
■ Switching to Sleep Mode
Writing "1" in the SLP bit and the TMD bit and "0" in the STP bit of the low-power consumption mode
control register (LPMCR) triggers a switch to a sleep mode. At this time, if the MSC bit is "0" in the clock
selection register (CKSCR), a switch to the PLL sleep mode is triggered. If the MSC bit is "1", a switch to
the main sleep mode is triggered.
Note:
When "1" is written to the SLP and STP bits at the same time, the STP bit setting overrides the SLP bit
setting and the mode switches to the stop mode. When "1" is written to the SLP bit and "0" is written to
the TMD bit at the same time, the TMD bit setting overrides the SLP bit setting and the mode switches
to the timebase timer mode.
● Data retention function
In a sleep mode, the contents of dedicated registers, such as accumulators, and the internal RAM are
retained.
● Operation during an interrupt request
Writing "1" in the SLP bit of the low-power consumption mode control register during an interrupt request
does not trigger a switch to a sleep mode. If the CPU does not accept the interrupt, the CPU executes the
next instruction. If the CPU accepts the interrupt, CPU operation immediately branches to the interrupt
processing routine.
● Status of pins
During a sleep mode, all pins (excluding those used for bus I/O or bus control) retain their previous status.
127
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
■ Release of Sleep Mode
The low-power consumption control circuit releases sleep modes when a reset is input or an interrupt
occurs.
● Return by a reset
A sleep mode is initialized to the main clock mode by a reset.
● Return by an interrupt
If an interrupt request of level seven or higher is issued from a peripheral circuit during a sleep mode, the
sleep mode is released. After the mode is released, the interrupt is handled as an ordinary interrupt. If the
interrupt is accepted according to the setting of the I flag of the condition code register (CCR), interrupt
level mask register (ILM), and interrupt control register (ICR), the CPU executes the interrupt processing.
If the interrupt is not accepted, the CPU executes the instruction following the instruction specifying the
sleep mode.
Figure 8.5-1 shows the release of a sleep mode when an interrupt occurs.
Figure 8.5-1 Release of Sleep Mode by Interrupt Occurrence
Interrrupt from peripheral function
Set the enable flag.
IL smaller than 7
INT occurrence?
NO
(IL smaller than 7)
Sleep mode is
not released.
Sleep mode is
not released.
YES
I=0
YES
Next instruction
is executed.
NO
YES
ILM smaller than IL
Sleep mode is
released.
Next instruction
is executed.
NO
Interrupt is executed.
Note:
When interrupt processing is executed, the CPU normally executes the instruction that follows the
instruction in which switching to a sleep mode has been specified. The CPU then proceeds to interrupt
processing. If the switching to sleep mode and acceptance of an external bus hold request occur at the
same time, however, the CPU may proceed to interrupt processing before executing the next instruction.
128
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.5.2
Timebase Timer Mode
This mode causes all functions, excluding oscillation, the timebase timer, and the clock
timer, to stop. In this mode, only the timebase timer and clock timer operate.
■ Switching to the Timebase Timer Mode
When "0" is written to the TMD bit of the low-power consumption mode control register (LPMCR) in the
PLL clock mode or main clock mode, switching to the timebase timer mode occurs.
Please note that the status differentiates between Main timebase timer mode and PLL timebase timer mode.
The resulting state depends on the clock which is selected by the MCS-bit in CKSCR. See also Figure 8.61.
The power consumption is significantly higher in PLL timebase timer mode. Please refer to your datasheet
for specific values.
● Data retention function
In the timebase timer mode, the contents of dedicated registers, such as accumulators, and the internal
RAM are retained.
● Operation during an interrupt request
Writing "0" in the TMD bit of the low-power consumption mode control register (LPMCR) during an
interrupt request does not trigger a switch to the timebase timer mode.
● Status of pins
Whether the external pins in the timebase timer mode retain the state they had immediately before
switching to the timebase timer mode or go to the high-impedance state can be controlled by the low-power
consumption mode control register (LPMCR: SPL).
129
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
■ Release of Timebase Timer Mode
The low-power consumption control circuit releases the timebase timer mode when a reset is input or an
interrupt occurs.
● Return by a reset
The timebase timer mode is initialized to the main clock mode by a reset.
Note:
The RST signal must be asserted for at least 100 μs in Main timebase timer mode.
● Return by an interrupt
If an interrupt request of level seven or higher is issued from a peripheral circuit during the timebase timer
mode (IL2, IL1, and IL0 of the interrupt control register (ICR) do not indicate 111B), the low-power
consumption mode control circuit releases the timebase timer mode. After the mode is released, the
interrupt is handled as an ordinary interrupt. If the interrupt is accepted according to the setting of the I flag
of the condition code register (CCR), interrupt level mask register (ILM), or interrupt control register
(ICR), the CPU executes the interrupt processing. If the interrupt is not accepted, the CPU executes the
instruction following the instruction specifying the timebase timer mode.
Notes:
When interrupt processing is executed, the CPU normally executes the instruction following the
instruction in which switching to the timebase timer mode has been specified. The CPU then proceeds
to interrupt processing. If the switching to the timebase timer mode and acceptance of an external bus
hold request occur at the same time, however, the CPU may proceed to interrupt processing before
executing the next instruction.
Wake up from Main timebase timer mode by interrupt is internally delayed up to 40 μs.
To set a pin to high impedance when the pin is shared by a peripheral function and a port in timebase
timer mode, disable the output of peripheral functions, and set the TMD bit of the low-power
consumption mode control register (LPMCR) to "0".
This applies to the following pins:
P06/OUT0, P07/OUT1, P10/OUT2, P11/OUT3, P15/TOT0, P20/TX1, P34/SOT0, P35/SCK0
130
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.5.3
Stop Mode
Because this mode causes oscillation to stop and inactivates all functions, data can be
retained by the lowest power consumption.
■ Switching to the Stop Mode
When "1" is written to the STP bit of the low-power consumption mode control register (LPMCR),
switching to the stop mode occurs.
● Data retention function
In the stop mode, the contents of the dedicated registers, such as accumulators, and the internal RAM are
retained.
● Operation during an interrupt request
Writing "1" in the STP bit of the low-power consumption mode control register (LPMCR) does not trigger
a switch to the stop mode.
● Status of pins
Whether the external pins in the stop mode retain the state they had immediately before switching to the
stop mode or go to the high-impedance state can be controlled by the SPL bit of the low-power
consumption mode control register (LPMCR).
131
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
■ Release of Stop Mode
The low-power consumption control circuit releases the stop mode when a reset is input or an interrupt
occurs. Because oscillation of the operating clock is halted before returning from the stop mode, the lowpower consumption control circuit enters the oscillation stabilization wait state, then releases the stop
mode.
● Return by a reset
After the stop mode is released by a reset, the oscillation stabilization wait state is set. The reset sequence is
executed after the oscillation stabilization wait time.
Note:
The RST signal must be asserted for at least 100 μs + oscillation time of the oscillator + 16 machine
clock cycles in stop mode. Refer to the AC characteristics section of the data sheet.
● Return by an interrupt
If an interrupt request of level seven or higher is issued from a peripheral circuit during the stop mode (IL2,
IL1, and IL0 of the interrupt control register (ICR) do not indicate 111B), the low-power consumption
mode control circuit releases the stop mode. The interrupt is then handled as an ordinary interrupt after the
oscillation stabilization wait time of the main clock specified by the WS1 and WS0 bits of the clock
selection register (CKSCR). If the interrupt is accepted according to the setting of the I flag of the condition
code register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR), the CPU
executes the interrupt processing. If the interrupt is not accepted, the CPU executes the instruction
following the instruction specifying the stop mode.
Note:
When interrupt processing is executed, the CPU normally executes the instruction following the
instruction in which switching to the stop mode has been specified. The CPU then proceeds to interrupt
processing. If the switching to the stop mode and acceptance of an external bus hold request occur at the
same time, however, the CPU may proceed to interrupt processing before executing the next instruction.
Figure 8.5-2 shows a return from the stop mode.
Figure 8.5-2 Release of the Stop Mode (External Reset)
RST pin
Stop mode
Oscillating
Oscillation stabilization wait
Main clock
Oscillating
PLL clock
Inactive
Inactive
Main clock
CPU clock
CPU operation
Inactive
Reset released
Stop mode released
132
Reset sequence Execution
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
Notes:
• To set a pin to high-impedance when the pin is shared by a peripheral function and a port in stop mode,
disable the output of peripheral functions, and set the STP bit of the low-power consumption mode
control register (LPMCR) to "1".
This applies to the following pins:
P06/OUT0, P07/OUT1, P10/OUT2, P11/OUT3, P15/TOT0, P20/TX1, P34/SOT0, P35/SCK0
• In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL stop
mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock oscillation
stabilization wait time. The oscillation stabilization wait times for the main clock and PLL clock are
counted simultaneously according to the value specified in the oscillation stabilization wait time
selection bits (CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait
time selection bits (CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to
account for the longer of main clock and PLL clock oscillation stabilization wait time. The PLL clock
oscillation stabilization wait time, however, requires 214/HCLK or more. Set the oscillation stabilization
wait time selection bits (CKSCR: WS1, WS0) in the clock selection register to "10B" or "11B".
133
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.6
Status Change Diagram
Figure 8.6-1 shows the status change diagram of the MB90945 series.
■ Status Change Diagram
Figure 8.6-1 Status Change Diagram
External reset, watch-dog timer
reset, software reset
Power-on
Reset
Power-on reset
Osc
MCS=0
Main clock mode
PLL clock mode
MCS=1
SLP=1
SLP=1
Int
Main sleep mode
TMD=0
Int
Main
timebase
timer mode
STP=1
Int
TMD=0
STP=1
PLL stop mode
Osc
Main clock oscillation
stabilization wait
Int: Interrupt
Osc: Oscillation stabilization wait end
134
PLL sleep mode
PLL
timebase
timer mode
Main stop
mode
Int
Int
Int
Osc
PLL clock oscillation
stabilization wait
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
■ Operation Status in Each Operating Mode
Table 8.6-1 lists the operation status in each operating mode.
Table 8.6-1 Operation Status in Each Operating Mode
Operation status
Main
clock
PLL clock
PLL
CPU
Peripheral
Timebase
timer
Clock
source
Active
Active
PLL sleep
Active
Active
Active
Timebase timer *1
PLL clock
PLL stop
Inactive
Inactive
PLL oscillation
stabilization wait
Active
Active
Main
Inactive
Inactive
Inactive
Active
Active
Active
Main sleep
Active
Timebase timer *2
Active
Inactive
Main stop
Inactive
Main oscillation
stabilization wait
Active
Power-on reset
Inactive
Inactive
Main
clock
Active
Inactive
Active
Reset
Inactive
Inactive
Active
Inactive
Active
*3
*1: During the PLL clock mode
*2: During the main clock mode
*3: During reset phase, the timebase timer starts running as soon as a clock is available (not immediately in
power-on).
At the end of the reset phase, the timer value is reset to the initial value.
135
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
8.7
Usage Notes on Low-Power Consumption Mode
Note the following four items when using the low-power consumption mode:
• Switching to the standby mode and interrupt
• Notes on the transition to standby mode
• Release of a standby mode by an interrupt
• Release of the stop mode
• Oscillation stabilization wait time
• Switching to the clock modes
• Notes on accessing the low-power consumption mode control register (LPMCR) to
enter the standby mode
■ Switching to the Standby Mode and Interrupt
During an interrupt request to the CPU from a peripheral function, the CPU ignores the setting of the lowpower consumption mode control register (LPMCR) even if "1" is written to the STP and SLP bits or if "0"
is written to the TMD bit. Thus, switching to each standby mode is disabled (even after processing of the
interrupt is completed, there is no switch to a standby mode). If the interrupt level is seven or a higher
priority, this action does not depend on whether the interrupt request is accepted by the CPU. However,
during execution of interrupt processing by the CPU, if the interrupt request flag for the interrupt is cleared
and no other interrupt requests have been issued, switching to a standby mode can be performed.
■ Notes on the Transition to Standby Mode
To set a pin to high-impedance when the pin is shared by a peripheral function and a port in stop mode or
timebase timer mode, use the following procedure:
1. Disable the output of peripheral functions.
2. Set the SPL bit to "1", STP bit to "1", or TMD bit to "0" in the low-power mode control register
(LPMCR).
■ Release of the Standby Mode by an Interrupt
If an interrupt request of interrupt level seven or a higher priority is issued from a peripheral function
during the sleep, timebase timer, or stop mode, the standby mode is released, which does not depend on
whether the CPU accepts the interrupt.
After the release of the standby mode by an interrupt, normal processing is performed. The CPU branches
to the interrupt handling routine provided that the priority of the interrupt request indicated by the interrupt
level setting bits (IL2, IL1, and IL0 of ICR) is higher than the interrupt level mask register (ILM) and the
interrupt enable flag (I) of the condition code register (CCR) is set to "1" (enabled).
If the interrupt is not accepted, the CPU starts the execution with the instruction following the instruction in
which switching to the standby mode has been specified.
When interrupt processing is executed normally, the CPU first executes the instruction following the
instruction in which switching to the standby mode has been specified. The CPU then proceeds to interrupt
processing.
Depending on the condition when switching to a standby mode was performed, however, the CPU may
proceed to interrupt processing before executing the next instruction.
136
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
Note:
If the CPU does not branch to the interrupt processing routine immediately after a return, action such as
interrupt disabling must be taken before a standby mode is set.
■ Release of the Stop Mode
The stop mode can be released by an input that has been set as an external interrupt input cause before the
system enters the stop mode. As an input cause, an "H" level signal, "L" level signal, rising edge, or falling
edge can be selected.
■ Oscillation Stabilization Wait Time
● Clock oscillation stabilization wait time
Because the oscillator for oscillation is halted in the stop mode, an oscillation stabilization wait time is
required. A time period selected by the WS1 and WS0 bits of the clock selection register (CKSCR) is used
as the oscillation stabilization wait time. The WS1 and WS0 bits can be set to "00B" only in the main clock
mode.
● PLL clock oscillation stabilization wait time
In main clock mode, the PLL multiplication circuit stops. When changing to PLL clock mode, it is
necessary to reserve the PLL clock oscillation stabilization wait time.
In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL stop
mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock oscillation
stabilization wait time. The oscillation stabilization wait times for the main clock and PLL clock are
counted simultaneously according to the value specified in the oscillation stabilization wait time selection
bits (CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection
bits (CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the
longer of main clock and PLL clock oscillation stabilization wait time. The PLL clock oscillation
stabilization wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time
selection bits (CKSCR: WS1, WS0) in the clock selection register to "10B" or "11B".
■ Switching to the Clock Modes
When the clock mode is switched, the mode should not switch to the low power consumption mode, or
other clock mode until the switching termination. To check the switching termination, the MCM bit of the
clock selection register (CKSCR) is read. The other switching to other clock mode or to low power
consumption mode may not be done before the switching termination.
■ Notes on accessing the Low-power Consumption Mode Control Register (LPMCR) to
Enter the Standby Mode
● To access the low-power consumption mode control register (LPMCR) with assembler language
To set the low-power consumption mode control register (LPMCR) to enter the standby mode, use the
instruction listed in Table 8.3-2.
The low-power consumption mode transition included in Table 8.3-2 must always be followed by an array
of instructions highlighted by a line below.
137
CHAPTER 8 LOW-POWER CONTROL CIRCUIT
MOV
LPMCR, #H’XX
; the low-power mode transition instruction in Table 8.3-2
NOP
NOP
JMP
$+3
; jump to next instruction
MOV
A, #H’10
; any instruction
The device does not guarantee its operation after returning from the low-power consumption mode if you
place an array of instructions other than the one enclosed in the line.
● To access the low-power consumption mode control register (LPMCR) with C language
To enter the standby mode using the low-power consumption mode control register (LPMCR), use one of
the following methods (1) to (3) to access the register.
(1)Specify the standby mode transition instruction as a function and insert two _wait_nop() built-in
functions after that instruction. If any interrupt other than the interrupt to return from the standby mode
can occur within the function, optimize the function during compilation to suppress the LINK and
UNLINK instructions from occurring.
Example: Timebase timer mode transition function
Void enter_timebase(){
IO_LPMCR_byte = 0x10;
wait_nop();
wait_nop();
}
/* Set LPMCR TMD bit to 0 */
(2)Define the standby mode transition instruction using _asm statements and insert two NOP and JMP
instructions after that instruction.
Example: Transition to sleep mode
_asm(" MOV I:_IO_LPMCR, #H’58");
_asm(" NOP");
_asm(" NOP");
_asm(" JMP $+3");
/* Set LPMCR SLP bit to 1 */
/* Jump to next instruction */
(3)Define the standby mode transition instruction between #pragma asm and #pragma endasm and insert
two NOP and JMP instructions after that instruction.
Example: Transition to stop mode
#pragma asm
MOV I:_IO_LPMCR, #H’98
NOP
NOP
JMP $+3
#pragma endasm
138
/* Set LPMCR STP bit to 1 */
/* Jump to next instruction */;
CHAPTER 9
MEMORY ACCESS MODES
This chapter explains the functions and operations of
the memory access modes.
9.1 Outline of Memory Access Modes
9.2 Mode Pins
9.3 Mode Data
139
CHAPTER 9 MEMORY ACCESS MODES
9.1
Outline of Memory Access Modes
In the F2MC-16LX, the following two memory access modes are provided for each of the
access methods and access areas:
• Operation mode
• Bus mode
■ Memory Access Modes
Operation mode
RUN
Flash programming
Bus mode
Single chip
For the MB90945 series, the external bus function is not supported. Therefore the following part of this
document is not fully supported. In user applications, please use the MB90945 series in the single chip
mode.
To set the MB90945 series into the single chip mode, the mode inputs (MD2 to MD0) should be "011B"
and the most significant two bits of the mode data (M1 and M0) should be "00B".
● Operation mode
Operation mode means the mode for controlling the device operation status. The operation mode is
specified by the MDx mode setting pin and the Mx bit in mode data.
● Bus mode
Bus mode means the mode for controlling the internal ROM operation and external access function. The
bus mode is specified by the MDx mode setting pin and the Mx bit in mode data. The MDx mode setting
pin specifies the bus mode for reading the reset vector and mode data, and the Mx bit in mode data
specifies the bus mode for normal operation.
140
CHAPTER 9 MEMORY ACCESS MODES
9.2
Mode Pins
Table 9.2-1 describes the operations specified by combinations of the MD2 to MD0
external pins.
■ Mode Pins
Table 9.2-1 Mode Pins and Modes
Mode pin setting
Mode name
Reset vector
access area
External data
bus width
MD2
MD1
MD0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
Flash memory serial
programming *1, *2
-
-
1
1
1
Flash memory *2
-
-
Remarks
Reserved
Internal vector mode
Internal
(Mode data)
Reset sequence and later
segments are controlled
based on mode data.
Reserved
Mode for use of a
parallel programmer
*1: Data cannot be written only by setting the flash serial programming mode by mode pins.
Other must be set. For details, see the examples of flash memory serial programming connection.
*2: Not available on MB90V390HA/HB and MN90947A
141
CHAPTER 9 MEMORY ACCESS MODES
9.3
Mode Data
Mode data is stored at FFFFDFH of main memory and used for controlling the CPU
operation. This data is fetched during a reset sequence and stored in the mode register
inside the device. The mode register value can be changed only by a reset sequence.
The setting of this register is valid after the reset sequence.
Always set the reserved bits to "0".
■ Mode Data
Figure 9.3-1 shows the diagram of the setting of the bits.
Figure 9.3-1 Mode Data Structure
Mode data
7
6
5
4
3
2
1
0
M1
M0
0
0
0
0
0
0
Function extension bit (reserved area)
Bus mode setting bits
■ Bus Mode Setting Bits
These bits are used to specify the operation mode after the reset sequence is completed. Table 9.3-1 shows
the relationship between the bits and the functions.
Table 9.3-1 Bus Mode Setting Bits and Functions
142
M1
M0
0
0
0
1
1
0
1
1
Function
Single chip mode
(Inhibited)
CHAPTER 9 MEMORY ACCESS MODES
Figure 9.3-2 shows the diagram of the correspondence between the access areas and physical addresses for
each bus mode.
Figure 9.3-2 Access Areas and Physical Addresses in Each Bus Mode
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
FBFFFFH
FB0000H
FAFFFFH
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
ROM (FC bank)
ROM (FB bank)
ROM (FA bank)
FA0000H
F9FFFFH
F90000H
00FFFFH
008000H
0050FFH
004100H
003FFFH
ROM (F9 bank)
ROM (Image of
FF bank)
RAM 4 Kbytes
Peripheral
003500H
0030FFH
RAM 12 Kbytes
000100H
0000BFH
000000H
: No access
Peripheral
: Internal access
Note:
This is only an example for the demonstration of different access areas. Any specific device might
differ from the shown map. Please refer to the respective datasheet or Section "2.3 Memory Space
Map".
143
CHAPTER 9 MEMORY ACCESS MODES
■ Recommended Setting
Table 9.3-2 lists a sample recommended setting of mode pins and mode data.
Table 9.3-2 Sample Recommended Setting of Mode Pins and Mode Data
Sample setting
Single chip
MD2
MD1
MD0
M1
M0
0
1
1
0
0
Note:
For the MB90945 series devices with Flash memory, the mode data have predetermined values by the
hard-wired logic.
For more information, refer to Section "25.9 Reset Vector Address in Flash Memory".
144
CHAPTER 10
I/O PORTS
This chapter explains the functions and operations of
the I/O ports.
10.1 I/O Ports
10.2 I/O Port Registers
145
CHAPTER 10 I/O PORTS
10.1
I/O Ports
Each pin of the ports can be specified as input or output using the direction register if
the corresponding peripheral does not use the pin. When a pin is specified as input, the
logic level at the pin is read. When a pin is specified as output, the data register value is
read. The above also applies to a read operation for the read-modify-write instructions.
■ I/O Ports
When a pin is used as an output of other peripheral function, the peripheral output value is read regardless
of the direction register value.
It is generally recommended that the read-modify-write instructions should not be used for setting the data
register prior to setting the port as an output. This is because the read-modify-write instruction in this case
results reading the logic level at the port rather than the register value.
Figure 10.1-1 shows the block diagram of the I/O ports.
Figure 10.1-1 I/O Port Block Diagram
Internal data bus
Data register read
Data register
Data register write
Direction register
Direction register write
Direction register read
146
Pin
CHAPTER 10 I/O PORTS
10.2
I/O Port Registers
There are four types of I/O port registers:
• Port data register (PDR0 to PDRB)
• Port direction register (DDR0 to DDRB)
• Analog input enable register (ADER)
• Input level select register (ILSR)
■ I/O Port Registers
Figure 10.2-1 shows the I/O port registers.
Figure 10.2-1 I/O Port Registers
Bit
15/7
14/6
13/5
12/4
11/3
10/2
9/1
8/0
Address: 000000 H
P07
P06
P05
P04
P03
P02
P01
P00
Port data register (For Port 0) (PDR0)
Address: 000001 H
P17
P16
P15
P14
P13
P12
P11
P10
Port data register (For Port 1) (PDR1)
Address: 000002 H
P27
P26
P25
P24
P23
P22
P21
P20
Port data register (For Port 2) (PDR2)
Address: 000003 H
P37
P36
P35
P34
P33
P32
P31
P30
Port data register (For Port 3) (PDR3)
Address: 000004 H
P47
P46
P45
P44
P43
P42
P41
P40
Port data register (For Port 4) (PDR4)
Address: 000005 H
P57
P56
P55
P54
P53
P52
P51
P50
Port data register (For Port 5) (PDR5)
Address: 000006 H
P67
P66
P65
P64
P63
P62
P61
P60
Port data register (For Port 6) (PDR6)
Address: 000008 H
-
-
-
-
-
-
P81
P80
Port data register (For Port 8) (PDR8)
Address: 000009 H
P97
P96
P95
P94
P93
P92
P91
P90
Port data register (For Port 9) (PDR9)
Address: 00000A H
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Port data register (For Port A) (PDRA)
Address: 00000B H
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Port data register (For Port B) (PDRB)
Address: 000010 H
D07
D06
D05
D04
D03
D02
D01
D00
Port direction register (For Port 0) (DDR0)
Address: 000011 H
D17
D16
D15
D14
D13
D12
D11
D10
Port direction register (For Port 1) (DDR1)
Address: 000012 H
D27
D26
D25
D24
D23
D22
D21
D20
Port direction register (For Port 2) (DDR2)
Address: 000013 H
D37
D36
D35
D34
D33
D32
D31
D30
Port direction register (For Port 3) (DDR3)
Address: 000014 H
D47
D46
D45
D44
D43
D42
D41
D40
Port direction register (For Port 4) (DDR4)
Address: 000015 H
D57
D56
D55
D54
D53
D52
D51
D50
Port direction register (For Port 5) (DDR5)
Address: 000016 H
D67
D66
D65
D64
D63
D62
D61
D60
Port direction register (For Port 6) (DDR6)
Address: 000018 H
-
-
-
-
-
-
D81
D80
Port direction register (For Port 8) (DDR8)
Address: 000019 H
D97
D96
D95
D94
D93
D92
D91
D90
Port direction register (For Port 9) (DDR9)
Address: 00001A H
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
Port direction register (For Port A) (DDRA)
Address: 00001B H
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Port direction register (For Port B) (DDRB)
15/7
14/6
13/5
12/4
11/3
10/2
9/1
8/0
Address: 00000C H
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
Address: 00000D H
ADSEL
ADE14
ADE13
ADE12
ADE11
ADE10
ADE9
ADE8
Bit
Analog input enable register (For Port 6)
(ADER0)
Analog input enable register (For Port B)
(ADER1)
147
CHAPTER 10 I/O PORTS
10.2.1
Port Data Register
Note that R/W for I/O ports differ from R/W for memory in the following points:
• Input mode
Read: The level at the corresponding pin is read.
Write: Data is written to an output latch.
• Output mode
Read: The data register latch value is read.
Write: Data is written to an output latch and output to the corresponding pin.
■ Port Data Register
Figure 10.2-2 shows the port data registers.
Figure 10.2-2 Port Data Registers
PDR0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
Access
Address: 000000H
P07
P06
P05
P04
P03
P02
P01
P00
Undefined
R/W
PDR1
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Address: 000001H
P17
P16
P15
P14
P13
P12
P11
P10
Undefined
R/W
Undefined
R/W
Undefined
R/W
Undefined
R/W
Undefined
R/W
Undefined
R/W
Undefined
R/W
Undefined
R/W
Undefined
R/W
Undefined
R/W
PDR2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Address: 000002H
P27
P26
P25
P24
P23
P22
P21
P20
PDR3
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Address: 000003H
P37
P36
P35
P34
P33
P32
P31
P30
PDR4
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Address: 000004H
P47
P46
P45
P44
P43
P42
P41
P40
PDR5
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Address: 000005H
P57
P56
P55
P54
P53
P52
P51
P50
PDR6
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Address: 000006H
P67
P66
P65
P64
P65
P62
P61
P60
PDR8
bit7
bit6
bit5
bit4
bit3
bit2
Address: 000008H
bit1
bit0
P81
P80
PDR9
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Address: 000009H
P97
P96
P95
P94
P93
P92
P91
P90
PDRA
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Address: 00000AH
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PDRB
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Address: 00000BH
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Note:
Bit7 to bit2 of PDR8 are reserved. They must always be written to "0". Reading them returns "X".
These bits physically exist in MB90V390HA/HB but they do not exist in the other devices of MB90945 series.
148
CHAPTER 10 I/O PORTS
■ Reading the Port Data Register
When a port data register is read, the value depends on the corresponding bit in the port direction register
and on the current status of the resource that is connected to the same pin (if applicable).
The following cases are possible:
DDR value
Resource
Read value
0 (input)
enabled
Resource value
1 (output)
enabled
Resource value
0 (input)
disabled
Pin value
1 (output)
disabled
PDR value
149
CHAPTER 10 I/O PORTS
10.2.2
Port Direction Register
When a pin is used as a port, the corresponding pin is controlled as described below:
0: Input mode
1: Output mode
■ Port Direction Register
Figure 10.2-3 shows the port direction registers.
Figure 10.2-3 Port Direction Registers
DDR0
Initial value
Access
00000000B
R/W
bit8
D10
00000000B
R/W
bit1
D21
bit0
D20
00000000B
R/W
bit10
D32
bit9
D31
bit8
D30
00000000B
R/W
bit3
D43
bit2
D42
bit1
D41
bit0
D40
00000000B
R/W
bit12
D54
bit11
D53
bit10
D52
bit9
D51
bit8
D50
00000000B
R/W
bit5
D65
bit4
D64
bit3
D65
bit2
D62
bit1
D61
bit0
D60
00000000B
R/W
bit5
bit4
bit3
bit2
bit1
D81
bit0
D80
00000000B
R/W
bit7
D07
bit6
D06
bit5
D05
bit4
D04
bit3
D03
bit2
D02
bit1
D01
bit0
D00
bit15
D17
bit14
D16
bit13
D15
bit12
D14
bit11
D13
bit10
D12
bit9
D11
bit7
D27
bit6
D26
bit5
D25
bit4
D24
bit3
D23
bit2
D22
bit15
D37
bit14
D36
bit13
D35
bit12
D34
bit11
D33
bit7
D47
bit6
D46
bit5
D45
bit4
D44
bit15
D57
bit14
D56
bit13
D55
Address: 000016H
bit7
D67
bit6
D66
DDR8
bit7
bit6
Address: 000010H
DDR1
Address: 000011H
DDR2
Address: 000012H
DDR3
Address: 000013H
DDR4
Address: 000014H
DDR5
Address: 000015H
DDR6
Address: 000018H
DDR9
Address: 000019H
DDRA
Address: 00001AH
DDRB
Address: 00001BH
bit15
D97
bit14
D96
bit13
D95
bit12
D94
bit11
D93
bit10
D92
bit9
D91
bit8
D90
00000000B
R/W
bit7
DA7
bit6
DA6
bit5
DA5
bit4
DA4
bit3
DA3
bit2
DA2
bit1
DA1
bit0
DA0
00000000B
R/W
bit15
DB7
bit14
DB6
bit13
DB5
bit12
DB4
bit11
DB3
bit10
DB2
bit9
DB1
bit8
DB0
00000000B
R/W
Note:
Bit7 to bit2 of DDR8 are reserved. They must always be written to "0". Reading them returns "X".
These bits physically exist in MB90V390HA/HB but they do not exist in the other devices of MB90945 series.
■ Reading the Port Direction Register
The port direction register can be read independently from the status of the corresponding resource.
However, the value of the DDR influences the result of a read access on the port data register.
150
CHAPTER 10 I/O PORTS
10.2.3
Analog Input Enable Register
This register controls the port 6 and port B pins as described below:
0: Port input/output mode
1: Analog input mode
If an external pin is used as an analog input for the A/D converter, the corresponding bit
should be set to "1".
■ Analog Input Enable Registers
Figure 10.2-4 shows the analog input enable register.
Figure 10.2-4 Analog Input Enable Registers (ADER1/ADER0)
Address:
bit15
bit14
bit13
bit12
bit11
bit10
bit9
ADER1
ADSEL ADE14 ADE13 ADE12 ADE11 ADE10 ADE9
0000000DH R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
ADER0
ADE7
0000000CH R/W
bit8
Initial value
ADE8
R/W
01111111B
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ADE6
R/W
ADE5
R/W
ADE4
R/W
ADE3
R/W
ADE2
R/W
ADE1
R/W
ADE0
R/W
11111111B
R/W: Readable/writable
Note:
If bit15 (ADSEL) is set to "0" the pins ANIN 0 to ANIN 7 (Port P60 to P67) are selected as inputs for
the A/D Converter. If this bit is set to "1" the pins ANIN 8 to ANIN 14 (Port PB0 to PB6) are selected
as inputs for the A/D Converter.
151
CHAPTER 10 I/O PORTS
10.2.4
Input Level Select Register (MB90V390HA/HB only)
In MB90V390HA/HB, the input level select register (ILSR) allows to switch from
automotive hysteresis input levels to CMOS hysteresis input levels. In the other
MB90945 series devices, the input levels are hardwired, and the ILSR register does not
exist. To set MB90V390HA/HB to the same input level configuration as the other
MB90945 series devices, the value 5000H must be written to ILSR. For other MB90945
series devices, writing to the ILSR register addresses is ignored.
■ Input Level Select Register (MB90V390HA/HB Only)
In MB90V390HA/HB, the input level select register ILSR is located on addresses 0EH and 0FH.
Figure 10.2-5 Input Level Select Register (ILSR)
Address:
bit15
0000000FH ILSPB
R/W
0000000EH
bit14
ILI2C
R/W
bit13
bit12
ILRX0 ILRX1
R/W
R/W
bit11
bit10
bit9
bit8
Initial value
ILB
R/W
ILA
R/W
IL9
R/W
IL8
R/W
00000000B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IL7
R/W
IL6
R/W
IL5
R/W
IL4
R/W
IL3
R/W
IL2
R/W
IL1
R/W
IL0
R/W
00000000B
R/W: Readable/writable
[bit15] ILSPB
If the ILSPB bit is set to "0", the input level of P44 will be selected by IL4 (bit4 of ILSR). If the
ILSPB bit is set to "1", the input level of P44 will be the opposite of the one selected by the IL4 bit.
The initial value of this bit is "0".
The initial value of this register is 0000H, so for MB90V390HA/HB, the input levels for all ports
will be "Automotive Hysteresis" after reset. To set MB90V390HA/HB to the same input level
configuration as the other MB90945 series devices, the value 5000H must be written to this register.
[bit14] ILI2C
If the ILI2C bit is set to "0", the input level of P42/SDA and P43/SCL will be selected by IL4 (bit4
of ILSR). If the ILI2C bit is set to "1", the input level of P42/SDA and P43/SCL will be the opposite
of the one selected by the IL4 bit. The initial value of this bit is "0".
[bit13] ILRX0
If the ILRX0 bit is set to "0", the input level of P30/RX0 will be selected by IL3 (bit3 of ILSR). If
the ILRX0 bit is set to "1", the input level of P30/RX0 will be the opposite of the one selected by the
IL3 bit. The initial value of this bit is "0".
[bit12] ILRX1
If the ILRX1 bit is set to "0", the input level of P21/RX1 will be selected by IL2 (bit2 of ILSR). If
the ILRX1 bit is set to "1", the input level of P21/RX1 will be the opposite of the one selected by the
IL2 bit. The initial value of this bit is "0".
152
CHAPTER 10 I/O PORTS
[bit11 to bit0] ILB to IL0
These bits set the input level of the corresponding port. IL0 sets the input level of Port0, ILB sets the
input level of PortB. Setting these bits to "0" selects the "Automotive Hysteresis" input level, setting
these bits to "1" selects the "CMOS Hysteresis" input level. The initial value of these bits is "0".
153
CHAPTER 10 I/O PORTS
154
CHAPTER 11
TIMEBASE TIMER
This chapter explains the functions and operations of
the timebase timer.
11.1 Outline of Timebase Timer
11.2 Timebase Timer Control Register
11.3 Operations of Timebase Timer
155
CHAPTER 11 TIMEBASE TIMER
11.1
Outline of Timebase Timer
The timebase timer consists of an 18-bit timebase counter and a control register. The
18-bit timebase counter divides the system clock. The timebase timer issues interrupts
at specified intervals based on carry signals of the timebase counter.
■ Outline of Timebase Timer
When the power is turned-on, the timebase counter can be cleared to all zeroes by setting the stop mode or
by software (writing "0" to the TBR bit). The timebase counter is incremented while the source oscillation
is input.
The timebase counter can be used as a timer for supplying clock to the watch-dog timer or for waiting for
the oscillation to stabilize.
■ Block Diagram of Timebase Timer
Figure 11.1-1 shows a block diagram of the timebase timer.
Figure 11.1-1 Block Diagram of Timebase Timer
WTE
Output enable
WT1
WT0
Two-bit
counter
Selector
Reset
control
Reset
Timebase counter
f/2
Power-on
reset
STOP
mode
1
1
1
1
1
1
1
1
2
11
12
13
14
15
16
17
2
Selector
1/210 to 1/217
WS1
156
2
2
2
TBOF
TBC1
WS0
2
Clear
control
TBR
TBC0
2
Selector
2
1
218
IRQ
TBOF
Clear
EI 2OS
Timebase devision output
Osciliation stabilization wait completion signal
CHAPTER 11 TIMEBASE TIMER
11.2
Timebase Timer Control Register
The timebase timer control register controls interrupts of the timebase timer and can
clear the timebase counter.
■ Timebase Timer Control Register (TBTC)
Figure 11.2-1 Configuration of the Timebase Timer Control Register (TBTC)
Address:
0000A9H
bit15 bit14 bit13 bit12 bit11 bit10 bit9
Reserved
-
-
TBIE TBOF TBR TBC1 TBC0
R/W
-
-
R/W R/W
W
Initial value
1XX00100 B
bit8
R/W R/W
TBC1
TBC0
0
0
1.024 ms (at 4 MHz)
Timebase timer interval control bits
0
1
4.096 ms (at 4 MHz)
1
0
16.384 ms (at 4MHz)
1
1
131.072 ms (at 4 MHz)
Timebase timer reset bit
TBR
0
1
TBOF
Read
Write
Clear all bits to "0"
Always "1"
No effect
Timebase timer interrupt request flag bit
Read
Write
0
No interrupt
Clear this bit
1
Interrupt request
No effect
TBIE
Timebase timer interrupt enable bit
0
Disable Interrupt
1
Enable Interrupt
Undefined bit
-
-
Undefined bit
-
Reserved
0
R/W
W
X
-
:
:
:
:
Readable / writable
Write only (read always returns "0")
Undefined value
Undefined
:
Initial value
1
-
Reserved bit
Always write"1" to this bit
157
CHAPTER 11 TIMEBASE TIMER
Table 11.2-1 Function Description of Each Bit of the Timebase Timer Control Register
Bit name
Function
bit15
Reserved
This is a reserved bit. When writing data to the TBTC register ensure that "1" is
written to this bit.
bit14, bit13
Undefined
-
bit12
TBIE:
Timebase timer
interrupt enable bit
This bit is used to enable interval interrupts based on the timebase timer. Writing
"1" to this bit enables interrupts, and writing "0" disables interrupts. This bit is
initialized to "0" upon a reset. This bit is readable and writable.
bit11
TBOF:
Timebase timer
interrupt request flag
bit
This is an interrupt request flag for the timebase timer. While the TBIE bit is "1",
an interrupt request is issued when "1" is written to TBOF. This bit is set to "1" for
each interval specified with the TBC1 and TBC0 bits.
This bit is cleared by writing "0", transition to stop or a reset. Writing "1" has no
effect.
"1" is always read by a read-modify-write instruction.
bit10
TBR:
Timebase timer reset
bit
This bit clears all bits of the timebase timer counter to "0".
Writing "0" clears the timebase counter.
Writing "1" has no effect.
"1" is always read from this bit.
bit9, bit8
TBC1, TBC0:
Timebase timer
interval control bits
These bits are used to set the timebase timer interval.
Table 11.2-2 lists the specifiable intervals.
Table 11.2-2 shows the settings for TBC1 and TBC0:
Table 11.2-2 Selecting the Timebase Timer Interval
158
TBC1
TBC0
Interval at 4 MHz source oscillation
0
0
1.024 ms
0
1
4.096 ms
1
0
16.384 ms
1
1
131.072 ms
CHAPTER 11 TIMEBASE TIMER
11.3
Operations of Timebase Timer
The timebase timer functions as a watch-dog timer clock source, timer for waiting for
the oscillation to stabilize, and interval timer for generating interrupts at specified
intervals.
■ Timebase Counter
The timebase counter consists of an 18-bit counter for a clock generated by dividing the source oscillation
input by two. This clock is used to generate the machine clock. While the source oscillation is input, the
timebase counter keeps counting. The timebase counter is cleared by a power-on reset, transition to stop or
writing "0" to the TBR bit of the TBTC register.
■ Interval Interrupt Function
Interrupts are generated at specified intervals according to the carry signals of the timebase counter. The
TBOF flag is set at the intervals specified with the TBC1 and TBC0 bits of the TBTC register. The flag is
written to reference to the time at which the timebase timer is cleared last.
Upon transition to stop mode, the timebase timer is used as a timer for waiting for the oscillation to
stabilize upon recovery. Therefore, the TBOF flag is immediately cleared upon mode transition.
159
CHAPTER 11 TIMEBASE TIMER
160
CHAPTER 12
WATCH-DOG TIMER
This chapter explains the functions and operations of
the watch-dog timer.
12.1 Outline of Watch-Dog Timer
12.2 Watch-Dog Timer Operation
161
CHAPTER 12 WATCH-DOG TIMER
12.1
Outline of Watch-Dog Timer
The watch-dog timer consists of a two-bit watch-dog counter, control register, and
watch-dog reset controller. The two-bit watch-dog counter uses the carry signals of an
18-bit timebase counter as a clock source.
■ Watch-dog Timer Block Diagram
Figure 12.1-1 shows the diagram of the configuration of the watch-dog timer.
Figure 12.1-1 Watch-dog Timer Block Diagram
Watch-dog timer control register (WDTC)
PONR
WRST ERST SRST WTE WT1 WT0
Watch-dog timer
2
Activate
Reset occurrence
Sleep mode
Timebase timer mode
Stop mode
Counter clear
control circuit
Count clock
selector
Deactivate
2-bit counter
Reset
occurrence
Watch-dog reset
generation circuit
Internal reset
generation
circuit
Clear
4
(Timebase timer counter)
Main clock
(HCLK divided by 2)
HCLK : Oscillation clock
162
21
22
28
29
210
211 212
213
214
215
216
217 218
CHAPTER 12 WATCH-DOG TIMER
■ Watch-dog Timer Control Register (WDTC)
Figure 12.1-2 Configuration of Watch-dog Timer Control Register (WDTC)
Address :
0000A8H
bit7
bit6
PONR
-
R
-
bit5
bit4
WRST ERST SRST
R
R
bit2
bit1
bit0
Initial value
WTE
WT1
WT0
XXXXX111B
W
W
W
bit3
R
R : Read only
W : Write only
X : Undefined value
- : Undefined
[bit7, bit5 to bit3] PONR, WRST, ERST, and SRST
These flags indicate the reset causes. The flags are set upon a reset as described in Table 12.1-1.
All bits are cleared to "0" after the WDTC register is read. These bits are read-only bits.
Table 12.1-1 Reset Cause Registers
Reset cause
PONR
WRST
ERST
SRST
Power-on
1
-
-
-
Watch-dog timer
*
1
*
*
External pin
*
*
1
*
RST bit
*
*
*
1
*: The previous value is maintained.
[bit2] WTE
While the watch-dog timer is stopped, writing "0" to this bit activates the watch-dog timer.
Subsequently, writing "0" clears the watch-dog timer counter. Writing "1" has no effect.
The watch-dog timer is stopped by power-on or reset by watch-dog timer. "1" is always read from this
bit.
163
CHAPTER 12 WATCH-DOG TIMER
[bit1, bit0] WT1, WT0
These bits are used to select the watch-dog timer interval. Only the data items written during watch-dog
timer activation are valid. Data items that are written outside watch-dog timer activation are ignored.
Table 12.1-2 lists the interval settings.
These bits are write only bits.
Table 12.1-2 Watch-dog Timer Interval Selection Bit
Interval *
WT1
WT0
Main clock cycle count
Minimum
Maximum
0
0
approx. 3.58 ms
approx. 4.61 ms
214 plus or minus 211
cycles
0
1
approx. 14.33 ms
approx. 18.43 ms
216 plus or minus 213
cycles
1
0
approx. 57.23 ms
approx. 73.73 ms
218 plus or minus 215
cycles
1
1
approx. 458.7 ms
approx. 589.82 ms
221 plus or minus 218
cycles
*: For a source oscillation of 4 MHz.
Note:
The interval time uses the carry signal of the timebase timer or clock timer as a count clock. If the
timebase timer or clock timer is cleared, the interval time of the watch-dog timer may become long.
The time-base timer is also cleared by writing zero to the TBR bit in the timebase timer control register
(TBTC), transition from main clock mode to PLL clock mode.
164
CHAPTER 12 WATCH-DOG TIMER
12.2
Watch-Dog Timer Operation
The watch-dog timer function enables detection of program surge.
If the watch-dog timer is not accessed within the specified time due to, for example, a
program surge, the watch-dog timer resets the system.
■ State transition diagram of the Watch-dog Timer
The watch-dog timer has four states:
Inactive: The watch-dog timer does not operate.
Running: The watch-dog counter is counting up from 0.
Stopped: The watch-dog counter is stopped at count value 0.
Overflow: The watch-dog counter asserts a watch-dog reset.
Figure 12.2-1 State transition diagram of the Watch-dog Timer
Inactive
(Initial State)
Write "0"
to WTE
Reset
Reset
Running
Start counting from 0
Release of stop mode by interrupt
Release of timebase timer mode by interrupt
Release of sleep mode by interrupt
Stopped
count = 0
Transition to stop mode
Transition to timebase timer mode
Transition to sleep mode
Counter
overflow
Overflow
Assert watch-dog reset
Always
Write "0" to WTE
165
CHAPTER 12 WATCH-DOG TIMER
■ Activation
The watch-dog timer is activated by writing "0" to the WTE bit of the WDTC register while the watch-dog
timer is stopped. At the same time, the WT1 and WT0 bits are used to set the watch-dog timer reset
interval. Only the interval setting specified during activation is valid.
■ Watch-dog Counter
Once the watch-dog timer is activated, the watch-dog timer counter must be periodically cleared within the
program. Writing "0" to the WTE bit of the WDTC register clears the watch-dog counter. The watch-dog
counter consists of a two-bit counter which uses the carry signals of the timebase timer as a clock source.
Therefore, the watch-dog reset time may become longer than the setting if the timebase counter is cleared.
Figure 12.2-2 is a diagram of the watch-dog timer operation.
Figure 12.2-2 Watch-dog Timer Operation
Timebase
Watch-dog
00
01
10
00
01
10
11
00
WTE write
Watch-dog
activation
Watch-dog
clear
Watch-dog reset
■ Watch-dog Stop
The watch-dog timer is stopped by transition to stop mode, timebase timer mode or sleep mode.
■ Watch-dog deactivation
The watch-dog timer is deactivated by any kind of reset
■ Watch-dog timer behavior in stop mode, timebase timer mode, and sleep mode
When transition to stop mode, timebase timer, mode or sleep mode occurs, watch-dog timer is cleared and
stops. When CPU is release from stop mode, timbase timer mode, or sleep mode, watch-dog timer starts
counting again from cleared state (Table 12.2-1).
166
CHAPTER 12 WATCH-DOG TIMER
■ Watch-dog timer behavior at reset
When any kind of reset is asserted, the watch-dog timer is deactivated and remains inactive after reset is
released (Table 12.2-1).
Table 12.2-1 : Watch-dog timer clear and stop conditions
Mode
Reset
WDTC
register
WTE=0
Stop mode
Sleep mode
Timebase
timer mode
Transition
to the mode
Writing
to the register
Transition
to the mode
Transition
to the mode
Transition
to the mode
Watch-dog state during
the mode
Inactive
N/A
Stopped
(keep cleared)
Stopped
(keep cleared)
Stopped
(keep cleared)
Watch-dog reset during
the mode
Does not occur
N/A
Does not occur
Does not occur
Does not occur
Inactive
Running (start
counting from
cleared state)
Running (start
counting from
cleared state)
Running (start
counting from
cleared state)
Running (start
counting from
cleared state)
Counter clear timing
Watch-dog state after
leaving the mode
This Table assumes that the previous watch-dog state was "Running".
167
CHAPTER 12 WATCH-DOG TIMER
168
CHAPTER 13
16-BIT I/O TIMER
This chapter explains the functions and operations of
the 16-bit I/O timer.
13.1 Outline of 16-Bit I/O Timer
13.2 16-Bit I/O Timer Registers
13.3 16-Bit Free Run Timer
13.4 Output Compare
13.5 Input Capture
169
CHAPTER 13 16-BIT I/O TIMER
13.1
Outline of 16-Bit I/O Timer
The MB90945 series contains two 16-bit free run timer modules, two output compare
modules, and three input capture modules and supports six input channels and four
output channels. The following sections describe the 16-bit free run timer, Output
Compare and Input Capture.
■ 16-bit Free Run Timer
The two 16-bit free-run timers consist of a 16-bit up counter, control register, and prescaler each. The
values output from these timer counters are used as the base timer for input capture and output compare.
● Eight counter clocks are available.
Internal clock: φ, φ/2, φ /4, φ/8, φ/16, φ/32, φ/64, φ/128 (φ is machine clock)
● An interrupt can be generated upon a counter overflow or a match with compare register 0 and 1.
● The counter value can be initialized to "0000H" upon a reset, software clear, or match with compare
register 0 (for MB90V390HA/HB, free run timer 1 can not be cleared by a match with compare register
0 but with compare register 4).
■ Output Compare (2 Channels Per One Module)
The two output compare modules consist of two 16-bit compare registers, compare output latch, and
control register each.
Output compare 0 and 1 (channels OUT0, OUT1, OUT2 and OUT3) are assigned to free run timer 0.
When a 16-bit free run timer value matches the corresponding compare register value, the output level is
reversed and an interrupt can be issued.
● The two compare registers can be used independently for each output compare.
Output pins and interrupt flags corresponding to compare registers
● Output pins can be controlled based on pairs of the two compare registers.
Output pins can be reversed by using the two compare registers.
● Initial values for output pins can be set.
● Interrupts can be generated upon a compare match.
170
CHAPTER 13 16-BIT I/O TIMER
■ Input Capture (2 Channels Per One Module)
The three input capture modules consist of two 16-bit capture registers and control registers each
corresponding to two independent external input pins.
Input capture 0 (channels IN0 and IN1) is assigned to free run timer 0 and input capture 1 and 2 (channels
IN2, IN3, IN4 and IN5) are assigned to free run timer 1.
The 16-bit free run timer values can be stored in the capture register and an interrupt is issued
simultaneously upon detection of an edge of a signal input from an external input pin.
● The detection edge of an external input signal can be specified.
Rising, falling, or both edges
● Two input channels can operate independently.
● An interrupt can be issued upon a valid edge of an external input signal.
The intelligent I/O service can be activated upon an input capture interrupt.
■ Block Diagram of 16-bit I/O Timer
Figure 13.1-1 shows the block diagram of the 16-bit I/O timer.
Figure 13.1-1 Block Diagram of 16-bit I/O Timer
Control logic
To each block
Interrupt
16-bit free run timer 0/1
16-bit timer
FRCK
Bus
Clear
Output compare 0/2
Compare register 0
T Q
OUT0
OUT2
T Q
OUT1
OUT3
Output compare 1/3
Compare register 1
Input capture 0/2/4
Capture register 0
Input capture 1/3/5
Capture register 1
Edge selection
IN0
IN2
IN4
Edge selection
IN1
IN3
IN5
171
CHAPTER 13 16-BIT I/O TIMER
13.2
16-Bit I/O Timer Registers
The 16-bit I/O timer has the following three registers:
• 16-bit free run timer register
• 16-bit output compare register
• 16-bit input capture register
■ 16-bit Free Run Timer 0 and 1
bit15
bit0
00352C H
TCDT0
Timer data register 0
00353C H
TCDT1
Timer data register 1
00352E H
TCCSH0
TCCSL0
Timer status register 0
00353E H
TCCSH1
TCCSL1
Timer status register 1
■ 16-bit Output Compare
bit15
172
bit0
003530 H
003532 H
OCCP0/1
Compare register 0/1
003534 H
003536 H
OCCP2/3
Compare register 2/3
000058 H
000059 H
OCS1
OCS0
Control status register 0/1
00005A H
00005B H
OCS3
OCS2
Control status register 2/3
CHAPTER 13 16-BIT I/O TIMER
■ 16-bit Input Capture
bit15
bit0
003520 H
003522 H
IPCP0/1
Capture register 0/1
003524 H
003526 H
IPCP2/3
Capture register 2/3
003528 H
00352A H
IPCP4/5
Capture register 4/5
000054 H
000055 H
ICS0/1
0035C9 H
ICS4/5
ICE01
0035CAH
0035CBH
Control register 2/3
ICS2/3
000056 H
Control register 4/5
Capture Edge register 0/1
ICE23
ICE45
Control register 0/1
Capture Edge register 2/3
Capture Edge register 4/5
173
CHAPTER 13 16-BIT I/O TIMER
13.3
16-Bit Free Run Timer
The 16-bit free run timer consists of a 16-bit up counter and a control status register.
The count values of this timer are used as the base timer for the output compares and
input captures.
• Eight counter clock frequencies are available.
• An interrupt can be generated upon a counter value overflow.
• The counter value can be initialized upon a match with compare register 0, depending
on the mode.
• Two separate timers are available on MB90945 series.
■ 16-bit Free Run Timer Block Diagram
Figure 13.3-1 16-bit Free Run Timer Block Diagram
φ
Interrupt request
IVF
IVFE STOP MODE CLR CLK2 CLK1 CLK0
Divider
FRCK
Comparator 0 /1
Bus
16-bit up counter
Clock
Count value output
Note: The figure above is also valid for timer 1
Timer 0 is connected to ICU0/1 and OCU0/1/2/3
Timer 1 is connected to ICU2/3/4/5
174
T15
to
T00
CHAPTER 13 16-BIT I/O TIMER
13.3.1
Data Register
The data register can read the count value of the 16-bit free run timer. The counter value
is cleared to "0000" upon a reset. The timer value can be set by writing a value to this
register. However, ensure that the value is written while the operation is stopped
(STOP=1).
The data register must be accessed by the word access instructions.
■ Data Register of Free Run Timer
Figure 13.3-2 Configuration of the Data Register of Free Run Timer (TCDT0/1)
Address:
TCDT0/1
00352CH
00352DH
00353CH
00353DH
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
Tn15 Tn14 Tn13 Tn12 Tn11 Tn10 Tn9 Tn8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Tn7 Tn6 Tn5 Tn4 Tn3 Tn2 Tn1 Tn0
Initial value
0000000000000000B
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCDT0/1
Lower bits
Tn0
Timer Data Register 0
Tn1
Timer Data Register 1
Tn2
Timer Data Register 2
Tn3
Timer Data Register 3
Tn4
Timer Data Register 4
Tn5
Timer Data Register 5
Tn6
Timer Data Register 6
Tn7
Timer Data Register 7
n = 0, 1
TCDT0/1
R/W: Readable / writable
Upper bits
Tn8
Timer Data Register 8
Tn9
Timer Data Register 9
Tn10
Timer Data Register 10
Tn11
Timer Data Register 11
Tn12
Timer Data Register 12
Tn13
Timer Data Register 13
Tn14
Timer Data Register 14
Tn15
Timer Data Register 15
n = 0, 1
The 16-bit free run timer is initialized upon the following factors:
•
Reset
•
Clear bit (CLR) of control status register
•
A match between compare register 0 and the timer counter value.
For MB90V390HA/HB, free run timer 1 cannot be initialized upon a match with compare register 0 but
upon a match with compare register 4. Refer to the MB90390 Series Hardware manual for details.
175
CHAPTER 13 16-BIT I/O TIMER
13.3.2
Control Status Register
The control status register sets the operation mode of the 16-bit free run timer, starts
and stops the 16-bit free run timer, and controls interrupts.
■ Control Status Register of Free Run Timer (Lower)
Figure 13.3-3 Configuration of the Control Status Register of Free Run Timer (TCCSL0/1)
Address:
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
TCCSL0/1
IVF IVFE STOP MODE CLR CLK2 CLK1 CLK0
00352EH
00353EH R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
00000000B
CLK2
CLK1
0
0
0
φ
0
0
1
φ/2
0
1
0
φ/4
0
1
1
φ/8
1
0
0
φ / 16
1
0
1
φ / 32
1
1
0
φ / 64
1
1
1
φ / 128
CLK0
Count clock selection bits
φ = MCU clock
CLR
0
1
MODE
Read always "0"
Write
No effect
Clear timer to "0000B"
Set reset condition of timer bit
Initialization by reset or clear bit
1
Initialization by reset, clear bit, or compare register 0 (4)
1
IVFE
Stop the timer bit
Counter enabled
Counter disabled (stop)
Interrupt enable bit
0
Interrupt disabled
1
Interrupt enabled
IVF
176
Read
0
STOP
0
R/W
Clear timer bit
Interrupt request flag bit
Read
Write
: Readable / writable
0
No interrupt
Clear this bit
: Initial value
1
Interrupt request
No effect
CHAPTER 13 16-BIT I/O TIMER
Table 13.3-1 Control Status Register of Free Run Timer (Lower)
Bit name
Function
bit7
IVF:
Interrupt request flag
bit
This bit is the interrupt request flag bit and clear bit
• Writing "0": A possible interrupt is cleared.
• Writing "1": No effect.
• "1" is always read during a read-modify-write cycle.
bit6
IVFE:
Interrupt enable bit
This bit enables the interrupt request
• Writing "0": Interrupt disabled.
• Writing "1": Interrupt enabled.
bit5
STOP:
Stop the timer bit
This bit stops the timer.
• Writing "0": Counter enabled (operation).
• Writing "1": Counter disabled (stop).
bit4
MODE:
Set reset condition of
timer bit
• "0": Initialization by reset or clear bit
• "1": Initialization by reset, clear bit, or compare register 0
For MB90V390HA/HB, free run timer 1 cannot be initialized upon a match with
compare register 0 but upon a match with compare register 4. Refer to the MB90390
Series Hardware manual for details.
bit3
CLR:
Clear timer bit
This bit initializes the operating free run timer to the value "0000"
• Writing "0": no effect.
• Writing "1": Counter is initialized.
Note:
To initialize the counter value while the timer is stopped, write "0000" to the data
register.
bit2 to
bit0
CLK2 to CLK0:
Count clock selection
bits
These bits select the count clock for the 16-bit free run timer. The clock is updated
immediately after a value is written to these bits. Therefore, ensure that the input
capture operations are stopped before a value is written to these bits.
CLK2
CLK1
CLK0
Count
clock
φ = 20
MHz
φ = 16
MHz
φ =8
MHz
φ =4
MHz
φ =1
MHz
0
0
0
φ
50 ns
62.5 ns
125 ns
0.25 μs
1 μs
0
0
1
φ /2
100 ns
125 ns
0.25 μs
0.5 μs
2 μs
0
1
0
φ /4
0.2 μs
0.25 μs
0.5 μs
1 μs
4 μs
0
1
1
φ /8
0.4 μs
0.5 μs
1 μs
2 μs
8 μs
1
0
0
φ / 16
0.8 μs
1 μs
2 μs
4 μs
16 μs
1
0
1
φ / 32
1.6 μs
2 μs
4 μs
8 μs
32 μs
1
1
0
φ / 64
3.2 μs
4 μs
8 μs
16 μs
64 μs
1
1
1
φ / 128
6.4 μs
8 μs
16 μs
32 μs
128 μs
177
CHAPTER 13 16-BIT I/O TIMER
■ Control Status Register of Free Run Timer (Upper)
Figure 13.3-4 Configuration of the Control Status Register of Free Run Timer (TCCSH0/TCCSH1)
Address:
TCCSH0/1
00352FH
00353FH
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
Initial value
0XXXXXXX B
ECKE
R/W
-
-
-
-
-
-
ECKE
R/W
: Readable / writable
-
: Undefined
External clock enable bit
0
Internal time clock
1
External clock from FRCK
: Initial value
Table 13.3-2 Control Status Register of Free Run Timer (Upper)
Bit name
bit15
ECKE:
External clock enable
bit
bit14 to
bit8
Undefined
178
Function
This bit chose between internal time clock and external clock from FRCK
• Writing "0": Internal clock selected.
• Writing "1": External clock selected.
-
CHAPTER 13 16-BIT I/O TIMER
13.3.3
16-Bit Free Run Timer Operation
The 16-bit free run timer starts counting from counter value "0000" after the reset is
released. The counter value is used as the reference time for the 16-bit output compare
and 16-bit input capture operations.
■ 16-bit Free Run Timer Operation
The counter value is cleared in the following conditions:
•
When an overflow occurs
•
When a match with the output compare register 0 (4) occurs (This depends on the mode.)
•
When "1" is written to the CLR bit of the TCCS register during operation
•
When "0000" is written to the TCDT register during stop
•
Reset
An interrupt can be generated when an overflow occurs or when the counter is cleared by a match with the
compare register 0 (4). (Compare match interrupts can be used only in an appropriate mode.)
■ Clearing the Counter by an Overflow
Figure 13.3-5 Clearing the Counter by an Overflow
Counter value
FFFF H
Overflow
BFFF H
7FFF H
3FFF H
0000 H
Time
Reset
Interrupt
179
CHAPTER 13 16-BIT I/O TIMER
■ Clearing the Counter upon a Match with Output Compare Register 0 (4)
Figure 13.3-6 Clearing the Counter upon a Match with Output Compare Register 0 (4)
Counter value
FFFF H
Match
BFFF H
Match
7FFF H
3FFF H
Time
0000 H
Reset
Compare
register value
Interrupt
BFFFH
■ 16-bit Free Run Timer Timing
● 16-bit free run timer clear timing (match with the compare register 0/4)
The counter can be cleared upon a reset, software clear, or a match with the compare register 0 (4). By a
reset or software clear, the counter is immediately cleared. By a match with compare register 0 (4), the
counter is cleared in synchronization with the count timing.
Figure 13.3-7 16-bit Free Run Timer Clear Timing (Match with the Compare Register 0/4)
φ
Compare
register value
N
Compare match
Counter value
180
N
0000
CHAPTER 13 16-BIT I/O TIMER
13.4
Output Compare
The output compare module consists of two 16-bit compare registers, two compare
output pins, and one control register. If the value written to the compare register of this
module matches the 16-bit free run timer value, the output level of the pin can be
reversed and an interrupt can be issued.
■ Output Compare
•
Two separate output compare modules are available on MB90945 series.
•
For each module, two compare registers exist which can be used independently. Depending on the
mode setting, the two compare registers can be used to control pin outputs.
•
The initial value for each pin output can be specified separately.
•
An interrupt can be issued upon a match as a result of comparison.
•
One pulse width modulated signal can be generated for each module.
•
Three pulse width modulated signals are possible when the two modules are combined.
■ Output Compare Block Diagram
Figure 13.4-1 shows the block diagram of output compare.
Figure 13.4-1 Output Compare Block Diagram
16-bit timer counter value (T15 to T00)
T
Compare control
Q
OTE0
OUT0
CMP0EXT
Compare register 0
CMOD1
16-bit timer counter value ( T15 to T00)
Bus
CMOD0
T
Compare control
Q
OTE1
OUT1
Compare register 1
ICP1
ICP0 ICE1 ICE0
Controller
Control blocks
Compare 1
interrupt
Compare 0
interrupt
Note: The figure above is also valid for output compare unit 2/3,
The CMP0EXT signal is explained in Figure 13.4-5
181
CHAPTER 13 16-BIT I/O TIMER
13.4.1
Output Compare Register
These 16-bit compare registers are compared with the 16-bit free run timer. Since the
initial register values are undefined, set appropriate value before enabling the
operation. These registers must be accessed by the word access instructions. When
the value of the register matches that of the 16-bit free run timer, a compare signal is
generated and the output compare interrupt flag is set. If output is enabled, the output
level corresponding to the compare register is reversed.
To rewriting the compare register, within the compare interrupt routine or compare
operation is disabled. Be sure not to occur simultaneously a compare match and
writing the compare register.
■ Output Compare Register
Figure 13.4-2 Configuration of the Output Compare Register (OCCP0 to OCCP3)
Address:
003530 H
003531 H
003532 H
003533 H
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
C15 C14 C13 C12 C11 C10 C09 C08 C07 C06 C05 C04 C03 C02 C01 C00
Initial value
XXXXXXXXXXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
003534 H
003535 H
003536 H
003537 H
003538 H
003539 H
00353A H
00353B H
00356A H
00356B H
00356C H
00356E H
R/W: Readable/writable
182
bit8
OCCPn
lower bits
C00
Compare Data Register 0
C01
Compare Data Register 1
C02
Compare Data Register 2
C03
Compare Data Register 3
C04
Compare Data Register 4
C05
Compare Data Register 5
C06
Compare Data Register 6
C07
Compare Data Register 7
n = 0, 1, 2, 3, 4, 5, 6, 7
OCCPn
upper bits
C08
Compare Data Register 8
C09
Compare Data Register 9
C10
Compare Data Register 10
C11
Compare Data Register 11
C12
Compare Data Register 12
C13
Compare Data Register 13
C14
Compare Data Register 14
C15
Compare Data Register 15
n = 0, 1, 2, 3, 4, 5, 6, 7
CHAPTER 13 16-BIT I/O TIMER
13.4.2
Control Status Register of Output Compare
The control status register sets the operation mode of output compare, starts and stops
output compare, controls interrupts, and sets the external output pins.
■ Control Status Register of Output Compare (Lower)
Figure 13.4-3 Configuration of the Control Status Register of Output Compare (OCS0/OCS2)
Address: bit7 bit6 bit5 bit4
000058 H ICPm ICPn ICEm ICEn
00005AH
00005CH R/W R/W R/W R/W
003568 H
bit3 bit2 bit1 bit0
-
-
CSTm CSTn
-
-
R/W R/W
Initial value
0000XX00B
CSTn
0
Compare operation enabled for unit n
CSTm
0
Compare operation disabled for unit m
1
Compare operation enabled for unit m
ICEn
Compare interrupt enable bit for unit n
Output compare interrupt disabled for unit n
1
Output compare interrupt enabled for unit n
: Readable/writable
: Initial value
Compare interrupt enable bit for unit m
0
Output compare interrupt disabled for unit m
1
Output compare interrupt enabled for unit m
1
: Undefined value
: Undefined
Comparison with timer bit for unit m
0
ICPn
0
X
-
Compare operation disabled for unit n
1
ICEm
R/W
Comparison with timer bit for unit n
ICPm
0
1
Compare match enable bit for unit n
No compare match for unit n
Compare match for unit n
Compare match enable bit for unit m
No compare match for unit m
Compare match for unit m
n = 0, 2 m = 1, 3
183
CHAPTER 13 16-BIT I/O TIMER
Table 13.4-1 Control Status Register of Output Compare (Lower)
Bit name
bit7
ICPm:
Compare match
enable bit for unit m
bit6
ICPn:
Compare match
enable bit for unit n
Function
These bits are used as output compare interrupt flags. "1" is set to these bits when the
compare register value matches the 16-bit free-run timer value. While the interrupt
request bits (ICEm and ICEn) are enabled, an output compare interrupt occurs when the
ICPm and ICPn bits are set. These bits are cleared by writing "0".
• "0": No compare match.
• "1": Compare match.
• Writing "1" has no effect.
• "1" is always read by a read-modify-write instruction.
Note:
ICPn: Corresponds to output compare n.
ICPm: Corresponds to output compare m.
bit5
ICEm:
Compare interrupt
enable bit for unit m
These bits are used as output compare interrupt enable flags. While the "1" is written to
these bits, an output compare interrupt occurs when an interrupt flag (ICPm or ICPn) is
set.
bit4
ICEn:
Compare interrupt
enable bit for unit n
• Writing "0": Output compare interrupt disabled.
• Writing "1": Output compare interrupt enabled.
Note:
ICEn: Corresponds to output compare unit n.
ICEm: Corresponds to output compare unit m.
bit3,
bit2
Undefined
bit1
CSTm:
Comparison with
timer bit for unit m
bit0
CSTn:
Comparison with
timer bit for unit n
n = 0, 2
184
m = 1, 3
These bits are used to enable the compare register before the compare operation is
enabled
• Writing "0": Compare operation disabled.
• Writing "1": Compare operation enabled.
Note:
Ensure that a value is written to the compare register before the compare operation is
enabled.
CSTn: Corresponds to output compare n.
CSTm: Corresponds to output compare m.
Since output compare is synchronized with the 16-bit free run timer clock, stopping
the 16-bit free run timer stops compare operation.
CHAPTER 13 16-BIT I/O TIMER
■ Control Status Register of Output Compare (Upper)
Figure 13.4-4 Configuration of the Control Status Register of Output Compare (OCS1/OCS3)
Address: bit15 bit14
000059 H CMOD1 00005BH
00005DH R/W 003569 H
bit13 bit12 bit11 bit10
bit9
bit8
-
CMOD0
-
R/W R/W R/W R/W R/W
OTEm OTEn OTDm OTDn
Initial value
0XX00000B
OTDn
0
1
OTDm
0
1
OTEn
: Readable / writable
X
-
: Undefined value
: Undefined
Sets "0" for compare pin output for unit n
Sets"1" for compare pin output for unit n
Output pin level select bit for unit m
Sets "0" for compare pin output for unit m
Sets"1" for compare pin output for unit m
Output pin select bit for unit n
0
General-purpose port for correspond. pin of unit n
1
Output compare pin output for unit n
OTEm
R/W
Output pin level select bit for unit n
Output pin select bit for unit m
0
General-purpose port for correspond. pin of unit m
1
Output compare pin output for unit m
CMOD1
0
CMOD0
0
Define comparison mode for pin
See description for details
: Initial value
n = 0, 2, 4, 6 m = 1, 3, 5, 7
Table 13.4-2 Control Status Register of Output Compare (Upper) (1 / 2)
Bit name
bit15 and
bit12
CMOD0, CMOD1:
Define comparison
mode for pin
bit14,
bit13
Undefined
bit11
OTEm:
Output pin select
bit for unit m
bit10
OTEn:
Output pin select
bit for unit n
Function
These bits define the operation mode for the pin output value. Depending on the defined
mode, the level is reversed upon a match with different compare registers. See Table
13.4-3 and Section "13.4.3 16-Bit Output Compare Operation" for details.
These bits are used to enable the output compare output pins. The initial value for these
bits is "0".
• "0": General-purpose port.
• "1": Output compare pin output.
Note:
OTEn: Corresponds to output compare n.
OTEm: Corresponds to output compare m.
When they are specified as outputs, the corresponding bits of the Port Direction
Registers should also be set to "1".
185
CHAPTER 13 16-BIT I/O TIMER
Table 13.4-2 Control Status Register of Output Compare (Upper) (2 / 2)
Bit name
Function
bit9
OTDm:
Output pin level
select bit for unit m
bit8
OTDn:
Output pin level
select bit for unit n
n = 0, 2
These bits are used to change the pin output level when the compare pin output is
enabled. The initial value of the compare pin output is "0". Ensure that the compare
operation is stopped before a value is written. When read, these bits indicate the output
compare pin output value.
• Writing "0": Sets "0" for compare pin output.
• Writing "1": Sets "1" for compare pin output.
Note:
OTDn: Corresponds to output compare n.
OTDm: Corresponds to output compare m.
m = 1, 3
Table 13.4-3 Function of CMOD1 and CMOD0 Bits
Pin output value reversed upon match with register no.
OCS1
Register OCCPx
CMOD1
CMOD0
OUT0
OUT1
x
0
0
1
x
1
0
0/1
CMOD1
CMOD0
OUT2
OUT3
0
0
2
3
0
1
2
2/3
1
0
0/2
0/3
1
1
0/2
0/2/3
OCS3
Register OCCPx
Figure 13.4-5 Block Diagram of Output Selection (OCU Module 1)
Compare
Control 2
OUT2
CMOD1
CMP0EXT
CMOD0
Compare
Control 3
OUT3
For OCU module 1, which requires a match with Output Compare Register 0 if CMOD1, CMOD0 = "10B",
the comparison result from module 0 is carried inside by the CMP0EXT signal. Of course, this does not
apply to module 0 itself. Here, no other register can be used but OCCP0 and OCCP1.
186
CHAPTER 13 16-BIT I/O TIMER
13.4.3
16-Bit Output Compare Operation
In the 16-bit output compare operation, an interrupt request flag can be set and the
output level can be reversed when the specified compare register value matches the
16-bit free-run timer value. The CMOD0 and CMOD1 bits can be used to define the
corresponding compare registers for each pin.
■ Sample Output Waveform when CMOD0 and CMOD1 = "00B"
When CMOD0 and CMOD1 = "00B", the output level of the pin corresponding to the compare register is
reversed on every match with the register value. Each output value is controlled by one compare register.
OUT0: The level is only reversed by a match with compare register 0.
OUT1: The level is only reversed by a match with compare register 1.
Figure 13.4-6 Sample of Output Waveform when CMOD0 and CMOD1 = "00B"
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
OCCP0 value
BFFFH
OCCP1 value
7FFFH
OUT0
OUT1
Compare 0
interrupt
Compare 1
interrupt
Note: In this figure, the initial value is "0" for both pins.
187
CHAPTER 13 16-BIT I/O TIMER
■ Sample Output Waveform with Two Compare Registers when CMOD0 and CMOD1 =
"01B"
When CMOD0 and CMOD1 = "01B", the output level of the pin corresponding to compare register 0 (2) is
reversed on every match with the register value. This is identical to the behavior for CMOD0 and CMOD1
= "00B". However, the output level of the second pin is reversed on a match with either compare register 0
or compare register 1 (3). This allows to define a pulsed signal with one edge defined by the value in
compare register 0 and the other edge defined by compare register 1 (3) or vice versa. If both compare
registers have the same value, the operation is identical to the case for CMOD0 and CMOD1 = "00B".
A pulse width modulated signal with differing frequency can be defined by using this mode together with
the reset option by compare register match for the free run timer (MODE-bit in TCCSL0/TCCSL1
registers).
OUT0 (2): The level is only reversed by a match with compare register 0 (2).
OUT1 (3): The level is reversed by a match with compare register 0 (2) or with compare register 1 (3).
Figure 13.4-7 Sample of a Output Waveform when CMOD0 and CMOD1 = "01B"
(No Timer Reset by Match)
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
OCCP0 value
BFFFH
OCCP1 value
7FFFH
OUT0
OUT1
Note: In this figure, the initial value is "0" for both pins.
188
CHAPTER 13 16-BIT I/O TIMER
Figure 13.4-8 Sample of a Output Waveform when CMOD0 and CMOD1 = "01B"
(with Timer Reset by Match)
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
OCCP0 value
BFFFH
OCCP1 value
7FFFH
OUT0
OUT1
Note: In this figure, the initial value is "0" for both pins.
189
CHAPTER 13 16-BIT I/O TIMER
■ Sample Output Waveform when CMOD0 and CMOD1 = "10B"
The operation mode defined by CMOD0 and CMOD1 = "10B" is intended for the use of three pulse width
modulated signals instead of two. If this mode is set to OCU module 1, a match of the timer value with
compare register 0 reverses both OUT2 and OUT3. For the third pulsed signal, the CMOD0 and CMOD1
bits of OCU module 0 should be set to "01B".
In register OCS1: CMOD0 and CMOD1 = "01B"
OUT0: The level is only reversed by a match with compare register 0.
OUT1: The level is reversed by a match with compare register 0 or with compare register 1.
In register OCS3: CMOD0 and CMOD1 = "10B"
OUT2: The level is reversed by a match with compare register 0 or with compare register 2.
OUT3: The level is reversed by a match with compare register 0 or with compare register 3.
Figure 13.4-9 Output Waveform when OCS1.CMOD0 and CMOD1 = "01B" and OCS3.
CMOD0 and CMOD1 = "10B"
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
OCCP0 value
BFFFH
OCCP1 value
7FFFH
OCCP2 value
3FFFH
OCCP3 value
5FFFH
OUT0
OUT1
OUT2
OUT3
Note: In this figure, the initial value is "0" for all pins.
Timer reset is by match with compare register 0.
190
CHAPTER 13 16-BIT I/O TIMER
■ Sample Output Waveform when CMOD0 and CMOD1 = "11B"
When CMOD0 and CMOD1 = "11B", the output level of the OUT3 pin is reversed by the compare
registers 0, 2 or 3. For the pin OUT1, this setting is identical to CMOD0 and CMOD1 = "01B" (see also
Table 13.4-3).
OUT0: The level is only reversed by a match with compare register 0.
OUT1: The level is reversed by a match with compare register 0 or with compare register 1.
OUT2: The level is reversed by a match with compare register 0 or with compare register 2.
OUT3: The level is reversed by a match with compare register 0, compare register 2 or with compare
register 3.
Figure 13.4-10 Output Waveform when OCS1.CMOD0 and CMOD1 = "11B" and OCS3.
CMOD0 and CMOD1 = "11B"
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
OCCP0 value
BFFFH
OCCP1 value
7FFFH
OCCP2 value
3FFFH
OCCP3 value
5FFFH
OUT0
OUT1
OUT2
OUT3
Note: In this figure, the initial value is "0" for all pins.
Timer reset is by match with compare register 0.
191
CHAPTER 13 16-BIT I/O TIMER
■ Output Compare Timing
In output compare operation, a compare match signal is generated when the free run timer value matches
the specified compare register value. The output value can be reversed and an interrupt can be issued. The
output reverse timing upon a compare match is synchronized with the counter timing.
● Compare operation upon update of compare register
When the compare register is updated, comparison with the counter value is not performed.
● Interrupt timing
Figure 13.4-11 Interrupt Timing
φ
N
Counter value
N+1
N
Compare register
value
Compare match
Interrupt
● Output pin change timing
Figure 13.4-12 Output Pin Change Timing
Counter value
Compare register
value
Compare match
signal
Pin output
192
N
N+1
N
N
N+1
CHAPTER 13 16-BIT I/O TIMER
13.5
Input Capture
Input capture detects a rising or falling edge or both edges of an external input signal
and stores a 16-bit free run timer value at that time in a register. In addition, input
capture can generate an interrupt upon detection of an edge. Input capture consists of
an input capture data register and a control register.
■ Input Capture
Each input capture has a corresponding external input pin.
● The valid edge of an external input can be selected from the following three types:
Table 13.5-1 Types of External Input Edges
Rising edge
Falling edge
Both edges
● An interrupt can be generated upon detection of a valid edge of an external input.
■ Input Capture Block Diagram
Figure 13.5-1 shows a block diagram of input capture.
Figure 13.5-1 Input Capture Block Diagram
IN0
Edge detection
Capture data register 0
Count value from free run timer
EG11 EG10 EG01 EG00
IEI1
IEI0
Bus
Capture data register 1
Edge detection
ICP1
ICP0
ICE1
IN1
ICE0
Interrupt
Interrupt
Note: The figure above is also valid for Input Capture Unit 2/3 and 4/5
193
CHAPTER 13 16-BIT I/O TIMER
13.5.1
Input Capture Register Details
Input capture has the three registers listed. These registers store a value from the 16-bit
free running timer when a valid edge of the corresponding external pin input waveform
is detected. (The registers must be accessed in word mode. No values can be written to
the registers.)
• Input capture data register
• Input capture control register
• Input capture edge register
■ Input Capture Data Register
Figure 13.5-2 Configuration of the Input Capture Data Register (IPCP0 to IPCP5)
Address:
003520 H
.
.
.
00352BH
bit15 bit14 bit13 bit12 bit11 bit10 bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
XXXXXXXXXXXXXXXXB
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
IPCPn
lower bits
CP00
Input Capture Data Register 0
CP01
Input Capture Data Register 1
CP02
Input Capture Data Register 2
CP03
Input Capture Data Register 3
CP04
Input Capture Data Register 4
CP05
Input Capture Data Register 5
CP06
Input Capture Data Register 6
CP07
Input Capture Data Register 7
n = 0,1,2,3,4,5
R: Read only
194
IPCPn
upper bits
CP08
Input Capture Data Register 8
CP09
Input Capture Data Register 9
CP10
Input Capture Data Register 10
CP11
Input Capture Data Register 11
CP12
Input Capture Data Register 12
CP13
Input Capture Data Register 13
CP14
Input Capture Data Register 14
CP15
Input Capture Data Register 15
n = 0,1,2,3,4,5
CHAPTER 13 16-BIT I/O TIMER
■ Control Status Register
Figure 13.5-3 Configuration of the Control Status Register (ICS01, ICS23, ICS45)
Address: bit15/7 bit14/6 bit13/5 bit12/4 bit11/3 bit10/2 bit9/1 bit8/0
ICS01:
000054H ICPm ICPn ICEm ICEn EGm1 EGm0 EGn1 EGn0
ICS23:
000055H R/W R/W R/W R/W R/W R/W R/W R/W
ICS45:
000056H
Initial value
00000000 B
EGn1
EGn0
0
0
No edge detection (stop)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
EGm1
EGm0
0
0
No edge detection (stop)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
ICEn
1
Enable Interrupt
Interrupt enable bit (input capture m)
0
Disable Interrupt
1
Enable Interrupt
Interrupt request flag bit (input capture n)
Read
Write
0
No valid detected
Clear this bit
1
Valid detected
No effect
ICPm
: Initial value
Interrupt enable bit (input capture n)
Disable Interrupt
ICPn
: Readable / writable
Edge selection bit (input capture m)
0
ICEm
R/W
Edge selection bit (input capture n)
Interrupt request flag bit (input capture m)
Read
Write
0
No valid detected
Clear this bit
1
Valid detected
No effect
n = 0, 2, 4 m = 1, 3, 5
195
CHAPTER 13 16-BIT I/O TIMER
Table 13.5-2 Input Capture Control Status Register Bits (Upper and Lower)
Bit name
Function
bit15/bit7
ICPn+1/3:
Interrupt request flag
bit (Input capture
n+1/3)
This bit is used as interrupt request flag for input capture n and m.
• "1" is set to this bit upon detection of a valid edge of an external input pin.
• While the interrupt enable bit (ICEn+1/3) is set, an interrupt can be generated
upon detection of a valid edge.
• Writing "0" will clear this bit.
• Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
bit14/bit6
ICPn/2:
Interrupt request flag
bit (Input capture
n/2)
This bit is used as interrupt request flag for input capture n and m.
• "1" is set to this bit upon detection of a valid edge of an external input pin.
• While the interrupt enable bit (ICEn/2) is set, an interrupt can be generated upon
detection of a valid edge.
• Writing "0" will clear this bit.
• Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
bit13/bit5
ICEn+1/3:
Interrupt request
enable bit (Input
capture n+1/3)
This bit is used to enable input capture interrupt request for input capture n+1/3.
• While "1" is written to this bit, an input capture interrupt is generated when the
interrupt flag (ICPn+1/3) is set.
bit12/4
ICEn/2:
Interrupt request
enable bit (Input
capture n/2)
This bit is used to enable input capture interrupt request for input capture n/2.
• While "1" is written to this bit, an input capture interrupt is generated when the
interrupt flag (ICPn/2) is set.
bit11, bit10/
bit3, bit2
EG[n+1]1, EG[n+1]0/
EG31, EG30
These bits are used to specify the valid edge polarity of an external input for input
capture n+1/3.
• These bits are also used to enable input capture operation.
bit9, bit8/
bit1, bit0
EGn1, EGn0 / EG21,
EG20
These bits are used to specify the valid edge polarity of an external input for input
capture n/2.
• These bits are also used to enable input capture operation.
n = 0, 4
196
CHAPTER 13 16-BIT I/O TIMER
■ Input Capture Edge Register
Figure 13.5-4 Configuration of the Input Capture Edge Register (ICE01, ICE23, ICE45)
Address:
bit15/7 bit14/6 bit13/5 bit12/4 bit11/3 bit10/2 bit9/1
bit8/0
IUCE IEIm
IEIn
R/W R
R
0035C9H
0035CAH
0035CBH
-
-
-
-
-
Initial value
X X X X X 0*X XB
* ICE01 and ICE45 ("X" otherwise)
IEIn
Valid edge indication bit (input capture n)
0
Falling edge detected
1
Rising edge detected
IEIm
Valid edge indication bit (input capture m)
0
Falling edge detected
1
Rising edge detected
R/W
: Readable/writable
R
: Read only
IUCE
-
: Undefined
0
External Input Capture connection
: Initial value
1
UART2/3 to Input Capture connection
(Only Input capture 1 and 5)
n = 0, 2, 4
Input Capture to UART2/3 connection enable bit
m = 1, 3, 5
197
CHAPTER 13 16-BIT I/O TIMER
Table 13.5-3 Input Capture Edge Register Bits (Upper and Lower)
Bit name
Function
bit15 to bit11/
bit7 to bit3
Undefined
bit10
IUCE1/5:
Input Capture to UART3
connection enable bit
This bit selects the capture source for input capture unit 1 and 5, and
is used by UART3-LIN-Operation.
Undefined bit for MB90947A,
MB90F947(A), and
MB90F949(A) else
This bit selects the capture source for input capture unit 3 and is used
by UART2-LIN-Operation.
bit2
IUCE3:
Input Capture to UART2
connection enable bit
bit9/bit1
IEIm:
Valid edge indication bits
-
• Writing "0": The capture source is external.
• Writing "1": The capture source is UART3.
• Writing "0": The capture source is external.
• Writing "1": The capture source is UART2.
This bit is a valid edge indication bit for capture register IPCP1,
IPCP3 and IPCP5, to indicate that a rising or falling edge is detected.
• "0": falling edge detected.
• "1": rising edge detected.
• This bit is read only.
Note:
The read value is meaningless, if EGm1, EGm0 = "00B".
bit8/bit0
IEIn:
Valid edge indication bits
This bit is a valid edge indication bit for capture register IPCP0,
IPCP2 and IPCP4, to indicate that a rising of falling edge is detected.
• "0": falling edge detected.
• "1": rising edge detected.
• This bit is read only.
Note:
The read value is meaningless, if EGn1, EGn0 = "00B".
n = 0, 2, 4
198
m = 1, 3, 5
CHAPTER 13 16-BIT I/O TIMER
13.5.2
16-Bit Input Capture Operation
In 16-bit input capture operation, an interrupt can be generated upon detection of at the
specified edge, fetching the 16-bit free-run timer value and writing it to the capture
register.
■ Sample of Input Capture Fetch Timing
• Capture 0: Rising edge
• Capture 1: Falling edge
• Capture example: Both edges
Figure 13.5-5 Sample of Input Capture Fetch Timing
Counter value
FFFF H
BFFF H
7FFF H
3FFF H
0000 H
Time
Reset
IN0
IN1
IN example
Capture 0
Capture 1
Capture
example
Undefined
3FFFH
Undefined
Undefined
7FFFH
BFFFH
3FFFH
Capture 0
interrupt
Capture 1
interrupt
Capture
interrupt
199
CHAPTER 13 16-BIT I/O TIMER
■ Input Capture Input Timing
● Capture timing for input signals
Figure 13.5-6 Capture Timing for Input Signals
φ
Counter value
Input capture
input
N
N+1
Valid edge
Capture signal
Capture register
Interrupt
200
N+1
CHAPTER 14
16-BIT RELOAD TIMER
(WITH EVENT COUNT
FUNCTION)
This chapter explains the functions and operations of
the 16-bit reload timer (with the event count function).
14.1 Outline of 16-Bit Reload Timer (with Event Count Function)
14.2 16-Bit Reload Timer (with Event Count Function)
14.3 Internal Clock and External Clock Operations of 16-Bit Reload
Timer
14.4 Underflow Operation of 16-Bit Reload Timer
14.5 Output Pin Functions of 16-Bit Reload Timer
14.6 Counter Operation State
201
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
14.1
Outline of 16-Bit Reload Timer (with Event Count Function)
The 16-bit reload timer consists of a 16-bit down-counter, a 16-bit reload register, one
input pin (TIN0) and one output pin (TOT0), and a control register. The input clock can
be selected from one external clock and three types of internal clock.
■ Outline of 16-bit Reload Timer (with Event Count Function)
The output pin (TOT0) outputs a toggle output waveform in reload mode and outputs a square waveform
indicating counting in one-shot mode. The input pin (TIN0) is used for event input in event count mode,
and can be used for trigger input or gate input in internal clock mode.
■ Intelligent I/O Service (EI2OS) Function and Interrupts
The timer includes a circuit that supports EI2OS. The timer can activate EI2OS when an underflow occurs.
■ Block Diagram of 16-bit Reload Timer
Figure 14.1-1 shows the block diagram of the 16-bit reload timer.
Figure 14.1-1 Block Diagram of 16-bit Reload Timer
16
F2 M C - 16 L X B U S
16-bit reload register
8
Reload
RELD
UF
16-bit down-counter
OUTE
16
OUTL
2
OUT
CTL.
GATE
INTE
UF
CSL1
Clock selector
CNTE
CSL0
IRQ
Clear
I 2OSCLR
TRG
Re-trigger
2
EXCK
Port (TIN)
IN CTL
3
2
1
2
3
5
2
Prescaler
clear
Output enable
Port (TOT)
MOD2
MOD1
Peripheral clock
3
202
MOD0
UART baud rate (ch0)
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
14.2
16-Bit Reload Timer (with Event Count Function)
The 16-bit reload timer has the following two types of registers:
• Timer control register (TMCSR0)
• 16-bit timer register (TMR0)/16-bit reload register (TMRLR0)
■ 16-bit Reload Timer Register
Figure 14.2-1 16-bit Reload Timer Registers
Address:
TMCSR0 (upper):
Address:
TMCSR0 (lower):
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
000051H
-
-
-
-
CSL1 CSL0 MOD2 MOD1
-
-
-
-
R/W R/W R/W R/W
Initial value
XXXX0000B
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
000050H
MOD0 OUTE OUTL RELD I NTE
UF
CNTE TRG
Initial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
TMR/TMRLR0 (upper): 003541H
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
TMR/TMRLR0 (lower): 003540H
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable / writable
X : Undefined value
: Undefined
203
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
14.2.1
Timer Control Status Register (TMCSR0)
Controls the operation mode and interrupts for the 16-bit timer. Only modify bits other
than UF, CNTE, and TRG when CNTE = "0".
■ Timer Control Status Register (TMCSR0)
Figure 14.2-2 Configuration of the Timer Control Status Register (TMCSR0)
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
Address:
TMCSR0 (upper): 000051H
Address:
TMCSR0 (lower): 000050H
-
-
-
-
CSL1 CSL0 MOD2 MOD1
-
-
-
-
R/W R/W R/W R/W
Initial value
XXXX0000B
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
MOD0 OUTE OUTL RELD I NTE
UF
CNTE TRG
Initial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable / writable
X : Undefined value
: Undefined
■ Register Contents of Timer Control Register (TMCSR0)
[bit11, bit10] CSL1, CSL0 (Clock select 1, 0)
The count clock select bits. Table 14.2-1 lists the selected clock sources.
Table 14.2-1 Clock Sources for CSL Bit Settings
204
CSL1
CSL0
Clock source (machine cycle φ = 16 MHz)
0
0
φ/21 (0.125 μs)
0
1
φ/23 (0.5 μs)
1
0
φ/25 (2.0 μs)
1
1
External event count mode
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
[bit9 to bit7] MOD2 to MOD0
These bits set the operation mode and I/O pin functions.
The MOD2 bit selects the I/O functions. When MOD2 = "0", the input pin functions as a trigger input.
In this case, the reload register contents is loaded to the counter when an active edge is input to the
input pin and count operation proceeds. When MOD2 = "1", the timer operates in gate counter mode
and the input pin functions as a gate input. In this mode, the counter only counts while an active level is
input to the input pin.
The MOD1, MOD0 bits set the pin functions for each mode. Table 14.2-2 and Table 14.2-3 list the
MOD2 to MOD0 bit settings.
Table 14.2-2 MOD2 to MOD0 Bit Settings (1)
MOD2
MOD1
MOD0
Input pin function
Active edge or level
0
0
0
Trigger disabled
-
0
0
1
Trigger input
Rising edge
0
1
0
Falling edge
0
1
1
Both edges
1
x
0
1
x
1
Gate input
"L" level
"H" level
Internal clock mode (CSL0, CSL1 = "00B", "01B", or "10B")
Table 14.2-3 MOD2 to MOD0 Bit Settings (2)
MOD2
x
MOD1
MOD0
Input pin function
Active edge or level
0
0
-
-
0
1
Trigger input
Rising edge
1
0
Falling edge
1
1
Both edges
•
Event counter mode (CSL0,CSL1 = "11B")
•
Bits marked as x in the table can be set to any value.
205
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
[bit6] OUTE
Output enable bit. The TOT0 pin functions as a general-purpose port when this bit is "0" and as the
timer output pin when this bit is "1". In reload mode, the output waveform toggles. In one-shot mode,
TOT0 outputs a square waveform that indicates that counting is in progress.
[bit5] OUTL
This bit sets the output level for the TOT0 pin.
Table 14.2-4 OUTE, RELD, and OUTL Settings
OUTE
RELD
OUTL
Output waveform
0
x
x
General-purpose port
1
0
0
Output an "H" level square waveform during counting.
1
0
1
Output an "L" level square waveform during counting.
1
1
0
Toggle output. Starts with "L" level output.
1
1
1
Toggle output. Starts with "H" level output.
[bit4] RELD (Reload)
This bit enables reload operations. When RELD is "1", the timer operates in reload mode. In this mode,
the timer loads the reload register contents into the counter and continues counting whenever an
underflow occurs (when the counter value changes from 0000H to FFFFH). When RELD is "0", the
timer operates in one-shot mode. In this mode, the count operation stops when an underflow occurs due
to the counter value changing from 0000H to FFFFH.
[bit3] INTE (Interrupt enable)
Timer interrupt request enable bit. When INTE is "1", an interrupt request is generated when the UF bit
changes to "1". When INTE is "0", no interrupt request is generated, even when the UF bit changes to
"1".
[bit2] UF (Underflow)
Timer interrupt request flag. UF is set to "1" when an underflow occurs (when the counter value
changes from 0000H to FFFFH). Cleared by writing "0" or by the intelligent I/O service. Writing "1" to
this bit has no meaning. Read as "1" by read-modify-write instructions.
[bit1] CNTE (Count enable)
Timer count enable bit. Writing "1" to CNTE sets the timer to wait for a trigger. Writing "0" stops count
operation.
[bit0] TRG (Trigger)
Software trigger bit. Writing "1" to TRG applies a software trigger, causing the timer to load the reload
register contents to the counter and start counting. Writing "0" has no meaning. Reading always returns
"0". Applying a trigger using this register is only valid when CNTE = "1". Writing "1" has no effect if
CNTE = "0".
206
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
14.2.2
Register Layout of 16-Bit Timer Register (TMR0)/
16-Bit Reload Register (TMRLR0)
• TMR0 contents (for reading)
Reading this register reads the count value of the 16-bit timer. The initial value is
undefined. Always use the word access instructions to read this register.
• TMRLR0 contents (for writing)
The 16-bit reload register holds the initial count value. The initial value is undefined.
Always use the word access instructions to write to this register.
■ 16-bit Timer Register (TMR0)/16-bit Reload Register (TMRLR0)
Figure 14.2-3 Configuration of the 16-bit Timer Register (TMR0)/16-bit Reload Register (TMRLR0)
Address:
TMR0/TMRLR0 (upper): 003541H
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
TMR0/TMRLR0 (lower): 003540H
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable / writable
X : Undefined value
207
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
14.3
Internal Clock and External Clock Operations of 16-Bit
Reload Timer
The machine clock divided by 21, 23, or 25 can be selected as the clock sources for
operating the timer from an internal divide clock. The external input pin can be selected
as either a trigger input or gate input by a register setting.
If an external clock is selected, the TIN pin functions as an external event input pin to
count the number of valid edges set in the register.
■ Internal Clock Operation of 16-bit Reload Timer
Writing "1" to both the CNTE and TRG bits in the control register enables and starts counting at one time.
Using the TRG bit as a trigger input is always available when the timer is enabled (CNTE = "1"), regardless
of the operation mode.
Figure 14.3-1 shows counter activation and counter operation. A time period T (T: machine cycle) is
required from the counter start trigger being input until the reload register data is loaded into counter.
Figure 14.3-1 Activation and Operation of 16-bit Reload Timer Counter
Count clock
Counter
Reload data
Data load
CNTE (bit)
TRG (bit)
T
208
-1
-1
-1
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
■ Input Pin Functions of 16-bit Reload Timer (in Internal Clock Mode)
The TIN0 pin can be used as either a trigger input or a gate input when an internal clock is selected as the
clock source. When used as a trigger input, input of an active edge causes the timer to load the reload
register contents to the counter and then start count operation after clearing the internal prescaler. Input a
pulse width of at least 2T (T is the machine cycle) to TIN0.
Figure 14.3-2 shows the operation of trigger input.
Figure 14.3-2 Trigger Input Operation of 16-bit Reload Timer
Count clock
Rising edge detected
TIN
Prescaler clear
Counter
Reload data
0000H
-1
-1
-1
Load
2T2.5T
When used as a gate input, the counter only counts while the active level specified by the MOD0 bit of the
control register is input to the TIN0 pin. In this case, the count clock continues to operate unless stopped.
The software trigger can be used in gate mode, regardless of the gate level. Input a pulse width of at least
2T (T is the machine cycle) to the TIN0 pin. Figure 14.3-3 shows the operation of gate input.
Figure 14.3-3 Gate Input Operation of 16-bit Reload Timer
Count clock
TIN
Counter
When MOD0 = "1" (Count when "H" is input)
-1
-1
-1
■ External Event Counter
The TIN0 pin functions as an external event input pin when an external clock is selected. The counter
counts on the active edge specified in the register. Input a pulse width of at least 4T (T is the machine
cycle) to the TIN0 pin.
209
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
14.4
Underflow Operation of 16-Bit Reload Timer
An underflow is defined for this timer as the time when the counter value changes from
0000H to FFFFH. Therefore, an underflow occurs after (reload register setting + 1)
counts.
■ Underflow Operation of 16-bit Reload Timer
If the RELD bit in the control register is "1" when the underflow occurs, the contents of the reload register
is loaded into the counter and counting continues. When RELD is "0", counting stops with the counter at
FFFFH.
The UF bit in the control register is set when the underflow occurs. If the INTE bit is "1" at this time, an
interrupt request is generated.
Figure 14.4-1 shows the operation when an underflow occurs.
Figure 14.4-1 Underflow Operation of 16-bit Reload Timer
Count clock
Counter
0000H
Reload data
Data load
Underflow set
[RELD=1]
Count clock
Counter
0000H
Underflow set
[RELD=0]
210
FFFFH
-1
-1
-1
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
14.5
Output Pin Functions of 16-Bit Reload Timer
In reload mode, the TOT0 pin performs toggle output (inverts at each underflow). In oneshot mode, the TOT0 pin functions as a pulse output that shows a particular level while
the count is in progress.
■ Output Pin Functions of 16-bit Reload Timer
The OUTL bit of the control register sets the output polarity. When OUTL = "0", the initial value for toggle
output is "0" and the one-shot pulse output is "1" while the count is in progress. The output waveforms are
opposite when OUTL = "1".
Figure 14.5-1 and Figure 14.5-2 show the output pin functions.
Figure 14.5-1 Output Pin Function of 16-bit Reload Timer (1)
Count start
Underflow
Level is opposite when
OUTL = "1"
TOT
General-purpose port
OUTE
CNTE
Trigger
[RELD=1, OUTL=0]
Figure 14.5-2 Output Pin Function of 16-bit Reload Timer (2)
Underflow
TOT
Level is opposite
when OUTL = "1"
General-purpose port
OUTE
CNTE
Trigger
Waiting for a trigger
[RELD=0, OUTL=0]
211
CHAPTER 14 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
14.6
Counter Operation State
The counter state is determined by the CNTE bit in the control register and the internal
WAIT signal. Available states are: CNTE = "0" and WAIT = "1" (STOP state), CNTE = "1"
and WAIT = "1" (WAIT state for trigger), and CNTE = "1" and WAIT = "0" (RUN state).
■ Counter Operation State
Figure 14.6-1 shows the transitions between each state.
Figure 14.6-1 Counter State Transitions
Reset
State transitions by hardware
STOP
CNTE=0, WAIT=1
State transitions by external input
State transitions by register access
TIN pin: Input disabled
TOT pin: OUTE=0: General-purpose port
OUTE=1: Initial value output
Counter: Retains the value while
counting stopped.
Value undefined after reset.
CNTE=0
CNTE=0
CNTE=1
TRG=1
CNTE=1
TRG=0
WAIT
CNTE=1, WAIT=1
RUN
TIN pin: Only trigger input enabled *
TOT pin: OUTE=0: General-purpose port
OUTE=1: Initial value output
TIN pin: Functions as TIN pin
*
TOT pin: OUTE=0: General-purpose port
RELD . UF
OUTE=1: Initial value output
Counter: Running
Counter: Retains the value while
counting stopped.
Value undefined after reset until
load.
TRG=1
LOAD
External trigger from TIN
CNTE=1, WAIT=0
TRG=1
CNTE=1, WAIT=0
Load contents of the reload
register to the counter.
RELD . UF
External trigger from TIN
*: Before using TIN pin, the corresponding bit of the DDR must be to "0".
212
Load complete
CHAPTER 15
8/16-BIT PPG
This chapter explains the 8/16-bit PPG and its functions.
15.1 Outline of 8/16-Bit PPG
15.2 Block Diagram of 8/16-Bit PPG
15.3 8/16-Bit PPG Registers
15.4 Operations of 8/16-Bit PPG
15.5 Selecting a Count Clock for 8/16-Bit PPG
15.6 Controlling Pin Output of 8/16-Bit PPG Pulses
15.7 8/16-Bit PPG Interrupts
15.8 Initial Values of 8/16-Bit PPG Hardware
213
CHAPTER 15 8/16-BIT PPG
15.1
Outline of 8/16-Bit PPG
The 8/16-bit programmable pulse generator (PPG) consists of two 8-bit down counters,
four 8-bit reload registers, one 16-bit control register, 2 external pulse output signals,
and 2 interrupt outputs. The following functions are implemented:
■ Function of 8/16-bit PPG
● 8-bit PPG output, 2-channel independent operation mode:
Two independent channels of PPG output operation are implemented.
● 16-bit PPG output operation mode:
One channel of 16-bit PPG output operation is implemented.
● 8+8-bit PPG output operation mode:
8-bit PPG output operation is implemented at specified intervals, using channel 0 output as channel 1 clock
input.
● PPG output operation:
Pulse waves are output at specified intervals and duty ratio. With an external circuit, this module can be
used as a D/A converter.
The MB90945 series contains six PPG’s. The following sections only describe the functionality of the
PPG0/PPG1. The remaining PPG’s have the identical function and the register addresses should be found
in the I/O map.
Figure 15.1-1 shows the connection of internal PPG modules and external pins.
Figure 15.1-1 Relationship between PPG Modules and External Pins
PPG0 / PPG1
PPG2 / PPG3
Internal
Modules
PPG4 / PPG5
PPG6 / PPG7
PPG8 / PPG9
PPGA / PPGB
214
PPG00
PPG10
PPG01
PPG11
PPG02
PPG12
PPG03
PPG13
PPG04
PPG14
PPG05
PPG15
External
Pins
CHAPTER 15 8/16-BIT PPG
15.2
Block Diagram of 8/16-Bit PPG
Figure 15.2-1 shows the block diagram of the 8/16-bit PPG (ch0). Figure 15.2-2 shows
the block diagram of the 8/16-bit PPG (ch1).
■ Block Diagram of 8/16-bit PPG
Figure 15.2-1 8-bit PPG ch0 Block Diagram
PPG00 output enable
PPG00
Peripheral clock 16-division
Peripheral clock 8-division
Peripheral clock 4-division
Peripheral clock 2-division
Peripheral clock
PPG00
Output latch
Invert
Clear
PEN0
In MB90945 series, this IRQ signal merged
with the channel1 IRQ signal by or loqic.
Count clock
selection
Timebase counter output,
512-division of main clock
"L"/"H" selection
PCNT
(down counter)
lRQ
Reload
ch1 -borrow
"L"/"H" selector
PRLL0
PRLBH0
Temporary buffer
PIE0
PRLH0
PUF0
"L" data bus
"H" data bus
PPGC0
(Operation mode control)
215
CHAPTER 15 8/16-BIT PPG
Figure 15.2-2 8-bit PPG ch1 Block Diagram
PPG10 output enable
PPG10
Peripheral clock 16-division
Peripheral clock 8-division
Peripheral clock 4-division
Peripheral clock 2-division
Peripheral clock
PPG10
Output latch
Invert
Count clock
selection
Clear
PEN1
In MB90945 series, this IRQ signal merged
with the channel1 IRQ signal by or loqic.
PCNT
(down counter)
ch0-borrow
lRQ
Reload
Timebase counter output,
512-division of main clock
"L"/"H" selection
"L"/"H" selector
PRLL1
PRLBH1
Temporary buffer
PIE1
PRLH1
PUF1
"L" data bus
"H" data bus
PPGC1
(Operation mode control)
216
CHAPTER 15 8/16-BIT PPG
● Details of pins in block diagram
Table 15.2-1 lists the actual pin names and interrupt request numbers of the 8-/16-bit PPG timer.
Table 15.2-1 Pins and Interrupt Request Numbers in Block Diagram
Channel
Output Pin
PPG0
P56/PPG00
PPG1
P50/PPG10
PPG2
P57/PPG01
PPG3
P51/PPG11
PPG4
PB0/PPG02
PPG5
P52/PPG12
PPG6
PB1/PPG03
PPG7
P53/PPG13
PPG8
PB2/PPG04
PPG9
P54/PPG14
PPGA
PB3/PPG05
PPGB
P55/PPG15
Interrupt Request Number
#17 (11H)
#18 (12H)
#19 (13H)
#20 (14H)
#21 (15H)
#22 (16H)
● PPG operation mode control register 0 (PPGC0)
This register enables or disables operation of the 8-/16-bit PPG timer 0, the pin output, and an underflow
interrupt. It also indicates the occurrence of an underflow.
● PPG0/1 count clock select register (PPG01)
This register sets the count clock of the 8-/16-bit PPG timer 0.
● PPG0 reload registers (PRLH0 and PRLL0)
These registers set the High width or Low width of the output pulse. The values set in these registers are
reloaded to the PPG0 down counter (PCNT0) when the 8-/16-bit PPG timer 0 is started.
● PPG0 down counter (PCNT0)
This counter is an 8-bit down counter that alternately reloads the values set in the PPG0 reload registers
(PRLH0 and PRLL0) to decrement. When an underflow occurs, the pin output is inverted. This counter is
concatenated for use as a single-channel 16-bit PPG down counter.
● PPG0 temporary buffer (PRLBH0)
This buffer prevents deviation of the output pulse width caused at writing to the PPG reload registers
(PRLH0 and PRLL0). This buffer stores the PRLH0 value temporarily and enables it in synchronization
with the timing of writing to the PRLL0.
217
CHAPTER 15 8/16-BIT PPG
● Reload register L/H selector
This selector detects the current pin output level to select which register value, Low reload register
(PRLL0) or High reload register (PRLH0), should be reloaded to the PPG0 down counter.
● Count clock selector
This selector selects the count clock to be input to the PPG0 down counter from five frequency-divided
clocks of the machine clock or the frequency-divided clocks of the timebase timer.
● PPG output control circuit
This circuit inverts the pin output level and the output when an underflow occurs.
218
CHAPTER 15 8/16-BIT PPG
15.3
8/16-Bit PPG Registers
The 8/16-bit PPG has the following five types of registers:
• PPG0 (2, 4, 6, 8, A) Operation Mode Control Register (PPGCn)
• PPG1 (3, 5, 7, 9, B) Operation Mode Control Register (PPGCm)
• PPG0/1 Clock Select Register (PPGnm)
• Reload register H (RRLHn)
• Reload register L (RRLHm)
■ 8/16-bit PPG Registers
Figure 15.3-1 8/16-bit PPG Registers
PPGCn
Address: ch0 000038H
ch2 00003CH
ch4 000040H
ch6 000044H
ch8 000048H
chA 00004CH
PPGCm
Address: ch1 000039H
ch3 00003DH
ch5 000041H
ch7 000045H
ch9 000049H
chB 00004DH
PPGnm
Address: ch01 00003AH
ch23 00003EH
ch45 000042H
ch67 000046H
ch89 00004AH
chAB 00004EH
PRLHn/PRLHm
Address: ch0 003501H
ch1 003503H
ch2 003505H
ch3 003507H
ch4 003509H
ch5 00350BH
ch6 00350DH
ch7 00350F H
ch8 003511 H
ch9 003513 H
chA 003515H
chB 003517H
PRLLn/PRLLm
Address: ch0 003500H
ch1 003502H
ch2 003504H
ch3 003506H
ch4 003508H
ch5 00350AH
ch6 00350CH
ch7 00350EH
ch8 003510 H
ch9 003512 H
chA 003514H
chB 003516H
bit7
bit6
PEN0
R/W
bit15
-
bit14
PEN1
R/W
bit7
bit5
bit4
bit3
PE00
PIE0
PUF0
R/W
bit13
PE10
-
bit6
R/W
bit5
R/W
bit12
PIE1
R/W
bit4
R/W
bit2
bit1
bit0
Initial value:
Reserved
-
-
bit11
bit10
bit9
PUF1
MD1
MD0 Reserved
R/W
bit3
R/W
bit2
0 - 000--1B
W
R/W
bit8
Initial value:
0-000001B
W
bit1
bit0
Initial value:
000000--B
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
R/W
R/W
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
-
-
bit9
bit8
Initial value:
XXXXXXXXB
R/W
bit7
R/W
bit6
R/W
bit5
R/W
bit4
R/W
bit3
R/W
bit2
R/W
bit1
R/W
bit0
Initial value:
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
n = 0, 2, 4, 6, 8, A
m = 1, 3, 5, 7, 9, B
219
CHAPTER 15 8/16-BIT PPG
15.3.1
PPG0 Operation Mode Control Register (PPGC0)
PPGC0 is a 8-bit control register that selects the operation mode of the block, controls
pin outputs, selects count clock, and controls triggers.
■ PPG0 Operation Mode Control Register (PPGC0)
Figure 15.3-2 Configuration of the PPG0 Operation Mode Control Register (PPGC0)
Address:
ch0, 000038H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PEN0
-
PE00
PIE0
PUF0
-
-
Reserved
R/W
-
R/W
R/W
R/W
-
-
Other channels:
ch2 00003CH
ch4 000040H
ch6 000044H
ch8 000048H
chA 00004CH
Initial value:
0X000XX1B
W
Reserved
1
PUF0
PPG counter underflow is not detected
1
PPG counter underflow is detected
Interrupt disabled
1
Interrupt enabled
: Write only
-
: Undefined value
X
: Undefined
: Initial value
220
PPG output enable 00 bit
0
Pulse output disabled (general-purpose port)
1
Pulse output enabled
PEN0
W
PPG interrupt enable bit
0
PE00
: Readable / writable
PPG underflow flag bit
0
PIE0
R/W
When setting PPGC0
Always set this bit to "1"
PPG enable bit
0
Stop ( "L" level output maintained)
1
PPG operation enabled
CHAPTER 15 8/16-BIT PPG
Table 15.3-1 Bit Function Description of the PPG0 Operation Mode Control Register
Bit name
Function
bit7
PEN0:
Operation enable bit
When set to "1", this bit enables the counter operation of the PPG. When operation is
disabled but output is enabled (bit5), a low level is maintained at the output.
bit5
PE00:
PPG00 pin output
enable bit
When set to "1", this bit enables the pulse output. For MB90945 series, the pulse signal is
output to the "PPG00" external pin. When disabled, the pin can be used as generalpurpose port.
bit4
PIE0:
PPG interrupt enable
bit
While this bit is "1", an interrupt request is issued as soon as PUF0 is set to "1". No
interrupt request is issued while this bit is set to "0".
bit3
PUF0:
PPG underflow bit
In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to "1"
when an underflow occurs as a result of the ch0 counter value becoming from 00H to FFH.
In 16-bit PPG mode, this bit is set to "1" when an underflow occurs as a result of the
Channel 0 and 1 counter value changing from 0000H to FFFFH. To set this bit to "0", write
"0". Writing "1" to this bit has not effect. Upon a read operation during a read-modifywrite instruction, "1" is read.
bit0
Reserved
This is a reserved bit. When setting PPGC0, always set this bit to "1".
221
CHAPTER 15 8/16-BIT PPG
15.3.2
PPG1 Operation Mode Control Register (PPGC1)
PPGC1 is a 8-bit control register that selects the operation mode of the block, controls
pin outputs, selects count clock, and controls triggers.
■ PPG1 Operation Mode Control Register (PPGC1)
Figure 15.3-3 Configuration of the PPG1 Operation Mode Control Register
bit15
Address:
ch1 000039H
Other channels:
ch3 00003DH
ch5 000041H
ch7 000048H
ch9 000049H
chB 00004DH
bit14
bit13
bit12
bit11
bit10
bit9
bit8
PEN1
-
PE10
PIE1
PUF1
MD1
MD0
Reserved
R/W
-
R/W
R/W
R/W
R/W
R/W
W
Initial value:
0X000001B
Reserved
1
MD1
MD0
0
0
8-bit PPG 2ch independent mode
0
1
8-bit prescaler + 8-bit PPG 1ch mode
1
0
Reserved
1
16-bit PPG 1ch mode
PPG counter underflow is not detected.
1
PPG counter underflow is detected.
PPG interrupt enable bit
0
Interrupt disabled.
1
Interrupt enabled.
PE10
PPG output enable 10 bit
0
Pulse output disabled (general-purpose port).
1
Pulse output enabled.
PEN1
222
PPG underflow flag bit
0
PIE1
: Readable / writable
: Write only
: Undefined value
: Undefined
: Initial value
PPG count mode bit
1
PUF1
R/W
W
X
When setting PPGC1, always set this bit to 1.
PPG enable bit
0
Stop ( "L" level output msintsinrd).
1
PPG operation enabled.
CHAPTER 15 8/16-BIT PPG
Table 15.3-2 Bit Function Description of the PPG1 Operation Mode Control Register
Bit name
Function
bit15
PEN1:
Operation enable bit
When set to "1", this bit enables the counter operation of the PPG. When operation
is disabled but output is enabled (bit13), a low level is maintained at the output.
bit13
PE10:
PPG10 pin output
enable bit
When set to "1", this bit enables the pulse output. For MB90945 series, the pulse
signal is output to the "PPG10" external pin. When disabled, the pin can be used as
general-purpose port.
bit12
PIE1:
PPG interrupt enable
bit
While this bit is "1", an interrupt request is issued as soon as PUF1 is set to "1". No
interrupt request is issued while this bit is set to "0".
bit11
PUF1:
PPG underflow bit
In 8-bit PPG 2-channel mode or 8-bit prescaler + 8-bit PPG mode, this bit is set to
"1" when an underflow occurs as a result of the ch0 counter value becoming from
00H to FFH. In 16-bit PPG mode, this bit is set to "1" when an underflow occurs as a
result of the Channel 0 and 1 counter value changing from 0000H to FFFFH. To set
this bit to "0", write "0". Writing "1" to this bit has not effect. Upon a read operation
during a read-modify-write instruction, "1" is read.
bit10,
bit9
MD1, MD0:
PPG count mode bit
These bits select the PPG timer operation mode as described in Figure 15.3-3. Do
not set "10" in these bits.
To write "01B" to these bits, ensure that "01B" is not written to the PEN0 bit of
PPGC0 or PEN1 bit of PPGC1. Write "11B" or "00B" in both the PEN0 and PEN1
bits simultaneously.
To write "11B" to these bits, update PPGC0 and PPGC1 by word transfer and write
"11B" or "00" to both the PEN0 and PEN1 bits simultaneously.
bit8
Reserved
This is a reserved bit. When setting PPGC1, always write "1" to this bit.
223
CHAPTER 15 8/16-BIT PPG
15.3.3
PPG0/1 Clock Select Register (PPG01)
PPG01 is an 8-bit control register that controls the counter clock of the 8/16-bit PPG.
■ PPG0/1 Clock Select Register (PPG01)
Figure 15.3-4 Configuration of the PPG0/1 Clock Select Register (PPG01)
Address:
ch01 00003AH
Other channels:
ch23 00003EH
ch45 000042H
ch67 000046H
ch89 00004AH
chAB 00004EH
R/W
X
-
224
bit1
bit0
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
bit7
bit6
-
-
R/W
-
-
R/W
: Readable / writable
: Undefined value
: Undefined
: Initial value
bit5
R/W
bit4
R/W
bit3
R/W
bit2
R/W
Initial value:
0 0 0 0 0 0 X XB
PCM2
PCM1
PCM0
0
0
0
Count clock selection bit (ch0)
Peripheral Clock
0
0
1
Peripheral Clock/2
0
1
0
Peripheral Clock/4
0
1
1
Peripheral Clock/8
1
0
0
Peripheral Clock/16
1
1
1
Clock input from timebase timer
PCS2
PCS1
PCS0
0
0
0
Peripheral Clock
0
0
1
Peripheral Clock/2
0
1
0
Peripheral Clock/4
0
1
1
Peripheral Clock/8
1
0
0
Peripheral Clock/16
1
1
1
Clock input from timebase timer
Count clock selection bit (ch1)
CHAPTER 15 8/16-BIT PPG
Table 15.3-3 Bit Function Description of the Clock Select Register (PPG01)
Bit name
bit7 to bit5
bit4 to bit2
PCS2 to PCS0:
Count clock selection
bit (ch1)
PCM2 to PCM0:
Count clock selection
bit (ch0)
Function
These bits select the operation clock for the down counter of channel 1 as described
below.
Note:
In 8-bit prescaler + 8-bit PPG mode or in 16-bit PPG mode, ch1 PPG operates in
response to a counter clock from ch0. Therefore, the setting in these bits has no
effect.
PCS2
PCS1
PCS0
Operation mode
0
0
0
Peripheral clock (62.5 ns machine clock, 16 MHz)
0
0
1
Peripheral clock/2 (125 ns machine clock, 16 MHz)
0
1
0
Peripheral clock/4 (250 ns machine clock, 16 MHz)
0
1
1
Peripheral clock/8 (500 ns machine clock, 16 MHz)
1
0
0
Peripheral clock/16 (1 μs machine clock, 16 MHz)
1
0
1
Clock input from the timebase timer (128 μs, 4 MHz
source oscillation)
These bits select the operation clock for the down counter of channel 0 as described
below.
PCM2
PCM1
PCM0
Operation mode
0
0
0
Peripheral clock (62.5 ns machine clock, 16 MHz)
0
0
1
Peripheral clock/2 (125 ns machine clock, 16 MHz)
0
1
0
Peripheral clock/4 (250 ns machine clock, 16 MHz)
0
1
1
Peripheral clock/8 (500 ns machine clock, 16 MHz)
1
0
0
Peripheral clock/16 (1 μs machine clock, 16 MHz)
1
0
1
Clock input from the timebase timer (128 μs, 4 MHz
source oscillation)
225
CHAPTER 15 8/16-BIT PPG
15.3.4
Reload Register (PRLL/PRLH)
The reload registers (PRLL and PRLH) are 8-bit registers that store reload values for the
PCNT down counters. The PRLL and PRLH registers are readable and writable.
■ Reload Registers (PRLL/PRLH)
Figure 15.3-5 Configuration of the Reload Registers
Reload register H (PRLHn)
Address: ch0 003501H
ch1 003503H
ch2 003505H
ch3 003507H
ch4 003509H
ch5 00350BH
ch6 00350DH
ch7 00350F H
ch8 003511 H
ch9 003513 H
chA 003515H
chB 003517H
Reload register L (PRLLn)
Address: ch0 003500H
ch1 003502H
ch2 003504H
ch3 003506H
ch4 003508H
ch5 00350AH
ch6 00350BH
ch7 00350EH
ch8 003510 H
ch9 003512 H
chA 003514H
chB 003516H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value:
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value:
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
n = 0, 1, ... , 9, A, B
R/W : Readable / writable
Table 15.3-4 Register Function of the Reload Registers
Register name
Function
PRLLn
Holds the "L" side reload value.
PRLHn
Holds the "H" side reload value.
Note:
In 8-bit prescaler + 8-bit PPG mode, different values in PRLL and PRLH of ch0 may cause the PPG
waveform of ch1 to vary in each cycle. Write the same value to PRLL and PRLH of ch0.
226
CHAPTER 15 8/16-BIT PPG
15.4
Operations of 8/16-Bit PPG
One 8/16-bit PPG consists of two channels of 8-bit PPG units. These two channels can
be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG
mode, and single-channel 16-bit PPG mode.
■ Operations of 8/16-bit PPG
Each of the 8-bit PPG units has two eight-bit reload registers. One reload register is for the "L" pulse width
(PRLL) and the other is for the "H" pulse width (PRLH). The values stored in these registers are reloaded
into the 8-bit down counter (PCNT), from the PRLL and PRLH in turn. The pin output value is inverted
upon a reload caused by counter borrow. This operation results in the pulses of the specified "L" pulse
width and "H" pulse width.
Table 15.4-1 lists the relationship between the reload operation and pulse outputs.
Table 15.4-1 Reload Operation and Pulse Output
Reload operation
Pin output change
PRLH → PCNT
PPG0/PPG1
[0 → 1]
Rise
PRLL → PCNT
PPG0/PPG1
[1 → 0]
Fall
When "1" is set in bit4 (PIE0) of PPGC0 or in bit12 (PIE1) of PPGC1, an interrupt request is output upon a
borrow from 00H to FFH (from 0000H to FFFFH in 16-bit PPG mode) of each counter.
■ Operation Modes of 8/16-bit PPG
This block can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG mode,
and single-channel 16-bit PPG mode.
● Independent two-channel mode
The two channels of 8-bit PPG units operate independently. The PPG00 pin is connected to the ch0 PPG
output, while the PPG10 pin is connected to the ch1 PPG output.
● 8-bit prescaler + 8-bit PPG mode
ch0 is used as an 8-bit prescaler while the count in ch1 is based on borrow outputs from ch0. Thus, 8-bit
PPG waveforms can be output with arbitrary length of cycle time. The PPG00 pin is connected to the ch0
prescaler output, while the PPG10 pin is connected to the ch1 PPG output.
● 16-bit PPG 1ch mode
ch0 and ch1 are connected and used as a single 16-bit PPG. The PPG00 and PPG10 pins are connected to
the 16-bit PPG output.
227
CHAPTER 15 8/16-BIT PPG
■ 8/16-bit PPG Output Operation
In this block, the ch0 PPG is activated to start counting when "1" is written to bit7 (PEN0) of the PPGC0
(PWM operation mode control) register. Similarly, the ch1 PPG is activated to start counting when "1" is
written to bit15 (PEN1) of the PPGC1 register. Once the operation has started, counting is terminated by
writing "0" to bit7 (PEN0) of PPGC0 or in bit15 (PEN1) of PPGC1. Once the counting is terminated, the
output is maintained at the "L" level.
In 8-bit prescaler + 8-bit PPG mode, do not set ch1 to be in operation while ch0 operation is stopped.
In 16-bit PPG mode, ensure that bit7 (PEN0) of PPGC0 register and bit15 (PEN1) of PPGC1 register are
started or stopped simultaneously. The figure below is a diagram of PPG output operation. During PPG
operation, a pulse wave is continuously output at a frequency and duty ratio (the ratio of the "H"-level
period of the pulse wave to the "L"-level period). PPG continues operation until stop is specified explicitly.
Figure 15.4-1 PPG Output Operation, Output Waveform
PEN
Starts operation based on PEN (from "L" side).
Output pin
PPG
T
(L+1)
T
(H+1)
(Start)
L : PRLL value
H : PRLH value
T : Input from peripheral clock ( , /4, /16)
or timer base counter (depending on the
clock selection by PPG01)
■ Relationship between 8/16-bit PPG Reload Value and Pulse Width
The width of the output pulse is determined by adding 1 to the reload register value and multiplying it by
the count clock cycle. Note that when the reload register value is 00H during 8-bit PPG operation or 0000H
during 16-bit PPG operation, the pulse width is equivalent to one count clock cycle. In addition, note that
when the reload register value is FFH during 8-PPG operation, the pulse width is equivalent to 256 count
clock cycles. When the reload register value is FFFFH during 16-bit PPG operation, the pulse width is
equivalent to 65536 count clock cycles.
Pl =T
Ph=T
228
(L+1)
(H+1)
L
H
: PRLL value
: PRLH value
T : Input clock cycle
Ph : High pulse width
Pl : Low pulse width
CHAPTER 15 8/16-BIT PPG
15.5
Selecting a Count Clock for 8/16-Bit PPG
The count clock used for the operation is supplied from the peripheral clock or the
timebase timer. The count clock can be selected from six choices.
■ Selecting a Count Clock for 8/16-bit PPG
Select ch0 clock at bit4 to bit2 (PCM2 to PCM0) of the PPG01 register, and ch1 clock at bit7 to bit5 (PCS2
to PCS0) of the PPG01 register.
The clock is selected from a peripheral clock 1/16 to 1 times higher than a machine clock or an input clock
from the timebase timer.
In 8-bit prescaler + 8-bit PPG mode or 16-bit PPG mode, however, the setting in the PCS2 to PCS0 has no
effect.
When the timebase timer input is used, the first count cycle after a trigger or a stop may be shifted. The
cycle may also be shifted if the timebase counter is cleared during operation of this module.
In 8-bit prescaler + 8-bit PPG mode, if ch1 is activated while ch0 is in operation and ch1 is stopped, the
first count cycle may be shifted.
229
CHAPTER 15 8/16-BIT PPG
15.6
Controlling Pin Output of 8/16-Bit PPG Pulses
The pulses generated by this module can be output from external pins PPG00 and
PPG10.
■ Controlling Pin Output of 8/16-bit PPG Pulses
To output the pulses from an external pin, write "1" to the bit corresponding to each pin (PPGC0: PE00,
PPGC1: PE10). When "0" is written to these bits (default), the pulses are not output from the corresponding
external pins; the pins work as general-purpose ports.
In 16-bit PPG mode, the same waveform is output from PPG00 and PPG10. Thus, the same output can be
obtained by enabling both external pin.
In 8-bit prescaler + 8-bit PPG mode, the 8-bit prescaler toggle output waveform is output from PPG00,
while the 8-bit PPG waveform is output from PPG10. Figure 15.6-1 is a diagram of output waveforms in
this mode.
Figure 15.6-1 8+8 PPG Output Operation Waveform
Ph0
Pl0
PPG0
PPG1
Ph1
Pl0 = T
Pl1
(L0+1)
Ph0 = T
(L0+1)
Pl1 = T
(L0+1)
(L1+1)
Ph1 = T
(L0+1)
(H1+1)
L0 :
L1 :
H1 :
T :
Ph0 :
Pl0 :
Ph1 :
ch0 PRLL value and ch0 PRLH value
ch1 PRLL value
ch1 PRLH value
Input clock cycle
PPG00 "H" pulse width
PPG00 "L" pulse width
PPG10 "H" pulse width
Pl1 :
PPG10 "L" pulse width
Note:
Set the same value in ch0 PRLL and ch0 PRLH.
230
CHAPTER 15 8/16-BIT PPG
15.7
8/16-Bit PPG Interrupts
For the 8/16-bit PPG, an interrupt becomes active when the reload value counts out and
a borrow occurs.
■ 8/16-bit PPG Interrupts
In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, an interrupt is requested by a borrow in each
counter. In 16-bit PPG mode, PUF0 and PUF1 are simultaneously set by a borrow in the 16-bit counter.
Therefore, enable only PIE0 or PIE1 to unify the interrupt causes. In addition, simultaneously clear the
interrupt flags for PUF0 and PUF1.
231
CHAPTER 15 8/16-BIT PPG
15.8
Initial Values of 8/16-Bit PPG Hardware
The hardware components of this block are initialized to the following values when
reset:
■ Initial Values of 8/16-bit PPG Hardware
● Registers
•
PPGC0 → 0X000XX1B
•
PPGC1 → 0X000001B
•
PPG01 → 000000XXB
● Pulse outputs
•
PPG00 → "L"
•
PPG10 → "L"
•
PE00
→
PPG00 output disabled
•
PE10
→
PPG10 output disabled
● Interrupt requests
•
IRQ0 → "L"
•
IRQ1 → "L"
Hardware components other than the above are not initialized.
Note:
In a mode other than 16-bit PPG mode, it is recommended to use a word transfer instruction to write
data in reload registers PRLL and PRLH. If two byte transfer instructions are used to write a data item
to these registers, a pulse of unexpected cycle time may be output depending on the timing.
Figure 15.8-1 Write Timing for 8/16-bit PPG Reload Registers (PRLL and PRLH)
PPG0
B
A
C
B
A
➀
B
C
C
D
D
Assume that PRLL is updated from A to C before point ➀ in the time chart above, and PRLH is updated
from B to D after point ➀. Since the PRL values at point ➀ are PRLL=C and PRLH=B, a pulse of L side
count value C and H side count value B is output only once.
Similarly, to write data in PRL of ch0 and ch1 in 16-bit PPG mode, use a long word transfer instruction, or
use word transfer instructions in the order of ch0 and then ch1. In this mode, the data is only temporarily
written to ch0 PRL. Then, the data is actually written into ch0 PRL when the ch1 PRL is written to.
232
CHAPTER 15 8/16-BIT PPG
In a mode other than 16-bit PPG mode, ch0 and ch1 PRL are written independently.
Figure 15.8-2 PRL Write Operation Block Diagram
ch0 PRL write data
ch1 PRL write data
Transferred in synchronization
with ch1 write in 16-bit
Temporary latch
PPG mode
ch0 write in a mode other
than 16-bit PPG mode
ch1 write
ch0 PRL
ch1 PRL
233
CHAPTER 15 8/16-BIT PPG
234
CHAPTER 16
DTP/EXTERNAL
INTERRUPTS
This chapter explains the functions and operations of
the DTP/external interrupts.
16.1 Outline of DTP/External Interrupts
16.2 DTP/External Interrupt Registers
16.3 Operations of DTP/External Interrupts
16.4 Switching between DTP and External Interrupt Requests
16.5 Notes on Using DTP/External Interrupts
235
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.1
Outline of DTP/External Interrupts
The data transfer peripheral (DTP) is located between an external peripheral and the
F2MC-16LX CPU. The DTP receives a DMA request or interrupt request from the external
peripheral, transfers the request to the F2MC-16LX CPU to activate the intelligent I/O
service or interrupt processing.
■ Outline of DTP/external Interrupts
For the intelligent I/O service, "H" and "L" request levels are available. For an external interrupt request,
four request levels are available: "H", "L", rising edge, and falling edge.
For the MB90945 series, the external bus interface is not supported. Therefore the DTP/external interrupt
can not serve as the data transfer peripheral. It can be only used as the external interrupt.
■ Block Diagram of DTP/external Interrupts
Figure 16.1-1 Block Diagram of DTP/external Interrupts
8
8
Interrupt/DTP enable register
Gate
8
Edge detection circuit
Cause F/F
8
Request input
Interrupt/DTP cause register
16
Request level setting register
■ DTP/external Interrupts Registers
Figure 16.1-2 DTP/external Interrupt Registers
Address : 000030H
Address : 000031H
Address : 000032H
Address : 000033H
236
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
Interrupt/DTP enable register
(ENIR)
External interrupt request register
(EIRR)
Request level setting register
(ELVR)
Request level setting register
(ELVR)
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.2
DTP/External Interrupt Registers
The DTP/external interrupts has the following three types of registers:
• Interrupt/DTP enable register (ENIR: interrupt request enable register)
• Interrupt/DTP flag (EIRR: external interrupt request register)
• Request level setting register (ELVR: external level register)
■ Interrupt/DTP Enable Register (ENIR: Interrupt Request Enable Register)
Address:
000030H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable / writable
ENIR enables the function to issue a request to the interrupt controller using a device pin as a DTP/external
interrupt request input. A pin corresponding to a "1" bit of this register is used as a DTP/external interrupt
request input. A pin corresponding to a "0" bit holds the DTP/external interrupt request input cause, but
does not issue a request to the interrupt controller.
■ Interrupt/DTP Flag (EIRR: External Interrupt Request Register)
Address:
000031H
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
XXXXXXXX B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W ........ The objects differ
R/W: Readable / writable
for R and W.
The EIRR indicates the presence of DTP/external interrupt requests at the pins corresponding to the "1" bits
of this register. Writing "0" to a bit of this register clears the corresponding request flag. Writing "1" has no
effect. "1" is always read from this register by a read-modify-write instruction.
Note:
If multiple external interrupt request outputs are enabled (ENIR: EN3 to EN0=1), only the bits for
which the CPU accepts an interrupt (bits for which "1" was set in ER3 to ER0) are cleared. No other
bits must be cleared unconditionally.
237
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
■ Request Level Setting Register (ELVR: External Level Register)
Address :
000032 H
Address :
000033 H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
LB3
LA3
LB2
LA2
LB1
LA1
LB0
LA0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W: Readable / writable
ELVR defines the request event at the external pin. Each pin is assigned two bits as described in Table
16.2-1. If a request is detected by the input level, the interrupt flag is set as long as the input is at the
specified level even after the flag is reset by software.
Table 16.2-1 Interrupt Request Detection Factor for External Pins
238
LBx
LAx
Interrupt request detection factor
0
0
"L" level pin input
0
1
"H" level pin input
1
0
Rising edge pin input
1
1
Falling edge pin input
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.3
Operations of DTP/External Interrupts
When the interrupt flag is set, this block signals an interrupt to the interrupt controller.
The interrupt controller judges the priority levels of the simultaneous interrupts, and
issues an interrupt request to the F2MC-16LX CPU if the interrupt from this block has
the highest priority. The F2MC-16LX CPU compares the ILM bits of its internal CCR
register and the interrupt request. If the interrupt level of the request is higher than that
indicated by the ILM bits, the F2MC-16LX CPU activates the hardware interrupt
processing microprogram as soon as the currently executing instruction is terminated.
■ External Interrupt Operation
In the hardware interrupt processing microprogram, the CPU reads the ISE bit information from the
interrupt controller, identifies that the request is for interrupt processing based on that information, and
branches to the interrupt processing microprogram. The interrupt processing microprogram reads the
interrupt vector area and issues an interrupt acknowledgment signal for the interrupt controller. Then, the
microprogram transfers the jump destination address of the macro instruction generated from the vector to
the program counter, and executes the user interrupt processing program.
Figure 16.3-1 External Interrupt
DTP/external interrupt
Interrupt controller
F2MC-16LX CPU
ICRyy
IL
Other request
ELVR
EIRR
ENIR
Cause
CMP
ICRxx
CMP
ILM
INTA
239
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
■ DTP Operation
To activate the intelligent I/O service, the user program initially sets the address of a register, assigned
between 000000H and 0000FFH, in the I/O address pointer of the intelligent I/O service descriptor. Then,
the user program sets the start address of the memory buffer in the buffer address pointer.
The DTP operation sequence is almost the same as for external interrupts. The operation is identical until
the CPU activates the hardware interrupt processing microprogram. Then, for the DTP, control is
transferred to the intelligent I/O service processing microprogram, since the ISE bit read by the CPU within
the hardware interrupt processing microprogram indicates the DTP. Once the intelligent I/O service is
activated, a read or write signal is sent to the addresses external peripheral, and data is transferred between
the peripheral and the chip. The external peripheral must cancel the interrupt request to this chip within
three machine cycles after the transfer is made. When the transfer is completed, the descriptor is updated,
and the interrupt controller generates a signal that clears the transfer cause. Upon receiving the signal to
clear the transfer cause, this resource clears the flip-flop holding the cause and prepares for the next request
from the pin. For details of the intelligent I/O service processing, refer to the "MB90500 Programming
Manual".
Figure 16.3-2 Timing to Cancel the External Interrupt at the End of DTP Operation
Edge request or "H" level request
Internal operation
Interrupt cause
* When data is transferred from the I/O register to memory
in the intelligent I/O service
Selecting and
reading
descriptor
Read address
Address bus pin
Data bus pin
Write address
Read data
Write data
Read signal
Write signal
Cancel within three machine cycles.
Data, address
bus
Internal bus
Register
External peripheral
Figure 16.3-3 Sample Interface to the External Peripheral
INT
IRQ
DTP
Cancel within three machine
cycles after transfer.
240
MB90945
CORE
MEMORY
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.4
Switching between DTP and External Interrupt Requests
To switch between DTP and external interrupt requests, use the ISE bit in the ICR
register corresponding to this block, which is in the interrupt controller. Each pin is
individually assigned ICR. Thus, a pin is used for a DTP request if "1" is written to the
ISE bit of the corresponding ICR, and is used for an external interrupt request if "0" is
written to the bit.
■ Switching between DTP and External Interrupt Requests
Figure 16.4-1 Switching between DTP and External Interrupt Requests
Interrupt controller
0
ICR xx
ICR yy
1
F2MC-16LX CPU
Pin
DTP/external
interrupt
DTP
External interrupt
241
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
16.5
Notes on Using DTP/External Interrupts
Note carefully the following items when using DTP/external interrupts:
• Conditions on the externally connected peripheral when DTP is used
• DTP/external interrupt operation procedure
• External interrupt request level
■ Notes on Using DTP/external Interrupts
● Conditions on the externally connected peripheral when DTP is used
DTP supports only external peripherals that automatically clear a request once a transfer is completed. The
system must be designed so that a transfer request is canceled within three machine cycles (provisional)
after transfer operation starts. Otherwise, this resource assumes that a transfer request is issued.
● DTP/external interrupt operation procedure
To set registers in the DTP/external interrupt, follow the steps below:
1. Disable the bits corresponding to the enable register.
2. Set the bits corresponding to the request level setting register.
3. Clear the bits corresponding to the cause register.
4. Enable the bits corresponding to the enable register.
(Steps 3. and 4. can be simultaneously performed by word specification.)
To set a register in this resource, ensure that the enable register is disabled. Before enabling the enable
register, ensure that the cause register is cleared. Clearing the cause register prevents a false interrupt cause
from being determined while registers are set or interrupts are enabled.
● External interrupt request level
To detect an edge for an edge request level, you need at least the minimum pulse width described in
datasheet. Please refer to it.
As shown in Figure 16.5-1, when the request input level is related to the level setting, a request that is input
from an external device to the interrupt controller is kept active even if the request is later canceled because
a cause hold circuit has been installed. To cancel the request to the interrupt controller, the cause hold
circuit must be cleared as shown in Figure 16.5-2.
Figure 16.5-1 Clearing the Cause Hold Circuit upon Level Set
Level detection
Interrupt cause
Cause F/F (interrupt/DTP
cause register)
The cause is kept held unless cleared.
242
Enable gate
To interrupt
controller
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
Figure 16.5-2 Interrupt Cause and Interrupt Request to the Interrupt Controller while Interrupts are
Enabled
Interrupt cause
"H" level
Interrupt request to
the interrupt controller
Set inactive when the cause F/F is cleared.
243
CHAPTER 16 DTP/EXTERNAL INTERRUPTS
244
CHAPTER 17
8/10-BIT A/D CONVERTER
This chapter explains the functions and operations of
the 8/10-bit A/D converter.
17.1 Outline of the 8/10-Bit A/D Converter
17.2 Configuration of the 8/10-Bit A/D Converter
17.3 8/10-Bit A/D Converter Pins
17.4 8/10-Bit A/D Converter Registers
17.5 8/10-Bit A/D Converter Interrupts
17.6 Operation of the 8/10-Bit A/D Converter
17.7 Notes on the 8/10-Bit A/D Converter
17.8 Sample Program 1 for the 8/10-Bit A/D Converter
(Single Conversion Mode Using EI2OS)
17.9 Sample Program 2 for the 8/10-Bit A/D Converter
(Continuous Conversion Mode Using EI2OS)
17.10 Sample Program 3 for the 8/10-Bit A/D Converter
(Stop Conversion Mode Using EI2OS)
245
CHAPTER 17 8/10-BIT A/D CONVERTER
17.1
Outline of the 8/10-Bit A/D Converter
Using the RC-type successive approximation conversion method, the 8/10-bit A/D
converter converts an analog input voltage into a 10-bit or 8-bit digital value. An input
signal is selected from fifteen channels for analog input pins. The conversion can be
activated by software and external trigger.
■ Functions of the 8/10-bit A/D Converter
The converter converts the analog voltage input to an analog input pin (input voltage) to a digital value.
The converter has the following features:
• The minimum conversion time is 4.9 μs (only possible at certain machine clock frequencies; includes
the sampling time).
• The minimum sampling time is 1.6 μs (only possible at certain machine clock frequencies).
• The converter uses the RC-type successive approximation conversion method with a sample hold
circuit.
• A resolution of 10 bits or 8 bits can be selected.
• Up to 15 channels for analog input pins can be selected by a program.
• At the end of A/D conversion, an interrupt request can be generated and EI2OS can be activated.
• In the interrupt-enabled state, the conversion data protection function prevents any part of the data from
being lost through continuous conversion.
• The conversion can be activated by software and external trigger.
• The MB90945 series has 15 analog inputs, where from either channels 0 to 7 or channels 8 to 14 can be
selected as inputs for the A/D converter.
Table 17.1-1 8/10-bit A/D Converter Conversion Modes
Single conversion
Scan conversion
Single conversion
mode
Converts the input of a specified
channel (single channel) just once.
Converts the inputs of two or more consecutive channels (up
to eight channels) just once. Either channels 0 to 7 or 8 to 14
can be selected.
Continuous
conversion mode
Converts the input of a specified
channel (single channel) repeatedly.
Converts the inputs of two or more consecutive channels (up
to eight channels) repeatedly.Either channels 0 to 7 or 8 to 14
can be selected.
Stop conversion
mode
Converts the input of a specified
channel (single channel), after
which it is on standby for the next
activation.
Converts the inputs of two or more consecutive channels (up
to eight channels). Either channels 0 to 7 or 8 to 14 can be
selected.
When a channel has been converted, the converter is put on
standby for the next activation.
246
CHAPTER 17 8/10-BIT A/D CONVERTER
Table 17.1-2 8/10-bit A/D Converter Interrupts and EI2OS
Interrupt control register
Vector table address
EI2OS
Interrupt No.
#31 (1FH)
Register name
Address
Lower
Upper
Bank
ICR10
0000BAH
FFFF80H
FFFF81H
FFFF82H
Available
247
CHAPTER 17 8/10-BIT A/D CONVERTER
17.2
Configuration of the 8/10-Bit A/D Converter
The 8/10-bit A/D converter has nine blocks:
• A/D control status register (ADCS0, ADCS1)
• A/D data register (ADCR0, ADCR1)
• Clock selector (Input clock selector for activating A/D conversion)
• Decoder
• Analog channel selector
• Sample hold circuit
• D/A converter
• Comparator
• Control circuit
■ Block Diagram of the 8/10-bit A/D Converter
Figure 17.2-1 Block Diagram of the 8/10-bit A/D Converter
Interrupt request signal #31 (1FH)
A/D control status register
(ADCS0/ADCS1)
BUSY INT INTE PAUS STS1 STS0 STRT Reserved MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
6
PB6/AN14
PB5/AN13
PB4/AN12
PB3/AN11
PB2/AN10
PB1/AN9
PB0/AN8
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
ADSEL
A/D data register
(ADCR0/ADCS1)
: Machine clock
- : Undefined
248
2
Clock selector
Analog
channel
selector
S10 ST1 ST0 CT1 CT0
Decoder
Internal data bus
16-bit reload timer 1 output
External trigger (ADTG)
φ
Sample
hold circuit
AVRH/L
AVcc
AVss
Comparator
Control circuit
2
D/A converter
2
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CHAPTER 17 8/10-BIT A/D CONVERTER
● A/D control status register (ADCS0, ADCS1)
This register selects activation by software or another activation trigger, the conversion mode, and the A/D
conversion channel. It also enables or disables interrupt requests, checks the interrupt request status, and
indicates whether the conversion has halted or is in progress.
● A/D data register (ADCR0, ADCR1)
This register holds the result of A/D conversion and selects the resolution for A/D conversion.
● Clock selector
This selector selects the clock for activating A/D conversion. External trigger (ADTG) can be used as the
activation clock.
● Decoder
This circuit selects the analog input pin to be used based on the settings of the ANE0 to ANE2 bits and
ANS0 to ANS2 bits of the A/D control status register (ADCS0).
● Analog channel selector
This circuit selects the pin to be used from fifteen analog input pins.
● Sample hold circuit
This circuit maintains the input voltage of the channel selected by the analog channel selector. It samples
and maintains the input voltage obtained immediately after the activation of A/D conversion. This circuit
protects the A/D conversion from any variations in the input voltage during approximation.
● D/A converter
This circuit generates a reference voltage for comparison with the input voltage maintained by the sample
hold circuit.
● Comparator
This circuit compares the input voltage maintained by the sample hold circuit with the output voltage of the
D/A converter to determine which is greater.
● Control circuit
This circuit determines the A/D conversion value based on the decision signal generated by the comparator.
When the A/D conversion has been completed, the circuit sets the conversion result in the A/D data register
(ADCR0, ADCR1) and generates an interrupt request.
249
CHAPTER 17 8/10-BIT A/D CONVERTER
17.3
8/10-Bit A/D Converter Pins
This section describes the 8/10-bit A/D converter pins and provides pin block diagrams.
■ 8/10-bit A/D Converter Pins
The A/D converter pins are also used as general ports.
Table 17.3-1 8/10-bit A/D Converter Pins
Function
Pin name
Ch 0
P60/AN0
Ch 1
P61/AN1
Ch 2
P62/AN2
Ch 3
P63/AN3
Ch 4
P64/AN4
Ch 5
P65/AN5
Ch 6
P66/AN6
Ch 7
P67/AN7
Ch 8
PB0/AN8
Ch 9
PB1/AN9
Ch 10
PB2/AN10
Ch 11
PB3/AN11
Ch 12
PB4/AN12
Ch 13
PB5/AN13
Ch 14
PB6/AN14
Pin function
Input-output signal type
Pull-up option
Standby control
CMOS output/automotive
hysteresis input or analog
input
Not selectable
Not selectable
Port 6
I/O or analog
input
Port B
I/O or analog
input
■ Analog Input Enable Registers
Figure 17.3-1 shows the analog input enable register.
Figure 17.3-1 Analog Input Enable Registers (ADER1/ADER0)
Address:
00000DH
00000CH
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
ADSEL ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value:
0111111111111111B
R/W
R/W : Readable / writable
Note:
If bit15 (ADSEL) is set to "0" the pins ANIN 0 to ANIN 7 (Port P60 to P67) are selected as inputs for
the A/D Converter. If this bit is set to "1" the pins ANIN 8 to ANIN 14 (Port PB0 to PB6) are selected
as inputs for the A/D Converter.
250
CHAPTER 17 8/10-BIT A/D CONVERTER
■ Block Diagram of the 8/10-bit A/D Converter Pins
Figure 17.3-2 Block Diagram of the P60/AN0 to P67/AN7 and PB0/AN8 to PB6/AN14pins
Internal data bus
ADER
Analog input
PDR read
Output latch
PDR
(Port data register)
PDR write
Pin
Direction latch
DDR write
DDR read
DDR
(Port direction register)
standby control (SBL = 1)
Notes:
To use a pin as an input port, set the corresponding bit of the DDR6 / DDRB register to "0", and handle
it as normal digital input. Set the corresponding bit of the ADER register to "0".
To use the pin as an analog input pin, set the corresponding bit of the ADER register to "1". The value
read from the PDR6 / PDRB register is "0".
251
CHAPTER 17 8/10-BIT A/D CONVERTER
17.4
8/10-Bit A/D Converter Registers
This section lists the 8/10-bit A/D converter registers.
■ 8/10-bit A/D Converter Registers
Figure 17.4-1 8/10-bit A/D Converter Registers
Address :
252
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
00000D / 00000CH
ADER1
ADER0
000035 / 000034H
ADCS1
ADCS0
000037 / 000036H
ADCR1
ADCR0
CHAPTER 17 8/10-BIT A/D CONVERTER
17.4.1
Analog Input Enable/ADC Select Register
The MB90945 series has 15 analog inputs but only one A/D converter with 8 inputs.
Therefore, the special bit ADSEL can be used to select the analog input channels.
■ Upper Bits of the Analog Input Enable/ADC Select Register (ADER1)
Figure 17.4-2 Configuration of the Upper Bits of Analog Input Enable/ADC Select Register (ADER1)
bit15
Address
00000D H
bit14
bit13
bit12
bit11
bit10
bit9
ADSEL ADE14 ADE13 ADE12 ADE11 ADE10 ADE9
R/W
R/W
R/W
R/W
R/W
R/W
ADEx
0
1
ADSEL
0
1
R/W : Readable / writable
: Initial value
R/W
bit8
ADE8
Initial value
01111111B
R/W
Analog input enable bits
Port input mode (port B)
Analog input mode (initial value)
ADC input selection bit
AN 0 to AN 7 (port 6) are selected as input
AN 8 to AN 14 (port B) are selected as inputs
■ Lower Bits of the Analog Input Enable Register (ADER0)
Figure 17.4-3 Configuration of the Lower Bits of the Analog Input Enable Register (ADER0)
Address
00000C H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W : Readable / writable
ADEx
0
1
Initial value
11111111B
Analog input enable bits
Port input mode (port 6)
Analog input mode (initial value)
: Initial value
253
CHAPTER 17 8/10-BIT A/D CONVERTER
17.4.2
A/D Control Status Register 1 (ADCS1)
A/D control status register 1 (ADCS1) selects activation by software or activation
trigger, enables or disables interrupt requests, and indicates interrupt request status
and whether conversion is halted or in progress.
■ Upper Bits of the A/D Control Status Register (ADCS1)
Figure 17.4-4 Configuration of the A/D Control Status Register 1 (ADCS1)
Address
000035H
bit15
bit14
BUSY
INT
INTE PAUS STS1 STS0 STRT Reserved
R/W
R/W
R/W
bit13
bit12
R/W
bit11
R/W
bit10
R/W
bit9
W
bit8
bit7
bit0
Initial value
(ADCS0)
00000000B
R/W
Reserved bit
Reserved
Always write 0 to this bit.
STRT
0
1
A/D conversion activation bit
(valid only when activated by software (ADC2: EXT= 0))
Does not activate the A/D conversion
Activate the A/D conversion function
A/D activation select bit
STS1 STS0
0
0
Activation by software
0
1
1
0
1
1
Activation by external trigger or software
Activation by 16-bit reload timer 1 output
or software
Activation by external trigger, 16-bit
reload timer 1 output, or software
Halt flag bit
(valid only when EI2OS is used)
PAUS
0
1
A/D conversion is not halted
A/D conversion is halted
INTE
254
1
Enables interrupt request output
Reading
Writing
0
A/D conversion has not been completed Clears this bit.
1
A/D conversion has been completed No change,no effect on other bits
BUSY
: Readable / writable
: Write only
: Undefined
: Initial value
Disables interrupt request output
Interrupt request flag bit
INT
R/W
W
-
Interrupt request enable bit
0
Busy bit
Reading
Writing
0
A/D conveision is halted
1
A/D conversion is in progress No change,no effect on other bits
Stops the A/D conversion
CHAPTER 17 8/10-BIT A/D CONVERTER
Table 17.4-1 Function Description of Each Bit of Control Status Register 1 (ADCS1)
Bit name
bit15
bit14
bit13
Function
BUSY:
Busy bit
This bit indicates the operating status of the A/D converter.
INT:
Interrupt request flag
bit
When A/D conversion data is set in the A/D data register, this bit is set to "1".
INTE:
Interrupt request
enable bit
•
If the value read from this bit is "0", A/D conversion has halted. If the read value is "1", A/D
conversion is in progress.
• Writing "0" to this bit forces the A/D conversion to stop. Writing "1" to this bit does not change
the bit value and has no effect on other bits.
Note:
Never select forced stop (BUSY = 0) and software activation (STRT = 1) simultaneously.
•
When both this bit and the interrupt request enable bit (ADCS: INTE) are "1", an interrupt
request is generated. If EI2OS has been enabled, it is activated.
• Writing "0" to this bit clears the bit. Writing "1" to this bit does not change the bit value and has
no effect on other bits.
• When EI2OS is activated, this bit is cleared.
Note:
When clearing this bit by writing "0" it, do so only while the A/D converter is not operating.
This bit enables or disables interrupt output to the CPU.
•
•
bit12
When both this bit and the interrupt request flag bit (ADCS: INT) are set to "1", an interrupt
request is generated.
When EI2OS is used, set this bit to "1".
PAUS:
Halt flag bit
When A/D conversion stops temporarily, this bit is set to "1".
bit11,
bit10
STS1, STS0:
A/D activation select
bit
These bits select how A/D conversion is to be activated.
bit9
STRT:
A/D conversion
activation bit
This bit allows software to start A/D conversion.
Reserved
Note:
Always write "0" to this bit.
bit8
•
This A/D converter has just one A/D data register. In continuous conversion mode, if a
conversion result were written before the previous conversion result was read by the CPU, the
previous result would be lost. When continuous conversion mode is selected, the program must
be written so that the conversion result is automatically transferred to memory by EI2OS each
time a conversion is completed. This bit also protects against multiple interrupts preventing the
completion of conversion data transfer before the next conversion. When a conversion is
completed, this bit is set to "1". This status is maintained until EI2OS finishes transferring the
contents of the data register. Meanwhile, the A/D conversion is halted so that no conversion data
can be stored. When EI2OS completes the transfer, the A/D converter automatically resumes the
conversion.
Note:
This bit is valid only when EI2OS is used.
•
When two or more activation causes are shared, activation is the result of the cause that occurs
first.
Note:
Change the setting during A/D conversion only while there is no corresponding activation
cause, since the change becomes effective immediately.
• Writing "1" to this bit activates A/D conversion.
• Writing "0" to this bit doesn’t active A/D conversion.
• In stop conversion mode, conversion cannot be reactivated with this bit.
Note:
Never select forced stop (BUSY = 0) and software activation (STRT = 1) simultaneously.
255
CHAPTER 17 8/10-BIT A/D CONVERTER
17.4.3
A/D Control Status Register 0 (ADCS0)
A/D control status register 0 (ADCS0) selects the conversion mode and A/D conversion
channel.
■ A/D Control Status Register 0 (ADCS0)
Figure 17.4-5 Configuration of the A/D Control Status Register 0 (ADCS0)
bit15
Address
000034H
(ADCS: H)
bit6
bit8 bit7
bit5
bit4
bit3
bit2
bit1
bit0
MD1
MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
R/W
R/W
R/W
R/W
ANE2 ANE1 ANE0
0
0
R/W
R/W
R/W
Initial value
00000000B
R/W
A/D conversion end channel select bit
0
AN0 / AN8 pin
0
0
1
AN1 / AN9 pin
0
1
0
AN2 / AN10 pin
0
1
1
AN3 / AN11 pin
1
0
0
AN4 / AN12 pin
1
0
1
AN5 / AN13 pin
1
1
0
AN6 / AN14 pin
1
1
1
AN7 pin
A/D conversion start channel select bit
ANS2 ANS1 ANS0
Halt
0
0
0
AN0/8
0
0
1
AN1/9
0
1
0
AN2/10
0
1
1
AN3/11
1
0
0
AN4/12
1
0
1
AN5/13
1
1
0
AN6/14
1
1
1
AN7
MD1
R/W
256
: Readable / writable
: Initial value
Read during
conversion
Read during a pause in
stop conversion mode
Number of
the current
conversion
channel
Number of the last
conversion channel
MD0
A/D conversion mode select bit
0
0
Single conversion mode 1 (reactivation allowed
during operation)
0
1
Single conversion mode 2 (reactivation not
allowed during operation)
1
0
1
1
Continuous conversion mode (reactivation not
allowed during operation)
Stop conversion mode (reactivation not allowed
during operation)
CHAPTER 17 8/10-BIT A/D CONVERTER
Table 17.4-2 Function Description of Each Bit of Control Status Register 0 (ADCS0)
Bit name
Function
bit7,
bit6
MD1, MD0:
A/D conversion
mode select bit
These bits select the conversion mode of the A/D conversion function.
bit5 to
bit3
ANS2 to ANS0:
A/D conversion
start channel select
bits
These bits set the A/D conversion start channel and indicate the number of the current
conversion channel.
• When activated, A/D conversion starts from the channel specified by these bits.
• During A/D conversion, the bits indicate the number of the current conversion channel.
During a pause in stop conversion mode, the bits indicate the number of the last
conversion channel.
bit5 to
bit3
ANE2 to ANE0:
A/D conversion
start channel select
bits
These bits set the A/D conversion end channel.
• When activated, A/D conversion is performed up to the channel specified by these bits.
• When these bits specify the channel specified by ANS2 to ANS0, just that channel is
converted. In continuous or stop conversion mode, the start channel specified by ANS2
to ANS0 is converted after the channel specified by these bits. If the start channel is
greater than the end channel, the start channel to AN7 and AN0 to the end channel are
converted in that order in a single series of conversions.
• The two-bit value of the MD1 and MD0 bits determines the mode that is selected from
among four modes: single conversion mode 1, single conversion mode 2, continuous
conversion mode, and stop conversion mode.
• The operation in each mode is described below:
- Single conversion mode 1:
Just a single A/D conversion from the channel set by ANS2 to ANS0 to the channel
set by ANE2 to ANE0 is performed.
Reactivation during operation is allowed.
- Single conversion mode 2:
Just a single A/D conversion from the channel set by ANS2 to ANS0 to the channel
set by ANE2 to ANE0 is performed.
Reactivation during operation is not allowed.
- Continuous conversion mode:
A/D conversion from the channel set by ANS2 to ANS0 to the channel set by ANE2
to ANE0 is performed repeatedly. The repeated conversion continues until it is
stopped by the BUSY bit. Reactivation during operation is not allowed.
- Stop conversion mode:
A/D conversion from the channel set by ANS2 to ANS0 to the channel set by ANE2
to ANE0 is performed repeatedly with a pause after the conversion of each channel.
The repeated conversion continues until it is stopped by the BUSY bit.
Reactivation during operation is not allowed. In the pause state, the conversion is
reactivated when an activation cause selected by the STS1 and STS0 bits is
generated.
Note:
In the single conversion mode, continuous conversion mode, and stop conversion
mode, no reactivation by external trigger or software is allowed.
257
CHAPTER 17 8/10-BIT A/D CONVERTER
17.4.4
A/D Data Register (ADCR0, ADCR1)
The A/D data register (ADCR0, ADCR1) holds the result of A/D conversion and selects
the resolution of A/D conversion.
■ A/D Data Register (ADCR0, ADCR1)
Figure 17.4-6 A/D Data Register (ADCR0, ADCR1)
Bit15 Bit14 Bit13 Bit12 Bit11
Bit1 Bit10
Bit0 Bit9
6H S10
000037h
R/W
W
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Initial value
ST1
ST0
CT1
CT0
-
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
00000XXX B
W
W
W
W
-
R
R
R
R
R
R
R
R
R
R
XXXXXXXXB
AD data bit
D0 to D9
Conversion data
R
W
X
-
: Read only
: Write only
: Undefined value
: Undefined
Comparison time setting bit
CT1
0
0
1
1
CT0
00
1
0
1
44 machine cycles (5.50µ[email protected])
66 machine cycles (3.3µ[email protected] )
88 machine cycles (3.67µ[email protected])
176 machine cycles (7.33µ[email protected])
ST1
00
0
1
1
ST0
0
1
0
1
Sampling time setting bit
20 machine cycles (2.5µ[email protected])
32 machine cycles (1.6µ[email protected])
48 machine cycles (2.0µ[email protected])
128 machine cycles (5.33µ[email protected])
S10
0
1
A/D conversion resolution selection bit
10-bit resolution mode (D9 to D0)
8-bit resolution mode (D7 to D0)
Note:
When setting the comparison and sampling time, the minimal required value has to be respected. For
example, 44 machine cycles cannot be used with some frequencies. Please see the data sheet for the
precise specification.
258
CHAPTER 17 8/10-BIT A/D CONVERTER
Table 17.4-3 Function Description of Each Bit of A/D Data Register 0 (ADCR0)
Bit name
Function
bit15
S10:
A/D conversion
resolution selection
bit
This bit selects an A/D conversion resolution.
• Writing "0" to this bit selects a resolution of 10 bits, and writing "1" to this bit selects a
resolution of 8 bits.
Note:
The data bit to be used depends on the resolution.
bit14,
bit13
ST1, ST0:
Sampling time
setting bits
These bits select the sampling time for A/D conversion.
• When A/D conversion is activated, analog input is fetched during the time set in this
bit.
Note:
Setting these bits to "00B" during 16(20, 24)-MHz operation may disable normal
fetching of the analog voltage. The 00 setting is proposed for up to 8 MHz.
bit12,
bit11
CT1, CT0:
Comparison time
setting bits
These bits select the comparison time for A/D conversion.
• After analog input is fetched (i.e., sampling time elapses), conversion result data is
defined and stored in bit9 to bit0 of this register after the time set in these bits.
Note:
Setting these bits to "00B" during 16(20, 24)-MHz operation may disable normal
acquisition of the analog conversion value. The "00B" setting is proposed for up to 8
MHz.
bit10
Undefined
bit9 to
bit0
D9 to D0:
A/D data bits
The A/D conversion results are stored and the register is rewritten each time conversion
ends.
• Usually, the last conversion value is stored.
• The initial value of this register is undefined.
Note:
The conversion data protection function is provided. (See Section "17.6 Operation of
the 8/10-Bit A/D Converter") Do not write data to these bits during A/D conversion.
Note:
• To rewrite the S10 bit, do so while the A/D is in a pause before conversion. If the bit is rewritten after
the conversion, the contents of ADCR become undefined.
• To read the contents of the ADCR register in 10-bit mode, use a word transfer instruction (MOVW A,
002EH, etc.).
259
CHAPTER 17 8/10-BIT A/D CONVERTER
17.5
8/10-Bit A/D Converter Interrupts
The 8/10-bit A/D converter can generate an interrupt request when the data for the A/D
conversion is set in the A/D data register. This function supports the extended
intelligent I/O service (EI2OS).
■ 8/10-bit A/D Converter Interrupts
Table 17.5-1 Interrupt Control Bits of the 8/10-bit A/D Converter and the Interrupt Cause
8/10-bit A/D converter
Interrupt request flag bit
ADCS: INT
Interrupt request enable bit
ADCS: INTE
Interrupt cause
Writing the A/D conversion result to the A/D data register
When A/D conversion is performed and its result is set in the A/D data register (ADCR), the INT bit of the
A/D control status register (ADCS1) is set to "1". If the interrupt request is enabled (ADCS1: INTE = 1), an
interrupt request is output to the interrupt controller.
■ 8/10-bit A/D Converter Interrupts and EI2OS
Table 17.5-2 8/10-bit A/D Converter Interrupts and EI2OS
Interrupt control register
Interrupt no.
#31 (1FH)
Vector table address
EI2OS
Register
name
Address
Lower
Upper
Bank
ICR10
0000BAH
FFFF80H
FFFF81H
FFFF82H
Available
■ EI2OS Function of the 8/10-bit A/D Converter
Using the EI2OS function, the 10-bit A/D converter can transfer the A/D conversion result to memory.
When the transfer is performed, a conversion data protection function halts the A/D conversion until the A/
D conversion data is transferred to memory, and clears the INT bit. The function prevents any part of the
data from being lost.
260
CHAPTER 17 8/10-BIT A/D CONVERTER
17.6
Operation of the 8/10-Bit A/D Converter
The 8/10-bit A/D converter has three conversion modes: single conversion mode,
continuous conversion mode, and stop conversion mode. This section describes
operation in each mode.
■ Operation in Single Conversion Mode
In single conversion mode, the analog inputs from the channel specified by the ANS bits to the channel
specified by the ANE bits are sequentially converted. When the channels up to the end channel specified by
the ANE bits have been converted, A/D conversion stops. If the start and end channels are the same (ANS
= ANE), just the channel specified by the ANS bits is converted.
Figure 17.6-1 shows the settings required for operation in single conversion mode.
Figure 17.6-1 Settings for Single Conversion Mode
bit15
bit14
ADCS BUSY INT
bit13
bit12
bit11
bit10
bit9
bit8
bit7
INTE PAUS STS1 STS0 STRT RESV MD1
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
0
ADCR
S10
ADER
ADSEL
ST1
ST0
CT1
CT0
-
Holds the conversion data.
: Used during conversion.
: Set the bit that corresponds to the used pin to "1".
0 : Set to "0".
Reference:
The followings are sample conversion sequences in single conversion mode:
(It is assumed that ADSEL = 0.)
ANS = 000B, ANE = 011B: AN0 → AN1 → AN2 → AN3 → End
ANS = 110B, ANE = 010B: AN6 → AN7 → AN0 → AN1 → AN2 → End
ANS = 011B, ANE = 011B: AN3 → End
261
CHAPTER 17 8/10-BIT A/D CONVERTER
■ Operation in Stop Conversion Mode
In stop conversion mode, the analog inputs from the channel specified by the ANS bits to the channel
specified by the ANE bits are sequentially converted with a pause after the conversion of each channel.
When the end channel specified by the ANE bits has been processed, A/D conversion, with pauses, starts
again with the channel specified by the ANS bits. If the start and end channels are the same (ANS = ANE),
the conversion of the channel specified by the ANS bits is repeated. To reactivate conversion during a
pause, generate the activation cause specified by the STS1 and STS0 bits.
Figure 17.6-2 shows settings required for operation in stop conversion mode.
Figure 17.6-2 Settings for Stop Conversion Mode
bit15
bit14
ADCS BUSY INT
bit13
bit12
bit11
bit10
bit9
bit8
INTE PAUS STS1 STS0 STRT RESV MD1
0
ADCR
S10
ADER
ADSEL
ST1
bit7
ST0
CT1
CT0
-
1
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
1
Holds the conversion data.
: Used during conversion.
: Set the bit that corresponds to the used pin to "1".
0 : Set to "0".
1 : Set to "1".
Reference:
The followings are sample conversion sequences in stop conversion mode:
(It is assumed that ADSEL = 0.)
ANS = 000B, ANE = 011B:
AN0 → Pause → AN1 → Pause → AN2 → Pause → AN3 → Pause → AN0 → Repeat
ANS = 110B, ANE = 011B:
AN6 → Pause → AN7 → Pause → AN0 → Pause → AN1 → Pause → AN2 → Pause → AN3 →
Pause→ AN6 → Repeat
ANS = 011B, ANE = 011B:
AN3 → Pause → AN3 → Pause → Repeat
262
CHAPTER 17 8/10-BIT A/D CONVERTER
17.6.1
Conversion Using EI2OS
The 8/10-bit A/D converter can use EI2OS transfer the A/D conversion result to memory.
■ Conversion Using EI2OS
Figure 17.6-3 shows the operation flow when EI2OS is used.
Figure 17.6-3 Sample Operation Flowchart when EI2OS is Used
Start A/D conversion
Sample and hold
EI2OS started
Conversion
End conversion
Transfer dat a
Has the
data transfer been
repeated for the specified
number of
times? *
Generate an interrupt
YES
Interrupt processing
NO
Interrupt cleared
*: The number of times is determined by an EI2OS setting.
When EI2OS is used, the conversion data protection function prevents any part of the data from being lost
even in continuous conversion. Multiple data items can be safely transferred to memory.
263
CHAPTER 17 8/10-BIT A/D CONVERTER
17.6.2
A/D Conversion Data Protection Function
When A/D conversion is performed in the interrupt enabled state, the conversion data
protection function operates.
■ A/D Conversion Data Protection Function
The A/D converter has just one data register that holds conversion data. When a single A/D conversion is
completed, the data in the data register is rewritten.
If the conversion data were not transferred to memory before the next conversion data was stored, part of
the conversion data would be lost. The data protection function operates in the interrupt enabled state
(INTE = 1), as described below, to prevent loss of data.
● Data protection function when EI2OS is not used
When conversion data is stored in the A/D data register (ADCR), the INT bit of the A/D control status
register1 (ADCS1) is set to "1".
While the INT bit is "1", A/D conversion is halted.
Halt status is released when the INT bit is cleared after data in the A/D data register (ADCR) has been
transferred to memory by the interrupt routine.
● Data protection function when EI2OS is used
In continuous conversion using EI2OS, the PAUS bit of the A/D control status register1 (ADCS1) is kept at
"1" when a conversion ends. This status continues until EI2OS finishes transferring the conversion data
from the data register to memory. In the meantime, the A/D conversion is halted, and the next conversion
data is not stored. When the data transfer to memory is completed, the PAUS bit is cleared to "0" and
conversion resumes.
Figure 17.6-4 shows the operation flow of the data protection function when EI2OS is used.
264
CHAPTER 17 8/10-BIT A/D CONVERTER
Figure 17.6-4 Operation Flowchart of the Data Protection Function when EI2OS is Used
Set EI2OS
Start continuous A/D
conversion
End first conversion
Store data in the data
register
Activate EI2OS
End second conversion
Has EI2OS
ended?
NO
Halt A/D
YES
Store data in the data
register
Third conversion
Activate EI2OS
Continue
Terminate all conversions
Continue
Store data in the data
register
Activate EI2OS
Interrupt processing routine
Initialize or stop A/D
End
Note: The steps while the A/D converter is halted are omitted.
Notes:
• The conversion data protection function operates only in the interrupt enabled state (ADCS1: INTE =
1).
• If interrupts are disabled during a pause in A/D conversion while EI2OS is operating, A/D conversion
may start again. This will cause new data to be written before the old data is transferred. Reactivation
attempted during a pause will cause the old data to be destroyed.
• Reactivation attempted during a pause will destroy the standby data.
265
CHAPTER 17 8/10-BIT A/D CONVERTER
17.7
Notes on the 8/10-Bit A/D Converter
Notes on using the 8/10-bit A/D converter.
■ Usage Notes on the 8/10-bit A/D Converter
● Analog input pin
The A/D input pins are also used as the I/O pins of ports 6 and B. The corresponding port direction register
(DDR6 and DDRB) and the analog input enable register (ADER) determine which pin is used for which
purpose.
To use a pin as analog input, write "0" to the corresponding bit of DDR6, resp. of DDRB, and thereby
change the port setting to input. Then, set the analog input mode (ADEx = 1) in the ADER register and
determine the input gate of the port.
If an intermediate-level signal is input in the port input mode (ADEx = 0), a leakage current flows through
the gate.
● Sequence of turning-on the A/D converter and analog input
Do not turn-on power to the A/D converter (AVCC, AVRH, AVRL) and to the analog inputs (AN0 to AN7)
before the digital power supply (VCC) has been turned-on.
Do not turn-off the digital power supply (VCC) before power to the A/D converter and the analog inputs has
been turned-off.
● Supply voltage to the A/D converter
The supply voltage to the A/D converter (AVCC) must not exceed the digital power supply (VCC);
otherwise, latch-up may occur.
266
CHAPTER 17 8/10-BIT A/D CONVERTER
17.8
Sample Program 1 for the 8/10-Bit A/D Converter (Single
Conversion Mode Using EI2OS)
This section contains a sample program for A/D conversion in single conversion mode
using EI2OS.
■ Sample Program for Single Conversion Mode Using EI2OS
● Processing
• Analog inputs AN1 to AN3 are converted once.
• The conversion data is sequentially transferred to addresses 200H to 205H.
• A resolution of 10 bits is selected.
• The conversion is activated by software.
Figure 17.8-1 Flowchart of Program Using EI2OS (Single Conversion Mode)
Start conversion
AN1
Interrupt
Transfer by EI2OS
AN12
Interrupt
Transfer by EI2OS
AN13
Interrupt
Transfer by EI2OS
End
Interrupt sequence
Parallel processing
267
CHAPTER 17 8/10-BIT A/D CONVERTER
● Coding example
BAPL
EQU
000100H
;Lower buffer address pointer
BAPM
EQU
000101H
;Intermediate buffer address pointer
BAPH
EQU
000102H
;Upper buffer address pointer
ISCS
EQU
000103H
;EI2OS status register
IOAL
EQU
000104H
;Lower I/O address register
IOAH
EQU
000105H
;Upper I/O address register
DCTL
EQU
000106H
;Lower data counter
DCTH
EQU
000107H
;Upper data counter
DDR6
EQU
000016H
;Port direction register (for port 6)
ADER0
EQU
00000CH
;Analog input enable register
ICR10
EQU
0000BAH
;Interrupt control register for ADC
ADCS0
EQU
000034H
;A/D control status register
ADCS1
EQU
000035H
;
ADCR0
EQU
000036H
;A/D data register
ADCR1
EQU
000037H
;
;-----Main program--------------------------------------------------------------CODE
CSEG
START:
;Assumes that the stack pointer (SP) has already
;been initialized
AND
CCR,#0BFH
;Disables interrupts
MOV
ICR10,#00H
;Interrupt level: 0 (highest priority)
MOV
BAPL,#00H
;Sets the address to which the conversion data is
;transferred and stored
MOV
BAPM,#02H
;(Uses 200H to 205H)
MOV
BAPH,#00H
;
MOV
ISCS,#18H
;Transfers word data, adds 1 to the address,
;then transfers the data from I/O to memory
MOV
IOAL,#36H
;Sets the address of the analog data register as
MOV
IOAH,#00H
;the transfer source address pointer
MOV
DCTL,#03H
;Sets the EI2OS transfer count to three, which is
;the same value as the conversion count
MOV
DDR6,#11110001B ;Sets P61 to P63 as input
MOV
ADER0,#00001110B ;Sets P61/AN1 to P63/AN3 as analog inputs
MOV
CTH,#00H
;
MOV
ADCS0,#0BH
;Single activation. Converts AN1 to AN3
MOV
ADCS1,#0A2H
;Software activation. Begins A/D conversion
;Enables interrupts
MOV
ILM,#07H
;Sets ILM in PS to level 7
OR
CCR,#40H
;Enables interrupts
LOOP:
MOV
MOV
BRA
268
A,#00H
A,#01H
LOOP
;Endless loop
CHAPTER 17 8/10-BIT A/D CONVERTER
;-----Interrupt program---------------------------------------------------------ED_INT1:
MOV
I:ADCS1,#00H
;Stops A/D conversion. Clears and disables the
;interrupt flag.
RETI
;Returns from interrupt.
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFB4H
;Sets vector for interrupt #18 (12H)
DSL
ED_INT1
ORG
0FFDCH
; Sets reset vector.
DSL
START
DB
00H
; Sets single-chip mode.
VECT
ENDS
END
START
269
CHAPTER 17 8/10-BIT A/D CONVERTER
17.9
Sample Program 2 for the 8/10-Bit A/D Converter
(Continuous Conversion Mode Using EI2OS)
This section contains a sample program for A/D conversion in continuous conversion
mode using EI2OS.
■ Sample Program for Continuous Conversion Mode Using EI2OS
● Processing
• Analog inputs AN3 to AN5 are converted twice. Two conversion data items are obtained for each
channel.
• The conversion data is sequentially transferred to addresses 600H to 60BH.
• A resolution of 10 bits is selected.
• The conversion is activated by 16-bit reload timer 1 (this is possible only with MB90V390HA/HB).
Figure 17.9-1 Flowchart of Program Using EI2OS (Continuous Conversion Mode)
Start conversion
AN3
Interrupt
Transfer by EI2OS
AN4
Interrupt
Transfer by EI2OS
AN5
Interrupt
Transfer by EI2OS
After a total of
six transfers
Interrupt sequence
End
270
CHAPTER 17 8/10-BIT A/D CONVERTER
● Coding example
BAPL
BAPM
BAPH
ISCS
IOAL
IOAH
DCTL
DCTH
DDR6
ADER0
ICR10
ADCS0
ADCS1
ADCR0
ADCR1
TMCSR1L
TMCSR1H
TMRL1L
TMRL1H
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
000100H
000101H
000102H
000103H
000104H
000105H
000106H
000107H
000016H
00000CH
0000BAH
000034H
000035H
000036H
000037H
000068H
000069H
003902H
003903H
;Lower buffer address pointer
;Middle buffer address pointer
;Upper buffer address pointer
;EI2OS status register
;Lower I/O address register
;Upper I/O address register
;Lower data counter
;Upper data counter
;Port direction register (for port 6)
;Analog input enable register
;Interrupt control register for ADC
;A/D control status register
;
;A/D data register
;
;Lower control status register 1
;
;16-bit reload register 1
;
;-----Main program--------------------------------------------------------------CODE
START:
AND
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVW
MOV
CSEG
;Assumes that the stack pointer (SP) has already
;been initialized
CCR,#0BFH
;Disables interrupts
ICR10,#08H
;Interrupt level: 0 (highest priority) Enables EI2OS when
;interrput
BAPL,#00H
;Sets the address to which the conversion data is stored
BAPM,#06H
;(Uses 600H to 60BH)
BAPH,#00H
;
ISCS,#18H
;Transfers word data, adds 1 to the address, then
;transfers from I/O to memory
IOAL,#36H
;Sets the address of the analog data register as the
IOAH,#00H
;transfer source address pointer
DCTL,#06H
;Six transfer by EI2OS (two transfers each for three
;channels)
DDR6,#00000000B ;Sets P60 to P67 as input
ADER0,#00111000B ;Sets P63/AN3 to P65/AN5 as analog inputx
DCTH,#00H
;
ADCS0,#9DH
;Continuous conversion mode.Converts AN3 to AN5
ADCS1,#0A8H
;Activates the 16-bit timer,starts A/D conversion,and
;enables interrupts
TMRL1L,#0320H
;Sets the timer value to 800(320H),100 s
TMCSR1H,#00H
;Sets the clock source to 125 ns and disables
;external trigger
MOV
TMCSR1L,#12H
MOV
MOV
OR
TMCSR1L,#13H
ILM,#07H
CCR,#40H
;Disables timer output,disables interruputs,and
;enables reload
;Activates the 16-bit timer
;Sets ILM in PS to level 7
;Enables interrupts
271
CHAPTER 17 8/10-BIT A/D CONVERTER
LOOP:
MOV
MOV
BRA
A,#00H
A,#01H
LOOP
;Endless loop
;-----Interrupt program---------------------------------------------------------ED_INT1:
MOV
I:ADCS1,#80H
;Does not stop A/D conversion. Clears and disables
;the interrupt flag
RETI
;Returns from interrupt
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFB4H
;Sets vector for interrupt #18 (12H)
DSL
ED_INT1
ORG
0FFDCH
;Sets reset vector
DSL
START
DB
00H
;Sets single-chip mode
VECT
ENDS
END
START
272
CHAPTER 17 8/10-BIT A/D CONVERTER
17.10
Sample Program 3 for the 8/10-Bit A/D Converter
(Stop Conversion Mode Using EI2OS)
This section contains a sample program for A/D conversion in stop conversion mode
using EI2OS.
■ Sample Program for Stop Conversion Mode Using EI2OS
● Processing
• Analog input AN3 is converted 12 times at regular intervals.
• The conversion data is sequentially transferred to addresses 600H to 617H.
• A resolution of 10 bits is selected.
• The conversion is activated by 16-bit reload timer 1 (this is possible only with MB90V390HA/HB).
Figure 17.10-1 Flowchart of Program Using EI2OS (Stop Conversion Mode)
Start conversion
AN3
Interrupt
Transfer by EI2OS
Stop
Activation by 16-bit reload timer 1
After 12 transfers
Interrupt sequence
End
273
CHAPTER 17 8/10-BIT A/D CONVERTER
● Coding example
BAPL
BAPM
BAPH
ISCS
IOAL
IOAH
DCTL
DCTH
DDR6
ADER0
ICR10
ADCS0
ADCS1
ADCR0
ADCR1
TMCSR1L
TMCSR1H
TMRL1L
TMRL1H
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
000100H
000101H
000102H
000103H
000104H
000105H
000106H
000107H
000016H
00000CH
0000BAH
000034H
000035H
000036H
000037H
000068H
000069H
003902H
003903H
;Lower buffer address pointer
;Middle buffer address pointer
;Upper buffer address pointer
;EI2OS status registerr
;Lower I/O address register
;Upper I/O address register
;Lower data counter
;Upper data counter
;Port direction register (for port 6)
;Analog input enable register
;Interrupt control register for ADC
;A/D control status register
;
;A/D data register
;
;Lower control status register 1
;
;16-bit reload register 1
;
;-----Main program--------------------------------------------------------------CODE
CSEG
START:
;Assumes that the stack pointer (SP) has already
;been initialized
AND
CCR,#0BFH
;Disables interrupts
MOV
ICR10,#08H
;Interrupt level: 0 (highest priority) + EI2OS
MOV
BAPL,#00H
;Sets the address to which conversion data is stored
MOV
BAPM,#06H
;(Uses 600H to 617H)
MOV
BAPH,#00H
;
MOV
ISCS,#19H
;Transfers word data, adds 1 to the address,
;transfers from I/O to memory, then ends by a
;resource request
MOV
IOAL,#36H
;Sets the address of the analog data register as the
MOV
IOAH,#00H
;transfer source address pointer
MOV
DCTL,#0CH
;Transfers only channel 3 twelve times by EI2OS
MOV
DDR6,#00000000B ;Sets P60 to P67 as input
MOV
ADER0,#00001000B ;Sets P63/AN3 as analog input
MOV
ADCS0,#0DBH
;Stop conversion mode. Converts AN3 CH
MOV
ADCS1,#0A8H
;Activates the 16-bit timer, starts A/D conversion,
;and enables interrupts
MOVW
TMRL1L,#0320H
;Sets the timer value to 800 (320H), 100 μs
MOV
TMCSR1H,#00H
;Sets the clock source to 125 ns and disables
;external trigger
MOV
TMCSR1L,#12H
;Disables timer output, disables interrupts, and
;enables reload
MOV
TMCSR1L,#13H
;Activates the 16-bit timer
MOV
ILM,#07H
;Sets ILM in PS to level 7
OR
CCR,#40H
;Enables interrupts
LOOP:
MOV
A,#00H
;Endless loop
MOV
A,#01H
BRA
LOOP
274
CHAPTER 17 8/10-BIT A/D CONVERTER
;-----Interrupt program---------------------------------------------------------ED_INT1:
MOV
I:ADCS1,#80H
;Does not stop A/D conversion. Clears and disables
;the interrupt flag
RETI
;Returns from interrupt
CODE
ENDS
;-----Vector setting------------------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFB4H
;Sets vector for interrupt #18 (12H)
DSL
ED_INT1
ORG
0FFDCH
;Sets reset vector
DSL
START
DB
00H
;Sets single-chip mode
VECT
ENDS
END
START
275
CHAPTER 17 8/10-BIT A/D CONVERTER
276
CHAPTER 18
UART0
This chapter explains the functions and operations of
the UART0.
18.1 Features of UART0
18.2 UART0 Block Diagram
18.3 UART0 Registers
18.4 UART0 Operation
18.5 Baud Rate
18.6 Internal and External Clock
18.7 Transfer Data Format
18.8 Parity Bit
18.9 Interrupt Generation and Flag Set Timings
18.10 UART0 Application Example
277
CHAPTER 18 UART0
18.1
Features of UART0
The UART0 is a serial I/O port for asynchronous or CLK synchronous communication.
The MB90945 series contains two UARTs, UART0 and UART3. For UART3 see
"CHAPTER 19 UART2/3".
■ Feature of UART0
UART0 has the following features.
• Full duplex double buffer
• Supports CLK synchronous and CLK asynchronous start-stop data transfer
• Multiprocessor mode support (mode 2)
• Internally dedicated baud rate generator (12 types)
• Supports flexible baud rate setting using an external clock input or internal timer
• Variable data length (7 to 9 bits, [no parity]; 6 to 8 bits [with parity])
• Error detect function (framing, overrun, and parity)
• Interrupt function (receive and transmit interrupts), Error detect function (framing, overrun, and parity)
• NRZ type transfer format
278
CHAPTER 18 UART0
18.2
UART0 Block Diagram
Figure 18.2-1 shows the block diagram of UART0.
■ UART0 Block Diagram
Figure 18.2-1 UART0 Block Diagram
CONTROL BUS
Receive interrupt
(to CPU)
Dedicated baud rate clock
SCK0
Transmit clock
16-bit reload timer 0
Clock select
circuit
Transmit interrupt
(to CPU)
Receive clock
SCK0
SIN0
Receive control circuit
Transmit control circuit
Start bit detect
circuit
Transmit start circuit
Receive bit counter
Transmit bit counter
Receive parity
counter
Transmit parity
counter
SOT0
Receive status
evaluation circuit
Transmit shifter
Receive shifter
Receive
complete
Transmit start
UIDR
UODR
Receive error
indication signal
for EI2OS (to CPU)
Data bus
UMC
register
PEN
SBL
MC1
MC0
SMDE
RFC
SCKE
SOE
USR
register
RDRF
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
URD
register
BCH
RC3
RC2
RC1
RC0
BCH0
P
D8
CONTROL BUS
Note: this diagram is valid for UART0
279
CHAPTER 18 UART0
18.3
UART0 Registers
The UART0 has the following four registers:
• Serial mode control register
• Status register
• Input data register/output data register
• Rate and data register
■ UART0 Registers
Figure 18.3-1 UART0 Registers
Serial mode control register (UMC0)
bit7
bit6
Address:
PEN
SBL
000020H
(R/W)
(0)
Status register (USR0)
bit15
Address:
000021H
RDRF
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
MC1
MC0
SMDE
RFC
SCKE
SOE
00000100B
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(W)
(1)
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ORFE
PE
TDRE
RIE
TIE
RBF
TBF
(R)
(0)
(R)
(0)
(R)
(1)
(R/W)
(0)
(R/W)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
00010000B
Input data register(UIDR0(read))/output data register (UODR0(write))
Address:
000022H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
Rate and data register (URD0)
bit15
bit14
Address:
BCH
RC3
000023H
(R/W)
(0)
R/W : Readable / writable
R : Read only
X : Undefined value
280
(R/W)
(0)
bit13
bit12
bit11
RC2
RC1
RC0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
bit10
bit9
bit8
BCH0
P
D8
(R/W)
(0)
(R/W)
(0)
(R/W)
(X)
XXXXXXXXB
0000000XB
CHAPTER 18 UART0
18.3.1
Serial Mode Control Register (UMC0)
UMC0 specifies the operation mode of UART0. Set the operation mode while operation
is halted. However, the RFC bit can be accessed during operation.
■ Serial Mode Control Register (UMC0)
Figure 18.3-2 Configuration of the Serial Mode Control Register (UMC0)
Address:
000020 H
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PEN SBL MC1 MC0
SMDE
RFC
SCKE
Initial value
00000100B
SOE
R/W R/W R/W R/W R/W W R/W R/W
SOE
Serial Output enable bit
0
Disable SOT0 pin (high Z)
1
Enable SOT0 pin (TxData)
SCKE
Serial clock output enable bit
0
External serial clock input
1
Internal serial clock output
Receiver flag clear bit
RFC
Write
Read
0
Clear RDRF, ORFE, PE
1
No effect
SMDE
0
1
Always "1"
Synchro mode enable bit
Start-Stop-CLK synchronous trnasfer
Asynchronous transfer
MC0
MC1
0
0
Mode 0: Asynchronous, 7(6) data bits
Mode control bits
1
0
Mode 1: Asynchronous, 8(7) data bits
0
1
Mode 2: Async. Multiprocessor, 8+1 data bits
1
1
Mode 3: Asynchronous, 9(8) data bits
SBL
Stop bit length bit
0
1 bit
1
2 bits
bit7
PEN
R/W
W
: Readable / writable
: Write only (read returns always "0")
: Initial value
Parity enable bit
0
Do not use parity
1
Use parity
281
CHAPTER 18 UART0
■ Serial Mode Control Register (UMC0) Contents
Table 18.3-1 Function of Each Bit of the Serial Control Register
Bit name
Function
bit7
PEN:
Parity enable bit
Specifies whether to add (for transmit) or detect (for receive) a parity bit in serial data I/O. Set to "0"
in mode 2.
0: Do not use parity
1: Use parity
bit6
SBL:
Stop bit length bit
Specifies the number of stop bits for transmit data. For receive data, the first stop bit only is
recognized and any second stop bit is ignored.
0: 1 bit length
1: 2 bits length
bit5,
bit4
MC1, MC0:
Mode control bits
Control the length of the transferred data. Table 18.4-1 lists the four transfer modes (data lengths)
selectable by these bits.
Mode
MC1
MC0
Data Length
0
0
0
7 (6)
1
0
1
8 (7)
2
1
0
8+1
3
1
1
9 (8)
The figures enclosed in parentheses indicate the data length with parity.
"+1" means Address/Data-Bit instead of parity
bit3
SMDE:
Synchro mode enable
bit
Selects the transfer method.
0:Start-stop CLK synchronous transfer (clocked synchronous transfer using start and stop bits.)
1:Start-stop CLK asynchronous transfer
bit2
RFC:
Receiver flag clear
bit
Writing "0" to this bit clears the RDRF, ORFE, and PE flags in the USR0 register. Writing "1" has
no effect. Reading always returns "1".
Note:
When receive interrupts are enabled during UART0 operation, only write "0" to RFC when
either RDRF, ORFE, or PE is "1".
bit1
SCKE:
Serial clock output
enable bit
Writing "1" to this bit in CLK synchronous mode switches the port pin to the UART0 serial clock
output pin and outputs the synchronizing clock. Set to "0" in CLK asynchronous mode or external
clock mode.
0: The pin functions as a general-purpose I/O port and does not output the serial clock. The pin
functions as the external clock input pin when the port is set to input mode (DDR=0) and RC3 to
RC0 are set to "1111B".
1: The pin functions as the UART0 serial clock output pin.
Note:
The corresponding bit of the Port Direction register should be set to "1" when the port pin is
used as the clock output.
bit0
SOE:
Serial output enable
bit
Writing "1" to this bit switches the port pin to the UART0 serial data output pin and enables serial
output.
0: The pin functions as a port pin and does not output serial data.
1: The pin functions as the UART0 serial data output pin (SOT0).
Note:
The corresponding bit of the Port Direction register should be set to "1" when the port pin is
used as the serial output.
282
CHAPTER 18 UART0
18.3.2
Status Register (USR0)
USR0 indicates the current state of the UART0 port.
■ Status Register (USR0)
Figure 18.3-3 Configuration of the Status Register (USR0)
Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
000021 H RDRF ORFE
TDRE
PE
R
R
R
RIE TIE RBF TBF
R R/W R/W R
R
Initial value
00010000B
TBF
Transmission busy flag bit
0
Transmitter idle
1
Transmitter busy
RBF
Receiver busy flag bit
0
Receiver idle
1
Receiver busy
TIE
Transmission interrupt enable bit
0
Disable interrupt
1
Enable interrupt
RIE
Reception interrupt enable bit
0
Disable interrupt
1
Enable interrupt
TDRE
Tr ansmission data register empty bit
0
Data present in UODR0
1
No data in UODR0
PE
No parity error occurred
1
Parity error occurred
ORFE
: Readable / writable
: Flag is read only, write to it has no effect
: Initial value
Overrun/Framing error bit
0
No overrun/framing error occurred
1
An overrun/framing error occurred during reception
RDRF
R/W
R
Parity error bit
0
Reception data register full bit
0
No data in UIDR0
1
Data present in UIDR0
283
CHAPTER 18 UART0
■ Status Register (USR0) Contents
Table 18.3-2 Function of Each Bit of the Status Register
Bit name
Function
bit15
RDRF:
Receiver data register
full bit
This flag indicates the state of the UIDR0 (input data register). The flag is set when the receive data
is loaded into UIDR0. Reading UIDR0 or writing "0" to RFC in the UMC0 register clears the flag. If
RIE is active, a receive interrupt request is generated when RDRF is set.
0: No data in UIDR0
1: Data present in UIDR0
bit14
ORFE:
Overrun/framing
error bit
The flag is set when an overrun or framing error occurs in receiving. Writing "0" to RFC in the
UMC0 register clears the flag. When this flag is set, the data in UIDR0 is invalid and the load from
the receive shifter to UIDR0 is not performed. If RIE is active, a receive interrupt request is
generated when ORFE is set.
0: No error
1: Error (see table below)
RDRF
0
0
1
1
ORFE
0
1
0
1
UIDR0 state
Empty
Framing error
Vaild data
Overrun error
bit13
PE:
Parity error bit
The flag is set when a receive parity error occurs. Writing "0" to RFC in the UMC0 register clears
the flag. When this flag is set, the data in UIDR0 is invalid and the load from the receive shifter to
UIDR0 is not performed. If RIE is active, a receive interrupt request is generated when PE is set.
0: No parity error
1: Parity error
bit12
TDRE:
Transmission data
register empty bit
This flag indicates the state of the UODR0 (output data register). Writing transmit data to the
UODR0 register clears the flag. The flag is set when the data is loaded to the transmit shifter and the
transmission is started. If TIE is active, a transmit interrupt request is generated when TDRE is set.
0: Data present in UODR0
1: No data in UODR0
bit11
RIE:
Reception interrupt
enable bit
Enables receive interrupt requests.
0: Disable interrupts.
1: Enable interrupts.
bit10
TIE:
Transmission
interrupt enable bit
Enables transmit interrupt requests. A transmit interrupt is generated immediately if transmit
interrupts are enabled when TDRE is "1".
0: Disable interrupts.
1: Enable interrupts.
bit9
RBF:
Receiver busy flag bit
This flag indicates that UART0 is receiving input data. The flag is set when the start bit is detected
and cleared when the stop bit is detected.
0: Receiver idle
1: Receiver busy
bit8
TBF:
Transmitter busy flag
bit
This flag indicates that UART0 is transmitting input data. The flag is set when transmit data is
written to the UODR0 register and cleared when transmission completes.
0: Transmitter idle
1: Transmitter busy
284
CHAPTER 18 UART0
18.3.3
Input Data Register (UIDR0) and Output Data Register
(UODR0)
UIDR0 (input data register) is the serial data input register. UODR0 (output data register)
is the serial data output register.
The most significant two bits (D7 and D6) are ignored if the data length is 6 bits and the
most significant bit (D7) is ignored if the data length is 7 bits. Write to UODR0 only
when TDRE = "1" in the USR0 register. Read UIDR0 only when RDRF = "1" in the USR0
register.
■ Input Data Register (UIDR0) and Output Data Register (UODR0)
Figure 18.3-4 Configuration of the Input Data Register (UIDR0) and Output Data Register (UODR0)
Address:
000022 H
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Initial value
XXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
R/W: Readable/writable
Data Registers
Read
Read from Input Data Register
Write
Write to Output Data Register
285
CHAPTER 18 UART0
18.3.4
Rate and Data Register (URD0)
URD0 selects the data transfer speed (baud rate) for UART0. The register also holds the
most significant bit (bit8) of the data when the transmit data length is 9 bits. Set the
baud rate and parity when UART0 is halted.
■ Rate and Data Register (URD0)
Figure 18.3-5 Configuration of the Rate and Data Register (URD0)
Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
000023 H BCH RC3 RC2 RC1 RC0 BCH0 P D8
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
0000000XB
D8
UIDRn/UODRn data bit 8
X
Read/write
P
Parity bit
0
Even parity
1
Odd parity
BCH0
-
Baud rate clock change bit 1
See description for details
RC3 to RC0
-
BCH
-
R/W
286
: Readable / writable
: Initial value
Rate control bit
See description for details
Baud rate clock change bit
See description for details
CHAPTER 18 UART0
■ Rate and Data Register (URD0) Contents
Table 18.3-3 Function of Each Bit of the Rate and Data Register
Bit name
bit15,
bit10
bit14 to
bit11
BCH, BCH0:
Baud rate clock
change bits
RC3 to RC0:
Rate control bit
Function
Specifies the machine cycles for the baud rate clock (see Section "18.4 UART0
Operation" for details).
BCH
BCH0
0
0
1
0
1
0
Divider
ratio
6
4
3
1
1
5
Setting example for different machine cycles
For 24 MHz: 24/6 = 4 MHz
For 16 MHz: 16/4 = 4 MHz
For 12 MHz: 12/3 = 4 MHz
For 20 MHz: 20/5 = 4 MHz;
For 10 MHz: 10/5 = 2 MHz
Selects the clock input for the UART0 port (see Section "18.4 UART0 Operation" for
details).
RC3 to
RC0
"0000"
to
"1011"
"1101"
Clock Input
"1111"
External Clock
Dedicated baud rate generator
16-bit Reload Timer 0
bit9
P:
Parity bit
Sets even or odd parity when parity is active (PEN = "1").
0: Even parity
1: Odd parity
bit8
D8:
UIDR0/UODR0
Data bit 8
Holds the bit8 of the transfer data in mode 2 or 3 (9-bit data length) and no parity.
Treated as bit8 of the UIDR0 register for reading. Treated as bit8 of the UODR0 register
for writing. The bit has no meaning in the other modes. Write to D8 only when TDRE =
"1" in the USR0 register.
287
CHAPTER 18 UART0
18.4
UART0 Operation
Table 18.4-1 lists the operating modes for UART0. Set the UMC0 register to switch
between modes.
■ UART0 Operation Modes
Table 18.4-1 UART0 Operating Modes
Mode
Parity
Data length
On
6
Off
7
On
7
Off
8
Off
8+1
On
8
Off
9
Clock mode
Length of stop bits *
0
1
2
CLK asynchronous or CLK
synchronous
1 bit or 2 bits
3
*: The number of stop bits can only be set for transmission. The number of receive stop bits is always set to one. Do not
set modes other than those listed above. UART0 does not operate if an invalid mode is set.
Note:
UART0 uses start-stop clock synchronous transfer. Therefore, a start and stop bit are added to the data
even in clock synchronous transfer.
288
CHAPTER 18 UART0
18.5
Baud Rate
When the dedicated baud rate generator is used, the following two types of baud rates
are available:
• CLK synchronous baud rate
• CLK asynchronous baud rate
■ CLK Synchronous Baud Rate
The five URD0 register bits: BCH, BCH0 and RC3, RC2, RC1 select the baud rate for CLK synchronous
transfer.
First select the machine clock divider ratio using BCH and BCH0.
BCH BCH0
0
0
→
Divide by 6 [For example, at 24 MHz: 24/6 = 4 MHz]
0
1
→
Divide by 4 [For example, at 16 MHz: 16/4 = 4 MHz]
1
0
→
Divide by 3 [For example, at 12 MHz: 12/3 = 4 MHz]
1
1
→
Divide by 5 [For example, at 20 MHz: 20/5 = 4 MHz]
Then, set the division ratio for the clock selected above in RC3, RC2, RC1, and RC0. The following three
settings are available for CLK synchronous transfer. Other settings are prohibited.
RC3
RC2
RC1
RC0
0
1
0
1
→
Divide by 2 [For example, at 4 MHz: 4/2 = 2.0 M (bps)]
0
1
1
1
→
Divide by 4 [For example, at 4 MHz: 4/4 = 1.0 M (bps)]
1
0
0
1
→
Divide by 8 [For example, at 4 MHz: 4/8 = 0.5 M (bps)]
(At 2 MHz, the speed becomes half the above examples.)
■ CLK Asynchronous Baud Rate
The six URD0 register bits: BCH, BCH0 and RC3, RC2, RC1, RC0 select the baud rate for CLK
asynchronous transfer.
First select the machine clock divider ratio using BCH and BCH0.
BCH BCH0
0
0
→
Divide by 6 [For example, at 24 MHz: 24/6 = 4 MHz]
0
1
→
Divide by 4 [For example, at 16 MHz: 16/4 = 4 MHz]
1
0
→
Divide by 3 [For example, at 12 MHz: 12/3 = 4 MHz]
1
1
→
Divide by 5 [For example, at 10 MHz: 20/5 = 2 MHz]
289
CHAPTER 18 UART0
Then, set the asynchronous transfer clock division ratio for the clock selected above in RC3, RC2, RC1,
and RC0. The following settings are available.
Baud rate =
Baud rate =
Baud rate =
Baud rate =
Φ /6
2m-1
Φ /4
2m-1
Φ /3
2m-1
Φ /5
2m-1
[bps] (machine cycle = 24 MHz)
[bps] (machine cycle = 16 MHz)
[bps] (machine cycle = 12 MHz)
[bps] (machine cycle = 20 (10) MHz)
The above 12 baud rates can be selected. The following formula shows how to calculate the CLK
synchronous baud rate.
Baud rate =
Baud rate =
Baud rate =
Baud rate =
Φ /6
2m-1
Φ /4
2m-1
Φ /3
2m-1
Φ /5
2m-1
[bps] (machine cycle = 24 MHz)
[bps] (machine cycle = 16 MHz)
[bps] (machine cycle = 12 MHz)
[bps] (machine cycle = 20 (10) MHz)
where φ is a machine cycle and m is in decimal notation for RC3 to RC1.
Note:
The above formula for m=0 or m=1 cannot be calculated.
Data transfer is possible if the CLK asynchronous baud rate is in the range -1% to +1%. The baud rate
is the CLK synchronous baud rate divided by 8 x 13, 8 x 12, or 8.
Table 18.5-1 shows examples for 24 MHz, 20 MHz, 16 MHz, and 12 MHz machine cycles. However,
do not use the settings marked as "-" in the table.
290
CHAPTER 18 UART0
Table 18.5-1 Baud Rate
CLK asynchronous (μs/Baud)
CLK synchronous (μs/Baud)
24 MHz
20 MHz
16 MHz
12 MHz
CLK
asynchronous
divider ratio
24 MHz
20 MHz
16 MHz
12 MHz
BCH/
0=00
BCH/
0=11
BCH/
0=01
BCH/
0=10
R
C
3
R
C
2
R
C
1
R
C
0
BCH/
0=00
BCH/
0=11
BCH/
0=01
BCH/
0=10
0
0
0
0
-
-
-
-
8 × 12
-
-
-
-
0
0
0
1
26/
38460
26/
38460
26/
38460
26/
38460
8 × 13
-
-
-
-
0
0
1
0
-
-
8
-
-
-
-
0
0
1
1
2/
500000
2/
500000
2/
500000
2/
500000
8
-
-
-
-
0
1
0
0
48/
20833
48/
20833
48/
20833
48/
20833
8 × 12
-
-
-
-
0
1
0
1
52/
19230
52/
19230
52/
19230
52/
19230
8 × 13
0.5 / 2M
0.5 / 2M
0.5 / 2M
0.5 / 2M
0
1
1
0
96/
10417
96/
10417
96/
10417
96/
10417
8 × 12
-
-
-
-
0
1
1
1
104/
9615
104/
9615
104/
9615
104/
9615
8 × 13
1 / 1M
1 / 1M
1 / 1M
1 / 1M
1
0
0
0
192/
5208
192/
5208
192/
5208
192/
5208
8 × 12
-
-
-
-
1
0
0
1
208/
4808
208/
4808
208/
4808
208/
4808
8 × 13
2 / 500K
2 / 500K
2 / 500K
2 / 500K
1
0
1
0
-
-
-
-
8
-
-
-
-
1
0
1
1
16/
62500
16/
62500
16/
62500
16/
62500
8
-
-
-
-
1
1
0
0
-
-
-
-
-
-
-
-
-
1
1
0
1
-
-
-
-
-
-
-
-
-
1
1
1
0
-
-
-
-
-
-
-
-
-
1
1
1
1
-
-
-
-
-
-
-
-
-
291
CHAPTER 18 UART0
18.6
Internal and External Clock
Setting RC3 to RC0 to "1101B" selects the clock signal from the 16-bit reload timer 0.
Setting RC3 to RC0 to "1111B" selects the external clock. The external clock frequency
has a maximum value of 2 MHz.
■ Internal and External Clock
The CLK asynchronous baud rate is the CLK synchronous baud rate divided by 8. Also, data transfer is
possible if the CLK asynchronous baud rate is in the range -1% to +1% of the selected baud rate. Table
18.6-1 lists the baud rates when the internal timer is selected as the clock. The values in this table are
calculated for a machine cycle of 7.3728 MHz. However, do not use the settings marked as "-" in the table.
Baud rate=
φ/X
8 × 2 (n+1)
[bps]
⎛ φ: Machine cycle
⎜
⎜ X: Divider ratio for the count clock source for
⎜
the internal timer
⎜
⎝ n: Reload value (decimal)
⎞
⎟
⎟
⎟
⎟
⎠
Table 18.6-1 Baud Rate and Reload Value
Reload value
Baud rate
X = 21
(divide machine cycle by 2)
X = 23
(divide machine cycle by 8)
76800
2
-
38400
5
-
19200
11
2
9600
23
5
4800
47
11
2400
95
23
1200
191
47
600
383
95
300
767
191
The values in the table are the reload values (decimal) for reload count operation of the 16-bit reload timer.
292
CHAPTER 18 UART0
18.7
Transfer Data Format
UART0 only handles NRZ (non-return-to-zero) type data. Figure 18.7-1 shows the
relationship between the transmit/receive clock and the data for CLK synchronous
mode.
■ Transfer Data Format
Figure 18.7-1 Transfer Data Format
SCK0
SIN0, SOT0
0
Start
1
LSB
0
1
1
0
0
1
0
MSB
1
1
⎫
Stop
Depends
D8 Stop ⎬ on the mode.
⎭
The transferred data is 01001101B (mode 1) or 101001101B (mode 3).
As shown in Figure 18.7-1, the transfer data always starts with the start bit (L level data), the specified
number of data bits are transmitted with the LSB first, then transmission ends with the stop bit ("H" level
data). Always input a clock if external clock operation is selected. When an internal clock (the dedicated
baud rate generator or 16-bit Reload Timer) is selected, the clock is output continuously. When using CLK
synchronous transfer, do not start data transfer until the selected baud rate clock has stabilized (for two
baud rate clock cycles).
When using CLK asynchronous transfer, set the SCKE bit in the UMC0 register to "0" to disable clock
output. The transfer data format of SIN0 and SOT0 is the same as shown in Figure 18.7-1.
293
CHAPTER 18 UART0
18.8
Parity Bit
The P bit in the URD0 register specifies whether to use even or odd parity when parity is
enabled. The PEN bit in the UMC0 register enables parity.
■ Parity Bit
Inputting the data shown in Figure 18.8-1 to SIN0 when even parity is set causes a receive parity error.
Figure 18.8-1 also shows the data transmitted when sending 001101B with even parity and odd parity.
Figure 18.8-1 Serial Data with Parity Enabled
SIN0
(Receive parity error occurs P = 0)
0
Start
1
LSB
0
1
1
0
0
MSB
0
1
Stop
(Parity)
SOT0
(Even parity transmission P = 0)
0
Start
1
LSB
0
1
1
0
0
MSB
1
1
Stop
(Parity)
SOT0
(Odd parity transmission P = 1)
0
Start
1
LSB
0
1
1
0
0
MSB
0
(Parity)
294
1
Stop
CHAPTER 18 UART0
18.9
Interrupt Generation and Flag Set Timings
UART0 has two interrupt causes and six flags. The two interrupt causes are the receive
and transmit interrupts. The six flags are RDRF, ORFE, PE, TDRE, RBF, and TBF. For
reception, the RDRF, ORFE, and PE flags request an interrupt. For transmission, the
TDRE flag requests an interrupt.
■ Set Timings of the Six Flags
● RDRF flag
The RDRF flag is set when receive data is loaded into the UIDR0 register. The flag is cleared by writing
"0" to RFC in the UMC0 register or by reading the UIDR0 register.
● ORFE flag
The ORFE flag is an overrun or framing error flag. The flag is set when a receive error occurs and is
cleared by writing "0" to RFC in the UMC0 register.
● PE flag
The PE flag is a reception parity error flag. The flag is set when a receive parity error occurs and is cleared
by writing "0" to RFC in the UMC0 register. Note that the parity detect function is not available in mode 2.
● TDRE flag
The TDRE flag is set when the UODR0 register becomes empty and is available for writing. The flag is
cleared by writing to the UODR0 register. The above four flags (RDRF, ORFE, PE, and TDRE) trigger
transmit or receive interrupts.
● RBF and TBF flags
The RBF and TBF flags indicate that reception or transmission is in progress. The RBF flag becomes active
during reception, and the TBF flag becomes active during transmission.
295
CHAPTER 18 UART0
18.9.1
Flag Set Timings for a Receive Operation
(Mode 0, mode 1, or mode 3)
The RDRF, ORFE, and PE flags are set and an interrupt request to the CPU generated
when the final stop bit is detected indicating the end of reception transfer. The data in
UIDR0 is invalid when either the ORFE or PE bit is active.
■ Flag Set Timings for a Receive Operation (in Mode 0, Mode 1, or Mode 3)
Figure 18.9-1, Figure 18.9-2, and Figure 18.9-3 show the set timings of the RDRF, ORFE, and PE flags
respectively.
Figure 18.9-1 RDRF Set Timing (Mode 0, Mode 1, or Mode 3)
Data
Stop
(Stop)
RDRF
Receive interrupt
Figure 18.9-2 ORFE Set Timing (Mode 0, Mode 1, or Mode 3)
Data
Stop
Data
RDRF = 1
RDRF = 0
ORFE
ORFE
Receive interrupt
Stop
Receive interrupt
(Overrun error)
(Framing error)
Figure 18.9-3 PE Set Timing (Mode 0, Mode 1, or Mode 3)
Data
PE
Receive interrupt
296
Stop
(Stop)
CHAPTER 18 UART0
18.9.2
Flag Set Timings for a Receive Operation (in Mode 2)
The RDRF flag is set when the final stop bit is detected and reception transfer ends with
the last data bit (D8) having the value "1".
The ORFE flag is set when the final stop bit is detected, irrespective of the value of the
last data bit (D8). The data in UIDR0 is invalid when the ORFE bit is active.
The interrupt request to the CPU is generated when either of the flags are set (see
Section "18.10 UART0 Application Example" for details on using mode 2).
■ Flag Set Timings for a Receive Operation (in Mode 2)
Figure 18.9-4 RDRF Set Timing (Mode 2)
Data
D6
D7
D8
Stop
(Stop)
RDRF
Receive interrupt
Figure 18.9-5 ORFE Set Timing (Mode 2)
Data
D7
D8
Stop
Data
RDRF = 1
RDRF = 0
ORFE
ORFE
Receive interrupt
D7
D8
Stop
Receive interrupt
(Overrun error)
(Framing error)
297
CHAPTER 18 UART0
18.9.3
Flag Set Timings for a Transmit Operation
TDRE is set and an interrupt request to the CPU is generated when the data written in
UODR0 register is transferred to the internal shift register and the next data can be
written to UODR0.
■ Flag Set Timings for a Transmit Operation
Figure 18.9-6 TDRE Set Timing (Mode 0)
UODR write
TDRE
Interrupt request to the CPU
Transmit interrupt
SOT0 output
ST D0 D1
ST: Start bit
298
D2 D3 D4
D5 D6 D7
D0 to D7: Data bits
SP
SP ST D0 D1
SP: Stop bit
D2 D3
CHAPTER 18 UART0
18.9.4
Status Flag During Transmit and Receive Operation
RBF is set when the start bit is detected and cleared when a stop bit is detected. The
receive data in UIDR0 at the RBF clear timing is not yet valid. The data in UIDR0
becomes valid at the RDRF set timing.
■ Status Flag during Transmit and Receive Operation
Figure 18.9-7 shows the relationship between the RBF and receive interrupt flag timing.
Figure 18.9-7 RBF Set Timing (Mode 0)
SIN0 input
ST D0 D1
D2 D3 D4
D5 D6 D7
SP
RBF
RDRF, PE, ORFE
ST: Start bit
D0 to D7: Data bits
SP: Stop bit
Writing the transmission data to UODR0 sets TBF. TBF is cleared when transmission completes.
Figure 18.9-8 TBF Set Timing (Mode 0)
UODR write
ST D0 D1
SOT0 output
D2 D3 D4
D5 D6 D7
SP
SP
TBF
ST: Start bit
D0 to D7: Data bits
SP: Stop bit
Note:
Receive operation starts after releasing a reset unless the SIN0 input pin is fixed at "1". Therefore,
before setting the mode, write "0" to RFC in the UMC0 register to clear any receive flags that have been
set.
Set the communication mode when the RBF and TBF flags in the USR0 register are "0". The data
transmitted and received during mode setting cannot be guaranteed.
■ EI2OS (Extended Intelligent I/O Service)
See the Section "3.7 Extended Intelligent I/O Service (EI2OS)" for details on EI2OS.
299
CHAPTER 18 UART0
18.10
UART0 Application Example
Mode 2 is used when a number of slave CPUs are connected to a host CPU (see Figure
18.9-7.)
■ Application Example
Figure 18.10-1 RBF Set Timing (Mode 0)
SIN0 input
ST D0 D1
D2 D3 D4
D5 D6 D7
SP
RBF
RDRF, PE, ORFE
ST: Start bit
D0 to D7: Data bits
SP: Stop bit
As shown in Figure 18.10-2, communication starts with the host CPU transmitting address data. The ninth
bit (D8) of the address data is set to "1". The address selects the slave CPU with which communication will
be established. The selected slave CPU communicates with the host CPU using a protocol determined by
the user. In normal data, D8 is set to "0". Unselected slave CPUs wait in standby until the next
communication session starts. Figure 18.10-3 shows a flowchart of operation in this mode.
Because the parity check function is not available in this mode, set the PEN bit in the UMC0 register to "0".
Figure 18.10-2 Example System Configuration Using Mode 2
SOT0
SIN0
Host CPU
300
SOT0 SIN0
SOT0 SIN0
Slave CPU #0
Slave CPU #1
CHAPTER 18 UART0
Figure 18.10-3 Communication Flowchart for Mode 2 Operation
(Host CPU)
(Slave CPU)
Start
Start
Set the transfer mode to "3"
Set the slave CPU selection
in D0 to D7. Set D8 to "1".
Transfer the byte.
Set the transfer mode to "2"
Receive a byte
No
Selected?
Set D8 to "0" and perform
communications
End
Yes
Set the transfer mode to 3
and enable SOT0 output
Perform communications
with the master CPU
Use the status flag to
confirm transfer completion,
then set the transfer mode to
2 and disable SOT0 output
301
CHAPTER 18 UART0
302
CHAPTER 19
UART2/3
This chapter explains the functions and operations of
the UART2/3.
19.1 Overview of UART2/3
19.2 Configuration of UART2/3
19.3 UART2/3 Pins
19.4 UART2/3 Registers
19.5 UART2/3 Interrupts
19.6 UART2/3 Baud Rates
19.7 Operation of UART2/3
19.8 Notes on Using UART2/3
303
CHAPTER 19 UART2/3
19.1
Overview of UART2/3
The UART2/3 with LIN (Local Interconnect Network) - Function is a general-purpose
serial data communication interface for performing synchronous or asynchronous
communication with external devices. UART2/3 provide bidirectional communication
function (normal mode), master-slave communication function (multiprocessor mode in
master/slave systems), and special features for LIN-bus systems (working both as
master or as slave device).
Please note that UART2 and UART3 are not software compatible to the UART0.
■ UART2/3 Functions
● UART2/3 functions
UART2/3 are a general-purpose serial data communication interface for transmitting serial data to and
receiving data from another CPU and peripheral devices. It has the functions listed in Table 19.1-1.
Table 19.1-1 UART2/3 Functions (1 / 2)
Item
Function
Data buffer
Full-duplex
Serial Input
The machine clock performs oversampling 5 times and the receive value is determined
by the majority decision of sampling value (asynchronous mode only)
Transfer mode
• Clock synchronous (start-stop synchronization and start-stop-bit-option)
• Clock asynchronous (using start-, stop-bits)
Baud rate
• A dedicated baud rate generator is provided, which consists of a 15-bit-reload
counter
• An external clock can be input and also be adjusted by the reload counter
Data length
• 7 bits (not in synchronous or LIN mode)
• 8 bits
Signal mode
Non-return to zero (NRZ)
Start bit timing
Clock synchronization to the falling edge of the start bit in asynchronous mode
Reception error
detection
• Framing error
• Overrun error
• Parity error (Not supported in Mode 1)
Interrupt request
• Reception interrupt (reception complete, reception error detect, LIN-Synch-break
detect)
• Transmission interrupt (transmission data empty)
• Interrupt request to ICU (LIN synch field detection: LSYN)
• Both transmission and reception support for extended intelligent
I/O service (EI2OS) and DMA function
304
CHAPTER 19 UART2/3
Table 19.1-1 UART2/3 Functions (2 / 2)
Item
Function
Master-slave communication
function
(multiprocessor mode)
One-to-n communication (one master to n slaves)
(This function is supported both for master and slave system)
Synchronous mode
Function as Master- or Slave-UART
Transceiving pins
Direct access possible
LIN bus options
•
•
•
•
•
Synchronous serial clock
The synchronous serial clock can be output continuously on the SCK pin for
synchronous communication with start & stop bits
Clock delay option
Special synchronous Clock Mode for delaying clock (useful for SPI)
Operation as master device
Operation as slave device
Generation of LIN-Sync-break
Detection of LIN-Sync-break
Detection of start/stop edges in LIN-Sync-field connected to ICU 1, 3 or 5
305
CHAPTER 19 UART2/3
■ UART2/3 Operation Modes
The UART2/3 operate in four different modes, which are determined by the MD0- and the MD1-bit of the
serial mode register (SMR2/3). Mode 0 and mode 2 are used for bidirectional serial communication, mode
1 for master/slave communication and mode 3 for LIN master/slave communication.
Table 19.1-2 UART2/3 Operation Modes
Data length
Operation mode
parity disabled
0
normal mode
1
multiprocessor
2
normal mode
3
LIN mode
parity enabled
7 or 8
-
7 or 8 + 1 *2
8
8
-
Synchronization of
mode
Length of
stop bit
data bit
direction *1
asynchronous
1 or 2
L/M
asynchronous
1 or 2
L/M
synchronous
0, 1 or 2
L/M
asynchronous
1
L
*1: means the data bit transfer format: LSB or MSB first.
*2: "+1" means the indicator bit of the address/data selection in the multiprocessor mode, instead of parity.
Note:
Mode 1 operation is supported both for master or slave operation of UART2/3 in a master-slave
connection system. In Mode 3 the UART2/3 function is locked to 8N1-Format, LSB first.
If the mode is changed, UART2/3 cuts off all possible transmission or reception and awaits then new
action.
The MD1 and MD0 bit of the Serial Mode Register (SMR2/3) determine the operation mode of UART2/3
as shown in the following table:
Table 19.1-3 Mode Bit Setting
306
MD1
MD0
Mode
Description
0
0
0
Asynchronous (normal mode)
0
1
1
Asynchronous (multiprocessor mode)
1
0
2
Synchronous (normal mode)
1
1
3
Asynchronous (LIN mode)
CHAPTER 19 UART2/3
■ UART2/3 Interrupt and EI2OS
Table 19.1-4 UART2/3 Interrupt and EI2OS
Interrupt control register
Interrupt cause
Interrupt
number
Vector table address
EI2OS
Register
name
Address
Lower
Upper
Bank
UART2
reception
interrupt
#39(27H)
ICR14
0000BEH
FFFF60H
FFFF61H
FFFF62H
*1
UART2
transmission
interrupt
#40(28H)
ICR14
0000BEH
FFFF5CH
FFFF5DH
FFFF5EH
*2
UART3
reception
interrupt
#39(27H)
ICR14
0000BEH
FFFF60H
FFFF61H
FFFF62H
*3
UART3
transmission
interrupt
#40(28H)
ICR14
0000BEH
FFFF5CH
FFFF5DH
FFFF5EH
*4
*1: EI2OS service for UART2 reception is usable only if the UART2 transmission interrupt and both of
transmission and reception interrupt for UART3 are disabled. When detecting receive errors, stop request
for EI2OS service is supported.
*2: EI2OS service for UART2 transmission is usable only if the UART2 reception interrupt and both of
transmission and reception interrupt for UART3 are disabled.
*3: EI2OS service for UART3 reception is usable only if the UART3 transmission interrupt and both of
transmission and reception interrupt for UART2 are disabled. When detecting receive errors, stop request
for EI2OS service is supported.
*4: EI2OS service for UART3 transmission is usable only if the UART3 reception interrupt and both of
transmission and reception interrupt for UART2 are disabled.
307
CHAPTER 19 UART2/3
19.2
Configuration of UART2/3
This section provides a short overview on the building blocks of UART2/3.
■ Block Diagram of UART2/3
UART2/3 consists of the following blocks:
• Reload counter
• Reception control circuit
• Reception shift register
• Reception data register (RDR2/3)
• Transmission control circuit
• Transmission shift register
• Transmission data register (TDR2/3)
• Error detection circuit
• Oversampling unit
• Interrupt generation circuit
• LIN synch break/synch field detection
• Bus idle detection circuit
• LIN-UART2/3 serial mode register (SMR2/3)
• Serial control register (SCR2/3)
• Serial status register (SSR2/3)
• Extended communication control register (ECCR2/3)
• Extended status/control register (ESCR2/3)
308
CHAPTER 19 UART2/3
Figure 19.2-1 Block Diagram of UART2/3
(OTO,
EXT,
REST)
Machine clock
PE
ORE FRE
TIE
RIE
LBIE
LBD
transmission clock
Reload
Counter
SCK2/3
TRANSMISSION
CONTROL
CIRCUIT
RECEPTION
CONTROL
CIRCUIT
Pin
RBI
TBI
Start bit
Detection
circuit
Transmission
Start circuit
Received
Bit counter
Transmission
Bit counter
Received
Parity counter
Transmission
Parity counter
Restart Reception
Reload Counter
SIN2/3
Interrupt
Generation
circuit
reception clock
Pin
reception
IRQ
transmisson
IRQ
TDRE
SOT2/3
Oversampling
Unit
Pin
RDRF
reception
complete
SOT2/3
SIN2/3
Signal
to ICU
LIN synch
break detection
circuitand
synch field
SIN2/3
Reception
shift register
Transmission
shift register
LIN synch
break
generation
circuit
transmission
start
Bus idle
Detection
circuit
Error
Detection
RDR2/3
PE
ORE
FRE
To EI 2OS
LBR
LBL1
LBL0
TDR2/3
RBI
LBD
TBI
Internal data bus
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
SSR2/3
register
MD1
MD0
OTO
EXT
REST
UPCL
SCKE
SOE
SMR2/3
register
PEN
P
SBL
CL
A/D
CRE
RXE
TXE
SCR2/3
register
LBIE
LBD
LBL1
LBL0
SOPE
SIOP
CCO
SCES
LBR
MS
ESCR2/3 SCDE
register
SSM
ECCR2/3
register
RBI
TBI
309
CHAPTER 19 UART2/3
■ Explanation of the Different Blocks
● Reload counter
The reload counter functions as the dedicated baud rate generator. It can select external input clock or
internal clock for the transmitting and receiving clocks. The reload counter has a 15 bit register for the
reload value. The actual count of the transmission reload counter can be read via the BGR02/BGR12,
respectively BGR03/BGR13.
● Reception control circuit
The reception control circuit consists of a received bit counter, start bit detection circuit, and received
parity counter. The received bit counter counts reception data bits. When reception of one data item for the
specified data length is complete, the received bit counter sets the reception data register full flag in the
serial status register. The start bit detection circuit detects start bits from the serial input signal and sends a
signal to the reload counter to synchronize it to the falling edge of these start bits. The reception parity
counter calculates the parity of the reception data.
● Reception shift register
The reception shift register fetches reception data input from the SIN2/3 pin, shifting the data bit by bit.
When reception is complete, the reception shift register transfers receive data to the RDR2/3 register.
● Reception data register (RDR2/3)
This register retains reception data. Serial input data is converted and stored in this register.
● Transmission control circuit
The transmission control circuit consists of a transmission bit counter, transmission start circuit, and
transmission parity counter. The transmission bit counter counts transmission data bits. The transmission of
one data item of the specified data length is transmitted. When the transmission bit counter indicates the
transmission start of written data, the transmission data register full flag in the serial status register is set.
At this time, if the transmission interrupt is enabled, the transmission interrupt request is generated. The
transmission start circuit starts transmission when data is written to TDR2/3. The transmission parity
counter generates a parity bit for data to be transmitted if parity is enabled.
● Transmission shift register
The transmission shift register transfers data written to the TDR2/3 register to itself and outputs the data to
the SOT2/3 pin, shifting the data bit by bit.
● Transmission data register (TDR2/3)
This register sets transmission data. Data written to this register is converted to serial data and output.
● Error detection circuit
The error detection circuit checks if there was any error during the last reception. If an error has occurred it
sets the corresponding error flags.
310
CHAPTER 19 UART2/3
● Oversampling unit
The oversampling unit oversamples the incoming data at the SIN2/3 pin for five times with the machine
clock. It is not operated in synchronous operation mode.
● Interrupt generation circuit
The interrupt generation circuit administers all cases of generating a reception or transmission interrupt. If a
corresponding enable flag is set and an interrupt case occurs the interrupt will be generated immediately.
● LIN synch break and synch field detection circuit
The LIN synch break and LIN synchronization field detection circuit detects a LIN synch break, if a LIN
master node is sending a message header. If a LIN synch break is detected a special flag bit is generated.
The first and the fifth falling edge of the LIN synchronization field is recognized by this circuit by
generating an internal signal (LSYN) for the input capture unit to measure the actual serial clock time of
the transmitting master node.
● LIN synch break generation circuit
The LIN synch break generation circuit generates a LIN synch break of a determined length.
● Bus idle detection circuit
The bus idle detection circuit recognizes if neither reception nor transmission is going on. In this case, the
circuit generates the special flag bits TBI and RBI.
● LIN-UART2/3 serial mode register (SMR2/3)
This register performs the following operations:
• Selecting the LIN-UART2/3 operation mode
• Selecting a clock input source
• Selecting if an external clock is connected "one-to-one" or connected to the reload counter
• Resetting dedicated reload timer
• Resetting the LIN-UART2/3 (preserving the settings of the registers)
• Specifying whether to enable serial data output to the corresponding pin
• Specifying whether to enable clock output to the corresponding pin
311
CHAPTER 19 UART2/3
● Serial control register (SCR2/3)
This register performs the following operations:
• Specifying whether to provide parity bits
• Selecting parity bits
• Specifying a stop bit length
• Specifying a data length
• Selecting a frame data format in mode 1
• Clearing the error flags
• Specifying whether to enable transmission
• Specifying whether to enable reception
● Serial status register (SSR2/3)
This register performs the following functions
• Indicating status of receive/transmit operations and errors
• Specifying LSB first or MSB first
• Receive interrupt enable/disable
• Transmit interrupt enable/disable
● Extended communication control register (ECCR2/3)
This register performs the following functions
• Indicating bus idle state
• Specifying synchronous clock
• Specifying LIN synch break generation
● Extended status/control register (ESCR2/3)
This register performs the following functions
• LIN synch break interrupt enable/disable
• Indicating LIN synch break detection
• Specifying LIN synch break length
• Directly accessing SIN2/3 and SOT2/3 pins
• Specifying continuous clock output operation
• Specifying sampling clock edge
312
CHAPTER 19 UART2/3
19.3
UART2/3 Pins
This section describes the UART2/3 pins and provides a pin block diagram.
■ UART2/3 Pins
The UART2/3 pins also serve as general ports. Table 19.3-1 lists the pin functions, I/O formats, and
settings required to use UART2/3.
Table 19.3-1 UART2/3 Pins
Pin name
P90/SIN2
P91/SCK2
Pin function
Pull-up
Standby
control
Port I/O or serial
data input
Port I/O or serial
clock input/output
P93/SIN3
Port I/O or serial
data input
P95/SOT3
Port I/O or serial
data output
Port I/O or serial
clock input/output
Setting required to use pin
Set as an input port
(DDR9:D90 = 0)
Set as an input port when a
clock is input
(DDR9:D91 = 0)
Port I/O or serial
data output
P92/SOT2
P94/SCK3
I/O format
Set to output enable mode
when a clock is output
(SMR2:SCKE = 1)
CMOS output
and selectable
Automotive/
CMOS
Hysteresis input
Set to output enable mode
(SMR2:SOE = 1)
Not selectable
Provided
Set as an input port
(DDR9:D93 = 0)
Set to output enable mode
(SMR3:SOE = 1)
Set as an input port when a
clock is input
(DDR9:D94 = 0)
Set to output enable mode
when a clock is output
(SMR3:SCKE = 1)
313
CHAPTER 19 UART2/3
Figure 19.3-1 Block Diagram of UART2/3 Pins
Resource input (*)
Port data register (PDR)
Resource output
Internal data bus
Resource output enable
PDR read
Output latch
Pch
PDR write
Pin
Port direction register (DDR)
Direction latch
Nch
DDR write
Standby control (SPL=1)
DDR read
Standby control: Stop mode, watch mode, timebase timer mode, and SPL=1
*: Resources are input or output to or from pins having peripheral functions.
314
General purpose I/O /SIN2/3
General purpose I/O /SCK2/3
General purpose I/O /SOT2/3
CHAPTER 19 UART2/3
19.4
UART2/3 Registers
The following figure shows the UART2/3 registers.
■ UART2/3 Registers
Figure 19.4-1 UART2/3 Registers
Address :
bit 15
003519H, 003518H
SCR3 (Serial control register)
bit 8 bit 7
bit 0
SMR3 (Serial mode register)
00351BH, 00351AH SSR3 (Serial status register)
RDR3/TDR3 (Rx, Tx data register)
00351DH, 00351CH ESCR3 (Extended status/control register)
ECCR3 (Extended communication control register)
00351FH, 00351EH BGR13 (Baud rate generator register13)
BGR03 (Baud rate generator register 03)
0035D9H, 0035D8H SCR2 (Serial control register)
SMR2 (Serial mode register)
0035DBH, 0035DAH SSR2 (Serial status register)
RDR2/TDR2 (Rx, Tx data register)
0035DDH, 0035DCH ESCR2 (Extended status/control register)
ECCR2 (Extended communication control register)
0035DFH, 0035DEH BGR12 (Baud rate generator register12)
BGR02 (Baud rate generator register 02)
315
CHAPTER 19 UART2/3
19.4.1
Serial Control Register (SCR2/3)
These registers specify parity bits, select the stop bit and data lengths, select a frame
data format in mode 1, clear the reception error flag, and specify whether to enable
transmission and reception.
■ Serial Control Register (SCR2/3)
Figure 19.4-2 Configuration of the Serial Control Register (SCR2/3)
Address:
SCR3: 003519H
SCR2: 0035D9H
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
PEN
P
SBL CL
Initial value
00000000B
A/D CRE RXE TXE
R/W R/W R/W R/W R/W W R/W R/W
TXE
Transmission enable bit
0
Disable Tr ansmission
1
Enable Tr ansmission
RXE
Reception enable bit
0
Disable Reception
1
Enable Reception
Clear reception errors flag bit
CRE
Write
Read
0
Ignored
1
Clear all reception
errors (PE, FRE, ORE)
A/D
Address / data selection bit
0
Data bit
1
Address bit
CL
Character (data frame) length selection bit
0
7 bits
1
8 bits
SBL
Stop bit length selection bit
0
1 stop bit
1
2 stop bits
P
Parity setting bit
0
Even Parity enabled
1
Odd Parity enabled
PEN
R/W
W
316
: Readable / writable
: Write only
: Initial value
Read always returns "0"
Parity enable bit
0
Parity disabled
1
Parity enabled
CHAPTER 19 UART2/3
Table 19.4-1 Functions of Each Bit of Control Register (SCR2/3)
Bit name
Function
bit15
PEN:
Parity enable bit
This bit selects whether to add a parity bit during transmission or detect it during
reception.
Parity is only provided in mode 0 and in mode 2 if SSM of the ECCR2/3 is selected.
This bit is fixed to "0" (no parity) in mode 1 and 3 (LIN).
bit14
P:
Parity selection bit
When parity is provided and enabled this bit selects even (0) or odd (1) parity
bit13
SBL:
Stop bit length
selection bit
This bit selects the length of the stop bit of an asynchronous data frame or a
synchronous frame if SSM of the ECCR2/3 is selected. This bit is fixed to "0" (1 stop
bit) in mode 3 (LIN).
Note:
The bit length of the stop bit is detected whenever it is received.
bit12
CL:
Data length selection
bit
This bit specifies the length of transmission or reception data. This bit is fixed to "1" (8
bits) in mode 2 and 3.
bit11
A/D:
Address/Data
selection bit
This bit specifies the data format in multiprocessor mode 1. Writing to this bit is
provided for a master CPU, reading from it for slave CPU. A "1" indicates an address
frame, a "0" indicates a usual data frame.
Note:
Please read the hints about using this bit in Section "19.8 Notes on Using UART2/
3".
bit10
CRE:
Clear reception error
flags bit
This bit clears the FRE, ORE, and PE flag of the Serial Status Register (SSR2/3).
Writing a "1" to it clears the error flag.
Writing a "0" has no effect.
Reading from it always returns "0".
Note:
Clear reception error flags after disabling the receive operation (RXE=0).
bit9
RXE:
Reception enable bit
This bit enables/disables LIN-UART2/3 reception.
If this bit is set to "0", UART2/3 disables the reception of data frames.
If this bit is set to "1", UART2/3 enables the reception of data frames.
The LIN synch break detection in mode 3 remains unaffected.
Note:
If reception is disabled (RXE=0) during receiving, it is stopped immediately. In this
case, data is not guaranteed.
bit8
TXE:
Transmission enable
bit
This bit enables/disables LIN-UART2/3 transmission.
If this bit is set to "0", UART2/3 disables the transmission of data frames.
If this bit is set to "1", UART2/3 enables the transmission of data frames.
Note:
If transmission is disabled (TXE=0) during transmitting, it is stopped immediately.
In this case, data is not guaranteed.
317
CHAPTER 19 UART2/3
19.4.2
Serial Mode Register (SMR2/3)
These registers select an operation mode and baud rate clock and specify whether to
enable output of serial data and clocks to the corresponding pin.
■ Serial Mode Register (SMR2/3)
Figure 19.4-3 Configuration of the Serial Mode Register (SMR2/3)
Address:
SMR3: 003518H
SMR2: 0035D8H
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
MD1 MD0 OTO EXT
REST UPCL SCKE
R/W R/W R/W R/W W
SOE
Initial value
00000000B
W R/W R/W
SOE
Serial data output enable bit of LIN-UART
0
General purpose I/O port
1
LIN-UART serial data output pin
SCKE
Serial clock output enable bit of LIN-UART
0
General purpose I/O port or LIN-UART clock input pin
1
Serial clock output pin of LIN-UART
UPCL
LIN-UART programmable clear bit (software reset)
Write
Read
0
Ignored
1
Reset UART
Always "0"
Restart dedicated reload counter bit
REST
Write
Ignored
1
Restart counter
EXT
318
: Readable / writable
: Write only
: Initial value
Always "0"
External serial slock source enable bit
0
Use internal baud rate generator (reload counter)
1
Use external serial clock source
OTO
R/W
W
Read
0
One-to-one external clock Input enable bit
0
Use external clock with baud rate generator (reload counter)
1
Use external clock as is
MD1
MD0
0
0
Mode 0: Asynchronous normal
Operation mode setting bit
0
1
Mode 1: Asynchronous multiprocessor
1
0
Mode 2: Synchronous
1
1
Mode 3: Asynchronous LIN
CHAPTER 19 UART2/3
Table 19.4-2 Bit Function of the Serial Mode Register (SMR2/3)
Bit name
Function
bit7,
bit6
MD1, MD0:
Operation mode
selection bits
These two bits set the UART2/3 operation mode.
bit5
OTO:
One-to-one external
clock selection bit
This bit sets an external clock directly to the LIN-UART2/3’s serial clock. This function
is used for operating mode 2 (synchronous) slave mode operation.
The OTO-Bit is only settable if the EXT-Bit (bit4) is also set.
bit4
EXT:
External clock
selection bit
This bit executes internal or external clock source for the reload counter
bit3
REST:
Restart of
transmission reload
counter bit
If a "1" is written to this bit the reload counter is restarted. Writing "0" to it has no
effect. Reading from this bit always returns "0".
bit2
UPCL:
UART2/3
programmable clear
bit (Software reset)
Writing a "1" to this bit resets LIN-UART2/3 immediately. The register settings are
preserved. Possible reception or transmission will cut off.
All flags (TDRE, RDRF, LBD, PE, ORE, FRE) are cleared and the Reception Data
Register (RDR2/3) contains 00H. Writing "0" to this bit has no effect. Reading from it
always returns "0".
LIN-UART2/3 reset should be performed after disabling the interrupt enable bits.
bit1
SCKE:
Serial clock output
enable bit
This bit controls the serial clock I/O ports.
• When this bit is "0", SCK2/3 pin operate as general purpose I/O port or serial clock
input pin. When this bit is "1", the pin operates as serial clock output pin and outputs
clock in operating mode 2 (synchronous). SCKE bit is fixed to 0 for MS=1.
Note:
When using SCK2/3 pin as serial clock input (SCKE=0) pin, set the corresponding
bit of DDR as input port. Also, select external clock (EXT = 1) using the external
clock selection bit.
Reference:
When the SCK2/3 pin is assigned to serial clock output (SCKE=1), it functions as
the serial clock output pin regardless of the status of the general purpose I/O ports.
bit0
SOE:
Serial data output
enable bit
This bit enables or disables the output of serial data.
• When this bit is "0", SOT2/3 pin operates as general purpose I/O pin. When this bit
is "1", SOT2/3 pin operates as serial data output pins (SOT2/3).
Reference:
When the output of serial data is enabled (SOE=1), SOT2/3 pin functions as serial
data output pin (SOT2/3) regardless of the status of general input-output ports.
319
CHAPTER 19 UART2/3
19.4.3
Serial Status Register (SSR2/3)
These registers check the transmission and reception status and error status, and
enable and disable the transmission and reception interrupts.
■ Serial Status Register (SSR2/3)
Figure 19.4-4 Configuration of the Serial Status Register (SSR2/3)
Address:
SSR3: 00351BH
SSR2: 0035DBH
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
PE ORE FRE
R
R
R
RDRF TDRE
R
BDS RIE TIE
Initial value
00001000B
R R/W R/W R/W
TIE
Disables Tr ansmission Interrupt
1
Enables Tr ansmission Interrupt
RIE
Disables Reception Interrupt
1
Enables Reception Interrupt
Send / receive LSB first
1
Send / receive MSB first
Transmission data register empty bit
0
Transmission data register is full
1
Transmission data register is empty
RDRF
Reception data register full bit
0
Reception data register is empty
1
Reception data register is full
FRE
Framing error bit
0
No framing error occurred
1
A framing error occurred during reception
ORE
Overrun error bit
0
No overrun error occurred
1
An overrun error occurred during reception
PE
320
Bit direction setting bit
0
TDRE
: Readable / writable
: Flag is read only, write to it has no effect
: Initial value
Reception Interrupt enable bit
0
BDS
R/W
R
Transmission Interrupt enable bit
0
Parity error bit
0
No parity error occurred
1
A parity error occurred during reception
CHAPTER 19 UART2/3
Table 19.4-3 Functions of Each Bit of Status Register (SSR2/3)
Bit name
Function
bit15
PE:
Parity error flag
bit
This bit is set to "1" when a parity error occurs during reception at PEN=1 and is cleared
when "1" is written to the CRE bit of the serial mode register (SCR2/3).
• A reception interrupt request is output when this bit and the RIE bit are "1".
• Data in the reception data register (RDR2/3) is invalid when this flag is set.
bit14
ORE:
Overrun error
flag bit
This bit is set to "1" when an overrun error occurs during reception and is cleared when "0"
is written to the CRE bit of the serial mode register (SCR2/3).
• A reception interrupt request is output when this bit and the RIE bit are "1".
• Data in the reception data register (RDR2/3) is invalid when this flag is set.
bit13
FRE:
Framing error
flag bit
This bit is set to "1" when a framing error occurs during reception and is cleared when "0"
is written to the CRE bit of the serial mode register 1 (SCR2/3).
• A reception interrupt request is output when this bit and the RIE bit are "1".
• Data in the reception data register (RDR2/3) is invalid when this flag is set.
Note:
When framing error is detected by the first or the second bit of the stop bit at SBL=1,
this bit is set to "1" as for either stop bit.
Thus, it is necessary to determine whether the receive data is enabled by the second bit
of the stop bit.
bit12
RDRF:
Receive data full
flag bit
This flag indicates the status of the reception data register (RDR2/3).
• This bit is set to "1" when reception data is loaded into RDR2/3 and can only be cleared
to "0" when the reception data register (RDR2/3) is read.
• A reception interrupt request is output when this bit and the RIE bit are "1".
bit11
TDRE:
Transmission
data empty flag
bit
This flag indicates the status of the transmission data register (TDR2/3).
• This bit is cleared to "0" when transmission data is written to TDR2/3 and is set to "1"
when data is loaded into the transmission shift register and transmission starts.
• A transmission interrupt request is generated if both this bit and the TIE bit are "1".
• If the LBR bit in the ECCR2/3 register is set to "1" while the TDRE bit is "1", then this
bit once changes to "0". When effective data to TDR2/3 doesn't exist after the
completion of LIN synch break generator, the TDRE bit returns to "1".
Note:
This bit is set to "1" (TDR2/3 empty) as its initial value.
bit10
BDS:
Transfer
direction
selection bit
This bit selects whether to transfer serial data from the least significant bit (LSB first,
BDS=0) or the most significant bit (MSB first, BDS=1).
This bit is fixed to "0" at mode 3.
Note:
When the BDS bit is rewritten after the receive data writing to receive data register
(RDR2/3) because an upper side and lower side are replaced at the time of writing
receive data to the receive data register (RDR2/3), the data of RDR2/3 becomes invalid.
bit9
RIE:
Reception
interrupt request
enable bit
This bit enables/disables the reception interrupt. If any of the RDRF, PE, ORE and FRE bits
is set and this bit is "1", then a reception interrupt is signaled to the interrupt controller.
bit8
TIE:
Transmission
interrupt request
enable bit
This bit enables or disables the transmission interrupt.
• A transmission interrupt request is output when this bit and the TDRE bit are "1".
321
CHAPTER 19 UART2/3
19.4.4
Reception and Transmission Data Register
(RDR2/3 and TDR2/3)
The reception data register (RDR2/3) holds the received data. The transmission data
register (TDR2/3) holds the transmission data. Both RDR2/3 and TDR2/3 registers are
located at the same address.
■ Bit Configuration of Reception and Transmission Data Registers (RDR2/3 and TDR2/3)
Figure 19.4-5 Transmission and Reception Data Registers (RDR2/3 and TDR2/3)
Address:
RDR3/TDR3: 00351AH
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Initial value
00000000B [RDR3]
11111111B [TDR3]
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
Data Registers
Read
Read from Reception Data Register
Write
Write to Tr ansmission Data Register
R/W: Readable / writable
■ Reception Data Register (RDR2/3)
RDR2/3 is the register that contains reception data. The serial data signal transmitted to the SIN2/3 pin is
converted in the shift register and stored there. When the data length is 7 bits, the uppermost bit (D7)
contains 0. When reception is complete the data is stored in this register and the reception data full flag bit
(SSR2/3:RDRF) is set to "1". If a reception interrupt request is enabled at this point, a reception interrupt
occurs.
Read RDR2/3 when the RDRF bit of the status register (SSR2/3) is "1". The RDRF bit is cleared
automatically to "0" when RDR2/3 is read. Also the reception interrupt is cleared if it is enabled and no
error has occurred.
Data in RDR2/3 is invalid when a reception error occurs (SSR2/3:PE, ORE, or FRE = 1).
322
CHAPTER 19 UART2/3
■ Transmission Data Register (TDR2/3)
When data to be transmitted is written to the transmission data register in transmission enable state, it is
transferred to the transmission shift register, then converted to serial data, and transmitted from the serial
data output terminal (SOT2/3 pin). If the data length is 7 bits, the uppermost bit (D7) is not sent.
When transmission data is written to this register, the transmission data empty flag bit (SSR2/3:TDRE) is
cleared to "0". When transfer to the transmission shift register is complete and starts, the bit is set to "1".
When the TDRE bit is "1", the next part of transmission data can be written. If output transmission interrupt
requests have been enabled, a transmission interrupt is generated. Write the next part of transmission data
when a transmission interrupt is generated or the TDRE bit is "1".
Note:
TDR2/3 is a write-only register and RDR2/3 is a read-only register. These registers are located at the
same address, so the read value is different from the write value. Therefore, instructions that perform a
read-modify-write (RMW) operation, such as the INC/DEC instruction, cannot be used.
323
CHAPTER 19 UART2/3
19.4.5
Extended Status/Control Register (ESCR2/3)
This register provides several LIN functions, direct access to the SIN2/3 and SOT2/3 pin
and setting for UART2/3 synchronous clock mode.
■ Extended Status/Control Register (ESCR2/3)
Figure 19.4-6 Configuration of the Extended Status/Control Register (ESCR2/3)
Initial value
0 0 0 0 0 X 0 0B
Address: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
ESCR3: 00351DH
LBD LBL1 LBL0 SOPE SIOP CCO SCES
ESCR2: 0035DDH LBIE
R/W R/W R/W R/W R/W R/W R/W R/W
SCES
Sampling clock edge selection bit (Mode 2)
0
Sampling on rising clock edge (normal)
1
Sampling on falling clock edge (inverted clock)
CCO
Continuous clock output bit (Mode 2)
0
Continuous Clock Output disabled
1
Continuous Clock Output enabled
Serial Input / Output Pin Access bit
SIOP
Write (if SOPE = "1")
Read
0
SOT is forced to "0"
1
SOT is forced to "1"
Reading the actual value of
SIN
SOPE
Enable serial output pin direct access bit
0
Serial output pin direct access disab le
1
Serial output pin direct access enab le
LBL1
LBL0
0
0
LIN synch break length 13 bit times
0
1
LIN synch break length 14 bit times
1
0
LIN synch break length 15 bit times
1
1
LIN synch break length 16 bit times
LIN synch break detected flag bit
LBD
0
Write
Clear LIN synch break
detected flag
1
Ignored
LBIE
R/W
X
*
324
:
:
:
:
Readable/writable
Indeterninate
Initial value
See Table 19.4-4 for RMW access
LIN synch break length select bits
Read (*)
No LIN synch break detected
LIN synch break detected
LIN synch break detection Interrupt enable bit
0
LIN synch break interrupt disable
1
LIN synch break interrupt enable
CHAPTER 19 UART2/3
Table 19.4-4 Function of Each Bit of the Extended Status/Control Register (ESCR2/3)
Bit name
Function
bit15
LBIE:
LIN synch break
detection interrupt
enable bit
This bit enables/disables LIN synch break interrupt
LIN synch break interrupt is connected to the reception interrupt. When the LBD bit is
set and this bit is "1", a reception interrupt is signaled to the interrupt controller. This bit
is fixed to "0" in operation mode 1 and mode 2.
bit14
LBD:
LIN synch break
detected flag bit
This bit goes to "1" if a LIN synch break was detected in operating mode 3.
Writing "0" to it clears this bit and the corresponding interrupt, if it is enabled.
It is recommended to write "0" to the RXE bit in the SCR2/3 register before using this
bit.
Read-modify-write instructions always return "1". Note that this does not indicate a LIN
synch break.
bit13,
bit12
LBL1, LBL0:
LIN synch break
length selection bits
These two bits determine how many serial bit times the LIN synch break is generated by
UART2/3. Receiving a LIN synch break is always fixed to 11 bit times.
bit11
SOPE:
Serial output pin direct
access enable* bit
Setting this bit to "1" enables the direct write to the SOT2/3 pin, if SOE = 1 (SMR2/3). *
bit10
SIOP:
Serial input/output pin
direct access * bit
Normal read instructions always return the actual value of the SIN2/3 pin. Writing to it
sets the bit value to the SOT2/3 pin, if SOPE = 1. During a Read-Modify-Write
instruction the bit returns the SOT2/3 value in the read cycle. *
bit9
CCO:
Continuos clock
output enable bit
This bit enables a continuos serial clock at the SCK2/3 pin if UART2/3 operates in
master mode 2 (synchronous) and the SCK2/3 pin is configured as a clock output.
Note:
When CCO bit is "1", use SSM bit of ECCR2/3 as setting to "1".
bit8
SCES:
Sampling clock edge
selection bit
This bit inverts the serial clock signal in operation mode 2 (synchronous
communication). Receiving data is sampled at the falling edge of the internal clock. If
the MS bit of the ECCR2/3 register is "0" (master mode) and the SCKE bit of the
SMR2/3 register is "1" (clock output enabled), the output clock signal is also inverted.
During operation mode 0, mode 1, mode 3, this bit is fixed to "0".
*: See Table 19.4-5.
Table 19.4-5 Description of the Interaction of SOPE and SIOP
SOPE
SIOP
Writing to SIOP
Reading from SIOP
0
R/W
Has no effect on SOT2/3, but
holds the written value
Returns current value of SIN2/3
1
R/W
Write "0" or "1" to SOT2/3
Returns current value of SIN2/3
-
RMW
Reads current value of SOT2/3 and write "0" or "1"
- : "0" or "1"
325
CHAPTER 19 UART2/3
19.4.6
Extended Communication Control Register (ECCR2/3)
The extended communication control register provides bus idle recognition interrupt
settings, synchronous clock settings, and the LIN synch break generation.
■ Extended Communication Control Register (ECCR2/3)
Figure 19.4-7 Configuration of the Extended Communication Control Register (ECCR2/3)
Address:
ECCR3: 00351CH
ECCR2: 0035DCH
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
LBR
-
MS SCDE SSM
RBI
W R/W R/W R/W R/W R
Initial value
X0000XXXB
TBI
R
Transmission bus idle flag bit
TBI *
0
Transmission is ongoing
1
No transmission activity
Reception bus idle flag bit
RBI **
0
Reception is ongoing
1
No reception activity
Unused bit
Reading value is undefined. Always write "0".
SSM
Synchronous start/stop bits in mode 2
0
No start/stop bits in synchronous mode 2
1
Enable start/stop bits in synchronous mode 2
SCDE
Serial clock delay enable bit in mode 2
0
Disable clock delay
1
Enable clock delay
MS
Master/slave mode selection bit
0
Master mode (generating serial clock)
1
Slave mode (receiving external serial clock)
Generating LIN synch break bit
LBR
Write
0
Ignored
1
Generate LIN synch break
0
R/W
R
W
X
-
326
: Readable / writable
: Read only
: Write only
: Indeterminate
: Undefined
: Initial value
Read
Always read "0"
Read value is undefined / always write 0
* : Not used in mode2 when MS = 1
** : Not used in mode2
CHAPTER 19 UART2/3
Table 19.4-6 Function of Each Bit of the Extended Communication Control Register (ECCR2/3)
Bit name
bit7
-
Function
This bit is undefined. Always write "0".
bit6
LBR:
Generating LIN
synch break bit
Writing "1" to this bit generates a LIN synch break of the length selected by the LBL0/1
bits of the ESCR2/3, if operation mode 3 is selected. Setting to "0" in operation mode 0.
bit5
MS:
Master/Slave mode
selection bit
This bit selects master or slave mode of UART2/3 in synchronous mode 2. If master is
selected, UART2/3 generates the synchronous clock by itself. If slave mode is selected,
UART2/3 receives external serial clock.
This bit is fixed to "0" in operation mode 0, mode1 and mode3.
Note:
If slave mode is selected, the clock source must be external and set to "One-to-One"
(SMR2/3: SCKE = 0, EXT = 1, OTO = 1).
bit4
SCDE:
Serial clock delay
enable bit
If this bit is set, the serial output clock is delayed as shown in Figure 19.7-4 while
UART2/3 operates in master mode 2 (the delay is one half serial clock cycle).
bit3
SSM:
Start/stop bit in mode
2
This bit adds start and stop bits to the synchronous data format in operation mode 2. It is
ignored in mode 0, mode1, and mode3.
bit2
Unused bit
Unused bit. Reading value is undefined. Always write to "0"
bit1
RBI:
Reception bus idle
flag bit
This bit is "1" if there is no reception activity on the SIN2/3 pin and it is kept at "1".
Do not use this bit in mode 2.
bit0
TBI:
Transmission bus
idle flag bit
This bit is "1" if there is no transmission activity on the SOT2/3 pin.
Do not use this bit in mode 2 when MS="1". When MS="0", this bit can be used.
327
CHAPTER 19 UART2/3
19.4.7
Baud Rate Generator Register 0/1
(BGR02/03 and BGR12/13)
The baud rate generator registers 0 and 1 (BGR02/03 and BGR12/13) set the division
ratio for the serial clock. Also the actual count of the transmission reload counter can
be read.
■ Bit Configuration of Baud Rate Generator Register (BGR02/03 and BGR12/13)
Figure 19.4-8 shows the configuration of the baud rate generator register (BGR02/03 and BGR12/13).
Figure 19.4-8 Configuration of Baud Rate Generator Register (BGR02/03 and BGR12/13)
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
00000000B
00000000B
BGR03: 00351EH
BGR13: 00351FH
BGR02: 0035DEH
BGR12: 0035DFH
Initial value
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BGR7 to 0
Write
Read
BGR14 to 8
Write
Read
Baud rate Generator Register 03
Write bit 7 to 0 of reload value to counter
Read bit 7 to 0 of transmission reload counter
Baud rate Generator Register 13
Write bit 14 to 8 of reload value to counter
Read bit 14 to 8 of transmission reload counter
Undefined bit
R/W : Readable / writable
R : Read only
Read
"0" is read.
The baud rate generator register sets the division ratio of the serial clock. The BGR12/13 and BGR02/03
correspond to the upper byte and lower byte, respectively, and writing of counter reload value and reading
of transmission reload counter value is allowed.
Also, both registers can be read or written via byte or word access.
When writing reload value other than "0" to baud rate generator register, the reload counter starts counting.
328
CHAPTER 19 UART2/3
19.5
UART2/3 Interrupts
UART2/3 uses both reception and transmission interrupts. An interrupt request can be
generated for either of the following causes:
• Receive data is set in the Reception Data Register (RDR2/3), or a reception error
occurs.
• Transmission data is transferred from the Transmission Data Register (TDR2/3) to the
transmission shift register and started.
• A LIN synch break is detected
The extended intelligent I/O service (EI2OS) is available for these interrupts.
■ LIN-UART2/3 Interrupts
Table 19.5-1 Interrupt Control Bits and Interrupt Causes of LIN-UART2/3
Reception/
transmission
/ICU
Interrupt
request
flag bit
Flag
register
Operation
mode
0
Reception
1
2
Interrupt
cause
SSR2/3
Receive data is
written to
RDR2/3
ORE
SSR2/3
Overrun error
*
PE
x
x
*
x
x
LBD
ESCR2/3
Transmission
TDRE
SSR2/3
Input capture
unit
ICP1/3/5
ICS01/
ICS23/
ICS45
x
x
ICP1/3/5
ICS01/
ICS23/
ICS45
x
x
How to clear the interrupt
request
3
RDRF
FRE
Interrupt
cause
enable bit
SSR2/3:
RIE
"1" is written to clear rec.
error bit (SCR2/3:CRE).
Framing error
x
Receive data is read.
Parity error
LIN synch
break detected
ESCR2/3:
LBIE
"0" is written to ESCR2/3:
LBD
TDR2/3 empty
SSR2/3:
TIE
Writing transmission data
and 1 writing in LIN synch
break generation bit
(ECCR2/3:LBR)
x
1st falling edge
of LIN synch
field
ICS01/
ICS23/
ICS45:
ICE1/3/5
Disable ICP1/ICP3/ICP5
temporary
x
5th falling
edge of LIN
synch field
ICS01/
ICS23/
ICS45:
ICE1/3/5
Disable ICP1/ICP3/ICP5
: Used
x : Unused
* : Only available if ECCR2/3.SSM = 1
329
CHAPTER 19 UART2/3
● Reception interrupt
If one of the following events occurs in reception mode, the corresponding flag bit of the serial status
register (SSR2/3) is set to "1":
• Data reception is complete, i. e. the received data was transferred from the received shift register to the
reception data register (RDR2/3): RDRF=1
• Overrun error, i. e. RDRF = 1 and RDR2/3 was not read by the CPU and next received data was
transferred to received data register (RDR2/3) from received shift register: ORE=1
• Framing error, i. e. a stop bit was expected, but a "0"-bit was received: FRE
• Parity error, i. e. a wrong parity bit was detected: PE
If at least one of these above flag bits go "1" and the reception interrupt is enabled (SSR2/3:RIE = 1), a
reception interrupt request is generated.
If the reception data register (RDR2/3) is read, the RDRF flag is automatically cleared to "0". Note that this
is the only way to reset the RDRF flag. The error flags are cleared to "0", if a "1" is written to the clear
reception error (CRE) flag bit of the serial control register (SCR2/3). The RDR2/3 contains only valid data
if the RDRF flag is "1" and no error bits are set.
Note, that the CRE flag is "write only" and by writing a "1" to it, it is internally held to "1" for one machine
clock cycle.
● Transmission interrupt
If transmission data is transferred from the transmission data register (TDR2/3) to the transfer shift register
and transfer is started, the transmission data register empty flag bit (TDRE) of the serial status register
(SSR2/3) is set to "1". In this case an interrupt request is generated, if the transmission interrupt enable
(TIE) bit of the SSR2/3 was set to "1" before.
As the initial value of TDRE (after hardware or software reset) is "1". So an interrupt is generated
immediately after the TIE flag is set to "1". Also note, that the only way to reset the TDRE flag is writing
data to the transmission data register (TDR2/3).
● LIN Synchronization Break Interrupt
This paragraph is only relevant, if UART2/3 operates in mode 3 as a LIN slave.
If the bus (serial input) goes "0" (dominant) for more than 11 bit times, the LIN break detected (LBD) flag
bit of the extended status/control register (ESCR2/3) is set to "1". Note, that in this case after 9 bit times the
reception error flags are set to "1", therefore the RXE flag has to be set to "0", if only a LIN synch break
detect is desired.
The interrupt and the LBD flag are cleared after writing a "1" to the LBD flag. This has to be performed
before input capture interrupt for LIN synch field.
330
CHAPTER 19 UART2/3
● LIN synch field edge detection interrupts
This paragraph is only relevant, if UART2/3 operates in mode 3 as a LIN slave. After a LIN synch break
detection, the next falling edge of the reception bus is indicated by UART2/3. Simultaneously an internal
signal connected to the ICU1/ICU3/ICU5 is set to "1". This signal is reset to "0" after the fifth falling edge
of the LIN synch field. In both cases the ICU1/3/5 generates an interrupt, if "both edge detection" and the
ICU1/ICU3/ICU5 interrupt are enabled. The difference of the ICU1/ICU3/ICU5 counter values is the serial
clock multiplied by 8. Dividing it by 8 results in the new detected and calculated baud rate for the dedicated
reload counter. This value - 1 has then to be written to the baud rate generator registers (BGR02/03 and
BGR12/13). There is no need to restart the reload counter, because it is automatically reset if a falling edge
of a start bit is detected
■ LIN-UART2/3 Interrupts and EI2OS
Table 19.5-2 UART2/3 Interrupt and EI2OS
Interrupt cause
Interrupt
number
Interrupt control register
Vector table address
EI2OS
Register name
Address
Lower
Upper
Bank
UART2
reception interrupt
#39(27H)
ICR14
0000BEH
FFFF60H
FFFF61H
FFFF62H
*1
UART2
transmission interrupt
#40(28H)
ICR14
0000BEH
FFFF5CH
FFFF5DH
FFFF5EH
*2
UART3
reception interrupt
#39(27H)
ICR14
0000BEH
FFFF60H
FFFF61H
FFFF62H
*3
UART3
transmission interrupt
#40(28H)
ICR14
0000BEH
FFFF5CH
FFFF5DH
FFFF5EH
*4
*1: EI2OS service for UART2 reception is usable only if the UART2 transmission interrupt and both of transmission and
reception interrupt for UART3 are disabled. When detecting receive errors, stop request for EI2OS service is
supported.
*2: EI2OS service for UART2 transmission is usable only if the UART2 reception interrupt and both of transmission and
reception interrupt for UART3 are disabled.
*3: EI2OS service for UART3 reception is usable only if the UART3 transmission interrupt and both of transmission and
reception interrupt for UART2 are disabled. When detecting receive errors, stop request for EI2OS service is
supported.
*4: EI2OS service for UART3 transmission is usable only if the UART3 reception interrupt and both of transmission and
reception interrupt for UART2 are disabled.
331
CHAPTER 19 UART2/3
■ UART2/3 EI2OS Functions
UART2/3 has a circuit for operating EI2OS, which can be started up for either reception or transmission
interrupts.
● For UART2 reception
UART2 shares the interrupt registers with the UART2 transmission interrupts and with UART3 reception
and transmission interrupts. Therefore, EI2OS can be started up only when no UART2 transmission
interrupts and no UART3 reception or transmission interrupts are used.
● For UART2 transmission
UART2 shares the interrupt registers with the UART2 reception interrupts and with UART3 reception and
transmission interrupts. Therefore, EI2OS can be started up only when no UART2 reception interrupts and
no UART3 reception or transmission interrupts are used.
● For UART3 reception
UART3 shares the interrupt registers with the UART3 transmission interrupts and with UART2 reception
and transmission interrupts. Therefore, EI2OS can be started up only when no UART3 transmission
interrupts and no UART2 reception or transmission interrupts are used.
● For UART3 transmission
UART3 shares the interrupt registers with the UART3 reception interrupts and with UART2 reception and
transmission interrupts. Therefore, EI2OS can be started up only when no UART3 reception interrupts and
no UART2 reception or transmission interrupts are used.
332
CHAPTER 19 UART2/3
19.5.1
Reception Interrupt Generation and Flag Set Timing
The followings are the reception interrupt causes: completion of reception (SSR2/3:
RDRF) and occurrence of a reception error (SSR2/3: PE, ORE, or FRE).
■ Reception Interrupt Generation and Flag Set Timing
Generally a reception interrupt is generated, if the received data is complete (RDRF = 1) and the reception
interrupt enable (RIE) flag bit of the serial status register (SSR2/3) was set to "1". This interrupt is
generated if the first stop bit is detected in mode 0, mode 1, mode 2 (if SSM = 1), mode 3, or the last data
bit was read in mode 2 (if SSM = 0).
Note:
If a reception error has occurred, the reception data register (RDR2/3) contains invalid data in each
mode.
Figure 19.5-1 Reception Operation and Flag Set Timing
Receive data
(mode 0/3)
ST
D0
D1
D2
....
D5
D6
D7/P
SP
ST
Receive data
(mode 1)
ST
D0
D1
D2
....
D6
D7
A/D
SP
ST
D2
....
D5
D6
D7
D0
Receive data
(mode 2)
D0
D1
D4
PE *1, FRE
RDRF
ORE *2
(if RDRF = "1")
reception interrupt occurs
*1: The PE flag will always remain "0" in mode 1 or mode 3.
*2: ORE only occurs, if the reception data is not read by the CPU (RDRF = 1) and
another data frame is read.
ST: Start bit
SP : Stop bit
A/D : Mode 1 (multi processor) address/data selection bit
Note:
The example in Figure 19.5-1 does not show all possible reception options for mode 0 and mode 3.
Here it is: "7p1" and "8N1" (p = "E" [even] or "O" [odd]).
Figure 19.5-2 ORE Set Timing
Receive
data
RDRF
ORE
333
CHAPTER 19 UART2/3
19.5.2
Transmission Interrupt Generation and Flag Set Timing
A transmission interrupt is generated when the transmission data is transferred from
transmission data register (TDR2/3) to transmission shift register and started.
■ Transmission Interrupt Generation and Flag Set Timing
A transmission interrupt is generated, when the next data to be sent is ready to be written to the
transmission data register (TDR2/3), i. e. the TDR2/3 is empty, and the transmission interrupt is enabled by
setting the transmission interrupt enable (TIE) bit of the serial status register (SSR2/3) to "1".
The transmission data register empty (TDRE) flag bit of the SSR2/3 indicates an empty TDR2/3. Because
the TDRE bit is "read only", it only can be cleared by writing data into TDR2/3.
The following figure demonstrates the transmission operation and flag set timing for the four modes of
UART2/3.
Figure 19.5-3 Transmission Operation and Flag Set Timing
Transmission interrupt occurs
Transmission interrupt occurs
Mode 0, 1, 2 (SSM=1) or 3:
Write to TDR3
TDRE
Serial output
ST D0 D1 D2 D3 D4 D5 D6 D7
P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
AD
AD
Transmission interrupt occurs
Transmission interrupt occurs
Mode 2 (SSM = 0):
Write to TDR3
TDRE
Serial output
ST: Start bit
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4
D0 ... D7: data bits
P: Parity
SP: Stop bit
AD: Address/data selection bit (mode1)
Note:
The example in Figure 19.5-3 does not show all possible transmission options for mode 0. Here it is:
"8p1" (p = "E" [even] or "O" [odd]). Parity is not provided in mode 3 or mode 2, if SSM = 0.
334
CHAPTER 19 UART2/3
■ Transmission Interrupt Request Generation Timing
If the TDRE flag is set to "1" when a transmission interrupt is enabled (SSR2/3: TIE=1), transmission
interrupt request is generated.
Note:
A transmission completion interrupt is generated immediately after the transmission interrupt is enabled
(TIE=1) because the TDRE bit is set to "1" as its initial value. TDRE is a read-only bit that can be
cleared only by writing new data to the output data register (TDR2/3). Carefully specify the
transmission interrupt enable timing.
335
CHAPTER 19 UART2/3
19.6
UART2/3 Baud Rates
One of the followings can be selected for the UART2/3 serial clock source:
• Dedicated baud rate generator (Reload Counter)
• External clock as it is (clock input to the SCK2/3 pin)
• External clock connected to the baud rate generator (Reload Counter)
■ UART2/3 Baud Rate Selection
The baud rate selection circuit is designed as shown below. One of the following three types of baud rates
can be selected:
● Baud rates determined using the dedicated baud rate generator (reload counter)
UART2/3 has two independent internal reload counters for transmission and reception serial clock. The
baud rate can be selected via the 15-bit reload value determined by the Baud Rate Generator Register 0 and
1 (BGR02/03 and BGR12/13).
The reload counter divides the machine clock by the value set in the Baud Rate Generator Register 0 and 1.
● Baud rates determined using external clock (one-to-one mode)
The clock input from UART2/3 clock pulse input pins (SCK2/3) is used as it is (synchronous). Any baud
rate less than the machine clock divided by 4 and is divisible can be set externally.
● Baud rates determined using the dedicated baud rate generator with external clock
An external clock source can also be connected internally to the reload counter. In this mode it is used
instead of the internal machine clock. This was designed to use quartz oscillators with special frequencies
and having the possibility to divide them.
336
CHAPTER 19 UART2/3
Figure 19.6-1 Baud Rate Selection Circuit (Reload Counter) for UART2/3
REST
Start bit falling
edge detected
Reload Value: v
Rxc = 0?
Reception
15-bit reload counter
set
FF
Reload
Rxc = v/2?
0
Reception
clock
reset
1
Reload Value: v
Machine clock
0
SCK2/3
(external
clock input)
EXT
Txc = 0?
Transmission
15-bit reload counter
1
Count Value: Txc
set
Txc = v/2?
OTO
FF
Reload
0
reset
1
Transmission
clock
Internal data bus
EXT
REST
OTO
SMR 2/3
register
BGR14
BGR13
BGR12
BGR11
BGR10
BGR9
BGR8
BGR12/13
register
BGR7
BGR6
BGR5
BGR4
BGR3
BGR2
BGR1
BGR0
BGR02/03
register
337
CHAPTER 19 UART2/3
19.6.1
Setting the Baud Rate
This section describes how the baud rates are set and the resulting serial clock
frequency is calculated.
■ Calculating the Baud Rate
Both 15-bit reload counters are programmed by the baud rate generator registers 0, 1 (BGR02/03 and
BGR12/13). The following formula shall be used to calculate the desired baud rate:
Reload Value:
v = [φ / b] - 1,
where φ is the machine clock, b the baud rate and [] gaussian brackets (mathematical rounding function).
● Example of calculation
If the CPU clock is 16 MHz and the desired baud rate is 19200 bps baud then the reload value v is:
v = [16 × 106 / 19200] - 1 = 832
The exact baud rate can then be recalculated: bexact = φ / (v + 1), here it is: 16 × 106 / 833 = 19207.6831
Note:
Setting the reload value to "0" stops the reload counter. For this reason the minimum division ratio is 2.
For asynchronous communication, the reload value must be greater than equal to 4 because 5 times
over-sampling is performed internally.
338
CHAPTER 19 UART2/3
■ Suggested Division Ratios for Different Machine Speeds and Baud Rates
The following settings are suggested for different MCU clock speeds and baud rates:
Table 19.6-1 Suggested Baud Rates and Reload Values at Different Machine Speeds
8 MHz
Baud
rate
Value
10 MHz
Dev.
Value
16 MHz
Dev.
Value
20 MHz
Dev.
Value
24 MHz
Dev.
Value
Dev.
4M
-
-
-
-
-
-
4
0
5
0
2M
-
-
4
0
7
0
9
0
11
0
1M
7
0
9
0
15
0
19
0
23
0
500000
15
0
19
0
31
0
39
0
47
0
460800
-
-
-
-
-
-
-
-
51
-0.16
250000
31
0
39
0
63
0
79
0
95
0
230400
-
-
-
-
-
-
-
-
103
-0.16
153600
51
-0.16
64
-0.16
103
-0.16
129
-0.16
155
-0.16
125000
63
0
79
0
127
0
159
0
191
0
115200
68
-0.64
86
0.22
138
0.08
173
0.22
207
-0.16
76800
103
-0.16
129
-0.16
207
-0.16
259
-0.16
311
-0.16
57600
138
0.08
173
0.22
277
0.08
346
-0.06
416
0.08
38400
207
-0.16
259
-0.16
416
0.08
520
0.03
624
0
28800
277
0.08
346
<0.01
554
-0.01
693
-0.06
832
-0.03
19200
416
0.08
520
0.03
832
-0.03
1041
0.03
1249
0
10417
767
<0.01
959
<0.01
1535
<0.01
1919
<0.01
2303
<0.01
9600
832
0.04
1041
0.03
1666
0.02
2083
0.03
2499
0
7200
1110
<0.01
1388
<0.01
2221
<0.01
2777
<0.01
3332
<0.01
4800
1666
0.02
2082
-0.02
3332
<0.01
4166
<0.01
4999
0
2400
3332
<0.01
4166
<0.01
6666
<0.01
8332
<0.01
9999
0
1200
6666
<0.01
8334
0.02
13332
<0.01
16666
<0.01
19999
0
600
13332
<0.01
16666
<0.01
26666
<0.01
-
-
-
-
300
26666
<0.01
-
-
-
-
-
-
-
-
Note:
Deviations are given in%.
Maximum Synchronous Baud Rate: MCU-Clock div. by 5.
339
CHAPTER 19 UART2/3
■ Using External Clock
If the EXT bit of the SMR2/3 is set, an external clock is selected, which has to be connected to the SCK2/3
pin. The external clock is used in the same way as the machine clock to the baud rate reload counter.
If One-to-one External Clock Input Mode (SMR2/3: OTO) is selected the SCK2/3 signal is directly
connected to the UART2/3 serial clock inputs. This is needed for the UART2/3 synchronous mode 2
operating as slave device.
Note, that in any case the resulting clock signal is synchronized to the machine clock in the UART2/3
module. This means that indivisible clock rates will result in phase unstable signals.
■ Counting Example
Assume the reload value is 832. The Figure 19.6-2 demonstrates the behavior of both reload counters:
Figure 19.6-2 Counting Example of the Reload Counters
Transmission/
Reception clock
Reload
count
001
000
832
831
830
829
828
827
414
413
412
411
reload count value
Transmission/
Reception clock
Reload
count
418
417
416
415
Note:
The falling edge of the Serial Clock Signal always occurs | (v + 1) / 2 | machine clock cycles after the
rising edge.
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CHAPTER 19 UART2/3
19.6.2 Restarting the Reload Counter
The Reload Counters can be restarted of the following reasons:
Transmission and reception reload counter:
• Global MCU reset
• UART2/3 programmable clear (SMR2/3:UPCL bit)
• User programmable restart (SMR2/3: REST bit)
Reception reload counter:
• Start bit falling edge detection in asynchronous mode
■ Programmable Restart
If the REST bit of the serial mode register (SMR2/3) is set by the user, both reload counters are restarted at
the next clock cycle. This feature is intended to use the transmission reload counter as a small timer.
The following figure illustrates a possible usage of this feature (assume that the reload value is 100).
Figure 19.6-3 Reload Counter Restart Example
MCU
clock
Reload
counter
clock
outputs
REST
Reload
value
37
36
35
100
99
98
97
96
95
94
93
92
91
90
89
88
87
Read
BGR03/13
Data
bus
90
: don’t care
In this example the number of MCU clock cycles (cyc) after REST is then:
cyc = v - c + 1 = 100 - 90 + 1 = 11,
where v is the reload value and c is the read counter value.
Note:
If UART2/3 is reset by setting SMR2/3:UPCL, the reload counters will also restart.
● Automatic restart
If a falling edge of a start bit is detected in asynchronous UART2/3 mode, the reception reload counter is
restarted. This is intended to synchronize the serial input shifter to the incoming serial data stream.
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CHAPTER 19 UART2/3
● Clearing reload counters
The baud rate reload/counter register (BGR12/13 and BGR02/03) and the baud rate reload counters are
cleared to "0" by the MCU global reset and the counters stop. The reload counters are cleared to "0" by
writing "1" to the UPCL bit in the SMR2/3 register. However, the value stored in the reload register is kept
unchanged and the counters start from reload value immediately. Writing "0" to the REST bit does not clear
the counters and they restart from reload value immediately.
342
CHAPTER 19 UART2/3
19.7
Operation of UART2/3
UART2/3 operates in operation mode 0 for normal bidirectional serial communication, in
mode 2 and mode 3 for bidirectional communication as master or slave, and in mode 1
as master or slave multiprocessor communication.
■ Operation of UART2/3
● Operation modes
There are four UART2/3 operation modes: modes 0 to modes 3. As listed in Table 19.7-1, an operation
mode can be selected according to the communication method.
Table 19.7-1 UART2/3 Operation Mode
Data length
Operation mode
0
Normal mode
1
Multiprocessor
2
Normal mode
3
LIN mode
Parity
disabled
Parity
enabled
7 or 8
-
7 or 8 + 1*2
8
8
-
Length
of stop
bit
Data bit
direction
Asynchronous
1 or 2
L/M
Asynchronous
1 or 2
L/M
Synchronous
0, 1 or 2
L/M
Asynchronous
1
L
Synchronization
of mode
*1
*1: means the data bit transfer format: LSB or MSB first
*2: "+1" means the indicator bit of the address/data selection in the multiprocessor mode, instead of
parity.
Note:
Mode 1 operation is supported both for master or slave operation of UART2/3 in a master-slave
connection system. In mode 3 the UART2/3 function is locked to 8N1-format, LSB first.
If the mode is changed, UART2/3 stops all transmission or reception operations and the state moves
into await state.
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CHAPTER 19 UART2/3
■ Inter-CPU Connection Method
External clock one-to-one connection (normal mode) and master-slave connection (multiprocessor mode)
can be selected. For either connection method, the data length, whether to enable parity, and the
synchronization method must be common to all CPUs. Select an operation mode as follows:
• In the one-to-one connection method, operation mode 0 or mode 2 must be used in the two CPUs. Select
operation mode 0 for asynchronous transfer mode and operation mode 2 for synchronous transfer mode.
Note, that one CPU has to set to the master and the other to the slave in synchronous mode 2.
• Select operation mode 1 for the master-slave connection method and use it either for the master or slave
system.
■ Synchronization Methods
In asynchronous operation, UART2/3 reception clock is automatically synchronized to the falling edge of a
received start bit.
• Start bit detection is edge sensitive. This means that a start bit is not detected before the next falling
edge on the serial data input SIN2/3 if SCR2/3:RXE bit is set to "1" while SIN2/3 is "0". A received
start bit is not memorized after SCR2/3:RXE bit is set to "0". This means that when SCR2/3:RXE bit is
set to "1" again, reception starts when a start bit is detected.
In synchronous mode the synchronization is performed either by the clock signal of the master device or by
UART2/3 itself if operating as master.
■ Signal Mode
UART2/3 can treat data only in non-return to zero (NRZ) format.
■ Operation Enable Bit
UART2/3 controls both transmission and reception using the operation enable bit for transmission (SCR2/
3: TXE) and reception (SCR2/3: RXE).
• If reception operation is disabled during reception (data is input to the reception shift register), finish
frame reception and read the received data of the reception data register (RDR2/3). Then, stop the
reception operation.
• If the transmission operation is disabled during transmission (data is output from the transmission shift
register), wait until there is no data in the transmission data register (TDR2/3) before stopping the
transmission operation.
344
CHAPTER 19 UART2/3
19.7.1
Operation in Asynchronous Mode (Operation Mode 0 and
Mode 1)
When UART2/3 is used in operation mode 0 (normal mode) or operation mode 1
(multiprocessor mode), the asynchronous transfer mode is selected.
■ Operation in Asynchronous Mode (Operation Mode 0 and Mode 1)
● Transfer data format
Generally each data transfer in the asynchronous mode operation begins with the start bit (low-level on
bus) and ends with at least one stop bit (high-level). The direction of the bit stream (LSB first or MSB first)
is determined by the BDS bit of the Serial Status Register (SSR2/3). The parity bit (if enabled) is always
placed between the last data bit and the (first) stop bit.
In operation mode 0, the length of the data frame can be 7 or 8 bits with or without parity and 1 or 2 stop
bits.
In operation mode 1, the length of the data frame can be 7 or 8 bits with a following address-/data-selection
bit instead of a parity bit. 1 or 2 stop bits can be selected.
The calculation formula for the bit length of a transfer frame is:
Length = 1 + d + p + s
(d = number of data bits [7 or 8], p = parity [0 or 1], s = number of stop bits [1 or 2]
Figure 19.7-1 Transfer Data Format (Operation Modes 0 and 1)
*1
*2
Operation mode 0
ST
D0
D1
D2
D3
D4
D5
D6
D7/P
SP SP
Operation mode 1
ST
D0
D1
D2
D3
D4
D5
D6
D7 A/D
SP
*1 D7 (bit 7) if parity is not provided and data length is 8 bits
P (parity) if parity is provided and data length is 7 bits
*2 only if SBL bit of SCR2/3 is set to 1
ST: Start Bit
SP: Stop Bit
A/D: Address/data selection bit in mode 1 (multiprocessor mode)
Note:
If BDS bit of the serial status register (SSR2/3) is set to "1" (MSB first), the bit stream processes as: D7,
D6, ..., D1, D0, (P).
During reception both stop bits are detected, if selected. However, the reception data register full (RDRF)
flag will go "1" at the first stop bit. The bus idle flag (RBI of ECCR2/3) goes "1" after the second stop bit if
no further start bit is detected. (The second stop bit belongs to "bus activity", although it is just mark level.)
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CHAPTER 19 UART2/3
● Transmission operation
If the transmission data register empty (TDRE) flag bit of the serial status register (SSR2/3) is "1",
transmission data is allowed to be written to the transmission data register (TDR2/3). When data is written,
the TDRE flag goes "0". If the transmission operation is enabled by the TXE-Bit ("1") of the serial control
register (SCR2/3), the data is written next to the transmission shift register and the transmission starts at the
next clock cycle of the serial clock, beginning with the start bit. Thereby the TDRE flag goes "1", so that
new data can be written to the TDR2/3.
If transmission interrupt is enabled (TIE = 1), the interrupt is generated by the TDRE flag. Note, that the
initial value of the TDRE flag is "1", so that in this case if TIE is set to "1" an interrupt will occur
immediately.
When the data length is set to 7 bits (CL=0), the unused bit of the TDR2/3 is always the MSB,
independently from the transfer direction setting in the BDS bit (LSB first or MSB first).
Note:
Because the initial value of the transmission data empty flag bit (SSR2/3: TDRE) is "1",
an interrupt generates immediately if the transmission interrupt is enabled (SSR2/3: TIE=1).
● Reception operation
Reception operation is performed when it is enabled by the reception enable (RXE) flag bit of the SCR2/3.
If a start bit is detected, a data frame is received according to the format specified by the SCR2/3. In case of
errors, the corresponding error flags are set (PE, ORE, FRE). After the reception of the data frame the data
is transferred from the serial shift register to the reception data register (RDR2/3) and the receive data
register full (RDRF) flag bit of the SSR2/3 is set. The data then has to be read by the CPU. By doing so, the
RDRF flag is cleared. If reception interrupt is enabled (RIE = 1), the interrupt is simply generated by the
RDRF.
When the data length is set to 7 bits (CL=0), the unused bit of the RDR2/3 is always the MSB,
independently from the transfer direction setting in the BDS bit (LSB first or MSB first).
Note:
Only when the RDRF flag bit is set and no errors have occurred the reception data register (RDR2/3)
contains valid data.
● Used clock
Use the internal clock or external clock. Select the baudrate generator (SMR2/3: EXT = 0 or 1, OTO = 0)
for desired baudrate.
● Stop bit, error detection, and parity:
Number of stop bit, 1 or 2 can be specified by the SBL bit of the SCR2/3 register. When receiving and 2-bit
is specified as the stop bit, the second stop bit is checked in addition to the first stop bit. The RBI (bus idle)
flag is set after the second stop bit. However the RDRF flag is set when the first stop bit is received. In
mode 0, parity error, overrun error and framing error are checked. In mode 1, parity check is not supported
and overrun error and framing error are checked. The PEN bit of the SCR2/3 register enables/disables the
parity bit and the P bit specifies even or odd parity in mode 0.
346
CHAPTER 19 UART2/3
19.7.2
Operation in Synchronous Mode (Operation Mode 2)
The clock synchronous transfer method is used for UART2/3 operation mode 2 (normal
mode).
■ Operation in Synchronous Mode (Operation Mode 2)
● Transfer data format
In the synchronous mode, 8-bit data is transferred without start or stop bits if the SSM bit of the extended
communication control register (ECCR2/3) is "0". The figure below illustrates the data format during a
transmission in the synchronous operation mode.
Figure 19.7-2 Transfer Data Format (Operation Mode 2)
Reception or transfer data
D0 D1 D2 D3 D4 D5 D6 D7
(ECCR2/3:SSM=0, SCR2/3:PEN=0)
*
ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP
Reception or transfer data
(ECCR2/3:SSM=1, SCR2/3:PEN=0)
*
ST D0 D1 D2 D3 D4 D5 D6 D7
Reception or transfer data
(ECCR2/3:SSM=1, SCR2/3:PEN=1)
P
SP SP
* only if SBL bit of SCR2/3 is set to
ST: Start bit
SP: Stop bit
P : Parity bit
● Clock inversion and start/stop bits in mode 2
If the SCES bit of the extended status/control register (ESCR2/3) is set the serial clock is inverted.
Therefore in slave mode UART2/3 samples the data bits at the falling edge of the received serial clock.
Note, that mark level becomes "0" when SCES bit is "1" in master mode. If the SSM bit of the extended
communication control register (ECCR2/3) is "1", the data format gets additional start and stop bits like in
asynchronous mode.
Figure 19.7-3 Transfer Data Format with Clock Inversion
Mark level
Reception or transmission clock
(SCES = 0, CCO = 0):
Reception or transmission clock
(SCES = 1, CCO = 0):
Data stream (SSM = 1)
(here: no parity, 1 stop bit)
Mark level
ST
SP
Data frame
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CHAPTER 19 UART2/3
● Clock supply
In operation mode 2, the number of clock cycles for the clock signal must be the same as the number of bits
for the data including start and stop bits. If the MS bit of the ECCR2/3 register is "0" (master mode) and the
SCKE bit of the SMR2/3 register is "1" (clock output enabled), the consistent clock cycles are generated
automatically. If the MS bit of the ECCR2/3 register is "1" (slave mode), make sure that correct clock
cycles are generated by the other communication device. While there is no communication, the clock signal
must be kept at "1" as the mark level.
If the SCDE bit of the ECCR2/3 register is "1", the clock output signal is delayed by the half of the serial
clock cycle as shown in Figure 19.7-4.
The operation is prepared for communication devices which use the falling edge of the serial clock signal
for the data sampling.
Figure 19.7-4 Delayed Transmitting Clock Signal(SCDE=1)
Transmission data
writing
Reception data sample edge (SCES = 0)
Transmitting or
receiving clock
(normal)
Mark level
Mark level
Transmitting
clock (SCDE = 1)
Transmission and
reception data
Mark level
0
1
1
0
LSB
1
0
0
1
MSB
Data
If the SCES bit of the ESCR2/3 register is "1", the serial clock signal is inverted. Receiving data is sampled
at the falling edge of the serial clock.
If the MS bit of the ECCR2/3 register is "0" (master mode) and the SCKE bit of the SMR2/3 register is "1"
(clock output enabled), the output clock signal is also inverted.
While there is no communication, the clock signal must be kept at "0" as the mark level.
If the CCO bit of the ESCR2/3 register is "1", the serial clock is signaled even while there is no data
communication. Therefore it is recommended to specify the start/stop bits as shown in Figure 19.7-5.
Figure 19.7-5 Continuous Clock Output in Mode 2
Reception or transmission clock
(SCES = 0, CCO = 1):
Reception or transmission clock
(SCES = 1, CCO = 1):
Data stream (SSM = 1)
(here: no parity, 1 stop bit)
ST
SP
Data frame
● Error detection
If no start/stop bits are selected (ECCR2/3: SSM = 0) only overrun errors are detected.
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CHAPTER 19 UART2/3
● Communication
For initialization of the synchronous mode, following settings have to be done:
Baud rate generator registers (BGR02/03 and BGR12/13):
Set the desired reload value for the dedicated baud rate reload counter
Serial mode control register (SMR2/3):
MD1, MD0: "10B" (Mode 2)
SCKE: "1" for the dedicated Baud Rate Reload Counter
"0" for external clock input
SOE: "1" for transmission and reception
"0" for reception only
Serial control register (SCR2/3):
RXE, TXE: set one or both of these flags to "1"
A/D: no Address/Data selection - don’t care
CL: automatically fixed to 8-bit data - don’t care
CRE: "1" to clear error flags and suspend reception
- when SSM=0 (initial value):
PEN, P, SBL: don’t care
- when SSM=1:
PEN: "1" if parity bit is added/detected, "0" if not
P: "0" for even parity, "1" odd parity
SBL: "1" for 2 stop bits, "0" for 1 stop bit
Serial status register (SSR2/3):
BDS: "0" for LSB first, "1" for MSB first
RIE: "1" if interrupts are used, "0" reception interrupts are disabled.
TIE: "1" if interrupts are used, "0" transmission interrupts are disabled
Extended communication control register (ECCR2/3):
SSM: "0" if no start/stop bits are desired (normal), "1" for adding start/stop bits (extended function)
MS: "0" for master mode (UART2/3 generates the serial clock), "1" for slave mode (UART2/3 receives
serial clock from the master device)
Initialization in synchronous slave mode:
The UART2/3 should be initialized as follows:
RXE=0, TXE=0, Do all other settings, UPCL=1, RXE=1, TXE=1
This ensures that the internal transmission and reception finite state machines are in the correct state.
349
CHAPTER 19 UART2/3
19.7.3
Operation with LIN Function (Operation Mode 3)
UART2/3 can be used either as LIN Master or LIN Slave. For this LIN function a special
mode is provided. Setting the UART2/3 to mode 3 configures the data format to 8N1LSB-first format.
■ Operation in Asynchronous LIN Mode (Operation Mode 3)
● UART2/3 as LIN master
In LIN master mode the master determines the baud rate of the whole sub bus, therefore slaves devices
have to synchronize to the master. Therefore the desired baud rate remains fixed in master operation after
initialization.
Writing "1" into the LBR bit of the extended communication control register (ECCR2/3) generates a 13 16 bit time "L" level on the SOT2/3 pin, which is the LIN synchronization break and the start of a LIN
message. Thereby the TDRE flag of the serial status register (SSR2/3) goes "0". If valid data does not exist
in the transmission data register (TDR2/3), this bit is reset to "1" after the break, and generates a
transmission interrupt for the CPU (if TIE of SSR2/3 is "1").
The length of the synchronization break to be sent can be determined by the LBL1/LBL0 bits of the
ESCR2/3 as follows:
Table 19.7-2 LIN Break Length
LBL1
LBL0
Length of Break
0
0
13 Bit times
1
0
14 Bit times
0
1
15 Bit times
1
1
16 Bit times
The synch field is sent as byte data of 0x55 after the LIN break. The 0x55 can be written to the TDR2/3 just
after writing the "1" to the LBR bit, although the TDRE flag is "0".
● UART2/3 as LIN slave
In LIN slave mode UART2/3 has to synchronize to the master’s baud rate. UART2/3 generates a reception
interrupt, when LIN synch break interrupt is enabled (LBIE=1) even if reception is disabled (RXE = 0). In
this case, when a synchronization break from the LIN master is detected, LBD bit of the ESCR2/3 is set to
"1". Writing "0" to this bit clears the reception interrupt request.
The LIN slave may need to calculate the baud rate from the synch field. In this case, the time between the
first falling edge to the fifth falling edge of the synch field is measured by the input capture module. For
this purpose, the input capture module is connected to the LIN-UART2/3 with an internal signal. This
internal signal changes from "0" to "1" at the first falling edge then "1" to "0" at the fifth falling edge.
Therefore the input capture module should be set to detect both rising and falling edge. Also the input
signal from the LIN-UART2/3 should be selected. The time measured by the input capture module
350
CHAPTER 19 UART2/3
represents 8 times of the baud rate clock cycle.
Therefore, baud rate setting value is summarized as follows:
without free run timer overflow : BGR value = {(b-a)×Fe/(8×φ)}-1
with free run timer overflow
: BGR value = {(max+b-a)×Fe/(8×φ)}-1
where max is the free run timer maximum value at the overflow occurs.
where a is the value of the ICU counter register after the first Interrupt
where b is the value of the ICU counter register after the second Interrupt
where φ is the machine clock frequency (MHz).
where Fe is the external clock frequency (MHz). When the internal baud rate generator is used
(EXT=0), it calculates as Fe=φ.
For the correspondence between other UARTs and ICUs, see "13.3 16-Bit Free Run Timer".
● LIN synch break detection interrupt and flags
If a LIN synch break is detected in the slave mode, the LIN synch break detected (LBD) flag of the ESCR2/
3 is set to "1". This causes an interrupt, if the LIN synch break interrupt enable (LBIE) bit is set.
Figure 19.7-6 LIN Synch Break Detection and Flag Set Timing.
Serial clock
0
cycle#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Serial
clock
Serial
Input
(LIN bus)
FRE
(RXE=1)
LBD
(RXE=0)
Reception interrupt occurs, if RXE=1
Reception interrupt occurs, if RXE=0
The figure above demonstrates the LIN synch break detection and flag set timing.
Note, that if reception is enabled (RXE = 1) and reception interrupt is enabled (RIE = 1), the reception data
framing error (FRE) flag bit of the SSR2/3 will cause a reception interrupt 2 bit times ("8N1") earlier than
the LIN break interrupt, so it is recommended to turn off RXE, if a LIN break is expected.
LBD is only supported in operation mode 3. Upon LIN break detection, the reception error flags (SSR2/
3:FRE, SSR2/3:ORE, SSR2/3:PE) and the reception data register full flag (SSR2/3:RDRF) are not cleared.
351
CHAPTER 19 UART2/3
Figure 19.7-7 shows a typical start of a LIN message frame and the behavior of the UART2/3.
Figure 19.7-7 UART2/3 Behavior as Slave in LIN Mode
Serial
clock
Serial
Input
(LIN bus)
LBR cleared
by CPU
LBD
Internal
ICU
Signal
Synch break (e. g. 14 Tbit)
Synch field
● LIN bus timing
Figure 19.7-8 LIN Bus Timing and UART2/3 Signals
no clock used
(calibration frame)
old serial clock
new (calibrated) serial clock
ICU count
LIN
bus
(SIN2/3)
RXE
LBD
(IRQ0)
LBIE
Internal
Signal
to ICU
IRQ from
ICU
RDRF
(IRQ0)
RIE
Read
RDR2/3
by CPU
Reception Interrupt
enable
LIN synch break begins
LIN synch break detected and Interrupt
IRQ cleared by CPU (LBD 0)
LBIE disable
IRQ from ICU
IRQ cleared: Begin of Input Capture
IRQ from ICU
IRQ cleared: Calculate & set new baud rate
Reception enable
Edge of Start bit of Identifier byte
Byte read in RDR2/3
RDR2/3 read by CPU
352
CHAPTER 19 UART2/3
19.7.4
Direct Access to Serial Pins
UART2/3 allows the user to directly access to the transmission pin (SOT2/3) or the
reception pin (SIN2/3).
■ UART2/3 Direct Pin Access
The UART2/3 provides the ability for the software to access directly to serial input or output pin. The
software can always monitor the incoming serial data by reading the SIOP bit of the ESCR2/3. If setting the
Serial Output Pin direct access Enable (SOPE) bit of the ESCR2/3 the software can force the SOT2/3 pin to
a desired value. Note, that this access is only possible, if the transmission shift register is empty (i. e. no
transmission activity).
In LIN mode, this function can be used for reading back the own transmission and is used for error
handling if something is physically wrong with the single-wire LIN-bus.
Notes:
• Write the desired value to the SIOP pin before enabling the output pin access to prevent undesired
output level because SIOP holds the last written value.
• During a Read-Modify-Write operation the SIOP bit returns the actual value of the SOT2/3 pin in the
read cycle instead of the value of SIN2/3 during a normal read instruction.
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CHAPTER 19 UART2/3
19.7.5
Bidirectional Communication Function (Normal Mode)
In operation mode 0 or mode 2, normal serial bidirectional communication is available.
Select operation mode 0 for asynchronous communication and operation mode 2 for
synchronous communication.
■ Bidirectional Communication Function
The settings shown in Figure 19.7-9 are required to operate UART2/3 in normal mode (operation mode 0
or mode 2).
Figure 19.7-9 Settings for UART2/3 Operation Mode 0 and Mode 2
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3
SCR2/3, SMR2/3 PEN
P
SBL
Mode 0→
Mode 2→
SSR2/3,
TDR2/3/RDR2/3
Mode 0→
Mode 2→
ESCR2/3,
ECCR2/3
Mode 0→
Mode 2→
×
1
0
+
354
PE
CL
A/D
+
×
×
CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
0
0
ORE FRE RDRF TDRE BDS
0
1
RIE
×
×
×
×
×
×
×
+
: Bit used
: Bit not used
: Set 1
: Set 0
: Bit used if SSM = 1 (Synchronous start- / stop-bit mode)
: Bit automatically set to correct value
0
0
0
0
0
0
0
0
0
Set conversion data (during writing)
Retain reception data (during reading)
TIE
LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES
×
×
bit2 bit1 bit0
-
LBR
0
×
MS SCDE SSM
×
×
×
-
0
0
RBI
TBI
CHAPTER 19 UART2/3
● Inter-CPU connection
As shown in Figure 19.7-10, interconnect two CPUs in UART2/3 mode 2
Figure 19.7-10 Connection Example of UART2/3 Mode 2 Bidirectional Communication
SOT
SOT
SIN
SIN
SCK
Input
Output
CPU-1 (Master)
SCK
CPU-2 (Slave)
Figure 19.7-11 Example of Bidirectional Communication Flowchart
(Transmission side)
(Reception side)
Start
Start
Operating mode setting
(either 0 or 2)
Operating mode setting
(match the transmission side)
Set 1-byte data to TDR3
and communicate
With reception data
NO
YES
With reception data
Read reception data
and process
NO
YES
Read reception data
and process
1-byte data transmission
(ANS)
355
CHAPTER 19 UART2/3
19.7.6
Master-Slave Communication Function
(Multiprocessor Mode)
UART2/3 communication with multiple CPUs connected in master-slave mode is
available for both master and slave systems.
■ Master-slave Communication Function
The settings shown in Figure 19.7-12 are required to operate UART2/3 in multiprocessor mode (operation
mode 1).
Figure 19.7-12 Settings for UART2/3 Operation Mode 1
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2
SCR2/3,
SMR2/3
Mode 1→
SSR2/3,
TDR2/3/RDR2/3
Mode 1→
ESCR2/3,
ECCR2/3
Mode 1→
×
1
0
+
PEN
P
+
×
PE
SBL
CL
A/D
bit1 bit0
CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
0
ORE FRE RDRF TDRE BDS
0
RIE
1
0
0
0
0
0
Set conversion data (during writing)
Retain reception data (during reading)
TIE
×
LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES
×
×
×
×
×
-
LBR
+
×
MS SCDE SSM
×
×
×
-
RBI
TBI
0
: Bit used
: Bit not used
: Set 1
: Set 0
: Bit automatically set to correct value
● Inter-CPU connection
As shown in Figure 19.7-13, a communication system consists of one master CPU and multiple slave CPUs
connected to two communication lines. UART2/3 can be used for the master or slave CPU.
Figure 19.7-13 Connection Example of UART2/3 Master/Slave Communication
SOT1
SIN1
Master CPU
SOT
SIN
Slave CPU #0
356
SOT
SIN
Slave CPU #1
CHAPTER 19 UART2/3
● Function selection
Select the operation mode and data transfer mode for master/slave communication as shown in Table 19.73.
Table 19.7-3 Selection of the Master/Slave Communication Function
Operation mode
Data
Master CPU
Address
transmission
and
reception
Data
transmission
and
reception
Mode 1
(transmit/
receive A/Dbit)
Parity
Synchronization
method
None
Asynchronous
Slave CPU
Mode 1
(transmit/
receive A/Dbit)
Stop
bit
A/D="1" + 7or 8-bit
address
1 or 2
bits
Bit
direction
LSB or
MSB
first
A/D="0" + 7or 8-bit data
Communication procedure
When the master CPU transmits address data, communication starts. The A/D bit in the address data is
set to "1", and the communication destination slave CPU is selected. Each slave CPU checks the
address data using a program. When the address data indicates the address assigned to a slave CPU, the
slave CPU communicates with the master CPU.
Figure 19.7-14 shows a flowchart of master/slave communication (multiprocessor mode).
357
CHAPTER 19 UART2/3
Figure 19.7-14 Master-slave Communication Flowchart
(Master CPU)
(Slave CPU)
Start
Start
Set operation mode 1
Set operation mode 1
Set SIN2/3 pin as the
serial data input pin.
Set SOT2/3 pin as the
serial data output pin.
Set SIN2/3 pin as the
serial data input pin.
Set SOT2/3 pin as the
port input pin.
Set 7 or 8 data bits.
Set 1 or 2 stop bits.
Set 7 or 8 data bits.
Set 1 or 2 stop bits.
Set “1” in AD bit
Set TXE = RXE = 1.
Set TXE = RXE = 1.
Receive Byte
Send Slave Address
Is
AD bit = 1 ?
NO
YES
Does
Slave Address
match?
Set “0” in AD bit.
NO
YES
Communicate with
slave CPU
Is
communication
complete?
Communicate with
master CPU
NO
YES
Communicate
with another
slave CPU?
YES
NO
YES
Set TXE = RXE = 0.
End
358
Is
communication
complete?
NO
CHAPTER 19 UART2/3
19.7.7
LIN Communication Function
UART2/3 communication with LIN devices is available for both LIN master and LIN slave
systems.
■ LIN-master-slave Communication Function
The settings shown in the figure below are required to operate UART2/3 in LIN communication mode
(operation mode 3).
Figure 19.7-15 Settings for UART2/3 in Operation Mode 3 (LIN)
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5
SCR2/3, SMR2/3 PEN
Mode 3→
SSR2/3,
TDR2/3/RDR2/3
Mode 3→
ESCR2/3,
ECCR2/3
Mode 3→
×
1
0
+
+
PE
P
SBL
CL
A/D
×
+
+
×
CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE
0
ORE FRE RDRF TDRE BDS
×
bit4 bit3 bit2 bit1 bit0
1
RIE
1
0
0
0
0
0
Set conversion data (during writing)
Retain reception data (during reading)
TIE
+
LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES
×
+
-
LBR
MS SCDE SSM
×
×
×
-
RBI
TBI
0
: Bit used
: Bit not used
: Set 1
: Set 0
: Bit automatically set to correct value
● LIN device connection
Figure 19.7-16 shows the communication system of one LIN master device and a LIN slave device.
UART2/3 can operate as both LIN master and LIN slave.
Figure 19.7-16 Connection Example of a Small LIN-bus System
SOT
SO
LIN bus
SIN
LIN master
SIN
Single-wiretransceiver
Single-wiretransceiver
LIN slave
359
CHAPTER 19 UART2/3
19.7.8
Sample Flowcharts for UART2/3 in LIN Communication
(Operation Mode 3)
This section contains sample flowcharts for UART2/3 in LIN communication.
■ UART2/3 as Master Device
Figure 19.7-17 UART2/3 LIN Master Flow Chart
START
Initial setting :
Set operation mode 3
Serial data output enabled
Baudrate setting
Synch break length setting
TXE=1, TIE=0
RXE=0, RIE=1
No
Send Message?
No (transmission)
Yes (reception)
Yes
Wake up?
RDRF=1
No
Data field reception?
(0x80 reception)
Reception interrupt
Yes
*1
Data 1 reception
Transmission data 1 set :
TDR2/3=Data 1
Transmission interrupt
enabled
RDRF=1
RXE=0
TDRE=1
Reception interrupt
Synch break interrupt enabled
Synch break transmission :
*1
Data N reception
Transmission interrupt
ECCR2/3 : LBR=1
Transmission data N set :
TDR2/3=Data N
Transmission interrupt
disabled
Synch field transmission :
TDR3=0x55
LBD=1
RDRF=1
Synch break interrupt
Reception interrupt
Reception enabled
LBD=0
Synch break interrupt disabled
*1
Data 1 reception
Data 1 reading
RDRF=1
RDRF=1
Reception interrupt
Reception interrupt
*1
*1
Synch field reception
Data 1 reception
Data 1 reading
Identify field set : TDR2/3=ID
RDRF=1
Reception interrupt
*1
*2
ID field reception
No
Without error
Yes
*1 :
*2 :
When errors occur, execute an error processing.
- If SSR : FRE or ORE bit is set to 1, set SCR : CRE bit to 1 in order to clear error flags.
- If ESCR : LBD bit is set to 1, execute an UART reset.
Note : In each processing, check error flags and cope suitably.
360
Error processing
CHAPTER 19 UART2/3
■ UART2/3 as Slave Device
Figure 19.7-18 UART2/3 LIN Slave Flow Chart
START
Initial setting :
Set operation mode 3
Serial data output enabled
Baudrate setting
Synch break length setting
TXE=1, TIE=0
RXE=0, RIE=1
Connection with UART and ICU
Reception prohibited
ICU interrupt enabled
Synch break interrupt enabled
Yes (reception)
LBD=1
RDRF=1
Synch break interrupt
No (transmission)
Data field
reception?
Reception interrupt
Synch break detection clear
ECCR2/3 : LBD=0
Synch break interrupt prohibited
*1
Transmission data 1 set
TDR2/3=Data 1
Transmission interrupt
enabled
Data 1 reception
RDRF=1
ICU interrupt
Reception interrupt
TDRE=1
*1
Data N reception
ICU data read
ICU interrupt flag clear
Transmission interrupt
Transmission data N set
TDR2/3=Data N
Transmission interrupt
prohibited
ICU interrupt
Reception prohibited
RDRF=1
ICU data read
Baud rate regulation
Reception enabled
ICU interrupt flag clear
ICU interrupt prohibited
Reception interrupt
*1
Data 1 reception
Data 1 read
RDRF=1
LBD=1
Reception interrupt
Synch break interrupt
*1
*1
Data N reception
Data N read
Reception prohibited
Identify field reception
*2
No
Error processing
Without error
Yes
Sleep mode?
No
Yes
Wake up reception?
No
Yes
Wake up
transmission?
*1 :
*2 :
When errors occur, execute an error processing.
- If SSR : FRE or ORE bit is set to 1, set SCR : CRE bit to 1 in order to clear error flags.
- If ESCR : LBD bit is set to 1, execute an UART reset.
Note : In each processing, check error flags and cope suitably.
No
Yes
Wake up code transmission
361
CHAPTER 19 UART2/3
19.8
Notes on Using UART2/3
Notes on using UART2/3 are given below.
■ Notes on Using UART2/3
● Enabling operations
In UART2/3, the control register (SCR2/3) has TXE (transmission) and RXE (reception) operation enable
bits. Both transmission and reception operations must be enabled before the communication starts because
they have been disabled as the default value (initial value). The operation can also be canceled by disabling
these bits.
● Communication mode setting
Set the communication mode while the system is not operating. If the mode is changed during transmission
or reception, the transmission or reception is stopped and possible data will be lost.
● Transmission interrupt enabling timing
The default (initial value) of the transmission data empty flag bit (SSR2/3: TDRE) is "1" (no transmission
data and transmission data write enable state). A transmission interrupt request is generated as soon as the
transmission interrupt request is enabled (SSR2/3: TIE=1). Be sure to set the TIE flag to "1" after setting
the transmission data to avoid an immediate interrupt.
● Start bit synchronization
In asynchronous mode, start bit detection is edge sensitive. This means that a start bit is not detected before
the next falling edge on the serial data input SIN2/3 if SCR2/3:RXE bit is set to "1" while SIN2/3 is "0".
In asynchronous mode, a received start bit is not memorized after SCR2/3:RXE bit is set to "0". This means
that when SCR2/3:RXE bit is set to "1" again, reception starts when a start bit is detected.
● Using LIN operation mode 3
The LIN features are available in mode 3 (transmitting, receiving synch break), but using mode 3 sets the
UART2/3 data format automatically to LIN format (8N1, LSB first). Note, that the length of the synch
break for transmission is variable but for reception it is fixed 11-bit time.
Note:
During LIN operation, please set SCES bit of ESCR2/3 register to "0".
● Changing operation settings
It is strongly recommended to reset UART2/3 after changing operation settings. Particularly if (for
example) start-/stop-bits added to or removed from the data format.
Note:
If settings in the serial mode register (SMR2/3) are desired, it is not useful to set the UPCL bit at the
same time to reset UART2/3. The correct operation settings are not guaranteed in this case. Thus it is
recommended to set the bits of the SMR2/3 and then to set them again plus the UPCL bit.
362
CHAPTER 19 UART2/3
● LIN slave settings
Set the baud rate before receiving the first LIN synch break for the slave operation. Otherwise, duration of
the synch break can not be correctly checked against the minimum requirement of the LIN specification (13
master bit time and 11 slave bit time).
● Software compatibility
Although this UART2/3 is similar to other UARTs in other microcontrollers, it is not software compatible
to them. The programming models may be the same, but the structure of the registers is different.
Furthermore the setting of the baud rate is now determined by a reload value instead of selecting a
predefined value.
● Bus idle function
The Bus Idle Function cannot be used in synchronous mode 2 and SSM=0.
● A/D bit (serial control register (SCR2/3): address/data type select bit)
• This bit is both a control and a flag bit, because writing to it sets the A/D bit for transmission, whereas
reading from it returns the last received A/D bit. Internally, the received and the transmitted A/D bit
values are stored in different registers.
The A/D bit of the transmission is read when the RMW system instruction is used, and the received A/D
data is read as for other reading.
• When the TDRE bit becomes "1" from "0" when the transmission operates, the A/D bit for the
transmission is loaded into the transmission shift register with the data of the transmission data register
(TDR2/3). Therefore, set the A/D bit to the A/D bit for the transmission before writing in the
transmission data register (TDR2/3).
● Software reset of UART2/3
Perform the software reset (SMR2/3: UPCL=1), when the TXE bit of the SCR2/3 register is "0".
● LIN synch field wait state
In mode 3 (LIN operation), the LBD bit in the ESCR2/3 register is set to "1" if the serial input is kept at "0"
for more than equal to 11-bit time. Then the UART2/3 waits for the following synch field to be received. If
the UART2/3 is set into this state for other reasons than the synch break, it should be initialized by the
software reset (SMR2/3:UPCL=1).
● Initialization in synchronous slave mode:
The UART2/3 should be initialized as follows:
RXE=0, TXE=0, Do all other settings, UPCL=1, RXE=1, TXE=1
This ensures that the internal transmission and reception finite state machines are in the correct state.
363
CHAPTER 19 UART2/3
364
CHAPTER 20
400 kHz I2C INTERFACE
This section explains the functions and operation of the
fast I2C interface.
20.1 I2C Interface Overview
20.2 I2C Interface Registers
20.3 I2C Interface Operation
20.4 Programming Flow Charts
365
CHAPTER 20 400 kHz I2C INTERFACE
20.1
I2C Interface Overview
The I2C interface is a serial I/O port supporting the Inter IC bus, operating as a master/
slave device on the I2C bus.
■ Features
• Master/slave transmitting and receiving functions
• Arbitration function
• Clock synchronization function
• General call addressing support
• Transfer direction detection function
• Repeated start condition generation and detection function
• Bus error detection function
• 7 bit addressing as master and slave
• 10 bit addressing as master and slave
• Possibility to give the interface a seven and a ten bit slave address
• Acknowledging upon slave address reception can be disabled (master-only operation)
• Address masking to give interface several slave addresses (in 7 and 10 bit mode)
• Up to 400 Kbytes transfer rate
• Possibility to use built-in noise filters for SDA and SCL
• Can receive data at 400 Kbytes if machine clock is higher than 6 MHz regardless of prescaler setting
• Can generate MCU interrupts on transmission and bus error events
• Supports being slowed down by a slave on bit and byte level
The I2C interface does not support SCL clock stretching on bit level since it can receive the full 400 Kbytes
data rate if the machine clock is higher than 6 MHz regardless of the prescaler setting. However, clock
stretching on byte level is performed since SCL is pulled "L" during an interrupt (INT="1" in IBCR
register).
366
CHAPTER 20 400 kHz I2C INTERFACE
Figure 20.1-1 Block Diagram
ICCR
I2C enable
EN
ICCR
Clock divider 1
2 3 4 5 ... 32
CS4
CS3
5
CS2
5
Clock selector
Sync
CS1
CS0
Clock divider 2 (by 12)
SCL duty cycle generator
Shift clock generator
IBSR
BB
Bus busy
RSC
Repeated start
LRB
Last bi t
TRX
Send/receive
Bus observer
Bus error
ADT
Address dat a
AL
Arbitration loss detector
ICCR
NSF
Internal data-bus
IBCR
enable
BER
BEIE
MCU
IRQ
Interrupt request
INTE
INT
Noise
filter
SCL
SDA
SCL
SDA
IBCR
SCC
MSS
ACK
GCAA
Start
Start-stop conditio n
generator
Master
ACK enable
ACK generator
GC-ACK enable
8
IDAR
IBSR
AAS
GCA
ISMK
ENSB
ITMK
ENTB
RAL
8
Slave
General call
enable 7 bit mode
Slave address
comparator
enable 10 bit mode
received ad. length
7
10
10
ITBA
ITMK
7
ISBA
ISMK
10
10
7
7
367
CHAPTER 20 400 kHz I2C INTERFACE
I2C Interface Registers
20.2
This section describes the function of the I2C interface registers in detail.
■ I2C Interface Registers
Figure 20.2-1 I2C Interface Registers (1/2)
Bus control register (IBCR)
Address:
0035A1H
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
BER BEIE SCC MSS ACK GCAA INTE
INT
Initial value
00000000B
R/W R/W W R/W R/W R/W R/W R/W
Bus status register (IBSR)
Address:
0035A0H
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
BB
RSC AL
LRB
TRX AAS GCA ADT
R
R
R
R
R
R
R
Initial value
00000000B
R
Ten bit slave address register (ITBA)
Address:
0035A3H
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
-
-
-
-
-
-
TA9 TA8
-
-
-
-
-
- R/W R/W
Initial value
00000000B
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Address:
0035A2 H
TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
00000000B
Ten bit slave address mask register (ITMK)
Address:
0035A5H
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
ENTB RAL -
-
-
-
TM9 TM8
R/W R/W -
-
-
- R/W R/W
Initial value
00111111B
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Address:
0035A4H
TM7 TM6 TM5 TM4 TM3 TM2 TM1 TM0
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value
11111111B
Seven bit slave address register (ISBA)
Address:
0035A6H
R/W
R
-
368
:
:
:
Readable/writable
Read only
Undefined
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
-
SA6 SA5 SA4 SA3 SA2 SA1 SA0
-
R/W R/W R/W R/W R/W R/W R/W
Initial value
00000000B
CHAPTER 20 400 kHz I2C INTERFACE
Figure 20.2-1 I2C Interface Registers (2/2)
Seven bit slave address mask register (ISMK)
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
0035A7 H
ENSB SM6 SM5 SM4 SM3 SM2 SM1SM0
Initial value
01111111B
R/W R/W R/W R/W R/W R/W R/W R/W
Data register (IDAR)
Address:
0035A8H
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
D7 D6 D5 D4 D3 D2
D1 D0
Initial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
Clock control register (ICCR)
Address:
0035AB H
R/W
:
Readable/writable
-
:
Undefined
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
-
NSF EN CS4 CS3 CS2 CS1 CS0
-
R/W R/W R/W R/W R/W R/W R/W
Initial value
00011111B
369
CHAPTER 20 400 kHz I2C INTERFACE
20.2.1
Bus Status Register (IBSR)
The bus status register (IBSR) has the following functions:
• Bus busy detection
• Repeated start condition detection
• Arbitration loss detection
• Acknowledge detection
• Data transfer direction indication
• Addressing as slave detection
• General call address detection
• Address data transfer detection
■ Bus Status Register (IBSR)
This register is read-only, all bits are controlled by the hardware. All bits are cleared if the interface is not
enabled (EN = "0" in ICCR).
Figure 20.2-2 Configuration of the Bus Status Register (IBSR)
Address:
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Initial value
0035A0H
BB
RSC
AL
LRB
TRX AAS
0 0 0 0 0 0 0 0B
R
R
R
R
R
R
GCA
ADT
R
R
ADT
Address data transfer bit
0
Incoming data in not address data (bus not in use)
1
Incoming data is address data
GCA
Generall call address not received as slave
1
General call address received as slave
AAS
not addressed as slave
1
Addressed as slave
Tr ansferring data bit
0
Not transmitting data
1
Transmitting data
LRB
Last received bit
0
Receiver did not acknowledge
1
Receiver did acknowledge
AL
Arbitration loss bit
0
No arbitration loss detected
1
Arbitration loss detected
RSC
Repeated start condition bit
0
Repeated start condition not detected
1
Bus in use, repeated start condition detected
BB
370
Addressed as slave bit
0
TRX
R
General Call Address bit
0
Bus busy bit
:
Read only
0
Stop condition detected (bus idle)
:
Initial value
1
Start condition detected (bus in use)
CHAPTER 20 400 kHz I2C INTERFACE
■ Bus Status Register (IBSR) Contents
Table 20.2-1 Function of Each Bit of the Bus Status Register (IBSR) (1 / 2)
Bit name
Function
bit7
BB:
Bus busy bit
This bit indicates the status of the I2C bus.
"0": Stop condition detected (bus idle).
"1": Start condition detected (bus in use).
This bit is set to "1" if a start condition is detected. It is reset upon a stop condition.
bit6
RSC:
Repeated start
condition bit
This bit indicates detection of a repeated start condition.
"0": Repeated start condition not detected.
"1": Start condition detected (bus in use).
This bit is cleared at the end of an address data transfer (ADT="0") or detection of a stop
condition.
bit5
AL:
Arbitration loss
bit
This bit indicates an arbitration loss.
"0": No arbitration loss detected.
"1": Arbitration loss occurred during master sending.
This bit is cleared by writing "0" to the INT bit or by writing "1" to the MSS bit in the IBCR
register.
An arbitration loss occurs if:
• the data sent does not match the data read on the SDA line at the rising SCL edge.
• a repeated start condition is generated by another master in the first bit of a data byte.
• the interface could not generate a start or stop condition because another slave pulled the
SCL line "L" before.
bit4
LRB:
Last received bit
This bit is used to store the acknowledge message from the receiving side.
"0": Receiver acknowledged.
"1": Receiver did not acknowledge.
It is changed by the hardware upon reception of bit9 (acknowledge bit) and is also cleared
by a start or stop condition.
bit3
TRX:
Transferring data
bit
This bit indicates data sending operation during data transfer.
"0": Not transmitting data.
"1": Transmitting data.
It is set to "1":
• if a start condition was generated in master mode.
• at the end of a first byte transfer and read access as slave or sending data as master.
It is set to "0" if:
• the bus is idle (BB="0").
• an arbitration loss occurred.
• a "1" is written to the SCC bit during master interrupt (MSS="1" and INT="1").
• the MSS bit being cleared during master interrupt (MSS="1" and INT="1").
• the interface is in slave mode and the last transferred byte was not acknowledged.
• the interface is in slave mode and it is receiving data.
• the interface is in master mode and is reading data from a slave.
bit2
AAS:
Addressed as
slave bit
This bit indicates detection of a slave addressing.
"0": Not addressed as slave.
"1": Addressed as slave.
This bit is cleared by a (repeated-) start or stop condition. It is set if the interface detects its
seven and/or ten bit slave address.
371
CHAPTER 20 400 kHz I2C INTERFACE
Table 20.2-1 Function of Each Bit of the Bus Status Register (IBSR) (2 / 2)
Bit name
Function
bit1
GCA:
General call
address bit
This bit indicates detection of a general call address (0x00).
"0": General call address not received as slave.
"1": General call address received as slave.
This bit is cleared by a (repeated-) start or stop condition.
bit0
ADT:
Address data
transfer bit
This bit indicates the detection of an address data transfer.
"0": Incoming data is not address data (or bus is not in use).
"1": Incoming data is address data.
This bit is set to "1" by a start condition. It is cleared after the second byte if a ten bit slave
address header with write access is detected, else it is cleared after the first byte.
"After" the first/second byte means:
• a "0" is written to the MSS bit during a master interrupt (MSS="1" and INT="1" in
IBCR).
• a "1" is written to the SCC bit during a master interrupt (MSS="1" and INT="1" in
IBCR).
• the INT bit is being cleared.
• the beginning of every byte transfer if the interface is not involved in the current transfer
as master or slave.
372
CHAPTER 20 400 kHz I2C INTERFACE
20.2.2
Bus Control Register (IBCR)
The bus control register (IBCR) has the following functions:
• Interrupt enabling flags
• Interrupt generation flag
• Bus error detection flag
• Repeated start condition generation
• Master / slave mode selection
• General call acknowledge generation enabling
• Data byte acknowledge generation enabling
■ Bus Control Register (IBCR)
Write access to this register should only occur while the INT="1" or if a transfer is to be started. The user
should not write to this register during an ongoing transfer since changes to the ACK or GCAA bits could
result in bus errors. All bits in this register except the BER and the BEIE bit are cleared if the interface is
not enabled (EN="0" in ICCR).
Figure 20.2-3 Configuration of the Bus Control Register (IBCR)
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
0035A1H
BER BEIE SCC MSS
ACK GCAA INTE
INT
Initial value
00000000B
R/W R/W W R/W R/W R/W R/W R/W
INT
0
1
Interrupt flag bit
see table on next page for details
INTE
Interrupt enable bit
0
Interrupt disabled
1
Interrupt enabled
GCCA
Generall call address acknowledge bit
0
No acknowledge on general call address
1
Acknowledge on general call address
ACK
Acknowledge bit
0
No Acknowledge on data byte reception
1
Acknowledge on data byte reception
MSS
Master slave select bit
0
Go to slave mode
1
Go to master mode (s. table below for details)
SCC
Start condition continue bit
0
Write: No effect:
1
Write: Generate repeated start condition
BEIE
W
:
Write only
R/W
:
Readable/writable
:
Initial value
Bus error interrupt enable bit
0
Bus error interrupt disabled
1
Bus error interrupt enabled
Bus error bit
BER
Write
Read
0
Clear bus error int.
No error detected
1
No effect
Error detected
373
CHAPTER 20 400 kHz I2C INTERFACE
■ Bus Control Register (IBCR) Contents
Table 20.2-2 Function of Each Bit of the Bus Control Register (IBCR) (1 / 2)
Bit name
Function
bit15
BER:
Bus error bit
This bit is the bus error interrupt flag. It is set by the hardware and cleared by the user.
It always reads "1" in a read-modify-write access.
Write access:
"0": Clear bus error interrupt flag
"1": No effect
Read access:
"0": No bus error detected
"1": One of the error conditions described below detected
When this bit is set, the EN bit in the ICCR register is cleared, the I2C interface goes to
pause status, data transfer is interrupted and all bits in the IBSR and the IBCR registers
except BER and BEIE are cleared. The BER bit must be cleared before the interface
may be reenabled.
This bit is set to "1" if:
• start or stop conditions are detected at wrong places: during an address data transfer
or during the transfer of the bits two to nine (acknowledge bit).
• a ten bit address header with read access is received before a ten bit write access.
bit14
BEIE:
Bus error
interrupt enable
bit
This bit enables the bus error interrupt. It only can be changed by the user.
"0": Bus error interrupt disabled
"1": Bus error interrupt enabled
Setting this bit to "1" enables MCU interrupt generation when the BER bit is set to "1".
bit13
SCC:
Start condition
continue bit
This bit is used to generate a repeated start condition. It is write only - it always reads
"0".
"0": No effect
"1": Generate repeated start condition during master transfer
A repeated start condition is generated if a "1" is written to this bit while an interrupt in
master mode (MSS="1" and INT="1") and the INT bit is cleared automatically.
bit12
MSS:
Master slave
select bit
This is the master/slave mode selection bit. It can only be set by the user, but it can be
cleared by the user and the hardware.
"0": Go to slave mode
"1": Go to master mode, generate start condition and send address data byte in IDAR
register. It is cleared if an arbitration loss event occurs during master sending.
If a "0" is written to it during a master interrupt (MSS="1" and INT="1"), the INT bit is
cleared automatically, a stop condition will be generated and the data transfer ends.
Note that the MSS bit is reset immediately, the generation of the stop condition can be
checked by polling the BB bit in the IBSR register.
If a "1" is written to it while the bus is idle (MSS="0" and BB="0"), a start condition is
generated and the contents of the IDAR register (which should be address data) is sent.
If a "1" is written to the MSS bit while the bus is in use (BB="1" and TRX="0" in IBSR;
MSS="0" in IBCR), the interface waits until the bus is free and then starts sending.
If the interface is addressed as slave with write access (data reception) in the meantime,
it will start sending after the transfer ended and the bus is free again. If the interface is
sending data as slave in the meantime (AAS="1" and TRX="1" in IBSR), it will not
start sending data if the bus of free again. It is important to check whether the interface
was addressed as slave (AAS="1" in IBSR), sent the data byte successfully (MSS="1"
in IBCR) or failed to send the data byte (AL="1" in IBSR) at the next interrupt.
374
CHAPTER 20 400 kHz I2C INTERFACE
Table 20.2-2 Function of Each Bit of the Bus Control Register (IBCR) (2 / 2)
Bit name
Function
bit11
ACK:
Acknowledge bit
This is the acknowledge generation on data byte reception enable bit. It only can be
changed by the user.
"0": The interface will not acknowledge on data byte reception
"1": The interface will acknowledge on data byte reception
This bit is not valid when receiving address bytes in slave mode - if the interface detects
its 7 or 10 bit slave address, it will acknowledge if the corresponding enable bit (ENTB
in ITMK or ENSB in ISMK) is set.
Write access to this bit should occur during an interrupt (INT="1") or if the bus is idle
(BB="0" in the IBSR register) only.
bit10
GCAA:
General call
address
acknowledge bit
This bit enables acknowledge generation when a general call address is received. It only
can be changed by the user.
"0": The interface will not acknowledge on general call address byte reception.
"1": The interface will acknowledge on general call address byte reception.
Write access to this bit should occur during an interrupt (INT="1") or if the bus is idle
(BB="0" in IBSR register) or the interface is disabled (EN="0" in ICCR register) only.
bit9
INTE:
Interrupt enable
bit
This bit enables the MCU interrupt generation. It only can be changed by the user.
"0": Interrupt disabled
"1": Interrupt enabled
Setting this bit to "1" enables MCU interrupt generation when the INT bit is set to "1"
(by the hardware).
bit8
INT:
Interrupt flag bit
This bit is the transfer end interrupt request flag. It is changed by the hardware and can
be cleared by the user. It always reads "1" in a Read-Modify-Write access.
Write access:
"0": Clear transfer end interrupt request flag
"1": No effect
Read access:
"0": Transfer not ended or not involved in current transfer or bus is idle
"1": Set at the end of a 1-byte data transfer or reception including the acknowledge bit
under the following conditions:
Device is bus master l.
Device is addressed as slave.
General call address received.
Arbitration loss occurred.
Set at the end of an address data reception (after first byte if seven bit address received,
after second byte if ten bit address received) including the acknowledge bit if the device
is addressed as slave.
While this bit is "1" the SCL line will hold an "L" level signal. Writing "0" to this bit
clears the setting, releases the SCL line, and executes transfer of the next byte or a
repeated start or stop condition is generated. Additionally, this bit is cleared if a "1" is
written to the SCC bit or the MSS bit is being cleared.
375
CHAPTER 20 400 kHz I2C INTERFACE
■ SCC, MSS and INT Bit Competition
Simultaneously writing to the SCC, MSS and INT bits causes a competition to transfer the next byte, to
generate a repeated start condition or to generate a stop condition. In these cases the order of priority is as
follows:
Next byte transfer and stop condition generation.
When "0" is written to the INT bit and "0" is written to the MSS bit, the MSS bit takes priority and a stop
condition is generated.
Next byte transfer and start condition generation.
When "0" is written to the INT bit and "1" is written to the SCC bit, the SCC bit takes priority. A repeated
start condition is generated and the contents of the IDAR register is sent.
Repeated start condition generation and stop condition generation.
When a "1" is written to the SCC bit and "0" to the MSS bit, the MSS bit clearing takes priority. A stop
condition is generated and the interface enters slave mode.
376
CHAPTER 20 400 kHz I2C INTERFACE
20.2.3
Ten Bit Slave Address Register (ITBA)
This register (ITBAH / ITBAL) designates the ten bit slave address.
■ Ten Bit Slave address Register (ITBA)
Write access to this register is only possible if the interface is disabled (EN="0" in ICCR).
Figure 20.2-4 Configuration of Ten Bit Slave address Register (ITBA)
Address:
0035A3 H
Address:
0035A2 H
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
-
-
-
-
-
-
TA9 TA8
-
-
-
-
-
-
R/W R/W
ITBAH (upper)
Initial value
00000000 B
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ITBAL (lower)
TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0
Initial value
0 0 0 0 0 0 0 0B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
:
Readable/writable
-
:
Undefined
■ Ten Bit Slave address Register (ITBA) Contents
Table 20.2-3 Function of Each Bit of the Ten Bit Slave address Register (ITBA)
Bit name
Function
bit15 to
bit10
Undefined
These bits always return "0".
bit9 to bit0
TA9 to TA0:
Ten bit slave
address
When address data is received in slave mode, it is compared to the ITBA register if
the ten bit address is enabled (ENTB="1" in the ITMK register). An acknowledge is
sent to the master after reception of a ten bit address header*1 with write access1.
Then, the second incoming byte is compared to the TBAL register. If a match is
detected, an acknowledge signal is sent to the master device and the AAS bit is set.
Additionally, the interface acknowledges upon the reception of a ten bit header*2
with read access2 after a repeated start condition.
All bits of the slave address may be masked using the ITMK register. The received
ten bit slave address is written back to the ITBA register, it is only valid while the
AAS bit in the IBSR register is "1".
*1. A ten bit header (write access) consists of the following bit sequence: 11110, TA9, TA8, 0.
*2. A ten bit header (read access) consists of the following bit sequence: 11110, TA9, TA8, 1.
377
CHAPTER 20 400 kHz I2C INTERFACE
20.2.4
Ten Bit Address Mask Register (ITMK)
This register contains the ten bit slave address mask and the ten bit slave address
enable bit.
■ Ten Bit address Mask Register (ITMK)
Figure 20.2-5 Ten Bit address Mask Register (ITMK)
Address:
0035A5H
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
ENTB RAL
-
-
-
-
TM9 TM8
R/W R/W -
-
-
-
R/W R/W
Address:
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0035A4 H
TM7 TM6 TM5 TM4 TM3 TM2 TM1TM0
R/W R/W R/W R/W R/W R/W R/W R/W
378
R/W
:
Readable/writable
-
:
Undefined
(upper)
Initial value
0 0 1 1 1 1 1 1B
(lower)
Initial value
1 1 1 1 1 1 1 1B
CHAPTER 20 400 kHz I2C INTERFACE
■ Ten Bit address Mask Register (ITMK) Contents
Table 20.2-4 Function of Each Bit of the Ten Bit address Mask Register (ITMK)
Bit name
Function
bit15
ENTB:
Enable ten bit
slave address bit
This bit enables the ten bit slave address (and the acknowledging upon its reception).
Write access to this bit is only possible if the interface is disabled (EN="0" in ICCR).
"0": Ten bit address disabled
"1": Ten bit address enabled
bit14
RAL:
Received slave
address length bit
This bit indicates whether the interface was addressed as a seven or ten bit slave. It is
read-only.
"0": Addressed as seven bit slave
"1": Addressed as ten bit slave
This bit can be used to determine whether the interface was addressed as a seven or ten
bit slave if both slave addresses are enabled (ENTB="1" and ENSB="1"). Its contents is
only valid if the AAS bit in the IBSR register is "1". This bit is also reset if the interface
is disabled (EN="0" in ICCR).
bit13 to
bit10
Undefined
These bits always return "1" during reading.
bit9 to bit0
TM9 to TM0:
Ten bit slave
address mask bits
This register is used to mask the ten bit slave address of the interface. Write access to
these bits is only possible if the interface is disabled (EN="0" in ICCR).
"0": Bit is not used in slave address comparison
"1": Bit is used in slave address comparison
This can be used to make the interface acknowledge on multiple ten bit slave addresses.
Only the bits set to "1" in this register are used in the ten bit slave address comparison.
The received slave address is written back to the ITBA register and thus may be
determined by reading the ITBA register if the AAS bit in
the IBSR register is "1".
Note:
If the address mask is changed after the interface had been enabled, the slave address
should also be set again since it could have been overwritten by a previously
received slave address.
379
CHAPTER 20 400 kHz I2C INTERFACE
20.2.5
Seven Bit Slave Address Register (ISBA)
This register designates the seven bit slave address.
■ Seven Bit Slave address Register (ISBA)
Write access to this register is only possible if the interface is disabled (EN="0" in ICCR).
Figure 20.2-6 Configuration of Seven Bit Slave address Register (ISBA)
Address:
0035A6 H
R/W
:
Readable/writable
-
:
Undefined
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
-
SA6 SA5 SA4 SA3 SA2 SA1 SA0
-
R/W R/W R/W R/W R/W R/W R/W
Initial value
00000000 B
■ Seven Bit Slave address Register (ISBA) Contents
Table 20.2-5 Function of Each Bit of the Seven Bit Slave address Register
Bit name
Function
bit7
Undefined
This bit always returns "0" during reading.
bit6 to bit0
SA6 to SA0:
Seven bit slave
address bits
When address data is received in slave mode, it is compared to the ISBA register if the
seven bit address is enabled (ENSB="1" in the ISMK register). If a match is detected, an
acknowledge signal is sent to the master device and the AAS bit is set.
All bits of the slave address may be masked using the ISMK register. The received
seven bit slave address is written back to the ISBA register, it is only valid while the
AAS bit in the IBSR register is "1".
The interface does not compare the contents of this register to the incoming data if a ten
bit header or a general call is received.
■ Seven Bit Slave address Mask Register (ISMK)
This register contains the seven bit slave address mask and the seven bit mode enable bit. Write access to
this register is only possible if the interface is disabled (EN="0" in ICCR).
Figure 20.2-7 Configuration of Seven Bit Slave address Mask Register (ISMK)
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
0035A7 H
ENSB SM6 SM5 SM4 SM3 SM2 SM1SM0
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
380
:
Readable/writable
Initial value
01111111 B
CHAPTER 20 400 kHz I2C INTERFACE
■ Seven Bit Slave address Mask Register (ISMK) Contents
Table 20.2-6 Function of Each Bit of the Seven Bit Slave address Mask Register
Bit name
Function
bit15
ENSB:
Enable seven bit
slave address bit
This bit enables the seven bit slave address (and the acknowledging upon its reception).
"0": Seven bit slave address disabled
"1": Seven bit slave address enabled
bit14 to
bit8
SM6 to SM0:
Seven bit slave
address mask bits
This register is used to mask the seven bit slave address of the interface.
"0": Bit is not used in slave address comparison.
"1": Bit is used in slave address comparison.
This can be used to make the interface acknowledge on multiple seven bit slave
addresses. Only the bits set to "1" in this register are used in the seven bit slave address
comparison. The received slave address is written back to the ISBA register and may
thus may be determined by reading the ISBA register if the AAS bit in the IBSR register
is "1".
Note:
If the address mask is changed after the interface had been enabled, the slave address
should also be set again since it could have been overwritten by a previously
received slave address.
381
CHAPTER 20 400 kHz I2C INTERFACE
20.2.6
Data Register (IDAR)
Data Register for the 400 kHz I2C Interface.
■ Data Register (IDAR)
Figure 20.2-8 Configuration of Data Register (IDAR)
Address:
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0035A8H
D7 D6 D5 D4 D3 D2
D1 D0
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
:
Initial value
00000000 B
Readable/writable
■ Data Register (IDAR) Contents
Table 20.2-7 Function of Each Bit of the Data Register
Bit name
bit7 to bit0
382
D7 to D0:
Data bits
Function
The data register is used in serial data transfer, and transfers data MSB-first. This
register is double buffered on the write side, so that when the bus is in use
(BB="1"), write data can be loaded to the register for serial transfer. The data byte
is loaded into the internal transfer register if the INT bit in the IBCR register is
being cleared or the bus is idle (BB="0" in IBSR). In a read access, the internal
register is read directly, therefore received data values in this register are only
valid if INT="1" in the IBCR register.
CHAPTER 20 400 kHz I2C INTERFACE
20.2.7
Clock Control Register (ICCR)
The clock control register (ICCR) has the following functions:
• Enable test mode
• Enable I/O pad noise filters
• Enable I2C interface operation
• Setting the serial clock frequency
■ Clock Control Register (ICCR)
Figure 20.2-9 Configuration of Clock Control Register (ICCR)
Address:
0035AB H
R/W
:
Readable/writable
-
:
Undefined
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
-
NSF EN CS4 CS3 CS2 CS1 CS0
-
R/W R/W R/W R/W R/W R/W R/W
ICCR
Initial value
00011111 B
383
CHAPTER 20 400 kHz I2C INTERFACE
■ Clock Control Register (ICCR) Contents
Table 20.2-8 Function of Each Bit of the Clock Control Register
Bit name
Function
bit15
Undefined
This bit always returns "0" during reading.
bit14
NSF:
I/O pad noise
filter enable bit
This bit enables the noise filters built into the SDA and SCL I/O pads.
The noise filter will suppress single spikes with a pulse width of 0 ns (minimum) and
between 1 and 1.5 cycles of internal-bus (maximum). The maximum depends on the
phase relationship between I2C signals (SDA, ACL) and machine clock.
It should be set to "1" if the interface is transmitting or receiving at data rates above 100
kBit.
bit13
EN:
Enable bit
This bit enables the I2C interface operation. It can only be set by the user but may be
cleared by the user and the hardware.
"0": Interface disabled
"1": Interface enabled
When this bit is set to "0" all bits in the IBSR register and IBCR register (except the
BER and BEIE bits) are cleared and the module is disabled and the I2C lines are left
open. It is cleared by the hardware if a bus error occurs (BER="1" in IBCR).
Note:
The interface immediately stops transmitting or receiving if is it is being disabled.
This might leave the I2C bus in an undesired state.
bit12 to
bit 8
CS4 to CS0:
Clock prescaler
bits
These bits select the serial bit rate. They can only be changed if the interface is disabled
(EN="0") or the EN bit is being cleared in the same write access.
n
CS4
CS3
CS2
CS1
CS0
1
0
0
0
0
1
Bitrate: φ / 28(+1)
2
0
0
0
1
0
Bitrate: φ / 40(+1)
3
0
0
0
1
1
Bitrate: φ / 52(+1)
4
0
0
1
0
0
Bitrate: φ / 64(+1)
1
1
1
1
1
Bitrate: φ / 400(+1)
...
31
(+1) means: Add 1 to divisor, if noise filter is enabled
384
CHAPTER 20 400 kHz I2C INTERFACE
■ Clock Prescaler Settings
The calculation formula for CS0 to CS4 is determined as follows:
Bitrate =
φ
n 12 + 16
n>0
: machine clock, Noise filter disabled
Bitrate =
φ
n 12 + 17
n>0
: machine clock, Noise filter enabled
Table 20.2-9 Prescaler Settings
n
CS4
CS3
CS2
CS1
CS0
1
0
0
0
0
1
2
0
0
0
1
0
3
0
0
0
1
1
1
1
1
...
31
1
1
Note:
Do not use n=0 prescaler setting, it violates SDA/SCL timings.
■ Common Machine Clock Frequencies
The most common machine clock frequencies with their prescaler settings and the resulting sending bit
rate:
Table 20.2-10 Common Machine Clock Frequencies
Machine clock
[MHz]
100 Kbits (Noise filter disabled)
n bit rate [Kbit]
400 Kbits (Noise filter enabled)
n bit rate [Kbit]
24
19
98
4
369
20
16
96
3
377
16
12
100
2
390
40/3 = 13.3
10
98
2
325
12
9
96
2
292
64/6 = 10.6
8
94
1
367
10
7
100
1
344
8
6
90
1
275
385
CHAPTER 20 400 kHz I2C INTERFACE
20.3
I2C Interface Operation
The I2C bus executes communication using two bi-directional bus lines, the serial data
line (SDA) and serial clock line (SCL). The I2C interface has two open-drain I/O pins
(SDA/SCL) corresponding to these lines, enabling wired logic applications.
■ Start Conditions
When the bus is free (BB="0" in IBSR, MSS="0" in IBCR), writing "1" to the MSS bit places the I2C
interface in master mode and generates a start condition.
If a "1" is written to it while the bus is idle (MSS="0" and BB="0"), a start condition is generated and the
contents of the IDAR register (which should be address data) is sent.
Repeated start conditions can be generated by writing "1" to the SCC bit when in bus master mode and
interrupt status (MSS="1" and INT="1" in IBCR).
If a "1" is written to the MSS bit while the bus is in use (BB="1" and TRX="0" in IBSR; MSS="0"and
INT="0"in IBCR), the interface waits until the bus is free and then starts sending.
If the interface is addressed as slave with write access (data reception) in the meantime, it will start sending
after the transfer ended and the bus is free again. If the interface is sending data as slave in the meantime, it
will not start sending data if the bus of free again. It is important to check whether the interface was
addressed as slave (MSS="0" in IBCR and AAS="1" in IBSR), sent the data byte successfully (MSS="1" in
IBCR) or failed to send the data byte (AL="1" in IBSR) at the next interrupt.
Writing "1" to the MSS bit or SCC bit in any other situation has no significance.
■ Stop Conditions
Writing "0" to the MSS bit in master mode (MSS="1" and INT="1" in IBCR) generates a stop condition
and places the device in slave mode. Writing "0" to the MSS bit in any other situation has no significance.
After clearing the MSS bit, the interface tries to generate a stop condition which might fail if another
master pulls the SCL line "L" before the stop condition has been generated. This will generate an interrupt
after the next byte has been transferred!
■ Slave address Detection
In slave mode, after a start condition is generated the BB is set to "1" and data sent from the master device
is received into the IDAR register.
After the reception of eight bits, the contents of the IDAR register is compared to the ISBA register using
the bit mask stored in ISMK if the ENSB bit in the ISMK register is "1". If a match results, the AAS bit is
set to "1" and an acknowledge signal is sent to the master. Then bit0 of the received data (bit0 of the IDAR
register) is inverted and stored in the TRX bit.
If the ENTB bit in the ITMK register is "1" and a ten bit address header (11110, TA1, TA0, write access) is
detected, the interface sends an acknowledge signal to the master and stores the inverted last data bit in the
TRX register. No interrupt is generated. Then, the next transferred byte is compared (using the bit mask
stored in ITMK) to the lower byte of the ITBA register. If a match is found, an acknowledge signal is sent
to the master, the AAS bit is set and an interrupt is generated.
If the interface was addressed as slave and detects a repeated start condition, the AAS bit is set after
reception of the ten bit address header (11110, TA1, TA0, read access) and an interrupt is generated.
386
CHAPTER 20 400 kHz I2C INTERFACE
Since there are separate registers for the ten and seven bit address and their bit masks, it is possible to make
the interface acknowledge on both addresses by setting the ENSB (in ISMK) and ENTB (in ITMK) bits.
The received slave address length (seven or ten bit) may be determined by reading the RAL bit in the
ITMK register (this bit is valid if the AAS bit is set only).
It is also possible to give the interface no slave address by setting both bits to "0" if it is only used as a
master.
All slave address bits may be masked with their corresponding mask register (ITMK or ISMK).
■ Slave address Masking
Only the bits set to "1" in the mask registers (ITMK / ISMK) are used for address comparison, all other bits
are ignored. The received slave address can be read from the ITBA (if ten bit address received, RAL="1")
or ISBA (if seven bit address received, RAL="0") register if the AAS bit in the IBSR register is "1".
If the bit masks are cleared, the interface can be used as a bus monitor since it will always be addressed as
slave. Note that this is not a real bus monitor because it acknowledges upon any slave address reception,
even if there is no other slave listening.
■ Addressing Slaves
In master mode, after a start condition is generated the BB and TRX bits are set to "1" and the contents of
the IDAR register is sent in MSB first order. After address data is sent and an acknowledge signal was
received from the slave device, bit0 of the sent data (bit0 of the IDAR register after sending) is inverted and
stored in the TRX bit. Acknowledgement by the slave may be checked using the LRB bit in the IBSR
register. This procedure also applies to a repeated start condition.
In order to address a ten bit slave for write access, two bytes have to be sent. The first one is the ten bit
address header which consists of the bit sequence "1 1 1 1 0 A9 A8 0", it is followed by the second byte
containing the lower eight bits of the ten bit slave address (A7 - A0).
A ten bit slave is accessed for reading by sending the above byte sequence and generating a repeated start
condition (SCC bit in IBCR) followed by a ten bit address header with read access (1 1 1 1 0 A9 A8 1).
Summary of the address data bytes:
7 bit slave, write access: Start condition - A6 A5 A4 A3 A2 A1 A0 0.
7 bit slave, read access: Start condition - A6 A5 A4 A3 A2 A1 A0 1.
10 bit slave, write access: Start condition - 1 1 1 1 0 A9 A8 0 - A7 A6 A5 A4 A3 A2 A1 A0.
10 bit slave, read access: Start condition - 1 1 1 1 0 A9 A8 1 - A7 A6 A5 A4 A3 A2 A1 A0 - repeated start
- 1 1 1 1 0 A9 A8 1.
■ Arbitration
During sending in master mode, if another master device is sending data at the same time, arbitration is
performed. If a device is sending the data value "1" and the data on the SDA line has an "L" level value, the
device is considered to have lost arbitration, and the AL bit is set to "1." Also, the AL bit is set to "1" if a
start condition is detected at the first bit of a data byte but the interface did not want to generate one or the
generation of a start or stop condition failed by some reason.
Arbitration loss detection clears both the MSS and TRX bit and immediately places the device in slave
mode so it is able to acknowledge if its own slave address is being sent.
387
CHAPTER 20 400 kHz I2C INTERFACE
■ Acknowledgement
Acknowledge bits are sent from the receiver to the transmitter. The ACK bit in the IBCR register can be
used to select whether to send an acknowledgment when data bytes are received.
When data is send in slave mode (read access from another master), if no acknowledgement is received
from the master, the TRX bit is set to "0" and the device goes to receiving mode. This enables the master to
generate a stop condition as soon as the slave has released the SCL line.
In master mode, acknowledgement by the slave can be checked by reading the LRB bit in the IBSR
register.
388
CHAPTER 20 400 kHz I2C INTERFACE
20.4
Programming Flow Charts
Each programming flow charts for the 400 kHz I2C interface is shown below.
■ Programming Flow Charts
Figure 20.4-1 Example of Slave Addressing and Sending Data
Addressing a 7 bit slave
Sending data
Start
Start
Address slave for write
Clear BER bit (if set);
Enable Interface EN:=1;
IDAR := Data Byte;
INT := 0
IDAR := sl.address<<1+RW;
MSS := 1; INT := 0
N
INT=1?
N
INT=1?
Y
Y
Y
BER=1?
Y
Bus error
BER=1?
N
N
AL=1?
Restart
transfer
Check
if AAS
Y
AL=1?
Restart
transfer
Check
if AAS
Y
N
N
ACK?
ACK?
N
(LRB=0?)
N
(LRB=0?)
Y
Y
Ready to send data
Last byte
transferred?
Y
N
Slave did not ACK
Generate
repeated start
or stop condition
Transfer End
Generate
repeated start or
stop condition
389
CHAPTER 20 400 kHz I2C INTERFACE
Figure 20.4-2 Example of Receiving Data
Start
Address slave for read
Clear ACK bit in IBCR if it’s the
last byte to read from slave;
INT := 0
N
INT=1?
Y
BER=1?
Y
N
N
Last byte
transferred?
Y
Transfer End
Generate
repeated start or
stop condition
390
Bus error
reenable IF
CHAPTER 21
SERIAL I/O
This chapter explains the functions and operations of
the serial I/O.
21.1 Outline of Serial I/O
21.2 Serial I/O Registers
21.3 Serial I/O Prescaler (CDCR)
21.4 Serial I/O Operation
391
CHAPTER 21 SERIAL I/O
21.1
Outline of Serial I/O
The serial I/O interface operates in two modes:
• Internal shift clock mode: Data is transferred in synchronization with the internal
clock.
• External shift clock mode: Data is transferred in synchronization with the clock
supplied via the external pin (SCK4). By manipulating the
general-purpose port sharing the external pin (SCK4),
data can also be transferred by a CPU instruction in this
mode.
■ Serial I/O Block Diagram
This block is a serial I/O interface that allows data transfer using clock synchronization. The interface
consists of a single eight-bit channel. Data can be transferred from the LSB or MSB.
Figure 21.1-1 Extended Serial I/O Interface Block Diagram
Internal data bus
(MSB first) D7 to D0
D7 to D0 (LSB first)
Transfer direction selection
SIN3
SIN4
Read
SDR (Serial data register)
Write
SOT4
SOT3
SCK3
SCK4
Control circuit
Shift clock counter
Internal clock
2
SMD2
1
0
SMD1 SMD0
SIE
SIR
BUSY
STOP
STRT MODE
Interrupt
request
Internal data bus
392
BDS
SOE
SCOE
CHAPTER 21 SERIAL I/O
21.2
Serial I/O Registers
The serial I/O has the following two registers:
• Serial mode control status register (SMCS)
• Serial data register (SDR)
■ Serial I/O Registers
Figure 21.2-1 Serial I/O Registers
Serial mode control status register (SMCS)
Address : bit15 bit14 bit13
00002DH SMD2 SMD1 SMD0
Address :
00002CH
bit7
bit6
bit5
bit12
bit11
bit10
bit9
bit8
SIE
SIR
BUSY
STOP STRT
bit4
bit3
bit2
bit1
bit0
MODE
BDS
SOE
SCOE
Serial data register (SDR)
Address :
00002EH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
393
CHAPTER 21 SERIAL I/O
21.2.1
Serial Mode Control Status Register (SMCS)
The serial mode control status register (SMCS) controls the serial I/O transfer mode.
■ Upper Byte of Serial Mode Control Status Register (SMCS)
Figure 21.2-2 Configuration of the Serial Mode Control Status Register (Upper Byte)
bit15
Address:
00002D H
bit14
SMD2 SMD1
R/W
R/W
bit13
bit12
bit11
bit10
bit9
bit8
SMD0
SIE
SIR
BUSY
STOP
STRT
R/W
R/W
R/W
R
R/W
R/W
STRT
0
1
STOP
0
1
BUSY
0
1
R/W : Readable/writable
R
: Read only
: Initial value
394
Initial value
00000010 B
Start bit
Writing "0" has no effect
"0" is always read
Writing "1" activates serial transfer, if MODE = 0
Stop bit
Normal operation
Transfer stopped
Tr ansfer status bit
Tr ansfer is stopped or standing by for serial data
register R/W
Serial transfer is active
SIR
0
1
Serial I/O interrupt request bit
No interrupt is requested
SIE
0
1
Serial I/O interrupt enable bit
Serial I/O interrupt disabled
Serial I/O interrupt enabled
SMD2 to
SMD0
000
001
010
011
100
101
110
111
Prescaler output clock is divided by 2
Prescaler output clock is divided by 4
Prescaler output clock is divided by 16
Prescaler output clock is divided by 32
Prescaler output clock is divided by 64
External shift clock mode
Prescaler output clock is divided by 8
Prescaler output clock is divided by 128
If SIE = 1, an interrupt request is issued to CPU
Shift clock mode selection bits
CHAPTER 21 SERIAL I/O
■ Lower Byte of Serial Mode Control Status Register (SMCS)
Figure 21.2-3 Configuration of the Serial Mode Control Status Register (Lower Byte)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
-
-
-
MODE
BDS
SOE
SCOE
-
-
-
-
R/W
R/W
R/W
R/W
Address :
00002C H
SCOE
0
1
SOE
0
1
Shift clock output enable bit
General-purpose port pin, transfer for each
instruction
Shift Clock output pin
Serial output enable bit
General-purpose port pin
Serial data output
BDS
0
1
R/W : Readable/writable
X
: Undefined value
: Undefined
: Initial value
MODE
0
1
Initial value
XXXX0000 B
Bit direction select bit
LSB first
MSB first
Serial mode selection bit
Transfer starts when STRT = 1
Tr ansfer starts, when the serial data register is
read or written to
395
CHAPTER 21 SERIAL I/O
■ Bit Functions of Serial Mode Control Status Register (SMCS)
Table 21.2-1 Bit Functions of Serial Mode Control Status Register
Bit No.
Name
Function
bit15
to
bit13
SMD0 to SMD2:
Shift clock mode
selection bits
See Table 21.2-2.
bit12
SIE:
Serial I/O interrupt
enable bit
This bit controls the serial I/O interrupt request as shown above.This bit is initialized to "0" upon a
reset. This bit is readable and writable.
bit11
SIR:
Serial I/O interrupt
request bit
When serial data transfer is completed, "1" is set to this bit. If this bit is set while interrupts are
enabled (SIE=1), an interrupt request is issued to the CPU. The clear condition varies with the
MODE bit.
When "0" is written to the MODE bit, the SIR bit is cleared by writing "0". When "1" is
written to the MODE bit, the SIR bit is cleared by reading or writing to SDR. When the
system is reset or "1" is written to the STOP bit, the SIR bit is cleared regardless of the
MODE bit value.
Writing "1" to the SIR bit has no effect. "1" is always read by a read operation of a read-modifywrite instruction.
bit10
BUSY:
Transfer status bit
The transfer status bit indicates whether serial transfer is being executed. This bit is initialized to "0"
upon a reset. This is a read-only bit.
bit9
STOP:
Stop bit
The stop bit forcibly terminates serial transfer. When "1" is written to this bit, the transfer is stopped.
This bit is initialized to "1" upon a reset. This bit is readable and writable.
bit8
STRT:
Start bit
The start bit activates serial transfer. Writing "1" to this bit starts the data transfer when the MODE
bit is set to "0". When the MODE bit is set to "1" and the STRT bit is set to "1", writing the data into
serial data register starts the transfer.
Writing "1" is ignored while the system is performing serial transfer or standing by for a
serial shift register read or write. Writing "0" has no effect. "0" is always read.
bit3
MODE:
Serial mode selection
bit
The serial mode selection bit is used to select the conditions to start the transfer operation from the
stop state. This bit must not be updated during operation.
bit2
BDS:
Bit Direction Select
bit
When serial data is input or output, this bit determines from which bit data is to be transferred first,
the least significant bit (LSB first) or the most significant bit (MSB first), as shown above. Specify
the bit ordering before any data is written to SDR.
bit1
SOE:
Serial Output Enable
bit
This bit controls the output from the serial I/O output external pins (SOT4).
SCOE:
Shift clock output
enable bit
This bit controls the output from the shift clock I/O output external pins (SCK4) as shown above.
bit0
This bit is initialized to "0" upon a reset and can be read or written to. To activate the
intelligent I/O service, ensure that "1" is written to this bit.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
Ensure that "0" is written to this bit when data is transferred for each instruction in
external shift clock mode.
This bit is initialized to "0" upon a reset. This bit is readable and writable.
396
CHAPTER 21 SERIAL I/O
■ Shift Clock Selection
The Shift Clock Mode Selection bits are used to select the serial shift clock mode, as shown in Table 21.22. The second part is related to the Serial I/O prescaler register (CDCR). For details, see Section "21.3
Serial I/O Prescaler (CDCR)".
Table 21.2-2 Setting the Serial Shift Clock Mode
SMD2
SMD1
SMD0
φ=24MHz
div=6
φ=20MHz
div=4
φ=16MHz
div=4
φ=8MHz
div=4
φ=4MHz
div=4
0
0
0
2 MHz
2.5 MHz
2 MHz
1 MHz
500 kHz
0
0
1
1 MHz
1.25 MHz
1 MHz
500 kHz
250 kHz
0
1
0
250 kHz
312.5 kHz
250 kHz
125 kHz
62.5 kHz
0
1
1
125 kHz
156.25 kHz
125 kHz
62.5 kHz
31.25 kHz
1
0
0
62.5kHz
78.125 kHz
62.5 kHz
31.25 kHz
15.625 kHz
1
0
1
1
1
0
500 kHz
625 kHz
500 kHz
250 kHz
125 kHz
1
1
1
31.25 kHz
39.1 kHz
31.25 kHz
15.625 kHz
7812.5 Hz
External shift clock mode
Table 21.2-3 Division Ratio for Serial I/O Prescaler Register
div
MD
DIV3
DIV2
DIV1
DIV0
Recommended
machine cycle
3
1
0
0
1
0
6 MHz
4
1
0
0
1
1
8 MHz
5
1
0
1
0
0
10 MHz
6
0
0
1
0
1
12 MHz
7
0
0
1
1
0
14 MHz
8
1
0
1
1
1
16 MHz
The SMD bits are initialized to "000B" upon a reset. These bits must not be updated during data transfer.
Shift operation can be performed for each instruction by specifying SCOE =0 during clock selection and by
using the ports that share the SCK4 pin.
397
CHAPTER 21 SERIAL I/O
21.2.2
Serial Data Register (SDR)
This serial data register stores the serial I/O transfer data. During transfer, the SDR
must not be read or written to.
■ Serial Data Register (SDR)
Figure 21.2-4 Configuration of Serial Data Register (SDR)
Address :
00002E H
R/W : Readable/writable
X
: Undefined value
398
bit7
bit6
bit5
bit4
D7
D6
D5
D4
R/W
R/W
R/W
R/W
bit3
bit2
bit1
bit0
D3
D2
D1
D0
R/W
R/W
R/W
R/W
Initial value
XXXXXXXXB
CHAPTER 21 SERIAL I/O
21.3
Serial I/O Prescaler (CDCR)
The Serial I/O Prescaler provides the shift clock for the Serial I/O.
The operation clock for the Serial I/O is obtained by dividing the machine clock. The
Serial I/O is designed so that a constant baud rate can be obtained for a variety of
machine clocks by the use of the communication prescaler. The CDCR register controls
the machine clock division.
■ Serial I/O Prescaler (CDCR)
Figure 21.3-1 Configuration of the Serial I/O Prescaler (CDCR)
Address :
00002FH
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
MD
-
NEG
-
DIV3
DIV2
DIV1
DIV0
R/W
-
R/W
-
R/W
R/W
R/W
R/W
DIV3 to
DIV0
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
NEG
0
1
R/W : Readable/writable
X
: Undefined value
-
MD
0
1
Initial value
0X0X0000 B
Machine cloc k division ratio bits
Division ratio: div =
Division ratio: div =
Division ratio: div =
Division ratio: div =
Division ratio: div =
Division ratio: div =
Division ratio: div =
Division ratio: div =
reserved
1
2
3
4
5
6
7
8
Negative cloc k operation bit
Normal operation
The shift clock signal is inverted
Machine clock divide mode select bit
The Serial I/O Prescaler is disabled.
The Serial I/O Prescaler is enabled.
: Undefined
: Initial value
Note:
When the division ratio is changed, allow two cycles for the clock to stabilize before starting
communication.
399
CHAPTER 21 SERIAL I/O
21.4
Serial I/O Operation
The extended serial I/O consists of the serial mode control status register (SMCS) and
shift register (SDR), and is used for input and output of 8-bit serial data.
■ Serial I/O Operation
The bits in the shift register are serially output via the serial output pin (SOT4 pin) at the falling edge of the
serial shift clock (external clock or internal clock). The bits are serially input to the shift register (SDR) via
the serial input pin (SIN4 pin) at the rising edge of the serial shift clock. The shift direction (transfer from
MSB or LSB) is specified by the direction specification bit (BDS) of the serial mode control status register
(SMCS).
At the end of serial data transfer, this block is stopped or stands by for a read or write of the data register
according to the MODE bit of the serial mode control status register (SMCS). To start transfer from the
stop or standby state, follow the procedure below.
• To resume operation from the stop state, write "0" to the STOP bit and "1" to the STRT bit. (The STOP
and STRT bits can be set simultaneously.)
• To resume operation from the serial shift data register R/W standby state, read or write to the data
register.
400
CHAPTER 21 SERIAL I/O
21.4.1
Shift Clock
There are two modes of shift clock: internal or external shift clock. These two modes
are selected by setting the SMCS. To switch the modes, ensure that serial I/O transfer is
stopped. To check whether the serial I/O transfer is stopped, read the BUSY bit.
■ Internal Shift Clock Mode
In internal shift clock mode, data transfer is based on the internal clock. As a synchronization timing
output, a shift clock of 50% duty ratio can be output from the SCK4 pin. Data is transferred at one bit per
clock. The transfer frequency and speed is expressed as follows:
Transfer frequency [Hz] =
φ
Transfer speed [s] =
A div
A div
φ
"A" is the division ratio indicated by the SMD bits of SMCS. The value can be 21, 22, 23, 24, 25, 26 or 27. φ
is the machine frequency.
■ External Shift Clock Mode
In external shift clock mode, the data transfer is based on the external clock supplied via the SCK4 pin.
Data is transferred at one bit per clock.
The transfer speed can be between DC and 1/(5 machine cycles). For example, the transfer speed can be up
to 2 MHz when 1 machine cycle is equal to 0.1 μs. The external clock frequency has a maximum value of 2
MHz.
A data bit can also be transferred by software, which is enabled as described below.
Select external shift clock mode, and write "0" to the SCOE bit of SMCS. Then, write "1" to the direction
register for the port sharing the SCK4 pin, and place the port in output mode. Then, when "1" and "0" are
written to the data register (PDR) of the port, the port value output via the SCK4 pin is fetched as the
external clock and transfer starts. Ensure that the shift clock starts from "H".
Note:
The SMCS or SDR must not be written to during serial I/O operation.
401
CHAPTER 21 SERIAL I/O
21.4.2
Serial I/O Operation
There are four serial I/O operation statuses:
• STOP
• Halt
• SDR R/W standby
• Transfer
■ Serial I/O Operation
● STOP
The STOP state is initiated upon RESET or when "1" is written to the STOP bit of SMCS. The shift
counter is initialized, and "0" is written to SIR.
To resume operation from the STOP state, write "0" to STOP and "1" to STRT. (These two bits can be
written to simultaneously.) Since the STOP bit overrides the STRT bit, transfer cannot be started by writing
"1" to STRT while "1" is written to STOP.
● Halt
When transfer is completed while the MODE bit is "0", "0" is set to BUSY and "1" is set to SIR of the
SMCS, the counter is initialized, and the system stops. To resume operation from the stop state, write "1" to
STRT.
● Serial data register R/W standby
When transfer is completed while the MODE bit is "1", "0" is set to BUSY and "1" is set to SIR of the
SMCS, and the system enters the serial data register R/W standby state. If the interrupt enable flag is set, an
interrupt signal is output from this block.
To resume operation from R/W standby state, read or write to the serial data register. This sets the BUSY
bit to "1" and starts data transfer.
● Transfer
"1" is set to the BUSY bit and serial transfer is being performed. According to the MODE bit, the halt state
or R/W standby state comes next.
Figure 21.4-1 is a diagram of the operation transitions.
402
CHAPTER 21 SERIAL I/O
Figure 21.4-1 Extended I/O Serial Interface Operation Transitions
STOP
STRT=0, BUSY=0
MODE=0
STOP=0
&
STRT=1
Reset
STOP=0 & STRT=0
End of transfer
STRT=0, BUSY=0
STOP=1
MODE=0
&
STOP=0
&
END
STOP=1
STOP=1
STOP=0
&
STRT=1
Transfer
Serial data register R/W standby
MODE=1 & END & STOP=0
STRT=1, BUSY=1
STRT=1, BUSY=0
MODE=1
SDR R/W & MODE=1
Serial data
Figure 21.4-2 Serial Data Register Read/Write
Data bus
SOT4
SOT3
SIN4
SIN3
Data bus
Read
Write
Interrupt output
Extended I/O
serial interface
Read
Write
CPU
(1)
(2)
Interrupt input
Data bus Interrupt controller
(1)If "1" is written to MODE, transfer ends according to the shift clock counter. The read/write
standby state starts when "1" is written to SIR. If "1" is written to the SIE bit, an interrupt
signal is generated. No interrupt signal is generated when SIE is inactive or transfer has
been terminated by writing "1" to STOP.
(2)Reading or writing to the serial data register clears the interrupt request and starts serial
transfer.
403
CHAPTER 21 SERIAL I/O
21.4.3
Shift Operation Start/Stop Timing
To start the shift operation, set the STOP bit to "0" and the STRT bit to "1" in SMCS.
The system may stop the shift operation at the end of transfer or when "1" is set in the
STOP bit.
• Stop by STOP=1 → The system stops with SIR=0 regardless of the MODE bit
• Stop by end of transfer → The system stops with SIR=1 regardless of the MODE bit
Regardless of the MODE bit, the BUSY bit becomes "1" during serial transfer and
becomes "0" during stop or R/W standby state. To check the transfer status, read this
bit.
■ Shift Operation Start/Stop Timing
● Internal shift clock mode (LSB first)
Figure 21.4-3 Shift Operation Start/Stop Timing (Internal Clock)
"1" output
SCK4
(Transfer start)
STRT
(Transfer end)
If MODE=0
BUSY
SOT4
DO0
DO7 (Data maintained)
● External shift clock mode (LSB first)
Figure 21.4-4 Shift Operation Start/Stop Timing (External Clock)
SCK4
(Transfer start)
STRT
(Transfer end)
If MODE=0
BUSY
SOT4
404
DO0
DO7 (Data maintained)
CHAPTER 21 SERIAL I/O
● External shift clock mode with instruction shift (LSB first)
Figure 21.4-5 Shift Operation Start/Stop Timing (External Shift Clock Mode with Instruction Shift)
SCK="0" in PDR
SCK4
STRT
SCK="0"in PDR
SCK="1" in PDR (Transfer end)
If MODE=0
BUSY
DO7 (Data maintained)
DO6
SOT4
Note: For an instruction shift, "H" is output when "1" is written to the bit corresponding to SCK of PDR,
and "L" is output when "0" is written. (When SCOE=0 in external shift clock mode)
● Stop by STOP=1 (LSB first, internal clock)
Figure 21.4-6 Stop Timing when "1" is Written to the STOP Bit
"1" output
SCK4
(Transfer start)
(Transfer stop)
If MODE=0
STRT
BUSY
STOP
DO3
SOT4
DO4
DO5 (Data maintained)
Note:
DO7 to DO0 indicate output data.
During serial data transfer, data is output from the serial output pin (SOT4) at the falling edge of the
shift clock, and input from the serial input pin (SIN4) at the rising edge.
405
CHAPTER 21 SERIAL I/O
Figure 21.4-7 Serial Data I/O Shift Timing
❍ LSB first (When the BDS bit is "0")
SCK4
SIN Input
SIN4
DI0
DI1
DI2
DI3
SOT Output
DI4
DI5
DI6
DI7
SOT4
DO0
DO1
DO2
DO4
DO5
DO6
DO7
DO3
❍ MSB first (When the BDS bit is "1")
SCK4
SIN Input
SIN4
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO4
DO3
DO2
DO1
DO0
SOT Output
SOT4
406
DO7
DO6
DO5
CHAPTER 21 SERIAL I/O
21.4.4
Interrupt Function of the Extended Serial I/O Interface
This block can issue an interrupt request to the CPU. At the end of data transfer, the SIR
bit is set as an interrupt flag. When "1" is written to the interrupt enable bit (SIE bit) of
SMCS, an interrupt request is issued to the CPU.
■ Interrupt Function of the Extended Serial I/O Interface
Figure 21.4-8 Interrupt Signal Output Timing of the Extended Serial I/O Interface
SCK4
(Transfer end)
BUSY
(Transfer start)
SIE=1
SIR
SDR RD/WR
SOT4
DO6
DO7 (Data is maintained.)
DO0
When MODE=1
SCK4
(Transfer end)
BUSY
SIE=1
SIR
SDR RD/WR
SOT4
DO6
DO7 (Data is maintained.)
When MODE=0
407
CHAPTER 21 SERIAL I/O
408
CHAPTER 22
CAN CONTROLLER
This chapter explains the functions and operations of
the CAN controller.
CAUTION: Do not use the clock modulation and CAN at
the same time on devices MB90F947, MB90F949 and
MB90V390HA. The problem is fixed on MB90F946A,
MB90947A, MB90F947A, MB90F949A, MB90V390HB.
22.1 Features of CAN Controller
22.2 Block Diagram of CAN Controller
22.3 List of Overall Control Registers
22.4 List of Message Buffers (ID Registers)
22.5 List of Message Buffers (DLC Registers and Data Registers)
22.6 Classifying the CAN Controller Registers
22.7 Transmission of CAN Controller
22.8 Reception of CAN Controller
22.9 Reception Flowchart of CAN Controller
22.10 How to Use the CAN Controller
22.11 Procedure for Transmission by Message Buffer (x)
22.12 Procedure for Reception by Message Buffer (x)
22.13 Setting Configuration of Multi-level Message Buffer
22.14 Setting the CAN Direct Mode Register
22.15 Precautions when Using CAN Controller
409
CHAPTER 22 CAN CONTROLLER
22.1
Features of CAN Controller
The CAN controller is a module built into a 16-bit microcontroller (F2MC-16LX). The CAN
(Controller Area Network) is the standard protocol for serial communication between
automobile controllers and is widely used in industrial applications.
■ Features of CAN Controller
The CAN controller has the following features:
● Conforms to CAN Specification Version 2.0 Part A and B
Supports transmission/reception in standard frame and extended frame formats
● Supports transmitting of data frames by receiving remote frames
● 16 transmitting/receiving message buffers
29-bit ID and 8-byte data
Multi-level message buffer configuration
● Supports full-bit comparison, full-bit mask and partial bit mask filtering.
Two acceptance mask registers in either standard frame format or extended frame formats
● Bit rate programmable from 10 Kbps to 1 Mbps (A minimum 8 MHz machine clock is required if 1 Mbps
is used)
410
CHAPTER 22 CAN CONTROLLER
22.2
Block Diagram of CAN Controller
Figure 22.2-1 shows a block diagram of the CAN controller.
■ Block Diagram of CAN Controller
Figure 22.2-1 Block Diagram of CAN Controller
TQ (Operating clock)
F2MC-16LX bus
Prescaler
1 to 64 frequency division
Clock
Bit timing generation
SYNC, TSEG1, TSEG2
PSC
TS1
BTR
TS2
RSJ
TOE
TS
RS
CSR
HALT
NIE
NT
Node status change
interrupt generation
IDLE, INT, SUSPND,
transmit, receive,
ERR, OVRLD
Bus state
machine
Node status
change interrupt
NS1, 0
Error
control
RTEC
Transmitting/receiving
sequencer
BVALR
TREQR
TBFx, clear
Transmitting
buffer X decision
TBFx
Data
counter
Error frame
generation
Acceptance
filter control
Overload
frame
generation
TDLC RDLC
TBFx
IDSEL
BITER, STFER,
CRCER, FRMER,
ACKER
TCANR
Output
driver
ARBLOST
TX
TRTRR
TCR
Stuffing
Transmission
shift register
RFWTR
TBFx, set, clear
Transmission
complete
interrupt
Transmission complete
interrupt generation
TDLC
TIER
CRC
generation
ACK
generation
CRCER
RBFx, set
RDLC
RCR
Reception
complete
interrupt
Reception complete
interrupt generation
RIER
RBFx, TBFx, set, clear
CRC generation/error
check
Receive shift
register
STFER
Destuffing/stuffing
error check
RRTRR
RBFx, set
IDSEL
ROVRR
ARBLOST
AMSR
AMR0
0
1
Acceptance
filter
Receiving buffer x
decision
BITER
Bit error
check
ACKER
Acknowledgment
error check
AMR1
IDR0 to IDR15
DLCR0 to
DLCR15
DTR0 to DTR15
RAM
RBFx
RAM address
generation
Arbitration
check
FRMER
Form error
check
PH1
Input
latch
RX
RBFx, TBFx, RDLC, TDLC, IDSEL
LEIR
LDER
411
CHAPTER 22 CAN CONTROLLER
22.3
List of Overall Control Registers
Table 22.3-1 lists overall control registers.
■ List of Overall Control Registers
Table 22.3-1 List of Overall Registers (1 / 2)
Address
Register
Abbreviation
Access
Initial value
CAN1
000080H
000081H
000082H
000083H
000084H
000085H
000086H
000087H
000088H
000089H
00008AH
00008BH
00008CH
00008DH
00008EH
00008FH
003900H
003901H
003902H
003903H
003904H
003905H
003906H
003907H
412
Message buffer
valid register
BVALR
R/W
00000000 00000000B
Transmit request
register
TREQR
R/W
00000000 00000000B
Transmit cancel
register
TCANR
W
00000000 00000000B
Transmit complete
register
TCR
R/W
00000000 00000000B
Receive complete
register
RCR
R/W
00000000 00000000B
Remote request
receiving register
RRTRR
R/W
00000000 00000000B
Receive overrun
register
ROVRR
R/W
00000000 00000000B
Receive interrupt
enable register
RIER
R/W
00000000 00000000B
Control status
register
CSR
R/W, R
00---000 0----0-1B
Last event
indicator register
LEIR
R/W
-------- 000-0000B
Receive/
transmit
error counter
RTEC
R
00000000 00000000B
Bit timing
register
BTR
R/W
-1111111 11111111B
CHAPTER 22 CAN CONTROLLER
Table 22.3-1 List of Overall Registers (2 / 2)
Address
Register
Abbreviation
Access
Initial value
CAN1
003908H
IDE register
IDER
R/W
XXXXXXXX XXXXXXXXB
Transmit RTR
register
TRTRR
R/W
00000000 00000000B
Remote frame receive
waiting
register
RFWTR
R/W
XXXXXXXX XXXXXXXXB
Transmit
TIER
interrupt enable register
R/W
00000000 00000000B
Acceptance mask select AMSR
register
R/W
XXXXXXXX XXXXXXXXB
003909H
00390AH
00390BH
00390CH
00390DH
00390EH
00390FH
003910H
003911H
003912H
XXXXXXXX XXXXXXXXB
003913H
003914H
003915H
Acceptance mask
register 0
AMR0
R/W
003916H
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
003917H
003918H
003919H
00391AH
Acceptance mask
register 1
AMR1
R/W
XXXXXXXX XXXXXXXXB
XXXXX--- XXXXXXXXB
00391BH
413
CHAPTER 22 CAN CONTROLLER
22.4
List of Message Buffers (ID Registers)
Table 22.4-1 lists message buffers (ID registers).
■ List of Message Buffers (ID Registers)
Table 22.4-1 List of Message Buffers (ID Registers) (1 / 3)
Address
Register
Abbreviation
Access
Initial value
CAN1
003800H
to
00381FH
Generalpurpose RAM
-
R/W
XXXXXXXXB
to
XXXXXXXXB
003820H
ID register 0
IDR0
R/W
XXXXXXXX XXXXXXXXB
003821H
003822H
XXXXX--- XXXXXXXXB
003823H
003824H
ID register 1
IDR1
R/W
XXXXXXXX XXXXXXXXB
003825H
003826H
XXXXX--- XXXXXXXXB
003827H
003828H
ID register 2
IDR2
R/W
XXXXXXXX XXXXXXXXB
003829H
00382AH
XXXXX--- XXXXXXXXB
00382BH
00382CH
ID register 3
IDR3
R/W
XXXXXXXX XXXXXXXXB
00382DH
00382EH
XXXXX--- XXXXXXXXB
00382FH
003830H
ID register 4
IDR4
R/W
XXXXXXXX XXXXXXXXB
003831H
003832H
003833H
414
XXXXX--- XXXXXXXXB
CHAPTER 22 CAN CONTROLLER
Table 22.4-1 List of Message Buffers (ID Registers) (2 / 3)
Address
Register
Abbreviation
Access
Initial value
CAN1
003834H
ID register 5
IDR5
R/W
XXXXXXXX XXXXXXXXB
003835H
003836H
XXXXX--- XXXXXXXXB
003837H
003838H
ID register 6
IDR6
R/W
XXXXXXXX XXXXXXXXB
003839H
00383AH
XXXXX--- XXXXXXXXB
00383BH
00383CH
ID register 7
IDR7
R/W
XXXXXXXX XXXXXXXXB
00383DH
00383EH
XXXXX--- XXXXXXXXB
00383FH
003840H
ID register 8
IDR8
R/W
XXXXXXXX XXXXXXXXB
003841H
003842H
XXXXX--- XXXXXXXXB
003843H
003844H
ID register 9
IDR9
R/W
XXXXXXXX XXXXXXXXB
003845H
003846H
XXXXX--- XXXXXXXXB
003847H
003848H
ID register 10
IDR10
R/W
XXXXXXXX XXXXXXXXB
003849H
00384AH
XXXXX--- XXXXXXXXB
00384BH
00384CH
ID register 11
IDR11
R/W
XXXXXXXX XXXXXXXXB
00384DH
00384EH
XXXXX--- XXXXXXXXB
00384FH
415
CHAPTER 22 CAN CONTROLLER
Table 22.4-1 List of Message Buffers (ID Registers) (3 / 3)
Address
Register
Abbreviation
Access
Initial value
CAN1
003850H
ID register 12
IDR12
R/W
XXXXXXXX XXXXXXXXB
003851H
003852H
XXXXX--- XXXXXXXXB
003853H
003854H
ID register 13
IDR13
R/W
XXXXXXXX XXXXXXXXB
003855H
003856H
XXXXX--- XXXXXXXXB
003857H
003858H
ID register 14
IDR14
R/W
XXXXXXXX XXXXXXXXB
003859H
00385AH
XXXXX--- XXXXXXXXB
00385BH
00385CH
ID register 15
IDR15
R/W
XXXXXXXX XXXXXXXXB
00385DH
00385EH
00385FH
416
XXXXX--- XXXXXXXXB
CHAPTER 22 CAN CONTROLLER
22.5
List of Message Buffers (DLC Registers and Data Registers)
Table 22.5-1 lists message buffers (DLC registers) and message buffers (data registers).
■ List of Message Buffers (DLC Registers and Data Registers)
Table 22.5-1 List of Message Buffers (DLC Registers and Data Register) (1 / 3)
Address
Register
Abbreviation
Access
Initial value
CAN1
003860H
DLC register 0
DLCR0
R/W
----XXXXB
DLC register 1
DLCR1
R/W
----XXXXB
DLC register 2
DLCR2
R/W
----XXXXB
DLC register 3
DLCR3
R/W
----XXXXB
DLC register 4
DLCR4
R/W
----XXXXB
DLC register 5
DLCR5
R/W
----XXXXB
DLC register 6
DLCR6
R/W
----XXXXB
DLC register 7
DLCR7
R/W
----XXXXB
DLC register 8
DLCR8
R/W
----XXXXB
DLC register 9
DLCR9
R/W
----XXXXB
DLC register 10
DLCR10
R/W
----XXXXB
DLC register 11
DLCR11
R/W
----XXXXB
003861H
003862H
003863H
003864H
003865H
003866H
003867H
003868H
003869H
00386AH
00386BH
00386CH
00386DH
00386EH
00386FH
003870H
003871H
003872H
003873H
003874H
003875H
003876H
003877H
417
CHAPTER 22 CAN CONTROLLER
Table 22.5-1 List of Message Buffers (DLC Registers and Data Register) (2 / 3)
Address
Register
Abbreviation
Access
Initial value
CAN1
DLC register 12
DLCR12
R/W
----XXXXB
DLC register 13
DLCR13
R/W
----XXXXB
DLC register 14
DLCR14
R/W
----XXXXB
DLC register 15
DLCR15
R/W
----XXXXB
003880H
to
003887H
Data register 0
(8 bytes)
DTR0
R/W
XXXXXXXXB
to
XXXXXXXXB
003888H
to
00388FH
Data register 1
(8 bytes)
DTR1
R/W
XXXXXXXXB
to
XXXXXXXXB
003890H
to
003897H
Data register 2
(8 bytes)
DTR2
R/W
XXXXXXXXB
to
XXXXXXXXB
003898H
to
00389FH
Data register 3
(8 bytes)
DTR3
R/W
XXXXXXXXB
to
XXXXXXXXB
0038A0H
to
0038A7H
Data register 4
(8 bytes)
DTR4
R/W
XXXXXXXXB
to
XXXXXXXXB
0038A8H
to
0038AFH
Data register 5
(8 bytes)
DTR5
R/W
XXXXXXXXB
to
XXXXXXXXB
0038B0H
to
0038B7H
Data register 6
(8 bytes)
DTR6
R/W
XXXXXXXXB
to
XXXXXXXXB
0038B8H
to
0038BFH
Data register 7
(8 bytes)
DTR7
R/W
XXXXXXXXB
to
XXXXXXXXB
0038C0H
to
0038C7H
Data register 8
(8 bytes)
DTR8
R/W
XXXXXXXXB
to
XXXXXXXXB
003878H
003879H
00387AH
00387BH
00387CH
00387DH
00387EH
00387FH
418
CHAPTER 22 CAN CONTROLLER
Table 22.5-1 List of Message Buffers (DLC Registers and Data Register) (3 / 3)
Address
Register
Abbreviation
Access
Initial value
CAN1
0038C8H
to
0038CFH
Data register 9
(8 bytes)
DTR9
R/W
XXXXXXXXB
to
XXXXXXXXB
0038D0H
to
0038D7H
Data register 10 (8
bytes)
DTR10
R/W
XXXXXXXXB
to
XXXXXXXXB
0038D8H
to
0038DFH
Data register 11
(8 bytes)
DTR11
R/W
XXXXXXXXB
to
XXXXXXXXB
0038E0H
to
0038E7H
Data register 12
(8 bytes)
DTR12
R/W
XXXXXXXXB
to
XXXXXXXXB
0038E8H
to
0038EFH
Data register 13
(8 bytes)
DTR13
R/W
XXXXXXXXB
to
XXXXXXXXB
0038F0H
to
0038F7H
Data register 14
(8 bytes)
DTR14
R/W
XXXXXXXXB
to
XXXXXXXXB
0038F8H
to
0038FFH
Data register 15
(8 bytes)
DTR15
R/W
XXXXXXXXB
to
XXXXXXXXB
419
CHAPTER 22 CAN CONTROLLER
22.6
Classifying the CAN Controller Registers
There are three types of CAN controller registers:
• Overall control registers
• Message buffer control registers
• Message buffers
■ Overall Control Registers
The overall control registers are the following four registers:
• Control status register (CSR)
• Last event indicator register (LEIR)
• Receive and transmit error counter (RTEC)
• Bit timing register (BTR)
■ Message Buffer Control Registers
The message buffer control registers are the following 14 registers:
• Message buffer valid register (BVALR)
• IDE register (IDER)
• Transmission request register (TREQR)
• Transmission RTR register (TRTRR)
• Remote frame receiving wait register (RFWTR)
• Transmission cancel register (TCANR)
• Transmission complete register (TCR)
• Transmission interrupt enable register (TIER)
• Reception complete register (RCR)
• Remote request receiving register (RRTRR)
• Receive overrun register (ROVRR)
• Reception interrupt enable register (RIER)
• Acceptance mask select register (AMSR)
• Acceptance mask registers 0 and 1 (AMR0 and AMR1)
■ Message Buffers
The message buffers are the following three registers:
• ID register x (x = 0 to 15) (IDRx)
• DLC register x (x = 0 to 15) (DLCRx)
• Data register x (x = 0 to 15) (DTRx)
420
CHAPTER 22 CAN CONTROLLER
22.6.1
Control Status Register (CSR)
Control status register (CSR) is prohibited from executing any bit manipulation
instructions (read-modify-write instructions).
■ Control Status Register (CSR) (Lower)
Figure 22.6-1 Configuration of the Control Status Register (CSR) (Lower Byte)
Address:
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
CAN1: 003900 H
TOE
-
-
-
-
NIE
R/W
-
-
-
-
R/W W R/W
Reserved
HALT
Initial value
0XXXX0X1 B
HALT
0
1
Write: Stops bus operation
Read: Bus operation in stop mode
Reserved
0
NIE
R/W
: Readable/writable
W
: Write only
X
:Undefined value
-
:Undefined
Bus operation stop bit
Write: Cancels bus operation stop
Read: Bus operation not in stop mode
Reserved bit
Do not write "1" to this bit
Node status transition interrupt enable bit
0
Node status transition interrupt enabled
1
Node status transition interrupt disabled
TOE
Transmit output enable bit
0
General-purpose port pin
1
Transmit pin of CAN controller
: Initial value
421
CHAPTER 22 CAN CONTROLLER
■ Control Status Register (CSR) (Lower) Contents
Table 22.6-1 Function of Each Bit of the Control Status Register (CSR) (Lower)
Bit name
Function
bit7
TOE:
Transmit output
enable bit
Writing "1" to this bit switches from a general-purpose port pin to a transmit pin of the
CAN controller.
0: General-purpose port pin
1: Transmit pin of CAN controller
bit6 to bit3
Undefined
bit2
NIE:
Node status
transition
interrupt enable
bit
This bit enables or disables a node status transition interrupt (when NT = 1).
0: Node status transition interrupt disabled
1: Node status transition interrupt enabled
bit1
Reserved bit
This is a reserved bit. Do not write "1" to this bit.
bit0
HALT:
Bus operation
stop bit
This bit controls the bus halt. The halt state of the bus can be checked by reading this
bit.
Writing to this bit
0: Cancels bus halt
1: Halt bus
Reading this bit
0: Bus operation not in stop state
1: Bus operation in stop state
Note :
Before writing "0" to this bit while node status is "Bus off", make sure that this bit is
"1".
Example program:
switch ( IO_CANCT0.CSR.bit.NS )
{
case 0 : /* error active */
break;
case 1 : /* warning */
break;
case 2 : /* error passive */
break;
default : /* bus off */
for ( i=0; ( i <= 500 ) && ( IO_CANCT0.CSR.bit.HALT == 0); i++);
IO_CANCT0.CSR.word = 0x0084; /* HALT = 0 */
break;
}
* The variable "i" is used for fail-safe.
422
CHAPTER 22 CAN CONTROLLER
■ Control Status Register (CSR) (Upper)
Figure 22.6-2 Configuration of the Control Status Register (CSR) (Upper Byte)
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
CAN1: 003901 H
TS RS
R
R
-
-
-
-
-
-
NT NS1 NS0
R/W R
Initial value
00XXX000 B
R
NS1
0
1
Warning (error active)
1
0
Error passive
1
1
Bus off
Node status transition flag bit
No change
1
Status changed
Receive status bit
0
Message not being received
1
Message being received
TS
Readable/writable
Read only
Undefined value
Undefined
Initial value
Error active
0
RS
:
:
:
:
:
Node status bits
0
NT
R/W
R
X
-
NS0
0
Tr ansmit status bit
0
Message not being transmitted
1
Message being transmitted
423
CHAPTER 22 CAN CONTROLLER
■ Control Status Register (CSR-upper) Contents
Table 22.6-2 Function of Each Bit of the Control Status Register (Upper)
Bit Name
Function
bit15
TS:
Transmit status
bit
This bit indicates whether a message is being transmitted.
0: Message not being transmitted
1: Message being transmitted
This bit is "0" even while error and overload frames are transmitted.
bit14
RS:
Receive status bit
This bit indicates whether a message is being received.
0: Message not being received
1: Message being received
While a message is on the bus, this bit becomes "1". Therefore, this bit is also "1" while
a message is being transmitted. This bit does not necessarily indicates whether a
receiving message passes through the acceptance filter.
As a result, when this bit is "0", it implies that the bus operation is stopped (HALT = 0);
the bus is in the intermission/bus idle or a error/overload frame is on the bus.
bit13 to
bit11
Undefined
bit10
NT:
Node status
transition flag bit
If the node status is changed to increment, or from Bus Off to Error Active, this bit is
set to "1".
In other words, the NT bit is set to "1" if the node status is changed from Error Active
(00) to Warning (01), from Warning (01) to Error Passive (10), from Error Passive (10)
to Bus Off (11), and from Bus Off (11) to Error Active (00). Numbers in parentheses
indicate the values of NS1 and NS0 bits.
When the node status transition interrupt enable bit (NIE) is "1", an interrupt is
generated. Writing "0" sets the NT bit to "0". Writing "1" to the NT bit is ignored. "1" is
read when a Read Modify Write instruction is performed.
bit9, bit8
NS1, NS0:
Node status bits 1
These bits indicate the current node status.
See Table 22.6-3 below for details.
−
Table 22.6-3 Correspondence between NS1 and NS0 and Node Status
NS1
NS0
Node Status
0
0
Error active
0
1
Warning (error active)
1
0
Error passive
1
1
Bus off
Note:
Warning (error active) is included in the error active in CAN Specification 2.0B for the node status,
however, indicates that the transmit error counter or receive error counter has exceeded 96. The node
status change diagram is shown in Figure 22.6-3.
424
CHAPTER 22 CAN CONTROLLER
Figure 22.6-3 Node Status Transition Diagram
Hardware reset
REC: Receive error counter
TEC: Transmit error counter
Error active
After 0 has been writtentothe HALT bit of
the register (CSR), continuous 11-bit "H"
levels (recessive bits) are input 128 times
to the receive input pin (RX).
REC >= 96
or
TEC >= 96
REC < 96
and
TEC < 96
Warning
(Error active)
REC >= 128
or
TEC >= 128
REC < 128
and
TEC < 128
Error passive
TEC >= 256
Bus off
(HALT =1)
425
CHAPTER 22 CAN CONTROLLER
22.6.2
Bus Operation Stop Bit (HALT = 1)
The bus operation stop bit sets or cancels stopping of bus operation, or indicates its
status
■ Conditions for Setting Bus Operation Stop (HALT=1)
There are three conditions for setting bus operation stop (HALT = 1):
• After hardware reset
• When node status changed to bus off
• By writing "1" to HALT
Note:
The bus operation should be stopped by writing "1" to HALT before the F2MC-16LX is changed in
low-power consumption mode (stop mode and timebase timer mode).
If transmission is in progress when "1" is written to HALT, the bus operation is stopped (HALT = 1)
after transmission is terminated. If reception is in progress when "1" is written to HALT, the bus
operation is stopped immediately (HALT = 1). If received messages are being stored in the message
buffer (x), stop the bus operation (HALT = 1) after storing the messages.
To check whether the bus operation has stopped, always read the HALT bit.
■ Conditions for Canceling Bus Operation Stop (HALT = 0)
• By writing "0" to HALT
Notes:
• Canceling the bus operation stop after hardware reset or by writing "1" to HALT as above conditions
is performed after "0" is written to HALT and continuous 11-bit "H" levels (recessive bits) have been
input to the receive input pin (RX) (HALT = 0).
• Canceling the bus operation stop when the node status is changed to bus off as above conditions is
performed after "0" is written to HALT and continuous 11-bit "H" levels (recessive bits) have been
input 128 times to the receive input pin (RX) (HALT = 0). Then, the values of both transmit and
receive error counters reach "0" and the node status is changed to error active.
• When write "0" to HALT during the node status is Bus Off, ensure that "1" is written to this bit.
■ State during Bus Operation Stop (HALT = 1)
• The bus does not perform any operation, such as transmission and reception.
• The transmit output pin (TX) outputs a "H" level (recessive bit).
• The values of other registers and error counters are not changed.
Note:
The bit timing register (BTR) should be set during bus operation stop (HALT = 1).
426
CHAPTER 22 CAN CONTROLLER
22.6.3
Last Event Indicator Register (LEIR)
This register indicates the last event.
The NTE, TCE, and RCE bits are exclusive. When the corresponding bit of the last event
is set to "1", other bits are set to "0"s.
■ Last Event Indicator Register (LEIR)
Figure 22.6-4 Configuration of the Last Event Indicator Register (LEIR)
Address:
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
CAN1: 003902 H
NTE
RCE
-
MBP3 MBP2 MBP1 MBP0
R/W R/W R/W
-
R/W R/W R/W R/W
TCE
Initial value
000X0000 B
MBP3 MBP2 MBP1 MBP0
Message buffer pointer bits
0 to 15 (initial value: "0000B")
RCE
Receive completion event bit
Read
WriteIgnored
0
-
Clear bit
1
Receive completion
Ignored
Transmit completion event bit
TCE
Read
Write
0
-
Clear bit
1
Transmit completion
Ignored
Node status transition event bit
NTE
Read
R/W
:
Readable/writable
0
X
:
Undefined value
1
-
:
Undefined
:
Initial value
Write
-
Transition event
Clear bit
Ignored
427
CHAPTER 22 CAN CONTROLLER
■ Last Event Indicator Register (LEIR) Contents
Table 22.6-4 Function of Each Bit of the Last Event Indicator Register
Bit name
Function
bit7
NTE:
Node status
transition event
bit
When this bit is "1", node status transition is the last event.
This bit is set to "1" at the same time the NT bit of the control status register (CSR) is
set.
This bit is also set to "1" irrespective of the setting of the node status transition interrupt
enable bit (NIE) of CSR.
0: Writing "0" to this bit sets the NTE bit to "0". Writing "1" to this bit is ignored.
1: "1" is read when a read modify write instruction is executed.
bit6
TCE:
Transmit
completion event
bit
When this bit is "1", it indicates that transmit completion is the last event.
This bit is set to "1" at the same time as any one of the bits of the transmit completion
register (TCR). This bit is also set to "1", irrespective of the settings of the bits of the
transmit interrupt enable register (TIER).
0: Writing "0" sets this bit to "0". Writing "1" to this bit is ignored.
"1" is read when a read modify write instruction is performed.
1: When this bit is set to "1", the MBP3 to MBP0 bits are used to indicate the message
buffer number completing the transmit operation.
bit5
RCE:
Receive
completion event
bit
When this bit is "1", it indicates that receive completion is the last event.
This bit is set to "1" at the same time as any one of the bits of the receive complete
register (RCR). This bit is also set to "1" irrespective of the settings of the bits of the
receive interrupt enable register (RIER).
0: Writing "0" sets this bit to "0". Writing "1" to this bit is ignored.
"1" is read when a read modify write instruction is performed.
1: When this bit is set to "1", the MBP3 to MBP0 bits are used to indicate the message
buffer number completing the receive operation.
bit4
Undefined
bit3 to bit0
MBP3 to MBP0:
message buffer
pointer bits
428
When the TCE or RCE bit is set to "1", these bits indicate the corresponding numbers of
the message buffers (0 to 15). If the NTE bit is set to "1", these bits have no meaning.
0: Writing "0" sets these bits to 0s. Writing "1" to these bits is ignored.
1: "1"s are read when a read modify write instruction is performed.
If LEIR is accessed within an CAN interrupt handler, the event causing the interrupt is
not necessarily the same as indicated by LEIR. In the time from interrupt request to the
LEIR access by the interrupt handler there may occur other CAN events.
CHAPTER 22 CAN CONTROLLER
22.6.4
Receive and Transmit Error Counters (RTEC)
The receive and transmit error counters indicate the counts for transmission errors and
reception errors defined in the CAN specifications. These registers can only be read.
■ Receive and Transmit Error Counters (RTEC)
Figure 22.6-5 Configuration of the Receive and Transmit Error Counters (RTEC)
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
(upper)
CAN1: 003905 H
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
Initial value
00000000 B
R
Address:
R
R
R
R
R
R
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
CAN1: 003904 H
REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
R
R
R
R
R
R
R
R
R
R
(lower)
Initial value
00000000 B
: Read only
■ Receive and Transmit Error Counters (RTEC) Contents
Table 22.6-5 Function of Each Bit of the Receive and Transmit Error Counters (RTEC)
Bit name
Function
bit15 to bit8
TEC7 to TEC0:
Transmit error
counter bits
These are transmit error counters.
TEC7 to TEC0 values indicate 0 to 7 when the counter value is more than 256,
and the subsequent increment is not counted for counter value. In this case, bus off
is indicated for the node status (NS1 and NS0 of control status register CSR = 11).
bit7 to bit0
REC7 to REC0:
Receive error
counter bits
These are receive error counters.
REC7 to REC0 values indicate 0 to 7 when the counter value is more than 256,
and the subsequent increment is not counted for counter value. In this case, error
passive is indicated for the node status (NS1 and NS0 of control status register
CSR = 10).
429
CHAPTER 22 CAN CONTROLLER
22.6.5
Bit Timing Register (BTR)
Bit timing register (BTR) stores the prescaler and bit timing setting.
■ Bit Timing Register (BTR)
Figure 22.6-6 Configuration of the Bit Timing Register (BTR)
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
CAN1: 003907 H
Address:
-
TS2.2 TS2.1 TS2.0 TS1.3 TS1.2 TS1.1 TS1.0
-
R/W R/W R/W R/W R/W R/W R/W
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
CAN1: 003906 H
RSJ1 RSJ0 PSC5 PSC4 PSC3 REC2 PSC1 PSC0
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
-
(upper)
Initial value
X1111111B
(lower)
Initial value
11111111 B
: Readable/writable
: Undefined
Note:
This register should be set during bus operation stop (HALT = 1).
■ Bit Timing Register (BTR) Contents
Table 22.6-6 Function of Each Bit of the Bit Timing Register (BTR)
Bit name
Function
bit15
Undefined
bit14 to
bit12
TS2.2 to TS2.0:
Time segment2
setting bits
These bits define the number of the time quanta (TQ’s) for the time segment 2
(TSEG2). The time segment 2 is equal to the phase buffer segment 2 (PHASE_SEG2)
in the CAN specification.
bit11 to
bit8
TS1.3 to TS1.0:
Time segment1
setting bits
These bits define the number of the time quanta (TQ’s) for the time segment 1
(TSEG1). The time segment 1 is equal to the propagation segment (PROP_SEG) +
phase buffer segment 1 (PHASE_SEG1) in the CAN specification.
bit7, bit6
RSJ1, RSJ0:
Resynchronization
jump width setting
bits
These bits define the number of the time quanta (TQ’s) for the resynchronization jump
width.
bit5 to bit0
PSC5 to PSC0:
Prescaler setting
bits
These bits define the time quanta (TQ) of the CAN controller. (see below for details.)
430
-
CHAPTER 22 CAN CONTROLLER
■ Prescaler Settings
The bit time segments defined in the CAN specification, and the CAN controller are shown in Figure
22.6-7 and Figure 22.6-8 respectively.
Figure 22.6-7 Bit Time Segment in CAN Specification
Nominal bit time
SYNC_SEG
PROP_SEG
PHASE_SEG1 PHASE_SEG2
Sample point
Figure 22.6-8 Bit Time Segment in CAN Controller
Nominal bit time
SYNC_SEG
TSEG1
TSEG2
Sample point
The relationship between PSC = PSC5 to PSC0, TS1 = TS1.3 to TS1.0, TS2 = TS2.2 to TS1.0, and RSJ =
RSJ1 and RSJ0 when the input clock (CLK), time quanta (TQ), bit time (BT), synchronous segment
(SYNC_SEG), time segment 1 and 2 (TSEG1 and TSEG2), and resynchronization jump width [(RSJ1 and
RSJ0) +1] frequency division is shown below.
The input clock is supplied with the machine clock.
TQ
BT
= (PSC + 1) x CLK
= SYNC_SEG + TSEG1 + TSEG2
= (1 + (TS1 + 1) + (TS2 +1)) x TQ
= (3 + TS1 +TS2) x TQ
RSJW = (RSJ + 1) x TQ
For correct operation, the following conditions should be met.
For 1
PSC
TSEG1
TSEG1
TSEG2
TSEG2
For PSC = 0:
TSEG1
TSEG2
TSEG2
63:
2TQ
RSJW
2TQ
RSJW
5TQ
2TQ
RSJW
In order to meet the bit timing requirements defined in the CAN specification, additions have to be met,
e.g. the propagation delay has to be considered.
431
CHAPTER 22 CAN CONTROLLER
22.6.6
Message Buffer Valid Register (BVALR)
Message buffer valid register (BVALR) stores the validity of the message buffers or
displays their state.
■ Message Buffer Valid Register (BVALR)
Figure 22.6-9 Configuration of the Message Buffer Valid Register (BVALR)
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
(upper)
CAN1: 000081 H
BVAL15 BVAL14 BVAL13 BVAL12 BVAL11 BVAL10 BVAL9 BVAL8
Initial value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
(lower)
CAN1: 000080 H
BVAL7 BVAL6 BVAL5 BVAL4 BVAL3 BVAL2 BVAL1 BVAL0
Initial value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
: Readable/writable
0: Message buffer (x) invalid
1: Message buffer (x) valid
If the message buffer (x) is set to invalid, it will not transmit or receive messages.
If the buffer is set to invalid during transmission operating, it becomes invalid (BVALx = 0) after the
transmission is completed or terminated by an error.
If the buffer is set to invalid during reception operating, it immediately becomes invalid (BVALx = 0). If
received messages are stored in a message buffer (x), the message buffer (x) is invalid after storing the
messages.
Note:
x indicates a message buffer number (x = 0 to 15).
When invaliding a message buffer (x) by writing "0" to a bit (BVALx), execution of a bit manipulation
instruction is prohibited until the bit is set to "0".
To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while the CAN controller is
operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN controller
is operating for CAN bus communication to enable transmission and reception), follow the procedure in
Section "22.15 Precautions when Using CAN Controller".
432
CHAPTER 22 CAN CONTROLLER
22.6.7
IDE Register (IDER)
This register stores the frame format used by the message buffers (x) during
transmission/reception.
■ IDE Register (IDER)
Figure 22.6-10 Configuration of the IDE Register (IDER)
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
(upper)
CAN1: 003909 H
IDE15 IDE14 IDE13 IDE12 IDE11 IDE10 IDE9 IDE8
Initial value
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
(lower)
CAN1: 003908 H
IDE7 IDE6 IDE5 IDE4 IDE3 IDE2
Initial value
XXXXXXXX B
IDE1 IDE0
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
: Readable/writable
0: The standard frame format (ID11 bit) is used for the message buffer (x).
1: The extended frame format (ID29 bit) is used for the message buffer (x).
Note:
This register should be set when the message buffer (x) is invalid (BVALx of the message buffer valid
register (BVALR) = 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received
messages to be stored.
To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while the CAN controller is
operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN controller
is operating for CAN bus communication to enable transmission and reception), follow the procedure in
Section "22.15 Precautions when Using CAN Controller".
433
CHAPTER 22 CAN CONTROLLER
22.6.8
Transmission Request Register (TREQR)
Transmission request register (TREQR) stores transmission requests to the message
buffers (x) or displays their state.
■ Transmission Request Register (TREQR)
Figure 22.6-11 Configuration of the Transmission Request Register (TREQR)
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
(upper)
CAN1: 000083 H
TREQ15 TREQ14 TREQ13 TREQ12 TREQ11 TREQ10 TREQ9 TREQ8
Initial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
(lower)
CAN1: 000082 H
TREQ7 TREQ6 TREQ5 TREQ4 TREQ3 TREQ2 TREQ1 TREQ0
Initial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
: Readable/writable
When "1" is written to TREQx, transmission to the message buffer (x) starts. If RFWTx of the remote
frame receiving wait register (RFWTR) *1 is "0", transmission starts immediately. However, if RFWTx = 1,
transmission starts after waiting until a remote frame is received (RRTRx of the remote request receiving
register (RRTRR)*1 becomes "1"). Transmission starts
is already "1" when "1" is written to TREQx.
*2
immediately even when RFWTx = 1, if RRTRx
*1: For RFWTR and TRTRR, see Figure 22.6-12 and Figure 22.6-13.
*2: For cancellation of transmission, see Figure 22.6-14 and Figure 22.6-15.
Writing "0" to TREQx is ignored.
"0" is read when a Read Modify Write instruction is performed.
If clearing (to "0") at completion of the transmit operation and setting by writing "1" are concurrent,
clearing is preferred.
If "1" is written to more than one bit, transmission is performed, starting with the lower-numbered message
buffer (x).
TREQx is "1" while transmission is pending, and becomes "0" when transmission is completed or canceled.
434
CHAPTER 22 CAN CONTROLLER
22.6.9
Transmission RTR Register (TRTRR)
This register stores the RTR (Remote Transmission Request) bits for the message
buffers (x).
■ Transmission RTR Register (TRTRR)
Figure 22.6-12 Configuration of the Transmission RTR Register (TRTRR)
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
(upper)
CAN1: 00390B H
TRTR15 TRTR14 TRTR13 TRTR12 TRTR11 TRTR10 TRTR9 TRTR8
Initial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
CAN1: 00390AH
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
(lower)
TRTR7 TRTR6 TRTR5 TRTR4 TRTR3 TRTR2 TRTR1 TRTR0
Initial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
: Readable/writable
0: Data frame.
1: Remote frame.
435
CHAPTER 22 CAN CONTROLLER
22.6.10
Remote Frame Receiving Wait Register (RFWTR)
Remote frame receiving wait register (RFWTR) stores the conditions for starting
transmission when a request for data frame transmission is set (TREQx of the
transmission request register (TREQR) is "1" and TRTRx of the transmitting RTR
register (TRTRR) is "0").
• 0: Transmission starts immediately.
• 1: Transmission starts after waiting until remote frame received (RRTRx of remote
request receiving register (RRTRR) becomes "1").
■ Remote Frame Receiving Wait Register (RFWTR)
Figure 22.6-13 Configuration of the Remote Frame Receiving Wait Register (RFWTR)
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
(upper)
CAN1: 00390DH
RFWT15 RFWT14 RFWT13 RFWT12 RFWT11 RFWT10 RFWT9 RFWT8
Initial value
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
(lower)
CAN1: 00390CH
RFWT7 RFWT6 RFWT5 RFWT4 RFWT3 RFWT2 RFWT1 RFWT0
Initial value
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
: Readable/writable
Note:
Transmission starts immediately if RRTRx was already "1" when a request for transmission is set.
For remote frame transmission, do not set RFWTx to "1".
436
CHAPTER 22 CAN CONTROLLER
22.6.11
Transmission Cancel Register (TCANR)
When "1" is written to TCANx, this register cancels a pending request for transmission
to the message buffer (x).
At completion of cancellation, TREQx of the transmission request register (TREQR)
becomes "0". Writing "0" to TCANx is ignored.
This is a write-only register and its read value is always "0".
■ Transmission Cancel Register (TCANR)
Figure 22.6-14 Configuration of the Transmission Cancel Register (TCANR)
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
(upper)
CAN1: 000085 H
TCAN15 TCAN14 TCAN13 TCAN12 TCAN11 TCAN10 TCAN9 TCAN8
Initial value
00000000 B
W
Address:
CAN1: 000084 H
W
W
W
W
W
W
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
TCAN7 TCAN6 TCAN5 TCAN4 TCAN3 TCAN2 TCAN1 TCAN0
W
W
W
W
W
W
W
W
W
(lower)
Initial value
00000000 B
W
: Write only
437
CHAPTER 22 CAN CONTROLLER
22.6.12
Transmission Complete Register (TCR)
At completion of transmission by the message buffer (x), the corresponding TCx
becomes "1".
If TIEx of the transmission complete interrupt enable register (TIER) is "1", an interrupt
occurs.
■ Transmission Complete Register (TCR)
Figure 22.6-15 Configuration of the Transmission Complete Register (TCR)
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
(upper)
CAN1: 000087 H
TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8
Initial value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
(lower)
CAN1: 000086 H
TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0
Initial value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
: Readable/writable
● Conditions for TCx = 0
• Write "0" to TCx.
• Write "1" to TREQx of the transmission request register (TREQR).
After the completion of transmission, write "0" to TCx to set it to "0". Writing "1" to TCx is ignored.
"1" is read when a Read Modify Write instruction is performed.
Note:
If setting to "1" by completion of the transmit operation and clearing to "0" by writing occur at the same
time, the bit is set to "1".
438
CHAPTER 22 CAN CONTROLLER
22.6.13
Transmission Interrupt Enable Register (TIER)
This register enables or disables the transmission interrupt by the message buffer (x).
The transmission interrupt is generated at transmission completion (when TCx of the
transmission complete register (TCR) is "1").
■ Transmission Interrupt Enable Register (TIER)
Figure 22.6-16 Configuration of the Transmission Interrupt Enable Register (TIER)
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
(upper)
CAN1: 00390F H
TIE15 TIE14 TIE13 TIE12 TIE11 TIE10 TIE9 TIE8
Initial value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
(lower)
CAN1: 00390EH
TIE7 TIE6 TIE5 TIE4 TIE3 TIE2
Initial value
00000000 B
TIE1 TIE0
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
: Readable/writable
0: Transmission interrupt disabled.
1: Transmission interrupt enabled.
439
CHAPTER 22 CAN CONTROLLER
22.6.14
Reception Complete Register (RCR)
At completion of storing received message in the message buffer (x), RCx becomes "1".
If RIEx of the reception complete interrupt enable register (RIER) is "1", an interrupt
occurs.
■ Reception Complete Register (RCR)
Figure 22.6-17 Configuration of the Reception Complete Register (RCR)
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
(upper)
CAN1: 000089 H
RC15 RC14 RC13 RC12 RC11 RC10 RC9
Initial value
00000000 B
RC8
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
CAN1: 000088 H
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
(lower)
Initial value
00000000 B
: Readable/writable
● Conditions for RCx = 0
Write "0" to RCx.
After completion of handling received message, write "0" to RCx to set it to "0". Writing "1" to RCx is
ignored.
"1" is read when a Read Modify Write instruction is performed.
Note:
If setting to "1" by completion of the receive operation and clearing to "0" by writing occur at the same
time, the bit is set to "1".
440
CHAPTER 22 CAN CONTROLLER
22.6.15
Remote Request Receiving Register (RRTRR)
After a remote frame is stored in the message buffer (x), RRTRx becomes "1" (at the
same time as RCx setting to "1").
■ Remote Request Receiving Register (RRTRR)
Figure 22.6-18 Configuration of the Remote Request Receiving Register (RRTRR)
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
(upper)
CAN1: 00008BH
RRTR15 RRTR14 RRTR13 RRTR12 RRTR11 RRTR10 RRTR9 RRTR8
Initial value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
(lower)
CAN1: 00008AH
RRTR7 RRTR6 RRTR5 RRTR4 RRTR3 RRTR2 RRTR1 RRTR0
Initial value
00000000B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
: Readable/writable
● Conditions for RRTRx = 0
• Write "0" to RRTRx.
• After a received data frame is stored in the message buffer (x) (at the same time as RCx setting to "1").
• Transmission by the message buffer (x) is completed (TCx of the transmission complete register (TCR)
is "1").
Writing "1" to RRTRx is ignored.
"1" is read when a Read Modify Write instruction is performed.
Note:
If setting to "1" by completion of the receive operation and clearing to "0" by writing occur at the same
time, the bit is set to "1".
441
CHAPTER 22 CAN CONTROLLER
22.6.16
Receive Overrun Register (ROVRR)
If RCx of the reception complete register (RCR) is "1" when completing storing of a
received message in the message buffer (x), ROVRx becomes "1", indicating that
reception has overrun.
■ Receive Overrun Register (ROVRR)
Figure 22.6-19 Configuration of the Receive Overrun Register (ROVRR)
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
(upper)
CAN1: 00008DH
ROVR15 ROVR14 ROVR13 ROVR12 ROVR11 ROVR10 ROVR9 ROVR8
Initial value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
CAN1: 00008CH
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ROVR7 ROVR6 ROVR5 ROVR4 ROVR3 ROVR2 ROVR1 ROVR0
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
(lower)
Initial value
00000000 B
: Readable/writable
Writing "0" to ROVRx results in ROVRx = 0. Writing "1" to ROVRx is ignored. After checking that
reception has overrun, write "0" to ROVRx to set it to "0".
"1" is read when a Read Modify Write instruction is performed.
Note:
If setting to "1" by completion of the receive operation and clearing to "0" by writing occur at the same
time, the bit is set to "1".
442
CHAPTER 22 CAN CONTROLLER
22.6.17
Reception Interrupt Enable Register (RIER)
Reception interrupt enable register (RIER) enables or disables the reception interrupt by
the message buffer (x).
The reception interrupt is generated at reception completion (when RCx of the reception
completion register (RCR) is "1").
■ Reception Interrupt Enable Register (RIER)
Figure 22.6-20 Configuration of the Reception Interrupt Enable Register (RIER)
Address:
CAN1: 0000BFH
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
(upper)
RIE15 RIE14 RIE13 RIE12 RIE11 RIE10 RIE9 RIE8
Initial value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
CAN1: 0000BE H
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
(lower)
RIE7 RIE6 RIE5 RIE4 RIE3 RIE2 RIE1 RIE0
Initial value
00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
: Readable/writable
0: Reception interrupt disabled.
1: Reception interrupt enabled.
443
CHAPTER 22 CAN CONTROLLER
22.6.18
Acceptance Mask Select Register (AMSR)
This register selects masks (acceptance mask) for comparison between the received
message ID’s and the message buffer ID’s.
■ Acceptance Mask Select Register (AMSR)
Figure 22.6-21 Configuration of the acceptance Mask Select Register (AMSR)
Address:
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
CAN1: 003910 H
AMS AMS AMS AMS AMS AMS AMS AMS
3.1 3.0 2.1 2.0 1.1 1.0 0.1 0.0
Byte 0
Initial value
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
CAN1: 003911 H
AMS AMS AMS AMS AMS AMS AMS AMS
7.1 7.0 6.1 6.0 5.1 5.0 4.1 4.0
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
CAN1: 003912 H
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
AMS AMS AMS AMS AMS AMS AMS AMS
11.1 11.0 10.1 10.0 9.1 9.0 8.1 8.0
Byte 1
Initial value
XXXXXXXX B
Byte 2
Initial value
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
CAN1: 003913 H
AMS AMS AMS AMS AMS AMS AMS AMS
15.1 15.0 14.1 14.0 13.1 13.0 12.1 12.0
R/W R/W R/W R/W R/W R/W R/W R/W
R/W
Byte 3
Initial value
XXXXXXXX B
: Readable/writable
Table 22.6-7 Selection of acceptance Mask
AMSx.1
AMSx.0
Acceptance mask
0
0
Full-bit comparison
0
1
Full-bit mask
1
0
Acceptance mask register 0 (AMR0)
1
1
Acceptance mask register 1 (AMR1)
Note:
AMSx.1 and AMSx.0 should be set when the message buffer (x) is invalid (BVALx of the message
buffer valid register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause
unnecessary received messages to be stored.
444
CHAPTER 22 CAN CONTROLLER
To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while the CAN controller is
operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN controller
is operating for CAN bus communication to enable transmission and reception), follow the procedure in
Section "22.15 Precautions when Using CAN Controller".
445
CHAPTER 22 CAN CONTROLLER
22.6.19
Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)
There are two acceptance mask registers, AMR0 and AMR1, both of which are available
either in the standard frame format or extended frame format.
AM28 to AM18 (11 bits) are used for acceptance masks in the standard frame format
and AM28 to AM0 (29 bits) are used for acceptance masks in the extended format.
■ Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)
Figure 22.6-22 Configuration of the acceptance Mask Register 0 (AMR0)
Address:
CAN1: 003914 H
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
Byte 0
Initial value
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
CAN1: 003915 H
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
Byte 1
AM20 AM19 AM18 AM17 AM16 AM15 AM14 AM13
Initial value
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
CAN1: 003916 H
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
AM12 AM11 AM10 AM9 AM8 AM7 AM6 AM5
Byte 2
Initial value
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
446
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
CAN1: 003917 H
AM4 AM3 AM2 AM1 AM0
-
-
-
R/W R/W R/W R/W R/W
-
-
-
R/W
:
Readable/writable
X
-
:
:
Undefined value
Undefined
Byte 3
Initial value
XXXXXXXX B
CHAPTER 22 CAN CONTROLLER
Figure 22.6-23 Configuration of the acceptance Mask Register 1 (AMR1)
Address:
CAN1: 003918 H
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
Byte 0
Initial value
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
CAN1: 003919 H
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
AM20 AM19 AM18 AM17 AM16 AM15 AM14 AM13
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
CAN1: 00391AH
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
AM12 AM11 AM10 AM9 AM8 AM7 AM6 AM5
Byte 1
Initial value
XXXXXXXX B
Byte 2
Initial value
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
CAN1: 00391BH
R/W
X
-
:
:
:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
AM4 AM3 AM2 AM1 AM0
-
-
-
R/W R/W R/W R/W R/W
-
-
-
Byte 3
Initial value
XXXXXXXX B
Readable/writable
Undefined value
Undefined
● 0: Compare
Compare the bit of the acceptance code (ID register IDRx for comparing with the received message ID)
corresponding to this bit with the bit of the received message ID. If there is no match, no message is
received.
● 1: Mask
Mask the bit of the acceptance code ID register (IDRx) corresponding to this bit. No comparison is made
with the bit of the received message ID.
Note:
AMR0 and AMR1 should be set when all the message buffers (x) selecting AMR0 and AMR1 are
invalid (BVALx of the message buffer valid register (BVALR) is "0"). Setting when the buffers are
valid (BVALx = 1) may cause unnecessary received messages to be stored.
To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while the CAN controller is
operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN controller
is operating for CAN bus communication to enable transmission and reception), follow the procedure in
Section "22.15 Precautions when Using CAN Controller".
447
CHAPTER 22 CAN CONTROLLER
22.6.20
Message Buffers
There are 16 message buffers. Message buffer x (x = 0 to 15) consists of an ID register
(IDRx), DLC register (DLCRx), and data register (DTRx).
■ Message Buffers
● The message buffer (x) is used both for transmission and reception.
● The lower-numbered message buffers are assigned higher priority.
• At transmission, when a request for transmission is made to more than one message buffer, transmission
is performed, starting with the lowest-numbered message buffer (See Section "22.7 Transmission of
CAN Controller").
• At reception, when the received message ID passes through the acceptance filter (mechanism for
comparing the acceptance-masked ID of received message and message buffer) of more than one
message buffer, the received message is stored in the lowest-numbered message buffer (See Section
"22.8 Reception of CAN Controller").
● When the same acceptance filter is set in more than one message buffer, the message buffers can be
used as a multi-level message buffer. This provides allowance for receiving time.
(See Section "22.12 Procedure for Reception by Message Buffer (x)").
Note:
A write operation to message buffers and general-purpose RAM areas should be performed in words to
even addresses only. A write operation in bytes causes undefined data to be written to the upper byte at
writing to the lower byte. Writing to the upper byte is ignored.
When the BVALx bit of the message buffer valid register (BVALR) is "0" (Invalid), the message
buffers x (IDRx, DLCRx, and DTRx) can be used as general-purpose RAM.
During the receive/transmit operation of the CAN controller, the CAN Controller write/read to/from the
message buffers. If the CPU tries to write/read to/from the message buffers in this period, the CPU has
to wait a maximum time of 64 machine cycles.
This is also true for the general-purpose RAM.
448
CHAPTER 22 CAN CONTROLLER
22.6.21
ID Register x (x = 0 to 15) (IDRx)
ID Register x (x = 0 to 15) (IDRx) is the ID register for message buffer (x).
■ ID Register x (x = 0 to 15) (IDRx)
Figure 22.6-24 Configuration of the ID Registers (IDRx)
Address:
CAN1: 003820 H + 4 * x
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
Byte 0
Initial value
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
Byte 1
CAN1: 003821 H + 4 * x
ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13
Initial value
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
CAN1: 003822 H + 4 * x
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
ID12 ID11 ID10 ID9
ID8 ID7 ID6
ID5
Byte 2
Initial value
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
Byte 3
CAN1: 003823 H + 4 * x
ID4 ID3
Initial value
XXXXX--- B
ID2
ID1
ID0
-
-
-
R/W R/W R/W R/W R/W
-
-
-
x = 0, ... , 15
R/W
:
Readable/writable
X
-
:
:
Undefined value
Undefined
When using the message buffer (x) in the standard frame format (IDEx of the IDE register (IDER) = 0), use
11 bits of ID28 to ID18. When using the buffer in the extended frame format (IDEx = 1), use 29 bits of
ID28 to ID0.
ID28 to ID0 have the following functions:
• Set acceptance code (ID for comparing with the received message ID).
• Set transmitted message ID.
Note:
In the standard frame format, setting 1s to all bits of ID28 to ID22 is prohibited.
• Store the received message ID.
Note:
All received message ID bits are stored (even if bits are masked). In the standard frame format, ID17 to
ID0 stores image of old message left in the receive shift register.
449
CHAPTER 22 CAN CONTROLLER
Note:
A write operation to this register should be performed in words. A write operation in bytes causes
undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is
ignored.
This register should be set when the message buffer (x) is invalid (BVALx of the message buffer valid
register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause unnecessary
received messages to be stored.
To invalidate the message buffer (by setting the BVALR: BVAL bit to "0") while the CAN controller is
operating for CAN communication (the read value of the CSR: HALT bit is "0" and the CAN controller
is operating for CAN bus communication to enable transmission and reception), follow the procedure in
Section "22.15 Precautions when Using CAN Controller".
450
CHAPTER 22 CAN CONTROLLER
22.6.22
DLC Register x (x = 0 to 15) (DLCRx)
DLC Register x (x = 0 to 15) (DLCRx) is the DLC register for message buffer x.
Figure 22.6-25 Configuration of the DLC Registers (DLCRx)
Address:
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
CAN1: 003860 H + 2 * x
R/W
:
Readable/writable
X
-
:
:
Undefined value
Undefined
-
-
-
-
DLC3 DLC2 DLC1 DLC0
-
-
-
- R/W R/W R/W R/W
(lower)
Initial value
----XXXX B
x = 0, ... , 15
■ DLC Register x (x = 0 to 15) (DLCRx)
● Transmission
• Set the data length (byte count) of a transmitted message when a data frame is transmitted (TRTRx of
the transmitting RTR register (TRTRR) is "0").
• Set the data length (byte count) of a requested message when a remote frame is transmitted (TRTRx =
1).
Note:
Setting other than 0000B to 1000B (0 to 8 bytes) is prohibited.
● Reception
• Store the data length (byte count) of a received message when a data frame is received (RRTRx of the
remote frame request receiving register (RRTRR) is "0").
• Store the data length (byte count) of a requested message when a remote frame is received (RRTRx =
1).
Note:
A write operation to this register should be performed in words. A write operation in bytes causes
undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is
ignored.
451
CHAPTER 22 CAN CONTROLLER
22.6.23
Data Register x (x = 0 to 15) (DTRx)
Data register x (x = 0 to 15) (DTRx) is the data register for message buffer (x).
This register is used only in transmitting and receiving a data frame but not in
transmitting and receiving a remote frame.
■ Data Register x (x = 0 to 15) (DTRx)
Figure 22.6-26 Configuration of the Data Registers (DTRx)
Address:
CAN1: 003880 H + 8 * x
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Byte 0
D7
Initial value
XXXXXXXX B
D6
D5
D4
D3
D2
D1
D0
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
CAN1: 003881 H + 8 * x
D7
D6
D5
D4
D3
D2
D1
D0
R/W R/W R/W R/W R/W R/W R/W R/W
Byte 1
Initial value
XXXXXXXX B
Address:
CAN1: 003882 H + 8 * x
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Byte 2
D7
Initial value
XXXXXXXX B
D6
D5
D4
D3
D2
D1
D0
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
CAN1: 003883 H + 8 * x
D7
D6
D5
D4
D3
D2
D1
D0
R/W R/W R/W R/W R/W R/W R/W R/W
Byte 3
Initial value
XXXXXXXX B
Address:
CAN1: 003884 H + 8 * x
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Byte 4
D7
Initial value
XXXXXXXX B
D6
D5
D4
D3
D2
D1
D0
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
CAN1: 003885 H + 8 * x
D7
D6
D5
D4
D3
D2
D1
D0
R/W R/W R/W R/W R/W R/W R/W R/W
Byte 5
Initial value
XXXXXXXX B
Address:
CAN1: 003886 H + 8 * x
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Byte 6
D7
Initial value
XXXXXXXX B
D6
D5
D4
D3
D2
D1
D0
R/W R/W R/W R/W R/W R/W R/W R/W
Address:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
CAN1: 003887 H + 8 * x
D7
D6
D5
D4
D3
D2
D1
D0
R/W R/W R/W R/W R/W R/W R/W R/W
452
R/W
:
Readable/writable
X
-
:
:
Undefined value
Undefined
Byte 7
Initial value
XXXXXXXX B
x = 0, 1, ... , 15
CHAPTER 22 CAN CONTROLLER
● Sets transmitted message data (any of 0 to 8 bytes)
Data is transmitted in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB.
● Stores received message data
Data is stored in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB.
Even if the received message data is less than 8 bytes, the remaining bytes of the data register (DTRx), to
which data are stored, are undefined.
Note:
A write operation to this register should be performed in words. A write operation in bytes causes
undefined data to be written to the upper byte at writing to the lower byte. Writing to the upper byte is
ignored.
453
CHAPTER 22 CAN CONTROLLER
22.7
Transmission of CAN Controller
When "1" is written to TREQx of the transmission request register (TREQR),
transmission by the message buffer (x) starts. At this time, TREQx becomes "1" and
TCx of the transmission complete register (TCR) becomes "0".
■ Starting Transmission of the CAN Controller
If RFWTx of the remote frame receiving wait register (RFWTR) is "0", transmission starts immediately. If
RFWTx is "1", transmission starts after waiting until a remote frame is received (RRTRx of the remote
request receiving register (RRTRR) becomes "1").
If a request for transmission is made to more than one message buffer (more than one TREQx is "1"),
transmission is performed, starting with the lowest-numbered message buffer.
Message transmission to the CAN bus (by the transmit output pin TX) starts when the bus is idle.
If TRTRx of the transmission RTR register (TRTRR) is "0", a data frame is transmitted. If TRTRx is "1", a
remote frame is transmitted.
If the message buffer competes with other CAN controllers on the CAN bus for transmission and
arbitration fails, or if an error occurs during transmission, the message buffer waits until the bus is idle and
repeats retransmission until it is successful.
■ Canceling a Transmission Request from the CAN Controller
● Canceling by transmission cancel register (TCANR)
A transmission request for message buffer (x) having not executed transmission during transmission
pending can be canceled by writing "1" to TCANx of the transmission cancel register (TCANR). At
completion of cancellation, TREQx becomes "0".
● Canceling by storing received message
The message buffer (x) having not executed transmission despite transmission request also performs
reception.
If the message buffer (x) has not executed transmission despite a request for transmission of a data frame
(TRTRx = 0 or TREQx = 1), the transmission request is canceled after storing received data frames passing
through the acceptance filter (TREQx = 0).
Note:
A transmission request is not canceled by storing remote frames (TREQx = 1 remains unchanged).
If the message buffer (x) has not executed transmission despite a request for transmission of a remote frame
(TRTRx = 1 or TREQx = 1), the transmission request is canceled after storing received remote frames
passing through the acceptance filter (TREQx = 0).
Note:
The transmission request is canceled by storing either data frames or remote frames.
454
CHAPTER 22 CAN CONTROLLER
■ Completing Transmission of the CAN Controller
When transmission is successful, RRTRx becomes "0", TREQx becomes "0", and TCx of the transmission
complete register (TCR) becomes "1".
If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt enable
register (TIER) is "1"), an interrupt occurs.
■ Transmission Flowchart of the CAN Controller
Figure 22.7-1 Transmission Flowchart of the CAN Controller
Transmission request
(TREQx := 1)
TCx := 0
0
TREQx?
1
0
RFWTx?
1
0
RRTRx?
1
If there are any other message buffers
meeting the above conditions, select
the lowest-numbered message buffer.
NO
Is the bus idle?
YES
0
1
TRTRx?
A data frame is transmitted.
A remote frame is transmitted.
NO
Is transmission
successful?
YES
TCANx?
1
RRTRx : = 0
TREQx := 0
TCx
:= 1
TREQx := 0
1
TIEx ?
0
0
A transmission complete
interrupt occurs.
End of transmission
455
CHAPTER 22 CAN CONTROLLER
22.8
Reception of CAN Controller
Reception starts when the start of data frame or remote frame (SOF) is detected on the
CAN bus.
■ Acceptance Filtering
The received message in the standard frame format is compared with the message buffer (x) set in the
standard frame format (IDEx of the IDE register (IDER) is "0"). The received message in the extended
frame format is compared with the message buffer (x) set (IDEx is "1") in the extended frame format.
If all the bits set to compare by the acceptance mask agree after comparison between the received message
ID and acceptance code (ID register (IDRx) for comparing with the received message ID), the received
message passes to the acceptance filter of the message buffer (x).
■ Storing Received Message
When the receive operation is successful, received messages are stored in a message buffer x including IDs
passed through the acceptance filter.
When receiving data frames, received messages are stored in the ID register (IDRx), DLC register
(DLCRx), and data register (DTRx).
Even if received message data is less than 8 bytes, some data is stored in the remaining bytes of the DTRx
and its value is undefined.
When receiving remote frames, received messages are stored only in the IDRx and DLCRx, and the DTRx
remains unchanged.
If there is more than one message buffer including IDs passed through the acceptance filter, the message
buffer x in which received messages are to be stored is determined according to the following rules.
• The order of priority of the message buffer x (x = 0 to 15) rises as its number lower; in other words,
message buffer 0 is given the highest and the message buffer 15 is given the lowest priority.
• Basically, message buffers with the RCx bit of 0 in the receive completion register (RCR) are preferred
in storing received messages.
• If the bits of the acceptance mask select register (AMSR) are set to all bits compare (for message buffers
with the AMSx.1 and AMSx.0 bits set to 00), received messages are stored irrespective of the value of
the RCx bit of the RCR.
• If there are message buffers with the RCx bit of the RCR set to "0", or with the bits of the AMSR set to
all bits compare, received messages are stored in the lowest-number (highest-priority) message buffer x.
• If there are no message buffers above-mentioned, received messages are stored in a lower-number
message buffer x.
• Message buffers should be arranged in ascending numeric order. The lowest message buffers should be
with all bits compare, then AMR0 or AMR1 masks. And The highest message buffers should be with all
bits mask.
456
CHAPTER 22 CAN CONTROLLER
Figure 22.8-1 shows a flowchart for determining the message buffer (x) where received messages are to be
stored. It is recommended that message buffers be arranged in the following order: message buffers in
which each AMSR bit is set to all bits compare, message buffers using AMR0 or AMR1, and message
buffers in which each AMSR bit is set to all bits mask.
Figure 22.8-1 Flowchart Determining Message Buffer (x) where Received Messages Stored
Start
Are message buffers with RCx set to 0
or with AMSx.1 and AMSx.0 set to 00
found?
NO
YES
Select the lowest-numbered
message buffer.
Select the lowest-numbered
message buffer.
End
■ Receive Overrun
When a message is stored in the message buffer with the corresponding RCx being already set to "1", it will
results in receive overrun. In this case, the corresponding ROVRx bit in the receive overrun register
ROVRR is set to "1".
■ Processing for Reception of Data Frame and Remote Frame
● Processing for reception of data frame
RRTRx of the remote request receiving register (RRTRR) becomes "0".
TREQx of the transmission request register (TREQR) becomes "0" (immediately before storing the
received message). A transmission request for message buffer (x) having not executed transmission will be
canceled.
Note:
A request for transmission of either a data frame or remote frame is canceled.
● Processing for reception of remote frame
RRTRx becomes "1".
If TRTRx of the transmitting RTR register (TRTRR) is "1", TREQx becomes "0". As a result, the request
for transmitting remote frame to message buffer having not executed transmission will be canceled.
Note:
A request for data frame transmission is not canceled.
For cancellation of a transmission request, see Figure 22.7-1.
457
CHAPTER 22 CAN CONTROLLER
■ Completing Reception
RCx of the reception complete register (RCR) becomes "1" after storing the received message.
If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is "1"), an
interrupt occurs.
Note:
This CAN controller will not receive any messages transmitted by itself.
458
CHAPTER 22 CAN CONTROLLER
22.9
Reception Flowchart of CAN Controller
Figure 22.9-1 shows a reception flowchart of the CAN controller.
■ Reception Flowchart of the CAN Controller
Figure 22.9-1 Reception Flowchart of the CAN Controller
Detection of start of data frame
or remote frame (SOF)
NO
Is any message buffer (x) passing to
the acceptance filter found?
YES
NO
Is reception
successful?
YES
Determine message buffer (x) where
received messages to be stored
Store the received message
in the message buffer (x)
1
RCx?
0
Data frame
ROVRx := 1
Remote frame
Received message?
RRTRx := 0
RRTRx := 1
1
TRTRx?
0
TREQx := 0
RCx := 1
RIEx ?
0
1
A reception interrupt
occurs
End of reception
459
CHAPTER 22 CAN CONTROLLER
22.10
How to Use the CAN Controller
The following settings are required to use the CAN controller:
• Bit timing
• Frame format
• ID
• Acceptance filter
• Low-power consumption mode
■ CAUTION:
Do not use the clock modulation and CAN at the same time on devices MB90F947, MB90F949 and
MB90V390HA. The problem is fixed on MB90F946A, MB90947A, MB90F947A, MB90F949A, MB90V390HB.
■ Setting Bit Timing
The bit timing register (BTR) should be set during bus operation stop (when the bus operation stop bit
(HALT) of the control status register (CSR) is "1").
After the setting completion, write "0" to HALT to cancel bus operation stop.
■ Setting Frame Format
Set the frame format used by the message buffer (x). When using the standard frame format, set IDEx of
the IDE register (IDER) to "0". When using the extended frame format, set IDEx to "1".
This setting should be made when the message buffer (x) is invalid (BVALx of the message buffer valid
register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received
messages to be stored.
■ Setting ID
Set the message buffer (x) ID to ID28 to ID0 of ID register (IDRx). The message buffer (x) ID need not be
set to ID17 to ID0 in the standard frame format. The message buffer (x) ID is used as a transmission
message at transmission and is used as an acceptance code at reception.
This setting should be made when the message buffer (x) is invalid (BVALx of the message buffer valid
register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received
messages to be stored.
■ Setting acceptance Filter
The acceptance filter of the message buffer (x) is set by an acceptance code and acceptance mask set. It
should be set when the acceptance message buffer (x) is invalid (BVALx of the message buffer enable
register (BVALR) is "0"). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received
messages to be stored.
Set the acceptance mask used in each message buffer (x) by the acceptance mask select register (AMSR).
The acceptance mask registers (AMR0 and AMR1) should also be set if used (For the setting details, see
Sections "22.6.18 Acceptance Mask Select Register (AMSR)" and "22.6.19 Acceptance Mask Registers 0
and 1 (AMR0 and AMR1)").
The acceptance mask should be set so that a transmission request may not be canceled when unnecessary
received messages are stored. For example, it should be set to a full-bit comparison if only one specific ID
is used for the transmission.
460
CHAPTER 22 CAN CONTROLLER
■ Setting Low-power Consumption Mode
To set the F2MC-16LX in a low-power consumption mode (stop and timebase timer), write "1" to the bus
operation stop bit (HALT) of the control status register (CSR), and then check that the bus operation has
stopped (HALT = 1).
461
CHAPTER 22 CAN CONTROLLER
22.11
Procedure for Transmission by Message Buffer (x)
After setting the bit timing, frame format, ID, and acceptance filter, set BVALx to "1" to
activate the message buffer (x).
■ Procedure for Transmission by Message Buffer (x)
● Setting transmit data length code
Set the transmit data length code (byte count) to DLC3 to DLC0 of the DLC register (DLCRx).
For data frame transmission (when TRTRx of the transmission RTR register (TRTRR) is "0"), set the data
length of the transmitted message.
For remote frame transmission (when TRTRx = 1), set the data length (byte count) of the requested
message.
Note:
Setting other than 0000B to 1000B (0 to 8 bytes) is prohibited.
● Setting transmit data (only for transmission of data frame)
For data frame transmission (when TRTRx of the transmission register (TRTRR) is "0"), set data as the
count of byte transmitted in the data register (DTRx).
Note:
Transmit data should be rewritten while the TREQx bit of the transmission request register (TREQR)
set to "0". There is no need for setting the BVALx bit of the message buffer valid register (BVALR) to
"0". Setting the BVALx bit to "0" may cause incoming remote frame to be lost.
● Setting transmission RTR register
For data frame transmission, set TRTRx of the transmission RTR register (TRTRR) to "0".
For remote frame transmission, set TRTRx to "1".
● Setting conditions for starting transmission (only for transmission of data frame)
Set RFWTx of the remote frame receiving wait register (RFWTR) to "0" to start transmission immediately
after a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is
"1" and TRTRx of the transmission RTR register (TRTRR) is "0").
Set RFWTx to "1" to start transmission after waiting until a remote frame is received (RRTRx of the
remote request receiving register (RRTRR) becomes "1") after a request for data frame transmission is set
(TREQx = 1 and TRTRx = 0).
Note:
Remote frame transmission can not be made, if RFWTx is set to "1".
462
CHAPTER 22 CAN CONTROLLER
● Setting transmission complete interrupt
When generating a transmission complete interrupt, set TIEx of the transmission complete interrupt enable
register (TIER) to "1".
When not generating a transmission complete interrupt, set TIEx to "0".
● Setting transmission request
For a transmission request, set TREQx of the transmission request register (TREQR) to "1".
● Canceling transmission request
When canceling a pending request for transmission to the message buffer (x), write "1" to TCANx of the
transmission cancel register (TCANR).
Check TREQx. For TREQx = 0, transmission cancellation is terminated or transmission is completed.
Check TCx of the transmission complete register (TCR). For TCx = 0, transmission cancellation is
terminated. For TCx = 1, transmission is completed.
● Processing for completion of transmission
If transmission is successful, TCx of the transmission complete register (TCR) becomes "1".
If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt enable
register (TIER) is "1"), an interrupt occurs.
After checking the transmission completion, write "0" to TCx to set it to "0". This cancels the transmission
complete interrupt.
In the following cases, the pending transmission request is canceled by receiving and storing a message.
• Request for data frame transmission by reception of data frame
• Request for remote frame transmission by reception of data frame
• Request for remote frame transmission by reception of remote frame
Request for data frame transmission is not canceled by receiving and storing a remote frame. ID and DLC,
however, are changed by the ID and DLC of the received remote frame. Note that the ID and DLC of data
frame to be transmitted become the value of received remote frame.
463
CHAPTER 22 CAN CONTROLLER
22.12
Procedure for Reception by Message Buffer (x)
After setting the bit timing, frame format, ID, and acceptance filter, make the settings
described below.
■ Procedure for Reception by Message Buffer (x)
● Setting reception interrupt
To enable reception interrupt, set RIEx of the reception interrupt enable register (RIER) to "1".
To disable reception interrupt, set RIEx to "0".
● Starting reception
When starting reception after setting, set BVALx of the message buffer valid register (BVALR) to "1" to
make the message buffer (x) valid.
● Processing for reception completion
If reception is successful after passing to the acceptance filter, the received message is stored in the
message buffer (x) and RCx of the reception complete register (RCR) becomes "1". For data frame
reception, RRTRx of the remote request receiving register (RRTRR) becomes "0". For remote frame
reception, RRTRx becomes "1".
If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is "1"), an
interrupt occurs.
After checking the reception completion (RCx = 1), process the received message.
After completion of processing the received message, check ROVRx of the reception overrun register
(ROVRR).
If ROVRx = 0, the processed received message is valid. Write "0" to RCRx to set it to "0" (the reception
complete interrupt is also canceled) to terminate reception.
If ROVRx = 1, a reception overrun occurred and the next message may have overwritten the processed
message. In this case, received messages should be processed again after setting the ROVRx bit to "0" by
writing "0" to it.
Figure 22.12-1 shows an example of receive interrupt handling.
464
CHAPTER 22 CAN CONTROLLER
Figure 22.12-1 Example of Receive Interrupt Handling
Interrupt with RCx = 1
Read received messages.
A: = ROVRx
ROVRx := 0
A = 0?
NO
YES
RCx := 0
End
465
CHAPTER 22 CAN CONTROLLER
22.13
Setting Configuration of Multi-level Message Buffer
If the receptions are performed frequently, or if several different ID’s of messages are
received, in other words, if there is insufficient time for handling messages, more than
one message buffer can be combined into a multi-level message buffer to provide
allowance for processing time of the received message by CPU.
■ Setting Configuration of Multi-level Message Buffer
To provide a multi-level message buffer, the same acceptance filter must be set in the combined message
buffers.
If the bits of the acceptance mask select register (AMSR) are set to all bits compare ((AMSx.1, AMSx.0) =
(0, 0)), multi-level message configuration of message buffers is not allowed. This is because all bits
compare causes received messages to be stored irrespective of the value of the RCx bit of the receive
completion register (RCR), so received messages are always stored in lower-numbered (lower-priority)
message buffers even if all bits compare and identical acceptance code (ID register (IDRx)) are specified
for more than one message buffer. Therefore, all bits compare and identical acceptance code should not be
specified for more than one message buffer.
Figure 22.13-1 shows operational examples of multi-level message buffers.
466
CHAPTER 22 CAN CONTROLLER
Figure 22.13-1 Examples of Operation of Multi-level Message Buffer
Initialization
AMS15, AMS14, AMS13
AMSR 10 10 10
Select AMR0.
...
AM28 to AM18
AMS0
ID28 to ID18
0000 1111 111
RC15, RC14, RC13
IDE
...
Message buffer 13
0101 0000 000
0
...
RCR 0
0
0
...
Message buffer 14
0101 0000 000
0
...
ROVRR 0
0
0
...
Message buffer 15
0101 0000 000
0
...
ROVR15, ROVR14, ROVR13
Mask
Message receiving
"The received message is stored in message buffer 13.
IDE
ID28 to ID18
Message receiving
0101 1111 000
0
...
Message buffer 13
0101 1111 000
0
...
RCR 0
0
1
...
Message buffer 14
0101 0000 000
0
...
ROVRR 0
0
0
...
Message buffer 15
0101 0000 000
0
...
Message receiving
"The received message is stored in message buffer 14.
Message receiving
0101 1111 001
0
...
Message buffer 13
0101 1111 000
0
...
RCR 0
1
1
...
Message buffer 14
0101 1111 001
0
...
ROVRR 0
0
0
...
Message buffer 15
0101 0000 000
0
...
Message receiving
"The received message is stored in message buffer 15.
Message receiving
0101 1111 010
0
...
Message buffer 13
0101 1111 000
0
...
RCR 1
1
1
...
Message buffer 14
0101 1111 001
0
...
ROVRR 0
0
0
...
Message buffer 15
0101 1111 010
0
...
Message receiving "An overrun occurs (ROVR13 = 1) and the received message is stored in message buffer 13.
Message receiving
0101 1111 011
0
...
Message buffer 13
0101 1111 011
0
...
RCR 1
1
1
...
0
...
ROVRR 0
0
1
...
0
...
Message buffer 14
Message buffer 15
0101 1111 001
0101 1111 010
Note:
Four messages are received with the same acceptance filter set in message buffers 13, 14 and 15.
467
CHAPTER 22 CAN CONTROLLER
22.14
Setting the CAN Direct Mode Register
The MB90945 series provides a clock modulator for the system clock. Since the CAN
controller is not able to operate with a modulated clock, the unmodulated clock is
provided to the CAN controller independently from the clock modulator settings.
■ CAN Direct Mode Register (CDMR)
Figure 22.14-1 Configuration of the CAN Direct Mode Register (CDMR)
Address:
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
CAN0: 00356EH
R/W
X
-
:
:
:
-
-
-
-
-
-
-
-
-
-
-
-
-
- R/W
DIRECT
Initial value
XXXXXXX0 B
Readable/writable
Undefined value
Undefined
■ CAN Direct Mode Register Contents
Table 22.14-1 Function of the DIRECT Bit of the CAN Direct Mode Register
Bit name
Function
bit7 to bit1
Undefined
-
bit0
DIRECT
The value "1" should be written to this bit when the clock modulation is disabled.
Then, the CAN Controller skips synchronization to the modulated clock, making
the communication between CAN and CPU as fast as possible.
The value "0" must be written to this bit if the clock modulation is enabled in
order to synchronize modulated system clock and unmodulated CAN clock.
468
CHAPTER 22 CAN CONTROLLER
22.15
Precautions when Using CAN Controller
Use of the CAN Controller requires the following cautions.
■ Caution for Disabling Message Buffers by BVAL Bits
The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set disabled
while CAN Controller is participating in CAN communication (the read value of the CSR: HALT bit is "0"
and CAN Controller is ready to transmit messages). This section shows the work around of this
malfunction.
● Condition
When following two conditions occur at the same time, the CAN Controller will not perform to transmit
messages normally.
• CAN Controller is participating in the CAN communication. (i.e. The read value of the CSR: HALT bit
is "0" and CAN Controller is ready to transmit messages)
• Message buffers are read when BVAL bits disable the message buffers.
● Work around
Operation for suppressing transmission request
Do not use BVAL bit for suppressing transmission request, use TCAN bit instead of it.
Operation for composing transmission message
For composing a transmission message, it is necessary to disable the message buffer by BVAL bit to
change contents of ID and IDE registers. In this case, BVAL bit should reset (BVAL=0) after checking
if TREQ bit is "0" or after completion of the previous message transmission (TC=1).
In case a buffer needs to be disabled, ensure that no transmission request is pending (if it was requested
before)! Therefore, do not reset BVALx-Bit before testing, if a transmission is ongoing:
a) Cancel the transmission request (TCANx=1;), if necessary
b) and wait for the transmission completion (while (TREQx==1);) by polling or interrupt.
Only after that the transmission buffer can be disabled (BVALx=0;).
Note for case a), if transmission of that buffer has already started, canceling the request is ignored and
disabling the buffer is delayed until the end of the transmission.
■ CAUTION:
Do not use the clock modulation and CAN at the same time on devices MB90F947, MB90F949 and
MB90V390HA. The problem is fixed on MB90F946A, MB90947A, MB90F947A, MB90F949A,
MB90V390HB.
469
CHAPTER 22 CAN CONTROLLER
470
CHAPTER 23
ADDRESS MATCH
DETECTION FUNCTION
This chapter explains the functions and operations of
the address match detection function.
23.1 Outline of the Address Match Detection Function
23.2 Registers of the Address Match Detection Function
23.3 Operation of the Address Match Detection Function
23.4 Example of the Address Match Detection Function
471
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION
23.1
Outline of the Address Match Detection Function
When an address matches the value set in the address detection register, the
instruction code to be read by the CPU is replaced with the INT9 instruction code (01H).
Consequently, the CPU executes the INT9 instruction when executing a specified
instruction. The address match detection function can be achieved using the INT9
interrupt routine for processing.
There are 5 address detection registers, each with an interrupt permission bit. When an
address matches the value set in the address detection register and the interrupt
permission bit is "1", the instruction code to be read by the CPU is replaced with the
INT9 instruction code.
■ Block Diagram of the address Match Detection Function
Address latch
Address detection
register
Permission bit
F2MC-16LX bus
472
Comparison
Figure 23.1-1 Block Diagram of the address Match Detection Function
INT9
instruction
F2MC-16LX
CPU core
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION
23.2
Registers of the Address Match Detection Function
The two types of registers for the address match detection function are as follows:
• Program address detection registers (PADR0 to PADR2)
• Program address detection control status register (PACSR0)
■ Program address Detection Registers (PADR0 to PADR2)
The program address detection registers 0 to 2 (PADR0 to PADR2) compare the address with the value
written in each register. If they match when the interrupt permission bit corresponding to ADCSR is "1",
the CPU is requested to issue the INT9 instruction.
When the corresponding interrupt bit is "0", nothing occurs.
Figure 23.2-1 Program address Detection Registers (PADR0 to PADR2)
byte
PADR0 35E2H/35E1H/35E0H
PADR1 35E5H/35E4H/35E3H
PADR2 35E8H/35E7H/35E6H
byte
byte
Access
R/W
R/W
R/W
Initial value
Undefined
Undefined
Undefined
Table 23.2-1 lists the correspondence between the program address detection registers (PADR0 to PADR2)
and PACSR0.
Table 23.2-1 Correspondence between PADR0 to PADR2 Registers and PACSR0 Register
Address detection register
Interrupt permission bit
PADR0
AD0E (bit1)
PADR1
AD1E (bit3)
PADR2
AD2E (bit5)
473
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION
■ Program address Detection Control Status Register (PACSR0)
The program address detection control status register (PACSR0) controls the operation of the address
detection function.
Figure 23.2-2 Program address Detection Control Status Registers (PACSR0)
Address:
00009E H
bit7
R/W
R/W
bit6
Reserved Reserved
R/W
bit5
bit4
bit3
bit2
bit1
bit0
AD2E
Reserved
AD1E
Reserved
AD0E
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000 B
: Readable/writable
Table 23.2-2 Function of Each Bit of PACSR0
Name
Function
bit7, bit6
Reserved bits
Bit7 and bit6 are reserved. Set these bits to "0" before setting PACSR0.
bit5
AD2E:
Address detect
register 2 enable
The AD2E bit is the operation permission bit for PADR2.
When this bit is "1", the address is compared with the PADR2 register. If they match,
the INT9 instruction is issued.
bit4
Reserved bit
Bit4 is reserved. Set this bit to "0" before setting PACSR0.
bit3
AD1E:
Address detect
register 1 enable
The AD1E bit is the operation permission bit for PADR1.
When this bit is "1", the address is compared with the PADR1 register. If they match,
the INT9 instruction is issued.
bit2
Reserved bit
Bit2 is reserved. Set this bit to "0" before setting PACSR0.
bit1
AD0E:
Address detect
register 0 enable
The AD0E bit is the operation permission bit for PADR0.
When this bit is "1", the address is compared with the PADR0 register. If they match,
the INT9 instruction is issued.
bit0
Reserved bit
Bit0 is reserved. Set this bit to "0" before setting PACSR0.
474
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION
23.3
Operation of the Address Match Detection Function
If the program counter specifies the same address as the address match detection
register, the INT9 instruction is executed. The address match detection function can be
achieved by processing the INT9 instruction routine.
■ Operation of the address Match Detection Function
There are 3 address detection registers with a compare enable bit. When the value set in the address
detection register and the value of the program counter match and the compare enable bit is set to "1", the
CPU executes the INT9 instruction.
Note:
If the value of the address detection register and the value of the program counter match, the contents of
internal data bus is changed to 01H. Consequently, the INT9 instruction is executed. Before changing
the contents of the address detection register, always set the compare enable bit to "0". While the
compare enable bit is set to "1", changing the contents of the address detection register may result in a
malfunction.
475
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION
23.4
Example of the Address Match Detection Function
Figure 23.4-1 shows a system configuration example of the address match detection
function. Table 23.4-1 lists the EEPROM memory map.
■ System Configuration Example of the address Match Detection Function
Figure 23.4-1 System Configuration Example of the address Match Detection Function
EEPROM
MCU
F2MC16LX
SIN
Pull-up resistor
Connector (UART)
Table 23.4-1 EEPROM Memory Map
Address
Description
0000H
Number of bytes of patch program No.0 (If 0, no program
error exists.)
0001H
Program address No.0 bit7 to bit0
0002H
Program address No.0 bit15 to bit8
0003H
Program address No.0 bit24 to bit16
0004H
Number of bytes of patch program No.1 (If 0, no program
error exists.)
0005H
Program address No.1 bit7 tobit 0
0006H
Program address No.1 bit15 to bit8
0007H
Program address No.1 bit24 to bit16
0010H or higher
Main body of patch program No. 0
● Initial status
EEPROM is set to all "0s".
476
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION
● When a program error occurs:
The main body of the patch program and program address are transferred to the MCU through the
connector (UART). The MCU writes the information to EEPROM.
● Reset sequence
The MCU reads the value of EEPROM after reset. If the number of bytes of the patch program is not "0",
the main body of the patch program is read from EEPROM and written to RAM. The MCU then uses either
PADR0 or PADR1 to set the patch address and sets the compare enable bit. If the relocatable patch
program is required, the first address of the patched program can be written to the RAM area. In this case,
the INT9 routine accesses this user-defined RAM area and jumps to the patched program.
● INT9 interrupt
The interrupt routine can know the address where the interrupt occurs by checking the value of the stack
program counter. The information that has been placed on the stack during the interrupt is discarded.
477
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION
■ Example of Program Patch Processing
Figure 23.4-2 Example of Program Patch Processing
000000H
Correction program
RAM
Program address
detection register
E2PROM
Program address
detection setting
(reset sequence)
Correction program byte number
Interrutp generation address
Correction program
Abnormal program
ROM
FFFFFFH
Setting the program address detecting of reset sequence, executing normal program
Branch to the patch program that is expanded to RAM by INT9 interruption from address match detection.
Executing the patch program by branching of INT9 operation.
Executing the mormal protram that is branched by the patch program
478
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION
Figure 23.4-3 Flow of Program Patch Processing
Reset
Reads 00H of EEPROM
INT9
YES
0000H(EEPROM)=0
To patch program
JMP 000400H
NO
Read address
0001H to 0003H (EEPROM)
MOV
PADR0 (MCU)
Execute patch program
000400H to 000480H
Read patch program
0010H to 0090H (EEPROM)
MOV
000400H to 000480H (MCU)
Terminate patch program
JMP FF0050H
Enable compare
MOV PACSR, #02H
Execute normal program
NO
PC=PADR0
YES
INT9
FFFFFFH
FF0050H
ROM
EEPROM
Abnormal program
FF0000H
FFFFH
FE0000H
0090H
Patch program
0010H
001100H
Stack area
0003H
0002H
0001H
0000H
Program address
low-order:
Program address
middle-order:
Program address
high-order:
Number of bytes of
the patch program:
RAM area
00
00
000480H
Patch program
RAM
000400H
RAM and register area
FF
000100H
I/O area
80
000000H
479
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION
480
CHAPTER 24
ROM MIRRORING MODULE
This chapter explains the ROM mirroring module.
24.1 Outline of ROM Mirroring Module
24.2 ROM Mirroring Register (ROMM)
481
CHAPTER 24 ROM MIRRORING MODULE
24.1
Outline of ROM Mirroring Module
The ROM Mirroring module switches whether to mirror the image of the FF bank of the
ROM to the 00 bank.
■ Block Diagram of ROM Mirroring Module
Figure 24.1-1 Block Diagram of ROM Mirroring Module
F2MC-16LX BUS
ROM Mirrroring Register
Address Area
FF bank
00 bank
ROM
482
CHAPTER 24 ROM MIRRORING MODULE
24.2
ROM Mirroring Register (ROMM)
Do not access the ROM mirroring register (ROMM) when addresses 004000 H to 00FFFFH
are being accessed.
■ ROM Mirroring Register (ROMM)
Figure 24.2-1 Configuration of the ROM Mirroring Register (ROMM)
Address:
00006FH
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
-
-
-
-
-
-
MS MI
-
-
-
-
-
-
R/W W
(+)
R/W
W
:
:
Readable/writable
Write only
X
-
:
:
Undefined value
Undefined
Initial value
XXXXXX+1 B
(+): MB90V390HA/HB, MB90F946A: read only, fixed to "1"
MB90F947, MB90F949: selectable; initial value "0"
MB90947A
: selectable; initial value "0"
Table 24.2-1 Function of Each Bit of ROM Mirroring Register
Bit name
Function
bit15 to
bit9
Undefined
bit9
MS:
Mirror size bit
"1": The ROM mirror size is 32 k Bytes (008000H to 00FFFFH)
"0": The ROM mirror size is 48 k Bytes (004000H to 00FFFFH)
Note:
This bit is fixed to "1" and read only in the MB90V390HA/HB and MB90F946A.
In MB90947A, MB90F947(A) and MB90F949(A), it is selectable.
bit8
MI:
Mirror bit
The image of the ROM data in the FF bank can also be found in the 00 bank when "1" is
written to this bit. However, this memory mapping will not be done when this bit is
written to "0". This bit is write only.
-
Note:
Only FF4000H/FF8000H to FFFFFFH is mirrored to 004000H/008000H to 00FFFFH when the ROM
mirroring function is activated. Therefore, addresses FF0000H to FF3FFFH/FF7FFFH will not be
mirrored to 00 bank.
483
CHAPTER 24 ROM MIRRORING MODULE
484
CHAPTER 25
1M/2M/3M-BIT FLASH
MEMORY
This chapter explains the functions and operations of
the 1M/2M/3M-bit flash memory. The following three
methods are available for writing data to and erasing
data from the flash memory:
• Parallel programmer
• Serial programmer
• Executing programs to write/erase data
This chapter explains "Executing programs to write/
erase data".
25.1 Overview of 1M/2M/3M-Bit Flash Memory
25.2 Block Diagram of the Entire Flash Memory and Sector
Configuration of the Flash Memory
25.3 Write/Erase Modes
25.4 Flash Memory Control Status Register (FMCS)
25.5 Starting the Flash Memory Automatic Algorithm
25.6 Confirming the Automatic Algorithm Execution State
25.7 Detailed Explanation of Writing to and Erasing Flash Memory
25.8 Notes on Using 1M/2M/3M-Bit Flash Memory
25.9 Reset Vector Address in Flash Memory
25.10 Example of Programming 1M/2M/3M-Bit Flash Memory
485
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.1
Overview of 1M/2M/3M-Bit Flash Memory
The 1M/2M/3M-bit flash memory is mapped to the F9/FC/FE to FF bank in the CPU
memory map. The functions of the flash memory interface circuit enable read-access
and program-access from the CPU in the same way as mask ROM. Instructions from the
CPU can be used via the flash memory interface circuit to write data to and erase data
from the flash memory. Internal CPU control therefore enables rewriting of the flash
memory while it is mounted. As a result, improvements in programs and data can be
performed efficiently.
■ 1M/2M/3M-bit Flash Memory Features
•
Use of automatic program algorithm (Embedded Algorithm: Equivalent to MBM29LV200)
•
Erase pause/restart functions provided
•
Detection of completion of writing/erasing using data polling or toggle bit functions
•
Detection of completion of writing/erasing using CPU interrupts
•
Sector erase function (any combination of sectors)
•
Minimum of 10,000 write/erase operations
Embedded AlgorithmTM is a trademark of Advanced Micro Device, Inc.
Note:
The manufacturer code and device code do not have the reading function. These codes cannot be
accessed by the command.
■ Writing to/Erasing Flash Memory
The flash memory cannot be written to and read at the same time. That is, when data is written to or erased
data from the flash memory, the program in the flash memory must first be copied to RAM. The entire
process is then executed in RAM so that data is simply written to the flash memory. This eliminates the
need for the program to access the flash memory from the flash memory itself.
■ Flash Memory Control Status Register (FMCS)
Figure 25.1-1 Configuration of Flash Memory Control Status Register (FMCS)
Address:
0000AE H
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
INTE
RDYINT
WE
RDY
Reserved
Reserved
Reserved
Reserved
000X0000B
R
R/W
R/W
R/W
R/W
R/W
R/W
R
486
: Readable/writable
: Read only
R/W
R/W
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.2
Block Diagram of the Entire Flash Memory and Sector
Configuration of the Flash Memory
Figure 25.2-1 shows a block diagram of the entire flash memory with the flash memory
interface circuit included. Figure 25.2-2 shows the sector configuration of the 1M-bit
flash memory and Figure 25.2-3 shows the sector configuration of the 2M-bit flash
memory and Figure 25.2-4 shows the sector configuration of the 3M-bit flash memory.
■ Block Diagram of the Entire Flash Memory
Figure 25.2-1 Block Diagram of the Entire Flash Memory
1M/2M/3M-bit
Flash memory
Flash memory
interface circuit
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
F2MC-16LX
bus
BYTE
INT
BYTE
CE
CE
OE
OE
WE
WE
AQ0 to AQ18
AQ0 to AQ17
AQ-1
DQ0 to DQ15
DQ0 to DQ15
RY/BY
RY/BY
RESET
Write enable interrupt signal
(to CPU)
External reset signal
RY/BY write
enable signal
487
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
■ Sector Configuration of the 1M-bit Flash Memory
Figure 25.2-2 shows the sector configuration of the 1M-bit flash memory. The addresses in the figure
indicate the high-order and low-order addresses of each sector.
Figure 25.2-2 Sector Configuration of the 1M-bit Flash Memory
MB90F947(A)
Programmer address*
CPU address
7FFFFH
FFFFFFH
7C000H
7BFFFH
FFC000H
FFBFFFH
7A000H
79FFFH
FFA000H
FF9FFFH
78000H
77FFFH
FF8000H
FF7FFFH
70000H
6FFFFH
FF0000H
FEFFFFH
60000H
FE0000H
SA4 (16-Kbyte)
SA3 (8-Kbyte)
SA2 (8-Kbyte)
SA1 (32-Kbyte)
SA0 (64-Kbyte)
*:Always use the programmer address when writing/erasing the Flash memory using
a parallel programmer.
488
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
■ Sector Configuration of the 2M-bit Flash Memory
Figure 25.2-3 shows the sector configuration of the 2M-bit flash memory. The addresses in the figure
indicate the high-order and low-order addresses of each sector.
Figure 25.2-3 Sector Configuration of the 2M-bit Flash Memory
MB90F949(A)
Programmer address*
CPU address
7FFFFH
FFFFFFH
7C000H
7BFFFH
FFC000H
FFBFFFH
7A000
H
Programmer
79FFFHaddress*
FFA000H
CPU address
FF9FFF
H
SA6 (16-Kbyte)
SA5 (8-Kbyte)
MB90F394H
SA4 (8-Kbyte)
SA8 (16 KByes)
SA7 (8 KBytes)
78000H
77FFFH
7FFFFH
7BFFFH
FFFFFFH
FF8000H
FF7FFF
FFBFFF
H
H
SA3 (32-Kbyte)
SA6 (8 KByes)
SA2 (64-Kbyte)
SA5 (32
70000H
6FFFFH
KBytes)
SA4 (64 KByes)
60000H
5FFFFH
SA1 (64-Kbyte)
SA3 (64 KBytes)
Unused
SA0 (64-Kbyte)
SA2 (64 KBytes)
SA1 (64 KByes)
50000H
4FFFFH
40000H
79FFFH
FF9FFFH
FF0000
H
FEFFFFH
77FFFH
FF7FFFH
6FFFFH
FE0000H
FEFFFFH
FDFFFF
H
5FFFFH
FDFFFFH
4FFFFH
FD0000H
FCFFFF
H
FCFFFF
H
3FFFFH
FC0000
FBFFFF
H
H
2FFFFH
FAFFFFH
*:Always use the programmer address when writing/erasing
the Flash memory using
1FFFF
F9FFFF
SA0 (64 KBytes)
a parallel programmer.
F8FFFF
0FFFF
H
Unused
H
H
H
00000H
F80000H
489
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
■ Sector Configuration of the 3M-bit Flash Memory
Figure 25.2-4 shows the sector configuration of the 3M-bit flash memory. The addresses in the figure
indicate the high-order and low-order addresses of each sector.
Figure 25.2-4 Sector Configuration of the 3M-bit Flash Memory
MB90F946A
Programmer address*
CPU address
7FFFFH
FFFFFFH
7C000H
7BFFFH
FFC000H
FFBFFFH
7A000H
79FFFH
FFA000H
FF9FFFH
SA8 (16-Kbyte)
SA7 (8-Kbyte)
SA6 (8-Kbyte)
MB90F394H
SA8 (16
SA5 (32-Kbyte)
KByes)
SA7 (8 KBytes)
78000HProgrammer
FF8000
CPU
H address
address*
FF7FFFH
77FFFH
7FFFF
FFFFFF
70000H
6FFFFH
SA4 (64-Kbyte)
SA6 (8 KByes)
SA5 (32 KBytes)
60000H
5FFFFH
H
H
7BFFFH
FF0000
H
FFBFFF
H
FEFFFFH
79FFFH
77FFFH
FF9FFFH
FE0000H
FDFFFF
FF7FFF
H
H
SA3 (64-Kbyte)
SA4 (64 KByes)
Unused
SA3
50000H
4FFFFH
(64 KBytes)
Unused
40000H
3FFFFH
SA2 (64-Kbyte)
SA2 (64 KBytes)
SA1 (64 KByes)
30000H
2FFFFH
SA1 (64-Kbyte)
SA0 (64 KBytes)
20000H
1FFFFH
SA0 (64-Kbyte)
Unused
10000H
6FFFFH
FEFFFFH
FD0000
H
FCFFFFH
5FFFFH
FDFFFFH
4FFFFH
FC0000H
FCFFFFH
FBFFFFH
3FFFFH
2FFFFH
1FFFFH
0FFFFH
00000H
FBFFFFH
FB0000H
FAFFFF
H
FAFFFF
H
FA0000
F9FFFF
H
H
F9FFFFH
F8FFFFH
F80000H
F90000H
* The programmer address is equivalent to
the CPU address
when data is written to the
F8FFFF
0FFFF
H
flash memory using a parallel programmer. H
When a general programmer
is used for
Unused
writing/erasing, this
address is used for writing/erasing.
00000H
F80000H
*:Always use the programmer address when writing/erasing the Flash memory using
a parallel programmer.
490
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.3
Write/Erase Modes
The flash memory can be accessed in two different ways: Flash memory mode and
alternative mode. Flash memory mode enables data to be directly written to or erased
from the external pins. Alternative mode enables data to be written to or erased from
the CPU via the internal bus. Use the mode external pins to select the mode.
■ Flash Memory Mode
The CPU stops when the mode pins are set to 111B while the reset signal is asserted. The flash memory
interface circuit is connected directly to ports 0, 1, 2, 3, 4 and 5, enabling direct control from the external
pins. This mode makes the MCU seem like a standard flash memory to the external pins, and write/erase
can be performed using a flash memory programmer.
In flash memory mode, all operations supported by the flash memory automatic algorithm can be used.
■ Alternative Mode
The flash memory is located in the F9/FC/FE to FF banks in the CPU memory space, and like ordinary
mask ROM, can be read-accessed and program-accessed from the CPU via the flash memory interface
circuit.
Since writing/erasing the flash memory is performed by instructions from the CPU via the flash memory
interface circuit, this mode allows rewriting even when the MCU is soldered on the target board.
Sector protect operations cannot be performed in these modes.
Note:
Writing/erasing the flash memory is not specified at all machine clock frequencies. Refer to the AC
Characteristics section of the data sheet.
■ Flash Memory Control Signals
Table 25.3-1 lists the flash memory control signals in flash memory mode.
There is almost a one-to-one correspondence between the flash memory control signals and the external
pins of the MBM29LV200. The VID (12 V) pins required by the sector protect operations are MD0, MD1,
and MD2 instead of A9, RESET, and OE for the MBM29LV200.
In flash memory mode, the external data bus signal width is limited to 8 bits, enabling only one-byte
access. The DQ15 to DQ8 pins are not supported. The BYTE pin should always be set to "0".
491
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
Table 25.3-1 Flash Memory Control Signals
MB90F947(A)/MB90F949(A)/MB90F946A
MBM29LV200
Pin number
Normal function
Flash memory mode
5
P30
AQ16
A15
6
P31
CE
CE
7
P32
OE
OE
8
P33
WE
WE
9
P34
AQ17
A16
10
P35
AQ18
-
11
P36
BYTE
BYTE
12
P37
RY/BY
RY/BY
18 to 21
P40 to P43
AQ8 to AQ11
A7 to A10
22, 23
P46, P47
AQ12, AQ13
A11, A12
24
P50
AQ14
A13
25
PB0
AQ15
A14
51
MD2
MD2
OE (VID)
52
MD1
MD1
RESET (VID)
53
MD0
MD0
A9 (VID)
54
RST
RESET
RESET
77 to 84
P00 to P07
DQ0 to DQ7
DQ0 to DQ7
85 to 89
P10 to P14
DQ8 to DQ12
DQ8 to DQ12
94 to 96
P15 to P17
DQ13 to DQ15
DQ13 to DQ15
97 to 100
P20 to P23
AQ0 to AQ3
A-1, A0 to A2
1 to 4
P24 to P27
AQ4 to AQ7
A3 to A6
Note: All port pins not mentioned above should be connected to VCC via a pull-up resistor.
492
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.4
Flash Memory Control Status Register (FMCS)
The flash memory control status register (FMCS), together with the flash memory
interface circuit, is used to write data to and erase data from the flash memory.
■ Flash Memory Control Status Register (FMCS)
Figure 25.4-1 Flash Memory Control Status Register (FMCS)
Address:
0000AE H
bit7
INTE
R/W
R/W
R
bit6
RDYINT
R/W
bit5
WE
R/W
bit4
RDY
R
bit3
Reserved
bit2
bit1
Reserved Reserved
R/W
R/W
R/W
bit0
Reserved
Initial value
000X0000B
R/W
: Readable/writable
: Read only
● Explanation of bits
[bit7] INTE (interrupt enable)
This bit generates an interrupt to the CPU when flash memory write/erase terminates.
An interrupt to the CPU is generated when the INTE and RDYINT bits are "1". No interrupt is
generated when the INTE bit is "0".
•
0: Disables interrupts when write/erase terminates.
•
1: Enables interrupts when write/erase terminates.
[bit6] RDYINT (ready interrupt)
This bit indicates the operating state of the flash memory.
This bit is set to "1" when flash memory write/erase terminates. Data cannot be written to or erased
from the flash memory while this bit is "0" after a flash memory write/erase. Flash memory write/erase
is enabled when write/erase terminates and this bit is set to "1".
Writing "0" clears this bit to "0". Writing "1" is ignored. This bit is set to "1" at the termination timing
of the flash memory automatic algorithm (see Section "25.5 Starting the Flash Memory Automatic
Algorithm"). When the read-modify-write (RMW) instruction is used, "1" is always read.
•
0: Write/erase is being executed.
•
1: Write/erase has terminated (interrupt request generated).
[bit5] WE (write enable)
This bit enables writing to the flash memory area.
When this bit is "1", writing after the command sequence (see Section "25.5 Starting the Flash Memory
Automatic Algorithm") is issued to the F9/FC/FE to FF bank writes to the flash memory area. When
this bit is "0", the write/erase signal is not generated. This bit is used when the flash memory Write/
Erase command is started.
If write/erase is not performed, it is recommended that this bit be set to "0" to prevent data from being
mistakenly written to the flash memory.
•
0: Disables flash memory write/erase.
•
1: Enables flash memory write/erase.
493
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
[bit4] RDY (ready)
This bit enables flash memory write/erase.
Flash memory write/erase is disabled while this bit is "0". However, Suspend commands, such as the
Read/Reset command and Sector Erase Suspend command, can be accepted even if this bit is "0".
•
0: Write/erase is being executed.
•
1: Write/erase has terminated (next data write/erase enabled).
[bit3 to bit0] Reserved bits
These bits are reserved for testing. During regular use, they should always be set to "0".
Note:
The RDYINT and RDY bits cannot be changed at the same time. Create a program so that decisions are
made using one or the other of these bits.
Figure 25.4-2 Transitions of the RDYINT and RDY Bits
Automatic algorithm
Termination timing
RDYINT bit
RDY bit
1 machine cycle
494
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.5
Starting the Flash Memory Automatic Algorithm
Four types of commands are available for starting the flash memory automatic
algorithm: Read/reset, Write, and Chip erase. Control of suspend and restart is enabled
for sector erase.
■ Command Sequence Table
Table 25.5-1 lists the commands used for flash memory write/erase. All of the data written to the command
register is in bytes, but use word access to write. The data of the high-order bytes at this time is ignored.
Table 25.5-1 Command Sequence Table
Command
sequence
1st bus write
cycle
Bus
write
access
2nd bus write cycle
3rd bus write cycle
4th bus write cycle
5th bus write cycle
6th bus write cycle
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Read/reset *
1
FxXXXX
XXF0
-
-
-
-
-
-
-
-
-
-
Read/reset *
4
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XXF0
RA
RD
-
-
-
-
Write program
4
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XXA0
PA
(even)
PD
(word)
-
-
-
-
Chip erase
6
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX80
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX10
Sector erase
6
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX80
FxAAAA
XXAA
Fx5554
XX55
SA
(even)
XX30
-
-
Sector Erase Suspend
Entering address FxXXXX data (xxB0H) suspends erasing during sector erase.
Sector Erase Restart
Entering address FxXXXX data (xx30H) restarts erasing after erasing is suspended during sector erase.
Auto-select
3
FxAAA
XXAA
Fx5554
XX55
FxAAAA
XX90
-
-
-
-
Notes:
•
The addresses Fx in the table mean FF and FE for 1M-bit flash memory and FF, FE, FD and FC for the
2M-bit flash memory and FF, FE, FD, FB, FA and F9 for the 3M-bit flash memory. Use these addresses
as the access target bank values for operations.
•
The addresses in the table are the values in the CPU memory map. All addresses and data are
represented using hexadecimal notation. However, the letter X is an optional value.
•
RA: Read address
•
PA: Write address. Only even addresses can be specified.
•
SA: Sector address. See Section "25.2 Block Diagram of the Entire Flash Memory and Sector
Configuration of the Flash Memory".
•
RD: Read data
•
PD: Write data. Only word data can be specified.
*: Both of the two types of read/reset commands can reset the flash memory to read mode.
495
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
The Auto-select command shown in Table 25.5-1 is used to know the state of sector protection. When
using the Auto-select command, set the address as follows.
Table 25.5-2 Address Setting at Auto-select
Sector protection
AQ13 to AQ18
AQ7
AQ2
AQ1
AQ0
DQ7 to DQ0
Sector Address
L
H
L
L
CODE*
*: When the sector address is protected, the output is "01H".
When the sector address is not protected, the output is "00H".
496
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.6
Confirming the Automatic Algorithm Execution State
Because the write/erase flow of the flash memory is controlled using the automatic
algorithm, the flash memory has hardware for posting its internal operating state and
completion of operation. This automatic algorithm enables confirmation of the
operating state of the built-in flash memory using the following hardware sequences.
■ Hardware Sequence Flags
The hardware sequence flags are configured from the five-bit output of DQ7, DQ6, DQ5, DQ3 and DQ2.
The functions of these bits are those of the data polling flag (DQ7), toggle bit flag (DQ6), timing limit
exceeded flag (DQ5), sector erase timer flag (DQ3) and toggle bit-2 flag (DQ2). The hardware sequence
flags can therefore be used to confirm that writing or chip sector erase has been completed or that erase
code write is valid.
The hardware sequence flags can be accessed by read-accessing the addresses of the target sectors in the
flash memory after setting of the command sequence (see Table 25.5-1 in Section "25.5 Starting the Flash
Memory Automatic Algorithm". Table 25.6-1 lists the bit assignments of the hardware sequence flags.
Table 25.6-1 Bit Assignments of Hardware Sequence Flags
Bit no.
7
6
5
4
3
2
1
0
Hardware sequence flag
DQ7
DQ6
DQ5
-
DQ3
DQ2
-
-
To determine whether automatic writing or chip sector erase is being executed, the hardware sequence flags
can be checked or the status can be determined from the RDY bit of the flash memory control register
(FMCS) that indicates whether writing has been completed. After writing/erasing has terminated, the state
returns to the read/reset state. When creating a program, use one of the flags to confirm that automatic
writing/erasing has terminated. Then, perform the next processing operation, such as data read. In addition,
the hardware sequence flags can be used to confirm whether the second or subsequent sector erase code
write is valid. The following sections describe each hardware sequence flag separately. Table 25.6-2 lists
the functions of the hardware sequence flags.
497
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
Table 25.6-2 Hardware Sequence Flag Functions
State
State
change for
normal
operation
Write → Write completed (write
address specified)
Chip/sector erase → Erase completed
Sector erase wait → Erase started
DQ7 →
DATA:7
DQ6
Toggle →
DATA:6
DQ5
0→
DATA:5
DQ3
0→
DATA:3
1→
DATA:2
0→1
Toggle →
Stop
0→1
1
Toggle →
Stop
0
Toggle
0
0→1
Toggle
0→1
Toggle →
1
0
1→0
Toggle
Sector erase suspend → Erase restarted
(sector being erased)
1→0
1→
Toggle
0
0→1
Toggle
Write
Chip/sector erase
DATA:7
DATA:6
DATA:5
DATA:3
DATA:2
DQ7
Toggle
1
0
1
0
Toggle
1
1
1*
* : If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2 to
toggle. DQ2 does not toggle when the successive reads are executed from other sectors.
498
DQ2
Erase → Sector erase suspended (sector
being erased)
Sector erase suspended (sector not
being erased)
Abnormal
operation
DQ7
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.6.1
Data Polling Flag (DQ7)
The data polling flag (DQ7) uses the data polling function to post that the automatic
algorithm is being executed or has terminated
■ Data Polling Flag (DQ7)
Table 25.6-3 and Table 25.6-4 list the state transitions of the data polling flag.
Table 25.6-3 Data Polling Flag State Transitions (State Change for Normal Operation)
Operating
state
Write →
Completed
Chip/sector
erase →
Completed
DQ7 →
DQ7
Sector
erase wait
→ Started
0→1
Sector erase
→ Erase
suspend
(sector being
erased)
0→1
0
Sector erase
suspend →
Restarted
(sector being
erased)
1→0
Sector erase
suspended
(sector not
being erased)
DATA:7
Table 25.6-4 Data Polling Flag State Transitions
(State Change for Abnormal Operation)
Operating
state
Write
Chip/sector
erase
DQ7
DQ7
0
● Write
Read-access during execution of the automatic write algorithm causes the flash memory to output the
opposite data of bit7 last written, regardless of the value at the address specified by the address signal.
Read-access at the end of the automatic write algorithm causes the flash memory to output bit7 of the read
value of the address specified by the address signal.
● Chip/sector erase
For a sector erase, read-access during execution of the chip erase/sector erase algorithm causes the flash
memory to output "0" from the sector currently being erased. For a chip erase, read-access causes the flash
memory to output "0" regardless of the value at the address specified by the address signal. Read-access at
the end of the automatic write algorithm causes the flash memory to output "1" in the same way.
499
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
● Sector erase suspend
Read-access during a sector erase suspend causes the flash memory to output "1" if the address specified by
the address signal belongs to the sector being erased. The flash memory outputs bit7 (DATA: 7) of the read
value at the address specified by the address signal if the address specified by the address signal does not
belong to the sector being erased. Referencing this flag together with the toggle bit flag (DQ6) enables a
decision to be made on whether the flash memory is in the erase suspended state and which sector is being
erased.
Note:
When the automatic algorithm is being started, read-access to the specified address is ignored. Since
termination of the data polling flag (DQ7) can be accepted for a data read and other bits output, data
read after the automatic algorithm has terminated should be performed after read-access has confirmed
that data polling has terminated.
500
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.6.2
Toggle Bit Flag (DQ6)
Like the data polling flag, the toggle bit flag (DQ6) uses the toggle bit function to post
that the automatic algorithm is being executed or has terminated.
■ Toggle Bit Flag (DQ6)
Table 25.6-5 and Table 25.6-6 list the state transitions of the toggle bit flag.
Table 25.6-5 Toggle Bit Flag State Transitions (State Change for Normal Operation)
Operating
state
Write →
Completed
Chip/sector
erase →
Completed
DQ6
Toggle →
DATA:6
Toggle →
Stop
Sector
erase wait
→ Started
Toggle
Sector erase
→ Erase
suspend
(sector being
erased)
Sector erase
suspend →
Restarted
(sector being
erased)
Toggle → 1
1 → Toggle
Sector erase
suspended
(sector not
being erased)
DATA:6
Table 25.6-6 Toggle Bit Flag State Transitions
(State Change for Abnormal Operation)
Operating
state
Write
Chip/sector
erase
DQ6
Toggle
Toggle
● Write/chip sector erase
Continuous read-access during execution of the automatic write algorithm and chip/sector erase algorithm
causes the flash memory to toggle the 1 or 0 state for every read cycle, regardless of the value at the
address specified by the address signal. Continuous read-access at the end of the automatic write algorithm
and chip/sector erase algorithm causes the flash memory to stop toggling bit6 and output bit6 (DATA: 6) of
the read value of the address specified by the address signal.
● Sector erase suspend
Read-access during a sector erase suspend causes the flash memory to output "1" if the address specified by
the address signal belongs to the sector being erased. The flash memory outputs bit6 (DATA: 6) of the read
value at the address specified by the address signal if the address specified by the address signal does not
belong to the sector being erased.
Note:
For a write, if the sector where data is to be written is rewrite-protected, the toggle bit terminates the
toggle operation after approximately 2μs without any data being rewritten. For an erase, if all of the
selected sectors are write-protected, the toggle bit performs toggling for approximately 100μs and then
returns to the read/reset state without any data being rewritten.
501
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.6.3
Timing Limit Exceeded Flag (DQ5)
The timing limit exceeded flag (DQ5) is used to post that execution of the automatic
algorithm has exceeded the time (internal pulse count) prescribed in the flash memory.
■ Timing Limit Exceeded Flag (DQ5)
Table 25.6-7 and Table 25.6-8 list the state transitions of the timing limit exceeded flag.
Table 25.6-7 Timing Limit Exceeded Flag State Transitions (State Change for Normal Operation)
Operating
state
Write →
Completed
Chip/sector
erase →
Completed
DQ5
0→
DATA:5
0→1
Sector
erase wait
→ Started
0
Sector erase
→ Erase
suspend
(sector being
erased)
Sector erase
suspend →
Restarted
(sector being
erased)
0
0
Sector erase
suspended
(sector not
being erased)
DATA:5
Table 25.6-8 Timing Limit Exceeded Bit Flag State Transitions
(State Change for Abnormal Operation)
Operating
state
Write
Chip/sector
erase
DQ5
1
1
● Write/chip sector erase
Read-access after write or chip/sector erase automatic algorithm activation causes the flash memory to
output "0" if the time is within the prescribed time (time required for write/erase) or to output "1" if the
prescribed time has been exceeded. Because this is done regardless of whether the automatic algorithm is
being executed or has terminated, it is possible to determine whether write/erase was successful or
unsuccessful. That is, when this flag outputs "1", writing can be determined to have been unsuccessful if
the automatic algorithm is still being executed by the data polling function or toggle bit function.
For example, writing "1" to a flash memory address where "0" has been written will cause the fail state to
occur. In this case, the flash memory will lock and execution of the automatic algorithm will not terminate.
As a result, valid data will not be output from the data polling flag (DQ7). In addition, the toggle bit flag
(DQ6) will exceed the time limit without stopping the toggle operation and the timing limit exceeded flag
(DQ5) will output "1". Note that this state indicates that the flash memory is not faulty, but has been used
correctly. When this state occurs, execute the Reset command.
502
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.6.4
Sector Erase Timer Flag (DQ3)
The sector erase timer flag (DQ3) is used to post whether the automatic algorithm is
being executed during the sector erase wait period after the Sector Erase command has
been started.
■ Sector Erase Timer Flag (DQ3)
Table 25.6-9 and Table 25.6-10 list the state transitions of the sector erase timer flag.
Table 25.6-9 Sector Erase Timer Flag State Transitions (State Change for Normal Operation)
Operating
state
Write →
Completed
Chip/sector
erase →
Completed
DQ3
0→
DATA:3
1
Sector
erase wait
→ Started
Sector erase
→ Erase
suspend (sector
being erased)
0→1
1→0
Sector erase
suspend →
Restarted
(sector being
erased)
0→1
Sector erase
suspended
(sector not
being erased)
DATA:3
Table 25.6-10 Sector Erase Timer Flag State Transitions
(State Change for Abnormal Operation)
Operating
state
DQ3
Chip/sector
erase
Write
0
1
● Sector erase
Read-access after the Sector Erase command has been started causes the flash memory to output "0" if the
automatic algorithm is being executed during the sector erase wait period, regardless of the value at the
address specified by the address signal of the sector that issued the command. The flash memory outputs
"1" if the sector erase wait period has been exceeded.
If the data polling function or toggle bit function indicates that the erase algorithm is being executed,
internally controlled erase has already started if this flag is "1". Continuous write of the sector erase codes
or commands other than the Sector Erase Suspend command will be ignored until erase is terminated.
If this flag is "0", the flash memory will accept write of additional sector erase codes. To confirm this, it is
recommended that the state of this flag be checked before continuing to write sector erase codes. If this flag
is "1" after the second state check, it is possible that additional sector erase codes may not be accepted.
503
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
● Read access during sector erase
Read-access during execution of sector erase suspend causes the flash memory to output "1" if the address
specified by the address signal belongs to the sector being erased. If this address does not belong to the
sector being erased, the flash memory outputs bit3 (DATA:3) of the corresponding memory value.
504
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.6.5
Toggle Bit-2 Flag (DQ2)
The toggle bit-2 flag (DQ2) is a flag that uses the toggle bit function to indicate that the
sector is in the erase-suspended state.
■ Toggle Bit-2 Flag (DQ2)
Table 25.6-11 and Table 25.6-12 list the state transitions of the toggle bit flag.
Table 25.6-11 Toggle Bit-2 Flag State Transitions (State Change for Normal Operation)
Operating
state
Write →
Completed
Chip/sector
erase →
Completed
Sector
erase wait
→ Started
Sector erase
→ Erase
suspend (sector
being erased)
Sector erase
suspend →
Restarted (sector
being erased)
Sector erase
suspended
(sector not
being erased)
DQ2
1→
DATA:2
Toggle →
Stop
Toggle
Toggle
Toggle
DATA:2
Table 25.6-12 Toggle Bit-2 Flag State Transitions
(State Change for Abnormal Operation)
Operating
state
Write
Chip/sector
erase
DQ2
1
1*
*: If the DQ5 outputs "1" (exceed the timing limit), successive reads from a writing or erasing sector cause DQ2 to toggle.
DQ2 does not toggle when the successive reads are executed from other sectors.
● During a sector erase operation
If successive reads are executed during the execution of the chip sector erase algorithm, a flash memory
toggles to output "1" and "0" to addresses alternately at every read access regardless of the location
indicated by the addresses. If successive reads are executed after the chip sector erase algorithm is
completed, the flash memory stops the toggle operation of the bit2 and outputs the read value of the bit2
(DATA: 2) to the location indicated by the address.
505
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
● While a sector erase operation is suspended
If successive reads are executed while a sector erase operation is suspended, and if the address indicates the
sector to be erased, the flash memory toggles to alternately output "1" and "0". If the address indicates the
sector is not to be erased, the flash memory outputs the read value of the bit2 (DATA: 2) to the location
indicated by the address.
In the erase-suspend-program mode, successive reads from the non-erase suspended sector causes the flash
memory to output "1".
Both DQ2 and DQ6 are used for detecting an erase-suspended sector (DQ2 toggles, but DQ6 does not).
DQ2 is also used for detecting an erasing sector. While erasing a sector, if a read access is executed from
the erasing sector, DQ2 toggles.
Reference:
If all sectors selected for erasing are write-protected, the toggle bit-2 toggles for about 100μs, and then
returns to the read/reset mode without writing the data.
506
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.7
Detailed Explanation of Writing to and Erasing Flash
Memory
This section describes each operation procedure of flash memory Read/Reset, Write,
Chip Erase, Sector Erase, Sector Erase Suspend, and Sector Erase Restart when a
command that starts the automatic algorithm is issued.
■ Detailed Explanation of Flash Memory Write/Erase
The flash memory executes the automatic algorithm by issuing a command sequence (see "■ Command
sequence table" in Section "25.5 Starting the Flash Memory Automatic Algorithm") for a write cycle to the
bus to perform read/reset, write, chip erase, sector erase, sector erase suspend, or sector erase restart
operations. Each bus write cycle must be performed continuously. In addition, whether the automatic
algorithm has terminated can be determined using the data polling or other function. At normal termination,
the flash memory is returned to the read/reset state.
Each operation of the flash memory is described in the following order:
•
Setting the read/reset state
•
Writing data
•
Erasing all data (erasing chips)
•
Erasing optional data (erasing sectors)
•
Suspending sector erase
•
Restarting sector erase
507
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.7.1
Setting The Read/Reset State
This section describes the procedure for issuing the Read/Reset command to set the
flash memory to the read/reset state.
■ Setting the Flash Memory to the Read/Reset State
The flash memory can be set to the read/reset state by sending the read/reset command in the command
sequence table (see "■ Command sequence table" in Section "25.5 Starting the Flash Memory Automatic
Algorithm") continuously to the target sector in the flash memory.
The read/reset command has two types of command sequences that execute the first and third bus
operations. However, there are no essential differences between these command sequences.
The read/reset state is the initial state of the flash memory. When the power is turned on and when a
command terminates normally, the flash memory is set to the read/reset state. In the read/reset state, other
commands wait for input.
In the read/reset state, data is read by regular read-access. As with the mask ROM, program access from the
CPU is enabled. The Read/Reset command is not required to read data by a regular read. The read/reset
command is mainly used to initialize the automatic algorithm in such cases as when a command does not
terminate normally.
508
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.7.2
Writing Data
This section describes the procedure for issuing the Write command to write data to the
flash memory.
■ Writing Data to the Flash Memory
The data write automatic algorithm of the flash memory can be started by sending the Write command in
the command sequence table (see "■ Command sequence table" in Section "25.5 Starting the Flash
Memory Automatic Algorithm") continuously to the target sector in the flash memory. When data write to
the target address is completed in the fourth cycle, the automatic algorithm and automatic write are started.
● Specifying addresses
Only even addresses can be specified as the write addresses specified in a write data cycle. Odd addresses
cannot be written correctly. That is, writing to even addresses must be done in units of word data.
Writing can be done in any order of addresses or even if the sector boundary is exceeded. However, the
Write command writes only data of one word for each execution.
● Notes on writing data
Writing cannot return data 0 to data 1. When data 1 is written to data 0, the data polling algorithm (DQ7) or
toggle operation (DQ6) does not terminate and the flash memory elements are determined to be faulty. If
the time prescribed for writing is thus exceeded, the timing limit exceeded flag (DQ5) is determined to be
an error. Otherwise, the data is viewed as if dummy data 1 had been written. However, when data is read in
the read/reset state, the data remains "0". Data 0 can be set to data 1 only by erase operations.
All commands are ignored during execution of the automatic write algorithm. If a hardware reset is started
during writing, the data of the written addresses will be unpredictable.
■ Writing to the Flash Memory
Figure 25.7-1 is an example of the procedure for writing to the flash memory. The hardware sequence flags
(see Section "25.6 Confirming the Automatic Algorithm Execution State") can be used to determine the
state of the automatic algorithm in the flash memory. Here, the data polling flag (DQ7) is used to confirm
that writing has terminated.
The data read to check the flag is read from the address written to last.
The data polling flag (DQ7) changes at the same time that the timing limit exceeded flag (DQ5) changes.
For example, even if the timing limit exceeded flag (DQ5) is "1", the data polling flag bit (DQ7) must be
rechecked.
Also for the toggle bit flag (DQ6), the toggle operation stops at the same time that the timing limit
exceeded flag bit (DQ5) changes to "1". The toggle bit flag (DQ6) must therefore be rechecked.
509
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
Figure 25.7-1 Example of the Flash Memory Write Procedure
Start writing
FMCS: WE (bit 5)
Enable flash memory write
Write command sequence
(1) FxAAAAH ← XXAAH
(2) Fx5554H ← XX55H
(3) FxAAAAH ← XXA0H
(4) Write address ← Write data
Read internal address
Data polling (DQ7)
Next address
Data
Data
0
Timing limit (DQ5)
1
Read internal address
Data
Data polling (DQ7)
Data
Write error
Final address
FMCS: WE (bit 5)
Disable flash memory write
Complete writing
510
Confirm with the hardware
sequence flags.
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.7.3
Erasing All Data (Erasing Chips)
This section describes the procedure for issuing the chip erase command to erase all
data in the flash memory.
■ Erasing All Data in the Flash Memory (Erasing Chips)
All data can be erased from the flash memory by sending the chip erase command in the command
sequence table (see "■ Command sequence table" in Section "25.5 Starting the Flash Memory Automatic
Algorithm") continuously to the target sector in the flash memory.
The chip erase command is executed in six bus operations. When writing of the sixth cycle is completed,
the chip erase operation is started. For chip erase, the user need not write to the flash memory before
erasing. During execution of the automatic erase algorithm, the flash memory writes "0" for verification
before all of the cells are erased automatically.
511
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.7.4
Erasing Optional Data (Erasing Sectors)
This section describes the procedure for issuing the sector erase command to erase
optional data (erase sector) in the flash memory. Individual sectors can be erased.
Multiple sectors can also be specified at one time.
■ Erasing Optional Data (Erasing Sectors) in the Flash Memory
Optional sectors in the flash memory can be erased by sending the sector erase command in the command
sequence table (see "■ Command sequence table" in Section "25.5 Starting the Flash Memory Automatic
Algorithm") continuously to the target sector in the flash memory.
● Specifying sectors
The sector erase command is executed in six bus operations. Sector erase wait of 50μs is started by writing
the sector erase code (30H) to an accessible even-numbered address in the target sector in the sixth cycle.
To erase multiple sectors, write the erase code (30H) to the addresses in the target sectors after the above
processing operation.
● Notes on specifying multiple sectors
Erase is started when the sector erase wait period of 50μs terminates after the final sector erase code has
been written. That is, to erase multiple sectors at one time, an erase code (sixth cycle of the command
sequence) must be written within 50μs of writing of the address of a sector and the address of the next
sector must be written within 50μs of writing of the previous erase code. Otherwise, the address and erase
code may not be accepted. The sector erase timer (hardware sequence flag DQ3) can be used to check
whether writing of the subsequent sector erase code is valid. At this time, specify so that the address used
for reading the sector erase timer indicates the sector to be erased.
■ Erasing Sectors in the Flash Memory
The hardware sequence flags (see Section "25.6 Confirming the Automatic Algorithm Execution State")
can be used to determine the state of the automatic algorithm in the flash memory. Figure 25.7-2 is an
example of the procedure for erasing sectors in the flash memory. Here, the toggle bit flag (DQ6) is used to
confirm that erasing has terminated.
The data that is read to check the flag is read from the sector to be erased.
The toggle bit flag (DQ6) stops the toggle operation at the same time that the timing limit exceeded flag
(DQ5) is changed to "1". For example, even if the timing limit exceeded flag (DQ5) is "1", the toggle bit
flag (DQ6) must be rechecked.
The data polling flag (DQ7) also changes at the same time that the timing limit exceeded flag bit (DQ5)
changes. As a result, the data polling flag (DQ7) must be rechecked.
512
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
Figure 25.7-2 Example of the Flash Memory Sector Erase Procedure
Start erasing
FMCS: WE (bit 5)
Enable flash memory erase
Erase command sequence
(1) FxAAAAH ← XXAA H
(2) Fx5554H ← XX55 H
(3) FxAAAAH ← XX80 H
(4) FxAAAAH ← XXAA H
(5) Fx5554H ← XX55 H
1
Sector erase timer (DQ3)
Read internal address
0
(6) Enter code to erase sector
(30H)
Y
Another erase sector
N
Read internal address 1
Next sector
Read internal address 2
Toggle bit (DQ6)
data 1(DQ6) = data 2(DQ6)
Y
N
0
Timing limit (DQ5)
1
Read internal address 1
Read internal address 2
N
Toggle bit (DQ6)
data 1(DQ6) = data 2(DQ6)
Y
Erase error
Final sector
N
Y
FMCS: WE (bit 5)
Disable flash memory erase
Confirm with the hardware
sequence flags.
Complete erasing
513
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.7.5
Suspending Sector Erase
This section describes the procedure for issuing the sector erase suspend command to
suspend erasing of flash memory sectors. Data can be read from sectors that are not
being erased.
■ Suspending Erasing of Flash Memory Sectors
Erasing of flash memory sectors can be suspended by sending the sector erase suspend command in the
command sequence table (see "■ Command sequence table" in Section "25.5 Starting the Flash Memory
Automatic Algorithm") continuously to the target sector in the flash memory.
The sector erase suspend command suspends the sector erase operation being executed and enables data to
be read from sectors that are not being erased. In this state, only reading is enabled; data cannot be written.
This command is valid only during sector erase operations that include the erase wait time. The command
will be ignored during chip erase or write operations.
This command is implemented by writing the erase suspend code (B0H). At this time, specify an optional
address in the flash memory for the address. An erase suspend command issued again during erasing of
sectors will be ignored.
Entering the sector erase suspend command during the sector erase wait period will immediately terminate
sector erase wait, cancel the erase operation, and set the erase stop state. Entering the erase suspend
command during the erase operation after the sector erase wait period has terminated will set the erase
suspend state after a maximum period of 15μs has elapsed.
514
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.7.6
Restarting Sector Erase
This section describes the procedure for issuing the sector erase restart command to
restart suspended erasing of flash memory sectors.
■ Restarting Erasing of Flash Memory Sectors
Suspended erasing of flash memory sectors can be restarted by sending the sector erase restart command in
the command sequence table (see "■ Command sequence table" in Section "25.5 Starting the Flash
Memory Automatic Algorithm") continuously to the target sector in the flash memory.
The sector erase restart command is used to restart erasing of sectors from the sector erase suspend state set
using the sector erase suspend command. The sector erase restart command is implemented by writing the
erase restart code (30H). At this time, specify an optional address in the flash memory area for the address.
If a sector erase restart command is issued during sector erase, the command will be ignored.
515
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.8
Notes on Using 1M/2M/3M-Bit Flash Memory
This section contains notes on using 1M/2M/3M-bit flash memory.
■ Notes on Using Flash Memory
● Input of a hardware reset (RST)
To input a hardware reset when the automatic algorithm has not been started and reading is in progress, a
minimum "L" level width of 500 ns must be maintained. In this case, a maximum of 500 ns is required until
data can be read from the flash memory after a hardware reset has been activated.
Similarly, to input a hardware reset when the automatic algorithm has been activated and writing or erasing
is in progress, a minimum "L" level width of 50 ns must be maintained. In this case, 20 μs are required
until data can be read after the operation for initializing the flash memory has terminated.
A hardware reset during writing may cause the data being written to be undefined. A hardware reset during
erasing may make the sector being erased unusable.
● Canceling of a software reset and watch-dog timer reset
When the flash memory is being written to or erased with CPU access and if reset conditions occur while
the automatic algorithm is active, the CPU may run out of control. This occurs because these reset
conditions cause the automatic algorithm to continue without initializing the flash memory unit, possibly
preventing the flash memory unit from entering the read state when the CPU starts the sequence after the
reset has been deasserted. These reset conditions must be disabled during writing to or erasing of the flash
memory.
● Program access to flash memory
When the automatic algorithm is operating, read access to the flash memory is disabled. With the memory
access mode of the CPU set to internal ROM mode, writing or erasing must be started after the program
area is switched to another area such as RAM. In this case, when sectors (SA4/SA6) containing interrupt
vectors are erased or written to, interrupt processing cannot be executed. For the same reason, all interrupt
sources other than the flash memory must be disabled while the automatic algorithm is operating.
● Hold function
When the CPU accepts a hold request, the Write signal WE of the flash memory unit may be skewed,
causing erroneous writing or erasing due to an erroneous write. When the acceptance of a hold request is
enabled (HDE bit of EPCR set to "1"), ensure that the WE bit of the control status register (FMCS) is "0".
● Extended intelligent I/O service (EI2OS)
Because write and erase interrupts issued to the CPU from the flash memory interface circuit cannot be
accepted by the EI2OS, they should not be used.
516
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
● Applying VID
Applying VID required for the sector protect operation should always be started and terminated when the
supply voltage is on.
517
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.9
Reset Vector Address in Flash Memory
The MB90F947(A), MB90F949(A), MB90F946A support a hard-wired reset vector.
When the addresses FFFFDCH to FFFFDFH are accessed for reading data in internal
vector mode, the values that have been determined by the hard-wired logic in advance
are read. However, in flash memory mode, as mentioned in the previous chapter, all
addresses can be accessed.
Consequently, it is meaningless to write data to these addresses. Especially when
programming flash memory from the CPU (that is, not in flash memory mode), do not
read these addresses for software polling. Otherwise, the flash memory returns a fixed
reset vector instead of the hardware sequence flag value.
■ Reset Vector address in Flash Memory
The following table shows the reset vector and mode data values determined in advance.
Table 25.9-1 Reset Vector and Mode Data Values
Reset vector
FFA000H
Mode data
00H
Note:
Because of the hard-wired reset vector, it is not necessary to specify the reset vector in the software.
However it is recommended to specify the same vector and the same mode data in the program, this will
prevent the mask ROM device to behave differently from the Flash device when the same program is
used.
518
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
25.10
Example of Programming 1M/2M/3M-Bit Flash Memory
This section presents a programming example of 1M/2M/3M-bit flash memory.
■ Programming Example of 1M/2M/3M-bit Flash Memory
Flash memory sample program
NAME
FLASHWE
TITLE FLASHWE
;------------------------------------------------------------------------------;2M/3M-bit-FLASH test program
;
;1: Transmits the program (address: FF8000H, sector: SA6) from FLASH to RAM
;
(address: 001500H).
;2: Executes the program on RAM.
;3: Writes the PDR1 value to FLASH (address: F90000H, sector: SA1).
;4: Reads the written value (address: F90000H, sector: SA1) and outputs it to PDR2.
;5: Erases the written sector (SA1).
;6: Checks and outputs erase data.
;Conditions
; - Number of bytes transmitted to RAM: 100H (256B)
; - Write/erase termination judgment
;
Judgment according to DQ5 (timing limit excess flag)
;
Judgment according to DQ6 (toggle bit flag)
;
Judgment according to RDY (FMCS)
; - Error handling
;
Hi output to P00 to P07
;
Reset command issuance
;------------------------------------------------------------------;
RESOUS IOSEG
ABS=00
;"RESOUS" I/O segment definition
ORG
0000H
PDR0
RB
1
PDR1
RB
1
PDR2
RB
1
PDR3
RB
1
ORG
0010H
DDR0
RB
1
DDR1
RB
1
DDR2
RB
1
DDR3
RB
1
ORG
00A1H
CKSCR
RB
1
ORG
00AEH
FMCS
RB
1
ORG
006FH
ROMM
RB
1
RESOUS ENDS
;
SSTA
SSEG
RW
0127H
STA_T
RW
1
SSTA
ENDS
;
DATA
DSEG
ABS=0FFH
;FLASH command address
ORG
5554H
COMADR2 RW
1
ORG
0AAAAH
COMADR1 RW
1
DATA
ENDS
519
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
;/////////////////////////////////////////////////////////////
;Main program (FFA000H)
;/////////////////////////////////////////////////////////////
CODE
CSEG
START:
;
/////////////////////////////////////////////////////
;
Initialization
;
/////////////////////////////////////////////////////
MOV
CKSCR,#0BAH
;3-multiple setting
MOV
RP,#0
MOV
A,#!STA_T
MOV
SSB,A
MOVW
A,#STA_T
MOVW
SP,A
MOV
ROMM,#00H
;Mirror OFF
MOV
PDR0,#00H
;For error check
MOV
DDR0,#0FFH
MOV
PDR1,#00H
;Port for data input
MOV
DDR1,#00H
MOV
PDR2,#00H
;Port for data output
MOV
DDR2,#0FFH
;
//////////////////////////////////////////////////////////////
;
Transfer of "FLASH write erase program (FF8000H)" to RAM (1500H address)
;
//////////////////////////////////////////////////////////////
MOVW
A,#1500H
;Transfer destination RAM area
MOVW
A,#08000H
;Transfer source address (program position)
MOVW
RW0,#100H
;Number of bytes to be transferred
MOVS
ADB,PCB
;Transfer of 100H from FF8000H to 001500H
CALLP
001500H
;Jump to the address containing the transferred
;
program
;
/////////////////////////////////////////////////////
;
Data output
;
/////////////////////////////////////////////////////
OUT
MOV
A,#0F9H
MOV
ADB,A
MOVW
RW2,#0000H
MOVW
A,@RW2+00
MOV
PDR2,A
END
JMP
*
CODE
ENDS
;////////////////////////////////////////////////////////////
;FLASH write erase program (SA6)
;////////////////////////////////////////////////////////////
RAMPRG CSEG
ABS=0FFH
ORG
0BC00H
;
////////////////////////////////////////////
Initialization
;
////////////////////////////////////////////
MOVW
RW0,#0500H
;RW0:RAM space for input data acquisition
From 00:0500
MOVW
RW2,#0000H
;RW2:Flash memory write address
From F9:0000
MOV
A,#00H
;DTB modification
MOV
DTB,A
;Bank specification for @RW0
MOV
A,#0F9H
;ADB modification 1
MOV
ADB,A
;Bank specification for write mode specification
;
address
MOV
PDR3,#00H
;Switch initialization
MOV
DDR3,#00H
;
WAIT1
BBC
PDR3:0,WAIT1
;PDR3: 0(write start at high level)
;
520
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
;////////////////////////////////////////////////
;Write (SA1)
;////////////////////////////////////////////////
MOV
A,PDR1
MOVW
@RW0+00,A
;PDR1 data allocation to RAM
MOV
FMCS,#20H
;Write mode setting
MOVW
ADB:COMADR1,#00AAH
;Flash write command 1
MOVW
ADB:COMADR2,#0055H
;Flash write command 2
MOVW
ADB:COMADR1,#00A0H
;Flash write command 3
;
MOVW
A,@RW0+00
;Input data (RW0) write to flash memory (RW2)
MOVW
@RW2+00,A
WRITE
;Wait time check
;
///////////////////////////////////////////////////////////////////
;
ERROR when the time limit excess check flag is set and toggle operation is
;
in progress
;
///////////////////////////////////////////////////////////////////
MOVW
A,@RW2+00
AND
A,#20H
;DQ5 time limit check
BZ
NTOW
;Time limit over
MOVW
A,@RW2+00
;AH
MOVW
A,@RW2+00
;AL
XORW
A
;XOR of AH and AL (1 when the values differ)
AND
A,#40H
;Is the DQ6 toggle bit different?
BNZ
ERROR
;To ERROR when the DQ6 toggle bit is different
;
///////////////////////////////////////
;
Write termination check (FMCS-RDY)
;
///////////////////////////////////////
;
///////////////////////////////////////
NTOW
MOVW
A,FMCS
AND
A,#10H
;Extraction of FMCS RDY bit (bit 4)
BZ
WRITE
;End of write?
MOV
FMCS,#00H
;Write mode release
;
/////////////////////////////////////////////////////
;
Write data output
;
/////////////////////////////////////////////////////
MOVW
RW2,#0000H
;Write data output
MOVW
A,@RW2+00
MOV
PDR2,A
;
WAIT2
BBC
PDR3:1,WAIT2
;PDR3: 1(sector erase start at high level)
;
;/////////////////////////////////////////////
;Sector erase (SA1)
;/////////////////////////////////////////////
MOV
@RW2+00,#0000H
;Address initialization
MOV
FMCS,#20H
;Erase mode setting
MOVW
ADB:COMADR1,#00AAH
;Flash erase command 1
MOVW
ADB:COMADR2,#0055H
;Flash erase command 2
MOVW
ADB:COMADR1,#0080H
;Flash erase command 3
MOVW
ADB:COMADR1,#00AAH
;Flash erase command 4
MOVW
ADB:COMADR2,#0055H
;Flash erase command 5
MOV
@RW2+00,#0030H
;Issuance of erase command 6 to the sector
to be erased
ELS
;Wait time check
;
///////////////////////////////////////////////////////////////////
;
ERROR when the time limit excess check flag is set and toggle operation is
;
in progress
;
///////////////////////////////////////////////////////////////////
MOVW
A,@RW2+00
AND
A,#20H
;DQ5 time limit check
BZ
NTOE
;Time limit over
MOVW
A,@RW2+00
;AH High and Low are alternately output from
MOVW
A,@RW2+00
;AL DQ6 per read during write operation.
XORW
A
;XOR of AH and AL (If the DQ6 value differs,
;
write operation is in progress (1)).
AND
A,#40H
;Is the DQ6 toggle bit High?
BNZ
ERROR
;ERROR when the DQ6 toggle bit is High
521
CHAPTER 25 1M/2M/3M-BIT FLASH MEMORY
;
;
;
NTOE
///////////////////////////////////////
Erase termination check (FMCS-RDY)
///////////////////////////////////////
MOVW
A,FMCS
;
AND
A,#10H
;Extraction of FMCS RDY bit (bit 4)
BZ
ELS
;End of sector erase?
MOV
FMCS,#00H
;FLASH erase mode release
RETP
;Return to the main program
;//////////////////////////////////////////////
;Error
;//////////////////////////////////////////////
ERROR
MOV
FMCS,#00H
;FLASH mode release
MOV
PDR0,#0FFH
;Error handling check
MOV
ADB:COMADR1,#0F0H
;Reset command (read is enabled)
RETP
;Return to the main program
RAMPRG ENDS
;/////////////////////////////////////////////
VECT
CSEG
ABS=0FFH
ORG
0FFDCH
DSL
START
DB
00H
VECT
ENDS
;
522
CHAPTER 26
EXAMPLES OF MB90F947
SYNCHRONOUS SERIAL
PROGRAMMING
CONNECTION
This chapter provides examples of F2MC-16LX
MB90F947 synchronous serial programming connection.
26.1 Basic Configuration of MB90F947 Synchronous Serial
Programming Connection
26.2 Example of Synchronous Serial Programming Connection (User
Power Supply Used)
26.3 Example of Synchronous Serial Programming Connection (Power
Supplied from the Programmer)
26.4 Example of Minimum Connection to the Flash Microcomputer
Programmer (User Power Supply Used)
26.5 Example of Minimum Connection to the Flash Microcomputer
Programmer (Power Supplied from the Programmer)
523
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION
26.1
Basic Configuration of MB90F947 Synchronous Serial
Programming Connection
The MB90F947 supports flash ROM serial onboard programming (Fujitsu standard).
This section describes the specifications.
■ Basic Configuration of MB90F947 Synchronous Serial Programming Connection
The AF220/AF210/AF120/AF110 flash microcomputer programmer from Yokogawa Digital Computer
Corporation is used for Fujitsu standard serial onboard programming.
Figure 26.1-1 Fujitsu Standard Serial Onboard Programming of MB90F947
Host interface cable (AZ201)
AF220/AF210/
AF120/AF110
flash
microcomputer
programmer
+
memory card
General-purpose
common cable (AZ210)
CLK synchronous serial
MB90F947
Stand-alone operation enabled
Note:
Ask the company representative from Yokogawa Digital Computer Corporation for details about the
functions and operations of the AF220/AF210/AF120/AF110 flash microcomputer programmer,
general-purpose common cable for connection (AZ210), and connectors.
524
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION
Table 26.1-1 Pins Used for Fujitsu Standard Synchronous Serial Onboard Programming
Pin
Function
Additional information
MD2, MD1
MD0
Mode pins
Controls programming mode from the flash microcomputer
programmer.
X0, X1
Oscillation pins
In programming mode, the CPU internal operation clock signal is
one multiple of the PLL clock signal frequency. Therefore, because
the oscillation clock frequency becomes the internal operation clock
signal, the oscillator used for serial reprogramming is 3 MHz to 20
MHz.
P00, P01
Programming activation pins
Input a low level to P00 and a high level to P01.
RST
Reset pin
SIN4
Serial data input pin
SOT4
Serial data output pin
SCK4
Serial clock signal input pin
C
C pin
This external capacitor pin is used to stabilize the power supply.
Connect a ceramic capacitor of approximately 0.1 or more μF to the
outside.
VCC
Power voltage supply pin
If the programming voltage (5 V ± 10%) is supplied from the user
system, the flash microcomputer programmer need not be
connected. Connect so that the power supply of the user side is not
short-circuited.
VSS
GND pin
Common to the ground of the flash microcomputer programmer.
−
Serial input-output is used.
Even if the P00, P01, SIN4, SOT4, and SCK4 pins are used for the user system, the control circuit shown in
the figure below is required. The /TICS signal of the flash microcomputer programmer can be used to
disconnect the user circuit during serial programming.
Sections "26.2 Example of Synchronous Serial Programming Connection (User Power Supply Used)" to
"26.5 Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from
the Programmer)" present examples the following four types of serial programming connection. See each
Section as required.
•
Synchronous serial programming connection (user power supply used)
•
Synchronous serial programming connection (power supplied from the programmer)
•
Minimum connection to the flash microcomputer programmer (user power supply used)
•
Minimum connection to the flash microcomputer programmer (power supplied from the programmer)
525
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION
Figure 26.1-2 Connecting User Circuitry for Serial Programming
AF220/AF210/
AF120/AF110
write control pin
MB90F947
write control pin
AF220/AF210/
AF120/AF110
/TICS pin
User
Table 26.1-2 System Configuration of Flash Microcomputer Programmers (Manufactured
by Yokogawa Digital Computer Corporation)
Model
Main unit
Function
AF220/AC4P
Ethernet interface built-in model and 100 to 220 V AC power adapter
AF210/AC4P
Standard model and 100 to 220 V AC power adapter
AF120/AC4P
Single-key Ethernet interface built-in model and 100 to 220 V AC
power adapter
AF110/AC4P
Single-key model and 100 to 220 V AC power adapter
AZ221
PC/AT RS232C cable for programmer
AZ210
Standard target probe (a) with a 1 m cable
FF201
Fujitsu F2MC-16LX flash microcomputer control module
AZ290
Remote controller
/P2
2 Mbytes PC card (optional) for flash memory sizes up to 128 Kbytes
/P4
4 Mbytes PC card (optional) for flash memory sizes up to 512 Kbytes
Inquiries: Yokogawa Digital Computer Corporation
Telephone number: (81)-42-333-6224
Note:
Although the AF200 flash microcomputer programmer is no longer manufactured, the programmer still
can be used in combination with the FF201 control module.
Examples of serial programming connection are given in Sections "26.2 Example of Synchronous
Serial Programming Connection (User Power Supply Used)" and "26.3 Example of Synchronous Serial
Programming Connection (Power Supplied from the Programmer)".
526
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION
■ Oscillating Clock Frequency and Serial Clock Input Frequency
The equation listed below can be used to calculate the serial clock frequencies that can be used for the
MB90F947. Set an appropriate serial clock input frequency in the flash microcomputer programmer
according to the oscillating clock frequency in use.
fSC = 0.125 × fOSC,
where fSC is the serial clock frequency and fOSC is the oscillating clock frequency.
Table 26.1-3 Examples of Serial Clock Frequencies that can be Used
Oscillating clock
frequency
Maximum serial clock
frequency that can be
used for microcomputers
Maximum serial clock
frequency that can be
used for the AF220,
AF210, AF120, and
AF110
Maximum serial clock
frequency that can be
used for the AF200
4 MHz
500 kHz
500 kHz
500 kHz
8 MHz *
1 MHz
850 kHz
500 kHz
16 MHz *
2 MHz
1.25 MHz
500 kHz
*: External clock only.
527
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION
26.2
Example of Synchronous Serial Programming Connection
(User Power Supply Used)
Figure 26.2-1 is an example of a synchronous serial programming connection for
internal vector modes (single-chip mode) when the user power supply is used.
The value "1" and "0" are input to mode pins MD2 and MD0 from TAUX3 and TMODE of
the AF220/AF210/AF120/AF110 programmer.
Serial reprogramming mode: MD2, MD1, MD0 = 110.
■ Example of Synchronous Serial Programming Connection (User Power Supply Used)
Figure 26.2-1 Example of Synchronous Serial Programming Connection for MB90F947 Internal Vector
Modes (User Power Supply Used)
AF220/AF210/AF120/AF110
flash microcomputer
programmer
TAUX3
User system
MB90F394H
MB90F947
Connector
DX10-28S or DX20-28S
MD2
(19)
10kΩ
10kΩ
MD1
10kΩ
TMODE
MD0
X0
(12)
X1
TAUX
P00
(23)
10kΩ
/TICS
(10)
User
10kΩ
/TRES
RST
(5)
10kΩ
User
TTXD
TRXD
TCK
TVcc
GND
(13)
(27)
(6)
0.1 or
more μF
(2)
(7, 8,
14,15,
21, 22
1, 28)
P01
C
SIN4
SOT4
SCK4
Vcc
User power
supply
Vss
Pin 14
Pins 3, 4, 9, 11, 16, 17, 18, 20,
24, 25, and 26 are open.
DX10-28S: Right-angle type
DX20-28S: Straight type
528
Pin 1
DX10-28S
DX20-28S
Pin 28
Pin 15
Connector (Hirose Electronics Ltd.)
pin arrangement
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION
•
Even if the SIN4, SOT4, and SCK4 pins are used for the user system, the control circuit shown in the
figure below is required in the same way that it is for P00. The /TICS signal of the flash microcomputer
programmer can be used to disconnect the user circuit during serial programming.
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
Figure 26.2-2 Connecting User Circuitry (detail)
AF220/AF210/
AF120/AF110
write control pin
MB90F947
write control pin
AF220/AF210/
AF120/AF110
/TICS pin
User
529
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION
26.3
Example of Synchronous Serial Programming Connection
(Power Supplied from the Programmer)
Figure 26.3-1 is an example of a synchronous serial programming connection for
internal vector modes (single-chip mode) when power is supplied from the programmer.
The value "1" and "0" are input to mode pins MD2 and MD0 from TAUX3 and TMODE of
the AF220/AF210/AF120/AF110 programmer.
Serial reprogramming mode: MD2, MD1, MD0 = 110.
■ Example of Synchronous Serial Programming Connection (Power Supplied from the
Programmer)
Figure 26.3-1 Example of Synchronous Serial Programming Connection for MB90F947 Internal Vector
Modes (Power Supplied from the Programmer)
AF220/AF210/AF120/AF110
flash microcomputer
programmer
TAUX3
User system
MB90F394H
MB90F947
Connector
DX10-28S or DX20-28S
MD2
(19)
10kΩ
10kΩ
MD1
10kΩ
TMODE
MD0
X0
(12)
X1
TAUX
P00
(23)
10kΩ
/TICS
(10)
User
10kΩ
/TRES
RST
(5)
10kΩ
User
TTXD
TRXD
TCK
TVcc
GND
(13)
(27)
(6)
0.1 or
more μF
(2)
(7, 8,
14,15,
21, 22
1, 28)
User power
supply
P01
C
SIN4
SOT4
SCK4
Vcc
Vss
Pin 14
Pins 3, 4, 9, 11, 16, 17, 18, 20,
24, 25, and 26 are open.
DX10-28S: Right-angle type
DX20-28S: Straight type
530
Pin 1
DX10-28S
DX20-28S
Pin 28
Pin 15
Connector (Hirose Electronics Ltd.)
pin arrangement
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION
•
Even if the SIN4, SOT4, and SCK4 pins are used for the user system, the control circuit shown in the
figure below is required in the same way that it is for P00. The /TICS signal of the flash microcomputer
programmer can be used to disconnect the user circuit during serial programming.
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
•
When the programming power is supplied from the AF220/AF210/AF120/AF110, be careful not to
short-circuit the user power supply.
Figure 26.3-2 Connecting User Circuitry (detail)
AF220/AF210/
AF120/AF110
write control pin
MB90F947
write control pin
AF220/AF210/
AF120/AF110
/TICS pin
User
531
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION
26.4
Example of Minimum Connection to the Flash
Microcomputer Programmer (User Power Supply Used)
Figure 26.4-1 is an example of the minimum connection to the flash microcomputer
programmer when the user power supply is used.
Serial reprogramming mode: MD2, MD1, MD0 = 110.
■ Example of Minimum Connection to the Flash Microcomputer Programmer
(User Power Supply Used)
For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcomputer programmer need
not be connected if the pins are set as described below.
Figure 26.4-1 Example of Minimum Connection to the Flash Microcomputer Programmer
(User Power Supply Used)
AF220/AF210/AF120/AF110 User system
flash microcomputer
programmer
MB90F394H
MB90F947
1 for serial
reprogramming
10 kΩ
MD2
1 for serial
reprogramming
10 kΩ
10 kΩ
MD1
10 kΩ
10 kΩ
MD0
0 for serial
reprogramming
10 kΩ
X0
X1
10 kΩ
0 for serial
reprogramming
P00
10 kΩ
User circuit
P01
1 for serial reprogramming
User
circuit
Connector
DX10-28S or
DX20-28S
/TRES
TTXD
TRXD
TCK
TVcc
(5)
(13)
(27)
(6)
(2)
GND
(7, 8,
14,15,
21, 22,
1, 28)
0.1 or
more μF
10 kΩ
RST
SIN4
SOT4
SCK4
Vcc
User power supply
Pins 3, 4, 9, 10, 11, 12, 16, 17, 18, 19,
20, 23, 24, 25, and 26 are open.
DX10-28S: Right-angle type
DX20-28S: Straight type
532
C
Vss
Pin 14
Pin 1
Pin 28
Pin 15
DX10-28S
DX20-28S
Connector (Hirose Electronics Ltd.)
pin arrangement
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION
•
Even if the SIN4, SOT4, and SCK4 pins are used for the user system, the control circuit shown in the
figure below is required. The /TICS signal of the flash microcomputer programmer can be used to
disconnect the user circuit during serial programming.
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
Figure 26.4-2 Connecting User Circuitry (detail)
AF220/AF210/
AF120/AF110
write control pin
MB90F947
write control pin
AF220/AF210/
AF120/AF110
/TICS pin
User
533
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION
26.5
Example of Minimum Connection to the Flash
Microcomputer Programmer (Power Supplied from the
Programmer)
Figure 26.5-1 is an example of the minimum connection to the flash microcomputer
programmer when power is supplied from the Programmer.
Serial reprogramming mode: MD2, MD1, MD0 = 110.
■ Example of Minimum Connection to the Flash Microcomputer Programmer
(Power Supplied from the Programmer)
For a flash memory write, the MD2, MD1, MD0, and P00 pins and flash microcomputer programmer need
not be connected if the pins are set as described below.
Figure 26.5-1 Example of Minimum Connection to the Flash Microcomputer Programmer
(Power Supplied from the Programmer)
AF220/AF210/AF120/AF110 User system
flash microcomputer
programmer
MB90F394H
MB90F947
1 for serial
reprogramming
MD2
1 for serial
reprogramming
MD1
MD0
0 for serial
reprogramming
X0
X1
P00
0 for serial
reprogramming
User circuit
P01
1 for serial reprogramming
User
circuit
C
Connector
DX10-28S or
DX20-28S
/TRES
TTXD
TRXD
TCK
(5)
(13)
(27)
(6)
(2)
(3)
(16)
RST
SIN4
SOT4
SCK4
Vcc
TVcc
GND
(7,8,
14,15,
21, 22,
1, 28)
Pins 4, 9, 10, 11, 12, 17, 18, 19,
20, 23, 24, 25, and 26 are open.
DX10-28S: Right-angle type
DX20-28S: Straight type
Vss
Pin 14
Pin 1
Pin 28
Pin 15
DX10-28S
DX20-28S
Connector (Hirose Electronics Ltd.)
pin arrangement
534
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION
•
Even if the SIN4, SOT4, and SCK4 pins are used for the user system, the control circuit shown in the
figure below is required. The /TICS signal of the flash microcomputer programmer can be used to
disconnect the user circuit during serial programming.
•
Connect the AF220/AF210/AF120/AF110 while the user power is off.
•
When the programming power is supplied from the AF220/AF210/AF120/AF110, be careful not to
short-circuit the user power supply.
Figure 26.5-2 Connecting User Circuitry (detail)
AF220/AF210/
AF120/AF110
write control pin
MB90F947
write control pin
AF220/AF210/
AF120/AF110
/TICS pin
User
535
CHAPTER 26 EXAMPLES OF MB90F947 SYNCHRONOUS SERIAL PROGRAMMING CONNECTION
536
APPENDIX
The appendixes provide I/O maps, instructions, and
other information.
APPENDIX A I/O Maps
APPENDIX B Instructions
APPENDIX C Timing Diagrams in Flash Memory Mode
APPENDIX D List of Interrupt Vectors
537
APPENDIX A I/O Maps
APPENDIX A I/O Maps
Table A-1 lists addresses to be assigned to the registers in the peripheral blocks.
■ I/O Maps
Table A-1 I/O Map (1 / 5)
Address
Register
Abbreviation
Access
Peripheral
Initial value
000000H
Port data register (For port 0)
PDR0
R/W
Port 0
XXXXXXXXB
000001H
Port data register (For port 1)
PDR1
R/W
Port 1
XXXXXXXXB
000002H
Port data register (For port 2)
PDR2
R/W
Port 2
XXXXXXXXB
000003H
Port data register (For port 3)
PDR3
R/W
Port 3
XXXXXXXXB
000004H
Port data register (For port 4)
PDR4
R/W
Port 4
XXXXXXXXB
000005H
Port data register (For port 5)
PDR5
R/W
Port 5
XXXXXXXXB
000006H
Port data register (For port 6)
PDR6
R/W
Port 6
XXXXXXXXB
000007H
Reserved
000008H
Port data register (For port 8)
PDR8
R/W
Port 8
XXXXXXXXB
000009H
Port data register (For port 9)
PDR9
R/W
Port 9
XXXXXXXXB
00000AH
Port data register (For port A)
PDRA
R/W
Port A
XXXXXXXXB
00000BH
Port data register (For port B)
PDRB
R/W
Port B
XXXXXXXXB
00000CH
Analog Input Enable register 0
ADER0
R/W
Port 6, A/D
11111111B
00000DH
Analog Input Enable register 1/
ADC Select
ADER1
R/W
Port B, A/D
01111111B
Input Level Select Register
(MB90V390HA/HB only)
ILSR
R/W
Ports
000010H
Port direction register (For port 0)
DDR0
R/W
Port 0
00000000B
000011H
Port direction register (For port 1)
DDR1
R/W
Port 1
00000000B
000012H
Port direction register (For port 2)
DDR2
R/W
Port 2
00000000B
000013H
Port direction register (For port 3)
DDR3
R/W
Port 3
00000000B
000014H
Port direction register (For port 4)
DDR4
R/W
Port 4
00000000B
000015H
Port direction register (For port 5)
DDR5
R/W
Port 5
00000000B
00000EH
00000FH
538
00000000B
00000000B
APPENDIX A I/O Maps
Table A-1 I/O Map (2 / 5)
Address
Register
000016H
Port direction register (For port 6)
Abbreviation
DDR6
000017H
Access
R/W
Peripheral
Initial value
Port 6
00000000B
Reserved
000018H
Port direction register (For port 8)
DDR8
R/W
Port 8
XXXXXX00B
000019H
Port direction register (For port 9)
DDR9
R/W
Port 9
00000000B
00001AH
Port direction register (For port A)
DDRA
R/W
Port A
00000000B
00001BH
Port direction register (For port B)
DDRB
R/W
Port B
00000000B
UART0
00000100B
00001CH to
00001FH
Reserved
000020H
Serial Mode Control 0
UMC0
R/W
000021H
Status 0
USR0
R/W
00010000B
000022H
Input/Output Data 0
UIDR0/
UODR0
R/W
XXXXXXXXB
000023H
Rate and Data 0
URD0
R/W
0000000XB
000024H to
00002BH
Reserved
00002CH
Serial Mode Control
SMCS4
R/W
00002DH
Serial Mode Control
SMCS4
R/W
00000010B
00002EH
Serial Data
SDR4
R/W
XXXXXXXXB
00002FH
Serial IO Prescaler/Edge Selector
CDCR4
R/W
0X0X0000B
000030H
External Interrupt Enable
ENIR
R/W
000031H
External Interrupt Request
EIRR
R/W
XXXXXXXXB
000032H
External Interrupt Level
ELVR
R/W
00000000B
000033H
External Interrupt Level
ELVR
R/W
00000000B
000034H
A/D Control Status 0
ADCS0
R/W
000035H
A/D Control Status 1
ADCS1
R/W
000036H
A/D Data 0
ADCR0
R
000037H
A/D Data 1
ADCR1
R/W
Serial IO
External Interrupt
A/D Converter
XXXX0000B
00000000B
00000000B
00000000B
XXXXXXXXB
00000XXXB
539
APPENDIX A I/O Maps
Table A-1 I/O Map (3 / 5)
Address
Register
Abbreviation
Access
Peripheral
Initial value
000038H
PPG0 operation mode control
register
PPGC0
R/W
000039H
PPG1 operation mode control
register
PPGC1
R/W
0X000001B
00003AH
PPG0 and PPG1 clock select
register
PPG01
R/W
000000XXB
00003BH
16-bit Programable
Pulse Generator 0/1
0X000XX1B
Reserved
00003CH
PPG2 operation mode control
register
PPGC2
R/W
00003DH
PPG3 operation mode control
register
PPGC3
R/W
0X000001B
00003EH
PPG2 and PPG3 clock select
register
PPG23
R/W
000000XXB
00003FH
16-bit Programable
Pulse Generator 2/3
0X000XX1B
Reserved
000040H
PPG4 operation mode control
register
PPGC4
R/W
000041H
PPG5 operation mode control
register
PPGC5
R/W
0X000001B
000042H
PPG4 and PPG5 clock select
register
PPG45
R/W
000000XXB
000043H
16-bit Programable
Pulse Generator 4/5
0X000XX1B
Reserved
000044H
PPG6 operation mode control
register
PPGC6
R/W
000045H
PPG7 operation mode control
register
PPGC7
R/W
0X000001B
000046H
PPG6 and PPG7 clock select
register
PPG67
R/W
000000XXB
000047H
16-bit Programable
Pulse Generator 6/7
0X000XX1B
Reserved
000048H
PPG8 operation mode control
register
PPGC8
R/W
000049H
PPG9 operation mode control
register
PPGC9
R/W
0X000001B
00004AH
PPG8 and PPG9 clock select
register
PPG89
R/W
000000XXB
00004BH
540
Reserved
16-bit Programable
Pulse Generator 8/9
0X000XX1B
APPENDIX A I/O Maps
Table A-1 I/O Map (4 / 5)
Address
Register
Abbreviation
Access
Peripheral
Initial value
00004CH
PPGA operation mode control
register
PPGCA
R/W
00004DH
PPGB operation mode control
register
PPGCB
R/W
0X000001B
00004EH
PPGA and PPGB clock select
register
PPGAB
R/W
000000XXB
00004FH
16-bit Programable
Pulse Generator A/B
0X000XX1B
Reserved
000050H
Timer Control Status 0
TMCSR0
R/W
000051H
Timer Control Status 0
TMCSR0
R/W
000052H to
000053H
16-bit Reload Timer 0
00000000B
XXXX0000B
Reserved
000054H
Input Capture Control Status 0/1
ICS01
R/W
Input Capture 0/1
00000000B
000055H
Input Capture Control Status 2/3
ICS23
R/W
Input Capture 2/3
00000000B
000056H
Input Capture Control Status 4/5
ICS45
R/W
Input Capture 4/5
00000000B
Output Compare 0/1
0000XX00B
000057H
Reserved
000058H
Output Compare Control Status 0
OCS0
R/W
000059H
Output Compare Control Status 1
OCS1
R/W
00005AH
Output Compare Control Status 2
OCS2
R/W
00005BH
Output Compare Control Status 3
OCS3
R/W
00005CH to
00006EH
00006FH
Output Compare 2/3
0000XX00B
0XX00000B
Reserved
ROM Mirror
ROMM
000070H to
00007FH
000080H to
00008FH
0XX00000B
W
ROM Mirror
XXXXXXX1B
Reserved
Reserved for CAN Interface 1. Refer to section about CAN Controller
000090H to
00009DH
Reserved
00009EH
ROM Correction Control Status 0
PACSR0
R/W
ROM Correction 0
00000000B
00009FH
Delayed Interrupt/release
DIRR
R/W
Delayed Interrupt
XXXXXXX0B
0000A0H
Low-power Mode
LPMCR
R/W
Low Power Controller
00011000B
0000A1H
Clock Selector
CKSCR
R/W
Low Power Controller
11111100B
541
APPENDIX A I/O Maps
Table A-1 I/O Map (5 / 5)
Address
Register
Abbreviation
0000A2H to
0000A7H
Access
Peripheral
Initial value
Reserved
0000A8H
Watch-dog Control
WDTC
R/W
Watch-dog Timer
XXXXX111B
0000A9H
Timebase Timer Control
TBTC
R/W
Timebase Timer
1XX00100B
Flash Memory
000X0000B
Interrupt controller
00000111B
0000AAH to
0000ADH
0000AEH
Reserved
Flash Control Status
(Flash devices only. Otherwise
reserved)
FMCS
0000AFH
R/W
Reserved
0000B0H
Interrupt control register 00
ICR00
R/W
0000B1H
Interrupt control register 01
ICR01
R/W
00000111B
0000B2H
Interrupt control register 02
ICR02
R/W
00000111B
0000B3H
Interrupt control register 03
ICR03
R/W
00000111B
0000B4H
Interrupt control register 04
ICR04
R/W
00000111B
0000B5H
Interrupt control register 05
ICR05
R/W
00000111B
0000B6H
Interrupt control register 06
ICR06
R/W
00000111B
0000B7H
Interrupt control register 07
ICR07
R/W
00000111B
0000B8H
Interrupt control register 08
ICR08
R/W
00000111B
0000B9H
Interrupt control register 09
ICR09
R/W
00000111B
0000BAH
Interrupt control register 10
ICR10
R/W
00000111B
0000BBH
Interrupt control register 11
ICR11
R/W
00000111B
0000BCH
Interrupt control register 12
ICR12
R/W
00000111B
0000BDH
Interrupt control register 13
ICR13
R/W
00000111B
0000BEH
Interrupt control register 14
ICR14
R/W
00000111B
0000BFH
Interrupt control register 15
ICR15
R/W
00000111B
0000COH to
0000FFH
542
Reserved
APPENDIX A I/O Maps
■ I/O Map (003XXX Addresses)
Table A-2 I/O Map (003XXX Addresses) (1 / 5)
Address
Register
Abbreviation
Access
Peripheral
16-bit Programable
Pulse Generator 0/1
Initial value
003500H
Reload L
PRLL0
R/W
003501H
Reload H
PRLH0
R/W
XXXXXXXXB
003502H
Reload L
PRLL1
R/W
XXXXXXXXB
003503H
Reload H
PRLH1
R/W
XXXXXXXXB
003504H
Reload L
PRLL2
R/W
003505H
Reload H
PRLH2
R/W
XXXXXXXXB
003506H
Reload L
PRLL3
R/W
XXXXXXXXB
003507H
Reload H
PRLH3
R/W
XXXXXXXXB
003508H
Reload L
PRLL4
R/W
003509H
Reload H
PRLH4
R/W
XXXXXXXXB
00350AH
Reload L
PRLL5
R/W
XXXXXXXXB
00350BH
Reload H
PRLH5
R/W
XXXXXXXXB
00350CH
Reload L
PRLL6
R/W
00350DH
Reload H
PRLH6
R/W
XXXXXXXXB
00350EH
Reload L
PRLL7
R/W
XXXXXXXXB
00350FH
Reload H
PRLH7
R/W
XXXXXXXXB
003510H
Reload L
PRLL8
R/W
003511H
Reload H
PRLH8
R/W
XXXXXXXXB
003512H
Reload L
PRLL9
R/W
XXXXXXXXB
003513H
Reload H
PRLH9
R/W
XXXXXXXXB
003514H
Reload L
PRLLA
R/W
003515H
Reload H
PRLHA
R/W
XXXXXXXXB
003516H
Reload L
PRLLB
R/W
XXXXXXXXB
003517H
Reload H
PRLHB
R/W
XXXXXXXXB
16-bit Programable
Pulse Generator 2/3
16-bit Programable
Pulse Generator 4/5
16-bit Programable
Pulse Generator 6/7
16-bit Programable
Pulse Generator 8/9
16-bit Programable
Pulse Generator A/B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
543
APPENDIX A I/O Maps
Table A-2 I/O Map (003XXX Addresses) (2 / 5)
Address
Register
Abbreviation
Access
Peripheral
Initial value
003518H
Serial Mode Register
SMR3
R/W
003519H
Serial Control Register
SCR3
R/W
00000000B
00351AH
Reception/Transmission Data
Register
RDR3/TDR3
R/W
00000000B
00351BH
Serial Status Register
SSR3
R/W
00001000B
00351CH
Extended Communication
Control Register
ECCR3
R/W
000000XXB
00351DH
Extended Status/Control
Register
ESCR3
R/W
00000X00B
00351EH
Baud Rate Register 0
BGR03
R/W
00000000B
00351FH
Baud Rate Register 1
BGR13
R/W
00000000B
003520H
Input Capture 0
IPCP0
R
003521H
Input Capture 0
IPCP0
R
XXXXXXXXB
003522H
Input Capture 1
IPCP1
R
XXXXXXXXB
003523H
Input Capture 1
IPCP1
R
XXXXXXXXB
003524H
Input Capture 2
IPCP2
R
003525H
Input Capture 2
IPCP2
R
XXXXXXXXB
003526H
Input Capture 3
IPCP3
R
XXXXXXXXB
003527H
Input Capture 3
IPCP3
R
XXXXXXXXB
003528H
Input Capture 4
IPCP4
R
003529H
Input Capture 4
IPCP4
R
XXXXXXXXB
00352AH
Input Capture 5
IPCP5
R
XXXXXXXXB
00352BH
Input Capture 5
IPCP5
R
XXXXXXXXB
00352CH
Timer Data 0
TCDT0
R/W
00352DH
Timer Data 0
TCDT0
R/W
00000000B
00352EH
Timer Control 0
TCCS0
R/W
00000000B
00352FH
Timer Control 0
TCCS0
R/W
0XXXXXXXB
544
UART3
Input Capture 0/1
Input Capture 2/3
Input Capture 4/5
IO Timer 0
00000000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
00000000B
APPENDIX A I/O Maps
Table A-2 I/O Map (003XXX Addresses) (3 / 5)
Address
Register
Abbreviation
Access
Peripheral
Initial value
003530H
Output Compare 0
OCCP0
R/W
003531H
Output Compare 0
OCCP0
R/W
XXXXXXXXB
003532H
Output Compare 1
OCCP1
R/W
XXXXXXXXB
003533H
Output Compare 1
OCCP1
R/W
XXXXXXXXB
003534H
Output Compare 2
OCCP2
R/W
003535H
Output Compare 2
OCCP2
R/W
XXXXXXXXB
003536H
Output Compare 3
OCCP3
R/W
XXXXXXXXB
003537H
Output Compare 3
OCCP3
R/W
XXXXXXXXB
003538H to
00353BH
Output Compare 0/1
Output Compare 2/3
XXXXXXXXB
XXXXXXXXB
Reserved
00353CH
Timer Data 1
TCDT1
R/W
00353DH
Timer Data 1
TCDT1
R/W
00000000B
00353EH
Timer Control 1
TCCS1
R/W
00000000B
00353FH
Timer Control 1
TCCS1
R/W
0XXXXXXXB
003540H
Timer 0/Reload 0
TMR0/
TMRLR0
R/W
003541H
Timer 0/Reload 0
TMR0/
TMRLR0
R/W
003542H
to 00356DH
00356EH
00356F to
00359FH
IO Timer 1
16-bit Reload Timer 0
00000000B
XXXXXXXXB
XXXXXXXXB
Reserved
CAN Direct Mode Register
CDMR
R/W
CAN clock sync
XXXXXXX0B
Reserved
545
APPENDIX A I/O Maps
Table A-2 I/O Map (003XXX Addresses) (4 / 5)
Address
Register
Abbreviation
Access
Peripheral
Initial value
0035A0H
I2C bus status register
IBSR
R
0035A1H
I2C bus control register
IBCR
R/W
00000000B
0035A2H
I2C ten bit slave address
register
ITBAL
R/W
00000000B
ITBAH
R/W
00000000B
ITMKL
R/W
11111111B
ITMKH
R/W
00111111B
0035A3H
0035A4H
0035A5H
I2C ten bit address mask
register
I2C Interface
00000000B
0035A6H
I2C seven bit slave address
register
ISBA
R/W
00000000B
0035A7H
I2C seven bit address mask
register
ISMK
R/W
01111111B
0035A8H
I2C data register
IDAR
R/W
00000000B
0035A9H to
0035AAH
0035ABH
Reserved
I2C clock control register
ICCR
0035ACH to
0035C1H
0035C2H
R/W
I2C Interface
00011111B
Phase Modulator
0XXXXXXXB
Reserved
Clock Modulator Control
Register
CMCR
0035C3H to
0035C8H
R/W
Reserved
0035C9H
Input Capture Edge 0/1
ICE01
R/W
Input Capture 0/1
XXXXX0XXB
0035CAH
Input Capture Edge 2/3
ICE23
R
Input Capture 2/3
XXXXXXXXB
0035CBH
Input Capture Edge 4/5
ICE45
R/W
Input Capture 4/5
XXXXX0XXB
PLL
XXXX0000
ROM Correction 0
XXXXXXXXB
0035CCH to
0035CEH
0035CFH
Reserved
PLL and Special
Configuration Control
Register
PSCCR
0035D0H to
0035DFH
W
Reserved
0035E0H
ROM Correction Address 0
PADR0
R/W
0035E1H
ROM Correction Address 0
PADR0
R/W
546
XXXXXXXXB
APPENDIX A I/O Maps
Table A-2 I/O Map (003XXX Addresses) (5 / 5)
Address
Register
Abbreviation
Access
Peripheral
Initial value
0035E2H
ROM Correction Address 0
PADR0
R/W
XXXXXXXXB
0035E3H
ROM Correction Address 1
PADR1
R/W
XXXXXXXXB
0035E4H
ROM Correction Address 1
PADR1
R/W
XXXXXXXXB
0035E5H
ROM Correction Address 1
PADR1
R/W
XXXXXXXXB
0035E6H
ROM Correction Address 2
PADR2
R/W
XXXXXXXXB
0035E7H
ROM Correction Address 2
PADR2
R/W
XXXXXXXXB
0035E8H
ROM Correction Address 2
PADR2
R/W
XXXXXXXXB
0035E9H to
0037FFH
Reserved
003800H to
0038FFH
Reserved for CAN Interface 1. Refer to section about CAN Controller
003900H to
0039FFH
Reserved for CAN Interface 1. Refer to section about CAN Controller
003A00 to
003FFFH
Reserved
• "X" indicates an undefined value.
• The addresses between 0000H and 00FFH and 3500H and 3FFFH, which have been reserved for the
main functions of the MCU, the result of read access to these reserved addresses is "X". Write access to
these addresses is not allowed.
● Explanation of write and read
R/W: Both read and write enabled
R: Only read enabled
W: Only write enabled
● Explanation of initial values
0: The initial value of this bit is "0".
1: The initial value of this bit is "1".
X: The initial value of this bit is undefined.
547
APPENDIX B Instructions
APPENDIX B Instructions
APPENDIX B describes the instructions used by the F2MC-16LX.
B.1 Instruction Types
B.2 Addressing
B.3 Direct Addressing
B.4 Indirect Addressing
B.5 Execution Cycle Count
B.6 Effective address field
B.7 How to Read the Instruction List
B.8 F2MC-16LX Instruction List
B.9 Instruction Map
Code: CM44-00202-1E
548
APPENDIX B Instructions
B.1
Instruction Types
The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an
effective address field of each instruction or using the instruction code itself.
■ Instruction Types
The F2MC-16LX supports the following 351 types of instructions:
•
41 transfer instructions (byte)
•
38 transfer instructions (word or long word)
•
42 addition/subtraction instructions (byte, word, or long word)
•
12 increment/decrement instructions (byte, word, or long word)
•
11 comparison instructions (byte, word, or long word)
•
11 unsigned multiplication/division instructions (word or long word)
•
11 signed multiplication/division instructions (word or long word)
•
39 logic instructions (byte or word)
•
6 logic instructions (long word)
•
6 sign inversion instructions (byte or word)
•
1 normalization instruction (long word)
•
18 shift instructions (byte, word, or long word)
•
50 branch instructions
•
6 accumulator operation instructions (byte or word)
•
28 other control instructions (byte, word, or long word)
•
21 bit operation instructions
•
10 string instructions
549
APPENDIX B Instructions
B.2
Addressing
With the F2MC-16LX, the address format is determined by the instruction effective
address field or the instruction code itself (implied). When the address format is
determined by the instruction code itself, specify an address in accordance with the
instruction code used. Some instructions permit the user to select several types of
addressing.
■ Addressing
The F2MC-16LX supports the following 23 types of addressing:
550
•
Immediate (#imm)
•
Register direct
•
Direct branch address (addr16)
•
Physical direct branch address (addr24)
•
I/O direct (io)
•
Abbreviated direct address (dir)
•
Direct address (addr16)
•
I/O direct bit address (io:bp)
•
Abbreviated direct bit address (dir:bp)
•
Direct bit address (addr16:bp)
•
Vector address (#vct)
•
Register indirect (@RWj j = 0 to 3)
•
Register indirect with post increment (@RWj+ j = 0 to 3)
•
Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
•
Long register indirect with displacement (@RLi + disp8 i = 0 to 3)
•
Program counter indirect with displacement (@PC + disp16)
•
Register indirect with base index (@RW0 + RW7, @RW1 + RW7)
•
Program counter relative branch address (rel)
•
Register list (rlst)
•
Accumulator indirect (@A)
•
Accumulator indirect branch address (@A)
•
Indirectly-specified branch address (@ear)
•
Indirectly-specified branch address (@eam)
APPENDIX B Instructions
■ Effective Address Field
Table B.2-1 lists the address formats specified by the effective address field.
Table B.2-1 Effective Address Field
Code
Representation
00
R0
RW0
RL0
01
R1
RW1
(RL0)
02
R2
RW2
RL1
03
R3
RW3
(RL1)
04
R4
RW4
RL2
05
R5
RW5
(RL2)
06
R6
RW6
RL3
07
R7
RW7
(RL3)
08
@RW0
09
@RW1
Address format
Default bank
Register direct: Individual parts correspond to the
byte, word, and long word types in order from the
left.
None
DTB
DTB
Register indirect
0A
@RW2
ADB
0B
@RW3
SPB
0C
@RW0+
DTB
0D
@RW1+
DTB
Register indirect with post increment
0E
@RW2+
ADB
0F
@RW3+
SPB
10
@RW0+disp8
DTB
11
@RW1+disp8
DTB
Register indirect with 8-bit displacement
12
@RW2+disp8
ADB
13
@RW3+disp8
SPB
14
@RW4+disp8
DTB
15
@RW5+disp8
DTB
Register indirect with 8-bit displacement
16
@RW6+disp8
ADB
17
@RW7+disp8
SPB
18
@RW0+disp16
DTB
19
@RW1+disp16
DTB
Register indirect with 16-bit displacement
1A
@RW2+disp16
ADB
1B
@RW3+disp16
SPB
1C
@RW0+RW7
Register indirect with index
DTB
1D
@RW1+RW7
Register indirect with index
DTB
1E
@PC+disp16
PC indirect with 16-bit displacement
PCB
1F
addr16
Direct address
DTB
551
APPENDIX B Instructions
B.3
Direct Addressing
An operand value, register, or address is specified explicitly in direct addressing mode.
■ Direct Addressing
● Immediate addressing (#imm)
Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32).
Figure B.3-1 Example of Immediate Addressing (#imm)
MOVW A, #01212H (This instruction stores the operand value in A.)
Before execution
A 2233
4455
After execution
A 4455
1 2 1 2 (Some instructions transfer AL to AH.)
● Register direct addressing
Specify a register explicitly as an operand. Table B.3-1 lists the registers that can be specified. Figure B.3-2
shows an example of register direct addressing.
Table B.3-1 Direct Addressing Registers
General-purpose register
Special-purpose register
Byte
R0, R1, R2, R3, R4, R5, R6, R7
Word
RW0, RW1, RW2, RW3, RW4, RW5, RW6,
RW7
Long word
RL0, RL1, RL2, RL3
Accumulator
A, AL
Pointer
SP *
Bank
PCB, DTB, USB, SSB, ADB
Page
DPR
Control
PS, CCR, RP, ILM
*: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on
the value of the S flag bit in the condition code register (CCR). For branch instructions, the program
counter (PC) is not specified in an instruction operand but is specified implicitly.
552
APPENDIX B Instructions
Figure B.3-2 Example of Register Direct Addressing
MOV R0, A (This instruction transfers the eight low-order bits of A to the generalpurpose register R0.)
Before execution
A 0716
2534
Memory space
R0
After execution
A 0716
2564
??
Memory space
R0
34
● Direct branch addressing (addr16)
Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which
indicates the branch destination in the logical address space. Direct branch addressing is used for an
unconditional branch, subroutine call, or software interrupt instruction. Bit23 to bit16 of the address are
specified by the program counter bank register (PCB).
Figure B.3-3 Example of Direct Branch Addressing (addr16)
JMP 3B20H (This instruction causes an unconditional branch by direct branch
addressing in a bank.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
62
4F3C21H
20
4F3C22H
3B
JMP 3B20H
553
APPENDIX B Instructions
● Physical direct branch addressing (addr24)
Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical
direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction.
Figure B.3-4 Example of Direct Branch Addressing (addr24)
JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit
addressing.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
PCB 3 3
Memory space
333B20H
Next instruction
4F3C20H
63
4F3C21H
20
4F3C22H
3B
4F3C23H
33
JMPP 333B20H
● I/O direct addressing (io)
Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the
physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB)
and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an
instruction using I/O direct addressing.
Figure B.3-5 Example of I/O Direct Addressing (io)
MOVW A, i : 0C0H (This instruction reads data by I/O direct addressing and stores it
in A.)
Before execution
After execution
554
A 0716
2534
A 2534 FFEE
Memory space
0000C0H
EE
0000C1H
FF
APPENDIX B Instructions
● Abbreviated direct addressing (dir)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB).
Figure B.3-6 Example of Abbreviated Direct Addressing (dir)
MOV S : 20H, A (This instruction writes the contents of the eight low-order bits of A in
abbreviated direct addressing mode.)
Before execution
A 4455
DPR 6 6
After execution
A 4455
DPR 6 6
1212
DTB 7 7
Memory space
776620H
1212
DTB 7 7
??
Memory space
776620H
12
● Direct addressing (addr16)
Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are
specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for
this mode of addressing.
Figure B.3-7 Example of Direct Addressing (addr16)
MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.)
Before execution
After execution
A 2020
A AABB
AABB
0123
DTB 5 5
Memory space
553B21H
01
553B20H
23
DTB 5 5
555
APPENDIX B Instructions
● I/O direct bit addressing (io:bp)
Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp",
where the larger number indicates the most significant bit (MSB) and the lower number indicates the least
significant bit (LSB).
Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp)
SETB i : 0C1H : 0 (This instruction sets bits by I/O direct bit addressing.)
Memory space
Before execution
0000C1H
00
Memory space
After execution
0000C1H
01
● Abbreviated direct bit addressing (dir:bp)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are
specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure B.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp)
SETB S : 10H : 0 (This instruction sets bits by abbreviated direct bit addressing.)
Memory space
Before execution
DTB 5 5
DPR 6 6
556610H
00
Memory space
After execution
DTB 5 5
DPR 6 6
556610H
01
● Direct bit addressing (addr16:bp)
Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register
(DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit
(MSB) and the lower number indicates the least significant bit (LSB).
Figure B.3-10 Example of Direct Bit Addressing (addr16:bp)
SETB 2222H : 0 (This instruction sets bits by direct bit addressing.)
Memory space
Before execution
DTB 5 5
552222H
00
Memory space
After execution
556
DTB 5 5
552222H
01
APPENDIX B Instructions
● Vector Addressing (#vct)
Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector
numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction.
Figure B.3-11 Example of Vector Addressing (#vct)
CALLV #15 (This instruction causes a branch to the address indicated by the interrupt
vector specified in an operand.)
Before execution
PC 0 0 0 0
Memory space
PCB F F
After execution
FFC000H
EF
FFFFE0H
00
FFFFE1H
D0
CALLV #15
PC D 0 0 0
PCB F F
Table B.3-2 CALLV Vector List
Instruction
Vector address L
Vector address H
CALLV #0
XXFFFEH
XXFFFFH
CALLV #1
XXFFFCH
XXFFFDH
CALLV #2
XXFFFAH
XXFFFBH
CALLV #3
XXFFF8H
XXFFF9H
CALLV #4
XXFFF6H
XXFFF7H
CALLV #5
XXFFF4H
XXFFF5H
CALLV #6
XXFFF2H
XXFFF3H
CALLV #7
XXFFF0H
XXFFF1H
CALLV #8
XXFFEEH
XXFFEFH
CALLV #9
XXFFECH
XXFFEDH
CALLV #10
XXFFEAH
XXFFEBH
CALLV #11
XXFFE8H
XXFFE9H
CALLV #12
XXFFE6H
XXFFE7H
CALLV #13
XXFFE4H
XXFFE5H
CALLV #14
XXFFE2H
XXFFE3H
CALLV #15
XXFFE0H
XXFFE1H
Note: A PCB register value is set in XX.
Note:
When the program counter bank register (PCB) is FFH, the vector area overlaps the vector area of
INT #vct8 (#0 to #7). Use vector addressing carefully (see Table B.3-2).
557
APPENDIX B Instructions
B.4
Indirect Addressing
In indirect addressing mode, an address is specified indirectly by the address data of an
operand.
■ Indirect Addressing
● Register indirect addressing (@RWj j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to
23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register
(SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when
RW2 is used.
Figure B.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3)
MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores
it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 0 F
DTB 7 8
● Register indirect addressing with post increment (@RWj+ j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. After operand
operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word).
Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system
stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank
register (ADB) when RW2 is used.
If the post increment results in the address of the register that specifies the increment, the incremented
value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to
writing by an instruction and, therefore, the register that would be incremented becomes write data.
558
APPENDIX B Instructions
Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3)
MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post
increment and stores it in A.)
Before execution
A 0716
2534
Memory space
RW1 D 3 0 F
After execution
DTB 7 8
78D30FH
EE
78D310H
FF
A 2534 FFEE
RW1 D 3 1 1
DTB 7 8
● Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
Memory is accessed using the address obtained by adding an offset to the contents of general-purpose
register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric
values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or
RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is
used, or additional data bank register (ADB) when RW2 or RW6 is used.
Figure B.4-3 Example of Register Indirect Addressing with Offset
(@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+10H)
RW1 D 3 0 F
After execution
DTB 7 8
Memory space
78D31FH
EE
78D320H
FF
A 2534 FFEE
RW1 D 3 0 F
DTB 7 8
559
APPENDIX B Instructions
● Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the
contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value.
Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3)
MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with
an offset and stores it in A.)
Before execution
A 0716
2534
(+25H)
RL2 F 3 8 2
After execution
4B02
Memory space
824B27H
EE
824B28H
FF
A 2534 FFEE
RL2 F 3 8 2
4B02
● Program counter indirect addressing with offset (@PC + disp16)
Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one
word long. Address bits 16 to 23 are specified by the program counter bank register (PCB). Note that the
operand address of each of the following instructions is not deemed to be (next instruction address +
disp16):
•
DBNZ eam, rel
•
DWBNZ eam, rel
•
CBNE eam, #imm8, rel
•
CWBNE eam, #imm16, rel
•
MOV eam, #imm8
•
MOVW eam, #imm16
Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16)
MOVW A, @PC+20H (This instruction reads data by program counter indirect
addressing with an offset and stores it in A.)
Before execution
A 0716
2534
Memory space
PCB C 5 PC 4 5 5 6
After execution
A 2534
FFEE
PCB C 5 PC 4 5 5 A
560
+4
C54556H
73
C54557H
9E
C54558H
20
C54559H
00
C5455AH
.
.
.
+20H
C5457AH
EE
C5457BH
FF
MOVW
A, @PC+20H
APPENDIX B Instructions
● Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7)
Memory is accessed using the address determined by adding RW0 or RW1 to the contents of generalpurpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB).
Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7)
MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with
a base index and stores it in A.)
Before execution
A 0716
RW1 D 3 0 F
WR7 0 1 0 1
After execution
A 2534
RW1 D 3 0 F
2534
+
DTB 7 8
Memory space
78D410H
EE
78D411H
FF
FFEE
DTB 7 8
WR7 0 1 0 1
561
APPENDIX B Instructions
● Program counter relative branch addressing (rel)
The address of the branch destination is a value determined by adding an 8-bit offset to the program
counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is
not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte
bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to
23 are indicated by the program counter bank register (PCB).
Figure B.4-7 Example of Program Counter Relative Branch Addressing (rel)
BRA 10H (This instruction causes an unconditional relative branch.)
Before execution
After execution
PC 3 C 2 0
PC 3 C 3 2
PCB 4 F
PCB 4 F
Memory space
4F3C32H
Next instruction
4F3C21H
10
4F3C20H
60
BRA 10H
● Register list (rlst)
Specify a register to be pushed onto or popped from a stack.
Figure B.4-8 Configuration of the Register List
MSB
LSB
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
A register is selected when the corresponding bit is 1 and deselected when the bit is 0.
562
APPENDIX B Instructions
Figure B.4-9 Example of Register List (rlist)
POPW, RW0, RW4 (This instruction transfers memory data indicated by the SP to
multiple word registers indicated by the register list.)
SP
34FA
SP
34FE
RW0
×× ××
RW0
02 01
RW1
×× ××
RW1
×× ××
RW2
×× ××
RW2
×× ××
RW3
×× ××
RW3
×× ××
RW4
×× ××
RW4
04 03
RW5
×× ××
RW5
×× ××
RW6
×× ××
RW6
×× ××
RW7
×× ××
RW7
×× ××
Memory space
SP
Memory space
01
34FAH
01
34FAH
02
34FBH
02
34FBH
03
34FCH
03
34FCH
04
34FDH
04
34FDH
34FEH
SP
Before execution
34FEH
After execution
● Accumulator indirect addressing (@A)
Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the
accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB).
Figure B.4-10 Example of Accumulator Indirect Addressing (@A)
MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.)
Before execution
A
0716
2534
DTB B B
After execution
A
0716
Memory space
BB2534H
EE
BB2535H
FF
FFEE
DTB B B
563
APPENDIX B Instructions
● Accumulator indirect branch addressing (@A)
The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the
accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are
specified by the program counter bank register (PCB). For the Jump Context (JCTX) instruction, however,
address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for
unconditional branch instructions.
Figure B.4-11 Example of Accumulator Indirect Branch Addressing (@A)
JMP @A (This instruction causes an unconditional branch by accumulator indirect
branch addressing.)
Before execution
PC 3 C 2 0
A 6677
After execution
PC 3 B 2 0
A 6677
PCB 4 F
3B20
Memory space
4F3B20H
Next instruction
4F3C20H
61
JMP @A
PCB 4 F
3B20
● Indirect specification branch addressing (@ear)
The address of the branch destination is the word data at the address indicated by ear.
Figure B.4-12 Example of Indirect Specification Branch Addressing (@ear)
JMP @@RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
After execution
564
PC 3 C 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
PC 3 B 2 0
PCB 4 F
RW0 7 F 4 8
DTB 2 1
Memory space
217F48H
20
217F49H
3B
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
08
JMP @@RW0
APPENDIX B Instructions
● Indirect specification branch addressing (@eam)
The address of the branch destination is the word data at the address indicated by eam.
Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam)
JMP @RW0 (This instruction causes an unconditional branch by register indirect
addressing.)
Before execution
PC 3 C 2 0
PCB 4 F
RW0 3 B 2 0
After execution
PC 3 B 2 0
PCB 4 F
Memory space
4F3B20H
Next instruction
4F3C20H
73
4F3C21H
00
JMP @RW0
RW0 3 B 2 0
565
APPENDIX B Instructions
B.5
Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is
obtained by adding the number of cycles required for each instruction, "correction
value" determined by the condition, and the number of cycles for instruction fetch.
■ Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is obtained by adding the
number of cycles required for each instruction, "correction value" determined by the condition, and the
number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal
ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments.
Therefore, intervening in data access increases the execution cycle count.
Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the
program fetches every byte of an instruction being executed. Therefore, intervening in data access increases
the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register,
internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the
cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register.
Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add
the "access count x cycle count for the halt" as a correction value to the normal execution count.
566
APPENDIX B Instructions
■ Calculating the Execution Cycle Count
Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data.
Table B.5-1 Execution Cycle Counts in Each Addressing Mode
(a) *
Code
Operand
00
|
07
Ri
Rwi
RLi
08
|
0B
Execution cycle count in
each addressing mode
Register access count in
each addressing mode
See the instruction list.
See the instruction list.
@RWj
2
1
0C
|
0F
@RWj+
4
2
10
|
17
@RWi+disp8
2
1
18
|
1B
@RWi+disp16
2
1
1C
1D
1E
1F
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
4
4
2
1
2
2
0
0
*: (a) is used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction List".
567
APPENDIX B Instructions
Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles
(b) byte *
Operand
(c) word *
(d) long *
Cycle
count
Access
count
Cycle
count
Access
count
Cycle
count
Access
count
Internal register
+0
1
+0
1
+0
2
Internal memory
Even address
+0
1
+0
1
+0
2
Internal memory
Odd address
+0
1
+2
2
+4
4
External data bus
16-bit even address
+1
1
+1
1
+2
2
External data bus
16-bit odd address
+1
1
+4
2
+8
4
External data bus
8-bits
+1
1
+4
2
+8
4
*: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in "B.8 F2MC-16LX Instruction
List".
Note:
When an external data bus is used, the cycle counts during which an instruction is made to wait by
ready input or automatic ready must also be added.
Table B.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
-
+2
External data bus 16-bits
-
+3
External data bus 8-bits
+3
-
Notes:
• When an external data bus is used, the cycle counts during which an instruction is made to wait
by ready input or automatic ready must also be added.
• Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the
correction values to calculate the worst case.
568
APPENDIX B Instructions
B.6
Effective address field
Table B.6-1 shows the effective address field.
■ Effective Address Field
Table B.6-1 Effective Address Field
Code
Representation
Address format
Byte count of
extended
address part *
Register direct: Individual parts correspond to
the byte, word, and long word types in order
from the left.
-
Register indirect
0
Register indirect with post increment
0
Register indirect with 8-bit displacement
1
Register indirect with 16-bit displacement
2
00
01
R0
R1
RW0
RW1
RL0
(RL0)
02
03
R2
R3
RW2
RW3
RL1
(RL1)
04
05
R4
R5
RW4
RW5
RL2
(RL2)
06
07
R6
R7
RW6
RW7
RL3
(RL3)
08
09
@RW0
@RW1
0A
0B
@RW2
@RW3
0C
0D
@RW0+
@RW1+
0E
0F
@RW2+
@RW3+
10
11
@RW0+disp8
@RW1+disp8
12
13
@RW2+disp8
@RW3+disp8
14
15
@RW4+disp8
@RW5+disp8
16
17
@RW6+disp8
@RW7+disp8
18
19
@RW0+disp16
@RW1+disp16
1A
1B
@RW2+disp16
@RW3+disp16
1C
1D
@RW0+RW7
@RW1+RW7
Register indirect with index
Register indirect with index
0
0
1E
1F
@PC+disp16
addr16
PC indirect with 16-bit displacement
Direct address
2
2
*1: Each byte count of the extended address part applies to + in the # (byte count) column in "B.8 F2MC-16LX
Instruction List".
569
APPENDIX B Instructions
B.7
How to Read the Instruction List
Table B.7-1 describes the items used in "B.8 F2MC-16LX Instruction List", and Table
B.7-2 describes the symbols used in the same list.
■ Description of Instruction Presentation Items and Symbols
Table B.7-1 Description of Items in the Instruction List (1/2)
Item
Mnemonic
Uppercase, symbol: Represented as is in the assembler.
Lowercase: Rewritten in the assembler.
Number of following lowercase: Indicates bit length in the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
See Table B.2-1 for the alphabetical letters in items.
RG
B
Operation
570
Description
Indicates the number of times a register access is performed during instruction
execution.
The number is used to calculate the correction value for CPU intermittent
operation.
Indicates the correction value used to calculate the actual number of cycles during
instruction execution.
The actual number of cycles during instruction execution can be determined by
adding the value in the ~ column to this value.
Indicates the instruction operation.
LH
Indicates the special operation for bit15 to bit08 of the accumulator.
Z: Transfers 0.
X: Transfers after sign extension.
-: No transfer
AH
Indicates the special operation for the 16 high-order bits of the accumulator.
*: Transfers from AL to AH.
-: No transfer
Z: Transfers 00 to AH.
X: Transfers 00H or FFH to AH after AL sign extension.
APPENDIX B Instructions
Table B.7-1 Description of Items in the Instruction List (1/2)
Item
Description
I
Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N
(negative), Z (zero), V (overflow), C (carry).
*: Changes upon instruction execution.
-: No change
S: Set upon instruction execution.
R: Reset upon instruction execution.
S
T
N
Z
V
C
RMW
Indicates whether the instruction is a Read Modify Write instruction (reading data
from memory by the I instruction and writing the result to memory).
*: Read Modify Write instruction
-: Not Read Modify Write instruction
Note:
Cannot be used for an address that has different meanings between read and
write operations.
Table B.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
A
Explanation
The bit length used varies depending on the 32-bit accumulator instruction.
Byte: Low-order 8 bits of byte AL
Word: 16 bits of word AL
Long word: 32 bits of AL and AH
AH
16 high-order bits of A
AL
16 low-order bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
program counter bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
571
APPENDIX B Instructions
Table B.7-2 Explanation on Symbols in the Instruction List (1/2)
Symbol
Ri
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
Direct addressing
addr24
Physical direct addressing
ad24 0-15
Bit0 to bit15 of addr24
ad24 16-23
Bit16 to bit23 of addr24
io
I/O area (000000H to 0000FFH)
#imm4
4-bit immediate data
#imm8
8-bit immediate data
#imm16
16-bit immediate data
#imm32
32-bit immediate data
ext (imm8)
16-bit data obtained by sign extension of 8-bit immediate data
disp8
8-bit displacement
disp16
16-bit displacement
bp
572
Explanation
Bit offset
vct4
Vector number (0 to 15)
vct8
Vector number (0 to 255)
( )b
Bit address
rel
PC relative branch
ear
Effective addressing (code 00 to 07)
eam
Effective addressing (code 08 to 1F)
rlst
Register list
APPENDIX B Instructions
B.8
F2MC-16LX Instruction List
Table B.8-1 to Table B.8-18 list the instructions used by the F2MC-16LX.
■ F2MC-16LX Instruction List
Table B.8-1 41 Transfer Instructions (Byte)
Mnemonic
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
XCH
XCH
XCH
XCH
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RLi+disp8
A,#imm4
A,dir
A,addr16
A,Ri
A,ear
A,eam
A,io
A,#imm8
A,@A
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
Ri,A
ear,A
eam,A
io,A
@RLi+disp8,A
Ri,ear
Ri,eam
ear,Ri
eam,Ri
Ri,#imm8
io,#imm8
dir,#imm8
ear,#imm8
eam,#imm8
@AL,AH
A,ear
A,eam
Ri,ear
Ri,eam
#
~
RG
B
2
3
1
2
2+
2
2
2
3
1
2
3
2
2
2+
2
2
2
2
3
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
2
2+
2
2+
3
4
2
2
3 + (a)
3
2
3
10
1
3
4
2
2
3 + (a)
3
2
3
5
10
3
4
2
2
3 + (a)
3
10
3
4 + (a)
4
5 + (a)
2
5
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
0
0
1
1
0
0
0
0
2
0
0
0
1
1
0
0
0
0
1
2
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
2
0
4
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
0
2 × (b)
0
2 × (b)
Operation
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi)+disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
Z
Z
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table.
573
APPENDIX B Instructions
Table B.8-2 38 Transfer Instructions (Word, Long Word)
Mnemonic
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW
XCHW
XCHW
MOVL
MOVL
MOVL
MOVL
MOVL
A,dir
A,addr16
A,SP
A,RWi
A,ear
A,eam
A,io
A,@A
A,#imm16
A,@RWi+disp8
A,@RLi+disp8
dir,A
addr16,A
SP,A
RWi,A
ear,A
eam,A
io,A
@RWi+disp8,A
@RLi+disp8,A
RWi,ear
RWi,eam
ear,RWi
eam,RWi
RWi,#imm16
io,#imm16
ear,#imm16
eam,#imm16
@AL,AH
A,ear
A,eam
RWi, ear
RWi, eam
A,ear
A,eam
A,#imm32
ear,A
eam,A
#
~
RG
B
2
3
1
1
2
2+
2
2
3
2
3
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
2
2
2+
2
2+
2
2+
5
2
2+
3
4
1
2
2
3 + (a)
3
3
2
5
10
3
4
1
2
2
3 + (a)
3
5
10
3
4 + (a)
4
5 + (a)
2
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
4
5 + (a)
3
4
5 + (a)
0
0
0
1
1
0
0
0
0
1
2
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
0
2
0
4
2
2
0
0
2
0
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
0
(c)
0
(c)
0
(c)
0
(c)
(c)
0
2 × (c)
0
2 × (c)
0
(d)
0
0
(d)
Operation
word (A) ← (dir)
word (A) ← (addr16)
word (A) ← (SP)
word (A) ← (RWi)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← (io)
word (A) ← ((A))
word (A) ← imm16
word (A) ← ((RWi)+disp8)
word (A) ← ((RLi)+disp8)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
word ((RWi)+disp8) ← (A)
word ((RLi)+disp8) ← (A)
word (RWi) ← (ear)
word (RWi) ← (eam)
word (ear) ← (RWi)
word (eam) ← (RWi)
word (RWi) ← imm16
word (io) ← imm16
word (ear) ← imm16
word (eam) ← imm16
word ((A)) ← (AH)
word (A) ↔ (ear)
word (A) ↔ (eam)
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
long (ear) ← (A)
long(eam) ← (A)
LH
AH
I
S
T
N
Z
V
C
RMW
-
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a), (c), and (d) in the table.
574
APPENDIX B Instructions
Table B.8-3 42 Addition/Subtraction Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
ADDW
ADDW
ADDW
ADDW
ADDW
ADDW
ADDCW
ADDCW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBCW
SUBCW
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A,ear
A,eam
A,#imm32
A,ear
A,eam
A,#imm32
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
2+
5
2
2+
5
2
3
4+(a)
2
3
5+(a)
3
4+(a)
2
3
4+(a)
2
3
5+(a)
3
4+(a)
6
7+(a)
4
6
7+(a)
4
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
2
0
0
2
0
0
0
0
(c)
0
0
2 × (c)
0
(c)
0
0
(c)
0
0
2 × (c)
0
(c)
0
(d)
0
0
(d)
0
Operation
byte (A) ← (A) + imm8
byte (A) ← (A) + (dir)
byte (A) ← (A) + (ear)
byte (A) ← (A) + (eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear)+ (C)
byte (A) ← (A) + (eam)+ (C)
byte (A) ← (AH) + (AL) + (C)
(decimal)
byte (A) ← (A) - imm8
byte (A) ← (A) - (dir)
byte (A) ← (A) - (ear)
byte (A) ← (A) - (eam)
byte (ear) ← (ear) - (A)
byte (eam) ← (eam) - (A)
byte (A) ← (AH) - (AL) - (C)
byte (A) ← (A) - (ear) - (C)
byte (A) ← (A) - (eam) - (C)
byte (A) ← (AH) - (AL) - (C)
(decimal)
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) - (AL)
word (A) ← (A) - (ear)
word (A) ← (A) - (eam)
word (A) ← (A) - imm16
word (ear) ← (ear) - (A)
word (eam) ← (eam) - (A)
word (A) ← (A) - (ear) - (C)
word (A) ← (A) - (eam) - (C)
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
long (A) ← (A) - (ear)
long (A) ← (A) - (eam)
long (A) ← (A) - imm32
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
575
APPENDIX B Instructions
Table B.8-4 12 Increment/decrement Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
INC
ear
2
3
2
0
INC
eam
2+
5+(a)
0
2 × (b)
DEC
ear
2
3
2
0
DEC
eam
2+
5+(a)
0
2 × (b)
INCW
ear
2
3
2
0
INCW
eam
2+
5+(a)
0
2 × (c)
DECW
ear
2
3
2
0
DECW
eam
2+
5+(a)
0
2 × (c)
INCL
ear
2
7
4
0
INCL
eam
2+
9+(a)
0
2 × (d)
DECL
ear
2
7
4
0
DECL
eam
2+
9+(a)
0
2 × (d)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
byte (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
byte (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
byte (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
byte (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
word (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
word (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
word (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
word (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
Table B.8-5 11 Compare Instructions (Byte, Word, Long Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
CMP
Mnemonic
A
1
1
0
0
byte (AH) - (AL)
Operation
-
-
-
-
-
*
*
*
*
-
CMP
A,ear
2
2
1
0
byte (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMP
A,eam
2+
3+(a)
0
(b)
byte (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMP
A,#imm8
2
2
0
0
byte (A) - imm8
-
-
-
-
-
*
*
*
*
-
CMPW
A
1
1
0
0
word (AH) - (AL)
-
-
-
-
-
*
*
*
*
-
CMPW
A,ear
2
2
1
0
word (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPW
A,eam
2+
3+(a)
0
(c)
word (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPW
A,#imm16
3
2
0
0
word (A) - imm16
-
-
-
-
-
*
*
*
*
-
CMPL
A,ear
2
6
2
0
long (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPL
A,eam
2+
7+(a)
0
(d)
long (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPL
A,#imm32
5
3
0
0
long (A) - imm32
-
-
-
-
-
*
*
*
*
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
576
APPENDIX B Instructions
Table B.8-6 11 Unsigned Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIVU
A
1
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
-
-
-
-
-
-
-
*
*
-
DIVU
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
-
-
-
-
-
-
-
*
*
-
DIVU
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MULU
A
1
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A
1
*11
0
0
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,ear
2
*12
1
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,eam
2+
*13
0
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
*1: 3: Division by 0 7: Overflow 15: Normal
*2: 4: Division by 0 8: Overflow 16: Normal
*3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal
*4: 4: Division by 0 7: Overflow 22: Normal
*5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal
*6: (b): Division by 0 or overflow 2 × (b): Normal
*7: (c): Division by 0 or overflow 2 × (c): Normal
*8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0.
*9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0.
*10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0.
*11: 3: Word (AH) is 0. 11: Word (AH) is not 0.
*12: 4: Word (ear) is 0. 12: Word (ear) is not 0.
*13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0.
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
577
APPENDIX B Instructions
Table B.8-7 11 Signed Multiplication/Division Instructions (Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIV
A
2
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL) remainder → byte (AH)
Z
-
-
-
-
-
-
*
*
-
DIV
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A) remainder → byte (ear)
Z
-
-
-
-
-
-
*
*
-
DIV
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A) remainder → byte (eam)
Z
-
-
-
-
-
-
*
*
-
DIVW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A) remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A) remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MUL
A
2
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
MULW
A
2
*11
0
0
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULW
A,ear
2
*12
1
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULW
A,eam
2+
*13
0
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
*1:
*2:
*3:
*4:
3: Division by 0, 8 or 18: Overflow, 18: Normal
4: Division by 0, 11 or 22: Overflow, 23: Normal
5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal
When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal
When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal
*5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal
When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal
*6: (b): Division by 0 or overflow, 2 × (b): Normal
*7: (c): Division by 0 or overflow, 2 × (c): Normal
*8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative
*9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative
*10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative
*11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative
*12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative
*13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative
Notes:
• The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a
pre-operation count or a post-operation count depending on the detection timing.
• When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed.
• See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
578
APPENDIX B Instructions
Table B.8-8 39 Logic 1 Instructions (Byte, Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
AND
A,#imm8
2
2
0
0
AND
A,ear
2
3
1
0
byte (A) ← (A) and imm8
-
-
-
-
-
*
*
R
-
-
byte (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
AND
A,eam
2+
4+(a)
0
-
(b)
byte (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
AND
ear,A
2
3
-
2
0
byte (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
AND
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
OR
A,#imm8
2
2
0
0
byte (A) ← (A) or imm8
-
-
-
-
-
*
*
R
-
-
OR
A,ear
2
3
1
0
byte (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
OR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
OR
ear,A
2
3
2
0
byte (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
OR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XOR
A,#imm8
2
2
0
0
byte (A) ← (A) xor imm8
-
-
-
-
-
*
*
R
-
-
XOR
A,ear
2
3
1
0
byte (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XOR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XOR
ear,A
2
3
2
0
byte (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XOR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOT
A
1
2
0
0
byte (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOT
ear
2
3
2
0
byte (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOT
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
ANDW
A
1
2
0
0
word (A) ← (AH) and (A)
-
-
-
-
-
*
*
R
-
-
ANDW
A,#imm16
3
2
0
0
word (A) ← (A) and imm16
-
-
-
-
-
*
*
R
-
-
ANDW
A,ear
2
3
1
0
word (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
ANDW
ear,A
2
3
2
0
word (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
ANDW
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
ORW
A
1
2
0
0
word (A) ← (AH) or (A)
-
-
-
-
-
*
*
R
-
-
ORW
A,#imm16
3
2
0
0
word (A) ← (A) or imm16
-
-
-
-
-
*
*
R
-
-
ORW
A,ear
2
3
1
0
word (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
ORW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
ORW
ear,A
2
3
2
0
word (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
ORW
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
-
XORW
A
1
2
0
0
word (A) ← (AH) xor (A)
-
-
-
-
-
*
*
R
-
XORW
A,#imm16
3
2
0
0
word (A) ← (A) xor imm16
-
-
-
-
-
*
*
R
-
-
XORW
A,ear
2
3
1
0
word (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XORW
ear,A
2
3
2
0
word (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOTW
A
1
2
0
0
word (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOTW
ear
2
3
2
0
word (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOTW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
579
APPENDIX B Instructions
Table B.8-9 6 Logic 2 Instructions (Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
ANDL
A,ear
2
6
2
0
long (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
ORL
A,ear
2
6
2
0
long (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
ORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
XORL
A,ear
2
6
2
0
long (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (d) in the table.
Table B.8-10 6 Sign Inversion Instructions (Byte, Word)
Mnemonic
NEG
A
#
~
RG
B
1
2
0
0
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
byte (A) ← 0 - (A)
X
-
-
-
-
*
*
*
*
-
byte (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
byte (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
-
NEG
ear
2
3
2
0
NEG
eam
2+
5+(a)
0
2 × (b)
NEGW
A
1
2
0
0
word (A) ← 0 - (A)
-
-
-
-
-
*
*
*
*
word (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
word (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
NEGW
ear
2
3
2
0
NEGW
eam
2+
5+(a)
0
2 × (c)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (c) in the table.
Table B.8-11 1 Normalization Instruction (Long Word)
Mnemonic
NRML
A,R0
#
~
RG
B
2
*1
1
0
Operation
long (A) ← Shift left to the position where '1' is set
for the first time.
byte (R0) ← Shift count at that time
*1: 4 when all accumulators have a value of 0; otherwise, 6+(R0)
580
LH
AH
I
S
T
N
Z
V
C
RMW
-
-
-
-
-
-
*
-
-
-
APPENDIX B Instructions
Table B.8-12 18 Shift Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
RORC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
A
2
2
0
0
byte (A) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
ear
2
3
2
0
byte (ear) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
-
RORC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Right rotation with carry
-
-
-
-
-
*
*
-
*
*
ROLC
ear
2
3
2
0
byte (ear) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
-
ROLC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Left rotation with carry
-
-
-
-
-
*
*
-
*
*
ASR
A,R0
2
*1
1
0
byte (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSR
A,R0
2
*1
1
0
byte (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSL
A,R0
2
*1
1
0
byte (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRW
A
1
2
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSRW
A/SHRW A
1
2
0
0
word (A) ← Logical right shift (A, 1 bit)
-
-
-
-
*
R
*
-
*
-
LSLW
A/SHLW A
1
2
0
0
word (A) ← Logical left shift (A, 1 bit)
-
-
-
-
-
*
*
-
*
-
ASRW
A,R0
2
*1
1
0
word (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRW
A,R0
2
*1
1
0
word (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLW
A,R0
2
*1
1
0
word (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRL
A,R0
2
*2
1
0
long (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRL
A,R0
2
*2
1
0
long (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLL
A,R0
2
*2
1
0
long (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
*1: 6 when R0 is 0; otherwise, 5 + (R0)
*2: 6 when R0 is 0; otherwise, 6 + (R0)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (b) in the table.
581
APPENDIX B Instructions
Table B.8-13 31 Branch 1 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
BZ/BEQ
rel
2
*1
0
0
Branch on (Z) = 1
-
-
-
-
-
-
-
-
-
-
BNZ/
BNE
rel
2
*1
0
0
Branch on (Z) = 0
-
-
-
-
-
-
-
-
-
-
BC/BLO
rel
2
*1
0
0
Branch on (C) = 1
-
-
-
-
-
-
-
-
-
-
BNC/
BHS
rel
2
*1
0
0
Branch on (C) = 0
-
-
-
-
-
-
-
-
-
-
BN
rel
2
*1
0
0
Branch on (N) = 1
-
-
-
-
-
-
-
-
-
-
BP
rel
2
*1
0
0
Branch on (N) = 0
-
-
-
-
-
-
-
-
-
-
BV
rel
2
*1
0
0
Branch on (V) = 1
-
-
-
-
-
-
-
-
-
-
BNV
rel
2
*1
0
0
Branch on (V) = 0
-
-
-
-
-
-
-
-
-
-
BT
rel
2
*1
0
0
Branch on (T) = 1
-
-
-
-
-
-
-
-
-
-
BNT
rel
2
*1
0
0
Branch on (T) = 0
-
-
-
-
-
-
-
-
-
-
BLT
rel
2
*1
0
0
Branch on (V) xor (N) = 1
-
-
-
-
-
-
-
-
-
-
BGE
rel
2
*1
0
0
Branch on (V) xor (N) = 0
-
-
-
-
-
-
-
-
-
-
BLE
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BGT
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BLS
rel
2
*1
0
0
Branch on (C) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BHI
rel
2
*1
0
0
Branch on (C) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BRA
rel
2
*1
0
0
Unconditional branch
-
-
-
-
-
-
-
-
-
-
JMP
@A
1
2
0
0
word (PC) ← (A)
-
-
-
-
-
-
-
-
-
-
JMP
addr16
3
3
0
0
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
JMP
@ear
2
3
1
0
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
JMP
@eam
2+
4+(a)
0
(c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
JMPP
@ear *3
2
5
2
0
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
JMPP
@eam *3
2+
6+(a)
0
(d)
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
JMPP
addr24
4
4
0
0
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
CALL
@ear *4
2
6
1
(c)
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
CALL
@eam *4
2+
7+(a)
0
2 × (c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
CALL
addr16 *5
3
6
0
(c)
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
CALLV
#vct4 *5
1
7
0
2 × (c)
Vector call instruction
-
-
-
-
-
-
-
-
-
-
CALLP
@ear *6
2
10
2
2 × (c)
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
CALLP
@eam *6
2+
11+(a)
0
*2
CALLP
addr24 *7
4
10
0
2 × (c)
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
*1: 4 when a branch is made; otherwise, 3
*2: 3 × (c) + (b)
*3: Read (word) of branch destination address
*4: W: Save to stack (word) R: Read (word) of branch destination address
*5: Save to stack (word)
*6: W: Save to stack (long word), R: Read (long word) of branch destination address
*7: Save to stack (long word)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
582
APPENDIX B Instructions
Table B.8-14 19 Branch 2 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S T N Z V C
RMW
CBNE
A,#imm8,rel
3
*1
0
0
Branch on byte (A) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
A,#imm16,rel
4
*1
0
0
Branch on word (A) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CBNE
ear,#imm8,rel
4
*2
1
0
Branch on byte (ear) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CBNE
eam,#imm8,rel *9
4+
*3
0
(b)
Branch on byte (eam) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
ear,#imm16,rel
5
*4
1
0
Branch on word (ear) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CWBNE
eam,#imm16,rel*9
5+
*3
0
(c)
Branch on word (eam) not equal to imm16
-
-
-
-
-
*
*
*
*
-
DBNZ
ear,rel
3
*5
2
0
byte (ear) ← (ear) - 1, Branch on (ear) not equal to 0
-
-
-
-
-
*
*
*
-
-
DBNZ
eam,rel
3+
*6
2
-
-
-
-
-
*
*
*
-
*
DWBNZ
ear,rel
3
*5
2
-
-
-
-
-
*
*
*
-
-
DWBNZ
eam,rel
3+
*6
2
2 × (c) word (eam) ← (eam) - 1, Branch on (eam) not equal to 0
-
-
-
-
-
*
*
*
-
*
INT
#vct8
2
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT
addr16
3
16
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INTP
addr24
4
17
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
1
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
1
*8
0
*7
Return from interrupt
-
-
*
*
*
*
*
*
*
-
2
6
0
(c)
Saves the old frame pointer in the stack upon entering the
function, then sets the new frame pointer and reserves the
local pointer area.
-
-
-
-
-
-
-
-
-
-
1
5
0
(c)
Recovers the old frame pointer from the stack upon exiting
the function.
-
-
-
-
-
-
-
-
-
-
INT9
RETI
LINK
#imm8
UNLINK
2 × (b) byte (eam) ← (eam) - 1, Branch on (eam) not equal to 0
0
word (ear) ← (ear) - 1, Branch on (ear) not equal to 0
RET
*10
1
4
0
(c)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
RETP
*11
1
6
0
(d)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
*1: 5 when a branch is made; otherwise, 4
*2: 13 when a branch is made; otherwise, 12
*3: 7+(a) when a branch is made; otherwise, 6+(a)
*4: 8 when a branch is made; otherwise, 7
*5: 7 when a branch is made; otherwise, 6
*6: 8+(a) when a branch is made; otherwise, 7+(a)
*7: 3 × (b) + 2 × (c) when jumping to the next interruption request; 6 × (c) when returning from the current interruption
*8: 15 when jumping to the next interruption request; 17 when returning from the current interruption
*9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction.
*10: Return from stack (word)
*11: Return from stack (long word)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table.
583
APPENDIX B Instructions
Table B.8-15 28 Other Control Instructions (Byte, Word, Long Word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
PUSHW
A
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (A)
-
-
-
-
-
-
-
-
-
-
PUSHW
AH
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (AH)
-
-
-
-
-
-
-
-
-
-
PUSHW
PS
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (PS)
-
-
-
-
-
-
-
-
-
-
PUSHW
rlst
2
*3
*5
*4
(SP) ← (SP) - 2n, ((SP)) ← (rlst)
-
-
-
-
-
-
-
-
-
-
POPW
A
1
3
0
(c)
word (A) ← ((SP)), (SP) ← (SP) + 2
-
*
-
-
-
-
-
-
-
-
POPW
AH
1
3
0
(c)
word (AH) ← ((SP)), (SP) ← (SP) + 2
-
-
-
-
-
-
-
-
-
-
POPW
PS
1
4
0
(c)
word (PS) ← ((SP)), (SP) ← (SP) + 2
-
-
*
*
*
*
*
*
*
-
POPW
rlst
2
*2
*5
*4
(rlst) ← ((SP)), (SP) ← (SP) + 2n
-
-
-
-
-
-
-
-
-
-
JCTX
@A
1
14
0
6 × (c)
Context switch instruction
-
-
*
*
*
*
*
*
*
-
AND
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) and imm8
-
-
*
*
*
*
*
*
*
-
OR
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) or imm8
-
-
*
*
*
*
*
*
*
-
MOV
RP,#imm8
2
2
0
0
byte (RP) ← imm8
-
-
-
-
-
-
-
-
-
-
MOV
ILM,#imm8
2
2
0
0
byte (ILM) ← imm8
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,ear
2
3
1
0
word (RWi) ← ear
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,eam
2+
2+(a)
1
0
word (RWi) ← eam
-
-
-
-
-
-
-
-
-
-
MOVEA
A,ear
2
1
0
0
word (A) ← ear
-
*
-
-
-
-
-
-
-
-
MOVEA
A,eam
2+
1+(a)
0
0
word (A) ← eam
-
*
-
-
-
-
-
-
-
-
ADDSP
#imm8
2
3
0
0
word (SP) ← (SP) + ext(imm8)
-
-
-
-
-
-
-
-
-
-
ADDSP
#imm16
3
3
0
0
word (SP) ← (SP) + imm16
-
-
-
-
-
-
-
-
-
-
MOV
A,brg1
2
*1
0
0
byte (A) ← (brg1)
Z
*
-
-
-
*
*
-
-
-
MOV
brg2,A
2
1
0
0
byte (brg2) ← (A)
-
-
-
-
-
*
*
-
-
-
NOP
1
1
0
0
No operation
-
-
-
-
-
-
-
-
-
-
ADB
1
1
0
0
Prefix code for AD space access
-
-
-
-
-
-
-
-
-
-
DTB
1
1
0
0
Prefix code for DT space access
-
-
-
-
-
-
-
-
-
-
PCB
1
1
0
0
Prefix code for PC space access
-
-
-
-
-
-
-
-
-
-
SPB
1
1
0
0
Prefix code for SP space access
-
-
-
-
-
-
-
-
-
-
NCC
1
1
0
0
Prefix code for flag no-change
-
-
-
-
-
-
-
-
-
-
CMR
1
1
0
0
Prefix code for common register bank
-
-
-
-
-
-
-
-
-
-
*1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2
*2: 7 + 3 × (POP count) + 2 × (POP last register number), 7 when RLST = 0 (no transfer register)
*3: 29 + 3 × (PUSH count) - 3 × (PUSH last register number), 8 when RLST = 0 (no transfer register)
*4: (POP count) × (c) or (PUSH count) × (c)
*5: (POP count) or (PUSH count)
Note:
See Table B.5-1 and Table B.5-2 for information on (a) and (c) in the table.
584
APPENDIX B Instructions
Table B.8-16 21 Bit Operand Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
MOVB
A,dir:bp
3
5
0
(b)
byte (A) ← (dir:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,addr16:bp
4
5
0
(b)
byte (A) ← (addr16:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,io:bp
3
4
0
(b)
byte (A) ← (io:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
dir:bp,A
3
7
0
2 × (b)
bit (dir:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
addr16:bp,A
4
7
0
2 × (b)
bit (addr16:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
io:bp,A
3
6
0
2 × (b)
bit (io:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
SETB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
CLRB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
CLRB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
CLRB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
BBC
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
io:bp,rel
4
*2
0
(b)
Branch on (io:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBS
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
io:bp,rel
4
*2
0
(b)
Branch on (io:bp) b = 1
-
-
-
-
-
-
*
-
-
-
SBBS
addr16:bp,rel
5
*3
0
2 × (b)
Branch on (addr16:bp) b = 1,
bit (addr16:bp) b ← 1
-
-
-
-
-
-
*
-
-
*
WBTS
io:bp
3
*4
0
*5
Waits until (io:bp) b = 1
-
-
-
-
-
-
-
-
-
-
WBTC
io:bp
3
*4
0
*5
Waits until (io:bp) b = 0
-
-
-
-
-
-
-
-
-
-
*1: 8 when a branch is made; otherwise, 7
*2: 7 when a branch is made; otherwise, 6
*3: 10 when the condition is met; otherwise, 9
*4: Undefined count
*5: Until the condition is met
Note:
See Table B.5-1 and Table B.5-2 for information on (b) in the table.
Table B.8-17 6 Accumulator Operation Instructions (Byte, Word)
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
SWAP
Mnemonic
1
3
0
0
byte (A)0-7 ↔ (A)8-15
Operation
-
-
-
-
-
-
-
-
-
-
SWAPW
1
2
0
0
word (AH) ↔ (AL)
-
*
-
-
-
-
-
-
-
-
EXT
1
1
0
0
Byte sign extension
X
-
-
-
-
*
*
-
-
-
EXTW
1
2
0
0
Word sign extension
-
X
-
-
-
*
*
-
-
-
ZEXT
1
1
0
0
Byte zero extension
Z
-
-
-
-
R
*
-
-
-
ZEXTW
1
1
0
0
Word zero extension
-
Z
-
-
-
R
*
-
-
-
585
APPENDIX B Instructions
Table B.8-18 10 String Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
MOVS / MOVSI
2
*2
*5
*3
byte transfer @AH+ ← @AL+, counter = RW0
-
-
-
MOVSD
2
*2
*5
*3
byte transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SCEQ / SCEQI
2
*1
*8
*4
byte search @AH+ ← AL, counter = RW0
-
-
-
-
-
-
*
*
*
*
-
SCEQD
2
*1
*8
*4
byte search @AH- ← AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
FILS / FILSI
2
6m+6
*8
*3
byte fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
MOVSW / MOVSWI
2
*2
*5
*6
word transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
-
MOVSWD
2
*2
*5
*6
word transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCWEQ / SCWEQI
2
*1
*8
*7
word search @AH+ - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCWEQD
2
*1
*8
*7
word search @AH- - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
FILSW / FILSWI
2
6m+6
*8
*6
word fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
*1: 5 when RW0 is 0, 4 + 7 × (RW0) when the counter expires, or 7n + 5 when a match occurs
*2: 5 when RW0 is 0; otherwise, 4 + 8 × (RW0)
*3: (b) × (RW0) + (b) × (RW0) When the source and destination access different areas, calculate the (b) item individually.
*4: (b) × n
*5: 2 × (b) × (RW0)
*6: (c) × (RW0) + (c) × (RW0) When the source and destination access different areas, calculate the (c) item individually.
*7: (c) × n
*8: (b) × (RW0)
Note:
m: RW0 value (counter value), n: Loop count
See Table B.5-1 and Table B.5-2 for information on (b) and (c) in the table.
586
APPENDIX B Instructions
B.9
Instruction Map
Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction
map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F2MC-16LX
instruction map.
■ Structure of Instruction Map
Figure B.9-1 Structure of Instruction Map
Basic page map
Bit operation
instructions
Character string
operation
instructions
2-byte
instructions
: Byte 1
ea instructions × 9 : Byte 2
An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An
instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it
references byte 1, and can check the following one byte by referencing the map for byte 2. Figure B.9-2
shows the correspondence between an actual instruction code and instruction map.
587
APPENDIX B Instructions
Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map
Some instructions do
not contain byte 2.
Instruction
code
Length varies
depending on the
instruction.
Byte 1
Byte 2
Operand
Operand
...
[Basic page map]
XY
+Z
[Extended page map]*
UV
+W
*: The extended page map is a generic name of maps for bit operation instructions, character
string operation instructions, 2-byte instructions, and ea instructions. Actually, there are
multiple extended page maps for each type of instructions.
An example of an instruction code is shown in Table B.9-1.
Table B.9-1 Example of an Instruction Code
Byte 1
(from basic page map)
Byte 2
(from extended page map)
NOP
00 +0=00
-
AND A, #8
30 +4=34
-
MOV A, ADB
60 +F=6F
00 +0=00
@RW2+d8, #8, rel
70 +0=70
F0 +2=F2
Instruction
588
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
A
ZEXT
SWAP
ADDSP
DTB
ADB
SPB
#8
A, #8
dir, A
A, dir
io, A
A, io
JMP
BRA
60
MULU
DIVU
ea
@A instruction 2
A
MOVW
MOVX
RET
SP, A A, addr16
A0
B0
C0
ea
instruction 8
D0
E0
rel
rel
LSRW
ASRW
LSLW
SWAPW
ZEXTW
XORW
ORW
ANDW
A
A
MOVW
RWi, ea
PUSHW
POPW
2-byte
XCHW
A
rlst
rlst instruction
RWi, ea
Character
XORW
PUSHW
POPW
XCH
operation
A, #16
PS
PS string
Ri, ea
instruction
MOVW
ea, RWi
Bit operation MOV
A instruction
ea, Ri
ORW
PUSHW
POPW
A, #16
AH
AH
ANDW
PUSHW
POPW
A
A, #16
A
CMPW
MOVL
MOVW
RETI
A, #16
A, #32 addr16, A
ADDSP
MULUW
NOTW
A
#16
A
A
A
EXTW
A
BHI
BLS
BGT
BLE
rel
rel
rel
rel
rel
BGE
CMPL
CMPW
A, #32
NEGW
A
rel
rel
rel
rel
rel
rel
BLT
BT
BNV
BV
BP
BN
BNC/BHS
rel
BC/BLO
BNZ/BNE
rel
BZ/BEQ
MOV
MOV
CBNE A, CWBNE A, MOVW
MOVW
INTP
MOV
RP, #8
ILM, #8
#8, rel
#16, rel
A, #16 A,addr16
addr24
Ri, ea
#4
F0
rel
ADDW
MOVW
MOVW
INT
ea
MOVW
MOVW
MOVW
MOV A,
MOVW
A, #16
A, dir
A, io
#vct8 instruction 9
A, RWi
RWi, A RWi, #16 @RWi+d8 @RWi+d8, A
NOT
ea
instruction 7
MOVX
MOVX
CALLP
ea
A, dir
A, io
addr24 instruction 6
MOVW
MOVW
RETP
A, #8
A, SP
io, #16
A, #8
90
BNT
SUBL
SUBW
A, #32
A
A
A
XOR
OR
OR
CCR, #8
80
ea
MOV
MOV
MOV
MOV
MOVX A, MOV
CALL
rel instruction 1
A, Ri
Ri, A
Ri, #8
A, Ri @RWi+d8
A, #4
70
MOV
JMP
ea
A, addr16
addr16 instruction 3
MOV
MOV
50
MOVX
MOV
JMPP
ea
A, #8
A, #8 addr16, A
addr24 instruction 4
MOV
MOV
MOV
40
SUBW
MOVW
MOVW
INT
MOVEA
A
A, #16
dir, A
io, A
addr16
RWi, ea
UNLINK
A
CMP
A
A, #8
A, #8
SUBC
SUB
ADD
30
AND
AND
MOV
MOV
CALL
ea
CCR, #8
A, #8
dir, #8
io, #8
addr16 instruction 5
CMP
A
A, dir
A, dir
ADDC
SUB
ADD
20
LINK
ADDL
ADDW
#imm8
A, #32
EXT
@A
PCB
A
JCTX
SUBDC
ADDDC
NEG
NCC
INT9
A
CMR
10
NOP
00
APPENDIX B Instructions
Table B.9-2 Basic Page Map
589
590
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
10
MOVB
io:bp, A
20
30
CLRB
io:bp
40
50
SETB
io:bp
60
70
BBC
io;bp, rel
80
90
BBS
io:bp, rel
A0
B0
MOVB
MOVB A, MOVB
MOVB
CLRB
CLRB
SETB
SETB
BBC
BBC
BBS
BBS
A, dir:bp addr16:bp
dir:bp, A addr16:bp,A
dir:bp addr16:bp
dir:bp addr16:bp dir:bp, rel addr16:bp,rel dir:bp, rel addr16:bp,rel
MOVB
A, io:bp
00
WBTS
io:bp
C0
D0
WBTC
io:bp
E0
SBBS
addr16:bp
F0
APPENDIX B Instructions
Table B.9-3 Bit Operation Instruction Map (First Byte = 6CH)
MOVSI
MOVSD
PCB, PCB
PCB, DTB
PCB, ADB
PCB, SPB
DTB, PCB
DTB, DTB
DTB, ADB
DTB, SPB
ADB, PCB
ADB, DTB
ADB, ADB
ADB, SPB
SPB, PCB
SPB, DTB
SPB, ADB
SPB, SPB
+1
+2
+3
+4
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
10
+0
00
MOVSWI
20
MOVSWD
30
40
50
60
70
90
A0
B0
C0
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SCEQI
SCEQD
SCWEQI SCWEQD FILSI
PCB
PCB
PCB
PCB
PCB
80
D0
FILSI
SPB
ADB
DTB
PCB
E0
F0
APPENDIX B Instructions
Table B.9-4 Character String Operation Instruction Map (First Byte = 6EH)
591
592
LSLW
LSLL
LSL
MOVW
MOVW
A, R0
A, R0
A, R0 @RL2+d8, A A, @RL2+d8
MOVW
MOVW
NRML
A, @A @AL, AH
A, R0
ASRW
ASRL
ASR
MOVW
MOVW
A, R0
A, R0
A, R0 @RL3+d8, A A, @RL3+d8
LSRW
LSRL
LSR
A, R0
A, R0
A, R0
+D
+E
+F
MOVW
MOVW
@RL1+d8, A A, @RL1+d8
MOVW
MOVW
@RL0+d8, A A, @RL0+d8
+C
+B
+A
+9
+8
A
MOV
MOV
MOVX
MOV
MOV
A, PCB
A, @A A, @RL3+d8 @RL3+d8, A A, @RL3+d8
+6
ROLC
MOV
MOV
A, @A @AL, AH
+5
A
MOV
MOV
MOVX
MOV
MOV
A, DPR
DPR, A A, @RL2+d8 @RL2+d8, A A, @RL2+d8
+4
ROLC
MOV
MOV
A, USB
USB, A
+3
+7
MOV
MOV
MOVX
MOV
MOV
A, SSB
SSB, A A, @RL1+d8 @RL1+d8, A A, @RL1+d8
+2
40
MOV
MOV
A, ADB
ADB, A
30
+1
20
MOV
MOV
MOVX
MOV
MOV
A, DTB
DTB, A A, @RL0+d8 @RL0+d8, A A, @RL0+d8
10
+0
00
50
DIVU
MULW
MUL
60
A
A
A
70
80
90
A0
B0
C0
D0
E0
F0
APPENDIX B Instructions
Table B.9-5 2-byte Instruction Map (First Byte = 6FH)
50
90
B0
D0
@RW1, @RW1+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
@RW2, @RW2+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
@RW3, @RW3+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
SUBL
SUBL A,
A, RL2 @RW5+d8
SUBL
SUBL A,
A, RL3 @RW6+d8
SUBL
SUBL A,
A, RL3 @RW7+d8
ADDL
ADDL A,
A, RL2 @RW5+d8
ADDL
ADDL A,
A, RL3 @RW6+d8
ADDL
ADDL A,
A, RL3 @RW7+d8
ADDL
ADDL A, SUBL
SUBL A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ADDL
ADDL A, SUBL
SUBL A, Use
@RW0+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW0+RW7
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
#16, rel A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
,#8, rel
ADDL
ADDL A, SUBL
SUBL A, Use
@RW1+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW1+RW7
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
#16, rel A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
,#8, rel
ADDL
ADDL A,
A,@RW2+ @PC+d16
ADDL
ADDL A, SUBL
SUBL A, Use
A,@RW3+
addr16 A,@RW3+
addr16 prohibited
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
SUBL
SUBL A,
A,@RW2+ @PC+d16
@RW0, @RW0+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
SUBL
SUBL A,
A, RL2 @RW4+d8
Use
prohibited
ANDL
ANDL A,
A,@RW2+ @PC+d16
ANDL
ANDL A,
A, RL3 @RW7+d8
ANDL
ANDL A,
A, RL3 @RW6+d8
ANDL
ANDL A,
A, RL2 @RW5+d8
ANDL
ANDL A,
A, RL2 @RW4+d8
ORL
ORL A,
A,@RW2+ @PC+d16
ORL
ORL A,
A, RL3 @RW7+d8
ORL
ORL A,
A, RL3 @RW6+d8
ORL
ORL A,
A, RL2 @RW5+d8
ORL
ORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A,@RW2+ @PC+d16
XORL
XORL A,
A, RL3 @RW7+d8
XORL
XORL A,
A, RL3 @RW6+d8
XORL
XORL A,
A, RL2 @RW5+d8
XORL
XORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A, RL1 @RW3+d8
addr16,
,#8, rel
Use
@PC+d16,
prohibited
,#8, rel
@RW3, @RW3+d16
#8, rel
,#8, rel
@RW2, @RW2+d16
#8, rel
,#8, rel
@RW1, @RW1+d16
#8, rel
,#8, rel
@RW0, @RW0+d16
#8, rel
,#8, rel
R7, @RW7+d8,
#8, rel
#8, rel
R6, @RW6+d8,
#8, rel
#8, rel
R5, @RW5+d8,
#8, rel
#8, rel
R4, @RW4+d8,
#8, rel
#8, rel
R3, @RW3+d8,
#8, rel
#8, rel
addr16, CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
#16, rel A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 prohibited
@PC+d16, CMPL
CMPL A,
#16, rel A,@RW2+ @PC+d16
RW7, @RW7+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW7+d8
RW6, @RW6+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW6+d8
RW5, @RW5+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW5+d8
RW4, @RW4+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW4+d8
ORL
ORL A,
A, RL1 @RW3+d8
R2, @RW2+d8,
#8, rel
#8, rel
R1, @RW1+d8,
#8, rel
#8, rel
ADDL
ADDL A,
A, RL2 @RW4+d8
ANDL
ANDL A,
A, RL1 @RW3+d8
XORL
XORL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW1+d8
+4
RW3, @RW3+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW3+d8
ORL
ORL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW1+d8
SUBL
SUBL A,
A, RL1 @RW3+d8
ANDL
ANDL A,
A, RL1 @RW2+d8
ANDL
ANDL A,
A, RL0 @RW1+d8
ADDL
ADDL A,
A, RL1 @RW3+d8
RW2, @RW2+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW2+d8
RW1, @RW1+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW1+d8
+3
CBNE ↓
F0
R0, @RW0+d8,
#8, rel
#8, rel
CBNE ↓
E0
SUBL
SUBL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW0+d8
C0
ADDL
ADDL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW0+d8
A0
+2
ANDL
ANDL A,
A, RL0 @RW0+d8
80
SUBL
SUBL A,
A, RL0 @RW1+d8
70
ADDL
ADDL A,
A, RL0 @RW1+d8
60
RW0, @RW0+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW0+d8
CWBNE ↓ CWBNE ↓
40
+1
30
+0
20
SUBL
SUBL A,
A, RL0 @RW0+d8
10
ADDL
ADDL A,
A, RL0 @RW0+d8
00
APPENDIX B Instructions
Table B.9-6 ea Instruction 1 (First Byte = 70H)
593
594
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW7+d8
@RL3 @@RW7+d8
RL3 @RW7+d8
RL3 @RW7+d8
A, RL3 @RW7+d8
RL3, A @RW7+d8,A
R7, #8 @RW7+d8,#8
A, RW7 @RW7+d8
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #8 @RW0+d16,#8
A,@RW0 @RW0+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1,A @RW1+d16,A @RW1, #8 @RW1+d16,#8
A,@RW1 @RW1+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2,A @RW2+d16,A @RW2, #8 @RW2+d16,#8
A,@RW2 @RW2+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3,A @RW3+d16,A @RW3, #8 @RW3+d16,#8
A,@RW3 @RW3+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+,A @RW0+RW7,A @RW0+, #8 @RW0+RW7,#8 A,@RW0+ @RW0+RW7
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+,A @RW1+RW7,A @RW1+, #8 @RW1+RW7,#8 A,@RW1+ @RW1+RW7
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+,A @PC+d16, A @RW2+, #8 @PC+d16, #8 A,@RW2+ @PC+d16
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+,A
addr16, A @RW3+, #8
addr16, #8 A,@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW6+d8
@RL3 @@RW6+d8
RL3 @RW6+d8
RL3 @RW6+d8
A, RL3 @RW6+d8
RL3, A @RW6+d8,A
R6, #8 @RW6+d8,#8
A, RW6 @RW6+d8
D0
+6
C0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW5+d8
@RL2 @@RW5+d8
RL2 @RW5+d8
RL2 @RW5+d8
A, RL2 @RW5+d8
RL2, A @RW5+d8,A
R5, #8 @RW5+d8,#8
A, RW5 @RW5+d8
B0
+5
A0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW4+d8
@RL2 @@RW4+d8
RL2 @RW4+d8
RL2 @RW4+d8
A, RL2 @RW4+d8
RL2, A @RW4+d8,A
R4, #8 @RW4+d8,#8
A, RW4 @RW4+d8
90
+4
80
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW3+d8
@RL1 @@RW3+d8
RL1 @RW3+d8
RL1 @RW3+d8
A, RL1 @RW3+d8
RL1, A @RW3+d8,A
R3, #8 @RW3+d8,#8
A, RW3 @RW3+d8
70
+3
60
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW2+d8
@RL1 @@RW2+d8
RL1 @RW2+d8
RL1 @RW2+d8
A, RL1 @RW2+d8
RL1, A @RW2+d8,A
R2, #8 @RW2+d8,#8
A, RW2 @RW2+d8
50
+2
40
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW1+d8
@RL0 @@RW1+d8
RL0 @RW1+d8
RL0 @RW1+d8
A, RL0 @RW1+d8
RL0, A @RW1+d8,A
R1, #8 @RW1+d8,#8
A, RW1 @RW1+d8
30
+1
20
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW0+d8
@RL0 @@RW0+d8
RL0 @RW0+d8
RL0 @RW0+d8
A, RL0 @RW0+d8
RL0, A @RW0+d8,A
R0, #8 @RW0+d8,#8
A, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-7 ea Instruction 2 (First Byte = 71H)
D0
E0
F0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A A,@RW3+
addr16 A,@RW3+
addr16
+D
+E
+F
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R7 @RW7+d8
A, R7 @RW7+d8
R7, A @RW7+d8,A
A, R7 @RW7+d8
A, R7 @RW7+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R6 @RW6+d8
A, R6 @RW6+d8
R6, A @RW6+d8,A
A, R6 @RW6+d8
A, R6 @RW6+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R5 @RW5+d8
A, R5 @RW5+d8
R5, A @RW5+d8,A
A, R5 @RW5+d8
A, R5 @RW5+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R4 @RW4+d8
A, R4 @RW4+d8
R4, A @RW4+d8,A
A, R4 @RW4+d8
A, R4 @RW4+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R3 @RW3+d8
A, R3 @RW3+d8
R3, A @RW3+d8,A
A, R3 @RW3+d8
A, R3 @RW3+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R2 @RW2+d8
A, R2 @RW2+d8
R2, A @RW2+d8,A
A, R2 @RW2+d8
A, R2 @RW2+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R1 @RW1+d8
A, R1 @RW1+d8
R1, A @RW1+d8,A
A, R1 @RW1+d8
A, R1 @RW1+d8
+C
INC
DEC
R7 @RW7+d8
C0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ROLC
RORC
RORC
INC
R7 @RW7+d8
R7 @RW7+d8
ROLC
INC
DEC
R6 @RW6+d8
B0
+B
ROLC
RORC
RORC
INC
R6 @RW6+d8
R6 @RW6+d8
ROLC
INC
DEC
R5 @RW5+d8
A0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ROLC
RORC
RORC
INC
R5 @RW5+d8
R5 @RW5+d8
ROLC
INC
DEC
R4 @RW4+d8
90
+A
ROLC
RORC
RORC
INC
R4 @RW4+d8
R4 @RW4+d8
ROLC
INC
DEC
R3 @RW3+d8
INC
DEC
R2 @RW2+d8
INC
DEC
R1 @RW1+d8
80
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R0 @RW0+d8
A, R0 @RW0+d8
R0, A @RW0+d8,A
A, R0 @RW0+d8
A, R0 @RW0+d8
70
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ROLC
RORC
RORC
INC
R3 @RW3+d8
R3 @RW3+d8
ROLC
60
INC
DEC
R0 @RW0+d8
50
+9
ROLC
RORC
RORC
INC
R2 @RW2+d8
R2 @RW2+d8
ROLC
40
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0, A @RW0+d16,A
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ROLC
RORC
RORC
INC
R1 @RW1+d8
R1 @RW1+d8
ROLC
30
ROLC
RORC
RORC
INC
R0 @RW0+d8
R0 @RW0+d8
20
ROLC
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX B Instructions
Table B.9-8 ea Instruction 3 (First Byte = 72H)
595
596
CALL
CALL
RW5 @@RW5+d8
CALL
CALL
RW6 @@RW6+d8
CALL
CALL
RW7 @@RW7+d8
JMP
JMP
@RW5 @@RW5+d8
JMP
JMP
@RW6 @@RW6+d8
JMP
JMP
@RW7 @@RW7+d8
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16 @RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #16 @RW0+d16,#16 A,@RW0 @RW0+d16
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16 @RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, #16 @RW1+d16,#16 A,@RW1 @RW1+d16
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16 @RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, #16 @RW2+d16,#16 A,@RW2 @RW2+d16
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16 @RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, #16 @RW3+d16,#16 A,@RW3 @RW3+d16
JMP
JMP @
CALL
CALL @
INCW
INCW @
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, #16 @RW0+RW7,#16 A,@RW0+ @RW0+RW7
JMP
JMP @
CALL
CALL @
INCW
INCW @
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, #16 @RW1+RW7,#16 A,@RW1+ @RW1+RW7
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16 @RW2+ @@PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A @RW2+, #16 @PC+d16, #16 A,@RW2+ @PC+d16
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A @RW3+, #16
addr16, #16 A,@RW3+
addr16
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW7 @RW7+d8
RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, A @RW7+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW6 @RW6+d8
RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, A @RW6+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW5 @RW5+d8
RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, A @RW5+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW4 @RW4+d8
RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, A @RW4+d8,A
MOVW
MOVW
RW7, #16 @RW7+d8,#16
MOVW
MOVW
RW6, #16 @RW6+d8,#16
MOVW
MOVW
RW5, #16 @RW5+d8,#16
MOVW
MOVW
RW4, #16 @RW4+d8,#16
XCHW
XCHW A,
A, RW7 @RW7+d8
XCHW
XCHW A,
A, RW6 @RW6+d8
XCHW
XCHW A,
A, RW5 @RW5+d8
XCHW
XCHW A,
A, RW4 @RW4+d8
XCHW
XCHW A,
A, RW3 @RW3+d8
XCHW
XCHW A,
A, RW2 @RW2+d8
XCHW
XCHW A,
A, RW1 @RW1+d8
CALL
CALL
RW4 @@RW4+d8
MOVW
MOVW
RW3, #16 @RW3+d8,#16
MOVW
MOVW
RW2, #16 @RW2+d8,#16
MOVW
MOVW
RW1, #16 @RW1+d8,#16
JMP
JMP
@RW4 @@RW4+d8
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW3 @RW3+d8
RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, A @RW3+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW2 @RW2+d8
RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, A @RW2+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW1 @RW1+d8
RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, A @RW1+d8,A
+4
F0
XCHW
XCHW A,
A, RW0 @RW0+d8
E0
CALL
CALL
RW3 @@RW3+d8
D0
MOVW
MOVW
RW0, #16 @RW0+d8,#16
C0
JMP
JMP
@RW3 @@RW3+d8
B0
+3
A0
CALL
CALL
RW2 @@RW2+d8
90
JMP
JMP
@RW2 @@RW2+d8
80
+2
70
CALL
CALL
RW1 @@RW1+d8
60
JMP
JMP
@RW1 @@RW1+d8
50
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW0 @RW0+d8
RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, A @RW0+d8,A
40
+1
30
CALL
CALL
RW0 @@RW0+d8
20
JMP
JMP
@RW0 @@RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-9 ea Instruction 4 (First Byte = 73H)
ADD
A, SUB
SUB
SUB
ADDC
A, ADDC
A,
ADDC
ADDC A,
A, CMP
CMP
CMP
CMP
A,
A,
A, AND
AND
AND
AND
AND
AND
A,
A,
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r PC+d16, r
+F A,@RW3+
ADD
ADD
SUB
SUB
ADDC
ADDC
CMP
CMP
AND
AND
OR
OR
XOR
XOR
DBNZ
DBNZ
A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+
A, addr16 A,@RW3+ A, addr16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ADD
SUB
CMP
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW1+ @RW1+RW7 @RW1+, r W1+RW7, r
A,
CMP
OR
OR
A,
A,@RW1+ @RW1+RW7
ADD
ADD
ADDC A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ADDC
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW0+ @RW0+RW7 @RW0+, r W0+RW7, r
A,
OR
OR
A,
A,@RW0+ @RW0+RW7
SUB
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
SUB
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW3 @RW3+d16 @RW3, r W3+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
A,
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW2 @RW2+d16 @RW2, r W2+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW1 @RW1+d16 @RW1, r W1+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW0 @RW0+d16 @RW0, r W0+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
R7, r RW7+d8, r
ADD
F0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
R6, r RW6+d8, r
E0
ADD
D0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
R5, r RW5+d8, r
C0
ADD
B0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
R4, r RW4+d8, r
A0
ADD
90
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
R3, r RW3+d8, r
80
ADD
70
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
R2, r RW2+d8, r
60
ADD
50
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
R1, r RW1+d8, r
40
ADD
30
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
R0, r RW0+d8, r
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX B Instructions
Table B.9-10 ea Instruction 5 (First Byte = 74H)
597
598
NOT
NOT
R2 @RW2+d8
SUB
SUB
SUB
SUB
SUB
SUB
@RW2+, A @PC+d16,A
SUB
SUB
@RW3+, A addr16, A
ADD
ADD
@RW2+, A @PC+d16,A
ADD
ADD
@RW3+, A addr16, A
+F
@RW1+RW7,A @RW1+, A @RW1+RW7,A
ADD @R
@RW0+RW7,A @RW0+, A @RW0+RW7,A
ADD @R
+E
+D @RW1+, A
ADD
+C @RW0+, A
ADD
NOT
NOT
@RW1+ @RW1+RW7
NOT
NOT
@RW0+ @RW0+RW7
SUBC
SUBC A, NEG
NEG A,
AND
AND
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
OR
OR
@RW3+, A addr16, A
XOR
XOR
@RW3+, A addr16, A
NOT
NOT
@RW3+
addr16
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
NOT
NOT
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+ @PC+d16
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A
NOT
NOT
@RW3 @RW3+d16
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
+B
XOR
NOT
NOT
R7, A @RW7+d8, A
R7 @RW7+d8
XOR
NOT
NOT
R6, A @RW6+d8, A
R6 @RW6+d8
XOR
NOT
NOT
R5, A @RW5+d8, A
R5 @RW5+d8
XOR
NOT
NOT
R4, A @RW4+d8, A
R4 @RW4+d8
XOR
NOT
NOT
R3, A @RW3+d8, A
R3 @RW3+d8
XOR
R2, A @RW2+d8,A
XOR
NOT
NOT
R1, A @RW1+d8, A
R1 @RW1+d8
NOT
NOT
@RW2 @RW2+d16
XOR
F0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
NEG A,
AND
AND
OR
OR
R7 @RW7+d8
R7, A @RW7+d8, A
R7, A @RW7+d8, A
XOR
XOR
XOR
XOR
XOR
XOR
E0
XOR
NOT
NOT
R0, A @RW0+d8, A
R0 @RW0+d8
D0
+A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R7, A @RW7+d8, A
R7, A @RW7+d8, A
A, R7 @RW7+d8
ADD
NEG A,
AND
AND
OR
OR
R6 @RW6+d8
R6, A @RW6+d8, A
R6, A @RW6+d8, A
NEG A,
AND
AND
OR
OR
R5 @RW5+d8
R5, A @RW5+d8, A
R5, A @RW5+d8, A
NEG A,
AND
AND
OR
OR
R4 @RW4+d8
R4, A @RW4+d8, A
R4, A @RW4+d8, A
NEG A,
AND
AND
OR
OR
R3 @RW3+d8
R3, A @RW3+d8, A
R3, A @RW3+d8, A
NEG A,
AND
AND
OR
OR
R2 @RW2+d8
R2, A @RW2+d8,A
R2, A @RW2+d8,A
NEG A,
AND
AND
OR
OR
R1 @RW1+d8
R1, A @RW1+d8, A
R1, A @RW1+d8, A
XOR
C0
NOT
NOT
@RW1 @RW1+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R6, A @RW6+d8, A
R6, A @RW6+d8, A
A, R6 @RW6+d8
ADD
B0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R5, A @RW5+d8, A
R5, A @RW5+d8, A
A, R5 @RW5+d8
ADD
A0
+9
ADD
SUB
SUB
SUBC
SUBC A, NEG
R4, A @RW4+d8, A
R4, A @RW4+d8, A
A, R4 @RW4+d8
ADD
90
NOT
NOT
@RW0 @RW0+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R3, A @RW3+d8, A
R3, A @RW3+d8, A
A, R3 @RW3+d8
ADD
80
NEG A,
AND
AND
OR
OR
R0 @RW0+d8
R0, A @RW0+d8, A
R0, A @RW0+d8, A
70
ADD
ADD
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R2, A @RW2+d8,A
R2, A @RW2+d8,A
A, R2 @RW2+d8
60
ADD
50
ADD
SUB
SUB
SUBC
SUBC A, NEG
R1, A @RW1+d8, A
R1, A @RW1+d8, A
A, R1 @RW1+d8
40
ADD
30
ADD
SUB
SUB
SUBC
SUBC A, NEG
R0, A @RW0+d8, A
R0, A @RW0+d8, A
A, R0 @RW0+d8
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX B Instructions
Table B.9-11 ea Instruction 6 (First Byte = 75H)
ADDW A, SUBW
ADDW
ADDCW
CMPW
ADDCW A, CMPW
ADDCW A,
ANDW
CMPW A, ANDW
CMPW A,
ORW
ORW
ANDW A, ORW
ANDW A,
ANDW A,
ORW
ORW
ORW
A,
A,
A, XORW
XORW A, DWBNZ
DWBNZ
+F A,@RW3+
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
addr 16 A,@RW3+ addr 16
A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr16 A,@RW3+
addr 16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r @PC+d16,r
SUBW A, ADDCW
SUBW A,
ANDW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW1+ @RW1+RW7 @RW1+, r @RW1+RW7,r
SUBW
ADDW A,
ADDW
CMPW A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
CMPW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW0+ @RW0+RW7 @RW0+, r @RW0+RW7,r
ADDCW A,
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ADDCW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW3 @RW3+d16 @RW3, r @RW3+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
SUBW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW2 @RW2+d16 @RW2, r @RW2+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
SUBW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW1 @RW1+d16 @RW1, r @RW1+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADDW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW0 @RW0+d16 @RW0, r @RW0+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
ADDW
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, r @RW7+d8,r
F0
+7
E0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, r @RW6+d8,r
D0
+6
C0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, r @RW5+d8,r
B0
+5
A0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, r @RW4+d8,r
90
+4
80
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, r @RW3+d8,r
70
+3
60
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, r @RW2+d8,r
50
+2
40
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, r @RW1+d8,r
30
+1
20
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, r @RW0+d8,r
10
+0
00
APPENDIX B Instructions
Table B.9-12 ea Instruction 7 (First Byte = 76H)
599
600
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
@RW3 @RW3+d16
SUBW
SUBW
@RW3+, A addr16, A
ADDW
ADDW
@RW3+, A addr16, A
+F
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
ORW
ORW
@RW3+, A addr16, A
XORW
XORW
@RW3+, A addr16, A
NOTW
NOTW
@RW3+
addr16
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
@RW2+ @PC+d16
SUBW
SUBW
@RW2+, A @PC+d16,A
ADDW
ADDW
@RW2+, A @PC+d16,A
+E
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7
@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+ @RW1+RW7
SUBCW
+D
SUBW
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7
@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+ @RW0+RW7
SUBW
SUBCW
+C
ADDW
ADDW
SUBW
SUBCW A,
+B @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
SUBW
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
@RW2 @RW2+d16
ADDW
ADDW
SUBW
+A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
SUBW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
@RW1 @RW1+d16
ADDW
ADDW
SUBCW A,
+9 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
@RW0 @RW0+d16
SUBW
NOTW
NOTW
RW7 @RW7+d8
NOTW
NOTW
RW6 @RW6+d8
NOTW
NOTW
RW5 @RW5+d8
+8 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
SUBW
XORW
XORW
RW7, A @RW7+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
A, RW7 @RW7+d8
RW7 @RW7+d8
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
+7
ADDW
XORW
XORW
RW6, A @RW6+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
A, RW6 @RW6+d8
RW6 @RW6+d8
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
+6
ADDW
XORW
XORW
RW5, A @RW5+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
A, RW5 @RW5+d8
RW5 @RW5+d8
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
+5
NOTW
NOTW
RW4 @RW4+d8
XORW
XORW
RW4, A @RW4+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
A, RW4 @RW4+d8
RW4 @RW4+d8
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
+4
F0
NOTW
NOTW
RW0 @RW0+d8
E0
NOTW
NOTW
RW3 @RW3+d8
D0
XORW
XORW
RW3, A @RW3+d8, A
C0
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
A, RW3 @RW3+d8
RW3 @RW3+d8
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
B0
+3
A0
NOTW
NOTW
RW2 @RW2+d8
90
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
A, RW2 @RW2+d8
RW2 @RW2+d8
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
80
+2
70
NOTW
NOTW
RW1 @RW1+d8
60
XORW
XORW
RW1, A @RW1+d8, A
50
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
A, RW1 @RW1+d8
RW1 @RW1+d8
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
40
+1
30
XORW
XORW
RW0, A @RW0+d8, A
20
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
A, RW0 @RW0+d8
RW0 @RW0+d8
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
10
+0
00
APPENDIX B Instructions
Table B.9-13 ea Instruction 8 (First Byte = 77H)
DIV
DIV
A, DIVW
DIVW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
DIV
DIV
A, DIVW
DIVW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MUL
MUL A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MUL
MUL A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MUL
MUL A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW MULUW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MULU
MULU A, MULUW MULUW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MULU
MULU A, MULUW MULUW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
+9
+A
+B
+C
+D
+E
+F A, @RW3+
MULU
DIV
DIV
A, DIVW
DIVW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MUL
MUL A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
addr16 A,@RW3+ addr16
A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
A, DIVW
DIVW A,
addr16 A,@RW3+
addr16
DIV
DIV
A, DIVW
DIVW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
F0
+7
E0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
D0
+6
C0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
B0
+5
A0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
90
+4
80
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
70
+3
60
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
50
+2
40
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
30
+1
20
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-14 ea Instruction 9 (First Byte = 78H)
601
602
MOVEA
MOVEA RW1
RW1,RW4 ,@RW4+d8
MOVEA
MOVEA RW1
RW1,RW5 ,@RW5+d8
MOVEA
MOVEA RW1
RW1,RW6 ,@RW6+d8
MOVEA
MOVEA RW1
RW1,RW7 ,@RW7+d8
MOVEA
MOVEA RW1
RW1,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,@RW1 ,@RW1+d16
MOVEA
MOVEA RW1
RW1,@RW2 ,@RW2+d16
MOVEA
MOVEA RW1
RW1,@RW3 ,@RW3+d16
MOVEA
MOVEA RW0
RW0,RW4 ,@RW4+d8
MOVEA
MOVEA RW0
RW0,RW5 ,@RW5+d8
MOVEA
MOVEA RW0
RW0,RW6 ,@RW6+d8
MOVEA
MOVEA RW0
RW0,RW7 ,@RW7+d8
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
+4
+5
+6
+7
50
70
90
B0
C0
D0
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW3 ,@RW3+d16 RW6,@RW3 ,@RW3+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2 ,@RW2+d16 RW6,@RW2 ,@RW2+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW1 ,@RW1+d16 RW6,@RW1 ,@RW1+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW0 ,@RW0+d16 RW6,@RW0 ,@RW0+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW7 ,@RW7+d8
RW6,RW7 ,@RW7+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW6 ,@RW6+d8
RW6,RW6 ,@RW6+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW5 ,@RW5+d8
RW6,RW5 ,@RW5+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW4 ,@RW4+d8
RW6,RW4 ,@RW4+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW3 ,@RW3+d8
RW6,RW3 ,@RW3+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW2 ,@RW2+d8
RW6,RW2 ,@RW2+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW1 ,@RW1+d8
RW6,RW1 ,@RW1+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW0 ,@RW0+d8
RW6,RW0 ,@RW0+d8
A0
F0
MOVEA
MOVEA RW7
RW7,@RW3 ,@RW3+d16
MOVEA
MOVEA RW7
RW7,@RW2 ,@RW2+d16
MOVEA
MOVEA RW7
RW7,@RW1 ,@RW1+d16
MOVEA
MOVEA RW7
RW7,@RW0 ,@RW0+d16
MOVEA
MOVEA RW7
RW7,RW7 ,@RW7+d8
MOVEA
MOVEA RW7
RW7,RW6 ,@RW6+d8
MOVEA
MOVEA RW7
RW7,RW5 ,@RW5+d8
MOVEA
MOVEA RW7
RW7,RW4 ,@RW4+d8
MOVEA
MOVEA RW7
RW7,RW3 ,@RW3+d8
MOVEA
MOVEA RW7
RW7,RW2 ,@RW2+d8
MOVEA
MOVEA RW7
RW7,RW1 ,@RW1+d8
MOVEA
MOVEA RW7
RW7,RW0 ,@RW0+d8
E0
MOVEA
MOVEA RW3
RW3,@RW2+ ,@PC+d16
MOVEA
MOVEA RW4
RW4,@RW2+ ,@PC+d16
MOVEA
MOVEA RW7
RW7,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
RW6,@RW3+ RW6, addr16 [email protected]+ RW7, addr16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2+ ,@PC+d16
RW6,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
RW0,@RW3+ RW0, addr16 RW1,@RW3+ RW1, addr16 RW2,@RW3+ RW2, addr16 RW3,@RW3+ RW3, addr16 RW4,@RW3+ RW4, addr16 RW5,@RW3+ RW5, addr16
MOVEA
MOVEA RW2
RW2,@RW2+ ,@PC+d16
+F
MOVEA
MOVEA RW1
RW1,@RW2+ ,@PC+d16
MOVEA
MOVEA RW0
RW0,@RW2+ ,@PC+d16
MOVEA RW1
+E
MOVEA
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4 MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW2,@RW1+ ,@RW1+RW7 RW3,@RW1+ ,@RW1+RW7 RW4,@RW1+ ,@RW1+RW7 RW5,@RW1+ ,@RW1+RW7 RW6,@RW1+ ,@RW1+RW7 RW7,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW4
RW4,@RW3 ,@RW3+d16
MOVEA
MOVEA RW4
RW4,@RW2 ,@RW2+d16
MOVEA
MOVEA RW4
RW4,@RW1 ,@RW1+d16
MOVEA
MOVEA RW4
RW4,@RW0 ,@RW0+d16
MOVEA
MOVEA RW4
RW4,RW7 ,@RW7+d8
MOVEA
MOVEA RW4
RW4,RW6 ,@RW6+d8
MOVEA
MOVEA RW4
RW4,RW5 ,@RW5+d8
MOVEA
MOVEA RW4
RW4,RW4 ,@RW4+d8
MOVEA
MOVEA RW4
RW4,RW3 ,@RW3+d8
MOVEA
MOVEA RW4
RW4,RW2 ,@RW2+d8
MOVEA
MOVEA RW4
RW4,RW1 ,@RW1+d8
MOVEA
MOVEA RW4
RW4,RW0 ,@RW0+d8
80
+D RW0,@RW1+ ,@RW1+RW7 RW1,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW3
RW3,@RW3 ,@RW3+d16
MOVEA
MOVEA RW3
RW3,@RW2 ,@RW2+d16
MOVEA
MOVEA RW3
RW3,@RW1 ,@RW1+d16
MOVEA
MOVEA RW3
RW3,@RW0 ,@RW0+d16
MOVEA
MOVEA RW3
RW3,RW7 ,@RW7+d8
MOVEA
MOVEA RW3
RW3,RW6 ,@RW6+d8
MOVEA
MOVEA RW3
RW3,RW5 ,@RW5+d8
MOVEA
MOVEA RW3
RW3,RW4 ,@RW4+d8
MOVEA
MOVEA RW3
RW3,RW3 ,@RW3+d8
MOVEA
MOVEA RW3
RW3,RW2 ,@RW2+d8
MOVEA
MOVEA RW3
RW3,RW1 ,@RW1+d8
MOVEA
MOVEA RW3
RW3,RW0 ,@RW0+d8
60
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4 MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW2,@RW0+ ,@RW0+RW7 RW3,@RW0+ ,@RW0+RW7 RW4,@RW0+ ,@RW0+RW7 RW5,@RW0+ ,@RW0+RW7 RW6,@RW0+ ,@RW0+RW7 RW7,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW2
RW2,@RW3 ,@RW3+d16
MOVEA
MOVEA RW2
RW2,@RW2 ,@RW2+d16
MOVEA
MOVEA RW2
RW2,@RW1 ,@RW1+d16
MOVEA
MOVEA RW2
RW2,@RW0 ,@RW0+d16
MOVEA
MOVEA RW2
RW2,RW7 ,@RW7+d8
MOVEA
MOVEA RW2
RW2,RW6 ,@RW6+d8
MOVEA
MOVEA RW2
RW2,RW5 ,@RW5+d8
MOVEA
MOVEA RW2
RW2,RW4 ,@RW4+d8
MOVEA
MOVEA RW2
RW2,RW3 ,@RW3+d8
MOVEA
MOVEA RW2
RW2,RW2 ,@RW2+d8
MOVEA
MOVEA RW2
RW2,RW1 ,@RW1+d8
MOVEA
MOVEA RW2
RW2,RW0 ,@RW0+d8
40
+C RW0,@RW0+ ,@RW0+RW7 RW1,@RW0+ ,@RW0+RW7
+B RW0,@RW3 ,@RW3+d16
+A RW0,@RW2 ,@RW2+d16
+9 RW0,@RW1 ,@RW1+d16
MOVEA RW1
MOVEA
MOVEA RW1
RW1,RW3 ,@RW3+d8
MOVEA
MOVEA RW0
RW0,RW3 ,@RW3+d8
+3
MOVEA
MOVEA
MOVEA RW1
RW1,RW2 ,@RW2+d8
MOVEA
MOVEA RW0
RW0,RW2 ,@RW2+d8
+2
+8 RW0,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,RW1 ,@RW1+d8
MOVEA
MOVEA RW0
RW0,RW1 ,@RW1+d8
+1
30
MOVEA
MOVEA RW1
RW1,RW0 ,@RW0+d8
20
MOVEA
MOVEA RW0
RW0,RW0 ,@RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-15 MOVEA RWi, ea Instruction (First Byte = 79H)
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW2 @RW2+d16 R1,@RW2 @RW2+d16 R2,@RW2 @RW2+d16 R3,@RW2 @RW2+d16 R4,@RW2 @RW2+d16 R5,@RW2 @RW2+d16 R6,@RW2 @RW2+d16 R7,@RW2 @RW2+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW3+
addr16 @RW3+
addr16
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16
@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-16 MOV Ri, ea Instruction (First Byte = 7AH)
603
604
MOVW
MOVW RW5,
RW5,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW1 @RW1+d16 RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16 RW3,@RW1 @RW1+d16 RW4,@RW1 @RW1+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW2 @RW2+d16 RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16 RW3,@RW2 @RW2+d16 RW4,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW3 @RW3+d16 RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16 RW3,@RW3 @RW3+d16 RW4,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4, MOVW
MOVW RW5, MOVW
MOVW RW6, MOVW
MOVW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, @RW2+ @PC+d16
RW2, @RW2+ @PC+d16
RW3, @RW2+ @PC+d16
RW4, @RW2+ @PC+d16
MOVW
MOVW
RW1, @RW3+ RW1, addr16
MOVW
RW0, @RW1+
MOVW
MOVW
RW0, @RW2+ @PC+d16
MOVW
MOVW
RW0, @RW3+ RW0, addr16
+9
+A
+B
+C
+D
+E
+F
MOVW
MOVW
RW2, @RW3+ RW2, addr16
MOVW
MOVW
RW3, @RW3+ RW3, addr16
MOVW
MOVW
RW5, @RW3+ RW5, addr16
MOVW
MOVW
RW5, @RW2+ @PC+d16
MOVW
MOVW
RW6, @RW3+ RW6, addr16
MOVW
MOVW RW6,
RW6, @RW2+ @PC+d16
MOVW
MOVW
RW7, @RW3+ RW7, addr16
MOVW
MOVW RW7,
RW7, @RW2+ @PC+d16
MOVW RW7,
@RW1+RW7
MOVW
MOVW RW7,
RW7,@RW3 @RW3+d16
MOVW
MOVW RW7,
RW7,@RW2 @RW2+d16
MOVW
MOVW RW7,
RW7,@RW1 @RW1+d16
MOVW
MOVW RW7,
RW7,@RW0 @RW0+d16
MOVW
MOVW RW7,
RW7, RW7 @RW7+d8
MOVW
MOVW RW7,
RW7, RW6 @RW6+d8
MOVW
MOVW RW7,
RW7, RW5 @RW5+d8
MOVW
MOVW RW7,
RW7, RW4 @RW4+d8
MOVW RW6, MOVW
@RW1+RW7 RW7, @RW1+
MOVW
MOVW RW6,
RW6,@RW3 @RW3+d16
MOVW
MOVW RW6,
RW6,@RW2 @RW2+d16
MOVW
MOVW RW6,
RW6,@RW1 @RW1+d16
MOVW
MOVW RW6,
RW6,@RW0 @RW0+d16
MOVW
MOVW RW6,
RW6, RW7 @RW7+d8
MOVW
MOVW RW6,
RW6, RW6 @RW6+d8
MOVW
MOVW RW6,
RW6, RW5 @RW5+d8
MOVW
MOVW RW6,
RW6, RW4 @RW4+d8
MOVW
MOVW
@RW1+RW7 RW6, @RW1+
MOVW
MOVW RW5,
RW5, RW6 @RW6+d8
MOVW
MOVW RW5,
RW5, RW5 @RW5+d8
MOVW RW4, MOVW
@RW1+RW7 RW5, @RW1+
MOVW
MOVW
RW4, @RW3+ RW4, addr16
MOVW RW3, MOVW
@RW1+RW7 RW4, @RW1+
MOVW
MOVW RW5,
RW5,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW0 @RW0+d16 RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16 RW3,@RW0 @RW0+d16 RW4,@RW0 @RW0+d16
+8
MOVW RW2, MOVW
@RW1+RW7 RW3, @RW1+
MOVW
MOVW RW5,
RW5,@RW1 @RW1+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
MOVW
MOVW
RW0, RW7 @RW7+d8
+7
MOVW RW1, MOVW
@RW1+RW7 RW2, @RW1+
MOVW
MOVW RW5,
RW5,@RW0 @RW0+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
MOVW
MOVW
RW0, RW6 @RW6+d8
+6
MOVW
MOVW
@RW1+RW7 RW1, @RW1+
MOVW
MOVW RW5,
RW5, RW7 @RW7+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
MOVW
MOVW
RW0, RW5 @RW5+d8
+5
MOVW
MOVW RW5,
RW5, RW4 @RW4+d8
MOVW
MOVW RW7,
RW7, RW3 @RW3+d8
MOVW
MOVW RW7,
RW7, RW2 @RW2+d8
MOVW
MOVW RW7,
RW7, RW1 @RW1+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
MOVW
MOVW RW6,
RW6, RW3 @RW3+d8
MOVW
MOVW RW6,
RW6, RW2 @RW2+d8
MOVW
MOVW RW6,
RW6, RW1 @RW1+d8
MOVW
MOVW
RW0, RW4 @RW4+d8
MOVW
MOVW RW5,
RW5, RW3 @RW3+d8
MOVW
MOVW RW5,
RW5, RW2 @RW2+d8
MOVW
MOVW RW5,
RW5, RW1 @RW1+d8
+4
F0
MOVW
MOVW RW7,
RW7, RW0 @RW0+d8
E0
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
D0
MOVW
MOVW RW6,
RW6, RW0 @RW0+d8
C0
MOVW
MOVW
RW0, RW3 @RW3+d8
B0
MOVW
MOVW RW5,
RW5, RW0 @RW0+d8
A0
+3
90
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
80
MOVW
MOVW
RW0, RW2 @RW2+d8
70
+2
60
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
50
MOVW
MOVW
RW0, RW1 @RW1+d8
40
+1
30
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
20
MOVW
MOVW
RW0, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-17 MOVW RWi, ea Instruction (First Byte = 7BH)
+F
+E
+D
+C
+B
+A
+9
+8
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R1 addr16, R1
MOV
MOV
@RW3+, R0 addr16, R0
MOV
MOV
MOV
@RW2+, R1 @PC+d16, R1
@RW2+, R0 @PC+d16, R0
MOV
MOV
MOV
MOV
MOV
@RW0+, R1 @RW0+RW7, R1
MOV
@RW3, R1 @RW3+d16, R1
MOV
@RW2, R1 @RW2+d16, R1
MOV
@RW1, R1 @RW1+d16, R1
MOV
@RW1+, R1 @RW1+RW7, R1
MOV
MOV
@RW0, R1 @RW0+d16, R1
MOV
@RW1+, R0 @RW1+RW7, R0
MOV
@RW0+, R0 @RW0+RW7, R0
MOV
@RW3, R0 @RW3+d16, R0
MOV
@RW2, R0 @RW2+d16, R0
MOV
@RW1, R0 @RW1+d16, R0
MOV
@RW0, R0 @RW0+d16, R0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R2 addr16, R2
MOV
@RW2+, R2 @PC+d16, R2
MOV
@RW1+, R2 @RW1+RW7, R2
MOV
@RW0+, R2 @RW0+RW7, R2
MOV
@RW3, R2 @RW3+d16, R2
MOV
@RW2, R2 @RW2+d16, R2
MOV
@RW1, R2 @RW1+d16, R2
MOV
@RW0, R2 @RW0+d16, R2
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R3 addr16, R3
MOV
@RW2+, R3 @PC+d16, R3
MOV
@RW1+, R3 @RW1+RW7, R3
MOV
@RW0+, R3 @RW0+RW7, R3
MOV
@RW3, R3 @RW3+d16, R3
MOV
@RW2, R3 @RW2+d16, R3
MOV
@RW1, R3 @RW1+d16, R3
MOV
@RW0, R3 @RW0+d16, R3
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R4 addr16, R4
MOV
@RW2+, R4 @PC+d16, R4
MOV
@RW1+, R4 @RW1+RW7, R4
MOV
@RW0+, R4 @RW0+RW7, R4
MOV
@RW3, R4 @RW3+d16, R4
MOV
@RW2, R4 @RW2+d16, R4
MOV
@RW1, R4 @RW1+d16, R4
MOV
@RW0, R4 @RW0+d16, R4
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R5 addr16, R5
MOV
@RW2+, R5 @PC+d16, R5
MOV
@RW1+, R5 @RW1+RW7, R5
MOV
@RW0+, R5 @RW0+RW7, R5
MOV
@RW3, R5 @RW3+d16, R5
MOV
@RW2, R5 @RW2+d16, R5
MOV
@RW1, R5 @RW1+d16, R5
MOV
@RW0, R5 @RW0+d16, R5
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R6 addr16, R6
MOV
@RW2+, R6 @PC+d16, R6
MOV
@RW1+, R6 @RW1+RW7, R6
MOV
@RW0+, R6 @RW0+RW7, R6
MOV
@RW3, R6 @RW3+d16, R6
MOV
@RW2, R6 @RW2+d16, R6
MOV
@RW1, R6 @RW1+d16, R6
MOV
@RW0, R6 @RW0+d16,
R6
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R7 addr16, R7
MOV
@RW2+, R7 @PC+d16, R7
MOV
@RW1+, R7 @RW1+RW7, R7
MOV
@RW0+, R7 @RW0+RW7, R7
MOV
@RW3, R7 @RW3+d16, R7
MOV
@RW2, R7 @RW2+d16, R7
MOV
@RW1, R7 @RW1+d16, R7
MOV
@RW0, R7 @RW0+d16, R7
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R7, R0 @RW7+d8, R0
R7, R1 @RW7+d8, R1
R7, R2 @RW7+d8, R2
R7, R3 @RW7+d8, R3
R7, R4 @RW7+d8, R4
R7, R5 @RW7+d8, R5
R7, R6 @RW7+d8, R6
R7, R7 @RW7+d8, R7
F0
+7
E0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R6, R0 @RW6+d8, R0
R6, R1 @RW6+d8, R1
R6, R2 @RW6+d8, R2
R6, R3 @RW6+d8, R3
R6, R4 @RW6+d8, R4
R6, R5 @RW6+d8, R5
R6, R6 @RW6+d8, R6
R6, R7 @RW6+d8, R7
D0
+6
C0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R5, R0 @RW5+d8, R0
R5, R1 @RW5+d8, R1
R5, R2 @RW5+d8, R2
R5, R3 @RW5+d8, R3
R5, R4 @RW5+d8, R4
R5, R5 @RW5+d8, R5
R5, R6 @RW5+d8, R6
R5, R7 @RW5+d8, R7
B0
+5
A0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R4, R0 @RW4+d8, R0
R4, R1 @RW4+d8, R1
R4, R2 @RW4+d8, R2
R4, R3 @RW4+d8, R3
R4, R4 @RW4+d8, R4
R4, R5 @RW4+d8, R5
R4, R6 @RW4+d8, R6
R4, R7 @RW4+d8, R7
90
+4
80
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R3, R0 @RW3+d8, R0
R3, R1 @RW3+d8, R1
R3, R2 @RW3+d8, R2
R3, R3 @RW3+d8, R3
R3, R4 @RW3+d8, R4
R3, R5 @RW3+d8, R5
R3, R6 @RW3+d8, R6
R3, R7 @RW3+d8, R7
70
+3
60
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R2, R0 @RW2+d8, R0
R2, R1 @RW2+d8, R1
R2, R2 @RW2+d8, R2
R2, R3 @RW2+d8, R3
R2, R4 @RW2+d8, R4
R2, R5 @RW2+d8, R5
R2, R6 @RW2+d8, R6
R2, R7 @RW2+d8, R7
50
+2
40
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R1, R0 @RW1+d8, R0
R1, R1 @RW1+d8, R1
R1, R2 @RW1+d8, R2
R1, R3 @RW1+d8, R3
R1, R4 @RW1+d8, R4
R1, R5 @RW1+d8, R5
R1, R6 @RW1+d8, R6
R1, R7 @RW1+d8, R7
30
+1
20
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R0, R0 @RW0+d8, R0
R0, R1 @RW0+d8, R1
R0, R2 @RW0+d8, R2
R0, R3 @RW0+d8, R3
R0, R4 @RW0+d8, R4
R0, R5 @RW0+d8, R5
R0, R6 @RW0+d8, R6
R0, R7 @RW0+d8, R7
10
+0
00
APPENDIX B Instructions
Table B.9-18 MOV ea, Ri Instruction (First Byte = 7CH)
605
606
MOVW
[email protected]
@RW2, RW1 +d16, RW1
MOVW
[email protected]
@RW3, RW1 +d16, RW1
MOVW
[email protected]
@RW0+, RW1 +RW7,RW1
MOVW
[email protected]
@RW1+,RW1 +RW7,RW1
MOVW
[email protected]
@RW2+,RW1 +d16, RW1
MOVW
MOVW
@RW3+,RW1 addr16, RW1
MOVW
[email protected]
@RW2, RW0 +d16, RW0
MOVW
[email protected]
@RW3, RW0 +d16, RW0
MOVW
[email protected]
@RW0+,RW0 +RW7,RW0
MOVW
[email protected]
@RW1+,RW0 +RW7,RW0
MOVW
[email protected]
@RW2+,RW0 +d16, RW0
MOVW
MOVW
@RW3+,RW0 addr16, RW0
+B
+C
+D
+E
+F
MOVW
MOVW
@RW3+,RW2 addr16, RW2
MOVW
[email protected]
@RW2+,RW2 +d16, RW2
MOVW
[email protected]
@RW1+,RW2 +RW7,RW2
MOVW
[email protected]
@RW0+,RW2 +RW7,RW2
MOVW
[email protected]
@RW3, RW2 +d16, RW2
MOVW
[email protected]
@RW2, RW2 +d16, RW2
MOVW
MOVW
@RW3+,RW3 addr16, RW3
MOVW
[email protected]
@RW2+,RW3 +d16, RW3
MOVW
[email protected]
@RW1+,RW3 -+RW7,RW3
MOVW
[email protected]
@RW0+,RW3 +RW7,RW3
MOVW
[email protected]
@RW3, RW3 +d16, RW3
MOVW
[email protected]
@RW2, RW3 +d16, RW3
MOVW
[email protected]
@RW1, RW3 +d16, RW3
MOVW
MOVW
@RW3+,RW4 addr16, RW4
MOVW
[email protected]
@RW2+,RW4 +d16, RW4
MOVW
[email protected]
@RW1+,RW4 +RW7,RW4
MOVW
[email protected]
@RW0+,RW4 +RW7,RW4
MOVW
[email protected]
@RW3, RW4 +d16, RW4
MOVW
[email protected]
@RW2, RW4 +d16, RW4
MOVW
[email protected]
@RW1, RW4 +d16, RW4
MOVW
MOVW
@RW3+,RW5 addr16, RW5
MOVW
[email protected]
@RW2+,RW5 +d16, RW5
MOVW
[email protected]
@RW1+,RW5 +RW7,RW5
MOVW
[email protected]
@RW0+,RW5 +RW7,RW5
MOVW
[email protected]
@RW3, RW5 +d16, RW5
MOVW
[email protected]
@RW2, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW5 +d16, RW5
MOVW
MOVW
@RW3+,RW6 addr16, RW6
MOVW
MOVW @PC
@RW2+,RW6 +d16, RW6
MOVW
[email protected]
@RW1+,RW6 +RW7,RW6
MOVW
[email protected]
@RW0+,RW6 +RW7,RW6
MOVW
[email protected]
@RW3, RW6 +d16, RW6
MOVW
[email protected]
@RW2, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW6 +d16, RW6
MOVW
MOVW
@RW3+,RW7 addr16, RW7
MOVW
[email protected]
@RW2+,RW7 +d16, RW7
MOVW
[email protected]
@RW1+,RW7 +RW7,RW7
MOVW
[email protected]
@RW0+,RW7 +RW7,RW7
MOVW
[email protected]
@RW3, RW7 +d16, RW7
MOVW
[email protected]
@RW2, RW7 +d16, RW7
MOVW
[email protected]
@RW1, RW7 +d16, RW7
MOVW
[email protected]
@RW0, RW7 +d16, RW7
+A
MOVW
[email protected]
@RW1, RW2 +d16, RW2
MOVW
[email protected]
@RW0, RW6 +d16, RW6
MOVW
[email protected]
@RW1, RW1 +d16, RW1
MOVW
[email protected]
@RW0, RW5 +d16, RW5
MOVW
[email protected]
@RW1, RW0 +d16, RW0
MOVW
[email protected]
@RW0, RW4 +d16, RW4
+9
MOVW
[email protected]
@RW0, RW3 +d16, RW3
MOVW
[email protected]
@RW0, RW1 +d16, RW1
MOVW
[email protected]
@RW0, RW0 +d16, RW0
+8
MOVW
[email protected]
@RW0, RW2 +d16, RW2
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW7, RW0 @RW7+d8, RW0
RW7, RW1 @RW7+d8, RW1 RW7, RW2 @RW7+d8, RW2 RW7, RW3 @RW7+d8, RW3 RW7, RW4 @RW7+d8, RW4 RW7, RW5 @RW7+d8, RW5 RW7, RW6 @RW7+d8, RW6 RW7, RW7 @RW7+d8, RW7
F0
+7
E0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW6, RW0 @RW6+d8, RW0
RW6, RW1 @RW6+d8, RW1 RW6, RW2 @RW6+d8, RW2 RW6, RW3 @RW6+d8, RW3 RW6, RW4 @RW6+d8, RW4 RW6, RW5 @RW6+d8, RW5 RW6, RW6 @RW6+d8, RW6 RW6, RW7 @RW6+d8, RW7
D0
+6
C0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW5, RW0 @RW5+d8, RW0
RW5, RW1 @RW5+d8, RW1 RW5, RW2 @RW5+d8, RW2 RW5, RW3 @RW5+d8, RW3 RW5, RW4 @RW5+d8, RW4 RW5, RW5 @RW5+d8, RW5 RW5, RW6 @RW5+d8, RW6 RW5, RW7 @RW5+d8, RW7
B0
+5
A0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW4, RW0 @RW4+d8, RW0
RW4, RW1 @RW4+d8, RW1 RW4, RW2 @RW4+d8, RW2 RW4, RW3 @RW4+d8, RW3 RW4, RW4 @RW4+d8, RW4 RW4, RW5 @RW4+d8, RW5 RW4, RW6 @RW4+d8, RW6 RW4, RW7 @RW4+d8, RW7
90
+4
80
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW3, RW0 @RW3+d8, RW0
RW3, RW1 @RW3+d8, RW1 RW3, RW2 @RW3+d8, RW2 RW3, RW3 @RW3+d8, RW3 RW3, RW4 @RW3+d8, RW4 RW3, RW5 @RW3+d8, RW5 RW3, RW6 @RW3+d8, RW6 RW3, RW7 @RW3+d8, RW7
70
+3
60
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW2, RW0 @RW2+d8, RW0
RW2, RW1 @RW2+d8, RW1 RW2, RW2 @RW2+d8, RW2 RW2, RW3 @RW2+d8, RW3 RW2, RW4 @RW2+d8, RW4 RW2, RW5 @RW2+d8, RW5 RW2, RW6 @RW2+d8, RW6 RW2, RW7 @RW2+d8, RW7
50
+2
40
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW1, RW0 @RW1+d8, RW0
RW1, RW1 @RW1+d8, RW1 RW1, RW2 @RW1+d8, RW2 RW1, RW3 @RW1+d8, RW3 RW1, RW4 @RW1+d8, RW4 RW1, RW5 @RW1+d8, RW5 RW1, RW6 @RW1+d8, RW6 RW1, RW7 @RW1+d8, RW7
30
+1
20
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW0, RW0 @RW0+d8, RW0
RW0, RW1 @RW0+d8, RW1 RW0, RW2 @RW0+d8, RW2 RW0, RW3 @RW0+d8, RW3 RW0, RW4 @RW0+d8, RW4 RW0, RW5 @RW0+d8, RW5 RW0, RW6 @RW0+d8, RW6 RW0, RW7 @RW0+d8, RW7
10
+0
00
APPENDIX B Instructions
Table B.9-19 MOVW ea, Rwi Instruction (First Byte = 7DH)
XCH
XCH
XCH
XCH
R1,
XCH
XCH R1,
R1,@RW2 W2+d16, A
XCH
XCH
R2,
XCH
XCH R2,
R2,@RW2 W2+d16, A
XCH
XCH
R3,
XCH
XCH R3,
R3,@RW2 W2+d16, A
XCH
XCH
R4,
XCH
XCH R4,
R4,@RW2 W2+d16, A
XCH
XCH
R5,
XCH
XCH R5,
R5,@RW2 W2+d16, A
XCH
XCH
R6,
XCH
XCH R6,
R6,@RW2 W2+d16, A
XCH
XCH
R7,
XCH
XCH R7,
R7,@RW2 W2+d16, A
XCH
XCH
XCH
XCH
XCH
R1, XCH
XCH
R2, XCH
XCH
R3, XCH
XCH
R4, XCH
XCH
R5, XCH
XCH
R6, XCH
XCH
R7,
+F R0,@RW3+ R0, addr16
XCH
XCH
R1,@RW3+ R1, addr16
XCH
XCH
R2,@RW3+ R2, addr16
XCH
XCH
R3,@RW3+ R3, addr16
XCH
XCH
R4,@RW3+ R4, addr16
XCH
XCH
R5,@RW3+ R5, addr16
XCH
XCH
R6,@RW3+ R6, addr16
XCH
XCH
R7,@RW3+ R7, addr16
+E R0,@RW2+ @PC+d16 R1,@RW2+ @PC+d16 R2,@RW2+ @PC+d16 R3,@RW2+ @PC+d16 R4,@RW2+ @PC+d16 R5,@RW2+ @PC+d16 R6,@RW2+ @PC+d16 R7,@RW2+ @PC+d16
R0, XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW1+RW7 R1,@RW1+ @RW1+RW7 R2,@RW1+ @RW1+RW7 R3,@RW1+ @RW1+RW7 R4,@RW1+ @RW1+RW7 R5,@RW1+ @RW1+RW7 R6,@RW1+ @RW1+RW7 R7,@RW1+ @RW1+RW7
+D R0,@RW1+
XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW0+RW7 R1,@RW0+ @RW0+RW7 R2,@RW0+ @RW0+RW7 R3,@RW0+ @RW0+RW7 R4,@RW0+ @RW0+RW7 R5,@RW0+ @RW0+RW7 R6,@RW0+ @RW0+RW7 R7,@RW0+ @RW0+RW7
XCH
+C R0,@RW0+
+B R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
R0,
+A R0,@RW2 W2+d16, A
R0,
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
+9
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
+8
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
F0
+7
E0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-20 XCH Ri, ea Instruction (First Byte = 7EH)
607
608
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2+ @PC+d16
RW1,@RW2+ @PC+d16
RW2,@RW2+ @PC+d16
RW3,@RW2+ @PC+d16
RW4,@RW2+ @PC+d16
RW5,@RW2+ @PC+d16
RW6,@RW2+ @PC+d16
RW7,@RW2+ @PC+d16
XCHW
XCHW
RW0,@RW3+ RW0, addr16
+E
+F
XCHW
XCHW
RW7,@RW3+ RW7, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW1+ @RW1+RW7 RW1,@RW1+ @RW1+RW7 RW2,@RW1+ @RW1+RW7 RW3,@RW1+ @RW1+RW7 RW4,@RW1+ @RW1+RW7 RW5,@RW1+ @RW1+RW7 RW6,@RW1+ @RW1+RW7 RW7,@RW1+ @RW1+RW7
+D
XCHW
XCHW
RW6,@RW3+ RW6, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
+C
XCHW
XCHW
RW5,@RW3+ RW5, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW3 @RW3+d16
RW1,@RW3 @RW3+d16
RW2,@RW3 @RW3+d16
RW3,@RW3 @RW3+d16
RW4,@RW3 @RW3+d16
RW5,@RW3 @RW3+d16 RW6,@RW3 @RW3+d16
RW7,@RW3 @RW3+d16
+B
XCHW
XCHW
RW4,@RW3+ RW4, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2 @RW2+d16
RW1,@RW2 @RW2+d16
RW2,@RW2 @RW2+d16
RW3,@RW2 @RW2+d16
RW4,@RW2 @RW2+d16
RW5,@RW2 @RW2+d16 RW6,@RW2 @RW2+d16
RW7,@RW2 @RW2+d16
+A
XCHW
XCHW
RW3,@RW3+ RW3, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW1 @RW1+d16
RW1,@RW1 @RW1+d16
RW2,@RW1 @RW1+d16
RW3,@RW1 @RW1+d16
RW4,@RW1 @RW1+d16
RW5,@RW1 @RW1+d16 RW6,@RW1 @RW1+d16
RW7,@RW1 @RW1+d16
+9
XCHW
XCHW
RW2,@RW3+ RW2, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW0 @RW0+d16
RW1,@RW0 @RW0+d16
RW2,@RW0 @RW0+d16
RW3,@RW0 @RW0+d16
RW4,@RW0 @RW0+d16
RW5,@RW0 @RW0+d16 RW6,@RW0 @RW0+d16
RW7,@RW0 @RW0+d16
+8
XCHW
XCHW
RW1,@RW3+ RW1, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW7 @RW7+d8
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
RW5, RW7 @RW7+d8
RW6, RW7 @RW7+d8
RW7, RW7 @RW7+d8
F0
+7
E0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW6 @RW6+d8
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
RW5, RW6 @RW6+d8
RW6, RW6 @RW6+d8
RW7, RW6 @RW6+d8
D0
+6
C0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW5 @RW5+d8
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
RW5, RW5 @RW5+d8
RW6, RW5 @RW5+d8
RW7, RW5 @RW5+d8
B0
+5
A0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW4 @RW4+d8
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
RW5, RW4 @RW4+d8
RW6, RW4 @RW4+d8
RW7, RW4 @RW4+d8
90
+4
80
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW3 @RW3+d8
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
RW5, RW3 @RW3+d8
RW6, RW3 @RW3+d8
RW7, RW3 @RW3+d8
70
+3
60
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW2 @RW2+d8
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
RW5, RW2 @RW2+d8
RW6, RW2 @RW2+d8
RW7, RW2 @RW2+d8
50
+2
40
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW1 @RW1+d8
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
RW5, RW1 @RW1+d8
RW6, RW1 @RW1+d8
RW7, RW1 @RW1+d8
30
+1
20
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW0 @RW0+d8
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
RW5, RW0 @RW0+d8
RW6, RW0 @RW0+d8
RW7, RW0 @RW0+d8
10
+0
00
APPENDIX B Instructions
Table B.9-21 XCHW RWi, ea Instruction (First Byte = 7FH)
APPENDIX C Timing Diagrams in Flash Memory Mode
APPENDIX C Timing Diagrams in Flash Memory Mode
Each timing diagram for the external pins of the Flash devices in MB90945 series during
Flash Memory mode is shown below.
■ Data Read by Read Access
Figure C-1 Timing Diagram for Read Access
tRC
Address stable
AQ16 to AQ0
tACC
CE
tDF
tOE
OE
tOEH
WE
tOH
tCE
High
impedance
DQ7 to DQ0
High impedance
Output defined
609
APPENDIX C Timing Diagrams in Flash Memory Mode
■ Write, Data Polling, Read (WE Control)
Figure C-2 Write, Data Polling, Read (WE Control)
Third bus cycle
AQ18
to
AQ0
Data polling
7AAAAH
PA
tWC
tAS
PA
tRC
tAH
CE
tGHWL
OE
tWP
tWHWH1
WE
tCS
DQ7
to
DQ0
tOE
tWPH
tDF
tDH
A0H
PD
DQ7
DOUT
tDS
tOH
5.0 V
PA: Write address
PD: Write data
DQ7: Reverse output of write data
DOUT: Output of write data
Note:
The last two bus cycle sequences out of the four are described.
610
tCE
APPENDIX C Timing Diagrams in Flash Memory Mode
■ Write, Data Polling, Read (CE Control)
Figure C-3 Timing Diagram for Write Access (CE Control)
Third bus cycle
Data polling
7AAAAH
AQ18 to AQ0
PA
tWC
tAS
PA
tAH
tWH
WE
tGHWL
OE
tCP
tWHWH1
CE
tCPH
tWS
tDH
A0H
PD
DQ7
DOUT
DQ7 to DQ0
tDS
5.0 V
PA: Write address
PD: Write data
DQ7: Reverse output of write data
DOUT: Output of write data
Note:
The last two bus cycle sequences out of the four are described.
611
APPENDIX C Timing Diagrams in Flash Memory Mode
■ Chip Erase/Sector Erase Command Sequence
Figure C-4 Timing Diagram for Write Access (Chip Erasing/Sector Erasing)
tAS
AQ18
to
AQ0
7AAAAH
tAH
75555H
7AAAAH
7AAAAH
75555H
SA*
CE
tGHWL
OE
tWP
WE
tWPH
tCS
DQ7
to
DQ0
tDH
AAH
55H
80H
AAH
55H
10H/30H
tDS
VCC
tVCS
Note:
SA is the sector address at sector erasing. 7AAAAH (or 6AAAAH) is the address at chip erasing.
612
APPENDIX C Timing Diagrams in Flash Memory Mode
■ Data Polling
Figure C-5 Timing Diagram for Data Polling
tCH
CE
tOE
tDF
OE
tOEH
WE
tCE
tOH
*
DQ7
DQ7
High
impedance
DQ7 = Valid data
tWHWH1 or
tWHWH2
DQ6 to DQ0
DQ6 to DQ0
= Valid data
DQ6 to DQ0 = Invalid
* DQ7 is valid data (The device terminates automatic operation).
tOE
■ Toggle Bit
Figure C-6 Timing Diagram for Toggle Bit
CE
tOEH
WE
tOES
OE
*
Data (DQ7 to DQ0)
DQ6 = Toggle
DQ6 = Toggle
* DQ6 stops toggling (The device terminates automatic operation).
DQ6 = Stop toggling
DQ7 to
DQ0 = Valid
tOE
613
APPENDIX C Timing Diagrams in Flash Memory Mode
■ RY/BY Timing during Writing/Erasing
Figure C-7 Timing Diagram for Output of RY/BY Signal during Writing/Erasing
CE
Rising edge of last write pulse
WE
Writing or erasing
RY/BY
tBUSY
■ RST and RY/BY Timing
Figure C-8 Timing Diagram for Output of RY/BY Signal at Hardware Reset
CE
RY/BY
tRP
RST
tReady
614
APPENDIX C Timing Diagrams in Flash Memory Mode
■ Enable Sector Protect/Verify Sector Protect
Figure C-9 Enable Sector Protect/Verify Sector Protect
AQ18 to AQ9
SAx
AQ8, AQ2, and AQ1
SAy
(AQ8, AQ2, AQ1) = (0, 1, 0)
MD0 12 V
5V
MD2 12 V
5V
tVLHT
tVLHT
OE
WE
tWPP
tOESP
CE
tCSP
DQ7 to DQ0
01H
SAx: First sector address
SAy: Next sector address
tOE
615
APPENDIX C Timing Diagrams in Flash Memory Mode
■ Temporary Sector Protect Cancellation
Figure C-10 Temporary Sector Protect Cancellation
MD1
12 V
5V
5V
CE
WE
tVLHT
RY/BY
616
Write/erase command sequence
APPENDIX D List of Interrupt Vectors
APPENDIX D List of Interrupt Vectors
The interrupt vector table to be referenced for interrupt processing is allocated to
FFFC00H to FFFFFFH in the memory area and also used for software interrupts.
■ List of Interrupt Vectors
Table D-1 lists the interrupt vectors for the MB90945 series.
Table D-1 Interrupt Vectors (1 / 2)
Software
interrupt
instruction
Vector
address L
Vector
address M
Vector
address H
Mode
register
Interrupt
no.
INT 0
FFFFECH
FFFFEDH
FFFFEEH
Unused
#0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
INT 7
FFFFE0H
FFFFE1H
FFFFE2H
Unused
#7
None
INT 8
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDFH
#8
(RESET vector)
INT 9
FFFFD8H
FFFFD9H
FFFFDAH
Unused
#9
INT9 instruction
INT 10
FFFFD4H
FFFFD5H
FFFFD6H
Unused
#10
<Exception>
INT 11
FFFFD0H
FFFFD1H
FFFFD2H
Unused
#11
Timebase timer
INT 12
FFFFCCH
FFFFCDH
FFFFCEH
Unused
#12
External interrupt (INT0 to
INT7)
INT 13
FFFFC8H
FFFFC9H
FFFFCAH
Unused
#13
-
INT 14
FFFFC4H
FFFFC5H
FFFFC6H
Unused
#14
-
INT 15
FFFFC0H
FFFFC1H
FFFFC2H
Unused
#15
CAN 1 RX
INT 16
FFFFBCH
FFFFBDH
FFFFBEH
Unused
#16
CAN 1 TX/NS
INT 17
FFFFB8H
FFFFB9H
FFFFBAH
Unused
#17
PPG 0/PPG 1
INT 18
FFFFB4H
FFFFB5H
FFFFB6H
Unused
#18
PPG 2/PPG 3
INT 19
FFFFB0H
FFFFB1H
FFFFB2H
Unused
#19
PPG 4/PPG 5
INT 20
FFFFACH
FFFFADH
FFFFAEH
Unused
#20
PPG 6/PPG 7
INT 21
FFFFA8H
FFFFA9H
FFFFAAH
Unused
#21
PPG 8/PPG 9
INT 22
FFFFA4H
FFFFA5H
FFFFA6H
Unused
#22
PPG A/PPG B
INT 23
FFFFA0H
FFFFA1H
FFFFA2H
Unused
#23
16-bit reload timer 0
Hardware interrupt
None
.
.
.
617
APPENDIX D List of Interrupt Vectors
Table D-1 Interrupt Vectors (2 / 2)
Software
interrupt
instruction
Vector
address L
Vector
address M
Vector
address H
Mode
register
Interrupt
no.
Hardware interrupt
INT 24
FFFF9CH
FFFF9DH
FFFF9EH
Unused
#24
-
INT 25
FFFF98H
FFFF99H
FFFF9AH
Unused
#25
Input capture 0/1
INT 26
FFFF94H
FFFF95H
FFFF96H
Unused
#26
Output compare 0/1
INT 27
FFFF90H
FFFF91H
FFFF92H
Unused
#27
Input capture 2/3
INT 28
FFFF8CH
FFFF8DH
FFFF8EH
Unused
#28
Output compare 2/3
INT 29
FFFF88H
FFFF89H
FFFF8AH
Unused
#29
Input capture 4/5
INT 30
FFFF84H
FFFF85H
FFFF86H
Unused
#30
I 2C
INT 31
FFFF80H
FFFF81H
FFFF82H
Unused
#31
A/D converter
INT 32
FFFF7CH
FFFF7DH
FFFF7EH
Unused
#32
I/O timer 0/1
INT 33
FFFF78H
FFFF79H
FFFF7AH
Unused
#33
Serial I/O
INT 34
FFFF74H
FFFF75H
FFFF76H
Unused
#34
INT 35
FFFF70H
FFFF71H
FFFF72H
Unused
#35
UART 0 RX
INT 36
FFFF6CH
FFFF6DH
FFFF6EH
Unused
#36
UART 0 TX
INT 37
FFFF68H
FFFF69H
FFFF6AH
Unused
#37
-
INT 38
FFFF64H
FFFF65H
FFFF66H
Unused
#38
-
INT 39
FFFF60H
FFFF61H
FFFF62H
Unused
#39
UART 3 RX
INT 40
FFFF5CH
FFFF5DH
FFFF5EH
Unused
#40
UART 3 TX
INT 41
FFFF58H
FFFF59H
FFFF5AH
Unused
#41
Flash Memory
INT 42
FFFF54H
FFFF55H
FFFF56H
Unused
#42
Delayed interrupt
INT 43
FFFF50H
FFFF51H
FFFF52H
Unused
#43
None
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
INT 254
FFFC04H
FFFC05H
FFFC06H
Unused
#254
None
INT 255
FFFC00H
FFFC01H
FFFC02H
Unused
#255
None
618
-
.
.
.
APPENDIX D List of Interrupt Vectors
■ Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers
Table D-2 summarizes the relationships among the interrupt causes, interrupt vectors, and interrupt control
registers of the MB90945 series.
Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (1 / 2)
Interrupt vector
Interrupt control register
EI2OS
clear
Number
Address
Number
Address
Reset
N
#08
FFFFDCH
-
-
INT9 instruction
N
#09
FFFFD8H
-
-
Exception
N
#10
FFFFD4H
-
-
Timebase timer
N
#11
FFFFD0H
ICR00
Y1
#12
FFFFCCH
0000B0H
External interrupt (INT0 to INT7)
-
-
#13
FFFFC8H
ICR01
-
#14
FFFFC4H
0000B1H
CAN 1 RX
N
#15
FFFFC0H
ICR02
N
#16
FFFFBCH
0000B2H
CAN 1 TX/NS
PPG 0/PPG 1
N
#17
FFFFB8H
ICR03
N
#18
FFFFB4H
0000B3H
PPG 2/PPG 3
PPG 4/PPG 5
N
#19
FFFFB0H
ICR04
N
#20
FFFFACH
0000B4H
PPG 6/PPG 7
PPG 8/PPG 9
N
#21
FFFFA8H
ICR05
N
#22
FFFFA4H
0000B5H
PPG A/PPG B
16-bit reload timer 0
Y1
#23
FFFFA0H
ICR06
#24
FFFF9CH
0000B6H
-
Input capture 0/1
Y1
#25
FFFF98H
ICR07
Y1
#26
FFFF94H
0000B7H
Output compare 0/1
Input capture 2/3
Y1
#27
FFFF90H
ICR08
Y1
#28
FFFF8CH
0000B8H
Output compare 2/3
Input capture 4/5
Y1
#29
FFFF88H
ICR09
I 2C
#30
FFFF84H
0000B9H
Y1
A/D converter
Y1
#31
FFFF80H
ICR10
N
#32
FFFF7CH
0000BAH
I/O timer 0/1
Interrupt cause
-
619
APPENDIX D List of Interrupt Vectors
Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (2 / 2)
Interrupt vector
EI2OS
clear
Number
Address
Y1
#33
FFFF78H
-
34
FFFF74H
UART 0 RX
Y2
35
FFFF70H
UART 0 TX
Y1
36
FFFF6CH
-
-
37
FFFF68H
-
-
38
FFFF64H
UART 3 RX
Y2
39
FFFF60H
UART 3 TX
Y1
40
FFFF5CH
Flash memory
N
41
FFFF58H
Delayed interrupt
N
42
FFFF54H
Interrupt cause
Serial I/O
-
Interrupt control register
Number
Address
ICR11
0000BBH
ICR12
0000BCH
ICR13
0000BDH
ICR14
0000BEH
ICR15
0000BFH
Y1: An EI2OS interrupt clear signal or EI2OS register read access clears the interrupt request flag.
Y2: An EI2OS interrupt clear signal or EI2OS register read access clears the interrupt request flag. A stop request is issued.
N: An EI2OS interrupt clear signal does not clear the interrupt request flag.
Note:
For a peripheral module having two interrupt causes for one interrupt number, an EI2OS interrupt clear
signal clears both interrupt request flags.
When EI2OS ends, an EI2OS clear signal is sent to every interrupt flag assigned to each interrupt
number.
EI2OS is activated when one of two interrupts assigned to an interrupt control register (ICR) is caused
while EI2OS is enabled. This means that an EI2OS descriptor that should essentially be specific to each
interrupt cause is shared by two interrupts. Therefore, while one interrupt is enabled, the other interrupt
must be disabled.
620
INDEX
The index follows on the next page.
This is listed in alphabetic order.
621
Index
Numerics
16-bit Free-running Timer
16-bit Free Run Timer Timing........................... 180
16-bit Free Run Timer Operation ....................... 179
16-bit Free-running Timer................................. 170
16-bit Free-running Timer 0 and 1 ..................... 172
16-bit Free-running Timer Block Diagram.......... 174
16-bit I/O Timer
Block Diagram of 16-bit I/O Timer .................... 171
16-bit Input Capture
16-bit Input Capture ......................................... 173
16-bit Output Compare
16-bit Output Compare ..................................... 172
16-bit Reload Register
Register Layout of 16-bit Timer Register (TMR0)/
16-bit Reload Register (TMRLR0)........ 207
16-bit Reload Timer
16-bit Reload Timer Register............................. 203
Block Diagram of 16-bit Reload Timer............... 202
Input Pin Functions of 16-bit Reload Timer
(in Internal Clock Mode)...................... 209
Internal Clock Operation of
16-bit Reload Timer ............................ 208
Outline of 16-bit Reload Timer
(with Event Count Function) ................ 202
Output Pin Functions of 16-bit Reload Timer......211
Underflow Operation of 16-bit Reload Timer......210
16-bit Timer Register
16-bit Timer Register (TMR0)/
16-bit Reload Register (TMRLR0)........ 207
1M/2M/3M-bit Flash Memory
1M/2M/3M-bit Flash Memory Features.............. 486
Programming Example of 1M/2M/3M-bit
Flash Memory..................................... 519
622
1M-bit Flash Memory
Sector Configuration of the 1M-bit
Flash Memory .................................... 488
24-bit Operand
24-bit Operand Specification............................... 30
2M-bit Flash Memory
Sector Configuration of the 2M-bit
Flash Memory ............................ 489, 490
8/10-bit A/D Converter
8/10-bit A/D Converter Interrupts...................... 260
8/10-bit A/D Converter Interrupts and EI2OS ..... 260
8/10-bit A/D Converter Pins.............................. 250
8/10-bit A/D Converter Registers ...................... 252
Block Diagram of the 8/10-bit A/D Converter
......................................................... 248
Block Diagram of the 8/10-bit A/D Converter Pins
......................................................... 251
EI2OS Function of the 8/10-bit A/D Converter
......................................................... 260
Functions of the 8/10-bit A/D Converter ............ 246
Usage Notes on the 8/10-bit A/D Converter........ 266
8/16-bit PPG
8/16-bit PPG Interrupts..................................... 231
8/16-bit PPG Output Operation ......................... 228
8/16-bit PPG Registers ..................................... 219
Block Diagram of 8/16-bit PPG......................... 215
Controlling Pin Output of 8/16-bit PPG Pulses
......................................................... 230
Function of 8/16-bit PPG .................................. 214
Initial Values of 8/16-bit PPG Hardware ............ 232
Operation Modes of 8/16-bit PPG...................... 227
Operations of 8/16-bit PPG ............................... 227
Relationship between 8/16-bit PPG Reload Value
and Pulse Width.................................. 228
Selecting a Count Clock for 8/16-bit PPG .......... 229
A
A
Accumulator (A) ................................................ 36
A/D Control Status Register
A/D Control Status Register 0 (ADCS0) ............ 256
Upper Bits of the A/D Control Status Register
(ADCS1)............................................ 254
A/D Conversion
A/D Conversion Data Protection Function.......... 264
A/D Converter
8/10-bit A/D Converter Pins.............................. 250
Block Diagram of the 8/10-bit
A/D Converter .................................... 248
Block Diagram of the 8/10-bit A/D Converter Pins
.......................................................... 251
EI2OS Function of the 8/10-bit A/D Converter
.......................................................... 260
Functions of the 8/10-bit A/D Converter ............ 246
Usage Notes on the 8/10-bit A/D Converter........ 266
A/D Data Register
A/D Data Register (ADCR0, 1) ......................... 258
Acceptance Filter
Setting Acceptance Filter .................................. 460
Acceptance Filtering
Acceptance Filtering ........................................ 456
Acceptance Mask Registers
Acceptance Mask Registers 0 and 1
(AMR0 and AMR1) ............................ 446
Acceptance Mask Select Register
Acceptance Mask Select Register (AMSR)......... 444
Accumulator
Accumulator (A) ................................................ 36
Acknowledgement
Acknowledgement ........................................... 388
Activation
Activation ....................................................... 166
ADCR
A/D Data Register (ADCR0, 1) ......................... 258
ADCS
A/D Control Status Register 0 (ADCS0) ............ 256
Upper Bits of the A/D Control Status Register
(ADCS1)............................................ 254
Address Generation
Address Generation Types .................................. 27
Address Match Detection
Block Diagram of the Address Match Detection
Function............................................. 472
Operation of the Address Match Detection
Function............................................. 475
System Configuration Example of the Address Match
Detection Function .............................. 476
Addressing
Addressing ...................................................... 550
Addressing Slaves............................................ 387
Bank Addressing Types.......................................31
Direct Addressing .............................................552
Indirect Addressing...........................................558
ADER
Lower Bits of the Analog Input Enable Register
(ADER0) ............................................253
Upper Bits of the Analog Input Enable/
ADC Select Register (ADER1) .............253
Alternative Mode
Alternative Mode..............................................491
AMR
Acceptance Mask Registers 0 and 1
(AMR0 and AMR1).............................446
AMSR
Acceptance Mask Select Register (AMSR) .........444
Analog Input Enable Register
Analog Input Enable Registers...................151, 250
Lower Bits of the Analog Input Enable Register
(ADER0) ............................................253
Analog Input Enable/ADC Select Register
Upper Bits of the Analog Input Enable/
ADC Select Register (ADER1) .............253
Application Example
Application Example ........................................300
Arbitration
Arbitration .......................................................387
Asynchronous
CLK Asynchronous Baud Rate ..........................289
Operation in Asynchronous LIN Mode
(Operation Mode 3) .............................350
Operation in Asynchronous Mode ......................345
Asynchronous LIN Mode
Operation in Asynchronous LIN Mode
(Operation Mode 3) .............................350
Asynchronous Mode
Operation in Asynchronous Mode ......................345
B
Bank Addressing
Bank Addressing Types.......................................31
Bank Select Prefix
Bank Select Prefix ..............................................44
BAP
Buffer Address Pointer (BAP) .............................69
Basic Configuration
Basic Configuration of MB90F947 Serial
Programming Connection .....................524
Baud Rate
Calculating the Baud Rate .................................338
CLK Asynchronous Baud Rate ..........................289
CLK Synchronous Baud Rate ............................289
Suggested Division Ratios for Different Machine
Speeds and Baud Rates.........................339
UART2/3 Baud Rate Selection ..........................336
623
Baud Rate Generator Register
Bit Configuration of Baud Rate Generator Register
(BGR02/03 and BGR12/13) ................. 328
BGR
Bit Configuration of Baud Rate Generator Register
(BGR02/03 and BGR12/13) ................. 328
Bidirectional Communication
Bidirectional Communication Function .............. 354
Bit
SCC, MSS and INT Bit Competition.................. 376
Bit Timing Register
Bit Timing Register (BTR)................................ 430
Bit Timing Register (BTR) Contents .................. 430
Block Diagram
16-bit Free-running Timer Block Diagram.......... 174
Block Diagram of 16-bit I/O Timer .................... 171
Block Diagram of 16-bit Reload Timer............... 202
Block Diagram of 8/16-bit PPG .........................215
Block Diagram of CAN Controller..................... 411
Block Diagram of Delayed Interrupt .................... 76
Block Diagram of DTP/External Interrupts ......... 236
Block Diagram of MB90F946A.............................6
Block Diagram of MB90F947(A)/
MB90947A............................................. 7
Block Diagram of MB90F949(A) .......................... 8
Block Diagram of MB90V390HA/HB.................... 5
Block Diagram of ROM Mirroring Module......... 482
Block Diagram of the 8/10-bit
A/D Converter .................................... 248
Block Diagram of the 8/10-bit A/D Converter Pins
.......................................................... 251
Block Diagram of the Address Match Detection
Function ............................................. 472
Block Diagram of the Clock Generation Block...... 82
Block Diagram of the Entire Flash Memory........ 487
Block Diagram of the Low-power Consumption
Control Circuit .................................... 119
Block Diagram of Timebase Timer .................... 156
Block Diagram of UART2/3.............................. 308
Block Diagrams of the External Reset Pin .......... 108
Input Capture Block Diagram ............................ 193
Output Compare Block Diagram........................ 181
Serial I/O Block Diagram.................................. 392
UART0 Block Diagram .................................... 279
Watch-dog Timer Block Diagram ...................... 162
BTR
Bit Timing Register (BTR)................................ 430
Bit Timing Register (BTR) Contents .................. 430
Buffer Address Pointer
Buffer Address Pointer (BAP) ............................. 69
Bus Control Register
Bus Control Register (IBCR)............................. 373
Bus Control Register (IBCR) Contents ............... 374
Bus Mode
Bus Mode Setting Bits ......................................142
624
Bus Operation Stop
Conditions for Canceling Bus Operation Stop
(HALT=0).......................................... 426
Conditions for Setting Bus Operation Stop
(HALT=1).......................................... 426
State During Bus Operation Stop (HALT=1) ...... 426
Bus Status Register
Bus Status Register (IBSR) ............................... 370
Bus Status Register (IBSR) Contents ................. 371
BVAL Bits
Caution for Disabling Message Buffers by BVAL Bits
......................................................... 469
BVALR
Message Buffer Valid Register (BVALR) .......... 432
C
Calculating
Calculating the Execution Cycle Count ............. 567
CAN Controller
Block Diagram of CAN Controller .................... 411
Canceling a Transmission Request from the CAN
Controller........................................... 454
Completing Transmission of the
CAN Controller .................................. 455
Features of CAN Controller .............................. 410
Reception Flowchart of the CAN Controller ....... 459
Starting Transmission of the CAN Controller ..... 454
Transmission Flowchart of the
CAN Controller .................................. 455
CAN Direct Mode Register
CAN Direct Mode Register (CDMR)................. 468
CAN Direct Mode Register Contents ................. 468
Cancellation
Temporary Sector Protect Cancellation ............. 616
CCR
Condition Code Register (CCR) .......................... 38
CDCR
Serial I/O Prescaler (CDCR) ............................. 399
CDMR
CAN Direct Mode Register (CDMR)................. 468
CE Control
Write, Data Polling, Read (CE Control) ............ 611
Chip Erase
Chip Erase/Sector Erase Command Sequence
......................................................... 612
Circuit
Block Diagram of the Low-power Consumption
Control Circuit.................................... 119
Input-output Circuits .......................................... 17
CKSCR
Configuration of the Clock Selection Register
(CKSCR) ............................................. 85
CLK
CLK Asynchronous Baud Rate.......................... 289
CLK Synchronous Baud Rate............................ 289
Clock
Block Diagram of the Clock Generation Block
............................................................ 82
Clock Mode Transition ....................................... 90
Clock Modulator................................................ 91
Clock Prescaler Settings ................................... 385
Clock Selection Registers ................................... 84
Clock Supply Map ............................................. 81
Clocks............................................................... 80
Common Machine Clock Frequencies ................ 385
Configuration of the Clock Selection Register
(CKSCR) ............................................. 85
Connection of an Oscillator or an External Clock to the
Microcontroller..................................... 94
External Shift Clock Mode................................ 401
Input Pin Functions of 16-bit Reload Timer
(in Internal Clock Mode) ..................... 209
Internal and External Clock............................... 292
Internal Clock Operation of
16-bit Reload Timer ............................ 208
Internal Shift Clock Mode................................. 401
Machine Clock .................................................. 91
Oscillating Clock Frequency and Serial Clock Input
Frequency .......................................... 527
Selection of a PLL Clock Multiplier .................... 90
Shift Clock Selection........................................ 397
Using External Clock ....................................... 340
Selecting a Count Clock for 8/16-bit PPG........... 229
Clock Control Register
Clock Control Register (ICCR) ......................... 383
Clock Control Register (ICCR) Contents............ 384
Clock Generation
Block Diagram of the Clock Generation Block
............................................................ 82
Clock Mode
Clock Mode..................................................... 117
Clock Mode Transition ....................................... 90
Switching to the Clock Mode ............................ 137
Clock Modulator
Clock Modulator................................................ 91
Clock Modulator Control Register
Clock Modulator Control Register (CMCR) ......... 99
Clock Modulator Control Register Contents ....... 100
Clock Prescaler
Clock Prescaler Settings ................................... 385
Clock Selection Register
Clock Selection Registers ................................... 84
Configuration of the Clock Selection Register
(CKSCR) ............................................. 85
Clock Supply
Clock Supply Map ............................................. 81
CMCR
Clock Modulator Control Register (CMCR) ......... 99
CMOD
Sample Output Waveform when CMOD0 and
CMOD1= "00B" ..................................187
Sample Output Waveform when CMOD0 and
CMOD1= "10B" ..................................190
Sample Output Waveform when CMOD0 and
CMOD1= "11B" ..................................191
Sample Output Waveform with Two Compare
Registers when CMOD0 and
CMOD1= "01B" ..................................188
CMR
Common Register Bank Prefix (CMR) .................45
Command Sequence Table
Command Sequence Table ................................495
Common Machine Clock Frequencies
Common Machine Clock Frequencies ................385
Common Register Bank
Common Register Bank Prefix (CMR) .................45
Communication
Bidirectional Communication Function...............354
LIN-master-slave Communication Function ........359
Master-slave Communication Function...............356
Condition Code Register
Condition Code Register (CCR) ...........................38
Conditions
Start Conditions................................................386
Stop Conditions................................................386
Configuration of the PLL and Special Configuration
Control Register
Configuration of the PLL and Special Configuration
Control Register (PSCCR)......................88
Connection
Basic Configuration of MB90F947 Serial
Programming Connection .....................524
Example of Minimum Connection to the Flash
Microcomputer Programmer (Power
Supplied from the Programmer) ............534
Example of Minimum Connection to the Flash
Microcomputer Programmer (User Power
Supply Used).......................................532
Example of Serial Programming Connection (Power
Supplied from the Programmer) ............530
Example of Serial Programming Connection
(User Power Supply Used)....................528
Inter-CPU Connection Method...........................344
Consecutive Prefix Codes
Consecutive Prefix Codes....................................46
Continuous Conversion Mode
Sample Program for Continuous Conversion Mode
Using EI2OS .......................................270
Control Signals
Flash Memory Control Signals...........................491
Control Status Register
Control Status Register......................................195
Control Status Register (CSR) (Lower)...............421
625
Control Status Register (CSR) (Upper)............... 423
Control Status Register (CSR-lower)
Contents ............................................. 422
Control Status Register (CSR-upper)
Contents ............................................. 424
Control Status Register of Free-running Timer
(Lower) .............................................. 176
Control Status Register of Free-running Timer
(Upper) .............................................. 178
Control Status Register of Output Compare
(Lower) .............................................. 183
Control Status Register of Output Compare
(Upper) .............................................. 185
Conversion
Conversion Using EI2OS .................................. 263
Conversion Mode
Operation in Single Conversion Mode................ 261
Operation in Stop Conversion Mode .................. 262
Sample Program for Stop Conversion Mode Using
EI2OS ................................................ 273
Sample Program for Continuous Conversion Mode
Using EI2OS ....................................... 270
Program Counter
Program Counter (PC) ........................................ 41
Counter
Clearing the Counter by an Overflow ................. 179
Clearing the Counter upon a Match with Output
Compare Register 0 (4) ........................ 180
Counter Operation State.................................... 212
Counting Example
Counting Example............................................340
CPU
CPU Operating Modes and Current
Consumption ......................................116
Inter-CPU Connection Method .......................... 344
Outline of CPU Memory Space ........................... 25
Outline of the CPU ............................................. 24
CPU Intermittent Operating Mode
CPU Intermittent Operating Mode ..................... 117
CPU Intermittent Operation Mode
CPU Intermittent Operation Mode ..................... 125
CSR
Control Status Register (CSR) (Lower) .............. 421
Control Status Register (CSR) (Upper)............... 423
Control Status Register (CSR-lower) Contents
.......................................................... 422
Control Status Register (CSR-upper) Contents
.......................................................... 424
D
Data Counter
Data Counter (DCT) ........................................... 68
Data Direction Register
Reading the Data Direction Register .................. 150
626
Data Format
Transfer Data Format ....................................... 293
Data Frame
Processing for Reception of Data Frame and Remote
Frame ................................................ 457
Data Polling
Data Polling ................................................... 613
Write, Data Polling, Read (CE Control) ............ 611
Write, Data Polling, Read (WE Control) ........... 610
Data Polling Flag
Data Polling Flag (DQ7)................................... 499
Data Register
Data Register (IDAR)....................................... 382
Data Register Contents ..................................... 382
Data Register x (x=0 to 15) (DTRx)................... 452
DCT
Data Counter (DCT)........................................... 68
Delayed Interrupt
Block Diagram of Delayed Interrupt .................... 76
Delayed Interrupt Cause Issuance/
Cancellation Register (DIRR: Delayed
Interrupt Request Register) .................... 77
Delayed Interrupt Issuance.................................. 78
Delayed Interrupt Cause Issuance/Cancellation
Register
Delayed Interrupt Cause Issuance/
Cancellation Register (DIRR: Delayed
Interrupt Request Register) .................... 77
Description
Description of Instruction Presentation Items and
Symbols ............................................ 570
Detection
Slave Address Detection ................................... 386
Device
Handling the Device........................................... 20
Different Blocks
Explanation of the Different Blocks................... 310
Different Machine Speeds
Suggested Division Ratios for Different Machine
Speeds and Baud Rates........................ 339
Direct Addressing
Direct Addressing ............................................ 552
DIRR
Delayed Interrupt Cause Issuance/
Cancellation Register (DIRR: Delayed
Interrupt Request Register) .................... 77
Disabling Message Buffers
Caution for Disabling Message Buffers
by BVAL Bits .................................... 469
Division Ratios
Suggested Division Ratios for Different Machine
Speeds and Baud Rates........................ 339
DLC
List of Message Buffers (DLC Registers and Data
Registers) ........................................... 417
DLC Register
DLC Register x (x=0 to 15) (DLCRx) ................ 451
DLCRx
DLC Register x (x=0 to 15) (DLCRx) ................ 451
DQ
Data Polling Flag (DQ7)................................... 499
Sector Erase Timer Flag (DQ3) ......................... 503
Timing Limit Exceeded Flag (DQ5)................... 502
Toggle Bit Flag (DQ6) ..................................... 501
Toggle Bit-2 Flag (DQ2) .................................. 505
DTP
DTP Operation ................................................ 240
Switching between DTP and External Interrupt
Requests............................................. 241
DTP/External Interrupt
Block Diagram of DTP/External Interrupts......... 236
DTP/External Interrupts Registers ..................... 236
Notes on Using DTP/External Interrupts ............ 242
Outline of DTP/External Interrupts .................... 236
DTRx
Data Register x (x=0 to 15) (DTRx)................... 452
E
ECCR
Extended Communication Control Register
(ECCR2/3) ......................................... 326
Effective Address Field
Effective Address Field ........................... 551, 569
EI2OS
UART2/3 Interrupt and EI2OS .......................... 307
EI2OS
8/10-bit A/D Converter Interrupts and EI2OS
.......................................................... 260
Conversion Using EI2OS .................................. 263
EI2OS (Extended Intelligent I/O Service) ........... 299
EI2OS Function of the 8/10-bit A/D
Converter ........................................... 260
EI2OS Operation Flow........................................ 71
Extended Intelligent I/O Service (EI2OS) ....... 51, 66
Intelligent I/O Service (EI2OS) Function and
Interrupts............................................ 202
LIN-UART2/3 Interrupts and EI2OS.................. 331
Sample Program for Continuous Conversion Mode
Using EI2OS....................................... 270
Sample Program for Single Conversion Mode Using
EI2OS ................................................ 267
Sample Program for Stop Conversion Mode Using
EI2OS ................................................ 273
UART2/3 EI2OS Functions............................... 332
2OS Status Register
EI
EI2OS Status Register (ISCS).............................. 70
EIRR
Interrupt/DTP Flags (EIRR: External Interrupt
Request Register).................................237
ELVR
Request Level Setting Register (ELVR: External
Level Register)....................................238
ENIR
Interrupt/DTP Enable Register (ENIR: Interrupt
Request Enable Register)......................237
Entire Flash Memory
Block Diagram of the Entire Flash Memory ........487
Erase
Detailed Explanation of Flash Memory Write/Erase
..........................................................507
Erasing
Erasing All Data in the Flash Memory (Erasing Chips)
..........................................................511
Erasing Optional Data (Erasing Sectors) in the Flash
Memory..............................................512
Erasing Sectors in the Flash Memory..................512
Restarting Erasing of Flash Memory Sectors .......515
Suspending Erasing of Flash Memory Sectors
..........................................................514
Writing to/Erasing Flash Memory ......................486
ESCR
Extended Status/Control Register (ESCR2/3)
..........................................................324
Event Counter
External Event Counter .....................................209
Exceptions
Exceptions .........................................................51
Execution Cycle Count
Calculating the Execution Cycle Count.............. 567
Execution Cycle Count..................................... 566
Extended Communication Control Register
Extended Communication Control Register
(ECCR2/3)..........................................326
Extended Intelligent I/O Service
EI2OS (Extended Intelligent I/O Service)............299
Extended Intelligent I/O Service (EI2OS)........51, 66
Extended Intelligent I/O Service Descriptor
Extended Intelligent I/O Service Descriptor (ISD)
............................................................68
Extended Serial I/O Interface
Interrupt Function of the Extended Serial I/O
Interface .............................................407
Extended Status/Control Register
Extended Status/Control Register (ESCR2/3)
..........................................................324
External Clock
Connection of an Oscillator or an External Clock
to the Microcontroller ............................94
Internal and External Clock ...............................292
Using External Clock ........................................340
627
External Event Counter
External Event Counter..................................... 209
External Interrupt
External Interrupt Operation.............................. 239
Switching between DTP and External Interrupt
Requests............................................. 241
External Interrupt Request Register
Interrupt/DTP Flags (EIRR: External Interrupt
Request Register) ................................ 237
External Level Register
Request Level Setting Register (ELVR: External
Level Register).................................... 238
External Reset
Block Diagrams of the External Reset Pin .......... 108
External Shift Clock Mode
External Shift Clock Mode ................................ 401
F
F2MC-16LX Instruction List
F2MC-16LX Instruction List ............................. 573
Features
Features........................................................... 366
Fetch
Mode Fetch...................................................... 110
Sample of Input Capture Fetch Timing ............... 199
Filter
Setting Acceptance Filter .................................. 460
Filtering
Acceptance Filtering......................................... 456
Flag
Data Polling Flag (DQ7) ................................... 499
Flag Set Timings for a Receive Operation
(in Mode 0, Mode1, or Mode3)............. 296
Flag Set Timings for a Receive Operation (in Mode 2)
.......................................................... 297
Flag Set Timings for a Transmit Operation ......... 298
Reception Interrupt Generation and Flag Set Timing
.......................................................... 333
Sector Erase Timer Flag (DQ3) .........................503
Status Flag During Transmit and Receive Operation
.......................................................... 299
Timing Limit Exceeded Flag (DQ5)...................502
Toggle Bit Flag (DQ6)......................................501
Toggle Bit-2 Flag (DQ2)................................... 505
Transmission Interrupt Generation and
Flag Set Timing .................................. 334
Flag Change Disable Prefix
Flag Change Disable Prefix (NCC) ...................... 45
Flags
Hardware Sequence Flags ................................. 497
Interrupt/DTP Flags (EIRR: External Interrupt
Request Register) ................................ 237
Set Timings of the Six Flags.............................. 295
628
Flash Memory
1M/2M/3M-bit Flash Memory Features ............. 486
Block Diagram of the Entire Flash Memory ....... 487
Detailed Explanation of Flash Memory Write/Erase
......................................................... 507
Erasing All Data in the Flash Memory (Erasing Chips)
......................................................... 511
Erasing Optional Data (Erasing Sectors) in the Flash
Memory ............................................ 512
Erasing Sectors in the Flash Memory ................. 512
Flash Memory Control Signals .......................... 491
Flash Memory Mode ........................................ 491
Notes on Using Flash Memory .......................... 516
Programming Example of 1M/2M/3M-bit
Flash Memory .................................... 519
Reset Vector Address in Flash Memory ............. 518
Restarting Erasing of Flash Memory Sectors ...... 515
Sector Configuration of the 1M-bit
Flash Memory .................................... 488
Sector Configuration of the 2M-bit Flash Memory
................................................. 489, 490
Setting the Flash Memory to the Read/Reset State
......................................................... 508
Suspending Erasing of Flash Memory Sectors
......................................................... 514
Writing Data to the Flash Memory..................... 509
Writing to the Flash Memory ............................ 509
Writing to/Erasing Flash Memory...................... 486
Flash Memory Control Status Register
Flash Memory Control Status Register (FMCS)
................................................. 486, 493
Flash Memory Mode
Flash Memory Mode ........................................ 491
Flash Microcomputer Programmer
Example of Minimum Connection to the Flash
Microcomputer Programmer (Power
Supplied from the Programmer) ........... 534
Example of Minimum Connection to the Flash
Microcomputer Programmer
(User Power Supply Used)................... 532
Flow Charts
Programming Flow Charts ................................ 389
FMCS
Flash Memory Control Status Register (FMCS)
................................................. 486, 493
Frame
Processing for Reception of Data Frame and Remote
Frame ................................................ 457
Frame Format
Setting Frame Format....................................... 460
Free-running Timer
16-bit Free Run Timer Timing .......................... 180
16-bit Free Run Timer Operation....................... 179
16-bit Free-running Timer ................................ 170
16-bit Free-running Timer 0 and 1 ..................... 172
16-bit Free-running Timer Block Diagram.......... 174
Control Status Register of Free-running Timer
(Lower) ............................................. 176
Control Status Register of Free-running Timer
(Upper) ............................................. 178
Data Register of Free-running Timer.................. 175
G
General-purpose Registers
General-purpose Registers .................................. 35
H
HALT
Conditions for Canceling Bus Operation Stop
(HALT=0).......................................... 426
Conditions for Setting Bus Operation Stop
(HALT=1).......................................... 426
State During Bus Operation Stop (HALT=1)
.......................................................... 426
Handling
Handling the Device........................................... 20
Hardware
Initial Values of 8/16-bit PPG Hardware ............ 232
Hardware Interrupt
Hardware Interrupt Operation.............................. 61
Hardware Interrupts ..................................... 50, 60
Occurrence and Release of Hardware Interrupt
............................................................ 62
Structure of Hardware Interrupt ........................... 60
Hardware Sequence Flags
Hardware Sequence Flags ................................. 497
HB
Block Diagram of MB90V390HA/HB ................... 5
Input Level Select Register
(MB90V390HA/HB Only)................... 152
Pin Assignment of MB90V390HA/HB .................. 9
I
I/O
I/O Area............................................................ 26
I/O Map
I/O Map (3XXX Addresses).............................. 543
I/O Maps
I/O Maps......................................................... 538
I/O Port
I/O Port Registers............................................. 147
I/O Ports ......................................................... 146
I/O Register Address Pointer
I/O Register Address Pointer (IOA) ..................... 69
I/O Timer
Block Diagram of 16-bit I/O Timer.................... 171
2C Interface Registers
I
I2C Interface Registers...................................... 368
IBCR
Bus Control Register (IBCR) .............................373
Bus Control Register (IBCR) Contents ...............374
IBSR
Bus Status Register (IBSR)................................370
Bus Status Register (IBSR) Contents ..................371
ICCR
Clock Control Register (ICCR) ..........................383
Clock Control Register (ICCR) Contents ............384
ICR
Interrupt Control Register (ICR) ..........................54
ID Register
ID Register x (x=0 to 15) (IDRx) .......................449
List of Message Buffers (ID Registers) ...............414
IDAR
Data Register (IDAR) .......................................382
IDE Register
IDE Register (IDER).........................................433
IDER
IDE Register (IDER).........................................433
IDRx
ID Register x (x=0 to 15) (IDRx) .......................449
ILM
Interrupt Level Mask Register (ILM)....................40
Indirect Addressing
Indirect Addressing...........................................558
Initial Values
Initial Values of 8/16-bit PPG Hardware .............232
Input Capture
Input Capture ...................................................193
Input Capture (2 Channels Per One Module)
..........................................................171
Input Capture Block Diagram ............................193
Input Capture Input Timing ...............................200
16-bit Input capture...........................................173
Sample of Input Capture Fetch timing ................199
Input Capture Data Register
Input Capture Data Register...............................194
Input Capture Edge Register
Input Capture Edge Register ..............................197
Input Data Register
Input Data Register (UIDR0) and Output Data
Register (UODR0) ...............................285
Input Level Select Register
Input Level Select Register
(MB90V390HA/HB Only) ...................152
Input-output Circuit
Input-output Circuits...........................................17
Instruction
Description of Instruction Presentation Items and
Symbols............................................. 570
Exception Due to Execution of an Undefined
Instruction.............................................74
Execution of an Undefined Instruction..................74
629
F2MC-16LX Instruction List ............................. 573
Instruction Types............................................. 549
Structure of Instruction Map............................. 587
Instructions
Interrupt Disable Instructions .............................. 46
Precautions for Use of "DIV A, Ri" and "DIVW A,
RWi" Instructions.................................. 47
Restrictions on Interrupt Disable Instructions and
Prefix Instructions ................................. 46
Use of the "DIV A, Ri" and "DIVW A, RWi"
Instructions without Precautions ............. 48
Instruction Presentation Items and Symbols
Description of Instruction Presentation Items and
Symbols ............................................ 570
Intelligent I/O Service
Intelligent I/O Service (EI2OS) Function and
Interrupts............................................202
Inter-CPU Connection
Inter-CPU Connection Method .......................... 344
Interface
Interrupt Function of the Extended Serial I/O
Interface ............................................. 407
Internal
Internal and External Clock ............................... 292
Internal Clock
Internal Clock Operation of
16-bit Reload Timer ............................ 208
Internal Clock Mode
Input Pin Functions of 16-bit Reload Timer
(in Internal Clock Mode)...................... 209
Internal Shift Clock Mode
Internal Shift Clock Mode ................................. 401
Interrupt
8/10-bit A/D Converter Interrupts ...................... 260
8/10-bit A/D Converter Interrupts and EI2OS
.......................................................... 260
8/16-bit PPG Interrupts ..................................... 231
Block Diagram of Delayed Interrupt .................... 76
Hardware Interrupt Operation.............................. 61
Hardware Interrupts...................................... 50, 60
Intelligent I/O Service (EI2OS) Function and
Interrupts............................................202
Interrupt Causes,Interrupt Vectors,and Interrupt
Control Registers................................ 619
Interrupt Flow .................................................... 58
Interrupt Function of the Extended Serial I/O
Interface ............................................. 407
Interval Interrupt Function ................................ 159
LIN-UART2/3 Interrupts .................................. 329
LIN-UART2/3 Interrupts and EI2OS .................. 331
Multiple Interrupts.............................................. 63
Occurrence and Release of Hardware Interrupt
............................................................ 62
Reception Interrupt Generation and Flag Set Timing
.......................................................... 333
630
Release of the Standby Mode by an Interrupt
......................................................... 136
Software Interrupts....................................... 50, 64
Structure of Hardware Interrupt........................... 60
Switching to a Standby Mode and Interrupt ........ 136
Transmission Interrupt Generation and Flag Set
Timing .............................................. 334
Transmission Interrupt Request Generation
Timing ............................................... 335
UART2/3 Interrupt and EI2OS .......................... 307
Interrupt Control Register
Interrupt Causes,Interrupt Vectors,and Interrupt
Control Registers ............................... 619
Interrupt Control Register (ICR).......................... 54
Interrupt Disable Instructions
Interrupt Disable Instructions .............................. 46
Restrictions on Interrupt Disable Instructions and
Prefix instructions ................................. 46
Interrupt Level Mask Register
Interrupt Level Mask Register (ILM) ................... 40
Interrupt Request Enable Register
Interrupt/DTP Enable Register (ENIR: Interrupt
Request Enable Register) ..................... 237
Interrupt Vector
Interrupt Causes,Interrupt Vectors,and Interrupt
Control Registers ............................... 619
Interrupt Vector ................................................. 52
List of Interrupt Vectors .................................. 617
List of MB90945 Interrupt Vectors...................... 64
Interrupt/DTP Enable Register
Interrupt/DTP Enable Register (ENIR: Interrupt
Request Enable Register) ..................... 237
Interrupt/DTP Flags
Interrupt/DTP Flags (EIRR: External Interrupt
Request Register)................................ 237
Interval Interrupt
Interval Interrupt Function ................................ 159
IOA
I/O Register Address Pointer (IOA) ..................... 69
ISCS
EI2OS Status Register (ISCS).............................. 70
ISD
Extended Intelligent I/O Service Descriptor (ISD)
........................................................... 68
ISMK
Seven Bit Slave Address Mask Register (ISMK)
......................................................... 380
Seven Bit Slave Address Mask Register (ISMK)
Contents............................................. 381
ITBA
Ten Bit Slave Address Register (ITBA) ............. 377
Ten Bit Slave Address Register (ITBA) Contents
......................................................... 377
ITMK
Ten Bit Address Mask Register (ITMK)............. 378
Ten Bit Address Mask Register (ITMK) Contents
.......................................................... 379
L
Last Event Indicator Register
Last Event Indicator Register (LEIR) ................. 427
Last Event Indicator Register (LEIR)
Contents............................................. 428
LEIR
Last Event Indicator Register (LEIR) ................. 427
Last Event Indicator Register (LEIR)
Contents............................................. 428
LIN-master-slave Communication
LIN-master-slave Communication Function ....... 359
LIN-UART
LIN-UART2/3 Interrupts .................................. 329
LIN-UART2/3 Interrupts and EI2OS.................. 331
Low-power Consumption Control Circuit
Block Diagram of the Low-power Consumption
Control Circuit.................................... 119
Low-power Consumption Mode
Setting Low-power Consumption Mode ............. 461
Low-power Consumption Mode Control Register
Notes on Accessing the Low-power Consumption
Mode Control Register (LPMCR) to Enter
the Standby Mode ............................... 137
Access to the Low-power Consumption Mode Control
Register.............................................. 123
Low-power Consumption Mode Control Register
(LPMCR) ........................................... 121
LPMCR
Low-power Consumption Mode Control Register
(LPMCR) ........................................... 121
Notes on Accessing the Low-power Consumption
Mode Control Register (LPMCR) to Enter
the Standby Mode ............................... 137
M
Machine Clock
Machine Clock .................................................. 91
Main Clock Mode
Main Clock Mode and PLL Clock Mode .............. 90
Masking
Slave Address Masking .................................... 387
Master Device
UART2/3 as Master Device .............................. 360
Master-slave Communication
Master-slave Communication Function .............. 356
MB90945
List of MB90945 Interrupt Vectors ...................... 64
MB90947A
Block Diagram of MB90F947(A)/
MB90947A .............................................7
Pin Assignment of MB90947A/MB90F947(A)/
MB90F949(A).......................................11
MB90F946A
Block Diagram of MB90F946A .............................6
Pin Assignment of MB90F946A ..........................10
MB90F947
Basic Configuration of MB90F947 Serial
Programming Connection .....................524
Block Diagram of MB90F947(A)/
MB90947A .............................................7
Pin Assignment of MB90947A/MB90F947(A)/
MB90F949(A).......................................11
MB90F949
Block Diagram of MB90F949(A)...........................8
Pin Assignment of MB90947A/MB90F947(A)/
MB90F949(A).......................................11
MB90V390
Block Diagram of MB90V390HA/HB ....................5
Input Level Select Register
(MB90V390HA/HB Only) ...................152
Pin Assignment of MB90V390HA/HB ...................9
MB90V390HA
Block Diagram of MB90V390HA/HB ....................5
Input Level Select Register
(MB90V390HA/HB Only) ...................152
Pin Assignment of MB90V390HA/HB ...................9
Memory Access Mode
Memory Access Modes .....................................140
Memory Space
Memory Space Map............................................28
Multi-byte Data Allocation in Memory Space........33
Outline of CPU Memory Space............................25
Message Buffer
Procedure for Reception by Message Buffer (x)
..........................................................464
Procedure for Transmission by Message Buffer (x)
..........................................................462
Setting Configuration of Multi-level Message Buffer
..........................................................466
Message Buffer Control Registers
Message Buffer Control Registers ......................420
Message Buffer Valid Register
Message Buffer Valid Register (BVALR) ...........432
Message Buffers
Caution for Disabling Message Buffers by BVAL Bits
..........................................................469
List of Message Buffers (DLC Registers and
Data Registers) ....................................417
List of Message Buffers (ID Registers) ...............414
Message Buffers.......................................420, 448
631
Microcontroller
Connection of an Oscillator or an External Clock t
o the Microcontroller ............................. 94
Minimum Connection
Example of Minimum Connection to the Flash
Microcomputer Programmer (Power
Supplied from the Programmer)............534
Example of Minimum Connection to the Flash
Microcomputer Programmer (User Power
Supply Used) ......................................532
Mode
Alternative Mode ............................................. 491
Bus Mode Setting Bits ......................................142
Clock Mode..................................................... 117
Clock Mode Transition ....................................... 90
CPU Intermittent Operation Mode ..................... 125
External Shift Clock Mode ................................ 401
Flag Set Timings for a Receive Operation
(in Mode 0, Mode1, or Mode3)............. 296
Flag Set Timings for a Receive Operation
(in Mode 2)......................................... 297
Flash Memory Mode ........................................ 491
Input Pin Functions of 16-bit Reload Timer
(in Internal Clock Mode)...................... 209
Internal Shift Clock Mode ................................. 401
Main Clock Mode and PLL Clock Mode .............. 90
Memory Access Modes..................................... 140
Mode Data....................................................... 142
Mode Fetch...................................................... 110
Mode Pins ............................................... 109, 141
Notes on the Transition to Standby Mode ........... 136
Operation in Asynchronous LIN Mode
(Operation Mode 3) ............................. 350
Operation in Asynchronous Mode...................... 345
Operation in Single Conversion Mode................ 261
Operation in Stop Conversion Mode .................. 262
Operation in Synchronous Mode
(Operation Mode 2) ............................. 347
Operation Modes of 8/16-bit PPG ...................... 227
Operation Status During Standby Mode.............. 126
Operation Status in Each Operating Mode .......... 135
Recommended Startup Sequence for Phase
Modulation Mode................................ 101
Release of Sleep Mode......................................128
Release of Stop Mode ....................................... 132
Release of the Standby Mode by an Interrupt
.......................................................... 136
Release of the Stop Mode.................................. 137
Release of Timebase Timer Mode...................... 130
Sample Program for Single Conversion Mode
Using EI2OS ....................................... 267
Sample Program for Stop Conversion Mode
Using EI2OS ....................................... 273
Signal Mode .................................................... 344
Standby Mode.................................................. 117
Switching to a Standby Mode and Interrupt ........ 136
632
Switching to Sleep Mode .................................. 127
Switching to the Clock mode ............................ 137
Switching to the Stop Mode .............................. 131
Switching to the Timebase Timer Mode ............. 129
UART0 Operation Modes................................. 288
UART2/3 Operation Modes .............................. 306
Sample Program for Continuous Conversion Mode
Using EI2OS....................................... 270
Sample Program for Single Conversion Mode
Using EI2OS....................................... 267
Mode Data
Status of Pins after Mode Data is Read............... 114
MSS
SCC, MSS and INT Bit Competition ................. 376
Multi-byte
Accessing Multi-byte Data.................................. 33
Multi-byte Data Allocation in Memory Space....... 33
Multi-level Message Buffer
Setting Configuration of Multi-level Message Buffer
......................................................... 466
Multiple Interrupt
Multiple Interrupts ............................................. 63
Multiplier
Selection of a PLL Clock Multiplier .................... 90
N
NCC
Flag Change Disable Prefix (NCC) ...................... 45
Notes
Notes on Operation ............................................ 76
O
Operand
24-bit Operand Specification............................... 30
Operating Mode
CPU Operating Modes and Current Consumption
......................................................... 116
Operation
Status Flag During Transmit and Receive Operation
......................................................... 299
Operation Enable Bit
Operation Enable Bit........................................ 344
Operation Mode
Operation in Asynchronous LIN Mode
(Operation Mode 3)............................. 350
Operation in Synchronous Mode
(Operation Mode 2)............................. 347
Operation Modes of 8/16-bit PPG...................... 227
UART0 Operation Modes................................. 288
UART2/3 Operation Modes .............................. 306
Operation State
Counter Operation State ................................... 212
Operation Status
Operation Status in Each Operating Mode .......... 135
Oscillating Clock Frequency
Oscillating Clock Frequency and Serial Clock Input
Frequency .......................................... 527
Oscillation Stabilization Wait
Oscillation Stabilization Wait and Reset State
.......................................................... 107
Oscillation Stabilization Wait Time
Oscillation Stabilization Wait Time ............. 93, 137
Reset Causes and Oscillation Stabilization Wait Times
.......................................................... 106
Oscillator
Connection of an Oscillator or an External Clock
to the Microcontroller............................ 94
Others
Others ............................................................... 65
Output Compare
Clearing the Counter upon a Match with Output
Compare Register 0 (4)........................ 180
Control Status Register of Output Compare (Lower)
.......................................................... 183
Control Status Register of Output Compare (Upper)
.......................................................... 185
Output Compare .............................................. 181
Output Compare (2 Channels Per One Module)
.......................................................... 170
Output Compare Block Diagram ....................... 181
Output Compare Register.................................. 182
Output Compare Timing ................................... 192
16-bit Output compare...................................... 172
Output Compare Register
Clearing the Counter upon a Match with Output
Compare Register 0 (4)........................ 180
Output Compare Register.................................. 182
Output Data Register
Input Data Register (UIDR0) and Output Data
Register (UODR0) .............................. 285
Output Waveform
Sample Output Waveform when CMOD0 and
CMOD1= "00B".................................. 187
Sample Output Waveform with Two Compare
Registers when CMOD0 and
CMOD1= "01B".................................. 188
Overall Control Registers
Overall Control Registers.................................. 420
List of Overall Control registers ........................ 412
Overflow
Clearing the Counter by an Overflow ................. 179
Overrun
Receive Overrun .............................................. 457
Overview
Overview .......................................................... 98
P
Package Dimensions
Package Dimensions ...........................................12
PACSR
Program Address Detection Control Status Register
(PACSR0)...........................................474
PADR
Program Address Detection Registers
(PADR0 to PADR2) ............................473
Parity
Parity Bit .........................................................294
PC
Program Counter (PC).........................................41
Phase Modulation Mode
Recommended Startup Sequence
for Phase Modulation Mode..................101
Pin Assignment
Pin Assignment of MB90947A/MB90F947(A)/
MB90F949(A).......................................11
Pin Assignment of MB90F946A ..........................10
Pin Assignment of MB90V390HA/HB ...................9
Pin Functions
Pin Functions .....................................................13
PLL
Configuration of the PLL and Special Configuration
Control Register (PSCCR)......................88
Selection of a PLL Clock Multiplier .....................90
PLL Clock
Selection of a PLL Clock Multiplier .....................90
PLL Clock Mode
Main Clock Mode and PLL Clock Mode...............90
Port Data Register
Port Data Register.............................................148
Reading the Port Data Register ..........................149
Port Direction Register
Data Direction Register .....................................150
Power Supplied
Example of Serial Programming Connection (Power
Supplied from the Programmer) ............530
PPG
8/16-bit PPG Interrupts .....................................231
8/16-bit PPG Output Operation ....................228229
8/16-bit PPG Registers ......................................219
Block Diagram of 8/16-bit PPG .........................215
Controlling Pin Output of 8/16-bit PPG Pulses
..........................................................230
Function of 8/16-bit PPG...................................214
Initial Values of 8/16-bit PPG Hardware .............232
Operation Modes of 8/16-bit PPG ......................227
Operations of 8/16-bit PPG................................227
PPG0/1 Clock Select Register (PPG01) ..............224
Relationship between 8/16-bit PPG Reload Value and
Pulse Width.........................................228
Selecting a Count Clock for 8/16-bit PPG ...........229
633
PPG0 Operation Mode Control Register
PPG0 Operation Mode Control Register (PPGC0)
.......................................................... 220
PPG0/1 Clock Select Register
PPG0/1 Clock Select Register (PPG01) .............. 224
PPG1 Operation Mode Control Register
PPG1 Operation Mode Control Register (PPGC1)
.......................................................... 222
PPGC
PPG0 Operation Mode Control Register (PPGC0)
.......................................................... 220
PPG1 Operation Mode Control Register (PPGC1)
.......................................................... 222
Prefix
Bank Select Prefix.............................................. 44
Common Register Bank Prefix (CMR) ................. 45
Consecutive Prefix Codes ................................... 46
Flag Change Disable Prefix (NCC) ...................... 45
Prefix Instructions
Restrictions on Interrupt Disable Instructions and
Prefix Instructions ................................. 46
Prescaler
Clock Prescaler Settings.................................... 385
Prescaler Settings ............................................. 431
Serial I/O Prescaler (CDCR).............................. 399
Priorities
Priorities of the STP, SLP, and TMD Bits........... 123
PRLH
Reload Register (PRLL/PRLH) .........................226
PRLL
Reload Register (PRLL/PRLH) .........................226
Processor Status
Processor Status (PS).......................................... 38
Product Overview
Product Overview................................................. 2
Program Address Detection Control Status Register
Program Address Detection Control Status Register
(PACSR0) .......................................... 474
Program Address Detection Registers
Program Address Detection Registers
(PADR0 to PADR2) ............................ 473
Program Patch Processing
Example of Program Patch Processing ............... 478
Programmable Restart
Programmable Restart....................................... 341
Programmer
Example of Serial Programming Connection (Power
Supplied from the Programmer)............530
Programming
Programming Flow Charts ................................ 389
Programming Example
Programming Example of 1M/2M/3M-bit
Flash Memory..................................... 519
634
Protect
Enable Sector Protect/Verify Sector Protect........ 615
Protection
A/D Conversion Data Protection Function.......... 264
PS
Processor Status (PS) ......................................... 38
PSCCR
Configuration of the PLL and Special Configuration
Control Register (PSCCR) ..................... 88
Pulse Width
Relationship between 8/16-bit PPG Reload Value and
Pulse Width........................................ 228
R
RAM
RAM Area ........................................................ 26
Rate and Data Register
Rate and Data Register (URD0) ........................ 286
Rate and Data Register (URD0) Contents........... 287
RCR
Reception Complete Register (RCR).................. 440
RDR
Reception Data Register (RDR2/3) .................... 322
Read Access
Data Read by Read Access ............................... 609
Reading
Reading the Port Data Register.......................... 149
Receive and Transmit Error Counters
Receive and Transmit Error Counters (RTEC)
......................................................... 429
Receive and Transmit Error Counters (RTEC)
Contents............................................. 429
Receive Operation
Flag Set Timings for a Receive Operation
(in Mode 0, Mode1, or Mode3) ............ 296
Flag Set Timings for a Receive Operation
(in Mode 2) ........................................ 297
Status Flag During Transmit and Receive Operation
......................................................... 299
Receive Overrun
Receive Overrun .............................................. 457
Receive Overrun Register
Receive Overrun Register (ROVRR) ................. 442
Received Message
Storing Received Message ................................ 456
Reception
Completing Reception ...................................... 458
Procedure for Reception by Message Buffer (x)
......................................................... 464
Processing for Reception of Data Frame and
Remote Frame ................................... 457
Reception Flowchart of the CAN Controller
......................................................... 459
Reception and Transmission Data Registers
Bit Configuration of Reception and Transmission Data
Registers (RDR2/3 and TDR2/3) .......... 322
Reception Complete Register
Reception Complete Register (RCR).................. 440
Reception Data Register
Reception Data Register (RDR2/3) .................... 322
Reception Interrupt
Reception Interrupt Generation and Flag Set Timing
.......................................................... 333
Reception Interrupt Enable Register
Reception Interrupt Enable Register (RIER)
.......................................................... 443
Recommended Setting
Recommended Setting ...................................... 144
Register Bank
Register Bank .................................................... 42
Register Bank Pointer
Register Bank Pointer (RP) ................................. 39
Reload Register
Register Layout of 16-bit Timer Register (TMR0)/
16-bit Reload Register (TMRLR0)........ 207
Reload Register (PRLL/PRLH) ......................... 226
Reload Timer
16-bit Reload Timer Register ............................ 203
Block Diagram of 16-bit Reload Timer .............. 202
Input Pin Functions of 16-bit Reload Timer
(in Internal Clock Mode) ..................... 209
Internal Clock Operation of
16-bit Reload Timer ............................ 208
Outline of 16-bit Reload Timer
(with Event Count Function) ................ 202
Output Pin Functions of 16-bit Reload Timer
.......................................................... 211
Underflow Operation of 16-bit Reload Timer
.......................................................... 210
Reload Value
Relationship between 8/16-bit PPG Reload Value and
Pulse Width ........................................ 228
Remote Frame
Processing for Reception of Data Frame and
Remote Frame .................................... 457
Remote Frame Receiving Wait Register
Remote Frame Receiving Wait Register (RFWTR)
.......................................................... 436
Remote Request Receiving Register
Remote Request Receiving Register (RRTRR)
.......................................................... 441
Request Level Setting Register
Request Level Setting Register
(ELVR: External Level Register).......... 238
Reset
Block Diagrams of the External Reset Pin .......... 108
Causes of a Reset ............................................. 104
Correspondence between Reset Cause Bits and
Reset Causes .......................................112
Notes about Reset Cause Bits.............................112
Oscillation Stabilization Wait and Reset State
..........................................................107
Overview of Reset Operation .............................109
Reset Cause Bits...............................................111
Reset Causes and Oscillation Stabilization Wait Times
..........................................................106
Setting the Flash Memory to the Read/Reset State
..........................................................508
Status of Pins During a Reset .............................114
Reset Cause Bits
Correspondence between Reset Cause Bits and
Reset Causes .......................................112
Reset Cause Bits...............................................111
Notes about Reset Cause bits .............................112
Reset Vector
Reset Vector Address in Flash Memory ..............518
Restart
Programmable Restart.......................................341
Restarting
Restarting Erasing of Flash Memory Sectors
..........................................................515
RFWTR
Remote Frame Receiving Wait Register (RFWTR)
..........................................................436
RIER
Reception Interrupt Enable Register (RIER)........443
ROM
ROM Area .........................................................26
ROM Mirroring Module
Block Diagram of ROM Mirroring Module.........482
ROM Mirroring Register
ROM Mirroring Register (ROMM) ....................483
ROMM
ROM Mirroring Register (ROMM) ....................483
ROVRR
Receive Overrun Register (ROVRR) ..................442
RP
Register Bank Pointer (RP)..................................39
RRTRR
Remote Request Receiving Register (RRTRR)
..........................................................441
RST
RST and RY/BY Timing ...................................614
RTEC
Receive and Transmit Error Counters (RTEC)
..........................................................429
Receive and Transmit Error Counters (RTEC)
Contents .............................................429
RY/BY
RST and RY/BY Timing ...................................614
635
RY/BY Timing During Writing/Erasing ............. 614
S
Sample Output Waveform
Sample Output Waveform when CMOD0 and
CMOD1= "00B".................................. 187
Sample Output Waveform when CMOD0 and
CMOD1= "10B".................................. 190
Sample Output Waveform when CMOD0 and
CMOD1= "11B".................................. 191
Sample Output Waveform with Two Compare
Registers when CMOD0 and
CMOD1= "01B".................................. 188
Sample Program
Sample Program for Continuous Conversion Mode
Using EI2OS ....................................... 270
Sample Program for Single Conversion Mode
Using EI2OS ....................................... 267
Sample Program for Stop Conversion Mode
Using EI2OS ....................................... 273
SCC
SCC, MSS and INT Bit Competition.................. 376
SCR
Serial Control Register (SCR2/3) ....................... 316
SDR
Serial Shift Data Register (SDR)........................ 398
Sector
Sector Configuration of the 1M-bit Flash Memory
.......................................................... 488
Sector Configuration of the 2M-bit Flash Memory
.................................................. 489, 490
Sector Erase
Chip Erase/Sector Erase Command Sequence
.......................................................... 612
Sector Erase Timer Flag
Sector Erase Timer Flag (DQ3) .........................503
Sector Protect
Enable Sector Protect/Verify Sector Protect ........ 615
Temporary Sector Protect Cancellation............... 616
Sectors
Erasing Optional Data (Erasing Sectors)
in the Flash Memory............................ 512
Erasing Sectors in the Flash Memory ................. 512
Restarting Erasing of Flash Memory Sectors....... 515
Suspending Erasing of Flash Memory Sectors
.......................................................... 514
Serial Clock Input Frequency
Oscillating Clock Frequency and Serial Clock Input
Frequency........................................... 527
Serial Control Register
Serial Control Register (SCR2/3) ....................... 316
Serial I/O
Serial I/O Block Diagram.................................. 392
Serial I/O Operation ................................. 400, 402
636
Serial I/O Prescaler (CDCR) ............................. 399
Serial I/O Registers .......................................... 393
Serial I/O Prescaler
Serial I/O Prescaler (CDCR) ............................. 399
Serial Mode Control Register
Serial Mode Control Register (UMC0)............... 281
Serial Mode Control Register (UMC0) Contents
......................................................... 282
Serial Mode Control Status Register
Bit Functions of Serial Mode Control Status Register
(SMCS) ............................................. 396
Lower Byte of Serial Mode Control Status Register
(SMCS) ............................................. 395
Upper Byte of Serial Mode Control Status Register
(SMCS) ............................................. 394
Serial Mode Register
Serial Mode Register (SMR2/3) ........................ 318
Serial Programming Connection
Basic Configuration of MB90F947 Serial
Programming Connection .................... 524
Example of Serial Programming Connection (Power
Supplied from the Programmer) ........... 530
Example of Serial Programming Connection
(User Power Supply Used)................... 528
Serial Shift Data Register
Serial Shift Data Register (SDR) ....................... 398
Serial Status Register
Serial Status Register (SSR2/3) ......................... 320
Setting Bit Timing
Setting Bit Timing ........................................... 460
Setting ID
Setting ID........................................................ 460
Seven Bit Slave Address Mask Register
Seven Bit Slave Address Mask Register (ISMK)
......................................................... 380
Seven Bit Slave Address Mask Register (ISMK)
Contents............................................. 381
Seven Bit Slave Address Register
Seven Bit Slave Address Register ...................... 380
Seven Bit Slave Address Register Contents ........ 380
Shift Clock
External Shift Clock Mode................................ 401
Internal Shift Clock Mode................................. 401
Shift Clock Selection........................................ 397
Shift Operation
Shift Operation Start/Stop Timing ..................... 404
Signal Mode
Signal Mode .................................................... 344
Single Conversion Mode
Operation in Single Conversion Mode ............... 261
Sample Program for Single Conversion Mode
Using EI2OS....................................... 267
Slave
Addressing Slaves............................................ 387
Slave Address
Slave Address Detection ................................... 386
Slave Address Masking .................................... 387
Slave Device
UART2/3 as Slave Device ................................ 361
Sleep Mode
Release of Sleep Mode ..................................... 128
Switching to Sleep Mode .................................. 127
SLP
Priorities of the STP, SLP, and TMD Bits .......... 123
SMCS
Bit Functions of Serial Mode Control Status Register
(SMCS).............................................. 396
Lower Byte of Serial Mode Control Status Register
(SMCS).............................................. 395
Upper Byte of Serial Mode Control Status Register
(SMCS).............................................. 394
SMR
Serial Mode Register (SMR2/3) ........................ 318
Software Interrupt
Software Interrupt Operation............................... 64
Software Interrupts....................................... 50, 64
Structure of Software interrupts........................... 64
Special Registers
Special Registers................................................ 34
SSP
User Stack Pointer (USP) and System Stack Pointer
(SSP) ................................................... 37
SSR
Serial Status Register (SSR2/3) ......................... 320
Standby Mode
Release of the Standby Mode by an Interrupt
.......................................................... 136
Standby Mode ................................................. 117
Switching to a Standby Mode and Interrupt ........ 136
Notes on the Transition to Standby mode ........... 136
Operation Status During Standby mode.............. 126
Start Conditions
Start Conditions ............................................... 386
State transition diagram of the Watch-dog Timer
................................................................... 165
Status Change Diagram
Status Change Diagram .................................... 134
Status Flag
Status Flag During Transmit and Receive Operation
.......................................................... 299
Status Register
Status Register (USR0)..................................... 283
Status Register (USR0) Contents ....................... 284
Stop Conditions
Stop Conditions ............................................... 386
Stop Conversion Mode
Operation in Stop Conversion Mode .................. 262
Sample Program for Stop Conversion Mode
Using EI2OS .......................................273
Stop Mode
Release of Stop Mode .......................................132
Release of the Stop Mode ..................................137
Switching to the Stop Mode...............................131
STP
Priorities of the STP, SLP, and TMD Bits ...........123
Structure
Structure ............................................................67
Structure of Instruction Map ............................. 587
Switching ..............................................................137
Synchronization
Synchronization Methods ..................................344
Synchronization Methods
Synchronization Methods ..................................344
Synchronous
CLK Synchronous Baud Rate ............................289
Operation in Synchronous Mode (Operation Mode 2)
..........................................................347
Synchronous Mode
Operation in Synchronous Mode (Operation Mode 2)
..........................................................347
System Stack Pointer
User Stack Pointer (USP) and System Stack Pointer
(SSP)....................................................37
T
TBTC
Timebase Timer Control Register (TBTC) ..........157
TCANR
Transmission Cancel Register (TCANR) ............437
TCR
Transmission Complete Register (TCR)..............438
TDR
Bit Configuration of Reception and Transmission Data
Registers (RDR2/3 and TDR2/3)...........322
Transmission Data Register (TDR2/3) ................323
Ten Bit Address Mask Register
Ten Bit Address Mask Register (ITMK) .............378
Ten Bit Address Mask Register (ITMK) Contents
..........................................................379
Ten Bit Slave Address Register
Ten Bit Slave Address Register (ITBA) ..............377
Ten Bit Slave Address Register (ITBA) Contents
..........................................................377
TIER
Transmission Interrupt Enable Register (TIER)
..........................................................439
Timebase Counter
Timebase Counter.............................................159
Timebase Timer
Block Diagram of Timebase Timer.....................156
637
Outline of Timebase Timer................................ 156
Timebase Timer Control Register
Timebase Timer Control Register (TBTC).......... 157
Timebase Timer Mode
Release of Timebase Timer Mode...................... 130
Switching to the Timebase Timer Mode ............. 129
Timer Control Register
Register Contents of Timer Control Register
(TMCSR0) ......................................... 204
Timer Control Register (TMCSR0) .................... 204
Timer Register
Register Layout of 16-bit Timer Register (TMR0)/
16-bit Reload Register (TMRLR0)
.......................................................... 207
Timing Limit Exceeded Flag
Timing Limit Exceeded Flag (DQ5)...................502
TMCSR
Register Contents of Timer Control Register
(TMCSR0) ......................................... 204
Register Layout of Timer Control Register (TMCSR0)
.......................................................... 204
TMD
Priorities of the STP, SLP, and TMD Bits........... 123
TMR
Register Layout of 16-bit Timer Register (TMR0)/
16-bit Reload Register (TMRLR0)........ 207
TMRLR
16-bit Timer Register (TMR0)/
16-bit Reload Register (TMRLR0)........ 207
Toggle Bit
Toggle Bit ....................................................... 613
Toggle Bit Flag
Toggle Bit Flag (DQ6)......................................501
Toggle Bit-2 Flag
Toggle Bit-2 Flag (DQ2)................................... 505
Transfer
Transfer Data Format........................................ 293
Transmission
Canceling a Transmission Request
from the CAN Controller ..................... 454
Completing Transmission of the
CAN Controller................................... 455
Procedure for Transmission by Message Buffer (x)
.......................................................... 462
Starting Transmission of the CAN Controller
.......................................................... 454
Transmission Flowchart of the CAN Controller
.......................................................... 455
Transmission Cancel Register
Transmission Cancel Register (TCANR) ............437
Transmission Complete Register
Transmission Complete Register (TCR) ............. 438
Transmission Data Register
Transmission Data Register (TDR2/3)................ 323
638
Transmission Interrupt
Transmission Interrupt Generation and
Flag Set Timing .................................. 334
Transmission Interrupt Request Generation Timing
......................................................... 335
Transmission Interrupt Enable Register
Transmission Interrupt Enable Register (TIER)
......................................................... 439
Transmission Request Register
Transmission Request Register (TREQR)........... 434
Transmission RTR Register
Transmission RTR Register (TRTRR) ............... 435
Transmit
Status Flag During Transmit and Receive Operation
......................................................... 299
Transmit Operation
Flag Set Timings for a Transmit Operation ......... 298
TREQR
Transmission Request Register (TREQR)........... 434
TRTRR
Transmission RTR Register (TRTRR) ............... 435
U
UART
Block Diagram of UART2/3 ............................. 308
Feature of UART0 ........................................... 278
Notes on Using UART2/3................................. 362
Operation of UART2/3..................................... 343
UART0 Block Diagram.................................... 279
UART0 Operation Modes................................. 288
UART0 Registers............................................. 280
UART2/3 as Master Device .............................. 360
UART2/3 as Slave Device ................................ 361
UART2/3 Baud Rate Selection.......................... 336
UART2/3 Direct Pin Access ............................. 353
UART2/3 EI2OS Functions............................... 332
UART2/3 Functions ......................................... 304
UART2/3 Interrupt and EI2OS .......................... 307
UART2/3 Operation Modes .............................. 306
UART2/3 Pins ................................................. 313
UART2/3 Registers.......................................... 315
UMC
Serial Mode Control Register (UMC0)............... 281
Serial Mode Control Register (UMC0) Contents
......................................................... 282
Undefined Instruction
Exception Due to Execution
of an Undefined Instruction.................... 74
Execution of an Undefined Instruction ................. 74
Underflow Operation
Underflow Operation of 16-bit Reload Timer
......................................................... 210
UODR
Input Data Register (UIDR0) and Output Data
Register (UODR0) .............................. 285
URD
Rate and Data Register (URD0)......................... 286
Rate and Data Register (URD0) Contents ........... 287
User Power Supply
Example of Serial Programming Connection
(User Power Supply Used) ................... 528
User Stack Pointer
User Stack Pointer (USP) and System Stack Pointer
(SSP) ................................................... 37
USP
User Stack Pointer (USP) and System Stack Pointer
(SSP) ................................................... 37
USR
Status Register (USR0)..................................... 283
Status Register (USR0) Contents ....................... 284
W
Watch-dog
Watch-dog Stop ............................................... 166
Watch-dog Counter
Watch-dog Counter...........................................166
Watch-dog deactivation ........................................166
Watch-dog Timer
Watch-dog Timer Block Diagram ......................162
Watch-dog timer behavior at reset .......................167
Watch-dog timer behavior in stop mode etc. ........166
Watch-dog Timer Control Register
Watch-dog Timer Control Register (WDTC)
..........................................................163
WDTC
Watch-dog Timer Control Register (WDTC)
..........................................................163
WE Control
Write, Data Polling, Read (WE Control) .............610
Write
Detailed Explanation of Flash Memory
Write/Erase .........................................507
Writing
Writing Data to the Flash Memory .....................509
Writing to the Flash Memory .............................509
Writing to/Erasing Flash Memory ......................486
639
640
CM44-10134-2E
FUJITSU MICROELECTRONICS • CONTROLLER MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90945 Series
HARDWARE MANUAL
July 2008 the second edition
Published
FUJITSU MICROELECTRONICS LIMITED
Edited
Business & Media Promotion Dept.